From 73d38eb54b1b735c994537b3b403cc92a8a1c09c Mon Sep 17 00:00:00 2001 From: HS Date: Fri, 16 Dec 2022 02:47:45 -0800 Subject: [PATCH 1/2] Issue chipsalliance/UHDM#831: Fix compile issues on MinGW * Rename "interface" to "interface_inst" to avoid conflicing with system defined class with the same name. * Rename "module" to "module_inst" since the latter is now a C++ reserved word as of C++ 20. --- include/Surelog/Design/Netlist.h | 6 +- include/Surelog/DesignCompile/CompileHelper.h | 2 +- include/Surelog/DesignCompile/CompileModule.h | 8 +- .../DesignCompile/NetlistElaboration.h | 2 +- include/Surelog/DesignCompile/UhdmWriter.h | 8 +- src/Common/PlatformFileSystem_test.cpp | 2 +- src/DesignCompile/CompileExpression.cpp | 6 +- src/DesignCompile/CompileHelper.cpp | 4 +- src/DesignCompile/CompileStmt.cpp | 4 +- src/DesignCompile/Elaboration_test.cpp | 2 +- src/DesignCompile/EvalFunc.cpp | 2 +- src/DesignCompile/NetlistElaboration.cpp | 26 ++-- src/DesignCompile/UhdmWriter.cpp | 141 +++++++++--------- src/hellodesign.cpp | 11 +- src/hellouhdm.cpp | 8 +- src/roundtrip.cpp | 49 +++--- third_party/UHDM | 2 +- 17 files changed, 144 insertions(+), 139 deletions(-) diff --git a/include/Surelog/Design/Netlist.h b/include/Surelog/Design/Netlist.h index f56bdf3b26..875af93fe3 100644 --- a/include/Surelog/Design/Netlist.h +++ b/include/Surelog/Design/Netlist.h @@ -47,7 +47,7 @@ class Netlist { InstanceMap; typedef std::map> SymbolTable; - std::vector* interfaces() { return m_interfaces; } + std::vector* interfaces() { return m_interfaces; } std::vector* interface_arrays() { return m_interface_arrays; } @@ -66,7 +66,7 @@ class Netlist { std::vector* process_stmts() { return m_process_stmts; } std::vector* param_assigns() { return m_param_assigns; } - void interfaces(std::vector* interfaces) { + void interfaces(std::vector* interfaces) { m_interfaces = interfaces; } void interface_arrays(std::vector* interfaces) { @@ -111,7 +111,7 @@ class Netlist { ModuleInstance* const m_parent; // members of the netlist - std::vector* m_interfaces = nullptr; + std::vector* m_interfaces = nullptr; std::vector* m_interface_arrays = nullptr; std::vector* m_nets = nullptr; std::vector* m_ports = nullptr; diff --git a/include/Surelog/DesignCompile/CompileHelper.h b/include/Surelog/DesignCompile/CompileHelper.h index aadcddfdbe..d55bc04586 100644 --- a/include/Surelog/DesignCompile/CompileHelper.h +++ b/include/Surelog/DesignCompile/CompileHelper.h @@ -563,7 +563,7 @@ class CompileHelper final { ErrorContainer* m_errors = nullptr; SymbolTable* m_symbols = nullptr; ExprBuilder m_exprBuilder; - UHDM::module* m_exprEvalPlaceHolder = nullptr; + UHDM::module_inst* m_exprEvalPlaceHolder = nullptr; // Caches UHDM::int_typespec* buildIntTypespec(CompileDesign* compileDesign, PathId fileId, std::string_view name, diff --git a/include/Surelog/DesignCompile/CompileModule.h b/include/Surelog/DesignCompile/CompileModule.h index 2e2f9ffb40..9222ea9acf 100644 --- a/include/Surelog/DesignCompile/CompileModule.h +++ b/include/Surelog/DesignCompile/CompileModule.h @@ -37,12 +37,12 @@ class SymbolTable; class ValuedComponentI; struct FunctorCompileModule { - FunctorCompileModule(CompileDesign* compiler, ModuleDefinition* module, + FunctorCompileModule(CompileDesign* compiler, ModuleDefinition* mdl, Design* design, SymbolTable* symbols, ErrorContainer* errors, ValuedComponentI* instance = nullptr) : m_compileDesign(compiler), - m_module(module), + m_module(mdl), m_design(design), m_symbols(symbols), m_errors(errors), @@ -60,11 +60,11 @@ struct FunctorCompileModule { class CompileModule final { public: - CompileModule(CompileDesign* compiler, ModuleDefinition* module, + CompileModule(CompileDesign* compiler, ModuleDefinition* mdl, Design* design, SymbolTable* symbols, ErrorContainer* errors, ValuedComponentI* instance = nullptr) : m_compileDesign(compiler), - m_module(module), + m_module(mdl), m_design(design), m_symbols(symbols), m_errors(errors), diff --git a/include/Surelog/DesignCompile/NetlistElaboration.h b/include/Surelog/DesignCompile/NetlistElaboration.h index 3649f5c008..cf67a91ea5 100644 --- a/include/Surelog/DesignCompile/NetlistElaboration.h +++ b/include/Surelog/DesignCompile/NetlistElaboration.h @@ -59,7 +59,7 @@ class NetlistElaboration : public TestbenchElaboration { bool elab_parameters_(ModuleInstance* instance, bool port_params); bool elab_interfaces_(ModuleInstance* instance); bool elab_generates_(ModuleInstance* instance); - UHDM::interface* elab_interface_( + UHDM::interface_inst* elab_interface_( ModuleInstance* instance, ModuleInstance* interf_instance, std::string_view instName, std::string_view defName, ModuleDefinition* mod, PathId fileId, int lineNb, diff --git a/include/Surelog/DesignCompile/UhdmWriter.h b/include/Surelog/DesignCompile/UhdmWriter.h index 6281600d37..52881adeb1 100644 --- a/include/Surelog/DesignCompile/UhdmWriter.h +++ b/include/Surelog/DesignCompile/UhdmWriter.h @@ -75,21 +75,21 @@ class UhdmWriter final { ModPortMap& modPortMap, SignalBaseClassMap& signalBaseMap, SignalMap& signalMap, ModuleInstance* instance = nullptr, ModuleDefinition* mod = nullptr); - void writeModule(ModuleDefinition* mod, UHDM::module* m, UHDM::Serializer& s, + void writeModule(ModuleDefinition* mod, UHDM::module_inst* m, UHDM::Serializer& s, ComponentMap& componentMap, ModPortMap& modPortMap, ModuleInstance* instance = nullptr); - void writeInterface(ModuleDefinition* mod, UHDM::interface* m, + void writeInterface(ModuleDefinition* mod, UHDM::interface_inst* m, UHDM::Serializer& s, ComponentMap& componentMap, ModPortMap& modPortMap, ModuleInstance* instance = nullptr); bool writeElabInterface(UHDM::Serializer& s, ModuleInstance* instance, - UHDM::interface* m, ExprBuilder& exprBuilder); + UHDM::interface_inst* m, ExprBuilder& exprBuilder); void writeInstance(ModuleDefinition* mod, ModuleInstance* instance, UHDM::any* m, CompileDesign* compileDesign, ComponentMap& componentMap, ModPortMap& modPortMap, InstanceMap& instanceMap, ExprBuilder& exprBuilder); bool writeElabModule(UHDM::Serializer& s, ModuleInstance* instance, - UHDM::module* m, ExprBuilder& exprBuilder); + UHDM::module_inst* m, ExprBuilder& exprBuilder); bool writeElabProgram(UHDM::Serializer& s, ModuleInstance* instance, UHDM::program* m); bool writeElabGenScope(UHDM::Serializer& s, ModuleInstance* instance, diff --git a/src/Common/PlatformFileSystem_test.cpp b/src/Common/PlatformFileSystem_test.cpp index bcd82910c1..be572350d4 100644 --- a/src/Common/PlatformFileSystem_test.cpp +++ b/src/Common/PlatformFileSystem_test.cpp @@ -36,7 +36,7 @@ // UHDM #include #include -#include +#include #include #include #include diff --git a/src/DesignCompile/CompileExpression.cpp b/src/DesignCompile/CompileExpression.cpp index af49dd5f63..21723712d9 100644 --- a/src/DesignCompile/CompileExpression.cpp +++ b/src/DesignCompile/CompileExpression.cpp @@ -746,7 +746,7 @@ any *CompileHelper::decodeHierPath(hier_path *path, bool &invalidValue, eval.setGetValueFunctor(getValueFunctor); eval.setGetTaskFuncFunctor(getTaskFuncFunctor); if (m_exprEvalPlaceHolder == nullptr) { - m_exprEvalPlaceHolder = compileDesign->getSerializer().MakeModule(); + m_exprEvalPlaceHolder = compileDesign->getSerializer().MakeModule_inst(); m_exprEvalPlaceHolder->Param_assigns( compileDesign->getSerializer().MakeParam_assignVec()); } else { @@ -800,7 +800,7 @@ expr *CompileHelper::reduceExpr(any *result, bool &invalidValue, eval.setGetValueFunctor(getValueFunctor); eval.setGetTaskFuncFunctor(getTaskFuncFunctor); if (m_exprEvalPlaceHolder == nullptr) { - m_exprEvalPlaceHolder = compileDesign->getSerializer().MakeModule(); + m_exprEvalPlaceHolder = compileDesign->getSerializer().MakeModule_inst(); m_exprEvalPlaceHolder->Param_assigns( compileDesign->getSerializer().MakeParam_assignVec()); } else { @@ -3817,7 +3817,7 @@ uint64_t CompileHelper::Bits(const UHDM::any *typespec, bool &invalidValue, eval.setGetValueFunctor(getValueFunctor); eval.setGetTaskFuncFunctor(getTaskFuncFunctor); if (m_exprEvalPlaceHolder == nullptr) { - m_exprEvalPlaceHolder = compileDesign->getSerializer().MakeModule(); + m_exprEvalPlaceHolder = compileDesign->getSerializer().MakeModule_inst(); m_exprEvalPlaceHolder->Param_assigns( compileDesign->getSerializer().MakeParam_assignVec()); } else { diff --git a/src/DesignCompile/CompileHelper.cpp b/src/DesignCompile/CompileHelper.cpp index 3523845c00..3d1cb27c8e 100644 --- a/src/DesignCompile/CompileHelper.cpp +++ b/src/DesignCompile/CompileHelper.cpp @@ -3208,7 +3208,7 @@ UHDM::any* CompileHelper::compileTfCall(DesignComponent* component, VectorOfany* arguments = compileTfCallArguments(component, fC, argListNode, compileDesign, call, nullptr, false, false); - module* modTmp = s.MakeModule(); + module_inst* modTmp = s.MakeModule_inst(); modTmp->VpiName("tmp"); const VectorOfseq_formal_decl* decls = stmt->Ios(); VectorOfparam_assign* passigns = s.MakeParam_assignVec(); @@ -3237,7 +3237,7 @@ UHDM::any* CompileHelper::compileTfCall(DesignComponent* component, ElaboratorListener* listener = new ElaboratorListener(&s, false); vpiHandle defModule = NewVpiHandle(modTmp); - listener->listenModule(defModule); + listener->listenModule_inst(defModule); vpi_free_object(defModule); delete listener; return (any*)cts->Rhs(); diff --git a/src/DesignCompile/CompileStmt.cpp b/src/DesignCompile/CompileStmt.cpp index 6aa8c2685f..ec0515802f 100644 --- a/src/DesignCompile/CompileStmt.cpp +++ b/src/DesignCompile/CompileStmt.cpp @@ -2824,8 +2824,8 @@ UHDM::any* CompileHelper::bindVariable(DesignComponent* component, } break; } - case uhdmmodule: { - module* mod = (module*)scope; + case uhdmmodule_inst: { + module_inst* mod = (module_inst*)scope; if (mod->Variables()) { for (auto var : *mod->Variables()) { if (var->VpiName() == name) return var; diff --git a/src/DesignCompile/Elaboration_test.cpp b/src/DesignCompile/Elaboration_test.cpp index 3be67ab0cd..22f8934e7d 100644 --- a/src/DesignCompile/Elaboration_test.cpp +++ b/src/DesignCompile/Elaboration_test.cpp @@ -37,7 +37,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/src/DesignCompile/EvalFunc.cpp b/src/DesignCompile/EvalFunc.cpp index b131d9d43d..0b2611c325 100644 --- a/src/DesignCompile/EvalFunc.cpp +++ b/src/DesignCompile/EvalFunc.cpp @@ -68,7 +68,7 @@ expr* CompileHelper::EvalFunc(UHDM::function* func, std::vector* args, eval.setGetValueFunctor(getValueFunctor); eval.setGetTaskFuncFunctor(getTaskFuncFunctor); if (m_exprEvalPlaceHolder == nullptr) { - m_exprEvalPlaceHolder = compileDesign->getSerializer().MakeModule(); + m_exprEvalPlaceHolder = compileDesign->getSerializer().MakeModule_inst(); m_exprEvalPlaceHolder->Param_assigns( compileDesign->getSerializer().MakeParam_assignVec()); } else { diff --git a/src/DesignCompile/NetlistElaboration.cpp b/src/DesignCompile/NetlistElaboration.cpp index 464a012bb4..5e55308e46 100644 --- a/src/DesignCompile/NetlistElaboration.cpp +++ b/src/DesignCompile/NetlistElaboration.cpp @@ -1248,7 +1248,7 @@ bool NetlistElaboration::high_conn_(ModuleInstance* instance) { ref->Actual_group(mp); p->Low_conn(ref); } - } else if (net && (net->UhdmType() == uhdminterface) && + } else if (net && (net->UhdmType() == uhdminterface_inst) && (lowconn_is_nettype)) { BaseClass* sm = nullptr; if (orderedConnection) { @@ -1386,7 +1386,7 @@ bool NetlistElaboration::high_conn_(ModuleInstance* instance) { return true; } -interface* NetlistElaboration::elab_interface_( +interface_inst* NetlistElaboration::elab_interface_( ModuleInstance* instance, ModuleInstance* interf_instance, std::string_view instName, std::string_view defName, ModuleDefinition* mod, PathId fileId, int lineNb, interface_array* interf_array, @@ -1398,12 +1398,12 @@ interface* NetlistElaboration::elab_interface_( instance->setNetlist(netlist); } Serializer& s = m_compileDesign->getSerializer(); - VectorOfinterface* subInterfaces = netlist->interfaces(); + VectorOfinterface_inst* subInterfaces = netlist->interfaces(); if (subInterfaces == nullptr) { - subInterfaces = s.MakeInterfaceVec(); + subInterfaces = s.MakeInterface_instVec(); netlist->interfaces(subInterfaces); } - interface* sm = s.MakeInterface(); + interface_inst* sm = s.MakeInterface_inst(); sm->VpiName(instName); sm->VpiDefName(defName); // sm->VpiFullName(??); @@ -1434,7 +1434,7 @@ interface* NetlistElaboration::elab_interface_( StrCat(instName, ".", orig_modport.first); if (!modPortName.empty() && (modportfullname != modPortName)) continue; modport* dest_modport = s.MakeModport(); - dest_modport->Interface(sm); + dest_modport->Interface_inst(sm); dest_modport->VpiParent(sm); const FileContent* orig_fC = orig_modport.second.getFileContent(); const NodeId orig_nodeId = orig_modport.second.getNodeId(); @@ -1457,7 +1457,7 @@ interface* NetlistElaboration::elab_interface_( if (net == nullptr) { net = bind_net_(instance, sigName); } - if (net && (net->UhdmType() == uhdminterface)) { + if (net && (net->UhdmType() == uhdminterface_inst)) { ref_obj* n = s.MakeRef_obj(); n->VpiName(sigName); n->VpiFullName(StrCat(instance->getFullPathName(), ".", sigName)); @@ -2328,7 +2328,7 @@ bool NetlistElaboration::elab_ports_nets_( ref->Actual_group(array_int); } - interface* sm = elab_interface_( + interface_inst* sm = elab_interface_( instance, interfaceInstance, signame, orig_interf->getName(), orig_interf, instance->getFileId(), instance->getLineNb(), array_int, ""); @@ -2339,7 +2339,7 @@ bool NetlistElaboration::elab_ports_nets_( auto interfs = netlist->interfaces(); if (interfs == nullptr) { - netlist->interfaces(s.MakeInterfaceVec()); + netlist->interfaces(s.MakeInterface_instVec()); interfs = netlist->interfaces(); } interfs->push_back(sm); @@ -2537,20 +2537,20 @@ any* NetlistElaboration::bind_net_(ModuleInstance* instance, BaseClass* baseclass = (*itr).second; port* conn = any_cast(baseclass); ref_obj* ref1 = nullptr; - const interface* interf = nullptr; + const interface_inst* interf = nullptr; if (conn) { ref1 = any_cast((BaseClass*)conn->Low_conn()); } if (ref1) { - interf = any_cast((BaseClass*)ref1->Actual_group()); + interf = any_cast((BaseClass*)ref1->Actual_group()); } if (interf == nullptr) { - interf = any_cast(baseclass); + interf = any_cast(baseclass); } if ((interf == nullptr) && ref1) { modport* mport = any_cast((BaseClass*)ref1->Actual_group()); if (mport) { - interf = mport->Interface(); + interf = mport->Interface_inst(); } } if (interf) { diff --git a/src/DesignCompile/UhdmWriter.cpp b/src/DesignCompile/UhdmWriter.cpp index ceea873fdf..1f862bf7eb 100644 --- a/src/DesignCompile/UhdmWriter.cpp +++ b/src/DesignCompile/UhdmWriter.cpp @@ -1095,7 +1095,8 @@ void UhdmWriter::writePackage(Package* pack, package* p, Serializer& s, lateBinding(s, pack, p, componentMap); } -void UhdmWriter::writeModule(ModuleDefinition* mod, module* m, Serializer& s, +void UhdmWriter::writeModule(ModuleDefinition* mod, module_inst* m, + Serializer& s, UhdmWriter::ComponentMap& componentMap, UhdmWriter::ModPortMap& modPortMap, ModuleInstance* instance) { @@ -1266,7 +1267,7 @@ void UhdmWriter::writeModule(ModuleDefinition* mod, module* m, Serializer& s, } } -void UhdmWriter::writeInterface(ModuleDefinition* mod, interface* m, +void UhdmWriter::writeInterface(ModuleDefinition* mod, interface_inst* m, Serializer& s, ComponentMap& componentMap, ModPortMap& modPortMap, ModuleInstance* instance) { @@ -2122,8 +2123,8 @@ void UhdmWriter::lateTypedefBinding(UHDM::Serializer& s, DesignComponent* mod, } } } - } else if (parent->UhdmType() == uhdmmodule) { - module* m = (module*)parent; + } else if (parent->UhdmType() == uhdmmodule_inst) { + module_inst* m = (module_inst*)parent; if (auto vars = m->Variables()) { for (auto decl : *vars) { if (decl->VpiName() == name) { @@ -2842,8 +2843,8 @@ void UhdmWriter::lateBinding(UHDM::Serializer& s, DesignComponent* mod, } if (ref->Actual_group()) continue; - if (m->UhdmType() == uhdmmodule || m->UhdmType() == uhdminterface || - m->UhdmType() == uhdmprogram) { + if (m->UhdmType() == uhdmmodule_inst || + m->UhdmType() == uhdminterface_inst || m->UhdmType() == uhdmprogram) { instance* inst = (instance*)m; if (inst->Nets()) { for (auto n : *inst->Nets()) { @@ -2996,7 +2997,8 @@ void UhdmWriter::lateBinding(UHDM::Serializer& s, DesignComponent* mod, ->getCommandLineParser() ->muteStdout()); } else { - if (m->UhdmType() == uhdmmodule || m->UhdmType() == uhdminterface || + if (m->UhdmType() == uhdmmodule_inst || + m->UhdmType() == uhdminterface_inst || m->UhdmType() == uhdmprogram) { instance* inst = (instance*)m; logic_net* net = s.MakeLogic_net(); @@ -3019,7 +3021,7 @@ void UhdmWriter::lateBinding(UHDM::Serializer& s, DesignComponent* mod, } bool UhdmWriter::writeElabModule(Serializer& s, ModuleInstance* instance, - module* m, ExprBuilder& exprBuilder) { + module_inst* m, ExprBuilder& exprBuilder) { Netlist* netlist = instance->getNetlist(); if (netlist == nullptr) return true; m->Ports(netlist->ports()); @@ -3152,7 +3154,8 @@ bool UhdmWriter::writeElabModule(Serializer& s, ModuleInstance* instance, } bool UhdmWriter::writeElabInterface(Serializer& s, ModuleInstance* instance, - interface* m, ExprBuilder& exprBuilder) { + interface_inst* m, + ExprBuilder& exprBuilder) { Netlist* netlist = instance->getNetlist(); ComponentMap componentMap; DesignComponent* mod = instance->getDefinition(); @@ -3241,7 +3244,7 @@ bool UhdmWriter::writeElabInterface(Serializer& s, ModuleInstance* instance, VectorOfmodport* dest_modports = s.MakeModportVec(); for (auto& orig_modport : orig_modports) { modport* dest_modport = s.MakeModport(); - dest_modport->Interface(m); + dest_modport->Interface_inst(m); dest_modport->VpiName(orig_modport.first); dest_modport->VpiParent(m); const FileContent* orig_fC = orig_modport.second.getFileContent(); @@ -3380,27 +3383,27 @@ void UhdmWriter::writeInstance(ModuleDefinition* mod, ModuleInstance* instance, ExprBuilder& exprBuilder) { FileSystem* const fileSystem = FileSystem::getInstance(); Serializer& s = compileDesign->getSerializer(); - VectorOfmodule* subModules = nullptr; + VectorOfmodule_inst* subModules = nullptr; VectorOfprogram* subPrograms = nullptr; - VectorOfinterface* subInterfaces = nullptr; + VectorOfinterface_inst* subInterfaces = nullptr; VectorOfprimitive* subPrimitives = nullptr; VectorOfprimitive_array* subPrimitiveArrays = nullptr; VectorOfgen_scope_array* subGenScopeArrays = nullptr; - if (m->UhdmType() == uhdmmodule) { - writeElabModule(s, instance, (module*)m, exprBuilder); + if (m->UhdmType() == uhdmmodule_inst) { + writeElabModule(s, instance, (module_inst*)m, exprBuilder); } else if (m->UhdmType() == uhdmgen_scope) { writeElabGenScope(s, instance, (gen_scope*)m, exprBuilder); - } else if (m->UhdmType() == uhdminterface) { - writeElabInterface(s, instance, (interface*)m, exprBuilder); + } else if (m->UhdmType() == uhdminterface_inst) { + writeElabInterface(s, instance, (interface_inst*)m, exprBuilder); } Netlist* netlist = instance->getNetlist(); if (netlist) { if (VectorOfinterface_array* subInterfaceArrays = netlist->interface_arrays()) { UHDM_OBJECT_TYPE utype = m->UhdmType(); - if (utype == uhdmmodule) { - ((module*)m)->Interface_arrays(subInterfaceArrays); + if (utype == uhdmmodule_inst) { + ((module_inst*)m)->Interface_arrays(subInterfaceArrays); for (interface_array* array : *subInterfaceArrays) { array->VpiParent(m); } @@ -3409,34 +3412,34 @@ void UhdmWriter::writeInstance(ModuleDefinition* mod, ModuleInstance* instance, for (interface_array* array : *subInterfaceArrays) { array->VpiParent(m); } - } else if (utype == uhdminterface) { - ((interface*)m)->Interface_arrays(subInterfaceArrays); + } else if (utype == uhdminterface_inst) { + ((interface_inst*)m)->Interface_arrays(subInterfaceArrays); for (interface_array* array : *subInterfaceArrays) { array->VpiParent(m); } } } - if (VectorOfinterface* subInterfaces = netlist->interfaces()) { + if (VectorOfinterface_inst* subInterfaces = netlist->interfaces()) { UHDM_OBJECT_TYPE utype = m->UhdmType(); - if (utype == uhdmmodule) { - ((module*)m)->Interfaces(subInterfaces); - for (interface* interf : *subInterfaces) { + if (utype == uhdmmodule_inst) { + ((module_inst*)m)->Interfaces(subInterfaces); + for (interface_inst* interf : *subInterfaces) { interf->VpiParent(m); } } else if (utype == uhdmgen_scope) { ((gen_scope*)m)->Interfaces(subInterfaces); - for (interface* interf : *subInterfaces) { + for (interface_inst* interf : *subInterfaces) { interf->VpiParent(m); } - } else if (utype == uhdminterface) { - ((interface*)m)->Interfaces(subInterfaces); - for (interface* interf : *subInterfaces) { + } else if (utype == uhdminterface_inst) { + ((interface_inst*)m)->Interfaces(subInterfaces); + for (interface_inst* interf : *subInterfaces) { interf->VpiParent(m); } } } } - std::map tempInstanceMap; + std::map tempInstanceMap; for (unsigned int i = 0; i < instance->getNbChildren(); i++) { ModuleInstance* child = instance->getChildren(i); DesignComponent* childDef = child->getDefinition(); @@ -3444,8 +3447,8 @@ void UhdmWriter::writeInstance(ModuleDefinition* mod, ModuleInstance* instance, valuedcomponenti_cast(childDef)) { VObjectType insttype = child->getType(); if (insttype == VObjectType::slModule_instantiation) { - if (subModules == nullptr) subModules = s.MakeModuleVec(); - module* sm = s.MakeModule(); + if (subModules == nullptr) subModules = s.MakeModule_instVec(); + module_inst* sm = s.MakeModule_inst(); tempInstanceMap.emplace(child, sm); if (childDef && !childDef->getFileContents().empty() && compileDesign->getCompiler()->isLibraryFile( @@ -3461,10 +3464,10 @@ void UhdmWriter::writeInstance(ModuleDefinition* mod, ModuleInstance* instance, child->getFileContent()->populateCoreMembers(child->getNodeId(), child->getNodeId(), sm); subModules->push_back(sm); - if (m->UhdmType() == uhdmmodule) { - ((module*)m)->Modules(subModules); - sm->Instance((module*)m); - sm->Module((module*)m); + if (m->UhdmType() == uhdmmodule_inst) { + ((module_inst*)m)->Modules(subModules); + sm->Instance((module_inst*)m); + sm->Module_inst((module_inst*)m); sm->VpiParent(m); } else if (m->UhdmType() == uhdmgen_scope) { ((gen_scope*)m)->Modules(subModules); @@ -3506,22 +3509,22 @@ void UhdmWriter::writeInstance(ModuleDefinition* mod, ModuleInstance* instance, sm->Gen_scopes()->push_back(a_gen_scope); a_gen_scope->VpiParent(sm); UHDM_OBJECT_TYPE utype = m->UhdmType(); - if (utype == uhdmmodule) { - ((module*)m)->Gen_scope_arrays(subGenScopeArrays); + if (utype == uhdmmodule_inst) { + ((module_inst*)m)->Gen_scope_arrays(subGenScopeArrays); sm->VpiParent(m); } else if (utype == uhdmgen_scope) { ((gen_scope*)m)->Gen_scope_arrays(subGenScopeArrays); sm->VpiParent(m); - } else if (utype == uhdminterface) { - ((interface*)m)->Gen_scope_arrays(subGenScopeArrays); + } else if (utype == uhdminterface_inst) { + ((interface_inst*)m)->Gen_scope_arrays(subGenScopeArrays); sm->VpiParent(m); } writeInstance(mm, child, a_gen_scope, compileDesign, componentMap, modPortMap, instanceMap, exprBuilder); } else if (insttype == VObjectType::slInterface_instantiation) { - if (subInterfaces == nullptr) subInterfaces = s.MakeInterfaceVec(); - interface* sm = s.MakeInterface(); + if (subInterfaces == nullptr) subInterfaces = s.MakeInterface_instVec(); + interface_inst* sm = s.MakeInterface_inst(); sm->VpiName(child->getInstanceName()); sm->VpiDefName(child->getModuleName()); sm->VpiFullName(child->getFullPathName()); @@ -3532,15 +3535,15 @@ void UhdmWriter::writeInstance(ModuleDefinition* mod, ModuleInstance* instance, sm->VpiDefLineNo(defFile->Line(mm->getNodeIds()[0])); subInterfaces->push_back(sm); UHDM_OBJECT_TYPE utype = m->UhdmType(); - if (utype == uhdmmodule) { - ((module*)m)->Interfaces(subInterfaces); - sm->Instance((module*)m); + if (utype == uhdmmodule_inst) { + ((module_inst*)m)->Interfaces(subInterfaces); + sm->Instance((module_inst*)m); sm->VpiParent(m); } else if (utype == uhdmgen_scope) { ((gen_scope*)m)->Interfaces(subInterfaces); sm->VpiParent(m); - } else if (utype == uhdminterface) { - ((interface*)m)->Interfaces(subInterfaces); + } else if (utype == uhdminterface_inst) { + ((interface_inst*)m)->Interfaces(subInterfaces); sm->VpiParent(m); } writeInstance(mm, child, sm, compileDesign, componentMap, modPortMap, @@ -3637,9 +3640,9 @@ void UhdmWriter::writeInstance(ModuleDefinition* mod, ModuleInstance* instance, child->getFileContent()->populateCoreMembers(child->getNodeId(), child->getNodeId(), gate); UHDM_OBJECT_TYPE utype = m->UhdmType(); - if (utype == uhdmmodule) { - ((module*)m)->Primitives(subPrimitives); - ((module*)m)->Primitive_arrays(subPrimitiveArrays); + if (utype == uhdmmodule_inst) { + ((module_inst*)m)->Primitives(subPrimitives); + ((module_inst*)m)->Primitive_arrays(subPrimitiveArrays); gate->VpiParent(m); } else if (utype == uhdmgen_scope) { ((gen_scope*)m)->Primitives(subPrimitives); @@ -3663,9 +3666,9 @@ void UhdmWriter::writeInstance(ModuleDefinition* mod, ModuleInstance* instance, sm->VpiDefLineNo(defFile->Line(prog->getNodeIds()[0])); subPrograms->push_back(sm); UHDM_OBJECT_TYPE utype = m->UhdmType(); - if (utype == uhdmmodule) { - ((module*)m)->Programs(subPrograms); - sm->Instance((module*)m); + if (utype == uhdmmodule_inst) { + ((module_inst*)m)->Programs(subPrograms); + sm->Instance((module_inst*)m); sm->VpiParent(m); } else if (utype == uhdmgen_scope) { ((gen_scope*)m)->Programs(subPrograms); @@ -3674,8 +3677,8 @@ void UhdmWriter::writeInstance(ModuleDefinition* mod, ModuleInstance* instance, writeElabProgram(s, child, sm); } else { // Undefined module - if (subModules == nullptr) subModules = s.MakeModuleVec(); - module* sm = s.MakeModule(); + if (subModules == nullptr) subModules = s.MakeModule_instVec(); + module_inst* sm = s.MakeModule_inst(); sm->VpiName(child->getInstanceName()); sm->VpiDefName(child->getModuleName()); sm->VpiFullName(child->getFullPathName()); @@ -3683,10 +3686,10 @@ void UhdmWriter::writeInstance(ModuleDefinition* mod, ModuleInstance* instance, child->getNodeId(), sm); subModules->push_back(sm); UHDM_OBJECT_TYPE utype = m->UhdmType(); - if (utype == uhdmmodule) { - ((module*)m)->Modules(subModules); - sm->Instance((module*)m); - sm->Module((module*)m); + if (utype == uhdmmodule_inst) { + ((module_inst*)m)->Modules(subModules); + sm->Instance((module_inst*)m); + sm->Module_inst((module_inst*)m); sm->VpiParent(m); } else if (utype == uhdmgen_scope) { ((gen_scope*)m)->Modules(subModules); @@ -3697,16 +3700,16 @@ void UhdmWriter::writeInstance(ModuleDefinition* mod, ModuleInstance* instance, } } - if (m->UhdmType() == uhdmmodule) { + if (m->UhdmType() == uhdmmodule_inst) { const auto& moduleArrayModuleInstancesMap = instance->getModuleArrayModuleInstancesMap(); if (!moduleArrayModuleInstancesMap.empty()) { - ((module*)m)->Module_arrays(s.MakeModule_arrayVec()); + ((module_inst*)m)->Module_arrays(s.MakeModule_arrayVec()); for (auto [modArray, modInstances] : moduleArrayModuleInstancesMap) { if (!modInstances.empty()) { - modArray->Modules(s.MakeModuleVec()); + modArray->Modules(s.MakeModule_instVec()); modArray->VpiParent(m); - ((module*)m)->Module_arrays()->push_back(modArray); + ((module_inst*)m)->Module_arrays()->push_back(modArray); for (ModuleInstance* modInst : modInstances) { auto it = tempInstanceMap.find(modInst); if (it != tempInstanceMap.end()) { @@ -3906,14 +3909,14 @@ vpiHandle UhdmWriter::write(PathId uhdmFileId) { // Interfaces auto modules = m_design->getModuleDefinitions(); - VectorOfinterface* uhdm_interfaces = s.MakeInterfaceVec(); + VectorOfinterface_inst* uhdm_interfaces = s.MakeInterface_instVec(); for (const auto& modNamePair : modules) { ModuleDefinition* mod = modNamePair.second; if (mod->getFileContents().empty()) { // Built-in primitive } else if (mod->getType() == VObjectType::slInterface_declaration) { const FileContent* fC = mod->getFileContents()[0]; - interface* m = s.MakeInterface(); + interface_inst* m = s.MakeInterface_inst(); componentMap.emplace(mod, m); m->VpiParent(d); m->VpiDefName(mod->getName()); @@ -3928,7 +3931,7 @@ vpiHandle UhdmWriter::write(PathId uhdmFileId) { d->AllInterfaces(uhdm_interfaces); // Modules - VectorOfmodule* uhdm_modules = s.MakeModuleVec(); + VectorOfmodule_inst* uhdm_modules = s.MakeModule_instVec(); // Udps VectorOfudp_defn* uhdm_udps = s.MakeUdp_defnVec(); for (const auto& modNamePair : modules) { @@ -3937,7 +3940,7 @@ vpiHandle UhdmWriter::write(PathId uhdmFileId) { // Built-in primitive } else if (mod->getType() == VObjectType::slModule_declaration) { const FileContent* fC = mod->getFileContents()[0]; - module* m = s.MakeModule(); + module_inst* m = s.MakeModule_inst(); if (m_compileDesign->getCompiler()->isLibraryFile( mod->getFileContents()[0]->getFileId())) { m->VpiCellInstance(true); @@ -3989,16 +3992,16 @@ vpiHandle UhdmWriter::write(PathId uhdmFileId) { // Elaborated Model (Folded) // Top-level modules - VectorOfmodule* uhdm_top_modules = s.MakeModuleVec(); + VectorOfmodule_inst* uhdm_top_modules = s.MakeModule_instVec(); for (ModuleInstance* inst : topLevelModules) { DesignComponent* component = inst->getDefinition(); ModuleDefinition* mod = valuedcomponenti_cast(component); const auto& itr = componentMap.find(mod); - module* m = s.MakeModule(); + module_inst* m = s.MakeModule_inst(); m->VpiTopModule(true); m->VpiTop(true); - module* def = (module*)itr->second; + module_inst* def = (module_inst*)itr->second; m->VpiDefName(def->VpiDefName()); m->VpiName(def->VpiDefName()); // Top's instance name is module name m->VpiFullName( diff --git a/src/hellodesign.cpp b/src/hellodesign.cpp index 206a3f2050..9dc8ddc16b 100644 --- a/src/hellodesign.cpp +++ b/src/hellodesign.cpp @@ -36,12 +36,13 @@ #include class DesignListener final : public UHDM::VpiListener { - void enterModule(const UHDM::module *const object, vpiHandle handle) final { + void enterModule_inst(const UHDM::module_inst *const object, + vpiHandle handle) final { const std::string &instName = object->VpiName(); - m_flatTraversal = - (instName.empty()) && ((object->VpiParent() == 0) || - ((object->VpiParent() != 0) && - (object->VpiParent()->VpiType() != vpiModule))); + m_flatTraversal = (instName.empty()) && + ((object->VpiParent() == 0) || + ((object->VpiParent() != 0) && + (object->VpiParent()->VpiType() != vpiModuleInst))); if (m_flatTraversal) std::cout << "Entering Module Definition: " << object->VpiDefName() << " " << intptr_t(object) << " " << object->UhdmId() << std::endl; diff --git a/src/hellouhdm.cpp b/src/hellouhdm.cpp index 80d856ee90..9c1d059ed0 100644 --- a/src/hellouhdm.cpp +++ b/src/hellouhdm.cpp @@ -100,7 +100,7 @@ int main(int argc, const char** argv) { result += "Module List:\n"; vpiHandle modItr = vpi_iterate(UHDM::uhdmallModules, the_design); while (vpiHandle obj_h = vpi_scan(modItr)) { - if (vpi_get(vpiType, obj_h) != vpiModule) { + if (vpi_get(vpiType, obj_h) != vpiModuleInst) { result += "ERROR: this is not a module\n"; } std::string defName; @@ -171,16 +171,16 @@ int main(int argc, const char** argv) { // Recursive tree traversal margin = " " + margin; - if (vpi_get(vpiType, obj_h) == vpiModule || + if (vpi_get(vpiType, obj_h) == vpiModuleInst || vpi_get(vpiType, obj_h) == vpiGenScope) { - vpiHandle subItr = vpi_iterate(vpiModule, obj_h); + vpiHandle subItr = vpi_iterate(vpiModuleInst, obj_h); while (vpiHandle sub_h = vpi_scan(subItr)) { res += inst_visit(sub_h, margin); vpi_release_handle(sub_h); } vpi_release_handle(subItr); } - if (vpi_get(vpiType, obj_h) == vpiModule || + if (vpi_get(vpiType, obj_h) == vpiModuleInst || vpi_get(vpiType, obj_h) == vpiGenScope) { vpiHandle subItr = vpi_iterate(vpiGenScopeArray, obj_h); while (vpiHandle sub_h = vpi_scan(subItr)) { diff --git a/src/roundtrip.cpp b/src/roundtrip.cpp index 4facd4614c..287a48d4ff 100644 --- a/src/roundtrip.cpp +++ b/src/roundtrip.cpp @@ -343,17 +343,17 @@ class RoundTripTracer final : public UHDM::UhdmListener { } } - inline static bool isModuleDefinition(const UHDM::module *const module) { - return ((module->VpiParent() == nullptr) || - (module->VpiParent()->UhdmType() != UHDM::uhdmmodule)) && - module->VpiName().empty(); + inline static bool isModuleDefinition(const UHDM::module_inst *const mdl) { + return ((mdl->VpiParent() == nullptr) || + (mdl->VpiParent()->UhdmType() != UHDM::uhdmmodule_inst)) && + mdl->VpiName().empty(); } inline static bool isInterfaceDefinition( - const UHDM::interface *const module) { - return ((module->VpiParent() == nullptr) || - (module->VpiParent()->UhdmType() != UHDM::uhdminterface)) && - module->VpiName().empty(); + const UHDM::interface_inst *const mdl) { + return ((mdl->VpiParent() == nullptr) || + (mdl->VpiParent()->UhdmType() != UHDM::uhdminterface_inst)) && + mdl->VpiName().empty(); } inline bool isWalkingModuleDefinition() const { @@ -361,8 +361,8 @@ class RoundTripTracer final : public UHDM::UhdmListener { rend = callstack.rend(); it != rend; ++it) { const UHDM::any *const any = *it; - if (any->UhdmType() == UHDM::uhdmmodule) { - return isModuleDefinition(static_cast(any)); + if (any->UhdmType() == UHDM::uhdmmodule_inst) { + return isModuleDefinition(static_cast(any)); } } return false; @@ -671,8 +671,8 @@ class RoundTripTracer final : public UHDM::UhdmListener { return; } - if ((parent->UhdmType() == UHDM::uhdmmodule) && - static_cast(parent)->VpiTop()) { + if ((parent->UhdmType() == UHDM::uhdmmodule_inst) && + static_cast(parent)->VpiTop()) { visited.insert(object); return; } @@ -2283,7 +2283,8 @@ class RoundTripTracer final : public UHDM::UhdmListener { if (visited.find(object) != visited.end()) return; const UHDM::any *const parent = object->VpiParent(); - if ((parent == nullptr) || (parent->UhdmType() != UHDM::uhdmmodule)) return; + if ((parent == nullptr) || (parent->UhdmType() != UHDM::uhdmmodule_inst)) + return; constexpr std::string_view keyword1 = "unnamed_clocking_block"; constexpr std::string_view keyword2 = "default"; @@ -2296,12 +2297,12 @@ class RoundTripTracer final : public UHDM::UhdmListener { const std::filesystem::path &filepath = object->VpiFile(); const std::string name = formatName(object->VpiName()); - const UHDM::module *const module = - static_cast(parent); + const UHDM::module_inst *const mdl = + static_cast(parent); std::string text; - if (module->Global_clocking() == object) { + if (mdl->Global_clocking() == object) { text.append(keyword3).append(1, kOverwriteMarker); - } else if (module->Default_clocking() == object) { + } else if (mdl->Default_clocking() == object) { text.append(keyword2).append(1, kOverwriteMarker); } text.append(keyword4); @@ -2687,7 +2688,7 @@ class RoundTripTracer final : public UHDM::UhdmListener { enterVariables_(object); } - void enterInterface(const UHDM::interface *const object) final { + void enterInterface_inst(const UHDM::interface_inst *const object) final { if (visited.find(object) != visited.end()) return; const std::filesystem::path &filepath = object->VpiFile(); @@ -2757,7 +2758,7 @@ class RoundTripTracer final : public UHDM::UhdmListener { object->VpiEndColumnNo() - keyword2.length(), keyword2); } - void enterModule(const UHDM::module *const object) final { + void enterModule_inst(const UHDM::module_inst *const object) final { if (visited.find(object) != visited.end()) return; const std::filesystem::path &filepath = object->VpiFile(); @@ -3396,7 +3397,7 @@ class RoundTripTracer final : public UHDM::UhdmListener { const UHDM::VectorOfclass_defn &objects) final {} void enterAllInterfaces(const UHDM::any *const object, - const UHDM::VectorOfinterface &objects) final {} + const UHDM::VectorOfinterface_inst &objects) final {} void enterAllUdps(const UHDM::any *const object, const UHDM::VectorOfudp_defn &objects) final {} @@ -3405,8 +3406,8 @@ class RoundTripTracer final : public UHDM::UhdmListener { const UHDM::VectorOfprogram &objects) final {} void enterAllModules(const UHDM::any *const object, - const UHDM::VectorOfmodule &objects) final { - for (UHDM::VectorOfmodule::const_reference module : objects) { + const UHDM::VectorOfmodule_inst &objects) final { + for (UHDM::VectorOfmodule_inst::const_reference module : objects) { module->VpiTop(false); } } @@ -3427,8 +3428,8 @@ class RoundTripTracer final : public UHDM::UhdmListener { const UHDM::VectorOfparam_assign &objects) final {} void enterTopModules(const UHDM::any *const object, - const UHDM::VectorOfmodule &objects) final { - for (UHDM::VectorOfmodule::const_reference module : objects) { + const UHDM::VectorOfmodule_inst &objects) final { + for (UHDM::VectorOfmodule_inst::const_reference module : objects) { module->VpiTop(true); visited.insert(module); } diff --git a/third_party/UHDM b/third_party/UHDM index e572ac3a37..ae0a2dc423 160000 --- a/third_party/UHDM +++ b/third_party/UHDM @@ -1 +1 @@ -Subproject commit e572ac3a376b43a2a74e6f5b359b815bebe99159 +Subproject commit ae0a2dc4236bc1e2e389de3ccad2d99add07a3f4 From 5b7fd29c4187e9b7d3be87c5abf08ef045518e74 Mon Sep 17 00:00:00 2001 From: HS Date: Tue, 20 Dec 2022 22:46:21 -0800 Subject: [PATCH 2/2] Log update --- tests/1364_2005/1364_2005.log | 40 +- tests/AaFirstTest/AaFirstTest.log | 2 +- tests/AllBinding/AllBinding.log | 22 +- tests/AlwaysNoElab/AlwaysNoElab.log | 36 +- tests/ArianeElab/ArianeElab.log | 1958 ++-- tests/ArianeElab2/ArianeElab2.log | 2158 ++--- tests/ArrayInst/ArrayInst.log | 326 +- .../ArrayMethodIterator.log | 12 +- tests/ArrayNet/ArrayNet.log | 16 +- tests/ArrayTypespec/ArrayTypespec.log | 16 +- tests/ArrayVarName/ArrayVarName.log | 34 +- tests/Assert/Assert.log | 12 +- tests/Assertions/Assertions.log | 46 +- tests/AssignPattern/AssignPattern.log | 16 +- tests/AssignPlus/AssignPlus.log | 26 +- tests/AssignRhsFlat/AssignRhsFlat.log | 20 +- tests/AssignSubs/AssignSubs.log | 26 +- tests/Assignments/Assignments.log | 44 +- tests/AssociativeArray/AssociativeArray.log | 24 +- tests/AssumeProp/AssumeProp.log | 12 +- tests/Attributes/Attributes.log | 130 +- tests/Attributes2/Attributes2.log | 38 +- tests/BadLabel/BadLabel.log | 50 +- tests/BadScope/BadScope.log | 18 +- tests/BeginKeywords/BeginKeywords.log | 2 +- tests/BiasValue/BiasValue.log | 42 +- tests/BinarySize/BinarySize.log | 48 +- tests/BindStmt/BindStmt.log | 294 +- tests/BindStmt2/BindStmt2.log | 342 +- tests/BindVarsAndEnum/BindVarsAndEnum.log | 62 +- tests/Bindings/Bindings.log | 212 +- tests/BitComplex/BitComplex.log | 34 +- tests/BitPartSelect/BitPartSelect.log | 48 +- tests/BitRanges/BitRanges.log | 28 +- tests/BitSelect/BitSelect.log | 62 +- tests/BitSelectExpr/BitSelectExpr.log | 30 +- tests/BitSelectHier/BitSelectHier.log | 4 +- tests/BitsArray/BitsArray.log | 60 +- tests/BitsHierPath/BitsHierPath.log | 80 +- tests/BitsLogic/BitsLogic.log | 26 +- tests/BitsOp/BitsOp.log | 120 +- tests/BitsStructMember/BitsStructMember.log | 32 +- tests/BlackBox/BlackBox.log | 40 +- tests/BlackBox/BlackBoxInst.log | 30 +- tests/BlackBox/BlackBoxInstTop.log | 14 +- tests/BlackBox/BlackBoxMod.log | 14 +- tests/BlackBox/BlackBoxSubMod.log | 28 +- .../BlackParrotComplex/BlackParrotComplex.log | 108 +- tests/BlackParrotConf/BlackParrotConf.log | 3130 +++---- .../BlackParrotMuteErrors.log | 6516 ++++++------- tests/BlackParrotParam/BlackParrotParam.log | 1534 ++-- .../BlackParrotSkipParam.log | 42 +- .../BlackParrotStructParam.log | 102 +- .../BlackboxMissingDef/BlackboxMissingDef.log | 30 +- tests/BuiltInMethod/BuiltInMethod.log | 28 +- tests/CarryTrans/CarryTrans.log | 216 +- tests/CaseExpression/CaseExpression.log | 146 +- tests/CaseFullElab/CaseFullElab.log | 130 +- tests/CaseInside/CaseInside.log | 12 +- tests/CastEnum/CastEnum.log | 16 +- tests/CastPartSelect/CastPartSelect.log | 22 +- tests/CastShift/CastShift.log | 46 +- tests/CastStructMember/CastStructMember.log | 28 +- tests/CastToParam/CastToParam.log | 36 +- tests/CastTypespec/CastTypespec.log | 52 +- tests/CastUnsigned/CastUnsigned.log | 36 +- tests/Cell/Cell.log | 72 +- tests/Chandle/Chandle.log | 12 +- tests/CheckerInst/CheckerInst.log | 34 +- tests/ClassFsm/ClassFsm.log | 58 +- tests/ClassFuncProto/ClassFuncProto.log | 24 +- tests/ClassFuncTask/ClassFuncTask.log | 4 +- tests/ClassMemberRef/ClassMemberRef.log | 16 +- tests/ClassMethodCall/ClassMethodCall.log | 16 +- tests/ClassMini/ClassMini.log | 16 +- tests/ClassParam/ClassParam.log | 4 +- tests/ClassParamAsParam/ClassParamAsParam.log | 12 +- tests/ClassScope/ClassScope.log | 958 +- tests/ClassTypeParam/ClassTypeParam.log | 16 +- tests/ClockingBlock/ClockingBlock.log | 32 +- tests/ClockingDrive/ClockingDrive.log | 20 +- tests/ClockingSntx/ClockingSntx.log | 94 +- tests/ClogCast/ClogCast.log | 72 +- tests/ClogParam/ClogParam.log | 80 +- tests/CmdLineOverride/CmdLineOverride.log | 20 +- tests/ComplexBitSelect/ComplexBitSelect.log | 60 +- tests/ComplexEscaped/ComplexEscaped.log | 22 +- .../ComplexParamOverload.log | 112 +- .../ComplexParamOverload2.log | 122 +- tests/ComplexVarSelect/ComplexVarSelect.log | 24 +- tests/ConcatOrder/ConcatOrder.log | 92 +- tests/ConcatRadix/ConcatRadix.log | 22 +- tests/ConcatVal/ConcatVal.log | 36 +- tests/ConcatWidth/ConcatWidth.log | 56 +- tests/CondOpPrec/CondOpPred.log | 42 +- tests/ConditionalOp/ConditionalOp.log | 96 +- tests/Connection/Connection.log | 64 +- tests/ConstCapital/ConstCapital.log | 22 +- tests/ConstExpand/ConstExpand.log | 30 +- tests/ConstHighConn/ConstHighConn.log | 42 +- tests/ConstPort/ConstPort.log | 40 +- tests/ConstantBits/ConstantBits.log | 26 +- tests/ConstantRange/ConstantRange.log | 66 +- tests/ContAssign/ContAssign.log | 32 +- tests/Context/Context.log | 30 +- tests/CovMacro/CovMacro.log | 52 +- tests/CrossFunc/CrossFunc.log | 44 +- tests/CrossItem/CrossItem.log | 16 +- tests/DataAttrib/DataAttrib.log | 20 +- tests/DecValue/DecValue.log | 46 +- tests/DefParamIndex/DefParamIndex.log | 52 +- tests/DefaultNetType/DefaultNetType.log | 82 +- tests/DefaultTag/DefaultTag.log | 22 +- tests/DeferAssert/DeferAssert.log | 16 +- tests/Delay2Param/Delay2Param.log | 150 +- tests/DelayAssign/DelayAssign.log | 208 +- tests/Disable/Disable.log | 12 +- tests/DollarBits/DollarBits.log | 70 +- tests/DollarBitsUnary/DollarBitsUnary.log | 30 +- tests/DollarRoot/DollarRoot.log | 494 +- tests/DoublePres/DoublePres.log | 314 +- tests/DpiChandle/DpiChandle.log | 32 +- tests/DpiFunc/DpiFunc.log | 20 +- tests/DpiTask/DpiTask.log | 20 +- tests/DynArrayKind/DynArrayKind.log | 36 +- tests/EarlgreyPackParam/EarlgreyPackParam.log | 152 +- tests/ElabCParam/ElabCParam.log | 168 +- tests/ElabIf/ElabIf.log | 72 +- tests/ElabParam/ElabParam.log | 32 +- tests/EmptyAssign/EmptyAssign.log | 46 +- tests/EnumConcat/EnumConcat.log | 20 +- tests/EnumConst/EnumConst.log | 10 +- tests/EnumConstConcat/EnumConstConcat.log | 16 +- tests/EnumConstElab/EnumConstElab.log | 76 +- tests/EnumVal/EnumVal.log | 12 +- tests/EnumVar/EnumVar.log | 16 +- tests/EnumVarNoTypedef/EnumVarNoTypedef.log | 12 +- tests/Escape/Escape.log | 4 +- tests/EvalFunc/EvalFunc.log | 96 +- tests/EvalFuncArray/EvalFuncArray.log | 4 +- tests/EvalFuncCont/EvalFuncCont.log | 62 +- tests/EvalFuncNamed/EvalFuncNamed.log | 66 +- tests/EvalFuncPack/EvalFuncPack.log | 42 +- tests/Event/Event.log | 12 +- tests/ExpectStmt/ExpectStmt.log | 24 +- .../ExponTimeIfElseGen/ExponTimeIfElseGen.log | 52 +- tests/ExtendClassMember/ExtendClassMember.log | 4 +- tests/FSM2Always/FSM2Always.log | 120 +- tests/FSMBsp13/FSMBsp13.log | 674 +- tests/FSMFunction/FSMFunction.log | 132 +- tests/FSMSingleAlways/FSMSingleAlways.log | 112 +- tests/FileList/FileList.log | 46 +- tests/FileParam/FileParam.log | 8 +- tests/ForElab/ForElab.log | 56 +- tests/ForLoop/ForLoop.log | 20 +- tests/ForLoopBind/ForLoopBind.log | 4 +- tests/ForeachArray/ForeachArray.log | 16 +- tests/ForeachClass/ForeachClass.log | 4 +- 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tests/GateLevel/GateLevel.log | 168 +- tests/Gates/Gates.log | 468 +- tests/GenBlock/GenBlock.log | 40 +- tests/GenBlockVar/GenBlockVar.log | 18 +- tests/GenCaseStmt/GenCaseStmt.log | 60 +- tests/GenIf/GenIf.log | 12 +- tests/GenModHierPath/GenModHierPath.log | 36 +- tests/GenNet/GenNet.log | 46 +- tests/GenScopeFullName/GenScopeFullName.log | 30 +- tests/GenScopeFunc/GenScopeFunc.log | 24 +- tests/GenScopeHierPath/GenScopeHierPath.log | 202 +- tests/GenScopeHierPath2/GenScopeHierPath2.log | 30 +- tests/GenerateAssigns/GenerateAssigns.log | 48 +- tests/GenerateBlock/GenerateBlock.log | 16 +- tests/GenerateInterface/GenerateInterface.log | 98 +- tests/GenerateModule/GenerateModule.log | 118 +- tests/GenerateRegion/GenerateRegion.log | 214 +- tests/GenerateUnnamed/GenerateUnnamed.log | 74 +- tests/HierBitSelect/HierBitSelect.log | 20 +- tests/HierBitSlice/HierBitSlice.log | 334 +- tests/HierMultiSelect/HierMultiSelect.log | 32 +- .../HierPathBeginBlock/HierPathBeginBlock.log | 54 +- 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+- tests/ParamOverload4/ParamOverload4.log | 40 +- tests/ParamOverloadProp/ParamOverloadProp.log | 34 +- tests/ParamOverloading/ParamOverloading.log | 84 +- tests/ParamRef/ParamRef.log | 52 +- tests/ParamScope/ParamScope.log | 78 +- .../ParamSubstituteComplex.log | 154 +- tests/ParamTypespec/ParamTypespec.log | 42 +- tests/ParamTypespec2/ParamTypespec2.log | 62 +- tests/PartSelect3/PartSelect3.log | 16 +- tests/PartSelect4/PartSelect4.log | 124 +- tests/PartSelectElab/PartSelectElab.log | 36 +- tests/PartSelectHier/PartSelectHier.log | 20 +- .../PartSelectHierPath/PartSelectHierPath.log | 18 +- .../PartSelectNoParent/PartSelectNoParent.log | 54 +- tests/PartSelectParent/PartSelectParent.log | 26 +- tests/PartSelectRange/PartSelectRange.log | 36 +- tests/PatAssignOp/PatAssignOp.log | 62 +- .../PatternAssignLogic/PatternAssignLogic.log | 16 +- tests/PatternAssignment/PatternAssignment.log | 24 +- tests/PatternOrder/PatternOrder.log | 12 +- tests/PkgImportFunc/PkgImportFunc.log | 22 +- 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tests/UnitClass/UnitClass.log | 2 +- tests/UnitConcat/UnitConcat.log | 8 +- tests/UnitDefParam/UnitDefParam.log | 350 +- tests/UnitElab/UnitElab.log | 5656 ++++++------ tests/UnitElabBlock/UnitElabBlock.log | 2 +- .../UnitElabExternNested.log | 2 +- tests/UnitEnum/UnitEnum.log | 32 +- tests/UnitForeach/UnitForeach.log | 2 +- tests/UnitLibrary/UnitLibrary.log | 2 +- tests/UnitPackage/UnitPackage.log | 82 +- tests/UnitPartSelect/UnitPartSelect.log | 128 +- tests/UnitPython/UnitPython.log | 2 +- tests/UnitSVA/UnitSVA.log | 40 +- tests/UnitTest/UnitTest.log | 128 +- tests/UnitThisNew/UnitThisNew.log | 4 +- tests/UnpackPort/UnpackPort.log | 50 +- tests/UnpackedTypespec/UnpackedTypespec.log | 36 +- tests/UnsignedParam/UnsignedParam.log | 48 +- tests/UnsizeConstExpr/UnsizeConstExpr.log | 16 +- tests/Unsized/Unsized.log | 24 +- tests/UnsizedArray/UnsizedArray.log | 12 +- tests/UnsizedConstInst/UnsizedConstInst.log | 50 +- tests/UnsizedElabComp/UnsizedElabComp.log | 38 +- tests/UnsizedPacked/UnsizedPacked.log | 16 +- tests/UnsizedParam/UnsizedParam.log | 64 +- tests/Value4States/Value4States.log | 24 +- tests/ValueSize/ValueSize.log | 4 +- tests/Values/Values.log | 28 +- tests/VarDecl/VarDecl.log | 30 +- tests/VarDecl2/VarDecl2.log | 30 +- tests/VarInFunc/VarInFunc.log | 44 +- tests/VarRangeTypedef/VarRangeTypedef.log | 4 +- tests/VarSelect/VarSelect.log | 20 +- tests/VarSelectGenStmt/VarSelectGenStmt.log | 68 +- tests/VarType/VarType.log | 20 +- tests/VirtualClass/VirtualClass.log | 24 +- tests/VoidFuncReturn/VoidFuncReturn.log | 24 +- tests/Wand/Wand.log | 32 +- tests/WildConn/WildConn.log | 58 +- tests/WireLogicSize/WireLogicSize.log | 68 +- tests/WireUnpacked/WireUnpacked.log | 16 +- tests/XValue/XValue.log | 36 +- third_party/tests/AVLMM/AVLMM.log | 2 +- third_party/tests/AmiqEth/AmiqEth.log | 2 +- .../AmiqSimpleTestSuite.log | 4 +- third_party/tests/ApbSlave/ApbSlave.log | 2 +- third_party/tests/AzadiRTL/AzadiRTL.log | 2 +- third_party/tests/BuildOVMPkg/BuildOVMPkg.log | 2 +- third_party/tests/BuildUVMPkg/BuildUVMPkg.log | 2 +- third_party/tests/Compl1001/Compl1001.log | 2 +- third_party/tests/CoresSweRV/CoresSweRV.log | 4 +- .../tests/CoresSweRVMP/CoresSweRVMP.log | 28 +- third_party/tests/Driver/Driver.log | 4 +- .../Earlgrey_0_1/sim-icarus/Earlgrey_0_1.log | 2 +- .../Earlgrey_Verilator_01_05_21.log | 4 +- .../sim-verilator/Earlgrey_Verilator_0_1.log | 4 +- third_party/tests/Ibex/Ibex.log | 4 +- third_party/tests/IbexGoogle/IbexGoogle.log | 2 +- third_party/tests/IncompTitan/IncompTitan.log | 2 +- third_party/tests/MiniAmiq/MiniAmiq.log | 4 +- third_party/tests/Monitor/Monitor.log | 4 +- .../tests/NyuziProcessor/NyuziProcessor.log | 296 +- third_party/tests/OVMSwitch/OVMSwitch.log | 4 +- third_party/tests/Opentitan/Earlgrey.log | 2 +- third_party/tests/Opentitan/Opentitan.log | 4 +- third_party/tests/RiscV/RiscV.log | 2 +- third_party/tests/Rp32/rp32.log | 8 +- third_party/tests/SVSwitch/SVSwitch.log | 4 +- third_party/tests/Scoreboard/Scoreboard.log | 2 +- third_party/tests/Scr1/Scr1.log | 2 +- third_party/tests/Scr1SvTests/Scr1SvTests.log | 2 +- third_party/tests/SeqDriver/SeqDriver.log | 4 +- third_party/tests/SimpleOVM/SimpleOVM.log | 2 +- .../SimpleParserTest/SimpleParserTest.log | 948 +- third_party/tests/SimpleUVM/SimpleUVM.log | 4 +- third_party/tests/SimpleVMM/SimpleVMM.log | 2 +- third_party/tests/Sky130Cell/Sky130Cell.log | 8180 ++++++++--------- third_party/tests/Tnoc/Tnoc.log | 4 +- .../tests/UVMNestedSeq/UVMNestedSeq.log | 4 +- third_party/tests/UVMSwitch/UVMSwitch.log | 4 +- third_party/tests/UnitAmiqEth/UnitAmiqEth.log | 2 +- .../aes_5cycle_2stage/YosysBigSimAes.log | 2 +- .../amber23/YosysBigSimAmber23.log | 2 +- .../elliptic_curve_group/YosysBigSimEllip.log | 2 +- .../YosysBigSim/lm32/YosysBigSimLm32.log | 2 +- .../openmsp430/YosysBigSimOpenMsp.log | 2 +- .../reed_solomon_decoder/YosysBigSimReed.log | 2 +- .../softusb_navre/YosysBigSimSoft.log | 2 +- .../verilog-pong/YosysBigSimPong.log | 2 +- .../tests/YosysBoom/YosysSmallBoom.log | 2 +- third_party/tests/YosysCam/YosysCam.log | 2 +- third_party/tests/YosysDsp/YosysDsp.log | 2 +- third_party/tests/YosysEth/YosysEth.log | 2 +- third_party/tests/YosysIce40/YosysIce40.log | 2 +- .../tests/YosysMarlann/YosysMarlann.log | 2 +- .../YosysOldTests/aes_core/YosysOldAes.log | 2 +- .../tests/YosysOldTests/i2c/YosysOldI2c.log | 2 +- .../YosysOldTests/openmsp430/YosysOldOpen.log | 2 +- .../tests/YosysOldTests/or1200/YosysOldOr.log | 2 +- .../tests/YosysOldTests/sasc/YosysOldSasc.log | 2 +- .../simple_spi/YosysOldSimpleSpi.log | 2 +- .../tests/YosysOldTests/spi/YosysOldSpi.log | 2 +- .../YosysOldTests/ss_pcm/YosysOldSsPcm.log | 2 +- .../systemcaes/YosysOldSystem.log | 2 +- .../YosysOldTests/usb_phy/YosysOldUsb.log | 2 +- third_party/tests/YosysRiscv/YosysRiscv.log | 2 +- third_party/tests/YosysSmall/YosysSmall.log | 2 +- third_party/tests/YosysVerx/YosysVerx.log | 2 +- third_party/tests/oh/BasicOh.log | 6982 +++++++------- third_party/tests/xgate/Xgate.log | 4 +- 589 files changed, 33060 insertions(+), 33078 deletions(-) diff --git a/tests/1364_2005/1364_2005.log b/tests/1364_2005/1364_2005.log index 4a6f4c896b..53d8f4bfd3 100644 --- a/tests/1364_2005/1364_2005.log +++ b/tests/1364_2005/1364_2005.log @@ -116,7 +116,7 @@ constant 10 design 1 logic_net 16 logic_typespec 4 -module 3 +module_inst 3 range 5 === UHDM Object Stats End === [INF:UH0707] Elaborating UHDM... @@ -126,7 +126,7 @@ constant 10 design 1 logic_net 16 logic_typespec 4 -module 3 +module_inst 3 range 5 === UHDM Object Stats End === [INF:UH0708] Writing UHDM DB: ${SURELOG_DIR}/build/regression/1364_2005/slpp_all/surelog.uhdm ... @@ -142,7 +142,7 @@ design: (work@main) |vpiElaborated:1 |vpiName:work@main |uhdmallModules: -\_module: work@main (work@main), file:${SURELOG_DIR}/tests/1364_2005/dut.v, line:3:1, endln:11:10 +\_module_inst: work@main (work@main), file:${SURELOG_DIR}/tests/1364_2005/dut.v, line:3:1, endln:11:10 |vpiParent: \_design: (work@main) |vpiFullName:work@main @@ -150,68 +150,68 @@ design: (work@main) |vpiNet: \_logic_net: (work@main.foo), line:5:14, endln:5:17 |vpiParent: - \_module: work@main (work@main), file:${SURELOG_DIR}/tests/1364_2005/dut.v, line:3:1, endln:11:10 + \_module_inst: work@main (work@main), file:${SURELOG_DIR}/tests/1364_2005/dut.v, line:3:1, endln:11:10 |vpiName:foo |vpiFullName:work@main.foo |vpiNetType:48 |vpiNet: \_logic_net: (work@main.bar), line:5:19, endln:5:22 |vpiParent: - \_module: work@main (work@main), file:${SURELOG_DIR}/tests/1364_2005/dut.v, line:3:1, endln:11:10 + \_module_inst: work@main (work@main), file:${SURELOG_DIR}/tests/1364_2005/dut.v, line:3:1, endln:11:10 |vpiName:bar |vpiFullName:work@main.bar |vpiNetType:48 |vpiNet: \_logic_net: (work@main.adr), line:6:14, endln:6:17 |vpiParent: - \_module: work@main (work@main), file:${SURELOG_DIR}/tests/1364_2005/dut.v, line:3:1, endln:11:10 + \_module_inst: work@main (work@main), file:${SURELOG_DIR}/tests/1364_2005/dut.v, line:3:1, endln:11:10 |vpiName:adr |vpiFullName:work@main.adr |vpiNetType:48 |vpiNet: \_logic_net: (work@main.bit), line:8:13, endln:8:16 |vpiParent: - \_module: work@main (work@main), file:${SURELOG_DIR}/tests/1364_2005/dut.v, line:3:1, endln:11:10 + \_module_inst: work@main (work@main), file:${SURELOG_DIR}/tests/1364_2005/dut.v, line:3:1, endln:11:10 |vpiName:bit |vpiFullName:work@main.bit |vpiNetType:48 |vpiNet: \_logic_net: (work@main.rst), line:8:18, endln:8:21 |vpiParent: - \_module: work@main (work@main), file:${SURELOG_DIR}/tests/1364_2005/dut.v, line:3:1, endln:11:10 + \_module_inst: work@main (work@main), file:${SURELOG_DIR}/tests/1364_2005/dut.v, line:3:1, endln:11:10 |vpiName:rst |vpiFullName:work@main.rst |vpiNetType:48 |vpiNet: \_logic_net: (work@main.clk), line:8:23, endln:8:26 |vpiParent: - \_module: work@main (work@main), file:${SURELOG_DIR}/tests/1364_2005/dut.v, line:3:1, endln:11:10 + \_module_inst: work@main (work@main), file:${SURELOG_DIR}/tests/1364_2005/dut.v, line:3:1, endln:11:10 |vpiName:clk |vpiFullName:work@main.clk |vpiNetType:48 |vpiNet: \_logic_net: (work@main.load_enable), line:9:13, endln:9:24 |vpiParent: - \_module: work@main (work@main), file:${SURELOG_DIR}/tests/1364_2005/dut.v, line:3:1, endln:11:10 + \_module_inst: work@main (work@main), file:${SURELOG_DIR}/tests/1364_2005/dut.v, line:3:1, endln:11:10 |vpiName:load_enable |vpiFullName:work@main.load_enable |vpiNetType:48 |vpiNet: \_logic_net: (work@main.write_enable), line:9:26, endln:9:38 |vpiParent: - \_module: work@main (work@main), file:${SURELOG_DIR}/tests/1364_2005/dut.v, line:3:1, endln:11:10 + \_module_inst: work@main (work@main), file:${SURELOG_DIR}/tests/1364_2005/dut.v, line:3:1, endln:11:10 |vpiName:write_enable |vpiFullName:work@main.write_enable |vpiNetType:48 |uhdmtopModules: -\_module: work@main (work@main), file:${SURELOG_DIR}/tests/1364_2005/dut.v, line:3:1, endln:11:10 +\_module_inst: work@main (work@main), file:${SURELOG_DIR}/tests/1364_2005/dut.v, line:3:1, endln:11:10 |vpiName:work@main |vpiDefName:work@main |vpiTop:1 |vpiNet: \_logic_net: (work@main.foo), line:5:14, endln:5:17 |vpiParent: - \_module: work@main (work@main), file:${SURELOG_DIR}/tests/1364_2005/dut.v, line:3:1, endln:11:10 + \_module_inst: work@main (work@main), file:${SURELOG_DIR}/tests/1364_2005/dut.v, line:3:1, endln:11:10 |vpiTypespec: \_logic_typespec: , line:5:4, endln:5:13 |vpiRange: @@ -238,7 +238,7 @@ design: (work@main) |vpiNet: \_logic_net: (work@main.bar), line:5:19, endln:5:22 |vpiParent: - \_module: work@main (work@main), file:${SURELOG_DIR}/tests/1364_2005/dut.v, line:3:1, endln:11:10 + \_module_inst: work@main (work@main), file:${SURELOG_DIR}/tests/1364_2005/dut.v, line:3:1, endln:11:10 |vpiTypespec: \_logic_typespec: , line:5:4, endln:5:13 |vpiName:bar @@ -247,7 +247,7 @@ design: (work@main) |vpiNet: \_logic_net: (work@main.adr), line:6:14, endln:6:17 |vpiParent: - \_module: work@main (work@main), file:${SURELOG_DIR}/tests/1364_2005/dut.v, line:3:1, endln:11:10 + \_module_inst: work@main (work@main), file:${SURELOG_DIR}/tests/1364_2005/dut.v, line:3:1, endln:11:10 |vpiTypespec: \_logic_typespec: , line:6:4, endln:6:13 |vpiRange: @@ -274,7 +274,7 @@ design: (work@main) |vpiNet: \_logic_net: (work@main.bit), line:8:13, endln:8:16 |vpiParent: - \_module: work@main (work@main), file:${SURELOG_DIR}/tests/1364_2005/dut.v, line:3:1, endln:11:10 + \_module_inst: work@main (work@main), file:${SURELOG_DIR}/tests/1364_2005/dut.v, line:3:1, endln:11:10 |vpiTypespec: \_logic_typespec: , line:8:4, endln:8:7 |vpiName:bit @@ -283,7 +283,7 @@ design: (work@main) |vpiNet: \_logic_net: (work@main.rst), line:8:18, endln:8:21 |vpiParent: - \_module: work@main (work@main), file:${SURELOG_DIR}/tests/1364_2005/dut.v, line:3:1, endln:11:10 + \_module_inst: work@main (work@main), file:${SURELOG_DIR}/tests/1364_2005/dut.v, line:3:1, endln:11:10 |vpiTypespec: \_logic_typespec: , line:8:4, endln:8:7 |vpiName:rst @@ -292,7 +292,7 @@ design: (work@main) |vpiNet: \_logic_net: (work@main.clk), line:8:23, endln:8:26 |vpiParent: - \_module: work@main (work@main), file:${SURELOG_DIR}/tests/1364_2005/dut.v, line:3:1, endln:11:10 + \_module_inst: work@main (work@main), file:${SURELOG_DIR}/tests/1364_2005/dut.v, line:3:1, endln:11:10 |vpiTypespec: \_logic_typespec: , line:8:4, endln:8:7 |vpiName:clk @@ -301,7 +301,7 @@ design: (work@main) |vpiNet: \_logic_net: (work@main.load_enable), line:9:13, endln:9:24 |vpiParent: - \_module: work@main (work@main), file:${SURELOG_DIR}/tests/1364_2005/dut.v, line:3:1, endln:11:10 + \_module_inst: work@main (work@main), file:${SURELOG_DIR}/tests/1364_2005/dut.v, line:3:1, endln:11:10 |vpiTypespec: \_logic_typespec: , line:9:4, endln:9:7 |vpiName:load_enable @@ -310,7 +310,7 @@ design: (work@main) |vpiNet: \_logic_net: (work@main.write_enable), line:9:26, endln:9:38 |vpiParent: - \_module: work@main (work@main), file:${SURELOG_DIR}/tests/1364_2005/dut.v, line:3:1, endln:11:10 + \_module_inst: work@main (work@main), file:${SURELOG_DIR}/tests/1364_2005/dut.v, line:3:1, endln:11:10 |vpiTypespec: \_logic_typespec: , line:9:4, endln:9:7 |vpiName:write_enable diff --git a/tests/AaFirstTest/AaFirstTest.log b/tests/AaFirstTest/AaFirstTest.log index d39c0e3be0..7977c6b893 100644 --- a/tests/AaFirstTest/AaFirstTest.log +++ b/tests/AaFirstTest/AaFirstTest.log @@ -54,7 +54,7 @@ io_decl 11 logic_net 2 logic_typespec 3 logic_var 1 -module 4 +module_inst 4 package 2 port 3 ref_obj 3 diff --git a/tests/AllBinding/AllBinding.log b/tests/AllBinding/AllBinding.log index 8b8e2b4bbc..12002da06f 100644 --- a/tests/AllBinding/AllBinding.log +++ b/tests/AllBinding/AllBinding.log @@ -101,7 +101,7 @@ enum_typespec 1 enum_var 2 logic_net 2 logic_typespec 1 -module 3 +module_inst 3 port 2 range 1 ref_obj 2 @@ -116,7 +116,7 @@ enum_typespec 1 enum_var 2 logic_net 2 logic_typespec 1 -module 3 +module_inst 3 port 3 range 1 ref_obj 3 @@ -134,7 +134,7 @@ design: (work@top) |vpiElaborated:1 |vpiName:work@top |uhdmallModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/AllBinding/dut.sv, line:1:1, endln:5:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/AllBinding/dut.sv, line:1:1, endln:5:10 |vpiParent: \_design: (work@top) |vpiFullName:work@top @@ -142,19 +142,19 @@ design: (work@top) |vpiNet: \_logic_net: (work@top.dmem2exu_resp_i), line:1:57, endln:1:72 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/AllBinding/dut.sv, line:1:1, endln:5:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/AllBinding/dut.sv, line:1:1, endln:5:10 |vpiName:dmem2exu_resp_i |vpiFullName:work@top.dmem2exu_resp_i |vpiNet: \_logic_net: (work@top.dmem2exu_resp_ii), line:3:37, endln:3:53 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/AllBinding/dut.sv, line:1:1, endln:5:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/AllBinding/dut.sv, line:1:1, endln:5:10 |vpiName:dmem2exu_resp_ii |vpiFullName:work@top.dmem2exu_resp_ii |vpiPort: \_port: (dmem2exu_resp_i), line:1:57, endln:1:72 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/AllBinding/dut.sv, line:1:1, endln:5:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/AllBinding/dut.sv, line:1:1, endln:5:10 |vpiName:dmem2exu_resp_i |vpiDirection:1 |vpiLowConn: @@ -209,12 +209,12 @@ design: (work@top) |vpiTypedef: \_enum_typespec: (type_scr1_mem_resp_e), line:1:1, endln:5:24 |uhdmtopModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/AllBinding/dut.sv, line:1:1, endln:5:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/AllBinding/dut.sv, line:1:1, endln:5:10 |vpiName:work@top |vpiVariables: \_enum_var: (work@top.dmem2exu_resp_i), line:1:57, endln:1:72 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/AllBinding/dut.sv, line:1:1, endln:5:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/AllBinding/dut.sv, line:1:1, endln:5:10 |vpiTypespec: \_enum_typespec: (type_scr1_mem_resp_e), line:1:1, endln:5:24 |vpiName:dmem2exu_resp_i @@ -223,7 +223,7 @@ design: (work@top) |vpiVariables: \_enum_var: (work@top.dmem2exu_resp_ii), line:3:37, endln:3:53 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/AllBinding/dut.sv, line:1:1, endln:5:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/AllBinding/dut.sv, line:1:1, endln:5:10 |vpiTypespec: \_enum_typespec: (type_scr1_mem_resp_e), line:1:1, endln:5:24 |vpiName:dmem2exu_resp_ii @@ -235,7 +235,7 @@ design: (work@top) |vpiPort: \_port: (dmem2exu_resp_i), line:1:57, endln:1:72 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/AllBinding/dut.sv, line:1:1, endln:5:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/AllBinding/dut.sv, line:1:1, endln:5:10 |vpiName:dmem2exu_resp_i |vpiDirection:1 |vpiLowConn: @@ -249,7 +249,7 @@ design: (work@top) |vpiTypedef: \_enum_typespec: (type_scr1_mem_resp_e), line:1:1, endln:5:24 |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/AllBinding/dut.sv, line:1:1, endln:5:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/AllBinding/dut.sv, line:1:1, endln:5:10 =================== [ FATAL] : 0 [ SYNTAX] : 0 diff --git a/tests/AlwaysNoElab/AlwaysNoElab.log b/tests/AlwaysNoElab/AlwaysNoElab.log index e3b7c9f66e..666755d64e 100644 --- a/tests/AlwaysNoElab/AlwaysNoElab.log +++ b/tests/AlwaysNoElab/AlwaysNoElab.log @@ -445,7 +445,7 @@ io_decl 11 logic_net 2 logic_typespec 1 logic_var 2 -module 5 +module_inst 5 operation 7 package 2 param_assign 4 @@ -476,7 +476,7 @@ io_decl 22 logic_net 2 logic_typespec 1 logic_var 2 -module 5 +module_inst 5 operation 8 package 2 param_assign 4 @@ -974,14 +974,14 @@ design: (work@dut) \_int_typespec: |vpiSigned:1 |uhdmallModules: -\_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/AlwaysNoElab/dut.sv, line:1:1, endln:12:10 +\_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/AlwaysNoElab/dut.sv, line:1:1, endln:12:10 |vpiParent: \_design: (work@dut) |vpiFullName:work@dut |vpiParameter: \_parameter: (work@dut.NrDevices), line:2:17, endln:2:26 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/AlwaysNoElab/dut.sv, line:1:1, endln:12:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/AlwaysNoElab/dut.sv, line:1:1, endln:12:10 |UINT:1 |vpiSigned:1 |vpiName:NrDevices @@ -989,7 +989,7 @@ design: (work@dut) |vpiParameter: \_parameter: (work@dut.NumBitsDeviceSel), line:5:27, endln:5:43 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/AlwaysNoElab/dut.sv, line:1:1, endln:12:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/AlwaysNoElab/dut.sv, line:1:1, endln:12:10 |vpiTypespec: \_int_typespec: , line:5:14, endln:5:26 |vpiParent: @@ -1004,7 +1004,7 @@ design: (work@dut) |vpiParamAssign: \_param_assign: , line:2:17, endln:2:30 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/AlwaysNoElab/dut.sv, line:1:1, endln:12:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/AlwaysNoElab/dut.sv, line:1:1, endln:12:10 |vpiRhs: \_constant: , line:2:29, endln:2:30 |vpiDecompile:1 @@ -1021,7 +1021,7 @@ design: (work@dut) |vpiParamAssign: \_param_assign: , line:5:27, endln:5:83 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/AlwaysNoElab/dut.sv, line:1:1, endln:12:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/AlwaysNoElab/dut.sv, line:1:1, endln:12:10 |vpiRhs: \_operation: , line:5:46, endln:5:83 |vpiOpType:32 @@ -1067,20 +1067,20 @@ design: (work@dut) |vpiNet: \_logic_net: (work@dut.device_sel_req), line:6:32, endln:6:46 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/AlwaysNoElab/dut.sv, line:1:1, endln:12:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/AlwaysNoElab/dut.sv, line:1:1, endln:12:10 |vpiName:device_sel_req |vpiFullName:work@dut.device_sel_req |vpiNetType:36 |vpiNet: \_logic_net: (work@dut.device), line:7:7, endln:7:13 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/AlwaysNoElab/dut.sv, line:1:1, endln:12:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/AlwaysNoElab/dut.sv, line:1:1, endln:12:10 |vpiName:device |vpiFullName:work@dut.device |vpiProcess: \_always: , line:8:3, endln:10:6 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/AlwaysNoElab/dut.sv, line:1:1, endln:12:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/AlwaysNoElab/dut.sv, line:1:1, endln:12:10 |vpiStmt: \_begin: (work@dut), line:8:15, endln:10:6 |vpiParent: @@ -1117,12 +1117,12 @@ design: (work@dut) \_logic_var: (work@dut.device_sel_req), line:6:32, endln:6:46 |vpiAlwaysType:2 |uhdmtopModules: -\_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/AlwaysNoElab/dut.sv, line:1:1, endln:12:10 +\_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/AlwaysNoElab/dut.sv, line:1:1, endln:12:10 |vpiName:work@dut |vpiVariables: \_logic_var: (work@dut.device_sel_req), line:6:32, endln:6:46 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/AlwaysNoElab/dut.sv, line:1:1, endln:12:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/AlwaysNoElab/dut.sv, line:1:1, endln:12:10 |vpiTypespec: \_logic_typespec: , line:6:3, endln:6:31 |vpiRange: @@ -1167,7 +1167,7 @@ design: (work@dut) |vpiVariables: \_int_var: (work@dut.device), line:7:7, endln:7:17 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/AlwaysNoElab/dut.sv, line:1:1, endln:12:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/AlwaysNoElab/dut.sv, line:1:1, endln:12:10 |vpiTypespec: \_int_typespec: , line:7:3, endln:7:6 |vpiSigned:1 @@ -1183,7 +1183,7 @@ design: (work@dut) |vpiParameter: \_parameter: (work@dut.NrDevices), line:2:17, endln:2:26 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/AlwaysNoElab/dut.sv, line:1:1, endln:12:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/AlwaysNoElab/dut.sv, line:1:1, endln:12:10 |UINT:1 |vpiSigned:1 |vpiName:NrDevices @@ -1191,7 +1191,7 @@ design: (work@dut) |vpiParameter: \_parameter: (work@dut.NumBitsDeviceSel), line:5:27, endln:5:43 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/AlwaysNoElab/dut.sv, line:1:1, endln:12:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/AlwaysNoElab/dut.sv, line:1:1, endln:12:10 |vpiTypespec: \_int_typespec: , line:5:14, endln:5:26 |vpiParent: @@ -1204,7 +1204,7 @@ design: (work@dut) |vpiParamAssign: \_param_assign: , line:2:17, endln:2:30 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/AlwaysNoElab/dut.sv, line:1:1, endln:12:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/AlwaysNoElab/dut.sv, line:1:1, endln:12:10 |vpiRhs: \_constant: , line:2:29, endln:2:30 |vpiDecompile:3 @@ -1216,7 +1216,7 @@ design: (work@dut) |vpiParamAssign: \_param_assign: , line:5:27, endln:5:83 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/AlwaysNoElab/dut.sv, line:1:1, endln:12:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/AlwaysNoElab/dut.sv, line:1:1, endln:12:10 |vpiRhs: \_constant: , line:5:46, endln:5:83 |vpiDecompile:2 @@ -1233,7 +1233,7 @@ design: (work@dut) |vpiProcess: \_always: , line:8:3, endln:10:6 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/AlwaysNoElab/dut.sv, line:1:1, endln:12:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/AlwaysNoElab/dut.sv, line:1:1, endln:12:10 |vpiStmt: \_begin: (work@dut), line:8:15, endln:10:6 |vpiParent: diff --git a/tests/ArianeElab/ArianeElab.log b/tests/ArianeElab/ArianeElab.log index c6e114b11d..a413620ac3 100644 --- a/tests/ArianeElab/ArianeElab.log +++ b/tests/ArianeElab/ArianeElab.log @@ -20248,7 +20248,7 @@ logic_net 13 logic_typespec 1690 logic_var 98 long_int_typespec 4 -module 46 +module_inst 46 operation 2288 package 9 packed_array_typespec 102 @@ -20305,7 +20305,7 @@ logic_net 13 logic_typespec 1690 logic_var 206 long_int_typespec 4 -module 50 +module_inst 50 operation 3690 package 9 packed_array_typespec 102 @@ -69188,7 +69188,7 @@ design: (work@top) |vpiTypespec: \_struct_typespec: (ariane_pkg::ariane_cfg_t), line:684:13, endln:684:19 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 |vpiName:ariane_pkg::ariane_cfg_t |vpiInstance: \_package: ariane_pkg (ariane_pkg::), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:674:1, endln:1483:11 @@ -72750,7 +72750,7 @@ design: (work@top) |vpiTypedef: \_struct_typespec: (ariane_pkg::amo_req_t), line:1337:13, endln:1337:19 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 |vpiName:ariane_pkg::amo_req_t |vpiInstance: \_package: ariane_pkg (ariane_pkg::), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:674:1, endln:1483:11 @@ -72779,7 +72779,7 @@ design: (work@top) |vpiTypespec: \_enum_typespec: (ariane_pkg::amo_t), line:1265:5, endln:1280:13 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 |vpiName:ariane_pkg::amo_t |vpiInstance: \_package: ariane_pkg (ariane_pkg::), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:674:1, endln:1483:11 @@ -73005,7 +73005,7 @@ design: (work@top) |vpiTypedef: \_struct_typespec: (ariane_pkg::amo_resp_t), line:1346:13, endln:1346:19 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 |vpiName:ariane_pkg::amo_resp_t |vpiInstance: \_package: ariane_pkg (ariane_pkg::), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:674:1, endln:1483:11 @@ -73069,7 +73069,7 @@ design: (work@top) |vpiTypedef: \_struct_typespec: (ariane_pkg::bht_prediction_t), line:994:13, endln:994:19 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 |vpiName:ariane_pkg::bht_prediction_t |vpiInstance: \_package: ariane_pkg (ariane_pkg::), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:674:1, endln:1483:11 @@ -73109,7 +73109,7 @@ design: (work@top) |vpiTypedef: \_struct_typespec: (ariane_pkg::bht_update_t), line:988:13, endln:988:19 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 |vpiName:ariane_pkg::bht_update_t |vpiInstance: \_package: ariane_pkg (ariane_pkg::), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:674:1, endln:1483:11 @@ -73185,7 +73185,7 @@ design: (work@top) |vpiTypedef: \_struct_typespec: (ariane_pkg::bp_resolve_t), line:955:13, endln:955:19 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 |vpiName:ariane_pkg::bp_resolve_t |vpiInstance: \_package: ariane_pkg (ariane_pkg::), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:674:1, endln:1483:11 @@ -73318,7 +73318,7 @@ design: (work@top) |vpiTypespec: \_enum_typespec: (ariane_pkg::cf_t), line:943:5, endln:949:12 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 |vpiName:ariane_pkg::cf_t |vpiInstance: \_package: ariane_pkg (ariane_pkg::), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:674:1, endln:1483:11 @@ -73382,7 +73382,7 @@ design: (work@top) |vpiTypedef: \_struct_typespec: (ariane_pkg::branchpredict_sbe_t), line:967:13, endln:967:19 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 |vpiName:ariane_pkg::branchpredict_sbe_t |vpiInstance: \_package: ariane_pkg (ariane_pkg::), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:674:1, endln:1483:11 @@ -73438,7 +73438,7 @@ design: (work@top) |vpiTypedef: \_struct_typespec: (ariane_pkg::btb_prediction_t), line:978:13, endln:978:19 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 |vpiName:ariane_pkg::btb_prediction_t |vpiInstance: \_package: ariane_pkg (ariane_pkg::), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:674:1, endln:1483:11 @@ -73498,7 +73498,7 @@ design: (work@top) |vpiTypedef: \_struct_typespec: (ariane_pkg::btb_update_t), line:972:13, endln:972:19 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 |vpiName:ariane_pkg::btb_update_t |vpiInstance: \_package: ariane_pkg (ariane_pkg::), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:674:1, endln:1483:11 @@ -73596,7 +73596,7 @@ design: (work@top) |vpiTypedef: \_struct_typespec: (ariane_pkg::dcache_req_i_t), line:1352:13, endln:1352:19 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 |vpiName:ariane_pkg::dcache_req_i_t |vpiInstance: \_package: ariane_pkg (ariane_pkg::), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:674:1, endln:1483:11 @@ -73848,7 +73848,7 @@ design: (work@top) |vpiTypedef: \_struct_typespec: (ariane_pkg::dcache_req_o_t), line:1364:13, endln:1364:19 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 |vpiName:ariane_pkg::dcache_req_o_t |vpiInstance: \_package: ariane_pkg (ariane_pkg::), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:674:1, endln:1483:11 @@ -73924,7 +73924,7 @@ design: (work@top) |vpiTypedef: \_struct_typespec: (ariane_pkg::exception_t), line:936:13, endln:936:19 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 |vpiName:ariane_pkg::exception_t |vpiInstance: \_package: ariane_pkg (ariane_pkg::), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:674:1, endln:1483:11 @@ -73972,7 +73972,7 @@ design: (work@top) |vpiTypedef: \_struct_typespec: (ariane_pkg::fetch_entry_t), line:1229:13, endln:1229:19 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 |vpiName:ariane_pkg::fetch_entry_t |vpiInstance: \_package: ariane_pkg (ariane_pkg::), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:674:1, endln:1483:11 @@ -74076,7 +74076,7 @@ design: (work@top) |vpiTypedef: \_enum_typespec: (ariane_pkg::frontend_exception_t), line:1295:5, endln:1299:28 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 |vpiName:ariane_pkg::frontend_exception_t |vpiInstance: \_package: ariane_pkg (ariane_pkg::), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:674:1, endln:1483:11 @@ -74123,7 +74123,7 @@ design: (work@top) |vpiTypedef: \_struct_typespec: (ariane_pkg::fu_data_t), line:1123:13, endln:1123:19 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 |vpiName:ariane_pkg::fu_data_t |vpiInstance: \_package: ariane_pkg (ariane_pkg::), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:674:1, endln:1483:11 @@ -74136,7 +74136,7 @@ design: (work@top) |vpiTypespec: \_enum_typespec: (ariane_pkg::fu_t), line:999:5, endln:1009:12 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 |vpiName:ariane_pkg::fu_t |vpiInstance: \_package: ariane_pkg (ariane_pkg::), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:674:1, endln:1483:11 @@ -74229,7 +74229,7 @@ design: (work@top) |vpiTypespec: \_enum_typespec: (ariane_pkg::fu_op), line:1085:5, endln:1121:38 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 |vpiName:ariane_pkg::fu_op |vpiInstance: \_package: ariane_pkg (ariane_pkg::), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:674:1, endln:1483:11 @@ -75071,7 +75071,7 @@ design: (work@top) |vpiTypedef: \_struct_typespec: (ariane_pkg::icache_areq_i_t), line:1305:13, endln:1305:19 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 |vpiName:ariane_pkg::icache_areq_i_t |vpiInstance: \_package: ariane_pkg (ariane_pkg::), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:674:1, endln:1483:11 @@ -75143,7 +75143,7 @@ design: (work@top) |vpiTypedef: \_struct_typespec: (ariane_pkg::icache_areq_o_t), line:1311:13, endln:1311:19 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 |vpiName:ariane_pkg::icache_areq_o_t |vpiInstance: \_package: ariane_pkg (ariane_pkg::), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:674:1, endln:1483:11 @@ -75203,7 +75203,7 @@ design: (work@top) |vpiTypedef: \_struct_typespec: (ariane_pkg::icache_dreq_i_t), line:1317:13, endln:1317:19 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 |vpiName:ariane_pkg::icache_dreq_i_t |vpiInstance: \_package: ariane_pkg (ariane_pkg::), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:674:1, endln:1483:11 @@ -75311,7 +75311,7 @@ design: (work@top) |vpiTypedef: \_struct_typespec: (ariane_pkg::icache_dreq_o_t), line:1325:13, endln:1325:19 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 |vpiName:ariane_pkg::icache_dreq_o_t |vpiInstance: \_package: ariane_pkg (ariane_pkg::), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:674:1, endln:1483:11 @@ -75435,7 +75435,7 @@ design: (work@top) |vpiTypedef: \_struct_typespec: (ariane_pkg::irq_ctrl_t), line:1018:13, endln:1018:19 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 |vpiName:ariane_pkg::irq_ctrl_t |vpiInstance: \_package: ariane_pkg (ariane_pkg::), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:674:1, endln:1483:11 @@ -75511,7 +75511,7 @@ design: (work@top) |vpiTypedef: \_struct_typespec: (ariane_pkg::lsu_ctrl_t), line:1214:13, endln:1214:19 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 |vpiName:ariane_pkg::lsu_ctrl_t |vpiInstance: \_package: ariane_pkg (ariane_pkg::), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:674:1, endln:1483:11 @@ -75719,7 +75719,7 @@ design: (work@top) |vpiTypedef: \_struct_typespec: (ariane_pkg::ras_t), line:983:13, endln:983:19 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 |vpiName:ariane_pkg::ras_t |vpiInstance: \_package: ariane_pkg (ariane_pkg::), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:674:1, endln:1483:11 @@ -75779,7 +75779,7 @@ design: (work@top) |vpiTypedef: \_struct_typespec: (ariane_pkg::scoreboard_entry_t), line:1239:13, endln:1239:19 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 |vpiName:ariane_pkg::scoreboard_entry_t |vpiInstance: \_package: ariane_pkg (ariane_pkg::), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:674:1, endln:1483:11 @@ -76107,7 +76107,7 @@ design: (work@top) |vpiTypedef: \_struct_typespec: (ariane_pkg::tlb_update_t), line:1282:13, endln:1282:19 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 |vpiName:ariane_pkg::tlb_update_t |vpiInstance: \_package: ariane_pkg (ariane_pkg::), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:674:1, endln:1483:11 @@ -89503,14 +89503,14 @@ design: (work@top) |vpiInstance: \_package: fpnew_pkg (fpnew_pkg::), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1485:1, endln:1955:11 |uhdmallModules: -\_module: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2058:1, endln:2067:10 +\_module_inst: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2058:1, endln:2067:10 |vpiParent: \_design: (work@top) |vpiFullName:work@ariane |vpiParameter: \_parameter: (work@ariane.ARIANE_MARCHID), line:855:30, endln:855:44 |vpiParent: - \_module: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2058:1, endln:2067:10 + \_module_inst: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2058:1, endln:2067:10 |vpiTypespec: \_logic_typespec: (xlen_t), line:30:13, endln:30:29 |vpiParent: @@ -89545,7 +89545,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@ariane.ASID_WIDTH), line:782:16, endln:782:26 |vpiParent: - \_module: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2058:1, endln:2067:10 + \_module_inst: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2058:1, endln:2067:10 |INT:16 |vpiTypespec: \_int_typespec: @@ -89558,7 +89558,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@ariane.ArianeDefaultConfig), line:706:29, endln:706:48 |vpiParent: - \_module: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2058:1, endln:2067:10 + \_module_inst: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2058:1, endln:2067:10 |vpiTypespec: \_struct_typespec: (ariane_pkg::ariane_cfg_t), line:684:13, endln:684:19 |vpiParent: @@ -90095,7 +90095,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@ariane.BITS_SATURATION_COUNTER), line:783:16, endln:783:39 |vpiParent: - \_module: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2058:1, endln:2067:10 + \_module_inst: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2058:1, endln:2067:10 |UINT:2 |vpiTypespec: \_int_typespec: @@ -90108,7 +90108,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@ariane.CONFIG_L1D_SIZE), line:1075:27, endln:1075:42 |vpiParent: - \_module: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2058:1, endln:2067:10 + \_module_inst: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2058:1, endln:2067:10 |INT:32768 |vpiTypespec: \_int_typespec: , line:1075:14, endln:1075:26 @@ -90123,7 +90123,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@ariane.CONFIG_L1I_SIZE), line:1069:27, endln:1069:42 |vpiParent: - \_module: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2058:1, endln:2067:10 + \_module_inst: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2058:1, endln:2067:10 |INT:16384 |vpiTypespec: \_int_typespec: , line:1069:14, endln:1069:26 @@ -90138,7 +90138,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@ariane.DCACHE_INDEX_WIDTH), line:1077:29, endln:1077:47 |vpiParent: - \_module: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2058:1, endln:2067:10 + \_module_inst: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2058:1, endln:2067:10 |UINT:12 |vpiTypespec: \_int_typespec: , line:1077:16, endln:1077:28 @@ -90153,7 +90153,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@ariane.DCACHE_LINE_WIDTH), line:1079:29, endln:1079:46 |vpiParent: - \_module: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2058:1, endln:2067:10 + \_module_inst: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2058:1, endln:2067:10 |UINT:128 |vpiTypespec: \_int_typespec: , line:1079:16, endln:1079:28 @@ -90168,7 +90168,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@ariane.DCACHE_SET_ASSOC), line:1076:28, endln:1076:44 |vpiParent: - \_module: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2058:1, endln:2067:10 + \_module_inst: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2058:1, endln:2067:10 |UINT:8 |vpiTypespec: \_int_typespec: , line:1076:15, endln:1076:27 @@ -90183,7 +90183,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@ariane.DCACHE_TAG_WIDTH), line:1078:29, endln:1078:45 |vpiParent: - \_module: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2058:1, endln:2067:10 + \_module_inst: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2058:1, endln:2067:10 |INT:44 |vpiTypespec: \_int_typespec: , line:1078:16, endln:1078:28 @@ -90198,7 +90198,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@ariane.DEPTH_COMMIT), line:804:29, endln:804:41 |vpiParent: - \_module: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2058:1, endln:2067:10 + \_module_inst: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2058:1, endln:2067:10 |UINT:8 |vpiTypespec: \_int_typespec: , line:804:16, endln:804:28 @@ -90213,7 +90213,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@ariane.DEPTH_SPEC), line:795:29, endln:795:39 |vpiParent: - \_module: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2058:1, endln:2067:10 + \_module_inst: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2058:1, endln:2067:10 |UINT:4 |vpiTypespec: \_int_typespec: , line:795:16, endln:795:28 @@ -90228,7 +90228,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@ariane.DebugHartInfo), line:874:31, endln:874:44 |vpiParent: - \_module: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2058:1, endln:2067:10 + \_module_inst: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2058:1, endln:2067:10 |vpiTypespec: \_unsupported_typespec: (dm::hartinfo_t), line:874:16, endln:874:20 |vpiParent: @@ -90243,7 +90243,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@ariane.ENABLE_CYCLE_COUNT), line:900:20, endln:900:38 |vpiParent: - \_module: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2058:1, endln:2067:10 + \_module_inst: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2058:1, endln:2067:10 |BIN:1 |vpiTypespec: \_bit_typespec: , line:900:16, endln:900:19 @@ -90259,7 +90259,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@ariane.ENABLE_RENAME), line:786:16, endln:786:29 |vpiParent: - \_module: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2058:1, endln:2067:10 + \_module_inst: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2058:1, endln:2067:10 |BIN:0 |vpiTypespec: \_int_typespec: @@ -90286,7 +90286,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@ariane.ENABLE_SPIKE_COMMIT_LOG), line:884:20, endln:884:43 |vpiParent: - \_module: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2058:1, endln:2067:10 + \_module_inst: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2058:1, endln:2067:10 |BIN:1 |vpiTypespec: \_bit_typespec: , line:884:16, endln:884:19 @@ -90302,7 +90302,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@ariane.ENABLE_WFI), line:901:20, endln:901:30 |vpiParent: - \_module: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2058:1, endln:2067:10 + \_module_inst: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2058:1, endln:2067:10 |BIN:1 |vpiTypespec: \_bit_typespec: , line:901:16, endln:901:19 @@ -90318,7 +90318,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@ariane.EXC_OFF_RST), line:1011:16, endln:1011:27 |vpiParent: - \_module: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2058:1, endln:2067:10 + \_module_inst: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2058:1, endln:2067:10 |HEX:80 |vpiTypespec: \_int_typespec: @@ -90345,7 +90345,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@ariane.FETCH_FIFO_DEPTH), line:929:29, endln:929:45 |vpiParent: - \_module: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2058:1, endln:2067:10 + \_module_inst: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2058:1, endln:2067:10 |UINT:4 |vpiTypespec: \_int_typespec: , line:929:16, endln:929:28 @@ -90360,7 +90360,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@ariane.FETCH_WIDTH), line:930:29, endln:930:40 |vpiParent: - \_module: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2058:1, endln:2067:10 + \_module_inst: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2058:1, endln:2067:10 |UINT:32 |vpiTypespec: \_int_typespec: , line:930:16, endln:930:28 @@ -90375,7 +90375,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@ariane.FLEN), line:839:16, endln:839:20 |vpiParent: - \_module: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2058:1, endln:2067:10 + \_module_inst: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2058:1, endln:2067:10 |INT:64 |vpiTypespec: \_int_typespec: @@ -90388,7 +90388,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@ariane.FP_PRESENT), line:836:20, endln:836:30 |vpiParent: - \_module: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2058:1, endln:2067:10 + \_module_inst: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2058:1, endln:2067:10 |UINT:1 |vpiTypespec: \_bit_typespec: , line:836:16, endln:836:19 @@ -90404,7 +90404,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@ariane.ICACHE_INDEX_WIDTH), line:1071:29, endln:1071:47 |vpiParent: - \_module: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2058:1, endln:2067:10 + \_module_inst: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2058:1, endln:2067:10 |UINT:12 |vpiTypespec: \_int_typespec: , line:1071:16, endln:1071:28 @@ -90419,7 +90419,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@ariane.ICACHE_LINE_WIDTH), line:1073:29, endln:1073:46 |vpiParent: - \_module: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2058:1, endln:2067:10 + \_module_inst: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2058:1, endln:2067:10 |UINT:128 |vpiTypespec: \_int_typespec: , line:1073:16, endln:1073:28 @@ -90434,7 +90434,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@ariane.ICACHE_SET_ASSOC), line:1070:29, endln:1070:45 |vpiParent: - \_module: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2058:1, endln:2067:10 + \_module_inst: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2058:1, endln:2067:10 |UINT:4 |vpiTypespec: \_int_typespec: , line:1070:16, endln:1070:28 @@ -90449,7 +90449,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@ariane.ICACHE_TAG_WIDTH), line:1072:29, endln:1072:45 |vpiParent: - \_module: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2058:1, endln:2067:10 + \_module_inst: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2058:1, endln:2067:10 |INT:44 |vpiTypespec: \_int_typespec: , line:1072:16, endln:1072:28 @@ -90464,7 +90464,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@ariane.INSTR_PER_FETCH), line:932:29, endln:932:44 |vpiParent: - \_module: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2058:1, endln:2067:10 + \_module_inst: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2058:1, endln:2067:10 |INT:2 |vpiTypespec: \_int_typespec: , line:932:16, endln:932:28 @@ -90479,7 +90479,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@ariane.INVALIDATE_ON_FLUSH), line:890:22, endln:890:41 |vpiParent: - \_module: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2058:1, endln:2067:10 + \_module_inst: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2058:1, endln:2067:10 |BIN:1 |vpiTypespec: \_logic_typespec: , line:890:16, endln:890:21 @@ -90494,7 +90494,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@ariane.ISA_CODE), line:857:30, endln:857:38 |vpiParent: - \_module: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2058:1, endln:2067:10 + \_module_inst: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2058:1, endln:2067:10 |vpiTypespec: \_logic_typespec: (xlen_t), line:30:13, endln:30:29 |vpiParent: @@ -90529,7 +90529,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@ariane.ISSUE_WIDTH), line:788:16, endln:788:27 |vpiParent: - \_module: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2058:1, endln:2067:10 + \_module_inst: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2058:1, endln:2067:10 |UINT:1 |vpiTypespec: \_int_typespec: @@ -90542,7 +90542,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@ariane.LAT_COMP_FP16), line:827:29, endln:827:42 |vpiParent: - \_module: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2058:1, endln:2067:10 + \_module_inst: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2058:1, endln:2067:10 |DEC:1 |vpiTypespec: \_int_typespec: , line:827:16, endln:827:28 @@ -90557,7 +90557,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@ariane.LAT_COMP_FP16ALT), line:828:29, endln:828:45 |vpiParent: - \_module: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2058:1, endln:2067:10 + \_module_inst: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2058:1, endln:2067:10 |DEC:1 |vpiTypespec: \_int_typespec: , line:828:16, endln:828:28 @@ -90572,7 +90572,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@ariane.LAT_COMP_FP32), line:825:29, endln:825:42 |vpiParent: - \_module: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2058:1, endln:2067:10 + \_module_inst: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2058:1, endln:2067:10 |DEC:2 |vpiTypespec: \_int_typespec: , line:825:16, endln:825:28 @@ -90587,7 +90587,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@ariane.LAT_COMP_FP64), line:826:29, endln:826:42 |vpiParent: - \_module: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2058:1, endln:2067:10 + \_module_inst: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2058:1, endln:2067:10 |DEC:3 |vpiTypespec: \_int_typespec: , line:826:16, endln:826:28 @@ -90602,7 +90602,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@ariane.LAT_COMP_FP8), line:829:29, endln:829:41 |vpiParent: - \_module: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2058:1, endln:2067:10 + \_module_inst: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2058:1, endln:2067:10 |DEC:1 |vpiTypespec: \_int_typespec: , line:829:16, endln:829:28 @@ -90617,7 +90617,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@ariane.LAT_CONV), line:832:29, endln:832:37 |vpiParent: - \_module: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2058:1, endln:2067:10 + \_module_inst: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2058:1, endln:2067:10 |DEC:2 |vpiTypespec: \_int_typespec: , line:832:16, endln:832:28 @@ -90632,7 +90632,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@ariane.LAT_DIVSQRT), line:830:29, endln:830:40 |vpiParent: - \_module: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2058:1, endln:2067:10 + \_module_inst: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2058:1, endln:2067:10 |DEC:2 |vpiTypespec: \_int_typespec: , line:830:16, endln:830:28 @@ -90647,7 +90647,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@ariane.LAT_NONCOMP), line:831:29, endln:831:40 |vpiParent: - \_module: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2058:1, endln:2067:10 + \_module_inst: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2058:1, endln:2067:10 |DEC:1 |vpiTypespec: \_int_typespec: , line:831:16, endln:831:28 @@ -90662,7 +90662,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@ariane.MachineIrq), line:1014:16, endln:1014:26 |vpiParent: - \_module: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2058:1, endln:2067:10 + \_module_inst: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2058:1, endln:2067:10 |UINT:0 |vpiTypespec: \_int_typespec: @@ -90675,7 +90675,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@ariane.NR_COMMIT_PORTS), line:784:16, endln:784:31 |vpiParent: - \_module: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2058:1, endln:2067:10 + \_module_inst: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2058:1, endln:2067:10 |UINT:2 |vpiTypespec: \_int_typespec: @@ -90688,7 +90688,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@ariane.NR_LOAD_PIPE_REGS), line:791:29, endln:791:46 |vpiParent: - \_module: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2058:1, endln:2067:10 + \_module_inst: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2058:1, endln:2067:10 |UINT:1 |vpiTypespec: \_int_typespec: , line:791:16, endln:791:28 @@ -90703,7 +90703,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@ariane.NR_SB_ENTRIES), line:779:16, endln:779:29 |vpiParent: - \_module: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2058:1, endln:2067:10 + \_module_inst: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2058:1, endln:2067:10 |UINT:8 |vpiTypespec: \_int_typespec: @@ -90716,7 +90716,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@ariane.NR_STORE_PIPE_REGS), line:792:29, endln:792:47 |vpiParent: - \_module: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2058:1, endln:2067:10 + \_module_inst: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2058:1, endln:2067:10 |UINT:0 |vpiTypespec: \_int_typespec: , line:792:16, endln:792:28 @@ -90731,7 +90731,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@ariane.NR_WB_PORTS), line:871:16, endln:871:27 |vpiParent: - \_module: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2058:1, endln:2067:10 + \_module_inst: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2058:1, endln:2067:10 |UINT:4 |vpiTypespec: \_int_typespec: @@ -90744,7 +90744,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@ariane.NSX), line:846:20, endln:846:23 |vpiParent: - \_module: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2058:1, endln:2067:10 + \_module_inst: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2058:1, endln:2067:10 |UINT:0 |vpiTypespec: \_bit_typespec: , line:846:16, endln:846:19 @@ -90760,7 +90760,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@ariane.NrMaxRules), line:682:16, endln:682:26 |vpiParent: - \_module: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2058:1, endln:2067:10 + \_module_inst: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2058:1, endln:2067:10 |UINT:16 |vpiTypespec: \_int_typespec: @@ -90773,7 +90773,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@ariane.PPN4K_WIDTH), line:1293:16, endln:1293:27 |vpiParent: - \_module: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2058:1, endln:2067:10 + \_module_inst: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2058:1, endln:2067:10 |UINT:38 |vpiTypespec: \_int_typespec: @@ -90786,7 +90786,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@ariane.REG_ADDR_SIZE), line:870:16, endln:870:29 |vpiParent: - \_module: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2058:1, endln:2067:10 + \_module_inst: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2058:1, endln:2067:10 |UINT:6 |vpiTypespec: \_int_typespec: @@ -90799,7 +90799,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@ariane.RVA), line:816:20, endln:816:23 |vpiParent: - \_module: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2058:1, endln:2067:10 + \_module_inst: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2058:1, endln:2067:10 |BIN:1 |vpiTypespec: \_bit_typespec: , line:816:16, endln:816:19 @@ -90815,7 +90815,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@ariane.RVD), line:814:20, endln:814:23 |vpiParent: - \_module: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2058:1, endln:2067:10 + \_module_inst: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2058:1, endln:2067:10 |INT:1 |vpiTypespec: \_bit_typespec: , line:814:16, endln:814:19 @@ -90831,7 +90831,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@ariane.RVF), line:813:20, endln:813:23 |vpiParent: - \_module: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2058:1, endln:2067:10 + \_module_inst: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2058:1, endln:2067:10 |INT:1 |vpiTypespec: \_bit_typespec: , line:813:16, endln:813:19 @@ -90847,7 +90847,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@ariane.RVFVEC), line:848:20, endln:848:26 |vpiParent: - \_module: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2058:1, endln:2067:10 + \_module_inst: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2058:1, endln:2067:10 |UINT:0 |vpiTypespec: \_bit_typespec: , line:848:16, endln:848:19 @@ -90863,7 +90863,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@ariane.SMODE_STATUS_READ_MASK), line:905:29, endln:905:51 |vpiParent: - \_module: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2058:1, endln:2067:10 + \_module_inst: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2058:1, endln:2067:10 |vpiTypespec: \_logic_typespec: , line:905:16, endln:905:28 |vpiParent: @@ -90897,7 +90897,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@ariane.SMODE_STATUS_WRITE_MASK), line:918:29, endln:918:52 |vpiParent: - \_module: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2058:1, endln:2067:10 + \_module_inst: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2058:1, endln:2067:10 |vpiTypespec: \_logic_typespec: , line:918:16, endln:918:28 |vpiParent: @@ -90931,7 +90931,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@ariane.SupervisorIrq), line:1013:16, endln:1013:29 |vpiParent: - \_module: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2058:1, endln:2067:10 + \_module_inst: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2058:1, endln:2067:10 |UINT:1 |vpiTypespec: \_int_typespec: @@ -90944,7 +90944,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@ariane.TRANS_ID_BITS), line:780:16, endln:780:29 |vpiParent: - \_module: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2058:1, endln:2067:10 + \_module_inst: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2058:1, endln:2067:10 |UINT:3 |vpiTypespec: \_int_typespec: @@ -90957,7 +90957,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@ariane.XF16), line:819:20, endln:819:24 |vpiParent: - \_module: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2058:1, endln:2067:10 + \_module_inst: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2058:1, endln:2067:10 |BIN:0 |vpiTypespec: \_bit_typespec: , line:819:16, endln:819:19 @@ -90973,7 +90973,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@ariane.XF16ALT), line:820:20, endln:820:27 |vpiParent: - \_module: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2058:1, endln:2067:10 + \_module_inst: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2058:1, endln:2067:10 |BIN:0 |vpiTypespec: \_bit_typespec: , line:820:16, endln:820:19 @@ -90989,7 +90989,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@ariane.XF16ALTVEC), line:850:20, endln:850:30 |vpiParent: - \_module: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2058:1, endln:2067:10 + \_module_inst: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2058:1, endln:2067:10 |UINT:0 |vpiTypespec: \_bit_typespec: , line:850:16, endln:850:19 @@ -91005,7 +91005,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@ariane.XF16VEC), line:849:20, endln:849:27 |vpiParent: - \_module: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2058:1, endln:2067:10 + \_module_inst: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2058:1, endln:2067:10 |UINT:0 |vpiTypespec: \_bit_typespec: , line:849:16, endln:849:19 @@ -91021,7 +91021,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@ariane.XF8), line:821:20, endln:821:23 |vpiParent: - \_module: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2058:1, endln:2067:10 + \_module_inst: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2058:1, endln:2067:10 |BIN:0 |vpiTypespec: \_bit_typespec: , line:821:16, endln:821:19 @@ -91037,7 +91037,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@ariane.XF8VEC), line:851:20, endln:851:26 |vpiParent: - \_module: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2058:1, endln:2067:10 + \_module_inst: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2058:1, endln:2067:10 |UINT:0 |vpiTypespec: \_bit_typespec: , line:851:16, endln:851:19 @@ -91053,7 +91053,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@ariane.XFVEC), line:822:20, endln:822:25 |vpiParent: - \_module: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2058:1, endln:2067:10 + \_module_inst: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2058:1, endln:2067:10 |BIN:0 |vpiTypespec: \_bit_typespec: , line:822:16, endln:822:19 @@ -91069,7 +91069,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@ariane.ZERO_TVAL), line:902:20, endln:902:29 |vpiParent: - \_module: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2058:1, endln:2067:10 + \_module_inst: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2058:1, endln:2067:10 |BIN:0 |vpiTypespec: \_bit_typespec: , line:902:16, endln:902:19 @@ -91085,7 +91085,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@ariane.ArianeCfg), line:2059:38, endln:2059:47 |vpiParent: - \_module: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2058:1, endln:2067:10 + \_module_inst: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2058:1, endln:2067:10 |vpiTypespec: \_struct_typespec: (ariane_pkg::ariane_cfg_t), line:684:13, endln:684:19 |vpiName:ArianeCfg @@ -91093,7 +91093,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:682:16, endln:682:31 |vpiParent: - \_module: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2058:1, endln:2067:10 + \_module_inst: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2058:1, endln:2067:10 |vpiRhs: \_constant: , line:682:29, endln:682:31 |vpiParent: @@ -91122,7 +91122,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:706:29, endln:728:6 |vpiParent: - \_module: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2058:1, endln:2067:10 + \_module_inst: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2058:1, endln:2067:10 |vpiRhs: \_operation: , line:706:51, endln:728:6 |vpiParent: @@ -91934,7 +91934,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:779:16, endln:779:33 |vpiParent: - \_module: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2058:1, endln:2067:10 + \_module_inst: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2058:1, endln:2067:10 |vpiRhs: \_constant: , line:779:32, endln:779:33 |vpiParent: @@ -91963,7 +91963,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:780:16, endln:780:53 |vpiParent: - \_module: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2058:1, endln:2067:10 + \_module_inst: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2058:1, endln:2067:10 |vpiRhs: \_constant: , line:780:32, endln:780:53 |vpiParent: @@ -91992,7 +91992,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:782:16, endln:782:60 |vpiParent: - \_module: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2058:1, endln:2067:10 + \_module_inst: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2058:1, endln:2067:10 |vpiRhs: \_constant: , line:782:32, endln:782:51 |vpiParent: @@ -92021,7 +92021,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:783:16, endln:783:43 |vpiParent: - \_module: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2058:1, endln:2067:10 + \_module_inst: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2058:1, endln:2067:10 |vpiRhs: \_constant: , line:783:42, endln:783:43 |vpiParent: @@ -92050,7 +92050,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:784:16, endln:784:35 |vpiParent: - \_module: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2058:1, endln:2067:10 + \_module_inst: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2058:1, endln:2067:10 |vpiRhs: \_constant: , line:784:34, endln:784:35 |vpiParent: @@ -92079,7 +92079,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:786:16, endln:786:36 |vpiParent: - \_module: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2058:1, endln:2067:10 + \_module_inst: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2058:1, endln:2067:10 |vpiRhs: \_constant: , line:786:32, endln:786:36 |vpiParent: @@ -92136,7 +92136,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:788:16, endln:788:31 |vpiParent: - \_module: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2058:1, endln:2067:10 + \_module_inst: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2058:1, endln:2067:10 |vpiRhs: \_constant: , line:788:30, endln:788:31 |vpiParent: @@ -92165,7 +92165,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:791:29, endln:791:50 |vpiParent: - \_module: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2058:1, endln:2067:10 + \_module_inst: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2058:1, endln:2067:10 |vpiRhs: \_constant: , line:791:49, endln:791:50 |vpiParent: @@ -92198,7 +92198,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:792:29, endln:792:51 |vpiParent: - \_module: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2058:1, endln:2067:10 + \_module_inst: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2058:1, endln:2067:10 |vpiRhs: \_constant: , line:792:50, endln:792:51 |vpiParent: @@ -92231,7 +92231,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:795:29, endln:795:45 |vpiParent: - \_module: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2058:1, endln:2067:10 + \_module_inst: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2058:1, endln:2067:10 |vpiRhs: \_constant: , line:795:44, endln:795:45 |vpiParent: @@ -92264,7 +92264,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:804:29, endln:804:45 |vpiParent: - \_module: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2058:1, endln:2067:10 + \_module_inst: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2058:1, endln:2067:10 |vpiRhs: \_constant: , line:804:44, endln:804:45 |vpiParent: @@ -92297,7 +92297,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:813:20, endln:813:42 |vpiParent: - \_module: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2058:1, endln:2067:10 + \_module_inst: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2058:1, endln:2067:10 |vpiRhs: \_constant: , line:813:26, endln:813:33 |vpiParent: @@ -92332,7 +92332,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:814:20, endln:814:42 |vpiParent: - \_module: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2058:1, endln:2067:10 + \_module_inst: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2058:1, endln:2067:10 |vpiRhs: \_constant: , line:814:26, endln:814:33 |vpiParent: @@ -92367,7 +92367,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:816:20, endln:816:30 |vpiParent: - \_module: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2058:1, endln:2067:10 + \_module_inst: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2058:1, endln:2067:10 |vpiRhs: \_constant: , line:816:26, endln:816:30 |vpiParent: @@ -92402,7 +92402,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:819:20, endln:819:34 |vpiParent: - \_module: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2058:1, endln:2067:10 + \_module_inst: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2058:1, endln:2067:10 |vpiRhs: \_constant: , line:819:30, endln:819:34 |vpiParent: @@ -92437,7 +92437,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:820:20, endln:820:34 |vpiParent: - \_module: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2058:1, endln:2067:10 + \_module_inst: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2058:1, endln:2067:10 |vpiRhs: \_constant: , line:820:30, endln:820:34 |vpiParent: @@ -92472,7 +92472,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:821:20, endln:821:34 |vpiParent: - \_module: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2058:1, endln:2067:10 + \_module_inst: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2058:1, endln:2067:10 |vpiRhs: \_constant: , line:821:30, endln:821:34 |vpiParent: @@ -92507,7 +92507,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:822:20, endln:822:34 |vpiParent: - \_module: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2058:1, endln:2067:10 + \_module_inst: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2058:1, endln:2067:10 |vpiRhs: \_constant: , line:822:30, endln:822:34 |vpiParent: @@ -92542,7 +92542,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:825:29, endln:825:51 |vpiParent: - \_module: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2058:1, endln:2067:10 + \_module_inst: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2058:1, endln:2067:10 |vpiRhs: \_constant: , line:825:48, endln:825:51 |vpiParent: @@ -92575,7 +92575,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:826:29, endln:826:51 |vpiParent: - \_module: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2058:1, endln:2067:10 + \_module_inst: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2058:1, endln:2067:10 |vpiRhs: \_constant: , line:826:48, endln:826:51 |vpiParent: @@ -92608,7 +92608,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:827:29, endln:827:51 |vpiParent: - \_module: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2058:1, endln:2067:10 + \_module_inst: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2058:1, endln:2067:10 |vpiRhs: \_constant: , line:827:48, endln:827:51 |vpiParent: @@ -92641,7 +92641,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:828:29, endln:828:51 |vpiParent: - \_module: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2058:1, endln:2067:10 + \_module_inst: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2058:1, endln:2067:10 |vpiRhs: \_constant: , line:828:48, endln:828:51 |vpiParent: @@ -92674,7 +92674,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:829:29, endln:829:51 |vpiParent: - \_module: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2058:1, endln:2067:10 + \_module_inst: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2058:1, endln:2067:10 |vpiRhs: \_constant: , line:829:48, endln:829:51 |vpiParent: @@ -92707,7 +92707,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:830:29, endln:830:51 |vpiParent: - \_module: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2058:1, endln:2067:10 + \_module_inst: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2058:1, endln:2067:10 |vpiRhs: \_constant: , line:830:48, endln:830:51 |vpiParent: @@ -92740,7 +92740,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:831:29, endln:831:51 |vpiParent: - \_module: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2058:1, endln:2067:10 + \_module_inst: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2058:1, endln:2067:10 |vpiRhs: \_constant: , line:831:48, endln:831:51 |vpiParent: @@ -92773,7 +92773,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:832:29, endln:832:51 |vpiParent: - \_module: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2058:1, endln:2067:10 + \_module_inst: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2058:1, endln:2067:10 |vpiRhs: \_constant: , line:832:48, endln:832:51 |vpiParent: @@ -92806,7 +92806,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:836:20, endln:836:65 |vpiParent: - \_module: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2058:1, endln:2067:10 + \_module_inst: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2058:1, endln:2067:10 |vpiRhs: \_constant: , line:836:33, endln:836:59 |vpiParent: @@ -92841,7 +92841,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:839:16, endln:844:27 |vpiParent: - \_module: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2058:1, endln:2067:10 + \_module_inst: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2058:1, endln:2067:10 |vpiRhs: \_constant: , line:839:26, endln:839:29 |vpiParent: @@ -92870,7 +92870,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:846:20, endln:846:54 |vpiParent: - \_module: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2058:1, endln:2067:10 + \_module_inst: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2058:1, endln:2067:10 |vpiRhs: \_constant: , line:846:26, endln:846:46 |vpiParent: @@ -92905,7 +92905,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:848:20, endln:848:58 |vpiParent: - \_module: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2058:1, endln:2067:10 + \_module_inst: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2058:1, endln:2067:10 |vpiRhs: \_constant: , line:848:33, endln:848:48 |vpiParent: @@ -92940,7 +92940,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:849:20, endln:849:58 |vpiParent: - \_module: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2058:1, endln:2067:10 + \_module_inst: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2058:1, endln:2067:10 |vpiRhs: \_constant: , line:849:33, endln:849:48 |vpiParent: @@ -92975,7 +92975,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:850:20, endln:850:58 |vpiParent: - \_module: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2058:1, endln:2067:10 + \_module_inst: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2058:1, endln:2067:10 |vpiRhs: \_constant: , line:850:33, endln:850:48 |vpiParent: @@ -93010,7 +93010,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:851:20, endln:851:57 |vpiParent: - \_module: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2058:1, endln:2067:10 + \_module_inst: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2058:1, endln:2067:10 |vpiRhs: \_constant: , line:851:33, endln:851:48 |vpiParent: @@ -93045,7 +93045,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:855:30, endln:855:78 |vpiParent: - \_module: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2058:1, endln:2067:10 + \_module_inst: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2058:1, endln:2067:10 |vpiRhs: \_operation: , line:855:47, endln:855:78 |vpiParent: @@ -93140,7 +93140,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:857:30, endln:867:86 |vpiParent: - \_module: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2058:1, endln:2067:10 + \_module_inst: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2058:1, endln:2067:10 |vpiRhs: \_operation: , line:857:41, endln:867:86 |vpiParent: @@ -93507,7 +93507,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:870:16, endln:870:33 |vpiParent: - \_module: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2058:1, endln:2067:10 + \_module_inst: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2058:1, endln:2067:10 |vpiRhs: \_constant: , line:870:32, endln:870:33 |vpiParent: @@ -93536,7 +93536,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:871:16, endln:871:31 |vpiParent: - \_module: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2058:1, endln:2067:10 + \_module_inst: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2058:1, endln:2067:10 |vpiRhs: \_constant: , line:871:30, endln:871:31 |vpiParent: @@ -93565,7 +93565,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:874:31, endln:881:48 |vpiParent: - \_module: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2058:1, endln:2067:10 + \_module_inst: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2058:1, endln:2067:10 |vpiRhs: \_operation: , line:874:47, endln:881:48 |vpiParent: @@ -93687,7 +93687,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:884:20, endln:884:50 |vpiParent: - \_module: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2058:1, endln:2067:10 + \_module_inst: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2058:1, endln:2067:10 |vpiRhs: \_constant: , line:884:46, endln:884:50 |vpiParent: @@ -93722,7 +93722,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:890:22, endln:890:48 |vpiParent: - \_module: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2058:1, endln:2067:10 + \_module_inst: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2058:1, endln:2067:10 |vpiRhs: \_constant: , line:890:44, endln:890:48 |vpiParent: @@ -93755,7 +93755,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:900:20, endln:900:45 |vpiParent: - \_module: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2058:1, endln:2067:10 + \_module_inst: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2058:1, endln:2067:10 |vpiRhs: \_constant: , line:900:41, endln:900:45 |vpiParent: @@ -93790,7 +93790,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:901:20, endln:901:37 |vpiParent: - \_module: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2058:1, endln:2067:10 + \_module_inst: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2058:1, endln:2067:10 |vpiRhs: \_constant: , line:901:33, endln:901:37 |vpiParent: @@ -93825,7 +93825,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:902:20, endln:902:36 |vpiParent: - \_module: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2058:1, endln:2067:10 + \_module_inst: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2058:1, endln:2067:10 |vpiRhs: \_constant: , line:902:32, endln:902:36 |vpiParent: @@ -93860,7 +93860,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:905:29, endln:916:71 |vpiParent: - \_module: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2058:1, endln:2067:10 + \_module_inst: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2058:1, endln:2067:10 |vpiRhs: \_operation: , line:905:54, endln:916:71 |vpiParent: @@ -94366,7 +94366,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:918:29, endln:923:73 |vpiParent: - \_module: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2058:1, endln:2067:10 + \_module_inst: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2058:1, endln:2067:10 |vpiRhs: \_operation: , line:918:55, endln:923:73 |vpiParent: @@ -94633,7 +94633,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:929:29, endln:929:50 |vpiParent: - \_module: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2058:1, endln:2067:10 + \_module_inst: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2058:1, endln:2067:10 |vpiRhs: \_constant: , line:929:49, endln:929:50 |vpiParent: @@ -94666,7 +94666,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:930:29, endln:930:51 |vpiParent: - \_module: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2058:1, endln:2067:10 + \_module_inst: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2058:1, endln:2067:10 |vpiRhs: \_constant: , line:930:49, endln:930:51 |vpiParent: @@ -94699,7 +94699,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:932:29, endln:932:63 |vpiParent: - \_module: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2058:1, endln:2067:10 + \_module_inst: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2058:1, endln:2067:10 |vpiRhs: \_constant: , line:932:47, endln:932:58 |vpiParent: @@ -94732,7 +94732,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:1011:16, endln:1011:40 |vpiParent: - \_module: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2058:1, endln:2067:10 + \_module_inst: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2058:1, endln:2067:10 |vpiRhs: \_constant: , line:1011:35, endln:1011:40 |vpiParent: @@ -94789,7 +94789,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:1013:16, endln:1013:33 |vpiParent: - \_module: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2058:1, endln:2067:10 + \_module_inst: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2058:1, endln:2067:10 |vpiRhs: \_constant: , line:1013:32, endln:1013:33 |vpiParent: @@ -94818,7 +94818,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:1014:16, endln:1014:30 |vpiParent: - \_module: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2058:1, endln:2067:10 + \_module_inst: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2058:1, endln:2067:10 |vpiRhs: \_constant: , line:1014:29, endln:1014:30 |vpiParent: @@ -94847,7 +94847,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:1069:27, endln:1069:55 |vpiParent: - \_module: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2058:1, endln:2067:10 + \_module_inst: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2058:1, endln:2067:10 |vpiRhs: \_constant: , line:1069:48, endln:1069:50 |vpiParent: @@ -94880,7 +94880,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:1070:29, endln:1070:51 |vpiParent: - \_module: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2058:1, endln:2067:10 + \_module_inst: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2058:1, endln:2067:10 |vpiRhs: \_constant: , line:1070:50, endln:1070:51 |vpiParent: @@ -94913,7 +94913,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:1071:29, endln:1071:92 |vpiParent: - \_module: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2058:1, endln:2067:10 + \_module_inst: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2058:1, endln:2067:10 |vpiRhs: \_constant: , line:1071:50, endln:1071:92 |vpiParent: @@ -94946,7 +94946,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:1072:29, endln:1072:80 |vpiParent: - \_module: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2058:1, endln:2067:10 + \_module_inst: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2058:1, endln:2067:10 |vpiRhs: \_constant: , line:1072:50, endln:1072:61 |vpiParent: @@ -94979,7 +94979,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:1073:29, endln:1073:53 |vpiParent: - \_module: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2058:1, endln:2067:10 + \_module_inst: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2058:1, endln:2067:10 |vpiRhs: \_constant: , line:1073:50, endln:1073:53 |vpiParent: @@ -95012,7 +95012,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:1075:27, endln:1075:55 |vpiParent: - \_module: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2058:1, endln:2067:10 + \_module_inst: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2058:1, endln:2067:10 |vpiRhs: \_constant: , line:1075:48, endln:1075:50 |vpiParent: @@ -95045,7 +95045,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:1076:28, endln:1076:50 |vpiParent: - \_module: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2058:1, endln:2067:10 + \_module_inst: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2058:1, endln:2067:10 |vpiRhs: \_constant: , line:1076:49, endln:1076:50 |vpiParent: @@ -95078,7 +95078,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:1077:29, endln:1077:92 |vpiParent: - \_module: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2058:1, endln:2067:10 + \_module_inst: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2058:1, endln:2067:10 |vpiRhs: \_constant: , line:1077:50, endln:1077:92 |vpiParent: @@ -95111,7 +95111,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:1078:29, endln:1078:80 |vpiParent: - \_module: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2058:1, endln:2067:10 + \_module_inst: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2058:1, endln:2067:10 |vpiRhs: \_constant: , line:1078:50, endln:1078:61 |vpiParent: @@ -95144,7 +95144,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:1079:29, endln:1079:53 |vpiParent: - \_module: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2058:1, endln:2067:10 + \_module_inst: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2058:1, endln:2067:10 |vpiRhs: \_constant: , line:1079:50, endln:1079:53 |vpiParent: @@ -95177,7 +95177,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:1293:16, endln:1293:32 |vpiParent: - \_module: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2058:1, endln:2067:10 + \_module_inst: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2058:1, endln:2067:10 |vpiRhs: \_constant: , line:1293:30, endln:1293:32 |vpiParent: @@ -95206,7 +95206,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:2059:38, endln:2059:85 |vpiParent: - \_module: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2058:1, endln:2067:10 + \_module_inst: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2058:1, endln:2067:10 |vpiRhs: \_operation: , line:2059:54, endln:2059:66 |vpiOpType:75 @@ -99250,14 +99250,14 @@ design: (work@top) |vpiInstance: \_package: ariane_pkg (ariane_pkg::), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:674:1, endln:1483:11 |uhdmallModules: -\_module: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2025:1, endln:2055:10 +\_module_inst: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2025:1, endln:2055:10 |vpiParent: \_design: (work@top) |vpiFullName:work@ex_stage |vpiParameter: \_parameter: (work@ex_stage.ARIANE_MARCHID), line:855:30, endln:855:44 |vpiParent: - \_module: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2025:1, endln:2055:10 + \_module_inst: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2025:1, endln:2055:10 |vpiTypespec: \_logic_typespec: (xlen_t), line:30:13, endln:30:29 |vpiParent: @@ -99292,7 +99292,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@ex_stage.ASID_WIDTH), line:782:16, endln:782:26 |vpiParent: - \_module: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2025:1, endln:2055:10 + \_module_inst: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2025:1, endln:2055:10 |INT:16 |vpiTypespec: \_int_typespec: @@ -99305,7 +99305,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@ex_stage.ArianeDefaultConfig), line:706:29, endln:706:48 |vpiParent: - \_module: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2025:1, endln:2055:10 + \_module_inst: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2025:1, endln:2055:10 |vpiTypespec: \_struct_typespec: (ariane_pkg::ariane_cfg_t), line:684:13, endln:684:19 |vpiParent: @@ -99842,7 +99842,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@ex_stage.BITS_SATURATION_COUNTER), line:783:16, endln:783:39 |vpiParent: - \_module: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2025:1, endln:2055:10 + \_module_inst: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2025:1, endln:2055:10 |UINT:2 |vpiTypespec: \_int_typespec: @@ -99855,7 +99855,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@ex_stage.CONFIG_L1D_SIZE), line:1075:27, endln:1075:42 |vpiParent: - \_module: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2025:1, endln:2055:10 + \_module_inst: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2025:1, endln:2055:10 |INT:32768 |vpiTypespec: \_int_typespec: , line:1075:14, endln:1075:26 @@ -99870,7 +99870,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@ex_stage.CONFIG_L1I_SIZE), line:1069:27, endln:1069:42 |vpiParent: - \_module: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2025:1, endln:2055:10 + \_module_inst: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2025:1, endln:2055:10 |INT:16384 |vpiTypespec: \_int_typespec: , line:1069:14, endln:1069:26 @@ -99885,7 +99885,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@ex_stage.DCACHE_INDEX_WIDTH), line:1077:29, endln:1077:47 |vpiParent: - \_module: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2025:1, endln:2055:10 + \_module_inst: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2025:1, endln:2055:10 |UINT:12 |vpiTypespec: \_int_typespec: , line:1077:16, endln:1077:28 @@ -99900,7 +99900,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@ex_stage.DCACHE_LINE_WIDTH), line:1079:29, endln:1079:46 |vpiParent: - \_module: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2025:1, endln:2055:10 + \_module_inst: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2025:1, endln:2055:10 |UINT:128 |vpiTypespec: \_int_typespec: , line:1079:16, endln:1079:28 @@ -99915,7 +99915,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@ex_stage.DCACHE_SET_ASSOC), line:1076:28, endln:1076:44 |vpiParent: - \_module: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2025:1, endln:2055:10 + \_module_inst: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2025:1, endln:2055:10 |UINT:8 |vpiTypespec: \_int_typespec: , line:1076:15, endln:1076:27 @@ -99930,7 +99930,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@ex_stage.DCACHE_TAG_WIDTH), line:1078:29, endln:1078:45 |vpiParent: - \_module: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2025:1, endln:2055:10 + \_module_inst: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2025:1, endln:2055:10 |INT:44 |vpiTypespec: \_int_typespec: , line:1078:16, endln:1078:28 @@ -99945,7 +99945,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@ex_stage.DEPTH_COMMIT), line:804:29, endln:804:41 |vpiParent: - \_module: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2025:1, endln:2055:10 + \_module_inst: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2025:1, endln:2055:10 |UINT:8 |vpiTypespec: \_int_typespec: , line:804:16, endln:804:28 @@ -99960,7 +99960,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@ex_stage.DEPTH_SPEC), line:795:29, endln:795:39 |vpiParent: - \_module: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2025:1, endln:2055:10 + \_module_inst: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2025:1, endln:2055:10 |UINT:4 |vpiTypespec: \_int_typespec: , line:795:16, endln:795:28 @@ -99975,7 +99975,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@ex_stage.DebugHartInfo), line:874:31, endln:874:44 |vpiParent: - \_module: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2025:1, endln:2055:10 + \_module_inst: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2025:1, endln:2055:10 |vpiTypespec: \_unsupported_typespec: (dm::hartinfo_t), line:874:16, endln:874:20 |vpiParent: @@ -99990,7 +99990,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@ex_stage.ENABLE_CYCLE_COUNT), line:900:20, endln:900:38 |vpiParent: - \_module: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2025:1, endln:2055:10 + \_module_inst: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2025:1, endln:2055:10 |BIN:1 |vpiTypespec: \_bit_typespec: , line:900:16, endln:900:19 @@ -100006,7 +100006,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@ex_stage.ENABLE_RENAME), line:786:16, endln:786:29 |vpiParent: - \_module: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2025:1, endln:2055:10 + \_module_inst: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2025:1, endln:2055:10 |BIN:0 |vpiTypespec: \_int_typespec: @@ -100033,7 +100033,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@ex_stage.ENABLE_SPIKE_COMMIT_LOG), line:884:20, endln:884:43 |vpiParent: - \_module: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2025:1, endln:2055:10 + \_module_inst: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2025:1, endln:2055:10 |BIN:1 |vpiTypespec: \_bit_typespec: , line:884:16, endln:884:19 @@ -100049,7 +100049,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@ex_stage.ENABLE_WFI), line:901:20, endln:901:30 |vpiParent: - \_module: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2025:1, endln:2055:10 + \_module_inst: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2025:1, endln:2055:10 |BIN:1 |vpiTypespec: \_bit_typespec: , line:901:16, endln:901:19 @@ -100065,7 +100065,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@ex_stage.EXC_OFF_RST), line:1011:16, endln:1011:27 |vpiParent: - \_module: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2025:1, endln:2055:10 + \_module_inst: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2025:1, endln:2055:10 |HEX:80 |vpiTypespec: \_int_typespec: @@ -100092,7 +100092,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@ex_stage.FETCH_FIFO_DEPTH), line:929:29, endln:929:45 |vpiParent: - \_module: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2025:1, endln:2055:10 + \_module_inst: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2025:1, endln:2055:10 |UINT:4 |vpiTypespec: \_int_typespec: , line:929:16, endln:929:28 @@ -100107,7 +100107,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@ex_stage.FETCH_WIDTH), line:930:29, endln:930:40 |vpiParent: - \_module: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2025:1, endln:2055:10 + \_module_inst: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2025:1, endln:2055:10 |UINT:32 |vpiTypespec: \_int_typespec: , line:930:16, endln:930:28 @@ -100122,7 +100122,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@ex_stage.FLEN), line:839:16, endln:839:20 |vpiParent: - \_module: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2025:1, endln:2055:10 + \_module_inst: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2025:1, endln:2055:10 |INT:64 |vpiTypespec: \_int_typespec: @@ -100135,7 +100135,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@ex_stage.FP_PRESENT), line:836:20, endln:836:30 |vpiParent: - \_module: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2025:1, endln:2055:10 + \_module_inst: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2025:1, endln:2055:10 |UINT:1 |vpiTypespec: \_bit_typespec: , line:836:16, endln:836:19 @@ -100151,7 +100151,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@ex_stage.ICACHE_INDEX_WIDTH), line:1071:29, endln:1071:47 |vpiParent: - \_module: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2025:1, endln:2055:10 + \_module_inst: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2025:1, endln:2055:10 |UINT:12 |vpiTypespec: \_int_typespec: , line:1071:16, endln:1071:28 @@ -100166,7 +100166,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@ex_stage.ICACHE_LINE_WIDTH), line:1073:29, endln:1073:46 |vpiParent: - \_module: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2025:1, endln:2055:10 + \_module_inst: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2025:1, endln:2055:10 |UINT:128 |vpiTypespec: \_int_typespec: , line:1073:16, endln:1073:28 @@ -100181,7 +100181,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@ex_stage.ICACHE_SET_ASSOC), line:1070:29, endln:1070:45 |vpiParent: - \_module: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2025:1, endln:2055:10 + \_module_inst: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2025:1, endln:2055:10 |UINT:4 |vpiTypespec: \_int_typespec: , line:1070:16, endln:1070:28 @@ -100196,7 +100196,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@ex_stage.ICACHE_TAG_WIDTH), line:1072:29, endln:1072:45 |vpiParent: - \_module: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2025:1, endln:2055:10 + \_module_inst: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2025:1, endln:2055:10 |INT:44 |vpiTypespec: \_int_typespec: , line:1072:16, endln:1072:28 @@ -100211,7 +100211,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@ex_stage.INSTR_PER_FETCH), line:932:29, endln:932:44 |vpiParent: - \_module: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2025:1, endln:2055:10 + \_module_inst: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2025:1, endln:2055:10 |INT:2 |vpiTypespec: \_int_typespec: , line:932:16, endln:932:28 @@ -100226,7 +100226,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@ex_stage.INVALIDATE_ON_FLUSH), line:890:22, endln:890:41 |vpiParent: - \_module: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2025:1, endln:2055:10 + \_module_inst: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2025:1, endln:2055:10 |BIN:1 |vpiTypespec: \_logic_typespec: , line:890:16, endln:890:21 @@ -100241,7 +100241,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@ex_stage.ISA_CODE), line:857:30, endln:857:38 |vpiParent: - \_module: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2025:1, endln:2055:10 + \_module_inst: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2025:1, endln:2055:10 |vpiTypespec: \_logic_typespec: (xlen_t), line:30:13, endln:30:29 |vpiParent: @@ -100276,7 +100276,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@ex_stage.ISSUE_WIDTH), line:788:16, endln:788:27 |vpiParent: - \_module: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2025:1, endln:2055:10 + \_module_inst: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2025:1, endln:2055:10 |UINT:1 |vpiTypespec: \_int_typespec: @@ -100289,7 +100289,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@ex_stage.LAT_COMP_FP16), line:827:29, endln:827:42 |vpiParent: - \_module: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2025:1, endln:2055:10 + \_module_inst: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2025:1, endln:2055:10 |DEC:1 |vpiTypespec: \_int_typespec: , line:827:16, endln:827:28 @@ -100304,7 +100304,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@ex_stage.LAT_COMP_FP16ALT), line:828:29, endln:828:45 |vpiParent: - \_module: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2025:1, endln:2055:10 + \_module_inst: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2025:1, endln:2055:10 |DEC:1 |vpiTypespec: \_int_typespec: , line:828:16, endln:828:28 @@ -100319,7 +100319,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@ex_stage.LAT_COMP_FP32), line:825:29, endln:825:42 |vpiParent: - \_module: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2025:1, endln:2055:10 + \_module_inst: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2025:1, endln:2055:10 |DEC:2 |vpiTypespec: \_int_typespec: , line:825:16, endln:825:28 @@ -100334,7 +100334,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@ex_stage.LAT_COMP_FP64), line:826:29, endln:826:42 |vpiParent: - \_module: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2025:1, endln:2055:10 + \_module_inst: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2025:1, endln:2055:10 |DEC:3 |vpiTypespec: \_int_typespec: , line:826:16, endln:826:28 @@ -100349,7 +100349,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@ex_stage.LAT_COMP_FP8), line:829:29, endln:829:41 |vpiParent: - \_module: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2025:1, endln:2055:10 + \_module_inst: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2025:1, endln:2055:10 |DEC:1 |vpiTypespec: \_int_typespec: , line:829:16, endln:829:28 @@ -100364,7 +100364,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@ex_stage.LAT_CONV), line:832:29, endln:832:37 |vpiParent: - \_module: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2025:1, endln:2055:10 + \_module_inst: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2025:1, endln:2055:10 |DEC:2 |vpiTypespec: \_int_typespec: , line:832:16, endln:832:28 @@ -100379,7 +100379,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@ex_stage.LAT_DIVSQRT), line:830:29, endln:830:40 |vpiParent: - \_module: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2025:1, endln:2055:10 + \_module_inst: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2025:1, endln:2055:10 |DEC:2 |vpiTypespec: \_int_typespec: , line:830:16, endln:830:28 @@ -100394,7 +100394,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@ex_stage.LAT_NONCOMP), line:831:29, endln:831:40 |vpiParent: - \_module: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2025:1, endln:2055:10 + \_module_inst: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2025:1, endln:2055:10 |DEC:1 |vpiTypespec: \_int_typespec: , line:831:16, endln:831:28 @@ -100409,7 +100409,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@ex_stage.MachineIrq), line:1014:16, endln:1014:26 |vpiParent: - \_module: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2025:1, endln:2055:10 + \_module_inst: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2025:1, endln:2055:10 |UINT:0 |vpiTypespec: \_int_typespec: @@ -100422,7 +100422,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@ex_stage.NR_COMMIT_PORTS), line:784:16, endln:784:31 |vpiParent: - \_module: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2025:1, endln:2055:10 + \_module_inst: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2025:1, endln:2055:10 |UINT:2 |vpiTypespec: \_int_typespec: @@ -100435,7 +100435,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@ex_stage.NR_LOAD_PIPE_REGS), line:791:29, endln:791:46 |vpiParent: - \_module: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2025:1, endln:2055:10 + \_module_inst: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2025:1, endln:2055:10 |UINT:1 |vpiTypespec: \_int_typespec: , line:791:16, endln:791:28 @@ -100450,7 +100450,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@ex_stage.NR_SB_ENTRIES), line:779:16, endln:779:29 |vpiParent: - \_module: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2025:1, endln:2055:10 + \_module_inst: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2025:1, endln:2055:10 |UINT:8 |vpiTypespec: \_int_typespec: @@ -100463,7 +100463,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@ex_stage.NR_STORE_PIPE_REGS), line:792:29, endln:792:47 |vpiParent: - \_module: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2025:1, endln:2055:10 + \_module_inst: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2025:1, endln:2055:10 |UINT:0 |vpiTypespec: \_int_typespec: , line:792:16, endln:792:28 @@ -100478,7 +100478,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@ex_stage.NR_WB_PORTS), line:871:16, endln:871:27 |vpiParent: - \_module: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2025:1, endln:2055:10 + \_module_inst: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2025:1, endln:2055:10 |UINT:4 |vpiTypespec: \_int_typespec: @@ -100491,7 +100491,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@ex_stage.NSX), line:846:20, endln:846:23 |vpiParent: - \_module: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2025:1, endln:2055:10 + \_module_inst: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2025:1, endln:2055:10 |UINT:0 |vpiTypespec: \_bit_typespec: , line:846:16, endln:846:19 @@ -100507,7 +100507,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@ex_stage.NrMaxRules), line:682:16, endln:682:26 |vpiParent: - \_module: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2025:1, endln:2055:10 + \_module_inst: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2025:1, endln:2055:10 |UINT:16 |vpiTypespec: \_int_typespec: @@ -100520,7 +100520,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@ex_stage.PPN4K_WIDTH), line:1293:16, endln:1293:27 |vpiParent: - \_module: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2025:1, endln:2055:10 + \_module_inst: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2025:1, endln:2055:10 |UINT:38 |vpiTypespec: \_int_typespec: @@ -100533,7 +100533,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@ex_stage.REG_ADDR_SIZE), line:870:16, endln:870:29 |vpiParent: - \_module: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2025:1, endln:2055:10 + \_module_inst: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2025:1, endln:2055:10 |UINT:6 |vpiTypespec: \_int_typespec: @@ -100546,7 +100546,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@ex_stage.RVA), line:816:20, endln:816:23 |vpiParent: - \_module: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2025:1, endln:2055:10 + \_module_inst: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2025:1, endln:2055:10 |BIN:1 |vpiTypespec: \_bit_typespec: , line:816:16, endln:816:19 @@ -100562,7 +100562,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@ex_stage.RVD), line:814:20, endln:814:23 |vpiParent: - \_module: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2025:1, endln:2055:10 + \_module_inst: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2025:1, endln:2055:10 |INT:1 |vpiTypespec: \_bit_typespec: , line:814:16, endln:814:19 @@ -100578,7 +100578,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@ex_stage.RVF), line:813:20, endln:813:23 |vpiParent: - \_module: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2025:1, endln:2055:10 + \_module_inst: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2025:1, endln:2055:10 |INT:1 |vpiTypespec: \_bit_typespec: , line:813:16, endln:813:19 @@ -100594,7 +100594,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@ex_stage.RVFVEC), line:848:20, endln:848:26 |vpiParent: - \_module: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2025:1, endln:2055:10 + \_module_inst: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2025:1, endln:2055:10 |UINT:0 |vpiTypespec: \_bit_typespec: , line:848:16, endln:848:19 @@ -100610,7 +100610,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@ex_stage.SMODE_STATUS_READ_MASK), line:905:29, endln:905:51 |vpiParent: - \_module: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2025:1, endln:2055:10 + \_module_inst: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2025:1, endln:2055:10 |vpiTypespec: \_logic_typespec: , line:905:16, endln:905:28 |vpiParent: @@ -100644,7 +100644,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@ex_stage.SMODE_STATUS_WRITE_MASK), line:918:29, endln:918:52 |vpiParent: - \_module: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2025:1, endln:2055:10 + \_module_inst: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2025:1, endln:2055:10 |vpiTypespec: \_logic_typespec: , line:918:16, endln:918:28 |vpiParent: @@ -100678,7 +100678,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@ex_stage.SupervisorIrq), line:1013:16, endln:1013:29 |vpiParent: - \_module: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2025:1, endln:2055:10 + \_module_inst: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2025:1, endln:2055:10 |UINT:1 |vpiTypespec: \_int_typespec: @@ -100691,7 +100691,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@ex_stage.TRANS_ID_BITS), line:780:16, endln:780:29 |vpiParent: - \_module: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2025:1, endln:2055:10 + \_module_inst: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2025:1, endln:2055:10 |UINT:3 |vpiTypespec: \_int_typespec: @@ -100704,7 +100704,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@ex_stage.XF16), line:819:20, endln:819:24 |vpiParent: - \_module: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2025:1, endln:2055:10 + \_module_inst: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2025:1, endln:2055:10 |BIN:0 |vpiTypespec: \_bit_typespec: , line:819:16, endln:819:19 @@ -100720,7 +100720,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@ex_stage.XF16ALT), line:820:20, endln:820:27 |vpiParent: - \_module: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2025:1, endln:2055:10 + \_module_inst: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2025:1, endln:2055:10 |BIN:0 |vpiTypespec: \_bit_typespec: , line:820:16, endln:820:19 @@ -100736,7 +100736,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@ex_stage.XF16ALTVEC), line:850:20, endln:850:30 |vpiParent: - \_module: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2025:1, endln:2055:10 + \_module_inst: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2025:1, endln:2055:10 |UINT:0 |vpiTypespec: \_bit_typespec: , line:850:16, endln:850:19 @@ -100752,7 +100752,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@ex_stage.XF16VEC), line:849:20, endln:849:27 |vpiParent: - \_module: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2025:1, endln:2055:10 + \_module_inst: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2025:1, endln:2055:10 |UINT:0 |vpiTypespec: \_bit_typespec: , line:849:16, endln:849:19 @@ -100768,7 +100768,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@ex_stage.XF8), line:821:20, endln:821:23 |vpiParent: - \_module: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2025:1, endln:2055:10 + \_module_inst: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2025:1, endln:2055:10 |BIN:0 |vpiTypespec: \_bit_typespec: , line:821:16, endln:821:19 @@ -100784,7 +100784,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@ex_stage.XF8VEC), line:851:20, endln:851:26 |vpiParent: - \_module: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2025:1, endln:2055:10 + \_module_inst: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2025:1, endln:2055:10 |UINT:0 |vpiTypespec: \_bit_typespec: , line:851:16, endln:851:19 @@ -100800,7 +100800,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@ex_stage.XFVEC), line:822:20, endln:822:25 |vpiParent: - \_module: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2025:1, endln:2055:10 + \_module_inst: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2025:1, endln:2055:10 |BIN:0 |vpiTypespec: \_bit_typespec: , line:822:16, endln:822:19 @@ -100816,7 +100816,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@ex_stage.ZERO_TVAL), line:902:20, endln:902:29 |vpiParent: - \_module: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2025:1, endln:2055:10 + \_module_inst: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2025:1, endln:2055:10 |BIN:0 |vpiTypespec: \_bit_typespec: , line:902:16, endln:902:19 @@ -100832,7 +100832,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@ex_stage.ASID_WIDTH), line:2026:28, endln:2026:38 |vpiParent: - \_module: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2025:1, endln:2055:10 + \_module_inst: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2025:1, endln:2055:10 |UINT:1 |vpiTypespec: \_int_typespec: , line:2026:15, endln:2026:27 @@ -100843,7 +100843,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@ex_stage.ArianeCfg), line:2027:40, endln:2027:49 |vpiParent: - \_module: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2025:1, endln:2055:10 + \_module_inst: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2025:1, endln:2055:10 |vpiTypespec: \_struct_typespec: (ariane_pkg::ariane_cfg_t), line:684:13, endln:684:19 |vpiName:ArianeCfg @@ -100851,7 +100851,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:682:16, endln:682:31 |vpiParent: - \_module: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2025:1, endln:2055:10 + \_module_inst: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2025:1, endln:2055:10 |vpiRhs: \_constant: , line:682:29, endln:682:31 |vpiParent: @@ -100880,7 +100880,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:706:29, endln:728:6 |vpiParent: - \_module: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2025:1, endln:2055:10 + \_module_inst: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2025:1, endln:2055:10 |vpiRhs: \_operation: , line:706:51, endln:728:6 |vpiParent: @@ -101692,7 +101692,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:779:16, endln:779:33 |vpiParent: - \_module: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2025:1, endln:2055:10 + \_module_inst: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2025:1, endln:2055:10 |vpiRhs: \_constant: , line:779:32, endln:779:33 |vpiParent: @@ -101721,7 +101721,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:780:16, endln:780:53 |vpiParent: - \_module: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2025:1, endln:2055:10 + \_module_inst: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2025:1, endln:2055:10 |vpiRhs: \_constant: , line:780:32, endln:780:53 |vpiParent: @@ -101750,7 +101750,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:782:16, endln:782:60 |vpiParent: - \_module: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2025:1, endln:2055:10 + \_module_inst: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2025:1, endln:2055:10 |vpiRhs: \_constant: , line:782:32, endln:782:51 |vpiParent: @@ -101779,7 +101779,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:783:16, endln:783:43 |vpiParent: - \_module: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2025:1, endln:2055:10 + \_module_inst: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2025:1, endln:2055:10 |vpiRhs: \_constant: , line:783:42, endln:783:43 |vpiParent: @@ -101808,7 +101808,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:784:16, endln:784:35 |vpiParent: - \_module: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2025:1, endln:2055:10 + \_module_inst: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2025:1, endln:2055:10 |vpiRhs: \_constant: , line:784:34, endln:784:35 |vpiParent: @@ -101837,7 +101837,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:786:16, endln:786:36 |vpiParent: - \_module: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2025:1, endln:2055:10 + \_module_inst: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2025:1, endln:2055:10 |vpiRhs: \_constant: , line:786:32, endln:786:36 |vpiParent: @@ -101894,7 +101894,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:788:16, endln:788:31 |vpiParent: - \_module: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2025:1, endln:2055:10 + \_module_inst: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2025:1, endln:2055:10 |vpiRhs: \_constant: , line:788:30, endln:788:31 |vpiParent: @@ -101923,7 +101923,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:791:29, endln:791:50 |vpiParent: - \_module: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2025:1, endln:2055:10 + \_module_inst: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2025:1, endln:2055:10 |vpiRhs: \_constant: , line:791:49, endln:791:50 |vpiParent: @@ -101956,7 +101956,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:792:29, endln:792:51 |vpiParent: - \_module: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2025:1, endln:2055:10 + \_module_inst: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2025:1, endln:2055:10 |vpiRhs: \_constant: , line:792:50, endln:792:51 |vpiParent: @@ -101989,7 +101989,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:795:29, endln:795:45 |vpiParent: - \_module: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2025:1, endln:2055:10 + \_module_inst: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2025:1, endln:2055:10 |vpiRhs: \_constant: , line:795:44, endln:795:45 |vpiParent: @@ -102022,7 +102022,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:804:29, endln:804:45 |vpiParent: - \_module: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2025:1, endln:2055:10 + \_module_inst: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2025:1, endln:2055:10 |vpiRhs: \_constant: , line:804:44, endln:804:45 |vpiParent: @@ -102055,7 +102055,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:813:20, endln:813:42 |vpiParent: - \_module: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2025:1, endln:2055:10 + \_module_inst: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2025:1, endln:2055:10 |vpiRhs: \_constant: , line:813:26, endln:813:33 |vpiParent: @@ -102090,7 +102090,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:814:20, endln:814:42 |vpiParent: - \_module: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2025:1, endln:2055:10 + \_module_inst: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2025:1, endln:2055:10 |vpiRhs: \_constant: , line:814:26, endln:814:33 |vpiParent: @@ -102125,7 +102125,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:816:20, endln:816:30 |vpiParent: - \_module: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2025:1, endln:2055:10 + \_module_inst: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2025:1, endln:2055:10 |vpiRhs: \_constant: , line:816:26, endln:816:30 |vpiParent: @@ -102160,7 +102160,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:819:20, endln:819:34 |vpiParent: - \_module: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2025:1, endln:2055:10 + \_module_inst: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2025:1, endln:2055:10 |vpiRhs: \_constant: , line:819:30, endln:819:34 |vpiParent: @@ -102195,7 +102195,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:820:20, endln:820:34 |vpiParent: - \_module: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2025:1, endln:2055:10 + \_module_inst: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2025:1, endln:2055:10 |vpiRhs: \_constant: , line:820:30, endln:820:34 |vpiParent: @@ -102230,7 +102230,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:821:20, endln:821:34 |vpiParent: - \_module: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2025:1, endln:2055:10 + \_module_inst: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2025:1, endln:2055:10 |vpiRhs: \_constant: , line:821:30, endln:821:34 |vpiParent: @@ -102265,7 +102265,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:822:20, endln:822:34 |vpiParent: - \_module: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2025:1, endln:2055:10 + \_module_inst: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2025:1, endln:2055:10 |vpiRhs: \_constant: , line:822:30, endln:822:34 |vpiParent: @@ -102300,7 +102300,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:825:29, endln:825:51 |vpiParent: - \_module: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2025:1, endln:2055:10 + \_module_inst: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2025:1, endln:2055:10 |vpiRhs: \_constant: , line:825:48, endln:825:51 |vpiParent: @@ -102333,7 +102333,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:826:29, endln:826:51 |vpiParent: - \_module: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2025:1, endln:2055:10 + \_module_inst: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2025:1, endln:2055:10 |vpiRhs: \_constant: , line:826:48, endln:826:51 |vpiParent: @@ -102366,7 +102366,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:827:29, endln:827:51 |vpiParent: - \_module: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2025:1, endln:2055:10 + \_module_inst: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2025:1, endln:2055:10 |vpiRhs: \_constant: , line:827:48, endln:827:51 |vpiParent: @@ -102399,7 +102399,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:828:29, endln:828:51 |vpiParent: - \_module: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2025:1, endln:2055:10 + \_module_inst: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2025:1, endln:2055:10 |vpiRhs: \_constant: , line:828:48, endln:828:51 |vpiParent: @@ -102432,7 +102432,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:829:29, endln:829:51 |vpiParent: - \_module: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2025:1, endln:2055:10 + \_module_inst: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2025:1, endln:2055:10 |vpiRhs: \_constant: , line:829:48, endln:829:51 |vpiParent: @@ -102465,7 +102465,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:830:29, endln:830:51 |vpiParent: - \_module: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2025:1, endln:2055:10 + \_module_inst: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2025:1, endln:2055:10 |vpiRhs: \_constant: , line:830:48, endln:830:51 |vpiParent: @@ -102498,7 +102498,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:831:29, endln:831:51 |vpiParent: - \_module: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2025:1, endln:2055:10 + \_module_inst: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2025:1, endln:2055:10 |vpiRhs: \_constant: , line:831:48, endln:831:51 |vpiParent: @@ -102531,7 +102531,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:832:29, endln:832:51 |vpiParent: - \_module: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2025:1, endln:2055:10 + \_module_inst: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2025:1, endln:2055:10 |vpiRhs: \_constant: , line:832:48, endln:832:51 |vpiParent: @@ -102564,7 +102564,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:836:20, endln:836:65 |vpiParent: - \_module: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2025:1, endln:2055:10 + \_module_inst: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2025:1, endln:2055:10 |vpiRhs: \_constant: , line:836:33, endln:836:59 |vpiParent: @@ -102599,7 +102599,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:839:16, endln:844:27 |vpiParent: - \_module: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2025:1, endln:2055:10 + \_module_inst: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2025:1, endln:2055:10 |vpiRhs: \_constant: , line:839:26, endln:839:29 |vpiParent: @@ -102628,7 +102628,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:846:20, endln:846:54 |vpiParent: - \_module: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2025:1, endln:2055:10 + \_module_inst: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2025:1, endln:2055:10 |vpiRhs: \_constant: , line:846:26, endln:846:46 |vpiParent: @@ -102663,7 +102663,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:848:20, endln:848:58 |vpiParent: - \_module: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2025:1, endln:2055:10 + \_module_inst: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2025:1, endln:2055:10 |vpiRhs: \_constant: , line:848:33, endln:848:48 |vpiParent: @@ -102698,7 +102698,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:849:20, endln:849:58 |vpiParent: - \_module: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2025:1, endln:2055:10 + \_module_inst: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2025:1, endln:2055:10 |vpiRhs: \_constant: , line:849:33, endln:849:48 |vpiParent: @@ -102733,7 +102733,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:850:20, endln:850:58 |vpiParent: - \_module: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2025:1, endln:2055:10 + \_module_inst: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2025:1, endln:2055:10 |vpiRhs: \_constant: , line:850:33, endln:850:48 |vpiParent: @@ -102768,7 +102768,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:851:20, endln:851:57 |vpiParent: - \_module: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2025:1, endln:2055:10 + \_module_inst: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2025:1, endln:2055:10 |vpiRhs: \_constant: , line:851:33, endln:851:48 |vpiParent: @@ -102803,7 +102803,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:855:30, endln:855:78 |vpiParent: - \_module: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2025:1, endln:2055:10 + \_module_inst: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2025:1, endln:2055:10 |vpiRhs: \_operation: , line:855:47, endln:855:78 |vpiParent: @@ -102898,7 +102898,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:857:30, endln:867:86 |vpiParent: - \_module: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2025:1, endln:2055:10 + \_module_inst: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2025:1, endln:2055:10 |vpiRhs: \_operation: , line:857:41, endln:867:86 |vpiParent: @@ -103265,7 +103265,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:870:16, endln:870:33 |vpiParent: - \_module: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2025:1, endln:2055:10 + \_module_inst: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2025:1, endln:2055:10 |vpiRhs: \_constant: , line:870:32, endln:870:33 |vpiParent: @@ -103294,7 +103294,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:871:16, endln:871:31 |vpiParent: - \_module: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2025:1, endln:2055:10 + \_module_inst: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2025:1, endln:2055:10 |vpiRhs: \_constant: , line:871:30, endln:871:31 |vpiParent: @@ -103323,7 +103323,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:874:31, endln:881:48 |vpiParent: - \_module: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2025:1, endln:2055:10 + \_module_inst: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2025:1, endln:2055:10 |vpiRhs: \_operation: , line:874:47, endln:881:48 |vpiParent: @@ -103445,7 +103445,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:884:20, endln:884:50 |vpiParent: - \_module: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2025:1, endln:2055:10 + \_module_inst: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2025:1, endln:2055:10 |vpiRhs: \_constant: , line:884:46, endln:884:50 |vpiParent: @@ -103480,7 +103480,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:890:22, endln:890:48 |vpiParent: - \_module: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2025:1, endln:2055:10 + \_module_inst: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2025:1, endln:2055:10 |vpiRhs: \_constant: , line:890:44, endln:890:48 |vpiParent: @@ -103513,7 +103513,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:900:20, endln:900:45 |vpiParent: - \_module: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2025:1, endln:2055:10 + \_module_inst: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2025:1, endln:2055:10 |vpiRhs: \_constant: , line:900:41, endln:900:45 |vpiParent: @@ -103548,7 +103548,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:901:20, endln:901:37 |vpiParent: - \_module: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2025:1, endln:2055:10 + \_module_inst: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2025:1, endln:2055:10 |vpiRhs: \_constant: , line:901:33, endln:901:37 |vpiParent: @@ -103583,7 +103583,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:902:20, endln:902:36 |vpiParent: - \_module: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2025:1, endln:2055:10 + \_module_inst: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2025:1, endln:2055:10 |vpiRhs: \_constant: , line:902:32, endln:902:36 |vpiParent: @@ -103618,7 +103618,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:905:29, endln:916:71 |vpiParent: - \_module: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2025:1, endln:2055:10 + \_module_inst: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2025:1, endln:2055:10 |vpiRhs: \_operation: , line:905:54, endln:916:71 |vpiParent: @@ -104124,7 +104124,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:918:29, endln:923:73 |vpiParent: - \_module: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2025:1, endln:2055:10 + \_module_inst: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2025:1, endln:2055:10 |vpiRhs: \_operation: , line:918:55, endln:923:73 |vpiParent: @@ -104391,7 +104391,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:929:29, endln:929:50 |vpiParent: - \_module: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2025:1, endln:2055:10 + \_module_inst: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2025:1, endln:2055:10 |vpiRhs: \_constant: , line:929:49, endln:929:50 |vpiParent: @@ -104424,7 +104424,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:930:29, endln:930:51 |vpiParent: - \_module: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2025:1, endln:2055:10 + \_module_inst: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2025:1, endln:2055:10 |vpiRhs: \_constant: , line:930:49, endln:930:51 |vpiParent: @@ -104457,7 +104457,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:932:29, endln:932:63 |vpiParent: - \_module: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2025:1, endln:2055:10 + \_module_inst: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2025:1, endln:2055:10 |vpiRhs: \_constant: , line:932:47, endln:932:58 |vpiParent: @@ -104490,7 +104490,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:1011:16, endln:1011:40 |vpiParent: - \_module: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2025:1, endln:2055:10 + \_module_inst: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2025:1, endln:2055:10 |vpiRhs: \_constant: , line:1011:35, endln:1011:40 |vpiParent: @@ -104547,7 +104547,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:1013:16, endln:1013:33 |vpiParent: - \_module: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2025:1, endln:2055:10 + \_module_inst: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2025:1, endln:2055:10 |vpiRhs: \_constant: , line:1013:32, endln:1013:33 |vpiParent: @@ -104576,7 +104576,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:1014:16, endln:1014:30 |vpiParent: - \_module: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2025:1, endln:2055:10 + \_module_inst: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2025:1, endln:2055:10 |vpiRhs: \_constant: , line:1014:29, endln:1014:30 |vpiParent: @@ -104605,7 +104605,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:1069:27, endln:1069:55 |vpiParent: - \_module: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2025:1, endln:2055:10 + \_module_inst: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2025:1, endln:2055:10 |vpiRhs: \_constant: , line:1069:48, endln:1069:50 |vpiParent: @@ -104638,7 +104638,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:1070:29, endln:1070:51 |vpiParent: - \_module: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2025:1, endln:2055:10 + \_module_inst: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2025:1, endln:2055:10 |vpiRhs: \_constant: , line:1070:50, endln:1070:51 |vpiParent: @@ -104671,7 +104671,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:1071:29, endln:1071:92 |vpiParent: - \_module: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2025:1, endln:2055:10 + \_module_inst: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2025:1, endln:2055:10 |vpiRhs: \_constant: , line:1071:50, endln:1071:92 |vpiParent: @@ -104704,7 +104704,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:1072:29, endln:1072:80 |vpiParent: - \_module: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2025:1, endln:2055:10 + \_module_inst: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2025:1, endln:2055:10 |vpiRhs: \_constant: , line:1072:50, endln:1072:61 |vpiParent: @@ -104737,7 +104737,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:1073:29, endln:1073:53 |vpiParent: - \_module: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2025:1, endln:2055:10 + \_module_inst: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2025:1, endln:2055:10 |vpiRhs: \_constant: , line:1073:50, endln:1073:53 |vpiParent: @@ -104770,7 +104770,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:1075:27, endln:1075:55 |vpiParent: - \_module: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2025:1, endln:2055:10 + \_module_inst: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2025:1, endln:2055:10 |vpiRhs: \_constant: , line:1075:48, endln:1075:50 |vpiParent: @@ -104803,7 +104803,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:1076:28, endln:1076:50 |vpiParent: - \_module: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2025:1, endln:2055:10 + \_module_inst: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2025:1, endln:2055:10 |vpiRhs: \_constant: , line:1076:49, endln:1076:50 |vpiParent: @@ -104836,7 +104836,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:1077:29, endln:1077:92 |vpiParent: - \_module: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2025:1, endln:2055:10 + \_module_inst: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2025:1, endln:2055:10 |vpiRhs: \_constant: , line:1077:50, endln:1077:92 |vpiParent: @@ -104869,7 +104869,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:1078:29, endln:1078:80 |vpiParent: - \_module: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2025:1, endln:2055:10 + \_module_inst: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2025:1, endln:2055:10 |vpiRhs: \_constant: , line:1078:50, endln:1078:61 |vpiParent: @@ -104902,7 +104902,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:1079:29, endln:1079:53 |vpiParent: - \_module: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2025:1, endln:2055:10 + \_module_inst: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2025:1, endln:2055:10 |vpiRhs: \_constant: , line:1079:50, endln:1079:53 |vpiParent: @@ -104935,7 +104935,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:1293:16, endln:1293:32 |vpiParent: - \_module: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2025:1, endln:2055:10 + \_module_inst: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2025:1, endln:2055:10 |vpiRhs: \_constant: , line:1293:30, endln:1293:32 |vpiParent: @@ -104964,7 +104964,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:2026:28, endln:2026:42 |vpiParent: - \_module: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2025:1, endln:2055:10 + \_module_inst: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2025:1, endln:2055:10 |vpiRhs: \_constant: , line:2026:41, endln:2026:42 |vpiDecompile:1 @@ -104978,7 +104978,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:2027:40, endln:2027:83 |vpiParent: - \_module: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2025:1, endln:2055:10 + \_module_inst: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2025:1, endln:2055:10 |vpiRhs: \_operation: , line:2027:52, endln:2027:64 |vpiOpType:75 @@ -105346,14 +105346,14 @@ design: (work@top) |vpiTaskFunc: \_function: (ariane_pkg::extract_transfer_size), line:1458:5, endln:1482:16 |uhdmallModules: -\_module: work@fpnew_top (work@fpnew_top), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1958:1, endln:1987:10 +\_module_inst: work@fpnew_top (work@fpnew_top), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1958:1, endln:1987:10 |vpiParent: \_design: (work@top) |vpiFullName:work@fpnew_top |vpiParameter: \_parameter: (work@fpnew_top.Features), line:1960:45, endln:1960:53 |vpiParent: - \_module: work@fpnew_top (work@fpnew_top), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1958:1, endln:1987:10 + \_module_inst: work@fpnew_top (work@fpnew_top), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1958:1, endln:1987:10 |vpiTypespec: \_struct_typespec: (fpnew_pkg::fpu_features_t), line:1662:11, endln:1662:17 |vpiName:Features @@ -105361,7 +105361,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@fpnew_top.Implementation), line:1961:45, endln:1961:59 |vpiParent: - \_module: work@fpnew_top (work@fpnew_top), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1958:1, endln:1987:10 + \_module_inst: work@fpnew_top (work@fpnew_top), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1958:1, endln:1987:10 |vpiTypespec: \_struct_typespec: (fpnew_pkg::fpu_implementation_t), line:1720:11, endln:1720:17 |vpiName:Implementation @@ -105369,7 +105369,7 @@ design: (work@top) |vpiParameter: \_type_parameter: (work@fpnew_top.TagType), line:1962:45, endln:1962:52 |vpiParent: - \_module: work@fpnew_top (work@fpnew_top), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1958:1, endln:1987:10 + \_module_inst: work@fpnew_top (work@fpnew_top), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1958:1, endln:1987:10 |vpiName:TagType |vpiFullName:work@fpnew_top.TagType |vpiTypespec: @@ -105379,7 +105379,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@fpnew_top.WIDTH), line:1964:27, endln:1964:32 |vpiParent: - \_module: work@fpnew_top (work@fpnew_top), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1958:1, endln:1987:10 + \_module_inst: work@fpnew_top (work@fpnew_top), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1958:1, endln:1987:10 |vpiTypespec: \_int_typespec: , line:1964:14, endln:1964:26 |vpiParent: @@ -105390,7 +105390,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@fpnew_top.NUM_OPERANDS), line:1965:27, endln:1965:39 |vpiParent: - \_module: work@fpnew_top (work@fpnew_top), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1958:1, endln:1987:10 + \_module_inst: work@fpnew_top (work@fpnew_top), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1958:1, endln:1987:10 |UINT:3 |vpiTypespec: \_int_typespec: , line:1965:14, endln:1965:26 @@ -105402,7 +105402,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@fpnew_top.NUM_FORMATS), line:1969:27, endln:1969:38 |vpiParent: - \_module: work@fpnew_top (work@fpnew_top), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1958:1, endln:1987:10 + \_module_inst: work@fpnew_top (work@fpnew_top), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1958:1, endln:1987:10 |UINT:5 |vpiTypespec: \_int_typespec: , line:1969:14, endln:1969:26 @@ -105414,7 +105414,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:1960:45, endln:1960:84 |vpiParent: - \_module: work@fpnew_top (work@fpnew_top), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1958:1, endln:1987:10 + \_module_inst: work@fpnew_top (work@fpnew_top), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1958:1, endln:1987:10 |vpiRhs: \_operation: , line:1960:62, endln:1960:73 |vpiOpType:75 @@ -105508,7 +105508,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:1961:45, endln:1961:87 |vpiParent: - \_module: work@fpnew_top (work@fpnew_top), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1958:1, endln:1987:10 + \_module_inst: work@fpnew_top (work@fpnew_top), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1958:1, endln:1987:10 |vpiRhs: \_operation: , line:1961:62, endln:1961:73 |vpiOpType:75 @@ -105667,7 +105667,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:1964:27, endln:1964:56 |vpiParent: - \_module: work@fpnew_top (work@fpnew_top), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1958:1, endln:1987:10 + \_module_inst: work@fpnew_top (work@fpnew_top), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1958:1, endln:1987:10 |vpiRhs: \_hier_path: (Features.Width), line:1964:42, endln:1964:56 |vpiName:Features.Width @@ -105684,7 +105684,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:1965:27, endln:1965:43 |vpiParent: - \_module: work@fpnew_top (work@fpnew_top), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1958:1, endln:1987:10 + \_module_inst: work@fpnew_top (work@fpnew_top), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1958:1, endln:1987:10 |vpiRhs: \_constant: , line:1965:42, endln:1965:43 |vpiDecompile:3 @@ -105698,7 +105698,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:1969:27, endln:1969:67 |vpiParent: - \_module: work@fpnew_top (work@fpnew_top), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1958:1, endln:1987:10 + \_module_inst: work@fpnew_top (work@fpnew_top), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1958:1, endln:1987:10 |vpiRhs: \_constant: , line:1969:42, endln:1969:53 |vpiDecompile:5 @@ -105711,14 +105711,14 @@ design: (work@top) \_parameter: (work@fpnew_top.NUM_FORMATS), line:1969:27, endln:1969:38 |vpiDefName:work@fpnew_top |uhdmallModules: -\_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 +\_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 |vpiParent: \_design: (work@top) |vpiFullName:work@fpu_wrap |vpiParameter: \_parameter: (work@fpu_wrap.ARIANE_MARCHID), line:855:30, endln:855:44 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 |vpiTypespec: \_logic_typespec: (xlen_t), line:30:13, endln:30:29 |vpiParent: @@ -105753,7 +105753,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@fpu_wrap.ASID_WIDTH), line:782:16, endln:782:26 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 |INT:16 |vpiTypespec: \_int_typespec: @@ -105766,7 +105766,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@fpu_wrap.ArianeDefaultConfig), line:706:29, endln:706:48 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 |vpiTypespec: \_struct_typespec: (ariane_pkg::ariane_cfg_t), line:684:13, endln:684:19 |vpiParent: @@ -106303,7 +106303,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@fpu_wrap.BITS_SATURATION_COUNTER), line:783:16, endln:783:39 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 |UINT:2 |vpiTypespec: \_int_typespec: @@ -106316,7 +106316,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@fpu_wrap.CONFIG_L1D_SIZE), line:1075:27, endln:1075:42 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 |INT:32768 |vpiTypespec: \_int_typespec: , line:1075:14, endln:1075:26 @@ -106331,7 +106331,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@fpu_wrap.CONFIG_L1I_SIZE), line:1069:27, endln:1069:42 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 |INT:16384 |vpiTypespec: \_int_typespec: , line:1069:14, endln:1069:26 @@ -106346,7 +106346,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@fpu_wrap.DCACHE_INDEX_WIDTH), line:1077:29, endln:1077:47 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 |UINT:12 |vpiTypespec: \_int_typespec: , line:1077:16, endln:1077:28 @@ -106361,7 +106361,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@fpu_wrap.DCACHE_LINE_WIDTH), line:1079:29, endln:1079:46 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 |UINT:128 |vpiTypespec: \_int_typespec: , line:1079:16, endln:1079:28 @@ -106376,7 +106376,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@fpu_wrap.DCACHE_SET_ASSOC), line:1076:28, endln:1076:44 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 |UINT:8 |vpiTypespec: \_int_typespec: , line:1076:15, endln:1076:27 @@ -106391,7 +106391,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@fpu_wrap.DCACHE_TAG_WIDTH), line:1078:29, endln:1078:45 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 |INT:44 |vpiTypespec: \_int_typespec: , line:1078:16, endln:1078:28 @@ -106406,7 +106406,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@fpu_wrap.DEPTH_COMMIT), line:804:29, endln:804:41 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 |UINT:8 |vpiTypespec: \_int_typespec: , line:804:16, endln:804:28 @@ -106421,7 +106421,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@fpu_wrap.DEPTH_SPEC), line:795:29, endln:795:39 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 |UINT:4 |vpiTypespec: \_int_typespec: , line:795:16, endln:795:28 @@ -106436,7 +106436,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@fpu_wrap.DebugHartInfo), line:874:31, endln:874:44 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 |vpiTypespec: \_unsupported_typespec: (dm::hartinfo_t), line:874:16, endln:874:20 |vpiParent: @@ -106451,7 +106451,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@fpu_wrap.ENABLE_CYCLE_COUNT), line:900:20, endln:900:38 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 |BIN:1 |vpiTypespec: \_bit_typespec: , line:900:16, endln:900:19 @@ -106467,7 +106467,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@fpu_wrap.ENABLE_RENAME), line:786:16, endln:786:29 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 |BIN:0 |vpiTypespec: \_int_typespec: @@ -106494,7 +106494,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@fpu_wrap.ENABLE_SPIKE_COMMIT_LOG), line:884:20, endln:884:43 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 |BIN:1 |vpiTypespec: \_bit_typespec: , line:884:16, endln:884:19 @@ -106510,7 +106510,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@fpu_wrap.ENABLE_WFI), line:901:20, endln:901:30 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 |BIN:1 |vpiTypespec: \_bit_typespec: , line:901:16, endln:901:19 @@ -106526,7 +106526,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@fpu_wrap.EXC_OFF_RST), line:1011:16, endln:1011:27 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 |HEX:80 |vpiTypespec: \_int_typespec: @@ -106553,7 +106553,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@fpu_wrap.FETCH_FIFO_DEPTH), line:929:29, endln:929:45 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 |UINT:4 |vpiTypespec: \_int_typespec: , line:929:16, endln:929:28 @@ -106568,7 +106568,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@fpu_wrap.FETCH_WIDTH), line:930:29, endln:930:40 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 |UINT:32 |vpiTypespec: \_int_typespec: , line:930:16, endln:930:28 @@ -106583,7 +106583,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@fpu_wrap.FLEN), line:839:16, endln:839:20 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 |INT:64 |vpiTypespec: \_int_typespec: @@ -106596,7 +106596,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@fpu_wrap.FP_PRESENT), line:836:20, endln:836:30 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 |UINT:1 |vpiTypespec: \_bit_typespec: , line:836:16, endln:836:19 @@ -106612,7 +106612,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@fpu_wrap.ICACHE_INDEX_WIDTH), line:1071:29, endln:1071:47 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 |UINT:12 |vpiTypespec: \_int_typespec: , line:1071:16, endln:1071:28 @@ -106627,7 +106627,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@fpu_wrap.ICACHE_LINE_WIDTH), line:1073:29, endln:1073:46 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 |UINT:128 |vpiTypespec: \_int_typespec: , line:1073:16, endln:1073:28 @@ -106642,7 +106642,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@fpu_wrap.ICACHE_SET_ASSOC), line:1070:29, endln:1070:45 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 |UINT:4 |vpiTypespec: \_int_typespec: , line:1070:16, endln:1070:28 @@ -106657,7 +106657,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@fpu_wrap.ICACHE_TAG_WIDTH), line:1072:29, endln:1072:45 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 |INT:44 |vpiTypespec: \_int_typespec: , line:1072:16, endln:1072:28 @@ -106672,7 +106672,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@fpu_wrap.INSTR_PER_FETCH), line:932:29, endln:932:44 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 |INT:2 |vpiTypespec: \_int_typespec: , line:932:16, endln:932:28 @@ -106687,7 +106687,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@fpu_wrap.INVALIDATE_ON_FLUSH), line:890:22, endln:890:41 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 |BIN:1 |vpiTypespec: \_logic_typespec: , line:890:16, endln:890:21 @@ -106702,7 +106702,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@fpu_wrap.ISA_CODE), line:857:30, endln:857:38 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 |vpiTypespec: \_logic_typespec: (xlen_t), line:30:13, endln:30:29 |vpiParent: @@ -106737,7 +106737,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@fpu_wrap.ISSUE_WIDTH), line:788:16, endln:788:27 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 |UINT:1 |vpiTypespec: \_int_typespec: @@ -106750,7 +106750,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@fpu_wrap.LAT_COMP_FP16), line:827:29, endln:827:42 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 |DEC:1 |vpiTypespec: \_int_typespec: , line:827:16, endln:827:28 @@ -106765,7 +106765,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@fpu_wrap.LAT_COMP_FP16ALT), line:828:29, endln:828:45 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 |DEC:1 |vpiTypespec: \_int_typespec: , line:828:16, endln:828:28 @@ -106780,7 +106780,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@fpu_wrap.LAT_COMP_FP32), line:825:29, endln:825:42 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 |DEC:2 |vpiTypespec: \_int_typespec: , line:825:16, endln:825:28 @@ -106795,7 +106795,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@fpu_wrap.LAT_COMP_FP64), line:826:29, endln:826:42 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 |DEC:3 |vpiTypespec: \_int_typespec: , line:826:16, endln:826:28 @@ -106810,7 +106810,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@fpu_wrap.LAT_COMP_FP8), line:829:29, endln:829:41 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 |DEC:1 |vpiTypespec: \_int_typespec: , line:829:16, endln:829:28 @@ -106825,7 +106825,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@fpu_wrap.LAT_CONV), line:832:29, endln:832:37 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 |DEC:2 |vpiTypespec: \_int_typespec: , line:832:16, endln:832:28 @@ -106840,7 +106840,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@fpu_wrap.LAT_DIVSQRT), line:830:29, endln:830:40 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 |DEC:2 |vpiTypespec: \_int_typespec: , line:830:16, endln:830:28 @@ -106855,7 +106855,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@fpu_wrap.LAT_NONCOMP), line:831:29, endln:831:40 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 |DEC:1 |vpiTypespec: \_int_typespec: , line:831:16, endln:831:28 @@ -106870,7 +106870,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@fpu_wrap.MachineIrq), line:1014:16, endln:1014:26 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 |UINT:0 |vpiTypespec: \_int_typespec: @@ -106883,7 +106883,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@fpu_wrap.NR_COMMIT_PORTS), line:784:16, endln:784:31 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 |UINT:2 |vpiTypespec: \_int_typespec: @@ -106896,7 +106896,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@fpu_wrap.NR_LOAD_PIPE_REGS), line:791:29, endln:791:46 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 |UINT:1 |vpiTypespec: \_int_typespec: , line:791:16, endln:791:28 @@ -106911,7 +106911,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@fpu_wrap.NR_SB_ENTRIES), line:779:16, endln:779:29 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 |UINT:8 |vpiTypespec: \_int_typespec: @@ -106924,7 +106924,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@fpu_wrap.NR_STORE_PIPE_REGS), line:792:29, endln:792:47 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 |UINT:0 |vpiTypespec: \_int_typespec: , line:792:16, endln:792:28 @@ -106939,7 +106939,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@fpu_wrap.NR_WB_PORTS), line:871:16, endln:871:27 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 |UINT:4 |vpiTypespec: \_int_typespec: @@ -106952,7 +106952,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@fpu_wrap.NSX), line:846:20, endln:846:23 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 |UINT:0 |vpiTypespec: \_bit_typespec: , line:846:16, endln:846:19 @@ -106968,7 +106968,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@fpu_wrap.NrMaxRules), line:682:16, endln:682:26 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 |UINT:16 |vpiTypespec: \_int_typespec: @@ -106981,7 +106981,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@fpu_wrap.PPN4K_WIDTH), line:1293:16, endln:1293:27 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 |UINT:38 |vpiTypespec: \_int_typespec: @@ -106994,7 +106994,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@fpu_wrap.REG_ADDR_SIZE), line:870:16, endln:870:29 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 |UINT:6 |vpiTypespec: \_int_typespec: @@ -107007,7 +107007,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@fpu_wrap.RVA), line:816:20, endln:816:23 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 |BIN:1 |vpiTypespec: \_bit_typespec: , line:816:16, endln:816:19 @@ -107023,7 +107023,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@fpu_wrap.RVD), line:814:20, endln:814:23 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 |INT:1 |vpiTypespec: \_bit_typespec: , line:814:16, endln:814:19 @@ -107039,7 +107039,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@fpu_wrap.RVF), line:813:20, endln:813:23 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 |INT:1 |vpiTypespec: \_bit_typespec: , line:813:16, endln:813:19 @@ -107055,7 +107055,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@fpu_wrap.RVFVEC), line:848:20, endln:848:26 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 |UINT:0 |vpiTypespec: \_bit_typespec: , line:848:16, endln:848:19 @@ -107071,7 +107071,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@fpu_wrap.SMODE_STATUS_READ_MASK), line:905:29, endln:905:51 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 |vpiTypespec: \_logic_typespec: , line:905:16, endln:905:28 |vpiParent: @@ -107105,7 +107105,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@fpu_wrap.SMODE_STATUS_WRITE_MASK), line:918:29, endln:918:52 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 |vpiTypespec: \_logic_typespec: , line:918:16, endln:918:28 |vpiParent: @@ -107139,7 +107139,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@fpu_wrap.SupervisorIrq), line:1013:16, endln:1013:29 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 |UINT:1 |vpiTypespec: \_int_typespec: @@ -107152,7 +107152,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@fpu_wrap.TRANS_ID_BITS), line:780:16, endln:780:29 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 |UINT:3 |vpiTypespec: \_int_typespec: @@ -107165,7 +107165,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@fpu_wrap.XF16), line:819:20, endln:819:24 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 |BIN:0 |vpiTypespec: \_bit_typespec: , line:819:16, endln:819:19 @@ -107181,7 +107181,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@fpu_wrap.XF16ALT), line:820:20, endln:820:27 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 |BIN:0 |vpiTypespec: \_bit_typespec: , line:820:16, endln:820:19 @@ -107197,7 +107197,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@fpu_wrap.XF16ALTVEC), line:850:20, endln:850:30 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 |UINT:0 |vpiTypespec: \_bit_typespec: , line:850:16, endln:850:19 @@ -107213,7 +107213,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@fpu_wrap.XF16VEC), line:849:20, endln:849:27 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 |UINT:0 |vpiTypespec: \_bit_typespec: , line:849:16, endln:849:19 @@ -107229,7 +107229,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@fpu_wrap.XF8), line:821:20, endln:821:23 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 |BIN:0 |vpiTypespec: \_bit_typespec: , line:821:16, endln:821:19 @@ -107245,7 +107245,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@fpu_wrap.XF8VEC), line:851:20, endln:851:26 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 |UINT:0 |vpiTypespec: \_bit_typespec: , line:851:16, endln:851:19 @@ -107261,7 +107261,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@fpu_wrap.XFVEC), line:822:20, endln:822:25 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 |BIN:0 |vpiTypespec: \_bit_typespec: , line:822:16, endln:822:19 @@ -107277,7 +107277,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@fpu_wrap.ZERO_TVAL), line:902:20, endln:902:29 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 |BIN:0 |vpiTypespec: \_bit_typespec: , line:902:16, endln:902:19 @@ -107293,7 +107293,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:682:16, endln:682:31 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 |vpiRhs: \_constant: , line:682:29, endln:682:31 |vpiParent: @@ -107322,7 +107322,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:706:29, endln:728:6 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 |vpiRhs: \_operation: , line:706:51, endln:728:6 |vpiParent: @@ -108134,7 +108134,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:779:16, endln:779:33 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 |vpiRhs: \_constant: , line:779:32, endln:779:33 |vpiParent: @@ -108163,7 +108163,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:780:16, endln:780:53 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 |vpiRhs: \_constant: , line:780:32, endln:780:53 |vpiParent: @@ -108192,7 +108192,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:782:16, endln:782:60 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 |vpiRhs: \_constant: , line:782:32, endln:782:51 |vpiParent: @@ -108221,7 +108221,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:783:16, endln:783:43 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 |vpiRhs: \_constant: , line:783:42, endln:783:43 |vpiParent: @@ -108250,7 +108250,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:784:16, endln:784:35 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 |vpiRhs: \_constant: , line:784:34, endln:784:35 |vpiParent: @@ -108279,7 +108279,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:786:16, endln:786:36 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 |vpiRhs: \_constant: , line:786:32, endln:786:36 |vpiParent: @@ -108336,7 +108336,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:788:16, endln:788:31 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 |vpiRhs: \_constant: , line:788:30, endln:788:31 |vpiParent: @@ -108365,7 +108365,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:791:29, endln:791:50 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 |vpiRhs: \_constant: , line:791:49, endln:791:50 |vpiParent: @@ -108398,7 +108398,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:792:29, endln:792:51 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 |vpiRhs: \_constant: , line:792:50, endln:792:51 |vpiParent: @@ -108431,7 +108431,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:795:29, endln:795:45 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 |vpiRhs: \_constant: , line:795:44, endln:795:45 |vpiParent: @@ -108464,7 +108464,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:804:29, endln:804:45 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 |vpiRhs: \_constant: , line:804:44, endln:804:45 |vpiParent: @@ -108497,7 +108497,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:813:20, endln:813:42 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 |vpiRhs: \_constant: , line:813:26, endln:813:33 |vpiParent: @@ -108532,7 +108532,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:814:20, endln:814:42 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 |vpiRhs: \_constant: , line:814:26, endln:814:33 |vpiParent: @@ -108567,7 +108567,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:816:20, endln:816:30 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 |vpiRhs: \_constant: , line:816:26, endln:816:30 |vpiParent: @@ -108602,7 +108602,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:819:20, endln:819:34 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 |vpiRhs: \_constant: , line:819:30, endln:819:34 |vpiParent: @@ -108637,7 +108637,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:820:20, endln:820:34 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 |vpiRhs: \_constant: , line:820:30, endln:820:34 |vpiParent: @@ -108672,7 +108672,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:821:20, endln:821:34 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 |vpiRhs: \_constant: , line:821:30, endln:821:34 |vpiParent: @@ -108707,7 +108707,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:822:20, endln:822:34 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 |vpiRhs: \_constant: , line:822:30, endln:822:34 |vpiParent: @@ -108742,7 +108742,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:825:29, endln:825:51 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 |vpiRhs: \_constant: , line:825:48, endln:825:51 |vpiParent: @@ -108775,7 +108775,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:826:29, endln:826:51 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 |vpiRhs: \_constant: , line:826:48, endln:826:51 |vpiParent: @@ -108808,7 +108808,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:827:29, endln:827:51 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 |vpiRhs: \_constant: , line:827:48, endln:827:51 |vpiParent: @@ -108841,7 +108841,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:828:29, endln:828:51 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 |vpiRhs: \_constant: , line:828:48, endln:828:51 |vpiParent: @@ -108874,7 +108874,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:829:29, endln:829:51 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 |vpiRhs: \_constant: , line:829:48, endln:829:51 |vpiParent: @@ -108907,7 +108907,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:830:29, endln:830:51 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 |vpiRhs: \_constant: , line:830:48, endln:830:51 |vpiParent: @@ -108940,7 +108940,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:831:29, endln:831:51 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 |vpiRhs: \_constant: , line:831:48, endln:831:51 |vpiParent: @@ -108973,7 +108973,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:832:29, endln:832:51 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 |vpiRhs: \_constant: , line:832:48, endln:832:51 |vpiParent: @@ -109006,7 +109006,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:836:20, endln:836:65 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 |vpiRhs: \_constant: , line:836:33, endln:836:59 |vpiParent: @@ -109041,7 +109041,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:839:16, endln:844:27 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 |vpiRhs: \_constant: , line:839:26, endln:839:29 |vpiParent: @@ -109070,7 +109070,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:846:20, endln:846:54 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 |vpiRhs: \_constant: , line:846:26, endln:846:46 |vpiParent: @@ -109105,7 +109105,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:848:20, endln:848:58 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 |vpiRhs: \_constant: , line:848:33, endln:848:48 |vpiParent: @@ -109140,7 +109140,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:849:20, endln:849:58 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 |vpiRhs: \_constant: , line:849:33, endln:849:48 |vpiParent: @@ -109175,7 +109175,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:850:20, endln:850:58 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 |vpiRhs: \_constant: , line:850:33, endln:850:48 |vpiParent: @@ -109210,7 +109210,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:851:20, endln:851:57 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 |vpiRhs: \_constant: , line:851:33, endln:851:48 |vpiParent: @@ -109245,7 +109245,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:855:30, endln:855:78 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 |vpiRhs: \_operation: , line:855:47, endln:855:78 |vpiParent: @@ -109340,7 +109340,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:857:30, endln:867:86 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 |vpiRhs: \_operation: , line:857:41, endln:867:86 |vpiParent: @@ -109707,7 +109707,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:870:16, endln:870:33 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 |vpiRhs: \_constant: , line:870:32, endln:870:33 |vpiParent: @@ -109736,7 +109736,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:871:16, endln:871:31 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 |vpiRhs: \_constant: , line:871:30, endln:871:31 |vpiParent: @@ -109765,7 +109765,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:874:31, endln:881:48 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 |vpiRhs: \_operation: , line:874:47, endln:881:48 |vpiParent: @@ -109887,7 +109887,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:884:20, endln:884:50 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 |vpiRhs: \_constant: , line:884:46, endln:884:50 |vpiParent: @@ -109922,7 +109922,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:890:22, endln:890:48 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 |vpiRhs: \_constant: , line:890:44, endln:890:48 |vpiParent: @@ -109955,7 +109955,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:900:20, endln:900:45 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 |vpiRhs: \_constant: , line:900:41, endln:900:45 |vpiParent: @@ -109990,7 +109990,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:901:20, endln:901:37 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 |vpiRhs: \_constant: , line:901:33, endln:901:37 |vpiParent: @@ -110025,7 +110025,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:902:20, endln:902:36 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 |vpiRhs: \_constant: , line:902:32, endln:902:36 |vpiParent: @@ -110060,7 +110060,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:905:29, endln:916:71 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 |vpiRhs: \_operation: , line:905:54, endln:916:71 |vpiParent: @@ -110566,7 +110566,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:918:29, endln:923:73 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 |vpiRhs: \_operation: , line:918:55, endln:923:73 |vpiParent: @@ -110833,7 +110833,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:929:29, endln:929:50 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 |vpiRhs: \_constant: , line:929:49, endln:929:50 |vpiParent: @@ -110866,7 +110866,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:930:29, endln:930:51 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 |vpiRhs: \_constant: , line:930:49, endln:930:51 |vpiParent: @@ -110899,7 +110899,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:932:29, endln:932:63 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 |vpiRhs: \_constant: , line:932:47, endln:932:58 |vpiParent: @@ -110932,7 +110932,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:1011:16, endln:1011:40 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 |vpiRhs: \_constant: , line:1011:35, endln:1011:40 |vpiParent: @@ -110989,7 +110989,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:1013:16, endln:1013:33 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 |vpiRhs: \_constant: , line:1013:32, endln:1013:33 |vpiParent: @@ -111018,7 +111018,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:1014:16, endln:1014:30 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 |vpiRhs: \_constant: , line:1014:29, endln:1014:30 |vpiParent: @@ -111047,7 +111047,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:1069:27, endln:1069:55 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 |vpiRhs: \_constant: , line:1069:48, endln:1069:50 |vpiParent: @@ -111080,7 +111080,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:1070:29, endln:1070:51 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 |vpiRhs: \_constant: , line:1070:50, endln:1070:51 |vpiParent: @@ -111113,7 +111113,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:1071:29, endln:1071:92 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 |vpiRhs: \_constant: , line:1071:50, endln:1071:92 |vpiParent: @@ -111146,7 +111146,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:1072:29, endln:1072:80 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 |vpiRhs: \_constant: , line:1072:50, endln:1072:61 |vpiParent: @@ -111179,7 +111179,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:1073:29, endln:1073:53 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 |vpiRhs: \_constant: , line:1073:50, endln:1073:53 |vpiParent: @@ -111212,7 +111212,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:1075:27, endln:1075:55 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 |vpiRhs: \_constant: , line:1075:48, endln:1075:50 |vpiParent: @@ -111245,7 +111245,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:1076:28, endln:1076:50 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 |vpiRhs: \_constant: , line:1076:49, endln:1076:50 |vpiParent: @@ -111278,7 +111278,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:1077:29, endln:1077:92 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 |vpiRhs: \_constant: , line:1077:50, endln:1077:92 |vpiParent: @@ -111311,7 +111311,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:1078:29, endln:1078:80 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 |vpiRhs: \_constant: , line:1078:50, endln:1078:61 |vpiParent: @@ -111344,7 +111344,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:1079:29, endln:1079:53 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 |vpiRhs: \_constant: , line:1079:50, endln:1079:53 |vpiParent: @@ -111377,7 +111377,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:1293:16, endln:1293:32 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1990:1, endln:2023:10 |vpiRhs: \_constant: , line:1293:30, endln:1293:32 |vpiParent: @@ -111499,27 +111499,27 @@ design: (work@top) |vpiTaskFunc: \_function: (ariane_pkg::extract_transfer_size), line:1458:5, endln:1482:16 |uhdmallModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2069:1, endln:2074:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2069:1, endln:2074:10 |vpiParent: \_design: (work@top) |vpiFullName:work@top |vpiDefName:work@top |uhdmtopModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2069:1, endln:2074:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2069:1, endln:2074:10 |vpiName:work@top |vpiDefName:work@top |vpiTop:1 |vpiTopModule:1 - |vpiModule: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 + |vpiModuleInst: + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2069:1, endln:2074:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2069:1, endln:2074:10 |vpiName:i_ariane |vpiFullName:work@top.i_ariane |vpiParameter: \_parameter: (work@top.i_ariane.ARIANE_MARCHID), line:855:30, endln:855:44 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 |vpiTypespec: \_logic_typespec: (xlen_t), line:30:13, endln:30:29 |vpiParent: @@ -111554,7 +111554,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.i_ariane.ASID_WIDTH), line:782:16, endln:782:26 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 |INT:16 |vpiTypespec: \_int_typespec: @@ -111567,7 +111567,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.i_ariane.ArianeDefaultConfig), line:706:29, endln:706:48 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 |vpiTypespec: \_struct_typespec: (ariane_pkg::ariane_cfg_t), line:684:13, endln:684:19 |vpiParent: @@ -112104,7 +112104,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.i_ariane.BITS_SATURATION_COUNTER), line:783:16, endln:783:39 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 |UINT:2 |vpiTypespec: \_int_typespec: @@ -112117,7 +112117,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.i_ariane.CONFIG_L1D_SIZE), line:1075:27, endln:1075:42 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 |INT:32768 |vpiTypespec: \_int_typespec: , line:1075:14, endln:1075:26 @@ -112132,7 +112132,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.i_ariane.CONFIG_L1I_SIZE), line:1069:27, endln:1069:42 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 |INT:16384 |vpiTypespec: \_int_typespec: , line:1069:14, endln:1069:26 @@ -112147,7 +112147,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.i_ariane.DCACHE_INDEX_WIDTH), line:1077:29, endln:1077:47 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 |UINT:12 |vpiTypespec: \_int_typespec: , line:1077:16, endln:1077:28 @@ -112162,7 +112162,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.i_ariane.DCACHE_LINE_WIDTH), line:1079:29, endln:1079:46 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 |UINT:128 |vpiTypespec: \_int_typespec: , line:1079:16, endln:1079:28 @@ -112177,7 +112177,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.i_ariane.DCACHE_SET_ASSOC), line:1076:28, endln:1076:44 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 |UINT:8 |vpiTypespec: \_int_typespec: , line:1076:15, endln:1076:27 @@ -112192,7 +112192,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.i_ariane.DCACHE_TAG_WIDTH), line:1078:29, endln:1078:45 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 |INT:44 |vpiTypespec: \_int_typespec: , line:1078:16, endln:1078:28 @@ -112207,7 +112207,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.i_ariane.DEPTH_COMMIT), line:804:29, endln:804:41 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 |UINT:8 |vpiTypespec: \_int_typespec: , line:804:16, endln:804:28 @@ -112222,7 +112222,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.i_ariane.DEPTH_SPEC), line:795:29, endln:795:39 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 |UINT:4 |vpiTypespec: \_int_typespec: , line:795:16, endln:795:28 @@ -112237,7 +112237,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.i_ariane.DebugHartInfo), line:874:31, endln:874:44 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 |vpiTypespec: \_unsupported_typespec: (dm::hartinfo_t), line:874:16, endln:874:20 |vpiParent: @@ -112252,7 +112252,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.i_ariane.ENABLE_CYCLE_COUNT), line:900:20, endln:900:38 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 |BIN:1 |vpiTypespec: \_bit_typespec: , line:900:16, endln:900:19 @@ -112268,7 +112268,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.i_ariane.ENABLE_RENAME), line:786:16, endln:786:29 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 |BIN:0 |vpiTypespec: \_int_typespec: @@ -112295,7 +112295,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.i_ariane.ENABLE_SPIKE_COMMIT_LOG), line:884:20, endln:884:43 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 |BIN:1 |vpiTypespec: \_bit_typespec: , line:884:16, endln:884:19 @@ -112311,7 +112311,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.i_ariane.ENABLE_WFI), line:901:20, endln:901:30 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 |BIN:1 |vpiTypespec: \_bit_typespec: , line:901:16, endln:901:19 @@ -112327,7 +112327,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.i_ariane.EXC_OFF_RST), line:1011:16, endln:1011:27 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 |HEX:80 |vpiTypespec: \_int_typespec: @@ -112354,7 +112354,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.i_ariane.FETCH_FIFO_DEPTH), line:929:29, endln:929:45 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 |UINT:4 |vpiTypespec: \_int_typespec: , line:929:16, endln:929:28 @@ -112369,7 +112369,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.i_ariane.FETCH_WIDTH), line:930:29, endln:930:40 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 |UINT:32 |vpiTypespec: \_int_typespec: , line:930:16, endln:930:28 @@ -112384,7 +112384,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.i_ariane.FLEN), line:839:16, endln:839:20 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 |INT:64 |vpiTypespec: \_int_typespec: @@ -112397,7 +112397,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.i_ariane.FP_PRESENT), line:836:20, endln:836:30 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 |UINT:1 |vpiTypespec: \_bit_typespec: , line:836:16, endln:836:19 @@ -112413,7 +112413,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.i_ariane.ICACHE_INDEX_WIDTH), line:1071:29, endln:1071:47 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 |UINT:12 |vpiTypespec: \_int_typespec: , line:1071:16, endln:1071:28 @@ -112428,7 +112428,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.i_ariane.ICACHE_LINE_WIDTH), line:1073:29, endln:1073:46 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 |UINT:128 |vpiTypespec: \_int_typespec: , line:1073:16, endln:1073:28 @@ -112443,7 +112443,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.i_ariane.ICACHE_SET_ASSOC), line:1070:29, endln:1070:45 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 |UINT:4 |vpiTypespec: \_int_typespec: , line:1070:16, endln:1070:28 @@ -112458,7 +112458,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.i_ariane.ICACHE_TAG_WIDTH), line:1072:29, endln:1072:45 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 |INT:44 |vpiTypespec: \_int_typespec: , line:1072:16, endln:1072:28 @@ -112473,7 +112473,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.i_ariane.INSTR_PER_FETCH), line:932:29, endln:932:44 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 |INT:2 |vpiTypespec: \_int_typespec: , line:932:16, endln:932:28 @@ -112488,7 +112488,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.i_ariane.INVALIDATE_ON_FLUSH), line:890:22, endln:890:41 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 |BIN:1 |vpiTypespec: \_logic_typespec: , line:890:16, endln:890:21 @@ -112503,7 +112503,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.i_ariane.ISA_CODE), line:857:30, endln:857:38 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 |vpiTypespec: \_logic_typespec: (xlen_t), line:30:13, endln:30:29 |vpiParent: @@ -112538,7 +112538,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.i_ariane.ISSUE_WIDTH), line:788:16, endln:788:27 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 |UINT:1 |vpiTypespec: \_int_typespec: @@ -112551,7 +112551,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.i_ariane.LAT_COMP_FP16), line:827:29, endln:827:42 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 |DEC:1 |vpiTypespec: \_int_typespec: , line:827:16, endln:827:28 @@ -112566,7 +112566,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.i_ariane.LAT_COMP_FP16ALT), line:828:29, endln:828:45 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 |DEC:1 |vpiTypespec: \_int_typespec: , line:828:16, endln:828:28 @@ -112581,7 +112581,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.i_ariane.LAT_COMP_FP32), line:825:29, endln:825:42 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 |DEC:2 |vpiTypespec: \_int_typespec: , line:825:16, endln:825:28 @@ -112596,7 +112596,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.i_ariane.LAT_COMP_FP64), line:826:29, endln:826:42 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 |DEC:3 |vpiTypespec: \_int_typespec: , line:826:16, endln:826:28 @@ -112611,7 +112611,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.i_ariane.LAT_COMP_FP8), line:829:29, endln:829:41 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 |DEC:1 |vpiTypespec: \_int_typespec: , line:829:16, endln:829:28 @@ -112626,7 +112626,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.i_ariane.LAT_CONV), line:832:29, endln:832:37 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 |DEC:2 |vpiTypespec: \_int_typespec: , line:832:16, endln:832:28 @@ -112641,7 +112641,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.i_ariane.LAT_DIVSQRT), line:830:29, endln:830:40 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 |DEC:2 |vpiTypespec: \_int_typespec: , line:830:16, endln:830:28 @@ -112656,7 +112656,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.i_ariane.LAT_NONCOMP), line:831:29, endln:831:40 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 |DEC:1 |vpiTypespec: \_int_typespec: , line:831:16, endln:831:28 @@ -112671,7 +112671,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.i_ariane.MachineIrq), line:1014:16, endln:1014:26 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 |UINT:0 |vpiTypespec: \_int_typespec: @@ -112684,7 +112684,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.i_ariane.NR_COMMIT_PORTS), line:784:16, endln:784:31 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 |UINT:2 |vpiTypespec: \_int_typespec: @@ -112697,7 +112697,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.i_ariane.NR_LOAD_PIPE_REGS), line:791:29, endln:791:46 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 |UINT:1 |vpiTypespec: \_int_typespec: , line:791:16, endln:791:28 @@ -112712,7 +112712,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.i_ariane.NR_SB_ENTRIES), line:779:16, endln:779:29 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 |UINT:8 |vpiTypespec: \_int_typespec: @@ -112725,7 +112725,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.i_ariane.NR_STORE_PIPE_REGS), line:792:29, endln:792:47 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 |UINT:0 |vpiTypespec: \_int_typespec: , line:792:16, endln:792:28 @@ -112740,7 +112740,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.i_ariane.NR_WB_PORTS), line:871:16, endln:871:27 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 |UINT:4 |vpiTypespec: \_int_typespec: @@ -112753,7 +112753,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.i_ariane.NSX), line:846:20, endln:846:23 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 |UINT:0 |vpiTypespec: \_bit_typespec: , line:846:16, endln:846:19 @@ -112769,7 +112769,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.i_ariane.NrMaxRules), line:682:16, endln:682:26 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 |UINT:16 |vpiTypespec: \_int_typespec: @@ -112782,7 +112782,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.i_ariane.PPN4K_WIDTH), line:1293:16, endln:1293:27 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 |UINT:38 |vpiTypespec: \_int_typespec: @@ -112795,7 +112795,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.i_ariane.REG_ADDR_SIZE), line:870:16, endln:870:29 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 |UINT:6 |vpiTypespec: \_int_typespec: @@ -112808,7 +112808,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.i_ariane.RVA), line:816:20, endln:816:23 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 |BIN:1 |vpiTypespec: \_bit_typespec: , line:816:16, endln:816:19 @@ -112824,7 +112824,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.i_ariane.RVD), line:814:20, endln:814:23 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 |INT:1 |vpiTypespec: \_bit_typespec: , line:814:16, endln:814:19 @@ -112840,7 +112840,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.i_ariane.RVF), line:813:20, endln:813:23 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 |INT:1 |vpiTypespec: \_bit_typespec: , line:813:16, endln:813:19 @@ -112856,7 +112856,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.i_ariane.RVFVEC), line:848:20, endln:848:26 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 |UINT:0 |vpiTypespec: \_bit_typespec: , line:848:16, endln:848:19 @@ -112872,7 +112872,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.i_ariane.SMODE_STATUS_READ_MASK), line:905:29, endln:905:51 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 |vpiTypespec: \_logic_typespec: , line:905:16, endln:905:28 |vpiParent: @@ -112906,7 +112906,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.i_ariane.SMODE_STATUS_WRITE_MASK), line:918:29, endln:918:52 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 |vpiTypespec: \_logic_typespec: , line:918:16, endln:918:28 |vpiParent: @@ -112940,7 +112940,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.i_ariane.SupervisorIrq), line:1013:16, endln:1013:29 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 |UINT:1 |vpiTypespec: \_int_typespec: @@ -112953,7 +112953,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.i_ariane.TRANS_ID_BITS), line:780:16, endln:780:29 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 |UINT:3 |vpiTypespec: \_int_typespec: @@ -112966,7 +112966,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.i_ariane.XF16), line:819:20, endln:819:24 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 |BIN:0 |vpiTypespec: \_bit_typespec: , line:819:16, endln:819:19 @@ -112982,7 +112982,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.i_ariane.XF16ALT), line:820:20, endln:820:27 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 |BIN:0 |vpiTypespec: \_bit_typespec: , line:820:16, endln:820:19 @@ -112998,7 +112998,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.i_ariane.XF16ALTVEC), line:850:20, endln:850:30 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 |UINT:0 |vpiTypespec: \_bit_typespec: , line:850:16, endln:850:19 @@ -113014,7 +113014,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.i_ariane.XF16VEC), line:849:20, endln:849:27 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 |UINT:0 |vpiTypespec: \_bit_typespec: , line:849:16, endln:849:19 @@ -113030,7 +113030,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.i_ariane.XF8), line:821:20, endln:821:23 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 |BIN:0 |vpiTypespec: \_bit_typespec: , line:821:16, endln:821:19 @@ -113046,7 +113046,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.i_ariane.XF8VEC), line:851:20, endln:851:26 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 |UINT:0 |vpiTypespec: \_bit_typespec: , line:851:16, endln:851:19 @@ -113062,7 +113062,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.i_ariane.XFVEC), line:822:20, endln:822:25 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 |BIN:0 |vpiTypespec: \_bit_typespec: , line:822:16, endln:822:19 @@ -113078,7 +113078,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.i_ariane.ZERO_TVAL), line:902:20, endln:902:29 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 |BIN:0 |vpiTypespec: \_bit_typespec: , line:902:16, endln:902:19 @@ -113094,7 +113094,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.i_ariane.ArianeCfg), line:2059:38, endln:2059:47 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 |vpiTypespec: \_struct_typespec: (ariane_pkg::ariane_cfg_t), line:684:13, endln:684:19 |vpiParent: @@ -113629,7 +113629,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:2059:38, endln:2059:85 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 |vpiOverriden:1 |vpiRhs: \_ref_obj: (ariane_soc::ArianeSocCfg), line:2071:19, endln:2071:29 @@ -113639,7 +113639,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:682:16, endln:682:31 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 |vpiRhs: \_constant: , line:682:29, endln:682:31 |vpiDecompile:16 @@ -113653,7 +113653,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:706:29, endln:728:6 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 |vpiRhs: \_operation: , line:706:51, endln:728:6 |vpiParent: @@ -114315,7 +114315,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:779:16, endln:779:33 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 |vpiRhs: \_constant: , line:779:32, endln:779:33 |vpiDecompile:8 @@ -114329,7 +114329,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:780:16, endln:780:53 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 |vpiRhs: \_constant: , line:780:32, endln:780:53 |vpiDecompile:3 @@ -114343,7 +114343,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:782:16, endln:782:60 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 |vpiRhs: \_constant: , line:782:32, endln:782:60 |vpiDecompile:16 @@ -114357,7 +114357,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:783:16, endln:783:43 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 |vpiRhs: \_constant: , line:783:42, endln:783:43 |vpiDecompile:2 @@ -114371,7 +114371,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:784:16, endln:784:35 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 |vpiRhs: \_constant: , line:784:34, endln:784:35 |vpiDecompile:2 @@ -114385,7 +114385,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:786:16, endln:786:36 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 |vpiRhs: \_constant: , line:786:32, endln:786:36 |vpiDecompile:1'b0 @@ -114399,7 +114399,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:788:16, endln:788:31 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 |vpiRhs: \_constant: , line:788:30, endln:788:31 |vpiDecompile:1 @@ -114413,7 +114413,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:791:29, endln:791:50 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 |vpiRhs: \_constant: , line:791:49, endln:791:50 |vpiDecompile:1 @@ -114427,7 +114427,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:792:29, endln:792:51 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 |vpiRhs: \_constant: , line:792:50, endln:792:51 |vpiDecompile:0 @@ -114441,7 +114441,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:795:29, endln:795:45 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 |vpiRhs: \_constant: , line:795:44, endln:795:45 |vpiDecompile:4 @@ -114455,7 +114455,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:804:29, endln:804:45 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 |vpiRhs: \_constant: , line:804:44, endln:804:45 |vpiDecompile:8 @@ -114469,7 +114469,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:813:20, endln:813:42 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 |vpiRhs: \_constant: , line:813:26, endln:813:42 |vpiDecompile:1 @@ -114483,7 +114483,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:814:20, endln:814:42 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 |vpiRhs: \_constant: , line:814:26, endln:814:42 |vpiDecompile:1 @@ -114497,7 +114497,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:816:20, endln:816:30 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 |vpiRhs: \_constant: , line:816:26, endln:816:30 |vpiDecompile:1'b1 @@ -114511,7 +114511,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:819:20, endln:819:34 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 |vpiRhs: \_constant: , line:819:30, endln:819:34 |vpiDecompile:1'b0 @@ -114525,7 +114525,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:820:20, endln:820:34 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 |vpiRhs: \_constant: , line:820:30, endln:820:34 |vpiDecompile:1'b0 @@ -114539,7 +114539,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:821:20, endln:821:34 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 |vpiRhs: \_constant: , line:821:30, endln:821:34 |vpiDecompile:1'b0 @@ -114553,7 +114553,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:822:20, endln:822:34 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 |vpiRhs: \_constant: , line:822:30, endln:822:34 |vpiDecompile:1'b0 @@ -114567,7 +114567,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:825:29, endln:825:51 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 |vpiRhs: \_constant: , line:825:48, endln:825:51 |vpiDecompile:2 @@ -114581,7 +114581,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:826:29, endln:826:51 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 |vpiRhs: \_constant: , line:826:48, endln:826:51 |vpiDecompile:3 @@ -114595,7 +114595,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:827:29, endln:827:51 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 |vpiRhs: \_constant: , line:827:48, endln:827:51 |vpiDecompile:1 @@ -114609,7 +114609,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:828:29, endln:828:51 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 |vpiRhs: \_constant: , line:828:48, endln:828:51 |vpiDecompile:1 @@ -114623,7 +114623,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:829:29, endln:829:51 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 |vpiRhs: \_constant: , line:829:48, endln:829:51 |vpiDecompile:1 @@ -114637,7 +114637,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:830:29, endln:830:51 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 |vpiRhs: \_constant: , line:830:48, endln:830:51 |vpiDecompile:2 @@ -114651,7 +114651,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:831:29, endln:831:51 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 |vpiRhs: \_constant: , line:831:48, endln:831:51 |vpiDecompile:1 @@ -114665,7 +114665,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:832:29, endln:832:51 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 |vpiRhs: \_constant: , line:832:48, endln:832:51 |vpiDecompile:2 @@ -114679,7 +114679,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:836:20, endln:836:65 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 |vpiRhs: \_constant: , line:836:33, endln:836:65 |vpiDecompile:1 @@ -114693,7 +114693,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:839:16, endln:844:27 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 |vpiRhs: \_constant: , line:839:26, endln:844:27 |vpiDecompile:64 @@ -114707,7 +114707,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:846:20, endln:846:54 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 |vpiRhs: \_constant: , line:846:26, endln:846:54 |vpiDecompile:0 @@ -114721,7 +114721,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:848:20, endln:848:58 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 |vpiRhs: \_constant: , line:848:33, endln:848:58 |vpiDecompile:0 @@ -114735,7 +114735,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:849:20, endln:849:58 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 |vpiRhs: \_constant: , line:849:33, endln:849:58 |vpiDecompile:0 @@ -114749,7 +114749,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:850:20, endln:850:58 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 |vpiRhs: \_constant: , line:850:33, endln:850:58 |vpiDecompile:0 @@ -114763,7 +114763,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:851:20, endln:851:57 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 |vpiRhs: \_constant: , line:851:33, endln:851:57 |vpiDecompile:0 @@ -114777,7 +114777,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:855:30, endln:855:78 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 |vpiRhs: \_operation: , line:855:47, endln:855:78 |vpiTypespec: @@ -114864,7 +114864,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:857:30, endln:867:86 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 |vpiRhs: \_operation: , line:857:41, endln:867:86 |vpiTypespec: @@ -115227,7 +115227,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:870:16, endln:870:33 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 |vpiRhs: \_constant: , line:870:32, endln:870:33 |vpiDecompile:6 @@ -115241,7 +115241,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:871:16, endln:871:31 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 |vpiRhs: \_constant: , line:871:30, endln:871:31 |vpiDecompile:4 @@ -115255,7 +115255,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:874:31, endln:881:48 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 |vpiRhs: \_operation: , line:874:47, endln:881:48 |vpiParent: @@ -115364,7 +115364,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:884:20, endln:884:50 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 |vpiRhs: \_constant: , line:884:46, endln:884:50 |vpiDecompile:1'b1 @@ -115378,7 +115378,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:890:22, endln:890:48 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 |vpiRhs: \_constant: , line:890:44, endln:890:48 |vpiDecompile:1'b1 @@ -115392,7 +115392,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:900:20, endln:900:45 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 |vpiRhs: \_constant: , line:900:41, endln:900:45 |vpiDecompile:1'b1 @@ -115406,7 +115406,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:901:20, endln:901:37 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 |vpiRhs: \_constant: , line:901:33, endln:901:37 |vpiDecompile:1'b1 @@ -115420,7 +115420,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:902:20, endln:902:36 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 |vpiRhs: \_constant: , line:902:32, endln:902:36 |vpiDecompile:1'b0 @@ -115434,7 +115434,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:905:29, endln:916:71 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 |vpiRhs: \_operation: , line:905:54, endln:916:71 |vpiTypespec: @@ -115930,7 +115930,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:918:29, endln:923:73 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 |vpiRhs: \_operation: , line:918:55, endln:923:73 |vpiTypespec: @@ -116189,7 +116189,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:929:29, endln:929:50 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 |vpiRhs: \_constant: , line:929:49, endln:929:50 |vpiDecompile:4 @@ -116203,7 +116203,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:930:29, endln:930:51 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 |vpiRhs: \_constant: , line:930:49, endln:930:51 |vpiDecompile:32 @@ -116217,7 +116217,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:932:29, endln:932:63 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 |vpiRhs: \_constant: , line:932:47, endln:932:63 |vpiDecompile:2 @@ -116231,7 +116231,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:1011:16, endln:1011:40 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 |vpiRhs: \_constant: , line:1011:35, endln:1011:40 |vpiDecompile:8'h80 @@ -116245,7 +116245,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:1013:16, endln:1013:33 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 |vpiRhs: \_constant: , line:1013:32, endln:1013:33 |vpiDecompile:1 @@ -116259,7 +116259,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:1014:16, endln:1014:30 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 |vpiRhs: \_constant: , line:1014:29, endln:1014:30 |vpiDecompile:0 @@ -116273,7 +116273,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:1069:27, endln:1069:55 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 |vpiRhs: \_constant: , line:1069:48, endln:1069:55 |vpiDecompile:16384 @@ -116287,7 +116287,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:1070:29, endln:1070:51 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 |vpiRhs: \_constant: , line:1070:50, endln:1070:51 |vpiDecompile:4 @@ -116301,7 +116301,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:1071:29, endln:1071:92 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 |vpiRhs: \_constant: , line:1071:50, endln:1071:92 |vpiDecompile:12 @@ -116315,7 +116315,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:1072:29, endln:1072:80 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 |vpiRhs: \_constant: , line:1072:50, endln:1072:80 |vpiDecompile:44 @@ -116329,7 +116329,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:1073:29, endln:1073:53 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 |vpiRhs: \_constant: , line:1073:50, endln:1073:53 |vpiDecompile:128 @@ -116343,7 +116343,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:1075:27, endln:1075:55 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 |vpiRhs: \_constant: , line:1075:48, endln:1075:55 |vpiDecompile:32768 @@ -116357,7 +116357,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:1076:28, endln:1076:50 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 |vpiRhs: \_constant: , line:1076:49, endln:1076:50 |vpiDecompile:8 @@ -116371,7 +116371,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:1077:29, endln:1077:92 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 |vpiRhs: \_constant: , line:1077:50, endln:1077:92 |vpiDecompile:12 @@ -116385,7 +116385,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:1078:29, endln:1078:80 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 |vpiRhs: \_constant: , line:1078:50, endln:1078:80 |vpiDecompile:44 @@ -116399,7 +116399,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:1079:29, endln:1079:53 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 |vpiRhs: \_constant: , line:1079:50, endln:1079:53 |vpiDecompile:128 @@ -116413,7 +116413,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:1293:16, endln:1293:32 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 |vpiRhs: \_constant: , line:1293:30, endln:1293:32 |vpiDecompile:38 @@ -116488,13 +116488,13 @@ design: (work@top) |vpiTaskFunc: \_function: (ariane_pkg::check_cfg), line:731:5, endln:743:16 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 |vpiName:check_cfg |vpiFullName:ariane_pkg::check_cfg |vpiVisibility:1 |vpiAutomatic:1 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 |vpiIODecl: \_io_decl: (Cfg), line:731:53, endln:731:56 |vpiParent: @@ -116795,11 +116795,11 @@ design: (work@top) |vpiOperand: \_constant: , line:740:36, endln:740:38 |vpiInstance: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 |vpiTaskFunc: \_function: (ariane_pkg::range_check), line:745:5, endln:748:30 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 |vpiName:range_check |vpiFullName:ariane_pkg::range_check |vpiVisibility:1 @@ -116807,7 +116807,7 @@ design: (work@top) |vpiReturn: \_logic_var: , line:745:24, endln:745:29 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 |vpiIODecl: \_io_decl: (base), line:745:54, endln:745:58 |vpiParent: @@ -116897,11 +116897,11 @@ design: (work@top) |vpiActual: \_io_decl: (len), line:745:72, endln:745:75 |vpiInstance: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 |vpiTaskFunc: \_function: (ariane_pkg::is_inside_nonidempotent_regions), line:750:5, endln:757:50 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 |vpiName:is_inside_nonidempotent_regions |vpiFullName:ariane_pkg::is_inside_nonidempotent_regions |vpiVariables: @@ -116917,7 +116917,7 @@ design: (work@top) |vpiReturn: \_logic_var: , line:750:24, endln:750:29 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 |vpiIODecl: \_io_decl: (Cfg), line:750:76, endln:750:79 |vpiParent: @@ -117161,11 +117161,11 @@ design: (work@top) |vpiActual: \_logic_var: (ariane_pkg::is_inside_nonidempotent_regions::pass), line:751:29, endln:751:33 |vpiInstance: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 |vpiTaskFunc: \_function: (ariane_pkg::is_inside_execute_regions), line:759:5, endln:767:44 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 |vpiName:is_inside_execute_regions |vpiFullName:ariane_pkg::is_inside_execute_regions |vpiVariables: @@ -117181,7 +117181,7 @@ design: (work@top) |vpiReturn: \_logic_var: , line:759:24, endln:759:29 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 |vpiIODecl: \_io_decl: (Cfg), line:759:70, endln:759:73 |vpiParent: @@ -117425,11 +117425,11 @@ design: (work@top) |vpiActual: \_logic_var: (ariane_pkg::is_inside_execute_regions::pass), line:761:29, endln:761:33 |vpiInstance: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 |vpiTaskFunc: \_function: (ariane_pkg::is_inside_cacheable_regions), line:769:5, endln:776:46 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 |vpiName:is_inside_cacheable_regions |vpiFullName:ariane_pkg::is_inside_cacheable_regions |vpiVariables: @@ -117446,7 +117446,7 @@ design: (work@top) |vpiReturn: \_logic_var: , line:769:24, endln:769:29 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 |vpiIODecl: \_io_decl: (Cfg), line:769:72, endln:769:75 |vpiParent: @@ -117691,11 +117691,11 @@ design: (work@top) |vpiActual: \_logic_var: (ariane_pkg::is_inside_cacheable_regions::pass), line:770:39, endln:770:43 |vpiInstance: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 |vpiTaskFunc: \_function: (ariane_pkg::op_is_branch), line:1132:5, endln:1137:16 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 |vpiName:op_is_branch |vpiFullName:ariane_pkg::op_is_branch |vpiVisibility:1 @@ -117703,7 +117703,7 @@ design: (work@top) |vpiReturn: \_logic_var: , line:1132:24, endln:1132:29 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 |vpiIODecl: \_io_decl: (op), line:1132:56, endln:1132:58 |vpiParent: @@ -117830,11 +117830,11 @@ design: (work@top) |vpiCondition: \_constant: , line:1135:48, endln:1135:52 |vpiInstance: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 |vpiTaskFunc: \_function: (ariane_pkg::is_rs1_fpr), line:1142:5, endln:1157:16 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 |vpiName:is_rs1_fpr |vpiFullName:ariane_pkg::is_rs1_fpr |vpiVisibility:1 @@ -117842,7 +117842,7 @@ design: (work@top) |vpiReturn: \_logic_var: , line:1142:24, endln:1142:29 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 |vpiIODecl: \_io_decl: (op), line:1142:54, endln:1142:56 |vpiParent: @@ -118034,11 +118034,11 @@ design: (work@top) |vpiCondition: \_constant: , line:1156:20, endln:1156:24 |vpiInstance: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 |vpiTaskFunc: \_function: (ariane_pkg::is_rs2_fpr), line:1159:5, endln:1173:16 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 |vpiName:is_rs2_fpr |vpiFullName:ariane_pkg::is_rs2_fpr |vpiVisibility:1 @@ -118046,7 +118046,7 @@ design: (work@top) |vpiReturn: \_logic_var: , line:1159:24, endln:1159:29 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 |vpiIODecl: \_io_decl: (op), line:1159:54, endln:1159:56 |vpiParent: @@ -118249,11 +118249,11 @@ design: (work@top) |vpiCondition: \_constant: , line:1172:20, endln:1172:24 |vpiInstance: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 |vpiTaskFunc: \_function: (ariane_pkg::is_imm_fpr), line:1176:5, endln:1186:16 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 |vpiName:is_imm_fpr |vpiFullName:ariane_pkg::is_imm_fpr |vpiVisibility:1 @@ -118261,7 +118261,7 @@ design: (work@top) |vpiReturn: \_logic_var: , line:1176:24, endln:1176:29 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 |vpiIODecl: \_io_decl: (op), line:1176:54, endln:1176:56 |vpiParent: @@ -118396,11 +118396,11 @@ design: (work@top) |vpiCondition: \_constant: , line:1185:20, endln:1185:24 |vpiInstance: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 |vpiTaskFunc: \_function: (ariane_pkg::is_rd_fpr), line:1188:5, endln:1203:16 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 |vpiName:is_rd_fpr |vpiFullName:ariane_pkg::is_rd_fpr |vpiVisibility:1 @@ -118408,7 +118408,7 @@ design: (work@top) |vpiReturn: \_logic_var: , line:1188:24, endln:1188:29 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 |vpiIODecl: \_io_decl: (op), line:1188:53, endln:1188:55 |vpiParent: @@ -118616,11 +118616,11 @@ design: (work@top) |vpiCondition: \_constant: , line:1202:20, endln:1202:24 |vpiInstance: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 |vpiTaskFunc: \_function: (ariane_pkg::is_amo), line:1205:5, endln:1212:16 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 |vpiName:is_amo |vpiFullName:ariane_pkg::is_amo |vpiVisibility:1 @@ -118628,7 +118628,7 @@ design: (work@top) |vpiReturn: \_logic_var: , line:1205:24, endln:1205:29 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 |vpiIODecl: \_io_decl: (op), line:1205:44, endln:1205:46 |vpiParent: @@ -118702,11 +118702,11 @@ design: (work@top) |vpiCondition: \_constant: , line:1210:29, endln:1210:33 |vpiInstance: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 |vpiTaskFunc: \_function: (ariane_pkg::sext32), line:1373:5, endln:1375:16 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 |vpiName:sext32 |vpiFullName:ariane_pkg::sext32 |vpiVisibility:1 @@ -118714,7 +118714,7 @@ design: (work@top) |vpiReturn: \_logic_var: , line:1373:24, endln:1373:37 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 |vpiIODecl: \_io_decl: (operand), line:1373:59, endln:1373:66 |vpiParent: @@ -118784,11 +118784,11 @@ design: (work@top) |vpiRightRange: \_constant: , line:1374:59, endln:1374:60 |vpiInstance: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 |vpiTaskFunc: \_function: (ariane_pkg::uj_imm), line:1380:5, endln:1382:16 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 |vpiName:uj_imm |vpiFullName:ariane_pkg::uj_imm |vpiVisibility:1 @@ -118796,7 +118796,7 @@ design: (work@top) |vpiReturn: \_logic_var: , line:1380:24, endln:1380:47 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 |vpiIODecl: \_io_decl: (instruction_i), line:1380:69, endln:1380:82 |vpiParent: @@ -118907,11 +118907,11 @@ design: (work@top) |vpiOperand: \_constant: , line:1381:122, endln:1381:126 |vpiInstance: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 |vpiTaskFunc: \_function: (ariane_pkg::i_imm), line:1384:5, endln:1386:16 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 |vpiName:i_imm |vpiFullName:ariane_pkg::i_imm |vpiVisibility:1 @@ -118919,7 +118919,7 @@ design: (work@top) |vpiReturn: \_logic_var: , line:1384:24, endln:1384:47 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 |vpiIODecl: \_io_decl: (instruction_i), line:1384:68, endln:1384:81 |vpiParent: @@ -118996,11 +118996,11 @@ design: (work@top) |vpiRightRange: \_constant: , line:1385:76, endln:1385:78 |vpiInstance: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 |vpiTaskFunc: \_function: (ariane_pkg::sb_imm), line:1388:5, endln:1390:16 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 |vpiName:sb_imm |vpiFullName:ariane_pkg::sb_imm |vpiVisibility:1 @@ -119008,7 +119008,7 @@ design: (work@top) |vpiReturn: \_logic_var: , line:1388:24, endln:1388:47 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 |vpiIODecl: \_io_decl: (instruction_i), line:1388:69, endln:1388:82 |vpiParent: @@ -119135,11 +119135,11 @@ design: (work@top) |vpiOperand: \_constant: , line:1389:139, endln:1389:143 |vpiInstance: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 |vpiTaskFunc: \_function: (ariane_pkg::data_align), line:1396:5, endln:1411:16 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 |vpiName:data_align |vpiFullName:ariane_pkg::data_align |vpiVariables: @@ -119163,7 +119163,7 @@ design: (work@top) |vpiReturn: \_logic_var: , line:1396:24, endln:1396:37 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 |vpiIODecl: \_io_decl: (addr), line:1396:62, endln:1396:66 |vpiParent: @@ -119894,11 +119894,11 @@ design: (work@top) |vpiRightRange: \_constant: , line:1410:39, endln:1410:40 |vpiInstance: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 |vpiTaskFunc: \_function: (ariane_pkg::be_gen), line:1414:5, endln:1453:16 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 |vpiName:be_gen |vpiFullName:ariane_pkg::be_gen |vpiVisibility:1 @@ -119906,7 +119906,7 @@ design: (work@top) |vpiReturn: \_logic_var: , line:1414:24, endln:1414:35 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 |vpiIODecl: \_io_decl: (addr), line:1414:55, endln:1414:59 |vpiParent: @@ -120301,11 +120301,11 @@ design: (work@top) |vpiCondition: \_constant: , line:1452:16, endln:1452:20 |vpiInstance: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 |vpiTaskFunc: \_function: (ariane_pkg::extract_transfer_size), line:1458:5, endln:1482:16 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 |vpiName:extract_transfer_size |vpiFullName:ariane_pkg::extract_transfer_size |vpiVisibility:1 @@ -120313,7 +120313,7 @@ design: (work@top) |vpiReturn: \_logic_var: , line:1458:24, endln:1458:35 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 |vpiIODecl: \_io_decl: (op), line:1458:64, endln:1458:66 |vpiParent: @@ -120724,19 +120724,19 @@ design: (work@top) |vpiCondition: \_constant: , line:1480:33, endln:1480:38 |vpiInstance: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2069:1, endln:2074:10 - |vpiModule: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2069:1, endln:2074:10 + |vpiModuleInst: + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 |vpiName:ex_stage_i |vpiFullName:work@top.i_ariane.ex_stage_i |vpiParameter: \_parameter: (work@top.i_ariane.ex_stage_i.ARIANE_MARCHID), line:855:30, endln:855:44 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 |vpiTypespec: \_logic_typespec: (xlen_t), line:30:13, endln:30:29 |vpiParent: @@ -120771,7 +120771,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.i_ariane.ex_stage_i.ASID_WIDTH), line:782:16, endln:782:26 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 |INT:16 |vpiTypespec: \_int_typespec: @@ -120784,7 +120784,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.i_ariane.ex_stage_i.ArianeDefaultConfig), line:706:29, endln:706:48 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 |vpiTypespec: \_struct_typespec: (ariane_pkg::ariane_cfg_t), line:684:13, endln:684:19 |vpiParent: @@ -121321,7 +121321,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.i_ariane.ex_stage_i.BITS_SATURATION_COUNTER), line:783:16, endln:783:39 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 |UINT:2 |vpiTypespec: \_int_typespec: @@ -121334,7 +121334,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.i_ariane.ex_stage_i.CONFIG_L1D_SIZE), line:1075:27, endln:1075:42 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 |INT:32768 |vpiTypespec: \_int_typespec: , line:1075:14, endln:1075:26 @@ -121349,7 +121349,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.i_ariane.ex_stage_i.CONFIG_L1I_SIZE), line:1069:27, endln:1069:42 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 |INT:16384 |vpiTypespec: \_int_typespec: , line:1069:14, endln:1069:26 @@ -121364,7 +121364,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.i_ariane.ex_stage_i.DCACHE_INDEX_WIDTH), line:1077:29, endln:1077:47 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 |UINT:12 |vpiTypespec: \_int_typespec: , line:1077:16, endln:1077:28 @@ -121379,7 +121379,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.i_ariane.ex_stage_i.DCACHE_LINE_WIDTH), line:1079:29, endln:1079:46 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 |UINT:128 |vpiTypespec: \_int_typespec: , line:1079:16, endln:1079:28 @@ -121394,7 +121394,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.i_ariane.ex_stage_i.DCACHE_SET_ASSOC), line:1076:28, endln:1076:44 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 |UINT:8 |vpiTypespec: \_int_typespec: , line:1076:15, endln:1076:27 @@ -121409,7 +121409,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.i_ariane.ex_stage_i.DCACHE_TAG_WIDTH), line:1078:29, endln:1078:45 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 |INT:44 |vpiTypespec: \_int_typespec: , line:1078:16, endln:1078:28 @@ -121424,7 +121424,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.i_ariane.ex_stage_i.DEPTH_COMMIT), line:804:29, endln:804:41 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 |UINT:8 |vpiTypespec: \_int_typespec: , line:804:16, endln:804:28 @@ -121439,7 +121439,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.i_ariane.ex_stage_i.DEPTH_SPEC), line:795:29, endln:795:39 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 |UINT:4 |vpiTypespec: \_int_typespec: , line:795:16, endln:795:28 @@ -121454,7 +121454,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.i_ariane.ex_stage_i.DebugHartInfo), line:874:31, endln:874:44 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 |vpiTypespec: \_unsupported_typespec: (dm::hartinfo_t), line:874:16, endln:874:20 |vpiParent: @@ -121469,7 +121469,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.i_ariane.ex_stage_i.ENABLE_CYCLE_COUNT), line:900:20, endln:900:38 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 |BIN:1 |vpiTypespec: \_bit_typespec: , line:900:16, endln:900:19 @@ -121485,7 +121485,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.i_ariane.ex_stage_i.ENABLE_RENAME), line:786:16, endln:786:29 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 |BIN:0 |vpiTypespec: \_int_typespec: @@ -121512,7 +121512,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.i_ariane.ex_stage_i.ENABLE_SPIKE_COMMIT_LOG), line:884:20, endln:884:43 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 |BIN:1 |vpiTypespec: \_bit_typespec: , line:884:16, endln:884:19 @@ -121528,7 +121528,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.i_ariane.ex_stage_i.ENABLE_WFI), line:901:20, endln:901:30 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 |BIN:1 |vpiTypespec: \_bit_typespec: , line:901:16, endln:901:19 @@ -121544,7 +121544,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.i_ariane.ex_stage_i.EXC_OFF_RST), line:1011:16, endln:1011:27 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 |HEX:80 |vpiTypespec: \_int_typespec: @@ -121571,7 +121571,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.i_ariane.ex_stage_i.FETCH_FIFO_DEPTH), line:929:29, endln:929:45 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 |UINT:4 |vpiTypespec: \_int_typespec: , line:929:16, endln:929:28 @@ -121586,7 +121586,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.i_ariane.ex_stage_i.FETCH_WIDTH), line:930:29, endln:930:40 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 |UINT:32 |vpiTypespec: \_int_typespec: , line:930:16, endln:930:28 @@ -121601,7 +121601,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.i_ariane.ex_stage_i.FLEN), line:839:16, endln:839:20 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 |INT:64 |vpiTypespec: \_int_typespec: @@ -121614,7 +121614,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.i_ariane.ex_stage_i.FP_PRESENT), line:836:20, endln:836:30 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 |UINT:1 |vpiTypespec: \_bit_typespec: , line:836:16, endln:836:19 @@ -121630,7 +121630,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.i_ariane.ex_stage_i.ICACHE_INDEX_WIDTH), line:1071:29, endln:1071:47 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 |UINT:12 |vpiTypespec: \_int_typespec: , line:1071:16, endln:1071:28 @@ -121645,7 +121645,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.i_ariane.ex_stage_i.ICACHE_LINE_WIDTH), line:1073:29, endln:1073:46 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 |UINT:128 |vpiTypespec: \_int_typespec: , line:1073:16, endln:1073:28 @@ -121660,7 +121660,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.i_ariane.ex_stage_i.ICACHE_SET_ASSOC), line:1070:29, endln:1070:45 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 |UINT:4 |vpiTypespec: \_int_typespec: , line:1070:16, endln:1070:28 @@ -121675,7 +121675,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.i_ariane.ex_stage_i.ICACHE_TAG_WIDTH), line:1072:29, endln:1072:45 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 |INT:44 |vpiTypespec: \_int_typespec: , line:1072:16, endln:1072:28 @@ -121690,7 +121690,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.i_ariane.ex_stage_i.INSTR_PER_FETCH), line:932:29, endln:932:44 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 |INT:2 |vpiTypespec: \_int_typespec: , line:932:16, endln:932:28 @@ -121705,7 +121705,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.i_ariane.ex_stage_i.INVALIDATE_ON_FLUSH), line:890:22, endln:890:41 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 |BIN:1 |vpiTypespec: \_logic_typespec: , line:890:16, endln:890:21 @@ -121720,7 +121720,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.i_ariane.ex_stage_i.ISA_CODE), line:857:30, endln:857:38 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 |vpiTypespec: \_logic_typespec: (xlen_t), line:30:13, endln:30:29 |vpiParent: @@ -121755,7 +121755,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.i_ariane.ex_stage_i.ISSUE_WIDTH), line:788:16, endln:788:27 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 |UINT:1 |vpiTypespec: \_int_typespec: @@ -121768,7 +121768,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.i_ariane.ex_stage_i.LAT_COMP_FP16), line:827:29, endln:827:42 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 |DEC:1 |vpiTypespec: \_int_typespec: , line:827:16, endln:827:28 @@ -121783,7 +121783,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.i_ariane.ex_stage_i.LAT_COMP_FP16ALT), line:828:29, endln:828:45 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 |DEC:1 |vpiTypespec: \_int_typespec: , line:828:16, endln:828:28 @@ -121798,7 +121798,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.i_ariane.ex_stage_i.LAT_COMP_FP32), line:825:29, endln:825:42 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 |DEC:2 |vpiTypespec: \_int_typespec: , line:825:16, endln:825:28 @@ -121813,7 +121813,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.i_ariane.ex_stage_i.LAT_COMP_FP64), line:826:29, endln:826:42 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 |DEC:3 |vpiTypespec: \_int_typespec: , line:826:16, endln:826:28 @@ -121828,7 +121828,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.i_ariane.ex_stage_i.LAT_COMP_FP8), line:829:29, endln:829:41 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 |DEC:1 |vpiTypespec: \_int_typespec: , line:829:16, endln:829:28 @@ -121843,7 +121843,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.i_ariane.ex_stage_i.LAT_CONV), line:832:29, endln:832:37 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 |DEC:2 |vpiTypespec: \_int_typespec: , line:832:16, endln:832:28 @@ -121858,7 +121858,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.i_ariane.ex_stage_i.LAT_DIVSQRT), line:830:29, endln:830:40 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 |DEC:2 |vpiTypespec: \_int_typespec: , line:830:16, endln:830:28 @@ -121873,7 +121873,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.i_ariane.ex_stage_i.LAT_NONCOMP), line:831:29, endln:831:40 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 |DEC:1 |vpiTypespec: \_int_typespec: , line:831:16, endln:831:28 @@ -121888,7 +121888,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.i_ariane.ex_stage_i.MachineIrq), line:1014:16, endln:1014:26 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 |UINT:0 |vpiTypespec: \_int_typespec: @@ -121901,7 +121901,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.i_ariane.ex_stage_i.NR_COMMIT_PORTS), line:784:16, endln:784:31 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 |UINT:2 |vpiTypespec: \_int_typespec: @@ -121914,7 +121914,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.i_ariane.ex_stage_i.NR_LOAD_PIPE_REGS), line:791:29, endln:791:46 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 |UINT:1 |vpiTypespec: \_int_typespec: , line:791:16, endln:791:28 @@ -121929,7 +121929,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.i_ariane.ex_stage_i.NR_SB_ENTRIES), line:779:16, endln:779:29 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 |UINT:8 |vpiTypespec: \_int_typespec: @@ -121942,7 +121942,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.i_ariane.ex_stage_i.NR_STORE_PIPE_REGS), line:792:29, endln:792:47 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 |UINT:0 |vpiTypespec: \_int_typespec: , line:792:16, endln:792:28 @@ -121957,7 +121957,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.i_ariane.ex_stage_i.NR_WB_PORTS), line:871:16, endln:871:27 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 |UINT:4 |vpiTypespec: \_int_typespec: @@ -121970,7 +121970,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.i_ariane.ex_stage_i.NSX), line:846:20, endln:846:23 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 |UINT:0 |vpiTypespec: \_bit_typespec: , line:846:16, endln:846:19 @@ -121986,7 +121986,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.i_ariane.ex_stage_i.NrMaxRules), line:682:16, endln:682:26 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 |UINT:16 |vpiTypespec: \_int_typespec: @@ -121999,7 +121999,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.i_ariane.ex_stage_i.PPN4K_WIDTH), line:1293:16, endln:1293:27 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 |UINT:38 |vpiTypespec: \_int_typespec: @@ -122012,7 +122012,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.i_ariane.ex_stage_i.REG_ADDR_SIZE), line:870:16, endln:870:29 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 |UINT:6 |vpiTypespec: \_int_typespec: @@ -122025,7 +122025,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.i_ariane.ex_stage_i.RVA), line:816:20, endln:816:23 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 |BIN:1 |vpiTypespec: \_bit_typespec: , line:816:16, endln:816:19 @@ -122041,7 +122041,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.i_ariane.ex_stage_i.RVD), line:814:20, endln:814:23 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 |INT:1 |vpiTypespec: \_bit_typespec: , line:814:16, endln:814:19 @@ -122057,7 +122057,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.i_ariane.ex_stage_i.RVF), line:813:20, endln:813:23 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 |INT:1 |vpiTypespec: \_bit_typespec: , line:813:16, endln:813:19 @@ -122073,7 +122073,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.i_ariane.ex_stage_i.RVFVEC), line:848:20, endln:848:26 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 |UINT:0 |vpiTypespec: \_bit_typespec: , line:848:16, endln:848:19 @@ -122089,7 +122089,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.i_ariane.ex_stage_i.SMODE_STATUS_READ_MASK), line:905:29, endln:905:51 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 |vpiTypespec: \_logic_typespec: , line:905:16, endln:905:28 |vpiParent: @@ -122123,7 +122123,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.i_ariane.ex_stage_i.SMODE_STATUS_WRITE_MASK), line:918:29, endln:918:52 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 |vpiTypespec: \_logic_typespec: , line:918:16, endln:918:28 |vpiParent: @@ -122157,7 +122157,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.i_ariane.ex_stage_i.SupervisorIrq), line:1013:16, endln:1013:29 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 |UINT:1 |vpiTypespec: \_int_typespec: @@ -122170,7 +122170,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.i_ariane.ex_stage_i.TRANS_ID_BITS), line:780:16, endln:780:29 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 |UINT:3 |vpiTypespec: \_int_typespec: @@ -122183,7 +122183,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.i_ariane.ex_stage_i.XF16), line:819:20, endln:819:24 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 |BIN:0 |vpiTypespec: \_bit_typespec: , line:819:16, endln:819:19 @@ -122199,7 +122199,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.i_ariane.ex_stage_i.XF16ALT), line:820:20, endln:820:27 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 |BIN:0 |vpiTypespec: \_bit_typespec: , line:820:16, endln:820:19 @@ -122215,7 +122215,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.i_ariane.ex_stage_i.XF16ALTVEC), line:850:20, endln:850:30 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 |UINT:0 |vpiTypespec: \_bit_typespec: , line:850:16, endln:850:19 @@ -122231,7 +122231,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.i_ariane.ex_stage_i.XF16VEC), line:849:20, endln:849:27 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 |UINT:0 |vpiTypespec: \_bit_typespec: , line:849:16, endln:849:19 @@ -122247,7 +122247,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.i_ariane.ex_stage_i.XF8), line:821:20, endln:821:23 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 |BIN:0 |vpiTypespec: \_bit_typespec: , line:821:16, endln:821:19 @@ -122263,7 +122263,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.i_ariane.ex_stage_i.XF8VEC), line:851:20, endln:851:26 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 |UINT:0 |vpiTypespec: \_bit_typespec: , line:851:16, endln:851:19 @@ -122279,7 +122279,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.i_ariane.ex_stage_i.XFVEC), line:822:20, endln:822:25 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 |BIN:0 |vpiTypespec: \_bit_typespec: , line:822:16, endln:822:19 @@ -122295,7 +122295,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.i_ariane.ex_stage_i.ZERO_TVAL), line:902:20, endln:902:29 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 |BIN:0 |vpiTypespec: \_bit_typespec: , line:902:16, endln:902:19 @@ -122311,7 +122311,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.i_ariane.ex_stage_i.ASID_WIDTH), line:2026:28, endln:2026:38 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 |UINT:1 |vpiTypespec: \_int_typespec: , line:2026:15, endln:2026:27 @@ -122322,7 +122322,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.i_ariane.ex_stage_i.ArianeCfg), line:2027:40, endln:2027:49 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 |vpiTypespec: \_struct_typespec: (ariane_pkg::ariane_cfg_t), line:684:13, endln:684:19 |vpiParent: @@ -122857,7 +122857,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:2026:28, endln:2026:42 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 |vpiOverriden:1 |vpiRhs: \_constant: , line:2026:41, endln:2026:42 @@ -122872,7 +122872,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:2027:40, endln:2027:83 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 |vpiOverriden:1 |vpiRhs: \_ref_obj: (ariane_soc::ArianeSocCfg), line:2063:19, endln:2063:28 @@ -122884,7 +122884,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:682:16, endln:682:31 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 |vpiRhs: \_constant: , line:682:29, endln:682:31 |vpiDecompile:16 @@ -122898,7 +122898,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:706:29, endln:728:6 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 |vpiRhs: \_operation: , line:706:51, endln:728:6 |vpiParent: @@ -123560,7 +123560,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:779:16, endln:779:33 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 |vpiRhs: \_constant: , line:779:32, endln:779:33 |vpiDecompile:8 @@ -123574,7 +123574,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:780:16, endln:780:53 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 |vpiRhs: \_constant: , line:780:32, endln:780:53 |vpiDecompile:3 @@ -123588,7 +123588,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:782:16, endln:782:60 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 |vpiOverriden:1 |vpiRhs: \_constant: , line:782:32, endln:782:60 @@ -123603,7 +123603,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:783:16, endln:783:43 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 |vpiRhs: \_constant: , line:783:42, endln:783:43 |vpiDecompile:2 @@ -123617,7 +123617,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:784:16, endln:784:35 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 |vpiRhs: \_constant: , line:784:34, endln:784:35 |vpiDecompile:2 @@ -123631,7 +123631,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:786:16, endln:786:36 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 |vpiRhs: \_constant: , line:786:32, endln:786:36 |vpiDecompile:1'b0 @@ -123645,7 +123645,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:788:16, endln:788:31 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 |vpiRhs: \_constant: , line:788:30, endln:788:31 |vpiDecompile:1 @@ -123659,7 +123659,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:791:29, endln:791:50 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 |vpiRhs: \_constant: , line:791:49, endln:791:50 |vpiDecompile:1 @@ -123673,7 +123673,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:792:29, endln:792:51 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 |vpiRhs: \_constant: , line:792:50, endln:792:51 |vpiDecompile:0 @@ -123687,7 +123687,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:795:29, endln:795:45 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 |vpiRhs: \_constant: , line:795:44, endln:795:45 |vpiDecompile:4 @@ -123701,7 +123701,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:804:29, endln:804:45 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 |vpiRhs: \_constant: , line:804:44, endln:804:45 |vpiDecompile:8 @@ -123715,7 +123715,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:813:20, endln:813:42 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 |vpiRhs: \_constant: , line:813:26, endln:813:42 |vpiDecompile:1 @@ -123729,7 +123729,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:814:20, endln:814:42 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 |vpiRhs: \_constant: , line:814:26, endln:814:42 |vpiDecompile:1 @@ -123743,7 +123743,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:816:20, endln:816:30 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 |vpiRhs: \_constant: , line:816:26, endln:816:30 |vpiDecompile:1'b1 @@ -123757,7 +123757,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:819:20, endln:819:34 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 |vpiRhs: \_constant: , line:819:30, endln:819:34 |vpiDecompile:1'b0 @@ -123771,7 +123771,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:820:20, endln:820:34 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 |vpiRhs: \_constant: , line:820:30, endln:820:34 |vpiDecompile:1'b0 @@ -123785,7 +123785,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:821:20, endln:821:34 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 |vpiRhs: \_constant: , line:821:30, endln:821:34 |vpiDecompile:1'b0 @@ -123799,7 +123799,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:822:20, endln:822:34 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 |vpiRhs: \_constant: , line:822:30, endln:822:34 |vpiDecompile:1'b0 @@ -123813,7 +123813,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:825:29, endln:825:51 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 |vpiRhs: \_constant: , line:825:48, endln:825:51 |vpiDecompile:2 @@ -123827,7 +123827,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:826:29, endln:826:51 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 |vpiRhs: \_constant: , line:826:48, endln:826:51 |vpiDecompile:3 @@ -123841,7 +123841,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:827:29, endln:827:51 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 |vpiRhs: \_constant: , line:827:48, endln:827:51 |vpiDecompile:1 @@ -123855,7 +123855,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:828:29, endln:828:51 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 |vpiRhs: \_constant: , line:828:48, endln:828:51 |vpiDecompile:1 @@ -123869,7 +123869,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:829:29, endln:829:51 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 |vpiRhs: \_constant: , line:829:48, endln:829:51 |vpiDecompile:1 @@ -123883,7 +123883,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:830:29, endln:830:51 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 |vpiRhs: \_constant: , line:830:48, endln:830:51 |vpiDecompile:2 @@ -123897,7 +123897,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:831:29, endln:831:51 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 |vpiRhs: \_constant: , line:831:48, endln:831:51 |vpiDecompile:1 @@ -123911,7 +123911,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:832:29, endln:832:51 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 |vpiRhs: \_constant: , line:832:48, endln:832:51 |vpiDecompile:2 @@ -123925,7 +123925,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:836:20, endln:836:65 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 |vpiRhs: \_constant: , line:836:33, endln:836:65 |vpiDecompile:1 @@ -123939,7 +123939,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:839:16, endln:844:27 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 |vpiRhs: \_constant: , line:839:26, endln:844:27 |vpiDecompile:64 @@ -123953,7 +123953,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:846:20, endln:846:54 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 |vpiRhs: \_constant: , line:846:26, endln:846:54 |vpiDecompile:0 @@ -123967,7 +123967,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:848:20, endln:848:58 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 |vpiRhs: \_constant: , line:848:33, endln:848:58 |vpiDecompile:0 @@ -123981,7 +123981,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:849:20, endln:849:58 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 |vpiRhs: \_constant: , line:849:33, endln:849:58 |vpiDecompile:0 @@ -123995,7 +123995,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:850:20, endln:850:58 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 |vpiRhs: \_constant: , line:850:33, endln:850:58 |vpiDecompile:0 @@ -124009,7 +124009,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:851:20, endln:851:57 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 |vpiRhs: \_constant: , line:851:33, endln:851:57 |vpiDecompile:0 @@ -124023,7 +124023,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:855:30, endln:855:78 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 |vpiRhs: \_operation: , line:855:47, endln:855:78 |vpiTypespec: @@ -124110,7 +124110,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:857:30, endln:867:86 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 |vpiRhs: \_operation: , line:857:41, endln:867:86 |vpiTypespec: @@ -124473,7 +124473,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:870:16, endln:870:33 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 |vpiRhs: \_constant: , line:870:32, endln:870:33 |vpiDecompile:6 @@ -124487,7 +124487,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:871:16, endln:871:31 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 |vpiRhs: \_constant: , line:871:30, endln:871:31 |vpiDecompile:4 @@ -124501,7 +124501,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:874:31, endln:881:48 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 |vpiRhs: \_operation: , line:874:47, endln:881:48 |vpiParent: @@ -124610,7 +124610,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:884:20, endln:884:50 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 |vpiRhs: \_constant: , line:884:46, endln:884:50 |vpiDecompile:1'b1 @@ -124624,7 +124624,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:890:22, endln:890:48 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 |vpiRhs: \_constant: , line:890:44, endln:890:48 |vpiDecompile:1'b1 @@ -124638,7 +124638,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:900:20, endln:900:45 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 |vpiRhs: \_constant: , line:900:41, endln:900:45 |vpiDecompile:1'b1 @@ -124652,7 +124652,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:901:20, endln:901:37 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 |vpiRhs: \_constant: , line:901:33, endln:901:37 |vpiDecompile:1'b1 @@ -124666,7 +124666,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:902:20, endln:902:36 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 |vpiRhs: \_constant: , line:902:32, endln:902:36 |vpiDecompile:1'b0 @@ -124680,7 +124680,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:905:29, endln:916:71 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 |vpiRhs: \_operation: , line:905:54, endln:916:71 |vpiTypespec: @@ -125176,7 +125176,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:918:29, endln:923:73 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 |vpiRhs: \_operation: , line:918:55, endln:923:73 |vpiTypespec: @@ -125435,7 +125435,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:929:29, endln:929:50 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 |vpiRhs: \_constant: , line:929:49, endln:929:50 |vpiDecompile:4 @@ -125449,7 +125449,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:930:29, endln:930:51 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 |vpiRhs: \_constant: , line:930:49, endln:930:51 |vpiDecompile:32 @@ -125463,7 +125463,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:932:29, endln:932:63 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 |vpiRhs: \_constant: , line:932:47, endln:932:63 |vpiDecompile:2 @@ -125477,7 +125477,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:1011:16, endln:1011:40 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 |vpiRhs: \_constant: , line:1011:35, endln:1011:40 |vpiDecompile:8'h80 @@ -125491,7 +125491,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:1013:16, endln:1013:33 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 |vpiRhs: \_constant: , line:1013:32, endln:1013:33 |vpiDecompile:1 @@ -125505,7 +125505,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:1014:16, endln:1014:30 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 |vpiRhs: \_constant: , line:1014:29, endln:1014:30 |vpiDecompile:0 @@ -125519,7 +125519,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:1069:27, endln:1069:55 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 |vpiRhs: \_constant: , line:1069:48, endln:1069:55 |vpiDecompile:16384 @@ -125533,7 +125533,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:1070:29, endln:1070:51 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 |vpiRhs: \_constant: , line:1070:50, endln:1070:51 |vpiDecompile:4 @@ -125547,7 +125547,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:1071:29, endln:1071:92 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 |vpiRhs: \_constant: , line:1071:50, endln:1071:92 |vpiDecompile:12 @@ -125561,7 +125561,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:1072:29, endln:1072:80 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 |vpiRhs: \_constant: , line:1072:50, endln:1072:80 |vpiDecompile:44 @@ -125575,7 +125575,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:1073:29, endln:1073:53 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 |vpiRhs: \_constant: , line:1073:50, endln:1073:53 |vpiDecompile:128 @@ -125589,7 +125589,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:1075:27, endln:1075:55 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 |vpiRhs: \_constant: , line:1075:48, endln:1075:55 |vpiDecompile:32768 @@ -125603,7 +125603,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:1076:28, endln:1076:50 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 |vpiRhs: \_constant: , line:1076:49, endln:1076:50 |vpiDecompile:8 @@ -125617,7 +125617,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:1077:29, endln:1077:92 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 |vpiRhs: \_constant: , line:1077:50, endln:1077:92 |vpiDecompile:12 @@ -125631,7 +125631,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:1078:29, endln:1078:80 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 |vpiRhs: \_constant: , line:1078:50, endln:1078:80 |vpiDecompile:44 @@ -125645,7 +125645,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:1079:29, endln:1079:53 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 |vpiRhs: \_constant: , line:1079:50, endln:1079:53 |vpiDecompile:128 @@ -125659,7 +125659,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:1293:16, endln:1293:32 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 |vpiRhs: \_constant: , line:1293:30, endln:1293:32 |vpiDecompile:38 @@ -125734,13 +125734,13 @@ design: (work@top) |vpiTaskFunc: \_function: (ariane_pkg::check_cfg), line:731:5, endln:743:16 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 |vpiName:check_cfg |vpiFullName:ariane_pkg::check_cfg |vpiVisibility:1 |vpiAutomatic:1 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 |vpiIODecl: \_io_decl: (Cfg), line:731:53, endln:731:56 |vpiParent: @@ -126041,11 +126041,11 @@ design: (work@top) |vpiOperand: \_constant: , line:740:36, endln:740:38 |vpiInstance: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 |vpiTaskFunc: \_function: (ariane_pkg::range_check), line:745:5, endln:748:30 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 |vpiName:range_check |vpiFullName:ariane_pkg::range_check |vpiVisibility:1 @@ -126053,7 +126053,7 @@ design: (work@top) |vpiReturn: \_logic_var: , line:745:24, endln:745:29 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 |vpiIODecl: \_io_decl: (base), line:745:54, endln:745:58 |vpiParent: @@ -126143,11 +126143,11 @@ design: (work@top) |vpiActual: \_io_decl: (len), line:745:72, endln:745:75 |vpiInstance: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 |vpiTaskFunc: \_function: (ariane_pkg::is_inside_nonidempotent_regions), line:750:5, endln:757:50 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 |vpiName:is_inside_nonidempotent_regions |vpiFullName:ariane_pkg::is_inside_nonidempotent_regions |vpiVariables: @@ -126163,7 +126163,7 @@ design: (work@top) |vpiReturn: \_logic_var: , line:750:24, endln:750:29 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 |vpiIODecl: \_io_decl: (Cfg), line:750:76, endln:750:79 |vpiParent: @@ -126407,11 +126407,11 @@ design: (work@top) |vpiActual: \_logic_var: (ariane_pkg::is_inside_nonidempotent_regions::pass), line:751:29, endln:751:33 |vpiInstance: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 |vpiTaskFunc: \_function: (ariane_pkg::is_inside_execute_regions), line:759:5, endln:767:44 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 |vpiName:is_inside_execute_regions |vpiFullName:ariane_pkg::is_inside_execute_regions |vpiVariables: @@ -126427,7 +126427,7 @@ design: (work@top) |vpiReturn: \_logic_var: , line:759:24, endln:759:29 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 |vpiIODecl: \_io_decl: (Cfg), line:759:70, endln:759:73 |vpiParent: @@ -126671,11 +126671,11 @@ design: (work@top) |vpiActual: \_logic_var: (ariane_pkg::is_inside_execute_regions::pass), line:761:29, endln:761:33 |vpiInstance: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 |vpiTaskFunc: \_function: (ariane_pkg::is_inside_cacheable_regions), line:769:5, endln:776:46 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 |vpiName:is_inside_cacheable_regions |vpiFullName:ariane_pkg::is_inside_cacheable_regions |vpiVariables: @@ -126692,7 +126692,7 @@ design: (work@top) |vpiReturn: \_logic_var: , line:769:24, endln:769:29 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 |vpiIODecl: \_io_decl: (Cfg), line:769:72, endln:769:75 |vpiParent: @@ -126937,11 +126937,11 @@ design: (work@top) |vpiActual: \_logic_var: (ariane_pkg::is_inside_cacheable_regions::pass), line:770:39, endln:770:43 |vpiInstance: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 |vpiTaskFunc: \_function: (ariane_pkg::op_is_branch), line:1132:5, endln:1137:16 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 |vpiName:op_is_branch |vpiFullName:ariane_pkg::op_is_branch |vpiVisibility:1 @@ -126949,7 +126949,7 @@ design: (work@top) |vpiReturn: \_logic_var: , line:1132:24, endln:1132:29 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 |vpiIODecl: \_io_decl: (op), line:1132:56, endln:1132:58 |vpiParent: @@ -127076,11 +127076,11 @@ design: (work@top) |vpiCondition: \_constant: , line:1135:48, endln:1135:52 |vpiInstance: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 |vpiTaskFunc: \_function: (ariane_pkg::is_rs1_fpr), line:1142:5, endln:1157:16 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 |vpiName:is_rs1_fpr |vpiFullName:ariane_pkg::is_rs1_fpr |vpiVisibility:1 @@ -127088,7 +127088,7 @@ design: (work@top) |vpiReturn: \_logic_var: , line:1142:24, endln:1142:29 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 |vpiIODecl: \_io_decl: (op), line:1142:54, endln:1142:56 |vpiParent: @@ -127280,11 +127280,11 @@ design: (work@top) |vpiCondition: \_constant: , line:1156:20, endln:1156:24 |vpiInstance: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 |vpiTaskFunc: \_function: (ariane_pkg::is_rs2_fpr), line:1159:5, endln:1173:16 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 |vpiName:is_rs2_fpr |vpiFullName:ariane_pkg::is_rs2_fpr |vpiVisibility:1 @@ -127292,7 +127292,7 @@ design: (work@top) |vpiReturn: \_logic_var: , line:1159:24, endln:1159:29 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 |vpiIODecl: \_io_decl: (op), line:1159:54, endln:1159:56 |vpiParent: @@ -127495,11 +127495,11 @@ design: (work@top) |vpiCondition: \_constant: , line:1172:20, endln:1172:24 |vpiInstance: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 |vpiTaskFunc: \_function: (ariane_pkg::is_imm_fpr), line:1176:5, endln:1186:16 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 |vpiName:is_imm_fpr |vpiFullName:ariane_pkg::is_imm_fpr |vpiVisibility:1 @@ -127507,7 +127507,7 @@ design: (work@top) |vpiReturn: \_logic_var: , line:1176:24, endln:1176:29 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 |vpiIODecl: \_io_decl: (op), line:1176:54, endln:1176:56 |vpiParent: @@ -127642,11 +127642,11 @@ design: (work@top) |vpiCondition: \_constant: , line:1185:20, endln:1185:24 |vpiInstance: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 |vpiTaskFunc: \_function: (ariane_pkg::is_rd_fpr), line:1188:5, endln:1203:16 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 |vpiName:is_rd_fpr |vpiFullName:ariane_pkg::is_rd_fpr |vpiVisibility:1 @@ -127654,7 +127654,7 @@ design: (work@top) |vpiReturn: \_logic_var: , line:1188:24, endln:1188:29 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 |vpiIODecl: \_io_decl: (op), line:1188:53, endln:1188:55 |vpiParent: @@ -127862,11 +127862,11 @@ design: (work@top) |vpiCondition: \_constant: , line:1202:20, endln:1202:24 |vpiInstance: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 |vpiTaskFunc: \_function: (ariane_pkg::is_amo), line:1205:5, endln:1212:16 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 |vpiName:is_amo |vpiFullName:ariane_pkg::is_amo |vpiVisibility:1 @@ -127874,7 +127874,7 @@ design: (work@top) |vpiReturn: \_logic_var: , line:1205:24, endln:1205:29 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 |vpiIODecl: \_io_decl: (op), line:1205:44, endln:1205:46 |vpiParent: @@ -127948,11 +127948,11 @@ design: (work@top) |vpiCondition: \_constant: , line:1210:29, endln:1210:33 |vpiInstance: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 |vpiTaskFunc: \_function: (ariane_pkg::sext32), line:1373:5, endln:1375:16 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 |vpiName:sext32 |vpiFullName:ariane_pkg::sext32 |vpiVisibility:1 @@ -127960,7 +127960,7 @@ design: (work@top) |vpiReturn: \_logic_var: , line:1373:24, endln:1373:37 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 |vpiIODecl: \_io_decl: (operand), line:1373:59, endln:1373:66 |vpiParent: @@ -128030,11 +128030,11 @@ design: (work@top) |vpiRightRange: \_constant: , line:1374:59, endln:1374:60 |vpiInstance: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 |vpiTaskFunc: \_function: (ariane_pkg::uj_imm), line:1380:5, endln:1382:16 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 |vpiName:uj_imm |vpiFullName:ariane_pkg::uj_imm |vpiVisibility:1 @@ -128042,7 +128042,7 @@ design: (work@top) |vpiReturn: \_logic_var: , line:1380:24, endln:1380:47 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 |vpiIODecl: \_io_decl: (instruction_i), line:1380:69, endln:1380:82 |vpiParent: @@ -128153,11 +128153,11 @@ design: (work@top) |vpiOperand: \_constant: , line:1381:122, endln:1381:126 |vpiInstance: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 |vpiTaskFunc: \_function: (ariane_pkg::i_imm), line:1384:5, endln:1386:16 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 |vpiName:i_imm |vpiFullName:ariane_pkg::i_imm |vpiVisibility:1 @@ -128165,7 +128165,7 @@ design: (work@top) |vpiReturn: \_logic_var: , line:1384:24, endln:1384:47 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 |vpiIODecl: \_io_decl: (instruction_i), line:1384:68, endln:1384:81 |vpiParent: @@ -128242,11 +128242,11 @@ design: (work@top) |vpiRightRange: \_constant: , line:1385:76, endln:1385:78 |vpiInstance: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 |vpiTaskFunc: \_function: (ariane_pkg::sb_imm), line:1388:5, endln:1390:16 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 |vpiName:sb_imm |vpiFullName:ariane_pkg::sb_imm |vpiVisibility:1 @@ -128254,7 +128254,7 @@ design: (work@top) |vpiReturn: \_logic_var: , line:1388:24, endln:1388:47 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 |vpiIODecl: \_io_decl: (instruction_i), line:1388:69, endln:1388:82 |vpiParent: @@ -128381,11 +128381,11 @@ design: (work@top) |vpiOperand: \_constant: , line:1389:139, endln:1389:143 |vpiInstance: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 |vpiTaskFunc: \_function: (ariane_pkg::data_align), line:1396:5, endln:1411:16 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 |vpiName:data_align |vpiFullName:ariane_pkg::data_align |vpiVariables: @@ -128409,7 +128409,7 @@ design: (work@top) |vpiReturn: \_logic_var: , line:1396:24, endln:1396:37 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 |vpiIODecl: \_io_decl: (addr), line:1396:62, endln:1396:66 |vpiParent: @@ -129140,11 +129140,11 @@ design: (work@top) |vpiRightRange: \_constant: , line:1410:39, endln:1410:40 |vpiInstance: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 |vpiTaskFunc: \_function: (ariane_pkg::be_gen), line:1414:5, endln:1453:16 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 |vpiName:be_gen |vpiFullName:ariane_pkg::be_gen |vpiVisibility:1 @@ -129152,7 +129152,7 @@ design: (work@top) |vpiReturn: \_logic_var: , line:1414:24, endln:1414:35 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 |vpiIODecl: \_io_decl: (addr), line:1414:55, endln:1414:59 |vpiParent: @@ -129547,11 +129547,11 @@ design: (work@top) |vpiCondition: \_constant: , line:1452:16, endln:1452:20 |vpiInstance: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 |vpiTaskFunc: \_function: (ariane_pkg::extract_transfer_size), line:1458:5, endln:1482:16 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 |vpiName:extract_transfer_size |vpiFullName:ariane_pkg::extract_transfer_size |vpiVisibility:1 @@ -129559,7 +129559,7 @@ design: (work@top) |vpiReturn: \_logic_var: , line:1458:24, endln:1458:35 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 |vpiIODecl: \_io_decl: (op), line:1458:64, endln:1458:66 |vpiParent: @@ -129970,13 +129970,13 @@ design: (work@top) |vpiCondition: \_constant: , line:1480:33, endln:1480:38 |vpiInstance: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 |vpiInstance: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2070:5, endln:2072:21 |vpiGenScopeArray: \_gen_scope_array: (work@top.i_ariane.ex_stage_i.fpu_gen), line:2031:9, endln:2051:5 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2061:3, endln:2064:23 |vpiName:fpu_gen |vpiFullName:work@top.i_ariane.ex_stage_i.fpu_gen |vpiGenScope: @@ -130121,8 +130121,8 @@ design: (work@top) |vpiFullName:work@top.i_ariane.ex_stage_i.fpu_gen.fpu_data |vpiActual: \_struct_var: (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_data), line:2032:23, endln:2032:31 - |vpiModule: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 + |vpiModuleInst: + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 |vpiParent: \_gen_scope: (work@top.i_ariane.ex_stage_i.fpu_gen) |vpiName:fpu_i @@ -131705,7 +131705,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:682:16, endln:682:31 |vpiParent: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 |vpiRhs: \_constant: , line:682:29, endln:682:31 |vpiDecompile:16 @@ -131719,7 +131719,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:706:29, endln:728:6 |vpiParent: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 |vpiRhs: \_operation: , line:706:51, endln:728:6 |vpiParent: @@ -132381,7 +132381,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:779:16, endln:779:33 |vpiParent: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 |vpiRhs: \_constant: , line:779:32, endln:779:33 |vpiDecompile:8 @@ -132395,7 +132395,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:780:16, endln:780:53 |vpiParent: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 |vpiRhs: \_constant: , line:780:32, endln:780:53 |vpiDecompile:3 @@ -132409,7 +132409,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:782:16, endln:782:60 |vpiParent: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 |vpiRhs: \_constant: , line:782:32, endln:782:60 |vpiDecompile:16 @@ -132423,7 +132423,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:783:16, endln:783:43 |vpiParent: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 |vpiRhs: \_constant: , line:783:42, endln:783:43 |vpiDecompile:2 @@ -132437,7 +132437,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:784:16, endln:784:35 |vpiParent: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 |vpiRhs: \_constant: , line:784:34, endln:784:35 |vpiDecompile:2 @@ -132451,7 +132451,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:786:16, endln:786:36 |vpiParent: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 |vpiRhs: \_constant: , line:786:32, endln:786:36 |vpiDecompile:1'b0 @@ -132465,7 +132465,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:788:16, endln:788:31 |vpiParent: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 |vpiRhs: \_constant: , line:788:30, endln:788:31 |vpiDecompile:1 @@ -132479,7 +132479,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:791:29, endln:791:50 |vpiParent: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 |vpiRhs: \_constant: , line:791:49, endln:791:50 |vpiDecompile:1 @@ -132493,7 +132493,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:792:29, endln:792:51 |vpiParent: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 |vpiRhs: \_constant: , line:792:50, endln:792:51 |vpiDecompile:0 @@ -132507,7 +132507,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:795:29, endln:795:45 |vpiParent: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 |vpiRhs: \_constant: , line:795:44, endln:795:45 |vpiDecompile:4 @@ -132521,7 +132521,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:804:29, endln:804:45 |vpiParent: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 |vpiRhs: \_constant: , line:804:44, endln:804:45 |vpiDecompile:8 @@ -132535,7 +132535,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:813:20, endln:813:42 |vpiParent: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 |vpiRhs: \_constant: , line:813:26, endln:813:42 |vpiDecompile:1 @@ -132549,7 +132549,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:814:20, endln:814:42 |vpiParent: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 |vpiRhs: \_constant: , line:814:26, endln:814:42 |vpiDecompile:1 @@ -132563,7 +132563,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:816:20, endln:816:30 |vpiParent: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 |vpiRhs: \_constant: , line:816:26, endln:816:30 |vpiDecompile:1'b1 @@ -132577,7 +132577,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:819:20, endln:819:34 |vpiParent: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 |vpiRhs: \_constant: , line:819:30, endln:819:34 |vpiDecompile:1'b0 @@ -132591,7 +132591,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:820:20, endln:820:34 |vpiParent: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 |vpiRhs: \_constant: , line:820:30, endln:820:34 |vpiDecompile:1'b0 @@ -132605,7 +132605,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:821:20, endln:821:34 |vpiParent: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 |vpiRhs: \_constant: , line:821:30, endln:821:34 |vpiDecompile:1'b0 @@ -132619,7 +132619,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:822:20, endln:822:34 |vpiParent: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 |vpiRhs: \_constant: , line:822:30, endln:822:34 |vpiDecompile:1'b0 @@ -132633,7 +132633,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:825:29, endln:825:51 |vpiParent: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 |vpiRhs: \_constant: , line:825:48, endln:825:51 |vpiDecompile:2 @@ -132647,7 +132647,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:826:29, endln:826:51 |vpiParent: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 |vpiRhs: \_constant: , line:826:48, endln:826:51 |vpiDecompile:3 @@ -132661,7 +132661,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:827:29, endln:827:51 |vpiParent: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 |vpiRhs: \_constant: , line:827:48, endln:827:51 |vpiDecompile:1 @@ -132675,7 +132675,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:828:29, endln:828:51 |vpiParent: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 |vpiRhs: \_constant: , line:828:48, endln:828:51 |vpiDecompile:1 @@ -132689,7 +132689,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:829:29, endln:829:51 |vpiParent: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 |vpiRhs: \_constant: , line:829:48, endln:829:51 |vpiDecompile:1 @@ -132703,7 +132703,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:830:29, endln:830:51 |vpiParent: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 |vpiRhs: \_constant: , line:830:48, endln:830:51 |vpiDecompile:2 @@ -132717,7 +132717,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:831:29, endln:831:51 |vpiParent: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 |vpiRhs: \_constant: , line:831:48, endln:831:51 |vpiDecompile:1 @@ -132731,7 +132731,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:832:29, endln:832:51 |vpiParent: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 |vpiRhs: \_constant: , line:832:48, endln:832:51 |vpiDecompile:2 @@ -132745,7 +132745,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:836:20, endln:836:65 |vpiParent: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 |vpiRhs: \_constant: , line:836:33, endln:836:65 |vpiDecompile:1 @@ -132759,7 +132759,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:839:16, endln:844:27 |vpiParent: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 |vpiRhs: \_constant: , line:839:26, endln:844:27 |vpiDecompile:64 @@ -132773,7 +132773,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:846:20, endln:846:54 |vpiParent: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 |vpiRhs: \_constant: , line:846:26, endln:846:54 |vpiDecompile:0 @@ -132787,7 +132787,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:848:20, endln:848:58 |vpiParent: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 |vpiRhs: \_constant: , line:848:33, endln:848:58 |vpiDecompile:0 @@ -132801,7 +132801,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:849:20, endln:849:58 |vpiParent: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 |vpiRhs: \_constant: , line:849:33, endln:849:58 |vpiDecompile:0 @@ -132815,7 +132815,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:850:20, endln:850:58 |vpiParent: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 |vpiRhs: \_constant: , line:850:33, endln:850:58 |vpiDecompile:0 @@ -132829,7 +132829,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:851:20, endln:851:57 |vpiParent: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 |vpiRhs: \_constant: , line:851:33, endln:851:57 |vpiDecompile:0 @@ -132843,7 +132843,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:855:30, endln:855:78 |vpiParent: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 |vpiRhs: \_operation: , line:855:47, endln:855:78 |vpiParent: @@ -132932,7 +132932,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:857:30, endln:867:86 |vpiParent: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 |vpiRhs: \_operation: , line:857:41, endln:867:86 |vpiParent: @@ -133301,7 +133301,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:870:16, endln:870:33 |vpiParent: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 |vpiRhs: \_constant: , line:870:32, endln:870:33 |vpiDecompile:6 @@ -133315,7 +133315,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:871:16, endln:871:31 |vpiParent: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 |vpiRhs: \_constant: , line:871:30, endln:871:31 |vpiDecompile:4 @@ -133329,7 +133329,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:874:31, endln:881:48 |vpiParent: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 |vpiRhs: \_operation: , line:874:47, endln:881:48 |vpiParent: @@ -133438,7 +133438,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:884:20, endln:884:50 |vpiParent: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 |vpiRhs: \_constant: , line:884:46, endln:884:50 |vpiDecompile:1'b1 @@ -133452,7 +133452,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:890:22, endln:890:48 |vpiParent: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 |vpiRhs: \_constant: , line:890:44, endln:890:48 |vpiDecompile:1'b1 @@ -133466,7 +133466,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:900:20, endln:900:45 |vpiParent: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 |vpiRhs: \_constant: , line:900:41, endln:900:45 |vpiDecompile:1'b1 @@ -133480,7 +133480,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:901:20, endln:901:37 |vpiParent: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 |vpiRhs: \_constant: , line:901:33, endln:901:37 |vpiDecompile:1'b1 @@ -133494,7 +133494,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:902:20, endln:902:36 |vpiParent: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 |vpiRhs: \_constant: , line:902:32, endln:902:36 |vpiDecompile:1'b0 @@ -133508,7 +133508,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:905:29, endln:916:71 |vpiParent: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 |vpiRhs: \_operation: , line:905:54, endln:916:71 |vpiParent: @@ -134008,7 +134008,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:918:29, endln:923:73 |vpiParent: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 |vpiRhs: \_operation: , line:918:55, endln:923:73 |vpiParent: @@ -134269,7 +134269,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:929:29, endln:929:50 |vpiParent: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 |vpiRhs: \_constant: , line:929:49, endln:929:50 |vpiDecompile:4 @@ -134283,7 +134283,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:930:29, endln:930:51 |vpiParent: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 |vpiRhs: \_constant: , line:930:49, endln:930:51 |vpiDecompile:32 @@ -134297,7 +134297,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:932:29, endln:932:63 |vpiParent: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 |vpiRhs: \_constant: , line:932:47, endln:932:63 |vpiDecompile:2 @@ -134311,7 +134311,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:1011:16, endln:1011:40 |vpiParent: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 |vpiRhs: \_constant: , line:1011:35, endln:1011:40 |vpiDecompile:8'h80 @@ -134325,7 +134325,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:1013:16, endln:1013:33 |vpiParent: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 |vpiRhs: \_constant: , line:1013:32, endln:1013:33 |vpiDecompile:1 @@ -134339,7 +134339,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:1014:16, endln:1014:30 |vpiParent: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 |vpiRhs: \_constant: , line:1014:29, endln:1014:30 |vpiDecompile:0 @@ -134353,7 +134353,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:1069:27, endln:1069:55 |vpiParent: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 |vpiRhs: \_constant: , line:1069:48, endln:1069:55 |vpiDecompile:16384 @@ -134367,7 +134367,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:1070:29, endln:1070:51 |vpiParent: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 |vpiRhs: \_constant: , line:1070:50, endln:1070:51 |vpiDecompile:4 @@ -134381,7 +134381,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:1071:29, endln:1071:92 |vpiParent: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 |vpiRhs: \_constant: , line:1071:50, endln:1071:92 |vpiDecompile:12 @@ -134395,7 +134395,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:1072:29, endln:1072:80 |vpiParent: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 |vpiRhs: \_constant: , line:1072:50, endln:1072:80 |vpiDecompile:44 @@ -134409,7 +134409,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:1073:29, endln:1073:53 |vpiParent: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 |vpiRhs: \_constant: , line:1073:50, endln:1073:53 |vpiDecompile:128 @@ -134423,7 +134423,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:1075:27, endln:1075:55 |vpiParent: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 |vpiRhs: \_constant: , line:1075:48, endln:1075:55 |vpiDecompile:32768 @@ -134437,7 +134437,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:1076:28, endln:1076:50 |vpiParent: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 |vpiRhs: \_constant: , line:1076:49, endln:1076:50 |vpiDecompile:8 @@ -134451,7 +134451,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:1077:29, endln:1077:92 |vpiParent: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 |vpiRhs: \_constant: , line:1077:50, endln:1077:92 |vpiDecompile:12 @@ -134465,7 +134465,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:1078:29, endln:1078:80 |vpiParent: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 |vpiRhs: \_constant: , line:1078:50, endln:1078:80 |vpiDecompile:44 @@ -134479,7 +134479,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:1079:29, endln:1079:53 |vpiParent: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 |vpiRhs: \_constant: , line:1079:50, endln:1079:53 |vpiDecompile:128 @@ -134493,7 +134493,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:1293:16, endln:1293:32 |vpiParent: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 |vpiRhs: \_constant: , line:1293:30, endln:1293:32 |vpiDecompile:38 @@ -134568,13 +134568,13 @@ design: (work@top) |vpiTaskFunc: \_function: (ariane_pkg::check_cfg), line:731:5, endln:743:16 |vpiParent: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 |vpiName:check_cfg |vpiFullName:ariane_pkg::check_cfg |vpiVisibility:1 |vpiAutomatic:1 |vpiParent: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 |vpiIODecl: \_io_decl: (Cfg), line:731:53, endln:731:56 |vpiParent: @@ -134875,11 +134875,11 @@ design: (work@top) |vpiOperand: \_constant: , line:740:36, endln:740:38 |vpiInstance: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 |vpiTaskFunc: \_function: (ariane_pkg::range_check), line:745:5, endln:748:30 |vpiParent: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 |vpiName:range_check |vpiFullName:ariane_pkg::range_check |vpiVisibility:1 @@ -134887,7 +134887,7 @@ design: (work@top) |vpiReturn: \_logic_var: , line:745:24, endln:745:29 |vpiParent: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 |vpiIODecl: \_io_decl: (base), line:745:54, endln:745:58 |vpiParent: @@ -134977,11 +134977,11 @@ design: (work@top) |vpiActual: \_io_decl: (len), line:745:72, endln:745:75 |vpiInstance: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 |vpiTaskFunc: \_function: (ariane_pkg::is_inside_nonidempotent_regions), line:750:5, endln:757:50 |vpiParent: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 |vpiName:is_inside_nonidempotent_regions |vpiFullName:ariane_pkg::is_inside_nonidempotent_regions |vpiVariables: @@ -134997,7 +134997,7 @@ design: (work@top) |vpiReturn: \_logic_var: , line:750:24, endln:750:29 |vpiParent: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 |vpiIODecl: \_io_decl: (Cfg), line:750:76, endln:750:79 |vpiParent: @@ -135247,11 +135247,11 @@ design: (work@top) |vpiActual: \_logic_var: (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.is_inside_nonidempotent_regions.pass), line:751:29, endln:751:33 |vpiInstance: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 |vpiTaskFunc: \_function: (ariane_pkg::is_inside_execute_regions), line:759:5, endln:767:44 |vpiParent: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 |vpiName:is_inside_execute_regions |vpiFullName:ariane_pkg::is_inside_execute_regions |vpiVariables: @@ -135267,7 +135267,7 @@ design: (work@top) |vpiReturn: \_logic_var: , line:759:24, endln:759:29 |vpiParent: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 |vpiIODecl: \_io_decl: (Cfg), line:759:70, endln:759:73 |vpiParent: @@ -135517,11 +135517,11 @@ design: (work@top) |vpiActual: \_logic_var: (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.is_inside_execute_regions.pass), line:761:29, endln:761:33 |vpiInstance: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 |vpiTaskFunc: \_function: (ariane_pkg::is_inside_cacheable_regions), line:769:5, endln:776:46 |vpiParent: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 |vpiName:is_inside_cacheable_regions |vpiFullName:ariane_pkg::is_inside_cacheable_regions |vpiVariables: @@ -135538,7 +135538,7 @@ design: (work@top) |vpiReturn: \_logic_var: , line:769:24, endln:769:29 |vpiParent: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 |vpiIODecl: \_io_decl: (Cfg), line:769:72, endln:769:75 |vpiParent: @@ -135790,11 +135790,11 @@ design: (work@top) |vpiActual: \_logic_var: (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.is_inside_cacheable_regions.pass), line:770:39, endln:770:43 |vpiInstance: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 |vpiTaskFunc: \_function: (ariane_pkg::op_is_branch), line:1132:5, endln:1137:16 |vpiParent: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 |vpiName:op_is_branch |vpiFullName:ariane_pkg::op_is_branch |vpiVisibility:1 @@ -135802,7 +135802,7 @@ design: (work@top) |vpiReturn: \_logic_var: , line:1132:24, endln:1132:29 |vpiParent: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 |vpiIODecl: \_io_decl: (op), line:1132:56, endln:1132:58 |vpiParent: @@ -135929,11 +135929,11 @@ design: (work@top) |vpiCondition: \_constant: , line:1135:48, endln:1135:52 |vpiInstance: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 |vpiTaskFunc: \_function: (ariane_pkg::is_rs1_fpr), line:1142:5, endln:1157:16 |vpiParent: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 |vpiName:is_rs1_fpr |vpiFullName:ariane_pkg::is_rs1_fpr |vpiVisibility:1 @@ -135941,7 +135941,7 @@ design: (work@top) |vpiReturn: \_logic_var: , line:1142:24, endln:1142:29 |vpiParent: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 |vpiIODecl: \_io_decl: (op), line:1142:54, endln:1142:56 |vpiParent: @@ -136133,11 +136133,11 @@ design: (work@top) |vpiCondition: \_constant: , line:1156:20, endln:1156:24 |vpiInstance: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 |vpiTaskFunc: \_function: (ariane_pkg::is_rs2_fpr), line:1159:5, endln:1173:16 |vpiParent: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 |vpiName:is_rs2_fpr |vpiFullName:ariane_pkg::is_rs2_fpr |vpiVisibility:1 @@ -136145,7 +136145,7 @@ design: (work@top) |vpiReturn: \_logic_var: , line:1159:24, endln:1159:29 |vpiParent: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 |vpiIODecl: \_io_decl: (op), line:1159:54, endln:1159:56 |vpiParent: @@ -136348,11 +136348,11 @@ design: (work@top) |vpiCondition: \_constant: , line:1172:20, endln:1172:24 |vpiInstance: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 |vpiTaskFunc: \_function: (ariane_pkg::is_imm_fpr), line:1176:5, endln:1186:16 |vpiParent: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 |vpiName:is_imm_fpr |vpiFullName:ariane_pkg::is_imm_fpr |vpiVisibility:1 @@ -136360,7 +136360,7 @@ design: (work@top) |vpiReturn: \_logic_var: , line:1176:24, endln:1176:29 |vpiParent: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 |vpiIODecl: \_io_decl: (op), line:1176:54, endln:1176:56 |vpiParent: @@ -136495,11 +136495,11 @@ design: (work@top) |vpiCondition: \_constant: , line:1185:20, endln:1185:24 |vpiInstance: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 |vpiTaskFunc: \_function: (ariane_pkg::is_rd_fpr), line:1188:5, endln:1203:16 |vpiParent: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 |vpiName:is_rd_fpr |vpiFullName:ariane_pkg::is_rd_fpr |vpiVisibility:1 @@ -136507,7 +136507,7 @@ design: (work@top) |vpiReturn: \_logic_var: , line:1188:24, endln:1188:29 |vpiParent: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 |vpiIODecl: \_io_decl: (op), line:1188:53, endln:1188:55 |vpiParent: @@ -136715,11 +136715,11 @@ design: (work@top) |vpiCondition: \_constant: , line:1202:20, endln:1202:24 |vpiInstance: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 |vpiTaskFunc: \_function: (ariane_pkg::is_amo), line:1205:5, endln:1212:16 |vpiParent: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 |vpiName:is_amo |vpiFullName:ariane_pkg::is_amo |vpiVisibility:1 @@ -136727,7 +136727,7 @@ design: (work@top) |vpiReturn: \_logic_var: , line:1205:24, endln:1205:29 |vpiParent: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 |vpiIODecl: \_io_decl: (op), line:1205:44, endln:1205:46 |vpiParent: @@ -136801,11 +136801,11 @@ design: (work@top) |vpiCondition: \_constant: , line:1210:29, endln:1210:33 |vpiInstance: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 |vpiTaskFunc: \_function: (ariane_pkg::sext32), line:1373:5, endln:1375:16 |vpiParent: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 |vpiName:sext32 |vpiFullName:ariane_pkg::sext32 |vpiVisibility:1 @@ -136813,7 +136813,7 @@ design: (work@top) |vpiReturn: \_logic_var: , line:1373:24, endln:1373:37 |vpiParent: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 |vpiIODecl: \_io_decl: (operand), line:1373:59, endln:1373:66 |vpiParent: @@ -136883,11 +136883,11 @@ design: (work@top) |vpiRightRange: \_constant: , line:1374:59, endln:1374:60 |vpiInstance: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 |vpiTaskFunc: \_function: (ariane_pkg::uj_imm), line:1380:5, endln:1382:16 |vpiParent: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 |vpiName:uj_imm |vpiFullName:ariane_pkg::uj_imm |vpiVisibility:1 @@ -136895,7 +136895,7 @@ design: (work@top) |vpiReturn: \_logic_var: , line:1380:24, endln:1380:47 |vpiParent: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 |vpiIODecl: \_io_decl: (instruction_i), line:1380:69, endln:1380:82 |vpiParent: @@ -137006,11 +137006,11 @@ design: (work@top) |vpiOperand: \_constant: , line:1381:122, endln:1381:126 |vpiInstance: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 |vpiTaskFunc: \_function: (ariane_pkg::i_imm), line:1384:5, endln:1386:16 |vpiParent: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 |vpiName:i_imm |vpiFullName:ariane_pkg::i_imm |vpiVisibility:1 @@ -137018,7 +137018,7 @@ design: (work@top) |vpiReturn: \_logic_var: , line:1384:24, endln:1384:47 |vpiParent: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 |vpiIODecl: \_io_decl: (instruction_i), line:1384:68, endln:1384:81 |vpiParent: @@ -137095,11 +137095,11 @@ design: (work@top) |vpiRightRange: \_constant: , line:1385:76, endln:1385:78 |vpiInstance: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 |vpiTaskFunc: \_function: (ariane_pkg::sb_imm), line:1388:5, endln:1390:16 |vpiParent: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 |vpiName:sb_imm |vpiFullName:ariane_pkg::sb_imm |vpiVisibility:1 @@ -137107,7 +137107,7 @@ design: (work@top) |vpiReturn: \_logic_var: , line:1388:24, endln:1388:47 |vpiParent: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 |vpiIODecl: \_io_decl: (instruction_i), line:1388:69, endln:1388:82 |vpiParent: @@ -137234,11 +137234,11 @@ design: (work@top) |vpiOperand: \_constant: , line:1389:139, endln:1389:143 |vpiInstance: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 |vpiTaskFunc: \_function: (ariane_pkg::data_align), line:1396:5, endln:1411:16 |vpiParent: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 |vpiName:data_align |vpiFullName:ariane_pkg::data_align |vpiVariables: @@ -137262,7 +137262,7 @@ design: (work@top) |vpiReturn: \_logic_var: , line:1396:24, endln:1396:37 |vpiParent: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 |vpiIODecl: \_io_decl: (addr), line:1396:62, endln:1396:66 |vpiParent: @@ -137993,11 +137993,11 @@ design: (work@top) |vpiRightRange: \_constant: , line:1410:39, endln:1410:40 |vpiInstance: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 |vpiTaskFunc: \_function: (ariane_pkg::be_gen), line:1414:5, endln:1453:16 |vpiParent: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 |vpiName:be_gen |vpiFullName:ariane_pkg::be_gen |vpiVisibility:1 @@ -138005,7 +138005,7 @@ design: (work@top) |vpiReturn: \_logic_var: , line:1414:24, endln:1414:35 |vpiParent: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 |vpiIODecl: \_io_decl: (addr), line:1414:55, endln:1414:59 |vpiParent: @@ -138400,11 +138400,11 @@ design: (work@top) |vpiCondition: \_constant: , line:1452:16, endln:1452:20 |vpiInstance: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 |vpiTaskFunc: \_function: (ariane_pkg::extract_transfer_size), line:1458:5, endln:1482:16 |vpiParent: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 |vpiName:extract_transfer_size |vpiFullName:ariane_pkg::extract_transfer_size |vpiVisibility:1 @@ -138412,7 +138412,7 @@ design: (work@top) |vpiReturn: \_logic_var: , line:1458:24, endln:1458:35 |vpiParent: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 |vpiIODecl: \_io_decl: (op), line:1458:64, endln:1458:66 |vpiParent: @@ -138823,11 +138823,11 @@ design: (work@top) |vpiCondition: \_constant: , line:1480:33, endln:1480:38 |vpiInstance: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 |vpiPort: \_port: (clk_i), line:2036:18, endln:2036:23 |vpiParent: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 |vpiName:clk_i |vpiHighConn: \_ref_obj: (work@top.i_ariane.ex_stage_i.fpu_gen.clk_i), line:2036:18, endln:2036:23 @@ -138838,11 +138838,11 @@ design: (work@top) |vpiActual: \_logic_net: (work@top.i_ariane.ex_stage_i.fpu_gen.clk_i), line:2036:18, endln:2036:23 |vpiInstance: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 |vpiPort: \_port: (rst_ni), line:2037:18, endln:2037:24 |vpiParent: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 |vpiName:rst_ni |vpiHighConn: \_ref_obj: (work@top.i_ariane.ex_stage_i.fpu_gen.rst_ni), line:2037:18, endln:2037:24 @@ -138853,11 +138853,11 @@ design: (work@top) |vpiActual: \_logic_net: (work@top.i_ariane.ex_stage_i.fpu_gen.rst_ni), line:2037:18, endln:2037:24 |vpiInstance: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 |vpiPort: \_port: (flush_i), line:2038:18, endln:2038:25 |vpiParent: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 |vpiName:flush_i |vpiHighConn: \_ref_obj: (work@top.i_ariane.ex_stage_i.fpu_gen.flush_i), line:2038:18, endln:2038:25 @@ -138868,11 +138868,11 @@ design: (work@top) |vpiActual: \_logic_net: (work@top.i_ariane.ex_stage_i.fpu_gen.flush_i), line:2038:18, endln:2038:25 |vpiInstance: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 |vpiPort: \_port: (fpu_valid_i), line:2039:18, endln:2039:29 |vpiParent: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 |vpiName:fpu_valid_i |vpiHighConn: \_ref_obj: (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_valid_i), line:2039:18, endln:2039:29 @@ -138883,11 +138883,11 @@ design: (work@top) |vpiActual: \_logic_net: (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_valid_i), line:2039:18, endln:2039:29 |vpiInstance: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 |vpiPort: \_port: (fpu_ready_o), line:2040:18, endln:2040:29 |vpiParent: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 |vpiName:fpu_ready_o |vpiHighConn: \_ref_obj: (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_ready_o), line:2040:18, endln:2040:29 @@ -138898,11 +138898,11 @@ design: (work@top) |vpiActual: \_logic_net: (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_ready_o), line:2040:18, endln:2040:29 |vpiInstance: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 |vpiPort: \_port: (fu_data_i), line:2041:18, endln:2041:27 |vpiParent: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 |vpiName:fu_data_i |vpiHighConn: \_ref_obj: (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_data), line:2041:30, endln:2041:38 @@ -138913,11 +138913,11 @@ design: (work@top) |vpiActual: \_struct_var: (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_data), line:2032:23, endln:2032:31 |vpiInstance: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 |vpiPort: \_port: (fpu_fmt_i), line:2042:18, endln:2042:27 |vpiParent: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 |vpiName:fpu_fmt_i |vpiHighConn: \_ref_obj: (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_fmt_i), line:2042:18, endln:2042:27 @@ -138928,11 +138928,11 @@ design: (work@top) |vpiActual: \_logic_net: (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_fmt_i), line:2042:18, endln:2042:27 |vpiInstance: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 |vpiPort: \_port: (fpu_rm_i), line:2043:18, endln:2043:26 |vpiParent: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 |vpiName:fpu_rm_i |vpiHighConn: \_ref_obj: (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_rm_i), line:2043:18, endln:2043:26 @@ -138943,11 +138943,11 @@ design: (work@top) |vpiActual: \_logic_net: (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_rm_i), line:2043:18, endln:2043:26 |vpiInstance: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 |vpiPort: \_port: (fpu_frm_i), line:2044:18, endln:2044:27 |vpiParent: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 |vpiName:fpu_frm_i |vpiHighConn: \_ref_obj: (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_frm_i), line:2044:18, endln:2044:27 @@ -138958,11 +138958,11 @@ design: (work@top) |vpiActual: \_logic_net: (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_frm_i), line:2044:18, endln:2044:27 |vpiInstance: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 |vpiPort: \_port: (fpu_prec_i), line:2045:18, endln:2045:28 |vpiParent: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 |vpiName:fpu_prec_i |vpiHighConn: \_ref_obj: (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_prec_i), line:2045:18, endln:2045:28 @@ -138973,11 +138973,11 @@ design: (work@top) |vpiActual: \_logic_net: (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_prec_i), line:2045:18, endln:2045:28 |vpiInstance: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 |vpiPort: \_port: (fpu_trans_id_o), line:2046:18, endln:2046:32 |vpiParent: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 |vpiName:fpu_trans_id_o |vpiHighConn: \_ref_obj: (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_trans_id_o), line:2046:18, endln:2046:32 @@ -138988,11 +138988,11 @@ design: (work@top) |vpiActual: \_logic_net: (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_trans_id_o), line:2046:18, endln:2046:32 |vpiInstance: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 |vpiPort: \_port: (result_o), line:2047:18, endln:2047:26 |vpiParent: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 |vpiName:result_o |vpiHighConn: \_ref_obj: (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_result_o), line:2047:29, endln:2047:41 @@ -139003,11 +139003,11 @@ design: (work@top) |vpiActual: \_logic_net: (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_result_o), line:2047:29, endln:2047:41 |vpiInstance: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 |vpiPort: \_port: (fpu_valid_o), line:2048:18, endln:2048:29 |vpiParent: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 |vpiName:fpu_valid_o |vpiHighConn: \_ref_obj: (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_valid_o), line:2048:18, endln:2048:29 @@ -139018,11 +139018,11 @@ design: (work@top) |vpiActual: \_logic_net: (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_valid_o), line:2048:18, endln:2048:29 |vpiInstance: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 |vpiPort: \_port: (fpu_exception_o), line:2049:18, endln:2049:33 |vpiParent: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 |vpiName:fpu_exception_o |vpiHighConn: \_ref_obj: (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_exception_o), line:2049:18, endln:2049:33 @@ -139033,11 +139033,11 @@ design: (work@top) |vpiActual: \_logic_net: (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_exception_o), line:2049:18, endln:2049:33 |vpiInstance: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 |vpiGenScopeArray: \_gen_scope_array: (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen), line:1991:3, endln:2020:6 |vpiParent: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15 |vpiName:fpu_gen |vpiFullName:work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen |vpiGenScope: @@ -141251,8 +141251,8 @@ design: (work@top) |vpiConstType:7 |vpiLhs: \_parameter: (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.FPU_IMPLEMENTATION), line:2001:44, endln:2001:62 - |vpiModule: - \_module: work@fpnew_top (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2014:8, endln:2018:24 + |vpiModuleInst: + \_module_inst: work@fpnew_top (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2014:8, endln:2018:24 |vpiParent: \_gen_scope: (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen) |vpiName:i_fpnew_bulk @@ -142213,10 +142213,10 @@ design: (work@top) |vpiParameter: \_type_parameter: (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.TagType) |vpiParent: - \_module: work@fpnew_top (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2014:8, endln:2018:24 + \_module_inst: work@fpnew_top (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2014:8, endln:2018:24 |vpiName:TagType |vpiInstance: - \_module: work@fpnew_top (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2014:8, endln:2018:24 + \_module_inst: work@fpnew_top (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2014:8, endln:2018:24 |vpiFullName:work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.TagType |vpiTypespec: \_logic_typespec: , line:2017:25, endln:2017:50 @@ -142278,7 +142278,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:1960:45, endln:1960:84 |vpiParent: - \_module: work@fpnew_top (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2014:8, endln:2018:24 + \_module_inst: work@fpnew_top (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2014:8, endln:2018:24 |vpiOverriden:1 |vpiRhs: \_operation: , line:2015:25, endln:2015:37 @@ -142547,7 +142547,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:1961:45, endln:1961:87 |vpiParent: - \_module: work@fpnew_top (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2014:8, endln:2018:24 + \_module_inst: work@fpnew_top (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2014:8, endln:2018:24 |vpiOverriden:1 |vpiRhs: \_operation: , line:2016:25, endln:2016:43 @@ -143535,7 +143535,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:1964:27, endln:1964:56 |vpiParent: - \_module: work@fpnew_top (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2014:8, endln:2018:24 + \_module_inst: work@fpnew_top (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2014:8, endln:2018:24 |vpiRhs: \_constant: , line:1964:42, endln:1964:56 |vpiDecompile:64 @@ -143549,7 +143549,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:1965:27, endln:1965:43 |vpiParent: - \_module: work@fpnew_top (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2014:8, endln:2018:24 + \_module_inst: work@fpnew_top (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2014:8, endln:2018:24 |vpiRhs: \_constant: , line:1965:42, endln:1965:43 |vpiDecompile:3 @@ -143563,7 +143563,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:1969:27, endln:1969:67 |vpiParent: - \_module: work@fpnew_top (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2014:8, endln:2018:24 + \_module_inst: work@fpnew_top (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2014:8, endln:2018:24 |vpiRhs: \_constant: , line:1969:42, endln:1969:67 |vpiDecompile:5 @@ -143580,7 +143580,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_nanbox_check[0]), line:1971:56, endln:1983:6 |vpiParent: - \_module: work@fpnew_top (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2014:8, endln:2018:24 + \_module_inst: work@fpnew_top (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2014:8, endln:2018:24 |vpiName:gen_nanbox_check[0] |vpiFullName:work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_nanbox_check[0] |vpiGenScope: @@ -144048,7 +144048,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_nanbox_check[1]), line:1971:56, endln:1983:6 |vpiParent: - \_module: work@fpnew_top (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2014:8, endln:2018:24 + \_module_inst: work@fpnew_top (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2014:8, endln:2018:24 |vpiName:gen_nanbox_check[1] |vpiFullName:work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_nanbox_check[1] |vpiGenScope: @@ -144138,7 +144138,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_nanbox_check[2]), line:1971:56, endln:1983:6 |vpiParent: - \_module: work@fpnew_top (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2014:8, endln:2018:24 + \_module_inst: work@fpnew_top (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2014:8, endln:2018:24 |vpiName:gen_nanbox_check[2] |vpiFullName:work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_nanbox_check[2] |vpiGenScope: @@ -144606,7 +144606,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_nanbox_check[3]), line:1971:56, endln:1983:6 |vpiParent: - \_module: work@fpnew_top (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2014:8, endln:2018:24 + \_module_inst: work@fpnew_top (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2014:8, endln:2018:24 |vpiName:gen_nanbox_check[3] |vpiFullName:work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_nanbox_check[3] |vpiGenScope: @@ -145074,7 +145074,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_nanbox_check[4]), line:1971:56, endln:1983:6 |vpiParent: - \_module: work@fpnew_top (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2014:8, endln:2018:24 + \_module_inst: work@fpnew_top (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2014:8, endln:2018:24 |vpiName:gen_nanbox_check[4] |vpiFullName:work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_nanbox_check[4] |vpiGenScope: diff --git a/tests/ArianeElab2/ArianeElab2.log b/tests/ArianeElab2/ArianeElab2.log index afeeb6944a..f380d6cc45 100644 --- a/tests/ArianeElab2/ArianeElab2.log +++ b/tests/ArianeElab2/ArianeElab2.log @@ -20871,7 +20871,7 @@ logic_net 13 logic_typespec 100496 logic_var 98 long_int_typespec 4 -module 576 +module_inst 576 operation 92394 package 9 packed_array_typespec 49406 @@ -20927,7 +20927,7 @@ logic_net 13 logic_typespec 100496 logic_var 206 long_int_typespec 4 -module 608 +module_inst 608 operation 94063 package 9 packed_array_typespec 49406 @@ -69809,7 +69809,7 @@ design: (work@top) |vpiTypespec: \_struct_typespec: (ariane_pkg::ariane_cfg_t), line:684:13, endln:684:19 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 |vpiName:ariane_pkg::ariane_cfg_t |vpiInstance: \_package: ariane_pkg (ariane_pkg::), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:674:1, endln:1483:11 @@ -73371,7 +73371,7 @@ design: (work@top) |vpiTypedef: \_struct_typespec: (ariane_pkg::amo_req_t), line:1337:13, endln:1337:19 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 |vpiName:ariane_pkg::amo_req_t |vpiInstance: \_package: ariane_pkg (ariane_pkg::), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:674:1, endln:1483:11 @@ -73400,7 +73400,7 @@ design: (work@top) |vpiTypespec: \_enum_typespec: (ariane_pkg::amo_t), line:1265:5, endln:1280:13 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 |vpiName:ariane_pkg::amo_t |vpiInstance: \_package: ariane_pkg (ariane_pkg::), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:674:1, endln:1483:11 @@ -73626,7 +73626,7 @@ design: (work@top) |vpiTypedef: \_struct_typespec: (ariane_pkg::amo_resp_t), line:1346:13, endln:1346:19 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 |vpiName:ariane_pkg::amo_resp_t |vpiInstance: \_package: ariane_pkg (ariane_pkg::), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:674:1, endln:1483:11 @@ -73690,7 +73690,7 @@ design: (work@top) |vpiTypedef: \_struct_typespec: (ariane_pkg::bht_prediction_t), line:994:13, endln:994:19 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 |vpiName:ariane_pkg::bht_prediction_t |vpiInstance: \_package: ariane_pkg (ariane_pkg::), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:674:1, endln:1483:11 @@ -73730,7 +73730,7 @@ design: (work@top) |vpiTypedef: \_struct_typespec: (ariane_pkg::bht_update_t), line:988:13, endln:988:19 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 |vpiName:ariane_pkg::bht_update_t |vpiInstance: \_package: ariane_pkg (ariane_pkg::), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:674:1, endln:1483:11 @@ -73806,7 +73806,7 @@ design: (work@top) |vpiTypedef: \_struct_typespec: (ariane_pkg::bp_resolve_t), line:955:13, endln:955:19 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 |vpiName:ariane_pkg::bp_resolve_t |vpiInstance: \_package: ariane_pkg (ariane_pkg::), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:674:1, endln:1483:11 @@ -73939,7 +73939,7 @@ design: (work@top) |vpiTypespec: \_enum_typespec: (ariane_pkg::cf_t), line:943:5, endln:949:12 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 |vpiName:ariane_pkg::cf_t |vpiInstance: \_package: ariane_pkg (ariane_pkg::), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:674:1, endln:1483:11 @@ -74003,7 +74003,7 @@ design: (work@top) |vpiTypedef: \_struct_typespec: (ariane_pkg::branchpredict_sbe_t), line:967:13, endln:967:19 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 |vpiName:ariane_pkg::branchpredict_sbe_t |vpiInstance: \_package: ariane_pkg (ariane_pkg::), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:674:1, endln:1483:11 @@ -74059,7 +74059,7 @@ design: (work@top) |vpiTypedef: \_struct_typespec: (ariane_pkg::btb_prediction_t), line:978:13, endln:978:19 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 |vpiName:ariane_pkg::btb_prediction_t |vpiInstance: \_package: ariane_pkg (ariane_pkg::), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:674:1, endln:1483:11 @@ -74119,7 +74119,7 @@ design: (work@top) |vpiTypedef: \_struct_typespec: (ariane_pkg::btb_update_t), line:972:13, endln:972:19 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 |vpiName:ariane_pkg::btb_update_t |vpiInstance: \_package: ariane_pkg (ariane_pkg::), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:674:1, endln:1483:11 @@ -74217,7 +74217,7 @@ design: (work@top) |vpiTypedef: \_struct_typespec: (ariane_pkg::dcache_req_i_t), line:1352:13, endln:1352:19 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 |vpiName:ariane_pkg::dcache_req_i_t |vpiInstance: \_package: ariane_pkg (ariane_pkg::), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:674:1, endln:1483:11 @@ -74469,7 +74469,7 @@ design: (work@top) |vpiTypedef: \_struct_typespec: (ariane_pkg::dcache_req_o_t), line:1364:13, endln:1364:19 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 |vpiName:ariane_pkg::dcache_req_o_t |vpiInstance: \_package: ariane_pkg (ariane_pkg::), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:674:1, endln:1483:11 @@ -74545,7 +74545,7 @@ design: (work@top) |vpiTypedef: \_struct_typespec: (ariane_pkg::exception_t), line:936:13, endln:936:19 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 |vpiName:ariane_pkg::exception_t |vpiInstance: \_package: ariane_pkg (ariane_pkg::), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:674:1, endln:1483:11 @@ -74593,7 +74593,7 @@ design: (work@top) |vpiTypedef: \_struct_typespec: (ariane_pkg::fetch_entry_t), line:1229:13, endln:1229:19 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 |vpiName:ariane_pkg::fetch_entry_t |vpiInstance: \_package: ariane_pkg (ariane_pkg::), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:674:1, endln:1483:11 @@ -74697,7 +74697,7 @@ design: (work@top) |vpiTypedef: \_enum_typespec: (ariane_pkg::frontend_exception_t), line:1295:5, endln:1299:28 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 |vpiName:ariane_pkg::frontend_exception_t |vpiInstance: \_package: ariane_pkg (ariane_pkg::), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:674:1, endln:1483:11 @@ -74744,7 +74744,7 @@ design: (work@top) |vpiTypedef: \_struct_typespec: (ariane_pkg::fu_data_t), line:1123:13, endln:1123:19 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 |vpiName:ariane_pkg::fu_data_t |vpiInstance: \_package: ariane_pkg (ariane_pkg::), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:674:1, endln:1483:11 @@ -74757,7 +74757,7 @@ design: (work@top) |vpiTypespec: \_enum_typespec: (ariane_pkg::fu_t), line:999:5, endln:1009:12 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 |vpiName:ariane_pkg::fu_t |vpiInstance: \_package: ariane_pkg (ariane_pkg::), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:674:1, endln:1483:11 @@ -74850,7 +74850,7 @@ design: (work@top) |vpiTypespec: \_enum_typespec: (ariane_pkg::fu_op), line:1085:5, endln:1121:38 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 |vpiName:ariane_pkg::fu_op |vpiInstance: \_package: ariane_pkg (ariane_pkg::), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:674:1, endln:1483:11 @@ -75692,7 +75692,7 @@ design: (work@top) |vpiTypedef: \_struct_typespec: (ariane_pkg::icache_areq_i_t), line:1305:13, endln:1305:19 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 |vpiName:ariane_pkg::icache_areq_i_t |vpiInstance: \_package: ariane_pkg (ariane_pkg::), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:674:1, endln:1483:11 @@ -75764,7 +75764,7 @@ design: (work@top) |vpiTypedef: \_struct_typespec: (ariane_pkg::icache_areq_o_t), line:1311:13, endln:1311:19 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 |vpiName:ariane_pkg::icache_areq_o_t |vpiInstance: \_package: ariane_pkg (ariane_pkg::), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:674:1, endln:1483:11 @@ -75824,7 +75824,7 @@ design: (work@top) |vpiTypedef: \_struct_typespec: (ariane_pkg::icache_dreq_i_t), line:1317:13, endln:1317:19 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 |vpiName:ariane_pkg::icache_dreq_i_t |vpiInstance: \_package: ariane_pkg (ariane_pkg::), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:674:1, endln:1483:11 @@ -75932,7 +75932,7 @@ design: (work@top) |vpiTypedef: \_struct_typespec: (ariane_pkg::icache_dreq_o_t), line:1325:13, endln:1325:19 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 |vpiName:ariane_pkg::icache_dreq_o_t |vpiInstance: \_package: ariane_pkg (ariane_pkg::), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:674:1, endln:1483:11 @@ -76056,7 +76056,7 @@ design: (work@top) |vpiTypedef: \_struct_typespec: (ariane_pkg::irq_ctrl_t), line:1018:13, endln:1018:19 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 |vpiName:ariane_pkg::irq_ctrl_t |vpiInstance: \_package: ariane_pkg (ariane_pkg::), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:674:1, endln:1483:11 @@ -76132,7 +76132,7 @@ design: (work@top) |vpiTypedef: \_struct_typespec: (ariane_pkg::lsu_ctrl_t), line:1214:13, endln:1214:19 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 |vpiName:ariane_pkg::lsu_ctrl_t |vpiInstance: \_package: ariane_pkg (ariane_pkg::), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:674:1, endln:1483:11 @@ -76340,7 +76340,7 @@ design: (work@top) |vpiTypedef: \_struct_typespec: (ariane_pkg::ras_t), line:983:13, endln:983:19 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 |vpiName:ariane_pkg::ras_t |vpiInstance: \_package: ariane_pkg (ariane_pkg::), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:674:1, endln:1483:11 @@ -76400,7 +76400,7 @@ design: (work@top) |vpiTypedef: \_struct_typespec: (ariane_pkg::scoreboard_entry_t), line:1239:13, endln:1239:19 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 |vpiName:ariane_pkg::scoreboard_entry_t |vpiInstance: \_package: ariane_pkg (ariane_pkg::), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:674:1, endln:1483:11 @@ -76728,7 +76728,7 @@ design: (work@top) |vpiTypedef: \_struct_typespec: (ariane_pkg::tlb_update_t), line:1282:13, endln:1282:19 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 |vpiName:ariane_pkg::tlb_update_t |vpiInstance: \_package: ariane_pkg (ariane_pkg::), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:674:1, endln:1483:11 @@ -90134,14 +90134,14 @@ design: (work@top) |vpiInstance: \_package: fpnew_pkg (fpnew_pkg::), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:1485:1, endln:1955:11 |uhdmallModules: -\_module: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2114:1, endln:2123:10 +\_module_inst: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2114:1, endln:2123:10 |vpiParent: \_design: (work@top) |vpiFullName:work@ariane |vpiParameter: \_parameter: (work@ariane.ARIANE_MARCHID), line:855:30, endln:855:44 |vpiParent: - \_module: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2114:1, endln:2123:10 + \_module_inst: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2114:1, endln:2123:10 |vpiTypespec: \_logic_typespec: (xlen_t), line:30:13, endln:30:29 |vpiParent: @@ -90176,7 +90176,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@ariane.ASID_WIDTH), line:782:16, endln:782:26 |vpiParent: - \_module: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2114:1, endln:2123:10 + \_module_inst: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2114:1, endln:2123:10 |INT:16 |vpiTypespec: \_int_typespec: @@ -90189,7 +90189,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@ariane.ArianeDefaultConfig), line:706:29, endln:706:48 |vpiParent: - \_module: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2114:1, endln:2123:10 + \_module_inst: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2114:1, endln:2123:10 |vpiTypespec: \_struct_typespec: (ariane_pkg::ariane_cfg_t), line:684:13, endln:684:19 |vpiParent: @@ -90726,7 +90726,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@ariane.BITS_SATURATION_COUNTER), line:783:16, endln:783:39 |vpiParent: - \_module: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2114:1, endln:2123:10 + \_module_inst: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2114:1, endln:2123:10 |UINT:2 |vpiTypespec: \_int_typespec: @@ -90739,7 +90739,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@ariane.CONFIG_L1D_SIZE), line:1075:27, endln:1075:42 |vpiParent: - \_module: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2114:1, endln:2123:10 + \_module_inst: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2114:1, endln:2123:10 |INT:32768 |vpiTypespec: \_int_typespec: , line:1075:14, endln:1075:26 @@ -90754,7 +90754,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@ariane.CONFIG_L1I_SIZE), line:1069:27, endln:1069:42 |vpiParent: - \_module: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2114:1, endln:2123:10 + \_module_inst: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2114:1, endln:2123:10 |INT:16384 |vpiTypespec: \_int_typespec: , line:1069:14, endln:1069:26 @@ -90769,7 +90769,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@ariane.DCACHE_INDEX_WIDTH), line:1077:29, endln:1077:47 |vpiParent: - \_module: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2114:1, endln:2123:10 + \_module_inst: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2114:1, endln:2123:10 |UINT:12 |vpiTypespec: \_int_typespec: , line:1077:16, endln:1077:28 @@ -90784,7 +90784,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@ariane.DCACHE_LINE_WIDTH), line:1079:29, endln:1079:46 |vpiParent: - \_module: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2114:1, endln:2123:10 + \_module_inst: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2114:1, endln:2123:10 |UINT:128 |vpiTypespec: \_int_typespec: , line:1079:16, endln:1079:28 @@ -90799,7 +90799,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@ariane.DCACHE_SET_ASSOC), line:1076:28, endln:1076:44 |vpiParent: - \_module: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2114:1, endln:2123:10 + \_module_inst: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2114:1, endln:2123:10 |UINT:8 |vpiTypespec: \_int_typespec: , line:1076:15, endln:1076:27 @@ -90814,7 +90814,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@ariane.DCACHE_TAG_WIDTH), line:1078:29, endln:1078:45 |vpiParent: - \_module: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2114:1, endln:2123:10 + \_module_inst: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2114:1, endln:2123:10 |INT:44 |vpiTypespec: \_int_typespec: , line:1078:16, endln:1078:28 @@ -90829,7 +90829,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@ariane.DEPTH_COMMIT), line:804:29, endln:804:41 |vpiParent: - \_module: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2114:1, endln:2123:10 + \_module_inst: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2114:1, endln:2123:10 |UINT:8 |vpiTypespec: \_int_typespec: , line:804:16, endln:804:28 @@ -90844,7 +90844,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@ariane.DEPTH_SPEC), line:795:29, endln:795:39 |vpiParent: - \_module: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2114:1, endln:2123:10 + \_module_inst: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2114:1, endln:2123:10 |UINT:4 |vpiTypespec: \_int_typespec: , line:795:16, endln:795:28 @@ -90859,7 +90859,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@ariane.DebugHartInfo), line:874:31, endln:874:44 |vpiParent: - \_module: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2114:1, endln:2123:10 + \_module_inst: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2114:1, endln:2123:10 |vpiTypespec: \_unsupported_typespec: (dm::hartinfo_t), line:874:16, endln:874:20 |vpiParent: @@ -90874,7 +90874,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@ariane.ENABLE_CYCLE_COUNT), line:900:20, endln:900:38 |vpiParent: - \_module: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2114:1, endln:2123:10 + \_module_inst: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2114:1, endln:2123:10 |BIN:1 |vpiTypespec: \_bit_typespec: , line:900:16, endln:900:19 @@ -90890,7 +90890,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@ariane.ENABLE_RENAME), line:786:16, endln:786:29 |vpiParent: - \_module: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2114:1, endln:2123:10 + \_module_inst: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2114:1, endln:2123:10 |BIN:0 |vpiTypespec: \_int_typespec: @@ -90917,7 +90917,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@ariane.ENABLE_SPIKE_COMMIT_LOG), line:884:20, endln:884:43 |vpiParent: - \_module: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2114:1, endln:2123:10 + \_module_inst: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2114:1, endln:2123:10 |BIN:1 |vpiTypespec: \_bit_typespec: , line:884:16, endln:884:19 @@ -90933,7 +90933,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@ariane.ENABLE_WFI), line:901:20, endln:901:30 |vpiParent: - \_module: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2114:1, endln:2123:10 + \_module_inst: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2114:1, endln:2123:10 |BIN:1 |vpiTypespec: \_bit_typespec: , line:901:16, endln:901:19 @@ -90949,7 +90949,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@ariane.EXC_OFF_RST), line:1011:16, endln:1011:27 |vpiParent: - \_module: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2114:1, endln:2123:10 + \_module_inst: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2114:1, endln:2123:10 |HEX:80 |vpiTypespec: \_int_typespec: @@ -90976,7 +90976,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@ariane.FETCH_FIFO_DEPTH), line:929:29, endln:929:45 |vpiParent: - \_module: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2114:1, endln:2123:10 + \_module_inst: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2114:1, endln:2123:10 |UINT:4 |vpiTypespec: \_int_typespec: , line:929:16, endln:929:28 @@ -90991,7 +90991,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@ariane.FETCH_WIDTH), line:930:29, endln:930:40 |vpiParent: - \_module: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2114:1, endln:2123:10 + \_module_inst: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2114:1, endln:2123:10 |UINT:32 |vpiTypespec: \_int_typespec: , line:930:16, endln:930:28 @@ -91006,7 +91006,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@ariane.FLEN), line:839:16, endln:839:20 |vpiParent: - \_module: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2114:1, endln:2123:10 + \_module_inst: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2114:1, endln:2123:10 |INT:64 |vpiTypespec: \_int_typespec: @@ -91019,7 +91019,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@ariane.FP_PRESENT), line:836:20, endln:836:30 |vpiParent: - \_module: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2114:1, endln:2123:10 + \_module_inst: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2114:1, endln:2123:10 |UINT:1 |vpiTypespec: \_bit_typespec: , line:836:16, endln:836:19 @@ -91035,7 +91035,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@ariane.ICACHE_INDEX_WIDTH), line:1071:29, endln:1071:47 |vpiParent: - \_module: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2114:1, endln:2123:10 + \_module_inst: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2114:1, endln:2123:10 |UINT:12 |vpiTypespec: \_int_typespec: , line:1071:16, endln:1071:28 @@ -91050,7 +91050,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@ariane.ICACHE_LINE_WIDTH), line:1073:29, endln:1073:46 |vpiParent: - \_module: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2114:1, endln:2123:10 + \_module_inst: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2114:1, endln:2123:10 |UINT:128 |vpiTypespec: \_int_typespec: , line:1073:16, endln:1073:28 @@ -91065,7 +91065,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@ariane.ICACHE_SET_ASSOC), line:1070:29, endln:1070:45 |vpiParent: - \_module: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2114:1, endln:2123:10 + \_module_inst: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2114:1, endln:2123:10 |UINT:4 |vpiTypespec: \_int_typespec: , line:1070:16, endln:1070:28 @@ -91080,7 +91080,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@ariane.ICACHE_TAG_WIDTH), line:1072:29, endln:1072:45 |vpiParent: - \_module: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2114:1, endln:2123:10 + \_module_inst: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2114:1, endln:2123:10 |INT:44 |vpiTypespec: \_int_typespec: , line:1072:16, endln:1072:28 @@ -91095,7 +91095,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@ariane.INSTR_PER_FETCH), line:932:29, endln:932:44 |vpiParent: - \_module: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2114:1, endln:2123:10 + \_module_inst: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2114:1, endln:2123:10 |INT:2 |vpiTypespec: \_int_typespec: , line:932:16, endln:932:28 @@ -91110,7 +91110,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@ariane.INVALIDATE_ON_FLUSH), line:890:22, endln:890:41 |vpiParent: - \_module: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2114:1, endln:2123:10 + \_module_inst: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2114:1, endln:2123:10 |BIN:1 |vpiTypespec: \_logic_typespec: , line:890:16, endln:890:21 @@ -91125,7 +91125,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@ariane.ISA_CODE), line:857:30, endln:857:38 |vpiParent: - \_module: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2114:1, endln:2123:10 + \_module_inst: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2114:1, endln:2123:10 |vpiTypespec: \_logic_typespec: (xlen_t), line:30:13, endln:30:29 |vpiParent: @@ -91160,7 +91160,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@ariane.ISSUE_WIDTH), line:788:16, endln:788:27 |vpiParent: - \_module: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2114:1, endln:2123:10 + \_module_inst: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2114:1, endln:2123:10 |UINT:1 |vpiTypespec: \_int_typespec: @@ -91173,7 +91173,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@ariane.LAT_COMP_FP16), line:827:29, endln:827:42 |vpiParent: - \_module: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2114:1, endln:2123:10 + \_module_inst: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2114:1, endln:2123:10 |DEC:1 |vpiTypespec: \_int_typespec: , line:827:16, endln:827:28 @@ -91188,7 +91188,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@ariane.LAT_COMP_FP16ALT), line:828:29, endln:828:45 |vpiParent: - \_module: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2114:1, endln:2123:10 + \_module_inst: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2114:1, endln:2123:10 |DEC:1 |vpiTypespec: \_int_typespec: , line:828:16, endln:828:28 @@ -91203,7 +91203,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@ariane.LAT_COMP_FP32), line:825:29, endln:825:42 |vpiParent: - \_module: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2114:1, endln:2123:10 + \_module_inst: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2114:1, endln:2123:10 |DEC:2 |vpiTypespec: \_int_typespec: , line:825:16, endln:825:28 @@ -91218,7 +91218,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@ariane.LAT_COMP_FP64), line:826:29, endln:826:42 |vpiParent: - \_module: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2114:1, endln:2123:10 + \_module_inst: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2114:1, endln:2123:10 |DEC:3 |vpiTypespec: \_int_typespec: , line:826:16, endln:826:28 @@ -91233,7 +91233,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@ariane.LAT_COMP_FP8), line:829:29, endln:829:41 |vpiParent: - \_module: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2114:1, endln:2123:10 + \_module_inst: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2114:1, endln:2123:10 |DEC:1 |vpiTypespec: \_int_typespec: , line:829:16, endln:829:28 @@ -91248,7 +91248,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@ariane.LAT_CONV), line:832:29, endln:832:37 |vpiParent: - \_module: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2114:1, endln:2123:10 + \_module_inst: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2114:1, endln:2123:10 |DEC:2 |vpiTypespec: \_int_typespec: , line:832:16, endln:832:28 @@ -91263,7 +91263,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@ariane.LAT_DIVSQRT), line:830:29, endln:830:40 |vpiParent: - \_module: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2114:1, endln:2123:10 + \_module_inst: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2114:1, endln:2123:10 |DEC:2 |vpiTypespec: \_int_typespec: , line:830:16, endln:830:28 @@ -91278,7 +91278,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@ariane.LAT_NONCOMP), line:831:29, endln:831:40 |vpiParent: - \_module: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2114:1, endln:2123:10 + \_module_inst: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2114:1, endln:2123:10 |DEC:1 |vpiTypespec: \_int_typespec: , line:831:16, endln:831:28 @@ -91293,7 +91293,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@ariane.MachineIrq), line:1014:16, endln:1014:26 |vpiParent: - \_module: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2114:1, endln:2123:10 + \_module_inst: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2114:1, endln:2123:10 |UINT:0 |vpiTypespec: \_int_typespec: @@ -91306,7 +91306,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@ariane.NR_COMMIT_PORTS), line:784:16, endln:784:31 |vpiParent: - \_module: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2114:1, endln:2123:10 + \_module_inst: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2114:1, endln:2123:10 |UINT:2 |vpiTypespec: \_int_typespec: @@ -91319,7 +91319,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@ariane.NR_LOAD_PIPE_REGS), line:791:29, endln:791:46 |vpiParent: - \_module: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2114:1, endln:2123:10 + \_module_inst: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2114:1, endln:2123:10 |UINT:1 |vpiTypespec: \_int_typespec: , line:791:16, endln:791:28 @@ -91334,7 +91334,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@ariane.NR_SB_ENTRIES), line:779:16, endln:779:29 |vpiParent: - \_module: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2114:1, endln:2123:10 + \_module_inst: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2114:1, endln:2123:10 |UINT:8 |vpiTypespec: \_int_typespec: @@ -91347,7 +91347,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@ariane.NR_STORE_PIPE_REGS), line:792:29, endln:792:47 |vpiParent: - \_module: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2114:1, endln:2123:10 + \_module_inst: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2114:1, endln:2123:10 |UINT:0 |vpiTypespec: \_int_typespec: , line:792:16, endln:792:28 @@ -91362,7 +91362,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@ariane.NR_WB_PORTS), line:871:16, endln:871:27 |vpiParent: - \_module: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2114:1, endln:2123:10 + \_module_inst: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2114:1, endln:2123:10 |UINT:4 |vpiTypespec: \_int_typespec: @@ -91375,7 +91375,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@ariane.NSX), line:846:20, endln:846:23 |vpiParent: - \_module: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2114:1, endln:2123:10 + \_module_inst: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2114:1, endln:2123:10 |UINT:0 |vpiTypespec: \_bit_typespec: , line:846:16, endln:846:19 @@ -91391,7 +91391,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@ariane.NrMaxRules), line:682:16, endln:682:26 |vpiParent: - \_module: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2114:1, endln:2123:10 + \_module_inst: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2114:1, endln:2123:10 |UINT:16 |vpiTypespec: \_int_typespec: @@ -91404,7 +91404,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@ariane.PPN4K_WIDTH), line:1293:16, endln:1293:27 |vpiParent: - \_module: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2114:1, endln:2123:10 + \_module_inst: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2114:1, endln:2123:10 |UINT:38 |vpiTypespec: \_int_typespec: @@ -91417,7 +91417,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@ariane.REG_ADDR_SIZE), line:870:16, endln:870:29 |vpiParent: - \_module: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2114:1, endln:2123:10 + \_module_inst: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2114:1, endln:2123:10 |UINT:6 |vpiTypespec: \_int_typespec: @@ -91430,7 +91430,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@ariane.RVA), line:816:20, endln:816:23 |vpiParent: - \_module: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2114:1, endln:2123:10 + \_module_inst: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2114:1, endln:2123:10 |BIN:1 |vpiTypespec: \_bit_typespec: , line:816:16, endln:816:19 @@ -91446,7 +91446,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@ariane.RVD), line:814:20, endln:814:23 |vpiParent: - \_module: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2114:1, endln:2123:10 + \_module_inst: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2114:1, endln:2123:10 |INT:1 |vpiTypespec: \_bit_typespec: , line:814:16, endln:814:19 @@ -91462,7 +91462,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@ariane.RVF), line:813:20, endln:813:23 |vpiParent: - \_module: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2114:1, endln:2123:10 + \_module_inst: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2114:1, endln:2123:10 |INT:1 |vpiTypespec: \_bit_typespec: , line:813:16, endln:813:19 @@ -91478,7 +91478,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@ariane.RVFVEC), line:848:20, endln:848:26 |vpiParent: - \_module: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2114:1, endln:2123:10 + \_module_inst: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2114:1, endln:2123:10 |UINT:0 |vpiTypespec: \_bit_typespec: , line:848:16, endln:848:19 @@ -91494,7 +91494,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@ariane.SMODE_STATUS_READ_MASK), line:905:29, endln:905:51 |vpiParent: - \_module: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2114:1, endln:2123:10 + \_module_inst: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2114:1, endln:2123:10 |vpiTypespec: \_logic_typespec: , line:905:16, endln:905:28 |vpiParent: @@ -91528,7 +91528,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@ariane.SMODE_STATUS_WRITE_MASK), line:918:29, endln:918:52 |vpiParent: - \_module: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2114:1, endln:2123:10 + \_module_inst: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2114:1, endln:2123:10 |vpiTypespec: \_logic_typespec: , line:918:16, endln:918:28 |vpiParent: @@ -91562,7 +91562,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@ariane.SupervisorIrq), line:1013:16, endln:1013:29 |vpiParent: - \_module: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2114:1, endln:2123:10 + \_module_inst: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2114:1, endln:2123:10 |UINT:1 |vpiTypespec: \_int_typespec: @@ -91575,7 +91575,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@ariane.TRANS_ID_BITS), line:780:16, endln:780:29 |vpiParent: - \_module: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2114:1, endln:2123:10 + \_module_inst: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2114:1, endln:2123:10 |UINT:3 |vpiTypespec: \_int_typespec: @@ -91588,7 +91588,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@ariane.XF16), line:819:20, endln:819:24 |vpiParent: - \_module: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2114:1, endln:2123:10 + \_module_inst: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2114:1, endln:2123:10 |BIN:0 |vpiTypespec: \_bit_typespec: , line:819:16, endln:819:19 @@ -91604,7 +91604,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@ariane.XF16ALT), line:820:20, endln:820:27 |vpiParent: - \_module: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2114:1, endln:2123:10 + \_module_inst: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2114:1, endln:2123:10 |BIN:0 |vpiTypespec: \_bit_typespec: , line:820:16, endln:820:19 @@ -91620,7 +91620,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@ariane.XF16ALTVEC), line:850:20, endln:850:30 |vpiParent: - \_module: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2114:1, endln:2123:10 + \_module_inst: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2114:1, endln:2123:10 |UINT:0 |vpiTypespec: \_bit_typespec: , line:850:16, endln:850:19 @@ -91636,7 +91636,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@ariane.XF16VEC), line:849:20, endln:849:27 |vpiParent: - \_module: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2114:1, endln:2123:10 + \_module_inst: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2114:1, endln:2123:10 |UINT:0 |vpiTypespec: \_bit_typespec: , line:849:16, endln:849:19 @@ -91652,7 +91652,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@ariane.XF8), line:821:20, endln:821:23 |vpiParent: - \_module: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2114:1, endln:2123:10 + \_module_inst: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2114:1, endln:2123:10 |BIN:0 |vpiTypespec: \_bit_typespec: , line:821:16, endln:821:19 @@ -91668,7 +91668,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@ariane.XF8VEC), line:851:20, endln:851:26 |vpiParent: - \_module: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2114:1, endln:2123:10 + \_module_inst: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2114:1, endln:2123:10 |UINT:0 |vpiTypespec: \_bit_typespec: , line:851:16, endln:851:19 @@ -91684,7 +91684,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@ariane.XFVEC), line:822:20, endln:822:25 |vpiParent: - \_module: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2114:1, endln:2123:10 + \_module_inst: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2114:1, endln:2123:10 |BIN:0 |vpiTypespec: \_bit_typespec: , line:822:16, endln:822:19 @@ -91700,7 +91700,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@ariane.ZERO_TVAL), line:902:20, endln:902:29 |vpiParent: - \_module: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2114:1, endln:2123:10 + \_module_inst: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2114:1, endln:2123:10 |BIN:0 |vpiTypespec: \_bit_typespec: , line:902:16, endln:902:19 @@ -91716,7 +91716,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@ariane.ArianeCfg), line:2115:38, endln:2115:47 |vpiParent: - \_module: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2114:1, endln:2123:10 + \_module_inst: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2114:1, endln:2123:10 |vpiTypespec: \_struct_typespec: (ariane_pkg::ariane_cfg_t), line:684:13, endln:684:19 |vpiName:ArianeCfg @@ -91724,7 +91724,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:682:16, endln:682:31 |vpiParent: - \_module: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2114:1, endln:2123:10 + \_module_inst: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2114:1, endln:2123:10 |vpiRhs: \_constant: , line:682:29, endln:682:31 |vpiParent: @@ -91753,7 +91753,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:706:29, endln:728:6 |vpiParent: - \_module: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2114:1, endln:2123:10 + \_module_inst: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2114:1, endln:2123:10 |vpiRhs: \_operation: , line:706:51, endln:728:6 |vpiParent: @@ -92565,7 +92565,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:779:16, endln:779:33 |vpiParent: - \_module: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2114:1, endln:2123:10 + \_module_inst: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2114:1, endln:2123:10 |vpiRhs: \_constant: , line:779:32, endln:779:33 |vpiParent: @@ -92594,7 +92594,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:780:16, endln:780:53 |vpiParent: - \_module: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2114:1, endln:2123:10 + \_module_inst: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2114:1, endln:2123:10 |vpiRhs: \_constant: , line:780:32, endln:780:53 |vpiParent: @@ -92623,7 +92623,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:782:16, endln:782:60 |vpiParent: - \_module: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2114:1, endln:2123:10 + \_module_inst: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2114:1, endln:2123:10 |vpiRhs: \_constant: , line:782:32, endln:782:51 |vpiParent: @@ -92652,7 +92652,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:783:16, endln:783:43 |vpiParent: - \_module: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2114:1, endln:2123:10 + \_module_inst: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2114:1, endln:2123:10 |vpiRhs: \_constant: , line:783:42, endln:783:43 |vpiParent: @@ -92681,7 +92681,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:784:16, endln:784:35 |vpiParent: - \_module: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2114:1, endln:2123:10 + \_module_inst: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2114:1, endln:2123:10 |vpiRhs: \_constant: , line:784:34, endln:784:35 |vpiParent: @@ -92710,7 +92710,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:786:16, endln:786:36 |vpiParent: - \_module: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2114:1, endln:2123:10 + \_module_inst: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2114:1, endln:2123:10 |vpiRhs: \_constant: , line:786:32, endln:786:36 |vpiParent: @@ -92767,7 +92767,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:788:16, endln:788:31 |vpiParent: - \_module: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2114:1, endln:2123:10 + \_module_inst: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2114:1, endln:2123:10 |vpiRhs: \_constant: , line:788:30, endln:788:31 |vpiParent: @@ -92796,7 +92796,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:791:29, endln:791:50 |vpiParent: - \_module: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2114:1, endln:2123:10 + \_module_inst: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2114:1, endln:2123:10 |vpiRhs: \_constant: , line:791:49, endln:791:50 |vpiParent: @@ -92829,7 +92829,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:792:29, endln:792:51 |vpiParent: - \_module: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2114:1, endln:2123:10 + \_module_inst: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2114:1, endln:2123:10 |vpiRhs: \_constant: , line:792:50, endln:792:51 |vpiParent: @@ -92862,7 +92862,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:795:29, endln:795:45 |vpiParent: - \_module: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2114:1, endln:2123:10 + \_module_inst: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2114:1, endln:2123:10 |vpiRhs: \_constant: , line:795:44, endln:795:45 |vpiParent: @@ -92895,7 +92895,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:804:29, endln:804:45 |vpiParent: - \_module: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2114:1, endln:2123:10 + \_module_inst: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2114:1, endln:2123:10 |vpiRhs: \_constant: , line:804:44, endln:804:45 |vpiParent: @@ -92928,7 +92928,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:813:20, endln:813:42 |vpiParent: - \_module: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2114:1, endln:2123:10 + \_module_inst: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2114:1, endln:2123:10 |vpiRhs: \_constant: , line:813:26, endln:813:33 |vpiParent: @@ -92963,7 +92963,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:814:20, endln:814:42 |vpiParent: - \_module: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2114:1, endln:2123:10 + \_module_inst: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2114:1, endln:2123:10 |vpiRhs: \_constant: , line:814:26, endln:814:33 |vpiParent: @@ -92998,7 +92998,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:816:20, endln:816:30 |vpiParent: - \_module: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2114:1, endln:2123:10 + \_module_inst: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2114:1, endln:2123:10 |vpiRhs: \_constant: , line:816:26, endln:816:30 |vpiParent: @@ -93033,7 +93033,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:819:20, endln:819:34 |vpiParent: - \_module: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2114:1, endln:2123:10 + \_module_inst: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2114:1, endln:2123:10 |vpiRhs: \_constant: , line:819:30, endln:819:34 |vpiParent: @@ -93068,7 +93068,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:820:20, endln:820:34 |vpiParent: - \_module: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2114:1, endln:2123:10 + \_module_inst: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2114:1, endln:2123:10 |vpiRhs: \_constant: , line:820:30, endln:820:34 |vpiParent: @@ -93103,7 +93103,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:821:20, endln:821:34 |vpiParent: - \_module: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2114:1, endln:2123:10 + \_module_inst: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2114:1, endln:2123:10 |vpiRhs: \_constant: , line:821:30, endln:821:34 |vpiParent: @@ -93138,7 +93138,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:822:20, endln:822:34 |vpiParent: - \_module: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2114:1, endln:2123:10 + \_module_inst: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2114:1, endln:2123:10 |vpiRhs: \_constant: , line:822:30, endln:822:34 |vpiParent: @@ -93173,7 +93173,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:825:29, endln:825:51 |vpiParent: - \_module: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2114:1, endln:2123:10 + \_module_inst: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2114:1, endln:2123:10 |vpiRhs: \_constant: , line:825:48, endln:825:51 |vpiParent: @@ -93206,7 +93206,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:826:29, endln:826:51 |vpiParent: - \_module: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2114:1, endln:2123:10 + \_module_inst: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2114:1, endln:2123:10 |vpiRhs: \_constant: , line:826:48, endln:826:51 |vpiParent: @@ -93239,7 +93239,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:827:29, endln:827:51 |vpiParent: - \_module: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2114:1, endln:2123:10 + \_module_inst: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2114:1, endln:2123:10 |vpiRhs: \_constant: , line:827:48, endln:827:51 |vpiParent: @@ -93272,7 +93272,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:828:29, endln:828:51 |vpiParent: - \_module: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2114:1, endln:2123:10 + \_module_inst: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2114:1, endln:2123:10 |vpiRhs: \_constant: , line:828:48, endln:828:51 |vpiParent: @@ -93305,7 +93305,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:829:29, endln:829:51 |vpiParent: - \_module: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2114:1, endln:2123:10 + \_module_inst: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2114:1, endln:2123:10 |vpiRhs: \_constant: , line:829:48, endln:829:51 |vpiParent: @@ -93338,7 +93338,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:830:29, endln:830:51 |vpiParent: - \_module: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2114:1, endln:2123:10 + \_module_inst: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2114:1, endln:2123:10 |vpiRhs: \_constant: , line:830:48, endln:830:51 |vpiParent: @@ -93371,7 +93371,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:831:29, endln:831:51 |vpiParent: - \_module: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2114:1, endln:2123:10 + \_module_inst: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2114:1, endln:2123:10 |vpiRhs: \_constant: , line:831:48, endln:831:51 |vpiParent: @@ -93404,7 +93404,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:832:29, endln:832:51 |vpiParent: - \_module: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2114:1, endln:2123:10 + \_module_inst: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2114:1, endln:2123:10 |vpiRhs: \_constant: , line:832:48, endln:832:51 |vpiParent: @@ -93437,7 +93437,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:836:20, endln:836:65 |vpiParent: - \_module: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2114:1, endln:2123:10 + \_module_inst: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2114:1, endln:2123:10 |vpiRhs: \_constant: , line:836:33, endln:836:59 |vpiParent: @@ -93472,7 +93472,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:839:16, endln:844:27 |vpiParent: - \_module: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2114:1, endln:2123:10 + \_module_inst: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2114:1, endln:2123:10 |vpiRhs: \_constant: , line:839:26, endln:839:29 |vpiParent: @@ -93501,7 +93501,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:846:20, endln:846:54 |vpiParent: - \_module: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2114:1, endln:2123:10 + \_module_inst: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2114:1, endln:2123:10 |vpiRhs: \_constant: , line:846:26, endln:846:46 |vpiParent: @@ -93536,7 +93536,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:848:20, endln:848:58 |vpiParent: - \_module: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2114:1, endln:2123:10 + \_module_inst: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2114:1, endln:2123:10 |vpiRhs: \_constant: , line:848:33, endln:848:48 |vpiParent: @@ -93571,7 +93571,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:849:20, endln:849:58 |vpiParent: - \_module: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2114:1, endln:2123:10 + \_module_inst: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2114:1, endln:2123:10 |vpiRhs: \_constant: , line:849:33, endln:849:48 |vpiParent: @@ -93606,7 +93606,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:850:20, endln:850:58 |vpiParent: - \_module: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2114:1, endln:2123:10 + \_module_inst: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2114:1, endln:2123:10 |vpiRhs: \_constant: , line:850:33, endln:850:48 |vpiParent: @@ -93641,7 +93641,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:851:20, endln:851:57 |vpiParent: - \_module: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2114:1, endln:2123:10 + \_module_inst: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2114:1, endln:2123:10 |vpiRhs: \_constant: , line:851:33, endln:851:48 |vpiParent: @@ -93676,7 +93676,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:855:30, endln:855:78 |vpiParent: - \_module: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2114:1, endln:2123:10 + \_module_inst: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2114:1, endln:2123:10 |vpiRhs: \_operation: , line:855:47, endln:855:78 |vpiParent: @@ -93771,7 +93771,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:857:30, endln:867:86 |vpiParent: - \_module: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2114:1, endln:2123:10 + \_module_inst: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2114:1, endln:2123:10 |vpiRhs: \_operation: , line:857:41, endln:867:86 |vpiParent: @@ -94138,7 +94138,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:870:16, endln:870:33 |vpiParent: - \_module: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2114:1, endln:2123:10 + \_module_inst: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2114:1, endln:2123:10 |vpiRhs: \_constant: , line:870:32, endln:870:33 |vpiParent: @@ -94167,7 +94167,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:871:16, endln:871:31 |vpiParent: - \_module: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2114:1, endln:2123:10 + \_module_inst: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2114:1, endln:2123:10 |vpiRhs: \_constant: , line:871:30, endln:871:31 |vpiParent: @@ -94196,7 +94196,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:874:31, endln:881:48 |vpiParent: - \_module: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2114:1, endln:2123:10 + \_module_inst: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2114:1, endln:2123:10 |vpiRhs: \_operation: , line:874:47, endln:881:48 |vpiParent: @@ -94318,7 +94318,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:884:20, endln:884:50 |vpiParent: - \_module: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2114:1, endln:2123:10 + \_module_inst: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2114:1, endln:2123:10 |vpiRhs: \_constant: , line:884:46, endln:884:50 |vpiParent: @@ -94353,7 +94353,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:890:22, endln:890:48 |vpiParent: - \_module: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2114:1, endln:2123:10 + \_module_inst: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2114:1, endln:2123:10 |vpiRhs: \_constant: , line:890:44, endln:890:48 |vpiParent: @@ -94386,7 +94386,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:900:20, endln:900:45 |vpiParent: - \_module: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2114:1, endln:2123:10 + \_module_inst: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2114:1, endln:2123:10 |vpiRhs: \_constant: , line:900:41, endln:900:45 |vpiParent: @@ -94421,7 +94421,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:901:20, endln:901:37 |vpiParent: - \_module: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2114:1, endln:2123:10 + \_module_inst: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2114:1, endln:2123:10 |vpiRhs: \_constant: , line:901:33, endln:901:37 |vpiParent: @@ -94456,7 +94456,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:902:20, endln:902:36 |vpiParent: - \_module: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2114:1, endln:2123:10 + \_module_inst: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2114:1, endln:2123:10 |vpiRhs: \_constant: , line:902:32, endln:902:36 |vpiParent: @@ -94491,7 +94491,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:905:29, endln:916:71 |vpiParent: - \_module: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2114:1, endln:2123:10 + \_module_inst: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2114:1, endln:2123:10 |vpiRhs: \_operation: , line:905:54, endln:916:71 |vpiParent: @@ -94997,7 +94997,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:918:29, endln:923:73 |vpiParent: - \_module: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2114:1, endln:2123:10 + \_module_inst: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2114:1, endln:2123:10 |vpiRhs: \_operation: , line:918:55, endln:923:73 |vpiParent: @@ -95264,7 +95264,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:929:29, endln:929:50 |vpiParent: - \_module: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2114:1, endln:2123:10 + \_module_inst: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2114:1, endln:2123:10 |vpiRhs: \_constant: , line:929:49, endln:929:50 |vpiParent: @@ -95297,7 +95297,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:930:29, endln:930:51 |vpiParent: - \_module: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2114:1, endln:2123:10 + \_module_inst: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2114:1, endln:2123:10 |vpiRhs: \_constant: , line:930:49, endln:930:51 |vpiParent: @@ -95330,7 +95330,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:932:29, endln:932:63 |vpiParent: - \_module: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2114:1, endln:2123:10 + \_module_inst: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2114:1, endln:2123:10 |vpiRhs: \_constant: , line:932:47, endln:932:58 |vpiParent: @@ -95363,7 +95363,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:1011:16, endln:1011:40 |vpiParent: - \_module: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2114:1, endln:2123:10 + \_module_inst: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2114:1, endln:2123:10 |vpiRhs: \_constant: , line:1011:35, endln:1011:40 |vpiParent: @@ -95420,7 +95420,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:1013:16, endln:1013:33 |vpiParent: - \_module: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2114:1, endln:2123:10 + \_module_inst: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2114:1, endln:2123:10 |vpiRhs: \_constant: , line:1013:32, endln:1013:33 |vpiParent: @@ -95449,7 +95449,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:1014:16, endln:1014:30 |vpiParent: - \_module: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2114:1, endln:2123:10 + \_module_inst: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2114:1, endln:2123:10 |vpiRhs: \_constant: , line:1014:29, endln:1014:30 |vpiParent: @@ -95478,7 +95478,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:1069:27, endln:1069:55 |vpiParent: - \_module: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2114:1, endln:2123:10 + \_module_inst: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2114:1, endln:2123:10 |vpiRhs: \_constant: , line:1069:48, endln:1069:50 |vpiParent: @@ -95511,7 +95511,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:1070:29, endln:1070:51 |vpiParent: - \_module: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2114:1, endln:2123:10 + \_module_inst: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2114:1, endln:2123:10 |vpiRhs: \_constant: , line:1070:50, endln:1070:51 |vpiParent: @@ -95544,7 +95544,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:1071:29, endln:1071:92 |vpiParent: - \_module: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2114:1, endln:2123:10 + \_module_inst: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2114:1, endln:2123:10 |vpiRhs: \_constant: , line:1071:50, endln:1071:92 |vpiParent: @@ -95577,7 +95577,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:1072:29, endln:1072:80 |vpiParent: - \_module: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2114:1, endln:2123:10 + \_module_inst: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2114:1, endln:2123:10 |vpiRhs: \_constant: , line:1072:50, endln:1072:61 |vpiParent: @@ -95610,7 +95610,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:1073:29, endln:1073:53 |vpiParent: - \_module: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2114:1, endln:2123:10 + \_module_inst: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2114:1, endln:2123:10 |vpiRhs: \_constant: , line:1073:50, endln:1073:53 |vpiParent: @@ -95643,7 +95643,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:1075:27, endln:1075:55 |vpiParent: - \_module: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2114:1, endln:2123:10 + \_module_inst: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2114:1, endln:2123:10 |vpiRhs: \_constant: , line:1075:48, endln:1075:50 |vpiParent: @@ -95676,7 +95676,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:1076:28, endln:1076:50 |vpiParent: - \_module: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2114:1, endln:2123:10 + \_module_inst: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2114:1, endln:2123:10 |vpiRhs: \_constant: , line:1076:49, endln:1076:50 |vpiParent: @@ -95709,7 +95709,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:1077:29, endln:1077:92 |vpiParent: - \_module: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2114:1, endln:2123:10 + \_module_inst: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2114:1, endln:2123:10 |vpiRhs: \_constant: , line:1077:50, endln:1077:92 |vpiParent: @@ -95742,7 +95742,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:1078:29, endln:1078:80 |vpiParent: - \_module: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2114:1, endln:2123:10 + \_module_inst: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2114:1, endln:2123:10 |vpiRhs: \_constant: , line:1078:50, endln:1078:61 |vpiParent: @@ -95775,7 +95775,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:1079:29, endln:1079:53 |vpiParent: - \_module: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2114:1, endln:2123:10 + \_module_inst: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2114:1, endln:2123:10 |vpiRhs: \_constant: , line:1079:50, endln:1079:53 |vpiParent: @@ -95808,7 +95808,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:1293:16, endln:1293:32 |vpiParent: - \_module: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2114:1, endln:2123:10 + \_module_inst: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2114:1, endln:2123:10 |vpiRhs: \_constant: , line:1293:30, endln:1293:32 |vpiParent: @@ -95837,7 +95837,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:2115:38, endln:2115:85 |vpiParent: - \_module: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2114:1, endln:2123:10 + \_module_inst: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2114:1, endln:2123:10 |vpiRhs: \_operation: , line:2115:54, endln:2115:66 |vpiOpType:75 @@ -99881,14 +99881,14 @@ design: (work@top) |vpiInstance: \_package: ariane_pkg (ariane_pkg::), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:674:1, endln:1483:11 |uhdmallModules: -\_module: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2081:1, endln:2111:10 +\_module_inst: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2081:1, endln:2111:10 |vpiParent: \_design: (work@top) |vpiFullName:work@ex_stage |vpiParameter: \_parameter: (work@ex_stage.ARIANE_MARCHID), line:855:30, endln:855:44 |vpiParent: - \_module: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2081:1, endln:2111:10 + \_module_inst: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2081:1, endln:2111:10 |vpiTypespec: \_logic_typespec: (xlen_t), line:30:13, endln:30:29 |vpiParent: @@ -99923,7 +99923,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@ex_stage.ASID_WIDTH), line:782:16, endln:782:26 |vpiParent: - \_module: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2081:1, endln:2111:10 + \_module_inst: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2081:1, endln:2111:10 |INT:16 |vpiTypespec: \_int_typespec: @@ -99936,7 +99936,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@ex_stage.ArianeDefaultConfig), line:706:29, endln:706:48 |vpiParent: - \_module: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2081:1, endln:2111:10 + \_module_inst: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2081:1, endln:2111:10 |vpiTypespec: \_struct_typespec: (ariane_pkg::ariane_cfg_t), line:684:13, endln:684:19 |vpiParent: @@ -100473,7 +100473,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@ex_stage.BITS_SATURATION_COUNTER), line:783:16, endln:783:39 |vpiParent: - \_module: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2081:1, endln:2111:10 + \_module_inst: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2081:1, endln:2111:10 |UINT:2 |vpiTypespec: \_int_typespec: @@ -100486,7 +100486,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@ex_stage.CONFIG_L1D_SIZE), line:1075:27, endln:1075:42 |vpiParent: - \_module: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2081:1, endln:2111:10 + \_module_inst: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2081:1, endln:2111:10 |INT:32768 |vpiTypespec: \_int_typespec: , line:1075:14, endln:1075:26 @@ -100501,7 +100501,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@ex_stage.CONFIG_L1I_SIZE), line:1069:27, endln:1069:42 |vpiParent: - \_module: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2081:1, endln:2111:10 + \_module_inst: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2081:1, endln:2111:10 |INT:16384 |vpiTypespec: \_int_typespec: , line:1069:14, endln:1069:26 @@ -100516,7 +100516,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@ex_stage.DCACHE_INDEX_WIDTH), line:1077:29, endln:1077:47 |vpiParent: - \_module: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2081:1, endln:2111:10 + \_module_inst: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2081:1, endln:2111:10 |UINT:12 |vpiTypespec: \_int_typespec: , line:1077:16, endln:1077:28 @@ -100531,7 +100531,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@ex_stage.DCACHE_LINE_WIDTH), line:1079:29, endln:1079:46 |vpiParent: - \_module: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2081:1, endln:2111:10 + \_module_inst: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2081:1, endln:2111:10 |UINT:128 |vpiTypespec: \_int_typespec: , line:1079:16, endln:1079:28 @@ -100546,7 +100546,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@ex_stage.DCACHE_SET_ASSOC), line:1076:28, endln:1076:44 |vpiParent: - \_module: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2081:1, endln:2111:10 + \_module_inst: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2081:1, endln:2111:10 |UINT:8 |vpiTypespec: \_int_typespec: , line:1076:15, endln:1076:27 @@ -100561,7 +100561,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@ex_stage.DCACHE_TAG_WIDTH), line:1078:29, endln:1078:45 |vpiParent: - \_module: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2081:1, endln:2111:10 + \_module_inst: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2081:1, endln:2111:10 |INT:44 |vpiTypespec: \_int_typespec: , line:1078:16, endln:1078:28 @@ -100576,7 +100576,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@ex_stage.DEPTH_COMMIT), line:804:29, endln:804:41 |vpiParent: - \_module: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2081:1, endln:2111:10 + \_module_inst: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2081:1, endln:2111:10 |UINT:8 |vpiTypespec: \_int_typespec: , line:804:16, endln:804:28 @@ -100591,7 +100591,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@ex_stage.DEPTH_SPEC), line:795:29, endln:795:39 |vpiParent: - \_module: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2081:1, endln:2111:10 + \_module_inst: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2081:1, endln:2111:10 |UINT:4 |vpiTypespec: \_int_typespec: , line:795:16, endln:795:28 @@ -100606,7 +100606,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@ex_stage.DebugHartInfo), line:874:31, endln:874:44 |vpiParent: - \_module: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2081:1, endln:2111:10 + \_module_inst: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2081:1, endln:2111:10 |vpiTypespec: \_unsupported_typespec: (dm::hartinfo_t), line:874:16, endln:874:20 |vpiParent: @@ -100621,7 +100621,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@ex_stage.ENABLE_CYCLE_COUNT), line:900:20, endln:900:38 |vpiParent: - \_module: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2081:1, endln:2111:10 + \_module_inst: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2081:1, endln:2111:10 |BIN:1 |vpiTypespec: \_bit_typespec: , line:900:16, endln:900:19 @@ -100637,7 +100637,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@ex_stage.ENABLE_RENAME), line:786:16, endln:786:29 |vpiParent: - \_module: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2081:1, endln:2111:10 + \_module_inst: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2081:1, endln:2111:10 |BIN:0 |vpiTypespec: \_int_typespec: @@ -100664,7 +100664,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@ex_stage.ENABLE_SPIKE_COMMIT_LOG), line:884:20, endln:884:43 |vpiParent: - \_module: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2081:1, endln:2111:10 + \_module_inst: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2081:1, endln:2111:10 |BIN:1 |vpiTypespec: \_bit_typespec: , line:884:16, endln:884:19 @@ -100680,7 +100680,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@ex_stage.ENABLE_WFI), line:901:20, endln:901:30 |vpiParent: - \_module: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2081:1, endln:2111:10 + \_module_inst: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2081:1, endln:2111:10 |BIN:1 |vpiTypespec: \_bit_typespec: , line:901:16, endln:901:19 @@ -100696,7 +100696,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@ex_stage.EXC_OFF_RST), line:1011:16, endln:1011:27 |vpiParent: - \_module: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2081:1, endln:2111:10 + \_module_inst: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2081:1, endln:2111:10 |HEX:80 |vpiTypespec: \_int_typespec: @@ -100723,7 +100723,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@ex_stage.FETCH_FIFO_DEPTH), line:929:29, endln:929:45 |vpiParent: - \_module: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2081:1, endln:2111:10 + \_module_inst: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2081:1, endln:2111:10 |UINT:4 |vpiTypespec: \_int_typespec: , line:929:16, endln:929:28 @@ -100738,7 +100738,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@ex_stage.FETCH_WIDTH), line:930:29, endln:930:40 |vpiParent: - \_module: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2081:1, endln:2111:10 + \_module_inst: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2081:1, endln:2111:10 |UINT:32 |vpiTypespec: \_int_typespec: , line:930:16, endln:930:28 @@ -100753,7 +100753,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@ex_stage.FLEN), line:839:16, endln:839:20 |vpiParent: - \_module: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2081:1, endln:2111:10 + \_module_inst: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2081:1, endln:2111:10 |INT:64 |vpiTypespec: \_int_typespec: @@ -100766,7 +100766,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@ex_stage.FP_PRESENT), line:836:20, endln:836:30 |vpiParent: - \_module: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2081:1, endln:2111:10 + \_module_inst: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2081:1, endln:2111:10 |UINT:1 |vpiTypespec: \_bit_typespec: , line:836:16, endln:836:19 @@ -100782,7 +100782,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@ex_stage.ICACHE_INDEX_WIDTH), line:1071:29, endln:1071:47 |vpiParent: - \_module: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2081:1, endln:2111:10 + \_module_inst: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2081:1, endln:2111:10 |UINT:12 |vpiTypespec: \_int_typespec: , line:1071:16, endln:1071:28 @@ -100797,7 +100797,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@ex_stage.ICACHE_LINE_WIDTH), line:1073:29, endln:1073:46 |vpiParent: - \_module: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2081:1, endln:2111:10 + \_module_inst: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2081:1, endln:2111:10 |UINT:128 |vpiTypespec: \_int_typespec: , line:1073:16, endln:1073:28 @@ -100812,7 +100812,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@ex_stage.ICACHE_SET_ASSOC), line:1070:29, endln:1070:45 |vpiParent: - \_module: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2081:1, endln:2111:10 + \_module_inst: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2081:1, endln:2111:10 |UINT:4 |vpiTypespec: \_int_typespec: , line:1070:16, endln:1070:28 @@ -100827,7 +100827,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@ex_stage.ICACHE_TAG_WIDTH), line:1072:29, endln:1072:45 |vpiParent: - \_module: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2081:1, endln:2111:10 + \_module_inst: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2081:1, endln:2111:10 |INT:44 |vpiTypespec: \_int_typespec: , line:1072:16, endln:1072:28 @@ -100842,7 +100842,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@ex_stage.INSTR_PER_FETCH), line:932:29, endln:932:44 |vpiParent: - \_module: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2081:1, endln:2111:10 + \_module_inst: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2081:1, endln:2111:10 |INT:2 |vpiTypespec: \_int_typespec: , line:932:16, endln:932:28 @@ -100857,7 +100857,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@ex_stage.INVALIDATE_ON_FLUSH), line:890:22, endln:890:41 |vpiParent: - \_module: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2081:1, endln:2111:10 + \_module_inst: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2081:1, endln:2111:10 |BIN:1 |vpiTypespec: \_logic_typespec: , line:890:16, endln:890:21 @@ -100872,7 +100872,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@ex_stage.ISA_CODE), line:857:30, endln:857:38 |vpiParent: - \_module: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2081:1, endln:2111:10 + \_module_inst: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2081:1, endln:2111:10 |vpiTypespec: \_logic_typespec: (xlen_t), line:30:13, endln:30:29 |vpiParent: @@ -100907,7 +100907,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@ex_stage.ISSUE_WIDTH), line:788:16, endln:788:27 |vpiParent: - \_module: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2081:1, endln:2111:10 + \_module_inst: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2081:1, endln:2111:10 |UINT:1 |vpiTypespec: \_int_typespec: @@ -100920,7 +100920,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@ex_stage.LAT_COMP_FP16), line:827:29, endln:827:42 |vpiParent: - \_module: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2081:1, endln:2111:10 + \_module_inst: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2081:1, endln:2111:10 |DEC:1 |vpiTypespec: \_int_typespec: , line:827:16, endln:827:28 @@ -100935,7 +100935,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@ex_stage.LAT_COMP_FP16ALT), line:828:29, endln:828:45 |vpiParent: - \_module: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2081:1, endln:2111:10 + \_module_inst: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2081:1, endln:2111:10 |DEC:1 |vpiTypespec: \_int_typespec: , line:828:16, endln:828:28 @@ -100950,7 +100950,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@ex_stage.LAT_COMP_FP32), line:825:29, endln:825:42 |vpiParent: - \_module: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2081:1, endln:2111:10 + \_module_inst: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2081:1, endln:2111:10 |DEC:2 |vpiTypespec: \_int_typespec: , line:825:16, endln:825:28 @@ -100965,7 +100965,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@ex_stage.LAT_COMP_FP64), line:826:29, endln:826:42 |vpiParent: - \_module: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2081:1, endln:2111:10 + \_module_inst: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2081:1, endln:2111:10 |DEC:3 |vpiTypespec: \_int_typespec: , line:826:16, endln:826:28 @@ -100980,7 +100980,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@ex_stage.LAT_COMP_FP8), line:829:29, endln:829:41 |vpiParent: - \_module: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2081:1, endln:2111:10 + \_module_inst: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2081:1, endln:2111:10 |DEC:1 |vpiTypespec: \_int_typespec: , line:829:16, endln:829:28 @@ -100995,7 +100995,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@ex_stage.LAT_CONV), line:832:29, endln:832:37 |vpiParent: - \_module: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2081:1, endln:2111:10 + \_module_inst: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2081:1, endln:2111:10 |DEC:2 |vpiTypespec: \_int_typespec: , line:832:16, endln:832:28 @@ -101010,7 +101010,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@ex_stage.LAT_DIVSQRT), line:830:29, endln:830:40 |vpiParent: - \_module: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2081:1, endln:2111:10 + \_module_inst: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2081:1, endln:2111:10 |DEC:2 |vpiTypespec: \_int_typespec: , line:830:16, endln:830:28 @@ -101025,7 +101025,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@ex_stage.LAT_NONCOMP), line:831:29, endln:831:40 |vpiParent: - \_module: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2081:1, endln:2111:10 + \_module_inst: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2081:1, endln:2111:10 |DEC:1 |vpiTypespec: \_int_typespec: , line:831:16, endln:831:28 @@ -101040,7 +101040,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@ex_stage.MachineIrq), line:1014:16, endln:1014:26 |vpiParent: - \_module: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2081:1, endln:2111:10 + \_module_inst: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2081:1, endln:2111:10 |UINT:0 |vpiTypespec: \_int_typespec: @@ -101053,7 +101053,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@ex_stage.NR_COMMIT_PORTS), line:784:16, endln:784:31 |vpiParent: - \_module: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2081:1, endln:2111:10 + \_module_inst: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2081:1, endln:2111:10 |UINT:2 |vpiTypespec: \_int_typespec: @@ -101066,7 +101066,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@ex_stage.NR_LOAD_PIPE_REGS), line:791:29, endln:791:46 |vpiParent: - \_module: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2081:1, endln:2111:10 + \_module_inst: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2081:1, endln:2111:10 |UINT:1 |vpiTypespec: \_int_typespec: , line:791:16, endln:791:28 @@ -101081,7 +101081,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@ex_stage.NR_SB_ENTRIES), line:779:16, endln:779:29 |vpiParent: - \_module: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2081:1, endln:2111:10 + \_module_inst: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2081:1, endln:2111:10 |UINT:8 |vpiTypespec: \_int_typespec: @@ -101094,7 +101094,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@ex_stage.NR_STORE_PIPE_REGS), line:792:29, endln:792:47 |vpiParent: - \_module: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2081:1, endln:2111:10 + \_module_inst: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2081:1, endln:2111:10 |UINT:0 |vpiTypespec: \_int_typespec: , line:792:16, endln:792:28 @@ -101109,7 +101109,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@ex_stage.NR_WB_PORTS), line:871:16, endln:871:27 |vpiParent: - \_module: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2081:1, endln:2111:10 + \_module_inst: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2081:1, endln:2111:10 |UINT:4 |vpiTypespec: \_int_typespec: @@ -101122,7 +101122,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@ex_stage.NSX), line:846:20, endln:846:23 |vpiParent: - \_module: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2081:1, endln:2111:10 + \_module_inst: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2081:1, endln:2111:10 |UINT:0 |vpiTypespec: \_bit_typespec: , line:846:16, endln:846:19 @@ -101138,7 +101138,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@ex_stage.NrMaxRules), line:682:16, endln:682:26 |vpiParent: - \_module: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2081:1, endln:2111:10 + \_module_inst: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2081:1, endln:2111:10 |UINT:16 |vpiTypespec: \_int_typespec: @@ -101151,7 +101151,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@ex_stage.PPN4K_WIDTH), line:1293:16, endln:1293:27 |vpiParent: - \_module: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2081:1, endln:2111:10 + \_module_inst: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2081:1, endln:2111:10 |UINT:38 |vpiTypespec: \_int_typespec: @@ -101164,7 +101164,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@ex_stage.REG_ADDR_SIZE), line:870:16, endln:870:29 |vpiParent: - \_module: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2081:1, endln:2111:10 + \_module_inst: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2081:1, endln:2111:10 |UINT:6 |vpiTypespec: \_int_typespec: @@ -101177,7 +101177,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@ex_stage.RVA), line:816:20, endln:816:23 |vpiParent: - \_module: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2081:1, endln:2111:10 + \_module_inst: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2081:1, endln:2111:10 |BIN:1 |vpiTypespec: \_bit_typespec: , line:816:16, endln:816:19 @@ -101193,7 +101193,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@ex_stage.RVD), line:814:20, endln:814:23 |vpiParent: - \_module: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2081:1, endln:2111:10 + \_module_inst: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2081:1, endln:2111:10 |INT:1 |vpiTypespec: \_bit_typespec: , line:814:16, endln:814:19 @@ -101209,7 +101209,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@ex_stage.RVF), line:813:20, endln:813:23 |vpiParent: - \_module: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2081:1, endln:2111:10 + \_module_inst: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2081:1, endln:2111:10 |INT:1 |vpiTypespec: \_bit_typespec: , line:813:16, endln:813:19 @@ -101225,7 +101225,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@ex_stage.RVFVEC), line:848:20, endln:848:26 |vpiParent: - \_module: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2081:1, endln:2111:10 + \_module_inst: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2081:1, endln:2111:10 |UINT:0 |vpiTypespec: \_bit_typespec: , line:848:16, endln:848:19 @@ -101241,7 +101241,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@ex_stage.SMODE_STATUS_READ_MASK), line:905:29, endln:905:51 |vpiParent: - \_module: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2081:1, endln:2111:10 + \_module_inst: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2081:1, endln:2111:10 |vpiTypespec: \_logic_typespec: , line:905:16, endln:905:28 |vpiParent: @@ -101275,7 +101275,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@ex_stage.SMODE_STATUS_WRITE_MASK), line:918:29, endln:918:52 |vpiParent: - \_module: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2081:1, endln:2111:10 + \_module_inst: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2081:1, endln:2111:10 |vpiTypespec: \_logic_typespec: , line:918:16, endln:918:28 |vpiParent: @@ -101309,7 +101309,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@ex_stage.SupervisorIrq), line:1013:16, endln:1013:29 |vpiParent: - \_module: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2081:1, endln:2111:10 + \_module_inst: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2081:1, endln:2111:10 |UINT:1 |vpiTypespec: \_int_typespec: @@ -101322,7 +101322,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@ex_stage.TRANS_ID_BITS), line:780:16, endln:780:29 |vpiParent: - \_module: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2081:1, endln:2111:10 + \_module_inst: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2081:1, endln:2111:10 |UINT:3 |vpiTypespec: \_int_typespec: @@ -101335,7 +101335,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@ex_stage.XF16), line:819:20, endln:819:24 |vpiParent: - \_module: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2081:1, endln:2111:10 + \_module_inst: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2081:1, endln:2111:10 |BIN:0 |vpiTypespec: \_bit_typespec: , line:819:16, endln:819:19 @@ -101351,7 +101351,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@ex_stage.XF16ALT), line:820:20, endln:820:27 |vpiParent: - \_module: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2081:1, endln:2111:10 + \_module_inst: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2081:1, endln:2111:10 |BIN:0 |vpiTypespec: \_bit_typespec: , line:820:16, endln:820:19 @@ -101367,7 +101367,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@ex_stage.XF16ALTVEC), line:850:20, endln:850:30 |vpiParent: - \_module: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2081:1, endln:2111:10 + \_module_inst: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2081:1, endln:2111:10 |UINT:0 |vpiTypespec: \_bit_typespec: , line:850:16, endln:850:19 @@ -101383,7 +101383,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@ex_stage.XF16VEC), line:849:20, endln:849:27 |vpiParent: - \_module: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2081:1, endln:2111:10 + \_module_inst: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2081:1, endln:2111:10 |UINT:0 |vpiTypespec: \_bit_typespec: , line:849:16, endln:849:19 @@ -101399,7 +101399,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@ex_stage.XF8), line:821:20, endln:821:23 |vpiParent: - \_module: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2081:1, endln:2111:10 + \_module_inst: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2081:1, endln:2111:10 |BIN:0 |vpiTypespec: \_bit_typespec: , line:821:16, endln:821:19 @@ -101415,7 +101415,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@ex_stage.XF8VEC), line:851:20, endln:851:26 |vpiParent: - \_module: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2081:1, endln:2111:10 + \_module_inst: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2081:1, endln:2111:10 |UINT:0 |vpiTypespec: \_bit_typespec: , line:851:16, endln:851:19 @@ -101431,7 +101431,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@ex_stage.XFVEC), line:822:20, endln:822:25 |vpiParent: - \_module: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2081:1, endln:2111:10 + \_module_inst: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2081:1, endln:2111:10 |BIN:0 |vpiTypespec: \_bit_typespec: , line:822:16, endln:822:19 @@ -101447,7 +101447,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@ex_stage.ZERO_TVAL), line:902:20, endln:902:29 |vpiParent: - \_module: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2081:1, endln:2111:10 + \_module_inst: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2081:1, endln:2111:10 |BIN:0 |vpiTypespec: \_bit_typespec: , line:902:16, endln:902:19 @@ -101463,7 +101463,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@ex_stage.ASID_WIDTH), line:2082:28, endln:2082:38 |vpiParent: - \_module: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2081:1, endln:2111:10 + \_module_inst: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2081:1, endln:2111:10 |UINT:1 |vpiTypespec: \_int_typespec: , line:2082:15, endln:2082:27 @@ -101474,7 +101474,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@ex_stage.ArianeCfg), line:2083:40, endln:2083:49 |vpiParent: - \_module: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2081:1, endln:2111:10 + \_module_inst: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2081:1, endln:2111:10 |vpiTypespec: \_struct_typespec: (ariane_pkg::ariane_cfg_t), line:684:13, endln:684:19 |vpiName:ArianeCfg @@ -101482,7 +101482,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:682:16, endln:682:31 |vpiParent: - \_module: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2081:1, endln:2111:10 + \_module_inst: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2081:1, endln:2111:10 |vpiRhs: \_constant: , line:682:29, endln:682:31 |vpiParent: @@ -101511,7 +101511,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:706:29, endln:728:6 |vpiParent: - \_module: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2081:1, endln:2111:10 + \_module_inst: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2081:1, endln:2111:10 |vpiRhs: \_operation: , line:706:51, endln:728:6 |vpiParent: @@ -102323,7 +102323,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:779:16, endln:779:33 |vpiParent: - \_module: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2081:1, endln:2111:10 + \_module_inst: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2081:1, endln:2111:10 |vpiRhs: \_constant: , line:779:32, endln:779:33 |vpiParent: @@ -102352,7 +102352,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:780:16, endln:780:53 |vpiParent: - \_module: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2081:1, endln:2111:10 + \_module_inst: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2081:1, endln:2111:10 |vpiRhs: \_constant: , line:780:32, endln:780:53 |vpiParent: @@ -102381,7 +102381,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:782:16, endln:782:60 |vpiParent: - \_module: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2081:1, endln:2111:10 + \_module_inst: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2081:1, endln:2111:10 |vpiRhs: \_constant: , line:782:32, endln:782:51 |vpiParent: @@ -102410,7 +102410,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:783:16, endln:783:43 |vpiParent: - \_module: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2081:1, endln:2111:10 + \_module_inst: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2081:1, endln:2111:10 |vpiRhs: \_constant: , line:783:42, endln:783:43 |vpiParent: @@ -102439,7 +102439,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:784:16, endln:784:35 |vpiParent: - \_module: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2081:1, endln:2111:10 + \_module_inst: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2081:1, endln:2111:10 |vpiRhs: \_constant: , line:784:34, endln:784:35 |vpiParent: @@ -102468,7 +102468,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:786:16, endln:786:36 |vpiParent: - \_module: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2081:1, endln:2111:10 + \_module_inst: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2081:1, endln:2111:10 |vpiRhs: \_constant: , line:786:32, endln:786:36 |vpiParent: @@ -102525,7 +102525,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:788:16, endln:788:31 |vpiParent: - \_module: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2081:1, endln:2111:10 + \_module_inst: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2081:1, endln:2111:10 |vpiRhs: \_constant: , line:788:30, endln:788:31 |vpiParent: @@ -102554,7 +102554,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:791:29, endln:791:50 |vpiParent: - \_module: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2081:1, endln:2111:10 + \_module_inst: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2081:1, endln:2111:10 |vpiRhs: \_constant: , line:791:49, endln:791:50 |vpiParent: @@ -102587,7 +102587,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:792:29, endln:792:51 |vpiParent: - \_module: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2081:1, endln:2111:10 + \_module_inst: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2081:1, endln:2111:10 |vpiRhs: \_constant: , line:792:50, endln:792:51 |vpiParent: @@ -102620,7 +102620,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:795:29, endln:795:45 |vpiParent: - \_module: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2081:1, endln:2111:10 + \_module_inst: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2081:1, endln:2111:10 |vpiRhs: \_constant: , line:795:44, endln:795:45 |vpiParent: @@ -102653,7 +102653,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:804:29, endln:804:45 |vpiParent: - \_module: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2081:1, endln:2111:10 + \_module_inst: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2081:1, endln:2111:10 |vpiRhs: \_constant: , line:804:44, endln:804:45 |vpiParent: @@ -102686,7 +102686,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:813:20, endln:813:42 |vpiParent: - \_module: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2081:1, endln:2111:10 + \_module_inst: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2081:1, endln:2111:10 |vpiRhs: \_constant: , line:813:26, endln:813:33 |vpiParent: @@ -102721,7 +102721,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:814:20, endln:814:42 |vpiParent: - \_module: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2081:1, endln:2111:10 + \_module_inst: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2081:1, endln:2111:10 |vpiRhs: \_constant: , line:814:26, endln:814:33 |vpiParent: @@ -102756,7 +102756,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:816:20, endln:816:30 |vpiParent: - \_module: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2081:1, endln:2111:10 + \_module_inst: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2081:1, endln:2111:10 |vpiRhs: \_constant: , line:816:26, endln:816:30 |vpiParent: @@ -102791,7 +102791,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:819:20, endln:819:34 |vpiParent: - \_module: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2081:1, endln:2111:10 + \_module_inst: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2081:1, endln:2111:10 |vpiRhs: \_constant: , line:819:30, endln:819:34 |vpiParent: @@ -102826,7 +102826,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:820:20, endln:820:34 |vpiParent: - \_module: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2081:1, endln:2111:10 + \_module_inst: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2081:1, endln:2111:10 |vpiRhs: \_constant: , line:820:30, endln:820:34 |vpiParent: @@ -102861,7 +102861,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:821:20, endln:821:34 |vpiParent: - \_module: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2081:1, endln:2111:10 + \_module_inst: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2081:1, endln:2111:10 |vpiRhs: \_constant: , line:821:30, endln:821:34 |vpiParent: @@ -102896,7 +102896,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:822:20, endln:822:34 |vpiParent: - \_module: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2081:1, endln:2111:10 + \_module_inst: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2081:1, endln:2111:10 |vpiRhs: \_constant: , line:822:30, endln:822:34 |vpiParent: @@ -102931,7 +102931,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:825:29, endln:825:51 |vpiParent: - \_module: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2081:1, endln:2111:10 + \_module_inst: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2081:1, endln:2111:10 |vpiRhs: \_constant: , line:825:48, endln:825:51 |vpiParent: @@ -102964,7 +102964,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:826:29, endln:826:51 |vpiParent: - \_module: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2081:1, endln:2111:10 + \_module_inst: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2081:1, endln:2111:10 |vpiRhs: \_constant: , line:826:48, endln:826:51 |vpiParent: @@ -102997,7 +102997,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:827:29, endln:827:51 |vpiParent: - \_module: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2081:1, endln:2111:10 + \_module_inst: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2081:1, endln:2111:10 |vpiRhs: \_constant: , line:827:48, endln:827:51 |vpiParent: @@ -103030,7 +103030,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:828:29, endln:828:51 |vpiParent: - \_module: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2081:1, endln:2111:10 + \_module_inst: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2081:1, endln:2111:10 |vpiRhs: \_constant: , line:828:48, endln:828:51 |vpiParent: @@ -103063,7 +103063,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:829:29, endln:829:51 |vpiParent: - \_module: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2081:1, endln:2111:10 + \_module_inst: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2081:1, endln:2111:10 |vpiRhs: \_constant: , line:829:48, endln:829:51 |vpiParent: @@ -103096,7 +103096,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:830:29, endln:830:51 |vpiParent: - \_module: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2081:1, endln:2111:10 + \_module_inst: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2081:1, endln:2111:10 |vpiRhs: \_constant: , line:830:48, endln:830:51 |vpiParent: @@ -103129,7 +103129,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:831:29, endln:831:51 |vpiParent: - \_module: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2081:1, endln:2111:10 + \_module_inst: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2081:1, endln:2111:10 |vpiRhs: \_constant: , line:831:48, endln:831:51 |vpiParent: @@ -103162,7 +103162,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:832:29, endln:832:51 |vpiParent: - \_module: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2081:1, endln:2111:10 + \_module_inst: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2081:1, endln:2111:10 |vpiRhs: \_constant: , line:832:48, endln:832:51 |vpiParent: @@ -103195,7 +103195,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:836:20, endln:836:65 |vpiParent: - \_module: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2081:1, endln:2111:10 + \_module_inst: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2081:1, endln:2111:10 |vpiRhs: \_constant: , line:836:33, endln:836:59 |vpiParent: @@ -103230,7 +103230,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:839:16, endln:844:27 |vpiParent: - \_module: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2081:1, endln:2111:10 + \_module_inst: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2081:1, endln:2111:10 |vpiRhs: \_constant: , line:839:26, endln:839:29 |vpiParent: @@ -103259,7 +103259,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:846:20, endln:846:54 |vpiParent: - \_module: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2081:1, endln:2111:10 + \_module_inst: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2081:1, endln:2111:10 |vpiRhs: \_constant: , line:846:26, endln:846:46 |vpiParent: @@ -103294,7 +103294,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:848:20, endln:848:58 |vpiParent: - \_module: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2081:1, endln:2111:10 + \_module_inst: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2081:1, endln:2111:10 |vpiRhs: \_constant: , line:848:33, endln:848:48 |vpiParent: @@ -103329,7 +103329,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:849:20, endln:849:58 |vpiParent: - \_module: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2081:1, endln:2111:10 + \_module_inst: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2081:1, endln:2111:10 |vpiRhs: \_constant: , line:849:33, endln:849:48 |vpiParent: @@ -103364,7 +103364,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:850:20, endln:850:58 |vpiParent: - \_module: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2081:1, endln:2111:10 + \_module_inst: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2081:1, endln:2111:10 |vpiRhs: \_constant: , line:850:33, endln:850:48 |vpiParent: @@ -103399,7 +103399,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:851:20, endln:851:57 |vpiParent: - \_module: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2081:1, endln:2111:10 + \_module_inst: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2081:1, endln:2111:10 |vpiRhs: \_constant: , line:851:33, endln:851:48 |vpiParent: @@ -103434,7 +103434,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:855:30, endln:855:78 |vpiParent: - \_module: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2081:1, endln:2111:10 + \_module_inst: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2081:1, endln:2111:10 |vpiRhs: \_operation: , line:855:47, endln:855:78 |vpiParent: @@ -103529,7 +103529,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:857:30, endln:867:86 |vpiParent: - \_module: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2081:1, endln:2111:10 + \_module_inst: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2081:1, endln:2111:10 |vpiRhs: \_operation: , line:857:41, endln:867:86 |vpiParent: @@ -103896,7 +103896,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:870:16, endln:870:33 |vpiParent: - \_module: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2081:1, endln:2111:10 + \_module_inst: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2081:1, endln:2111:10 |vpiRhs: \_constant: , line:870:32, endln:870:33 |vpiParent: @@ -103925,7 +103925,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:871:16, endln:871:31 |vpiParent: - \_module: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2081:1, endln:2111:10 + \_module_inst: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2081:1, endln:2111:10 |vpiRhs: \_constant: , line:871:30, endln:871:31 |vpiParent: @@ -103954,7 +103954,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:874:31, endln:881:48 |vpiParent: - \_module: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2081:1, endln:2111:10 + \_module_inst: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2081:1, endln:2111:10 |vpiRhs: \_operation: , line:874:47, endln:881:48 |vpiParent: @@ -104076,7 +104076,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:884:20, endln:884:50 |vpiParent: - \_module: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2081:1, endln:2111:10 + \_module_inst: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2081:1, endln:2111:10 |vpiRhs: \_constant: , line:884:46, endln:884:50 |vpiParent: @@ -104111,7 +104111,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:890:22, endln:890:48 |vpiParent: - \_module: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2081:1, endln:2111:10 + \_module_inst: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2081:1, endln:2111:10 |vpiRhs: \_constant: , line:890:44, endln:890:48 |vpiParent: @@ -104144,7 +104144,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:900:20, endln:900:45 |vpiParent: - \_module: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2081:1, endln:2111:10 + \_module_inst: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2081:1, endln:2111:10 |vpiRhs: \_constant: , line:900:41, endln:900:45 |vpiParent: @@ -104179,7 +104179,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:901:20, endln:901:37 |vpiParent: - \_module: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2081:1, endln:2111:10 + \_module_inst: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2081:1, endln:2111:10 |vpiRhs: \_constant: , line:901:33, endln:901:37 |vpiParent: @@ -104214,7 +104214,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:902:20, endln:902:36 |vpiParent: - \_module: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2081:1, endln:2111:10 + \_module_inst: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2081:1, endln:2111:10 |vpiRhs: \_constant: , line:902:32, endln:902:36 |vpiParent: @@ -104249,7 +104249,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:905:29, endln:916:71 |vpiParent: - \_module: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2081:1, endln:2111:10 + \_module_inst: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2081:1, endln:2111:10 |vpiRhs: \_operation: , line:905:54, endln:916:71 |vpiParent: @@ -104755,7 +104755,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:918:29, endln:923:73 |vpiParent: - \_module: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2081:1, endln:2111:10 + \_module_inst: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2081:1, endln:2111:10 |vpiRhs: \_operation: , line:918:55, endln:923:73 |vpiParent: @@ -105022,7 +105022,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:929:29, endln:929:50 |vpiParent: - \_module: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2081:1, endln:2111:10 + \_module_inst: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2081:1, endln:2111:10 |vpiRhs: \_constant: , line:929:49, endln:929:50 |vpiParent: @@ -105055,7 +105055,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:930:29, endln:930:51 |vpiParent: - \_module: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2081:1, endln:2111:10 + \_module_inst: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2081:1, endln:2111:10 |vpiRhs: \_constant: , line:930:49, endln:930:51 |vpiParent: @@ -105088,7 +105088,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:932:29, endln:932:63 |vpiParent: - \_module: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2081:1, endln:2111:10 + \_module_inst: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2081:1, endln:2111:10 |vpiRhs: \_constant: , line:932:47, endln:932:58 |vpiParent: @@ -105121,7 +105121,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:1011:16, endln:1011:40 |vpiParent: - \_module: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2081:1, endln:2111:10 + \_module_inst: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2081:1, endln:2111:10 |vpiRhs: \_constant: , line:1011:35, endln:1011:40 |vpiParent: @@ -105178,7 +105178,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:1013:16, endln:1013:33 |vpiParent: - \_module: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2081:1, endln:2111:10 + \_module_inst: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2081:1, endln:2111:10 |vpiRhs: \_constant: , line:1013:32, endln:1013:33 |vpiParent: @@ -105207,7 +105207,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:1014:16, endln:1014:30 |vpiParent: - \_module: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2081:1, endln:2111:10 + \_module_inst: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2081:1, endln:2111:10 |vpiRhs: \_constant: , line:1014:29, endln:1014:30 |vpiParent: @@ -105236,7 +105236,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:1069:27, endln:1069:55 |vpiParent: - \_module: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2081:1, endln:2111:10 + \_module_inst: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2081:1, endln:2111:10 |vpiRhs: \_constant: , line:1069:48, endln:1069:50 |vpiParent: @@ -105269,7 +105269,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:1070:29, endln:1070:51 |vpiParent: - \_module: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2081:1, endln:2111:10 + \_module_inst: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2081:1, endln:2111:10 |vpiRhs: \_constant: , line:1070:50, endln:1070:51 |vpiParent: @@ -105302,7 +105302,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:1071:29, endln:1071:92 |vpiParent: - \_module: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2081:1, endln:2111:10 + \_module_inst: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2081:1, endln:2111:10 |vpiRhs: \_constant: , line:1071:50, endln:1071:92 |vpiParent: @@ -105335,7 +105335,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:1072:29, endln:1072:80 |vpiParent: - \_module: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2081:1, endln:2111:10 + \_module_inst: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2081:1, endln:2111:10 |vpiRhs: \_constant: , line:1072:50, endln:1072:61 |vpiParent: @@ -105368,7 +105368,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:1073:29, endln:1073:53 |vpiParent: - \_module: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2081:1, endln:2111:10 + \_module_inst: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2081:1, endln:2111:10 |vpiRhs: \_constant: , line:1073:50, endln:1073:53 |vpiParent: @@ -105401,7 +105401,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:1075:27, endln:1075:55 |vpiParent: - \_module: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2081:1, endln:2111:10 + \_module_inst: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2081:1, endln:2111:10 |vpiRhs: \_constant: , line:1075:48, endln:1075:50 |vpiParent: @@ -105434,7 +105434,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:1076:28, endln:1076:50 |vpiParent: - \_module: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2081:1, endln:2111:10 + \_module_inst: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2081:1, endln:2111:10 |vpiRhs: \_constant: , line:1076:49, endln:1076:50 |vpiParent: @@ -105467,7 +105467,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:1077:29, endln:1077:92 |vpiParent: - \_module: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2081:1, endln:2111:10 + \_module_inst: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2081:1, endln:2111:10 |vpiRhs: \_constant: , line:1077:50, endln:1077:92 |vpiParent: @@ -105500,7 +105500,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:1078:29, endln:1078:80 |vpiParent: - \_module: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2081:1, endln:2111:10 + \_module_inst: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2081:1, endln:2111:10 |vpiRhs: \_constant: , line:1078:50, endln:1078:61 |vpiParent: @@ -105533,7 +105533,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:1079:29, endln:1079:53 |vpiParent: - \_module: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2081:1, endln:2111:10 + \_module_inst: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2081:1, endln:2111:10 |vpiRhs: \_constant: , line:1079:50, endln:1079:53 |vpiParent: @@ -105566,7 +105566,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:1293:16, endln:1293:32 |vpiParent: - \_module: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2081:1, endln:2111:10 + \_module_inst: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2081:1, endln:2111:10 |vpiRhs: \_constant: , line:1293:30, endln:1293:32 |vpiParent: @@ -105595,7 +105595,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:2082:28, endln:2082:42 |vpiParent: - \_module: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2081:1, endln:2111:10 + \_module_inst: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2081:1, endln:2111:10 |vpiRhs: \_constant: , line:2082:41, endln:2082:42 |vpiDecompile:1 @@ -105609,7 +105609,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:2083:40, endln:2083:83 |vpiParent: - \_module: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2081:1, endln:2111:10 + \_module_inst: work@ex_stage (work@ex_stage), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2081:1, endln:2111:10 |vpiRhs: \_operation: , line:2083:52, endln:2083:64 |vpiOpType:75 @@ -105977,14 +105977,14 @@ design: (work@top) |vpiTaskFunc: \_function: (ariane_pkg::extract_transfer_size), line:1458:5, endln:1482:16 |uhdmallModules: -\_module: work@fpnew_opgroup_block (work@fpnew_opgroup_block), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:1958:1, endln:2002:10 +\_module_inst: work@fpnew_opgroup_block (work@fpnew_opgroup_block), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:1958:1, endln:2002:10 |vpiParent: \_design: (work@top) |vpiFullName:work@fpnew_opgroup_block |vpiParameter: \_parameter: (work@fpnew_opgroup_block.OpGroup), line:1959:41, endln:1959:48 |vpiParent: - \_module: work@fpnew_opgroup_block (work@fpnew_opgroup_block), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:1958:1, endln:2002:10 + \_module_inst: work@fpnew_opgroup_block (work@fpnew_opgroup_block), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:1958:1, endln:2002:10 |INT:0 |vpiTypespec: \_enum_typespec: (fpnew_pkg::opgroup_e), line:1574:3, endln:1576:15 @@ -105993,7 +105993,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@fpnew_opgroup_block.Width), line:1961:41, endln:1961:46 |vpiParent: - \_module: work@fpnew_opgroup_block (work@fpnew_opgroup_block), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:1958:1, endln:2002:10 + \_module_inst: work@fpnew_opgroup_block (work@fpnew_opgroup_block), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:1958:1, endln:2002:10 |UINT:32 |vpiTypespec: \_int_typespec: , line:1961:13, endln:1961:25 @@ -106004,7 +106004,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@fpnew_opgroup_block.EnableVectors), line:1962:41, endln:1962:54 |vpiParent: - \_module: work@fpnew_opgroup_block (work@fpnew_opgroup_block), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:1958:1, endln:2002:10 + \_module_inst: work@fpnew_opgroup_block (work@fpnew_opgroup_block), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:1958:1, endln:2002:10 |BIN:1 |vpiTypespec: \_logic_typespec: , line:1962:13, endln:1962:18 @@ -106015,7 +106015,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@fpnew_opgroup_block.FpFmtMask), line:1963:41, endln:1963:50 |vpiParent: - \_module: work@fpnew_opgroup_block (work@fpnew_opgroup_block), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:1958:1, endln:2002:10 + \_module_inst: work@fpnew_opgroup_block (work@fpnew_opgroup_block), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:1958:1, endln:2002:10 |BIN:1 |vpiTypespec: \_logic_typespec: (fpnew_pkg::fmt_logic_t), line:1528:11, endln:1528:37 @@ -106024,7 +106024,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@fpnew_opgroup_block.IntFmtMask), line:1964:41, endln:1964:51 |vpiParent: - \_module: work@fpnew_opgroup_block (work@fpnew_opgroup_block), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:1958:1, endln:2002:10 + \_module_inst: work@fpnew_opgroup_block (work@fpnew_opgroup_block), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:1958:1, endln:2002:10 |BIN:1 |vpiTypespec: \_logic_typespec: (fpnew_pkg::ifmt_logic_t), line:1566:11, endln:1566:38 @@ -106033,7 +106033,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@fpnew_opgroup_block.FmtPipeRegs), line:1965:41, endln:1965:52 |vpiParent: - \_module: work@fpnew_opgroup_block (work@fpnew_opgroup_block), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:1958:1, endln:2002:10 + \_module_inst: work@fpnew_opgroup_block (work@fpnew_opgroup_block), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:1958:1, endln:2002:10 |vpiTypespec: \_logic_typespec: (fpnew_pkg::fmt_unsigned_t), line:1529:11, endln:1529:43 |vpiName:FmtPipeRegs @@ -106041,7 +106041,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@fpnew_opgroup_block.FmtUnitTypes), line:1966:41, endln:1966:53 |vpiParent: - \_module: work@fpnew_opgroup_block (work@fpnew_opgroup_block), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:1958:1, endln:2002:10 + \_module_inst: work@fpnew_opgroup_block (work@fpnew_opgroup_block), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:1958:1, endln:2002:10 |vpiTypespec: \_packed_array_typespec: (fpnew_pkg::fmt_unit_types_t), line:1654:11, endln:1654:22 |vpiName:FmtUnitTypes @@ -106049,7 +106049,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@fpnew_opgroup_block.PipeConfig), line:1967:41, endln:1967:51 |vpiParent: - \_module: work@fpnew_opgroup_block (work@fpnew_opgroup_block), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:1958:1, endln:2002:10 + \_module_inst: work@fpnew_opgroup_block (work@fpnew_opgroup_block), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:1958:1, endln:2002:10 |INT:0 |vpiTypespec: \_enum_typespec: (fpnew_pkg::pipe_config_t), line:1639:3, endln:1644:19 @@ -106058,7 +106058,7 @@ design: (work@top) |vpiParameter: \_type_parameter: (work@fpnew_opgroup_block.TagType), line:1968:41, endln:1968:48 |vpiParent: - \_module: work@fpnew_opgroup_block (work@fpnew_opgroup_block), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:1958:1, endln:2002:10 + \_module_inst: work@fpnew_opgroup_block (work@fpnew_opgroup_block), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:1958:1, endln:2002:10 |vpiName:TagType |vpiFullName:work@fpnew_opgroup_block.TagType |vpiTypespec: @@ -106068,7 +106068,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@fpnew_opgroup_block.NUM_FORMATS), line:1970:27, endln:1970:38 |vpiParent: - \_module: work@fpnew_opgroup_block (work@fpnew_opgroup_block), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:1958:1, endln:2002:10 + \_module_inst: work@fpnew_opgroup_block (work@fpnew_opgroup_block), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:1958:1, endln:2002:10 |UINT:5 |vpiTypespec: \_int_typespec: , line:1970:14, endln:1970:26 @@ -106080,7 +106080,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@fpnew_opgroup_block.NUM_OPERANDS), line:1971:27, endln:1971:39 |vpiParent: - \_module: work@fpnew_opgroup_block (work@fpnew_opgroup_block), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:1958:1, endln:2002:10 + \_module_inst: work@fpnew_opgroup_block (work@fpnew_opgroup_block), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:1958:1, endln:2002:10 |vpiTypespec: \_int_typespec: , line:1971:14, endln:1971:26 |vpiLocalParam:1 @@ -106089,7 +106089,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:1959:41, endln:1959:74 |vpiParent: - \_module: work@fpnew_opgroup_block (work@fpnew_opgroup_block), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:1958:1, endln:2002:10 + \_module_inst: work@fpnew_opgroup_block (work@fpnew_opgroup_block), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:1958:1, endln:2002:10 |vpiRhs: \_constant: , line:1959:57, endln:1959:68 |vpiDecompile:0 @@ -106103,7 +106103,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:1961:41, endln:1961:59 |vpiParent: - \_module: work@fpnew_opgroup_block (work@fpnew_opgroup_block), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:1958:1, endln:2002:10 + \_module_inst: work@fpnew_opgroup_block (work@fpnew_opgroup_block), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:1958:1, endln:2002:10 |vpiRhs: \_constant: , line:1961:57, endln:1961:59 |vpiDecompile:32 @@ -106117,7 +106117,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:1962:41, endln:1962:61 |vpiParent: - \_module: work@fpnew_opgroup_block (work@fpnew_opgroup_block), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:1958:1, endln:2002:10 + \_module_inst: work@fpnew_opgroup_block (work@fpnew_opgroup_block), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:1958:1, endln:2002:10 |vpiRhs: \_constant: , line:1962:57, endln:1962:61 |vpiDecompile:1'b1 @@ -106131,7 +106131,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:1963:41, endln:1963:59 |vpiParent: - \_module: work@fpnew_opgroup_block (work@fpnew_opgroup_block), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:1958:1, endln:2002:10 + \_module_inst: work@fpnew_opgroup_block (work@fpnew_opgroup_block), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:1958:1, endln:2002:10 |vpiRhs: \_constant: , line:1963:57, endln:1963:59 |vpiDecompile:'1 @@ -106145,7 +106145,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:1964:41, endln:1964:59 |vpiParent: - \_module: work@fpnew_opgroup_block (work@fpnew_opgroup_block), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:1958:1, endln:2002:10 + \_module_inst: work@fpnew_opgroup_block (work@fpnew_opgroup_block), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:1958:1, endln:2002:10 |vpiRhs: \_constant: , line:1964:57, endln:1964:59 |vpiDecompile:'1 @@ -106159,7 +106159,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:1965:41, endln:1965:70 |vpiParent: - \_module: work@fpnew_opgroup_block (work@fpnew_opgroup_block), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:1958:1, endln:2002:10 + \_module_inst: work@fpnew_opgroup_block (work@fpnew_opgroup_block), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:1958:1, endln:2002:10 |vpiRhs: \_operation: , line:1965:57, endln:1965:70 |vpiOpType:75 @@ -106179,7 +106179,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:1966:41, endln:1966:88 |vpiParent: - \_module: work@fpnew_opgroup_block (work@fpnew_opgroup_block), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:1958:1, endln:2002:10 + \_module_inst: work@fpnew_opgroup_block (work@fpnew_opgroup_block), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:1958:1, endln:2002:10 |vpiRhs: \_operation: , line:1966:57, endln:1966:88 |vpiOpType:75 @@ -106199,7 +106199,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:1967:41, endln:1967:74 |vpiParent: - \_module: work@fpnew_opgroup_block (work@fpnew_opgroup_block), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:1958:1, endln:2002:10 + \_module_inst: work@fpnew_opgroup_block (work@fpnew_opgroup_block), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:1958:1, endln:2002:10 |vpiRhs: \_constant: , line:1967:57, endln:1967:68 |vpiDecompile:0 @@ -106213,7 +106213,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:1970:27, endln:1970:67 |vpiParent: - \_module: work@fpnew_opgroup_block (work@fpnew_opgroup_block), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:1958:1, endln:2002:10 + \_module_inst: work@fpnew_opgroup_block (work@fpnew_opgroup_block), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:1958:1, endln:2002:10 |vpiRhs: \_constant: , line:1970:42, endln:1970:53 |vpiDecompile:5 @@ -106227,7 +106227,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:1971:27, endln:1971:74 |vpiParent: - \_module: work@fpnew_opgroup_block (work@fpnew_opgroup_block), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:1958:1, endln:2002:10 + \_module_inst: work@fpnew_opgroup_block (work@fpnew_opgroup_block), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:1958:1, endln:2002:10 |vpiRhs: \_func_call: (fpnew_pkg::num_operands), line:1971:42, endln:1971:53 |vpiArgument: @@ -106242,14 +106242,14 @@ design: (work@top) \_parameter: (work@fpnew_opgroup_block.NUM_OPERANDS), line:1971:27, endln:1971:39 |vpiDefName:work@fpnew_opgroup_block |uhdmallModules: -\_module: work@fpnew_top (work@fpnew_top), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2006:1, endln:2039:10 +\_module_inst: work@fpnew_top (work@fpnew_top), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2006:1, endln:2039:10 |vpiParent: \_design: (work@top) |vpiFullName:work@fpnew_top |vpiParameter: \_parameter: (work@fpnew_top.Features), line:2008:45, endln:2008:53 |vpiParent: - \_module: work@fpnew_top (work@fpnew_top), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2006:1, endln:2039:10 + \_module_inst: work@fpnew_top (work@fpnew_top), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2006:1, endln:2039:10 |vpiTypespec: \_struct_typespec: (fpnew_pkg::fpu_features_t), line:1662:11, endln:1662:17 |vpiName:Features @@ -106257,7 +106257,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@fpnew_top.Implementation), line:2009:45, endln:2009:59 |vpiParent: - \_module: work@fpnew_top (work@fpnew_top), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2006:1, endln:2039:10 + \_module_inst: work@fpnew_top (work@fpnew_top), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2006:1, endln:2039:10 |vpiTypespec: \_struct_typespec: (fpnew_pkg::fpu_implementation_t), line:1720:11, endln:1720:17 |vpiName:Implementation @@ -106265,7 +106265,7 @@ design: (work@top) |vpiParameter: \_type_parameter: (work@fpnew_top.TagType), line:2010:45, endln:2010:52 |vpiParent: - \_module: work@fpnew_top (work@fpnew_top), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2006:1, endln:2039:10 + \_module_inst: work@fpnew_top (work@fpnew_top), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2006:1, endln:2039:10 |vpiName:TagType |vpiFullName:work@fpnew_top.TagType |vpiTypespec: @@ -106275,7 +106275,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@fpnew_top.WIDTH), line:2012:27, endln:2012:32 |vpiParent: - \_module: work@fpnew_top (work@fpnew_top), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2006:1, endln:2039:10 + \_module_inst: work@fpnew_top (work@fpnew_top), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2006:1, endln:2039:10 |vpiTypespec: \_int_typespec: , line:2012:14, endln:2012:26 |vpiParent: @@ -106286,7 +106286,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@fpnew_top.NUM_OPERANDS), line:2013:27, endln:2013:39 |vpiParent: - \_module: work@fpnew_top (work@fpnew_top), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2006:1, endln:2039:10 + \_module_inst: work@fpnew_top (work@fpnew_top), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2006:1, endln:2039:10 |UINT:3 |vpiTypespec: \_int_typespec: , line:2013:14, endln:2013:26 @@ -106298,7 +106298,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@fpnew_top.NUM_OPGROUPS), line:2016:27, endln:2016:39 |vpiParent: - \_module: work@fpnew_top (work@fpnew_top), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2006:1, endln:2039:10 + \_module_inst: work@fpnew_top (work@fpnew_top), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2006:1, endln:2039:10 |UINT:4 |vpiTypespec: \_int_typespec: , line:2016:14, endln:2016:26 @@ -106310,7 +106310,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@fpnew_top.NUM_FORMATS), line:2017:27, endln:2017:38 |vpiParent: - \_module: work@fpnew_top (work@fpnew_top), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2006:1, endln:2039:10 + \_module_inst: work@fpnew_top (work@fpnew_top), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2006:1, endln:2039:10 |UINT:5 |vpiTypespec: \_int_typespec: , line:2017:14, endln:2017:26 @@ -106322,7 +106322,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:2008:45, endln:2008:84 |vpiParent: - \_module: work@fpnew_top (work@fpnew_top), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2006:1, endln:2039:10 + \_module_inst: work@fpnew_top (work@fpnew_top), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2006:1, endln:2039:10 |vpiRhs: \_operation: , line:2008:62, endln:2008:73 |vpiOpType:75 @@ -106416,7 +106416,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:2009:45, endln:2009:87 |vpiParent: - \_module: work@fpnew_top (work@fpnew_top), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2006:1, endln:2039:10 + \_module_inst: work@fpnew_top (work@fpnew_top), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2006:1, endln:2039:10 |vpiRhs: \_operation: , line:2009:62, endln:2009:73 |vpiOpType:75 @@ -106575,7 +106575,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:2012:27, endln:2012:56 |vpiParent: - \_module: work@fpnew_top (work@fpnew_top), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2006:1, endln:2039:10 + \_module_inst: work@fpnew_top (work@fpnew_top), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2006:1, endln:2039:10 |vpiRhs: \_hier_path: (Features.Width), line:2012:42, endln:2012:56 |vpiName:Features.Width @@ -106592,7 +106592,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:2013:27, endln:2013:43 |vpiParent: - \_module: work@fpnew_top (work@fpnew_top), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2006:1, endln:2039:10 + \_module_inst: work@fpnew_top (work@fpnew_top), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2006:1, endln:2039:10 |vpiRhs: \_constant: , line:2013:42, endln:2013:43 |vpiDecompile:3 @@ -106606,7 +106606,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:2016:27, endln:2016:65 |vpiParent: - \_module: work@fpnew_top (work@fpnew_top), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2006:1, endln:2039:10 + \_module_inst: work@fpnew_top (work@fpnew_top), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2006:1, endln:2039:10 |vpiRhs: \_constant: , line:2016:42, endln:2016:53 |vpiDecompile:4 @@ -106620,7 +106620,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:2017:27, endln:2017:67 |vpiParent: - \_module: work@fpnew_top (work@fpnew_top), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2006:1, endln:2039:10 + \_module_inst: work@fpnew_top (work@fpnew_top), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2006:1, endln:2039:10 |vpiRhs: \_constant: , line:2017:42, endln:2017:53 |vpiDecompile:5 @@ -106633,14 +106633,14 @@ design: (work@top) \_parameter: (work@fpnew_top.NUM_FORMATS), line:2017:27, endln:2017:38 |vpiDefName:work@fpnew_top |uhdmallModules: -\_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 +\_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 |vpiParent: \_design: (work@top) |vpiFullName:work@fpu_wrap |vpiParameter: \_parameter: (work@fpu_wrap.ARIANE_MARCHID), line:855:30, endln:855:44 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 |vpiTypespec: \_logic_typespec: (xlen_t), line:30:13, endln:30:29 |vpiParent: @@ -106675,7 +106675,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@fpu_wrap.ASID_WIDTH), line:782:16, endln:782:26 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 |INT:16 |vpiTypespec: \_int_typespec: @@ -106688,7 +106688,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@fpu_wrap.ArianeDefaultConfig), line:706:29, endln:706:48 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 |vpiTypespec: \_struct_typespec: (ariane_pkg::ariane_cfg_t), line:684:13, endln:684:19 |vpiParent: @@ -107225,7 +107225,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@fpu_wrap.BITS_SATURATION_COUNTER), line:783:16, endln:783:39 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 |UINT:2 |vpiTypespec: \_int_typespec: @@ -107238,7 +107238,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@fpu_wrap.CONFIG_L1D_SIZE), line:1075:27, endln:1075:42 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 |INT:32768 |vpiTypespec: \_int_typespec: , line:1075:14, endln:1075:26 @@ -107253,7 +107253,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@fpu_wrap.CONFIG_L1I_SIZE), line:1069:27, endln:1069:42 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 |INT:16384 |vpiTypespec: \_int_typespec: , line:1069:14, endln:1069:26 @@ -107268,7 +107268,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@fpu_wrap.DCACHE_INDEX_WIDTH), line:1077:29, endln:1077:47 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 |UINT:12 |vpiTypespec: \_int_typespec: , line:1077:16, endln:1077:28 @@ -107283,7 +107283,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@fpu_wrap.DCACHE_LINE_WIDTH), line:1079:29, endln:1079:46 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 |UINT:128 |vpiTypespec: \_int_typespec: , line:1079:16, endln:1079:28 @@ -107298,7 +107298,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@fpu_wrap.DCACHE_SET_ASSOC), line:1076:28, endln:1076:44 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 |UINT:8 |vpiTypespec: \_int_typespec: , line:1076:15, endln:1076:27 @@ -107313,7 +107313,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@fpu_wrap.DCACHE_TAG_WIDTH), line:1078:29, endln:1078:45 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 |INT:44 |vpiTypespec: \_int_typespec: , line:1078:16, endln:1078:28 @@ -107328,7 +107328,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@fpu_wrap.DEPTH_COMMIT), line:804:29, endln:804:41 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 |UINT:8 |vpiTypespec: \_int_typespec: , line:804:16, endln:804:28 @@ -107343,7 +107343,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@fpu_wrap.DEPTH_SPEC), line:795:29, endln:795:39 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 |UINT:4 |vpiTypespec: \_int_typespec: , line:795:16, endln:795:28 @@ -107358,7 +107358,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@fpu_wrap.DebugHartInfo), line:874:31, endln:874:44 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 |vpiTypespec: \_unsupported_typespec: (dm::hartinfo_t), line:874:16, endln:874:20 |vpiParent: @@ -107373,7 +107373,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@fpu_wrap.ENABLE_CYCLE_COUNT), line:900:20, endln:900:38 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 |BIN:1 |vpiTypespec: \_bit_typespec: , line:900:16, endln:900:19 @@ -107389,7 +107389,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@fpu_wrap.ENABLE_RENAME), line:786:16, endln:786:29 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 |BIN:0 |vpiTypespec: \_int_typespec: @@ -107416,7 +107416,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@fpu_wrap.ENABLE_SPIKE_COMMIT_LOG), line:884:20, endln:884:43 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 |BIN:1 |vpiTypespec: \_bit_typespec: , line:884:16, endln:884:19 @@ -107432,7 +107432,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@fpu_wrap.ENABLE_WFI), line:901:20, endln:901:30 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 |BIN:1 |vpiTypespec: \_bit_typespec: , line:901:16, endln:901:19 @@ -107448,7 +107448,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@fpu_wrap.EXC_OFF_RST), line:1011:16, endln:1011:27 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 |HEX:80 |vpiTypespec: \_int_typespec: @@ -107475,7 +107475,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@fpu_wrap.FETCH_FIFO_DEPTH), line:929:29, endln:929:45 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 |UINT:4 |vpiTypespec: \_int_typespec: , line:929:16, endln:929:28 @@ -107490,7 +107490,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@fpu_wrap.FETCH_WIDTH), line:930:29, endln:930:40 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 |UINT:32 |vpiTypespec: \_int_typespec: , line:930:16, endln:930:28 @@ -107505,7 +107505,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@fpu_wrap.FLEN), line:839:16, endln:839:20 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 |INT:64 |vpiTypespec: \_int_typespec: @@ -107518,7 +107518,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@fpu_wrap.FP_PRESENT), line:836:20, endln:836:30 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 |UINT:1 |vpiTypespec: \_bit_typespec: , line:836:16, endln:836:19 @@ -107534,7 +107534,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@fpu_wrap.ICACHE_INDEX_WIDTH), line:1071:29, endln:1071:47 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 |UINT:12 |vpiTypespec: \_int_typespec: , line:1071:16, endln:1071:28 @@ -107549,7 +107549,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@fpu_wrap.ICACHE_LINE_WIDTH), line:1073:29, endln:1073:46 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 |UINT:128 |vpiTypespec: \_int_typespec: , line:1073:16, endln:1073:28 @@ -107564,7 +107564,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@fpu_wrap.ICACHE_SET_ASSOC), line:1070:29, endln:1070:45 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 |UINT:4 |vpiTypespec: \_int_typespec: , line:1070:16, endln:1070:28 @@ -107579,7 +107579,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@fpu_wrap.ICACHE_TAG_WIDTH), line:1072:29, endln:1072:45 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 |INT:44 |vpiTypespec: \_int_typespec: , line:1072:16, endln:1072:28 @@ -107594,7 +107594,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@fpu_wrap.INSTR_PER_FETCH), line:932:29, endln:932:44 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 |INT:2 |vpiTypespec: \_int_typespec: , line:932:16, endln:932:28 @@ -107609,7 +107609,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@fpu_wrap.INVALIDATE_ON_FLUSH), line:890:22, endln:890:41 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 |BIN:1 |vpiTypespec: \_logic_typespec: , line:890:16, endln:890:21 @@ -107624,7 +107624,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@fpu_wrap.ISA_CODE), line:857:30, endln:857:38 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 |vpiTypespec: \_logic_typespec: (xlen_t), line:30:13, endln:30:29 |vpiParent: @@ -107659,7 +107659,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@fpu_wrap.ISSUE_WIDTH), line:788:16, endln:788:27 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 |UINT:1 |vpiTypespec: \_int_typespec: @@ -107672,7 +107672,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@fpu_wrap.LAT_COMP_FP16), line:827:29, endln:827:42 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 |DEC:1 |vpiTypespec: \_int_typespec: , line:827:16, endln:827:28 @@ -107687,7 +107687,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@fpu_wrap.LAT_COMP_FP16ALT), line:828:29, endln:828:45 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 |DEC:1 |vpiTypespec: \_int_typespec: , line:828:16, endln:828:28 @@ -107702,7 +107702,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@fpu_wrap.LAT_COMP_FP32), line:825:29, endln:825:42 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 |DEC:2 |vpiTypespec: \_int_typespec: , line:825:16, endln:825:28 @@ -107717,7 +107717,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@fpu_wrap.LAT_COMP_FP64), line:826:29, endln:826:42 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 |DEC:3 |vpiTypespec: \_int_typespec: , line:826:16, endln:826:28 @@ -107732,7 +107732,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@fpu_wrap.LAT_COMP_FP8), line:829:29, endln:829:41 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 |DEC:1 |vpiTypespec: \_int_typespec: , line:829:16, endln:829:28 @@ -107747,7 +107747,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@fpu_wrap.LAT_CONV), line:832:29, endln:832:37 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 |DEC:2 |vpiTypespec: \_int_typespec: , line:832:16, endln:832:28 @@ -107762,7 +107762,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@fpu_wrap.LAT_DIVSQRT), line:830:29, endln:830:40 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 |DEC:2 |vpiTypespec: \_int_typespec: , line:830:16, endln:830:28 @@ -107777,7 +107777,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@fpu_wrap.LAT_NONCOMP), line:831:29, endln:831:40 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 |DEC:1 |vpiTypespec: \_int_typespec: , line:831:16, endln:831:28 @@ -107792,7 +107792,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@fpu_wrap.MachineIrq), line:1014:16, endln:1014:26 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 |UINT:0 |vpiTypespec: \_int_typespec: @@ -107805,7 +107805,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@fpu_wrap.NR_COMMIT_PORTS), line:784:16, endln:784:31 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 |UINT:2 |vpiTypespec: \_int_typespec: @@ -107818,7 +107818,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@fpu_wrap.NR_LOAD_PIPE_REGS), line:791:29, endln:791:46 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 |UINT:1 |vpiTypespec: \_int_typespec: , line:791:16, endln:791:28 @@ -107833,7 +107833,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@fpu_wrap.NR_SB_ENTRIES), line:779:16, endln:779:29 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 |UINT:8 |vpiTypespec: \_int_typespec: @@ -107846,7 +107846,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@fpu_wrap.NR_STORE_PIPE_REGS), line:792:29, endln:792:47 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 |UINT:0 |vpiTypespec: \_int_typespec: , line:792:16, endln:792:28 @@ -107861,7 +107861,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@fpu_wrap.NR_WB_PORTS), line:871:16, endln:871:27 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 |UINT:4 |vpiTypespec: \_int_typespec: @@ -107874,7 +107874,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@fpu_wrap.NSX), line:846:20, endln:846:23 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 |UINT:0 |vpiTypespec: \_bit_typespec: , line:846:16, endln:846:19 @@ -107890,7 +107890,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@fpu_wrap.NrMaxRules), line:682:16, endln:682:26 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 |UINT:16 |vpiTypespec: \_int_typespec: @@ -107903,7 +107903,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@fpu_wrap.PPN4K_WIDTH), line:1293:16, endln:1293:27 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 |UINT:38 |vpiTypespec: \_int_typespec: @@ -107916,7 +107916,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@fpu_wrap.REG_ADDR_SIZE), line:870:16, endln:870:29 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 |UINT:6 |vpiTypespec: \_int_typespec: @@ -107929,7 +107929,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@fpu_wrap.RVA), line:816:20, endln:816:23 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 |BIN:1 |vpiTypespec: \_bit_typespec: , line:816:16, endln:816:19 @@ -107945,7 +107945,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@fpu_wrap.RVD), line:814:20, endln:814:23 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 |INT:1 |vpiTypespec: \_bit_typespec: , line:814:16, endln:814:19 @@ -107961,7 +107961,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@fpu_wrap.RVF), line:813:20, endln:813:23 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 |INT:1 |vpiTypespec: \_bit_typespec: , line:813:16, endln:813:19 @@ -107977,7 +107977,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@fpu_wrap.RVFVEC), line:848:20, endln:848:26 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 |UINT:0 |vpiTypespec: \_bit_typespec: , line:848:16, endln:848:19 @@ -107993,7 +107993,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@fpu_wrap.SMODE_STATUS_READ_MASK), line:905:29, endln:905:51 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 |vpiTypespec: \_logic_typespec: , line:905:16, endln:905:28 |vpiParent: @@ -108027,7 +108027,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@fpu_wrap.SMODE_STATUS_WRITE_MASK), line:918:29, endln:918:52 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 |vpiTypespec: \_logic_typespec: , line:918:16, endln:918:28 |vpiParent: @@ -108061,7 +108061,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@fpu_wrap.SupervisorIrq), line:1013:16, endln:1013:29 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 |UINT:1 |vpiTypespec: \_int_typespec: @@ -108074,7 +108074,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@fpu_wrap.TRANS_ID_BITS), line:780:16, endln:780:29 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 |UINT:3 |vpiTypespec: \_int_typespec: @@ -108087,7 +108087,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@fpu_wrap.XF16), line:819:20, endln:819:24 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 |BIN:0 |vpiTypespec: \_bit_typespec: , line:819:16, endln:819:19 @@ -108103,7 +108103,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@fpu_wrap.XF16ALT), line:820:20, endln:820:27 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 |BIN:0 |vpiTypespec: \_bit_typespec: , line:820:16, endln:820:19 @@ -108119,7 +108119,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@fpu_wrap.XF16ALTVEC), line:850:20, endln:850:30 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 |UINT:0 |vpiTypespec: \_bit_typespec: , line:850:16, endln:850:19 @@ -108135,7 +108135,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@fpu_wrap.XF16VEC), line:849:20, endln:849:27 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 |UINT:0 |vpiTypespec: \_bit_typespec: , line:849:16, endln:849:19 @@ -108151,7 +108151,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@fpu_wrap.XF8), line:821:20, endln:821:23 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 |BIN:0 |vpiTypespec: \_bit_typespec: , line:821:16, endln:821:19 @@ -108167,7 +108167,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@fpu_wrap.XF8VEC), line:851:20, endln:851:26 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 |UINT:0 |vpiTypespec: \_bit_typespec: , line:851:16, endln:851:19 @@ -108183,7 +108183,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@fpu_wrap.XFVEC), line:822:20, endln:822:25 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 |BIN:0 |vpiTypespec: \_bit_typespec: , line:822:16, endln:822:19 @@ -108199,7 +108199,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@fpu_wrap.ZERO_TVAL), line:902:20, endln:902:29 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 |BIN:0 |vpiTypespec: \_bit_typespec: , line:902:16, endln:902:19 @@ -108215,7 +108215,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:682:16, endln:682:31 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 |vpiRhs: \_constant: , line:682:29, endln:682:31 |vpiParent: @@ -108244,7 +108244,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:706:29, endln:728:6 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 |vpiRhs: \_operation: , line:706:51, endln:728:6 |vpiParent: @@ -109056,7 +109056,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:779:16, endln:779:33 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 |vpiRhs: \_constant: , line:779:32, endln:779:33 |vpiParent: @@ -109085,7 +109085,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:780:16, endln:780:53 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 |vpiRhs: \_constant: , line:780:32, endln:780:53 |vpiParent: @@ -109114,7 +109114,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:782:16, endln:782:60 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 |vpiRhs: \_constant: , line:782:32, endln:782:51 |vpiParent: @@ -109143,7 +109143,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:783:16, endln:783:43 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 |vpiRhs: \_constant: , line:783:42, endln:783:43 |vpiParent: @@ -109172,7 +109172,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:784:16, endln:784:35 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 |vpiRhs: \_constant: , line:784:34, endln:784:35 |vpiParent: @@ -109201,7 +109201,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:786:16, endln:786:36 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 |vpiRhs: \_constant: , line:786:32, endln:786:36 |vpiParent: @@ -109258,7 +109258,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:788:16, endln:788:31 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 |vpiRhs: \_constant: , line:788:30, endln:788:31 |vpiParent: @@ -109287,7 +109287,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:791:29, endln:791:50 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 |vpiRhs: \_constant: , line:791:49, endln:791:50 |vpiParent: @@ -109320,7 +109320,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:792:29, endln:792:51 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 |vpiRhs: \_constant: , line:792:50, endln:792:51 |vpiParent: @@ -109353,7 +109353,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:795:29, endln:795:45 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 |vpiRhs: \_constant: , line:795:44, endln:795:45 |vpiParent: @@ -109386,7 +109386,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:804:29, endln:804:45 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 |vpiRhs: \_constant: , line:804:44, endln:804:45 |vpiParent: @@ -109419,7 +109419,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:813:20, endln:813:42 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 |vpiRhs: \_constant: , line:813:26, endln:813:33 |vpiParent: @@ -109454,7 +109454,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:814:20, endln:814:42 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 |vpiRhs: \_constant: , line:814:26, endln:814:33 |vpiParent: @@ -109489,7 +109489,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:816:20, endln:816:30 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 |vpiRhs: \_constant: , line:816:26, endln:816:30 |vpiParent: @@ -109524,7 +109524,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:819:20, endln:819:34 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 |vpiRhs: \_constant: , line:819:30, endln:819:34 |vpiParent: @@ -109559,7 +109559,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:820:20, endln:820:34 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 |vpiRhs: \_constant: , line:820:30, endln:820:34 |vpiParent: @@ -109594,7 +109594,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:821:20, endln:821:34 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 |vpiRhs: \_constant: , line:821:30, endln:821:34 |vpiParent: @@ -109629,7 +109629,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:822:20, endln:822:34 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 |vpiRhs: \_constant: , line:822:30, endln:822:34 |vpiParent: @@ -109664,7 +109664,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:825:29, endln:825:51 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 |vpiRhs: \_constant: , line:825:48, endln:825:51 |vpiParent: @@ -109697,7 +109697,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:826:29, endln:826:51 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 |vpiRhs: \_constant: , line:826:48, endln:826:51 |vpiParent: @@ -109730,7 +109730,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:827:29, endln:827:51 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 |vpiRhs: \_constant: , line:827:48, endln:827:51 |vpiParent: @@ -109763,7 +109763,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:828:29, endln:828:51 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 |vpiRhs: \_constant: , line:828:48, endln:828:51 |vpiParent: @@ -109796,7 +109796,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:829:29, endln:829:51 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 |vpiRhs: \_constant: , line:829:48, endln:829:51 |vpiParent: @@ -109829,7 +109829,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:830:29, endln:830:51 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 |vpiRhs: \_constant: , line:830:48, endln:830:51 |vpiParent: @@ -109862,7 +109862,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:831:29, endln:831:51 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 |vpiRhs: \_constant: , line:831:48, endln:831:51 |vpiParent: @@ -109895,7 +109895,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:832:29, endln:832:51 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 |vpiRhs: \_constant: , line:832:48, endln:832:51 |vpiParent: @@ -109928,7 +109928,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:836:20, endln:836:65 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 |vpiRhs: \_constant: , line:836:33, endln:836:59 |vpiParent: @@ -109963,7 +109963,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:839:16, endln:844:27 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 |vpiRhs: \_constant: , line:839:26, endln:839:29 |vpiParent: @@ -109992,7 +109992,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:846:20, endln:846:54 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 |vpiRhs: \_constant: , line:846:26, endln:846:46 |vpiParent: @@ -110027,7 +110027,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:848:20, endln:848:58 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 |vpiRhs: \_constant: , line:848:33, endln:848:48 |vpiParent: @@ -110062,7 +110062,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:849:20, endln:849:58 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 |vpiRhs: \_constant: , line:849:33, endln:849:48 |vpiParent: @@ -110097,7 +110097,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:850:20, endln:850:58 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 |vpiRhs: \_constant: , line:850:33, endln:850:48 |vpiParent: @@ -110132,7 +110132,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:851:20, endln:851:57 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 |vpiRhs: \_constant: , line:851:33, endln:851:48 |vpiParent: @@ -110167,7 +110167,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:855:30, endln:855:78 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 |vpiRhs: \_operation: , line:855:47, endln:855:78 |vpiParent: @@ -110262,7 +110262,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:857:30, endln:867:86 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 |vpiRhs: \_operation: , line:857:41, endln:867:86 |vpiParent: @@ -110629,7 +110629,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:870:16, endln:870:33 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 |vpiRhs: \_constant: , line:870:32, endln:870:33 |vpiParent: @@ -110658,7 +110658,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:871:16, endln:871:31 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 |vpiRhs: \_constant: , line:871:30, endln:871:31 |vpiParent: @@ -110687,7 +110687,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:874:31, endln:881:48 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 |vpiRhs: \_operation: , line:874:47, endln:881:48 |vpiParent: @@ -110809,7 +110809,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:884:20, endln:884:50 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 |vpiRhs: \_constant: , line:884:46, endln:884:50 |vpiParent: @@ -110844,7 +110844,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:890:22, endln:890:48 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 |vpiRhs: \_constant: , line:890:44, endln:890:48 |vpiParent: @@ -110877,7 +110877,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:900:20, endln:900:45 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 |vpiRhs: \_constant: , line:900:41, endln:900:45 |vpiParent: @@ -110912,7 +110912,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:901:20, endln:901:37 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 |vpiRhs: \_constant: , line:901:33, endln:901:37 |vpiParent: @@ -110947,7 +110947,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:902:20, endln:902:36 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 |vpiRhs: \_constant: , line:902:32, endln:902:36 |vpiParent: @@ -110982,7 +110982,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:905:29, endln:916:71 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 |vpiRhs: \_operation: , line:905:54, endln:916:71 |vpiParent: @@ -111488,7 +111488,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:918:29, endln:923:73 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 |vpiRhs: \_operation: , line:918:55, endln:923:73 |vpiParent: @@ -111755,7 +111755,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:929:29, endln:929:50 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 |vpiRhs: \_constant: , line:929:49, endln:929:50 |vpiParent: @@ -111788,7 +111788,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:930:29, endln:930:51 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 |vpiRhs: \_constant: , line:930:49, endln:930:51 |vpiParent: @@ -111821,7 +111821,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:932:29, endln:932:63 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 |vpiRhs: \_constant: , line:932:47, endln:932:58 |vpiParent: @@ -111854,7 +111854,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:1011:16, endln:1011:40 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 |vpiRhs: \_constant: , line:1011:35, endln:1011:40 |vpiParent: @@ -111911,7 +111911,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:1013:16, endln:1013:33 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 |vpiRhs: \_constant: , line:1013:32, endln:1013:33 |vpiParent: @@ -111940,7 +111940,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:1014:16, endln:1014:30 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 |vpiRhs: \_constant: , line:1014:29, endln:1014:30 |vpiParent: @@ -111969,7 +111969,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:1069:27, endln:1069:55 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 |vpiRhs: \_constant: , line:1069:48, endln:1069:50 |vpiParent: @@ -112002,7 +112002,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:1070:29, endln:1070:51 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 |vpiRhs: \_constant: , line:1070:50, endln:1070:51 |vpiParent: @@ -112035,7 +112035,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:1071:29, endln:1071:92 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 |vpiRhs: \_constant: , line:1071:50, endln:1071:92 |vpiParent: @@ -112068,7 +112068,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:1072:29, endln:1072:80 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 |vpiRhs: \_constant: , line:1072:50, endln:1072:61 |vpiParent: @@ -112101,7 +112101,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:1073:29, endln:1073:53 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 |vpiRhs: \_constant: , line:1073:50, endln:1073:53 |vpiParent: @@ -112134,7 +112134,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:1075:27, endln:1075:55 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 |vpiRhs: \_constant: , line:1075:48, endln:1075:50 |vpiParent: @@ -112167,7 +112167,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:1076:28, endln:1076:50 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 |vpiRhs: \_constant: , line:1076:49, endln:1076:50 |vpiParent: @@ -112200,7 +112200,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:1077:29, endln:1077:92 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 |vpiRhs: \_constant: , line:1077:50, endln:1077:92 |vpiParent: @@ -112233,7 +112233,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:1078:29, endln:1078:80 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 |vpiRhs: \_constant: , line:1078:50, endln:1078:61 |vpiParent: @@ -112266,7 +112266,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:1079:29, endln:1079:53 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 |vpiRhs: \_constant: , line:1079:50, endln:1079:53 |vpiParent: @@ -112299,7 +112299,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:1293:16, endln:1293:32 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2042:1, endln:2079:10 |vpiRhs: \_constant: , line:1293:30, endln:1293:32 |vpiParent: @@ -112421,27 +112421,27 @@ design: (work@top) |vpiTaskFunc: \_function: (ariane_pkg::extract_transfer_size), line:1458:5, endln:1482:16 |uhdmallModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2125:1, endln:2130:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2125:1, endln:2130:10 |vpiParent: \_design: (work@top) |vpiFullName:work@top |vpiDefName:work@top |uhdmtopModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2125:1, endln:2130:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2125:1, endln:2130:10 |vpiName:work@top |vpiDefName:work@top |vpiTop:1 |vpiTopModule:1 - |vpiModule: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 + |vpiModuleInst: + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2125:1, endln:2130:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2125:1, endln:2130:10 |vpiName:i_ariane |vpiFullName:work@top.i_ariane |vpiParameter: \_parameter: (work@top.i_ariane.ARIANE_MARCHID), line:855:30, endln:855:44 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 |vpiTypespec: \_logic_typespec: (xlen_t), line:30:13, endln:30:29 |vpiParent: @@ -112476,7 +112476,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.i_ariane.ASID_WIDTH), line:782:16, endln:782:26 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 |INT:16 |vpiTypespec: \_int_typespec: @@ -112489,7 +112489,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.i_ariane.ArianeDefaultConfig), line:706:29, endln:706:48 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 |vpiTypespec: \_struct_typespec: (ariane_pkg::ariane_cfg_t), line:684:13, endln:684:19 |vpiParent: @@ -113026,7 +113026,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.i_ariane.BITS_SATURATION_COUNTER), line:783:16, endln:783:39 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 |UINT:2 |vpiTypespec: \_int_typespec: @@ -113039,7 +113039,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.i_ariane.CONFIG_L1D_SIZE), line:1075:27, endln:1075:42 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 |INT:32768 |vpiTypespec: \_int_typespec: , line:1075:14, endln:1075:26 @@ -113054,7 +113054,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.i_ariane.CONFIG_L1I_SIZE), line:1069:27, endln:1069:42 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 |INT:16384 |vpiTypespec: \_int_typespec: , line:1069:14, endln:1069:26 @@ -113069,7 +113069,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.i_ariane.DCACHE_INDEX_WIDTH), line:1077:29, endln:1077:47 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 |UINT:12 |vpiTypespec: \_int_typespec: , line:1077:16, endln:1077:28 @@ -113084,7 +113084,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.i_ariane.DCACHE_LINE_WIDTH), line:1079:29, endln:1079:46 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 |UINT:128 |vpiTypespec: \_int_typespec: , line:1079:16, endln:1079:28 @@ -113099,7 +113099,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.i_ariane.DCACHE_SET_ASSOC), line:1076:28, endln:1076:44 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 |UINT:8 |vpiTypespec: \_int_typespec: , line:1076:15, endln:1076:27 @@ -113114,7 +113114,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.i_ariane.DCACHE_TAG_WIDTH), line:1078:29, endln:1078:45 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 |INT:44 |vpiTypespec: \_int_typespec: , line:1078:16, endln:1078:28 @@ -113129,7 +113129,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.i_ariane.DEPTH_COMMIT), line:804:29, endln:804:41 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 |UINT:8 |vpiTypespec: \_int_typespec: , line:804:16, endln:804:28 @@ -113144,7 +113144,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.i_ariane.DEPTH_SPEC), line:795:29, endln:795:39 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 |UINT:4 |vpiTypespec: \_int_typespec: , line:795:16, endln:795:28 @@ -113159,7 +113159,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.i_ariane.DebugHartInfo), line:874:31, endln:874:44 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 |vpiTypespec: \_unsupported_typespec: (dm::hartinfo_t), line:874:16, endln:874:20 |vpiParent: @@ -113174,7 +113174,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.i_ariane.ENABLE_CYCLE_COUNT), line:900:20, endln:900:38 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 |BIN:1 |vpiTypespec: \_bit_typespec: , line:900:16, endln:900:19 @@ -113190,7 +113190,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.i_ariane.ENABLE_RENAME), line:786:16, endln:786:29 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 |BIN:0 |vpiTypespec: \_int_typespec: @@ -113217,7 +113217,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.i_ariane.ENABLE_SPIKE_COMMIT_LOG), line:884:20, endln:884:43 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 |BIN:1 |vpiTypespec: \_bit_typespec: , line:884:16, endln:884:19 @@ -113233,7 +113233,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.i_ariane.ENABLE_WFI), line:901:20, endln:901:30 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 |BIN:1 |vpiTypespec: \_bit_typespec: , line:901:16, endln:901:19 @@ -113249,7 +113249,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.i_ariane.EXC_OFF_RST), line:1011:16, endln:1011:27 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 |HEX:80 |vpiTypespec: \_int_typespec: @@ -113276,7 +113276,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.i_ariane.FETCH_FIFO_DEPTH), line:929:29, endln:929:45 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 |UINT:4 |vpiTypespec: \_int_typespec: , line:929:16, endln:929:28 @@ -113291,7 +113291,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.i_ariane.FETCH_WIDTH), line:930:29, endln:930:40 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 |UINT:32 |vpiTypespec: \_int_typespec: , line:930:16, endln:930:28 @@ -113306,7 +113306,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.i_ariane.FLEN), line:839:16, endln:839:20 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 |INT:64 |vpiTypespec: \_int_typespec: @@ -113319,7 +113319,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.i_ariane.FP_PRESENT), line:836:20, endln:836:30 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 |UINT:1 |vpiTypespec: \_bit_typespec: , line:836:16, endln:836:19 @@ -113335,7 +113335,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.i_ariane.ICACHE_INDEX_WIDTH), line:1071:29, endln:1071:47 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 |UINT:12 |vpiTypespec: \_int_typespec: , line:1071:16, endln:1071:28 @@ -113350,7 +113350,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.i_ariane.ICACHE_LINE_WIDTH), line:1073:29, endln:1073:46 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 |UINT:128 |vpiTypespec: \_int_typespec: , line:1073:16, endln:1073:28 @@ -113365,7 +113365,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.i_ariane.ICACHE_SET_ASSOC), line:1070:29, endln:1070:45 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 |UINT:4 |vpiTypespec: \_int_typespec: , line:1070:16, endln:1070:28 @@ -113380,7 +113380,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.i_ariane.ICACHE_TAG_WIDTH), line:1072:29, endln:1072:45 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 |INT:44 |vpiTypespec: \_int_typespec: , line:1072:16, endln:1072:28 @@ -113395,7 +113395,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.i_ariane.INSTR_PER_FETCH), line:932:29, endln:932:44 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 |INT:2 |vpiTypespec: \_int_typespec: , line:932:16, endln:932:28 @@ -113410,7 +113410,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.i_ariane.INVALIDATE_ON_FLUSH), line:890:22, endln:890:41 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 |BIN:1 |vpiTypespec: \_logic_typespec: , line:890:16, endln:890:21 @@ -113425,7 +113425,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.i_ariane.ISA_CODE), line:857:30, endln:857:38 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 |vpiTypespec: \_logic_typespec: (xlen_t), line:30:13, endln:30:29 |vpiParent: @@ -113460,7 +113460,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.i_ariane.ISSUE_WIDTH), line:788:16, endln:788:27 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 |UINT:1 |vpiTypespec: \_int_typespec: @@ -113473,7 +113473,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.i_ariane.LAT_COMP_FP16), line:827:29, endln:827:42 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 |DEC:1 |vpiTypespec: \_int_typespec: , line:827:16, endln:827:28 @@ -113488,7 +113488,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.i_ariane.LAT_COMP_FP16ALT), line:828:29, endln:828:45 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 |DEC:1 |vpiTypespec: \_int_typespec: , line:828:16, endln:828:28 @@ -113503,7 +113503,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.i_ariane.LAT_COMP_FP32), line:825:29, endln:825:42 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 |DEC:2 |vpiTypespec: \_int_typespec: , line:825:16, endln:825:28 @@ -113518,7 +113518,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.i_ariane.LAT_COMP_FP64), line:826:29, endln:826:42 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 |DEC:3 |vpiTypespec: \_int_typespec: , line:826:16, endln:826:28 @@ -113533,7 +113533,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.i_ariane.LAT_COMP_FP8), line:829:29, endln:829:41 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 |DEC:1 |vpiTypespec: \_int_typespec: , line:829:16, endln:829:28 @@ -113548,7 +113548,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.i_ariane.LAT_CONV), line:832:29, endln:832:37 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 |DEC:2 |vpiTypespec: \_int_typespec: , line:832:16, endln:832:28 @@ -113563,7 +113563,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.i_ariane.LAT_DIVSQRT), line:830:29, endln:830:40 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 |DEC:2 |vpiTypespec: \_int_typespec: , line:830:16, endln:830:28 @@ -113578,7 +113578,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.i_ariane.LAT_NONCOMP), line:831:29, endln:831:40 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 |DEC:1 |vpiTypespec: \_int_typespec: , line:831:16, endln:831:28 @@ -113593,7 +113593,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.i_ariane.MachineIrq), line:1014:16, endln:1014:26 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 |UINT:0 |vpiTypespec: \_int_typespec: @@ -113606,7 +113606,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.i_ariane.NR_COMMIT_PORTS), line:784:16, endln:784:31 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 |UINT:2 |vpiTypespec: \_int_typespec: @@ -113619,7 +113619,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.i_ariane.NR_LOAD_PIPE_REGS), line:791:29, endln:791:46 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 |UINT:1 |vpiTypespec: \_int_typespec: , line:791:16, endln:791:28 @@ -113634,7 +113634,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.i_ariane.NR_SB_ENTRIES), line:779:16, endln:779:29 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 |UINT:8 |vpiTypespec: \_int_typespec: @@ -113647,7 +113647,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.i_ariane.NR_STORE_PIPE_REGS), line:792:29, endln:792:47 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 |UINT:0 |vpiTypespec: \_int_typespec: , line:792:16, endln:792:28 @@ -113662,7 +113662,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.i_ariane.NR_WB_PORTS), line:871:16, endln:871:27 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 |UINT:4 |vpiTypespec: \_int_typespec: @@ -113675,7 +113675,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.i_ariane.NSX), line:846:20, endln:846:23 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 |UINT:0 |vpiTypespec: \_bit_typespec: , line:846:16, endln:846:19 @@ -113691,7 +113691,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.i_ariane.NrMaxRules), line:682:16, endln:682:26 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 |UINT:16 |vpiTypespec: \_int_typespec: @@ -113704,7 +113704,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.i_ariane.PPN4K_WIDTH), line:1293:16, endln:1293:27 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 |UINT:38 |vpiTypespec: \_int_typespec: @@ -113717,7 +113717,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.i_ariane.REG_ADDR_SIZE), line:870:16, endln:870:29 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 |UINT:6 |vpiTypespec: \_int_typespec: @@ -113730,7 +113730,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.i_ariane.RVA), line:816:20, endln:816:23 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 |BIN:1 |vpiTypespec: \_bit_typespec: , line:816:16, endln:816:19 @@ -113746,7 +113746,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.i_ariane.RVD), line:814:20, endln:814:23 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 |INT:1 |vpiTypespec: \_bit_typespec: , line:814:16, endln:814:19 @@ -113762,7 +113762,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.i_ariane.RVF), line:813:20, endln:813:23 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 |INT:1 |vpiTypespec: \_bit_typespec: , line:813:16, endln:813:19 @@ -113778,7 +113778,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.i_ariane.RVFVEC), line:848:20, endln:848:26 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 |UINT:0 |vpiTypespec: \_bit_typespec: , line:848:16, endln:848:19 @@ -113794,7 +113794,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.i_ariane.SMODE_STATUS_READ_MASK), line:905:29, endln:905:51 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 |vpiTypespec: \_logic_typespec: , line:905:16, endln:905:28 |vpiParent: @@ -113828,7 +113828,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.i_ariane.SMODE_STATUS_WRITE_MASK), line:918:29, endln:918:52 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 |vpiTypespec: \_logic_typespec: , line:918:16, endln:918:28 |vpiParent: @@ -113862,7 +113862,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.i_ariane.SupervisorIrq), line:1013:16, endln:1013:29 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 |UINT:1 |vpiTypespec: \_int_typespec: @@ -113875,7 +113875,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.i_ariane.TRANS_ID_BITS), line:780:16, endln:780:29 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 |UINT:3 |vpiTypespec: \_int_typespec: @@ -113888,7 +113888,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.i_ariane.XF16), line:819:20, endln:819:24 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 |BIN:0 |vpiTypespec: \_bit_typespec: , line:819:16, endln:819:19 @@ -113904,7 +113904,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.i_ariane.XF16ALT), line:820:20, endln:820:27 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 |BIN:0 |vpiTypespec: \_bit_typespec: , line:820:16, endln:820:19 @@ -113920,7 +113920,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.i_ariane.XF16ALTVEC), line:850:20, endln:850:30 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 |UINT:0 |vpiTypespec: \_bit_typespec: , line:850:16, endln:850:19 @@ -113936,7 +113936,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.i_ariane.XF16VEC), line:849:20, endln:849:27 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 |UINT:0 |vpiTypespec: \_bit_typespec: , line:849:16, endln:849:19 @@ -113952,7 +113952,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.i_ariane.XF8), line:821:20, endln:821:23 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 |BIN:0 |vpiTypespec: \_bit_typespec: , line:821:16, endln:821:19 @@ -113968,7 +113968,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.i_ariane.XF8VEC), line:851:20, endln:851:26 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 |UINT:0 |vpiTypespec: \_bit_typespec: , line:851:16, endln:851:19 @@ -113984,7 +113984,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.i_ariane.XFVEC), line:822:20, endln:822:25 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 |BIN:0 |vpiTypespec: \_bit_typespec: , line:822:16, endln:822:19 @@ -114000,7 +114000,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.i_ariane.ZERO_TVAL), line:902:20, endln:902:29 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 |BIN:0 |vpiTypespec: \_bit_typespec: , line:902:16, endln:902:19 @@ -114016,7 +114016,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.i_ariane.ArianeCfg), line:2115:38, endln:2115:47 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 |vpiTypespec: \_struct_typespec: (ariane_pkg::ariane_cfg_t), line:684:13, endln:684:19 |vpiParent: @@ -114551,7 +114551,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:2115:38, endln:2115:85 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 |vpiOverriden:1 |vpiRhs: \_ref_obj: (ariane_soc::ArianeSocCfg), line:2127:19, endln:2127:29 @@ -114561,7 +114561,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:682:16, endln:682:31 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 |vpiRhs: \_constant: , line:682:29, endln:682:31 |vpiDecompile:16 @@ -114575,7 +114575,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:706:29, endln:728:6 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 |vpiRhs: \_operation: , line:706:51, endln:728:6 |vpiParent: @@ -115237,7 +115237,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:779:16, endln:779:33 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 |vpiRhs: \_constant: , line:779:32, endln:779:33 |vpiDecompile:8 @@ -115251,7 +115251,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:780:16, endln:780:53 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 |vpiRhs: \_constant: , line:780:32, endln:780:53 |vpiDecompile:3 @@ -115265,7 +115265,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:782:16, endln:782:60 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 |vpiRhs: \_constant: , line:782:32, endln:782:60 |vpiDecompile:16 @@ -115279,7 +115279,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:783:16, endln:783:43 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 |vpiRhs: \_constant: , line:783:42, endln:783:43 |vpiDecompile:2 @@ -115293,7 +115293,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:784:16, endln:784:35 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 |vpiRhs: \_constant: , line:784:34, endln:784:35 |vpiDecompile:2 @@ -115307,7 +115307,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:786:16, endln:786:36 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 |vpiRhs: \_constant: , line:786:32, endln:786:36 |vpiDecompile:1'b0 @@ -115321,7 +115321,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:788:16, endln:788:31 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 |vpiRhs: \_constant: , line:788:30, endln:788:31 |vpiDecompile:1 @@ -115335,7 +115335,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:791:29, endln:791:50 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 |vpiRhs: \_constant: , line:791:49, endln:791:50 |vpiDecompile:1 @@ -115349,7 +115349,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:792:29, endln:792:51 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 |vpiRhs: \_constant: , line:792:50, endln:792:51 |vpiDecompile:0 @@ -115363,7 +115363,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:795:29, endln:795:45 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 |vpiRhs: \_constant: , line:795:44, endln:795:45 |vpiDecompile:4 @@ -115377,7 +115377,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:804:29, endln:804:45 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 |vpiRhs: \_constant: , line:804:44, endln:804:45 |vpiDecompile:8 @@ -115391,7 +115391,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:813:20, endln:813:42 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 |vpiRhs: \_constant: , line:813:26, endln:813:42 |vpiDecompile:1 @@ -115405,7 +115405,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:814:20, endln:814:42 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 |vpiRhs: \_constant: , line:814:26, endln:814:42 |vpiDecompile:1 @@ -115419,7 +115419,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:816:20, endln:816:30 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 |vpiRhs: \_constant: , line:816:26, endln:816:30 |vpiDecompile:1'b1 @@ -115433,7 +115433,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:819:20, endln:819:34 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 |vpiRhs: \_constant: , line:819:30, endln:819:34 |vpiDecompile:1'b0 @@ -115447,7 +115447,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:820:20, endln:820:34 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 |vpiRhs: \_constant: , line:820:30, endln:820:34 |vpiDecompile:1'b0 @@ -115461,7 +115461,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:821:20, endln:821:34 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 |vpiRhs: \_constant: , line:821:30, endln:821:34 |vpiDecompile:1'b0 @@ -115475,7 +115475,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:822:20, endln:822:34 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 |vpiRhs: \_constant: , line:822:30, endln:822:34 |vpiDecompile:1'b0 @@ -115489,7 +115489,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:825:29, endln:825:51 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 |vpiRhs: \_constant: , line:825:48, endln:825:51 |vpiDecompile:2 @@ -115503,7 +115503,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:826:29, endln:826:51 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 |vpiRhs: \_constant: , line:826:48, endln:826:51 |vpiDecompile:3 @@ -115517,7 +115517,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:827:29, endln:827:51 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 |vpiRhs: \_constant: , line:827:48, endln:827:51 |vpiDecompile:1 @@ -115531,7 +115531,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:828:29, endln:828:51 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 |vpiRhs: \_constant: , line:828:48, endln:828:51 |vpiDecompile:1 @@ -115545,7 +115545,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:829:29, endln:829:51 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 |vpiRhs: \_constant: , line:829:48, endln:829:51 |vpiDecompile:1 @@ -115559,7 +115559,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:830:29, endln:830:51 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 |vpiRhs: \_constant: , line:830:48, endln:830:51 |vpiDecompile:2 @@ -115573,7 +115573,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:831:29, endln:831:51 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 |vpiRhs: \_constant: , line:831:48, endln:831:51 |vpiDecompile:1 @@ -115587,7 +115587,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:832:29, endln:832:51 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 |vpiRhs: \_constant: , line:832:48, endln:832:51 |vpiDecompile:2 @@ -115601,7 +115601,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:836:20, endln:836:65 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 |vpiRhs: \_constant: , line:836:33, endln:836:65 |vpiDecompile:1 @@ -115615,7 +115615,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:839:16, endln:844:27 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 |vpiRhs: \_constant: , line:839:26, endln:844:27 |vpiDecompile:64 @@ -115629,7 +115629,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:846:20, endln:846:54 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 |vpiRhs: \_constant: , line:846:26, endln:846:54 |vpiDecompile:0 @@ -115643,7 +115643,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:848:20, endln:848:58 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 |vpiRhs: \_constant: , line:848:33, endln:848:58 |vpiDecompile:0 @@ -115657,7 +115657,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:849:20, endln:849:58 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 |vpiRhs: \_constant: , line:849:33, endln:849:58 |vpiDecompile:0 @@ -115671,7 +115671,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:850:20, endln:850:58 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 |vpiRhs: \_constant: , line:850:33, endln:850:58 |vpiDecompile:0 @@ -115685,7 +115685,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:851:20, endln:851:57 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 |vpiRhs: \_constant: , line:851:33, endln:851:57 |vpiDecompile:0 @@ -115699,7 +115699,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:855:30, endln:855:78 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 |vpiRhs: \_operation: , line:855:47, endln:855:78 |vpiTypespec: @@ -115786,7 +115786,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:857:30, endln:867:86 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 |vpiRhs: \_operation: , line:857:41, endln:867:86 |vpiTypespec: @@ -116149,7 +116149,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:870:16, endln:870:33 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 |vpiRhs: \_constant: , line:870:32, endln:870:33 |vpiDecompile:6 @@ -116163,7 +116163,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:871:16, endln:871:31 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 |vpiRhs: \_constant: , line:871:30, endln:871:31 |vpiDecompile:4 @@ -116177,7 +116177,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:874:31, endln:881:48 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 |vpiRhs: \_operation: , line:874:47, endln:881:48 |vpiParent: @@ -116286,7 +116286,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:884:20, endln:884:50 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 |vpiRhs: \_constant: , line:884:46, endln:884:50 |vpiDecompile:1'b1 @@ -116300,7 +116300,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:890:22, endln:890:48 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 |vpiRhs: \_constant: , line:890:44, endln:890:48 |vpiDecompile:1'b1 @@ -116314,7 +116314,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:900:20, endln:900:45 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 |vpiRhs: \_constant: , line:900:41, endln:900:45 |vpiDecompile:1'b1 @@ -116328,7 +116328,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:901:20, endln:901:37 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 |vpiRhs: \_constant: , line:901:33, endln:901:37 |vpiDecompile:1'b1 @@ -116342,7 +116342,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:902:20, endln:902:36 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 |vpiRhs: \_constant: , line:902:32, endln:902:36 |vpiDecompile:1'b0 @@ -116356,7 +116356,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:905:29, endln:916:71 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 |vpiRhs: \_operation: , line:905:54, endln:916:71 |vpiTypespec: @@ -116852,7 +116852,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:918:29, endln:923:73 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 |vpiRhs: \_operation: , line:918:55, endln:923:73 |vpiTypespec: @@ -117111,7 +117111,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:929:29, endln:929:50 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 |vpiRhs: \_constant: , line:929:49, endln:929:50 |vpiDecompile:4 @@ -117125,7 +117125,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:930:29, endln:930:51 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 |vpiRhs: \_constant: , line:930:49, endln:930:51 |vpiDecompile:32 @@ -117139,7 +117139,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:932:29, endln:932:63 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 |vpiRhs: \_constant: , line:932:47, endln:932:63 |vpiDecompile:2 @@ -117153,7 +117153,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:1011:16, endln:1011:40 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 |vpiRhs: \_constant: , line:1011:35, endln:1011:40 |vpiDecompile:8'h80 @@ -117167,7 +117167,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:1013:16, endln:1013:33 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 |vpiRhs: \_constant: , line:1013:32, endln:1013:33 |vpiDecompile:1 @@ -117181,7 +117181,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:1014:16, endln:1014:30 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 |vpiRhs: \_constant: , line:1014:29, endln:1014:30 |vpiDecompile:0 @@ -117195,7 +117195,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:1069:27, endln:1069:55 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 |vpiRhs: \_constant: , line:1069:48, endln:1069:55 |vpiDecompile:16384 @@ -117209,7 +117209,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:1070:29, endln:1070:51 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 |vpiRhs: \_constant: , line:1070:50, endln:1070:51 |vpiDecompile:4 @@ -117223,7 +117223,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:1071:29, endln:1071:92 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 |vpiRhs: \_constant: , line:1071:50, endln:1071:92 |vpiDecompile:12 @@ -117237,7 +117237,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:1072:29, endln:1072:80 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 |vpiRhs: \_constant: , line:1072:50, endln:1072:80 |vpiDecompile:44 @@ -117251,7 +117251,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:1073:29, endln:1073:53 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 |vpiRhs: \_constant: , line:1073:50, endln:1073:53 |vpiDecompile:128 @@ -117265,7 +117265,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:1075:27, endln:1075:55 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 |vpiRhs: \_constant: , line:1075:48, endln:1075:55 |vpiDecompile:32768 @@ -117279,7 +117279,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:1076:28, endln:1076:50 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 |vpiRhs: \_constant: , line:1076:49, endln:1076:50 |vpiDecompile:8 @@ -117293,7 +117293,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:1077:29, endln:1077:92 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 |vpiRhs: \_constant: , line:1077:50, endln:1077:92 |vpiDecompile:12 @@ -117307,7 +117307,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:1078:29, endln:1078:80 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 |vpiRhs: \_constant: , line:1078:50, endln:1078:80 |vpiDecompile:44 @@ -117321,7 +117321,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:1079:29, endln:1079:53 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 |vpiRhs: \_constant: , line:1079:50, endln:1079:53 |vpiDecompile:128 @@ -117335,7 +117335,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:1293:16, endln:1293:32 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 |vpiRhs: \_constant: , line:1293:30, endln:1293:32 |vpiDecompile:38 @@ -117410,13 +117410,13 @@ design: (work@top) |vpiTaskFunc: \_function: (ariane_pkg::check_cfg), line:731:5, endln:743:16 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 |vpiName:check_cfg |vpiFullName:ariane_pkg::check_cfg |vpiVisibility:1 |vpiAutomatic:1 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 |vpiIODecl: \_io_decl: (Cfg), line:731:53, endln:731:56 |vpiParent: @@ -117717,11 +117717,11 @@ design: (work@top) |vpiOperand: \_constant: , line:740:36, endln:740:38 |vpiInstance: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 |vpiTaskFunc: \_function: (ariane_pkg::range_check), line:745:5, endln:748:30 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 |vpiName:range_check |vpiFullName:ariane_pkg::range_check |vpiVisibility:1 @@ -117729,7 +117729,7 @@ design: (work@top) |vpiReturn: \_logic_var: , line:745:24, endln:745:29 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 |vpiIODecl: \_io_decl: (base), line:745:54, endln:745:58 |vpiParent: @@ -117819,11 +117819,11 @@ design: (work@top) |vpiActual: \_io_decl: (len), line:745:72, endln:745:75 |vpiInstance: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 |vpiTaskFunc: \_function: (ariane_pkg::is_inside_nonidempotent_regions), line:750:5, endln:757:50 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 |vpiName:is_inside_nonidempotent_regions |vpiFullName:ariane_pkg::is_inside_nonidempotent_regions |vpiVariables: @@ -117839,7 +117839,7 @@ design: (work@top) |vpiReturn: \_logic_var: , line:750:24, endln:750:29 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 |vpiIODecl: \_io_decl: (Cfg), line:750:76, endln:750:79 |vpiParent: @@ -118083,11 +118083,11 @@ design: (work@top) |vpiActual: \_logic_var: (ariane_pkg::is_inside_nonidempotent_regions::pass), line:751:29, endln:751:33 |vpiInstance: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 |vpiTaskFunc: \_function: (ariane_pkg::is_inside_execute_regions), line:759:5, endln:767:44 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 |vpiName:is_inside_execute_regions |vpiFullName:ariane_pkg::is_inside_execute_regions |vpiVariables: @@ -118103,7 +118103,7 @@ design: (work@top) |vpiReturn: \_logic_var: , line:759:24, endln:759:29 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 |vpiIODecl: \_io_decl: (Cfg), line:759:70, endln:759:73 |vpiParent: @@ -118347,11 +118347,11 @@ design: (work@top) |vpiActual: \_logic_var: (ariane_pkg::is_inside_execute_regions::pass), line:761:29, endln:761:33 |vpiInstance: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 |vpiTaskFunc: \_function: (ariane_pkg::is_inside_cacheable_regions), line:769:5, endln:776:46 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 |vpiName:is_inside_cacheable_regions |vpiFullName:ariane_pkg::is_inside_cacheable_regions |vpiVariables: @@ -118368,7 +118368,7 @@ design: (work@top) |vpiReturn: \_logic_var: , line:769:24, endln:769:29 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 |vpiIODecl: \_io_decl: (Cfg), line:769:72, endln:769:75 |vpiParent: @@ -118613,11 +118613,11 @@ design: (work@top) |vpiActual: \_logic_var: (ariane_pkg::is_inside_cacheable_regions::pass), line:770:39, endln:770:43 |vpiInstance: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 |vpiTaskFunc: \_function: (ariane_pkg::op_is_branch), line:1132:5, endln:1137:16 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 |vpiName:op_is_branch |vpiFullName:ariane_pkg::op_is_branch |vpiVisibility:1 @@ -118625,7 +118625,7 @@ design: (work@top) |vpiReturn: \_logic_var: , line:1132:24, endln:1132:29 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 |vpiIODecl: \_io_decl: (op), line:1132:56, endln:1132:58 |vpiParent: @@ -118752,11 +118752,11 @@ design: (work@top) |vpiCondition: \_constant: , line:1135:48, endln:1135:52 |vpiInstance: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 |vpiTaskFunc: \_function: (ariane_pkg::is_rs1_fpr), line:1142:5, endln:1157:16 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 |vpiName:is_rs1_fpr |vpiFullName:ariane_pkg::is_rs1_fpr |vpiVisibility:1 @@ -118764,7 +118764,7 @@ design: (work@top) |vpiReturn: \_logic_var: , line:1142:24, endln:1142:29 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 |vpiIODecl: \_io_decl: (op), line:1142:54, endln:1142:56 |vpiParent: @@ -118956,11 +118956,11 @@ design: (work@top) |vpiCondition: \_constant: , line:1156:20, endln:1156:24 |vpiInstance: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 |vpiTaskFunc: \_function: (ariane_pkg::is_rs2_fpr), line:1159:5, endln:1173:16 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 |vpiName:is_rs2_fpr |vpiFullName:ariane_pkg::is_rs2_fpr |vpiVisibility:1 @@ -118968,7 +118968,7 @@ design: (work@top) |vpiReturn: \_logic_var: , line:1159:24, endln:1159:29 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 |vpiIODecl: \_io_decl: (op), line:1159:54, endln:1159:56 |vpiParent: @@ -119171,11 +119171,11 @@ design: (work@top) |vpiCondition: \_constant: , line:1172:20, endln:1172:24 |vpiInstance: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 |vpiTaskFunc: \_function: (ariane_pkg::is_imm_fpr), line:1176:5, endln:1186:16 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 |vpiName:is_imm_fpr |vpiFullName:ariane_pkg::is_imm_fpr |vpiVisibility:1 @@ -119183,7 +119183,7 @@ design: (work@top) |vpiReturn: \_logic_var: , line:1176:24, endln:1176:29 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 |vpiIODecl: \_io_decl: (op), line:1176:54, endln:1176:56 |vpiParent: @@ -119318,11 +119318,11 @@ design: (work@top) |vpiCondition: \_constant: , line:1185:20, endln:1185:24 |vpiInstance: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 |vpiTaskFunc: \_function: (ariane_pkg::is_rd_fpr), line:1188:5, endln:1203:16 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 |vpiName:is_rd_fpr |vpiFullName:ariane_pkg::is_rd_fpr |vpiVisibility:1 @@ -119330,7 +119330,7 @@ design: (work@top) |vpiReturn: \_logic_var: , line:1188:24, endln:1188:29 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 |vpiIODecl: \_io_decl: (op), line:1188:53, endln:1188:55 |vpiParent: @@ -119538,11 +119538,11 @@ design: (work@top) |vpiCondition: \_constant: , line:1202:20, endln:1202:24 |vpiInstance: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 |vpiTaskFunc: \_function: (ariane_pkg::is_amo), line:1205:5, endln:1212:16 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 |vpiName:is_amo |vpiFullName:ariane_pkg::is_amo |vpiVisibility:1 @@ -119550,7 +119550,7 @@ design: (work@top) |vpiReturn: \_logic_var: , line:1205:24, endln:1205:29 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 |vpiIODecl: \_io_decl: (op), line:1205:44, endln:1205:46 |vpiParent: @@ -119624,11 +119624,11 @@ design: (work@top) |vpiCondition: \_constant: , line:1210:29, endln:1210:33 |vpiInstance: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 |vpiTaskFunc: \_function: (ariane_pkg::sext32), line:1373:5, endln:1375:16 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 |vpiName:sext32 |vpiFullName:ariane_pkg::sext32 |vpiVisibility:1 @@ -119636,7 +119636,7 @@ design: (work@top) |vpiReturn: \_logic_var: , line:1373:24, endln:1373:37 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 |vpiIODecl: \_io_decl: (operand), line:1373:59, endln:1373:66 |vpiParent: @@ -119706,11 +119706,11 @@ design: (work@top) |vpiRightRange: \_constant: , line:1374:59, endln:1374:60 |vpiInstance: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 |vpiTaskFunc: \_function: (ariane_pkg::uj_imm), line:1380:5, endln:1382:16 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 |vpiName:uj_imm |vpiFullName:ariane_pkg::uj_imm |vpiVisibility:1 @@ -119718,7 +119718,7 @@ design: (work@top) |vpiReturn: \_logic_var: , line:1380:24, endln:1380:47 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 |vpiIODecl: \_io_decl: (instruction_i), line:1380:69, endln:1380:82 |vpiParent: @@ -119829,11 +119829,11 @@ design: (work@top) |vpiOperand: \_constant: , line:1381:122, endln:1381:126 |vpiInstance: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 |vpiTaskFunc: \_function: (ariane_pkg::i_imm), line:1384:5, endln:1386:16 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 |vpiName:i_imm |vpiFullName:ariane_pkg::i_imm |vpiVisibility:1 @@ -119841,7 +119841,7 @@ design: (work@top) |vpiReturn: \_logic_var: , line:1384:24, endln:1384:47 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 |vpiIODecl: \_io_decl: (instruction_i), line:1384:68, endln:1384:81 |vpiParent: @@ -119918,11 +119918,11 @@ design: (work@top) |vpiRightRange: \_constant: , line:1385:76, endln:1385:78 |vpiInstance: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 |vpiTaskFunc: \_function: (ariane_pkg::sb_imm), line:1388:5, endln:1390:16 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 |vpiName:sb_imm |vpiFullName:ariane_pkg::sb_imm |vpiVisibility:1 @@ -119930,7 +119930,7 @@ design: (work@top) |vpiReturn: \_logic_var: , line:1388:24, endln:1388:47 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 |vpiIODecl: \_io_decl: (instruction_i), line:1388:69, endln:1388:82 |vpiParent: @@ -120057,11 +120057,11 @@ design: (work@top) |vpiOperand: \_constant: , line:1389:139, endln:1389:143 |vpiInstance: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 |vpiTaskFunc: \_function: (ariane_pkg::data_align), line:1396:5, endln:1411:16 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 |vpiName:data_align |vpiFullName:ariane_pkg::data_align |vpiVariables: @@ -120085,7 +120085,7 @@ design: (work@top) |vpiReturn: \_logic_var: , line:1396:24, endln:1396:37 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 |vpiIODecl: \_io_decl: (addr), line:1396:62, endln:1396:66 |vpiParent: @@ -120816,11 +120816,11 @@ design: (work@top) |vpiRightRange: \_constant: , line:1410:39, endln:1410:40 |vpiInstance: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 |vpiTaskFunc: \_function: (ariane_pkg::be_gen), line:1414:5, endln:1453:16 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 |vpiName:be_gen |vpiFullName:ariane_pkg::be_gen |vpiVisibility:1 @@ -120828,7 +120828,7 @@ design: (work@top) |vpiReturn: \_logic_var: , line:1414:24, endln:1414:35 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 |vpiIODecl: \_io_decl: (addr), line:1414:55, endln:1414:59 |vpiParent: @@ -121223,11 +121223,11 @@ design: (work@top) |vpiCondition: \_constant: , line:1452:16, endln:1452:20 |vpiInstance: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 |vpiTaskFunc: \_function: (ariane_pkg::extract_transfer_size), line:1458:5, endln:1482:16 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 |vpiName:extract_transfer_size |vpiFullName:ariane_pkg::extract_transfer_size |vpiVisibility:1 @@ -121235,7 +121235,7 @@ design: (work@top) |vpiReturn: \_logic_var: , line:1458:24, endln:1458:35 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 |vpiIODecl: \_io_decl: (op), line:1458:64, endln:1458:66 |vpiParent: @@ -121646,19 +121646,19 @@ design: (work@top) |vpiCondition: \_constant: , line:1480:33, endln:1480:38 |vpiInstance: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2125:1, endln:2130:10 - |vpiModule: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2125:1, endln:2130:10 + |vpiModuleInst: + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 |vpiParent: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 |vpiName:ex_stage_i |vpiFullName:work@top.i_ariane.ex_stage_i |vpiParameter: \_parameter: (work@top.i_ariane.ex_stage_i.ARIANE_MARCHID), line:855:30, endln:855:44 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 |vpiTypespec: \_logic_typespec: (xlen_t), line:30:13, endln:30:29 |vpiParent: @@ -121693,7 +121693,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.i_ariane.ex_stage_i.ASID_WIDTH), line:782:16, endln:782:26 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 |INT:16 |vpiTypespec: \_int_typespec: @@ -121706,7 +121706,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.i_ariane.ex_stage_i.ArianeDefaultConfig), line:706:29, endln:706:48 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 |vpiTypespec: \_struct_typespec: (ariane_pkg::ariane_cfg_t), line:684:13, endln:684:19 |vpiParent: @@ -122243,7 +122243,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.i_ariane.ex_stage_i.BITS_SATURATION_COUNTER), line:783:16, endln:783:39 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 |UINT:2 |vpiTypespec: \_int_typespec: @@ -122256,7 +122256,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.i_ariane.ex_stage_i.CONFIG_L1D_SIZE), line:1075:27, endln:1075:42 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 |INT:32768 |vpiTypespec: \_int_typespec: , line:1075:14, endln:1075:26 @@ -122271,7 +122271,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.i_ariane.ex_stage_i.CONFIG_L1I_SIZE), line:1069:27, endln:1069:42 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 |INT:16384 |vpiTypespec: \_int_typespec: , line:1069:14, endln:1069:26 @@ -122286,7 +122286,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.i_ariane.ex_stage_i.DCACHE_INDEX_WIDTH), line:1077:29, endln:1077:47 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 |UINT:12 |vpiTypespec: \_int_typespec: , line:1077:16, endln:1077:28 @@ -122301,7 +122301,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.i_ariane.ex_stage_i.DCACHE_LINE_WIDTH), line:1079:29, endln:1079:46 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 |UINT:128 |vpiTypespec: \_int_typespec: , line:1079:16, endln:1079:28 @@ -122316,7 +122316,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.i_ariane.ex_stage_i.DCACHE_SET_ASSOC), line:1076:28, endln:1076:44 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 |UINT:8 |vpiTypespec: \_int_typespec: , line:1076:15, endln:1076:27 @@ -122331,7 +122331,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.i_ariane.ex_stage_i.DCACHE_TAG_WIDTH), line:1078:29, endln:1078:45 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 |INT:44 |vpiTypespec: \_int_typespec: , line:1078:16, endln:1078:28 @@ -122346,7 +122346,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.i_ariane.ex_stage_i.DEPTH_COMMIT), line:804:29, endln:804:41 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 |UINT:8 |vpiTypespec: \_int_typespec: , line:804:16, endln:804:28 @@ -122361,7 +122361,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.i_ariane.ex_stage_i.DEPTH_SPEC), line:795:29, endln:795:39 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 |UINT:4 |vpiTypespec: \_int_typespec: , line:795:16, endln:795:28 @@ -122376,7 +122376,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.i_ariane.ex_stage_i.DebugHartInfo), line:874:31, endln:874:44 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 |vpiTypespec: \_unsupported_typespec: (dm::hartinfo_t), line:874:16, endln:874:20 |vpiParent: @@ -122391,7 +122391,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.i_ariane.ex_stage_i.ENABLE_CYCLE_COUNT), line:900:20, endln:900:38 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 |BIN:1 |vpiTypespec: \_bit_typespec: , line:900:16, endln:900:19 @@ -122407,7 +122407,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.i_ariane.ex_stage_i.ENABLE_RENAME), line:786:16, endln:786:29 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 |BIN:0 |vpiTypespec: \_int_typespec: @@ -122434,7 +122434,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.i_ariane.ex_stage_i.ENABLE_SPIKE_COMMIT_LOG), line:884:20, endln:884:43 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 |BIN:1 |vpiTypespec: \_bit_typespec: , line:884:16, endln:884:19 @@ -122450,7 +122450,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.i_ariane.ex_stage_i.ENABLE_WFI), line:901:20, endln:901:30 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 |BIN:1 |vpiTypespec: \_bit_typespec: , line:901:16, endln:901:19 @@ -122466,7 +122466,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.i_ariane.ex_stage_i.EXC_OFF_RST), line:1011:16, endln:1011:27 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 |HEX:80 |vpiTypespec: \_int_typespec: @@ -122493,7 +122493,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.i_ariane.ex_stage_i.FETCH_FIFO_DEPTH), line:929:29, endln:929:45 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 |UINT:4 |vpiTypespec: \_int_typespec: , line:929:16, endln:929:28 @@ -122508,7 +122508,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.i_ariane.ex_stage_i.FETCH_WIDTH), line:930:29, endln:930:40 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 |UINT:32 |vpiTypespec: \_int_typespec: , line:930:16, endln:930:28 @@ -122523,7 +122523,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.i_ariane.ex_stage_i.FLEN), line:839:16, endln:839:20 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 |INT:64 |vpiTypespec: \_int_typespec: @@ -122536,7 +122536,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.i_ariane.ex_stage_i.FP_PRESENT), line:836:20, endln:836:30 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 |UINT:1 |vpiTypespec: \_bit_typespec: , line:836:16, endln:836:19 @@ -122552,7 +122552,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.i_ariane.ex_stage_i.ICACHE_INDEX_WIDTH), line:1071:29, endln:1071:47 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 |UINT:12 |vpiTypespec: \_int_typespec: , line:1071:16, endln:1071:28 @@ -122567,7 +122567,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.i_ariane.ex_stage_i.ICACHE_LINE_WIDTH), line:1073:29, endln:1073:46 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 |UINT:128 |vpiTypespec: \_int_typespec: , line:1073:16, endln:1073:28 @@ -122582,7 +122582,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.i_ariane.ex_stage_i.ICACHE_SET_ASSOC), line:1070:29, endln:1070:45 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 |UINT:4 |vpiTypespec: \_int_typespec: , line:1070:16, endln:1070:28 @@ -122597,7 +122597,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.i_ariane.ex_stage_i.ICACHE_TAG_WIDTH), line:1072:29, endln:1072:45 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 |INT:44 |vpiTypespec: \_int_typespec: , line:1072:16, endln:1072:28 @@ -122612,7 +122612,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.i_ariane.ex_stage_i.INSTR_PER_FETCH), line:932:29, endln:932:44 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 |INT:2 |vpiTypespec: \_int_typespec: , line:932:16, endln:932:28 @@ -122627,7 +122627,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.i_ariane.ex_stage_i.INVALIDATE_ON_FLUSH), line:890:22, endln:890:41 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 |BIN:1 |vpiTypespec: \_logic_typespec: , line:890:16, endln:890:21 @@ -122642,7 +122642,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.i_ariane.ex_stage_i.ISA_CODE), line:857:30, endln:857:38 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 |vpiTypespec: \_logic_typespec: (xlen_t), line:30:13, endln:30:29 |vpiParent: @@ -122677,7 +122677,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.i_ariane.ex_stage_i.ISSUE_WIDTH), line:788:16, endln:788:27 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 |UINT:1 |vpiTypespec: \_int_typespec: @@ -122690,7 +122690,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.i_ariane.ex_stage_i.LAT_COMP_FP16), line:827:29, endln:827:42 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 |DEC:1 |vpiTypespec: \_int_typespec: , line:827:16, endln:827:28 @@ -122705,7 +122705,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.i_ariane.ex_stage_i.LAT_COMP_FP16ALT), line:828:29, endln:828:45 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 |DEC:1 |vpiTypespec: \_int_typespec: , line:828:16, endln:828:28 @@ -122720,7 +122720,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.i_ariane.ex_stage_i.LAT_COMP_FP32), line:825:29, endln:825:42 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 |DEC:2 |vpiTypespec: \_int_typespec: , line:825:16, endln:825:28 @@ -122735,7 +122735,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.i_ariane.ex_stage_i.LAT_COMP_FP64), line:826:29, endln:826:42 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 |DEC:3 |vpiTypespec: \_int_typespec: , line:826:16, endln:826:28 @@ -122750,7 +122750,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.i_ariane.ex_stage_i.LAT_COMP_FP8), line:829:29, endln:829:41 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 |DEC:1 |vpiTypespec: \_int_typespec: , line:829:16, endln:829:28 @@ -122765,7 +122765,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.i_ariane.ex_stage_i.LAT_CONV), line:832:29, endln:832:37 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 |DEC:2 |vpiTypespec: \_int_typespec: , line:832:16, endln:832:28 @@ -122780,7 +122780,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.i_ariane.ex_stage_i.LAT_DIVSQRT), line:830:29, endln:830:40 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 |DEC:2 |vpiTypespec: \_int_typespec: , line:830:16, endln:830:28 @@ -122795,7 +122795,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.i_ariane.ex_stage_i.LAT_NONCOMP), line:831:29, endln:831:40 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 |DEC:1 |vpiTypespec: \_int_typespec: , line:831:16, endln:831:28 @@ -122810,7 +122810,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.i_ariane.ex_stage_i.MachineIrq), line:1014:16, endln:1014:26 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 |UINT:0 |vpiTypespec: \_int_typespec: @@ -122823,7 +122823,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.i_ariane.ex_stage_i.NR_COMMIT_PORTS), line:784:16, endln:784:31 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 |UINT:2 |vpiTypespec: \_int_typespec: @@ -122836,7 +122836,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.i_ariane.ex_stage_i.NR_LOAD_PIPE_REGS), line:791:29, endln:791:46 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 |UINT:1 |vpiTypespec: \_int_typespec: , line:791:16, endln:791:28 @@ -122851,7 +122851,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.i_ariane.ex_stage_i.NR_SB_ENTRIES), line:779:16, endln:779:29 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 |UINT:8 |vpiTypespec: \_int_typespec: @@ -122864,7 +122864,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.i_ariane.ex_stage_i.NR_STORE_PIPE_REGS), line:792:29, endln:792:47 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 |UINT:0 |vpiTypespec: \_int_typespec: , line:792:16, endln:792:28 @@ -122879,7 +122879,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.i_ariane.ex_stage_i.NR_WB_PORTS), line:871:16, endln:871:27 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 |UINT:4 |vpiTypespec: \_int_typespec: @@ -122892,7 +122892,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.i_ariane.ex_stage_i.NSX), line:846:20, endln:846:23 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 |UINT:0 |vpiTypespec: \_bit_typespec: , line:846:16, endln:846:19 @@ -122908,7 +122908,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.i_ariane.ex_stage_i.NrMaxRules), line:682:16, endln:682:26 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 |UINT:16 |vpiTypespec: \_int_typespec: @@ -122921,7 +122921,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.i_ariane.ex_stage_i.PPN4K_WIDTH), line:1293:16, endln:1293:27 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 |UINT:38 |vpiTypespec: \_int_typespec: @@ -122934,7 +122934,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.i_ariane.ex_stage_i.REG_ADDR_SIZE), line:870:16, endln:870:29 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 |UINT:6 |vpiTypespec: \_int_typespec: @@ -122947,7 +122947,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.i_ariane.ex_stage_i.RVA), line:816:20, endln:816:23 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 |BIN:1 |vpiTypespec: \_bit_typespec: , line:816:16, endln:816:19 @@ -122963,7 +122963,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.i_ariane.ex_stage_i.RVD), line:814:20, endln:814:23 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 |INT:1 |vpiTypespec: \_bit_typespec: , line:814:16, endln:814:19 @@ -122979,7 +122979,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.i_ariane.ex_stage_i.RVF), line:813:20, endln:813:23 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 |INT:1 |vpiTypespec: \_bit_typespec: , line:813:16, endln:813:19 @@ -122995,7 +122995,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.i_ariane.ex_stage_i.RVFVEC), line:848:20, endln:848:26 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 |UINT:0 |vpiTypespec: \_bit_typespec: , line:848:16, endln:848:19 @@ -123011,7 +123011,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.i_ariane.ex_stage_i.SMODE_STATUS_READ_MASK), line:905:29, endln:905:51 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 |vpiTypespec: \_logic_typespec: , line:905:16, endln:905:28 |vpiParent: @@ -123045,7 +123045,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.i_ariane.ex_stage_i.SMODE_STATUS_WRITE_MASK), line:918:29, endln:918:52 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 |vpiTypespec: \_logic_typespec: , line:918:16, endln:918:28 |vpiParent: @@ -123079,7 +123079,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.i_ariane.ex_stage_i.SupervisorIrq), line:1013:16, endln:1013:29 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 |UINT:1 |vpiTypespec: \_int_typespec: @@ -123092,7 +123092,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.i_ariane.ex_stage_i.TRANS_ID_BITS), line:780:16, endln:780:29 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 |UINT:3 |vpiTypespec: \_int_typespec: @@ -123105,7 +123105,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.i_ariane.ex_stage_i.XF16), line:819:20, endln:819:24 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 |BIN:0 |vpiTypespec: \_bit_typespec: , line:819:16, endln:819:19 @@ -123121,7 +123121,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.i_ariane.ex_stage_i.XF16ALT), line:820:20, endln:820:27 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 |BIN:0 |vpiTypespec: \_bit_typespec: , line:820:16, endln:820:19 @@ -123137,7 +123137,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.i_ariane.ex_stage_i.XF16ALTVEC), line:850:20, endln:850:30 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 |UINT:0 |vpiTypespec: \_bit_typespec: , line:850:16, endln:850:19 @@ -123153,7 +123153,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.i_ariane.ex_stage_i.XF16VEC), line:849:20, endln:849:27 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 |UINT:0 |vpiTypespec: \_bit_typespec: , line:849:16, endln:849:19 @@ -123169,7 +123169,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.i_ariane.ex_stage_i.XF8), line:821:20, endln:821:23 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 |BIN:0 |vpiTypespec: \_bit_typespec: , line:821:16, endln:821:19 @@ -123185,7 +123185,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.i_ariane.ex_stage_i.XF8VEC), line:851:20, endln:851:26 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 |UINT:0 |vpiTypespec: \_bit_typespec: , line:851:16, endln:851:19 @@ -123201,7 +123201,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.i_ariane.ex_stage_i.XFVEC), line:822:20, endln:822:25 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 |BIN:0 |vpiTypespec: \_bit_typespec: , line:822:16, endln:822:19 @@ -123217,7 +123217,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.i_ariane.ex_stage_i.ZERO_TVAL), line:902:20, endln:902:29 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 |BIN:0 |vpiTypespec: \_bit_typespec: , line:902:16, endln:902:19 @@ -123233,7 +123233,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.i_ariane.ex_stage_i.ASID_WIDTH), line:2082:28, endln:2082:38 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 |UINT:1 |vpiTypespec: \_int_typespec: , line:2082:15, endln:2082:27 @@ -123244,7 +123244,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.i_ariane.ex_stage_i.ArianeCfg), line:2083:40, endln:2083:49 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 |vpiTypespec: \_struct_typespec: (ariane_pkg::ariane_cfg_t), line:684:13, endln:684:19 |vpiParent: @@ -123779,7 +123779,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:2082:28, endln:2082:42 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 |vpiOverriden:1 |vpiRhs: \_constant: , line:2082:41, endln:2082:42 @@ -123794,7 +123794,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:2083:40, endln:2083:83 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 |vpiOverriden:1 |vpiRhs: \_ref_obj: (ariane_soc::ArianeSocCfg), line:2119:19, endln:2119:28 @@ -123806,7 +123806,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:682:16, endln:682:31 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 |vpiRhs: \_constant: , line:682:29, endln:682:31 |vpiDecompile:16 @@ -123820,7 +123820,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:706:29, endln:728:6 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 |vpiRhs: \_operation: , line:706:51, endln:728:6 |vpiParent: @@ -124482,7 +124482,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:779:16, endln:779:33 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 |vpiRhs: \_constant: , line:779:32, endln:779:33 |vpiDecompile:8 @@ -124496,7 +124496,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:780:16, endln:780:53 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 |vpiRhs: \_constant: , line:780:32, endln:780:53 |vpiDecompile:3 @@ -124510,7 +124510,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:782:16, endln:782:60 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 |vpiOverriden:1 |vpiRhs: \_constant: , line:782:32, endln:782:60 @@ -124525,7 +124525,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:783:16, endln:783:43 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 |vpiRhs: \_constant: , line:783:42, endln:783:43 |vpiDecompile:2 @@ -124539,7 +124539,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:784:16, endln:784:35 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 |vpiRhs: \_constant: , line:784:34, endln:784:35 |vpiDecompile:2 @@ -124553,7 +124553,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:786:16, endln:786:36 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 |vpiRhs: \_constant: , line:786:32, endln:786:36 |vpiDecompile:1'b0 @@ -124567,7 +124567,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:788:16, endln:788:31 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 |vpiRhs: \_constant: , line:788:30, endln:788:31 |vpiDecompile:1 @@ -124581,7 +124581,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:791:29, endln:791:50 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 |vpiRhs: \_constant: , line:791:49, endln:791:50 |vpiDecompile:1 @@ -124595,7 +124595,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:792:29, endln:792:51 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 |vpiRhs: \_constant: , line:792:50, endln:792:51 |vpiDecompile:0 @@ -124609,7 +124609,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:795:29, endln:795:45 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 |vpiRhs: \_constant: , line:795:44, endln:795:45 |vpiDecompile:4 @@ -124623,7 +124623,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:804:29, endln:804:45 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 |vpiRhs: \_constant: , line:804:44, endln:804:45 |vpiDecompile:8 @@ -124637,7 +124637,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:813:20, endln:813:42 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 |vpiRhs: \_constant: , line:813:26, endln:813:42 |vpiDecompile:1 @@ -124651,7 +124651,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:814:20, endln:814:42 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 |vpiRhs: \_constant: , line:814:26, endln:814:42 |vpiDecompile:1 @@ -124665,7 +124665,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:816:20, endln:816:30 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 |vpiRhs: \_constant: , line:816:26, endln:816:30 |vpiDecompile:1'b1 @@ -124679,7 +124679,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:819:20, endln:819:34 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 |vpiRhs: \_constant: , line:819:30, endln:819:34 |vpiDecompile:1'b0 @@ -124693,7 +124693,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:820:20, endln:820:34 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 |vpiRhs: \_constant: , line:820:30, endln:820:34 |vpiDecompile:1'b0 @@ -124707,7 +124707,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:821:20, endln:821:34 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 |vpiRhs: \_constant: , line:821:30, endln:821:34 |vpiDecompile:1'b0 @@ -124721,7 +124721,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:822:20, endln:822:34 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 |vpiRhs: \_constant: , line:822:30, endln:822:34 |vpiDecompile:1'b0 @@ -124735,7 +124735,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:825:29, endln:825:51 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 |vpiRhs: \_constant: , line:825:48, endln:825:51 |vpiDecompile:2 @@ -124749,7 +124749,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:826:29, endln:826:51 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 |vpiRhs: \_constant: , line:826:48, endln:826:51 |vpiDecompile:3 @@ -124763,7 +124763,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:827:29, endln:827:51 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 |vpiRhs: \_constant: , line:827:48, endln:827:51 |vpiDecompile:1 @@ -124777,7 +124777,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:828:29, endln:828:51 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 |vpiRhs: \_constant: , line:828:48, endln:828:51 |vpiDecompile:1 @@ -124791,7 +124791,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:829:29, endln:829:51 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 |vpiRhs: \_constant: , line:829:48, endln:829:51 |vpiDecompile:1 @@ -124805,7 +124805,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:830:29, endln:830:51 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 |vpiRhs: \_constant: , line:830:48, endln:830:51 |vpiDecompile:2 @@ -124819,7 +124819,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:831:29, endln:831:51 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 |vpiRhs: \_constant: , line:831:48, endln:831:51 |vpiDecompile:1 @@ -124833,7 +124833,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:832:29, endln:832:51 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 |vpiRhs: \_constant: , line:832:48, endln:832:51 |vpiDecompile:2 @@ -124847,7 +124847,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:836:20, endln:836:65 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 |vpiRhs: \_constant: , line:836:33, endln:836:65 |vpiDecompile:1 @@ -124861,7 +124861,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:839:16, endln:844:27 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 |vpiRhs: \_constant: , line:839:26, endln:844:27 |vpiDecompile:64 @@ -124875,7 +124875,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:846:20, endln:846:54 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 |vpiRhs: \_constant: , line:846:26, endln:846:54 |vpiDecompile:0 @@ -124889,7 +124889,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:848:20, endln:848:58 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 |vpiRhs: \_constant: , line:848:33, endln:848:58 |vpiDecompile:0 @@ -124903,7 +124903,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:849:20, endln:849:58 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 |vpiRhs: \_constant: , line:849:33, endln:849:58 |vpiDecompile:0 @@ -124917,7 +124917,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:850:20, endln:850:58 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 |vpiRhs: \_constant: , line:850:33, endln:850:58 |vpiDecompile:0 @@ -124931,7 +124931,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:851:20, endln:851:57 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 |vpiRhs: \_constant: , line:851:33, endln:851:57 |vpiDecompile:0 @@ -124945,7 +124945,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:855:30, endln:855:78 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 |vpiRhs: \_operation: , line:855:47, endln:855:78 |vpiTypespec: @@ -125032,7 +125032,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:857:30, endln:867:86 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 |vpiRhs: \_operation: , line:857:41, endln:867:86 |vpiTypespec: @@ -125395,7 +125395,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:870:16, endln:870:33 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 |vpiRhs: \_constant: , line:870:32, endln:870:33 |vpiDecompile:6 @@ -125409,7 +125409,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:871:16, endln:871:31 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 |vpiRhs: \_constant: , line:871:30, endln:871:31 |vpiDecompile:4 @@ -125423,7 +125423,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:874:31, endln:881:48 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 |vpiRhs: \_operation: , line:874:47, endln:881:48 |vpiParent: @@ -125532,7 +125532,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:884:20, endln:884:50 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 |vpiRhs: \_constant: , line:884:46, endln:884:50 |vpiDecompile:1'b1 @@ -125546,7 +125546,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:890:22, endln:890:48 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 |vpiRhs: \_constant: , line:890:44, endln:890:48 |vpiDecompile:1'b1 @@ -125560,7 +125560,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:900:20, endln:900:45 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 |vpiRhs: \_constant: , line:900:41, endln:900:45 |vpiDecompile:1'b1 @@ -125574,7 +125574,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:901:20, endln:901:37 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 |vpiRhs: \_constant: , line:901:33, endln:901:37 |vpiDecompile:1'b1 @@ -125588,7 +125588,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:902:20, endln:902:36 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 |vpiRhs: \_constant: , line:902:32, endln:902:36 |vpiDecompile:1'b0 @@ -125602,7 +125602,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:905:29, endln:916:71 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 |vpiRhs: \_operation: , line:905:54, endln:916:71 |vpiTypespec: @@ -126098,7 +126098,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:918:29, endln:923:73 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 |vpiRhs: \_operation: , line:918:55, endln:923:73 |vpiTypespec: @@ -126357,7 +126357,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:929:29, endln:929:50 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 |vpiRhs: \_constant: , line:929:49, endln:929:50 |vpiDecompile:4 @@ -126371,7 +126371,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:930:29, endln:930:51 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 |vpiRhs: \_constant: , line:930:49, endln:930:51 |vpiDecompile:32 @@ -126385,7 +126385,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:932:29, endln:932:63 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 |vpiRhs: \_constant: , line:932:47, endln:932:63 |vpiDecompile:2 @@ -126399,7 +126399,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:1011:16, endln:1011:40 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 |vpiRhs: \_constant: , line:1011:35, endln:1011:40 |vpiDecompile:8'h80 @@ -126413,7 +126413,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:1013:16, endln:1013:33 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 |vpiRhs: \_constant: , line:1013:32, endln:1013:33 |vpiDecompile:1 @@ -126427,7 +126427,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:1014:16, endln:1014:30 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 |vpiRhs: \_constant: , line:1014:29, endln:1014:30 |vpiDecompile:0 @@ -126441,7 +126441,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:1069:27, endln:1069:55 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 |vpiRhs: \_constant: , line:1069:48, endln:1069:55 |vpiDecompile:16384 @@ -126455,7 +126455,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:1070:29, endln:1070:51 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 |vpiRhs: \_constant: , line:1070:50, endln:1070:51 |vpiDecompile:4 @@ -126469,7 +126469,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:1071:29, endln:1071:92 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 |vpiRhs: \_constant: , line:1071:50, endln:1071:92 |vpiDecompile:12 @@ -126483,7 +126483,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:1072:29, endln:1072:80 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 |vpiRhs: \_constant: , line:1072:50, endln:1072:80 |vpiDecompile:44 @@ -126497,7 +126497,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:1073:29, endln:1073:53 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 |vpiRhs: \_constant: , line:1073:50, endln:1073:53 |vpiDecompile:128 @@ -126511,7 +126511,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:1075:27, endln:1075:55 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 |vpiRhs: \_constant: , line:1075:48, endln:1075:55 |vpiDecompile:32768 @@ -126525,7 +126525,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:1076:28, endln:1076:50 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 |vpiRhs: \_constant: , line:1076:49, endln:1076:50 |vpiDecompile:8 @@ -126539,7 +126539,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:1077:29, endln:1077:92 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 |vpiRhs: \_constant: , line:1077:50, endln:1077:92 |vpiDecompile:12 @@ -126553,7 +126553,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:1078:29, endln:1078:80 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 |vpiRhs: \_constant: , line:1078:50, endln:1078:80 |vpiDecompile:44 @@ -126567,7 +126567,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:1079:29, endln:1079:53 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 |vpiRhs: \_constant: , line:1079:50, endln:1079:53 |vpiDecompile:128 @@ -126581,7 +126581,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:1293:16, endln:1293:32 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 |vpiRhs: \_constant: , line:1293:30, endln:1293:32 |vpiDecompile:38 @@ -126656,13 +126656,13 @@ design: (work@top) |vpiTaskFunc: \_function: (ariane_pkg::check_cfg), line:731:5, endln:743:16 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 |vpiName:check_cfg |vpiFullName:ariane_pkg::check_cfg |vpiVisibility:1 |vpiAutomatic:1 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 |vpiIODecl: \_io_decl: (Cfg), line:731:53, endln:731:56 |vpiParent: @@ -126963,11 +126963,11 @@ design: (work@top) |vpiOperand: \_constant: , line:740:36, endln:740:38 |vpiInstance: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 |vpiTaskFunc: \_function: (ariane_pkg::range_check), line:745:5, endln:748:30 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 |vpiName:range_check |vpiFullName:ariane_pkg::range_check |vpiVisibility:1 @@ -126975,7 +126975,7 @@ design: (work@top) |vpiReturn: \_logic_var: , line:745:24, endln:745:29 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 |vpiIODecl: \_io_decl: (base), line:745:54, endln:745:58 |vpiParent: @@ -127065,11 +127065,11 @@ design: (work@top) |vpiActual: \_io_decl: (len), line:745:72, endln:745:75 |vpiInstance: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 |vpiTaskFunc: \_function: (ariane_pkg::is_inside_nonidempotent_regions), line:750:5, endln:757:50 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 |vpiName:is_inside_nonidempotent_regions |vpiFullName:ariane_pkg::is_inside_nonidempotent_regions |vpiVariables: @@ -127085,7 +127085,7 @@ design: (work@top) |vpiReturn: \_logic_var: , line:750:24, endln:750:29 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 |vpiIODecl: \_io_decl: (Cfg), line:750:76, endln:750:79 |vpiParent: @@ -127329,11 +127329,11 @@ design: (work@top) |vpiActual: \_logic_var: (ariane_pkg::is_inside_nonidempotent_regions::pass), line:751:29, endln:751:33 |vpiInstance: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 |vpiTaskFunc: \_function: (ariane_pkg::is_inside_execute_regions), line:759:5, endln:767:44 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 |vpiName:is_inside_execute_regions |vpiFullName:ariane_pkg::is_inside_execute_regions |vpiVariables: @@ -127349,7 +127349,7 @@ design: (work@top) |vpiReturn: \_logic_var: , line:759:24, endln:759:29 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 |vpiIODecl: \_io_decl: (Cfg), line:759:70, endln:759:73 |vpiParent: @@ -127593,11 +127593,11 @@ design: (work@top) |vpiActual: \_logic_var: (ariane_pkg::is_inside_execute_regions::pass), line:761:29, endln:761:33 |vpiInstance: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 |vpiTaskFunc: \_function: (ariane_pkg::is_inside_cacheable_regions), line:769:5, endln:776:46 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 |vpiName:is_inside_cacheable_regions |vpiFullName:ariane_pkg::is_inside_cacheable_regions |vpiVariables: @@ -127614,7 +127614,7 @@ design: (work@top) |vpiReturn: \_logic_var: , line:769:24, endln:769:29 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 |vpiIODecl: \_io_decl: (Cfg), line:769:72, endln:769:75 |vpiParent: @@ -127859,11 +127859,11 @@ design: (work@top) |vpiActual: \_logic_var: (ariane_pkg::is_inside_cacheable_regions::pass), line:770:39, endln:770:43 |vpiInstance: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 |vpiTaskFunc: \_function: (ariane_pkg::op_is_branch), line:1132:5, endln:1137:16 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 |vpiName:op_is_branch |vpiFullName:ariane_pkg::op_is_branch |vpiVisibility:1 @@ -127871,7 +127871,7 @@ design: (work@top) |vpiReturn: \_logic_var: , line:1132:24, endln:1132:29 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 |vpiIODecl: \_io_decl: (op), line:1132:56, endln:1132:58 |vpiParent: @@ -127998,11 +127998,11 @@ design: (work@top) |vpiCondition: \_constant: , line:1135:48, endln:1135:52 |vpiInstance: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 |vpiTaskFunc: \_function: (ariane_pkg::is_rs1_fpr), line:1142:5, endln:1157:16 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 |vpiName:is_rs1_fpr |vpiFullName:ariane_pkg::is_rs1_fpr |vpiVisibility:1 @@ -128010,7 +128010,7 @@ design: (work@top) |vpiReturn: \_logic_var: , line:1142:24, endln:1142:29 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 |vpiIODecl: \_io_decl: (op), line:1142:54, endln:1142:56 |vpiParent: @@ -128202,11 +128202,11 @@ design: (work@top) |vpiCondition: \_constant: , line:1156:20, endln:1156:24 |vpiInstance: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 |vpiTaskFunc: \_function: (ariane_pkg::is_rs2_fpr), line:1159:5, endln:1173:16 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 |vpiName:is_rs2_fpr |vpiFullName:ariane_pkg::is_rs2_fpr |vpiVisibility:1 @@ -128214,7 +128214,7 @@ design: (work@top) |vpiReturn: \_logic_var: , line:1159:24, endln:1159:29 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 |vpiIODecl: \_io_decl: (op), line:1159:54, endln:1159:56 |vpiParent: @@ -128417,11 +128417,11 @@ design: (work@top) |vpiCondition: \_constant: , line:1172:20, endln:1172:24 |vpiInstance: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 |vpiTaskFunc: \_function: (ariane_pkg::is_imm_fpr), line:1176:5, endln:1186:16 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 |vpiName:is_imm_fpr |vpiFullName:ariane_pkg::is_imm_fpr |vpiVisibility:1 @@ -128429,7 +128429,7 @@ design: (work@top) |vpiReturn: \_logic_var: , line:1176:24, endln:1176:29 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 |vpiIODecl: \_io_decl: (op), line:1176:54, endln:1176:56 |vpiParent: @@ -128564,11 +128564,11 @@ design: (work@top) |vpiCondition: \_constant: , line:1185:20, endln:1185:24 |vpiInstance: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 |vpiTaskFunc: \_function: (ariane_pkg::is_rd_fpr), line:1188:5, endln:1203:16 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 |vpiName:is_rd_fpr |vpiFullName:ariane_pkg::is_rd_fpr |vpiVisibility:1 @@ -128576,7 +128576,7 @@ design: (work@top) |vpiReturn: \_logic_var: , line:1188:24, endln:1188:29 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 |vpiIODecl: \_io_decl: (op), line:1188:53, endln:1188:55 |vpiParent: @@ -128784,11 +128784,11 @@ design: (work@top) |vpiCondition: \_constant: , line:1202:20, endln:1202:24 |vpiInstance: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 |vpiTaskFunc: \_function: (ariane_pkg::is_amo), line:1205:5, endln:1212:16 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 |vpiName:is_amo |vpiFullName:ariane_pkg::is_amo |vpiVisibility:1 @@ -128796,7 +128796,7 @@ design: (work@top) |vpiReturn: \_logic_var: , line:1205:24, endln:1205:29 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 |vpiIODecl: \_io_decl: (op), line:1205:44, endln:1205:46 |vpiParent: @@ -128870,11 +128870,11 @@ design: (work@top) |vpiCondition: \_constant: , line:1210:29, endln:1210:33 |vpiInstance: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 |vpiTaskFunc: \_function: (ariane_pkg::sext32), line:1373:5, endln:1375:16 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 |vpiName:sext32 |vpiFullName:ariane_pkg::sext32 |vpiVisibility:1 @@ -128882,7 +128882,7 @@ design: (work@top) |vpiReturn: \_logic_var: , line:1373:24, endln:1373:37 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 |vpiIODecl: \_io_decl: (operand), line:1373:59, endln:1373:66 |vpiParent: @@ -128952,11 +128952,11 @@ design: (work@top) |vpiRightRange: \_constant: , line:1374:59, endln:1374:60 |vpiInstance: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 |vpiTaskFunc: \_function: (ariane_pkg::uj_imm), line:1380:5, endln:1382:16 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 |vpiName:uj_imm |vpiFullName:ariane_pkg::uj_imm |vpiVisibility:1 @@ -128964,7 +128964,7 @@ design: (work@top) |vpiReturn: \_logic_var: , line:1380:24, endln:1380:47 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 |vpiIODecl: \_io_decl: (instruction_i), line:1380:69, endln:1380:82 |vpiParent: @@ -129075,11 +129075,11 @@ design: (work@top) |vpiOperand: \_constant: , line:1381:122, endln:1381:126 |vpiInstance: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 |vpiTaskFunc: \_function: (ariane_pkg::i_imm), line:1384:5, endln:1386:16 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 |vpiName:i_imm |vpiFullName:ariane_pkg::i_imm |vpiVisibility:1 @@ -129087,7 +129087,7 @@ design: (work@top) |vpiReturn: \_logic_var: , line:1384:24, endln:1384:47 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 |vpiIODecl: \_io_decl: (instruction_i), line:1384:68, endln:1384:81 |vpiParent: @@ -129164,11 +129164,11 @@ design: (work@top) |vpiRightRange: \_constant: , line:1385:76, endln:1385:78 |vpiInstance: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 |vpiTaskFunc: \_function: (ariane_pkg::sb_imm), line:1388:5, endln:1390:16 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 |vpiName:sb_imm |vpiFullName:ariane_pkg::sb_imm |vpiVisibility:1 @@ -129176,7 +129176,7 @@ design: (work@top) |vpiReturn: \_logic_var: , line:1388:24, endln:1388:47 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 |vpiIODecl: \_io_decl: (instruction_i), line:1388:69, endln:1388:82 |vpiParent: @@ -129303,11 +129303,11 @@ design: (work@top) |vpiOperand: \_constant: , line:1389:139, endln:1389:143 |vpiInstance: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 |vpiTaskFunc: \_function: (ariane_pkg::data_align), line:1396:5, endln:1411:16 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 |vpiName:data_align |vpiFullName:ariane_pkg::data_align |vpiVariables: @@ -129331,7 +129331,7 @@ design: (work@top) |vpiReturn: \_logic_var: , line:1396:24, endln:1396:37 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 |vpiIODecl: \_io_decl: (addr), line:1396:62, endln:1396:66 |vpiParent: @@ -130062,11 +130062,11 @@ design: (work@top) |vpiRightRange: \_constant: , line:1410:39, endln:1410:40 |vpiInstance: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 |vpiTaskFunc: \_function: (ariane_pkg::be_gen), line:1414:5, endln:1453:16 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 |vpiName:be_gen |vpiFullName:ariane_pkg::be_gen |vpiVisibility:1 @@ -130074,7 +130074,7 @@ design: (work@top) |vpiReturn: \_logic_var: , line:1414:24, endln:1414:35 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 |vpiIODecl: \_io_decl: (addr), line:1414:55, endln:1414:59 |vpiParent: @@ -130469,11 +130469,11 @@ design: (work@top) |vpiCondition: \_constant: , line:1452:16, endln:1452:20 |vpiInstance: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 |vpiTaskFunc: \_function: (ariane_pkg::extract_transfer_size), line:1458:5, endln:1482:16 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 |vpiName:extract_transfer_size |vpiFullName:ariane_pkg::extract_transfer_size |vpiVisibility:1 @@ -130481,7 +130481,7 @@ design: (work@top) |vpiReturn: \_logic_var: , line:1458:24, endln:1458:35 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 |vpiIODecl: \_io_decl: (op), line:1458:64, endln:1458:66 |vpiParent: @@ -130892,13 +130892,13 @@ design: (work@top) |vpiCondition: \_constant: , line:1480:33, endln:1480:38 |vpiInstance: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 |vpiInstance: - \_module: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 + \_module_inst: work@ariane (work@top.i_ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2126:5, endln:2128:21 |vpiGenScopeArray: \_gen_scope_array: (work@top.i_ariane.ex_stage_i.fpu_gen), line:2087:9, endln:2107:5 |vpiParent: - \_module: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 + \_module_inst: work@ex_stage (work@top.i_ariane.ex_stage_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2117:3, endln:2120:23 |vpiName:fpu_gen |vpiFullName:work@top.i_ariane.ex_stage_i.fpu_gen |vpiGenScope: @@ -131043,8 +131043,8 @@ design: (work@top) |vpiFullName:work@top.i_ariane.ex_stage_i.fpu_gen.fpu_data |vpiActual: \_struct_var: (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_data), line:2088:23, endln:2088:31 - |vpiModule: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 + |vpiModuleInst: + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 |vpiParent: \_gen_scope: (work@top.i_ariane.ex_stage_i.fpu_gen) |vpiName:fpu_i @@ -132627,7 +132627,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:682:16, endln:682:31 |vpiParent: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 |vpiRhs: \_constant: , line:682:29, endln:682:31 |vpiDecompile:16 @@ -132641,7 +132641,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:706:29, endln:728:6 |vpiParent: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 |vpiRhs: \_operation: , line:706:51, endln:728:6 |vpiParent: @@ -133303,7 +133303,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:779:16, endln:779:33 |vpiParent: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 |vpiRhs: \_constant: , line:779:32, endln:779:33 |vpiDecompile:8 @@ -133317,7 +133317,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:780:16, endln:780:53 |vpiParent: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 |vpiRhs: \_constant: , line:780:32, endln:780:53 |vpiDecompile:3 @@ -133331,7 +133331,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:782:16, endln:782:60 |vpiParent: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 |vpiRhs: \_constant: , line:782:32, endln:782:60 |vpiDecompile:16 @@ -133345,7 +133345,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:783:16, endln:783:43 |vpiParent: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 |vpiRhs: \_constant: , line:783:42, endln:783:43 |vpiDecompile:2 @@ -133359,7 +133359,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:784:16, endln:784:35 |vpiParent: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 |vpiRhs: \_constant: , line:784:34, endln:784:35 |vpiDecompile:2 @@ -133373,7 +133373,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:786:16, endln:786:36 |vpiParent: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 |vpiRhs: \_constant: , line:786:32, endln:786:36 |vpiDecompile:1'b0 @@ -133387,7 +133387,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:788:16, endln:788:31 |vpiParent: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 |vpiRhs: \_constant: , line:788:30, endln:788:31 |vpiDecompile:1 @@ -133401,7 +133401,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:791:29, endln:791:50 |vpiParent: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 |vpiRhs: \_constant: , line:791:49, endln:791:50 |vpiDecompile:1 @@ -133415,7 +133415,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:792:29, endln:792:51 |vpiParent: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 |vpiRhs: \_constant: , line:792:50, endln:792:51 |vpiDecompile:0 @@ -133429,7 +133429,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:795:29, endln:795:45 |vpiParent: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 |vpiRhs: \_constant: , line:795:44, endln:795:45 |vpiDecompile:4 @@ -133443,7 +133443,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:804:29, endln:804:45 |vpiParent: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 |vpiRhs: \_constant: , line:804:44, endln:804:45 |vpiDecompile:8 @@ -133457,7 +133457,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:813:20, endln:813:42 |vpiParent: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 |vpiRhs: \_constant: , line:813:26, endln:813:42 |vpiDecompile:1 @@ -133471,7 +133471,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:814:20, endln:814:42 |vpiParent: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 |vpiRhs: \_constant: , line:814:26, endln:814:42 |vpiDecompile:1 @@ -133485,7 +133485,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:816:20, endln:816:30 |vpiParent: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 |vpiRhs: \_constant: , line:816:26, endln:816:30 |vpiDecompile:1'b1 @@ -133499,7 +133499,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:819:20, endln:819:34 |vpiParent: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 |vpiRhs: \_constant: , line:819:30, endln:819:34 |vpiDecompile:1'b0 @@ -133513,7 +133513,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:820:20, endln:820:34 |vpiParent: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 |vpiRhs: \_constant: , line:820:30, endln:820:34 |vpiDecompile:1'b0 @@ -133527,7 +133527,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:821:20, endln:821:34 |vpiParent: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 |vpiRhs: \_constant: , line:821:30, endln:821:34 |vpiDecompile:1'b0 @@ -133541,7 +133541,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:822:20, endln:822:34 |vpiParent: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 |vpiRhs: \_constant: , line:822:30, endln:822:34 |vpiDecompile:1'b0 @@ -133555,7 +133555,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:825:29, endln:825:51 |vpiParent: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 |vpiRhs: \_constant: , line:825:48, endln:825:51 |vpiDecompile:2 @@ -133569,7 +133569,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:826:29, endln:826:51 |vpiParent: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 |vpiRhs: \_constant: , line:826:48, endln:826:51 |vpiDecompile:3 @@ -133583,7 +133583,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:827:29, endln:827:51 |vpiParent: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 |vpiRhs: \_constant: , line:827:48, endln:827:51 |vpiDecompile:1 @@ -133597,7 +133597,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:828:29, endln:828:51 |vpiParent: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 |vpiRhs: \_constant: , line:828:48, endln:828:51 |vpiDecompile:1 @@ -133611,7 +133611,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:829:29, endln:829:51 |vpiParent: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 |vpiRhs: \_constant: , line:829:48, endln:829:51 |vpiDecompile:1 @@ -133625,7 +133625,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:830:29, endln:830:51 |vpiParent: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 |vpiRhs: \_constant: , line:830:48, endln:830:51 |vpiDecompile:2 @@ -133639,7 +133639,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:831:29, endln:831:51 |vpiParent: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 |vpiRhs: \_constant: , line:831:48, endln:831:51 |vpiDecompile:1 @@ -133653,7 +133653,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:832:29, endln:832:51 |vpiParent: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 |vpiRhs: \_constant: , line:832:48, endln:832:51 |vpiDecompile:2 @@ -133667,7 +133667,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:836:20, endln:836:65 |vpiParent: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 |vpiRhs: \_constant: , line:836:33, endln:836:65 |vpiDecompile:1 @@ -133681,7 +133681,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:839:16, endln:844:27 |vpiParent: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 |vpiRhs: \_constant: , line:839:26, endln:844:27 |vpiDecompile:64 @@ -133695,7 +133695,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:846:20, endln:846:54 |vpiParent: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 |vpiRhs: \_constant: , line:846:26, endln:846:54 |vpiDecompile:0 @@ -133709,7 +133709,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:848:20, endln:848:58 |vpiParent: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 |vpiRhs: \_constant: , line:848:33, endln:848:58 |vpiDecompile:0 @@ -133723,7 +133723,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:849:20, endln:849:58 |vpiParent: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 |vpiRhs: \_constant: , line:849:33, endln:849:58 |vpiDecompile:0 @@ -133737,7 +133737,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:850:20, endln:850:58 |vpiParent: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 |vpiRhs: \_constant: , line:850:33, endln:850:58 |vpiDecompile:0 @@ -133751,7 +133751,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:851:20, endln:851:57 |vpiParent: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 |vpiRhs: \_constant: , line:851:33, endln:851:57 |vpiDecompile:0 @@ -133765,7 +133765,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:855:30, endln:855:78 |vpiParent: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 |vpiRhs: \_operation: , line:855:47, endln:855:78 |vpiParent: @@ -133854,7 +133854,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:857:30, endln:867:86 |vpiParent: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 |vpiRhs: \_operation: , line:857:41, endln:867:86 |vpiParent: @@ -134223,7 +134223,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:870:16, endln:870:33 |vpiParent: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 |vpiRhs: \_constant: , line:870:32, endln:870:33 |vpiDecompile:6 @@ -134237,7 +134237,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:871:16, endln:871:31 |vpiParent: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 |vpiRhs: \_constant: , line:871:30, endln:871:31 |vpiDecompile:4 @@ -134251,7 +134251,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:874:31, endln:881:48 |vpiParent: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 |vpiRhs: \_operation: , line:874:47, endln:881:48 |vpiParent: @@ -134360,7 +134360,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:884:20, endln:884:50 |vpiParent: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 |vpiRhs: \_constant: , line:884:46, endln:884:50 |vpiDecompile:1'b1 @@ -134374,7 +134374,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:890:22, endln:890:48 |vpiParent: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 |vpiRhs: \_constant: , line:890:44, endln:890:48 |vpiDecompile:1'b1 @@ -134388,7 +134388,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:900:20, endln:900:45 |vpiParent: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 |vpiRhs: \_constant: , line:900:41, endln:900:45 |vpiDecompile:1'b1 @@ -134402,7 +134402,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:901:20, endln:901:37 |vpiParent: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 |vpiRhs: \_constant: , line:901:33, endln:901:37 |vpiDecompile:1'b1 @@ -134416,7 +134416,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:902:20, endln:902:36 |vpiParent: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 |vpiRhs: \_constant: , line:902:32, endln:902:36 |vpiDecompile:1'b0 @@ -134430,7 +134430,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:905:29, endln:916:71 |vpiParent: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 |vpiRhs: \_operation: , line:905:54, endln:916:71 |vpiParent: @@ -134930,7 +134930,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:918:29, endln:923:73 |vpiParent: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 |vpiRhs: \_operation: , line:918:55, endln:923:73 |vpiParent: @@ -135191,7 +135191,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:929:29, endln:929:50 |vpiParent: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 |vpiRhs: \_constant: , line:929:49, endln:929:50 |vpiDecompile:4 @@ -135205,7 +135205,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:930:29, endln:930:51 |vpiParent: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 |vpiRhs: \_constant: , line:930:49, endln:930:51 |vpiDecompile:32 @@ -135219,7 +135219,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:932:29, endln:932:63 |vpiParent: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 |vpiRhs: \_constant: , line:932:47, endln:932:63 |vpiDecompile:2 @@ -135233,7 +135233,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:1011:16, endln:1011:40 |vpiParent: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 |vpiRhs: \_constant: , line:1011:35, endln:1011:40 |vpiDecompile:8'h80 @@ -135247,7 +135247,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:1013:16, endln:1013:33 |vpiParent: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 |vpiRhs: \_constant: , line:1013:32, endln:1013:33 |vpiDecompile:1 @@ -135261,7 +135261,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:1014:16, endln:1014:30 |vpiParent: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 |vpiRhs: \_constant: , line:1014:29, endln:1014:30 |vpiDecompile:0 @@ -135275,7 +135275,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:1069:27, endln:1069:55 |vpiParent: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 |vpiRhs: \_constant: , line:1069:48, endln:1069:55 |vpiDecompile:16384 @@ -135289,7 +135289,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:1070:29, endln:1070:51 |vpiParent: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 |vpiRhs: \_constant: , line:1070:50, endln:1070:51 |vpiDecompile:4 @@ -135303,7 +135303,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:1071:29, endln:1071:92 |vpiParent: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 |vpiRhs: \_constant: , line:1071:50, endln:1071:92 |vpiDecompile:12 @@ -135317,7 +135317,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:1072:29, endln:1072:80 |vpiParent: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 |vpiRhs: \_constant: , line:1072:50, endln:1072:80 |vpiDecompile:44 @@ -135331,7 +135331,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:1073:29, endln:1073:53 |vpiParent: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 |vpiRhs: \_constant: , line:1073:50, endln:1073:53 |vpiDecompile:128 @@ -135345,7 +135345,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:1075:27, endln:1075:55 |vpiParent: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 |vpiRhs: \_constant: , line:1075:48, endln:1075:55 |vpiDecompile:32768 @@ -135359,7 +135359,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:1076:28, endln:1076:50 |vpiParent: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 |vpiRhs: \_constant: , line:1076:49, endln:1076:50 |vpiDecompile:8 @@ -135373,7 +135373,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:1077:29, endln:1077:92 |vpiParent: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 |vpiRhs: \_constant: , line:1077:50, endln:1077:92 |vpiDecompile:12 @@ -135387,7 +135387,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:1078:29, endln:1078:80 |vpiParent: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 |vpiRhs: \_constant: , line:1078:50, endln:1078:80 |vpiDecompile:44 @@ -135401,7 +135401,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:1079:29, endln:1079:53 |vpiParent: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 |vpiRhs: \_constant: , line:1079:50, endln:1079:53 |vpiDecompile:128 @@ -135415,7 +135415,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:1293:16, endln:1293:32 |vpiParent: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 |vpiRhs: \_constant: , line:1293:30, endln:1293:32 |vpiDecompile:38 @@ -135490,13 +135490,13 @@ design: (work@top) |vpiTaskFunc: \_function: (ariane_pkg::check_cfg), line:731:5, endln:743:16 |vpiParent: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 |vpiName:check_cfg |vpiFullName:ariane_pkg::check_cfg |vpiVisibility:1 |vpiAutomatic:1 |vpiParent: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 |vpiIODecl: \_io_decl: (Cfg), line:731:53, endln:731:56 |vpiParent: @@ -135797,11 +135797,11 @@ design: (work@top) |vpiOperand: \_constant: , line:740:36, endln:740:38 |vpiInstance: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 |vpiTaskFunc: \_function: (ariane_pkg::range_check), line:745:5, endln:748:30 |vpiParent: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 |vpiName:range_check |vpiFullName:ariane_pkg::range_check |vpiVisibility:1 @@ -135809,7 +135809,7 @@ design: (work@top) |vpiReturn: \_logic_var: , line:745:24, endln:745:29 |vpiParent: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 |vpiIODecl: \_io_decl: (base), line:745:54, endln:745:58 |vpiParent: @@ -135899,11 +135899,11 @@ design: (work@top) |vpiActual: \_io_decl: (len), line:745:72, endln:745:75 |vpiInstance: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 |vpiTaskFunc: \_function: (ariane_pkg::is_inside_nonidempotent_regions), line:750:5, endln:757:50 |vpiParent: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 |vpiName:is_inside_nonidempotent_regions |vpiFullName:ariane_pkg::is_inside_nonidempotent_regions |vpiVariables: @@ -135919,7 +135919,7 @@ design: (work@top) |vpiReturn: \_logic_var: , line:750:24, endln:750:29 |vpiParent: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 |vpiIODecl: \_io_decl: (Cfg), line:750:76, endln:750:79 |vpiParent: @@ -136169,11 +136169,11 @@ design: (work@top) |vpiActual: \_logic_var: (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.is_inside_nonidempotent_regions.pass), line:751:29, endln:751:33 |vpiInstance: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 |vpiTaskFunc: \_function: (ariane_pkg::is_inside_execute_regions), line:759:5, endln:767:44 |vpiParent: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 |vpiName:is_inside_execute_regions |vpiFullName:ariane_pkg::is_inside_execute_regions |vpiVariables: @@ -136189,7 +136189,7 @@ design: (work@top) |vpiReturn: \_logic_var: , line:759:24, endln:759:29 |vpiParent: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 |vpiIODecl: \_io_decl: (Cfg), line:759:70, endln:759:73 |vpiParent: @@ -136439,11 +136439,11 @@ design: (work@top) |vpiActual: \_logic_var: (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.is_inside_execute_regions.pass), line:761:29, endln:761:33 |vpiInstance: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 |vpiTaskFunc: \_function: (ariane_pkg::is_inside_cacheable_regions), line:769:5, endln:776:46 |vpiParent: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 |vpiName:is_inside_cacheable_regions |vpiFullName:ariane_pkg::is_inside_cacheable_regions |vpiVariables: @@ -136460,7 +136460,7 @@ design: (work@top) |vpiReturn: \_logic_var: , line:769:24, endln:769:29 |vpiParent: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 |vpiIODecl: \_io_decl: (Cfg), line:769:72, endln:769:75 |vpiParent: @@ -136712,11 +136712,11 @@ design: (work@top) |vpiActual: \_logic_var: (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.is_inside_cacheable_regions.pass), line:770:39, endln:770:43 |vpiInstance: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 |vpiTaskFunc: \_function: (ariane_pkg::op_is_branch), line:1132:5, endln:1137:16 |vpiParent: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 |vpiName:op_is_branch |vpiFullName:ariane_pkg::op_is_branch |vpiVisibility:1 @@ -136724,7 +136724,7 @@ design: (work@top) |vpiReturn: \_logic_var: , line:1132:24, endln:1132:29 |vpiParent: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 |vpiIODecl: \_io_decl: (op), line:1132:56, endln:1132:58 |vpiParent: @@ -136851,11 +136851,11 @@ design: (work@top) |vpiCondition: \_constant: , line:1135:48, endln:1135:52 |vpiInstance: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 |vpiTaskFunc: \_function: (ariane_pkg::is_rs1_fpr), line:1142:5, endln:1157:16 |vpiParent: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 |vpiName:is_rs1_fpr |vpiFullName:ariane_pkg::is_rs1_fpr |vpiVisibility:1 @@ -136863,7 +136863,7 @@ design: (work@top) |vpiReturn: \_logic_var: , line:1142:24, endln:1142:29 |vpiParent: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 |vpiIODecl: \_io_decl: (op), line:1142:54, endln:1142:56 |vpiParent: @@ -137055,11 +137055,11 @@ design: (work@top) |vpiCondition: \_constant: , line:1156:20, endln:1156:24 |vpiInstance: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 |vpiTaskFunc: \_function: (ariane_pkg::is_rs2_fpr), line:1159:5, endln:1173:16 |vpiParent: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 |vpiName:is_rs2_fpr |vpiFullName:ariane_pkg::is_rs2_fpr |vpiVisibility:1 @@ -137067,7 +137067,7 @@ design: (work@top) |vpiReturn: \_logic_var: , line:1159:24, endln:1159:29 |vpiParent: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 |vpiIODecl: \_io_decl: (op), line:1159:54, endln:1159:56 |vpiParent: @@ -137270,11 +137270,11 @@ design: (work@top) |vpiCondition: \_constant: , line:1172:20, endln:1172:24 |vpiInstance: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 |vpiTaskFunc: \_function: (ariane_pkg::is_imm_fpr), line:1176:5, endln:1186:16 |vpiParent: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 |vpiName:is_imm_fpr |vpiFullName:ariane_pkg::is_imm_fpr |vpiVisibility:1 @@ -137282,7 +137282,7 @@ design: (work@top) |vpiReturn: \_logic_var: , line:1176:24, endln:1176:29 |vpiParent: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 |vpiIODecl: \_io_decl: (op), line:1176:54, endln:1176:56 |vpiParent: @@ -137417,11 +137417,11 @@ design: (work@top) |vpiCondition: \_constant: , line:1185:20, endln:1185:24 |vpiInstance: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 |vpiTaskFunc: \_function: (ariane_pkg::is_rd_fpr), line:1188:5, endln:1203:16 |vpiParent: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 |vpiName:is_rd_fpr |vpiFullName:ariane_pkg::is_rd_fpr |vpiVisibility:1 @@ -137429,7 +137429,7 @@ design: (work@top) |vpiReturn: \_logic_var: , line:1188:24, endln:1188:29 |vpiParent: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 |vpiIODecl: \_io_decl: (op), line:1188:53, endln:1188:55 |vpiParent: @@ -137637,11 +137637,11 @@ design: (work@top) |vpiCondition: \_constant: , line:1202:20, endln:1202:24 |vpiInstance: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 |vpiTaskFunc: \_function: (ariane_pkg::is_amo), line:1205:5, endln:1212:16 |vpiParent: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 |vpiName:is_amo |vpiFullName:ariane_pkg::is_amo |vpiVisibility:1 @@ -137649,7 +137649,7 @@ design: (work@top) |vpiReturn: \_logic_var: , line:1205:24, endln:1205:29 |vpiParent: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 |vpiIODecl: \_io_decl: (op), line:1205:44, endln:1205:46 |vpiParent: @@ -137723,11 +137723,11 @@ design: (work@top) |vpiCondition: \_constant: , line:1210:29, endln:1210:33 |vpiInstance: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 |vpiTaskFunc: \_function: (ariane_pkg::sext32), line:1373:5, endln:1375:16 |vpiParent: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 |vpiName:sext32 |vpiFullName:ariane_pkg::sext32 |vpiVisibility:1 @@ -137735,7 +137735,7 @@ design: (work@top) |vpiReturn: \_logic_var: , line:1373:24, endln:1373:37 |vpiParent: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 |vpiIODecl: \_io_decl: (operand), line:1373:59, endln:1373:66 |vpiParent: @@ -137805,11 +137805,11 @@ design: (work@top) |vpiRightRange: \_constant: , line:1374:59, endln:1374:60 |vpiInstance: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 |vpiTaskFunc: \_function: (ariane_pkg::uj_imm), line:1380:5, endln:1382:16 |vpiParent: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 |vpiName:uj_imm |vpiFullName:ariane_pkg::uj_imm |vpiVisibility:1 @@ -137817,7 +137817,7 @@ design: (work@top) |vpiReturn: \_logic_var: , line:1380:24, endln:1380:47 |vpiParent: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 |vpiIODecl: \_io_decl: (instruction_i), line:1380:69, endln:1380:82 |vpiParent: @@ -137928,11 +137928,11 @@ design: (work@top) |vpiOperand: \_constant: , line:1381:122, endln:1381:126 |vpiInstance: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 |vpiTaskFunc: \_function: (ariane_pkg::i_imm), line:1384:5, endln:1386:16 |vpiParent: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 |vpiName:i_imm |vpiFullName:ariane_pkg::i_imm |vpiVisibility:1 @@ -137940,7 +137940,7 @@ design: (work@top) |vpiReturn: \_logic_var: , line:1384:24, endln:1384:47 |vpiParent: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 |vpiIODecl: \_io_decl: (instruction_i), line:1384:68, endln:1384:81 |vpiParent: @@ -138017,11 +138017,11 @@ design: (work@top) |vpiRightRange: \_constant: , line:1385:76, endln:1385:78 |vpiInstance: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 |vpiTaskFunc: \_function: (ariane_pkg::sb_imm), line:1388:5, endln:1390:16 |vpiParent: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 |vpiName:sb_imm |vpiFullName:ariane_pkg::sb_imm |vpiVisibility:1 @@ -138029,7 +138029,7 @@ design: (work@top) |vpiReturn: \_logic_var: , line:1388:24, endln:1388:47 |vpiParent: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 |vpiIODecl: \_io_decl: (instruction_i), line:1388:69, endln:1388:82 |vpiParent: @@ -138156,11 +138156,11 @@ design: (work@top) |vpiOperand: \_constant: , line:1389:139, endln:1389:143 |vpiInstance: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 |vpiTaskFunc: \_function: (ariane_pkg::data_align), line:1396:5, endln:1411:16 |vpiParent: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 |vpiName:data_align |vpiFullName:ariane_pkg::data_align |vpiVariables: @@ -138184,7 +138184,7 @@ design: (work@top) |vpiReturn: \_logic_var: , line:1396:24, endln:1396:37 |vpiParent: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 |vpiIODecl: \_io_decl: (addr), line:1396:62, endln:1396:66 |vpiParent: @@ -138915,11 +138915,11 @@ design: (work@top) |vpiRightRange: \_constant: , line:1410:39, endln:1410:40 |vpiInstance: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 |vpiTaskFunc: \_function: (ariane_pkg::be_gen), line:1414:5, endln:1453:16 |vpiParent: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 |vpiName:be_gen |vpiFullName:ariane_pkg::be_gen |vpiVisibility:1 @@ -138927,7 +138927,7 @@ design: (work@top) |vpiReturn: \_logic_var: , line:1414:24, endln:1414:35 |vpiParent: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 |vpiIODecl: \_io_decl: (addr), line:1414:55, endln:1414:59 |vpiParent: @@ -139322,11 +139322,11 @@ design: (work@top) |vpiCondition: \_constant: , line:1452:16, endln:1452:20 |vpiInstance: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 |vpiTaskFunc: \_function: (ariane_pkg::extract_transfer_size), line:1458:5, endln:1482:16 |vpiParent: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 |vpiName:extract_transfer_size |vpiFullName:ariane_pkg::extract_transfer_size |vpiVisibility:1 @@ -139334,7 +139334,7 @@ design: (work@top) |vpiReturn: \_logic_var: , line:1458:24, endln:1458:35 |vpiParent: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 |vpiIODecl: \_io_decl: (op), line:1458:64, endln:1458:66 |vpiParent: @@ -139745,11 +139745,11 @@ design: (work@top) |vpiCondition: \_constant: , line:1480:33, endln:1480:38 |vpiInstance: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 |vpiPort: \_port: (clk_i), line:2092:18, endln:2092:23 |vpiParent: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 |vpiName:clk_i |vpiHighConn: \_ref_obj: (work@top.i_ariane.ex_stage_i.fpu_gen.clk_i), line:2092:18, endln:2092:23 @@ -139760,11 +139760,11 @@ design: (work@top) |vpiActual: \_logic_net: (work@top.i_ariane.ex_stage_i.fpu_gen.clk_i), line:2092:18, endln:2092:23 |vpiInstance: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 |vpiPort: \_port: (rst_ni), line:2093:18, endln:2093:24 |vpiParent: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 |vpiName:rst_ni |vpiHighConn: \_ref_obj: (work@top.i_ariane.ex_stage_i.fpu_gen.rst_ni), line:2093:18, endln:2093:24 @@ -139775,11 +139775,11 @@ design: (work@top) |vpiActual: \_logic_net: (work@top.i_ariane.ex_stage_i.fpu_gen.rst_ni), line:2093:18, endln:2093:24 |vpiInstance: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 |vpiPort: \_port: (flush_i), line:2094:18, endln:2094:25 |vpiParent: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 |vpiName:flush_i |vpiHighConn: \_ref_obj: (work@top.i_ariane.ex_stage_i.fpu_gen.flush_i), line:2094:18, endln:2094:25 @@ -139790,11 +139790,11 @@ design: (work@top) |vpiActual: \_logic_net: (work@top.i_ariane.ex_stage_i.fpu_gen.flush_i), line:2094:18, endln:2094:25 |vpiInstance: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 |vpiPort: \_port: (fpu_valid_i), line:2095:18, endln:2095:29 |vpiParent: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 |vpiName:fpu_valid_i |vpiHighConn: \_ref_obj: (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_valid_i), line:2095:18, endln:2095:29 @@ -139805,11 +139805,11 @@ design: (work@top) |vpiActual: \_logic_net: (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_valid_i), line:2095:18, endln:2095:29 |vpiInstance: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 |vpiPort: \_port: (fpu_ready_o), line:2096:18, endln:2096:29 |vpiParent: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 |vpiName:fpu_ready_o |vpiHighConn: \_ref_obj: (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_ready_o), line:2096:18, endln:2096:29 @@ -139820,11 +139820,11 @@ design: (work@top) |vpiActual: \_logic_net: (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_ready_o), line:2096:18, endln:2096:29 |vpiInstance: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 |vpiPort: \_port: (fu_data_i), line:2097:18, endln:2097:27 |vpiParent: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 |vpiName:fu_data_i |vpiHighConn: \_ref_obj: (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_data), line:2097:30, endln:2097:38 @@ -139835,11 +139835,11 @@ design: (work@top) |vpiActual: \_struct_var: (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_data), line:2088:23, endln:2088:31 |vpiInstance: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 |vpiPort: \_port: (fpu_fmt_i), line:2098:18, endln:2098:27 |vpiParent: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 |vpiName:fpu_fmt_i |vpiHighConn: \_ref_obj: (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_fmt_i), line:2098:18, endln:2098:27 @@ -139850,11 +139850,11 @@ design: (work@top) |vpiActual: \_logic_net: (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_fmt_i), line:2098:18, endln:2098:27 |vpiInstance: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 |vpiPort: \_port: (fpu_rm_i), line:2099:18, endln:2099:26 |vpiParent: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 |vpiName:fpu_rm_i |vpiHighConn: \_ref_obj: (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_rm_i), line:2099:18, endln:2099:26 @@ -139865,11 +139865,11 @@ design: (work@top) |vpiActual: \_logic_net: (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_rm_i), line:2099:18, endln:2099:26 |vpiInstance: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 |vpiPort: \_port: (fpu_frm_i), line:2100:18, endln:2100:27 |vpiParent: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 |vpiName:fpu_frm_i |vpiHighConn: \_ref_obj: (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_frm_i), line:2100:18, endln:2100:27 @@ -139880,11 +139880,11 @@ design: (work@top) |vpiActual: \_logic_net: (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_frm_i), line:2100:18, endln:2100:27 |vpiInstance: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 |vpiPort: \_port: (fpu_prec_i), line:2101:18, endln:2101:28 |vpiParent: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 |vpiName:fpu_prec_i |vpiHighConn: \_ref_obj: (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_prec_i), line:2101:18, endln:2101:28 @@ -139895,11 +139895,11 @@ design: (work@top) |vpiActual: \_logic_net: (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_prec_i), line:2101:18, endln:2101:28 |vpiInstance: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 |vpiPort: \_port: (fpu_trans_id_o), line:2102:18, endln:2102:32 |vpiParent: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 |vpiName:fpu_trans_id_o |vpiHighConn: \_ref_obj: (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_trans_id_o), line:2102:18, endln:2102:32 @@ -139910,11 +139910,11 @@ design: (work@top) |vpiActual: \_logic_net: (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_trans_id_o), line:2102:18, endln:2102:32 |vpiInstance: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 |vpiPort: \_port: (result_o), line:2103:18, endln:2103:26 |vpiParent: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 |vpiName:result_o |vpiHighConn: \_ref_obj: (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_result_o), line:2103:29, endln:2103:41 @@ -139925,11 +139925,11 @@ design: (work@top) |vpiActual: \_logic_net: (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_result_o), line:2103:29, endln:2103:41 |vpiInstance: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 |vpiPort: \_port: (fpu_valid_o), line:2104:18, endln:2104:29 |vpiParent: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 |vpiName:fpu_valid_o |vpiHighConn: \_ref_obj: (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_valid_o), line:2104:18, endln:2104:29 @@ -139940,11 +139940,11 @@ design: (work@top) |vpiActual: \_logic_net: (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_valid_o), line:2104:18, endln:2104:29 |vpiInstance: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 |vpiPort: \_port: (fpu_exception_o), line:2105:18, endln:2105:33 |vpiParent: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 |vpiName:fpu_exception_o |vpiHighConn: \_ref_obj: (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_exception_o), line:2105:18, endln:2105:33 @@ -139955,11 +139955,11 @@ design: (work@top) |vpiActual: \_logic_net: (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_exception_o), line:2105:18, endln:2105:33 |vpiInstance: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 |vpiGenScopeArray: \_gen_scope_array: (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen), line:2043:3, endln:2076:6 |vpiParent: - \_module: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 + \_module_inst: work@fpu_wrap (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15 |vpiName:fpu_gen |vpiFullName:work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen |vpiGenScope: @@ -142208,8 +142208,8 @@ design: (work@top) |vpiName:default |vpiLhs: \_parameter: (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.DEBUGMOI), line:2066:17, endln:2066:25 - |vpiModule: - \_module: work@fpnew_top (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2070:8, endln:2074:24 + |vpiModuleInst: + \_module_inst: work@fpnew_top (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2070:8, endln:2074:24 |vpiParent: \_gen_scope: (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen) |vpiName:i_fpnew_bulk @@ -143170,10 +143170,10 @@ design: (work@top) |vpiParameter: \_type_parameter: (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.TagType) |vpiParent: - \_module: work@fpnew_top (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2070:8, endln:2074:24 + \_module_inst: work@fpnew_top (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2070:8, endln:2074:24 |vpiName:TagType |vpiInstance: - \_module: work@fpnew_top (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2070:8, endln:2074:24 + \_module_inst: work@fpnew_top (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2070:8, endln:2074:24 |vpiFullName:work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.TagType |vpiTypespec: \_logic_typespec: , line:2073:25, endln:2073:50 @@ -143247,7 +143247,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:2008:45, endln:2008:84 |vpiParent: - \_module: work@fpnew_top (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2070:8, endln:2074:24 + \_module_inst: work@fpnew_top (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2070:8, endln:2074:24 |vpiOverriden:1 |vpiRhs: \_operation: , line:2071:25, endln:2071:37 @@ -143516,7 +143516,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:2009:45, endln:2009:87 |vpiParent: - \_module: work@fpnew_top (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2070:8, endln:2074:24 + \_module_inst: work@fpnew_top (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2070:8, endln:2074:24 |vpiOverriden:1 |vpiRhs: \_operation: , line:2072:25, endln:2072:43 @@ -144504,7 +144504,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:2012:27, endln:2012:56 |vpiParent: - \_module: work@fpnew_top (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2070:8, endln:2074:24 + \_module_inst: work@fpnew_top (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2070:8, endln:2074:24 |vpiRhs: \_constant: , line:2012:42, endln:2012:56 |vpiDecompile:64 @@ -144518,7 +144518,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:2013:27, endln:2013:43 |vpiParent: - \_module: work@fpnew_top (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2070:8, endln:2074:24 + \_module_inst: work@fpnew_top (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2070:8, endln:2074:24 |vpiRhs: \_constant: , line:2013:42, endln:2013:43 |vpiDecompile:3 @@ -144532,7 +144532,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:2016:27, endln:2016:65 |vpiParent: - \_module: work@fpnew_top (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2070:8, endln:2074:24 + \_module_inst: work@fpnew_top (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2070:8, endln:2074:24 |vpiRhs: \_constant: , line:2016:42, endln:2016:65 |vpiDecompile:4 @@ -144546,7 +144546,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:2017:27, endln:2017:67 |vpiParent: - \_module: work@fpnew_top (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2070:8, endln:2074:24 + \_module_inst: work@fpnew_top (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2070:8, endln:2074:24 |vpiRhs: \_constant: , line:2017:42, endln:2017:67 |vpiDecompile:5 @@ -144563,7 +144563,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[0]), line:2019:64, endln:2035:6 |vpiParent: - \_module: work@fpnew_top (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2070:8, endln:2074:24 + \_module_inst: work@fpnew_top (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2070:8, endln:2074:24 |vpiName:gen_operation_groups[0] |vpiFullName:work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[0] |vpiGenScope: @@ -144654,8 +144654,8 @@ design: (work@top) |vpiConstType:9 |vpiLhs: \_parameter: (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[0].DEBUGYOU), line:2021:18, endln:2021:26 - |vpiModule: - \_module: work@fpnew_opgroup_block (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[0].i_opgroup_block), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2023:5, endln:2034:7 + |vpiModuleInst: + \_module_inst: work@fpnew_opgroup_block (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[0].i_opgroup_block), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2023:5, endln:2034:7 |vpiParent: \_gen_scope: (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[0]) |vpiName:i_opgroup_block @@ -145123,10 +145123,10 @@ design: (work@top) |vpiParameter: \_type_parameter: (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[0].i_opgroup_block.TagType) |vpiParent: - \_module: work@fpnew_opgroup_block (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[0].i_opgroup_block), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2023:5, endln:2034:7 + \_module_inst: work@fpnew_opgroup_block (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[0].i_opgroup_block), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2023:5, endln:2034:7 |vpiName:TagType |vpiInstance: - \_module: work@fpnew_opgroup_block (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[0].i_opgroup_block), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2023:5, endln:2034:7 + \_module_inst: work@fpnew_opgroup_block (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[0].i_opgroup_block), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2023:5, endln:2034:7 |vpiFullName:work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[0].i_opgroup_block.TagType |vpiTypespec: \_logic_typespec: , line:2073:25, endln:2073:50 @@ -145178,7 +145178,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:1959:41, endln:1959:74 |vpiParent: - \_module: work@fpnew_opgroup_block (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[0].i_opgroup_block), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2023:5, endln:2034:7 + \_module_inst: work@fpnew_opgroup_block (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[0].i_opgroup_block), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2023:5, endln:2034:7 |vpiOverriden:1 |vpiRhs: \_constant: , line:1959:57, endln:1959:74 @@ -145193,7 +145193,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:1961:41, endln:1961:59 |vpiParent: - \_module: work@fpnew_opgroup_block (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[0].i_opgroup_block), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2023:5, endln:2034:7 + \_module_inst: work@fpnew_opgroup_block (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[0].i_opgroup_block), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2023:5, endln:2034:7 |vpiOverriden:1 |vpiRhs: \_constant: , line:1961:57, endln:1961:59 @@ -145208,7 +145208,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:1962:41, endln:1962:61 |vpiParent: - \_module: work@fpnew_opgroup_block (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[0].i_opgroup_block), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2023:5, endln:2034:7 + \_module_inst: work@fpnew_opgroup_block (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[0].i_opgroup_block), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2023:5, endln:2034:7 |vpiOverriden:1 |vpiRhs: \_constant: , line:1962:57, endln:1962:61 @@ -145223,7 +145223,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:1963:41, endln:1963:59 |vpiParent: - \_module: work@fpnew_opgroup_block (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[0].i_opgroup_block), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2023:5, endln:2034:7 + \_module_inst: work@fpnew_opgroup_block (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[0].i_opgroup_block), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2023:5, endln:2034:7 |vpiOverriden:1 |vpiRhs: \_constant: , line:1963:57, endln:1963:59 @@ -145238,7 +145238,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:1964:41, endln:1964:59 |vpiParent: - \_module: work@fpnew_opgroup_block (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[0].i_opgroup_block), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2023:5, endln:2034:7 + \_module_inst: work@fpnew_opgroup_block (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[0].i_opgroup_block), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2023:5, endln:2034:7 |vpiOverriden:1 |vpiRhs: \_hier_path: (Features.IntFmtMask), line:2028:24, endln:2028:43 @@ -145297,7 +145297,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:1965:41, endln:1965:70 |vpiParent: - \_module: work@fpnew_opgroup_block (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[0].i_opgroup_block), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2023:5, endln:2034:7 + \_module_inst: work@fpnew_opgroup_block (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[0].i_opgroup_block), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2023:5, endln:2034:7 |vpiOverriden:1 |vpiRhs: \_hier_path: (Implementation.PipeRegs[0]), line:2029:24, endln:2029:54 @@ -145422,7 +145422,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:1966:41, endln:1966:88 |vpiParent: - \_module: work@fpnew_opgroup_block (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[0].i_opgroup_block), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2023:5, endln:2034:7 + \_module_inst: work@fpnew_opgroup_block (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[0].i_opgroup_block), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2023:5, endln:2034:7 |vpiOverriden:1 |vpiRhs: \_hier_path: (Implementation.UnitTypes[0]), line:2030:24, endln:2030:55 @@ -145464,7 +145464,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:1967:41, endln:1967:74 |vpiParent: - \_module: work@fpnew_opgroup_block (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[0].i_opgroup_block), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2023:5, endln:2034:7 + \_module_inst: work@fpnew_opgroup_block (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[0].i_opgroup_block), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2023:5, endln:2034:7 |vpiOverriden:1 |vpiRhs: \_constant: , line:1967:57, endln:1967:74 @@ -145479,7 +145479,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:1970:27, endln:1970:67 |vpiParent: - \_module: work@fpnew_opgroup_block (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[0].i_opgroup_block), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2023:5, endln:2034:7 + \_module_inst: work@fpnew_opgroup_block (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[0].i_opgroup_block), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2023:5, endln:2034:7 |vpiRhs: \_constant: , line:1970:42, endln:1970:67 |vpiDecompile:5 @@ -145493,7 +145493,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:1971:27, endln:1971:74 |vpiParent: - \_module: work@fpnew_opgroup_block (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[0].i_opgroup_block), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2023:5, endln:2034:7 + \_module_inst: work@fpnew_opgroup_block (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[0].i_opgroup_block), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2023:5, endln:2034:7 |vpiRhs: \_constant: , line:1971:42, endln:1971:74 |vpiDecompile:3 @@ -145510,7 +145510,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[0].i_opgroup_block.gen_parallel_slices[0]), line:1974:55, endln:2000:6 |vpiParent: - \_module: work@fpnew_opgroup_block (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[0].i_opgroup_block), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2023:5, endln:2034:7 + \_module_inst: work@fpnew_opgroup_block (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[0].i_opgroup_block), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2023:5, endln:2034:7 |vpiName:gen_parallel_slices[0] |vpiFullName:work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[0].i_opgroup_block.gen_parallel_slices[0] |vpiGenScope: @@ -145814,7 +145814,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[0].i_opgroup_block.gen_parallel_slices[1]), line:1974:55, endln:2000:6 |vpiParent: - \_module: work@fpnew_opgroup_block (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[0].i_opgroup_block), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2023:5, endln:2034:7 + \_module_inst: work@fpnew_opgroup_block (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[0].i_opgroup_block), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2023:5, endln:2034:7 |vpiName:gen_parallel_slices[1] |vpiFullName:work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[0].i_opgroup_block.gen_parallel_slices[1] |vpiGenScope: @@ -146118,7 +146118,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[0].i_opgroup_block.gen_parallel_slices[2]), line:1974:55, endln:2000:6 |vpiParent: - \_module: work@fpnew_opgroup_block (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[0].i_opgroup_block), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2023:5, endln:2034:7 + \_module_inst: work@fpnew_opgroup_block (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[0].i_opgroup_block), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2023:5, endln:2034:7 |vpiName:gen_parallel_slices[2] |vpiFullName:work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[0].i_opgroup_block.gen_parallel_slices[2] |vpiGenScope: @@ -146422,7 +146422,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[0].i_opgroup_block.gen_parallel_slices[3]), line:1974:55, endln:2000:6 |vpiParent: - \_module: work@fpnew_opgroup_block (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[0].i_opgroup_block), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2023:5, endln:2034:7 + \_module_inst: work@fpnew_opgroup_block (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[0].i_opgroup_block), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2023:5, endln:2034:7 |vpiName:gen_parallel_slices[3] |vpiFullName:work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[0].i_opgroup_block.gen_parallel_slices[3] |vpiGenScope: @@ -146726,7 +146726,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[0].i_opgroup_block.gen_parallel_slices[4]), line:1974:55, endln:2000:6 |vpiParent: - \_module: work@fpnew_opgroup_block (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[0].i_opgroup_block), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2023:5, endln:2034:7 + \_module_inst: work@fpnew_opgroup_block (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[0].i_opgroup_block), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2023:5, endln:2034:7 |vpiName:gen_parallel_slices[4] |vpiFullName:work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[0].i_opgroup_block.gen_parallel_slices[4] |vpiGenScope: @@ -147030,7 +147030,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[1]), line:2019:64, endln:2035:6 |vpiParent: - \_module: work@fpnew_top (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2070:8, endln:2074:24 + \_module_inst: work@fpnew_top (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2070:8, endln:2074:24 |vpiName:gen_operation_groups[1] |vpiFullName:work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[1] |vpiGenScope: @@ -147121,8 +147121,8 @@ design: (work@top) |vpiConstType:9 |vpiLhs: \_parameter: (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[1].DEBUGYOU), line:2021:18, endln:2021:26 - |vpiModule: - \_module: work@fpnew_opgroup_block (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[1].i_opgroup_block), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2023:5, endln:2034:7 + |vpiModuleInst: + \_module_inst: work@fpnew_opgroup_block (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[1].i_opgroup_block), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2023:5, endln:2034:7 |vpiParent: \_gen_scope: (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[1]) |vpiName:i_opgroup_block @@ -147590,10 +147590,10 @@ design: (work@top) |vpiParameter: \_type_parameter: (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[1].i_opgroup_block.TagType) |vpiParent: - \_module: work@fpnew_opgroup_block (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[1].i_opgroup_block), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2023:5, endln:2034:7 + \_module_inst: work@fpnew_opgroup_block (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[1].i_opgroup_block), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2023:5, endln:2034:7 |vpiName:TagType |vpiInstance: - \_module: work@fpnew_opgroup_block (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[1].i_opgroup_block), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2023:5, endln:2034:7 + \_module_inst: work@fpnew_opgroup_block (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[1].i_opgroup_block), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2023:5, endln:2034:7 |vpiFullName:work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[1].i_opgroup_block.TagType |vpiTypespec: \_logic_typespec: , line:2073:25, endln:2073:50 @@ -147645,7 +147645,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:1959:41, endln:1959:74 |vpiParent: - \_module: work@fpnew_opgroup_block (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[1].i_opgroup_block), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2023:5, endln:2034:7 + \_module_inst: work@fpnew_opgroup_block (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[1].i_opgroup_block), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2023:5, endln:2034:7 |vpiOverriden:1 |vpiRhs: \_constant: , line:1959:57, endln:1959:74 @@ -147660,7 +147660,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:1961:41, endln:1961:59 |vpiParent: - \_module: work@fpnew_opgroup_block (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[1].i_opgroup_block), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2023:5, endln:2034:7 + \_module_inst: work@fpnew_opgroup_block (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[1].i_opgroup_block), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2023:5, endln:2034:7 |vpiOverriden:1 |vpiRhs: \_constant: , line:1961:57, endln:1961:59 @@ -147675,7 +147675,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:1962:41, endln:1962:61 |vpiParent: - \_module: work@fpnew_opgroup_block (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[1].i_opgroup_block), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2023:5, endln:2034:7 + \_module_inst: work@fpnew_opgroup_block (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[1].i_opgroup_block), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2023:5, endln:2034:7 |vpiOverriden:1 |vpiRhs: \_constant: , line:1962:57, endln:1962:61 @@ -147690,7 +147690,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:1963:41, endln:1963:59 |vpiParent: - \_module: work@fpnew_opgroup_block (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[1].i_opgroup_block), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2023:5, endln:2034:7 + \_module_inst: work@fpnew_opgroup_block (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[1].i_opgroup_block), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2023:5, endln:2034:7 |vpiOverriden:1 |vpiRhs: \_constant: , line:1963:57, endln:1963:59 @@ -147705,7 +147705,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:1964:41, endln:1964:59 |vpiParent: - \_module: work@fpnew_opgroup_block (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[1].i_opgroup_block), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2023:5, endln:2034:7 + \_module_inst: work@fpnew_opgroup_block (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[1].i_opgroup_block), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2023:5, endln:2034:7 |vpiOverriden:1 |vpiRhs: \_hier_path: (Features.IntFmtMask), line:2028:24, endln:2028:43 @@ -147737,7 +147737,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:1965:41, endln:1965:70 |vpiParent: - \_module: work@fpnew_opgroup_block (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[1].i_opgroup_block), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2023:5, endln:2034:7 + \_module_inst: work@fpnew_opgroup_block (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[1].i_opgroup_block), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2023:5, endln:2034:7 |vpiOverriden:1 |vpiRhs: \_hier_path: (Implementation.PipeRegs[1]), line:2029:24, endln:2029:54 @@ -147779,7 +147779,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:1966:41, endln:1966:88 |vpiParent: - \_module: work@fpnew_opgroup_block (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[1].i_opgroup_block), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2023:5, endln:2034:7 + \_module_inst: work@fpnew_opgroup_block (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[1].i_opgroup_block), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2023:5, endln:2034:7 |vpiOverriden:1 |vpiRhs: \_hier_path: (Implementation.UnitTypes[1]), line:2030:24, endln:2030:55 @@ -147821,7 +147821,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:1967:41, endln:1967:74 |vpiParent: - \_module: work@fpnew_opgroup_block (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[1].i_opgroup_block), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2023:5, endln:2034:7 + \_module_inst: work@fpnew_opgroup_block (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[1].i_opgroup_block), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2023:5, endln:2034:7 |vpiOverriden:1 |vpiRhs: \_constant: , line:1967:57, endln:1967:74 @@ -147836,7 +147836,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:1970:27, endln:1970:67 |vpiParent: - \_module: work@fpnew_opgroup_block (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[1].i_opgroup_block), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2023:5, endln:2034:7 + \_module_inst: work@fpnew_opgroup_block (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[1].i_opgroup_block), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2023:5, endln:2034:7 |vpiRhs: \_constant: , line:1970:42, endln:1970:67 |vpiDecompile:5 @@ -147850,7 +147850,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:1971:27, endln:1971:74 |vpiParent: - \_module: work@fpnew_opgroup_block (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[1].i_opgroup_block), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2023:5, endln:2034:7 + \_module_inst: work@fpnew_opgroup_block (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[1].i_opgroup_block), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2023:5, endln:2034:7 |vpiRhs: \_constant: , line:1971:42, endln:1971:74 |vpiDecompile:2 @@ -147867,7 +147867,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[1].i_opgroup_block.gen_parallel_slices[0]), line:1974:55, endln:2000:6 |vpiParent: - \_module: work@fpnew_opgroup_block (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[1].i_opgroup_block), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2023:5, endln:2034:7 + \_module_inst: work@fpnew_opgroup_block (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[1].i_opgroup_block), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2023:5, endln:2034:7 |vpiName:gen_parallel_slices[0] |vpiFullName:work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[1].i_opgroup_block.gen_parallel_slices[0] |vpiGenScope: @@ -148171,7 +148171,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[1].i_opgroup_block.gen_parallel_slices[1]), line:1974:55, endln:2000:6 |vpiParent: - \_module: work@fpnew_opgroup_block (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[1].i_opgroup_block), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2023:5, endln:2034:7 + \_module_inst: work@fpnew_opgroup_block (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[1].i_opgroup_block), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2023:5, endln:2034:7 |vpiName:gen_parallel_slices[1] |vpiFullName:work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[1].i_opgroup_block.gen_parallel_slices[1] |vpiGenScope: @@ -148475,7 +148475,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[1].i_opgroup_block.gen_parallel_slices[2]), line:1974:55, endln:2000:6 |vpiParent: - \_module: work@fpnew_opgroup_block (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[1].i_opgroup_block), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2023:5, endln:2034:7 + \_module_inst: work@fpnew_opgroup_block (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[1].i_opgroup_block), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2023:5, endln:2034:7 |vpiName:gen_parallel_slices[2] |vpiFullName:work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[1].i_opgroup_block.gen_parallel_slices[2] |vpiGenScope: @@ -148779,7 +148779,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[1].i_opgroup_block.gen_parallel_slices[3]), line:1974:55, endln:2000:6 |vpiParent: - \_module: work@fpnew_opgroup_block (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[1].i_opgroup_block), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2023:5, endln:2034:7 + \_module_inst: work@fpnew_opgroup_block (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[1].i_opgroup_block), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2023:5, endln:2034:7 |vpiName:gen_parallel_slices[3] |vpiFullName:work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[1].i_opgroup_block.gen_parallel_slices[3] |vpiGenScope: @@ -149083,7 +149083,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[1].i_opgroup_block.gen_parallel_slices[4]), line:1974:55, endln:2000:6 |vpiParent: - \_module: work@fpnew_opgroup_block (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[1].i_opgroup_block), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2023:5, endln:2034:7 + \_module_inst: work@fpnew_opgroup_block (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[1].i_opgroup_block), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2023:5, endln:2034:7 |vpiName:gen_parallel_slices[4] |vpiFullName:work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[1].i_opgroup_block.gen_parallel_slices[4] |vpiGenScope: @@ -149387,7 +149387,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[2]), line:2019:64, endln:2035:6 |vpiParent: - \_module: work@fpnew_top (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2070:8, endln:2074:24 + \_module_inst: work@fpnew_top (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2070:8, endln:2074:24 |vpiName:gen_operation_groups[2] |vpiFullName:work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[2] |vpiGenScope: @@ -149478,8 +149478,8 @@ design: (work@top) |vpiConstType:9 |vpiLhs: \_parameter: (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[2].DEBUGYOU), line:2021:18, endln:2021:26 - |vpiModule: - \_module: work@fpnew_opgroup_block (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[2].i_opgroup_block), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2023:5, endln:2034:7 + |vpiModuleInst: + \_module_inst: work@fpnew_opgroup_block (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[2].i_opgroup_block), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2023:5, endln:2034:7 |vpiParent: \_gen_scope: (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[2]) |vpiName:i_opgroup_block @@ -149947,10 +149947,10 @@ design: (work@top) |vpiParameter: \_type_parameter: (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[2].i_opgroup_block.TagType) |vpiParent: - \_module: work@fpnew_opgroup_block (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[2].i_opgroup_block), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2023:5, endln:2034:7 + \_module_inst: work@fpnew_opgroup_block (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[2].i_opgroup_block), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2023:5, endln:2034:7 |vpiName:TagType |vpiInstance: - \_module: work@fpnew_opgroup_block (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[2].i_opgroup_block), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2023:5, endln:2034:7 + \_module_inst: work@fpnew_opgroup_block (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[2].i_opgroup_block), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2023:5, endln:2034:7 |vpiFullName:work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[2].i_opgroup_block.TagType |vpiTypespec: \_logic_typespec: , line:2073:25, endln:2073:50 @@ -150002,7 +150002,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:1959:41, endln:1959:74 |vpiParent: - \_module: work@fpnew_opgroup_block (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[2].i_opgroup_block), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2023:5, endln:2034:7 + \_module_inst: work@fpnew_opgroup_block (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[2].i_opgroup_block), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2023:5, endln:2034:7 |vpiOverriden:1 |vpiRhs: \_constant: , line:1959:57, endln:1959:74 @@ -150017,7 +150017,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:1961:41, endln:1961:59 |vpiParent: - \_module: work@fpnew_opgroup_block (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[2].i_opgroup_block), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2023:5, endln:2034:7 + \_module_inst: work@fpnew_opgroup_block (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[2].i_opgroup_block), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2023:5, endln:2034:7 |vpiOverriden:1 |vpiRhs: \_constant: , line:1961:57, endln:1961:59 @@ -150032,7 +150032,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:1962:41, endln:1962:61 |vpiParent: - \_module: work@fpnew_opgroup_block (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[2].i_opgroup_block), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2023:5, endln:2034:7 + \_module_inst: work@fpnew_opgroup_block (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[2].i_opgroup_block), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2023:5, endln:2034:7 |vpiOverriden:1 |vpiRhs: \_constant: , line:1962:57, endln:1962:61 @@ -150047,7 +150047,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:1963:41, endln:1963:59 |vpiParent: - \_module: work@fpnew_opgroup_block (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[2].i_opgroup_block), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2023:5, endln:2034:7 + \_module_inst: work@fpnew_opgroup_block (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[2].i_opgroup_block), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2023:5, endln:2034:7 |vpiOverriden:1 |vpiRhs: \_constant: , line:1963:57, endln:1963:59 @@ -150062,7 +150062,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:1964:41, endln:1964:59 |vpiParent: - \_module: work@fpnew_opgroup_block (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[2].i_opgroup_block), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2023:5, endln:2034:7 + \_module_inst: work@fpnew_opgroup_block (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[2].i_opgroup_block), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2023:5, endln:2034:7 |vpiOverriden:1 |vpiRhs: \_hier_path: (Features.IntFmtMask), line:2028:24, endln:2028:43 @@ -150094,7 +150094,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:1965:41, endln:1965:70 |vpiParent: - \_module: work@fpnew_opgroup_block (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[2].i_opgroup_block), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2023:5, endln:2034:7 + \_module_inst: work@fpnew_opgroup_block (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[2].i_opgroup_block), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2023:5, endln:2034:7 |vpiOverriden:1 |vpiRhs: \_hier_path: (Implementation.PipeRegs[2]), line:2029:24, endln:2029:54 @@ -150136,7 +150136,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:1966:41, endln:1966:88 |vpiParent: - \_module: work@fpnew_opgroup_block (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[2].i_opgroup_block), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2023:5, endln:2034:7 + \_module_inst: work@fpnew_opgroup_block (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[2].i_opgroup_block), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2023:5, endln:2034:7 |vpiOverriden:1 |vpiRhs: \_hier_path: (Implementation.UnitTypes[2]), line:2030:24, endln:2030:55 @@ -150178,7 +150178,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:1967:41, endln:1967:74 |vpiParent: - \_module: work@fpnew_opgroup_block (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[2].i_opgroup_block), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2023:5, endln:2034:7 + \_module_inst: work@fpnew_opgroup_block (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[2].i_opgroup_block), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2023:5, endln:2034:7 |vpiOverriden:1 |vpiRhs: \_constant: , line:1967:57, endln:1967:74 @@ -150193,7 +150193,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:1970:27, endln:1970:67 |vpiParent: - \_module: work@fpnew_opgroup_block (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[2].i_opgroup_block), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2023:5, endln:2034:7 + \_module_inst: work@fpnew_opgroup_block (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[2].i_opgroup_block), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2023:5, endln:2034:7 |vpiRhs: \_constant: , line:1970:42, endln:1970:67 |vpiDecompile:5 @@ -150207,7 +150207,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:1971:27, endln:1971:74 |vpiParent: - \_module: work@fpnew_opgroup_block (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[2].i_opgroup_block), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2023:5, endln:2034:7 + \_module_inst: work@fpnew_opgroup_block (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[2].i_opgroup_block), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2023:5, endln:2034:7 |vpiRhs: \_constant: , line:1971:42, endln:1971:74 |vpiDecompile:2 @@ -150224,7 +150224,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[2].i_opgroup_block.gen_parallel_slices[0]), line:1974:55, endln:2000:6 |vpiParent: - \_module: work@fpnew_opgroup_block (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[2].i_opgroup_block), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2023:5, endln:2034:7 + \_module_inst: work@fpnew_opgroup_block (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[2].i_opgroup_block), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2023:5, endln:2034:7 |vpiName:gen_parallel_slices[0] |vpiFullName:work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[2].i_opgroup_block.gen_parallel_slices[0] |vpiGenScope: @@ -150528,7 +150528,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[2].i_opgroup_block.gen_parallel_slices[1]), line:1974:55, endln:2000:6 |vpiParent: - \_module: work@fpnew_opgroup_block (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[2].i_opgroup_block), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2023:5, endln:2034:7 + \_module_inst: work@fpnew_opgroup_block (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[2].i_opgroup_block), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2023:5, endln:2034:7 |vpiName:gen_parallel_slices[1] |vpiFullName:work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[2].i_opgroup_block.gen_parallel_slices[1] |vpiGenScope: @@ -150832,7 +150832,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[2].i_opgroup_block.gen_parallel_slices[2]), line:1974:55, endln:2000:6 |vpiParent: - \_module: work@fpnew_opgroup_block (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[2].i_opgroup_block), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2023:5, endln:2034:7 + \_module_inst: work@fpnew_opgroup_block (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[2].i_opgroup_block), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2023:5, endln:2034:7 |vpiName:gen_parallel_slices[2] |vpiFullName:work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[2].i_opgroup_block.gen_parallel_slices[2] |vpiGenScope: @@ -151136,7 +151136,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[2].i_opgroup_block.gen_parallel_slices[3]), line:1974:55, endln:2000:6 |vpiParent: - \_module: work@fpnew_opgroup_block (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[2].i_opgroup_block), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2023:5, endln:2034:7 + \_module_inst: work@fpnew_opgroup_block (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[2].i_opgroup_block), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2023:5, endln:2034:7 |vpiName:gen_parallel_slices[3] |vpiFullName:work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[2].i_opgroup_block.gen_parallel_slices[3] |vpiGenScope: @@ -151440,7 +151440,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[2].i_opgroup_block.gen_parallel_slices[4]), line:1974:55, endln:2000:6 |vpiParent: - \_module: work@fpnew_opgroup_block (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[2].i_opgroup_block), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2023:5, endln:2034:7 + \_module_inst: work@fpnew_opgroup_block (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[2].i_opgroup_block), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2023:5, endln:2034:7 |vpiName:gen_parallel_slices[4] |vpiFullName:work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[2].i_opgroup_block.gen_parallel_slices[4] |vpiGenScope: @@ -151744,7 +151744,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[3]), line:2019:64, endln:2035:6 |vpiParent: - \_module: work@fpnew_top (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2070:8, endln:2074:24 + \_module_inst: work@fpnew_top (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2070:8, endln:2074:24 |vpiName:gen_operation_groups[3] |vpiFullName:work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[3] |vpiGenScope: @@ -151835,8 +151835,8 @@ design: (work@top) |vpiConstType:9 |vpiLhs: \_parameter: (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[3].DEBUGYOU), line:2021:18, endln:2021:26 - |vpiModule: - \_module: work@fpnew_opgroup_block (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[3].i_opgroup_block), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2023:5, endln:2034:7 + |vpiModuleInst: + \_module_inst: work@fpnew_opgroup_block (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[3].i_opgroup_block), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2023:5, endln:2034:7 |vpiParent: \_gen_scope: (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[3]) |vpiName:i_opgroup_block @@ -152304,10 +152304,10 @@ design: (work@top) |vpiParameter: \_type_parameter: (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[3].i_opgroup_block.TagType) |vpiParent: - \_module: work@fpnew_opgroup_block (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[3].i_opgroup_block), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2023:5, endln:2034:7 + \_module_inst: work@fpnew_opgroup_block (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[3].i_opgroup_block), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2023:5, endln:2034:7 |vpiName:TagType |vpiInstance: - \_module: work@fpnew_opgroup_block (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[3].i_opgroup_block), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2023:5, endln:2034:7 + \_module_inst: work@fpnew_opgroup_block (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[3].i_opgroup_block), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2023:5, endln:2034:7 |vpiFullName:work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[3].i_opgroup_block.TagType |vpiTypespec: \_logic_typespec: , line:2073:25, endln:2073:50 @@ -152359,7 +152359,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:1959:41, endln:1959:74 |vpiParent: - \_module: work@fpnew_opgroup_block (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[3].i_opgroup_block), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2023:5, endln:2034:7 + \_module_inst: work@fpnew_opgroup_block (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[3].i_opgroup_block), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2023:5, endln:2034:7 |vpiOverriden:1 |vpiRhs: \_constant: , line:1959:57, endln:1959:74 @@ -152374,7 +152374,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:1961:41, endln:1961:59 |vpiParent: - \_module: work@fpnew_opgroup_block (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[3].i_opgroup_block), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2023:5, endln:2034:7 + \_module_inst: work@fpnew_opgroup_block (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[3].i_opgroup_block), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2023:5, endln:2034:7 |vpiOverriden:1 |vpiRhs: \_constant: , line:1961:57, endln:1961:59 @@ -152389,7 +152389,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:1962:41, endln:1962:61 |vpiParent: - \_module: work@fpnew_opgroup_block (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[3].i_opgroup_block), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2023:5, endln:2034:7 + \_module_inst: work@fpnew_opgroup_block (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[3].i_opgroup_block), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2023:5, endln:2034:7 |vpiOverriden:1 |vpiRhs: \_constant: , line:1962:57, endln:1962:61 @@ -152404,7 +152404,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:1963:41, endln:1963:59 |vpiParent: - \_module: work@fpnew_opgroup_block (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[3].i_opgroup_block), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2023:5, endln:2034:7 + \_module_inst: work@fpnew_opgroup_block (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[3].i_opgroup_block), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2023:5, endln:2034:7 |vpiOverriden:1 |vpiRhs: \_constant: , line:1963:57, endln:1963:59 @@ -152419,7 +152419,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:1964:41, endln:1964:59 |vpiParent: - \_module: work@fpnew_opgroup_block (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[3].i_opgroup_block), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2023:5, endln:2034:7 + \_module_inst: work@fpnew_opgroup_block (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[3].i_opgroup_block), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2023:5, endln:2034:7 |vpiOverriden:1 |vpiRhs: \_hier_path: (Features.IntFmtMask), line:2028:24, endln:2028:43 @@ -152451,7 +152451,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:1965:41, endln:1965:70 |vpiParent: - \_module: work@fpnew_opgroup_block (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[3].i_opgroup_block), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2023:5, endln:2034:7 + \_module_inst: work@fpnew_opgroup_block (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[3].i_opgroup_block), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2023:5, endln:2034:7 |vpiOverriden:1 |vpiRhs: \_hier_path: (Implementation.PipeRegs[3]), line:2029:24, endln:2029:54 @@ -152493,7 +152493,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:1966:41, endln:1966:88 |vpiParent: - \_module: work@fpnew_opgroup_block (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[3].i_opgroup_block), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2023:5, endln:2034:7 + \_module_inst: work@fpnew_opgroup_block (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[3].i_opgroup_block), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2023:5, endln:2034:7 |vpiOverriden:1 |vpiRhs: \_hier_path: (Implementation.UnitTypes[3]), line:2030:24, endln:2030:55 @@ -152535,7 +152535,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:1967:41, endln:1967:74 |vpiParent: - \_module: work@fpnew_opgroup_block (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[3].i_opgroup_block), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2023:5, endln:2034:7 + \_module_inst: work@fpnew_opgroup_block (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[3].i_opgroup_block), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2023:5, endln:2034:7 |vpiOverriden:1 |vpiRhs: \_constant: , line:1967:57, endln:1967:74 @@ -152550,7 +152550,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:1970:27, endln:1970:67 |vpiParent: - \_module: work@fpnew_opgroup_block (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[3].i_opgroup_block), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2023:5, endln:2034:7 + \_module_inst: work@fpnew_opgroup_block (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[3].i_opgroup_block), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2023:5, endln:2034:7 |vpiRhs: \_constant: , line:1970:42, endln:1970:67 |vpiDecompile:5 @@ -152564,7 +152564,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:1971:27, endln:1971:74 |vpiParent: - \_module: work@fpnew_opgroup_block (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[3].i_opgroup_block), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2023:5, endln:2034:7 + \_module_inst: work@fpnew_opgroup_block (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[3].i_opgroup_block), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2023:5, endln:2034:7 |vpiRhs: \_constant: , line:1971:42, endln:1971:74 |vpiDecompile:3 @@ -152581,7 +152581,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[3].i_opgroup_block.gen_parallel_slices[0]), line:1974:55, endln:2000:6 |vpiParent: - \_module: work@fpnew_opgroup_block (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[3].i_opgroup_block), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2023:5, endln:2034:7 + \_module_inst: work@fpnew_opgroup_block (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[3].i_opgroup_block), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2023:5, endln:2034:7 |vpiName:gen_parallel_slices[0] |vpiFullName:work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[3].i_opgroup_block.gen_parallel_slices[0] |vpiGenScope: @@ -152885,7 +152885,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[3].i_opgroup_block.gen_parallel_slices[1]), line:1974:55, endln:2000:6 |vpiParent: - \_module: work@fpnew_opgroup_block (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[3].i_opgroup_block), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2023:5, endln:2034:7 + \_module_inst: work@fpnew_opgroup_block (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[3].i_opgroup_block), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2023:5, endln:2034:7 |vpiName:gen_parallel_slices[1] |vpiFullName:work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[3].i_opgroup_block.gen_parallel_slices[1] |vpiGenScope: @@ -153189,7 +153189,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[3].i_opgroup_block.gen_parallel_slices[2]), line:1974:55, endln:2000:6 |vpiParent: - \_module: work@fpnew_opgroup_block (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[3].i_opgroup_block), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2023:5, endln:2034:7 + \_module_inst: work@fpnew_opgroup_block (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[3].i_opgroup_block), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2023:5, endln:2034:7 |vpiName:gen_parallel_slices[2] |vpiFullName:work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[3].i_opgroup_block.gen_parallel_slices[2] |vpiGenScope: @@ -153493,7 +153493,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[3].i_opgroup_block.gen_parallel_slices[3]), line:1974:55, endln:2000:6 |vpiParent: - \_module: work@fpnew_opgroup_block (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[3].i_opgroup_block), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2023:5, endln:2034:7 + \_module_inst: work@fpnew_opgroup_block (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[3].i_opgroup_block), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2023:5, endln:2034:7 |vpiName:gen_parallel_slices[3] |vpiFullName:work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[3].i_opgroup_block.gen_parallel_slices[3] |vpiGenScope: @@ -153797,7 +153797,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[3].i_opgroup_block.gen_parallel_slices[4]), line:1974:55, endln:2000:6 |vpiParent: - \_module: work@fpnew_opgroup_block (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[3].i_opgroup_block), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2023:5, endln:2034:7 + \_module_inst: work@fpnew_opgroup_block (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[3].i_opgroup_block), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2023:5, endln:2034:7 |vpiName:gen_parallel_slices[4] |vpiFullName:work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[3].i_opgroup_block.gen_parallel_slices[4] |vpiGenScope: diff --git a/tests/ArrayInst/ArrayInst.log b/tests/ArrayInst/ArrayInst.log index 460a5b6b9e..c5cc6dc0f0 100644 --- a/tests/ArrayInst/ArrayInst.log +++ b/tests/ArrayInst/ArrayInst.log @@ -123,8 +123,8 @@ n<> u<89> t c<1> l<1:1> el<11:1> === UHDM Object Stats Begin (Non-Elaborated Model) === constant 100 design 1 -module 53 module_array 13 +module_inst 53 module_typespec 13 range 39 === UHDM Object Stats End === @@ -133,8 +133,8 @@ range 39 === UHDM Object Stats Begin (Elaborated Model) === constant 100 design 1 -module 53 module_array 13 +module_inst 53 module_typespec 13 range 39 === UHDM Object Stats End === @@ -151,7 +151,7 @@ design: (work@top) |vpiElaborated:1 |vpiName:work@top |uhdmallModules: -\_module: work@flop (work@flop), file:${SURELOG_DIR}/tests/ArrayInst/dut.sv, line:4:1, endln:6:10 +\_module_inst: work@flop (work@flop), file:${SURELOG_DIR}/tests/ArrayInst/dut.sv, line:4:1, endln:6:10 |vpiParent: \_design: (work@top) |vpiFullName:work@flop @@ -159,7 +159,7 @@ design: (work@top) |vpiModuleArray: \_module_array: (work@qq), line:5:6, endln:5:7 |vpiParent: - \_module: work@flop (work@flop), file:${SURELOG_DIR}/tests/ArrayInst/dut.sv, line:4:1, endln:6:10 + \_module_inst: work@flop (work@flop), file:${SURELOG_DIR}/tests/ArrayInst/dut.sv, line:4:1, endln:6:10 |vpiName:q |vpiFullName:work@qq |vpiRange: @@ -184,13 +184,13 @@ design: (work@top) \_module_typespec: (qq), line:5:3, endln:5:5 |vpiName:qq |uhdmallModules: -\_module: work@qq (work@qq), file:${SURELOG_DIR}/tests/ArrayInst/dut.sv, line:1:1, endln:2:10 +\_module_inst: work@qq (work@qq), file:${SURELOG_DIR}/tests/ArrayInst/dut.sv, line:1:1, endln:2:10 |vpiParent: \_design: (work@top) |vpiFullName:work@qq |vpiDefName:work@qq |uhdmallModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/ArrayInst/dut.sv, line:8:1, endln:10:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ArrayInst/dut.sv, line:8:1, endln:10:10 |vpiParent: \_design: (work@top) |vpiFullName:work@top @@ -198,7 +198,7 @@ design: (work@top) |vpiModuleArray: \_module_array: (work@flop), line:9:8, endln:9:23 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ArrayInst/dut.sv, line:8:1, endln:10:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ArrayInst/dut.sv, line:8:1, endln:10:10 |vpiName:flop_instances1 |vpiFullName:work@flop |vpiRange: @@ -225,7 +225,7 @@ design: (work@top) |vpiModuleArray: \_module_array: (work@flop), line:9:32, endln:9:47 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ArrayInst/dut.sv, line:8:1, endln:10:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ArrayInst/dut.sv, line:8:1, endln:10:10 |vpiName:flop_instances2 |vpiFullName:work@flop |vpiRange: @@ -268,48 +268,48 @@ design: (work@top) \_module_typespec: (flop), line:9:3, endln:9:7 |vpiName:flop |uhdmtopModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/ArrayInst/dut.sv, line:8:1, endln:10:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ArrayInst/dut.sv, line:8:1, endln:10:10 |vpiName:work@top |vpiDefName:work@top |vpiTop:1 |vpiTopModule:1 - |vpiModule: - \_module: work@flop (work@top.flop_instances1[0]), file:${SURELOG_DIR}/tests/ArrayInst/dut.sv, line:9:3, endln:9:60 + |vpiModuleInst: + \_module_inst: work@flop (work@top.flop_instances1[0]), file:${SURELOG_DIR}/tests/ArrayInst/dut.sv, line:9:3, endln:9:60 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ArrayInst/dut.sv, line:8:1, endln:10:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ArrayInst/dut.sv, line:8:1, endln:10:10 |vpiName:flop_instances1[0] |vpiFullName:work@top.flop_instances1[0] |vpiDefName:work@flop |vpiDefFile:${SURELOG_DIR}/tests/ArrayInst/dut.sv |vpiDefLineNo:4 |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ArrayInst/dut.sv, line:8:1, endln:10:10 - |vpiModule: - \_module: work@qq (work@top.flop_instances1[0].q[0]), file:${SURELOG_DIR}/tests/ArrayInst/dut.sv, line:5:3, endln:5:15 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ArrayInst/dut.sv, line:8:1, endln:10:10 + |vpiModuleInst: + \_module_inst: work@qq (work@top.flop_instances1[0].q[0]), file:${SURELOG_DIR}/tests/ArrayInst/dut.sv, line:5:3, endln:5:15 |vpiParent: - \_module: work@flop (work@top.flop_instances1[0]), file:${SURELOG_DIR}/tests/ArrayInst/dut.sv, line:9:3, endln:9:60 + \_module_inst: work@flop (work@top.flop_instances1[0]), file:${SURELOG_DIR}/tests/ArrayInst/dut.sv, line:9:3, endln:9:60 |vpiName:q[0] |vpiFullName:work@top.flop_instances1[0].q[0] |vpiDefName:work@qq |vpiDefFile:${SURELOG_DIR}/tests/ArrayInst/dut.sv |vpiDefLineNo:1 |vpiInstance: - \_module: work@flop (work@top.flop_instances1[0]), file:${SURELOG_DIR}/tests/ArrayInst/dut.sv, line:9:3, endln:9:60 - |vpiModule: - \_module: work@qq (work@top.flop_instances1[0].q[1]), file:${SURELOG_DIR}/tests/ArrayInst/dut.sv, line:5:3, endln:5:15 + \_module_inst: work@flop (work@top.flop_instances1[0]), file:${SURELOG_DIR}/tests/ArrayInst/dut.sv, line:9:3, endln:9:60 + |vpiModuleInst: + \_module_inst: work@qq (work@top.flop_instances1[0].q[1]), file:${SURELOG_DIR}/tests/ArrayInst/dut.sv, line:5:3, endln:5:15 |vpiParent: - \_module: work@flop (work@top.flop_instances1[0]), file:${SURELOG_DIR}/tests/ArrayInst/dut.sv, line:9:3, endln:9:60 + \_module_inst: work@flop (work@top.flop_instances1[0]), file:${SURELOG_DIR}/tests/ArrayInst/dut.sv, line:9:3, endln:9:60 |vpiName:q[1] |vpiFullName:work@top.flop_instances1[0].q[1] |vpiDefName:work@qq |vpiDefFile:${SURELOG_DIR}/tests/ArrayInst/dut.sv |vpiDefLineNo:1 |vpiInstance: - \_module: work@flop (work@top.flop_instances1[0]), file:${SURELOG_DIR}/tests/ArrayInst/dut.sv, line:9:3, endln:9:60 + \_module_inst: work@flop (work@top.flop_instances1[0]), file:${SURELOG_DIR}/tests/ArrayInst/dut.sv, line:9:3, endln:9:60 |vpiModuleArray: \_module_array: (work@qq), line:5:6, endln:5:7 |vpiParent: - \_module: work@flop (work@top.flop_instances1[0]), file:${SURELOG_DIR}/tests/ArrayInst/dut.sv, line:9:3, endln:9:60 + \_module_inst: work@flop (work@top.flop_instances1[0]), file:${SURELOG_DIR}/tests/ArrayInst/dut.sv, line:9:3, endln:9:60 |vpiName:q |vpiFullName:work@qq |vpiRange: @@ -330,50 +330,50 @@ design: (work@top) |vpiSize:64 |UINT:0 |vpiConstType:9 - |vpiModule: - \_module: work@qq (work@top.flop_instances1[0].q[0]), file:${SURELOG_DIR}/tests/ArrayInst/dut.sv, line:5:3, endln:5:15 - |vpiModule: - \_module: work@qq (work@top.flop_instances1[0].q[1]), file:${SURELOG_DIR}/tests/ArrayInst/dut.sv, line:5:3, endln:5:15 + |vpiModuleInst: + \_module_inst: work@qq (work@top.flop_instances1[0].q[0]), file:${SURELOG_DIR}/tests/ArrayInst/dut.sv, line:5:3, endln:5:15 + |vpiModuleInst: + \_module_inst: work@qq (work@top.flop_instances1[0].q[1]), file:${SURELOG_DIR}/tests/ArrayInst/dut.sv, line:5:3, endln:5:15 |vpiElemTypespec: \_module_typespec: (qq), line:5:3, endln:5:5 |vpiName:qq - |vpiModule: - \_module: work@flop (work@top.flop_instances1[1]), file:${SURELOG_DIR}/tests/ArrayInst/dut.sv, line:9:3, endln:9:60 + |vpiModuleInst: + \_module_inst: work@flop (work@top.flop_instances1[1]), file:${SURELOG_DIR}/tests/ArrayInst/dut.sv, line:9:3, endln:9:60 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ArrayInst/dut.sv, line:8:1, endln:10:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ArrayInst/dut.sv, line:8:1, endln:10:10 |vpiName:flop_instances1[1] |vpiFullName:work@top.flop_instances1[1] |vpiDefName:work@flop |vpiDefFile:${SURELOG_DIR}/tests/ArrayInst/dut.sv |vpiDefLineNo:4 |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ArrayInst/dut.sv, line:8:1, endln:10:10 - |vpiModule: - \_module: work@qq (work@top.flop_instances1[1].q[0]), file:${SURELOG_DIR}/tests/ArrayInst/dut.sv, line:5:3, endln:5:15 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ArrayInst/dut.sv, line:8:1, endln:10:10 + |vpiModuleInst: + \_module_inst: work@qq (work@top.flop_instances1[1].q[0]), file:${SURELOG_DIR}/tests/ArrayInst/dut.sv, line:5:3, endln:5:15 |vpiParent: - \_module: work@flop (work@top.flop_instances1[1]), file:${SURELOG_DIR}/tests/ArrayInst/dut.sv, line:9:3, endln:9:60 + \_module_inst: work@flop (work@top.flop_instances1[1]), file:${SURELOG_DIR}/tests/ArrayInst/dut.sv, line:9:3, endln:9:60 |vpiName:q[0] |vpiFullName:work@top.flop_instances1[1].q[0] |vpiDefName:work@qq |vpiDefFile:${SURELOG_DIR}/tests/ArrayInst/dut.sv |vpiDefLineNo:1 |vpiInstance: - \_module: work@flop (work@top.flop_instances1[1]), file:${SURELOG_DIR}/tests/ArrayInst/dut.sv, line:9:3, endln:9:60 - |vpiModule: - \_module: work@qq (work@top.flop_instances1[1].q[1]), file:${SURELOG_DIR}/tests/ArrayInst/dut.sv, line:5:3, endln:5:15 + \_module_inst: work@flop (work@top.flop_instances1[1]), file:${SURELOG_DIR}/tests/ArrayInst/dut.sv, line:9:3, endln:9:60 + |vpiModuleInst: + \_module_inst: work@qq (work@top.flop_instances1[1].q[1]), file:${SURELOG_DIR}/tests/ArrayInst/dut.sv, line:5:3, endln:5:15 |vpiParent: - \_module: work@flop (work@top.flop_instances1[1]), file:${SURELOG_DIR}/tests/ArrayInst/dut.sv, line:9:3, endln:9:60 + \_module_inst: work@flop (work@top.flop_instances1[1]), file:${SURELOG_DIR}/tests/ArrayInst/dut.sv, line:9:3, endln:9:60 |vpiName:q[1] |vpiFullName:work@top.flop_instances1[1].q[1] |vpiDefName:work@qq |vpiDefFile:${SURELOG_DIR}/tests/ArrayInst/dut.sv |vpiDefLineNo:1 |vpiInstance: - \_module: work@flop (work@top.flop_instances1[1]), file:${SURELOG_DIR}/tests/ArrayInst/dut.sv, line:9:3, endln:9:60 + \_module_inst: work@flop (work@top.flop_instances1[1]), file:${SURELOG_DIR}/tests/ArrayInst/dut.sv, line:9:3, endln:9:60 |vpiModuleArray: \_module_array: (work@qq), line:5:6, endln:5:7 |vpiParent: - \_module: work@flop (work@top.flop_instances1[1]), file:${SURELOG_DIR}/tests/ArrayInst/dut.sv, line:9:3, endln:9:60 + \_module_inst: work@flop (work@top.flop_instances1[1]), file:${SURELOG_DIR}/tests/ArrayInst/dut.sv, line:9:3, endln:9:60 |vpiName:q |vpiFullName:work@qq |vpiRange: @@ -394,50 +394,50 @@ design: (work@top) |vpiSize:64 |UINT:0 |vpiConstType:9 - |vpiModule: - \_module: work@qq (work@top.flop_instances1[1].q[0]), file:${SURELOG_DIR}/tests/ArrayInst/dut.sv, line:5:3, endln:5:15 - |vpiModule: - \_module: work@qq (work@top.flop_instances1[1].q[1]), file:${SURELOG_DIR}/tests/ArrayInst/dut.sv, line:5:3, endln:5:15 + |vpiModuleInst: + \_module_inst: work@qq (work@top.flop_instances1[1].q[0]), file:${SURELOG_DIR}/tests/ArrayInst/dut.sv, line:5:3, endln:5:15 + |vpiModuleInst: + \_module_inst: work@qq (work@top.flop_instances1[1].q[1]), file:${SURELOG_DIR}/tests/ArrayInst/dut.sv, line:5:3, endln:5:15 |vpiElemTypespec: \_module_typespec: (qq), line:5:3, endln:5:5 |vpiName:qq - |vpiModule: - \_module: work@flop (work@top.flop_instances2[0][0]), file:${SURELOG_DIR}/tests/ArrayInst/dut.sv, line:9:3, endln:9:60 + |vpiModuleInst: + \_module_inst: work@flop (work@top.flop_instances2[0][0]), file:${SURELOG_DIR}/tests/ArrayInst/dut.sv, line:9:3, endln:9:60 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ArrayInst/dut.sv, line:8:1, endln:10:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ArrayInst/dut.sv, line:8:1, endln:10:10 |vpiName:flop_instances2[0][0] |vpiFullName:work@top.flop_instances2[0][0] |vpiDefName:work@flop |vpiDefFile:${SURELOG_DIR}/tests/ArrayInst/dut.sv |vpiDefLineNo:4 |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ArrayInst/dut.sv, line:8:1, endln:10:10 - |vpiModule: - \_module: work@qq (work@top.flop_instances2[0][0].q[0]), file:${SURELOG_DIR}/tests/ArrayInst/dut.sv, line:5:3, endln:5:15 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ArrayInst/dut.sv, line:8:1, endln:10:10 + |vpiModuleInst: + \_module_inst: work@qq (work@top.flop_instances2[0][0].q[0]), file:${SURELOG_DIR}/tests/ArrayInst/dut.sv, line:5:3, endln:5:15 |vpiParent: - \_module: work@flop (work@top.flop_instances2[0][0]), file:${SURELOG_DIR}/tests/ArrayInst/dut.sv, line:9:3, endln:9:60 + \_module_inst: work@flop (work@top.flop_instances2[0][0]), file:${SURELOG_DIR}/tests/ArrayInst/dut.sv, line:9:3, endln:9:60 |vpiName:q[0] |vpiFullName:work@top.flop_instances2[0][0].q[0] |vpiDefName:work@qq |vpiDefFile:${SURELOG_DIR}/tests/ArrayInst/dut.sv |vpiDefLineNo:1 |vpiInstance: - \_module: work@flop (work@top.flop_instances2[0][0]), file:${SURELOG_DIR}/tests/ArrayInst/dut.sv, line:9:3, endln:9:60 - |vpiModule: - \_module: work@qq (work@top.flop_instances2[0][0].q[1]), file:${SURELOG_DIR}/tests/ArrayInst/dut.sv, line:5:3, endln:5:15 + \_module_inst: work@flop (work@top.flop_instances2[0][0]), file:${SURELOG_DIR}/tests/ArrayInst/dut.sv, line:9:3, endln:9:60 + |vpiModuleInst: + \_module_inst: work@qq (work@top.flop_instances2[0][0].q[1]), file:${SURELOG_DIR}/tests/ArrayInst/dut.sv, line:5:3, endln:5:15 |vpiParent: - \_module: work@flop (work@top.flop_instances2[0][0]), file:${SURELOG_DIR}/tests/ArrayInst/dut.sv, line:9:3, endln:9:60 + \_module_inst: work@flop (work@top.flop_instances2[0][0]), file:${SURELOG_DIR}/tests/ArrayInst/dut.sv, line:9:3, endln:9:60 |vpiName:q[1] |vpiFullName:work@top.flop_instances2[0][0].q[1] |vpiDefName:work@qq |vpiDefFile:${SURELOG_DIR}/tests/ArrayInst/dut.sv |vpiDefLineNo:1 |vpiInstance: - \_module: work@flop (work@top.flop_instances2[0][0]), file:${SURELOG_DIR}/tests/ArrayInst/dut.sv, line:9:3, endln:9:60 + \_module_inst: work@flop (work@top.flop_instances2[0][0]), file:${SURELOG_DIR}/tests/ArrayInst/dut.sv, line:9:3, endln:9:60 |vpiModuleArray: \_module_array: (work@qq), line:5:6, endln:5:7 |vpiParent: - \_module: work@flop (work@top.flop_instances2[0][0]), file:${SURELOG_DIR}/tests/ArrayInst/dut.sv, line:9:3, endln:9:60 + \_module_inst: work@flop (work@top.flop_instances2[0][0]), file:${SURELOG_DIR}/tests/ArrayInst/dut.sv, line:9:3, endln:9:60 |vpiName:q |vpiFullName:work@qq |vpiRange: @@ -458,50 +458,50 @@ design: (work@top) |vpiSize:64 |UINT:0 |vpiConstType:9 - |vpiModule: - \_module: work@qq (work@top.flop_instances2[0][0].q[0]), file:${SURELOG_DIR}/tests/ArrayInst/dut.sv, line:5:3, endln:5:15 - |vpiModule: - \_module: work@qq (work@top.flop_instances2[0][0].q[1]), file:${SURELOG_DIR}/tests/ArrayInst/dut.sv, line:5:3, endln:5:15 + |vpiModuleInst: + \_module_inst: work@qq (work@top.flop_instances2[0][0].q[0]), file:${SURELOG_DIR}/tests/ArrayInst/dut.sv, line:5:3, endln:5:15 + |vpiModuleInst: + \_module_inst: work@qq (work@top.flop_instances2[0][0].q[1]), file:${SURELOG_DIR}/tests/ArrayInst/dut.sv, line:5:3, endln:5:15 |vpiElemTypespec: \_module_typespec: (qq), line:5:3, endln:5:5 |vpiName:qq - |vpiModule: - \_module: work@flop (work@top.flop_instances2[0][1]), file:${SURELOG_DIR}/tests/ArrayInst/dut.sv, line:9:3, endln:9:60 + |vpiModuleInst: + \_module_inst: work@flop (work@top.flop_instances2[0][1]), file:${SURELOG_DIR}/tests/ArrayInst/dut.sv, line:9:3, endln:9:60 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ArrayInst/dut.sv, line:8:1, endln:10:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ArrayInst/dut.sv, line:8:1, endln:10:10 |vpiName:flop_instances2[0][1] |vpiFullName:work@top.flop_instances2[0][1] |vpiDefName:work@flop |vpiDefFile:${SURELOG_DIR}/tests/ArrayInst/dut.sv |vpiDefLineNo:4 |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ArrayInst/dut.sv, line:8:1, endln:10:10 - |vpiModule: - \_module: work@qq (work@top.flop_instances2[0][1].q[0]), file:${SURELOG_DIR}/tests/ArrayInst/dut.sv, line:5:3, endln:5:15 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ArrayInst/dut.sv, line:8:1, endln:10:10 + |vpiModuleInst: + \_module_inst: work@qq (work@top.flop_instances2[0][1].q[0]), file:${SURELOG_DIR}/tests/ArrayInst/dut.sv, line:5:3, endln:5:15 |vpiParent: - \_module: work@flop (work@top.flop_instances2[0][1]), file:${SURELOG_DIR}/tests/ArrayInst/dut.sv, line:9:3, endln:9:60 + \_module_inst: work@flop (work@top.flop_instances2[0][1]), file:${SURELOG_DIR}/tests/ArrayInst/dut.sv, line:9:3, endln:9:60 |vpiName:q[0] |vpiFullName:work@top.flop_instances2[0][1].q[0] |vpiDefName:work@qq |vpiDefFile:${SURELOG_DIR}/tests/ArrayInst/dut.sv |vpiDefLineNo:1 |vpiInstance: - \_module: work@flop (work@top.flop_instances2[0][1]), file:${SURELOG_DIR}/tests/ArrayInst/dut.sv, line:9:3, endln:9:60 - |vpiModule: - \_module: work@qq (work@top.flop_instances2[0][1].q[1]), file:${SURELOG_DIR}/tests/ArrayInst/dut.sv, line:5:3, endln:5:15 + \_module_inst: work@flop (work@top.flop_instances2[0][1]), file:${SURELOG_DIR}/tests/ArrayInst/dut.sv, line:9:3, endln:9:60 + |vpiModuleInst: + \_module_inst: work@qq (work@top.flop_instances2[0][1].q[1]), file:${SURELOG_DIR}/tests/ArrayInst/dut.sv, line:5:3, endln:5:15 |vpiParent: - \_module: work@flop (work@top.flop_instances2[0][1]), file:${SURELOG_DIR}/tests/ArrayInst/dut.sv, line:9:3, endln:9:60 + \_module_inst: work@flop (work@top.flop_instances2[0][1]), file:${SURELOG_DIR}/tests/ArrayInst/dut.sv, line:9:3, endln:9:60 |vpiName:q[1] |vpiFullName:work@top.flop_instances2[0][1].q[1] |vpiDefName:work@qq |vpiDefFile:${SURELOG_DIR}/tests/ArrayInst/dut.sv |vpiDefLineNo:1 |vpiInstance: - \_module: work@flop (work@top.flop_instances2[0][1]), file:${SURELOG_DIR}/tests/ArrayInst/dut.sv, line:9:3, endln:9:60 + \_module_inst: work@flop (work@top.flop_instances2[0][1]), file:${SURELOG_DIR}/tests/ArrayInst/dut.sv, line:9:3, endln:9:60 |vpiModuleArray: \_module_array: (work@qq), line:5:6, endln:5:7 |vpiParent: - \_module: work@flop (work@top.flop_instances2[0][1]), file:${SURELOG_DIR}/tests/ArrayInst/dut.sv, line:9:3, endln:9:60 + \_module_inst: work@flop (work@top.flop_instances2[0][1]), file:${SURELOG_DIR}/tests/ArrayInst/dut.sv, line:9:3, endln:9:60 |vpiName:q |vpiFullName:work@qq |vpiRange: @@ -522,50 +522,50 @@ design: (work@top) |vpiSize:64 |UINT:0 |vpiConstType:9 - |vpiModule: - \_module: work@qq (work@top.flop_instances2[0][1].q[0]), file:${SURELOG_DIR}/tests/ArrayInst/dut.sv, line:5:3, endln:5:15 - |vpiModule: - \_module: work@qq (work@top.flop_instances2[0][1].q[1]), file:${SURELOG_DIR}/tests/ArrayInst/dut.sv, line:5:3, endln:5:15 + |vpiModuleInst: + \_module_inst: work@qq (work@top.flop_instances2[0][1].q[0]), file:${SURELOG_DIR}/tests/ArrayInst/dut.sv, line:5:3, endln:5:15 + |vpiModuleInst: + \_module_inst: work@qq (work@top.flop_instances2[0][1].q[1]), file:${SURELOG_DIR}/tests/ArrayInst/dut.sv, line:5:3, endln:5:15 |vpiElemTypespec: \_module_typespec: (qq), line:5:3, endln:5:5 |vpiName:qq - |vpiModule: - \_module: work@flop (work@top.flop_instances2[1][0]), file:${SURELOG_DIR}/tests/ArrayInst/dut.sv, line:9:3, endln:9:60 + |vpiModuleInst: + \_module_inst: work@flop (work@top.flop_instances2[1][0]), file:${SURELOG_DIR}/tests/ArrayInst/dut.sv, line:9:3, endln:9:60 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ArrayInst/dut.sv, line:8:1, endln:10:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ArrayInst/dut.sv, line:8:1, endln:10:10 |vpiName:flop_instances2[1][0] |vpiFullName:work@top.flop_instances2[1][0] |vpiDefName:work@flop |vpiDefFile:${SURELOG_DIR}/tests/ArrayInst/dut.sv |vpiDefLineNo:4 |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ArrayInst/dut.sv, line:8:1, endln:10:10 - |vpiModule: - \_module: work@qq (work@top.flop_instances2[1][0].q[0]), file:${SURELOG_DIR}/tests/ArrayInst/dut.sv, line:5:3, endln:5:15 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ArrayInst/dut.sv, line:8:1, endln:10:10 + |vpiModuleInst: + \_module_inst: work@qq (work@top.flop_instances2[1][0].q[0]), file:${SURELOG_DIR}/tests/ArrayInst/dut.sv, line:5:3, endln:5:15 |vpiParent: - \_module: work@flop (work@top.flop_instances2[1][0]), file:${SURELOG_DIR}/tests/ArrayInst/dut.sv, line:9:3, endln:9:60 + \_module_inst: work@flop (work@top.flop_instances2[1][0]), file:${SURELOG_DIR}/tests/ArrayInst/dut.sv, line:9:3, endln:9:60 |vpiName:q[0] |vpiFullName:work@top.flop_instances2[1][0].q[0] |vpiDefName:work@qq |vpiDefFile:${SURELOG_DIR}/tests/ArrayInst/dut.sv |vpiDefLineNo:1 |vpiInstance: - \_module: work@flop (work@top.flop_instances2[1][0]), file:${SURELOG_DIR}/tests/ArrayInst/dut.sv, line:9:3, endln:9:60 - |vpiModule: - \_module: work@qq (work@top.flop_instances2[1][0].q[1]), file:${SURELOG_DIR}/tests/ArrayInst/dut.sv, line:5:3, endln:5:15 + \_module_inst: work@flop (work@top.flop_instances2[1][0]), file:${SURELOG_DIR}/tests/ArrayInst/dut.sv, line:9:3, endln:9:60 + |vpiModuleInst: + \_module_inst: work@qq (work@top.flop_instances2[1][0].q[1]), file:${SURELOG_DIR}/tests/ArrayInst/dut.sv, line:5:3, endln:5:15 |vpiParent: - \_module: work@flop (work@top.flop_instances2[1][0]), file:${SURELOG_DIR}/tests/ArrayInst/dut.sv, line:9:3, endln:9:60 + \_module_inst: work@flop (work@top.flop_instances2[1][0]), file:${SURELOG_DIR}/tests/ArrayInst/dut.sv, line:9:3, endln:9:60 |vpiName:q[1] |vpiFullName:work@top.flop_instances2[1][0].q[1] |vpiDefName:work@qq |vpiDefFile:${SURELOG_DIR}/tests/ArrayInst/dut.sv |vpiDefLineNo:1 |vpiInstance: - \_module: work@flop (work@top.flop_instances2[1][0]), file:${SURELOG_DIR}/tests/ArrayInst/dut.sv, line:9:3, endln:9:60 + \_module_inst: work@flop (work@top.flop_instances2[1][0]), file:${SURELOG_DIR}/tests/ArrayInst/dut.sv, line:9:3, endln:9:60 |vpiModuleArray: \_module_array: (work@qq), line:5:6, endln:5:7 |vpiParent: - \_module: work@flop (work@top.flop_instances2[1][0]), file:${SURELOG_DIR}/tests/ArrayInst/dut.sv, line:9:3, endln:9:60 + \_module_inst: work@flop (work@top.flop_instances2[1][0]), file:${SURELOG_DIR}/tests/ArrayInst/dut.sv, line:9:3, endln:9:60 |vpiName:q |vpiFullName:work@qq |vpiRange: @@ -586,50 +586,50 @@ design: (work@top) |vpiSize:64 |UINT:0 |vpiConstType:9 - |vpiModule: - \_module: work@qq (work@top.flop_instances2[1][0].q[0]), file:${SURELOG_DIR}/tests/ArrayInst/dut.sv, line:5:3, endln:5:15 - |vpiModule: - \_module: work@qq (work@top.flop_instances2[1][0].q[1]), file:${SURELOG_DIR}/tests/ArrayInst/dut.sv, line:5:3, endln:5:15 + |vpiModuleInst: + \_module_inst: work@qq (work@top.flop_instances2[1][0].q[0]), file:${SURELOG_DIR}/tests/ArrayInst/dut.sv, line:5:3, endln:5:15 + |vpiModuleInst: + \_module_inst: work@qq (work@top.flop_instances2[1][0].q[1]), file:${SURELOG_DIR}/tests/ArrayInst/dut.sv, line:5:3, endln:5:15 |vpiElemTypespec: \_module_typespec: (qq), line:5:3, endln:5:5 |vpiName:qq - |vpiModule: - \_module: work@flop (work@top.flop_instances2[1][1]), file:${SURELOG_DIR}/tests/ArrayInst/dut.sv, line:9:3, endln:9:60 + |vpiModuleInst: + \_module_inst: work@flop (work@top.flop_instances2[1][1]), file:${SURELOG_DIR}/tests/ArrayInst/dut.sv, line:9:3, endln:9:60 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ArrayInst/dut.sv, line:8:1, endln:10:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ArrayInst/dut.sv, line:8:1, endln:10:10 |vpiName:flop_instances2[1][1] |vpiFullName:work@top.flop_instances2[1][1] |vpiDefName:work@flop |vpiDefFile:${SURELOG_DIR}/tests/ArrayInst/dut.sv |vpiDefLineNo:4 |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ArrayInst/dut.sv, line:8:1, endln:10:10 - |vpiModule: - \_module: work@qq (work@top.flop_instances2[1][1].q[0]), file:${SURELOG_DIR}/tests/ArrayInst/dut.sv, line:5:3, endln:5:15 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ArrayInst/dut.sv, line:8:1, endln:10:10 + |vpiModuleInst: + \_module_inst: work@qq (work@top.flop_instances2[1][1].q[0]), file:${SURELOG_DIR}/tests/ArrayInst/dut.sv, line:5:3, endln:5:15 |vpiParent: - \_module: work@flop (work@top.flop_instances2[1][1]), file:${SURELOG_DIR}/tests/ArrayInst/dut.sv, line:9:3, endln:9:60 + \_module_inst: work@flop (work@top.flop_instances2[1][1]), file:${SURELOG_DIR}/tests/ArrayInst/dut.sv, line:9:3, endln:9:60 |vpiName:q[0] |vpiFullName:work@top.flop_instances2[1][1].q[0] |vpiDefName:work@qq |vpiDefFile:${SURELOG_DIR}/tests/ArrayInst/dut.sv |vpiDefLineNo:1 |vpiInstance: - \_module: work@flop (work@top.flop_instances2[1][1]), file:${SURELOG_DIR}/tests/ArrayInst/dut.sv, line:9:3, endln:9:60 - |vpiModule: - \_module: work@qq (work@top.flop_instances2[1][1].q[1]), file:${SURELOG_DIR}/tests/ArrayInst/dut.sv, line:5:3, endln:5:15 + \_module_inst: work@flop (work@top.flop_instances2[1][1]), file:${SURELOG_DIR}/tests/ArrayInst/dut.sv, line:9:3, endln:9:60 + |vpiModuleInst: + \_module_inst: work@qq (work@top.flop_instances2[1][1].q[1]), file:${SURELOG_DIR}/tests/ArrayInst/dut.sv, line:5:3, endln:5:15 |vpiParent: - \_module: work@flop (work@top.flop_instances2[1][1]), file:${SURELOG_DIR}/tests/ArrayInst/dut.sv, line:9:3, endln:9:60 + \_module_inst: work@flop (work@top.flop_instances2[1][1]), file:${SURELOG_DIR}/tests/ArrayInst/dut.sv, line:9:3, endln:9:60 |vpiName:q[1] |vpiFullName:work@top.flop_instances2[1][1].q[1] |vpiDefName:work@qq |vpiDefFile:${SURELOG_DIR}/tests/ArrayInst/dut.sv |vpiDefLineNo:1 |vpiInstance: - \_module: work@flop (work@top.flop_instances2[1][1]), file:${SURELOG_DIR}/tests/ArrayInst/dut.sv, line:9:3, endln:9:60 + \_module_inst: work@flop (work@top.flop_instances2[1][1]), file:${SURELOG_DIR}/tests/ArrayInst/dut.sv, line:9:3, endln:9:60 |vpiModuleArray: \_module_array: (work@qq), line:5:6, endln:5:7 |vpiParent: - \_module: work@flop (work@top.flop_instances2[1][1]), file:${SURELOG_DIR}/tests/ArrayInst/dut.sv, line:9:3, endln:9:60 + \_module_inst: work@flop (work@top.flop_instances2[1][1]), file:${SURELOG_DIR}/tests/ArrayInst/dut.sv, line:9:3, endln:9:60 |vpiName:q |vpiFullName:work@qq |vpiRange: @@ -650,50 +650,50 @@ design: (work@top) |vpiSize:64 |UINT:0 |vpiConstType:9 - |vpiModule: - \_module: work@qq (work@top.flop_instances2[1][1].q[0]), file:${SURELOG_DIR}/tests/ArrayInst/dut.sv, line:5:3, endln:5:15 - |vpiModule: - \_module: work@qq (work@top.flop_instances2[1][1].q[1]), file:${SURELOG_DIR}/tests/ArrayInst/dut.sv, line:5:3, endln:5:15 + |vpiModuleInst: + \_module_inst: work@qq (work@top.flop_instances2[1][1].q[0]), file:${SURELOG_DIR}/tests/ArrayInst/dut.sv, line:5:3, endln:5:15 + |vpiModuleInst: + \_module_inst: work@qq (work@top.flop_instances2[1][1].q[1]), file:${SURELOG_DIR}/tests/ArrayInst/dut.sv, line:5:3, endln:5:15 |vpiElemTypespec: \_module_typespec: (qq), line:5:3, endln:5:5 |vpiName:qq - |vpiModule: - \_module: work@flop (work@top.flop_instances2[2][0]), file:${SURELOG_DIR}/tests/ArrayInst/dut.sv, line:9:3, endln:9:60 + |vpiModuleInst: + \_module_inst: work@flop (work@top.flop_instances2[2][0]), file:${SURELOG_DIR}/tests/ArrayInst/dut.sv, line:9:3, endln:9:60 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ArrayInst/dut.sv, line:8:1, endln:10:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ArrayInst/dut.sv, line:8:1, endln:10:10 |vpiName:flop_instances2[2][0] |vpiFullName:work@top.flop_instances2[2][0] |vpiDefName:work@flop |vpiDefFile:${SURELOG_DIR}/tests/ArrayInst/dut.sv |vpiDefLineNo:4 |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ArrayInst/dut.sv, line:8:1, endln:10:10 - |vpiModule: - \_module: work@qq (work@top.flop_instances2[2][0].q[0]), file:${SURELOG_DIR}/tests/ArrayInst/dut.sv, line:5:3, endln:5:15 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ArrayInst/dut.sv, line:8:1, endln:10:10 + |vpiModuleInst: + \_module_inst: work@qq (work@top.flop_instances2[2][0].q[0]), file:${SURELOG_DIR}/tests/ArrayInst/dut.sv, line:5:3, endln:5:15 |vpiParent: - \_module: work@flop (work@top.flop_instances2[2][0]), file:${SURELOG_DIR}/tests/ArrayInst/dut.sv, line:9:3, endln:9:60 + \_module_inst: work@flop (work@top.flop_instances2[2][0]), file:${SURELOG_DIR}/tests/ArrayInst/dut.sv, line:9:3, endln:9:60 |vpiName:q[0] |vpiFullName:work@top.flop_instances2[2][0].q[0] |vpiDefName:work@qq |vpiDefFile:${SURELOG_DIR}/tests/ArrayInst/dut.sv |vpiDefLineNo:1 |vpiInstance: - \_module: work@flop (work@top.flop_instances2[2][0]), file:${SURELOG_DIR}/tests/ArrayInst/dut.sv, line:9:3, endln:9:60 - |vpiModule: - \_module: work@qq (work@top.flop_instances2[2][0].q[1]), file:${SURELOG_DIR}/tests/ArrayInst/dut.sv, line:5:3, endln:5:15 + \_module_inst: work@flop (work@top.flop_instances2[2][0]), file:${SURELOG_DIR}/tests/ArrayInst/dut.sv, line:9:3, endln:9:60 + |vpiModuleInst: + \_module_inst: work@qq (work@top.flop_instances2[2][0].q[1]), file:${SURELOG_DIR}/tests/ArrayInst/dut.sv, line:5:3, endln:5:15 |vpiParent: - \_module: work@flop (work@top.flop_instances2[2][0]), file:${SURELOG_DIR}/tests/ArrayInst/dut.sv, line:9:3, endln:9:60 + \_module_inst: work@flop (work@top.flop_instances2[2][0]), file:${SURELOG_DIR}/tests/ArrayInst/dut.sv, line:9:3, endln:9:60 |vpiName:q[1] |vpiFullName:work@top.flop_instances2[2][0].q[1] |vpiDefName:work@qq |vpiDefFile:${SURELOG_DIR}/tests/ArrayInst/dut.sv |vpiDefLineNo:1 |vpiInstance: - \_module: work@flop (work@top.flop_instances2[2][0]), file:${SURELOG_DIR}/tests/ArrayInst/dut.sv, line:9:3, endln:9:60 + \_module_inst: work@flop (work@top.flop_instances2[2][0]), file:${SURELOG_DIR}/tests/ArrayInst/dut.sv, line:9:3, endln:9:60 |vpiModuleArray: \_module_array: (work@qq), line:5:6, endln:5:7 |vpiParent: - \_module: work@flop (work@top.flop_instances2[2][0]), file:${SURELOG_DIR}/tests/ArrayInst/dut.sv, line:9:3, endln:9:60 + \_module_inst: work@flop (work@top.flop_instances2[2][0]), file:${SURELOG_DIR}/tests/ArrayInst/dut.sv, line:9:3, endln:9:60 |vpiName:q |vpiFullName:work@qq |vpiRange: @@ -714,50 +714,50 @@ design: (work@top) |vpiSize:64 |UINT:0 |vpiConstType:9 - |vpiModule: - \_module: work@qq (work@top.flop_instances2[2][0].q[0]), file:${SURELOG_DIR}/tests/ArrayInst/dut.sv, line:5:3, endln:5:15 - |vpiModule: - \_module: work@qq (work@top.flop_instances2[2][0].q[1]), file:${SURELOG_DIR}/tests/ArrayInst/dut.sv, line:5:3, endln:5:15 + |vpiModuleInst: + \_module_inst: work@qq (work@top.flop_instances2[2][0].q[0]), file:${SURELOG_DIR}/tests/ArrayInst/dut.sv, line:5:3, endln:5:15 + |vpiModuleInst: + \_module_inst: work@qq (work@top.flop_instances2[2][0].q[1]), file:${SURELOG_DIR}/tests/ArrayInst/dut.sv, line:5:3, endln:5:15 |vpiElemTypespec: \_module_typespec: (qq), line:5:3, endln:5:5 |vpiName:qq - |vpiModule: - \_module: work@flop (work@top.flop_instances2[2][1]), file:${SURELOG_DIR}/tests/ArrayInst/dut.sv, line:9:3, endln:9:60 + |vpiModuleInst: + \_module_inst: work@flop (work@top.flop_instances2[2][1]), file:${SURELOG_DIR}/tests/ArrayInst/dut.sv, line:9:3, endln:9:60 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ArrayInst/dut.sv, line:8:1, endln:10:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ArrayInst/dut.sv, line:8:1, endln:10:10 |vpiName:flop_instances2[2][1] |vpiFullName:work@top.flop_instances2[2][1] |vpiDefName:work@flop |vpiDefFile:${SURELOG_DIR}/tests/ArrayInst/dut.sv |vpiDefLineNo:4 |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ArrayInst/dut.sv, line:8:1, endln:10:10 - |vpiModule: - \_module: work@qq (work@top.flop_instances2[2][1].q[0]), file:${SURELOG_DIR}/tests/ArrayInst/dut.sv, line:5:3, endln:5:15 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ArrayInst/dut.sv, line:8:1, endln:10:10 + |vpiModuleInst: + \_module_inst: work@qq (work@top.flop_instances2[2][1].q[0]), file:${SURELOG_DIR}/tests/ArrayInst/dut.sv, line:5:3, endln:5:15 |vpiParent: - \_module: work@flop (work@top.flop_instances2[2][1]), file:${SURELOG_DIR}/tests/ArrayInst/dut.sv, line:9:3, endln:9:60 + \_module_inst: work@flop (work@top.flop_instances2[2][1]), file:${SURELOG_DIR}/tests/ArrayInst/dut.sv, line:9:3, endln:9:60 |vpiName:q[0] |vpiFullName:work@top.flop_instances2[2][1].q[0] |vpiDefName:work@qq |vpiDefFile:${SURELOG_DIR}/tests/ArrayInst/dut.sv |vpiDefLineNo:1 |vpiInstance: - \_module: work@flop (work@top.flop_instances2[2][1]), file:${SURELOG_DIR}/tests/ArrayInst/dut.sv, line:9:3, endln:9:60 - |vpiModule: - \_module: work@qq (work@top.flop_instances2[2][1].q[1]), file:${SURELOG_DIR}/tests/ArrayInst/dut.sv, line:5:3, endln:5:15 + \_module_inst: work@flop (work@top.flop_instances2[2][1]), file:${SURELOG_DIR}/tests/ArrayInst/dut.sv, line:9:3, endln:9:60 + |vpiModuleInst: + \_module_inst: work@qq (work@top.flop_instances2[2][1].q[1]), file:${SURELOG_DIR}/tests/ArrayInst/dut.sv, line:5:3, endln:5:15 |vpiParent: - \_module: work@flop (work@top.flop_instances2[2][1]), file:${SURELOG_DIR}/tests/ArrayInst/dut.sv, line:9:3, endln:9:60 + \_module_inst: work@flop (work@top.flop_instances2[2][1]), file:${SURELOG_DIR}/tests/ArrayInst/dut.sv, line:9:3, endln:9:60 |vpiName:q[1] |vpiFullName:work@top.flop_instances2[2][1].q[1] |vpiDefName:work@qq |vpiDefFile:${SURELOG_DIR}/tests/ArrayInst/dut.sv |vpiDefLineNo:1 |vpiInstance: - \_module: work@flop (work@top.flop_instances2[2][1]), file:${SURELOG_DIR}/tests/ArrayInst/dut.sv, line:9:3, endln:9:60 + \_module_inst: work@flop (work@top.flop_instances2[2][1]), file:${SURELOG_DIR}/tests/ArrayInst/dut.sv, line:9:3, endln:9:60 |vpiModuleArray: \_module_array: (work@qq), line:5:6, endln:5:7 |vpiParent: - \_module: work@flop (work@top.flop_instances2[2][1]), file:${SURELOG_DIR}/tests/ArrayInst/dut.sv, line:9:3, endln:9:60 + \_module_inst: work@flop (work@top.flop_instances2[2][1]), file:${SURELOG_DIR}/tests/ArrayInst/dut.sv, line:9:3, endln:9:60 |vpiName:q |vpiFullName:work@qq |vpiRange: @@ -778,17 +778,17 @@ design: (work@top) |vpiSize:64 |UINT:0 |vpiConstType:9 - |vpiModule: - \_module: work@qq (work@top.flop_instances2[2][1].q[0]), file:${SURELOG_DIR}/tests/ArrayInst/dut.sv, line:5:3, endln:5:15 - |vpiModule: - \_module: work@qq (work@top.flop_instances2[2][1].q[1]), file:${SURELOG_DIR}/tests/ArrayInst/dut.sv, line:5:3, endln:5:15 + |vpiModuleInst: + \_module_inst: work@qq (work@top.flop_instances2[2][1].q[0]), file:${SURELOG_DIR}/tests/ArrayInst/dut.sv, line:5:3, endln:5:15 + |vpiModuleInst: + \_module_inst: work@qq (work@top.flop_instances2[2][1].q[1]), file:${SURELOG_DIR}/tests/ArrayInst/dut.sv, line:5:3, endln:5:15 |vpiElemTypespec: \_module_typespec: (qq), line:5:3, endln:5:5 |vpiName:qq |vpiModuleArray: \_module_array: (work@flop), line:9:8, endln:9:23 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ArrayInst/dut.sv, line:8:1, endln:10:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ArrayInst/dut.sv, line:8:1, endln:10:10 |vpiName:flop_instances1 |vpiFullName:work@flop |vpiRange: @@ -809,17 +809,17 @@ design: (work@top) |vpiSize:64 |UINT:0 |vpiConstType:9 - |vpiModule: - \_module: work@flop (work@top.flop_instances1[0]), file:${SURELOG_DIR}/tests/ArrayInst/dut.sv, line:9:3, endln:9:60 - |vpiModule: - \_module: work@flop (work@top.flop_instances1[1]), file:${SURELOG_DIR}/tests/ArrayInst/dut.sv, line:9:3, endln:9:60 + |vpiModuleInst: + \_module_inst: work@flop (work@top.flop_instances1[0]), file:${SURELOG_DIR}/tests/ArrayInst/dut.sv, line:9:3, endln:9:60 + |vpiModuleInst: + \_module_inst: work@flop (work@top.flop_instances1[1]), file:${SURELOG_DIR}/tests/ArrayInst/dut.sv, line:9:3, endln:9:60 |vpiElemTypespec: \_module_typespec: (flop), line:9:3, endln:9:7 |vpiName:flop |vpiModuleArray: \_module_array: (work@flop), line:9:32, endln:9:47 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ArrayInst/dut.sv, line:8:1, endln:10:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ArrayInst/dut.sv, line:8:1, endln:10:10 |vpiName:flop_instances2 |vpiFullName:work@flop |vpiRange: @@ -858,18 +858,18 @@ design: (work@top) |vpiSize:64 |UINT:0 |vpiConstType:9 - |vpiModule: - \_module: work@flop (work@top.flop_instances2[0][0]), file:${SURELOG_DIR}/tests/ArrayInst/dut.sv, line:9:3, endln:9:60 - |vpiModule: - \_module: work@flop (work@top.flop_instances2[0][1]), file:${SURELOG_DIR}/tests/ArrayInst/dut.sv, line:9:3, endln:9:60 - |vpiModule: - \_module: work@flop (work@top.flop_instances2[1][0]), file:${SURELOG_DIR}/tests/ArrayInst/dut.sv, line:9:3, endln:9:60 - |vpiModule: - \_module: work@flop (work@top.flop_instances2[1][1]), file:${SURELOG_DIR}/tests/ArrayInst/dut.sv, line:9:3, endln:9:60 - |vpiModule: - \_module: work@flop (work@top.flop_instances2[2][0]), file:${SURELOG_DIR}/tests/ArrayInst/dut.sv, line:9:3, endln:9:60 - |vpiModule: - \_module: work@flop (work@top.flop_instances2[2][1]), file:${SURELOG_DIR}/tests/ArrayInst/dut.sv, line:9:3, endln:9:60 + |vpiModuleInst: + \_module_inst: work@flop (work@top.flop_instances2[0][0]), file:${SURELOG_DIR}/tests/ArrayInst/dut.sv, line:9:3, endln:9:60 + |vpiModuleInst: + \_module_inst: work@flop (work@top.flop_instances2[0][1]), file:${SURELOG_DIR}/tests/ArrayInst/dut.sv, line:9:3, endln:9:60 + |vpiModuleInst: + \_module_inst: work@flop (work@top.flop_instances2[1][0]), file:${SURELOG_DIR}/tests/ArrayInst/dut.sv, line:9:3, endln:9:60 + |vpiModuleInst: + \_module_inst: work@flop (work@top.flop_instances2[1][1]), file:${SURELOG_DIR}/tests/ArrayInst/dut.sv, line:9:3, endln:9:60 + |vpiModuleInst: + \_module_inst: work@flop (work@top.flop_instances2[2][0]), file:${SURELOG_DIR}/tests/ArrayInst/dut.sv, line:9:3, endln:9:60 + |vpiModuleInst: + \_module_inst: work@flop (work@top.flop_instances2[2][1]), file:${SURELOG_DIR}/tests/ArrayInst/dut.sv, line:9:3, endln:9:60 |vpiElemTypespec: \_module_typespec: (flop), line:9:3, endln:9:7 |vpiName:flop diff --git a/tests/ArrayMethodIterator/ArrayMethodIterator.log b/tests/ArrayMethodIterator/ArrayMethodIterator.log index 63c5926297..fb3c59ead3 100644 --- a/tests/ArrayMethodIterator/ArrayMethodIterator.log +++ b/tests/ArrayMethodIterator/ArrayMethodIterator.log @@ -195,7 +195,7 @@ int_typespec 1 int_var 1 logic_net 1 method_func_call 1 -module 2 +module_inst 2 package 3 range 2 ref_obj 5 @@ -220,7 +220,7 @@ int_typespec 1 int_var 2 logic_net 1 method_func_call 2 -module 2 +module_inst 2 package 3 range 2 ref_obj 10 @@ -502,7 +502,7 @@ design: (work@top) |vpiName:uvm_object |vpiFullName:pkg::uvm_object |uhdmallModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/ArrayMethodIterator/dut.sv, line:27:1, endln:31:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ArrayMethodIterator/dut.sv, line:27:1, endln:31:10 |vpiParent: \_design: (work@top) |vpiFullName:work@top @@ -510,16 +510,16 @@ design: (work@top) |vpiNet: \_logic_net: (work@top.c1), line:29:20, endln:29:22 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ArrayMethodIterator/dut.sv, line:27:1, endln:31:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ArrayMethodIterator/dut.sv, line:27:1, endln:31:10 |vpiName:c1 |vpiFullName:work@top.c1 |uhdmtopModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/ArrayMethodIterator/dut.sv, line:27:1, endln:31:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ArrayMethodIterator/dut.sv, line:27:1, endln:31:10 |vpiName:work@top |vpiVariables: \_class_var: (work@top.c1), line:29:20, endln:29:22 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ArrayMethodIterator/dut.sv, line:27:1, endln:31:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ArrayMethodIterator/dut.sv, line:27:1, endln:31:10 |vpiTypespec: \_class_typespec: (pkg::uvm_callbacks), line:29:1, endln:29:6 |vpiParent: diff --git a/tests/ArrayNet/ArrayNet.log b/tests/ArrayNet/ArrayNet.log index 59cd528dae..7e7c3b1d21 100644 --- a/tests/ArrayNet/ArrayNet.log +++ b/tests/ArrayNet/ArrayNet.log @@ -102,7 +102,7 @@ design 1 initial 1 logic_net 2 logic_typespec 1 -module 3 +module_inst 3 range 3 ref_obj 1 sys_func_call 1 @@ -117,7 +117,7 @@ design 1 initial 2 logic_net 2 logic_typespec 1 -module 3 +module_inst 3 range 3 ref_obj 2 sys_func_call 2 @@ -135,7 +135,7 @@ design: (work@memory) |vpiElaborated:1 |vpiName:work@memory |uhdmallModules: -\_module: work@memory (work@memory), file:${SURELOG_DIR}/tests/ArrayNet/dut.sv, line:1:1, endln:7:10 +\_module_inst: work@memory (work@memory), file:${SURELOG_DIR}/tests/ArrayNet/dut.sv, line:1:1, endln:7:10 |vpiParent: \_design: (work@memory) |vpiFullName:work@memory @@ -143,14 +143,14 @@ design: (work@memory) |vpiNet: \_logic_net: (work@memory.my_memory), line:2:11, endln:2:20 |vpiParent: - \_module: work@memory (work@memory), file:${SURELOG_DIR}/tests/ArrayNet/dut.sv, line:1:1, endln:7:10 + \_module_inst: work@memory (work@memory), file:${SURELOG_DIR}/tests/ArrayNet/dut.sv, line:1:1, endln:7:10 |vpiName:my_memory |vpiFullName:work@memory.my_memory |vpiNetType:48 |vpiProcess: \_initial: , line:4:1, endln:6:4 |vpiParent: - \_module: work@memory (work@memory), file:${SURELOG_DIR}/tests/ArrayNet/dut.sv, line:1:1, endln:7:10 + \_module_inst: work@memory (work@memory), file:${SURELOG_DIR}/tests/ArrayNet/dut.sv, line:1:1, endln:7:10 |vpiStmt: \_begin: (work@memory), line:4:9, endln:6:4 |vpiParent: @@ -178,14 +178,14 @@ design: (work@memory) \_array_net: (work@memory.my_memory), line:2:11, endln:2:20 |vpiName:$readmemh |uhdmtopModules: -\_module: work@memory (work@memory), file:${SURELOG_DIR}/tests/ArrayNet/dut.sv, line:1:1, endln:7:10 +\_module_inst: work@memory (work@memory), file:${SURELOG_DIR}/tests/ArrayNet/dut.sv, line:1:1, endln:7:10 |vpiName:work@memory |vpiDefName:work@memory |vpiTop:1 |vpiArrayNet: \_array_net: (work@memory.my_memory), line:2:11, endln:2:20 |vpiParent: - \_module: work@memory (work@memory), file:${SURELOG_DIR}/tests/ArrayNet/dut.sv, line:1:1, endln:7:10 + \_module_inst: work@memory (work@memory), file:${SURELOG_DIR}/tests/ArrayNet/dut.sv, line:1:1, endln:7:10 |vpiSize:256 |vpiName:my_memory |vpiFullName:work@memory.my_memory @@ -237,7 +237,7 @@ design: (work@memory) |vpiProcess: \_initial: , line:4:1, endln:6:4 |vpiParent: - \_module: work@memory (work@memory), file:${SURELOG_DIR}/tests/ArrayNet/dut.sv, line:1:1, endln:7:10 + \_module_inst: work@memory (work@memory), file:${SURELOG_DIR}/tests/ArrayNet/dut.sv, line:1:1, endln:7:10 |vpiStmt: \_begin: (work@memory), line:4:9, endln:6:4 |vpiParent: diff --git a/tests/ArrayTypespec/ArrayTypespec.log b/tests/ArrayTypespec/ArrayTypespec.log index 9df28c25c3..2af74f9fe6 100644 --- a/tests/ArrayTypespec/ArrayTypespec.log +++ b/tests/ArrayTypespec/ArrayTypespec.log @@ -68,7 +68,7 @@ array_typespec 4 constant 30 design 1 int_typespec 4 -module 4 +module_inst 4 operation 10 param_assign 2 parameter 3 @@ -81,7 +81,7 @@ array_typespec 4 constant 30 design 1 int_typespec 4 -module 4 +module_inst 4 operation 10 param_assign 2 parameter 3 @@ -100,14 +100,14 @@ design: (work@top) |vpiElaborated:1 |vpiName:work@top |uhdmallModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/ArrayTypespec/dut.sv, line:1:1, endln:3:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ArrayTypespec/dut.sv, line:1:1, endln:3:10 |vpiParent: \_design: (work@top) |vpiFullName:work@top |vpiParameter: \_parameter: (work@top.P), line:2:19, endln:2:20 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ArrayTypespec/dut.sv, line:1:1, endln:3:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ArrayTypespec/dut.sv, line:1:1, endln:3:10 |vpiSize:1 |vpiTypespec: \_array_typespec: @@ -153,7 +153,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:2:19, endln:2:36 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ArrayTypespec/dut.sv, line:1:1, endln:3:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ArrayTypespec/dut.sv, line:1:1, endln:3:10 |vpiRhs: \_operation: , line:2:27, endln:2:36 |vpiOpType:75 @@ -173,12 +173,12 @@ design: (work@top) \_parameter: (work@top.P), line:2:19, endln:2:20 |vpiDefName:work@top |uhdmtopModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/ArrayTypespec/dut.sv, line:1:1, endln:3:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ArrayTypespec/dut.sv, line:1:1, endln:3:10 |vpiName:work@top |vpiParameter: \_parameter: (work@top.P), line:2:19, endln:2:20 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ArrayTypespec/dut.sv, line:1:1, endln:3:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ArrayTypespec/dut.sv, line:1:1, endln:3:10 |vpiSize:1 |vpiTypespec: \_array_typespec: @@ -260,7 +260,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:2:19, endln:2:36 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ArrayTypespec/dut.sv, line:1:1, endln:3:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ArrayTypespec/dut.sv, line:1:1, endln:3:10 |vpiRhs: \_operation: , line:2:27, endln:2:36 |vpiParent: diff --git a/tests/ArrayVarName/ArrayVarName.log b/tests/ArrayVarName/ArrayVarName.log index 93389cb2c1..59dc8042eb 100644 --- a/tests/ArrayVarName/ArrayVarName.log +++ b/tests/ArrayVarName/ArrayVarName.log @@ -125,7 +125,7 @@ function 1 int_typespec 5 int_var 3 logic_net 1 -module 4 +module_inst 4 operation 2 param_assign 2 parameter 2 @@ -150,7 +150,7 @@ function 2 int_typespec 5 int_var 6 logic_net 1 -module 4 +module_inst 4 operation 3 param_assign 2 parameter 2 @@ -172,7 +172,7 @@ design: (work@top) |vpiElaborated:1 |vpiName:work@top |uhdmallModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/ArrayVarName/dut.sv, line:1:1, endln:8:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ArrayVarName/dut.sv, line:1:1, endln:8:10 |vpiParent: \_design: (work@top) |vpiFullName:work@top @@ -180,7 +180,7 @@ design: (work@top) |vpiTaskFunc: \_function: (work@top.get_a1), line:4:4, endln:7:15 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ArrayVarName/dut.sv, line:1:1, endln:8:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ArrayVarName/dut.sv, line:1:1, endln:8:10 |vpiName:get_a1 |vpiFullName:work@top.get_a1 |vpiVariables: @@ -235,7 +235,7 @@ design: (work@top) |vpiSigned:1 |vpiSigned:1 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ArrayVarName/dut.sv, line:1:1, endln:8:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ArrayVarName/dut.sv, line:1:1, endln:8:10 |vpiStmt: \_begin: (work@top.get_a1) |vpiParent: @@ -289,17 +289,17 @@ design: (work@top) |UINT:1 |vpiConstType:9 |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ArrayVarName/dut.sv, line:1:1, endln:8:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ArrayVarName/dut.sv, line:1:1, endln:8:10 |vpiNet: \_logic_net: (work@top.o), line:1:23, endln:1:24 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ArrayVarName/dut.sv, line:1:1, endln:8:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ArrayVarName/dut.sv, line:1:1, endln:8:10 |vpiName:o |vpiFullName:work@top.o |vpiPort: \_port: (o), line:1:23, endln:1:24 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ArrayVarName/dut.sv, line:1:1, endln:8:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ArrayVarName/dut.sv, line:1:1, endln:8:10 |vpiName:o |vpiDirection:2 |vpiLowConn: @@ -312,7 +312,7 @@ design: (work@top) |vpiContAssign: \_cont_assign: , line:2:11, endln:2:23 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ArrayVarName/dut.sv, line:1:1, endln:8:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ArrayVarName/dut.sv, line:1:1, endln:8:10 |vpiRhs: \_func_call: (get_a1), line:2:15, endln:2:23 |vpiParent: @@ -329,12 +329,12 @@ design: (work@top) |vpiActual: \_int_var: (work@top.o), line:1:23, endln:1:24 |uhdmtopModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/ArrayVarName/dut.sv, line:1:1, endln:8:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ArrayVarName/dut.sv, line:1:1, endln:8:10 |vpiName:work@top |vpiVariables: \_int_var: (work@top.o), line:1:23, endln:1:24 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ArrayVarName/dut.sv, line:1:1, endln:8:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ArrayVarName/dut.sv, line:1:1, endln:8:10 |vpiTypespec: \_int_typespec: , line:1:19, endln:1:22 |vpiSigned:1 @@ -347,7 +347,7 @@ design: (work@top) |vpiTaskFunc: \_function: (work@top.get_a1), line:4:4, endln:7:15 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ArrayVarName/dut.sv, line:1:1, endln:8:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ArrayVarName/dut.sv, line:1:1, endln:8:10 |vpiName:get_a1 |vpiFullName:work@top.get_a1 |vpiVariables: @@ -372,7 +372,7 @@ design: (work@top) |vpiReturn: \_int_var: , line:4:23, endln:4:26 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ArrayVarName/dut.sv, line:1:1, endln:8:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ArrayVarName/dut.sv, line:1:1, endln:8:10 |vpiStmt: \_begin: (work@top.get_a1) |vpiParent: @@ -446,12 +446,12 @@ design: (work@top) |vpiActual: \_array_var: (work@top.get_a1.a), line:5:11, endln:5:12 |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ArrayVarName/dut.sv, line:1:1, endln:8:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ArrayVarName/dut.sv, line:1:1, endln:8:10 |vpiTopModule:1 |vpiPort: \_port: (o), line:1:23, endln:1:24 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ArrayVarName/dut.sv, line:1:1, endln:8:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ArrayVarName/dut.sv, line:1:1, endln:8:10 |vpiName:o |vpiDirection:2 |vpiLowConn: @@ -466,11 +466,11 @@ design: (work@top) \_int_typespec: , line:1:19, endln:1:22 |vpiSigned:1 |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ArrayVarName/dut.sv, line:1:1, endln:8:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ArrayVarName/dut.sv, line:1:1, endln:8:10 |vpiContAssign: \_cont_assign: , line:2:11, endln:2:23 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ArrayVarName/dut.sv, line:1:1, endln:8:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ArrayVarName/dut.sv, line:1:1, endln:8:10 |vpiRhs: \_constant: , line:5:24, endln:5:25 |vpiParent: diff --git a/tests/Assert/Assert.log b/tests/Assert/Assert.log index a5953c3d20..be3c4eaf0f 100644 --- a/tests/Assert/Assert.log +++ b/tests/Assert/Assert.log @@ -77,7 +77,7 @@ n<> u<50> t c<1> l<1:1> el<8:1> assert_stmt 1 design 1 logic_net 1 -module 2 +module_inst 2 operation 1 property_spec 1 ref_obj 1 @@ -88,7 +88,7 @@ ref_obj 1 assert_stmt 2 design 1 logic_net 1 -module 2 +module_inst 2 operation 2 property_spec 2 ref_obj 2 @@ -106,7 +106,7 @@ design: (work@dut) |vpiElaborated:1 |vpiName:work@dut |uhdmallModules: -\_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/Assert/dut.sv, line:1:1, endln:7:10 +\_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/Assert/dut.sv, line:1:1, endln:7:10 |vpiParent: \_design: (work@dut) |vpiFullName:work@dut @@ -114,7 +114,7 @@ design: (work@dut) |vpiAssertion: \_assert_stmt: (work@dut), line:4:1, endln:4:73 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/Assert/dut.sv, line:1:1, endln:7:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/Assert/dut.sv, line:1:1, endln:7:10 |vpiFullName:work@dut |vpiProperty: \_property_spec: , line:4:19, endln:4:71 @@ -129,7 +129,7 @@ design: (work@dut) |vpiActual: \_logic_net: (Clock) |uhdmtopModules: -\_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/Assert/dut.sv, line:1:1, endln:7:10 +\_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/Assert/dut.sv, line:1:1, endln:7:10 |vpiName:work@dut |vpiDefName:work@dut |vpiTop:1 @@ -140,7 +140,7 @@ design: (work@dut) |vpiAssertion: \_assert_stmt: (work@dut), line:4:1, endln:4:73 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/Assert/dut.sv, line:1:1, endln:7:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/Assert/dut.sv, line:1:1, endln:7:10 |vpiFullName:work@dut |vpiProperty: \_property_spec: , line:4:19, endln:4:71 diff --git a/tests/Assertions/Assertions.log b/tests/Assertions/Assertions.log index a9fbc7ad15..8bd616bbad 100644 --- a/tests/Assertions/Assertions.log +++ b/tests/Assertions/Assertions.log @@ -468,7 +468,7 @@ immediate_assert 1 logic_net 6 logic_typespec 5 logic_var 4 -module 3 +module_inst 3 operation 4 packed_array_typespec 1 port 2 @@ -488,7 +488,7 @@ immediate_assert 2 logic_net 6 logic_typespec 5 logic_var 4 -module 3 +module_inst 3 operation 8 packed_array_typespec 1 port 3 @@ -509,17 +509,17 @@ design: (work@m) |vpiElaborated:1 |vpiName:work@m |uhdmallModules: -\_module: work@m (work@m), file:${SURELOG_DIR}/tests/Assertions/dut.sv, line:1:1, endln:13:14 +\_module_inst: work@m (work@m), file:${SURELOG_DIR}/tests/Assertions/dut.sv, line:1:1, endln:13:14 |vpiParent: \_design: (work@m) |vpiFullName:work@m |vpiTypedef: \_bit_typespec: (bits), line:4:9, endln:4:19 |vpiParent: - \_module: work@m (work@m), file:${SURELOG_DIR}/tests/Assertions/dut.sv, line:1:1, endln:13:14 + \_module_inst: work@m (work@m), file:${SURELOG_DIR}/tests/Assertions/dut.sv, line:1:1, endln:13:14 |vpiName:bits |vpiInstance: - \_module: work@m (work@m), file:${SURELOG_DIR}/tests/Assertions/dut.sv, line:1:1, endln:13:14 + \_module_inst: work@m (work@m), file:${SURELOG_DIR}/tests/Assertions/dut.sv, line:1:1, endln:13:14 |vpiRange: \_range: , line:4:13, endln:4:19 |vpiLeftRange: @@ -543,41 +543,41 @@ design: (work@m) |vpiNet: \_logic_net: (work@m.clock), line:1:16, endln:1:21 |vpiParent: - \_module: work@m (work@m), file:${SURELOG_DIR}/tests/Assertions/dut.sv, line:1:1, endln:13:14 + \_module_inst: work@m (work@m), file:${SURELOG_DIR}/tests/Assertions/dut.sv, line:1:1, endln:13:14 |vpiName:clock |vpiFullName:work@m.clock |vpiNet: \_logic_net: (work@m.a), line:2:14, endln:2:15 |vpiParent: - \_module: work@m (work@m), file:${SURELOG_DIR}/tests/Assertions/dut.sv, line:1:1, endln:13:14 + \_module_inst: work@m (work@m), file:${SURELOG_DIR}/tests/Assertions/dut.sv, line:1:1, endln:13:14 |vpiName:a |vpiFullName:work@m.a |vpiNetType:36 |vpiNet: \_logic_net: (work@m.b), line:2:17, endln:2:18 |vpiParent: - \_module: work@m (work@m), file:${SURELOG_DIR}/tests/Assertions/dut.sv, line:1:1, endln:13:14 + \_module_inst: work@m (work@m), file:${SURELOG_DIR}/tests/Assertions/dut.sv, line:1:1, endln:13:14 |vpiName:b |vpiFullName:work@m.b |vpiNetType:36 |vpiNet: \_logic_net: (work@m.c), line:3:7, endln:3:8 |vpiParent: - \_module: work@m (work@m), file:${SURELOG_DIR}/tests/Assertions/dut.sv, line:1:1, endln:13:14 + \_module_inst: work@m (work@m), file:${SURELOG_DIR}/tests/Assertions/dut.sv, line:1:1, endln:13:14 |vpiName:c |vpiFullName:work@m.c |vpiNetType:36 |vpiNet: \_logic_net: (work@m.d), line:3:10, endln:3:11 |vpiParent: - \_module: work@m (work@m), file:${SURELOG_DIR}/tests/Assertions/dut.sv, line:1:1, endln:13:14 + \_module_inst: work@m (work@m), file:${SURELOG_DIR}/tests/Assertions/dut.sv, line:1:1, endln:13:14 |vpiName:d |vpiFullName:work@m.d |vpiNetType:36 |vpiAssertion: \_assert_stmt: (work@m.a2), line:12:1, endln:12:54 |vpiParent: - \_module: work@m (work@m), file:${SURELOG_DIR}/tests/Assertions/dut.sv, line:1:1, endln:13:14 + \_module_inst: work@m (work@m), file:${SURELOG_DIR}/tests/Assertions/dut.sv, line:1:1, endln:13:14 |vpiName:a2 |vpiFullName:work@m.a2 |vpiProperty: @@ -595,7 +595,7 @@ design: (work@m) |vpiPort: \_port: (clock), line:1:16, endln:1:21 |vpiParent: - \_module: work@m (work@m), file:${SURELOG_DIR}/tests/Assertions/dut.sv, line:1:1, endln:13:14 + \_module_inst: work@m (work@m), file:${SURELOG_DIR}/tests/Assertions/dut.sv, line:1:1, endln:13:14 |vpiName:clock |vpiDirection:1 |vpiLowConn: @@ -607,7 +607,7 @@ design: (work@m) |vpiProcess: \_always: , line:7:1, endln:8:35 |vpiParent: - \_module: work@m (work@m), file:${SURELOG_DIR}/tests/Assertions/dut.sv, line:1:1, endln:13:14 + \_module_inst: work@m (work@m), file:${SURELOG_DIR}/tests/Assertions/dut.sv, line:1:1, endln:13:14 |vpiStmt: \_immediate_assert: (a1), line:8:1, endln:8:35 |vpiParent: @@ -698,12 +698,12 @@ design: (work@m) \_logic_var: (work@m.b), line:2:17, endln:2:18 |vpiAlwaysType:2 |uhdmtopModules: -\_module: work@m (work@m), file:${SURELOG_DIR}/tests/Assertions/dut.sv, line:1:1, endln:13:14 +\_module_inst: work@m (work@m), file:${SURELOG_DIR}/tests/Assertions/dut.sv, line:1:1, endln:13:14 |vpiName:work@m |vpiVariables: \_logic_var: (work@m.a), line:2:14, endln:2:15 |vpiParent: - \_module: work@m (work@m), file:${SURELOG_DIR}/tests/Assertions/dut.sv, line:1:1, endln:13:14 + \_module_inst: work@m (work@m), file:${SURELOG_DIR}/tests/Assertions/dut.sv, line:1:1, endln:13:14 |vpiTypespec: \_logic_typespec: , line:2:1, endln:2:13 |vpiRange: @@ -748,7 +748,7 @@ design: (work@m) |vpiVariables: \_logic_var: (work@m.b), line:2:17, endln:2:18 |vpiParent: - \_module: work@m (work@m), file:${SURELOG_DIR}/tests/Assertions/dut.sv, line:1:1, endln:13:14 + \_module_inst: work@m (work@m), file:${SURELOG_DIR}/tests/Assertions/dut.sv, line:1:1, endln:13:14 |vpiTypespec: \_logic_typespec: , line:2:1, endln:2:13 |vpiName:b @@ -775,7 +775,7 @@ design: (work@m) |vpiVariables: \_logic_var: (work@m.c), line:3:7, endln:3:8 |vpiParent: - \_module: work@m (work@m), file:${SURELOG_DIR}/tests/Assertions/dut.sv, line:1:1, endln:13:14 + \_module_inst: work@m (work@m), file:${SURELOG_DIR}/tests/Assertions/dut.sv, line:1:1, endln:13:14 |vpiTypespec: \_logic_typespec: , line:3:1, endln:3:6 |vpiName:c @@ -784,7 +784,7 @@ design: (work@m) |vpiVariables: \_logic_var: (work@m.d), line:3:10, endln:3:11 |vpiParent: - \_module: work@m (work@m), file:${SURELOG_DIR}/tests/Assertions/dut.sv, line:1:1, endln:13:14 + \_module_inst: work@m (work@m), file:${SURELOG_DIR}/tests/Assertions/dut.sv, line:1:1, endln:13:14 |vpiTypespec: \_logic_typespec: , line:3:1, endln:3:6 |vpiName:d @@ -797,7 +797,7 @@ design: (work@m) |vpiNet: \_logic_net: (work@m.clock), line:1:16, endln:1:21 |vpiParent: - \_module: work@m (work@m), file:${SURELOG_DIR}/tests/Assertions/dut.sv, line:1:1, endln:13:14 + \_module_inst: work@m (work@m), file:${SURELOG_DIR}/tests/Assertions/dut.sv, line:1:1, endln:13:14 |vpiTypespec: \_logic_typespec: , line:1:16, endln:1:16 |vpiName:clock @@ -805,7 +805,7 @@ design: (work@m) |vpiAssertion: \_assert_stmt: (work@m.a2), line:12:1, endln:12:54 |vpiParent: - \_module: work@m (work@m), file:${SURELOG_DIR}/tests/Assertions/dut.sv, line:1:1, endln:13:14 + \_module_inst: work@m (work@m), file:${SURELOG_DIR}/tests/Assertions/dut.sv, line:1:1, endln:13:14 |vpiName:a2 |vpiFullName:work@m.a2 |vpiProperty: @@ -829,7 +829,7 @@ design: (work@m) |vpiPort: \_port: (clock), line:1:16, endln:1:21 |vpiParent: - \_module: work@m (work@m), file:${SURELOG_DIR}/tests/Assertions/dut.sv, line:1:1, endln:13:14 + \_module_inst: work@m (work@m), file:${SURELOG_DIR}/tests/Assertions/dut.sv, line:1:1, endln:13:14 |vpiName:clock |vpiDirection:1 |vpiLowConn: @@ -843,11 +843,11 @@ design: (work@m) |vpiTypedef: \_logic_typespec: , line:1:16, endln:1:16 |vpiInstance: - \_module: work@m (work@m), file:${SURELOG_DIR}/tests/Assertions/dut.sv, line:1:1, endln:13:14 + \_module_inst: work@m (work@m), file:${SURELOG_DIR}/tests/Assertions/dut.sv, line:1:1, endln:13:14 |vpiProcess: \_always: , line:7:1, endln:8:35 |vpiParent: - \_module: work@m (work@m), file:${SURELOG_DIR}/tests/Assertions/dut.sv, line:1:1, endln:13:14 + \_module_inst: work@m (work@m), file:${SURELOG_DIR}/tests/Assertions/dut.sv, line:1:1, endln:13:14 |vpiStmt: \_immediate_assert: (a1), line:8:1, endln:8:35 |vpiParent: diff --git a/tests/AssignPattern/AssignPattern.log b/tests/AssignPattern/AssignPattern.log index 47f8ab95c7..4bad934842 100644 --- a/tests/AssignPattern/AssignPattern.log +++ b/tests/AssignPattern/AssignPattern.log @@ -88,7 +88,7 @@ cont_assign 2 design 1 integer_typespec 1 logic_net 2 -module 3 +module_inst 3 operation 3 ref_obj 2 tagged_pattern 1 @@ -101,7 +101,7 @@ cont_assign 4 design 1 integer_typespec 1 logic_net 2 -module 3 +module_inst 3 operation 6 ref_obj 4 tagged_pattern 1 @@ -119,7 +119,7 @@ design: (work@top) |vpiElaborated:1 |vpiName:work@top |uhdmallModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/AssignPattern/dut.sv, line:1:1, endln:4:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/AssignPattern/dut.sv, line:1:1, endln:4:10 |vpiParent: \_design: (work@top) |vpiFullName:work@top @@ -127,7 +127,7 @@ design: (work@top) |vpiContAssign: \_cont_assign: , line:2:11, endln:2:22 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/AssignPattern/dut.sv, line:1:1, endln:4:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/AssignPattern/dut.sv, line:1:1, endln:4:10 |vpiRhs: \_operation: , line:2:16, endln:2:22 |vpiParent: @@ -155,7 +155,7 @@ design: (work@top) |vpiContAssign: \_cont_assign: , line:3:11, endln:3:23 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/AssignPattern/dut.sv, line:1:1, endln:4:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/AssignPattern/dut.sv, line:1:1, endln:4:10 |vpiRhs: \_operation: , line:3:16, endln:3:23 |vpiParent: @@ -189,7 +189,7 @@ design: (work@top) |vpiActual: \_logic_net: (uu) |uhdmtopModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/AssignPattern/dut.sv, line:1:1, endln:4:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/AssignPattern/dut.sv, line:1:1, endln:4:10 |vpiName:work@top |vpiDefName:work@top |vpiTop:1 @@ -205,7 +205,7 @@ design: (work@top) |vpiContAssign: \_cont_assign: , line:2:11, endln:2:22 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/AssignPattern/dut.sv, line:1:1, endln:4:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/AssignPattern/dut.sv, line:1:1, endln:4:10 |vpiRhs: \_operation: , line:2:16, endln:2:22 |vpiParent: @@ -224,7 +224,7 @@ design: (work@top) |vpiContAssign: \_cont_assign: , line:3:11, endln:3:23 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/AssignPattern/dut.sv, line:1:1, endln:4:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/AssignPattern/dut.sv, line:1:1, endln:4:10 |vpiRhs: \_operation: , line:3:16, endln:3:23 |vpiParent: diff --git a/tests/AssignPlus/AssignPlus.log b/tests/AssignPlus/AssignPlus.log index 228d0f0404..6d2bb08daa 100644 --- a/tests/AssignPlus/AssignPlus.log +++ b/tests/AssignPlus/AssignPlus.log @@ -212,7 +212,7 @@ design 1 gen_scope 10 gen_scope_array 10 int_typespec 7 -module 6 +module_inst 6 operation 46 param_assign 2 parameter 7 @@ -228,7 +228,7 @@ design 1 gen_scope 15 gen_scope_array 15 int_typespec 7 -module 6 +module_inst 6 operation 86 param_assign 2 parameter 7 @@ -247,14 +247,14 @@ design: (work@top) |vpiElaborated:1 |vpiName:work@top |uhdmallModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/AssignPlus/dut.sv, line:1:1, endln:11:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/AssignPlus/dut.sv, line:1:1, endln:11:10 |vpiParent: \_design: (work@top) |vpiFullName:work@top |vpiParameter: \_parameter: (work@top.bht_row_width_p), line:3:14, endln:3:29 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/AssignPlus/dut.sv, line:1:1, endln:11:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/AssignPlus/dut.sv, line:1:1, endln:11:10 |UINT:10 |vpiTypespec: \_int_typespec: @@ -263,7 +263,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:3:14, endln:3:34 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/AssignPlus/dut.sv, line:1:1, endln:11:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/AssignPlus/dut.sv, line:1:1, endln:11:10 |vpiRhs: \_constant: , line:3:32, endln:3:34 |vpiDecompile:10 @@ -276,12 +276,12 @@ design: (work@top) \_parameter: (work@top.bht_row_width_p), line:3:14, endln:3:29 |vpiDefName:work@top |uhdmtopModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/AssignPlus/dut.sv, line:1:1, endln:11:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/AssignPlus/dut.sv, line:1:1, endln:11:10 |vpiName:work@top |vpiParameter: \_parameter: (work@top.bht_row_width_p), line:3:14, endln:3:29 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/AssignPlus/dut.sv, line:1:1, endln:11:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/AssignPlus/dut.sv, line:1:1, endln:11:10 |UINT:10 |vpiTypespec: \_int_typespec: @@ -292,7 +292,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:3:14, endln:3:34 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/AssignPlus/dut.sv, line:1:1, endln:11:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/AssignPlus/dut.sv, line:1:1, endln:11:10 |vpiRhs: \_constant: , line:3:32, endln:3:34 |vpiDecompile:10 @@ -309,7 +309,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.wval[0]), line:6:5, endln:9:8 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/AssignPlus/dut.sv, line:1:1, endln:11:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/AssignPlus/dut.sv, line:1:1, endln:11:10 |vpiName:wval[0] |vpiFullName:work@top.wval[0] |vpiGenScope: @@ -526,7 +526,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.wval[2]), line:6:5, endln:9:8 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/AssignPlus/dut.sv, line:1:1, endln:11:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/AssignPlus/dut.sv, line:1:1, endln:11:10 |vpiName:wval[2] |vpiFullName:work@top.wval[2] |vpiGenScope: @@ -743,7 +743,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.wval[4]), line:6:5, endln:9:8 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/AssignPlus/dut.sv, line:1:1, endln:11:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/AssignPlus/dut.sv, line:1:1, endln:11:10 |vpiName:wval[4] |vpiFullName:work@top.wval[4] |vpiGenScope: @@ -960,7 +960,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.wval[6]), line:6:5, endln:9:8 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/AssignPlus/dut.sv, line:1:1, endln:11:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/AssignPlus/dut.sv, line:1:1, endln:11:10 |vpiName:wval[6] |vpiFullName:work@top.wval[6] |vpiGenScope: @@ -1177,7 +1177,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.wval[8]), line:6:5, endln:9:8 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/AssignPlus/dut.sv, line:1:1, endln:11:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/AssignPlus/dut.sv, line:1:1, endln:11:10 |vpiName:wval[8] |vpiFullName:work@top.wval[8] |vpiGenScope: diff --git a/tests/AssignRhsFlat/AssignRhsFlat.log b/tests/AssignRhsFlat/AssignRhsFlat.log index 2f98a6c4ea..9eeeff9752 100644 --- a/tests/AssignRhsFlat/AssignRhsFlat.log +++ b/tests/AssignRhsFlat/AssignRhsFlat.log @@ -142,7 +142,7 @@ design 1 int_typespec 6 logic_net 1 logic_typespec 2 -module 2 +module_inst 2 operation 10 ref_obj 2 string_typespec 9 @@ -160,7 +160,7 @@ design 1 int_typespec 6 logic_net 1 logic_typespec 2 -module 2 +module_inst 2 operation 16 ref_obj 3 string_typespec 9 @@ -182,17 +182,17 @@ design: (work@dut) |vpiElaborated:1 |vpiName:work@dut |uhdmallModules: -\_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/AssignRhsFlat/dut.sv, line:1:1, endln:13:10 +\_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/AssignRhsFlat/dut.sv, line:1:1, endln:13:10 |vpiParent: \_design: (work@dut) |vpiFullName:work@dut |vpiTypedef: \_struct_typespec: (ABC), line:2:9, endln:2:15 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/AssignRhsFlat/dut.sv, line:1:1, endln:13:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/AssignRhsFlat/dut.sv, line:1:1, endln:13:10 |vpiName:ABC |vpiInstance: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/AssignRhsFlat/dut.sv, line:1:1, endln:13:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/AssignRhsFlat/dut.sv, line:1:1, endln:13:10 |vpiTypespecMember: \_typespec_member: (A), line:3:7, endln:3:8 |vpiParent: @@ -298,13 +298,13 @@ design: (work@dut) |vpiNet: \_logic_net: (work@dut.test), line:10:5, endln:10:9 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/AssignRhsFlat/dut.sv, line:1:1, endln:13:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/AssignRhsFlat/dut.sv, line:1:1, endln:13:10 |vpiName:test |vpiFullName:work@dut.test |vpiContAssign: \_cont_assign: , line:12:8, endln:12:61 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/AssignRhsFlat/dut.sv, line:1:1, endln:13:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/AssignRhsFlat/dut.sv, line:1:1, endln:13:10 |vpiRhs: \_operation: , line:12:15, endln:12:61 |vpiParent: @@ -373,12 +373,12 @@ design: (work@dut) |vpiActual: \_struct_var: (work@dut.test), line:10:5, endln:10:9 |uhdmtopModules: -\_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/AssignRhsFlat/dut.sv, line:1:1, endln:13:10 +\_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/AssignRhsFlat/dut.sv, line:1:1, endln:13:10 |vpiName:work@dut |vpiVariables: \_struct_var: (work@dut.test), line:10:5, endln:10:9 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/AssignRhsFlat/dut.sv, line:1:1, endln:13:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/AssignRhsFlat/dut.sv, line:1:1, endln:13:10 |vpiTypespec: \_struct_typespec: (ABC), line:2:9, endln:2:15 |vpiName:test @@ -392,7 +392,7 @@ design: (work@dut) |vpiContAssign: \_cont_assign: , line:12:8, endln:12:61 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/AssignRhsFlat/dut.sv, line:1:1, endln:13:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/AssignRhsFlat/dut.sv, line:1:1, endln:13:10 |vpiRhs: \_operation: , line:12:15, endln:12:61 |vpiParent: diff --git a/tests/AssignSubs/AssignSubs.log b/tests/AssignSubs/AssignSubs.log index f9c4683fab..3b82c6d911 100644 --- a/tests/AssignSubs/AssignSubs.log +++ b/tests/AssignSubs/AssignSubs.log @@ -208,7 +208,7 @@ int_typespec 1 logic_net 3 logic_typespec 6 logic_var 1 -module 6 +module_inst 6 operation 5 package 3 parameter 1 @@ -237,7 +237,7 @@ int_typespec 1 logic_net 3 logic_typespec 6 logic_var 1 -module 6 +module_inst 6 operation 7 package 3 parameter 1 @@ -308,7 +308,7 @@ design: (work@dut) |vpiTypedef: \_enum_typespec: (pkg::priv_lvl_e), line:2:2, endln:4:16 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/AssignSubs/dut.sv, line:7:1, endln:19:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/AssignSubs/dut.sv, line:7:1, endln:19:10 |vpiName:pkg::priv_lvl_e |vpiInstance: \_package: pkg (pkg::), file:${SURELOG_DIR}/tests/AssignSubs/dut.sv, line:1:1, endln:5:11 @@ -343,7 +343,7 @@ design: (work@dut) |vpiDefName:pkg |vpiTop:1 |uhdmallModules: -\_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/AssignSubs/dut.sv, line:7:1, endln:19:10 +\_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/AssignSubs/dut.sv, line:7:1, endln:19:10 |vpiParent: \_design: (work@dut) |vpiFullName:work@dut @@ -355,20 +355,20 @@ design: (work@dut) |vpiNet: \_logic_net: (work@dut.c), line:12:14, endln:12:15 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/AssignSubs/dut.sv, line:7:1, endln:19:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/AssignSubs/dut.sv, line:7:1, endln:19:10 |vpiName:c |vpiFullName:work@dut.c |vpiNetType:36 |vpiNet: \_logic_net: (work@dut.a0), line:7:12, endln:7:14 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/AssignSubs/dut.sv, line:7:1, endln:19:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/AssignSubs/dut.sv, line:7:1, endln:19:10 |vpiName:a0 |vpiFullName:work@dut.a0 |vpiPort: \_port: (a0), line:7:12, endln:7:14 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/AssignSubs/dut.sv, line:7:1, endln:19:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/AssignSubs/dut.sv, line:7:1, endln:19:10 |vpiName:a0 |vpiDirection:1 |vpiLowConn: @@ -378,12 +378,12 @@ design: (work@dut) |vpiTypedef: \_logic_typespec: , line:8:8, endln:8:8 |uhdmtopModules: -\_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/AssignSubs/dut.sv, line:7:1, endln:19:10 +\_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/AssignSubs/dut.sv, line:7:1, endln:19:10 |vpiName:work@dut |vpiVariables: \_array_var: (work@dut.c), line:12:14, endln:12:19 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/AssignSubs/dut.sv, line:7:1, endln:19:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/AssignSubs/dut.sv, line:7:1, endln:19:10 |vpiSize:4 |vpiTypespec: \_array_typespec: @@ -470,7 +470,7 @@ design: (work@dut) |vpiNet: \_logic_net: (work@dut.a0), line:7:12, endln:7:14 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/AssignSubs/dut.sv, line:7:1, endln:19:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/AssignSubs/dut.sv, line:7:1, endln:19:10 |vpiTypespec: \_logic_typespec: , line:8:8, endln:8:8 |vpiName:a0 @@ -479,7 +479,7 @@ design: (work@dut) |vpiPort: \_port: (a0), line:7:12, endln:7:14 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/AssignSubs/dut.sv, line:7:1, endln:19:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/AssignSubs/dut.sv, line:7:1, endln:19:10 |vpiName:a0 |vpiDirection:1 |vpiLowConn: @@ -493,11 +493,11 @@ design: (work@dut) |vpiTypedef: \_logic_typespec: , line:8:8, endln:8:8 |vpiInstance: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/AssignSubs/dut.sv, line:7:1, endln:19:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/AssignSubs/dut.sv, line:7:1, endln:19:10 |vpiGenScopeArray: \_gen_scope_array: (work@dut.genblk1[0]), line:14:33, endln:18:5 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/AssignSubs/dut.sv, line:7:1, endln:19:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/AssignSubs/dut.sv, line:7:1, endln:19:10 |vpiName:genblk1[0] |vpiFullName:work@dut.genblk1[0] |vpiGenScope: diff --git a/tests/Assignments/Assignments.log b/tests/Assignments/Assignments.log index ed15302b77..0d7929ba49 100644 --- a/tests/Assignments/Assignments.log +++ b/tests/Assignments/Assignments.log @@ -623,7 +623,7 @@ logic_net 13 logic_typespec 6 logic_var 1 method_func_call 3 -module 2 +module_inst 2 operation 4 package 2 part_select 3 @@ -667,7 +667,7 @@ logic_net 13 logic_typespec 6 logic_var 1 method_func_call 6 -module 2 +module_inst 2 operation 8 package 2 part_select 6 @@ -1164,7 +1164,7 @@ design: (work@dut) \_int_typespec: |vpiSigned:1 |uhdmallModules: -\_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/Assignments/dut.sv, line:1:1, endln:22:10 +\_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/Assignments/dut.sv, line:1:1, endln:22:10 |vpiParent: \_design: (work@dut) |vpiFullName:work@dut @@ -1172,12 +1172,12 @@ design: (work@dut) |vpiTaskFunc: \_function: (work@dut.uvm_packer::get_packed_bits), line:5:3, endln:12:14 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/Assignments/dut.sv, line:1:1, endln:22:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/Assignments/dut.sv, line:1:1, endln:22:10 |vpiName:uvm_packer::get_packed_bits |vpiFullName:work@dut.uvm_packer::get_packed_bits |vpiVisibility:1 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/Assignments/dut.sv, line:1:1, endln:22:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/Assignments/dut.sv, line:1:1, endln:22:10 |vpiIODecl: \_io_decl: (stream), line:5:62, endln:5:68 |vpiDirection:6 @@ -1464,23 +1464,23 @@ design: (work@dut) |vpiActual: \_int_var: (work@dut.uvm_packer::get_packed_bits.i), line:10:14, endln:10:15 |vpiInstance: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/Assignments/dut.sv, line:1:1, endln:22:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/Assignments/dut.sv, line:1:1, endln:22:10 |vpiNet: \_logic_net: (work@dut.clk), line:1:12, endln:1:15 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/Assignments/dut.sv, line:1:1, endln:22:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/Assignments/dut.sv, line:1:1, endln:22:10 |vpiName:clk |vpiFullName:work@dut.clk |vpiNet: \_logic_net: (work@dut.o), line:1:17, endln:1:18 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/Assignments/dut.sv, line:1:1, endln:22:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/Assignments/dut.sv, line:1:1, endln:22:10 |vpiName:o |vpiFullName:work@dut.o |vpiPort: \_port: (clk), line:1:12, endln:1:15 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/Assignments/dut.sv, line:1:1, endln:22:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/Assignments/dut.sv, line:1:1, endln:22:10 |vpiName:clk |vpiDirection:1 |vpiLowConn: @@ -1492,7 +1492,7 @@ design: (work@dut) |vpiPort: \_port: (o), line:1:17, endln:1:18 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/Assignments/dut.sv, line:1:1, endln:22:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/Assignments/dut.sv, line:1:1, endln:22:10 |vpiName:o |vpiDirection:2 |vpiLowConn: @@ -1504,7 +1504,7 @@ design: (work@dut) |vpiProcess: \_always: , line:14:3, endln:20:6 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/Assignments/dut.sv, line:1:1, endln:22:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/Assignments/dut.sv, line:1:1, endln:22:10 |vpiStmt: \_event_control: , line:14:10, endln:14:24 |vpiParent: @@ -1661,19 +1661,19 @@ design: (work@dut) |#1 |vpiAlwaysType:1 |uhdmtopModules: -\_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/Assignments/dut.sv, line:1:1, endln:22:10 +\_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/Assignments/dut.sv, line:1:1, endln:22:10 |vpiName:work@dut |vpiDefName:work@dut |vpiTop:1 |vpiTaskFunc: \_function: (work@dut.uvm_packer::get_packed_bits), line:5:3, endln:12:14 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/Assignments/dut.sv, line:1:1, endln:22:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/Assignments/dut.sv, line:1:1, endln:22:10 |vpiName:uvm_packer::get_packed_bits |vpiFullName:work@dut.uvm_packer::get_packed_bits |vpiVisibility:1 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/Assignments/dut.sv, line:1:1, endln:22:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/Assignments/dut.sv, line:1:1, endln:22:10 |vpiIODecl: \_io_decl: (stream), line:5:62, endln:5:68 |vpiParent: @@ -1930,11 +1930,11 @@ design: (work@dut) |vpiActual: \_io_decl: (stream), line:5:62, endln:5:68 |vpiInstance: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/Assignments/dut.sv, line:1:1, endln:22:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/Assignments/dut.sv, line:1:1, endln:22:10 |vpiNet: \_logic_net: (work@dut.clk), line:1:12, endln:1:15 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/Assignments/dut.sv, line:1:1, endln:22:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/Assignments/dut.sv, line:1:1, endln:22:10 |vpiTypespec: \_logic_typespec: , line:2:9, endln:2:9 |vpiName:clk @@ -1942,7 +1942,7 @@ design: (work@dut) |vpiNet: \_logic_net: (work@dut.o), line:1:17, endln:1:18 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/Assignments/dut.sv, line:1:1, endln:22:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/Assignments/dut.sv, line:1:1, endln:22:10 |vpiTypespec: \_logic_typespec: , line:3:10, endln:3:10 |vpiName:o @@ -1987,7 +1987,7 @@ design: (work@dut) |vpiPort: \_port: (clk), line:1:12, endln:1:15 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/Assignments/dut.sv, line:1:1, endln:22:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/Assignments/dut.sv, line:1:1, endln:22:10 |vpiName:clk |vpiDirection:1 |vpiLowConn: @@ -2001,11 +2001,11 @@ design: (work@dut) |vpiTypedef: \_logic_typespec: , line:2:9, endln:2:9 |vpiInstance: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/Assignments/dut.sv, line:1:1, endln:22:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/Assignments/dut.sv, line:1:1, endln:22:10 |vpiPort: \_port: (o), line:1:17, endln:1:18 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/Assignments/dut.sv, line:1:1, endln:22:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/Assignments/dut.sv, line:1:1, endln:22:10 |vpiName:o |vpiDirection:2 |vpiLowConn: @@ -2019,11 +2019,11 @@ design: (work@dut) |vpiTypedef: \_logic_typespec: , line:3:10, endln:3:10 |vpiInstance: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/Assignments/dut.sv, line:1:1, endln:22:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/Assignments/dut.sv, line:1:1, endln:22:10 |vpiProcess: \_always: , line:14:3, endln:20:6 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/Assignments/dut.sv, line:1:1, endln:22:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/Assignments/dut.sv, line:1:1, endln:22:10 |vpiStmt: \_event_control: , line:14:10, endln:14:24 |vpiParent: diff --git a/tests/AssociativeArray/AssociativeArray.log b/tests/AssociativeArray/AssociativeArray.log index a642fa0ea8..12b5bc1efb 100644 --- a/tests/AssociativeArray/AssociativeArray.log +++ b/tests/AssociativeArray/AssociativeArray.log @@ -111,7 +111,7 @@ design 1 int_typespec 3 int_var 2 logic_net 2 -module 3 +module_inst 3 range 2 ref_obj 4 string_typespec 1 @@ -128,7 +128,7 @@ design 1 int_typespec 3 int_var 2 logic_net 2 -module 3 +module_inst 3 range 2 ref_obj 6 string_typespec 1 @@ -146,7 +146,7 @@ design: (work@top) |vpiElaborated:1 |vpiName:work@top |uhdmallModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/AssociativeArray/dut.sv, line:1:1, endln:7:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/AssociativeArray/dut.sv, line:1:1, endln:7:10 |vpiParent: \_design: (work@top) |vpiFullName:work@top @@ -154,19 +154,19 @@ design: (work@top) |vpiNet: \_logic_net: (work@top.a), line:2:8, endln:2:9 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/AssociativeArray/dut.sv, line:1:1, endln:7:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/AssociativeArray/dut.sv, line:1:1, endln:7:10 |vpiName:a |vpiFullName:work@top.a |vpiNet: \_logic_net: (work@top.b), line:5:8, endln:5:9 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/AssociativeArray/dut.sv, line:1:1, endln:7:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/AssociativeArray/dut.sv, line:1:1, endln:7:10 |vpiName:b |vpiFullName:work@top.b |vpiContAssign: \_cont_assign: , line:3:11, endln:3:19 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/AssociativeArray/dut.sv, line:1:1, endln:7:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/AssociativeArray/dut.sv, line:1:1, endln:7:10 |vpiRhs: \_constant: , line:3:18, endln:3:19 |vpiParent: @@ -196,7 +196,7 @@ design: (work@top) |vpiContAssign: \_cont_assign: , line:6:11, endln:6:24 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/AssociativeArray/dut.sv, line:1:1, endln:7:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/AssociativeArray/dut.sv, line:1:1, endln:7:10 |vpiRhs: \_constant: , line:6:23, endln:6:24 |vpiParent: @@ -224,12 +224,12 @@ design: (work@top) |STRING:HERE |vpiConstType:6 |uhdmtopModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/AssociativeArray/dut.sv, line:1:1, endln:7:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/AssociativeArray/dut.sv, line:1:1, endln:7:10 |vpiName:work@top |vpiVariables: \_array_var: (work@top.a), line:2:8, endln:2:15 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/AssociativeArray/dut.sv, line:1:1, endln:7:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/AssociativeArray/dut.sv, line:1:1, endln:7:10 |vpiSize:1 |vpiTypespec: \_array_typespec: @@ -252,7 +252,7 @@ design: (work@top) |vpiVariables: \_array_var: (work@top.b), line:5:8, endln:5:18 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/AssociativeArray/dut.sv, line:1:1, endln:7:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/AssociativeArray/dut.sv, line:1:1, endln:7:10 |vpiSize:1 |vpiTypespec: \_array_typespec: @@ -277,7 +277,7 @@ design: (work@top) |vpiContAssign: \_cont_assign: , line:3:11, endln:3:19 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/AssociativeArray/dut.sv, line:1:1, endln:7:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/AssociativeArray/dut.sv, line:1:1, endln:7:10 |vpiRhs: \_constant: , line:3:18, endln:3:19 |vpiLhs: @@ -305,7 +305,7 @@ design: (work@top) |vpiContAssign: \_cont_assign: , line:6:11, endln:6:24 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/AssociativeArray/dut.sv, line:1:1, endln:7:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/AssociativeArray/dut.sv, line:1:1, endln:7:10 |vpiRhs: \_constant: , line:6:23, endln:6:24 |vpiLhs: diff --git a/tests/AssumeProp/AssumeProp.log b/tests/AssumeProp/AssumeProp.log index 2124faa499..98cca754d3 100644 --- a/tests/AssumeProp/AssumeProp.log +++ b/tests/AssumeProp/AssumeProp.log @@ -112,7 +112,7 @@ constant 2 design 1 hier_path 1 logic_net 3 -module 2 +module_inst 2 operation 3 property_spec 1 ref_obj 7 @@ -126,7 +126,7 @@ constant 2 design 1 hier_path 2 logic_net 3 -module 2 +module_inst 2 operation 6 property_spec 2 ref_obj 14 @@ -147,7 +147,7 @@ design: (work@dut) |vpiElaborated:1 |vpiName:work@dut |uhdmallModules: -\_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/AssumeProp/dut.sv, line:1:1, endln:10:10 +\_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/AssumeProp/dut.sv, line:1:1, endln:10:10 |vpiParent: \_design: (work@dut) |vpiFullName:work@dut @@ -155,7 +155,7 @@ design: (work@dut) |vpiAssertion: \_assume: (work@dut.aw_select), line:4:5, endln:7:64 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/AssumeProp/dut.sv, line:1:1, endln:10:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/AssumeProp/dut.sv, line:1:1, endln:10:10 |vpiName:aw_select |vpiFullName:work@dut.aw_select |vpiStmt: @@ -237,7 +237,7 @@ design: (work@dut) |vpiActual: \_logic_net: (NoMstPorts) |uhdmtopModules: -\_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/AssumeProp/dut.sv, line:1:1, endln:10:10 +\_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/AssumeProp/dut.sv, line:1:1, endln:10:10 |vpiName:work@dut |vpiDefName:work@dut |vpiTop:1 @@ -256,7 +256,7 @@ design: (work@dut) |vpiAssertion: \_assume: (work@dut.aw_select), line:4:5, endln:7:64 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/AssumeProp/dut.sv, line:1:1, endln:10:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/AssumeProp/dut.sv, line:1:1, endln:10:10 |vpiName:aw_select |vpiFullName:work@dut.aw_select |vpiStmt: diff --git a/tests/Attributes/Attributes.log b/tests/Attributes/Attributes.log index 760770e8ca..24a30649e2 100644 --- a/tests/Attributes/Attributes.log +++ b/tests/Attributes/Attributes.log @@ -935,12 +935,12 @@ if_else 1 initial 1 int_typespec 9 int_var 4 -interface 2 +interface_inst 2 io_decl 15 logic_net 26 logic_typespec 24 logic_var 1 -module 9 +module_inst 9 operation 4 package 5 port 16 @@ -979,12 +979,12 @@ if_else 2 initial 2 int_typespec 9 int_var 4 -interface 2 +interface_inst 2 io_decl 26 logic_net 26 logic_typespec 24 logic_var 1 -module 9 +module_inst 9 operation 8 package 5 port 24 @@ -1522,7 +1522,7 @@ design: (work@foo) \_class_defn: (work@toto), file:${SURELOG_DIR}/tests/Attributes/test_attributes.sv, line:42:23, endln:49:9 |vpiName:class_attribute |uhdmallInterfaces: -\_interface: work@itf (work@itf), file:${SURELOG_DIR}/tests/Attributes/test_attributes.sv, line:52:22, endln:57:13 +\_interface_inst: work@itf (work@itf), file:${SURELOG_DIR}/tests/Attributes/test_attributes.sv, line:52:22, endln:57:13 |vpiParent: \_design: (work@foo) |vpiFullName:work@itf @@ -1531,7 +1531,7 @@ design: (work@foo) |vpiName:test_interface |vpiDefName:work@itf |uhdmallInterfaces: -\_interface: work@itf2 (work@itf2), file:${SURELOG_DIR}/tests/Attributes/test_attributes.sv, line:54:25, endln:55:15 +\_interface_inst: work@itf2 (work@itf2), file:${SURELOG_DIR}/tests/Attributes/test_attributes.sv, line:54:25, endln:55:15 |vpiParent: \_design: (work@foo) |vpiFullName:work@itf2 @@ -1680,7 +1680,7 @@ design: (work@foo) |vpiSize:3 |STRING:x 1 1 : 1 |uhdmallModules: -\_module: work@bar (work@bar), file:${SURELOG_DIR}/tests/Attributes/dut.sv, line:1:1, endln:11:10 +\_module_inst: work@bar (work@bar), file:${SURELOG_DIR}/tests/Attributes/dut.sv, line:1:1, endln:11:10 |vpiParent: \_design: (work@foo) |vpiFullName:work@bar @@ -1688,35 +1688,35 @@ design: (work@foo) |vpiNet: \_logic_net: (work@bar.clk), line:1:12, endln:1:15 |vpiParent: - \_module: work@bar (work@bar), file:${SURELOG_DIR}/tests/Attributes/dut.sv, line:1:1, endln:11:10 + \_module_inst: work@bar (work@bar), file:${SURELOG_DIR}/tests/Attributes/dut.sv, line:1:1, endln:11:10 |vpiName:clk |vpiFullName:work@bar.clk |vpiNetType:1 |vpiNet: \_logic_net: (work@bar.rst), line:1:17, endln:1:20 |vpiParent: - \_module: work@bar (work@bar), file:${SURELOG_DIR}/tests/Attributes/dut.sv, line:1:1, endln:11:10 + \_module_inst: work@bar (work@bar), file:${SURELOG_DIR}/tests/Attributes/dut.sv, line:1:1, endln:11:10 |vpiName:rst |vpiFullName:work@bar.rst |vpiNetType:1 |vpiNet: \_logic_net: (work@bar.inp), line:1:22, endln:1:25 |vpiParent: - \_module: work@bar (work@bar), file:${SURELOG_DIR}/tests/Attributes/dut.sv, line:1:1, endln:11:10 + \_module_inst: work@bar (work@bar), file:${SURELOG_DIR}/tests/Attributes/dut.sv, line:1:1, endln:11:10 |vpiName:inp |vpiFullName:work@bar.inp |vpiNetType:1 |vpiNet: \_logic_net: (work@bar.out), line:1:27, endln:1:30 |vpiParent: - \_module: work@bar (work@bar), file:${SURELOG_DIR}/tests/Attributes/dut.sv, line:1:1, endln:11:10 + \_module_inst: work@bar (work@bar), file:${SURELOG_DIR}/tests/Attributes/dut.sv, line:1:1, endln:11:10 |vpiName:out |vpiFullName:work@bar.out |vpiNetType:48 |vpiPort: \_port: (clk), line:1:12, endln:1:15 |vpiParent: - \_module: work@bar (work@bar), file:${SURELOG_DIR}/tests/Attributes/dut.sv, line:1:1, endln:11:10 + \_module_inst: work@bar (work@bar), file:${SURELOG_DIR}/tests/Attributes/dut.sv, line:1:1, endln:11:10 |vpiName:clk |vpiDirection:1 |vpiLowConn: @@ -1728,7 +1728,7 @@ design: (work@foo) |vpiPort: \_port: (rst), line:1:17, endln:1:20 |vpiParent: - \_module: work@bar (work@bar), file:${SURELOG_DIR}/tests/Attributes/dut.sv, line:1:1, endln:11:10 + \_module_inst: work@bar (work@bar), file:${SURELOG_DIR}/tests/Attributes/dut.sv, line:1:1, endln:11:10 |vpiName:rst |vpiDirection:1 |vpiLowConn: @@ -1740,7 +1740,7 @@ design: (work@foo) |vpiPort: \_port: (inp), line:1:22, endln:1:25 |vpiParent: - \_module: work@bar (work@bar), file:${SURELOG_DIR}/tests/Attributes/dut.sv, line:1:1, endln:11:10 + \_module_inst: work@bar (work@bar), file:${SURELOG_DIR}/tests/Attributes/dut.sv, line:1:1, endln:11:10 |vpiName:inp |vpiDirection:1 |vpiLowConn: @@ -1752,7 +1752,7 @@ design: (work@foo) |vpiPort: \_port: (out), line:1:27, endln:1:30 |vpiParent: - \_module: work@bar (work@bar), file:${SURELOG_DIR}/tests/Attributes/dut.sv, line:1:1, endln:11:10 + \_module_inst: work@bar (work@bar), file:${SURELOG_DIR}/tests/Attributes/dut.sv, line:1:1, endln:11:10 |vpiName:out |vpiDirection:2 |vpiLowConn: @@ -1764,7 +1764,7 @@ design: (work@foo) |vpiProcess: \_always: , line:7:3, endln:9:26 |vpiParent: - \_module: work@bar (work@bar), file:${SURELOG_DIR}/tests/Attributes/dut.sv, line:1:1, endln:11:10 + \_module_inst: work@bar (work@bar), file:${SURELOG_DIR}/tests/Attributes/dut.sv, line:1:1, endln:11:10 |vpiStmt: \_event_control: , line:7:10, endln:7:24 |vpiParent: @@ -1843,7 +1843,7 @@ design: (work@foo) \_logic_net: (work@foo.bar_instance.out), line:1:27, endln:1:30 |vpiAlwaysType:1 |uhdmallModules: -\_module: work@foo (work@foo), file:${SURELOG_DIR}/tests/Attributes/dut.sv, line:13:1, endln:41:10 +\_module_inst: work@foo (work@foo), file:${SURELOG_DIR}/tests/Attributes/dut.sv, line:13:1, endln:41:10 |vpiParent: \_design: (work@foo) |vpiFullName:work@foo @@ -1851,35 +1851,35 @@ design: (work@foo) |vpiNet: \_logic_net: (work@foo.clk), line:13:12, endln:13:15 |vpiParent: - \_module: work@foo (work@foo), file:${SURELOG_DIR}/tests/Attributes/dut.sv, line:13:1, endln:41:10 + \_module_inst: work@foo (work@foo), file:${SURELOG_DIR}/tests/Attributes/dut.sv, line:13:1, endln:41:10 |vpiName:clk |vpiFullName:work@foo.clk |vpiNetType:1 |vpiNet: \_logic_net: (work@foo.rst), line:13:17, endln:13:20 |vpiParent: - \_module: work@foo (work@foo), file:${SURELOG_DIR}/tests/Attributes/dut.sv, line:13:1, endln:41:10 + \_module_inst: work@foo (work@foo), file:${SURELOG_DIR}/tests/Attributes/dut.sv, line:13:1, endln:41:10 |vpiName:rst |vpiFullName:work@foo.rst |vpiNetType:1 |vpiNet: \_logic_net: (work@foo.inp), line:13:22, endln:13:25 |vpiParent: - \_module: work@foo (work@foo), file:${SURELOG_DIR}/tests/Attributes/dut.sv, line:13:1, endln:41:10 + \_module_inst: work@foo (work@foo), file:${SURELOG_DIR}/tests/Attributes/dut.sv, line:13:1, endln:41:10 |vpiName:inp |vpiFullName:work@foo.inp |vpiNetType:1 |vpiNet: \_logic_net: (work@foo.out), line:13:27, endln:13:30 |vpiParent: - \_module: work@foo (work@foo), file:${SURELOG_DIR}/tests/Attributes/dut.sv, line:13:1, endln:41:10 + \_module_inst: work@foo (work@foo), file:${SURELOG_DIR}/tests/Attributes/dut.sv, line:13:1, endln:41:10 |vpiName:out |vpiFullName:work@foo.out |vpiNetType:1 |vpiPort: \_port: (clk), line:13:12, endln:13:15 |vpiParent: - \_module: work@foo (work@foo), file:${SURELOG_DIR}/tests/Attributes/dut.sv, line:13:1, endln:41:10 + \_module_inst: work@foo (work@foo), file:${SURELOG_DIR}/tests/Attributes/dut.sv, line:13:1, endln:41:10 |vpiName:clk |vpiDirection:1 |vpiLowConn: @@ -1891,7 +1891,7 @@ design: (work@foo) |vpiPort: \_port: (rst), line:13:17, endln:13:20 |vpiParent: - \_module: work@foo (work@foo), file:${SURELOG_DIR}/tests/Attributes/dut.sv, line:13:1, endln:41:10 + \_module_inst: work@foo (work@foo), file:${SURELOG_DIR}/tests/Attributes/dut.sv, line:13:1, endln:41:10 |vpiName:rst |vpiDirection:1 |vpiLowConn: @@ -1903,7 +1903,7 @@ design: (work@foo) |vpiPort: \_port: (inp), line:13:22, endln:13:25 |vpiParent: - \_module: work@foo (work@foo), file:${SURELOG_DIR}/tests/Attributes/dut.sv, line:13:1, endln:41:10 + \_module_inst: work@foo (work@foo), file:${SURELOG_DIR}/tests/Attributes/dut.sv, line:13:1, endln:41:10 |vpiName:inp |vpiDirection:1 |vpiLowConn: @@ -1915,7 +1915,7 @@ design: (work@foo) |vpiPort: \_port: (out), line:13:27, endln:13:30 |vpiParent: - \_module: work@foo (work@foo), file:${SURELOG_DIR}/tests/Attributes/dut.sv, line:13:1, endln:41:10 + \_module_inst: work@foo (work@foo), file:${SURELOG_DIR}/tests/Attributes/dut.sv, line:13:1, endln:41:10 |vpiName:out |vpiDirection:2 |vpiLowConn: @@ -1927,7 +1927,7 @@ design: (work@foo) |vpiProcess: \_initial: , line:26:3, endln:37:6 |vpiParent: - \_module: work@foo (work@foo), file:${SURELOG_DIR}/tests/Attributes/dut.sv, line:13:1, endln:41:10 + \_module_inst: work@foo (work@foo), file:${SURELOG_DIR}/tests/Attributes/dut.sv, line:13:1, endln:41:10 |vpiStmt: \_begin: (work@foo), line:26:11, endln:37:6 |vpiParent: @@ -2059,7 +2059,7 @@ design: (work@foo) |vpiContAssign: \_cont_assign: , line:22:10, endln:22:62 |vpiParent: - \_module: work@foo (work@foo), file:${SURELOG_DIR}/tests/Attributes/dut.sv, line:13:1, endln:41:10 + \_module_inst: work@foo (work@foo), file:${SURELOG_DIR}/tests/Attributes/dut.sv, line:13:1, endln:41:10 |vpiRhs: \_operation: , line:22:18, endln:22:62 |vpiParent: @@ -2096,7 +2096,7 @@ design: (work@foo) |vpiContAssign: \_cont_assign: , line:24:10, endln:24:69 |vpiParent: - \_module: work@foo (work@foo), file:${SURELOG_DIR}/tests/Attributes/dut.sv, line:13:1, endln:41:10 + \_module_inst: work@foo (work@foo), file:${SURELOG_DIR}/tests/Attributes/dut.sv, line:13:1, endln:41:10 |vpiRhs: \_operation: , line:24:22, endln:24:69 |vpiParent: @@ -2131,7 +2131,7 @@ design: (work@foo) |vpiActual: \_logic_net: ($37) |uhdmallModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/Attributes/test_attributes.sv, line:32:1, endln:39:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/Attributes/test_attributes.sv, line:32:1, endln:39:10 |vpiParent: \_design: (work@foo) |vpiFullName:work@top @@ -2140,7 +2140,7 @@ design: (work@foo) |vpiName:mymoduleTop |vpiDefName:work@top |uhdmallModules: -\_module: work@top::top2 (work@top::top2), file:${SURELOG_DIR}/tests/Attributes/test_attributes.sv, line:35:3, endln:36:12 +\_module_inst: work@top::top2 (work@top::top2), file:${SURELOG_DIR}/tests/Attributes/test_attributes.sv, line:35:3, endln:36:12 |vpiParent: \_design: (work@foo) |vpiFullName:work@top::top2 @@ -2149,14 +2149,14 @@ design: (work@foo) |vpiName:mymoduleTop2 |vpiDefName:work@top::top2 |uhdmtopModules: -\_module: work@foo (work@foo), file:${SURELOG_DIR}/tests/Attributes/dut.sv, line:13:1, endln:41:10 +\_module_inst: work@foo (work@foo), file:${SURELOG_DIR}/tests/Attributes/dut.sv, line:13:1, endln:41:10 |vpiName:work@foo |vpiDefName:work@foo |vpiTop:1 |vpiNet: \_logic_net: (work@foo.clk), line:13:12, endln:13:15 |vpiParent: - \_module: work@foo (work@foo), file:${SURELOG_DIR}/tests/Attributes/dut.sv, line:13:1, endln:41:10 + \_module_inst: work@foo (work@foo), file:${SURELOG_DIR}/tests/Attributes/dut.sv, line:13:1, endln:41:10 |vpiTypespec: \_logic_typespec: , line:14:10, endln:14:14 |vpiName:clk @@ -2165,7 +2165,7 @@ design: (work@foo) |vpiNet: \_logic_net: (work@foo.rst), line:13:17, endln:13:20 |vpiParent: - \_module: work@foo (work@foo), file:${SURELOG_DIR}/tests/Attributes/dut.sv, line:13:1, endln:41:10 + \_module_inst: work@foo (work@foo), file:${SURELOG_DIR}/tests/Attributes/dut.sv, line:13:1, endln:41:10 |vpiTypespec: \_logic_typespec: , line:15:10, endln:15:14 |vpiName:rst @@ -2174,7 +2174,7 @@ design: (work@foo) |vpiNet: \_logic_net: (work@foo.inp), line:13:22, endln:13:25 |vpiParent: - \_module: work@foo (work@foo), file:${SURELOG_DIR}/tests/Attributes/dut.sv, line:13:1, endln:41:10 + \_module_inst: work@foo (work@foo), file:${SURELOG_DIR}/tests/Attributes/dut.sv, line:13:1, endln:41:10 |vpiTypespec: \_logic_typespec: , line:16:10, endln:16:14 |vpiName:inp @@ -2183,7 +2183,7 @@ design: (work@foo) |vpiNet: \_logic_net: (work@foo.out), line:13:27, endln:13:30 |vpiParent: - \_module: work@foo (work@foo), file:${SURELOG_DIR}/tests/Attributes/dut.sv, line:13:1, endln:41:10 + \_module_inst: work@foo (work@foo), file:${SURELOG_DIR}/tests/Attributes/dut.sv, line:13:1, endln:41:10 |vpiTypespec: \_logic_typespec: , line:17:10, endln:17:14 |vpiName:out @@ -2217,7 +2217,7 @@ design: (work@foo) |vpiPort: \_port: (clk), line:13:12, endln:13:15 |vpiParent: - \_module: work@foo (work@foo), file:${SURELOG_DIR}/tests/Attributes/dut.sv, line:13:1, endln:41:10 + \_module_inst: work@foo (work@foo), file:${SURELOG_DIR}/tests/Attributes/dut.sv, line:13:1, endln:41:10 |vpiName:clk |vpiDirection:1 |vpiLowConn: @@ -2231,11 +2231,11 @@ design: (work@foo) |vpiTypedef: \_logic_typespec: , line:14:10, endln:14:14 |vpiInstance: - \_module: work@foo (work@foo), file:${SURELOG_DIR}/tests/Attributes/dut.sv, line:13:1, endln:41:10 + \_module_inst: work@foo (work@foo), file:${SURELOG_DIR}/tests/Attributes/dut.sv, line:13:1, endln:41:10 |vpiPort: \_port: (rst), line:13:17, endln:13:20 |vpiParent: - \_module: work@foo (work@foo), file:${SURELOG_DIR}/tests/Attributes/dut.sv, line:13:1, endln:41:10 + \_module_inst: work@foo (work@foo), file:${SURELOG_DIR}/tests/Attributes/dut.sv, line:13:1, endln:41:10 |vpiName:rst |vpiDirection:1 |vpiLowConn: @@ -2249,11 +2249,11 @@ design: (work@foo) |vpiTypedef: \_logic_typespec: , line:15:10, endln:15:14 |vpiInstance: - \_module: work@foo (work@foo), file:${SURELOG_DIR}/tests/Attributes/dut.sv, line:13:1, endln:41:10 + \_module_inst: work@foo (work@foo), file:${SURELOG_DIR}/tests/Attributes/dut.sv, line:13:1, endln:41:10 |vpiPort: \_port: (inp), line:13:22, endln:13:25 |vpiParent: - \_module: work@foo (work@foo), file:${SURELOG_DIR}/tests/Attributes/dut.sv, line:13:1, endln:41:10 + \_module_inst: work@foo (work@foo), file:${SURELOG_DIR}/tests/Attributes/dut.sv, line:13:1, endln:41:10 |vpiName:inp |vpiDirection:1 |vpiLowConn: @@ -2267,11 +2267,11 @@ design: (work@foo) |vpiTypedef: \_logic_typespec: , line:16:10, endln:16:14 |vpiInstance: - \_module: work@foo (work@foo), file:${SURELOG_DIR}/tests/Attributes/dut.sv, line:13:1, endln:41:10 + \_module_inst: work@foo (work@foo), file:${SURELOG_DIR}/tests/Attributes/dut.sv, line:13:1, endln:41:10 |vpiPort: \_port: (out), line:13:27, endln:13:30 |vpiParent: - \_module: work@foo (work@foo), file:${SURELOG_DIR}/tests/Attributes/dut.sv, line:13:1, endln:41:10 + \_module_inst: work@foo (work@foo), file:${SURELOG_DIR}/tests/Attributes/dut.sv, line:13:1, endln:41:10 |vpiName:out |vpiDirection:2 |vpiLowConn: @@ -2285,11 +2285,11 @@ design: (work@foo) |vpiTypedef: \_logic_typespec: , line:17:10, endln:17:14 |vpiInstance: - \_module: work@foo (work@foo), file:${SURELOG_DIR}/tests/Attributes/dut.sv, line:13:1, endln:41:10 + \_module_inst: work@foo (work@foo), file:${SURELOG_DIR}/tests/Attributes/dut.sv, line:13:1, endln:41:10 |vpiProcess: \_initial: , line:26:3, endln:37:6 |vpiParent: - \_module: work@foo (work@foo), file:${SURELOG_DIR}/tests/Attributes/dut.sv, line:13:1, endln:41:10 + \_module_inst: work@foo (work@foo), file:${SURELOG_DIR}/tests/Attributes/dut.sv, line:13:1, endln:41:10 |vpiStmt: \_begin: (work@foo), line:26:11, endln:37:6 |vpiParent: @@ -2386,10 +2386,10 @@ design: (work@foo) |vpiFullName:work@foo.b |vpiActual: \_logic_net: (b) - |vpiModule: - \_module: work@bar (work@foo.bar_instance), file:${SURELOG_DIR}/tests/Attributes/dut.sv, line:19:3, endln:19:105 + |vpiModuleInst: + \_module_inst: work@bar (work@foo.bar_instance), file:${SURELOG_DIR}/tests/Attributes/dut.sv, line:19:3, endln:19:105 |vpiParent: - \_module: work@foo (work@foo), file:${SURELOG_DIR}/tests/Attributes/dut.sv, line:13:1, endln:41:10 + \_module_inst: work@foo (work@foo), file:${SURELOG_DIR}/tests/Attributes/dut.sv, line:13:1, endln:41:10 |vpiName:bar_instance |vpiFullName:work@foo.bar_instance |vpiDefName:work@bar @@ -2398,7 +2398,7 @@ design: (work@foo) |vpiNet: \_logic_net: (work@foo.bar_instance.clk), line:1:12, endln:1:15 |vpiParent: - \_module: work@bar (work@foo.bar_instance), file:${SURELOG_DIR}/tests/Attributes/dut.sv, line:19:3, endln:19:105 + \_module_inst: work@bar (work@foo.bar_instance), file:${SURELOG_DIR}/tests/Attributes/dut.sv, line:19:3, endln:19:105 |vpiTypespec: \_logic_typespec: , line:2:10, endln:2:14 |vpiName:clk @@ -2407,7 +2407,7 @@ design: (work@foo) |vpiNet: \_logic_net: (work@foo.bar_instance.rst), line:1:17, endln:1:20 |vpiParent: - \_module: work@bar (work@foo.bar_instance), file:${SURELOG_DIR}/tests/Attributes/dut.sv, line:19:3, endln:19:105 + \_module_inst: work@bar (work@foo.bar_instance), file:${SURELOG_DIR}/tests/Attributes/dut.sv, line:19:3, endln:19:105 |vpiTypespec: \_logic_typespec: , line:3:10, endln:3:14 |vpiName:rst @@ -2416,7 +2416,7 @@ design: (work@foo) |vpiNet: \_logic_net: (work@foo.bar_instance.inp), line:1:22, endln:1:25 |vpiParent: - \_module: work@bar (work@foo.bar_instance), file:${SURELOG_DIR}/tests/Attributes/dut.sv, line:19:3, endln:19:105 + \_module_inst: work@bar (work@foo.bar_instance), file:${SURELOG_DIR}/tests/Attributes/dut.sv, line:19:3, endln:19:105 |vpiTypespec: \_logic_typespec: , line:4:10, endln:4:14 |vpiName:inp @@ -2425,18 +2425,18 @@ design: (work@foo) |vpiNet: \_logic_net: (work@foo.bar_instance.out), line:1:27, endln:1:30 |vpiParent: - \_module: work@bar (work@foo.bar_instance), file:${SURELOG_DIR}/tests/Attributes/dut.sv, line:19:3, endln:19:105 + \_module_inst: work@bar (work@foo.bar_instance), file:${SURELOG_DIR}/tests/Attributes/dut.sv, line:19:3, endln:19:105 |vpiTypespec: \_logic_typespec: , line:5:10, endln:5:13 |vpiName:out |vpiFullName:work@foo.bar_instance.out |vpiNetType:48 |vpiInstance: - \_module: work@foo (work@foo), file:${SURELOG_DIR}/tests/Attributes/dut.sv, line:13:1, endln:41:10 + \_module_inst: work@foo (work@foo), file:${SURELOG_DIR}/tests/Attributes/dut.sv, line:13:1, endln:41:10 |vpiPort: \_port: (clk), line:1:12, endln:1:15 |vpiParent: - \_module: work@bar (work@foo.bar_instance), file:${SURELOG_DIR}/tests/Attributes/dut.sv, line:19:3, endln:19:105 + \_module_inst: work@bar (work@foo.bar_instance), file:${SURELOG_DIR}/tests/Attributes/dut.sv, line:19:3, endln:19:105 |vpiName:clk |vpiDirection:1 |vpiHighConn: @@ -2458,7 +2458,7 @@ design: (work@foo) |vpiTypedef: \_logic_typespec: , line:2:10, endln:2:14 |vpiInstance: - \_module: work@bar (work@foo.bar_instance), file:${SURELOG_DIR}/tests/Attributes/dut.sv, line:19:3, endln:19:105 + \_module_inst: work@bar (work@foo.bar_instance), file:${SURELOG_DIR}/tests/Attributes/dut.sv, line:19:3, endln:19:105 |vpiAttribute: \_attribute: (clock_connected), line:19:25, endln:19:48 |vpiParent: @@ -2468,7 +2468,7 @@ design: (work@foo) |vpiPort: \_port: (rst), line:1:17, endln:1:20 |vpiParent: - \_module: work@bar (work@foo.bar_instance), file:${SURELOG_DIR}/tests/Attributes/dut.sv, line:19:3, endln:19:105 + \_module_inst: work@bar (work@foo.bar_instance), file:${SURELOG_DIR}/tests/Attributes/dut.sv, line:19:3, endln:19:105 |vpiName:rst |vpiDirection:1 |vpiHighConn: @@ -2490,11 +2490,11 @@ design: (work@foo) |vpiTypedef: \_logic_typespec: , line:3:10, endln:3:14 |vpiInstance: - \_module: work@bar (work@foo.bar_instance), file:${SURELOG_DIR}/tests/Attributes/dut.sv, line:19:3, endln:19:105 + \_module_inst: work@bar (work@foo.bar_instance), file:${SURELOG_DIR}/tests/Attributes/dut.sv, line:19:3, endln:19:105 |vpiPort: \_port: (inp), line:1:22, endln:1:25 |vpiParent: - \_module: work@bar (work@foo.bar_instance), file:${SURELOG_DIR}/tests/Attributes/dut.sv, line:19:3, endln:19:105 + \_module_inst: work@bar (work@foo.bar_instance), file:${SURELOG_DIR}/tests/Attributes/dut.sv, line:19:3, endln:19:105 |vpiName:inp |vpiDirection:1 |vpiHighConn: @@ -2516,7 +2516,7 @@ design: (work@foo) |vpiTypedef: \_logic_typespec: , line:4:10, endln:4:14 |vpiInstance: - \_module: work@bar (work@foo.bar_instance), file:${SURELOG_DIR}/tests/Attributes/dut.sv, line:19:3, endln:19:105 + \_module_inst: work@bar (work@foo.bar_instance), file:${SURELOG_DIR}/tests/Attributes/dut.sv, line:19:3, endln:19:105 |vpiAttribute: \_attribute: (this_is_the_input), line:19:65, endln:19:91 |vpiParent: @@ -2526,7 +2526,7 @@ design: (work@foo) |vpiPort: \_port: (out), line:1:27, endln:1:30 |vpiParent: - \_module: work@bar (work@foo.bar_instance), file:${SURELOG_DIR}/tests/Attributes/dut.sv, line:19:3, endln:19:105 + \_module_inst: work@bar (work@foo.bar_instance), file:${SURELOG_DIR}/tests/Attributes/dut.sv, line:19:3, endln:19:105 |vpiName:out |vpiDirection:2 |vpiHighConn: @@ -2548,11 +2548,11 @@ design: (work@foo) |vpiTypedef: \_logic_typespec: , line:5:10, endln:5:13 |vpiInstance: - \_module: work@bar (work@foo.bar_instance), file:${SURELOG_DIR}/tests/Attributes/dut.sv, line:19:3, endln:19:105 + \_module_inst: work@bar (work@foo.bar_instance), file:${SURELOG_DIR}/tests/Attributes/dut.sv, line:19:3, endln:19:105 |vpiProcess: \_always: , line:7:3, endln:9:26 |vpiParent: - \_module: work@bar (work@foo.bar_instance), file:${SURELOG_DIR}/tests/Attributes/dut.sv, line:19:3, endln:19:105 + \_module_inst: work@bar (work@foo.bar_instance), file:${SURELOG_DIR}/tests/Attributes/dut.sv, line:19:3, endln:19:105 |vpiStmt: \_event_control: , line:7:10, endln:7:24 |vpiParent: @@ -2627,7 +2627,7 @@ design: (work@foo) |vpiContAssign: \_cont_assign: , line:22:10, endln:22:62 |vpiParent: - \_module: work@foo (work@foo), file:${SURELOG_DIR}/tests/Attributes/dut.sv, line:13:1, endln:41:10 + \_module_inst: work@foo (work@foo), file:${SURELOG_DIR}/tests/Attributes/dut.sv, line:13:1, endln:41:10 |vpiRhs: \_operation: , line:22:18, endln:22:62 |vpiParent: @@ -2666,7 +2666,7 @@ design: (work@foo) |vpiContAssign: \_cont_assign: , line:24:10, endln:24:69 |vpiParent: - \_module: work@foo (work@foo), file:${SURELOG_DIR}/tests/Attributes/dut.sv, line:13:1, endln:41:10 + \_module_inst: work@foo (work@foo), file:${SURELOG_DIR}/tests/Attributes/dut.sv, line:13:1, endln:41:10 |vpiRhs: \_operation: , line:24:22, endln:24:69 |vpiParent: @@ -2697,12 +2697,12 @@ design: (work@foo) |vpiActual: \_logic_net: ($37) |uhdmtopModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/Attributes/test_attributes.sv, line:32:1, endln:39:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/Attributes/test_attributes.sv, line:32:1, endln:39:10 |vpiName:work@top |vpiAttribute: \_attribute: (mymoduleTop), line:31:4, endln:31:15 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/Attributes/test_attributes.sv, line:32:1, endln:39:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/Attributes/test_attributes.sv, line:32:1, endln:39:10 |vpiName:mymoduleTop |vpiDefName:work@top |vpiTop:1 diff --git a/tests/Attributes2/Attributes2.log b/tests/Attributes2/Attributes2.log index 9d4c881bef..91c02879c4 100644 --- a/tests/Attributes2/Attributes2.log +++ b/tests/Attributes2/Attributes2.log @@ -370,7 +370,7 @@ io_decl 11 logic_net 4 logic_typespec 6 logic_var 1 -module 5 +module_inst 5 package 2 port 4 ref_obj 5 @@ -395,7 +395,7 @@ io_decl 22 logic_net 4 logic_typespec 6 logic_var 1 -module 5 +module_inst 5 package 2 port 6 ref_obj 8 @@ -889,7 +889,7 @@ design: (work@foo) \_int_typespec: |vpiSigned:1 |uhdmallModules: -\_module: work@bar (work@bar), file:${SURELOG_DIR}/tests/Attributes2/dut.sv, line:2:1, endln:5:10 +\_module_inst: work@bar (work@bar), file:${SURELOG_DIR}/tests/Attributes2/dut.sv, line:2:1, endln:5:10 |vpiParent: \_design: (work@foo) |vpiFullName:work@bar @@ -897,14 +897,14 @@ design: (work@foo) |vpiNet: \_logic_net: (work@bar.clk), line:2:12, endln:2:15 |vpiParent: - \_module: work@bar (work@bar), file:${SURELOG_DIR}/tests/Attributes2/dut.sv, line:2:1, endln:5:10 + \_module_inst: work@bar (work@bar), file:${SURELOG_DIR}/tests/Attributes2/dut.sv, line:2:1, endln:5:10 |vpiName:clk |vpiFullName:work@bar.clk |vpiNetType:1 |vpiPort: \_port: (clk), line:2:12, endln:2:15 |vpiParent: - \_module: work@bar (work@bar), file:${SURELOG_DIR}/tests/Attributes2/dut.sv, line:2:1, endln:5:10 + \_module_inst: work@bar (work@bar), file:${SURELOG_DIR}/tests/Attributes2/dut.sv, line:2:1, endln:5:10 |vpiName:clk |vpiDirection:1 |vpiLowConn: @@ -914,7 +914,7 @@ design: (work@foo) |vpiTypedef: \_logic_typespec: , line:3:10, endln:3:14 |uhdmallModules: -\_module: work@foo (work@foo), file:${SURELOG_DIR}/tests/Attributes2/dut.sv, line:8:1, endln:12:10 +\_module_inst: work@foo (work@foo), file:${SURELOG_DIR}/tests/Attributes2/dut.sv, line:8:1, endln:12:10 |vpiParent: \_design: (work@foo) |vpiFullName:work@foo @@ -922,14 +922,14 @@ design: (work@foo) |vpiNet: \_logic_net: (work@foo.clk), line:8:12, endln:8:15 |vpiParent: - \_module: work@foo (work@foo), file:${SURELOG_DIR}/tests/Attributes2/dut.sv, line:8:1, endln:12:10 + \_module_inst: work@foo (work@foo), file:${SURELOG_DIR}/tests/Attributes2/dut.sv, line:8:1, endln:12:10 |vpiName:clk |vpiFullName:work@foo.clk |vpiNetType:1 |vpiPort: \_port: (clk), line:8:12, endln:8:15 |vpiParent: - \_module: work@foo (work@foo), file:${SURELOG_DIR}/tests/Attributes2/dut.sv, line:8:1, endln:12:10 + \_module_inst: work@foo (work@foo), file:${SURELOG_DIR}/tests/Attributes2/dut.sv, line:8:1, endln:12:10 |vpiName:clk |vpiDirection:1 |vpiLowConn: @@ -939,14 +939,14 @@ design: (work@foo) |vpiTypedef: \_logic_typespec: , line:9:28, endln:9:32 |uhdmtopModules: -\_module: work@foo (work@foo), file:${SURELOG_DIR}/tests/Attributes2/dut.sv, line:8:1, endln:12:10 +\_module_inst: work@foo (work@foo), file:${SURELOG_DIR}/tests/Attributes2/dut.sv, line:8:1, endln:12:10 |vpiName:work@foo |vpiDefName:work@foo |vpiTop:1 |vpiNet: \_logic_net: (work@foo.clk), line:8:12, endln:8:15 |vpiParent: - \_module: work@foo (work@foo), file:${SURELOG_DIR}/tests/Attributes2/dut.sv, line:8:1, endln:12:10 + \_module_inst: work@foo (work@foo), file:${SURELOG_DIR}/tests/Attributes2/dut.sv, line:8:1, endln:12:10 |vpiTypespec: \_logic_typespec: , line:9:28, endln:9:32 |vpiName:clk @@ -959,7 +959,7 @@ design: (work@foo) |vpiPort: \_port: (clk), line:8:12, endln:8:15 |vpiParent: - \_module: work@foo (work@foo), file:${SURELOG_DIR}/tests/Attributes2/dut.sv, line:8:1, endln:12:10 + \_module_inst: work@foo (work@foo), file:${SURELOG_DIR}/tests/Attributes2/dut.sv, line:8:1, endln:12:10 |vpiName:clk |vpiDirection:1 |vpiLowConn: @@ -973,11 +973,11 @@ design: (work@foo) |vpiTypedef: \_logic_typespec: , line:9:28, endln:9:32 |vpiInstance: - \_module: work@foo (work@foo), file:${SURELOG_DIR}/tests/Attributes2/dut.sv, line:8:1, endln:12:10 - |vpiModule: - \_module: work@bar (work@foo.bar_instance_1), file:${SURELOG_DIR}/tests/Attributes2/dut.sv, line:11:3, endln:11:55 + \_module_inst: work@foo (work@foo), file:${SURELOG_DIR}/tests/Attributes2/dut.sv, line:8:1, endln:12:10 + |vpiModuleInst: + \_module_inst: work@bar (work@foo.bar_instance_1), file:${SURELOG_DIR}/tests/Attributes2/dut.sv, line:11:3, endln:11:55 |vpiParent: - \_module: work@foo (work@foo), file:${SURELOG_DIR}/tests/Attributes2/dut.sv, line:8:1, endln:12:10 + \_module_inst: work@foo (work@foo), file:${SURELOG_DIR}/tests/Attributes2/dut.sv, line:8:1, endln:12:10 |vpiName:bar_instance_1 |vpiFullName:work@foo.bar_instance_1 |vpiDefName:work@bar @@ -986,18 +986,18 @@ design: (work@foo) |vpiNet: \_logic_net: (work@foo.bar_instance_1.clk), line:2:12, endln:2:15 |vpiParent: - \_module: work@bar (work@foo.bar_instance_1), file:${SURELOG_DIR}/tests/Attributes2/dut.sv, line:11:3, endln:11:55 + \_module_inst: work@bar (work@foo.bar_instance_1), file:${SURELOG_DIR}/tests/Attributes2/dut.sv, line:11:3, endln:11:55 |vpiTypespec: \_logic_typespec: , line:3:10, endln:3:14 |vpiName:clk |vpiFullName:work@foo.bar_instance_1.clk |vpiNetType:1 |vpiInstance: - \_module: work@foo (work@foo), file:${SURELOG_DIR}/tests/Attributes2/dut.sv, line:8:1, endln:12:10 + \_module_inst: work@foo (work@foo), file:${SURELOG_DIR}/tests/Attributes2/dut.sv, line:8:1, endln:12:10 |vpiPort: \_port: (clk), line:2:12, endln:2:15 |vpiParent: - \_module: work@bar (work@foo.bar_instance_1), file:${SURELOG_DIR}/tests/Attributes2/dut.sv, line:11:3, endln:11:55 + \_module_inst: work@bar (work@foo.bar_instance_1), file:${SURELOG_DIR}/tests/Attributes2/dut.sv, line:11:3, endln:11:55 |vpiName:clk |vpiDirection:1 |vpiHighConn: @@ -1019,7 +1019,7 @@ design: (work@foo) |vpiTypedef: \_logic_typespec: , line:3:10, endln:3:14 |vpiInstance: - \_module: work@bar (work@foo.bar_instance_1), file:${SURELOG_DIR}/tests/Attributes2/dut.sv, line:11:3, endln:11:55 + \_module_inst: work@bar (work@foo.bar_instance_1), file:${SURELOG_DIR}/tests/Attributes2/dut.sv, line:11:3, endln:11:55 |vpiAttribute: \_attribute: (this_is_clock), line:11:27, endln:11:40 |vpiParent: diff --git a/tests/BadLabel/BadLabel.log b/tests/BadLabel/BadLabel.log index 50f4bd6fec..d027ef8bc7 100644 --- a/tests/BadLabel/BadLabel.log +++ b/tests/BadLabel/BadLabel.log @@ -367,10 +367,10 @@ fork_stmt 1 func_call 3 if_stmt 1 initial 3 -interface 4 +interface_inst 4 logic_net 4 logic_typespec 2 -module 8 +module_inst 8 named_begin 1 named_fork 3 operation 1 @@ -394,10 +394,10 @@ fork_stmt 2 func_call 6 if_stmt 2 initial 6 -interface 4 +interface_inst 4 logic_net 4 logic_typespec 2 -module 8 +module_inst 8 named_begin 2 named_fork 6 operation 2 @@ -438,13 +438,13 @@ design: (work@test) \_design: (work@test) |vpiName:work@c |uhdmallInterfaces: -\_interface: work@intf (work@intf), file:${SURELOG_DIR}/tests/BadLabel/dut.sv, line:7:1, endln:8:23 +\_interface_inst: work@intf (work@intf), file:${SURELOG_DIR}/tests/BadLabel/dut.sv, line:7:1, endln:8:23 |vpiParent: \_design: (work@test) |vpiFullName:work@intf |vpiDefName:work@intf |uhdmallInterfaces: -\_interface: work@itf (work@itf), file:${SURELOG_DIR}/tests/BadLabel/dut.sv, line:12:22, endln:20:13 +\_interface_inst: work@itf (work@itf), file:${SURELOG_DIR}/tests/BadLabel/dut.sv, line:12:22, endln:20:13 |vpiParent: \_design: (work@test) |vpiFullName:work@itf @@ -453,7 +453,7 @@ design: (work@test) |vpiName:test_interface |vpiDefName:work@itf |uhdmallInterfaces: -\_interface: work@itf2 (work@itf2), file:${SURELOG_DIR}/tests/BadLabel/dut.sv, line:14:25, endln:15:22 +\_interface_inst: work@itf2 (work@itf2), file:${SURELOG_DIR}/tests/BadLabel/dut.sv, line:14:25, endln:15:22 |vpiParent: \_design: (work@test) |vpiFullName:work@itf2 @@ -462,7 +462,7 @@ design: (work@test) |vpiName:test_interface2 |vpiDefName:work@itf2 |uhdmallInterfaces: -\_interface: work@itf3 (work@itf3), file:${SURELOG_DIR}/tests/BadLabel/dut.sv, line:17:25, endln:18:26 +\_interface_inst: work@itf3 (work@itf3), file:${SURELOG_DIR}/tests/BadLabel/dut.sv, line:17:25, endln:18:26 |vpiParent: \_design: (work@test) |vpiFullName:work@itf3 @@ -471,7 +471,7 @@ design: (work@test) |vpiName:test_interface2 |vpiDefName:work@itf3 |uhdmallModules: -\_module: work@block_tb (work@block_tb), file:${SURELOG_DIR}/tests/BadLabel/dut.sv, line:60:1, endln:66:10 +\_module_inst: work@block_tb (work@block_tb), file:${SURELOG_DIR}/tests/BadLabel/dut.sv, line:60:1, endln:66:10 |vpiParent: \_design: (work@test) |vpiFullName:work@block_tb @@ -479,14 +479,14 @@ design: (work@test) |vpiNet: \_logic_net: (work@block_tb.a), line:61:6, endln:61:7 |vpiParent: - \_module: work@block_tb (work@block_tb), file:${SURELOG_DIR}/tests/BadLabel/dut.sv, line:60:1, endln:66:10 + \_module_inst: work@block_tb (work@block_tb), file:${SURELOG_DIR}/tests/BadLabel/dut.sv, line:60:1, endln:66:10 |vpiName:a |vpiFullName:work@block_tb.a |vpiNetType:48 |vpiProcess: \_initial: , line:62:2, endln:65:14 |vpiParent: - \_module: work@block_tb (work@block_tb), file:${SURELOG_DIR}/tests/BadLabel/dut.sv, line:60:1, endln:66:10 + \_module_inst: work@block_tb (work@block_tb), file:${SURELOG_DIR}/tests/BadLabel/dut.sv, line:60:1, endln:66:10 |vpiStmt: \_named_fork: (work@block_tb.name1), line:63:17, endln:65:14 |vpiParent: @@ -516,7 +516,7 @@ design: (work@test) |vpiActual: \_logic_net: (work@block_tb.a), line:61:6, endln:61:11 |uhdmallModules: -\_module: work@test (work@test), file:${SURELOG_DIR}/tests/BadLabel/dut.sv, line:23:1, endln:57:21 +\_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/BadLabel/dut.sv, line:23:1, endln:57:21 |vpiParent: \_design: (work@test) |vpiFullName:work@test @@ -524,13 +524,13 @@ design: (work@test) |vpiNet: \_logic_net: (work@test.err), line:27:8, endln:27:11 |vpiParent: - \_module: work@test (work@test), file:${SURELOG_DIR}/tests/BadLabel/dut.sv, line:23:1, endln:57:21 + \_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/BadLabel/dut.sv, line:23:1, endln:57:21 |vpiName:err |vpiFullName:work@test.err |vpiProcess: \_initial: , line:29:4, endln:32:25 |vpiParent: - \_module: work@test (work@test), file:${SURELOG_DIR}/tests/BadLabel/dut.sv, line:23:1, endln:57:21 + \_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/BadLabel/dut.sv, line:23:1, endln:57:21 |vpiStmt: \_named_begin: (work@test.dummy_label), line:30:4, endln:32:25 |vpiParent: @@ -570,7 +570,7 @@ design: (work@test) |vpiProcess: \_initial: , line:40:1, endln:54:6 |vpiParent: - \_module: work@test (work@test), file:${SURELOG_DIR}/tests/BadLabel/dut.sv, line:23:1, endln:57:21 + \_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/BadLabel/dut.sv, line:23:1, endln:57:21 |vpiStmt: \_begin: (work@test), line:40:9, endln:54:6 |vpiParent: @@ -627,24 +627,24 @@ design: (work@test) |vpiConstType:6 |vpiName:print |uhdmallModules: -\_module: work@test::sub (work@test::sub), file:${SURELOG_DIR}/tests/BadLabel/dut.sv, line:34:4, endln:35:19 +\_module_inst: work@test::sub (work@test::sub), file:${SURELOG_DIR}/tests/BadLabel/dut.sv, line:34:4, endln:35:19 |vpiParent: \_design: (work@test) |vpiFullName:work@test::sub |vpiDefName:work@test::sub |uhdmallModules: -\_module: work@test::sub2 (work@test::sub2), file:${SURELOG_DIR}/tests/BadLabel/dut.sv, line:37:4, endln:38:24 +\_module_inst: work@test::sub2 (work@test::sub2), file:${SURELOG_DIR}/tests/BadLabel/dut.sv, line:37:4, endln:38:24 |vpiParent: \_design: (work@test) |vpiFullName:work@test::sub2 |vpiDefName:work@test::sub2 |uhdmtopModules: -\_module: work@test (work@test), file:${SURELOG_DIR}/tests/BadLabel/dut.sv, line:23:1, endln:57:21 +\_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/BadLabel/dut.sv, line:23:1, endln:57:21 |vpiName:work@test |vpiVariables: \_bit_var: (work@test.err), line:27:8, endln:27:15 |vpiParent: - \_module: work@test (work@test), file:${SURELOG_DIR}/tests/BadLabel/dut.sv, line:23:1, endln:57:21 + \_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/BadLabel/dut.sv, line:23:1, endln:57:21 |vpiTypespec: \_bit_typespec: , line:27:4, endln:27:7 |vpiSigned:1 @@ -663,7 +663,7 @@ design: (work@test) |vpiProcess: \_initial: , line:29:4, endln:32:25 |vpiParent: - \_module: work@test (work@test), file:${SURELOG_DIR}/tests/BadLabel/dut.sv, line:23:1, endln:57:21 + \_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/BadLabel/dut.sv, line:23:1, endln:57:21 |vpiStmt: \_named_begin: (work@test.dummy_label), line:30:4, endln:32:25 |vpiParent: @@ -697,7 +697,7 @@ design: (work@test) |vpiProcess: \_initial: , line:40:1, endln:54:6 |vpiParent: - \_module: work@test (work@test), file:${SURELOG_DIR}/tests/BadLabel/dut.sv, line:23:1, endln:57:21 + \_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/BadLabel/dut.sv, line:23:1, endln:57:21 |vpiStmt: \_begin: (work@test), line:40:9, endln:54:6 |vpiParent: @@ -742,14 +742,14 @@ design: (work@test) \_constant: , line:51:11, endln:51:13 |vpiName:print |uhdmtopModules: -\_module: work@block_tb (work@block_tb), file:${SURELOG_DIR}/tests/BadLabel/dut.sv, line:60:1, endln:66:10 +\_module_inst: work@block_tb (work@block_tb), file:${SURELOG_DIR}/tests/BadLabel/dut.sv, line:60:1, endln:66:10 |vpiName:work@block_tb |vpiDefName:work@block_tb |vpiTop:1 |vpiNet: \_logic_net: (work@block_tb.a), line:61:6, endln:61:11 |vpiParent: - \_module: work@block_tb (work@block_tb), file:${SURELOG_DIR}/tests/BadLabel/dut.sv, line:60:1, endln:66:10 + \_module_inst: work@block_tb (work@block_tb), file:${SURELOG_DIR}/tests/BadLabel/dut.sv, line:60:1, endln:66:10 |vpiTypespec: \_logic_typespec: , line:61:2, endln:61:5 |vpiName:a @@ -759,7 +759,7 @@ design: (work@test) |vpiProcess: \_initial: , line:62:2, endln:65:14 |vpiParent: - \_module: work@block_tb (work@block_tb), file:${SURELOG_DIR}/tests/BadLabel/dut.sv, line:60:1, endln:66:10 + \_module_inst: work@block_tb (work@block_tb), file:${SURELOG_DIR}/tests/BadLabel/dut.sv, line:60:1, endln:66:10 |vpiStmt: \_named_fork: (work@block_tb.name1), line:63:17, endln:65:14 |vpiParent: @@ -785,7 +785,7 @@ design: (work@test) |vpiContAssign: \_cont_assign: , line:61:6, endln:61:7 |vpiParent: - \_module: work@block_tb (work@block_tb), file:${SURELOG_DIR}/tests/BadLabel/dut.sv, line:60:1, endln:66:10 + \_module_inst: work@block_tb (work@block_tb), file:${SURELOG_DIR}/tests/BadLabel/dut.sv, line:60:1, endln:66:10 |vpiNetDeclAssign:1 |vpiRhs: \_constant: , line:61:10, endln:61:11 diff --git a/tests/BadScope/BadScope.log b/tests/BadScope/BadScope.log index 11324ee1b9..f1a680bffc 100644 --- a/tests/BadScope/BadScope.log +++ b/tests/BadScope/BadScope.log @@ -181,7 +181,7 @@ design 1 import_typespec 1 logic_net 1 logic_typespec 14 -module 4 +module_inst 4 operation 4 package 3 param_assign 2 @@ -201,7 +201,7 @@ design 1 import_typespec 1 logic_net 1 logic_typespec 14 -module 4 +module_inst 4 operation 4 package 3 param_assign 2 @@ -281,7 +281,7 @@ design: (work@top3) |vpiTypedef: \_struct_typespec: (pack::status_t), line:4:10, endln:4:16 |vpiParent: - \_module: work@top3 (work@top3), file:${SURELOG_DIR}/tests/BadScope/dut.sv, line:12:1, endln:26:10 + \_module_inst: work@top3 (work@top3), file:${SURELOG_DIR}/tests/BadScope/dut.sv, line:12:1, endln:26:10 |vpiName:pack::status_t |vpiInstance: \_package: pack (pack::), file:${SURELOG_DIR}/tests/BadScope/dut.sv, line:2:1, endln:9:11 @@ -321,14 +321,14 @@ design: (work@top3) |vpiDefName:pack |vpiTop:1 |uhdmallModules: -\_module: work@top3 (work@top3), file:${SURELOG_DIR}/tests/BadScope/dut.sv, line:12:1, endln:26:10 +\_module_inst: work@top3 (work@top3), file:${SURELOG_DIR}/tests/BadScope/dut.sv, line:12:1, endln:26:10 |vpiParent: \_design: (work@top3) |vpiFullName:work@top3 |vpiParameter: \_parameter: (work@top3.MSTATUS_RST_VAL), line:21:22, endln:21:37 |vpiParent: - \_module: work@top3 (work@top3), file:${SURELOG_DIR}/tests/BadScope/dut.sv, line:12:1, endln:26:10 + \_module_inst: work@top3 (work@top3), file:${SURELOG_DIR}/tests/BadScope/dut.sv, line:12:1, endln:26:10 |vpiTypespec: \_struct_typespec: (pack::status_t), line:4:10, endln:4:16 |vpiLocalParam:1 @@ -337,7 +337,7 @@ design: (work@top3) |vpiParamAssign: \_param_assign: , line:21:22, endln:25:54 |vpiParent: - \_module: work@top3 (work@top3), file:${SURELOG_DIR}/tests/BadScope/dut.sv, line:12:1, endln:26:10 + \_module_inst: work@top3 (work@top3), file:${SURELOG_DIR}/tests/BadScope/dut.sv, line:12:1, endln:26:10 |vpiRhs: \_operation: , line:21:40, endln:25:54 |vpiOpType:75 @@ -405,12 +405,12 @@ design: (work@top3) \_import_typespec: (pack), line:13:8, endln:13:15 |vpiDefName:work@top3 |uhdmtopModules: -\_module: work@top3 (work@top3), file:${SURELOG_DIR}/tests/BadScope/dut.sv, line:12:1, endln:26:10 +\_module_inst: work@top3 (work@top3), file:${SURELOG_DIR}/tests/BadScope/dut.sv, line:12:1, endln:26:10 |vpiName:work@top3 |vpiParameter: \_parameter: (work@top3.MSTATUS_RST_VAL), line:21:22, endln:21:37 |vpiParent: - \_module: work@top3 (work@top3), file:${SURELOG_DIR}/tests/BadScope/dut.sv, line:12:1, endln:26:10 + \_module_inst: work@top3 (work@top3), file:${SURELOG_DIR}/tests/BadScope/dut.sv, line:12:1, endln:26:10 |vpiTypespec: \_struct_typespec: (pack::status_t), line:4:10, endln:4:16 |vpiParent: @@ -457,7 +457,7 @@ design: (work@top3) |vpiParamAssign: \_param_assign: , line:21:22, endln:25:54 |vpiParent: - \_module: work@top3 (work@top3), file:${SURELOG_DIR}/tests/BadScope/dut.sv, line:12:1, endln:26:10 + \_module_inst: work@top3 (work@top3), file:${SURELOG_DIR}/tests/BadScope/dut.sv, line:12:1, endln:26:10 |vpiRhs: \_operation: , line:21:40, endln:25:54 |vpiParent: diff --git a/tests/BeginKeywords/BeginKeywords.log b/tests/BeginKeywords/BeginKeywords.log index e7476b1193..797994284f 100644 --- a/tests/BeginKeywords/BeginKeywords.log +++ b/tests/BeginKeywords/BeginKeywords.log @@ -50,7 +50,7 @@ Instance tree: design 1 logic_net 2 logic_typespec 1 -module 2 +module_inst 2 === UHDM Object Stats End === [INF:UH0708] Writing UHDM DB: ${SURELOG_DIR}/build/regression/BeginKeywords/slpp_all/surelog.uhdm ... diff --git a/tests/BiasValue/BiasValue.log b/tests/BiasValue/BiasValue.log index 47560c62e0..19271f8cbc 100644 --- a/tests/BiasValue/BiasValue.log +++ b/tests/BiasValue/BiasValue.log @@ -440,7 +440,7 @@ io_decl 11 logic_net 4 logic_typespec 3 logic_var 2 -module 5 +module_inst 5 operation 8 package 2 param_assign 6 @@ -468,7 +468,7 @@ io_decl 22 logic_net 4 logic_typespec 3 logic_var 2 -module 5 +module_inst 5 operation 9 package 2 param_assign 6 @@ -965,14 +965,14 @@ design: (work@bp_be_rec_to_fp) \_int_typespec: |vpiSigned:1 |uhdmallModules: -\_module: work@bp_be_rec_to_fp (work@bp_be_rec_to_fp), file:${SURELOG_DIR}/tests/BiasValue/dut.sv, line:1:1, endln:10:10 +\_module_inst: work@bp_be_rec_to_fp (work@bp_be_rec_to_fp), file:${SURELOG_DIR}/tests/BiasValue/dut.sv, line:1:1, endln:10:10 |vpiParent: \_design: (work@bp_be_rec_to_fp) |vpiFullName:work@bp_be_rec_to_fp |vpiParameter: \_parameter: (work@bp_be_rec_to_fp.sp_exp_width_gp), line:2:14, endln:2:29 |vpiParent: - \_module: work@bp_be_rec_to_fp (work@bp_be_rec_to_fp), file:${SURELOG_DIR}/tests/BiasValue/dut.sv, line:1:1, endln:10:10 + \_module_inst: work@bp_be_rec_to_fp (work@bp_be_rec_to_fp), file:${SURELOG_DIR}/tests/BiasValue/dut.sv, line:1:1, endln:10:10 |UINT:8 |vpiTypespec: \_int_typespec: @@ -982,7 +982,7 @@ design: (work@bp_be_rec_to_fp) |vpiParameter: \_parameter: (work@bp_be_rec_to_fp.dp_exp_width_gp), line:3:14, endln:3:29 |vpiParent: - \_module: work@bp_be_rec_to_fp (work@bp_be_rec_to_fp), file:${SURELOG_DIR}/tests/BiasValue/dut.sv, line:1:1, endln:10:10 + \_module_inst: work@bp_be_rec_to_fp (work@bp_be_rec_to_fp), file:${SURELOG_DIR}/tests/BiasValue/dut.sv, line:1:1, endln:10:10 |UINT:11 |vpiTypespec: \_int_typespec: @@ -992,14 +992,14 @@ design: (work@bp_be_rec_to_fp) |vpiParameter: \_parameter: (work@bp_be_rec_to_fp.bias_adj_lp), line:4:14, endln:4:25 |vpiParent: - \_module: work@bp_be_rec_to_fp (work@bp_be_rec_to_fp), file:${SURELOG_DIR}/tests/BiasValue/dut.sv, line:1:1, endln:10:10 + \_module_inst: work@bp_be_rec_to_fp (work@bp_be_rec_to_fp), file:${SURELOG_DIR}/tests/BiasValue/dut.sv, line:1:1, endln:10:10 |vpiLocalParam:1 |vpiName:bias_adj_lp |vpiFullName:work@bp_be_rec_to_fp.bias_adj_lp |vpiParamAssign: \_param_assign: , line:2:14, endln:2:35 |vpiParent: - \_module: work@bp_be_rec_to_fp (work@bp_be_rec_to_fp), file:${SURELOG_DIR}/tests/BiasValue/dut.sv, line:1:1, endln:10:10 + \_module_inst: work@bp_be_rec_to_fp (work@bp_be_rec_to_fp), file:${SURELOG_DIR}/tests/BiasValue/dut.sv, line:1:1, endln:10:10 |vpiRhs: \_constant: , line:2:34, endln:2:35 |vpiDecompile:8 @@ -1013,7 +1013,7 @@ design: (work@bp_be_rec_to_fp) |vpiParamAssign: \_param_assign: , line:3:14, endln:3:36 |vpiParent: - \_module: work@bp_be_rec_to_fp (work@bp_be_rec_to_fp), file:${SURELOG_DIR}/tests/BiasValue/dut.sv, line:1:1, endln:10:10 + \_module_inst: work@bp_be_rec_to_fp (work@bp_be_rec_to_fp), file:${SURELOG_DIR}/tests/BiasValue/dut.sv, line:1:1, endln:10:10 |vpiRhs: \_constant: , line:3:34, endln:3:36 |vpiDecompile:11 @@ -1027,7 +1027,7 @@ design: (work@bp_be_rec_to_fp) |vpiParamAssign: \_param_assign: , line:4:14, endln:4:75 |vpiParent: - \_module: work@bp_be_rec_to_fp (work@bp_be_rec_to_fp), file:${SURELOG_DIR}/tests/BiasValue/dut.sv, line:1:1, endln:10:10 + \_module_inst: work@bp_be_rec_to_fp (work@bp_be_rec_to_fp), file:${SURELOG_DIR}/tests/BiasValue/dut.sv, line:1:1, endln:10:10 |vpiRhs: \_operation: , line:4:28, endln:4:75 |vpiOpType:11 @@ -1073,24 +1073,24 @@ design: (work@bp_be_rec_to_fp) |vpiNet: \_logic_net: (work@bp_be_rec_to_fp.adjusted_exp), line:6:28, endln:6:40 |vpiParent: - \_module: work@bp_be_rec_to_fp (work@bp_be_rec_to_fp), file:${SURELOG_DIR}/tests/BiasValue/dut.sv, line:1:1, endln:10:10 + \_module_inst: work@bp_be_rec_to_fp (work@bp_be_rec_to_fp), file:${SURELOG_DIR}/tests/BiasValue/dut.sv, line:1:1, endln:10:10 |vpiName:adjusted_exp |vpiFullName:work@bp_be_rec_to_fp.adjusted_exp |vpiNetType:1 |vpiNet: \_logic_net: (work@bp_be_rec_to_fp.wrong_range), line:8:26, endln:8:37 |vpiParent: - \_module: work@bp_be_rec_to_fp (work@bp_be_rec_to_fp), file:${SURELOG_DIR}/tests/BiasValue/dut.sv, line:1:1, endln:10:10 + \_module_inst: work@bp_be_rec_to_fp (work@bp_be_rec_to_fp), file:${SURELOG_DIR}/tests/BiasValue/dut.sv, line:1:1, endln:10:10 |vpiName:wrong_range |vpiFullName:work@bp_be_rec_to_fp.wrong_range |vpiNetType:36 |uhdmtopModules: -\_module: work@bp_be_rec_to_fp (work@bp_be_rec_to_fp), file:${SURELOG_DIR}/tests/BiasValue/dut.sv, line:1:1, endln:10:10 +\_module_inst: work@bp_be_rec_to_fp (work@bp_be_rec_to_fp), file:${SURELOG_DIR}/tests/BiasValue/dut.sv, line:1:1, endln:10:10 |vpiName:work@bp_be_rec_to_fp |vpiVariables: \_logic_var: (work@bp_be_rec_to_fp.wrong_range), line:8:26, endln:8:37 |vpiParent: - \_module: work@bp_be_rec_to_fp (work@bp_be_rec_to_fp), file:${SURELOG_DIR}/tests/BiasValue/dut.sv, line:1:1, endln:10:10 + \_module_inst: work@bp_be_rec_to_fp (work@bp_be_rec_to_fp), file:${SURELOG_DIR}/tests/BiasValue/dut.sv, line:1:1, endln:10:10 |vpiTypespec: \_logic_typespec: , line:8:3, endln:8:25 |vpiRange: @@ -1135,7 +1135,7 @@ design: (work@bp_be_rec_to_fp) |vpiParameter: \_parameter: (work@bp_be_rec_to_fp.sp_exp_width_gp), line:2:14, endln:2:29 |vpiParent: - \_module: work@bp_be_rec_to_fp (work@bp_be_rec_to_fp), file:${SURELOG_DIR}/tests/BiasValue/dut.sv, line:1:1, endln:10:10 + \_module_inst: work@bp_be_rec_to_fp (work@bp_be_rec_to_fp), file:${SURELOG_DIR}/tests/BiasValue/dut.sv, line:1:1, endln:10:10 |UINT:8 |vpiTypespec: \_int_typespec: @@ -1147,7 +1147,7 @@ design: (work@bp_be_rec_to_fp) |vpiParameter: \_parameter: (work@bp_be_rec_to_fp.dp_exp_width_gp), line:3:14, endln:3:29 |vpiParent: - \_module: work@bp_be_rec_to_fp (work@bp_be_rec_to_fp), file:${SURELOG_DIR}/tests/BiasValue/dut.sv, line:1:1, endln:10:10 + \_module_inst: work@bp_be_rec_to_fp (work@bp_be_rec_to_fp), file:${SURELOG_DIR}/tests/BiasValue/dut.sv, line:1:1, endln:10:10 |UINT:11 |vpiTypespec: \_int_typespec: @@ -1159,14 +1159,14 @@ design: (work@bp_be_rec_to_fp) |vpiParameter: \_parameter: (work@bp_be_rec_to_fp.bias_adj_lp), line:4:14, endln:4:25 |vpiParent: - \_module: work@bp_be_rec_to_fp (work@bp_be_rec_to_fp), file:${SURELOG_DIR}/tests/BiasValue/dut.sv, line:1:1, endln:10:10 + \_module_inst: work@bp_be_rec_to_fp (work@bp_be_rec_to_fp), file:${SURELOG_DIR}/tests/BiasValue/dut.sv, line:1:1, endln:10:10 |vpiLocalParam:1 |vpiName:bias_adj_lp |vpiFullName:work@bp_be_rec_to_fp.bias_adj_lp |vpiParamAssign: \_param_assign: , line:2:14, endln:2:35 |vpiParent: - \_module: work@bp_be_rec_to_fp (work@bp_be_rec_to_fp), file:${SURELOG_DIR}/tests/BiasValue/dut.sv, line:1:1, endln:10:10 + \_module_inst: work@bp_be_rec_to_fp (work@bp_be_rec_to_fp), file:${SURELOG_DIR}/tests/BiasValue/dut.sv, line:1:1, endln:10:10 |vpiRhs: \_constant: , line:2:34, endln:2:35 |vpiDecompile:8 @@ -1180,7 +1180,7 @@ design: (work@bp_be_rec_to_fp) |vpiParamAssign: \_param_assign: , line:3:14, endln:3:36 |vpiParent: - \_module: work@bp_be_rec_to_fp (work@bp_be_rec_to_fp), file:${SURELOG_DIR}/tests/BiasValue/dut.sv, line:1:1, endln:10:10 + \_module_inst: work@bp_be_rec_to_fp (work@bp_be_rec_to_fp), file:${SURELOG_DIR}/tests/BiasValue/dut.sv, line:1:1, endln:10:10 |vpiRhs: \_constant: , line:3:34, endln:3:36 |vpiDecompile:11 @@ -1194,7 +1194,7 @@ design: (work@bp_be_rec_to_fp) |vpiParamAssign: \_param_assign: , line:4:14, endln:4:75 |vpiParent: - \_module: work@bp_be_rec_to_fp (work@bp_be_rec_to_fp), file:${SURELOG_DIR}/tests/BiasValue/dut.sv, line:1:1, endln:10:10 + \_module_inst: work@bp_be_rec_to_fp (work@bp_be_rec_to_fp), file:${SURELOG_DIR}/tests/BiasValue/dut.sv, line:1:1, endln:10:10 |vpiRhs: \_constant: , line:4:28, endln:4:75 |vpiDecompile:-1792 @@ -1208,7 +1208,7 @@ design: (work@bp_be_rec_to_fp) |vpiNet: \_logic_net: (work@bp_be_rec_to_fp.adjusted_exp), line:6:28, endln:6:40 |vpiParent: - \_module: work@bp_be_rec_to_fp (work@bp_be_rec_to_fp), file:${SURELOG_DIR}/tests/BiasValue/dut.sv, line:1:1, endln:10:10 + \_module_inst: work@bp_be_rec_to_fp (work@bp_be_rec_to_fp), file:${SURELOG_DIR}/tests/BiasValue/dut.sv, line:1:1, endln:10:10 |vpiTypespec: \_logic_typespec: , line:6:3, endln:6:27 |vpiRange: @@ -1236,7 +1236,7 @@ design: (work@bp_be_rec_to_fp) |vpiContAssign: \_cont_assign: , line:6:28, endln:6:40 |vpiParent: - \_module: work@bp_be_rec_to_fp (work@bp_be_rec_to_fp), file:${SURELOG_DIR}/tests/BiasValue/dut.sv, line:1:1, endln:10:10 + \_module_inst: work@bp_be_rec_to_fp (work@bp_be_rec_to_fp), file:${SURELOG_DIR}/tests/BiasValue/dut.sv, line:1:1, endln:10:10 |vpiNetDeclAssign:1 |vpiRhs: \_operation: , line:6:43, endln:6:61 diff --git a/tests/BinarySize/BinarySize.log b/tests/BinarySize/BinarySize.log index a471dd7bfd..fa07a2c379 100644 --- a/tests/BinarySize/BinarySize.log +++ b/tests/BinarySize/BinarySize.log @@ -29,7 +29,7 @@ design 1 logic_net 1 logic_typespec 1 logic_var 1 -module 4 +module_inst 4 range 2 ref_obj 18 === UHDM Object Stats End === @@ -42,7 +42,7 @@ design 1 logic_net 1 logic_typespec 1 logic_var 1 -module 4 +module_inst 4 range 2 ref_obj 27 === UHDM Object Stats End === @@ -59,7 +59,7 @@ design: (work@top) |vpiElaborated:1 |vpiName:work@top |uhdmallModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/BinarySize/dut.sv, line:1:1, endln:13:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/BinarySize/dut.sv, line:1:1, endln:13:10 |vpiParent: \_design: (work@top) |vpiFullName:work@top @@ -67,14 +67,14 @@ design: (work@top) |vpiNet: \_logic_net: (work@top.first), line:2:22, endln:2:27 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/BinarySize/dut.sv, line:1:1, endln:13:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/BinarySize/dut.sv, line:1:1, endln:13:10 |vpiName:first |vpiFullName:work@top.first |vpiNetType:36 |vpiContAssign: \_cont_assign: , line:3:10, endln:3:23 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/BinarySize/dut.sv, line:1:1, endln:13:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/BinarySize/dut.sv, line:1:1, endln:13:10 |vpiRhs: \_constant: , line:3:18, endln:3:23 |vpiParent: @@ -94,7 +94,7 @@ design: (work@top) |vpiContAssign: \_cont_assign: , line:4:10, endln:4:22 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/BinarySize/dut.sv, line:1:1, endln:13:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/BinarySize/dut.sv, line:1:1, endln:13:10 |vpiRhs: \_constant: , line:4:18, endln:4:22 |vpiParent: @@ -114,7 +114,7 @@ design: (work@top) |vpiContAssign: \_cont_assign: , line:5:10, endln:5:23 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/BinarySize/dut.sv, line:1:1, endln:13:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/BinarySize/dut.sv, line:1:1, endln:13:10 |vpiRhs: \_constant: , line:5:18, endln:5:23 |vpiParent: @@ -134,7 +134,7 @@ design: (work@top) |vpiContAssign: \_cont_assign: , line:6:10, endln:6:22 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/BinarySize/dut.sv, line:1:1, endln:13:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/BinarySize/dut.sv, line:1:1, endln:13:10 |vpiRhs: \_constant: , line:6:18, endln:6:22 |vpiParent: @@ -154,7 +154,7 @@ design: (work@top) |vpiContAssign: \_cont_assign: , line:7:10, endln:7:23 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/BinarySize/dut.sv, line:1:1, endln:13:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/BinarySize/dut.sv, line:1:1, endln:13:10 |vpiRhs: \_constant: , line:7:18, endln:7:23 |vpiParent: @@ -174,7 +174,7 @@ design: (work@top) |vpiContAssign: \_cont_assign: , line:8:10, endln:8:22 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/BinarySize/dut.sv, line:1:1, endln:13:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/BinarySize/dut.sv, line:1:1, endln:13:10 |vpiRhs: \_constant: , line:8:18, endln:8:22 |vpiParent: @@ -194,7 +194,7 @@ design: (work@top) |vpiContAssign: \_cont_assign: , line:9:10, endln:9:23 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/BinarySize/dut.sv, line:1:1, endln:13:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/BinarySize/dut.sv, line:1:1, endln:13:10 |vpiRhs: \_constant: , line:9:18, endln:9:23 |vpiParent: @@ -214,7 +214,7 @@ design: (work@top) |vpiContAssign: \_cont_assign: , line:10:10, endln:10:22 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/BinarySize/dut.sv, line:1:1, endln:13:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/BinarySize/dut.sv, line:1:1, endln:13:10 |vpiRhs: \_constant: , line:10:18, endln:10:22 |vpiParent: @@ -234,7 +234,7 @@ design: (work@top) |vpiContAssign: \_cont_assign: , line:11:10, endln:11:23 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/BinarySize/dut.sv, line:1:1, endln:13:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/BinarySize/dut.sv, line:1:1, endln:13:10 |vpiRhs: \_constant: , line:11:18, endln:11:23 |vpiParent: @@ -252,12 +252,12 @@ design: (work@top) |vpiActual: \_logic_var: (work@top.first), line:2:22, endln:2:27 |uhdmtopModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/BinarySize/dut.sv, line:1:1, endln:13:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/BinarySize/dut.sv, line:1:1, endln:13:10 |vpiName:work@top |vpiVariables: \_logic_var: (work@top.first), line:2:22, endln:2:27 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/BinarySize/dut.sv, line:1:1, endln:13:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/BinarySize/dut.sv, line:1:1, endln:13:10 |vpiTypespec: \_logic_typespec: , line:2:3, endln:2:21 |vpiRange: @@ -305,7 +305,7 @@ design: (work@top) |vpiContAssign: \_cont_assign: , line:3:10, endln:3:23 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/BinarySize/dut.sv, line:1:1, endln:13:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/BinarySize/dut.sv, line:1:1, endln:13:10 |vpiRhs: \_constant: , line:3:18, endln:3:23 |vpiLhs: @@ -319,7 +319,7 @@ design: (work@top) |vpiContAssign: \_cont_assign: , line:4:10, endln:4:22 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/BinarySize/dut.sv, line:1:1, endln:13:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/BinarySize/dut.sv, line:1:1, endln:13:10 |vpiRhs: \_constant: , line:4:18, endln:4:22 |vpiLhs: @@ -333,7 +333,7 @@ design: (work@top) |vpiContAssign: \_cont_assign: , line:5:10, endln:5:23 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/BinarySize/dut.sv, line:1:1, endln:13:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/BinarySize/dut.sv, line:1:1, endln:13:10 |vpiRhs: \_constant: , line:5:18, endln:5:23 |vpiLhs: @@ -347,7 +347,7 @@ design: (work@top) |vpiContAssign: \_cont_assign: , line:6:10, endln:6:22 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/BinarySize/dut.sv, line:1:1, endln:13:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/BinarySize/dut.sv, line:1:1, endln:13:10 |vpiRhs: \_constant: , line:6:18, endln:6:22 |vpiLhs: @@ -361,7 +361,7 @@ design: (work@top) |vpiContAssign: \_cont_assign: , line:7:10, endln:7:23 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/BinarySize/dut.sv, line:1:1, endln:13:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/BinarySize/dut.sv, line:1:1, endln:13:10 |vpiRhs: \_constant: , line:7:18, endln:7:23 |vpiLhs: @@ -375,7 +375,7 @@ design: (work@top) |vpiContAssign: \_cont_assign: , line:8:10, endln:8:22 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/BinarySize/dut.sv, line:1:1, endln:13:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/BinarySize/dut.sv, line:1:1, endln:13:10 |vpiRhs: \_constant: , line:8:18, endln:8:22 |vpiLhs: @@ -389,7 +389,7 @@ design: (work@top) |vpiContAssign: \_cont_assign: , line:9:10, endln:9:23 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/BinarySize/dut.sv, line:1:1, endln:13:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/BinarySize/dut.sv, line:1:1, endln:13:10 |vpiRhs: \_constant: , line:9:18, endln:9:23 |vpiLhs: @@ -403,7 +403,7 @@ design: (work@top) |vpiContAssign: \_cont_assign: , line:10:10, endln:10:22 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/BinarySize/dut.sv, line:1:1, endln:13:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/BinarySize/dut.sv, line:1:1, endln:13:10 |vpiRhs: \_constant: , line:10:18, endln:10:22 |vpiLhs: @@ -417,7 +417,7 @@ design: (work@top) |vpiContAssign: \_cont_assign: , line:11:10, endln:11:23 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/BinarySize/dut.sv, line:1:1, endln:13:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/BinarySize/dut.sv, line:1:1, endln:13:10 |vpiRhs: \_constant: , line:11:18, endln:11:23 |vpiLhs: diff --git a/tests/BindStmt/BindStmt.log b/tests/BindStmt/BindStmt.log index bd15e63035..0b674d260c 100644 --- a/tests/BindStmt/BindStmt.log +++ b/tests/BindStmt/BindStmt.log @@ -444,7 +444,7 @@ gen_scope_array 2 int_typespec 2 logic_net 28 logic_typespec 38 -module 31 +module_inst 31 operation 3 param_assign 11 parameter 11 @@ -463,7 +463,7 @@ gen_scope_array 3 int_typespec 2 logic_net 28 logic_typespec 38 -module 31 +module_inst 31 operation 3 param_assign 11 parameter 11 @@ -484,14 +484,14 @@ design: (work@testbench) |vpiElaborated:1 |vpiName:work@testbench |uhdmallModules: -\_module: work@bp_lce (work@bp_lce), file:${SURELOG_DIR}/tests/BindStmt/dut.sv, line:1:1, endln:3:10 +\_module_inst: work@bp_lce (work@bp_lce), file:${SURELOG_DIR}/tests/BindStmt/dut.sv, line:1:1, endln:3:10 |vpiParent: \_design: (work@testbench) |vpiFullName:work@bp_lce |vpiParameter: \_parameter: (work@bp_lce.sets_p), line:1:27, endln:1:33 |vpiParent: - \_module: work@bp_lce (work@bp_lce), file:${SURELOG_DIR}/tests/BindStmt/dut.sv, line:1:1, endln:3:10 + \_module_inst: work@bp_lce (work@bp_lce), file:${SURELOG_DIR}/tests/BindStmt/dut.sv, line:1:1, endln:3:10 |STRING:inv |vpiTypespec: \_string_typespec: @@ -500,7 +500,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:1:27, endln:1:41 |vpiParent: - \_module: work@bp_lce (work@bp_lce), file:${SURELOG_DIR}/tests/BindStmt/dut.sv, line:1:1, endln:3:10 + \_module_inst: work@bp_lce (work@bp_lce), file:${SURELOG_DIR}/tests/BindStmt/dut.sv, line:1:1, endln:3:10 |vpiRhs: \_constant: , line:1:36, endln:1:41 |vpiDecompile:inv @@ -515,21 +515,21 @@ design: (work@testbench) |vpiNet: \_logic_net: (work@bp_lce.a), line:1:55, endln:1:56 |vpiParent: - \_module: work@bp_lce (work@bp_lce), file:${SURELOG_DIR}/tests/BindStmt/dut.sv, line:1:1, endln:3:10 + \_module_inst: work@bp_lce (work@bp_lce), file:${SURELOG_DIR}/tests/BindStmt/dut.sv, line:1:1, endln:3:10 |vpiName:a |vpiFullName:work@bp_lce.a |vpiNetType:36 |vpiNet: \_logic_net: (work@bp_lce.b), line:1:71, endln:1:72 |vpiParent: - \_module: work@bp_lce (work@bp_lce), file:${SURELOG_DIR}/tests/BindStmt/dut.sv, line:1:1, endln:3:10 + \_module_inst: work@bp_lce (work@bp_lce), file:${SURELOG_DIR}/tests/BindStmt/dut.sv, line:1:1, endln:3:10 |vpiName:b |vpiFullName:work@bp_lce.b |vpiNetType:36 |vpiPort: \_port: (a), line:1:55, endln:1:56 |vpiParent: - \_module: work@bp_lce (work@bp_lce), file:${SURELOG_DIR}/tests/BindStmt/dut.sv, line:1:1, endln:3:10 + \_module_inst: work@bp_lce (work@bp_lce), file:${SURELOG_DIR}/tests/BindStmt/dut.sv, line:1:1, endln:3:10 |vpiName:a |vpiDirection:1 |vpiLowConn: @@ -541,7 +541,7 @@ design: (work@testbench) |vpiPort: \_port: (b), line:1:71, endln:1:72 |vpiParent: - \_module: work@bp_lce (work@bp_lce), file:${SURELOG_DIR}/tests/BindStmt/dut.sv, line:1:1, endln:3:10 + \_module_inst: work@bp_lce (work@bp_lce), file:${SURELOG_DIR}/tests/BindStmt/dut.sv, line:1:1, endln:3:10 |vpiName:b |vpiDirection:2 |vpiLowConn: @@ -553,7 +553,7 @@ design: (work@testbench) |vpiContAssign: \_cont_assign: , line:2:8, endln:2:12 |vpiParent: - \_module: work@bp_lce (work@bp_lce), file:${SURELOG_DIR}/tests/BindStmt/dut.sv, line:1:1, endln:3:10 + \_module_inst: work@bp_lce (work@bp_lce), file:${SURELOG_DIR}/tests/BindStmt/dut.sv, line:1:1, endln:3:10 |vpiRhs: \_ref_obj: (work@bp_lce.d), line:2:11, endln:2:12 |vpiParent: @@ -571,14 +571,14 @@ design: (work@testbench) |vpiActual: \_logic_net: (c) |uhdmallModules: -\_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BindStmt/dut.sv, line:8:1, endln:11:10 +\_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BindStmt/dut.sv, line:8:1, endln:11:10 |vpiParent: \_design: (work@testbench) |vpiFullName:work@bp_me_nonsynth_lce_tracer |vpiParameter: \_parameter: (work@bp_me_nonsynth_lce_tracer.sets_p), line:8:46, endln:8:52 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BindStmt/dut.sv, line:8:1, endln:11:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BindStmt/dut.sv, line:8:1, endln:11:10 |STRING:inv |vpiTypespec: \_string_typespec: @@ -587,7 +587,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:8:46, endln:8:60 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BindStmt/dut.sv, line:8:1, endln:11:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BindStmt/dut.sv, line:8:1, endln:11:10 |vpiRhs: \_constant: , line:8:55, endln:8:60 |vpiDecompile:inv @@ -602,21 +602,21 @@ design: (work@testbench) |vpiNet: \_logic_net: (work@bp_me_nonsynth_lce_tracer.c), line:8:74, endln:8:75 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BindStmt/dut.sv, line:8:1, endln:11:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BindStmt/dut.sv, line:8:1, endln:11:10 |vpiName:c |vpiFullName:work@bp_me_nonsynth_lce_tracer.c |vpiNetType:36 |vpiNet: \_logic_net: (work@bp_me_nonsynth_lce_tracer.d), line:8:90, endln:8:91 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BindStmt/dut.sv, line:8:1, endln:11:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BindStmt/dut.sv, line:8:1, endln:11:10 |vpiName:d |vpiFullName:work@bp_me_nonsynth_lce_tracer.d |vpiNetType:36 |vpiPort: \_port: (c), line:8:74, endln:8:75 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BindStmt/dut.sv, line:8:1, endln:11:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BindStmt/dut.sv, line:8:1, endln:11:10 |vpiName:c |vpiDirection:1 |vpiLowConn: @@ -628,7 +628,7 @@ design: (work@testbench) |vpiPort: \_port: (d), line:8:90, endln:8:91 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BindStmt/dut.sv, line:8:1, endln:11:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BindStmt/dut.sv, line:8:1, endln:11:10 |vpiName:d |vpiDirection:2 |vpiLowConn: @@ -640,7 +640,7 @@ design: (work@testbench) |vpiContAssign: \_cont_assign: , line:9:10, endln:9:14 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BindStmt/dut.sv, line:8:1, endln:11:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BindStmt/dut.sv, line:8:1, endln:11:10 |vpiRhs: \_ref_obj: (work@bp_me_nonsynth_lce_tracer.b), line:9:13, endln:9:14 |vpiParent: @@ -658,14 +658,14 @@ design: (work@testbench) |vpiActual: \_logic_net: (a) |uhdmallModules: -\_module: work@bp_me_nonsynth_lce_tracer2 (work@bp_me_nonsynth_lce_tracer2), file:${SURELOG_DIR}/tests/BindStmt/dut.sv, line:13:1, endln:16:10 +\_module_inst: work@bp_me_nonsynth_lce_tracer2 (work@bp_me_nonsynth_lce_tracer2), file:${SURELOG_DIR}/tests/BindStmt/dut.sv, line:13:1, endln:16:10 |vpiParent: \_design: (work@testbench) |vpiFullName:work@bp_me_nonsynth_lce_tracer2 |vpiParameter: \_parameter: (work@bp_me_nonsynth_lce_tracer2.sets_p), line:13:47, endln:13:53 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer2 (work@bp_me_nonsynth_lce_tracer2), file:${SURELOG_DIR}/tests/BindStmt/dut.sv, line:13:1, endln:16:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer2 (work@bp_me_nonsynth_lce_tracer2), file:${SURELOG_DIR}/tests/BindStmt/dut.sv, line:13:1, endln:16:10 |STRING:inv |vpiTypespec: \_string_typespec: @@ -674,7 +674,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:13:47, endln:13:61 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer2 (work@bp_me_nonsynth_lce_tracer2), file:${SURELOG_DIR}/tests/BindStmt/dut.sv, line:13:1, endln:16:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer2 (work@bp_me_nonsynth_lce_tracer2), file:${SURELOG_DIR}/tests/BindStmt/dut.sv, line:13:1, endln:16:10 |vpiRhs: \_constant: , line:13:56, endln:13:61 |vpiDecompile:inv @@ -689,28 +689,28 @@ design: (work@testbench) |vpiNet: \_logic_net: (work@bp_me_nonsynth_lce_tracer2.a), line:13:75, endln:13:76 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer2 (work@bp_me_nonsynth_lce_tracer2), file:${SURELOG_DIR}/tests/BindStmt/dut.sv, line:13:1, endln:16:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer2 (work@bp_me_nonsynth_lce_tracer2), file:${SURELOG_DIR}/tests/BindStmt/dut.sv, line:13:1, endln:16:10 |vpiName:a |vpiFullName:work@bp_me_nonsynth_lce_tracer2.a |vpiNetType:36 |vpiNet: \_logic_net: (work@bp_me_nonsynth_lce_tracer2.b), line:13:91, endln:13:92 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer2 (work@bp_me_nonsynth_lce_tracer2), file:${SURELOG_DIR}/tests/BindStmt/dut.sv, line:13:1, endln:16:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer2 (work@bp_me_nonsynth_lce_tracer2), file:${SURELOG_DIR}/tests/BindStmt/dut.sv, line:13:1, endln:16:10 |vpiName:b |vpiFullName:work@bp_me_nonsynth_lce_tracer2.b |vpiNetType:36 |vpiNet: \_logic_net: (work@bp_me_nonsynth_lce_tracer2.clk), line:13:106, endln:13:109 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer2 (work@bp_me_nonsynth_lce_tracer2), file:${SURELOG_DIR}/tests/BindStmt/dut.sv, line:13:1, endln:16:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer2 (work@bp_me_nonsynth_lce_tracer2), file:${SURELOG_DIR}/tests/BindStmt/dut.sv, line:13:1, endln:16:10 |vpiName:clk |vpiFullName:work@bp_me_nonsynth_lce_tracer2.clk |vpiNetType:36 |vpiPort: \_port: (a), line:13:75, endln:13:76 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer2 (work@bp_me_nonsynth_lce_tracer2), file:${SURELOG_DIR}/tests/BindStmt/dut.sv, line:13:1, endln:16:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer2 (work@bp_me_nonsynth_lce_tracer2), file:${SURELOG_DIR}/tests/BindStmt/dut.sv, line:13:1, endln:16:10 |vpiName:a |vpiDirection:1 |vpiLowConn: @@ -722,7 +722,7 @@ design: (work@testbench) |vpiPort: \_port: (b), line:13:91, endln:13:92 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer2 (work@bp_me_nonsynth_lce_tracer2), file:${SURELOG_DIR}/tests/BindStmt/dut.sv, line:13:1, endln:16:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer2 (work@bp_me_nonsynth_lce_tracer2), file:${SURELOG_DIR}/tests/BindStmt/dut.sv, line:13:1, endln:16:10 |vpiName:b |vpiDirection:2 |vpiLowConn: @@ -734,7 +734,7 @@ design: (work@testbench) |vpiPort: \_port: (clk), line:13:106, endln:13:109 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer2 (work@bp_me_nonsynth_lce_tracer2), file:${SURELOG_DIR}/tests/BindStmt/dut.sv, line:13:1, endln:16:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer2 (work@bp_me_nonsynth_lce_tracer2), file:${SURELOG_DIR}/tests/BindStmt/dut.sv, line:13:1, endln:16:10 |vpiName:clk |vpiDirection:1 |vpiLowConn: @@ -746,7 +746,7 @@ design: (work@testbench) |vpiContAssign: \_cont_assign: , line:14:10, endln:14:14 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer2 (work@bp_me_nonsynth_lce_tracer2), file:${SURELOG_DIR}/tests/BindStmt/dut.sv, line:13:1, endln:16:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer2 (work@bp_me_nonsynth_lce_tracer2), file:${SURELOG_DIR}/tests/BindStmt/dut.sv, line:13:1, endln:16:10 |vpiRhs: \_ref_obj: (work@bp_me_nonsynth_lce_tracer2.b), line:14:13, endln:14:14 |vpiParent: @@ -764,26 +764,26 @@ design: (work@testbench) |vpiActual: \_logic_net: (work@testbench.u1.lce_tracer2.a), line:13:75, endln:13:76 |uhdmallModules: -\_module: work@inter (work@inter), file:${SURELOG_DIR}/tests/BindStmt/dut.sv, line:19:1, endln:23:10 +\_module_inst: work@inter (work@inter), file:${SURELOG_DIR}/tests/BindStmt/dut.sv, line:19:1, endln:23:10 |vpiParent: \_design: (work@testbench) |vpiFullName:work@inter |vpiDefName:work@inter |uhdmallModules: -\_module: work@sub (work@sub), file:${SURELOG_DIR}/tests/BindStmt/dut.sv, line:5:1, endln:6:10 +\_module_inst: work@sub (work@sub), file:${SURELOG_DIR}/tests/BindStmt/dut.sv, line:5:1, endln:6:10 |vpiParent: \_design: (work@testbench) |vpiFullName:work@sub |vpiDefName:work@sub |uhdmallModules: -\_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BindStmt/dut.sv, line:25:1, endln:52:10 +\_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BindStmt/dut.sv, line:25:1, endln:52:10 |vpiParent: \_design: (work@testbench) |vpiFullName:work@testbench |vpiParameter: \_parameter: (work@testbench.p), line:30:13, endln:30:14 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BindStmt/dut.sv, line:25:1, endln:52:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BindStmt/dut.sv, line:25:1, endln:52:10 |UINT:0 |vpiTypespec: \_int_typespec: @@ -792,7 +792,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:30:13, endln:30:18 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BindStmt/dut.sv, line:25:1, endln:52:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BindStmt/dut.sv, line:25:1, endln:52:10 |vpiRhs: \_constant: , line:30:17, endln:30:18 |vpiDecompile:0 @@ -807,14 +807,14 @@ design: (work@testbench) |vpiNet: \_logic_net: (work@testbench.clk), line:25:31, endln:25:34 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BindStmt/dut.sv, line:25:1, endln:52:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BindStmt/dut.sv, line:25:1, endln:52:10 |vpiName:clk |vpiFullName:work@testbench.clk |vpiNetType:36 |vpiPort: \_port: (clk), line:25:31, endln:25:34 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BindStmt/dut.sv, line:25:1, endln:52:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BindStmt/dut.sv, line:25:1, endln:52:10 |vpiName:clk |vpiDirection:1 |vpiLowConn: @@ -824,12 +824,12 @@ design: (work@testbench) |vpiTypedef: \_logic_typespec: , line:25:25, endln:25:30 |uhdmtopModules: -\_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BindStmt/dut.sv, line:25:1, endln:52:10 +\_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BindStmt/dut.sv, line:25:1, endln:52:10 |vpiName:work@testbench |vpiParameter: \_parameter: (work@testbench.p), line:30:13, endln:30:14 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BindStmt/dut.sv, line:25:1, endln:52:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BindStmt/dut.sv, line:25:1, endln:52:10 |UINT:0 |vpiTypespec: \_int_typespec: @@ -840,7 +840,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:30:13, endln:30:18 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BindStmt/dut.sv, line:25:1, endln:52:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BindStmt/dut.sv, line:25:1, endln:52:10 |vpiRhs: \_constant: , line:30:17, endln:30:18 |vpiDecompile:0 @@ -856,7 +856,7 @@ design: (work@testbench) |vpiNet: \_logic_net: (work@testbench.clk), line:25:31, endln:25:34 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BindStmt/dut.sv, line:25:1, endln:52:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BindStmt/dut.sv, line:25:1, endln:52:10 |vpiTypespec: \_logic_typespec: , line:25:25, endln:25:30 |vpiName:clk @@ -866,7 +866,7 @@ design: (work@testbench) |vpiPort: \_port: (clk), line:25:31, endln:25:34 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BindStmt/dut.sv, line:25:1, endln:52:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BindStmt/dut.sv, line:25:1, endln:52:10 |vpiName:clk |vpiDirection:1 |vpiLowConn: @@ -880,17 +880,17 @@ design: (work@testbench) |vpiTypedef: \_logic_typespec: , line:25:25, endln:25:30 |vpiInstance: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BindStmt/dut.sv, line:25:1, endln:52:10 - |vpiModule: - \_module: work@bp_lce (work@testbench.u1), file:${SURELOG_DIR}/tests/BindStmt/dut.sv, line:27:3, endln:27:30 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BindStmt/dut.sv, line:25:1, endln:52:10 + |vpiModuleInst: + \_module_inst: work@bp_lce (work@testbench.u1), file:${SURELOG_DIR}/tests/BindStmt/dut.sv, line:27:3, endln:27:30 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BindStmt/dut.sv, line:25:1, endln:52:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BindStmt/dut.sv, line:25:1, endln:52:10 |vpiName:u1 |vpiFullName:work@testbench.u1 |vpiParameter: \_parameter: (work@testbench.u1.sets_p), line:1:27, endln:1:33 |vpiParent: - \_module: work@bp_lce (work@testbench.u1), file:${SURELOG_DIR}/tests/BindStmt/dut.sv, line:27:3, endln:27:30 + \_module_inst: work@bp_lce (work@testbench.u1), file:${SURELOG_DIR}/tests/BindStmt/dut.sv, line:27:3, endln:27:30 |STRING:inv |vpiTypespec: \_string_typespec: @@ -901,7 +901,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:1:27, endln:1:41 |vpiParent: - \_module: work@bp_lce (work@testbench.u1), file:${SURELOG_DIR}/tests/BindStmt/dut.sv, line:27:3, endln:27:30 + \_module_inst: work@bp_lce (work@testbench.u1), file:${SURELOG_DIR}/tests/BindStmt/dut.sv, line:27:3, endln:27:30 |vpiOverriden:1 |vpiRhs: \_constant: , line:1:36, endln:1:41 @@ -919,7 +919,7 @@ design: (work@testbench) |vpiNet: \_logic_net: (work@testbench.u1.a), line:1:55, endln:1:56 |vpiParent: - \_module: work@bp_lce (work@testbench.u1), file:${SURELOG_DIR}/tests/BindStmt/dut.sv, line:27:3, endln:27:30 + \_module_inst: work@bp_lce (work@testbench.u1), file:${SURELOG_DIR}/tests/BindStmt/dut.sv, line:27:3, endln:27:30 |vpiTypespec: \_logic_typespec: , line:1:49, endln:1:54 |vpiName:a @@ -928,7 +928,7 @@ design: (work@testbench) |vpiNet: \_logic_net: (work@testbench.u1.b), line:1:71, endln:1:72 |vpiParent: - \_module: work@bp_lce (work@testbench.u1), file:${SURELOG_DIR}/tests/BindStmt/dut.sv, line:27:3, endln:27:30 + \_module_inst: work@bp_lce (work@testbench.u1), file:${SURELOG_DIR}/tests/BindStmt/dut.sv, line:27:3, endln:27:30 |vpiTypespec: \_logic_typespec: , line:1:65, endln:1:70 |vpiName:b @@ -943,11 +943,11 @@ design: (work@testbench) |vpiName:d |vpiNetType:1 |vpiInstance: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BindStmt/dut.sv, line:25:1, endln:52:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BindStmt/dut.sv, line:25:1, endln:52:10 |vpiPort: \_port: (a), line:1:55, endln:1:56 |vpiParent: - \_module: work@bp_lce (work@testbench.u1), file:${SURELOG_DIR}/tests/BindStmt/dut.sv, line:27:3, endln:27:30 + \_module_inst: work@bp_lce (work@testbench.u1), file:${SURELOG_DIR}/tests/BindStmt/dut.sv, line:27:3, endln:27:30 |vpiName:a |vpiDirection:1 |vpiLowConn: @@ -961,11 +961,11 @@ design: (work@testbench) |vpiTypedef: \_logic_typespec: , line:1:49, endln:1:54 |vpiInstance: - \_module: work@bp_lce (work@testbench.u1), file:${SURELOG_DIR}/tests/BindStmt/dut.sv, line:27:3, endln:27:30 + \_module_inst: work@bp_lce (work@testbench.u1), file:${SURELOG_DIR}/tests/BindStmt/dut.sv, line:27:3, endln:27:30 |vpiPort: \_port: (b), line:1:71, endln:1:72 |vpiParent: - \_module: work@bp_lce (work@testbench.u1), file:${SURELOG_DIR}/tests/BindStmt/dut.sv, line:27:3, endln:27:30 + \_module_inst: work@bp_lce (work@testbench.u1), file:${SURELOG_DIR}/tests/BindStmt/dut.sv, line:27:3, endln:27:30 |vpiName:b |vpiDirection:2 |vpiLowConn: @@ -979,17 +979,17 @@ design: (work@testbench) |vpiTypedef: \_logic_typespec: , line:1:65, endln:1:70 |vpiInstance: - \_module: work@bp_lce (work@testbench.u1), file:${SURELOG_DIR}/tests/BindStmt/dut.sv, line:27:3, endln:27:30 - |vpiModule: - \_module: work@bp_me_nonsynth_lce_tracer (work@testbench.lce_tracer1), file:${SURELOG_DIR}/tests/BindStmt/dut.sv, line:34:13, endln:36:41 + \_module_inst: work@bp_lce (work@testbench.u1), file:${SURELOG_DIR}/tests/BindStmt/dut.sv, line:27:3, endln:27:30 + |vpiModuleInst: + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@testbench.lce_tracer1), file:${SURELOG_DIR}/tests/BindStmt/dut.sv, line:34:13, endln:36:41 |vpiParent: - \_module: work@bp_lce (work@testbench.u1), file:${SURELOG_DIR}/tests/BindStmt/dut.sv, line:27:3, endln:27:30 + \_module_inst: work@bp_lce (work@testbench.u1), file:${SURELOG_DIR}/tests/BindStmt/dut.sv, line:27:3, endln:27:30 |vpiName:lce_tracer1 |vpiFullName:work@testbench.lce_tracer1 |vpiParameter: \_parameter: (work@testbench.u1.lce_tracer1.sets_p), line:8:46, endln:8:52 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@testbench.lce_tracer1), file:${SURELOG_DIR}/tests/BindStmt/dut.sv, line:34:13, endln:36:41 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@testbench.lce_tracer1), file:${SURELOG_DIR}/tests/BindStmt/dut.sv, line:34:13, endln:36:41 |STRING:inv |vpiTypespec: \_string_typespec: @@ -1000,7 +1000,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:8:46, endln:8:60 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@testbench.lce_tracer1), file:${SURELOG_DIR}/tests/BindStmt/dut.sv, line:34:13, endln:36:41 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@testbench.lce_tracer1), file:${SURELOG_DIR}/tests/BindStmt/dut.sv, line:34:13, endln:36:41 |vpiOverriden:1 |vpiRhs: \_constant: , line:8:55, endln:8:60 @@ -1018,7 +1018,7 @@ design: (work@testbench) |vpiNet: \_logic_net: (work@testbench.u1.lce_tracer1.c), line:8:74, endln:8:75 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@testbench.lce_tracer1), file:${SURELOG_DIR}/tests/BindStmt/dut.sv, line:34:13, endln:36:41 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@testbench.lce_tracer1), file:${SURELOG_DIR}/tests/BindStmt/dut.sv, line:34:13, endln:36:41 |vpiTypespec: \_logic_typespec: , line:8:68, endln:8:73 |vpiName:c @@ -1027,7 +1027,7 @@ design: (work@testbench) |vpiNet: \_logic_net: (work@testbench.u1.lce_tracer1.d), line:8:90, endln:8:91 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@testbench.lce_tracer1), file:${SURELOG_DIR}/tests/BindStmt/dut.sv, line:34:13, endln:36:41 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@testbench.lce_tracer1), file:${SURELOG_DIR}/tests/BindStmt/dut.sv, line:34:13, endln:36:41 |vpiTypespec: \_logic_typespec: , line:8:84, endln:8:89 |vpiName:d @@ -1042,11 +1042,11 @@ design: (work@testbench) |vpiName:b |vpiNetType:1 |vpiInstance: - \_module: work@bp_lce (work@testbench.u1), file:${SURELOG_DIR}/tests/BindStmt/dut.sv, line:27:3, endln:27:30 + \_module_inst: work@bp_lce (work@testbench.u1), file:${SURELOG_DIR}/tests/BindStmt/dut.sv, line:27:3, endln:27:30 |vpiPort: \_port: (c), line:8:74, endln:8:75 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@testbench.lce_tracer1), file:${SURELOG_DIR}/tests/BindStmt/dut.sv, line:34:13, endln:36:41 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@testbench.lce_tracer1), file:${SURELOG_DIR}/tests/BindStmt/dut.sv, line:34:13, endln:36:41 |vpiName:c |vpiDirection:1 |vpiHighConn: @@ -1068,11 +1068,11 @@ design: (work@testbench) |vpiTypedef: \_logic_typespec: , line:8:68, endln:8:73 |vpiInstance: - \_module: work@bp_me_nonsynth_lce_tracer (work@testbench.lce_tracer1), file:${SURELOG_DIR}/tests/BindStmt/dut.sv, line:34:13, endln:36:41 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@testbench.lce_tracer1), file:${SURELOG_DIR}/tests/BindStmt/dut.sv, line:34:13, endln:36:41 |vpiPort: \_port: (d), line:8:90, endln:8:91 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@testbench.lce_tracer1), file:${SURELOG_DIR}/tests/BindStmt/dut.sv, line:34:13, endln:36:41 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@testbench.lce_tracer1), file:${SURELOG_DIR}/tests/BindStmt/dut.sv, line:34:13, endln:36:41 |vpiName:d |vpiDirection:2 |vpiHighConn: @@ -1094,22 +1094,22 @@ design: (work@testbench) |vpiTypedef: \_logic_typespec: , line:8:84, endln:8:89 |vpiInstance: - \_module: work@bp_me_nonsynth_lce_tracer (work@testbench.lce_tracer1), file:${SURELOG_DIR}/tests/BindStmt/dut.sv, line:34:13, endln:36:41 - |vpiModule: - \_module: work@sub (work@testbench.lce_tracer1.sub1), file:${SURELOG_DIR}/tests/BindStmt/dut.sv, line:10:3, endln:10:14 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@testbench.lce_tracer1), file:${SURELOG_DIR}/tests/BindStmt/dut.sv, line:34:13, endln:36:41 + |vpiModuleInst: + \_module_inst: work@sub (work@testbench.lce_tracer1.sub1), file:${SURELOG_DIR}/tests/BindStmt/dut.sv, line:10:3, endln:10:14 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@testbench.lce_tracer1), file:${SURELOG_DIR}/tests/BindStmt/dut.sv, line:34:13, endln:36:41 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@testbench.lce_tracer1), file:${SURELOG_DIR}/tests/BindStmt/dut.sv, line:34:13, endln:36:41 |vpiName:sub1 |vpiFullName:work@testbench.lce_tracer1.sub1 |vpiDefName:work@sub |vpiDefFile:${SURELOG_DIR}/tests/BindStmt/dut.sv |vpiDefLineNo:5 |vpiInstance: - \_module: work@bp_me_nonsynth_lce_tracer (work@testbench.lce_tracer1), file:${SURELOG_DIR}/tests/BindStmt/dut.sv, line:34:13, endln:36:41 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@testbench.lce_tracer1), file:${SURELOG_DIR}/tests/BindStmt/dut.sv, line:34:13, endln:36:41 |vpiContAssign: \_cont_assign: , line:9:10, endln:9:14 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@testbench.lce_tracer1), file:${SURELOG_DIR}/tests/BindStmt/dut.sv, line:34:13, endln:36:41 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@testbench.lce_tracer1), file:${SURELOG_DIR}/tests/BindStmt/dut.sv, line:34:13, endln:36:41 |vpiRhs: \_ref_obj: (work@testbench.u1.lce_tracer1.b), line:9:13, endln:9:14 |vpiParent: @@ -1126,16 +1126,16 @@ design: (work@testbench) |vpiFullName:work@testbench.u1.lce_tracer1.a |vpiActual: \_logic_net: (a) - |vpiModule: - \_module: work@bp_me_nonsynth_lce_tracer2 (work@testbench.lce_tracer2), file:${SURELOG_DIR}/tests/BindStmt/dut.sv, line:40:13, endln:42:31 + |vpiModuleInst: + \_module_inst: work@bp_me_nonsynth_lce_tracer2 (work@testbench.lce_tracer2), file:${SURELOG_DIR}/tests/BindStmt/dut.sv, line:40:13, endln:42:31 |vpiParent: - \_module: work@bp_lce (work@testbench.u1), file:${SURELOG_DIR}/tests/BindStmt/dut.sv, line:27:3, endln:27:30 + \_module_inst: work@bp_lce (work@testbench.u1), file:${SURELOG_DIR}/tests/BindStmt/dut.sv, line:27:3, endln:27:30 |vpiName:lce_tracer2 |vpiFullName:work@testbench.lce_tracer2 |vpiParameter: \_parameter: (work@testbench.u1.lce_tracer2.sets_p), line:13:47, endln:13:53 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer2 (work@testbench.lce_tracer2), file:${SURELOG_DIR}/tests/BindStmt/dut.sv, line:40:13, endln:42:31 + \_module_inst: work@bp_me_nonsynth_lce_tracer2 (work@testbench.lce_tracer2), file:${SURELOG_DIR}/tests/BindStmt/dut.sv, line:40:13, endln:42:31 |STRING:inv |vpiTypespec: \_string_typespec: @@ -1146,7 +1146,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:13:47, endln:13:61 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer2 (work@testbench.lce_tracer2), file:${SURELOG_DIR}/tests/BindStmt/dut.sv, line:40:13, endln:42:31 + \_module_inst: work@bp_me_nonsynth_lce_tracer2 (work@testbench.lce_tracer2), file:${SURELOG_DIR}/tests/BindStmt/dut.sv, line:40:13, endln:42:31 |vpiOverriden:1 |vpiRhs: \_constant: , line:13:56, endln:13:61 @@ -1164,7 +1164,7 @@ design: (work@testbench) |vpiNet: \_logic_net: (work@testbench.u1.lce_tracer2.a), line:13:75, endln:13:76 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer2 (work@testbench.lce_tracer2), file:${SURELOG_DIR}/tests/BindStmt/dut.sv, line:40:13, endln:42:31 + \_module_inst: work@bp_me_nonsynth_lce_tracer2 (work@testbench.lce_tracer2), file:${SURELOG_DIR}/tests/BindStmt/dut.sv, line:40:13, endln:42:31 |vpiTypespec: \_logic_typespec: , line:13:69, endln:13:74 |vpiName:a @@ -1173,7 +1173,7 @@ design: (work@testbench) |vpiNet: \_logic_net: (work@testbench.u1.lce_tracer2.b), line:13:91, endln:13:92 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer2 (work@testbench.lce_tracer2), file:${SURELOG_DIR}/tests/BindStmt/dut.sv, line:40:13, endln:42:31 + \_module_inst: work@bp_me_nonsynth_lce_tracer2 (work@testbench.lce_tracer2), file:${SURELOG_DIR}/tests/BindStmt/dut.sv, line:40:13, endln:42:31 |vpiTypespec: \_logic_typespec: , line:13:85, endln:13:90 |vpiName:b @@ -1182,18 +1182,18 @@ design: (work@testbench) |vpiNet: \_logic_net: (work@testbench.u1.lce_tracer2.clk), line:13:106, endln:13:109 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer2 (work@testbench.lce_tracer2), file:${SURELOG_DIR}/tests/BindStmt/dut.sv, line:40:13, endln:42:31 + \_module_inst: work@bp_me_nonsynth_lce_tracer2 (work@testbench.lce_tracer2), file:${SURELOG_DIR}/tests/BindStmt/dut.sv, line:40:13, endln:42:31 |vpiTypespec: \_logic_typespec: , line:13:100, endln:13:105 |vpiName:clk |vpiFullName:work@testbench.u1.lce_tracer2.clk |vpiNetType:36 |vpiInstance: - \_module: work@bp_lce (work@testbench.u1), file:${SURELOG_DIR}/tests/BindStmt/dut.sv, line:27:3, endln:27:30 + \_module_inst: work@bp_lce (work@testbench.u1), file:${SURELOG_DIR}/tests/BindStmt/dut.sv, line:27:3, endln:27:30 |vpiPort: \_port: (a), line:13:75, endln:13:76 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer2 (work@testbench.lce_tracer2), file:${SURELOG_DIR}/tests/BindStmt/dut.sv, line:40:13, endln:42:31 + \_module_inst: work@bp_me_nonsynth_lce_tracer2 (work@testbench.lce_tracer2), file:${SURELOG_DIR}/tests/BindStmt/dut.sv, line:40:13, endln:42:31 |vpiName:a |vpiDirection:1 |vpiHighConn: @@ -1215,11 +1215,11 @@ design: (work@testbench) |vpiTypedef: \_logic_typespec: , line:13:69, endln:13:74 |vpiInstance: - \_module: work@bp_me_nonsynth_lce_tracer2 (work@testbench.lce_tracer2), file:${SURELOG_DIR}/tests/BindStmt/dut.sv, line:40:13, endln:42:31 + \_module_inst: work@bp_me_nonsynth_lce_tracer2 (work@testbench.lce_tracer2), file:${SURELOG_DIR}/tests/BindStmt/dut.sv, line:40:13, endln:42:31 |vpiPort: \_port: (b), line:13:91, endln:13:92 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer2 (work@testbench.lce_tracer2), file:${SURELOG_DIR}/tests/BindStmt/dut.sv, line:40:13, endln:42:31 + \_module_inst: work@bp_me_nonsynth_lce_tracer2 (work@testbench.lce_tracer2), file:${SURELOG_DIR}/tests/BindStmt/dut.sv, line:40:13, endln:42:31 |vpiName:b |vpiDirection:2 |vpiHighConn: @@ -1241,11 +1241,11 @@ design: (work@testbench) |vpiTypedef: \_logic_typespec: , line:13:85, endln:13:90 |vpiInstance: - \_module: work@bp_me_nonsynth_lce_tracer2 (work@testbench.lce_tracer2), file:${SURELOG_DIR}/tests/BindStmt/dut.sv, line:40:13, endln:42:31 + \_module_inst: work@bp_me_nonsynth_lce_tracer2 (work@testbench.lce_tracer2), file:${SURELOG_DIR}/tests/BindStmt/dut.sv, line:40:13, endln:42:31 |vpiPort: \_port: (clk), line:13:106, endln:13:109 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer2 (work@testbench.lce_tracer2), file:${SURELOG_DIR}/tests/BindStmt/dut.sv, line:40:13, endln:42:31 + \_module_inst: work@bp_me_nonsynth_lce_tracer2 (work@testbench.lce_tracer2), file:${SURELOG_DIR}/tests/BindStmt/dut.sv, line:40:13, endln:42:31 |vpiName:clk |vpiDirection:1 |vpiHighConn: @@ -1267,22 +1267,22 @@ design: (work@testbench) |vpiTypedef: \_logic_typespec: , line:13:100, endln:13:105 |vpiInstance: - \_module: work@bp_me_nonsynth_lce_tracer2 (work@testbench.lce_tracer2), file:${SURELOG_DIR}/tests/BindStmt/dut.sv, line:40:13, endln:42:31 - |vpiModule: - \_module: work@sub (work@testbench.lce_tracer2.sub1), file:${SURELOG_DIR}/tests/BindStmt/dut.sv, line:15:3, endln:15:14 + \_module_inst: work@bp_me_nonsynth_lce_tracer2 (work@testbench.lce_tracer2), file:${SURELOG_DIR}/tests/BindStmt/dut.sv, line:40:13, endln:42:31 + |vpiModuleInst: + \_module_inst: work@sub (work@testbench.lce_tracer2.sub1), file:${SURELOG_DIR}/tests/BindStmt/dut.sv, line:15:3, endln:15:14 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer2 (work@testbench.lce_tracer2), file:${SURELOG_DIR}/tests/BindStmt/dut.sv, line:40:13, endln:42:31 + \_module_inst: work@bp_me_nonsynth_lce_tracer2 (work@testbench.lce_tracer2), file:${SURELOG_DIR}/tests/BindStmt/dut.sv, line:40:13, endln:42:31 |vpiName:sub1 |vpiFullName:work@testbench.lce_tracer2.sub1 |vpiDefName:work@sub |vpiDefFile:${SURELOG_DIR}/tests/BindStmt/dut.sv |vpiDefLineNo:5 |vpiInstance: - \_module: work@bp_me_nonsynth_lce_tracer2 (work@testbench.lce_tracer2), file:${SURELOG_DIR}/tests/BindStmt/dut.sv, line:40:13, endln:42:31 + \_module_inst: work@bp_me_nonsynth_lce_tracer2 (work@testbench.lce_tracer2), file:${SURELOG_DIR}/tests/BindStmt/dut.sv, line:40:13, endln:42:31 |vpiContAssign: \_cont_assign: , line:14:10, endln:14:14 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer2 (work@testbench.lce_tracer2), file:${SURELOG_DIR}/tests/BindStmt/dut.sv, line:40:13, endln:42:31 + \_module_inst: work@bp_me_nonsynth_lce_tracer2 (work@testbench.lce_tracer2), file:${SURELOG_DIR}/tests/BindStmt/dut.sv, line:40:13, endln:42:31 |vpiRhs: \_ref_obj: (work@testbench.u1.lce_tracer2.b), line:14:13, endln:14:14 |vpiParent: @@ -1302,7 +1302,7 @@ design: (work@testbench) |vpiContAssign: \_cont_assign: , line:2:8, endln:2:12 |vpiParent: - \_module: work@bp_lce (work@testbench.u1), file:${SURELOG_DIR}/tests/BindStmt/dut.sv, line:27:3, endln:27:30 + \_module_inst: work@bp_lce (work@testbench.u1), file:${SURELOG_DIR}/tests/BindStmt/dut.sv, line:27:3, endln:27:30 |vpiRhs: \_ref_obj: (work@testbench.u1.d), line:2:11, endln:2:12 |vpiParent: @@ -1319,10 +1319,10 @@ design: (work@testbench) |vpiFullName:work@testbench.u1.c |vpiActual: \_logic_net: (c) - |vpiModule: - \_module: work@inter (work@testbench.tt), file:${SURELOG_DIR}/tests/BindStmt/dut.sv, line:28:3, endln:28:15 + |vpiModuleInst: + \_module_inst: work@inter (work@testbench.tt), file:${SURELOG_DIR}/tests/BindStmt/dut.sv, line:28:3, endln:28:15 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BindStmt/dut.sv, line:25:1, endln:52:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BindStmt/dut.sv, line:25:1, endln:52:10 |vpiName:tt |vpiFullName:work@testbench.tt |vpiDefName:work@inter @@ -1331,22 +1331,22 @@ design: (work@testbench) |vpiNet: \_logic_net: (work@testbench.tt.clk) |vpiParent: - \_module: work@inter (work@testbench.tt), file:${SURELOG_DIR}/tests/BindStmt/dut.sv, line:28:3, endln:28:15 + \_module_inst: work@inter (work@testbench.tt), file:${SURELOG_DIR}/tests/BindStmt/dut.sv, line:28:3, endln:28:15 |vpiName:clk |vpiFullName:work@testbench.tt.clk |vpiNetType:1 |vpiInstance: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BindStmt/dut.sv, line:25:1, endln:52:10 - |vpiModule: - \_module: work@bp_lce (work@testbench.tt.u1), file:${SURELOG_DIR}/tests/BindStmt/dut.sv, line:21:2, endln:21:29 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BindStmt/dut.sv, line:25:1, endln:52:10 + |vpiModuleInst: + \_module_inst: work@bp_lce (work@testbench.tt.u1), file:${SURELOG_DIR}/tests/BindStmt/dut.sv, line:21:2, endln:21:29 |vpiParent: - \_module: work@inter (work@testbench.tt), file:${SURELOG_DIR}/tests/BindStmt/dut.sv, line:28:3, endln:28:15 + \_module_inst: work@inter (work@testbench.tt), file:${SURELOG_DIR}/tests/BindStmt/dut.sv, line:28:3, endln:28:15 |vpiName:u1 |vpiFullName:work@testbench.tt.u1 |vpiParameter: \_parameter: (work@testbench.tt.u1.sets_p), line:1:27, endln:1:33 |vpiParent: - \_module: work@bp_lce (work@testbench.tt.u1), file:${SURELOG_DIR}/tests/BindStmt/dut.sv, line:21:2, endln:21:29 + \_module_inst: work@bp_lce (work@testbench.tt.u1), file:${SURELOG_DIR}/tests/BindStmt/dut.sv, line:21:2, endln:21:29 |STRING:inv |vpiTypespec: \_string_typespec: @@ -1357,7 +1357,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:1:27, endln:1:41 |vpiParent: - \_module: work@bp_lce (work@testbench.tt.u1), file:${SURELOG_DIR}/tests/BindStmt/dut.sv, line:21:2, endln:21:29 + \_module_inst: work@bp_lce (work@testbench.tt.u1), file:${SURELOG_DIR}/tests/BindStmt/dut.sv, line:21:2, endln:21:29 |vpiOverriden:1 |vpiRhs: \_constant: , line:1:36, endln:1:41 @@ -1375,7 +1375,7 @@ design: (work@testbench) |vpiNet: \_logic_net: (work@testbench.tt.u1.a), line:1:55, endln:1:56 |vpiParent: - \_module: work@bp_lce (work@testbench.tt.u1), file:${SURELOG_DIR}/tests/BindStmt/dut.sv, line:21:2, endln:21:29 + \_module_inst: work@bp_lce (work@testbench.tt.u1), file:${SURELOG_DIR}/tests/BindStmt/dut.sv, line:21:2, endln:21:29 |vpiTypespec: \_logic_typespec: , line:1:49, endln:1:54 |vpiName:a @@ -1384,18 +1384,18 @@ design: (work@testbench) |vpiNet: \_logic_net: (work@testbench.tt.u1.b), line:1:71, endln:1:72 |vpiParent: - \_module: work@bp_lce (work@testbench.tt.u1), file:${SURELOG_DIR}/tests/BindStmt/dut.sv, line:21:2, endln:21:29 + \_module_inst: work@bp_lce (work@testbench.tt.u1), file:${SURELOG_DIR}/tests/BindStmt/dut.sv, line:21:2, endln:21:29 |vpiTypespec: \_logic_typespec: , line:1:65, endln:1:70 |vpiName:b |vpiFullName:work@testbench.tt.u1.b |vpiNetType:36 |vpiInstance: - \_module: work@inter (work@testbench.tt), file:${SURELOG_DIR}/tests/BindStmt/dut.sv, line:28:3, endln:28:15 + \_module_inst: work@inter (work@testbench.tt), file:${SURELOG_DIR}/tests/BindStmt/dut.sv, line:28:3, endln:28:15 |vpiPort: \_port: (a), line:1:55, endln:1:56 |vpiParent: - \_module: work@bp_lce (work@testbench.tt.u1), file:${SURELOG_DIR}/tests/BindStmt/dut.sv, line:21:2, endln:21:29 + \_module_inst: work@bp_lce (work@testbench.tt.u1), file:${SURELOG_DIR}/tests/BindStmt/dut.sv, line:21:2, endln:21:29 |vpiName:a |vpiDirection:1 |vpiLowConn: @@ -1409,11 +1409,11 @@ design: (work@testbench) |vpiTypedef: \_logic_typespec: , line:1:49, endln:1:54 |vpiInstance: - \_module: work@bp_lce (work@testbench.tt.u1), file:${SURELOG_DIR}/tests/BindStmt/dut.sv, line:21:2, endln:21:29 + \_module_inst: work@bp_lce (work@testbench.tt.u1), file:${SURELOG_DIR}/tests/BindStmt/dut.sv, line:21:2, endln:21:29 |vpiPort: \_port: (b), line:1:71, endln:1:72 |vpiParent: - \_module: work@bp_lce (work@testbench.tt.u1), file:${SURELOG_DIR}/tests/BindStmt/dut.sv, line:21:2, endln:21:29 + \_module_inst: work@bp_lce (work@testbench.tt.u1), file:${SURELOG_DIR}/tests/BindStmt/dut.sv, line:21:2, endln:21:29 |vpiName:b |vpiDirection:2 |vpiLowConn: @@ -1427,17 +1427,17 @@ design: (work@testbench) |vpiTypedef: \_logic_typespec: , line:1:65, endln:1:70 |vpiInstance: - \_module: work@bp_lce (work@testbench.tt.u1), file:${SURELOG_DIR}/tests/BindStmt/dut.sv, line:21:2, endln:21:29 - |vpiModule: - \_module: work@bp_me_nonsynth_lce_tracer (work@testbench.tt.lce_tracer1), file:${SURELOG_DIR}/tests/BindStmt/dut.sv, line:34:13, endln:36:41 + \_module_inst: work@bp_lce (work@testbench.tt.u1), file:${SURELOG_DIR}/tests/BindStmt/dut.sv, line:21:2, endln:21:29 + |vpiModuleInst: + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@testbench.tt.lce_tracer1), file:${SURELOG_DIR}/tests/BindStmt/dut.sv, line:34:13, endln:36:41 |vpiParent: - \_module: work@bp_lce (work@testbench.tt.u1), file:${SURELOG_DIR}/tests/BindStmt/dut.sv, line:21:2, endln:21:29 + \_module_inst: work@bp_lce (work@testbench.tt.u1), file:${SURELOG_DIR}/tests/BindStmt/dut.sv, line:21:2, endln:21:29 |vpiName:lce_tracer1 |vpiFullName:work@testbench.tt.lce_tracer1 |vpiParameter: \_parameter: (work@testbench.tt.u1.lce_tracer1.sets_p), line:8:46, endln:8:52 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@testbench.tt.lce_tracer1), file:${SURELOG_DIR}/tests/BindStmt/dut.sv, line:34:13, endln:36:41 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@testbench.tt.lce_tracer1), file:${SURELOG_DIR}/tests/BindStmt/dut.sv, line:34:13, endln:36:41 |STRING:inv |vpiTypespec: \_string_typespec: @@ -1448,7 +1448,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:8:46, endln:8:60 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@testbench.tt.lce_tracer1), file:${SURELOG_DIR}/tests/BindStmt/dut.sv, line:34:13, endln:36:41 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@testbench.tt.lce_tracer1), file:${SURELOG_DIR}/tests/BindStmt/dut.sv, line:34:13, endln:36:41 |vpiOverriden:1 |vpiRhs: \_constant: , line:8:55, endln:8:60 @@ -1466,7 +1466,7 @@ design: (work@testbench) |vpiNet: \_logic_net: (work@testbench.tt.u1.lce_tracer1.c), line:8:74, endln:8:75 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@testbench.tt.lce_tracer1), file:${SURELOG_DIR}/tests/BindStmt/dut.sv, line:34:13, endln:36:41 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@testbench.tt.lce_tracer1), file:${SURELOG_DIR}/tests/BindStmt/dut.sv, line:34:13, endln:36:41 |vpiTypespec: \_logic_typespec: , line:8:68, endln:8:73 |vpiName:c @@ -1475,18 +1475,18 @@ design: (work@testbench) |vpiNet: \_logic_net: (work@testbench.tt.u1.lce_tracer1.d), line:8:90, endln:8:91 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@testbench.tt.lce_tracer1), file:${SURELOG_DIR}/tests/BindStmt/dut.sv, line:34:13, endln:36:41 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@testbench.tt.lce_tracer1), file:${SURELOG_DIR}/tests/BindStmt/dut.sv, line:34:13, endln:36:41 |vpiTypespec: \_logic_typespec: , line:8:84, endln:8:89 |vpiName:d |vpiFullName:work@testbench.tt.u1.lce_tracer1.d |vpiNetType:36 |vpiInstance: - \_module: work@bp_lce (work@testbench.tt.u1), file:${SURELOG_DIR}/tests/BindStmt/dut.sv, line:21:2, endln:21:29 + \_module_inst: work@bp_lce (work@testbench.tt.u1), file:${SURELOG_DIR}/tests/BindStmt/dut.sv, line:21:2, endln:21:29 |vpiPort: \_port: (c), line:8:74, endln:8:75 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@testbench.tt.lce_tracer1), file:${SURELOG_DIR}/tests/BindStmt/dut.sv, line:34:13, endln:36:41 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@testbench.tt.lce_tracer1), file:${SURELOG_DIR}/tests/BindStmt/dut.sv, line:34:13, endln:36:41 |vpiName:c |vpiDirection:1 |vpiHighConn: @@ -1508,11 +1508,11 @@ design: (work@testbench) |vpiTypedef: \_logic_typespec: , line:8:68, endln:8:73 |vpiInstance: - \_module: work@bp_me_nonsynth_lce_tracer (work@testbench.tt.lce_tracer1), file:${SURELOG_DIR}/tests/BindStmt/dut.sv, line:34:13, endln:36:41 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@testbench.tt.lce_tracer1), file:${SURELOG_DIR}/tests/BindStmt/dut.sv, line:34:13, endln:36:41 |vpiPort: \_port: (d), line:8:90, endln:8:91 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@testbench.tt.lce_tracer1), file:${SURELOG_DIR}/tests/BindStmt/dut.sv, line:34:13, endln:36:41 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@testbench.tt.lce_tracer1), file:${SURELOG_DIR}/tests/BindStmt/dut.sv, line:34:13, endln:36:41 |vpiName:d |vpiDirection:2 |vpiHighConn: @@ -1534,22 +1534,22 @@ design: (work@testbench) |vpiTypedef: \_logic_typespec: , line:8:84, endln:8:89 |vpiInstance: - \_module: work@bp_me_nonsynth_lce_tracer (work@testbench.tt.lce_tracer1), file:${SURELOG_DIR}/tests/BindStmt/dut.sv, line:34:13, endln:36:41 - |vpiModule: - \_module: work@sub (work@testbench.tt.lce_tracer1.sub1), file:${SURELOG_DIR}/tests/BindStmt/dut.sv, line:10:3, endln:10:14 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@testbench.tt.lce_tracer1), file:${SURELOG_DIR}/tests/BindStmt/dut.sv, line:34:13, endln:36:41 + |vpiModuleInst: + \_module_inst: work@sub (work@testbench.tt.lce_tracer1.sub1), file:${SURELOG_DIR}/tests/BindStmt/dut.sv, line:10:3, endln:10:14 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@testbench.tt.lce_tracer1), file:${SURELOG_DIR}/tests/BindStmt/dut.sv, line:34:13, endln:36:41 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@testbench.tt.lce_tracer1), file:${SURELOG_DIR}/tests/BindStmt/dut.sv, line:34:13, endln:36:41 |vpiName:sub1 |vpiFullName:work@testbench.tt.lce_tracer1.sub1 |vpiDefName:work@sub |vpiDefFile:${SURELOG_DIR}/tests/BindStmt/dut.sv |vpiDefLineNo:5 |vpiInstance: - \_module: work@bp_me_nonsynth_lce_tracer (work@testbench.tt.lce_tracer1), file:${SURELOG_DIR}/tests/BindStmt/dut.sv, line:34:13, endln:36:41 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@testbench.tt.lce_tracer1), file:${SURELOG_DIR}/tests/BindStmt/dut.sv, line:34:13, endln:36:41 |vpiContAssign: \_cont_assign: , line:9:10, endln:9:14 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@testbench.tt.lce_tracer1), file:${SURELOG_DIR}/tests/BindStmt/dut.sv, line:34:13, endln:36:41 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@testbench.tt.lce_tracer1), file:${SURELOG_DIR}/tests/BindStmt/dut.sv, line:34:13, endln:36:41 |vpiRhs: \_ref_obj: (work@testbench.tt.u1.lce_tracer1.b), line:9:13, endln:9:14 |vpiParent: @@ -1566,16 +1566,16 @@ design: (work@testbench) |vpiFullName:work@testbench.tt.u1.lce_tracer1.a |vpiActual: \_logic_net: (work@testbench.tt.u1.a), line:1:55, endln:1:56 - |vpiModule: - \_module: work@bp_me_nonsynth_lce_tracer2 (work@testbench.tt.lce_tracer2), file:${SURELOG_DIR}/tests/BindStmt/dut.sv, line:40:13, endln:42:31 + |vpiModuleInst: + \_module_inst: work@bp_me_nonsynth_lce_tracer2 (work@testbench.tt.lce_tracer2), file:${SURELOG_DIR}/tests/BindStmt/dut.sv, line:40:13, endln:42:31 |vpiParent: - \_module: work@bp_lce (work@testbench.tt.u1), file:${SURELOG_DIR}/tests/BindStmt/dut.sv, line:21:2, endln:21:29 + \_module_inst: work@bp_lce (work@testbench.tt.u1), file:${SURELOG_DIR}/tests/BindStmt/dut.sv, line:21:2, endln:21:29 |vpiName:lce_tracer2 |vpiFullName:work@testbench.tt.lce_tracer2 |vpiParameter: \_parameter: (work@testbench.tt.u1.lce_tracer2.sets_p), line:13:47, endln:13:53 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer2 (work@testbench.tt.lce_tracer2), file:${SURELOG_DIR}/tests/BindStmt/dut.sv, line:40:13, endln:42:31 + \_module_inst: work@bp_me_nonsynth_lce_tracer2 (work@testbench.tt.lce_tracer2), file:${SURELOG_DIR}/tests/BindStmt/dut.sv, line:40:13, endln:42:31 |STRING:inv |vpiTypespec: \_string_typespec: @@ -1586,7 +1586,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:13:47, endln:13:61 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer2 (work@testbench.tt.lce_tracer2), file:${SURELOG_DIR}/tests/BindStmt/dut.sv, line:40:13, endln:42:31 + \_module_inst: work@bp_me_nonsynth_lce_tracer2 (work@testbench.tt.lce_tracer2), file:${SURELOG_DIR}/tests/BindStmt/dut.sv, line:40:13, endln:42:31 |vpiOverriden:1 |vpiRhs: \_constant: , line:13:56, endln:13:61 @@ -1604,7 +1604,7 @@ design: (work@testbench) |vpiNet: \_logic_net: (work@testbench.tt.u1.lce_tracer2.a), line:13:75, endln:13:76 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer2 (work@testbench.tt.lce_tracer2), file:${SURELOG_DIR}/tests/BindStmt/dut.sv, line:40:13, endln:42:31 + \_module_inst: work@bp_me_nonsynth_lce_tracer2 (work@testbench.tt.lce_tracer2), file:${SURELOG_DIR}/tests/BindStmt/dut.sv, line:40:13, endln:42:31 |vpiTypespec: \_logic_typespec: , line:13:69, endln:13:74 |vpiName:a @@ -1613,7 +1613,7 @@ design: (work@testbench) |vpiNet: \_logic_net: (work@testbench.tt.u1.lce_tracer2.b), line:13:91, endln:13:92 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer2 (work@testbench.tt.lce_tracer2), file:${SURELOG_DIR}/tests/BindStmt/dut.sv, line:40:13, endln:42:31 + \_module_inst: work@bp_me_nonsynth_lce_tracer2 (work@testbench.tt.lce_tracer2), file:${SURELOG_DIR}/tests/BindStmt/dut.sv, line:40:13, endln:42:31 |vpiTypespec: \_logic_typespec: , line:13:85, endln:13:90 |vpiName:b @@ -1622,18 +1622,18 @@ design: (work@testbench) |vpiNet: \_logic_net: (work@testbench.tt.u1.lce_tracer2.clk), line:13:106, endln:13:109 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer2 (work@testbench.tt.lce_tracer2), file:${SURELOG_DIR}/tests/BindStmt/dut.sv, line:40:13, endln:42:31 + \_module_inst: work@bp_me_nonsynth_lce_tracer2 (work@testbench.tt.lce_tracer2), file:${SURELOG_DIR}/tests/BindStmt/dut.sv, line:40:13, endln:42:31 |vpiTypespec: \_logic_typespec: , line:13:100, endln:13:105 |vpiName:clk |vpiFullName:work@testbench.tt.u1.lce_tracer2.clk |vpiNetType:36 |vpiInstance: - \_module: work@bp_lce (work@testbench.tt.u1), file:${SURELOG_DIR}/tests/BindStmt/dut.sv, line:21:2, endln:21:29 + \_module_inst: work@bp_lce (work@testbench.tt.u1), file:${SURELOG_DIR}/tests/BindStmt/dut.sv, line:21:2, endln:21:29 |vpiPort: \_port: (a), line:13:75, endln:13:76 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer2 (work@testbench.tt.lce_tracer2), file:${SURELOG_DIR}/tests/BindStmt/dut.sv, line:40:13, endln:42:31 + \_module_inst: work@bp_me_nonsynth_lce_tracer2 (work@testbench.tt.lce_tracer2), file:${SURELOG_DIR}/tests/BindStmt/dut.sv, line:40:13, endln:42:31 |vpiName:a |vpiDirection:1 |vpiHighConn: @@ -1655,11 +1655,11 @@ design: (work@testbench) |vpiTypedef: \_logic_typespec: , line:13:69, endln:13:74 |vpiInstance: - \_module: work@bp_me_nonsynth_lce_tracer2 (work@testbench.tt.lce_tracer2), file:${SURELOG_DIR}/tests/BindStmt/dut.sv, line:40:13, endln:42:31 + \_module_inst: work@bp_me_nonsynth_lce_tracer2 (work@testbench.tt.lce_tracer2), file:${SURELOG_DIR}/tests/BindStmt/dut.sv, line:40:13, endln:42:31 |vpiPort: \_port: (b), line:13:91, endln:13:92 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer2 (work@testbench.tt.lce_tracer2), file:${SURELOG_DIR}/tests/BindStmt/dut.sv, line:40:13, endln:42:31 + \_module_inst: work@bp_me_nonsynth_lce_tracer2 (work@testbench.tt.lce_tracer2), file:${SURELOG_DIR}/tests/BindStmt/dut.sv, line:40:13, endln:42:31 |vpiName:b |vpiDirection:2 |vpiHighConn: @@ -1681,11 +1681,11 @@ design: (work@testbench) |vpiTypedef: \_logic_typespec: , line:13:85, endln:13:90 |vpiInstance: - \_module: work@bp_me_nonsynth_lce_tracer2 (work@testbench.tt.lce_tracer2), file:${SURELOG_DIR}/tests/BindStmt/dut.sv, line:40:13, endln:42:31 + \_module_inst: work@bp_me_nonsynth_lce_tracer2 (work@testbench.tt.lce_tracer2), file:${SURELOG_DIR}/tests/BindStmt/dut.sv, line:40:13, endln:42:31 |vpiPort: \_port: (clk), line:13:106, endln:13:109 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer2 (work@testbench.tt.lce_tracer2), file:${SURELOG_DIR}/tests/BindStmt/dut.sv, line:40:13, endln:42:31 + \_module_inst: work@bp_me_nonsynth_lce_tracer2 (work@testbench.tt.lce_tracer2), file:${SURELOG_DIR}/tests/BindStmt/dut.sv, line:40:13, endln:42:31 |vpiName:clk |vpiDirection:1 |vpiHighConn: @@ -1707,22 +1707,22 @@ design: (work@testbench) |vpiTypedef: \_logic_typespec: , line:13:100, endln:13:105 |vpiInstance: - \_module: work@bp_me_nonsynth_lce_tracer2 (work@testbench.tt.lce_tracer2), file:${SURELOG_DIR}/tests/BindStmt/dut.sv, line:40:13, endln:42:31 - |vpiModule: - \_module: work@sub (work@testbench.tt.lce_tracer2.sub1), file:${SURELOG_DIR}/tests/BindStmt/dut.sv, line:15:3, endln:15:14 + \_module_inst: work@bp_me_nonsynth_lce_tracer2 (work@testbench.tt.lce_tracer2), file:${SURELOG_DIR}/tests/BindStmt/dut.sv, line:40:13, endln:42:31 + |vpiModuleInst: + \_module_inst: work@sub (work@testbench.tt.lce_tracer2.sub1), file:${SURELOG_DIR}/tests/BindStmt/dut.sv, line:15:3, endln:15:14 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer2 (work@testbench.tt.lce_tracer2), file:${SURELOG_DIR}/tests/BindStmt/dut.sv, line:40:13, endln:42:31 + \_module_inst: work@bp_me_nonsynth_lce_tracer2 (work@testbench.tt.lce_tracer2), file:${SURELOG_DIR}/tests/BindStmt/dut.sv, line:40:13, endln:42:31 |vpiName:sub1 |vpiFullName:work@testbench.tt.lce_tracer2.sub1 |vpiDefName:work@sub |vpiDefFile:${SURELOG_DIR}/tests/BindStmt/dut.sv |vpiDefLineNo:5 |vpiInstance: - \_module: work@bp_me_nonsynth_lce_tracer2 (work@testbench.tt.lce_tracer2), file:${SURELOG_DIR}/tests/BindStmt/dut.sv, line:40:13, endln:42:31 + \_module_inst: work@bp_me_nonsynth_lce_tracer2 (work@testbench.tt.lce_tracer2), file:${SURELOG_DIR}/tests/BindStmt/dut.sv, line:40:13, endln:42:31 |vpiContAssign: \_cont_assign: , line:14:10, endln:14:14 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer2 (work@testbench.tt.lce_tracer2), file:${SURELOG_DIR}/tests/BindStmt/dut.sv, line:40:13, endln:42:31 + \_module_inst: work@bp_me_nonsynth_lce_tracer2 (work@testbench.tt.lce_tracer2), file:${SURELOG_DIR}/tests/BindStmt/dut.sv, line:40:13, endln:42:31 |vpiRhs: \_ref_obj: (work@testbench.tt.u1.lce_tracer2.b), line:14:13, endln:14:14 |vpiParent: @@ -1742,7 +1742,7 @@ design: (work@testbench) |vpiContAssign: \_cont_assign: , line:2:8, endln:2:12 |vpiParent: - \_module: work@bp_lce (work@testbench.tt.u1), file:${SURELOG_DIR}/tests/BindStmt/dut.sv, line:21:2, endln:21:29 + \_module_inst: work@bp_lce (work@testbench.tt.u1), file:${SURELOG_DIR}/tests/BindStmt/dut.sv, line:21:2, endln:21:29 |vpiRhs: \_ref_obj: (work@testbench.tt.u1.d), line:2:11, endln:2:12 |vpiParent: @@ -1762,7 +1762,7 @@ design: (work@testbench) |vpiGenScopeArray: \_gen_scope_array: (work@testbench.do_bind), line:31:3, endln:49:6 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BindStmt/dut.sv, line:25:1, endln:52:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BindStmt/dut.sv, line:25:1, endln:52:10 |vpiName:do_bind |vpiFullName:work@testbench.do_bind |vpiGenScope: diff --git a/tests/BindStmt2/BindStmt2.log b/tests/BindStmt2/BindStmt2.log index ea0d333588..8a031a4f6c 100644 --- a/tests/BindStmt2/BindStmt2.log +++ b/tests/BindStmt2/BindStmt2.log @@ -601,7 +601,7 @@ int_typespec 10 logic_net 40 logic_typespec 26 logic_var 14 -module 11 +module_inst 11 operation 8 param_assign 8 parameter 8 @@ -623,7 +623,7 @@ int_typespec 10 logic_net 40 logic_typespec 26 logic_var 14 -module 11 +module_inst 11 operation 8 param_assign 8 parameter 8 @@ -656,14 +656,14 @@ design: (work@rv_dm) |vpiElaborated:1 |vpiName:work@rv_dm |uhdmallModules: -\_module: work@dmidpi (work@dmidpi), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:36:1, endln:54:10 +\_module_inst: work@dmidpi (work@dmidpi), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:36:1, endln:54:10 |vpiParent: \_design: (work@rv_dm) |vpiFullName:work@dmidpi |vpiParameter: \_parameter: (work@dmidpi.Name), line:37:20, endln:37:24 |vpiParent: - \_module: work@dmidpi (work@dmidpi), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:36:1, endln:54:10 + \_module_inst: work@dmidpi (work@dmidpi), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:36:1, endln:54:10 |STRING:dmi0 |vpiTypespec: \_string_typespec: , line:37:13, endln:37:19 @@ -674,7 +674,7 @@ design: (work@rv_dm) |vpiParameter: \_parameter: (work@dmidpi.ListenPort), line:38:17, endln:38:27 |vpiParent: - \_module: work@dmidpi (work@dmidpi), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:36:1, endln:54:10 + \_module_inst: work@dmidpi (work@dmidpi), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:36:1, endln:54:10 |UINT:44853 |vpiTypespec: \_int_typespec: , line:38:13, endln:38:16 @@ -687,7 +687,7 @@ design: (work@rv_dm) |vpiParamAssign: \_param_assign: , line:37:20, endln:37:33 |vpiParent: - \_module: work@dmidpi (work@dmidpi), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:36:1, endln:54:10 + \_module_inst: work@dmidpi (work@dmidpi), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:36:1, endln:54:10 |vpiRhs: \_constant: , line:37:27, endln:37:33 |vpiDecompile:dmi0 @@ -701,7 +701,7 @@ design: (work@rv_dm) |vpiParamAssign: \_param_assign: , line:38:17, endln:38:35 |vpiParent: - \_module: work@dmidpi (work@dmidpi), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:36:1, endln:54:10 + \_module_inst: work@dmidpi (work@dmidpi), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:36:1, endln:54:10 |vpiRhs: \_constant: , line:38:30, endln:38:35 |vpiDecompile:44853 @@ -716,79 +716,79 @@ design: (work@rv_dm) |vpiNet: \_logic_net: (work@dmidpi.clk_i), line:40:21, endln:40:26 |vpiParent: - \_module: work@dmidpi (work@dmidpi), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:36:1, endln:54:10 + \_module_inst: work@dmidpi (work@dmidpi), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:36:1, endln:54:10 |vpiName:clk_i |vpiFullName:work@dmidpi.clk_i |vpiNet: \_logic_net: (work@dmidpi.rst_ni), line:41:21, endln:41:27 |vpiParent: - \_module: work@dmidpi (work@dmidpi), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:36:1, endln:54:10 + \_module_inst: work@dmidpi (work@dmidpi), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:36:1, endln:54:10 |vpiName:rst_ni |vpiFullName:work@dmidpi.rst_ni |vpiNet: \_logic_net: (work@dmidpi.dmi_req_valid), line:43:21, endln:43:34 |vpiParent: - \_module: work@dmidpi (work@dmidpi), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:36:1, endln:54:10 + \_module_inst: work@dmidpi (work@dmidpi), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:36:1, endln:54:10 |vpiName:dmi_req_valid |vpiFullName:work@dmidpi.dmi_req_valid |vpiNet: \_logic_net: (work@dmidpi.dmi_req_ready), line:44:21, endln:44:34 |vpiParent: - \_module: work@dmidpi (work@dmidpi), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:36:1, endln:54:10 + \_module_inst: work@dmidpi (work@dmidpi), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:36:1, endln:54:10 |vpiName:dmi_req_ready |vpiFullName:work@dmidpi.dmi_req_ready |vpiNet: \_logic_net: (work@dmidpi.dmi_req_addr), line:45:21, endln:45:33 |vpiParent: - \_module: work@dmidpi (work@dmidpi), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:36:1, endln:54:10 + \_module_inst: work@dmidpi (work@dmidpi), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:36:1, endln:54:10 |vpiName:dmi_req_addr |vpiFullName:work@dmidpi.dmi_req_addr |vpiNet: \_logic_net: (work@dmidpi.dmi_req_op), line:46:21, endln:46:31 |vpiParent: - \_module: work@dmidpi (work@dmidpi), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:36:1, endln:54:10 + \_module_inst: work@dmidpi (work@dmidpi), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:36:1, endln:54:10 |vpiName:dmi_req_op |vpiFullName:work@dmidpi.dmi_req_op |vpiNet: \_logic_net: (work@dmidpi.dmi_req_data), line:47:21, endln:47:33 |vpiParent: - \_module: work@dmidpi (work@dmidpi), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:36:1, endln:54:10 + \_module_inst: work@dmidpi (work@dmidpi), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:36:1, endln:54:10 |vpiName:dmi_req_data |vpiFullName:work@dmidpi.dmi_req_data |vpiNet: \_logic_net: (work@dmidpi.dmi_rsp_valid), line:48:21, endln:48:34 |vpiParent: - \_module: work@dmidpi (work@dmidpi), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:36:1, endln:54:10 + \_module_inst: work@dmidpi (work@dmidpi), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:36:1, endln:54:10 |vpiName:dmi_rsp_valid |vpiFullName:work@dmidpi.dmi_rsp_valid |vpiNet: \_logic_net: (work@dmidpi.dmi_rsp_ready), line:49:21, endln:49:34 |vpiParent: - \_module: work@dmidpi (work@dmidpi), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:36:1, endln:54:10 + \_module_inst: work@dmidpi (work@dmidpi), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:36:1, endln:54:10 |vpiName:dmi_rsp_ready |vpiFullName:work@dmidpi.dmi_rsp_ready |vpiNet: \_logic_net: (work@dmidpi.dmi_rsp_data), line:50:21, endln:50:33 |vpiParent: - \_module: work@dmidpi (work@dmidpi), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:36:1, endln:54:10 + \_module_inst: work@dmidpi (work@dmidpi), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:36:1, endln:54:10 |vpiName:dmi_rsp_data |vpiFullName:work@dmidpi.dmi_rsp_data |vpiNet: \_logic_net: (work@dmidpi.dmi_rsp_resp), line:51:21, endln:51:33 |vpiParent: - \_module: work@dmidpi (work@dmidpi), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:36:1, endln:54:10 + \_module_inst: work@dmidpi (work@dmidpi), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:36:1, endln:54:10 |vpiName:dmi_rsp_resp |vpiFullName:work@dmidpi.dmi_rsp_resp |vpiNet: \_logic_net: (work@dmidpi.dmi_rst_n), line:52:21, endln:52:30 |vpiParent: - \_module: work@dmidpi (work@dmidpi), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:36:1, endln:54:10 + \_module_inst: work@dmidpi (work@dmidpi), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:36:1, endln:54:10 |vpiName:dmi_rst_n |vpiFullName:work@dmidpi.dmi_rst_n |vpiPort: \_port: (clk_i), line:40:21, endln:40:26 |vpiParent: - \_module: work@dmidpi (work@dmidpi), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:36:1, endln:54:10 + \_module_inst: work@dmidpi (work@dmidpi), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:36:1, endln:54:10 |vpiName:clk_i |vpiDirection:1 |vpiLowConn: @@ -801,7 +801,7 @@ design: (work@rv_dm) |vpiPort: \_port: (rst_ni), line:41:21, endln:41:27 |vpiParent: - \_module: work@dmidpi (work@dmidpi), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:36:1, endln:54:10 + \_module_inst: work@dmidpi (work@dmidpi), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:36:1, endln:54:10 |vpiName:rst_ni |vpiDirection:1 |vpiLowConn: @@ -814,7 +814,7 @@ design: (work@rv_dm) |vpiPort: \_port: (dmi_req_valid), line:43:21, endln:43:34 |vpiParent: - \_module: work@dmidpi (work@dmidpi), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:36:1, endln:54:10 + \_module_inst: work@dmidpi (work@dmidpi), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:36:1, endln:54:10 |vpiName:dmi_req_valid |vpiDirection:2 |vpiLowConn: @@ -827,7 +827,7 @@ design: (work@rv_dm) |vpiPort: \_port: (dmi_req_ready), line:44:21, endln:44:34 |vpiParent: - \_module: work@dmidpi (work@dmidpi), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:36:1, endln:54:10 + \_module_inst: work@dmidpi (work@dmidpi), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:36:1, endln:54:10 |vpiName:dmi_req_ready |vpiDirection:1 |vpiLowConn: @@ -840,7 +840,7 @@ design: (work@rv_dm) |vpiPort: \_port: (dmi_req_addr), line:45:21, endln:45:33 |vpiParent: - \_module: work@dmidpi (work@dmidpi), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:36:1, endln:54:10 + \_module_inst: work@dmidpi (work@dmidpi), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:36:1, endln:54:10 |vpiName:dmi_req_addr |vpiDirection:2 |vpiLowConn: @@ -871,7 +871,7 @@ design: (work@rv_dm) |vpiPort: \_port: (dmi_req_op), line:46:21, endln:46:31 |vpiParent: - \_module: work@dmidpi (work@dmidpi), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:36:1, endln:54:10 + \_module_inst: work@dmidpi (work@dmidpi), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:36:1, endln:54:10 |vpiName:dmi_req_op |vpiDirection:2 |vpiLowConn: @@ -902,7 +902,7 @@ design: (work@rv_dm) |vpiPort: \_port: (dmi_req_data), line:47:21, endln:47:33 |vpiParent: - \_module: work@dmidpi (work@dmidpi), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:36:1, endln:54:10 + \_module_inst: work@dmidpi (work@dmidpi), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:36:1, endln:54:10 |vpiName:dmi_req_data |vpiDirection:2 |vpiLowConn: @@ -933,7 +933,7 @@ design: (work@rv_dm) |vpiPort: \_port: (dmi_rsp_valid), line:48:21, endln:48:34 |vpiParent: - \_module: work@dmidpi (work@dmidpi), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:36:1, endln:54:10 + \_module_inst: work@dmidpi (work@dmidpi), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:36:1, endln:54:10 |vpiName:dmi_rsp_valid |vpiDirection:1 |vpiLowConn: @@ -946,7 +946,7 @@ design: (work@rv_dm) |vpiPort: \_port: (dmi_rsp_ready), line:49:21, endln:49:34 |vpiParent: - \_module: work@dmidpi (work@dmidpi), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:36:1, endln:54:10 + \_module_inst: work@dmidpi (work@dmidpi), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:36:1, endln:54:10 |vpiName:dmi_rsp_ready |vpiDirection:2 |vpiLowConn: @@ -959,7 +959,7 @@ design: (work@rv_dm) |vpiPort: \_port: (dmi_rsp_data), line:50:21, endln:50:33 |vpiParent: - \_module: work@dmidpi (work@dmidpi), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:36:1, endln:54:10 + \_module_inst: work@dmidpi (work@dmidpi), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:36:1, endln:54:10 |vpiName:dmi_rsp_data |vpiDirection:1 |vpiLowConn: @@ -990,7 +990,7 @@ design: (work@rv_dm) |vpiPort: \_port: (dmi_rsp_resp), line:51:21, endln:51:33 |vpiParent: - \_module: work@dmidpi (work@dmidpi), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:36:1, endln:54:10 + \_module_inst: work@dmidpi (work@dmidpi), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:36:1, endln:54:10 |vpiName:dmi_rsp_resp |vpiDirection:1 |vpiLowConn: @@ -1021,7 +1021,7 @@ design: (work@rv_dm) |vpiPort: \_port: (dmi_rst_n), line:52:21, endln:52:30 |vpiParent: - \_module: work@dmidpi (work@dmidpi), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:36:1, endln:54:10 + \_module_inst: work@dmidpi (work@dmidpi), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:36:1, endln:54:10 |vpiName:dmi_rst_n |vpiDirection:2 |vpiLowConn: @@ -1032,14 +1032,14 @@ design: (work@rv_dm) \_bit_typespec: , line:52:10, endln:52:13 |vpiSigned:1 |uhdmallModules: -\_module: work@rv_dm (work@rv_dm), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:1:1, endln:34:10 +\_module_inst: work@rv_dm (work@rv_dm), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:1:1, endln:34:10 |vpiParent: \_design: (work@rv_dm) |vpiFullName:work@rv_dm |vpiParameter: \_parameter: (work@rv_dm.NrHarts), line:2:30, endln:2:37 |vpiParent: - \_module: work@rv_dm (work@rv_dm), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:1:1, endln:34:10 + \_module_inst: work@rv_dm (work@rv_dm), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:1:1, endln:34:10 |UINT:1 |vpiTypespec: \_int_typespec: , line:2:13, endln:2:16 @@ -1052,7 +1052,7 @@ design: (work@rv_dm) |vpiParameter: \_parameter: (work@rv_dm.IdcodeValue), line:3:30, endln:3:41 |vpiParent: - \_module: work@rv_dm (work@rv_dm), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:1:1, endln:34:10 + \_module_inst: work@rv_dm (work@rv_dm), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:1:1, endln:34:10 |HEX:00000001 |vpiTypespec: \_logic_typespec: , line:3:13, endln:3:25 @@ -1081,7 +1081,7 @@ design: (work@rv_dm) |vpiParamAssign: \_param_assign: , line:2:30, endln:2:41 |vpiParent: - \_module: work@rv_dm (work@rv_dm), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:1:1, endln:34:10 + \_module_inst: work@rv_dm (work@rv_dm), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:1:1, endln:34:10 |vpiRhs: \_constant: , line:2:40, endln:2:41 |vpiDecompile:1 @@ -1095,7 +1095,7 @@ design: (work@rv_dm) |vpiParamAssign: \_param_assign: , line:3:30, endln:3:57 |vpiParent: - \_module: work@rv_dm (work@rv_dm), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:1:1, endln:34:10 + \_module_inst: work@rv_dm (work@rv_dm), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:1:1, endln:34:10 |vpiRhs: \_constant: , line:3:44, endln:3:57 |vpiDecompile:32'h0000_0001 @@ -1110,145 +1110,145 @@ design: (work@rv_dm) |vpiNet: \_logic_net: (work@rv_dm.clk_i), line:5:30, endln:5:35 |vpiParent: - \_module: work@rv_dm (work@rv_dm), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:1:1, endln:34:10 + \_module_inst: work@rv_dm (work@rv_dm), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:1:1, endln:34:10 |vpiName:clk_i |vpiFullName:work@rv_dm.clk_i |vpiNetType:36 |vpiNet: \_logic_net: (work@rv_dm.rst_ni), line:6:30, endln:6:36 |vpiParent: - \_module: work@rv_dm (work@rv_dm), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:1:1, endln:34:10 + \_module_inst: work@rv_dm (work@rv_dm), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:1:1, endln:34:10 |vpiName:rst_ni |vpiFullName:work@rv_dm.rst_ni |vpiNetType:36 |vpiNet: \_logic_net: (work@rv_dm.hw_debug_en_i), line:8:31, endln:8:44 |vpiParent: - \_module: work@rv_dm (work@rv_dm), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:1:1, endln:34:10 + \_module_inst: work@rv_dm (work@rv_dm), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:1:1, endln:34:10 |vpiName:hw_debug_en_i |vpiFullName:work@rv_dm.hw_debug_en_i |vpiNet: \_logic_net: (work@rv_dm.testmode_i), line:9:30, endln:9:40 |vpiParent: - \_module: work@rv_dm (work@rv_dm), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:1:1, endln:34:10 + \_module_inst: work@rv_dm (work@rv_dm), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:1:1, endln:34:10 |vpiName:testmode_i |vpiFullName:work@rv_dm.testmode_i |vpiNetType:36 |vpiNet: \_logic_net: (work@rv_dm.ndmreset_o), line:10:30, endln:10:40 |vpiParent: - \_module: work@rv_dm (work@rv_dm), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:1:1, endln:34:10 + \_module_inst: work@rv_dm (work@rv_dm), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:1:1, endln:34:10 |vpiName:ndmreset_o |vpiFullName:work@rv_dm.ndmreset_o |vpiNetType:36 |vpiNet: \_logic_net: (work@rv_dm.dmactive_o), line:11:30, endln:11:40 |vpiParent: - \_module: work@rv_dm (work@rv_dm), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:1:1, endln:34:10 + \_module_inst: work@rv_dm (work@rv_dm), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:1:1, endln:34:10 |vpiName:dmactive_o |vpiFullName:work@rv_dm.dmactive_o |vpiNetType:36 |vpiNet: \_logic_net: (work@rv_dm.debug_req_o), line:12:30, endln:12:41 |vpiParent: - \_module: work@rv_dm (work@rv_dm), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:1:1, endln:34:10 + \_module_inst: work@rv_dm (work@rv_dm), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:1:1, endln:34:10 |vpiName:debug_req_o |vpiFullName:work@rv_dm.debug_req_o |vpiNetType:36 |vpiNet: \_logic_net: (work@rv_dm.unavailable_i), line:13:30, endln:13:43 |vpiParent: - \_module: work@rv_dm (work@rv_dm), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:1:1, endln:34:10 + \_module_inst: work@rv_dm (work@rv_dm), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:1:1, endln:34:10 |vpiName:unavailable_i |vpiFullName:work@rv_dm.unavailable_i |vpiNetType:36 |vpiNet: \_logic_net: (work@rv_dm.tl_d_i), line:17:30, endln:17:36 |vpiParent: - \_module: work@rv_dm (work@rv_dm), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:1:1, endln:34:10 + \_module_inst: work@rv_dm (work@rv_dm), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:1:1, endln:34:10 |vpiName:tl_d_i |vpiFullName:work@rv_dm.tl_d_i |vpiNet: \_logic_net: (work@rv_dm.tl_d_o), line:18:30, endln:18:36 |vpiParent: - \_module: work@rv_dm (work@rv_dm), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:1:1, endln:34:10 + \_module_inst: work@rv_dm (work@rv_dm), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:1:1, endln:34:10 |vpiName:tl_d_o |vpiFullName:work@rv_dm.tl_d_o |vpiNet: \_logic_net: (work@rv_dm.tl_h_o), line:21:30, endln:21:36 |vpiParent: - \_module: work@rv_dm (work@rv_dm), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:1:1, endln:34:10 + \_module_inst: work@rv_dm (work@rv_dm), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:1:1, endln:34:10 |vpiName:tl_h_o |vpiFullName:work@rv_dm.tl_h_o |vpiNet: \_logic_net: (work@rv_dm.tl_h_i), line:22:30, endln:22:36 |vpiParent: - \_module: work@rv_dm (work@rv_dm), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:1:1, endln:34:10 + \_module_inst: work@rv_dm (work@rv_dm), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:1:1, endln:34:10 |vpiName:tl_h_i |vpiFullName:work@rv_dm.tl_h_i |vpiNet: \_logic_net: (work@rv_dm.jtag_req_i), line:24:31, endln:24:41 |vpiParent: - \_module: work@rv_dm (work@rv_dm), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:1:1, endln:34:10 + \_module_inst: work@rv_dm (work@rv_dm), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:1:1, endln:34:10 |vpiName:jtag_req_i |vpiFullName:work@rv_dm.jtag_req_i |vpiNet: \_logic_net: (work@rv_dm.jtag_rsp_o), line:25:31, endln:25:41 |vpiParent: - \_module: work@rv_dm (work@rv_dm), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:1:1, endln:34:10 + \_module_inst: work@rv_dm (work@rv_dm), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:1:1, endln:34:10 |vpiName:jtag_rsp_o |vpiFullName:work@rv_dm.jtag_rsp_o |vpiNet: \_logic_net: (work@rv_dm.dmi_req), line:28:18, endln:28:25 |vpiParent: - \_module: work@rv_dm (work@rv_dm), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:1:1, endln:34:10 + \_module_inst: work@rv_dm (work@rv_dm), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:1:1, endln:34:10 |vpiName:dmi_req |vpiFullName:work@rv_dm.dmi_req |vpiNet: \_logic_net: (work@rv_dm.dmi_rsp), line:29:18, endln:29:25 |vpiParent: - \_module: work@rv_dm (work@rv_dm), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:1:1, endln:34:10 + \_module_inst: work@rv_dm (work@rv_dm), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:1:1, endln:34:10 |vpiName:dmi_rsp |vpiFullName:work@rv_dm.dmi_rsp |vpiNet: \_logic_net: (work@rv_dm.dmi_req_valid), line:30:9, endln:30:22 |vpiParent: - \_module: work@rv_dm (work@rv_dm), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:1:1, endln:34:10 + \_module_inst: work@rv_dm (work@rv_dm), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:1:1, endln:34:10 |vpiName:dmi_req_valid |vpiFullName:work@rv_dm.dmi_req_valid |vpiNetType:36 |vpiNet: \_logic_net: (work@rv_dm.dmi_req_ready), line:30:24, endln:30:37 |vpiParent: - \_module: work@rv_dm (work@rv_dm), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:1:1, endln:34:10 + \_module_inst: work@rv_dm (work@rv_dm), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:1:1, endln:34:10 |vpiName:dmi_req_ready |vpiFullName:work@rv_dm.dmi_req_ready |vpiNetType:36 |vpiNet: \_logic_net: (work@rv_dm.dmi_rsp_valid), line:31:9, endln:31:22 |vpiParent: - \_module: work@rv_dm (work@rv_dm), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:1:1, endln:34:10 + \_module_inst: work@rv_dm (work@rv_dm), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:1:1, endln:34:10 |vpiName:dmi_rsp_valid |vpiFullName:work@rv_dm.dmi_rsp_valid |vpiNetType:36 |vpiNet: \_logic_net: (work@rv_dm.dmi_rsp_ready), line:31:24, endln:31:37 |vpiParent: - \_module: work@rv_dm (work@rv_dm), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:1:1, endln:34:10 + \_module_inst: work@rv_dm (work@rv_dm), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:1:1, endln:34:10 |vpiName:dmi_rsp_ready |vpiFullName:work@rv_dm.dmi_rsp_ready |vpiNetType:36 |vpiNet: \_logic_net: (work@rv_dm.dmi_rst_n), line:32:9, endln:32:18 |vpiParent: - \_module: work@rv_dm (work@rv_dm), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:1:1, endln:34:10 + \_module_inst: work@rv_dm (work@rv_dm), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:1:1, endln:34:10 |vpiName:dmi_rst_n |vpiFullName:work@rv_dm.dmi_rst_n |vpiNetType:36 |vpiPort: \_port: (clk_i), line:5:30, endln:5:35 |vpiParent: - \_module: work@rv_dm (work@rv_dm), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:1:1, endln:34:10 + \_module_inst: work@rv_dm (work@rv_dm), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:1:1, endln:34:10 |vpiName:clk_i |vpiDirection:1 |vpiLowConn: @@ -1260,7 +1260,7 @@ design: (work@rv_dm) |vpiPort: \_port: (rst_ni), line:6:30, endln:6:36 |vpiParent: - \_module: work@rv_dm (work@rv_dm), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:1:1, endln:34:10 + \_module_inst: work@rv_dm (work@rv_dm), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:1:1, endln:34:10 |vpiName:rst_ni |vpiDirection:1 |vpiLowConn: @@ -1272,7 +1272,7 @@ design: (work@rv_dm) |vpiPort: \_port: (hw_debug_en_i), line:8:31, endln:8:44 |vpiParent: - \_module: work@rv_dm (work@rv_dm), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:1:1, endln:34:10 + \_module_inst: work@rv_dm (work@rv_dm), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:1:1, endln:34:10 |vpiName:hw_debug_en_i |vpiDirection:1 |vpiLowConn: @@ -1285,7 +1285,7 @@ design: (work@rv_dm) |vpiPort: \_port: (testmode_i), line:9:30, endln:9:40 |vpiParent: - \_module: work@rv_dm (work@rv_dm), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:1:1, endln:34:10 + \_module_inst: work@rv_dm (work@rv_dm), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:1:1, endln:34:10 |vpiName:testmode_i |vpiDirection:1 |vpiLowConn: @@ -1297,7 +1297,7 @@ design: (work@rv_dm) |vpiPort: \_port: (ndmreset_o), line:10:30, endln:10:40 |vpiParent: - \_module: work@rv_dm (work@rv_dm), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:1:1, endln:34:10 + \_module_inst: work@rv_dm (work@rv_dm), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:1:1, endln:34:10 |vpiName:ndmreset_o |vpiDirection:2 |vpiLowConn: @@ -1309,7 +1309,7 @@ design: (work@rv_dm) |vpiPort: \_port: (dmactive_o), line:11:30, endln:11:40 |vpiParent: - \_module: work@rv_dm (work@rv_dm), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:1:1, endln:34:10 + \_module_inst: work@rv_dm (work@rv_dm), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:1:1, endln:34:10 |vpiName:dmactive_o |vpiDirection:2 |vpiLowConn: @@ -1321,7 +1321,7 @@ design: (work@rv_dm) |vpiPort: \_port: (debug_req_o), line:12:30, endln:12:41 |vpiParent: - \_module: work@rv_dm (work@rv_dm), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:1:1, endln:34:10 + \_module_inst: work@rv_dm (work@rv_dm), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:1:1, endln:34:10 |vpiName:debug_req_o |vpiDirection:2 |vpiLowConn: @@ -1361,7 +1361,7 @@ design: (work@rv_dm) |vpiPort: \_port: (unavailable_i), line:13:30, endln:13:43 |vpiParent: - \_module: work@rv_dm (work@rv_dm), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:1:1, endln:34:10 + \_module_inst: work@rv_dm (work@rv_dm), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:1:1, endln:34:10 |vpiName:unavailable_i |vpiDirection:1 |vpiLowConn: @@ -1401,7 +1401,7 @@ design: (work@rv_dm) |vpiPort: \_port: (tl_d_i), line:17:30, endln:17:36 |vpiParent: - \_module: work@rv_dm (work@rv_dm), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:1:1, endln:34:10 + \_module_inst: work@rv_dm (work@rv_dm), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:1:1, endln:34:10 |vpiName:tl_d_i |vpiDirection:1 |vpiLowConn: @@ -1414,7 +1414,7 @@ design: (work@rv_dm) |vpiPort: \_port: (tl_d_o), line:18:30, endln:18:36 |vpiParent: - \_module: work@rv_dm (work@rv_dm), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:1:1, endln:34:10 + \_module_inst: work@rv_dm (work@rv_dm), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:1:1, endln:34:10 |vpiName:tl_d_o |vpiDirection:2 |vpiLowConn: @@ -1427,7 +1427,7 @@ design: (work@rv_dm) |vpiPort: \_port: (tl_h_o), line:21:30, endln:21:36 |vpiParent: - \_module: work@rv_dm (work@rv_dm), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:1:1, endln:34:10 + \_module_inst: work@rv_dm (work@rv_dm), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:1:1, endln:34:10 |vpiName:tl_h_o |vpiDirection:2 |vpiLowConn: @@ -1440,7 +1440,7 @@ design: (work@rv_dm) |vpiPort: \_port: (tl_h_i), line:22:30, endln:22:36 |vpiParent: - \_module: work@rv_dm (work@rv_dm), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:1:1, endln:34:10 + \_module_inst: work@rv_dm (work@rv_dm), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:1:1, endln:34:10 |vpiName:tl_h_i |vpiDirection:1 |vpiLowConn: @@ -1453,7 +1453,7 @@ design: (work@rv_dm) |vpiPort: \_port: (jtag_req_i), line:24:31, endln:24:41 |vpiParent: - \_module: work@rv_dm (work@rv_dm), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:1:1, endln:34:10 + \_module_inst: work@rv_dm (work@rv_dm), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:1:1, endln:34:10 |vpiName:jtag_req_i |vpiDirection:1 |vpiLowConn: @@ -1466,7 +1466,7 @@ design: (work@rv_dm) |vpiPort: \_port: (jtag_rsp_o), line:25:31, endln:25:41 |vpiParent: - \_module: work@rv_dm (work@rv_dm), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:1:1, endln:34:10 + \_module_inst: work@rv_dm (work@rv_dm), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:1:1, endln:34:10 |vpiName:jtag_rsp_o |vpiDirection:2 |vpiLowConn: @@ -1477,81 +1477,81 @@ design: (work@rv_dm) \_unsupported_typespec: (jtag_pkg::jtag_rsp_t), line:25:10, endln:25:20 |vpiName:jtag_pkg::jtag_rsp_t |uhdmallModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:56:1, endln:71:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:56:1, endln:71:10 |vpiParent: \_design: (work@rv_dm) |vpiFullName:work@top |vpiDefName:work@top |uhdmtopModules: -\_module: work@rv_dm (work@rv_dm), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:1:1, endln:34:10 +\_module_inst: work@rv_dm (work@rv_dm), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:1:1, endln:34:10 |vpiName:work@rv_dm |vpiVariables: \_logic_var: (work@rv_dm.hw_debug_en_i), line:8:31, endln:8:44 |vpiParent: - \_module: work@rv_dm (work@rv_dm), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:1:1, endln:34:10 + \_module_inst: work@rv_dm (work@rv_dm), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:1:1, endln:34:10 |vpiName:hw_debug_en_i |vpiFullName:work@rv_dm.hw_debug_en_i |vpiVisibility:1 |vpiVariables: \_logic_var: (work@rv_dm.tl_d_i), line:17:30, endln:17:36 |vpiParent: - \_module: work@rv_dm (work@rv_dm), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:1:1, endln:34:10 + \_module_inst: work@rv_dm (work@rv_dm), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:1:1, endln:34:10 |vpiName:tl_d_i |vpiFullName:work@rv_dm.tl_d_i |vpiVisibility:1 |vpiVariables: \_logic_var: (work@rv_dm.tl_d_o), line:18:30, endln:18:36 |vpiParent: - \_module: work@rv_dm (work@rv_dm), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:1:1, endln:34:10 + \_module_inst: work@rv_dm (work@rv_dm), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:1:1, endln:34:10 |vpiName:tl_d_o |vpiFullName:work@rv_dm.tl_d_o |vpiVisibility:1 |vpiVariables: \_logic_var: (work@rv_dm.tl_h_o), line:21:30, endln:21:36 |vpiParent: - \_module: work@rv_dm (work@rv_dm), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:1:1, endln:34:10 + \_module_inst: work@rv_dm (work@rv_dm), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:1:1, endln:34:10 |vpiName:tl_h_o |vpiFullName:work@rv_dm.tl_h_o |vpiVisibility:1 |vpiVariables: \_logic_var: (work@rv_dm.tl_h_i), line:22:30, endln:22:36 |vpiParent: - \_module: work@rv_dm (work@rv_dm), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:1:1, endln:34:10 + \_module_inst: work@rv_dm (work@rv_dm), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:1:1, endln:34:10 |vpiName:tl_h_i |vpiFullName:work@rv_dm.tl_h_i |vpiVisibility:1 |vpiVariables: \_logic_var: (work@rv_dm.jtag_req_i), line:24:31, endln:24:41 |vpiParent: - \_module: work@rv_dm (work@rv_dm), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:1:1, endln:34:10 + \_module_inst: work@rv_dm (work@rv_dm), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:1:1, endln:34:10 |vpiName:jtag_req_i |vpiFullName:work@rv_dm.jtag_req_i |vpiVisibility:1 |vpiVariables: \_logic_var: (work@rv_dm.jtag_rsp_o), line:25:31, endln:25:41 |vpiParent: - \_module: work@rv_dm (work@rv_dm), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:1:1, endln:34:10 + \_module_inst: work@rv_dm (work@rv_dm), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:1:1, endln:34:10 |vpiName:jtag_rsp_o |vpiFullName:work@rv_dm.jtag_rsp_o |vpiVisibility:1 |vpiVariables: \_logic_var: (work@rv_dm.dmi_req), line:28:18, endln:28:25 |vpiParent: - \_module: work@rv_dm (work@rv_dm), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:1:1, endln:34:10 + \_module_inst: work@rv_dm (work@rv_dm), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:1:1, endln:34:10 |vpiName:dmi_req |vpiFullName:work@rv_dm.dmi_req |vpiVisibility:1 |vpiVariables: \_logic_var: (work@rv_dm.dmi_rsp), line:29:18, endln:29:25 |vpiParent: - \_module: work@rv_dm (work@rv_dm), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:1:1, endln:34:10 + \_module_inst: work@rv_dm (work@rv_dm), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:1:1, endln:34:10 |vpiName:dmi_rsp |vpiFullName:work@rv_dm.dmi_rsp |vpiVisibility:1 |vpiVariables: \_logic_var: (work@rv_dm.dmi_req_valid), line:30:9, endln:30:22 |vpiParent: - \_module: work@rv_dm (work@rv_dm), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:1:1, endln:34:10 + \_module_inst: work@rv_dm (work@rv_dm), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:1:1, endln:34:10 |vpiTypespec: \_logic_typespec: , line:30:3, endln:30:8 |vpiName:dmi_req_valid @@ -1560,7 +1560,7 @@ design: (work@rv_dm) |vpiVariables: \_logic_var: (work@rv_dm.dmi_req_ready), line:30:24, endln:30:37 |vpiParent: - \_module: work@rv_dm (work@rv_dm), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:1:1, endln:34:10 + \_module_inst: work@rv_dm (work@rv_dm), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:1:1, endln:34:10 |vpiTypespec: \_logic_typespec: , line:30:3, endln:30:8 |vpiName:dmi_req_ready @@ -1569,7 +1569,7 @@ design: (work@rv_dm) |vpiVariables: \_logic_var: (work@rv_dm.dmi_rsp_valid), line:31:9, endln:31:22 |vpiParent: - \_module: work@rv_dm (work@rv_dm), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:1:1, endln:34:10 + \_module_inst: work@rv_dm (work@rv_dm), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:1:1, endln:34:10 |vpiTypespec: \_logic_typespec: , line:31:3, endln:31:8 |vpiName:dmi_rsp_valid @@ -1578,7 +1578,7 @@ design: (work@rv_dm) |vpiVariables: \_logic_var: (work@rv_dm.dmi_rsp_ready), line:31:24, endln:31:37 |vpiParent: - \_module: work@rv_dm (work@rv_dm), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:1:1, endln:34:10 + \_module_inst: work@rv_dm (work@rv_dm), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:1:1, endln:34:10 |vpiTypespec: \_logic_typespec: , line:31:3, endln:31:8 |vpiName:dmi_rsp_ready @@ -1587,7 +1587,7 @@ design: (work@rv_dm) |vpiVariables: \_logic_var: (work@rv_dm.dmi_rst_n), line:32:9, endln:32:18 |vpiParent: - \_module: work@rv_dm (work@rv_dm), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:1:1, endln:34:10 + \_module_inst: work@rv_dm (work@rv_dm), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:1:1, endln:34:10 |vpiTypespec: \_logic_typespec: , line:32:3, endln:32:8 |vpiName:dmi_rst_n @@ -1596,7 +1596,7 @@ design: (work@rv_dm) |vpiParameter: \_parameter: (work@rv_dm.NrHarts), line:2:30, endln:2:37 |vpiParent: - \_module: work@rv_dm (work@rv_dm), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:1:1, endln:34:10 + \_module_inst: work@rv_dm (work@rv_dm), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:1:1, endln:34:10 |UINT:1 |vpiTypespec: \_int_typespec: , line:2:13, endln:2:16 @@ -1609,7 +1609,7 @@ design: (work@rv_dm) |vpiParameter: \_parameter: (work@rv_dm.IdcodeValue), line:3:30, endln:3:41 |vpiParent: - \_module: work@rv_dm (work@rv_dm), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:1:1, endln:34:10 + \_module_inst: work@rv_dm (work@rv_dm), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:1:1, endln:34:10 |HEX:00000001 |vpiTypespec: \_logic_typespec: , line:3:13, endln:3:25 @@ -1640,7 +1640,7 @@ design: (work@rv_dm) |vpiParamAssign: \_param_assign: , line:2:30, endln:2:41 |vpiParent: - \_module: work@rv_dm (work@rv_dm), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:1:1, endln:34:10 + \_module_inst: work@rv_dm (work@rv_dm), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:1:1, endln:34:10 |vpiRhs: \_constant: , line:2:40, endln:2:41 |vpiDecompile:1 @@ -1654,7 +1654,7 @@ design: (work@rv_dm) |vpiParamAssign: \_param_assign: , line:3:30, endln:3:57 |vpiParent: - \_module: work@rv_dm (work@rv_dm), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:1:1, endln:34:10 + \_module_inst: work@rv_dm (work@rv_dm), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:1:1, endln:34:10 |vpiRhs: \_constant: , line:3:44, endln:3:57 |vpiDecompile:32'h00000001 @@ -1670,7 +1670,7 @@ design: (work@rv_dm) |vpiNet: \_logic_net: (work@rv_dm.clk_i), line:5:30, endln:5:35 |vpiParent: - \_module: work@rv_dm (work@rv_dm), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:1:1, endln:34:10 + \_module_inst: work@rv_dm (work@rv_dm), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:1:1, endln:34:10 |vpiTypespec: \_logic_typespec: , line:5:10, endln:5:15 |vpiName:clk_i @@ -1679,7 +1679,7 @@ design: (work@rv_dm) |vpiNet: \_logic_net: (work@rv_dm.rst_ni), line:6:30, endln:6:36 |vpiParent: - \_module: work@rv_dm (work@rv_dm), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:1:1, endln:34:10 + \_module_inst: work@rv_dm (work@rv_dm), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:1:1, endln:34:10 |vpiTypespec: \_logic_typespec: , line:6:10, endln:6:15 |vpiName:rst_ni @@ -1688,7 +1688,7 @@ design: (work@rv_dm) |vpiNet: \_logic_net: (work@rv_dm.testmode_i), line:9:30, endln:9:40 |vpiParent: - \_module: work@rv_dm (work@rv_dm), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:1:1, endln:34:10 + \_module_inst: work@rv_dm (work@rv_dm), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:1:1, endln:34:10 |vpiTypespec: \_logic_typespec: , line:9:10, endln:9:15 |vpiName:testmode_i @@ -1697,7 +1697,7 @@ design: (work@rv_dm) |vpiNet: \_logic_net: (work@rv_dm.ndmreset_o), line:10:30, endln:10:40 |vpiParent: - \_module: work@rv_dm (work@rv_dm), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:1:1, endln:34:10 + \_module_inst: work@rv_dm (work@rv_dm), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:1:1, endln:34:10 |vpiTypespec: \_logic_typespec: , line:10:10, endln:10:15 |vpiName:ndmreset_o @@ -1706,7 +1706,7 @@ design: (work@rv_dm) |vpiNet: \_logic_net: (work@rv_dm.dmactive_o), line:11:30, endln:11:40 |vpiParent: - \_module: work@rv_dm (work@rv_dm), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:1:1, endln:34:10 + \_module_inst: work@rv_dm (work@rv_dm), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:1:1, endln:34:10 |vpiTypespec: \_logic_typespec: , line:11:10, endln:11:15 |vpiName:dmactive_o @@ -1715,7 +1715,7 @@ design: (work@rv_dm) |vpiNet: \_logic_net: (work@rv_dm.debug_req_o), line:12:30, endln:12:41 |vpiParent: - \_module: work@rv_dm (work@rv_dm), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:1:1, endln:34:10 + \_module_inst: work@rv_dm (work@rv_dm), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:1:1, endln:34:10 |vpiTypespec: \_logic_typespec: , line:12:10, endln:12:29 |vpiRange: @@ -1742,7 +1742,7 @@ design: (work@rv_dm) |vpiNet: \_logic_net: (work@rv_dm.unavailable_i), line:13:30, endln:13:43 |vpiParent: - \_module: work@rv_dm (work@rv_dm), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:1:1, endln:34:10 + \_module_inst: work@rv_dm (work@rv_dm), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:1:1, endln:34:10 |vpiTypespec: \_logic_typespec: , line:13:10, endln:13:29 |vpiRange: @@ -1770,7 +1770,7 @@ design: (work@rv_dm) |vpiPort: \_port: (clk_i), line:5:30, endln:5:35 |vpiParent: - \_module: work@rv_dm (work@rv_dm), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:1:1, endln:34:10 + \_module_inst: work@rv_dm (work@rv_dm), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:1:1, endln:34:10 |vpiName:clk_i |vpiDirection:1 |vpiLowConn: @@ -1784,11 +1784,11 @@ design: (work@rv_dm) |vpiTypedef: \_logic_typespec: , line:5:10, endln:5:15 |vpiInstance: - \_module: work@rv_dm (work@rv_dm), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:1:1, endln:34:10 + \_module_inst: work@rv_dm (work@rv_dm), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:1:1, endln:34:10 |vpiPort: \_port: (rst_ni), line:6:30, endln:6:36 |vpiParent: - \_module: work@rv_dm (work@rv_dm), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:1:1, endln:34:10 + \_module_inst: work@rv_dm (work@rv_dm), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:1:1, endln:34:10 |vpiName:rst_ni |vpiDirection:1 |vpiLowConn: @@ -1802,11 +1802,11 @@ design: (work@rv_dm) |vpiTypedef: \_logic_typespec: , line:6:10, endln:6:15 |vpiInstance: - \_module: work@rv_dm (work@rv_dm), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:1:1, endln:34:10 + \_module_inst: work@rv_dm (work@rv_dm), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:1:1, endln:34:10 |vpiPort: \_port: (hw_debug_en_i), line:8:31, endln:8:44 |vpiParent: - \_module: work@rv_dm (work@rv_dm), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:1:1, endln:34:10 + \_module_inst: work@rv_dm (work@rv_dm), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:1:1, endln:34:10 |vpiName:hw_debug_en_i |vpiDirection:1 |vpiLowConn: @@ -1821,11 +1821,11 @@ design: (work@rv_dm) \_unsupported_typespec: (lc_ctrl_pkg::lc_tx_t), line:8:10, endln:8:23 |vpiName:lc_ctrl_pkg::lc_tx_t |vpiInstance: - \_module: work@rv_dm (work@rv_dm), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:1:1, endln:34:10 + \_module_inst: work@rv_dm (work@rv_dm), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:1:1, endln:34:10 |vpiPort: \_port: (testmode_i), line:9:30, endln:9:40 |vpiParent: - \_module: work@rv_dm (work@rv_dm), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:1:1, endln:34:10 + \_module_inst: work@rv_dm (work@rv_dm), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:1:1, endln:34:10 |vpiName:testmode_i |vpiDirection:1 |vpiLowConn: @@ -1839,11 +1839,11 @@ design: (work@rv_dm) |vpiTypedef: \_logic_typespec: , line:9:10, endln:9:15 |vpiInstance: - \_module: work@rv_dm (work@rv_dm), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:1:1, endln:34:10 + \_module_inst: work@rv_dm (work@rv_dm), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:1:1, endln:34:10 |vpiPort: \_port: (ndmreset_o), line:10:30, endln:10:40 |vpiParent: - \_module: work@rv_dm (work@rv_dm), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:1:1, endln:34:10 + \_module_inst: work@rv_dm (work@rv_dm), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:1:1, endln:34:10 |vpiName:ndmreset_o |vpiDirection:2 |vpiLowConn: @@ -1857,11 +1857,11 @@ design: (work@rv_dm) |vpiTypedef: \_logic_typespec: , line:10:10, endln:10:15 |vpiInstance: - \_module: work@rv_dm (work@rv_dm), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:1:1, endln:34:10 + \_module_inst: work@rv_dm (work@rv_dm), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:1:1, endln:34:10 |vpiPort: \_port: (dmactive_o), line:11:30, endln:11:40 |vpiParent: - \_module: work@rv_dm (work@rv_dm), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:1:1, endln:34:10 + \_module_inst: work@rv_dm (work@rv_dm), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:1:1, endln:34:10 |vpiName:dmactive_o |vpiDirection:2 |vpiLowConn: @@ -1875,11 +1875,11 @@ design: (work@rv_dm) |vpiTypedef: \_logic_typespec: , line:11:10, endln:11:15 |vpiInstance: - \_module: work@rv_dm (work@rv_dm), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:1:1, endln:34:10 + \_module_inst: work@rv_dm (work@rv_dm), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:1:1, endln:34:10 |vpiPort: \_port: (debug_req_o), line:12:30, endln:12:41 |vpiParent: - \_module: work@rv_dm (work@rv_dm), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:1:1, endln:34:10 + \_module_inst: work@rv_dm (work@rv_dm), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:1:1, endln:34:10 |vpiName:debug_req_o |vpiDirection:2 |vpiLowConn: @@ -1913,11 +1913,11 @@ design: (work@rv_dm) |UINT:0 |vpiConstType:9 |vpiInstance: - \_module: work@rv_dm (work@rv_dm), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:1:1, endln:34:10 + \_module_inst: work@rv_dm (work@rv_dm), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:1:1, endln:34:10 |vpiPort: \_port: (unavailable_i), line:13:30, endln:13:43 |vpiParent: - \_module: work@rv_dm (work@rv_dm), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:1:1, endln:34:10 + \_module_inst: work@rv_dm (work@rv_dm), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:1:1, endln:34:10 |vpiName:unavailable_i |vpiDirection:1 |vpiLowConn: @@ -1951,11 +1951,11 @@ design: (work@rv_dm) |UINT:0 |vpiConstType:9 |vpiInstance: - \_module: work@rv_dm (work@rv_dm), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:1:1, endln:34:10 + \_module_inst: work@rv_dm (work@rv_dm), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:1:1, endln:34:10 |vpiPort: \_port: (tl_d_i), line:17:30, endln:17:36 |vpiParent: - \_module: work@rv_dm (work@rv_dm), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:1:1, endln:34:10 + \_module_inst: work@rv_dm (work@rv_dm), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:1:1, endln:34:10 |vpiName:tl_d_i |vpiDirection:1 |vpiLowConn: @@ -1970,11 +1970,11 @@ design: (work@rv_dm) \_unsupported_typespec: (tlul_pkg::tl_h2d_t), line:17:10, endln:17:20 |vpiName:tlul_pkg::tl_h2d_t |vpiInstance: - \_module: work@rv_dm (work@rv_dm), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:1:1, endln:34:10 + \_module_inst: work@rv_dm (work@rv_dm), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:1:1, endln:34:10 |vpiPort: \_port: (tl_d_o), line:18:30, endln:18:36 |vpiParent: - \_module: work@rv_dm (work@rv_dm), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:1:1, endln:34:10 + \_module_inst: work@rv_dm (work@rv_dm), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:1:1, endln:34:10 |vpiName:tl_d_o |vpiDirection:2 |vpiLowConn: @@ -1989,11 +1989,11 @@ design: (work@rv_dm) \_unsupported_typespec: (tlul_pkg::tl_d2h_t), line:18:10, endln:18:20 |vpiName:tlul_pkg::tl_d2h_t |vpiInstance: - \_module: work@rv_dm (work@rv_dm), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:1:1, endln:34:10 + \_module_inst: work@rv_dm (work@rv_dm), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:1:1, endln:34:10 |vpiPort: \_port: (tl_h_o), line:21:30, endln:21:36 |vpiParent: - \_module: work@rv_dm (work@rv_dm), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:1:1, endln:34:10 + \_module_inst: work@rv_dm (work@rv_dm), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:1:1, endln:34:10 |vpiName:tl_h_o |vpiDirection:2 |vpiLowConn: @@ -2008,11 +2008,11 @@ design: (work@rv_dm) \_unsupported_typespec: (tlul_pkg::tl_h2d_t), line:21:10, endln:21:20 |vpiName:tlul_pkg::tl_h2d_t |vpiInstance: - \_module: work@rv_dm (work@rv_dm), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:1:1, endln:34:10 + \_module_inst: work@rv_dm (work@rv_dm), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:1:1, endln:34:10 |vpiPort: \_port: (tl_h_i), line:22:30, endln:22:36 |vpiParent: - \_module: work@rv_dm (work@rv_dm), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:1:1, endln:34:10 + \_module_inst: work@rv_dm (work@rv_dm), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:1:1, endln:34:10 |vpiName:tl_h_i |vpiDirection:1 |vpiLowConn: @@ -2027,11 +2027,11 @@ design: (work@rv_dm) \_unsupported_typespec: (tlul_pkg::tl_d2h_t), line:22:10, endln:22:20 |vpiName:tlul_pkg::tl_d2h_t |vpiInstance: - \_module: work@rv_dm (work@rv_dm), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:1:1, endln:34:10 + \_module_inst: work@rv_dm (work@rv_dm), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:1:1, endln:34:10 |vpiPort: \_port: (jtag_req_i), line:24:31, endln:24:41 |vpiParent: - \_module: work@rv_dm (work@rv_dm), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:1:1, endln:34:10 + \_module_inst: work@rv_dm (work@rv_dm), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:1:1, endln:34:10 |vpiName:jtag_req_i |vpiDirection:1 |vpiLowConn: @@ -2046,11 +2046,11 @@ design: (work@rv_dm) \_unsupported_typespec: (jtag_pkg::jtag_req_t), line:24:10, endln:24:20 |vpiName:jtag_pkg::jtag_req_t |vpiInstance: - \_module: work@rv_dm (work@rv_dm), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:1:1, endln:34:10 + \_module_inst: work@rv_dm (work@rv_dm), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:1:1, endln:34:10 |vpiPort: \_port: (jtag_rsp_o), line:25:31, endln:25:41 |vpiParent: - \_module: work@rv_dm (work@rv_dm), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:1:1, endln:34:10 + \_module_inst: work@rv_dm (work@rv_dm), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:1:1, endln:34:10 |vpiName:jtag_rsp_o |vpiDirection:2 |vpiLowConn: @@ -2065,16 +2065,16 @@ design: (work@rv_dm) \_unsupported_typespec: (jtag_pkg::jtag_rsp_t), line:25:10, endln:25:20 |vpiName:jtag_pkg::jtag_rsp_t |vpiInstance: - \_module: work@rv_dm (work@rv_dm), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:1:1, endln:34:10 - |vpiModule: - \_module: work@dmidpi (u_dmidpi), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:57:14, endln:70:5 + \_module_inst: work@rv_dm (work@rv_dm), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:1:1, endln:34:10 + |vpiModuleInst: + \_module_inst: work@dmidpi (u_dmidpi), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:57:14, endln:70:5 |vpiParent: - \_module: work@rv_dm (work@rv_dm), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:1:1, endln:34:10 + \_module_inst: work@rv_dm (work@rv_dm), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:1:1, endln:34:10 |vpiName:u_dmidpi |vpiVariables: \_bit_var: (work@rv_dm.u_dmidpi.clk_i), line:40:21, endln:40:26 |vpiParent: - \_module: work@dmidpi (u_dmidpi), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:57:14, endln:70:5 + \_module_inst: work@dmidpi (u_dmidpi), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:57:14, endln:70:5 |vpiTypespec: \_bit_typespec: , line:40:10, endln:40:13 |vpiSigned:1 @@ -2084,7 +2084,7 @@ design: (work@rv_dm) |vpiVariables: \_bit_var: (work@rv_dm.u_dmidpi.rst_ni), line:41:21, endln:41:27 |vpiParent: - \_module: work@dmidpi (u_dmidpi), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:57:14, endln:70:5 + \_module_inst: work@dmidpi (u_dmidpi), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:57:14, endln:70:5 |vpiTypespec: \_bit_typespec: , line:41:10, endln:41:13 |vpiSigned:1 @@ -2094,7 +2094,7 @@ design: (work@rv_dm) |vpiVariables: \_bit_var: (work@rv_dm.u_dmidpi.dmi_req_valid), line:43:21, endln:43:34 |vpiParent: - \_module: work@dmidpi (u_dmidpi), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:57:14, endln:70:5 + \_module_inst: work@dmidpi (u_dmidpi), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:57:14, endln:70:5 |vpiTypespec: \_bit_typespec: , line:43:10, endln:43:13 |vpiSigned:1 @@ -2104,7 +2104,7 @@ design: (work@rv_dm) |vpiVariables: \_bit_var: (work@rv_dm.u_dmidpi.dmi_req_ready), line:44:21, endln:44:34 |vpiParent: - \_module: work@dmidpi (u_dmidpi), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:57:14, endln:70:5 + \_module_inst: work@dmidpi (u_dmidpi), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:57:14, endln:70:5 |vpiTypespec: \_bit_typespec: , line:44:10, endln:44:13 |vpiSigned:1 @@ -2114,7 +2114,7 @@ design: (work@rv_dm) |vpiVariables: \_bit_var: (work@rv_dm.u_dmidpi.dmi_req_addr), line:45:21, endln:45:33 |vpiParent: - \_module: work@dmidpi (u_dmidpi), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:57:14, endln:70:5 + \_module_inst: work@dmidpi (u_dmidpi), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:57:14, endln:70:5 |vpiTypespec: \_bit_typespec: , line:45:10, endln:45:19 |vpiRange: @@ -2142,7 +2142,7 @@ design: (work@rv_dm) |vpiVariables: \_bit_var: (work@rv_dm.u_dmidpi.dmi_req_op), line:46:21, endln:46:31 |vpiParent: - \_module: work@dmidpi (u_dmidpi), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:57:14, endln:70:5 + \_module_inst: work@dmidpi (u_dmidpi), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:57:14, endln:70:5 |vpiTypespec: \_bit_typespec: , line:46:10, endln:46:19 |vpiRange: @@ -2170,7 +2170,7 @@ design: (work@rv_dm) |vpiVariables: \_bit_var: (work@rv_dm.u_dmidpi.dmi_req_data), line:47:21, endln:47:33 |vpiParent: - \_module: work@dmidpi (u_dmidpi), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:57:14, endln:70:5 + \_module_inst: work@dmidpi (u_dmidpi), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:57:14, endln:70:5 |vpiTypespec: \_bit_typespec: , line:47:10, endln:47:20 |vpiRange: @@ -2198,7 +2198,7 @@ design: (work@rv_dm) |vpiVariables: \_bit_var: (work@rv_dm.u_dmidpi.dmi_rsp_valid), line:48:21, endln:48:34 |vpiParent: - \_module: work@dmidpi (u_dmidpi), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:57:14, endln:70:5 + \_module_inst: work@dmidpi (u_dmidpi), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:57:14, endln:70:5 |vpiTypespec: \_bit_typespec: , line:48:10, endln:48:13 |vpiSigned:1 @@ -2208,7 +2208,7 @@ design: (work@rv_dm) |vpiVariables: \_bit_var: (work@rv_dm.u_dmidpi.dmi_rsp_ready), line:49:21, endln:49:34 |vpiParent: - \_module: work@dmidpi (u_dmidpi), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:57:14, endln:70:5 + \_module_inst: work@dmidpi (u_dmidpi), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:57:14, endln:70:5 |vpiTypespec: \_bit_typespec: , line:49:10, endln:49:13 |vpiSigned:1 @@ -2218,7 +2218,7 @@ design: (work@rv_dm) |vpiVariables: \_bit_var: (work@rv_dm.u_dmidpi.dmi_rsp_data), line:50:21, endln:50:33 |vpiParent: - \_module: work@dmidpi (u_dmidpi), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:57:14, endln:70:5 + \_module_inst: work@dmidpi (u_dmidpi), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:57:14, endln:70:5 |vpiTypespec: \_bit_typespec: , line:50:10, endln:50:20 |vpiRange: @@ -2246,7 +2246,7 @@ design: (work@rv_dm) |vpiVariables: \_bit_var: (work@rv_dm.u_dmidpi.dmi_rsp_resp), line:51:21, endln:51:33 |vpiParent: - \_module: work@dmidpi (u_dmidpi), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:57:14, endln:70:5 + \_module_inst: work@dmidpi (u_dmidpi), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:57:14, endln:70:5 |vpiTypespec: \_bit_typespec: , line:51:10, endln:51:19 |vpiRange: @@ -2274,7 +2274,7 @@ design: (work@rv_dm) |vpiVariables: \_bit_var: (work@rv_dm.u_dmidpi.dmi_rst_n), line:52:21, endln:52:30 |vpiParent: - \_module: work@dmidpi (u_dmidpi), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:57:14, endln:70:5 + \_module_inst: work@dmidpi (u_dmidpi), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:57:14, endln:70:5 |vpiTypespec: \_bit_typespec: , line:52:10, endln:52:13 |vpiSigned:1 @@ -2284,7 +2284,7 @@ design: (work@rv_dm) |vpiParameter: \_parameter: (work@rv_dm.u_dmidpi.Name), line:37:20, endln:37:24 |vpiParent: - \_module: work@dmidpi (u_dmidpi), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:57:14, endln:70:5 + \_module_inst: work@dmidpi (u_dmidpi), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:57:14, endln:70:5 |STRING:dmi0 |vpiTypespec: \_string_typespec: , line:37:13, endln:37:19 @@ -2295,7 +2295,7 @@ design: (work@rv_dm) |vpiParameter: \_parameter: (work@rv_dm.u_dmidpi.ListenPort), line:38:17, endln:38:27 |vpiParent: - \_module: work@dmidpi (u_dmidpi), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:57:14, endln:70:5 + \_module_inst: work@dmidpi (u_dmidpi), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:57:14, endln:70:5 |UINT:44853 |vpiTypespec: \_int_typespec: , line:38:13, endln:38:16 @@ -2308,7 +2308,7 @@ design: (work@rv_dm) |vpiParamAssign: \_param_assign: , line:37:20, endln:37:33 |vpiParent: - \_module: work@dmidpi (u_dmidpi), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:57:14, endln:70:5 + \_module_inst: work@dmidpi (u_dmidpi), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:57:14, endln:70:5 |vpiRhs: \_constant: , line:37:27, endln:37:33 |vpiDecompile:dmi0 @@ -2322,7 +2322,7 @@ design: (work@rv_dm) |vpiParamAssign: \_param_assign: , line:38:17, endln:38:35 |vpiParent: - \_module: work@dmidpi (u_dmidpi), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:57:14, endln:70:5 + \_module_inst: work@dmidpi (u_dmidpi), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:57:14, endln:70:5 |vpiRhs: \_constant: , line:38:30, endln:38:35 |vpiDecompile:44853 @@ -2337,11 +2337,11 @@ design: (work@rv_dm) |vpiDefFile:${SURELOG_DIR}/tests/BindStmt2/dut.sv |vpiDefLineNo:36 |vpiInstance: - \_module: work@rv_dm (work@rv_dm), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:1:1, endln:34:10 + \_module_inst: work@rv_dm (work@rv_dm), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:1:1, endln:34:10 |vpiPort: \_port: (clk_i), line:40:21, endln:40:26 |vpiParent: - \_module: work@dmidpi (u_dmidpi), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:57:14, endln:70:5 + \_module_inst: work@dmidpi (u_dmidpi), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:57:14, endln:70:5 |vpiName:clk_i |vpiDirection:1 |vpiLowConn: @@ -2356,11 +2356,11 @@ design: (work@rv_dm) \_bit_typespec: , line:40:10, endln:40:13 |vpiSigned:1 |vpiInstance: - \_module: work@dmidpi (u_dmidpi), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:57:14, endln:70:5 + \_module_inst: work@dmidpi (u_dmidpi), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:57:14, endln:70:5 |vpiPort: \_port: (rst_ni), line:41:21, endln:41:27 |vpiParent: - \_module: work@dmidpi (u_dmidpi), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:57:14, endln:70:5 + \_module_inst: work@dmidpi (u_dmidpi), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:57:14, endln:70:5 |vpiName:rst_ni |vpiDirection:1 |vpiLowConn: @@ -2375,11 +2375,11 @@ design: (work@rv_dm) \_bit_typespec: , line:41:10, endln:41:13 |vpiSigned:1 |vpiInstance: - \_module: work@dmidpi (u_dmidpi), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:57:14, endln:70:5 + \_module_inst: work@dmidpi (u_dmidpi), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:57:14, endln:70:5 |vpiPort: \_port: (dmi_req_valid), line:43:21, endln:43:34 |vpiParent: - \_module: work@dmidpi (u_dmidpi), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:57:14, endln:70:5 + \_module_inst: work@dmidpi (u_dmidpi), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:57:14, endln:70:5 |vpiName:dmi_req_valid |vpiDirection:2 |vpiLowConn: @@ -2394,11 +2394,11 @@ design: (work@rv_dm) \_bit_typespec: , line:43:10, endln:43:13 |vpiSigned:1 |vpiInstance: - \_module: work@dmidpi (u_dmidpi), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:57:14, endln:70:5 + \_module_inst: work@dmidpi (u_dmidpi), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:57:14, endln:70:5 |vpiPort: \_port: (dmi_req_ready), line:44:21, endln:44:34 |vpiParent: - \_module: work@dmidpi (u_dmidpi), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:57:14, endln:70:5 + \_module_inst: work@dmidpi (u_dmidpi), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:57:14, endln:70:5 |vpiName:dmi_req_ready |vpiDirection:1 |vpiLowConn: @@ -2413,11 +2413,11 @@ design: (work@rv_dm) \_bit_typespec: , line:44:10, endln:44:13 |vpiSigned:1 |vpiInstance: - \_module: work@dmidpi (u_dmidpi), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:57:14, endln:70:5 + \_module_inst: work@dmidpi (u_dmidpi), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:57:14, endln:70:5 |vpiPort: \_port: (dmi_req_addr), line:45:21, endln:45:33 |vpiParent: - \_module: work@dmidpi (u_dmidpi), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:57:14, endln:70:5 + \_module_inst: work@dmidpi (u_dmidpi), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:57:14, endln:70:5 |vpiName:dmi_req_addr |vpiDirection:2 |vpiHighConn: @@ -2469,11 +2469,11 @@ design: (work@rv_dm) |vpiConstType:9 |vpiSigned:1 |vpiInstance: - \_module: work@dmidpi (u_dmidpi), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:57:14, endln:70:5 + \_module_inst: work@dmidpi (u_dmidpi), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:57:14, endln:70:5 |vpiPort: \_port: (dmi_req_op), line:46:21, endln:46:31 |vpiParent: - \_module: work@dmidpi (u_dmidpi), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:57:14, endln:70:5 + \_module_inst: work@dmidpi (u_dmidpi), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:57:14, endln:70:5 |vpiName:dmi_req_op |vpiDirection:2 |vpiHighConn: @@ -2525,11 +2525,11 @@ design: (work@rv_dm) |vpiConstType:9 |vpiSigned:1 |vpiInstance: - \_module: work@dmidpi (u_dmidpi), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:57:14, endln:70:5 + \_module_inst: work@dmidpi (u_dmidpi), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:57:14, endln:70:5 |vpiPort: \_port: (dmi_req_data), line:47:21, endln:47:33 |vpiParent: - \_module: work@dmidpi (u_dmidpi), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:57:14, endln:70:5 + \_module_inst: work@dmidpi (u_dmidpi), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:57:14, endln:70:5 |vpiName:dmi_req_data |vpiDirection:2 |vpiHighConn: @@ -2581,11 +2581,11 @@ design: (work@rv_dm) |vpiConstType:9 |vpiSigned:1 |vpiInstance: - \_module: work@dmidpi (u_dmidpi), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:57:14, endln:70:5 + \_module_inst: work@dmidpi (u_dmidpi), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:57:14, endln:70:5 |vpiPort: \_port: (dmi_rsp_valid), line:48:21, endln:48:34 |vpiParent: - \_module: work@dmidpi (u_dmidpi), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:57:14, endln:70:5 + \_module_inst: work@dmidpi (u_dmidpi), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:57:14, endln:70:5 |vpiName:dmi_rsp_valid |vpiDirection:1 |vpiLowConn: @@ -2600,11 +2600,11 @@ design: (work@rv_dm) \_bit_typespec: , line:48:10, endln:48:13 |vpiSigned:1 |vpiInstance: - \_module: work@dmidpi (u_dmidpi), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:57:14, endln:70:5 + \_module_inst: work@dmidpi (u_dmidpi), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:57:14, endln:70:5 |vpiPort: \_port: (dmi_rsp_ready), line:49:21, endln:49:34 |vpiParent: - \_module: work@dmidpi (u_dmidpi), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:57:14, endln:70:5 + \_module_inst: work@dmidpi (u_dmidpi), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:57:14, endln:70:5 |vpiName:dmi_rsp_ready |vpiDirection:2 |vpiLowConn: @@ -2619,11 +2619,11 @@ design: (work@rv_dm) \_bit_typespec: , line:49:10, endln:49:13 |vpiSigned:1 |vpiInstance: - \_module: work@dmidpi (u_dmidpi), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:57:14, endln:70:5 + \_module_inst: work@dmidpi (u_dmidpi), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:57:14, endln:70:5 |vpiPort: \_port: (dmi_rsp_data), line:50:21, endln:50:33 |vpiParent: - \_module: work@dmidpi (u_dmidpi), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:57:14, endln:70:5 + \_module_inst: work@dmidpi (u_dmidpi), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:57:14, endln:70:5 |vpiName:dmi_rsp_data |vpiDirection:1 |vpiHighConn: @@ -2675,11 +2675,11 @@ design: (work@rv_dm) |vpiConstType:9 |vpiSigned:1 |vpiInstance: - \_module: work@dmidpi (u_dmidpi), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:57:14, endln:70:5 + \_module_inst: work@dmidpi (u_dmidpi), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:57:14, endln:70:5 |vpiPort: \_port: (dmi_rsp_resp), line:51:21, endln:51:33 |vpiParent: - \_module: work@dmidpi (u_dmidpi), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:57:14, endln:70:5 + \_module_inst: work@dmidpi (u_dmidpi), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:57:14, endln:70:5 |vpiName:dmi_rsp_resp |vpiDirection:1 |vpiHighConn: @@ -2731,11 +2731,11 @@ design: (work@rv_dm) |vpiConstType:9 |vpiSigned:1 |vpiInstance: - \_module: work@dmidpi (u_dmidpi), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:57:14, endln:70:5 + \_module_inst: work@dmidpi (u_dmidpi), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:57:14, endln:70:5 |vpiPort: \_port: (dmi_rst_n), line:52:21, endln:52:30 |vpiParent: - \_module: work@dmidpi (u_dmidpi), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:57:14, endln:70:5 + \_module_inst: work@dmidpi (u_dmidpi), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:57:14, endln:70:5 |vpiName:dmi_rst_n |vpiDirection:2 |vpiHighConn: @@ -2758,9 +2758,9 @@ design: (work@rv_dm) \_bit_typespec: , line:52:10, endln:52:13 |vpiSigned:1 |vpiInstance: - \_module: work@dmidpi (u_dmidpi), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:57:14, endln:70:5 + \_module_inst: work@dmidpi (u_dmidpi), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:57:14, endln:70:5 |uhdmtopModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:56:1, endln:71:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:56:1, endln:71:10 |vpiName:work@top |vpiDefName:work@top |vpiTop:1 diff --git a/tests/BindVarsAndEnum/BindVarsAndEnum.log b/tests/BindVarsAndEnum/BindVarsAndEnum.log index 035cf047a9..c6ed96e9c5 100644 --- a/tests/BindVarsAndEnum/BindVarsAndEnum.log +++ b/tests/BindVarsAndEnum/BindVarsAndEnum.log @@ -467,7 +467,7 @@ io_decl 11 logic_net 6 logic_typespec 1 logic_var 1 -module 3 +module_inst 3 operation 2 package 2 port 6 @@ -501,7 +501,7 @@ io_decl 22 logic_net 6 logic_typespec 1 logic_var 1 -module 3 +module_inst 3 operation 4 package 2 port 9 @@ -997,17 +997,17 @@ design: (work@conditional_Fsm) \_int_typespec: |vpiSigned:1 |uhdmallModules: -\_module: work@conditional_Fsm (work@conditional_Fsm), file:${SURELOG_DIR}/tests/BindVarsAndEnum/dut.sv, line:1:1, endln:18:10 +\_module_inst: work@conditional_Fsm (work@conditional_Fsm), file:${SURELOG_DIR}/tests/BindVarsAndEnum/dut.sv, line:1:1, endln:18:10 |vpiParent: \_design: (work@conditional_Fsm) |vpiFullName:work@conditional_Fsm |vpiTypedef: \_enum_typespec: (state), line:7:3, endln:7:65 |vpiParent: - \_module: work@conditional_Fsm (work@conditional_Fsm), file:${SURELOG_DIR}/tests/BindVarsAndEnum/dut.sv, line:1:1, endln:18:10 + \_module_inst: work@conditional_Fsm (work@conditional_Fsm), file:${SURELOG_DIR}/tests/BindVarsAndEnum/dut.sv, line:1:1, endln:18:10 |vpiName:state |vpiInstance: - \_module: work@conditional_Fsm (work@conditional_Fsm), file:${SURELOG_DIR}/tests/BindVarsAndEnum/dut.sv, line:1:1, endln:18:10 + \_module_inst: work@conditional_Fsm (work@conditional_Fsm), file:${SURELOG_DIR}/tests/BindVarsAndEnum/dut.sv, line:1:1, endln:18:10 |vpiBaseTypespec: \_logic_typespec: , line:7:16, endln:7:27 |vpiRange: @@ -1050,43 +1050,43 @@ design: (work@conditional_Fsm) |vpiNet: \_logic_net: (work@conditional_Fsm.reset), line:1:36, endln:1:41 |vpiParent: - \_module: work@conditional_Fsm (work@conditional_Fsm), file:${SURELOG_DIR}/tests/BindVarsAndEnum/dut.sv, line:1:1, endln:18:10 + \_module_inst: work@conditional_Fsm (work@conditional_Fsm), file:${SURELOG_DIR}/tests/BindVarsAndEnum/dut.sv, line:1:1, endln:18:10 |vpiName:reset |vpiFullName:work@conditional_Fsm.reset |vpiNet: \_logic_net: (work@conditional_Fsm.increment), line:2:13, endln:2:22 |vpiParent: - \_module: work@conditional_Fsm (work@conditional_Fsm), file:${SURELOG_DIR}/tests/BindVarsAndEnum/dut.sv, line:1:1, endln:18:10 + \_module_inst: work@conditional_Fsm (work@conditional_Fsm), file:${SURELOG_DIR}/tests/BindVarsAndEnum/dut.sv, line:1:1, endln:18:10 |vpiName:increment |vpiFullName:work@conditional_Fsm.increment |vpiNet: \_logic_net: (work@conditional_Fsm.count), line:3:14, endln:3:19 |vpiParent: - \_module: work@conditional_Fsm (work@conditional_Fsm), file:${SURELOG_DIR}/tests/BindVarsAndEnum/dut.sv, line:1:1, endln:18:10 + \_module_inst: work@conditional_Fsm (work@conditional_Fsm), file:${SURELOG_DIR}/tests/BindVarsAndEnum/dut.sv, line:1:1, endln:18:10 |vpiName:count |vpiFullName:work@conditional_Fsm.count |vpiNet: \_logic_net: (work@conditional_Fsm.clock), line:5:7, endln:5:12 |vpiParent: - \_module: work@conditional_Fsm (work@conditional_Fsm), file:${SURELOG_DIR}/tests/BindVarsAndEnum/dut.sv, line:1:1, endln:18:10 + \_module_inst: work@conditional_Fsm (work@conditional_Fsm), file:${SURELOG_DIR}/tests/BindVarsAndEnum/dut.sv, line:1:1, endln:18:10 |vpiName:clock |vpiFullName:work@conditional_Fsm.clock |vpiNet: \_logic_net: (work@conditional_Fsm.curr_state), line:8:9, endln:8:19 |vpiParent: - \_module: work@conditional_Fsm (work@conditional_Fsm), file:${SURELOG_DIR}/tests/BindVarsAndEnum/dut.sv, line:1:1, endln:18:10 + \_module_inst: work@conditional_Fsm (work@conditional_Fsm), file:${SURELOG_DIR}/tests/BindVarsAndEnum/dut.sv, line:1:1, endln:18:10 |vpiName:curr_state |vpiFullName:work@conditional_Fsm.curr_state |vpiNet: \_logic_net: (work@conditional_Fsm.next_state), line:8:21, endln:8:31 |vpiParent: - \_module: work@conditional_Fsm (work@conditional_Fsm), file:${SURELOG_DIR}/tests/BindVarsAndEnum/dut.sv, line:1:1, endln:18:10 + \_module_inst: work@conditional_Fsm (work@conditional_Fsm), file:${SURELOG_DIR}/tests/BindVarsAndEnum/dut.sv, line:1:1, endln:18:10 |vpiName:next_state |vpiFullName:work@conditional_Fsm.next_state |vpiPort: \_port: (reset), line:1:36, endln:1:41 |vpiParent: - \_module: work@conditional_Fsm (work@conditional_Fsm), file:${SURELOG_DIR}/tests/BindVarsAndEnum/dut.sv, line:1:1, endln:18:10 + \_module_inst: work@conditional_Fsm (work@conditional_Fsm), file:${SURELOG_DIR}/tests/BindVarsAndEnum/dut.sv, line:1:1, endln:18:10 |vpiName:reset |vpiDirection:1 |vpiLowConn: @@ -1099,7 +1099,7 @@ design: (work@conditional_Fsm) |vpiPort: \_port: (increment), line:2:13, endln:2:22 |vpiParent: - \_module: work@conditional_Fsm (work@conditional_Fsm), file:${SURELOG_DIR}/tests/BindVarsAndEnum/dut.sv, line:1:1, endln:18:10 + \_module_inst: work@conditional_Fsm (work@conditional_Fsm), file:${SURELOG_DIR}/tests/BindVarsAndEnum/dut.sv, line:1:1, endln:18:10 |vpiName:increment |vpiDirection:1 |vpiLowConn: @@ -1112,7 +1112,7 @@ design: (work@conditional_Fsm) |vpiPort: \_port: (count), line:3:14, endln:3:19 |vpiParent: - \_module: work@conditional_Fsm (work@conditional_Fsm), file:${SURELOG_DIR}/tests/BindVarsAndEnum/dut.sv, line:1:1, endln:18:10 + \_module_inst: work@conditional_Fsm (work@conditional_Fsm), file:${SURELOG_DIR}/tests/BindVarsAndEnum/dut.sv, line:1:1, endln:18:10 |vpiName:count |vpiDirection:2 |vpiLowConn: @@ -1125,7 +1125,7 @@ design: (work@conditional_Fsm) |vpiProcess: \_always: , line:11:3, endln:11:31 |vpiParent: - \_module: work@conditional_Fsm (work@conditional_Fsm), file:${SURELOG_DIR}/tests/BindVarsAndEnum/dut.sv, line:1:1, endln:18:10 + \_module_inst: work@conditional_Fsm (work@conditional_Fsm), file:${SURELOG_DIR}/tests/BindVarsAndEnum/dut.sv, line:1:1, endln:18:10 |vpiStmt: \_delay_control: , line:11:10, endln:11:15 |vpiParent: @@ -1162,7 +1162,7 @@ design: (work@conditional_Fsm) |vpiProcess: \_always: , line:13:3, endln:17:4 |vpiParent: - \_module: work@conditional_Fsm (work@conditional_Fsm), file:${SURELOG_DIR}/tests/BindVarsAndEnum/dut.sv, line:1:1, endln:18:10 + \_module_inst: work@conditional_Fsm (work@conditional_Fsm), file:${SURELOG_DIR}/tests/BindVarsAndEnum/dut.sv, line:1:1, endln:18:10 |vpiStmt: \_event_control: , line:13:13, endln:13:29 |vpiParent: @@ -1225,12 +1225,12 @@ design: (work@conditional_Fsm) \_enum_var: (work@conditional_Fsm.curr_state), line:8:9, endln:8:19 |vpiAlwaysType:3 |uhdmtopModules: -\_module: work@conditional_Fsm (work@conditional_Fsm), file:${SURELOG_DIR}/tests/BindVarsAndEnum/dut.sv, line:1:1, endln:18:10 +\_module_inst: work@conditional_Fsm (work@conditional_Fsm), file:${SURELOG_DIR}/tests/BindVarsAndEnum/dut.sv, line:1:1, endln:18:10 |vpiName:work@conditional_Fsm |vpiVariables: \_bit_var: (work@conditional_Fsm.reset), line:1:36, endln:1:41 |vpiParent: - \_module: work@conditional_Fsm (work@conditional_Fsm), file:${SURELOG_DIR}/tests/BindVarsAndEnum/dut.sv, line:1:1, endln:18:10 + \_module_inst: work@conditional_Fsm (work@conditional_Fsm), file:${SURELOG_DIR}/tests/BindVarsAndEnum/dut.sv, line:1:1, endln:18:10 |vpiTypespec: \_bit_typespec: , line:1:32, endln:1:35 |vpiSigned:1 @@ -1240,7 +1240,7 @@ design: (work@conditional_Fsm) |vpiVariables: \_bit_var: (work@conditional_Fsm.increment), line:2:13, endln:2:22 |vpiParent: - \_module: work@conditional_Fsm (work@conditional_Fsm), file:${SURELOG_DIR}/tests/BindVarsAndEnum/dut.sv, line:1:1, endln:18:10 + \_module_inst: work@conditional_Fsm (work@conditional_Fsm), file:${SURELOG_DIR}/tests/BindVarsAndEnum/dut.sv, line:1:1, endln:18:10 |vpiTypespec: \_bit_typespec: , line:2:9, endln:2:12 |vpiSigned:1 @@ -1250,7 +1250,7 @@ design: (work@conditional_Fsm) |vpiVariables: \_int_var: (work@conditional_Fsm.count), line:3:14, endln:3:19 |vpiParent: - \_module: work@conditional_Fsm (work@conditional_Fsm), file:${SURELOG_DIR}/tests/BindVarsAndEnum/dut.sv, line:1:1, endln:18:10 + \_module_inst: work@conditional_Fsm (work@conditional_Fsm), file:${SURELOG_DIR}/tests/BindVarsAndEnum/dut.sv, line:1:1, endln:18:10 |vpiTypespec: \_int_typespec: , line:3:10, endln:3:13 |vpiSigned:1 @@ -1261,7 +1261,7 @@ design: (work@conditional_Fsm) |vpiVariables: \_bit_var: (work@conditional_Fsm.clock), line:5:7, endln:5:12 |vpiParent: - \_module: work@conditional_Fsm (work@conditional_Fsm), file:${SURELOG_DIR}/tests/BindVarsAndEnum/dut.sv, line:1:1, endln:18:10 + \_module_inst: work@conditional_Fsm (work@conditional_Fsm), file:${SURELOG_DIR}/tests/BindVarsAndEnum/dut.sv, line:1:1, endln:18:10 |vpiTypespec: \_bit_typespec: , line:5:3, endln:5:6 |vpiSigned:1 @@ -1271,7 +1271,7 @@ design: (work@conditional_Fsm) |vpiVariables: \_enum_var: (work@conditional_Fsm.curr_state), line:8:9, endln:8:19 |vpiParent: - \_module: work@conditional_Fsm (work@conditional_Fsm), file:${SURELOG_DIR}/tests/BindVarsAndEnum/dut.sv, line:1:1, endln:18:10 + \_module_inst: work@conditional_Fsm (work@conditional_Fsm), file:${SURELOG_DIR}/tests/BindVarsAndEnum/dut.sv, line:1:1, endln:18:10 |vpiTypespec: \_enum_typespec: (state), line:7:3, endln:7:65 |vpiName:curr_state @@ -1280,7 +1280,7 @@ design: (work@conditional_Fsm) |vpiVariables: \_enum_var: (work@conditional_Fsm.next_state), line:8:21, endln:8:31 |vpiParent: - \_module: work@conditional_Fsm (work@conditional_Fsm), file:${SURELOG_DIR}/tests/BindVarsAndEnum/dut.sv, line:1:1, endln:18:10 + \_module_inst: work@conditional_Fsm (work@conditional_Fsm), file:${SURELOG_DIR}/tests/BindVarsAndEnum/dut.sv, line:1:1, endln:18:10 |vpiTypespec: \_enum_typespec: (state), line:7:3, endln:7:65 |vpiName:next_state @@ -1294,7 +1294,7 @@ design: (work@conditional_Fsm) |vpiPort: \_port: (reset), line:1:36, endln:1:41 |vpiParent: - \_module: work@conditional_Fsm (work@conditional_Fsm), file:${SURELOG_DIR}/tests/BindVarsAndEnum/dut.sv, line:1:1, endln:18:10 + \_module_inst: work@conditional_Fsm (work@conditional_Fsm), file:${SURELOG_DIR}/tests/BindVarsAndEnum/dut.sv, line:1:1, endln:18:10 |vpiName:reset |vpiDirection:1 |vpiLowConn: @@ -1309,11 +1309,11 @@ design: (work@conditional_Fsm) \_bit_typespec: , line:1:32, endln:1:35 |vpiSigned:1 |vpiInstance: - \_module: work@conditional_Fsm (work@conditional_Fsm), file:${SURELOG_DIR}/tests/BindVarsAndEnum/dut.sv, line:1:1, endln:18:10 + \_module_inst: work@conditional_Fsm (work@conditional_Fsm), file:${SURELOG_DIR}/tests/BindVarsAndEnum/dut.sv, line:1:1, endln:18:10 |vpiPort: \_port: (increment), line:2:13, endln:2:22 |vpiParent: - \_module: work@conditional_Fsm (work@conditional_Fsm), file:${SURELOG_DIR}/tests/BindVarsAndEnum/dut.sv, line:1:1, endln:18:10 + \_module_inst: work@conditional_Fsm (work@conditional_Fsm), file:${SURELOG_DIR}/tests/BindVarsAndEnum/dut.sv, line:1:1, endln:18:10 |vpiName:increment |vpiDirection:1 |vpiLowConn: @@ -1328,11 +1328,11 @@ design: (work@conditional_Fsm) \_bit_typespec: , line:2:9, endln:2:12 |vpiSigned:1 |vpiInstance: - \_module: work@conditional_Fsm (work@conditional_Fsm), file:${SURELOG_DIR}/tests/BindVarsAndEnum/dut.sv, line:1:1, endln:18:10 + \_module_inst: work@conditional_Fsm (work@conditional_Fsm), file:${SURELOG_DIR}/tests/BindVarsAndEnum/dut.sv, line:1:1, endln:18:10 |vpiPort: \_port: (count), line:3:14, endln:3:19 |vpiParent: - \_module: work@conditional_Fsm (work@conditional_Fsm), file:${SURELOG_DIR}/tests/BindVarsAndEnum/dut.sv, line:1:1, endln:18:10 + \_module_inst: work@conditional_Fsm (work@conditional_Fsm), file:${SURELOG_DIR}/tests/BindVarsAndEnum/dut.sv, line:1:1, endln:18:10 |vpiName:count |vpiDirection:2 |vpiLowConn: @@ -1347,11 +1347,11 @@ design: (work@conditional_Fsm) \_int_typespec: , line:3:10, endln:3:13 |vpiSigned:1 |vpiInstance: - \_module: work@conditional_Fsm (work@conditional_Fsm), file:${SURELOG_DIR}/tests/BindVarsAndEnum/dut.sv, line:1:1, endln:18:10 + \_module_inst: work@conditional_Fsm (work@conditional_Fsm), file:${SURELOG_DIR}/tests/BindVarsAndEnum/dut.sv, line:1:1, endln:18:10 |vpiProcess: \_always: , line:11:3, endln:11:31 |vpiParent: - \_module: work@conditional_Fsm (work@conditional_Fsm), file:${SURELOG_DIR}/tests/BindVarsAndEnum/dut.sv, line:1:1, endln:18:10 + \_module_inst: work@conditional_Fsm (work@conditional_Fsm), file:${SURELOG_DIR}/tests/BindVarsAndEnum/dut.sv, line:1:1, endln:18:10 |vpiStmt: \_delay_control: , line:11:10, endln:11:15 |vpiParent: @@ -1388,7 +1388,7 @@ design: (work@conditional_Fsm) |vpiProcess: \_always: , line:13:3, endln:17:4 |vpiParent: - \_module: work@conditional_Fsm (work@conditional_Fsm), file:${SURELOG_DIR}/tests/BindVarsAndEnum/dut.sv, line:1:1, endln:18:10 + \_module_inst: work@conditional_Fsm (work@conditional_Fsm), file:${SURELOG_DIR}/tests/BindVarsAndEnum/dut.sv, line:1:1, endln:18:10 |vpiStmt: \_event_control: , line:13:13, endln:13:29 |vpiParent: diff --git a/tests/Bindings/Bindings.log b/tests/Bindings/Bindings.log index 9189b13784..2424b5f5ac 100644 --- a/tests/Bindings/Bindings.log +++ b/tests/Bindings/Bindings.log @@ -1366,7 +1366,7 @@ io_decl 11 logic_net 21 logic_typespec 18 logic_var 2 -module 26 +module_inst 26 operation 53 package 5 param_assign 35 @@ -1411,7 +1411,7 @@ io_decl 22 logic_net 21 logic_typespec 18 logic_var 2 -module 26 +module_inst 26 operation 73 package 5 param_assign 35 @@ -2172,14 +2172,14 @@ design: (work@dut1) \_int_typespec: |vpiSigned:1 |uhdmallModules: -\_module: work@bsg_dff_reset (work@bsg_dff_reset), file:${SURELOG_DIR}/tests/Bindings/dut.sv, line:67:1, endln:80:10 +\_module_inst: work@bsg_dff_reset (work@bsg_dff_reset), file:${SURELOG_DIR}/tests/Bindings/dut.sv, line:67:1, endln:80:10 |vpiParent: \_design: (work@dut1) |vpiFullName:work@bsg_dff_reset |vpiParameter: \_parameter: (work@bsg_dff_reset.width_p), line:67:25, endln:67:32 |vpiParent: - \_module: work@bsg_dff_reset (work@bsg_dff_reset), file:${SURELOG_DIR}/tests/Bindings/dut.sv, line:67:1, endln:80:10 + \_module_inst: work@bsg_dff_reset (work@bsg_dff_reset), file:${SURELOG_DIR}/tests/Bindings/dut.sv, line:67:1, endln:80:10 |vpiTypespec: \_int_typespec: (width_p), line:75:22, endln:75:29 |vpiName:width_p @@ -2192,7 +2192,7 @@ design: (work@dut1) |vpiParameter: \_parameter: (work@bsg_dff_reset.reset_val_p), line:67:37, endln:67:48 |vpiParent: - \_module: work@bsg_dff_reset (work@bsg_dff_reset), file:${SURELOG_DIR}/tests/Bindings/dut.sv, line:67:1, endln:80:10 + \_module_inst: work@bsg_dff_reset (work@bsg_dff_reset), file:${SURELOG_DIR}/tests/Bindings/dut.sv, line:67:1, endln:80:10 |UINT:0 |vpiTypespec: \_int_typespec: @@ -2201,7 +2201,7 @@ design: (work@dut1) |vpiParameter: \_parameter: (work@bsg_dff_reset.harden_p), line:67:52, endln:67:60 |vpiParent: - \_module: work@bsg_dff_reset (work@bsg_dff_reset), file:${SURELOG_DIR}/tests/Bindings/dut.sv, line:67:1, endln:80:10 + \_module_inst: work@bsg_dff_reset (work@bsg_dff_reset), file:${SURELOG_DIR}/tests/Bindings/dut.sv, line:67:1, endln:80:10 |UINT:0 |vpiTypespec: \_int_typespec: @@ -2210,7 +2210,7 @@ design: (work@dut1) |vpiParamAssign: \_param_assign: , line:67:25, endln:67:35 |vpiParent: - \_module: work@bsg_dff_reset (work@bsg_dff_reset), file:${SURELOG_DIR}/tests/Bindings/dut.sv, line:67:1, endln:80:10 + \_module_inst: work@bsg_dff_reset (work@bsg_dff_reset), file:${SURELOG_DIR}/tests/Bindings/dut.sv, line:67:1, endln:80:10 |vpiRhs: \_operation: , line:67:33, endln:67:35 |vpiOpType:1 @@ -2225,7 +2225,7 @@ design: (work@dut1) |vpiParamAssign: \_param_assign: , line:67:37, endln:67:50 |vpiParent: - \_module: work@bsg_dff_reset (work@bsg_dff_reset), file:${SURELOG_DIR}/tests/Bindings/dut.sv, line:67:1, endln:80:10 + \_module_inst: work@bsg_dff_reset (work@bsg_dff_reset), file:${SURELOG_DIR}/tests/Bindings/dut.sv, line:67:1, endln:80:10 |vpiRhs: \_constant: , line:67:49, endln:67:50 |vpiDecompile:0 @@ -2239,7 +2239,7 @@ design: (work@dut1) |vpiParamAssign: \_param_assign: , line:67:52, endln:67:62 |vpiParent: - \_module: work@bsg_dff_reset (work@bsg_dff_reset), file:${SURELOG_DIR}/tests/Bindings/dut.sv, line:67:1, endln:80:10 + \_module_inst: work@bsg_dff_reset (work@bsg_dff_reset), file:${SURELOG_DIR}/tests/Bindings/dut.sv, line:67:1, endln:80:10 |vpiRhs: \_constant: , line:67:61, endln:67:62 |vpiDecompile:0 @@ -2254,7 +2254,7 @@ design: (work@dut1) |vpiProcess: \_always: , line:72:4, endln:78:9 |vpiParent: - \_module: work@bsg_dff_reset (work@bsg_dff_reset), file:${SURELOG_DIR}/tests/Bindings/dut.sv, line:67:1, endln:80:10 + \_module_inst: work@bsg_dff_reset (work@bsg_dff_reset), file:${SURELOG_DIR}/tests/Bindings/dut.sv, line:67:1, endln:80:10 |vpiStmt: \_event_control: , line:72:11, endln:72:27 |vpiParent: @@ -2338,14 +2338,14 @@ design: (work@dut1) \_logic_net: (data_r) |vpiAlwaysType:1 |uhdmallModules: -\_module: work@dut1 (work@dut1), file:${SURELOG_DIR}/tests/Bindings/dut.sv, line:20:1, endln:31:10 +\_module_inst: work@dut1 (work@dut1), file:${SURELOG_DIR}/tests/Bindings/dut.sv, line:20:1, endln:31:10 |vpiParent: \_design: (work@dut1) |vpiFullName:work@dut1 |vpiParameter: \_parameter: (work@dut1.NrDevices), line:21:17, endln:21:26 |vpiParent: - \_module: work@dut1 (work@dut1), file:${SURELOG_DIR}/tests/Bindings/dut.sv, line:20:1, endln:31:10 + \_module_inst: work@dut1 (work@dut1), file:${SURELOG_DIR}/tests/Bindings/dut.sv, line:20:1, endln:31:10 |UINT:1 |vpiTypespec: \_int_typespec: , line:21:13, endln:21:16 @@ -2358,7 +2358,7 @@ design: (work@dut1) |vpiParameter: \_parameter: (work@dut1.NumBitsDeviceSel), line:24:27, endln:24:43 |vpiParent: - \_module: work@dut1 (work@dut1), file:${SURELOG_DIR}/tests/Bindings/dut.sv, line:20:1, endln:31:10 + \_module_inst: work@dut1 (work@dut1), file:${SURELOG_DIR}/tests/Bindings/dut.sv, line:20:1, endln:31:10 |vpiTypespec: \_int_typespec: , line:24:14, endln:24:26 |vpiParent: @@ -2373,7 +2373,7 @@ design: (work@dut1) |vpiParamAssign: \_param_assign: , line:21:17, endln:21:30 |vpiParent: - \_module: work@dut1 (work@dut1), file:${SURELOG_DIR}/tests/Bindings/dut.sv, line:20:1, endln:31:10 + \_module_inst: work@dut1 (work@dut1), file:${SURELOG_DIR}/tests/Bindings/dut.sv, line:20:1, endln:31:10 |vpiRhs: \_constant: , line:21:29, endln:21:30 |vpiDecompile:1 @@ -2387,7 +2387,7 @@ design: (work@dut1) |vpiParamAssign: \_param_assign: , line:24:27, endln:24:83 |vpiParent: - \_module: work@dut1 (work@dut1), file:${SURELOG_DIR}/tests/Bindings/dut.sv, line:20:1, endln:31:10 + \_module_inst: work@dut1 (work@dut1), file:${SURELOG_DIR}/tests/Bindings/dut.sv, line:20:1, endln:31:10 |vpiRhs: \_operation: , line:24:46, endln:24:83 |vpiOpType:32 @@ -2433,20 +2433,20 @@ design: (work@dut1) |vpiNet: \_logic_net: (work@dut1.device_sel_req), line:25:32, endln:25:46 |vpiParent: - \_module: work@dut1 (work@dut1), file:${SURELOG_DIR}/tests/Bindings/dut.sv, line:20:1, endln:31:10 + \_module_inst: work@dut1 (work@dut1), file:${SURELOG_DIR}/tests/Bindings/dut.sv, line:20:1, endln:31:10 |vpiName:device_sel_req |vpiFullName:work@dut1.device_sel_req |vpiNetType:36 |vpiNet: \_logic_net: (work@dut1.device), line:26:7, endln:26:13 |vpiParent: - \_module: work@dut1 (work@dut1), file:${SURELOG_DIR}/tests/Bindings/dut.sv, line:20:1, endln:31:10 + \_module_inst: work@dut1 (work@dut1), file:${SURELOG_DIR}/tests/Bindings/dut.sv, line:20:1, endln:31:10 |vpiName:device |vpiFullName:work@dut1.device |vpiProcess: \_always: , line:27:3, endln:29:6 |vpiParent: - \_module: work@dut1 (work@dut1), file:${SURELOG_DIR}/tests/Bindings/dut.sv, line:20:1, endln:31:10 + \_module_inst: work@dut1 (work@dut1), file:${SURELOG_DIR}/tests/Bindings/dut.sv, line:20:1, endln:31:10 |vpiStmt: \_begin: (work@dut1), line:27:15, endln:29:6 |vpiParent: @@ -2483,14 +2483,14 @@ design: (work@dut1) \_logic_var: (work@dut1.device_sel_req), line:25:32, endln:25:46 |vpiAlwaysType:2 |uhdmallModules: -\_module: work@dut2 (work@dut2), file:${SURELOG_DIR}/tests/Bindings/dut.sv, line:35:1, endln:50:10 +\_module_inst: work@dut2 (work@dut2), file:${SURELOG_DIR}/tests/Bindings/dut.sv, line:35:1, endln:50:10 |vpiParent: \_design: (work@dut1) |vpiFullName:work@dut2 |vpiParameter: \_parameter: (work@dut2.num_out_p), line:35:25, endln:35:34 |vpiParent: - \_module: work@dut2 (work@dut2), file:${SURELOG_DIR}/tests/Bindings/dut.sv, line:35:1, endln:50:10 + \_module_inst: work@dut2 (work@dut2), file:${SURELOG_DIR}/tests/Bindings/dut.sv, line:35:1, endln:50:10 |STRING:inv |vpiTypespec: \_string_typespec: @@ -2499,7 +2499,7 @@ design: (work@dut1) |vpiParamAssign: \_param_assign: , line:35:25, endln:35:40 |vpiParent: - \_module: work@dut2 (work@dut2), file:${SURELOG_DIR}/tests/Bindings/dut.sv, line:35:1, endln:50:10 + \_module_inst: work@dut2 (work@dut2), file:${SURELOG_DIR}/tests/Bindings/dut.sv, line:35:1, endln:50:10 |vpiRhs: \_constant: , line:35:35, endln:35:40 |vpiDecompile:inv @@ -2514,20 +2514,20 @@ design: (work@dut1) |vpiNet: \_logic_net: (work@dut2.i), line:37:36, endln:37:37 |vpiParent: - \_module: work@dut2 (work@dut2), file:${SURELOG_DIR}/tests/Bindings/dut.sv, line:35:1, endln:50:10 + \_module_inst: work@dut2 (work@dut2), file:${SURELOG_DIR}/tests/Bindings/dut.sv, line:35:1, endln:50:10 |vpiName:i |vpiFullName:work@dut2.i |vpiNet: \_logic_net: (work@dut2.o), line:38:36, endln:38:37 |vpiParent: - \_module: work@dut2 (work@dut2), file:${SURELOG_DIR}/tests/Bindings/dut.sv, line:35:1, endln:50:10 + \_module_inst: work@dut2 (work@dut2), file:${SURELOG_DIR}/tests/Bindings/dut.sv, line:35:1, endln:50:10 |vpiName:o |vpiFullName:work@dut2.o |vpiNetType:36 |vpiPort: \_port: (i), line:37:36, endln:37:37 |vpiParent: - \_module: work@dut2 (work@dut2), file:${SURELOG_DIR}/tests/Bindings/dut.sv, line:35:1, endln:50:10 + \_module_inst: work@dut2 (work@dut2), file:${SURELOG_DIR}/tests/Bindings/dut.sv, line:35:1, endln:50:10 |vpiName:i |vpiDirection:1 |vpiLowConn: @@ -2572,7 +2572,7 @@ design: (work@dut1) |vpiPort: \_port: (o), line:38:36, endln:38:37 |vpiParent: - \_module: work@dut2 (work@dut2), file:${SURELOG_DIR}/tests/Bindings/dut.sv, line:35:1, endln:50:10 + \_module_inst: work@dut2 (work@dut2), file:${SURELOG_DIR}/tests/Bindings/dut.sv, line:35:1, endln:50:10 |vpiName:o |vpiDirection:2 |vpiLowConn: @@ -2610,14 +2610,14 @@ design: (work@dut1) |UINT:0 |vpiConstType:9 |uhdmallModules: -\_module: work@dut3 (work@dut3), file:${SURELOG_DIR}/tests/Bindings/dut.sv, line:54:1, endln:64:10 +\_module_inst: work@dut3 (work@dut3), file:${SURELOG_DIR}/tests/Bindings/dut.sv, line:54:1, endln:64:10 |vpiParent: \_design: (work@dut1) |vpiFullName:work@dut3 |vpiParameter: \_parameter: (work@dut3.LfsrDw), line:54:45, endln:54:51 |vpiParent: - \_module: work@dut3 (work@dut3), file:${SURELOG_DIR}/tests/Bindings/dut.sv, line:54:1, endln:64:10 + \_module_inst: work@dut3 (work@dut3), file:${SURELOG_DIR}/tests/Bindings/dut.sv, line:54:1, endln:64:10 |UINT:3 |vpiTypespec: \_int_typespec: , line:54:26, endln:54:38 @@ -2628,7 +2628,7 @@ design: (work@dut1) |vpiParamAssign: \_param_assign: , line:54:45, endln:54:61 |vpiParent: - \_module: work@dut3 (work@dut3), file:${SURELOG_DIR}/tests/Bindings/dut.sv, line:54:1, endln:64:10 + \_module_inst: work@dut3 (work@dut3), file:${SURELOG_DIR}/tests/Bindings/dut.sv, line:54:1, endln:64:10 |vpiRhs: \_constant: , line:54:60, endln:54:61 |vpiDecompile:3 @@ -2643,7 +2643,7 @@ design: (work@dut1) |vpiContAssign: \_cont_assign: , line:60:10, endln:60:95 |vpiParent: - \_module: work@dut3 (work@dut3), file:${SURELOG_DIR}/tests/Bindings/dut.sv, line:54:1, endln:64:10 + \_module_inst: work@dut3 (work@dut3), file:${SURELOG_DIR}/tests/Bindings/dut.sv, line:54:1, endln:64:10 |vpiRhs: \_operation: , line:60:28, endln:60:95 |vpiParent: @@ -2750,7 +2750,7 @@ design: (work@dut1) |vpiContAssign: \_cont_assign: , line:62:9, endln:62:28 |vpiParent: - \_module: work@dut3 (work@dut3), file:${SURELOG_DIR}/tests/Bindings/dut.sv, line:54:1, endln:64:10 + \_module_inst: work@dut3 (work@dut3), file:${SURELOG_DIR}/tests/Bindings/dut.sv, line:54:1, endln:64:10 |vpiRhs: \_operation: , line:62:18, endln:62:28 |vpiParent: @@ -2778,32 +2778,32 @@ design: (work@dut1) |vpiActual: \_logic_net: (lockup) |uhdmallModules: -\_module: work@dut5 (work@dut5), file:${SURELOG_DIR}/tests/Bindings/dut.sv, line:82:1, endln:108:10 +\_module_inst: work@dut5 (work@dut5), file:${SURELOG_DIR}/tests/Bindings/dut.sv, line:82:1, endln:108:10 |vpiParent: \_design: (work@dut1) |vpiFullName:work@dut5 |vpiParameter: \_parameter: (work@dut5.inputs_p), line:83:14, endln:83:22 |vpiParent: - \_module: work@dut5 (work@dut5), file:${SURELOG_DIR}/tests/Bindings/dut.sv, line:82:1, endln:108:10 + \_module_inst: work@dut5 (work@dut5), file:${SURELOG_DIR}/tests/Bindings/dut.sv, line:82:1, endln:108:10 |vpiName:inputs_p |vpiFullName:work@dut5.inputs_p |vpiParameter: \_parameter: (work@dut5.lg_inputs_p), line:84:13, endln:84:24 |vpiParent: - \_module: work@dut5 (work@dut5), file:${SURELOG_DIR}/tests/Bindings/dut.sv, line:82:1, endln:108:10 + \_module_inst: work@dut5 (work@dut5), file:${SURELOG_DIR}/tests/Bindings/dut.sv, line:82:1, endln:108:10 |vpiName:lg_inputs_p |vpiFullName:work@dut5.lg_inputs_p |vpiParameter: \_parameter: (work@dut5.width_p), line:85:13, endln:85:20 |vpiParent: - \_module: work@dut5 (work@dut5), file:${SURELOG_DIR}/tests/Bindings/dut.sv, line:82:1, endln:108:10 + \_module_inst: work@dut5 (work@dut5), file:${SURELOG_DIR}/tests/Bindings/dut.sv, line:82:1, endln:108:10 |vpiName:width_p |vpiFullName:work@dut5.width_p |vpiParameter: \_parameter: (work@dut5.TxWidth), line:86:17, endln:86:24 |vpiParent: - \_module: work@dut5 (work@dut5), file:${SURELOG_DIR}/tests/Bindings/dut.sv, line:82:1, endln:108:10 + \_module_inst: work@dut5 (work@dut5), file:${SURELOG_DIR}/tests/Bindings/dut.sv, line:82:1, endln:108:10 |UINT:4 |vpiTypespec: \_int_typespec: , line:86:13, endln:86:16 @@ -2816,19 +2816,19 @@ design: (work@dut1) |vpiParameter: \_parameter: (work@dut5.LC_TX_DEFAULT), line:94:22, endln:94:35 |vpiParent: - \_module: work@dut5 (work@dut5), file:${SURELOG_DIR}/tests/Bindings/dut.sv, line:82:1, endln:108:10 + \_module_inst: work@dut5 (work@dut5), file:${SURELOG_DIR}/tests/Bindings/dut.sv, line:82:1, endln:108:10 |vpiTypespec: \_enum_typespec: (lc_tx_t), line:87:5, endln:90:15 |vpiParent: - \_module: work@dut5 (work@dut5), file:${SURELOG_DIR}/tests/Bindings/dut.sv, line:82:1, endln:108:10 + \_module_inst: work@dut5 (work@dut5), file:${SURELOG_DIR}/tests/Bindings/dut.sv, line:82:1, endln:108:10 |vpiName:lc_tx_t |vpiTypedefAlias: \_enum_typespec: (lc_tx_e), line:87:5, endln:90:15 |vpiParent: - \_module: work@dut5 (work@dut5), file:${SURELOG_DIR}/tests/Bindings/dut.sv, line:82:1, endln:108:10 + \_module_inst: work@dut5 (work@dut5), file:${SURELOG_DIR}/tests/Bindings/dut.sv, line:82:1, endln:108:10 |vpiName:lc_tx_e |vpiInstance: - \_module: work@dut5 (work@dut5), file:${SURELOG_DIR}/tests/Bindings/dut.sv, line:82:1, endln:108:10 + \_module_inst: work@dut5 (work@dut5), file:${SURELOG_DIR}/tests/Bindings/dut.sv, line:82:1, endln:108:10 |vpiBaseTypespec: \_logic_typespec: , line:87:18, endln:87:37 |vpiRange: @@ -2874,7 +2874,7 @@ design: (work@dut1) |vpiDecompile:4'b0101 |vpiSize:4 |vpiInstance: - \_module: work@dut5 (work@dut5), file:${SURELOG_DIR}/tests/Bindings/dut.sv, line:82:1, endln:108:10 + \_module_inst: work@dut5 (work@dut5), file:${SURELOG_DIR}/tests/Bindings/dut.sv, line:82:1, endln:108:10 |vpiBaseTypespec: \_logic_typespec: , line:87:18, endln:87:37 |vpiParent: @@ -2933,7 +2933,7 @@ design: (work@dut1) |vpiParamAssign: \_param_assign: , line:83:14, endln:83:27 |vpiParent: - \_module: work@dut5 (work@dut5), file:${SURELOG_DIR}/tests/Bindings/dut.sv, line:82:1, endln:108:10 + \_module_inst: work@dut5 (work@dut5), file:${SURELOG_DIR}/tests/Bindings/dut.sv, line:82:1, endln:108:10 |vpiRhs: \_operation: , line:83:25, endln:83:27 |vpiOpType:1 @@ -2948,7 +2948,7 @@ design: (work@dut1) |vpiParamAssign: \_param_assign: , line:84:13, endln:84:45 |vpiParent: - \_module: work@dut5 (work@dut5), file:${SURELOG_DIR}/tests/Bindings/dut.sv, line:82:1, endln:108:10 + \_module_inst: work@dut5 (work@dut5), file:${SURELOG_DIR}/tests/Bindings/dut.sv, line:82:1, endln:108:10 |vpiRhs: \_sys_func_call: ($clog2), line:84:29, endln:84:45 |vpiArgument: @@ -2962,7 +2962,7 @@ design: (work@dut1) |vpiParamAssign: \_param_assign: , line:85:13, endln:85:25 |vpiParent: - \_module: work@dut5 (work@dut5), file:${SURELOG_DIR}/tests/Bindings/dut.sv, line:82:1, endln:108:10 + \_module_inst: work@dut5 (work@dut5), file:${SURELOG_DIR}/tests/Bindings/dut.sv, line:82:1, endln:108:10 |vpiRhs: \_operation: , line:85:23, endln:85:25 |vpiOpType:1 @@ -2977,7 +2977,7 @@ design: (work@dut1) |vpiParamAssign: \_param_assign: , line:86:17, endln:86:28 |vpiParent: - \_module: work@dut5 (work@dut5), file:${SURELOG_DIR}/tests/Bindings/dut.sv, line:82:1, endln:108:10 + \_module_inst: work@dut5 (work@dut5), file:${SURELOG_DIR}/tests/Bindings/dut.sv, line:82:1, endln:108:10 |vpiRhs: \_constant: , line:86:27, endln:86:28 |vpiDecompile:4 @@ -2991,7 +2991,7 @@ design: (work@dut1) |vpiParamAssign: \_param_assign: , line:94:22, endln:94:41 |vpiParent: - \_module: work@dut5 (work@dut5), file:${SURELOG_DIR}/tests/Bindings/dut.sv, line:82:1, endln:108:10 + \_module_inst: work@dut5 (work@dut5), file:${SURELOG_DIR}/tests/Bindings/dut.sv, line:82:1, endln:108:10 |vpiRhs: \_ref_obj: (Off), line:94:38, endln:94:41 |vpiName:Off @@ -3007,17 +3007,17 @@ design: (work@dut1) |vpiNet: \_logic_net: (work@dut5.shifted), line:96:23, endln:96:30 |vpiParent: - \_module: work@dut5 (work@dut5), file:${SURELOG_DIR}/tests/Bindings/dut.sv, line:82:1, endln:108:10 + \_module_inst: work@dut5 (work@dut5), file:${SURELOG_DIR}/tests/Bindings/dut.sv, line:82:1, endln:108:10 |vpiName:shifted |vpiFullName:work@dut5.shifted |vpiNetType:1 |uhdmtopModules: -\_module: work@dut1 (work@dut1), file:${SURELOG_DIR}/tests/Bindings/dut.sv, line:20:1, endln:31:10 +\_module_inst: work@dut1 (work@dut1), file:${SURELOG_DIR}/tests/Bindings/dut.sv, line:20:1, endln:31:10 |vpiName:work@dut1 |vpiVariables: \_logic_var: (work@dut1.device_sel_req), line:25:32, endln:25:46 |vpiParent: - \_module: work@dut1 (work@dut1), file:${SURELOG_DIR}/tests/Bindings/dut.sv, line:20:1, endln:31:10 + \_module_inst: work@dut1 (work@dut1), file:${SURELOG_DIR}/tests/Bindings/dut.sv, line:20:1, endln:31:10 |vpiTypespec: \_logic_typespec: , line:25:3, endln:25:31 |vpiRange: @@ -3062,7 +3062,7 @@ design: (work@dut1) |vpiVariables: \_int_var: (work@dut1.device), line:26:7, endln:26:17 |vpiParent: - \_module: work@dut1 (work@dut1), file:${SURELOG_DIR}/tests/Bindings/dut.sv, line:20:1, endln:31:10 + \_module_inst: work@dut1 (work@dut1), file:${SURELOG_DIR}/tests/Bindings/dut.sv, line:20:1, endln:31:10 |vpiTypespec: \_int_typespec: , line:26:3, endln:26:6 |vpiSigned:1 @@ -3078,7 +3078,7 @@ design: (work@dut1) |vpiParameter: \_parameter: (work@dut1.NrDevices), line:21:17, endln:21:26 |vpiParent: - \_module: work@dut1 (work@dut1), file:${SURELOG_DIR}/tests/Bindings/dut.sv, line:20:1, endln:31:10 + \_module_inst: work@dut1 (work@dut1), file:${SURELOG_DIR}/tests/Bindings/dut.sv, line:20:1, endln:31:10 |UINT:1 |vpiTypespec: \_int_typespec: , line:21:13, endln:21:16 @@ -3091,7 +3091,7 @@ design: (work@dut1) |vpiParameter: \_parameter: (work@dut1.NumBitsDeviceSel), line:24:27, endln:24:43 |vpiParent: - \_module: work@dut1 (work@dut1), file:${SURELOG_DIR}/tests/Bindings/dut.sv, line:20:1, endln:31:10 + \_module_inst: work@dut1 (work@dut1), file:${SURELOG_DIR}/tests/Bindings/dut.sv, line:20:1, endln:31:10 |vpiTypespec: \_int_typespec: , line:24:14, endln:24:26 |vpiParent: @@ -3104,7 +3104,7 @@ design: (work@dut1) |vpiParamAssign: \_param_assign: , line:21:17, endln:21:30 |vpiParent: - \_module: work@dut1 (work@dut1), file:${SURELOG_DIR}/tests/Bindings/dut.sv, line:20:1, endln:31:10 + \_module_inst: work@dut1 (work@dut1), file:${SURELOG_DIR}/tests/Bindings/dut.sv, line:20:1, endln:31:10 |vpiRhs: \_constant: , line:21:29, endln:21:30 |vpiDecompile:1 @@ -3118,7 +3118,7 @@ design: (work@dut1) |vpiParamAssign: \_param_assign: , line:24:27, endln:24:83 |vpiParent: - \_module: work@dut1 (work@dut1), file:${SURELOG_DIR}/tests/Bindings/dut.sv, line:20:1, endln:31:10 + \_module_inst: work@dut1 (work@dut1), file:${SURELOG_DIR}/tests/Bindings/dut.sv, line:20:1, endln:31:10 |vpiRhs: \_constant: , line:24:46, endln:24:83 |vpiDecompile:1 @@ -3135,7 +3135,7 @@ design: (work@dut1) |vpiProcess: \_always: , line:27:3, endln:29:6 |vpiParent: - \_module: work@dut1 (work@dut1), file:${SURELOG_DIR}/tests/Bindings/dut.sv, line:20:1, endln:31:10 + \_module_inst: work@dut1 (work@dut1), file:${SURELOG_DIR}/tests/Bindings/dut.sv, line:20:1, endln:31:10 |vpiStmt: \_begin: (work@dut1), line:27:15, endln:29:6 |vpiParent: @@ -3172,12 +3172,12 @@ design: (work@dut1) \_logic_var: (work@dut1.device_sel_req), line:25:32, endln:25:46 |vpiAlwaysType:2 |uhdmtopModules: -\_module: work@dut2 (work@dut2), file:${SURELOG_DIR}/tests/Bindings/dut.sv, line:35:1, endln:50:10 +\_module_inst: work@dut2 (work@dut2), file:${SURELOG_DIR}/tests/Bindings/dut.sv, line:35:1, endln:50:10 |vpiName:work@dut2 |vpiParameter: \_parameter: (work@dut2.num_out_p), line:35:25, endln:35:34 |vpiParent: - \_module: work@dut2 (work@dut2), file:${SURELOG_DIR}/tests/Bindings/dut.sv, line:35:1, endln:50:10 + \_module_inst: work@dut2 (work@dut2), file:${SURELOG_DIR}/tests/Bindings/dut.sv, line:35:1, endln:50:10 |STRING:inv |vpiTypespec: \_string_typespec: @@ -3188,7 +3188,7 @@ design: (work@dut1) |vpiParamAssign: \_param_assign: , line:35:25, endln:35:40 |vpiParent: - \_module: work@dut2 (work@dut2), file:${SURELOG_DIR}/tests/Bindings/dut.sv, line:35:1, endln:50:10 + \_module_inst: work@dut2 (work@dut2), file:${SURELOG_DIR}/tests/Bindings/dut.sv, line:35:1, endln:50:10 |vpiRhs: \_constant: , line:35:35, endln:35:40 |vpiDecompile:inv @@ -3204,7 +3204,7 @@ design: (work@dut1) |vpiNet: \_logic_net: (work@dut2.i), line:37:36, endln:37:37 |vpiParent: - \_module: work@dut2 (work@dut2), file:${SURELOG_DIR}/tests/Bindings/dut.sv, line:35:1, endln:50:10 + \_module_inst: work@dut2 (work@dut2), file:${SURELOG_DIR}/tests/Bindings/dut.sv, line:35:1, endln:50:10 |vpiTypespec: \_logic_typespec: , line:37:12, endln:37:35 |vpiRange: @@ -3230,7 +3230,7 @@ design: (work@dut1) |vpiNet: \_logic_net: (work@dut2.o), line:38:36, endln:38:37 |vpiParent: - \_module: work@dut2 (work@dut2), file:${SURELOG_DIR}/tests/Bindings/dut.sv, line:35:1, endln:50:10 + \_module_inst: work@dut2 (work@dut2), file:${SURELOG_DIR}/tests/Bindings/dut.sv, line:35:1, endln:50:10 |vpiTypespec: \_logic_typespec: , line:38:14, endln:38:35 |vpiRange: @@ -3258,7 +3258,7 @@ design: (work@dut1) |vpiPort: \_port: (i), line:37:36, endln:37:37 |vpiParent: - \_module: work@dut2 (work@dut2), file:${SURELOG_DIR}/tests/Bindings/dut.sv, line:35:1, endln:50:10 + \_module_inst: work@dut2 (work@dut2), file:${SURELOG_DIR}/tests/Bindings/dut.sv, line:35:1, endln:50:10 |vpiName:i |vpiDirection:1 |vpiLowConn: @@ -3292,11 +3292,11 @@ design: (work@dut1) |UINT:0 |vpiConstType:9 |vpiInstance: - \_module: work@dut2 (work@dut2), file:${SURELOG_DIR}/tests/Bindings/dut.sv, line:35:1, endln:50:10 + \_module_inst: work@dut2 (work@dut2), file:${SURELOG_DIR}/tests/Bindings/dut.sv, line:35:1, endln:50:10 |vpiPort: \_port: (o), line:38:36, endln:38:37 |vpiParent: - \_module: work@dut2 (work@dut2), file:${SURELOG_DIR}/tests/Bindings/dut.sv, line:35:1, endln:50:10 + \_module_inst: work@dut2 (work@dut2), file:${SURELOG_DIR}/tests/Bindings/dut.sv, line:35:1, endln:50:10 |vpiName:o |vpiDirection:2 |vpiLowConn: @@ -3330,11 +3330,11 @@ design: (work@dut1) |UINT:0 |vpiConstType:9 |vpiInstance: - \_module: work@dut2 (work@dut2), file:${SURELOG_DIR}/tests/Bindings/dut.sv, line:35:1, endln:50:10 + \_module_inst: work@dut2 (work@dut2), file:${SURELOG_DIR}/tests/Bindings/dut.sv, line:35:1, endln:50:10 |vpiGenScopeArray: \_gen_scope_array: (work@dut2.genblk1), line:46:9, endln:48:9 |vpiParent: - \_module: work@dut2 (work@dut2), file:${SURELOG_DIR}/tests/Bindings/dut.sv, line:35:1, endln:50:10 + \_module_inst: work@dut2 (work@dut2), file:${SURELOG_DIR}/tests/Bindings/dut.sv, line:35:1, endln:50:10 |vpiName:genblk1 |vpiFullName:work@dut2.genblk1 |vpiGenScope: @@ -3386,12 +3386,12 @@ design: (work@dut1) |vpiActual: \_logic_net: (work@dut2.o), line:38:36, endln:38:37 |uhdmtopModules: -\_module: work@dut3 (work@dut3), file:${SURELOG_DIR}/tests/Bindings/dut.sv, line:54:1, endln:64:10 +\_module_inst: work@dut3 (work@dut3), file:${SURELOG_DIR}/tests/Bindings/dut.sv, line:54:1, endln:64:10 |vpiName:work@dut3 |vpiParameter: \_parameter: (work@dut3.LfsrDw), line:54:45, endln:54:51 |vpiParent: - \_module: work@dut3 (work@dut3), file:${SURELOG_DIR}/tests/Bindings/dut.sv, line:54:1, endln:64:10 + \_module_inst: work@dut3 (work@dut3), file:${SURELOG_DIR}/tests/Bindings/dut.sv, line:54:1, endln:64:10 |UINT:3 |vpiTypespec: \_int_typespec: , line:54:26, endln:54:38 @@ -3402,7 +3402,7 @@ design: (work@dut1) |vpiParamAssign: \_param_assign: , line:54:45, endln:54:61 |vpiParent: - \_module: work@dut3 (work@dut3), file:${SURELOG_DIR}/tests/Bindings/dut.sv, line:54:1, endln:64:10 + \_module_inst: work@dut3 (work@dut3), file:${SURELOG_DIR}/tests/Bindings/dut.sv, line:54:1, endln:64:10 |vpiRhs: \_constant: , line:54:60, endln:54:61 |vpiDecompile:3 @@ -3436,16 +3436,16 @@ design: (work@dut1) |vpiName:lockup |vpiNetType:1 |vpiTopModule:1 - |vpiModule: - \_module: work@bsg_dff_reset (work@dut3.a1), file:${SURELOG_DIR}/tests/Bindings/dut.sv, line:56:3, endln:56:37 + |vpiModuleInst: + \_module_inst: work@bsg_dff_reset (work@dut3.a1), file:${SURELOG_DIR}/tests/Bindings/dut.sv, line:56:3, endln:56:37 |vpiParent: - \_module: work@dut3 (work@dut3), file:${SURELOG_DIR}/tests/Bindings/dut.sv, line:54:1, endln:64:10 + \_module_inst: work@dut3 (work@dut3), file:${SURELOG_DIR}/tests/Bindings/dut.sv, line:54:1, endln:64:10 |vpiName:a1 |vpiFullName:work@dut3.a1 |vpiParameter: \_parameter: (work@dut3.a1.width_p), line:67:25, endln:67:32 |vpiParent: - \_module: work@bsg_dff_reset (work@dut3.a1), file:${SURELOG_DIR}/tests/Bindings/dut.sv, line:56:3, endln:56:37 + \_module_inst: work@bsg_dff_reset (work@dut3.a1), file:${SURELOG_DIR}/tests/Bindings/dut.sv, line:56:3, endln:56:37 |vpiTypespec: \_int_typespec: (width_p), line:75:22, endln:75:29 |vpiParent: @@ -3458,7 +3458,7 @@ design: (work@dut1) |vpiParameter: \_parameter: (work@dut3.a1.reset_val_p), line:67:37, endln:67:48 |vpiParent: - \_module: work@bsg_dff_reset (work@dut3.a1), file:${SURELOG_DIR}/tests/Bindings/dut.sv, line:56:3, endln:56:37 + \_module_inst: work@bsg_dff_reset (work@dut3.a1), file:${SURELOG_DIR}/tests/Bindings/dut.sv, line:56:3, endln:56:37 |UINT:0 |vpiTypespec: \_int_typespec: @@ -3469,7 +3469,7 @@ design: (work@dut1) |vpiParameter: \_parameter: (work@dut3.a1.harden_p), line:67:52, endln:67:60 |vpiParent: - \_module: work@bsg_dff_reset (work@dut3.a1), file:${SURELOG_DIR}/tests/Bindings/dut.sv, line:56:3, endln:56:37 + \_module_inst: work@bsg_dff_reset (work@dut3.a1), file:${SURELOG_DIR}/tests/Bindings/dut.sv, line:56:3, endln:56:37 |UINT:0 |vpiTypespec: \_int_typespec: @@ -3480,7 +3480,7 @@ design: (work@dut1) |vpiParamAssign: \_param_assign: , line:67:25, endln:67:35 |vpiParent: - \_module: work@bsg_dff_reset (work@dut3.a1), file:${SURELOG_DIR}/tests/Bindings/dut.sv, line:56:3, endln:56:37 + \_module_inst: work@bsg_dff_reset (work@dut3.a1), file:${SURELOG_DIR}/tests/Bindings/dut.sv, line:56:3, endln:56:37 |vpiOverriden:1 |vpiRhs: \_constant: , line:67:33, endln:67:35 @@ -3495,7 +3495,7 @@ design: (work@dut1) |vpiParamAssign: \_param_assign: , line:67:37, endln:67:50 |vpiParent: - \_module: work@bsg_dff_reset (work@dut3.a1), file:${SURELOG_DIR}/tests/Bindings/dut.sv, line:56:3, endln:56:37 + \_module_inst: work@bsg_dff_reset (work@dut3.a1), file:${SURELOG_DIR}/tests/Bindings/dut.sv, line:56:3, endln:56:37 |vpiRhs: \_constant: , line:67:49, endln:67:50 |vpiDecompile:0 @@ -3509,7 +3509,7 @@ design: (work@dut1) |vpiParamAssign: \_param_assign: , line:67:52, endln:67:62 |vpiParent: - \_module: work@bsg_dff_reset (work@dut3.a1), file:${SURELOG_DIR}/tests/Bindings/dut.sv, line:56:3, endln:56:37 + \_module_inst: work@bsg_dff_reset (work@dut3.a1), file:${SURELOG_DIR}/tests/Bindings/dut.sv, line:56:3, endln:56:37 |vpiRhs: \_constant: , line:67:61, endln:67:62 |vpiDecompile:0 @@ -3540,11 +3540,11 @@ design: (work@dut1) |vpiName:data_i |vpiNetType:1 |vpiInstance: - \_module: work@dut3 (work@dut3), file:${SURELOG_DIR}/tests/Bindings/dut.sv, line:54:1, endln:64:10 + \_module_inst: work@dut3 (work@dut3), file:${SURELOG_DIR}/tests/Bindings/dut.sv, line:54:1, endln:64:10 |vpiProcess: \_always: , line:72:4, endln:78:9 |vpiParent: - \_module: work@bsg_dff_reset (work@dut3.a1), file:${SURELOG_DIR}/tests/Bindings/dut.sv, line:56:3, endln:56:37 + \_module_inst: work@bsg_dff_reset (work@dut3.a1), file:${SURELOG_DIR}/tests/Bindings/dut.sv, line:56:3, endln:56:37 |vpiStmt: \_event_control: , line:72:11, endln:72:27 |vpiParent: @@ -3629,16 +3629,16 @@ design: (work@dut1) |vpiActual: \_logic_net: (data_r) |vpiAlwaysType:1 - |vpiModule: - \_module: work@bsg_dff_reset (work@dut3.a2), file:${SURELOG_DIR}/tests/Bindings/dut.sv, line:58:3, endln:58:22 + |vpiModuleInst: + \_module_inst: work@bsg_dff_reset (work@dut3.a2), file:${SURELOG_DIR}/tests/Bindings/dut.sv, line:58:3, endln:58:22 |vpiParent: - \_module: work@dut3 (work@dut3), file:${SURELOG_DIR}/tests/Bindings/dut.sv, line:54:1, endln:64:10 + \_module_inst: work@dut3 (work@dut3), file:${SURELOG_DIR}/tests/Bindings/dut.sv, line:54:1, endln:64:10 |vpiName:a2 |vpiFullName:work@dut3.a2 |vpiParameter: \_parameter: (work@dut3.a2.width_p), line:67:25, endln:67:32 |vpiParent: - \_module: work@bsg_dff_reset (work@dut3.a2), file:${SURELOG_DIR}/tests/Bindings/dut.sv, line:58:3, endln:58:22 + \_module_inst: work@bsg_dff_reset (work@dut3.a2), file:${SURELOG_DIR}/tests/Bindings/dut.sv, line:58:3, endln:58:22 |vpiTypespec: \_int_typespec: (width_p), line:75:22, endln:75:29 |vpiParent: @@ -3651,7 +3651,7 @@ design: (work@dut1) |vpiParameter: \_parameter: (work@dut3.a2.reset_val_p), line:67:37, endln:67:48 |vpiParent: - \_module: work@bsg_dff_reset (work@dut3.a2), file:${SURELOG_DIR}/tests/Bindings/dut.sv, line:58:3, endln:58:22 + \_module_inst: work@bsg_dff_reset (work@dut3.a2), file:${SURELOG_DIR}/tests/Bindings/dut.sv, line:58:3, endln:58:22 |UINT:0 |vpiTypespec: \_int_typespec: @@ -3662,7 +3662,7 @@ design: (work@dut1) |vpiParameter: \_parameter: (work@dut3.a2.harden_p), line:67:52, endln:67:60 |vpiParent: - \_module: work@bsg_dff_reset (work@dut3.a2), file:${SURELOG_DIR}/tests/Bindings/dut.sv, line:58:3, endln:58:22 + \_module_inst: work@bsg_dff_reset (work@dut3.a2), file:${SURELOG_DIR}/tests/Bindings/dut.sv, line:58:3, endln:58:22 |UINT:0 |vpiTypespec: \_int_typespec: @@ -3673,7 +3673,7 @@ design: (work@dut1) |vpiParamAssign: \_param_assign: , line:67:25, endln:67:35 |vpiParent: - \_module: work@bsg_dff_reset (work@dut3.a2), file:${SURELOG_DIR}/tests/Bindings/dut.sv, line:58:3, endln:58:22 + \_module_inst: work@bsg_dff_reset (work@dut3.a2), file:${SURELOG_DIR}/tests/Bindings/dut.sv, line:58:3, endln:58:22 |vpiRhs: \_constant: , line:67:33, endln:67:35 |vpiDecompile:-1 @@ -3687,7 +3687,7 @@ design: (work@dut1) |vpiParamAssign: \_param_assign: , line:67:37, endln:67:50 |vpiParent: - \_module: work@bsg_dff_reset (work@dut3.a2), file:${SURELOG_DIR}/tests/Bindings/dut.sv, line:58:3, endln:58:22 + \_module_inst: work@bsg_dff_reset (work@dut3.a2), file:${SURELOG_DIR}/tests/Bindings/dut.sv, line:58:3, endln:58:22 |vpiRhs: \_constant: , line:67:49, endln:67:50 |vpiDecompile:0 @@ -3701,7 +3701,7 @@ design: (work@dut1) |vpiParamAssign: \_param_assign: , line:67:52, endln:67:62 |vpiParent: - \_module: work@bsg_dff_reset (work@dut3.a2), file:${SURELOG_DIR}/tests/Bindings/dut.sv, line:58:3, endln:58:22 + \_module_inst: work@bsg_dff_reset (work@dut3.a2), file:${SURELOG_DIR}/tests/Bindings/dut.sv, line:58:3, endln:58:22 |vpiRhs: \_constant: , line:67:61, endln:67:62 |vpiDecompile:0 @@ -3716,11 +3716,11 @@ design: (work@dut1) |vpiDefFile:${SURELOG_DIR}/tests/Bindings/dut.sv |vpiDefLineNo:67 |vpiInstance: - \_module: work@dut3 (work@dut3), file:${SURELOG_DIR}/tests/Bindings/dut.sv, line:54:1, endln:64:10 + \_module_inst: work@dut3 (work@dut3), file:${SURELOG_DIR}/tests/Bindings/dut.sv, line:54:1, endln:64:10 |vpiProcess: \_always: , line:72:4, endln:78:9 |vpiParent: - \_module: work@bsg_dff_reset (work@dut3.a2), file:${SURELOG_DIR}/tests/Bindings/dut.sv, line:58:3, endln:58:22 + \_module_inst: work@bsg_dff_reset (work@dut3.a2), file:${SURELOG_DIR}/tests/Bindings/dut.sv, line:58:3, endln:58:22 |vpiStmt: \_event_control: , line:72:11, endln:72:27 |vpiParent: @@ -3808,7 +3808,7 @@ design: (work@dut1) |vpiContAssign: \_cont_assign: , line:60:10, endln:60:95 |vpiParent: - \_module: work@dut3 (work@dut3), file:${SURELOG_DIR}/tests/Bindings/dut.sv, line:54:1, endln:64:10 + \_module_inst: work@dut3 (work@dut3), file:${SURELOG_DIR}/tests/Bindings/dut.sv, line:54:1, endln:64:10 |vpiRhs: \_operation: , line:60:28, endln:60:95 |vpiParent: @@ -3906,7 +3906,7 @@ design: (work@dut1) |vpiContAssign: \_cont_assign: , line:62:9, endln:62:28 |vpiParent: - \_module: work@dut3 (work@dut3), file:${SURELOG_DIR}/tests/Bindings/dut.sv, line:54:1, endln:64:10 + \_module_inst: work@dut3 (work@dut3), file:${SURELOG_DIR}/tests/Bindings/dut.sv, line:54:1, endln:64:10 |vpiRhs: \_operation: , line:62:18, endln:62:28 |vpiParent: @@ -3934,30 +3934,30 @@ design: (work@dut1) |vpiActual: \_logic_net: (lockup) |uhdmtopModules: -\_module: work@dut5 (work@dut5), file:${SURELOG_DIR}/tests/Bindings/dut.sv, line:82:1, endln:108:10 +\_module_inst: work@dut5 (work@dut5), file:${SURELOG_DIR}/tests/Bindings/dut.sv, line:82:1, endln:108:10 |vpiName:work@dut5 |vpiParameter: \_parameter: (work@dut5.inputs_p), line:83:14, endln:83:22 |vpiParent: - \_module: work@dut5 (work@dut5), file:${SURELOG_DIR}/tests/Bindings/dut.sv, line:82:1, endln:108:10 + \_module_inst: work@dut5 (work@dut5), file:${SURELOG_DIR}/tests/Bindings/dut.sv, line:82:1, endln:108:10 |vpiName:inputs_p |vpiFullName:work@dut5.inputs_p |vpiParameter: \_parameter: (work@dut5.lg_inputs_p), line:84:13, endln:84:24 |vpiParent: - \_module: work@dut5 (work@dut5), file:${SURELOG_DIR}/tests/Bindings/dut.sv, line:82:1, endln:108:10 + \_module_inst: work@dut5 (work@dut5), file:${SURELOG_DIR}/tests/Bindings/dut.sv, line:82:1, endln:108:10 |vpiName:lg_inputs_p |vpiFullName:work@dut5.lg_inputs_p |vpiParameter: \_parameter: (work@dut5.width_p), line:85:13, endln:85:20 |vpiParent: - \_module: work@dut5 (work@dut5), file:${SURELOG_DIR}/tests/Bindings/dut.sv, line:82:1, endln:108:10 + \_module_inst: work@dut5 (work@dut5), file:${SURELOG_DIR}/tests/Bindings/dut.sv, line:82:1, endln:108:10 |vpiName:width_p |vpiFullName:work@dut5.width_p |vpiParameter: \_parameter: (work@dut5.TxWidth), line:86:17, endln:86:24 |vpiParent: - \_module: work@dut5 (work@dut5), file:${SURELOG_DIR}/tests/Bindings/dut.sv, line:82:1, endln:108:10 + \_module_inst: work@dut5 (work@dut5), file:${SURELOG_DIR}/tests/Bindings/dut.sv, line:82:1, endln:108:10 |UINT:4 |vpiTypespec: \_int_typespec: , line:86:13, endln:86:16 @@ -3970,7 +3970,7 @@ design: (work@dut1) |vpiParameter: \_parameter: (work@dut5.LC_TX_DEFAULT), line:94:22, endln:94:35 |vpiParent: - \_module: work@dut5 (work@dut5), file:${SURELOG_DIR}/tests/Bindings/dut.sv, line:82:1, endln:108:10 + \_module_inst: work@dut5 (work@dut5), file:${SURELOG_DIR}/tests/Bindings/dut.sv, line:82:1, endln:108:10 |vpiTypespec: \_enum_typespec: (lc_tx_t), line:87:5, endln:90:15 |vpiParent: @@ -3982,7 +3982,7 @@ design: (work@dut1) \_enum_typespec: (lc_tx_t), line:87:5, endln:90:15 |vpiName:lc_tx_e |vpiInstance: - \_module: work@dut5 (work@dut5), file:${SURELOG_DIR}/tests/Bindings/dut.sv, line:82:1, endln:108:10 + \_module_inst: work@dut5 (work@dut5), file:${SURELOG_DIR}/tests/Bindings/dut.sv, line:82:1, endln:108:10 |vpiBaseTypespec: \_logic_typespec: , line:87:18, endln:87:37 |vpiParent: @@ -4037,7 +4037,7 @@ design: (work@dut1) |vpiDecompile:4'b0101 |vpiSize:4 |vpiInstance: - \_module: work@dut5 (work@dut5), file:${SURELOG_DIR}/tests/Bindings/dut.sv, line:82:1, endln:108:10 + \_module_inst: work@dut5 (work@dut5), file:${SURELOG_DIR}/tests/Bindings/dut.sv, line:82:1, endln:108:10 |vpiBaseTypespec: \_logic_typespec: , line:87:18, endln:87:37 |vpiParent: @@ -4096,7 +4096,7 @@ design: (work@dut1) |vpiParamAssign: \_param_assign: , line:83:14, endln:83:27 |vpiParent: - \_module: work@dut5 (work@dut5), file:${SURELOG_DIR}/tests/Bindings/dut.sv, line:82:1, endln:108:10 + \_module_inst: work@dut5 (work@dut5), file:${SURELOG_DIR}/tests/Bindings/dut.sv, line:82:1, endln:108:10 |vpiRhs: \_constant: , line:83:25, endln:83:27 |vpiDecompile:-1 @@ -4108,7 +4108,7 @@ design: (work@dut1) |vpiParamAssign: \_param_assign: , line:84:13, endln:84:45 |vpiParent: - \_module: work@dut5 (work@dut5), file:${SURELOG_DIR}/tests/Bindings/dut.sv, line:82:1, endln:108:10 + \_module_inst: work@dut5 (work@dut5), file:${SURELOG_DIR}/tests/Bindings/dut.sv, line:82:1, endln:108:10 |vpiRhs: \_constant: , line:84:29, endln:84:45 |vpiDecompile:0 @@ -4120,7 +4120,7 @@ design: (work@dut1) |vpiParamAssign: \_param_assign: , line:85:13, endln:85:25 |vpiParent: - \_module: work@dut5 (work@dut5), file:${SURELOG_DIR}/tests/Bindings/dut.sv, line:82:1, endln:108:10 + \_module_inst: work@dut5 (work@dut5), file:${SURELOG_DIR}/tests/Bindings/dut.sv, line:82:1, endln:108:10 |vpiRhs: \_constant: , line:85:23, endln:85:25 |vpiDecompile:-1 @@ -4132,7 +4132,7 @@ design: (work@dut1) |vpiParamAssign: \_param_assign: , line:86:17, endln:86:28 |vpiParent: - \_module: work@dut5 (work@dut5), file:${SURELOG_DIR}/tests/Bindings/dut.sv, line:82:1, endln:108:10 + \_module_inst: work@dut5 (work@dut5), file:${SURELOG_DIR}/tests/Bindings/dut.sv, line:82:1, endln:108:10 |vpiRhs: \_constant: , line:86:27, endln:86:28 |vpiDecompile:4 @@ -4146,7 +4146,7 @@ design: (work@dut1) |vpiParamAssign: \_param_assign: , line:94:22, endln:94:41 |vpiParent: - \_module: work@dut5 (work@dut5), file:${SURELOG_DIR}/tests/Bindings/dut.sv, line:82:1, endln:108:10 + \_module_inst: work@dut5 (work@dut5), file:${SURELOG_DIR}/tests/Bindings/dut.sv, line:82:1, endln:108:10 |vpiRhs: \_constant: , line:94:38, endln:94:41 |vpiDecompile:4'b0101 @@ -4166,7 +4166,7 @@ design: (work@dut1) |vpiNet: \_logic_net: (work@dut5.shifted), line:96:23, endln:96:30 |vpiParent: - \_module: work@dut5 (work@dut5), file:${SURELOG_DIR}/tests/Bindings/dut.sv, line:82:1, endln:108:10 + \_module_inst: work@dut5 (work@dut5), file:${SURELOG_DIR}/tests/Bindings/dut.sv, line:82:1, endln:108:10 |vpiTypespec: \_logic_typespec: , line:96:4, endln:96:22 |vpiRange: @@ -4206,7 +4206,7 @@ design: (work@dut1) |vpiContAssign: \_cont_assign: , line:96:23, endln:96:30 |vpiParent: - \_module: work@dut5 (work@dut5), file:${SURELOG_DIR}/tests/Bindings/dut.sv, line:82:1, endln:108:10 + \_module_inst: work@dut5 (work@dut5), file:${SURELOG_DIR}/tests/Bindings/dut.sv, line:82:1, endln:108:10 |vpiNetDeclAssign:1 |vpiRhs: \_operation: , line:96:33, endln:96:69 diff --git a/tests/BitComplex/BitComplex.log b/tests/BitComplex/BitComplex.log index 6defcd4a04..36c6cf464d 100644 --- a/tests/BitComplex/BitComplex.log +++ b/tests/BitComplex/BitComplex.log @@ -209,7 +209,7 @@ int_typespec 15 int_var 1 logic_net 2 logic_typespec 5 -module 8 +module_inst 8 operation 4 package 3 param_assign 10 @@ -233,7 +233,7 @@ int_typespec 15 int_var 1 logic_net 2 logic_typespec 5 -module 8 +module_inst 8 operation 4 package 3 param_assign 10 @@ -543,14 +543,14 @@ design: (work@top) |vpiDefName:keymgr_pkg |vpiTop:1 |uhdmallModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/BitComplex/dut.sv, line:10:1, endln:14:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/BitComplex/dut.sv, line:10:1, endln:14:10 |vpiParent: \_design: (work@top) |vpiFullName:work@top |vpiParameter: \_parameter: (work@top.PP), line:12:14, endln:12:16 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/BitComplex/dut.sv, line:10:1, endln:14:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/BitComplex/dut.sv, line:10:1, endln:14:10 |UINT:16 |vpiTypespec: \_int_typespec: @@ -559,7 +559,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:12:14, endln:12:46 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/BitComplex/dut.sv, line:10:1, endln:14:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/BitComplex/dut.sv, line:10:1, endln:14:10 |vpiRhs: \_constant: , line:12:20, endln:12:46 |vpiDecompile:16 @@ -574,20 +574,20 @@ design: (work@top) |vpiNet: \_logic_net: (work@top.o), line:10:23, endln:10:24 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/BitComplex/dut.sv, line:10:1, endln:14:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/BitComplex/dut.sv, line:10:1, endln:14:10 |vpiName:o |vpiFullName:work@top.o |vpiNet: \_logic_net: (work@top.keymgr_key_i), line:11:29, endln:11:41 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/BitComplex/dut.sv, line:10:1, endln:14:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/BitComplex/dut.sv, line:10:1, endln:14:10 |vpiName:keymgr_key_i |vpiFullName:work@top.keymgr_key_i |vpiNetType:1 |vpiPort: \_port: (o), line:10:23, endln:10:24 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/BitComplex/dut.sv, line:10:1, endln:14:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/BitComplex/dut.sv, line:10:1, endln:14:10 |vpiName:o |vpiDirection:2 |vpiLowConn: @@ -600,7 +600,7 @@ design: (work@top) |vpiContAssign: \_cont_assign: , line:13:11, endln:13:41 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/BitComplex/dut.sv, line:10:1, endln:14:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/BitComplex/dut.sv, line:10:1, endln:14:10 |vpiRhs: \_constant: , line:13:15, endln:13:41 |vpiParent: @@ -618,12 +618,12 @@ design: (work@top) |vpiActual: \_int_var: (work@top.o), line:10:23, endln:10:24 |uhdmtopModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/BitComplex/dut.sv, line:10:1, endln:14:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/BitComplex/dut.sv, line:10:1, endln:14:10 |vpiName:work@top |vpiVariables: \_int_var: (work@top.o), line:10:23, endln:10:24 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/BitComplex/dut.sv, line:10:1, endln:14:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/BitComplex/dut.sv, line:10:1, endln:14:10 |vpiTypespec: \_int_typespec: , line:10:19, endln:10:22 |vpiSigned:1 @@ -634,7 +634,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.PP), line:12:14, endln:12:16 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/BitComplex/dut.sv, line:10:1, endln:14:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/BitComplex/dut.sv, line:10:1, endln:14:10 |UINT:16 |vpiTypespec: \_int_typespec: @@ -645,7 +645,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:12:14, endln:12:46 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/BitComplex/dut.sv, line:10:1, endln:14:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/BitComplex/dut.sv, line:10:1, endln:14:10 |vpiRhs: \_constant: , line:12:20, endln:12:46 |vpiDecompile:16 @@ -661,7 +661,7 @@ design: (work@top) |vpiNet: \_struct_net: (work@top.keymgr_key_i), line:11:29, endln:11:41 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/BitComplex/dut.sv, line:10:1, endln:14:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/BitComplex/dut.sv, line:10:1, endln:14:10 |vpiTypespec: \_struct_typespec: (keymgr_pkg::hw_key_req_t), line:5:12, endln:5:18 |vpiName:keymgr_key_i @@ -671,7 +671,7 @@ design: (work@top) |vpiPort: \_port: (o), line:10:23, endln:10:24 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/BitComplex/dut.sv, line:10:1, endln:14:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/BitComplex/dut.sv, line:10:1, endln:14:10 |vpiName:o |vpiDirection:2 |vpiLowConn: @@ -686,11 +686,11 @@ design: (work@top) \_int_typespec: , line:10:19, endln:10:22 |vpiSigned:1 |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/BitComplex/dut.sv, line:10:1, endln:14:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/BitComplex/dut.sv, line:10:1, endln:14:10 |vpiContAssign: \_cont_assign: , line:13:11, endln:13:41 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/BitComplex/dut.sv, line:10:1, endln:14:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/BitComplex/dut.sv, line:10:1, endln:14:10 |vpiRhs: \_constant: , line:13:15, endln:13:41 |vpiParent: diff --git a/tests/BitPartSelect/BitPartSelect.log b/tests/BitPartSelect/BitPartSelect.log index e95099409b..010a7580ee 100644 --- a/tests/BitPartSelect/BitPartSelect.log +++ b/tests/BitPartSelect/BitPartSelect.log @@ -245,7 +245,7 @@ int_typespec 6 logic_net 3 logic_typespec 3 logic_var 3 -module 6 +module_inst 6 operation 9 param_assign 6 parameter 6 @@ -264,7 +264,7 @@ int_typespec 6 logic_net 3 logic_typespec 3 logic_var 3 -module 6 +module_inst 6 operation 10 param_assign 6 parameter 6 @@ -285,14 +285,14 @@ design: (work@top) |vpiElaborated:1 |vpiName:work@top |uhdmallModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/BitPartSelect/dut.sv, line:1:1, endln:10:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/BitPartSelect/dut.sv, line:1:1, endln:10:10 |vpiParent: \_design: (work@top) |vpiFullName:work@top |vpiParameter: \_parameter: (work@top.Width), line:2:27, endln:2:32 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/BitPartSelect/dut.sv, line:1:1, endln:10:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/BitPartSelect/dut.sv, line:1:1, endln:10:10 |UINT:16 |vpiTypespec: \_int_typespec: , line:2:14, endln:2:26 @@ -303,7 +303,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.Depth), line:3:27, endln:3:32 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/BitPartSelect/dut.sv, line:1:1, endln:10:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/BitPartSelect/dut.sv, line:1:1, endln:10:10 |UINT:4 |vpiTypespec: \_int_typespec: , line:3:14, endln:3:26 @@ -314,7 +314,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.PTR_WIDTH), line:4:28, endln:4:37 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/BitPartSelect/dut.sv, line:1:1, endln:10:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/BitPartSelect/dut.sv, line:1:1, endln:10:10 |UINT:2 |vpiTypespec: \_int_typespec: , line:4:15, endln:4:27 @@ -326,7 +326,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:2:27, endln:2:43 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/BitPartSelect/dut.sv, line:1:1, endln:10:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/BitPartSelect/dut.sv, line:1:1, endln:10:10 |vpiRhs: \_constant: , line:2:41, endln:2:43 |vpiDecompile:16 @@ -340,7 +340,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:3:27, endln:3:41 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/BitPartSelect/dut.sv, line:1:1, endln:10:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/BitPartSelect/dut.sv, line:1:1, endln:10:10 |vpiRhs: \_constant: , line:3:40, endln:3:41 |vpiDecompile:4 @@ -354,7 +354,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:4:28, endln:4:41 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/BitPartSelect/dut.sv, line:1:1, endln:10:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/BitPartSelect/dut.sv, line:1:1, endln:10:10 |vpiRhs: \_constant: , line:4:40, endln:4:41 |vpiDecompile:2 @@ -369,28 +369,28 @@ design: (work@top) |vpiNet: \_logic_net: (work@top.storage), line:5:33, endln:5:40 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/BitPartSelect/dut.sv, line:1:1, endln:10:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/BitPartSelect/dut.sv, line:1:1, endln:10:10 |vpiName:storage |vpiFullName:work@top.storage |vpiNetType:36 |vpiNet: \_logic_net: (work@top.storage_rdata), line:6:22, endln:6:35 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/BitPartSelect/dut.sv, line:1:1, endln:10:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/BitPartSelect/dut.sv, line:1:1, endln:10:10 |vpiName:storage_rdata |vpiFullName:work@top.storage_rdata |vpiNetType:36 |vpiNet: \_logic_net: (work@top.fifo_rptr), line:7:25, endln:7:34 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/BitPartSelect/dut.sv, line:1:1, endln:10:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/BitPartSelect/dut.sv, line:1:1, endln:10:10 |vpiName:fifo_rptr |vpiFullName:work@top.fifo_rptr |vpiNetType:36 |vpiContAssign: \_cont_assign: , line:9:11, endln:9:60 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/BitPartSelect/dut.sv, line:1:1, endln:10:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/BitPartSelect/dut.sv, line:1:1, endln:10:10 |vpiRhs: \_bit_select: (work@top.storage), line:9:27, endln:9:60 |vpiParent: @@ -439,12 +439,12 @@ design: (work@top) |vpiActual: \_logic_var: (work@top.storage_rdata), line:6:22, endln:6:35 |uhdmtopModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/BitPartSelect/dut.sv, line:1:1, endln:10:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/BitPartSelect/dut.sv, line:1:1, endln:10:10 |vpiName:work@top |vpiVariables: \_logic_var: (work@top.storage), line:5:33, endln:5:40 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/BitPartSelect/dut.sv, line:1:1, endln:10:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/BitPartSelect/dut.sv, line:1:1, endln:10:10 |vpiTypespec: \_logic_typespec: , line:5:4, endln:5:32 |vpiRange: @@ -525,7 +525,7 @@ design: (work@top) |vpiVariables: \_logic_var: (work@top.storage_rdata), line:6:22, endln:6:35 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/BitPartSelect/dut.sv, line:1:1, endln:10:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/BitPartSelect/dut.sv, line:1:1, endln:10:10 |vpiTypespec: \_logic_typespec: , line:6:4, endln:6:21 |vpiRange: @@ -570,7 +570,7 @@ design: (work@top) |vpiVariables: \_logic_var: (work@top.fifo_rptr), line:7:25, endln:7:34 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/BitPartSelect/dut.sv, line:1:1, endln:10:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/BitPartSelect/dut.sv, line:1:1, endln:10:10 |vpiTypespec: \_logic_typespec: , line:7:3, endln:7:24 |vpiRange: @@ -615,7 +615,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.Width), line:2:27, endln:2:32 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/BitPartSelect/dut.sv, line:1:1, endln:10:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/BitPartSelect/dut.sv, line:1:1, endln:10:10 |UINT:16 |vpiTypespec: \_int_typespec: , line:2:14, endln:2:26 @@ -626,7 +626,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.Depth), line:3:27, endln:3:32 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/BitPartSelect/dut.sv, line:1:1, endln:10:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/BitPartSelect/dut.sv, line:1:1, endln:10:10 |UINT:4 |vpiTypespec: \_int_typespec: , line:3:14, endln:3:26 @@ -637,7 +637,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.PTR_WIDTH), line:4:28, endln:4:37 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/BitPartSelect/dut.sv, line:1:1, endln:10:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/BitPartSelect/dut.sv, line:1:1, endln:10:10 |UINT:2 |vpiTypespec: \_int_typespec: , line:4:15, endln:4:27 @@ -649,7 +649,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:2:27, endln:2:43 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/BitPartSelect/dut.sv, line:1:1, endln:10:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/BitPartSelect/dut.sv, line:1:1, endln:10:10 |vpiRhs: \_constant: , line:2:41, endln:2:43 |vpiDecompile:16 @@ -663,7 +663,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:3:27, endln:3:41 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/BitPartSelect/dut.sv, line:1:1, endln:10:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/BitPartSelect/dut.sv, line:1:1, endln:10:10 |vpiRhs: \_constant: , line:3:40, endln:3:41 |vpiDecompile:4 @@ -677,7 +677,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:4:28, endln:4:41 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/BitPartSelect/dut.sv, line:1:1, endln:10:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/BitPartSelect/dut.sv, line:1:1, endln:10:10 |vpiRhs: \_constant: , line:4:40, endln:4:41 |vpiDecompile:2 @@ -694,7 +694,7 @@ design: (work@top) |vpiContAssign: \_cont_assign: , line:9:11, endln:9:60 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/BitPartSelect/dut.sv, line:1:1, endln:10:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/BitPartSelect/dut.sv, line:1:1, endln:10:10 |vpiRhs: \_bit_select: (work@top.storage), line:9:27, endln:9:60 |vpiParent: diff --git a/tests/BitRanges/BitRanges.log b/tests/BitRanges/BitRanges.log index 83cf604749..88b0b2949f 100644 --- a/tests/BitRanges/BitRanges.log +++ b/tests/BitRanges/BitRanges.log @@ -87,7 +87,7 @@ bit_var 2 constant 22 design 1 logic_net 2 -module 3 +module_inst 3 port 4 range 11 ref_obj 4 @@ -102,7 +102,7 @@ bit_var 2 constant 22 design 1 logic_net 2 -module 3 +module_inst 3 port 6 range 11 ref_obj 6 @@ -120,7 +120,7 @@ design: (work@top) |vpiElaborated:1 |vpiName:work@top |uhdmallModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/BitRanges/dut.sv, line:1:1, endln:6:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/BitRanges/dut.sv, line:1:1, endln:6:10 |vpiParent: \_design: (work@top) |vpiFullName:work@top @@ -128,19 +128,19 @@ design: (work@top) |vpiNet: \_logic_net: (work@top.dmi_req_ram), line:3:21, endln:3:32 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/BitRanges/dut.sv, line:1:1, endln:6:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/BitRanges/dut.sv, line:1:1, endln:6:10 |vpiName:dmi_req_ram |vpiFullName:work@top.dmi_req_ram |vpiNet: \_logic_net: (work@top.dmi_req_addr), line:4:21, endln:4:33 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/BitRanges/dut.sv, line:1:1, endln:6:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/BitRanges/dut.sv, line:1:1, endln:6:10 |vpiName:dmi_req_addr |vpiFullName:work@top.dmi_req_addr |vpiPort: \_port: (dmi_req_ram), line:3:21, endln:3:32 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/BitRanges/dut.sv, line:1:1, endln:6:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/BitRanges/dut.sv, line:1:1, endln:6:10 |vpiName:dmi_req_ram |vpiDirection:2 |vpiLowConn: @@ -194,7 +194,7 @@ design: (work@top) |vpiPort: \_port: (dmi_req_addr), line:4:21, endln:4:33 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/BitRanges/dut.sv, line:1:1, endln:6:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/BitRanges/dut.sv, line:1:1, endln:6:10 |vpiName:dmi_req_addr |vpiDirection:2 |vpiLowConn: @@ -223,12 +223,12 @@ design: (work@top) |vpiConstType:9 |vpiSigned:1 |uhdmtopModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/BitRanges/dut.sv, line:1:1, endln:6:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/BitRanges/dut.sv, line:1:1, endln:6:10 |vpiName:work@top |vpiVariables: \_array_var: (work@top.dmi_req_ram), line:3:21, endln:3:40 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/BitRanges/dut.sv, line:1:1, endln:6:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/BitRanges/dut.sv, line:1:1, endln:6:10 |vpiSize:2 |vpiTypespec: \_array_typespec: @@ -286,7 +286,7 @@ design: (work@top) |vpiVariables: \_bit_var: (work@top.dmi_req_addr), line:4:21, endln:4:33 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/BitRanges/dut.sv, line:1:1, endln:6:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/BitRanges/dut.sv, line:1:1, endln:6:10 |vpiTypespec: \_bit_typespec: , line:4:10, endln:4:19 |vpiRange: @@ -317,7 +317,7 @@ design: (work@top) |vpiPort: \_port: (dmi_req_ram), line:3:21, endln:3:32 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/BitRanges/dut.sv, line:1:1, endln:6:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/BitRanges/dut.sv, line:1:1, endln:6:10 |vpiName:dmi_req_ram |vpiDirection:2 |vpiLowConn: @@ -352,11 +352,11 @@ design: (work@top) |vpiConstType:9 |vpiSigned:1 |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/BitRanges/dut.sv, line:1:1, endln:6:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/BitRanges/dut.sv, line:1:1, endln:6:10 |vpiPort: \_port: (dmi_req_addr), line:4:21, endln:4:33 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/BitRanges/dut.sv, line:1:1, endln:6:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/BitRanges/dut.sv, line:1:1, endln:6:10 |vpiName:dmi_req_addr |vpiDirection:2 |vpiLowConn: @@ -391,7 +391,7 @@ design: (work@top) |vpiConstType:9 |vpiSigned:1 |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/BitRanges/dut.sv, line:1:1, endln:6:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/BitRanges/dut.sv, line:1:1, endln:6:10 =================== [ FATAL] : 0 [ SYNTAX] : 0 diff --git a/tests/BitSelect/BitSelect.log b/tests/BitSelect/BitSelect.log index d2e47e0216..1ea974874f 100644 --- a/tests/BitSelect/BitSelect.log +++ b/tests/BitSelect/BitSelect.log @@ -211,7 +211,7 @@ gen_scope 6 gen_scope_array 6 int_typespec 11 logic_typespec 6 -module 13 +module_inst 13 operation 10 param_assign 10 parameter 13 @@ -229,7 +229,7 @@ gen_scope 9 gen_scope_array 9 int_typespec 11 logic_typespec 6 -module 16 +module_inst 16 operation 10 param_assign 13 parameter 13 @@ -249,14 +249,14 @@ design: (work@dut) |vpiElaborated:1 |vpiName:work@dut |uhdmallModules: -\_module: work@alert_sender (work@alert_sender), file:${SURELOG_DIR}/tests/BitSelect/dut.sv, line:1:1, endln:5:10 +\_module_inst: work@alert_sender (work@alert_sender), file:${SURELOG_DIR}/tests/BitSelect/dut.sv, line:1:1, endln:5:10 |vpiParent: \_design: (work@dut) |vpiFullName:work@alert_sender |vpiParameter: \_parameter: (work@alert_sender.AsyncOn), line:3:17, endln:3:24 |vpiParent: - \_module: work@alert_sender (work@alert_sender), file:${SURELOG_DIR}/tests/BitSelect/dut.sv, line:1:1, endln:5:10 + \_module_inst: work@alert_sender (work@alert_sender), file:${SURELOG_DIR}/tests/BitSelect/dut.sv, line:1:1, endln:5:10 |BIN:0 |vpiTypespec: \_bit_typespec: , line:3:13, endln:3:16 @@ -268,7 +268,7 @@ design: (work@dut) |vpiParamAssign: \_param_assign: , line:3:17, endln:3:31 |vpiParent: - \_module: work@alert_sender (work@alert_sender), file:${SURELOG_DIR}/tests/BitSelect/dut.sv, line:1:1, endln:5:10 + \_module_inst: work@alert_sender (work@alert_sender), file:${SURELOG_DIR}/tests/BitSelect/dut.sv, line:1:1, endln:5:10 |vpiRhs: \_constant: , line:3:27, endln:3:31 |vpiDecompile:1'b0 @@ -281,14 +281,14 @@ design: (work@dut) \_parameter: (work@alert_sender.AsyncOn), line:3:17, endln:3:24 |vpiDefName:work@alert_sender |uhdmallModules: -\_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/BitSelect/dut.sv, line:6:1, endln:15:10 +\_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/BitSelect/dut.sv, line:6:1, endln:15:10 |vpiParent: \_design: (work@dut) |vpiFullName:work@dut |vpiParameter: \_parameter: (work@dut.NumAlerts), line:7:33, endln:7:42 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/BitSelect/dut.sv, line:6:1, endln:15:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/BitSelect/dut.sv, line:6:1, endln:15:10 |UINT:3 |vpiTypespec: \_int_typespec: , line:7:11, endln:7:14 @@ -301,7 +301,7 @@ design: (work@dut) |vpiParameter: \_parameter: (work@dut.AlertAsyncOn), line:8:33, endln:8:45 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/BitSelect/dut.sv, line:6:1, endln:15:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/BitSelect/dut.sv, line:6:1, endln:15:10 |vpiTypespec: \_logic_typespec: , line:8:11, endln:8:32 |vpiParent: @@ -339,13 +339,13 @@ design: (work@dut) |vpiParameter: \_parameter: (work@dut.res), line:9:11, endln:9:14 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/BitSelect/dut.sv, line:6:1, endln:15:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/BitSelect/dut.sv, line:6:1, endln:15:10 |vpiName:res |vpiFullName:work@dut.res |vpiParamAssign: \_param_assign: , line:7:33, endln:7:46 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/BitSelect/dut.sv, line:6:1, endln:15:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/BitSelect/dut.sv, line:6:1, endln:15:10 |vpiRhs: \_constant: , line:7:45, endln:7:46 |vpiDecompile:3 @@ -359,7 +359,7 @@ design: (work@dut) |vpiParamAssign: \_param_assign: , line:8:33, endln:8:65 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/BitSelect/dut.sv, line:6:1, endln:15:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/BitSelect/dut.sv, line:6:1, endln:15:10 |vpiRhs: \_operation: , line:8:48, endln:8:65 |vpiOpType:34 @@ -384,7 +384,7 @@ design: (work@dut) |vpiParamAssign: \_param_assign: , line:9:11, endln:9:33 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/BitSelect/dut.sv, line:6:1, endln:15:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/BitSelect/dut.sv, line:6:1, endln:15:10 |vpiRhs: \_bit_select: (AlertAsyncOn), line:9:18, endln:9:33 |vpiParent: @@ -403,12 +403,12 @@ design: (work@dut) \_parameter: (work@dut.res), line:9:11, endln:9:14 |vpiDefName:work@dut |uhdmtopModules: -\_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/BitSelect/dut.sv, line:6:1, endln:15:10 +\_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/BitSelect/dut.sv, line:6:1, endln:15:10 |vpiName:work@dut |vpiParameter: \_parameter: (work@dut.NumAlerts), line:7:33, endln:7:42 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/BitSelect/dut.sv, line:6:1, endln:15:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/BitSelect/dut.sv, line:6:1, endln:15:10 |UINT:3 |vpiTypespec: \_int_typespec: , line:7:11, endln:7:14 @@ -421,7 +421,7 @@ design: (work@dut) |vpiParameter: \_parameter: (work@dut.AlertAsyncOn), line:8:33, endln:8:45 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/BitSelect/dut.sv, line:6:1, endln:15:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/BitSelect/dut.sv, line:6:1, endln:15:10 |vpiTypespec: \_logic_typespec: , line:8:11, endln:8:32 |vpiParent: @@ -464,13 +464,13 @@ design: (work@dut) |vpiParameter: \_parameter: (work@dut.res), line:9:11, endln:9:14 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/BitSelect/dut.sv, line:6:1, endln:15:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/BitSelect/dut.sv, line:6:1, endln:15:10 |vpiName:res |vpiFullName:work@dut.res |vpiParamAssign: \_param_assign: , line:7:33, endln:7:46 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/BitSelect/dut.sv, line:6:1, endln:15:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/BitSelect/dut.sv, line:6:1, endln:15:10 |vpiRhs: \_constant: , line:7:45, endln:7:46 |vpiDecompile:3 @@ -484,7 +484,7 @@ design: (work@dut) |vpiParamAssign: \_param_assign: , line:8:33, endln:8:65 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/BitSelect/dut.sv, line:6:1, endln:15:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/BitSelect/dut.sv, line:6:1, endln:15:10 |vpiRhs: \_constant: , line:8:48, endln:8:65 |vpiDecompile:3'b111 @@ -506,7 +506,7 @@ design: (work@dut) |vpiParamAssign: \_param_assign: , line:9:11, endln:9:33 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/BitSelect/dut.sv, line:6:1, endln:15:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/BitSelect/dut.sv, line:6:1, endln:15:10 |vpiRhs: \_constant: , line:9:18, endln:9:33 |vpiDecompile:1'b1 @@ -521,7 +521,7 @@ design: (work@dut) |vpiGenScopeArray: \_gen_scope_array: (work@dut.gen_alert_tx[0]), line:10:40, endln:14:4 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/BitSelect/dut.sv, line:6:1, endln:15:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/BitSelect/dut.sv, line:6:1, endln:15:10 |vpiName:gen_alert_tx[0] |vpiFullName:work@dut.gen_alert_tx[0] |vpiGenScope: @@ -539,8 +539,8 @@ design: (work@dut) |vpiLocalParam:1 |vpiName:i |vpiFullName:work@dut.gen_alert_tx[0].i - |vpiModule: - \_module: work@alert_sender (work@dut.gen_alert_tx[0].i_alert_sender), file:${SURELOG_DIR}/tests/BitSelect/dut.sv, line:11:3, endln:13:23 + |vpiModuleInst: + \_module_inst: work@alert_sender (work@dut.gen_alert_tx[0].i_alert_sender), file:${SURELOG_DIR}/tests/BitSelect/dut.sv, line:11:3, endln:13:23 |vpiParent: \_gen_scope: (work@dut.gen_alert_tx[0]) |vpiName:i_alert_sender @@ -560,7 +560,7 @@ design: (work@dut) |vpiParamAssign: \_param_assign: , line:3:17, endln:3:31 |vpiParent: - \_module: work@alert_sender (work@dut.gen_alert_tx[0].i_alert_sender), file:${SURELOG_DIR}/tests/BitSelect/dut.sv, line:11:3, endln:13:23 + \_module_inst: work@alert_sender (work@dut.gen_alert_tx[0].i_alert_sender), file:${SURELOG_DIR}/tests/BitSelect/dut.sv, line:11:3, endln:13:23 |vpiOverriden:1 |vpiRhs: \_constant: , line:3:27, endln:3:31 @@ -578,7 +578,7 @@ design: (work@dut) |vpiGenScopeArray: \_gen_scope_array: (work@dut.gen_alert_tx[1]), line:10:40, endln:14:4 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/BitSelect/dut.sv, line:6:1, endln:15:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/BitSelect/dut.sv, line:6:1, endln:15:10 |vpiName:gen_alert_tx[1] |vpiFullName:work@dut.gen_alert_tx[1] |vpiGenScope: @@ -596,8 +596,8 @@ design: (work@dut) |vpiLocalParam:1 |vpiName:i |vpiFullName:work@dut.gen_alert_tx[1].i - |vpiModule: - \_module: work@alert_sender (work@dut.gen_alert_tx[1].i_alert_sender), file:${SURELOG_DIR}/tests/BitSelect/dut.sv, line:11:3, endln:13:23 + |vpiModuleInst: + \_module_inst: work@alert_sender (work@dut.gen_alert_tx[1].i_alert_sender), file:${SURELOG_DIR}/tests/BitSelect/dut.sv, line:11:3, endln:13:23 |vpiParent: \_gen_scope: (work@dut.gen_alert_tx[1]) |vpiName:i_alert_sender @@ -617,7 +617,7 @@ design: (work@dut) |vpiParamAssign: \_param_assign: , line:3:17, endln:3:31 |vpiParent: - \_module: work@alert_sender (work@dut.gen_alert_tx[1].i_alert_sender), file:${SURELOG_DIR}/tests/BitSelect/dut.sv, line:11:3, endln:13:23 + \_module_inst: work@alert_sender (work@dut.gen_alert_tx[1].i_alert_sender), file:${SURELOG_DIR}/tests/BitSelect/dut.sv, line:11:3, endln:13:23 |vpiOverriden:1 |vpiRhs: \_constant: , line:3:27, endln:3:31 @@ -635,7 +635,7 @@ design: (work@dut) |vpiGenScopeArray: \_gen_scope_array: (work@dut.gen_alert_tx[2]), line:10:40, endln:14:4 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/BitSelect/dut.sv, line:6:1, endln:15:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/BitSelect/dut.sv, line:6:1, endln:15:10 |vpiName:gen_alert_tx[2] |vpiFullName:work@dut.gen_alert_tx[2] |vpiGenScope: @@ -653,8 +653,8 @@ design: (work@dut) |vpiLocalParam:1 |vpiName:i |vpiFullName:work@dut.gen_alert_tx[2].i - |vpiModule: - \_module: work@alert_sender (work@dut.gen_alert_tx[2].i_alert_sender), file:${SURELOG_DIR}/tests/BitSelect/dut.sv, line:11:3, endln:13:23 + |vpiModuleInst: + \_module_inst: work@alert_sender (work@dut.gen_alert_tx[2].i_alert_sender), file:${SURELOG_DIR}/tests/BitSelect/dut.sv, line:11:3, endln:13:23 |vpiParent: \_gen_scope: (work@dut.gen_alert_tx[2]) |vpiName:i_alert_sender @@ -674,7 +674,7 @@ design: (work@dut) |vpiParamAssign: \_param_assign: , line:3:17, endln:3:31 |vpiParent: - \_module: work@alert_sender (work@dut.gen_alert_tx[2].i_alert_sender), file:${SURELOG_DIR}/tests/BitSelect/dut.sv, line:11:3, endln:13:23 + \_module_inst: work@alert_sender (work@dut.gen_alert_tx[2].i_alert_sender), file:${SURELOG_DIR}/tests/BitSelect/dut.sv, line:11:3, endln:13:23 |vpiOverriden:1 |vpiRhs: \_constant: , line:3:27, endln:3:31 diff --git a/tests/BitSelectExpr/BitSelectExpr.log b/tests/BitSelectExpr/BitSelectExpr.log index 57d0057b4c..ffe9e53d75 100644 --- a/tests/BitSelectExpr/BitSelectExpr.log +++ b/tests/BitSelectExpr/BitSelectExpr.log @@ -117,7 +117,7 @@ hier_path 2 int_typespec 4 int_var 1 logic_net 2 -module 4 +module_inst 4 operation 2 packed_array_typespec 1 packed_array_var 1 @@ -139,7 +139,7 @@ hier_path 3 int_typespec 4 int_var 1 logic_net 2 -module 4 +module_inst 4 operation 3 packed_array_typespec 1 packed_array_var 1 @@ -163,17 +163,17 @@ design: (work@top) |vpiElaborated:1 |vpiName:work@top |uhdmallModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/BitSelectExpr/dut.sv, line:1:1, endln:12:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/BitSelectExpr/dut.sv, line:1:1, endln:12:10 |vpiParent: \_design: (work@top) |vpiFullName:work@top |vpiTypedef: \_struct_typespec: (sram_otp_key_rsp_t), line:3:12, endln:3:18 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/BitSelectExpr/dut.sv, line:1:1, endln:12:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/BitSelectExpr/dut.sv, line:1:1, endln:12:10 |vpiName:sram_otp_key_rsp_t |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/BitSelectExpr/dut.sv, line:1:1, endln:12:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/BitSelectExpr/dut.sv, line:1:1, endln:12:10 |vpiPacked:1 |vpiTypespecMember: \_typespec_member: (nonce), line:4:14, endln:4:19 @@ -194,19 +194,19 @@ design: (work@top) |vpiNet: \_logic_net: (work@top.o), line:1:23, endln:1:24 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/BitSelectExpr/dut.sv, line:1:1, endln:12:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/BitSelectExpr/dut.sv, line:1:1, endln:12:10 |vpiName:o |vpiFullName:work@top.o |vpiNet: \_logic_net: (work@top.sram_otp_key_o), line:7:29, endln:7:43 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/BitSelectExpr/dut.sv, line:1:1, endln:12:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/BitSelectExpr/dut.sv, line:1:1, endln:12:10 |vpiName:sram_otp_key_o |vpiFullName:work@top.sram_otp_key_o |vpiPort: \_port: (o), line:1:23, endln:1:24 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/BitSelectExpr/dut.sv, line:1:1, endln:12:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/BitSelectExpr/dut.sv, line:1:1, endln:12:10 |vpiName:o |vpiDirection:2 |vpiLowConn: @@ -219,7 +219,7 @@ design: (work@top) |vpiContAssign: \_cont_assign: , line:9:11, endln:9:40 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/BitSelectExpr/dut.sv, line:1:1, endln:12:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/BitSelectExpr/dut.sv, line:1:1, endln:12:10 |vpiRhs: \_constant: , line:9:39, endln:9:40 |vpiParent: @@ -267,12 +267,12 @@ design: (work@top) \_hier_path: (sram_otp_key_o[...].nonce), line:9:11, endln:9:25 |vpiName:nonce |uhdmtopModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/BitSelectExpr/dut.sv, line:1:1, endln:12:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/BitSelectExpr/dut.sv, line:1:1, endln:12:10 |vpiName:work@top |vpiVariables: \_int_var: (work@top.o), line:1:23, endln:1:24 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/BitSelectExpr/dut.sv, line:1:1, endln:12:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/BitSelectExpr/dut.sv, line:1:1, endln:12:10 |vpiTypespec: \_int_typespec: , line:1:19, endln:1:22 |vpiSigned:1 @@ -283,7 +283,7 @@ design: (work@top) |vpiVariables: \_packed_array_var: (work@top.sram_otp_key_o), line:7:29, endln:7:43 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/BitSelectExpr/dut.sv, line:1:1, endln:12:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/BitSelectExpr/dut.sv, line:1:1, endln:12:10 |vpiName:sram_otp_key_o |vpiFullName:work@top.sram_otp_key_o |vpiVisibility:1 @@ -320,7 +320,7 @@ design: (work@top) |vpiPort: \_port: (o), line:1:23, endln:1:24 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/BitSelectExpr/dut.sv, line:1:1, endln:12:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/BitSelectExpr/dut.sv, line:1:1, endln:12:10 |vpiName:o |vpiDirection:2 |vpiLowConn: @@ -335,11 +335,11 @@ design: (work@top) \_int_typespec: , line:1:19, endln:1:22 |vpiSigned:1 |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/BitSelectExpr/dut.sv, line:1:1, endln:12:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/BitSelectExpr/dut.sv, line:1:1, endln:12:10 |vpiContAssign: \_cont_assign: , line:9:11, endln:9:40 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/BitSelectExpr/dut.sv, line:1:1, endln:12:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/BitSelectExpr/dut.sv, line:1:1, endln:12:10 |vpiRhs: \_constant: , line:9:39, endln:9:40 |vpiLhs: diff --git a/tests/BitSelectHier/BitSelectHier.log b/tests/BitSelectHier/BitSelectHier.log index b61f8e68cf..9534aa7ab7 100644 --- a/tests/BitSelectHier/BitSelectHier.log +++ b/tests/BitSelectHier/BitSelectHier.log @@ -216,7 +216,7 @@ design 1 function 5 hier_path 2 io_decl 3 -module 1 +module_inst 1 package 3 range 9 ref_obj 8 @@ -239,7 +239,7 @@ design 1 function 12 hier_path 5 io_decl 8 -module 1 +module_inst 1 package 3 range 9 ref_obj 20 diff --git a/tests/BitsArray/BitsArray.log b/tests/BitsArray/BitsArray.log index ac31c1afa4..031c652253 100644 --- a/tests/BitsArray/BitsArray.log +++ b/tests/BitsArray/BitsArray.log @@ -242,7 +242,7 @@ int_typespec 4 logic_net 5 logic_typespec 5 logic_var 1 -module 12 +module_inst 12 operation 7 param_assign 4 parameter 4 @@ -264,7 +264,7 @@ int_typespec 4 logic_net 5 logic_typespec 5 logic_var 1 -module 12 +module_inst 12 operation 8 param_assign 4 parameter 4 @@ -285,14 +285,14 @@ design: (work@top) |vpiElaborated:1 |vpiName:work@top |uhdmallModules: -\_module: work@aes_reg_status (work@aes_reg_status), file:${SURELOG_DIR}/tests/BitsArray/dut.sv, line:2:1, endln:7:10 +\_module_inst: work@aes_reg_status (work@aes_reg_status), file:${SURELOG_DIR}/tests/BitsArray/dut.sv, line:2:1, endln:7:10 |vpiParent: \_design: (work@top) |vpiFullName:work@aes_reg_status |vpiParameter: \_parameter: (work@aes_reg_status.Width), line:3:18, endln:3:23 |vpiParent: - \_module: work@aes_reg_status (work@aes_reg_status), file:${SURELOG_DIR}/tests/BitsArray/dut.sv, line:2:1, endln:7:10 + \_module_inst: work@aes_reg_status (work@aes_reg_status), file:${SURELOG_DIR}/tests/BitsArray/dut.sv, line:2:1, endln:7:10 |UINT:1 |vpiTypespec: \_int_typespec: , line:3:14, endln:3:17 @@ -305,7 +305,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:3:18, endln:3:27 |vpiParent: - \_module: work@aes_reg_status (work@aes_reg_status), file:${SURELOG_DIR}/tests/BitsArray/dut.sv, line:2:1, endln:7:10 + \_module_inst: work@aes_reg_status (work@aes_reg_status), file:${SURELOG_DIR}/tests/BitsArray/dut.sv, line:2:1, endln:7:10 |vpiRhs: \_constant: , line:3:26, endln:3:27 |vpiDecompile:1 @@ -320,14 +320,14 @@ design: (work@top) |vpiNet: \_logic_net: (work@aes_reg_status.we_i), line:5:28, endln:5:32 |vpiParent: - \_module: work@aes_reg_status (work@aes_reg_status), file:${SURELOG_DIR}/tests/BitsArray/dut.sv, line:2:1, endln:7:10 + \_module_inst: work@aes_reg_status (work@aes_reg_status), file:${SURELOG_DIR}/tests/BitsArray/dut.sv, line:2:1, endln:7:10 |vpiName:we_i |vpiFullName:work@aes_reg_status.we_i |vpiNetType:36 |vpiPort: \_port: (we_i), line:5:28, endln:5:32 |vpiParent: - \_module: work@aes_reg_status (work@aes_reg_status), file:${SURELOG_DIR}/tests/BitsArray/dut.sv, line:2:1, endln:7:10 + \_module_inst: work@aes_reg_status (work@aes_reg_status), file:${SURELOG_DIR}/tests/BitsArray/dut.sv, line:2:1, endln:7:10 |vpiName:we_i |vpiDirection:1 |vpiLowConn: @@ -365,7 +365,7 @@ design: (work@top) |UINT:0 |vpiConstType:9 |uhdmallModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/BitsArray/dut.sv, line:9:1, endln:21:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/BitsArray/dut.sv, line:9:1, endln:21:10 |vpiParent: \_design: (work@top) |vpiFullName:work@top @@ -373,25 +373,25 @@ design: (work@top) |vpiNet: \_logic_net: (work@top.fcoe_reserved_before_sof), line:11:8, endln:11:32 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/BitsArray/dut.sv, line:9:1, endln:21:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/BitsArray/dut.sv, line:9:1, endln:21:10 |vpiName:fcoe_reserved_before_sof |vpiFullName:work@top.fcoe_reserved_before_sof |vpiNet: \_logic_net: (work@top.key_init_we), line:13:16, endln:13:27 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/BitsArray/dut.sv, line:9:1, endln:21:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/BitsArray/dut.sv, line:9:1, endln:21:10 |vpiName:key_init_we |vpiFullName:work@top.key_init_we |vpiNetType:36 |uhdmallModules: -\_module: work@toto (work@toto), file:${SURELOG_DIR}/tests/BitsArray/dut.sv, line:23:1, endln:30:10 +\_module_inst: work@toto (work@toto), file:${SURELOG_DIR}/tests/BitsArray/dut.sv, line:23:1, endln:30:10 |vpiParent: \_design: (work@top) |vpiFullName:work@toto |vpiParameter: \_parameter: (work@toto.a), line:27:14, endln:27:15 |vpiParent: - \_module: work@toto (work@toto), file:${SURELOG_DIR}/tests/BitsArray/dut.sv, line:23:1, endln:30:10 + \_module_inst: work@toto (work@toto), file:${SURELOG_DIR}/tests/BitsArray/dut.sv, line:23:1, endln:30:10 |UINT:1 |vpiTypespec: \_int_typespec: @@ -400,7 +400,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:27:14, endln:27:52 |vpiParent: - \_module: work@toto (work@toto), file:${SURELOG_DIR}/tests/BitsArray/dut.sv, line:23:1, endln:30:10 + \_module_inst: work@toto (work@toto), file:${SURELOG_DIR}/tests/BitsArray/dut.sv, line:23:1, endln:30:10 |vpiRhs: \_constant: , line:27:18, endln:27:52 |vpiDecompile:1 @@ -415,16 +415,16 @@ design: (work@top) |vpiNet: \_logic_net: (work@toto.fcoe_reserved_before_sof), line:25:6, endln:25:30 |vpiParent: - \_module: work@toto (work@toto), file:${SURELOG_DIR}/tests/BitsArray/dut.sv, line:23:1, endln:30:10 + \_module_inst: work@toto (work@toto), file:${SURELOG_DIR}/tests/BitsArray/dut.sv, line:23:1, endln:30:10 |vpiName:fcoe_reserved_before_sof |vpiFullName:work@toto.fcoe_reserved_before_sof |uhdmtopModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/BitsArray/dut.sv, line:9:1, endln:21:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/BitsArray/dut.sv, line:9:1, endln:21:10 |vpiName:work@top |vpiVariables: \_array_var: (work@top.fcoe_reserved_before_sof), line:11:8, endln:11:34 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/BitsArray/dut.sv, line:9:1, endln:21:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/BitsArray/dut.sv, line:9:1, endln:21:10 |vpiSize:1 |vpiTypespec: \_array_typespec: @@ -444,7 +444,7 @@ design: (work@top) |vpiVariables: \_array_var: (work@top.key_init_we), line:13:16, endln:13:31 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/BitsArray/dut.sv, line:9:1, endln:21:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/BitsArray/dut.sv, line:9:1, endln:21:10 |vpiSize:2 |vpiTypespec: \_array_typespec: @@ -525,16 +525,16 @@ design: (work@top) |vpiDefName:work@top |vpiTop:1 |vpiTopModule:1 - |vpiModule: - \_module: work@aes_reg_status (work@top.u_reg_status_key_init), file:${SURELOG_DIR}/tests/BitsArray/dut.sv, line:15:4, endln:19:6 + |vpiModuleInst: + \_module_inst: work@aes_reg_status (work@top.u_reg_status_key_init), file:${SURELOG_DIR}/tests/BitsArray/dut.sv, line:15:4, endln:19:6 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/BitsArray/dut.sv, line:9:1, endln:21:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/BitsArray/dut.sv, line:9:1, endln:21:10 |vpiName:u_reg_status_key_init |vpiFullName:work@top.u_reg_status_key_init |vpiParameter: \_parameter: (work@top.u_reg_status_key_init.Width), line:3:18, endln:3:23 |vpiParent: - \_module: work@aes_reg_status (work@top.u_reg_status_key_init), file:${SURELOG_DIR}/tests/BitsArray/dut.sv, line:15:4, endln:19:6 + \_module_inst: work@aes_reg_status (work@top.u_reg_status_key_init), file:${SURELOG_DIR}/tests/BitsArray/dut.sv, line:15:4, endln:19:6 |UINT:1 |vpiTypespec: \_int_typespec: , line:3:14, endln:3:17 @@ -547,7 +547,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:3:18, endln:3:27 |vpiParent: - \_module: work@aes_reg_status (work@top.u_reg_status_key_init), file:${SURELOG_DIR}/tests/BitsArray/dut.sv, line:15:4, endln:19:6 + \_module_inst: work@aes_reg_status (work@top.u_reg_status_key_init), file:${SURELOG_DIR}/tests/BitsArray/dut.sv, line:15:4, endln:19:6 |vpiOverriden:1 |vpiRhs: \_constant: , line:3:26, endln:3:27 @@ -565,7 +565,7 @@ design: (work@top) |vpiNet: \_logic_net: (work@top.u_reg_status_key_init.we_i), line:5:28, endln:5:32 |vpiParent: - \_module: work@aes_reg_status (work@top.u_reg_status_key_init), file:${SURELOG_DIR}/tests/BitsArray/dut.sv, line:15:4, endln:19:6 + \_module_inst: work@aes_reg_status (work@top.u_reg_status_key_init), file:${SURELOG_DIR}/tests/BitsArray/dut.sv, line:15:4, endln:19:6 |vpiTypespec: \_logic_typespec: , line:5:10, endln:5:27 |vpiRange: @@ -590,11 +590,11 @@ design: (work@top) |vpiFullName:work@top.u_reg_status_key_init.we_i |vpiNetType:36 |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/BitsArray/dut.sv, line:9:1, endln:21:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/BitsArray/dut.sv, line:9:1, endln:21:10 |vpiPort: \_port: (we_i), line:5:28, endln:5:32 |vpiParent: - \_module: work@aes_reg_status (work@top.u_reg_status_key_init), file:${SURELOG_DIR}/tests/BitsArray/dut.sv, line:15:4, endln:19:6 + \_module_inst: work@aes_reg_status (work@top.u_reg_status_key_init), file:${SURELOG_DIR}/tests/BitsArray/dut.sv, line:15:4, endln:19:6 |vpiName:we_i |vpiDirection:1 |vpiHighConn: @@ -677,14 +677,14 @@ design: (work@top) |UINT:0 |vpiConstType:9 |vpiInstance: - \_module: work@aes_reg_status (work@top.u_reg_status_key_init), file:${SURELOG_DIR}/tests/BitsArray/dut.sv, line:15:4, endln:19:6 + \_module_inst: work@aes_reg_status (work@top.u_reg_status_key_init), file:${SURELOG_DIR}/tests/BitsArray/dut.sv, line:15:4, endln:19:6 |uhdmtopModules: -\_module: work@toto (work@toto), file:${SURELOG_DIR}/tests/BitsArray/dut.sv, line:23:1, endln:30:10 +\_module_inst: work@toto (work@toto), file:${SURELOG_DIR}/tests/BitsArray/dut.sv, line:23:1, endln:30:10 |vpiName:work@toto |vpiVariables: \_array_var: (work@toto.fcoe_reserved_before_sof), line:25:6, endln:25:32 |vpiParent: - \_module: work@toto (work@toto), file:${SURELOG_DIR}/tests/BitsArray/dut.sv, line:23:1, endln:30:10 + \_module_inst: work@toto (work@toto), file:${SURELOG_DIR}/tests/BitsArray/dut.sv, line:23:1, endln:30:10 |vpiSize:1 |vpiTypespec: \_array_typespec: @@ -704,7 +704,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@toto.a), line:27:14, endln:27:15 |vpiParent: - \_module: work@toto (work@toto), file:${SURELOG_DIR}/tests/BitsArray/dut.sv, line:23:1, endln:30:10 + \_module_inst: work@toto (work@toto), file:${SURELOG_DIR}/tests/BitsArray/dut.sv, line:23:1, endln:30:10 |UINT:1 |vpiTypespec: \_int_typespec: @@ -715,7 +715,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:27:14, endln:27:52 |vpiParent: - \_module: work@toto (work@toto), file:${SURELOG_DIR}/tests/BitsArray/dut.sv, line:23:1, endln:30:10 + \_module_inst: work@toto (work@toto), file:${SURELOG_DIR}/tests/BitsArray/dut.sv, line:23:1, endln:30:10 |vpiRhs: \_constant: , line:27:18, endln:27:52 |vpiDecompile:1 diff --git a/tests/BitsHierPath/BitsHierPath.log b/tests/BitsHierPath/BitsHierPath.log index 6bb6a1cd7b..4781998ef3 100644 --- a/tests/BitsHierPath/BitsHierPath.log +++ b/tests/BitsHierPath/BitsHierPath.log @@ -271,7 +271,7 @@ design 1 int_typespec 7 logic_net 1 logic_typespec 4 -module 16 +module_inst 16 package 3 param_assign 7 parameter 7 @@ -290,7 +290,7 @@ design 1 int_typespec 7 logic_net 1 logic_typespec 4 -module 16 +module_inst 16 package 3 param_assign 7 parameter 7 @@ -449,14 +449,14 @@ design: (work@top) |vpiDefName:pkg |vpiTop:1 |uhdmallModules: -\_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/BitsHierPath/dut.sv, line:8:1, endln:9:10 +\_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/BitsHierPath/dut.sv, line:8:1, endln:9:10 |vpiParent: \_design: (work@top) |vpiFullName:work@dut |vpiParameter: \_parameter: (work@dut.Width), line:8:28, endln:8:33 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/BitsHierPath/dut.sv, line:8:1, endln:9:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/BitsHierPath/dut.sv, line:8:1, endln:9:10 |UINT:1 |vpiTypespec: \_int_typespec: , line:8:24, endln:8:27 @@ -469,7 +469,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:8:28, endln:8:37 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/BitsHierPath/dut.sv, line:8:1, endln:9:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/BitsHierPath/dut.sv, line:8:1, endln:9:10 |vpiRhs: \_constant: , line:8:36, endln:8:37 |vpiDecompile:1 @@ -482,14 +482,14 @@ design: (work@top) \_parameter: (work@dut.Width), line:8:28, endln:8:33 |vpiDefName:work@dut |uhdmallModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/BitsHierPath/dut.sv, line:11:1, endln:17:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/BitsHierPath/dut.sv, line:11:1, endln:17:10 |vpiParent: \_design: (work@top) |vpiFullName:work@top |vpiParameter: \_parameter: (work@top.SyncWidth), line:12:19, endln:12:28 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/BitsHierPath/dut.sv, line:11:1, endln:17:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/BitsHierPath/dut.sv, line:11:1, endln:17:10 |UINT:17 |vpiTypespec: \_int_typespec: , line:12:15, endln:12:18 @@ -503,7 +503,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:12:19, endln:12:47 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/BitsHierPath/dut.sv, line:11:1, endln:17:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/BitsHierPath/dut.sv, line:11:1, endln:17:10 |vpiRhs: \_constant: , line:12:31, endln:12:47 |vpiDecompile:17 @@ -518,14 +518,14 @@ design: (work@top) |vpiNet: \_logic_net: (work@top.in), line:11:33, endln:11:35 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/BitsHierPath/dut.sv, line:11:1, endln:17:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/BitsHierPath/dut.sv, line:11:1, endln:17:10 |vpiName:in |vpiFullName:work@top.in |vpiNetType:1 |vpiPort: \_port: (in), line:11:33, endln:11:35 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/BitsHierPath/dut.sv, line:11:1, endln:17:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/BitsHierPath/dut.sv, line:11:1, endln:17:10 |vpiName:in |vpiDirection:1 |vpiLowConn: @@ -535,12 +535,12 @@ design: (work@top) |vpiTypedef: \_struct_typespec: (pkg::struct_t), line:2:11, endln:2:17 |uhdmtopModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/BitsHierPath/dut.sv, line:11:1, endln:17:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/BitsHierPath/dut.sv, line:11:1, endln:17:10 |vpiName:work@top |vpiParameter: \_parameter: (work@top.SyncWidth), line:12:19, endln:12:28 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/BitsHierPath/dut.sv, line:11:1, endln:17:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/BitsHierPath/dut.sv, line:11:1, endln:17:10 |UINT:17 |vpiTypespec: \_int_typespec: , line:12:15, endln:12:18 @@ -554,7 +554,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:12:19, endln:12:47 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/BitsHierPath/dut.sv, line:11:1, endln:17:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/BitsHierPath/dut.sv, line:11:1, endln:17:10 |vpiRhs: \_constant: , line:12:31, endln:12:47 |vpiDecompile:17 @@ -570,7 +570,7 @@ design: (work@top) |vpiNet: \_struct_net: (work@top.in), line:11:33, endln:11:35 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/BitsHierPath/dut.sv, line:11:1, endln:17:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/BitsHierPath/dut.sv, line:11:1, endln:17:10 |vpiTypespec: \_struct_typespec: (pkg::struct_t), line:2:11, endln:2:17 |vpiName:in @@ -580,7 +580,7 @@ design: (work@top) |vpiPort: \_port: (in), line:11:33, endln:11:35 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/BitsHierPath/dut.sv, line:11:1, endln:17:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/BitsHierPath/dut.sv, line:11:1, endln:17:10 |vpiName:in |vpiDirection:1 |vpiLowConn: @@ -594,17 +594,17 @@ design: (work@top) |vpiTypedef: \_struct_typespec: (pkg::struct_t), line:2:11, endln:2:17 |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/BitsHierPath/dut.sv, line:11:1, endln:17:10 - |vpiModule: - \_module: work@dut (work@top.dut1), file:${SURELOG_DIR}/tests/BitsHierPath/dut.sv, line:13:4, endln:13:40 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/BitsHierPath/dut.sv, line:11:1, endln:17:10 + |vpiModuleInst: + \_module_inst: work@dut (work@top.dut1), file:${SURELOG_DIR}/tests/BitsHierPath/dut.sv, line:13:4, endln:13:40 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/BitsHierPath/dut.sv, line:11:1, endln:17:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/BitsHierPath/dut.sv, line:11:1, endln:17:10 |vpiName:dut1 |vpiFullName:work@top.dut1 |vpiParameter: \_parameter: (work@top.dut1.Width), line:8:28, endln:8:33 |vpiParent: - \_module: work@dut (work@top.dut1), file:${SURELOG_DIR}/tests/BitsHierPath/dut.sv, line:13:4, endln:13:40 + \_module_inst: work@dut (work@top.dut1), file:${SURELOG_DIR}/tests/BitsHierPath/dut.sv, line:13:4, endln:13:40 |UINT:1 |vpiTypespec: \_int_typespec: , line:8:24, endln:8:27 @@ -617,7 +617,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:8:28, endln:8:37 |vpiParent: - \_module: work@dut (work@top.dut1), file:${SURELOG_DIR}/tests/BitsHierPath/dut.sv, line:13:4, endln:13:40 + \_module_inst: work@dut (work@top.dut1), file:${SURELOG_DIR}/tests/BitsHierPath/dut.sv, line:13:4, endln:13:40 |vpiOverriden:1 |vpiRhs: \_constant: , line:8:36, endln:8:37 @@ -633,17 +633,17 @@ design: (work@top) |vpiDefFile:${SURELOG_DIR}/tests/BitsHierPath/dut.sv |vpiDefLineNo:8 |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/BitsHierPath/dut.sv, line:11:1, endln:17:10 - |vpiModule: - \_module: work@dut (work@top.dut2), file:${SURELOG_DIR}/tests/BitsHierPath/dut.sv, line:14:4, endln:14:38 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/BitsHierPath/dut.sv, line:11:1, endln:17:10 + |vpiModuleInst: + \_module_inst: work@dut (work@top.dut2), file:${SURELOG_DIR}/tests/BitsHierPath/dut.sv, line:14:4, endln:14:38 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/BitsHierPath/dut.sv, line:11:1, endln:17:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/BitsHierPath/dut.sv, line:11:1, endln:17:10 |vpiName:dut2 |vpiFullName:work@top.dut2 |vpiParameter: \_parameter: (work@top.dut2.Width), line:8:28, endln:8:33 |vpiParent: - \_module: work@dut (work@top.dut2), file:${SURELOG_DIR}/tests/BitsHierPath/dut.sv, line:14:4, endln:14:38 + \_module_inst: work@dut (work@top.dut2), file:${SURELOG_DIR}/tests/BitsHierPath/dut.sv, line:14:4, endln:14:38 |UINT:1 |vpiTypespec: \_int_typespec: , line:8:24, endln:8:27 @@ -656,7 +656,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:8:28, endln:8:37 |vpiParent: - \_module: work@dut (work@top.dut2), file:${SURELOG_DIR}/tests/BitsHierPath/dut.sv, line:14:4, endln:14:38 + \_module_inst: work@dut (work@top.dut2), file:${SURELOG_DIR}/tests/BitsHierPath/dut.sv, line:14:4, endln:14:38 |vpiOverriden:1 |vpiRhs: \_constant: , line:8:36, endln:8:37 @@ -672,17 +672,17 @@ design: (work@top) |vpiDefFile:${SURELOG_DIR}/tests/BitsHierPath/dut.sv |vpiDefLineNo:8 |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/BitsHierPath/dut.sv, line:11:1, endln:17:10 - |vpiModule: - \_module: work@dut (work@top.dut3), file:${SURELOG_DIR}/tests/BitsHierPath/dut.sv, line:15:4, endln:15:36 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/BitsHierPath/dut.sv, line:11:1, endln:17:10 + |vpiModuleInst: + \_module_inst: work@dut (work@top.dut3), file:${SURELOG_DIR}/tests/BitsHierPath/dut.sv, line:15:4, endln:15:36 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/BitsHierPath/dut.sv, line:11:1, endln:17:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/BitsHierPath/dut.sv, line:11:1, endln:17:10 |vpiName:dut3 |vpiFullName:work@top.dut3 |vpiParameter: \_parameter: (work@top.dut3.Width), line:8:28, endln:8:33 |vpiParent: - \_module: work@dut (work@top.dut3), file:${SURELOG_DIR}/tests/BitsHierPath/dut.sv, line:15:4, endln:15:36 + \_module_inst: work@dut (work@top.dut3), file:${SURELOG_DIR}/tests/BitsHierPath/dut.sv, line:15:4, endln:15:36 |UINT:1 |vpiTypespec: \_int_typespec: , line:8:24, endln:8:27 @@ -695,7 +695,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:8:28, endln:8:37 |vpiParent: - \_module: work@dut (work@top.dut3), file:${SURELOG_DIR}/tests/BitsHierPath/dut.sv, line:15:4, endln:15:36 + \_module_inst: work@dut (work@top.dut3), file:${SURELOG_DIR}/tests/BitsHierPath/dut.sv, line:15:4, endln:15:36 |vpiOverriden:1 |vpiRhs: \_constant: , line:8:36, endln:8:37 @@ -711,17 +711,17 @@ design: (work@top) |vpiDefFile:${SURELOG_DIR}/tests/BitsHierPath/dut.sv |vpiDefLineNo:8 |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/BitsHierPath/dut.sv, line:11:1, endln:17:10 - |vpiModule: - \_module: work@dut (work@top.dut4), file:${SURELOG_DIR}/tests/BitsHierPath/dut.sv, line:16:4, endln:16:43 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/BitsHierPath/dut.sv, line:11:1, endln:17:10 + |vpiModuleInst: + \_module_inst: work@dut (work@top.dut4), file:${SURELOG_DIR}/tests/BitsHierPath/dut.sv, line:16:4, endln:16:43 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/BitsHierPath/dut.sv, line:11:1, endln:17:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/BitsHierPath/dut.sv, line:11:1, endln:17:10 |vpiName:dut4 |vpiFullName:work@top.dut4 |vpiParameter: \_parameter: (work@top.dut4.Width), line:8:28, endln:8:33 |vpiParent: - \_module: work@dut (work@top.dut4), file:${SURELOG_DIR}/tests/BitsHierPath/dut.sv, line:16:4, endln:16:43 + \_module_inst: work@dut (work@top.dut4), file:${SURELOG_DIR}/tests/BitsHierPath/dut.sv, line:16:4, endln:16:43 |UINT:1 |vpiTypespec: \_int_typespec: , line:8:24, endln:8:27 @@ -734,7 +734,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:8:28, endln:8:37 |vpiParent: - \_module: work@dut (work@top.dut4), file:${SURELOG_DIR}/tests/BitsHierPath/dut.sv, line:16:4, endln:16:43 + \_module_inst: work@dut (work@top.dut4), file:${SURELOG_DIR}/tests/BitsHierPath/dut.sv, line:16:4, endln:16:43 |vpiOverriden:1 |vpiRhs: \_constant: , line:8:36, endln:8:37 @@ -750,7 +750,7 @@ design: (work@top) |vpiDefFile:${SURELOG_DIR}/tests/BitsHierPath/dut.sv |vpiDefLineNo:8 |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/BitsHierPath/dut.sv, line:11:1, endln:17:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/BitsHierPath/dut.sv, line:11:1, endln:17:10 =================== [ FATAL] : 0 [ SYNTAX] : 0 diff --git a/tests/BitsLogic/BitsLogic.log b/tests/BitsLogic/BitsLogic.log index c3e4be49e8..e7e7346908 100644 --- a/tests/BitsLogic/BitsLogic.log +++ b/tests/BitsLogic/BitsLogic.log @@ -205,7 +205,7 @@ int_typespec 2 logic_net 1 logic_typespec 6 logic_var 1 -module 5 +module_inst 5 operation 2 package 3 packed_array_typespec 1 @@ -224,7 +224,7 @@ int_typespec 2 logic_net 1 logic_typespec 6 logic_var 1 -module 5 +module_inst 5 operation 2 package 3 packed_array_typespec 1 @@ -255,7 +255,7 @@ design: (work@top) |vpiTypedef: \_struct_typespec: (SchedulerTypes::IntIssueQueueEntry), line:3:9, endln:3:15 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/BitsLogic/dut.sv, line:12:1, endln:28:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/BitsLogic/dut.sv, line:12:1, endln:28:10 |vpiName:SchedulerTypes::IntIssueQueueEntry |vpiInstance: \_package: SchedulerTypes (SchedulerTypes::), file:${SURELOG_DIR}/tests/BitsLogic/dut.sv, line:1:1, endln:8:11 @@ -288,14 +288,14 @@ design: (work@top) |vpiDefName:SchedulerTypes |vpiTop:1 |uhdmallModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/BitsLogic/dut.sv, line:12:1, endln:28:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/BitsLogic/dut.sv, line:12:1, endln:28:10 |vpiParent: \_design: (work@top) |vpiFullName:work@top |vpiParameter: \_parameter: (work@top.p), line:24:11, endln:24:12 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/BitsLogic/dut.sv, line:12:1, endln:28:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/BitsLogic/dut.sv, line:12:1, endln:28:10 |UINT:12 |vpiTypespec: \_int_typespec: @@ -304,7 +304,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:24:11, endln:24:38 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/BitsLogic/dut.sv, line:12:1, endln:28:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/BitsLogic/dut.sv, line:12:1, endln:28:10 |vpiRhs: \_constant: , line:24:15, endln:24:38 |vpiDecompile:12 @@ -320,10 +320,10 @@ design: (work@top) |vpiTypedef: \_struct_typespec: (ReplayQueueEntry), line:14:10, endln:14:16 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/BitsLogic/dut.sv, line:12:1, endln:28:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/BitsLogic/dut.sv, line:12:1, endln:28:10 |vpiName:ReplayQueueEntry |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/BitsLogic/dut.sv, line:12:1, endln:28:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/BitsLogic/dut.sv, line:12:1, endln:28:10 |vpiPacked:1 |vpiTypespecMember: \_typespec_member: (intValid), line:16:23, endln:16:31 @@ -467,17 +467,17 @@ design: (work@top) |vpiNet: \_logic_net: (work@top.b), line:26:15, endln:26:16 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/BitsLogic/dut.sv, line:12:1, endln:28:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/BitsLogic/dut.sv, line:12:1, endln:28:10 |vpiName:b |vpiFullName:work@top.b |vpiNetType:36 |uhdmtopModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/BitsLogic/dut.sv, line:12:1, endln:28:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/BitsLogic/dut.sv, line:12:1, endln:28:10 |vpiName:work@top |vpiVariables: \_logic_var: (work@top.b), line:26:15, endln:26:16 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/BitsLogic/dut.sv, line:12:1, endln:28:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/BitsLogic/dut.sv, line:12:1, endln:28:10 |vpiTypespec: \_logic_typespec: , line:26:1, endln:26:14 |vpiRange: @@ -522,7 +522,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.p), line:24:11, endln:24:12 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/BitsLogic/dut.sv, line:12:1, endln:28:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/BitsLogic/dut.sv, line:12:1, endln:28:10 |UINT:12 |vpiTypespec: \_int_typespec: @@ -533,7 +533,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:24:11, endln:24:38 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/BitsLogic/dut.sv, line:12:1, endln:28:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/BitsLogic/dut.sv, line:12:1, endln:28:10 |vpiRhs: \_constant: , line:24:15, endln:24:38 |vpiDecompile:12 diff --git a/tests/BitsOp/BitsOp.log b/tests/BitsOp/BitsOp.log index 50b3d7986e..d20bbc10f5 100644 --- a/tests/BitsOp/BitsOp.log +++ b/tests/BitsOp/BitsOp.log @@ -64,7 +64,7 @@ int_typespec 86 logic_net 10 logic_typespec 41 logic_var 4 -module 16 +module_inst 16 named_begin 1 operation 78 package 12 @@ -100,7 +100,7 @@ int_typespec 86 logic_net 10 logic_typespec 41 logic_var 4 -module 16 +module_inst 16 named_begin 2 operation 81 package 12 @@ -2192,7 +2192,7 @@ design: (work@dut) |vpiTypedef: \_enum_typespec: (flash_ctrl_pkg::flash_erase_op_e), line:66:1, endln:69:20 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/BitsOp/dut.sv, line:75:1, endln:101:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/BitsOp/dut.sv, line:75:1, endln:101:10 |vpiName:flash_ctrl_pkg::flash_erase_op_e |vpiInstance: \_package: flash_ctrl_pkg (flash_ctrl_pkg::), file:${SURELOG_DIR}/tests/BitsOp/dut.sv, line:65:1, endln:72:11 @@ -2215,7 +2215,7 @@ design: (work@dut) |vpiTypedef: \_logic_typespec: (flash_ctrl_pkg::sha_word_t), line:71:9, endln:71:21 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/BitsOp/dut.sv, line:75:1, endln:101:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/BitsOp/dut.sv, line:75:1, endln:101:10 |vpiName:flash_ctrl_pkg::sha_word_t |vpiInstance: \_package: flash_ctrl_pkg (flash_ctrl_pkg::), file:${SURELOG_DIR}/tests/BitsOp/dut.sv, line:65:1, endln:72:11 @@ -2240,17 +2240,17 @@ design: (work@dut) |vpiDefName:flash_ctrl_pkg |vpiTop:1 |uhdmallModules: -\_module: work@dmi_jtag (work@dmi_jtag), file:${SURELOG_DIR}/tests/BitsOp/dut.sv, line:104:1, endln:127:21 +\_module_inst: work@dmi_jtag (work@dmi_jtag), file:${SURELOG_DIR}/tests/BitsOp/dut.sv, line:104:1, endln:127:21 |vpiParent: \_design: (work@dut) |vpiFullName:work@dmi_jtag |vpiTypedef: \_struct_typespec: (dmi_t), line:106:11, endln:106:17 |vpiParent: - \_module: work@dmi_jtag (work@dmi_jtag), file:${SURELOG_DIR}/tests/BitsOp/dut.sv, line:104:1, endln:127:21 + \_module_inst: work@dmi_jtag (work@dmi_jtag), file:${SURELOG_DIR}/tests/BitsOp/dut.sv, line:104:1, endln:127:21 |vpiName:dmi_t |vpiInstance: - \_module: work@dmi_jtag (work@dmi_jtag), file:${SURELOG_DIR}/tests/BitsOp/dut.sv, line:104:1, endln:127:21 + \_module_inst: work@dmi_jtag (work@dmi_jtag), file:${SURELOG_DIR}/tests/BitsOp/dut.sv, line:104:1, endln:127:21 |vpiPacked:1 |vpiTypespecMember: \_typespec_member: (address), line:107:18, endln:107:25 @@ -2358,27 +2358,27 @@ design: (work@dut) |vpiNet: \_logic_net: (work@dmi_jtag.dr_d), line:112:28, endln:112:32 |vpiParent: - \_module: work@dmi_jtag (work@dmi_jtag), file:${SURELOG_DIR}/tests/BitsOp/dut.sv, line:104:1, endln:127:21 + \_module_inst: work@dmi_jtag (work@dmi_jtag), file:${SURELOG_DIR}/tests/BitsOp/dut.sv, line:104:1, endln:127:21 |vpiName:dr_d |vpiFullName:work@dmi_jtag.dr_d |vpiNetType:36 |vpiNet: \_logic_net: (work@dmi_jtag.dr_q), line:112:34, endln:112:38 |vpiParent: - \_module: work@dmi_jtag (work@dmi_jtag), file:${SURELOG_DIR}/tests/BitsOp/dut.sv, line:104:1, endln:127:21 + \_module_inst: work@dmi_jtag (work@dmi_jtag), file:${SURELOG_DIR}/tests/BitsOp/dut.sv, line:104:1, endln:127:21 |vpiName:dr_q |vpiFullName:work@dmi_jtag.dr_q |vpiNetType:36 |vpiNet: \_logic_net: (work@dmi_jtag.dmi), line:114:10, endln:114:13 |vpiParent: - \_module: work@dmi_jtag (work@dmi_jtag), file:${SURELOG_DIR}/tests/BitsOp/dut.sv, line:104:1, endln:127:21 + \_module_inst: work@dmi_jtag (work@dmi_jtag), file:${SURELOG_DIR}/tests/BitsOp/dut.sv, line:104:1, endln:127:21 |vpiName:dmi |vpiFullName:work@dmi_jtag.dmi |vpiProcess: \_always: , line:117:3, endln:125:6 |vpiParent: - \_module: work@dmi_jtag (work@dmi_jtag), file:${SURELOG_DIR}/tests/BitsOp/dut.sv, line:104:1, endln:127:21 + \_module_inst: work@dmi_jtag (work@dmi_jtag), file:${SURELOG_DIR}/tests/BitsOp/dut.sv, line:104:1, endln:127:21 |vpiStmt: \_named_begin: (work@dmi_jtag.p_shift), line:117:15, endln:125:6 |vpiParent: @@ -2484,7 +2484,7 @@ design: (work@dut) |vpiContAssign: \_cont_assign: , line:115:10, endln:115:37 |vpiParent: - \_module: work@dmi_jtag (work@dmi_jtag), file:${SURELOG_DIR}/tests/BitsOp/dut.sv, line:104:1, endln:127:21 + \_module_inst: work@dmi_jtag (work@dmi_jtag), file:${SURELOG_DIR}/tests/BitsOp/dut.sv, line:104:1, endln:127:21 |vpiRhs: \_operation: , line:115:25, endln:115:37 |vpiParent: @@ -2509,14 +2509,14 @@ design: (work@dut) |vpiActual: \_struct_net: (work@dmi_jtag.dmi), line:114:10, endln:114:13 |uhdmallModules: -\_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/BitsOp/dut.sv, line:75:1, endln:101:10 +\_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/BitsOp/dut.sv, line:75:1, endln:101:10 |vpiParent: \_design: (work@dut) |vpiFullName:work@dut |vpiParameter: \_parameter: (work@dut.WordByte), line:78:18, endln:78:26 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/BitsOp/dut.sv, line:75:1, endln:101:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/BitsOp/dut.sv, line:75:1, endln:101:10 |vpiTypespec: \_int_typespec: , line:78:14, endln:78:17 |vpiParent: @@ -2529,7 +2529,7 @@ design: (work@dut) |vpiParameter: \_parameter: (work@dut.DataWidth), line:80:18, endln:80:27 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/BitsOp/dut.sv, line:75:1, endln:101:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/BitsOp/dut.sv, line:75:1, endln:101:10 |INT:32 |vpiTypespec: \_int_typespec: , line:80:14, endln:80:17 @@ -2543,7 +2543,7 @@ design: (work@dut) |vpiParameter: \_parameter: (work@dut.DataBitWidth), line:81:18, endln:81:30 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/BitsOp/dut.sv, line:75:1, endln:101:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/BitsOp/dut.sv, line:75:1, endln:101:10 |vpiTypespec: \_int_typespec: , line:81:14, endln:81:17 |vpiParent: @@ -2556,7 +2556,7 @@ design: (work@dut) |vpiParameter: \_parameter: (work@dut.EraseBitWidth), line:82:18, endln:82:31 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/BitsOp/dut.sv, line:75:1, endln:101:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/BitsOp/dut.sv, line:75:1, endln:101:10 |UINT:1 |vpiTypespec: \_int_typespec: , line:82:14, endln:82:17 @@ -2570,7 +2570,7 @@ design: (work@dut) |vpiParameter: \_parameter: (work@dut.HashWordBits), line:84:27, endln:84:39 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/BitsOp/dut.sv, line:75:1, endln:101:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/BitsOp/dut.sv, line:75:1, endln:101:10 |vpiTypespec: \_int_typespec: , line:84:14, endln:84:26 |vpiParent: @@ -2581,7 +2581,7 @@ design: (work@dut) |vpiParameter: \_parameter: (work@dut.REQFIFO_WIDTH), line:86:27, endln:86:40 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/BitsOp/dut.sv, line:75:1, endln:101:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/BitsOp/dut.sv, line:75:1, endln:101:10 |vpiTypespec: \_int_typespec: , line:86:14, endln:86:26 |vpiParent: @@ -2592,7 +2592,7 @@ design: (work@dut) |vpiParamAssign: \_param_assign: , line:78:18, endln:78:48 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/BitsOp/dut.sv, line:75:1, endln:101:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/BitsOp/dut.sv, line:75:1, endln:101:10 |vpiRhs: \_operation: , line:78:29, endln:78:48 |vpiOpType:12 @@ -2617,7 +2617,7 @@ design: (work@dut) |vpiParamAssign: \_param_assign: , line:80:18, endln:80:47 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/BitsOp/dut.sv, line:75:1, endln:101:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/BitsOp/dut.sv, line:75:1, endln:101:10 |vpiRhs: \_constant: , line:80:30, endln:80:39 |vpiDecompile:32 @@ -2631,7 +2631,7 @@ design: (work@dut) |vpiParamAssign: \_param_assign: , line:81:18, endln:81:52 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/BitsOp/dut.sv, line:75:1, endln:101:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/BitsOp/dut.sv, line:75:1, endln:101:10 |vpiRhs: \_sys_func_call: ($clog2), line:81:33, endln:81:52 |vpiArgument: @@ -2658,7 +2658,7 @@ design: (work@dut) |vpiParamAssign: \_param_assign: , line:82:18, endln:82:57 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/BitsOp/dut.sv, line:75:1, endln:101:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/BitsOp/dut.sv, line:75:1, endln:101:10 |vpiRhs: \_constant: , line:82:34, endln:82:57 |vpiDecompile:1 @@ -2672,7 +2672,7 @@ design: (work@dut) |vpiParamAssign: \_param_assign: , line:84:27, endln:84:67 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/BitsOp/dut.sv, line:75:1, endln:101:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/BitsOp/dut.sv, line:75:1, endln:101:10 |vpiRhs: \_sys_func_call: ($clog2), line:84:42, endln:84:67 |vpiArgument: @@ -2689,7 +2689,7 @@ design: (work@dut) |vpiParamAssign: \_param_assign: , line:86:27, endln:86:70 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/BitsOp/dut.sv, line:75:1, endln:101:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/BitsOp/dut.sv, line:75:1, endln:101:10 |vpiRhs: \_operation: , line:86:43, endln:86:70 |vpiOpType:11 @@ -2714,10 +2714,10 @@ design: (work@dut) |vpiTypedef: \_bit_typespec: (MyBits), line:97:11, endln:97:31 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/BitsOp/dut.sv, line:75:1, endln:101:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/BitsOp/dut.sv, line:75:1, endln:101:10 |vpiName:MyBits |vpiInstance: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/BitsOp/dut.sv, line:75:1, endln:101:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/BitsOp/dut.sv, line:75:1, endln:101:10 |vpiRange: \_range: , line:97:14, endln:97:31 |vpiLeftRange: @@ -2740,10 +2740,10 @@ design: (work@dut) |vpiTypedef: \_struct_typespec: (MyType), line:92:11, endln:92:17 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/BitsOp/dut.sv, line:75:1, endln:101:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/BitsOp/dut.sv, line:75:1, endln:101:10 |vpiName:MyType |vpiInstance: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/BitsOp/dut.sv, line:75:1, endln:101:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/BitsOp/dut.sv, line:75:1, endln:101:10 |vpiTypespecMember: \_typespec_member: (valid), line:93:11, endln:93:16 |vpiParent: @@ -2803,33 +2803,33 @@ design: (work@dut) |vpiNet: \_logic_net: (work@dut.tl_h_i), line:75:39, endln:75:45 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/BitsOp/dut.sv, line:75:1, endln:101:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/BitsOp/dut.sv, line:75:1, endln:101:10 |vpiName:tl_h_i |vpiFullName:work@dut.tl_h_i |vpiNet: \_logic_net: (work@dut.err_source), line:88:38, endln:88:48 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/BitsOp/dut.sv, line:75:1, endln:101:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/BitsOp/dut.sv, line:75:1, endln:101:10 |vpiName:err_source |vpiFullName:work@dut.err_source |vpiNetType:36 |vpiNet: \_logic_net: (work@dut.err_size), line:89:38, endln:89:46 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/BitsOp/dut.sv, line:75:1, endln:101:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/BitsOp/dut.sv, line:75:1, endln:101:10 |vpiName:err_size |vpiFullName:work@dut.err_size |vpiNetType:36 |vpiNet: \_logic_net: (work@dut.b), line:98:10, endln:98:11 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/BitsOp/dut.sv, line:75:1, endln:101:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/BitsOp/dut.sv, line:75:1, endln:101:10 |vpiName:b |vpiFullName:work@dut.b |vpiPort: \_port: (tl_h_i), line:75:39, endln:75:45 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/BitsOp/dut.sv, line:75:1, endln:101:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/BitsOp/dut.sv, line:75:1, endln:101:10 |vpiName:tl_h_i |vpiDirection:1 |vpiLowConn: @@ -2839,12 +2839,12 @@ design: (work@dut) |vpiTypedef: \_struct_typespec: (tlul_pkg::tl_h2d_t), line:32:11, endln:32:17 |uhdmtopModules: -\_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/BitsOp/dut.sv, line:75:1, endln:101:10 +\_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/BitsOp/dut.sv, line:75:1, endln:101:10 |vpiName:work@dut |vpiVariables: \_logic_var: (work@dut.err_source), line:88:38, endln:88:48 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/BitsOp/dut.sv, line:75:1, endln:101:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/BitsOp/dut.sv, line:75:1, endln:101:10 |vpiTypespec: \_logic_typespec: , line:88:3, endln:88:37 |vpiRange: @@ -2889,7 +2889,7 @@ design: (work@dut) |vpiVariables: \_logic_var: (work@dut.err_size), line:89:38, endln:89:46 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/BitsOp/dut.sv, line:75:1, endln:101:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/BitsOp/dut.sv, line:75:1, endln:101:10 |vpiTypespec: \_logic_typespec: , line:89:3, endln:89:35 |vpiRange: @@ -2934,7 +2934,7 @@ design: (work@dut) |vpiVariables: \_bit_var: (work@dut.b), line:98:10, endln:98:11 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/BitsOp/dut.sv, line:75:1, endln:101:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/BitsOp/dut.sv, line:75:1, endln:101:10 |vpiTypespec: \_bit_typespec: (MyBits), line:97:11, endln:97:31 |vpiName:MyBits @@ -2965,7 +2965,7 @@ design: (work@dut) |vpiParameter: \_parameter: (work@dut.WordByte), line:78:18, endln:78:26 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/BitsOp/dut.sv, line:75:1, endln:101:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/BitsOp/dut.sv, line:75:1, endln:101:10 |vpiTypespec: \_int_typespec: , line:78:14, endln:78:17 |vpiParent: @@ -2978,7 +2978,7 @@ design: (work@dut) |vpiParameter: \_parameter: (work@dut.DataWidth), line:80:18, endln:80:27 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/BitsOp/dut.sv, line:75:1, endln:101:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/BitsOp/dut.sv, line:75:1, endln:101:10 |INT:32 |vpiTypespec: \_int_typespec: , line:80:14, endln:80:17 @@ -2992,7 +2992,7 @@ design: (work@dut) |vpiParameter: \_parameter: (work@dut.DataBitWidth), line:81:18, endln:81:30 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/BitsOp/dut.sv, line:75:1, endln:101:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/BitsOp/dut.sv, line:75:1, endln:101:10 |vpiTypespec: \_int_typespec: , line:81:14, endln:81:17 |vpiParent: @@ -3005,7 +3005,7 @@ design: (work@dut) |vpiParameter: \_parameter: (work@dut.EraseBitWidth), line:82:18, endln:82:31 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/BitsOp/dut.sv, line:75:1, endln:101:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/BitsOp/dut.sv, line:75:1, endln:101:10 |UINT:1 |vpiTypespec: \_int_typespec: , line:82:14, endln:82:17 @@ -3019,7 +3019,7 @@ design: (work@dut) |vpiParameter: \_parameter: (work@dut.HashWordBits), line:84:27, endln:84:39 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/BitsOp/dut.sv, line:75:1, endln:101:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/BitsOp/dut.sv, line:75:1, endln:101:10 |vpiTypespec: \_int_typespec: , line:84:14, endln:84:26 |vpiParent: @@ -3030,7 +3030,7 @@ design: (work@dut) |vpiParameter: \_parameter: (work@dut.REQFIFO_WIDTH), line:86:27, endln:86:40 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/BitsOp/dut.sv, line:75:1, endln:101:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/BitsOp/dut.sv, line:75:1, endln:101:10 |vpiTypespec: \_int_typespec: , line:86:14, endln:86:26 |vpiParent: @@ -3041,7 +3041,7 @@ design: (work@dut) |vpiParamAssign: \_param_assign: , line:78:18, endln:78:48 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/BitsOp/dut.sv, line:75:1, endln:101:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/BitsOp/dut.sv, line:75:1, endln:101:10 |vpiRhs: \_constant: , line:78:29, endln:78:48 |vpiDecompile:4 @@ -3055,7 +3055,7 @@ design: (work@dut) |vpiParamAssign: \_param_assign: , line:80:18, endln:80:47 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/BitsOp/dut.sv, line:75:1, endln:101:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/BitsOp/dut.sv, line:75:1, endln:101:10 |vpiRhs: \_constant: , line:80:30, endln:80:47 |vpiDecompile:32 @@ -3069,7 +3069,7 @@ design: (work@dut) |vpiParamAssign: \_param_assign: , line:81:18, endln:81:52 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/BitsOp/dut.sv, line:75:1, endln:101:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/BitsOp/dut.sv, line:75:1, endln:101:10 |vpiRhs: \_constant: , line:81:33, endln:81:52 |vpiDecompile:2 @@ -3083,7 +3083,7 @@ design: (work@dut) |vpiParamAssign: \_param_assign: , line:82:18, endln:82:57 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/BitsOp/dut.sv, line:75:1, endln:101:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/BitsOp/dut.sv, line:75:1, endln:101:10 |vpiRhs: \_constant: , line:82:34, endln:82:57 |vpiDecompile:1 @@ -3097,7 +3097,7 @@ design: (work@dut) |vpiParamAssign: \_param_assign: , line:84:27, endln:84:67 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/BitsOp/dut.sv, line:75:1, endln:101:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/BitsOp/dut.sv, line:75:1, endln:101:10 |vpiRhs: \_constant: , line:84:42, endln:84:67 |vpiDecompile:5 @@ -3111,7 +3111,7 @@ design: (work@dut) |vpiParamAssign: \_param_assign: , line:86:27, endln:86:70 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/BitsOp/dut.sv, line:75:1, endln:101:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/BitsOp/dut.sv, line:75:1, endln:101:10 |vpiRhs: \_constant: , line:86:43, endln:86:70 |vpiDecompile:83 @@ -3137,7 +3137,7 @@ design: (work@dut) |vpiNet: \_struct_net: (work@dut.tl_h_i), line:75:39, endln:75:45 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/BitsOp/dut.sv, line:75:1, endln:101:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/BitsOp/dut.sv, line:75:1, endln:101:10 |vpiTypespec: \_struct_typespec: (tlul_pkg::tl_h2d_t), line:32:11, endln:32:17 |vpiName:tl_h_i @@ -3146,7 +3146,7 @@ design: (work@dut) |vpiPort: \_port: (tl_h_i), line:75:39, endln:75:45 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/BitsOp/dut.sv, line:75:1, endln:101:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/BitsOp/dut.sv, line:75:1, endln:101:10 |vpiName:tl_h_i |vpiDirection:1 |vpiLowConn: @@ -3160,14 +3160,14 @@ design: (work@dut) |vpiTypedef: \_struct_typespec: (tlul_pkg::tl_h2d_t), line:32:11, endln:32:17 |vpiInstance: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/BitsOp/dut.sv, line:75:1, endln:101:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/BitsOp/dut.sv, line:75:1, endln:101:10 |uhdmtopModules: -\_module: work@dmi_jtag (work@dmi_jtag), file:${SURELOG_DIR}/tests/BitsOp/dut.sv, line:104:1, endln:127:21 +\_module_inst: work@dmi_jtag (work@dmi_jtag), file:${SURELOG_DIR}/tests/BitsOp/dut.sv, line:104:1, endln:127:21 |vpiName:work@dmi_jtag |vpiVariables: \_logic_var: (work@dmi_jtag.dr_d), line:112:28, endln:112:32 |vpiParent: - \_module: work@dmi_jtag (work@dmi_jtag), file:${SURELOG_DIR}/tests/BitsOp/dut.sv, line:104:1, endln:127:21 + \_module_inst: work@dmi_jtag (work@dmi_jtag), file:${SURELOG_DIR}/tests/BitsOp/dut.sv, line:104:1, endln:127:21 |vpiTypespec: \_logic_typespec: , line:112:3, endln:112:27 |vpiRange: @@ -3212,7 +3212,7 @@ design: (work@dut) |vpiVariables: \_logic_var: (work@dmi_jtag.dr_q), line:112:34, endln:112:38 |vpiParent: - \_module: work@dmi_jtag (work@dmi_jtag), file:${SURELOG_DIR}/tests/BitsOp/dut.sv, line:104:1, endln:127:21 + \_module_inst: work@dmi_jtag (work@dmi_jtag), file:${SURELOG_DIR}/tests/BitsOp/dut.sv, line:104:1, endln:127:21 |vpiTypespec: \_logic_typespec: , line:112:3, endln:112:27 |vpiName:dr_q @@ -3243,7 +3243,7 @@ design: (work@dut) |vpiNet: \_struct_net: (work@dmi_jtag.dmi), line:114:10, endln:114:13 |vpiParent: - \_module: work@dmi_jtag (work@dmi_jtag), file:${SURELOG_DIR}/tests/BitsOp/dut.sv, line:104:1, endln:127:21 + \_module_inst: work@dmi_jtag (work@dmi_jtag), file:${SURELOG_DIR}/tests/BitsOp/dut.sv, line:104:1, endln:127:21 |vpiTypespec: \_struct_typespec: (dmi_t), line:106:11, endln:106:17 |vpiName:dmi @@ -3264,7 +3264,7 @@ design: (work@dut) |vpiProcess: \_always: , line:117:3, endln:125:6 |vpiParent: - \_module: work@dmi_jtag (work@dmi_jtag), file:${SURELOG_DIR}/tests/BitsOp/dut.sv, line:104:1, endln:127:21 + \_module_inst: work@dmi_jtag (work@dmi_jtag), file:${SURELOG_DIR}/tests/BitsOp/dut.sv, line:104:1, endln:127:21 |vpiStmt: \_named_begin: (work@dmi_jtag.p_shift), line:117:15, endln:125:6 |vpiParent: @@ -3359,7 +3359,7 @@ design: (work@dut) |vpiContAssign: \_cont_assign: , line:115:10, endln:115:37 |vpiParent: - \_module: work@dmi_jtag (work@dmi_jtag), file:${SURELOG_DIR}/tests/BitsOp/dut.sv, line:104:1, endln:127:21 + \_module_inst: work@dmi_jtag (work@dmi_jtag), file:${SURELOG_DIR}/tests/BitsOp/dut.sv, line:104:1, endln:127:21 |vpiRhs: \_operation: , line:115:25, endln:115:37 |vpiParent: @@ -3370,7 +3370,7 @@ design: (work@dut) \_operation: , line:115:25, endln:115:37 |vpiName:dmi_t |vpiInstance: - \_module: work@dmi_jtag (work@dmi_jtag), file:${SURELOG_DIR}/tests/BitsOp/dut.sv, line:104:1, endln:127:21 + \_module_inst: work@dmi_jtag (work@dmi_jtag), file:${SURELOG_DIR}/tests/BitsOp/dut.sv, line:104:1, endln:127:21 |vpiPacked:1 |vpiTypespecMember: \_typespec_member: (address), line:107:18, endln:107:25 diff --git a/tests/BitsStructMember/BitsStructMember.log b/tests/BitsStructMember/BitsStructMember.log index a8b02ebf7b..70e657c1a4 100644 --- a/tests/BitsStructMember/BitsStructMember.log +++ b/tests/BitsStructMember/BitsStructMember.log @@ -41,7 +41,7 @@ int_typespec 7 int_var 1 logic_net 6 logic_typespec 11 -module 6 +module_inst 6 operation 15 package 3 param_assign 4 @@ -72,7 +72,7 @@ int_typespec 7 int_var 2 logic_net 6 logic_typespec 11 -module 6 +module_inst 6 operation 20 package 3 param_assign 4 @@ -433,7 +433,7 @@ design: (work@top) |vpiDefName:keymgr_pkg |vpiTop:1 |uhdmallModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/BitsStructMember/dut.sv, line:16:1, endln:28:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/BitsStructMember/dut.sv, line:16:1, endln:28:10 |vpiParent: \_design: (work@top) |vpiFullName:work@top @@ -441,21 +441,21 @@ design: (work@top) |vpiNet: \_logic_net: (work@top.keymgr_data_i), line:16:48, endln:16:61 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/BitsStructMember/dut.sv, line:16:1, endln:28:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/BitsStructMember/dut.sv, line:16:1, endln:28:10 |vpiName:keymgr_data_i |vpiFullName:work@top.keymgr_data_i |vpiNetType:1 |vpiNet: \_logic_net: (work@top.kmac_mask_o), line:17:30, endln:17:41 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/BitsStructMember/dut.sv, line:16:1, endln:28:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/BitsStructMember/dut.sv, line:16:1, endln:28:10 |vpiName:kmac_mask_o |vpiFullName:work@top.kmac_mask_o |vpiNetType:36 |vpiPort: \_port: (keymgr_data_i), line:16:48, endln:16:61 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/BitsStructMember/dut.sv, line:16:1, endln:28:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/BitsStructMember/dut.sv, line:16:1, endln:28:10 |vpiName:keymgr_data_i |vpiDirection:1 |vpiLowConn: @@ -467,7 +467,7 @@ design: (work@top) |vpiPort: \_port: (kmac_mask_o), line:17:30, endln:17:41 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/BitsStructMember/dut.sv, line:16:1, endln:28:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/BitsStructMember/dut.sv, line:16:1, endln:28:10 |vpiName:kmac_mask_o |vpiDirection:2 |vpiLowConn: @@ -509,7 +509,7 @@ design: (work@top) |vpiProcess: \_always: , line:19:3, endln:27:6 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/BitsStructMember/dut.sv, line:16:1, endln:28:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/BitsStructMember/dut.sv, line:16:1, endln:28:10 |vpiStmt: \_begin: (work@top), line:19:15, endln:27:6 |vpiParent: @@ -703,14 +703,14 @@ design: (work@top) |vpiConstType:9 |vpiAlwaysType:2 |uhdmtopModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/BitsStructMember/dut.sv, line:16:1, endln:28:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/BitsStructMember/dut.sv, line:16:1, endln:28:10 |vpiName:work@top |vpiDefName:work@top |vpiTop:1 |vpiNet: \_struct_net: (work@top.keymgr_data_i), line:16:48, endln:16:61 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/BitsStructMember/dut.sv, line:16:1, endln:28:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/BitsStructMember/dut.sv, line:16:1, endln:28:10 |vpiTypespec: \_struct_typespec: (keymgr_pkg::kmac_data_req_t), line:5:11, endln:5:17 |vpiName:keymgr_data_i @@ -719,7 +719,7 @@ design: (work@top) |vpiNet: \_logic_net: (work@top.kmac_mask_o), line:17:30, endln:17:41 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/BitsStructMember/dut.sv, line:16:1, endln:28:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/BitsStructMember/dut.sv, line:16:1, endln:28:10 |vpiTypespec: \_logic_typespec: , line:17:9, endln:17:29 |vpiRange: @@ -771,7 +771,7 @@ design: (work@top) |vpiPort: \_port: (keymgr_data_i), line:16:48, endln:16:61 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/BitsStructMember/dut.sv, line:16:1, endln:28:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/BitsStructMember/dut.sv, line:16:1, endln:28:10 |vpiName:keymgr_data_i |vpiDirection:1 |vpiLowConn: @@ -785,11 +785,11 @@ design: (work@top) |vpiTypedef: \_struct_typespec: (keymgr_pkg::kmac_data_req_t), line:5:11, endln:5:17 |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/BitsStructMember/dut.sv, line:16:1, endln:28:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/BitsStructMember/dut.sv, line:16:1, endln:28:10 |vpiPort: \_port: (kmac_mask_o), line:17:30, endln:17:41 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/BitsStructMember/dut.sv, line:16:1, endln:28:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/BitsStructMember/dut.sv, line:16:1, endln:28:10 |vpiName:kmac_mask_o |vpiDirection:2 |vpiLowConn: @@ -836,11 +836,11 @@ design: (work@top) |UINT:0 |vpiConstType:9 |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/BitsStructMember/dut.sv, line:16:1, endln:28:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/BitsStructMember/dut.sv, line:16:1, endln:28:10 |vpiProcess: \_always: , line:19:3, endln:27:6 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/BitsStructMember/dut.sv, line:16:1, endln:28:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/BitsStructMember/dut.sv, line:16:1, endln:28:10 |vpiStmt: \_begin: (work@top), line:19:15, endln:27:6 |vpiParent: diff --git a/tests/BlackBox/BlackBox.log b/tests/BlackBox/BlackBox.log index ec738ac02e..363c568ad9 100644 --- a/tests/BlackBox/BlackBox.log +++ b/tests/BlackBox/BlackBox.log @@ -165,7 +165,7 @@ hier_path 1 int_typespec 2 int_var 1 logic_net 2 -module 8 +module_inst 8 operation 2 parameter 1 ref_obj 5 @@ -183,7 +183,7 @@ hier_path 2 int_typespec 2 int_var 2 logic_net 2 -module 9 +module_inst 9 operation 2 parameter 1 ref_obj 10 @@ -201,7 +201,7 @@ design: (work@top) |vpiElaborated:1 |vpiName:work@top |uhdmallModules: -\_module: work@core (work@core), file:${SURELOG_DIR}/tests/BlackBox/dut.sv, line:5:1, endln:9:10 +\_module_inst: work@core (work@core), file:${SURELOG_DIR}/tests/BlackBox/dut.sv, line:5:1, endln:9:10 |vpiParent: \_design: (work@top) |vpiFullName:work@core @@ -209,17 +209,17 @@ design: (work@top) |vpiNet: \_logic_net: (work@core.wb_writeback_en), line:7:5, endln:7:20 |vpiParent: - \_module: work@core (work@core), file:${SURELOG_DIR}/tests/BlackBox/dut.sv, line:5:1, endln:9:10 + \_module_inst: work@core (work@core), file:${SURELOG_DIR}/tests/BlackBox/dut.sv, line:5:1, endln:9:10 |vpiName:wb_writeback_en |vpiFullName:work@core.wb_writeback_en |uhdmallModules: -\_module: work@nyuzi (work@nyuzi), file:${SURELOG_DIR}/tests/BlackBox/dut.sv, line:12:1, endln:21:10 +\_module_inst: work@nyuzi (work@nyuzi), file:${SURELOG_DIR}/tests/BlackBox/dut.sv, line:12:1, endln:21:10 |vpiParent: \_design: (work@top) |vpiFullName:work@nyuzi |vpiDefName:work@nyuzi |uhdmallModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/BlackBox/dut.sv, line:25:1, endln:34:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/BlackBox/dut.sv, line:25:1, endln:34:10 |vpiParent: \_design: (work@top) |vpiFullName:work@top @@ -227,7 +227,7 @@ design: (work@top) |vpiContAssign: \_cont_assign: , line:31:12, endln:31:54 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/BlackBox/dut.sv, line:25:1, endln:34:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/BlackBox/dut.sv, line:25:1, endln:34:10 |vpiRhs: \_hier_path: (nyuzi.core_gen[0].core.wb_writeback_en), line:31:16, endln:31:54 |vpiParent: @@ -270,7 +270,7 @@ design: (work@top) |vpiActual: \_logic_net: (o) |uhdmtopModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/BlackBox/dut.sv, line:25:1, endln:34:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/BlackBox/dut.sv, line:25:1, endln:34:10 |vpiName:work@top |vpiDefName:work@top |vpiTop:1 @@ -279,21 +279,21 @@ design: (work@top) |vpiName:o |vpiNetType:1 |vpiTopModule:1 - |vpiModule: - \_module: work@nyuzi (work@top.nyuzi), file:${SURELOG_DIR}/tests/BlackBox/dut.sv, line:29:1, endln:29:16 + |vpiModuleInst: + \_module_inst: work@nyuzi (work@top.nyuzi), file:${SURELOG_DIR}/tests/BlackBox/dut.sv, line:29:1, endln:29:16 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/BlackBox/dut.sv, line:25:1, endln:34:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/BlackBox/dut.sv, line:25:1, endln:34:10 |vpiName:nyuzi |vpiFullName:work@top.nyuzi |vpiDefName:work@nyuzi |vpiDefFile:${SURELOG_DIR}/tests/BlackBox/dut.sv |vpiDefLineNo:12 |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/BlackBox/dut.sv, line:25:1, endln:34:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/BlackBox/dut.sv, line:25:1, endln:34:10 |vpiGenScopeArray: \_gen_scope_array: (work@top.nyuzi.core_gen[0]), line:17:9, endln:19:12 |vpiParent: - \_module: work@nyuzi (work@top.nyuzi), file:${SURELOG_DIR}/tests/BlackBox/dut.sv, line:29:1, endln:29:16 + \_module_inst: work@nyuzi (work@top.nyuzi), file:${SURELOG_DIR}/tests/BlackBox/dut.sv, line:29:1, endln:29:16 |vpiName:core_gen[0] |vpiFullName:work@top.nyuzi.core_gen[0] |vpiGenScope: @@ -311,8 +311,8 @@ design: (work@top) |vpiLocalParam:1 |vpiName:core_idx |vpiFullName:work@top.nyuzi.core_gen[0].core_idx - |vpiModule: - \_module: work@core (work@top.nyuzi.core_gen[0].core), file:${SURELOG_DIR}/tests/BlackBox/dut.sv, line:18:13, endln:18:26 + |vpiModuleInst: + \_module_inst: work@core (work@top.nyuzi.core_gen[0].core), file:${SURELOG_DIR}/tests/BlackBox/dut.sv, line:18:13, endln:18:26 |vpiParent: \_gen_scope: (work@top.nyuzi.core_gen[0]) |vpiName:core @@ -320,7 +320,7 @@ design: (work@top) |vpiVariables: \_int_var: (work@top.nyuzi.core_gen[0].core.wb_writeback_en), line:7:5, endln:7:20 |vpiParent: - \_module: work@core (work@top.nyuzi.core_gen[0].core), file:${SURELOG_DIR}/tests/BlackBox/dut.sv, line:18:13, endln:18:26 + \_module_inst: work@core (work@top.nyuzi.core_gen[0].core), file:${SURELOG_DIR}/tests/BlackBox/dut.sv, line:18:13, endln:18:26 |vpiTypespec: \_int_typespec: , line:7:1, endln:7:4 |vpiSigned:1 @@ -328,14 +328,14 @@ design: (work@top) |vpiFullName:work@top.nyuzi.core_gen[0].core.wb_writeback_en |vpiVisibility:1 |vpiInstance: - \_module: work@core (work@top.nyuzi.core_gen[0].core), file:${SURELOG_DIR}/tests/BlackBox/dut.sv, line:18:13, endln:18:26 + \_module_inst: work@core (work@top.nyuzi.core_gen[0].core), file:${SURELOG_DIR}/tests/BlackBox/dut.sv, line:18:13, endln:18:26 |vpiDefName:work@core |vpiDefFile:${SURELOG_DIR}/tests/BlackBox/dut.sv |vpiDefLineNo:5 |vpiContAssign: \_cont_assign: , line:31:12, endln:31:54 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/BlackBox/dut.sv, line:25:1, endln:34:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/BlackBox/dut.sv, line:25:1, endln:34:10 |vpiRhs: \_hier_path: (nyuzi.core_gen[0].core.wb_writeback_en), line:31:16, endln:31:54 |vpiParent: @@ -347,7 +347,7 @@ design: (work@top) \_hier_path: (nyuzi.core_gen[0].core.wb_writeback_en), line:31:16, endln:31:54 |vpiName:nyuzi |vpiActual: - \_module: work@nyuzi (work@top.nyuzi), file:${SURELOG_DIR}/tests/BlackBox/dut.sv, line:29:1, endln:29:16 + \_module_inst: work@nyuzi (work@top.nyuzi), file:${SURELOG_DIR}/tests/BlackBox/dut.sv, line:29:1, endln:29:16 |vpiActual: \_bit_select: (core_gen), line:31:22, endln:31:30 |vpiParent: @@ -367,7 +367,7 @@ design: (work@top) \_hier_path: (nyuzi.core_gen[0].core.wb_writeback_en), line:31:16, endln:31:54 |vpiName:core |vpiActual: - \_module: work@core (work@top.nyuzi.core_gen[0].core), file:${SURELOG_DIR}/tests/BlackBox/dut.sv, line:18:13, endln:18:26 + \_module_inst: work@core (work@top.nyuzi.core_gen[0].core), file:${SURELOG_DIR}/tests/BlackBox/dut.sv, line:18:13, endln:18:26 |vpiActual: \_ref_obj: (wb_writeback_en), line:31:39, endln:31:54 |vpiParent: diff --git a/tests/BlackBox/BlackBoxInst.log b/tests/BlackBox/BlackBoxInst.log index dc493dd423..e8c67b0a32 100644 --- a/tests/BlackBox/BlackBoxInst.log +++ b/tests/BlackBox/BlackBoxInst.log @@ -165,7 +165,7 @@ gen_scope 1 gen_scope_array 1 hier_path 1 logic_net 2 -module 7 +module_inst 7 operation 2 ref_obj 5 === UHDM Object Stats End === @@ -180,7 +180,7 @@ gen_scope 2 gen_scope_array 2 hier_path 2 logic_net 2 -module 7 +module_inst 7 operation 2 ref_obj 10 === UHDM Object Stats End === @@ -199,7 +199,7 @@ design: (work@top) |vpiElaborated:1 |vpiName:work@top |uhdmallModules: -\_module: work@core (work@core), file:${SURELOG_DIR}/tests/BlackBox/dut.sv, line:5:1, endln:9:10 +\_module_inst: work@core (work@core), file:${SURELOG_DIR}/tests/BlackBox/dut.sv, line:5:1, endln:9:10 |vpiParent: \_design: (work@top) |vpiFullName:work@core @@ -207,17 +207,17 @@ design: (work@top) |vpiNet: \_logic_net: (work@core.wb_writeback_en), line:7:5, endln:7:20 |vpiParent: - \_module: work@core (work@core), file:${SURELOG_DIR}/tests/BlackBox/dut.sv, line:5:1, endln:9:10 + \_module_inst: work@core (work@core), file:${SURELOG_DIR}/tests/BlackBox/dut.sv, line:5:1, endln:9:10 |vpiName:wb_writeback_en |vpiFullName:work@core.wb_writeback_en |uhdmallModules: -\_module: work@nyuzi (work@nyuzi), file:${SURELOG_DIR}/tests/BlackBox/dut.sv, line:12:1, endln:21:10 +\_module_inst: work@nyuzi (work@nyuzi), file:${SURELOG_DIR}/tests/BlackBox/dut.sv, line:12:1, endln:21:10 |vpiParent: \_design: (work@top) |vpiFullName:work@nyuzi |vpiDefName:work@nyuzi |uhdmallModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/BlackBox/dut.sv, line:25:1, endln:34:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/BlackBox/dut.sv, line:25:1, endln:34:10 |vpiParent: \_design: (work@top) |vpiFullName:work@top @@ -225,7 +225,7 @@ design: (work@top) |vpiContAssign: \_cont_assign: , line:31:12, endln:31:54 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/BlackBox/dut.sv, line:25:1, endln:34:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/BlackBox/dut.sv, line:25:1, endln:34:10 |vpiRhs: \_hier_path: (nyuzi.core_gen[0].core.wb_writeback_en), line:31:16, endln:31:54 |vpiParent: @@ -268,7 +268,7 @@ design: (work@top) |vpiActual: \_logic_net: (o) |uhdmtopModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/BlackBox/dut.sv, line:25:1, endln:34:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/BlackBox/dut.sv, line:25:1, endln:34:10 |vpiName:work@top |vpiDefName:work@top |vpiTop:1 @@ -277,21 +277,21 @@ design: (work@top) |vpiName:o |vpiNetType:1 |vpiTopModule:1 - |vpiModule: - \_module: work@nyuzi (work@top.nyuzi), file:${SURELOG_DIR}/tests/BlackBox/dut.sv, line:29:1, endln:29:16 + |vpiModuleInst: + \_module_inst: work@nyuzi (work@top.nyuzi), file:${SURELOG_DIR}/tests/BlackBox/dut.sv, line:29:1, endln:29:16 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/BlackBox/dut.sv, line:25:1, endln:34:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/BlackBox/dut.sv, line:25:1, endln:34:10 |vpiName:nyuzi |vpiFullName:work@top.nyuzi |vpiDefName:work@nyuzi |vpiDefFile:${SURELOG_DIR}/tests/BlackBox/dut.sv |vpiDefLineNo:12 |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/BlackBox/dut.sv, line:25:1, endln:34:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/BlackBox/dut.sv, line:25:1, endln:34:10 |vpiGenScopeArray: \_gen_scope_array: (work@top.nyuzi.core_gen[0]), line:17:9, endln:19:12 |vpiParent: - \_module: work@nyuzi (work@top.nyuzi), file:${SURELOG_DIR}/tests/BlackBox/dut.sv, line:29:1, endln:29:16 + \_module_inst: work@nyuzi (work@top.nyuzi), file:${SURELOG_DIR}/tests/BlackBox/dut.sv, line:29:1, endln:29:16 |vpiName:core_gen[0] |vpiFullName:work@top.nyuzi.core_gen[0] |vpiGenScope: @@ -302,7 +302,7 @@ design: (work@top) |vpiContAssign: \_cont_assign: , line:31:12, endln:31:54 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/BlackBox/dut.sv, line:25:1, endln:34:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/BlackBox/dut.sv, line:25:1, endln:34:10 |vpiRhs: \_hier_path: (nyuzi.core_gen[0].core.wb_writeback_en), line:31:16, endln:31:54 |vpiParent: @@ -314,7 +314,7 @@ design: (work@top) \_hier_path: (nyuzi.core_gen[0].core.wb_writeback_en), line:31:16, endln:31:54 |vpiName:nyuzi |vpiActual: - \_module: work@nyuzi (work@top.nyuzi), file:${SURELOG_DIR}/tests/BlackBox/dut.sv, line:29:1, endln:29:16 + \_module_inst: work@nyuzi (work@top.nyuzi), file:${SURELOG_DIR}/tests/BlackBox/dut.sv, line:29:1, endln:29:16 |vpiActual: \_bit_select: (core_gen), line:31:22, endln:31:30 |vpiParent: diff --git a/tests/BlackBox/BlackBoxInstTop.log b/tests/BlackBox/BlackBoxInstTop.log index baf1bbaa6e..df779dae31 100644 --- a/tests/BlackBox/BlackBoxInstTop.log +++ b/tests/BlackBox/BlackBoxInstTop.log @@ -157,14 +157,14 @@ n<> u<121> t c<1> l<5:1> el<34:10> === UHDM Object Stats Begin (Non-Elaborated Model) === design 1 logic_net 1 -module 4 +module_inst 4 === UHDM Object Stats End === [INF:UH0707] Elaborating UHDM... === UHDM Object Stats Begin (Elaborated Model) === design 1 logic_net 1 -module 4 +module_inst 4 === UHDM Object Stats End === [INF:UH0708] Writing UHDM DB: ${SURELOG_DIR}/build/regression/BlackBoxInstTop/slpp_all/surelog.uhdm ... @@ -179,7 +179,7 @@ design: (work@top) |vpiElaborated:1 |vpiName:work@top |uhdmallModules: -\_module: work@core (work@core), file:${SURELOG_DIR}/tests/BlackBox/dut.sv, line:5:1, endln:9:10 +\_module_inst: work@core (work@core), file:${SURELOG_DIR}/tests/BlackBox/dut.sv, line:5:1, endln:9:10 |vpiParent: \_design: (work@top) |vpiFullName:work@core @@ -187,23 +187,23 @@ design: (work@top) |vpiNet: \_logic_net: (work@core.wb_writeback_en), line:7:5, endln:7:20 |vpiParent: - \_module: work@core (work@core), file:${SURELOG_DIR}/tests/BlackBox/dut.sv, line:5:1, endln:9:10 + \_module_inst: work@core (work@core), file:${SURELOG_DIR}/tests/BlackBox/dut.sv, line:5:1, endln:9:10 |vpiName:wb_writeback_en |vpiFullName:work@core.wb_writeback_en |uhdmallModules: -\_module: work@nyuzi (work@nyuzi), file:${SURELOG_DIR}/tests/BlackBox/dut.sv, line:12:1, endln:21:10 +\_module_inst: work@nyuzi (work@nyuzi), file:${SURELOG_DIR}/tests/BlackBox/dut.sv, line:12:1, endln:21:10 |vpiParent: \_design: (work@top) |vpiFullName:work@nyuzi |vpiDefName:work@nyuzi |uhdmallModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/BlackBox/dut.sv, line:25:1, endln:34:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/BlackBox/dut.sv, line:25:1, endln:34:10 |vpiParent: \_design: (work@top) |vpiFullName:work@top |vpiDefName:work@top |uhdmtopModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/BlackBox/dut.sv, line:25:1, endln:34:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/BlackBox/dut.sv, line:25:1, endln:34:10 |vpiName:work@top |vpiDefName:work@top |vpiTop:1 diff --git a/tests/BlackBox/BlackBoxMod.log b/tests/BlackBox/BlackBoxMod.log index cbd97d953a..6f62169468 100644 --- a/tests/BlackBox/BlackBoxMod.log +++ b/tests/BlackBox/BlackBoxMod.log @@ -157,14 +157,14 @@ n<> u<121> t c<1> l<5:1> el<34:10> === UHDM Object Stats Begin (Non-Elaborated Model) === design 1 logic_net 1 -module 4 +module_inst 4 === UHDM Object Stats End === [INF:UH0707] Elaborating UHDM... === UHDM Object Stats Begin (Elaborated Model) === design 1 logic_net 1 -module 4 +module_inst 4 === UHDM Object Stats End === [INF:UH0708] Writing UHDM DB: ${SURELOG_DIR}/build/regression/BlackBoxMod/slpp_all/surelog.uhdm ... @@ -179,7 +179,7 @@ design: (work@top) |vpiElaborated:1 |vpiName:work@top |uhdmallModules: -\_module: work@core (work@core), file:${SURELOG_DIR}/tests/BlackBox/dut.sv, line:5:1, endln:9:10 +\_module_inst: work@core (work@core), file:${SURELOG_DIR}/tests/BlackBox/dut.sv, line:5:1, endln:9:10 |vpiParent: \_design: (work@top) |vpiFullName:work@core @@ -187,23 +187,23 @@ design: (work@top) |vpiNet: \_logic_net: (work@core.wb_writeback_en), line:7:5, endln:7:20 |vpiParent: - \_module: work@core (work@core), file:${SURELOG_DIR}/tests/BlackBox/dut.sv, line:5:1, endln:9:10 + \_module_inst: work@core (work@core), file:${SURELOG_DIR}/tests/BlackBox/dut.sv, line:5:1, endln:9:10 |vpiName:wb_writeback_en |vpiFullName:work@core.wb_writeback_en |uhdmallModules: -\_module: work@nyuzi (work@nyuzi), file:${SURELOG_DIR}/tests/BlackBox/dut.sv, line:12:1, endln:21:10 +\_module_inst: work@nyuzi (work@nyuzi), file:${SURELOG_DIR}/tests/BlackBox/dut.sv, line:12:1, endln:21:10 |vpiParent: \_design: (work@top) |vpiFullName:work@nyuzi |vpiDefName:work@nyuzi |uhdmallModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/BlackBox/dut.sv, line:25:1, endln:34:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/BlackBox/dut.sv, line:25:1, endln:34:10 |vpiParent: \_design: (work@top) |vpiFullName:work@top |vpiDefName:work@top |uhdmtopModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/BlackBox/dut.sv, line:25:1, endln:34:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/BlackBox/dut.sv, line:25:1, endln:34:10 |vpiName:work@top |vpiDefName:work@top |vpiTop:1 diff --git a/tests/BlackBox/BlackBoxSubMod.log b/tests/BlackBox/BlackBoxSubMod.log index e0b31ceeca..61390384b9 100644 --- a/tests/BlackBox/BlackBoxSubMod.log +++ b/tests/BlackBox/BlackBoxSubMod.log @@ -161,7 +161,7 @@ cont_assign 1 design 1 hier_path 1 logic_net 2 -module 6 +module_inst 6 ref_obj 5 === UHDM Object Stats End === [INF:UH0707] Elaborating UHDM... @@ -173,7 +173,7 @@ cont_assign 2 design 1 hier_path 2 logic_net 2 -module 6 +module_inst 6 ref_obj 10 === UHDM Object Stats End === [ERR:UH0725] ${SURELOG_DIR}/tests/BlackBox/dut.sv:31:16: Unresolved hierarchical reference "nyuzi.core_gen[0].core.wb_writeback_en". @@ -191,7 +191,7 @@ design: (work@top) |vpiElaborated:1 |vpiName:work@top |uhdmallModules: -\_module: work@core (work@core), file:${SURELOG_DIR}/tests/BlackBox/dut.sv, line:5:1, endln:9:10 +\_module_inst: work@core (work@core), file:${SURELOG_DIR}/tests/BlackBox/dut.sv, line:5:1, endln:9:10 |vpiParent: \_design: (work@top) |vpiFullName:work@core @@ -199,17 +199,17 @@ design: (work@top) |vpiNet: \_logic_net: (work@core.wb_writeback_en), line:7:5, endln:7:20 |vpiParent: - \_module: work@core (work@core), file:${SURELOG_DIR}/tests/BlackBox/dut.sv, line:5:1, endln:9:10 + \_module_inst: work@core (work@core), file:${SURELOG_DIR}/tests/BlackBox/dut.sv, line:5:1, endln:9:10 |vpiName:wb_writeback_en |vpiFullName:work@core.wb_writeback_en |uhdmallModules: -\_module: work@nyuzi (work@nyuzi), file:${SURELOG_DIR}/tests/BlackBox/dut.sv, line:12:1, endln:21:10 +\_module_inst: work@nyuzi (work@nyuzi), file:${SURELOG_DIR}/tests/BlackBox/dut.sv, line:12:1, endln:21:10 |vpiParent: \_design: (work@top) |vpiFullName:work@nyuzi |vpiDefName:work@nyuzi |uhdmallModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/BlackBox/dut.sv, line:25:1, endln:34:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/BlackBox/dut.sv, line:25:1, endln:34:10 |vpiParent: \_design: (work@top) |vpiFullName:work@top @@ -217,7 +217,7 @@ design: (work@top) |vpiContAssign: \_cont_assign: , line:31:12, endln:31:54 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/BlackBox/dut.sv, line:25:1, endln:34:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/BlackBox/dut.sv, line:25:1, endln:34:10 |vpiRhs: \_hier_path: (nyuzi.core_gen[0].core.wb_writeback_en), line:31:16, endln:31:54 |vpiParent: @@ -260,7 +260,7 @@ design: (work@top) |vpiActual: \_logic_net: (o) |uhdmtopModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/BlackBox/dut.sv, line:25:1, endln:34:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/BlackBox/dut.sv, line:25:1, endln:34:10 |vpiName:work@top |vpiDefName:work@top |vpiTop:1 @@ -269,21 +269,21 @@ design: (work@top) |vpiName:o |vpiNetType:1 |vpiTopModule:1 - |vpiModule: - \_module: work@nyuzi (work@top.nyuzi), file:${SURELOG_DIR}/tests/BlackBox/dut.sv, line:29:1, endln:29:16 + |vpiModuleInst: + \_module_inst: work@nyuzi (work@top.nyuzi), file:${SURELOG_DIR}/tests/BlackBox/dut.sv, line:29:1, endln:29:16 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/BlackBox/dut.sv, line:25:1, endln:34:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/BlackBox/dut.sv, line:25:1, endln:34:10 |vpiName:nyuzi |vpiFullName:work@top.nyuzi |vpiDefName:work@nyuzi |vpiDefFile:${SURELOG_DIR}/tests/BlackBox/dut.sv |vpiDefLineNo:12 |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/BlackBox/dut.sv, line:25:1, endln:34:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/BlackBox/dut.sv, line:25:1, endln:34:10 |vpiContAssign: \_cont_assign: , line:31:12, endln:31:54 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/BlackBox/dut.sv, line:25:1, endln:34:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/BlackBox/dut.sv, line:25:1, endln:34:10 |vpiRhs: \_hier_path: (nyuzi.core_gen[0].core.wb_writeback_en), line:31:16, endln:31:54 |vpiParent: @@ -295,7 +295,7 @@ design: (work@top) \_hier_path: (nyuzi.core_gen[0].core.wb_writeback_en), line:31:16, endln:31:54 |vpiName:nyuzi |vpiActual: - \_module: work@nyuzi (work@top.nyuzi), file:${SURELOG_DIR}/tests/BlackBox/dut.sv, line:29:1, endln:29:16 + \_module_inst: work@nyuzi (work@top.nyuzi), file:${SURELOG_DIR}/tests/BlackBox/dut.sv, line:29:1, endln:29:16 |vpiActual: \_bit_select: (core_gen), line:31:22, endln:31:30 |vpiParent: diff --git a/tests/BlackParrotComplex/BlackParrotComplex.log b/tests/BlackParrotComplex/BlackParrotComplex.log index 84872c5581..b5722d8e7f 100644 --- a/tests/BlackParrotComplex/BlackParrotComplex.log +++ b/tests/BlackParrotComplex/BlackParrotComplex.log @@ -3189,7 +3189,7 @@ int_typespec 19 int_var 4 io_decl 11 logic_var 1 -module 10 +module_inst 10 operation 421 package 2 param_assign 22 @@ -3221,7 +3221,7 @@ int_typespec 19 int_var 4 io_decl 22 logic_var 1 -module 10 +module_inst 10 operation 421 package 2 param_assign 22 @@ -3720,14 +3720,14 @@ design: (work@top) \_int_typespec: |vpiSigned:1 |uhdmallModules: -\_module: work@bottom (work@bottom), file:${SURELOG_DIR}/tests/BlackParrotComplex/dut.sv, line:79:1, endln:88:10 +\_module_inst: work@bottom (work@bottom), file:${SURELOG_DIR}/tests/BlackParrotComplex/dut.sv, line:79:1, endln:88:10 |vpiParent: \_design: (work@top) |vpiFullName:work@bottom |vpiParameter: \_parameter: (work@bottom.A3), line:81:17, endln:81:19 |vpiParent: - \_module: work@bottom (work@bottom), file:${SURELOG_DIR}/tests/BlackParrotComplex/dut.sv, line:79:1, endln:88:10 + \_module_inst: work@bottom (work@bottom), file:${SURELOG_DIR}/tests/BlackParrotComplex/dut.sv, line:79:1, endln:88:10 |vpiSize:1 |vpiTypespec: \_array_typespec: @@ -3764,13 +3764,13 @@ design: (work@top) |vpiParameter: \_parameter: (work@bottom.A), line:82:13, endln:82:14 |vpiParent: - \_module: work@bottom (work@bottom), file:${SURELOG_DIR}/tests/BlackParrotComplex/dut.sv, line:79:1, endln:88:10 + \_module_inst: work@bottom (work@bottom), file:${SURELOG_DIR}/tests/BlackParrotComplex/dut.sv, line:79:1, endln:88:10 |vpiName:A |vpiFullName:work@bottom.A |vpiParamAssign: \_param_assign: , line:81:17, endln:81:36 |vpiParent: - \_module: work@bottom (work@bottom), file:${SURELOG_DIR}/tests/BlackParrotComplex/dut.sv, line:79:1, endln:88:10 + \_module_inst: work@bottom (work@bottom), file:${SURELOG_DIR}/tests/BlackParrotComplex/dut.sv, line:79:1, endln:88:10 |vpiRhs: \_operation: , line:81:27, endln:81:36 |vpiOpType:33 @@ -3803,7 +3803,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:82:13, endln:82:22 |vpiParent: - \_module: work@bottom (work@bottom), file:${SURELOG_DIR}/tests/BlackParrotComplex/dut.sv, line:79:1, endln:88:10 + \_module_inst: work@bottom (work@bottom), file:${SURELOG_DIR}/tests/BlackParrotComplex/dut.sv, line:79:1, endln:88:10 |vpiRhs: \_bit_select: (A3), line:82:17, endln:82:22 |vpiParent: @@ -3822,14 +3822,14 @@ design: (work@top) \_parameter: (work@bottom.A), line:82:13, endln:82:14 |vpiDefName:work@bottom |uhdmallModules: -\_module: work@middle (work@middle), file:${SURELOG_DIR}/tests/BlackParrotComplex/dut.sv, line:67:1, endln:76:10 +\_module_inst: work@middle (work@middle), file:${SURELOG_DIR}/tests/BlackParrotComplex/dut.sv, line:67:1, endln:76:10 |vpiParent: \_design: (work@top) |vpiFullName:work@middle |vpiParameter: \_parameter: (work@middle.A3), line:69:17, endln:69:19 |vpiParent: - \_module: work@middle (work@middle), file:${SURELOG_DIR}/tests/BlackParrotComplex/dut.sv, line:67:1, endln:76:10 + \_module_inst: work@middle (work@middle), file:${SURELOG_DIR}/tests/BlackParrotComplex/dut.sv, line:67:1, endln:76:10 |vpiSize:1 |vpiTypespec: \_array_typespec: @@ -3866,13 +3866,13 @@ design: (work@top) |vpiParameter: \_parameter: (work@middle.A), line:70:13, endln:70:14 |vpiParent: - \_module: work@middle (work@middle), file:${SURELOG_DIR}/tests/BlackParrotComplex/dut.sv, line:67:1, endln:76:10 + \_module_inst: work@middle (work@middle), file:${SURELOG_DIR}/tests/BlackParrotComplex/dut.sv, line:67:1, endln:76:10 |vpiName:A |vpiFullName:work@middle.A |vpiParamAssign: \_param_assign: , line:69:17, endln:69:37 |vpiParent: - \_module: work@middle (work@middle), file:${SURELOG_DIR}/tests/BlackParrotComplex/dut.sv, line:67:1, endln:76:10 + \_module_inst: work@middle (work@middle), file:${SURELOG_DIR}/tests/BlackParrotComplex/dut.sv, line:67:1, endln:76:10 |vpiRhs: \_operation: , line:69:27, endln:69:37 |vpiOpType:75 @@ -3899,7 +3899,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:70:13, endln:70:22 |vpiParent: - \_module: work@middle (work@middle), file:${SURELOG_DIR}/tests/BlackParrotComplex/dut.sv, line:67:1, endln:76:10 + \_module_inst: work@middle (work@middle), file:${SURELOG_DIR}/tests/BlackParrotComplex/dut.sv, line:67:1, endln:76:10 |vpiRhs: \_bit_select: (A3), line:70:17, endln:70:22 |vpiParent: @@ -3918,14 +3918,14 @@ design: (work@top) \_parameter: (work@middle.A), line:70:13, endln:70:14 |vpiDefName:work@middle |uhdmallModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/BlackParrotComplex/dut.sv, line:3:1, endln:64:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/BlackParrotComplex/dut.sv, line:3:1, endln:64:10 |vpiParent: \_design: (work@top) |vpiFullName:work@top |vpiParameter: \_parameter: (work@top.i), line:4:13, endln:4:14 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/BlackParrotComplex/dut.sv, line:3:1, endln:64:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/BlackParrotComplex/dut.sv, line:3:1, endln:64:10 |UINT:0 |vpiTypespec: \_int_typespec: @@ -3935,7 +3935,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.dims_p), line:5:12, endln:5:18 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/BlackParrotComplex/dut.sv, line:3:1, endln:64:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/BlackParrotComplex/dut.sv, line:3:1, endln:64:10 |UINT:2 |vpiTypespec: \_int_typespec: @@ -3944,13 +3944,13 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.dirs_lp), line:6:11, endln:6:18 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/BlackParrotComplex/dut.sv, line:3:1, endln:64:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/BlackParrotComplex/dut.sv, line:3:1, endln:64:10 |vpiName:dirs_lp |vpiFullName:work@top.dirs_lp |vpiParameter: \_parameter: (work@top.StrictXY), line:8:34, endln:8:42 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/BlackParrotComplex/dut.sv, line:3:1, endln:64:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/BlackParrotComplex/dut.sv, line:3:1, endln:64:10 |vpiTypespec: \_bit_typespec: , line:8:14, endln:8:33 |vpiParent: @@ -4016,7 +4016,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.StrictX), line:27:36, endln:27:43 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/BlackParrotComplex/dut.sv, line:3:1, endln:64:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/BlackParrotComplex/dut.sv, line:3:1, endln:64:10 |vpiTypespec: \_bit_typespec: , line:27:16, endln:27:35 |vpiParent: @@ -4082,7 +4082,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.routing_matrix_p), line:40:48, endln:40:64 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/BlackParrotComplex/dut.sv, line:3:1, endln:64:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/BlackParrotComplex/dut.sv, line:3:1, endln:64:10 |vpiTypespec: \_bit_typespec: , line:40:12, endln:40:47 |vpiParent: @@ -4167,14 +4167,14 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.output_dirs_sparse_lp), line:45:12, endln:45:33 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/BlackParrotComplex/dut.sv, line:3:1, endln:64:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/BlackParrotComplex/dut.sv, line:3:1, endln:64:10 |vpiLocalParam:1 |vpiName:output_dirs_sparse_lp |vpiFullName:work@top.output_dirs_sparse_lp |vpiParamAssign: \_param_assign: , line:4:13, endln:4:18 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/BlackParrotComplex/dut.sv, line:3:1, endln:64:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/BlackParrotComplex/dut.sv, line:3:1, endln:64:10 |vpiRhs: \_constant: , line:4:17, endln:4:18 |vpiDecompile:0 @@ -4188,7 +4188,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:5:12, endln:5:35 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/BlackParrotComplex/dut.sv, line:3:1, endln:64:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/BlackParrotComplex/dut.sv, line:3:1, endln:64:10 |vpiRhs: \_constant: , line:5:34, endln:5:35 |vpiDecompile:2 @@ -4202,7 +4202,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:6:11, endln:6:39 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/BlackParrotComplex/dut.sv, line:3:1, endln:64:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/BlackParrotComplex/dut.sv, line:3:1, endln:64:10 |vpiRhs: \_operation: , line:6:29, endln:6:39 |vpiOpType:24 @@ -4237,7 +4237,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:8:34, endln:25:33 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/BlackParrotComplex/dut.sv, line:3:1, endln:64:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/BlackParrotComplex/dut.sv, line:3:1, endln:64:10 |vpiRhs: \_operation: , line:9:31, endln:25:33 |vpiOpType:33 @@ -4336,7 +4336,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:27:36, endln:38:32 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/BlackParrotComplex/dut.sv, line:3:1, endln:64:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/BlackParrotComplex/dut.sv, line:3:1, endln:64:10 |vpiRhs: \_operation: , line:28:32, endln:38:32 |vpiOpType:33 @@ -4403,7 +4403,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:40:48, endln:40:102 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/BlackParrotComplex/dut.sv, line:3:1, endln:64:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/BlackParrotComplex/dut.sv, line:3:1, endln:64:10 |vpiRhs: \_operation: , line:40:68, endln:40:102 |vpiOpType:32 @@ -4440,7 +4440,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:45:12, endln:51:249 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/BlackParrotComplex/dut.sv, line:3:1, endln:64:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/BlackParrotComplex/dut.sv, line:3:1, endln:64:10 |vpiRhs: \_operation: , line:45:36, endln:51:249 |vpiOpType:24 @@ -7638,7 +7638,7 @@ design: (work@top) |vpiProcess: \_initial: , line:56:1, endln:58:4 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/BlackParrotComplex/dut.sv, line:3:1, endln:64:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/BlackParrotComplex/dut.sv, line:3:1, endln:64:10 |vpiStmt: \_begin: (work@top), line:56:9, endln:58:4 |vpiParent: @@ -7664,12 +7664,12 @@ design: (work@top) |vpiFullName:work@top.output_dirs_sparse_lp |vpiName:$display |uhdmtopModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/BlackParrotComplex/dut.sv, line:3:1, endln:64:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/BlackParrotComplex/dut.sv, line:3:1, endln:64:10 |vpiName:work@top |vpiParameter: \_parameter: (work@top.i), line:4:13, endln:4:14 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/BlackParrotComplex/dut.sv, line:3:1, endln:64:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/BlackParrotComplex/dut.sv, line:3:1, endln:64:10 |UINT:0 |vpiTypespec: \_int_typespec: @@ -7681,7 +7681,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.dims_p), line:5:12, endln:5:18 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/BlackParrotComplex/dut.sv, line:3:1, endln:64:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/BlackParrotComplex/dut.sv, line:3:1, endln:64:10 |UINT:2 |vpiTypespec: \_int_typespec: @@ -7692,13 +7692,13 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.dirs_lp), line:6:11, endln:6:18 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/BlackParrotComplex/dut.sv, line:3:1, endln:64:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/BlackParrotComplex/dut.sv, line:3:1, endln:64:10 |vpiName:dirs_lp |vpiFullName:work@top.dirs_lp |vpiParameter: \_parameter: (work@top.StrictXY), line:8:34, endln:8:42 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/BlackParrotComplex/dut.sv, line:3:1, endln:64:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/BlackParrotComplex/dut.sv, line:3:1, endln:64:10 |vpiTypespec: \_bit_typespec: , line:8:14, endln:8:33 |vpiParent: @@ -7770,7 +7770,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.StrictX), line:27:36, endln:27:43 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/BlackParrotComplex/dut.sv, line:3:1, endln:64:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/BlackParrotComplex/dut.sv, line:3:1, endln:64:10 |vpiTypespec: \_bit_typespec: , line:27:16, endln:27:35 |vpiParent: @@ -7842,7 +7842,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.routing_matrix_p), line:40:48, endln:40:64 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/BlackParrotComplex/dut.sv, line:3:1, endln:64:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/BlackParrotComplex/dut.sv, line:3:1, endln:64:10 |vpiTypespec: \_bit_typespec: , line:40:12, endln:40:47 |vpiParent: @@ -7939,14 +7939,14 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.output_dirs_sparse_lp), line:45:12, endln:45:33 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/BlackParrotComplex/dut.sv, line:3:1, endln:64:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/BlackParrotComplex/dut.sv, line:3:1, endln:64:10 |vpiLocalParam:1 |vpiName:output_dirs_sparse_lp |vpiFullName:work@top.output_dirs_sparse_lp |vpiParamAssign: \_param_assign: , line:4:13, endln:4:18 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/BlackParrotComplex/dut.sv, line:3:1, endln:64:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/BlackParrotComplex/dut.sv, line:3:1, endln:64:10 |vpiRhs: \_constant: , line:4:17, endln:4:18 |vpiDecompile:0 @@ -7960,7 +7960,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:5:12, endln:5:35 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/BlackParrotComplex/dut.sv, line:3:1, endln:64:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/BlackParrotComplex/dut.sv, line:3:1, endln:64:10 |vpiRhs: \_constant: , line:5:34, endln:5:35 |vpiDecompile:2 @@ -7974,7 +7974,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:6:11, endln:6:39 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/BlackParrotComplex/dut.sv, line:3:1, endln:64:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/BlackParrotComplex/dut.sv, line:3:1, endln:64:10 |vpiRhs: \_constant: , line:6:29, endln:6:39 |vpiDecompile:5 @@ -7986,7 +7986,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:8:34, endln:25:33 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/BlackParrotComplex/dut.sv, line:3:1, endln:64:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/BlackParrotComplex/dut.sv, line:3:1, endln:64:10 |vpiRhs: \_operation: , line:9:31, endln:25:33 |vpiTypespec: @@ -8090,7 +8090,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:27:36, endln:38:32 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/BlackParrotComplex/dut.sv, line:3:1, endln:64:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/BlackParrotComplex/dut.sv, line:3:1, endln:64:10 |vpiRhs: \_operation: , line:28:32, endln:38:32 |vpiTypespec: @@ -8162,7 +8162,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:40:48, endln:40:102 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/BlackParrotComplex/dut.sv, line:3:1, endln:64:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/BlackParrotComplex/dut.sv, line:3:1, endln:64:10 |vpiRhs: \_operation: , line:9:31, endln:25:33 |vpiLhs: @@ -8170,7 +8170,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:45:12, endln:51:249 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/BlackParrotComplex/dut.sv, line:3:1, endln:64:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/BlackParrotComplex/dut.sv, line:3:1, endln:64:10 |vpiRhs: \_constant: , line:45:36, endln:51:249 |vpiDecompile:5 @@ -8185,7 +8185,7 @@ design: (work@top) |vpiProcess: \_initial: , line:56:1, endln:58:4 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/BlackParrotComplex/dut.sv, line:3:1, endln:64:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/BlackParrotComplex/dut.sv, line:3:1, endln:64:10 |vpiStmt: \_begin: (work@top), line:56:9, endln:58:4 |vpiParent: @@ -8207,12 +8207,12 @@ design: (work@top) \_parameter: (work@top.output_dirs_sparse_lp), line:45:12, endln:45:33 |vpiName:$display |uhdmtopModules: -\_module: work@middle (work@middle), file:${SURELOG_DIR}/tests/BlackParrotComplex/dut.sv, line:67:1, endln:76:10 +\_module_inst: work@middle (work@middle), file:${SURELOG_DIR}/tests/BlackParrotComplex/dut.sv, line:67:1, endln:76:10 |vpiName:work@middle |vpiParameter: \_parameter: (work@middle.A3), line:69:17, endln:69:19 |vpiParent: - \_module: work@middle (work@middle), file:${SURELOG_DIR}/tests/BlackParrotComplex/dut.sv, line:67:1, endln:76:10 + \_module_inst: work@middle (work@middle), file:${SURELOG_DIR}/tests/BlackParrotComplex/dut.sv, line:67:1, endln:76:10 |vpiSize:1 |vpiTypespec: \_array_typespec: @@ -8269,13 +8269,13 @@ design: (work@top) |vpiParameter: \_parameter: (work@middle.A), line:70:13, endln:70:14 |vpiParent: - \_module: work@middle (work@middle), file:${SURELOG_DIR}/tests/BlackParrotComplex/dut.sv, line:67:1, endln:76:10 + \_module_inst: work@middle (work@middle), file:${SURELOG_DIR}/tests/BlackParrotComplex/dut.sv, line:67:1, endln:76:10 |vpiName:A |vpiFullName:work@middle.A |vpiParamAssign: \_param_assign: , line:69:17, endln:69:37 |vpiParent: - \_module: work@middle (work@middle), file:${SURELOG_DIR}/tests/BlackParrotComplex/dut.sv, line:67:1, endln:76:10 + \_module_inst: work@middle (work@middle), file:${SURELOG_DIR}/tests/BlackParrotComplex/dut.sv, line:67:1, endln:76:10 |vpiRhs: \_operation: , line:69:27, endln:69:37 |vpiParent: @@ -8339,7 +8339,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:70:13, endln:70:22 |vpiParent: - \_module: work@middle (work@middle), file:${SURELOG_DIR}/tests/BlackParrotComplex/dut.sv, line:67:1, endln:76:10 + \_module_inst: work@middle (work@middle), file:${SURELOG_DIR}/tests/BlackParrotComplex/dut.sv, line:67:1, endln:76:10 |vpiRhs: \_constant: , line:70:17, endln:70:22 |vpiDecompile:1 @@ -8352,12 +8352,12 @@ design: (work@top) |vpiTop:1 |vpiTopModule:1 |uhdmtopModules: -\_module: work@bottom (work@bottom), file:${SURELOG_DIR}/tests/BlackParrotComplex/dut.sv, line:79:1, endln:88:10 +\_module_inst: work@bottom (work@bottom), file:${SURELOG_DIR}/tests/BlackParrotComplex/dut.sv, line:79:1, endln:88:10 |vpiName:work@bottom |vpiParameter: \_parameter: (work@bottom.A3), line:81:17, endln:81:19 |vpiParent: - \_module: work@bottom (work@bottom), file:${SURELOG_DIR}/tests/BlackParrotComplex/dut.sv, line:79:1, endln:88:10 + \_module_inst: work@bottom (work@bottom), file:${SURELOG_DIR}/tests/BlackParrotComplex/dut.sv, line:79:1, endln:88:10 |vpiSize:1 |vpiTypespec: \_array_typespec: @@ -8414,13 +8414,13 @@ design: (work@top) |vpiParameter: \_parameter: (work@bottom.A), line:82:13, endln:82:14 |vpiParent: - \_module: work@bottom (work@bottom), file:${SURELOG_DIR}/tests/BlackParrotComplex/dut.sv, line:79:1, endln:88:10 + \_module_inst: work@bottom (work@bottom), file:${SURELOG_DIR}/tests/BlackParrotComplex/dut.sv, line:79:1, endln:88:10 |vpiName:A |vpiFullName:work@bottom.A |vpiParamAssign: \_param_assign: , line:81:17, endln:81:36 |vpiParent: - \_module: work@bottom (work@bottom), file:${SURELOG_DIR}/tests/BlackParrotComplex/dut.sv, line:79:1, endln:88:10 + \_module_inst: work@bottom (work@bottom), file:${SURELOG_DIR}/tests/BlackParrotComplex/dut.sv, line:79:1, endln:88:10 |vpiRhs: \_operation: , line:81:27, endln:81:36 |vpiTypespec: @@ -8455,7 +8455,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:82:13, endln:82:22 |vpiParent: - \_module: work@bottom (work@bottom), file:${SURELOG_DIR}/tests/BlackParrotComplex/dut.sv, line:79:1, endln:88:10 + \_module_inst: work@bottom (work@bottom), file:${SURELOG_DIR}/tests/BlackParrotComplex/dut.sv, line:79:1, endln:88:10 |vpiRhs: \_constant: , line:82:17, endln:82:22 |vpiDecompile:3 diff --git a/tests/BlackParrotConf/BlackParrotConf.log b/tests/BlackParrotConf/BlackParrotConf.log index 957a12eced..a3cda4ba6d 100644 --- a/tests/BlackParrotConf/BlackParrotConf.log +++ b/tests/BlackParrotConf/BlackParrotConf.log @@ -20474,7 +20474,7 @@ int_typespec 1068 integer_typespec 3800 logic_net 40 logic_typespec 756 -module 23 +module_inst 23 operation 1047 package 24 packed_array_typespec 43 @@ -20517,7 +20517,7 @@ int_typespec 1068 integer_typespec 3800 logic_net 40 logic_typespec 756 -module 23 +module_inst 23 operation 1047 package 24 packed_array_typespec 43 @@ -34100,7 +34100,7 @@ design: (work@testbench) |vpiTypedef: \_enum_typespec: (bp_common_pkg::bp_coh_states_e), line:757:1, endln:767:19 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiName:bp_common_pkg::bp_coh_states_e |vpiInstance: \_package: bp_me_pkg (bp_me_pkg::), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:4412:1, endln:5667:23 @@ -34166,7 +34166,7 @@ design: (work@testbench) |vpiTypedef: \_enum_typespec: (bp_common_pkg::bp_fe_command_queue_opcodes_e), line:341:1, endln:350:33 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiName:bp_common_pkg::bp_fe_command_queue_opcodes_e |vpiInstance: \_package: bp_me_pkg (bp_me_pkg::), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:4412:1, endln:5667:23 @@ -34238,7 +34238,7 @@ design: (work@testbench) |vpiTypedef: \_enum_typespec: (bp_common_pkg::bp_fe_command_queue_subopcodes_e), line:386:1, endln:395:36 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiName:bp_common_pkg::bp_fe_command_queue_subopcodes_e |vpiInstance: \_package: bp_me_pkg (bp_me_pkg::), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:4412:1, endln:5667:23 @@ -34310,7 +34310,7 @@ design: (work@testbench) |vpiTypedef: \_enum_typespec: (bp_common_pkg::bp_fe_exception_code_e), line:369:1, endln:375:26 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiName:bp_common_pkg::bp_fe_exception_code_e |vpiInstance: \_package: bp_me_pkg (bp_me_pkg::), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:4412:1, endln:5667:23 @@ -34364,7 +34364,7 @@ design: (work@testbench) |vpiTypedef: \_enum_typespec: (bp_common_pkg::bp_fe_misprediction_reason_e), line:355:1, endln:359:32 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiName:bp_common_pkg::bp_fe_misprediction_reason_e |vpiInstance: \_package: bp_me_pkg (bp_me_pkg::), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:4412:1, endln:5667:23 @@ -34388,7 +34388,7 @@ design: (work@testbench) |vpiTypedef: \_enum_typespec: (bp_common_pkg::bp_fe_queue_type_e), line:324:1, endln:328:22 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiName:bp_common_pkg::bp_fe_queue_type_e |vpiInstance: \_package: bp_me_pkg (bp_me_pkg::), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:4412:1, endln:5667:23 @@ -34412,7 +34412,7 @@ design: (work@testbench) |vpiTypedef: \_enum_typespec: (bp_common_pkg::bp_lce_cce_lru_dirty_e), line:729:1, endln:733:26 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiName:bp_common_pkg::bp_lce_cce_lru_dirty_e |vpiInstance: \_package: bp_me_pkg (bp_me_pkg::), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:4412:1, endln:5667:23 @@ -34436,7 +34436,7 @@ design: (work@testbench) |vpiTypedef: \_enum_typespec: (bp_common_pkg::bp_lce_cce_req_non_excl_e), line:718:1, endln:722:29 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiName:bp_common_pkg::bp_lce_cce_req_non_excl_e |vpiInstance: \_package: bp_me_pkg (bp_me_pkg::), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:4412:1, endln:5667:23 @@ -34460,7 +34460,7 @@ design: (work@testbench) |vpiTypedef: \_enum_typespec: (bp_common_pkg::bp_lce_cce_req_type_e), line:701:1, endln:708:25 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiName:bp_common_pkg::bp_lce_cce_req_type_e |vpiInstance: \_package: bp_me_pkg (bp_me_pkg::), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:4412:1, endln:5667:23 @@ -34514,7 +34514,7 @@ design: (work@testbench) |vpiTypedef: \_enum_typespec: (bp_common_pkg::bp_lce_cce_resp_type_e), line:814:1, endln:822:26 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiName:bp_common_pkg::bp_lce_cce_resp_type_e |vpiInstance: \_package: bp_me_pkg (bp_me_pkg::), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:4412:1, endln:5667:23 @@ -34574,7 +34574,7 @@ design: (work@testbench) |vpiTypedef: \_enum_typespec: (bp_common_pkg::bp_lce_cce_uc_req_size_e), line:739:1, endln:745:28 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiName:bp_common_pkg::bp_lce_cce_uc_req_size_e |vpiInstance: \_package: bp_me_pkg (bp_me_pkg::), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:4412:1, endln:5667:23 @@ -34628,7 +34628,7 @@ design: (work@testbench) |vpiTypedef: \_enum_typespec: (bp_common_pkg::bp_lce_cmd_type_e), line:788:1, endln:801:21 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiName:bp_common_pkg::bp_lce_cmd_type_e |vpiInstance: \_package: bp_me_pkg (bp_me_pkg::), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:4412:1, endln:5667:23 @@ -34718,7 +34718,7 @@ design: (work@testbench) |vpiTypedef: \_struct_typespec: (bp_common_rv64_pkg::bp_mcause_s), line:1849:9, endln:1849:15 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiName:bp_common_rv64_pkg::bp_mcause_s |vpiInstance: \_package: bp_be_pkg (bp_be_pkg::), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:2530:1, endln:3363:23 @@ -34778,7 +34778,7 @@ design: (work@testbench) |vpiTypedef: \_logic_typespec: (bp_common_rv64_pkg::bp_mcounter_s), line:1866:9, endln:1866:21 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiName:bp_common_rv64_pkg::bp_mcounter_s |vpiInstance: \_package: bp_be_pkg (bp_be_pkg::), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:2530:1, endln:3363:23 @@ -34803,7 +34803,7 @@ design: (work@testbench) |vpiTypedef: \_struct_typespec: (bp_common_rv64_pkg::bp_mcounteren_s), line:1645:9, endln:1645:15 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiName:bp_common_rv64_pkg::bp_mcounteren_s |vpiInstance: \_package: bp_be_pkg (bp_be_pkg::), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:2530:1, endln:3363:23 @@ -34843,7 +34843,7 @@ design: (work@testbench) |vpiTypedef: \_struct_typespec: (bp_common_rv64_pkg::bp_mcountinhibit_s), line:1894:9, endln:1894:15 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiName:bp_common_rv64_pkg::bp_mcountinhibit_s |vpiInstance: \_package: bp_be_pkg (bp_be_pkg::), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:2530:1, endln:3363:23 @@ -34883,7 +34883,7 @@ design: (work@testbench) |vpiTypedef: \_logic_typespec: (bp_common_rv64_pkg::bp_mcycle_s), line:1866:9, endln:1866:21 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiName:bp_common_rv64_pkg::bp_mcycle_s |vpiTypedefAlias: \_logic_typespec: (bp_mcounter_s), line:1866:9, endln:1866:21 @@ -34937,7 +34937,7 @@ design: (work@testbench) |vpiTypedef: \_struct_typespec: (bp_common_rv64_pkg::bp_medeleg_s), line:1469:9, endln:1469:15 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiName:bp_common_rv64_pkg::bp_medeleg_s |vpiInstance: \_package: bp_be_pkg (bp_be_pkg::), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:2530:1, endln:3363:23 @@ -35053,7 +35053,7 @@ design: (work@testbench) |vpiTypedef: \_struct_typespec: (bp_common_rv64_pkg::bp_mepc_s), line:1748:9, endln:1748:15 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiName:bp_common_rv64_pkg::bp_mepc_s |vpiInstance: \_package: bp_be_pkg (bp_be_pkg::), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:2530:1, endln:3363:23 @@ -35113,7 +35113,7 @@ design: (work@testbench) |vpiTypedef: \_struct_typespec: (bp_common_rv64_pkg::bp_mideleg_s), line:1516:9, endln:1516:15 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiName:bp_common_rv64_pkg::bp_mideleg_s |vpiInstance: \_package: bp_be_pkg (bp_be_pkg::), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:2530:1, endln:3363:23 @@ -35217,7 +35217,7 @@ design: (work@testbench) |vpiTypedef: \_struct_typespec: (bp_common_rv64_pkg::bp_mie_s), line:1577:9, endln:1577:15 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiName:bp_common_rv64_pkg::bp_mie_s |vpiInstance: \_package: bp_be_pkg (bp_be_pkg::), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:2530:1, endln:3363:23 @@ -35321,7 +35321,7 @@ design: (work@testbench) |vpiTypedef: \_logic_typespec: (bp_common_rv64_pkg::bp_minstret_s), line:1866:9, endln:1866:21 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiName:bp_common_rv64_pkg::bp_minstret_s |vpiTypedefAlias: \_logic_typespec: (bp_mcounter_s), line:1866:9, endln:1866:21 @@ -35375,7 +35375,7 @@ design: (work@testbench) |vpiTypedef: \_struct_typespec: (bp_common_rv64_pkg::bp_mip_s), line:1699:9, endln:1699:15 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiName:bp_common_rv64_pkg::bp_mip_s |vpiInstance: \_package: bp_be_pkg (bp_be_pkg::), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:2530:1, endln:3363:23 @@ -35479,7 +35479,7 @@ design: (work@testbench) |vpiTypedef: \_logic_typespec: (bp_common_rv64_pkg::bp_mscratch_s), line:1665:9, endln:1665:21 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiName:bp_common_rv64_pkg::bp_mscratch_s |vpiInstance: \_package: bp_be_pkg (bp_be_pkg::), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:2530:1, endln:3363:23 @@ -35504,7 +35504,7 @@ design: (work@testbench) |vpiTypedef: \_struct_typespec: (bp_common_rv64_pkg::bp_mstatus_s), line:1430:9, endln:1430:15 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiName:bp_common_rv64_pkg::bp_mstatus_s |vpiInstance: \_package: bp_be_pkg (bp_be_pkg::), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:2530:1, endln:3363:23 @@ -35644,7 +35644,7 @@ design: (work@testbench) |vpiTypedef: \_struct_typespec: (bp_common_rv64_pkg::bp_mtval_s), line:1735:9, endln:1735:15 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiName:bp_common_rv64_pkg::bp_mtval_s |vpiInstance: \_package: bp_be_pkg (bp_be_pkg::), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:2530:1, endln:3363:23 @@ -35704,7 +35704,7 @@ design: (work@testbench) |vpiTypedef: \_struct_typespec: (bp_common_rv64_pkg::bp_mtvec_s), line:1622:9, endln:1622:15 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiName:bp_common_rv64_pkg::bp_mtvec_s |vpiInstance: \_package: bp_be_pkg (bp_be_pkg::), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:2530:1, endln:3363:23 @@ -35748,12 +35748,12 @@ design: (work@testbench) |vpiTypedef: \_struct_typespec: (bp_common_rv64_pkg::bp_pmpaddr0_s), line:1815:9, endln:1815:15 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiName:bp_common_rv64_pkg::bp_pmpaddr0_s |vpiTypedefAlias: \_struct_typespec: (bp_common_rv64_pkg::bp_pmpaddr_s), line:1815:9, endln:1815:15 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiName:bp_common_rv64_pkg::bp_pmpaddr_s |vpiInstance: \_package: bp_be_pkg (bp_be_pkg::), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:2530:1, endln:3363:23 @@ -35836,7 +35836,7 @@ design: (work@testbench) |vpiTypedef: \_struct_typespec: (bp_common_rv64_pkg::bp_pmpaddr1_s), line:1815:9, endln:1815:15 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiName:bp_common_rv64_pkg::bp_pmpaddr1_s |vpiTypedefAlias: \_struct_typespec: (bp_common_rv64_pkg::bp_pmpaddr_s), line:1815:9, endln:1815:15 @@ -35882,7 +35882,7 @@ design: (work@testbench) |vpiTypedef: \_struct_typespec: (bp_common_rv64_pkg::bp_pmpaddr2_s), line:1815:9, endln:1815:15 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiName:bp_common_rv64_pkg::bp_pmpaddr2_s |vpiTypedefAlias: \_struct_typespec: (bp_common_rv64_pkg::bp_pmpaddr_s), line:1815:9, endln:1815:15 @@ -35928,7 +35928,7 @@ design: (work@testbench) |vpiTypedef: \_struct_typespec: (bp_common_rv64_pkg::bp_pmpaddr3_s), line:1815:9, endln:1815:15 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiName:bp_common_rv64_pkg::bp_pmpaddr3_s |vpiTypedefAlias: \_struct_typespec: (bp_common_rv64_pkg::bp_pmpaddr_s), line:1815:9, endln:1815:15 @@ -35976,12 +35976,12 @@ design: (work@testbench) |vpiTypedef: \_struct_typespec: (bp_common_rv64_pkg::bp_pmpcfg0_s), line:1786:9, endln:1786:15 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiName:bp_common_rv64_pkg::bp_pmpcfg0_s |vpiTypedefAlias: \_struct_typespec: (bp_common_rv64_pkg::bp_pmpcfg_s), line:1786:9, endln:1786:15 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiName:bp_common_rv64_pkg::bp_pmpcfg_s |vpiInstance: \_package: bp_be_pkg (bp_be_pkg::), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:2530:1, endln:3363:23 @@ -36020,7 +36020,7 @@ design: (work@testbench) |vpiElemTypespec: \_struct_typespec: (bp_common_rv64_pkg::rv64_pmpcfg_entry_s), line:1760:9, endln:1760:15 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiName:bp_common_rv64_pkg::rv64_pmpcfg_entry_s |vpiInstance: \_package: bp_be_pkg (bp_be_pkg::), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:2530:1, endln:3363:23 @@ -36354,7 +36354,7 @@ design: (work@testbench) |vpiTypedef: \_struct_typespec: (bp_common_rv64_pkg::bp_satp_s), line:1329:9, endln:1329:15 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiName:bp_common_rv64_pkg::bp_satp_s |vpiInstance: \_package: bp_be_pkg (bp_be_pkg::), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:2530:1, endln:3363:23 @@ -36414,7 +36414,7 @@ design: (work@testbench) |vpiTypedef: \_struct_typespec: (bp_common_rv64_pkg::bp_scause_s), line:1292:9, endln:1292:15 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiName:bp_common_rv64_pkg::bp_scause_s |vpiInstance: \_package: bp_be_pkg (bp_be_pkg::), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:2530:1, endln:3363:23 @@ -36474,7 +36474,7 @@ design: (work@testbench) |vpiTypedef: \_struct_typespec: (bp_common_rv64_pkg::bp_scounteren_s), line:1247:9, endln:1247:15 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiName:bp_common_rv64_pkg::bp_scounteren_s |vpiInstance: \_package: bp_be_pkg (bp_be_pkg::), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:2530:1, endln:3363:23 @@ -36514,7 +36514,7 @@ design: (work@testbench) |vpiTypedef: \_logic_typespec: (bp_common_rv64_pkg::bp_sepc_s), line:1276:9, endln:1276:21 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiName:bp_common_rv64_pkg::bp_sepc_s |vpiInstance: \_package: bp_be_pkg (bp_be_pkg::), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:2530:1, endln:3363:23 @@ -36539,7 +36539,7 @@ design: (work@testbench) |vpiTypedef: \_logic_typespec: (bp_common_rv64_pkg::bp_sscratch_s), line:1267:9, endln:1267:21 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiName:bp_common_rv64_pkg::bp_sscratch_s |vpiInstance: \_package: bp_be_pkg (bp_be_pkg::), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:2530:1, endln:3363:23 @@ -36564,7 +36564,7 @@ design: (work@testbench) |vpiTypedef: \_logic_typespec: (bp_common_rv64_pkg::bp_stval_s), line:1309:9, endln:1309:21 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiName:bp_common_rv64_pkg::bp_stval_s |vpiInstance: \_package: bp_be_pkg (bp_be_pkg::), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:2530:1, endln:3363:23 @@ -36589,7 +36589,7 @@ design: (work@testbench) |vpiTypedef: \_struct_typespec: (bp_common_rv64_pkg::bp_stvec_s), line:1225:9, endln:1225:15 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiName:bp_common_rv64_pkg::bp_stvec_s |vpiInstance: \_package: bp_be_pkg (bp_be_pkg::), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:2530:1, endln:3363:23 @@ -36941,7 +36941,7 @@ design: (work@testbench) |vpiTypedef: \_struct_typespec: (bp_common_rv64_pkg::rv64_instr_itype_s), line:1989:11, endln:1989:17 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiName:bp_common_rv64_pkg::rv64_instr_itype_s |vpiInstance: \_package: bp_be_pkg (bp_be_pkg::), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:2530:1, endln:3363:23 @@ -37093,7 +37093,7 @@ design: (work@testbench) |vpiTypedef: \_struct_typespec: (bp_common_rv64_pkg::rv64_instr_rtype_s), line:1980:11, endln:1980:17 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiName:bp_common_rv64_pkg::rv64_instr_rtype_s |vpiInstance: \_package: bp_be_pkg (bp_be_pkg::), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:2530:1, endln:3363:23 @@ -37281,7 +37281,7 @@ design: (work@testbench) |vpiTypedef: \_struct_typespec: (bp_common_rv64_pkg::rv64_instr_s), line:2012:11, endln:2012:17 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiName:bp_common_rv64_pkg::rv64_instr_s |vpiInstance: \_package: bp_be_pkg (bp_be_pkg::), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:2530:1, endln:3363:23 @@ -37330,7 +37330,7 @@ design: (work@testbench) |vpiTypespec: \_struct_typespec: (bp_common_rv64_pkg::rv64_instr_stype_s), line:1997:11, endln:1997:17 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiName:bp_common_rv64_pkg::rv64_instr_stype_s |vpiInstance: \_package: bp_be_pkg (bp_be_pkg::), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:2530:1, endln:3363:23 @@ -37528,7 +37528,7 @@ design: (work@testbench) |vpiTypespec: \_struct_typespec: (bp_common_rv64_pkg::rv64_instr_utype_s), line:2006:11, endln:2006:17 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiName:bp_common_rv64_pkg::rv64_instr_utype_s |vpiInstance: \_package: bp_be_pkg (bp_be_pkg::), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:2530:1, endln:3363:23 @@ -37658,7 +37658,7 @@ design: (work@testbench) |vpiTypedef: \_struct_typespec: (bp_common_rv64_pkg::rv64_mcause_s), line:1843:9, endln:1843:15 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiName:bp_common_rv64_pkg::rv64_mcause_s |vpiInstance: \_package: bp_be_pkg (bp_be_pkg::), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:2530:1, endln:3363:23 @@ -37718,7 +37718,7 @@ design: (work@testbench) |vpiTypedef: \_logic_typespec: (bp_common_rv64_pkg::rv64_mcounter_s), line:1865:9, endln:1865:21 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiName:bp_common_rv64_pkg::rv64_mcounter_s |vpiInstance: \_package: bp_be_pkg (bp_be_pkg::), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:2530:1, endln:3363:23 @@ -37743,7 +37743,7 @@ design: (work@testbench) |vpiTypedef: \_struct_typespec: (bp_common_rv64_pkg::rv64_mcounteren_s), line:1637:9, endln:1637:15 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiName:bp_common_rv64_pkg::rv64_mcounteren_s |vpiInstance: \_package: bp_be_pkg (bp_be_pkg::), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:2530:1, endln:3363:23 @@ -37835,7 +37835,7 @@ design: (work@testbench) |vpiTypedef: \_struct_typespec: (bp_common_rv64_pkg::rv64_mcountinhibit_s), line:1886:9, endln:1886:15 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiName:bp_common_rv64_pkg::rv64_mcountinhibit_s |vpiInstance: \_package: bp_be_pkg (bp_be_pkg::), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:2530:1, endln:3363:23 @@ -37927,7 +37927,7 @@ design: (work@testbench) |vpiTypedef: \_logic_typespec: (bp_common_rv64_pkg::rv64_mcycle_s), line:1865:9, endln:1865:21 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiName:bp_common_rv64_pkg::rv64_mcycle_s |vpiTypedefAlias: \_logic_typespec: (rv64_mcounter_s), line:1865:9, endln:1865:21 @@ -37981,7 +37981,7 @@ design: (work@testbench) |vpiTypedef: \_logic_typespec: (bp_common_rv64_pkg::rv64_medeleg_s), line:1467:9, endln:1467:21 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiName:bp_common_rv64_pkg::rv64_medeleg_s |vpiInstance: \_package: bp_be_pkg (bp_be_pkg::), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:2530:1, endln:3363:23 @@ -38006,7 +38006,7 @@ design: (work@testbench) |vpiTypedef: \_logic_typespec: (bp_common_rv64_pkg::rv64_mepc_s), line:1747:9, endln:1747:21 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiName:bp_common_rv64_pkg::rv64_mepc_s |vpiInstance: \_package: bp_be_pkg (bp_be_pkg::), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:2530:1, endln:3363:23 @@ -38031,7 +38031,7 @@ design: (work@testbench) |vpiTypedef: \_struct_typespec: (bp_common_rv64_pkg::rv64_mideleg_s), line:1490:9, endln:1490:15 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiName:bp_common_rv64_pkg::rv64_mideleg_s |vpiInstance: \_package: bp_be_pkg (bp_be_pkg::), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:2530:1, endln:3363:23 @@ -38267,7 +38267,7 @@ design: (work@testbench) |vpiTypedef: \_struct_typespec: (bp_common_rv64_pkg::rv64_mie_s), line:1551:9, endln:1551:15 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiName:bp_common_rv64_pkg::rv64_mie_s |vpiInstance: \_package: bp_be_pkg (bp_be_pkg::), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:2530:1, endln:3363:23 @@ -38503,7 +38503,7 @@ design: (work@testbench) |vpiTypedef: \_logic_typespec: (bp_common_rv64_pkg::rv64_minstret_s), line:1865:9, endln:1865:21 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiName:bp_common_rv64_pkg::rv64_minstret_s |vpiTypedefAlias: \_logic_typespec: (rv64_mcounter_s), line:1865:9, endln:1865:21 @@ -38557,7 +38557,7 @@ design: (work@testbench) |vpiTypedef: \_struct_typespec: (bp_common_rv64_pkg::rv64_mip_s), line:1673:9, endln:1673:15 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiName:bp_common_rv64_pkg::rv64_mip_s |vpiInstance: \_package: bp_be_pkg (bp_be_pkg::), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:2530:1, endln:3363:23 @@ -38793,7 +38793,7 @@ design: (work@testbench) |vpiTypedef: \_logic_typespec: (bp_common_rv64_pkg::rv64_mscratch_s), line:1664:9, endln:1664:21 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiName:bp_common_rv64_pkg::rv64_mscratch_s |vpiInstance: \_package: bp_be_pkg (bp_be_pkg::), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:2530:1, endln:3363:23 @@ -38818,7 +38818,7 @@ design: (work@testbench) |vpiTypedef: \_struct_typespec: (bp_common_rv64_pkg::rv64_mstatus_s), line:1352:9, endln:1352:15 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiName:bp_common_rv64_pkg::rv64_mstatus_s |vpiInstance: \_package: bp_be_pkg (bp_be_pkg::), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:2530:1, endln:3363:23 @@ -39370,7 +39370,7 @@ design: (work@testbench) |vpiTypedef: \_logic_typespec: (bp_common_rv64_pkg::rv64_mtval_s), line:1734:9, endln:1734:21 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiName:bp_common_rv64_pkg::rv64_mtval_s |vpiInstance: \_package: bp_be_pkg (bp_be_pkg::), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:2530:1, endln:3363:23 @@ -39395,7 +39395,7 @@ design: (work@testbench) |vpiTypedef: \_struct_typespec: (bp_common_rv64_pkg::rv64_mtvec_s), line:1612:9, endln:1612:15 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiName:bp_common_rv64_pkg::rv64_mtvec_s |vpiInstance: \_package: bp_be_pkg (bp_be_pkg::), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:2530:1, endln:3363:23 @@ -39475,12 +39475,12 @@ design: (work@testbench) |vpiTypedef: \_struct_typespec: (bp_common_rv64_pkg::rv64_pmpaddr0_s), line:1804:9, endln:1804:15 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiName:bp_common_rv64_pkg::rv64_pmpaddr0_s |vpiTypedefAlias: \_struct_typespec: (bp_common_rv64_pkg::rv64_pmpaddr_s), line:1804:9, endln:1804:15 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiName:bp_common_rv64_pkg::rv64_pmpaddr_s |vpiInstance: \_package: bp_be_pkg (bp_be_pkg::), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:2530:1, endln:3363:23 @@ -39635,7 +39635,7 @@ design: (work@testbench) |vpiTypedef: \_struct_typespec: (bp_common_rv64_pkg::rv64_pmpaddr1_s), line:1804:9, endln:1804:15 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiName:bp_common_rv64_pkg::rv64_pmpaddr1_s |vpiTypedefAlias: \_struct_typespec: (bp_common_rv64_pkg::rv64_pmpaddr_s), line:1804:9, endln:1804:15 @@ -39717,7 +39717,7 @@ design: (work@testbench) |vpiTypedef: \_struct_typespec: (bp_common_rv64_pkg::rv64_pmpaddr2_s), line:1804:9, endln:1804:15 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiName:bp_common_rv64_pkg::rv64_pmpaddr2_s |vpiTypedefAlias: \_struct_typespec: (bp_common_rv64_pkg::rv64_pmpaddr_s), line:1804:9, endln:1804:15 @@ -39799,7 +39799,7 @@ design: (work@testbench) |vpiTypedef: \_struct_typespec: (bp_common_rv64_pkg::rv64_pmpaddr3_s), line:1804:9, endln:1804:15 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiName:bp_common_rv64_pkg::rv64_pmpaddr3_s |vpiTypedefAlias: \_struct_typespec: (bp_common_rv64_pkg::rv64_pmpaddr_s), line:1804:9, endln:1804:15 @@ -39883,12 +39883,12 @@ design: (work@testbench) |vpiTypedef: \_struct_typespec: (bp_common_rv64_pkg::rv64_pmpcfg0_s), line:1779:9, endln:1779:15 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiName:bp_common_rv64_pkg::rv64_pmpcfg0_s |vpiTypedefAlias: \_struct_typespec: (bp_common_rv64_pkg::rv64_pmpcfg_s), line:1779:9, endln:1779:15 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiName:bp_common_rv64_pkg::rv64_pmpcfg_s |vpiInstance: \_package: bp_be_pkg (bp_be_pkg::), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:2530:1, endln:3363:23 @@ -40117,7 +40117,7 @@ design: (work@testbench) |vpiTypedef: \_struct_typespec: (bp_common_rv64_pkg::rv64_pmpcfg1_s), line:1779:9, endln:1779:15 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiName:bp_common_rv64_pkg::rv64_pmpcfg1_s |vpiTypedefAlias: \_struct_typespec: (bp_common_rv64_pkg::rv64_pmpcfg_s), line:1779:9, endln:1779:15 @@ -40311,7 +40311,7 @@ design: (work@testbench) |vpiTypedef: \_struct_typespec: (bp_common_rv64_pkg::rv64_satp_s), line:1317:9, endln:1317:15 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiName:bp_common_rv64_pkg::rv64_satp_s |vpiInstance: \_package: bp_be_pkg (bp_be_pkg::), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:2530:1, endln:3363:23 @@ -40427,7 +40427,7 @@ design: (work@testbench) |vpiTypedef: \_struct_typespec: (bp_common_rv64_pkg::rv64_scause_s), line:1286:9, endln:1286:15 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiName:bp_common_rv64_pkg::rv64_scause_s |vpiInstance: \_package: bp_be_pkg (bp_be_pkg::), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:2530:1, endln:3363:23 @@ -40487,7 +40487,7 @@ design: (work@testbench) |vpiTypedef: \_struct_typespec: (bp_common_rv64_pkg::rv64_scounteren_s), line:1240:9, endln:1240:15 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiName:bp_common_rv64_pkg::rv64_scounteren_s |vpiInstance: \_package: bp_be_pkg (bp_be_pkg::), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:2530:1, endln:3363:23 @@ -40563,7 +40563,7 @@ design: (work@testbench) |vpiTypedef: \_logic_typespec: (bp_common_rv64_pkg::rv64_sepc_s), line:1275:9, endln:1275:21 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiName:bp_common_rv64_pkg::rv64_sepc_s |vpiInstance: \_package: bp_be_pkg (bp_be_pkg::), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:2530:1, endln:3363:23 @@ -40588,7 +40588,7 @@ design: (work@testbench) |vpiTypedef: \_logic_typespec: (bp_common_rv64_pkg::rv64_sscratch_s), line:1266:9, endln:1266:21 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiName:bp_common_rv64_pkg::rv64_sscratch_s |vpiInstance: \_package: bp_be_pkg (bp_be_pkg::), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:2530:1, endln:3363:23 @@ -40613,7 +40613,7 @@ design: (work@testbench) |vpiTypedef: \_logic_typespec: (bp_common_rv64_pkg::rv64_stval_s), line:1308:9, endln:1308:21 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiName:bp_common_rv64_pkg::rv64_stval_s |vpiInstance: \_package: bp_be_pkg (bp_be_pkg::), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:2530:1, endln:3363:23 @@ -40638,7 +40638,7 @@ design: (work@testbench) |vpiTypedef: \_struct_typespec: (bp_common_rv64_pkg::rv64_stvec_s), line:1215:9, endln:1215:15 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiName:bp_common_rv64_pkg::rv64_stvec_s |vpiInstance: \_package: bp_be_pkg (bp_be_pkg::), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:2530:1, endln:3363:23 @@ -50271,7 +50271,7 @@ design: (work@testbench) |vpiTypespec: \_struct_typespec: (bp_common_aviary_pkg::bp_proc_param_s), line:2062:9, endln:2062:15 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiName:bp_common_aviary_pkg::bp_proc_param_s |vpiInstance: \_package: bp_common_aviary_pkg (bp_common_aviary_pkg::), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:2026:1, endln:2528:11 @@ -53849,7 +53849,7 @@ design: (work@testbench) |vpiTypedef: \_enum_typespec: (bp_common_aviary_pkg::bp_cfg_e), line:2504:3, endln:2513:14 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiName:bp_common_aviary_pkg::bp_cfg_e |vpiInstance: \_package: bp_common_aviary_pkg (bp_common_aviary_pkg::), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:2026:1, endln:2528:11 @@ -56097,7 +56097,7 @@ design: (work@testbench) |vpiTypedef: \_enum_typespec: (bp_be_pkg::bp_be_baddr_e), line:3041:1, endln:3045:17 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiName:bp_be_pkg::bp_be_baddr_e |vpiInstance: \_package: bp_be_pkg (bp_be_pkg::), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:2530:1, endln:3363:23 @@ -56121,7 +56121,7 @@ design: (work@testbench) |vpiTypedef: \_enum_typespec: (bp_be_pkg::bp_be_csr_fu_op_e), line:2994:1, endln:3017:21 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiName:bp_be_pkg::bp_be_csr_fu_op_e |vpiInstance: \_package: bp_be_pkg (bp_be_pkg::), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:2530:1, endln:3363:23 @@ -56241,7 +56241,7 @@ design: (work@testbench) |vpiTypedef: \_struct_typespec: (bp_be_pkg::bp_be_decode_s), line:3059:9, endln:3059:15 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiName:bp_be_pkg::bp_be_decode_s |vpiInstance: \_package: bp_be_pkg (bp_be_pkg::), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:2530:1, endln:3363:23 @@ -56542,7 +56542,7 @@ design: (work@testbench) |vpiTypespec: \_struct_typespec: (bp_be_pkg::bp_be_fu_op_s), line:3019:9, endln:3019:15 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiName:bp_be_pkg::bp_be_fu_op_s |vpiInstance: \_package: bp_be_pkg (bp_be_pkg::), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:2530:1, endln:3363:23 @@ -56567,7 +56567,7 @@ design: (work@testbench) |vpiTypespec: \_enum_typespec: (bp_be_pkg::bp_be_int_fu_op_e), line:2951:1, endln:2968:21 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiName:bp_be_pkg::bp_be_int_fu_op_e |vpiInstance: \_package: bp_be_pkg (bp_be_pkg::), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:2530:1, endln:3363:23 @@ -56697,7 +56697,7 @@ design: (work@testbench) |vpiTypespec: \_enum_typespec: (bp_be_pkg::bp_be_mmu_fu_op_e), line:2970:1, endln:2992:21 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiName:bp_be_pkg::bp_be_mmu_fu_op_e |vpiInstance: \_package: bp_be_pkg (bp_be_pkg::), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:2530:1, endln:3363:23 @@ -56855,7 +56855,7 @@ design: (work@testbench) |vpiTypespec: \_enum_typespec: (bp_be_pkg::bp_be_src1_e), line:3029:1, endln:3033:16 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiName:bp_be_pkg::bp_be_src1_e |vpiInstance: \_package: bp_be_pkg (bp_be_pkg::), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:2530:1, endln:3363:23 @@ -56889,7 +56889,7 @@ design: (work@testbench) |vpiTypespec: \_enum_typespec: (bp_be_pkg::bp_be_src2_e), line:3035:1, endln:3039:16 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiName:bp_be_pkg::bp_be_src2_e |vpiInstance: \_package: bp_be_pkg (bp_be_pkg::), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:2530:1, endln:3363:23 @@ -56935,7 +56935,7 @@ design: (work@testbench) |vpiTypespec: \_enum_typespec: (bp_be_pkg::bp_be_offset_e), line:3047:1, endln:3051:18 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiName:bp_be_pkg::bp_be_offset_e |vpiInstance: \_package: bp_be_pkg (bp_be_pkg::), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:2530:1, endln:3363:23 @@ -56969,7 +56969,7 @@ design: (work@testbench) |vpiTypespec: \_enum_typespec: (bp_be_pkg::bp_be_result_e), line:3053:1, endln:3057:18 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiName:bp_be_pkg::bp_be_result_e |vpiInstance: \_package: bp_be_pkg (bp_be_pkg::), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:2530:1, endln:3363:23 @@ -56998,7 +56998,7 @@ design: (work@testbench) |vpiTypedef: \_struct_typespec: (bp_be_pkg::bp_be_ecode_dec_s), line:3091:9, endln:3091:15 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiName:bp_be_pkg::bp_be_ecode_dec_s |vpiInstance: \_package: bp_be_pkg (bp_be_pkg::), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:2530:1, endln:3363:23 @@ -57262,7 +57262,7 @@ design: (work@testbench) |vpiTypedef: \_struct_typespec: (bp_be_pkg::bp_be_exception_s), line:3115:9, endln:3115:15 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiName:bp_be_pkg::bp_be_exception_s |vpiInstance: \_package: bp_be_pkg (bp_be_pkg::), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:2530:1, endln:3363:23 @@ -57446,7 +57446,7 @@ design: (work@testbench) |vpiTypedef: \_struct_typespec: (bp_be_pkg::bp_sv39_pte_s), line:3169:11, endln:3169:17 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiName:bp_be_pkg::bp_sv39_pte_s |vpiInstance: \_package: bp_be_pkg (bp_be_pkg::), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:2530:1, endln:3363:23 @@ -58065,7 +58065,7 @@ design: (work@testbench) |vpiTypedef: \_enum_typespec: (bp_me_nonsynth_pkg::bp_me_nonsynth_lce_opcode_e), line:4378:3, endln:4401:33 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiName:bp_me_nonsynth_pkg::bp_me_nonsynth_lce_opcode_e |vpiInstance: \_package: bp_me_nonsynth_pkg (bp_me_nonsynth_pkg::), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:4373:1, endln:4403:11 @@ -59606,7 +59606,7 @@ design: (work@testbench) |vpiTypedef: \_enum_typespec: (bp_me_pkg::bp_cce_inst_alu_op_e), line:4874:1, endln:4886:24 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiName:bp_me_pkg::bp_cce_inst_alu_op_e |vpiInstance: \_package: bp_me_pkg (bp_me_pkg::), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:4412:1, endln:5667:23 @@ -59701,7 +59701,7 @@ design: (work@testbench) |vpiTypedef: \_struct_typespec: (bp_me_pkg::bp_cce_inst_bftype_s), line:5366:9, endln:5366:15 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiName:bp_me_pkg::bp_cce_inst_bftype_s |vpiInstance: \_package: bp_me_pkg (bp_me_pkg::), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:4412:1, endln:5667:23 @@ -59781,7 +59781,7 @@ design: (work@testbench) |vpiTypedef: \_struct_typespec: (bp_me_pkg::bp_cce_inst_bitype_s), line:5348:9, endln:5348:15 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiName:bp_me_pkg::bp_cce_inst_bitype_s |vpiInstance: \_package: bp_me_pkg (bp_me_pkg::), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:4412:1, endln:5667:23 @@ -59902,7 +59902,7 @@ design: (work@testbench) |vpiTypespec: \_union_typespec: (bp_me_pkg::bp_cce_inst_src_u), line:5058:9, endln:5058:14 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiName:bp_me_pkg::bp_cce_inst_src_u |vpiInstance: \_package: bp_me_pkg (bp_me_pkg::), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:4412:1, endln:5667:23 @@ -59915,7 +59915,7 @@ design: (work@testbench) |vpiTypespec: \_enum_typespec: (bp_me_pkg::bp_cce_inst_opd_gpr_e), line:4934:1, endln:4943:25 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiName:bp_me_pkg::bp_cce_inst_opd_gpr_e |vpiInstance: \_package: bp_me_pkg (bp_me_pkg::), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:4412:1, endln:5667:23 @@ -60002,7 +60002,7 @@ design: (work@testbench) |vpiTypespec: \_enum_typespec: (bp_me_pkg::bp_cce_inst_opd_flag_e), line:4947:1, endln:4974:26 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiName:bp_me_pkg::bp_cce_inst_opd_flag_e |vpiInstance: \_package: bp_me_pkg (bp_me_pkg::), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:4412:1, endln:5667:23 @@ -60137,7 +60137,7 @@ design: (work@testbench) |vpiTypespec: \_enum_typespec: (bp_me_pkg::bp_cce_inst_opd_special_e), line:4999:1, endln:5019:29 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiName:bp_me_pkg::bp_cce_inst_opd_special_e |vpiInstance: \_package: bp_me_pkg (bp_me_pkg::), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:4412:1, endln:5667:23 @@ -60266,7 +60266,7 @@ design: (work@testbench) |vpiTypespec: \_enum_typespec: (bp_me_pkg::bp_cce_inst_opd_params_e), line:5024:1, endln:5033:28 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiName:bp_me_pkg::bp_cce_inst_opd_params_e |vpiInstance: \_package: bp_me_pkg (bp_me_pkg::), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:4412:1, endln:5667:23 @@ -60341,7 +60341,7 @@ design: (work@testbench) |vpiTypespec: \_enum_typespec: (bp_me_pkg::bp_cce_inst_opd_queue_e), line:5039:1, endln:5049:27 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiName:bp_me_pkg::bp_cce_inst_opd_queue_e |vpiInstance: \_package: bp_me_pkg (bp_me_pkg::), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:4412:1, endln:5667:23 @@ -60434,7 +60434,7 @@ design: (work@testbench) |vpiTypedef: \_enum_typespec: (bp_me_pkg::bp_cce_inst_branch_op_e), line:4893:1, endln:4898:27 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiName:bp_me_pkg::bp_cce_inst_branch_op_e |vpiInstance: \_package: bp_me_pkg (bp_me_pkg::), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:4412:1, endln:5667:23 @@ -60487,7 +60487,7 @@ design: (work@testbench) |vpiTypedef: \_struct_typespec: (bp_me_pkg::bp_cce_inst_btype_s), line:5328:9, endln:5328:15 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiName:bp_me_pkg::bp_cce_inst_btype_s |vpiInstance: \_package: bp_me_pkg (bp_me_pkg::), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:4412:1, endln:5667:23 @@ -60627,7 +60627,7 @@ design: (work@testbench) |vpiTypedef: \_struct_typespec: (bp_me_pkg::bp_cce_inst_decoded_s), line:5542:9, endln:5542:15 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiName:bp_me_pkg::bp_cce_inst_decoded_s |vpiInstance: \_package: bp_me_pkg (bp_me_pkg::), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:4412:1, endln:5667:23 @@ -60688,7 +60688,7 @@ design: (work@testbench) |vpiTypespec: \_enum_typespec: (bp_me_pkg::bp_cce_inst_op_e), line:4716:1, endln:4725:20 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiName:bp_me_pkg::bp_cce_inst_op_e |vpiInstance: \_package: bp_me_pkg (bp_me_pkg::), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:4412:1, endln:5667:23 @@ -60763,7 +60763,7 @@ design: (work@testbench) |vpiTypespec: \_union_typespec: (bp_me_pkg::bp_cce_inst_minor_op_u), line:4859:9, endln:4859:14 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiName:bp_me_pkg::bp_cce_inst_minor_op_u |vpiInstance: \_package: bp_me_pkg (bp_me_pkg::), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:4412:1, endln:5667:23 @@ -60776,7 +60776,7 @@ design: (work@testbench) |vpiTypespec: \_enum_typespec: (bp_me_pkg::bp_cce_inst_minor_alu_op_e), line:4732:1, endln:4749:30 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiName:bp_me_pkg::bp_cce_inst_minor_alu_op_e |vpiInstance: \_package: bp_me_pkg (bp_me_pkg::), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:4412:1, endln:5667:23 @@ -60893,7 +60893,7 @@ design: (work@testbench) |vpiTypespec: \_enum_typespec: (bp_me_pkg::bp_cce_inst_minor_branch_op_e), line:4752:1, endln:4770:33 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiName:bp_me_pkg::bp_cce_inst_minor_branch_op_e |vpiInstance: \_package: bp_me_pkg (bp_me_pkg::), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:4412:1, endln:5667:23 @@ -60986,7 +60986,7 @@ design: (work@testbench) |vpiTypespec: \_enum_typespec: (bp_me_pkg::bp_cce_inst_minor_reg_data_op_e), line:4773:1, endln:4788:35 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiName:bp_me_pkg::bp_cce_inst_minor_reg_data_op_e |vpiInstance: \_package: bp_me_pkg (bp_me_pkg::), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:4412:1, endln:5667:23 @@ -61091,7 +61091,7 @@ design: (work@testbench) |vpiTypespec: \_enum_typespec: (bp_me_pkg::bp_cce_inst_minor_flag_op_e), line:4807:1, endln:4820:31 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiName:bp_me_pkg::bp_cce_inst_minor_flag_op_e |vpiInstance: \_package: bp_me_pkg (bp_me_pkg::), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:4412:1, endln:5667:23 @@ -61190,7 +61190,7 @@ design: (work@testbench) |vpiTypespec: \_enum_typespec: (bp_me_pkg::bp_cce_inst_minor_dir_op_e), line:4823:1, endln:4833:30 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiName:bp_me_pkg::bp_cce_inst_minor_dir_op_e |vpiInstance: \_package: bp_me_pkg (bp_me_pkg::), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:4412:1, endln:5667:23 @@ -61283,7 +61283,7 @@ design: (work@testbench) |vpiTypespec: \_enum_typespec: (bp_me_pkg::bp_cce_inst_minor_queue_op_e), line:4846:1, endln:4856:32 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiName:bp_me_pkg::bp_cce_inst_minor_queue_op_e |vpiInstance: \_package: bp_me_pkg (bp_me_pkg::), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:4412:1, endln:5667:23 @@ -61369,7 +61369,7 @@ design: (work@testbench) |vpiTypespec: \_union_typespec: (bp_me_pkg::bp_cce_inst_dst_u), line:5083:9, endln:5083:14 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiName:bp_me_pkg::bp_cce_inst_dst_u |vpiInstance: \_package: bp_me_pkg (bp_me_pkg::), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:4412:1, endln:5667:23 @@ -61435,7 +61435,7 @@ design: (work@testbench) |vpiTypespec: \_enum_typespec: (bp_me_pkg::bp_cce_inst_dst_sel_e), line:5090:1, endln:5095:25 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiName:bp_me_pkg::bp_cce_inst_dst_sel_e |vpiInstance: \_package: bp_me_pkg (bp_me_pkg::), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:4412:1, endln:5667:23 @@ -61510,7 +61510,7 @@ design: (work@testbench) |vpiTypespec: \_enum_typespec: (bp_me_pkg::bp_cce_inst_src_sel_e), line:5066:1, endln:5074:25 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiName:bp_me_pkg::bp_cce_inst_src_sel_e |vpiInstance: \_package: bp_me_pkg (bp_me_pkg::), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:4412:1, endln:5667:23 @@ -61615,7 +61615,7 @@ design: (work@testbench) |vpiTypespec: \_enum_typespec: (bp_me_pkg::bp_cce_inst_mux_sel_addr_e), line:5108:1, endln:5124:30 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiName:bp_me_pkg::bp_cce_inst_mux_sel_addr_e |vpiInstance: \_package: bp_me_pkg (bp_me_pkg::), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:4412:1, endln:5667:23 @@ -61744,7 +61744,7 @@ design: (work@testbench) |vpiTypespec: \_enum_typespec: (bp_me_pkg::bp_cce_inst_mux_sel_lce_e), line:5129:1, endln:5145:29 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiName:bp_me_pkg::bp_cce_inst_mux_sel_lce_e |vpiInstance: \_package: bp_me_pkg (bp_me_pkg::), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:4412:1, endln:5667:23 @@ -61873,7 +61873,7 @@ design: (work@testbench) |vpiTypespec: \_enum_typespec: (bp_me_pkg::bp_cce_inst_mux_sel_way_e), line:5150:1, endln:5164:29 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiName:bp_me_pkg::bp_cce_inst_mux_sel_way_e |vpiInstance: \_package: bp_me_pkg (bp_me_pkg::), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:4412:1, endln:5667:23 @@ -62002,7 +62002,7 @@ design: (work@testbench) |vpiTypespec: \_enum_typespec: (bp_me_pkg::bp_cce_inst_mux_sel_coh_state_e), line:5170:1, endln:5184:35 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiName:bp_me_pkg::bp_cce_inst_mux_sel_coh_state_e |vpiInstance: \_package: bp_me_pkg (bp_me_pkg::), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:4412:1, endln:5667:23 @@ -62439,7 +62439,7 @@ design: (work@testbench) |vpiTypespec: \_struct_typespec: (bp_me_pkg::bp_cce_spec_s), line:4917:9, endln:4917:15 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiName:bp_me_pkg::bp_cce_spec_s |vpiInstance: \_package: bp_me_pkg (bp_me_pkg::), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:4412:1, endln:5667:23 @@ -62614,7 +62614,7 @@ design: (work@testbench) |vpiTypespec: \_enum_typespec: (bp_me_pkg::bp_cce_inst_dst_q_sel_e), line:5222:1, endln:5225:27 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiName:bp_me_pkg::bp_cce_inst_dst_q_sel_e |vpiInstance: \_package: bp_me_pkg (bp_me_pkg::), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:4412:1, endln:5667:23 @@ -62665,7 +62665,7 @@ design: (work@testbench) |vpiTypespec: \_enum_typespec: (bp_me_pkg::bp_cce_inst_src_q_sel_e), line:5204:1, endln:5209:27 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiName:bp_me_pkg::bp_cce_inst_src_q_sel_e |vpiInstance: \_package: bp_me_pkg (bp_me_pkg::), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:4412:1, endln:5667:23 @@ -63181,7 +63181,7 @@ design: (work@testbench) |vpiTypedef: \_struct_typespec: (bp_me_pkg::bp_cce_inst_dptype_s), line:5399:9, endln:5399:15 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiName:bp_me_pkg::bp_cce_inst_dptype_s |vpiInstance: \_package: bp_me_pkg (bp_me_pkg::), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:4412:1, endln:5667:23 @@ -63265,7 +63265,7 @@ design: (work@testbench) |vpiTypedef: \_struct_typespec: (bp_me_pkg::bp_cce_inst_drtype_s), line:5419:9, endln:5419:15 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiName:bp_me_pkg::bp_cce_inst_drtype_s |vpiInstance: \_package: bp_me_pkg (bp_me_pkg::), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:4412:1, endln:5667:23 @@ -63381,7 +63381,7 @@ design: (work@testbench) |vpiTypedef: \_enum_typespec: (bp_me_pkg::bp_cce_inst_dst_q_e), line:5214:1, endln:5217:23 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiName:bp_me_pkg::bp_cce_inst_dst_q_e |vpiInstance: \_package: bp_me_pkg (bp_me_pkg::), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:4412:1, endln:5667:23 @@ -63428,7 +63428,7 @@ design: (work@testbench) |vpiTypedef: \_struct_typespec: (bp_me_pkg::bp_cce_inst_dwtype_s), line:5443:9, endln:5443:15 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiName:bp_me_pkg::bp_cce_inst_dwtype_s |vpiInstance: \_package: bp_me_pkg (bp_me_pkg::), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:4412:1, endln:5667:23 @@ -63544,7 +63544,7 @@ design: (work@testbench) |vpiTypedef: \_enum_typespec: (bp_me_pkg::bp_cce_inst_flag_onehot_e), line:4977:1, endln:4994:29 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiName:bp_me_pkg::bp_cce_inst_flag_onehot_e |vpiInstance: \_package: bp_me_pkg (bp_me_pkg::), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:4412:1, endln:5667:23 @@ -63669,7 +63669,7 @@ design: (work@testbench) |vpiTypedef: \_struct_typespec: (bp_me_pkg::bp_cce_inst_itype_s), line:5277:9, endln:5277:15 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiName:bp_me_pkg::bp_cce_inst_itype_s |vpiInstance: \_package: bp_me_pkg (bp_me_pkg::), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:4412:1, endln:5667:23 @@ -63781,7 +63781,7 @@ design: (work@testbench) |vpiTypedef: \_enum_typespec: (bp_me_pkg::bp_cce_inst_minor_mem_op_e), line:4795:1, endln:4804:30 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiName:bp_me_pkg::bp_cce_inst_minor_mem_op_e |vpiInstance: \_package: bp_me_pkg (bp_me_pkg::), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:4412:1, endln:5667:23 @@ -63864,7 +63864,7 @@ design: (work@testbench) |vpiTypedef: \_struct_typespec: (bp_me_pkg::bp_cce_inst_mltype_s), line:5297:9, endln:5297:15 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiName:bp_me_pkg::bp_cce_inst_mltype_s |vpiInstance: \_package: bp_me_pkg (bp_me_pkg::), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:4412:1, endln:5667:23 @@ -63948,7 +63948,7 @@ design: (work@testbench) |vpiTypedef: \_struct_typespec: (bp_me_pkg::bp_cce_inst_mstype_s), line:5313:9, endln:5313:15 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiName:bp_me_pkg::bp_cce_inst_mstype_s |vpiInstance: \_package: bp_me_pkg (bp_me_pkg::), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:4412:1, endln:5667:23 @@ -64052,7 +64052,7 @@ design: (work@testbench) |vpiTypedef: \_struct_typespec: (bp_me_pkg::bp_cce_inst_popq_s), line:5466:9, endln:5466:15 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiName:bp_me_pkg::bp_cce_inst_popq_s |vpiInstance: \_package: bp_me_pkg (bp_me_pkg::), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:4412:1, endln:5667:23 @@ -64172,7 +64172,7 @@ design: (work@testbench) |vpiTypedef: \_struct_typespec: (bp_me_pkg::bp_cce_inst_pushq_s), line:5485:9, endln:5485:15 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiName:bp_me_pkg::bp_cce_inst_pushq_s |vpiInstance: \_package: bp_me_pkg (bp_me_pkg::), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:4412:1, endln:5667:23 @@ -64392,7 +64392,7 @@ design: (work@testbench) |vpiTypedef: \_struct_typespec: (bp_me_pkg::bp_cce_inst_rtype_s), line:5258:9, endln:5258:15 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiName:bp_me_pkg::bp_cce_inst_rtype_s |vpiInstance: \_package: bp_me_pkg (bp_me_pkg::), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:4412:1, endln:5667:23 @@ -64472,7 +64472,7 @@ design: (work@testbench) |vpiTypedef: \_struct_typespec: (bp_me_pkg::bp_cce_inst_s), line:5528:9, endln:5528:15 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiName:bp_me_pkg::bp_cce_inst_s |vpiInstance: \_package: bp_me_pkg (bp_me_pkg::), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:4412:1, endln:5667:23 @@ -64517,7 +64517,7 @@ design: (work@testbench) |vpiTypespec: \_union_typespec: (bp_me_pkg::bp_cce_inst_type_u), line:5512:9, endln:5512:14 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiName:bp_me_pkg::bp_cce_inst_type_u |vpiInstance: \_package: bp_me_pkg (bp_me_pkg::), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:4412:1, endln:5667:23 @@ -64614,7 +64614,7 @@ design: (work@testbench) |vpiTypespec: \_struct_typespec: (bp_me_pkg::bp_cce_inst_stype_s), line:5379:9, endln:5379:15 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiName:bp_me_pkg::bp_cce_inst_stype_s |vpiInstance: \_package: bp_me_pkg (bp_me_pkg::), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:4412:1, endln:5667:23 @@ -64699,7 +64699,7 @@ design: (work@testbench) |vpiTypespec: \_enum_typespec: (bp_me_pkg::bp_cce_inst_spec_op_e), line:4905:1, endln:4911:25 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiName:bp_me_pkg::bp_cce_inst_spec_op_e |vpiInstance: \_package: bp_me_pkg (bp_me_pkg::), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:4412:1, endln:5667:23 @@ -64859,7 +64859,7 @@ design: (work@testbench) |vpiTypedef: \_enum_typespec: (bp_me_pkg::bp_cce_inst_src_q_e), line:5194:1, endln:5199:23 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiName:bp_me_pkg::bp_cce_inst_src_q_e |vpiInstance: \_package: bp_me_pkg (bp_me_pkg::), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:4412:1, endln:5667:23 @@ -64958,7 +64958,7 @@ design: (work@testbench) |vpiTypedef: \_enum_typespec: (bsg_noc_pkg::Dirs), line:5672:3, endln:5672:53 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiName:bsg_noc_pkg::Dirs |vpiInstance: \_package: bsg_noc_pkg (bsg_noc_pkg::), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5669:1, endln:5673:11 @@ -65017,14 +65017,14 @@ design: (work@testbench) |vpiDefName:bsg_noc_pkg |vpiTop:1 |uhdmallModules: -\_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 +\_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiParent: \_design: (work@testbench) |vpiFullName:work@bp_me_nonsynth_lce_tracer |vpiParameter: \_parameter: (work@bp_me_nonsynth_lce_tracer.bp_data_cmd_num_flit_gp), line:911:13, endln:911:36 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |UINT:4 |vpiTypespec: \_int_typespec: @@ -65036,7 +65036,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@bp_me_nonsynth_lce_tracer.bp_data_resp_num_flit_gp), line:910:13, endln:910:37 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |UINT:4 |vpiTypespec: \_int_typespec: @@ -65048,7 +65048,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@bp_me_nonsynth_lce_tracer.bp_eaddr_width_gp), line:899:14, endln:899:31 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |UINT:64 |vpiTypespec: \_int_typespec: @@ -65061,7 +65061,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@bp_me_nonsynth_lce_tracer.bp_instr_width_gp), line:900:14, endln:900:31 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |UINT:32 |vpiTypespec: \_int_typespec: @@ -65074,7 +65074,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@bp_me_nonsynth_lce_tracer.bp_log_file_gp), line:80:12, endln:80:26 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |UINT:2 |vpiTypespec: \_int_typespec: @@ -65087,7 +65087,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@bp_me_nonsynth_lce_tracer.bp_log_none_gp), line:78:12, endln:78:26 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |UINT:0 |vpiTypespec: \_int_typespec: @@ -65100,7 +65100,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@bp_me_nonsynth_lce_tracer.bp_log_stdout_gp), line:79:12, endln:79:28 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |UINT:1 |vpiTypespec: \_int_typespec: @@ -65113,7 +65113,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@bp_me_nonsynth_lce_tracer.bp_page_offset_width_gp), line:908:13, endln:908:36 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |INT:12 |vpiTypespec: \_int_typespec: @@ -65125,7 +65125,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@bp_me_nonsynth_lce_tracer.bp_page_size_in_bytes_gp), line:907:13, endln:907:37 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |UINT:4096 |vpiTypespec: \_int_typespec: @@ -65137,7 +65137,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@bp_me_nonsynth_lce_tracer.bp_sv39_paddr_width_gp), line:905:13, endln:905:35 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |UINT:56 |vpiTypespec: \_int_typespec: @@ -65149,7 +65149,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@bp_me_nonsynth_lce_tracer.bp_sv39_page_table_depth_gp), line:902:13, endln:902:40 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |UINT:3 |vpiTypespec: \_int_typespec: @@ -65161,7 +65161,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@bp_me_nonsynth_lce_tracer.bp_sv39_ppn_width_gp), line:906:13, endln:906:33 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |UINT:44 |vpiTypespec: \_int_typespec: @@ -65173,7 +65173,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@bp_me_nonsynth_lce_tracer.bp_sv39_pte_width_gp), line:903:13, endln:903:33 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |UINT:64 |vpiTypespec: \_int_typespec: @@ -65185,7 +65185,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@bp_me_nonsynth_lce_tracer.bp_sv39_vaddr_width_gp), line:904:13, endln:904:35 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |UINT:39 |vpiTypespec: \_int_typespec: @@ -65197,7 +65197,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@bp_me_nonsynth_lce_tracer.cfg_link_dev_base_addr_gp), line:915:14, endln:915:39 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |HEX:01?????? |vpiTypespec: \_int_typespec: @@ -65224,7 +65224,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@bp_me_nonsynth_lce_tracer.clint_dev_base_addr_gp), line:916:14, endln:916:36 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |HEX:02?????? |vpiTypespec: \_int_typespec: @@ -65251,7 +65251,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@bp_me_nonsynth_lce_tracer.dram_base_addr_gp), line:913:14, endln:913:31 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |HEX:80000000 |vpiTypespec: \_int_typespec: @@ -65278,7 +65278,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@bp_me_nonsynth_lce_tracer.host_dev_base_addr_gp), line:917:14, endln:917:35 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |HEX:03?????? |vpiTypespec: \_int_typespec: @@ -65305,7 +65305,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@bp_me_nonsynth_lce_tracer.mipi_reg_base_addr_gp), line:920:14, endln:920:35 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |HEX:02000??? |vpiTypespec: \_int_typespec: @@ -65332,7 +65332,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@bp_me_nonsynth_lce_tracer.mtime_reg_addr_gp), line:922:14, endln:922:31 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |HEX:0200bff8 |vpiTypespec: \_int_typespec: @@ -65359,7 +65359,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@bp_me_nonsynth_lce_tracer.mtimecmp_reg_base_addr_gp), line:921:14, endln:921:39 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |HEX:02004??? |vpiTypespec: \_int_typespec: @@ -65386,7 +65386,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@bp_me_nonsynth_lce_tracer.plic_dev_base_addr_gp), line:918:14, endln:918:35 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |HEX:0c?????? |vpiTypespec: \_int_typespec: @@ -65413,7 +65413,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@bp_me_nonsynth_lce_tracer.plic_reg_base_addr_gp), line:923:14, endln:923:35 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |HEX:0c000??? |vpiTypespec: \_int_typespec: @@ -65440,7 +65440,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@bp_me_nonsynth_lce_tracer.all_cfgs_gp), line:2516:44, endln:2516:55 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiTypespec: \_packed_array_typespec: , line:2516:13, endln:2516:28 |vpiParent: @@ -66161,7 +66161,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@bp_me_nonsynth_lce_tracer.bp_dual_core_cfg_p), line:2300:30, endln:2300:48 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiTypespec: \_struct_typespec: (bp_common_aviary_pkg::bp_proc_param_s), line:2062:9, endln:2062:15 |vpiParent: @@ -66857,7 +66857,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@bp_me_nonsynth_lce_tracer.bp_half_core_cfg_p), line:2198:30, endln:2198:48 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiTypespec: \_struct_typespec: (bp_common_aviary_pkg::bp_proc_param_s), line:2062:9, endln:2062:15 |vpiParent: @@ -67553,7 +67553,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@bp_me_nonsynth_lce_tracer.bp_inv_cfg_p), line:2195:30, endln:2195:42 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiTypespec: \_struct_typespec: (bp_common_aviary_pkg::bp_proc_param_s), line:2062:9, endln:2062:15 |vpiParent: @@ -68249,7 +68249,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@bp_me_nonsynth_lce_tracer.bp_oct_core_cfg_p), line:2402:30, endln:2402:47 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiTypespec: \_struct_typespec: (bp_common_aviary_pkg::bp_proc_param_s), line:2062:9, endln:2062:15 |vpiParent: @@ -68945,7 +68945,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@bp_me_nonsynth_lce_tracer.bp_quad_core_cfg_p), line:2351:30, endln:2351:48 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiTypespec: \_struct_typespec: (bp_common_aviary_pkg::bp_proc_param_s), line:2062:9, endln:2062:15 |vpiParent: @@ -69641,7 +69641,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@bp_me_nonsynth_lce_tracer.bp_sexta_core_cfg_p), line:2453:30, endln:2453:49 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiTypespec: \_struct_typespec: (bp_common_aviary_pkg::bp_proc_param_s), line:2062:9, endln:2062:15 |vpiParent: @@ -70337,7 +70337,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@bp_me_nonsynth_lce_tracer.bp_single_core_cfg_p), line:2249:30, endln:2249:50 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiTypespec: \_struct_typespec: (bp_common_aviary_pkg::bp_proc_param_s), line:2062:9, endln:2062:15 |vpiParent: @@ -71033,7 +71033,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@bp_me_nonsynth_lce_tracer.lg_max_cfgs), line:2193:14, endln:2193:25 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |INT:7 |vpiTypespec: \_int_typespec: @@ -71046,7 +71046,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@bp_me_nonsynth_lce_tracer.max_cfgs), line:2192:14, endln:2192:22 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |UINT:128 |vpiTypespec: \_int_typespec: @@ -71059,7 +71059,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@bp_me_nonsynth_lce_tracer.bp_params_p), line:5680:27, endln:5680:38 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiTypespec: \_unsupported_typespec: (bp_params_e), line:5680:15, endln:5680:26 |vpiParent: @@ -71070,7 +71070,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@bp_me_nonsynth_lce_tracer.proc_param_lp), line:5682:32, endln:5682:45 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiTypespec: \_struct_typespec: (bp_common_aviary_pkg::bp_proc_param_s), line:2062:9, endln:2062:15 |vpiLocalParam:1 @@ -71079,434 +71079,434 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@bp_me_nonsynth_lce_tracer.multicore_p), line:5684:16, endln:5684:27 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiLocalParam:1 |vpiName:multicore_p |vpiFullName:work@bp_me_nonsynth_lce_tracer.multicore_p |vpiParameter: \_parameter: (work@bp_me_nonsynth_lce_tracer.cc_x_dim_p), line:5686:16, endln:5686:26 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiLocalParam:1 |vpiName:cc_x_dim_p |vpiFullName:work@bp_me_nonsynth_lce_tracer.cc_x_dim_p |vpiParameter: \_parameter: (work@bp_me_nonsynth_lce_tracer.cc_y_dim_p), line:5687:16, endln:5687:26 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiLocalParam:1 |vpiName:cc_y_dim_p |vpiFullName:work@bp_me_nonsynth_lce_tracer.cc_y_dim_p |vpiParameter: \_parameter: (work@bp_me_nonsynth_lce_tracer.ic_x_dim_p), line:5689:16, endln:5689:26 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiLocalParam:1 |vpiName:ic_x_dim_p |vpiFullName:work@bp_me_nonsynth_lce_tracer.ic_x_dim_p |vpiParameter: \_parameter: (work@bp_me_nonsynth_lce_tracer.ic_y_dim_p), line:5690:16, endln:5690:26 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiLocalParam:1 |vpiName:ic_y_dim_p |vpiFullName:work@bp_me_nonsynth_lce_tracer.ic_y_dim_p |vpiParameter: \_parameter: (work@bp_me_nonsynth_lce_tracer.mc_x_dim_p), line:5691:16, endln:5691:26 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiLocalParam:1 |vpiName:mc_x_dim_p |vpiFullName:work@bp_me_nonsynth_lce_tracer.mc_x_dim_p |vpiParameter: \_parameter: (work@bp_me_nonsynth_lce_tracer.mc_y_dim_p), line:5692:16, endln:5692:26 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiLocalParam:1 |vpiName:mc_y_dim_p |vpiFullName:work@bp_me_nonsynth_lce_tracer.mc_y_dim_p |vpiParameter: \_parameter: (work@bp_me_nonsynth_lce_tracer.cac_x_dim_p), line:5693:16, endln:5693:27 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiLocalParam:1 |vpiName:cac_x_dim_p |vpiFullName:work@bp_me_nonsynth_lce_tracer.cac_x_dim_p |vpiParameter: \_parameter: (work@bp_me_nonsynth_lce_tracer.cac_y_dim_p), line:5694:16, endln:5694:27 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiLocalParam:1 |vpiName:cac_y_dim_p |vpiFullName:work@bp_me_nonsynth_lce_tracer.cac_y_dim_p |vpiParameter: \_parameter: (work@bp_me_nonsynth_lce_tracer.sac_x_dim_p), line:5695:16, endln:5695:27 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiLocalParam:1 |vpiName:sac_x_dim_p |vpiFullName:work@bp_me_nonsynth_lce_tracer.sac_x_dim_p |vpiParameter: \_parameter: (work@bp_me_nonsynth_lce_tracer.sac_y_dim_p), line:5696:16, endln:5696:27 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiLocalParam:1 |vpiName:sac_y_dim_p |vpiFullName:work@bp_me_nonsynth_lce_tracer.sac_y_dim_p |vpiParameter: \_parameter: (work@bp_me_nonsynth_lce_tracer.cacc_type_p), line:5697:16, endln:5697:27 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiLocalParam:1 |vpiName:cacc_type_p |vpiFullName:work@bp_me_nonsynth_lce_tracer.cacc_type_p |vpiParameter: \_parameter: (work@bp_me_nonsynth_lce_tracer.sacc_type_p), line:5698:16, endln:5698:27 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiLocalParam:1 |vpiName:sacc_type_p |vpiFullName:work@bp_me_nonsynth_lce_tracer.sacc_type_p |vpiParameter: \_parameter: (work@bp_me_nonsynth_lce_tracer.num_core_p), line:5700:16, endln:5700:26 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiLocalParam:1 |vpiName:num_core_p |vpiFullName:work@bp_me_nonsynth_lce_tracer.num_core_p |vpiParameter: \_parameter: (work@bp_me_nonsynth_lce_tracer.num_io_p), line:5701:16, endln:5701:24 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiLocalParam:1 |vpiName:num_io_p |vpiFullName:work@bp_me_nonsynth_lce_tracer.num_io_p |vpiParameter: \_parameter: (work@bp_me_nonsynth_lce_tracer.num_l2e_p), line:5702:16, endln:5702:25 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiLocalParam:1 |vpiName:num_l2e_p |vpiFullName:work@bp_me_nonsynth_lce_tracer.num_l2e_p |vpiParameter: \_parameter: (work@bp_me_nonsynth_lce_tracer.num_cacc_p), line:5703:16, endln:5703:26 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiLocalParam:1 |vpiName:num_cacc_p |vpiFullName:work@bp_me_nonsynth_lce_tracer.num_cacc_p |vpiParameter: \_parameter: (work@bp_me_nonsynth_lce_tracer.num_sacc_p), line:5704:16, endln:5704:26 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiLocalParam:1 |vpiName:num_sacc_p |vpiFullName:work@bp_me_nonsynth_lce_tracer.num_sacc_p |vpiParameter: \_parameter: (work@bp_me_nonsynth_lce_tracer.num_cce_p), line:5706:16, endln:5706:25 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiLocalParam:1 |vpiName:num_cce_p |vpiFullName:work@bp_me_nonsynth_lce_tracer.num_cce_p |vpiParameter: \_parameter: (work@bp_me_nonsynth_lce_tracer.num_lce_p), line:5707:16, endln:5707:25 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiLocalParam:1 |vpiName:num_lce_p |vpiFullName:work@bp_me_nonsynth_lce_tracer.num_lce_p |vpiParameter: \_parameter: (work@bp_me_nonsynth_lce_tracer.core_id_width_p), line:5709:16, endln:5709:31 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiLocalParam:1 |vpiName:core_id_width_p |vpiFullName:work@bp_me_nonsynth_lce_tracer.core_id_width_p |vpiParameter: \_parameter: (work@bp_me_nonsynth_lce_tracer.cce_id_width_p), line:5710:16, endln:5710:30 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiLocalParam:1 |vpiName:cce_id_width_p |vpiFullName:work@bp_me_nonsynth_lce_tracer.cce_id_width_p |vpiParameter: \_parameter: (work@bp_me_nonsynth_lce_tracer.lce_id_width_p), line:5711:16, endln:5711:30 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiLocalParam:1 |vpiName:lce_id_width_p |vpiFullName:work@bp_me_nonsynth_lce_tracer.lce_id_width_p |vpiParameter: \_parameter: (work@bp_me_nonsynth_lce_tracer.vaddr_width_p), line:5713:16, endln:5713:29 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiLocalParam:1 |vpiName:vaddr_width_p |vpiFullName:work@bp_me_nonsynth_lce_tracer.vaddr_width_p |vpiParameter: \_parameter: (work@bp_me_nonsynth_lce_tracer.paddr_width_p), line:5714:16, endln:5714:29 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiLocalParam:1 |vpiName:paddr_width_p |vpiFullName:work@bp_me_nonsynth_lce_tracer.paddr_width_p |vpiParameter: \_parameter: (work@bp_me_nonsynth_lce_tracer.asid_width_p), line:5715:16, endln:5715:28 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiLocalParam:1 |vpiName:asid_width_p |vpiFullName:work@bp_me_nonsynth_lce_tracer.asid_width_p |vpiParameter: \_parameter: (work@bp_me_nonsynth_lce_tracer.boot_pc_p), line:5717:16, endln:5717:25 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiLocalParam:1 |vpiName:boot_pc_p |vpiFullName:work@bp_me_nonsynth_lce_tracer.boot_pc_p |vpiParameter: \_parameter: (work@bp_me_nonsynth_lce_tracer.boot_in_debug_p), line:5718:16, endln:5718:31 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiLocalParam:1 |vpiName:boot_in_debug_p |vpiFullName:work@bp_me_nonsynth_lce_tracer.boot_in_debug_p |vpiParameter: \_parameter: (work@bp_me_nonsynth_lce_tracer.branch_metadata_fwd_width_p), line:5720:16, endln:5720:43 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiLocalParam:1 |vpiName:branch_metadata_fwd_width_p |vpiFullName:work@bp_me_nonsynth_lce_tracer.branch_metadata_fwd_width_p |vpiParameter: \_parameter: (work@bp_me_nonsynth_lce_tracer.btb_tag_width_p), line:5721:16, endln:5721:31 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiLocalParam:1 |vpiName:btb_tag_width_p |vpiFullName:work@bp_me_nonsynth_lce_tracer.btb_tag_width_p |vpiParameter: \_parameter: (work@bp_me_nonsynth_lce_tracer.btb_idx_width_p), line:5722:16, endln:5722:31 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiLocalParam:1 |vpiName:btb_idx_width_p |vpiFullName:work@bp_me_nonsynth_lce_tracer.btb_idx_width_p |vpiParameter: \_parameter: (work@bp_me_nonsynth_lce_tracer.bht_idx_width_p), line:5723:16, endln:5723:31 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiLocalParam:1 |vpiName:bht_idx_width_p |vpiFullName:work@bp_me_nonsynth_lce_tracer.bht_idx_width_p |vpiParameter: \_parameter: (work@bp_me_nonsynth_lce_tracer.ghist_width_p), line:5724:16, endln:5724:29 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiLocalParam:1 |vpiName:ghist_width_p |vpiFullName:work@bp_me_nonsynth_lce_tracer.ghist_width_p |vpiParameter: \_parameter: (work@bp_me_nonsynth_lce_tracer.itlb_els_p), line:5726:16, endln:5726:26 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiLocalParam:1 |vpiName:itlb_els_p |vpiFullName:work@bp_me_nonsynth_lce_tracer.itlb_els_p |vpiParameter: \_parameter: (work@bp_me_nonsynth_lce_tracer.dtlb_els_p), line:5727:16, endln:5727:26 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiLocalParam:1 |vpiName:dtlb_els_p |vpiFullName:work@bp_me_nonsynth_lce_tracer.dtlb_els_p |vpiParameter: \_parameter: (work@bp_me_nonsynth_lce_tracer.lr_sc_p), line:5729:16, endln:5729:23 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiLocalParam:1 |vpiName:lr_sc_p |vpiFullName:work@bp_me_nonsynth_lce_tracer.lr_sc_p |vpiParameter: \_parameter: (work@bp_me_nonsynth_lce_tracer.amo_swap_p), line:5730:16, endln:5730:26 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiLocalParam:1 |vpiName:amo_swap_p |vpiFullName:work@bp_me_nonsynth_lce_tracer.amo_swap_p |vpiParameter: \_parameter: (work@bp_me_nonsynth_lce_tracer.amo_fetch_logic_p), line:5731:16, endln:5731:33 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiLocalParam:1 |vpiName:amo_fetch_logic_p |vpiFullName:work@bp_me_nonsynth_lce_tracer.amo_fetch_logic_p |vpiParameter: \_parameter: (work@bp_me_nonsynth_lce_tracer.amo_fetch_arithmetic_p), line:5732:16, endln:5732:38 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiLocalParam:1 |vpiName:amo_fetch_arithmetic_p |vpiFullName:work@bp_me_nonsynth_lce_tracer.amo_fetch_arithmetic_p |vpiParameter: \_parameter: (work@bp_me_nonsynth_lce_tracer.l1_coherent_p), line:5734:16, endln:5734:29 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiLocalParam:1 |vpiName:l1_coherent_p |vpiFullName:work@bp_me_nonsynth_lce_tracer.l1_coherent_p |vpiParameter: \_parameter: (work@bp_me_nonsynth_lce_tracer.l1_writethrough_p), line:5735:16, endln:5735:33 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiLocalParam:1 |vpiName:l1_writethrough_p |vpiFullName:work@bp_me_nonsynth_lce_tracer.l1_writethrough_p |vpiParameter: \_parameter: (work@bp_me_nonsynth_lce_tracer.dcache_sets_p), line:5736:16, endln:5736:29 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiLocalParam:1 |vpiName:dcache_sets_p |vpiFullName:work@bp_me_nonsynth_lce_tracer.dcache_sets_p |vpiParameter: \_parameter: (work@bp_me_nonsynth_lce_tracer.dcache_assoc_p), line:5737:16, endln:5737:30 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiLocalParam:1 |vpiName:dcache_assoc_p |vpiFullName:work@bp_me_nonsynth_lce_tracer.dcache_assoc_p |vpiParameter: \_parameter: (work@bp_me_nonsynth_lce_tracer.dcache_block_width_p), line:5738:16, endln:5738:36 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiLocalParam:1 |vpiName:dcache_block_width_p |vpiFullName:work@bp_me_nonsynth_lce_tracer.dcache_block_width_p |vpiParameter: \_parameter: (work@bp_me_nonsynth_lce_tracer.dcache_fill_width_p), line:5739:16, endln:5739:35 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiLocalParam:1 |vpiName:dcache_fill_width_p |vpiFullName:work@bp_me_nonsynth_lce_tracer.dcache_fill_width_p |vpiParameter: \_parameter: (work@bp_me_nonsynth_lce_tracer.icache_sets_p), line:5740:16, endln:5740:29 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiLocalParam:1 |vpiName:icache_sets_p |vpiFullName:work@bp_me_nonsynth_lce_tracer.icache_sets_p |vpiParameter: \_parameter: (work@bp_me_nonsynth_lce_tracer.icache_assoc_p), line:5741:16, endln:5741:30 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiLocalParam:1 |vpiName:icache_assoc_p |vpiFullName:work@bp_me_nonsynth_lce_tracer.icache_assoc_p |vpiParameter: \_parameter: (work@bp_me_nonsynth_lce_tracer.icache_block_width_p), line:5742:16, endln:5742:36 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiLocalParam:1 |vpiName:icache_block_width_p |vpiFullName:work@bp_me_nonsynth_lce_tracer.icache_block_width_p |vpiParameter: \_parameter: (work@bp_me_nonsynth_lce_tracer.icache_fill_width_p), line:5743:16, endln:5743:35 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiLocalParam:1 |vpiName:icache_fill_width_p |vpiFullName:work@bp_me_nonsynth_lce_tracer.icache_fill_width_p |vpiParameter: \_parameter: (work@bp_me_nonsynth_lce_tracer.acache_sets_p), line:5744:16, endln:5744:29 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiLocalParam:1 |vpiName:acache_sets_p |vpiFullName:work@bp_me_nonsynth_lce_tracer.acache_sets_p |vpiParameter: \_parameter: (work@bp_me_nonsynth_lce_tracer.acache_assoc_p), line:5745:16, endln:5745:30 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiLocalParam:1 |vpiName:acache_assoc_p |vpiFullName:work@bp_me_nonsynth_lce_tracer.acache_assoc_p |vpiParameter: \_parameter: (work@bp_me_nonsynth_lce_tracer.acache_block_width_p), line:5746:16, endln:5746:36 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiLocalParam:1 |vpiName:acache_block_width_p |vpiFullName:work@bp_me_nonsynth_lce_tracer.acache_block_width_p |vpiParameter: \_parameter: (work@bp_me_nonsynth_lce_tracer.acache_fill_width_p), line:5747:16, endln:5747:35 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiLocalParam:1 |vpiName:acache_fill_width_p |vpiFullName:work@bp_me_nonsynth_lce_tracer.acache_fill_width_p |vpiParameter: \_parameter: (work@bp_me_nonsynth_lce_tracer.lce_assoc_p), line:5748:16, endln:5748:27 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiLocalParam:1 |vpiName:lce_assoc_p |vpiFullName:work@bp_me_nonsynth_lce_tracer.lce_assoc_p |vpiParameter: \_parameter: (work@bp_me_nonsynth_lce_tracer.lce_assoc_width_p), line:5752:16, endln:5752:33 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiLocalParam:1 |vpiName:lce_assoc_width_p |vpiFullName:work@bp_me_nonsynth_lce_tracer.lce_assoc_width_p |vpiParameter: \_parameter: (work@bp_me_nonsynth_lce_tracer.lce_sets_p), line:5753:16, endln:5753:26 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiLocalParam:1 |vpiName:lce_sets_p |vpiFullName:work@bp_me_nonsynth_lce_tracer.lce_sets_p |vpiParameter: \_parameter: (work@bp_me_nonsynth_lce_tracer.lce_sets_width_p), line:5757:16, endln:5757:32 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiLocalParam:1 |vpiName:lce_sets_width_p |vpiFullName:work@bp_me_nonsynth_lce_tracer.lce_sets_width_p |vpiParameter: \_parameter: (work@bp_me_nonsynth_lce_tracer.cce_block_width_p), line:5759:16, endln:5759:33 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiLocalParam:1 |vpiName:cce_block_width_p |vpiFullName:work@bp_me_nonsynth_lce_tracer.cce_block_width_p |vpiParameter: \_parameter: (work@bp_me_nonsynth_lce_tracer.cce_pc_width_p), line:5771:16, endln:5771:30 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiLocalParam:1 |vpiName:cce_pc_width_p |vpiFullName:work@bp_me_nonsynth_lce_tracer.cce_pc_width_p |vpiParameter: \_parameter: (work@bp_me_nonsynth_lce_tracer.num_cce_instr_ram_els_p), line:5772:16, endln:5772:39 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiLocalParam:1 |vpiName:num_cce_instr_ram_els_p |vpiFullName:work@bp_me_nonsynth_lce_tracer.num_cce_instr_ram_els_p |vpiParameter: \_parameter: (work@bp_me_nonsynth_lce_tracer.cce_way_groups_p), line:5773:16, endln:5773:32 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiLocalParam:1 |vpiName:cce_way_groups_p |vpiFullName:work@bp_me_nonsynth_lce_tracer.cce_way_groups_p |vpiParameter: \_parameter: (work@bp_me_nonsynth_lce_tracer.cce_instr_width_p), line:5774:16, endln:5774:33 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |UINT:34 |vpiTypespec: \_int_typespec: @@ -71516,105 +71516,105 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@bp_me_nonsynth_lce_tracer.cce_ucode_p), line:5775:16, endln:5775:27 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiLocalParam:1 |vpiName:cce_ucode_p |vpiFullName:work@bp_me_nonsynth_lce_tracer.cce_ucode_p |vpiParameter: \_parameter: (work@bp_me_nonsynth_lce_tracer.l2_en_p), line:5777:16, endln:5777:23 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiLocalParam:1 |vpiName:l2_en_p |vpiFullName:work@bp_me_nonsynth_lce_tracer.l2_en_p |vpiParameter: \_parameter: (work@bp_me_nonsynth_lce_tracer.l2_sets_p), line:5778:16, endln:5778:25 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiLocalParam:1 |vpiName:l2_sets_p |vpiFullName:work@bp_me_nonsynth_lce_tracer.l2_sets_p |vpiParameter: \_parameter: (work@bp_me_nonsynth_lce_tracer.l2_assoc_p), line:5779:16, endln:5779:26 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiLocalParam:1 |vpiName:l2_assoc_p |vpiFullName:work@bp_me_nonsynth_lce_tracer.l2_assoc_p |vpiParameter: \_parameter: (work@bp_me_nonsynth_lce_tracer.l2_outstanding_reqs_p), line:5780:16, endln:5780:37 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiLocalParam:1 |vpiName:l2_outstanding_reqs_p |vpiFullName:work@bp_me_nonsynth_lce_tracer.l2_outstanding_reqs_p |vpiParameter: \_parameter: (work@bp_me_nonsynth_lce_tracer.fe_queue_fifo_els_p), line:5782:16, endln:5782:35 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiLocalParam:1 |vpiName:fe_queue_fifo_els_p |vpiFullName:work@bp_me_nonsynth_lce_tracer.fe_queue_fifo_els_p |vpiParameter: \_parameter: (work@bp_me_nonsynth_lce_tracer.fe_cmd_fifo_els_p), line:5783:16, endln:5783:33 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiLocalParam:1 |vpiName:fe_cmd_fifo_els_p |vpiFullName:work@bp_me_nonsynth_lce_tracer.fe_cmd_fifo_els_p |vpiParameter: \_parameter: (work@bp_me_nonsynth_lce_tracer.async_coh_clk_p), line:5785:16, endln:5785:31 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiLocalParam:1 |vpiName:async_coh_clk_p |vpiFullName:work@bp_me_nonsynth_lce_tracer.async_coh_clk_p |vpiParameter: \_parameter: (work@bp_me_nonsynth_lce_tracer.coh_noc_max_credits_p), line:5786:16, endln:5786:37 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiLocalParam:1 |vpiName:coh_noc_max_credits_p |vpiFullName:work@bp_me_nonsynth_lce_tracer.coh_noc_max_credits_p |vpiParameter: \_parameter: (work@bp_me_nonsynth_lce_tracer.coh_noc_flit_width_p), line:5787:16, endln:5787:36 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiLocalParam:1 |vpiName:coh_noc_flit_width_p |vpiFullName:work@bp_me_nonsynth_lce_tracer.coh_noc_flit_width_p |vpiParameter: \_parameter: (work@bp_me_nonsynth_lce_tracer.coh_noc_cid_width_p), line:5788:16, endln:5788:35 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiLocalParam:1 |vpiName:coh_noc_cid_width_p |vpiFullName:work@bp_me_nonsynth_lce_tracer.coh_noc_cid_width_p |vpiParameter: \_parameter: (work@bp_me_nonsynth_lce_tracer.coh_noc_len_width_p), line:5789:16, endln:5789:35 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiLocalParam:1 |vpiName:coh_noc_len_width_p |vpiFullName:work@bp_me_nonsynth_lce_tracer.coh_noc_len_width_p |vpiParameter: \_parameter: (work@bp_me_nonsynth_lce_tracer.coh_noc_y_cord_width_p), line:5790:16, endln:5790:38 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiLocalParam:1 |vpiName:coh_noc_y_cord_width_p |vpiFullName:work@bp_me_nonsynth_lce_tracer.coh_noc_y_cord_width_p |vpiParameter: \_parameter: (work@bp_me_nonsynth_lce_tracer.coh_noc_x_cord_width_p), line:5791:16, endln:5791:38 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiLocalParam:1 |vpiName:coh_noc_x_cord_width_p |vpiFullName:work@bp_me_nonsynth_lce_tracer.coh_noc_x_cord_width_p |vpiParameter: \_parameter: (work@bp_me_nonsynth_lce_tracer.coh_noc_dims_p), line:5792:16, endln:5792:30 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |UINT:2 |vpiTypespec: \_int_typespec: @@ -71624,14 +71624,14 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@bp_me_nonsynth_lce_tracer.coh_noc_dirs_p), line:5793:16, endln:5793:30 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiLocalParam:1 |vpiName:coh_noc_dirs_p |vpiFullName:work@bp_me_nonsynth_lce_tracer.coh_noc_dirs_p |vpiParameter: \_parameter: (work@bp_me_nonsynth_lce_tracer.coh_noc_trans_p), line:5794:16, endln:5794:31 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |UINT:0 |vpiTypespec: \_int_typespec: @@ -71641,7 +71641,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@bp_me_nonsynth_lce_tracer.coh_noc_cord_markers_pos_p), line:5795:20, endln:5795:46 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiSize:1 |vpiTypespec: \_array_typespec: @@ -71677,56 +71677,56 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@bp_me_nonsynth_lce_tracer.coh_noc_cord_width_p), line:5798:16, endln:5798:36 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiLocalParam:1 |vpiName:coh_noc_cord_width_p |vpiFullName:work@bp_me_nonsynth_lce_tracer.coh_noc_cord_width_p |vpiParameter: \_parameter: (work@bp_me_nonsynth_lce_tracer.async_mem_clk_p), line:5800:16, endln:5800:31 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiLocalParam:1 |vpiName:async_mem_clk_p |vpiFullName:work@bp_me_nonsynth_lce_tracer.async_mem_clk_p |vpiParameter: \_parameter: (work@bp_me_nonsynth_lce_tracer.mem_noc_max_credits_p), line:5801:16, endln:5801:37 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiLocalParam:1 |vpiName:mem_noc_max_credits_p |vpiFullName:work@bp_me_nonsynth_lce_tracer.mem_noc_max_credits_p |vpiParameter: \_parameter: (work@bp_me_nonsynth_lce_tracer.mem_noc_flit_width_p), line:5802:16, endln:5802:36 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiLocalParam:1 |vpiName:mem_noc_flit_width_p |vpiFullName:work@bp_me_nonsynth_lce_tracer.mem_noc_flit_width_p |vpiParameter: \_parameter: (work@bp_me_nonsynth_lce_tracer.mem_noc_cid_width_p), line:5803:16, endln:5803:35 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiLocalParam:1 |vpiName:mem_noc_cid_width_p |vpiFullName:work@bp_me_nonsynth_lce_tracer.mem_noc_cid_width_p |vpiParameter: \_parameter: (work@bp_me_nonsynth_lce_tracer.mem_noc_len_width_p), line:5804:16, endln:5804:35 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiLocalParam:1 |vpiName:mem_noc_len_width_p |vpiFullName:work@bp_me_nonsynth_lce_tracer.mem_noc_len_width_p |vpiParameter: \_parameter: (work@bp_me_nonsynth_lce_tracer.mem_noc_y_cord_width_p), line:5805:16, endln:5805:38 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiLocalParam:1 |vpiName:mem_noc_y_cord_width_p |vpiFullName:work@bp_me_nonsynth_lce_tracer.mem_noc_y_cord_width_p |vpiParameter: \_parameter: (work@bp_me_nonsynth_lce_tracer.mem_noc_x_cord_width_p), line:5806:16, endln:5806:38 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |UINT:0 |vpiTypespec: \_int_typespec: @@ -71736,7 +71736,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@bp_me_nonsynth_lce_tracer.mem_noc_dims_p), line:5807:16, endln:5807:30 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |UINT:1 |vpiTypespec: \_int_typespec: @@ -71746,7 +71746,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@bp_me_nonsynth_lce_tracer.mem_noc_cord_dims_p), line:5808:16, endln:5808:35 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |UINT:2 |vpiTypespec: \_int_typespec: @@ -71756,14 +71756,14 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@bp_me_nonsynth_lce_tracer.mem_noc_dirs_p), line:5809:16, endln:5809:30 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiLocalParam:1 |vpiName:mem_noc_dirs_p |vpiFullName:work@bp_me_nonsynth_lce_tracer.mem_noc_dirs_p |vpiParameter: \_parameter: (work@bp_me_nonsynth_lce_tracer.mem_noc_trans_p), line:5810:16, endln:5810:31 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |UINT:1 |vpiTypespec: \_int_typespec: @@ -71773,7 +71773,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@bp_me_nonsynth_lce_tracer.mem_noc_cord_markers_pos_p), line:5811:20, endln:5811:46 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiSize:1 |vpiTypespec: \_array_typespec: @@ -71809,56 +71809,56 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@bp_me_nonsynth_lce_tracer.mem_noc_cord_width_p), line:5814:16, endln:5814:36 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiLocalParam:1 |vpiName:mem_noc_cord_width_p |vpiFullName:work@bp_me_nonsynth_lce_tracer.mem_noc_cord_width_p |vpiParameter: \_parameter: (work@bp_me_nonsynth_lce_tracer.async_io_clk_p), line:5816:16, endln:5816:30 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiLocalParam:1 |vpiName:async_io_clk_p |vpiFullName:work@bp_me_nonsynth_lce_tracer.async_io_clk_p |vpiParameter: \_parameter: (work@bp_me_nonsynth_lce_tracer.io_noc_max_credits_p), line:5817:16, endln:5817:36 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiLocalParam:1 |vpiName:io_noc_max_credits_p |vpiFullName:work@bp_me_nonsynth_lce_tracer.io_noc_max_credits_p |vpiParameter: \_parameter: (work@bp_me_nonsynth_lce_tracer.io_noc_did_width_p), line:5818:16, endln:5818:34 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiLocalParam:1 |vpiName:io_noc_did_width_p |vpiFullName:work@bp_me_nonsynth_lce_tracer.io_noc_did_width_p |vpiParameter: \_parameter: (work@bp_me_nonsynth_lce_tracer.io_noc_flit_width_p), line:5819:16, endln:5819:35 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiLocalParam:1 |vpiName:io_noc_flit_width_p |vpiFullName:work@bp_me_nonsynth_lce_tracer.io_noc_flit_width_p |vpiParameter: \_parameter: (work@bp_me_nonsynth_lce_tracer.io_noc_cid_width_p), line:5820:16, endln:5820:34 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiLocalParam:1 |vpiName:io_noc_cid_width_p |vpiFullName:work@bp_me_nonsynth_lce_tracer.io_noc_cid_width_p |vpiParameter: \_parameter: (work@bp_me_nonsynth_lce_tracer.io_noc_len_width_p), line:5821:16, endln:5821:34 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiLocalParam:1 |vpiName:io_noc_len_width_p |vpiFullName:work@bp_me_nonsynth_lce_tracer.io_noc_len_width_p |vpiParameter: \_parameter: (work@bp_me_nonsynth_lce_tracer.io_noc_y_cord_width_p), line:5822:16, endln:5822:37 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |UINT:0 |vpiTypespec: \_int_typespec: @@ -71868,14 +71868,14 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@bp_me_nonsynth_lce_tracer.io_noc_x_cord_width_p), line:5823:16, endln:5823:37 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiLocalParam:1 |vpiName:io_noc_x_cord_width_p |vpiFullName:work@bp_me_nonsynth_lce_tracer.io_noc_x_cord_width_p |vpiParameter: \_parameter: (work@bp_me_nonsynth_lce_tracer.io_noc_dims_p), line:5824:16, endln:5824:29 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |UINT:1 |vpiTypespec: \_int_typespec: @@ -71885,7 +71885,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@bp_me_nonsynth_lce_tracer.io_noc_cord_dims_p), line:5825:16, endln:5825:34 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |UINT:2 |vpiTypespec: \_int_typespec: @@ -71895,14 +71895,14 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@bp_me_nonsynth_lce_tracer.io_noc_dirs_p), line:5826:16, endln:5826:29 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiLocalParam:1 |vpiName:io_noc_dirs_p |vpiFullName:work@bp_me_nonsynth_lce_tracer.io_noc_dirs_p |vpiParameter: \_parameter: (work@bp_me_nonsynth_lce_tracer.io_noc_trans_p), line:5827:16, endln:5827:30 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |UINT:0 |vpiTypespec: \_int_typespec: @@ -71912,7 +71912,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@bp_me_nonsynth_lce_tracer.io_noc_cord_markers_pos_p), line:5828:20, endln:5828:45 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiSize:1 |vpiTypespec: \_array_typespec: @@ -71948,14 +71948,14 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@bp_me_nonsynth_lce_tracer.io_noc_cord_width_p), line:5831:16, endln:5831:35 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiLocalParam:1 |vpiName:io_noc_cord_width_p |vpiFullName:work@bp_me_nonsynth_lce_tracer.io_noc_cord_width_p |vpiParameter: \_parameter: (work@bp_me_nonsynth_lce_tracer.dword_width_p), line:5833:16, endln:5833:29 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |UINT:64 |vpiTypespec: \_int_typespec: @@ -71965,7 +71965,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@bp_me_nonsynth_lce_tracer.word_width_p), line:5834:16, endln:5834:28 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |UINT:32 |vpiTypespec: \_int_typespec: @@ -71975,7 +71975,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@bp_me_nonsynth_lce_tracer.instr_width_p), line:5835:16, endln:5835:29 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |UINT:32 |vpiTypespec: \_int_typespec: @@ -71985,7 +71985,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@bp_me_nonsynth_lce_tracer.csr_addr_width_p), line:5836:16, endln:5836:32 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |UINT:12 |vpiTypespec: \_int_typespec: @@ -71995,7 +71995,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@bp_me_nonsynth_lce_tracer.reg_addr_width_p), line:5837:16, endln:5837:32 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |UINT:5 |vpiTypespec: \_int_typespec: @@ -72005,7 +72005,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@bp_me_nonsynth_lce_tracer.page_offset_width_p), line:5838:16, endln:5838:35 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |UINT:12 |vpiTypespec: \_int_typespec: @@ -72015,21 +72015,21 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@bp_me_nonsynth_lce_tracer.vtag_width_p), line:5840:16, endln:5840:28 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiLocalParam:1 |vpiName:vtag_width_p |vpiFullName:work@bp_me_nonsynth_lce_tracer.vtag_width_p |vpiParameter: \_parameter: (work@bp_me_nonsynth_lce_tracer.ptag_width_p), line:5841:16, endln:5841:28 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiLocalParam:1 |vpiName:ptag_width_p |vpiFullName:work@bp_me_nonsynth_lce_tracer.ptag_width_p |vpiParameter: \_parameter: (work@bp_me_nonsynth_lce_tracer.sets_p), line:5844:17, endln:5844:23 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |STRING:inv |vpiTypespec: \_string_typespec: @@ -72038,7 +72038,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@bp_me_nonsynth_lce_tracer.assoc_p), line:5845:17, endln:5845:24 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |STRING:inv |vpiTypespec: \_string_typespec: @@ -72047,7 +72047,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@bp_me_nonsynth_lce_tracer.block_width_p), line:5846:17, endln:5846:30 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |STRING:inv |vpiTypespec: \_string_typespec: @@ -72056,7 +72056,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@bp_me_nonsynth_lce_tracer.lce_trace_file_p), line:5848:18, endln:5848:34 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |STRING:lce |vpiTypespec: \_string_typespec: @@ -72066,119 +72066,119 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@bp_me_nonsynth_lce_tracer.block_size_in_bytes_lp), line:5850:18, endln:5850:40 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiLocalParam:1 |vpiName:block_size_in_bytes_lp |vpiFullName:work@bp_me_nonsynth_lce_tracer.block_size_in_bytes_lp |vpiParameter: \_parameter: (work@bp_me_nonsynth_lce_tracer.block_offset_bits_lp), line:5852:18, endln:5852:38 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiLocalParam:1 |vpiName:block_offset_bits_lp |vpiFullName:work@bp_me_nonsynth_lce_tracer.block_offset_bits_lp |vpiParameter: \_parameter: (work@bp_me_nonsynth_lce_tracer.lg_sets_lp), line:5854:18, endln:5854:28 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiLocalParam:1 |vpiName:lg_sets_lp |vpiFullName:work@bp_me_nonsynth_lce_tracer.lg_sets_lp |vpiParameter: \_parameter: (work@bp_me_nonsynth_lce_tracer.lg_assoc_lp), line:5855:18, endln:5855:29 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiLocalParam:1 |vpiName:lg_assoc_lp |vpiFullName:work@bp_me_nonsynth_lce_tracer.lg_assoc_lp |vpiParameter: \_parameter: (work@bp_me_nonsynth_lce_tracer.ptag_width_lp), line:5857:18, endln:5857:31 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiLocalParam:1 |vpiName:ptag_width_lp |vpiFullName:work@bp_me_nonsynth_lce_tracer.ptag_width_lp |vpiParameter: \_parameter: (work@bp_me_nonsynth_lce_tracer.lg_num_cce_lp), line:5859:18, endln:5859:31 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiLocalParam:1 |vpiName:lg_num_cce_lp |vpiFullName:work@bp_me_nonsynth_lce_tracer.lg_num_cce_lp |vpiParameter: \_parameter: (work@bp_me_nonsynth_lce_tracer.lce_req_data_width_lp), line:5861:18, endln:5861:39 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiLocalParam:1 |vpiName:lce_req_data_width_lp |vpiFullName:work@bp_me_nonsynth_lce_tracer.lce_req_data_width_lp |vpiParameter: \_parameter: (work@bp_me_nonsynth_lce_tracer.lce_req_payload_width_lp), line:5865:16, endln:5865:40 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiLocalParam:1 |vpiName:lce_req_payload_width_lp |vpiFullName:work@bp_me_nonsynth_lce_tracer.lce_req_payload_width_lp |vpiParameter: \_parameter: (work@bp_me_nonsynth_lce_tracer.lce_cmd_payload_width_lp), line:5868:16, endln:5868:40 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiLocalParam:1 |vpiName:lce_cmd_payload_width_lp |vpiFullName:work@bp_me_nonsynth_lce_tracer.lce_cmd_payload_width_lp |vpiParameter: \_parameter: (work@bp_me_nonsynth_lce_tracer.lce_resp_payload_width_lp), line:5871:16, endln:5871:41 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiLocalParam:1 |vpiName:lce_resp_payload_width_lp |vpiFullName:work@bp_me_nonsynth_lce_tracer.lce_resp_payload_width_lp |vpiParameter: \_parameter: (work@bp_me_nonsynth_lce_tracer.lce_req_msg_header_width_lp), line:5876:16, endln:5876:43 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiLocalParam:1 |vpiName:lce_req_msg_header_width_lp |vpiFullName:work@bp_me_nonsynth_lce_tracer.lce_req_msg_header_width_lp |vpiParameter: \_parameter: (work@bp_me_nonsynth_lce_tracer.lce_cmd_msg_header_width_lp), line:5881:16, endln:5881:43 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiLocalParam:1 |vpiName:lce_cmd_msg_header_width_lp |vpiFullName:work@bp_me_nonsynth_lce_tracer.lce_cmd_msg_header_width_lp |vpiParameter: \_parameter: (work@bp_me_nonsynth_lce_tracer.lce_resp_msg_header_width_lp), line:5886:16, endln:5886:44 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiLocalParam:1 |vpiName:lce_resp_msg_header_width_lp |vpiFullName:work@bp_me_nonsynth_lce_tracer.lce_resp_msg_header_width_lp |vpiParameter: \_parameter: (work@bp_me_nonsynth_lce_tracer.lce_req_msg_width_lp), line:5891:16, endln:5891:36 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiLocalParam:1 |vpiName:lce_req_msg_width_lp |vpiFullName:work@bp_me_nonsynth_lce_tracer.lce_req_msg_width_lp |vpiParameter: \_parameter: (work@bp_me_nonsynth_lce_tracer.lce_cmd_msg_width_lp), line:5898:16, endln:5898:36 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiLocalParam:1 |vpiName:lce_cmd_msg_width_lp |vpiFullName:work@bp_me_nonsynth_lce_tracer.lce_cmd_msg_width_lp |vpiParameter: \_parameter: (work@bp_me_nonsynth_lce_tracer.lce_resp_msg_width_lp), line:5905:16, endln:5905:37 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiLocalParam:1 |vpiName:lce_resp_msg_width_lp |vpiFullName:work@bp_me_nonsynth_lce_tracer.lce_resp_msg_width_lp |vpiParamAssign: \_param_assign: , line:78:12, endln:78:32 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiRhs: \_constant: , line:78:31, endln:78:32 |vpiParent: @@ -72207,7 +72207,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:79:12, endln:79:32 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiRhs: \_constant: , line:79:31, endln:79:32 |vpiParent: @@ -72236,7 +72236,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:80:12, endln:80:32 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiRhs: \_constant: , line:80:31, endln:80:32 |vpiParent: @@ -72265,7 +72265,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:899:14, endln:899:36 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiRhs: \_constant: , line:899:34, endln:899:36 |vpiParent: @@ -72294,7 +72294,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:900:14, endln:900:36 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiRhs: \_constant: , line:900:34, endln:900:36 |vpiParent: @@ -72323,7 +72323,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:902:13, endln:902:44 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiRhs: \_constant: , line:902:43, endln:902:44 |vpiParent: @@ -72351,7 +72351,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:903:13, endln:903:38 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiRhs: \_constant: , line:903:36, endln:903:38 |vpiParent: @@ -72379,7 +72379,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:904:13, endln:904:40 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiRhs: \_constant: , line:904:38, endln:904:40 |vpiParent: @@ -72407,7 +72407,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:905:13, endln:905:40 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiRhs: \_constant: , line:905:38, endln:905:40 |vpiParent: @@ -72435,7 +72435,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:906:13, endln:906:38 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiRhs: \_constant: , line:906:36, endln:906:38 |vpiParent: @@ -72463,7 +72463,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:907:13, endln:907:44 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiRhs: \_constant: , line:907:40, endln:907:44 |vpiParent: @@ -72491,7 +72491,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:908:13, endln:908:114 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiRhs: \_constant: , line:908:41, endln:908:72 |vpiParent: @@ -72519,7 +72519,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:910:13, endln:910:41 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiRhs: \_constant: , line:910:40, endln:910:41 |vpiParent: @@ -72547,7 +72547,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:911:13, endln:911:40 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiRhs: \_constant: , line:911:39, endln:911:40 |vpiParent: @@ -72575,7 +72575,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:913:14, endln:913:55 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiRhs: \_constant: , line:913:42, endln:913:55 |vpiParent: @@ -72632,7 +72632,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:915:14, endln:915:55 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiRhs: \_constant: , line:915:42, endln:915:55 |vpiParent: @@ -72689,7 +72689,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:916:14, endln:916:55 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiRhs: \_constant: , line:916:42, endln:916:55 |vpiParent: @@ -72746,7 +72746,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:917:14, endln:917:55 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiRhs: \_constant: , line:917:42, endln:917:55 |vpiParent: @@ -72803,7 +72803,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:918:14, endln:918:55 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiRhs: \_constant: , line:918:42, endln:918:55 |vpiParent: @@ -72860,7 +72860,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:920:14, endln:920:55 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiRhs: \_constant: , line:920:42, endln:920:55 |vpiParent: @@ -72917,7 +72917,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:921:14, endln:921:55 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiRhs: \_constant: , line:921:42, endln:921:55 |vpiParent: @@ -72974,7 +72974,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:922:14, endln:922:55 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiRhs: \_constant: , line:922:42, endln:922:55 |vpiParent: @@ -73031,7 +73031,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:923:14, endln:923:55 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiRhs: \_constant: , line:923:42, endln:923:55 |vpiParent: @@ -73088,7 +73088,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:2192:14, endln:2192:31 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiRhs: \_constant: , line:2192:28, endln:2192:31 |vpiParent: @@ -73117,7 +73117,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:2193:14, endln:2193:71 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiRhs: \_constant: , line:2193:30, endln:2193:45 |vpiParent: @@ -73146,7 +73146,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:2195:30, endln:2196:22 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiRhs: \_operation: , line:2196:5, endln:2196:22 |vpiParent: @@ -73868,7 +73868,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:2198:30, endln:2247:8 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiRhs: \_operation: , line:2199:5, endln:2247:8 |vpiParent: @@ -75253,7 +75253,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:2249:30, endln:2298:8 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiRhs: \_operation: , line:2250:5, endln:2298:8 |vpiParent: @@ -76638,7 +76638,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:2300:30, endln:2349:8 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiRhs: \_operation: , line:2301:5, endln:2349:8 |vpiParent: @@ -78023,7 +78023,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:2351:30, endln:2400:8 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiRhs: \_operation: , line:2352:5, endln:2400:8 |vpiParent: @@ -79408,7 +79408,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:2402:30, endln:2451:8 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiRhs: \_operation: , line:2403:5, endln:2451:8 |vpiParent: @@ -80793,7 +80793,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:2453:30, endln:2502:8 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiRhs: \_operation: , line:2454:5, endln:2502:8 |vpiParent: @@ -82178,7 +82178,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:2516:44, endln:2525:4 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiRhs: \_operation: , line:2517:3, endln:2525:4 |vpiParent: @@ -82951,7 +82951,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:5680:27, endln:5680:62 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiRhs: \_ref_obj: (e_bp_unicore_half_cfg), line:5680:41, endln:5680:62 |vpiName:e_bp_unicore_half_cfg @@ -82960,7 +82960,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:5682:32, endln:5682:72 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiRhs: \_bit_select: (all_cfgs_gp), line:5682:48, endln:5682:72 |vpiParent: @@ -82978,7 +82978,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:5684:16, endln:5684:53 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiRhs: \_hier_path: (proc_param_lp.multicore), line:5684:30, endln:5684:53 |vpiName:proc_param_lp.multicore @@ -82995,7 +82995,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:5686:16, endln:5686:52 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiRhs: \_hier_path: (proc_param_lp.cc_x_dim), line:5686:30, endln:5686:52 |vpiName:proc_param_lp.cc_x_dim @@ -83012,7 +83012,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:5687:16, endln:5687:52 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiRhs: \_hier_path: (proc_param_lp.cc_y_dim), line:5687:30, endln:5687:52 |vpiName:proc_param_lp.cc_y_dim @@ -83029,7 +83029,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:5689:16, endln:5689:39 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiRhs: \_ref_obj: (cc_x_dim_p), line:5689:29, endln:5689:39 |vpiName:cc_x_dim_p @@ -83038,7 +83038,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:5690:16, endln:5690:51 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiRhs: \_hier_path: (proc_param_lp.ic_y_dim), line:5690:29, endln:5690:51 |vpiName:proc_param_lp.ic_y_dim @@ -83055,7 +83055,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:5691:16, endln:5691:39 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiRhs: \_ref_obj: (cc_x_dim_p), line:5691:29, endln:5691:39 |vpiName:cc_x_dim_p @@ -83064,7 +83064,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:5692:16, endln:5692:51 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiRhs: \_hier_path: (proc_param_lp.mc_y_dim), line:5692:29, endln:5692:51 |vpiName:proc_param_lp.mc_y_dim @@ -83081,7 +83081,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:5693:16, endln:5693:53 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiRhs: \_hier_path: (proc_param_lp.cac_x_dim), line:5693:30, endln:5693:53 |vpiName:proc_param_lp.cac_x_dim @@ -83098,7 +83098,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:5694:16, endln:5694:40 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiRhs: \_ref_obj: (cc_y_dim_p), line:5694:30, endln:5694:40 |vpiName:cc_y_dim_p @@ -83107,7 +83107,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:5695:16, endln:5695:53 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiRhs: \_hier_path: (proc_param_lp.sac_x_dim), line:5695:30, endln:5695:53 |vpiName:proc_param_lp.sac_x_dim @@ -83124,7 +83124,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:5696:16, endln:5696:40 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiRhs: \_ref_obj: (cc_y_dim_p), line:5696:30, endln:5696:40 |vpiName:cc_y_dim_p @@ -83133,7 +83133,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:5697:16, endln:5697:53 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiRhs: \_hier_path: (proc_param_lp.cacc_type), line:5697:30, endln:5697:53 |vpiName:proc_param_lp.cacc_type @@ -83150,7 +83150,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:5698:16, endln:5698:53 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiRhs: \_hier_path: (proc_param_lp.sacc_type), line:5698:30, endln:5698:53 |vpiName:proc_param_lp.sacc_type @@ -83167,7 +83167,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:5700:16, endln:5700:53 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiRhs: \_operation: , line:5700:30, endln:5700:53 |vpiOpType:25 @@ -83186,7 +83186,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:5701:16, endln:5701:53 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiRhs: \_operation: , line:5701:30, endln:5701:53 |vpiOpType:25 @@ -83205,7 +83205,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:5702:16, endln:5702:53 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiRhs: \_operation: , line:5702:30, endln:5702:53 |vpiOpType:25 @@ -83224,7 +83224,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:5703:16, endln:5703:55 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiRhs: \_operation: , line:5703:30, endln:5703:55 |vpiOpType:25 @@ -83243,7 +83243,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:5704:16, endln:5704:55 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiRhs: \_operation: , line:5704:30, endln:5704:55 |vpiOpType:25 @@ -83262,7 +83262,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:5706:16, endln:5706:49 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiRhs: \_hier_path: (proc_param_lp.num_cce), line:5706:28, endln:5706:49 |vpiName:proc_param_lp.num_cce @@ -83279,7 +83279,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:5707:16, endln:5707:49 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiRhs: \_hier_path: (proc_param_lp.num_lce), line:5707:28, endln:5707:49 |vpiName:proc_param_lp.num_lce @@ -83296,7 +83296,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:5709:16, endln:5709:103 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiRhs: \_operation: , line:5709:36, endln:5709:102 |vpiOpType:32 @@ -83361,7 +83361,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:5710:16, endln:5710:127 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiRhs: \_operation: , line:5710:36, endln:5710:126 |vpiOpType:32 @@ -83530,7 +83530,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:5711:16, endln:5711:127 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiRhs: \_operation: , line:5711:36, endln:5711:126 |vpiOpType:32 @@ -83699,7 +83699,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:5713:16, endln:5713:57 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiRhs: \_hier_path: (proc_param_lp.vaddr_width), line:5713:32, endln:5713:57 |vpiName:proc_param_lp.vaddr_width @@ -83716,7 +83716,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:5714:16, endln:5714:57 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiRhs: \_hier_path: (proc_param_lp.paddr_width), line:5714:32, endln:5714:57 |vpiName:proc_param_lp.paddr_width @@ -83733,7 +83733,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:5715:16, endln:5715:56 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiRhs: \_hier_path: (proc_param_lp.asid_width), line:5715:32, endln:5715:56 |vpiName:proc_param_lp.asid_width @@ -83750,7 +83750,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:5717:16, endln:5717:55 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiRhs: \_hier_path: (proc_param_lp.boot_pc), line:5717:34, endln:5717:55 |vpiName:proc_param_lp.boot_pc @@ -83767,7 +83767,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:5718:16, endln:5718:61 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiRhs: \_hier_path: (proc_param_lp.boot_in_debug), line:5718:34, endln:5718:61 |vpiName:proc_param_lp.boot_in_debug @@ -83784,7 +83784,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:5720:16, endln:5720:85 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiRhs: \_hier_path: (proc_param_lp.branch_metadata_fwd_width), line:5720:46, endln:5720:85 |vpiName:proc_param_lp.branch_metadata_fwd_width @@ -83801,7 +83801,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:5721:16, endln:5721:73 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiRhs: \_hier_path: (proc_param_lp.btb_tag_width), line:5721:46, endln:5721:73 |vpiName:proc_param_lp.btb_tag_width @@ -83818,7 +83818,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:5722:16, endln:5722:73 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiRhs: \_hier_path: (proc_param_lp.btb_idx_width), line:5722:46, endln:5722:73 |vpiName:proc_param_lp.btb_idx_width @@ -83835,7 +83835,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:5723:16, endln:5723:73 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiRhs: \_hier_path: (proc_param_lp.bht_idx_width), line:5723:46, endln:5723:73 |vpiName:proc_param_lp.bht_idx_width @@ -83852,7 +83852,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:5724:16, endln:5724:71 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiRhs: \_hier_path: (proc_param_lp.ghist_width), line:5724:46, endln:5724:71 |vpiName:proc_param_lp.ghist_width @@ -83869,7 +83869,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:5726:16, endln:5726:64 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiRhs: \_hier_path: (proc_param_lp.itlb_els), line:5726:42, endln:5726:64 |vpiName:proc_param_lp.itlb_els @@ -83886,7 +83886,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:5727:16, endln:5727:64 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiRhs: \_hier_path: (proc_param_lp.dtlb_els), line:5727:42, endln:5727:64 |vpiName:proc_param_lp.dtlb_els @@ -83903,7 +83903,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:5729:16, endln:5729:64 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiRhs: \_hier_path: (proc_param_lp.lr_sc), line:5729:45, endln:5729:64 |vpiName:proc_param_lp.lr_sc @@ -83920,7 +83920,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:5730:16, endln:5730:67 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiRhs: \_hier_path: (proc_param_lp.amo_swap), line:5730:45, endln:5730:67 |vpiName:proc_param_lp.amo_swap @@ -83937,7 +83937,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:5731:16, endln:5731:74 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiRhs: \_hier_path: (proc_param_lp.amo_fetch_logic), line:5731:45, endln:5731:74 |vpiName:proc_param_lp.amo_fetch_logic @@ -83954,7 +83954,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:5732:16, endln:5732:79 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiRhs: \_hier_path: (proc_param_lp.amo_fetch_arithmetic), line:5732:45, endln:5732:79 |vpiName:proc_param_lp.amo_fetch_arithmetic @@ -83971,7 +83971,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:5734:16, endln:5734:70 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiRhs: \_hier_path: (proc_param_lp.l1_coherent), line:5734:45, endln:5734:70 |vpiName:proc_param_lp.l1_coherent @@ -83988,7 +83988,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:5735:16, endln:5735:74 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiRhs: \_hier_path: (proc_param_lp.l1_writethrough), line:5735:45, endln:5735:74 |vpiName:proc_param_lp.l1_writethrough @@ -84005,7 +84005,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:5736:16, endln:5736:70 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiRhs: \_hier_path: (proc_param_lp.dcache_sets), line:5736:45, endln:5736:70 |vpiName:proc_param_lp.dcache_sets @@ -84022,7 +84022,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:5737:16, endln:5737:71 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiRhs: \_hier_path: (proc_param_lp.dcache_assoc), line:5737:45, endln:5737:71 |vpiName:proc_param_lp.dcache_assoc @@ -84039,7 +84039,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:5738:16, endln:5738:77 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiRhs: \_hier_path: (proc_param_lp.dcache_block_width), line:5738:45, endln:5738:77 |vpiName:proc_param_lp.dcache_block_width @@ -84056,7 +84056,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:5739:16, endln:5739:76 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiRhs: \_hier_path: (proc_param_lp.dcache_fill_width), line:5739:45, endln:5739:76 |vpiName:proc_param_lp.dcache_fill_width @@ -84073,7 +84073,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:5740:16, endln:5740:70 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiRhs: \_hier_path: (proc_param_lp.icache_sets), line:5740:45, endln:5740:70 |vpiName:proc_param_lp.icache_sets @@ -84090,7 +84090,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:5741:16, endln:5741:71 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiRhs: \_hier_path: (proc_param_lp.icache_assoc), line:5741:45, endln:5741:71 |vpiName:proc_param_lp.icache_assoc @@ -84107,7 +84107,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:5742:16, endln:5742:77 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiRhs: \_hier_path: (proc_param_lp.icache_block_width), line:5742:45, endln:5742:77 |vpiName:proc_param_lp.icache_block_width @@ -84124,7 +84124,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:5743:16, endln:5743:76 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiRhs: \_hier_path: (proc_param_lp.icache_fill_width), line:5743:45, endln:5743:76 |vpiName:proc_param_lp.icache_fill_width @@ -84141,7 +84141,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:5744:16, endln:5744:70 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiRhs: \_hier_path: (proc_param_lp.acache_sets), line:5744:45, endln:5744:70 |vpiName:proc_param_lp.acache_sets @@ -84158,7 +84158,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:5745:16, endln:5745:71 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiRhs: \_hier_path: (proc_param_lp.acache_assoc), line:5745:45, endln:5745:71 |vpiName:proc_param_lp.acache_assoc @@ -84175,7 +84175,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:5746:16, endln:5746:77 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiRhs: \_hier_path: (proc_param_lp.acache_block_width), line:5746:45, endln:5746:77 |vpiName:proc_param_lp.acache_block_width @@ -84192,7 +84192,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:5747:16, endln:5747:76 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiRhs: \_hier_path: (proc_param_lp.acache_fill_width), line:5747:45, endln:5747:76 |vpiName:proc_param_lp.acache_fill_width @@ -84209,7 +84209,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:5748:16, endln:5750:131 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiRhs: \_operation: , line:5748:46, endln:5750:130 |vpiOpType:32 @@ -84293,7 +84293,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:5752:16, endln:5752:94 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiRhs: \_operation: , line:5752:47, endln:5752:93 |vpiOpType:32 @@ -84338,7 +84338,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:5753:16, endln:5755:127 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiRhs: \_operation: , line:5753:46, endln:5755:126 |vpiOpType:32 @@ -84422,7 +84422,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:5757:16, endln:5757:92 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiRhs: \_operation: , line:5757:47, endln:5757:91 |vpiOpType:32 @@ -84467,7 +84467,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:5759:16, endln:5767:3 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiRhs: \_operation: , line:5759:47, endln:5767:2 |vpiOpType:32 @@ -84551,7 +84551,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:5771:16, endln:5771:71 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiRhs: \_hier_path: (proc_param_lp.cce_pc_width), line:5771:45, endln:5771:71 |vpiName:proc_param_lp.cce_pc_width @@ -84568,7 +84568,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:5772:16, endln:5772:62 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiRhs: \_operation: , line:5772:45, endln:5772:62 |vpiOpType:43 @@ -84590,7 +84590,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:5773:16, endln:5773:116 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiRhs: \_operation: , line:5773:46, endln:5773:115 |vpiOpType:32 @@ -84624,7 +84624,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:5774:16, endln:5774:47 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiRhs: \_constant: , line:5774:45, endln:5774:47 |vpiDecompile:34 @@ -84638,7 +84638,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:5775:16, endln:5775:68 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiRhs: \_hier_path: (proc_param_lp.cce_ucode), line:5775:45, endln:5775:68 |vpiName:proc_param_lp.cce_ucode @@ -84655,7 +84655,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:5777:16, endln:5777:48 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiRhs: \_hier_path: (proc_param_lp.l2_en), line:5777:29, endln:5777:48 |vpiName:proc_param_lp.l2_en @@ -84672,7 +84672,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:5778:16, endln:5778:50 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiRhs: \_hier_path: (proc_param_lp.l2_sets), line:5778:29, endln:5778:50 |vpiName:proc_param_lp.l2_sets @@ -84689,7 +84689,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:5779:16, endln:5779:51 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiRhs: \_hier_path: (proc_param_lp.l2_assoc), line:5779:29, endln:5779:51 |vpiName:proc_param_lp.l2_assoc @@ -84706,7 +84706,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:5780:16, endln:5780:73 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiRhs: \_hier_path: (proc_param_lp.l2_outstanding_reqs), line:5780:40, endln:5780:73 |vpiName:proc_param_lp.l2_outstanding_reqs @@ -84723,7 +84723,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:5782:16, endln:5782:69 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiRhs: \_hier_path: (proc_param_lp.fe_queue_fifo_els), line:5782:38, endln:5782:69 |vpiName:proc_param_lp.fe_queue_fifo_els @@ -84740,7 +84740,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:5783:16, endln:5783:67 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiRhs: \_hier_path: (proc_param_lp.fe_cmd_fifo_els), line:5783:38, endln:5783:67 |vpiName:proc_param_lp.fe_cmd_fifo_els @@ -84757,7 +84757,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:5785:16, endln:5785:68 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiRhs: \_hier_path: (proc_param_lp.async_coh_clk), line:5785:41, endln:5785:68 |vpiName:proc_param_lp.async_coh_clk @@ -84774,7 +84774,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:5786:16, endln:5786:74 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiRhs: \_hier_path: (proc_param_lp.coh_noc_max_credits), line:5786:41, endln:5786:74 |vpiName:proc_param_lp.coh_noc_max_credits @@ -84791,7 +84791,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:5787:16, endln:5787:73 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiRhs: \_hier_path: (proc_param_lp.coh_noc_flit_width), line:5787:41, endln:5787:73 |vpiName:proc_param_lp.coh_noc_flit_width @@ -84808,7 +84808,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:5788:16, endln:5788:72 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiRhs: \_hier_path: (proc_param_lp.coh_noc_cid_width), line:5788:41, endln:5788:72 |vpiName:proc_param_lp.coh_noc_cid_width @@ -84825,7 +84825,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:5789:16, endln:5789:72 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiRhs: \_hier_path: (proc_param_lp.coh_noc_len_width), line:5789:41, endln:5789:72 |vpiName:proc_param_lp.coh_noc_len_width @@ -84842,7 +84842,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:5790:16, endln:5790:136 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiRhs: \_operation: , line:5790:43, endln:5790:135 |vpiOpType:32 @@ -84953,7 +84953,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:5791:16, endln:5791:140 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiRhs: \_operation: , line:5791:43, endln:5791:139 |vpiOpType:32 @@ -85064,7 +85064,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:5792:16, endln:5792:42 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiRhs: \_constant: , line:5792:41, endln:5792:42 |vpiDecompile:2 @@ -85078,7 +85078,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:5793:16, endln:5793:61 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiRhs: \_operation: , line:5793:41, endln:5793:61 |vpiOpType:24 @@ -85113,7 +85113,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:5794:16, endln:5794:42 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiRhs: \_constant: , line:5794:41, endln:5794:42 |vpiDecompile:0 @@ -85127,7 +85127,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:5795:20, endln:5797:84 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiRhs: \_operation: , line:5795:67, endln:5797:84 |vpiOpType:32 @@ -85203,7 +85203,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:5798:16, endln:5798:83 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiRhs: \_bit_select: (coh_noc_cord_markers_pos_p), line:5798:41, endln:5798:83 |vpiParent: @@ -85221,7 +85221,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:5800:16, endln:5800:71 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiRhs: \_hier_path: (proc_param_lp.async_mem_clk), line:5800:44, endln:5800:71 |vpiName:proc_param_lp.async_mem_clk @@ -85238,7 +85238,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:5801:16, endln:5801:77 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiRhs: \_hier_path: (proc_param_lp.mem_noc_max_credits), line:5801:44, endln:5801:77 |vpiName:proc_param_lp.mem_noc_max_credits @@ -85255,7 +85255,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:5802:16, endln:5802:76 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiRhs: \_hier_path: (proc_param_lp.mem_noc_flit_width), line:5802:44, endln:5802:76 |vpiName:proc_param_lp.mem_noc_flit_width @@ -85272,7 +85272,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:5803:16, endln:5803:75 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiRhs: \_hier_path: (proc_param_lp.mem_noc_cid_width), line:5803:44, endln:5803:75 |vpiName:proc_param_lp.mem_noc_cid_width @@ -85289,7 +85289,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:5804:16, endln:5804:75 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiRhs: \_hier_path: (proc_param_lp.mem_noc_len_width), line:5804:44, endln:5804:75 |vpiName:proc_param_lp.mem_noc_len_width @@ -85306,7 +85306,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:5805:16, endln:5805:139 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiRhs: \_operation: , line:5805:46, endln:5805:138 |vpiOpType:32 @@ -85417,7 +85417,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:5806:16, endln:5806:45 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiRhs: \_constant: , line:5806:44, endln:5806:45 |vpiDecompile:0 @@ -85431,7 +85431,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:5807:16, endln:5807:45 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiRhs: \_constant: , line:5807:44, endln:5807:45 |vpiDecompile:1 @@ -85445,7 +85445,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:5808:16, endln:5808:45 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiRhs: \_constant: , line:5808:44, endln:5808:45 |vpiDecompile:2 @@ -85459,7 +85459,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:5809:16, endln:5809:64 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiRhs: \_operation: , line:5809:44, endln:5809:64 |vpiOpType:24 @@ -85494,7 +85494,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:5810:16, endln:5810:45 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiRhs: \_constant: , line:5810:44, endln:5810:45 |vpiDecompile:1 @@ -85508,7 +85508,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:5811:20, endln:5813:84 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiRhs: \_operation: , line:5811:72, endln:5813:84 |vpiOpType:32 @@ -85584,7 +85584,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:5814:16, endln:5814:86 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiRhs: \_bit_select: (mem_noc_cord_markers_pos_p), line:5814:44, endln:5814:86 |vpiParent: @@ -85602,7 +85602,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:5816:16, endln:5816:69 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiRhs: \_hier_path: (proc_param_lp.async_io_clk), line:5816:43, endln:5816:69 |vpiName:proc_param_lp.async_io_clk @@ -85619,7 +85619,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:5817:16, endln:5817:75 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiRhs: \_hier_path: (proc_param_lp.io_noc_max_credits), line:5817:43, endln:5817:75 |vpiName:proc_param_lp.io_noc_max_credits @@ -85636,7 +85636,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:5818:16, endln:5818:73 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiRhs: \_hier_path: (proc_param_lp.io_noc_did_width), line:5818:43, endln:5818:73 |vpiName:proc_param_lp.io_noc_did_width @@ -85653,7 +85653,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:5819:16, endln:5819:74 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiRhs: \_hier_path: (proc_param_lp.io_noc_flit_width), line:5819:43, endln:5819:74 |vpiName:proc_param_lp.io_noc_flit_width @@ -85670,7 +85670,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:5820:16, endln:5820:73 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiRhs: \_hier_path: (proc_param_lp.io_noc_cid_width), line:5820:43, endln:5820:73 |vpiName:proc_param_lp.io_noc_cid_width @@ -85687,7 +85687,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:5821:16, endln:5821:73 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiRhs: \_hier_path: (proc_param_lp.io_noc_len_width), line:5821:43, endln:5821:73 |vpiName:proc_param_lp.io_noc_len_width @@ -85704,7 +85704,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:5822:16, endln:5822:44 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiRhs: \_constant: , line:5822:43, endln:5822:44 |vpiDecompile:0 @@ -85718,7 +85718,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:5823:16, endln:5823:61 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiRhs: \_ref_obj: (io_noc_did_width_p), line:5823:43, endln:5823:61 |vpiName:io_noc_did_width_p @@ -85727,7 +85727,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:5824:16, endln:5824:44 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiRhs: \_constant: , line:5824:43, endln:5824:44 |vpiDecompile:1 @@ -85741,7 +85741,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:5825:16, endln:5825:44 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiRhs: \_constant: , line:5825:43, endln:5825:44 |vpiDecompile:2 @@ -85755,7 +85755,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:5826:16, endln:5826:67 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiRhs: \_operation: , line:5826:43, endln:5826:67 |vpiOpType:24 @@ -85790,7 +85790,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:5827:16, endln:5827:44 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiRhs: \_constant: , line:5827:43, endln:5827:44 |vpiDecompile:0 @@ -85804,7 +85804,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:5828:20, endln:5830:81 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiRhs: \_operation: , line:5828:70, endln:5830:81 |vpiOpType:32 @@ -85880,7 +85880,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:5831:16, endln:5831:83 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiRhs: \_bit_select: (io_noc_cord_markers_pos_p), line:5831:43, endln:5831:83 |vpiParent: @@ -85898,7 +85898,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:5833:16, endln:5833:40 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiRhs: \_constant: , line:5833:38, endln:5833:40 |vpiDecompile:64 @@ -85912,7 +85912,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:5834:16, endln:5834:40 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiRhs: \_constant: , line:5834:38, endln:5834:40 |vpiDecompile:32 @@ -85926,7 +85926,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:5835:16, endln:5835:40 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiRhs: \_constant: , line:5835:38, endln:5835:40 |vpiDecompile:32 @@ -85940,7 +85940,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:5836:16, endln:5836:40 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiRhs: \_constant: , line:5836:38, endln:5836:40 |vpiDecompile:12 @@ -85954,7 +85954,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:5837:16, endln:5837:39 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiRhs: \_constant: , line:5837:38, endln:5837:39 |vpiDecompile:5 @@ -85968,7 +85968,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:5838:16, endln:5838:40 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiRhs: \_constant: , line:5838:38, endln:5838:40 |vpiDecompile:12 @@ -85982,7 +85982,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:5840:16, endln:5840:79 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiRhs: \_operation: , line:5840:32, endln:5840:79 |vpiOpType:11 @@ -86009,7 +86009,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:5841:16, endln:5841:79 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiRhs: \_operation: , line:5841:32, endln:5841:79 |vpiOpType:11 @@ -86036,7 +86036,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:5844:17, endln:5844:31 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiRhs: \_constant: , line:5844:26, endln:5844:31 |vpiDecompile:inv @@ -86050,7 +86050,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:5845:17, endln:5845:32 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiRhs: \_constant: , line:5845:27, endln:5845:32 |vpiDecompile:inv @@ -86064,7 +86064,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:5846:17, endln:5846:38 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiRhs: \_constant: , line:5846:33, endln:5846:38 |vpiDecompile:inv @@ -86078,7 +86078,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:5848:18, endln:5848:42 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiRhs: \_constant: , line:5848:37, endln:5848:42 |vpiDecompile:lce @@ -86092,7 +86092,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:5850:18, endln:5850:60 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiRhs: \_operation: , line:5850:42, endln:5850:59 |vpiOpType:12 @@ -86114,7 +86114,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:5852:18, endln:5852:110 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiRhs: \_operation: , line:5852:41, endln:5852:109 |vpiOpType:32 @@ -86159,7 +86159,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:5854:18, endln:5854:68 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiRhs: \_operation: , line:5854:31, endln:5854:67 |vpiOpType:32 @@ -86204,7 +86204,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:5855:18, endln:5855:71 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiRhs: \_operation: , line:5855:32, endln:5855:70 |vpiOpType:32 @@ -86249,7 +86249,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:5857:18, endln:5857:79 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiRhs: \_operation: , line:5857:33, endln:5857:78 |vpiOpType:11 @@ -86278,7 +86278,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:5859:18, endln:5859:77 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiRhs: \_operation: , line:5859:34, endln:5859:76 |vpiOpType:32 @@ -86323,7 +86323,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:5861:18, endln:5861:55 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiRhs: \_ref_obj: (dword_width_p), line:5861:42, endln:5861:55 |vpiName:dword_width_p @@ -86332,7 +86332,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:5865:16, endln:5866:117 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiRhs: \_operation: , line:5866:4, endln:5866:116 |vpiOpType:24 @@ -86412,7 +86412,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:5868:16, endln:5869:119 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiRhs: \_operation: , line:5869:4, endln:5869:118 |vpiOpType:24 @@ -86529,7 +86529,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:5871:16, endln:5872:34 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiRhs: \_operation: , line:5872:4, endln:5872:33 |vpiOpType:24 @@ -86548,7 +86548,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:5876:16, endln:5877:96 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiRhs: \_operation: , line:5877:4, endln:5877:95 |vpiOpType:24 @@ -86597,7 +86597,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:5881:16, endln:5882:96 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiRhs: \_operation: , line:5882:4, endln:5882:95 |vpiOpType:24 @@ -86646,7 +86646,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:5886:16, endln:5887:97 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiRhs: \_operation: , line:5887:4, endln:5887:96 |vpiOpType:24 @@ -86695,7 +86695,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:5891:16, endln:5894:20 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiRhs: \_operation: , line:5893:3, endln:5894:19 |vpiOpType:24 @@ -86754,7 +86754,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:5898:16, endln:5901:20 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiRhs: \_operation: , line:5900:3, endln:5901:19 |vpiOpType:24 @@ -86813,7 +86813,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:5905:16, endln:5908:20 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiRhs: \_operation: , line:5907:3, endln:5908:19 |vpiOpType:24 @@ -86872,10 +86872,10 @@ design: (work@testbench) |vpiTypedef: \_struct_typespec: (bp_bedrock_lce_cmd_msg_header_s), line:5982:11, endln:5982:17 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiName:bp_bedrock_lce_cmd_msg_header_s |vpiInstance: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiPacked:1 |vpiTypespecMember: \_typespec_member: (payload), line:5984:58, endln:5984:65 @@ -87000,10 +87000,10 @@ design: (work@testbench) |vpiTypedef: \_struct_typespec: (bp_bedrock_lce_cmd_msg_s), line:5990:11, endln:5990:17 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiName:bp_bedrock_lce_cmd_msg_s |vpiInstance: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiPacked:1 |vpiTypespecMember: \_typespec_member: (data), line:5992:54, endln:5992:58 @@ -87065,10 +87065,10 @@ design: (work@testbench) |vpiTypedef: \_struct_typespec: (bp_bedrock_lce_cmd_payload_s), line:5949:11, endln:5949:17 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiName:bp_bedrock_lce_cmd_payload_s |vpiInstance: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiPacked:1 |vpiTypespecMember: \_typespec_member: (target_state), line:5951:50, endln:5951:62 @@ -87396,10 +87396,10 @@ design: (work@testbench) |vpiTypedef: \_struct_typespec: (bp_bedrock_lce_req_msg_header_s), line:5967:11, endln:5967:17 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiName:bp_bedrock_lce_req_msg_header_s |vpiInstance: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiPacked:1 |vpiTypespecMember: \_typespec_member: (payload), line:5969:58, endln:5969:65 @@ -87524,10 +87524,10 @@ design: (work@testbench) |vpiTypedef: \_struct_typespec: (bp_bedrock_lce_req_msg_s), line:5975:11, endln:5975:17 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiName:bp_bedrock_lce_req_msg_s |vpiInstance: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiPacked:1 |vpiTypespecMember: \_typespec_member: (data), line:5977:54, endln:5977:58 @@ -87589,10 +87589,10 @@ design: (work@testbench) |vpiTypedef: \_struct_typespec: (bp_bedrock_lce_req_payload_s), line:5941:11, endln:5941:17 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiName:bp_bedrock_lce_req_payload_s |vpiInstance: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiPacked:1 |vpiTypespecMember: \_typespec_member: (lru_way_id), line:5943:70, endln:5943:80 @@ -87784,10 +87784,10 @@ design: (work@testbench) |vpiTypedef: \_struct_typespec: (bp_bedrock_lce_resp_msg_header_s), line:5997:11, endln:5997:17 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiName:bp_bedrock_lce_resp_msg_header_s |vpiInstance: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiPacked:1 |vpiTypespecMember: \_typespec_member: (payload), line:5999:59, endln:5999:66 @@ -87912,10 +87912,10 @@ design: (work@testbench) |vpiTypedef: \_struct_typespec: (bp_bedrock_lce_resp_msg_s), line:6005:11, endln:6005:17 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiName:bp_bedrock_lce_resp_msg_s |vpiInstance: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiPacked:1 |vpiTypespecMember: \_typespec_member: (data), line:6007:54, endln:6007:58 @@ -87977,10 +87977,10 @@ design: (work@testbench) |vpiTypedef: \_struct_typespec: (bp_bedrock_lce_resp_payload_s), line:5960:11, endln:5960:17 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiName:bp_bedrock_lce_resp_payload_s |vpiInstance: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiPacked:1 |vpiTypespecMember: \_typespec_member: (src_id), line:5962:49, endln:5962:55 @@ -88112,157 +88112,157 @@ design: (work@testbench) |vpiNet: \_logic_net: (work@bp_me_nonsynth_lce_tracer.clk_i), line:5914:61, endln:5914:66 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiName:clk_i |vpiFullName:work@bp_me_nonsynth_lce_tracer.clk_i |vpiNet: \_logic_net: (work@bp_me_nonsynth_lce_tracer.reset_i), line:5915:61, endln:5915:68 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiName:reset_i |vpiFullName:work@bp_me_nonsynth_lce_tracer.reset_i |vpiNet: \_logic_net: (work@bp_me_nonsynth_lce_tracer.lce_id_i), line:5917:61, endln:5917:69 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiName:lce_id_i |vpiFullName:work@bp_me_nonsynth_lce_tracer.lce_id_i |vpiNet: \_logic_net: (work@bp_me_nonsynth_lce_tracer.lce_req_i), line:5920:61, endln:5920:70 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiName:lce_req_i |vpiFullName:work@bp_me_nonsynth_lce_tracer.lce_req_i |vpiNet: \_logic_net: (work@bp_me_nonsynth_lce_tracer.lce_req_v_i), line:5921:61, endln:5921:72 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiName:lce_req_v_i |vpiFullName:work@bp_me_nonsynth_lce_tracer.lce_req_v_i |vpiNet: \_logic_net: (work@bp_me_nonsynth_lce_tracer.lce_req_ready_i), line:5922:61, endln:5922:76 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiName:lce_req_ready_i |vpiFullName:work@bp_me_nonsynth_lce_tracer.lce_req_ready_i |vpiNet: \_logic_net: (work@bp_me_nonsynth_lce_tracer.lce_resp_i), line:5924:61, endln:5924:71 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiName:lce_resp_i |vpiFullName:work@bp_me_nonsynth_lce_tracer.lce_resp_i |vpiNet: \_logic_net: (work@bp_me_nonsynth_lce_tracer.lce_resp_v_i), line:5925:61, endln:5925:73 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiName:lce_resp_v_i |vpiFullName:work@bp_me_nonsynth_lce_tracer.lce_resp_v_i |vpiNet: \_logic_net: (work@bp_me_nonsynth_lce_tracer.lce_resp_ready_i), line:5926:61, endln:5926:77 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiName:lce_resp_ready_i |vpiFullName:work@bp_me_nonsynth_lce_tracer.lce_resp_ready_i |vpiNet: \_logic_net: (work@bp_me_nonsynth_lce_tracer.lce_cmd_i), line:5928:61, endln:5928:70 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiName:lce_cmd_i |vpiFullName:work@bp_me_nonsynth_lce_tracer.lce_cmd_i |vpiNet: \_logic_net: (work@bp_me_nonsynth_lce_tracer.lce_cmd_v_i), line:5929:61, endln:5929:72 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiName:lce_cmd_v_i |vpiFullName:work@bp_me_nonsynth_lce_tracer.lce_cmd_v_i |vpiNet: \_logic_net: (work@bp_me_nonsynth_lce_tracer.lce_cmd_yumi_i), line:5930:61, endln:5930:75 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiName:lce_cmd_yumi_i |vpiFullName:work@bp_me_nonsynth_lce_tracer.lce_cmd_yumi_i |vpiNet: \_logic_net: (work@bp_me_nonsynth_lce_tracer.lce_cmd_o_i), line:5932:61, endln:5932:72 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiName:lce_cmd_o_i |vpiFullName:work@bp_me_nonsynth_lce_tracer.lce_cmd_o_i |vpiNet: \_logic_net: (work@bp_me_nonsynth_lce_tracer.lce_cmd_o_v_i), line:5933:61, endln:5933:74 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiName:lce_cmd_o_v_i |vpiFullName:work@bp_me_nonsynth_lce_tracer.lce_cmd_o_v_i |vpiNet: \_logic_net: (work@bp_me_nonsynth_lce_tracer.lce_cmd_o_ready_i), line:5934:61, endln:5934:78 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiName:lce_cmd_o_ready_i |vpiFullName:work@bp_me_nonsynth_lce_tracer.lce_cmd_o_ready_i |vpiNet: \_logic_net: (work@bp_me_nonsynth_lce_tracer.lce_req), line:6014:29, endln:6014:36 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiName:lce_req |vpiFullName:work@bp_me_nonsynth_lce_tracer.lce_req |vpiNet: \_logic_net: (work@bp_me_nonsynth_lce_tracer.lce_resp), line:6015:29, endln:6015:37 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiName:lce_resp |vpiFullName:work@bp_me_nonsynth_lce_tracer.lce_resp |vpiNet: \_logic_net: (work@bp_me_nonsynth_lce_tracer.lce_cmd), line:6016:29, endln:6016:36 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiName:lce_cmd |vpiFullName:work@bp_me_nonsynth_lce_tracer.lce_cmd |vpiNet: \_logic_net: (work@bp_me_nonsynth_lce_tracer.lce_cmd_lo), line:6016:38, endln:6016:48 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiName:lce_cmd_lo |vpiFullName:work@bp_me_nonsynth_lce_tracer.lce_cmd_lo |vpiNet: \_logic_net: (work@bp_me_nonsynth_lce_tracer.lce_req_payload), line:6017:33, endln:6017:48 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiName:lce_req_payload |vpiFullName:work@bp_me_nonsynth_lce_tracer.lce_req_payload |vpiNet: \_logic_net: (work@bp_me_nonsynth_lce_tracer.lce_resp_payload), line:6018:33, endln:6018:49 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiName:lce_resp_payload |vpiFullName:work@bp_me_nonsynth_lce_tracer.lce_resp_payload |vpiNet: \_logic_net: (work@bp_me_nonsynth_lce_tracer.lce_cmd_payload), line:6019:33, endln:6019:48 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiName:lce_cmd_payload |vpiFullName:work@bp_me_nonsynth_lce_tracer.lce_cmd_payload |vpiNet: \_logic_net: (work@bp_me_nonsynth_lce_tracer.lce_cmd_lo_payload), line:6019:50, endln:6019:68 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiName:lce_cmd_lo_payload |vpiFullName:work@bp_me_nonsynth_lce_tracer.lce_cmd_lo_payload |vpiNet: \_logic_net: (work@bp_me_nonsynth_lce_tracer.file), line:6030:11, endln:6030:15 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiName:file |vpiFullName:work@bp_me_nonsynth_lce_tracer.file |vpiNet: \_logic_net: (work@bp_me_nonsynth_lce_tracer.file_name), line:6031:10, endln:6031:19 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiName:file_name |vpiFullName:work@bp_me_nonsynth_lce_tracer.file_name |vpiPort: \_port: (clk_i), line:5914:61, endln:5914:66 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiName:clk_i |vpiDirection:1 |vpiLowConn: @@ -88274,7 +88274,7 @@ design: (work@testbench) |vpiPort: \_port: (reset_i), line:5915:61, endln:5915:68 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiName:reset_i |vpiDirection:1 |vpiLowConn: @@ -88286,7 +88286,7 @@ design: (work@testbench) |vpiPort: \_port: (lce_id_i), line:5917:61, endln:5917:69 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiName:lce_id_i |vpiDirection:1 |vpiLowConn: @@ -88326,7 +88326,7 @@ design: (work@testbench) |vpiPort: \_port: (lce_req_i), line:5920:61, endln:5920:70 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiName:lce_req_i |vpiDirection:1 |vpiLowConn: @@ -88366,7 +88366,7 @@ design: (work@testbench) |vpiPort: \_port: (lce_req_v_i), line:5921:61, endln:5921:72 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiName:lce_req_v_i |vpiDirection:1 |vpiLowConn: @@ -88378,7 +88378,7 @@ design: (work@testbench) |vpiPort: \_port: (lce_req_ready_i), line:5922:61, endln:5922:76 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiName:lce_req_ready_i |vpiDirection:1 |vpiLowConn: @@ -88390,7 +88390,7 @@ design: (work@testbench) |vpiPort: \_port: (lce_resp_i), line:5924:61, endln:5924:71 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiName:lce_resp_i |vpiDirection:1 |vpiLowConn: @@ -88430,7 +88430,7 @@ design: (work@testbench) |vpiPort: \_port: (lce_resp_v_i), line:5925:61, endln:5925:73 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiName:lce_resp_v_i |vpiDirection:1 |vpiLowConn: @@ -88442,7 +88442,7 @@ design: (work@testbench) |vpiPort: \_port: (lce_resp_ready_i), line:5926:61, endln:5926:77 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiName:lce_resp_ready_i |vpiDirection:1 |vpiLowConn: @@ -88454,7 +88454,7 @@ design: (work@testbench) |vpiPort: \_port: (lce_cmd_i), line:5928:61, endln:5928:70 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiName:lce_cmd_i |vpiDirection:1 |vpiLowConn: @@ -88494,7 +88494,7 @@ design: (work@testbench) |vpiPort: \_port: (lce_cmd_v_i), line:5929:61, endln:5929:72 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiName:lce_cmd_v_i |vpiDirection:1 |vpiLowConn: @@ -88506,7 +88506,7 @@ design: (work@testbench) |vpiPort: \_port: (lce_cmd_yumi_i), line:5930:61, endln:5930:75 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiName:lce_cmd_yumi_i |vpiDirection:1 |vpiLowConn: @@ -88518,7 +88518,7 @@ design: (work@testbench) |vpiPort: \_port: (lce_cmd_o_i), line:5932:61, endln:5932:72 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiName:lce_cmd_o_i |vpiDirection:1 |vpiLowConn: @@ -88558,7 +88558,7 @@ design: (work@testbench) |vpiPort: \_port: (lce_cmd_o_v_i), line:5933:61, endln:5933:74 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiName:lce_cmd_o_v_i |vpiDirection:1 |vpiLowConn: @@ -88570,7 +88570,7 @@ design: (work@testbench) |vpiPort: \_port: (lce_cmd_o_ready_i), line:5934:61, endln:5934:78 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiName:lce_cmd_o_ready_i |vpiDirection:1 |vpiLowConn: @@ -88582,7 +88582,7 @@ design: (work@testbench) |vpiProcess: \_always: , line:6033:3, endln:6036:6 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiStmt: \_event_control: , line:6033:13, endln:6033:31 |vpiParent: @@ -88675,7 +88675,7 @@ design: (work@testbench) |vpiProcess: \_always: , line:6038:3, endln:6082:6 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiStmt: \_event_control: , line:6038:13, endln:6038:29 |vpiParent: @@ -89579,7 +89579,7 @@ design: (work@testbench) |vpiContAssign: \_cont_assign: , line:6021:10, endln:6021:29 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiRhs: \_ref_obj: (work@bp_me_nonsynth_lce_tracer.lce_req_i), line:6021:20, endln:6021:29 |vpiParent: @@ -89595,7 +89595,7 @@ design: (work@testbench) |vpiContAssign: \_cont_assign: , line:6022:10, endln:6022:31 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiRhs: \_ref_obj: (work@bp_me_nonsynth_lce_tracer.lce_resp_i), line:6022:21, endln:6022:31 |vpiParent: @@ -89611,7 +89611,7 @@ design: (work@testbench) |vpiContAssign: \_cont_assign: , line:6023:10, endln:6023:29 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiRhs: \_ref_obj: (work@bp_me_nonsynth_lce_tracer.lce_cmd_i), line:6023:20, endln:6023:29 |vpiParent: @@ -89627,7 +89627,7 @@ design: (work@testbench) |vpiContAssign: \_cont_assign: , line:6024:10, endln:6024:34 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiRhs: \_ref_obj: (work@bp_me_nonsynth_lce_tracer.lce_cmd_o_i), line:6024:23, endln:6024:34 |vpiParent: @@ -89643,7 +89643,7 @@ design: (work@testbench) |vpiContAssign: \_cont_assign: , line:6025:10, endln:6025:50 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiRhs: \_hier_path: (lce_req.header.payload), line:6025:28, endln:6025:50 |vpiParent: @@ -89671,7 +89671,7 @@ design: (work@testbench) |vpiContAssign: \_cont_assign: , line:6026:10, endln:6026:52 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiRhs: \_hier_path: (lce_resp.header.payload), line:6026:29, endln:6026:52 |vpiParent: @@ -89699,7 +89699,7 @@ design: (work@testbench) |vpiContAssign: \_cont_assign: , line:6027:10, endln:6027:50 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiRhs: \_hier_path: (lce_cmd.header.payload), line:6027:28, endln:6027:50 |vpiParent: @@ -89727,7 +89727,7 @@ design: (work@testbench) |vpiContAssign: \_cont_assign: , line:6028:10, endln:6028:56 |vpiParent: - \_module: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:5676:1, endln:6084:10 |vpiRhs: \_hier_path: (lce_cmd_lo.header.payload), line:6028:31, endln:6028:56 |vpiParent: @@ -89753,14 +89753,14 @@ design: (work@testbench) |vpiName:lce_cmd_lo_payload |vpiFullName:work@bp_me_nonsynth_lce_tracer.lce_cmd_lo_payload |uhdmallModules: -\_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 +\_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiParent: \_design: (work@testbench) |vpiFullName:work@testbench |vpiParameter: \_parameter: (work@testbench.bp_data_cmd_num_flit_gp), line:911:13, endln:911:36 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |UINT:4 |vpiTypespec: \_int_typespec: @@ -89772,7 +89772,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.bp_data_resp_num_flit_gp), line:910:13, endln:910:37 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |UINT:4 |vpiTypespec: \_int_typespec: @@ -89784,7 +89784,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.bp_eaddr_width_gp), line:899:14, endln:899:31 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |UINT:64 |vpiTypespec: \_int_typespec: @@ -89797,7 +89797,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.bp_instr_width_gp), line:900:14, endln:900:31 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |UINT:32 |vpiTypespec: \_int_typespec: @@ -89810,7 +89810,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.bp_log_file_gp), line:80:12, endln:80:26 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |UINT:2 |vpiTypespec: \_int_typespec: @@ -89823,7 +89823,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.bp_log_none_gp), line:78:12, endln:78:26 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |UINT:0 |vpiTypespec: \_int_typespec: @@ -89836,7 +89836,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.bp_log_stdout_gp), line:79:12, endln:79:28 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |UINT:1 |vpiTypespec: \_int_typespec: @@ -89849,7 +89849,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.bp_page_offset_width_gp), line:908:13, endln:908:36 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |INT:12 |vpiTypespec: \_int_typespec: @@ -89861,7 +89861,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.bp_page_size_in_bytes_gp), line:907:13, endln:907:37 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |UINT:4096 |vpiTypespec: \_int_typespec: @@ -89873,7 +89873,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.bp_sv39_paddr_width_gp), line:905:13, endln:905:35 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |UINT:56 |vpiTypespec: \_int_typespec: @@ -89885,7 +89885,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.bp_sv39_page_table_depth_gp), line:902:13, endln:902:40 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |UINT:3 |vpiTypespec: \_int_typespec: @@ -89897,7 +89897,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.bp_sv39_ppn_width_gp), line:906:13, endln:906:33 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |UINT:44 |vpiTypespec: \_int_typespec: @@ -89909,7 +89909,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.bp_sv39_pte_width_gp), line:903:13, endln:903:33 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |UINT:64 |vpiTypespec: \_int_typespec: @@ -89921,7 +89921,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.bp_sv39_vaddr_width_gp), line:904:13, endln:904:35 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |UINT:39 |vpiTypespec: \_int_typespec: @@ -89933,7 +89933,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.cfg_link_dev_base_addr_gp), line:915:14, endln:915:39 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |HEX:01?????? |vpiTypespec: \_int_typespec: @@ -89960,7 +89960,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.clint_dev_base_addr_gp), line:916:14, endln:916:36 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |HEX:02?????? |vpiTypespec: \_int_typespec: @@ -89987,7 +89987,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.dram_base_addr_gp), line:913:14, endln:913:31 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |HEX:80000000 |vpiTypespec: \_int_typespec: @@ -90014,7 +90014,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.host_dev_base_addr_gp), line:917:14, endln:917:35 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |HEX:03?????? |vpiTypespec: \_int_typespec: @@ -90041,7 +90041,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.mipi_reg_base_addr_gp), line:920:14, endln:920:35 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |HEX:02000??? |vpiTypespec: \_int_typespec: @@ -90068,7 +90068,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.mtime_reg_addr_gp), line:922:14, endln:922:31 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |HEX:0200bff8 |vpiTypespec: \_int_typespec: @@ -90095,7 +90095,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.mtimecmp_reg_base_addr_gp), line:921:14, endln:921:39 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |HEX:02004??? |vpiTypespec: \_int_typespec: @@ -90122,7 +90122,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.plic_dev_base_addr_gp), line:918:14, endln:918:35 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |HEX:0c?????? |vpiTypespec: \_int_typespec: @@ -90149,7 +90149,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.plic_reg_base_addr_gp), line:923:14, endln:923:35 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |HEX:0c000??? |vpiTypespec: \_int_typespec: @@ -90176,7 +90176,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.all_cfgs_gp), line:2516:44, endln:2516:55 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiTypespec: \_packed_array_typespec: , line:2516:13, endln:2516:28 |vpiParent: @@ -90897,7 +90897,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.bp_dual_core_cfg_p), line:2300:30, endln:2300:48 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiTypespec: \_struct_typespec: (bp_common_aviary_pkg::bp_proc_param_s), line:2062:9, endln:2062:15 |vpiParent: @@ -91593,7 +91593,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.bp_half_core_cfg_p), line:2198:30, endln:2198:48 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiTypespec: \_struct_typespec: (bp_common_aviary_pkg::bp_proc_param_s), line:2062:9, endln:2062:15 |vpiParent: @@ -92289,7 +92289,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.bp_inv_cfg_p), line:2195:30, endln:2195:42 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiTypespec: \_struct_typespec: (bp_common_aviary_pkg::bp_proc_param_s), line:2062:9, endln:2062:15 |vpiParent: @@ -92985,7 +92985,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.bp_oct_core_cfg_p), line:2402:30, endln:2402:47 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiTypespec: \_struct_typespec: (bp_common_aviary_pkg::bp_proc_param_s), line:2062:9, endln:2062:15 |vpiParent: @@ -93681,7 +93681,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.bp_quad_core_cfg_p), line:2351:30, endln:2351:48 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiTypespec: \_struct_typespec: (bp_common_aviary_pkg::bp_proc_param_s), line:2062:9, endln:2062:15 |vpiParent: @@ -94377,7 +94377,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.bp_sexta_core_cfg_p), line:2453:30, endln:2453:49 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiTypespec: \_struct_typespec: (bp_common_aviary_pkg::bp_proc_param_s), line:2062:9, endln:2062:15 |vpiParent: @@ -95073,7 +95073,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.bp_single_core_cfg_p), line:2249:30, endln:2249:50 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiTypespec: \_struct_typespec: (bp_common_aviary_pkg::bp_proc_param_s), line:2062:9, endln:2062:15 |vpiParent: @@ -95769,7 +95769,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.lg_max_cfgs), line:2193:14, endln:2193:25 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |INT:7 |vpiTypespec: \_int_typespec: @@ -95782,7 +95782,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.max_cfgs), line:2192:14, endln:2192:22 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |UINT:128 |vpiTypespec: \_int_typespec: @@ -95795,7 +95795,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.bp_data_cmd_num_flit_gp), line:911:13, endln:911:36 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |UINT:4 |vpiTypespec: \_int_typespec: @@ -95807,7 +95807,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.bp_data_resp_num_flit_gp), line:910:13, endln:910:37 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |UINT:4 |vpiTypespec: \_int_typespec: @@ -95819,7 +95819,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.bp_eaddr_width_gp), line:899:14, endln:899:31 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |UINT:64 |vpiTypespec: \_int_typespec: @@ -95832,7 +95832,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.bp_instr_width_gp), line:900:14, endln:900:31 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |UINT:32 |vpiTypespec: \_int_typespec: @@ -95845,7 +95845,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.bp_log_file_gp), line:80:12, endln:80:26 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |UINT:2 |vpiTypespec: \_int_typespec: @@ -95858,7 +95858,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.bp_log_none_gp), line:78:12, endln:78:26 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |UINT:0 |vpiTypespec: \_int_typespec: @@ -95871,7 +95871,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.bp_log_stdout_gp), line:79:12, endln:79:28 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |UINT:1 |vpiTypespec: \_int_typespec: @@ -95884,7 +95884,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.bp_page_offset_width_gp), line:908:13, endln:908:36 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |INT:12 |vpiTypespec: \_int_typespec: @@ -95896,7 +95896,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.bp_page_size_in_bytes_gp), line:907:13, endln:907:37 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |UINT:4096 |vpiTypespec: \_int_typespec: @@ -95908,7 +95908,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.bp_sv39_paddr_width_gp), line:905:13, endln:905:35 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |UINT:56 |vpiTypespec: \_int_typespec: @@ -95920,7 +95920,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.bp_sv39_page_table_depth_gp), line:902:13, endln:902:40 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |UINT:3 |vpiTypespec: \_int_typespec: @@ -95932,7 +95932,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.bp_sv39_ppn_width_gp), line:906:13, endln:906:33 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |UINT:44 |vpiTypespec: \_int_typespec: @@ -95944,7 +95944,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.bp_sv39_pte_width_gp), line:903:13, endln:903:33 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |UINT:64 |vpiTypespec: \_int_typespec: @@ -95956,7 +95956,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.bp_sv39_vaddr_width_gp), line:904:13, endln:904:35 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |UINT:39 |vpiTypespec: \_int_typespec: @@ -95968,7 +95968,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.cfg_link_dev_base_addr_gp), line:915:14, endln:915:39 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |HEX:01?????? |vpiTypespec: \_int_typespec: @@ -95995,7 +95995,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.clint_dev_base_addr_gp), line:916:14, endln:916:36 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |HEX:02?????? |vpiTypespec: \_int_typespec: @@ -96022,7 +96022,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.dram_base_addr_gp), line:913:14, endln:913:31 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |HEX:80000000 |vpiTypespec: \_int_typespec: @@ -96049,7 +96049,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.host_dev_base_addr_gp), line:917:14, endln:917:35 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |HEX:03?????? |vpiTypespec: \_int_typespec: @@ -96076,7 +96076,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.mipi_reg_base_addr_gp), line:920:14, endln:920:35 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |HEX:02000??? |vpiTypespec: \_int_typespec: @@ -96103,7 +96103,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.mtime_reg_addr_gp), line:922:14, endln:922:31 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |HEX:0200bff8 |vpiTypespec: \_int_typespec: @@ -96130,7 +96130,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.mtimecmp_reg_base_addr_gp), line:921:14, endln:921:39 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |HEX:02004??? |vpiTypespec: \_int_typespec: @@ -96157,7 +96157,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.plic_dev_base_addr_gp), line:918:14, endln:918:35 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |HEX:0c?????? |vpiTypespec: \_int_typespec: @@ -96184,7 +96184,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.plic_reg_base_addr_gp), line:923:14, endln:923:35 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |HEX:0c000??? |vpiTypespec: \_int_typespec: @@ -96211,7 +96211,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.rv64_byte_width_gp), line:1962:14, endln:1962:32 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |UINT:8 |vpiTypespec: \_int_typespec: @@ -96224,7 +96224,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.rv64_csr_addr_width_gp), line:1973:14, endln:1973:36 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |UINT:12 |vpiTypespec: \_int_typespec: @@ -96237,7 +96237,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.rv64_dword_width_gp), line:1965:14, endln:1965:33 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |UINT:64 |vpiTypespec: \_int_typespec: @@ -96250,7 +96250,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.rv64_eaddr_width_gp), line:1961:14, endln:1961:33 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |UINT:64 |vpiTypespec: \_int_typespec: @@ -96263,7 +96263,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.rv64_funct3_width_gp), line:1971:14, endln:1971:34 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |UINT:3 |vpiTypespec: \_int_typespec: @@ -96276,7 +96276,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.rv64_funct7_width_gp), line:1972:14, endln:1972:34 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |UINT:7 |vpiTypespec: \_int_typespec: @@ -96289,7 +96289,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.rv64_hword_width_gp), line:1963:14, endln:1963:33 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |UINT:16 |vpiTypespec: \_int_typespec: @@ -96302,7 +96302,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.rv64_imm11to5_width_gp), line:1976:14, endln:1976:36 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |UINT:7 |vpiTypespec: \_int_typespec: @@ -96315,7 +96315,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.rv64_imm12_width_gp), line:1975:14, endln:1975:33 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |UINT:12 |vpiTypespec: \_int_typespec: @@ -96328,7 +96328,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.rv64_imm20_width_gp), line:1974:14, endln:1974:33 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |UINT:20 |vpiTypespec: \_int_typespec: @@ -96341,7 +96341,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.rv64_imm4to0_width_gp), line:1977:14, endln:1977:35 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |UINT:5 |vpiTypespec: \_int_typespec: @@ -96354,7 +96354,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.rv64_instr_width_gp), line:1960:14, endln:1960:33 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |UINT:32 |vpiTypespec: \_int_typespec: @@ -96367,7 +96367,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.rv64_opcode_width_gp), line:1970:14, endln:1970:34 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |UINT:7 |vpiTypespec: \_int_typespec: @@ -96380,7 +96380,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.rv64_priv_width_gp), line:1978:14, endln:1978:32 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |UINT:2 |vpiTypespec: \_int_typespec: @@ -96393,7 +96393,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.rv64_reg_addr_width_gp), line:1967:14, endln:1967:36 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |UINT:5 |vpiTypespec: \_int_typespec: @@ -96406,7 +96406,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.rv64_reg_data_width_gp), line:1966:14, endln:1966:36 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |UINT:64 |vpiTypespec: \_int_typespec: @@ -96419,7 +96419,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.rv64_rf_els_gp), line:1959:14, endln:1959:28 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |UINT:32 |vpiTypespec: \_int_typespec: @@ -96432,7 +96432,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.rv64_shamt_width_gp), line:1968:14, endln:1968:33 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |UINT:6 |vpiTypespec: \_int_typespec: @@ -96445,7 +96445,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.rv64_shamtw_width_gp), line:1969:14, endln:1969:34 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |UINT:5 |vpiTypespec: \_int_typespec: @@ -96458,7 +96458,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.rv64_word_width_gp), line:1964:14, endln:1964:32 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |UINT:32 |vpiTypespec: \_int_typespec: @@ -96471,7 +96471,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.bp_data_cmd_num_flit_gp), line:911:13, endln:911:36 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |UINT:4 |vpiTypespec: \_int_typespec: @@ -96483,7 +96483,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.bp_data_resp_num_flit_gp), line:910:13, endln:910:37 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |UINT:4 |vpiTypespec: \_int_typespec: @@ -96495,7 +96495,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.bp_eaddr_width_gp), line:899:14, endln:899:31 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |UINT:64 |vpiTypespec: \_int_typespec: @@ -96508,7 +96508,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.bp_instr_width_gp), line:900:14, endln:900:31 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |UINT:32 |vpiTypespec: \_int_typespec: @@ -96521,7 +96521,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.bp_log_file_gp), line:80:12, endln:80:26 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |UINT:2 |vpiTypespec: \_int_typespec: @@ -96534,7 +96534,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.bp_log_none_gp), line:78:12, endln:78:26 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |UINT:0 |vpiTypespec: \_int_typespec: @@ -96547,7 +96547,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.bp_log_stdout_gp), line:79:12, endln:79:28 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |UINT:1 |vpiTypespec: \_int_typespec: @@ -96560,7 +96560,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.bp_page_offset_width_gp), line:908:13, endln:908:36 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |INT:12 |vpiTypespec: \_int_typespec: @@ -96572,7 +96572,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.bp_page_size_in_bytes_gp), line:907:13, endln:907:37 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |UINT:4096 |vpiTypespec: \_int_typespec: @@ -96584,7 +96584,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.bp_sv39_paddr_width_gp), line:905:13, endln:905:35 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |UINT:56 |vpiTypespec: \_int_typespec: @@ -96596,7 +96596,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.bp_sv39_page_table_depth_gp), line:902:13, endln:902:40 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |UINT:3 |vpiTypespec: \_int_typespec: @@ -96608,7 +96608,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.bp_sv39_ppn_width_gp), line:906:13, endln:906:33 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |UINT:44 |vpiTypespec: \_int_typespec: @@ -96620,7 +96620,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.bp_sv39_pte_width_gp), line:903:13, endln:903:33 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |UINT:64 |vpiTypespec: \_int_typespec: @@ -96632,7 +96632,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.bp_sv39_vaddr_width_gp), line:904:13, endln:904:35 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |UINT:39 |vpiTypespec: \_int_typespec: @@ -96644,7 +96644,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.cfg_link_dev_base_addr_gp), line:915:14, endln:915:39 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |HEX:01?????? |vpiTypespec: \_int_typespec: @@ -96671,7 +96671,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.clint_dev_base_addr_gp), line:916:14, endln:916:36 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |HEX:02?????? |vpiTypespec: \_int_typespec: @@ -96698,7 +96698,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.dram_base_addr_gp), line:913:14, endln:913:31 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |HEX:80000000 |vpiTypespec: \_int_typespec: @@ -96725,7 +96725,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.host_dev_base_addr_gp), line:917:14, endln:917:35 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |HEX:03?????? |vpiTypespec: \_int_typespec: @@ -96752,7 +96752,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.mem_cmd_payload_mask_gp), line:5661:14, endln:5661:37 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiLocalParam:1 |vpiName:mem_cmd_payload_mask_gp |vpiFullName:work@testbench.mem_cmd_payload_mask_gp @@ -96760,7 +96760,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.mem_resp_payload_mask_gp), line:5662:14, endln:5662:38 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiLocalParam:1 |vpiName:mem_resp_payload_mask_gp |vpiFullName:work@testbench.mem_resp_payload_mask_gp @@ -96768,7 +96768,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.mipi_reg_base_addr_gp), line:920:14, endln:920:35 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |HEX:02000??? |vpiTypespec: \_int_typespec: @@ -96795,7 +96795,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.mtime_reg_addr_gp), line:922:14, endln:922:31 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |HEX:0200bff8 |vpiTypespec: \_int_typespec: @@ -96822,7 +96822,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.mtimecmp_reg_base_addr_gp), line:921:14, endln:921:39 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |HEX:02004??? |vpiTypespec: \_int_typespec: @@ -96849,7 +96849,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.plic_dev_base_addr_gp), line:918:14, endln:918:35 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |HEX:0c?????? |vpiTypespec: \_int_typespec: @@ -96876,7 +96876,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.plic_reg_base_addr_gp), line:923:14, endln:923:35 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |HEX:0c000??? |vpiTypespec: \_int_typespec: @@ -96903,7 +96903,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.bp_params_p), line:6092:26, endln:6092:37 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiTypespec: \_unsupported_typespec: (bp_params_e), line:6092:14, endln:6092:25 |vpiParent: @@ -96914,7 +96914,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.proc_param_lp), line:6094:32, endln:6094:45 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiTypespec: \_struct_typespec: (bp_common_aviary_pkg::bp_proc_param_s), line:2062:9, endln:2062:15 |vpiLocalParam:1 @@ -96923,434 +96923,434 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.multicore_p), line:6096:16, endln:6096:27 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiLocalParam:1 |vpiName:multicore_p |vpiFullName:work@testbench.multicore_p |vpiParameter: \_parameter: (work@testbench.cc_x_dim_p), line:6098:16, endln:6098:26 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiLocalParam:1 |vpiName:cc_x_dim_p |vpiFullName:work@testbench.cc_x_dim_p |vpiParameter: \_parameter: (work@testbench.cc_y_dim_p), line:6099:16, endln:6099:26 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiLocalParam:1 |vpiName:cc_y_dim_p |vpiFullName:work@testbench.cc_y_dim_p |vpiParameter: \_parameter: (work@testbench.ic_x_dim_p), line:6101:16, endln:6101:26 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiLocalParam:1 |vpiName:ic_x_dim_p |vpiFullName:work@testbench.ic_x_dim_p |vpiParameter: \_parameter: (work@testbench.ic_y_dim_p), line:6102:16, endln:6102:26 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiLocalParam:1 |vpiName:ic_y_dim_p |vpiFullName:work@testbench.ic_y_dim_p |vpiParameter: \_parameter: (work@testbench.mc_x_dim_p), line:6103:16, endln:6103:26 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiLocalParam:1 |vpiName:mc_x_dim_p |vpiFullName:work@testbench.mc_x_dim_p |vpiParameter: \_parameter: (work@testbench.mc_y_dim_p), line:6104:16, endln:6104:26 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiLocalParam:1 |vpiName:mc_y_dim_p |vpiFullName:work@testbench.mc_y_dim_p |vpiParameter: \_parameter: (work@testbench.cac_x_dim_p), line:6105:16, endln:6105:27 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiLocalParam:1 |vpiName:cac_x_dim_p |vpiFullName:work@testbench.cac_x_dim_p |vpiParameter: \_parameter: (work@testbench.cac_y_dim_p), line:6106:16, endln:6106:27 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiLocalParam:1 |vpiName:cac_y_dim_p |vpiFullName:work@testbench.cac_y_dim_p |vpiParameter: \_parameter: (work@testbench.sac_x_dim_p), line:6107:16, endln:6107:27 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiLocalParam:1 |vpiName:sac_x_dim_p |vpiFullName:work@testbench.sac_x_dim_p |vpiParameter: \_parameter: (work@testbench.sac_y_dim_p), line:6108:16, endln:6108:27 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiLocalParam:1 |vpiName:sac_y_dim_p |vpiFullName:work@testbench.sac_y_dim_p |vpiParameter: \_parameter: (work@testbench.cacc_type_p), line:6109:16, endln:6109:27 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiLocalParam:1 |vpiName:cacc_type_p |vpiFullName:work@testbench.cacc_type_p |vpiParameter: \_parameter: (work@testbench.sacc_type_p), line:6110:16, endln:6110:27 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiLocalParam:1 |vpiName:sacc_type_p |vpiFullName:work@testbench.sacc_type_p |vpiParameter: \_parameter: (work@testbench.num_core_p), line:6112:16, endln:6112:26 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiLocalParam:1 |vpiName:num_core_p |vpiFullName:work@testbench.num_core_p |vpiParameter: \_parameter: (work@testbench.num_io_p), line:6113:16, endln:6113:24 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiLocalParam:1 |vpiName:num_io_p |vpiFullName:work@testbench.num_io_p |vpiParameter: \_parameter: (work@testbench.num_l2e_p), line:6114:16, endln:6114:25 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiLocalParam:1 |vpiName:num_l2e_p |vpiFullName:work@testbench.num_l2e_p |vpiParameter: \_parameter: (work@testbench.num_cacc_p), line:6115:16, endln:6115:26 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiLocalParam:1 |vpiName:num_cacc_p |vpiFullName:work@testbench.num_cacc_p |vpiParameter: \_parameter: (work@testbench.num_sacc_p), line:6116:16, endln:6116:26 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiLocalParam:1 |vpiName:num_sacc_p |vpiFullName:work@testbench.num_sacc_p |vpiParameter: \_parameter: (work@testbench.num_cce_p), line:6118:16, endln:6118:25 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiLocalParam:1 |vpiName:num_cce_p |vpiFullName:work@testbench.num_cce_p |vpiParameter: \_parameter: (work@testbench.num_lce_p), line:6119:16, endln:6119:25 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiLocalParam:1 |vpiName:num_lce_p |vpiFullName:work@testbench.num_lce_p |vpiParameter: \_parameter: (work@testbench.core_id_width_p), line:6121:16, endln:6121:31 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiLocalParam:1 |vpiName:core_id_width_p |vpiFullName:work@testbench.core_id_width_p |vpiParameter: \_parameter: (work@testbench.cce_id_width_p), line:6122:16, endln:6122:30 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiLocalParam:1 |vpiName:cce_id_width_p |vpiFullName:work@testbench.cce_id_width_p |vpiParameter: \_parameter: (work@testbench.lce_id_width_p), line:6123:16, endln:6123:30 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiLocalParam:1 |vpiName:lce_id_width_p |vpiFullName:work@testbench.lce_id_width_p |vpiParameter: \_parameter: (work@testbench.vaddr_width_p), line:6125:16, endln:6125:29 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiLocalParam:1 |vpiName:vaddr_width_p |vpiFullName:work@testbench.vaddr_width_p |vpiParameter: \_parameter: (work@testbench.paddr_width_p), line:6126:16, endln:6126:29 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiLocalParam:1 |vpiName:paddr_width_p |vpiFullName:work@testbench.paddr_width_p |vpiParameter: \_parameter: (work@testbench.asid_width_p), line:6127:16, endln:6127:28 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiLocalParam:1 |vpiName:asid_width_p |vpiFullName:work@testbench.asid_width_p |vpiParameter: \_parameter: (work@testbench.boot_pc_p), line:6129:16, endln:6129:25 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiLocalParam:1 |vpiName:boot_pc_p |vpiFullName:work@testbench.boot_pc_p |vpiParameter: \_parameter: (work@testbench.boot_in_debug_p), line:6130:16, endln:6130:31 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiLocalParam:1 |vpiName:boot_in_debug_p |vpiFullName:work@testbench.boot_in_debug_p |vpiParameter: \_parameter: (work@testbench.branch_metadata_fwd_width_p), line:6132:16, endln:6132:43 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiLocalParam:1 |vpiName:branch_metadata_fwd_width_p |vpiFullName:work@testbench.branch_metadata_fwd_width_p |vpiParameter: \_parameter: (work@testbench.btb_tag_width_p), line:6133:16, endln:6133:31 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiLocalParam:1 |vpiName:btb_tag_width_p |vpiFullName:work@testbench.btb_tag_width_p |vpiParameter: \_parameter: (work@testbench.btb_idx_width_p), line:6134:16, endln:6134:31 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiLocalParam:1 |vpiName:btb_idx_width_p |vpiFullName:work@testbench.btb_idx_width_p |vpiParameter: \_parameter: (work@testbench.bht_idx_width_p), line:6135:16, endln:6135:31 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiLocalParam:1 |vpiName:bht_idx_width_p |vpiFullName:work@testbench.bht_idx_width_p |vpiParameter: \_parameter: (work@testbench.ghist_width_p), line:6136:16, endln:6136:29 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiLocalParam:1 |vpiName:ghist_width_p |vpiFullName:work@testbench.ghist_width_p |vpiParameter: \_parameter: (work@testbench.itlb_els_p), line:6138:16, endln:6138:26 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiLocalParam:1 |vpiName:itlb_els_p |vpiFullName:work@testbench.itlb_els_p |vpiParameter: \_parameter: (work@testbench.dtlb_els_p), line:6139:16, endln:6139:26 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiLocalParam:1 |vpiName:dtlb_els_p |vpiFullName:work@testbench.dtlb_els_p |vpiParameter: \_parameter: (work@testbench.lr_sc_p), line:6141:16, endln:6141:23 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiLocalParam:1 |vpiName:lr_sc_p |vpiFullName:work@testbench.lr_sc_p |vpiParameter: \_parameter: (work@testbench.amo_swap_p), line:6142:16, endln:6142:26 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiLocalParam:1 |vpiName:amo_swap_p |vpiFullName:work@testbench.amo_swap_p |vpiParameter: \_parameter: (work@testbench.amo_fetch_logic_p), line:6143:16, endln:6143:33 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiLocalParam:1 |vpiName:amo_fetch_logic_p |vpiFullName:work@testbench.amo_fetch_logic_p |vpiParameter: \_parameter: (work@testbench.amo_fetch_arithmetic_p), line:6144:16, endln:6144:38 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiLocalParam:1 |vpiName:amo_fetch_arithmetic_p |vpiFullName:work@testbench.amo_fetch_arithmetic_p |vpiParameter: \_parameter: (work@testbench.l1_coherent_p), line:6146:16, endln:6146:29 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiLocalParam:1 |vpiName:l1_coherent_p |vpiFullName:work@testbench.l1_coherent_p |vpiParameter: \_parameter: (work@testbench.l1_writethrough_p), line:6147:16, endln:6147:33 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiLocalParam:1 |vpiName:l1_writethrough_p |vpiFullName:work@testbench.l1_writethrough_p |vpiParameter: \_parameter: (work@testbench.dcache_sets_p), line:6148:16, endln:6148:29 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiLocalParam:1 |vpiName:dcache_sets_p |vpiFullName:work@testbench.dcache_sets_p |vpiParameter: \_parameter: (work@testbench.dcache_assoc_p), line:6149:16, endln:6149:30 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiLocalParam:1 |vpiName:dcache_assoc_p |vpiFullName:work@testbench.dcache_assoc_p |vpiParameter: \_parameter: (work@testbench.dcache_block_width_p), line:6150:16, endln:6150:36 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiLocalParam:1 |vpiName:dcache_block_width_p |vpiFullName:work@testbench.dcache_block_width_p |vpiParameter: \_parameter: (work@testbench.dcache_fill_width_p), line:6151:16, endln:6151:35 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiLocalParam:1 |vpiName:dcache_fill_width_p |vpiFullName:work@testbench.dcache_fill_width_p |vpiParameter: \_parameter: (work@testbench.icache_sets_p), line:6152:16, endln:6152:29 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiLocalParam:1 |vpiName:icache_sets_p |vpiFullName:work@testbench.icache_sets_p |vpiParameter: \_parameter: (work@testbench.icache_assoc_p), line:6153:16, endln:6153:30 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiLocalParam:1 |vpiName:icache_assoc_p |vpiFullName:work@testbench.icache_assoc_p |vpiParameter: \_parameter: (work@testbench.icache_block_width_p), line:6154:16, endln:6154:36 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiLocalParam:1 |vpiName:icache_block_width_p |vpiFullName:work@testbench.icache_block_width_p |vpiParameter: \_parameter: (work@testbench.icache_fill_width_p), line:6155:16, endln:6155:35 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiLocalParam:1 |vpiName:icache_fill_width_p |vpiFullName:work@testbench.icache_fill_width_p |vpiParameter: \_parameter: (work@testbench.acache_sets_p), line:6156:16, endln:6156:29 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiLocalParam:1 |vpiName:acache_sets_p |vpiFullName:work@testbench.acache_sets_p |vpiParameter: \_parameter: (work@testbench.acache_assoc_p), line:6157:16, endln:6157:30 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiLocalParam:1 |vpiName:acache_assoc_p |vpiFullName:work@testbench.acache_assoc_p |vpiParameter: \_parameter: (work@testbench.acache_block_width_p), line:6158:16, endln:6158:36 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiLocalParam:1 |vpiName:acache_block_width_p |vpiFullName:work@testbench.acache_block_width_p |vpiParameter: \_parameter: (work@testbench.acache_fill_width_p), line:6159:16, endln:6159:35 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiLocalParam:1 |vpiName:acache_fill_width_p |vpiFullName:work@testbench.acache_fill_width_p |vpiParameter: \_parameter: (work@testbench.lce_assoc_p), line:6160:16, endln:6160:27 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiLocalParam:1 |vpiName:lce_assoc_p |vpiFullName:work@testbench.lce_assoc_p |vpiParameter: \_parameter: (work@testbench.lce_assoc_width_p), line:6164:16, endln:6164:33 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiLocalParam:1 |vpiName:lce_assoc_width_p |vpiFullName:work@testbench.lce_assoc_width_p |vpiParameter: \_parameter: (work@testbench.lce_sets_p), line:6165:16, endln:6165:26 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiLocalParam:1 |vpiName:lce_sets_p |vpiFullName:work@testbench.lce_sets_p |vpiParameter: \_parameter: (work@testbench.lce_sets_width_p), line:6169:16, endln:6169:32 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiLocalParam:1 |vpiName:lce_sets_width_p |vpiFullName:work@testbench.lce_sets_width_p |vpiParameter: \_parameter: (work@testbench.cce_block_width_p), line:6171:16, endln:6171:33 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiLocalParam:1 |vpiName:cce_block_width_p |vpiFullName:work@testbench.cce_block_width_p |vpiParameter: \_parameter: (work@testbench.cce_pc_width_p), line:6183:16, endln:6183:30 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiLocalParam:1 |vpiName:cce_pc_width_p |vpiFullName:work@testbench.cce_pc_width_p |vpiParameter: \_parameter: (work@testbench.num_cce_instr_ram_els_p), line:6184:16, endln:6184:39 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiLocalParam:1 |vpiName:num_cce_instr_ram_els_p |vpiFullName:work@testbench.num_cce_instr_ram_els_p |vpiParameter: \_parameter: (work@testbench.cce_way_groups_p), line:6185:16, endln:6185:32 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiLocalParam:1 |vpiName:cce_way_groups_p |vpiFullName:work@testbench.cce_way_groups_p |vpiParameter: \_parameter: (work@testbench.cce_instr_width_p), line:6186:16, endln:6186:33 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |UINT:34 |vpiTypespec: \_int_typespec: @@ -97360,105 +97360,105 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.cce_ucode_p), line:6187:16, endln:6187:27 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiLocalParam:1 |vpiName:cce_ucode_p |vpiFullName:work@testbench.cce_ucode_p |vpiParameter: \_parameter: (work@testbench.l2_en_p), line:6189:16, endln:6189:23 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiLocalParam:1 |vpiName:l2_en_p |vpiFullName:work@testbench.l2_en_p |vpiParameter: \_parameter: (work@testbench.l2_sets_p), line:6190:16, endln:6190:25 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiLocalParam:1 |vpiName:l2_sets_p |vpiFullName:work@testbench.l2_sets_p |vpiParameter: \_parameter: (work@testbench.l2_assoc_p), line:6191:16, endln:6191:26 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiLocalParam:1 |vpiName:l2_assoc_p |vpiFullName:work@testbench.l2_assoc_p |vpiParameter: \_parameter: (work@testbench.l2_outstanding_reqs_p), line:6192:16, endln:6192:37 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiLocalParam:1 |vpiName:l2_outstanding_reqs_p |vpiFullName:work@testbench.l2_outstanding_reqs_p |vpiParameter: \_parameter: (work@testbench.fe_queue_fifo_els_p), line:6194:16, endln:6194:35 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiLocalParam:1 |vpiName:fe_queue_fifo_els_p |vpiFullName:work@testbench.fe_queue_fifo_els_p |vpiParameter: \_parameter: (work@testbench.fe_cmd_fifo_els_p), line:6195:16, endln:6195:33 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiLocalParam:1 |vpiName:fe_cmd_fifo_els_p |vpiFullName:work@testbench.fe_cmd_fifo_els_p |vpiParameter: \_parameter: (work@testbench.async_coh_clk_p), line:6197:16, endln:6197:31 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiLocalParam:1 |vpiName:async_coh_clk_p |vpiFullName:work@testbench.async_coh_clk_p |vpiParameter: \_parameter: (work@testbench.coh_noc_max_credits_p), line:6198:16, endln:6198:37 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiLocalParam:1 |vpiName:coh_noc_max_credits_p |vpiFullName:work@testbench.coh_noc_max_credits_p |vpiParameter: \_parameter: (work@testbench.coh_noc_flit_width_p), line:6199:16, endln:6199:36 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiLocalParam:1 |vpiName:coh_noc_flit_width_p |vpiFullName:work@testbench.coh_noc_flit_width_p |vpiParameter: \_parameter: (work@testbench.coh_noc_cid_width_p), line:6200:16, endln:6200:35 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiLocalParam:1 |vpiName:coh_noc_cid_width_p |vpiFullName:work@testbench.coh_noc_cid_width_p |vpiParameter: \_parameter: (work@testbench.coh_noc_len_width_p), line:6201:16, endln:6201:35 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiLocalParam:1 |vpiName:coh_noc_len_width_p |vpiFullName:work@testbench.coh_noc_len_width_p |vpiParameter: \_parameter: (work@testbench.coh_noc_y_cord_width_p), line:6202:16, endln:6202:38 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiLocalParam:1 |vpiName:coh_noc_y_cord_width_p |vpiFullName:work@testbench.coh_noc_y_cord_width_p |vpiParameter: \_parameter: (work@testbench.coh_noc_x_cord_width_p), line:6203:16, endln:6203:38 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiLocalParam:1 |vpiName:coh_noc_x_cord_width_p |vpiFullName:work@testbench.coh_noc_x_cord_width_p |vpiParameter: \_parameter: (work@testbench.coh_noc_dims_p), line:6204:16, endln:6204:30 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |UINT:2 |vpiTypespec: \_int_typespec: @@ -97468,14 +97468,14 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.coh_noc_dirs_p), line:6205:16, endln:6205:30 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiLocalParam:1 |vpiName:coh_noc_dirs_p |vpiFullName:work@testbench.coh_noc_dirs_p |vpiParameter: \_parameter: (work@testbench.coh_noc_trans_p), line:6206:16, endln:6206:31 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |UINT:0 |vpiTypespec: \_int_typespec: @@ -97485,7 +97485,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.coh_noc_cord_markers_pos_p), line:6207:20, endln:6207:46 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiSize:1 |vpiTypespec: \_array_typespec: @@ -97521,56 +97521,56 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.coh_noc_cord_width_p), line:6210:16, endln:6210:36 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiLocalParam:1 |vpiName:coh_noc_cord_width_p |vpiFullName:work@testbench.coh_noc_cord_width_p |vpiParameter: \_parameter: (work@testbench.async_mem_clk_p), line:6212:16, endln:6212:31 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiLocalParam:1 |vpiName:async_mem_clk_p |vpiFullName:work@testbench.async_mem_clk_p |vpiParameter: \_parameter: (work@testbench.mem_noc_max_credits_p), line:6213:16, endln:6213:37 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiLocalParam:1 |vpiName:mem_noc_max_credits_p |vpiFullName:work@testbench.mem_noc_max_credits_p |vpiParameter: \_parameter: (work@testbench.mem_noc_flit_width_p), line:6214:16, endln:6214:36 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiLocalParam:1 |vpiName:mem_noc_flit_width_p |vpiFullName:work@testbench.mem_noc_flit_width_p |vpiParameter: \_parameter: (work@testbench.mem_noc_cid_width_p), line:6215:16, endln:6215:35 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiLocalParam:1 |vpiName:mem_noc_cid_width_p |vpiFullName:work@testbench.mem_noc_cid_width_p |vpiParameter: \_parameter: (work@testbench.mem_noc_len_width_p), line:6216:16, endln:6216:35 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiLocalParam:1 |vpiName:mem_noc_len_width_p |vpiFullName:work@testbench.mem_noc_len_width_p |vpiParameter: \_parameter: (work@testbench.mem_noc_y_cord_width_p), line:6217:16, endln:6217:38 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiLocalParam:1 |vpiName:mem_noc_y_cord_width_p |vpiFullName:work@testbench.mem_noc_y_cord_width_p |vpiParameter: \_parameter: (work@testbench.mem_noc_x_cord_width_p), line:6218:16, endln:6218:38 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |UINT:0 |vpiTypespec: \_int_typespec: @@ -97580,7 +97580,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.mem_noc_dims_p), line:6219:16, endln:6219:30 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |UINT:1 |vpiTypespec: \_int_typespec: @@ -97590,7 +97590,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.mem_noc_cord_dims_p), line:6220:16, endln:6220:35 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |UINT:2 |vpiTypespec: \_int_typespec: @@ -97600,14 +97600,14 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.mem_noc_dirs_p), line:6221:16, endln:6221:30 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiLocalParam:1 |vpiName:mem_noc_dirs_p |vpiFullName:work@testbench.mem_noc_dirs_p |vpiParameter: \_parameter: (work@testbench.mem_noc_trans_p), line:6222:16, endln:6222:31 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |UINT:1 |vpiTypespec: \_int_typespec: @@ -97617,7 +97617,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.mem_noc_cord_markers_pos_p), line:6223:20, endln:6223:46 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiSize:1 |vpiTypespec: \_array_typespec: @@ -97653,56 +97653,56 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.mem_noc_cord_width_p), line:6226:16, endln:6226:36 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiLocalParam:1 |vpiName:mem_noc_cord_width_p |vpiFullName:work@testbench.mem_noc_cord_width_p |vpiParameter: \_parameter: (work@testbench.async_io_clk_p), line:6228:16, endln:6228:30 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiLocalParam:1 |vpiName:async_io_clk_p |vpiFullName:work@testbench.async_io_clk_p |vpiParameter: \_parameter: (work@testbench.io_noc_max_credits_p), line:6229:16, endln:6229:36 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiLocalParam:1 |vpiName:io_noc_max_credits_p |vpiFullName:work@testbench.io_noc_max_credits_p |vpiParameter: \_parameter: (work@testbench.io_noc_did_width_p), line:6230:16, endln:6230:34 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiLocalParam:1 |vpiName:io_noc_did_width_p |vpiFullName:work@testbench.io_noc_did_width_p |vpiParameter: \_parameter: (work@testbench.io_noc_flit_width_p), line:6231:16, endln:6231:35 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiLocalParam:1 |vpiName:io_noc_flit_width_p |vpiFullName:work@testbench.io_noc_flit_width_p |vpiParameter: \_parameter: (work@testbench.io_noc_cid_width_p), line:6232:16, endln:6232:34 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiLocalParam:1 |vpiName:io_noc_cid_width_p |vpiFullName:work@testbench.io_noc_cid_width_p |vpiParameter: \_parameter: (work@testbench.io_noc_len_width_p), line:6233:16, endln:6233:34 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiLocalParam:1 |vpiName:io_noc_len_width_p |vpiFullName:work@testbench.io_noc_len_width_p |vpiParameter: \_parameter: (work@testbench.io_noc_y_cord_width_p), line:6234:16, endln:6234:37 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |UINT:0 |vpiTypespec: \_int_typespec: @@ -97712,14 +97712,14 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.io_noc_x_cord_width_p), line:6235:16, endln:6235:37 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiLocalParam:1 |vpiName:io_noc_x_cord_width_p |vpiFullName:work@testbench.io_noc_x_cord_width_p |vpiParameter: \_parameter: (work@testbench.io_noc_dims_p), line:6236:16, endln:6236:29 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |UINT:1 |vpiTypespec: \_int_typespec: @@ -97729,7 +97729,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.io_noc_cord_dims_p), line:6237:16, endln:6237:34 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |UINT:2 |vpiTypespec: \_int_typespec: @@ -97739,14 +97739,14 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.io_noc_dirs_p), line:6238:16, endln:6238:29 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiLocalParam:1 |vpiName:io_noc_dirs_p |vpiFullName:work@testbench.io_noc_dirs_p |vpiParameter: \_parameter: (work@testbench.io_noc_trans_p), line:6239:16, endln:6239:30 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |UINT:0 |vpiTypespec: \_int_typespec: @@ -97756,7 +97756,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.io_noc_cord_markers_pos_p), line:6240:20, endln:6240:45 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiSize:1 |vpiTypespec: \_array_typespec: @@ -97792,14 +97792,14 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.io_noc_cord_width_p), line:6243:16, endln:6243:35 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiLocalParam:1 |vpiName:io_noc_cord_width_p |vpiFullName:work@testbench.io_noc_cord_width_p |vpiParameter: \_parameter: (work@testbench.dword_width_p), line:6245:16, endln:6245:29 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |UINT:64 |vpiTypespec: \_int_typespec: @@ -97809,7 +97809,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.word_width_p), line:6246:16, endln:6246:28 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |UINT:32 |vpiTypespec: \_int_typespec: @@ -97819,7 +97819,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.instr_width_p), line:6247:16, endln:6247:29 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |UINT:32 |vpiTypespec: \_int_typespec: @@ -97829,7 +97829,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.csr_addr_width_p), line:6248:16, endln:6248:32 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |UINT:12 |vpiTypespec: \_int_typespec: @@ -97839,7 +97839,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.reg_addr_width_p), line:6249:16, endln:6249:32 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |UINT:5 |vpiTypespec: \_int_typespec: @@ -97849,7 +97849,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.page_offset_width_p), line:6250:16, endln:6250:35 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |UINT:12 |vpiTypespec: \_int_typespec: @@ -97859,56 +97859,56 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.vtag_width_p), line:6252:16, endln:6252:28 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiLocalParam:1 |vpiName:vtag_width_p |vpiFullName:work@testbench.vtag_width_p |vpiParameter: \_parameter: (work@testbench.ptag_width_p), line:6253:16, endln:6253:28 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiLocalParam:1 |vpiName:ptag_width_p |vpiFullName:work@testbench.ptag_width_p |vpiParameter: \_parameter: (work@testbench.fe_queue_width_lp), line:6256:16, endln:6256:33 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiLocalParam:1 |vpiName:fe_queue_width_lp |vpiFullName:work@testbench.fe_queue_width_lp |vpiParameter: \_parameter: (work@testbench.fe_cmd_width_lp), line:6277:16, endln:6277:31 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiLocalParam:1 |vpiName:fe_cmd_width_lp |vpiFullName:work@testbench.fe_cmd_width_lp |vpiParameter: \_parameter: (work@testbench.cce_mem_payload_width_lp), line:6386:16, endln:6386:40 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiLocalParam:1 |vpiName:cce_mem_payload_width_lp |vpiFullName:work@testbench.cce_mem_payload_width_lp |vpiParameter: \_parameter: (work@testbench.cce_mem_msg_header_width_lp), line:6391:16, endln:6391:43 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiLocalParam:1 |vpiName:cce_mem_msg_header_width_lp |vpiFullName:work@testbench.cce_mem_msg_header_width_lp |vpiParameter: \_parameter: (work@testbench.cce_mem_msg_width_lp), line:6396:16, endln:6396:36 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiLocalParam:1 |vpiName:cce_mem_msg_width_lp |vpiFullName:work@testbench.cce_mem_msg_width_lp |vpiParameter: \_parameter: (work@testbench.icache_trace_p), line:6405:16, endln:6405:30 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |UINT:0 |vpiTypespec: \_int_typespec: @@ -97917,7 +97917,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.dcache_trace_p), line:6406:16, endln:6406:30 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |UINT:0 |vpiTypespec: \_int_typespec: @@ -97926,7 +97926,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.lce_trace_p), line:6407:16, endln:6407:27 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |UINT:0 |vpiTypespec: \_int_typespec: @@ -97935,7 +97935,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.cce_trace_p), line:6408:16, endln:6408:27 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |UINT:0 |vpiTypespec: \_int_typespec: @@ -97944,7 +97944,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.dram_trace_p), line:6409:16, endln:6409:28 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |UINT:0 |vpiTypespec: \_int_typespec: @@ -97953,7 +97953,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.vm_trace_p), line:6410:16, endln:6410:26 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |UINT:0 |vpiTypespec: \_int_typespec: @@ -97962,7 +97962,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.cmt_trace_p), line:6411:16, endln:6411:27 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |UINT:0 |vpiTypespec: \_int_typespec: @@ -97971,7 +97971,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.core_profile_p), line:6412:16, endln:6412:30 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |UINT:0 |vpiTypespec: \_int_typespec: @@ -97980,7 +97980,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.pc_profile_p), line:6413:16, endln:6413:28 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |UINT:0 |vpiTypespec: \_int_typespec: @@ -97989,7 +97989,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.br_profile_p), line:6414:16, endln:6414:28 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |UINT:0 |vpiTypespec: \_int_typespec: @@ -97998,7 +97998,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.cosim_p), line:6415:16, endln:6415:23 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |UINT:0 |vpiTypespec: \_int_typespec: @@ -98007,7 +98007,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.checkpoint_p), line:6418:16, endln:6418:28 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |UINT:0 |vpiTypespec: \_int_typespec: @@ -98016,7 +98016,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.cosim_memsize_p), line:6419:16, endln:6419:31 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |UINT:0 |vpiTypespec: \_int_typespec: @@ -98025,7 +98025,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.cosim_cfg_file_p), line:6420:16, endln:6420:32 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |STRING:prog.cfg |vpiTypespec: \_string_typespec: @@ -98034,7 +98034,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.cosim_instr_p), line:6421:16, endln:6421:29 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |UINT:0 |vpiTypespec: \_int_typespec: @@ -98043,7 +98043,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.warmup_instr_p), line:6422:16, endln:6422:30 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |UINT:0 |vpiTypespec: \_int_typespec: @@ -98052,7 +98052,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.preload_mem_p), line:6425:16, endln:6425:29 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |UINT:0 |vpiTypespec: \_int_typespec: @@ -98061,7 +98061,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.use_ddr_p), line:6426:16, endln:6426:25 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |UINT:0 |vpiTypespec: \_int_typespec: @@ -98070,7 +98070,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.use_dramsim3_p), line:6427:16, endln:6427:30 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |UINT:0 |vpiTypespec: \_int_typespec: @@ -98079,7 +98079,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.dram_fixed_latency_p), line:6428:16, endln:6428:36 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |UINT:0 |vpiTypespec: \_int_typespec: @@ -98088,7 +98088,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.mem_offset_p), line:6429:36, endln:6429:48 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |HEX:80000000 |vpiTypespec: \_int_typespec: , line:6429:16, endln:6429:35 @@ -98129,13 +98129,13 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.mem_cap_in_bytes_p), line:6430:16, endln:6430:34 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiName:mem_cap_in_bytes_p |vpiFullName:work@testbench.mem_cap_in_bytes_p |vpiParameter: \_parameter: (work@testbench.mem_file_p), line:6431:16, endln:6431:26 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |STRING:prog.mem |vpiTypespec: \_string_typespec: @@ -98144,7 +98144,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:78:12, endln:78:32 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_constant: , line:78:31, endln:78:32 |vpiParent: @@ -98173,7 +98173,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:79:12, endln:79:32 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_constant: , line:79:31, endln:79:32 |vpiParent: @@ -98202,7 +98202,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:80:12, endln:80:32 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_constant: , line:80:31, endln:80:32 |vpiParent: @@ -98231,7 +98231,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:899:14, endln:899:36 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_constant: , line:899:34, endln:899:36 |vpiParent: @@ -98260,7 +98260,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:900:14, endln:900:36 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_constant: , line:900:34, endln:900:36 |vpiParent: @@ -98289,7 +98289,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:902:13, endln:902:44 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_constant: , line:902:43, endln:902:44 |vpiParent: @@ -98317,7 +98317,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:903:13, endln:903:38 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_constant: , line:903:36, endln:903:38 |vpiParent: @@ -98345,7 +98345,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:904:13, endln:904:40 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_constant: , line:904:38, endln:904:40 |vpiParent: @@ -98373,7 +98373,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:905:13, endln:905:40 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_constant: , line:905:38, endln:905:40 |vpiParent: @@ -98401,7 +98401,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:906:13, endln:906:38 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_constant: , line:906:36, endln:906:38 |vpiParent: @@ -98429,7 +98429,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:907:13, endln:907:44 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_constant: , line:907:40, endln:907:44 |vpiParent: @@ -98457,7 +98457,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:908:13, endln:908:114 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_constant: , line:908:41, endln:908:72 |vpiParent: @@ -98485,7 +98485,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:910:13, endln:910:41 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_constant: , line:910:40, endln:910:41 |vpiParent: @@ -98513,7 +98513,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:911:13, endln:911:40 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_constant: , line:911:39, endln:911:40 |vpiParent: @@ -98541,7 +98541,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:913:14, endln:913:55 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_constant: , line:913:42, endln:913:55 |vpiParent: @@ -98598,7 +98598,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:915:14, endln:915:55 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_constant: , line:915:42, endln:915:55 |vpiParent: @@ -98655,7 +98655,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:916:14, endln:916:55 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_constant: , line:916:42, endln:916:55 |vpiParent: @@ -98712,7 +98712,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:917:14, endln:917:55 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_constant: , line:917:42, endln:917:55 |vpiParent: @@ -98769,7 +98769,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:918:14, endln:918:55 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_constant: , line:918:42, endln:918:55 |vpiParent: @@ -98826,7 +98826,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:920:14, endln:920:55 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_constant: , line:920:42, endln:920:55 |vpiParent: @@ -98883,7 +98883,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:921:14, endln:921:55 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_constant: , line:921:42, endln:921:55 |vpiParent: @@ -98940,7 +98940,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:922:14, endln:922:55 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_constant: , line:922:42, endln:922:55 |vpiParent: @@ -98997,7 +98997,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:923:14, endln:923:55 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_constant: , line:923:42, endln:923:55 |vpiParent: @@ -99054,7 +99054,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:2192:14, endln:2192:31 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_constant: , line:2192:28, endln:2192:31 |vpiParent: @@ -99083,7 +99083,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:2193:14, endln:2193:71 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_constant: , line:2193:30, endln:2193:45 |vpiParent: @@ -99112,7 +99112,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:2195:30, endln:2196:22 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_operation: , line:2196:5, endln:2196:22 |vpiParent: @@ -99834,7 +99834,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:2198:30, endln:2247:8 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_operation: , line:2199:5, endln:2247:8 |vpiParent: @@ -101219,7 +101219,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:2249:30, endln:2298:8 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_operation: , line:2250:5, endln:2298:8 |vpiParent: @@ -102604,7 +102604,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:2300:30, endln:2349:8 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_operation: , line:2301:5, endln:2349:8 |vpiParent: @@ -103989,7 +103989,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:2351:30, endln:2400:8 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_operation: , line:2352:5, endln:2400:8 |vpiParent: @@ -105374,7 +105374,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:2402:30, endln:2451:8 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_operation: , line:2403:5, endln:2451:8 |vpiParent: @@ -106759,7 +106759,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:2453:30, endln:2502:8 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_operation: , line:2454:5, endln:2502:8 |vpiParent: @@ -108144,7 +108144,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:2516:44, endln:2525:4 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_operation: , line:2517:3, endln:2525:4 |vpiParent: @@ -108917,7 +108917,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:78:12, endln:78:32 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_constant: , line:78:31, endln:78:32 |vpiParent: @@ -108946,7 +108946,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:79:12, endln:79:32 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_constant: , line:79:31, endln:79:32 |vpiParent: @@ -108975,7 +108975,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:80:12, endln:80:32 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_constant: , line:80:31, endln:80:32 |vpiParent: @@ -109004,7 +109004,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:899:14, endln:899:36 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_constant: , line:899:34, endln:899:36 |vpiParent: @@ -109033,7 +109033,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:900:14, endln:900:36 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_constant: , line:900:34, endln:900:36 |vpiParent: @@ -109062,7 +109062,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:902:13, endln:902:44 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_constant: , line:902:43, endln:902:44 |vpiParent: @@ -109090,7 +109090,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:903:13, endln:903:38 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_constant: , line:903:36, endln:903:38 |vpiParent: @@ -109118,7 +109118,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:904:13, endln:904:40 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_constant: , line:904:38, endln:904:40 |vpiParent: @@ -109146,7 +109146,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:905:13, endln:905:40 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_constant: , line:905:38, endln:905:40 |vpiParent: @@ -109174,7 +109174,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:906:13, endln:906:38 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_constant: , line:906:36, endln:906:38 |vpiParent: @@ -109202,7 +109202,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:907:13, endln:907:44 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_constant: , line:907:40, endln:907:44 |vpiParent: @@ -109230,7 +109230,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:908:13, endln:908:114 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_constant: , line:908:41, endln:908:72 |vpiParent: @@ -109258,7 +109258,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:910:13, endln:910:41 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_constant: , line:910:40, endln:910:41 |vpiParent: @@ -109286,7 +109286,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:911:13, endln:911:40 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_constant: , line:911:39, endln:911:40 |vpiParent: @@ -109314,7 +109314,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:913:14, endln:913:55 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_constant: , line:913:42, endln:913:55 |vpiParent: @@ -109371,7 +109371,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:915:14, endln:915:55 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_constant: , line:915:42, endln:915:55 |vpiParent: @@ -109428,7 +109428,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:916:14, endln:916:55 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_constant: , line:916:42, endln:916:55 |vpiParent: @@ -109485,7 +109485,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:917:14, endln:917:55 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_constant: , line:917:42, endln:917:55 |vpiParent: @@ -109542,7 +109542,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:918:14, endln:918:55 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_constant: , line:918:42, endln:918:55 |vpiParent: @@ -109599,7 +109599,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:920:14, endln:920:55 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_constant: , line:920:42, endln:920:55 |vpiParent: @@ -109656,7 +109656,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:921:14, endln:921:55 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_constant: , line:921:42, endln:921:55 |vpiParent: @@ -109713,7 +109713,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:922:14, endln:922:55 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_constant: , line:922:42, endln:922:55 |vpiParent: @@ -109770,7 +109770,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:923:14, endln:923:55 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_constant: , line:923:42, endln:923:55 |vpiParent: @@ -109827,7 +109827,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:1959:14, endln:1959:41 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_constant: , line:1959:39, endln:1959:41 |vpiParent: @@ -109856,7 +109856,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:1960:14, endln:1960:41 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_constant: , line:1960:39, endln:1960:41 |vpiParent: @@ -109885,7 +109885,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:1961:14, endln:1961:41 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_constant: , line:1961:39, endln:1961:41 |vpiParent: @@ -109914,7 +109914,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:1962:14, endln:1962:40 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_constant: , line:1962:39, endln:1962:40 |vpiParent: @@ -109943,7 +109943,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:1963:14, endln:1963:41 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_constant: , line:1963:39, endln:1963:41 |vpiParent: @@ -109972,7 +109972,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:1964:14, endln:1964:41 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_constant: , line:1964:39, endln:1964:41 |vpiParent: @@ -110001,7 +110001,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:1965:14, endln:1965:41 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_constant: , line:1965:39, endln:1965:41 |vpiParent: @@ -110030,7 +110030,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:1966:14, endln:1966:41 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_constant: , line:1966:39, endln:1966:41 |vpiParent: @@ -110059,7 +110059,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:1967:14, endln:1967:40 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_constant: , line:1967:39, endln:1967:40 |vpiParent: @@ -110088,7 +110088,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:1968:14, endln:1968:40 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_constant: , line:1968:39, endln:1968:40 |vpiParent: @@ -110117,7 +110117,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:1969:14, endln:1969:40 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_constant: , line:1969:39, endln:1969:40 |vpiParent: @@ -110146,7 +110146,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:1970:14, endln:1970:40 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_constant: , line:1970:39, endln:1970:40 |vpiParent: @@ -110175,7 +110175,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:1971:14, endln:1971:40 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_constant: , line:1971:39, endln:1971:40 |vpiParent: @@ -110204,7 +110204,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:1972:14, endln:1972:40 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_constant: , line:1972:39, endln:1972:40 |vpiParent: @@ -110233,7 +110233,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:1973:14, endln:1973:41 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_constant: , line:1973:39, endln:1973:41 |vpiParent: @@ -110262,7 +110262,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:1974:14, endln:1974:41 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_constant: , line:1974:39, endln:1974:41 |vpiParent: @@ -110291,7 +110291,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:1975:14, endln:1975:41 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_constant: , line:1975:39, endln:1975:41 |vpiParent: @@ -110320,7 +110320,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:1976:14, endln:1976:40 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_constant: , line:1976:39, endln:1976:40 |vpiParent: @@ -110349,7 +110349,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:1977:14, endln:1977:40 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_constant: , line:1977:39, endln:1977:40 |vpiParent: @@ -110378,7 +110378,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:1978:14, endln:1978:40 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_constant: , line:1978:39, endln:1978:40 |vpiParent: @@ -110407,7 +110407,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:78:12, endln:78:32 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_constant: , line:78:31, endln:78:32 |vpiParent: @@ -110436,7 +110436,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:79:12, endln:79:32 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_constant: , line:79:31, endln:79:32 |vpiParent: @@ -110465,7 +110465,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:80:12, endln:80:32 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_constant: , line:80:31, endln:80:32 |vpiParent: @@ -110494,7 +110494,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:899:14, endln:899:36 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_constant: , line:899:34, endln:899:36 |vpiParent: @@ -110523,7 +110523,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:900:14, endln:900:36 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_constant: , line:900:34, endln:900:36 |vpiParent: @@ -110552,7 +110552,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:902:13, endln:902:44 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_constant: , line:902:43, endln:902:44 |vpiParent: @@ -110580,7 +110580,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:903:13, endln:903:38 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_constant: , line:903:36, endln:903:38 |vpiParent: @@ -110608,7 +110608,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:904:13, endln:904:40 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_constant: , line:904:38, endln:904:40 |vpiParent: @@ -110636,7 +110636,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:905:13, endln:905:40 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_constant: , line:905:38, endln:905:40 |vpiParent: @@ -110664,7 +110664,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:906:13, endln:906:38 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_constant: , line:906:36, endln:906:38 |vpiParent: @@ -110692,7 +110692,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:907:13, endln:907:44 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_constant: , line:907:40, endln:907:44 |vpiParent: @@ -110720,7 +110720,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:908:13, endln:908:114 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_constant: , line:908:41, endln:908:72 |vpiParent: @@ -110748,7 +110748,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:910:13, endln:910:41 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_constant: , line:910:40, endln:910:41 |vpiParent: @@ -110776,7 +110776,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:911:13, endln:911:40 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_constant: , line:911:39, endln:911:40 |vpiParent: @@ -110804,7 +110804,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:913:14, endln:913:55 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_constant: , line:913:42, endln:913:55 |vpiParent: @@ -110861,7 +110861,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:915:14, endln:915:55 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_constant: , line:915:42, endln:915:55 |vpiParent: @@ -110918,7 +110918,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:916:14, endln:916:55 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_constant: , line:916:42, endln:916:55 |vpiParent: @@ -110975,7 +110975,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:917:14, endln:917:55 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_constant: , line:917:42, endln:917:55 |vpiParent: @@ -111032,7 +111032,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:918:14, endln:918:55 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_constant: , line:918:42, endln:918:55 |vpiParent: @@ -111089,7 +111089,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:920:14, endln:920:55 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_constant: , line:920:42, endln:920:55 |vpiParent: @@ -111146,7 +111146,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:921:14, endln:921:55 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_constant: , line:921:42, endln:921:55 |vpiParent: @@ -111203,7 +111203,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:922:14, endln:922:55 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_constant: , line:922:42, endln:922:55 |vpiParent: @@ -111260,7 +111260,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:923:14, endln:923:55 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_constant: , line:923:42, endln:923:55 |vpiParent: @@ -111317,7 +111317,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:5661:14, endln:5661:93 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_operation: , line:5661:41, endln:5661:93 |vpiParent: @@ -111372,7 +111372,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:5662:14, endln:5662:93 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_operation: , line:5662:41, endln:5662:93 |vpiParent: @@ -111427,7 +111427,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6092:26, endln:6092:56 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_ref_obj: (e_bp_default_cfg), line:6092:40, endln:6092:56 |vpiName:e_bp_default_cfg @@ -111438,7 +111438,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6094:32, endln:6094:72 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_bit_select: (all_cfgs_gp), line:6094:48, endln:6094:72 |vpiParent: @@ -111456,7 +111456,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6096:16, endln:6096:53 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_hier_path: (proc_param_lp.multicore), line:6096:30, endln:6096:53 |vpiName:proc_param_lp.multicore @@ -111473,7 +111473,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6098:16, endln:6098:52 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_hier_path: (proc_param_lp.cc_x_dim), line:6098:30, endln:6098:52 |vpiName:proc_param_lp.cc_x_dim @@ -111490,7 +111490,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6099:16, endln:6099:52 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_hier_path: (proc_param_lp.cc_y_dim), line:6099:30, endln:6099:52 |vpiName:proc_param_lp.cc_y_dim @@ -111507,7 +111507,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6101:16, endln:6101:39 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_ref_obj: (cc_x_dim_p), line:6101:29, endln:6101:39 |vpiName:cc_x_dim_p @@ -111516,7 +111516,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6102:16, endln:6102:51 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_hier_path: (proc_param_lp.ic_y_dim), line:6102:29, endln:6102:51 |vpiName:proc_param_lp.ic_y_dim @@ -111533,7 +111533,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6103:16, endln:6103:39 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_ref_obj: (cc_x_dim_p), line:6103:29, endln:6103:39 |vpiName:cc_x_dim_p @@ -111542,7 +111542,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6104:16, endln:6104:51 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_hier_path: (proc_param_lp.mc_y_dim), line:6104:29, endln:6104:51 |vpiName:proc_param_lp.mc_y_dim @@ -111559,7 +111559,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6105:16, endln:6105:53 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_hier_path: (proc_param_lp.cac_x_dim), line:6105:30, endln:6105:53 |vpiName:proc_param_lp.cac_x_dim @@ -111576,7 +111576,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6106:16, endln:6106:40 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_ref_obj: (cc_y_dim_p), line:6106:30, endln:6106:40 |vpiName:cc_y_dim_p @@ -111585,7 +111585,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6107:16, endln:6107:53 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_hier_path: (proc_param_lp.sac_x_dim), line:6107:30, endln:6107:53 |vpiName:proc_param_lp.sac_x_dim @@ -111602,7 +111602,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6108:16, endln:6108:40 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_ref_obj: (cc_y_dim_p), line:6108:30, endln:6108:40 |vpiName:cc_y_dim_p @@ -111611,7 +111611,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6109:16, endln:6109:53 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_hier_path: (proc_param_lp.cacc_type), line:6109:30, endln:6109:53 |vpiName:proc_param_lp.cacc_type @@ -111628,7 +111628,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6110:16, endln:6110:53 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_hier_path: (proc_param_lp.sacc_type), line:6110:30, endln:6110:53 |vpiName:proc_param_lp.sacc_type @@ -111645,7 +111645,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6112:16, endln:6112:53 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_operation: , line:6112:30, endln:6112:53 |vpiOpType:25 @@ -111664,7 +111664,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6113:16, endln:6113:53 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_operation: , line:6113:30, endln:6113:53 |vpiOpType:25 @@ -111683,7 +111683,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6114:16, endln:6114:53 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_operation: , line:6114:30, endln:6114:53 |vpiOpType:25 @@ -111702,7 +111702,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6115:16, endln:6115:55 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_operation: , line:6115:30, endln:6115:55 |vpiOpType:25 @@ -111721,7 +111721,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6116:16, endln:6116:55 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_operation: , line:6116:30, endln:6116:55 |vpiOpType:25 @@ -111740,7 +111740,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6118:16, endln:6118:49 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_hier_path: (proc_param_lp.num_cce), line:6118:28, endln:6118:49 |vpiName:proc_param_lp.num_cce @@ -111757,7 +111757,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6119:16, endln:6119:49 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_hier_path: (proc_param_lp.num_lce), line:6119:28, endln:6119:49 |vpiName:proc_param_lp.num_lce @@ -111774,7 +111774,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6121:16, endln:6121:103 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_operation: , line:6121:36, endln:6121:102 |vpiOpType:32 @@ -111839,7 +111839,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6122:16, endln:6122:127 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_operation: , line:6122:36, endln:6122:126 |vpiOpType:32 @@ -112008,7 +112008,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6123:16, endln:6123:127 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_operation: , line:6123:36, endln:6123:126 |vpiOpType:32 @@ -112177,7 +112177,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6125:16, endln:6125:57 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_hier_path: (proc_param_lp.vaddr_width), line:6125:32, endln:6125:57 |vpiName:proc_param_lp.vaddr_width @@ -112194,7 +112194,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6126:16, endln:6126:57 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_hier_path: (proc_param_lp.paddr_width), line:6126:32, endln:6126:57 |vpiName:proc_param_lp.paddr_width @@ -112211,7 +112211,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6127:16, endln:6127:56 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_hier_path: (proc_param_lp.asid_width), line:6127:32, endln:6127:56 |vpiName:proc_param_lp.asid_width @@ -112228,7 +112228,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6129:16, endln:6129:55 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_hier_path: (proc_param_lp.boot_pc), line:6129:34, endln:6129:55 |vpiName:proc_param_lp.boot_pc @@ -112245,7 +112245,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6130:16, endln:6130:61 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_hier_path: (proc_param_lp.boot_in_debug), line:6130:34, endln:6130:61 |vpiName:proc_param_lp.boot_in_debug @@ -112262,7 +112262,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6132:16, endln:6132:85 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_hier_path: (proc_param_lp.branch_metadata_fwd_width), line:6132:46, endln:6132:85 |vpiName:proc_param_lp.branch_metadata_fwd_width @@ -112279,7 +112279,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6133:16, endln:6133:73 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_hier_path: (proc_param_lp.btb_tag_width), line:6133:46, endln:6133:73 |vpiName:proc_param_lp.btb_tag_width @@ -112296,7 +112296,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6134:16, endln:6134:73 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_hier_path: (proc_param_lp.btb_idx_width), line:6134:46, endln:6134:73 |vpiName:proc_param_lp.btb_idx_width @@ -112313,7 +112313,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6135:16, endln:6135:73 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_hier_path: (proc_param_lp.bht_idx_width), line:6135:46, endln:6135:73 |vpiName:proc_param_lp.bht_idx_width @@ -112330,7 +112330,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6136:16, endln:6136:71 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_hier_path: (proc_param_lp.ghist_width), line:6136:46, endln:6136:71 |vpiName:proc_param_lp.ghist_width @@ -112347,7 +112347,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6138:16, endln:6138:64 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_hier_path: (proc_param_lp.itlb_els), line:6138:42, endln:6138:64 |vpiName:proc_param_lp.itlb_els @@ -112364,7 +112364,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6139:16, endln:6139:64 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_hier_path: (proc_param_lp.dtlb_els), line:6139:42, endln:6139:64 |vpiName:proc_param_lp.dtlb_els @@ -112381,7 +112381,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6141:16, endln:6141:64 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_hier_path: (proc_param_lp.lr_sc), line:6141:45, endln:6141:64 |vpiName:proc_param_lp.lr_sc @@ -112398,7 +112398,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6142:16, endln:6142:67 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_hier_path: (proc_param_lp.amo_swap), line:6142:45, endln:6142:67 |vpiName:proc_param_lp.amo_swap @@ -112415,7 +112415,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6143:16, endln:6143:74 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_hier_path: (proc_param_lp.amo_fetch_logic), line:6143:45, endln:6143:74 |vpiName:proc_param_lp.amo_fetch_logic @@ -112432,7 +112432,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6144:16, endln:6144:79 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_hier_path: (proc_param_lp.amo_fetch_arithmetic), line:6144:45, endln:6144:79 |vpiName:proc_param_lp.amo_fetch_arithmetic @@ -112449,7 +112449,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6146:16, endln:6146:70 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_hier_path: (proc_param_lp.l1_coherent), line:6146:45, endln:6146:70 |vpiName:proc_param_lp.l1_coherent @@ -112466,7 +112466,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6147:16, endln:6147:74 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_hier_path: (proc_param_lp.l1_writethrough), line:6147:45, endln:6147:74 |vpiName:proc_param_lp.l1_writethrough @@ -112483,7 +112483,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6148:16, endln:6148:70 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_hier_path: (proc_param_lp.dcache_sets), line:6148:45, endln:6148:70 |vpiName:proc_param_lp.dcache_sets @@ -112500,7 +112500,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6149:16, endln:6149:71 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_hier_path: (proc_param_lp.dcache_assoc), line:6149:45, endln:6149:71 |vpiName:proc_param_lp.dcache_assoc @@ -112517,7 +112517,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6150:16, endln:6150:77 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_hier_path: (proc_param_lp.dcache_block_width), line:6150:45, endln:6150:77 |vpiName:proc_param_lp.dcache_block_width @@ -112534,7 +112534,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6151:16, endln:6151:76 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_hier_path: (proc_param_lp.dcache_fill_width), line:6151:45, endln:6151:76 |vpiName:proc_param_lp.dcache_fill_width @@ -112551,7 +112551,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6152:16, endln:6152:70 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_hier_path: (proc_param_lp.icache_sets), line:6152:45, endln:6152:70 |vpiName:proc_param_lp.icache_sets @@ -112568,7 +112568,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6153:16, endln:6153:71 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_hier_path: (proc_param_lp.icache_assoc), line:6153:45, endln:6153:71 |vpiName:proc_param_lp.icache_assoc @@ -112585,7 +112585,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6154:16, endln:6154:77 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_hier_path: (proc_param_lp.icache_block_width), line:6154:45, endln:6154:77 |vpiName:proc_param_lp.icache_block_width @@ -112602,7 +112602,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6155:16, endln:6155:76 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_hier_path: (proc_param_lp.icache_fill_width), line:6155:45, endln:6155:76 |vpiName:proc_param_lp.icache_fill_width @@ -112619,7 +112619,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6156:16, endln:6156:70 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_hier_path: (proc_param_lp.acache_sets), line:6156:45, endln:6156:70 |vpiName:proc_param_lp.acache_sets @@ -112636,7 +112636,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6157:16, endln:6157:71 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_hier_path: (proc_param_lp.acache_assoc), line:6157:45, endln:6157:71 |vpiName:proc_param_lp.acache_assoc @@ -112653,7 +112653,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6158:16, endln:6158:77 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_hier_path: (proc_param_lp.acache_block_width), line:6158:45, endln:6158:77 |vpiName:proc_param_lp.acache_block_width @@ -112670,7 +112670,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6159:16, endln:6159:76 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_hier_path: (proc_param_lp.acache_fill_width), line:6159:45, endln:6159:76 |vpiName:proc_param_lp.acache_fill_width @@ -112687,7 +112687,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6160:16, endln:6162:131 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_operation: , line:6160:46, endln:6162:130 |vpiOpType:32 @@ -112771,7 +112771,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6164:16, endln:6164:94 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_operation: , line:6164:47, endln:6164:93 |vpiOpType:32 @@ -112816,7 +112816,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6165:16, endln:6167:127 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_operation: , line:6165:46, endln:6167:126 |vpiOpType:32 @@ -112900,7 +112900,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6169:16, endln:6169:92 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_operation: , line:6169:47, endln:6169:91 |vpiOpType:32 @@ -112945,7 +112945,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6171:16, endln:6179:3 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_operation: , line:6171:47, endln:6179:2 |vpiOpType:32 @@ -113029,7 +113029,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6183:16, endln:6183:71 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_hier_path: (proc_param_lp.cce_pc_width), line:6183:45, endln:6183:71 |vpiName:proc_param_lp.cce_pc_width @@ -113046,7 +113046,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6184:16, endln:6184:62 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_operation: , line:6184:45, endln:6184:62 |vpiOpType:43 @@ -113068,7 +113068,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6185:16, endln:6185:116 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_operation: , line:6185:46, endln:6185:115 |vpiOpType:32 @@ -113102,7 +113102,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6186:16, endln:6186:47 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_constant: , line:6186:45, endln:6186:47 |vpiDecompile:34 @@ -113116,7 +113116,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6187:16, endln:6187:68 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_hier_path: (proc_param_lp.cce_ucode), line:6187:45, endln:6187:68 |vpiName:proc_param_lp.cce_ucode @@ -113133,7 +113133,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6189:16, endln:6189:48 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_hier_path: (proc_param_lp.l2_en), line:6189:29, endln:6189:48 |vpiName:proc_param_lp.l2_en @@ -113150,7 +113150,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6190:16, endln:6190:50 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_hier_path: (proc_param_lp.l2_sets), line:6190:29, endln:6190:50 |vpiName:proc_param_lp.l2_sets @@ -113167,7 +113167,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6191:16, endln:6191:51 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_hier_path: (proc_param_lp.l2_assoc), line:6191:29, endln:6191:51 |vpiName:proc_param_lp.l2_assoc @@ -113184,7 +113184,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6192:16, endln:6192:73 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_hier_path: (proc_param_lp.l2_outstanding_reqs), line:6192:40, endln:6192:73 |vpiName:proc_param_lp.l2_outstanding_reqs @@ -113201,7 +113201,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6194:16, endln:6194:69 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_hier_path: (proc_param_lp.fe_queue_fifo_els), line:6194:38, endln:6194:69 |vpiName:proc_param_lp.fe_queue_fifo_els @@ -113218,7 +113218,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6195:16, endln:6195:67 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_hier_path: (proc_param_lp.fe_cmd_fifo_els), line:6195:38, endln:6195:67 |vpiName:proc_param_lp.fe_cmd_fifo_els @@ -113235,7 +113235,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6197:16, endln:6197:68 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_hier_path: (proc_param_lp.async_coh_clk), line:6197:41, endln:6197:68 |vpiName:proc_param_lp.async_coh_clk @@ -113252,7 +113252,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6198:16, endln:6198:74 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_hier_path: (proc_param_lp.coh_noc_max_credits), line:6198:41, endln:6198:74 |vpiName:proc_param_lp.coh_noc_max_credits @@ -113269,7 +113269,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6199:16, endln:6199:73 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_hier_path: (proc_param_lp.coh_noc_flit_width), line:6199:41, endln:6199:73 |vpiName:proc_param_lp.coh_noc_flit_width @@ -113286,7 +113286,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6200:16, endln:6200:72 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_hier_path: (proc_param_lp.coh_noc_cid_width), line:6200:41, endln:6200:72 |vpiName:proc_param_lp.coh_noc_cid_width @@ -113303,7 +113303,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6201:16, endln:6201:72 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_hier_path: (proc_param_lp.coh_noc_len_width), line:6201:41, endln:6201:72 |vpiName:proc_param_lp.coh_noc_len_width @@ -113320,7 +113320,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6202:16, endln:6202:136 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_operation: , line:6202:43, endln:6202:135 |vpiOpType:32 @@ -113431,7 +113431,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6203:16, endln:6203:140 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_operation: , line:6203:43, endln:6203:139 |vpiOpType:32 @@ -113542,7 +113542,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6204:16, endln:6204:42 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_constant: , line:6204:41, endln:6204:42 |vpiDecompile:2 @@ -113556,7 +113556,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6205:16, endln:6205:61 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_operation: , line:6205:41, endln:6205:61 |vpiOpType:24 @@ -113591,7 +113591,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6206:16, endln:6206:42 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_constant: , line:6206:41, endln:6206:42 |vpiDecompile:0 @@ -113605,7 +113605,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6207:20, endln:6209:84 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_operation: , line:6207:67, endln:6209:84 |vpiOpType:32 @@ -113681,7 +113681,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6210:16, endln:6210:83 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_bit_select: (coh_noc_cord_markers_pos_p), line:6210:41, endln:6210:83 |vpiParent: @@ -113699,7 +113699,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6212:16, endln:6212:71 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_hier_path: (proc_param_lp.async_mem_clk), line:6212:44, endln:6212:71 |vpiName:proc_param_lp.async_mem_clk @@ -113716,7 +113716,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6213:16, endln:6213:77 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_hier_path: (proc_param_lp.mem_noc_max_credits), line:6213:44, endln:6213:77 |vpiName:proc_param_lp.mem_noc_max_credits @@ -113733,7 +113733,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6214:16, endln:6214:76 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_hier_path: (proc_param_lp.mem_noc_flit_width), line:6214:44, endln:6214:76 |vpiName:proc_param_lp.mem_noc_flit_width @@ -113750,7 +113750,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6215:16, endln:6215:75 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_hier_path: (proc_param_lp.mem_noc_cid_width), line:6215:44, endln:6215:75 |vpiName:proc_param_lp.mem_noc_cid_width @@ -113767,7 +113767,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6216:16, endln:6216:75 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_hier_path: (proc_param_lp.mem_noc_len_width), line:6216:44, endln:6216:75 |vpiName:proc_param_lp.mem_noc_len_width @@ -113784,7 +113784,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6217:16, endln:6217:139 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_operation: , line:6217:46, endln:6217:138 |vpiOpType:32 @@ -113895,7 +113895,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6218:16, endln:6218:45 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_constant: , line:6218:44, endln:6218:45 |vpiDecompile:0 @@ -113909,7 +113909,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6219:16, endln:6219:45 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_constant: , line:6219:44, endln:6219:45 |vpiDecompile:1 @@ -113923,7 +113923,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6220:16, endln:6220:45 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_constant: , line:6220:44, endln:6220:45 |vpiDecompile:2 @@ -113937,7 +113937,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6221:16, endln:6221:64 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_operation: , line:6221:44, endln:6221:64 |vpiOpType:24 @@ -113972,7 +113972,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6222:16, endln:6222:45 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_constant: , line:6222:44, endln:6222:45 |vpiDecompile:1 @@ -113986,7 +113986,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6223:20, endln:6225:84 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_operation: , line:6223:72, endln:6225:84 |vpiOpType:32 @@ -114062,7 +114062,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6226:16, endln:6226:86 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_bit_select: (mem_noc_cord_markers_pos_p), line:6226:44, endln:6226:86 |vpiParent: @@ -114080,7 +114080,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6228:16, endln:6228:69 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_hier_path: (proc_param_lp.async_io_clk), line:6228:43, endln:6228:69 |vpiName:proc_param_lp.async_io_clk @@ -114097,7 +114097,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6229:16, endln:6229:75 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_hier_path: (proc_param_lp.io_noc_max_credits), line:6229:43, endln:6229:75 |vpiName:proc_param_lp.io_noc_max_credits @@ -114114,7 +114114,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6230:16, endln:6230:73 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_hier_path: (proc_param_lp.io_noc_did_width), line:6230:43, endln:6230:73 |vpiName:proc_param_lp.io_noc_did_width @@ -114131,7 +114131,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6231:16, endln:6231:74 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_hier_path: (proc_param_lp.io_noc_flit_width), line:6231:43, endln:6231:74 |vpiName:proc_param_lp.io_noc_flit_width @@ -114148,7 +114148,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6232:16, endln:6232:73 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_hier_path: (proc_param_lp.io_noc_cid_width), line:6232:43, endln:6232:73 |vpiName:proc_param_lp.io_noc_cid_width @@ -114165,7 +114165,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6233:16, endln:6233:73 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_hier_path: (proc_param_lp.io_noc_len_width), line:6233:43, endln:6233:73 |vpiName:proc_param_lp.io_noc_len_width @@ -114182,7 +114182,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6234:16, endln:6234:44 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_constant: , line:6234:43, endln:6234:44 |vpiDecompile:0 @@ -114196,7 +114196,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6235:16, endln:6235:61 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_ref_obj: (io_noc_did_width_p), line:6235:43, endln:6235:61 |vpiName:io_noc_did_width_p @@ -114205,7 +114205,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6236:16, endln:6236:44 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_constant: , line:6236:43, endln:6236:44 |vpiDecompile:1 @@ -114219,7 +114219,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6237:16, endln:6237:44 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_constant: , line:6237:43, endln:6237:44 |vpiDecompile:2 @@ -114233,7 +114233,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6238:16, endln:6238:67 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_operation: , line:6238:43, endln:6238:67 |vpiOpType:24 @@ -114268,7 +114268,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6239:16, endln:6239:44 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_constant: , line:6239:43, endln:6239:44 |vpiDecompile:0 @@ -114282,7 +114282,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6240:20, endln:6242:81 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_operation: , line:6240:70, endln:6242:81 |vpiOpType:32 @@ -114358,7 +114358,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6243:16, endln:6243:83 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_bit_select: (io_noc_cord_markers_pos_p), line:6243:43, endln:6243:83 |vpiParent: @@ -114376,7 +114376,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6245:16, endln:6245:40 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_constant: , line:6245:38, endln:6245:40 |vpiDecompile:64 @@ -114390,7 +114390,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6246:16, endln:6246:40 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_constant: , line:6246:38, endln:6246:40 |vpiDecompile:32 @@ -114404,7 +114404,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6247:16, endln:6247:40 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_constant: , line:6247:38, endln:6247:40 |vpiDecompile:32 @@ -114418,7 +114418,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6248:16, endln:6248:40 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_constant: , line:6248:38, endln:6248:40 |vpiDecompile:12 @@ -114432,7 +114432,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6249:16, endln:6249:39 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_constant: , line:6249:38, endln:6249:39 |vpiDecompile:5 @@ -114446,7 +114446,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6250:16, endln:6250:40 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_constant: , line:6250:38, endln:6250:40 |vpiDecompile:12 @@ -114460,7 +114460,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6252:16, endln:6252:79 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_operation: , line:6252:32, endln:6252:79 |vpiOpType:11 @@ -114487,7 +114487,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6253:16, endln:6253:79 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_operation: , line:6253:32, endln:6253:79 |vpiOpType:11 @@ -114514,7 +114514,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6256:16, endln:6275:5 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_operation: , line:6257:4, endln:6273:5 |vpiOpType:24 @@ -114640,7 +114640,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6277:16, endln:6381:5 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_operation: , line:6278:4, endln:6379:5 |vpiOpType:24 @@ -115334,7 +115334,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6386:16, endln:6387:94 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_operation: , line:6387:4, endln:6387:93 |vpiOpType:24 @@ -115415,7 +115415,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6391:16, endln:6392:96 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_operation: , line:6392:4, endln:6392:95 |vpiOpType:24 @@ -115468,7 +115468,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6396:16, endln:6399:20 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_operation: , line:6398:3, endln:6399:19 |vpiOpType:24 @@ -115531,7 +115531,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6405:16, endln:6405:47 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_constant: , line:6405:46, endln:6405:47 |vpiDecompile:0 @@ -115545,7 +115545,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6406:16, endln:6406:47 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_constant: , line:6406:46, endln:6406:47 |vpiDecompile:0 @@ -115559,7 +115559,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6407:16, endln:6407:47 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_constant: , line:6407:46, endln:6407:47 |vpiDecompile:0 @@ -115573,7 +115573,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6408:16, endln:6408:47 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_constant: , line:6408:46, endln:6408:47 |vpiDecompile:0 @@ -115587,7 +115587,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6409:16, endln:6409:47 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_constant: , line:6409:46, endln:6409:47 |vpiDecompile:0 @@ -115601,7 +115601,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6410:16, endln:6410:47 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_constant: , line:6410:46, endln:6410:47 |vpiDecompile:0 @@ -115615,7 +115615,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6411:16, endln:6411:47 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_constant: , line:6411:46, endln:6411:47 |vpiDecompile:0 @@ -115629,7 +115629,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6412:16, endln:6412:47 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_constant: , line:6412:46, endln:6412:47 |vpiDecompile:0 @@ -115643,7 +115643,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6413:16, endln:6413:47 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_constant: , line:6413:46, endln:6413:47 |vpiDecompile:0 @@ -115657,7 +115657,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6414:16, endln:6414:47 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_constant: , line:6414:46, endln:6414:47 |vpiDecompile:0 @@ -115671,7 +115671,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6415:16, endln:6415:47 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_constant: , line:6415:46, endln:6415:47 |vpiDecompile:0 @@ -115685,7 +115685,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6418:16, endln:6418:47 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_constant: , line:6418:46, endln:6418:47 |vpiDecompile:0 @@ -115699,7 +115699,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6419:16, endln:6419:47 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_constant: , line:6419:46, endln:6419:47 |vpiDecompile:0 @@ -115713,7 +115713,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6420:16, endln:6420:56 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_constant: , line:6420:46, endln:6420:56 |vpiDecompile:prog.cfg @@ -115727,7 +115727,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6421:16, endln:6421:47 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_constant: , line:6421:46, endln:6421:47 |vpiDecompile:0 @@ -115741,7 +115741,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6422:16, endln:6422:47 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_constant: , line:6422:46, endln:6422:47 |vpiDecompile:0 @@ -115755,7 +115755,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6425:16, endln:6425:47 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_constant: , line:6425:46, endln:6425:47 |vpiDecompile:0 @@ -115769,7 +115769,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6426:16, endln:6426:47 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_constant: , line:6426:46, endln:6426:47 |vpiDecompile:0 @@ -115783,7 +115783,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6427:16, endln:6427:47 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_constant: , line:6427:46, endln:6427:47 |vpiDecompile:0 @@ -115797,7 +115797,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6428:16, endln:6428:47 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_constant: , line:6428:46, endln:6428:47 |vpiDecompile:0 @@ -115811,7 +115811,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6429:36, endln:6429:68 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_constant: , line:6429:51, endln:6429:68 |vpiDecompile:32'h8000_0000 @@ -115825,7 +115825,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6430:16, endln:6430:42 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_operation: , line:6430:37, endln:6430:42 |vpiOpType:43 @@ -115850,7 +115850,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6431:16, endln:6431:47 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_constant: , line:6431:37, endln:6431:47 |vpiDecompile:prog.mem @@ -116155,31 +116155,31 @@ design: (work@testbench) |vpiNet: \_logic_net: (work@testbench.clk_i), line:6433:10, endln:6433:15 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiName:clk_i |vpiFullName:work@testbench.clk_i |vpiNet: \_logic_net: (work@testbench.reset_i), line:6434:12, endln:6434:19 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiName:reset_i |vpiFullName:work@testbench.reset_i |vpiNet: \_logic_net: (work@testbench.dram_clk_i), line:6435:12, endln:6435:22 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiName:dram_clk_i |vpiFullName:work@testbench.dram_clk_i |vpiNet: \_logic_net: (work@testbench.dram_reset_i), line:6436:12, endln:6436:24 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiName:dram_reset_i |vpiFullName:work@testbench.dram_reset_i |vpiPort: \_port: (clk_i), line:6433:10, endln:6433:15 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiName:clk_i |vpiDirection:1 |vpiLowConn: @@ -116191,7 +116191,7 @@ design: (work@testbench) |vpiPort: \_port: (reset_i), line:6434:12, endln:6434:19 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiName:reset_i |vpiDirection:1 |vpiLowConn: @@ -116203,7 +116203,7 @@ design: (work@testbench) |vpiPort: \_port: (dram_clk_i), line:6435:12, endln:6435:22 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiName:dram_clk_i |vpiDirection:1 |vpiLowConn: @@ -116215,7 +116215,7 @@ design: (work@testbench) |vpiPort: \_port: (dram_reset_i), line:6436:12, endln:6436:24 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiName:dram_reset_i |vpiDirection:1 |vpiLowConn: @@ -116225,12 +116225,12 @@ design: (work@testbench) |vpiTypedef: \_logic_typespec: , line:6436:12, endln:6436:12 |uhdmtopModules: -\_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 +\_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiName:work@testbench |vpiParameter: \_parameter: (work@testbench.bp_data_cmd_num_flit_gp), line:911:13, endln:911:36 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |UINT:4 |vpiTypespec: \_int_typespec: @@ -116242,7 +116242,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.bp_data_resp_num_flit_gp), line:910:13, endln:910:37 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |UINT:4 |vpiTypespec: \_int_typespec: @@ -116254,7 +116254,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.bp_eaddr_width_gp), line:899:14, endln:899:31 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |UINT:64 |vpiTypespec: \_int_typespec: @@ -116267,7 +116267,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.bp_instr_width_gp), line:900:14, endln:900:31 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |UINT:32 |vpiTypespec: \_int_typespec: @@ -116280,7 +116280,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.bp_log_file_gp), line:80:12, endln:80:26 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |UINT:2 |vpiTypespec: \_int_typespec: @@ -116293,7 +116293,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.bp_log_none_gp), line:78:12, endln:78:26 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |UINT:0 |vpiTypespec: \_int_typespec: @@ -116306,7 +116306,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.bp_log_stdout_gp), line:79:12, endln:79:28 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |UINT:1 |vpiTypespec: \_int_typespec: @@ -116319,7 +116319,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.bp_page_offset_width_gp), line:908:13, endln:908:36 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |INT:12 |vpiTypespec: \_int_typespec: @@ -116331,7 +116331,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.bp_page_size_in_bytes_gp), line:907:13, endln:907:37 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |UINT:4096 |vpiTypespec: \_int_typespec: @@ -116343,7 +116343,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.bp_sv39_paddr_width_gp), line:905:13, endln:905:35 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |UINT:56 |vpiTypespec: \_int_typespec: @@ -116355,7 +116355,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.bp_sv39_page_table_depth_gp), line:902:13, endln:902:40 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |UINT:3 |vpiTypespec: \_int_typespec: @@ -116367,7 +116367,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.bp_sv39_ppn_width_gp), line:906:13, endln:906:33 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |UINT:44 |vpiTypespec: \_int_typespec: @@ -116379,7 +116379,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.bp_sv39_pte_width_gp), line:903:13, endln:903:33 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |UINT:64 |vpiTypespec: \_int_typespec: @@ -116391,7 +116391,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.bp_sv39_vaddr_width_gp), line:904:13, endln:904:35 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |UINT:39 |vpiTypespec: \_int_typespec: @@ -116403,7 +116403,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.cfg_link_dev_base_addr_gp), line:915:14, endln:915:39 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |HEX:01?????? |vpiTypespec: \_int_typespec: @@ -116430,7 +116430,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.clint_dev_base_addr_gp), line:916:14, endln:916:36 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |HEX:02?????? |vpiTypespec: \_int_typespec: @@ -116457,7 +116457,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.dram_base_addr_gp), line:913:14, endln:913:31 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |HEX:80000000 |vpiTypespec: \_int_typespec: @@ -116484,7 +116484,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.host_dev_base_addr_gp), line:917:14, endln:917:35 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |HEX:03?????? |vpiTypespec: \_int_typespec: @@ -116511,7 +116511,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.mipi_reg_base_addr_gp), line:920:14, endln:920:35 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |HEX:02000??? |vpiTypespec: \_int_typespec: @@ -116538,7 +116538,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.mtime_reg_addr_gp), line:922:14, endln:922:31 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |HEX:0200bff8 |vpiTypespec: \_int_typespec: @@ -116565,7 +116565,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.mtimecmp_reg_base_addr_gp), line:921:14, endln:921:39 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |HEX:02004??? |vpiTypespec: \_int_typespec: @@ -116592,7 +116592,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.plic_dev_base_addr_gp), line:918:14, endln:918:35 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |HEX:0c?????? |vpiTypespec: \_int_typespec: @@ -116619,7 +116619,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.plic_reg_base_addr_gp), line:923:14, endln:923:35 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |HEX:0c000??? |vpiTypespec: \_int_typespec: @@ -116646,7 +116646,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.all_cfgs_gp), line:2516:44, endln:2516:55 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiTypespec: \_packed_array_typespec: , line:2516:13, endln:2516:28 |vpiParent: @@ -117367,7 +117367,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.bp_dual_core_cfg_p), line:2300:30, endln:2300:48 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiTypespec: \_struct_typespec: (bp_common_aviary_pkg::bp_proc_param_s), line:2062:9, endln:2062:15 |vpiParent: @@ -118063,7 +118063,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.bp_half_core_cfg_p), line:2198:30, endln:2198:48 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiTypespec: \_struct_typespec: (bp_common_aviary_pkg::bp_proc_param_s), line:2062:9, endln:2062:15 |vpiParent: @@ -118759,7 +118759,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.bp_inv_cfg_p), line:2195:30, endln:2195:42 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiTypespec: \_struct_typespec: (bp_common_aviary_pkg::bp_proc_param_s), line:2062:9, endln:2062:15 |vpiParent: @@ -119455,7 +119455,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.bp_oct_core_cfg_p), line:2402:30, endln:2402:47 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiTypespec: \_struct_typespec: (bp_common_aviary_pkg::bp_proc_param_s), line:2062:9, endln:2062:15 |vpiParent: @@ -120151,7 +120151,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.bp_quad_core_cfg_p), line:2351:30, endln:2351:48 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiTypespec: \_struct_typespec: (bp_common_aviary_pkg::bp_proc_param_s), line:2062:9, endln:2062:15 |vpiParent: @@ -120847,7 +120847,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.bp_sexta_core_cfg_p), line:2453:30, endln:2453:49 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiTypespec: \_struct_typespec: (bp_common_aviary_pkg::bp_proc_param_s), line:2062:9, endln:2062:15 |vpiParent: @@ -121543,7 +121543,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.bp_single_core_cfg_p), line:2249:30, endln:2249:50 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiTypespec: \_struct_typespec: (bp_common_aviary_pkg::bp_proc_param_s), line:2062:9, endln:2062:15 |vpiParent: @@ -122239,7 +122239,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.lg_max_cfgs), line:2193:14, endln:2193:25 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |INT:7 |vpiTypespec: \_int_typespec: @@ -122252,7 +122252,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.max_cfgs), line:2192:14, endln:2192:22 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |UINT:128 |vpiTypespec: \_int_typespec: @@ -122265,7 +122265,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.bp_data_cmd_num_flit_gp), line:911:13, endln:911:36 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |UINT:4 |vpiTypespec: \_int_typespec: @@ -122277,7 +122277,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.bp_data_resp_num_flit_gp), line:910:13, endln:910:37 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |UINT:4 |vpiTypespec: \_int_typespec: @@ -122289,7 +122289,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.bp_eaddr_width_gp), line:899:14, endln:899:31 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |UINT:64 |vpiTypespec: \_int_typespec: @@ -122302,7 +122302,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.bp_instr_width_gp), line:900:14, endln:900:31 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |UINT:32 |vpiTypespec: \_int_typespec: @@ -122315,7 +122315,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.bp_log_file_gp), line:80:12, endln:80:26 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |UINT:2 |vpiTypespec: \_int_typespec: @@ -122328,7 +122328,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.bp_log_none_gp), line:78:12, endln:78:26 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |UINT:0 |vpiTypespec: \_int_typespec: @@ -122341,7 +122341,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.bp_log_stdout_gp), line:79:12, endln:79:28 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |UINT:1 |vpiTypespec: \_int_typespec: @@ -122354,7 +122354,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.bp_page_offset_width_gp), line:908:13, endln:908:36 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |INT:12 |vpiTypespec: \_int_typespec: @@ -122366,7 +122366,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.bp_page_size_in_bytes_gp), line:907:13, endln:907:37 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |UINT:4096 |vpiTypespec: \_int_typespec: @@ -122378,7 +122378,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.bp_sv39_paddr_width_gp), line:905:13, endln:905:35 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |UINT:56 |vpiTypespec: \_int_typespec: @@ -122390,7 +122390,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.bp_sv39_page_table_depth_gp), line:902:13, endln:902:40 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |UINT:3 |vpiTypespec: \_int_typespec: @@ -122402,7 +122402,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.bp_sv39_ppn_width_gp), line:906:13, endln:906:33 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |UINT:44 |vpiTypespec: \_int_typespec: @@ -122414,7 +122414,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.bp_sv39_pte_width_gp), line:903:13, endln:903:33 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |UINT:64 |vpiTypespec: \_int_typespec: @@ -122426,7 +122426,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.bp_sv39_vaddr_width_gp), line:904:13, endln:904:35 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |UINT:39 |vpiTypespec: \_int_typespec: @@ -122438,7 +122438,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.cfg_link_dev_base_addr_gp), line:915:14, endln:915:39 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |HEX:01?????? |vpiTypespec: \_int_typespec: @@ -122465,7 +122465,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.clint_dev_base_addr_gp), line:916:14, endln:916:36 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |HEX:02?????? |vpiTypespec: \_int_typespec: @@ -122492,7 +122492,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.dram_base_addr_gp), line:913:14, endln:913:31 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |HEX:80000000 |vpiTypespec: \_int_typespec: @@ -122519,7 +122519,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.host_dev_base_addr_gp), line:917:14, endln:917:35 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |HEX:03?????? |vpiTypespec: \_int_typespec: @@ -122546,7 +122546,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.mipi_reg_base_addr_gp), line:920:14, endln:920:35 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |HEX:02000??? |vpiTypespec: \_int_typespec: @@ -122573,7 +122573,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.mtime_reg_addr_gp), line:922:14, endln:922:31 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |HEX:0200bff8 |vpiTypespec: \_int_typespec: @@ -122600,7 +122600,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.mtimecmp_reg_base_addr_gp), line:921:14, endln:921:39 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |HEX:02004??? |vpiTypespec: \_int_typespec: @@ -122627,7 +122627,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.plic_dev_base_addr_gp), line:918:14, endln:918:35 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |HEX:0c?????? |vpiTypespec: \_int_typespec: @@ -122654,7 +122654,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.plic_reg_base_addr_gp), line:923:14, endln:923:35 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |HEX:0c000??? |vpiTypespec: \_int_typespec: @@ -122681,7 +122681,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.rv64_byte_width_gp), line:1962:14, endln:1962:32 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |UINT:8 |vpiTypespec: \_int_typespec: @@ -122694,7 +122694,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.rv64_csr_addr_width_gp), line:1973:14, endln:1973:36 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |UINT:12 |vpiTypespec: \_int_typespec: @@ -122707,7 +122707,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.rv64_dword_width_gp), line:1965:14, endln:1965:33 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |UINT:64 |vpiTypespec: \_int_typespec: @@ -122720,7 +122720,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.rv64_eaddr_width_gp), line:1961:14, endln:1961:33 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |UINT:64 |vpiTypespec: \_int_typespec: @@ -122733,7 +122733,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.rv64_funct3_width_gp), line:1971:14, endln:1971:34 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |UINT:3 |vpiTypespec: \_int_typespec: @@ -122746,7 +122746,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.rv64_funct7_width_gp), line:1972:14, endln:1972:34 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |UINT:7 |vpiTypespec: \_int_typespec: @@ -122759,7 +122759,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.rv64_hword_width_gp), line:1963:14, endln:1963:33 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |UINT:16 |vpiTypespec: \_int_typespec: @@ -122772,7 +122772,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.rv64_imm11to5_width_gp), line:1976:14, endln:1976:36 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |UINT:7 |vpiTypespec: \_int_typespec: @@ -122785,7 +122785,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.rv64_imm12_width_gp), line:1975:14, endln:1975:33 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |UINT:12 |vpiTypespec: \_int_typespec: @@ -122798,7 +122798,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.rv64_imm20_width_gp), line:1974:14, endln:1974:33 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |UINT:20 |vpiTypespec: \_int_typespec: @@ -122811,7 +122811,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.rv64_imm4to0_width_gp), line:1977:14, endln:1977:35 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |UINT:5 |vpiTypespec: \_int_typespec: @@ -122824,7 +122824,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.rv64_instr_width_gp), line:1960:14, endln:1960:33 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |UINT:32 |vpiTypespec: \_int_typespec: @@ -122837,7 +122837,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.rv64_opcode_width_gp), line:1970:14, endln:1970:34 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |UINT:7 |vpiTypespec: \_int_typespec: @@ -122850,7 +122850,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.rv64_priv_width_gp), line:1978:14, endln:1978:32 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |UINT:2 |vpiTypespec: \_int_typespec: @@ -122863,7 +122863,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.rv64_reg_addr_width_gp), line:1967:14, endln:1967:36 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |UINT:5 |vpiTypespec: \_int_typespec: @@ -122876,7 +122876,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.rv64_reg_data_width_gp), line:1966:14, endln:1966:36 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |UINT:64 |vpiTypespec: \_int_typespec: @@ -122889,7 +122889,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.rv64_rf_els_gp), line:1959:14, endln:1959:28 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |UINT:32 |vpiTypespec: \_int_typespec: @@ -122902,7 +122902,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.rv64_shamt_width_gp), line:1968:14, endln:1968:33 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |UINT:6 |vpiTypespec: \_int_typespec: @@ -122915,7 +122915,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.rv64_shamtw_width_gp), line:1969:14, endln:1969:34 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |UINT:5 |vpiTypespec: \_int_typespec: @@ -122928,7 +122928,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.rv64_word_width_gp), line:1964:14, endln:1964:32 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |UINT:32 |vpiTypespec: \_int_typespec: @@ -122941,7 +122941,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.bp_data_cmd_num_flit_gp), line:911:13, endln:911:36 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |UINT:4 |vpiTypespec: \_int_typespec: @@ -122953,7 +122953,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.bp_data_resp_num_flit_gp), line:910:13, endln:910:37 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |UINT:4 |vpiTypespec: \_int_typespec: @@ -122965,7 +122965,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.bp_eaddr_width_gp), line:899:14, endln:899:31 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |UINT:64 |vpiTypespec: \_int_typespec: @@ -122978,7 +122978,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.bp_instr_width_gp), line:900:14, endln:900:31 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |UINT:32 |vpiTypespec: \_int_typespec: @@ -122991,7 +122991,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.bp_log_file_gp), line:80:12, endln:80:26 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |UINT:2 |vpiTypespec: \_int_typespec: @@ -123004,7 +123004,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.bp_log_none_gp), line:78:12, endln:78:26 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |UINT:0 |vpiTypespec: \_int_typespec: @@ -123017,7 +123017,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.bp_log_stdout_gp), line:79:12, endln:79:28 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |UINT:1 |vpiTypespec: \_int_typespec: @@ -123030,7 +123030,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.bp_page_offset_width_gp), line:908:13, endln:908:36 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |INT:12 |vpiTypespec: \_int_typespec: @@ -123042,7 +123042,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.bp_page_size_in_bytes_gp), line:907:13, endln:907:37 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |UINT:4096 |vpiTypespec: \_int_typespec: @@ -123054,7 +123054,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.bp_sv39_paddr_width_gp), line:905:13, endln:905:35 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |UINT:56 |vpiTypespec: \_int_typespec: @@ -123066,7 +123066,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.bp_sv39_page_table_depth_gp), line:902:13, endln:902:40 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |UINT:3 |vpiTypespec: \_int_typespec: @@ -123078,7 +123078,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.bp_sv39_ppn_width_gp), line:906:13, endln:906:33 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |UINT:44 |vpiTypespec: \_int_typespec: @@ -123090,7 +123090,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.bp_sv39_pte_width_gp), line:903:13, endln:903:33 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |UINT:64 |vpiTypespec: \_int_typespec: @@ -123102,7 +123102,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.bp_sv39_vaddr_width_gp), line:904:13, endln:904:35 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |UINT:39 |vpiTypespec: \_int_typespec: @@ -123114,7 +123114,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.cfg_link_dev_base_addr_gp), line:915:14, endln:915:39 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |HEX:01?????? |vpiTypespec: \_int_typespec: @@ -123141,7 +123141,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.clint_dev_base_addr_gp), line:916:14, endln:916:36 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |HEX:02?????? |vpiTypespec: \_int_typespec: @@ -123168,7 +123168,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.dram_base_addr_gp), line:913:14, endln:913:31 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |HEX:80000000 |vpiTypespec: \_int_typespec: @@ -123195,7 +123195,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.host_dev_base_addr_gp), line:917:14, endln:917:35 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |HEX:03?????? |vpiTypespec: \_int_typespec: @@ -123222,7 +123222,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.mem_cmd_payload_mask_gp), line:5661:14, endln:5661:37 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiLocalParam:1 |vpiName:mem_cmd_payload_mask_gp |vpiFullName:work@testbench.mem_cmd_payload_mask_gp @@ -123230,7 +123230,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.mem_resp_payload_mask_gp), line:5662:14, endln:5662:38 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiLocalParam:1 |vpiName:mem_resp_payload_mask_gp |vpiFullName:work@testbench.mem_resp_payload_mask_gp @@ -123238,7 +123238,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.mipi_reg_base_addr_gp), line:920:14, endln:920:35 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |HEX:02000??? |vpiTypespec: \_int_typespec: @@ -123265,7 +123265,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.mtime_reg_addr_gp), line:922:14, endln:922:31 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |HEX:0200bff8 |vpiTypespec: \_int_typespec: @@ -123292,7 +123292,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.mtimecmp_reg_base_addr_gp), line:921:14, endln:921:39 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |HEX:02004??? |vpiTypespec: \_int_typespec: @@ -123319,7 +123319,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.plic_dev_base_addr_gp), line:918:14, endln:918:35 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |HEX:0c?????? |vpiTypespec: \_int_typespec: @@ -123346,7 +123346,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.plic_reg_base_addr_gp), line:923:14, endln:923:35 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |HEX:0c000??? |vpiTypespec: \_int_typespec: @@ -123373,7 +123373,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.bp_params_p), line:6092:26, endln:6092:37 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiTypespec: \_unsupported_typespec: (bp_params_e), line:6092:14, endln:6092:25 |vpiParent: @@ -123384,7 +123384,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.proc_param_lp), line:6094:32, endln:6094:45 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiTypespec: \_struct_typespec: (bp_common_aviary_pkg::bp_proc_param_s), line:2062:9, endln:2062:15 |vpiParent: @@ -124079,434 +124079,434 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.multicore_p), line:6096:16, endln:6096:27 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiLocalParam:1 |vpiName:multicore_p |vpiFullName:work@testbench.multicore_p |vpiParameter: \_parameter: (work@testbench.cc_x_dim_p), line:6098:16, endln:6098:26 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiLocalParam:1 |vpiName:cc_x_dim_p |vpiFullName:work@testbench.cc_x_dim_p |vpiParameter: \_parameter: (work@testbench.cc_y_dim_p), line:6099:16, endln:6099:26 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiLocalParam:1 |vpiName:cc_y_dim_p |vpiFullName:work@testbench.cc_y_dim_p |vpiParameter: \_parameter: (work@testbench.ic_x_dim_p), line:6101:16, endln:6101:26 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiLocalParam:1 |vpiName:ic_x_dim_p |vpiFullName:work@testbench.ic_x_dim_p |vpiParameter: \_parameter: (work@testbench.ic_y_dim_p), line:6102:16, endln:6102:26 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiLocalParam:1 |vpiName:ic_y_dim_p |vpiFullName:work@testbench.ic_y_dim_p |vpiParameter: \_parameter: (work@testbench.mc_x_dim_p), line:6103:16, endln:6103:26 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiLocalParam:1 |vpiName:mc_x_dim_p |vpiFullName:work@testbench.mc_x_dim_p |vpiParameter: \_parameter: (work@testbench.mc_y_dim_p), line:6104:16, endln:6104:26 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiLocalParam:1 |vpiName:mc_y_dim_p |vpiFullName:work@testbench.mc_y_dim_p |vpiParameter: \_parameter: (work@testbench.cac_x_dim_p), line:6105:16, endln:6105:27 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiLocalParam:1 |vpiName:cac_x_dim_p |vpiFullName:work@testbench.cac_x_dim_p |vpiParameter: \_parameter: (work@testbench.cac_y_dim_p), line:6106:16, endln:6106:27 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiLocalParam:1 |vpiName:cac_y_dim_p |vpiFullName:work@testbench.cac_y_dim_p |vpiParameter: \_parameter: (work@testbench.sac_x_dim_p), line:6107:16, endln:6107:27 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiLocalParam:1 |vpiName:sac_x_dim_p |vpiFullName:work@testbench.sac_x_dim_p |vpiParameter: \_parameter: (work@testbench.sac_y_dim_p), line:6108:16, endln:6108:27 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiLocalParam:1 |vpiName:sac_y_dim_p |vpiFullName:work@testbench.sac_y_dim_p |vpiParameter: \_parameter: (work@testbench.cacc_type_p), line:6109:16, endln:6109:27 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiLocalParam:1 |vpiName:cacc_type_p |vpiFullName:work@testbench.cacc_type_p |vpiParameter: \_parameter: (work@testbench.sacc_type_p), line:6110:16, endln:6110:27 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiLocalParam:1 |vpiName:sacc_type_p |vpiFullName:work@testbench.sacc_type_p |vpiParameter: \_parameter: (work@testbench.num_core_p), line:6112:16, endln:6112:26 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiLocalParam:1 |vpiName:num_core_p |vpiFullName:work@testbench.num_core_p |vpiParameter: \_parameter: (work@testbench.num_io_p), line:6113:16, endln:6113:24 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiLocalParam:1 |vpiName:num_io_p |vpiFullName:work@testbench.num_io_p |vpiParameter: \_parameter: (work@testbench.num_l2e_p), line:6114:16, endln:6114:25 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiLocalParam:1 |vpiName:num_l2e_p |vpiFullName:work@testbench.num_l2e_p |vpiParameter: \_parameter: (work@testbench.num_cacc_p), line:6115:16, endln:6115:26 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiLocalParam:1 |vpiName:num_cacc_p |vpiFullName:work@testbench.num_cacc_p |vpiParameter: \_parameter: (work@testbench.num_sacc_p), line:6116:16, endln:6116:26 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiLocalParam:1 |vpiName:num_sacc_p |vpiFullName:work@testbench.num_sacc_p |vpiParameter: \_parameter: (work@testbench.num_cce_p), line:6118:16, endln:6118:25 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiLocalParam:1 |vpiName:num_cce_p |vpiFullName:work@testbench.num_cce_p |vpiParameter: \_parameter: (work@testbench.num_lce_p), line:6119:16, endln:6119:25 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiLocalParam:1 |vpiName:num_lce_p |vpiFullName:work@testbench.num_lce_p |vpiParameter: \_parameter: (work@testbench.core_id_width_p), line:6121:16, endln:6121:31 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiLocalParam:1 |vpiName:core_id_width_p |vpiFullName:work@testbench.core_id_width_p |vpiParameter: \_parameter: (work@testbench.cce_id_width_p), line:6122:16, endln:6122:30 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiLocalParam:1 |vpiName:cce_id_width_p |vpiFullName:work@testbench.cce_id_width_p |vpiParameter: \_parameter: (work@testbench.lce_id_width_p), line:6123:16, endln:6123:30 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiLocalParam:1 |vpiName:lce_id_width_p |vpiFullName:work@testbench.lce_id_width_p |vpiParameter: \_parameter: (work@testbench.vaddr_width_p), line:6125:16, endln:6125:29 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiLocalParam:1 |vpiName:vaddr_width_p |vpiFullName:work@testbench.vaddr_width_p |vpiParameter: \_parameter: (work@testbench.paddr_width_p), line:6126:16, endln:6126:29 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiLocalParam:1 |vpiName:paddr_width_p |vpiFullName:work@testbench.paddr_width_p |vpiParameter: \_parameter: (work@testbench.asid_width_p), line:6127:16, endln:6127:28 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiLocalParam:1 |vpiName:asid_width_p |vpiFullName:work@testbench.asid_width_p |vpiParameter: \_parameter: (work@testbench.boot_pc_p), line:6129:16, endln:6129:25 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiLocalParam:1 |vpiName:boot_pc_p |vpiFullName:work@testbench.boot_pc_p |vpiParameter: \_parameter: (work@testbench.boot_in_debug_p), line:6130:16, endln:6130:31 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiLocalParam:1 |vpiName:boot_in_debug_p |vpiFullName:work@testbench.boot_in_debug_p |vpiParameter: \_parameter: (work@testbench.branch_metadata_fwd_width_p), line:6132:16, endln:6132:43 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiLocalParam:1 |vpiName:branch_metadata_fwd_width_p |vpiFullName:work@testbench.branch_metadata_fwd_width_p |vpiParameter: \_parameter: (work@testbench.btb_tag_width_p), line:6133:16, endln:6133:31 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiLocalParam:1 |vpiName:btb_tag_width_p |vpiFullName:work@testbench.btb_tag_width_p |vpiParameter: \_parameter: (work@testbench.btb_idx_width_p), line:6134:16, endln:6134:31 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiLocalParam:1 |vpiName:btb_idx_width_p |vpiFullName:work@testbench.btb_idx_width_p |vpiParameter: \_parameter: (work@testbench.bht_idx_width_p), line:6135:16, endln:6135:31 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiLocalParam:1 |vpiName:bht_idx_width_p |vpiFullName:work@testbench.bht_idx_width_p |vpiParameter: \_parameter: (work@testbench.ghist_width_p), line:6136:16, endln:6136:29 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiLocalParam:1 |vpiName:ghist_width_p |vpiFullName:work@testbench.ghist_width_p |vpiParameter: \_parameter: (work@testbench.itlb_els_p), line:6138:16, endln:6138:26 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiLocalParam:1 |vpiName:itlb_els_p |vpiFullName:work@testbench.itlb_els_p |vpiParameter: \_parameter: (work@testbench.dtlb_els_p), line:6139:16, endln:6139:26 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiLocalParam:1 |vpiName:dtlb_els_p |vpiFullName:work@testbench.dtlb_els_p |vpiParameter: \_parameter: (work@testbench.lr_sc_p), line:6141:16, endln:6141:23 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiLocalParam:1 |vpiName:lr_sc_p |vpiFullName:work@testbench.lr_sc_p |vpiParameter: \_parameter: (work@testbench.amo_swap_p), line:6142:16, endln:6142:26 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiLocalParam:1 |vpiName:amo_swap_p |vpiFullName:work@testbench.amo_swap_p |vpiParameter: \_parameter: (work@testbench.amo_fetch_logic_p), line:6143:16, endln:6143:33 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiLocalParam:1 |vpiName:amo_fetch_logic_p |vpiFullName:work@testbench.amo_fetch_logic_p |vpiParameter: \_parameter: (work@testbench.amo_fetch_arithmetic_p), line:6144:16, endln:6144:38 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiLocalParam:1 |vpiName:amo_fetch_arithmetic_p |vpiFullName:work@testbench.amo_fetch_arithmetic_p |vpiParameter: \_parameter: (work@testbench.l1_coherent_p), line:6146:16, endln:6146:29 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiLocalParam:1 |vpiName:l1_coherent_p |vpiFullName:work@testbench.l1_coherent_p |vpiParameter: \_parameter: (work@testbench.l1_writethrough_p), line:6147:16, endln:6147:33 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiLocalParam:1 |vpiName:l1_writethrough_p |vpiFullName:work@testbench.l1_writethrough_p |vpiParameter: \_parameter: (work@testbench.dcache_sets_p), line:6148:16, endln:6148:29 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiLocalParam:1 |vpiName:dcache_sets_p |vpiFullName:work@testbench.dcache_sets_p |vpiParameter: \_parameter: (work@testbench.dcache_assoc_p), line:6149:16, endln:6149:30 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiLocalParam:1 |vpiName:dcache_assoc_p |vpiFullName:work@testbench.dcache_assoc_p |vpiParameter: \_parameter: (work@testbench.dcache_block_width_p), line:6150:16, endln:6150:36 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiLocalParam:1 |vpiName:dcache_block_width_p |vpiFullName:work@testbench.dcache_block_width_p |vpiParameter: \_parameter: (work@testbench.dcache_fill_width_p), line:6151:16, endln:6151:35 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiLocalParam:1 |vpiName:dcache_fill_width_p |vpiFullName:work@testbench.dcache_fill_width_p |vpiParameter: \_parameter: (work@testbench.icache_sets_p), line:6152:16, endln:6152:29 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiLocalParam:1 |vpiName:icache_sets_p |vpiFullName:work@testbench.icache_sets_p |vpiParameter: \_parameter: (work@testbench.icache_assoc_p), line:6153:16, endln:6153:30 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiLocalParam:1 |vpiName:icache_assoc_p |vpiFullName:work@testbench.icache_assoc_p |vpiParameter: \_parameter: (work@testbench.icache_block_width_p), line:6154:16, endln:6154:36 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiLocalParam:1 |vpiName:icache_block_width_p |vpiFullName:work@testbench.icache_block_width_p |vpiParameter: \_parameter: (work@testbench.icache_fill_width_p), line:6155:16, endln:6155:35 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiLocalParam:1 |vpiName:icache_fill_width_p |vpiFullName:work@testbench.icache_fill_width_p |vpiParameter: \_parameter: (work@testbench.acache_sets_p), line:6156:16, endln:6156:29 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiLocalParam:1 |vpiName:acache_sets_p |vpiFullName:work@testbench.acache_sets_p |vpiParameter: \_parameter: (work@testbench.acache_assoc_p), line:6157:16, endln:6157:30 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiLocalParam:1 |vpiName:acache_assoc_p |vpiFullName:work@testbench.acache_assoc_p |vpiParameter: \_parameter: (work@testbench.acache_block_width_p), line:6158:16, endln:6158:36 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiLocalParam:1 |vpiName:acache_block_width_p |vpiFullName:work@testbench.acache_block_width_p |vpiParameter: \_parameter: (work@testbench.acache_fill_width_p), line:6159:16, endln:6159:35 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiLocalParam:1 |vpiName:acache_fill_width_p |vpiFullName:work@testbench.acache_fill_width_p |vpiParameter: \_parameter: (work@testbench.lce_assoc_p), line:6160:16, endln:6160:27 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiLocalParam:1 |vpiName:lce_assoc_p |vpiFullName:work@testbench.lce_assoc_p |vpiParameter: \_parameter: (work@testbench.lce_assoc_width_p), line:6164:16, endln:6164:33 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiLocalParam:1 |vpiName:lce_assoc_width_p |vpiFullName:work@testbench.lce_assoc_width_p |vpiParameter: \_parameter: (work@testbench.lce_sets_p), line:6165:16, endln:6165:26 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiLocalParam:1 |vpiName:lce_sets_p |vpiFullName:work@testbench.lce_sets_p |vpiParameter: \_parameter: (work@testbench.lce_sets_width_p), line:6169:16, endln:6169:32 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiLocalParam:1 |vpiName:lce_sets_width_p |vpiFullName:work@testbench.lce_sets_width_p |vpiParameter: \_parameter: (work@testbench.cce_block_width_p), line:6171:16, endln:6171:33 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiLocalParam:1 |vpiName:cce_block_width_p |vpiFullName:work@testbench.cce_block_width_p |vpiParameter: \_parameter: (work@testbench.cce_pc_width_p), line:6183:16, endln:6183:30 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiLocalParam:1 |vpiName:cce_pc_width_p |vpiFullName:work@testbench.cce_pc_width_p |vpiParameter: \_parameter: (work@testbench.num_cce_instr_ram_els_p), line:6184:16, endln:6184:39 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiLocalParam:1 |vpiName:num_cce_instr_ram_els_p |vpiFullName:work@testbench.num_cce_instr_ram_els_p |vpiParameter: \_parameter: (work@testbench.cce_way_groups_p), line:6185:16, endln:6185:32 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiLocalParam:1 |vpiName:cce_way_groups_p |vpiFullName:work@testbench.cce_way_groups_p |vpiParameter: \_parameter: (work@testbench.cce_instr_width_p), line:6186:16, endln:6186:33 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |UINT:34 |vpiTypespec: \_int_typespec: @@ -124518,105 +124518,105 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.cce_ucode_p), line:6187:16, endln:6187:27 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiLocalParam:1 |vpiName:cce_ucode_p |vpiFullName:work@testbench.cce_ucode_p |vpiParameter: \_parameter: (work@testbench.l2_en_p), line:6189:16, endln:6189:23 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiLocalParam:1 |vpiName:l2_en_p |vpiFullName:work@testbench.l2_en_p |vpiParameter: \_parameter: (work@testbench.l2_sets_p), line:6190:16, endln:6190:25 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiLocalParam:1 |vpiName:l2_sets_p |vpiFullName:work@testbench.l2_sets_p |vpiParameter: \_parameter: (work@testbench.l2_assoc_p), line:6191:16, endln:6191:26 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiLocalParam:1 |vpiName:l2_assoc_p |vpiFullName:work@testbench.l2_assoc_p |vpiParameter: \_parameter: (work@testbench.l2_outstanding_reqs_p), line:6192:16, endln:6192:37 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiLocalParam:1 |vpiName:l2_outstanding_reqs_p |vpiFullName:work@testbench.l2_outstanding_reqs_p |vpiParameter: \_parameter: (work@testbench.fe_queue_fifo_els_p), line:6194:16, endln:6194:35 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiLocalParam:1 |vpiName:fe_queue_fifo_els_p |vpiFullName:work@testbench.fe_queue_fifo_els_p |vpiParameter: \_parameter: (work@testbench.fe_cmd_fifo_els_p), line:6195:16, endln:6195:33 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiLocalParam:1 |vpiName:fe_cmd_fifo_els_p |vpiFullName:work@testbench.fe_cmd_fifo_els_p |vpiParameter: \_parameter: (work@testbench.async_coh_clk_p), line:6197:16, endln:6197:31 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiLocalParam:1 |vpiName:async_coh_clk_p |vpiFullName:work@testbench.async_coh_clk_p |vpiParameter: \_parameter: (work@testbench.coh_noc_max_credits_p), line:6198:16, endln:6198:37 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiLocalParam:1 |vpiName:coh_noc_max_credits_p |vpiFullName:work@testbench.coh_noc_max_credits_p |vpiParameter: \_parameter: (work@testbench.coh_noc_flit_width_p), line:6199:16, endln:6199:36 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiLocalParam:1 |vpiName:coh_noc_flit_width_p |vpiFullName:work@testbench.coh_noc_flit_width_p |vpiParameter: \_parameter: (work@testbench.coh_noc_cid_width_p), line:6200:16, endln:6200:35 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiLocalParam:1 |vpiName:coh_noc_cid_width_p |vpiFullName:work@testbench.coh_noc_cid_width_p |vpiParameter: \_parameter: (work@testbench.coh_noc_len_width_p), line:6201:16, endln:6201:35 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiLocalParam:1 |vpiName:coh_noc_len_width_p |vpiFullName:work@testbench.coh_noc_len_width_p |vpiParameter: \_parameter: (work@testbench.coh_noc_y_cord_width_p), line:6202:16, endln:6202:38 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiLocalParam:1 |vpiName:coh_noc_y_cord_width_p |vpiFullName:work@testbench.coh_noc_y_cord_width_p |vpiParameter: \_parameter: (work@testbench.coh_noc_x_cord_width_p), line:6203:16, endln:6203:38 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiLocalParam:1 |vpiName:coh_noc_x_cord_width_p |vpiFullName:work@testbench.coh_noc_x_cord_width_p |vpiParameter: \_parameter: (work@testbench.coh_noc_dims_p), line:6204:16, endln:6204:30 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |UINT:2 |vpiTypespec: \_int_typespec: @@ -124628,14 +124628,14 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.coh_noc_dirs_p), line:6205:16, endln:6205:30 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiLocalParam:1 |vpiName:coh_noc_dirs_p |vpiFullName:work@testbench.coh_noc_dirs_p |vpiParameter: \_parameter: (work@testbench.coh_noc_trans_p), line:6206:16, endln:6206:31 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |UINT:0 |vpiTypespec: \_int_typespec: @@ -124647,7 +124647,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.coh_noc_cord_markers_pos_p), line:6207:20, endln:6207:46 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiSize:1 |vpiTypespec: \_array_typespec: @@ -124705,56 +124705,56 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.coh_noc_cord_width_p), line:6210:16, endln:6210:36 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiLocalParam:1 |vpiName:coh_noc_cord_width_p |vpiFullName:work@testbench.coh_noc_cord_width_p |vpiParameter: \_parameter: (work@testbench.async_mem_clk_p), line:6212:16, endln:6212:31 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiLocalParam:1 |vpiName:async_mem_clk_p |vpiFullName:work@testbench.async_mem_clk_p |vpiParameter: \_parameter: (work@testbench.mem_noc_max_credits_p), line:6213:16, endln:6213:37 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiLocalParam:1 |vpiName:mem_noc_max_credits_p |vpiFullName:work@testbench.mem_noc_max_credits_p |vpiParameter: \_parameter: (work@testbench.mem_noc_flit_width_p), line:6214:16, endln:6214:36 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiLocalParam:1 |vpiName:mem_noc_flit_width_p |vpiFullName:work@testbench.mem_noc_flit_width_p |vpiParameter: \_parameter: (work@testbench.mem_noc_cid_width_p), line:6215:16, endln:6215:35 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiLocalParam:1 |vpiName:mem_noc_cid_width_p |vpiFullName:work@testbench.mem_noc_cid_width_p |vpiParameter: \_parameter: (work@testbench.mem_noc_len_width_p), line:6216:16, endln:6216:35 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiLocalParam:1 |vpiName:mem_noc_len_width_p |vpiFullName:work@testbench.mem_noc_len_width_p |vpiParameter: \_parameter: (work@testbench.mem_noc_y_cord_width_p), line:6217:16, endln:6217:38 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiLocalParam:1 |vpiName:mem_noc_y_cord_width_p |vpiFullName:work@testbench.mem_noc_y_cord_width_p |vpiParameter: \_parameter: (work@testbench.mem_noc_x_cord_width_p), line:6218:16, endln:6218:38 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |UINT:0 |vpiTypespec: \_int_typespec: @@ -124766,7 +124766,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.mem_noc_dims_p), line:6219:16, endln:6219:30 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |UINT:1 |vpiTypespec: \_int_typespec: @@ -124778,7 +124778,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.mem_noc_cord_dims_p), line:6220:16, endln:6220:35 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |UINT:2 |vpiTypespec: \_int_typespec: @@ -124790,14 +124790,14 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.mem_noc_dirs_p), line:6221:16, endln:6221:30 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiLocalParam:1 |vpiName:mem_noc_dirs_p |vpiFullName:work@testbench.mem_noc_dirs_p |vpiParameter: \_parameter: (work@testbench.mem_noc_trans_p), line:6222:16, endln:6222:31 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |UINT:1 |vpiTypespec: \_int_typespec: @@ -124809,7 +124809,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.mem_noc_cord_markers_pos_p), line:6223:20, endln:6223:46 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiSize:1 |vpiTypespec: \_array_typespec: @@ -124867,56 +124867,56 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.mem_noc_cord_width_p), line:6226:16, endln:6226:36 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiLocalParam:1 |vpiName:mem_noc_cord_width_p |vpiFullName:work@testbench.mem_noc_cord_width_p |vpiParameter: \_parameter: (work@testbench.async_io_clk_p), line:6228:16, endln:6228:30 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiLocalParam:1 |vpiName:async_io_clk_p |vpiFullName:work@testbench.async_io_clk_p |vpiParameter: \_parameter: (work@testbench.io_noc_max_credits_p), line:6229:16, endln:6229:36 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiLocalParam:1 |vpiName:io_noc_max_credits_p |vpiFullName:work@testbench.io_noc_max_credits_p |vpiParameter: \_parameter: (work@testbench.io_noc_did_width_p), line:6230:16, endln:6230:34 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiLocalParam:1 |vpiName:io_noc_did_width_p |vpiFullName:work@testbench.io_noc_did_width_p |vpiParameter: \_parameter: (work@testbench.io_noc_flit_width_p), line:6231:16, endln:6231:35 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiLocalParam:1 |vpiName:io_noc_flit_width_p |vpiFullName:work@testbench.io_noc_flit_width_p |vpiParameter: \_parameter: (work@testbench.io_noc_cid_width_p), line:6232:16, endln:6232:34 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiLocalParam:1 |vpiName:io_noc_cid_width_p |vpiFullName:work@testbench.io_noc_cid_width_p |vpiParameter: \_parameter: (work@testbench.io_noc_len_width_p), line:6233:16, endln:6233:34 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiLocalParam:1 |vpiName:io_noc_len_width_p |vpiFullName:work@testbench.io_noc_len_width_p |vpiParameter: \_parameter: (work@testbench.io_noc_y_cord_width_p), line:6234:16, endln:6234:37 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |UINT:0 |vpiTypespec: \_int_typespec: @@ -124928,14 +124928,14 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.io_noc_x_cord_width_p), line:6235:16, endln:6235:37 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiLocalParam:1 |vpiName:io_noc_x_cord_width_p |vpiFullName:work@testbench.io_noc_x_cord_width_p |vpiParameter: \_parameter: (work@testbench.io_noc_dims_p), line:6236:16, endln:6236:29 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |UINT:1 |vpiTypespec: \_int_typespec: @@ -124947,7 +124947,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.io_noc_cord_dims_p), line:6237:16, endln:6237:34 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |UINT:2 |vpiTypespec: \_int_typespec: @@ -124959,14 +124959,14 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.io_noc_dirs_p), line:6238:16, endln:6238:29 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiLocalParam:1 |vpiName:io_noc_dirs_p |vpiFullName:work@testbench.io_noc_dirs_p |vpiParameter: \_parameter: (work@testbench.io_noc_trans_p), line:6239:16, endln:6239:30 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |UINT:0 |vpiTypespec: \_int_typespec: @@ -124978,7 +124978,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.io_noc_cord_markers_pos_p), line:6240:20, endln:6240:45 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiSize:1 |vpiTypespec: \_array_typespec: @@ -125036,14 +125036,14 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.io_noc_cord_width_p), line:6243:16, endln:6243:35 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiLocalParam:1 |vpiName:io_noc_cord_width_p |vpiFullName:work@testbench.io_noc_cord_width_p |vpiParameter: \_parameter: (work@testbench.dword_width_p), line:6245:16, endln:6245:29 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |UINT:64 |vpiTypespec: \_int_typespec: @@ -125055,7 +125055,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.word_width_p), line:6246:16, endln:6246:28 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |UINT:32 |vpiTypespec: \_int_typespec: @@ -125067,7 +125067,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.instr_width_p), line:6247:16, endln:6247:29 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |UINT:32 |vpiTypespec: \_int_typespec: @@ -125079,7 +125079,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.csr_addr_width_p), line:6248:16, endln:6248:32 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |UINT:12 |vpiTypespec: \_int_typespec: @@ -125091,7 +125091,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.reg_addr_width_p), line:6249:16, endln:6249:32 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |UINT:5 |vpiTypespec: \_int_typespec: @@ -125103,7 +125103,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.page_offset_width_p), line:6250:16, endln:6250:35 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |UINT:12 |vpiTypespec: \_int_typespec: @@ -125115,56 +125115,56 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.vtag_width_p), line:6252:16, endln:6252:28 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiLocalParam:1 |vpiName:vtag_width_p |vpiFullName:work@testbench.vtag_width_p |vpiParameter: \_parameter: (work@testbench.ptag_width_p), line:6253:16, endln:6253:28 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiLocalParam:1 |vpiName:ptag_width_p |vpiFullName:work@testbench.ptag_width_p |vpiParameter: \_parameter: (work@testbench.fe_queue_width_lp), line:6256:16, endln:6256:33 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiLocalParam:1 |vpiName:fe_queue_width_lp |vpiFullName:work@testbench.fe_queue_width_lp |vpiParameter: \_parameter: (work@testbench.fe_cmd_width_lp), line:6277:16, endln:6277:31 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiLocalParam:1 |vpiName:fe_cmd_width_lp |vpiFullName:work@testbench.fe_cmd_width_lp |vpiParameter: \_parameter: (work@testbench.cce_mem_payload_width_lp), line:6386:16, endln:6386:40 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiLocalParam:1 |vpiName:cce_mem_payload_width_lp |vpiFullName:work@testbench.cce_mem_payload_width_lp |vpiParameter: \_parameter: (work@testbench.cce_mem_msg_header_width_lp), line:6391:16, endln:6391:43 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiLocalParam:1 |vpiName:cce_mem_msg_header_width_lp |vpiFullName:work@testbench.cce_mem_msg_header_width_lp |vpiParameter: \_parameter: (work@testbench.cce_mem_msg_width_lp), line:6396:16, endln:6396:36 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiLocalParam:1 |vpiName:cce_mem_msg_width_lp |vpiFullName:work@testbench.cce_mem_msg_width_lp |vpiParameter: \_parameter: (work@testbench.icache_trace_p), line:6405:16, endln:6405:30 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |UINT:0 |vpiTypespec: \_int_typespec: @@ -125175,7 +125175,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.dcache_trace_p), line:6406:16, endln:6406:30 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |UINT:0 |vpiTypespec: \_int_typespec: @@ -125186,7 +125186,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.lce_trace_p), line:6407:16, endln:6407:27 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |UINT:0 |vpiTypespec: \_int_typespec: @@ -125197,7 +125197,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.cce_trace_p), line:6408:16, endln:6408:27 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |UINT:0 |vpiTypespec: \_int_typespec: @@ -125208,7 +125208,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.dram_trace_p), line:6409:16, endln:6409:28 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |UINT:0 |vpiTypespec: \_int_typespec: @@ -125219,7 +125219,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.vm_trace_p), line:6410:16, endln:6410:26 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |UINT:0 |vpiTypespec: \_int_typespec: @@ -125230,7 +125230,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.cmt_trace_p), line:6411:16, endln:6411:27 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |UINT:0 |vpiTypespec: \_int_typespec: @@ -125241,7 +125241,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.core_profile_p), line:6412:16, endln:6412:30 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |UINT:0 |vpiTypespec: \_int_typespec: @@ -125252,7 +125252,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.pc_profile_p), line:6413:16, endln:6413:28 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |UINT:0 |vpiTypespec: \_int_typespec: @@ -125263,7 +125263,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.br_profile_p), line:6414:16, endln:6414:28 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |UINT:0 |vpiTypespec: \_int_typespec: @@ -125274,7 +125274,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.cosim_p), line:6415:16, endln:6415:23 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |UINT:0 |vpiTypespec: \_int_typespec: @@ -125285,7 +125285,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.checkpoint_p), line:6418:16, endln:6418:28 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |UINT:0 |vpiTypespec: \_int_typespec: @@ -125296,7 +125296,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.cosim_memsize_p), line:6419:16, endln:6419:31 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |UINT:0 |vpiTypespec: \_int_typespec: @@ -125307,7 +125307,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.cosim_cfg_file_p), line:6420:16, endln:6420:32 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |STRING:prog.cfg |vpiTypespec: \_string_typespec: @@ -125318,7 +125318,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.cosim_instr_p), line:6421:16, endln:6421:29 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |UINT:0 |vpiTypespec: \_int_typespec: @@ -125329,7 +125329,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.warmup_instr_p), line:6422:16, endln:6422:30 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |UINT:0 |vpiTypespec: \_int_typespec: @@ -125340,7 +125340,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.preload_mem_p), line:6425:16, endln:6425:29 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |UINT:0 |vpiTypespec: \_int_typespec: @@ -125351,7 +125351,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.use_ddr_p), line:6426:16, endln:6426:25 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |UINT:0 |vpiTypespec: \_int_typespec: @@ -125362,7 +125362,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.use_dramsim3_p), line:6427:16, endln:6427:30 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |UINT:0 |vpiTypespec: \_int_typespec: @@ -125373,7 +125373,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.dram_fixed_latency_p), line:6428:16, endln:6428:36 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |UINT:0 |vpiTypespec: \_int_typespec: @@ -125384,7 +125384,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.mem_offset_p), line:6429:36, endln:6429:48 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |HEX:80000000 |vpiTypespec: \_int_typespec: , line:6429:16, endln:6429:35 @@ -125428,13 +125428,13 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.mem_cap_in_bytes_p), line:6430:16, endln:6430:34 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiName:mem_cap_in_bytes_p |vpiFullName:work@testbench.mem_cap_in_bytes_p |vpiParameter: \_parameter: (work@testbench.mem_file_p), line:6431:16, endln:6431:26 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |STRING:prog.mem |vpiTypespec: \_string_typespec: @@ -125445,7 +125445,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6092:26, endln:6092:56 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_ref_obj: (e_bp_default_cfg), line:6092:40, endln:6092:56 |vpiName:e_bp_default_cfg @@ -125456,7 +125456,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6094:32, endln:6094:72 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_bit_select: (all_cfgs_gp), line:6094:48, endln:6094:72 |vpiParent: @@ -125476,7 +125476,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6096:16, endln:6096:53 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_hier_path: (proc_param_lp.multicore), line:6096:30, endln:6096:53 |vpiName:proc_param_lp.multicore @@ -125495,7 +125495,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6098:16, endln:6098:52 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_hier_path: (proc_param_lp.cc_x_dim), line:6098:30, endln:6098:52 |vpiName:proc_param_lp.cc_x_dim @@ -125514,7 +125514,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6099:16, endln:6099:52 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_hier_path: (proc_param_lp.cc_y_dim), line:6099:30, endln:6099:52 |vpiName:proc_param_lp.cc_y_dim @@ -125533,7 +125533,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6101:16, endln:6101:39 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_hier_path: (proc_param_lp.cc_x_dim), line:6101:29, endln:6101:39 |vpiName:proc_param_lp.cc_x_dim @@ -125554,7 +125554,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6102:16, endln:6102:51 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_hier_path: (proc_param_lp.ic_y_dim), line:6102:29, endln:6102:51 |vpiName:proc_param_lp.ic_y_dim @@ -125573,7 +125573,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6103:16, endln:6103:39 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_hier_path: (proc_param_lp.cc_x_dim), line:6103:29, endln:6103:39 |vpiName:proc_param_lp.cc_x_dim @@ -125594,7 +125594,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6104:16, endln:6104:51 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_hier_path: (proc_param_lp.mc_y_dim), line:6104:29, endln:6104:51 |vpiName:proc_param_lp.mc_y_dim @@ -125613,7 +125613,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6105:16, endln:6105:53 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_hier_path: (proc_param_lp.cac_x_dim), line:6105:30, endln:6105:53 |vpiName:proc_param_lp.cac_x_dim @@ -125632,7 +125632,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6106:16, endln:6106:40 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_hier_path: (proc_param_lp.cc_y_dim), line:6106:30, endln:6106:40 |vpiName:proc_param_lp.cc_y_dim @@ -125653,7 +125653,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6107:16, endln:6107:53 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_hier_path: (proc_param_lp.sac_x_dim), line:6107:30, endln:6107:53 |vpiName:proc_param_lp.sac_x_dim @@ -125672,7 +125672,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6108:16, endln:6108:40 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_hier_path: (proc_param_lp.cc_y_dim), line:6108:30, endln:6108:40 |vpiName:proc_param_lp.cc_y_dim @@ -125693,7 +125693,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6109:16, endln:6109:53 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_hier_path: (proc_param_lp.cacc_type), line:6109:30, endln:6109:53 |vpiName:proc_param_lp.cacc_type @@ -125712,7 +125712,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6110:16, endln:6110:53 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_hier_path: (proc_param_lp.sacc_type), line:6110:30, endln:6110:53 |vpiName:proc_param_lp.sacc_type @@ -125731,7 +125731,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6112:16, endln:6112:53 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_operation: , line:6112:30, endln:6112:53 |vpiOpType:25 @@ -125774,7 +125774,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6113:16, endln:6113:53 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_operation: , line:6113:30, endln:6113:53 |vpiOpType:25 @@ -125817,7 +125817,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6114:16, endln:6114:53 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_operation: , line:6114:30, endln:6114:53 |vpiOpType:25 @@ -125860,7 +125860,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6115:16, endln:6115:55 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_operation: , line:6115:30, endln:6115:55 |vpiOpType:25 @@ -125903,7 +125903,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6116:16, endln:6116:55 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_operation: , line:6116:30, endln:6116:55 |vpiOpType:25 @@ -125946,7 +125946,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6118:16, endln:6118:49 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_hier_path: (proc_param_lp.num_cce), line:6118:28, endln:6118:49 |vpiName:proc_param_lp.num_cce @@ -125965,7 +125965,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6119:16, endln:6119:49 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_hier_path: (proc_param_lp.num_lce), line:6119:28, endln:6119:49 |vpiName:proc_param_lp.num_lce @@ -125984,7 +125984,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6121:16, endln:6121:103 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_operation: , line:6121:36, endln:6121:102 |vpiOpType:32 @@ -126097,7 +126097,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6122:16, endln:6122:127 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_operation: , line:6122:36, endln:6122:126 |vpiOpType:32 @@ -126314,7 +126314,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6123:16, endln:6123:127 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_operation: , line:6123:36, endln:6123:126 |vpiParent: @@ -126533,7 +126533,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6125:16, endln:6125:57 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_hier_path: (proc_param_lp.vaddr_width), line:6125:32, endln:6125:57 |vpiName:proc_param_lp.vaddr_width @@ -126552,7 +126552,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6126:16, endln:6126:57 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_hier_path: (proc_param_lp.paddr_width), line:6126:32, endln:6126:57 |vpiName:proc_param_lp.paddr_width @@ -126571,7 +126571,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6127:16, endln:6127:56 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_hier_path: (proc_param_lp.asid_width), line:6127:32, endln:6127:56 |vpiName:proc_param_lp.asid_width @@ -126590,7 +126590,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6129:16, endln:6129:55 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_hier_path: (proc_param_lp.boot_pc), line:6129:34, endln:6129:55 |vpiName:proc_param_lp.boot_pc @@ -126609,7 +126609,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6130:16, endln:6130:61 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_hier_path: (proc_param_lp.boot_in_debug), line:6130:34, endln:6130:61 |vpiName:proc_param_lp.boot_in_debug @@ -126628,7 +126628,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6132:16, endln:6132:85 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_hier_path: (proc_param_lp.branch_metadata_fwd_width), line:6132:46, endln:6132:85 |vpiName:proc_param_lp.branch_metadata_fwd_width @@ -126647,7 +126647,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6133:16, endln:6133:73 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_hier_path: (proc_param_lp.btb_tag_width), line:6133:46, endln:6133:73 |vpiName:proc_param_lp.btb_tag_width @@ -126666,7 +126666,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6134:16, endln:6134:73 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_hier_path: (proc_param_lp.btb_idx_width), line:6134:46, endln:6134:73 |vpiName:proc_param_lp.btb_idx_width @@ -126685,7 +126685,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6135:16, endln:6135:73 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_hier_path: (proc_param_lp.bht_idx_width), line:6135:46, endln:6135:73 |vpiName:proc_param_lp.bht_idx_width @@ -126704,7 +126704,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6136:16, endln:6136:71 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_hier_path: (proc_param_lp.ghist_width), line:6136:46, endln:6136:71 |vpiName:proc_param_lp.ghist_width @@ -126723,7 +126723,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6138:16, endln:6138:64 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_hier_path: (proc_param_lp.itlb_els), line:6138:42, endln:6138:64 |vpiName:proc_param_lp.itlb_els @@ -126742,7 +126742,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6139:16, endln:6139:64 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_hier_path: (proc_param_lp.dtlb_els), line:6139:42, endln:6139:64 |vpiName:proc_param_lp.dtlb_els @@ -126761,7 +126761,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6141:16, endln:6141:64 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_hier_path: (proc_param_lp.lr_sc), line:6141:45, endln:6141:64 |vpiName:proc_param_lp.lr_sc @@ -126780,7 +126780,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6142:16, endln:6142:67 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_hier_path: (proc_param_lp.amo_swap), line:6142:45, endln:6142:67 |vpiName:proc_param_lp.amo_swap @@ -126799,7 +126799,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6143:16, endln:6143:74 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_hier_path: (proc_param_lp.amo_fetch_logic), line:6143:45, endln:6143:74 |vpiName:proc_param_lp.amo_fetch_logic @@ -126818,7 +126818,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6144:16, endln:6144:79 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_hier_path: (proc_param_lp.amo_fetch_arithmetic), line:6144:45, endln:6144:79 |vpiName:proc_param_lp.amo_fetch_arithmetic @@ -126837,7 +126837,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6146:16, endln:6146:70 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_hier_path: (proc_param_lp.l1_coherent), line:6146:45, endln:6146:70 |vpiName:proc_param_lp.l1_coherent @@ -126856,7 +126856,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6147:16, endln:6147:74 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_hier_path: (proc_param_lp.l1_writethrough), line:6147:45, endln:6147:74 |vpiName:proc_param_lp.l1_writethrough @@ -126875,7 +126875,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6148:16, endln:6148:70 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_hier_path: (proc_param_lp.dcache_sets), line:6148:45, endln:6148:70 |vpiName:proc_param_lp.dcache_sets @@ -126894,7 +126894,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6149:16, endln:6149:71 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_hier_path: (proc_param_lp.dcache_assoc), line:6149:45, endln:6149:71 |vpiName:proc_param_lp.dcache_assoc @@ -126913,7 +126913,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6150:16, endln:6150:77 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_hier_path: (proc_param_lp.dcache_block_width), line:6150:45, endln:6150:77 |vpiName:proc_param_lp.dcache_block_width @@ -126932,7 +126932,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6151:16, endln:6151:76 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_hier_path: (proc_param_lp.dcache_fill_width), line:6151:45, endln:6151:76 |vpiName:proc_param_lp.dcache_fill_width @@ -126951,7 +126951,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6152:16, endln:6152:70 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_hier_path: (proc_param_lp.icache_sets), line:6152:45, endln:6152:70 |vpiName:proc_param_lp.icache_sets @@ -126970,7 +126970,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6153:16, endln:6153:71 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_hier_path: (proc_param_lp.icache_assoc), line:6153:45, endln:6153:71 |vpiName:proc_param_lp.icache_assoc @@ -126989,7 +126989,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6154:16, endln:6154:77 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_hier_path: (proc_param_lp.icache_block_width), line:6154:45, endln:6154:77 |vpiName:proc_param_lp.icache_block_width @@ -127008,7 +127008,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6155:16, endln:6155:76 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_hier_path: (proc_param_lp.icache_fill_width), line:6155:45, endln:6155:76 |vpiName:proc_param_lp.icache_fill_width @@ -127027,7 +127027,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6156:16, endln:6156:70 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_hier_path: (proc_param_lp.acache_sets), line:6156:45, endln:6156:70 |vpiName:proc_param_lp.acache_sets @@ -127046,7 +127046,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6157:16, endln:6157:71 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_hier_path: (proc_param_lp.acache_assoc), line:6157:45, endln:6157:71 |vpiName:proc_param_lp.acache_assoc @@ -127065,7 +127065,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6158:16, endln:6158:77 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_hier_path: (proc_param_lp.acache_block_width), line:6158:45, endln:6158:77 |vpiName:proc_param_lp.acache_block_width @@ -127084,7 +127084,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6159:16, endln:6159:76 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_hier_path: (proc_param_lp.acache_fill_width), line:6159:45, endln:6159:76 |vpiName:proc_param_lp.acache_fill_width @@ -127103,7 +127103,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6160:16, endln:6162:131 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_operation: , line:6160:46, endln:6162:130 |vpiParent: @@ -127309,7 +127309,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6164:16, endln:6164:94 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_operation: , line:6164:47, endln:6164:93 |vpiOpType:32 @@ -127348,7 +127348,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6165:16, endln:6167:127 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_operation: , line:6165:46, endln:6167:126 |vpiParent: @@ -127554,7 +127554,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6169:16, endln:6169:92 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_operation: , line:6169:47, endln:6169:91 |vpiOpType:32 @@ -127593,7 +127593,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6171:16, endln:6179:3 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_operation: , line:6171:47, endln:6179:2 |vpiParent: @@ -127799,7 +127799,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6183:16, endln:6183:71 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_hier_path: (proc_param_lp.cce_pc_width), line:6183:45, endln:6183:71 |vpiName:proc_param_lp.cce_pc_width @@ -127818,7 +127818,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6184:16, endln:6184:62 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_operation: , line:6184:45, endln:6184:62 |vpiOpType:43 @@ -127852,7 +127852,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6185:16, endln:6185:116 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_operation: , line:6185:46, endln:6185:115 |vpiOpType:32 @@ -127934,7 +127934,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6186:16, endln:6186:47 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_constant: , line:6186:45, endln:6186:47 |vpiDecompile:34 @@ -127948,7 +127948,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6187:16, endln:6187:68 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_hier_path: (proc_param_lp.cce_ucode), line:6187:45, endln:6187:68 |vpiName:proc_param_lp.cce_ucode @@ -127967,7 +127967,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6189:16, endln:6189:48 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_hier_path: (proc_param_lp.l2_en), line:6189:29, endln:6189:48 |vpiName:proc_param_lp.l2_en @@ -127986,7 +127986,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6190:16, endln:6190:50 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_hier_path: (proc_param_lp.l2_sets), line:6190:29, endln:6190:50 |vpiName:proc_param_lp.l2_sets @@ -128005,7 +128005,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6191:16, endln:6191:51 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_hier_path: (proc_param_lp.l2_assoc), line:6191:29, endln:6191:51 |vpiName:proc_param_lp.l2_assoc @@ -128024,7 +128024,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6192:16, endln:6192:73 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_hier_path: (proc_param_lp.l2_outstanding_reqs), line:6192:40, endln:6192:73 |vpiName:proc_param_lp.l2_outstanding_reqs @@ -128043,7 +128043,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6194:16, endln:6194:69 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_hier_path: (proc_param_lp.fe_queue_fifo_els), line:6194:38, endln:6194:69 |vpiName:proc_param_lp.fe_queue_fifo_els @@ -128062,7 +128062,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6195:16, endln:6195:67 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_hier_path: (proc_param_lp.fe_cmd_fifo_els), line:6195:38, endln:6195:67 |vpiName:proc_param_lp.fe_cmd_fifo_els @@ -128081,7 +128081,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6197:16, endln:6197:68 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_hier_path: (proc_param_lp.async_coh_clk), line:6197:41, endln:6197:68 |vpiName:proc_param_lp.async_coh_clk @@ -128100,7 +128100,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6198:16, endln:6198:74 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_hier_path: (proc_param_lp.coh_noc_max_credits), line:6198:41, endln:6198:74 |vpiName:proc_param_lp.coh_noc_max_credits @@ -128119,7 +128119,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6199:16, endln:6199:73 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_hier_path: (proc_param_lp.coh_noc_flit_width), line:6199:41, endln:6199:73 |vpiName:proc_param_lp.coh_noc_flit_width @@ -128138,7 +128138,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6200:16, endln:6200:72 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_hier_path: (proc_param_lp.coh_noc_cid_width), line:6200:41, endln:6200:72 |vpiName:proc_param_lp.coh_noc_cid_width @@ -128157,7 +128157,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6201:16, endln:6201:72 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_hier_path: (proc_param_lp.coh_noc_len_width), line:6201:41, endln:6201:72 |vpiName:proc_param_lp.coh_noc_len_width @@ -128176,7 +128176,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6202:16, endln:6202:136 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_operation: , line:6202:43, endln:6202:135 |vpiParent: @@ -128361,7 +128361,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6203:16, endln:6203:140 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_operation: , line:6203:43, endln:6203:139 |vpiParent: @@ -128546,7 +128546,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6204:16, endln:6204:42 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_constant: , line:6204:41, endln:6204:42 |vpiDecompile:2 @@ -128560,7 +128560,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6205:16, endln:6205:61 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_constant: , line:6205:41, endln:6205:61 |vpiDecompile:5 @@ -128572,7 +128572,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6206:16, endln:6206:42 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_constant: , line:6206:41, endln:6206:42 |vpiDecompile:0 @@ -128586,7 +128586,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6207:20, endln:6209:84 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_operation: , line:6209:9, endln:6209:84 |vpiParent: @@ -129150,7 +129150,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6210:16, endln:6210:83 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_operation: , line:6209:11, endln:6209:56 |vpiParent: @@ -129165,7 +129165,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6212:16, endln:6212:71 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_hier_path: (proc_param_lp.async_mem_clk), line:6212:44, endln:6212:71 |vpiName:proc_param_lp.async_mem_clk @@ -129184,7 +129184,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6213:16, endln:6213:77 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_hier_path: (proc_param_lp.mem_noc_max_credits), line:6213:44, endln:6213:77 |vpiName:proc_param_lp.mem_noc_max_credits @@ -129203,7 +129203,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6214:16, endln:6214:76 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_hier_path: (proc_param_lp.mem_noc_flit_width), line:6214:44, endln:6214:76 |vpiName:proc_param_lp.mem_noc_flit_width @@ -129222,7 +129222,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6215:16, endln:6215:75 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_hier_path: (proc_param_lp.mem_noc_cid_width), line:6215:44, endln:6215:75 |vpiName:proc_param_lp.mem_noc_cid_width @@ -129241,7 +129241,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6216:16, endln:6216:75 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_hier_path: (proc_param_lp.mem_noc_len_width), line:6216:44, endln:6216:75 |vpiName:proc_param_lp.mem_noc_len_width @@ -129260,7 +129260,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6217:16, endln:6217:139 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_operation: , line:6217:46, endln:6217:138 |vpiParent: @@ -129445,7 +129445,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6218:16, endln:6218:45 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_constant: , line:6218:44, endln:6218:45 |vpiDecompile:0 @@ -129459,7 +129459,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6219:16, endln:6219:45 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_constant: , line:6219:44, endln:6219:45 |vpiDecompile:1 @@ -129473,7 +129473,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6220:16, endln:6220:45 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_constant: , line:6220:44, endln:6220:45 |vpiDecompile:2 @@ -129487,7 +129487,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6221:16, endln:6221:64 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_constant: , line:6221:44, endln:6221:64 |vpiDecompile:3 @@ -129499,7 +129499,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6222:16, endln:6222:45 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_constant: , line:6222:44, endln:6222:45 |vpiDecompile:1 @@ -129513,7 +129513,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6223:20, endln:6225:84 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_operation: , line:6224:9, endln:6224:84 |vpiParent: @@ -129906,7 +129906,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6226:16, endln:6226:86 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_operation: , line:6217:46, endln:6217:138 |vpiLhs: @@ -129914,7 +129914,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6228:16, endln:6228:69 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_hier_path: (proc_param_lp.async_io_clk), line:6228:43, endln:6228:69 |vpiName:proc_param_lp.async_io_clk @@ -129933,7 +129933,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6229:16, endln:6229:75 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_hier_path: (proc_param_lp.io_noc_max_credits), line:6229:43, endln:6229:75 |vpiName:proc_param_lp.io_noc_max_credits @@ -129952,7 +129952,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6230:16, endln:6230:73 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_hier_path: (proc_param_lp.io_noc_did_width), line:6230:43, endln:6230:73 |vpiName:proc_param_lp.io_noc_did_width @@ -129971,7 +129971,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6231:16, endln:6231:74 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_hier_path: (proc_param_lp.io_noc_flit_width), line:6231:43, endln:6231:74 |vpiName:proc_param_lp.io_noc_flit_width @@ -129990,7 +129990,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6232:16, endln:6232:73 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_hier_path: (proc_param_lp.io_noc_cid_width), line:6232:43, endln:6232:73 |vpiName:proc_param_lp.io_noc_cid_width @@ -130009,7 +130009,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6233:16, endln:6233:73 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_hier_path: (proc_param_lp.io_noc_len_width), line:6233:43, endln:6233:73 |vpiName:proc_param_lp.io_noc_len_width @@ -130028,7 +130028,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6234:16, endln:6234:44 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_constant: , line:6234:43, endln:6234:44 |vpiDecompile:0 @@ -130042,7 +130042,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6235:16, endln:6235:61 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_hier_path: (proc_param_lp.io_noc_did_width), line:6235:43, endln:6235:61 |vpiName:proc_param_lp.io_noc_did_width @@ -130063,7 +130063,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6236:16, endln:6236:44 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_constant: , line:6236:43, endln:6236:44 |vpiDecompile:1 @@ -130077,7 +130077,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6237:16, endln:6237:44 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_constant: , line:6237:43, endln:6237:44 |vpiDecompile:2 @@ -130091,7 +130091,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6238:16, endln:6238:67 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_constant: , line:6238:43, endln:6238:67 |vpiDecompile:5 @@ -130103,7 +130103,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6239:16, endln:6239:44 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_constant: , line:6239:43, endln:6239:44 |vpiDecompile:0 @@ -130117,7 +130117,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6240:20, endln:6242:81 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_operation: , line:6242:9, endln:6242:81 |vpiParent: @@ -130186,7 +130186,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6243:16, endln:6243:83 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_hier_path: (proc_param_lp.io_noc_did_width), line:6230:43, endln:6230:73 |vpiName:proc_param_lp.io_noc_did_width @@ -130207,7 +130207,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6245:16, endln:6245:40 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_constant: , line:6245:38, endln:6245:40 |vpiDecompile:64 @@ -130221,7 +130221,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6246:16, endln:6246:40 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_constant: , line:6246:38, endln:6246:40 |vpiDecompile:32 @@ -130235,7 +130235,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6247:16, endln:6247:40 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_constant: , line:6247:38, endln:6247:40 |vpiDecompile:32 @@ -130249,7 +130249,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6248:16, endln:6248:40 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_constant: , line:6248:38, endln:6248:40 |vpiDecompile:12 @@ -130263,7 +130263,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6249:16, endln:6249:39 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_constant: , line:6249:38, endln:6249:39 |vpiDecompile:5 @@ -130277,7 +130277,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6250:16, endln:6250:40 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_constant: , line:6250:38, endln:6250:40 |vpiDecompile:12 @@ -130291,7 +130291,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6252:16, endln:6252:79 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_operation: , line:6252:32, endln:6252:79 |vpiOpType:11 @@ -130323,7 +130323,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6253:16, endln:6253:79 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_operation: , line:6253:32, endln:6253:79 |vpiOpType:11 @@ -130355,7 +130355,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6256:16, endln:6275:5 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_operation: , line:6257:4, endln:6273:5 |vpiOpType:24 @@ -130559,7 +130559,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6277:16, endln:6381:5 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_operation: , line:6278:4, endln:6379:5 |vpiOpType:24 @@ -131497,7 +131497,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6386:16, endln:6387:94 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_operation: , line:6387:4, endln:6387:93 |vpiParent: @@ -131571,7 +131571,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6391:16, endln:6392:96 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_operation: , line:6392:4, endln:6392:95 |vpiOpType:24 @@ -131625,7 +131625,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6396:16, endln:6399:20 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_operation: , line:6398:3, endln:6399:19 |vpiOpType:24 @@ -131686,7 +131686,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6405:16, endln:6405:47 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_constant: , line:6405:46, endln:6405:47 |vpiDecompile:0 @@ -131700,7 +131700,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6406:16, endln:6406:47 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_constant: , line:6406:46, endln:6406:47 |vpiDecompile:0 @@ -131714,7 +131714,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6407:16, endln:6407:47 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_constant: , line:6407:46, endln:6407:47 |vpiDecompile:0 @@ -131728,7 +131728,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6408:16, endln:6408:47 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_constant: , line:6408:46, endln:6408:47 |vpiDecompile:0 @@ -131742,7 +131742,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6409:16, endln:6409:47 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_constant: , line:6409:46, endln:6409:47 |vpiDecompile:0 @@ -131756,7 +131756,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6410:16, endln:6410:47 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_constant: , line:6410:46, endln:6410:47 |vpiDecompile:0 @@ -131770,7 +131770,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6411:16, endln:6411:47 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_constant: , line:6411:46, endln:6411:47 |vpiDecompile:0 @@ -131784,7 +131784,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6412:16, endln:6412:47 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_constant: , line:6412:46, endln:6412:47 |vpiDecompile:0 @@ -131798,7 +131798,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6413:16, endln:6413:47 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_constant: , line:6413:46, endln:6413:47 |vpiDecompile:0 @@ -131812,7 +131812,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6414:16, endln:6414:47 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_constant: , line:6414:46, endln:6414:47 |vpiDecompile:0 @@ -131826,7 +131826,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6415:16, endln:6415:47 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_constant: , line:6415:46, endln:6415:47 |vpiDecompile:0 @@ -131840,7 +131840,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6418:16, endln:6418:47 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_constant: , line:6418:46, endln:6418:47 |vpiDecompile:0 @@ -131854,7 +131854,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6419:16, endln:6419:47 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_constant: , line:6419:46, endln:6419:47 |vpiDecompile:0 @@ -131868,7 +131868,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6420:16, endln:6420:56 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_constant: , line:6420:46, endln:6420:56 |vpiDecompile:prog.cfg @@ -131882,7 +131882,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6421:16, endln:6421:47 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_constant: , line:6421:46, endln:6421:47 |vpiDecompile:0 @@ -131896,7 +131896,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6422:16, endln:6422:47 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_constant: , line:6422:46, endln:6422:47 |vpiDecompile:0 @@ -131910,7 +131910,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6425:16, endln:6425:47 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_constant: , line:6425:46, endln:6425:47 |vpiDecompile:0 @@ -131924,7 +131924,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6426:16, endln:6426:47 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_constant: , line:6426:46, endln:6426:47 |vpiDecompile:0 @@ -131938,7 +131938,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6427:16, endln:6427:47 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_constant: , line:6427:46, endln:6427:47 |vpiDecompile:0 @@ -131952,7 +131952,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6428:16, endln:6428:47 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_constant: , line:6428:46, endln:6428:47 |vpiDecompile:0 @@ -131966,7 +131966,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6429:36, endln:6429:68 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_constant: , line:6429:51, endln:6429:68 |vpiDecompile:32'h80000000 @@ -131980,7 +131980,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6430:16, endln:6430:42 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_constant: , line:6430:37, endln:6430:42 |vpiDecompile:134217728 @@ -131992,7 +131992,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:6431:16, endln:6431:47 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_constant: , line:6431:37, endln:6431:47 |vpiDecompile:prog.mem @@ -132006,7 +132006,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:78:12, endln:78:32 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_constant: , line:78:31, endln:78:32 |vpiDecompile:0 @@ -132020,7 +132020,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:79:12, endln:79:32 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_constant: , line:79:31, endln:79:32 |vpiDecompile:1 @@ -132034,7 +132034,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:80:12, endln:80:32 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_constant: , line:80:31, endln:80:32 |vpiDecompile:2 @@ -132048,7 +132048,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:899:14, endln:899:36 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_constant: , line:899:34, endln:899:36 |vpiDecompile:64 @@ -132062,7 +132062,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:900:14, endln:900:36 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_constant: , line:900:34, endln:900:36 |vpiDecompile:32 @@ -132076,7 +132076,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:902:13, endln:902:44 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_constant: , line:902:43, endln:902:44 |vpiDecompile:3 @@ -132090,7 +132090,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:903:13, endln:903:38 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_constant: , line:903:36, endln:903:38 |vpiDecompile:64 @@ -132104,7 +132104,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:904:13, endln:904:40 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_constant: , line:904:38, endln:904:40 |vpiDecompile:39 @@ -132118,7 +132118,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:905:13, endln:905:40 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_constant: , line:905:38, endln:905:40 |vpiDecompile:56 @@ -132132,7 +132132,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:906:13, endln:906:38 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_constant: , line:906:36, endln:906:38 |vpiDecompile:44 @@ -132146,7 +132146,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:907:13, endln:907:44 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_constant: , line:907:40, endln:907:44 |vpiDecompile:4096 @@ -132160,7 +132160,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:908:13, endln:908:114 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_constant: , line:908:39, endln:908:114 |vpiDecompile:12 @@ -132174,7 +132174,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:910:13, endln:910:41 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_constant: , line:910:40, endln:910:41 |vpiDecompile:4 @@ -132188,7 +132188,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:911:13, endln:911:40 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_constant: , line:911:39, endln:911:40 |vpiDecompile:4 @@ -132202,7 +132202,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:913:14, endln:913:55 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_constant: , line:913:42, endln:913:55 |vpiDecompile:32'h80000000 @@ -132216,7 +132216,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:915:14, endln:915:55 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_constant: , line:915:42, endln:915:55 |vpiDecompile:32'h01?????? @@ -132230,7 +132230,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:916:14, endln:916:55 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_constant: , line:916:42, endln:916:55 |vpiDecompile:32'h02?????? @@ -132244,7 +132244,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:917:14, endln:917:55 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_constant: , line:917:42, endln:917:55 |vpiDecompile:32'h03?????? @@ -132258,7 +132258,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:918:14, endln:918:55 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_constant: , line:918:42, endln:918:55 |vpiDecompile:32'h0c?????? @@ -132272,7 +132272,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:920:14, endln:920:55 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_constant: , line:920:42, endln:920:55 |vpiDecompile:32'h02000??? @@ -132286,7 +132286,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:921:14, endln:921:55 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_constant: , line:921:42, endln:921:55 |vpiDecompile:32'h02004??? @@ -132300,7 +132300,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:922:14, endln:922:55 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_constant: , line:922:42, endln:922:55 |vpiDecompile:32'h0200bff8 @@ -132314,7 +132314,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:923:14, endln:923:55 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_constant: , line:923:42, endln:923:55 |vpiDecompile:32'h0c000??? @@ -132328,7 +132328,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:2192:14, endln:2192:31 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_constant: , line:2192:28, endln:2192:31 |vpiDecompile:128 @@ -132342,7 +132342,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:2193:14, endln:2193:71 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_constant: , line:2193:28, endln:2193:71 |vpiDecompile:7 @@ -132356,7 +132356,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:2195:30, endln:2196:22 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_operation: , line:2196:5, endln:2196:22 |vpiParent: @@ -133375,7 +133375,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:2198:30, endln:2247:8 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_operation: , line:2199:5, endln:2247:8 |vpiParent: @@ -134394,7 +134394,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:2249:30, endln:2298:8 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_operation: , line:2250:5, endln:2298:8 |vpiParent: @@ -135413,7 +135413,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:2300:30, endln:2349:8 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_operation: , line:2301:5, endln:2349:8 |vpiParent: @@ -136432,7 +136432,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:2351:30, endln:2400:8 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_operation: , line:2352:5, endln:2400:8 |vpiParent: @@ -137451,7 +137451,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:2402:30, endln:2451:8 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_operation: , line:2403:5, endln:2451:8 |vpiParent: @@ -138470,7 +138470,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:2453:30, endln:2502:8 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_operation: , line:2454:5, endln:2502:8 |vpiParent: @@ -139489,7 +139489,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:2516:44, endln:2525:4 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_operation: , line:2517:3, endln:2525:4 |vpiTypespec: @@ -140262,7 +140262,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:78:12, endln:78:32 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_constant: , line:78:31, endln:78:32 |vpiDecompile:0 @@ -140276,7 +140276,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:79:12, endln:79:32 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_constant: , line:79:31, endln:79:32 |vpiDecompile:1 @@ -140290,7 +140290,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:80:12, endln:80:32 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_constant: , line:80:31, endln:80:32 |vpiDecompile:2 @@ -140304,7 +140304,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:899:14, endln:899:36 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_constant: , line:899:34, endln:899:36 |vpiDecompile:64 @@ -140318,7 +140318,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:900:14, endln:900:36 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_constant: , line:900:34, endln:900:36 |vpiDecompile:32 @@ -140332,7 +140332,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:902:13, endln:902:44 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_constant: , line:902:43, endln:902:44 |vpiDecompile:3 @@ -140346,7 +140346,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:903:13, endln:903:38 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_constant: , line:903:36, endln:903:38 |vpiDecompile:64 @@ -140360,7 +140360,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:904:13, endln:904:40 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_constant: , line:904:38, endln:904:40 |vpiDecompile:39 @@ -140374,7 +140374,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:905:13, endln:905:40 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_constant: , line:905:38, endln:905:40 |vpiDecompile:56 @@ -140388,7 +140388,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:906:13, endln:906:38 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_constant: , line:906:36, endln:906:38 |vpiDecompile:44 @@ -140402,7 +140402,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:907:13, endln:907:44 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_constant: , line:907:40, endln:907:44 |vpiDecompile:4096 @@ -140416,7 +140416,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:908:13, endln:908:114 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_constant: , line:908:39, endln:908:114 |vpiDecompile:12 @@ -140430,7 +140430,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:910:13, endln:910:41 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_constant: , line:910:40, endln:910:41 |vpiDecompile:4 @@ -140444,7 +140444,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:911:13, endln:911:40 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_constant: , line:911:39, endln:911:40 |vpiDecompile:4 @@ -140458,7 +140458,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:913:14, endln:913:55 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_constant: , line:913:42, endln:913:55 |vpiDecompile:32'h80000000 @@ -140472,7 +140472,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:915:14, endln:915:55 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_constant: , line:915:42, endln:915:55 |vpiDecompile:32'h01?????? @@ -140486,7 +140486,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:916:14, endln:916:55 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_constant: , line:916:42, endln:916:55 |vpiDecompile:32'h02?????? @@ -140500,7 +140500,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:917:14, endln:917:55 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_constant: , line:917:42, endln:917:55 |vpiDecompile:32'h03?????? @@ -140514,7 +140514,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:918:14, endln:918:55 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_constant: , line:918:42, endln:918:55 |vpiDecompile:32'h0c?????? @@ -140528,7 +140528,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:920:14, endln:920:55 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_constant: , line:920:42, endln:920:55 |vpiDecompile:32'h02000??? @@ -140542,7 +140542,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:921:14, endln:921:55 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_constant: , line:921:42, endln:921:55 |vpiDecompile:32'h02004??? @@ -140556,7 +140556,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:922:14, endln:922:55 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_constant: , line:922:42, endln:922:55 |vpiDecompile:32'h0200bff8 @@ -140570,7 +140570,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:923:14, endln:923:55 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_constant: , line:923:42, endln:923:55 |vpiDecompile:32'h0c000??? @@ -140584,7 +140584,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:1959:14, endln:1959:41 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_constant: , line:1959:39, endln:1959:41 |vpiDecompile:32 @@ -140598,7 +140598,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:1960:14, endln:1960:41 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_constant: , line:1960:39, endln:1960:41 |vpiDecompile:32 @@ -140612,7 +140612,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:1961:14, endln:1961:41 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_constant: , line:1961:39, endln:1961:41 |vpiDecompile:64 @@ -140626,7 +140626,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:1962:14, endln:1962:40 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_constant: , line:1962:39, endln:1962:40 |vpiDecompile:8 @@ -140640,7 +140640,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:1963:14, endln:1963:41 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_constant: , line:1963:39, endln:1963:41 |vpiDecompile:16 @@ -140654,7 +140654,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:1964:14, endln:1964:41 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_constant: , line:1964:39, endln:1964:41 |vpiDecompile:32 @@ -140668,7 +140668,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:1965:14, endln:1965:41 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_constant: , line:1965:39, endln:1965:41 |vpiDecompile:64 @@ -140682,7 +140682,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:1966:14, endln:1966:41 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_constant: , line:1966:39, endln:1966:41 |vpiDecompile:64 @@ -140696,7 +140696,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:1967:14, endln:1967:40 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_constant: , line:1967:39, endln:1967:40 |vpiDecompile:5 @@ -140710,7 +140710,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:1968:14, endln:1968:40 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_constant: , line:1968:39, endln:1968:40 |vpiDecompile:6 @@ -140724,7 +140724,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:1969:14, endln:1969:40 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_constant: , line:1969:39, endln:1969:40 |vpiDecompile:5 @@ -140738,7 +140738,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:1970:14, endln:1970:40 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_constant: , line:1970:39, endln:1970:40 |vpiDecompile:7 @@ -140752,7 +140752,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:1971:14, endln:1971:40 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_constant: , line:1971:39, endln:1971:40 |vpiDecompile:3 @@ -140766,7 +140766,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:1972:14, endln:1972:40 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_constant: , line:1972:39, endln:1972:40 |vpiDecompile:7 @@ -140780,7 +140780,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:1973:14, endln:1973:41 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_constant: , line:1973:39, endln:1973:41 |vpiDecompile:12 @@ -140794,7 +140794,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:1974:14, endln:1974:41 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_constant: , line:1974:39, endln:1974:41 |vpiDecompile:20 @@ -140808,7 +140808,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:1975:14, endln:1975:41 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_constant: , line:1975:39, endln:1975:41 |vpiDecompile:12 @@ -140822,7 +140822,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:1976:14, endln:1976:40 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_constant: , line:1976:39, endln:1976:40 |vpiDecompile:7 @@ -140836,7 +140836,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:1977:14, endln:1977:40 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_constant: , line:1977:39, endln:1977:40 |vpiDecompile:5 @@ -140850,7 +140850,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:1978:14, endln:1978:40 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_constant: , line:1978:39, endln:1978:40 |vpiDecompile:2 @@ -140864,7 +140864,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:78:12, endln:78:32 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_constant: , line:78:31, endln:78:32 |vpiDecompile:0 @@ -140878,7 +140878,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:79:12, endln:79:32 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_constant: , line:79:31, endln:79:32 |vpiDecompile:1 @@ -140892,7 +140892,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:80:12, endln:80:32 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_constant: , line:80:31, endln:80:32 |vpiDecompile:2 @@ -140906,7 +140906,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:899:14, endln:899:36 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_constant: , line:899:34, endln:899:36 |vpiDecompile:64 @@ -140920,7 +140920,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:900:14, endln:900:36 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_constant: , line:900:34, endln:900:36 |vpiDecompile:32 @@ -140934,7 +140934,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:902:13, endln:902:44 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_constant: , line:902:43, endln:902:44 |vpiDecompile:3 @@ -140948,7 +140948,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:903:13, endln:903:38 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_constant: , line:903:36, endln:903:38 |vpiDecompile:64 @@ -140962,7 +140962,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:904:13, endln:904:40 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_constant: , line:904:38, endln:904:40 |vpiDecompile:39 @@ -140976,7 +140976,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:905:13, endln:905:40 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_constant: , line:905:38, endln:905:40 |vpiDecompile:56 @@ -140990,7 +140990,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:906:13, endln:906:38 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_constant: , line:906:36, endln:906:38 |vpiDecompile:44 @@ -141004,7 +141004,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:907:13, endln:907:44 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_constant: , line:907:40, endln:907:44 |vpiDecompile:4096 @@ -141018,7 +141018,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:908:13, endln:908:114 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_constant: , line:908:39, endln:908:114 |vpiDecompile:12 @@ -141032,7 +141032,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:910:13, endln:910:41 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_constant: , line:910:40, endln:910:41 |vpiDecompile:4 @@ -141046,7 +141046,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:911:13, endln:911:40 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_constant: , line:911:39, endln:911:40 |vpiDecompile:4 @@ -141060,7 +141060,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:913:14, endln:913:55 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_constant: , line:913:42, endln:913:55 |vpiDecompile:32'h80000000 @@ -141074,7 +141074,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:915:14, endln:915:55 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_constant: , line:915:42, endln:915:55 |vpiDecompile:32'h01?????? @@ -141088,7 +141088,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:916:14, endln:916:55 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_constant: , line:916:42, endln:916:55 |vpiDecompile:32'h02?????? @@ -141102,7 +141102,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:917:14, endln:917:55 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_constant: , line:917:42, endln:917:55 |vpiDecompile:32'h03?????? @@ -141116,7 +141116,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:918:14, endln:918:55 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_constant: , line:918:42, endln:918:55 |vpiDecompile:32'h0c?????? @@ -141130,7 +141130,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:920:14, endln:920:55 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_constant: , line:920:42, endln:920:55 |vpiDecompile:32'h02000??? @@ -141144,7 +141144,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:921:14, endln:921:55 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_constant: , line:921:42, endln:921:55 |vpiDecompile:32'h02004??? @@ -141158,7 +141158,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:922:14, endln:922:55 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_constant: , line:922:42, endln:922:55 |vpiDecompile:32'h0200bff8 @@ -141172,7 +141172,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:923:14, endln:923:55 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_constant: , line:923:42, endln:923:55 |vpiDecompile:32'h0c000??? @@ -141186,7 +141186,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:5661:14, endln:5661:93 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_operation: , line:5661:41, endln:5661:93 |vpiOpType:29 @@ -141235,7 +141235,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:5662:14, endln:5662:93 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiRhs: \_operation: , line:5662:41, endln:5662:93 |vpiOpType:29 @@ -141576,7 +141576,7 @@ design: (work@testbench) |vpiNet: \_logic_net: (work@testbench.clk_i), line:6433:10, endln:6433:15 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiTypespec: \_logic_typespec: , line:6433:10, endln:6433:10 |vpiName:clk_i @@ -141584,7 +141584,7 @@ design: (work@testbench) |vpiNet: \_logic_net: (work@testbench.reset_i), line:6434:12, endln:6434:19 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiTypespec: \_logic_typespec: , line:6434:12, endln:6434:12 |vpiName:reset_i @@ -141592,7 +141592,7 @@ design: (work@testbench) |vpiNet: \_logic_net: (work@testbench.dram_clk_i), line:6435:12, endln:6435:22 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiTypespec: \_logic_typespec: , line:6435:12, endln:6435:12 |vpiName:dram_clk_i @@ -141600,7 +141600,7 @@ design: (work@testbench) |vpiNet: \_logic_net: (work@testbench.dram_reset_i), line:6436:12, endln:6436:24 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiTypespec: \_logic_typespec: , line:6436:12, endln:6436:12 |vpiName:dram_reset_i @@ -141637,7 +141637,7 @@ design: (work@testbench) |vpiPort: \_port: (clk_i), line:6433:10, endln:6433:15 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiName:clk_i |vpiDirection:1 |vpiLowConn: @@ -141651,11 +141651,11 @@ design: (work@testbench) |vpiTypedef: \_logic_typespec: , line:6433:10, endln:6433:10 |vpiInstance: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiPort: \_port: (reset_i), line:6434:12, endln:6434:19 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiName:reset_i |vpiDirection:1 |vpiLowConn: @@ -141669,11 +141669,11 @@ design: (work@testbench) |vpiTypedef: \_logic_typespec: , line:6434:12, endln:6434:12 |vpiInstance: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiPort: \_port: (dram_clk_i), line:6435:12, endln:6435:22 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiName:dram_clk_i |vpiDirection:1 |vpiLowConn: @@ -141687,11 +141687,11 @@ design: (work@testbench) |vpiTypedef: \_logic_typespec: , line:6435:12, endln:6435:12 |vpiInstance: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiPort: \_port: (dram_reset_i), line:6436:12, endln:6436:24 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiName:dram_reset_i |vpiDirection:1 |vpiLowConn: @@ -141705,11 +141705,11 @@ design: (work@testbench) |vpiTypedef: \_logic_typespec: , line:6436:12, endln:6436:12 |vpiInstance: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiGenScopeArray: \_gen_scope_array: (work@testbench.genblk1), line:6439:2, endln:6499:8 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BlackParrotConf/dut.sv, line:6086:1, endln:6503:10 |vpiName:genblk1 |vpiFullName:work@testbench.genblk1 |vpiGenScope: diff --git a/tests/BlackParrotMuteErrors/BlackParrotMuteErrors.log b/tests/BlackParrotMuteErrors/BlackParrotMuteErrors.log index d836262038..4d7b30b8cf 100644 --- a/tests/BlackParrotMuteErrors/BlackParrotMuteErrors.log +++ b/tests/BlackParrotMuteErrors/BlackParrotMuteErrors.log @@ -6664,7 +6664,7 @@ integer_var 6 io_decl 19 logic_typespec 2801 logic_var 1 -module 47 +module_inst 47 operation 659 package 14 packed_array_typespec 36 @@ -6713,7 +6713,7 @@ integer_var 10 io_decl 51 logic_typespec 4353 logic_var 1 -module 67 +module_inst 67 operation 1481 package 14 packed_array_typespec 36 @@ -24396,7 +24396,7 @@ design: (work@otp_ctrl) |vpiTypedef: \_struct_typespec: (otp_ctrl_reg_pkg::otp_ctrl_hw2reg_creator_sw_cfg_digest_mreg_t), line:260:11, endln:260:17 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiName:otp_ctrl_reg_pkg::otp_ctrl_hw2reg_creator_sw_cfg_digest_mreg_t |vpiInstance: \_package: otp_ctrl_part_pkg (otp_ctrl_part_pkg::), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:790:1, endln:875:11 @@ -24440,7 +24440,7 @@ design: (work@otp_ctrl) |vpiTypedef: \_struct_typespec: (otp_ctrl_reg_pkg::otp_ctrl_hw2reg_direct_access_rdata_mreg_t), line:256:11, endln:256:17 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiName:otp_ctrl_reg_pkg::otp_ctrl_hw2reg_direct_access_rdata_mreg_t |vpiInstance: \_package: otp_ctrl_part_pkg (otp_ctrl_part_pkg::), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:790:1, endln:875:11 @@ -24484,7 +24484,7 @@ design: (work@otp_ctrl) |vpiTypedef: \_struct_typespec: (otp_ctrl_reg_pkg::otp_ctrl_hw2reg_direct_access_regwen_reg_t), line:252:11, endln:252:17 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiName:otp_ctrl_reg_pkg::otp_ctrl_hw2reg_direct_access_regwen_reg_t |vpiInstance: \_package: otp_ctrl_part_pkg (otp_ctrl_part_pkg::), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:790:1, endln:875:11 @@ -24508,7 +24508,7 @@ design: (work@otp_ctrl) |vpiTypedef: \_struct_typespec: (otp_ctrl_reg_pkg::otp_ctrl_hw2reg_err_code_mreg_t), line:248:11, endln:248:17 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiName:otp_ctrl_reg_pkg::otp_ctrl_hw2reg_err_code_mreg_t |vpiInstance: \_package: otp_ctrl_part_pkg (otp_ctrl_part_pkg::), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:790:1, endln:875:11 @@ -24552,7 +24552,7 @@ design: (work@otp_ctrl) |vpiTypedef: \_struct_typespec: (otp_ctrl_reg_pkg::otp_ctrl_hw2reg_hw_cfg_digest_mreg_t), line:268:11, endln:268:17 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiName:otp_ctrl_reg_pkg::otp_ctrl_hw2reg_hw_cfg_digest_mreg_t |vpiInstance: \_package: otp_ctrl_part_pkg (otp_ctrl_part_pkg::), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:790:1, endln:875:11 @@ -24596,7 +24596,7 @@ design: (work@otp_ctrl) |vpiTypedef: \_struct_typespec: (otp_ctrl_reg_pkg::otp_ctrl_hw2reg_intr_state_reg_t), line:189:11, endln:189:17 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiName:otp_ctrl_reg_pkg::otp_ctrl_hw2reg_intr_state_reg_t |vpiInstance: \_package: otp_ctrl_part_pkg (otp_ctrl_part_pkg::), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:790:1, endln:875:11 @@ -24702,7 +24702,7 @@ design: (work@otp_ctrl) |vpiTypedef: \_struct_typespec: (otp_ctrl_reg_pkg::otp_ctrl_hw2reg_owner_sw_cfg_digest_mreg_t), line:264:11, endln:264:17 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiName:otp_ctrl_reg_pkg::otp_ctrl_hw2reg_owner_sw_cfg_digest_mreg_t |vpiInstance: \_package: otp_ctrl_part_pkg (otp_ctrl_part_pkg::), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:790:1, endln:875:11 @@ -24746,7 +24746,7 @@ design: (work@otp_ctrl) |vpiTypedef: \_struct_typespec: (otp_ctrl_reg_pkg::otp_ctrl_hw2reg_secret0_digest_mreg_t), line:272:11, endln:272:17 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiName:otp_ctrl_reg_pkg::otp_ctrl_hw2reg_secret0_digest_mreg_t |vpiInstance: \_package: otp_ctrl_part_pkg (otp_ctrl_part_pkg::), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:790:1, endln:875:11 @@ -24790,7 +24790,7 @@ design: (work@otp_ctrl) |vpiTypedef: \_struct_typespec: (otp_ctrl_reg_pkg::otp_ctrl_hw2reg_secret1_digest_mreg_t), line:276:11, endln:276:17 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiName:otp_ctrl_reg_pkg::otp_ctrl_hw2reg_secret1_digest_mreg_t |vpiInstance: \_package: otp_ctrl_part_pkg (otp_ctrl_part_pkg::), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:790:1, endln:875:11 @@ -24834,7 +24834,7 @@ design: (work@otp_ctrl) |vpiTypedef: \_struct_typespec: (otp_ctrl_reg_pkg::otp_ctrl_hw2reg_secret2_digest_mreg_t), line:280:11, endln:280:17 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiName:otp_ctrl_reg_pkg::otp_ctrl_hw2reg_secret2_digest_mreg_t |vpiInstance: \_package: otp_ctrl_part_pkg (otp_ctrl_part_pkg::), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:790:1, endln:875:11 @@ -24878,7 +24878,7 @@ design: (work@otp_ctrl) |vpiTypedef: \_struct_typespec: (otp_ctrl_reg_pkg::otp_ctrl_hw2reg_status_reg_t), line:200:11, endln:200:17 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiName:otp_ctrl_reg_pkg::otp_ctrl_hw2reg_status_reg_t |vpiInstance: \_package: otp_ctrl_part_pkg (otp_ctrl_part_pkg::), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:790:1, endln:875:11 @@ -25381,7 +25381,7 @@ design: (work@otp_ctrl) |vpiTypedef: \_struct_typespec: (otp_ctrl_reg_pkg::otp_ctrl_hw2reg_t), line:307:11, endln:307:17 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiName:otp_ctrl_reg_pkg::otp_ctrl_hw2reg_t |vpiInstance: \_package: otp_ctrl_part_pkg (otp_ctrl_part_pkg::), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:790:1, endln:875:11 @@ -25729,7 +25729,7 @@ design: (work@otp_ctrl) |vpiTypedef: \_enum_typespec: (otp_ctrl_reg_pkg::otp_ctrl_id_e), line:363:3, endln:397:19 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiName:otp_ctrl_reg_pkg::otp_ctrl_id_e |vpiInstance: \_package: otp_ctrl_part_pkg (otp_ctrl_part_pkg::), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:790:1, endln:875:11 @@ -25939,7 +25939,7 @@ design: (work@otp_ctrl) |vpiTypedef: \_struct_typespec: (otp_ctrl_reg_pkg::otp_ctrl_reg2hw_alert_test_reg_t), line:123:11, endln:123:17 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiName:otp_ctrl_reg_pkg::otp_ctrl_reg2hw_alert_test_reg_t |vpiInstance: \_package: otp_ctrl_part_pkg (otp_ctrl_part_pkg::), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:790:1, endln:875:11 @@ -26045,7 +26045,7 @@ design: (work@otp_ctrl) |vpiTypedef: \_struct_typespec: (otp_ctrl_reg_pkg::otp_ctrl_reg2hw_check_timeout_reg_t), line:168:11, endln:168:17 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiName:otp_ctrl_reg_pkg::otp_ctrl_reg2hw_check_timeout_reg_t |vpiInstance: \_package: otp_ctrl_part_pkg (otp_ctrl_part_pkg::), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:790:1, endln:875:11 @@ -26089,7 +26089,7 @@ design: (work@otp_ctrl) |vpiTypedef: \_struct_typespec: (otp_ctrl_reg_pkg::otp_ctrl_reg2hw_check_trigger_reg_t), line:157:11, endln:157:17 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiName:otp_ctrl_reg_pkg::otp_ctrl_reg2hw_check_trigger_reg_t |vpiInstance: \_package: otp_ctrl_part_pkg (otp_ctrl_part_pkg::), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:790:1, endln:875:11 @@ -26195,7 +26195,7 @@ design: (work@otp_ctrl) |vpiTypedef: \_struct_typespec: (otp_ctrl_reg_pkg::otp_ctrl_reg2hw_consistency_check_period_reg_t), line:176:11, endln:176:17 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiName:otp_ctrl_reg_pkg::otp_ctrl_reg2hw_consistency_check_period_reg_t |vpiInstance: \_package: otp_ctrl_part_pkg (otp_ctrl_part_pkg::), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:790:1, endln:875:11 @@ -26239,7 +26239,7 @@ design: (work@otp_ctrl) |vpiTypedef: \_struct_typespec: (otp_ctrl_reg_pkg::otp_ctrl_reg2hw_creator_sw_cfg_read_lock_reg_t), line:180:11, endln:180:17 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiName:otp_ctrl_reg_pkg::otp_ctrl_reg2hw_creator_sw_cfg_read_lock_reg_t |vpiInstance: \_package: otp_ctrl_part_pkg (otp_ctrl_part_pkg::), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:790:1, endln:875:11 @@ -26263,7 +26263,7 @@ design: (work@otp_ctrl) |vpiTypedef: \_struct_typespec: (otp_ctrl_reg_pkg::otp_ctrl_reg2hw_direct_access_address_reg_t), line:149:11, endln:149:17 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiName:otp_ctrl_reg_pkg::otp_ctrl_reg2hw_direct_access_address_reg_t |vpiInstance: \_package: otp_ctrl_part_pkg (otp_ctrl_part_pkg::), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:790:1, endln:875:11 @@ -26307,7 +26307,7 @@ design: (work@otp_ctrl) |vpiTypedef: \_struct_typespec: (otp_ctrl_reg_pkg::otp_ctrl_reg2hw_direct_access_cmd_reg_t), line:134:11, endln:134:17 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiName:otp_ctrl_reg_pkg::otp_ctrl_reg2hw_direct_access_cmd_reg_t |vpiInstance: \_package: otp_ctrl_part_pkg (otp_ctrl_part_pkg::), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:790:1, endln:875:11 @@ -26462,7 +26462,7 @@ design: (work@otp_ctrl) |vpiTypedef: \_struct_typespec: (otp_ctrl_reg_pkg::otp_ctrl_reg2hw_direct_access_wdata_mreg_t), line:153:11, endln:153:17 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiName:otp_ctrl_reg_pkg::otp_ctrl_reg2hw_direct_access_wdata_mreg_t |vpiInstance: \_package: otp_ctrl_part_pkg (otp_ctrl_part_pkg::), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:790:1, endln:875:11 @@ -26506,7 +26506,7 @@ design: (work@otp_ctrl) |vpiTypedef: \_struct_typespec: (otp_ctrl_reg_pkg::otp_ctrl_reg2hw_integrity_check_period_reg_t), line:172:11, endln:172:17 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiName:otp_ctrl_reg_pkg::otp_ctrl_reg2hw_integrity_check_period_reg_t |vpiInstance: \_package: otp_ctrl_part_pkg (otp_ctrl_part_pkg::), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:790:1, endln:875:11 @@ -26550,7 +26550,7 @@ design: (work@otp_ctrl) |vpiTypedef: \_struct_typespec: (otp_ctrl_reg_pkg::otp_ctrl_reg2hw_intr_enable_reg_t), line:103:11, endln:103:17 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiName:otp_ctrl_reg_pkg::otp_ctrl_reg2hw_intr_enable_reg_t |vpiInstance: \_package: otp_ctrl_part_pkg (otp_ctrl_part_pkg::), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:790:1, endln:875:11 @@ -26624,7 +26624,7 @@ design: (work@otp_ctrl) |vpiTypedef: \_struct_typespec: (otp_ctrl_reg_pkg::otp_ctrl_reg2hw_intr_state_reg_t), line:94:11, endln:94:17 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiName:otp_ctrl_reg_pkg::otp_ctrl_reg2hw_intr_state_reg_t |vpiInstance: \_package: otp_ctrl_part_pkg (otp_ctrl_part_pkg::), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:790:1, endln:875:11 @@ -26698,7 +26698,7 @@ design: (work@otp_ctrl) |vpiTypedef: \_struct_typespec: (otp_ctrl_reg_pkg::otp_ctrl_reg2hw_intr_test_reg_t), line:112:11, endln:112:17 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiName:otp_ctrl_reg_pkg::otp_ctrl_reg2hw_intr_test_reg_t |vpiInstance: \_package: otp_ctrl_part_pkg (otp_ctrl_part_pkg::), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:790:1, endln:875:11 @@ -26804,7 +26804,7 @@ design: (work@otp_ctrl) |vpiTypedef: \_struct_typespec: (otp_ctrl_reg_pkg::otp_ctrl_reg2hw_owner_sw_cfg_read_lock_reg_t), line:184:11, endln:184:17 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiName:otp_ctrl_reg_pkg::otp_ctrl_reg2hw_owner_sw_cfg_read_lock_reg_t |vpiInstance: \_package: otp_ctrl_part_pkg (otp_ctrl_part_pkg::), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:790:1, endln:875:11 @@ -26828,7 +26828,7 @@ design: (work@otp_ctrl) |vpiTypedef: \_struct_typespec: (otp_ctrl_reg_pkg::otp_ctrl_reg2hw_t), line:288:11, endln:288:17 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiName:otp_ctrl_reg_pkg::otp_ctrl_reg2hw_t |vpiInstance: \_package: otp_ctrl_part_pkg (otp_ctrl_part_pkg::), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:790:1, endln:875:11 @@ -33956,7 +33956,7 @@ design: (work@otp_ctrl) |vpiElemTypespec: \_struct_typespec: (otp_ctrl_pkg::part_info_t), line:555:11, endln:555:17 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiName:otp_ctrl_pkg::part_info_t |vpiInstance: \_package: otp_ctrl_part_pkg (otp_ctrl_part_pkg::), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:790:1, endln:875:11 @@ -33969,7 +33969,7 @@ design: (work@otp_ctrl) |vpiTypespec: \_enum_typespec: (otp_ctrl_pkg::part_variant_e), line:549:3, endln:553:20 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiName:otp_ctrl_pkg::part_variant_e |vpiInstance: \_package: otp_ctrl_part_pkg (otp_ctrl_part_pkg::), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:790:1, endln:875:11 @@ -34098,7 +34098,7 @@ design: (work@otp_ctrl) |vpiTypespec: \_enum_typespec: (otp_ctrl_pkg::key_sel_e), line:526:3, endln:530:15 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiName:otp_ctrl_pkg::key_sel_e |vpiInstance: \_package: otp_ctrl_part_pkg (otp_ctrl_part_pkg::), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:790:1, endln:875:11 @@ -47818,7 +47818,7 @@ design: (work@otp_ctrl) |vpiTypedef: \_enum_typespec: (otp_ctrl_pkg::access_e), line:457:3, endln:460:14 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiName:otp_ctrl_pkg::access_e |vpiInstance: \_package: otp_ctrl_part_pkg (otp_ctrl_part_pkg::), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:790:1, endln:875:11 @@ -47859,7 +47859,7 @@ design: (work@otp_ctrl) |vpiTypedef: \_enum_typespec: (otp_ctrl_pkg::dai_cmd_e), line:469:3, endln:473:15 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiName:otp_ctrl_pkg::dai_cmd_e |vpiInstance: \_package: otp_ctrl_part_pkg (otp_ctrl_part_pkg::), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:790:1, endln:875:11 @@ -47906,7 +47906,7 @@ design: (work@otp_ctrl) |vpiTypedef: \_logic_typespec: (otp_ctrl_pkg::digest_const_array_t), line:745:11, endln:745:56 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiName:otp_ctrl_pkg::digest_const_array_t |vpiInstance: \_package: otp_ctrl_part_pkg (otp_ctrl_part_pkg::), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:790:1, endln:875:11 @@ -47949,7 +47949,7 @@ design: (work@otp_ctrl) |vpiTypedef: \_logic_typespec: (otp_ctrl_pkg::digest_iv_array_t), line:754:11, endln:754:58 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiName:otp_ctrl_pkg::digest_iv_array_t |vpiInstance: \_package: otp_ctrl_part_pkg (otp_ctrl_part_pkg::), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:790:1, endln:875:11 @@ -47992,7 +47992,7 @@ design: (work@otp_ctrl) |vpiTypedef: \_enum_typespec: (otp_ctrl_pkg::digest_mode_e), line:540:3, endln:543:19 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiName:otp_ctrl_pkg::digest_mode_e |vpiInstance: \_package: otp_ctrl_part_pkg (otp_ctrl_part_pkg::), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:790:1, endln:875:11 @@ -48033,7 +48033,7 @@ design: (work@otp_ctrl) |vpiTypedef: \_enum_typespec: (otp_ctrl_pkg::digest_sel_e), line:532:3, endln:538:18 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiName:otp_ctrl_pkg::digest_sel_e |vpiInstance: \_package: otp_ctrl_part_pkg (otp_ctrl_part_pkg::), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:790:1, endln:875:11 @@ -48092,7 +48092,7 @@ design: (work@otp_ctrl) |vpiTypedef: \_struct_typespec: (otp_ctrl_pkg::flash_otp_key_req_t), line:651:11, endln:651:17 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiName:otp_ctrl_pkg::flash_otp_key_req_t |vpiInstance: \_package: otp_ctrl_part_pkg (otp_ctrl_part_pkg::), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:790:1, endln:875:11 @@ -48132,7 +48132,7 @@ design: (work@otp_ctrl) |vpiTypedef: \_struct_typespec: (otp_ctrl_pkg::flash_otp_key_rsp_t), line:664:11, endln:664:17 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiName:otp_ctrl_pkg::flash_otp_key_rsp_t |vpiInstance: \_package: otp_ctrl_part_pkg (otp_ctrl_part_pkg::), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:790:1, endln:875:11 @@ -48224,7 +48224,7 @@ design: (work@otp_ctrl) |vpiTypedef: \_logic_typespec: (otp_ctrl_pkg::key_array_t), line:736:11, endln:736:56 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiName:otp_ctrl_pkg::key_array_t |vpiInstance: \_package: otp_ctrl_part_pkg (otp_ctrl_part_pkg::), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:790:1, endln:875:11 @@ -48269,7 +48269,7 @@ design: (work@otp_ctrl) |vpiTypedef: \_struct_typespec: (otp_ctrl_pkg::lc_otp_program_req_t), line:599:11, endln:599:17 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiName:otp_ctrl_pkg::lc_otp_program_req_t |vpiInstance: \_package: otp_ctrl_part_pkg (otp_ctrl_part_pkg::), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:790:1, endln:875:11 @@ -48327,7 +48327,7 @@ design: (work@otp_ctrl) |vpiTypedef: \_struct_typespec: (otp_ctrl_pkg::lc_otp_program_rsp_t), line:605:11, endln:605:17 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiName:otp_ctrl_pkg::lc_otp_program_rsp_t |vpiInstance: \_package: otp_ctrl_part_pkg (otp_ctrl_part_pkg::), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:790:1, endln:875:11 @@ -48367,7 +48367,7 @@ design: (work@otp_ctrl) |vpiTypedef: \_struct_typespec: (otp_ctrl_pkg::lc_otp_token_req_t), line:611:11, endln:611:17 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiName:otp_ctrl_pkg::lc_otp_token_req_t |vpiInstance: \_package: otp_ctrl_part_pkg (otp_ctrl_part_pkg::), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:790:1, endln:875:11 @@ -48408,7 +48408,7 @@ design: (work@otp_ctrl) |vpiTypedef: \_struct_typespec: (otp_ctrl_pkg::lc_otp_token_rsp_t), line:616:11, endln:616:17 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiName:otp_ctrl_pkg::lc_otp_token_rsp_t |vpiInstance: \_package: otp_ctrl_part_pkg (otp_ctrl_part_pkg::), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:790:1, endln:875:11 @@ -48449,7 +48449,7 @@ design: (work@otp_ctrl) |vpiTypedef: \_logic_typespec: (otp_ctrl_pkg::lfsr_perm_t), line:730:11, endln:730:55 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiName:otp_ctrl_pkg::lfsr_perm_t |vpiInstance: \_package: otp_ctrl_part_pkg (otp_ctrl_part_pkg::), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:790:1, endln:875:11 @@ -48492,7 +48492,7 @@ design: (work@otp_ctrl) |vpiTypedef: \_logic_typespec: (otp_ctrl_pkg::lfsr_seed_t), line:729:11, endln:729:32 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiName:otp_ctrl_pkg::lfsr_seed_t |vpiInstance: \_package: otp_ctrl_part_pkg (otp_ctrl_part_pkg::), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:790:1, endln:875:11 @@ -48517,7 +48517,7 @@ design: (work@otp_ctrl) |vpiTypedef: \_logic_typespec: (otp_ctrl_pkg::otbn_key_t), line:636:11, endln:636:35 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiName:otp_ctrl_pkg::otbn_key_t |vpiInstance: \_package: otp_ctrl_part_pkg (otp_ctrl_part_pkg::), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:790:1, endln:875:11 @@ -48542,7 +48542,7 @@ design: (work@otp_ctrl) |vpiTypedef: \_logic_typespec: (otp_ctrl_pkg::otbn_nonce_t), line:637:11, endln:637:37 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiName:otp_ctrl_pkg::otbn_nonce_t |vpiInstance: \_package: otp_ctrl_part_pkg (otp_ctrl_part_pkg::), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:790:1, endln:875:11 @@ -48567,7 +48567,7 @@ design: (work@otp_ctrl) |vpiTypedef: \_struct_typespec: (otp_ctrl_pkg::otbn_otp_key_req_t), line:660:11, endln:660:17 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiName:otp_ctrl_pkg::otbn_otp_key_req_t |vpiInstance: \_package: otp_ctrl_part_pkg (otp_ctrl_part_pkg::), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:790:1, endln:875:11 @@ -48591,7 +48591,7 @@ design: (work@otp_ctrl) |vpiTypedef: \_struct_typespec: (otp_ctrl_pkg::otbn_otp_key_rsp_t), line:686:11, endln:686:17 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiName:otp_ctrl_pkg::otbn_otp_key_rsp_t |vpiInstance: \_package: otp_ctrl_part_pkg (otp_ctrl_part_pkg::), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:790:1, endln:875:11 @@ -48709,7 +48709,7 @@ design: (work@otp_ctrl) |vpiTypedef: \_struct_typespec: (otp_ctrl_pkg::otp_ast_req_t), line:714:11, endln:714:17 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiName:otp_ctrl_pkg::otp_ast_req_t |vpiInstance: \_package: otp_ctrl_part_pkg (otp_ctrl_part_pkg::), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:790:1, endln:875:11 @@ -48753,7 +48753,7 @@ design: (work@otp_ctrl) |vpiTypedef: \_struct_typespec: (otp_ctrl_pkg::otp_ast_rsp_t), line:718:11, endln:718:17 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiName:otp_ctrl_pkg::otp_ast_rsp_t |vpiInstance: \_package: otp_ctrl_part_pkg (otp_ctrl_part_pkg::), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:790:1, endln:875:11 @@ -48851,7 +48851,7 @@ design: (work@otp_ctrl) |vpiTypedef: \_enum_typespec: (otp_ctrl_pkg::otp_err_e), line:490:3, endln:499:15 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiName:otp_ctrl_pkg::otp_err_e |vpiInstance: \_package: otp_ctrl_part_pkg (otp_ctrl_part_pkg::), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:790:1, endln:875:11 @@ -48928,7 +48928,7 @@ design: (work@otp_ctrl) |vpiTypedef: \_struct_typespec: (otp_ctrl_pkg::otp_keymgr_key_t), line:639:11, endln:639:17 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiName:otp_ctrl_pkg::otp_keymgr_key_t |vpiInstance: \_package: otp_ctrl_part_pkg (otp_ctrl_part_pkg::), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:790:1, endln:875:11 @@ -49024,7 +49024,7 @@ design: (work@otp_ctrl) |vpiTypedef: \_struct_typespec: (otp_ctrl_pkg::otp_lc_data_t), line:573:11, endln:573:17 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiName:otp_ctrl_pkg::otp_lc_data_t |vpiInstance: \_package: otp_ctrl_part_pkg (otp_ctrl_part_pkg::), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:790:1, endln:875:11 @@ -49184,7 +49184,7 @@ design: (work@otp_ctrl) |vpiTypedef: \_struct_typespec: (otp_ctrl_pkg::otp_pwr_state_t), line:705:11, endln:705:17 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiName:otp_ctrl_pkg::otp_pwr_state_t |vpiInstance: \_package: otp_ctrl_part_pkg (otp_ctrl_part_pkg::), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:790:1, endln:875:11 @@ -49208,7 +49208,7 @@ design: (work@otp_ctrl) |vpiTypedef: \_enum_typespec: (otp_ctrl_pkg::otp_scrmbl_cmd_e), line:511:3, endln:518:22 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiName:otp_ctrl_pkg::otp_scrmbl_cmd_e |vpiInstance: \_package: otp_ctrl_part_pkg (otp_ctrl_part_pkg::), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:790:1, endln:875:11 @@ -49273,7 +49273,7 @@ design: (work@otp_ctrl) |vpiTypedef: \_struct_typespec: (otp_ctrl_pkg::part_access_t), line:463:11, endln:463:17 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiName:otp_ctrl_pkg::part_access_t |vpiInstance: \_package: otp_ctrl_part_pkg (otp_ctrl_part_pkg::), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:790:1, endln:875:11 @@ -49309,7 +49309,7 @@ design: (work@otp_ctrl) |vpiTypedef: \_struct_typespec: (otp_ctrl_pkg::pwr_otp_init_req_t), line:697:11, endln:697:17 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiName:otp_ctrl_pkg::pwr_otp_init_req_t |vpiInstance: \_package: otp_ctrl_part_pkg (otp_ctrl_part_pkg::), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:790:1, endln:875:11 @@ -49333,7 +49333,7 @@ design: (work@otp_ctrl) |vpiTypedef: \_struct_typespec: (otp_ctrl_pkg::pwr_otp_init_rsp_t), line:701:11, endln:701:17 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiName:otp_ctrl_pkg::pwr_otp_init_rsp_t |vpiInstance: \_package: otp_ctrl_part_pkg (otp_ctrl_part_pkg::), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:790:1, endln:875:11 @@ -49357,7 +49357,7 @@ design: (work@otp_ctrl) |vpiTypedef: \_logic_typespec: (otp_ctrl_pkg::sram_key_t), line:634:11, endln:634:35 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiName:otp_ctrl_pkg::sram_key_t |vpiInstance: \_package: otp_ctrl_part_pkg (otp_ctrl_part_pkg::), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:790:1, endln:875:11 @@ -49382,7 +49382,7 @@ design: (work@otp_ctrl) |vpiTypedef: \_logic_typespec: (otp_ctrl_pkg::sram_nonce_t), line:635:11, endln:635:37 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiName:otp_ctrl_pkg::sram_nonce_t |vpiInstance: \_package: otp_ctrl_part_pkg (otp_ctrl_part_pkg::), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:790:1, endln:875:11 @@ -49407,7 +49407,7 @@ design: (work@otp_ctrl) |vpiTypedef: \_struct_typespec: (otp_ctrl_pkg::sram_otp_key_req_t), line:656:11, endln:656:17 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiName:otp_ctrl_pkg::sram_otp_key_req_t |vpiInstance: \_package: otp_ctrl_part_pkg (otp_ctrl_part_pkg::), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:790:1, endln:875:11 @@ -49431,7 +49431,7 @@ design: (work@otp_ctrl) |vpiTypedef: \_struct_typespec: (otp_ctrl_pkg::sram_otp_key_rsp_t), line:679:11, endln:679:17 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiName:otp_ctrl_pkg::sram_otp_key_rsp_t |vpiInstance: \_package: otp_ctrl_part_pkg (otp_ctrl_part_pkg::), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:790:1, endln:875:11 @@ -83464,14 +83464,14 @@ design: (work@otp_ctrl) \_int_typespec: |vpiSigned:1 |uhdmallModules: -\_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 +\_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiParent: \_design: (work@otp_ctrl) |vpiFullName:work@otp_ctrl |vpiParameter: \_parameter: (work@otp_ctrl.ConstSelWidth), line:522:17, endln:522:30 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |INT:3 |vpiTypespec: \_int_typespec: , line:522:13, endln:522:16 @@ -83487,7 +83487,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.CreatorRootKeyShare0Offset), line:77:17, endln:77:43 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:1888 |vpiTypespec: \_int_typespec: , line:77:13, endln:77:16 @@ -83503,7 +83503,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.CreatorRootKeyShare0Size), line:78:17, endln:78:41 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:32 |vpiTypespec: \_int_typespec: , line:78:13, endln:78:16 @@ -83519,7 +83519,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.CreatorRootKeyShare1Offset), line:79:17, endln:79:43 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:1920 |vpiTypespec: \_int_typespec: , line:79:13, endln:79:16 @@ -83535,7 +83535,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.CreatorRootKeyShare1Size), line:80:17, endln:80:41 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:32 |vpiTypespec: \_int_typespec: , line:80:13, endln:80:16 @@ -83551,7 +83551,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.CreatorSwCfgContentOffset), line:37:17, endln:37:42 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:0 |vpiTypespec: \_int_typespec: , line:37:13, endln:37:16 @@ -83567,7 +83567,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.CreatorSwCfgContentSize), line:38:17, endln:38:40 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:760 |vpiTypespec: \_int_typespec: , line:38:13, endln:38:16 @@ -83583,7 +83583,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.CreatorSwCfgDigestOffset), line:39:17, endln:39:41 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:760 |vpiTypespec: \_int_typespec: , line:39:13, endln:39:16 @@ -83599,7 +83599,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.CreatorSwCfgDigestSize), line:40:17, endln:40:39 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:8 |vpiTypespec: \_int_typespec: , line:40:13, endln:40:16 @@ -83615,7 +83615,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.CreatorSwCfgOffset), line:35:17, endln:35:35 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:0 |vpiTypespec: \_int_typespec: , line:35:13, endln:35:16 @@ -83631,7 +83631,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.CreatorSwCfgSize), line:36:17, endln:36:33 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:768 |vpiTypespec: \_int_typespec: , line:36:13, endln:36:16 @@ -83647,7 +83647,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.DaiCmdWidth), line:468:17, endln:468:28 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:3 |vpiTypespec: \_int_typespec: , line:468:13, endln:468:16 @@ -83663,7 +83663,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.DeviceIdOffset), line:49:17, endln:49:31 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:1536 |vpiTypespec: \_int_typespec: , line:49:13, endln:49:16 @@ -83679,7 +83679,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.DeviceIdSize), line:50:17, endln:50:29 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:32 |vpiTypespec: \_int_typespec: , line:50:13, endln:50:16 @@ -83695,7 +83695,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.EdnDataWidth), line:448:17, endln:448:29 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:64 |vpiTypespec: \_int_typespec: , line:448:13, endln:448:16 @@ -83711,7 +83711,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.FLASH_OTP_KEY_RSP_DEFAULT), line:672:33, endln:672:58 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiTypespec: \_struct_typespec: (otp_ctrl_pkg::flash_otp_key_rsp_t), line:664:11, endln:664:17 |vpiParent: @@ -83810,7 +83810,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.FlashAddrKeySeedOffset), line:65:17, endln:65:39 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:1784 |vpiTypespec: \_int_typespec: , line:65:13, endln:65:16 @@ -83826,7 +83826,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.FlashAddrKeySeedSize), line:66:17, endln:66:37 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:32 |vpiTypespec: \_int_typespec: , line:66:13, endln:66:16 @@ -83842,7 +83842,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.FlashDataKeySeedOffset), line:67:17, endln:67:39 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:1816 |vpiTypespec: \_int_typespec: , line:67:13, endln:67:16 @@ -83858,7 +83858,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.FlashDataKeySeedSize), line:68:17, endln:68:37 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:32 |vpiTypespec: \_int_typespec: , line:68:13, endln:68:16 @@ -83874,7 +83874,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.FlashKeySeedWidth), line:625:17, endln:625:34 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:256 |vpiTypespec: \_int_typespec: , line:625:13, endln:625:16 @@ -83890,7 +83890,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.FlashKeyWidth), line:628:17, endln:628:30 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:128 |vpiTypespec: \_int_typespec: , line:628:13, endln:628:16 @@ -83906,7 +83906,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.HwCfgContentOffset), line:51:17, endln:51:35 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:1568 |vpiTypespec: \_int_typespec: , line:51:13, endln:51:16 @@ -83922,7 +83922,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.HwCfgContentSize), line:52:17, endln:52:33 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:168 |vpiTypespec: \_int_typespec: , line:52:13, endln:52:16 @@ -83938,7 +83938,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.HwCfgDigestOffset), line:53:17, endln:53:34 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:1736 |vpiTypespec: \_int_typespec: , line:53:13, endln:53:16 @@ -83954,7 +83954,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.HwCfgDigestSize), line:54:17, endln:54:32 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:8 |vpiTypespec: \_int_typespec: , line:54:13, endln:54:16 @@ -83970,7 +83970,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.HwCfgOffset), line:47:17, endln:47:28 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:1536 |vpiTypespec: \_int_typespec: , line:47:13, endln:47:16 @@ -83986,7 +83986,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.HwCfgSize), line:48:17, endln:48:26 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:208 |vpiTypespec: \_int_typespec: , line:48:13, endln:48:16 @@ -84002,7 +84002,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.KeyMgrKeyWidth), line:627:17, endln:627:31 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:256 |vpiTypespec: \_int_typespec: , line:627:13, endln:627:16 @@ -84018,7 +84018,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.LcStateOffset), line:85:17, endln:85:30 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:1992 |vpiTypespec: \_int_typespec: , line:85:13, endln:85:16 @@ -84034,7 +84034,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.LcStateSize), line:86:17, endln:86:28 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:24 |vpiTypespec: \_int_typespec: , line:86:13, endln:86:16 @@ -84050,7 +84050,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.LcTransitionCntOffset), line:87:17, endln:87:38 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:2016 |vpiTypespec: \_int_typespec: , line:87:13, endln:87:16 @@ -84066,7 +84066,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.LcTransitionCntSize), line:88:17, endln:88:36 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:32 |vpiTypespec: \_int_typespec: , line:88:13, endln:88:16 @@ -84082,7 +84082,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.LfsrWidth), line:728:18, endln:728:27 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:40 |vpiTypespec: \_int_typespec: , line:728:14, endln:728:17 @@ -84099,7 +84099,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.LifeCycleOffset), line:83:17, endln:83:32 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:1992 |vpiTypespec: \_int_typespec: , line:83:13, endln:83:16 @@ -84115,7 +84115,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.LifeCycleSize), line:84:17, endln:84:30 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:56 |vpiTypespec: \_int_typespec: , line:84:13, endln:84:16 @@ -84131,7 +84131,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.NumAlerts), line:89:17, endln:89:26 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:2 |vpiTypespec: \_int_typespec: , line:89:13, endln:89:16 @@ -84147,7 +84147,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.NumDaiWords), line:30:17, endln:30:28 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:2 |vpiTypespec: \_int_typespec: , line:30:13, endln:30:16 @@ -84163,7 +84163,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.NumDebugWindowWords), line:33:17, endln:33:36 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:16 |vpiTypespec: \_int_typespec: , line:33:13, endln:33:16 @@ -84179,7 +84179,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.NumDigestSets), line:521:17, endln:521:30 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:5 |vpiTypespec: \_int_typespec: , line:521:13, endln:521:16 @@ -84195,7 +84195,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.NumDigestWords), line:31:17, endln:31:31 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:2 |vpiTypespec: \_int_typespec: , line:31:13, endln:31:16 @@ -84211,7 +84211,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.NumErrorEntries), line:29:17, endln:29:32 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:9 |vpiTypespec: \_int_typespec: , line:29:13, endln:29:16 @@ -84227,7 +84227,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.NumPart), line:34:17, endln:34:24 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:7 |vpiTypespec: \_int_typespec: , line:34:13, endln:34:16 @@ -84243,7 +84243,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.NumPartWidth), line:450:17, endln:450:29 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |INT:3 |vpiTypespec: \_int_typespec: , line:450:13, endln:450:16 @@ -84259,7 +84259,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.NumPresentRounds), line:508:17, endln:508:33 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:31 |vpiTypespec: \_int_typespec: , line:508:13, endln:508:16 @@ -84275,7 +84275,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.NumScrmblKeys), line:520:17, endln:520:30 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:3 |vpiTypespec: \_int_typespec: , line:520:13, endln:520:16 @@ -84291,7 +84291,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.NumSramKeyReqSlots), line:27:17, endln:27:35 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:2 |vpiTypespec: \_int_typespec: , line:27:13, endln:27:16 @@ -84307,7 +84307,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.NumSwCfgWindowWords), line:32:17, endln:32:36 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:512 |vpiTypespec: \_int_typespec: , line:32:13, endln:32:16 @@ -84323,7 +84323,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OTP_CTRL_ALERT_TEST_OFFSET), line:325:26, endln:325:52 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |HEX:c |vpiTypespec: \_logic_typespec: , line:325:13, endln:325:25 @@ -84357,7 +84357,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OTP_CTRL_CHECK_REGWEN_OFFSET), line:337:26, endln:337:54 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |HEX:3c |vpiTypespec: \_logic_typespec: , line:337:13, endln:337:25 @@ -84391,7 +84391,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OTP_CTRL_CHECK_TIMEOUT_OFFSET), line:338:26, endln:338:55 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |HEX:40 |vpiTypespec: \_logic_typespec: , line:338:13, endln:338:25 @@ -84425,7 +84425,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OTP_CTRL_CHECK_TRIGGER_OFFSET), line:336:26, endln:336:55 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |HEX:38 |vpiTypespec: \_logic_typespec: , line:336:13, endln:336:25 @@ -84459,7 +84459,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OTP_CTRL_CHECK_TRIGGER_REGWEN_OFFSET), line:335:26, endln:335:62 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |HEX:34 |vpiTypespec: \_logic_typespec: , line:335:13, endln:335:25 @@ -84493,7 +84493,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OTP_CTRL_CONSISTENCY_CHECK_PERIOD_OFFSET), line:340:26, endln:340:66 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |HEX:48 |vpiTypespec: \_logic_typespec: , line:340:13, endln:340:25 @@ -84527,7 +84527,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_OFFSET), line:343:26, endln:343:65 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |HEX:54 |vpiTypespec: \_logic_typespec: , line:343:13, endln:343:25 @@ -84561,7 +84561,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_OFFSET), line:344:26, endln:344:65 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |HEX:58 |vpiTypespec: \_logic_typespec: , line:344:13, endln:344:25 @@ -84595,7 +84595,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OTP_CTRL_CREATOR_SW_CFG_READ_LOCK_OFFSET), line:341:26, endln:341:66 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |HEX:4c |vpiTypespec: \_logic_typespec: , line:341:13, endln:341:25 @@ -84629,7 +84629,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OTP_CTRL_DIRECT_ACCESS_ADDRESS_OFFSET), line:330:26, endln:330:63 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |HEX:20 |vpiTypespec: \_logic_typespec: , line:330:13, endln:330:25 @@ -84663,7 +84663,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OTP_CTRL_DIRECT_ACCESS_CMD_OFFSET), line:329:26, endln:329:59 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |HEX:1c |vpiTypespec: \_logic_typespec: , line:329:13, endln:329:25 @@ -84697,7 +84697,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OTP_CTRL_DIRECT_ACCESS_RDATA_0_OFFSET), line:333:26, endln:333:63 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |HEX:2c |vpiTypespec: \_logic_typespec: , line:333:13, endln:333:25 @@ -84731,7 +84731,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OTP_CTRL_DIRECT_ACCESS_RDATA_1_OFFSET), line:334:26, endln:334:63 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |HEX:30 |vpiTypespec: \_logic_typespec: , line:334:13, endln:334:25 @@ -84765,7 +84765,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OTP_CTRL_DIRECT_ACCESS_REGWEN_OFFSET), line:328:26, endln:328:62 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |HEX:18 |vpiTypespec: \_logic_typespec: , line:328:13, endln:328:25 @@ -84799,7 +84799,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OTP_CTRL_DIRECT_ACCESS_WDATA_0_OFFSET), line:331:26, endln:331:63 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |HEX:24 |vpiTypespec: \_logic_typespec: , line:331:13, endln:331:25 @@ -84833,7 +84833,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OTP_CTRL_DIRECT_ACCESS_WDATA_1_OFFSET), line:332:26, endln:332:63 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |HEX:28 |vpiTypespec: \_logic_typespec: , line:332:13, endln:332:25 @@ -84867,7 +84867,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OTP_CTRL_ERR_CODE_OFFSET), line:327:26, endln:327:50 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |HEX:14 |vpiTypespec: \_logic_typespec: , line:327:13, endln:327:25 @@ -84901,7 +84901,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OTP_CTRL_HW_CFG_DIGEST_0_OFFSET), line:347:26, endln:347:57 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |HEX:64 |vpiTypespec: \_logic_typespec: , line:347:13, endln:347:25 @@ -84935,7 +84935,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OTP_CTRL_HW_CFG_DIGEST_1_OFFSET), line:348:26, endln:348:57 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |HEX:68 |vpiTypespec: \_logic_typespec: , line:348:13, endln:348:25 @@ -84969,7 +84969,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OTP_CTRL_INTEGRITY_CHECK_PERIOD_OFFSET), line:339:26, endln:339:64 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |HEX:44 |vpiTypespec: \_logic_typespec: , line:339:13, endln:339:25 @@ -85003,7 +85003,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OTP_CTRL_INTR_ENABLE_OFFSET), line:323:26, endln:323:53 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |HEX:4 |vpiTypespec: \_logic_typespec: , line:323:13, endln:323:25 @@ -85037,7 +85037,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OTP_CTRL_INTR_STATE_OFFSET), line:322:26, endln:322:52 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |HEX:0 |vpiTypespec: \_logic_typespec: , line:322:13, endln:322:25 @@ -85071,7 +85071,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OTP_CTRL_INTR_TEST_OFFSET), line:324:26, endln:324:51 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |HEX:8 |vpiTypespec: \_logic_typespec: , line:324:13, endln:324:25 @@ -85105,7 +85105,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OTP_CTRL_OWNER_SW_CFG_DIGEST_0_OFFSET), line:345:26, endln:345:63 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |HEX:5c |vpiTypespec: \_logic_typespec: , line:345:13, endln:345:25 @@ -85139,7 +85139,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OTP_CTRL_OWNER_SW_CFG_DIGEST_1_OFFSET), line:346:26, endln:346:63 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |HEX:60 |vpiTypespec: \_logic_typespec: , line:346:13, endln:346:25 @@ -85173,7 +85173,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OTP_CTRL_OWNER_SW_CFG_READ_LOCK_OFFSET), line:342:26, endln:342:64 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |HEX:50 |vpiTypespec: \_logic_typespec: , line:342:13, endln:342:25 @@ -85207,7 +85207,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OTP_CTRL_PERMIT), line:400:25, endln:400:40 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiSize:33 |vpiTypespec: \_array_typespec: @@ -85309,7 +85309,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OTP_CTRL_SECRET0_DIGEST_0_OFFSET), line:349:26, endln:349:58 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |HEX:6c |vpiTypespec: \_logic_typespec: , line:349:13, endln:349:25 @@ -85343,7 +85343,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OTP_CTRL_SECRET0_DIGEST_1_OFFSET), line:350:26, endln:350:58 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |HEX:70 |vpiTypespec: \_logic_typespec: , line:350:13, endln:350:25 @@ -85377,7 +85377,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OTP_CTRL_SECRET1_DIGEST_0_OFFSET), line:351:26, endln:351:58 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |HEX:74 |vpiTypespec: \_logic_typespec: , line:351:13, endln:351:25 @@ -85411,7 +85411,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OTP_CTRL_SECRET1_DIGEST_1_OFFSET), line:352:26, endln:352:58 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |HEX:78 |vpiTypespec: \_logic_typespec: , line:352:13, endln:352:25 @@ -85445,7 +85445,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OTP_CTRL_SECRET2_DIGEST_0_OFFSET), line:353:26, endln:353:58 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |HEX:7c |vpiTypespec: \_logic_typespec: , line:353:13, endln:353:25 @@ -85479,7 +85479,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OTP_CTRL_SECRET2_DIGEST_1_OFFSET), line:354:26, endln:354:58 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |HEX:80 |vpiTypespec: \_logic_typespec: , line:354:13, endln:354:25 @@ -85513,7 +85513,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OTP_CTRL_STATUS_OFFSET), line:326:26, endln:326:48 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |HEX:10 |vpiTypespec: \_logic_typespec: , line:326:13, endln:326:25 @@ -85547,7 +85547,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OTP_CTRL_SW_CFG_WINDOW_OFFSET), line:357:26, endln:357:55 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |HEX:1000 |vpiTypespec: \_logic_typespec: , line:357:13, endln:357:25 @@ -85581,7 +85581,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OTP_CTRL_SW_CFG_WINDOW_SIZE), line:358:26, endln:358:53 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |HEX:800 |vpiTypespec: \_logic_typespec: , line:358:13, endln:358:25 @@ -85615,7 +85615,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OTP_CTRL_TEST_ACCESS_OFFSET), line:359:26, endln:359:53 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |HEX:2000 |vpiTypespec: \_logic_typespec: , line:359:13, endln:359:25 @@ -85649,7 +85649,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OTP_CTRL_TEST_ACCESS_SIZE), line:360:26, endln:360:51 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |HEX:40 |vpiTypespec: \_logic_typespec: , line:360:13, endln:360:25 @@ -85683,7 +85683,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OTP_KEYMGR_KEY_DEFAULT), line:645:30, endln:645:52 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiTypespec: \_struct_typespec: (otp_ctrl_pkg::otp_keymgr_key_t), line:639:11, endln:639:17 |vpiParent: @@ -85786,7 +85786,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OTP_LC_DATA_DEFAULT), line:587:27, endln:587:46 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiTypespec: \_struct_typespec: (otp_ctrl_pkg::otp_lc_data_t), line:573:11, endln:573:17 |vpiParent: @@ -85953,7 +85953,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OtbnKeyWidth), line:631:17, endln:631:29 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:128 |vpiTypespec: \_int_typespec: , line:631:13, endln:631:16 @@ -85969,7 +85969,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OtbnNonceWidth), line:632:17, endln:632:31 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:256 |vpiTypespec: \_int_typespec: , line:632:13, endln:632:16 @@ -85985,7 +85985,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OtpAddrShift), line:488:17, endln:488:29 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |INT:1 |vpiTypespec: \_int_typespec: , line:488:13, endln:488:16 @@ -86001,7 +86001,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OtpAddrWidth), line:481:17, endln:481:29 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |INT:10 |vpiTypespec: \_int_typespec: , line:481:13, endln:481:16 @@ -86017,7 +86017,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OtpByteAddrWidth), line:28:17, endln:28:33 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:11 |vpiTypespec: \_int_typespec: , line:28:13, endln:28:16 @@ -86033,7 +86033,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OtpDepth), line:482:17, endln:482:25 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |INT:1024 |vpiTypespec: \_int_typespec: , line:482:13, endln:482:16 @@ -86049,7 +86049,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OtpErrWidth), line:484:17, endln:484:28 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:3 |vpiTypespec: \_int_typespec: , line:484:13, endln:484:16 @@ -86065,7 +86065,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OtpIfWidth), line:486:17, endln:486:27 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |INT:64 |vpiTypespec: \_int_typespec: , line:486:13, endln:486:16 @@ -86081,7 +86081,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OtpPwrSeqWidth), line:485:17, endln:485:31 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:2 |vpiTypespec: \_int_typespec: , line:485:13, endln:485:16 @@ -86097,7 +86097,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OtpSizeWidth), line:483:17, endln:483:29 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:2 |vpiTypespec: \_int_typespec: , line:483:13, endln:483:16 @@ -86113,7 +86113,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OtpWidth), line:480:17, endln:480:25 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:16 |vpiTypespec: \_int_typespec: , line:480:13, endln:480:16 @@ -86129,7 +86129,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OwnerSwCfgContentOffset), line:43:17, endln:43:40 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:768 |vpiTypespec: \_int_typespec: , line:43:13, endln:43:16 @@ -86145,7 +86145,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OwnerSwCfgContentSize), line:44:17, endln:44:38 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:760 |vpiTypespec: \_int_typespec: , line:44:13, endln:44:16 @@ -86161,7 +86161,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OwnerSwCfgDigestOffset), line:45:17, endln:45:39 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:1528 |vpiTypespec: \_int_typespec: , line:45:13, endln:45:16 @@ -86177,7 +86177,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OwnerSwCfgDigestSize), line:46:17, endln:46:37 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:8 |vpiTypespec: \_int_typespec: , line:46:13, endln:46:16 @@ -86193,7 +86193,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OwnerSwCfgOffset), line:41:17, endln:41:33 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:768 |vpiTypespec: \_int_typespec: , line:41:13, endln:41:16 @@ -86209,7 +86209,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OwnerSwCfgSize), line:42:17, endln:42:31 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:768 |vpiTypespec: \_int_typespec: , line:42:13, endln:42:16 @@ -86225,7 +86225,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.RmaTokenOffset), line:75:17, endln:75:31 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:1872 |vpiTypespec: \_int_typespec: , line:75:13, endln:75:16 @@ -86241,7 +86241,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.RmaTokenSize), line:76:17, endln:76:29 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:16 |vpiTypespec: \_int_typespec: , line:76:13, endln:76:16 @@ -86257,7 +86257,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.RndCnstDigestConstDefault), line:746:34, endln:746:59 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiTypespec: \_logic_typespec: (digest_const_array_t), line:745:11, endln:745:56 |vpiParent: @@ -86358,7 +86358,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.RndCnstDigestIVDefault), line:755:31, endln:755:53 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiTypespec: \_logic_typespec: (digest_iv_array_t), line:754:11, endln:754:58 |vpiParent: @@ -86459,7 +86459,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.RndCnstKeyDefault), line:737:25, endln:737:42 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiTypespec: \_logic_typespec: (key_array_t), line:736:11, endln:736:56 |vpiParent: @@ -86560,7 +86560,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.RndCnstLfsrPermDefault), line:732:26, endln:732:48 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |HEX:4235171482c225f79289b32181a0163a760355d3447063d16661e44c12a5 |vpiTypespec: \_logic_typespec: (lfsr_perm_t), line:730:11, endln:730:55 @@ -86663,7 +86663,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.RndCnstLfsrSeedDefault), line:731:26, endln:731:48 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |HEX:453d28ea98 |vpiTypespec: \_logic_typespec: (lfsr_seed_t), line:729:11, endln:729:32 @@ -86726,7 +86726,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.RndCnstRawUnlockTokenDefault), line:763:37, endln:763:65 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |HEX:cbbd013ff15eba2f3065461eeb88463e |vpiTypespec: \_unsupported_typespec: (lc_ctrl_pkg::lc_token_t), line:763:13, endln:763:26 @@ -86741,7 +86741,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.ScrmblBlockHalfWords), line:509:17, endln:509:37 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |INT:4 |vpiTypespec: \_int_typespec: , line:509:13, endln:509:16 @@ -86757,7 +86757,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.ScrmblBlockWidth), line:506:17, endln:506:33 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:64 |vpiTypespec: \_int_typespec: , line:506:13, endln:506:16 @@ -86773,7 +86773,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.ScrmblKeyWidth), line:505:17, endln:505:31 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:128 |vpiTypespec: \_int_typespec: , line:505:13, endln:505:16 @@ -86789,7 +86789,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.Secret0DigestOffset), line:61:17, endln:61:36 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:1776 |vpiTypespec: \_int_typespec: , line:61:13, endln:61:16 @@ -86805,7 +86805,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.Secret0DigestSize), line:62:17, endln:62:34 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:8 |vpiTypespec: \_int_typespec: , line:62:13, endln:62:16 @@ -86821,7 +86821,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.Secret0Offset), line:55:17, endln:55:30 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:1744 |vpiTypespec: \_int_typespec: , line:55:13, endln:55:16 @@ -86837,7 +86837,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.Secret0Size), line:56:17, endln:56:28 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:40 |vpiTypespec: \_int_typespec: , line:56:13, endln:56:16 @@ -86853,7 +86853,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.Secret1DigestOffset), line:71:17, endln:71:36 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:1864 |vpiTypespec: \_int_typespec: , line:71:13, endln:71:16 @@ -86869,7 +86869,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.Secret1DigestSize), line:72:17, endln:72:34 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:8 |vpiTypespec: \_int_typespec: , line:72:13, endln:72:16 @@ -86885,7 +86885,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.Secret1Offset), line:63:17, endln:63:30 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:1784 |vpiTypespec: \_int_typespec: , line:63:13, endln:63:16 @@ -86901,7 +86901,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.Secret1Size), line:64:17, endln:64:28 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:88 |vpiTypespec: \_int_typespec: , line:64:13, endln:64:16 @@ -86917,7 +86917,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.Secret2DigestOffset), line:81:17, endln:81:36 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:1984 |vpiTypespec: \_int_typespec: , line:81:13, endln:81:16 @@ -86933,7 +86933,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.Secret2DigestSize), line:82:17, endln:82:34 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:8 |vpiTypespec: \_int_typespec: , line:82:13, endln:82:16 @@ -86949,7 +86949,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.Secret2Offset), line:73:17, endln:73:30 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:1872 |vpiTypespec: \_int_typespec: , line:73:13, endln:73:16 @@ -86965,7 +86965,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.Secret2Size), line:74:17, endln:74:28 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:120 |vpiTypespec: \_int_typespec: , line:74:13, endln:74:16 @@ -86981,7 +86981,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.SramDataKeySeedOffset), line:69:17, endln:69:38 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:1848 |vpiTypespec: \_int_typespec: , line:69:13, endln:69:16 @@ -86997,7 +86997,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.SramDataKeySeedSize), line:70:17, endln:70:36 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:16 |vpiTypespec: \_int_typespec: , line:70:13, endln:70:16 @@ -87013,7 +87013,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.SramKeySeedWidth), line:626:17, endln:626:33 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:128 |vpiTypespec: \_int_typespec: , line:626:13, endln:626:16 @@ -87029,7 +87029,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.SramKeyWidth), line:629:17, endln:629:29 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:128 |vpiTypespec: \_int_typespec: , line:629:13, endln:629:16 @@ -87045,7 +87045,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.SramNonceWidth), line:630:17, endln:630:31 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:64 |vpiTypespec: \_int_typespec: , line:630:13, endln:630:16 @@ -87061,7 +87061,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.SwWindowAddrWidth), line:452:17, endln:452:34 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |INT:9 |vpiTypespec: \_int_typespec: , line:452:13, endln:452:16 @@ -87077,7 +87077,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.TestExitTokenOffset), line:59:17, endln:59:36 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:1760 |vpiTypespec: \_int_typespec: , line:59:13, endln:59:16 @@ -87093,7 +87093,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.TestExitTokenSize), line:60:17, endln:60:34 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:16 |vpiTypespec: \_int_typespec: , line:60:13, endln:60:16 @@ -87109,7 +87109,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.TestUnlockTokenOffset), line:57:17, endln:57:38 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:1744 |vpiTypespec: \_int_typespec: , line:57:13, endln:57:16 @@ -87125,7 +87125,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.TestUnlockTokenSize), line:58:17, endln:58:36 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:16 |vpiTypespec: \_int_typespec: , line:58:13, endln:58:16 @@ -87141,7 +87141,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.CreatorRootKeyShare0Offset), line:77:17, endln:77:43 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:1888 |vpiTypespec: \_int_typespec: , line:77:13, endln:77:16 @@ -87157,7 +87157,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.CreatorRootKeyShare0Size), line:78:17, endln:78:41 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:32 |vpiTypespec: \_int_typespec: , line:78:13, endln:78:16 @@ -87173,7 +87173,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.CreatorRootKeyShare1Offset), line:79:17, endln:79:43 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:1920 |vpiTypespec: \_int_typespec: , line:79:13, endln:79:16 @@ -87189,7 +87189,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.CreatorRootKeyShare1Size), line:80:17, endln:80:41 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:32 |vpiTypespec: \_int_typespec: , line:80:13, endln:80:16 @@ -87205,7 +87205,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.CreatorSwCfgContentOffset), line:37:17, endln:37:42 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:0 |vpiTypespec: \_int_typespec: , line:37:13, endln:37:16 @@ -87221,7 +87221,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.CreatorSwCfgContentSize), line:38:17, endln:38:40 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:760 |vpiTypespec: \_int_typespec: , line:38:13, endln:38:16 @@ -87237,7 +87237,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.CreatorSwCfgDigestOffset), line:39:17, endln:39:41 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:760 |vpiTypespec: \_int_typespec: , line:39:13, endln:39:16 @@ -87253,7 +87253,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.CreatorSwCfgDigestSize), line:40:17, endln:40:39 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:8 |vpiTypespec: \_int_typespec: , line:40:13, endln:40:16 @@ -87269,7 +87269,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.CreatorSwCfgOffset), line:35:17, endln:35:35 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:0 |vpiTypespec: \_int_typespec: , line:35:13, endln:35:16 @@ -87285,7 +87285,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.CreatorSwCfgSize), line:36:17, endln:36:33 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:768 |vpiTypespec: \_int_typespec: , line:36:13, endln:36:16 @@ -87301,7 +87301,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.DeviceIdOffset), line:49:17, endln:49:31 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:1536 |vpiTypespec: \_int_typespec: , line:49:13, endln:49:16 @@ -87317,7 +87317,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.DeviceIdSize), line:50:17, endln:50:29 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:32 |vpiTypespec: \_int_typespec: , line:50:13, endln:50:16 @@ -87333,7 +87333,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.FlashAddrKeySeedOffset), line:65:17, endln:65:39 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:1784 |vpiTypespec: \_int_typespec: , line:65:13, endln:65:16 @@ -87349,7 +87349,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.FlashAddrKeySeedSize), line:66:17, endln:66:37 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:32 |vpiTypespec: \_int_typespec: , line:66:13, endln:66:16 @@ -87365,7 +87365,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.FlashDataKeySeedOffset), line:67:17, endln:67:39 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:1816 |vpiTypespec: \_int_typespec: , line:67:13, endln:67:16 @@ -87381,7 +87381,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.FlashDataKeySeedSize), line:68:17, endln:68:37 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:32 |vpiTypespec: \_int_typespec: , line:68:13, endln:68:16 @@ -87397,7 +87397,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.HwCfgContentOffset), line:51:17, endln:51:35 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:1568 |vpiTypespec: \_int_typespec: , line:51:13, endln:51:16 @@ -87413,7 +87413,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.HwCfgContentSize), line:52:17, endln:52:33 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:168 |vpiTypespec: \_int_typespec: , line:52:13, endln:52:16 @@ -87429,7 +87429,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.HwCfgDigestOffset), line:53:17, endln:53:34 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:1736 |vpiTypespec: \_int_typespec: , line:53:13, endln:53:16 @@ -87445,7 +87445,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.HwCfgDigestSize), line:54:17, endln:54:32 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:8 |vpiTypespec: \_int_typespec: , line:54:13, endln:54:16 @@ -87461,7 +87461,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.HwCfgOffset), line:47:17, endln:47:28 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:1536 |vpiTypespec: \_int_typespec: , line:47:13, endln:47:16 @@ -87477,7 +87477,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.HwCfgSize), line:48:17, endln:48:26 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:208 |vpiTypespec: \_int_typespec: , line:48:13, endln:48:16 @@ -87493,7 +87493,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.LcStateOffset), line:85:17, endln:85:30 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:1992 |vpiTypespec: \_int_typespec: , line:85:13, endln:85:16 @@ -87509,7 +87509,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.LcStateSize), line:86:17, endln:86:28 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:24 |vpiTypespec: \_int_typespec: , line:86:13, endln:86:16 @@ -87525,7 +87525,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.LcTransitionCntOffset), line:87:17, endln:87:38 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:2016 |vpiTypespec: \_int_typespec: , line:87:13, endln:87:16 @@ -87541,7 +87541,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.LcTransitionCntSize), line:88:17, endln:88:36 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:32 |vpiTypespec: \_int_typespec: , line:88:13, endln:88:16 @@ -87557,7 +87557,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.LifeCycleOffset), line:83:17, endln:83:32 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:1992 |vpiTypespec: \_int_typespec: , line:83:13, endln:83:16 @@ -87573,7 +87573,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.LifeCycleSize), line:84:17, endln:84:30 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:56 |vpiTypespec: \_int_typespec: , line:84:13, endln:84:16 @@ -87589,7 +87589,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.NumAlerts), line:89:17, endln:89:26 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:2 |vpiTypespec: \_int_typespec: , line:89:13, endln:89:16 @@ -87605,7 +87605,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.NumDaiWords), line:30:17, endln:30:28 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:2 |vpiTypespec: \_int_typespec: , line:30:13, endln:30:16 @@ -87621,7 +87621,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.NumDebugWindowWords), line:33:17, endln:33:36 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:16 |vpiTypespec: \_int_typespec: , line:33:13, endln:33:16 @@ -87637,7 +87637,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.NumDigestWords), line:31:17, endln:31:31 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:2 |vpiTypespec: \_int_typespec: , line:31:13, endln:31:16 @@ -87653,7 +87653,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.NumErrorEntries), line:29:17, endln:29:32 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:9 |vpiTypespec: \_int_typespec: , line:29:13, endln:29:16 @@ -87669,7 +87669,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.NumPart), line:34:17, endln:34:24 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:7 |vpiTypespec: \_int_typespec: , line:34:13, endln:34:16 @@ -87685,7 +87685,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.NumSramKeyReqSlots), line:27:17, endln:27:35 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:2 |vpiTypespec: \_int_typespec: , line:27:13, endln:27:16 @@ -87701,7 +87701,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.NumSwCfgWindowWords), line:32:17, endln:32:36 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:512 |vpiTypespec: \_int_typespec: , line:32:13, endln:32:16 @@ -87717,7 +87717,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OTP_CTRL_ALERT_TEST_OFFSET), line:325:26, endln:325:52 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |HEX:c |vpiTypespec: \_logic_typespec: , line:325:13, endln:325:25 @@ -87751,7 +87751,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OTP_CTRL_CHECK_REGWEN_OFFSET), line:337:26, endln:337:54 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |HEX:3c |vpiTypespec: \_logic_typespec: , line:337:13, endln:337:25 @@ -87785,7 +87785,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OTP_CTRL_CHECK_TIMEOUT_OFFSET), line:338:26, endln:338:55 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |HEX:40 |vpiTypespec: \_logic_typespec: , line:338:13, endln:338:25 @@ -87819,7 +87819,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OTP_CTRL_CHECK_TRIGGER_OFFSET), line:336:26, endln:336:55 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |HEX:38 |vpiTypespec: \_logic_typespec: , line:336:13, endln:336:25 @@ -87853,7 +87853,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OTP_CTRL_CHECK_TRIGGER_REGWEN_OFFSET), line:335:26, endln:335:62 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |HEX:34 |vpiTypespec: \_logic_typespec: , line:335:13, endln:335:25 @@ -87887,7 +87887,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OTP_CTRL_CONSISTENCY_CHECK_PERIOD_OFFSET), line:340:26, endln:340:66 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |HEX:48 |vpiTypespec: \_logic_typespec: , line:340:13, endln:340:25 @@ -87921,7 +87921,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_OFFSET), line:343:26, endln:343:65 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |HEX:54 |vpiTypespec: \_logic_typespec: , line:343:13, endln:343:25 @@ -87955,7 +87955,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_OFFSET), line:344:26, endln:344:65 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |HEX:58 |vpiTypespec: \_logic_typespec: , line:344:13, endln:344:25 @@ -87989,7 +87989,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OTP_CTRL_CREATOR_SW_CFG_READ_LOCK_OFFSET), line:341:26, endln:341:66 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |HEX:4c |vpiTypespec: \_logic_typespec: , line:341:13, endln:341:25 @@ -88023,7 +88023,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OTP_CTRL_DIRECT_ACCESS_ADDRESS_OFFSET), line:330:26, endln:330:63 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |HEX:20 |vpiTypespec: \_logic_typespec: , line:330:13, endln:330:25 @@ -88057,7 +88057,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OTP_CTRL_DIRECT_ACCESS_CMD_OFFSET), line:329:26, endln:329:59 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |HEX:1c |vpiTypespec: \_logic_typespec: , line:329:13, endln:329:25 @@ -88091,7 +88091,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OTP_CTRL_DIRECT_ACCESS_RDATA_0_OFFSET), line:333:26, endln:333:63 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |HEX:2c |vpiTypespec: \_logic_typespec: , line:333:13, endln:333:25 @@ -88125,7 +88125,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OTP_CTRL_DIRECT_ACCESS_RDATA_1_OFFSET), line:334:26, endln:334:63 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |HEX:30 |vpiTypespec: \_logic_typespec: , line:334:13, endln:334:25 @@ -88159,7 +88159,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OTP_CTRL_DIRECT_ACCESS_REGWEN_OFFSET), line:328:26, endln:328:62 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |HEX:18 |vpiTypespec: \_logic_typespec: , line:328:13, endln:328:25 @@ -88193,7 +88193,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OTP_CTRL_DIRECT_ACCESS_WDATA_0_OFFSET), line:331:26, endln:331:63 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |HEX:24 |vpiTypespec: \_logic_typespec: , line:331:13, endln:331:25 @@ -88227,7 +88227,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OTP_CTRL_DIRECT_ACCESS_WDATA_1_OFFSET), line:332:26, endln:332:63 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |HEX:28 |vpiTypespec: \_logic_typespec: , line:332:13, endln:332:25 @@ -88261,7 +88261,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OTP_CTRL_ERR_CODE_OFFSET), line:327:26, endln:327:50 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |HEX:14 |vpiTypespec: \_logic_typespec: , line:327:13, endln:327:25 @@ -88295,7 +88295,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OTP_CTRL_HW_CFG_DIGEST_0_OFFSET), line:347:26, endln:347:57 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |HEX:64 |vpiTypespec: \_logic_typespec: , line:347:13, endln:347:25 @@ -88329,7 +88329,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OTP_CTRL_HW_CFG_DIGEST_1_OFFSET), line:348:26, endln:348:57 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |HEX:68 |vpiTypespec: \_logic_typespec: , line:348:13, endln:348:25 @@ -88363,7 +88363,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OTP_CTRL_INTEGRITY_CHECK_PERIOD_OFFSET), line:339:26, endln:339:64 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |HEX:44 |vpiTypespec: \_logic_typespec: , line:339:13, endln:339:25 @@ -88397,7 +88397,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OTP_CTRL_INTR_ENABLE_OFFSET), line:323:26, endln:323:53 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |HEX:4 |vpiTypespec: \_logic_typespec: , line:323:13, endln:323:25 @@ -88431,7 +88431,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OTP_CTRL_INTR_STATE_OFFSET), line:322:26, endln:322:52 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |HEX:0 |vpiTypespec: \_logic_typespec: , line:322:13, endln:322:25 @@ -88465,7 +88465,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OTP_CTRL_INTR_TEST_OFFSET), line:324:26, endln:324:51 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |HEX:8 |vpiTypespec: \_logic_typespec: , line:324:13, endln:324:25 @@ -88499,7 +88499,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OTP_CTRL_OWNER_SW_CFG_DIGEST_0_OFFSET), line:345:26, endln:345:63 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |HEX:5c |vpiTypespec: \_logic_typespec: , line:345:13, endln:345:25 @@ -88533,7 +88533,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OTP_CTRL_OWNER_SW_CFG_DIGEST_1_OFFSET), line:346:26, endln:346:63 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |HEX:60 |vpiTypespec: \_logic_typespec: , line:346:13, endln:346:25 @@ -88567,7 +88567,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OTP_CTRL_OWNER_SW_CFG_READ_LOCK_OFFSET), line:342:26, endln:342:64 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |HEX:50 |vpiTypespec: \_logic_typespec: , line:342:13, endln:342:25 @@ -88601,7 +88601,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OTP_CTRL_PERMIT), line:400:25, endln:400:40 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiSize:33 |vpiTypespec: \_array_typespec: @@ -88703,7 +88703,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OTP_CTRL_SECRET0_DIGEST_0_OFFSET), line:349:26, endln:349:58 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |HEX:6c |vpiTypespec: \_logic_typespec: , line:349:13, endln:349:25 @@ -88737,7 +88737,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OTP_CTRL_SECRET0_DIGEST_1_OFFSET), line:350:26, endln:350:58 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |HEX:70 |vpiTypespec: \_logic_typespec: , line:350:13, endln:350:25 @@ -88771,7 +88771,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OTP_CTRL_SECRET1_DIGEST_0_OFFSET), line:351:26, endln:351:58 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |HEX:74 |vpiTypespec: \_logic_typespec: , line:351:13, endln:351:25 @@ -88805,7 +88805,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OTP_CTRL_SECRET1_DIGEST_1_OFFSET), line:352:26, endln:352:58 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |HEX:78 |vpiTypespec: \_logic_typespec: , line:352:13, endln:352:25 @@ -88839,7 +88839,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OTP_CTRL_SECRET2_DIGEST_0_OFFSET), line:353:26, endln:353:58 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |HEX:7c |vpiTypespec: \_logic_typespec: , line:353:13, endln:353:25 @@ -88873,7 +88873,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OTP_CTRL_SECRET2_DIGEST_1_OFFSET), line:354:26, endln:354:58 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |HEX:80 |vpiTypespec: \_logic_typespec: , line:354:13, endln:354:25 @@ -88907,7 +88907,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OTP_CTRL_STATUS_OFFSET), line:326:26, endln:326:48 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |HEX:10 |vpiTypespec: \_logic_typespec: , line:326:13, endln:326:25 @@ -88941,7 +88941,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OTP_CTRL_SW_CFG_WINDOW_OFFSET), line:357:26, endln:357:55 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |HEX:1000 |vpiTypespec: \_logic_typespec: , line:357:13, endln:357:25 @@ -88975,7 +88975,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OTP_CTRL_SW_CFG_WINDOW_SIZE), line:358:26, endln:358:53 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |HEX:800 |vpiTypespec: \_logic_typespec: , line:358:13, endln:358:25 @@ -89009,7 +89009,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OTP_CTRL_TEST_ACCESS_OFFSET), line:359:26, endln:359:53 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |HEX:2000 |vpiTypespec: \_logic_typespec: , line:359:13, endln:359:25 @@ -89043,7 +89043,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OTP_CTRL_TEST_ACCESS_SIZE), line:360:26, endln:360:51 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |HEX:40 |vpiTypespec: \_logic_typespec: , line:360:13, endln:360:25 @@ -89077,7 +89077,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OtpByteAddrWidth), line:28:17, endln:28:33 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:11 |vpiTypespec: \_int_typespec: , line:28:13, endln:28:16 @@ -89093,7 +89093,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OwnerSwCfgContentOffset), line:43:17, endln:43:40 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:768 |vpiTypespec: \_int_typespec: , line:43:13, endln:43:16 @@ -89109,7 +89109,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OwnerSwCfgContentSize), line:44:17, endln:44:38 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:760 |vpiTypespec: \_int_typespec: , line:44:13, endln:44:16 @@ -89125,7 +89125,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OwnerSwCfgDigestOffset), line:45:17, endln:45:39 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:1528 |vpiTypespec: \_int_typespec: , line:45:13, endln:45:16 @@ -89141,7 +89141,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OwnerSwCfgDigestSize), line:46:17, endln:46:37 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:8 |vpiTypespec: \_int_typespec: , line:46:13, endln:46:16 @@ -89157,7 +89157,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OwnerSwCfgOffset), line:41:17, endln:41:33 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:768 |vpiTypespec: \_int_typespec: , line:41:13, endln:41:16 @@ -89173,7 +89173,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OwnerSwCfgSize), line:42:17, endln:42:31 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:768 |vpiTypespec: \_int_typespec: , line:42:13, endln:42:16 @@ -89189,7 +89189,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.RmaTokenOffset), line:75:17, endln:75:31 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:1872 |vpiTypespec: \_int_typespec: , line:75:13, endln:75:16 @@ -89205,7 +89205,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.RmaTokenSize), line:76:17, endln:76:29 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:16 |vpiTypespec: \_int_typespec: , line:76:13, endln:76:16 @@ -89221,7 +89221,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.Secret0DigestOffset), line:61:17, endln:61:36 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:1776 |vpiTypespec: \_int_typespec: , line:61:13, endln:61:16 @@ -89237,7 +89237,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.Secret0DigestSize), line:62:17, endln:62:34 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:8 |vpiTypespec: \_int_typespec: , line:62:13, endln:62:16 @@ -89253,7 +89253,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.Secret0Offset), line:55:17, endln:55:30 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:1744 |vpiTypespec: \_int_typespec: , line:55:13, endln:55:16 @@ -89269,7 +89269,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.Secret0Size), line:56:17, endln:56:28 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:40 |vpiTypespec: \_int_typespec: , line:56:13, endln:56:16 @@ -89285,7 +89285,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.Secret1DigestOffset), line:71:17, endln:71:36 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:1864 |vpiTypespec: \_int_typespec: , line:71:13, endln:71:16 @@ -89301,7 +89301,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.Secret1DigestSize), line:72:17, endln:72:34 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:8 |vpiTypespec: \_int_typespec: , line:72:13, endln:72:16 @@ -89317,7 +89317,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.Secret1Offset), line:63:17, endln:63:30 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:1784 |vpiTypespec: \_int_typespec: , line:63:13, endln:63:16 @@ -89333,7 +89333,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.Secret1Size), line:64:17, endln:64:28 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:88 |vpiTypespec: \_int_typespec: , line:64:13, endln:64:16 @@ -89349,7 +89349,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.Secret2DigestOffset), line:81:17, endln:81:36 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:1984 |vpiTypespec: \_int_typespec: , line:81:13, endln:81:16 @@ -89365,7 +89365,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.Secret2DigestSize), line:82:17, endln:82:34 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:8 |vpiTypespec: \_int_typespec: , line:82:13, endln:82:16 @@ -89381,7 +89381,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.Secret2Offset), line:73:17, endln:73:30 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:1872 |vpiTypespec: \_int_typespec: , line:73:13, endln:73:16 @@ -89397,7 +89397,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.Secret2Size), line:74:17, endln:74:28 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:120 |vpiTypespec: \_int_typespec: , line:74:13, endln:74:16 @@ -89413,7 +89413,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.SramDataKeySeedOffset), line:69:17, endln:69:38 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:1848 |vpiTypespec: \_int_typespec: , line:69:13, endln:69:16 @@ -89429,7 +89429,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.SramDataKeySeedSize), line:70:17, endln:70:36 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:16 |vpiTypespec: \_int_typespec: , line:70:13, endln:70:16 @@ -89445,7 +89445,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.TestExitTokenOffset), line:59:17, endln:59:36 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:1760 |vpiTypespec: \_int_typespec: , line:59:13, endln:59:16 @@ -89461,7 +89461,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.TestExitTokenSize), line:60:17, endln:60:34 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:16 |vpiTypespec: \_int_typespec: , line:60:13, endln:60:16 @@ -89477,7 +89477,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.TestUnlockTokenOffset), line:57:17, endln:57:38 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:1744 |vpiTypespec: \_int_typespec: , line:57:13, endln:57:16 @@ -89493,7 +89493,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.TestUnlockTokenSize), line:58:17, endln:58:36 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:16 |vpiTypespec: \_int_typespec: , line:58:13, endln:58:16 @@ -89509,7 +89509,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.ConstSelWidth), line:522:17, endln:522:30 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |INT:3 |vpiTypespec: \_int_typespec: , line:522:13, endln:522:16 @@ -89525,7 +89525,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.CreatorRootKeyShare0Offset), line:77:17, endln:77:43 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:1888 |vpiTypespec: \_int_typespec: , line:77:13, endln:77:16 @@ -89541,7 +89541,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.CreatorRootKeyShare0Size), line:78:17, endln:78:41 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:32 |vpiTypespec: \_int_typespec: , line:78:13, endln:78:16 @@ -89557,7 +89557,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.CreatorRootKeyShare1Offset), line:79:17, endln:79:43 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:1920 |vpiTypespec: \_int_typespec: , line:79:13, endln:79:16 @@ -89573,7 +89573,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.CreatorRootKeyShare1Size), line:80:17, endln:80:41 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:32 |vpiTypespec: \_int_typespec: , line:80:13, endln:80:16 @@ -89589,7 +89589,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.CreatorSwCfgContentOffset), line:37:17, endln:37:42 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:0 |vpiTypespec: \_int_typespec: , line:37:13, endln:37:16 @@ -89605,7 +89605,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.CreatorSwCfgContentSize), line:38:17, endln:38:40 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:760 |vpiTypespec: \_int_typespec: , line:38:13, endln:38:16 @@ -89621,7 +89621,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.CreatorSwCfgDigestOffset), line:39:17, endln:39:41 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:760 |vpiTypespec: \_int_typespec: , line:39:13, endln:39:16 @@ -89637,7 +89637,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.CreatorSwCfgDigestSize), line:40:17, endln:40:39 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:8 |vpiTypespec: \_int_typespec: , line:40:13, endln:40:16 @@ -89653,7 +89653,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.CreatorSwCfgOffset), line:35:17, endln:35:35 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:0 |vpiTypespec: \_int_typespec: , line:35:13, endln:35:16 @@ -89669,7 +89669,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.CreatorSwCfgSize), line:36:17, endln:36:33 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:768 |vpiTypespec: \_int_typespec: , line:36:13, endln:36:16 @@ -89685,7 +89685,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.DaiCmdWidth), line:468:17, endln:468:28 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:3 |vpiTypespec: \_int_typespec: , line:468:13, endln:468:16 @@ -89701,7 +89701,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.DeviceIdOffset), line:49:17, endln:49:31 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:1536 |vpiTypespec: \_int_typespec: , line:49:13, endln:49:16 @@ -89717,7 +89717,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.DeviceIdSize), line:50:17, endln:50:29 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:32 |vpiTypespec: \_int_typespec: , line:50:13, endln:50:16 @@ -89733,7 +89733,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.EdnDataWidth), line:448:17, endln:448:29 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:64 |vpiTypespec: \_int_typespec: , line:448:13, endln:448:16 @@ -89749,7 +89749,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.FLASH_OTP_KEY_RSP_DEFAULT), line:672:33, endln:672:58 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiTypespec: \_struct_typespec: (otp_ctrl_pkg::flash_otp_key_rsp_t), line:664:11, endln:664:17 |vpiParent: @@ -89848,7 +89848,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.FlashAddrKeySeedOffset), line:65:17, endln:65:39 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:1784 |vpiTypespec: \_int_typespec: , line:65:13, endln:65:16 @@ -89864,7 +89864,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.FlashAddrKeySeedSize), line:66:17, endln:66:37 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:32 |vpiTypespec: \_int_typespec: , line:66:13, endln:66:16 @@ -89880,7 +89880,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.FlashDataKeySeedOffset), line:67:17, endln:67:39 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:1816 |vpiTypespec: \_int_typespec: , line:67:13, endln:67:16 @@ -89896,7 +89896,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.FlashDataKeySeedSize), line:68:17, endln:68:37 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:32 |vpiTypespec: \_int_typespec: , line:68:13, endln:68:16 @@ -89912,7 +89912,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.FlashKeySeedWidth), line:625:17, endln:625:34 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:256 |vpiTypespec: \_int_typespec: , line:625:13, endln:625:16 @@ -89928,7 +89928,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.FlashKeyWidth), line:628:17, endln:628:30 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:128 |vpiTypespec: \_int_typespec: , line:628:13, endln:628:16 @@ -89944,7 +89944,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.HwCfgContentOffset), line:51:17, endln:51:35 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:1568 |vpiTypespec: \_int_typespec: , line:51:13, endln:51:16 @@ -89960,7 +89960,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.HwCfgContentSize), line:52:17, endln:52:33 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:168 |vpiTypespec: \_int_typespec: , line:52:13, endln:52:16 @@ -89976,7 +89976,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.HwCfgDigestOffset), line:53:17, endln:53:34 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:1736 |vpiTypespec: \_int_typespec: , line:53:13, endln:53:16 @@ -89992,7 +89992,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.HwCfgDigestSize), line:54:17, endln:54:32 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:8 |vpiTypespec: \_int_typespec: , line:54:13, endln:54:16 @@ -90008,7 +90008,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.HwCfgOffset), line:47:17, endln:47:28 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:1536 |vpiTypespec: \_int_typespec: , line:47:13, endln:47:16 @@ -90024,7 +90024,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.HwCfgSize), line:48:17, endln:48:26 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:208 |vpiTypespec: \_int_typespec: , line:48:13, endln:48:16 @@ -90040,7 +90040,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.KeyMgrKeyWidth), line:627:17, endln:627:31 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:256 |vpiTypespec: \_int_typespec: , line:627:13, endln:627:16 @@ -90056,7 +90056,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.LcStateOffset), line:85:17, endln:85:30 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:1992 |vpiTypespec: \_int_typespec: , line:85:13, endln:85:16 @@ -90072,7 +90072,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.LcStateSize), line:86:17, endln:86:28 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:24 |vpiTypespec: \_int_typespec: , line:86:13, endln:86:16 @@ -90088,7 +90088,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.LcTransitionCntOffset), line:87:17, endln:87:38 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:2016 |vpiTypespec: \_int_typespec: , line:87:13, endln:87:16 @@ -90104,7 +90104,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.LcTransitionCntSize), line:88:17, endln:88:36 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:32 |vpiTypespec: \_int_typespec: , line:88:13, endln:88:16 @@ -90120,7 +90120,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.LfsrWidth), line:728:18, endln:728:27 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:40 |vpiTypespec: \_int_typespec: , line:728:14, endln:728:17 @@ -90137,7 +90137,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.LifeCycleOffset), line:83:17, endln:83:32 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:1992 |vpiTypespec: \_int_typespec: , line:83:13, endln:83:16 @@ -90153,7 +90153,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.LifeCycleSize), line:84:17, endln:84:30 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:56 |vpiTypespec: \_int_typespec: , line:84:13, endln:84:16 @@ -90169,7 +90169,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.NumAlerts), line:89:17, endln:89:26 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:2 |vpiTypespec: \_int_typespec: , line:89:13, endln:89:16 @@ -90185,7 +90185,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.NumDaiWords), line:30:17, endln:30:28 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:2 |vpiTypespec: \_int_typespec: , line:30:13, endln:30:16 @@ -90201,7 +90201,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.NumDebugWindowWords), line:33:17, endln:33:36 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:16 |vpiTypespec: \_int_typespec: , line:33:13, endln:33:16 @@ -90217,7 +90217,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.NumDigestSets), line:521:17, endln:521:30 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:5 |vpiTypespec: \_int_typespec: , line:521:13, endln:521:16 @@ -90233,7 +90233,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.NumDigestWords), line:31:17, endln:31:31 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:2 |vpiTypespec: \_int_typespec: , line:31:13, endln:31:16 @@ -90249,7 +90249,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.NumErrorEntries), line:29:17, endln:29:32 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:9 |vpiTypespec: \_int_typespec: , line:29:13, endln:29:16 @@ -90265,7 +90265,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.NumPart), line:34:17, endln:34:24 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:7 |vpiTypespec: \_int_typespec: , line:34:13, endln:34:16 @@ -90281,7 +90281,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.NumPartWidth), line:450:17, endln:450:29 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |INT:3 |vpiTypespec: \_int_typespec: , line:450:13, endln:450:16 @@ -90297,7 +90297,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.NumPresentRounds), line:508:17, endln:508:33 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:31 |vpiTypespec: \_int_typespec: , line:508:13, endln:508:16 @@ -90313,7 +90313,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.NumScrmblKeys), line:520:17, endln:520:30 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:3 |vpiTypespec: \_int_typespec: , line:520:13, endln:520:16 @@ -90329,7 +90329,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.NumSramKeyReqSlots), line:27:17, endln:27:35 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:2 |vpiTypespec: \_int_typespec: , line:27:13, endln:27:16 @@ -90345,7 +90345,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.NumSwCfgWindowWords), line:32:17, endln:32:36 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:512 |vpiTypespec: \_int_typespec: , line:32:13, endln:32:16 @@ -90361,7 +90361,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OTP_CTRL_ALERT_TEST_OFFSET), line:325:26, endln:325:52 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |HEX:c |vpiTypespec: \_logic_typespec: , line:325:13, endln:325:25 @@ -90395,7 +90395,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OTP_CTRL_CHECK_REGWEN_OFFSET), line:337:26, endln:337:54 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |HEX:3c |vpiTypespec: \_logic_typespec: , line:337:13, endln:337:25 @@ -90429,7 +90429,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OTP_CTRL_CHECK_TIMEOUT_OFFSET), line:338:26, endln:338:55 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |HEX:40 |vpiTypespec: \_logic_typespec: , line:338:13, endln:338:25 @@ -90463,7 +90463,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OTP_CTRL_CHECK_TRIGGER_OFFSET), line:336:26, endln:336:55 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |HEX:38 |vpiTypespec: \_logic_typespec: , line:336:13, endln:336:25 @@ -90497,7 +90497,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OTP_CTRL_CHECK_TRIGGER_REGWEN_OFFSET), line:335:26, endln:335:62 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |HEX:34 |vpiTypespec: \_logic_typespec: , line:335:13, endln:335:25 @@ -90531,7 +90531,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OTP_CTRL_CONSISTENCY_CHECK_PERIOD_OFFSET), line:340:26, endln:340:66 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |HEX:48 |vpiTypespec: \_logic_typespec: , line:340:13, endln:340:25 @@ -90565,7 +90565,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_OFFSET), line:343:26, endln:343:65 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |HEX:54 |vpiTypespec: \_logic_typespec: , line:343:13, endln:343:25 @@ -90599,7 +90599,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_OFFSET), line:344:26, endln:344:65 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |HEX:58 |vpiTypespec: \_logic_typespec: , line:344:13, endln:344:25 @@ -90633,7 +90633,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OTP_CTRL_CREATOR_SW_CFG_READ_LOCK_OFFSET), line:341:26, endln:341:66 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |HEX:4c |vpiTypespec: \_logic_typespec: , line:341:13, endln:341:25 @@ -90667,7 +90667,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OTP_CTRL_DIRECT_ACCESS_ADDRESS_OFFSET), line:330:26, endln:330:63 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |HEX:20 |vpiTypespec: \_logic_typespec: , line:330:13, endln:330:25 @@ -90701,7 +90701,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OTP_CTRL_DIRECT_ACCESS_CMD_OFFSET), line:329:26, endln:329:59 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |HEX:1c |vpiTypespec: \_logic_typespec: , line:329:13, endln:329:25 @@ -90735,7 +90735,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OTP_CTRL_DIRECT_ACCESS_RDATA_0_OFFSET), line:333:26, endln:333:63 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |HEX:2c |vpiTypespec: \_logic_typespec: , line:333:13, endln:333:25 @@ -90769,7 +90769,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OTP_CTRL_DIRECT_ACCESS_RDATA_1_OFFSET), line:334:26, endln:334:63 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |HEX:30 |vpiTypespec: \_logic_typespec: , line:334:13, endln:334:25 @@ -90803,7 +90803,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OTP_CTRL_DIRECT_ACCESS_REGWEN_OFFSET), line:328:26, endln:328:62 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |HEX:18 |vpiTypespec: \_logic_typespec: , line:328:13, endln:328:25 @@ -90837,7 +90837,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OTP_CTRL_DIRECT_ACCESS_WDATA_0_OFFSET), line:331:26, endln:331:63 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |HEX:24 |vpiTypespec: \_logic_typespec: , line:331:13, endln:331:25 @@ -90871,7 +90871,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OTP_CTRL_DIRECT_ACCESS_WDATA_1_OFFSET), line:332:26, endln:332:63 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |HEX:28 |vpiTypespec: \_logic_typespec: , line:332:13, endln:332:25 @@ -90905,7 +90905,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OTP_CTRL_ERR_CODE_OFFSET), line:327:26, endln:327:50 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |HEX:14 |vpiTypespec: \_logic_typespec: , line:327:13, endln:327:25 @@ -90939,7 +90939,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OTP_CTRL_HW_CFG_DIGEST_0_OFFSET), line:347:26, endln:347:57 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |HEX:64 |vpiTypespec: \_logic_typespec: , line:347:13, endln:347:25 @@ -90973,7 +90973,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OTP_CTRL_HW_CFG_DIGEST_1_OFFSET), line:348:26, endln:348:57 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |HEX:68 |vpiTypespec: \_logic_typespec: , line:348:13, endln:348:25 @@ -91007,7 +91007,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OTP_CTRL_INTEGRITY_CHECK_PERIOD_OFFSET), line:339:26, endln:339:64 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |HEX:44 |vpiTypespec: \_logic_typespec: , line:339:13, endln:339:25 @@ -91041,7 +91041,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OTP_CTRL_INTR_ENABLE_OFFSET), line:323:26, endln:323:53 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |HEX:4 |vpiTypespec: \_logic_typespec: , line:323:13, endln:323:25 @@ -91075,7 +91075,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OTP_CTRL_INTR_STATE_OFFSET), line:322:26, endln:322:52 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |HEX:0 |vpiTypespec: \_logic_typespec: , line:322:13, endln:322:25 @@ -91109,7 +91109,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OTP_CTRL_INTR_TEST_OFFSET), line:324:26, endln:324:51 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |HEX:8 |vpiTypespec: \_logic_typespec: , line:324:13, endln:324:25 @@ -91143,7 +91143,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OTP_CTRL_OWNER_SW_CFG_DIGEST_0_OFFSET), line:345:26, endln:345:63 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |HEX:5c |vpiTypespec: \_logic_typespec: , line:345:13, endln:345:25 @@ -91177,7 +91177,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OTP_CTRL_OWNER_SW_CFG_DIGEST_1_OFFSET), line:346:26, endln:346:63 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |HEX:60 |vpiTypespec: \_logic_typespec: , line:346:13, endln:346:25 @@ -91211,7 +91211,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OTP_CTRL_OWNER_SW_CFG_READ_LOCK_OFFSET), line:342:26, endln:342:64 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |HEX:50 |vpiTypespec: \_logic_typespec: , line:342:13, endln:342:25 @@ -91245,7 +91245,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OTP_CTRL_PERMIT), line:400:25, endln:400:40 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiSize:33 |vpiTypespec: \_array_typespec: @@ -91347,7 +91347,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OTP_CTRL_SECRET0_DIGEST_0_OFFSET), line:349:26, endln:349:58 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |HEX:6c |vpiTypespec: \_logic_typespec: , line:349:13, endln:349:25 @@ -91381,7 +91381,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OTP_CTRL_SECRET0_DIGEST_1_OFFSET), line:350:26, endln:350:58 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |HEX:70 |vpiTypespec: \_logic_typespec: , line:350:13, endln:350:25 @@ -91415,7 +91415,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OTP_CTRL_SECRET1_DIGEST_0_OFFSET), line:351:26, endln:351:58 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |HEX:74 |vpiTypespec: \_logic_typespec: , line:351:13, endln:351:25 @@ -91449,7 +91449,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OTP_CTRL_SECRET1_DIGEST_1_OFFSET), line:352:26, endln:352:58 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |HEX:78 |vpiTypespec: \_logic_typespec: , line:352:13, endln:352:25 @@ -91483,7 +91483,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OTP_CTRL_SECRET2_DIGEST_0_OFFSET), line:353:26, endln:353:58 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |HEX:7c |vpiTypespec: \_logic_typespec: , line:353:13, endln:353:25 @@ -91517,7 +91517,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OTP_CTRL_SECRET2_DIGEST_1_OFFSET), line:354:26, endln:354:58 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |HEX:80 |vpiTypespec: \_logic_typespec: , line:354:13, endln:354:25 @@ -91551,7 +91551,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OTP_CTRL_STATUS_OFFSET), line:326:26, endln:326:48 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |HEX:10 |vpiTypespec: \_logic_typespec: , line:326:13, endln:326:25 @@ -91585,7 +91585,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OTP_CTRL_SW_CFG_WINDOW_OFFSET), line:357:26, endln:357:55 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |HEX:1000 |vpiTypespec: \_logic_typespec: , line:357:13, endln:357:25 @@ -91619,7 +91619,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OTP_CTRL_SW_CFG_WINDOW_SIZE), line:358:26, endln:358:53 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |HEX:800 |vpiTypespec: \_logic_typespec: , line:358:13, endln:358:25 @@ -91653,7 +91653,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OTP_CTRL_TEST_ACCESS_OFFSET), line:359:26, endln:359:53 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |HEX:2000 |vpiTypespec: \_logic_typespec: , line:359:13, endln:359:25 @@ -91687,7 +91687,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OTP_CTRL_TEST_ACCESS_SIZE), line:360:26, endln:360:51 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |HEX:40 |vpiTypespec: \_logic_typespec: , line:360:13, endln:360:25 @@ -91721,7 +91721,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OTP_KEYMGR_KEY_DEFAULT), line:645:30, endln:645:52 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiTypespec: \_struct_typespec: (otp_ctrl_pkg::otp_keymgr_key_t), line:639:11, endln:639:17 |vpiParent: @@ -91824,7 +91824,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OTP_LC_DATA_DEFAULT), line:587:27, endln:587:46 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiTypespec: \_struct_typespec: (otp_ctrl_pkg::otp_lc_data_t), line:573:11, endln:573:17 |vpiParent: @@ -91991,7 +91991,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OtbnKeyWidth), line:631:17, endln:631:29 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:128 |vpiTypespec: \_int_typespec: , line:631:13, endln:631:16 @@ -92007,7 +92007,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OtbnNonceWidth), line:632:17, endln:632:31 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:256 |vpiTypespec: \_int_typespec: , line:632:13, endln:632:16 @@ -92023,7 +92023,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OtpAddrShift), line:488:17, endln:488:29 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |INT:1 |vpiTypespec: \_int_typespec: , line:488:13, endln:488:16 @@ -92039,7 +92039,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OtpAddrWidth), line:481:17, endln:481:29 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |INT:10 |vpiTypespec: \_int_typespec: , line:481:13, endln:481:16 @@ -92055,7 +92055,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OtpByteAddrWidth), line:28:17, endln:28:33 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:11 |vpiTypespec: \_int_typespec: , line:28:13, endln:28:16 @@ -92071,7 +92071,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OtpDepth), line:482:17, endln:482:25 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |INT:1024 |vpiTypespec: \_int_typespec: , line:482:13, endln:482:16 @@ -92087,7 +92087,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OtpErrWidth), line:484:17, endln:484:28 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:3 |vpiTypespec: \_int_typespec: , line:484:13, endln:484:16 @@ -92103,7 +92103,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OtpIfWidth), line:486:17, endln:486:27 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |INT:64 |vpiTypespec: \_int_typespec: , line:486:13, endln:486:16 @@ -92119,7 +92119,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OtpPwrSeqWidth), line:485:17, endln:485:31 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:2 |vpiTypespec: \_int_typespec: , line:485:13, endln:485:16 @@ -92135,7 +92135,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OtpSizeWidth), line:483:17, endln:483:29 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:2 |vpiTypespec: \_int_typespec: , line:483:13, endln:483:16 @@ -92151,7 +92151,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OtpWidth), line:480:17, endln:480:25 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:16 |vpiTypespec: \_int_typespec: , line:480:13, endln:480:16 @@ -92167,7 +92167,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OwnerSwCfgContentOffset), line:43:17, endln:43:40 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:768 |vpiTypespec: \_int_typespec: , line:43:13, endln:43:16 @@ -92183,7 +92183,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OwnerSwCfgContentSize), line:44:17, endln:44:38 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:760 |vpiTypespec: \_int_typespec: , line:44:13, endln:44:16 @@ -92199,7 +92199,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OwnerSwCfgDigestOffset), line:45:17, endln:45:39 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:1528 |vpiTypespec: \_int_typespec: , line:45:13, endln:45:16 @@ -92215,7 +92215,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OwnerSwCfgDigestSize), line:46:17, endln:46:37 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:8 |vpiTypespec: \_int_typespec: , line:46:13, endln:46:16 @@ -92231,7 +92231,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OwnerSwCfgOffset), line:41:17, endln:41:33 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:768 |vpiTypespec: \_int_typespec: , line:41:13, endln:41:16 @@ -92247,7 +92247,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OwnerSwCfgSize), line:42:17, endln:42:31 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:768 |vpiTypespec: \_int_typespec: , line:42:13, endln:42:16 @@ -92263,7 +92263,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.PartInfo), line:795:26, endln:795:34 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiSize:1 |vpiTypespec: \_array_typespec: @@ -92632,7 +92632,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.RmaTokenOffset), line:75:17, endln:75:31 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:1872 |vpiTypespec: \_int_typespec: , line:75:13, endln:75:16 @@ -92648,7 +92648,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.RmaTokenSize), line:76:17, endln:76:29 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:16 |vpiTypespec: \_int_typespec: , line:76:13, endln:76:16 @@ -92664,7 +92664,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.RndCnstDigestConstDefault), line:746:34, endln:746:59 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiTypespec: \_logic_typespec: (digest_const_array_t), line:745:11, endln:745:56 |vpiParent: @@ -92765,7 +92765,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.RndCnstDigestIVDefault), line:755:31, endln:755:53 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiTypespec: \_logic_typespec: (digest_iv_array_t), line:754:11, endln:754:58 |vpiParent: @@ -92866,7 +92866,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.RndCnstKeyDefault), line:737:25, endln:737:42 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiTypespec: \_logic_typespec: (key_array_t), line:736:11, endln:736:56 |vpiParent: @@ -92967,7 +92967,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.RndCnstLfsrPermDefault), line:732:26, endln:732:48 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |HEX:4235171482c225f79289b32181a0163a760355d3447063d16661e44c12a5 |vpiTypespec: \_logic_typespec: (lfsr_perm_t), line:730:11, endln:730:55 @@ -93070,7 +93070,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.RndCnstLfsrSeedDefault), line:731:26, endln:731:48 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |HEX:453d28ea98 |vpiTypespec: \_logic_typespec: (lfsr_seed_t), line:729:11, endln:729:32 @@ -93133,7 +93133,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.RndCnstRawUnlockTokenDefault), line:763:37, endln:763:65 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |HEX:cbbd013ff15eba2f3065461eeb88463e |vpiTypespec: \_unsupported_typespec: (lc_ctrl_pkg::lc_token_t), line:763:13, endln:763:26 @@ -93148,7 +93148,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.ScrmblBlockHalfWords), line:509:17, endln:509:37 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |INT:4 |vpiTypespec: \_int_typespec: , line:509:13, endln:509:16 @@ -93164,7 +93164,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.ScrmblBlockWidth), line:506:17, endln:506:33 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:64 |vpiTypespec: \_int_typespec: , line:506:13, endln:506:16 @@ -93180,7 +93180,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.ScrmblKeyWidth), line:505:17, endln:505:31 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:128 |vpiTypespec: \_int_typespec: , line:505:13, endln:505:16 @@ -93196,7 +93196,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.Secret0DigestOffset), line:61:17, endln:61:36 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:1776 |vpiTypespec: \_int_typespec: , line:61:13, endln:61:16 @@ -93212,7 +93212,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.Secret0DigestSize), line:62:17, endln:62:34 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:8 |vpiTypespec: \_int_typespec: , line:62:13, endln:62:16 @@ -93228,7 +93228,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.Secret0Offset), line:55:17, endln:55:30 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:1744 |vpiTypespec: \_int_typespec: , line:55:13, endln:55:16 @@ -93244,7 +93244,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.Secret0Size), line:56:17, endln:56:28 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:40 |vpiTypespec: \_int_typespec: , line:56:13, endln:56:16 @@ -93260,7 +93260,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.Secret1DigestOffset), line:71:17, endln:71:36 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:1864 |vpiTypespec: \_int_typespec: , line:71:13, endln:71:16 @@ -93276,7 +93276,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.Secret1DigestSize), line:72:17, endln:72:34 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:8 |vpiTypespec: \_int_typespec: , line:72:13, endln:72:16 @@ -93292,7 +93292,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.Secret1Offset), line:63:17, endln:63:30 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:1784 |vpiTypespec: \_int_typespec: , line:63:13, endln:63:16 @@ -93308,7 +93308,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.Secret1Size), line:64:17, endln:64:28 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:88 |vpiTypespec: \_int_typespec: , line:64:13, endln:64:16 @@ -93324,7 +93324,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.Secret2DigestOffset), line:81:17, endln:81:36 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:1984 |vpiTypespec: \_int_typespec: , line:81:13, endln:81:16 @@ -93340,7 +93340,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.Secret2DigestSize), line:82:17, endln:82:34 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:8 |vpiTypespec: \_int_typespec: , line:82:13, endln:82:16 @@ -93356,7 +93356,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.Secret2Offset), line:73:17, endln:73:30 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:1872 |vpiTypespec: \_int_typespec: , line:73:13, endln:73:16 @@ -93372,7 +93372,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.Secret2Size), line:74:17, endln:74:28 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:120 |vpiTypespec: \_int_typespec: , line:74:13, endln:74:16 @@ -93388,7 +93388,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.SramDataKeySeedOffset), line:69:17, endln:69:38 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:1848 |vpiTypespec: \_int_typespec: , line:69:13, endln:69:16 @@ -93404,7 +93404,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.SramDataKeySeedSize), line:70:17, endln:70:36 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:16 |vpiTypespec: \_int_typespec: , line:70:13, endln:70:16 @@ -93420,7 +93420,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.SramKeySeedWidth), line:626:17, endln:626:33 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:128 |vpiTypespec: \_int_typespec: , line:626:13, endln:626:16 @@ -93436,7 +93436,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.SramKeyWidth), line:629:17, endln:629:29 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:128 |vpiTypespec: \_int_typespec: , line:629:13, endln:629:16 @@ -93452,7 +93452,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.SramNonceWidth), line:630:17, endln:630:31 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:64 |vpiTypespec: \_int_typespec: , line:630:13, endln:630:16 @@ -93468,7 +93468,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.SwWindowAddrWidth), line:452:17, endln:452:34 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |INT:9 |vpiTypespec: \_int_typespec: , line:452:13, endln:452:16 @@ -93484,7 +93484,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.TestExitTokenOffset), line:59:17, endln:59:36 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:1760 |vpiTypespec: \_int_typespec: , line:59:13, endln:59:16 @@ -93500,7 +93500,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.TestExitTokenSize), line:60:17, endln:60:34 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:16 |vpiTypespec: \_int_typespec: , line:60:13, endln:60:16 @@ -93516,7 +93516,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.TestUnlockTokenOffset), line:57:17, endln:57:38 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:1744 |vpiTypespec: \_int_typespec: , line:57:13, endln:57:16 @@ -93532,7 +93532,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.TestUnlockTokenSize), line:58:17, endln:58:36 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:16 |vpiTypespec: \_int_typespec: , line:58:13, endln:58:16 @@ -93548,7 +93548,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:27:17, endln:27:39 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:27:38, endln:27:39 |vpiParent: @@ -93583,7 +93583,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:28:17, endln:28:38 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:28:36, endln:28:38 |vpiParent: @@ -93618,7 +93618,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:29:17, endln:29:36 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:29:35, endln:29:36 |vpiParent: @@ -93653,7 +93653,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:30:17, endln:30:32 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:30:31, endln:30:32 |vpiParent: @@ -93688,7 +93688,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:31:17, endln:31:35 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:31:34, endln:31:35 |vpiParent: @@ -93723,7 +93723,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:32:17, endln:32:42 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:32:39, endln:32:42 |vpiParent: @@ -93758,7 +93758,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:33:17, endln:33:41 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:33:39, endln:33:41 |vpiParent: @@ -93793,7 +93793,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:34:17, endln:34:28 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:34:27, endln:34:28 |vpiParent: @@ -93828,7 +93828,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:35:17, endln:35:39 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:35:38, endln:35:39 |vpiParent: @@ -93863,7 +93863,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:36:17, endln:36:39 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:36:36, endln:36:39 |vpiParent: @@ -93898,7 +93898,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:37:17, endln:37:46 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:37:45, endln:37:46 |vpiParent: @@ -93933,7 +93933,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:38:17, endln:38:46 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:38:43, endln:38:46 |vpiParent: @@ -93968,7 +93968,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:39:17, endln:39:47 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:39:44, endln:39:47 |vpiParent: @@ -94003,7 +94003,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:40:17, endln:40:43 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:40:42, endln:40:43 |vpiParent: @@ -94038,7 +94038,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:41:17, endln:41:39 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:41:36, endln:41:39 |vpiParent: @@ -94073,7 +94073,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:42:17, endln:42:37 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:42:34, endln:42:37 |vpiParent: @@ -94108,7 +94108,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:43:17, endln:43:46 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:43:43, endln:43:46 |vpiParent: @@ -94143,7 +94143,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:44:17, endln:44:44 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:44:41, endln:44:44 |vpiParent: @@ -94178,7 +94178,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:45:17, endln:45:46 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:45:42, endln:45:46 |vpiParent: @@ -94213,7 +94213,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:46:17, endln:46:41 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:46:40, endln:46:41 |vpiParent: @@ -94248,7 +94248,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:47:17, endln:47:35 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:47:31, endln:47:35 |vpiParent: @@ -94283,7 +94283,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:48:17, endln:48:32 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:48:29, endln:48:32 |vpiParent: @@ -94318,7 +94318,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:49:17, endln:49:38 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:49:34, endln:49:38 |vpiParent: @@ -94353,7 +94353,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:50:17, endln:50:34 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:50:32, endln:50:34 |vpiParent: @@ -94388,7 +94388,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:51:17, endln:51:42 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:51:38, endln:51:42 |vpiParent: @@ -94423,7 +94423,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:52:17, endln:52:39 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:52:36, endln:52:39 |vpiParent: @@ -94458,7 +94458,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:53:17, endln:53:41 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:53:37, endln:53:41 |vpiParent: @@ -94493,7 +94493,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:54:17, endln:54:36 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:54:35, endln:54:36 |vpiParent: @@ -94528,7 +94528,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:55:17, endln:55:37 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:55:33, endln:55:37 |vpiParent: @@ -94563,7 +94563,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:56:17, endln:56:33 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:56:31, endln:56:33 |vpiParent: @@ -94598,7 +94598,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:57:17, endln:57:45 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:57:41, endln:57:45 |vpiParent: @@ -94633,7 +94633,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:58:17, endln:58:41 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:58:39, endln:58:41 |vpiParent: @@ -94668,7 +94668,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:59:17, endln:59:43 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:59:39, endln:59:43 |vpiParent: @@ -94703,7 +94703,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:60:17, endln:60:39 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:60:37, endln:60:39 |vpiParent: @@ -94738,7 +94738,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:61:17, endln:61:43 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:61:39, endln:61:43 |vpiParent: @@ -94773,7 +94773,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:62:17, endln:62:38 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:62:37, endln:62:38 |vpiParent: @@ -94808,7 +94808,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:63:17, endln:63:37 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:63:33, endln:63:37 |vpiParent: @@ -94843,7 +94843,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:64:17, endln:64:33 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:64:31, endln:64:33 |vpiParent: @@ -94878,7 +94878,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:65:17, endln:65:46 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:65:42, endln:65:46 |vpiParent: @@ -94913,7 +94913,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:66:17, endln:66:42 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:66:40, endln:66:42 |vpiParent: @@ -94948,7 +94948,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:67:17, endln:67:46 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:67:42, endln:67:46 |vpiParent: @@ -94983,7 +94983,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:68:17, endln:68:42 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:68:40, endln:68:42 |vpiParent: @@ -95018,7 +95018,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:69:17, endln:69:45 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:69:41, endln:69:45 |vpiParent: @@ -95053,7 +95053,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:70:17, endln:70:41 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:70:39, endln:70:41 |vpiParent: @@ -95088,7 +95088,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:71:17, endln:71:43 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:71:39, endln:71:43 |vpiParent: @@ -95123,7 +95123,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:72:17, endln:72:38 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:72:37, endln:72:38 |vpiParent: @@ -95158,7 +95158,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:73:17, endln:73:37 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:73:33, endln:73:37 |vpiParent: @@ -95193,7 +95193,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:74:17, endln:74:34 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:74:31, endln:74:34 |vpiParent: @@ -95228,7 +95228,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:75:17, endln:75:38 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:75:34, endln:75:38 |vpiParent: @@ -95263,7 +95263,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:76:17, endln:76:34 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:76:32, endln:76:34 |vpiParent: @@ -95298,7 +95298,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:77:17, endln:77:50 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:77:46, endln:77:50 |vpiParent: @@ -95333,7 +95333,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:78:17, endln:78:46 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:78:44, endln:78:46 |vpiParent: @@ -95368,7 +95368,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:79:17, endln:79:50 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:79:46, endln:79:50 |vpiParent: @@ -95403,7 +95403,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:80:17, endln:80:46 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:80:44, endln:80:46 |vpiParent: @@ -95438,7 +95438,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:81:17, endln:81:43 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:81:39, endln:81:43 |vpiParent: @@ -95473,7 +95473,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:82:17, endln:82:38 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:82:37, endln:82:38 |vpiParent: @@ -95508,7 +95508,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:83:17, endln:83:39 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:83:35, endln:83:39 |vpiParent: @@ -95543,7 +95543,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:84:17, endln:84:35 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:84:33, endln:84:35 |vpiParent: @@ -95578,7 +95578,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:85:17, endln:85:37 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:85:33, endln:85:37 |vpiParent: @@ -95613,7 +95613,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:86:17, endln:86:33 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:86:31, endln:86:33 |vpiParent: @@ -95648,7 +95648,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:87:17, endln:87:45 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:87:41, endln:87:45 |vpiParent: @@ -95683,7 +95683,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:88:17, endln:88:41 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:88:39, endln:88:41 |vpiParent: @@ -95718,7 +95718,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:89:17, endln:89:30 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:89:29, endln:89:30 |vpiParent: @@ -95753,7 +95753,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:322:26, endln:322:60 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:322:55, endln:322:60 |vpiParent: @@ -95825,7 +95825,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:323:26, endln:323:61 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:323:56, endln:323:61 |vpiParent: @@ -95897,7 +95897,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:324:26, endln:324:59 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:324:54, endln:324:59 |vpiParent: @@ -95969,7 +95969,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:325:26, endln:325:60 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:325:55, endln:325:60 |vpiParent: @@ -96041,7 +96041,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:326:26, endln:326:57 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:326:51, endln:326:57 |vpiParent: @@ -96113,7 +96113,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:327:26, endln:327:59 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:327:53, endln:327:59 |vpiParent: @@ -96185,7 +96185,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:328:26, endln:328:71 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:328:65, endln:328:71 |vpiParent: @@ -96257,7 +96257,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:329:26, endln:329:68 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:329:62, endln:329:68 |vpiParent: @@ -96329,7 +96329,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:330:26, endln:330:72 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:330:66, endln:330:72 |vpiParent: @@ -96401,7 +96401,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:331:26, endln:331:72 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:331:66, endln:331:72 |vpiParent: @@ -96473,7 +96473,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:332:26, endln:332:72 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:332:66, endln:332:72 |vpiParent: @@ -96545,7 +96545,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:333:26, endln:333:72 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:333:66, endln:333:72 |vpiParent: @@ -96617,7 +96617,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:334:26, endln:334:72 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:334:66, endln:334:72 |vpiParent: @@ -96689,7 +96689,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:335:26, endln:335:71 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:335:65, endln:335:71 |vpiParent: @@ -96761,7 +96761,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:336:26, endln:336:64 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:336:58, endln:336:64 |vpiParent: @@ -96833,7 +96833,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:337:26, endln:337:63 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:337:57, endln:337:63 |vpiParent: @@ -96905,7 +96905,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:338:26, endln:338:64 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:338:58, endln:338:64 |vpiParent: @@ -96977,7 +96977,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:339:26, endln:339:73 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:339:67, endln:339:73 |vpiParent: @@ -97049,7 +97049,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:340:26, endln:340:75 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:340:69, endln:340:75 |vpiParent: @@ -97121,7 +97121,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:341:26, endln:341:75 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:341:69, endln:341:75 |vpiParent: @@ -97193,7 +97193,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:342:26, endln:342:73 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:342:67, endln:342:73 |vpiParent: @@ -97265,7 +97265,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:343:26, endln:343:74 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:343:68, endln:343:74 |vpiParent: @@ -97337,7 +97337,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:344:26, endln:344:74 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:344:68, endln:344:74 |vpiParent: @@ -97409,7 +97409,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:345:26, endln:345:72 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:345:66, endln:345:72 |vpiParent: @@ -97481,7 +97481,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:346:26, endln:346:72 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:346:66, endln:346:72 |vpiParent: @@ -97553,7 +97553,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:347:26, endln:347:66 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:347:60, endln:347:66 |vpiParent: @@ -97625,7 +97625,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:348:26, endln:348:66 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:348:60, endln:348:66 |vpiParent: @@ -97697,7 +97697,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:349:26, endln:349:67 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:349:61, endln:349:67 |vpiParent: @@ -97769,7 +97769,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:350:26, endln:350:67 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:350:61, endln:350:67 |vpiParent: @@ -97841,7 +97841,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:351:26, endln:351:67 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:351:61, endln:351:67 |vpiParent: @@ -97913,7 +97913,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:352:26, endln:352:67 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:352:61, endln:352:67 |vpiParent: @@ -97985,7 +97985,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:353:26, endln:353:67 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:353:61, endln:353:67 |vpiParent: @@ -98057,7 +98057,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:354:26, endln:354:67 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:354:61, endln:354:67 |vpiParent: @@ -98129,7 +98129,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:357:26, endln:357:66 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:357:58, endln:357:66 |vpiParent: @@ -98201,7 +98201,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:358:26, endln:358:65 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:358:58, endln:358:65 |vpiParent: @@ -98273,7 +98273,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:359:26, endln:359:64 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:359:56, endln:359:64 |vpiParent: @@ -98345,7 +98345,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:360:26, endln:360:62 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:360:56, endln:360:62 |vpiParent: @@ -98417,7 +98417,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:400:25, endln:434:4 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_operation: , line:400:48, endln:434:4 |vpiParent: @@ -98792,7 +98792,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:448:17, endln:448:34 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:448:32, endln:448:34 |vpiParent: @@ -98827,7 +98827,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:450:17, endln:450:46 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:450:32, endln:450:46 |vpiParent: @@ -98862,7 +98862,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:452:17, endln:452:63 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:452:37, endln:452:63 |vpiParent: @@ -98897,7 +98897,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:468:17, endln:468:32 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:468:31, endln:468:32 |vpiParent: @@ -98932,7 +98932,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:480:17, endln:480:38 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:480:36, endln:480:38 |vpiParent: @@ -98967,7 +98967,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:481:17, endln:481:73 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:481:36, endln:481:52 |vpiParent: @@ -99002,7 +99002,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:482:17, endln:482:51 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:482:36, endln:482:37 |vpiParent: @@ -99037,7 +99037,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:483:17, endln:483:37 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:483:36, endln:483:37 |vpiParent: @@ -99072,7 +99072,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:484:17, endln:484:37 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:484:36, endln:484:37 |vpiParent: @@ -99107,7 +99107,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:485:17, endln:485:37 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:485:36, endln:485:37 |vpiParent: @@ -99142,7 +99142,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:486:17, endln:486:60 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:486:36, endln:486:51 |vpiParent: @@ -99177,7 +99177,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:488:17, endln:488:67 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:488:36, endln:488:52 |vpiParent: @@ -99212,7 +99212,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:505:17, endln:505:39 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:505:36, endln:505:39 |vpiParent: @@ -99247,7 +99247,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:506:17, endln:506:38 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:506:36, endln:506:38 |vpiParent: @@ -99282,7 +99282,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:508:17, endln:508:38 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:508:36, endln:508:38 |vpiParent: @@ -99317,7 +99317,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:509:17, endln:509:67 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:509:40, endln:509:56 |vpiParent: @@ -99352,7 +99352,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:520:17, endln:520:34 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:520:33, endln:520:34 |vpiParent: @@ -99387,7 +99387,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:521:17, endln:521:34 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:521:33, endln:521:34 |vpiParent: @@ -99422,7 +99422,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:522:17, endln:524:53 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:522:33, endln:522:64 |vpiParent: @@ -99457,7 +99457,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:587:27, endln:597:4 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_operation: , line:587:49, endln:597:4 |vpiParent: @@ -99786,7 +99786,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:625:17, endln:625:40 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:625:37, endln:625:40 |vpiParent: @@ -99821,7 +99821,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:626:17, endln:626:40 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:626:37, endln:626:40 |vpiParent: @@ -99856,7 +99856,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:627:17, endln:627:39 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:627:36, endln:627:39 |vpiParent: @@ -99891,7 +99891,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:628:17, endln:628:39 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:628:36, endln:628:39 |vpiParent: @@ -99926,7 +99926,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:629:17, endln:629:39 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:629:36, endln:629:39 |vpiParent: @@ -99961,7 +99961,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:630:17, endln:630:38 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:630:36, endln:630:38 |vpiParent: @@ -99996,7 +99996,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:631:17, endln:631:39 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:631:36, endln:631:39 |vpiParent: @@ -100031,7 +100031,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:632:17, endln:632:39 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:632:36, endln:632:39 |vpiParent: @@ -100066,7 +100066,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:645:30, endln:649:4 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_operation: , line:645:55, endln:649:4 |vpiParent: @@ -100229,7 +100229,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:672:33, endln:677:4 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_operation: , line:672:61, endln:677:4 |vpiParent: @@ -100405,7 +100405,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:728:18, endln:728:32 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:728:30, endln:728:32 |vpiParent: @@ -100441,7 +100441,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:731:26, endln:731:65 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:731:51, endln:731:65 |vpiParent: @@ -100570,7 +100570,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:732:26, endln:733:72 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:733:7, endln:733:72 |vpiParent: @@ -100779,7 +100779,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:737:25, endln:741:4 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_operation: , line:737:45, endln:741:4 |vpiParent: @@ -100913,7 +100913,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:746:34, endln:752:4 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_operation: , line:746:62, endln:752:4 |vpiParent: @@ -101063,7 +101063,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:755:31, endln:761:4 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_operation: , line:755:56, endln:761:4 |vpiParent: @@ -101213,7 +101213,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:763:37, endln:764:42 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:764:5, endln:764:42 |vpiParent: @@ -101247,7 +101247,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:27:17, endln:27:39 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:27:38, endln:27:39 |vpiParent: @@ -101282,7 +101282,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:28:17, endln:28:38 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:28:36, endln:28:38 |vpiParent: @@ -101317,7 +101317,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:29:17, endln:29:36 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:29:35, endln:29:36 |vpiParent: @@ -101352,7 +101352,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:30:17, endln:30:32 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:30:31, endln:30:32 |vpiParent: @@ -101387,7 +101387,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:31:17, endln:31:35 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:31:34, endln:31:35 |vpiParent: @@ -101422,7 +101422,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:32:17, endln:32:42 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:32:39, endln:32:42 |vpiParent: @@ -101457,7 +101457,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:33:17, endln:33:41 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:33:39, endln:33:41 |vpiParent: @@ -101492,7 +101492,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:34:17, endln:34:28 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:34:27, endln:34:28 |vpiParent: @@ -101527,7 +101527,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:35:17, endln:35:39 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:35:38, endln:35:39 |vpiParent: @@ -101562,7 +101562,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:36:17, endln:36:39 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:36:36, endln:36:39 |vpiParent: @@ -101597,7 +101597,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:37:17, endln:37:46 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:37:45, endln:37:46 |vpiParent: @@ -101632,7 +101632,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:38:17, endln:38:46 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:38:43, endln:38:46 |vpiParent: @@ -101667,7 +101667,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:39:17, endln:39:47 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:39:44, endln:39:47 |vpiParent: @@ -101702,7 +101702,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:40:17, endln:40:43 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:40:42, endln:40:43 |vpiParent: @@ -101737,7 +101737,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:41:17, endln:41:39 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:41:36, endln:41:39 |vpiParent: @@ -101772,7 +101772,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:42:17, endln:42:37 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:42:34, endln:42:37 |vpiParent: @@ -101807,7 +101807,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:43:17, endln:43:46 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:43:43, endln:43:46 |vpiParent: @@ -101842,7 +101842,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:44:17, endln:44:44 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:44:41, endln:44:44 |vpiParent: @@ -101877,7 +101877,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:45:17, endln:45:46 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:45:42, endln:45:46 |vpiParent: @@ -101912,7 +101912,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:46:17, endln:46:41 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:46:40, endln:46:41 |vpiParent: @@ -101947,7 +101947,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:47:17, endln:47:35 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:47:31, endln:47:35 |vpiParent: @@ -101982,7 +101982,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:48:17, endln:48:32 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:48:29, endln:48:32 |vpiParent: @@ -102017,7 +102017,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:49:17, endln:49:38 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:49:34, endln:49:38 |vpiParent: @@ -102052,7 +102052,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:50:17, endln:50:34 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:50:32, endln:50:34 |vpiParent: @@ -102087,7 +102087,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:51:17, endln:51:42 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:51:38, endln:51:42 |vpiParent: @@ -102122,7 +102122,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:52:17, endln:52:39 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:52:36, endln:52:39 |vpiParent: @@ -102157,7 +102157,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:53:17, endln:53:41 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:53:37, endln:53:41 |vpiParent: @@ -102192,7 +102192,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:54:17, endln:54:36 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:54:35, endln:54:36 |vpiParent: @@ -102227,7 +102227,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:55:17, endln:55:37 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:55:33, endln:55:37 |vpiParent: @@ -102262,7 +102262,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:56:17, endln:56:33 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:56:31, endln:56:33 |vpiParent: @@ -102297,7 +102297,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:57:17, endln:57:45 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:57:41, endln:57:45 |vpiParent: @@ -102332,7 +102332,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:58:17, endln:58:41 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:58:39, endln:58:41 |vpiParent: @@ -102367,7 +102367,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:59:17, endln:59:43 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:59:39, endln:59:43 |vpiParent: @@ -102402,7 +102402,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:60:17, endln:60:39 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:60:37, endln:60:39 |vpiParent: @@ -102437,7 +102437,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:61:17, endln:61:43 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:61:39, endln:61:43 |vpiParent: @@ -102472,7 +102472,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:62:17, endln:62:38 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:62:37, endln:62:38 |vpiParent: @@ -102507,7 +102507,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:63:17, endln:63:37 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:63:33, endln:63:37 |vpiParent: @@ -102542,7 +102542,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:64:17, endln:64:33 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:64:31, endln:64:33 |vpiParent: @@ -102577,7 +102577,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:65:17, endln:65:46 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:65:42, endln:65:46 |vpiParent: @@ -102612,7 +102612,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:66:17, endln:66:42 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:66:40, endln:66:42 |vpiParent: @@ -102647,7 +102647,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:67:17, endln:67:46 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:67:42, endln:67:46 |vpiParent: @@ -102682,7 +102682,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:68:17, endln:68:42 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:68:40, endln:68:42 |vpiParent: @@ -102717,7 +102717,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:69:17, endln:69:45 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:69:41, endln:69:45 |vpiParent: @@ -102752,7 +102752,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:70:17, endln:70:41 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:70:39, endln:70:41 |vpiParent: @@ -102787,7 +102787,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:71:17, endln:71:43 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:71:39, endln:71:43 |vpiParent: @@ -102822,7 +102822,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:72:17, endln:72:38 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:72:37, endln:72:38 |vpiParent: @@ -102857,7 +102857,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:73:17, endln:73:37 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:73:33, endln:73:37 |vpiParent: @@ -102892,7 +102892,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:74:17, endln:74:34 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:74:31, endln:74:34 |vpiParent: @@ -102927,7 +102927,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:75:17, endln:75:38 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:75:34, endln:75:38 |vpiParent: @@ -102962,7 +102962,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:76:17, endln:76:34 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:76:32, endln:76:34 |vpiParent: @@ -102997,7 +102997,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:77:17, endln:77:50 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:77:46, endln:77:50 |vpiParent: @@ -103032,7 +103032,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:78:17, endln:78:46 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:78:44, endln:78:46 |vpiParent: @@ -103067,7 +103067,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:79:17, endln:79:50 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:79:46, endln:79:50 |vpiParent: @@ -103102,7 +103102,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:80:17, endln:80:46 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:80:44, endln:80:46 |vpiParent: @@ -103137,7 +103137,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:81:17, endln:81:43 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:81:39, endln:81:43 |vpiParent: @@ -103172,7 +103172,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:82:17, endln:82:38 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:82:37, endln:82:38 |vpiParent: @@ -103207,7 +103207,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:83:17, endln:83:39 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:83:35, endln:83:39 |vpiParent: @@ -103242,7 +103242,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:84:17, endln:84:35 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:84:33, endln:84:35 |vpiParent: @@ -103277,7 +103277,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:85:17, endln:85:37 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:85:33, endln:85:37 |vpiParent: @@ -103312,7 +103312,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:86:17, endln:86:33 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:86:31, endln:86:33 |vpiParent: @@ -103347,7 +103347,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:87:17, endln:87:45 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:87:41, endln:87:45 |vpiParent: @@ -103382,7 +103382,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:88:17, endln:88:41 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:88:39, endln:88:41 |vpiParent: @@ -103417,7 +103417,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:89:17, endln:89:30 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:89:29, endln:89:30 |vpiParent: @@ -103452,7 +103452,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:322:26, endln:322:60 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:322:55, endln:322:60 |vpiParent: @@ -103524,7 +103524,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:323:26, endln:323:61 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:323:56, endln:323:61 |vpiParent: @@ -103596,7 +103596,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:324:26, endln:324:59 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:324:54, endln:324:59 |vpiParent: @@ -103668,7 +103668,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:325:26, endln:325:60 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:325:55, endln:325:60 |vpiParent: @@ -103740,7 +103740,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:326:26, endln:326:57 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:326:51, endln:326:57 |vpiParent: @@ -103812,7 +103812,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:327:26, endln:327:59 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:327:53, endln:327:59 |vpiParent: @@ -103884,7 +103884,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:328:26, endln:328:71 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:328:65, endln:328:71 |vpiParent: @@ -103956,7 +103956,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:329:26, endln:329:68 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:329:62, endln:329:68 |vpiParent: @@ -104028,7 +104028,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:330:26, endln:330:72 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:330:66, endln:330:72 |vpiParent: @@ -104100,7 +104100,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:331:26, endln:331:72 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:331:66, endln:331:72 |vpiParent: @@ -104172,7 +104172,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:332:26, endln:332:72 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:332:66, endln:332:72 |vpiParent: @@ -104244,7 +104244,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:333:26, endln:333:72 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:333:66, endln:333:72 |vpiParent: @@ -104316,7 +104316,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:334:26, endln:334:72 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:334:66, endln:334:72 |vpiParent: @@ -104388,7 +104388,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:335:26, endln:335:71 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:335:65, endln:335:71 |vpiParent: @@ -104460,7 +104460,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:336:26, endln:336:64 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:336:58, endln:336:64 |vpiParent: @@ -104532,7 +104532,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:337:26, endln:337:63 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:337:57, endln:337:63 |vpiParent: @@ -104604,7 +104604,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:338:26, endln:338:64 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:338:58, endln:338:64 |vpiParent: @@ -104676,7 +104676,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:339:26, endln:339:73 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:339:67, endln:339:73 |vpiParent: @@ -104748,7 +104748,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:340:26, endln:340:75 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:340:69, endln:340:75 |vpiParent: @@ -104820,7 +104820,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:341:26, endln:341:75 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:341:69, endln:341:75 |vpiParent: @@ -104892,7 +104892,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:342:26, endln:342:73 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:342:67, endln:342:73 |vpiParent: @@ -104964,7 +104964,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:343:26, endln:343:74 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:343:68, endln:343:74 |vpiParent: @@ -105036,7 +105036,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:344:26, endln:344:74 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:344:68, endln:344:74 |vpiParent: @@ -105108,7 +105108,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:345:26, endln:345:72 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:345:66, endln:345:72 |vpiParent: @@ -105180,7 +105180,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:346:26, endln:346:72 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:346:66, endln:346:72 |vpiParent: @@ -105252,7 +105252,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:347:26, endln:347:66 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:347:60, endln:347:66 |vpiParent: @@ -105324,7 +105324,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:348:26, endln:348:66 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:348:60, endln:348:66 |vpiParent: @@ -105396,7 +105396,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:349:26, endln:349:67 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:349:61, endln:349:67 |vpiParent: @@ -105468,7 +105468,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:350:26, endln:350:67 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:350:61, endln:350:67 |vpiParent: @@ -105540,7 +105540,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:351:26, endln:351:67 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:351:61, endln:351:67 |vpiParent: @@ -105612,7 +105612,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:352:26, endln:352:67 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:352:61, endln:352:67 |vpiParent: @@ -105684,7 +105684,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:353:26, endln:353:67 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:353:61, endln:353:67 |vpiParent: @@ -105756,7 +105756,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:354:26, endln:354:67 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:354:61, endln:354:67 |vpiParent: @@ -105828,7 +105828,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:357:26, endln:357:66 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:357:58, endln:357:66 |vpiParent: @@ -105900,7 +105900,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:358:26, endln:358:65 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:358:58, endln:358:65 |vpiParent: @@ -105972,7 +105972,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:359:26, endln:359:64 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:359:56, endln:359:64 |vpiParent: @@ -106044,7 +106044,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:360:26, endln:360:62 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:360:56, endln:360:62 |vpiParent: @@ -106116,7 +106116,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:400:25, endln:434:4 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_operation: , line:400:48, endln:434:4 |vpiParent: @@ -106491,7 +106491,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:27:17, endln:27:39 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:27:38, endln:27:39 |vpiParent: @@ -106526,7 +106526,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:28:17, endln:28:38 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:28:36, endln:28:38 |vpiParent: @@ -106561,7 +106561,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:29:17, endln:29:36 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:29:35, endln:29:36 |vpiParent: @@ -106596,7 +106596,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:30:17, endln:30:32 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:30:31, endln:30:32 |vpiParent: @@ -106631,7 +106631,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:31:17, endln:31:35 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:31:34, endln:31:35 |vpiParent: @@ -106666,7 +106666,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:32:17, endln:32:42 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:32:39, endln:32:42 |vpiParent: @@ -106701,7 +106701,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:33:17, endln:33:41 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:33:39, endln:33:41 |vpiParent: @@ -106736,7 +106736,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:34:17, endln:34:28 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:34:27, endln:34:28 |vpiParent: @@ -106771,7 +106771,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:35:17, endln:35:39 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:35:38, endln:35:39 |vpiParent: @@ -106806,7 +106806,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:36:17, endln:36:39 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:36:36, endln:36:39 |vpiParent: @@ -106841,7 +106841,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:37:17, endln:37:46 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:37:45, endln:37:46 |vpiParent: @@ -106876,7 +106876,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:38:17, endln:38:46 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:38:43, endln:38:46 |vpiParent: @@ -106911,7 +106911,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:39:17, endln:39:47 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:39:44, endln:39:47 |vpiParent: @@ -106946,7 +106946,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:40:17, endln:40:43 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:40:42, endln:40:43 |vpiParent: @@ -106981,7 +106981,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:41:17, endln:41:39 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:41:36, endln:41:39 |vpiParent: @@ -107016,7 +107016,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:42:17, endln:42:37 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:42:34, endln:42:37 |vpiParent: @@ -107051,7 +107051,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:43:17, endln:43:46 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:43:43, endln:43:46 |vpiParent: @@ -107086,7 +107086,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:44:17, endln:44:44 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:44:41, endln:44:44 |vpiParent: @@ -107121,7 +107121,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:45:17, endln:45:46 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:45:42, endln:45:46 |vpiParent: @@ -107156,7 +107156,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:46:17, endln:46:41 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:46:40, endln:46:41 |vpiParent: @@ -107191,7 +107191,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:47:17, endln:47:35 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:47:31, endln:47:35 |vpiParent: @@ -107226,7 +107226,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:48:17, endln:48:32 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:48:29, endln:48:32 |vpiParent: @@ -107261,7 +107261,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:49:17, endln:49:38 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:49:34, endln:49:38 |vpiParent: @@ -107296,7 +107296,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:50:17, endln:50:34 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:50:32, endln:50:34 |vpiParent: @@ -107331,7 +107331,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:51:17, endln:51:42 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:51:38, endln:51:42 |vpiParent: @@ -107366,7 +107366,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:52:17, endln:52:39 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:52:36, endln:52:39 |vpiParent: @@ -107401,7 +107401,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:53:17, endln:53:41 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:53:37, endln:53:41 |vpiParent: @@ -107436,7 +107436,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:54:17, endln:54:36 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:54:35, endln:54:36 |vpiParent: @@ -107471,7 +107471,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:55:17, endln:55:37 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:55:33, endln:55:37 |vpiParent: @@ -107506,7 +107506,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:56:17, endln:56:33 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:56:31, endln:56:33 |vpiParent: @@ -107541,7 +107541,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:57:17, endln:57:45 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:57:41, endln:57:45 |vpiParent: @@ -107576,7 +107576,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:58:17, endln:58:41 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:58:39, endln:58:41 |vpiParent: @@ -107611,7 +107611,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:59:17, endln:59:43 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:59:39, endln:59:43 |vpiParent: @@ -107646,7 +107646,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:60:17, endln:60:39 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:60:37, endln:60:39 |vpiParent: @@ -107681,7 +107681,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:61:17, endln:61:43 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:61:39, endln:61:43 |vpiParent: @@ -107716,7 +107716,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:62:17, endln:62:38 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:62:37, endln:62:38 |vpiParent: @@ -107751,7 +107751,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:63:17, endln:63:37 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:63:33, endln:63:37 |vpiParent: @@ -107786,7 +107786,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:64:17, endln:64:33 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:64:31, endln:64:33 |vpiParent: @@ -107821,7 +107821,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:65:17, endln:65:46 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:65:42, endln:65:46 |vpiParent: @@ -107856,7 +107856,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:66:17, endln:66:42 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:66:40, endln:66:42 |vpiParent: @@ -107891,7 +107891,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:67:17, endln:67:46 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:67:42, endln:67:46 |vpiParent: @@ -107926,7 +107926,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:68:17, endln:68:42 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:68:40, endln:68:42 |vpiParent: @@ -107961,7 +107961,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:69:17, endln:69:45 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:69:41, endln:69:45 |vpiParent: @@ -107996,7 +107996,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:70:17, endln:70:41 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:70:39, endln:70:41 |vpiParent: @@ -108031,7 +108031,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:71:17, endln:71:43 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:71:39, endln:71:43 |vpiParent: @@ -108066,7 +108066,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:72:17, endln:72:38 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:72:37, endln:72:38 |vpiParent: @@ -108101,7 +108101,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:73:17, endln:73:37 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:73:33, endln:73:37 |vpiParent: @@ -108136,7 +108136,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:74:17, endln:74:34 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:74:31, endln:74:34 |vpiParent: @@ -108171,7 +108171,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:75:17, endln:75:38 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:75:34, endln:75:38 |vpiParent: @@ -108206,7 +108206,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:76:17, endln:76:34 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:76:32, endln:76:34 |vpiParent: @@ -108241,7 +108241,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:77:17, endln:77:50 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:77:46, endln:77:50 |vpiParent: @@ -108276,7 +108276,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:78:17, endln:78:46 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:78:44, endln:78:46 |vpiParent: @@ -108311,7 +108311,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:79:17, endln:79:50 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:79:46, endln:79:50 |vpiParent: @@ -108346,7 +108346,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:80:17, endln:80:46 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:80:44, endln:80:46 |vpiParent: @@ -108381,7 +108381,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:81:17, endln:81:43 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:81:39, endln:81:43 |vpiParent: @@ -108416,7 +108416,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:82:17, endln:82:38 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:82:37, endln:82:38 |vpiParent: @@ -108451,7 +108451,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:83:17, endln:83:39 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:83:35, endln:83:39 |vpiParent: @@ -108486,7 +108486,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:84:17, endln:84:35 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:84:33, endln:84:35 |vpiParent: @@ -108521,7 +108521,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:85:17, endln:85:37 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:85:33, endln:85:37 |vpiParent: @@ -108556,7 +108556,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:86:17, endln:86:33 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:86:31, endln:86:33 |vpiParent: @@ -108591,7 +108591,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:87:17, endln:87:45 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:87:41, endln:87:45 |vpiParent: @@ -108626,7 +108626,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:88:17, endln:88:41 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:88:39, endln:88:41 |vpiParent: @@ -108661,7 +108661,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:89:17, endln:89:30 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:89:29, endln:89:30 |vpiParent: @@ -108696,7 +108696,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:322:26, endln:322:60 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:322:55, endln:322:60 |vpiParent: @@ -108768,7 +108768,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:323:26, endln:323:61 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:323:56, endln:323:61 |vpiParent: @@ -108840,7 +108840,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:324:26, endln:324:59 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:324:54, endln:324:59 |vpiParent: @@ -108912,7 +108912,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:325:26, endln:325:60 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:325:55, endln:325:60 |vpiParent: @@ -108984,7 +108984,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:326:26, endln:326:57 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:326:51, endln:326:57 |vpiParent: @@ -109056,7 +109056,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:327:26, endln:327:59 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:327:53, endln:327:59 |vpiParent: @@ -109128,7 +109128,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:328:26, endln:328:71 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:328:65, endln:328:71 |vpiParent: @@ -109200,7 +109200,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:329:26, endln:329:68 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:329:62, endln:329:68 |vpiParent: @@ -109272,7 +109272,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:330:26, endln:330:72 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:330:66, endln:330:72 |vpiParent: @@ -109344,7 +109344,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:331:26, endln:331:72 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:331:66, endln:331:72 |vpiParent: @@ -109416,7 +109416,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:332:26, endln:332:72 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:332:66, endln:332:72 |vpiParent: @@ -109488,7 +109488,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:333:26, endln:333:72 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:333:66, endln:333:72 |vpiParent: @@ -109560,7 +109560,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:334:26, endln:334:72 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:334:66, endln:334:72 |vpiParent: @@ -109632,7 +109632,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:335:26, endln:335:71 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:335:65, endln:335:71 |vpiParent: @@ -109704,7 +109704,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:336:26, endln:336:64 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:336:58, endln:336:64 |vpiParent: @@ -109776,7 +109776,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:337:26, endln:337:63 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:337:57, endln:337:63 |vpiParent: @@ -109848,7 +109848,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:338:26, endln:338:64 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:338:58, endln:338:64 |vpiParent: @@ -109920,7 +109920,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:339:26, endln:339:73 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:339:67, endln:339:73 |vpiParent: @@ -109992,7 +109992,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:340:26, endln:340:75 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:340:69, endln:340:75 |vpiParent: @@ -110064,7 +110064,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:341:26, endln:341:75 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:341:69, endln:341:75 |vpiParent: @@ -110136,7 +110136,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:342:26, endln:342:73 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:342:67, endln:342:73 |vpiParent: @@ -110208,7 +110208,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:343:26, endln:343:74 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:343:68, endln:343:74 |vpiParent: @@ -110280,7 +110280,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:344:26, endln:344:74 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:344:68, endln:344:74 |vpiParent: @@ -110352,7 +110352,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:345:26, endln:345:72 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:345:66, endln:345:72 |vpiParent: @@ -110424,7 +110424,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:346:26, endln:346:72 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:346:66, endln:346:72 |vpiParent: @@ -110496,7 +110496,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:347:26, endln:347:66 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:347:60, endln:347:66 |vpiParent: @@ -110568,7 +110568,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:348:26, endln:348:66 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:348:60, endln:348:66 |vpiParent: @@ -110640,7 +110640,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:349:26, endln:349:67 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:349:61, endln:349:67 |vpiParent: @@ -110712,7 +110712,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:350:26, endln:350:67 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:350:61, endln:350:67 |vpiParent: @@ -110784,7 +110784,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:351:26, endln:351:67 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:351:61, endln:351:67 |vpiParent: @@ -110856,7 +110856,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:352:26, endln:352:67 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:352:61, endln:352:67 |vpiParent: @@ -110928,7 +110928,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:353:26, endln:353:67 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:353:61, endln:353:67 |vpiParent: @@ -111000,7 +111000,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:354:26, endln:354:67 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:354:61, endln:354:67 |vpiParent: @@ -111072,7 +111072,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:357:26, endln:357:66 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:357:58, endln:357:66 |vpiParent: @@ -111144,7 +111144,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:358:26, endln:358:65 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:358:58, endln:358:65 |vpiParent: @@ -111216,7 +111216,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:359:26, endln:359:64 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:359:56, endln:359:64 |vpiParent: @@ -111288,7 +111288,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:360:26, endln:360:62 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:360:56, endln:360:62 |vpiParent: @@ -111360,7 +111360,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:400:25, endln:434:4 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_operation: , line:400:48, endln:434:4 |vpiParent: @@ -111735,7 +111735,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:27:17, endln:27:39 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:27:38, endln:27:39 |vpiParent: @@ -111770,7 +111770,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:28:17, endln:28:38 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:28:36, endln:28:38 |vpiParent: @@ -111805,7 +111805,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:29:17, endln:29:36 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:29:35, endln:29:36 |vpiParent: @@ -111840,7 +111840,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:30:17, endln:30:32 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:30:31, endln:30:32 |vpiParent: @@ -111875,7 +111875,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:31:17, endln:31:35 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:31:34, endln:31:35 |vpiParent: @@ -111910,7 +111910,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:32:17, endln:32:42 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:32:39, endln:32:42 |vpiParent: @@ -111945,7 +111945,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:33:17, endln:33:41 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:33:39, endln:33:41 |vpiParent: @@ -111980,7 +111980,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:34:17, endln:34:28 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:34:27, endln:34:28 |vpiParent: @@ -112015,7 +112015,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:35:17, endln:35:39 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:35:38, endln:35:39 |vpiParent: @@ -112050,7 +112050,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:36:17, endln:36:39 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:36:36, endln:36:39 |vpiParent: @@ -112085,7 +112085,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:37:17, endln:37:46 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:37:45, endln:37:46 |vpiParent: @@ -112120,7 +112120,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:38:17, endln:38:46 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:38:43, endln:38:46 |vpiParent: @@ -112155,7 +112155,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:39:17, endln:39:47 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:39:44, endln:39:47 |vpiParent: @@ -112190,7 +112190,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:40:17, endln:40:43 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:40:42, endln:40:43 |vpiParent: @@ -112225,7 +112225,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:41:17, endln:41:39 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:41:36, endln:41:39 |vpiParent: @@ -112260,7 +112260,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:42:17, endln:42:37 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:42:34, endln:42:37 |vpiParent: @@ -112295,7 +112295,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:43:17, endln:43:46 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:43:43, endln:43:46 |vpiParent: @@ -112330,7 +112330,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:44:17, endln:44:44 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:44:41, endln:44:44 |vpiParent: @@ -112365,7 +112365,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:45:17, endln:45:46 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:45:42, endln:45:46 |vpiParent: @@ -112400,7 +112400,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:46:17, endln:46:41 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:46:40, endln:46:41 |vpiParent: @@ -112435,7 +112435,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:47:17, endln:47:35 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:47:31, endln:47:35 |vpiParent: @@ -112470,7 +112470,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:48:17, endln:48:32 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:48:29, endln:48:32 |vpiParent: @@ -112505,7 +112505,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:49:17, endln:49:38 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:49:34, endln:49:38 |vpiParent: @@ -112540,7 +112540,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:50:17, endln:50:34 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:50:32, endln:50:34 |vpiParent: @@ -112575,7 +112575,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:51:17, endln:51:42 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:51:38, endln:51:42 |vpiParent: @@ -112610,7 +112610,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:52:17, endln:52:39 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:52:36, endln:52:39 |vpiParent: @@ -112645,7 +112645,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:53:17, endln:53:41 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:53:37, endln:53:41 |vpiParent: @@ -112680,7 +112680,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:54:17, endln:54:36 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:54:35, endln:54:36 |vpiParent: @@ -112715,7 +112715,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:55:17, endln:55:37 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:55:33, endln:55:37 |vpiParent: @@ -112750,7 +112750,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:56:17, endln:56:33 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:56:31, endln:56:33 |vpiParent: @@ -112785,7 +112785,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:57:17, endln:57:45 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:57:41, endln:57:45 |vpiParent: @@ -112820,7 +112820,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:58:17, endln:58:41 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:58:39, endln:58:41 |vpiParent: @@ -112855,7 +112855,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:59:17, endln:59:43 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:59:39, endln:59:43 |vpiParent: @@ -112890,7 +112890,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:60:17, endln:60:39 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:60:37, endln:60:39 |vpiParent: @@ -112925,7 +112925,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:61:17, endln:61:43 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:61:39, endln:61:43 |vpiParent: @@ -112960,7 +112960,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:62:17, endln:62:38 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:62:37, endln:62:38 |vpiParent: @@ -112995,7 +112995,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:63:17, endln:63:37 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:63:33, endln:63:37 |vpiParent: @@ -113030,7 +113030,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:64:17, endln:64:33 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:64:31, endln:64:33 |vpiParent: @@ -113065,7 +113065,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:65:17, endln:65:46 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:65:42, endln:65:46 |vpiParent: @@ -113100,7 +113100,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:66:17, endln:66:42 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:66:40, endln:66:42 |vpiParent: @@ -113135,7 +113135,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:67:17, endln:67:46 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:67:42, endln:67:46 |vpiParent: @@ -113170,7 +113170,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:68:17, endln:68:42 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:68:40, endln:68:42 |vpiParent: @@ -113205,7 +113205,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:69:17, endln:69:45 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:69:41, endln:69:45 |vpiParent: @@ -113240,7 +113240,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:70:17, endln:70:41 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:70:39, endln:70:41 |vpiParent: @@ -113275,7 +113275,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:71:17, endln:71:43 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:71:39, endln:71:43 |vpiParent: @@ -113310,7 +113310,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:72:17, endln:72:38 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:72:37, endln:72:38 |vpiParent: @@ -113345,7 +113345,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:73:17, endln:73:37 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:73:33, endln:73:37 |vpiParent: @@ -113380,7 +113380,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:74:17, endln:74:34 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:74:31, endln:74:34 |vpiParent: @@ -113415,7 +113415,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:75:17, endln:75:38 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:75:34, endln:75:38 |vpiParent: @@ -113450,7 +113450,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:76:17, endln:76:34 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:76:32, endln:76:34 |vpiParent: @@ -113485,7 +113485,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:77:17, endln:77:50 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:77:46, endln:77:50 |vpiParent: @@ -113520,7 +113520,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:78:17, endln:78:46 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:78:44, endln:78:46 |vpiParent: @@ -113555,7 +113555,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:79:17, endln:79:50 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:79:46, endln:79:50 |vpiParent: @@ -113590,7 +113590,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:80:17, endln:80:46 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:80:44, endln:80:46 |vpiParent: @@ -113625,7 +113625,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:81:17, endln:81:43 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:81:39, endln:81:43 |vpiParent: @@ -113660,7 +113660,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:82:17, endln:82:38 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:82:37, endln:82:38 |vpiParent: @@ -113695,7 +113695,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:83:17, endln:83:39 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:83:35, endln:83:39 |vpiParent: @@ -113730,7 +113730,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:84:17, endln:84:35 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:84:33, endln:84:35 |vpiParent: @@ -113765,7 +113765,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:85:17, endln:85:37 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:85:33, endln:85:37 |vpiParent: @@ -113800,7 +113800,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:86:17, endln:86:33 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:86:31, endln:86:33 |vpiParent: @@ -113835,7 +113835,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:87:17, endln:87:45 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:87:41, endln:87:45 |vpiParent: @@ -113870,7 +113870,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:88:17, endln:88:41 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:88:39, endln:88:41 |vpiParent: @@ -113905,7 +113905,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:89:17, endln:89:30 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:89:29, endln:89:30 |vpiParent: @@ -113940,7 +113940,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:322:26, endln:322:60 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:322:55, endln:322:60 |vpiParent: @@ -114012,7 +114012,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:323:26, endln:323:61 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:323:56, endln:323:61 |vpiParent: @@ -114084,7 +114084,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:324:26, endln:324:59 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:324:54, endln:324:59 |vpiParent: @@ -114156,7 +114156,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:325:26, endln:325:60 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:325:55, endln:325:60 |vpiParent: @@ -114228,7 +114228,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:326:26, endln:326:57 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:326:51, endln:326:57 |vpiParent: @@ -114300,7 +114300,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:327:26, endln:327:59 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:327:53, endln:327:59 |vpiParent: @@ -114372,7 +114372,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:328:26, endln:328:71 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:328:65, endln:328:71 |vpiParent: @@ -114444,7 +114444,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:329:26, endln:329:68 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:329:62, endln:329:68 |vpiParent: @@ -114516,7 +114516,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:330:26, endln:330:72 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:330:66, endln:330:72 |vpiParent: @@ -114588,7 +114588,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:331:26, endln:331:72 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:331:66, endln:331:72 |vpiParent: @@ -114660,7 +114660,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:332:26, endln:332:72 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:332:66, endln:332:72 |vpiParent: @@ -114732,7 +114732,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:333:26, endln:333:72 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:333:66, endln:333:72 |vpiParent: @@ -114804,7 +114804,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:334:26, endln:334:72 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:334:66, endln:334:72 |vpiParent: @@ -114876,7 +114876,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:335:26, endln:335:71 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:335:65, endln:335:71 |vpiParent: @@ -114948,7 +114948,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:336:26, endln:336:64 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:336:58, endln:336:64 |vpiParent: @@ -115020,7 +115020,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:337:26, endln:337:63 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:337:57, endln:337:63 |vpiParent: @@ -115092,7 +115092,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:338:26, endln:338:64 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:338:58, endln:338:64 |vpiParent: @@ -115164,7 +115164,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:339:26, endln:339:73 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:339:67, endln:339:73 |vpiParent: @@ -115236,7 +115236,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:340:26, endln:340:75 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:340:69, endln:340:75 |vpiParent: @@ -115308,7 +115308,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:341:26, endln:341:75 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:341:69, endln:341:75 |vpiParent: @@ -115380,7 +115380,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:342:26, endln:342:73 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:342:67, endln:342:73 |vpiParent: @@ -115452,7 +115452,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:343:26, endln:343:74 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:343:68, endln:343:74 |vpiParent: @@ -115524,7 +115524,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:344:26, endln:344:74 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:344:68, endln:344:74 |vpiParent: @@ -115596,7 +115596,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:345:26, endln:345:72 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:345:66, endln:345:72 |vpiParent: @@ -115668,7 +115668,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:346:26, endln:346:72 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:346:66, endln:346:72 |vpiParent: @@ -115740,7 +115740,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:347:26, endln:347:66 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:347:60, endln:347:66 |vpiParent: @@ -115812,7 +115812,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:348:26, endln:348:66 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:348:60, endln:348:66 |vpiParent: @@ -115884,7 +115884,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:349:26, endln:349:67 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:349:61, endln:349:67 |vpiParent: @@ -115956,7 +115956,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:350:26, endln:350:67 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:350:61, endln:350:67 |vpiParent: @@ -116028,7 +116028,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:351:26, endln:351:67 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:351:61, endln:351:67 |vpiParent: @@ -116100,7 +116100,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:352:26, endln:352:67 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:352:61, endln:352:67 |vpiParent: @@ -116172,7 +116172,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:353:26, endln:353:67 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:353:61, endln:353:67 |vpiParent: @@ -116244,7 +116244,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:354:26, endln:354:67 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:354:61, endln:354:67 |vpiParent: @@ -116316,7 +116316,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:357:26, endln:357:66 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:357:58, endln:357:66 |vpiParent: @@ -116388,7 +116388,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:358:26, endln:358:65 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:358:58, endln:358:65 |vpiParent: @@ -116460,7 +116460,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:359:26, endln:359:64 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:359:56, endln:359:64 |vpiParent: @@ -116532,7 +116532,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:360:26, endln:360:62 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:360:56, endln:360:62 |vpiParent: @@ -116604,7 +116604,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:400:25, endln:434:4 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_operation: , line:400:48, endln:434:4 |vpiParent: @@ -116979,7 +116979,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:448:17, endln:448:34 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:448:32, endln:448:34 |vpiParent: @@ -117014,7 +117014,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:450:17, endln:450:46 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:450:32, endln:450:46 |vpiParent: @@ -117049,7 +117049,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:452:17, endln:452:63 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:452:37, endln:452:63 |vpiParent: @@ -117084,7 +117084,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:468:17, endln:468:32 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:468:31, endln:468:32 |vpiParent: @@ -117119,7 +117119,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:480:17, endln:480:38 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:480:36, endln:480:38 |vpiParent: @@ -117154,7 +117154,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:481:17, endln:481:73 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:481:36, endln:481:52 |vpiParent: @@ -117189,7 +117189,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:482:17, endln:482:51 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:482:36, endln:482:37 |vpiParent: @@ -117224,7 +117224,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:483:17, endln:483:37 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:483:36, endln:483:37 |vpiParent: @@ -117259,7 +117259,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:484:17, endln:484:37 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:484:36, endln:484:37 |vpiParent: @@ -117294,7 +117294,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:485:17, endln:485:37 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:485:36, endln:485:37 |vpiParent: @@ -117329,7 +117329,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:486:17, endln:486:60 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:486:36, endln:486:51 |vpiParent: @@ -117364,7 +117364,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:488:17, endln:488:67 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:488:36, endln:488:52 |vpiParent: @@ -117399,7 +117399,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:505:17, endln:505:39 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:505:36, endln:505:39 |vpiParent: @@ -117434,7 +117434,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:506:17, endln:506:38 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:506:36, endln:506:38 |vpiParent: @@ -117469,7 +117469,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:508:17, endln:508:38 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:508:36, endln:508:38 |vpiParent: @@ -117504,7 +117504,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:509:17, endln:509:67 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:509:40, endln:509:56 |vpiParent: @@ -117539,7 +117539,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:520:17, endln:520:34 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:520:33, endln:520:34 |vpiParent: @@ -117574,7 +117574,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:521:17, endln:521:34 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:521:33, endln:521:34 |vpiParent: @@ -117609,7 +117609,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:522:17, endln:524:53 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:522:33, endln:522:64 |vpiParent: @@ -117644,7 +117644,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:587:27, endln:597:4 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_operation: , line:587:49, endln:597:4 |vpiParent: @@ -117973,7 +117973,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:625:17, endln:625:40 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:625:37, endln:625:40 |vpiParent: @@ -118008,7 +118008,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:626:17, endln:626:40 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:626:37, endln:626:40 |vpiParent: @@ -118043,7 +118043,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:627:17, endln:627:39 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:627:36, endln:627:39 |vpiParent: @@ -118078,7 +118078,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:628:17, endln:628:39 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:628:36, endln:628:39 |vpiParent: @@ -118113,7 +118113,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:629:17, endln:629:39 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:629:36, endln:629:39 |vpiParent: @@ -118148,7 +118148,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:630:17, endln:630:38 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:630:36, endln:630:38 |vpiParent: @@ -118183,7 +118183,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:631:17, endln:631:39 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:631:36, endln:631:39 |vpiParent: @@ -118218,7 +118218,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:632:17, endln:632:39 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:632:36, endln:632:39 |vpiParent: @@ -118253,7 +118253,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:645:30, endln:649:4 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_operation: , line:645:55, endln:649:4 |vpiParent: @@ -118416,7 +118416,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:672:33, endln:677:4 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_operation: , line:672:61, endln:677:4 |vpiParent: @@ -118592,7 +118592,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:728:18, endln:728:32 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:728:30, endln:728:32 |vpiParent: @@ -118628,7 +118628,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:731:26, endln:731:65 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:731:51, endln:731:65 |vpiParent: @@ -118757,7 +118757,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:732:26, endln:733:72 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:733:7, endln:733:72 |vpiParent: @@ -118966,7 +118966,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:737:25, endln:741:4 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_operation: , line:737:45, endln:741:4 |vpiParent: @@ -119100,7 +119100,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:746:34, endln:752:4 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_operation: , line:746:62, endln:752:4 |vpiParent: @@ -119250,7 +119250,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:755:31, endln:761:4 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_operation: , line:755:56, endln:761:4 |vpiParent: @@ -119400,7 +119400,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:763:37, endln:764:42 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:764:5, endln:764:42 |vpiParent: @@ -119434,7 +119434,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:795:26, endln:873:4 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_operation: , line:795:47, endln:873:4 |vpiParent: @@ -120989,14 +120989,14 @@ design: (work@otp_ctrl) |vpiInstance: \_package: otp_ctrl_pkg (otp_ctrl_pkg::), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:438:1, endln:766:26 |uhdmallModules: -\_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 +\_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiParent: \_design: (work@otp_ctrl) |vpiFullName:work@otp_ctrl_part_buf |vpiParameter: \_parameter: (work@otp_ctrl_part_buf.ConstSelWidth), line:522:17, endln:522:30 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |INT:3 |vpiTypespec: \_int_typespec: , line:522:13, endln:522:16 @@ -121012,7 +121012,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl_part_buf.CreatorRootKeyShare0Offset), line:77:17, endln:77:43 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |UINT:1888 |vpiTypespec: \_int_typespec: , line:77:13, endln:77:16 @@ -121028,7 +121028,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl_part_buf.CreatorRootKeyShare0Size), line:78:17, endln:78:41 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |UINT:32 |vpiTypespec: \_int_typespec: , line:78:13, endln:78:16 @@ -121044,7 +121044,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl_part_buf.CreatorRootKeyShare1Offset), line:79:17, endln:79:43 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |UINT:1920 |vpiTypespec: \_int_typespec: , line:79:13, endln:79:16 @@ -121060,7 +121060,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl_part_buf.CreatorRootKeyShare1Size), line:80:17, endln:80:41 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |UINT:32 |vpiTypespec: \_int_typespec: , line:80:13, endln:80:16 @@ -121076,7 +121076,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl_part_buf.CreatorSwCfgContentOffset), line:37:17, endln:37:42 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |UINT:0 |vpiTypespec: \_int_typespec: , line:37:13, endln:37:16 @@ -121092,7 +121092,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl_part_buf.CreatorSwCfgContentSize), line:38:17, endln:38:40 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |UINT:760 |vpiTypespec: \_int_typespec: , line:38:13, endln:38:16 @@ -121108,7 +121108,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl_part_buf.CreatorSwCfgDigestOffset), line:39:17, endln:39:41 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |UINT:760 |vpiTypespec: \_int_typespec: , line:39:13, endln:39:16 @@ -121124,7 +121124,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl_part_buf.CreatorSwCfgDigestSize), line:40:17, endln:40:39 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |UINT:8 |vpiTypespec: \_int_typespec: , line:40:13, endln:40:16 @@ -121140,7 +121140,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl_part_buf.CreatorSwCfgOffset), line:35:17, endln:35:35 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |UINT:0 |vpiTypespec: \_int_typespec: , line:35:13, endln:35:16 @@ -121156,7 +121156,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl_part_buf.CreatorSwCfgSize), line:36:17, endln:36:33 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |UINT:768 |vpiTypespec: \_int_typespec: , line:36:13, endln:36:16 @@ -121172,7 +121172,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl_part_buf.DaiCmdWidth), line:468:17, endln:468:28 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |UINT:3 |vpiTypespec: \_int_typespec: , line:468:13, endln:468:16 @@ -121188,7 +121188,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl_part_buf.DeviceIdOffset), line:49:17, endln:49:31 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |UINT:1536 |vpiTypespec: \_int_typespec: , line:49:13, endln:49:16 @@ -121204,7 +121204,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl_part_buf.DeviceIdSize), line:50:17, endln:50:29 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |UINT:32 |vpiTypespec: \_int_typespec: , line:50:13, endln:50:16 @@ -121220,7 +121220,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl_part_buf.EdnDataWidth), line:448:17, endln:448:29 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |UINT:64 |vpiTypespec: \_int_typespec: , line:448:13, endln:448:16 @@ -121236,7 +121236,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl_part_buf.FLASH_OTP_KEY_RSP_DEFAULT), line:672:33, endln:672:58 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiTypespec: \_struct_typespec: (otp_ctrl_pkg::flash_otp_key_rsp_t), line:664:11, endln:664:17 |vpiParent: @@ -121335,7 +121335,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl_part_buf.FlashAddrKeySeedOffset), line:65:17, endln:65:39 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |UINT:1784 |vpiTypespec: \_int_typespec: , line:65:13, endln:65:16 @@ -121351,7 +121351,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl_part_buf.FlashAddrKeySeedSize), line:66:17, endln:66:37 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |UINT:32 |vpiTypespec: \_int_typespec: , line:66:13, endln:66:16 @@ -121367,7 +121367,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl_part_buf.FlashDataKeySeedOffset), line:67:17, endln:67:39 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |UINT:1816 |vpiTypespec: \_int_typespec: , line:67:13, endln:67:16 @@ -121383,7 +121383,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl_part_buf.FlashDataKeySeedSize), line:68:17, endln:68:37 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |UINT:32 |vpiTypespec: \_int_typespec: , line:68:13, endln:68:16 @@ -121399,7 +121399,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl_part_buf.FlashKeySeedWidth), line:625:17, endln:625:34 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |UINT:256 |vpiTypespec: \_int_typespec: , line:625:13, endln:625:16 @@ -121415,7 +121415,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl_part_buf.FlashKeyWidth), line:628:17, endln:628:30 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |UINT:128 |vpiTypespec: \_int_typespec: , line:628:13, endln:628:16 @@ -121431,7 +121431,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl_part_buf.HwCfgContentOffset), line:51:17, endln:51:35 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |UINT:1568 |vpiTypespec: \_int_typespec: , line:51:13, endln:51:16 @@ -121447,7 +121447,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl_part_buf.HwCfgContentSize), line:52:17, endln:52:33 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |UINT:168 |vpiTypespec: \_int_typespec: , line:52:13, endln:52:16 @@ -121463,7 +121463,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl_part_buf.HwCfgDigestOffset), line:53:17, endln:53:34 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |UINT:1736 |vpiTypespec: \_int_typespec: , line:53:13, endln:53:16 @@ -121479,7 +121479,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl_part_buf.HwCfgDigestSize), line:54:17, endln:54:32 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |UINT:8 |vpiTypespec: \_int_typespec: , line:54:13, endln:54:16 @@ -121495,7 +121495,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl_part_buf.HwCfgOffset), line:47:17, endln:47:28 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |UINT:1536 |vpiTypespec: \_int_typespec: , line:47:13, endln:47:16 @@ -121511,7 +121511,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl_part_buf.HwCfgSize), line:48:17, endln:48:26 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |UINT:208 |vpiTypespec: \_int_typespec: , line:48:13, endln:48:16 @@ -121527,7 +121527,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl_part_buf.KeyMgrKeyWidth), line:627:17, endln:627:31 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |UINT:256 |vpiTypespec: \_int_typespec: , line:627:13, endln:627:16 @@ -121543,7 +121543,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl_part_buf.LcStateOffset), line:85:17, endln:85:30 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |UINT:1992 |vpiTypespec: \_int_typespec: , line:85:13, endln:85:16 @@ -121559,7 +121559,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl_part_buf.LcStateSize), line:86:17, endln:86:28 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |UINT:24 |vpiTypespec: \_int_typespec: , line:86:13, endln:86:16 @@ -121575,7 +121575,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl_part_buf.LcTransitionCntOffset), line:87:17, endln:87:38 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |UINT:2016 |vpiTypespec: \_int_typespec: , line:87:13, endln:87:16 @@ -121591,7 +121591,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl_part_buf.LcTransitionCntSize), line:88:17, endln:88:36 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |UINT:32 |vpiTypespec: \_int_typespec: , line:88:13, endln:88:16 @@ -121607,7 +121607,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl_part_buf.LfsrWidth), line:728:18, endln:728:27 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |UINT:40 |vpiTypespec: \_int_typespec: , line:728:14, endln:728:17 @@ -121624,7 +121624,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl_part_buf.LifeCycleOffset), line:83:17, endln:83:32 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |UINT:1992 |vpiTypespec: \_int_typespec: , line:83:13, endln:83:16 @@ -121640,7 +121640,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl_part_buf.LifeCycleSize), line:84:17, endln:84:30 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |UINT:56 |vpiTypespec: \_int_typespec: , line:84:13, endln:84:16 @@ -121656,7 +121656,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl_part_buf.NumAlerts), line:89:17, endln:89:26 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |UINT:2 |vpiTypespec: \_int_typespec: , line:89:13, endln:89:16 @@ -121672,7 +121672,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl_part_buf.NumDaiWords), line:30:17, endln:30:28 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |UINT:2 |vpiTypespec: \_int_typespec: , line:30:13, endln:30:16 @@ -121688,7 +121688,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl_part_buf.NumDebugWindowWords), line:33:17, endln:33:36 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |UINT:16 |vpiTypespec: \_int_typespec: , line:33:13, endln:33:16 @@ -121704,7 +121704,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl_part_buf.NumDigestSets), line:521:17, endln:521:30 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |UINT:5 |vpiTypespec: \_int_typespec: , line:521:13, endln:521:16 @@ -121720,7 +121720,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl_part_buf.NumDigestWords), line:31:17, endln:31:31 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |UINT:2 |vpiTypespec: \_int_typespec: , line:31:13, endln:31:16 @@ -121736,7 +121736,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl_part_buf.NumErrorEntries), line:29:17, endln:29:32 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |UINT:9 |vpiTypespec: \_int_typespec: , line:29:13, endln:29:16 @@ -121752,7 +121752,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl_part_buf.NumPart), line:34:17, endln:34:24 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |UINT:7 |vpiTypespec: \_int_typespec: , line:34:13, endln:34:16 @@ -121768,7 +121768,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl_part_buf.NumPartWidth), line:450:17, endln:450:29 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |INT:3 |vpiTypespec: \_int_typespec: , line:450:13, endln:450:16 @@ -121784,7 +121784,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl_part_buf.NumPresentRounds), line:508:17, endln:508:33 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |UINT:31 |vpiTypespec: \_int_typespec: , line:508:13, endln:508:16 @@ -121800,7 +121800,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl_part_buf.NumScrmblKeys), line:520:17, endln:520:30 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |UINT:3 |vpiTypespec: \_int_typespec: , line:520:13, endln:520:16 @@ -121816,7 +121816,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl_part_buf.NumSramKeyReqSlots), line:27:17, endln:27:35 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |UINT:2 |vpiTypespec: \_int_typespec: , line:27:13, endln:27:16 @@ -121832,7 +121832,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl_part_buf.NumSwCfgWindowWords), line:32:17, endln:32:36 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |UINT:512 |vpiTypespec: \_int_typespec: , line:32:13, endln:32:16 @@ -121848,7 +121848,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl_part_buf.OTP_CTRL_ALERT_TEST_OFFSET), line:325:26, endln:325:52 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |HEX:c |vpiTypespec: \_logic_typespec: , line:325:13, endln:325:25 @@ -121882,7 +121882,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl_part_buf.OTP_CTRL_CHECK_REGWEN_OFFSET), line:337:26, endln:337:54 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |HEX:3c |vpiTypespec: \_logic_typespec: , line:337:13, endln:337:25 @@ -121916,7 +121916,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl_part_buf.OTP_CTRL_CHECK_TIMEOUT_OFFSET), line:338:26, endln:338:55 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |HEX:40 |vpiTypespec: \_logic_typespec: , line:338:13, endln:338:25 @@ -121950,7 +121950,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl_part_buf.OTP_CTRL_CHECK_TRIGGER_OFFSET), line:336:26, endln:336:55 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |HEX:38 |vpiTypespec: \_logic_typespec: , line:336:13, endln:336:25 @@ -121984,7 +121984,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl_part_buf.OTP_CTRL_CHECK_TRIGGER_REGWEN_OFFSET), line:335:26, endln:335:62 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |HEX:34 |vpiTypespec: \_logic_typespec: , line:335:13, endln:335:25 @@ -122018,7 +122018,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl_part_buf.OTP_CTRL_CONSISTENCY_CHECK_PERIOD_OFFSET), line:340:26, endln:340:66 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |HEX:48 |vpiTypespec: \_logic_typespec: , line:340:13, endln:340:25 @@ -122052,7 +122052,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl_part_buf.OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_OFFSET), line:343:26, endln:343:65 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |HEX:54 |vpiTypespec: \_logic_typespec: , line:343:13, endln:343:25 @@ -122086,7 +122086,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl_part_buf.OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_OFFSET), line:344:26, endln:344:65 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |HEX:58 |vpiTypespec: \_logic_typespec: , line:344:13, endln:344:25 @@ -122120,7 +122120,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl_part_buf.OTP_CTRL_CREATOR_SW_CFG_READ_LOCK_OFFSET), line:341:26, endln:341:66 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |HEX:4c |vpiTypespec: \_logic_typespec: , line:341:13, endln:341:25 @@ -122154,7 +122154,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl_part_buf.OTP_CTRL_DIRECT_ACCESS_ADDRESS_OFFSET), line:330:26, endln:330:63 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |HEX:20 |vpiTypespec: \_logic_typespec: , line:330:13, endln:330:25 @@ -122188,7 +122188,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl_part_buf.OTP_CTRL_DIRECT_ACCESS_CMD_OFFSET), line:329:26, endln:329:59 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |HEX:1c |vpiTypespec: \_logic_typespec: , line:329:13, endln:329:25 @@ -122222,7 +122222,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl_part_buf.OTP_CTRL_DIRECT_ACCESS_RDATA_0_OFFSET), line:333:26, endln:333:63 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |HEX:2c |vpiTypespec: \_logic_typespec: , line:333:13, endln:333:25 @@ -122256,7 +122256,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl_part_buf.OTP_CTRL_DIRECT_ACCESS_RDATA_1_OFFSET), line:334:26, endln:334:63 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |HEX:30 |vpiTypespec: \_logic_typespec: , line:334:13, endln:334:25 @@ -122290,7 +122290,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl_part_buf.OTP_CTRL_DIRECT_ACCESS_REGWEN_OFFSET), line:328:26, endln:328:62 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |HEX:18 |vpiTypespec: \_logic_typespec: , line:328:13, endln:328:25 @@ -122324,7 +122324,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl_part_buf.OTP_CTRL_DIRECT_ACCESS_WDATA_0_OFFSET), line:331:26, endln:331:63 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |HEX:24 |vpiTypespec: \_logic_typespec: , line:331:13, endln:331:25 @@ -122358,7 +122358,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl_part_buf.OTP_CTRL_DIRECT_ACCESS_WDATA_1_OFFSET), line:332:26, endln:332:63 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |HEX:28 |vpiTypespec: \_logic_typespec: , line:332:13, endln:332:25 @@ -122392,7 +122392,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl_part_buf.OTP_CTRL_ERR_CODE_OFFSET), line:327:26, endln:327:50 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |HEX:14 |vpiTypespec: \_logic_typespec: , line:327:13, endln:327:25 @@ -122426,7 +122426,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl_part_buf.OTP_CTRL_HW_CFG_DIGEST_0_OFFSET), line:347:26, endln:347:57 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |HEX:64 |vpiTypespec: \_logic_typespec: , line:347:13, endln:347:25 @@ -122460,7 +122460,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl_part_buf.OTP_CTRL_HW_CFG_DIGEST_1_OFFSET), line:348:26, endln:348:57 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |HEX:68 |vpiTypespec: \_logic_typespec: , line:348:13, endln:348:25 @@ -122494,7 +122494,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl_part_buf.OTP_CTRL_INTEGRITY_CHECK_PERIOD_OFFSET), line:339:26, endln:339:64 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |HEX:44 |vpiTypespec: \_logic_typespec: , line:339:13, endln:339:25 @@ -122528,7 +122528,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl_part_buf.OTP_CTRL_INTR_ENABLE_OFFSET), line:323:26, endln:323:53 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |HEX:4 |vpiTypespec: \_logic_typespec: , line:323:13, endln:323:25 @@ -122562,7 +122562,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl_part_buf.OTP_CTRL_INTR_STATE_OFFSET), line:322:26, endln:322:52 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |HEX:0 |vpiTypespec: \_logic_typespec: , line:322:13, endln:322:25 @@ -122596,7 +122596,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl_part_buf.OTP_CTRL_INTR_TEST_OFFSET), line:324:26, endln:324:51 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |HEX:8 |vpiTypespec: \_logic_typespec: , line:324:13, endln:324:25 @@ -122630,7 +122630,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl_part_buf.OTP_CTRL_OWNER_SW_CFG_DIGEST_0_OFFSET), line:345:26, endln:345:63 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |HEX:5c |vpiTypespec: \_logic_typespec: , line:345:13, endln:345:25 @@ -122664,7 +122664,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl_part_buf.OTP_CTRL_OWNER_SW_CFG_DIGEST_1_OFFSET), line:346:26, endln:346:63 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |HEX:60 |vpiTypespec: \_logic_typespec: , line:346:13, endln:346:25 @@ -122698,7 +122698,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl_part_buf.OTP_CTRL_OWNER_SW_CFG_READ_LOCK_OFFSET), line:342:26, endln:342:64 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |HEX:50 |vpiTypespec: \_logic_typespec: , line:342:13, endln:342:25 @@ -122732,7 +122732,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl_part_buf.OTP_CTRL_PERMIT), line:400:25, endln:400:40 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiSize:33 |vpiTypespec: \_array_typespec: @@ -122834,7 +122834,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl_part_buf.OTP_CTRL_SECRET0_DIGEST_0_OFFSET), line:349:26, endln:349:58 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |HEX:6c |vpiTypespec: \_logic_typespec: , line:349:13, endln:349:25 @@ -122868,7 +122868,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl_part_buf.OTP_CTRL_SECRET0_DIGEST_1_OFFSET), line:350:26, endln:350:58 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |HEX:70 |vpiTypespec: \_logic_typespec: , line:350:13, endln:350:25 @@ -122902,7 +122902,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl_part_buf.OTP_CTRL_SECRET1_DIGEST_0_OFFSET), line:351:26, endln:351:58 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |HEX:74 |vpiTypespec: \_logic_typespec: , line:351:13, endln:351:25 @@ -122936,7 +122936,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl_part_buf.OTP_CTRL_SECRET1_DIGEST_1_OFFSET), line:352:26, endln:352:58 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |HEX:78 |vpiTypespec: \_logic_typespec: , line:352:13, endln:352:25 @@ -122970,7 +122970,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl_part_buf.OTP_CTRL_SECRET2_DIGEST_0_OFFSET), line:353:26, endln:353:58 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |HEX:7c |vpiTypespec: \_logic_typespec: , line:353:13, endln:353:25 @@ -123004,7 +123004,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl_part_buf.OTP_CTRL_SECRET2_DIGEST_1_OFFSET), line:354:26, endln:354:58 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |HEX:80 |vpiTypespec: \_logic_typespec: , line:354:13, endln:354:25 @@ -123038,7 +123038,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl_part_buf.OTP_CTRL_STATUS_OFFSET), line:326:26, endln:326:48 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |HEX:10 |vpiTypespec: \_logic_typespec: , line:326:13, endln:326:25 @@ -123072,7 +123072,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl_part_buf.OTP_CTRL_SW_CFG_WINDOW_OFFSET), line:357:26, endln:357:55 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |HEX:1000 |vpiTypespec: \_logic_typespec: , line:357:13, endln:357:25 @@ -123106,7 +123106,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl_part_buf.OTP_CTRL_SW_CFG_WINDOW_SIZE), line:358:26, endln:358:53 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |HEX:800 |vpiTypespec: \_logic_typespec: , line:358:13, endln:358:25 @@ -123140,7 +123140,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl_part_buf.OTP_CTRL_TEST_ACCESS_OFFSET), line:359:26, endln:359:53 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |HEX:2000 |vpiTypespec: \_logic_typespec: , line:359:13, endln:359:25 @@ -123174,7 +123174,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl_part_buf.OTP_CTRL_TEST_ACCESS_SIZE), line:360:26, endln:360:51 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |HEX:40 |vpiTypespec: \_logic_typespec: , line:360:13, endln:360:25 @@ -123208,7 +123208,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl_part_buf.OTP_KEYMGR_KEY_DEFAULT), line:645:30, endln:645:52 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiTypespec: \_struct_typespec: (otp_ctrl_pkg::otp_keymgr_key_t), line:639:11, endln:639:17 |vpiParent: @@ -123311,7 +123311,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl_part_buf.OTP_LC_DATA_DEFAULT), line:587:27, endln:587:46 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiTypespec: \_struct_typespec: (otp_ctrl_pkg::otp_lc_data_t), line:573:11, endln:573:17 |vpiParent: @@ -123478,7 +123478,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl_part_buf.OtbnKeyWidth), line:631:17, endln:631:29 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |UINT:128 |vpiTypespec: \_int_typespec: , line:631:13, endln:631:16 @@ -123494,7 +123494,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl_part_buf.OtbnNonceWidth), line:632:17, endln:632:31 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |UINT:256 |vpiTypespec: \_int_typespec: , line:632:13, endln:632:16 @@ -123510,7 +123510,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl_part_buf.OtpAddrShift), line:488:17, endln:488:29 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |INT:1 |vpiTypespec: \_int_typespec: , line:488:13, endln:488:16 @@ -123526,7 +123526,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl_part_buf.OtpAddrWidth), line:481:17, endln:481:29 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |INT:10 |vpiTypespec: \_int_typespec: , line:481:13, endln:481:16 @@ -123542,7 +123542,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl_part_buf.OtpByteAddrWidth), line:28:17, endln:28:33 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |UINT:11 |vpiTypespec: \_int_typespec: , line:28:13, endln:28:16 @@ -123558,7 +123558,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl_part_buf.OtpDepth), line:482:17, endln:482:25 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |INT:1024 |vpiTypespec: \_int_typespec: , line:482:13, endln:482:16 @@ -123574,7 +123574,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl_part_buf.OtpErrWidth), line:484:17, endln:484:28 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |UINT:3 |vpiTypespec: \_int_typespec: , line:484:13, endln:484:16 @@ -123590,7 +123590,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl_part_buf.OtpIfWidth), line:486:17, endln:486:27 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |INT:64 |vpiTypespec: \_int_typespec: , line:486:13, endln:486:16 @@ -123606,7 +123606,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl_part_buf.OtpPwrSeqWidth), line:485:17, endln:485:31 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |UINT:2 |vpiTypespec: \_int_typespec: , line:485:13, endln:485:16 @@ -123622,7 +123622,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl_part_buf.OtpSizeWidth), line:483:17, endln:483:29 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |UINT:2 |vpiTypespec: \_int_typespec: , line:483:13, endln:483:16 @@ -123638,7 +123638,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl_part_buf.OtpWidth), line:480:17, endln:480:25 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |UINT:16 |vpiTypespec: \_int_typespec: , line:480:13, endln:480:16 @@ -123654,7 +123654,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl_part_buf.OwnerSwCfgContentOffset), line:43:17, endln:43:40 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |UINT:768 |vpiTypespec: \_int_typespec: , line:43:13, endln:43:16 @@ -123670,7 +123670,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl_part_buf.OwnerSwCfgContentSize), line:44:17, endln:44:38 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |UINT:760 |vpiTypespec: \_int_typespec: , line:44:13, endln:44:16 @@ -123686,7 +123686,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl_part_buf.OwnerSwCfgDigestOffset), line:45:17, endln:45:39 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |UINT:1528 |vpiTypespec: \_int_typespec: , line:45:13, endln:45:16 @@ -123702,7 +123702,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl_part_buf.OwnerSwCfgDigestSize), line:46:17, endln:46:37 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |UINT:8 |vpiTypespec: \_int_typespec: , line:46:13, endln:46:16 @@ -123718,7 +123718,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl_part_buf.OwnerSwCfgOffset), line:41:17, endln:41:33 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |UINT:768 |vpiTypespec: \_int_typespec: , line:41:13, endln:41:16 @@ -123734,7 +123734,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl_part_buf.OwnerSwCfgSize), line:42:17, endln:42:31 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |UINT:768 |vpiTypespec: \_int_typespec: , line:42:13, endln:42:16 @@ -123750,7 +123750,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl_part_buf.RmaTokenOffset), line:75:17, endln:75:31 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |UINT:1872 |vpiTypespec: \_int_typespec: , line:75:13, endln:75:16 @@ -123766,7 +123766,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl_part_buf.RmaTokenSize), line:76:17, endln:76:29 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |UINT:16 |vpiTypespec: \_int_typespec: , line:76:13, endln:76:16 @@ -123782,7 +123782,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl_part_buf.RndCnstDigestConstDefault), line:746:34, endln:746:59 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiTypespec: \_logic_typespec: (digest_const_array_t), line:745:11, endln:745:56 |vpiParent: @@ -123883,7 +123883,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl_part_buf.RndCnstDigestIVDefault), line:755:31, endln:755:53 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiTypespec: \_logic_typespec: (digest_iv_array_t), line:754:11, endln:754:58 |vpiParent: @@ -123984,7 +123984,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl_part_buf.RndCnstKeyDefault), line:737:25, endln:737:42 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiTypespec: \_logic_typespec: (key_array_t), line:736:11, endln:736:56 |vpiParent: @@ -124085,7 +124085,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl_part_buf.RndCnstLfsrPermDefault), line:732:26, endln:732:48 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |HEX:4235171482c225f79289b32181a0163a760355d3447063d16661e44c12a5 |vpiTypespec: \_logic_typespec: (lfsr_perm_t), line:730:11, endln:730:55 @@ -124188,7 +124188,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl_part_buf.RndCnstLfsrSeedDefault), line:731:26, endln:731:48 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |HEX:453d28ea98 |vpiTypespec: \_logic_typespec: (lfsr_seed_t), line:729:11, endln:729:32 @@ -124251,7 +124251,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl_part_buf.RndCnstRawUnlockTokenDefault), line:763:37, endln:763:65 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |HEX:cbbd013ff15eba2f3065461eeb88463e |vpiTypespec: \_unsupported_typespec: (lc_ctrl_pkg::lc_token_t), line:763:13, endln:763:26 @@ -124266,7 +124266,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl_part_buf.ScrmblBlockHalfWords), line:509:17, endln:509:37 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |INT:4 |vpiTypespec: \_int_typespec: , line:509:13, endln:509:16 @@ -124282,7 +124282,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl_part_buf.ScrmblBlockWidth), line:506:17, endln:506:33 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |UINT:64 |vpiTypespec: \_int_typespec: , line:506:13, endln:506:16 @@ -124298,7 +124298,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl_part_buf.ScrmblKeyWidth), line:505:17, endln:505:31 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |UINT:128 |vpiTypespec: \_int_typespec: , line:505:13, endln:505:16 @@ -124314,7 +124314,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl_part_buf.Secret0DigestOffset), line:61:17, endln:61:36 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |UINT:1776 |vpiTypespec: \_int_typespec: , line:61:13, endln:61:16 @@ -124330,7 +124330,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl_part_buf.Secret0DigestSize), line:62:17, endln:62:34 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |UINT:8 |vpiTypespec: \_int_typespec: , line:62:13, endln:62:16 @@ -124346,7 +124346,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl_part_buf.Secret0Offset), line:55:17, endln:55:30 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |UINT:1744 |vpiTypespec: \_int_typespec: , line:55:13, endln:55:16 @@ -124362,7 +124362,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl_part_buf.Secret0Size), line:56:17, endln:56:28 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |UINT:40 |vpiTypespec: \_int_typespec: , line:56:13, endln:56:16 @@ -124378,7 +124378,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl_part_buf.Secret1DigestOffset), line:71:17, endln:71:36 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |UINT:1864 |vpiTypespec: \_int_typespec: , line:71:13, endln:71:16 @@ -124394,7 +124394,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl_part_buf.Secret1DigestSize), line:72:17, endln:72:34 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |UINT:8 |vpiTypespec: \_int_typespec: , line:72:13, endln:72:16 @@ -124410,7 +124410,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl_part_buf.Secret1Offset), line:63:17, endln:63:30 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |UINT:1784 |vpiTypespec: \_int_typespec: , line:63:13, endln:63:16 @@ -124426,7 +124426,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl_part_buf.Secret1Size), line:64:17, endln:64:28 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |UINT:88 |vpiTypespec: \_int_typespec: , line:64:13, endln:64:16 @@ -124442,7 +124442,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl_part_buf.Secret2DigestOffset), line:81:17, endln:81:36 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |UINT:1984 |vpiTypespec: \_int_typespec: , line:81:13, endln:81:16 @@ -124458,7 +124458,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl_part_buf.Secret2DigestSize), line:82:17, endln:82:34 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |UINT:8 |vpiTypespec: \_int_typespec: , line:82:13, endln:82:16 @@ -124474,7 +124474,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl_part_buf.Secret2Offset), line:73:17, endln:73:30 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |UINT:1872 |vpiTypespec: \_int_typespec: , line:73:13, endln:73:16 @@ -124490,7 +124490,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl_part_buf.Secret2Size), line:74:17, endln:74:28 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |UINT:120 |vpiTypespec: \_int_typespec: , line:74:13, endln:74:16 @@ -124506,7 +124506,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl_part_buf.SramDataKeySeedOffset), line:69:17, endln:69:38 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |UINT:1848 |vpiTypespec: \_int_typespec: , line:69:13, endln:69:16 @@ -124522,7 +124522,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl_part_buf.SramDataKeySeedSize), line:70:17, endln:70:36 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |UINT:16 |vpiTypespec: \_int_typespec: , line:70:13, endln:70:16 @@ -124538,7 +124538,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl_part_buf.SramKeySeedWidth), line:626:17, endln:626:33 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |UINT:128 |vpiTypespec: \_int_typespec: , line:626:13, endln:626:16 @@ -124554,7 +124554,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl_part_buf.SramKeyWidth), line:629:17, endln:629:29 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |UINT:128 |vpiTypespec: \_int_typespec: , line:629:13, endln:629:16 @@ -124570,7 +124570,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl_part_buf.SramNonceWidth), line:630:17, endln:630:31 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |UINT:64 |vpiTypespec: \_int_typespec: , line:630:13, endln:630:16 @@ -124586,7 +124586,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl_part_buf.SwWindowAddrWidth), line:452:17, endln:452:34 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |INT:9 |vpiTypespec: \_int_typespec: , line:452:13, endln:452:16 @@ -124602,7 +124602,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl_part_buf.TestExitTokenOffset), line:59:17, endln:59:36 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |UINT:1760 |vpiTypespec: \_int_typespec: , line:59:13, endln:59:16 @@ -124618,7 +124618,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl_part_buf.TestExitTokenSize), line:60:17, endln:60:34 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |UINT:16 |vpiTypespec: \_int_typespec: , line:60:13, endln:60:16 @@ -124634,7 +124634,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl_part_buf.TestUnlockTokenOffset), line:57:17, endln:57:38 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |UINT:1744 |vpiTypespec: \_int_typespec: , line:57:13, endln:57:16 @@ -124650,7 +124650,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl_part_buf.TestUnlockTokenSize), line:58:17, endln:58:36 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |UINT:16 |vpiTypespec: \_int_typespec: , line:58:13, endln:58:16 @@ -124666,7 +124666,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl_part_buf.CreatorRootKeyShare0Offset), line:77:17, endln:77:43 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |UINT:1888 |vpiTypespec: \_int_typespec: , line:77:13, endln:77:16 @@ -124682,7 +124682,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl_part_buf.CreatorRootKeyShare0Size), line:78:17, endln:78:41 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |UINT:32 |vpiTypespec: \_int_typespec: , line:78:13, endln:78:16 @@ -124698,7 +124698,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl_part_buf.CreatorRootKeyShare1Offset), line:79:17, endln:79:43 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |UINT:1920 |vpiTypespec: \_int_typespec: , line:79:13, endln:79:16 @@ -124714,7 +124714,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl_part_buf.CreatorRootKeyShare1Size), line:80:17, endln:80:41 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |UINT:32 |vpiTypespec: \_int_typespec: , line:80:13, endln:80:16 @@ -124730,7 +124730,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl_part_buf.CreatorSwCfgContentOffset), line:37:17, endln:37:42 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |UINT:0 |vpiTypespec: \_int_typespec: , line:37:13, endln:37:16 @@ -124746,7 +124746,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl_part_buf.CreatorSwCfgContentSize), line:38:17, endln:38:40 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |UINT:760 |vpiTypespec: \_int_typespec: , line:38:13, endln:38:16 @@ -124762,7 +124762,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl_part_buf.CreatorSwCfgDigestOffset), line:39:17, endln:39:41 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |UINT:760 |vpiTypespec: \_int_typespec: , line:39:13, endln:39:16 @@ -124778,7 +124778,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl_part_buf.CreatorSwCfgDigestSize), line:40:17, endln:40:39 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |UINT:8 |vpiTypespec: \_int_typespec: , line:40:13, endln:40:16 @@ -124794,7 +124794,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl_part_buf.CreatorSwCfgOffset), line:35:17, endln:35:35 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |UINT:0 |vpiTypespec: \_int_typespec: , line:35:13, endln:35:16 @@ -124810,7 +124810,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl_part_buf.CreatorSwCfgSize), line:36:17, endln:36:33 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |UINT:768 |vpiTypespec: \_int_typespec: , line:36:13, endln:36:16 @@ -124826,7 +124826,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl_part_buf.DeviceIdOffset), line:49:17, endln:49:31 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |UINT:1536 |vpiTypespec: \_int_typespec: , line:49:13, endln:49:16 @@ -124842,7 +124842,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl_part_buf.DeviceIdSize), line:50:17, endln:50:29 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |UINT:32 |vpiTypespec: \_int_typespec: , line:50:13, endln:50:16 @@ -124858,7 +124858,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl_part_buf.FlashAddrKeySeedOffset), line:65:17, endln:65:39 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |UINT:1784 |vpiTypespec: \_int_typespec: , line:65:13, endln:65:16 @@ -124874,7 +124874,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl_part_buf.FlashAddrKeySeedSize), line:66:17, endln:66:37 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |UINT:32 |vpiTypespec: \_int_typespec: , line:66:13, endln:66:16 @@ -124890,7 +124890,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl_part_buf.FlashDataKeySeedOffset), line:67:17, endln:67:39 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |UINT:1816 |vpiTypespec: \_int_typespec: , line:67:13, endln:67:16 @@ -124906,7 +124906,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl_part_buf.FlashDataKeySeedSize), line:68:17, endln:68:37 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |UINT:32 |vpiTypespec: \_int_typespec: , line:68:13, endln:68:16 @@ -124922,7 +124922,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl_part_buf.HwCfgContentOffset), line:51:17, endln:51:35 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |UINT:1568 |vpiTypespec: \_int_typespec: , line:51:13, endln:51:16 @@ -124938,7 +124938,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl_part_buf.HwCfgContentSize), line:52:17, endln:52:33 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |UINT:168 |vpiTypespec: \_int_typespec: , line:52:13, endln:52:16 @@ -124954,7 +124954,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl_part_buf.HwCfgDigestOffset), line:53:17, endln:53:34 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |UINT:1736 |vpiTypespec: \_int_typespec: , line:53:13, endln:53:16 @@ -124970,7 +124970,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl_part_buf.HwCfgDigestSize), line:54:17, endln:54:32 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |UINT:8 |vpiTypespec: \_int_typespec: , line:54:13, endln:54:16 @@ -124986,7 +124986,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl_part_buf.HwCfgOffset), line:47:17, endln:47:28 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |UINT:1536 |vpiTypespec: \_int_typespec: , line:47:13, endln:47:16 @@ -125002,7 +125002,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl_part_buf.HwCfgSize), line:48:17, endln:48:26 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |UINT:208 |vpiTypespec: \_int_typespec: , line:48:13, endln:48:16 @@ -125018,7 +125018,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl_part_buf.LcStateOffset), line:85:17, endln:85:30 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |UINT:1992 |vpiTypespec: \_int_typespec: , line:85:13, endln:85:16 @@ -125034,7 +125034,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl_part_buf.LcStateSize), line:86:17, endln:86:28 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |UINT:24 |vpiTypespec: \_int_typespec: , line:86:13, endln:86:16 @@ -125050,7 +125050,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl_part_buf.LcTransitionCntOffset), line:87:17, endln:87:38 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |UINT:2016 |vpiTypespec: \_int_typespec: , line:87:13, endln:87:16 @@ -125066,7 +125066,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl_part_buf.LcTransitionCntSize), line:88:17, endln:88:36 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |UINT:32 |vpiTypespec: \_int_typespec: , line:88:13, endln:88:16 @@ -125082,7 +125082,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl_part_buf.LifeCycleOffset), line:83:17, endln:83:32 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |UINT:1992 |vpiTypespec: \_int_typespec: , line:83:13, endln:83:16 @@ -125098,7 +125098,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl_part_buf.LifeCycleSize), line:84:17, endln:84:30 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |UINT:56 |vpiTypespec: \_int_typespec: , line:84:13, endln:84:16 @@ -125114,7 +125114,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl_part_buf.NumAlerts), line:89:17, endln:89:26 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |UINT:2 |vpiTypespec: \_int_typespec: , line:89:13, endln:89:16 @@ -125130,7 +125130,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl_part_buf.NumDaiWords), line:30:17, endln:30:28 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |UINT:2 |vpiTypespec: \_int_typespec: , line:30:13, endln:30:16 @@ -125146,7 +125146,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl_part_buf.NumDebugWindowWords), line:33:17, endln:33:36 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |UINT:16 |vpiTypespec: \_int_typespec: , line:33:13, endln:33:16 @@ -125162,7 +125162,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl_part_buf.NumDigestWords), line:31:17, endln:31:31 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |UINT:2 |vpiTypespec: \_int_typespec: , line:31:13, endln:31:16 @@ -125178,7 +125178,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl_part_buf.NumErrorEntries), line:29:17, endln:29:32 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |UINT:9 |vpiTypespec: \_int_typespec: , line:29:13, endln:29:16 @@ -125194,7 +125194,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl_part_buf.NumPart), line:34:17, endln:34:24 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |UINT:7 |vpiTypespec: \_int_typespec: , line:34:13, endln:34:16 @@ -125210,7 +125210,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl_part_buf.NumSramKeyReqSlots), line:27:17, endln:27:35 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |UINT:2 |vpiTypespec: \_int_typespec: , line:27:13, endln:27:16 @@ -125226,7 +125226,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl_part_buf.NumSwCfgWindowWords), line:32:17, endln:32:36 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |UINT:512 |vpiTypespec: \_int_typespec: , line:32:13, endln:32:16 @@ -125242,7 +125242,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl_part_buf.OTP_CTRL_ALERT_TEST_OFFSET), line:325:26, endln:325:52 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |HEX:c |vpiTypespec: \_logic_typespec: , line:325:13, endln:325:25 @@ -125276,7 +125276,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl_part_buf.OTP_CTRL_CHECK_REGWEN_OFFSET), line:337:26, endln:337:54 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |HEX:3c |vpiTypespec: \_logic_typespec: , line:337:13, endln:337:25 @@ -125310,7 +125310,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl_part_buf.OTP_CTRL_CHECK_TIMEOUT_OFFSET), line:338:26, endln:338:55 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |HEX:40 |vpiTypespec: \_logic_typespec: , line:338:13, endln:338:25 @@ -125344,7 +125344,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl_part_buf.OTP_CTRL_CHECK_TRIGGER_OFFSET), line:336:26, endln:336:55 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |HEX:38 |vpiTypespec: \_logic_typespec: , line:336:13, endln:336:25 @@ -125378,7 +125378,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl_part_buf.OTP_CTRL_CHECK_TRIGGER_REGWEN_OFFSET), line:335:26, endln:335:62 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |HEX:34 |vpiTypespec: \_logic_typespec: , line:335:13, endln:335:25 @@ -125412,7 +125412,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl_part_buf.OTP_CTRL_CONSISTENCY_CHECK_PERIOD_OFFSET), line:340:26, endln:340:66 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |HEX:48 |vpiTypespec: \_logic_typespec: , line:340:13, endln:340:25 @@ -125446,7 +125446,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl_part_buf.OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_OFFSET), line:343:26, endln:343:65 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |HEX:54 |vpiTypespec: \_logic_typespec: , line:343:13, endln:343:25 @@ -125480,7 +125480,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl_part_buf.OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_OFFSET), line:344:26, endln:344:65 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |HEX:58 |vpiTypespec: \_logic_typespec: , line:344:13, endln:344:25 @@ -125514,7 +125514,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl_part_buf.OTP_CTRL_CREATOR_SW_CFG_READ_LOCK_OFFSET), line:341:26, endln:341:66 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |HEX:4c |vpiTypespec: \_logic_typespec: , line:341:13, endln:341:25 @@ -125548,7 +125548,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl_part_buf.OTP_CTRL_DIRECT_ACCESS_ADDRESS_OFFSET), line:330:26, endln:330:63 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |HEX:20 |vpiTypespec: \_logic_typespec: , line:330:13, endln:330:25 @@ -125582,7 +125582,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl_part_buf.OTP_CTRL_DIRECT_ACCESS_CMD_OFFSET), line:329:26, endln:329:59 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |HEX:1c |vpiTypespec: \_logic_typespec: , line:329:13, endln:329:25 @@ -125616,7 +125616,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl_part_buf.OTP_CTRL_DIRECT_ACCESS_RDATA_0_OFFSET), line:333:26, endln:333:63 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |HEX:2c |vpiTypespec: \_logic_typespec: , line:333:13, endln:333:25 @@ -125650,7 +125650,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl_part_buf.OTP_CTRL_DIRECT_ACCESS_RDATA_1_OFFSET), line:334:26, endln:334:63 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |HEX:30 |vpiTypespec: \_logic_typespec: , line:334:13, endln:334:25 @@ -125684,7 +125684,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl_part_buf.OTP_CTRL_DIRECT_ACCESS_REGWEN_OFFSET), line:328:26, endln:328:62 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |HEX:18 |vpiTypespec: \_logic_typespec: , line:328:13, endln:328:25 @@ -125718,7 +125718,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl_part_buf.OTP_CTRL_DIRECT_ACCESS_WDATA_0_OFFSET), line:331:26, endln:331:63 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |HEX:24 |vpiTypespec: \_logic_typespec: , line:331:13, endln:331:25 @@ -125752,7 +125752,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl_part_buf.OTP_CTRL_DIRECT_ACCESS_WDATA_1_OFFSET), line:332:26, endln:332:63 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |HEX:28 |vpiTypespec: \_logic_typespec: , line:332:13, endln:332:25 @@ -125786,7 +125786,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl_part_buf.OTP_CTRL_ERR_CODE_OFFSET), line:327:26, endln:327:50 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |HEX:14 |vpiTypespec: \_logic_typespec: , line:327:13, endln:327:25 @@ -125820,7 +125820,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl_part_buf.OTP_CTRL_HW_CFG_DIGEST_0_OFFSET), line:347:26, endln:347:57 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |HEX:64 |vpiTypespec: \_logic_typespec: , line:347:13, endln:347:25 @@ -125854,7 +125854,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl_part_buf.OTP_CTRL_HW_CFG_DIGEST_1_OFFSET), line:348:26, endln:348:57 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |HEX:68 |vpiTypespec: \_logic_typespec: , line:348:13, endln:348:25 @@ -125888,7 +125888,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl_part_buf.OTP_CTRL_INTEGRITY_CHECK_PERIOD_OFFSET), line:339:26, endln:339:64 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |HEX:44 |vpiTypespec: \_logic_typespec: , line:339:13, endln:339:25 @@ -125922,7 +125922,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl_part_buf.OTP_CTRL_INTR_ENABLE_OFFSET), line:323:26, endln:323:53 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |HEX:4 |vpiTypespec: \_logic_typespec: , line:323:13, endln:323:25 @@ -125956,7 +125956,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl_part_buf.OTP_CTRL_INTR_STATE_OFFSET), line:322:26, endln:322:52 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |HEX:0 |vpiTypespec: \_logic_typespec: , line:322:13, endln:322:25 @@ -125990,7 +125990,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl_part_buf.OTP_CTRL_INTR_TEST_OFFSET), line:324:26, endln:324:51 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |HEX:8 |vpiTypespec: \_logic_typespec: , line:324:13, endln:324:25 @@ -126024,7 +126024,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl_part_buf.OTP_CTRL_OWNER_SW_CFG_DIGEST_0_OFFSET), line:345:26, endln:345:63 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |HEX:5c |vpiTypespec: \_logic_typespec: , line:345:13, endln:345:25 @@ -126058,7 +126058,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl_part_buf.OTP_CTRL_OWNER_SW_CFG_DIGEST_1_OFFSET), line:346:26, endln:346:63 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |HEX:60 |vpiTypespec: \_logic_typespec: , line:346:13, endln:346:25 @@ -126092,7 +126092,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl_part_buf.OTP_CTRL_OWNER_SW_CFG_READ_LOCK_OFFSET), line:342:26, endln:342:64 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |HEX:50 |vpiTypespec: \_logic_typespec: , line:342:13, endln:342:25 @@ -126126,7 +126126,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl_part_buf.OTP_CTRL_PERMIT), line:400:25, endln:400:40 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiSize:33 |vpiTypespec: \_array_typespec: @@ -126228,7 +126228,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl_part_buf.OTP_CTRL_SECRET0_DIGEST_0_OFFSET), line:349:26, endln:349:58 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |HEX:6c |vpiTypespec: \_logic_typespec: , line:349:13, endln:349:25 @@ -126262,7 +126262,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl_part_buf.OTP_CTRL_SECRET0_DIGEST_1_OFFSET), line:350:26, endln:350:58 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |HEX:70 |vpiTypespec: \_logic_typespec: , line:350:13, endln:350:25 @@ -126296,7 +126296,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl_part_buf.OTP_CTRL_SECRET1_DIGEST_0_OFFSET), line:351:26, endln:351:58 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |HEX:74 |vpiTypespec: \_logic_typespec: , line:351:13, endln:351:25 @@ -126330,7 +126330,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl_part_buf.OTP_CTRL_SECRET1_DIGEST_1_OFFSET), line:352:26, endln:352:58 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |HEX:78 |vpiTypespec: \_logic_typespec: , line:352:13, endln:352:25 @@ -126364,7 +126364,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl_part_buf.OTP_CTRL_SECRET2_DIGEST_0_OFFSET), line:353:26, endln:353:58 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |HEX:7c |vpiTypespec: \_logic_typespec: , line:353:13, endln:353:25 @@ -126398,7 +126398,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl_part_buf.OTP_CTRL_SECRET2_DIGEST_1_OFFSET), line:354:26, endln:354:58 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |HEX:80 |vpiTypespec: \_logic_typespec: , line:354:13, endln:354:25 @@ -126432,7 +126432,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl_part_buf.OTP_CTRL_STATUS_OFFSET), line:326:26, endln:326:48 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |HEX:10 |vpiTypespec: \_logic_typespec: , line:326:13, endln:326:25 @@ -126466,7 +126466,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl_part_buf.OTP_CTRL_SW_CFG_WINDOW_OFFSET), line:357:26, endln:357:55 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |HEX:1000 |vpiTypespec: \_logic_typespec: , line:357:13, endln:357:25 @@ -126500,7 +126500,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl_part_buf.OTP_CTRL_SW_CFG_WINDOW_SIZE), line:358:26, endln:358:53 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |HEX:800 |vpiTypespec: \_logic_typespec: , line:358:13, endln:358:25 @@ -126534,7 +126534,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl_part_buf.OTP_CTRL_TEST_ACCESS_OFFSET), line:359:26, endln:359:53 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |HEX:2000 |vpiTypespec: \_logic_typespec: , line:359:13, endln:359:25 @@ -126568,7 +126568,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl_part_buf.OTP_CTRL_TEST_ACCESS_SIZE), line:360:26, endln:360:51 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |HEX:40 |vpiTypespec: \_logic_typespec: , line:360:13, endln:360:25 @@ -126602,7 +126602,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl_part_buf.OtpByteAddrWidth), line:28:17, endln:28:33 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |UINT:11 |vpiTypespec: \_int_typespec: , line:28:13, endln:28:16 @@ -126618,7 +126618,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl_part_buf.OwnerSwCfgContentOffset), line:43:17, endln:43:40 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |UINT:768 |vpiTypespec: \_int_typespec: , line:43:13, endln:43:16 @@ -126634,7 +126634,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl_part_buf.OwnerSwCfgContentSize), line:44:17, endln:44:38 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |UINT:760 |vpiTypespec: \_int_typespec: , line:44:13, endln:44:16 @@ -126650,7 +126650,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl_part_buf.OwnerSwCfgDigestOffset), line:45:17, endln:45:39 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |UINT:1528 |vpiTypespec: \_int_typespec: , line:45:13, endln:45:16 @@ -126666,7 +126666,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl_part_buf.OwnerSwCfgDigestSize), line:46:17, endln:46:37 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |UINT:8 |vpiTypespec: \_int_typespec: , line:46:13, endln:46:16 @@ -126682,7 +126682,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl_part_buf.OwnerSwCfgOffset), line:41:17, endln:41:33 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |UINT:768 |vpiTypespec: \_int_typespec: , line:41:13, endln:41:16 @@ -126698,7 +126698,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl_part_buf.OwnerSwCfgSize), line:42:17, endln:42:31 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |UINT:768 |vpiTypespec: \_int_typespec: , line:42:13, endln:42:16 @@ -126714,7 +126714,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl_part_buf.RmaTokenOffset), line:75:17, endln:75:31 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |UINT:1872 |vpiTypespec: \_int_typespec: , line:75:13, endln:75:16 @@ -126730,7 +126730,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl_part_buf.RmaTokenSize), line:76:17, endln:76:29 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |UINT:16 |vpiTypespec: \_int_typespec: , line:76:13, endln:76:16 @@ -126746,7 +126746,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl_part_buf.Secret0DigestOffset), line:61:17, endln:61:36 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |UINT:1776 |vpiTypespec: \_int_typespec: , line:61:13, endln:61:16 @@ -126762,7 +126762,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl_part_buf.Secret0DigestSize), line:62:17, endln:62:34 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |UINT:8 |vpiTypespec: \_int_typespec: , line:62:13, endln:62:16 @@ -126778,7 +126778,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl_part_buf.Secret0Offset), line:55:17, endln:55:30 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |UINT:1744 |vpiTypespec: \_int_typespec: , line:55:13, endln:55:16 @@ -126794,7 +126794,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl_part_buf.Secret0Size), line:56:17, endln:56:28 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |UINT:40 |vpiTypespec: \_int_typespec: , line:56:13, endln:56:16 @@ -126810,7 +126810,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl_part_buf.Secret1DigestOffset), line:71:17, endln:71:36 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |UINT:1864 |vpiTypespec: \_int_typespec: , line:71:13, endln:71:16 @@ -126826,7 +126826,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl_part_buf.Secret1DigestSize), line:72:17, endln:72:34 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |UINT:8 |vpiTypespec: \_int_typespec: , line:72:13, endln:72:16 @@ -126842,7 +126842,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl_part_buf.Secret1Offset), line:63:17, endln:63:30 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |UINT:1784 |vpiTypespec: \_int_typespec: , line:63:13, endln:63:16 @@ -126858,7 +126858,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl_part_buf.Secret1Size), line:64:17, endln:64:28 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |UINT:88 |vpiTypespec: \_int_typespec: , line:64:13, endln:64:16 @@ -126874,7 +126874,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl_part_buf.Secret2DigestOffset), line:81:17, endln:81:36 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |UINT:1984 |vpiTypespec: \_int_typespec: , line:81:13, endln:81:16 @@ -126890,7 +126890,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl_part_buf.Secret2DigestSize), line:82:17, endln:82:34 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |UINT:8 |vpiTypespec: \_int_typespec: , line:82:13, endln:82:16 @@ -126906,7 +126906,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl_part_buf.Secret2Offset), line:73:17, endln:73:30 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |UINT:1872 |vpiTypespec: \_int_typespec: , line:73:13, endln:73:16 @@ -126922,7 +126922,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl_part_buf.Secret2Size), line:74:17, endln:74:28 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |UINT:120 |vpiTypespec: \_int_typespec: , line:74:13, endln:74:16 @@ -126938,7 +126938,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl_part_buf.SramDataKeySeedOffset), line:69:17, endln:69:38 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |UINT:1848 |vpiTypespec: \_int_typespec: , line:69:13, endln:69:16 @@ -126954,7 +126954,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl_part_buf.SramDataKeySeedSize), line:70:17, endln:70:36 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |UINT:16 |vpiTypespec: \_int_typespec: , line:70:13, endln:70:16 @@ -126970,7 +126970,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl_part_buf.TestExitTokenOffset), line:59:17, endln:59:36 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |UINT:1760 |vpiTypespec: \_int_typespec: , line:59:13, endln:59:16 @@ -126986,7 +126986,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl_part_buf.TestExitTokenSize), line:60:17, endln:60:34 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |UINT:16 |vpiTypespec: \_int_typespec: , line:60:13, endln:60:16 @@ -127002,7 +127002,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl_part_buf.TestUnlockTokenOffset), line:57:17, endln:57:38 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |UINT:1744 |vpiTypespec: \_int_typespec: , line:57:13, endln:57:16 @@ -127018,7 +127018,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl_part_buf.TestUnlockTokenSize), line:58:17, endln:58:36 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |UINT:16 |vpiTypespec: \_int_typespec: , line:58:13, endln:58:16 @@ -127034,7 +127034,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl_part_buf.Info), line:774:37, endln:774:41 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiTypespec: \_struct_typespec: (otp_ctrl_pkg::part_info_t), line:555:11, endln:555:17 |vpiName:Info @@ -127042,7 +127042,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl_part_buf.DigestOffset), line:786:18, endln:786:30 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiTypespec: \_int_typespec: , line:786:14, endln:786:17 |vpiParent: @@ -127055,7 +127055,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:27:17, endln:27:39 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiRhs: \_constant: , line:27:38, endln:27:39 |vpiParent: @@ -127090,7 +127090,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:28:17, endln:28:38 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiRhs: \_constant: , line:28:36, endln:28:38 |vpiParent: @@ -127125,7 +127125,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:29:17, endln:29:36 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiRhs: \_constant: , line:29:35, endln:29:36 |vpiParent: @@ -127160,7 +127160,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:30:17, endln:30:32 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiRhs: \_constant: , line:30:31, endln:30:32 |vpiParent: @@ -127195,7 +127195,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:31:17, endln:31:35 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiRhs: \_constant: , line:31:34, endln:31:35 |vpiParent: @@ -127230,7 +127230,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:32:17, endln:32:42 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiRhs: \_constant: , line:32:39, endln:32:42 |vpiParent: @@ -127265,7 +127265,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:33:17, endln:33:41 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiRhs: \_constant: , line:33:39, endln:33:41 |vpiParent: @@ -127300,7 +127300,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:34:17, endln:34:28 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiRhs: \_constant: , line:34:27, endln:34:28 |vpiParent: @@ -127335,7 +127335,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:35:17, endln:35:39 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiRhs: \_constant: , line:35:38, endln:35:39 |vpiParent: @@ -127370,7 +127370,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:36:17, endln:36:39 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiRhs: \_constant: , line:36:36, endln:36:39 |vpiParent: @@ -127405,7 +127405,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:37:17, endln:37:46 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiRhs: \_constant: , line:37:45, endln:37:46 |vpiParent: @@ -127440,7 +127440,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:38:17, endln:38:46 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiRhs: \_constant: , line:38:43, endln:38:46 |vpiParent: @@ -127475,7 +127475,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:39:17, endln:39:47 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiRhs: \_constant: , line:39:44, endln:39:47 |vpiParent: @@ -127510,7 +127510,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:40:17, endln:40:43 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiRhs: \_constant: , line:40:42, endln:40:43 |vpiParent: @@ -127545,7 +127545,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:41:17, endln:41:39 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiRhs: \_constant: , line:41:36, endln:41:39 |vpiParent: @@ -127580,7 +127580,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:42:17, endln:42:37 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiRhs: \_constant: , line:42:34, endln:42:37 |vpiParent: @@ -127615,7 +127615,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:43:17, endln:43:46 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiRhs: \_constant: , line:43:43, endln:43:46 |vpiParent: @@ -127650,7 +127650,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:44:17, endln:44:44 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiRhs: \_constant: , line:44:41, endln:44:44 |vpiParent: @@ -127685,7 +127685,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:45:17, endln:45:46 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiRhs: \_constant: , line:45:42, endln:45:46 |vpiParent: @@ -127720,7 +127720,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:46:17, endln:46:41 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiRhs: \_constant: , line:46:40, endln:46:41 |vpiParent: @@ -127755,7 +127755,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:47:17, endln:47:35 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiRhs: \_constant: , line:47:31, endln:47:35 |vpiParent: @@ -127790,7 +127790,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:48:17, endln:48:32 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiRhs: \_constant: , line:48:29, endln:48:32 |vpiParent: @@ -127825,7 +127825,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:49:17, endln:49:38 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiRhs: \_constant: , line:49:34, endln:49:38 |vpiParent: @@ -127860,7 +127860,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:50:17, endln:50:34 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiRhs: \_constant: , line:50:32, endln:50:34 |vpiParent: @@ -127895,7 +127895,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:51:17, endln:51:42 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiRhs: \_constant: , line:51:38, endln:51:42 |vpiParent: @@ -127930,7 +127930,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:52:17, endln:52:39 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiRhs: \_constant: , line:52:36, endln:52:39 |vpiParent: @@ -127965,7 +127965,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:53:17, endln:53:41 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiRhs: \_constant: , line:53:37, endln:53:41 |vpiParent: @@ -128000,7 +128000,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:54:17, endln:54:36 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiRhs: \_constant: , line:54:35, endln:54:36 |vpiParent: @@ -128035,7 +128035,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:55:17, endln:55:37 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiRhs: \_constant: , line:55:33, endln:55:37 |vpiParent: @@ -128070,7 +128070,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:56:17, endln:56:33 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiRhs: \_constant: , line:56:31, endln:56:33 |vpiParent: @@ -128105,7 +128105,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:57:17, endln:57:45 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiRhs: \_constant: , line:57:41, endln:57:45 |vpiParent: @@ -128140,7 +128140,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:58:17, endln:58:41 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiRhs: \_constant: , line:58:39, endln:58:41 |vpiParent: @@ -128175,7 +128175,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:59:17, endln:59:43 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiRhs: \_constant: , line:59:39, endln:59:43 |vpiParent: @@ -128210,7 +128210,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:60:17, endln:60:39 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiRhs: \_constant: , line:60:37, endln:60:39 |vpiParent: @@ -128245,7 +128245,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:61:17, endln:61:43 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiRhs: \_constant: , line:61:39, endln:61:43 |vpiParent: @@ -128280,7 +128280,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:62:17, endln:62:38 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiRhs: \_constant: , line:62:37, endln:62:38 |vpiParent: @@ -128315,7 +128315,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:63:17, endln:63:37 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiRhs: \_constant: , line:63:33, endln:63:37 |vpiParent: @@ -128350,7 +128350,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:64:17, endln:64:33 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiRhs: \_constant: , line:64:31, endln:64:33 |vpiParent: @@ -128385,7 +128385,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:65:17, endln:65:46 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiRhs: \_constant: , line:65:42, endln:65:46 |vpiParent: @@ -128420,7 +128420,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:66:17, endln:66:42 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiRhs: \_constant: , line:66:40, endln:66:42 |vpiParent: @@ -128455,7 +128455,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:67:17, endln:67:46 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiRhs: \_constant: , line:67:42, endln:67:46 |vpiParent: @@ -128490,7 +128490,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:68:17, endln:68:42 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiRhs: \_constant: , line:68:40, endln:68:42 |vpiParent: @@ -128525,7 +128525,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:69:17, endln:69:45 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiRhs: \_constant: , line:69:41, endln:69:45 |vpiParent: @@ -128560,7 +128560,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:70:17, endln:70:41 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiRhs: \_constant: , line:70:39, endln:70:41 |vpiParent: @@ -128595,7 +128595,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:71:17, endln:71:43 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiRhs: \_constant: , line:71:39, endln:71:43 |vpiParent: @@ -128630,7 +128630,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:72:17, endln:72:38 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiRhs: \_constant: , line:72:37, endln:72:38 |vpiParent: @@ -128665,7 +128665,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:73:17, endln:73:37 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiRhs: \_constant: , line:73:33, endln:73:37 |vpiParent: @@ -128700,7 +128700,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:74:17, endln:74:34 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiRhs: \_constant: , line:74:31, endln:74:34 |vpiParent: @@ -128735,7 +128735,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:75:17, endln:75:38 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiRhs: \_constant: , line:75:34, endln:75:38 |vpiParent: @@ -128770,7 +128770,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:76:17, endln:76:34 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiRhs: \_constant: , line:76:32, endln:76:34 |vpiParent: @@ -128805,7 +128805,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:77:17, endln:77:50 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiRhs: \_constant: , line:77:46, endln:77:50 |vpiParent: @@ -128840,7 +128840,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:78:17, endln:78:46 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiRhs: \_constant: , line:78:44, endln:78:46 |vpiParent: @@ -128875,7 +128875,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:79:17, endln:79:50 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiRhs: \_constant: , line:79:46, endln:79:50 |vpiParent: @@ -128910,7 +128910,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:80:17, endln:80:46 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiRhs: \_constant: , line:80:44, endln:80:46 |vpiParent: @@ -128945,7 +128945,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:81:17, endln:81:43 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiRhs: \_constant: , line:81:39, endln:81:43 |vpiParent: @@ -128980,7 +128980,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:82:17, endln:82:38 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiRhs: \_constant: , line:82:37, endln:82:38 |vpiParent: @@ -129015,7 +129015,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:83:17, endln:83:39 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiRhs: \_constant: , line:83:35, endln:83:39 |vpiParent: @@ -129050,7 +129050,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:84:17, endln:84:35 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiRhs: \_constant: , line:84:33, endln:84:35 |vpiParent: @@ -129085,7 +129085,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:85:17, endln:85:37 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiRhs: \_constant: , line:85:33, endln:85:37 |vpiParent: @@ -129120,7 +129120,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:86:17, endln:86:33 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiRhs: \_constant: , line:86:31, endln:86:33 |vpiParent: @@ -129155,7 +129155,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:87:17, endln:87:45 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiRhs: \_constant: , line:87:41, endln:87:45 |vpiParent: @@ -129190,7 +129190,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:88:17, endln:88:41 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiRhs: \_constant: , line:88:39, endln:88:41 |vpiParent: @@ -129225,7 +129225,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:89:17, endln:89:30 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiRhs: \_constant: , line:89:29, endln:89:30 |vpiParent: @@ -129260,7 +129260,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:322:26, endln:322:60 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiRhs: \_constant: , line:322:55, endln:322:60 |vpiParent: @@ -129332,7 +129332,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:323:26, endln:323:61 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiRhs: \_constant: , line:323:56, endln:323:61 |vpiParent: @@ -129404,7 +129404,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:324:26, endln:324:59 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiRhs: \_constant: , line:324:54, endln:324:59 |vpiParent: @@ -129476,7 +129476,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:325:26, endln:325:60 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiRhs: \_constant: , line:325:55, endln:325:60 |vpiParent: @@ -129548,7 +129548,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:326:26, endln:326:57 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiRhs: \_constant: , line:326:51, endln:326:57 |vpiParent: @@ -129620,7 +129620,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:327:26, endln:327:59 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiRhs: \_constant: , line:327:53, endln:327:59 |vpiParent: @@ -129692,7 +129692,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:328:26, endln:328:71 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiRhs: \_constant: , line:328:65, endln:328:71 |vpiParent: @@ -129764,7 +129764,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:329:26, endln:329:68 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiRhs: \_constant: , line:329:62, endln:329:68 |vpiParent: @@ -129836,7 +129836,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:330:26, endln:330:72 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiRhs: \_constant: , line:330:66, endln:330:72 |vpiParent: @@ -129908,7 +129908,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:331:26, endln:331:72 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiRhs: \_constant: , line:331:66, endln:331:72 |vpiParent: @@ -129980,7 +129980,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:332:26, endln:332:72 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiRhs: \_constant: , line:332:66, endln:332:72 |vpiParent: @@ -130052,7 +130052,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:333:26, endln:333:72 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiRhs: \_constant: , line:333:66, endln:333:72 |vpiParent: @@ -130124,7 +130124,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:334:26, endln:334:72 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiRhs: \_constant: , line:334:66, endln:334:72 |vpiParent: @@ -130196,7 +130196,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:335:26, endln:335:71 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiRhs: \_constant: , line:335:65, endln:335:71 |vpiParent: @@ -130268,7 +130268,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:336:26, endln:336:64 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiRhs: \_constant: , line:336:58, endln:336:64 |vpiParent: @@ -130340,7 +130340,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:337:26, endln:337:63 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiRhs: \_constant: , line:337:57, endln:337:63 |vpiParent: @@ -130412,7 +130412,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:338:26, endln:338:64 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiRhs: \_constant: , line:338:58, endln:338:64 |vpiParent: @@ -130484,7 +130484,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:339:26, endln:339:73 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiRhs: \_constant: , line:339:67, endln:339:73 |vpiParent: @@ -130556,7 +130556,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:340:26, endln:340:75 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiRhs: \_constant: , line:340:69, endln:340:75 |vpiParent: @@ -130628,7 +130628,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:341:26, endln:341:75 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiRhs: \_constant: , line:341:69, endln:341:75 |vpiParent: @@ -130700,7 +130700,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:342:26, endln:342:73 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiRhs: \_constant: , line:342:67, endln:342:73 |vpiParent: @@ -130772,7 +130772,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:343:26, endln:343:74 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiRhs: \_constant: , line:343:68, endln:343:74 |vpiParent: @@ -130844,7 +130844,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:344:26, endln:344:74 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiRhs: \_constant: , line:344:68, endln:344:74 |vpiParent: @@ -130916,7 +130916,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:345:26, endln:345:72 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiRhs: \_constant: , line:345:66, endln:345:72 |vpiParent: @@ -130988,7 +130988,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:346:26, endln:346:72 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiRhs: \_constant: , line:346:66, endln:346:72 |vpiParent: @@ -131060,7 +131060,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:347:26, endln:347:66 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiRhs: \_constant: , line:347:60, endln:347:66 |vpiParent: @@ -131132,7 +131132,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:348:26, endln:348:66 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiRhs: \_constant: , line:348:60, endln:348:66 |vpiParent: @@ -131204,7 +131204,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:349:26, endln:349:67 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiRhs: \_constant: , line:349:61, endln:349:67 |vpiParent: @@ -131276,7 +131276,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:350:26, endln:350:67 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiRhs: \_constant: , line:350:61, endln:350:67 |vpiParent: @@ -131348,7 +131348,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:351:26, endln:351:67 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiRhs: \_constant: , line:351:61, endln:351:67 |vpiParent: @@ -131420,7 +131420,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:352:26, endln:352:67 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiRhs: \_constant: , line:352:61, endln:352:67 |vpiParent: @@ -131492,7 +131492,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:353:26, endln:353:67 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiRhs: \_constant: , line:353:61, endln:353:67 |vpiParent: @@ -131564,7 +131564,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:354:26, endln:354:67 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiRhs: \_constant: , line:354:61, endln:354:67 |vpiParent: @@ -131636,7 +131636,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:357:26, endln:357:66 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiRhs: \_constant: , line:357:58, endln:357:66 |vpiParent: @@ -131708,7 +131708,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:358:26, endln:358:65 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiRhs: \_constant: , line:358:58, endln:358:65 |vpiParent: @@ -131780,7 +131780,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:359:26, endln:359:64 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiRhs: \_constant: , line:359:56, endln:359:64 |vpiParent: @@ -131852,7 +131852,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:360:26, endln:360:62 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiRhs: \_constant: , line:360:56, endln:360:62 |vpiParent: @@ -131924,7 +131924,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:400:25, endln:434:4 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiRhs: \_operation: , line:400:48, endln:434:4 |vpiParent: @@ -132299,7 +132299,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:448:17, endln:448:34 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiRhs: \_constant: , line:448:32, endln:448:34 |vpiParent: @@ -132334,7 +132334,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:450:17, endln:450:46 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiRhs: \_constant: , line:450:32, endln:450:46 |vpiParent: @@ -132369,7 +132369,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:452:17, endln:452:63 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiRhs: \_constant: , line:452:37, endln:452:63 |vpiParent: @@ -132404,7 +132404,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:468:17, endln:468:32 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiRhs: \_constant: , line:468:31, endln:468:32 |vpiParent: @@ -132439,7 +132439,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:480:17, endln:480:38 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiRhs: \_constant: , line:480:36, endln:480:38 |vpiParent: @@ -132474,7 +132474,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:481:17, endln:481:73 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiRhs: \_constant: , line:481:36, endln:481:52 |vpiParent: @@ -132509,7 +132509,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:482:17, endln:482:51 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiRhs: \_constant: , line:482:36, endln:482:37 |vpiParent: @@ -132544,7 +132544,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:483:17, endln:483:37 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiRhs: \_constant: , line:483:36, endln:483:37 |vpiParent: @@ -132579,7 +132579,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:484:17, endln:484:37 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiRhs: \_constant: , line:484:36, endln:484:37 |vpiParent: @@ -132614,7 +132614,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:485:17, endln:485:37 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiRhs: \_constant: , line:485:36, endln:485:37 |vpiParent: @@ -132649,7 +132649,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:486:17, endln:486:60 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiRhs: \_constant: , line:486:36, endln:486:51 |vpiParent: @@ -132684,7 +132684,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:488:17, endln:488:67 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiRhs: \_constant: , line:488:36, endln:488:52 |vpiParent: @@ -132719,7 +132719,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:505:17, endln:505:39 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiRhs: \_constant: , line:505:36, endln:505:39 |vpiParent: @@ -132754,7 +132754,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:506:17, endln:506:38 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiRhs: \_constant: , line:506:36, endln:506:38 |vpiParent: @@ -132789,7 +132789,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:508:17, endln:508:38 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiRhs: \_constant: , line:508:36, endln:508:38 |vpiParent: @@ -132824,7 +132824,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:509:17, endln:509:67 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiRhs: \_constant: , line:509:40, endln:509:56 |vpiParent: @@ -132859,7 +132859,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:520:17, endln:520:34 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiRhs: \_constant: , line:520:33, endln:520:34 |vpiParent: @@ -132894,7 +132894,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:521:17, endln:521:34 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiRhs: \_constant: , line:521:33, endln:521:34 |vpiParent: @@ -132929,7 +132929,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:522:17, endln:524:53 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiRhs: \_constant: , line:522:33, endln:522:64 |vpiParent: @@ -132964,7 +132964,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:587:27, endln:597:4 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiRhs: \_operation: , line:587:49, endln:597:4 |vpiParent: @@ -133293,7 +133293,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:625:17, endln:625:40 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiRhs: \_constant: , line:625:37, endln:625:40 |vpiParent: @@ -133328,7 +133328,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:626:17, endln:626:40 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiRhs: \_constant: , line:626:37, endln:626:40 |vpiParent: @@ -133363,7 +133363,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:627:17, endln:627:39 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiRhs: \_constant: , line:627:36, endln:627:39 |vpiParent: @@ -133398,7 +133398,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:628:17, endln:628:39 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiRhs: \_constant: , line:628:36, endln:628:39 |vpiParent: @@ -133433,7 +133433,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:629:17, endln:629:39 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiRhs: \_constant: , line:629:36, endln:629:39 |vpiParent: @@ -133468,7 +133468,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:630:17, endln:630:38 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiRhs: \_constant: , line:630:36, endln:630:38 |vpiParent: @@ -133503,7 +133503,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:631:17, endln:631:39 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiRhs: \_constant: , line:631:36, endln:631:39 |vpiParent: @@ -133538,7 +133538,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:632:17, endln:632:39 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiRhs: \_constant: , line:632:36, endln:632:39 |vpiParent: @@ -133573,7 +133573,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:645:30, endln:649:4 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiRhs: \_operation: , line:645:55, endln:649:4 |vpiParent: @@ -133736,7 +133736,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:672:33, endln:677:4 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiRhs: \_operation: , line:672:61, endln:677:4 |vpiParent: @@ -133912,7 +133912,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:728:18, endln:728:32 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiRhs: \_constant: , line:728:30, endln:728:32 |vpiParent: @@ -133948,7 +133948,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:731:26, endln:731:65 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiRhs: \_constant: , line:731:51, endln:731:65 |vpiParent: @@ -134077,7 +134077,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:732:26, endln:733:72 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiRhs: \_constant: , line:733:7, endln:733:72 |vpiParent: @@ -134286,7 +134286,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:737:25, endln:741:4 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiRhs: \_operation: , line:737:45, endln:741:4 |vpiParent: @@ -134420,7 +134420,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:746:34, endln:752:4 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiRhs: \_operation: , line:746:62, endln:752:4 |vpiParent: @@ -134570,7 +134570,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:755:31, endln:761:4 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiRhs: \_operation: , line:755:56, endln:761:4 |vpiParent: @@ -134720,7 +134720,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:763:37, endln:764:42 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiRhs: \_constant: , line:764:5, endln:764:42 |vpiParent: @@ -134754,7 +134754,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:27:17, endln:27:39 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiRhs: \_constant: , line:27:38, endln:27:39 |vpiParent: @@ -134789,7 +134789,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:28:17, endln:28:38 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiRhs: \_constant: , line:28:36, endln:28:38 |vpiParent: @@ -134824,7 +134824,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:29:17, endln:29:36 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiRhs: \_constant: , line:29:35, endln:29:36 |vpiParent: @@ -134859,7 +134859,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:30:17, endln:30:32 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiRhs: \_constant: , line:30:31, endln:30:32 |vpiParent: @@ -134894,7 +134894,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:31:17, endln:31:35 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiRhs: \_constant: , line:31:34, endln:31:35 |vpiParent: @@ -134929,7 +134929,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:32:17, endln:32:42 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiRhs: \_constant: , line:32:39, endln:32:42 |vpiParent: @@ -134964,7 +134964,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:33:17, endln:33:41 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiRhs: \_constant: , line:33:39, endln:33:41 |vpiParent: @@ -134999,7 +134999,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:34:17, endln:34:28 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiRhs: \_constant: , line:34:27, endln:34:28 |vpiParent: @@ -135034,7 +135034,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:35:17, endln:35:39 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiRhs: \_constant: , line:35:38, endln:35:39 |vpiParent: @@ -135069,7 +135069,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:36:17, endln:36:39 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiRhs: \_constant: , line:36:36, endln:36:39 |vpiParent: @@ -135104,7 +135104,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:37:17, endln:37:46 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiRhs: \_constant: , line:37:45, endln:37:46 |vpiParent: @@ -135139,7 +135139,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:38:17, endln:38:46 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiRhs: \_constant: , line:38:43, endln:38:46 |vpiParent: @@ -135174,7 +135174,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:39:17, endln:39:47 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiRhs: \_constant: , line:39:44, endln:39:47 |vpiParent: @@ -135209,7 +135209,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:40:17, endln:40:43 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiRhs: \_constant: , line:40:42, endln:40:43 |vpiParent: @@ -135244,7 +135244,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:41:17, endln:41:39 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiRhs: \_constant: , line:41:36, endln:41:39 |vpiParent: @@ -135279,7 +135279,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:42:17, endln:42:37 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiRhs: \_constant: , line:42:34, endln:42:37 |vpiParent: @@ -135314,7 +135314,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:43:17, endln:43:46 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiRhs: \_constant: , line:43:43, endln:43:46 |vpiParent: @@ -135349,7 +135349,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:44:17, endln:44:44 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiRhs: \_constant: , line:44:41, endln:44:44 |vpiParent: @@ -135384,7 +135384,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:45:17, endln:45:46 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiRhs: \_constant: , line:45:42, endln:45:46 |vpiParent: @@ -135419,7 +135419,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:46:17, endln:46:41 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiRhs: \_constant: , line:46:40, endln:46:41 |vpiParent: @@ -135454,7 +135454,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:47:17, endln:47:35 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiRhs: \_constant: , line:47:31, endln:47:35 |vpiParent: @@ -135489,7 +135489,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:48:17, endln:48:32 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiRhs: \_constant: , line:48:29, endln:48:32 |vpiParent: @@ -135524,7 +135524,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:49:17, endln:49:38 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiRhs: \_constant: , line:49:34, endln:49:38 |vpiParent: @@ -135559,7 +135559,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:50:17, endln:50:34 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiRhs: \_constant: , line:50:32, endln:50:34 |vpiParent: @@ -135594,7 +135594,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:51:17, endln:51:42 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiRhs: \_constant: , line:51:38, endln:51:42 |vpiParent: @@ -135629,7 +135629,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:52:17, endln:52:39 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiRhs: \_constant: , line:52:36, endln:52:39 |vpiParent: @@ -135664,7 +135664,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:53:17, endln:53:41 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiRhs: \_constant: , line:53:37, endln:53:41 |vpiParent: @@ -135699,7 +135699,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:54:17, endln:54:36 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiRhs: \_constant: , line:54:35, endln:54:36 |vpiParent: @@ -135734,7 +135734,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:55:17, endln:55:37 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiRhs: \_constant: , line:55:33, endln:55:37 |vpiParent: @@ -135769,7 +135769,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:56:17, endln:56:33 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiRhs: \_constant: , line:56:31, endln:56:33 |vpiParent: @@ -135804,7 +135804,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:57:17, endln:57:45 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiRhs: \_constant: , line:57:41, endln:57:45 |vpiParent: @@ -135839,7 +135839,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:58:17, endln:58:41 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiRhs: \_constant: , line:58:39, endln:58:41 |vpiParent: @@ -135874,7 +135874,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:59:17, endln:59:43 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiRhs: \_constant: , line:59:39, endln:59:43 |vpiParent: @@ -135909,7 +135909,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:60:17, endln:60:39 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiRhs: \_constant: , line:60:37, endln:60:39 |vpiParent: @@ -135944,7 +135944,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:61:17, endln:61:43 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiRhs: \_constant: , line:61:39, endln:61:43 |vpiParent: @@ -135979,7 +135979,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:62:17, endln:62:38 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiRhs: \_constant: , line:62:37, endln:62:38 |vpiParent: @@ -136014,7 +136014,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:63:17, endln:63:37 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiRhs: \_constant: , line:63:33, endln:63:37 |vpiParent: @@ -136049,7 +136049,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:64:17, endln:64:33 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiRhs: \_constant: , line:64:31, endln:64:33 |vpiParent: @@ -136084,7 +136084,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:65:17, endln:65:46 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiRhs: \_constant: , line:65:42, endln:65:46 |vpiParent: @@ -136119,7 +136119,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:66:17, endln:66:42 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiRhs: \_constant: , line:66:40, endln:66:42 |vpiParent: @@ -136154,7 +136154,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:67:17, endln:67:46 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiRhs: \_constant: , line:67:42, endln:67:46 |vpiParent: @@ -136189,7 +136189,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:68:17, endln:68:42 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiRhs: \_constant: , line:68:40, endln:68:42 |vpiParent: @@ -136224,7 +136224,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:69:17, endln:69:45 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiRhs: \_constant: , line:69:41, endln:69:45 |vpiParent: @@ -136259,7 +136259,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:70:17, endln:70:41 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiRhs: \_constant: , line:70:39, endln:70:41 |vpiParent: @@ -136294,7 +136294,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:71:17, endln:71:43 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiRhs: \_constant: , line:71:39, endln:71:43 |vpiParent: @@ -136329,7 +136329,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:72:17, endln:72:38 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiRhs: \_constant: , line:72:37, endln:72:38 |vpiParent: @@ -136364,7 +136364,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:73:17, endln:73:37 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiRhs: \_constant: , line:73:33, endln:73:37 |vpiParent: @@ -136399,7 +136399,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:74:17, endln:74:34 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiRhs: \_constant: , line:74:31, endln:74:34 |vpiParent: @@ -136434,7 +136434,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:75:17, endln:75:38 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiRhs: \_constant: , line:75:34, endln:75:38 |vpiParent: @@ -136469,7 +136469,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:76:17, endln:76:34 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiRhs: \_constant: , line:76:32, endln:76:34 |vpiParent: @@ -136504,7 +136504,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:77:17, endln:77:50 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiRhs: \_constant: , line:77:46, endln:77:50 |vpiParent: @@ -136539,7 +136539,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:78:17, endln:78:46 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiRhs: \_constant: , line:78:44, endln:78:46 |vpiParent: @@ -136574,7 +136574,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:79:17, endln:79:50 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiRhs: \_constant: , line:79:46, endln:79:50 |vpiParent: @@ -136609,7 +136609,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:80:17, endln:80:46 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiRhs: \_constant: , line:80:44, endln:80:46 |vpiParent: @@ -136644,7 +136644,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:81:17, endln:81:43 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiRhs: \_constant: , line:81:39, endln:81:43 |vpiParent: @@ -136679,7 +136679,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:82:17, endln:82:38 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiRhs: \_constant: , line:82:37, endln:82:38 |vpiParent: @@ -136714,7 +136714,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:83:17, endln:83:39 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiRhs: \_constant: , line:83:35, endln:83:39 |vpiParent: @@ -136749,7 +136749,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:84:17, endln:84:35 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiRhs: \_constant: , line:84:33, endln:84:35 |vpiParent: @@ -136784,7 +136784,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:85:17, endln:85:37 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiRhs: \_constant: , line:85:33, endln:85:37 |vpiParent: @@ -136819,7 +136819,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:86:17, endln:86:33 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiRhs: \_constant: , line:86:31, endln:86:33 |vpiParent: @@ -136854,7 +136854,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:87:17, endln:87:45 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiRhs: \_constant: , line:87:41, endln:87:45 |vpiParent: @@ -136889,7 +136889,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:88:17, endln:88:41 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiRhs: \_constant: , line:88:39, endln:88:41 |vpiParent: @@ -136924,7 +136924,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:89:17, endln:89:30 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiRhs: \_constant: , line:89:29, endln:89:30 |vpiParent: @@ -136959,7 +136959,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:322:26, endln:322:60 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiRhs: \_constant: , line:322:55, endln:322:60 |vpiParent: @@ -137031,7 +137031,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:323:26, endln:323:61 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiRhs: \_constant: , line:323:56, endln:323:61 |vpiParent: @@ -137103,7 +137103,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:324:26, endln:324:59 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiRhs: \_constant: , line:324:54, endln:324:59 |vpiParent: @@ -137175,7 +137175,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:325:26, endln:325:60 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiRhs: \_constant: , line:325:55, endln:325:60 |vpiParent: @@ -137247,7 +137247,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:326:26, endln:326:57 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiRhs: \_constant: , line:326:51, endln:326:57 |vpiParent: @@ -137319,7 +137319,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:327:26, endln:327:59 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiRhs: \_constant: , line:327:53, endln:327:59 |vpiParent: @@ -137391,7 +137391,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:328:26, endln:328:71 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiRhs: \_constant: , line:328:65, endln:328:71 |vpiParent: @@ -137463,7 +137463,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:329:26, endln:329:68 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiRhs: \_constant: , line:329:62, endln:329:68 |vpiParent: @@ -137535,7 +137535,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:330:26, endln:330:72 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiRhs: \_constant: , line:330:66, endln:330:72 |vpiParent: @@ -137607,7 +137607,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:331:26, endln:331:72 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiRhs: \_constant: , line:331:66, endln:331:72 |vpiParent: @@ -137679,7 +137679,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:332:26, endln:332:72 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiRhs: \_constant: , line:332:66, endln:332:72 |vpiParent: @@ -137751,7 +137751,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:333:26, endln:333:72 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiRhs: \_constant: , line:333:66, endln:333:72 |vpiParent: @@ -137823,7 +137823,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:334:26, endln:334:72 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiRhs: \_constant: , line:334:66, endln:334:72 |vpiParent: @@ -137895,7 +137895,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:335:26, endln:335:71 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiRhs: \_constant: , line:335:65, endln:335:71 |vpiParent: @@ -137967,7 +137967,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:336:26, endln:336:64 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiRhs: \_constant: , line:336:58, endln:336:64 |vpiParent: @@ -138039,7 +138039,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:337:26, endln:337:63 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiRhs: \_constant: , line:337:57, endln:337:63 |vpiParent: @@ -138111,7 +138111,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:338:26, endln:338:64 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiRhs: \_constant: , line:338:58, endln:338:64 |vpiParent: @@ -138183,7 +138183,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:339:26, endln:339:73 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiRhs: \_constant: , line:339:67, endln:339:73 |vpiParent: @@ -138255,7 +138255,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:340:26, endln:340:75 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiRhs: \_constant: , line:340:69, endln:340:75 |vpiParent: @@ -138327,7 +138327,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:341:26, endln:341:75 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiRhs: \_constant: , line:341:69, endln:341:75 |vpiParent: @@ -138399,7 +138399,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:342:26, endln:342:73 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiRhs: \_constant: , line:342:67, endln:342:73 |vpiParent: @@ -138471,7 +138471,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:343:26, endln:343:74 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiRhs: \_constant: , line:343:68, endln:343:74 |vpiParent: @@ -138543,7 +138543,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:344:26, endln:344:74 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiRhs: \_constant: , line:344:68, endln:344:74 |vpiParent: @@ -138615,7 +138615,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:345:26, endln:345:72 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiRhs: \_constant: , line:345:66, endln:345:72 |vpiParent: @@ -138687,7 +138687,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:346:26, endln:346:72 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiRhs: \_constant: , line:346:66, endln:346:72 |vpiParent: @@ -138759,7 +138759,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:347:26, endln:347:66 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiRhs: \_constant: , line:347:60, endln:347:66 |vpiParent: @@ -138831,7 +138831,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:348:26, endln:348:66 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiRhs: \_constant: , line:348:60, endln:348:66 |vpiParent: @@ -138903,7 +138903,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:349:26, endln:349:67 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiRhs: \_constant: , line:349:61, endln:349:67 |vpiParent: @@ -138975,7 +138975,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:350:26, endln:350:67 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiRhs: \_constant: , line:350:61, endln:350:67 |vpiParent: @@ -139047,7 +139047,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:351:26, endln:351:67 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiRhs: \_constant: , line:351:61, endln:351:67 |vpiParent: @@ -139119,7 +139119,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:352:26, endln:352:67 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiRhs: \_constant: , line:352:61, endln:352:67 |vpiParent: @@ -139191,7 +139191,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:353:26, endln:353:67 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiRhs: \_constant: , line:353:61, endln:353:67 |vpiParent: @@ -139263,7 +139263,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:354:26, endln:354:67 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiRhs: \_constant: , line:354:61, endln:354:67 |vpiParent: @@ -139335,7 +139335,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:357:26, endln:357:66 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiRhs: \_constant: , line:357:58, endln:357:66 |vpiParent: @@ -139407,7 +139407,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:358:26, endln:358:65 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiRhs: \_constant: , line:358:58, endln:358:65 |vpiParent: @@ -139479,7 +139479,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:359:26, endln:359:64 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiRhs: \_constant: , line:359:56, endln:359:64 |vpiParent: @@ -139551,7 +139551,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:360:26, endln:360:62 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiRhs: \_constant: , line:360:56, endln:360:62 |vpiParent: @@ -139623,7 +139623,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:400:25, endln:434:4 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiRhs: \_operation: , line:400:48, endln:434:4 |vpiParent: @@ -139998,7 +139998,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:774:37, endln:774:59 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiRhs: \_operation: , line:774:44, endln:774:59 |vpiTypespec: @@ -140017,7 +140017,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:786:18, endln:786:77 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:769:1, endln:788:10 |vpiRhs: \_operation: , line:786:33, endln:786:77 |vpiOpType:11 @@ -140218,12 +140218,12 @@ design: (work@otp_ctrl) |vpiTaskFunc: \_function: (otp_ctrl_pkg::vbits), line:14:1, endln:18:14 |uhdmtopModules: -\_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 +\_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiName:work@otp_ctrl |vpiParameter: \_parameter: (work@otp_ctrl.ConstSelWidth), line:522:17, endln:522:30 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |INT:3 |vpiTypespec: \_int_typespec: , line:522:13, endln:522:16 @@ -140239,7 +140239,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.CreatorRootKeyShare0Offset), line:77:17, endln:77:43 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:1888 |vpiTypespec: \_int_typespec: , line:77:13, endln:77:16 @@ -140255,7 +140255,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.CreatorRootKeyShare0Size), line:78:17, endln:78:41 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:32 |vpiTypespec: \_int_typespec: , line:78:13, endln:78:16 @@ -140271,7 +140271,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.CreatorRootKeyShare1Offset), line:79:17, endln:79:43 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:1920 |vpiTypespec: \_int_typespec: , line:79:13, endln:79:16 @@ -140287,7 +140287,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.CreatorRootKeyShare1Size), line:80:17, endln:80:41 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:32 |vpiTypespec: \_int_typespec: , line:80:13, endln:80:16 @@ -140303,7 +140303,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.CreatorSwCfgContentOffset), line:37:17, endln:37:42 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:0 |vpiTypespec: \_int_typespec: , line:37:13, endln:37:16 @@ -140319,7 +140319,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.CreatorSwCfgContentSize), line:38:17, endln:38:40 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:760 |vpiTypespec: \_int_typespec: , line:38:13, endln:38:16 @@ -140335,7 +140335,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.CreatorSwCfgDigestOffset), line:39:17, endln:39:41 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:760 |vpiTypespec: \_int_typespec: , line:39:13, endln:39:16 @@ -140351,7 +140351,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.CreatorSwCfgDigestSize), line:40:17, endln:40:39 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:8 |vpiTypespec: \_int_typespec: , line:40:13, endln:40:16 @@ -140367,7 +140367,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.CreatorSwCfgOffset), line:35:17, endln:35:35 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:0 |vpiTypespec: \_int_typespec: , line:35:13, endln:35:16 @@ -140383,7 +140383,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.CreatorSwCfgSize), line:36:17, endln:36:33 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:768 |vpiTypespec: \_int_typespec: , line:36:13, endln:36:16 @@ -140399,7 +140399,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.DaiCmdWidth), line:468:17, endln:468:28 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:3 |vpiTypespec: \_int_typespec: , line:468:13, endln:468:16 @@ -140415,7 +140415,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.DeviceIdOffset), line:49:17, endln:49:31 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:1536 |vpiTypespec: \_int_typespec: , line:49:13, endln:49:16 @@ -140431,7 +140431,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.DeviceIdSize), line:50:17, endln:50:29 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:32 |vpiTypespec: \_int_typespec: , line:50:13, endln:50:16 @@ -140447,7 +140447,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.EdnDataWidth), line:448:17, endln:448:29 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:64 |vpiTypespec: \_int_typespec: , line:448:13, endln:448:16 @@ -140463,7 +140463,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.FLASH_OTP_KEY_RSP_DEFAULT), line:672:33, endln:672:58 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiTypespec: \_struct_typespec: (otp_ctrl_pkg::flash_otp_key_rsp_t), line:664:11, endln:664:17 |vpiParent: @@ -140562,7 +140562,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.FlashAddrKeySeedOffset), line:65:17, endln:65:39 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:1784 |vpiTypespec: \_int_typespec: , line:65:13, endln:65:16 @@ -140578,7 +140578,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.FlashAddrKeySeedSize), line:66:17, endln:66:37 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:32 |vpiTypespec: \_int_typespec: , line:66:13, endln:66:16 @@ -140594,7 +140594,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.FlashDataKeySeedOffset), line:67:17, endln:67:39 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:1816 |vpiTypespec: \_int_typespec: , line:67:13, endln:67:16 @@ -140610,7 +140610,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.FlashDataKeySeedSize), line:68:17, endln:68:37 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:32 |vpiTypespec: \_int_typespec: , line:68:13, endln:68:16 @@ -140626,7 +140626,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.FlashKeySeedWidth), line:625:17, endln:625:34 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:256 |vpiTypespec: \_int_typespec: , line:625:13, endln:625:16 @@ -140642,7 +140642,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.FlashKeyWidth), line:628:17, endln:628:30 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:128 |vpiTypespec: \_int_typespec: , line:628:13, endln:628:16 @@ -140658,7 +140658,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.HwCfgContentOffset), line:51:17, endln:51:35 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:1568 |vpiTypespec: \_int_typespec: , line:51:13, endln:51:16 @@ -140674,7 +140674,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.HwCfgContentSize), line:52:17, endln:52:33 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:168 |vpiTypespec: \_int_typespec: , line:52:13, endln:52:16 @@ -140690,7 +140690,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.HwCfgDigestOffset), line:53:17, endln:53:34 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:1736 |vpiTypespec: \_int_typespec: , line:53:13, endln:53:16 @@ -140706,7 +140706,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.HwCfgDigestSize), line:54:17, endln:54:32 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:8 |vpiTypespec: \_int_typespec: , line:54:13, endln:54:16 @@ -140722,7 +140722,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.HwCfgOffset), line:47:17, endln:47:28 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:1536 |vpiTypespec: \_int_typespec: , line:47:13, endln:47:16 @@ -140738,7 +140738,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.HwCfgSize), line:48:17, endln:48:26 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:208 |vpiTypespec: \_int_typespec: , line:48:13, endln:48:16 @@ -140754,7 +140754,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.KeyMgrKeyWidth), line:627:17, endln:627:31 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:256 |vpiTypespec: \_int_typespec: , line:627:13, endln:627:16 @@ -140770,7 +140770,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.LcStateOffset), line:85:17, endln:85:30 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:1992 |vpiTypespec: \_int_typespec: , line:85:13, endln:85:16 @@ -140786,7 +140786,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.LcStateSize), line:86:17, endln:86:28 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:24 |vpiTypespec: \_int_typespec: , line:86:13, endln:86:16 @@ -140802,7 +140802,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.LcTransitionCntOffset), line:87:17, endln:87:38 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:2016 |vpiTypespec: \_int_typespec: , line:87:13, endln:87:16 @@ -140818,7 +140818,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.LcTransitionCntSize), line:88:17, endln:88:36 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:32 |vpiTypespec: \_int_typespec: , line:88:13, endln:88:16 @@ -140834,7 +140834,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.LfsrWidth), line:728:18, endln:728:27 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:40 |vpiTypespec: \_int_typespec: , line:728:14, endln:728:17 @@ -140851,7 +140851,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.LifeCycleOffset), line:83:17, endln:83:32 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:1992 |vpiTypespec: \_int_typespec: , line:83:13, endln:83:16 @@ -140867,7 +140867,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.LifeCycleSize), line:84:17, endln:84:30 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:56 |vpiTypespec: \_int_typespec: , line:84:13, endln:84:16 @@ -140883,7 +140883,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.NumAlerts), line:89:17, endln:89:26 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:2 |vpiTypespec: \_int_typespec: , line:89:13, endln:89:16 @@ -140899,7 +140899,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.NumDaiWords), line:30:17, endln:30:28 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:2 |vpiTypespec: \_int_typespec: , line:30:13, endln:30:16 @@ -140915,7 +140915,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.NumDebugWindowWords), line:33:17, endln:33:36 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:16 |vpiTypespec: \_int_typespec: , line:33:13, endln:33:16 @@ -140931,7 +140931,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.NumDigestSets), line:521:17, endln:521:30 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:5 |vpiTypespec: \_int_typespec: , line:521:13, endln:521:16 @@ -140947,7 +140947,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.NumDigestWords), line:31:17, endln:31:31 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:2 |vpiTypespec: \_int_typespec: , line:31:13, endln:31:16 @@ -140963,7 +140963,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.NumErrorEntries), line:29:17, endln:29:32 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:9 |vpiTypespec: \_int_typespec: , line:29:13, endln:29:16 @@ -140979,7 +140979,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.NumPart), line:34:17, endln:34:24 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:7 |vpiTypespec: \_int_typespec: , line:34:13, endln:34:16 @@ -140995,7 +140995,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.NumPartWidth), line:450:17, endln:450:29 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |INT:3 |vpiTypespec: \_int_typespec: , line:450:13, endln:450:16 @@ -141011,7 +141011,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.NumPresentRounds), line:508:17, endln:508:33 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:31 |vpiTypespec: \_int_typespec: , line:508:13, endln:508:16 @@ -141027,7 +141027,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.NumScrmblKeys), line:520:17, endln:520:30 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:3 |vpiTypespec: \_int_typespec: , line:520:13, endln:520:16 @@ -141043,7 +141043,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.NumSramKeyReqSlots), line:27:17, endln:27:35 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:2 |vpiTypespec: \_int_typespec: , line:27:13, endln:27:16 @@ -141059,7 +141059,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.NumSwCfgWindowWords), line:32:17, endln:32:36 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:512 |vpiTypespec: \_int_typespec: , line:32:13, endln:32:16 @@ -141075,7 +141075,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OTP_CTRL_ALERT_TEST_OFFSET), line:325:26, endln:325:52 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |HEX:c |vpiTypespec: \_logic_typespec: , line:325:13, endln:325:25 @@ -141109,7 +141109,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OTP_CTRL_CHECK_REGWEN_OFFSET), line:337:26, endln:337:54 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |HEX:3c |vpiTypespec: \_logic_typespec: , line:337:13, endln:337:25 @@ -141143,7 +141143,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OTP_CTRL_CHECK_TIMEOUT_OFFSET), line:338:26, endln:338:55 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |HEX:40 |vpiTypespec: \_logic_typespec: , line:338:13, endln:338:25 @@ -141177,7 +141177,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OTP_CTRL_CHECK_TRIGGER_OFFSET), line:336:26, endln:336:55 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |HEX:38 |vpiTypespec: \_logic_typespec: , line:336:13, endln:336:25 @@ -141211,7 +141211,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OTP_CTRL_CHECK_TRIGGER_REGWEN_OFFSET), line:335:26, endln:335:62 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |HEX:34 |vpiTypespec: \_logic_typespec: , line:335:13, endln:335:25 @@ -141245,7 +141245,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OTP_CTRL_CONSISTENCY_CHECK_PERIOD_OFFSET), line:340:26, endln:340:66 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |HEX:48 |vpiTypespec: \_logic_typespec: , line:340:13, endln:340:25 @@ -141279,7 +141279,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_OFFSET), line:343:26, endln:343:65 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |HEX:54 |vpiTypespec: \_logic_typespec: , line:343:13, endln:343:25 @@ -141313,7 +141313,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_OFFSET), line:344:26, endln:344:65 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |HEX:58 |vpiTypespec: \_logic_typespec: , line:344:13, endln:344:25 @@ -141347,7 +141347,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OTP_CTRL_CREATOR_SW_CFG_READ_LOCK_OFFSET), line:341:26, endln:341:66 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |HEX:4c |vpiTypespec: \_logic_typespec: , line:341:13, endln:341:25 @@ -141381,7 +141381,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OTP_CTRL_DIRECT_ACCESS_ADDRESS_OFFSET), line:330:26, endln:330:63 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |HEX:20 |vpiTypespec: \_logic_typespec: , line:330:13, endln:330:25 @@ -141415,7 +141415,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OTP_CTRL_DIRECT_ACCESS_CMD_OFFSET), line:329:26, endln:329:59 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |HEX:1c |vpiTypespec: \_logic_typespec: , line:329:13, endln:329:25 @@ -141449,7 +141449,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OTP_CTRL_DIRECT_ACCESS_RDATA_0_OFFSET), line:333:26, endln:333:63 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |HEX:2c |vpiTypespec: \_logic_typespec: , line:333:13, endln:333:25 @@ -141483,7 +141483,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OTP_CTRL_DIRECT_ACCESS_RDATA_1_OFFSET), line:334:26, endln:334:63 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |HEX:30 |vpiTypespec: \_logic_typespec: , line:334:13, endln:334:25 @@ -141517,7 +141517,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OTP_CTRL_DIRECT_ACCESS_REGWEN_OFFSET), line:328:26, endln:328:62 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |HEX:18 |vpiTypespec: \_logic_typespec: , line:328:13, endln:328:25 @@ -141551,7 +141551,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OTP_CTRL_DIRECT_ACCESS_WDATA_0_OFFSET), line:331:26, endln:331:63 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |HEX:24 |vpiTypespec: \_logic_typespec: , line:331:13, endln:331:25 @@ -141585,7 +141585,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OTP_CTRL_DIRECT_ACCESS_WDATA_1_OFFSET), line:332:26, endln:332:63 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |HEX:28 |vpiTypespec: \_logic_typespec: , line:332:13, endln:332:25 @@ -141619,7 +141619,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OTP_CTRL_ERR_CODE_OFFSET), line:327:26, endln:327:50 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |HEX:14 |vpiTypespec: \_logic_typespec: , line:327:13, endln:327:25 @@ -141653,7 +141653,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OTP_CTRL_HW_CFG_DIGEST_0_OFFSET), line:347:26, endln:347:57 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |HEX:64 |vpiTypespec: \_logic_typespec: , line:347:13, endln:347:25 @@ -141687,7 +141687,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OTP_CTRL_HW_CFG_DIGEST_1_OFFSET), line:348:26, endln:348:57 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |HEX:68 |vpiTypespec: \_logic_typespec: , line:348:13, endln:348:25 @@ -141721,7 +141721,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OTP_CTRL_INTEGRITY_CHECK_PERIOD_OFFSET), line:339:26, endln:339:64 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |HEX:44 |vpiTypespec: \_logic_typespec: , line:339:13, endln:339:25 @@ -141755,7 +141755,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OTP_CTRL_INTR_ENABLE_OFFSET), line:323:26, endln:323:53 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |HEX:4 |vpiTypespec: \_logic_typespec: , line:323:13, endln:323:25 @@ -141789,7 +141789,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OTP_CTRL_INTR_STATE_OFFSET), line:322:26, endln:322:52 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |HEX:0 |vpiTypespec: \_logic_typespec: , line:322:13, endln:322:25 @@ -141823,7 +141823,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OTP_CTRL_INTR_TEST_OFFSET), line:324:26, endln:324:51 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |HEX:8 |vpiTypespec: \_logic_typespec: , line:324:13, endln:324:25 @@ -141857,7 +141857,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OTP_CTRL_OWNER_SW_CFG_DIGEST_0_OFFSET), line:345:26, endln:345:63 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |HEX:5c |vpiTypespec: \_logic_typespec: , line:345:13, endln:345:25 @@ -141891,7 +141891,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OTP_CTRL_OWNER_SW_CFG_DIGEST_1_OFFSET), line:346:26, endln:346:63 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |HEX:60 |vpiTypespec: \_logic_typespec: , line:346:13, endln:346:25 @@ -141925,7 +141925,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OTP_CTRL_OWNER_SW_CFG_READ_LOCK_OFFSET), line:342:26, endln:342:64 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |HEX:50 |vpiTypespec: \_logic_typespec: , line:342:13, endln:342:25 @@ -141959,7 +141959,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OTP_CTRL_PERMIT), line:400:25, endln:400:40 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiSize:33 |vpiTypespec: \_array_typespec: @@ -142061,7 +142061,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OTP_CTRL_SECRET0_DIGEST_0_OFFSET), line:349:26, endln:349:58 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |HEX:6c |vpiTypespec: \_logic_typespec: , line:349:13, endln:349:25 @@ -142095,7 +142095,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OTP_CTRL_SECRET0_DIGEST_1_OFFSET), line:350:26, endln:350:58 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |HEX:70 |vpiTypespec: \_logic_typespec: , line:350:13, endln:350:25 @@ -142129,7 +142129,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OTP_CTRL_SECRET1_DIGEST_0_OFFSET), line:351:26, endln:351:58 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |HEX:74 |vpiTypespec: \_logic_typespec: , line:351:13, endln:351:25 @@ -142163,7 +142163,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OTP_CTRL_SECRET1_DIGEST_1_OFFSET), line:352:26, endln:352:58 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |HEX:78 |vpiTypespec: \_logic_typespec: , line:352:13, endln:352:25 @@ -142197,7 +142197,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OTP_CTRL_SECRET2_DIGEST_0_OFFSET), line:353:26, endln:353:58 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |HEX:7c |vpiTypespec: \_logic_typespec: , line:353:13, endln:353:25 @@ -142231,7 +142231,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OTP_CTRL_SECRET2_DIGEST_1_OFFSET), line:354:26, endln:354:58 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |HEX:80 |vpiTypespec: \_logic_typespec: , line:354:13, endln:354:25 @@ -142265,7 +142265,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OTP_CTRL_STATUS_OFFSET), line:326:26, endln:326:48 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |HEX:10 |vpiTypespec: \_logic_typespec: , line:326:13, endln:326:25 @@ -142299,7 +142299,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OTP_CTRL_SW_CFG_WINDOW_OFFSET), line:357:26, endln:357:55 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |HEX:1000 |vpiTypespec: \_logic_typespec: , line:357:13, endln:357:25 @@ -142333,7 +142333,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OTP_CTRL_SW_CFG_WINDOW_SIZE), line:358:26, endln:358:53 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |HEX:800 |vpiTypespec: \_logic_typespec: , line:358:13, endln:358:25 @@ -142367,7 +142367,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OTP_CTRL_TEST_ACCESS_OFFSET), line:359:26, endln:359:53 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |HEX:2000 |vpiTypespec: \_logic_typespec: , line:359:13, endln:359:25 @@ -142401,7 +142401,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OTP_CTRL_TEST_ACCESS_SIZE), line:360:26, endln:360:51 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |HEX:40 |vpiTypespec: \_logic_typespec: , line:360:13, endln:360:25 @@ -142435,7 +142435,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OTP_KEYMGR_KEY_DEFAULT), line:645:30, endln:645:52 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiTypespec: \_struct_typespec: (otp_ctrl_pkg::otp_keymgr_key_t), line:639:11, endln:639:17 |vpiParent: @@ -142538,7 +142538,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OTP_LC_DATA_DEFAULT), line:587:27, endln:587:46 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiTypespec: \_struct_typespec: (otp_ctrl_pkg::otp_lc_data_t), line:573:11, endln:573:17 |vpiParent: @@ -142705,7 +142705,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OtbnKeyWidth), line:631:17, endln:631:29 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:128 |vpiTypespec: \_int_typespec: , line:631:13, endln:631:16 @@ -142721,7 +142721,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OtbnNonceWidth), line:632:17, endln:632:31 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:256 |vpiTypespec: \_int_typespec: , line:632:13, endln:632:16 @@ -142737,7 +142737,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OtpAddrShift), line:488:17, endln:488:29 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |INT:1 |vpiTypespec: \_int_typespec: , line:488:13, endln:488:16 @@ -142753,7 +142753,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OtpAddrWidth), line:481:17, endln:481:29 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |INT:10 |vpiTypespec: \_int_typespec: , line:481:13, endln:481:16 @@ -142769,7 +142769,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OtpByteAddrWidth), line:28:17, endln:28:33 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:11 |vpiTypespec: \_int_typespec: , line:28:13, endln:28:16 @@ -142785,7 +142785,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OtpDepth), line:482:17, endln:482:25 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |INT:1024 |vpiTypespec: \_int_typespec: , line:482:13, endln:482:16 @@ -142801,7 +142801,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OtpErrWidth), line:484:17, endln:484:28 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:3 |vpiTypespec: \_int_typespec: , line:484:13, endln:484:16 @@ -142817,7 +142817,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OtpIfWidth), line:486:17, endln:486:27 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |INT:64 |vpiTypespec: \_int_typespec: , line:486:13, endln:486:16 @@ -142833,7 +142833,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OtpPwrSeqWidth), line:485:17, endln:485:31 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:2 |vpiTypespec: \_int_typespec: , line:485:13, endln:485:16 @@ -142849,7 +142849,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OtpSizeWidth), line:483:17, endln:483:29 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:2 |vpiTypespec: \_int_typespec: , line:483:13, endln:483:16 @@ -142865,7 +142865,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OtpWidth), line:480:17, endln:480:25 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:16 |vpiTypespec: \_int_typespec: , line:480:13, endln:480:16 @@ -142881,7 +142881,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OwnerSwCfgContentOffset), line:43:17, endln:43:40 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:768 |vpiTypespec: \_int_typespec: , line:43:13, endln:43:16 @@ -142897,7 +142897,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OwnerSwCfgContentSize), line:44:17, endln:44:38 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:760 |vpiTypespec: \_int_typespec: , line:44:13, endln:44:16 @@ -142913,7 +142913,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OwnerSwCfgDigestOffset), line:45:17, endln:45:39 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:1528 |vpiTypespec: \_int_typespec: , line:45:13, endln:45:16 @@ -142929,7 +142929,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OwnerSwCfgDigestSize), line:46:17, endln:46:37 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:8 |vpiTypespec: \_int_typespec: , line:46:13, endln:46:16 @@ -142945,7 +142945,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OwnerSwCfgOffset), line:41:17, endln:41:33 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:768 |vpiTypespec: \_int_typespec: , line:41:13, endln:41:16 @@ -142961,7 +142961,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OwnerSwCfgSize), line:42:17, endln:42:31 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:768 |vpiTypespec: \_int_typespec: , line:42:13, endln:42:16 @@ -142977,7 +142977,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.RmaTokenOffset), line:75:17, endln:75:31 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:1872 |vpiTypespec: \_int_typespec: , line:75:13, endln:75:16 @@ -142993,7 +142993,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.RmaTokenSize), line:76:17, endln:76:29 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:16 |vpiTypespec: \_int_typespec: , line:76:13, endln:76:16 @@ -143009,7 +143009,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.RndCnstDigestConstDefault), line:746:34, endln:746:59 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiTypespec: \_logic_typespec: (digest_const_array_t), line:745:11, endln:745:56 |vpiParent: @@ -143110,7 +143110,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.RndCnstDigestIVDefault), line:755:31, endln:755:53 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiTypespec: \_logic_typespec: (digest_iv_array_t), line:754:11, endln:754:58 |vpiParent: @@ -143211,7 +143211,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.RndCnstKeyDefault), line:737:25, endln:737:42 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiTypespec: \_logic_typespec: (key_array_t), line:736:11, endln:736:56 |vpiParent: @@ -143312,7 +143312,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.RndCnstLfsrPermDefault), line:732:26, endln:732:48 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |HEX:4235171482c225f79289b32181a0163a760355d3447063d16661e44c12a5 |vpiTypespec: \_logic_typespec: (lfsr_perm_t), line:730:11, endln:730:55 @@ -143415,7 +143415,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.RndCnstLfsrSeedDefault), line:731:26, endln:731:48 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |HEX:453d28ea98 |vpiTypespec: \_logic_typespec: (lfsr_seed_t), line:729:11, endln:729:32 @@ -143478,7 +143478,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.RndCnstRawUnlockTokenDefault), line:763:37, endln:763:65 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |HEX:cbbd013ff15eba2f3065461eeb88463e |vpiTypespec: \_unsupported_typespec: (lc_ctrl_pkg::lc_token_t), line:763:13, endln:763:26 @@ -143493,7 +143493,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.ScrmblBlockHalfWords), line:509:17, endln:509:37 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |INT:4 |vpiTypespec: \_int_typespec: , line:509:13, endln:509:16 @@ -143509,7 +143509,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.ScrmblBlockWidth), line:506:17, endln:506:33 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:64 |vpiTypespec: \_int_typespec: , line:506:13, endln:506:16 @@ -143525,7 +143525,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.ScrmblKeyWidth), line:505:17, endln:505:31 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:128 |vpiTypespec: \_int_typespec: , line:505:13, endln:505:16 @@ -143541,7 +143541,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.Secret0DigestOffset), line:61:17, endln:61:36 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:1776 |vpiTypespec: \_int_typespec: , line:61:13, endln:61:16 @@ -143557,7 +143557,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.Secret0DigestSize), line:62:17, endln:62:34 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:8 |vpiTypespec: \_int_typespec: , line:62:13, endln:62:16 @@ -143573,7 +143573,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.Secret0Offset), line:55:17, endln:55:30 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:1744 |vpiTypespec: \_int_typespec: , line:55:13, endln:55:16 @@ -143589,7 +143589,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.Secret0Size), line:56:17, endln:56:28 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:40 |vpiTypespec: \_int_typespec: , line:56:13, endln:56:16 @@ -143605,7 +143605,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.Secret1DigestOffset), line:71:17, endln:71:36 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:1864 |vpiTypespec: \_int_typespec: , line:71:13, endln:71:16 @@ -143621,7 +143621,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.Secret1DigestSize), line:72:17, endln:72:34 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:8 |vpiTypespec: \_int_typespec: , line:72:13, endln:72:16 @@ -143637,7 +143637,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.Secret1Offset), line:63:17, endln:63:30 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:1784 |vpiTypespec: \_int_typespec: , line:63:13, endln:63:16 @@ -143653,7 +143653,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.Secret1Size), line:64:17, endln:64:28 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:88 |vpiTypespec: \_int_typespec: , line:64:13, endln:64:16 @@ -143669,7 +143669,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.Secret2DigestOffset), line:81:17, endln:81:36 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:1984 |vpiTypespec: \_int_typespec: , line:81:13, endln:81:16 @@ -143685,7 +143685,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.Secret2DigestSize), line:82:17, endln:82:34 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:8 |vpiTypespec: \_int_typespec: , line:82:13, endln:82:16 @@ -143701,7 +143701,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.Secret2Offset), line:73:17, endln:73:30 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:1872 |vpiTypespec: \_int_typespec: , line:73:13, endln:73:16 @@ -143717,7 +143717,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.Secret2Size), line:74:17, endln:74:28 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:120 |vpiTypespec: \_int_typespec: , line:74:13, endln:74:16 @@ -143733,7 +143733,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.SramDataKeySeedOffset), line:69:17, endln:69:38 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:1848 |vpiTypespec: \_int_typespec: , line:69:13, endln:69:16 @@ -143749,7 +143749,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.SramDataKeySeedSize), line:70:17, endln:70:36 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:16 |vpiTypespec: \_int_typespec: , line:70:13, endln:70:16 @@ -143765,7 +143765,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.SramKeySeedWidth), line:626:17, endln:626:33 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:128 |vpiTypespec: \_int_typespec: , line:626:13, endln:626:16 @@ -143781,7 +143781,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.SramKeyWidth), line:629:17, endln:629:29 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:128 |vpiTypespec: \_int_typespec: , line:629:13, endln:629:16 @@ -143797,7 +143797,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.SramNonceWidth), line:630:17, endln:630:31 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:64 |vpiTypespec: \_int_typespec: , line:630:13, endln:630:16 @@ -143813,7 +143813,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.SwWindowAddrWidth), line:452:17, endln:452:34 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |INT:9 |vpiTypespec: \_int_typespec: , line:452:13, endln:452:16 @@ -143829,7 +143829,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.TestExitTokenOffset), line:59:17, endln:59:36 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:1760 |vpiTypespec: \_int_typespec: , line:59:13, endln:59:16 @@ -143845,7 +143845,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.TestExitTokenSize), line:60:17, endln:60:34 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:16 |vpiTypespec: \_int_typespec: , line:60:13, endln:60:16 @@ -143861,7 +143861,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.TestUnlockTokenOffset), line:57:17, endln:57:38 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:1744 |vpiTypespec: \_int_typespec: , line:57:13, endln:57:16 @@ -143877,7 +143877,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.TestUnlockTokenSize), line:58:17, endln:58:36 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:16 |vpiTypespec: \_int_typespec: , line:58:13, endln:58:16 @@ -143893,7 +143893,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.CreatorRootKeyShare0Offset), line:77:17, endln:77:43 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:1888 |vpiTypespec: \_int_typespec: , line:77:13, endln:77:16 @@ -143909,7 +143909,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.CreatorRootKeyShare0Size), line:78:17, endln:78:41 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:32 |vpiTypespec: \_int_typespec: , line:78:13, endln:78:16 @@ -143925,7 +143925,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.CreatorRootKeyShare1Offset), line:79:17, endln:79:43 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:1920 |vpiTypespec: \_int_typespec: , line:79:13, endln:79:16 @@ -143941,7 +143941,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.CreatorRootKeyShare1Size), line:80:17, endln:80:41 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:32 |vpiTypespec: \_int_typespec: , line:80:13, endln:80:16 @@ -143957,7 +143957,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.CreatorSwCfgContentOffset), line:37:17, endln:37:42 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:0 |vpiTypespec: \_int_typespec: , line:37:13, endln:37:16 @@ -143973,7 +143973,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.CreatorSwCfgContentSize), line:38:17, endln:38:40 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:760 |vpiTypespec: \_int_typespec: , line:38:13, endln:38:16 @@ -143989,7 +143989,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.CreatorSwCfgDigestOffset), line:39:17, endln:39:41 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:760 |vpiTypespec: \_int_typespec: , line:39:13, endln:39:16 @@ -144005,7 +144005,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.CreatorSwCfgDigestSize), line:40:17, endln:40:39 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:8 |vpiTypespec: \_int_typespec: , line:40:13, endln:40:16 @@ -144021,7 +144021,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.CreatorSwCfgOffset), line:35:17, endln:35:35 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:0 |vpiTypespec: \_int_typespec: , line:35:13, endln:35:16 @@ -144037,7 +144037,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.CreatorSwCfgSize), line:36:17, endln:36:33 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:768 |vpiTypespec: \_int_typespec: , line:36:13, endln:36:16 @@ -144053,7 +144053,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.DeviceIdOffset), line:49:17, endln:49:31 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:1536 |vpiTypespec: \_int_typespec: , line:49:13, endln:49:16 @@ -144069,7 +144069,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.DeviceIdSize), line:50:17, endln:50:29 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:32 |vpiTypespec: \_int_typespec: , line:50:13, endln:50:16 @@ -144085,7 +144085,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.FlashAddrKeySeedOffset), line:65:17, endln:65:39 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:1784 |vpiTypespec: \_int_typespec: , line:65:13, endln:65:16 @@ -144101,7 +144101,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.FlashAddrKeySeedSize), line:66:17, endln:66:37 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:32 |vpiTypespec: \_int_typespec: , line:66:13, endln:66:16 @@ -144117,7 +144117,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.FlashDataKeySeedOffset), line:67:17, endln:67:39 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:1816 |vpiTypespec: \_int_typespec: , line:67:13, endln:67:16 @@ -144133,7 +144133,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.FlashDataKeySeedSize), line:68:17, endln:68:37 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:32 |vpiTypespec: \_int_typespec: , line:68:13, endln:68:16 @@ -144149,7 +144149,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.HwCfgContentOffset), line:51:17, endln:51:35 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:1568 |vpiTypespec: \_int_typespec: , line:51:13, endln:51:16 @@ -144165,7 +144165,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.HwCfgContentSize), line:52:17, endln:52:33 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:168 |vpiTypespec: \_int_typespec: , line:52:13, endln:52:16 @@ -144181,7 +144181,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.HwCfgDigestOffset), line:53:17, endln:53:34 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:1736 |vpiTypespec: \_int_typespec: , line:53:13, endln:53:16 @@ -144197,7 +144197,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.HwCfgDigestSize), line:54:17, endln:54:32 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:8 |vpiTypespec: \_int_typespec: , line:54:13, endln:54:16 @@ -144213,7 +144213,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.HwCfgOffset), line:47:17, endln:47:28 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:1536 |vpiTypespec: \_int_typespec: , line:47:13, endln:47:16 @@ -144229,7 +144229,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.HwCfgSize), line:48:17, endln:48:26 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:208 |vpiTypespec: \_int_typespec: , line:48:13, endln:48:16 @@ -144245,7 +144245,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.LcStateOffset), line:85:17, endln:85:30 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:1992 |vpiTypespec: \_int_typespec: , line:85:13, endln:85:16 @@ -144261,7 +144261,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.LcStateSize), line:86:17, endln:86:28 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:24 |vpiTypespec: \_int_typespec: , line:86:13, endln:86:16 @@ -144277,7 +144277,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.LcTransitionCntOffset), line:87:17, endln:87:38 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:2016 |vpiTypespec: \_int_typespec: , line:87:13, endln:87:16 @@ -144293,7 +144293,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.LcTransitionCntSize), line:88:17, endln:88:36 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:32 |vpiTypespec: \_int_typespec: , line:88:13, endln:88:16 @@ -144309,7 +144309,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.LifeCycleOffset), line:83:17, endln:83:32 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:1992 |vpiTypespec: \_int_typespec: , line:83:13, endln:83:16 @@ -144325,7 +144325,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.LifeCycleSize), line:84:17, endln:84:30 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:56 |vpiTypespec: \_int_typespec: , line:84:13, endln:84:16 @@ -144341,7 +144341,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.NumAlerts), line:89:17, endln:89:26 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:2 |vpiTypespec: \_int_typespec: , line:89:13, endln:89:16 @@ -144357,7 +144357,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.NumDaiWords), line:30:17, endln:30:28 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:2 |vpiTypespec: \_int_typespec: , line:30:13, endln:30:16 @@ -144373,7 +144373,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.NumDebugWindowWords), line:33:17, endln:33:36 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:16 |vpiTypespec: \_int_typespec: , line:33:13, endln:33:16 @@ -144389,7 +144389,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.NumDigestWords), line:31:17, endln:31:31 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:2 |vpiTypespec: \_int_typespec: , line:31:13, endln:31:16 @@ -144405,7 +144405,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.NumErrorEntries), line:29:17, endln:29:32 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:9 |vpiTypespec: \_int_typespec: , line:29:13, endln:29:16 @@ -144421,7 +144421,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.NumPart), line:34:17, endln:34:24 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:7 |vpiTypespec: \_int_typespec: , line:34:13, endln:34:16 @@ -144437,7 +144437,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.NumSramKeyReqSlots), line:27:17, endln:27:35 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:2 |vpiTypespec: \_int_typespec: , line:27:13, endln:27:16 @@ -144453,7 +144453,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.NumSwCfgWindowWords), line:32:17, endln:32:36 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:512 |vpiTypespec: \_int_typespec: , line:32:13, endln:32:16 @@ -144469,7 +144469,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OTP_CTRL_ALERT_TEST_OFFSET), line:325:26, endln:325:52 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |HEX:c |vpiTypespec: \_logic_typespec: , line:325:13, endln:325:25 @@ -144503,7 +144503,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OTP_CTRL_CHECK_REGWEN_OFFSET), line:337:26, endln:337:54 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |HEX:3c |vpiTypespec: \_logic_typespec: , line:337:13, endln:337:25 @@ -144537,7 +144537,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OTP_CTRL_CHECK_TIMEOUT_OFFSET), line:338:26, endln:338:55 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |HEX:40 |vpiTypespec: \_logic_typespec: , line:338:13, endln:338:25 @@ -144571,7 +144571,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OTP_CTRL_CHECK_TRIGGER_OFFSET), line:336:26, endln:336:55 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |HEX:38 |vpiTypespec: \_logic_typespec: , line:336:13, endln:336:25 @@ -144605,7 +144605,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OTP_CTRL_CHECK_TRIGGER_REGWEN_OFFSET), line:335:26, endln:335:62 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |HEX:34 |vpiTypespec: \_logic_typespec: , line:335:13, endln:335:25 @@ -144639,7 +144639,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OTP_CTRL_CONSISTENCY_CHECK_PERIOD_OFFSET), line:340:26, endln:340:66 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |HEX:48 |vpiTypespec: \_logic_typespec: , line:340:13, endln:340:25 @@ -144673,7 +144673,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_OFFSET), line:343:26, endln:343:65 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |HEX:54 |vpiTypespec: \_logic_typespec: , line:343:13, endln:343:25 @@ -144707,7 +144707,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_OFFSET), line:344:26, endln:344:65 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |HEX:58 |vpiTypespec: \_logic_typespec: , line:344:13, endln:344:25 @@ -144741,7 +144741,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OTP_CTRL_CREATOR_SW_CFG_READ_LOCK_OFFSET), line:341:26, endln:341:66 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |HEX:4c |vpiTypespec: \_logic_typespec: , line:341:13, endln:341:25 @@ -144775,7 +144775,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OTP_CTRL_DIRECT_ACCESS_ADDRESS_OFFSET), line:330:26, endln:330:63 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |HEX:20 |vpiTypespec: \_logic_typespec: , line:330:13, endln:330:25 @@ -144809,7 +144809,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OTP_CTRL_DIRECT_ACCESS_CMD_OFFSET), line:329:26, endln:329:59 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |HEX:1c |vpiTypespec: \_logic_typespec: , line:329:13, endln:329:25 @@ -144843,7 +144843,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OTP_CTRL_DIRECT_ACCESS_RDATA_0_OFFSET), line:333:26, endln:333:63 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |HEX:2c |vpiTypespec: \_logic_typespec: , line:333:13, endln:333:25 @@ -144877,7 +144877,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OTP_CTRL_DIRECT_ACCESS_RDATA_1_OFFSET), line:334:26, endln:334:63 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |HEX:30 |vpiTypespec: \_logic_typespec: , line:334:13, endln:334:25 @@ -144911,7 +144911,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OTP_CTRL_DIRECT_ACCESS_REGWEN_OFFSET), line:328:26, endln:328:62 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |HEX:18 |vpiTypespec: \_logic_typespec: , line:328:13, endln:328:25 @@ -144945,7 +144945,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OTP_CTRL_DIRECT_ACCESS_WDATA_0_OFFSET), line:331:26, endln:331:63 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |HEX:24 |vpiTypespec: \_logic_typespec: , line:331:13, endln:331:25 @@ -144979,7 +144979,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OTP_CTRL_DIRECT_ACCESS_WDATA_1_OFFSET), line:332:26, endln:332:63 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |HEX:28 |vpiTypespec: \_logic_typespec: , line:332:13, endln:332:25 @@ -145013,7 +145013,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OTP_CTRL_ERR_CODE_OFFSET), line:327:26, endln:327:50 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |HEX:14 |vpiTypespec: \_logic_typespec: , line:327:13, endln:327:25 @@ -145047,7 +145047,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OTP_CTRL_HW_CFG_DIGEST_0_OFFSET), line:347:26, endln:347:57 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |HEX:64 |vpiTypespec: \_logic_typespec: , line:347:13, endln:347:25 @@ -145081,7 +145081,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OTP_CTRL_HW_CFG_DIGEST_1_OFFSET), line:348:26, endln:348:57 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |HEX:68 |vpiTypespec: \_logic_typespec: , line:348:13, endln:348:25 @@ -145115,7 +145115,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OTP_CTRL_INTEGRITY_CHECK_PERIOD_OFFSET), line:339:26, endln:339:64 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |HEX:44 |vpiTypespec: \_logic_typespec: , line:339:13, endln:339:25 @@ -145149,7 +145149,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OTP_CTRL_INTR_ENABLE_OFFSET), line:323:26, endln:323:53 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |HEX:4 |vpiTypespec: \_logic_typespec: , line:323:13, endln:323:25 @@ -145183,7 +145183,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OTP_CTRL_INTR_STATE_OFFSET), line:322:26, endln:322:52 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |HEX:0 |vpiTypespec: \_logic_typespec: , line:322:13, endln:322:25 @@ -145217,7 +145217,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OTP_CTRL_INTR_TEST_OFFSET), line:324:26, endln:324:51 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |HEX:8 |vpiTypespec: \_logic_typespec: , line:324:13, endln:324:25 @@ -145251,7 +145251,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OTP_CTRL_OWNER_SW_CFG_DIGEST_0_OFFSET), line:345:26, endln:345:63 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |HEX:5c |vpiTypespec: \_logic_typespec: , line:345:13, endln:345:25 @@ -145285,7 +145285,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OTP_CTRL_OWNER_SW_CFG_DIGEST_1_OFFSET), line:346:26, endln:346:63 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |HEX:60 |vpiTypespec: \_logic_typespec: , line:346:13, endln:346:25 @@ -145319,7 +145319,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OTP_CTRL_OWNER_SW_CFG_READ_LOCK_OFFSET), line:342:26, endln:342:64 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |HEX:50 |vpiTypespec: \_logic_typespec: , line:342:13, endln:342:25 @@ -145353,7 +145353,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OTP_CTRL_PERMIT), line:400:25, endln:400:40 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiSize:33 |vpiTypespec: \_array_typespec: @@ -145455,7 +145455,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OTP_CTRL_SECRET0_DIGEST_0_OFFSET), line:349:26, endln:349:58 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |HEX:6c |vpiTypespec: \_logic_typespec: , line:349:13, endln:349:25 @@ -145489,7 +145489,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OTP_CTRL_SECRET0_DIGEST_1_OFFSET), line:350:26, endln:350:58 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |HEX:70 |vpiTypespec: \_logic_typespec: , line:350:13, endln:350:25 @@ -145523,7 +145523,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OTP_CTRL_SECRET1_DIGEST_0_OFFSET), line:351:26, endln:351:58 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |HEX:74 |vpiTypespec: \_logic_typespec: , line:351:13, endln:351:25 @@ -145557,7 +145557,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OTP_CTRL_SECRET1_DIGEST_1_OFFSET), line:352:26, endln:352:58 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |HEX:78 |vpiTypespec: \_logic_typespec: , line:352:13, endln:352:25 @@ -145591,7 +145591,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OTP_CTRL_SECRET2_DIGEST_0_OFFSET), line:353:26, endln:353:58 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |HEX:7c |vpiTypespec: \_logic_typespec: , line:353:13, endln:353:25 @@ -145625,7 +145625,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OTP_CTRL_SECRET2_DIGEST_1_OFFSET), line:354:26, endln:354:58 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |HEX:80 |vpiTypespec: \_logic_typespec: , line:354:13, endln:354:25 @@ -145659,7 +145659,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OTP_CTRL_STATUS_OFFSET), line:326:26, endln:326:48 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |HEX:10 |vpiTypespec: \_logic_typespec: , line:326:13, endln:326:25 @@ -145693,7 +145693,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OTP_CTRL_SW_CFG_WINDOW_OFFSET), line:357:26, endln:357:55 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |HEX:1000 |vpiTypespec: \_logic_typespec: , line:357:13, endln:357:25 @@ -145727,7 +145727,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OTP_CTRL_SW_CFG_WINDOW_SIZE), line:358:26, endln:358:53 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |HEX:800 |vpiTypespec: \_logic_typespec: , line:358:13, endln:358:25 @@ -145761,7 +145761,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OTP_CTRL_TEST_ACCESS_OFFSET), line:359:26, endln:359:53 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |HEX:2000 |vpiTypespec: \_logic_typespec: , line:359:13, endln:359:25 @@ -145795,7 +145795,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OTP_CTRL_TEST_ACCESS_SIZE), line:360:26, endln:360:51 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |HEX:40 |vpiTypespec: \_logic_typespec: , line:360:13, endln:360:25 @@ -145829,7 +145829,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OtpByteAddrWidth), line:28:17, endln:28:33 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:11 |vpiTypespec: \_int_typespec: , line:28:13, endln:28:16 @@ -145845,7 +145845,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OwnerSwCfgContentOffset), line:43:17, endln:43:40 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:768 |vpiTypespec: \_int_typespec: , line:43:13, endln:43:16 @@ -145861,7 +145861,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OwnerSwCfgContentSize), line:44:17, endln:44:38 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:760 |vpiTypespec: \_int_typespec: , line:44:13, endln:44:16 @@ -145877,7 +145877,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OwnerSwCfgDigestOffset), line:45:17, endln:45:39 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:1528 |vpiTypespec: \_int_typespec: , line:45:13, endln:45:16 @@ -145893,7 +145893,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OwnerSwCfgDigestSize), line:46:17, endln:46:37 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:8 |vpiTypespec: \_int_typespec: , line:46:13, endln:46:16 @@ -145909,7 +145909,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OwnerSwCfgOffset), line:41:17, endln:41:33 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:768 |vpiTypespec: \_int_typespec: , line:41:13, endln:41:16 @@ -145925,7 +145925,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OwnerSwCfgSize), line:42:17, endln:42:31 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:768 |vpiTypespec: \_int_typespec: , line:42:13, endln:42:16 @@ -145941,7 +145941,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.RmaTokenOffset), line:75:17, endln:75:31 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:1872 |vpiTypespec: \_int_typespec: , line:75:13, endln:75:16 @@ -145957,7 +145957,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.RmaTokenSize), line:76:17, endln:76:29 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:16 |vpiTypespec: \_int_typespec: , line:76:13, endln:76:16 @@ -145973,7 +145973,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.Secret0DigestOffset), line:61:17, endln:61:36 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:1776 |vpiTypespec: \_int_typespec: , line:61:13, endln:61:16 @@ -145989,7 +145989,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.Secret0DigestSize), line:62:17, endln:62:34 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:8 |vpiTypespec: \_int_typespec: , line:62:13, endln:62:16 @@ -146005,7 +146005,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.Secret0Offset), line:55:17, endln:55:30 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:1744 |vpiTypespec: \_int_typespec: , line:55:13, endln:55:16 @@ -146021,7 +146021,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.Secret0Size), line:56:17, endln:56:28 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:40 |vpiTypespec: \_int_typespec: , line:56:13, endln:56:16 @@ -146037,7 +146037,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.Secret1DigestOffset), line:71:17, endln:71:36 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:1864 |vpiTypespec: \_int_typespec: , line:71:13, endln:71:16 @@ -146053,7 +146053,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.Secret1DigestSize), line:72:17, endln:72:34 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:8 |vpiTypespec: \_int_typespec: , line:72:13, endln:72:16 @@ -146069,7 +146069,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.Secret1Offset), line:63:17, endln:63:30 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:1784 |vpiTypespec: \_int_typespec: , line:63:13, endln:63:16 @@ -146085,7 +146085,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.Secret1Size), line:64:17, endln:64:28 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:88 |vpiTypespec: \_int_typespec: , line:64:13, endln:64:16 @@ -146101,7 +146101,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.Secret2DigestOffset), line:81:17, endln:81:36 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:1984 |vpiTypespec: \_int_typespec: , line:81:13, endln:81:16 @@ -146117,7 +146117,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.Secret2DigestSize), line:82:17, endln:82:34 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:8 |vpiTypespec: \_int_typespec: , line:82:13, endln:82:16 @@ -146133,7 +146133,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.Secret2Offset), line:73:17, endln:73:30 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:1872 |vpiTypespec: \_int_typespec: , line:73:13, endln:73:16 @@ -146149,7 +146149,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.Secret2Size), line:74:17, endln:74:28 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:120 |vpiTypespec: \_int_typespec: , line:74:13, endln:74:16 @@ -146165,7 +146165,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.SramDataKeySeedOffset), line:69:17, endln:69:38 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:1848 |vpiTypespec: \_int_typespec: , line:69:13, endln:69:16 @@ -146181,7 +146181,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.SramDataKeySeedSize), line:70:17, endln:70:36 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:16 |vpiTypespec: \_int_typespec: , line:70:13, endln:70:16 @@ -146197,7 +146197,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.TestExitTokenOffset), line:59:17, endln:59:36 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:1760 |vpiTypespec: \_int_typespec: , line:59:13, endln:59:16 @@ -146213,7 +146213,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.TestExitTokenSize), line:60:17, endln:60:34 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:16 |vpiTypespec: \_int_typespec: , line:60:13, endln:60:16 @@ -146229,7 +146229,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.TestUnlockTokenOffset), line:57:17, endln:57:38 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:1744 |vpiTypespec: \_int_typespec: , line:57:13, endln:57:16 @@ -146245,7 +146245,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.TestUnlockTokenSize), line:58:17, endln:58:36 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:16 |vpiTypespec: \_int_typespec: , line:58:13, endln:58:16 @@ -146261,7 +146261,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.ConstSelWidth), line:522:17, endln:522:30 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |INT:3 |vpiTypespec: \_int_typespec: , line:522:13, endln:522:16 @@ -146277,7 +146277,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.CreatorRootKeyShare0Offset), line:77:17, endln:77:43 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:1888 |vpiTypespec: \_int_typespec: , line:77:13, endln:77:16 @@ -146293,7 +146293,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.CreatorRootKeyShare0Size), line:78:17, endln:78:41 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:32 |vpiTypespec: \_int_typespec: , line:78:13, endln:78:16 @@ -146309,7 +146309,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.CreatorRootKeyShare1Offset), line:79:17, endln:79:43 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:1920 |vpiTypespec: \_int_typespec: , line:79:13, endln:79:16 @@ -146325,7 +146325,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.CreatorRootKeyShare1Size), line:80:17, endln:80:41 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:32 |vpiTypespec: \_int_typespec: , line:80:13, endln:80:16 @@ -146341,7 +146341,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.CreatorSwCfgContentOffset), line:37:17, endln:37:42 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:0 |vpiTypespec: \_int_typespec: , line:37:13, endln:37:16 @@ -146357,7 +146357,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.CreatorSwCfgContentSize), line:38:17, endln:38:40 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:760 |vpiTypespec: \_int_typespec: , line:38:13, endln:38:16 @@ -146373,7 +146373,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.CreatorSwCfgDigestOffset), line:39:17, endln:39:41 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:760 |vpiTypespec: \_int_typespec: , line:39:13, endln:39:16 @@ -146389,7 +146389,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.CreatorSwCfgDigestSize), line:40:17, endln:40:39 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:8 |vpiTypespec: \_int_typespec: , line:40:13, endln:40:16 @@ -146405,7 +146405,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.CreatorSwCfgOffset), line:35:17, endln:35:35 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:0 |vpiTypespec: \_int_typespec: , line:35:13, endln:35:16 @@ -146421,7 +146421,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.CreatorSwCfgSize), line:36:17, endln:36:33 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:768 |vpiTypespec: \_int_typespec: , line:36:13, endln:36:16 @@ -146437,7 +146437,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.DaiCmdWidth), line:468:17, endln:468:28 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:3 |vpiTypespec: \_int_typespec: , line:468:13, endln:468:16 @@ -146453,7 +146453,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.DeviceIdOffset), line:49:17, endln:49:31 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:1536 |vpiTypespec: \_int_typespec: , line:49:13, endln:49:16 @@ -146469,7 +146469,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.DeviceIdSize), line:50:17, endln:50:29 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:32 |vpiTypespec: \_int_typespec: , line:50:13, endln:50:16 @@ -146485,7 +146485,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.EdnDataWidth), line:448:17, endln:448:29 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:64 |vpiTypespec: \_int_typespec: , line:448:13, endln:448:16 @@ -146501,7 +146501,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.FLASH_OTP_KEY_RSP_DEFAULT), line:672:33, endln:672:58 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiTypespec: \_struct_typespec: (otp_ctrl_pkg::flash_otp_key_rsp_t), line:664:11, endln:664:17 |vpiParent: @@ -146600,7 +146600,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.FlashAddrKeySeedOffset), line:65:17, endln:65:39 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:1784 |vpiTypespec: \_int_typespec: , line:65:13, endln:65:16 @@ -146616,7 +146616,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.FlashAddrKeySeedSize), line:66:17, endln:66:37 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:32 |vpiTypespec: \_int_typespec: , line:66:13, endln:66:16 @@ -146632,7 +146632,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.FlashDataKeySeedOffset), line:67:17, endln:67:39 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:1816 |vpiTypespec: \_int_typespec: , line:67:13, endln:67:16 @@ -146648,7 +146648,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.FlashDataKeySeedSize), line:68:17, endln:68:37 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:32 |vpiTypespec: \_int_typespec: , line:68:13, endln:68:16 @@ -146664,7 +146664,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.FlashKeySeedWidth), line:625:17, endln:625:34 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:256 |vpiTypespec: \_int_typespec: , line:625:13, endln:625:16 @@ -146680,7 +146680,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.FlashKeyWidth), line:628:17, endln:628:30 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:128 |vpiTypespec: \_int_typespec: , line:628:13, endln:628:16 @@ -146696,7 +146696,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.HwCfgContentOffset), line:51:17, endln:51:35 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:1568 |vpiTypespec: \_int_typespec: , line:51:13, endln:51:16 @@ -146712,7 +146712,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.HwCfgContentSize), line:52:17, endln:52:33 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:168 |vpiTypespec: \_int_typespec: , line:52:13, endln:52:16 @@ -146728,7 +146728,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.HwCfgDigestOffset), line:53:17, endln:53:34 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:1736 |vpiTypespec: \_int_typespec: , line:53:13, endln:53:16 @@ -146744,7 +146744,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.HwCfgDigestSize), line:54:17, endln:54:32 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:8 |vpiTypespec: \_int_typespec: , line:54:13, endln:54:16 @@ -146760,7 +146760,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.HwCfgOffset), line:47:17, endln:47:28 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:1536 |vpiTypespec: \_int_typespec: , line:47:13, endln:47:16 @@ -146776,7 +146776,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.HwCfgSize), line:48:17, endln:48:26 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:208 |vpiTypespec: \_int_typespec: , line:48:13, endln:48:16 @@ -146792,7 +146792,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.KeyMgrKeyWidth), line:627:17, endln:627:31 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:256 |vpiTypespec: \_int_typespec: , line:627:13, endln:627:16 @@ -146808,7 +146808,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.LcStateOffset), line:85:17, endln:85:30 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:1992 |vpiTypespec: \_int_typespec: , line:85:13, endln:85:16 @@ -146824,7 +146824,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.LcStateSize), line:86:17, endln:86:28 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:24 |vpiTypespec: \_int_typespec: , line:86:13, endln:86:16 @@ -146840,7 +146840,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.LcTransitionCntOffset), line:87:17, endln:87:38 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:2016 |vpiTypespec: \_int_typespec: , line:87:13, endln:87:16 @@ -146856,7 +146856,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.LcTransitionCntSize), line:88:17, endln:88:36 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:32 |vpiTypespec: \_int_typespec: , line:88:13, endln:88:16 @@ -146872,7 +146872,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.LfsrWidth), line:728:18, endln:728:27 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:40 |vpiTypespec: \_int_typespec: , line:728:14, endln:728:17 @@ -146889,7 +146889,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.LifeCycleOffset), line:83:17, endln:83:32 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:1992 |vpiTypespec: \_int_typespec: , line:83:13, endln:83:16 @@ -146905,7 +146905,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.LifeCycleSize), line:84:17, endln:84:30 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:56 |vpiTypespec: \_int_typespec: , line:84:13, endln:84:16 @@ -146921,7 +146921,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.NumAlerts), line:89:17, endln:89:26 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:2 |vpiTypespec: \_int_typespec: , line:89:13, endln:89:16 @@ -146937,7 +146937,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.NumDaiWords), line:30:17, endln:30:28 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:2 |vpiTypespec: \_int_typespec: , line:30:13, endln:30:16 @@ -146953,7 +146953,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.NumDebugWindowWords), line:33:17, endln:33:36 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:16 |vpiTypespec: \_int_typespec: , line:33:13, endln:33:16 @@ -146969,7 +146969,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.NumDigestSets), line:521:17, endln:521:30 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:5 |vpiTypespec: \_int_typespec: , line:521:13, endln:521:16 @@ -146985,7 +146985,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.NumDigestWords), line:31:17, endln:31:31 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:2 |vpiTypespec: \_int_typespec: , line:31:13, endln:31:16 @@ -147001,7 +147001,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.NumErrorEntries), line:29:17, endln:29:32 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:9 |vpiTypespec: \_int_typespec: , line:29:13, endln:29:16 @@ -147017,7 +147017,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.NumPart), line:34:17, endln:34:24 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:7 |vpiTypespec: \_int_typespec: , line:34:13, endln:34:16 @@ -147033,7 +147033,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.NumPartWidth), line:450:17, endln:450:29 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |INT:3 |vpiTypespec: \_int_typespec: , line:450:13, endln:450:16 @@ -147049,7 +147049,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.NumPresentRounds), line:508:17, endln:508:33 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:31 |vpiTypespec: \_int_typespec: , line:508:13, endln:508:16 @@ -147065,7 +147065,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.NumScrmblKeys), line:520:17, endln:520:30 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:3 |vpiTypespec: \_int_typespec: , line:520:13, endln:520:16 @@ -147081,7 +147081,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.NumSramKeyReqSlots), line:27:17, endln:27:35 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:2 |vpiTypespec: \_int_typespec: , line:27:13, endln:27:16 @@ -147097,7 +147097,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.NumSwCfgWindowWords), line:32:17, endln:32:36 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:512 |vpiTypespec: \_int_typespec: , line:32:13, endln:32:16 @@ -147113,7 +147113,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OTP_CTRL_ALERT_TEST_OFFSET), line:325:26, endln:325:52 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |HEX:c |vpiTypespec: \_logic_typespec: , line:325:13, endln:325:25 @@ -147147,7 +147147,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OTP_CTRL_CHECK_REGWEN_OFFSET), line:337:26, endln:337:54 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |HEX:3c |vpiTypespec: \_logic_typespec: , line:337:13, endln:337:25 @@ -147181,7 +147181,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OTP_CTRL_CHECK_TIMEOUT_OFFSET), line:338:26, endln:338:55 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |HEX:40 |vpiTypespec: \_logic_typespec: , line:338:13, endln:338:25 @@ -147215,7 +147215,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OTP_CTRL_CHECK_TRIGGER_OFFSET), line:336:26, endln:336:55 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |HEX:38 |vpiTypespec: \_logic_typespec: , line:336:13, endln:336:25 @@ -147249,7 +147249,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OTP_CTRL_CHECK_TRIGGER_REGWEN_OFFSET), line:335:26, endln:335:62 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |HEX:34 |vpiTypespec: \_logic_typespec: , line:335:13, endln:335:25 @@ -147283,7 +147283,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OTP_CTRL_CONSISTENCY_CHECK_PERIOD_OFFSET), line:340:26, endln:340:66 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |HEX:48 |vpiTypespec: \_logic_typespec: , line:340:13, endln:340:25 @@ -147317,7 +147317,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_OFFSET), line:343:26, endln:343:65 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |HEX:54 |vpiTypespec: \_logic_typespec: , line:343:13, endln:343:25 @@ -147351,7 +147351,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_OFFSET), line:344:26, endln:344:65 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |HEX:58 |vpiTypespec: \_logic_typespec: , line:344:13, endln:344:25 @@ -147385,7 +147385,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OTP_CTRL_CREATOR_SW_CFG_READ_LOCK_OFFSET), line:341:26, endln:341:66 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |HEX:4c |vpiTypespec: \_logic_typespec: , line:341:13, endln:341:25 @@ -147419,7 +147419,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OTP_CTRL_DIRECT_ACCESS_ADDRESS_OFFSET), line:330:26, endln:330:63 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |HEX:20 |vpiTypespec: \_logic_typespec: , line:330:13, endln:330:25 @@ -147453,7 +147453,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OTP_CTRL_DIRECT_ACCESS_CMD_OFFSET), line:329:26, endln:329:59 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |HEX:1c |vpiTypespec: \_logic_typespec: , line:329:13, endln:329:25 @@ -147487,7 +147487,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OTP_CTRL_DIRECT_ACCESS_RDATA_0_OFFSET), line:333:26, endln:333:63 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |HEX:2c |vpiTypespec: \_logic_typespec: , line:333:13, endln:333:25 @@ -147521,7 +147521,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OTP_CTRL_DIRECT_ACCESS_RDATA_1_OFFSET), line:334:26, endln:334:63 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |HEX:30 |vpiTypespec: \_logic_typespec: , line:334:13, endln:334:25 @@ -147555,7 +147555,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OTP_CTRL_DIRECT_ACCESS_REGWEN_OFFSET), line:328:26, endln:328:62 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |HEX:18 |vpiTypespec: \_logic_typespec: , line:328:13, endln:328:25 @@ -147589,7 +147589,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OTP_CTRL_DIRECT_ACCESS_WDATA_0_OFFSET), line:331:26, endln:331:63 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |HEX:24 |vpiTypespec: \_logic_typespec: , line:331:13, endln:331:25 @@ -147623,7 +147623,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OTP_CTRL_DIRECT_ACCESS_WDATA_1_OFFSET), line:332:26, endln:332:63 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |HEX:28 |vpiTypespec: \_logic_typespec: , line:332:13, endln:332:25 @@ -147657,7 +147657,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OTP_CTRL_ERR_CODE_OFFSET), line:327:26, endln:327:50 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |HEX:14 |vpiTypespec: \_logic_typespec: , line:327:13, endln:327:25 @@ -147691,7 +147691,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OTP_CTRL_HW_CFG_DIGEST_0_OFFSET), line:347:26, endln:347:57 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |HEX:64 |vpiTypespec: \_logic_typespec: , line:347:13, endln:347:25 @@ -147725,7 +147725,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OTP_CTRL_HW_CFG_DIGEST_1_OFFSET), line:348:26, endln:348:57 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |HEX:68 |vpiTypespec: \_logic_typespec: , line:348:13, endln:348:25 @@ -147759,7 +147759,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OTP_CTRL_INTEGRITY_CHECK_PERIOD_OFFSET), line:339:26, endln:339:64 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |HEX:44 |vpiTypespec: \_logic_typespec: , line:339:13, endln:339:25 @@ -147793,7 +147793,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OTP_CTRL_INTR_ENABLE_OFFSET), line:323:26, endln:323:53 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |HEX:4 |vpiTypespec: \_logic_typespec: , line:323:13, endln:323:25 @@ -147827,7 +147827,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OTP_CTRL_INTR_STATE_OFFSET), line:322:26, endln:322:52 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |HEX:0 |vpiTypespec: \_logic_typespec: , line:322:13, endln:322:25 @@ -147861,7 +147861,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OTP_CTRL_INTR_TEST_OFFSET), line:324:26, endln:324:51 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |HEX:8 |vpiTypespec: \_logic_typespec: , line:324:13, endln:324:25 @@ -147895,7 +147895,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OTP_CTRL_OWNER_SW_CFG_DIGEST_0_OFFSET), line:345:26, endln:345:63 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |HEX:5c |vpiTypespec: \_logic_typespec: , line:345:13, endln:345:25 @@ -147929,7 +147929,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OTP_CTRL_OWNER_SW_CFG_DIGEST_1_OFFSET), line:346:26, endln:346:63 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |HEX:60 |vpiTypespec: \_logic_typespec: , line:346:13, endln:346:25 @@ -147963,7 +147963,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OTP_CTRL_OWNER_SW_CFG_READ_LOCK_OFFSET), line:342:26, endln:342:64 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |HEX:50 |vpiTypespec: \_logic_typespec: , line:342:13, endln:342:25 @@ -147997,7 +147997,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OTP_CTRL_PERMIT), line:400:25, endln:400:40 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiSize:33 |vpiTypespec: \_array_typespec: @@ -148099,7 +148099,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OTP_CTRL_SECRET0_DIGEST_0_OFFSET), line:349:26, endln:349:58 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |HEX:6c |vpiTypespec: \_logic_typespec: , line:349:13, endln:349:25 @@ -148133,7 +148133,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OTP_CTRL_SECRET0_DIGEST_1_OFFSET), line:350:26, endln:350:58 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |HEX:70 |vpiTypespec: \_logic_typespec: , line:350:13, endln:350:25 @@ -148167,7 +148167,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OTP_CTRL_SECRET1_DIGEST_0_OFFSET), line:351:26, endln:351:58 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |HEX:74 |vpiTypespec: \_logic_typespec: , line:351:13, endln:351:25 @@ -148201,7 +148201,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OTP_CTRL_SECRET1_DIGEST_1_OFFSET), line:352:26, endln:352:58 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |HEX:78 |vpiTypespec: \_logic_typespec: , line:352:13, endln:352:25 @@ -148235,7 +148235,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OTP_CTRL_SECRET2_DIGEST_0_OFFSET), line:353:26, endln:353:58 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |HEX:7c |vpiTypespec: \_logic_typespec: , line:353:13, endln:353:25 @@ -148269,7 +148269,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OTP_CTRL_SECRET2_DIGEST_1_OFFSET), line:354:26, endln:354:58 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |HEX:80 |vpiTypespec: \_logic_typespec: , line:354:13, endln:354:25 @@ -148303,7 +148303,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OTP_CTRL_STATUS_OFFSET), line:326:26, endln:326:48 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |HEX:10 |vpiTypespec: \_logic_typespec: , line:326:13, endln:326:25 @@ -148337,7 +148337,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OTP_CTRL_SW_CFG_WINDOW_OFFSET), line:357:26, endln:357:55 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |HEX:1000 |vpiTypespec: \_logic_typespec: , line:357:13, endln:357:25 @@ -148371,7 +148371,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OTP_CTRL_SW_CFG_WINDOW_SIZE), line:358:26, endln:358:53 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |HEX:800 |vpiTypespec: \_logic_typespec: , line:358:13, endln:358:25 @@ -148405,7 +148405,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OTP_CTRL_TEST_ACCESS_OFFSET), line:359:26, endln:359:53 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |HEX:2000 |vpiTypespec: \_logic_typespec: , line:359:13, endln:359:25 @@ -148439,7 +148439,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OTP_CTRL_TEST_ACCESS_SIZE), line:360:26, endln:360:51 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |HEX:40 |vpiTypespec: \_logic_typespec: , line:360:13, endln:360:25 @@ -148473,7 +148473,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OTP_KEYMGR_KEY_DEFAULT), line:645:30, endln:645:52 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiTypespec: \_struct_typespec: (otp_ctrl_pkg::otp_keymgr_key_t), line:639:11, endln:639:17 |vpiParent: @@ -148576,7 +148576,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OTP_LC_DATA_DEFAULT), line:587:27, endln:587:46 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiTypespec: \_struct_typespec: (otp_ctrl_pkg::otp_lc_data_t), line:573:11, endln:573:17 |vpiParent: @@ -148743,7 +148743,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OtbnKeyWidth), line:631:17, endln:631:29 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:128 |vpiTypespec: \_int_typespec: , line:631:13, endln:631:16 @@ -148759,7 +148759,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OtbnNonceWidth), line:632:17, endln:632:31 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:256 |vpiTypespec: \_int_typespec: , line:632:13, endln:632:16 @@ -148775,7 +148775,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OtpAddrShift), line:488:17, endln:488:29 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |INT:1 |vpiTypespec: \_int_typespec: , line:488:13, endln:488:16 @@ -148791,7 +148791,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OtpAddrWidth), line:481:17, endln:481:29 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |INT:10 |vpiTypespec: \_int_typespec: , line:481:13, endln:481:16 @@ -148807,7 +148807,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OtpByteAddrWidth), line:28:17, endln:28:33 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:11 |vpiTypespec: \_int_typespec: , line:28:13, endln:28:16 @@ -148823,7 +148823,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OtpDepth), line:482:17, endln:482:25 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |INT:1024 |vpiTypespec: \_int_typespec: , line:482:13, endln:482:16 @@ -148839,7 +148839,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OtpErrWidth), line:484:17, endln:484:28 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:3 |vpiTypespec: \_int_typespec: , line:484:13, endln:484:16 @@ -148855,7 +148855,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OtpIfWidth), line:486:17, endln:486:27 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |INT:64 |vpiTypespec: \_int_typespec: , line:486:13, endln:486:16 @@ -148871,7 +148871,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OtpPwrSeqWidth), line:485:17, endln:485:31 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:2 |vpiTypespec: \_int_typespec: , line:485:13, endln:485:16 @@ -148887,7 +148887,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OtpSizeWidth), line:483:17, endln:483:29 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:2 |vpiTypespec: \_int_typespec: , line:483:13, endln:483:16 @@ -148903,7 +148903,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OtpWidth), line:480:17, endln:480:25 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:16 |vpiTypespec: \_int_typespec: , line:480:13, endln:480:16 @@ -148919,7 +148919,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OwnerSwCfgContentOffset), line:43:17, endln:43:40 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:768 |vpiTypespec: \_int_typespec: , line:43:13, endln:43:16 @@ -148935,7 +148935,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OwnerSwCfgContentSize), line:44:17, endln:44:38 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:760 |vpiTypespec: \_int_typespec: , line:44:13, endln:44:16 @@ -148951,7 +148951,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OwnerSwCfgDigestOffset), line:45:17, endln:45:39 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:1528 |vpiTypespec: \_int_typespec: , line:45:13, endln:45:16 @@ -148967,7 +148967,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OwnerSwCfgDigestSize), line:46:17, endln:46:37 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:8 |vpiTypespec: \_int_typespec: , line:46:13, endln:46:16 @@ -148983,7 +148983,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OwnerSwCfgOffset), line:41:17, endln:41:33 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:768 |vpiTypespec: \_int_typespec: , line:41:13, endln:41:16 @@ -148999,7 +148999,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.OwnerSwCfgSize), line:42:17, endln:42:31 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:768 |vpiTypespec: \_int_typespec: , line:42:13, endln:42:16 @@ -149015,7 +149015,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.PartInfo), line:795:26, endln:795:34 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiSize:1 |vpiTypespec: \_array_typespec: @@ -149384,7 +149384,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.RmaTokenOffset), line:75:17, endln:75:31 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:1872 |vpiTypespec: \_int_typespec: , line:75:13, endln:75:16 @@ -149400,7 +149400,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.RmaTokenSize), line:76:17, endln:76:29 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:16 |vpiTypespec: \_int_typespec: , line:76:13, endln:76:16 @@ -149416,7 +149416,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.RndCnstDigestConstDefault), line:746:34, endln:746:59 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiTypespec: \_logic_typespec: (digest_const_array_t), line:745:11, endln:745:56 |vpiParent: @@ -149517,7 +149517,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.RndCnstDigestIVDefault), line:755:31, endln:755:53 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiTypespec: \_logic_typespec: (digest_iv_array_t), line:754:11, endln:754:58 |vpiParent: @@ -149618,7 +149618,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.RndCnstKeyDefault), line:737:25, endln:737:42 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiTypespec: \_logic_typespec: (key_array_t), line:736:11, endln:736:56 |vpiParent: @@ -149719,7 +149719,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.RndCnstLfsrPermDefault), line:732:26, endln:732:48 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |HEX:4235171482c225f79289b32181a0163a760355d3447063d16661e44c12a5 |vpiTypespec: \_logic_typespec: (lfsr_perm_t), line:730:11, endln:730:55 @@ -149822,7 +149822,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.RndCnstLfsrSeedDefault), line:731:26, endln:731:48 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |HEX:453d28ea98 |vpiTypespec: \_logic_typespec: (lfsr_seed_t), line:729:11, endln:729:32 @@ -149885,7 +149885,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.RndCnstRawUnlockTokenDefault), line:763:37, endln:763:65 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |HEX:cbbd013ff15eba2f3065461eeb88463e |vpiTypespec: \_unsupported_typespec: (lc_ctrl_pkg::lc_token_t), line:763:13, endln:763:26 @@ -149900,7 +149900,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.ScrmblBlockHalfWords), line:509:17, endln:509:37 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |INT:4 |vpiTypespec: \_int_typespec: , line:509:13, endln:509:16 @@ -149916,7 +149916,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.ScrmblBlockWidth), line:506:17, endln:506:33 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:64 |vpiTypespec: \_int_typespec: , line:506:13, endln:506:16 @@ -149932,7 +149932,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.ScrmblKeyWidth), line:505:17, endln:505:31 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:128 |vpiTypespec: \_int_typespec: , line:505:13, endln:505:16 @@ -149948,7 +149948,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.Secret0DigestOffset), line:61:17, endln:61:36 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:1776 |vpiTypespec: \_int_typespec: , line:61:13, endln:61:16 @@ -149964,7 +149964,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.Secret0DigestSize), line:62:17, endln:62:34 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:8 |vpiTypespec: \_int_typespec: , line:62:13, endln:62:16 @@ -149980,7 +149980,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.Secret0Offset), line:55:17, endln:55:30 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:1744 |vpiTypespec: \_int_typespec: , line:55:13, endln:55:16 @@ -149996,7 +149996,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.Secret0Size), line:56:17, endln:56:28 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:40 |vpiTypespec: \_int_typespec: , line:56:13, endln:56:16 @@ -150012,7 +150012,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.Secret1DigestOffset), line:71:17, endln:71:36 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:1864 |vpiTypespec: \_int_typespec: , line:71:13, endln:71:16 @@ -150028,7 +150028,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.Secret1DigestSize), line:72:17, endln:72:34 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:8 |vpiTypespec: \_int_typespec: , line:72:13, endln:72:16 @@ -150044,7 +150044,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.Secret1Offset), line:63:17, endln:63:30 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:1784 |vpiTypespec: \_int_typespec: , line:63:13, endln:63:16 @@ -150060,7 +150060,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.Secret1Size), line:64:17, endln:64:28 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:88 |vpiTypespec: \_int_typespec: , line:64:13, endln:64:16 @@ -150076,7 +150076,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.Secret2DigestOffset), line:81:17, endln:81:36 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:1984 |vpiTypespec: \_int_typespec: , line:81:13, endln:81:16 @@ -150092,7 +150092,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.Secret2DigestSize), line:82:17, endln:82:34 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:8 |vpiTypespec: \_int_typespec: , line:82:13, endln:82:16 @@ -150108,7 +150108,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.Secret2Offset), line:73:17, endln:73:30 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:1872 |vpiTypespec: \_int_typespec: , line:73:13, endln:73:16 @@ -150124,7 +150124,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.Secret2Size), line:74:17, endln:74:28 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:120 |vpiTypespec: \_int_typespec: , line:74:13, endln:74:16 @@ -150140,7 +150140,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.SramDataKeySeedOffset), line:69:17, endln:69:38 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:1848 |vpiTypespec: \_int_typespec: , line:69:13, endln:69:16 @@ -150156,7 +150156,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.SramDataKeySeedSize), line:70:17, endln:70:36 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:16 |vpiTypespec: \_int_typespec: , line:70:13, endln:70:16 @@ -150172,7 +150172,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.SramKeySeedWidth), line:626:17, endln:626:33 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:128 |vpiTypespec: \_int_typespec: , line:626:13, endln:626:16 @@ -150188,7 +150188,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.SramKeyWidth), line:629:17, endln:629:29 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:128 |vpiTypespec: \_int_typespec: , line:629:13, endln:629:16 @@ -150204,7 +150204,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.SramNonceWidth), line:630:17, endln:630:31 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:64 |vpiTypespec: \_int_typespec: , line:630:13, endln:630:16 @@ -150220,7 +150220,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.SwWindowAddrWidth), line:452:17, endln:452:34 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |INT:9 |vpiTypespec: \_int_typespec: , line:452:13, endln:452:16 @@ -150236,7 +150236,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.TestExitTokenOffset), line:59:17, endln:59:36 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:1760 |vpiTypespec: \_int_typespec: , line:59:13, endln:59:16 @@ -150252,7 +150252,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.TestExitTokenSize), line:60:17, endln:60:34 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:16 |vpiTypespec: \_int_typespec: , line:60:13, endln:60:16 @@ -150268,7 +150268,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.TestUnlockTokenOffset), line:57:17, endln:57:38 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:1744 |vpiTypespec: \_int_typespec: , line:57:13, endln:57:16 @@ -150284,7 +150284,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.TestUnlockTokenSize), line:58:17, endln:58:36 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |UINT:16 |vpiTypespec: \_int_typespec: , line:58:13, endln:58:16 @@ -150300,7 +150300,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:27:17, endln:27:39 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:27:38, endln:27:39 |vpiDecompile:2 @@ -150314,7 +150314,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:28:17, endln:28:38 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:28:36, endln:28:38 |vpiDecompile:11 @@ -150328,7 +150328,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:29:17, endln:29:36 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:29:35, endln:29:36 |vpiDecompile:9 @@ -150342,7 +150342,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:30:17, endln:30:32 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:30:31, endln:30:32 |vpiDecompile:2 @@ -150356,7 +150356,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:31:17, endln:31:35 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:31:34, endln:31:35 |vpiDecompile:2 @@ -150370,7 +150370,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:32:17, endln:32:42 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:32:39, endln:32:42 |vpiDecompile:512 @@ -150384,7 +150384,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:33:17, endln:33:41 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:33:39, endln:33:41 |vpiDecompile:16 @@ -150398,7 +150398,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:34:17, endln:34:28 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:34:27, endln:34:28 |vpiDecompile:7 @@ -150412,7 +150412,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:35:17, endln:35:39 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:35:38, endln:35:39 |vpiDecompile:0 @@ -150426,7 +150426,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:36:17, endln:36:39 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:36:36, endln:36:39 |vpiDecompile:768 @@ -150440,7 +150440,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:37:17, endln:37:46 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:37:45, endln:37:46 |vpiDecompile:0 @@ -150454,7 +150454,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:38:17, endln:38:46 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:38:43, endln:38:46 |vpiDecompile:760 @@ -150468,7 +150468,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:39:17, endln:39:47 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:39:44, endln:39:47 |vpiDecompile:760 @@ -150482,7 +150482,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:40:17, endln:40:43 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:40:42, endln:40:43 |vpiDecompile:8 @@ -150496,7 +150496,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:41:17, endln:41:39 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:41:36, endln:41:39 |vpiDecompile:768 @@ -150510,7 +150510,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:42:17, endln:42:37 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:42:34, endln:42:37 |vpiDecompile:768 @@ -150524,7 +150524,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:43:17, endln:43:46 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:43:43, endln:43:46 |vpiDecompile:768 @@ -150538,7 +150538,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:44:17, endln:44:44 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:44:41, endln:44:44 |vpiDecompile:760 @@ -150552,7 +150552,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:45:17, endln:45:46 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:45:42, endln:45:46 |vpiDecompile:1528 @@ -150566,7 +150566,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:46:17, endln:46:41 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:46:40, endln:46:41 |vpiDecompile:8 @@ -150580,7 +150580,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:47:17, endln:47:35 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:47:31, endln:47:35 |vpiDecompile:1536 @@ -150594,7 +150594,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:48:17, endln:48:32 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:48:29, endln:48:32 |vpiDecompile:208 @@ -150608,7 +150608,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:49:17, endln:49:38 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:49:34, endln:49:38 |vpiDecompile:1536 @@ -150622,7 +150622,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:50:17, endln:50:34 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:50:32, endln:50:34 |vpiDecompile:32 @@ -150636,7 +150636,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:51:17, endln:51:42 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:51:38, endln:51:42 |vpiDecompile:1568 @@ -150650,7 +150650,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:52:17, endln:52:39 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:52:36, endln:52:39 |vpiDecompile:168 @@ -150664,7 +150664,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:53:17, endln:53:41 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:53:37, endln:53:41 |vpiDecompile:1736 @@ -150678,7 +150678,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:54:17, endln:54:36 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:54:35, endln:54:36 |vpiDecompile:8 @@ -150692,7 +150692,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:55:17, endln:55:37 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:55:33, endln:55:37 |vpiDecompile:1744 @@ -150706,7 +150706,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:56:17, endln:56:33 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:56:31, endln:56:33 |vpiDecompile:40 @@ -150720,7 +150720,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:57:17, endln:57:45 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:57:41, endln:57:45 |vpiDecompile:1744 @@ -150734,7 +150734,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:58:17, endln:58:41 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:58:39, endln:58:41 |vpiDecompile:16 @@ -150748,7 +150748,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:59:17, endln:59:43 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:59:39, endln:59:43 |vpiDecompile:1760 @@ -150762,7 +150762,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:60:17, endln:60:39 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:60:37, endln:60:39 |vpiDecompile:16 @@ -150776,7 +150776,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:61:17, endln:61:43 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:61:39, endln:61:43 |vpiDecompile:1776 @@ -150790,7 +150790,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:62:17, endln:62:38 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:62:37, endln:62:38 |vpiDecompile:8 @@ -150804,7 +150804,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:63:17, endln:63:37 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:63:33, endln:63:37 |vpiDecompile:1784 @@ -150818,7 +150818,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:64:17, endln:64:33 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:64:31, endln:64:33 |vpiDecompile:88 @@ -150832,7 +150832,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:65:17, endln:65:46 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:65:42, endln:65:46 |vpiDecompile:1784 @@ -150846,7 +150846,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:66:17, endln:66:42 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:66:40, endln:66:42 |vpiDecompile:32 @@ -150860,7 +150860,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:67:17, endln:67:46 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:67:42, endln:67:46 |vpiDecompile:1816 @@ -150874,7 +150874,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:68:17, endln:68:42 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:68:40, endln:68:42 |vpiDecompile:32 @@ -150888,7 +150888,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:69:17, endln:69:45 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:69:41, endln:69:45 |vpiDecompile:1848 @@ -150902,7 +150902,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:70:17, endln:70:41 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:70:39, endln:70:41 |vpiDecompile:16 @@ -150916,7 +150916,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:71:17, endln:71:43 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:71:39, endln:71:43 |vpiDecompile:1864 @@ -150930,7 +150930,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:72:17, endln:72:38 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:72:37, endln:72:38 |vpiDecompile:8 @@ -150944,7 +150944,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:73:17, endln:73:37 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:73:33, endln:73:37 |vpiDecompile:1872 @@ -150958,7 +150958,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:74:17, endln:74:34 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:74:31, endln:74:34 |vpiDecompile:120 @@ -150972,7 +150972,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:75:17, endln:75:38 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:75:34, endln:75:38 |vpiDecompile:1872 @@ -150986,7 +150986,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:76:17, endln:76:34 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:76:32, endln:76:34 |vpiDecompile:16 @@ -151000,7 +151000,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:77:17, endln:77:50 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:77:46, endln:77:50 |vpiDecompile:1888 @@ -151014,7 +151014,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:78:17, endln:78:46 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:78:44, endln:78:46 |vpiDecompile:32 @@ -151028,7 +151028,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:79:17, endln:79:50 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:79:46, endln:79:50 |vpiDecompile:1920 @@ -151042,7 +151042,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:80:17, endln:80:46 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:80:44, endln:80:46 |vpiDecompile:32 @@ -151056,7 +151056,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:81:17, endln:81:43 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:81:39, endln:81:43 |vpiDecompile:1984 @@ -151070,7 +151070,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:82:17, endln:82:38 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:82:37, endln:82:38 |vpiDecompile:8 @@ -151084,7 +151084,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:83:17, endln:83:39 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:83:35, endln:83:39 |vpiDecompile:1992 @@ -151098,7 +151098,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:84:17, endln:84:35 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:84:33, endln:84:35 |vpiDecompile:56 @@ -151112,7 +151112,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:85:17, endln:85:37 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:85:33, endln:85:37 |vpiDecompile:1992 @@ -151126,7 +151126,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:86:17, endln:86:33 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:86:31, endln:86:33 |vpiDecompile:24 @@ -151140,7 +151140,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:87:17, endln:87:45 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:87:41, endln:87:45 |vpiDecompile:2016 @@ -151154,7 +151154,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:88:17, endln:88:41 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:88:39, endln:88:41 |vpiDecompile:32 @@ -151168,7 +151168,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:89:17, endln:89:30 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:89:29, endln:89:30 |vpiDecompile:2 @@ -151182,7 +151182,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:322:26, endln:322:60 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:322:55, endln:322:60 |vpiDecompile:14'h0 @@ -151194,7 +151194,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:323:26, endln:323:61 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:323:56, endln:323:61 |vpiDecompile:14'h4 @@ -151206,7 +151206,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:324:26, endln:324:59 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:324:54, endln:324:59 |vpiDecompile:14'h8 @@ -151218,7 +151218,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:325:26, endln:325:60 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:325:55, endln:325:60 |vpiDecompile:14'hc @@ -151230,7 +151230,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:326:26, endln:326:57 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:326:51, endln:326:57 |vpiDecompile:14'h10 @@ -151242,7 +151242,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:327:26, endln:327:59 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:327:53, endln:327:59 |vpiDecompile:14'h14 @@ -151254,7 +151254,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:328:26, endln:328:71 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:328:65, endln:328:71 |vpiDecompile:14'h18 @@ -151266,7 +151266,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:329:26, endln:329:68 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:329:62, endln:329:68 |vpiDecompile:14'h1c @@ -151278,7 +151278,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:330:26, endln:330:72 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:330:66, endln:330:72 |vpiDecompile:14'h20 @@ -151290,7 +151290,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:331:26, endln:331:72 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:331:66, endln:331:72 |vpiDecompile:14'h24 @@ -151302,7 +151302,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:332:26, endln:332:72 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:332:66, endln:332:72 |vpiDecompile:14'h28 @@ -151314,7 +151314,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:333:26, endln:333:72 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:333:66, endln:333:72 |vpiDecompile:14'h2c @@ -151326,7 +151326,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:334:26, endln:334:72 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:334:66, endln:334:72 |vpiDecompile:14'h30 @@ -151338,7 +151338,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:335:26, endln:335:71 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:335:65, endln:335:71 |vpiDecompile:14'h34 @@ -151350,7 +151350,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:336:26, endln:336:64 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:336:58, endln:336:64 |vpiDecompile:14'h38 @@ -151362,7 +151362,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:337:26, endln:337:63 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:337:57, endln:337:63 |vpiDecompile:14'h3c @@ -151374,7 +151374,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:338:26, endln:338:64 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:338:58, endln:338:64 |vpiDecompile:14'h40 @@ -151386,7 +151386,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:339:26, endln:339:73 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:339:67, endln:339:73 |vpiDecompile:14'h44 @@ -151398,7 +151398,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:340:26, endln:340:75 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:340:69, endln:340:75 |vpiDecompile:14'h48 @@ -151410,7 +151410,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:341:26, endln:341:75 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:341:69, endln:341:75 |vpiDecompile:14'h4c @@ -151422,7 +151422,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:342:26, endln:342:73 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:342:67, endln:342:73 |vpiDecompile:14'h50 @@ -151434,7 +151434,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:343:26, endln:343:74 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:343:68, endln:343:74 |vpiDecompile:14'h54 @@ -151446,7 +151446,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:344:26, endln:344:74 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:344:68, endln:344:74 |vpiDecompile:14'h58 @@ -151458,7 +151458,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:345:26, endln:345:72 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:345:66, endln:345:72 |vpiDecompile:14'h5c @@ -151470,7 +151470,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:346:26, endln:346:72 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:346:66, endln:346:72 |vpiDecompile:14'h60 @@ -151482,7 +151482,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:347:26, endln:347:66 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:347:60, endln:347:66 |vpiDecompile:14'h64 @@ -151494,7 +151494,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:348:26, endln:348:66 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:348:60, endln:348:66 |vpiDecompile:14'h68 @@ -151506,7 +151506,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:349:26, endln:349:67 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:349:61, endln:349:67 |vpiDecompile:14'h6c @@ -151518,7 +151518,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:350:26, endln:350:67 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:350:61, endln:350:67 |vpiDecompile:14'h70 @@ -151530,7 +151530,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:351:26, endln:351:67 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:351:61, endln:351:67 |vpiDecompile:14'h74 @@ -151542,7 +151542,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:352:26, endln:352:67 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:352:61, endln:352:67 |vpiDecompile:14'h78 @@ -151554,7 +151554,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:353:26, endln:353:67 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:353:61, endln:353:67 |vpiDecompile:14'h7c @@ -151566,7 +151566,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:354:26, endln:354:67 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:354:61, endln:354:67 |vpiDecompile:14'h80 @@ -151578,7 +151578,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:357:26, endln:357:66 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:357:58, endln:357:66 |vpiDecompile:14'h1000 @@ -151590,7 +151590,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:358:26, endln:358:65 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:358:58, endln:358:65 |vpiDecompile:14'h800 @@ -151602,7 +151602,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:359:26, endln:359:64 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:359:56, endln:359:64 |vpiDecompile:14'h2000 @@ -151614,7 +151614,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:360:26, endln:360:62 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:360:56, endln:360:62 |vpiDecompile:14'h40 @@ -151626,7 +151626,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:400:25, endln:434:4 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_operation: , line:400:48, endln:434:4 |vpiParent: @@ -151963,7 +151963,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:448:17, endln:448:34 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:448:32, endln:448:34 |vpiDecompile:64 @@ -151977,7 +151977,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:450:17, endln:450:46 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:450:32, endln:450:46 |vpiDecompile:3 @@ -151991,7 +151991,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:452:17, endln:452:63 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:452:37, endln:452:63 |vpiDecompile:9 @@ -152005,7 +152005,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:468:17, endln:468:32 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:468:31, endln:468:32 |vpiDecompile:3 @@ -152019,7 +152019,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:480:17, endln:480:38 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:480:36, endln:480:38 |vpiDecompile:16 @@ -152033,7 +152033,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:481:17, endln:481:73 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:481:36, endln:481:73 |vpiDecompile:10 @@ -152047,7 +152047,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:482:17, endln:482:51 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:482:36, endln:482:51 |vpiDecompile:1024 @@ -152061,7 +152061,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:483:17, endln:483:37 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:483:36, endln:483:37 |vpiDecompile:2 @@ -152075,7 +152075,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:484:17, endln:484:37 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:484:36, endln:484:37 |vpiDecompile:3 @@ -152089,7 +152089,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:485:17, endln:485:37 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:485:36, endln:485:37 |vpiDecompile:2 @@ -152103,7 +152103,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:486:17, endln:486:60 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:486:36, endln:486:60 |vpiDecompile:64 @@ -152117,7 +152117,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:488:17, endln:488:67 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:488:36, endln:488:67 |vpiDecompile:1 @@ -152131,7 +152131,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:505:17, endln:505:39 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:505:36, endln:505:39 |vpiDecompile:128 @@ -152145,7 +152145,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:506:17, endln:506:38 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:506:36, endln:506:38 |vpiDecompile:64 @@ -152159,7 +152159,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:508:17, endln:508:38 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:508:36, endln:508:38 |vpiDecompile:31 @@ -152173,7 +152173,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:509:17, endln:509:67 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:509:40, endln:509:67 |vpiDecompile:4 @@ -152187,7 +152187,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:520:17, endln:520:34 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:520:33, endln:520:34 |vpiDecompile:3 @@ -152201,7 +152201,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:521:17, endln:521:34 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:521:33, endln:521:34 |vpiDecompile:5 @@ -152215,7 +152215,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:522:17, endln:524:53 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:522:33, endln:524:53 |vpiDecompile:3 @@ -152229,7 +152229,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:587:27, endln:597:4 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_operation: , line:587:49, endln:597:4 |vpiParent: @@ -152464,7 +152464,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:625:17, endln:625:40 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:625:37, endln:625:40 |vpiDecompile:256 @@ -152478,7 +152478,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:626:17, endln:626:40 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:626:37, endln:626:40 |vpiDecompile:128 @@ -152492,7 +152492,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:627:17, endln:627:39 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:627:36, endln:627:39 |vpiDecompile:256 @@ -152506,7 +152506,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:628:17, endln:628:39 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:628:36, endln:628:39 |vpiDecompile:128 @@ -152520,7 +152520,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:629:17, endln:629:39 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:629:36, endln:629:39 |vpiDecompile:128 @@ -152534,7 +152534,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:630:17, endln:630:38 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:630:36, endln:630:38 |vpiDecompile:64 @@ -152548,7 +152548,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:631:17, endln:631:39 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:631:36, endln:631:39 |vpiDecompile:128 @@ -152562,7 +152562,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:632:17, endln:632:39 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:632:36, endln:632:39 |vpiDecompile:256 @@ -152576,7 +152576,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:645:30, endln:649:4 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_operation: , line:645:55, endln:649:4 |vpiParent: @@ -152707,7 +152707,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:672:33, endln:677:4 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_operation: , line:672:61, endln:677:4 |vpiParent: @@ -152842,7 +152842,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:728:18, endln:728:32 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:728:30, endln:728:32 |vpiDecompile:40 @@ -152856,7 +152856,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:731:26, endln:731:65 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:731:51, endln:731:65 |vpiDecompile:40'h453d28ea98 @@ -152868,7 +152868,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:732:26, endln:733:72 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:733:7, endln:733:72 |vpiDecompile:240'h4235171482c225f79289b32181a0163a760355d3447063d16661e44c12a5 @@ -152880,7 +152880,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:737:25, endln:741:4 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_operation: , line:737:45, endln:741:4 |vpiTypespec: @@ -153007,7 +153007,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:746:34, endln:752:4 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_operation: , line:746:62, endln:752:4 |vpiTypespec: @@ -153150,7 +153150,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:755:31, endln:761:4 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_operation: , line:755:56, endln:761:4 |vpiTypespec: @@ -153293,7 +153293,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:763:37, endln:764:42 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:764:5, endln:764:42 |vpiDecompile:128'hcbbd013ff15eba2f3065461eeb88463e @@ -153307,7 +153307,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:27:17, endln:27:39 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:27:38, endln:27:39 |vpiDecompile:2 @@ -153321,7 +153321,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:28:17, endln:28:38 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:28:36, endln:28:38 |vpiDecompile:11 @@ -153335,7 +153335,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:29:17, endln:29:36 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:29:35, endln:29:36 |vpiDecompile:9 @@ -153349,7 +153349,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:30:17, endln:30:32 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:30:31, endln:30:32 |vpiDecompile:2 @@ -153363,7 +153363,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:31:17, endln:31:35 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:31:34, endln:31:35 |vpiDecompile:2 @@ -153377,7 +153377,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:32:17, endln:32:42 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:32:39, endln:32:42 |vpiDecompile:512 @@ -153391,7 +153391,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:33:17, endln:33:41 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:33:39, endln:33:41 |vpiDecompile:16 @@ -153405,7 +153405,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:34:17, endln:34:28 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:34:27, endln:34:28 |vpiDecompile:7 @@ -153419,7 +153419,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:35:17, endln:35:39 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:35:38, endln:35:39 |vpiDecompile:0 @@ -153433,7 +153433,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:36:17, endln:36:39 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:36:36, endln:36:39 |vpiDecompile:768 @@ -153447,7 +153447,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:37:17, endln:37:46 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:37:45, endln:37:46 |vpiDecompile:0 @@ -153461,7 +153461,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:38:17, endln:38:46 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:38:43, endln:38:46 |vpiDecompile:760 @@ -153475,7 +153475,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:39:17, endln:39:47 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:39:44, endln:39:47 |vpiDecompile:760 @@ -153489,7 +153489,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:40:17, endln:40:43 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:40:42, endln:40:43 |vpiDecompile:8 @@ -153503,7 +153503,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:41:17, endln:41:39 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:41:36, endln:41:39 |vpiDecompile:768 @@ -153517,7 +153517,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:42:17, endln:42:37 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:42:34, endln:42:37 |vpiDecompile:768 @@ -153531,7 +153531,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:43:17, endln:43:46 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:43:43, endln:43:46 |vpiDecompile:768 @@ -153545,7 +153545,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:44:17, endln:44:44 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:44:41, endln:44:44 |vpiDecompile:760 @@ -153559,7 +153559,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:45:17, endln:45:46 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:45:42, endln:45:46 |vpiDecompile:1528 @@ -153573,7 +153573,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:46:17, endln:46:41 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:46:40, endln:46:41 |vpiDecompile:8 @@ -153587,7 +153587,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:47:17, endln:47:35 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:47:31, endln:47:35 |vpiDecompile:1536 @@ -153601,7 +153601,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:48:17, endln:48:32 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:48:29, endln:48:32 |vpiDecompile:208 @@ -153615,7 +153615,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:49:17, endln:49:38 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:49:34, endln:49:38 |vpiDecompile:1536 @@ -153629,7 +153629,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:50:17, endln:50:34 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:50:32, endln:50:34 |vpiDecompile:32 @@ -153643,7 +153643,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:51:17, endln:51:42 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:51:38, endln:51:42 |vpiDecompile:1568 @@ -153657,7 +153657,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:52:17, endln:52:39 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:52:36, endln:52:39 |vpiDecompile:168 @@ -153671,7 +153671,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:53:17, endln:53:41 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:53:37, endln:53:41 |vpiDecompile:1736 @@ -153685,7 +153685,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:54:17, endln:54:36 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:54:35, endln:54:36 |vpiDecompile:8 @@ -153699,7 +153699,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:55:17, endln:55:37 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:55:33, endln:55:37 |vpiDecompile:1744 @@ -153713,7 +153713,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:56:17, endln:56:33 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:56:31, endln:56:33 |vpiDecompile:40 @@ -153727,7 +153727,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:57:17, endln:57:45 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:57:41, endln:57:45 |vpiDecompile:1744 @@ -153741,7 +153741,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:58:17, endln:58:41 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:58:39, endln:58:41 |vpiDecompile:16 @@ -153755,7 +153755,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:59:17, endln:59:43 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:59:39, endln:59:43 |vpiDecompile:1760 @@ -153769,7 +153769,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:60:17, endln:60:39 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:60:37, endln:60:39 |vpiDecompile:16 @@ -153783,7 +153783,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:61:17, endln:61:43 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:61:39, endln:61:43 |vpiDecompile:1776 @@ -153797,7 +153797,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:62:17, endln:62:38 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:62:37, endln:62:38 |vpiDecompile:8 @@ -153811,7 +153811,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:63:17, endln:63:37 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:63:33, endln:63:37 |vpiDecompile:1784 @@ -153825,7 +153825,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:64:17, endln:64:33 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:64:31, endln:64:33 |vpiDecompile:88 @@ -153839,7 +153839,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:65:17, endln:65:46 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:65:42, endln:65:46 |vpiDecompile:1784 @@ -153853,7 +153853,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:66:17, endln:66:42 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:66:40, endln:66:42 |vpiDecompile:32 @@ -153867,7 +153867,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:67:17, endln:67:46 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:67:42, endln:67:46 |vpiDecompile:1816 @@ -153881,7 +153881,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:68:17, endln:68:42 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:68:40, endln:68:42 |vpiDecompile:32 @@ -153895,7 +153895,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:69:17, endln:69:45 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:69:41, endln:69:45 |vpiDecompile:1848 @@ -153909,7 +153909,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:70:17, endln:70:41 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:70:39, endln:70:41 |vpiDecompile:16 @@ -153923,7 +153923,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:71:17, endln:71:43 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:71:39, endln:71:43 |vpiDecompile:1864 @@ -153937,7 +153937,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:72:17, endln:72:38 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:72:37, endln:72:38 |vpiDecompile:8 @@ -153951,7 +153951,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:73:17, endln:73:37 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:73:33, endln:73:37 |vpiDecompile:1872 @@ -153965,7 +153965,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:74:17, endln:74:34 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:74:31, endln:74:34 |vpiDecompile:120 @@ -153979,7 +153979,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:75:17, endln:75:38 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:75:34, endln:75:38 |vpiDecompile:1872 @@ -153993,7 +153993,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:76:17, endln:76:34 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:76:32, endln:76:34 |vpiDecompile:16 @@ -154007,7 +154007,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:77:17, endln:77:50 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:77:46, endln:77:50 |vpiDecompile:1888 @@ -154021,7 +154021,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:78:17, endln:78:46 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:78:44, endln:78:46 |vpiDecompile:32 @@ -154035,7 +154035,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:79:17, endln:79:50 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:79:46, endln:79:50 |vpiDecompile:1920 @@ -154049,7 +154049,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:80:17, endln:80:46 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:80:44, endln:80:46 |vpiDecompile:32 @@ -154063,7 +154063,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:81:17, endln:81:43 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:81:39, endln:81:43 |vpiDecompile:1984 @@ -154077,7 +154077,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:82:17, endln:82:38 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:82:37, endln:82:38 |vpiDecompile:8 @@ -154091,7 +154091,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:83:17, endln:83:39 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:83:35, endln:83:39 |vpiDecompile:1992 @@ -154105,7 +154105,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:84:17, endln:84:35 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:84:33, endln:84:35 |vpiDecompile:56 @@ -154119,7 +154119,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:85:17, endln:85:37 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:85:33, endln:85:37 |vpiDecompile:1992 @@ -154133,7 +154133,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:86:17, endln:86:33 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:86:31, endln:86:33 |vpiDecompile:24 @@ -154147,7 +154147,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:87:17, endln:87:45 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:87:41, endln:87:45 |vpiDecompile:2016 @@ -154161,7 +154161,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:88:17, endln:88:41 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:88:39, endln:88:41 |vpiDecompile:32 @@ -154175,7 +154175,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:89:17, endln:89:30 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:89:29, endln:89:30 |vpiDecompile:2 @@ -154189,7 +154189,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:322:26, endln:322:60 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:322:55, endln:322:60 |vpiLhs: @@ -154197,7 +154197,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:323:26, endln:323:61 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:323:56, endln:323:61 |vpiLhs: @@ -154205,7 +154205,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:324:26, endln:324:59 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:324:54, endln:324:59 |vpiLhs: @@ -154213,7 +154213,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:325:26, endln:325:60 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:325:55, endln:325:60 |vpiLhs: @@ -154221,7 +154221,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:326:26, endln:326:57 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:326:51, endln:326:57 |vpiLhs: @@ -154229,7 +154229,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:327:26, endln:327:59 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:327:53, endln:327:59 |vpiLhs: @@ -154237,7 +154237,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:328:26, endln:328:71 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:328:65, endln:328:71 |vpiLhs: @@ -154245,7 +154245,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:329:26, endln:329:68 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:329:62, endln:329:68 |vpiLhs: @@ -154253,7 +154253,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:330:26, endln:330:72 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:330:66, endln:330:72 |vpiLhs: @@ -154261,7 +154261,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:331:26, endln:331:72 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:331:66, endln:331:72 |vpiLhs: @@ -154269,7 +154269,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:332:26, endln:332:72 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:332:66, endln:332:72 |vpiLhs: @@ -154277,7 +154277,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:333:26, endln:333:72 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:333:66, endln:333:72 |vpiLhs: @@ -154285,7 +154285,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:334:26, endln:334:72 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:334:66, endln:334:72 |vpiLhs: @@ -154293,7 +154293,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:335:26, endln:335:71 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:335:65, endln:335:71 |vpiLhs: @@ -154301,7 +154301,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:336:26, endln:336:64 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:336:58, endln:336:64 |vpiLhs: @@ -154309,7 +154309,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:337:26, endln:337:63 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:337:57, endln:337:63 |vpiLhs: @@ -154317,7 +154317,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:338:26, endln:338:64 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:338:58, endln:338:64 |vpiLhs: @@ -154325,7 +154325,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:339:26, endln:339:73 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:339:67, endln:339:73 |vpiLhs: @@ -154333,7 +154333,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:340:26, endln:340:75 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:340:69, endln:340:75 |vpiLhs: @@ -154341,7 +154341,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:341:26, endln:341:75 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:341:69, endln:341:75 |vpiLhs: @@ -154349,7 +154349,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:342:26, endln:342:73 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:342:67, endln:342:73 |vpiLhs: @@ -154357,7 +154357,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:343:26, endln:343:74 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:343:68, endln:343:74 |vpiLhs: @@ -154365,7 +154365,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:344:26, endln:344:74 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:344:68, endln:344:74 |vpiLhs: @@ -154373,7 +154373,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:345:26, endln:345:72 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:345:66, endln:345:72 |vpiLhs: @@ -154381,7 +154381,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:346:26, endln:346:72 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:346:66, endln:346:72 |vpiLhs: @@ -154389,7 +154389,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:347:26, endln:347:66 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:347:60, endln:347:66 |vpiLhs: @@ -154397,7 +154397,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:348:26, endln:348:66 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:348:60, endln:348:66 |vpiLhs: @@ -154405,7 +154405,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:349:26, endln:349:67 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:349:61, endln:349:67 |vpiLhs: @@ -154413,7 +154413,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:350:26, endln:350:67 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:350:61, endln:350:67 |vpiLhs: @@ -154421,7 +154421,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:351:26, endln:351:67 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:351:61, endln:351:67 |vpiLhs: @@ -154429,7 +154429,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:352:26, endln:352:67 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:352:61, endln:352:67 |vpiLhs: @@ -154437,7 +154437,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:353:26, endln:353:67 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:353:61, endln:353:67 |vpiLhs: @@ -154445,7 +154445,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:354:26, endln:354:67 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:354:61, endln:354:67 |vpiLhs: @@ -154453,7 +154453,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:357:26, endln:357:66 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:357:58, endln:357:66 |vpiLhs: @@ -154461,7 +154461,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:358:26, endln:358:65 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:358:58, endln:358:65 |vpiLhs: @@ -154469,7 +154469,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:359:26, endln:359:64 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:359:56, endln:359:64 |vpiLhs: @@ -154477,7 +154477,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:360:26, endln:360:62 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:360:56, endln:360:62 |vpiLhs: @@ -154485,7 +154485,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:400:25, endln:434:4 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_operation: , line:400:48, endln:434:4 |vpiParent: @@ -154822,7 +154822,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:27:17, endln:27:39 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:27:38, endln:27:39 |vpiDecompile:2 @@ -154836,7 +154836,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:28:17, endln:28:38 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:28:36, endln:28:38 |vpiDecompile:11 @@ -154850,7 +154850,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:29:17, endln:29:36 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:29:35, endln:29:36 |vpiDecompile:9 @@ -154864,7 +154864,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:30:17, endln:30:32 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:30:31, endln:30:32 |vpiDecompile:2 @@ -154878,7 +154878,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:31:17, endln:31:35 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:31:34, endln:31:35 |vpiDecompile:2 @@ -154892,7 +154892,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:32:17, endln:32:42 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:32:39, endln:32:42 |vpiDecompile:512 @@ -154906,7 +154906,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:33:17, endln:33:41 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:33:39, endln:33:41 |vpiDecompile:16 @@ -154920,7 +154920,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:34:17, endln:34:28 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:34:27, endln:34:28 |vpiDecompile:7 @@ -154934,7 +154934,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:35:17, endln:35:39 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:35:38, endln:35:39 |vpiDecompile:0 @@ -154948,7 +154948,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:36:17, endln:36:39 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:36:36, endln:36:39 |vpiDecompile:768 @@ -154962,7 +154962,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:37:17, endln:37:46 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:37:45, endln:37:46 |vpiDecompile:0 @@ -154976,7 +154976,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:38:17, endln:38:46 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:38:43, endln:38:46 |vpiDecompile:760 @@ -154990,7 +154990,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:39:17, endln:39:47 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:39:44, endln:39:47 |vpiDecompile:760 @@ -155004,7 +155004,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:40:17, endln:40:43 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:40:42, endln:40:43 |vpiDecompile:8 @@ -155018,7 +155018,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:41:17, endln:41:39 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:41:36, endln:41:39 |vpiDecompile:768 @@ -155032,7 +155032,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:42:17, endln:42:37 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:42:34, endln:42:37 |vpiDecompile:768 @@ -155046,7 +155046,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:43:17, endln:43:46 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:43:43, endln:43:46 |vpiDecompile:768 @@ -155060,7 +155060,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:44:17, endln:44:44 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:44:41, endln:44:44 |vpiDecompile:760 @@ -155074,7 +155074,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:45:17, endln:45:46 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:45:42, endln:45:46 |vpiDecompile:1528 @@ -155088,7 +155088,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:46:17, endln:46:41 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:46:40, endln:46:41 |vpiDecompile:8 @@ -155102,7 +155102,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:47:17, endln:47:35 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:47:31, endln:47:35 |vpiDecompile:1536 @@ -155116,7 +155116,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:48:17, endln:48:32 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:48:29, endln:48:32 |vpiDecompile:208 @@ -155130,7 +155130,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:49:17, endln:49:38 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:49:34, endln:49:38 |vpiDecompile:1536 @@ -155144,7 +155144,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:50:17, endln:50:34 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:50:32, endln:50:34 |vpiDecompile:32 @@ -155158,7 +155158,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:51:17, endln:51:42 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:51:38, endln:51:42 |vpiDecompile:1568 @@ -155172,7 +155172,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:52:17, endln:52:39 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:52:36, endln:52:39 |vpiDecompile:168 @@ -155186,7 +155186,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:53:17, endln:53:41 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:53:37, endln:53:41 |vpiDecompile:1736 @@ -155200,7 +155200,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:54:17, endln:54:36 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:54:35, endln:54:36 |vpiDecompile:8 @@ -155214,7 +155214,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:55:17, endln:55:37 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:55:33, endln:55:37 |vpiDecompile:1744 @@ -155228,7 +155228,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:56:17, endln:56:33 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:56:31, endln:56:33 |vpiDecompile:40 @@ -155242,7 +155242,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:57:17, endln:57:45 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:57:41, endln:57:45 |vpiDecompile:1744 @@ -155256,7 +155256,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:58:17, endln:58:41 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:58:39, endln:58:41 |vpiDecompile:16 @@ -155270,7 +155270,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:59:17, endln:59:43 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:59:39, endln:59:43 |vpiDecompile:1760 @@ -155284,7 +155284,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:60:17, endln:60:39 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:60:37, endln:60:39 |vpiDecompile:16 @@ -155298,7 +155298,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:61:17, endln:61:43 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:61:39, endln:61:43 |vpiDecompile:1776 @@ -155312,7 +155312,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:62:17, endln:62:38 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:62:37, endln:62:38 |vpiDecompile:8 @@ -155326,7 +155326,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:63:17, endln:63:37 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:63:33, endln:63:37 |vpiDecompile:1784 @@ -155340,7 +155340,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:64:17, endln:64:33 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:64:31, endln:64:33 |vpiDecompile:88 @@ -155354,7 +155354,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:65:17, endln:65:46 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:65:42, endln:65:46 |vpiDecompile:1784 @@ -155368,7 +155368,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:66:17, endln:66:42 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:66:40, endln:66:42 |vpiDecompile:32 @@ -155382,7 +155382,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:67:17, endln:67:46 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:67:42, endln:67:46 |vpiDecompile:1816 @@ -155396,7 +155396,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:68:17, endln:68:42 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:68:40, endln:68:42 |vpiDecompile:32 @@ -155410,7 +155410,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:69:17, endln:69:45 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:69:41, endln:69:45 |vpiDecompile:1848 @@ -155424,7 +155424,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:70:17, endln:70:41 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:70:39, endln:70:41 |vpiDecompile:16 @@ -155438,7 +155438,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:71:17, endln:71:43 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:71:39, endln:71:43 |vpiDecompile:1864 @@ -155452,7 +155452,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:72:17, endln:72:38 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:72:37, endln:72:38 |vpiDecompile:8 @@ -155466,7 +155466,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:73:17, endln:73:37 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:73:33, endln:73:37 |vpiDecompile:1872 @@ -155480,7 +155480,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:74:17, endln:74:34 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:74:31, endln:74:34 |vpiDecompile:120 @@ -155494,7 +155494,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:75:17, endln:75:38 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:75:34, endln:75:38 |vpiDecompile:1872 @@ -155508,7 +155508,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:76:17, endln:76:34 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:76:32, endln:76:34 |vpiDecompile:16 @@ -155522,7 +155522,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:77:17, endln:77:50 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:77:46, endln:77:50 |vpiDecompile:1888 @@ -155536,7 +155536,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:78:17, endln:78:46 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:78:44, endln:78:46 |vpiDecompile:32 @@ -155550,7 +155550,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:79:17, endln:79:50 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:79:46, endln:79:50 |vpiDecompile:1920 @@ -155564,7 +155564,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:80:17, endln:80:46 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:80:44, endln:80:46 |vpiDecompile:32 @@ -155578,7 +155578,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:81:17, endln:81:43 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:81:39, endln:81:43 |vpiDecompile:1984 @@ -155592,7 +155592,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:82:17, endln:82:38 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:82:37, endln:82:38 |vpiDecompile:8 @@ -155606,7 +155606,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:83:17, endln:83:39 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:83:35, endln:83:39 |vpiDecompile:1992 @@ -155620,7 +155620,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:84:17, endln:84:35 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:84:33, endln:84:35 |vpiDecompile:56 @@ -155634,7 +155634,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:85:17, endln:85:37 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:85:33, endln:85:37 |vpiDecompile:1992 @@ -155648,7 +155648,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:86:17, endln:86:33 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:86:31, endln:86:33 |vpiDecompile:24 @@ -155662,7 +155662,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:87:17, endln:87:45 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:87:41, endln:87:45 |vpiDecompile:2016 @@ -155676,7 +155676,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:88:17, endln:88:41 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:88:39, endln:88:41 |vpiDecompile:32 @@ -155690,7 +155690,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:89:17, endln:89:30 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:89:29, endln:89:30 |vpiDecompile:2 @@ -155704,7 +155704,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:322:26, endln:322:60 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:322:55, endln:322:60 |vpiLhs: @@ -155712,7 +155712,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:323:26, endln:323:61 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:323:56, endln:323:61 |vpiLhs: @@ -155720,7 +155720,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:324:26, endln:324:59 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:324:54, endln:324:59 |vpiLhs: @@ -155728,7 +155728,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:325:26, endln:325:60 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:325:55, endln:325:60 |vpiLhs: @@ -155736,7 +155736,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:326:26, endln:326:57 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:326:51, endln:326:57 |vpiLhs: @@ -155744,7 +155744,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:327:26, endln:327:59 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:327:53, endln:327:59 |vpiLhs: @@ -155752,7 +155752,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:328:26, endln:328:71 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:328:65, endln:328:71 |vpiLhs: @@ -155760,7 +155760,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:329:26, endln:329:68 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:329:62, endln:329:68 |vpiLhs: @@ -155768,7 +155768,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:330:26, endln:330:72 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:330:66, endln:330:72 |vpiLhs: @@ -155776,7 +155776,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:331:26, endln:331:72 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:331:66, endln:331:72 |vpiLhs: @@ -155784,7 +155784,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:332:26, endln:332:72 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:332:66, endln:332:72 |vpiLhs: @@ -155792,7 +155792,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:333:26, endln:333:72 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:333:66, endln:333:72 |vpiLhs: @@ -155800,7 +155800,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:334:26, endln:334:72 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:334:66, endln:334:72 |vpiLhs: @@ -155808,7 +155808,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:335:26, endln:335:71 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:335:65, endln:335:71 |vpiLhs: @@ -155816,7 +155816,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:336:26, endln:336:64 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:336:58, endln:336:64 |vpiLhs: @@ -155824,7 +155824,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:337:26, endln:337:63 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:337:57, endln:337:63 |vpiLhs: @@ -155832,7 +155832,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:338:26, endln:338:64 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:338:58, endln:338:64 |vpiLhs: @@ -155840,7 +155840,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:339:26, endln:339:73 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:339:67, endln:339:73 |vpiLhs: @@ -155848,7 +155848,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:340:26, endln:340:75 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:340:69, endln:340:75 |vpiLhs: @@ -155856,7 +155856,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:341:26, endln:341:75 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:341:69, endln:341:75 |vpiLhs: @@ -155864,7 +155864,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:342:26, endln:342:73 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:342:67, endln:342:73 |vpiLhs: @@ -155872,7 +155872,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:343:26, endln:343:74 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:343:68, endln:343:74 |vpiLhs: @@ -155880,7 +155880,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:344:26, endln:344:74 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:344:68, endln:344:74 |vpiLhs: @@ -155888,7 +155888,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:345:26, endln:345:72 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:345:66, endln:345:72 |vpiLhs: @@ -155896,7 +155896,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:346:26, endln:346:72 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:346:66, endln:346:72 |vpiLhs: @@ -155904,7 +155904,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:347:26, endln:347:66 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:347:60, endln:347:66 |vpiLhs: @@ -155912,7 +155912,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:348:26, endln:348:66 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:348:60, endln:348:66 |vpiLhs: @@ -155920,7 +155920,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:349:26, endln:349:67 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:349:61, endln:349:67 |vpiLhs: @@ -155928,7 +155928,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:350:26, endln:350:67 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:350:61, endln:350:67 |vpiLhs: @@ -155936,7 +155936,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:351:26, endln:351:67 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:351:61, endln:351:67 |vpiLhs: @@ -155944,7 +155944,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:352:26, endln:352:67 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:352:61, endln:352:67 |vpiLhs: @@ -155952,7 +155952,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:353:26, endln:353:67 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:353:61, endln:353:67 |vpiLhs: @@ -155960,7 +155960,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:354:26, endln:354:67 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:354:61, endln:354:67 |vpiLhs: @@ -155968,7 +155968,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:357:26, endln:357:66 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:357:58, endln:357:66 |vpiLhs: @@ -155976,7 +155976,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:358:26, endln:358:65 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:358:58, endln:358:65 |vpiLhs: @@ -155984,7 +155984,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:359:26, endln:359:64 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:359:56, endln:359:64 |vpiLhs: @@ -155992,7 +155992,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:360:26, endln:360:62 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:360:56, endln:360:62 |vpiLhs: @@ -156000,7 +156000,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:400:25, endln:434:4 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_operation: , line:400:48, endln:434:4 |vpiParent: @@ -156337,7 +156337,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:27:17, endln:27:39 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:27:38, endln:27:39 |vpiDecompile:2 @@ -156351,7 +156351,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:28:17, endln:28:38 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:28:36, endln:28:38 |vpiDecompile:11 @@ -156365,7 +156365,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:29:17, endln:29:36 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:29:35, endln:29:36 |vpiDecompile:9 @@ -156379,7 +156379,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:30:17, endln:30:32 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:30:31, endln:30:32 |vpiDecompile:2 @@ -156393,7 +156393,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:31:17, endln:31:35 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:31:34, endln:31:35 |vpiDecompile:2 @@ -156407,7 +156407,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:32:17, endln:32:42 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:32:39, endln:32:42 |vpiDecompile:512 @@ -156421,7 +156421,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:33:17, endln:33:41 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:33:39, endln:33:41 |vpiDecompile:16 @@ -156435,7 +156435,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:34:17, endln:34:28 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:34:27, endln:34:28 |vpiDecompile:7 @@ -156449,7 +156449,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:35:17, endln:35:39 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:35:38, endln:35:39 |vpiDecompile:0 @@ -156463,7 +156463,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:36:17, endln:36:39 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:36:36, endln:36:39 |vpiDecompile:768 @@ -156477,7 +156477,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:37:17, endln:37:46 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:37:45, endln:37:46 |vpiDecompile:0 @@ -156491,7 +156491,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:38:17, endln:38:46 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:38:43, endln:38:46 |vpiDecompile:760 @@ -156505,7 +156505,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:39:17, endln:39:47 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:39:44, endln:39:47 |vpiDecompile:760 @@ -156519,7 +156519,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:40:17, endln:40:43 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:40:42, endln:40:43 |vpiDecompile:8 @@ -156533,7 +156533,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:41:17, endln:41:39 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:41:36, endln:41:39 |vpiDecompile:768 @@ -156547,7 +156547,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:42:17, endln:42:37 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:42:34, endln:42:37 |vpiDecompile:768 @@ -156561,7 +156561,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:43:17, endln:43:46 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:43:43, endln:43:46 |vpiDecompile:768 @@ -156575,7 +156575,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:44:17, endln:44:44 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:44:41, endln:44:44 |vpiDecompile:760 @@ -156589,7 +156589,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:45:17, endln:45:46 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:45:42, endln:45:46 |vpiDecompile:1528 @@ -156603,7 +156603,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:46:17, endln:46:41 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:46:40, endln:46:41 |vpiDecompile:8 @@ -156617,7 +156617,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:47:17, endln:47:35 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:47:31, endln:47:35 |vpiDecompile:1536 @@ -156631,7 +156631,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:48:17, endln:48:32 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:48:29, endln:48:32 |vpiDecompile:208 @@ -156645,7 +156645,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:49:17, endln:49:38 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:49:34, endln:49:38 |vpiDecompile:1536 @@ -156659,7 +156659,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:50:17, endln:50:34 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:50:32, endln:50:34 |vpiDecompile:32 @@ -156673,7 +156673,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:51:17, endln:51:42 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:51:38, endln:51:42 |vpiDecompile:1568 @@ -156687,7 +156687,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:52:17, endln:52:39 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:52:36, endln:52:39 |vpiDecompile:168 @@ -156701,7 +156701,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:53:17, endln:53:41 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:53:37, endln:53:41 |vpiDecompile:1736 @@ -156715,7 +156715,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:54:17, endln:54:36 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:54:35, endln:54:36 |vpiDecompile:8 @@ -156729,7 +156729,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:55:17, endln:55:37 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:55:33, endln:55:37 |vpiDecompile:1744 @@ -156743,7 +156743,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:56:17, endln:56:33 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:56:31, endln:56:33 |vpiDecompile:40 @@ -156757,7 +156757,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:57:17, endln:57:45 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:57:41, endln:57:45 |vpiDecompile:1744 @@ -156771,7 +156771,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:58:17, endln:58:41 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:58:39, endln:58:41 |vpiDecompile:16 @@ -156785,7 +156785,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:59:17, endln:59:43 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:59:39, endln:59:43 |vpiDecompile:1760 @@ -156799,7 +156799,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:60:17, endln:60:39 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:60:37, endln:60:39 |vpiDecompile:16 @@ -156813,7 +156813,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:61:17, endln:61:43 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:61:39, endln:61:43 |vpiDecompile:1776 @@ -156827,7 +156827,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:62:17, endln:62:38 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:62:37, endln:62:38 |vpiDecompile:8 @@ -156841,7 +156841,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:63:17, endln:63:37 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:63:33, endln:63:37 |vpiDecompile:1784 @@ -156855,7 +156855,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:64:17, endln:64:33 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:64:31, endln:64:33 |vpiDecompile:88 @@ -156869,7 +156869,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:65:17, endln:65:46 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:65:42, endln:65:46 |vpiDecompile:1784 @@ -156883,7 +156883,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:66:17, endln:66:42 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:66:40, endln:66:42 |vpiDecompile:32 @@ -156897,7 +156897,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:67:17, endln:67:46 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:67:42, endln:67:46 |vpiDecompile:1816 @@ -156911,7 +156911,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:68:17, endln:68:42 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:68:40, endln:68:42 |vpiDecompile:32 @@ -156925,7 +156925,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:69:17, endln:69:45 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:69:41, endln:69:45 |vpiDecompile:1848 @@ -156939,7 +156939,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:70:17, endln:70:41 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:70:39, endln:70:41 |vpiDecompile:16 @@ -156953,7 +156953,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:71:17, endln:71:43 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:71:39, endln:71:43 |vpiDecompile:1864 @@ -156967,7 +156967,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:72:17, endln:72:38 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:72:37, endln:72:38 |vpiDecompile:8 @@ -156981,7 +156981,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:73:17, endln:73:37 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:73:33, endln:73:37 |vpiDecompile:1872 @@ -156995,7 +156995,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:74:17, endln:74:34 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:74:31, endln:74:34 |vpiDecompile:120 @@ -157009,7 +157009,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:75:17, endln:75:38 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:75:34, endln:75:38 |vpiDecompile:1872 @@ -157023,7 +157023,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:76:17, endln:76:34 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:76:32, endln:76:34 |vpiDecompile:16 @@ -157037,7 +157037,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:77:17, endln:77:50 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:77:46, endln:77:50 |vpiDecompile:1888 @@ -157051,7 +157051,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:78:17, endln:78:46 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:78:44, endln:78:46 |vpiDecompile:32 @@ -157065,7 +157065,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:79:17, endln:79:50 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:79:46, endln:79:50 |vpiDecompile:1920 @@ -157079,7 +157079,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:80:17, endln:80:46 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:80:44, endln:80:46 |vpiDecompile:32 @@ -157093,7 +157093,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:81:17, endln:81:43 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:81:39, endln:81:43 |vpiDecompile:1984 @@ -157107,7 +157107,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:82:17, endln:82:38 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:82:37, endln:82:38 |vpiDecompile:8 @@ -157121,7 +157121,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:83:17, endln:83:39 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:83:35, endln:83:39 |vpiDecompile:1992 @@ -157135,7 +157135,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:84:17, endln:84:35 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:84:33, endln:84:35 |vpiDecompile:56 @@ -157149,7 +157149,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:85:17, endln:85:37 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:85:33, endln:85:37 |vpiDecompile:1992 @@ -157163,7 +157163,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:86:17, endln:86:33 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:86:31, endln:86:33 |vpiDecompile:24 @@ -157177,7 +157177,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:87:17, endln:87:45 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:87:41, endln:87:45 |vpiDecompile:2016 @@ -157191,7 +157191,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:88:17, endln:88:41 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:88:39, endln:88:41 |vpiDecompile:32 @@ -157205,7 +157205,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:89:17, endln:89:30 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:89:29, endln:89:30 |vpiDecompile:2 @@ -157219,7 +157219,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:322:26, endln:322:60 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:322:55, endln:322:60 |vpiLhs: @@ -157227,7 +157227,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:323:26, endln:323:61 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:323:56, endln:323:61 |vpiLhs: @@ -157235,7 +157235,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:324:26, endln:324:59 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:324:54, endln:324:59 |vpiLhs: @@ -157243,7 +157243,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:325:26, endln:325:60 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:325:55, endln:325:60 |vpiLhs: @@ -157251,7 +157251,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:326:26, endln:326:57 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:326:51, endln:326:57 |vpiLhs: @@ -157259,7 +157259,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:327:26, endln:327:59 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:327:53, endln:327:59 |vpiLhs: @@ -157267,7 +157267,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:328:26, endln:328:71 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:328:65, endln:328:71 |vpiLhs: @@ -157275,7 +157275,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:329:26, endln:329:68 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:329:62, endln:329:68 |vpiLhs: @@ -157283,7 +157283,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:330:26, endln:330:72 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:330:66, endln:330:72 |vpiLhs: @@ -157291,7 +157291,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:331:26, endln:331:72 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:331:66, endln:331:72 |vpiLhs: @@ -157299,7 +157299,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:332:26, endln:332:72 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:332:66, endln:332:72 |vpiLhs: @@ -157307,7 +157307,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:333:26, endln:333:72 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:333:66, endln:333:72 |vpiLhs: @@ -157315,7 +157315,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:334:26, endln:334:72 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:334:66, endln:334:72 |vpiLhs: @@ -157323,7 +157323,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:335:26, endln:335:71 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:335:65, endln:335:71 |vpiLhs: @@ -157331,7 +157331,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:336:26, endln:336:64 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:336:58, endln:336:64 |vpiLhs: @@ -157339,7 +157339,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:337:26, endln:337:63 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:337:57, endln:337:63 |vpiLhs: @@ -157347,7 +157347,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:338:26, endln:338:64 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:338:58, endln:338:64 |vpiLhs: @@ -157355,7 +157355,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:339:26, endln:339:73 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:339:67, endln:339:73 |vpiLhs: @@ -157363,7 +157363,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:340:26, endln:340:75 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:340:69, endln:340:75 |vpiLhs: @@ -157371,7 +157371,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:341:26, endln:341:75 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:341:69, endln:341:75 |vpiLhs: @@ -157379,7 +157379,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:342:26, endln:342:73 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:342:67, endln:342:73 |vpiLhs: @@ -157387,7 +157387,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:343:26, endln:343:74 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:343:68, endln:343:74 |vpiLhs: @@ -157395,7 +157395,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:344:26, endln:344:74 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:344:68, endln:344:74 |vpiLhs: @@ -157403,7 +157403,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:345:26, endln:345:72 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:345:66, endln:345:72 |vpiLhs: @@ -157411,7 +157411,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:346:26, endln:346:72 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:346:66, endln:346:72 |vpiLhs: @@ -157419,7 +157419,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:347:26, endln:347:66 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:347:60, endln:347:66 |vpiLhs: @@ -157427,7 +157427,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:348:26, endln:348:66 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:348:60, endln:348:66 |vpiLhs: @@ -157435,7 +157435,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:349:26, endln:349:67 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:349:61, endln:349:67 |vpiLhs: @@ -157443,7 +157443,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:350:26, endln:350:67 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:350:61, endln:350:67 |vpiLhs: @@ -157451,7 +157451,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:351:26, endln:351:67 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:351:61, endln:351:67 |vpiLhs: @@ -157459,7 +157459,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:352:26, endln:352:67 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:352:61, endln:352:67 |vpiLhs: @@ -157467,7 +157467,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:353:26, endln:353:67 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:353:61, endln:353:67 |vpiLhs: @@ -157475,7 +157475,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:354:26, endln:354:67 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:354:61, endln:354:67 |vpiLhs: @@ -157483,7 +157483,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:357:26, endln:357:66 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:357:58, endln:357:66 |vpiLhs: @@ -157491,7 +157491,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:358:26, endln:358:65 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:358:58, endln:358:65 |vpiLhs: @@ -157499,7 +157499,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:359:26, endln:359:64 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:359:56, endln:359:64 |vpiLhs: @@ -157507,7 +157507,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:360:26, endln:360:62 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:360:56, endln:360:62 |vpiLhs: @@ -157515,7 +157515,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:400:25, endln:434:4 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_operation: , line:400:48, endln:434:4 |vpiParent: @@ -157852,7 +157852,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:448:17, endln:448:34 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:448:32, endln:448:34 |vpiDecompile:64 @@ -157866,7 +157866,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:450:17, endln:450:46 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:450:32, endln:450:46 |vpiDecompile:3 @@ -157880,7 +157880,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:452:17, endln:452:63 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:452:37, endln:452:63 |vpiDecompile:9 @@ -157894,7 +157894,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:468:17, endln:468:32 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:468:31, endln:468:32 |vpiDecompile:3 @@ -157908,7 +157908,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:480:17, endln:480:38 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:480:36, endln:480:38 |vpiDecompile:16 @@ -157922,7 +157922,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:481:17, endln:481:73 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:481:36, endln:481:73 |vpiDecompile:10 @@ -157936,7 +157936,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:482:17, endln:482:51 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:482:36, endln:482:51 |vpiDecompile:1024 @@ -157950,7 +157950,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:483:17, endln:483:37 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:483:36, endln:483:37 |vpiDecompile:2 @@ -157964,7 +157964,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:484:17, endln:484:37 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:484:36, endln:484:37 |vpiDecompile:3 @@ -157978,7 +157978,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:485:17, endln:485:37 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:485:36, endln:485:37 |vpiDecompile:2 @@ -157992,7 +157992,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:486:17, endln:486:60 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:486:36, endln:486:60 |vpiDecompile:64 @@ -158006,7 +158006,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:488:17, endln:488:67 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:488:36, endln:488:67 |vpiDecompile:1 @@ -158020,7 +158020,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:505:17, endln:505:39 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:505:36, endln:505:39 |vpiDecompile:128 @@ -158034,7 +158034,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:506:17, endln:506:38 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:506:36, endln:506:38 |vpiDecompile:64 @@ -158048,7 +158048,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:508:17, endln:508:38 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:508:36, endln:508:38 |vpiDecompile:31 @@ -158062,7 +158062,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:509:17, endln:509:67 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:509:40, endln:509:67 |vpiDecompile:4 @@ -158076,7 +158076,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:520:17, endln:520:34 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:520:33, endln:520:34 |vpiDecompile:3 @@ -158090,7 +158090,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:521:17, endln:521:34 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:521:33, endln:521:34 |vpiDecompile:5 @@ -158104,7 +158104,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:522:17, endln:524:53 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:522:33, endln:524:53 |vpiDecompile:3 @@ -158118,7 +158118,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:587:27, endln:597:4 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_operation: , line:587:49, endln:597:4 |vpiParent: @@ -158353,7 +158353,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:625:17, endln:625:40 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:625:37, endln:625:40 |vpiDecompile:256 @@ -158367,7 +158367,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:626:17, endln:626:40 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:626:37, endln:626:40 |vpiDecompile:128 @@ -158381,7 +158381,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:627:17, endln:627:39 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:627:36, endln:627:39 |vpiDecompile:256 @@ -158395,7 +158395,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:628:17, endln:628:39 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:628:36, endln:628:39 |vpiDecompile:128 @@ -158409,7 +158409,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:629:17, endln:629:39 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:629:36, endln:629:39 |vpiDecompile:128 @@ -158423,7 +158423,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:630:17, endln:630:38 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:630:36, endln:630:38 |vpiDecompile:64 @@ -158437,7 +158437,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:631:17, endln:631:39 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:631:36, endln:631:39 |vpiDecompile:128 @@ -158451,7 +158451,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:632:17, endln:632:39 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:632:36, endln:632:39 |vpiDecompile:256 @@ -158465,7 +158465,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:645:30, endln:649:4 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_operation: , line:645:55, endln:649:4 |vpiParent: @@ -158596,7 +158596,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:672:33, endln:677:4 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_operation: , line:672:61, endln:677:4 |vpiParent: @@ -158731,7 +158731,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:728:18, endln:728:32 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:728:30, endln:728:32 |vpiDecompile:40 @@ -158745,7 +158745,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:731:26, endln:731:65 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:731:51, endln:731:65 |vpiLhs: @@ -158753,7 +158753,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:732:26, endln:733:72 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:733:7, endln:733:72 |vpiLhs: @@ -158761,7 +158761,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:737:25, endln:741:4 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_operation: , line:737:45, endln:741:4 |vpiLhs: @@ -158769,7 +158769,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:746:34, endln:752:4 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_operation: , line:746:62, endln:752:4 |vpiLhs: @@ -158777,7 +158777,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:755:31, endln:761:4 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_operation: , line:755:56, endln:761:4 |vpiLhs: @@ -158785,7 +158785,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:763:37, endln:764:42 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_constant: , line:764:5, endln:764:42 |vpiDecompile:128'hcbbd013ff15eba2f3065461eeb88463e @@ -158799,7 +158799,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:795:26, endln:873:4 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiRhs: \_operation: , line:795:47, endln:873:4 |vpiParent: @@ -160248,7 +160248,7 @@ design: (work@otp_ctrl) |vpiTaskFunc: \_function: (otp_ctrl_pkg::vbits), line:14:1, endln:18:14 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiName:vbits |vpiFullName:otp_ctrl_pkg::vbits |vpiVisibility:1 @@ -160256,7 +160256,7 @@ design: (work@otp_ctrl) |vpiReturn: \_integer_var: , line:14:20, endln:14:27 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiIODecl: \_io_decl: (value), line:14:42, endln:14:47 |vpiParent: @@ -160307,12 +160307,12 @@ design: (work@otp_ctrl) |vpiFunction: \_function: (prim_util_pkg::_clog2), line:5:3, endln:12:14 |vpiInstance: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiTopModule:1 |vpiGenScopeArray: \_gen_scope_array: (work@otp_ctrl.gen_partitions[0]), line:882:39, endln:891:4 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiName:gen_partitions[0] |vpiFullName:work@otp_ctrl.gen_partitions[0] |vpiGenScope: @@ -160333,7 +160333,7 @@ design: (work@otp_ctrl) |vpiGenScopeArray: \_gen_scope_array: (work@otp_ctrl.gen_partitions[1]), line:882:39, endln:891:4 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiName:gen_partitions[1] |vpiFullName:work@otp_ctrl.gen_partitions[1] |vpiGenScope: @@ -160354,7 +160354,7 @@ design: (work@otp_ctrl) |vpiGenScopeArray: \_gen_scope_array: (work@otp_ctrl.gen_partitions[2]), line:882:39, endln:891:4 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiName:gen_partitions[2] |vpiFullName:work@otp_ctrl.gen_partitions[2] |vpiGenScope: @@ -160383,8 +160383,8 @@ design: (work@otp_ctrl) |vpiParent: \_gen_scope_array: (work@otp_ctrl.gen_partitions[2].gen_buffered), line:884:1, endln:889:4 |vpiFullName:work@otp_ctrl.gen_partitions[2].gen_buffered - |vpiModule: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + |vpiModuleInst: + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiParent: \_gen_scope: (work@otp_ctrl.gen_partitions[2].gen_buffered) |vpiName:u_part_buf @@ -164561,7 +164561,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:774:37, endln:774:59 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiOverriden:1 |vpiRhs: \_bit_select: (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf.PartInfo), line:886:15, endln:886:26 @@ -164590,7 +164590,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:786:18, endln:786:77 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_operation: , line:786:33, endln:786:77 |vpiParent: @@ -164654,7 +164654,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:27:17, endln:27:39 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:27:38, endln:27:39 |vpiDecompile:2 @@ -164668,7 +164668,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:28:17, endln:28:38 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:28:36, endln:28:38 |vpiDecompile:11 @@ -164682,7 +164682,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:29:17, endln:29:36 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:29:35, endln:29:36 |vpiDecompile:9 @@ -164696,7 +164696,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:30:17, endln:30:32 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:30:31, endln:30:32 |vpiDecompile:2 @@ -164710,7 +164710,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:31:17, endln:31:35 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:31:34, endln:31:35 |vpiDecompile:2 @@ -164724,7 +164724,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:32:17, endln:32:42 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:32:39, endln:32:42 |vpiDecompile:512 @@ -164738,7 +164738,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:33:17, endln:33:41 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:33:39, endln:33:41 |vpiDecompile:16 @@ -164752,7 +164752,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:34:17, endln:34:28 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:34:27, endln:34:28 |vpiDecompile:7 @@ -164766,7 +164766,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:35:17, endln:35:39 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:35:38, endln:35:39 |vpiDecompile:0 @@ -164780,7 +164780,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:36:17, endln:36:39 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:36:36, endln:36:39 |vpiDecompile:768 @@ -164794,7 +164794,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:37:17, endln:37:46 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:37:45, endln:37:46 |vpiDecompile:0 @@ -164808,7 +164808,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:38:17, endln:38:46 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:38:43, endln:38:46 |vpiDecompile:760 @@ -164822,7 +164822,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:39:17, endln:39:47 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:39:44, endln:39:47 |vpiDecompile:760 @@ -164836,7 +164836,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:40:17, endln:40:43 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:40:42, endln:40:43 |vpiDecompile:8 @@ -164850,7 +164850,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:41:17, endln:41:39 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:41:36, endln:41:39 |vpiDecompile:768 @@ -164864,7 +164864,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:42:17, endln:42:37 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:42:34, endln:42:37 |vpiDecompile:768 @@ -164878,7 +164878,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:43:17, endln:43:46 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:43:43, endln:43:46 |vpiDecompile:768 @@ -164892,7 +164892,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:44:17, endln:44:44 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:44:41, endln:44:44 |vpiDecompile:760 @@ -164906,7 +164906,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:45:17, endln:45:46 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:45:42, endln:45:46 |vpiDecompile:1528 @@ -164920,7 +164920,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:46:17, endln:46:41 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:46:40, endln:46:41 |vpiDecompile:8 @@ -164934,7 +164934,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:47:17, endln:47:35 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:47:31, endln:47:35 |vpiDecompile:1536 @@ -164948,7 +164948,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:48:17, endln:48:32 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:48:29, endln:48:32 |vpiDecompile:208 @@ -164962,7 +164962,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:49:17, endln:49:38 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:49:34, endln:49:38 |vpiDecompile:1536 @@ -164976,7 +164976,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:50:17, endln:50:34 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:50:32, endln:50:34 |vpiDecompile:32 @@ -164990,7 +164990,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:51:17, endln:51:42 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:51:38, endln:51:42 |vpiDecompile:1568 @@ -165004,7 +165004,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:52:17, endln:52:39 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:52:36, endln:52:39 |vpiDecompile:168 @@ -165018,7 +165018,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:53:17, endln:53:41 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:53:37, endln:53:41 |vpiDecompile:1736 @@ -165032,7 +165032,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:54:17, endln:54:36 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:54:35, endln:54:36 |vpiDecompile:8 @@ -165046,7 +165046,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:55:17, endln:55:37 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:55:33, endln:55:37 |vpiDecompile:1744 @@ -165060,7 +165060,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:56:17, endln:56:33 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:56:31, endln:56:33 |vpiDecompile:40 @@ -165074,7 +165074,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:57:17, endln:57:45 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:57:41, endln:57:45 |vpiDecompile:1744 @@ -165088,7 +165088,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:58:17, endln:58:41 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:58:39, endln:58:41 |vpiDecompile:16 @@ -165102,7 +165102,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:59:17, endln:59:43 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:59:39, endln:59:43 |vpiDecompile:1760 @@ -165116,7 +165116,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:60:17, endln:60:39 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:60:37, endln:60:39 |vpiDecompile:16 @@ -165130,7 +165130,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:61:17, endln:61:43 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:61:39, endln:61:43 |vpiDecompile:1776 @@ -165144,7 +165144,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:62:17, endln:62:38 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:62:37, endln:62:38 |vpiDecompile:8 @@ -165158,7 +165158,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:63:17, endln:63:37 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:63:33, endln:63:37 |vpiDecompile:1784 @@ -165172,7 +165172,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:64:17, endln:64:33 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:64:31, endln:64:33 |vpiDecompile:88 @@ -165186,7 +165186,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:65:17, endln:65:46 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:65:42, endln:65:46 |vpiDecompile:1784 @@ -165200,7 +165200,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:66:17, endln:66:42 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:66:40, endln:66:42 |vpiDecompile:32 @@ -165214,7 +165214,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:67:17, endln:67:46 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:67:42, endln:67:46 |vpiDecompile:1816 @@ -165228,7 +165228,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:68:17, endln:68:42 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:68:40, endln:68:42 |vpiDecompile:32 @@ -165242,7 +165242,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:69:17, endln:69:45 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:69:41, endln:69:45 |vpiDecompile:1848 @@ -165256,7 +165256,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:70:17, endln:70:41 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:70:39, endln:70:41 |vpiDecompile:16 @@ -165270,7 +165270,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:71:17, endln:71:43 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:71:39, endln:71:43 |vpiDecompile:1864 @@ -165284,7 +165284,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:72:17, endln:72:38 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:72:37, endln:72:38 |vpiDecompile:8 @@ -165298,7 +165298,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:73:17, endln:73:37 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:73:33, endln:73:37 |vpiDecompile:1872 @@ -165312,7 +165312,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:74:17, endln:74:34 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:74:31, endln:74:34 |vpiDecompile:120 @@ -165326,7 +165326,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:75:17, endln:75:38 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:75:34, endln:75:38 |vpiDecompile:1872 @@ -165340,7 +165340,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:76:17, endln:76:34 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:76:32, endln:76:34 |vpiDecompile:16 @@ -165354,7 +165354,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:77:17, endln:77:50 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:77:46, endln:77:50 |vpiDecompile:1888 @@ -165368,7 +165368,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:78:17, endln:78:46 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:78:44, endln:78:46 |vpiDecompile:32 @@ -165382,7 +165382,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:79:17, endln:79:50 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:79:46, endln:79:50 |vpiDecompile:1920 @@ -165396,7 +165396,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:80:17, endln:80:46 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:80:44, endln:80:46 |vpiDecompile:32 @@ -165410,7 +165410,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:81:17, endln:81:43 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:81:39, endln:81:43 |vpiDecompile:1984 @@ -165424,7 +165424,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:82:17, endln:82:38 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:82:37, endln:82:38 |vpiDecompile:8 @@ -165438,7 +165438,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:83:17, endln:83:39 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:83:35, endln:83:39 |vpiDecompile:1992 @@ -165452,7 +165452,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:84:17, endln:84:35 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:84:33, endln:84:35 |vpiDecompile:56 @@ -165466,7 +165466,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:85:17, endln:85:37 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:85:33, endln:85:37 |vpiDecompile:1992 @@ -165480,7 +165480,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:86:17, endln:86:33 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:86:31, endln:86:33 |vpiDecompile:24 @@ -165494,7 +165494,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:87:17, endln:87:45 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:87:41, endln:87:45 |vpiDecompile:2016 @@ -165508,7 +165508,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:88:17, endln:88:41 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:88:39, endln:88:41 |vpiDecompile:32 @@ -165522,7 +165522,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:89:17, endln:89:30 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:89:29, endln:89:30 |vpiDecompile:2 @@ -165536,7 +165536,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:322:26, endln:322:60 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:322:55, endln:322:60 |vpiDecompile:14'h0 @@ -165548,7 +165548,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:323:26, endln:323:61 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:323:56, endln:323:61 |vpiDecompile:14'h4 @@ -165560,7 +165560,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:324:26, endln:324:59 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:324:54, endln:324:59 |vpiDecompile:14'h8 @@ -165572,7 +165572,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:325:26, endln:325:60 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:325:55, endln:325:60 |vpiDecompile:14'hc @@ -165584,7 +165584,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:326:26, endln:326:57 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:326:51, endln:326:57 |vpiDecompile:14'h10 @@ -165596,7 +165596,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:327:26, endln:327:59 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:327:53, endln:327:59 |vpiDecompile:14'h14 @@ -165608,7 +165608,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:328:26, endln:328:71 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:328:65, endln:328:71 |vpiDecompile:14'h18 @@ -165620,7 +165620,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:329:26, endln:329:68 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:329:62, endln:329:68 |vpiDecompile:14'h1c @@ -165632,7 +165632,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:330:26, endln:330:72 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:330:66, endln:330:72 |vpiDecompile:14'h20 @@ -165644,7 +165644,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:331:26, endln:331:72 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:331:66, endln:331:72 |vpiDecompile:14'h24 @@ -165656,7 +165656,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:332:26, endln:332:72 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:332:66, endln:332:72 |vpiDecompile:14'h28 @@ -165668,7 +165668,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:333:26, endln:333:72 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:333:66, endln:333:72 |vpiDecompile:14'h2c @@ -165680,7 +165680,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:334:26, endln:334:72 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:334:66, endln:334:72 |vpiDecompile:14'h30 @@ -165692,7 +165692,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:335:26, endln:335:71 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:335:65, endln:335:71 |vpiDecompile:14'h34 @@ -165704,7 +165704,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:336:26, endln:336:64 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:336:58, endln:336:64 |vpiDecompile:14'h38 @@ -165716,7 +165716,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:337:26, endln:337:63 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:337:57, endln:337:63 |vpiDecompile:14'h3c @@ -165728,7 +165728,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:338:26, endln:338:64 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:338:58, endln:338:64 |vpiDecompile:14'h40 @@ -165740,7 +165740,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:339:26, endln:339:73 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:339:67, endln:339:73 |vpiDecompile:14'h44 @@ -165752,7 +165752,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:340:26, endln:340:75 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:340:69, endln:340:75 |vpiDecompile:14'h48 @@ -165764,7 +165764,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:341:26, endln:341:75 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:341:69, endln:341:75 |vpiDecompile:14'h4c @@ -165776,7 +165776,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:342:26, endln:342:73 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:342:67, endln:342:73 |vpiDecompile:14'h50 @@ -165788,7 +165788,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:343:26, endln:343:74 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:343:68, endln:343:74 |vpiDecompile:14'h54 @@ -165800,7 +165800,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:344:26, endln:344:74 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:344:68, endln:344:74 |vpiDecompile:14'h58 @@ -165812,7 +165812,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:345:26, endln:345:72 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:345:66, endln:345:72 |vpiDecompile:14'h5c @@ -165824,7 +165824,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:346:26, endln:346:72 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:346:66, endln:346:72 |vpiDecompile:14'h60 @@ -165836,7 +165836,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:347:26, endln:347:66 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:347:60, endln:347:66 |vpiDecompile:14'h64 @@ -165848,7 +165848,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:348:26, endln:348:66 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:348:60, endln:348:66 |vpiDecompile:14'h68 @@ -165860,7 +165860,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:349:26, endln:349:67 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:349:61, endln:349:67 |vpiDecompile:14'h6c @@ -165872,7 +165872,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:350:26, endln:350:67 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:350:61, endln:350:67 |vpiDecompile:14'h70 @@ -165884,7 +165884,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:351:26, endln:351:67 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:351:61, endln:351:67 |vpiDecompile:14'h74 @@ -165896,7 +165896,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:352:26, endln:352:67 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:352:61, endln:352:67 |vpiDecompile:14'h78 @@ -165908,7 +165908,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:353:26, endln:353:67 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:353:61, endln:353:67 |vpiDecompile:14'h7c @@ -165920,7 +165920,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:354:26, endln:354:67 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:354:61, endln:354:67 |vpiDecompile:14'h80 @@ -165932,7 +165932,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:357:26, endln:357:66 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:357:58, endln:357:66 |vpiDecompile:14'h1000 @@ -165944,7 +165944,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:358:26, endln:358:65 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:358:58, endln:358:65 |vpiDecompile:14'h800 @@ -165956,7 +165956,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:359:26, endln:359:64 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:359:56, endln:359:64 |vpiDecompile:14'h2000 @@ -165968,7 +165968,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:360:26, endln:360:62 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:360:56, endln:360:62 |vpiDecompile:14'h40 @@ -165980,7 +165980,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:400:25, endln:434:4 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_operation: , line:400:48, endln:434:4 |vpiParent: @@ -166317,7 +166317,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:448:17, endln:448:34 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:448:32, endln:448:34 |vpiDecompile:64 @@ -166331,7 +166331,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:450:17, endln:450:46 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:450:32, endln:450:46 |vpiDecompile:3 @@ -166345,7 +166345,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:452:17, endln:452:63 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:452:37, endln:452:63 |vpiDecompile:9 @@ -166359,7 +166359,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:468:17, endln:468:32 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:468:31, endln:468:32 |vpiDecompile:3 @@ -166373,7 +166373,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:480:17, endln:480:38 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:480:36, endln:480:38 |vpiDecompile:16 @@ -166387,7 +166387,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:481:17, endln:481:73 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:481:36, endln:481:73 |vpiDecompile:10 @@ -166401,7 +166401,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:482:17, endln:482:51 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:482:36, endln:482:51 |vpiDecompile:1024 @@ -166415,7 +166415,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:483:17, endln:483:37 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:483:36, endln:483:37 |vpiDecompile:2 @@ -166429,7 +166429,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:484:17, endln:484:37 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:484:36, endln:484:37 |vpiDecompile:3 @@ -166443,7 +166443,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:485:17, endln:485:37 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:485:36, endln:485:37 |vpiDecompile:2 @@ -166457,7 +166457,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:486:17, endln:486:60 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:486:36, endln:486:60 |vpiDecompile:64 @@ -166471,7 +166471,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:488:17, endln:488:67 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:488:36, endln:488:67 |vpiDecompile:1 @@ -166485,7 +166485,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:505:17, endln:505:39 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:505:36, endln:505:39 |vpiDecompile:128 @@ -166499,7 +166499,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:506:17, endln:506:38 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:506:36, endln:506:38 |vpiDecompile:64 @@ -166513,7 +166513,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:508:17, endln:508:38 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:508:36, endln:508:38 |vpiDecompile:31 @@ -166527,7 +166527,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:509:17, endln:509:67 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:509:40, endln:509:67 |vpiDecompile:4 @@ -166541,7 +166541,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:520:17, endln:520:34 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:520:33, endln:520:34 |vpiDecompile:3 @@ -166555,7 +166555,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:521:17, endln:521:34 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:521:33, endln:521:34 |vpiDecompile:5 @@ -166569,7 +166569,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:522:17, endln:524:53 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:522:33, endln:524:53 |vpiDecompile:3 @@ -166583,7 +166583,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:587:27, endln:597:4 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_operation: , line:587:49, endln:597:4 |vpiParent: @@ -166818,7 +166818,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:625:17, endln:625:40 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:625:37, endln:625:40 |vpiDecompile:256 @@ -166832,7 +166832,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:626:17, endln:626:40 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:626:37, endln:626:40 |vpiDecompile:128 @@ -166846,7 +166846,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:627:17, endln:627:39 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:627:36, endln:627:39 |vpiDecompile:256 @@ -166860,7 +166860,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:628:17, endln:628:39 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:628:36, endln:628:39 |vpiDecompile:128 @@ -166874,7 +166874,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:629:17, endln:629:39 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:629:36, endln:629:39 |vpiDecompile:128 @@ -166888,7 +166888,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:630:17, endln:630:38 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:630:36, endln:630:38 |vpiDecompile:64 @@ -166902,7 +166902,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:631:17, endln:631:39 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:631:36, endln:631:39 |vpiDecompile:128 @@ -166916,7 +166916,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:632:17, endln:632:39 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:632:36, endln:632:39 |vpiDecompile:256 @@ -166930,7 +166930,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:645:30, endln:649:4 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_operation: , line:645:55, endln:649:4 |vpiParent: @@ -167061,7 +167061,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:672:33, endln:677:4 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_operation: , line:672:61, endln:677:4 |vpiParent: @@ -167196,7 +167196,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:728:18, endln:728:32 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:728:30, endln:728:32 |vpiDecompile:40 @@ -167210,7 +167210,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:731:26, endln:731:65 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:731:51, endln:731:65 |vpiDecompile:40'h453d28ea98 @@ -167222,7 +167222,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:732:26, endln:733:72 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:733:7, endln:733:72 |vpiDecompile:240'h4235171482c225f79289b32181a0163a760355d3447063d16661e44c12a5 @@ -167234,7 +167234,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:737:25, endln:741:4 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_operation: , line:737:45, endln:741:4 |vpiParent: @@ -167363,7 +167363,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:746:34, endln:752:4 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_operation: , line:746:62, endln:752:4 |vpiParent: @@ -167508,7 +167508,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:755:31, endln:761:4 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_operation: , line:755:56, endln:761:4 |vpiParent: @@ -167653,7 +167653,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:763:37, endln:764:42 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:764:5, endln:764:42 |vpiDecompile:128'hcbbd013ff15eba2f3065461eeb88463e @@ -167667,7 +167667,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:27:17, endln:27:39 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:27:38, endln:27:39 |vpiDecompile:2 @@ -167681,7 +167681,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:28:17, endln:28:38 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:28:36, endln:28:38 |vpiDecompile:11 @@ -167695,7 +167695,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:29:17, endln:29:36 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:29:35, endln:29:36 |vpiDecompile:9 @@ -167709,7 +167709,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:30:17, endln:30:32 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:30:31, endln:30:32 |vpiDecompile:2 @@ -167723,7 +167723,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:31:17, endln:31:35 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:31:34, endln:31:35 |vpiDecompile:2 @@ -167737,7 +167737,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:32:17, endln:32:42 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:32:39, endln:32:42 |vpiDecompile:512 @@ -167751,7 +167751,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:33:17, endln:33:41 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:33:39, endln:33:41 |vpiDecompile:16 @@ -167765,7 +167765,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:34:17, endln:34:28 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:34:27, endln:34:28 |vpiDecompile:7 @@ -167779,7 +167779,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:35:17, endln:35:39 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:35:38, endln:35:39 |vpiDecompile:0 @@ -167793,7 +167793,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:36:17, endln:36:39 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:36:36, endln:36:39 |vpiDecompile:768 @@ -167807,7 +167807,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:37:17, endln:37:46 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:37:45, endln:37:46 |vpiDecompile:0 @@ -167821,7 +167821,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:38:17, endln:38:46 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:38:43, endln:38:46 |vpiDecompile:760 @@ -167835,7 +167835,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:39:17, endln:39:47 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:39:44, endln:39:47 |vpiDecompile:760 @@ -167849,7 +167849,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:40:17, endln:40:43 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:40:42, endln:40:43 |vpiDecompile:8 @@ -167863,7 +167863,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:41:17, endln:41:39 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:41:36, endln:41:39 |vpiDecompile:768 @@ -167877,7 +167877,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:42:17, endln:42:37 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:42:34, endln:42:37 |vpiDecompile:768 @@ -167891,7 +167891,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:43:17, endln:43:46 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:43:43, endln:43:46 |vpiDecompile:768 @@ -167905,7 +167905,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:44:17, endln:44:44 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:44:41, endln:44:44 |vpiDecompile:760 @@ -167919,7 +167919,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:45:17, endln:45:46 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:45:42, endln:45:46 |vpiDecompile:1528 @@ -167933,7 +167933,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:46:17, endln:46:41 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:46:40, endln:46:41 |vpiDecompile:8 @@ -167947,7 +167947,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:47:17, endln:47:35 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:47:31, endln:47:35 |vpiDecompile:1536 @@ -167961,7 +167961,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:48:17, endln:48:32 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:48:29, endln:48:32 |vpiDecompile:208 @@ -167975,7 +167975,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:49:17, endln:49:38 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:49:34, endln:49:38 |vpiDecompile:1536 @@ -167989,7 +167989,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:50:17, endln:50:34 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:50:32, endln:50:34 |vpiDecompile:32 @@ -168003,7 +168003,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:51:17, endln:51:42 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:51:38, endln:51:42 |vpiDecompile:1568 @@ -168017,7 +168017,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:52:17, endln:52:39 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:52:36, endln:52:39 |vpiDecompile:168 @@ -168031,7 +168031,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:53:17, endln:53:41 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:53:37, endln:53:41 |vpiDecompile:1736 @@ -168045,7 +168045,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:54:17, endln:54:36 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:54:35, endln:54:36 |vpiDecompile:8 @@ -168059,7 +168059,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:55:17, endln:55:37 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:55:33, endln:55:37 |vpiDecompile:1744 @@ -168073,7 +168073,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:56:17, endln:56:33 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:56:31, endln:56:33 |vpiDecompile:40 @@ -168087,7 +168087,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:57:17, endln:57:45 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:57:41, endln:57:45 |vpiDecompile:1744 @@ -168101,7 +168101,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:58:17, endln:58:41 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:58:39, endln:58:41 |vpiDecompile:16 @@ -168115,7 +168115,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:59:17, endln:59:43 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:59:39, endln:59:43 |vpiDecompile:1760 @@ -168129,7 +168129,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:60:17, endln:60:39 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:60:37, endln:60:39 |vpiDecompile:16 @@ -168143,7 +168143,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:61:17, endln:61:43 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:61:39, endln:61:43 |vpiDecompile:1776 @@ -168157,7 +168157,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:62:17, endln:62:38 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:62:37, endln:62:38 |vpiDecompile:8 @@ -168171,7 +168171,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:63:17, endln:63:37 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:63:33, endln:63:37 |vpiDecompile:1784 @@ -168185,7 +168185,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:64:17, endln:64:33 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:64:31, endln:64:33 |vpiDecompile:88 @@ -168199,7 +168199,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:65:17, endln:65:46 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:65:42, endln:65:46 |vpiDecompile:1784 @@ -168213,7 +168213,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:66:17, endln:66:42 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:66:40, endln:66:42 |vpiDecompile:32 @@ -168227,7 +168227,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:67:17, endln:67:46 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:67:42, endln:67:46 |vpiDecompile:1816 @@ -168241,7 +168241,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:68:17, endln:68:42 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:68:40, endln:68:42 |vpiDecompile:32 @@ -168255,7 +168255,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:69:17, endln:69:45 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:69:41, endln:69:45 |vpiDecompile:1848 @@ -168269,7 +168269,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:70:17, endln:70:41 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:70:39, endln:70:41 |vpiDecompile:16 @@ -168283,7 +168283,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:71:17, endln:71:43 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:71:39, endln:71:43 |vpiDecompile:1864 @@ -168297,7 +168297,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:72:17, endln:72:38 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:72:37, endln:72:38 |vpiDecompile:8 @@ -168311,7 +168311,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:73:17, endln:73:37 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:73:33, endln:73:37 |vpiDecompile:1872 @@ -168325,7 +168325,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:74:17, endln:74:34 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:74:31, endln:74:34 |vpiDecompile:120 @@ -168339,7 +168339,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:75:17, endln:75:38 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:75:34, endln:75:38 |vpiDecompile:1872 @@ -168353,7 +168353,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:76:17, endln:76:34 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:76:32, endln:76:34 |vpiDecompile:16 @@ -168367,7 +168367,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:77:17, endln:77:50 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:77:46, endln:77:50 |vpiDecompile:1888 @@ -168381,7 +168381,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:78:17, endln:78:46 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:78:44, endln:78:46 |vpiDecompile:32 @@ -168395,7 +168395,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:79:17, endln:79:50 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:79:46, endln:79:50 |vpiDecompile:1920 @@ -168409,7 +168409,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:80:17, endln:80:46 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:80:44, endln:80:46 |vpiDecompile:32 @@ -168423,7 +168423,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:81:17, endln:81:43 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:81:39, endln:81:43 |vpiDecompile:1984 @@ -168437,7 +168437,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:82:17, endln:82:38 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:82:37, endln:82:38 |vpiDecompile:8 @@ -168451,7 +168451,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:83:17, endln:83:39 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:83:35, endln:83:39 |vpiDecompile:1992 @@ -168465,7 +168465,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:84:17, endln:84:35 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:84:33, endln:84:35 |vpiDecompile:56 @@ -168479,7 +168479,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:85:17, endln:85:37 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:85:33, endln:85:37 |vpiDecompile:1992 @@ -168493,7 +168493,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:86:17, endln:86:33 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:86:31, endln:86:33 |vpiDecompile:24 @@ -168507,7 +168507,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:87:17, endln:87:45 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:87:41, endln:87:45 |vpiDecompile:2016 @@ -168521,7 +168521,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:88:17, endln:88:41 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:88:39, endln:88:41 |vpiDecompile:32 @@ -168535,7 +168535,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:89:17, endln:89:30 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:89:29, endln:89:30 |vpiDecompile:2 @@ -168549,7 +168549,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:322:26, endln:322:60 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:322:55, endln:322:60 |vpiLhs: @@ -168557,7 +168557,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:323:26, endln:323:61 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:323:56, endln:323:61 |vpiLhs: @@ -168565,7 +168565,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:324:26, endln:324:59 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:324:54, endln:324:59 |vpiLhs: @@ -168573,7 +168573,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:325:26, endln:325:60 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:325:55, endln:325:60 |vpiLhs: @@ -168581,7 +168581,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:326:26, endln:326:57 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:326:51, endln:326:57 |vpiLhs: @@ -168589,7 +168589,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:327:26, endln:327:59 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:327:53, endln:327:59 |vpiLhs: @@ -168597,7 +168597,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:328:26, endln:328:71 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:328:65, endln:328:71 |vpiLhs: @@ -168605,7 +168605,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:329:26, endln:329:68 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:329:62, endln:329:68 |vpiLhs: @@ -168613,7 +168613,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:330:26, endln:330:72 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:330:66, endln:330:72 |vpiLhs: @@ -168621,7 +168621,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:331:26, endln:331:72 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:331:66, endln:331:72 |vpiLhs: @@ -168629,7 +168629,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:332:26, endln:332:72 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:332:66, endln:332:72 |vpiLhs: @@ -168637,7 +168637,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:333:26, endln:333:72 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:333:66, endln:333:72 |vpiLhs: @@ -168645,7 +168645,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:334:26, endln:334:72 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:334:66, endln:334:72 |vpiLhs: @@ -168653,7 +168653,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:335:26, endln:335:71 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:335:65, endln:335:71 |vpiLhs: @@ -168661,7 +168661,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:336:26, endln:336:64 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:336:58, endln:336:64 |vpiLhs: @@ -168669,7 +168669,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:337:26, endln:337:63 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:337:57, endln:337:63 |vpiLhs: @@ -168677,7 +168677,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:338:26, endln:338:64 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:338:58, endln:338:64 |vpiLhs: @@ -168685,7 +168685,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:339:26, endln:339:73 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:339:67, endln:339:73 |vpiLhs: @@ -168693,7 +168693,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:340:26, endln:340:75 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:340:69, endln:340:75 |vpiLhs: @@ -168701,7 +168701,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:341:26, endln:341:75 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:341:69, endln:341:75 |vpiLhs: @@ -168709,7 +168709,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:342:26, endln:342:73 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:342:67, endln:342:73 |vpiLhs: @@ -168717,7 +168717,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:343:26, endln:343:74 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:343:68, endln:343:74 |vpiLhs: @@ -168725,7 +168725,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:344:26, endln:344:74 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:344:68, endln:344:74 |vpiLhs: @@ -168733,7 +168733,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:345:26, endln:345:72 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:345:66, endln:345:72 |vpiLhs: @@ -168741,7 +168741,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:346:26, endln:346:72 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:346:66, endln:346:72 |vpiLhs: @@ -168749,7 +168749,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:347:26, endln:347:66 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:347:60, endln:347:66 |vpiLhs: @@ -168757,7 +168757,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:348:26, endln:348:66 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:348:60, endln:348:66 |vpiLhs: @@ -168765,7 +168765,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:349:26, endln:349:67 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:349:61, endln:349:67 |vpiLhs: @@ -168773,7 +168773,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:350:26, endln:350:67 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:350:61, endln:350:67 |vpiLhs: @@ -168781,7 +168781,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:351:26, endln:351:67 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:351:61, endln:351:67 |vpiLhs: @@ -168789,7 +168789,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:352:26, endln:352:67 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:352:61, endln:352:67 |vpiLhs: @@ -168797,7 +168797,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:353:26, endln:353:67 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:353:61, endln:353:67 |vpiLhs: @@ -168805,7 +168805,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:354:26, endln:354:67 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:354:61, endln:354:67 |vpiLhs: @@ -168813,7 +168813,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:357:26, endln:357:66 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:357:58, endln:357:66 |vpiLhs: @@ -168821,7 +168821,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:358:26, endln:358:65 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:358:58, endln:358:65 |vpiLhs: @@ -168829,7 +168829,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:359:26, endln:359:64 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:359:56, endln:359:64 |vpiLhs: @@ -168837,7 +168837,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:360:26, endln:360:62 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:360:56, endln:360:62 |vpiLhs: @@ -168845,7 +168845,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:400:25, endln:434:4 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_operation: , line:400:48, endln:434:4 |vpiParent: @@ -169317,7 +169317,7 @@ design: (work@otp_ctrl) |vpiTaskFunc: \_function: (otp_ctrl_pkg::vbits), line:14:1, endln:18:14 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiName:vbits |vpiFullName:otp_ctrl_pkg::vbits |vpiVisibility:1 @@ -169325,7 +169325,7 @@ design: (work@otp_ctrl) |vpiReturn: \_integer_var: , line:14:20, endln:14:27 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiIODecl: \_io_decl: (value), line:14:42, endln:14:47 |vpiParent: @@ -169376,11 +169376,11 @@ design: (work@otp_ctrl) |vpiFunction: \_function: (prim_util_pkg::_clog2), line:5:3, endln:12:14 |vpiInstance: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[2].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiGenScopeArray: \_gen_scope_array: (work@otp_ctrl.gen_partitions[3]), line:882:39, endln:891:4 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiName:gen_partitions[3] |vpiFullName:work@otp_ctrl.gen_partitions[3] |vpiGenScope: @@ -169409,8 +169409,8 @@ design: (work@otp_ctrl) |vpiParent: \_gen_scope_array: (work@otp_ctrl.gen_partitions[3].gen_buffered), line:884:1, endln:889:4 |vpiFullName:work@otp_ctrl.gen_partitions[3].gen_buffered - |vpiModule: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + |vpiModuleInst: + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiParent: \_gen_scope: (work@otp_ctrl.gen_partitions[3].gen_buffered) |vpiName:u_part_buf @@ -173587,7 +173587,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:774:37, endln:774:59 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiOverriden:1 |vpiRhs: \_bit_select: (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf.PartInfo), line:886:15, endln:886:26 @@ -173616,7 +173616,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:786:18, endln:786:77 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_operation: , line:786:33, endln:786:77 |vpiParent: @@ -173680,7 +173680,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:27:17, endln:27:39 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:27:38, endln:27:39 |vpiDecompile:2 @@ -173694,7 +173694,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:28:17, endln:28:38 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:28:36, endln:28:38 |vpiDecompile:11 @@ -173708,7 +173708,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:29:17, endln:29:36 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:29:35, endln:29:36 |vpiDecompile:9 @@ -173722,7 +173722,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:30:17, endln:30:32 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:30:31, endln:30:32 |vpiDecompile:2 @@ -173736,7 +173736,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:31:17, endln:31:35 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:31:34, endln:31:35 |vpiDecompile:2 @@ -173750,7 +173750,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:32:17, endln:32:42 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:32:39, endln:32:42 |vpiDecompile:512 @@ -173764,7 +173764,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:33:17, endln:33:41 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:33:39, endln:33:41 |vpiDecompile:16 @@ -173778,7 +173778,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:34:17, endln:34:28 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:34:27, endln:34:28 |vpiDecompile:7 @@ -173792,7 +173792,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:35:17, endln:35:39 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:35:38, endln:35:39 |vpiDecompile:0 @@ -173806,7 +173806,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:36:17, endln:36:39 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:36:36, endln:36:39 |vpiDecompile:768 @@ -173820,7 +173820,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:37:17, endln:37:46 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:37:45, endln:37:46 |vpiDecompile:0 @@ -173834,7 +173834,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:38:17, endln:38:46 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:38:43, endln:38:46 |vpiDecompile:760 @@ -173848,7 +173848,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:39:17, endln:39:47 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:39:44, endln:39:47 |vpiDecompile:760 @@ -173862,7 +173862,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:40:17, endln:40:43 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:40:42, endln:40:43 |vpiDecompile:8 @@ -173876,7 +173876,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:41:17, endln:41:39 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:41:36, endln:41:39 |vpiDecompile:768 @@ -173890,7 +173890,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:42:17, endln:42:37 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:42:34, endln:42:37 |vpiDecompile:768 @@ -173904,7 +173904,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:43:17, endln:43:46 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:43:43, endln:43:46 |vpiDecompile:768 @@ -173918,7 +173918,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:44:17, endln:44:44 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:44:41, endln:44:44 |vpiDecompile:760 @@ -173932,7 +173932,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:45:17, endln:45:46 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:45:42, endln:45:46 |vpiDecompile:1528 @@ -173946,7 +173946,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:46:17, endln:46:41 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:46:40, endln:46:41 |vpiDecompile:8 @@ -173960,7 +173960,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:47:17, endln:47:35 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:47:31, endln:47:35 |vpiDecompile:1536 @@ -173974,7 +173974,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:48:17, endln:48:32 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:48:29, endln:48:32 |vpiDecompile:208 @@ -173988,7 +173988,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:49:17, endln:49:38 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:49:34, endln:49:38 |vpiDecompile:1536 @@ -174002,7 +174002,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:50:17, endln:50:34 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:50:32, endln:50:34 |vpiDecompile:32 @@ -174016,7 +174016,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:51:17, endln:51:42 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:51:38, endln:51:42 |vpiDecompile:1568 @@ -174030,7 +174030,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:52:17, endln:52:39 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:52:36, endln:52:39 |vpiDecompile:168 @@ -174044,7 +174044,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:53:17, endln:53:41 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:53:37, endln:53:41 |vpiDecompile:1736 @@ -174058,7 +174058,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:54:17, endln:54:36 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:54:35, endln:54:36 |vpiDecompile:8 @@ -174072,7 +174072,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:55:17, endln:55:37 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:55:33, endln:55:37 |vpiDecompile:1744 @@ -174086,7 +174086,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:56:17, endln:56:33 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:56:31, endln:56:33 |vpiDecompile:40 @@ -174100,7 +174100,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:57:17, endln:57:45 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:57:41, endln:57:45 |vpiDecompile:1744 @@ -174114,7 +174114,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:58:17, endln:58:41 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:58:39, endln:58:41 |vpiDecompile:16 @@ -174128,7 +174128,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:59:17, endln:59:43 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:59:39, endln:59:43 |vpiDecompile:1760 @@ -174142,7 +174142,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:60:17, endln:60:39 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:60:37, endln:60:39 |vpiDecompile:16 @@ -174156,7 +174156,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:61:17, endln:61:43 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:61:39, endln:61:43 |vpiDecompile:1776 @@ -174170,7 +174170,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:62:17, endln:62:38 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:62:37, endln:62:38 |vpiDecompile:8 @@ -174184,7 +174184,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:63:17, endln:63:37 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:63:33, endln:63:37 |vpiDecompile:1784 @@ -174198,7 +174198,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:64:17, endln:64:33 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:64:31, endln:64:33 |vpiDecompile:88 @@ -174212,7 +174212,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:65:17, endln:65:46 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:65:42, endln:65:46 |vpiDecompile:1784 @@ -174226,7 +174226,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:66:17, endln:66:42 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:66:40, endln:66:42 |vpiDecompile:32 @@ -174240,7 +174240,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:67:17, endln:67:46 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:67:42, endln:67:46 |vpiDecompile:1816 @@ -174254,7 +174254,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:68:17, endln:68:42 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:68:40, endln:68:42 |vpiDecompile:32 @@ -174268,7 +174268,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:69:17, endln:69:45 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:69:41, endln:69:45 |vpiDecompile:1848 @@ -174282,7 +174282,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:70:17, endln:70:41 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:70:39, endln:70:41 |vpiDecompile:16 @@ -174296,7 +174296,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:71:17, endln:71:43 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:71:39, endln:71:43 |vpiDecompile:1864 @@ -174310,7 +174310,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:72:17, endln:72:38 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:72:37, endln:72:38 |vpiDecompile:8 @@ -174324,7 +174324,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:73:17, endln:73:37 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:73:33, endln:73:37 |vpiDecompile:1872 @@ -174338,7 +174338,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:74:17, endln:74:34 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:74:31, endln:74:34 |vpiDecompile:120 @@ -174352,7 +174352,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:75:17, endln:75:38 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:75:34, endln:75:38 |vpiDecompile:1872 @@ -174366,7 +174366,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:76:17, endln:76:34 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:76:32, endln:76:34 |vpiDecompile:16 @@ -174380,7 +174380,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:77:17, endln:77:50 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:77:46, endln:77:50 |vpiDecompile:1888 @@ -174394,7 +174394,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:78:17, endln:78:46 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:78:44, endln:78:46 |vpiDecompile:32 @@ -174408,7 +174408,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:79:17, endln:79:50 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:79:46, endln:79:50 |vpiDecompile:1920 @@ -174422,7 +174422,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:80:17, endln:80:46 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:80:44, endln:80:46 |vpiDecompile:32 @@ -174436,7 +174436,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:81:17, endln:81:43 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:81:39, endln:81:43 |vpiDecompile:1984 @@ -174450,7 +174450,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:82:17, endln:82:38 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:82:37, endln:82:38 |vpiDecompile:8 @@ -174464,7 +174464,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:83:17, endln:83:39 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:83:35, endln:83:39 |vpiDecompile:1992 @@ -174478,7 +174478,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:84:17, endln:84:35 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:84:33, endln:84:35 |vpiDecompile:56 @@ -174492,7 +174492,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:85:17, endln:85:37 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:85:33, endln:85:37 |vpiDecompile:1992 @@ -174506,7 +174506,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:86:17, endln:86:33 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:86:31, endln:86:33 |vpiDecompile:24 @@ -174520,7 +174520,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:87:17, endln:87:45 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:87:41, endln:87:45 |vpiDecompile:2016 @@ -174534,7 +174534,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:88:17, endln:88:41 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:88:39, endln:88:41 |vpiDecompile:32 @@ -174548,7 +174548,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:89:17, endln:89:30 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:89:29, endln:89:30 |vpiDecompile:2 @@ -174562,7 +174562,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:322:26, endln:322:60 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:322:55, endln:322:60 |vpiDecompile:14'h0 @@ -174574,7 +174574,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:323:26, endln:323:61 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:323:56, endln:323:61 |vpiDecompile:14'h4 @@ -174586,7 +174586,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:324:26, endln:324:59 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:324:54, endln:324:59 |vpiDecompile:14'h8 @@ -174598,7 +174598,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:325:26, endln:325:60 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:325:55, endln:325:60 |vpiDecompile:14'hc @@ -174610,7 +174610,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:326:26, endln:326:57 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:326:51, endln:326:57 |vpiDecompile:14'h10 @@ -174622,7 +174622,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:327:26, endln:327:59 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:327:53, endln:327:59 |vpiDecompile:14'h14 @@ -174634,7 +174634,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:328:26, endln:328:71 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:328:65, endln:328:71 |vpiDecompile:14'h18 @@ -174646,7 +174646,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:329:26, endln:329:68 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:329:62, endln:329:68 |vpiDecompile:14'h1c @@ -174658,7 +174658,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:330:26, endln:330:72 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:330:66, endln:330:72 |vpiDecompile:14'h20 @@ -174670,7 +174670,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:331:26, endln:331:72 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:331:66, endln:331:72 |vpiDecompile:14'h24 @@ -174682,7 +174682,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:332:26, endln:332:72 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:332:66, endln:332:72 |vpiDecompile:14'h28 @@ -174694,7 +174694,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:333:26, endln:333:72 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:333:66, endln:333:72 |vpiDecompile:14'h2c @@ -174706,7 +174706,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:334:26, endln:334:72 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:334:66, endln:334:72 |vpiDecompile:14'h30 @@ -174718,7 +174718,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:335:26, endln:335:71 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:335:65, endln:335:71 |vpiDecompile:14'h34 @@ -174730,7 +174730,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:336:26, endln:336:64 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:336:58, endln:336:64 |vpiDecompile:14'h38 @@ -174742,7 +174742,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:337:26, endln:337:63 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:337:57, endln:337:63 |vpiDecompile:14'h3c @@ -174754,7 +174754,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:338:26, endln:338:64 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:338:58, endln:338:64 |vpiDecompile:14'h40 @@ -174766,7 +174766,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:339:26, endln:339:73 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:339:67, endln:339:73 |vpiDecompile:14'h44 @@ -174778,7 +174778,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:340:26, endln:340:75 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:340:69, endln:340:75 |vpiDecompile:14'h48 @@ -174790,7 +174790,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:341:26, endln:341:75 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:341:69, endln:341:75 |vpiDecompile:14'h4c @@ -174802,7 +174802,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:342:26, endln:342:73 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:342:67, endln:342:73 |vpiDecompile:14'h50 @@ -174814,7 +174814,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:343:26, endln:343:74 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:343:68, endln:343:74 |vpiDecompile:14'h54 @@ -174826,7 +174826,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:344:26, endln:344:74 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:344:68, endln:344:74 |vpiDecompile:14'h58 @@ -174838,7 +174838,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:345:26, endln:345:72 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:345:66, endln:345:72 |vpiDecompile:14'h5c @@ -174850,7 +174850,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:346:26, endln:346:72 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:346:66, endln:346:72 |vpiDecompile:14'h60 @@ -174862,7 +174862,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:347:26, endln:347:66 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:347:60, endln:347:66 |vpiDecompile:14'h64 @@ -174874,7 +174874,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:348:26, endln:348:66 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:348:60, endln:348:66 |vpiDecompile:14'h68 @@ -174886,7 +174886,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:349:26, endln:349:67 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:349:61, endln:349:67 |vpiDecompile:14'h6c @@ -174898,7 +174898,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:350:26, endln:350:67 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:350:61, endln:350:67 |vpiDecompile:14'h70 @@ -174910,7 +174910,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:351:26, endln:351:67 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:351:61, endln:351:67 |vpiDecompile:14'h74 @@ -174922,7 +174922,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:352:26, endln:352:67 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:352:61, endln:352:67 |vpiDecompile:14'h78 @@ -174934,7 +174934,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:353:26, endln:353:67 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:353:61, endln:353:67 |vpiDecompile:14'h7c @@ -174946,7 +174946,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:354:26, endln:354:67 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:354:61, endln:354:67 |vpiDecompile:14'h80 @@ -174958,7 +174958,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:357:26, endln:357:66 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:357:58, endln:357:66 |vpiDecompile:14'h1000 @@ -174970,7 +174970,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:358:26, endln:358:65 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:358:58, endln:358:65 |vpiDecompile:14'h800 @@ -174982,7 +174982,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:359:26, endln:359:64 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:359:56, endln:359:64 |vpiDecompile:14'h2000 @@ -174994,7 +174994,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:360:26, endln:360:62 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:360:56, endln:360:62 |vpiDecompile:14'h40 @@ -175006,7 +175006,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:400:25, endln:434:4 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_operation: , line:400:48, endln:434:4 |vpiParent: @@ -175343,7 +175343,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:448:17, endln:448:34 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:448:32, endln:448:34 |vpiDecompile:64 @@ -175357,7 +175357,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:450:17, endln:450:46 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:450:32, endln:450:46 |vpiDecompile:3 @@ -175371,7 +175371,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:452:17, endln:452:63 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:452:37, endln:452:63 |vpiDecompile:9 @@ -175385,7 +175385,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:468:17, endln:468:32 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:468:31, endln:468:32 |vpiDecompile:3 @@ -175399,7 +175399,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:480:17, endln:480:38 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:480:36, endln:480:38 |vpiDecompile:16 @@ -175413,7 +175413,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:481:17, endln:481:73 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:481:36, endln:481:73 |vpiDecompile:10 @@ -175427,7 +175427,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:482:17, endln:482:51 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:482:36, endln:482:51 |vpiDecompile:1024 @@ -175441,7 +175441,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:483:17, endln:483:37 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:483:36, endln:483:37 |vpiDecompile:2 @@ -175455,7 +175455,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:484:17, endln:484:37 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:484:36, endln:484:37 |vpiDecompile:3 @@ -175469,7 +175469,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:485:17, endln:485:37 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:485:36, endln:485:37 |vpiDecompile:2 @@ -175483,7 +175483,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:486:17, endln:486:60 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:486:36, endln:486:60 |vpiDecompile:64 @@ -175497,7 +175497,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:488:17, endln:488:67 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:488:36, endln:488:67 |vpiDecompile:1 @@ -175511,7 +175511,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:505:17, endln:505:39 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:505:36, endln:505:39 |vpiDecompile:128 @@ -175525,7 +175525,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:506:17, endln:506:38 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:506:36, endln:506:38 |vpiDecompile:64 @@ -175539,7 +175539,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:508:17, endln:508:38 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:508:36, endln:508:38 |vpiDecompile:31 @@ -175553,7 +175553,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:509:17, endln:509:67 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:509:40, endln:509:67 |vpiDecompile:4 @@ -175567,7 +175567,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:520:17, endln:520:34 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:520:33, endln:520:34 |vpiDecompile:3 @@ -175581,7 +175581,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:521:17, endln:521:34 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:521:33, endln:521:34 |vpiDecompile:5 @@ -175595,7 +175595,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:522:17, endln:524:53 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:522:33, endln:524:53 |vpiDecompile:3 @@ -175609,7 +175609,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:587:27, endln:597:4 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_operation: , line:587:49, endln:597:4 |vpiParent: @@ -175844,7 +175844,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:625:17, endln:625:40 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:625:37, endln:625:40 |vpiDecompile:256 @@ -175858,7 +175858,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:626:17, endln:626:40 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:626:37, endln:626:40 |vpiDecompile:128 @@ -175872,7 +175872,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:627:17, endln:627:39 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:627:36, endln:627:39 |vpiDecompile:256 @@ -175886,7 +175886,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:628:17, endln:628:39 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:628:36, endln:628:39 |vpiDecompile:128 @@ -175900,7 +175900,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:629:17, endln:629:39 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:629:36, endln:629:39 |vpiDecompile:128 @@ -175914,7 +175914,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:630:17, endln:630:38 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:630:36, endln:630:38 |vpiDecompile:64 @@ -175928,7 +175928,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:631:17, endln:631:39 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:631:36, endln:631:39 |vpiDecompile:128 @@ -175942,7 +175942,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:632:17, endln:632:39 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:632:36, endln:632:39 |vpiDecompile:256 @@ -175956,7 +175956,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:645:30, endln:649:4 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_operation: , line:645:55, endln:649:4 |vpiParent: @@ -176087,7 +176087,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:672:33, endln:677:4 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_operation: , line:672:61, endln:677:4 |vpiParent: @@ -176222,7 +176222,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:728:18, endln:728:32 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:728:30, endln:728:32 |vpiDecompile:40 @@ -176236,7 +176236,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:731:26, endln:731:65 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:731:51, endln:731:65 |vpiDecompile:40'h453d28ea98 @@ -176248,7 +176248,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:732:26, endln:733:72 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:733:7, endln:733:72 |vpiDecompile:240'h4235171482c225f79289b32181a0163a760355d3447063d16661e44c12a5 @@ -176260,7 +176260,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:737:25, endln:741:4 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_operation: , line:737:45, endln:741:4 |vpiParent: @@ -176389,7 +176389,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:746:34, endln:752:4 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_operation: , line:746:62, endln:752:4 |vpiParent: @@ -176534,7 +176534,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:755:31, endln:761:4 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_operation: , line:755:56, endln:761:4 |vpiParent: @@ -176679,7 +176679,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:763:37, endln:764:42 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:764:5, endln:764:42 |vpiDecompile:128'hcbbd013ff15eba2f3065461eeb88463e @@ -176693,7 +176693,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:27:17, endln:27:39 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:27:38, endln:27:39 |vpiDecompile:2 @@ -176707,7 +176707,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:28:17, endln:28:38 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:28:36, endln:28:38 |vpiDecompile:11 @@ -176721,7 +176721,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:29:17, endln:29:36 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:29:35, endln:29:36 |vpiDecompile:9 @@ -176735,7 +176735,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:30:17, endln:30:32 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:30:31, endln:30:32 |vpiDecompile:2 @@ -176749,7 +176749,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:31:17, endln:31:35 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:31:34, endln:31:35 |vpiDecompile:2 @@ -176763,7 +176763,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:32:17, endln:32:42 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:32:39, endln:32:42 |vpiDecompile:512 @@ -176777,7 +176777,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:33:17, endln:33:41 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:33:39, endln:33:41 |vpiDecompile:16 @@ -176791,7 +176791,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:34:17, endln:34:28 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:34:27, endln:34:28 |vpiDecompile:7 @@ -176805,7 +176805,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:35:17, endln:35:39 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:35:38, endln:35:39 |vpiDecompile:0 @@ -176819,7 +176819,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:36:17, endln:36:39 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:36:36, endln:36:39 |vpiDecompile:768 @@ -176833,7 +176833,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:37:17, endln:37:46 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:37:45, endln:37:46 |vpiDecompile:0 @@ -176847,7 +176847,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:38:17, endln:38:46 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:38:43, endln:38:46 |vpiDecompile:760 @@ -176861,7 +176861,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:39:17, endln:39:47 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:39:44, endln:39:47 |vpiDecompile:760 @@ -176875,7 +176875,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:40:17, endln:40:43 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:40:42, endln:40:43 |vpiDecompile:8 @@ -176889,7 +176889,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:41:17, endln:41:39 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:41:36, endln:41:39 |vpiDecompile:768 @@ -176903,7 +176903,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:42:17, endln:42:37 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:42:34, endln:42:37 |vpiDecompile:768 @@ -176917,7 +176917,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:43:17, endln:43:46 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:43:43, endln:43:46 |vpiDecompile:768 @@ -176931,7 +176931,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:44:17, endln:44:44 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:44:41, endln:44:44 |vpiDecompile:760 @@ -176945,7 +176945,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:45:17, endln:45:46 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:45:42, endln:45:46 |vpiDecompile:1528 @@ -176959,7 +176959,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:46:17, endln:46:41 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:46:40, endln:46:41 |vpiDecompile:8 @@ -176973,7 +176973,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:47:17, endln:47:35 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:47:31, endln:47:35 |vpiDecompile:1536 @@ -176987,7 +176987,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:48:17, endln:48:32 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:48:29, endln:48:32 |vpiDecompile:208 @@ -177001,7 +177001,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:49:17, endln:49:38 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:49:34, endln:49:38 |vpiDecompile:1536 @@ -177015,7 +177015,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:50:17, endln:50:34 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:50:32, endln:50:34 |vpiDecompile:32 @@ -177029,7 +177029,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:51:17, endln:51:42 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:51:38, endln:51:42 |vpiDecompile:1568 @@ -177043,7 +177043,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:52:17, endln:52:39 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:52:36, endln:52:39 |vpiDecompile:168 @@ -177057,7 +177057,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:53:17, endln:53:41 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:53:37, endln:53:41 |vpiDecompile:1736 @@ -177071,7 +177071,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:54:17, endln:54:36 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:54:35, endln:54:36 |vpiDecompile:8 @@ -177085,7 +177085,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:55:17, endln:55:37 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:55:33, endln:55:37 |vpiDecompile:1744 @@ -177099,7 +177099,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:56:17, endln:56:33 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:56:31, endln:56:33 |vpiDecompile:40 @@ -177113,7 +177113,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:57:17, endln:57:45 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:57:41, endln:57:45 |vpiDecompile:1744 @@ -177127,7 +177127,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:58:17, endln:58:41 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:58:39, endln:58:41 |vpiDecompile:16 @@ -177141,7 +177141,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:59:17, endln:59:43 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:59:39, endln:59:43 |vpiDecompile:1760 @@ -177155,7 +177155,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:60:17, endln:60:39 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:60:37, endln:60:39 |vpiDecompile:16 @@ -177169,7 +177169,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:61:17, endln:61:43 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:61:39, endln:61:43 |vpiDecompile:1776 @@ -177183,7 +177183,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:62:17, endln:62:38 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:62:37, endln:62:38 |vpiDecompile:8 @@ -177197,7 +177197,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:63:17, endln:63:37 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:63:33, endln:63:37 |vpiDecompile:1784 @@ -177211,7 +177211,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:64:17, endln:64:33 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:64:31, endln:64:33 |vpiDecompile:88 @@ -177225,7 +177225,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:65:17, endln:65:46 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:65:42, endln:65:46 |vpiDecompile:1784 @@ -177239,7 +177239,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:66:17, endln:66:42 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:66:40, endln:66:42 |vpiDecompile:32 @@ -177253,7 +177253,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:67:17, endln:67:46 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:67:42, endln:67:46 |vpiDecompile:1816 @@ -177267,7 +177267,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:68:17, endln:68:42 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:68:40, endln:68:42 |vpiDecompile:32 @@ -177281,7 +177281,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:69:17, endln:69:45 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:69:41, endln:69:45 |vpiDecompile:1848 @@ -177295,7 +177295,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:70:17, endln:70:41 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:70:39, endln:70:41 |vpiDecompile:16 @@ -177309,7 +177309,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:71:17, endln:71:43 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:71:39, endln:71:43 |vpiDecompile:1864 @@ -177323,7 +177323,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:72:17, endln:72:38 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:72:37, endln:72:38 |vpiDecompile:8 @@ -177337,7 +177337,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:73:17, endln:73:37 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:73:33, endln:73:37 |vpiDecompile:1872 @@ -177351,7 +177351,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:74:17, endln:74:34 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:74:31, endln:74:34 |vpiDecompile:120 @@ -177365,7 +177365,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:75:17, endln:75:38 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:75:34, endln:75:38 |vpiDecompile:1872 @@ -177379,7 +177379,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:76:17, endln:76:34 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:76:32, endln:76:34 |vpiDecompile:16 @@ -177393,7 +177393,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:77:17, endln:77:50 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:77:46, endln:77:50 |vpiDecompile:1888 @@ -177407,7 +177407,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:78:17, endln:78:46 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:78:44, endln:78:46 |vpiDecompile:32 @@ -177421,7 +177421,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:79:17, endln:79:50 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:79:46, endln:79:50 |vpiDecompile:1920 @@ -177435,7 +177435,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:80:17, endln:80:46 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:80:44, endln:80:46 |vpiDecompile:32 @@ -177449,7 +177449,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:81:17, endln:81:43 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:81:39, endln:81:43 |vpiDecompile:1984 @@ -177463,7 +177463,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:82:17, endln:82:38 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:82:37, endln:82:38 |vpiDecompile:8 @@ -177477,7 +177477,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:83:17, endln:83:39 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:83:35, endln:83:39 |vpiDecompile:1992 @@ -177491,7 +177491,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:84:17, endln:84:35 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:84:33, endln:84:35 |vpiDecompile:56 @@ -177505,7 +177505,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:85:17, endln:85:37 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:85:33, endln:85:37 |vpiDecompile:1992 @@ -177519,7 +177519,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:86:17, endln:86:33 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:86:31, endln:86:33 |vpiDecompile:24 @@ -177533,7 +177533,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:87:17, endln:87:45 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:87:41, endln:87:45 |vpiDecompile:2016 @@ -177547,7 +177547,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:88:17, endln:88:41 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:88:39, endln:88:41 |vpiDecompile:32 @@ -177561,7 +177561,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:89:17, endln:89:30 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:89:29, endln:89:30 |vpiDecompile:2 @@ -177575,7 +177575,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:322:26, endln:322:60 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:322:55, endln:322:60 |vpiLhs: @@ -177583,7 +177583,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:323:26, endln:323:61 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:323:56, endln:323:61 |vpiLhs: @@ -177591,7 +177591,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:324:26, endln:324:59 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:324:54, endln:324:59 |vpiLhs: @@ -177599,7 +177599,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:325:26, endln:325:60 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:325:55, endln:325:60 |vpiLhs: @@ -177607,7 +177607,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:326:26, endln:326:57 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:326:51, endln:326:57 |vpiLhs: @@ -177615,7 +177615,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:327:26, endln:327:59 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:327:53, endln:327:59 |vpiLhs: @@ -177623,7 +177623,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:328:26, endln:328:71 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:328:65, endln:328:71 |vpiLhs: @@ -177631,7 +177631,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:329:26, endln:329:68 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:329:62, endln:329:68 |vpiLhs: @@ -177639,7 +177639,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:330:26, endln:330:72 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:330:66, endln:330:72 |vpiLhs: @@ -177647,7 +177647,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:331:26, endln:331:72 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:331:66, endln:331:72 |vpiLhs: @@ -177655,7 +177655,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:332:26, endln:332:72 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:332:66, endln:332:72 |vpiLhs: @@ -177663,7 +177663,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:333:26, endln:333:72 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:333:66, endln:333:72 |vpiLhs: @@ -177671,7 +177671,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:334:26, endln:334:72 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:334:66, endln:334:72 |vpiLhs: @@ -177679,7 +177679,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:335:26, endln:335:71 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:335:65, endln:335:71 |vpiLhs: @@ -177687,7 +177687,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:336:26, endln:336:64 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:336:58, endln:336:64 |vpiLhs: @@ -177695,7 +177695,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:337:26, endln:337:63 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:337:57, endln:337:63 |vpiLhs: @@ -177703,7 +177703,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:338:26, endln:338:64 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:338:58, endln:338:64 |vpiLhs: @@ -177711,7 +177711,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:339:26, endln:339:73 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:339:67, endln:339:73 |vpiLhs: @@ -177719,7 +177719,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:340:26, endln:340:75 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:340:69, endln:340:75 |vpiLhs: @@ -177727,7 +177727,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:341:26, endln:341:75 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:341:69, endln:341:75 |vpiLhs: @@ -177735,7 +177735,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:342:26, endln:342:73 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:342:67, endln:342:73 |vpiLhs: @@ -177743,7 +177743,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:343:26, endln:343:74 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:343:68, endln:343:74 |vpiLhs: @@ -177751,7 +177751,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:344:26, endln:344:74 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:344:68, endln:344:74 |vpiLhs: @@ -177759,7 +177759,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:345:26, endln:345:72 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:345:66, endln:345:72 |vpiLhs: @@ -177767,7 +177767,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:346:26, endln:346:72 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:346:66, endln:346:72 |vpiLhs: @@ -177775,7 +177775,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:347:26, endln:347:66 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:347:60, endln:347:66 |vpiLhs: @@ -177783,7 +177783,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:348:26, endln:348:66 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:348:60, endln:348:66 |vpiLhs: @@ -177791,7 +177791,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:349:26, endln:349:67 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:349:61, endln:349:67 |vpiLhs: @@ -177799,7 +177799,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:350:26, endln:350:67 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:350:61, endln:350:67 |vpiLhs: @@ -177807,7 +177807,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:351:26, endln:351:67 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:351:61, endln:351:67 |vpiLhs: @@ -177815,7 +177815,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:352:26, endln:352:67 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:352:61, endln:352:67 |vpiLhs: @@ -177823,7 +177823,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:353:26, endln:353:67 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:353:61, endln:353:67 |vpiLhs: @@ -177831,7 +177831,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:354:26, endln:354:67 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:354:61, endln:354:67 |vpiLhs: @@ -177839,7 +177839,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:357:26, endln:357:66 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:357:58, endln:357:66 |vpiLhs: @@ -177847,7 +177847,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:358:26, endln:358:65 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:358:58, endln:358:65 |vpiLhs: @@ -177855,7 +177855,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:359:26, endln:359:64 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:359:56, endln:359:64 |vpiLhs: @@ -177863,7 +177863,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:360:26, endln:360:62 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:360:56, endln:360:62 |vpiLhs: @@ -177871,7 +177871,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:400:25, endln:434:4 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_operation: , line:400:48, endln:434:4 |vpiParent: @@ -178343,7 +178343,7 @@ design: (work@otp_ctrl) |vpiTaskFunc: \_function: (otp_ctrl_pkg::vbits), line:14:1, endln:18:14 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiName:vbits |vpiFullName:otp_ctrl_pkg::vbits |vpiVisibility:1 @@ -178351,7 +178351,7 @@ design: (work@otp_ctrl) |vpiReturn: \_integer_var: , line:14:20, endln:14:27 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiIODecl: \_io_decl: (value), line:14:42, endln:14:47 |vpiParent: @@ -178402,11 +178402,11 @@ design: (work@otp_ctrl) |vpiFunction: \_function: (prim_util_pkg::_clog2), line:5:3, endln:12:14 |vpiInstance: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiGenScopeArray: \_gen_scope_array: (work@otp_ctrl.gen_partitions[4]), line:882:39, endln:891:4 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiName:gen_partitions[4] |vpiFullName:work@otp_ctrl.gen_partitions[4] |vpiGenScope: @@ -178435,8 +178435,8 @@ design: (work@otp_ctrl) |vpiParent: \_gen_scope_array: (work@otp_ctrl.gen_partitions[4].gen_buffered), line:884:1, endln:889:4 |vpiFullName:work@otp_ctrl.gen_partitions[4].gen_buffered - |vpiModule: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + |vpiModuleInst: + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiParent: \_gen_scope: (work@otp_ctrl.gen_partitions[4].gen_buffered) |vpiName:u_part_buf @@ -182613,7 +182613,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:774:37, endln:774:59 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiOverriden:1 |vpiRhs: \_bit_select: (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf.PartInfo), line:886:15, endln:886:26 @@ -182642,7 +182642,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:786:18, endln:786:77 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_operation: , line:786:33, endln:786:77 |vpiParent: @@ -182706,7 +182706,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:27:17, endln:27:39 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:27:38, endln:27:39 |vpiDecompile:2 @@ -182720,7 +182720,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:28:17, endln:28:38 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:28:36, endln:28:38 |vpiDecompile:11 @@ -182734,7 +182734,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:29:17, endln:29:36 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:29:35, endln:29:36 |vpiDecompile:9 @@ -182748,7 +182748,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:30:17, endln:30:32 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:30:31, endln:30:32 |vpiDecompile:2 @@ -182762,7 +182762,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:31:17, endln:31:35 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:31:34, endln:31:35 |vpiDecompile:2 @@ -182776,7 +182776,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:32:17, endln:32:42 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:32:39, endln:32:42 |vpiDecompile:512 @@ -182790,7 +182790,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:33:17, endln:33:41 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:33:39, endln:33:41 |vpiDecompile:16 @@ -182804,7 +182804,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:34:17, endln:34:28 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:34:27, endln:34:28 |vpiDecompile:7 @@ -182818,7 +182818,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:35:17, endln:35:39 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:35:38, endln:35:39 |vpiDecompile:0 @@ -182832,7 +182832,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:36:17, endln:36:39 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:36:36, endln:36:39 |vpiDecompile:768 @@ -182846,7 +182846,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:37:17, endln:37:46 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:37:45, endln:37:46 |vpiDecompile:0 @@ -182860,7 +182860,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:38:17, endln:38:46 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:38:43, endln:38:46 |vpiDecompile:760 @@ -182874,7 +182874,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:39:17, endln:39:47 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:39:44, endln:39:47 |vpiDecompile:760 @@ -182888,7 +182888,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:40:17, endln:40:43 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:40:42, endln:40:43 |vpiDecompile:8 @@ -182902,7 +182902,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:41:17, endln:41:39 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:41:36, endln:41:39 |vpiDecompile:768 @@ -182916,7 +182916,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:42:17, endln:42:37 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:42:34, endln:42:37 |vpiDecompile:768 @@ -182930,7 +182930,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:43:17, endln:43:46 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:43:43, endln:43:46 |vpiDecompile:768 @@ -182944,7 +182944,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:44:17, endln:44:44 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:44:41, endln:44:44 |vpiDecompile:760 @@ -182958,7 +182958,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:45:17, endln:45:46 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:45:42, endln:45:46 |vpiDecompile:1528 @@ -182972,7 +182972,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:46:17, endln:46:41 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:46:40, endln:46:41 |vpiDecompile:8 @@ -182986,7 +182986,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:47:17, endln:47:35 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:47:31, endln:47:35 |vpiDecompile:1536 @@ -183000,7 +183000,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:48:17, endln:48:32 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:48:29, endln:48:32 |vpiDecompile:208 @@ -183014,7 +183014,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:49:17, endln:49:38 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:49:34, endln:49:38 |vpiDecompile:1536 @@ -183028,7 +183028,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:50:17, endln:50:34 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:50:32, endln:50:34 |vpiDecompile:32 @@ -183042,7 +183042,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:51:17, endln:51:42 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:51:38, endln:51:42 |vpiDecompile:1568 @@ -183056,7 +183056,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:52:17, endln:52:39 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:52:36, endln:52:39 |vpiDecompile:168 @@ -183070,7 +183070,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:53:17, endln:53:41 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:53:37, endln:53:41 |vpiDecompile:1736 @@ -183084,7 +183084,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:54:17, endln:54:36 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:54:35, endln:54:36 |vpiDecompile:8 @@ -183098,7 +183098,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:55:17, endln:55:37 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:55:33, endln:55:37 |vpiDecompile:1744 @@ -183112,7 +183112,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:56:17, endln:56:33 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:56:31, endln:56:33 |vpiDecompile:40 @@ -183126,7 +183126,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:57:17, endln:57:45 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:57:41, endln:57:45 |vpiDecompile:1744 @@ -183140,7 +183140,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:58:17, endln:58:41 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:58:39, endln:58:41 |vpiDecompile:16 @@ -183154,7 +183154,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:59:17, endln:59:43 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:59:39, endln:59:43 |vpiDecompile:1760 @@ -183168,7 +183168,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:60:17, endln:60:39 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:60:37, endln:60:39 |vpiDecompile:16 @@ -183182,7 +183182,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:61:17, endln:61:43 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:61:39, endln:61:43 |vpiDecompile:1776 @@ -183196,7 +183196,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:62:17, endln:62:38 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:62:37, endln:62:38 |vpiDecompile:8 @@ -183210,7 +183210,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:63:17, endln:63:37 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:63:33, endln:63:37 |vpiDecompile:1784 @@ -183224,7 +183224,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:64:17, endln:64:33 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:64:31, endln:64:33 |vpiDecompile:88 @@ -183238,7 +183238,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:65:17, endln:65:46 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:65:42, endln:65:46 |vpiDecompile:1784 @@ -183252,7 +183252,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:66:17, endln:66:42 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:66:40, endln:66:42 |vpiDecompile:32 @@ -183266,7 +183266,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:67:17, endln:67:46 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:67:42, endln:67:46 |vpiDecompile:1816 @@ -183280,7 +183280,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:68:17, endln:68:42 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:68:40, endln:68:42 |vpiDecompile:32 @@ -183294,7 +183294,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:69:17, endln:69:45 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:69:41, endln:69:45 |vpiDecompile:1848 @@ -183308,7 +183308,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:70:17, endln:70:41 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:70:39, endln:70:41 |vpiDecompile:16 @@ -183322,7 +183322,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:71:17, endln:71:43 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:71:39, endln:71:43 |vpiDecompile:1864 @@ -183336,7 +183336,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:72:17, endln:72:38 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:72:37, endln:72:38 |vpiDecompile:8 @@ -183350,7 +183350,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:73:17, endln:73:37 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:73:33, endln:73:37 |vpiDecompile:1872 @@ -183364,7 +183364,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:74:17, endln:74:34 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:74:31, endln:74:34 |vpiDecompile:120 @@ -183378,7 +183378,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:75:17, endln:75:38 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:75:34, endln:75:38 |vpiDecompile:1872 @@ -183392,7 +183392,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:76:17, endln:76:34 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:76:32, endln:76:34 |vpiDecompile:16 @@ -183406,7 +183406,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:77:17, endln:77:50 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:77:46, endln:77:50 |vpiDecompile:1888 @@ -183420,7 +183420,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:78:17, endln:78:46 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:78:44, endln:78:46 |vpiDecompile:32 @@ -183434,7 +183434,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:79:17, endln:79:50 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:79:46, endln:79:50 |vpiDecompile:1920 @@ -183448,7 +183448,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:80:17, endln:80:46 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:80:44, endln:80:46 |vpiDecompile:32 @@ -183462,7 +183462,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:81:17, endln:81:43 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:81:39, endln:81:43 |vpiDecompile:1984 @@ -183476,7 +183476,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:82:17, endln:82:38 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:82:37, endln:82:38 |vpiDecompile:8 @@ -183490,7 +183490,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:83:17, endln:83:39 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:83:35, endln:83:39 |vpiDecompile:1992 @@ -183504,7 +183504,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:84:17, endln:84:35 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:84:33, endln:84:35 |vpiDecompile:56 @@ -183518,7 +183518,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:85:17, endln:85:37 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:85:33, endln:85:37 |vpiDecompile:1992 @@ -183532,7 +183532,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:86:17, endln:86:33 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:86:31, endln:86:33 |vpiDecompile:24 @@ -183546,7 +183546,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:87:17, endln:87:45 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:87:41, endln:87:45 |vpiDecompile:2016 @@ -183560,7 +183560,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:88:17, endln:88:41 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:88:39, endln:88:41 |vpiDecompile:32 @@ -183574,7 +183574,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:89:17, endln:89:30 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:89:29, endln:89:30 |vpiDecompile:2 @@ -183588,7 +183588,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:322:26, endln:322:60 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:322:55, endln:322:60 |vpiDecompile:14'h0 @@ -183600,7 +183600,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:323:26, endln:323:61 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:323:56, endln:323:61 |vpiDecompile:14'h4 @@ -183612,7 +183612,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:324:26, endln:324:59 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:324:54, endln:324:59 |vpiDecompile:14'h8 @@ -183624,7 +183624,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:325:26, endln:325:60 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:325:55, endln:325:60 |vpiDecompile:14'hc @@ -183636,7 +183636,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:326:26, endln:326:57 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:326:51, endln:326:57 |vpiDecompile:14'h10 @@ -183648,7 +183648,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:327:26, endln:327:59 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:327:53, endln:327:59 |vpiDecompile:14'h14 @@ -183660,7 +183660,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:328:26, endln:328:71 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:328:65, endln:328:71 |vpiDecompile:14'h18 @@ -183672,7 +183672,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:329:26, endln:329:68 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:329:62, endln:329:68 |vpiDecompile:14'h1c @@ -183684,7 +183684,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:330:26, endln:330:72 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:330:66, endln:330:72 |vpiDecompile:14'h20 @@ -183696,7 +183696,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:331:26, endln:331:72 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:331:66, endln:331:72 |vpiDecompile:14'h24 @@ -183708,7 +183708,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:332:26, endln:332:72 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:332:66, endln:332:72 |vpiDecompile:14'h28 @@ -183720,7 +183720,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:333:26, endln:333:72 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:333:66, endln:333:72 |vpiDecompile:14'h2c @@ -183732,7 +183732,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:334:26, endln:334:72 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:334:66, endln:334:72 |vpiDecompile:14'h30 @@ -183744,7 +183744,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:335:26, endln:335:71 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:335:65, endln:335:71 |vpiDecompile:14'h34 @@ -183756,7 +183756,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:336:26, endln:336:64 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:336:58, endln:336:64 |vpiDecompile:14'h38 @@ -183768,7 +183768,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:337:26, endln:337:63 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:337:57, endln:337:63 |vpiDecompile:14'h3c @@ -183780,7 +183780,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:338:26, endln:338:64 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:338:58, endln:338:64 |vpiDecompile:14'h40 @@ -183792,7 +183792,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:339:26, endln:339:73 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:339:67, endln:339:73 |vpiDecompile:14'h44 @@ -183804,7 +183804,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:340:26, endln:340:75 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:340:69, endln:340:75 |vpiDecompile:14'h48 @@ -183816,7 +183816,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:341:26, endln:341:75 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:341:69, endln:341:75 |vpiDecompile:14'h4c @@ -183828,7 +183828,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:342:26, endln:342:73 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:342:67, endln:342:73 |vpiDecompile:14'h50 @@ -183840,7 +183840,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:343:26, endln:343:74 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:343:68, endln:343:74 |vpiDecompile:14'h54 @@ -183852,7 +183852,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:344:26, endln:344:74 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:344:68, endln:344:74 |vpiDecompile:14'h58 @@ -183864,7 +183864,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:345:26, endln:345:72 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:345:66, endln:345:72 |vpiDecompile:14'h5c @@ -183876,7 +183876,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:346:26, endln:346:72 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:346:66, endln:346:72 |vpiDecompile:14'h60 @@ -183888,7 +183888,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:347:26, endln:347:66 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:347:60, endln:347:66 |vpiDecompile:14'h64 @@ -183900,7 +183900,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:348:26, endln:348:66 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:348:60, endln:348:66 |vpiDecompile:14'h68 @@ -183912,7 +183912,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:349:26, endln:349:67 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:349:61, endln:349:67 |vpiDecompile:14'h6c @@ -183924,7 +183924,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:350:26, endln:350:67 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:350:61, endln:350:67 |vpiDecompile:14'h70 @@ -183936,7 +183936,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:351:26, endln:351:67 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:351:61, endln:351:67 |vpiDecompile:14'h74 @@ -183948,7 +183948,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:352:26, endln:352:67 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:352:61, endln:352:67 |vpiDecompile:14'h78 @@ -183960,7 +183960,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:353:26, endln:353:67 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:353:61, endln:353:67 |vpiDecompile:14'h7c @@ -183972,7 +183972,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:354:26, endln:354:67 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:354:61, endln:354:67 |vpiDecompile:14'h80 @@ -183984,7 +183984,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:357:26, endln:357:66 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:357:58, endln:357:66 |vpiDecompile:14'h1000 @@ -183996,7 +183996,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:358:26, endln:358:65 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:358:58, endln:358:65 |vpiDecompile:14'h800 @@ -184008,7 +184008,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:359:26, endln:359:64 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:359:56, endln:359:64 |vpiDecompile:14'h2000 @@ -184020,7 +184020,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:360:26, endln:360:62 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:360:56, endln:360:62 |vpiDecompile:14'h40 @@ -184032,7 +184032,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:400:25, endln:434:4 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_operation: , line:400:48, endln:434:4 |vpiParent: @@ -184369,7 +184369,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:448:17, endln:448:34 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:448:32, endln:448:34 |vpiDecompile:64 @@ -184383,7 +184383,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:450:17, endln:450:46 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:450:32, endln:450:46 |vpiDecompile:3 @@ -184397,7 +184397,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:452:17, endln:452:63 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:452:37, endln:452:63 |vpiDecompile:9 @@ -184411,7 +184411,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:468:17, endln:468:32 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:468:31, endln:468:32 |vpiDecompile:3 @@ -184425,7 +184425,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:480:17, endln:480:38 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:480:36, endln:480:38 |vpiDecompile:16 @@ -184439,7 +184439,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:481:17, endln:481:73 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:481:36, endln:481:73 |vpiDecompile:10 @@ -184453,7 +184453,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:482:17, endln:482:51 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:482:36, endln:482:51 |vpiDecompile:1024 @@ -184467,7 +184467,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:483:17, endln:483:37 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:483:36, endln:483:37 |vpiDecompile:2 @@ -184481,7 +184481,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:484:17, endln:484:37 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:484:36, endln:484:37 |vpiDecompile:3 @@ -184495,7 +184495,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:485:17, endln:485:37 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:485:36, endln:485:37 |vpiDecompile:2 @@ -184509,7 +184509,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:486:17, endln:486:60 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:486:36, endln:486:60 |vpiDecompile:64 @@ -184523,7 +184523,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:488:17, endln:488:67 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:488:36, endln:488:67 |vpiDecompile:1 @@ -184537,7 +184537,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:505:17, endln:505:39 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:505:36, endln:505:39 |vpiDecompile:128 @@ -184551,7 +184551,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:506:17, endln:506:38 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:506:36, endln:506:38 |vpiDecompile:64 @@ -184565,7 +184565,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:508:17, endln:508:38 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:508:36, endln:508:38 |vpiDecompile:31 @@ -184579,7 +184579,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:509:17, endln:509:67 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:509:40, endln:509:67 |vpiDecompile:4 @@ -184593,7 +184593,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:520:17, endln:520:34 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:520:33, endln:520:34 |vpiDecompile:3 @@ -184607,7 +184607,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:521:17, endln:521:34 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:521:33, endln:521:34 |vpiDecompile:5 @@ -184621,7 +184621,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:522:17, endln:524:53 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:522:33, endln:524:53 |vpiDecompile:3 @@ -184635,7 +184635,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:587:27, endln:597:4 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_operation: , line:587:49, endln:597:4 |vpiParent: @@ -184870,7 +184870,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:625:17, endln:625:40 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:625:37, endln:625:40 |vpiDecompile:256 @@ -184884,7 +184884,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:626:17, endln:626:40 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:626:37, endln:626:40 |vpiDecompile:128 @@ -184898,7 +184898,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:627:17, endln:627:39 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:627:36, endln:627:39 |vpiDecompile:256 @@ -184912,7 +184912,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:628:17, endln:628:39 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:628:36, endln:628:39 |vpiDecompile:128 @@ -184926,7 +184926,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:629:17, endln:629:39 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:629:36, endln:629:39 |vpiDecompile:128 @@ -184940,7 +184940,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:630:17, endln:630:38 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:630:36, endln:630:38 |vpiDecompile:64 @@ -184954,7 +184954,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:631:17, endln:631:39 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:631:36, endln:631:39 |vpiDecompile:128 @@ -184968,7 +184968,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:632:17, endln:632:39 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:632:36, endln:632:39 |vpiDecompile:256 @@ -184982,7 +184982,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:645:30, endln:649:4 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_operation: , line:645:55, endln:649:4 |vpiParent: @@ -185113,7 +185113,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:672:33, endln:677:4 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_operation: , line:672:61, endln:677:4 |vpiParent: @@ -185248,7 +185248,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:728:18, endln:728:32 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:728:30, endln:728:32 |vpiDecompile:40 @@ -185262,7 +185262,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:731:26, endln:731:65 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:731:51, endln:731:65 |vpiDecompile:40'h453d28ea98 @@ -185274,7 +185274,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:732:26, endln:733:72 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:733:7, endln:733:72 |vpiDecompile:240'h4235171482c225f79289b32181a0163a760355d3447063d16661e44c12a5 @@ -185286,7 +185286,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:737:25, endln:741:4 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_operation: , line:737:45, endln:741:4 |vpiParent: @@ -185415,7 +185415,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:746:34, endln:752:4 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_operation: , line:746:62, endln:752:4 |vpiParent: @@ -185560,7 +185560,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:755:31, endln:761:4 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_operation: , line:755:56, endln:761:4 |vpiParent: @@ -185705,7 +185705,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:763:37, endln:764:42 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:764:5, endln:764:42 |vpiDecompile:128'hcbbd013ff15eba2f3065461eeb88463e @@ -185719,7 +185719,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:27:17, endln:27:39 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:27:38, endln:27:39 |vpiDecompile:2 @@ -185733,7 +185733,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:28:17, endln:28:38 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:28:36, endln:28:38 |vpiDecompile:11 @@ -185747,7 +185747,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:29:17, endln:29:36 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:29:35, endln:29:36 |vpiDecompile:9 @@ -185761,7 +185761,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:30:17, endln:30:32 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:30:31, endln:30:32 |vpiDecompile:2 @@ -185775,7 +185775,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:31:17, endln:31:35 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:31:34, endln:31:35 |vpiDecompile:2 @@ -185789,7 +185789,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:32:17, endln:32:42 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:32:39, endln:32:42 |vpiDecompile:512 @@ -185803,7 +185803,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:33:17, endln:33:41 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:33:39, endln:33:41 |vpiDecompile:16 @@ -185817,7 +185817,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:34:17, endln:34:28 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:34:27, endln:34:28 |vpiDecompile:7 @@ -185831,7 +185831,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:35:17, endln:35:39 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:35:38, endln:35:39 |vpiDecompile:0 @@ -185845,7 +185845,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:36:17, endln:36:39 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:36:36, endln:36:39 |vpiDecompile:768 @@ -185859,7 +185859,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:37:17, endln:37:46 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:37:45, endln:37:46 |vpiDecompile:0 @@ -185873,7 +185873,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:38:17, endln:38:46 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:38:43, endln:38:46 |vpiDecompile:760 @@ -185887,7 +185887,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:39:17, endln:39:47 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:39:44, endln:39:47 |vpiDecompile:760 @@ -185901,7 +185901,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:40:17, endln:40:43 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:40:42, endln:40:43 |vpiDecompile:8 @@ -185915,7 +185915,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:41:17, endln:41:39 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:41:36, endln:41:39 |vpiDecompile:768 @@ -185929,7 +185929,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:42:17, endln:42:37 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:42:34, endln:42:37 |vpiDecompile:768 @@ -185943,7 +185943,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:43:17, endln:43:46 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:43:43, endln:43:46 |vpiDecompile:768 @@ -185957,7 +185957,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:44:17, endln:44:44 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:44:41, endln:44:44 |vpiDecompile:760 @@ -185971,7 +185971,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:45:17, endln:45:46 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:45:42, endln:45:46 |vpiDecompile:1528 @@ -185985,7 +185985,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:46:17, endln:46:41 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:46:40, endln:46:41 |vpiDecompile:8 @@ -185999,7 +185999,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:47:17, endln:47:35 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:47:31, endln:47:35 |vpiDecompile:1536 @@ -186013,7 +186013,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:48:17, endln:48:32 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:48:29, endln:48:32 |vpiDecompile:208 @@ -186027,7 +186027,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:49:17, endln:49:38 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:49:34, endln:49:38 |vpiDecompile:1536 @@ -186041,7 +186041,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:50:17, endln:50:34 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:50:32, endln:50:34 |vpiDecompile:32 @@ -186055,7 +186055,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:51:17, endln:51:42 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:51:38, endln:51:42 |vpiDecompile:1568 @@ -186069,7 +186069,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:52:17, endln:52:39 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:52:36, endln:52:39 |vpiDecompile:168 @@ -186083,7 +186083,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:53:17, endln:53:41 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:53:37, endln:53:41 |vpiDecompile:1736 @@ -186097,7 +186097,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:54:17, endln:54:36 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:54:35, endln:54:36 |vpiDecompile:8 @@ -186111,7 +186111,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:55:17, endln:55:37 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:55:33, endln:55:37 |vpiDecompile:1744 @@ -186125,7 +186125,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:56:17, endln:56:33 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:56:31, endln:56:33 |vpiDecompile:40 @@ -186139,7 +186139,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:57:17, endln:57:45 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:57:41, endln:57:45 |vpiDecompile:1744 @@ -186153,7 +186153,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:58:17, endln:58:41 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:58:39, endln:58:41 |vpiDecompile:16 @@ -186167,7 +186167,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:59:17, endln:59:43 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:59:39, endln:59:43 |vpiDecompile:1760 @@ -186181,7 +186181,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:60:17, endln:60:39 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:60:37, endln:60:39 |vpiDecompile:16 @@ -186195,7 +186195,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:61:17, endln:61:43 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:61:39, endln:61:43 |vpiDecompile:1776 @@ -186209,7 +186209,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:62:17, endln:62:38 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:62:37, endln:62:38 |vpiDecompile:8 @@ -186223,7 +186223,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:63:17, endln:63:37 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:63:33, endln:63:37 |vpiDecompile:1784 @@ -186237,7 +186237,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:64:17, endln:64:33 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:64:31, endln:64:33 |vpiDecompile:88 @@ -186251,7 +186251,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:65:17, endln:65:46 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:65:42, endln:65:46 |vpiDecompile:1784 @@ -186265,7 +186265,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:66:17, endln:66:42 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:66:40, endln:66:42 |vpiDecompile:32 @@ -186279,7 +186279,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:67:17, endln:67:46 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:67:42, endln:67:46 |vpiDecompile:1816 @@ -186293,7 +186293,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:68:17, endln:68:42 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:68:40, endln:68:42 |vpiDecompile:32 @@ -186307,7 +186307,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:69:17, endln:69:45 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:69:41, endln:69:45 |vpiDecompile:1848 @@ -186321,7 +186321,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:70:17, endln:70:41 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:70:39, endln:70:41 |vpiDecompile:16 @@ -186335,7 +186335,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:71:17, endln:71:43 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:71:39, endln:71:43 |vpiDecompile:1864 @@ -186349,7 +186349,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:72:17, endln:72:38 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:72:37, endln:72:38 |vpiDecompile:8 @@ -186363,7 +186363,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:73:17, endln:73:37 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:73:33, endln:73:37 |vpiDecompile:1872 @@ -186377,7 +186377,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:74:17, endln:74:34 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:74:31, endln:74:34 |vpiDecompile:120 @@ -186391,7 +186391,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:75:17, endln:75:38 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:75:34, endln:75:38 |vpiDecompile:1872 @@ -186405,7 +186405,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:76:17, endln:76:34 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:76:32, endln:76:34 |vpiDecompile:16 @@ -186419,7 +186419,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:77:17, endln:77:50 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:77:46, endln:77:50 |vpiDecompile:1888 @@ -186433,7 +186433,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:78:17, endln:78:46 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:78:44, endln:78:46 |vpiDecompile:32 @@ -186447,7 +186447,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:79:17, endln:79:50 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:79:46, endln:79:50 |vpiDecompile:1920 @@ -186461,7 +186461,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:80:17, endln:80:46 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:80:44, endln:80:46 |vpiDecompile:32 @@ -186475,7 +186475,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:81:17, endln:81:43 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:81:39, endln:81:43 |vpiDecompile:1984 @@ -186489,7 +186489,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:82:17, endln:82:38 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:82:37, endln:82:38 |vpiDecompile:8 @@ -186503,7 +186503,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:83:17, endln:83:39 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:83:35, endln:83:39 |vpiDecompile:1992 @@ -186517,7 +186517,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:84:17, endln:84:35 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:84:33, endln:84:35 |vpiDecompile:56 @@ -186531,7 +186531,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:85:17, endln:85:37 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:85:33, endln:85:37 |vpiDecompile:1992 @@ -186545,7 +186545,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:86:17, endln:86:33 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:86:31, endln:86:33 |vpiDecompile:24 @@ -186559,7 +186559,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:87:17, endln:87:45 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:87:41, endln:87:45 |vpiDecompile:2016 @@ -186573,7 +186573,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:88:17, endln:88:41 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:88:39, endln:88:41 |vpiDecompile:32 @@ -186587,7 +186587,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:89:17, endln:89:30 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:89:29, endln:89:30 |vpiDecompile:2 @@ -186601,7 +186601,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:322:26, endln:322:60 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:322:55, endln:322:60 |vpiLhs: @@ -186609,7 +186609,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:323:26, endln:323:61 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:323:56, endln:323:61 |vpiLhs: @@ -186617,7 +186617,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:324:26, endln:324:59 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:324:54, endln:324:59 |vpiLhs: @@ -186625,7 +186625,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:325:26, endln:325:60 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:325:55, endln:325:60 |vpiLhs: @@ -186633,7 +186633,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:326:26, endln:326:57 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:326:51, endln:326:57 |vpiLhs: @@ -186641,7 +186641,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:327:26, endln:327:59 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:327:53, endln:327:59 |vpiLhs: @@ -186649,7 +186649,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:328:26, endln:328:71 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:328:65, endln:328:71 |vpiLhs: @@ -186657,7 +186657,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:329:26, endln:329:68 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:329:62, endln:329:68 |vpiLhs: @@ -186665,7 +186665,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:330:26, endln:330:72 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:330:66, endln:330:72 |vpiLhs: @@ -186673,7 +186673,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:331:26, endln:331:72 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:331:66, endln:331:72 |vpiLhs: @@ -186681,7 +186681,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:332:26, endln:332:72 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:332:66, endln:332:72 |vpiLhs: @@ -186689,7 +186689,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:333:26, endln:333:72 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:333:66, endln:333:72 |vpiLhs: @@ -186697,7 +186697,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:334:26, endln:334:72 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:334:66, endln:334:72 |vpiLhs: @@ -186705,7 +186705,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:335:26, endln:335:71 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:335:65, endln:335:71 |vpiLhs: @@ -186713,7 +186713,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:336:26, endln:336:64 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:336:58, endln:336:64 |vpiLhs: @@ -186721,7 +186721,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:337:26, endln:337:63 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:337:57, endln:337:63 |vpiLhs: @@ -186729,7 +186729,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:338:26, endln:338:64 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:338:58, endln:338:64 |vpiLhs: @@ -186737,7 +186737,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:339:26, endln:339:73 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:339:67, endln:339:73 |vpiLhs: @@ -186745,7 +186745,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:340:26, endln:340:75 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:340:69, endln:340:75 |vpiLhs: @@ -186753,7 +186753,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:341:26, endln:341:75 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:341:69, endln:341:75 |vpiLhs: @@ -186761,7 +186761,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:342:26, endln:342:73 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:342:67, endln:342:73 |vpiLhs: @@ -186769,7 +186769,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:343:26, endln:343:74 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:343:68, endln:343:74 |vpiLhs: @@ -186777,7 +186777,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:344:26, endln:344:74 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:344:68, endln:344:74 |vpiLhs: @@ -186785,7 +186785,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:345:26, endln:345:72 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:345:66, endln:345:72 |vpiLhs: @@ -186793,7 +186793,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:346:26, endln:346:72 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:346:66, endln:346:72 |vpiLhs: @@ -186801,7 +186801,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:347:26, endln:347:66 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:347:60, endln:347:66 |vpiLhs: @@ -186809,7 +186809,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:348:26, endln:348:66 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:348:60, endln:348:66 |vpiLhs: @@ -186817,7 +186817,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:349:26, endln:349:67 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:349:61, endln:349:67 |vpiLhs: @@ -186825,7 +186825,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:350:26, endln:350:67 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:350:61, endln:350:67 |vpiLhs: @@ -186833,7 +186833,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:351:26, endln:351:67 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:351:61, endln:351:67 |vpiLhs: @@ -186841,7 +186841,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:352:26, endln:352:67 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:352:61, endln:352:67 |vpiLhs: @@ -186849,7 +186849,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:353:26, endln:353:67 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:353:61, endln:353:67 |vpiLhs: @@ -186857,7 +186857,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:354:26, endln:354:67 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:354:61, endln:354:67 |vpiLhs: @@ -186865,7 +186865,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:357:26, endln:357:66 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:357:58, endln:357:66 |vpiLhs: @@ -186873,7 +186873,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:358:26, endln:358:65 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:358:58, endln:358:65 |vpiLhs: @@ -186881,7 +186881,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:359:26, endln:359:64 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:359:56, endln:359:64 |vpiLhs: @@ -186889,7 +186889,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:360:26, endln:360:62 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:360:56, endln:360:62 |vpiLhs: @@ -186897,7 +186897,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:400:25, endln:434:4 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_operation: , line:400:48, endln:434:4 |vpiParent: @@ -187369,7 +187369,7 @@ design: (work@otp_ctrl) |vpiTaskFunc: \_function: (otp_ctrl_pkg::vbits), line:14:1, endln:18:14 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiName:vbits |vpiFullName:otp_ctrl_pkg::vbits |vpiVisibility:1 @@ -187377,7 +187377,7 @@ design: (work@otp_ctrl) |vpiReturn: \_integer_var: , line:14:20, endln:14:27 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiIODecl: \_io_decl: (value), line:14:42, endln:14:47 |vpiParent: @@ -187428,11 +187428,11 @@ design: (work@otp_ctrl) |vpiFunction: \_function: (prim_util_pkg::_clog2), line:5:3, endln:12:14 |vpiInstance: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[4].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiGenScopeArray: \_gen_scope_array: (work@otp_ctrl.gen_partitions[5]), line:882:39, endln:891:4 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiName:gen_partitions[5] |vpiFullName:work@otp_ctrl.gen_partitions[5] |vpiGenScope: @@ -187461,8 +187461,8 @@ design: (work@otp_ctrl) |vpiParent: \_gen_scope_array: (work@otp_ctrl.gen_partitions[5].gen_buffered), line:884:1, endln:889:4 |vpiFullName:work@otp_ctrl.gen_partitions[5].gen_buffered - |vpiModule: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + |vpiModuleInst: + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiParent: \_gen_scope: (work@otp_ctrl.gen_partitions[5].gen_buffered) |vpiName:u_part_buf @@ -191639,7 +191639,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:774:37, endln:774:59 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiOverriden:1 |vpiRhs: \_bit_select: (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf.PartInfo), line:886:15, endln:886:26 @@ -191668,7 +191668,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:786:18, endln:786:77 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_operation: , line:786:33, endln:786:77 |vpiParent: @@ -191732,7 +191732,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:27:17, endln:27:39 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:27:38, endln:27:39 |vpiDecompile:2 @@ -191746,7 +191746,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:28:17, endln:28:38 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:28:36, endln:28:38 |vpiDecompile:11 @@ -191760,7 +191760,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:29:17, endln:29:36 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:29:35, endln:29:36 |vpiDecompile:9 @@ -191774,7 +191774,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:30:17, endln:30:32 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:30:31, endln:30:32 |vpiDecompile:2 @@ -191788,7 +191788,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:31:17, endln:31:35 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:31:34, endln:31:35 |vpiDecompile:2 @@ -191802,7 +191802,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:32:17, endln:32:42 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:32:39, endln:32:42 |vpiDecompile:512 @@ -191816,7 +191816,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:33:17, endln:33:41 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:33:39, endln:33:41 |vpiDecompile:16 @@ -191830,7 +191830,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:34:17, endln:34:28 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:34:27, endln:34:28 |vpiDecompile:7 @@ -191844,7 +191844,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:35:17, endln:35:39 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:35:38, endln:35:39 |vpiDecompile:0 @@ -191858,7 +191858,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:36:17, endln:36:39 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:36:36, endln:36:39 |vpiDecompile:768 @@ -191872,7 +191872,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:37:17, endln:37:46 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:37:45, endln:37:46 |vpiDecompile:0 @@ -191886,7 +191886,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:38:17, endln:38:46 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:38:43, endln:38:46 |vpiDecompile:760 @@ -191900,7 +191900,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:39:17, endln:39:47 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:39:44, endln:39:47 |vpiDecompile:760 @@ -191914,7 +191914,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:40:17, endln:40:43 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:40:42, endln:40:43 |vpiDecompile:8 @@ -191928,7 +191928,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:41:17, endln:41:39 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:41:36, endln:41:39 |vpiDecompile:768 @@ -191942,7 +191942,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:42:17, endln:42:37 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:42:34, endln:42:37 |vpiDecompile:768 @@ -191956,7 +191956,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:43:17, endln:43:46 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:43:43, endln:43:46 |vpiDecompile:768 @@ -191970,7 +191970,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:44:17, endln:44:44 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:44:41, endln:44:44 |vpiDecompile:760 @@ -191984,7 +191984,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:45:17, endln:45:46 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:45:42, endln:45:46 |vpiDecompile:1528 @@ -191998,7 +191998,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:46:17, endln:46:41 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:46:40, endln:46:41 |vpiDecompile:8 @@ -192012,7 +192012,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:47:17, endln:47:35 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:47:31, endln:47:35 |vpiDecompile:1536 @@ -192026,7 +192026,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:48:17, endln:48:32 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:48:29, endln:48:32 |vpiDecompile:208 @@ -192040,7 +192040,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:49:17, endln:49:38 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:49:34, endln:49:38 |vpiDecompile:1536 @@ -192054,7 +192054,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:50:17, endln:50:34 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:50:32, endln:50:34 |vpiDecompile:32 @@ -192068,7 +192068,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:51:17, endln:51:42 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:51:38, endln:51:42 |vpiDecompile:1568 @@ -192082,7 +192082,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:52:17, endln:52:39 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:52:36, endln:52:39 |vpiDecompile:168 @@ -192096,7 +192096,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:53:17, endln:53:41 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:53:37, endln:53:41 |vpiDecompile:1736 @@ -192110,7 +192110,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:54:17, endln:54:36 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:54:35, endln:54:36 |vpiDecompile:8 @@ -192124,7 +192124,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:55:17, endln:55:37 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:55:33, endln:55:37 |vpiDecompile:1744 @@ -192138,7 +192138,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:56:17, endln:56:33 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:56:31, endln:56:33 |vpiDecompile:40 @@ -192152,7 +192152,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:57:17, endln:57:45 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:57:41, endln:57:45 |vpiDecompile:1744 @@ -192166,7 +192166,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:58:17, endln:58:41 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:58:39, endln:58:41 |vpiDecompile:16 @@ -192180,7 +192180,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:59:17, endln:59:43 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:59:39, endln:59:43 |vpiDecompile:1760 @@ -192194,7 +192194,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:60:17, endln:60:39 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:60:37, endln:60:39 |vpiDecompile:16 @@ -192208,7 +192208,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:61:17, endln:61:43 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:61:39, endln:61:43 |vpiDecompile:1776 @@ -192222,7 +192222,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:62:17, endln:62:38 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:62:37, endln:62:38 |vpiDecompile:8 @@ -192236,7 +192236,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:63:17, endln:63:37 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:63:33, endln:63:37 |vpiDecompile:1784 @@ -192250,7 +192250,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:64:17, endln:64:33 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:64:31, endln:64:33 |vpiDecompile:88 @@ -192264,7 +192264,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:65:17, endln:65:46 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:65:42, endln:65:46 |vpiDecompile:1784 @@ -192278,7 +192278,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:66:17, endln:66:42 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:66:40, endln:66:42 |vpiDecompile:32 @@ -192292,7 +192292,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:67:17, endln:67:46 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:67:42, endln:67:46 |vpiDecompile:1816 @@ -192306,7 +192306,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:68:17, endln:68:42 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:68:40, endln:68:42 |vpiDecompile:32 @@ -192320,7 +192320,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:69:17, endln:69:45 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:69:41, endln:69:45 |vpiDecompile:1848 @@ -192334,7 +192334,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:70:17, endln:70:41 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:70:39, endln:70:41 |vpiDecompile:16 @@ -192348,7 +192348,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:71:17, endln:71:43 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:71:39, endln:71:43 |vpiDecompile:1864 @@ -192362,7 +192362,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:72:17, endln:72:38 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:72:37, endln:72:38 |vpiDecompile:8 @@ -192376,7 +192376,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:73:17, endln:73:37 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:73:33, endln:73:37 |vpiDecompile:1872 @@ -192390,7 +192390,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:74:17, endln:74:34 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:74:31, endln:74:34 |vpiDecompile:120 @@ -192404,7 +192404,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:75:17, endln:75:38 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:75:34, endln:75:38 |vpiDecompile:1872 @@ -192418,7 +192418,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:76:17, endln:76:34 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:76:32, endln:76:34 |vpiDecompile:16 @@ -192432,7 +192432,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:77:17, endln:77:50 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:77:46, endln:77:50 |vpiDecompile:1888 @@ -192446,7 +192446,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:78:17, endln:78:46 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:78:44, endln:78:46 |vpiDecompile:32 @@ -192460,7 +192460,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:79:17, endln:79:50 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:79:46, endln:79:50 |vpiDecompile:1920 @@ -192474,7 +192474,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:80:17, endln:80:46 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:80:44, endln:80:46 |vpiDecompile:32 @@ -192488,7 +192488,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:81:17, endln:81:43 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:81:39, endln:81:43 |vpiDecompile:1984 @@ -192502,7 +192502,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:82:17, endln:82:38 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:82:37, endln:82:38 |vpiDecompile:8 @@ -192516,7 +192516,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:83:17, endln:83:39 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:83:35, endln:83:39 |vpiDecompile:1992 @@ -192530,7 +192530,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:84:17, endln:84:35 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:84:33, endln:84:35 |vpiDecompile:56 @@ -192544,7 +192544,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:85:17, endln:85:37 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:85:33, endln:85:37 |vpiDecompile:1992 @@ -192558,7 +192558,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:86:17, endln:86:33 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:86:31, endln:86:33 |vpiDecompile:24 @@ -192572,7 +192572,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:87:17, endln:87:45 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:87:41, endln:87:45 |vpiDecompile:2016 @@ -192586,7 +192586,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:88:17, endln:88:41 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:88:39, endln:88:41 |vpiDecompile:32 @@ -192600,7 +192600,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:89:17, endln:89:30 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:89:29, endln:89:30 |vpiDecompile:2 @@ -192614,7 +192614,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:322:26, endln:322:60 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:322:55, endln:322:60 |vpiDecompile:14'h0 @@ -192626,7 +192626,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:323:26, endln:323:61 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:323:56, endln:323:61 |vpiDecompile:14'h4 @@ -192638,7 +192638,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:324:26, endln:324:59 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:324:54, endln:324:59 |vpiDecompile:14'h8 @@ -192650,7 +192650,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:325:26, endln:325:60 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:325:55, endln:325:60 |vpiDecompile:14'hc @@ -192662,7 +192662,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:326:26, endln:326:57 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:326:51, endln:326:57 |vpiDecompile:14'h10 @@ -192674,7 +192674,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:327:26, endln:327:59 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:327:53, endln:327:59 |vpiDecompile:14'h14 @@ -192686,7 +192686,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:328:26, endln:328:71 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:328:65, endln:328:71 |vpiDecompile:14'h18 @@ -192698,7 +192698,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:329:26, endln:329:68 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:329:62, endln:329:68 |vpiDecompile:14'h1c @@ -192710,7 +192710,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:330:26, endln:330:72 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:330:66, endln:330:72 |vpiDecompile:14'h20 @@ -192722,7 +192722,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:331:26, endln:331:72 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:331:66, endln:331:72 |vpiDecompile:14'h24 @@ -192734,7 +192734,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:332:26, endln:332:72 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:332:66, endln:332:72 |vpiDecompile:14'h28 @@ -192746,7 +192746,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:333:26, endln:333:72 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:333:66, endln:333:72 |vpiDecompile:14'h2c @@ -192758,7 +192758,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:334:26, endln:334:72 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:334:66, endln:334:72 |vpiDecompile:14'h30 @@ -192770,7 +192770,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:335:26, endln:335:71 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:335:65, endln:335:71 |vpiDecompile:14'h34 @@ -192782,7 +192782,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:336:26, endln:336:64 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:336:58, endln:336:64 |vpiDecompile:14'h38 @@ -192794,7 +192794,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:337:26, endln:337:63 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:337:57, endln:337:63 |vpiDecompile:14'h3c @@ -192806,7 +192806,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:338:26, endln:338:64 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:338:58, endln:338:64 |vpiDecompile:14'h40 @@ -192818,7 +192818,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:339:26, endln:339:73 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:339:67, endln:339:73 |vpiDecompile:14'h44 @@ -192830,7 +192830,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:340:26, endln:340:75 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:340:69, endln:340:75 |vpiDecompile:14'h48 @@ -192842,7 +192842,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:341:26, endln:341:75 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:341:69, endln:341:75 |vpiDecompile:14'h4c @@ -192854,7 +192854,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:342:26, endln:342:73 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:342:67, endln:342:73 |vpiDecompile:14'h50 @@ -192866,7 +192866,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:343:26, endln:343:74 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:343:68, endln:343:74 |vpiDecompile:14'h54 @@ -192878,7 +192878,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:344:26, endln:344:74 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:344:68, endln:344:74 |vpiDecompile:14'h58 @@ -192890,7 +192890,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:345:26, endln:345:72 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:345:66, endln:345:72 |vpiDecompile:14'h5c @@ -192902,7 +192902,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:346:26, endln:346:72 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:346:66, endln:346:72 |vpiDecompile:14'h60 @@ -192914,7 +192914,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:347:26, endln:347:66 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:347:60, endln:347:66 |vpiDecompile:14'h64 @@ -192926,7 +192926,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:348:26, endln:348:66 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:348:60, endln:348:66 |vpiDecompile:14'h68 @@ -192938,7 +192938,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:349:26, endln:349:67 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:349:61, endln:349:67 |vpiDecompile:14'h6c @@ -192950,7 +192950,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:350:26, endln:350:67 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:350:61, endln:350:67 |vpiDecompile:14'h70 @@ -192962,7 +192962,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:351:26, endln:351:67 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:351:61, endln:351:67 |vpiDecompile:14'h74 @@ -192974,7 +192974,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:352:26, endln:352:67 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:352:61, endln:352:67 |vpiDecompile:14'h78 @@ -192986,7 +192986,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:353:26, endln:353:67 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:353:61, endln:353:67 |vpiDecompile:14'h7c @@ -192998,7 +192998,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:354:26, endln:354:67 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:354:61, endln:354:67 |vpiDecompile:14'h80 @@ -193010,7 +193010,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:357:26, endln:357:66 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:357:58, endln:357:66 |vpiDecompile:14'h1000 @@ -193022,7 +193022,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:358:26, endln:358:65 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:358:58, endln:358:65 |vpiDecompile:14'h800 @@ -193034,7 +193034,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:359:26, endln:359:64 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:359:56, endln:359:64 |vpiDecompile:14'h2000 @@ -193046,7 +193046,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:360:26, endln:360:62 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:360:56, endln:360:62 |vpiDecompile:14'h40 @@ -193058,7 +193058,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:400:25, endln:434:4 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_operation: , line:400:48, endln:434:4 |vpiParent: @@ -193395,7 +193395,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:448:17, endln:448:34 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:448:32, endln:448:34 |vpiDecompile:64 @@ -193409,7 +193409,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:450:17, endln:450:46 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:450:32, endln:450:46 |vpiDecompile:3 @@ -193423,7 +193423,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:452:17, endln:452:63 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:452:37, endln:452:63 |vpiDecompile:9 @@ -193437,7 +193437,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:468:17, endln:468:32 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:468:31, endln:468:32 |vpiDecompile:3 @@ -193451,7 +193451,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:480:17, endln:480:38 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:480:36, endln:480:38 |vpiDecompile:16 @@ -193465,7 +193465,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:481:17, endln:481:73 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:481:36, endln:481:73 |vpiDecompile:10 @@ -193479,7 +193479,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:482:17, endln:482:51 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:482:36, endln:482:51 |vpiDecompile:1024 @@ -193493,7 +193493,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:483:17, endln:483:37 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:483:36, endln:483:37 |vpiDecompile:2 @@ -193507,7 +193507,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:484:17, endln:484:37 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:484:36, endln:484:37 |vpiDecompile:3 @@ -193521,7 +193521,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:485:17, endln:485:37 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:485:36, endln:485:37 |vpiDecompile:2 @@ -193535,7 +193535,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:486:17, endln:486:60 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:486:36, endln:486:60 |vpiDecompile:64 @@ -193549,7 +193549,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:488:17, endln:488:67 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:488:36, endln:488:67 |vpiDecompile:1 @@ -193563,7 +193563,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:505:17, endln:505:39 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:505:36, endln:505:39 |vpiDecompile:128 @@ -193577,7 +193577,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:506:17, endln:506:38 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:506:36, endln:506:38 |vpiDecompile:64 @@ -193591,7 +193591,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:508:17, endln:508:38 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:508:36, endln:508:38 |vpiDecompile:31 @@ -193605,7 +193605,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:509:17, endln:509:67 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:509:40, endln:509:67 |vpiDecompile:4 @@ -193619,7 +193619,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:520:17, endln:520:34 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:520:33, endln:520:34 |vpiDecompile:3 @@ -193633,7 +193633,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:521:17, endln:521:34 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:521:33, endln:521:34 |vpiDecompile:5 @@ -193647,7 +193647,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:522:17, endln:524:53 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:522:33, endln:524:53 |vpiDecompile:3 @@ -193661,7 +193661,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:587:27, endln:597:4 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_operation: , line:587:49, endln:597:4 |vpiParent: @@ -193896,7 +193896,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:625:17, endln:625:40 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:625:37, endln:625:40 |vpiDecompile:256 @@ -193910,7 +193910,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:626:17, endln:626:40 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:626:37, endln:626:40 |vpiDecompile:128 @@ -193924,7 +193924,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:627:17, endln:627:39 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:627:36, endln:627:39 |vpiDecompile:256 @@ -193938,7 +193938,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:628:17, endln:628:39 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:628:36, endln:628:39 |vpiDecompile:128 @@ -193952,7 +193952,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:629:17, endln:629:39 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:629:36, endln:629:39 |vpiDecompile:128 @@ -193966,7 +193966,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:630:17, endln:630:38 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:630:36, endln:630:38 |vpiDecompile:64 @@ -193980,7 +193980,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:631:17, endln:631:39 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:631:36, endln:631:39 |vpiDecompile:128 @@ -193994,7 +193994,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:632:17, endln:632:39 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:632:36, endln:632:39 |vpiDecompile:256 @@ -194008,7 +194008,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:645:30, endln:649:4 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_operation: , line:645:55, endln:649:4 |vpiParent: @@ -194139,7 +194139,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:672:33, endln:677:4 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_operation: , line:672:61, endln:677:4 |vpiParent: @@ -194274,7 +194274,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:728:18, endln:728:32 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:728:30, endln:728:32 |vpiDecompile:40 @@ -194288,7 +194288,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:731:26, endln:731:65 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:731:51, endln:731:65 |vpiDecompile:40'h453d28ea98 @@ -194300,7 +194300,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:732:26, endln:733:72 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:733:7, endln:733:72 |vpiDecompile:240'h4235171482c225f79289b32181a0163a760355d3447063d16661e44c12a5 @@ -194312,7 +194312,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:737:25, endln:741:4 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_operation: , line:737:45, endln:741:4 |vpiParent: @@ -194441,7 +194441,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:746:34, endln:752:4 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_operation: , line:746:62, endln:752:4 |vpiParent: @@ -194586,7 +194586,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:755:31, endln:761:4 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_operation: , line:755:56, endln:761:4 |vpiParent: @@ -194731,7 +194731,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:763:37, endln:764:42 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:764:5, endln:764:42 |vpiDecompile:128'hcbbd013ff15eba2f3065461eeb88463e @@ -194745,7 +194745,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:27:17, endln:27:39 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:27:38, endln:27:39 |vpiDecompile:2 @@ -194759,7 +194759,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:28:17, endln:28:38 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:28:36, endln:28:38 |vpiDecompile:11 @@ -194773,7 +194773,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:29:17, endln:29:36 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:29:35, endln:29:36 |vpiDecompile:9 @@ -194787,7 +194787,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:30:17, endln:30:32 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:30:31, endln:30:32 |vpiDecompile:2 @@ -194801,7 +194801,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:31:17, endln:31:35 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:31:34, endln:31:35 |vpiDecompile:2 @@ -194815,7 +194815,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:32:17, endln:32:42 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:32:39, endln:32:42 |vpiDecompile:512 @@ -194829,7 +194829,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:33:17, endln:33:41 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:33:39, endln:33:41 |vpiDecompile:16 @@ -194843,7 +194843,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:34:17, endln:34:28 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:34:27, endln:34:28 |vpiDecompile:7 @@ -194857,7 +194857,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:35:17, endln:35:39 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:35:38, endln:35:39 |vpiDecompile:0 @@ -194871,7 +194871,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:36:17, endln:36:39 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:36:36, endln:36:39 |vpiDecompile:768 @@ -194885,7 +194885,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:37:17, endln:37:46 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:37:45, endln:37:46 |vpiDecompile:0 @@ -194899,7 +194899,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:38:17, endln:38:46 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:38:43, endln:38:46 |vpiDecompile:760 @@ -194913,7 +194913,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:39:17, endln:39:47 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:39:44, endln:39:47 |vpiDecompile:760 @@ -194927,7 +194927,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:40:17, endln:40:43 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:40:42, endln:40:43 |vpiDecompile:8 @@ -194941,7 +194941,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:41:17, endln:41:39 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:41:36, endln:41:39 |vpiDecompile:768 @@ -194955,7 +194955,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:42:17, endln:42:37 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:42:34, endln:42:37 |vpiDecompile:768 @@ -194969,7 +194969,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:43:17, endln:43:46 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:43:43, endln:43:46 |vpiDecompile:768 @@ -194983,7 +194983,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:44:17, endln:44:44 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:44:41, endln:44:44 |vpiDecompile:760 @@ -194997,7 +194997,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:45:17, endln:45:46 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:45:42, endln:45:46 |vpiDecompile:1528 @@ -195011,7 +195011,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:46:17, endln:46:41 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:46:40, endln:46:41 |vpiDecompile:8 @@ -195025,7 +195025,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:47:17, endln:47:35 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:47:31, endln:47:35 |vpiDecompile:1536 @@ -195039,7 +195039,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:48:17, endln:48:32 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:48:29, endln:48:32 |vpiDecompile:208 @@ -195053,7 +195053,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:49:17, endln:49:38 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:49:34, endln:49:38 |vpiDecompile:1536 @@ -195067,7 +195067,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:50:17, endln:50:34 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:50:32, endln:50:34 |vpiDecompile:32 @@ -195081,7 +195081,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:51:17, endln:51:42 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:51:38, endln:51:42 |vpiDecompile:1568 @@ -195095,7 +195095,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:52:17, endln:52:39 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:52:36, endln:52:39 |vpiDecompile:168 @@ -195109,7 +195109,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:53:17, endln:53:41 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:53:37, endln:53:41 |vpiDecompile:1736 @@ -195123,7 +195123,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:54:17, endln:54:36 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:54:35, endln:54:36 |vpiDecompile:8 @@ -195137,7 +195137,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:55:17, endln:55:37 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:55:33, endln:55:37 |vpiDecompile:1744 @@ -195151,7 +195151,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:56:17, endln:56:33 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:56:31, endln:56:33 |vpiDecompile:40 @@ -195165,7 +195165,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:57:17, endln:57:45 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:57:41, endln:57:45 |vpiDecompile:1744 @@ -195179,7 +195179,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:58:17, endln:58:41 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:58:39, endln:58:41 |vpiDecompile:16 @@ -195193,7 +195193,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:59:17, endln:59:43 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:59:39, endln:59:43 |vpiDecompile:1760 @@ -195207,7 +195207,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:60:17, endln:60:39 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:60:37, endln:60:39 |vpiDecompile:16 @@ -195221,7 +195221,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:61:17, endln:61:43 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:61:39, endln:61:43 |vpiDecompile:1776 @@ -195235,7 +195235,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:62:17, endln:62:38 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:62:37, endln:62:38 |vpiDecompile:8 @@ -195249,7 +195249,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:63:17, endln:63:37 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:63:33, endln:63:37 |vpiDecompile:1784 @@ -195263,7 +195263,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:64:17, endln:64:33 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:64:31, endln:64:33 |vpiDecompile:88 @@ -195277,7 +195277,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:65:17, endln:65:46 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:65:42, endln:65:46 |vpiDecompile:1784 @@ -195291,7 +195291,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:66:17, endln:66:42 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:66:40, endln:66:42 |vpiDecompile:32 @@ -195305,7 +195305,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:67:17, endln:67:46 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:67:42, endln:67:46 |vpiDecompile:1816 @@ -195319,7 +195319,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:68:17, endln:68:42 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:68:40, endln:68:42 |vpiDecompile:32 @@ -195333,7 +195333,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:69:17, endln:69:45 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:69:41, endln:69:45 |vpiDecompile:1848 @@ -195347,7 +195347,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:70:17, endln:70:41 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:70:39, endln:70:41 |vpiDecompile:16 @@ -195361,7 +195361,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:71:17, endln:71:43 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:71:39, endln:71:43 |vpiDecompile:1864 @@ -195375,7 +195375,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:72:17, endln:72:38 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:72:37, endln:72:38 |vpiDecompile:8 @@ -195389,7 +195389,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:73:17, endln:73:37 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:73:33, endln:73:37 |vpiDecompile:1872 @@ -195403,7 +195403,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:74:17, endln:74:34 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:74:31, endln:74:34 |vpiDecompile:120 @@ -195417,7 +195417,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:75:17, endln:75:38 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:75:34, endln:75:38 |vpiDecompile:1872 @@ -195431,7 +195431,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:76:17, endln:76:34 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:76:32, endln:76:34 |vpiDecompile:16 @@ -195445,7 +195445,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:77:17, endln:77:50 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:77:46, endln:77:50 |vpiDecompile:1888 @@ -195459,7 +195459,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:78:17, endln:78:46 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:78:44, endln:78:46 |vpiDecompile:32 @@ -195473,7 +195473,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:79:17, endln:79:50 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:79:46, endln:79:50 |vpiDecompile:1920 @@ -195487,7 +195487,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:80:17, endln:80:46 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:80:44, endln:80:46 |vpiDecompile:32 @@ -195501,7 +195501,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:81:17, endln:81:43 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:81:39, endln:81:43 |vpiDecompile:1984 @@ -195515,7 +195515,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:82:17, endln:82:38 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:82:37, endln:82:38 |vpiDecompile:8 @@ -195529,7 +195529,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:83:17, endln:83:39 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:83:35, endln:83:39 |vpiDecompile:1992 @@ -195543,7 +195543,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:84:17, endln:84:35 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:84:33, endln:84:35 |vpiDecompile:56 @@ -195557,7 +195557,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:85:17, endln:85:37 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:85:33, endln:85:37 |vpiDecompile:1992 @@ -195571,7 +195571,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:86:17, endln:86:33 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:86:31, endln:86:33 |vpiDecompile:24 @@ -195585,7 +195585,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:87:17, endln:87:45 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:87:41, endln:87:45 |vpiDecompile:2016 @@ -195599,7 +195599,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:88:17, endln:88:41 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:88:39, endln:88:41 |vpiDecompile:32 @@ -195613,7 +195613,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:89:17, endln:89:30 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:89:29, endln:89:30 |vpiDecompile:2 @@ -195627,7 +195627,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:322:26, endln:322:60 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:322:55, endln:322:60 |vpiLhs: @@ -195635,7 +195635,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:323:26, endln:323:61 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:323:56, endln:323:61 |vpiLhs: @@ -195643,7 +195643,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:324:26, endln:324:59 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:324:54, endln:324:59 |vpiLhs: @@ -195651,7 +195651,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:325:26, endln:325:60 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:325:55, endln:325:60 |vpiLhs: @@ -195659,7 +195659,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:326:26, endln:326:57 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:326:51, endln:326:57 |vpiLhs: @@ -195667,7 +195667,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:327:26, endln:327:59 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:327:53, endln:327:59 |vpiLhs: @@ -195675,7 +195675,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:328:26, endln:328:71 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:328:65, endln:328:71 |vpiLhs: @@ -195683,7 +195683,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:329:26, endln:329:68 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:329:62, endln:329:68 |vpiLhs: @@ -195691,7 +195691,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:330:26, endln:330:72 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:330:66, endln:330:72 |vpiLhs: @@ -195699,7 +195699,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:331:26, endln:331:72 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:331:66, endln:331:72 |vpiLhs: @@ -195707,7 +195707,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:332:26, endln:332:72 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:332:66, endln:332:72 |vpiLhs: @@ -195715,7 +195715,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:333:26, endln:333:72 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:333:66, endln:333:72 |vpiLhs: @@ -195723,7 +195723,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:334:26, endln:334:72 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:334:66, endln:334:72 |vpiLhs: @@ -195731,7 +195731,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:335:26, endln:335:71 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:335:65, endln:335:71 |vpiLhs: @@ -195739,7 +195739,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:336:26, endln:336:64 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:336:58, endln:336:64 |vpiLhs: @@ -195747,7 +195747,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:337:26, endln:337:63 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:337:57, endln:337:63 |vpiLhs: @@ -195755,7 +195755,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:338:26, endln:338:64 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:338:58, endln:338:64 |vpiLhs: @@ -195763,7 +195763,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:339:26, endln:339:73 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:339:67, endln:339:73 |vpiLhs: @@ -195771,7 +195771,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:340:26, endln:340:75 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:340:69, endln:340:75 |vpiLhs: @@ -195779,7 +195779,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:341:26, endln:341:75 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:341:69, endln:341:75 |vpiLhs: @@ -195787,7 +195787,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:342:26, endln:342:73 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:342:67, endln:342:73 |vpiLhs: @@ -195795,7 +195795,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:343:26, endln:343:74 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:343:68, endln:343:74 |vpiLhs: @@ -195803,7 +195803,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:344:26, endln:344:74 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:344:68, endln:344:74 |vpiLhs: @@ -195811,7 +195811,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:345:26, endln:345:72 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:345:66, endln:345:72 |vpiLhs: @@ -195819,7 +195819,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:346:26, endln:346:72 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:346:66, endln:346:72 |vpiLhs: @@ -195827,7 +195827,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:347:26, endln:347:66 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:347:60, endln:347:66 |vpiLhs: @@ -195835,7 +195835,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:348:26, endln:348:66 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:348:60, endln:348:66 |vpiLhs: @@ -195843,7 +195843,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:349:26, endln:349:67 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:349:61, endln:349:67 |vpiLhs: @@ -195851,7 +195851,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:350:26, endln:350:67 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:350:61, endln:350:67 |vpiLhs: @@ -195859,7 +195859,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:351:26, endln:351:67 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:351:61, endln:351:67 |vpiLhs: @@ -195867,7 +195867,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:352:26, endln:352:67 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:352:61, endln:352:67 |vpiLhs: @@ -195875,7 +195875,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:353:26, endln:353:67 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:353:61, endln:353:67 |vpiLhs: @@ -195883,7 +195883,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:354:26, endln:354:67 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:354:61, endln:354:67 |vpiLhs: @@ -195891,7 +195891,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:357:26, endln:357:66 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:357:58, endln:357:66 |vpiLhs: @@ -195899,7 +195899,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:358:26, endln:358:65 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:358:58, endln:358:65 |vpiLhs: @@ -195907,7 +195907,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:359:26, endln:359:64 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:359:56, endln:359:64 |vpiLhs: @@ -195915,7 +195915,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:360:26, endln:360:62 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_constant: , line:360:56, endln:360:62 |vpiLhs: @@ -195923,7 +195923,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:400:25, endln:434:4 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiRhs: \_operation: , line:400:48, endln:434:4 |vpiParent: @@ -196395,7 +196395,7 @@ design: (work@otp_ctrl) |vpiTaskFunc: \_function: (otp_ctrl_pkg::vbits), line:14:1, endln:18:14 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiName:vbits |vpiFullName:otp_ctrl_pkg::vbits |vpiVisibility:1 @@ -196403,7 +196403,7 @@ design: (work@otp_ctrl) |vpiReturn: \_integer_var: , line:14:20, endln:14:27 |vpiParent: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiIODecl: \_io_decl: (value), line:14:42, endln:14:47 |vpiParent: @@ -196454,11 +196454,11 @@ design: (work@otp_ctrl) |vpiFunction: \_function: (prim_util_pkg::_clog2), line:5:3, endln:12:14 |vpiInstance: - \_module: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 + \_module_inst: work@otp_ctrl_part_buf (work@otp_ctrl.gen_partitions[5].gen_buffered.u_part_buf), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:885:7, endln:888:23 |vpiGenScopeArray: \_gen_scope_array: (work@otp_ctrl.gen_partitions[6]), line:882:39, endln:891:4 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiName:gen_partitions[6] |vpiFullName:work@otp_ctrl.gen_partitions[6] |vpiGenScope: diff --git a/tests/BlackParrotParam/BlackParrotParam.log b/tests/BlackParrotParam/BlackParrotParam.log index 0b5313e07d..e1c3242333 100644 --- a/tests/BlackParrotParam/BlackParrotParam.log +++ b/tests/BlackParrotParam/BlackParrotParam.log @@ -8890,7 +8890,7 @@ io_decl 11 logic_net 3 logic_typespec 492 logic_var 1 -module 16 +module_inst 16 operation 333 package 17 packed_array_typespec 41 @@ -8931,7 +8931,7 @@ io_decl 22 logic_net 3 logic_typespec 492 logic_var 1 -module 16 +module_inst 16 operation 335 package 17 packed_array_typespec 41 @@ -22522,7 +22522,7 @@ design: (work@bp_be_ptw) |vpiTypedef: \_enum_typespec: (bp_common_pkg::bp_coh_states_e), line:757:1, endln:767:19 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiName:bp_common_pkg::bp_coh_states_e |vpiInstance: \_package: bp_be_pkg (bp_be_pkg::), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:2530:1, endln:3363:23 @@ -22588,7 +22588,7 @@ design: (work@bp_be_ptw) |vpiTypedef: \_enum_typespec: (bp_common_pkg::bp_fe_command_queue_opcodes_e), line:341:1, endln:350:33 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiName:bp_common_pkg::bp_fe_command_queue_opcodes_e |vpiInstance: \_package: bp_be_pkg (bp_be_pkg::), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:2530:1, endln:3363:23 @@ -22660,7 +22660,7 @@ design: (work@bp_be_ptw) |vpiTypedef: \_enum_typespec: (bp_common_pkg::bp_fe_command_queue_subopcodes_e), line:386:1, endln:395:36 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiName:bp_common_pkg::bp_fe_command_queue_subopcodes_e |vpiInstance: \_package: bp_be_pkg (bp_be_pkg::), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:2530:1, endln:3363:23 @@ -22732,7 +22732,7 @@ design: (work@bp_be_ptw) |vpiTypedef: \_enum_typespec: (bp_common_pkg::bp_fe_exception_code_e), line:369:1, endln:375:26 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiName:bp_common_pkg::bp_fe_exception_code_e |vpiInstance: \_package: bp_be_pkg (bp_be_pkg::), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:2530:1, endln:3363:23 @@ -22786,7 +22786,7 @@ design: (work@bp_be_ptw) |vpiTypedef: \_enum_typespec: (bp_common_pkg::bp_fe_misprediction_reason_e), line:355:1, endln:359:32 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiName:bp_common_pkg::bp_fe_misprediction_reason_e |vpiInstance: \_package: bp_be_pkg (bp_be_pkg::), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:2530:1, endln:3363:23 @@ -22810,7 +22810,7 @@ design: (work@bp_be_ptw) |vpiTypedef: \_enum_typespec: (bp_common_pkg::bp_fe_queue_type_e), line:324:1, endln:328:22 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiName:bp_common_pkg::bp_fe_queue_type_e |vpiInstance: \_package: bp_be_pkg (bp_be_pkg::), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:2530:1, endln:3363:23 @@ -22834,7 +22834,7 @@ design: (work@bp_be_ptw) |vpiTypedef: \_enum_typespec: (bp_common_pkg::bp_lce_cce_lru_dirty_e), line:729:1, endln:733:26 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiName:bp_common_pkg::bp_lce_cce_lru_dirty_e |vpiInstance: \_package: bp_be_pkg (bp_be_pkg::), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:2530:1, endln:3363:23 @@ -22858,7 +22858,7 @@ design: (work@bp_be_ptw) |vpiTypedef: \_enum_typespec: (bp_common_pkg::bp_lce_cce_req_non_excl_e), line:718:1, endln:722:29 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiName:bp_common_pkg::bp_lce_cce_req_non_excl_e |vpiInstance: \_package: bp_be_pkg (bp_be_pkg::), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:2530:1, endln:3363:23 @@ -22882,7 +22882,7 @@ design: (work@bp_be_ptw) |vpiTypedef: \_enum_typespec: (bp_common_pkg::bp_lce_cce_req_type_e), line:701:1, endln:708:25 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiName:bp_common_pkg::bp_lce_cce_req_type_e |vpiInstance: \_package: bp_be_pkg (bp_be_pkg::), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:2530:1, endln:3363:23 @@ -22936,7 +22936,7 @@ design: (work@bp_be_ptw) |vpiTypedef: \_enum_typespec: (bp_common_pkg::bp_lce_cce_resp_type_e), line:814:1, endln:822:26 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiName:bp_common_pkg::bp_lce_cce_resp_type_e |vpiInstance: \_package: bp_be_pkg (bp_be_pkg::), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:2530:1, endln:3363:23 @@ -22996,7 +22996,7 @@ design: (work@bp_be_ptw) |vpiTypedef: \_enum_typespec: (bp_common_pkg::bp_lce_cce_uc_req_size_e), line:739:1, endln:745:28 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiName:bp_common_pkg::bp_lce_cce_uc_req_size_e |vpiInstance: \_package: bp_be_pkg (bp_be_pkg::), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:2530:1, endln:3363:23 @@ -23050,7 +23050,7 @@ design: (work@bp_be_ptw) |vpiTypedef: \_enum_typespec: (bp_common_pkg::bp_lce_cmd_type_e), line:788:1, endln:801:21 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiName:bp_common_pkg::bp_lce_cmd_type_e |vpiInstance: \_package: bp_be_pkg (bp_be_pkg::), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:2530:1, endln:3363:23 @@ -23140,7 +23140,7 @@ design: (work@bp_be_ptw) |vpiTypedef: \_struct_typespec: (bp_common_rv64_pkg::bp_mcause_s), line:1849:9, endln:1849:15 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiName:bp_common_rv64_pkg::bp_mcause_s |vpiInstance: \_package: bp_be_pkg (bp_be_pkg::), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:2530:1, endln:3363:23 @@ -23200,7 +23200,7 @@ design: (work@bp_be_ptw) |vpiTypedef: \_logic_typespec: (bp_common_rv64_pkg::bp_mcounter_s), line:1866:9, endln:1866:21 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiName:bp_common_rv64_pkg::bp_mcounter_s |vpiInstance: \_package: bp_be_pkg (bp_be_pkg::), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:2530:1, endln:3363:23 @@ -23225,7 +23225,7 @@ design: (work@bp_be_ptw) |vpiTypedef: \_struct_typespec: (bp_common_rv64_pkg::bp_mcounteren_s), line:1645:9, endln:1645:15 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiName:bp_common_rv64_pkg::bp_mcounteren_s |vpiInstance: \_package: bp_be_pkg (bp_be_pkg::), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:2530:1, endln:3363:23 @@ -23265,7 +23265,7 @@ design: (work@bp_be_ptw) |vpiTypedef: \_struct_typespec: (bp_common_rv64_pkg::bp_mcountinhibit_s), line:1894:9, endln:1894:15 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiName:bp_common_rv64_pkg::bp_mcountinhibit_s |vpiInstance: \_package: bp_be_pkg (bp_be_pkg::), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:2530:1, endln:3363:23 @@ -23305,7 +23305,7 @@ design: (work@bp_be_ptw) |vpiTypedef: \_logic_typespec: (bp_common_rv64_pkg::bp_mcycle_s), line:1866:9, endln:1866:21 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiName:bp_common_rv64_pkg::bp_mcycle_s |vpiTypedefAlias: \_logic_typespec: (bp_mcounter_s), line:1866:9, endln:1866:21 @@ -23359,7 +23359,7 @@ design: (work@bp_be_ptw) |vpiTypedef: \_struct_typespec: (bp_common_rv64_pkg::bp_medeleg_s), line:1469:9, endln:1469:15 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiName:bp_common_rv64_pkg::bp_medeleg_s |vpiInstance: \_package: bp_be_pkg (bp_be_pkg::), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:2530:1, endln:3363:23 @@ -23475,7 +23475,7 @@ design: (work@bp_be_ptw) |vpiTypedef: \_struct_typespec: (bp_common_rv64_pkg::bp_mepc_s), line:1748:9, endln:1748:15 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiName:bp_common_rv64_pkg::bp_mepc_s |vpiInstance: \_package: bp_be_pkg (bp_be_pkg::), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:2530:1, endln:3363:23 @@ -23535,7 +23535,7 @@ design: (work@bp_be_ptw) |vpiTypedef: \_struct_typespec: (bp_common_rv64_pkg::bp_mideleg_s), line:1516:9, endln:1516:15 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiName:bp_common_rv64_pkg::bp_mideleg_s |vpiInstance: \_package: bp_be_pkg (bp_be_pkg::), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:2530:1, endln:3363:23 @@ -23639,7 +23639,7 @@ design: (work@bp_be_ptw) |vpiTypedef: \_struct_typespec: (bp_common_rv64_pkg::bp_mie_s), line:1577:9, endln:1577:15 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiName:bp_common_rv64_pkg::bp_mie_s |vpiInstance: \_package: bp_be_pkg (bp_be_pkg::), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:2530:1, endln:3363:23 @@ -23743,7 +23743,7 @@ design: (work@bp_be_ptw) |vpiTypedef: \_logic_typespec: (bp_common_rv64_pkg::bp_minstret_s), line:1866:9, endln:1866:21 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiName:bp_common_rv64_pkg::bp_minstret_s |vpiTypedefAlias: \_logic_typespec: (bp_mcounter_s), line:1866:9, endln:1866:21 @@ -23797,7 +23797,7 @@ design: (work@bp_be_ptw) |vpiTypedef: \_struct_typespec: (bp_common_rv64_pkg::bp_mip_s), line:1699:9, endln:1699:15 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiName:bp_common_rv64_pkg::bp_mip_s |vpiInstance: \_package: bp_be_pkg (bp_be_pkg::), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:2530:1, endln:3363:23 @@ -23901,7 +23901,7 @@ design: (work@bp_be_ptw) |vpiTypedef: \_logic_typespec: (bp_common_rv64_pkg::bp_mscratch_s), line:1665:9, endln:1665:21 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiName:bp_common_rv64_pkg::bp_mscratch_s |vpiInstance: \_package: bp_be_pkg (bp_be_pkg::), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:2530:1, endln:3363:23 @@ -23926,7 +23926,7 @@ design: (work@bp_be_ptw) |vpiTypedef: \_struct_typespec: (bp_common_rv64_pkg::bp_mstatus_s), line:1430:9, endln:1430:15 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiName:bp_common_rv64_pkg::bp_mstatus_s |vpiInstance: \_package: bp_be_pkg (bp_be_pkg::), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:2530:1, endln:3363:23 @@ -24066,7 +24066,7 @@ design: (work@bp_be_ptw) |vpiTypedef: \_struct_typespec: (bp_common_rv64_pkg::bp_mtval_s), line:1735:9, endln:1735:15 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiName:bp_common_rv64_pkg::bp_mtval_s |vpiInstance: \_package: bp_be_pkg (bp_be_pkg::), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:2530:1, endln:3363:23 @@ -24126,7 +24126,7 @@ design: (work@bp_be_ptw) |vpiTypedef: \_struct_typespec: (bp_common_rv64_pkg::bp_mtvec_s), line:1622:9, endln:1622:15 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiName:bp_common_rv64_pkg::bp_mtvec_s |vpiInstance: \_package: bp_be_pkg (bp_be_pkg::), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:2530:1, endln:3363:23 @@ -24170,12 +24170,12 @@ design: (work@bp_be_ptw) |vpiTypedef: \_struct_typespec: (bp_common_rv64_pkg::bp_pmpaddr0_s), line:1815:9, endln:1815:15 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiName:bp_common_rv64_pkg::bp_pmpaddr0_s |vpiTypedefAlias: \_struct_typespec: (bp_common_rv64_pkg::bp_pmpaddr_s), line:1815:9, endln:1815:15 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiName:bp_common_rv64_pkg::bp_pmpaddr_s |vpiInstance: \_package: bp_be_pkg (bp_be_pkg::), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:2530:1, endln:3363:23 @@ -24258,7 +24258,7 @@ design: (work@bp_be_ptw) |vpiTypedef: \_struct_typespec: (bp_common_rv64_pkg::bp_pmpaddr1_s), line:1815:9, endln:1815:15 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiName:bp_common_rv64_pkg::bp_pmpaddr1_s |vpiTypedefAlias: \_struct_typespec: (bp_common_rv64_pkg::bp_pmpaddr_s), line:1815:9, endln:1815:15 @@ -24304,7 +24304,7 @@ design: (work@bp_be_ptw) |vpiTypedef: \_struct_typespec: (bp_common_rv64_pkg::bp_pmpaddr2_s), line:1815:9, endln:1815:15 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiName:bp_common_rv64_pkg::bp_pmpaddr2_s |vpiTypedefAlias: \_struct_typespec: (bp_common_rv64_pkg::bp_pmpaddr_s), line:1815:9, endln:1815:15 @@ -24350,7 +24350,7 @@ design: (work@bp_be_ptw) |vpiTypedef: \_struct_typespec: (bp_common_rv64_pkg::bp_pmpaddr3_s), line:1815:9, endln:1815:15 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiName:bp_common_rv64_pkg::bp_pmpaddr3_s |vpiTypedefAlias: \_struct_typespec: (bp_common_rv64_pkg::bp_pmpaddr_s), line:1815:9, endln:1815:15 @@ -24398,12 +24398,12 @@ design: (work@bp_be_ptw) |vpiTypedef: \_struct_typespec: (bp_common_rv64_pkg::bp_pmpcfg0_s), line:1786:9, endln:1786:15 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiName:bp_common_rv64_pkg::bp_pmpcfg0_s |vpiTypedefAlias: \_struct_typespec: (bp_common_rv64_pkg::bp_pmpcfg_s), line:1786:9, endln:1786:15 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiName:bp_common_rv64_pkg::bp_pmpcfg_s |vpiInstance: \_package: bp_be_pkg (bp_be_pkg::), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:2530:1, endln:3363:23 @@ -24442,7 +24442,7 @@ design: (work@bp_be_ptw) |vpiElemTypespec: \_struct_typespec: (bp_common_rv64_pkg::rv64_pmpcfg_entry_s), line:1760:9, endln:1760:15 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiName:bp_common_rv64_pkg::rv64_pmpcfg_entry_s |vpiInstance: \_package: bp_be_pkg (bp_be_pkg::), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:2530:1, endln:3363:23 @@ -24776,7 +24776,7 @@ design: (work@bp_be_ptw) |vpiTypedef: \_struct_typespec: (bp_common_rv64_pkg::bp_satp_s), line:1329:9, endln:1329:15 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiName:bp_common_rv64_pkg::bp_satp_s |vpiInstance: \_package: bp_be_pkg (bp_be_pkg::), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:2530:1, endln:3363:23 @@ -24836,7 +24836,7 @@ design: (work@bp_be_ptw) |vpiTypedef: \_struct_typespec: (bp_common_rv64_pkg::bp_scause_s), line:1292:9, endln:1292:15 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiName:bp_common_rv64_pkg::bp_scause_s |vpiInstance: \_package: bp_be_pkg (bp_be_pkg::), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:2530:1, endln:3363:23 @@ -24896,7 +24896,7 @@ design: (work@bp_be_ptw) |vpiTypedef: \_struct_typespec: (bp_common_rv64_pkg::bp_scounteren_s), line:1247:9, endln:1247:15 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiName:bp_common_rv64_pkg::bp_scounteren_s |vpiInstance: \_package: bp_be_pkg (bp_be_pkg::), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:2530:1, endln:3363:23 @@ -24936,7 +24936,7 @@ design: (work@bp_be_ptw) |vpiTypedef: \_logic_typespec: (bp_common_rv64_pkg::bp_sepc_s), line:1276:9, endln:1276:21 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiName:bp_common_rv64_pkg::bp_sepc_s |vpiInstance: \_package: bp_be_pkg (bp_be_pkg::), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:2530:1, endln:3363:23 @@ -24961,7 +24961,7 @@ design: (work@bp_be_ptw) |vpiTypedef: \_logic_typespec: (bp_common_rv64_pkg::bp_sscratch_s), line:1267:9, endln:1267:21 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiName:bp_common_rv64_pkg::bp_sscratch_s |vpiInstance: \_package: bp_be_pkg (bp_be_pkg::), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:2530:1, endln:3363:23 @@ -24986,7 +24986,7 @@ design: (work@bp_be_ptw) |vpiTypedef: \_logic_typespec: (bp_common_rv64_pkg::bp_stval_s), line:1309:9, endln:1309:21 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiName:bp_common_rv64_pkg::bp_stval_s |vpiInstance: \_package: bp_be_pkg (bp_be_pkg::), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:2530:1, endln:3363:23 @@ -25011,7 +25011,7 @@ design: (work@bp_be_ptw) |vpiTypedef: \_struct_typespec: (bp_common_rv64_pkg::bp_stvec_s), line:1225:9, endln:1225:15 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiName:bp_common_rv64_pkg::bp_stvec_s |vpiInstance: \_package: bp_be_pkg (bp_be_pkg::), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:2530:1, endln:3363:23 @@ -25363,7 +25363,7 @@ design: (work@bp_be_ptw) |vpiTypedef: \_struct_typespec: (bp_common_rv64_pkg::rv64_instr_itype_s), line:1989:11, endln:1989:17 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiName:bp_common_rv64_pkg::rv64_instr_itype_s |vpiInstance: \_package: bp_be_pkg (bp_be_pkg::), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:2530:1, endln:3363:23 @@ -25515,7 +25515,7 @@ design: (work@bp_be_ptw) |vpiTypedef: \_struct_typespec: (bp_common_rv64_pkg::rv64_instr_rtype_s), line:1980:11, endln:1980:17 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiName:bp_common_rv64_pkg::rv64_instr_rtype_s |vpiInstance: \_package: bp_be_pkg (bp_be_pkg::), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:2530:1, endln:3363:23 @@ -25703,7 +25703,7 @@ design: (work@bp_be_ptw) |vpiTypedef: \_struct_typespec: (bp_common_rv64_pkg::rv64_instr_s), line:2012:11, endln:2012:17 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiName:bp_common_rv64_pkg::rv64_instr_s |vpiInstance: \_package: bp_be_pkg (bp_be_pkg::), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:2530:1, endln:3363:23 @@ -25752,7 +25752,7 @@ design: (work@bp_be_ptw) |vpiTypespec: \_struct_typespec: (bp_common_rv64_pkg::rv64_instr_stype_s), line:1997:11, endln:1997:17 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiName:bp_common_rv64_pkg::rv64_instr_stype_s |vpiInstance: \_package: bp_be_pkg (bp_be_pkg::), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:2530:1, endln:3363:23 @@ -25950,7 +25950,7 @@ design: (work@bp_be_ptw) |vpiTypespec: \_struct_typespec: (bp_common_rv64_pkg::rv64_instr_utype_s), line:2006:11, endln:2006:17 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiName:bp_common_rv64_pkg::rv64_instr_utype_s |vpiInstance: \_package: bp_be_pkg (bp_be_pkg::), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:2530:1, endln:3363:23 @@ -26080,7 +26080,7 @@ design: (work@bp_be_ptw) |vpiTypedef: \_struct_typespec: (bp_common_rv64_pkg::rv64_mcause_s), line:1843:9, endln:1843:15 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiName:bp_common_rv64_pkg::rv64_mcause_s |vpiInstance: \_package: bp_be_pkg (bp_be_pkg::), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:2530:1, endln:3363:23 @@ -26140,7 +26140,7 @@ design: (work@bp_be_ptw) |vpiTypedef: \_logic_typespec: (bp_common_rv64_pkg::rv64_mcounter_s), line:1865:9, endln:1865:21 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiName:bp_common_rv64_pkg::rv64_mcounter_s |vpiInstance: \_package: bp_be_pkg (bp_be_pkg::), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:2530:1, endln:3363:23 @@ -26165,7 +26165,7 @@ design: (work@bp_be_ptw) |vpiTypedef: \_struct_typespec: (bp_common_rv64_pkg::rv64_mcounteren_s), line:1637:9, endln:1637:15 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiName:bp_common_rv64_pkg::rv64_mcounteren_s |vpiInstance: \_package: bp_be_pkg (bp_be_pkg::), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:2530:1, endln:3363:23 @@ -26257,7 +26257,7 @@ design: (work@bp_be_ptw) |vpiTypedef: \_struct_typespec: (bp_common_rv64_pkg::rv64_mcountinhibit_s), line:1886:9, endln:1886:15 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiName:bp_common_rv64_pkg::rv64_mcountinhibit_s |vpiInstance: \_package: bp_be_pkg (bp_be_pkg::), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:2530:1, endln:3363:23 @@ -26349,7 +26349,7 @@ design: (work@bp_be_ptw) |vpiTypedef: \_logic_typespec: (bp_common_rv64_pkg::rv64_mcycle_s), line:1865:9, endln:1865:21 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiName:bp_common_rv64_pkg::rv64_mcycle_s |vpiTypedefAlias: \_logic_typespec: (rv64_mcounter_s), line:1865:9, endln:1865:21 @@ -26403,7 +26403,7 @@ design: (work@bp_be_ptw) |vpiTypedef: \_logic_typespec: (bp_common_rv64_pkg::rv64_medeleg_s), line:1467:9, endln:1467:21 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiName:bp_common_rv64_pkg::rv64_medeleg_s |vpiInstance: \_package: bp_be_pkg (bp_be_pkg::), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:2530:1, endln:3363:23 @@ -26428,7 +26428,7 @@ design: (work@bp_be_ptw) |vpiTypedef: \_logic_typespec: (bp_common_rv64_pkg::rv64_mepc_s), line:1747:9, endln:1747:21 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiName:bp_common_rv64_pkg::rv64_mepc_s |vpiInstance: \_package: bp_be_pkg (bp_be_pkg::), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:2530:1, endln:3363:23 @@ -26453,7 +26453,7 @@ design: (work@bp_be_ptw) |vpiTypedef: \_struct_typespec: (bp_common_rv64_pkg::rv64_mideleg_s), line:1490:9, endln:1490:15 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiName:bp_common_rv64_pkg::rv64_mideleg_s |vpiInstance: \_package: bp_be_pkg (bp_be_pkg::), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:2530:1, endln:3363:23 @@ -26689,7 +26689,7 @@ design: (work@bp_be_ptw) |vpiTypedef: \_struct_typespec: (bp_common_rv64_pkg::rv64_mie_s), line:1551:9, endln:1551:15 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiName:bp_common_rv64_pkg::rv64_mie_s |vpiInstance: \_package: bp_be_pkg (bp_be_pkg::), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:2530:1, endln:3363:23 @@ -26925,7 +26925,7 @@ design: (work@bp_be_ptw) |vpiTypedef: \_logic_typespec: (bp_common_rv64_pkg::rv64_minstret_s), line:1865:9, endln:1865:21 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiName:bp_common_rv64_pkg::rv64_minstret_s |vpiTypedefAlias: \_logic_typespec: (rv64_mcounter_s), line:1865:9, endln:1865:21 @@ -26979,7 +26979,7 @@ design: (work@bp_be_ptw) |vpiTypedef: \_struct_typespec: (bp_common_rv64_pkg::rv64_mip_s), line:1673:9, endln:1673:15 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiName:bp_common_rv64_pkg::rv64_mip_s |vpiInstance: \_package: bp_be_pkg (bp_be_pkg::), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:2530:1, endln:3363:23 @@ -27215,7 +27215,7 @@ design: (work@bp_be_ptw) |vpiTypedef: \_logic_typespec: (bp_common_rv64_pkg::rv64_mscratch_s), line:1664:9, endln:1664:21 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiName:bp_common_rv64_pkg::rv64_mscratch_s |vpiInstance: \_package: bp_be_pkg (bp_be_pkg::), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:2530:1, endln:3363:23 @@ -27240,7 +27240,7 @@ design: (work@bp_be_ptw) |vpiTypedef: \_struct_typespec: (bp_common_rv64_pkg::rv64_mstatus_s), line:1352:9, endln:1352:15 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiName:bp_common_rv64_pkg::rv64_mstatus_s |vpiInstance: \_package: bp_be_pkg (bp_be_pkg::), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:2530:1, endln:3363:23 @@ -27792,7 +27792,7 @@ design: (work@bp_be_ptw) |vpiTypedef: \_logic_typespec: (bp_common_rv64_pkg::rv64_mtval_s), line:1734:9, endln:1734:21 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiName:bp_common_rv64_pkg::rv64_mtval_s |vpiInstance: \_package: bp_be_pkg (bp_be_pkg::), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:2530:1, endln:3363:23 @@ -27817,7 +27817,7 @@ design: (work@bp_be_ptw) |vpiTypedef: \_struct_typespec: (bp_common_rv64_pkg::rv64_mtvec_s), line:1612:9, endln:1612:15 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiName:bp_common_rv64_pkg::rv64_mtvec_s |vpiInstance: \_package: bp_be_pkg (bp_be_pkg::), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:2530:1, endln:3363:23 @@ -27897,12 +27897,12 @@ design: (work@bp_be_ptw) |vpiTypedef: \_struct_typespec: (bp_common_rv64_pkg::rv64_pmpaddr0_s), line:1804:9, endln:1804:15 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiName:bp_common_rv64_pkg::rv64_pmpaddr0_s |vpiTypedefAlias: \_struct_typespec: (bp_common_rv64_pkg::rv64_pmpaddr_s), line:1804:9, endln:1804:15 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiName:bp_common_rv64_pkg::rv64_pmpaddr_s |vpiInstance: \_package: bp_be_pkg (bp_be_pkg::), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:2530:1, endln:3363:23 @@ -28057,7 +28057,7 @@ design: (work@bp_be_ptw) |vpiTypedef: \_struct_typespec: (bp_common_rv64_pkg::rv64_pmpaddr1_s), line:1804:9, endln:1804:15 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiName:bp_common_rv64_pkg::rv64_pmpaddr1_s |vpiTypedefAlias: \_struct_typespec: (bp_common_rv64_pkg::rv64_pmpaddr_s), line:1804:9, endln:1804:15 @@ -28139,7 +28139,7 @@ design: (work@bp_be_ptw) |vpiTypedef: \_struct_typespec: (bp_common_rv64_pkg::rv64_pmpaddr2_s), line:1804:9, endln:1804:15 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiName:bp_common_rv64_pkg::rv64_pmpaddr2_s |vpiTypedefAlias: \_struct_typespec: (bp_common_rv64_pkg::rv64_pmpaddr_s), line:1804:9, endln:1804:15 @@ -28221,7 +28221,7 @@ design: (work@bp_be_ptw) |vpiTypedef: \_struct_typespec: (bp_common_rv64_pkg::rv64_pmpaddr3_s), line:1804:9, endln:1804:15 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiName:bp_common_rv64_pkg::rv64_pmpaddr3_s |vpiTypedefAlias: \_struct_typespec: (bp_common_rv64_pkg::rv64_pmpaddr_s), line:1804:9, endln:1804:15 @@ -28305,12 +28305,12 @@ design: (work@bp_be_ptw) |vpiTypedef: \_struct_typespec: (bp_common_rv64_pkg::rv64_pmpcfg0_s), line:1779:9, endln:1779:15 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiName:bp_common_rv64_pkg::rv64_pmpcfg0_s |vpiTypedefAlias: \_struct_typespec: (bp_common_rv64_pkg::rv64_pmpcfg_s), line:1779:9, endln:1779:15 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiName:bp_common_rv64_pkg::rv64_pmpcfg_s |vpiInstance: \_package: bp_be_pkg (bp_be_pkg::), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:2530:1, endln:3363:23 @@ -28539,7 +28539,7 @@ design: (work@bp_be_ptw) |vpiTypedef: \_struct_typespec: (bp_common_rv64_pkg::rv64_pmpcfg1_s), line:1779:9, endln:1779:15 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiName:bp_common_rv64_pkg::rv64_pmpcfg1_s |vpiTypedefAlias: \_struct_typespec: (bp_common_rv64_pkg::rv64_pmpcfg_s), line:1779:9, endln:1779:15 @@ -28733,7 +28733,7 @@ design: (work@bp_be_ptw) |vpiTypedef: \_struct_typespec: (bp_common_rv64_pkg::rv64_satp_s), line:1317:9, endln:1317:15 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiName:bp_common_rv64_pkg::rv64_satp_s |vpiInstance: \_package: bp_be_pkg (bp_be_pkg::), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:2530:1, endln:3363:23 @@ -28849,7 +28849,7 @@ design: (work@bp_be_ptw) |vpiTypedef: \_struct_typespec: (bp_common_rv64_pkg::rv64_scause_s), line:1286:9, endln:1286:15 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiName:bp_common_rv64_pkg::rv64_scause_s |vpiInstance: \_package: bp_be_pkg (bp_be_pkg::), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:2530:1, endln:3363:23 @@ -28909,7 +28909,7 @@ design: (work@bp_be_ptw) |vpiTypedef: \_struct_typespec: (bp_common_rv64_pkg::rv64_scounteren_s), line:1240:9, endln:1240:15 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiName:bp_common_rv64_pkg::rv64_scounteren_s |vpiInstance: \_package: bp_be_pkg (bp_be_pkg::), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:2530:1, endln:3363:23 @@ -28985,7 +28985,7 @@ design: (work@bp_be_ptw) |vpiTypedef: \_logic_typespec: (bp_common_rv64_pkg::rv64_sepc_s), line:1275:9, endln:1275:21 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiName:bp_common_rv64_pkg::rv64_sepc_s |vpiInstance: \_package: bp_be_pkg (bp_be_pkg::), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:2530:1, endln:3363:23 @@ -29010,7 +29010,7 @@ design: (work@bp_be_ptw) |vpiTypedef: \_logic_typespec: (bp_common_rv64_pkg::rv64_sscratch_s), line:1266:9, endln:1266:21 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiName:bp_common_rv64_pkg::rv64_sscratch_s |vpiInstance: \_package: bp_be_pkg (bp_be_pkg::), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:2530:1, endln:3363:23 @@ -29035,7 +29035,7 @@ design: (work@bp_be_ptw) |vpiTypedef: \_logic_typespec: (bp_common_rv64_pkg::rv64_stval_s), line:1308:9, endln:1308:21 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiName:bp_common_rv64_pkg::rv64_stval_s |vpiInstance: \_package: bp_be_pkg (bp_be_pkg::), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:2530:1, endln:3363:23 @@ -29060,7 +29060,7 @@ design: (work@bp_be_ptw) |vpiTypedef: \_struct_typespec: (bp_common_rv64_pkg::rv64_stvec_s), line:1215:9, endln:1215:15 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiName:bp_common_rv64_pkg::rv64_stvec_s |vpiInstance: \_package: bp_be_pkg (bp_be_pkg::), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:2530:1, endln:3363:23 @@ -30768,7 +30768,7 @@ design: (work@bp_be_ptw) |vpiTypespec: \_struct_typespec: (bp_common_aviary_pkg::bp_proc_param_s), line:2062:9, endln:2062:15 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiName:bp_common_aviary_pkg::bp_proc_param_s |vpiInstance: \_package: bp_common_aviary_pkg (bp_common_aviary_pkg::), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:2026:1, endln:2528:11 @@ -34346,7 +34346,7 @@ design: (work@bp_be_ptw) |vpiTypedef: \_enum_typespec: (bp_common_aviary_pkg::bp_cfg_e), line:2504:3, endln:2513:14 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiName:bp_common_aviary_pkg::bp_cfg_e |vpiInstance: \_package: bp_common_aviary_pkg (bp_common_aviary_pkg::), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:2026:1, endln:2528:11 @@ -36594,7 +36594,7 @@ design: (work@bp_be_ptw) |vpiTypedef: \_enum_typespec: (bp_be_pkg::bp_be_baddr_e), line:3041:1, endln:3045:17 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiName:bp_be_pkg::bp_be_baddr_e |vpiInstance: \_package: bp_be_pkg (bp_be_pkg::), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:2530:1, endln:3363:23 @@ -36618,7 +36618,7 @@ design: (work@bp_be_ptw) |vpiTypedef: \_enum_typespec: (bp_be_pkg::bp_be_csr_fu_op_e), line:2994:1, endln:3017:21 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiName:bp_be_pkg::bp_be_csr_fu_op_e |vpiInstance: \_package: bp_be_pkg (bp_be_pkg::), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:2530:1, endln:3363:23 @@ -36738,7 +36738,7 @@ design: (work@bp_be_ptw) |vpiTypedef: \_struct_typespec: (bp_be_pkg::bp_be_decode_s), line:3059:9, endln:3059:15 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiName:bp_be_pkg::bp_be_decode_s |vpiInstance: \_package: bp_be_pkg (bp_be_pkg::), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:2530:1, endln:3363:23 @@ -37039,7 +37039,7 @@ design: (work@bp_be_ptw) |vpiTypespec: \_struct_typespec: (bp_be_pkg::bp_be_fu_op_s), line:3019:9, endln:3019:15 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiName:bp_be_pkg::bp_be_fu_op_s |vpiInstance: \_package: bp_be_pkg (bp_be_pkg::), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:2530:1, endln:3363:23 @@ -37064,7 +37064,7 @@ design: (work@bp_be_ptw) |vpiTypespec: \_enum_typespec: (bp_be_pkg::bp_be_int_fu_op_e), line:2951:1, endln:2968:21 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiName:bp_be_pkg::bp_be_int_fu_op_e |vpiInstance: \_package: bp_be_pkg (bp_be_pkg::), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:2530:1, endln:3363:23 @@ -37194,7 +37194,7 @@ design: (work@bp_be_ptw) |vpiTypespec: \_enum_typespec: (bp_be_pkg::bp_be_mmu_fu_op_e), line:2970:1, endln:2992:21 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiName:bp_be_pkg::bp_be_mmu_fu_op_e |vpiInstance: \_package: bp_be_pkg (bp_be_pkg::), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:2530:1, endln:3363:23 @@ -37352,7 +37352,7 @@ design: (work@bp_be_ptw) |vpiTypespec: \_enum_typespec: (bp_be_pkg::bp_be_src1_e), line:3029:1, endln:3033:16 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiName:bp_be_pkg::bp_be_src1_e |vpiInstance: \_package: bp_be_pkg (bp_be_pkg::), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:2530:1, endln:3363:23 @@ -37386,7 +37386,7 @@ design: (work@bp_be_ptw) |vpiTypespec: \_enum_typespec: (bp_be_pkg::bp_be_src2_e), line:3035:1, endln:3039:16 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiName:bp_be_pkg::bp_be_src2_e |vpiInstance: \_package: bp_be_pkg (bp_be_pkg::), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:2530:1, endln:3363:23 @@ -37432,7 +37432,7 @@ design: (work@bp_be_ptw) |vpiTypespec: \_enum_typespec: (bp_be_pkg::bp_be_offset_e), line:3047:1, endln:3051:18 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiName:bp_be_pkg::bp_be_offset_e |vpiInstance: \_package: bp_be_pkg (bp_be_pkg::), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:2530:1, endln:3363:23 @@ -37466,7 +37466,7 @@ design: (work@bp_be_ptw) |vpiTypespec: \_enum_typespec: (bp_be_pkg::bp_be_result_e), line:3053:1, endln:3057:18 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiName:bp_be_pkg::bp_be_result_e |vpiInstance: \_package: bp_be_pkg (bp_be_pkg::), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:2530:1, endln:3363:23 @@ -37495,7 +37495,7 @@ design: (work@bp_be_ptw) |vpiTypedef: \_struct_typespec: (bp_be_pkg::bp_be_ecode_dec_s), line:3091:9, endln:3091:15 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiName:bp_be_pkg::bp_be_ecode_dec_s |vpiInstance: \_package: bp_be_pkg (bp_be_pkg::), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:2530:1, endln:3363:23 @@ -37759,7 +37759,7 @@ design: (work@bp_be_ptw) |vpiTypedef: \_struct_typespec: (bp_be_pkg::bp_be_exception_s), line:3115:9, endln:3115:15 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiName:bp_be_pkg::bp_be_exception_s |vpiInstance: \_package: bp_be_pkg (bp_be_pkg::), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:2530:1, endln:3363:23 @@ -37943,7 +37943,7 @@ design: (work@bp_be_ptw) |vpiTypedef: \_struct_typespec: (bp_be_pkg::bp_sv39_pte_s), line:3169:11, endln:3169:17 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiName:bp_be_pkg::bp_sv39_pte_s |vpiInstance: \_package: bp_be_pkg (bp_be_pkg::), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:2530:1, endln:3363:23 @@ -38271,7 +38271,7 @@ design: (work@bp_be_ptw) |vpiTypedef: \_enum_typespec: (bp_be_dcache_pkg::bp_be_dcache_lce_data_mem_opcode_e), line:4316:3, endln:4327:40 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiName:bp_be_dcache_pkg::bp_be_dcache_lce_data_mem_opcode_e |vpiInstance: \_package: bp_be_dcache_pkg (bp_be_dcache_pkg::), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:3365:1, endln:4368:11 @@ -38318,7 +38318,7 @@ design: (work@bp_be_ptw) |vpiTypedef: \_enum_typespec: (bp_be_dcache_pkg::bp_be_dcache_lce_mode_e), line:4361:3, endln:4364:29 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiName:bp_be_dcache_pkg::bp_be_dcache_lce_mode_e |vpiInstance: \_package: bp_be_dcache_pkg (bp_be_dcache_pkg::), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:3365:1, endln:4368:11 @@ -38341,7 +38341,7 @@ design: (work@bp_be_ptw) |vpiTypedef: \_enum_typespec: (bp_be_dcache_pkg::bp_be_dcache_lce_stat_mem_opcode_e), line:4347:3, endln:4358:40 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiName:bp_be_dcache_pkg::bp_be_dcache_lce_stat_mem_opcode_e |vpiInstance: \_package: bp_be_dcache_pkg (bp_be_dcache_pkg::), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:3365:1, endln:4368:11 @@ -38388,7 +38388,7 @@ design: (work@bp_be_ptw) |vpiTypedef: \_enum_typespec: (bp_be_dcache_pkg::bp_be_dcache_lce_tag_mem_opcode_e), line:4331:3, endln:4342:39 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiName:bp_be_dcache_pkg::bp_be_dcache_lce_tag_mem_opcode_e |vpiInstance: \_package: bp_be_dcache_pkg (bp_be_dcache_pkg::), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:3365:1, endln:4368:11 @@ -38435,7 +38435,7 @@ design: (work@bp_be_ptw) |vpiTypedef: \_enum_typespec: (bp_be_dcache_pkg::bp_be_dcache_opcode_e), line:4290:3, endln:4311:27 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiName:bp_be_dcache_pkg::bp_be_dcache_opcode_e |vpiInstance: \_package: bp_be_dcache_pkg (bp_be_dcache_pkg::), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:3365:1, endln:4368:11 @@ -38984,14 +38984,14 @@ design: (work@bp_be_ptw) \_int_typespec: |vpiSigned:1 |uhdmallModules: -\_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 +\_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiParent: \_design: (work@bp_be_ptw) |vpiFullName:work@bp_be_ptw |vpiParameter: \_parameter: (work@bp_be_ptw.bp_data_cmd_num_flit_gp), line:911:13, endln:911:36 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |UINT:4 |vpiTypespec: \_int_typespec: @@ -39003,7 +39003,7 @@ design: (work@bp_be_ptw) |vpiParameter: \_parameter: (work@bp_be_ptw.bp_data_resp_num_flit_gp), line:910:13, endln:910:37 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |UINT:4 |vpiTypespec: \_int_typespec: @@ -39015,7 +39015,7 @@ design: (work@bp_be_ptw) |vpiParameter: \_parameter: (work@bp_be_ptw.bp_eaddr_width_gp), line:899:14, endln:899:31 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |UINT:64 |vpiTypespec: \_int_typespec: @@ -39028,7 +39028,7 @@ design: (work@bp_be_ptw) |vpiParameter: \_parameter: (work@bp_be_ptw.bp_instr_width_gp), line:900:14, endln:900:31 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |UINT:32 |vpiTypespec: \_int_typespec: @@ -39041,7 +39041,7 @@ design: (work@bp_be_ptw) |vpiParameter: \_parameter: (work@bp_be_ptw.bp_log_file_gp), line:80:12, endln:80:26 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |UINT:2 |vpiTypespec: \_int_typespec: @@ -39054,7 +39054,7 @@ design: (work@bp_be_ptw) |vpiParameter: \_parameter: (work@bp_be_ptw.bp_log_none_gp), line:78:12, endln:78:26 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |UINT:0 |vpiTypespec: \_int_typespec: @@ -39067,7 +39067,7 @@ design: (work@bp_be_ptw) |vpiParameter: \_parameter: (work@bp_be_ptw.bp_log_stdout_gp), line:79:12, endln:79:28 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |UINT:1 |vpiTypespec: \_int_typespec: @@ -39080,7 +39080,7 @@ design: (work@bp_be_ptw) |vpiParameter: \_parameter: (work@bp_be_ptw.bp_page_offset_width_gp), line:908:13, endln:908:36 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |INT:12 |vpiTypespec: \_int_typespec: @@ -39092,7 +39092,7 @@ design: (work@bp_be_ptw) |vpiParameter: \_parameter: (work@bp_be_ptw.bp_page_size_in_bytes_gp), line:907:13, endln:907:37 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |UINT:4096 |vpiTypespec: \_int_typespec: @@ -39104,7 +39104,7 @@ design: (work@bp_be_ptw) |vpiParameter: \_parameter: (work@bp_be_ptw.bp_sv39_paddr_width_gp), line:905:13, endln:905:35 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |UINT:56 |vpiTypespec: \_int_typespec: @@ -39116,7 +39116,7 @@ design: (work@bp_be_ptw) |vpiParameter: \_parameter: (work@bp_be_ptw.bp_sv39_page_table_depth_gp), line:902:13, endln:902:40 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |UINT:3 |vpiTypespec: \_int_typespec: @@ -39128,7 +39128,7 @@ design: (work@bp_be_ptw) |vpiParameter: \_parameter: (work@bp_be_ptw.bp_sv39_ppn_width_gp), line:906:13, endln:906:33 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |UINT:44 |vpiTypespec: \_int_typespec: @@ -39140,7 +39140,7 @@ design: (work@bp_be_ptw) |vpiParameter: \_parameter: (work@bp_be_ptw.bp_sv39_pte_width_gp), line:903:13, endln:903:33 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |UINT:64 |vpiTypespec: \_int_typespec: @@ -39152,7 +39152,7 @@ design: (work@bp_be_ptw) |vpiParameter: \_parameter: (work@bp_be_ptw.bp_sv39_vaddr_width_gp), line:904:13, endln:904:35 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |UINT:39 |vpiTypespec: \_int_typespec: @@ -39164,7 +39164,7 @@ design: (work@bp_be_ptw) |vpiParameter: \_parameter: (work@bp_be_ptw.cfg_link_dev_base_addr_gp), line:915:14, endln:915:39 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |HEX:01?????? |vpiTypespec: \_int_typespec: @@ -39191,7 +39191,7 @@ design: (work@bp_be_ptw) |vpiParameter: \_parameter: (work@bp_be_ptw.clint_dev_base_addr_gp), line:916:14, endln:916:36 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |HEX:02?????? |vpiTypespec: \_int_typespec: @@ -39218,7 +39218,7 @@ design: (work@bp_be_ptw) |vpiParameter: \_parameter: (work@bp_be_ptw.dram_base_addr_gp), line:913:14, endln:913:31 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |HEX:80000000 |vpiTypespec: \_int_typespec: @@ -39245,7 +39245,7 @@ design: (work@bp_be_ptw) |vpiParameter: \_parameter: (work@bp_be_ptw.host_dev_base_addr_gp), line:917:14, endln:917:35 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |HEX:03?????? |vpiTypespec: \_int_typespec: @@ -39272,7 +39272,7 @@ design: (work@bp_be_ptw) |vpiParameter: \_parameter: (work@bp_be_ptw.mipi_reg_base_addr_gp), line:920:14, endln:920:35 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |HEX:02000??? |vpiTypespec: \_int_typespec: @@ -39299,7 +39299,7 @@ design: (work@bp_be_ptw) |vpiParameter: \_parameter: (work@bp_be_ptw.mtime_reg_addr_gp), line:922:14, endln:922:31 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |HEX:0200bff8 |vpiTypespec: \_int_typespec: @@ -39326,7 +39326,7 @@ design: (work@bp_be_ptw) |vpiParameter: \_parameter: (work@bp_be_ptw.mtimecmp_reg_base_addr_gp), line:921:14, endln:921:39 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |HEX:02004??? |vpiTypespec: \_int_typespec: @@ -39353,7 +39353,7 @@ design: (work@bp_be_ptw) |vpiParameter: \_parameter: (work@bp_be_ptw.plic_dev_base_addr_gp), line:918:14, endln:918:35 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |HEX:0c?????? |vpiTypespec: \_int_typespec: @@ -39380,7 +39380,7 @@ design: (work@bp_be_ptw) |vpiParameter: \_parameter: (work@bp_be_ptw.plic_reg_base_addr_gp), line:923:14, endln:923:35 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |HEX:0c000??? |vpiTypespec: \_int_typespec: @@ -39407,7 +39407,7 @@ design: (work@bp_be_ptw) |vpiParameter: \_parameter: (work@bp_be_ptw.rv64_byte_width_gp), line:1962:14, endln:1962:32 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |UINT:8 |vpiTypespec: \_int_typespec: @@ -39420,7 +39420,7 @@ design: (work@bp_be_ptw) |vpiParameter: \_parameter: (work@bp_be_ptw.rv64_csr_addr_width_gp), line:1973:14, endln:1973:36 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |UINT:12 |vpiTypespec: \_int_typespec: @@ -39433,7 +39433,7 @@ design: (work@bp_be_ptw) |vpiParameter: \_parameter: (work@bp_be_ptw.rv64_dword_width_gp), line:1965:14, endln:1965:33 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |UINT:64 |vpiTypespec: \_int_typespec: @@ -39446,7 +39446,7 @@ design: (work@bp_be_ptw) |vpiParameter: \_parameter: (work@bp_be_ptw.rv64_eaddr_width_gp), line:1961:14, endln:1961:33 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |UINT:64 |vpiTypespec: \_int_typespec: @@ -39459,7 +39459,7 @@ design: (work@bp_be_ptw) |vpiParameter: \_parameter: (work@bp_be_ptw.rv64_funct3_width_gp), line:1971:14, endln:1971:34 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |UINT:3 |vpiTypespec: \_int_typespec: @@ -39472,7 +39472,7 @@ design: (work@bp_be_ptw) |vpiParameter: \_parameter: (work@bp_be_ptw.rv64_funct7_width_gp), line:1972:14, endln:1972:34 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |UINT:7 |vpiTypespec: \_int_typespec: @@ -39485,7 +39485,7 @@ design: (work@bp_be_ptw) |vpiParameter: \_parameter: (work@bp_be_ptw.rv64_hword_width_gp), line:1963:14, endln:1963:33 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |UINT:16 |vpiTypespec: \_int_typespec: @@ -39498,7 +39498,7 @@ design: (work@bp_be_ptw) |vpiParameter: \_parameter: (work@bp_be_ptw.rv64_imm11to5_width_gp), line:1976:14, endln:1976:36 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |UINT:7 |vpiTypespec: \_int_typespec: @@ -39511,7 +39511,7 @@ design: (work@bp_be_ptw) |vpiParameter: \_parameter: (work@bp_be_ptw.rv64_imm12_width_gp), line:1975:14, endln:1975:33 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |UINT:12 |vpiTypespec: \_int_typespec: @@ -39524,7 +39524,7 @@ design: (work@bp_be_ptw) |vpiParameter: \_parameter: (work@bp_be_ptw.rv64_imm20_width_gp), line:1974:14, endln:1974:33 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |UINT:20 |vpiTypespec: \_int_typespec: @@ -39537,7 +39537,7 @@ design: (work@bp_be_ptw) |vpiParameter: \_parameter: (work@bp_be_ptw.rv64_imm4to0_width_gp), line:1977:14, endln:1977:35 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |UINT:5 |vpiTypespec: \_int_typespec: @@ -39550,7 +39550,7 @@ design: (work@bp_be_ptw) |vpiParameter: \_parameter: (work@bp_be_ptw.rv64_instr_width_gp), line:1960:14, endln:1960:33 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |UINT:32 |vpiTypespec: \_int_typespec: @@ -39563,7 +39563,7 @@ design: (work@bp_be_ptw) |vpiParameter: \_parameter: (work@bp_be_ptw.rv64_opcode_width_gp), line:1970:14, endln:1970:34 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |UINT:7 |vpiTypespec: \_int_typespec: @@ -39576,7 +39576,7 @@ design: (work@bp_be_ptw) |vpiParameter: \_parameter: (work@bp_be_ptw.rv64_priv_width_gp), line:1978:14, endln:1978:32 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |UINT:2 |vpiTypespec: \_int_typespec: @@ -39589,7 +39589,7 @@ design: (work@bp_be_ptw) |vpiParameter: \_parameter: (work@bp_be_ptw.rv64_reg_addr_width_gp), line:1967:14, endln:1967:36 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |UINT:5 |vpiTypespec: \_int_typespec: @@ -39602,7 +39602,7 @@ design: (work@bp_be_ptw) |vpiParameter: \_parameter: (work@bp_be_ptw.rv64_reg_data_width_gp), line:1966:14, endln:1966:36 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |UINT:64 |vpiTypespec: \_int_typespec: @@ -39615,7 +39615,7 @@ design: (work@bp_be_ptw) |vpiParameter: \_parameter: (work@bp_be_ptw.rv64_rf_els_gp), line:1959:14, endln:1959:28 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |UINT:32 |vpiTypespec: \_int_typespec: @@ -39628,7 +39628,7 @@ design: (work@bp_be_ptw) |vpiParameter: \_parameter: (work@bp_be_ptw.rv64_shamt_width_gp), line:1968:14, endln:1968:33 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |UINT:6 |vpiTypespec: \_int_typespec: @@ -39641,7 +39641,7 @@ design: (work@bp_be_ptw) |vpiParameter: \_parameter: (work@bp_be_ptw.rv64_shamtw_width_gp), line:1969:14, endln:1969:34 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |UINT:5 |vpiTypespec: \_int_typespec: @@ -39654,7 +39654,7 @@ design: (work@bp_be_ptw) |vpiParameter: \_parameter: (work@bp_be_ptw.rv64_word_width_gp), line:1964:14, endln:1964:32 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |UINT:32 |vpiTypespec: \_int_typespec: @@ -39667,7 +39667,7 @@ design: (work@bp_be_ptw) |vpiParameter: \_parameter: (work@bp_be_ptw.all_cfgs_gp), line:2516:44, endln:2516:55 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiTypespec: \_packed_array_typespec: , line:2516:13, endln:2516:28 |vpiParent: @@ -40388,7 +40388,7 @@ design: (work@bp_be_ptw) |vpiParameter: \_parameter: (work@bp_be_ptw.bp_dual_core_cfg_p), line:2300:30, endln:2300:48 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiTypespec: \_struct_typespec: (bp_common_aviary_pkg::bp_proc_param_s), line:2062:9, endln:2062:15 |vpiParent: @@ -41084,7 +41084,7 @@ design: (work@bp_be_ptw) |vpiParameter: \_parameter: (work@bp_be_ptw.bp_half_core_cfg_p), line:2198:30, endln:2198:48 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiTypespec: \_struct_typespec: (bp_common_aviary_pkg::bp_proc_param_s), line:2062:9, endln:2062:15 |vpiParent: @@ -41780,7 +41780,7 @@ design: (work@bp_be_ptw) |vpiParameter: \_parameter: (work@bp_be_ptw.bp_inv_cfg_p), line:2195:30, endln:2195:42 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiTypespec: \_struct_typespec: (bp_common_aviary_pkg::bp_proc_param_s), line:2062:9, endln:2062:15 |vpiParent: @@ -42476,7 +42476,7 @@ design: (work@bp_be_ptw) |vpiParameter: \_parameter: (work@bp_be_ptw.bp_oct_core_cfg_p), line:2402:30, endln:2402:47 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiTypespec: \_struct_typespec: (bp_common_aviary_pkg::bp_proc_param_s), line:2062:9, endln:2062:15 |vpiParent: @@ -43172,7 +43172,7 @@ design: (work@bp_be_ptw) |vpiParameter: \_parameter: (work@bp_be_ptw.bp_quad_core_cfg_p), line:2351:30, endln:2351:48 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiTypespec: \_struct_typespec: (bp_common_aviary_pkg::bp_proc_param_s), line:2062:9, endln:2062:15 |vpiParent: @@ -43868,7 +43868,7 @@ design: (work@bp_be_ptw) |vpiParameter: \_parameter: (work@bp_be_ptw.bp_sexta_core_cfg_p), line:2453:30, endln:2453:49 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiTypespec: \_struct_typespec: (bp_common_aviary_pkg::bp_proc_param_s), line:2062:9, endln:2062:15 |vpiParent: @@ -44564,7 +44564,7 @@ design: (work@bp_be_ptw) |vpiParameter: \_parameter: (work@bp_be_ptw.bp_single_core_cfg_p), line:2249:30, endln:2249:50 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiTypespec: \_struct_typespec: (bp_common_aviary_pkg::bp_proc_param_s), line:2062:9, endln:2062:15 |vpiParent: @@ -45260,7 +45260,7 @@ design: (work@bp_be_ptw) |vpiParameter: \_parameter: (work@bp_be_ptw.lg_max_cfgs), line:2193:14, endln:2193:25 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |INT:7 |vpiTypespec: \_int_typespec: @@ -45273,7 +45273,7 @@ design: (work@bp_be_ptw) |vpiParameter: \_parameter: (work@bp_be_ptw.max_cfgs), line:2192:14, endln:2192:22 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |UINT:128 |vpiTypespec: \_int_typespec: @@ -45286,7 +45286,7 @@ design: (work@bp_be_ptw) |vpiParameter: \_parameter: (work@bp_be_ptw.bp_data_cmd_num_flit_gp), line:911:13, endln:911:36 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |UINT:4 |vpiTypespec: \_int_typespec: @@ -45298,7 +45298,7 @@ design: (work@bp_be_ptw) |vpiParameter: \_parameter: (work@bp_be_ptw.bp_data_resp_num_flit_gp), line:910:13, endln:910:37 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |UINT:4 |vpiTypespec: \_int_typespec: @@ -45310,7 +45310,7 @@ design: (work@bp_be_ptw) |vpiParameter: \_parameter: (work@bp_be_ptw.bp_eaddr_width_gp), line:899:14, endln:899:31 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |UINT:64 |vpiTypespec: \_int_typespec: @@ -45323,7 +45323,7 @@ design: (work@bp_be_ptw) |vpiParameter: \_parameter: (work@bp_be_ptw.bp_instr_width_gp), line:900:14, endln:900:31 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |UINT:32 |vpiTypespec: \_int_typespec: @@ -45336,7 +45336,7 @@ design: (work@bp_be_ptw) |vpiParameter: \_parameter: (work@bp_be_ptw.bp_log_file_gp), line:80:12, endln:80:26 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |UINT:2 |vpiTypespec: \_int_typespec: @@ -45349,7 +45349,7 @@ design: (work@bp_be_ptw) |vpiParameter: \_parameter: (work@bp_be_ptw.bp_log_none_gp), line:78:12, endln:78:26 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |UINT:0 |vpiTypespec: \_int_typespec: @@ -45362,7 +45362,7 @@ design: (work@bp_be_ptw) |vpiParameter: \_parameter: (work@bp_be_ptw.bp_log_stdout_gp), line:79:12, endln:79:28 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |UINT:1 |vpiTypespec: \_int_typespec: @@ -45375,7 +45375,7 @@ design: (work@bp_be_ptw) |vpiParameter: \_parameter: (work@bp_be_ptw.bp_page_offset_width_gp), line:908:13, endln:908:36 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |INT:12 |vpiTypespec: \_int_typespec: @@ -45387,7 +45387,7 @@ design: (work@bp_be_ptw) |vpiParameter: \_parameter: (work@bp_be_ptw.bp_page_size_in_bytes_gp), line:907:13, endln:907:37 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |UINT:4096 |vpiTypespec: \_int_typespec: @@ -45399,7 +45399,7 @@ design: (work@bp_be_ptw) |vpiParameter: \_parameter: (work@bp_be_ptw.bp_sv39_paddr_width_gp), line:905:13, endln:905:35 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |UINT:56 |vpiTypespec: \_int_typespec: @@ -45411,7 +45411,7 @@ design: (work@bp_be_ptw) |vpiParameter: \_parameter: (work@bp_be_ptw.bp_sv39_page_table_depth_gp), line:902:13, endln:902:40 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |UINT:3 |vpiTypespec: \_int_typespec: @@ -45423,7 +45423,7 @@ design: (work@bp_be_ptw) |vpiParameter: \_parameter: (work@bp_be_ptw.bp_sv39_ppn_width_gp), line:906:13, endln:906:33 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |UINT:44 |vpiTypespec: \_int_typespec: @@ -45435,7 +45435,7 @@ design: (work@bp_be_ptw) |vpiParameter: \_parameter: (work@bp_be_ptw.bp_sv39_pte_width_gp), line:903:13, endln:903:33 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |UINT:64 |vpiTypespec: \_int_typespec: @@ -45447,7 +45447,7 @@ design: (work@bp_be_ptw) |vpiParameter: \_parameter: (work@bp_be_ptw.bp_sv39_vaddr_width_gp), line:904:13, endln:904:35 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |UINT:39 |vpiTypespec: \_int_typespec: @@ -45459,7 +45459,7 @@ design: (work@bp_be_ptw) |vpiParameter: \_parameter: (work@bp_be_ptw.cfg_link_dev_base_addr_gp), line:915:14, endln:915:39 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |HEX:01?????? |vpiTypespec: \_int_typespec: @@ -45486,7 +45486,7 @@ design: (work@bp_be_ptw) |vpiParameter: \_parameter: (work@bp_be_ptw.clint_dev_base_addr_gp), line:916:14, endln:916:36 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |HEX:02?????? |vpiTypespec: \_int_typespec: @@ -45513,7 +45513,7 @@ design: (work@bp_be_ptw) |vpiParameter: \_parameter: (work@bp_be_ptw.dram_base_addr_gp), line:913:14, endln:913:31 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |HEX:80000000 |vpiTypespec: \_int_typespec: @@ -45540,7 +45540,7 @@ design: (work@bp_be_ptw) |vpiParameter: \_parameter: (work@bp_be_ptw.host_dev_base_addr_gp), line:917:14, endln:917:35 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |HEX:03?????? |vpiTypespec: \_int_typespec: @@ -45567,7 +45567,7 @@ design: (work@bp_be_ptw) |vpiParameter: \_parameter: (work@bp_be_ptw.mipi_reg_base_addr_gp), line:920:14, endln:920:35 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |HEX:02000??? |vpiTypespec: \_int_typespec: @@ -45594,7 +45594,7 @@ design: (work@bp_be_ptw) |vpiParameter: \_parameter: (work@bp_be_ptw.mtime_reg_addr_gp), line:922:14, endln:922:31 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |HEX:0200bff8 |vpiTypespec: \_int_typespec: @@ -45621,7 +45621,7 @@ design: (work@bp_be_ptw) |vpiParameter: \_parameter: (work@bp_be_ptw.mtimecmp_reg_base_addr_gp), line:921:14, endln:921:39 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |HEX:02004??? |vpiTypespec: \_int_typespec: @@ -45648,7 +45648,7 @@ design: (work@bp_be_ptw) |vpiParameter: \_parameter: (work@bp_be_ptw.plic_dev_base_addr_gp), line:918:14, endln:918:35 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |HEX:0c?????? |vpiTypespec: \_int_typespec: @@ -45675,7 +45675,7 @@ design: (work@bp_be_ptw) |vpiParameter: \_parameter: (work@bp_be_ptw.plic_reg_base_addr_gp), line:923:14, endln:923:35 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |HEX:0c000??? |vpiTypespec: \_int_typespec: @@ -45702,7 +45702,7 @@ design: (work@bp_be_ptw) |vpiParameter: \_parameter: (work@bp_be_ptw.rv64_byte_width_gp), line:1962:14, endln:1962:32 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |UINT:8 |vpiTypespec: \_int_typespec: @@ -45715,7 +45715,7 @@ design: (work@bp_be_ptw) |vpiParameter: \_parameter: (work@bp_be_ptw.rv64_csr_addr_width_gp), line:1973:14, endln:1973:36 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |UINT:12 |vpiTypespec: \_int_typespec: @@ -45728,7 +45728,7 @@ design: (work@bp_be_ptw) |vpiParameter: \_parameter: (work@bp_be_ptw.rv64_dword_width_gp), line:1965:14, endln:1965:33 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |UINT:64 |vpiTypespec: \_int_typespec: @@ -45741,7 +45741,7 @@ design: (work@bp_be_ptw) |vpiParameter: \_parameter: (work@bp_be_ptw.rv64_eaddr_width_gp), line:1961:14, endln:1961:33 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |UINT:64 |vpiTypespec: \_int_typespec: @@ -45754,7 +45754,7 @@ design: (work@bp_be_ptw) |vpiParameter: \_parameter: (work@bp_be_ptw.rv64_funct3_width_gp), line:1971:14, endln:1971:34 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |UINT:3 |vpiTypespec: \_int_typespec: @@ -45767,7 +45767,7 @@ design: (work@bp_be_ptw) |vpiParameter: \_parameter: (work@bp_be_ptw.rv64_funct7_width_gp), line:1972:14, endln:1972:34 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |UINT:7 |vpiTypespec: \_int_typespec: @@ -45780,7 +45780,7 @@ design: (work@bp_be_ptw) |vpiParameter: \_parameter: (work@bp_be_ptw.rv64_hword_width_gp), line:1963:14, endln:1963:33 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |UINT:16 |vpiTypespec: \_int_typespec: @@ -45793,7 +45793,7 @@ design: (work@bp_be_ptw) |vpiParameter: \_parameter: (work@bp_be_ptw.rv64_imm11to5_width_gp), line:1976:14, endln:1976:36 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |UINT:7 |vpiTypespec: \_int_typespec: @@ -45806,7 +45806,7 @@ design: (work@bp_be_ptw) |vpiParameter: \_parameter: (work@bp_be_ptw.rv64_imm12_width_gp), line:1975:14, endln:1975:33 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |UINT:12 |vpiTypespec: \_int_typespec: @@ -45819,7 +45819,7 @@ design: (work@bp_be_ptw) |vpiParameter: \_parameter: (work@bp_be_ptw.rv64_imm20_width_gp), line:1974:14, endln:1974:33 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |UINT:20 |vpiTypespec: \_int_typespec: @@ -45832,7 +45832,7 @@ design: (work@bp_be_ptw) |vpiParameter: \_parameter: (work@bp_be_ptw.rv64_imm4to0_width_gp), line:1977:14, endln:1977:35 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |UINT:5 |vpiTypespec: \_int_typespec: @@ -45845,7 +45845,7 @@ design: (work@bp_be_ptw) |vpiParameter: \_parameter: (work@bp_be_ptw.rv64_instr_width_gp), line:1960:14, endln:1960:33 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |UINT:32 |vpiTypespec: \_int_typespec: @@ -45858,7 +45858,7 @@ design: (work@bp_be_ptw) |vpiParameter: \_parameter: (work@bp_be_ptw.rv64_opcode_width_gp), line:1970:14, endln:1970:34 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |UINT:7 |vpiTypespec: \_int_typespec: @@ -45871,7 +45871,7 @@ design: (work@bp_be_ptw) |vpiParameter: \_parameter: (work@bp_be_ptw.rv64_priv_width_gp), line:1978:14, endln:1978:32 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |UINT:2 |vpiTypespec: \_int_typespec: @@ -45884,7 +45884,7 @@ design: (work@bp_be_ptw) |vpiParameter: \_parameter: (work@bp_be_ptw.rv64_reg_addr_width_gp), line:1967:14, endln:1967:36 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |UINT:5 |vpiTypespec: \_int_typespec: @@ -45897,7 +45897,7 @@ design: (work@bp_be_ptw) |vpiParameter: \_parameter: (work@bp_be_ptw.rv64_reg_data_width_gp), line:1966:14, endln:1966:36 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |UINT:64 |vpiTypespec: \_int_typespec: @@ -45910,7 +45910,7 @@ design: (work@bp_be_ptw) |vpiParameter: \_parameter: (work@bp_be_ptw.rv64_rf_els_gp), line:1959:14, endln:1959:28 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |UINT:32 |vpiTypespec: \_int_typespec: @@ -45923,7 +45923,7 @@ design: (work@bp_be_ptw) |vpiParameter: \_parameter: (work@bp_be_ptw.rv64_shamt_width_gp), line:1968:14, endln:1968:33 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |UINT:6 |vpiTypespec: \_int_typespec: @@ -45936,7 +45936,7 @@ design: (work@bp_be_ptw) |vpiParameter: \_parameter: (work@bp_be_ptw.rv64_shamtw_width_gp), line:1969:14, endln:1969:34 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |UINT:5 |vpiTypespec: \_int_typespec: @@ -45949,7 +45949,7 @@ design: (work@bp_be_ptw) |vpiParameter: \_parameter: (work@bp_be_ptw.rv64_word_width_gp), line:1964:14, endln:1964:32 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |UINT:32 |vpiTypespec: \_int_typespec: @@ -45962,7 +45962,7 @@ design: (work@bp_be_ptw) |vpiParameter: \_parameter: (work@bp_be_ptw.cfg_p), line:4377:24, endln:4377:29 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiTypespec: \_enum_typespec: (bp_common_aviary_pkg::bp_cfg_e), line:2504:3, endln:2513:14 |vpiName:cfg_p @@ -45970,7 +45970,7 @@ design: (work@bp_be_ptw) |vpiParameter: \_parameter: (work@bp_be_ptw.proc_param_lp), line:4379:32, endln:4379:45 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiTypespec: \_struct_typespec: (bp_common_aviary_pkg::bp_proc_param_s), line:2062:9, endln:2062:15 |vpiLocalParam:1 @@ -45979,203 +45979,203 @@ design: (work@bp_be_ptw) |vpiParameter: \_parameter: (work@bp_be_ptw.num_core_p), line:4381:16, endln:4381:26 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiLocalParam:1 |vpiName:num_core_p |vpiFullName:work@bp_be_ptw.num_core_p |vpiParameter: \_parameter: (work@bp_be_ptw.num_cce_p), line:4382:16, endln:4382:25 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiLocalParam:1 |vpiName:num_cce_p |vpiFullName:work@bp_be_ptw.num_cce_p |vpiParameter: \_parameter: (work@bp_be_ptw.num_lce_p), line:4383:16, endln:4383:25 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiLocalParam:1 |vpiName:num_lce_p |vpiFullName:work@bp_be_ptw.num_lce_p |vpiParameter: \_parameter: (work@bp_be_ptw.vaddr_width_p), line:4385:16, endln:4385:29 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiLocalParam:1 |vpiName:vaddr_width_p |vpiFullName:work@bp_be_ptw.vaddr_width_p |vpiParameter: \_parameter: (work@bp_be_ptw.paddr_width_p), line:4386:16, endln:4386:29 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiLocalParam:1 |vpiName:paddr_width_p |vpiFullName:work@bp_be_ptw.paddr_width_p |vpiParameter: \_parameter: (work@bp_be_ptw.asid_width_p), line:4387:16, endln:4387:28 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiLocalParam:1 |vpiName:asid_width_p |vpiFullName:work@bp_be_ptw.asid_width_p |vpiParameter: \_parameter: (work@bp_be_ptw.branch_metadata_fwd_width_p), line:4389:16, endln:4389:43 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiLocalParam:1 |vpiName:branch_metadata_fwd_width_p |vpiFullName:work@bp_be_ptw.branch_metadata_fwd_width_p |vpiParameter: \_parameter: (work@bp_be_ptw.btb_tag_width_p), line:4390:16, endln:4390:31 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiLocalParam:1 |vpiName:btb_tag_width_p |vpiFullName:work@bp_be_ptw.btb_tag_width_p |vpiParameter: \_parameter: (work@bp_be_ptw.btb_idx_width_p), line:4391:16, endln:4391:31 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiLocalParam:1 |vpiName:btb_idx_width_p |vpiFullName:work@bp_be_ptw.btb_idx_width_p |vpiParameter: \_parameter: (work@bp_be_ptw.bht_idx_width_p), line:4392:16, endln:4392:31 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiLocalParam:1 |vpiName:bht_idx_width_p |vpiFullName:work@bp_be_ptw.bht_idx_width_p |vpiParameter: \_parameter: (work@bp_be_ptw.ras_idx_width_p), line:4393:16, endln:4393:31 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiLocalParam:1 |vpiName:ras_idx_width_p |vpiFullName:work@bp_be_ptw.ras_idx_width_p |vpiParameter: \_parameter: (work@bp_be_ptw.itlb_els_p), line:4395:16, endln:4395:26 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiLocalParam:1 |vpiName:itlb_els_p |vpiFullName:work@bp_be_ptw.itlb_els_p |vpiParameter: \_parameter: (work@bp_be_ptw.dtlb_els_p), line:4396:16, endln:4396:26 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiLocalParam:1 |vpiName:dtlb_els_p |vpiFullName:work@bp_be_ptw.dtlb_els_p |vpiParameter: \_parameter: (work@bp_be_ptw.lce_sets_p), line:4398:16, endln:4398:26 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiLocalParam:1 |vpiName:lce_sets_p |vpiFullName:work@bp_be_ptw.lce_sets_p |vpiParameter: \_parameter: (work@bp_be_ptw.lce_assoc_p), line:4399:16, endln:4399:27 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiLocalParam:1 |vpiName:lce_assoc_p |vpiFullName:work@bp_be_ptw.lce_assoc_p |vpiParameter: \_parameter: (work@bp_be_ptw.cce_block_width_p), line:4400:16, endln:4400:33 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiLocalParam:1 |vpiName:cce_block_width_p |vpiFullName:work@bp_be_ptw.cce_block_width_p |vpiParameter: \_parameter: (work@bp_be_ptw.num_cce_instr_ram_els_p), line:4401:16, endln:4401:39 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiLocalParam:1 |vpiName:num_cce_instr_ram_els_p |vpiFullName:work@bp_be_ptw.num_cce_instr_ram_els_p |vpiParameter: \_parameter: (work@bp_be_ptw.fe_queue_fifo_els_p), line:4403:16, endln:4403:35 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiLocalParam:1 |vpiName:fe_queue_fifo_els_p |vpiFullName:work@bp_be_ptw.fe_queue_fifo_els_p |vpiParameter: \_parameter: (work@bp_be_ptw.fe_cmd_fifo_els_p), line:4404:16, endln:4404:33 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiLocalParam:1 |vpiName:fe_cmd_fifo_els_p |vpiFullName:work@bp_be_ptw.fe_cmd_fifo_els_p |vpiParameter: \_parameter: (work@bp_be_ptw.async_coh_clk_p), line:4406:16, endln:4406:31 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiLocalParam:1 |vpiName:async_coh_clk_p |vpiFullName:work@bp_be_ptw.async_coh_clk_p |vpiParameter: \_parameter: (work@bp_be_ptw.coh_noc_flit_width_p), line:4407:16, endln:4407:36 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiLocalParam:1 |vpiName:coh_noc_flit_width_p |vpiFullName:work@bp_be_ptw.coh_noc_flit_width_p |vpiParameter: \_parameter: (work@bp_be_ptw.coh_noc_cid_width_p), line:4408:16, endln:4408:35 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiLocalParam:1 |vpiName:coh_noc_cid_width_p |vpiFullName:work@bp_be_ptw.coh_noc_cid_width_p |vpiParameter: \_parameter: (work@bp_be_ptw.coh_noc_len_width_p), line:4409:16, endln:4409:35 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiLocalParam:1 |vpiName:coh_noc_len_width_p |vpiFullName:work@bp_be_ptw.coh_noc_len_width_p |vpiParameter: \_parameter: (work@bp_be_ptw.coh_noc_y_cord_width_p), line:4410:16, endln:4410:38 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiLocalParam:1 |vpiName:coh_noc_y_cord_width_p |vpiFullName:work@bp_be_ptw.coh_noc_y_cord_width_p |vpiParameter: \_parameter: (work@bp_be_ptw.coh_noc_x_cord_width_p), line:4411:16, endln:4411:38 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiLocalParam:1 |vpiName:coh_noc_x_cord_width_p |vpiFullName:work@bp_be_ptw.coh_noc_x_cord_width_p |vpiParameter: \_parameter: (work@bp_be_ptw.coh_noc_y_dim_p), line:4412:16, endln:4412:31 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiLocalParam:1 |vpiName:coh_noc_y_dim_p |vpiFullName:work@bp_be_ptw.coh_noc_y_dim_p |vpiParameter: \_parameter: (work@bp_be_ptw.coh_noc_x_dim_p), line:4413:16, endln:4413:31 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiLocalParam:1 |vpiName:coh_noc_x_dim_p |vpiFullName:work@bp_be_ptw.coh_noc_x_dim_p |vpiParameter: \_parameter: (work@bp_be_ptw.coh_noc_cord_width_p), line:4414:16, endln:4414:36 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiLocalParam:1 |vpiName:coh_noc_cord_width_p |vpiFullName:work@bp_be_ptw.coh_noc_cord_width_p |vpiParameter: \_parameter: (work@bp_be_ptw.coh_noc_dims_p), line:4415:16, endln:4415:30 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |UINT:2 |vpiTypespec: \_int_typespec: @@ -46185,14 +46185,14 @@ design: (work@bp_be_ptw) |vpiParameter: \_parameter: (work@bp_be_ptw.coh_noc_dirs_p), line:4416:16, endln:4416:30 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiLocalParam:1 |vpiName:coh_noc_dirs_p |vpiFullName:work@bp_be_ptw.coh_noc_dirs_p |vpiParameter: \_parameter: (work@bp_be_ptw.coh_noc_cord_markers_pos_p), line:4417:20, endln:4417:46 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiSize:1 |vpiTypespec: \_array_typespec: @@ -46228,105 +46228,105 @@ design: (work@bp_be_ptw) |vpiParameter: \_parameter: (work@bp_be_ptw.cfg_core_width_p), line:4420:16, endln:4420:32 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiLocalParam:1 |vpiName:cfg_core_width_p |vpiFullName:work@bp_be_ptw.cfg_core_width_p |vpiParameter: \_parameter: (work@bp_be_ptw.cfg_addr_width_p), line:4421:16, endln:4421:32 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiLocalParam:1 |vpiName:cfg_addr_width_p |vpiFullName:work@bp_be_ptw.cfg_addr_width_p |vpiParameter: \_parameter: (work@bp_be_ptw.cfg_data_width_p), line:4422:16, endln:4422:32 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiLocalParam:1 |vpiName:cfg_data_width_p |vpiFullName:work@bp_be_ptw.cfg_data_width_p |vpiParameter: \_parameter: (work@bp_be_ptw.async_mem_clk_p), line:4424:16, endln:4424:31 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiLocalParam:1 |vpiName:async_mem_clk_p |vpiFullName:work@bp_be_ptw.async_mem_clk_p |vpiParameter: \_parameter: (work@bp_be_ptw.mem_noc_max_credits_p), line:4425:16, endln:4425:37 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiLocalParam:1 |vpiName:mem_noc_max_credits_p |vpiFullName:work@bp_be_ptw.mem_noc_max_credits_p |vpiParameter: \_parameter: (work@bp_be_ptw.mem_noc_flit_width_p), line:4426:16, endln:4426:36 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiLocalParam:1 |vpiName:mem_noc_flit_width_p |vpiFullName:work@bp_be_ptw.mem_noc_flit_width_p |vpiParameter: \_parameter: (work@bp_be_ptw.mem_noc_reserved_width_p), line:4427:16, endln:4427:40 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiLocalParam:1 |vpiName:mem_noc_reserved_width_p |vpiFullName:work@bp_be_ptw.mem_noc_reserved_width_p |vpiParameter: \_parameter: (work@bp_be_ptw.mem_noc_cid_width_p), line:4428:16, endln:4428:35 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiLocalParam:1 |vpiName:mem_noc_cid_width_p |vpiFullName:work@bp_be_ptw.mem_noc_cid_width_p |vpiParameter: \_parameter: (work@bp_be_ptw.mem_noc_len_width_p), line:4429:16, endln:4429:35 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiLocalParam:1 |vpiName:mem_noc_len_width_p |vpiFullName:work@bp_be_ptw.mem_noc_len_width_p |vpiParameter: \_parameter: (work@bp_be_ptw.mem_noc_y_cord_width_p), line:4430:16, endln:4430:38 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiLocalParam:1 |vpiName:mem_noc_y_cord_width_p |vpiFullName:work@bp_be_ptw.mem_noc_y_cord_width_p |vpiParameter: \_parameter: (work@bp_be_ptw.mem_noc_x_cord_width_p), line:4431:16, endln:4431:38 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiLocalParam:1 |vpiName:mem_noc_x_cord_width_p |vpiFullName:work@bp_be_ptw.mem_noc_x_cord_width_p |vpiParameter: \_parameter: (work@bp_be_ptw.mem_noc_y_dim_p), line:4432:16, endln:4432:31 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiLocalParam:1 |vpiName:mem_noc_y_dim_p |vpiFullName:work@bp_be_ptw.mem_noc_y_dim_p |vpiParameter: \_parameter: (work@bp_be_ptw.mem_noc_x_dim_p), line:4433:16, endln:4433:31 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiLocalParam:1 |vpiName:mem_noc_x_dim_p |vpiFullName:work@bp_be_ptw.mem_noc_x_dim_p |vpiParameter: \_parameter: (work@bp_be_ptw.mem_noc_cord_width_p), line:4434:16, endln:4434:36 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiLocalParam:1 |vpiName:mem_noc_cord_width_p |vpiFullName:work@bp_be_ptw.mem_noc_cord_width_p |vpiParameter: \_parameter: (work@bp_be_ptw.mem_noc_dims_p), line:4435:16, endln:4435:30 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |UINT:2 |vpiTypespec: \_int_typespec: @@ -46336,14 +46336,14 @@ design: (work@bp_be_ptw) |vpiParameter: \_parameter: (work@bp_be_ptw.mem_noc_dirs_p), line:4436:16, endln:4436:30 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiLocalParam:1 |vpiName:mem_noc_dirs_p |vpiFullName:work@bp_be_ptw.mem_noc_dirs_p |vpiParameter: \_parameter: (work@bp_be_ptw.mem_noc_cord_markers_pos_p), line:4437:20, endln:4437:46 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiSize:1 |vpiTypespec: \_array_typespec: @@ -46379,21 +46379,21 @@ design: (work@bp_be_ptw) |vpiParameter: \_parameter: (work@bp_be_ptw.num_mem_p), line:4440:16, endln:4440:25 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiLocalParam:1 |vpiName:num_mem_p |vpiFullName:work@bp_be_ptw.num_mem_p |vpiParameter: \_parameter: (work@bp_be_ptw.mmio_x_pos_p), line:4441:16, endln:4441:28 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiLocalParam:1 |vpiName:mmio_x_pos_p |vpiFullName:work@bp_be_ptw.mmio_x_pos_p |vpiParameter: \_parameter: (work@bp_be_ptw.dword_width_p), line:4443:16, endln:4443:29 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |UINT:64 |vpiTypespec: \_int_typespec: @@ -46403,7 +46403,7 @@ design: (work@bp_be_ptw) |vpiParameter: \_parameter: (work@bp_be_ptw.instr_width_p), line:4444:16, endln:4444:29 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |UINT:32 |vpiTypespec: \_int_typespec: @@ -46413,7 +46413,7 @@ design: (work@bp_be_ptw) |vpiParameter: \_parameter: (work@bp_be_ptw.reg_addr_width_p), line:4445:16, endln:4445:32 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |UINT:5 |vpiTypespec: \_int_typespec: @@ -46423,7 +46423,7 @@ design: (work@bp_be_ptw) |vpiParameter: \_parameter: (work@bp_be_ptw.page_offset_width_p), line:4446:16, endln:4446:35 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |UINT:12 |vpiTypespec: \_int_typespec: @@ -46433,35 +46433,35 @@ design: (work@bp_be_ptw) |vpiParameter: \_parameter: (work@bp_be_ptw.vtag_width_p), line:4448:16, endln:4448:28 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiLocalParam:1 |vpiName:vtag_width_p |vpiFullName:work@bp_be_ptw.vtag_width_p |vpiParameter: \_parameter: (work@bp_be_ptw.ptag_width_p), line:4449:16, endln:4449:28 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiLocalParam:1 |vpiName:ptag_width_p |vpiFullName:work@bp_be_ptw.ptag_width_p |vpiParameter: \_parameter: (work@bp_be_ptw.fe_queue_width_lp), line:4452:16, endln:4452:33 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiLocalParam:1 |vpiName:fe_queue_width_lp |vpiFullName:work@bp_be_ptw.fe_queue_width_lp |vpiParameter: \_parameter: (work@bp_be_ptw.fe_cmd_width_lp), line:4473:16, endln:4473:31 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiLocalParam:1 |vpiName:fe_cmd_width_lp |vpiFullName:work@bp_be_ptw.fe_cmd_width_lp |vpiParameter: \_parameter: (work@bp_be_ptw.pte_width_p), line:4604:16, endln:4604:27 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |UINT:64 |vpiTypespec: \_int_typespec: @@ -46470,7 +46470,7 @@ design: (work@bp_be_ptw) |vpiParameter: \_parameter: (work@bp_be_ptw.page_table_depth_p), line:4605:16, endln:4605:34 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |UINT:3 |vpiTypespec: \_int_typespec: @@ -46479,14 +46479,14 @@ design: (work@bp_be_ptw) |vpiParameter: \_parameter: (work@bp_be_ptw.vpn_width_lp), line:4607:17, endln:4607:29 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiLocalParam:1 |vpiName:vpn_width_lp |vpiFullName:work@bp_be_ptw.vpn_width_lp |vpiParameter: \_parameter: (work@bp_be_ptw.ppn_width_lp), line:4608:17, endln:4608:29 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiTypespec: \_int_typespec: (ppn_width_lp), line:4625:70, endln:4625:82 |vpiName:ppn_width_lp @@ -46500,49 +46500,49 @@ design: (work@bp_be_ptw) |vpiParameter: \_parameter: (work@bp_be_ptw.dcache_pkt_width_lp), line:4609:17, endln:4609:36 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiLocalParam:1 |vpiName:dcache_pkt_width_lp |vpiFullName:work@bp_be_ptw.dcache_pkt_width_lp |vpiParameter: \_parameter: (work@bp_be_ptw.tlb_entry_width_lp), line:4612:17, endln:4612:35 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiLocalParam:1 |vpiName:tlb_entry_width_lp |vpiFullName:work@bp_be_ptw.tlb_entry_width_lp |vpiParameter: \_parameter: (work@bp_be_ptw.lg_page_table_depth_lp), line:4615:17, endln:4615:39 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiLocalParam:1 |vpiName:lg_page_table_depth_lp |vpiFullName:work@bp_be_ptw.lg_page_table_depth_lp |vpiParameter: \_parameter: (work@bp_be_ptw.pte_size_in_bytes_lp), line:4617:17, endln:4617:37 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiLocalParam:1 |vpiName:pte_size_in_bytes_lp |vpiFullName:work@bp_be_ptw.pte_size_in_bytes_lp |vpiParameter: \_parameter: (work@bp_be_ptw.lg_pte_size_in_bytes_lp), line:4618:17, endln:4618:40 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiLocalParam:1 |vpiName:lg_pte_size_in_bytes_lp |vpiFullName:work@bp_be_ptw.lg_pte_size_in_bytes_lp |vpiParameter: \_parameter: (work@bp_be_ptw.partial_vpn_width_lp), line:4619:17, endln:4619:37 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiLocalParam:1 |vpiName:partial_vpn_width_lp |vpiFullName:work@bp_be_ptw.partial_vpn_width_lp |vpiParamAssign: \_param_assign: , line:78:12, endln:78:32 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_constant: , line:78:31, endln:78:32 |vpiParent: @@ -46571,7 +46571,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:79:12, endln:79:32 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_constant: , line:79:31, endln:79:32 |vpiParent: @@ -46600,7 +46600,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:80:12, endln:80:32 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_constant: , line:80:31, endln:80:32 |vpiParent: @@ -46629,7 +46629,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:899:14, endln:899:36 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_constant: , line:899:34, endln:899:36 |vpiParent: @@ -46658,7 +46658,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:900:14, endln:900:36 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_constant: , line:900:34, endln:900:36 |vpiParent: @@ -46687,7 +46687,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:902:13, endln:902:44 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_constant: , line:902:43, endln:902:44 |vpiParent: @@ -46715,7 +46715,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:903:13, endln:903:38 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_constant: , line:903:36, endln:903:38 |vpiParent: @@ -46743,7 +46743,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:904:13, endln:904:40 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_constant: , line:904:38, endln:904:40 |vpiParent: @@ -46771,7 +46771,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:905:13, endln:905:40 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_constant: , line:905:38, endln:905:40 |vpiParent: @@ -46799,7 +46799,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:906:13, endln:906:38 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_constant: , line:906:36, endln:906:38 |vpiParent: @@ -46827,7 +46827,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:907:13, endln:907:44 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_constant: , line:907:40, endln:907:44 |vpiParent: @@ -46855,7 +46855,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:908:13, endln:908:114 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_constant: , line:908:41, endln:908:72 |vpiParent: @@ -46883,7 +46883,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:910:13, endln:910:41 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_constant: , line:910:40, endln:910:41 |vpiParent: @@ -46911,7 +46911,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:911:13, endln:911:40 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_constant: , line:911:39, endln:911:40 |vpiParent: @@ -46939,7 +46939,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:913:14, endln:913:55 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_constant: , line:913:42, endln:913:55 |vpiParent: @@ -46996,7 +46996,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:915:14, endln:915:55 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_constant: , line:915:42, endln:915:55 |vpiParent: @@ -47053,7 +47053,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:916:14, endln:916:55 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_constant: , line:916:42, endln:916:55 |vpiParent: @@ -47110,7 +47110,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:917:14, endln:917:55 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_constant: , line:917:42, endln:917:55 |vpiParent: @@ -47167,7 +47167,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:918:14, endln:918:55 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_constant: , line:918:42, endln:918:55 |vpiParent: @@ -47224,7 +47224,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:920:14, endln:920:55 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_constant: , line:920:42, endln:920:55 |vpiParent: @@ -47281,7 +47281,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:921:14, endln:921:55 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_constant: , line:921:42, endln:921:55 |vpiParent: @@ -47338,7 +47338,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:922:14, endln:922:55 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_constant: , line:922:42, endln:922:55 |vpiParent: @@ -47395,7 +47395,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:923:14, endln:923:55 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_constant: , line:923:42, endln:923:55 |vpiParent: @@ -47452,7 +47452,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:1959:14, endln:1959:41 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_constant: , line:1959:39, endln:1959:41 |vpiParent: @@ -47481,7 +47481,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:1960:14, endln:1960:41 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_constant: , line:1960:39, endln:1960:41 |vpiParent: @@ -47510,7 +47510,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:1961:14, endln:1961:41 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_constant: , line:1961:39, endln:1961:41 |vpiParent: @@ -47539,7 +47539,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:1962:14, endln:1962:40 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_constant: , line:1962:39, endln:1962:40 |vpiParent: @@ -47568,7 +47568,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:1963:14, endln:1963:41 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_constant: , line:1963:39, endln:1963:41 |vpiParent: @@ -47597,7 +47597,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:1964:14, endln:1964:41 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_constant: , line:1964:39, endln:1964:41 |vpiParent: @@ -47626,7 +47626,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:1965:14, endln:1965:41 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_constant: , line:1965:39, endln:1965:41 |vpiParent: @@ -47655,7 +47655,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:1966:14, endln:1966:41 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_constant: , line:1966:39, endln:1966:41 |vpiParent: @@ -47684,7 +47684,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:1967:14, endln:1967:40 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_constant: , line:1967:39, endln:1967:40 |vpiParent: @@ -47713,7 +47713,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:1968:14, endln:1968:40 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_constant: , line:1968:39, endln:1968:40 |vpiParent: @@ -47742,7 +47742,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:1969:14, endln:1969:40 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_constant: , line:1969:39, endln:1969:40 |vpiParent: @@ -47771,7 +47771,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:1970:14, endln:1970:40 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_constant: , line:1970:39, endln:1970:40 |vpiParent: @@ -47800,7 +47800,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:1971:14, endln:1971:40 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_constant: , line:1971:39, endln:1971:40 |vpiParent: @@ -47829,7 +47829,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:1972:14, endln:1972:40 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_constant: , line:1972:39, endln:1972:40 |vpiParent: @@ -47858,7 +47858,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:1973:14, endln:1973:41 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_constant: , line:1973:39, endln:1973:41 |vpiParent: @@ -47887,7 +47887,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:1974:14, endln:1974:41 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_constant: , line:1974:39, endln:1974:41 |vpiParent: @@ -47916,7 +47916,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:1975:14, endln:1975:41 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_constant: , line:1975:39, endln:1975:41 |vpiParent: @@ -47945,7 +47945,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:1976:14, endln:1976:40 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_constant: , line:1976:39, endln:1976:40 |vpiParent: @@ -47974,7 +47974,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:1977:14, endln:1977:40 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_constant: , line:1977:39, endln:1977:40 |vpiParent: @@ -48003,7 +48003,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:1978:14, endln:1978:40 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_constant: , line:1978:39, endln:1978:40 |vpiParent: @@ -48032,7 +48032,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:2192:14, endln:2192:31 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_constant: , line:2192:28, endln:2192:31 |vpiParent: @@ -48061,7 +48061,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:2193:14, endln:2193:71 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_constant: , line:2193:30, endln:2193:45 |vpiParent: @@ -48090,7 +48090,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:2195:30, endln:2196:22 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_operation: , line:2196:5, endln:2196:22 |vpiParent: @@ -48812,7 +48812,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:2198:30, endln:2247:8 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_operation: , line:2199:5, endln:2247:8 |vpiParent: @@ -50197,7 +50197,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:2249:30, endln:2298:8 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_operation: , line:2250:5, endln:2298:8 |vpiParent: @@ -51582,7 +51582,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:2300:30, endln:2349:8 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_operation: , line:2301:5, endln:2349:8 |vpiParent: @@ -52967,7 +52967,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:2351:30, endln:2400:8 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_operation: , line:2352:5, endln:2400:8 |vpiParent: @@ -54352,7 +54352,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:2402:30, endln:2451:8 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_operation: , line:2403:5, endln:2451:8 |vpiParent: @@ -55737,7 +55737,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:2453:30, endln:2502:8 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_operation: , line:2454:5, endln:2502:8 |vpiParent: @@ -57122,7 +57122,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:2516:44, endln:2525:4 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_operation: , line:2517:3, endln:2525:4 |vpiParent: @@ -57895,7 +57895,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:78:12, endln:78:32 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_constant: , line:78:31, endln:78:32 |vpiParent: @@ -57924,7 +57924,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:79:12, endln:79:32 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_constant: , line:79:31, endln:79:32 |vpiParent: @@ -57953,7 +57953,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:80:12, endln:80:32 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_constant: , line:80:31, endln:80:32 |vpiParent: @@ -57982,7 +57982,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:899:14, endln:899:36 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_constant: , line:899:34, endln:899:36 |vpiParent: @@ -58011,7 +58011,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:900:14, endln:900:36 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_constant: , line:900:34, endln:900:36 |vpiParent: @@ -58040,7 +58040,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:902:13, endln:902:44 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_constant: , line:902:43, endln:902:44 |vpiParent: @@ -58068,7 +58068,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:903:13, endln:903:38 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_constant: , line:903:36, endln:903:38 |vpiParent: @@ -58096,7 +58096,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:904:13, endln:904:40 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_constant: , line:904:38, endln:904:40 |vpiParent: @@ -58124,7 +58124,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:905:13, endln:905:40 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_constant: , line:905:38, endln:905:40 |vpiParent: @@ -58152,7 +58152,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:906:13, endln:906:38 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_constant: , line:906:36, endln:906:38 |vpiParent: @@ -58180,7 +58180,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:907:13, endln:907:44 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_constant: , line:907:40, endln:907:44 |vpiParent: @@ -58208,7 +58208,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:908:13, endln:908:114 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_constant: , line:908:41, endln:908:72 |vpiParent: @@ -58236,7 +58236,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:910:13, endln:910:41 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_constant: , line:910:40, endln:910:41 |vpiParent: @@ -58264,7 +58264,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:911:13, endln:911:40 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_constant: , line:911:39, endln:911:40 |vpiParent: @@ -58292,7 +58292,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:913:14, endln:913:55 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_constant: , line:913:42, endln:913:55 |vpiParent: @@ -58349,7 +58349,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:915:14, endln:915:55 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_constant: , line:915:42, endln:915:55 |vpiParent: @@ -58406,7 +58406,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:916:14, endln:916:55 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_constant: , line:916:42, endln:916:55 |vpiParent: @@ -58463,7 +58463,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:917:14, endln:917:55 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_constant: , line:917:42, endln:917:55 |vpiParent: @@ -58520,7 +58520,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:918:14, endln:918:55 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_constant: , line:918:42, endln:918:55 |vpiParent: @@ -58577,7 +58577,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:920:14, endln:920:55 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_constant: , line:920:42, endln:920:55 |vpiParent: @@ -58634,7 +58634,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:921:14, endln:921:55 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_constant: , line:921:42, endln:921:55 |vpiParent: @@ -58691,7 +58691,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:922:14, endln:922:55 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_constant: , line:922:42, endln:922:55 |vpiParent: @@ -58748,7 +58748,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:923:14, endln:923:55 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_constant: , line:923:42, endln:923:55 |vpiParent: @@ -58805,7 +58805,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:1959:14, endln:1959:41 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_constant: , line:1959:39, endln:1959:41 |vpiParent: @@ -58834,7 +58834,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:1960:14, endln:1960:41 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_constant: , line:1960:39, endln:1960:41 |vpiParent: @@ -58863,7 +58863,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:1961:14, endln:1961:41 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_constant: , line:1961:39, endln:1961:41 |vpiParent: @@ -58892,7 +58892,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:1962:14, endln:1962:40 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_constant: , line:1962:39, endln:1962:40 |vpiParent: @@ -58921,7 +58921,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:1963:14, endln:1963:41 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_constant: , line:1963:39, endln:1963:41 |vpiParent: @@ -58950,7 +58950,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:1964:14, endln:1964:41 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_constant: , line:1964:39, endln:1964:41 |vpiParent: @@ -58979,7 +58979,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:1965:14, endln:1965:41 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_constant: , line:1965:39, endln:1965:41 |vpiParent: @@ -59008,7 +59008,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:1966:14, endln:1966:41 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_constant: , line:1966:39, endln:1966:41 |vpiParent: @@ -59037,7 +59037,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:1967:14, endln:1967:40 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_constant: , line:1967:39, endln:1967:40 |vpiParent: @@ -59066,7 +59066,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:1968:14, endln:1968:40 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_constant: , line:1968:39, endln:1968:40 |vpiParent: @@ -59095,7 +59095,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:1969:14, endln:1969:40 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_constant: , line:1969:39, endln:1969:40 |vpiParent: @@ -59124,7 +59124,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:1970:14, endln:1970:40 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_constant: , line:1970:39, endln:1970:40 |vpiParent: @@ -59153,7 +59153,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:1971:14, endln:1971:40 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_constant: , line:1971:39, endln:1971:40 |vpiParent: @@ -59182,7 +59182,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:1972:14, endln:1972:40 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_constant: , line:1972:39, endln:1972:40 |vpiParent: @@ -59211,7 +59211,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:1973:14, endln:1973:41 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_constant: , line:1973:39, endln:1973:41 |vpiParent: @@ -59240,7 +59240,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:1974:14, endln:1974:41 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_constant: , line:1974:39, endln:1974:41 |vpiParent: @@ -59269,7 +59269,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:1975:14, endln:1975:41 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_constant: , line:1975:39, endln:1975:41 |vpiParent: @@ -59298,7 +59298,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:1976:14, endln:1976:40 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_constant: , line:1976:39, endln:1976:40 |vpiParent: @@ -59327,7 +59327,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:1977:14, endln:1977:40 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_constant: , line:1977:39, endln:1977:40 |vpiParent: @@ -59356,7 +59356,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:1978:14, endln:1978:40 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_constant: , line:1978:39, endln:1978:40 |vpiParent: @@ -59385,7 +59385,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:4377:24, endln:4377:44 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_ref_obj: (e_bp_inv_cfg), line:4377:32, endln:4377:44 |vpiName:e_bp_inv_cfg @@ -59396,7 +59396,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:4379:32, endln:4379:66 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_bit_select: (all_cfgs_gp), line:4379:48, endln:4379:66 |vpiParent: @@ -59414,7 +59414,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:4381:16, endln:4381:51 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_hier_path: (proc_param_lp.num_core), line:4381:29, endln:4381:51 |vpiName:proc_param_lp.num_core @@ -59431,7 +59431,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:4382:16, endln:4382:50 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_hier_path: (proc_param_lp.num_cce), line:4382:29, endln:4382:50 |vpiName:proc_param_lp.num_cce @@ -59448,7 +59448,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:4383:16, endln:4383:50 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_hier_path: (proc_param_lp.num_lce), line:4383:29, endln:4383:50 |vpiName:proc_param_lp.num_lce @@ -59465,7 +59465,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:4385:16, endln:4385:57 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_hier_path: (proc_param_lp.vaddr_width), line:4385:32, endln:4385:57 |vpiName:proc_param_lp.vaddr_width @@ -59482,7 +59482,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:4386:16, endln:4386:57 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_hier_path: (proc_param_lp.paddr_width), line:4386:32, endln:4386:57 |vpiName:proc_param_lp.paddr_width @@ -59499,7 +59499,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:4387:16, endln:4387:56 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_hier_path: (proc_param_lp.asid_width), line:4387:32, endln:4387:56 |vpiName:proc_param_lp.asid_width @@ -59516,7 +59516,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:4389:16, endln:4389:85 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_hier_path: (proc_param_lp.branch_metadata_fwd_width), line:4389:46, endln:4389:85 |vpiName:proc_param_lp.branch_metadata_fwd_width @@ -59533,7 +59533,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:4390:16, endln:4390:73 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_hier_path: (proc_param_lp.btb_tag_width), line:4390:46, endln:4390:73 |vpiName:proc_param_lp.btb_tag_width @@ -59550,7 +59550,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:4391:16, endln:4391:73 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_hier_path: (proc_param_lp.btb_idx_width), line:4391:46, endln:4391:73 |vpiName:proc_param_lp.btb_idx_width @@ -59567,7 +59567,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:4392:16, endln:4392:73 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_hier_path: (proc_param_lp.bht_idx_width), line:4392:46, endln:4392:73 |vpiName:proc_param_lp.bht_idx_width @@ -59584,7 +59584,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:4393:16, endln:4393:73 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_hier_path: (proc_param_lp.ras_idx_width), line:4393:46, endln:4393:73 |vpiName:proc_param_lp.ras_idx_width @@ -59601,7 +59601,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:4395:16, endln:4395:64 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_hier_path: (proc_param_lp.itlb_els), line:4395:42, endln:4395:64 |vpiName:proc_param_lp.itlb_els @@ -59618,7 +59618,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:4396:16, endln:4396:64 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_hier_path: (proc_param_lp.dtlb_els), line:4396:42, endln:4396:64 |vpiName:proc_param_lp.dtlb_els @@ -59635,7 +59635,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:4398:16, endln:4398:64 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_hier_path: (proc_param_lp.lce_sets), line:4398:42, endln:4398:64 |vpiName:proc_param_lp.lce_sets @@ -59652,7 +59652,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:4399:16, endln:4399:65 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_hier_path: (proc_param_lp.lce_assoc), line:4399:42, endln:4399:65 |vpiName:proc_param_lp.lce_assoc @@ -59669,7 +59669,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:4400:16, endln:4400:71 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_hier_path: (proc_param_lp.cce_block_width), line:4400:42, endln:4400:71 |vpiName:proc_param_lp.cce_block_width @@ -59686,7 +59686,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:4401:16, endln:4401:77 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_hier_path: (proc_param_lp.num_cce_instr_ram_els), line:4401:42, endln:4401:77 |vpiName:proc_param_lp.num_cce_instr_ram_els @@ -59703,7 +59703,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:4403:16, endln:4403:69 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_hier_path: (proc_param_lp.fe_queue_fifo_els), line:4403:38, endln:4403:69 |vpiName:proc_param_lp.fe_queue_fifo_els @@ -59720,7 +59720,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:4404:16, endln:4404:67 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_hier_path: (proc_param_lp.fe_cmd_fifo_els), line:4404:38, endln:4404:67 |vpiName:proc_param_lp.fe_cmd_fifo_els @@ -59737,7 +59737,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:4406:16, endln:4406:68 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_hier_path: (proc_param_lp.async_coh_clk), line:4406:41, endln:4406:68 |vpiName:proc_param_lp.async_coh_clk @@ -59754,7 +59754,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:4407:16, endln:4407:73 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_hier_path: (proc_param_lp.coh_noc_flit_width), line:4407:41, endln:4407:73 |vpiName:proc_param_lp.coh_noc_flit_width @@ -59771,7 +59771,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:4408:16, endln:4408:72 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_hier_path: (proc_param_lp.coh_noc_cid_width), line:4408:41, endln:4408:72 |vpiName:proc_param_lp.coh_noc_cid_width @@ -59788,7 +59788,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:4409:16, endln:4409:72 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_hier_path: (proc_param_lp.coh_noc_len_width), line:4409:41, endln:4409:72 |vpiName:proc_param_lp.coh_noc_len_width @@ -59805,7 +59805,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:4410:16, endln:4410:75 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_hier_path: (proc_param_lp.coh_noc_y_cord_width), line:4410:41, endln:4410:75 |vpiName:proc_param_lp.coh_noc_y_cord_width @@ -59822,7 +59822,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:4411:16, endln:4411:75 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_hier_path: (proc_param_lp.coh_noc_x_cord_width), line:4411:41, endln:4411:75 |vpiName:proc_param_lp.coh_noc_x_cord_width @@ -59839,7 +59839,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:4412:16, endln:4412:68 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_hier_path: (proc_param_lp.coh_noc_y_dim), line:4412:41, endln:4412:68 |vpiName:proc_param_lp.coh_noc_y_dim @@ -59856,7 +59856,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:4413:16, endln:4413:68 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_hier_path: (proc_param_lp.coh_noc_x_dim), line:4413:41, endln:4413:68 |vpiName:proc_param_lp.coh_noc_x_dim @@ -59873,7 +59873,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:4414:16, endln:4414:88 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_operation: , line:4414:41, endln:4414:88 |vpiOpType:24 @@ -59892,7 +59892,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:4415:16, endln:4415:42 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_constant: , line:4415:41, endln:4415:42 |vpiDecompile:2 @@ -59906,7 +59906,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:4416:16, endln:4416:61 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_operation: , line:4416:41, endln:4416:61 |vpiOpType:24 @@ -59941,7 +59941,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:4417:20, endln:4418:57 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_operation: , line:4418:7, endln:4418:57 |vpiOpType:75 @@ -59966,7 +59966,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:4420:16, endln:4420:63 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_hier_path: (proc_param_lp.cfg_core_width), line:4420:35, endln:4420:63 |vpiName:proc_param_lp.cfg_core_width @@ -59983,7 +59983,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:4421:16, endln:4421:63 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_hier_path: (proc_param_lp.cfg_addr_width), line:4421:35, endln:4421:63 |vpiName:proc_param_lp.cfg_addr_width @@ -60000,7 +60000,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:4422:16, endln:4422:63 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_hier_path: (proc_param_lp.cfg_data_width), line:4422:35, endln:4422:63 |vpiName:proc_param_lp.cfg_data_width @@ -60017,7 +60017,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:4424:16, endln:4424:71 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_hier_path: (proc_param_lp.async_mem_clk), line:4424:44, endln:4424:71 |vpiName:proc_param_lp.async_mem_clk @@ -60034,7 +60034,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:4425:16, endln:4425:77 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_hier_path: (proc_param_lp.mem_noc_max_credits), line:4425:44, endln:4425:77 |vpiName:proc_param_lp.mem_noc_max_credits @@ -60051,7 +60051,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:4426:16, endln:4426:76 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_hier_path: (proc_param_lp.mem_noc_flit_width), line:4426:44, endln:4426:76 |vpiName:proc_param_lp.mem_noc_flit_width @@ -60068,7 +60068,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:4427:16, endln:4427:80 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_hier_path: (proc_param_lp.mem_noc_reserved_width), line:4427:44, endln:4427:80 |vpiName:proc_param_lp.mem_noc_reserved_width @@ -60085,7 +60085,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:4428:16, endln:4428:75 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_hier_path: (proc_param_lp.mem_noc_cid_width), line:4428:44, endln:4428:75 |vpiName:proc_param_lp.mem_noc_cid_width @@ -60102,7 +60102,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:4429:16, endln:4429:75 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_hier_path: (proc_param_lp.mem_noc_len_width), line:4429:44, endln:4429:75 |vpiName:proc_param_lp.mem_noc_len_width @@ -60119,7 +60119,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:4430:16, endln:4430:78 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_hier_path: (proc_param_lp.mem_noc_y_cord_width), line:4430:44, endln:4430:78 |vpiName:proc_param_lp.mem_noc_y_cord_width @@ -60136,7 +60136,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:4431:16, endln:4431:78 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_hier_path: (proc_param_lp.mem_noc_x_cord_width), line:4431:44, endln:4431:78 |vpiName:proc_param_lp.mem_noc_x_cord_width @@ -60153,7 +60153,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:4432:16, endln:4432:71 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_hier_path: (proc_param_lp.mem_noc_y_dim), line:4432:44, endln:4432:71 |vpiName:proc_param_lp.mem_noc_y_dim @@ -60170,7 +60170,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:4433:16, endln:4433:71 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_hier_path: (proc_param_lp.mem_noc_x_dim), line:4433:44, endln:4433:71 |vpiName:proc_param_lp.mem_noc_x_dim @@ -60187,7 +60187,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:4434:16, endln:4434:91 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_operation: , line:4434:44, endln:4434:91 |vpiOpType:24 @@ -60206,7 +60206,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:4435:16, endln:4435:45 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_constant: , line:4435:44, endln:4435:45 |vpiDecompile:2 @@ -60220,7 +60220,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:4436:16, endln:4436:64 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_operation: , line:4436:44, endln:4436:64 |vpiOpType:24 @@ -60255,7 +60255,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:4437:20, endln:4438:57 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_operation: , line:4438:7, endln:4438:57 |vpiOpType:75 @@ -60280,7 +60280,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:4440:16, endln:4440:50 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_operation: , line:4440:31, endln:4440:50 |vpiOpType:24 @@ -60302,7 +60302,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:4441:16, endln:4441:52 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_operation: , line:4441:31, endln:4441:52 |vpiOpType:12 @@ -60337,7 +60337,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:4443:16, endln:4443:40 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_constant: , line:4443:38, endln:4443:40 |vpiDecompile:64 @@ -60351,7 +60351,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:4444:16, endln:4444:40 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_constant: , line:4444:38, endln:4444:40 |vpiDecompile:32 @@ -60365,7 +60365,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:4445:16, endln:4445:39 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_constant: , line:4445:38, endln:4445:39 |vpiDecompile:5 @@ -60379,7 +60379,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:4446:16, endln:4446:40 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_constant: , line:4446:38, endln:4446:40 |vpiDecompile:12 @@ -60393,7 +60393,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:4448:16, endln:4448:79 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_operation: , line:4448:32, endln:4448:79 |vpiOpType:11 @@ -60420,7 +60420,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:4449:16, endln:4449:79 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_operation: , line:4449:32, endln:4449:79 |vpiOpType:11 @@ -60447,7 +60447,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:4452:16, endln:4471:5 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_operation: , line:4453:4, endln:4469:5 |vpiOpType:24 @@ -60587,7 +60587,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:4473:16, endln:4600:5 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_operation: , line:4474:4, endln:4598:5 |vpiOpType:24 @@ -61229,7 +61229,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:4604:16, endln:4604:63 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_constant: , line:4604:43, endln:4604:63 |vpiDecompile:64 @@ -61243,7 +61243,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:4605:16, endln:4605:70 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_constant: , line:4605:43, endln:4605:70 |vpiDecompile:3 @@ -61257,7 +61257,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:4607:17, endln:4607:78 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_operation: , line:4607:43, endln:4607:78 |vpiOpType:11 @@ -61276,7 +61276,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:4608:17, endln:4608:78 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_operation: , line:4608:43, endln:4608:78 |vpiOpType:11 @@ -61295,7 +61295,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:4609:17, endln:4610:65 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_operation: , line:4610:4, endln:4610:64 |vpiOpType:24 @@ -61327,7 +61327,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:4612:17, endln:4613:48 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_operation: , line:4613:4, endln:4613:47 |vpiOpType:24 @@ -61366,7 +61366,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:4615:17, endln:4615:106 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_operation: , line:4615:45, endln:4615:105 |vpiOpType:32 @@ -61411,7 +61411,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:4617:17, endln:4617:73 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_operation: , line:4617:43, endln:4617:73 |vpiOpType:12 @@ -61437,7 +61437,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:4618:17, endln:4618:110 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_operation: , line:4618:45, endln:4618:109 |vpiOpType:32 @@ -61482,7 +61482,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:4619:17, endln:4619:88 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_operation: , line:4619:43, endln:4619:88 |vpiOpType:11 @@ -61706,7 +61706,7 @@ design: (work@bp_be_ptw) |vpiContAssign: \_cont_assign: , line:4625:10, endln:4625:90 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_operation: , line:4625:35, endln:4625:90 |vpiParent: @@ -61757,12 +61757,12 @@ design: (work@bp_be_ptw) \_ref_obj: (ptag) |vpiName:ptag |uhdmtopModules: -\_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 +\_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiName:work@bp_be_ptw |vpiParameter: \_parameter: (work@bp_be_ptw.bp_data_cmd_num_flit_gp), line:911:13, endln:911:36 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |UINT:4 |vpiTypespec: \_int_typespec: @@ -61774,7 +61774,7 @@ design: (work@bp_be_ptw) |vpiParameter: \_parameter: (work@bp_be_ptw.bp_data_resp_num_flit_gp), line:910:13, endln:910:37 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |UINT:4 |vpiTypespec: \_int_typespec: @@ -61786,7 +61786,7 @@ design: (work@bp_be_ptw) |vpiParameter: \_parameter: (work@bp_be_ptw.bp_eaddr_width_gp), line:899:14, endln:899:31 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |UINT:64 |vpiTypespec: \_int_typespec: @@ -61799,7 +61799,7 @@ design: (work@bp_be_ptw) |vpiParameter: \_parameter: (work@bp_be_ptw.bp_instr_width_gp), line:900:14, endln:900:31 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |UINT:32 |vpiTypespec: \_int_typespec: @@ -61812,7 +61812,7 @@ design: (work@bp_be_ptw) |vpiParameter: \_parameter: (work@bp_be_ptw.bp_log_file_gp), line:80:12, endln:80:26 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |UINT:2 |vpiTypespec: \_int_typespec: @@ -61825,7 +61825,7 @@ design: (work@bp_be_ptw) |vpiParameter: \_parameter: (work@bp_be_ptw.bp_log_none_gp), line:78:12, endln:78:26 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |UINT:0 |vpiTypespec: \_int_typespec: @@ -61838,7 +61838,7 @@ design: (work@bp_be_ptw) |vpiParameter: \_parameter: (work@bp_be_ptw.bp_log_stdout_gp), line:79:12, endln:79:28 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |UINT:1 |vpiTypespec: \_int_typespec: @@ -61851,7 +61851,7 @@ design: (work@bp_be_ptw) |vpiParameter: \_parameter: (work@bp_be_ptw.bp_page_offset_width_gp), line:908:13, endln:908:36 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |INT:12 |vpiTypespec: \_int_typespec: @@ -61863,7 +61863,7 @@ design: (work@bp_be_ptw) |vpiParameter: \_parameter: (work@bp_be_ptw.bp_page_size_in_bytes_gp), line:907:13, endln:907:37 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |UINT:4096 |vpiTypespec: \_int_typespec: @@ -61875,7 +61875,7 @@ design: (work@bp_be_ptw) |vpiParameter: \_parameter: (work@bp_be_ptw.bp_sv39_paddr_width_gp), line:905:13, endln:905:35 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |UINT:56 |vpiTypespec: \_int_typespec: @@ -61887,7 +61887,7 @@ design: (work@bp_be_ptw) |vpiParameter: \_parameter: (work@bp_be_ptw.bp_sv39_page_table_depth_gp), line:902:13, endln:902:40 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |UINT:3 |vpiTypespec: \_int_typespec: @@ -61899,7 +61899,7 @@ design: (work@bp_be_ptw) |vpiParameter: \_parameter: (work@bp_be_ptw.bp_sv39_ppn_width_gp), line:906:13, endln:906:33 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |UINT:44 |vpiTypespec: \_int_typespec: @@ -61911,7 +61911,7 @@ design: (work@bp_be_ptw) |vpiParameter: \_parameter: (work@bp_be_ptw.bp_sv39_pte_width_gp), line:903:13, endln:903:33 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |UINT:64 |vpiTypespec: \_int_typespec: @@ -61923,7 +61923,7 @@ design: (work@bp_be_ptw) |vpiParameter: \_parameter: (work@bp_be_ptw.bp_sv39_vaddr_width_gp), line:904:13, endln:904:35 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |UINT:39 |vpiTypespec: \_int_typespec: @@ -61935,7 +61935,7 @@ design: (work@bp_be_ptw) |vpiParameter: \_parameter: (work@bp_be_ptw.cfg_link_dev_base_addr_gp), line:915:14, endln:915:39 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |HEX:01?????? |vpiTypespec: \_int_typespec: @@ -61962,7 +61962,7 @@ design: (work@bp_be_ptw) |vpiParameter: \_parameter: (work@bp_be_ptw.clint_dev_base_addr_gp), line:916:14, endln:916:36 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |HEX:02?????? |vpiTypespec: \_int_typespec: @@ -61989,7 +61989,7 @@ design: (work@bp_be_ptw) |vpiParameter: \_parameter: (work@bp_be_ptw.dram_base_addr_gp), line:913:14, endln:913:31 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |HEX:80000000 |vpiTypespec: \_int_typespec: @@ -62016,7 +62016,7 @@ design: (work@bp_be_ptw) |vpiParameter: \_parameter: (work@bp_be_ptw.host_dev_base_addr_gp), line:917:14, endln:917:35 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |HEX:03?????? |vpiTypespec: \_int_typespec: @@ -62043,7 +62043,7 @@ design: (work@bp_be_ptw) |vpiParameter: \_parameter: (work@bp_be_ptw.mipi_reg_base_addr_gp), line:920:14, endln:920:35 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |HEX:02000??? |vpiTypespec: \_int_typespec: @@ -62070,7 +62070,7 @@ design: (work@bp_be_ptw) |vpiParameter: \_parameter: (work@bp_be_ptw.mtime_reg_addr_gp), line:922:14, endln:922:31 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |HEX:0200bff8 |vpiTypespec: \_int_typespec: @@ -62097,7 +62097,7 @@ design: (work@bp_be_ptw) |vpiParameter: \_parameter: (work@bp_be_ptw.mtimecmp_reg_base_addr_gp), line:921:14, endln:921:39 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |HEX:02004??? |vpiTypespec: \_int_typespec: @@ -62124,7 +62124,7 @@ design: (work@bp_be_ptw) |vpiParameter: \_parameter: (work@bp_be_ptw.plic_dev_base_addr_gp), line:918:14, endln:918:35 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |HEX:0c?????? |vpiTypespec: \_int_typespec: @@ -62151,7 +62151,7 @@ design: (work@bp_be_ptw) |vpiParameter: \_parameter: (work@bp_be_ptw.plic_reg_base_addr_gp), line:923:14, endln:923:35 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |HEX:0c000??? |vpiTypespec: \_int_typespec: @@ -62178,7 +62178,7 @@ design: (work@bp_be_ptw) |vpiParameter: \_parameter: (work@bp_be_ptw.rv64_byte_width_gp), line:1962:14, endln:1962:32 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |UINT:8 |vpiTypespec: \_int_typespec: @@ -62191,7 +62191,7 @@ design: (work@bp_be_ptw) |vpiParameter: \_parameter: (work@bp_be_ptw.rv64_csr_addr_width_gp), line:1973:14, endln:1973:36 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |UINT:12 |vpiTypespec: \_int_typespec: @@ -62204,7 +62204,7 @@ design: (work@bp_be_ptw) |vpiParameter: \_parameter: (work@bp_be_ptw.rv64_dword_width_gp), line:1965:14, endln:1965:33 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |UINT:64 |vpiTypespec: \_int_typespec: @@ -62217,7 +62217,7 @@ design: (work@bp_be_ptw) |vpiParameter: \_parameter: (work@bp_be_ptw.rv64_eaddr_width_gp), line:1961:14, endln:1961:33 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |UINT:64 |vpiTypespec: \_int_typespec: @@ -62230,7 +62230,7 @@ design: (work@bp_be_ptw) |vpiParameter: \_parameter: (work@bp_be_ptw.rv64_funct3_width_gp), line:1971:14, endln:1971:34 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |UINT:3 |vpiTypespec: \_int_typespec: @@ -62243,7 +62243,7 @@ design: (work@bp_be_ptw) |vpiParameter: \_parameter: (work@bp_be_ptw.rv64_funct7_width_gp), line:1972:14, endln:1972:34 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |UINT:7 |vpiTypespec: \_int_typespec: @@ -62256,7 +62256,7 @@ design: (work@bp_be_ptw) |vpiParameter: \_parameter: (work@bp_be_ptw.rv64_hword_width_gp), line:1963:14, endln:1963:33 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |UINT:16 |vpiTypespec: \_int_typespec: @@ -62269,7 +62269,7 @@ design: (work@bp_be_ptw) |vpiParameter: \_parameter: (work@bp_be_ptw.rv64_imm11to5_width_gp), line:1976:14, endln:1976:36 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |UINT:7 |vpiTypespec: \_int_typespec: @@ -62282,7 +62282,7 @@ design: (work@bp_be_ptw) |vpiParameter: \_parameter: (work@bp_be_ptw.rv64_imm12_width_gp), line:1975:14, endln:1975:33 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |UINT:12 |vpiTypespec: \_int_typespec: @@ -62295,7 +62295,7 @@ design: (work@bp_be_ptw) |vpiParameter: \_parameter: (work@bp_be_ptw.rv64_imm20_width_gp), line:1974:14, endln:1974:33 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |UINT:20 |vpiTypespec: \_int_typespec: @@ -62308,7 +62308,7 @@ design: (work@bp_be_ptw) |vpiParameter: \_parameter: (work@bp_be_ptw.rv64_imm4to0_width_gp), line:1977:14, endln:1977:35 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |UINT:5 |vpiTypespec: \_int_typespec: @@ -62321,7 +62321,7 @@ design: (work@bp_be_ptw) |vpiParameter: \_parameter: (work@bp_be_ptw.rv64_instr_width_gp), line:1960:14, endln:1960:33 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |UINT:32 |vpiTypespec: \_int_typespec: @@ -62334,7 +62334,7 @@ design: (work@bp_be_ptw) |vpiParameter: \_parameter: (work@bp_be_ptw.rv64_opcode_width_gp), line:1970:14, endln:1970:34 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |UINT:7 |vpiTypespec: \_int_typespec: @@ -62347,7 +62347,7 @@ design: (work@bp_be_ptw) |vpiParameter: \_parameter: (work@bp_be_ptw.rv64_priv_width_gp), line:1978:14, endln:1978:32 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |UINT:2 |vpiTypespec: \_int_typespec: @@ -62360,7 +62360,7 @@ design: (work@bp_be_ptw) |vpiParameter: \_parameter: (work@bp_be_ptw.rv64_reg_addr_width_gp), line:1967:14, endln:1967:36 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |UINT:5 |vpiTypespec: \_int_typespec: @@ -62373,7 +62373,7 @@ design: (work@bp_be_ptw) |vpiParameter: \_parameter: (work@bp_be_ptw.rv64_reg_data_width_gp), line:1966:14, endln:1966:36 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |UINT:64 |vpiTypespec: \_int_typespec: @@ -62386,7 +62386,7 @@ design: (work@bp_be_ptw) |vpiParameter: \_parameter: (work@bp_be_ptw.rv64_rf_els_gp), line:1959:14, endln:1959:28 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |UINT:32 |vpiTypespec: \_int_typespec: @@ -62399,7 +62399,7 @@ design: (work@bp_be_ptw) |vpiParameter: \_parameter: (work@bp_be_ptw.rv64_shamt_width_gp), line:1968:14, endln:1968:33 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |UINT:6 |vpiTypespec: \_int_typespec: @@ -62412,7 +62412,7 @@ design: (work@bp_be_ptw) |vpiParameter: \_parameter: (work@bp_be_ptw.rv64_shamtw_width_gp), line:1969:14, endln:1969:34 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |UINT:5 |vpiTypespec: \_int_typespec: @@ -62425,7 +62425,7 @@ design: (work@bp_be_ptw) |vpiParameter: \_parameter: (work@bp_be_ptw.rv64_word_width_gp), line:1964:14, endln:1964:32 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |UINT:32 |vpiTypespec: \_int_typespec: @@ -62438,7 +62438,7 @@ design: (work@bp_be_ptw) |vpiParameter: \_parameter: (work@bp_be_ptw.all_cfgs_gp), line:2516:44, endln:2516:55 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiTypespec: \_packed_array_typespec: , line:2516:13, endln:2516:28 |vpiParent: @@ -63159,7 +63159,7 @@ design: (work@bp_be_ptw) |vpiParameter: \_parameter: (work@bp_be_ptw.bp_dual_core_cfg_p), line:2300:30, endln:2300:48 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiTypespec: \_struct_typespec: (bp_common_aviary_pkg::bp_proc_param_s), line:2062:9, endln:2062:15 |vpiParent: @@ -63855,7 +63855,7 @@ design: (work@bp_be_ptw) |vpiParameter: \_parameter: (work@bp_be_ptw.bp_half_core_cfg_p), line:2198:30, endln:2198:48 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiTypespec: \_struct_typespec: (bp_common_aviary_pkg::bp_proc_param_s), line:2062:9, endln:2062:15 |vpiParent: @@ -64551,7 +64551,7 @@ design: (work@bp_be_ptw) |vpiParameter: \_parameter: (work@bp_be_ptw.bp_inv_cfg_p), line:2195:30, endln:2195:42 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiTypespec: \_struct_typespec: (bp_common_aviary_pkg::bp_proc_param_s), line:2062:9, endln:2062:15 |vpiParent: @@ -65247,7 +65247,7 @@ design: (work@bp_be_ptw) |vpiParameter: \_parameter: (work@bp_be_ptw.bp_oct_core_cfg_p), line:2402:30, endln:2402:47 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiTypespec: \_struct_typespec: (bp_common_aviary_pkg::bp_proc_param_s), line:2062:9, endln:2062:15 |vpiParent: @@ -65943,7 +65943,7 @@ design: (work@bp_be_ptw) |vpiParameter: \_parameter: (work@bp_be_ptw.bp_quad_core_cfg_p), line:2351:30, endln:2351:48 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiTypespec: \_struct_typespec: (bp_common_aviary_pkg::bp_proc_param_s), line:2062:9, endln:2062:15 |vpiParent: @@ -66639,7 +66639,7 @@ design: (work@bp_be_ptw) |vpiParameter: \_parameter: (work@bp_be_ptw.bp_sexta_core_cfg_p), line:2453:30, endln:2453:49 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiTypespec: \_struct_typespec: (bp_common_aviary_pkg::bp_proc_param_s), line:2062:9, endln:2062:15 |vpiParent: @@ -67335,7 +67335,7 @@ design: (work@bp_be_ptw) |vpiParameter: \_parameter: (work@bp_be_ptw.bp_single_core_cfg_p), line:2249:30, endln:2249:50 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiTypespec: \_struct_typespec: (bp_common_aviary_pkg::bp_proc_param_s), line:2062:9, endln:2062:15 |vpiParent: @@ -68031,7 +68031,7 @@ design: (work@bp_be_ptw) |vpiParameter: \_parameter: (work@bp_be_ptw.lg_max_cfgs), line:2193:14, endln:2193:25 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |INT:7 |vpiTypespec: \_int_typespec: @@ -68044,7 +68044,7 @@ design: (work@bp_be_ptw) |vpiParameter: \_parameter: (work@bp_be_ptw.max_cfgs), line:2192:14, endln:2192:22 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |UINT:128 |vpiTypespec: \_int_typespec: @@ -68057,7 +68057,7 @@ design: (work@bp_be_ptw) |vpiParameter: \_parameter: (work@bp_be_ptw.bp_data_cmd_num_flit_gp), line:911:13, endln:911:36 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |UINT:4 |vpiTypespec: \_int_typespec: @@ -68069,7 +68069,7 @@ design: (work@bp_be_ptw) |vpiParameter: \_parameter: (work@bp_be_ptw.bp_data_resp_num_flit_gp), line:910:13, endln:910:37 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |UINT:4 |vpiTypespec: \_int_typespec: @@ -68081,7 +68081,7 @@ design: (work@bp_be_ptw) |vpiParameter: \_parameter: (work@bp_be_ptw.bp_eaddr_width_gp), line:899:14, endln:899:31 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |UINT:64 |vpiTypespec: \_int_typespec: @@ -68094,7 +68094,7 @@ design: (work@bp_be_ptw) |vpiParameter: \_parameter: (work@bp_be_ptw.bp_instr_width_gp), line:900:14, endln:900:31 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |UINT:32 |vpiTypespec: \_int_typespec: @@ -68107,7 +68107,7 @@ design: (work@bp_be_ptw) |vpiParameter: \_parameter: (work@bp_be_ptw.bp_log_file_gp), line:80:12, endln:80:26 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |UINT:2 |vpiTypespec: \_int_typespec: @@ -68120,7 +68120,7 @@ design: (work@bp_be_ptw) |vpiParameter: \_parameter: (work@bp_be_ptw.bp_log_none_gp), line:78:12, endln:78:26 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |UINT:0 |vpiTypespec: \_int_typespec: @@ -68133,7 +68133,7 @@ design: (work@bp_be_ptw) |vpiParameter: \_parameter: (work@bp_be_ptw.bp_log_stdout_gp), line:79:12, endln:79:28 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |UINT:1 |vpiTypespec: \_int_typespec: @@ -68146,7 +68146,7 @@ design: (work@bp_be_ptw) |vpiParameter: \_parameter: (work@bp_be_ptw.bp_page_offset_width_gp), line:908:13, endln:908:36 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |INT:12 |vpiTypespec: \_int_typespec: @@ -68158,7 +68158,7 @@ design: (work@bp_be_ptw) |vpiParameter: \_parameter: (work@bp_be_ptw.bp_page_size_in_bytes_gp), line:907:13, endln:907:37 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |UINT:4096 |vpiTypespec: \_int_typespec: @@ -68170,7 +68170,7 @@ design: (work@bp_be_ptw) |vpiParameter: \_parameter: (work@bp_be_ptw.bp_sv39_paddr_width_gp), line:905:13, endln:905:35 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |UINT:56 |vpiTypespec: \_int_typespec: @@ -68182,7 +68182,7 @@ design: (work@bp_be_ptw) |vpiParameter: \_parameter: (work@bp_be_ptw.bp_sv39_page_table_depth_gp), line:902:13, endln:902:40 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |UINT:3 |vpiTypespec: \_int_typespec: @@ -68194,7 +68194,7 @@ design: (work@bp_be_ptw) |vpiParameter: \_parameter: (work@bp_be_ptw.bp_sv39_ppn_width_gp), line:906:13, endln:906:33 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |UINT:44 |vpiTypespec: \_int_typespec: @@ -68206,7 +68206,7 @@ design: (work@bp_be_ptw) |vpiParameter: \_parameter: (work@bp_be_ptw.bp_sv39_pte_width_gp), line:903:13, endln:903:33 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |UINT:64 |vpiTypespec: \_int_typespec: @@ -68218,7 +68218,7 @@ design: (work@bp_be_ptw) |vpiParameter: \_parameter: (work@bp_be_ptw.bp_sv39_vaddr_width_gp), line:904:13, endln:904:35 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |UINT:39 |vpiTypespec: \_int_typespec: @@ -68230,7 +68230,7 @@ design: (work@bp_be_ptw) |vpiParameter: \_parameter: (work@bp_be_ptw.cfg_link_dev_base_addr_gp), line:915:14, endln:915:39 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |HEX:01?????? |vpiTypespec: \_int_typespec: @@ -68257,7 +68257,7 @@ design: (work@bp_be_ptw) |vpiParameter: \_parameter: (work@bp_be_ptw.clint_dev_base_addr_gp), line:916:14, endln:916:36 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |HEX:02?????? |vpiTypespec: \_int_typespec: @@ -68284,7 +68284,7 @@ design: (work@bp_be_ptw) |vpiParameter: \_parameter: (work@bp_be_ptw.dram_base_addr_gp), line:913:14, endln:913:31 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |HEX:80000000 |vpiTypespec: \_int_typespec: @@ -68311,7 +68311,7 @@ design: (work@bp_be_ptw) |vpiParameter: \_parameter: (work@bp_be_ptw.host_dev_base_addr_gp), line:917:14, endln:917:35 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |HEX:03?????? |vpiTypespec: \_int_typespec: @@ -68338,7 +68338,7 @@ design: (work@bp_be_ptw) |vpiParameter: \_parameter: (work@bp_be_ptw.mipi_reg_base_addr_gp), line:920:14, endln:920:35 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |HEX:02000??? |vpiTypespec: \_int_typespec: @@ -68365,7 +68365,7 @@ design: (work@bp_be_ptw) |vpiParameter: \_parameter: (work@bp_be_ptw.mtime_reg_addr_gp), line:922:14, endln:922:31 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |HEX:0200bff8 |vpiTypespec: \_int_typespec: @@ -68392,7 +68392,7 @@ design: (work@bp_be_ptw) |vpiParameter: \_parameter: (work@bp_be_ptw.mtimecmp_reg_base_addr_gp), line:921:14, endln:921:39 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |HEX:02004??? |vpiTypespec: \_int_typespec: @@ -68419,7 +68419,7 @@ design: (work@bp_be_ptw) |vpiParameter: \_parameter: (work@bp_be_ptw.plic_dev_base_addr_gp), line:918:14, endln:918:35 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |HEX:0c?????? |vpiTypespec: \_int_typespec: @@ -68446,7 +68446,7 @@ design: (work@bp_be_ptw) |vpiParameter: \_parameter: (work@bp_be_ptw.plic_reg_base_addr_gp), line:923:14, endln:923:35 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |HEX:0c000??? |vpiTypespec: \_int_typespec: @@ -68473,7 +68473,7 @@ design: (work@bp_be_ptw) |vpiParameter: \_parameter: (work@bp_be_ptw.rv64_byte_width_gp), line:1962:14, endln:1962:32 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |UINT:8 |vpiTypespec: \_int_typespec: @@ -68486,7 +68486,7 @@ design: (work@bp_be_ptw) |vpiParameter: \_parameter: (work@bp_be_ptw.rv64_csr_addr_width_gp), line:1973:14, endln:1973:36 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |UINT:12 |vpiTypespec: \_int_typespec: @@ -68499,7 +68499,7 @@ design: (work@bp_be_ptw) |vpiParameter: \_parameter: (work@bp_be_ptw.rv64_dword_width_gp), line:1965:14, endln:1965:33 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |UINT:64 |vpiTypespec: \_int_typespec: @@ -68512,7 +68512,7 @@ design: (work@bp_be_ptw) |vpiParameter: \_parameter: (work@bp_be_ptw.rv64_eaddr_width_gp), line:1961:14, endln:1961:33 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |UINT:64 |vpiTypespec: \_int_typespec: @@ -68525,7 +68525,7 @@ design: (work@bp_be_ptw) |vpiParameter: \_parameter: (work@bp_be_ptw.rv64_funct3_width_gp), line:1971:14, endln:1971:34 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |UINT:3 |vpiTypespec: \_int_typespec: @@ -68538,7 +68538,7 @@ design: (work@bp_be_ptw) |vpiParameter: \_parameter: (work@bp_be_ptw.rv64_funct7_width_gp), line:1972:14, endln:1972:34 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |UINT:7 |vpiTypespec: \_int_typespec: @@ -68551,7 +68551,7 @@ design: (work@bp_be_ptw) |vpiParameter: \_parameter: (work@bp_be_ptw.rv64_hword_width_gp), line:1963:14, endln:1963:33 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |UINT:16 |vpiTypespec: \_int_typespec: @@ -68564,7 +68564,7 @@ design: (work@bp_be_ptw) |vpiParameter: \_parameter: (work@bp_be_ptw.rv64_imm11to5_width_gp), line:1976:14, endln:1976:36 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |UINT:7 |vpiTypespec: \_int_typespec: @@ -68577,7 +68577,7 @@ design: (work@bp_be_ptw) |vpiParameter: \_parameter: (work@bp_be_ptw.rv64_imm12_width_gp), line:1975:14, endln:1975:33 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |UINT:12 |vpiTypespec: \_int_typespec: @@ -68590,7 +68590,7 @@ design: (work@bp_be_ptw) |vpiParameter: \_parameter: (work@bp_be_ptw.rv64_imm20_width_gp), line:1974:14, endln:1974:33 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |UINT:20 |vpiTypespec: \_int_typespec: @@ -68603,7 +68603,7 @@ design: (work@bp_be_ptw) |vpiParameter: \_parameter: (work@bp_be_ptw.rv64_imm4to0_width_gp), line:1977:14, endln:1977:35 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |UINT:5 |vpiTypespec: \_int_typespec: @@ -68616,7 +68616,7 @@ design: (work@bp_be_ptw) |vpiParameter: \_parameter: (work@bp_be_ptw.rv64_instr_width_gp), line:1960:14, endln:1960:33 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |UINT:32 |vpiTypespec: \_int_typespec: @@ -68629,7 +68629,7 @@ design: (work@bp_be_ptw) |vpiParameter: \_parameter: (work@bp_be_ptw.rv64_opcode_width_gp), line:1970:14, endln:1970:34 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |UINT:7 |vpiTypespec: \_int_typespec: @@ -68642,7 +68642,7 @@ design: (work@bp_be_ptw) |vpiParameter: \_parameter: (work@bp_be_ptw.rv64_priv_width_gp), line:1978:14, endln:1978:32 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |UINT:2 |vpiTypespec: \_int_typespec: @@ -68655,7 +68655,7 @@ design: (work@bp_be_ptw) |vpiParameter: \_parameter: (work@bp_be_ptw.rv64_reg_addr_width_gp), line:1967:14, endln:1967:36 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |UINT:5 |vpiTypespec: \_int_typespec: @@ -68668,7 +68668,7 @@ design: (work@bp_be_ptw) |vpiParameter: \_parameter: (work@bp_be_ptw.rv64_reg_data_width_gp), line:1966:14, endln:1966:36 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |UINT:64 |vpiTypespec: \_int_typespec: @@ -68681,7 +68681,7 @@ design: (work@bp_be_ptw) |vpiParameter: \_parameter: (work@bp_be_ptw.rv64_rf_els_gp), line:1959:14, endln:1959:28 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |UINT:32 |vpiTypespec: \_int_typespec: @@ -68694,7 +68694,7 @@ design: (work@bp_be_ptw) |vpiParameter: \_parameter: (work@bp_be_ptw.rv64_shamt_width_gp), line:1968:14, endln:1968:33 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |UINT:6 |vpiTypespec: \_int_typespec: @@ -68707,7 +68707,7 @@ design: (work@bp_be_ptw) |vpiParameter: \_parameter: (work@bp_be_ptw.rv64_shamtw_width_gp), line:1969:14, endln:1969:34 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |UINT:5 |vpiTypespec: \_int_typespec: @@ -68720,7 +68720,7 @@ design: (work@bp_be_ptw) |vpiParameter: \_parameter: (work@bp_be_ptw.rv64_word_width_gp), line:1964:14, endln:1964:32 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |UINT:32 |vpiTypespec: \_int_typespec: @@ -68733,7 +68733,7 @@ design: (work@bp_be_ptw) |vpiParameter: \_parameter: (work@bp_be_ptw.cfg_p), line:4377:24, endln:4377:29 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiTypespec: \_enum_typespec: (bp_common_aviary_pkg::bp_cfg_e), line:2504:3, endln:2513:14 |vpiParent: @@ -68829,7 +68829,7 @@ design: (work@bp_be_ptw) |vpiParameter: \_parameter: (work@bp_be_ptw.proc_param_lp), line:4379:32, endln:4379:45 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiTypespec: \_struct_typespec: (bp_common_aviary_pkg::bp_proc_param_s), line:2062:9, endln:2062:15 |vpiParent: @@ -69524,203 +69524,203 @@ design: (work@bp_be_ptw) |vpiParameter: \_parameter: (work@bp_be_ptw.num_core_p), line:4381:16, endln:4381:26 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiLocalParam:1 |vpiName:num_core_p |vpiFullName:work@bp_be_ptw.num_core_p |vpiParameter: \_parameter: (work@bp_be_ptw.num_cce_p), line:4382:16, endln:4382:25 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiLocalParam:1 |vpiName:num_cce_p |vpiFullName:work@bp_be_ptw.num_cce_p |vpiParameter: \_parameter: (work@bp_be_ptw.num_lce_p), line:4383:16, endln:4383:25 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiLocalParam:1 |vpiName:num_lce_p |vpiFullName:work@bp_be_ptw.num_lce_p |vpiParameter: \_parameter: (work@bp_be_ptw.vaddr_width_p), line:4385:16, endln:4385:29 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiLocalParam:1 |vpiName:vaddr_width_p |vpiFullName:work@bp_be_ptw.vaddr_width_p |vpiParameter: \_parameter: (work@bp_be_ptw.paddr_width_p), line:4386:16, endln:4386:29 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiLocalParam:1 |vpiName:paddr_width_p |vpiFullName:work@bp_be_ptw.paddr_width_p |vpiParameter: \_parameter: (work@bp_be_ptw.asid_width_p), line:4387:16, endln:4387:28 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiLocalParam:1 |vpiName:asid_width_p |vpiFullName:work@bp_be_ptw.asid_width_p |vpiParameter: \_parameter: (work@bp_be_ptw.branch_metadata_fwd_width_p), line:4389:16, endln:4389:43 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiLocalParam:1 |vpiName:branch_metadata_fwd_width_p |vpiFullName:work@bp_be_ptw.branch_metadata_fwd_width_p |vpiParameter: \_parameter: (work@bp_be_ptw.btb_tag_width_p), line:4390:16, endln:4390:31 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiLocalParam:1 |vpiName:btb_tag_width_p |vpiFullName:work@bp_be_ptw.btb_tag_width_p |vpiParameter: \_parameter: (work@bp_be_ptw.btb_idx_width_p), line:4391:16, endln:4391:31 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiLocalParam:1 |vpiName:btb_idx_width_p |vpiFullName:work@bp_be_ptw.btb_idx_width_p |vpiParameter: \_parameter: (work@bp_be_ptw.bht_idx_width_p), line:4392:16, endln:4392:31 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiLocalParam:1 |vpiName:bht_idx_width_p |vpiFullName:work@bp_be_ptw.bht_idx_width_p |vpiParameter: \_parameter: (work@bp_be_ptw.ras_idx_width_p), line:4393:16, endln:4393:31 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiLocalParam:1 |vpiName:ras_idx_width_p |vpiFullName:work@bp_be_ptw.ras_idx_width_p |vpiParameter: \_parameter: (work@bp_be_ptw.itlb_els_p), line:4395:16, endln:4395:26 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiLocalParam:1 |vpiName:itlb_els_p |vpiFullName:work@bp_be_ptw.itlb_els_p |vpiParameter: \_parameter: (work@bp_be_ptw.dtlb_els_p), line:4396:16, endln:4396:26 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiLocalParam:1 |vpiName:dtlb_els_p |vpiFullName:work@bp_be_ptw.dtlb_els_p |vpiParameter: \_parameter: (work@bp_be_ptw.lce_sets_p), line:4398:16, endln:4398:26 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiLocalParam:1 |vpiName:lce_sets_p |vpiFullName:work@bp_be_ptw.lce_sets_p |vpiParameter: \_parameter: (work@bp_be_ptw.lce_assoc_p), line:4399:16, endln:4399:27 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiLocalParam:1 |vpiName:lce_assoc_p |vpiFullName:work@bp_be_ptw.lce_assoc_p |vpiParameter: \_parameter: (work@bp_be_ptw.cce_block_width_p), line:4400:16, endln:4400:33 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiLocalParam:1 |vpiName:cce_block_width_p |vpiFullName:work@bp_be_ptw.cce_block_width_p |vpiParameter: \_parameter: (work@bp_be_ptw.num_cce_instr_ram_els_p), line:4401:16, endln:4401:39 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiLocalParam:1 |vpiName:num_cce_instr_ram_els_p |vpiFullName:work@bp_be_ptw.num_cce_instr_ram_els_p |vpiParameter: \_parameter: (work@bp_be_ptw.fe_queue_fifo_els_p), line:4403:16, endln:4403:35 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiLocalParam:1 |vpiName:fe_queue_fifo_els_p |vpiFullName:work@bp_be_ptw.fe_queue_fifo_els_p |vpiParameter: \_parameter: (work@bp_be_ptw.fe_cmd_fifo_els_p), line:4404:16, endln:4404:33 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiLocalParam:1 |vpiName:fe_cmd_fifo_els_p |vpiFullName:work@bp_be_ptw.fe_cmd_fifo_els_p |vpiParameter: \_parameter: (work@bp_be_ptw.async_coh_clk_p), line:4406:16, endln:4406:31 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiLocalParam:1 |vpiName:async_coh_clk_p |vpiFullName:work@bp_be_ptw.async_coh_clk_p |vpiParameter: \_parameter: (work@bp_be_ptw.coh_noc_flit_width_p), line:4407:16, endln:4407:36 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiLocalParam:1 |vpiName:coh_noc_flit_width_p |vpiFullName:work@bp_be_ptw.coh_noc_flit_width_p |vpiParameter: \_parameter: (work@bp_be_ptw.coh_noc_cid_width_p), line:4408:16, endln:4408:35 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiLocalParam:1 |vpiName:coh_noc_cid_width_p |vpiFullName:work@bp_be_ptw.coh_noc_cid_width_p |vpiParameter: \_parameter: (work@bp_be_ptw.coh_noc_len_width_p), line:4409:16, endln:4409:35 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiLocalParam:1 |vpiName:coh_noc_len_width_p |vpiFullName:work@bp_be_ptw.coh_noc_len_width_p |vpiParameter: \_parameter: (work@bp_be_ptw.coh_noc_y_cord_width_p), line:4410:16, endln:4410:38 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiLocalParam:1 |vpiName:coh_noc_y_cord_width_p |vpiFullName:work@bp_be_ptw.coh_noc_y_cord_width_p |vpiParameter: \_parameter: (work@bp_be_ptw.coh_noc_x_cord_width_p), line:4411:16, endln:4411:38 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiLocalParam:1 |vpiName:coh_noc_x_cord_width_p |vpiFullName:work@bp_be_ptw.coh_noc_x_cord_width_p |vpiParameter: \_parameter: (work@bp_be_ptw.coh_noc_y_dim_p), line:4412:16, endln:4412:31 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiLocalParam:1 |vpiName:coh_noc_y_dim_p |vpiFullName:work@bp_be_ptw.coh_noc_y_dim_p |vpiParameter: \_parameter: (work@bp_be_ptw.coh_noc_x_dim_p), line:4413:16, endln:4413:31 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiLocalParam:1 |vpiName:coh_noc_x_dim_p |vpiFullName:work@bp_be_ptw.coh_noc_x_dim_p |vpiParameter: \_parameter: (work@bp_be_ptw.coh_noc_cord_width_p), line:4414:16, endln:4414:36 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiLocalParam:1 |vpiName:coh_noc_cord_width_p |vpiFullName:work@bp_be_ptw.coh_noc_cord_width_p |vpiParameter: \_parameter: (work@bp_be_ptw.coh_noc_dims_p), line:4415:16, endln:4415:30 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |UINT:2 |vpiTypespec: \_int_typespec: @@ -69732,14 +69732,14 @@ design: (work@bp_be_ptw) |vpiParameter: \_parameter: (work@bp_be_ptw.coh_noc_dirs_p), line:4416:16, endln:4416:30 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiLocalParam:1 |vpiName:coh_noc_dirs_p |vpiFullName:work@bp_be_ptw.coh_noc_dirs_p |vpiParameter: \_parameter: (work@bp_be_ptw.coh_noc_cord_markers_pos_p), line:4417:20, endln:4417:46 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiSize:1 |vpiTypespec: \_array_typespec: @@ -69797,105 +69797,105 @@ design: (work@bp_be_ptw) |vpiParameter: \_parameter: (work@bp_be_ptw.cfg_core_width_p), line:4420:16, endln:4420:32 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiLocalParam:1 |vpiName:cfg_core_width_p |vpiFullName:work@bp_be_ptw.cfg_core_width_p |vpiParameter: \_parameter: (work@bp_be_ptw.cfg_addr_width_p), line:4421:16, endln:4421:32 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiLocalParam:1 |vpiName:cfg_addr_width_p |vpiFullName:work@bp_be_ptw.cfg_addr_width_p |vpiParameter: \_parameter: (work@bp_be_ptw.cfg_data_width_p), line:4422:16, endln:4422:32 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiLocalParam:1 |vpiName:cfg_data_width_p |vpiFullName:work@bp_be_ptw.cfg_data_width_p |vpiParameter: \_parameter: (work@bp_be_ptw.async_mem_clk_p), line:4424:16, endln:4424:31 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiLocalParam:1 |vpiName:async_mem_clk_p |vpiFullName:work@bp_be_ptw.async_mem_clk_p |vpiParameter: \_parameter: (work@bp_be_ptw.mem_noc_max_credits_p), line:4425:16, endln:4425:37 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiLocalParam:1 |vpiName:mem_noc_max_credits_p |vpiFullName:work@bp_be_ptw.mem_noc_max_credits_p |vpiParameter: \_parameter: (work@bp_be_ptw.mem_noc_flit_width_p), line:4426:16, endln:4426:36 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiLocalParam:1 |vpiName:mem_noc_flit_width_p |vpiFullName:work@bp_be_ptw.mem_noc_flit_width_p |vpiParameter: \_parameter: (work@bp_be_ptw.mem_noc_reserved_width_p), line:4427:16, endln:4427:40 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiLocalParam:1 |vpiName:mem_noc_reserved_width_p |vpiFullName:work@bp_be_ptw.mem_noc_reserved_width_p |vpiParameter: \_parameter: (work@bp_be_ptw.mem_noc_cid_width_p), line:4428:16, endln:4428:35 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiLocalParam:1 |vpiName:mem_noc_cid_width_p |vpiFullName:work@bp_be_ptw.mem_noc_cid_width_p |vpiParameter: \_parameter: (work@bp_be_ptw.mem_noc_len_width_p), line:4429:16, endln:4429:35 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiLocalParam:1 |vpiName:mem_noc_len_width_p |vpiFullName:work@bp_be_ptw.mem_noc_len_width_p |vpiParameter: \_parameter: (work@bp_be_ptw.mem_noc_y_cord_width_p), line:4430:16, endln:4430:38 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiLocalParam:1 |vpiName:mem_noc_y_cord_width_p |vpiFullName:work@bp_be_ptw.mem_noc_y_cord_width_p |vpiParameter: \_parameter: (work@bp_be_ptw.mem_noc_x_cord_width_p), line:4431:16, endln:4431:38 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiLocalParam:1 |vpiName:mem_noc_x_cord_width_p |vpiFullName:work@bp_be_ptw.mem_noc_x_cord_width_p |vpiParameter: \_parameter: (work@bp_be_ptw.mem_noc_y_dim_p), line:4432:16, endln:4432:31 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiLocalParam:1 |vpiName:mem_noc_y_dim_p |vpiFullName:work@bp_be_ptw.mem_noc_y_dim_p |vpiParameter: \_parameter: (work@bp_be_ptw.mem_noc_x_dim_p), line:4433:16, endln:4433:31 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiLocalParam:1 |vpiName:mem_noc_x_dim_p |vpiFullName:work@bp_be_ptw.mem_noc_x_dim_p |vpiParameter: \_parameter: (work@bp_be_ptw.mem_noc_cord_width_p), line:4434:16, endln:4434:36 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiLocalParam:1 |vpiName:mem_noc_cord_width_p |vpiFullName:work@bp_be_ptw.mem_noc_cord_width_p |vpiParameter: \_parameter: (work@bp_be_ptw.mem_noc_dims_p), line:4435:16, endln:4435:30 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |UINT:2 |vpiTypespec: \_int_typespec: @@ -69907,14 +69907,14 @@ design: (work@bp_be_ptw) |vpiParameter: \_parameter: (work@bp_be_ptw.mem_noc_dirs_p), line:4436:16, endln:4436:30 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiLocalParam:1 |vpiName:mem_noc_dirs_p |vpiFullName:work@bp_be_ptw.mem_noc_dirs_p |vpiParameter: \_parameter: (work@bp_be_ptw.mem_noc_cord_markers_pos_p), line:4437:20, endln:4437:46 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiSize:1 |vpiTypespec: \_array_typespec: @@ -69972,21 +69972,21 @@ design: (work@bp_be_ptw) |vpiParameter: \_parameter: (work@bp_be_ptw.num_mem_p), line:4440:16, endln:4440:25 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiLocalParam:1 |vpiName:num_mem_p |vpiFullName:work@bp_be_ptw.num_mem_p |vpiParameter: \_parameter: (work@bp_be_ptw.mmio_x_pos_p), line:4441:16, endln:4441:28 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiLocalParam:1 |vpiName:mmio_x_pos_p |vpiFullName:work@bp_be_ptw.mmio_x_pos_p |vpiParameter: \_parameter: (work@bp_be_ptw.dword_width_p), line:4443:16, endln:4443:29 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |UINT:64 |vpiTypespec: \_int_typespec: @@ -69998,7 +69998,7 @@ design: (work@bp_be_ptw) |vpiParameter: \_parameter: (work@bp_be_ptw.instr_width_p), line:4444:16, endln:4444:29 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |UINT:32 |vpiTypespec: \_int_typespec: @@ -70010,7 +70010,7 @@ design: (work@bp_be_ptw) |vpiParameter: \_parameter: (work@bp_be_ptw.reg_addr_width_p), line:4445:16, endln:4445:32 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |UINT:5 |vpiTypespec: \_int_typespec: @@ -70022,7 +70022,7 @@ design: (work@bp_be_ptw) |vpiParameter: \_parameter: (work@bp_be_ptw.page_offset_width_p), line:4446:16, endln:4446:35 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |UINT:12 |vpiTypespec: \_int_typespec: @@ -70034,35 +70034,35 @@ design: (work@bp_be_ptw) |vpiParameter: \_parameter: (work@bp_be_ptw.vtag_width_p), line:4448:16, endln:4448:28 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiLocalParam:1 |vpiName:vtag_width_p |vpiFullName:work@bp_be_ptw.vtag_width_p |vpiParameter: \_parameter: (work@bp_be_ptw.ptag_width_p), line:4449:16, endln:4449:28 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiLocalParam:1 |vpiName:ptag_width_p |vpiFullName:work@bp_be_ptw.ptag_width_p |vpiParameter: \_parameter: (work@bp_be_ptw.fe_queue_width_lp), line:4452:16, endln:4452:33 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiLocalParam:1 |vpiName:fe_queue_width_lp |vpiFullName:work@bp_be_ptw.fe_queue_width_lp |vpiParameter: \_parameter: (work@bp_be_ptw.fe_cmd_width_lp), line:4473:16, endln:4473:31 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiLocalParam:1 |vpiName:fe_cmd_width_lp |vpiFullName:work@bp_be_ptw.fe_cmd_width_lp |vpiParameter: \_parameter: (work@bp_be_ptw.pte_width_p), line:4604:16, endln:4604:27 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |UINT:64 |vpiTypespec: \_int_typespec: @@ -70073,7 +70073,7 @@ design: (work@bp_be_ptw) |vpiParameter: \_parameter: (work@bp_be_ptw.page_table_depth_p), line:4605:16, endln:4605:34 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |UINT:3 |vpiTypespec: \_int_typespec: @@ -70084,14 +70084,14 @@ design: (work@bp_be_ptw) |vpiParameter: \_parameter: (work@bp_be_ptw.vpn_width_lp), line:4607:17, endln:4607:29 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiLocalParam:1 |vpiName:vpn_width_lp |vpiFullName:work@bp_be_ptw.vpn_width_lp |vpiParameter: \_parameter: (work@bp_be_ptw.ppn_width_lp), line:4608:17, endln:4608:29 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiTypespec: \_int_typespec: (ppn_width_lp), line:4625:70, endln:4625:82 |vpiParent: @@ -70105,49 +70105,49 @@ design: (work@bp_be_ptw) |vpiParameter: \_parameter: (work@bp_be_ptw.dcache_pkt_width_lp), line:4609:17, endln:4609:36 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiLocalParam:1 |vpiName:dcache_pkt_width_lp |vpiFullName:work@bp_be_ptw.dcache_pkt_width_lp |vpiParameter: \_parameter: (work@bp_be_ptw.tlb_entry_width_lp), line:4612:17, endln:4612:35 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiLocalParam:1 |vpiName:tlb_entry_width_lp |vpiFullName:work@bp_be_ptw.tlb_entry_width_lp |vpiParameter: \_parameter: (work@bp_be_ptw.lg_page_table_depth_lp), line:4615:17, endln:4615:39 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiLocalParam:1 |vpiName:lg_page_table_depth_lp |vpiFullName:work@bp_be_ptw.lg_page_table_depth_lp |vpiParameter: \_parameter: (work@bp_be_ptw.pte_size_in_bytes_lp), line:4617:17, endln:4617:37 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiLocalParam:1 |vpiName:pte_size_in_bytes_lp |vpiFullName:work@bp_be_ptw.pte_size_in_bytes_lp |vpiParameter: \_parameter: (work@bp_be_ptw.lg_pte_size_in_bytes_lp), line:4618:17, endln:4618:40 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiLocalParam:1 |vpiName:lg_pte_size_in_bytes_lp |vpiFullName:work@bp_be_ptw.lg_pte_size_in_bytes_lp |vpiParameter: \_parameter: (work@bp_be_ptw.partial_vpn_width_lp), line:4619:17, endln:4619:37 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiLocalParam:1 |vpiName:partial_vpn_width_lp |vpiFullName:work@bp_be_ptw.partial_vpn_width_lp |vpiParamAssign: \_param_assign: , line:4377:24, endln:4377:44 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_constant: , line:4377:32, endln:4377:44 |vpiDecompile:0 @@ -70161,7 +70161,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:4379:32, endln:4379:66 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_bit_select: (all_cfgs_gp), line:4379:48, endln:4379:66 |vpiParent: @@ -70271,7 +70271,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:4381:16, endln:4381:51 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_constant: , line:4381:29, endln:4381:51 |vpiDecompile:inv @@ -70283,7 +70283,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:4382:16, endln:4382:50 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_constant: , line:4382:29, endln:4382:50 |vpiDecompile:inv @@ -70295,7 +70295,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:4383:16, endln:4383:50 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_constant: , line:4383:29, endln:4383:50 |vpiDecompile:inv @@ -70307,7 +70307,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:4385:16, endln:4385:57 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_constant: , line:4385:32, endln:4385:57 |vpiDecompile:inv @@ -70319,7 +70319,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:4386:16, endln:4386:57 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_constant: , line:4386:32, endln:4386:57 |vpiDecompile:inv @@ -70331,7 +70331,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:4387:16, endln:4387:56 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_constant: , line:4387:32, endln:4387:56 |vpiDecompile:inv @@ -70343,7 +70343,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:4389:16, endln:4389:85 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_constant: , line:4389:46, endln:4389:85 |vpiDecompile:inv @@ -70355,7 +70355,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:4390:16, endln:4390:73 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_constant: , line:4390:46, endln:4390:73 |vpiDecompile:inv @@ -70367,7 +70367,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:4391:16, endln:4391:73 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_constant: , line:4391:46, endln:4391:73 |vpiDecompile:inv @@ -70379,7 +70379,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:4392:16, endln:4392:73 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_constant: , line:4392:46, endln:4392:73 |vpiDecompile:inv @@ -70391,7 +70391,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:4393:16, endln:4393:73 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_constant: , line:4393:46, endln:4393:73 |vpiDecompile:inv @@ -70403,7 +70403,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:4395:16, endln:4395:64 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_constant: , line:4395:42, endln:4395:64 |vpiDecompile:inv @@ -70415,7 +70415,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:4396:16, endln:4396:64 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_constant: , line:4396:42, endln:4396:64 |vpiDecompile:inv @@ -70427,7 +70427,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:4398:16, endln:4398:64 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_constant: , line:4398:42, endln:4398:64 |vpiDecompile:inv @@ -70439,7 +70439,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:4399:16, endln:4399:65 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_constant: , line:4399:42, endln:4399:65 |vpiDecompile:inv @@ -70451,7 +70451,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:4400:16, endln:4400:71 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_constant: , line:4400:42, endln:4400:71 |vpiDecompile:inv @@ -70463,7 +70463,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:4401:16, endln:4401:77 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_constant: , line:4401:42, endln:4401:77 |vpiDecompile:inv @@ -70475,7 +70475,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:4403:16, endln:4403:69 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_constant: , line:4403:38, endln:4403:69 |vpiDecompile:inv @@ -70487,7 +70487,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:4404:16, endln:4404:67 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_constant: , line:4404:38, endln:4404:67 |vpiDecompile:inv @@ -70499,7 +70499,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:4406:16, endln:4406:68 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_constant: , line:4406:41, endln:4406:68 |vpiDecompile:inv @@ -70511,7 +70511,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:4407:16, endln:4407:73 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_constant: , line:4407:41, endln:4407:73 |vpiDecompile:inv @@ -70523,7 +70523,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:4408:16, endln:4408:72 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_constant: , line:4408:41, endln:4408:72 |vpiDecompile:inv @@ -70535,7 +70535,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:4409:16, endln:4409:72 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_constant: , line:4409:41, endln:4409:72 |vpiDecompile:inv @@ -70547,7 +70547,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:4410:16, endln:4410:75 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_constant: , line:4410:41, endln:4410:75 |vpiDecompile:inv @@ -70559,7 +70559,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:4411:16, endln:4411:75 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_constant: , line:4411:41, endln:4411:75 |vpiDecompile:inv @@ -70571,7 +70571,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:4412:16, endln:4412:68 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_constant: , line:4412:41, endln:4412:68 |vpiDecompile:inv @@ -70583,7 +70583,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:4413:16, endln:4413:68 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_constant: , line:4413:41, endln:4413:68 |vpiDecompile:inv @@ -70595,7 +70595,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:4414:16, endln:4414:88 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_constant: , line:4414:41, endln:4414:88 |vpiDecompile:13819116 @@ -70607,7 +70607,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:4415:16, endln:4415:42 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_constant: , line:4415:41, endln:4415:42 |vpiDecompile:2 @@ -70621,7 +70621,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:4416:16, endln:4416:61 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_constant: , line:4416:41, endln:4416:61 |vpiDecompile:5 @@ -70633,7 +70633,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:4417:20, endln:4418:57 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_operation: , line:4418:7, endln:4418:57 |vpiParent: @@ -70698,7 +70698,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:4420:16, endln:4420:63 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_constant: , line:4420:35, endln:4420:63 |vpiDecompile:inv @@ -70710,7 +70710,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:4421:16, endln:4421:63 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_constant: , line:4421:35, endln:4421:63 |vpiDecompile:inv @@ -70722,7 +70722,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:4422:16, endln:4422:63 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_constant: , line:4422:35, endln:4422:63 |vpiDecompile:inv @@ -70734,7 +70734,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:4424:16, endln:4424:71 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_constant: , line:4424:44, endln:4424:71 |vpiDecompile:inv @@ -70746,7 +70746,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:4425:16, endln:4425:77 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_constant: , line:4425:44, endln:4425:77 |vpiDecompile:inv @@ -70758,7 +70758,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:4426:16, endln:4426:76 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_constant: , line:4426:44, endln:4426:76 |vpiDecompile:inv @@ -70770,7 +70770,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:4427:16, endln:4427:80 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_constant: , line:4427:44, endln:4427:80 |vpiDecompile:inv @@ -70782,7 +70782,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:4428:16, endln:4428:75 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_constant: , line:4428:44, endln:4428:75 |vpiDecompile:inv @@ -70794,7 +70794,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:4429:16, endln:4429:75 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_constant: , line:4429:44, endln:4429:75 |vpiDecompile:inv @@ -70806,7 +70806,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:4430:16, endln:4430:78 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_constant: , line:4430:44, endln:4430:78 |vpiDecompile:inv @@ -70818,7 +70818,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:4431:16, endln:4431:78 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_constant: , line:4431:44, endln:4431:78 |vpiDecompile:inv @@ -70830,7 +70830,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:4432:16, endln:4432:71 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_constant: , line:4432:44, endln:4432:71 |vpiDecompile:inv @@ -70842,7 +70842,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:4433:16, endln:4433:71 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_constant: , line:4433:44, endln:4433:71 |vpiDecompile:inv @@ -70854,7 +70854,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:4434:16, endln:4434:91 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_constant: , line:4434:44, endln:4434:91 |vpiDecompile:13819116 @@ -70866,7 +70866,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:4435:16, endln:4435:45 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_constant: , line:4435:44, endln:4435:45 |vpiDecompile:2 @@ -70880,7 +70880,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:4436:16, endln:4436:64 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_constant: , line:4436:44, endln:4436:64 |vpiDecompile:5 @@ -70892,7 +70892,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:4437:20, endln:4438:57 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_operation: , line:4438:7, endln:4438:57 |vpiParent: @@ -70957,7 +70957,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:4440:16, endln:4440:50 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_constant: , line:4440:31, endln:4440:50 |vpiDecompile:6909560 @@ -70969,7 +70969,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:4441:16, endln:4441:52 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_constant: , line:4441:31, endln:4441:52 |vpiDecompile:3454779 @@ -70981,7 +70981,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:4443:16, endln:4443:40 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_constant: , line:4443:38, endln:4443:40 |vpiDecompile:64 @@ -70995,7 +70995,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:4444:16, endln:4444:40 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_constant: , line:4444:38, endln:4444:40 |vpiDecompile:32 @@ -71009,7 +71009,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:4445:16, endln:4445:39 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_constant: , line:4445:38, endln:4445:39 |vpiDecompile:5 @@ -71023,7 +71023,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:4446:16, endln:4446:40 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_constant: , line:4446:38, endln:4446:40 |vpiDecompile:12 @@ -71037,7 +71037,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:4448:16, endln:4448:79 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_constant: , line:4448:32, endln:4448:79 |vpiDecompile:6909546 @@ -71049,7 +71049,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:4449:16, endln:4449:79 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_constant: , line:4449:32, endln:4449:79 |vpiDecompile:6909546 @@ -71061,7 +71061,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:4452:16, endln:4471:5 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_constant: , line:4453:3, endln:4471:5 |vpiDecompile:13819150 @@ -71073,7 +71073,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:4473:16, endln:4600:5 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_constant: , line:4474:3, endln:4600:5 |vpiDecompile:13819125 @@ -71085,7 +71085,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:4604:16, endln:4604:63 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_constant: , line:4604:43, endln:4604:63 |vpiDecompile:64 @@ -71099,7 +71099,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:4605:16, endln:4605:70 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_constant: , line:4605:43, endln:4605:70 |vpiDecompile:3 @@ -71113,7 +71113,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:4607:17, endln:4607:78 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_constant: , line:4607:43, endln:4607:78 |vpiDecompile:6909546 @@ -71125,7 +71125,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:4608:17, endln:4608:78 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_constant: , line:4608:43, endln:4608:78 |vpiDecompile:6909546 @@ -71139,7 +71139,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:4609:17, endln:4610:65 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_constant: , line:4610:3, endln:4610:65 |vpiDecompile:80 @@ -71151,7 +71151,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:4612:17, endln:4613:48 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_constant: , line:4613:3, endln:4613:48 |vpiDecompile:6909552 @@ -71163,7 +71163,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:4615:17, endln:4615:106 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_constant: , line:4615:43, endln:4615:106 |vpiDecompile:2 @@ -71175,7 +71175,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:4617:17, endln:4617:73 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_constant: , line:4617:43, endln:4617:73 |vpiDecompile:8 @@ -71187,7 +71187,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:4618:17, endln:4618:110 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_constant: , line:4618:43, endln:4618:110 |vpiDecompile:3 @@ -71199,7 +71199,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:4619:17, endln:4619:88 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_constant: , line:4619:43, endln:4619:88 |vpiDecompile:9 @@ -71211,7 +71211,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:78:12, endln:78:32 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_constant: , line:78:31, endln:78:32 |vpiDecompile:0 @@ -71225,7 +71225,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:79:12, endln:79:32 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_constant: , line:79:31, endln:79:32 |vpiDecompile:1 @@ -71239,7 +71239,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:80:12, endln:80:32 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_constant: , line:80:31, endln:80:32 |vpiDecompile:2 @@ -71253,7 +71253,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:899:14, endln:899:36 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_constant: , line:899:34, endln:899:36 |vpiDecompile:64 @@ -71267,7 +71267,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:900:14, endln:900:36 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_constant: , line:900:34, endln:900:36 |vpiDecompile:32 @@ -71281,7 +71281,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:902:13, endln:902:44 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_constant: , line:902:43, endln:902:44 |vpiDecompile:3 @@ -71295,7 +71295,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:903:13, endln:903:38 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_constant: , line:903:36, endln:903:38 |vpiDecompile:64 @@ -71309,7 +71309,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:904:13, endln:904:40 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_constant: , line:904:38, endln:904:40 |vpiDecompile:39 @@ -71323,7 +71323,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:905:13, endln:905:40 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_constant: , line:905:38, endln:905:40 |vpiDecompile:56 @@ -71337,7 +71337,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:906:13, endln:906:38 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_constant: , line:906:36, endln:906:38 |vpiDecompile:44 @@ -71351,7 +71351,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:907:13, endln:907:44 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_constant: , line:907:40, endln:907:44 |vpiDecompile:4096 @@ -71365,7 +71365,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:908:13, endln:908:114 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_constant: , line:908:39, endln:908:114 |vpiDecompile:12 @@ -71379,7 +71379,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:910:13, endln:910:41 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_constant: , line:910:40, endln:910:41 |vpiDecompile:4 @@ -71393,7 +71393,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:911:13, endln:911:40 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_constant: , line:911:39, endln:911:40 |vpiDecompile:4 @@ -71407,7 +71407,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:913:14, endln:913:55 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_constant: , line:913:42, endln:913:55 |vpiDecompile:32'h80000000 @@ -71421,7 +71421,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:915:14, endln:915:55 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_constant: , line:915:42, endln:915:55 |vpiDecompile:32'h01?????? @@ -71435,7 +71435,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:916:14, endln:916:55 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_constant: , line:916:42, endln:916:55 |vpiDecompile:32'h02?????? @@ -71449,7 +71449,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:917:14, endln:917:55 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_constant: , line:917:42, endln:917:55 |vpiDecompile:32'h03?????? @@ -71463,7 +71463,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:918:14, endln:918:55 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_constant: , line:918:42, endln:918:55 |vpiDecompile:32'h0c?????? @@ -71477,7 +71477,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:920:14, endln:920:55 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_constant: , line:920:42, endln:920:55 |vpiDecompile:32'h02000??? @@ -71491,7 +71491,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:921:14, endln:921:55 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_constant: , line:921:42, endln:921:55 |vpiDecompile:32'h02004??? @@ -71505,7 +71505,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:922:14, endln:922:55 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_constant: , line:922:42, endln:922:55 |vpiDecompile:32'h0200bff8 @@ -71519,7 +71519,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:923:14, endln:923:55 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_constant: , line:923:42, endln:923:55 |vpiDecompile:32'h0c000??? @@ -71533,7 +71533,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:1959:14, endln:1959:41 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_constant: , line:1959:39, endln:1959:41 |vpiDecompile:32 @@ -71547,7 +71547,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:1960:14, endln:1960:41 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_constant: , line:1960:39, endln:1960:41 |vpiDecompile:32 @@ -71561,7 +71561,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:1961:14, endln:1961:41 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_constant: , line:1961:39, endln:1961:41 |vpiDecompile:64 @@ -71575,7 +71575,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:1962:14, endln:1962:40 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_constant: , line:1962:39, endln:1962:40 |vpiDecompile:8 @@ -71589,7 +71589,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:1963:14, endln:1963:41 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_constant: , line:1963:39, endln:1963:41 |vpiDecompile:16 @@ -71603,7 +71603,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:1964:14, endln:1964:41 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_constant: , line:1964:39, endln:1964:41 |vpiDecompile:32 @@ -71617,7 +71617,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:1965:14, endln:1965:41 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_constant: , line:1965:39, endln:1965:41 |vpiDecompile:64 @@ -71631,7 +71631,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:1966:14, endln:1966:41 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_constant: , line:1966:39, endln:1966:41 |vpiDecompile:64 @@ -71645,7 +71645,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:1967:14, endln:1967:40 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_constant: , line:1967:39, endln:1967:40 |vpiDecompile:5 @@ -71659,7 +71659,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:1968:14, endln:1968:40 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_constant: , line:1968:39, endln:1968:40 |vpiDecompile:6 @@ -71673,7 +71673,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:1969:14, endln:1969:40 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_constant: , line:1969:39, endln:1969:40 |vpiDecompile:5 @@ -71687,7 +71687,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:1970:14, endln:1970:40 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_constant: , line:1970:39, endln:1970:40 |vpiDecompile:7 @@ -71701,7 +71701,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:1971:14, endln:1971:40 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_constant: , line:1971:39, endln:1971:40 |vpiDecompile:3 @@ -71715,7 +71715,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:1972:14, endln:1972:40 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_constant: , line:1972:39, endln:1972:40 |vpiDecompile:7 @@ -71729,7 +71729,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:1973:14, endln:1973:41 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_constant: , line:1973:39, endln:1973:41 |vpiDecompile:12 @@ -71743,7 +71743,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:1974:14, endln:1974:41 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_constant: , line:1974:39, endln:1974:41 |vpiDecompile:20 @@ -71757,7 +71757,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:1975:14, endln:1975:41 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_constant: , line:1975:39, endln:1975:41 |vpiDecompile:12 @@ -71771,7 +71771,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:1976:14, endln:1976:40 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_constant: , line:1976:39, endln:1976:40 |vpiDecompile:7 @@ -71785,7 +71785,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:1977:14, endln:1977:40 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_constant: , line:1977:39, endln:1977:40 |vpiDecompile:5 @@ -71799,7 +71799,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:1978:14, endln:1978:40 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_constant: , line:1978:39, endln:1978:40 |vpiDecompile:2 @@ -71813,7 +71813,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:2192:14, endln:2192:31 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_constant: , line:2192:28, endln:2192:31 |vpiDecompile:128 @@ -71827,7 +71827,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:2193:14, endln:2193:71 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_constant: , line:2193:28, endln:2193:71 |vpiDecompile:7 @@ -71841,7 +71841,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:2195:30, endln:2196:22 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_operation: , line:2196:5, endln:2196:22 |vpiParent: @@ -72860,7 +72860,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:2198:30, endln:2247:8 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_operation: , line:2199:5, endln:2247:8 |vpiParent: @@ -73879,7 +73879,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:2249:30, endln:2298:8 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_operation: , line:2250:5, endln:2298:8 |vpiParent: @@ -74898,7 +74898,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:2300:30, endln:2349:8 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_operation: , line:2301:5, endln:2349:8 |vpiParent: @@ -75917,7 +75917,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:2351:30, endln:2400:8 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_operation: , line:2352:5, endln:2400:8 |vpiParent: @@ -76936,7 +76936,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:2402:30, endln:2451:8 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_operation: , line:2403:5, endln:2451:8 |vpiParent: @@ -77955,7 +77955,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:2453:30, endln:2502:8 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_operation: , line:2454:5, endln:2502:8 |vpiParent: @@ -78974,7 +78974,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:2516:44, endln:2525:4 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_operation: , line:2517:3, endln:2525:4 |vpiTypespec: @@ -79747,7 +79747,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:78:12, endln:78:32 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_constant: , line:78:31, endln:78:32 |vpiDecompile:0 @@ -79761,7 +79761,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:79:12, endln:79:32 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_constant: , line:79:31, endln:79:32 |vpiDecompile:1 @@ -79775,7 +79775,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:80:12, endln:80:32 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_constant: , line:80:31, endln:80:32 |vpiDecompile:2 @@ -79789,7 +79789,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:899:14, endln:899:36 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_constant: , line:899:34, endln:899:36 |vpiDecompile:64 @@ -79803,7 +79803,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:900:14, endln:900:36 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_constant: , line:900:34, endln:900:36 |vpiDecompile:32 @@ -79817,7 +79817,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:902:13, endln:902:44 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_constant: , line:902:43, endln:902:44 |vpiDecompile:3 @@ -79831,7 +79831,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:903:13, endln:903:38 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_constant: , line:903:36, endln:903:38 |vpiDecompile:64 @@ -79845,7 +79845,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:904:13, endln:904:40 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_constant: , line:904:38, endln:904:40 |vpiDecompile:39 @@ -79859,7 +79859,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:905:13, endln:905:40 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_constant: , line:905:38, endln:905:40 |vpiDecompile:56 @@ -79873,7 +79873,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:906:13, endln:906:38 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_constant: , line:906:36, endln:906:38 |vpiDecompile:44 @@ -79887,7 +79887,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:907:13, endln:907:44 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_constant: , line:907:40, endln:907:44 |vpiDecompile:4096 @@ -79901,7 +79901,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:908:13, endln:908:114 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_constant: , line:908:39, endln:908:114 |vpiDecompile:12 @@ -79915,7 +79915,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:910:13, endln:910:41 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_constant: , line:910:40, endln:910:41 |vpiDecompile:4 @@ -79929,7 +79929,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:911:13, endln:911:40 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_constant: , line:911:39, endln:911:40 |vpiDecompile:4 @@ -79943,7 +79943,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:913:14, endln:913:55 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_constant: , line:913:42, endln:913:55 |vpiDecompile:32'h80000000 @@ -79957,7 +79957,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:915:14, endln:915:55 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_constant: , line:915:42, endln:915:55 |vpiDecompile:32'h01?????? @@ -79971,7 +79971,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:916:14, endln:916:55 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_constant: , line:916:42, endln:916:55 |vpiDecompile:32'h02?????? @@ -79985,7 +79985,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:917:14, endln:917:55 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_constant: , line:917:42, endln:917:55 |vpiDecompile:32'h03?????? @@ -79999,7 +79999,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:918:14, endln:918:55 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_constant: , line:918:42, endln:918:55 |vpiDecompile:32'h0c?????? @@ -80013,7 +80013,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:920:14, endln:920:55 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_constant: , line:920:42, endln:920:55 |vpiDecompile:32'h02000??? @@ -80027,7 +80027,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:921:14, endln:921:55 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_constant: , line:921:42, endln:921:55 |vpiDecompile:32'h02004??? @@ -80041,7 +80041,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:922:14, endln:922:55 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_constant: , line:922:42, endln:922:55 |vpiDecompile:32'h0200bff8 @@ -80055,7 +80055,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:923:14, endln:923:55 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_constant: , line:923:42, endln:923:55 |vpiDecompile:32'h0c000??? @@ -80069,7 +80069,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:1959:14, endln:1959:41 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_constant: , line:1959:39, endln:1959:41 |vpiDecompile:32 @@ -80083,7 +80083,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:1960:14, endln:1960:41 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_constant: , line:1960:39, endln:1960:41 |vpiDecompile:32 @@ -80097,7 +80097,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:1961:14, endln:1961:41 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_constant: , line:1961:39, endln:1961:41 |vpiDecompile:64 @@ -80111,7 +80111,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:1962:14, endln:1962:40 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_constant: , line:1962:39, endln:1962:40 |vpiDecompile:8 @@ -80125,7 +80125,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:1963:14, endln:1963:41 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_constant: , line:1963:39, endln:1963:41 |vpiDecompile:16 @@ -80139,7 +80139,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:1964:14, endln:1964:41 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_constant: , line:1964:39, endln:1964:41 |vpiDecompile:32 @@ -80153,7 +80153,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:1965:14, endln:1965:41 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_constant: , line:1965:39, endln:1965:41 |vpiDecompile:64 @@ -80167,7 +80167,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:1966:14, endln:1966:41 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_constant: , line:1966:39, endln:1966:41 |vpiDecompile:64 @@ -80181,7 +80181,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:1967:14, endln:1967:40 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_constant: , line:1967:39, endln:1967:40 |vpiDecompile:5 @@ -80195,7 +80195,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:1968:14, endln:1968:40 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_constant: , line:1968:39, endln:1968:40 |vpiDecompile:6 @@ -80209,7 +80209,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:1969:14, endln:1969:40 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_constant: , line:1969:39, endln:1969:40 |vpiDecompile:5 @@ -80223,7 +80223,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:1970:14, endln:1970:40 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_constant: , line:1970:39, endln:1970:40 |vpiDecompile:7 @@ -80237,7 +80237,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:1971:14, endln:1971:40 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_constant: , line:1971:39, endln:1971:40 |vpiDecompile:3 @@ -80251,7 +80251,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:1972:14, endln:1972:40 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_constant: , line:1972:39, endln:1972:40 |vpiDecompile:7 @@ -80265,7 +80265,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:1973:14, endln:1973:41 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_constant: , line:1973:39, endln:1973:41 |vpiDecompile:12 @@ -80279,7 +80279,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:1974:14, endln:1974:41 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_constant: , line:1974:39, endln:1974:41 |vpiDecompile:20 @@ -80293,7 +80293,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:1975:14, endln:1975:41 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_constant: , line:1975:39, endln:1975:41 |vpiDecompile:12 @@ -80307,7 +80307,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:1976:14, endln:1976:40 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_constant: , line:1976:39, endln:1976:40 |vpiDecompile:7 @@ -80321,7 +80321,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:1977:14, endln:1977:40 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_constant: , line:1977:39, endln:1977:40 |vpiDecompile:5 @@ -80335,7 +80335,7 @@ design: (work@bp_be_ptw) |vpiParamAssign: \_param_assign: , line:1978:14, endln:1978:40 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_constant: , line:1978:39, endln:1978:40 |vpiDecompile:2 @@ -80568,7 +80568,7 @@ design: (work@bp_be_ptw) |vpiContAssign: \_cont_assign: , line:4625:10, endln:4625:90 |vpiParent: - \_module: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 + \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiRhs: \_operation: , line:4625:35, endln:4625:90 |vpiParent: diff --git a/tests/BlackParrotSkipParam/BlackParrotSkipParam.log b/tests/BlackParrotSkipParam/BlackParrotSkipParam.log index 924f508f96..f07074c513 100644 --- a/tests/BlackParrotSkipParam/BlackParrotSkipParam.log +++ b/tests/BlackParrotSkipParam/BlackParrotSkipParam.log @@ -395,7 +395,7 @@ int_typespec 11 int_var 4 io_decl 11 logic_var 1 -module 7 +module_inst 7 operation 2 package 2 param_assign 6 @@ -421,7 +421,7 @@ int_typespec 11 int_var 4 io_decl 22 logic_var 1 -module 7 +module_inst 7 operation 2 package 2 param_assign 6 @@ -919,14 +919,14 @@ design: (work@top) \_int_typespec: |vpiSigned:1 |uhdmallModules: -\_module: work@bsg_counter_set_en (work@bsg_counter_set_en), file:${SURELOG_DIR}/tests/BlackParrotSkipParam/dut.sv, line:2:1, endln:7:10 +\_module_inst: work@bsg_counter_set_en (work@bsg_counter_set_en), file:${SURELOG_DIR}/tests/BlackParrotSkipParam/dut.sv, line:2:1, endln:7:10 |vpiParent: \_design: (work@top) |vpiFullName:work@bsg_counter_set_en |vpiParameter: \_parameter: (work@bsg_counter_set_en.max_val_p), line:3:15, endln:3:24 |vpiParent: - \_module: work@bsg_counter_set_en (work@bsg_counter_set_en), file:${SURELOG_DIR}/tests/BlackParrotSkipParam/dut.sv, line:2:1, endln:7:10 + \_module_inst: work@bsg_counter_set_en (work@bsg_counter_set_en), file:${SURELOG_DIR}/tests/BlackParrotSkipParam/dut.sv, line:2:1, endln:7:10 |STRING:inv |vpiTypespec: \_string_typespec: @@ -935,13 +935,13 @@ design: (work@top) |vpiParameter: \_parameter: (work@bsg_counter_set_en.lg_max_val_lp), line:4:17, endln:4:30 |vpiParent: - \_module: work@bsg_counter_set_en (work@bsg_counter_set_en), file:${SURELOG_DIR}/tests/BlackParrotSkipParam/dut.sv, line:2:1, endln:7:10 + \_module_inst: work@bsg_counter_set_en (work@bsg_counter_set_en), file:${SURELOG_DIR}/tests/BlackParrotSkipParam/dut.sv, line:2:1, endln:7:10 |vpiName:lg_max_val_lp |vpiFullName:work@bsg_counter_set_en.lg_max_val_lp |vpiParameter: \_parameter: (work@bsg_counter_set_en.reset_val_p), line:5:17, endln:5:28 |vpiParent: - \_module: work@bsg_counter_set_en (work@bsg_counter_set_en), file:${SURELOG_DIR}/tests/BlackParrotSkipParam/dut.sv, line:2:1, endln:7:10 + \_module_inst: work@bsg_counter_set_en (work@bsg_counter_set_en), file:${SURELOG_DIR}/tests/BlackParrotSkipParam/dut.sv, line:2:1, endln:7:10 |UINT:0 |vpiTypespec: \_int_typespec: @@ -950,7 +950,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:3:15, endln:3:30 |vpiParent: - \_module: work@bsg_counter_set_en (work@bsg_counter_set_en), file:${SURELOG_DIR}/tests/BlackParrotSkipParam/dut.sv, line:2:1, endln:7:10 + \_module_inst: work@bsg_counter_set_en (work@bsg_counter_set_en), file:${SURELOG_DIR}/tests/BlackParrotSkipParam/dut.sv, line:2:1, endln:7:10 |vpiRhs: \_constant: , line:3:25, endln:3:30 |vpiDecompile:inv @@ -964,7 +964,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:4:17, endln:4:52 |vpiParent: - \_module: work@bsg_counter_set_en (work@bsg_counter_set_en), file:${SURELOG_DIR}/tests/BlackParrotSkipParam/dut.sv, line:2:1, endln:7:10 + \_module_inst: work@bsg_counter_set_en (work@bsg_counter_set_en), file:${SURELOG_DIR}/tests/BlackParrotSkipParam/dut.sv, line:2:1, endln:7:10 |vpiRhs: \_sys_func_call: ($clog2), line:4:32, endln:4:51 |vpiArgument: @@ -991,7 +991,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:5:17, endln:5:30 |vpiParent: - \_module: work@bsg_counter_set_en (work@bsg_counter_set_en), file:${SURELOG_DIR}/tests/BlackParrotSkipParam/dut.sv, line:2:1, endln:7:10 + \_module_inst: work@bsg_counter_set_en (work@bsg_counter_set_en), file:${SURELOG_DIR}/tests/BlackParrotSkipParam/dut.sv, line:2:1, endln:7:10 |vpiRhs: \_constant: , line:5:29, endln:5:30 |vpiDecompile:0 @@ -1004,27 +1004,27 @@ design: (work@top) \_parameter: (work@bsg_counter_set_en.reset_val_p), line:5:17, endln:5:28 |vpiDefName:work@bsg_counter_set_en |uhdmallModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/BlackParrotSkipParam/dut.sv, line:9:1, endln:17:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/BlackParrotSkipParam/dut.sv, line:9:1, endln:17:10 |vpiParent: \_design: (work@top) |vpiFullName:work@top |vpiDefName:work@top |uhdmtopModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/BlackParrotSkipParam/dut.sv, line:9:1, endln:17:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/BlackParrotSkipParam/dut.sv, line:9:1, endln:17:10 |vpiName:work@top |vpiDefName:work@top |vpiTop:1 |vpiTopModule:1 - |vpiModule: - \_module: work@bsg_counter_set_en (work@top.mtime_counter), file:${SURELOG_DIR}/tests/BlackParrotSkipParam/dut.sv, line:10:1, endln:14:18 + |vpiModuleInst: + \_module_inst: work@bsg_counter_set_en (work@top.mtime_counter), file:${SURELOG_DIR}/tests/BlackParrotSkipParam/dut.sv, line:10:1, endln:14:18 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/BlackParrotSkipParam/dut.sv, line:9:1, endln:17:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/BlackParrotSkipParam/dut.sv, line:9:1, endln:17:10 |vpiName:mtime_counter |vpiFullName:work@top.mtime_counter |vpiParameter: \_parameter: (work@top.mtime_counter.max_val_p), line:3:15, endln:3:24 |vpiParent: - \_module: work@bsg_counter_set_en (work@top.mtime_counter), file:${SURELOG_DIR}/tests/BlackParrotSkipParam/dut.sv, line:10:1, endln:14:18 + \_module_inst: work@bsg_counter_set_en (work@top.mtime_counter), file:${SURELOG_DIR}/tests/BlackParrotSkipParam/dut.sv, line:10:1, endln:14:18 |STRING:inv |vpiTypespec: \_string_typespec: @@ -1035,13 +1035,13 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.mtime_counter.lg_max_val_lp), line:4:17, endln:4:30 |vpiParent: - \_module: work@bsg_counter_set_en (work@top.mtime_counter), file:${SURELOG_DIR}/tests/BlackParrotSkipParam/dut.sv, line:10:1, endln:14:18 + \_module_inst: work@bsg_counter_set_en (work@top.mtime_counter), file:${SURELOG_DIR}/tests/BlackParrotSkipParam/dut.sv, line:10:1, endln:14:18 |vpiName:lg_max_val_lp |vpiFullName:work@top.mtime_counter.lg_max_val_lp |vpiParameter: \_parameter: (work@top.mtime_counter.reset_val_p), line:5:17, endln:5:28 |vpiParent: - \_module: work@bsg_counter_set_en (work@top.mtime_counter), file:${SURELOG_DIR}/tests/BlackParrotSkipParam/dut.sv, line:10:1, endln:14:18 + \_module_inst: work@bsg_counter_set_en (work@top.mtime_counter), file:${SURELOG_DIR}/tests/BlackParrotSkipParam/dut.sv, line:10:1, endln:14:18 |UINT:0 |vpiTypespec: \_int_typespec: @@ -1052,7 +1052,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:3:15, endln:3:30 |vpiParent: - \_module: work@bsg_counter_set_en (work@top.mtime_counter), file:${SURELOG_DIR}/tests/BlackParrotSkipParam/dut.sv, line:10:1, endln:14:18 + \_module_inst: work@bsg_counter_set_en (work@top.mtime_counter), file:${SURELOG_DIR}/tests/BlackParrotSkipParam/dut.sv, line:10:1, endln:14:18 |vpiRhs: \_constant: , line:3:25, endln:3:30 |vpiDecompile:inv @@ -1066,7 +1066,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:4:17, endln:4:52 |vpiParent: - \_module: work@bsg_counter_set_en (work@top.mtime_counter), file:${SURELOG_DIR}/tests/BlackParrotSkipParam/dut.sv, line:10:1, endln:14:18 + \_module_inst: work@bsg_counter_set_en (work@top.mtime_counter), file:${SURELOG_DIR}/tests/BlackParrotSkipParam/dut.sv, line:10:1, endln:14:18 |vpiOverriden:1 |vpiRhs: \_constant: , line:4:31, endln:4:52 @@ -1079,7 +1079,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:5:17, endln:5:30 |vpiParent: - \_module: work@bsg_counter_set_en (work@top.mtime_counter), file:${SURELOG_DIR}/tests/BlackParrotSkipParam/dut.sv, line:10:1, endln:14:18 + \_module_inst: work@bsg_counter_set_en (work@top.mtime_counter), file:${SURELOG_DIR}/tests/BlackParrotSkipParam/dut.sv, line:10:1, endln:14:18 |vpiOverriden:1 |vpiRhs: \_constant: , line:5:29, endln:5:30 @@ -1095,7 +1095,7 @@ design: (work@top) |vpiDefFile:${SURELOG_DIR}/tests/BlackParrotSkipParam/dut.sv |vpiDefLineNo:2 |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/BlackParrotSkipParam/dut.sv, line:9:1, endln:17:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/BlackParrotSkipParam/dut.sv, line:9:1, endln:17:10 =================== [ FATAL] : 0 [ SYNTAX] : 0 diff --git a/tests/BlackParrotStructParam/BlackParrotStructParam.log b/tests/BlackParrotStructParam/BlackParrotStructParam.log index 7ca44a3e5d..868888eb75 100644 --- a/tests/BlackParrotStructParam/BlackParrotStructParam.log +++ b/tests/BlackParrotStructParam/BlackParrotStructParam.log @@ -676,7 +676,7 @@ io_decl 11 logic_net 1 logic_typespec 1 logic_var 2 -module 7 +module_inst 7 operation 83 package 5 packed_array_typespec 8 @@ -715,7 +715,7 @@ io_decl 22 logic_net 1 logic_typespec 1 logic_var 2 -module 8 +module_inst 8 operation 83 package 5 packed_array_typespec 8 @@ -1083,7 +1083,7 @@ design: (work@top) |vpiTypespec: \_struct_typespec: (bp_common_aviary_pkg::bp_proc_param_s), line:5:9, endln:5:15 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/BlackParrotStructParam/dut.sv, line:55:1, endln:66:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/BlackParrotStructParam/dut.sv, line:55:1, endln:66:10 |vpiName:bp_common_aviary_pkg::bp_proc_param_s |vpiInstance: \_package: bp_common_aviary_pkg (bp_common_aviary_pkg::), file:${SURELOG_DIR}/tests/BlackParrotStructParam/dut.sv, line:1:1, endln:53:11 @@ -1305,7 +1305,7 @@ design: (work@top) |vpiTypedef: \_enum_typespec: (bp_common_aviary_pkg::bp_params_e), line:48:2, endln:51:17 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/BlackParrotStructParam/dut.sv, line:55:1, endln:66:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/BlackParrotStructParam/dut.sv, line:55:1, endln:66:10 |vpiName:bp_common_aviary_pkg::bp_params_e |vpiInstance: \_package: bp_common_aviary_pkg (bp_common_aviary_pkg::), file:${SURELOG_DIR}/tests/BlackParrotStructParam/dut.sv, line:1:1, endln:53:11 @@ -1777,14 +1777,14 @@ design: (work@top) \_int_typespec: |vpiSigned:1 |uhdmallModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/BlackParrotStructParam/dut.sv, line:55:1, endln:66:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/BlackParrotStructParam/dut.sv, line:55:1, endln:66:10 |vpiParent: \_design: (work@top) |vpiFullName:work@top |vpiParameter: \_parameter: (work@top.all_cfgs_gp), line:42:41, endln:42:52 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/BlackParrotStructParam/dut.sv, line:55:1, endln:66:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/BlackParrotStructParam/dut.sv, line:55:1, endln:66:10 |vpiTypespec: \_packed_array_typespec: , line:42:12, endln:42:27 |vpiParent: @@ -1846,7 +1846,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.bp_default_cfg_p), line:10:30, endln:10:46 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/BlackParrotStructParam/dut.sv, line:55:1, endln:66:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/BlackParrotStructParam/dut.sv, line:55:1, endln:66:10 |vpiTypespec: \_struct_typespec: (bp_common_aviary_pkg::bp_proc_param_s), line:5:9, endln:5:15 |vpiParent: @@ -1879,7 +1879,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.bp_multicore_1_cce_ucode_cfg_p), line:22:29, endln:22:59 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/BlackParrotStructParam/dut.sv, line:55:1, endln:66:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/BlackParrotStructParam/dut.sv, line:55:1, endln:66:10 |vpiTypespec: \_struct_typespec: (bp_common_aviary_pkg::bp_proc_param_s), line:5:9, endln:5:15 |vpiParent: @@ -1912,7 +1912,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.bp_multicore_cce_ucode_half_cfg_p), line:32:28, endln:32:61 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/BlackParrotStructParam/dut.sv, line:55:1, endln:66:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/BlackParrotStructParam/dut.sv, line:55:1, endln:66:10 |vpiTypespec: \_struct_typespec: (bp_common_aviary_pkg::bp_proc_param_s), line:5:9, endln:5:15 |vpiParent: @@ -1945,7 +1945,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.bp_multicore_cce_ucode_half_override_p), line:17:30, endln:17:68 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/BlackParrotStructParam/dut.sv, line:55:1, endln:66:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/BlackParrotStructParam/dut.sv, line:55:1, endln:66:10 |vpiTypespec: \_struct_typespec: (bp_common_aviary_pkg::bp_proc_param_s), line:5:9, endln:5:15 |vpiParent: @@ -1978,7 +1978,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.bp_unicore_cfg_p), line:15:29, endln:15:45 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/BlackParrotStructParam/dut.sv, line:55:1, endln:66:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/BlackParrotStructParam/dut.sv, line:55:1, endln:66:10 |vpiTypespec: \_struct_typespec: (bp_common_aviary_pkg::bp_proc_param_s), line:5:9, endln:5:15 |vpiParent: @@ -2011,7 +2011,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.max_cfgs), line:3:14, endln:3:22 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/BlackParrotStructParam/dut.sv, line:55:1, endln:66:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/BlackParrotStructParam/dut.sv, line:55:1, endln:66:10 |UINT:1 |vpiTypespec: \_int_typespec: @@ -2024,7 +2024,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.bp_params_p), line:56:25, endln:56:36 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/BlackParrotStructParam/dut.sv, line:55:1, endln:66:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/BlackParrotStructParam/dut.sv, line:55:1, endln:66:10 |vpiTypespec: \_enum_typespec: (bp_common_aviary_pkg::bp_params_e), line:48:2, endln:51:17 |vpiName:bp_params_p @@ -2032,7 +2032,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.proc_param_lp), line:57:30, endln:57:43 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/BlackParrotStructParam/dut.sv, line:55:1, endln:66:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/BlackParrotStructParam/dut.sv, line:55:1, endln:66:10 |vpiTypespec: \_struct_typespec: (bp_common_aviary_pkg::bp_proc_param_s), line:5:9, endln:5:15 |vpiLocalParam:1 @@ -2041,14 +2041,14 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.cc_x_dim_p), line:58:14, endln:58:24 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/BlackParrotStructParam/dut.sv, line:55:1, endln:66:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/BlackParrotStructParam/dut.sv, line:55:1, endln:66:10 |vpiLocalParam:1 |vpiName:cc_x_dim_p |vpiFullName:work@top.cc_x_dim_p |vpiParamAssign: \_param_assign: , line:3:14, endln:3:29 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/BlackParrotStructParam/dut.sv, line:55:1, endln:66:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/BlackParrotStructParam/dut.sv, line:55:1, endln:66:10 |vpiRhs: \_constant: , line:3:28, endln:3:29 |vpiParent: @@ -2077,7 +2077,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:10:30, endln:13:8 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/BlackParrotStructParam/dut.sv, line:55:1, endln:66:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/BlackParrotStructParam/dut.sv, line:55:1, endln:66:10 |vpiRhs: \_operation: , line:11:5, endln:13:8 |vpiParent: @@ -2136,7 +2136,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:15:29, endln:15:64 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/BlackParrotStructParam/dut.sv, line:55:1, endln:66:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/BlackParrotStructParam/dut.sv, line:55:1, endln:66:10 |vpiRhs: \_ref_obj: (work@top.bp_default_cfg_p), line:15:48, endln:15:64 |vpiParent: @@ -2179,7 +2179,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:17:30, endln:20:8 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/BlackParrotStructParam/dut.sv, line:55:1, endln:66:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/BlackParrotStructParam/dut.sv, line:55:1, endln:66:10 |vpiRhs: \_operation: , line:18:5, endln:20:8 |vpiParent: @@ -2238,7 +2238,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:22:29, endln:30:8 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/BlackParrotStructParam/dut.sv, line:55:1, endln:66:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/BlackParrotStructParam/dut.sv, line:55:1, endln:66:10 |vpiRhs: \_operation: , line:23:7, endln:30:8 |vpiParent: @@ -2297,7 +2297,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:32:28, endln:40:10 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/BlackParrotStructParam/dut.sv, line:55:1, endln:66:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/BlackParrotStructParam/dut.sv, line:55:1, endln:66:10 |vpiRhs: \_operation: , line:33:7, endln:40:10 |vpiParent: @@ -2356,7 +2356,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:42:41, endln:46:4 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/BlackParrotStructParam/dut.sv, line:55:1, endln:66:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/BlackParrotStructParam/dut.sv, line:55:1, endln:66:10 |vpiRhs: \_operation: , line:43:3, endln:46:4 |vpiParent: @@ -2434,7 +2434,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:56:25, endln:56:55 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/BlackParrotStructParam/dut.sv, line:55:1, endln:66:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/BlackParrotStructParam/dut.sv, line:55:1, endln:66:10 |vpiRhs: \_ref_obj: (e_bp_default_cfg), line:56:39, endln:56:55 |vpiName:e_bp_default_cfg @@ -2445,7 +2445,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:57:30, endln:57:70 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/BlackParrotStructParam/dut.sv, line:55:1, endln:66:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/BlackParrotStructParam/dut.sv, line:55:1, endln:66:10 |vpiRhs: \_bit_select: (all_cfgs_gp), line:57:46, endln:57:70 |vpiParent: @@ -2463,7 +2463,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:58:14, endln:58:50 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/BlackParrotStructParam/dut.sv, line:55:1, endln:66:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/BlackParrotStructParam/dut.sv, line:55:1, endln:66:10 |vpiRhs: \_hier_path: (proc_param_lp.cc_x_dim), line:58:28, endln:58:50 |vpiName:proc_param_lp.cc_x_dim @@ -2487,17 +2487,17 @@ design: (work@top) |vpiNet: \_logic_net: (work@top.aa), line:60:25, endln:60:27 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/BlackParrotStructParam/dut.sv, line:55:1, endln:66:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/BlackParrotStructParam/dut.sv, line:55:1, endln:66:10 |vpiName:aa |vpiFullName:work@top.aa |vpiNetType:36 |uhdmtopModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/BlackParrotStructParam/dut.sv, line:55:1, endln:66:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/BlackParrotStructParam/dut.sv, line:55:1, endln:66:10 |vpiName:work@top |vpiVariables: \_logic_var: (work@top.aa), line:60:25, endln:60:27 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/BlackParrotStructParam/dut.sv, line:55:1, endln:66:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/BlackParrotStructParam/dut.sv, line:55:1, endln:66:10 |vpiTypespec: \_logic_typespec: , line:60:2, endln:60:24 |vpiRange: @@ -2542,7 +2542,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.all_cfgs_gp), line:42:41, endln:42:52 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/BlackParrotStructParam/dut.sv, line:55:1, endln:66:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/BlackParrotStructParam/dut.sv, line:55:1, endln:66:10 |vpiTypespec: \_packed_array_typespec: , line:42:12, endln:42:27 |vpiParent: @@ -2604,7 +2604,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.bp_default_cfg_p), line:10:30, endln:10:46 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/BlackParrotStructParam/dut.sv, line:55:1, endln:66:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/BlackParrotStructParam/dut.sv, line:55:1, endln:66:10 |vpiTypespec: \_struct_typespec: (bp_common_aviary_pkg::bp_proc_param_s), line:5:9, endln:5:15 |vpiParent: @@ -2637,7 +2637,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.bp_multicore_1_cce_ucode_cfg_p), line:22:29, endln:22:59 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/BlackParrotStructParam/dut.sv, line:55:1, endln:66:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/BlackParrotStructParam/dut.sv, line:55:1, endln:66:10 |vpiTypespec: \_struct_typespec: (bp_common_aviary_pkg::bp_proc_param_s), line:5:9, endln:5:15 |vpiParent: @@ -2670,7 +2670,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.bp_multicore_cce_ucode_half_cfg_p), line:32:28, endln:32:61 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/BlackParrotStructParam/dut.sv, line:55:1, endln:66:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/BlackParrotStructParam/dut.sv, line:55:1, endln:66:10 |vpiTypespec: \_struct_typespec: (bp_common_aviary_pkg::bp_proc_param_s), line:5:9, endln:5:15 |vpiParent: @@ -2703,7 +2703,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.bp_multicore_cce_ucode_half_override_p), line:17:30, endln:17:68 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/BlackParrotStructParam/dut.sv, line:55:1, endln:66:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/BlackParrotStructParam/dut.sv, line:55:1, endln:66:10 |vpiTypespec: \_struct_typespec: (bp_common_aviary_pkg::bp_proc_param_s), line:5:9, endln:5:15 |vpiParent: @@ -2736,7 +2736,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.bp_unicore_cfg_p), line:15:29, endln:15:45 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/BlackParrotStructParam/dut.sv, line:55:1, endln:66:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/BlackParrotStructParam/dut.sv, line:55:1, endln:66:10 |vpiTypespec: \_struct_typespec: (bp_common_aviary_pkg::bp_proc_param_s), line:5:9, endln:5:15 |vpiParent: @@ -2769,7 +2769,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.max_cfgs), line:3:14, endln:3:22 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/BlackParrotStructParam/dut.sv, line:55:1, endln:66:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/BlackParrotStructParam/dut.sv, line:55:1, endln:66:10 |UINT:1 |vpiTypespec: \_int_typespec: @@ -2782,7 +2782,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.bp_params_p), line:56:25, endln:56:36 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/BlackParrotStructParam/dut.sv, line:55:1, endln:66:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/BlackParrotStructParam/dut.sv, line:55:1, endln:66:10 |vpiTypespec: \_enum_typespec: (bp_common_aviary_pkg::bp_params_e), line:48:2, endln:51:17 |vpiParent: @@ -2834,7 +2834,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.proc_param_lp), line:57:30, endln:57:43 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/BlackParrotStructParam/dut.sv, line:55:1, endln:66:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/BlackParrotStructParam/dut.sv, line:55:1, endln:66:10 |vpiTypespec: \_struct_typespec: (bp_common_aviary_pkg::bp_proc_param_s), line:5:9, endln:5:15 |vpiParent: @@ -2866,14 +2866,14 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.cc_x_dim_p), line:58:14, endln:58:24 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/BlackParrotStructParam/dut.sv, line:55:1, endln:66:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/BlackParrotStructParam/dut.sv, line:55:1, endln:66:10 |vpiLocalParam:1 |vpiName:cc_x_dim_p |vpiFullName:work@top.cc_x_dim_p |vpiParamAssign: \_param_assign: , line:56:25, endln:56:55 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/BlackParrotStructParam/dut.sv, line:55:1, endln:66:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/BlackParrotStructParam/dut.sv, line:55:1, endln:66:10 |vpiRhs: \_constant: , line:56:39, endln:56:55 |vpiDecompile:0 @@ -2887,7 +2887,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:57:30, endln:57:70 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/BlackParrotStructParam/dut.sv, line:55:1, endln:66:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/BlackParrotStructParam/dut.sv, line:55:1, endln:66:10 |vpiRhs: \_bit_select: (all_cfgs_gp), line:57:46, endln:57:70 |vpiParent: @@ -2953,7 +2953,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:58:14, endln:58:50 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/BlackParrotStructParam/dut.sv, line:55:1, endln:66:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/BlackParrotStructParam/dut.sv, line:55:1, endln:66:10 |vpiRhs: \_constant: , line:58:28, endln:58:50 |vpiDecompile:1 @@ -2965,7 +2965,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:3:14, endln:3:29 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/BlackParrotStructParam/dut.sv, line:55:1, endln:66:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/BlackParrotStructParam/dut.sv, line:55:1, endln:66:10 |vpiRhs: \_constant: , line:3:28, endln:3:29 |vpiDecompile:1 @@ -2979,7 +2979,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:10:30, endln:13:8 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/BlackParrotStructParam/dut.sv, line:55:1, endln:66:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/BlackParrotStructParam/dut.sv, line:55:1, endln:66:10 |vpiRhs: \_operation: , line:11:5, endln:13:8 |vpiParent: @@ -3023,7 +3023,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:15:29, endln:15:64 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/BlackParrotStructParam/dut.sv, line:55:1, endln:66:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/BlackParrotStructParam/dut.sv, line:55:1, endln:66:10 |vpiRhs: \_ref_obj: (bp_default_cfg_p), line:15:48, endln:15:64 |vpiName:bp_default_cfg_p @@ -3034,7 +3034,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:17:30, endln:20:8 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/BlackParrotStructParam/dut.sv, line:55:1, endln:66:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/BlackParrotStructParam/dut.sv, line:55:1, endln:66:10 |vpiRhs: \_operation: , line:18:5, endln:20:8 |vpiParent: @@ -3078,7 +3078,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:22:29, endln:30:8 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/BlackParrotStructParam/dut.sv, line:55:1, endln:66:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/BlackParrotStructParam/dut.sv, line:55:1, endln:66:10 |vpiRhs: \_operation: , line:23:7, endln:30:8 |vpiParent: @@ -3122,7 +3122,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:32:28, endln:40:10 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/BlackParrotStructParam/dut.sv, line:55:1, endln:66:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/BlackParrotStructParam/dut.sv, line:55:1, endln:66:10 |vpiRhs: \_operation: , line:33:7, endln:40:10 |vpiParent: @@ -3166,7 +3166,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:42:41, endln:46:4 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/BlackParrotStructParam/dut.sv, line:55:1, endln:66:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/BlackParrotStructParam/dut.sv, line:55:1, endln:66:10 |vpiRhs: \_operation: , line:43:3, endln:46:4 |vpiTypespec: @@ -3247,7 +3247,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.genblk1), line:62:2, endln:64:5 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/BlackParrotStructParam/dut.sv, line:55:1, endln:66:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/BlackParrotStructParam/dut.sv, line:55:1, endln:66:10 |vpiName:genblk1 |vpiFullName:work@top.genblk1 |vpiGenScope: @@ -3255,8 +3255,8 @@ design: (work@top) |vpiParent: \_gen_scope_array: (work@top.genblk1), line:62:2, endln:64:5 |vpiFullName:work@top.genblk1 - |vpiModule: - \_module: work@top.genblk1::OK (work@top.genblk1.ok), file:${SURELOG_DIR}/tests/BlackParrotStructParam/dut.sv, line:63:5, endln:63:13 + |vpiModuleInst: + \_module_inst: work@top.genblk1::OK (work@top.genblk1.ok), file:${SURELOG_DIR}/tests/BlackParrotStructParam/dut.sv, line:63:5, endln:63:13 |vpiParent: \_gen_scope: (work@top.genblk1) |vpiName:ok diff --git a/tests/BlackboxMissingDef/BlackboxMissingDef.log b/tests/BlackboxMissingDef/BlackboxMissingDef.log index b142940363..0bcb2fdf79 100644 --- a/tests/BlackboxMissingDef/BlackboxMissingDef.log +++ b/tests/BlackboxMissingDef/BlackboxMissingDef.log @@ -95,7 +95,7 @@ constant 21 design 1 logic_net 2 logic_typespec 3 -module 5 +module_inst 5 operation 3 param_assign 2 parameter 2 @@ -112,7 +112,7 @@ constant 21 design 1 logic_net 2 logic_typespec 3 -module 5 +module_inst 5 operation 3 param_assign 2 parameter 2 @@ -133,7 +133,7 @@ design: (work@top) |vpiElaborated:1 |vpiName:work@top |uhdmallModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/BlackboxMissingDef/dut.sv, line:1:1, endln:5:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/BlackboxMissingDef/dut.sv, line:1:1, endln:5:10 |vpiParent: \_design: (work@top) |vpiFullName:work@top @@ -141,14 +141,14 @@ design: (work@top) |vpiNet: \_logic_net: (work@top.e), line:1:30, endln:1:31 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/BlackboxMissingDef/dut.sv, line:1:1, endln:5:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/BlackboxMissingDef/dut.sv, line:1:1, endln:5:10 |vpiName:e |vpiFullName:work@top.e |vpiNetType:36 |vpiPort: \_port: (e), line:1:30, endln:1:31 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/BlackboxMissingDef/dut.sv, line:1:1, endln:5:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/BlackboxMissingDef/dut.sv, line:1:1, endln:5:10 |vpiName:e |vpiDirection:1 |vpiLowConn: @@ -207,14 +207,14 @@ design: (work@top) |UINT:0 |vpiConstType:9 |uhdmtopModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/BlackboxMissingDef/dut.sv, line:1:1, endln:5:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/BlackboxMissingDef/dut.sv, line:1:1, endln:5:10 |vpiName:work@top |vpiDefName:work@top |vpiTop:1 |vpiArrayNet: \_array_net: (work@top.e), line:1:30, endln:1:31 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/BlackboxMissingDef/dut.sv, line:1:1, endln:5:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/BlackboxMissingDef/dut.sv, line:1:1, endln:5:10 |vpiSize:2 |vpiName:e |vpiFullName:work@top.e @@ -274,7 +274,7 @@ design: (work@top) |vpiPort: \_port: (e), line:1:30, endln:1:31 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/BlackboxMissingDef/dut.sv, line:1:1, endln:5:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/BlackboxMissingDef/dut.sv, line:1:1, endln:5:10 |vpiName:e |vpiDirection:1 |vpiLowConn: @@ -308,17 +308,17 @@ design: (work@top) |UINT:0 |vpiConstType:9 |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/BlackboxMissingDef/dut.sv, line:1:1, endln:5:10 - |vpiModule: - \_module: work@top::PLLE2_ADV (work@top.pll), file:${SURELOG_DIR}/tests/BlackboxMissingDef/dut.sv, line:2:4, endln:4:13 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/BlackboxMissingDef/dut.sv, line:1:1, endln:5:10 + |vpiModuleInst: + \_module_inst: work@top::PLLE2_ADV (work@top.pll), file:${SURELOG_DIR}/tests/BlackboxMissingDef/dut.sv, line:2:4, endln:4:13 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/BlackboxMissingDef/dut.sv, line:1:1, endln:5:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/BlackboxMissingDef/dut.sv, line:1:1, endln:5:10 |vpiName:pll |vpiFullName:work@top.pll |vpiParamAssign: \_param_assign: |vpiParent: - \_module: work@top::PLLE2_ADV (work@top.pll), file:${SURELOG_DIR}/tests/BlackboxMissingDef/dut.sv, line:2:4, endln:4:13 + \_module_inst: work@top::PLLE2_ADV (work@top.pll), file:${SURELOG_DIR}/tests/BlackboxMissingDef/dut.sv, line:2:4, endln:4:13 |vpiOverriden:1 |vpiRhs: \_constant: , line:3:0, endln:3:0 @@ -332,7 +332,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: |vpiParent: - \_module: work@top::PLLE2_ADV (work@top.pll), file:${SURELOG_DIR}/tests/BlackboxMissingDef/dut.sv, line:2:4, endln:4:13 + \_module_inst: work@top::PLLE2_ADV (work@top.pll), file:${SURELOG_DIR}/tests/BlackboxMissingDef/dut.sv, line:2:4, endln:4:13 |vpiOverriden:1 |vpiRhs: \_constant: , line:3:0, endln:3:0 @@ -345,7 +345,7 @@ design: (work@top) |vpiName:TEST2 |vpiDefName:work@top::PLLE2_ADV |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/BlackboxMissingDef/dut.sv, line:1:1, endln:5:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/BlackboxMissingDef/dut.sv, line:1:1, endln:5:10 =================== [ FATAL] : 0 [ SYNTAX] : 0 diff --git a/tests/BuiltInMethod/BuiltInMethod.log b/tests/BuiltInMethod/BuiltInMethod.log index 307029aece..0b9cdfbff1 100644 --- a/tests/BuiltInMethod/BuiltInMethod.log +++ b/tests/BuiltInMethod/BuiltInMethod.log @@ -162,7 +162,7 @@ design 1 hier_path 4 logic_net 5 method_func_call 4 -module 3 +module_inst 3 operation 1 range 1 ref_obj 4 @@ -179,7 +179,7 @@ design 1 hier_path 4 logic_net 5 method_func_call 4 -module 3 +module_inst 3 operation 1 range 1 ref_obj 4 @@ -197,7 +197,7 @@ design: (work@top) |vpiElaborated:1 |vpiName:work@top |uhdmallModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/BuiltInMethod/dut.sv, line:1:1, endln:7:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/BuiltInMethod/dut.sv, line:1:1, endln:7:10 |vpiParent: \_design: (work@top) |vpiFullName:work@top @@ -205,40 +205,40 @@ design: (work@top) |vpiNet: \_logic_net: (work@top.b), line:2:10, endln:2:11 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/BuiltInMethod/dut.sv, line:1:1, endln:7:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/BuiltInMethod/dut.sv, line:1:1, endln:7:10 |vpiName:b |vpiFullName:work@top.b |vpiNet: \_logic_net: (work@top.o), line:3:10, endln:3:11 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/BuiltInMethod/dut.sv, line:1:1, endln:7:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/BuiltInMethod/dut.sv, line:1:1, endln:7:10 |vpiName:o |vpiFullName:work@top.o |vpiNet: \_logic_net: (work@top.o), line:4:10, endln:4:11 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/BuiltInMethod/dut.sv, line:1:1, endln:7:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/BuiltInMethod/dut.sv, line:1:1, endln:7:10 |vpiName:o |vpiFullName:work@top.o |vpiNet: \_logic_net: (work@top.o), line:5:10, endln:5:11 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/BuiltInMethod/dut.sv, line:1:1, endln:7:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/BuiltInMethod/dut.sv, line:1:1, endln:7:10 |vpiName:o |vpiFullName:work@top.o |vpiNet: \_logic_net: (work@top.o), line:6:10, endln:6:11 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/BuiltInMethod/dut.sv, line:1:1, endln:7:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/BuiltInMethod/dut.sv, line:1:1, endln:7:10 |vpiName:o |vpiFullName:work@top.o |uhdmtopModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/BuiltInMethod/dut.sv, line:1:1, endln:7:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/BuiltInMethod/dut.sv, line:1:1, endln:7:10 |vpiName:work@top |vpiVariables: \_array_var: (work@top.b), line:2:10, endln:2:13 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/BuiltInMethod/dut.sv, line:1:1, endln:7:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/BuiltInMethod/dut.sv, line:1:1, endln:7:10 |vpiSize:1 |vpiTypespec: \_array_typespec: @@ -287,7 +287,7 @@ design: (work@top) |vpiVariables: \_byte_var: (work@top.o), line:3:10, endln:3:19 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/BuiltInMethod/dut.sv, line:1:1, endln:7:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/BuiltInMethod/dut.sv, line:1:1, endln:7:10 |vpiTypespec: \_byte_typespec: , line:3:5, endln:3:9 |vpiSigned:1 @@ -308,7 +308,7 @@ design: (work@top) |vpiVariables: \_byte_var: (work@top.o), line:4:10, endln:4:18 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/BuiltInMethod/dut.sv, line:1:1, endln:7:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/BuiltInMethod/dut.sv, line:1:1, endln:7:10 |vpiTypespec: \_byte_typespec: , line:4:5, endln:4:9 |vpiSigned:1 @@ -329,7 +329,7 @@ design: (work@top) |vpiVariables: \_byte_var: (work@top.o), line:5:10, endln:5:19 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/BuiltInMethod/dut.sv, line:1:1, endln:7:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/BuiltInMethod/dut.sv, line:1:1, endln:7:10 |vpiTypespec: \_byte_typespec: , line:5:5, endln:5:9 |vpiSigned:1 @@ -350,7 +350,7 @@ design: (work@top) |vpiVariables: \_byte_var: (work@top.o), line:6:10, endln:6:22 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/BuiltInMethod/dut.sv, line:1:1, endln:7:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/BuiltInMethod/dut.sv, line:1:1, endln:7:10 |vpiTypespec: \_byte_typespec: , line:6:5, endln:6:9 |vpiSigned:1 diff --git a/tests/CarryTrans/CarryTrans.log b/tests/CarryTrans/CarryTrans.log index 3ff05f2c46..97f4eb2d46 100644 --- a/tests/CarryTrans/CarryTrans.log +++ b/tests/CarryTrans/CarryTrans.log @@ -854,7 +854,7 @@ io_decl 11 logic_net 46 logic_typespec 30 logic_var 1 -module 7 +module_inst 7 operation 10 package 2 port 73 @@ -883,7 +883,7 @@ io_decl 22 logic_net 46 logic_typespec 30 logic_var 1 -module 7 +module_inst 7 operation 15 package 2 port 85 @@ -1380,7 +1380,7 @@ design: (work@carry_rtl) \_int_typespec: |vpiSigned:1 |uhdmallModules: -\_module: work@carry_gate (work@carry_gate), file:${SURELOG_DIR}/tests/CarryTrans/dut.sv, line:8:1, endln:16:10 +\_module_inst: work@carry_gate (work@carry_gate), file:${SURELOG_DIR}/tests/CarryTrans/dut.sv, line:8:1, endln:16:10 |vpiParent: \_design: (work@carry_rtl) |vpiFullName:work@carry_gate @@ -1388,52 +1388,52 @@ design: (work@carry_rtl) |vpiNet: \_logic_net: (work@carry_gate.a), line:8:25, endln:8:26 |vpiParent: - \_module: work@carry_gate (work@carry_gate), file:${SURELOG_DIR}/tests/CarryTrans/dut.sv, line:8:1, endln:16:10 + \_module_inst: work@carry_gate (work@carry_gate), file:${SURELOG_DIR}/tests/CarryTrans/dut.sv, line:8:1, endln:16:10 |vpiName:a |vpiFullName:work@carry_gate.a |vpiNet: \_logic_net: (work@carry_gate.b), line:8:28, endln:8:29 |vpiParent: - \_module: work@carry_gate (work@carry_gate), file:${SURELOG_DIR}/tests/CarryTrans/dut.sv, line:8:1, endln:16:10 + \_module_inst: work@carry_gate (work@carry_gate), file:${SURELOG_DIR}/tests/CarryTrans/dut.sv, line:8:1, endln:16:10 |vpiName:b |vpiFullName:work@carry_gate.b |vpiNet: \_logic_net: (work@carry_gate.c), line:8:31, endln:8:32 |vpiParent: - \_module: work@carry_gate (work@carry_gate), file:${SURELOG_DIR}/tests/CarryTrans/dut.sv, line:8:1, endln:16:10 + \_module_inst: work@carry_gate (work@carry_gate), file:${SURELOG_DIR}/tests/CarryTrans/dut.sv, line:8:1, endln:16:10 |vpiName:c |vpiFullName:work@carry_gate.c |vpiNet: \_logic_net: (work@carry_gate.cout), line:9:12, endln:9:16 |vpiParent: - \_module: work@carry_gate (work@carry_gate), file:${SURELOG_DIR}/tests/CarryTrans/dut.sv, line:8:1, endln:16:10 + \_module_inst: work@carry_gate (work@carry_gate), file:${SURELOG_DIR}/tests/CarryTrans/dut.sv, line:8:1, endln:16:10 |vpiName:cout |vpiFullName:work@carry_gate.cout |vpiNet: \_logic_net: (work@carry_gate.x), line:11:6, endln:11:7 |vpiParent: - \_module: work@carry_gate (work@carry_gate), file:${SURELOG_DIR}/tests/CarryTrans/dut.sv, line:8:1, endln:16:10 + \_module_inst: work@carry_gate (work@carry_gate), file:${SURELOG_DIR}/tests/CarryTrans/dut.sv, line:8:1, endln:16:10 |vpiName:x |vpiFullName:work@carry_gate.x |vpiNetType:1 |vpiNet: \_logic_net: (work@carry_gate.y), line:11:9, endln:11:10 |vpiParent: - \_module: work@carry_gate (work@carry_gate), file:${SURELOG_DIR}/tests/CarryTrans/dut.sv, line:8:1, endln:16:10 + \_module_inst: work@carry_gate (work@carry_gate), file:${SURELOG_DIR}/tests/CarryTrans/dut.sv, line:8:1, endln:16:10 |vpiName:y |vpiFullName:work@carry_gate.y |vpiNetType:1 |vpiNet: \_logic_net: (work@carry_gate.z), line:11:12, endln:11:13 |vpiParent: - \_module: work@carry_gate (work@carry_gate), file:${SURELOG_DIR}/tests/CarryTrans/dut.sv, line:8:1, endln:16:10 + \_module_inst: work@carry_gate (work@carry_gate), file:${SURELOG_DIR}/tests/CarryTrans/dut.sv, line:8:1, endln:16:10 |vpiName:z |vpiFullName:work@carry_gate.z |vpiNetType:1 |vpiPort: \_port: (a), line:8:25, endln:8:26 |vpiParent: - \_module: work@carry_gate (work@carry_gate), file:${SURELOG_DIR}/tests/CarryTrans/dut.sv, line:8:1, endln:16:10 + \_module_inst: work@carry_gate (work@carry_gate), file:${SURELOG_DIR}/tests/CarryTrans/dut.sv, line:8:1, endln:16:10 |vpiName:a |vpiDirection:1 |vpiLowConn: @@ -1445,7 +1445,7 @@ design: (work@carry_rtl) |vpiPort: \_port: (b), line:8:28, endln:8:29 |vpiParent: - \_module: work@carry_gate (work@carry_gate), file:${SURELOG_DIR}/tests/CarryTrans/dut.sv, line:8:1, endln:16:10 + \_module_inst: work@carry_gate (work@carry_gate), file:${SURELOG_DIR}/tests/CarryTrans/dut.sv, line:8:1, endln:16:10 |vpiName:b |vpiDirection:1 |vpiLowConn: @@ -1457,7 +1457,7 @@ design: (work@carry_rtl) |vpiPort: \_port: (c), line:8:31, endln:8:32 |vpiParent: - \_module: work@carry_gate (work@carry_gate), file:${SURELOG_DIR}/tests/CarryTrans/dut.sv, line:8:1, endln:16:10 + \_module_inst: work@carry_gate (work@carry_gate), file:${SURELOG_DIR}/tests/CarryTrans/dut.sv, line:8:1, endln:16:10 |vpiName:c |vpiDirection:1 |vpiLowConn: @@ -1469,7 +1469,7 @@ design: (work@carry_rtl) |vpiPort: \_port: (cout), line:9:12, endln:9:16 |vpiParent: - \_module: work@carry_gate (work@carry_gate), file:${SURELOG_DIR}/tests/CarryTrans/dut.sv, line:8:1, endln:16:10 + \_module_inst: work@carry_gate (work@carry_gate), file:${SURELOG_DIR}/tests/CarryTrans/dut.sv, line:8:1, endln:16:10 |vpiName:cout |vpiDirection:2 |vpiLowConn: @@ -1479,7 +1479,7 @@ design: (work@carry_rtl) |vpiTypedef: \_logic_typespec: , line:9:12, endln:9:12 |uhdmallModules: -\_module: work@carry_rtl (work@carry_rtl), file:${SURELOG_DIR}/tests/CarryTrans/dut.sv, line:1:1, endln:5:10 +\_module_inst: work@carry_rtl (work@carry_rtl), file:${SURELOG_DIR}/tests/CarryTrans/dut.sv, line:1:1, endln:5:10 |vpiParent: \_design: (work@carry_rtl) |vpiFullName:work@carry_rtl @@ -1487,31 +1487,31 @@ design: (work@carry_rtl) |vpiNet: \_logic_net: (work@carry_rtl.a), line:1:24, endln:1:25 |vpiParent: - \_module: work@carry_rtl (work@carry_rtl), file:${SURELOG_DIR}/tests/CarryTrans/dut.sv, line:1:1, endln:5:10 + \_module_inst: work@carry_rtl (work@carry_rtl), file:${SURELOG_DIR}/tests/CarryTrans/dut.sv, line:1:1, endln:5:10 |vpiName:a |vpiFullName:work@carry_rtl.a |vpiNet: \_logic_net: (work@carry_rtl.b), line:1:27, endln:1:28 |vpiParent: - \_module: work@carry_rtl (work@carry_rtl), file:${SURELOG_DIR}/tests/CarryTrans/dut.sv, line:1:1, endln:5:10 + \_module_inst: work@carry_rtl (work@carry_rtl), file:${SURELOG_DIR}/tests/CarryTrans/dut.sv, line:1:1, endln:5:10 |vpiName:b |vpiFullName:work@carry_rtl.b |vpiNet: \_logic_net: (work@carry_rtl.c), line:1:30, endln:1:31 |vpiParent: - \_module: work@carry_rtl (work@carry_rtl), file:${SURELOG_DIR}/tests/CarryTrans/dut.sv, line:1:1, endln:5:10 + \_module_inst: work@carry_rtl (work@carry_rtl), file:${SURELOG_DIR}/tests/CarryTrans/dut.sv, line:1:1, endln:5:10 |vpiName:c |vpiFullName:work@carry_rtl.c |vpiNet: \_logic_net: (work@carry_rtl.cout), line:2:11, endln:2:15 |vpiParent: - \_module: work@carry_rtl (work@carry_rtl), file:${SURELOG_DIR}/tests/CarryTrans/dut.sv, line:1:1, endln:5:10 + \_module_inst: work@carry_rtl (work@carry_rtl), file:${SURELOG_DIR}/tests/CarryTrans/dut.sv, line:1:1, endln:5:10 |vpiName:cout |vpiFullName:work@carry_rtl.cout |vpiPort: \_port: (a), line:1:24, endln:1:25 |vpiParent: - \_module: work@carry_rtl (work@carry_rtl), file:${SURELOG_DIR}/tests/CarryTrans/dut.sv, line:1:1, endln:5:10 + \_module_inst: work@carry_rtl (work@carry_rtl), file:${SURELOG_DIR}/tests/CarryTrans/dut.sv, line:1:1, endln:5:10 |vpiName:a |vpiDirection:1 |vpiLowConn: @@ -1523,7 +1523,7 @@ design: (work@carry_rtl) |vpiPort: \_port: (b), line:1:27, endln:1:28 |vpiParent: - \_module: work@carry_rtl (work@carry_rtl), file:${SURELOG_DIR}/tests/CarryTrans/dut.sv, line:1:1, endln:5:10 + \_module_inst: work@carry_rtl (work@carry_rtl), file:${SURELOG_DIR}/tests/CarryTrans/dut.sv, line:1:1, endln:5:10 |vpiName:b |vpiDirection:1 |vpiLowConn: @@ -1535,7 +1535,7 @@ design: (work@carry_rtl) |vpiPort: \_port: (c), line:1:30, endln:1:31 |vpiParent: - \_module: work@carry_rtl (work@carry_rtl), file:${SURELOG_DIR}/tests/CarryTrans/dut.sv, line:1:1, endln:5:10 + \_module_inst: work@carry_rtl (work@carry_rtl), file:${SURELOG_DIR}/tests/CarryTrans/dut.sv, line:1:1, endln:5:10 |vpiName:c |vpiDirection:1 |vpiLowConn: @@ -1547,7 +1547,7 @@ design: (work@carry_rtl) |vpiPort: \_port: (cout), line:2:11, endln:2:15 |vpiParent: - \_module: work@carry_rtl (work@carry_rtl), file:${SURELOG_DIR}/tests/CarryTrans/dut.sv, line:1:1, endln:5:10 + \_module_inst: work@carry_rtl (work@carry_rtl), file:${SURELOG_DIR}/tests/CarryTrans/dut.sv, line:1:1, endln:5:10 |vpiName:cout |vpiDirection:2 |vpiLowConn: @@ -1559,7 +1559,7 @@ design: (work@carry_rtl) |vpiContAssign: \_cont_assign: , line:3:11, endln:3:39 |vpiParent: - \_module: work@carry_rtl (work@carry_rtl), file:${SURELOG_DIR}/tests/CarryTrans/dut.sv, line:1:1, endln:5:10 + \_module_inst: work@carry_rtl (work@carry_rtl), file:${SURELOG_DIR}/tests/CarryTrans/dut.sv, line:1:1, endln:5:10 |vpiRhs: \_operation: , line:3:18, endln:3:39 |vpiParent: @@ -1642,7 +1642,7 @@ design: (work@carry_rtl) |vpiActual: \_logic_net: (work@carry_rtl.cout), line:2:11, endln:2:15 |uhdmallModules: -\_module: work@carry_trans (work@carry_trans), file:${SURELOG_DIR}/tests/CarryTrans/dut.sv, line:18:1, endln:37:10 +\_module_inst: work@carry_trans (work@carry_trans), file:${SURELOG_DIR}/tests/CarryTrans/dut.sv, line:18:1, endln:37:10 |vpiParent: \_design: (work@carry_rtl) |vpiFullName:work@carry_trans @@ -1650,80 +1650,80 @@ design: (work@carry_rtl) |vpiNet: \_logic_net: (work@carry_trans.a), line:18:26, endln:18:27 |vpiParent: - \_module: work@carry_trans (work@carry_trans), file:${SURELOG_DIR}/tests/CarryTrans/dut.sv, line:18:1, endln:37:10 + \_module_inst: work@carry_trans (work@carry_trans), file:${SURELOG_DIR}/tests/CarryTrans/dut.sv, line:18:1, endln:37:10 |vpiName:a |vpiFullName:work@carry_trans.a |vpiNet: \_logic_net: (work@carry_trans.b), line:18:29, endln:18:30 |vpiParent: - \_module: work@carry_trans (work@carry_trans), file:${SURELOG_DIR}/tests/CarryTrans/dut.sv, line:18:1, endln:37:10 + \_module_inst: work@carry_trans (work@carry_trans), file:${SURELOG_DIR}/tests/CarryTrans/dut.sv, line:18:1, endln:37:10 |vpiName:b |vpiFullName:work@carry_trans.b |vpiNet: \_logic_net: (work@carry_trans.c), line:18:32, endln:18:33 |vpiParent: - \_module: work@carry_trans (work@carry_trans), file:${SURELOG_DIR}/tests/CarryTrans/dut.sv, line:18:1, endln:37:10 + \_module_inst: work@carry_trans (work@carry_trans), file:${SURELOG_DIR}/tests/CarryTrans/dut.sv, line:18:1, endln:37:10 |vpiName:c |vpiFullName:work@carry_trans.c |vpiNet: \_logic_net: (work@carry_trans.cout), line:18:42, endln:18:46 |vpiParent: - \_module: work@carry_trans (work@carry_trans), file:${SURELOG_DIR}/tests/CarryTrans/dut.sv, line:18:1, endln:37:10 + \_module_inst: work@carry_trans (work@carry_trans), file:${SURELOG_DIR}/tests/CarryTrans/dut.sv, line:18:1, endln:37:10 |vpiName:cout |vpiFullName:work@carry_trans.cout |vpiNet: \_logic_net: (work@carry_trans.i1), line:20:6, endln:20:8 |vpiParent: - \_module: work@carry_trans (work@carry_trans), file:${SURELOG_DIR}/tests/CarryTrans/dut.sv, line:18:1, endln:37:10 + \_module_inst: work@carry_trans (work@carry_trans), file:${SURELOG_DIR}/tests/CarryTrans/dut.sv, line:18:1, endln:37:10 |vpiName:i1 |vpiFullName:work@carry_trans.i1 |vpiNetType:1 |vpiNet: \_logic_net: (work@carry_trans.i2), line:20:10, endln:20:12 |vpiParent: - \_module: work@carry_trans (work@carry_trans), file:${SURELOG_DIR}/tests/CarryTrans/dut.sv, line:18:1, endln:37:10 + \_module_inst: work@carry_trans (work@carry_trans), file:${SURELOG_DIR}/tests/CarryTrans/dut.sv, line:18:1, endln:37:10 |vpiName:i2 |vpiFullName:work@carry_trans.i2 |vpiNetType:1 |vpiNet: \_logic_net: (work@carry_trans.i3), line:20:14, endln:20:16 |vpiParent: - \_module: work@carry_trans (work@carry_trans), file:${SURELOG_DIR}/tests/CarryTrans/dut.sv, line:18:1, endln:37:10 + \_module_inst: work@carry_trans (work@carry_trans), file:${SURELOG_DIR}/tests/CarryTrans/dut.sv, line:18:1, endln:37:10 |vpiName:i3 |vpiFullName:work@carry_trans.i3 |vpiNetType:1 |vpiNet: \_logic_net: (work@carry_trans.i4), line:20:18, endln:20:20 |vpiParent: - \_module: work@carry_trans (work@carry_trans), file:${SURELOG_DIR}/tests/CarryTrans/dut.sv, line:18:1, endln:37:10 + \_module_inst: work@carry_trans (work@carry_trans), file:${SURELOG_DIR}/tests/CarryTrans/dut.sv, line:18:1, endln:37:10 |vpiName:i4 |vpiFullName:work@carry_trans.i4 |vpiNetType:1 |vpiNet: \_logic_net: (work@carry_trans.cn), line:20:22, endln:20:24 |vpiParent: - \_module: work@carry_trans (work@carry_trans), file:${SURELOG_DIR}/tests/CarryTrans/dut.sv, line:18:1, endln:37:10 + \_module_inst: work@carry_trans (work@carry_trans), file:${SURELOG_DIR}/tests/CarryTrans/dut.sv, line:18:1, endln:37:10 |vpiName:cn |vpiFullName:work@carry_trans.cn |vpiNetType:1 |vpiNet: \_logic_net: (work@carry_trans.zero), line:22:6, endln:22:10 |vpiParent: - \_module: work@carry_trans (work@carry_trans), file:${SURELOG_DIR}/tests/CarryTrans/dut.sv, line:18:1, endln:37:10 + \_module_inst: work@carry_trans (work@carry_trans), file:${SURELOG_DIR}/tests/CarryTrans/dut.sv, line:18:1, endln:37:10 |vpiName:zero |vpiFullName:work@carry_trans.zero |vpiNetType:1 |vpiNet: \_logic_net: (work@carry_trans.one), line:23:6, endln:23:9 |vpiParent: - \_module: work@carry_trans (work@carry_trans), file:${SURELOG_DIR}/tests/CarryTrans/dut.sv, line:18:1, endln:37:10 + \_module_inst: work@carry_trans (work@carry_trans), file:${SURELOG_DIR}/tests/CarryTrans/dut.sv, line:18:1, endln:37:10 |vpiName:one |vpiFullName:work@carry_trans.one |vpiNetType:1 |vpiPort: \_port: (a), line:18:26, endln:18:27 |vpiParent: - \_module: work@carry_trans (work@carry_trans), file:${SURELOG_DIR}/tests/CarryTrans/dut.sv, line:18:1, endln:37:10 + \_module_inst: work@carry_trans (work@carry_trans), file:${SURELOG_DIR}/tests/CarryTrans/dut.sv, line:18:1, endln:37:10 |vpiName:a |vpiDirection:1 |vpiLowConn: @@ -1735,7 +1735,7 @@ design: (work@carry_rtl) |vpiPort: \_port: (b), line:18:29, endln:18:30 |vpiParent: - \_module: work@carry_trans (work@carry_trans), file:${SURELOG_DIR}/tests/CarryTrans/dut.sv, line:18:1, endln:37:10 + \_module_inst: work@carry_trans (work@carry_trans), file:${SURELOG_DIR}/tests/CarryTrans/dut.sv, line:18:1, endln:37:10 |vpiName:b |vpiDirection:1 |vpiLowConn: @@ -1747,7 +1747,7 @@ design: (work@carry_rtl) |vpiPort: \_port: (c), line:18:32, endln:18:33 |vpiParent: - \_module: work@carry_trans (work@carry_trans), file:${SURELOG_DIR}/tests/CarryTrans/dut.sv, line:18:1, endln:37:10 + \_module_inst: work@carry_trans (work@carry_trans), file:${SURELOG_DIR}/tests/CarryTrans/dut.sv, line:18:1, endln:37:10 |vpiName:c |vpiDirection:1 |vpiLowConn: @@ -1759,7 +1759,7 @@ design: (work@carry_rtl) |vpiPort: \_port: (cout), line:18:42, endln:18:46 |vpiParent: - \_module: work@carry_trans (work@carry_trans), file:${SURELOG_DIR}/tests/CarryTrans/dut.sv, line:18:1, endln:37:10 + \_module_inst: work@carry_trans (work@carry_trans), file:${SURELOG_DIR}/tests/CarryTrans/dut.sv, line:18:1, endln:37:10 |vpiName:cout |vpiDirection:2 |vpiLowConn: @@ -1769,14 +1769,14 @@ design: (work@carry_rtl) |vpiTypedef: \_logic_typespec: , line:18:42, endln:18:42 |uhdmtopModules: -\_module: work@carry_rtl (work@carry_rtl), file:${SURELOG_DIR}/tests/CarryTrans/dut.sv, line:1:1, endln:5:10 +\_module_inst: work@carry_rtl (work@carry_rtl), file:${SURELOG_DIR}/tests/CarryTrans/dut.sv, line:1:1, endln:5:10 |vpiName:work@carry_rtl |vpiDefName:work@carry_rtl |vpiTop:1 |vpiNet: \_logic_net: (work@carry_rtl.a), line:1:24, endln:1:25 |vpiParent: - \_module: work@carry_rtl (work@carry_rtl), file:${SURELOG_DIR}/tests/CarryTrans/dut.sv, line:1:1, endln:5:10 + \_module_inst: work@carry_rtl (work@carry_rtl), file:${SURELOG_DIR}/tests/CarryTrans/dut.sv, line:1:1, endln:5:10 |vpiTypespec: \_logic_typespec: , line:1:24, endln:1:24 |vpiName:a @@ -1784,7 +1784,7 @@ design: (work@carry_rtl) |vpiNet: \_logic_net: (work@carry_rtl.b), line:1:27, endln:1:28 |vpiParent: - \_module: work@carry_rtl (work@carry_rtl), file:${SURELOG_DIR}/tests/CarryTrans/dut.sv, line:1:1, endln:5:10 + \_module_inst: work@carry_rtl (work@carry_rtl), file:${SURELOG_DIR}/tests/CarryTrans/dut.sv, line:1:1, endln:5:10 |vpiTypespec: \_logic_typespec: , line:1:24, endln:1:24 |vpiName:b @@ -1792,7 +1792,7 @@ design: (work@carry_rtl) |vpiNet: \_logic_net: (work@carry_rtl.c), line:1:30, endln:1:31 |vpiParent: - \_module: work@carry_rtl (work@carry_rtl), file:${SURELOG_DIR}/tests/CarryTrans/dut.sv, line:1:1, endln:5:10 + \_module_inst: work@carry_rtl (work@carry_rtl), file:${SURELOG_DIR}/tests/CarryTrans/dut.sv, line:1:1, endln:5:10 |vpiTypespec: \_logic_typespec: , line:1:24, endln:1:24 |vpiName:c @@ -1800,7 +1800,7 @@ design: (work@carry_rtl) |vpiNet: \_logic_net: (work@carry_rtl.cout), line:2:11, endln:2:15 |vpiParent: - \_module: work@carry_rtl (work@carry_rtl), file:${SURELOG_DIR}/tests/CarryTrans/dut.sv, line:1:1, endln:5:10 + \_module_inst: work@carry_rtl (work@carry_rtl), file:${SURELOG_DIR}/tests/CarryTrans/dut.sv, line:1:1, endln:5:10 |vpiTypespec: \_logic_typespec: , line:2:11, endln:2:11 |vpiName:cout @@ -1809,7 +1809,7 @@ design: (work@carry_rtl) |vpiPort: \_port: (a), line:1:24, endln:1:25 |vpiParent: - \_module: work@carry_rtl (work@carry_rtl), file:${SURELOG_DIR}/tests/CarryTrans/dut.sv, line:1:1, endln:5:10 + \_module_inst: work@carry_rtl (work@carry_rtl), file:${SURELOG_DIR}/tests/CarryTrans/dut.sv, line:1:1, endln:5:10 |vpiName:a |vpiDirection:1 |vpiLowConn: @@ -1823,11 +1823,11 @@ design: (work@carry_rtl) |vpiTypedef: \_logic_typespec: , line:1:24, endln:1:24 |vpiInstance: - \_module: work@carry_rtl (work@carry_rtl), file:${SURELOG_DIR}/tests/CarryTrans/dut.sv, line:1:1, endln:5:10 + \_module_inst: work@carry_rtl (work@carry_rtl), file:${SURELOG_DIR}/tests/CarryTrans/dut.sv, line:1:1, endln:5:10 |vpiPort: \_port: (b), line:1:27, endln:1:28 |vpiParent: - \_module: work@carry_rtl (work@carry_rtl), file:${SURELOG_DIR}/tests/CarryTrans/dut.sv, line:1:1, endln:5:10 + \_module_inst: work@carry_rtl (work@carry_rtl), file:${SURELOG_DIR}/tests/CarryTrans/dut.sv, line:1:1, endln:5:10 |vpiName:b |vpiDirection:1 |vpiLowConn: @@ -1841,11 +1841,11 @@ design: (work@carry_rtl) |vpiTypedef: \_logic_typespec: , line:1:24, endln:1:24 |vpiInstance: - \_module: work@carry_rtl (work@carry_rtl), file:${SURELOG_DIR}/tests/CarryTrans/dut.sv, line:1:1, endln:5:10 + \_module_inst: work@carry_rtl (work@carry_rtl), file:${SURELOG_DIR}/tests/CarryTrans/dut.sv, line:1:1, endln:5:10 |vpiPort: \_port: (c), line:1:30, endln:1:31 |vpiParent: - \_module: work@carry_rtl (work@carry_rtl), file:${SURELOG_DIR}/tests/CarryTrans/dut.sv, line:1:1, endln:5:10 + \_module_inst: work@carry_rtl (work@carry_rtl), file:${SURELOG_DIR}/tests/CarryTrans/dut.sv, line:1:1, endln:5:10 |vpiName:c |vpiDirection:1 |vpiLowConn: @@ -1859,11 +1859,11 @@ design: (work@carry_rtl) |vpiTypedef: \_logic_typespec: , line:1:24, endln:1:24 |vpiInstance: - \_module: work@carry_rtl (work@carry_rtl), file:${SURELOG_DIR}/tests/CarryTrans/dut.sv, line:1:1, endln:5:10 + \_module_inst: work@carry_rtl (work@carry_rtl), file:${SURELOG_DIR}/tests/CarryTrans/dut.sv, line:1:1, endln:5:10 |vpiPort: \_port: (cout), line:2:11, endln:2:15 |vpiParent: - \_module: work@carry_rtl (work@carry_rtl), file:${SURELOG_DIR}/tests/CarryTrans/dut.sv, line:1:1, endln:5:10 + \_module_inst: work@carry_rtl (work@carry_rtl), file:${SURELOG_DIR}/tests/CarryTrans/dut.sv, line:1:1, endln:5:10 |vpiName:cout |vpiDirection:2 |vpiLowConn: @@ -1877,11 +1877,11 @@ design: (work@carry_rtl) |vpiTypedef: \_logic_typespec: , line:2:11, endln:2:11 |vpiInstance: - \_module: work@carry_rtl (work@carry_rtl), file:${SURELOG_DIR}/tests/CarryTrans/dut.sv, line:1:1, endln:5:10 + \_module_inst: work@carry_rtl (work@carry_rtl), file:${SURELOG_DIR}/tests/CarryTrans/dut.sv, line:1:1, endln:5:10 |vpiContAssign: \_cont_assign: , line:3:11, endln:3:39 |vpiParent: - \_module: work@carry_rtl (work@carry_rtl), file:${SURELOG_DIR}/tests/CarryTrans/dut.sv, line:1:1, endln:5:10 + \_module_inst: work@carry_rtl (work@carry_rtl), file:${SURELOG_DIR}/tests/CarryTrans/dut.sv, line:1:1, endln:5:10 |vpiRhs: \_operation: , line:3:18, endln:3:39 |vpiParent: @@ -1964,14 +1964,14 @@ design: (work@carry_rtl) |vpiActual: \_logic_net: (work@carry_rtl.cout), line:2:11, endln:2:15 |uhdmtopModules: -\_module: work@carry_gate (work@carry_gate), file:${SURELOG_DIR}/tests/CarryTrans/dut.sv, line:8:1, endln:16:10 +\_module_inst: work@carry_gate (work@carry_gate), file:${SURELOG_DIR}/tests/CarryTrans/dut.sv, line:8:1, endln:16:10 |vpiName:work@carry_gate |vpiDefName:work@carry_gate |vpiTop:1 |vpiNet: \_logic_net: (work@carry_gate.a), line:8:25, endln:8:26 |vpiParent: - \_module: work@carry_gate (work@carry_gate), file:${SURELOG_DIR}/tests/CarryTrans/dut.sv, line:8:1, endln:16:10 + \_module_inst: work@carry_gate (work@carry_gate), file:${SURELOG_DIR}/tests/CarryTrans/dut.sv, line:8:1, endln:16:10 |vpiTypespec: \_logic_typespec: , line:8:25, endln:8:25 |vpiName:a @@ -1979,7 +1979,7 @@ design: (work@carry_rtl) |vpiNet: \_logic_net: (work@carry_gate.b), line:8:28, endln:8:29 |vpiParent: - \_module: work@carry_gate (work@carry_gate), file:${SURELOG_DIR}/tests/CarryTrans/dut.sv, line:8:1, endln:16:10 + \_module_inst: work@carry_gate (work@carry_gate), file:${SURELOG_DIR}/tests/CarryTrans/dut.sv, line:8:1, endln:16:10 |vpiTypespec: \_logic_typespec: , line:8:25, endln:8:25 |vpiName:b @@ -1987,7 +1987,7 @@ design: (work@carry_rtl) |vpiNet: \_logic_net: (work@carry_gate.c), line:8:31, endln:8:32 |vpiParent: - \_module: work@carry_gate (work@carry_gate), file:${SURELOG_DIR}/tests/CarryTrans/dut.sv, line:8:1, endln:16:10 + \_module_inst: work@carry_gate (work@carry_gate), file:${SURELOG_DIR}/tests/CarryTrans/dut.sv, line:8:1, endln:16:10 |vpiTypespec: \_logic_typespec: , line:8:25, endln:8:25 |vpiName:c @@ -1995,7 +1995,7 @@ design: (work@carry_rtl) |vpiNet: \_logic_net: (work@carry_gate.cout), line:9:12, endln:9:16 |vpiParent: - \_module: work@carry_gate (work@carry_gate), file:${SURELOG_DIR}/tests/CarryTrans/dut.sv, line:8:1, endln:16:10 + \_module_inst: work@carry_gate (work@carry_gate), file:${SURELOG_DIR}/tests/CarryTrans/dut.sv, line:8:1, endln:16:10 |vpiTypespec: \_logic_typespec: , line:9:12, endln:9:12 |vpiName:cout @@ -2003,7 +2003,7 @@ design: (work@carry_rtl) |vpiNet: \_logic_net: (work@carry_gate.x), line:11:6, endln:11:7 |vpiParent: - \_module: work@carry_gate (work@carry_gate), file:${SURELOG_DIR}/tests/CarryTrans/dut.sv, line:8:1, endln:16:10 + \_module_inst: work@carry_gate (work@carry_gate), file:${SURELOG_DIR}/tests/CarryTrans/dut.sv, line:8:1, endln:16:10 |vpiTypespec: \_logic_typespec: , line:11:1, endln:11:5 |vpiName:x @@ -2012,7 +2012,7 @@ design: (work@carry_rtl) |vpiNet: \_logic_net: (work@carry_gate.y), line:11:9, endln:11:10 |vpiParent: - \_module: work@carry_gate (work@carry_gate), file:${SURELOG_DIR}/tests/CarryTrans/dut.sv, line:8:1, endln:16:10 + \_module_inst: work@carry_gate (work@carry_gate), file:${SURELOG_DIR}/tests/CarryTrans/dut.sv, line:8:1, endln:16:10 |vpiTypespec: \_logic_typespec: , line:11:1, endln:11:5 |vpiName:y @@ -2021,7 +2021,7 @@ design: (work@carry_rtl) |vpiNet: \_logic_net: (work@carry_gate.z), line:11:12, endln:11:13 |vpiParent: - \_module: work@carry_gate (work@carry_gate), file:${SURELOG_DIR}/tests/CarryTrans/dut.sv, line:8:1, endln:16:10 + \_module_inst: work@carry_gate (work@carry_gate), file:${SURELOG_DIR}/tests/CarryTrans/dut.sv, line:8:1, endln:16:10 |vpiTypespec: \_logic_typespec: , line:11:1, endln:11:5 |vpiName:z @@ -2031,7 +2031,7 @@ design: (work@carry_rtl) |vpiPort: \_port: (a), line:8:25, endln:8:26 |vpiParent: - \_module: work@carry_gate (work@carry_gate), file:${SURELOG_DIR}/tests/CarryTrans/dut.sv, line:8:1, endln:16:10 + \_module_inst: work@carry_gate (work@carry_gate), file:${SURELOG_DIR}/tests/CarryTrans/dut.sv, line:8:1, endln:16:10 |vpiName:a |vpiDirection:1 |vpiLowConn: @@ -2045,11 +2045,11 @@ design: (work@carry_rtl) |vpiTypedef: \_logic_typespec: , line:8:25, endln:8:25 |vpiInstance: - \_module: work@carry_gate (work@carry_gate), file:${SURELOG_DIR}/tests/CarryTrans/dut.sv, line:8:1, endln:16:10 + \_module_inst: work@carry_gate (work@carry_gate), file:${SURELOG_DIR}/tests/CarryTrans/dut.sv, line:8:1, endln:16:10 |vpiPort: \_port: (b), line:8:28, endln:8:29 |vpiParent: - \_module: work@carry_gate (work@carry_gate), file:${SURELOG_DIR}/tests/CarryTrans/dut.sv, line:8:1, endln:16:10 + \_module_inst: work@carry_gate (work@carry_gate), file:${SURELOG_DIR}/tests/CarryTrans/dut.sv, line:8:1, endln:16:10 |vpiName:b |vpiDirection:1 |vpiLowConn: @@ -2063,11 +2063,11 @@ design: (work@carry_rtl) |vpiTypedef: \_logic_typespec: , line:8:25, endln:8:25 |vpiInstance: - \_module: work@carry_gate (work@carry_gate), file:${SURELOG_DIR}/tests/CarryTrans/dut.sv, line:8:1, endln:16:10 + \_module_inst: work@carry_gate (work@carry_gate), file:${SURELOG_DIR}/tests/CarryTrans/dut.sv, line:8:1, endln:16:10 |vpiPort: \_port: (c), line:8:31, endln:8:32 |vpiParent: - \_module: work@carry_gate (work@carry_gate), file:${SURELOG_DIR}/tests/CarryTrans/dut.sv, line:8:1, endln:16:10 + \_module_inst: work@carry_gate (work@carry_gate), file:${SURELOG_DIR}/tests/CarryTrans/dut.sv, line:8:1, endln:16:10 |vpiName:c |vpiDirection:1 |vpiLowConn: @@ -2081,11 +2081,11 @@ design: (work@carry_rtl) |vpiTypedef: \_logic_typespec: , line:8:25, endln:8:25 |vpiInstance: - \_module: work@carry_gate (work@carry_gate), file:${SURELOG_DIR}/tests/CarryTrans/dut.sv, line:8:1, endln:16:10 + \_module_inst: work@carry_gate (work@carry_gate), file:${SURELOG_DIR}/tests/CarryTrans/dut.sv, line:8:1, endln:16:10 |vpiPort: \_port: (cout), line:9:12, endln:9:16 |vpiParent: - \_module: work@carry_gate (work@carry_gate), file:${SURELOG_DIR}/tests/CarryTrans/dut.sv, line:8:1, endln:16:10 + \_module_inst: work@carry_gate (work@carry_gate), file:${SURELOG_DIR}/tests/CarryTrans/dut.sv, line:8:1, endln:16:10 |vpiName:cout |vpiDirection:2 |vpiLowConn: @@ -2099,11 +2099,11 @@ design: (work@carry_rtl) |vpiTypedef: \_logic_typespec: , line:9:12, endln:9:12 |vpiInstance: - \_module: work@carry_gate (work@carry_gate), file:${SURELOG_DIR}/tests/CarryTrans/dut.sv, line:8:1, endln:16:10 + \_module_inst: work@carry_gate (work@carry_gate), file:${SURELOG_DIR}/tests/CarryTrans/dut.sv, line:8:1, endln:16:10 |vpiPrimitive: \_gate: work@and (work@carry_gate.g1), line:12:5, endln:12:16 |vpiParent: - \_module: work@carry_gate (work@carry_gate), file:${SURELOG_DIR}/tests/CarryTrans/dut.sv, line:8:1, endln:16:10 + \_module_inst: work@carry_gate (work@carry_gate), file:${SURELOG_DIR}/tests/CarryTrans/dut.sv, line:8:1, endln:16:10 |vpiDefName:work@and |vpiName:g1 |vpiFullName:work@carry_gate.g1 @@ -2152,7 +2152,7 @@ design: (work@carry_rtl) |vpiPrimitive: \_gate: work@and (work@carry_gate.g2), line:13:5, endln:13:16 |vpiParent: - \_module: work@carry_gate (work@carry_gate), file:${SURELOG_DIR}/tests/CarryTrans/dut.sv, line:8:1, endln:16:10 + \_module_inst: work@carry_gate (work@carry_gate), file:${SURELOG_DIR}/tests/CarryTrans/dut.sv, line:8:1, endln:16:10 |vpiDefName:work@and |vpiName:g2 |vpiFullName:work@carry_gate.g2 @@ -2201,7 +2201,7 @@ design: (work@carry_rtl) |vpiPrimitive: \_gate: work@and (work@carry_gate.g3), line:14:5, endln:14:16 |vpiParent: - \_module: work@carry_gate (work@carry_gate), file:${SURELOG_DIR}/tests/CarryTrans/dut.sv, line:8:1, endln:16:10 + \_module_inst: work@carry_gate (work@carry_gate), file:${SURELOG_DIR}/tests/CarryTrans/dut.sv, line:8:1, endln:16:10 |vpiDefName:work@and |vpiName:g3 |vpiFullName:work@carry_gate.g3 @@ -2250,7 +2250,7 @@ design: (work@carry_rtl) |vpiPrimitive: \_gate: work@or (work@carry_gate.g4), line:15:4, endln:15:21 |vpiParent: - \_module: work@carry_gate (work@carry_gate), file:${SURELOG_DIR}/tests/CarryTrans/dut.sv, line:8:1, endln:16:10 + \_module_inst: work@carry_gate (work@carry_gate), file:${SURELOG_DIR}/tests/CarryTrans/dut.sv, line:8:1, endln:16:10 |vpiDefName:work@or |vpiName:g4 |vpiFullName:work@carry_gate.g4 @@ -2311,14 +2311,14 @@ design: (work@carry_rtl) |vpiActual: \_logic_net: (work@carry_gate.z), line:11:12, endln:11:13 |uhdmtopModules: -\_module: work@carry_trans (work@carry_trans), file:${SURELOG_DIR}/tests/CarryTrans/dut.sv, line:18:1, endln:37:10 +\_module_inst: work@carry_trans (work@carry_trans), file:${SURELOG_DIR}/tests/CarryTrans/dut.sv, line:18:1, endln:37:10 |vpiName:work@carry_trans |vpiDefName:work@carry_trans |vpiTop:1 |vpiNet: \_logic_net: (work@carry_trans.a), line:18:26, endln:18:27 |vpiParent: - \_module: work@carry_trans (work@carry_trans), file:${SURELOG_DIR}/tests/CarryTrans/dut.sv, line:18:1, endln:37:10 + \_module_inst: work@carry_trans (work@carry_trans), file:${SURELOG_DIR}/tests/CarryTrans/dut.sv, line:18:1, endln:37:10 |vpiTypespec: \_logic_typespec: , line:18:26, endln:18:26 |vpiName:a @@ -2326,7 +2326,7 @@ design: (work@carry_rtl) |vpiNet: \_logic_net: (work@carry_trans.b), line:18:29, endln:18:30 |vpiParent: - \_module: work@carry_trans (work@carry_trans), file:${SURELOG_DIR}/tests/CarryTrans/dut.sv, line:18:1, endln:37:10 + \_module_inst: work@carry_trans (work@carry_trans), file:${SURELOG_DIR}/tests/CarryTrans/dut.sv, line:18:1, endln:37:10 |vpiTypespec: \_logic_typespec: , line:18:26, endln:18:26 |vpiName:b @@ -2334,7 +2334,7 @@ design: (work@carry_rtl) |vpiNet: \_logic_net: (work@carry_trans.c), line:18:32, endln:18:33 |vpiParent: - \_module: work@carry_trans (work@carry_trans), file:${SURELOG_DIR}/tests/CarryTrans/dut.sv, line:18:1, endln:37:10 + \_module_inst: work@carry_trans (work@carry_trans), file:${SURELOG_DIR}/tests/CarryTrans/dut.sv, line:18:1, endln:37:10 |vpiTypespec: \_logic_typespec: , line:18:26, endln:18:26 |vpiName:c @@ -2342,7 +2342,7 @@ design: (work@carry_rtl) |vpiNet: \_logic_net: (work@carry_trans.cout), line:18:42, endln:18:46 |vpiParent: - \_module: work@carry_trans (work@carry_trans), file:${SURELOG_DIR}/tests/CarryTrans/dut.sv, line:18:1, endln:37:10 + \_module_inst: work@carry_trans (work@carry_trans), file:${SURELOG_DIR}/tests/CarryTrans/dut.sv, line:18:1, endln:37:10 |vpiTypespec: \_logic_typespec: , line:18:42, endln:18:42 |vpiName:cout @@ -2350,7 +2350,7 @@ design: (work@carry_rtl) |vpiNet: \_logic_net: (work@carry_trans.i1), line:20:6, endln:20:8 |vpiParent: - \_module: work@carry_trans (work@carry_trans), file:${SURELOG_DIR}/tests/CarryTrans/dut.sv, line:18:1, endln:37:10 + \_module_inst: work@carry_trans (work@carry_trans), file:${SURELOG_DIR}/tests/CarryTrans/dut.sv, line:18:1, endln:37:10 |vpiTypespec: \_logic_typespec: , line:20:1, endln:20:5 |vpiName:i1 @@ -2359,7 +2359,7 @@ design: (work@carry_rtl) |vpiNet: \_logic_net: (work@carry_trans.i2), line:20:10, endln:20:12 |vpiParent: - \_module: work@carry_trans (work@carry_trans), file:${SURELOG_DIR}/tests/CarryTrans/dut.sv, line:18:1, endln:37:10 + \_module_inst: work@carry_trans (work@carry_trans), file:${SURELOG_DIR}/tests/CarryTrans/dut.sv, line:18:1, endln:37:10 |vpiTypespec: \_logic_typespec: , line:20:1, endln:20:5 |vpiName:i2 @@ -2368,7 +2368,7 @@ design: (work@carry_rtl) |vpiNet: \_logic_net: (work@carry_trans.i3), line:20:14, endln:20:16 |vpiParent: - \_module: work@carry_trans (work@carry_trans), file:${SURELOG_DIR}/tests/CarryTrans/dut.sv, line:18:1, endln:37:10 + \_module_inst: work@carry_trans (work@carry_trans), file:${SURELOG_DIR}/tests/CarryTrans/dut.sv, line:18:1, endln:37:10 |vpiTypespec: \_logic_typespec: , line:20:1, endln:20:5 |vpiName:i3 @@ -2377,7 +2377,7 @@ design: (work@carry_rtl) |vpiNet: \_logic_net: (work@carry_trans.i4), line:20:18, endln:20:20 |vpiParent: - \_module: work@carry_trans (work@carry_trans), file:${SURELOG_DIR}/tests/CarryTrans/dut.sv, line:18:1, endln:37:10 + \_module_inst: work@carry_trans (work@carry_trans), file:${SURELOG_DIR}/tests/CarryTrans/dut.sv, line:18:1, endln:37:10 |vpiTypespec: \_logic_typespec: , line:20:1, endln:20:5 |vpiName:i4 @@ -2386,7 +2386,7 @@ design: (work@carry_rtl) |vpiNet: \_logic_net: (work@carry_trans.cn), line:20:22, endln:20:24 |vpiParent: - \_module: work@carry_trans (work@carry_trans), file:${SURELOG_DIR}/tests/CarryTrans/dut.sv, line:18:1, endln:37:10 + \_module_inst: work@carry_trans (work@carry_trans), file:${SURELOG_DIR}/tests/CarryTrans/dut.sv, line:18:1, endln:37:10 |vpiTypespec: \_logic_typespec: , line:20:1, endln:20:5 |vpiName:cn @@ -2395,7 +2395,7 @@ design: (work@carry_rtl) |vpiNet: \_logic_net: (work@carry_trans.zero), line:22:6, endln:22:10 |vpiParent: - \_module: work@carry_trans (work@carry_trans), file:${SURELOG_DIR}/tests/CarryTrans/dut.sv, line:18:1, endln:37:10 + \_module_inst: work@carry_trans (work@carry_trans), file:${SURELOG_DIR}/tests/CarryTrans/dut.sv, line:18:1, endln:37:10 |vpiTypespec: \_logic_typespec: , line:22:1, endln:22:5 |vpiName:zero @@ -2404,7 +2404,7 @@ design: (work@carry_rtl) |vpiNet: \_logic_net: (work@carry_trans.one), line:23:6, endln:23:9 |vpiParent: - \_module: work@carry_trans (work@carry_trans), file:${SURELOG_DIR}/tests/CarryTrans/dut.sv, line:18:1, endln:37:10 + \_module_inst: work@carry_trans (work@carry_trans), file:${SURELOG_DIR}/tests/CarryTrans/dut.sv, line:18:1, endln:37:10 |vpiTypespec: \_logic_typespec: , line:23:1, endln:23:5 |vpiName:one @@ -2414,7 +2414,7 @@ design: (work@carry_rtl) |vpiPort: \_port: (a), line:18:26, endln:18:27 |vpiParent: - \_module: work@carry_trans (work@carry_trans), file:${SURELOG_DIR}/tests/CarryTrans/dut.sv, line:18:1, endln:37:10 + \_module_inst: work@carry_trans (work@carry_trans), file:${SURELOG_DIR}/tests/CarryTrans/dut.sv, line:18:1, endln:37:10 |vpiName:a |vpiDirection:1 |vpiLowConn: @@ -2428,11 +2428,11 @@ design: (work@carry_rtl) |vpiTypedef: \_logic_typespec: , line:18:26, endln:18:26 |vpiInstance: - \_module: work@carry_trans (work@carry_trans), file:${SURELOG_DIR}/tests/CarryTrans/dut.sv, line:18:1, endln:37:10 + \_module_inst: work@carry_trans (work@carry_trans), file:${SURELOG_DIR}/tests/CarryTrans/dut.sv, line:18:1, endln:37:10 |vpiPort: \_port: (b), line:18:29, endln:18:30 |vpiParent: - \_module: work@carry_trans (work@carry_trans), file:${SURELOG_DIR}/tests/CarryTrans/dut.sv, line:18:1, endln:37:10 + \_module_inst: work@carry_trans (work@carry_trans), file:${SURELOG_DIR}/tests/CarryTrans/dut.sv, line:18:1, endln:37:10 |vpiName:b |vpiDirection:1 |vpiLowConn: @@ -2446,11 +2446,11 @@ design: (work@carry_rtl) |vpiTypedef: \_logic_typespec: , line:18:26, endln:18:26 |vpiInstance: - \_module: work@carry_trans (work@carry_trans), file:${SURELOG_DIR}/tests/CarryTrans/dut.sv, line:18:1, endln:37:10 + \_module_inst: work@carry_trans (work@carry_trans), file:${SURELOG_DIR}/tests/CarryTrans/dut.sv, line:18:1, endln:37:10 |vpiPort: \_port: (c), line:18:32, endln:18:33 |vpiParent: - \_module: work@carry_trans (work@carry_trans), file:${SURELOG_DIR}/tests/CarryTrans/dut.sv, line:18:1, endln:37:10 + \_module_inst: work@carry_trans (work@carry_trans), file:${SURELOG_DIR}/tests/CarryTrans/dut.sv, line:18:1, endln:37:10 |vpiName:c |vpiDirection:1 |vpiLowConn: @@ -2464,11 +2464,11 @@ design: (work@carry_rtl) |vpiTypedef: \_logic_typespec: , line:18:26, endln:18:26 |vpiInstance: - \_module: work@carry_trans (work@carry_trans), file:${SURELOG_DIR}/tests/CarryTrans/dut.sv, line:18:1, endln:37:10 + \_module_inst: work@carry_trans (work@carry_trans), file:${SURELOG_DIR}/tests/CarryTrans/dut.sv, line:18:1, endln:37:10 |vpiPort: \_port: (cout), line:18:42, endln:18:46 |vpiParent: - \_module: work@carry_trans (work@carry_trans), file:${SURELOG_DIR}/tests/CarryTrans/dut.sv, line:18:1, endln:37:10 + \_module_inst: work@carry_trans (work@carry_trans), file:${SURELOG_DIR}/tests/CarryTrans/dut.sv, line:18:1, endln:37:10 |vpiName:cout |vpiDirection:2 |vpiLowConn: @@ -2482,11 +2482,11 @@ design: (work@carry_rtl) |vpiTypedef: \_logic_typespec: , line:18:42, endln:18:42 |vpiInstance: - \_module: work@carry_trans (work@carry_trans), file:${SURELOG_DIR}/tests/CarryTrans/dut.sv, line:18:1, endln:37:10 + \_module_inst: work@carry_trans (work@carry_trans), file:${SURELOG_DIR}/tests/CarryTrans/dut.sv, line:18:1, endln:37:10 |vpiContAssign: \_cont_assign: , line:22:6, endln:22:10 |vpiParent: - \_module: work@carry_trans (work@carry_trans), file:${SURELOG_DIR}/tests/CarryTrans/dut.sv, line:18:1, endln:37:10 + \_module_inst: work@carry_trans (work@carry_trans), file:${SURELOG_DIR}/tests/CarryTrans/dut.sv, line:18:1, endln:37:10 |vpiNetDeclAssign:1 |vpiRhs: \_constant: , line:22:13, endln:22:17 @@ -2501,7 +2501,7 @@ design: (work@carry_rtl) |vpiContAssign: \_cont_assign: , line:23:6, endln:23:9 |vpiParent: - \_module: work@carry_trans (work@carry_trans), file:${SURELOG_DIR}/tests/CarryTrans/dut.sv, line:18:1, endln:37:10 + \_module_inst: work@carry_trans (work@carry_trans), file:${SURELOG_DIR}/tests/CarryTrans/dut.sv, line:18:1, endln:37:10 |vpiNetDeclAssign:1 |vpiRhs: \_constant: , line:23:12, endln:23:16 @@ -2516,7 +2516,7 @@ design: (work@carry_rtl) |vpiPrimitive: \_switch_tran: work@tranif1 (work@carry_trans.n1), line:25:9, endln:25:23 |vpiParent: - \_module: work@carry_trans (work@carry_trans), file:${SURELOG_DIR}/tests/CarryTrans/dut.sv, line:18:1, endln:37:10 + \_module_inst: work@carry_trans (work@carry_trans), file:${SURELOG_DIR}/tests/CarryTrans/dut.sv, line:18:1, endln:37:10 |vpiDefName:work@tranif1 |vpiName:n1 |vpiFullName:work@carry_trans.n1 @@ -2565,7 +2565,7 @@ design: (work@carry_rtl) |vpiPrimitive: \_switch_tran: work@tranif1 (work@carry_trans.n2), line:26:9, endln:26:24 |vpiParent: - \_module: work@carry_trans (work@carry_trans), file:${SURELOG_DIR}/tests/CarryTrans/dut.sv, line:18:1, endln:37:10 + \_module_inst: work@carry_trans (work@carry_trans), file:${SURELOG_DIR}/tests/CarryTrans/dut.sv, line:18:1, endln:37:10 |vpiDefName:work@tranif1 |vpiName:n2 |vpiFullName:work@carry_trans.n2 @@ -2614,7 +2614,7 @@ design: (work@carry_rtl) |vpiPrimitive: \_switch_tran: work@tranif1 (work@carry_trans.n3), line:27:9, endln:27:22 |vpiParent: - \_module: work@carry_trans (work@carry_trans), file:${SURELOG_DIR}/tests/CarryTrans/dut.sv, line:18:1, endln:37:10 + \_module_inst: work@carry_trans (work@carry_trans), file:${SURELOG_DIR}/tests/CarryTrans/dut.sv, line:18:1, endln:37:10 |vpiDefName:work@tranif1 |vpiName:n3 |vpiFullName:work@carry_trans.n3 @@ -2663,7 +2663,7 @@ design: (work@carry_rtl) |vpiPrimitive: \_switch_tran: work@tranif1 (work@carry_trans.n4), line:28:9, endln:28:24 |vpiParent: - \_module: work@carry_trans (work@carry_trans), file:${SURELOG_DIR}/tests/CarryTrans/dut.sv, line:18:1, endln:37:10 + \_module_inst: work@carry_trans (work@carry_trans), file:${SURELOG_DIR}/tests/CarryTrans/dut.sv, line:18:1, endln:37:10 |vpiDefName:work@tranif1 |vpiName:n4 |vpiFullName:work@carry_trans.n4 @@ -2712,7 +2712,7 @@ design: (work@carry_rtl) |vpiPrimitive: \_switch_tran: work@tranif1 (work@carry_trans.n5), line:29:9, endln:29:22 |vpiParent: - \_module: work@carry_trans (work@carry_trans), file:${SURELOG_DIR}/tests/CarryTrans/dut.sv, line:18:1, endln:37:10 + \_module_inst: work@carry_trans (work@carry_trans), file:${SURELOG_DIR}/tests/CarryTrans/dut.sv, line:18:1, endln:37:10 |vpiDefName:work@tranif1 |vpiName:n5 |vpiFullName:work@carry_trans.n5 @@ -2761,7 +2761,7 @@ design: (work@carry_rtl) |vpiPrimitive: \_switch_tran: work@tranif0 (work@carry_trans.p1), line:30:9, endln:30:23 |vpiParent: - \_module: work@carry_trans (work@carry_trans), file:${SURELOG_DIR}/tests/CarryTrans/dut.sv, line:18:1, endln:37:10 + \_module_inst: work@carry_trans (work@carry_trans), file:${SURELOG_DIR}/tests/CarryTrans/dut.sv, line:18:1, endln:37:10 |vpiDefName:work@tranif0 |vpiName:p1 |vpiFullName:work@carry_trans.p1 @@ -2810,7 +2810,7 @@ design: (work@carry_rtl) |vpiPrimitive: \_switch_tran: work@tranif0 (work@carry_trans.p2), line:31:9, endln:31:23 |vpiParent: - \_module: work@carry_trans (work@carry_trans), file:${SURELOG_DIR}/tests/CarryTrans/dut.sv, line:18:1, endln:37:10 + \_module_inst: work@carry_trans (work@carry_trans), file:${SURELOG_DIR}/tests/CarryTrans/dut.sv, line:18:1, endln:37:10 |vpiDefName:work@tranif0 |vpiName:p2 |vpiFullName:work@carry_trans.p2 @@ -2859,7 +2859,7 @@ design: (work@carry_rtl) |vpiPrimitive: \_switch_tran: work@tranif0 (work@carry_trans.p3), line:32:9, endln:32:22 |vpiParent: - \_module: work@carry_trans (work@carry_trans), file:${SURELOG_DIR}/tests/CarryTrans/dut.sv, line:18:1, endln:37:10 + \_module_inst: work@carry_trans (work@carry_trans), file:${SURELOG_DIR}/tests/CarryTrans/dut.sv, line:18:1, endln:37:10 |vpiDefName:work@tranif0 |vpiName:p3 |vpiFullName:work@carry_trans.p3 @@ -2908,7 +2908,7 @@ design: (work@carry_rtl) |vpiPrimitive: \_switch_tran: work@tranif0 (work@carry_trans.p4), line:33:9, endln:33:23 |vpiParent: - \_module: work@carry_trans (work@carry_trans), file:${SURELOG_DIR}/tests/CarryTrans/dut.sv, line:18:1, endln:37:10 + \_module_inst: work@carry_trans (work@carry_trans), file:${SURELOG_DIR}/tests/CarryTrans/dut.sv, line:18:1, endln:37:10 |vpiDefName:work@tranif0 |vpiName:p4 |vpiFullName:work@carry_trans.p4 @@ -2957,7 +2957,7 @@ design: (work@carry_rtl) |vpiPrimitive: \_switch_tran: work@tranif0 (work@carry_trans.p5), line:34:9, endln:34:22 |vpiParent: - \_module: work@carry_trans (work@carry_trans), file:${SURELOG_DIR}/tests/CarryTrans/dut.sv, line:18:1, endln:37:10 + \_module_inst: work@carry_trans (work@carry_trans), file:${SURELOG_DIR}/tests/CarryTrans/dut.sv, line:18:1, endln:37:10 |vpiDefName:work@tranif0 |vpiName:p5 |vpiFullName:work@carry_trans.p5 @@ -3006,7 +3006,7 @@ design: (work@carry_rtl) |vpiPrimitive: \_switch_tran: work@tranif1 (work@carry_trans.n6), line:35:9, endln:35:27 |vpiParent: - \_module: work@carry_trans (work@carry_trans), file:${SURELOG_DIR}/tests/CarryTrans/dut.sv, line:18:1, endln:37:10 + \_module_inst: work@carry_trans (work@carry_trans), file:${SURELOG_DIR}/tests/CarryTrans/dut.sv, line:18:1, endln:37:10 |vpiDefName:work@tranif1 |vpiName:n6 |vpiFullName:work@carry_trans.n6 @@ -3055,7 +3055,7 @@ design: (work@carry_rtl) |vpiPrimitive: \_switch_tran: work@tranif0 (work@carry_trans.p6), line:36:9, endln:36:26 |vpiParent: - \_module: work@carry_trans (work@carry_trans), file:${SURELOG_DIR}/tests/CarryTrans/dut.sv, line:18:1, endln:37:10 + \_module_inst: work@carry_trans (work@carry_trans), file:${SURELOG_DIR}/tests/CarryTrans/dut.sv, line:18:1, endln:37:10 |vpiDefName:work@tranif0 |vpiName:p6 |vpiFullName:work@carry_trans.p6 diff --git a/tests/CaseExpression/CaseExpression.log b/tests/CaseExpression/CaseExpression.log index 1ef79c4c0a..c6605d35f7 100644 --- a/tests/CaseExpression/CaseExpression.log +++ b/tests/CaseExpression/CaseExpression.log @@ -838,7 +838,7 @@ initial 1 int_typespec 8 logic_net 43 logic_typespec 28 -module 4 +module_inst 4 port 16 range 15 ref_obj 66 @@ -857,7 +857,7 @@ initial 2 int_typespec 8 logic_net 43 logic_typespec 28 -module 4 +module_inst 4 port 24 range 15 ref_obj 124 @@ -875,7 +875,7 @@ design: (work@case_expr_non_const_top) |vpiElaborated:1 |vpiName:work@case_expr_non_const_top |uhdmallModules: -\_module: work@case_expr_non_const_top (work@case_expr_non_const_top), file:${SURELOG_DIR}/tests/CaseExpression/dut.sv, line:3:1, endln:59:10 +\_module_inst: work@case_expr_non_const_top (work@case_expr_non_const_top), file:${SURELOG_DIR}/tests/CaseExpression/dut.sv, line:3:1, endln:59:10 |vpiParent: \_design: (work@case_expr_non_const_top) |vpiFullName:work@case_expr_non_const_top @@ -883,126 +883,126 @@ design: (work@case_expr_non_const_top) |vpiNet: \_logic_net: (work@case_expr_non_const_top.a), line:5:16, endln:5:17 |vpiParent: - \_module: work@case_expr_non_const_top (work@case_expr_non_const_top), file:${SURELOG_DIR}/tests/CaseExpression/dut.sv, line:3:1, endln:59:10 + \_module_inst: work@case_expr_non_const_top (work@case_expr_non_const_top), file:${SURELOG_DIR}/tests/CaseExpression/dut.sv, line:3:1, endln:59:10 |vpiName:a |vpiFullName:work@case_expr_non_const_top.a |vpiNetType:48 |vpiNet: \_logic_net: (work@case_expr_non_const_top.b), line:5:19, endln:5:20 |vpiParent: - \_module: work@case_expr_non_const_top (work@case_expr_non_const_top), file:${SURELOG_DIR}/tests/CaseExpression/dut.sv, line:3:1, endln:59:10 + \_module_inst: work@case_expr_non_const_top (work@case_expr_non_const_top), file:${SURELOG_DIR}/tests/CaseExpression/dut.sv, line:3:1, endln:59:10 |vpiName:b |vpiFullName:work@case_expr_non_const_top.b |vpiNetType:48 |vpiNet: \_logic_net: (work@case_expr_non_const_top.c), line:5:22, endln:5:23 |vpiParent: - \_module: work@case_expr_non_const_top (work@case_expr_non_const_top), file:${SURELOG_DIR}/tests/CaseExpression/dut.sv, line:3:1, endln:59:10 + \_module_inst: work@case_expr_non_const_top (work@case_expr_non_const_top), file:${SURELOG_DIR}/tests/CaseExpression/dut.sv, line:3:1, endln:59:10 |vpiName:c |vpiFullName:work@case_expr_non_const_top.c |vpiNetType:48 |vpiNet: \_logic_net: (work@case_expr_non_const_top.d), line:5:25, endln:5:26 |vpiParent: - \_module: work@case_expr_non_const_top (work@case_expr_non_const_top), file:${SURELOG_DIR}/tests/CaseExpression/dut.sv, line:3:1, endln:59:10 + \_module_inst: work@case_expr_non_const_top (work@case_expr_non_const_top), file:${SURELOG_DIR}/tests/CaseExpression/dut.sv, line:3:1, endln:59:10 |vpiName:d |vpiFullName:work@case_expr_non_const_top.d |vpiNetType:48 |vpiNet: \_logic_net: (work@case_expr_non_const_top.e), line:5:28, endln:5:29 |vpiParent: - \_module: work@case_expr_non_const_top (work@case_expr_non_const_top), file:${SURELOG_DIR}/tests/CaseExpression/dut.sv, line:3:1, endln:59:10 + \_module_inst: work@case_expr_non_const_top (work@case_expr_non_const_top), file:${SURELOG_DIR}/tests/CaseExpression/dut.sv, line:3:1, endln:59:10 |vpiName:e |vpiFullName:work@case_expr_non_const_top.e |vpiNetType:48 |vpiNet: \_logic_net: (work@case_expr_non_const_top.f), line:5:31, endln:5:32 |vpiParent: - \_module: work@case_expr_non_const_top (work@case_expr_non_const_top), file:${SURELOG_DIR}/tests/CaseExpression/dut.sv, line:3:1, endln:59:10 + \_module_inst: work@case_expr_non_const_top (work@case_expr_non_const_top), file:${SURELOG_DIR}/tests/CaseExpression/dut.sv, line:3:1, endln:59:10 |vpiName:f |vpiFullName:work@case_expr_non_const_top.f |vpiNetType:48 |vpiNet: \_logic_net: (work@case_expr_non_const_top.g), line:5:34, endln:5:35 |vpiParent: - \_module: work@case_expr_non_const_top (work@case_expr_non_const_top), file:${SURELOG_DIR}/tests/CaseExpression/dut.sv, line:3:1, endln:59:10 + \_module_inst: work@case_expr_non_const_top (work@case_expr_non_const_top), file:${SURELOG_DIR}/tests/CaseExpression/dut.sv, line:3:1, endln:59:10 |vpiName:g |vpiFullName:work@case_expr_non_const_top.g |vpiNetType:48 |vpiNet: \_logic_net: (work@case_expr_non_const_top.h), line:5:37, endln:5:38 |vpiParent: - \_module: work@case_expr_non_const_top (work@case_expr_non_const_top), file:${SURELOG_DIR}/tests/CaseExpression/dut.sv, line:3:1, endln:59:10 + \_module_inst: work@case_expr_non_const_top (work@case_expr_non_const_top), file:${SURELOG_DIR}/tests/CaseExpression/dut.sv, line:3:1, endln:59:10 |vpiName:h |vpiFullName:work@case_expr_non_const_top.h |vpiNetType:48 |vpiNet: \_logic_net: (work@case_expr_non_const_top.x_1b0), line:7:9, endln:7:14 |vpiParent: - \_module: work@case_expr_non_const_top (work@case_expr_non_const_top), file:${SURELOG_DIR}/tests/CaseExpression/dut.sv, line:3:1, endln:59:10 + \_module_inst: work@case_expr_non_const_top (work@case_expr_non_const_top), file:${SURELOG_DIR}/tests/CaseExpression/dut.sv, line:3:1, endln:59:10 |vpiName:x_1b0 |vpiFullName:work@case_expr_non_const_top.x_1b0 |vpiNetType:48 |vpiNet: \_logic_net: (work@case_expr_non_const_top.x_1b1), line:8:9, endln:8:14 |vpiParent: - \_module: work@case_expr_non_const_top (work@case_expr_non_const_top), file:${SURELOG_DIR}/tests/CaseExpression/dut.sv, line:3:1, endln:59:10 + \_module_inst: work@case_expr_non_const_top (work@case_expr_non_const_top), file:${SURELOG_DIR}/tests/CaseExpression/dut.sv, line:3:1, endln:59:10 |vpiName:x_1b1 |vpiFullName:work@case_expr_non_const_top.x_1b1 |vpiNetType:48 |vpiNet: \_logic_net: (work@case_expr_non_const_top.x_1sb0), line:9:16, endln:9:22 |vpiParent: - \_module: work@case_expr_non_const_top (work@case_expr_non_const_top), file:${SURELOG_DIR}/tests/CaseExpression/dut.sv, line:3:1, endln:59:10 + \_module_inst: work@case_expr_non_const_top (work@case_expr_non_const_top), file:${SURELOG_DIR}/tests/CaseExpression/dut.sv, line:3:1, endln:59:10 |vpiName:x_1sb0 |vpiFullName:work@case_expr_non_const_top.x_1sb0 |vpiNetType:48 |vpiNet: \_logic_net: (work@case_expr_non_const_top.x_1sb1), line:10:16, endln:10:22 |vpiParent: - \_module: work@case_expr_non_const_top (work@case_expr_non_const_top), file:${SURELOG_DIR}/tests/CaseExpression/dut.sv, line:3:1, endln:59:10 + \_module_inst: work@case_expr_non_const_top (work@case_expr_non_const_top), file:${SURELOG_DIR}/tests/CaseExpression/dut.sv, line:3:1, endln:59:10 |vpiName:x_1sb1 |vpiFullName:work@case_expr_non_const_top.x_1sb1 |vpiNetType:48 |vpiNet: \_logic_net: (work@case_expr_non_const_top.x_2b0), line:11:15, endln:11:20 |vpiParent: - \_module: work@case_expr_non_const_top (work@case_expr_non_const_top), file:${SURELOG_DIR}/tests/CaseExpression/dut.sv, line:3:1, endln:59:10 + \_module_inst: work@case_expr_non_const_top (work@case_expr_non_const_top), file:${SURELOG_DIR}/tests/CaseExpression/dut.sv, line:3:1, endln:59:10 |vpiName:x_2b0 |vpiFullName:work@case_expr_non_const_top.x_2b0 |vpiNetType:48 |vpiNet: \_logic_net: (work@case_expr_non_const_top.x_2b11), line:12:15, endln:12:21 |vpiParent: - \_module: work@case_expr_non_const_top (work@case_expr_non_const_top), file:${SURELOG_DIR}/tests/CaseExpression/dut.sv, line:3:1, endln:59:10 + \_module_inst: work@case_expr_non_const_top (work@case_expr_non_const_top), file:${SURELOG_DIR}/tests/CaseExpression/dut.sv, line:3:1, endln:59:10 |vpiName:x_2b11 |vpiFullName:work@case_expr_non_const_top.x_2b11 |vpiNetType:48 |vpiNet: \_logic_net: (work@case_expr_non_const_top.x_2sb01), line:13:22, endln:13:29 |vpiParent: - \_module: work@case_expr_non_const_top (work@case_expr_non_const_top), file:${SURELOG_DIR}/tests/CaseExpression/dut.sv, line:3:1, endln:59:10 + \_module_inst: work@case_expr_non_const_top (work@case_expr_non_const_top), file:${SURELOG_DIR}/tests/CaseExpression/dut.sv, line:3:1, endln:59:10 |vpiName:x_2sb01 |vpiFullName:work@case_expr_non_const_top.x_2sb01 |vpiNetType:48 |vpiNet: \_logic_net: (work@case_expr_non_const_top.x_2sb11), line:14:22, endln:14:29 |vpiParent: - \_module: work@case_expr_non_const_top (work@case_expr_non_const_top), file:${SURELOG_DIR}/tests/CaseExpression/dut.sv, line:3:1, endln:59:10 + \_module_inst: work@case_expr_non_const_top (work@case_expr_non_const_top), file:${SURELOG_DIR}/tests/CaseExpression/dut.sv, line:3:1, endln:59:10 |vpiName:x_2sb11 |vpiFullName:work@case_expr_non_const_top.x_2sb11 |vpiNetType:48 |vpiNet: \_logic_net: (work@case_expr_non_const_top.x_3b0), line:15:15, endln:15:20 |vpiParent: - \_module: work@case_expr_non_const_top (work@case_expr_non_const_top), file:${SURELOG_DIR}/tests/CaseExpression/dut.sv, line:3:1, endln:59:10 + \_module_inst: work@case_expr_non_const_top (work@case_expr_non_const_top), file:${SURELOG_DIR}/tests/CaseExpression/dut.sv, line:3:1, endln:59:10 |vpiName:x_3b0 |vpiFullName:work@case_expr_non_const_top.x_3b0 |vpiNetType:48 |vpiPort: \_port: (a), line:5:16, endln:5:17 |vpiParent: - \_module: work@case_expr_non_const_top (work@case_expr_non_const_top), file:${SURELOG_DIR}/tests/CaseExpression/dut.sv, line:3:1, endln:59:10 + \_module_inst: work@case_expr_non_const_top (work@case_expr_non_const_top), file:${SURELOG_DIR}/tests/CaseExpression/dut.sv, line:3:1, endln:59:10 |vpiName:a |vpiDirection:2 |vpiLowConn: @@ -1014,7 +1014,7 @@ design: (work@case_expr_non_const_top) |vpiPort: \_port: (b), line:5:19, endln:5:20 |vpiParent: - \_module: work@case_expr_non_const_top (work@case_expr_non_const_top), file:${SURELOG_DIR}/tests/CaseExpression/dut.sv, line:3:1, endln:59:10 + \_module_inst: work@case_expr_non_const_top (work@case_expr_non_const_top), file:${SURELOG_DIR}/tests/CaseExpression/dut.sv, line:3:1, endln:59:10 |vpiName:b |vpiDirection:2 |vpiLowConn: @@ -1026,7 +1026,7 @@ design: (work@case_expr_non_const_top) |vpiPort: \_port: (c), line:5:22, endln:5:23 |vpiParent: - \_module: work@case_expr_non_const_top (work@case_expr_non_const_top), file:${SURELOG_DIR}/tests/CaseExpression/dut.sv, line:3:1, endln:59:10 + \_module_inst: work@case_expr_non_const_top (work@case_expr_non_const_top), file:${SURELOG_DIR}/tests/CaseExpression/dut.sv, line:3:1, endln:59:10 |vpiName:c |vpiDirection:2 |vpiLowConn: @@ -1038,7 +1038,7 @@ design: (work@case_expr_non_const_top) |vpiPort: \_port: (d), line:5:25, endln:5:26 |vpiParent: - \_module: work@case_expr_non_const_top (work@case_expr_non_const_top), file:${SURELOG_DIR}/tests/CaseExpression/dut.sv, line:3:1, endln:59:10 + \_module_inst: work@case_expr_non_const_top (work@case_expr_non_const_top), file:${SURELOG_DIR}/tests/CaseExpression/dut.sv, line:3:1, endln:59:10 |vpiName:d |vpiDirection:2 |vpiLowConn: @@ -1050,7 +1050,7 @@ design: (work@case_expr_non_const_top) |vpiPort: \_port: (e), line:5:28, endln:5:29 |vpiParent: - \_module: work@case_expr_non_const_top (work@case_expr_non_const_top), file:${SURELOG_DIR}/tests/CaseExpression/dut.sv, line:3:1, endln:59:10 + \_module_inst: work@case_expr_non_const_top (work@case_expr_non_const_top), file:${SURELOG_DIR}/tests/CaseExpression/dut.sv, line:3:1, endln:59:10 |vpiName:e |vpiDirection:2 |vpiLowConn: @@ -1062,7 +1062,7 @@ design: (work@case_expr_non_const_top) |vpiPort: \_port: (f), line:5:31, endln:5:32 |vpiParent: - \_module: work@case_expr_non_const_top (work@case_expr_non_const_top), file:${SURELOG_DIR}/tests/CaseExpression/dut.sv, line:3:1, endln:59:10 + \_module_inst: work@case_expr_non_const_top (work@case_expr_non_const_top), file:${SURELOG_DIR}/tests/CaseExpression/dut.sv, line:3:1, endln:59:10 |vpiName:f |vpiDirection:2 |vpiLowConn: @@ -1074,7 +1074,7 @@ design: (work@case_expr_non_const_top) |vpiPort: \_port: (g), line:5:34, endln:5:35 |vpiParent: - \_module: work@case_expr_non_const_top (work@case_expr_non_const_top), file:${SURELOG_DIR}/tests/CaseExpression/dut.sv, line:3:1, endln:59:10 + \_module_inst: work@case_expr_non_const_top (work@case_expr_non_const_top), file:${SURELOG_DIR}/tests/CaseExpression/dut.sv, line:3:1, endln:59:10 |vpiName:g |vpiDirection:2 |vpiLowConn: @@ -1086,7 +1086,7 @@ design: (work@case_expr_non_const_top) |vpiPort: \_port: (h), line:5:37, endln:5:38 |vpiParent: - \_module: work@case_expr_non_const_top (work@case_expr_non_const_top), file:${SURELOG_DIR}/tests/CaseExpression/dut.sv, line:3:1, endln:59:10 + \_module_inst: work@case_expr_non_const_top (work@case_expr_non_const_top), file:${SURELOG_DIR}/tests/CaseExpression/dut.sv, line:3:1, endln:59:10 |vpiName:h |vpiDirection:2 |vpiLowConn: @@ -1098,7 +1098,7 @@ design: (work@case_expr_non_const_top) |vpiProcess: \_initial: , line:17:5, endln:58:8 |vpiParent: - \_module: work@case_expr_non_const_top (work@case_expr_non_const_top), file:${SURELOG_DIR}/tests/CaseExpression/dut.sv, line:3:1, endln:59:10 + \_module_inst: work@case_expr_non_const_top (work@case_expr_non_const_top), file:${SURELOG_DIR}/tests/CaseExpression/dut.sv, line:3:1, endln:59:10 |vpiStmt: \_begin: (work@case_expr_non_const_top), line:17:13, endln:58:8 |vpiParent: @@ -1995,14 +1995,14 @@ design: (work@case_expr_non_const_top) |vpiActual: \_logic_net: (work@case_expr_non_const_top.h), line:5:37, endln:5:38 |uhdmtopModules: -\_module: work@case_expr_non_const_top (work@case_expr_non_const_top), file:${SURELOG_DIR}/tests/CaseExpression/dut.sv, line:3:1, endln:59:10 +\_module_inst: work@case_expr_non_const_top (work@case_expr_non_const_top), file:${SURELOG_DIR}/tests/CaseExpression/dut.sv, line:3:1, endln:59:10 |vpiName:work@case_expr_non_const_top |vpiDefName:work@case_expr_non_const_top |vpiTop:1 |vpiNet: \_logic_net: (work@case_expr_non_const_top.a), line:5:16, endln:5:17 |vpiParent: - \_module: work@case_expr_non_const_top (work@case_expr_non_const_top), file:${SURELOG_DIR}/tests/CaseExpression/dut.sv, line:3:1, endln:59:10 + \_module_inst: work@case_expr_non_const_top (work@case_expr_non_const_top), file:${SURELOG_DIR}/tests/CaseExpression/dut.sv, line:3:1, endln:59:10 |vpiTypespec: \_logic_typespec: , line:5:12, endln:5:15 |vpiName:a @@ -2011,7 +2011,7 @@ design: (work@case_expr_non_const_top) |vpiNet: \_logic_net: (work@case_expr_non_const_top.b), line:5:19, endln:5:20 |vpiParent: - \_module: work@case_expr_non_const_top (work@case_expr_non_const_top), file:${SURELOG_DIR}/tests/CaseExpression/dut.sv, line:3:1, endln:59:10 + \_module_inst: work@case_expr_non_const_top (work@case_expr_non_const_top), file:${SURELOG_DIR}/tests/CaseExpression/dut.sv, line:3:1, endln:59:10 |vpiTypespec: \_logic_typespec: , line:5:12, endln:5:15 |vpiName:b @@ -2020,7 +2020,7 @@ design: (work@case_expr_non_const_top) |vpiNet: \_logic_net: (work@case_expr_non_const_top.c), line:5:22, endln:5:23 |vpiParent: - \_module: work@case_expr_non_const_top (work@case_expr_non_const_top), file:${SURELOG_DIR}/tests/CaseExpression/dut.sv, line:3:1, endln:59:10 + \_module_inst: work@case_expr_non_const_top (work@case_expr_non_const_top), file:${SURELOG_DIR}/tests/CaseExpression/dut.sv, line:3:1, endln:59:10 |vpiTypespec: \_logic_typespec: , line:5:12, endln:5:15 |vpiName:c @@ -2029,7 +2029,7 @@ design: (work@case_expr_non_const_top) |vpiNet: \_logic_net: (work@case_expr_non_const_top.d), line:5:25, endln:5:26 |vpiParent: - \_module: work@case_expr_non_const_top (work@case_expr_non_const_top), file:${SURELOG_DIR}/tests/CaseExpression/dut.sv, line:3:1, endln:59:10 + \_module_inst: work@case_expr_non_const_top (work@case_expr_non_const_top), file:${SURELOG_DIR}/tests/CaseExpression/dut.sv, line:3:1, endln:59:10 |vpiTypespec: \_logic_typespec: , line:5:12, endln:5:15 |vpiName:d @@ -2038,7 +2038,7 @@ design: (work@case_expr_non_const_top) |vpiNet: \_logic_net: (work@case_expr_non_const_top.e), line:5:28, endln:5:29 |vpiParent: - \_module: work@case_expr_non_const_top (work@case_expr_non_const_top), file:${SURELOG_DIR}/tests/CaseExpression/dut.sv, line:3:1, endln:59:10 + \_module_inst: work@case_expr_non_const_top (work@case_expr_non_const_top), file:${SURELOG_DIR}/tests/CaseExpression/dut.sv, line:3:1, endln:59:10 |vpiTypespec: \_logic_typespec: , line:5:12, endln:5:15 |vpiName:e @@ -2047,7 +2047,7 @@ design: (work@case_expr_non_const_top) |vpiNet: \_logic_net: (work@case_expr_non_const_top.f), line:5:31, endln:5:32 |vpiParent: - \_module: work@case_expr_non_const_top (work@case_expr_non_const_top), file:${SURELOG_DIR}/tests/CaseExpression/dut.sv, line:3:1, endln:59:10 + \_module_inst: work@case_expr_non_const_top (work@case_expr_non_const_top), file:${SURELOG_DIR}/tests/CaseExpression/dut.sv, line:3:1, endln:59:10 |vpiTypespec: \_logic_typespec: , line:5:12, endln:5:15 |vpiName:f @@ -2056,7 +2056,7 @@ design: (work@case_expr_non_const_top) |vpiNet: \_logic_net: (work@case_expr_non_const_top.g), line:5:34, endln:5:35 |vpiParent: - \_module: work@case_expr_non_const_top (work@case_expr_non_const_top), file:${SURELOG_DIR}/tests/CaseExpression/dut.sv, line:3:1, endln:59:10 + \_module_inst: work@case_expr_non_const_top (work@case_expr_non_const_top), file:${SURELOG_DIR}/tests/CaseExpression/dut.sv, line:3:1, endln:59:10 |vpiTypespec: \_logic_typespec: , line:5:12, endln:5:15 |vpiName:g @@ -2065,7 +2065,7 @@ design: (work@case_expr_non_const_top) |vpiNet: \_logic_net: (work@case_expr_non_const_top.h), line:5:37, endln:5:38 |vpiParent: - \_module: work@case_expr_non_const_top (work@case_expr_non_const_top), file:${SURELOG_DIR}/tests/CaseExpression/dut.sv, line:3:1, endln:59:10 + \_module_inst: work@case_expr_non_const_top (work@case_expr_non_const_top), file:${SURELOG_DIR}/tests/CaseExpression/dut.sv, line:3:1, endln:59:10 |vpiTypespec: \_logic_typespec: , line:5:12, endln:5:15 |vpiName:h @@ -2074,7 +2074,7 @@ design: (work@case_expr_non_const_top) |vpiNet: \_logic_net: (work@case_expr_non_const_top.x_1b0), line:7:9, endln:7:21 |vpiParent: - \_module: work@case_expr_non_const_top (work@case_expr_non_const_top), file:${SURELOG_DIR}/tests/CaseExpression/dut.sv, line:3:1, endln:59:10 + \_module_inst: work@case_expr_non_const_top (work@case_expr_non_const_top), file:${SURELOG_DIR}/tests/CaseExpression/dut.sv, line:3:1, endln:59:10 |vpiTypespec: \_logic_typespec: , line:7:5, endln:7:8 |vpiName:x_1b0 @@ -2083,7 +2083,7 @@ design: (work@case_expr_non_const_top) |vpiNet: \_logic_net: (work@case_expr_non_const_top.x_1b1), line:8:9, endln:8:21 |vpiParent: - \_module: work@case_expr_non_const_top (work@case_expr_non_const_top), file:${SURELOG_DIR}/tests/CaseExpression/dut.sv, line:3:1, endln:59:10 + \_module_inst: work@case_expr_non_const_top (work@case_expr_non_const_top), file:${SURELOG_DIR}/tests/CaseExpression/dut.sv, line:3:1, endln:59:10 |vpiTypespec: \_logic_typespec: , line:8:5, endln:8:8 |vpiName:x_1b1 @@ -2092,7 +2092,7 @@ design: (work@case_expr_non_const_top) |vpiNet: \_logic_net: (work@case_expr_non_const_top.x_1sb0), line:9:16, endln:9:30 |vpiParent: - \_module: work@case_expr_non_const_top (work@case_expr_non_const_top), file:${SURELOG_DIR}/tests/CaseExpression/dut.sv, line:3:1, endln:59:10 + \_module_inst: work@case_expr_non_const_top (work@case_expr_non_const_top), file:${SURELOG_DIR}/tests/CaseExpression/dut.sv, line:3:1, endln:59:10 |vpiTypespec: \_logic_typespec: , line:9:5, endln:9:8 |vpiSigned:1 @@ -2103,7 +2103,7 @@ design: (work@case_expr_non_const_top) |vpiNet: \_logic_net: (work@case_expr_non_const_top.x_1sb1), line:10:16, endln:10:30 |vpiParent: - \_module: work@case_expr_non_const_top (work@case_expr_non_const_top), file:${SURELOG_DIR}/tests/CaseExpression/dut.sv, line:3:1, endln:59:10 + \_module_inst: work@case_expr_non_const_top (work@case_expr_non_const_top), file:${SURELOG_DIR}/tests/CaseExpression/dut.sv, line:3:1, endln:59:10 |vpiTypespec: \_logic_typespec: , line:10:5, endln:10:8 |vpiSigned:1 @@ -2114,7 +2114,7 @@ design: (work@case_expr_non_const_top) |vpiNet: \_logic_net: (work@case_expr_non_const_top.x_2b0), line:11:15, endln:11:27 |vpiParent: - \_module: work@case_expr_non_const_top (work@case_expr_non_const_top), file:${SURELOG_DIR}/tests/CaseExpression/dut.sv, line:3:1, endln:59:10 + \_module_inst: work@case_expr_non_const_top (work@case_expr_non_const_top), file:${SURELOG_DIR}/tests/CaseExpression/dut.sv, line:3:1, endln:59:10 |vpiTypespec: \_logic_typespec: , line:11:5, endln:11:14 |vpiRange: @@ -2141,7 +2141,7 @@ design: (work@case_expr_non_const_top) |vpiNet: \_logic_net: (work@case_expr_non_const_top.x_2b11), line:12:15, endln:12:29 |vpiParent: - \_module: work@case_expr_non_const_top (work@case_expr_non_const_top), file:${SURELOG_DIR}/tests/CaseExpression/dut.sv, line:3:1, endln:59:10 + \_module_inst: work@case_expr_non_const_top (work@case_expr_non_const_top), file:${SURELOG_DIR}/tests/CaseExpression/dut.sv, line:3:1, endln:59:10 |vpiTypespec: \_logic_typespec: , line:12:5, endln:12:14 |vpiRange: @@ -2168,7 +2168,7 @@ design: (work@case_expr_non_const_top) |vpiNet: \_logic_net: (work@case_expr_non_const_top.x_2sb01), line:13:22, endln:13:38 |vpiParent: - \_module: work@case_expr_non_const_top (work@case_expr_non_const_top), file:${SURELOG_DIR}/tests/CaseExpression/dut.sv, line:3:1, endln:59:10 + \_module_inst: work@case_expr_non_const_top (work@case_expr_non_const_top), file:${SURELOG_DIR}/tests/CaseExpression/dut.sv, line:3:1, endln:59:10 |vpiTypespec: \_logic_typespec: , line:13:5, endln:13:21 |vpiRange: @@ -2197,7 +2197,7 @@ design: (work@case_expr_non_const_top) |vpiNet: \_logic_net: (work@case_expr_non_const_top.x_2sb11), line:14:22, endln:14:38 |vpiParent: - \_module: work@case_expr_non_const_top (work@case_expr_non_const_top), file:${SURELOG_DIR}/tests/CaseExpression/dut.sv, line:3:1, endln:59:10 + \_module_inst: work@case_expr_non_const_top (work@case_expr_non_const_top), file:${SURELOG_DIR}/tests/CaseExpression/dut.sv, line:3:1, endln:59:10 |vpiTypespec: \_logic_typespec: , line:14:5, endln:14:21 |vpiRange: @@ -2226,7 +2226,7 @@ design: (work@case_expr_non_const_top) |vpiNet: \_logic_net: (work@case_expr_non_const_top.x_3b0), line:15:15, endln:15:27 |vpiParent: - \_module: work@case_expr_non_const_top (work@case_expr_non_const_top), file:${SURELOG_DIR}/tests/CaseExpression/dut.sv, line:3:1, endln:59:10 + \_module_inst: work@case_expr_non_const_top (work@case_expr_non_const_top), file:${SURELOG_DIR}/tests/CaseExpression/dut.sv, line:3:1, endln:59:10 |vpiTypespec: \_logic_typespec: , line:15:5, endln:15:14 |vpiRange: @@ -2254,7 +2254,7 @@ design: (work@case_expr_non_const_top) |vpiPort: \_port: (a), line:5:16, endln:5:17 |vpiParent: - \_module: work@case_expr_non_const_top (work@case_expr_non_const_top), file:${SURELOG_DIR}/tests/CaseExpression/dut.sv, line:3:1, endln:59:10 + \_module_inst: work@case_expr_non_const_top (work@case_expr_non_const_top), file:${SURELOG_DIR}/tests/CaseExpression/dut.sv, line:3:1, endln:59:10 |vpiName:a |vpiDirection:2 |vpiLowConn: @@ -2268,11 +2268,11 @@ design: (work@case_expr_non_const_top) |vpiTypedef: \_logic_typespec: , line:5:12, endln:5:15 |vpiInstance: - \_module: work@case_expr_non_const_top (work@case_expr_non_const_top), file:${SURELOG_DIR}/tests/CaseExpression/dut.sv, line:3:1, endln:59:10 + \_module_inst: work@case_expr_non_const_top (work@case_expr_non_const_top), file:${SURELOG_DIR}/tests/CaseExpression/dut.sv, line:3:1, endln:59:10 |vpiPort: \_port: (b), line:5:19, endln:5:20 |vpiParent: - \_module: work@case_expr_non_const_top (work@case_expr_non_const_top), file:${SURELOG_DIR}/tests/CaseExpression/dut.sv, line:3:1, endln:59:10 + \_module_inst: work@case_expr_non_const_top (work@case_expr_non_const_top), file:${SURELOG_DIR}/tests/CaseExpression/dut.sv, line:3:1, endln:59:10 |vpiName:b |vpiDirection:2 |vpiLowConn: @@ -2286,11 +2286,11 @@ design: (work@case_expr_non_const_top) |vpiTypedef: \_logic_typespec: , line:5:12, endln:5:15 |vpiInstance: - \_module: work@case_expr_non_const_top (work@case_expr_non_const_top), file:${SURELOG_DIR}/tests/CaseExpression/dut.sv, line:3:1, endln:59:10 + \_module_inst: work@case_expr_non_const_top (work@case_expr_non_const_top), file:${SURELOG_DIR}/tests/CaseExpression/dut.sv, line:3:1, endln:59:10 |vpiPort: \_port: (c), line:5:22, endln:5:23 |vpiParent: - \_module: work@case_expr_non_const_top (work@case_expr_non_const_top), file:${SURELOG_DIR}/tests/CaseExpression/dut.sv, line:3:1, endln:59:10 + \_module_inst: work@case_expr_non_const_top (work@case_expr_non_const_top), file:${SURELOG_DIR}/tests/CaseExpression/dut.sv, line:3:1, endln:59:10 |vpiName:c |vpiDirection:2 |vpiLowConn: @@ -2304,11 +2304,11 @@ design: (work@case_expr_non_const_top) |vpiTypedef: \_logic_typespec: , line:5:12, endln:5:15 |vpiInstance: - \_module: work@case_expr_non_const_top (work@case_expr_non_const_top), file:${SURELOG_DIR}/tests/CaseExpression/dut.sv, line:3:1, endln:59:10 + \_module_inst: work@case_expr_non_const_top (work@case_expr_non_const_top), file:${SURELOG_DIR}/tests/CaseExpression/dut.sv, line:3:1, endln:59:10 |vpiPort: \_port: (d), line:5:25, endln:5:26 |vpiParent: - \_module: work@case_expr_non_const_top (work@case_expr_non_const_top), file:${SURELOG_DIR}/tests/CaseExpression/dut.sv, line:3:1, endln:59:10 + \_module_inst: work@case_expr_non_const_top (work@case_expr_non_const_top), file:${SURELOG_DIR}/tests/CaseExpression/dut.sv, line:3:1, endln:59:10 |vpiName:d |vpiDirection:2 |vpiLowConn: @@ -2322,11 +2322,11 @@ design: (work@case_expr_non_const_top) |vpiTypedef: \_logic_typespec: , line:5:12, endln:5:15 |vpiInstance: - \_module: work@case_expr_non_const_top (work@case_expr_non_const_top), file:${SURELOG_DIR}/tests/CaseExpression/dut.sv, line:3:1, endln:59:10 + \_module_inst: work@case_expr_non_const_top (work@case_expr_non_const_top), file:${SURELOG_DIR}/tests/CaseExpression/dut.sv, line:3:1, endln:59:10 |vpiPort: \_port: (e), line:5:28, endln:5:29 |vpiParent: - \_module: work@case_expr_non_const_top (work@case_expr_non_const_top), file:${SURELOG_DIR}/tests/CaseExpression/dut.sv, line:3:1, endln:59:10 + \_module_inst: work@case_expr_non_const_top (work@case_expr_non_const_top), file:${SURELOG_DIR}/tests/CaseExpression/dut.sv, line:3:1, endln:59:10 |vpiName:e |vpiDirection:2 |vpiLowConn: @@ -2340,11 +2340,11 @@ design: (work@case_expr_non_const_top) |vpiTypedef: \_logic_typespec: , line:5:12, endln:5:15 |vpiInstance: - \_module: work@case_expr_non_const_top (work@case_expr_non_const_top), file:${SURELOG_DIR}/tests/CaseExpression/dut.sv, line:3:1, endln:59:10 + \_module_inst: work@case_expr_non_const_top (work@case_expr_non_const_top), file:${SURELOG_DIR}/tests/CaseExpression/dut.sv, line:3:1, endln:59:10 |vpiPort: \_port: (f), line:5:31, endln:5:32 |vpiParent: - \_module: work@case_expr_non_const_top (work@case_expr_non_const_top), file:${SURELOG_DIR}/tests/CaseExpression/dut.sv, line:3:1, endln:59:10 + \_module_inst: work@case_expr_non_const_top (work@case_expr_non_const_top), file:${SURELOG_DIR}/tests/CaseExpression/dut.sv, line:3:1, endln:59:10 |vpiName:f |vpiDirection:2 |vpiLowConn: @@ -2358,11 +2358,11 @@ design: (work@case_expr_non_const_top) |vpiTypedef: \_logic_typespec: , line:5:12, endln:5:15 |vpiInstance: - \_module: work@case_expr_non_const_top (work@case_expr_non_const_top), file:${SURELOG_DIR}/tests/CaseExpression/dut.sv, line:3:1, endln:59:10 + \_module_inst: work@case_expr_non_const_top (work@case_expr_non_const_top), file:${SURELOG_DIR}/tests/CaseExpression/dut.sv, line:3:1, endln:59:10 |vpiPort: \_port: (g), line:5:34, endln:5:35 |vpiParent: - \_module: work@case_expr_non_const_top (work@case_expr_non_const_top), file:${SURELOG_DIR}/tests/CaseExpression/dut.sv, line:3:1, endln:59:10 + \_module_inst: work@case_expr_non_const_top (work@case_expr_non_const_top), file:${SURELOG_DIR}/tests/CaseExpression/dut.sv, line:3:1, endln:59:10 |vpiName:g |vpiDirection:2 |vpiLowConn: @@ -2376,11 +2376,11 @@ design: (work@case_expr_non_const_top) |vpiTypedef: \_logic_typespec: , line:5:12, endln:5:15 |vpiInstance: - \_module: work@case_expr_non_const_top (work@case_expr_non_const_top), file:${SURELOG_DIR}/tests/CaseExpression/dut.sv, line:3:1, endln:59:10 + \_module_inst: work@case_expr_non_const_top (work@case_expr_non_const_top), file:${SURELOG_DIR}/tests/CaseExpression/dut.sv, line:3:1, endln:59:10 |vpiPort: \_port: (h), line:5:37, endln:5:38 |vpiParent: - \_module: work@case_expr_non_const_top (work@case_expr_non_const_top), file:${SURELOG_DIR}/tests/CaseExpression/dut.sv, line:3:1, endln:59:10 + \_module_inst: work@case_expr_non_const_top (work@case_expr_non_const_top), file:${SURELOG_DIR}/tests/CaseExpression/dut.sv, line:3:1, endln:59:10 |vpiName:h |vpiDirection:2 |vpiLowConn: @@ -2394,11 +2394,11 @@ design: (work@case_expr_non_const_top) |vpiTypedef: \_logic_typespec: , line:5:12, endln:5:15 |vpiInstance: - \_module: work@case_expr_non_const_top (work@case_expr_non_const_top), file:${SURELOG_DIR}/tests/CaseExpression/dut.sv, line:3:1, endln:59:10 + \_module_inst: work@case_expr_non_const_top (work@case_expr_non_const_top), file:${SURELOG_DIR}/tests/CaseExpression/dut.sv, line:3:1, endln:59:10 |vpiProcess: \_initial: , line:17:5, endln:58:8 |vpiParent: - \_module: work@case_expr_non_const_top (work@case_expr_non_const_top), file:${SURELOG_DIR}/tests/CaseExpression/dut.sv, line:3:1, endln:59:10 + \_module_inst: work@case_expr_non_const_top (work@case_expr_non_const_top), file:${SURELOG_DIR}/tests/CaseExpression/dut.sv, line:3:1, endln:59:10 |vpiStmt: \_begin: (work@case_expr_non_const_top), line:17:13, endln:58:8 |vpiParent: @@ -3117,7 +3117,7 @@ design: (work@case_expr_non_const_top) |vpiContAssign: \_cont_assign: , line:7:9, endln:7:14 |vpiParent: - \_module: work@case_expr_non_const_top (work@case_expr_non_const_top), file:${SURELOG_DIR}/tests/CaseExpression/dut.sv, line:3:1, endln:59:10 + \_module_inst: work@case_expr_non_const_top (work@case_expr_non_const_top), file:${SURELOG_DIR}/tests/CaseExpression/dut.sv, line:3:1, endln:59:10 |vpiNetDeclAssign:1 |vpiRhs: \_constant: , line:7:17, endln:7:21 @@ -3132,7 +3132,7 @@ design: (work@case_expr_non_const_top) |vpiContAssign: \_cont_assign: , line:8:9, endln:8:14 |vpiParent: - \_module: work@case_expr_non_const_top (work@case_expr_non_const_top), file:${SURELOG_DIR}/tests/CaseExpression/dut.sv, line:3:1, endln:59:10 + \_module_inst: work@case_expr_non_const_top (work@case_expr_non_const_top), file:${SURELOG_DIR}/tests/CaseExpression/dut.sv, line:3:1, endln:59:10 |vpiNetDeclAssign:1 |vpiRhs: \_constant: , line:8:17, endln:8:21 @@ -3147,7 +3147,7 @@ design: (work@case_expr_non_const_top) |vpiContAssign: \_cont_assign: , line:9:16, endln:9:22 |vpiParent: - \_module: work@case_expr_non_const_top (work@case_expr_non_const_top), file:${SURELOG_DIR}/tests/CaseExpression/dut.sv, line:3:1, endln:59:10 + \_module_inst: work@case_expr_non_const_top (work@case_expr_non_const_top), file:${SURELOG_DIR}/tests/CaseExpression/dut.sv, line:3:1, endln:59:10 |vpiNetDeclAssign:1 |vpiRhs: \_constant: , line:9:25, endln:9:30 @@ -3165,7 +3165,7 @@ design: (work@case_expr_non_const_top) |vpiContAssign: \_cont_assign: , line:10:16, endln:10:22 |vpiParent: - \_module: work@case_expr_non_const_top (work@case_expr_non_const_top), file:${SURELOG_DIR}/tests/CaseExpression/dut.sv, line:3:1, endln:59:10 + \_module_inst: work@case_expr_non_const_top (work@case_expr_non_const_top), file:${SURELOG_DIR}/tests/CaseExpression/dut.sv, line:3:1, endln:59:10 |vpiNetDeclAssign:1 |vpiRhs: \_constant: , line:10:25, endln:10:30 @@ -3183,7 +3183,7 @@ design: (work@case_expr_non_const_top) |vpiContAssign: \_cont_assign: , line:11:15, endln:11:20 |vpiParent: - \_module: work@case_expr_non_const_top (work@case_expr_non_const_top), file:${SURELOG_DIR}/tests/CaseExpression/dut.sv, line:3:1, endln:59:10 + \_module_inst: work@case_expr_non_const_top (work@case_expr_non_const_top), file:${SURELOG_DIR}/tests/CaseExpression/dut.sv, line:3:1, endln:59:10 |vpiNetDeclAssign:1 |vpiRhs: \_constant: , line:11:23, endln:11:27 @@ -3192,7 +3192,7 @@ design: (work@case_expr_non_const_top) |vpiContAssign: \_cont_assign: , line:12:15, endln:12:21 |vpiParent: - \_module: work@case_expr_non_const_top (work@case_expr_non_const_top), file:${SURELOG_DIR}/tests/CaseExpression/dut.sv, line:3:1, endln:59:10 + \_module_inst: work@case_expr_non_const_top (work@case_expr_non_const_top), file:${SURELOG_DIR}/tests/CaseExpression/dut.sv, line:3:1, endln:59:10 |vpiNetDeclAssign:1 |vpiRhs: \_constant: , line:12:24, endln:12:29 @@ -3201,7 +3201,7 @@ design: (work@case_expr_non_const_top) |vpiContAssign: \_cont_assign: , line:13:22, endln:13:29 |vpiParent: - \_module: work@case_expr_non_const_top (work@case_expr_non_const_top), file:${SURELOG_DIR}/tests/CaseExpression/dut.sv, line:3:1, endln:59:10 + \_module_inst: work@case_expr_non_const_top (work@case_expr_non_const_top), file:${SURELOG_DIR}/tests/CaseExpression/dut.sv, line:3:1, endln:59:10 |vpiNetDeclAssign:1 |vpiRhs: \_constant: , line:13:32, endln:13:38 @@ -3210,7 +3210,7 @@ design: (work@case_expr_non_const_top) |vpiContAssign: \_cont_assign: , line:14:22, endln:14:29 |vpiParent: - \_module: work@case_expr_non_const_top (work@case_expr_non_const_top), file:${SURELOG_DIR}/tests/CaseExpression/dut.sv, line:3:1, endln:59:10 + \_module_inst: work@case_expr_non_const_top (work@case_expr_non_const_top), file:${SURELOG_DIR}/tests/CaseExpression/dut.sv, line:3:1, endln:59:10 |vpiNetDeclAssign:1 |vpiRhs: \_constant: , line:14:32, endln:14:38 @@ -3219,7 +3219,7 @@ design: (work@case_expr_non_const_top) |vpiContAssign: \_cont_assign: , line:15:15, endln:15:20 |vpiParent: - \_module: work@case_expr_non_const_top (work@case_expr_non_const_top), file:${SURELOG_DIR}/tests/CaseExpression/dut.sv, line:3:1, endln:59:10 + \_module_inst: work@case_expr_non_const_top (work@case_expr_non_const_top), file:${SURELOG_DIR}/tests/CaseExpression/dut.sv, line:3:1, endln:59:10 |vpiNetDeclAssign:1 |vpiRhs: \_constant: , line:15:23, endln:15:27 diff --git a/tests/CaseFullElab/CaseFullElab.log b/tests/CaseFullElab/CaseFullElab.log index e378b67457..b4ac89b0f7 100644 --- a/tests/CaseFullElab/CaseFullElab.log +++ b/tests/CaseFullElab/CaseFullElab.log @@ -686,7 +686,7 @@ io_decl 11 logic_net 16 logic_typespec 10 logic_var 1 -module 5 +module_inst 5 named_begin 1 operation 3 package 2 @@ -723,7 +723,7 @@ io_decl 22 logic_net 16 logic_typespec 10 logic_var 1 -module 5 +module_inst 5 named_begin 2 operation 6 package 2 @@ -1222,14 +1222,14 @@ design: (work@FSM) \_int_typespec: |vpiSigned:1 |uhdmallModules: -\_module: work@FSM (work@FSM), file:${SURELOG_DIR}/tests/CaseFullElab/top.sv, line:1:1, endln:42:12 +\_module_inst: work@FSM (work@FSM), file:${SURELOG_DIR}/tests/CaseFullElab/top.sv, line:1:1, endln:42:12 |vpiParent: \_design: (work@FSM) |vpiFullName:work@FSM |vpiParameter: \_parameter: (work@FSM.Stop), line:9:13, endln:9:17 |vpiParent: - \_module: work@FSM (work@FSM), file:${SURELOG_DIR}/tests/CaseFullElab/top.sv, line:1:1, endln:42:12 + \_module_inst: work@FSM (work@FSM), file:${SURELOG_DIR}/tests/CaseFullElab/top.sv, line:1:1, endln:42:12 |BIN:0000 |vpiTypespec: \_int_typespec: @@ -1246,7 +1246,7 @@ design: (work@FSM) |vpiParameter: \_parameter: (work@FSM.Move), line:10:13, endln:10:17 |vpiParent: - \_module: work@FSM (work@FSM), file:${SURELOG_DIR}/tests/CaseFullElab/top.sv, line:1:1, endln:42:12 + \_module_inst: work@FSM (work@FSM), file:${SURELOG_DIR}/tests/CaseFullElab/top.sv, line:1:1, endln:42:12 |BIN:0001 |vpiTypespec: \_int_typespec: @@ -1263,7 +1263,7 @@ design: (work@FSM) |vpiParameter: \_parameter: (work@FSM.Turn), line:11:13, endln:11:17 |vpiParent: - \_module: work@FSM (work@FSM), file:${SURELOG_DIR}/tests/CaseFullElab/top.sv, line:1:1, endln:42:12 + \_module_inst: work@FSM (work@FSM), file:${SURELOG_DIR}/tests/CaseFullElab/top.sv, line:1:1, endln:42:12 |BIN:0010 |vpiTypespec: \_int_typespec: @@ -1280,7 +1280,7 @@ design: (work@FSM) |vpiParameter: \_parameter: (work@FSM.Slow), line:12:13, endln:12:17 |vpiParent: - \_module: work@FSM (work@FSM), file:${SURELOG_DIR}/tests/CaseFullElab/top.sv, line:1:1, endln:42:12 + \_module_inst: work@FSM (work@FSM), file:${SURELOG_DIR}/tests/CaseFullElab/top.sv, line:1:1, endln:42:12 |BIN:0011 |vpiTypespec: \_int_typespec: @@ -1297,7 +1297,7 @@ design: (work@FSM) |vpiParameter: \_parameter: (work@FSM.Medium), line:13:13, endln:13:19 |vpiParent: - \_module: work@FSM (work@FSM), file:${SURELOG_DIR}/tests/CaseFullElab/top.sv, line:1:1, endln:42:12 + \_module_inst: work@FSM (work@FSM), file:${SURELOG_DIR}/tests/CaseFullElab/top.sv, line:1:1, endln:42:12 |BIN:0100 |vpiTypespec: \_int_typespec: @@ -1314,7 +1314,7 @@ design: (work@FSM) |vpiParameter: \_parameter: (work@FSM.Fast), line:14:13, endln:14:17 |vpiParent: - \_module: work@FSM (work@FSM), file:${SURELOG_DIR}/tests/CaseFullElab/top.sv, line:1:1, endln:42:12 + \_module_inst: work@FSM (work@FSM), file:${SURELOG_DIR}/tests/CaseFullElab/top.sv, line:1:1, endln:42:12 |BIN:0101 |vpiTypespec: \_int_typespec: @@ -1331,7 +1331,7 @@ design: (work@FSM) |vpiParameter: \_parameter: (work@FSM.Faster), line:15:13, endln:15:19 |vpiParent: - \_module: work@FSM (work@FSM), file:${SURELOG_DIR}/tests/CaseFullElab/top.sv, line:1:1, endln:42:12 + \_module_inst: work@FSM (work@FSM), file:${SURELOG_DIR}/tests/CaseFullElab/top.sv, line:1:1, endln:42:12 |BIN:0110 |vpiTypespec: \_int_typespec: @@ -1348,7 +1348,7 @@ design: (work@FSM) |vpiParamAssign: \_param_assign: , line:9:13, endln:9:30 |vpiParent: - \_module: work@FSM (work@FSM), file:${SURELOG_DIR}/tests/CaseFullElab/top.sv, line:1:1, endln:42:12 + \_module_inst: work@FSM (work@FSM), file:${SURELOG_DIR}/tests/CaseFullElab/top.sv, line:1:1, endln:42:12 |vpiRhs: \_constant: , line:9:23, endln:9:30 |vpiDecompile:4'b0000 @@ -1362,7 +1362,7 @@ design: (work@FSM) |vpiParamAssign: \_param_assign: , line:10:13, endln:10:30 |vpiParent: - \_module: work@FSM (work@FSM), file:${SURELOG_DIR}/tests/CaseFullElab/top.sv, line:1:1, endln:42:12 + \_module_inst: work@FSM (work@FSM), file:${SURELOG_DIR}/tests/CaseFullElab/top.sv, line:1:1, endln:42:12 |vpiRhs: \_constant: , line:10:23, endln:10:30 |vpiDecompile:4'b0001 @@ -1376,7 +1376,7 @@ design: (work@FSM) |vpiParamAssign: \_param_assign: , line:11:13, endln:11:30 |vpiParent: - \_module: work@FSM (work@FSM), file:${SURELOG_DIR}/tests/CaseFullElab/top.sv, line:1:1, endln:42:12 + \_module_inst: work@FSM (work@FSM), file:${SURELOG_DIR}/tests/CaseFullElab/top.sv, line:1:1, endln:42:12 |vpiRhs: \_constant: , line:11:23, endln:11:30 |vpiDecompile:4'b0010 @@ -1390,7 +1390,7 @@ design: (work@FSM) |vpiParamAssign: \_param_assign: , line:12:13, endln:12:30 |vpiParent: - \_module: work@FSM (work@FSM), file:${SURELOG_DIR}/tests/CaseFullElab/top.sv, line:1:1, endln:42:12 + \_module_inst: work@FSM (work@FSM), file:${SURELOG_DIR}/tests/CaseFullElab/top.sv, line:1:1, endln:42:12 |vpiRhs: \_constant: , line:12:23, endln:12:30 |vpiDecompile:4'b0011 @@ -1404,7 +1404,7 @@ design: (work@FSM) |vpiParamAssign: \_param_assign: , line:13:13, endln:13:30 |vpiParent: - \_module: work@FSM (work@FSM), file:${SURELOG_DIR}/tests/CaseFullElab/top.sv, line:1:1, endln:42:12 + \_module_inst: work@FSM (work@FSM), file:${SURELOG_DIR}/tests/CaseFullElab/top.sv, line:1:1, endln:42:12 |vpiRhs: \_constant: , line:13:23, endln:13:30 |vpiDecompile:4'b0100 @@ -1418,7 +1418,7 @@ design: (work@FSM) |vpiParamAssign: \_param_assign: , line:14:13, endln:14:30 |vpiParent: - \_module: work@FSM (work@FSM), file:${SURELOG_DIR}/tests/CaseFullElab/top.sv, line:1:1, endln:42:12 + \_module_inst: work@FSM (work@FSM), file:${SURELOG_DIR}/tests/CaseFullElab/top.sv, line:1:1, endln:42:12 |vpiRhs: \_constant: , line:14:23, endln:14:30 |vpiDecompile:4'b0101 @@ -1432,7 +1432,7 @@ design: (work@FSM) |vpiParamAssign: \_param_assign: , line:15:13, endln:15:30 |vpiParent: - \_module: work@FSM (work@FSM), file:${SURELOG_DIR}/tests/CaseFullElab/top.sv, line:1:1, endln:42:12 + \_module_inst: work@FSM (work@FSM), file:${SURELOG_DIR}/tests/CaseFullElab/top.sv, line:1:1, endln:42:12 |vpiRhs: \_constant: , line:15:23, endln:15:30 |vpiDecompile:4'b0110 @@ -1447,63 +1447,63 @@ design: (work@FSM) |vpiNet: \_logic_net: (work@FSM.clock), line:3:8, endln:3:13 |vpiParent: - \_module: work@FSM (work@FSM), file:${SURELOG_DIR}/tests/CaseFullElab/top.sv, line:1:1, endln:42:12 + \_module_inst: work@FSM (work@FSM), file:${SURELOG_DIR}/tests/CaseFullElab/top.sv, line:1:1, endln:42:12 |vpiName:clock |vpiFullName:work@FSM.clock |vpiNetType:1 |vpiNet: \_logic_net: (work@FSM.keys), line:3:15, endln:3:19 |vpiParent: - \_module: work@FSM (work@FSM), file:${SURELOG_DIR}/tests/CaseFullElab/top.sv, line:1:1, endln:42:12 + \_module_inst: work@FSM (work@FSM), file:${SURELOG_DIR}/tests/CaseFullElab/top.sv, line:1:1, endln:42:12 |vpiName:keys |vpiFullName:work@FSM.keys |vpiNetType:1 |vpiNet: \_logic_net: (work@FSM.brake), line:3:21, endln:3:26 |vpiParent: - \_module: work@FSM (work@FSM), file:${SURELOG_DIR}/tests/CaseFullElab/top.sv, line:1:1, endln:42:12 + \_module_inst: work@FSM (work@FSM), file:${SURELOG_DIR}/tests/CaseFullElab/top.sv, line:1:1, endln:42:12 |vpiName:brake |vpiFullName:work@FSM.brake |vpiNetType:1 |vpiNet: \_logic_net: (work@FSM.accelerate), line:3:28, endln:3:38 |vpiParent: - \_module: work@FSM (work@FSM), file:${SURELOG_DIR}/tests/CaseFullElab/top.sv, line:1:1, endln:42:12 + \_module_inst: work@FSM (work@FSM), file:${SURELOG_DIR}/tests/CaseFullElab/top.sv, line:1:1, endln:42:12 |vpiName:accelerate |vpiFullName:work@FSM.accelerate |vpiNetType:1 |vpiNet: \_logic_net: (work@FSM.Speed), line:5:13, endln:5:18 |vpiParent: - \_module: work@FSM (work@FSM), file:${SURELOG_DIR}/tests/CaseFullElab/top.sv, line:1:1, endln:42:12 + \_module_inst: work@FSM (work@FSM), file:${SURELOG_DIR}/tests/CaseFullElab/top.sv, line:1:1, endln:42:12 |vpiName:Speed |vpiFullName:work@FSM.Speed |vpiNetType:48 |vpiNet: \_logic_net: (work@FSM.Ctrl1), line:7:7, endln:7:12 |vpiParent: - \_module: work@FSM (work@FSM), file:${SURELOG_DIR}/tests/CaseFullElab/top.sv, line:1:1, endln:42:12 + \_module_inst: work@FSM (work@FSM), file:${SURELOG_DIR}/tests/CaseFullElab/top.sv, line:1:1, endln:42:12 |vpiName:Ctrl1 |vpiFullName:work@FSM.Ctrl1 |vpiNetType:48 |vpiNet: \_logic_net: (work@FSM.Ctrl2), line:7:14, endln:7:19 |vpiParent: - \_module: work@FSM (work@FSM), file:${SURELOG_DIR}/tests/CaseFullElab/top.sv, line:1:1, endln:42:12 + \_module_inst: work@FSM (work@FSM), file:${SURELOG_DIR}/tests/CaseFullElab/top.sv, line:1:1, endln:42:12 |vpiName:Ctrl2 |vpiFullName:work@FSM.Ctrl2 |vpiNetType:48 |vpiNet: \_logic_net: (work@FSM.Ctrl3), line:7:21, endln:7:26 |vpiParent: - \_module: work@FSM (work@FSM), file:${SURELOG_DIR}/tests/CaseFullElab/top.sv, line:1:1, endln:42:12 + \_module_inst: work@FSM (work@FSM), file:${SURELOG_DIR}/tests/CaseFullElab/top.sv, line:1:1, endln:42:12 |vpiName:Ctrl3 |vpiFullName:work@FSM.Ctrl3 |vpiNetType:48 |vpiPort: \_port: (clock), line:1:12, endln:1:17 |vpiParent: - \_module: work@FSM (work@FSM), file:${SURELOG_DIR}/tests/CaseFullElab/top.sv, line:1:1, endln:42:12 + \_module_inst: work@FSM (work@FSM), file:${SURELOG_DIR}/tests/CaseFullElab/top.sv, line:1:1, endln:42:12 |vpiName:clock |vpiDirection:1 |vpiLowConn: @@ -1515,7 +1515,7 @@ design: (work@FSM) |vpiPort: \_port: (keys), line:1:19, endln:1:23 |vpiParent: - \_module: work@FSM (work@FSM), file:${SURELOG_DIR}/tests/CaseFullElab/top.sv, line:1:1, endln:42:12 + \_module_inst: work@FSM (work@FSM), file:${SURELOG_DIR}/tests/CaseFullElab/top.sv, line:1:1, endln:42:12 |vpiName:keys |vpiDirection:1 |vpiLowConn: @@ -1527,7 +1527,7 @@ design: (work@FSM) |vpiPort: \_port: (brake), line:1:25, endln:1:30 |vpiParent: - \_module: work@FSM (work@FSM), file:${SURELOG_DIR}/tests/CaseFullElab/top.sv, line:1:1, endln:42:12 + \_module_inst: work@FSM (work@FSM), file:${SURELOG_DIR}/tests/CaseFullElab/top.sv, line:1:1, endln:42:12 |vpiName:brake |vpiDirection:1 |vpiLowConn: @@ -1539,7 +1539,7 @@ design: (work@FSM) |vpiPort: \_port: (accelerate), line:1:32, endln:1:42 |vpiParent: - \_module: work@FSM (work@FSM), file:${SURELOG_DIR}/tests/CaseFullElab/top.sv, line:1:1, endln:42:12 + \_module_inst: work@FSM (work@FSM), file:${SURELOG_DIR}/tests/CaseFullElab/top.sv, line:1:1, endln:42:12 |vpiName:accelerate |vpiDirection:1 |vpiLowConn: @@ -1551,7 +1551,7 @@ design: (work@FSM) |vpiPort: \_port: (Speed), line:1:44, endln:1:49 |vpiParent: - \_module: work@FSM (work@FSM), file:${SURELOG_DIR}/tests/CaseFullElab/top.sv, line:1:1, endln:42:12 + \_module_inst: work@FSM (work@FSM), file:${SURELOG_DIR}/tests/CaseFullElab/top.sv, line:1:1, endln:42:12 |vpiName:Speed |vpiDirection:2 |vpiLowConn: @@ -1581,7 +1581,7 @@ design: (work@FSM) |vpiProcess: \_always: , line:17:3, endln:40:6 |vpiParent: - \_module: work@FSM (work@FSM), file:${SURELOG_DIR}/tests/CaseFullElab/top.sv, line:1:1, endln:42:12 + \_module_inst: work@FSM (work@FSM), file:${SURELOG_DIR}/tests/CaseFullElab/top.sv, line:1:1, endln:42:12 |vpiStmt: \_event_control: , line:17:10, endln:17:42 |vpiParent: @@ -1846,12 +1846,12 @@ design: (work@FSM) \_logic_net: (work@FSM.Speed), line:5:13, endln:5:18 |vpiAlwaysType:1 |uhdmtopModules: -\_module: work@FSM (work@FSM), file:${SURELOG_DIR}/tests/CaseFullElab/top.sv, line:1:1, endln:42:12 +\_module_inst: work@FSM (work@FSM), file:${SURELOG_DIR}/tests/CaseFullElab/top.sv, line:1:1, endln:42:12 |vpiName:work@FSM |vpiParameter: \_parameter: (work@FSM.Stop), line:9:13, endln:9:17 |vpiParent: - \_module: work@FSM (work@FSM), file:${SURELOG_DIR}/tests/CaseFullElab/top.sv, line:1:1, endln:42:12 + \_module_inst: work@FSM (work@FSM), file:${SURELOG_DIR}/tests/CaseFullElab/top.sv, line:1:1, endln:42:12 |BIN:0000 |vpiTypespec: \_int_typespec: @@ -1876,7 +1876,7 @@ design: (work@FSM) |vpiParameter: \_parameter: (work@FSM.Move), line:10:13, endln:10:17 |vpiParent: - \_module: work@FSM (work@FSM), file:${SURELOG_DIR}/tests/CaseFullElab/top.sv, line:1:1, endln:42:12 + \_module_inst: work@FSM (work@FSM), file:${SURELOG_DIR}/tests/CaseFullElab/top.sv, line:1:1, endln:42:12 |BIN:0001 |vpiTypespec: \_int_typespec: @@ -1901,7 +1901,7 @@ design: (work@FSM) |vpiParameter: \_parameter: (work@FSM.Turn), line:11:13, endln:11:17 |vpiParent: - \_module: work@FSM (work@FSM), file:${SURELOG_DIR}/tests/CaseFullElab/top.sv, line:1:1, endln:42:12 + \_module_inst: work@FSM (work@FSM), file:${SURELOG_DIR}/tests/CaseFullElab/top.sv, line:1:1, endln:42:12 |BIN:0010 |vpiTypespec: \_int_typespec: @@ -1926,7 +1926,7 @@ design: (work@FSM) |vpiParameter: \_parameter: (work@FSM.Slow), line:12:13, endln:12:17 |vpiParent: - \_module: work@FSM (work@FSM), file:${SURELOG_DIR}/tests/CaseFullElab/top.sv, line:1:1, endln:42:12 + \_module_inst: work@FSM (work@FSM), file:${SURELOG_DIR}/tests/CaseFullElab/top.sv, line:1:1, endln:42:12 |BIN:0011 |vpiTypespec: \_int_typespec: @@ -1951,7 +1951,7 @@ design: (work@FSM) |vpiParameter: \_parameter: (work@FSM.Medium), line:13:13, endln:13:19 |vpiParent: - \_module: work@FSM (work@FSM), file:${SURELOG_DIR}/tests/CaseFullElab/top.sv, line:1:1, endln:42:12 + \_module_inst: work@FSM (work@FSM), file:${SURELOG_DIR}/tests/CaseFullElab/top.sv, line:1:1, endln:42:12 |BIN:0100 |vpiTypespec: \_int_typespec: @@ -1976,7 +1976,7 @@ design: (work@FSM) |vpiParameter: \_parameter: (work@FSM.Fast), line:14:13, endln:14:17 |vpiParent: - \_module: work@FSM (work@FSM), file:${SURELOG_DIR}/tests/CaseFullElab/top.sv, line:1:1, endln:42:12 + \_module_inst: work@FSM (work@FSM), file:${SURELOG_DIR}/tests/CaseFullElab/top.sv, line:1:1, endln:42:12 |BIN:0101 |vpiTypespec: \_int_typespec: @@ -2001,7 +2001,7 @@ design: (work@FSM) |vpiParameter: \_parameter: (work@FSM.Faster), line:15:13, endln:15:19 |vpiParent: - \_module: work@FSM (work@FSM), file:${SURELOG_DIR}/tests/CaseFullElab/top.sv, line:1:1, endln:42:12 + \_module_inst: work@FSM (work@FSM), file:${SURELOG_DIR}/tests/CaseFullElab/top.sv, line:1:1, endln:42:12 |BIN:0110 |vpiTypespec: \_int_typespec: @@ -2026,7 +2026,7 @@ design: (work@FSM) |vpiParamAssign: \_param_assign: , line:9:13, endln:9:30 |vpiParent: - \_module: work@FSM (work@FSM), file:${SURELOG_DIR}/tests/CaseFullElab/top.sv, line:1:1, endln:42:12 + \_module_inst: work@FSM (work@FSM), file:${SURELOG_DIR}/tests/CaseFullElab/top.sv, line:1:1, endln:42:12 |vpiRhs: \_constant: , line:9:23, endln:9:30 |vpiDecompile:4'b0000 @@ -2040,7 +2040,7 @@ design: (work@FSM) |vpiParamAssign: \_param_assign: , line:10:13, endln:10:30 |vpiParent: - \_module: work@FSM (work@FSM), file:${SURELOG_DIR}/tests/CaseFullElab/top.sv, line:1:1, endln:42:12 + \_module_inst: work@FSM (work@FSM), file:${SURELOG_DIR}/tests/CaseFullElab/top.sv, line:1:1, endln:42:12 |vpiRhs: \_constant: , line:10:23, endln:10:30 |vpiDecompile:4'b0001 @@ -2054,7 +2054,7 @@ design: (work@FSM) |vpiParamAssign: \_param_assign: , line:11:13, endln:11:30 |vpiParent: - \_module: work@FSM (work@FSM), file:${SURELOG_DIR}/tests/CaseFullElab/top.sv, line:1:1, endln:42:12 + \_module_inst: work@FSM (work@FSM), file:${SURELOG_DIR}/tests/CaseFullElab/top.sv, line:1:1, endln:42:12 |vpiRhs: \_constant: , line:11:23, endln:11:30 |vpiDecompile:4'b0010 @@ -2068,7 +2068,7 @@ design: (work@FSM) |vpiParamAssign: \_param_assign: , line:12:13, endln:12:30 |vpiParent: - \_module: work@FSM (work@FSM), file:${SURELOG_DIR}/tests/CaseFullElab/top.sv, line:1:1, endln:42:12 + \_module_inst: work@FSM (work@FSM), file:${SURELOG_DIR}/tests/CaseFullElab/top.sv, line:1:1, endln:42:12 |vpiRhs: \_constant: , line:12:23, endln:12:30 |vpiDecompile:4'b0011 @@ -2082,7 +2082,7 @@ design: (work@FSM) |vpiParamAssign: \_param_assign: , line:13:13, endln:13:30 |vpiParent: - \_module: work@FSM (work@FSM), file:${SURELOG_DIR}/tests/CaseFullElab/top.sv, line:1:1, endln:42:12 + \_module_inst: work@FSM (work@FSM), file:${SURELOG_DIR}/tests/CaseFullElab/top.sv, line:1:1, endln:42:12 |vpiRhs: \_constant: , line:13:23, endln:13:30 |vpiDecompile:4'b0100 @@ -2096,7 +2096,7 @@ design: (work@FSM) |vpiParamAssign: \_param_assign: , line:14:13, endln:14:30 |vpiParent: - \_module: work@FSM (work@FSM), file:${SURELOG_DIR}/tests/CaseFullElab/top.sv, line:1:1, endln:42:12 + \_module_inst: work@FSM (work@FSM), file:${SURELOG_DIR}/tests/CaseFullElab/top.sv, line:1:1, endln:42:12 |vpiRhs: \_constant: , line:14:23, endln:14:30 |vpiDecompile:4'b0101 @@ -2110,7 +2110,7 @@ design: (work@FSM) |vpiParamAssign: \_param_assign: , line:15:13, endln:15:30 |vpiParent: - \_module: work@FSM (work@FSM), file:${SURELOG_DIR}/tests/CaseFullElab/top.sv, line:1:1, endln:42:12 + \_module_inst: work@FSM (work@FSM), file:${SURELOG_DIR}/tests/CaseFullElab/top.sv, line:1:1, endln:42:12 |vpiRhs: \_constant: , line:15:23, endln:15:30 |vpiDecompile:4'b0110 @@ -2126,7 +2126,7 @@ design: (work@FSM) |vpiNet: \_logic_net: (work@FSM.clock), line:3:8, endln:3:13 |vpiParent: - \_module: work@FSM (work@FSM), file:${SURELOG_DIR}/tests/CaseFullElab/top.sv, line:1:1, endln:42:12 + \_module_inst: work@FSM (work@FSM), file:${SURELOG_DIR}/tests/CaseFullElab/top.sv, line:1:1, endln:42:12 |vpiTypespec: \_logic_typespec: , line:3:3, endln:3:7 |vpiName:clock @@ -2135,7 +2135,7 @@ design: (work@FSM) |vpiNet: \_logic_net: (work@FSM.keys), line:3:15, endln:3:19 |vpiParent: - \_module: work@FSM (work@FSM), file:${SURELOG_DIR}/tests/CaseFullElab/top.sv, line:1:1, endln:42:12 + \_module_inst: work@FSM (work@FSM), file:${SURELOG_DIR}/tests/CaseFullElab/top.sv, line:1:1, endln:42:12 |vpiTypespec: \_logic_typespec: , line:3:3, endln:3:7 |vpiName:keys @@ -2144,7 +2144,7 @@ design: (work@FSM) |vpiNet: \_logic_net: (work@FSM.brake), line:3:21, endln:3:26 |vpiParent: - \_module: work@FSM (work@FSM), file:${SURELOG_DIR}/tests/CaseFullElab/top.sv, line:1:1, endln:42:12 + \_module_inst: work@FSM (work@FSM), file:${SURELOG_DIR}/tests/CaseFullElab/top.sv, line:1:1, endln:42:12 |vpiTypespec: \_logic_typespec: , line:3:3, endln:3:7 |vpiName:brake @@ -2153,7 +2153,7 @@ design: (work@FSM) |vpiNet: \_logic_net: (work@FSM.accelerate), line:3:28, endln:3:38 |vpiParent: - \_module: work@FSM (work@FSM), file:${SURELOG_DIR}/tests/CaseFullElab/top.sv, line:1:1, endln:42:12 + \_module_inst: work@FSM (work@FSM), file:${SURELOG_DIR}/tests/CaseFullElab/top.sv, line:1:1, endln:42:12 |vpiTypespec: \_logic_typespec: , line:3:3, endln:3:7 |vpiName:accelerate @@ -2162,7 +2162,7 @@ design: (work@FSM) |vpiNet: \_logic_net: (work@FSM.Speed), line:5:13, endln:5:18 |vpiParent: - \_module: work@FSM (work@FSM), file:${SURELOG_DIR}/tests/CaseFullElab/top.sv, line:1:1, endln:42:12 + \_module_inst: work@FSM (work@FSM), file:${SURELOG_DIR}/tests/CaseFullElab/top.sv, line:1:1, endln:42:12 |vpiTypespec: \_logic_typespec: , line:5:3, endln:5:12 |vpiRange: @@ -2189,7 +2189,7 @@ design: (work@FSM) |vpiNet: \_logic_net: (work@FSM.Ctrl1), line:7:7, endln:7:12 |vpiParent: - \_module: work@FSM (work@FSM), file:${SURELOG_DIR}/tests/CaseFullElab/top.sv, line:1:1, endln:42:12 + \_module_inst: work@FSM (work@FSM), file:${SURELOG_DIR}/tests/CaseFullElab/top.sv, line:1:1, endln:42:12 |vpiTypespec: \_logic_typespec: , line:7:3, endln:7:6 |vpiName:Ctrl1 @@ -2198,7 +2198,7 @@ design: (work@FSM) |vpiNet: \_logic_net: (work@FSM.Ctrl2), line:7:14, endln:7:19 |vpiParent: - \_module: work@FSM (work@FSM), file:${SURELOG_DIR}/tests/CaseFullElab/top.sv, line:1:1, endln:42:12 + \_module_inst: work@FSM (work@FSM), file:${SURELOG_DIR}/tests/CaseFullElab/top.sv, line:1:1, endln:42:12 |vpiTypespec: \_logic_typespec: , line:7:3, endln:7:6 |vpiName:Ctrl2 @@ -2207,7 +2207,7 @@ design: (work@FSM) |vpiNet: \_logic_net: (work@FSM.Ctrl3), line:7:21, endln:7:26 |vpiParent: - \_module: work@FSM (work@FSM), file:${SURELOG_DIR}/tests/CaseFullElab/top.sv, line:1:1, endln:42:12 + \_module_inst: work@FSM (work@FSM), file:${SURELOG_DIR}/tests/CaseFullElab/top.sv, line:1:1, endln:42:12 |vpiTypespec: \_logic_typespec: , line:7:3, endln:7:6 |vpiName:Ctrl3 @@ -2217,7 +2217,7 @@ design: (work@FSM) |vpiPort: \_port: (clock), line:1:12, endln:1:17 |vpiParent: - \_module: work@FSM (work@FSM), file:${SURELOG_DIR}/tests/CaseFullElab/top.sv, line:1:1, endln:42:12 + \_module_inst: work@FSM (work@FSM), file:${SURELOG_DIR}/tests/CaseFullElab/top.sv, line:1:1, endln:42:12 |vpiName:clock |vpiDirection:1 |vpiLowConn: @@ -2231,11 +2231,11 @@ design: (work@FSM) |vpiTypedef: \_logic_typespec: , line:2:9, endln:2:9 |vpiInstance: - \_module: work@FSM (work@FSM), file:${SURELOG_DIR}/tests/CaseFullElab/top.sv, line:1:1, endln:42:12 + \_module_inst: work@FSM (work@FSM), file:${SURELOG_DIR}/tests/CaseFullElab/top.sv, line:1:1, endln:42:12 |vpiPort: \_port: (keys), line:1:19, endln:1:23 |vpiParent: - \_module: work@FSM (work@FSM), file:${SURELOG_DIR}/tests/CaseFullElab/top.sv, line:1:1, endln:42:12 + \_module_inst: work@FSM (work@FSM), file:${SURELOG_DIR}/tests/CaseFullElab/top.sv, line:1:1, endln:42:12 |vpiName:keys |vpiDirection:1 |vpiLowConn: @@ -2249,11 +2249,11 @@ design: (work@FSM) |vpiTypedef: \_logic_typespec: , line:2:9, endln:2:9 |vpiInstance: - \_module: work@FSM (work@FSM), file:${SURELOG_DIR}/tests/CaseFullElab/top.sv, line:1:1, endln:42:12 + \_module_inst: work@FSM (work@FSM), file:${SURELOG_DIR}/tests/CaseFullElab/top.sv, line:1:1, endln:42:12 |vpiPort: \_port: (brake), line:1:25, endln:1:30 |vpiParent: - \_module: work@FSM (work@FSM), file:${SURELOG_DIR}/tests/CaseFullElab/top.sv, line:1:1, endln:42:12 + \_module_inst: work@FSM (work@FSM), file:${SURELOG_DIR}/tests/CaseFullElab/top.sv, line:1:1, endln:42:12 |vpiName:brake |vpiDirection:1 |vpiLowConn: @@ -2267,11 +2267,11 @@ design: (work@FSM) |vpiTypedef: \_logic_typespec: , line:2:9, endln:2:9 |vpiInstance: - \_module: work@FSM (work@FSM), file:${SURELOG_DIR}/tests/CaseFullElab/top.sv, line:1:1, endln:42:12 + \_module_inst: work@FSM (work@FSM), file:${SURELOG_DIR}/tests/CaseFullElab/top.sv, line:1:1, endln:42:12 |vpiPort: \_port: (accelerate), line:1:32, endln:1:42 |vpiParent: - \_module: work@FSM (work@FSM), file:${SURELOG_DIR}/tests/CaseFullElab/top.sv, line:1:1, endln:42:12 + \_module_inst: work@FSM (work@FSM), file:${SURELOG_DIR}/tests/CaseFullElab/top.sv, line:1:1, endln:42:12 |vpiName:accelerate |vpiDirection:1 |vpiLowConn: @@ -2285,11 +2285,11 @@ design: (work@FSM) |vpiTypedef: \_logic_typespec: , line:2:9, endln:2:9 |vpiInstance: - \_module: work@FSM (work@FSM), file:${SURELOG_DIR}/tests/CaseFullElab/top.sv, line:1:1, endln:42:12 + \_module_inst: work@FSM (work@FSM), file:${SURELOG_DIR}/tests/CaseFullElab/top.sv, line:1:1, endln:42:12 |vpiPort: \_port: (Speed), line:1:44, endln:1:49 |vpiParent: - \_module: work@FSM (work@FSM), file:${SURELOG_DIR}/tests/CaseFullElab/top.sv, line:1:1, endln:42:12 + \_module_inst: work@FSM (work@FSM), file:${SURELOG_DIR}/tests/CaseFullElab/top.sv, line:1:1, endln:42:12 |vpiName:Speed |vpiDirection:2 |vpiLowConn: @@ -2323,11 +2323,11 @@ design: (work@FSM) |UINT:0 |vpiConstType:9 |vpiInstance: - \_module: work@FSM (work@FSM), file:${SURELOG_DIR}/tests/CaseFullElab/top.sv, line:1:1, endln:42:12 + \_module_inst: work@FSM (work@FSM), file:${SURELOG_DIR}/tests/CaseFullElab/top.sv, line:1:1, endln:42:12 |vpiProcess: \_always: , line:17:3, endln:40:6 |vpiParent: - \_module: work@FSM (work@FSM), file:${SURELOG_DIR}/tests/CaseFullElab/top.sv, line:1:1, endln:42:12 + \_module_inst: work@FSM (work@FSM), file:${SURELOG_DIR}/tests/CaseFullElab/top.sv, line:1:1, endln:42:12 |vpiStmt: \_event_control: , line:17:10, endln:17:42 |vpiParent: diff --git a/tests/CaseInside/CaseInside.log b/tests/CaseInside/CaseInside.log index 14d11e913f..58e98ca56d 100644 --- a/tests/CaseInside/CaseInside.log +++ b/tests/CaseInside/CaseInside.log @@ -468,7 +468,7 @@ io_decl 11 logic_net 2 logic_typespec 2 logic_var 1 -module 4 +module_inst 4 named_begin 1 operation 5 package 5 @@ -504,7 +504,7 @@ io_decl 22 logic_net 2 logic_typespec 2 logic_var 1 -module 4 +module_inst 4 named_begin 2 operation 10 package 5 @@ -1111,7 +1111,7 @@ design: (work@dm_csrs) \_int_typespec: |vpiSigned:1 |uhdmallModules: -\_module: work@dm_csrs (work@dm_csrs), file:${SURELOG_DIR}/tests/CaseInside/top.sv, line:12:1, endln:29:20 +\_module_inst: work@dm_csrs (work@dm_csrs), file:${SURELOG_DIR}/tests/CaseInside/top.sv, line:12:1, endln:29:20 |vpiParent: \_design: (work@dm_csrs) |vpiFullName:work@dm_csrs @@ -1119,7 +1119,7 @@ design: (work@dm_csrs) |vpiProcess: \_always: , line:13:3, endln:28:6 |vpiParent: - \_module: work@dm_csrs (work@dm_csrs), file:${SURELOG_DIR}/tests/CaseInside/top.sv, line:12:1, endln:29:20 + \_module_inst: work@dm_csrs (work@dm_csrs), file:${SURELOG_DIR}/tests/CaseInside/top.sv, line:12:1, endln:29:20 |vpiStmt: \_named_begin: (work@dm_csrs.csr_read_write), line:13:15, endln:28:6 |vpiParent: @@ -1255,7 +1255,7 @@ design: (work@dm_csrs) \_case_stmt: , line:15:7, endln:26:14 |vpiAlwaysType:2 |uhdmtopModules: -\_module: work@dm_csrs (work@dm_csrs), file:${SURELOG_DIR}/tests/CaseInside/top.sv, line:12:1, endln:29:20 +\_module_inst: work@dm_csrs (work@dm_csrs), file:${SURELOG_DIR}/tests/CaseInside/top.sv, line:12:1, endln:29:20 |vpiName:work@dm_csrs |vpiDefName:work@dm_csrs |vpiTop:1 @@ -1271,7 +1271,7 @@ design: (work@dm_csrs) |vpiProcess: \_always: , line:13:3, endln:28:6 |vpiParent: - \_module: work@dm_csrs (work@dm_csrs), file:${SURELOG_DIR}/tests/CaseInside/top.sv, line:12:1, endln:29:20 + \_module_inst: work@dm_csrs (work@dm_csrs), file:${SURELOG_DIR}/tests/CaseInside/top.sv, line:12:1, endln:29:20 |vpiStmt: \_named_begin: (work@dm_csrs.csr_read_write), line:13:15, endln:28:6 |vpiParent: diff --git a/tests/CastEnum/CastEnum.log b/tests/CastEnum/CastEnum.log index c54ef1e885..16c507cae8 100644 --- a/tests/CastEnum/CastEnum.log +++ b/tests/CastEnum/CastEnum.log @@ -398,7 +398,7 @@ io_decl 11 logic_net 1 logic_typespec 3 logic_var 1 -module 4 +module_inst 4 operation 2 package 5 range 3 @@ -425,7 +425,7 @@ io_decl 22 logic_net 1 logic_typespec 3 logic_var 1 -module 4 +module_inst 4 operation 3 package 5 range 3 @@ -1031,7 +1031,7 @@ design: (work@dm_csrs) \_int_typespec: |vpiSigned:1 |uhdmallModules: -\_module: work@dm_csrs (work@dm_csrs), file:${SURELOG_DIR}/tests/CastEnum/dut.sv, line:12:1, endln:17:10 +\_module_inst: work@dm_csrs (work@dm_csrs), file:${SURELOG_DIR}/tests/CastEnum/dut.sv, line:12:1, endln:17:10 |vpiParent: \_design: (work@dm_csrs) |vpiFullName:work@dm_csrs @@ -1039,13 +1039,13 @@ design: (work@dm_csrs) |vpiNet: \_logic_net: (work@dm_csrs.dtm_op), line:14:16, endln:14:22 |vpiParent: - \_module: work@dm_csrs (work@dm_csrs), file:${SURELOG_DIR}/tests/CastEnum/dut.sv, line:12:1, endln:17:10 + \_module_inst: work@dm_csrs (work@dm_csrs), file:${SURELOG_DIR}/tests/CastEnum/dut.sv, line:12:1, endln:17:10 |vpiName:dtm_op |vpiFullName:work@dm_csrs.dtm_op |vpiContAssign: \_cont_assign: , line:15:10, endln:15:46 |vpiParent: - \_module: work@dm_csrs (work@dm_csrs), file:${SURELOG_DIR}/tests/CastEnum/dut.sv, line:12:1, endln:17:10 + \_module_inst: work@dm_csrs (work@dm_csrs), file:${SURELOG_DIR}/tests/CastEnum/dut.sv, line:12:1, endln:17:10 |vpiRhs: \_operation: , line:15:19, endln:15:46 |vpiParent: @@ -1075,12 +1075,12 @@ design: (work@dm_csrs) |vpiActual: \_enum_var: (work@dm_csrs.dtm_op), line:14:16, endln:14:22 |uhdmtopModules: -\_module: work@dm_csrs (work@dm_csrs), file:${SURELOG_DIR}/tests/CastEnum/dut.sv, line:12:1, endln:17:10 +\_module_inst: work@dm_csrs (work@dm_csrs), file:${SURELOG_DIR}/tests/CastEnum/dut.sv, line:12:1, endln:17:10 |vpiName:work@dm_csrs |vpiVariables: \_enum_var: (work@dm_csrs.dtm_op), line:14:16, endln:14:22 |vpiParent: - \_module: work@dm_csrs (work@dm_csrs), file:${SURELOG_DIR}/tests/CastEnum/dut.sv, line:12:1, endln:17:10 + \_module_inst: work@dm_csrs (work@dm_csrs), file:${SURELOG_DIR}/tests/CastEnum/dut.sv, line:12:1, endln:17:10 |vpiTypespec: \_enum_typespec: (dm::dtm_op_e), line:3:1, endln:7:12 |vpiName:dtm_op @@ -1092,7 +1092,7 @@ design: (work@dm_csrs) |vpiContAssign: \_cont_assign: , line:15:10, endln:15:46 |vpiParent: - \_module: work@dm_csrs (work@dm_csrs), file:${SURELOG_DIR}/tests/CastEnum/dut.sv, line:12:1, endln:17:10 + \_module_inst: work@dm_csrs (work@dm_csrs), file:${SURELOG_DIR}/tests/CastEnum/dut.sv, line:12:1, endln:17:10 |vpiRhs: \_operation: , line:15:19, endln:15:46 |vpiParent: diff --git a/tests/CastPartSelect/CastPartSelect.log b/tests/CastPartSelect/CastPartSelect.log index 6afa3085e5..7763b82a88 100644 --- a/tests/CastPartSelect/CastPartSelect.log +++ b/tests/CastPartSelect/CastPartSelect.log @@ -393,7 +393,7 @@ io_decl 11 logic_net 4 logic_typespec 3 logic_var 1 -module 3 +module_inst 3 named_begin 1 operation 2 package 2 @@ -427,7 +427,7 @@ io_decl 22 logic_net 4 logic_typespec 3 logic_var 1 -module 3 +module_inst 3 named_begin 2 operation 4 package 2 @@ -925,7 +925,7 @@ design: (work@top) \_int_typespec: |vpiSigned:1 |uhdmallModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/CastPartSelect/dut.sv, line:1:1, endln:10:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/CastPartSelect/dut.sv, line:1:1, endln:10:10 |vpiParent: \_design: (work@top) |vpiFullName:work@top @@ -933,14 +933,14 @@ design: (work@top) |vpiNet: \_logic_net: (work@top.instr_rdata_i), line:1:32, endln:1:45 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/CastPartSelect/dut.sv, line:1:1, endln:10:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/CastPartSelect/dut.sv, line:1:1, endln:10:10 |vpiName:instr_rdata_i |vpiFullName:work@top.instr_rdata_i |vpiNetType:36 |vpiPort: \_port: (instr_rdata_i), line:1:32, endln:1:45 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/CastPartSelect/dut.sv, line:1:1, endln:10:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/CastPartSelect/dut.sv, line:1:1, endln:10:10 |vpiName:instr_rdata_i |vpiDirection:1 |vpiLowConn: @@ -970,7 +970,7 @@ design: (work@top) |vpiProcess: \_always: , line:3:2, endln:8:5 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/CastPartSelect/dut.sv, line:1:1, endln:10:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/CastPartSelect/dut.sv, line:1:1, endln:10:10 |vpiStmt: \_named_begin: (work@top.csr_pipeline_flushes), line:3:14, endln:8:5 |vpiParent: @@ -1053,14 +1053,14 @@ design: (work@top) \_logic_net: (csr_pipe_flush) |vpiAlwaysType:2 |uhdmtopModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/CastPartSelect/dut.sv, line:1:1, endln:10:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/CastPartSelect/dut.sv, line:1:1, endln:10:10 |vpiName:work@top |vpiDefName:work@top |vpiTop:1 |vpiNet: \_logic_net: (work@top.instr_rdata_i), line:1:32, endln:1:45 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/CastPartSelect/dut.sv, line:1:1, endln:10:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/CastPartSelect/dut.sv, line:1:1, endln:10:10 |vpiTypespec: \_logic_typespec: , line:1:19, endln:1:31 |vpiRange: @@ -1096,7 +1096,7 @@ design: (work@top) |vpiPort: \_port: (instr_rdata_i), line:1:32, endln:1:45 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/CastPartSelect/dut.sv, line:1:1, endln:10:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/CastPartSelect/dut.sv, line:1:1, endln:10:10 |vpiName:instr_rdata_i |vpiDirection:1 |vpiLowConn: @@ -1130,11 +1130,11 @@ design: (work@top) |UINT:0 |vpiConstType:9 |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/CastPartSelect/dut.sv, line:1:1, endln:10:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/CastPartSelect/dut.sv, line:1:1, endln:10:10 |vpiProcess: \_always: , line:3:2, endln:8:5 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/CastPartSelect/dut.sv, line:1:1, endln:10:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/CastPartSelect/dut.sv, line:1:1, endln:10:10 |vpiStmt: \_named_begin: (work@top.csr_pipeline_flushes), line:3:14, endln:8:5 |vpiParent: diff --git a/tests/CastShift/CastShift.log b/tests/CastShift/CastShift.log index e942996bb3..07a07cd97a 100644 --- a/tests/CastShift/CastShift.log +++ b/tests/CastShift/CastShift.log @@ -630,7 +630,7 @@ integer_typespec 8 io_decl 11 logic_typespec 4 logic_var 1 -module 6 +module_inst 6 operation 57 package 2 param_assign 8 @@ -660,7 +660,7 @@ integer_typespec 8 io_decl 22 logic_typespec 4 logic_var 1 -module 7 +module_inst 7 operation 57 package 2 param_assign 8 @@ -1157,14 +1157,14 @@ design: (work@dut) \_int_typespec: |vpiSigned:1 |uhdmallModules: -\_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/CastShift/dut.sv, line:1:1, endln:23:10 +\_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/CastShift/dut.sv, line:1:1, endln:23:10 |vpiParent: \_design: (work@dut) |vpiFullName:work@dut |vpiParameter: \_parameter: (work@dut.CSR_MISA_MXL), line:2:24, endln:2:36 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/CastShift/dut.sv, line:1:1, endln:23:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/CastShift/dut.sv, line:1:1, endln:23:10 |DEC:1 |vpiTypespec: \_logic_typespec: , line:2:11, endln:2:22 @@ -1193,7 +1193,7 @@ design: (work@dut) |vpiParameter: \_parameter: (work@dut.RV32M), line:3:15, endln:3:20 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/CastShift/dut.sv, line:1:1, endln:23:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/CastShift/dut.sv, line:1:1, endln:23:10 |UINT:1 |vpiTypespec: \_bit_typespec: , line:3:11, endln:3:14 @@ -1205,7 +1205,7 @@ design: (work@dut) |vpiParameter: \_parameter: (work@dut.RV32E), line:4:15, endln:4:20 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/CastShift/dut.sv, line:1:1, endln:23:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/CastShift/dut.sv, line:1:1, endln:23:10 |UINT:0 |vpiTypespec: \_bit_typespec: , line:4:11, endln:4:14 @@ -1217,7 +1217,7 @@ design: (work@dut) |vpiParameter: \_parameter: (work@dut.MISA_VALUE), line:5:25, endln:5:35 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/CastShift/dut.sv, line:1:1, endln:23:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/CastShift/dut.sv, line:1:1, endln:23:10 |vpiTypespec: \_logic_typespec: , line:5:12, endln:5:24 |vpiParent: @@ -1246,7 +1246,7 @@ design: (work@dut) |vpiParamAssign: \_param_assign: , line:2:24, endln:2:43 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/CastShift/dut.sv, line:1:1, endln:23:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/CastShift/dut.sv, line:1:1, endln:23:10 |vpiRhs: \_constant: , line:2:39, endln:2:43 |vpiDecompile:2'd1 @@ -1260,7 +1260,7 @@ design: (work@dut) |vpiParamAssign: \_param_assign: , line:3:15, endln:3:31 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/CastShift/dut.sv, line:1:1, endln:23:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/CastShift/dut.sv, line:1:1, endln:23:10 |vpiRhs: \_constant: , line:3:30, endln:3:31 |vpiDecompile:1 @@ -1274,7 +1274,7 @@ design: (work@dut) |vpiParamAssign: \_param_assign: , line:4:15, endln:4:31 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/CastShift/dut.sv, line:1:1, endln:23:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/CastShift/dut.sv, line:1:1, endln:23:10 |vpiRhs: \_constant: , line:4:30, endln:4:31 |vpiDecompile:0 @@ -1288,7 +1288,7 @@ design: (work@dut) |vpiParamAssign: \_param_assign: , line:5:25, endln:17:28 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/CastShift/dut.sv, line:1:1, endln:23:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/CastShift/dut.sv, line:1:1, endln:23:10 |vpiRhs: \_operation: , line:6:3, endln:17:28 |vpiOpType:29 @@ -1623,12 +1623,12 @@ design: (work@dut) \_parameter: (work@dut.MISA_VALUE), line:5:25, endln:5:35 |vpiDefName:work@dut |uhdmtopModules: -\_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/CastShift/dut.sv, line:1:1, endln:23:10 +\_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/CastShift/dut.sv, line:1:1, endln:23:10 |vpiName:work@dut |vpiParameter: \_parameter: (work@dut.CSR_MISA_MXL), line:2:24, endln:2:36 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/CastShift/dut.sv, line:1:1, endln:23:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/CastShift/dut.sv, line:1:1, endln:23:10 |DEC:1 |vpiTypespec: \_logic_typespec: , line:2:11, endln:2:22 @@ -1659,7 +1659,7 @@ design: (work@dut) |vpiParameter: \_parameter: (work@dut.RV32M), line:3:15, endln:3:20 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/CastShift/dut.sv, line:1:1, endln:23:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/CastShift/dut.sv, line:1:1, endln:23:10 |UINT:1 |vpiTypespec: \_bit_typespec: , line:3:11, endln:3:14 @@ -1671,7 +1671,7 @@ design: (work@dut) |vpiParameter: \_parameter: (work@dut.RV32E), line:4:15, endln:4:20 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/CastShift/dut.sv, line:1:1, endln:23:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/CastShift/dut.sv, line:1:1, endln:23:10 |UINT:0 |vpiTypespec: \_bit_typespec: , line:4:11, endln:4:14 @@ -1683,7 +1683,7 @@ design: (work@dut) |vpiParameter: \_parameter: (work@dut.MISA_VALUE), line:5:25, endln:5:35 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/CastShift/dut.sv, line:1:1, endln:23:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/CastShift/dut.sv, line:1:1, endln:23:10 |vpiTypespec: \_logic_typespec: , line:5:12, endln:5:24 |vpiParent: @@ -1714,7 +1714,7 @@ design: (work@dut) |vpiParamAssign: \_param_assign: , line:2:24, endln:2:43 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/CastShift/dut.sv, line:1:1, endln:23:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/CastShift/dut.sv, line:1:1, endln:23:10 |vpiRhs: \_constant: , line:2:39, endln:2:43 |vpiDecompile:1 @@ -1728,7 +1728,7 @@ design: (work@dut) |vpiParamAssign: \_param_assign: , line:3:15, endln:3:31 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/CastShift/dut.sv, line:1:1, endln:23:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/CastShift/dut.sv, line:1:1, endln:23:10 |vpiRhs: \_constant: , line:3:30, endln:3:31 |vpiDecompile:1 @@ -1742,7 +1742,7 @@ design: (work@dut) |vpiParamAssign: \_param_assign: , line:4:15, endln:4:31 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/CastShift/dut.sv, line:1:1, endln:23:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/CastShift/dut.sv, line:1:1, endln:23:10 |vpiRhs: \_constant: , line:4:30, endln:4:31 |vpiDecompile:0 @@ -1756,7 +1756,7 @@ design: (work@dut) |vpiParamAssign: \_param_assign: , line:5:25, endln:17:28 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/CastShift/dut.sv, line:1:1, endln:23:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/CastShift/dut.sv, line:1:1, endln:23:10 |vpiRhs: \_constant: , line:6:3, endln:17:28 |vpiDecompile:1074794756 @@ -1773,7 +1773,7 @@ design: (work@dut) |vpiGenScopeArray: \_gen_scope_array: (work@dut.genblk1), line:19:1, endln:21:4 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/CastShift/dut.sv, line:1:1, endln:23:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/CastShift/dut.sv, line:1:1, endln:23:10 |vpiName:genblk1 |vpiFullName:work@dut.genblk1 |vpiGenScope: @@ -1781,8 +1781,8 @@ design: (work@dut) |vpiParent: \_gen_scope_array: (work@dut.genblk1), line:19:1, endln:21:4 |vpiFullName:work@dut.genblk1 - |vpiModule: - \_module: work@dut.genblk1::OK (work@dut.genblk1.ok), file:${SURELOG_DIR}/tests/CastShift/dut.sv, line:20:3, endln:20:11 + |vpiModuleInst: + \_module_inst: work@dut.genblk1::OK (work@dut.genblk1.ok), file:${SURELOG_DIR}/tests/CastShift/dut.sv, line:20:3, endln:20:11 |vpiParent: \_gen_scope: (work@dut.genblk1) |vpiName:ok diff --git a/tests/CastStructMember/CastStructMember.log b/tests/CastStructMember/CastStructMember.log index bea401eac2..b0bec5c540 100644 --- a/tests/CastStructMember/CastStructMember.log +++ b/tests/CastStructMember/CastStructMember.log @@ -151,7 +151,7 @@ hier_path 2 int_typespec 4 logic_net 6 logic_typespec 4 -module 3 +module_inst 3 operation 8 param_assign 2 parameter 2 @@ -170,7 +170,7 @@ hier_path 2 int_typespec 4 logic_net 6 logic_typespec 4 -module 3 +module_inst 3 operation 10 param_assign 2 parameter 2 @@ -192,14 +192,14 @@ design: (work@Foo) |vpiElaborated:1 |vpiName:work@Foo |uhdmallModules: -\_module: work@Foo (work@Foo), file:${SURELOG_DIR}/tests/CastStructMember/dut.sv, line:6:1, endln:10:10 +\_module_inst: work@Foo (work@Foo), file:${SURELOG_DIR}/tests/CastStructMember/dut.sv, line:6:1, endln:10:10 |vpiParent: \_design: (work@Foo) |vpiFullName:work@Foo |vpiParameter: \_parameter: (work@Foo.w), line:7:22, endln:7:23 |vpiParent: - \_module: work@Foo (work@Foo), file:${SURELOG_DIR}/tests/CastStructMember/dut.sv, line:6:1, endln:10:10 + \_module_inst: work@Foo (work@Foo), file:${SURELOG_DIR}/tests/CastStructMember/dut.sv, line:6:1, endln:10:10 |vpiTypespec: \_struct_typespec: (width_t), line:2:9, endln:2:15 |vpiParent: @@ -228,7 +228,7 @@ design: (work@Foo) |vpiParamAssign: \_param_assign: , line:7:22, endln:7:38 |vpiParent: - \_module: work@Foo (work@Foo), file:${SURELOG_DIR}/tests/CastStructMember/dut.sv, line:6:1, endln:10:10 + \_module_inst: work@Foo (work@Foo), file:${SURELOG_DIR}/tests/CastStructMember/dut.sv, line:6:1, endln:10:10 |vpiRhs: \_operation: , line:7:26, endln:7:38 |vpiTypespec: @@ -251,26 +251,26 @@ design: (work@Foo) |vpiNet: \_logic_net: (work@Foo.t1), line:8:15, endln:8:17 |vpiParent: - \_module: work@Foo (work@Foo), file:${SURELOG_DIR}/tests/CastStructMember/dut.sv, line:6:1, endln:10:10 + \_module_inst: work@Foo (work@Foo), file:${SURELOG_DIR}/tests/CastStructMember/dut.sv, line:6:1, endln:10:10 |vpiName:t1 |vpiFullName:work@Foo.t1 |vpiNetType:1 |vpiNet: \_logic_net: (work@Foo.t2), line:9:15, endln:9:17 |vpiParent: - \_module: work@Foo (work@Foo), file:${SURELOG_DIR}/tests/CastStructMember/dut.sv, line:6:1, endln:10:10 + \_module_inst: work@Foo (work@Foo), file:${SURELOG_DIR}/tests/CastStructMember/dut.sv, line:6:1, endln:10:10 |vpiName:t2 |vpiFullName:work@Foo.t2 |vpiNetType:1 |vpiTypedef: \_struct_typespec: (width_t), line:2:9, endln:2:15 |uhdmtopModules: -\_module: work@Foo (work@Foo), file:${SURELOG_DIR}/tests/CastStructMember/dut.sv, line:6:1, endln:10:10 +\_module_inst: work@Foo (work@Foo), file:${SURELOG_DIR}/tests/CastStructMember/dut.sv, line:6:1, endln:10:10 |vpiName:work@Foo |vpiParameter: \_parameter: (work@Foo.w), line:7:22, endln:7:23 |vpiParent: - \_module: work@Foo (work@Foo), file:${SURELOG_DIR}/tests/CastStructMember/dut.sv, line:6:1, endln:10:10 + \_module_inst: work@Foo (work@Foo), file:${SURELOG_DIR}/tests/CastStructMember/dut.sv, line:6:1, endln:10:10 |vpiTypespec: \_struct_typespec: (width_t), line:2:9, endln:2:15 |vpiParent: @@ -299,7 +299,7 @@ design: (work@Foo) |vpiParamAssign: \_param_assign: , line:7:22, endln:7:38 |vpiParent: - \_module: work@Foo (work@Foo), file:${SURELOG_DIR}/tests/CastStructMember/dut.sv, line:6:1, endln:10:10 + \_module_inst: work@Foo (work@Foo), file:${SURELOG_DIR}/tests/CastStructMember/dut.sv, line:6:1, endln:10:10 |vpiRhs: \_operation: , line:7:26, endln:7:38 |vpiTypespec: @@ -323,7 +323,7 @@ design: (work@Foo) |vpiNet: \_logic_net: (work@Foo.t1), line:8:15, endln:8:17 |vpiParent: - \_module: work@Foo (work@Foo), file:${SURELOG_DIR}/tests/CastStructMember/dut.sv, line:6:1, endln:10:10 + \_module_inst: work@Foo (work@Foo), file:${SURELOG_DIR}/tests/CastStructMember/dut.sv, line:6:1, endln:10:10 |vpiTypespec: \_logic_typespec: , line:8:3, endln:8:14 |vpiRange: @@ -350,7 +350,7 @@ design: (work@Foo) |vpiNet: \_logic_net: (work@Foo.t2), line:9:15, endln:9:17 |vpiParent: - \_module: work@Foo (work@Foo), file:${SURELOG_DIR}/tests/CastStructMember/dut.sv, line:6:1, endln:10:10 + \_module_inst: work@Foo (work@Foo), file:${SURELOG_DIR}/tests/CastStructMember/dut.sv, line:6:1, endln:10:10 |vpiTypespec: \_logic_typespec: , line:9:3, endln:9:14 |vpiRange: @@ -378,7 +378,7 @@ design: (work@Foo) |vpiContAssign: \_cont_assign: , line:8:15, endln:8:17 |vpiParent: - \_module: work@Foo (work@Foo), file:${SURELOG_DIR}/tests/CastStructMember/dut.sv, line:6:1, endln:10:10 + \_module_inst: work@Foo (work@Foo), file:${SURELOG_DIR}/tests/CastStructMember/dut.sv, line:6:1, endln:10:10 |vpiNetDeclAssign:1 |vpiRhs: \_operation: , line:8:20, endln:8:31 @@ -403,7 +403,7 @@ design: (work@Foo) |vpiContAssign: \_cont_assign: , line:9:15, endln:9:17 |vpiParent: - \_module: work@Foo (work@Foo), file:${SURELOG_DIR}/tests/CastStructMember/dut.sv, line:6:1, endln:10:10 + \_module_inst: work@Foo (work@Foo), file:${SURELOG_DIR}/tests/CastStructMember/dut.sv, line:6:1, endln:10:10 |vpiNetDeclAssign:1 |vpiRhs: \_operation: , line:9:20, endln:9:25 diff --git a/tests/CastToParam/CastToParam.log b/tests/CastToParam/CastToParam.log index f77c5362d9..a02a6fe4a1 100644 --- a/tests/CastToParam/CastToParam.log +++ b/tests/CastToParam/CastToParam.log @@ -116,7 +116,7 @@ function 1 int_typespec 4 logic_typespec 1 logic_var 1 -module 5 +module_inst 5 operation 2 param_assign 4 parameter 4 @@ -133,7 +133,7 @@ function 2 int_typespec 4 logic_typespec 1 logic_var 1 -module 5 +module_inst 5 operation 3 param_assign 4 parameter 4 @@ -154,14 +154,14 @@ design: (work@top) |vpiElaborated:1 |vpiName:work@top |uhdmallModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/CastToParam/dut.sv, line:1:1, endln:11:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/CastToParam/dut.sv, line:1:1, endln:11:10 |vpiParent: \_design: (work@top) |vpiFullName:work@top |vpiParameter: \_parameter: (work@top.Depth), line:2:27, endln:2:32 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/CastToParam/dut.sv, line:1:1, endln:11:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/CastToParam/dut.sv, line:1:1, endln:11:10 |UINT:3 |vpiTypespec: \_int_typespec: , line:2:14, endln:2:26 @@ -172,7 +172,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.PTR_WIDTH), line:3:27, endln:3:36 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/CastToParam/dut.sv, line:1:1, endln:11:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/CastToParam/dut.sv, line:1:1, endln:11:10 |UINT:15 |vpiTypespec: \_int_typespec: , line:3:14, endln:3:26 @@ -187,7 +187,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:2:27, endln:2:36 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/CastToParam/dut.sv, line:1:1, endln:11:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/CastToParam/dut.sv, line:1:1, endln:11:10 |vpiRhs: \_constant: , line:2:35, endln:2:36 |vpiDecompile:3 @@ -201,7 +201,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:3:27, endln:3:41 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/CastToParam/dut.sv, line:1:1, endln:11:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/CastToParam/dut.sv, line:1:1, endln:11:10 |vpiRhs: \_constant: , line:3:39, endln:3:41 |vpiDecompile:15 @@ -216,7 +216,7 @@ design: (work@top) |vpiTaskFunc: \_function: (work@top.get_casted_depth), line:8:4, endln:10:15 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/CastToParam/dut.sv, line:1:1, endln:11:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/CastToParam/dut.sv, line:1:1, endln:11:10 |vpiName:get_casted_depth |vpiFullName:work@top.get_casted_depth |vpiVisibility:1 @@ -256,7 +256,7 @@ design: (work@top) |UINT:0 |vpiConstType:9 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/CastToParam/dut.sv, line:1:1, endln:11:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/CastToParam/dut.sv, line:1:1, endln:11:10 |vpiStmt: \_return_stmt: , line:9:7, endln:9:13 |vpiParent: @@ -275,14 +275,14 @@ design: (work@top) |vpiName:Depth |vpiFullName:work@top.get_casted_depth.Depth |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/CastToParam/dut.sv, line:1:1, endln:11:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/CastToParam/dut.sv, line:1:1, endln:11:10 |uhdmtopModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/CastToParam/dut.sv, line:1:1, endln:11:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/CastToParam/dut.sv, line:1:1, endln:11:10 |vpiName:work@top |vpiParameter: \_parameter: (work@top.Depth), line:2:27, endln:2:32 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/CastToParam/dut.sv, line:1:1, endln:11:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/CastToParam/dut.sv, line:1:1, endln:11:10 |UINT:3 |vpiTypespec: \_int_typespec: , line:2:14, endln:2:26 @@ -293,7 +293,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.PTR_WIDTH), line:3:27, endln:3:36 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/CastToParam/dut.sv, line:1:1, endln:11:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/CastToParam/dut.sv, line:1:1, endln:11:10 |UINT:15 |vpiTypespec: \_int_typespec: , line:3:14, endln:3:26 @@ -306,7 +306,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:2:27, endln:2:36 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/CastToParam/dut.sv, line:1:1, endln:11:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/CastToParam/dut.sv, line:1:1, endln:11:10 |vpiRhs: \_constant: , line:2:35, endln:2:36 |vpiDecompile:3 @@ -320,7 +320,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:3:27, endln:3:41 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/CastToParam/dut.sv, line:1:1, endln:11:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/CastToParam/dut.sv, line:1:1, endln:11:10 |vpiRhs: \_constant: , line:3:39, endln:3:41 |vpiDecompile:15 @@ -336,7 +336,7 @@ design: (work@top) |vpiTaskFunc: \_function: (work@top.get_casted_depth), line:8:4, endln:10:15 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/CastToParam/dut.sv, line:1:1, endln:11:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/CastToParam/dut.sv, line:1:1, endln:11:10 |vpiName:get_casted_depth |vpiFullName:work@top.get_casted_depth |vpiVisibility:1 @@ -344,7 +344,7 @@ design: (work@top) |vpiReturn: \_logic_var: , line:8:23, endln:8:38 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/CastToParam/dut.sv, line:1:1, endln:11:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/CastToParam/dut.sv, line:1:1, endln:11:10 |vpiStmt: \_return_stmt: , line:9:7, endln:9:13 |vpiParent: @@ -365,7 +365,7 @@ design: (work@top) |vpiActual: \_parameter: (work@top.Depth), line:2:27, endln:2:32 |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/CastToParam/dut.sv, line:1:1, endln:11:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/CastToParam/dut.sv, line:1:1, endln:11:10 |vpiTopModule:1 =================== [ FATAL] : 0 diff --git a/tests/CastTypespec/CastTypespec.log b/tests/CastTypespec/CastTypespec.log index 9b3e959a33..a00d0c3b88 100644 --- a/tests/CastTypespec/CastTypespec.log +++ b/tests/CastTypespec/CastTypespec.log @@ -762,7 +762,7 @@ integer_typespec 1 io_decl 11 logic_net 9 logic_var 1 -module 10 +module_inst 10 named_begin 1 operation 30 package 5 @@ -808,7 +808,7 @@ integer_typespec 1 io_decl 22 logic_net 9 logic_var 1 -module 10 +module_inst 10 named_begin 2 operation 40 package 5 @@ -1777,7 +1777,7 @@ design: (work@tlul_adapter_host) \_int_typespec: |vpiSigned:1 |uhdmallModules: -\_module: work@tlul_adapter_host (work@tlul_adapter_host), file:${SURELOG_DIR}/tests/CastTypespec/dut.sv, line:14:3, endln:23:12 +\_module_inst: work@tlul_adapter_host (work@tlul_adapter_host), file:${SURELOG_DIR}/tests/CastTypespec/dut.sv, line:14:3, endln:23:12 |vpiParent: \_design: (work@tlul_adapter_host) |vpiFullName:work@tlul_adapter_host @@ -1785,7 +1785,7 @@ design: (work@tlul_adapter_host) |vpiContAssign: \_cont_assign: , line:16:12, endln:19:6 |vpiParent: - \_module: work@tlul_adapter_host (work@tlul_adapter_host), file:${SURELOG_DIR}/tests/CastTypespec/dut.sv, line:14:3, endln:23:12 + \_module_inst: work@tlul_adapter_host (work@tlul_adapter_host), file:${SURELOG_DIR}/tests/CastTypespec/dut.sv, line:14:3, endln:23:12 |vpiRhs: \_operation: , line:16:19, endln:19:6 |vpiParent: @@ -1829,14 +1829,14 @@ design: (work@tlul_adapter_host) |vpiActual: \_logic_net: (tl_o) |uhdmallModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/CastTypespec/dut.sv, line:25:3, endln:42:12 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/CastTypespec/dut.sv, line:25:3, endln:42:12 |vpiParent: \_design: (work@tlul_adapter_host) |vpiFullName:work@top |vpiParameter: \_parameter: (work@top.HartSelLen), line:35:14, endln:35:24 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/CastTypespec/dut.sv, line:25:3, endln:42:12 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/CastTypespec/dut.sv, line:25:3, endln:42:12 |UINT:2 |vpiTypespec: \_int_typespec: @@ -1846,7 +1846,7 @@ design: (work@tlul_adapter_host) |vpiParamAssign: \_param_assign: , line:35:14, endln:35:28 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/CastTypespec/dut.sv, line:25:3, endln:42:12 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/CastTypespec/dut.sv, line:25:3, endln:42:12 |vpiRhs: \_constant: , line:35:27, endln:35:28 |vpiDecompile:2 @@ -1860,10 +1860,10 @@ design: (work@tlul_adapter_host) |vpiTypedef: \_struct_typespec: (ab_t), line:27:13, endln:27:19 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/CastTypespec/dut.sv, line:25:3, endln:42:12 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/CastTypespec/dut.sv, line:25:3, endln:42:12 |vpiName:ab_t |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/CastTypespec/dut.sv, line:25:3, endln:42:12 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/CastTypespec/dut.sv, line:25:3, endln:42:12 |vpiTypespecMember: \_typespec_member: (a), line:27:25, endln:27:26 |vpiParent: @@ -1898,31 +1898,31 @@ design: (work@tlul_adapter_host) |vpiNet: \_logic_net: (work@top.XYZ), line:26:25, endln:26:28 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/CastTypespec/dut.sv, line:25:3, endln:42:12 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/CastTypespec/dut.sv, line:25:3, endln:42:12 |vpiName:XYZ |vpiFullName:work@top.XYZ |vpiNet: \_logic_net: (work@top.a), line:28:9, endln:28:10 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/CastTypespec/dut.sv, line:25:3, endln:42:12 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/CastTypespec/dut.sv, line:25:3, endln:42:12 |vpiName:a |vpiFullName:work@top.a |vpiNet: \_logic_net: (work@top.b), line:28:11, endln:28:12 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/CastTypespec/dut.sv, line:25:3, endln:42:12 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/CastTypespec/dut.sv, line:25:3, endln:42:12 |vpiName:b |vpiFullName:work@top.b |vpiNet: \_logic_net: (work@top.c), line:28:13, endln:28:14 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/CastTypespec/dut.sv, line:25:3, endln:42:12 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/CastTypespec/dut.sv, line:25:3, endln:42:12 |vpiName:c |vpiFullName:work@top.c |vpiProcess: \_initial: , line:30:5, endln:33:8 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/CastTypespec/dut.sv, line:25:3, endln:42:12 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/CastTypespec/dut.sv, line:25:3, endln:42:12 |vpiStmt: \_begin: (work@top), line:30:13, endln:33:8 |vpiParent: @@ -2073,7 +2073,7 @@ design: (work@tlul_adapter_host) |vpiProcess: \_always: , line:36:3, endln:40:6 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/CastTypespec/dut.sv, line:25:3, endln:42:12 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/CastTypespec/dut.sv, line:25:3, endln:42:12 |vpiStmt: \_named_begin: (work@top.p_outmux), line:36:15, endln:40:6 |vpiParent: @@ -2164,7 +2164,7 @@ design: (work@tlul_adapter_host) \_logic_net: (resumereq_o) |vpiAlwaysType:2 |uhdmtopModules: -\_module: work@tlul_adapter_host (work@tlul_adapter_host), file:${SURELOG_DIR}/tests/CastTypespec/dut.sv, line:14:3, endln:23:12 +\_module_inst: work@tlul_adapter_host (work@tlul_adapter_host), file:${SURELOG_DIR}/tests/CastTypespec/dut.sv, line:14:3, endln:23:12 |vpiName:work@tlul_adapter_host |vpiDefName:work@tlul_adapter_host |vpiTop:1 @@ -2180,7 +2180,7 @@ design: (work@tlul_adapter_host) |vpiContAssign: \_cont_assign: , line:16:12, endln:19:6 |vpiParent: - \_module: work@tlul_adapter_host (work@tlul_adapter_host), file:${SURELOG_DIR}/tests/CastTypespec/dut.sv, line:14:3, endln:23:12 + \_module_inst: work@tlul_adapter_host (work@tlul_adapter_host), file:${SURELOG_DIR}/tests/CastTypespec/dut.sv, line:14:3, endln:23:12 |vpiRhs: \_operation: , line:16:19, endln:19:6 |vpiParent: @@ -2199,12 +2199,12 @@ design: (work@tlul_adapter_host) |vpiActual: \_logic_net: (tl_o) |uhdmtopModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/CastTypespec/dut.sv, line:25:3, endln:42:12 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/CastTypespec/dut.sv, line:25:3, endln:42:12 |vpiName:work@top |vpiVariables: \_struct_var: (work@top.XYZ), line:26:25, endln:26:38 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/CastTypespec/dut.sv, line:25:3, endln:42:12 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/CastTypespec/dut.sv, line:25:3, endln:42:12 |vpiTypespec: \_struct_typespec: , line:26:5, endln:26:11 |vpiTypespecMember: @@ -2280,7 +2280,7 @@ design: (work@tlul_adapter_host) |vpiVariables: \_int_var: (work@top.a), line:28:9, endln:28:10 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/CastTypespec/dut.sv, line:25:3, endln:42:12 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/CastTypespec/dut.sv, line:25:3, endln:42:12 |vpiTypespec: \_int_typespec: , line:28:5, endln:28:8 |vpiSigned:1 @@ -2290,7 +2290,7 @@ design: (work@tlul_adapter_host) |vpiVariables: \_int_var: (work@top.b), line:28:11, endln:28:12 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/CastTypespec/dut.sv, line:25:3, endln:42:12 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/CastTypespec/dut.sv, line:25:3, endln:42:12 |vpiTypespec: \_int_typespec: , line:28:5, endln:28:8 |vpiName:b @@ -2299,7 +2299,7 @@ design: (work@tlul_adapter_host) |vpiVariables: \_int_var: (work@top.c), line:28:13, endln:28:14 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/CastTypespec/dut.sv, line:25:3, endln:42:12 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/CastTypespec/dut.sv, line:25:3, endln:42:12 |vpiTypespec: \_int_typespec: , line:28:5, endln:28:8 |vpiName:c @@ -2308,7 +2308,7 @@ design: (work@tlul_adapter_host) |vpiParameter: \_parameter: (work@top.HartSelLen), line:35:14, endln:35:24 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/CastTypespec/dut.sv, line:25:3, endln:42:12 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/CastTypespec/dut.sv, line:25:3, endln:42:12 |UINT:2 |vpiTypespec: \_int_typespec: @@ -2320,7 +2320,7 @@ design: (work@tlul_adapter_host) |vpiParamAssign: \_param_assign: , line:35:14, endln:35:28 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/CastTypespec/dut.sv, line:25:3, endln:42:12 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/CastTypespec/dut.sv, line:25:3, endln:42:12 |vpiRhs: \_constant: , line:35:27, endln:35:28 |vpiDecompile:2 @@ -2351,7 +2351,7 @@ design: (work@tlul_adapter_host) |vpiProcess: \_initial: , line:30:5, endln:33:8 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/CastTypespec/dut.sv, line:25:3, endln:42:12 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/CastTypespec/dut.sv, line:25:3, endln:42:12 |vpiStmt: \_begin: (work@top), line:30:13, endln:33:8 |vpiParent: @@ -2455,7 +2455,7 @@ design: (work@tlul_adapter_host) |vpiProcess: \_always: , line:36:3, endln:40:6 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/CastTypespec/dut.sv, line:25:3, endln:42:12 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/CastTypespec/dut.sv, line:25:3, endln:42:12 |vpiStmt: \_named_begin: (work@top.p_outmux), line:36:15, endln:40:6 |vpiParent: diff --git a/tests/CastUnsigned/CastUnsigned.log b/tests/CastUnsigned/CastUnsigned.log index 487baa7c92..b61f32f60d 100644 --- a/tests/CastUnsigned/CastUnsigned.log +++ b/tests/CastUnsigned/CastUnsigned.log @@ -451,7 +451,7 @@ io_decl 11 logic_net 2 logic_typespec 2 logic_var 1 -module 9 +module_inst 9 named_begin 1 operation 2 package 2 @@ -487,7 +487,7 @@ io_decl 22 logic_net 2 logic_typespec 2 logic_var 1 -module 9 +module_inst 9 named_begin 2 operation 4 package 2 @@ -989,14 +989,14 @@ design: (work@top) \_int_typespec: |vpiSigned:1 |uhdmallModules: -\_module: work@M (work@M), file:${SURELOG_DIR}/tests/CastUnsigned/dut.sv, line:15:1, endln:17:10 +\_module_inst: work@M (work@M), file:${SURELOG_DIR}/tests/CastUnsigned/dut.sv, line:15:1, endln:17:10 |vpiParent: \_design: (work@top) |vpiFullName:work@M |vpiParameter: \_parameter: (work@M.P), line:16:26, endln:16:27 |vpiParent: - \_module: work@M (work@M), file:${SURELOG_DIR}/tests/CastUnsigned/dut.sv, line:15:1, endln:17:10 + \_module_inst: work@M (work@M), file:${SURELOG_DIR}/tests/CastUnsigned/dut.sv, line:15:1, endln:17:10 |BIN:0 |vpiTypespec: \_logic_typespec: , line:16:14, endln:16:25 @@ -1025,7 +1025,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:16:26, endln:16:32 |vpiParent: - \_module: work@M (work@M), file:${SURELOG_DIR}/tests/CastUnsigned/dut.sv, line:15:1, endln:17:10 + \_module_inst: work@M (work@M), file:${SURELOG_DIR}/tests/CastUnsigned/dut.sv, line:15:1, endln:17:10 |vpiRhs: \_constant: , line:16:30, endln:16:32 |vpiDecompile:'0 @@ -1038,14 +1038,14 @@ design: (work@top) \_parameter: (work@M.P), line:16:26, endln:16:27 |vpiDefName:work@M |uhdmallModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/CastUnsigned/dut.sv, line:2:1, endln:13:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/CastUnsigned/dut.sv, line:2:1, endln:13:10 |vpiParent: \_design: (work@top) |vpiFullName:work@top |vpiParameter: \_parameter: (work@top.INIT), line:4:19, endln:4:23 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/CastUnsigned/dut.sv, line:2:1, endln:13:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/CastUnsigned/dut.sv, line:2:1, endln:13:10 |BIN:0 |vpiTypespec: \_int_typespec: , line:4:12, endln:4:18 @@ -1057,7 +1057,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:4:19, endln:4:28 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/CastUnsigned/dut.sv, line:2:1, endln:13:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/CastUnsigned/dut.sv, line:2:1, endln:13:10 |vpiRhs: \_constant: , line:4:26, endln:4:28 |vpiDecompile:'0 @@ -1071,15 +1071,15 @@ design: (work@top) |vpiTypedef: \_interface_typespec: (foo_if), line:3:19, endln:3:26 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/CastUnsigned/dut.sv, line:2:1, endln:13:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/CastUnsigned/dut.sv, line:2:1, endln:13:10 |vpiName:foo_if |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/CastUnsigned/dut.sv, line:2:1, endln:13:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/CastUnsigned/dut.sv, line:2:1, endln:13:10 |vpiDefName:work@top |vpiProcess: \_always: , line:7:3, endln:11:6 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/CastUnsigned/dut.sv, line:2:1, endln:13:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/CastUnsigned/dut.sv, line:2:1, endln:13:10 |vpiStmt: \_named_begin: (work@top.proc_stall_tieoff), line:7:15, endln:11:6 |vpiParent: @@ -1157,12 +1157,12 @@ design: (work@top) |vpiName:stall |vpiAlwaysType:2 |uhdmtopModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/CastUnsigned/dut.sv, line:2:1, endln:13:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/CastUnsigned/dut.sv, line:2:1, endln:13:10 |vpiName:work@top |vpiParameter: \_parameter: (work@top.INIT), line:4:19, endln:4:23 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/CastUnsigned/dut.sv, line:2:1, endln:13:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/CastUnsigned/dut.sv, line:2:1, endln:13:10 |BIN:0 |vpiTypespec: \_int_typespec: , line:4:12, endln:4:18 @@ -1174,7 +1174,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:4:19, endln:4:28 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/CastUnsigned/dut.sv, line:2:1, endln:13:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/CastUnsigned/dut.sv, line:2:1, endln:13:10 |vpiRhs: \_constant: , line:4:26, endln:4:28 |vpiDecompile:32'b0 @@ -1201,7 +1201,7 @@ design: (work@top) |vpiProcess: \_always: , line:7:3, endln:11:6 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/CastUnsigned/dut.sv, line:2:1, endln:13:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/CastUnsigned/dut.sv, line:2:1, endln:13:10 |vpiStmt: \_named_begin: (work@top.proc_stall_tieoff), line:7:15, endln:11:6 |vpiParent: @@ -1281,12 +1281,12 @@ design: (work@top) |vpiName:stall |vpiAlwaysType:2 |uhdmtopModules: -\_module: work@M (work@M), file:${SURELOG_DIR}/tests/CastUnsigned/dut.sv, line:15:1, endln:17:10 +\_module_inst: work@M (work@M), file:${SURELOG_DIR}/tests/CastUnsigned/dut.sv, line:15:1, endln:17:10 |vpiName:work@M |vpiParameter: \_parameter: (work@M.P), line:16:26, endln:16:27 |vpiParent: - \_module: work@M (work@M), file:${SURELOG_DIR}/tests/CastUnsigned/dut.sv, line:15:1, endln:17:10 + \_module_inst: work@M (work@M), file:${SURELOG_DIR}/tests/CastUnsigned/dut.sv, line:15:1, endln:17:10 |BIN:0 |vpiTypespec: \_logic_typespec: , line:16:14, endln:16:25 @@ -1317,7 +1317,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:16:26, endln:16:32 |vpiParent: - \_module: work@M (work@M), file:${SURELOG_DIR}/tests/CastUnsigned/dut.sv, line:15:1, endln:17:10 + \_module_inst: work@M (work@M), file:${SURELOG_DIR}/tests/CastUnsigned/dut.sv, line:15:1, endln:17:10 |vpiRhs: \_constant: , line:16:30, endln:16:32 |vpiDecompile:8'b0 diff --git a/tests/Cell/Cell.log b/tests/Cell/Cell.log index efffa34bad..0492fac9ea 100644 --- a/tests/Cell/Cell.log +++ b/tests/Cell/Cell.log @@ -65,7 +65,7 @@ int_typespec 15 int_var 4 io_decl 11 logic_var 1 -module 16 +module_inst 16 operation 3 package 2 param_assign 6 @@ -92,7 +92,7 @@ int_typespec 15 int_var 4 io_decl 22 logic_var 1 -module 16 +module_inst 16 operation 4 package 2 param_assign 6 @@ -588,14 +588,14 @@ design: (work@top) \_int_typespec: |vpiSigned:1 |uhdmallModules: -\_module: work@assigner (work@assigner), file:${SURELOG_DIR}/tests/Cell/cell.v, line:1:1, endln:6:10 +\_module_inst: work@assigner (work@assigner), file:${SURELOG_DIR}/tests/Cell/cell.v, line:1:1, endln:6:10 |vpiParent: \_design: (work@top) |vpiFullName:work@assigner |vpiParameter: \_parameter: (work@assigner.invert), line:1:29, endln:1:35 |vpiParent: - \_module: work@assigner (work@assigner), file:${SURELOG_DIR}/tests/Cell/cell.v, line:1:1, endln:6:10 + \_module_inst: work@assigner (work@assigner), file:${SURELOG_DIR}/tests/Cell/cell.v, line:1:1, endln:6:10 |UINT:0 |vpiTypespec: \_int_typespec: @@ -604,7 +604,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:1:29, endln:1:39 |vpiParent: - \_module: work@assigner (work@assigner), file:${SURELOG_DIR}/tests/Cell/cell.v, line:1:1, endln:6:10 + \_module_inst: work@assigner (work@assigner), file:${SURELOG_DIR}/tests/Cell/cell.v, line:1:1, endln:6:10 |vpiRhs: \_constant: , line:1:38, endln:1:39 |vpiDecompile:0 @@ -618,14 +618,14 @@ design: (work@top) |vpiDefName:work@assigner |vpiCellInstance:1 |uhdmallModules: -\_module: work@middleman (work@middleman), file:${SURELOG_DIR}/tests/Cell/cell.v, line:8:1, endln:10:10 +\_module_inst: work@middleman (work@middleman), file:${SURELOG_DIR}/tests/Cell/cell.v, line:8:1, endln:10:10 |vpiParent: \_design: (work@top) |vpiFullName:work@middleman |vpiParameter: \_parameter: (work@middleman.invert), line:8:30, endln:8:36 |vpiParent: - \_module: work@middleman (work@middleman), file:${SURELOG_DIR}/tests/Cell/cell.v, line:8:1, endln:10:10 + \_module_inst: work@middleman (work@middleman), file:${SURELOG_DIR}/tests/Cell/cell.v, line:8:1, endln:10:10 |UINT:0 |vpiTypespec: \_int_typespec: @@ -634,7 +634,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:8:30, endln:8:40 |vpiParent: - \_module: work@middleman (work@middleman), file:${SURELOG_DIR}/tests/Cell/cell.v, line:8:1, endln:10:10 + \_module_inst: work@middleman (work@middleman), file:${SURELOG_DIR}/tests/Cell/cell.v, line:8:1, endln:10:10 |vpiRhs: \_constant: , line:8:39, endln:8:40 |vpiDecompile:0 @@ -648,27 +648,27 @@ design: (work@top) |vpiDefName:work@middleman |vpiCellInstance:1 |uhdmallModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/Cell/dut.sv, line:1:1, endln:4:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/Cell/dut.sv, line:1:1, endln:4:10 |vpiParent: \_design: (work@top) |vpiFullName:work@top |vpiDefName:work@top |uhdmtopModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/Cell/dut.sv, line:1:1, endln:4:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/Cell/dut.sv, line:1:1, endln:4:10 |vpiName:work@top |vpiDefName:work@top |vpiTop:1 |vpiTopModule:1 - |vpiModule: - \_module: work@middleman (work@top.mdl1), file:${SURELOG_DIR}/tests/Cell/dut.sv, line:2:4, endln:2:35 + |vpiModuleInst: + \_module_inst: work@middleman (work@top.mdl1), file:${SURELOG_DIR}/tests/Cell/dut.sv, line:2:4, endln:2:35 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/Cell/dut.sv, line:1:1, endln:4:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/Cell/dut.sv, line:1:1, endln:4:10 |vpiName:mdl1 |vpiFullName:work@top.mdl1 |vpiParameter: \_parameter: (work@top.mdl1.invert), line:8:30, endln:8:36 |vpiParent: - \_module: work@middleman (work@top.mdl1), file:${SURELOG_DIR}/tests/Cell/dut.sv, line:2:4, endln:2:35 + \_module_inst: work@middleman (work@top.mdl1), file:${SURELOG_DIR}/tests/Cell/dut.sv, line:2:4, endln:2:35 |UINT:0 |vpiTypespec: \_int_typespec: @@ -679,7 +679,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:8:30, endln:8:40 |vpiParent: - \_module: work@middleman (work@top.mdl1), file:${SURELOG_DIR}/tests/Cell/dut.sv, line:2:4, endln:2:35 + \_module_inst: work@middleman (work@top.mdl1), file:${SURELOG_DIR}/tests/Cell/dut.sv, line:2:4, endln:2:35 |vpiOverriden:1 |vpiRhs: \_constant: , line:8:39, endln:8:40 @@ -696,17 +696,17 @@ design: (work@top) |vpiDefFile:${SURELOG_DIR}/tests/Cell/cell.v |vpiDefLineNo:8 |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/Cell/dut.sv, line:1:1, endln:4:10 - |vpiModule: - \_module: work@assigner (work@top.mdl1.asgn), file:${SURELOG_DIR}/tests/Cell/cell.v, line:9:4, endln:9:39 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/Cell/dut.sv, line:1:1, endln:4:10 + |vpiModuleInst: + \_module_inst: work@assigner (work@top.mdl1.asgn), file:${SURELOG_DIR}/tests/Cell/cell.v, line:9:4, endln:9:39 |vpiParent: - \_module: work@middleman (work@top.mdl1), file:${SURELOG_DIR}/tests/Cell/dut.sv, line:2:4, endln:2:35 + \_module_inst: work@middleman (work@top.mdl1), file:${SURELOG_DIR}/tests/Cell/dut.sv, line:2:4, endln:2:35 |vpiName:asgn |vpiFullName:work@top.mdl1.asgn |vpiParameter: \_parameter: (work@top.mdl1.asgn.invert), line:1:29, endln:1:35 |vpiParent: - \_module: work@assigner (work@top.mdl1.asgn), file:${SURELOG_DIR}/tests/Cell/cell.v, line:9:4, endln:9:39 + \_module_inst: work@assigner (work@top.mdl1.asgn), file:${SURELOG_DIR}/tests/Cell/cell.v, line:9:4, endln:9:39 |UINT:0 |vpiTypespec: \_int_typespec: @@ -717,7 +717,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:1:29, endln:1:39 |vpiParent: - \_module: work@assigner (work@top.mdl1.asgn), file:${SURELOG_DIR}/tests/Cell/cell.v, line:9:4, endln:9:39 + \_module_inst: work@assigner (work@top.mdl1.asgn), file:${SURELOG_DIR}/tests/Cell/cell.v, line:9:4, endln:9:39 |vpiOverriden:1 |vpiRhs: \_constant: , line:1:38, endln:1:39 @@ -734,11 +734,11 @@ design: (work@top) |vpiDefFile:${SURELOG_DIR}/tests/Cell/cell.v |vpiDefLineNo:1 |vpiInstance: - \_module: work@middleman (work@top.mdl1), file:${SURELOG_DIR}/tests/Cell/dut.sv, line:2:4, endln:2:35 + \_module_inst: work@middleman (work@top.mdl1), file:${SURELOG_DIR}/tests/Cell/dut.sv, line:2:4, endln:2:35 |vpiGenScopeArray: \_gen_scope_array: (work@top.mdl1.asgn.genblk2), line:4:3, endln:5:23 |vpiParent: - \_module: work@assigner (work@top.mdl1.asgn), file:${SURELOG_DIR}/tests/Cell/cell.v, line:9:4, endln:9:39 + \_module_inst: work@assigner (work@top.mdl1.asgn), file:${SURELOG_DIR}/tests/Cell/cell.v, line:9:4, endln:9:39 |vpiName:genblk2 |vpiFullName:work@top.mdl1.asgn.genblk2 |vpiGenScope: @@ -767,16 +767,16 @@ design: (work@top) \_cont_assign: , line:5:12, endln:5:22 |vpiName:out |vpiFullName:work@top.mdl1.asgn.genblk2.out - |vpiModule: - \_module: work@middleman (work@top.mdl0), file:${SURELOG_DIR}/tests/Cell/dut.sv, line:3:4, endln:3:35 + |vpiModuleInst: + \_module_inst: work@middleman (work@top.mdl0), file:${SURELOG_DIR}/tests/Cell/dut.sv, line:3:4, endln:3:35 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/Cell/dut.sv, line:1:1, endln:4:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/Cell/dut.sv, line:1:1, endln:4:10 |vpiName:mdl0 |vpiFullName:work@top.mdl0 |vpiParameter: \_parameter: (work@top.mdl0.invert), line:8:30, endln:8:36 |vpiParent: - \_module: work@middleman (work@top.mdl0), file:${SURELOG_DIR}/tests/Cell/dut.sv, line:3:4, endln:3:35 + \_module_inst: work@middleman (work@top.mdl0), file:${SURELOG_DIR}/tests/Cell/dut.sv, line:3:4, endln:3:35 |UINT:0 |vpiTypespec: \_int_typespec: @@ -787,7 +787,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:8:30, endln:8:40 |vpiParent: - \_module: work@middleman (work@top.mdl0), file:${SURELOG_DIR}/tests/Cell/dut.sv, line:3:4, endln:3:35 + \_module_inst: work@middleman (work@top.mdl0), file:${SURELOG_DIR}/tests/Cell/dut.sv, line:3:4, endln:3:35 |vpiOverriden:1 |vpiRhs: \_constant: , line:8:39, endln:8:40 @@ -804,17 +804,17 @@ design: (work@top) |vpiDefFile:${SURELOG_DIR}/tests/Cell/cell.v |vpiDefLineNo:8 |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/Cell/dut.sv, line:1:1, endln:4:10 - |vpiModule: - \_module: work@assigner (work@top.mdl0.asgn), file:${SURELOG_DIR}/tests/Cell/cell.v, line:9:4, endln:9:39 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/Cell/dut.sv, line:1:1, endln:4:10 + |vpiModuleInst: + \_module_inst: work@assigner (work@top.mdl0.asgn), file:${SURELOG_DIR}/tests/Cell/cell.v, line:9:4, endln:9:39 |vpiParent: - \_module: work@middleman (work@top.mdl0), file:${SURELOG_DIR}/tests/Cell/dut.sv, line:3:4, endln:3:35 + \_module_inst: work@middleman (work@top.mdl0), file:${SURELOG_DIR}/tests/Cell/dut.sv, line:3:4, endln:3:35 |vpiName:asgn |vpiFullName:work@top.mdl0.asgn |vpiParameter: \_parameter: (work@top.mdl0.asgn.invert), line:1:29, endln:1:35 |vpiParent: - \_module: work@assigner (work@top.mdl0.asgn), file:${SURELOG_DIR}/tests/Cell/cell.v, line:9:4, endln:9:39 + \_module_inst: work@assigner (work@top.mdl0.asgn), file:${SURELOG_DIR}/tests/Cell/cell.v, line:9:4, endln:9:39 |UINT:0 |vpiTypespec: \_int_typespec: @@ -825,7 +825,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:1:29, endln:1:39 |vpiParent: - \_module: work@assigner (work@top.mdl0.asgn), file:${SURELOG_DIR}/tests/Cell/cell.v, line:9:4, endln:9:39 + \_module_inst: work@assigner (work@top.mdl0.asgn), file:${SURELOG_DIR}/tests/Cell/cell.v, line:9:4, endln:9:39 |vpiOverriden:1 |vpiRhs: \_constant: , line:1:38, endln:1:39 @@ -842,11 +842,11 @@ design: (work@top) |vpiDefFile:${SURELOG_DIR}/tests/Cell/cell.v |vpiDefLineNo:1 |vpiInstance: - \_module: work@middleman (work@top.mdl0), file:${SURELOG_DIR}/tests/Cell/dut.sv, line:3:4, endln:3:35 + \_module_inst: work@middleman (work@top.mdl0), file:${SURELOG_DIR}/tests/Cell/dut.sv, line:3:4, endln:3:35 |vpiGenScopeArray: \_gen_scope_array: (work@top.mdl0.asgn.genblk1), line:2:3, endln:3:22 |vpiParent: - \_module: work@assigner (work@top.mdl0.asgn), file:${SURELOG_DIR}/tests/Cell/cell.v, line:9:4, endln:9:39 + \_module_inst: work@assigner (work@top.mdl0.asgn), file:${SURELOG_DIR}/tests/Cell/cell.v, line:9:4, endln:9:39 |vpiName:genblk1 |vpiFullName:work@top.mdl0.asgn.genblk1 |vpiGenScope: diff --git a/tests/Chandle/Chandle.log b/tests/Chandle/Chandle.log index 118512c68c..8facbb953d 100644 --- a/tests/Chandle/Chandle.log +++ b/tests/Chandle/Chandle.log @@ -48,7 +48,7 @@ chandle_typespec 1 chandle_var 1 design 1 logic_net 1 -module 2 +module_inst 2 === UHDM Object Stats End === [INF:UH0707] Elaborating UHDM... @@ -57,7 +57,7 @@ chandle_typespec 1 chandle_var 1 design 1 logic_net 1 -module 2 +module_inst 2 === UHDM Object Stats End === [INF:UH0708] Writing UHDM DB: ${SURELOG_DIR}/build/regression/Chandle/slpp_all/surelog.uhdm ... @@ -72,7 +72,7 @@ design: (work@dut) |vpiElaborated:1 |vpiName:work@dut |uhdmallModules: -\_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/Chandle/dut.sv, line:1:1, endln:3:10 +\_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/Chandle/dut.sv, line:1:1, endln:3:10 |vpiParent: \_design: (work@dut) |vpiFullName:work@dut @@ -80,16 +80,16 @@ design: (work@dut) |vpiNet: \_logic_net: (work@dut.c), line:2:12, endln:2:13 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/Chandle/dut.sv, line:1:1, endln:3:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/Chandle/dut.sv, line:1:1, endln:3:10 |vpiName:c |vpiFullName:work@dut.c |uhdmtopModules: -\_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/Chandle/dut.sv, line:1:1, endln:3:10 +\_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/Chandle/dut.sv, line:1:1, endln:3:10 |vpiName:work@dut |vpiVariables: \_chandle_var: (work@dut.c), line:2:12, endln:2:13 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/Chandle/dut.sv, line:1:1, endln:3:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/Chandle/dut.sv, line:1:1, endln:3:10 |vpiName:c |vpiFullName:work@dut.c |vpiVisibility:1 diff --git a/tests/CheckerInst/CheckerInst.log b/tests/CheckerInst/CheckerInst.log index cd993de979..90f40663d6 100644 --- a/tests/CheckerInst/CheckerInst.log +++ b/tests/CheckerInst/CheckerInst.log @@ -318,7 +318,7 @@ event_control 1 logic_net 4 logic_typespec 1 logic_var 4 -module 2 +module_inst 2 ref_obj 1 === UHDM Object Stats End === [INF:UH0707] Elaborating UHDM... @@ -331,7 +331,7 @@ event_control 2 logic_net 4 logic_typespec 1 logic_var 4 -module 2 +module_inst 2 ref_obj 2 === UHDM Object Stats End === [INF:UH0708] Writing UHDM DB: ${SURELOG_DIR}/build/regression/CheckerInst/slpp_all/surelog.uhdm ... @@ -347,7 +347,7 @@ design: (work@top) |vpiElaborated:1 |vpiName:work@top |uhdmallModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/CheckerInst/dut.sv, line:1:1, endln:16:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/CheckerInst/dut.sv, line:1:1, endln:16:10 |vpiParent: \_design: (work@top) |vpiFullName:work@top @@ -355,35 +355,35 @@ design: (work@top) |vpiNet: \_logic_net: (work@top.a), line:2:9, endln:2:10 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/CheckerInst/dut.sv, line:1:1, endln:16:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/CheckerInst/dut.sv, line:1:1, endln:16:10 |vpiName:a |vpiFullName:work@top.a |vpiNetType:36 |vpiNet: \_logic_net: (work@top.b), line:2:12, endln:2:13 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/CheckerInst/dut.sv, line:1:1, endln:16:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/CheckerInst/dut.sv, line:1:1, endln:16:10 |vpiName:b |vpiFullName:work@top.b |vpiNetType:36 |vpiNet: \_logic_net: (work@top.c), line:2:15, endln:2:16 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/CheckerInst/dut.sv, line:1:1, endln:16:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/CheckerInst/dut.sv, line:1:1, endln:16:10 |vpiName:c |vpiFullName:work@top.c |vpiNetType:36 |vpiNet: \_logic_net: (work@top.clk), line:2:18, endln:2:21 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/CheckerInst/dut.sv, line:1:1, endln:16:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/CheckerInst/dut.sv, line:1:1, endln:16:10 |vpiName:clk |vpiFullName:work@top.clk |vpiNetType:36 |vpiAssertion: \_checker_inst: my_checker (work@top.check), line:13:3, endln:15:35 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/CheckerInst/dut.sv, line:1:1, endln:16:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/CheckerInst/dut.sv, line:1:1, endln:16:10 |vpiName:check |vpiFullName:work@top.check |vpiDefName:my_checker @@ -400,12 +400,12 @@ design: (work@top) |vpiActual: \_logic_var: (work@top.clk), line:2:18, endln:2:21 |uhdmtopModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/CheckerInst/dut.sv, line:1:1, endln:16:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/CheckerInst/dut.sv, line:1:1, endln:16:10 |vpiName:work@top |vpiVariables: \_logic_var: (work@top.a), line:2:9, endln:2:10 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/CheckerInst/dut.sv, line:1:1, endln:16:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/CheckerInst/dut.sv, line:1:1, endln:16:10 |vpiTypespec: \_logic_typespec: , line:2:3, endln:2:8 |vpiName:a @@ -414,7 +414,7 @@ design: (work@top) |vpiVariables: \_logic_var: (work@top.b), line:2:12, endln:2:13 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/CheckerInst/dut.sv, line:1:1, endln:16:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/CheckerInst/dut.sv, line:1:1, endln:16:10 |vpiTypespec: \_logic_typespec: , line:2:3, endln:2:8 |vpiName:b @@ -423,7 +423,7 @@ design: (work@top) |vpiVariables: \_logic_var: (work@top.c), line:2:15, endln:2:16 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/CheckerInst/dut.sv, line:1:1, endln:16:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/CheckerInst/dut.sv, line:1:1, endln:16:10 |vpiTypespec: \_logic_typespec: , line:2:3, endln:2:8 |vpiName:c @@ -432,7 +432,7 @@ design: (work@top) |vpiVariables: \_logic_var: (work@top.clk), line:2:18, endln:2:21 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/CheckerInst/dut.sv, line:1:1, endln:16:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/CheckerInst/dut.sv, line:1:1, endln:16:10 |vpiTypespec: \_logic_typespec: , line:2:3, endln:2:8 |vpiName:clk @@ -443,17 +443,17 @@ design: (work@top) |vpiAssertion: \_checker_inst: my_checker (work@top.check), line:13:3, endln:15:35 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/CheckerInst/dut.sv, line:1:1, endln:16:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/CheckerInst/dut.sv, line:1:1, endln:16:10 |vpiName:check |vpiFullName:work@top.check |vpiDefName:my_checker |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/CheckerInst/dut.sv, line:1:1, endln:16:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/CheckerInst/dut.sv, line:1:1, endln:16:10 |vpiTopModule:1 |vpiGlobalClocking: \_clocking_block: (work@top.top_clocking), line:3:3, endln:3:51 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/CheckerInst/dut.sv, line:1:1, endln:16:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/CheckerInst/dut.sv, line:1:1, endln:16:10 |vpiName:top_clocking |vpiFullName:work@top.top_clocking |vpiClockingEvent: @@ -469,7 +469,7 @@ design: (work@top) |vpiActual: \_logic_var: (work@top.clk), line:2:18, endln:2:21 |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/CheckerInst/dut.sv, line:1:1, endln:16:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/CheckerInst/dut.sv, line:1:1, endln:16:10 =================== [ FATAL] : 0 [ SYNTAX] : 0 diff --git a/tests/ClassFsm/ClassFsm.log b/tests/ClassFsm/ClassFsm.log index b808f991a4..4bc2eab21f 100644 --- a/tests/ClassFsm/ClassFsm.log +++ b/tests/ClassFsm/ClassFsm.log @@ -49,7 +49,7 @@ io_decl 2 logic_net 7 logic_typespec 10 method_func_call 2 -module 4 +module_inst 4 operation 2 param_assign 4 parameter 4 @@ -85,7 +85,7 @@ logic_net 7 logic_typespec 10 method_func_call 2 method_task_call 2 -module 4 +module_inst 4 operation 9 param_assign 28 parameter 4 @@ -108,7 +108,7 @@ design: (work@fsm_class) |vpiElaborated:1 |vpiName:work@fsm_class |uhdmallModules: -\_module: work@fsm_class (work@fsm_class), file:${SURELOG_DIR}/tests/ClassFsm/dut.sv, line:1:1, endln:87:10 +\_module_inst: work@fsm_class (work@fsm_class), file:${SURELOG_DIR}/tests/ClassFsm/dut.sv, line:1:1, endln:87:10 |vpiParent: \_design: (work@fsm_class) |vpiFullName:work@fsm_class @@ -116,7 +116,7 @@ design: (work@fsm_class) |vpiClassDefn: \_class_defn: (work@fsm_class::baseFsm), file:${SURELOG_DIR}/tests/ClassFsm/dut.sv, line:3:3, endln:24:11 |vpiParent: - \_module: work@fsm_class (work@fsm_class), file:${SURELOG_DIR}/tests/ClassFsm/dut.sv, line:1:1, endln:87:10 + \_module_inst: work@fsm_class (work@fsm_class), file:${SURELOG_DIR}/tests/ClassFsm/dut.sv, line:1:1, endln:87:10 |vpiName:baseFsm |vpiFullName:work@fsm_class::baseFsm |vpiVariables: @@ -348,7 +348,7 @@ design: (work@fsm_class) |vpiDerivedClasses: \_class_defn: (work@fsm_class::specificFSM), file:${SURELOG_DIR}/tests/ClassFsm/dut.sv, line:26:3, endln:79:11 |vpiParent: - \_module: work@fsm_class (work@fsm_class), file:${SURELOG_DIR}/tests/ClassFsm/dut.sv, line:1:1, endln:87:10 + \_module_inst: work@fsm_class (work@fsm_class), file:${SURELOG_DIR}/tests/ClassFsm/dut.sv, line:1:1, endln:87:10 |vpiName:specificFSM |vpiFullName:work@fsm_class::specificFSM |vpiParameter: @@ -856,31 +856,31 @@ design: (work@fsm_class) |vpiNet: \_logic_net: (work@fsm_class.clk), line:1:25, endln:1:28 |vpiParent: - \_module: work@fsm_class (work@fsm_class), file:${SURELOG_DIR}/tests/ClassFsm/dut.sv, line:1:1, endln:87:10 + \_module_inst: work@fsm_class (work@fsm_class), file:${SURELOG_DIR}/tests/ClassFsm/dut.sv, line:1:1, endln:87:10 |vpiName:clk |vpiFullName:work@fsm_class.clk |vpiNet: \_logic_net: (work@fsm_class.reset), line:1:36, endln:1:41 |vpiParent: - \_module: work@fsm_class (work@fsm_class), file:${SURELOG_DIR}/tests/ClassFsm/dut.sv, line:1:1, endln:87:10 + \_module_inst: work@fsm_class (work@fsm_class), file:${SURELOG_DIR}/tests/ClassFsm/dut.sv, line:1:1, endln:87:10 |vpiName:reset |vpiFullName:work@fsm_class.reset |vpiNet: \_logic_net: (work@fsm_class.x), line:1:49, endln:1:50 |vpiParent: - \_module: work@fsm_class (work@fsm_class), file:${SURELOG_DIR}/tests/ClassFsm/dut.sv, line:1:1, endln:87:10 + \_module_inst: work@fsm_class (work@fsm_class), file:${SURELOG_DIR}/tests/ClassFsm/dut.sv, line:1:1, endln:87:10 |vpiName:x |vpiFullName:work@fsm_class.x |vpiNet: \_logic_net: (work@fsm_class.P), line:81:15, endln:81:16 |vpiParent: - \_module: work@fsm_class (work@fsm_class), file:${SURELOG_DIR}/tests/ClassFsm/dut.sv, line:1:1, endln:87:10 + \_module_inst: work@fsm_class (work@fsm_class), file:${SURELOG_DIR}/tests/ClassFsm/dut.sv, line:1:1, endln:87:10 |vpiName:P |vpiFullName:work@fsm_class.P |vpiPort: \_port: (clk), line:1:25, endln:1:28 |vpiParent: - \_module: work@fsm_class (work@fsm_class), file:${SURELOG_DIR}/tests/ClassFsm/dut.sv, line:1:1, endln:87:10 + \_module_inst: work@fsm_class (work@fsm_class), file:${SURELOG_DIR}/tests/ClassFsm/dut.sv, line:1:1, endln:87:10 |vpiName:clk |vpiDirection:1 |vpiLowConn: @@ -892,7 +892,7 @@ design: (work@fsm_class) |vpiPort: \_port: (reset), line:1:36, endln:1:41 |vpiParent: - \_module: work@fsm_class (work@fsm_class), file:${SURELOG_DIR}/tests/ClassFsm/dut.sv, line:1:1, endln:87:10 + \_module_inst: work@fsm_class (work@fsm_class), file:${SURELOG_DIR}/tests/ClassFsm/dut.sv, line:1:1, endln:87:10 |vpiName:reset |vpiDirection:1 |vpiLowConn: @@ -904,7 +904,7 @@ design: (work@fsm_class) |vpiPort: \_port: (x), line:1:49, endln:1:50 |vpiParent: - \_module: work@fsm_class (work@fsm_class), file:${SURELOG_DIR}/tests/ClassFsm/dut.sv, line:1:1, endln:87:10 + \_module_inst: work@fsm_class (work@fsm_class), file:${SURELOG_DIR}/tests/ClassFsm/dut.sv, line:1:1, endln:87:10 |vpiName:x |vpiDirection:1 |vpiLowConn: @@ -916,7 +916,7 @@ design: (work@fsm_class) |vpiProcess: \_always: , line:82:3, endln:84:6 |vpiParent: - \_module: work@fsm_class (work@fsm_class), file:${SURELOG_DIR}/tests/ClassFsm/dut.sv, line:1:1, endln:87:10 + \_module_inst: work@fsm_class (work@fsm_class), file:${SURELOG_DIR}/tests/ClassFsm/dut.sv, line:1:1, endln:87:10 |vpiStmt: \_event_control: , line:82:10, endln:82:24 |vpiParent: @@ -959,7 +959,7 @@ design: (work@fsm_class) |vpiProcess: \_always: , line:85:3, endln:86:15 |vpiParent: - \_module: work@fsm_class (work@fsm_class), file:${SURELOG_DIR}/tests/ClassFsm/dut.sv, line:1:1, endln:87:10 + \_module_inst: work@fsm_class (work@fsm_class), file:${SURELOG_DIR}/tests/ClassFsm/dut.sv, line:1:1, endln:87:10 |vpiStmt: \_event_control: , line:85:10, endln:85:12 |vpiParent: @@ -974,12 +974,12 @@ design: (work@fsm_class) |vpiName:P |vpiAlwaysType:1 |uhdmtopModules: -\_module: work@fsm_class (work@fsm_class), file:${SURELOG_DIR}/tests/ClassFsm/dut.sv, line:1:1, endln:87:10 +\_module_inst: work@fsm_class (work@fsm_class), file:${SURELOG_DIR}/tests/ClassFsm/dut.sv, line:1:1, endln:87:10 |vpiName:work@fsm_class |vpiVariables: \_class_var: (work@fsm_class.P), line:81:15, endln:81:16 |vpiParent: - \_module: work@fsm_class (work@fsm_class), file:${SURELOG_DIR}/tests/ClassFsm/dut.sv, line:1:1, endln:87:10 + \_module_inst: work@fsm_class (work@fsm_class), file:${SURELOG_DIR}/tests/ClassFsm/dut.sv, line:1:1, endln:87:10 |vpiTypespec: \_class_typespec: (specificFSM), line:81:3, endln:81:14 |vpiParent: @@ -995,7 +995,7 @@ design: (work@fsm_class) |vpiClassDefn: \_class_defn: (work@fsm_class::baseFsm), file:${SURELOG_DIR}/tests/ClassFsm/dut.sv, line:3:3, endln:24:11 |vpiParent: - \_module: work@fsm_class (work@fsm_class), file:${SURELOG_DIR}/tests/ClassFsm/dut.sv, line:1:1, endln:87:10 + \_module_inst: work@fsm_class (work@fsm_class), file:${SURELOG_DIR}/tests/ClassFsm/dut.sv, line:1:1, endln:87:10 |vpiName:baseFsm |vpiFullName:work@fsm_class::baseFsm |vpiVariables: @@ -1172,7 +1172,7 @@ design: (work@fsm_class) |vpiClassDefn: \_class_defn: (work@fsm_class::specificFSM), file:${SURELOG_DIR}/tests/ClassFsm/dut.sv, line:26:3, endln:79:11 |vpiParent: - \_module: work@fsm_class (work@fsm_class), file:${SURELOG_DIR}/tests/ClassFsm/dut.sv, line:1:1, endln:87:10 + \_module_inst: work@fsm_class (work@fsm_class), file:${SURELOG_DIR}/tests/ClassFsm/dut.sv, line:1:1, endln:87:10 |vpiName:specificFSM |vpiFullName:work@fsm_class::specificFSM |vpiParameter: @@ -1616,7 +1616,7 @@ design: (work@fsm_class) |vpiNet: \_logic_net: (work@fsm_class.clk), line:1:25, endln:1:28 |vpiParent: - \_module: work@fsm_class (work@fsm_class), file:${SURELOG_DIR}/tests/ClassFsm/dut.sv, line:1:1, endln:87:10 + \_module_inst: work@fsm_class (work@fsm_class), file:${SURELOG_DIR}/tests/ClassFsm/dut.sv, line:1:1, endln:87:10 |vpiTypespec: \_logic_typespec: , line:1:25, endln:1:25 |vpiName:clk @@ -1624,7 +1624,7 @@ design: (work@fsm_class) |vpiNet: \_logic_net: (work@fsm_class.reset), line:1:36, endln:1:41 |vpiParent: - \_module: work@fsm_class (work@fsm_class), file:${SURELOG_DIR}/tests/ClassFsm/dut.sv, line:1:1, endln:87:10 + \_module_inst: work@fsm_class (work@fsm_class), file:${SURELOG_DIR}/tests/ClassFsm/dut.sv, line:1:1, endln:87:10 |vpiTypespec: \_logic_typespec: , line:1:36, endln:1:36 |vpiName:reset @@ -1632,7 +1632,7 @@ design: (work@fsm_class) |vpiNet: \_logic_net: (work@fsm_class.x), line:1:49, endln:1:50 |vpiParent: - \_module: work@fsm_class (work@fsm_class), file:${SURELOG_DIR}/tests/ClassFsm/dut.sv, line:1:1, endln:87:10 + \_module_inst: work@fsm_class (work@fsm_class), file:${SURELOG_DIR}/tests/ClassFsm/dut.sv, line:1:1, endln:87:10 |vpiTypespec: \_logic_typespec: , line:1:49, endln:1:49 |vpiName:x @@ -1641,7 +1641,7 @@ design: (work@fsm_class) |vpiPort: \_port: (clk), line:1:25, endln:1:28 |vpiParent: - \_module: work@fsm_class (work@fsm_class), file:${SURELOG_DIR}/tests/ClassFsm/dut.sv, line:1:1, endln:87:10 + \_module_inst: work@fsm_class (work@fsm_class), file:${SURELOG_DIR}/tests/ClassFsm/dut.sv, line:1:1, endln:87:10 |vpiName:clk |vpiDirection:1 |vpiLowConn: @@ -1655,11 +1655,11 @@ design: (work@fsm_class) |vpiTypedef: \_logic_typespec: , line:1:25, endln:1:25 |vpiInstance: - \_module: work@fsm_class (work@fsm_class), file:${SURELOG_DIR}/tests/ClassFsm/dut.sv, line:1:1, endln:87:10 + \_module_inst: work@fsm_class (work@fsm_class), file:${SURELOG_DIR}/tests/ClassFsm/dut.sv, line:1:1, endln:87:10 |vpiPort: \_port: (reset), line:1:36, endln:1:41 |vpiParent: - \_module: work@fsm_class (work@fsm_class), file:${SURELOG_DIR}/tests/ClassFsm/dut.sv, line:1:1, endln:87:10 + \_module_inst: work@fsm_class (work@fsm_class), file:${SURELOG_DIR}/tests/ClassFsm/dut.sv, line:1:1, endln:87:10 |vpiName:reset |vpiDirection:1 |vpiLowConn: @@ -1673,11 +1673,11 @@ design: (work@fsm_class) |vpiTypedef: \_logic_typespec: , line:1:36, endln:1:36 |vpiInstance: - \_module: work@fsm_class (work@fsm_class), file:${SURELOG_DIR}/tests/ClassFsm/dut.sv, line:1:1, endln:87:10 + \_module_inst: work@fsm_class (work@fsm_class), file:${SURELOG_DIR}/tests/ClassFsm/dut.sv, line:1:1, endln:87:10 |vpiPort: \_port: (x), line:1:49, endln:1:50 |vpiParent: - \_module: work@fsm_class (work@fsm_class), file:${SURELOG_DIR}/tests/ClassFsm/dut.sv, line:1:1, endln:87:10 + \_module_inst: work@fsm_class (work@fsm_class), file:${SURELOG_DIR}/tests/ClassFsm/dut.sv, line:1:1, endln:87:10 |vpiName:x |vpiDirection:1 |vpiLowConn: @@ -1691,11 +1691,11 @@ design: (work@fsm_class) |vpiTypedef: \_logic_typespec: , line:1:49, endln:1:49 |vpiInstance: - \_module: work@fsm_class (work@fsm_class), file:${SURELOG_DIR}/tests/ClassFsm/dut.sv, line:1:1, endln:87:10 + \_module_inst: work@fsm_class (work@fsm_class), file:${SURELOG_DIR}/tests/ClassFsm/dut.sv, line:1:1, endln:87:10 |vpiProcess: \_always: , line:82:3, endln:84:6 |vpiParent: - \_module: work@fsm_class (work@fsm_class), file:${SURELOG_DIR}/tests/ClassFsm/dut.sv, line:1:1, endln:87:10 + \_module_inst: work@fsm_class (work@fsm_class), file:${SURELOG_DIR}/tests/ClassFsm/dut.sv, line:1:1, endln:87:10 |vpiStmt: \_event_control: , line:82:10, endln:82:24 |vpiParent: @@ -1739,7 +1739,7 @@ design: (work@fsm_class) |vpiProcess: \_always: , line:85:3, endln:86:15 |vpiParent: - \_module: work@fsm_class (work@fsm_class), file:${SURELOG_DIR}/tests/ClassFsm/dut.sv, line:1:1, endln:87:10 + \_module_inst: work@fsm_class (work@fsm_class), file:${SURELOG_DIR}/tests/ClassFsm/dut.sv, line:1:1, endln:87:10 |vpiStmt: \_event_control: , line:85:10, endln:85:12 |vpiParent: diff --git a/tests/ClassFuncProto/ClassFuncProto.log b/tests/ClassFuncProto/ClassFuncProto.log index 1c6730fd5d..0475cc300b 100644 --- a/tests/ClassFuncProto/ClassFuncProto.log +++ b/tests/ClassFuncProto/ClassFuncProto.log @@ -521,7 +521,7 @@ int_var 6 io_decl 18 logic_net 2 logic_var 1 -module 3 +module_inst 3 package 2 range 3 ref_var 2 @@ -548,7 +548,7 @@ int_var 6 io_decl 78 logic_net 2 logic_var 1 -module 3 +module_inst 3 package 2 range 23 ref_var 16 @@ -1043,7 +1043,7 @@ design: (work@toto) \_int_typespec: |vpiSigned:1 |uhdmallModules: -\_module: work@toto (work@toto), file:${SURELOG_DIR}/tests/ClassFuncProto/top.v, line:6:1, endln:52:10 +\_module_inst: work@toto (work@toto), file:${SURELOG_DIR}/tests/ClassFuncProto/top.v, line:6:1, endln:52:10 |vpiParent: \_design: (work@toto) |vpiFullName:work@toto @@ -1051,7 +1051,7 @@ design: (work@toto) |vpiClassDefn: \_class_defn: (work@toto::c1), file:${SURELOG_DIR}/tests/ClassFuncProto/top.v, line:18:1, endln:48:9 |vpiParent: - \_module: work@toto (work@toto), file:${SURELOG_DIR}/tests/ClassFuncProto/top.v, line:6:1, endln:52:10 + \_module_inst: work@toto (work@toto), file:${SURELOG_DIR}/tests/ClassFuncProto/top.v, line:6:1, endln:52:10 |vpiName:c1 |vpiFullName:work@toto::c1 |vpiTypedef: @@ -1358,7 +1358,7 @@ design: (work@toto) |vpiClassDefn: \_class_defn: (work@toto::c2), file:${SURELOG_DIR}/tests/ClassFuncProto/top.v, line:8:1, endln:12:9 |vpiParent: - \_module: work@toto (work@toto), file:${SURELOG_DIR}/tests/ClassFuncProto/top.v, line:6:1, endln:52:10 + \_module_inst: work@toto (work@toto), file:${SURELOG_DIR}/tests/ClassFuncProto/top.v, line:6:1, endln:52:10 |vpiName:c2 |vpiFullName:work@toto::c2 |vpiTypedef: @@ -1370,7 +1370,7 @@ design: (work@toto) |vpiDerivedClasses: \_class_defn: (work@toto::c3), file:${SURELOG_DIR}/tests/ClassFuncProto/top.v, line:15:1, endln:16:9 |vpiParent: - \_module: work@toto (work@toto), file:${SURELOG_DIR}/tests/ClassFuncProto/top.v, line:6:1, endln:52:10 + \_module_inst: work@toto (work@toto), file:${SURELOG_DIR}/tests/ClassFuncProto/top.v, line:6:1, endln:52:10 |vpiName:c3 |vpiFullName:work@toto::c3 |vpiExtends: @@ -1391,18 +1391,18 @@ design: (work@toto) |vpiNet: \_logic_net: (work@toto.d), line:50:5, endln:50:6 |vpiParent: - \_module: work@toto (work@toto), file:${SURELOG_DIR}/tests/ClassFuncProto/top.v, line:6:1, endln:52:10 + \_module_inst: work@toto (work@toto), file:${SURELOG_DIR}/tests/ClassFuncProto/top.v, line:6:1, endln:52:10 |vpiName:d |vpiFullName:work@toto.d |uhdmtopModules: -\_module: work@toto (work@toto), file:${SURELOG_DIR}/tests/ClassFuncProto/top.v, line:6:1, endln:52:10 +\_module_inst: work@toto (work@toto), file:${SURELOG_DIR}/tests/ClassFuncProto/top.v, line:6:1, endln:52:10 |vpiName:work@toto |vpiDefName:work@toto |vpiTop:1 |vpiClassDefn: \_class_defn: (work@toto::c1), file:${SURELOG_DIR}/tests/ClassFuncProto/top.v, line:18:1, endln:48:9 |vpiParent: - \_module: work@toto (work@toto), file:${SURELOG_DIR}/tests/ClassFuncProto/top.v, line:6:1, endln:52:10 + \_module_inst: work@toto (work@toto), file:${SURELOG_DIR}/tests/ClassFuncProto/top.v, line:6:1, endln:52:10 |vpiName:c1 |vpiFullName:work@toto::c1 |vpiTypedef: @@ -1614,7 +1614,7 @@ design: (work@toto) |vpiClassDefn: \_class_defn: (work@toto::c2), file:${SURELOG_DIR}/tests/ClassFuncProto/top.v, line:8:1, endln:12:9 |vpiParent: - \_module: work@toto (work@toto), file:${SURELOG_DIR}/tests/ClassFuncProto/top.v, line:6:1, endln:52:10 + \_module_inst: work@toto (work@toto), file:${SURELOG_DIR}/tests/ClassFuncProto/top.v, line:6:1, endln:52:10 |vpiName:c2 |vpiFullName:work@toto::c2 |vpiTypedef: @@ -1628,7 +1628,7 @@ design: (work@toto) |vpiClassDefn: \_class_defn: (work@toto::c3), file:${SURELOG_DIR}/tests/ClassFuncProto/top.v, line:15:1, endln:16:9 |vpiParent: - \_module: work@toto (work@toto), file:${SURELOG_DIR}/tests/ClassFuncProto/top.v, line:6:1, endln:52:10 + \_module_inst: work@toto (work@toto), file:${SURELOG_DIR}/tests/ClassFuncProto/top.v, line:6:1, endln:52:10 |vpiName:c3 |vpiFullName:work@toto::c3 |vpiExtends: @@ -1647,7 +1647,7 @@ design: (work@toto) |vpiNet: \_logic_net: (work@toto.d), line:50:5, endln:50:6 |vpiParent: - \_module: work@toto (work@toto), file:${SURELOG_DIR}/tests/ClassFuncProto/top.v, line:6:1, endln:52:10 + \_module_inst: work@toto (work@toto), file:${SURELOG_DIR}/tests/ClassFuncProto/top.v, line:6:1, endln:52:10 |vpiTypespec: \_unsupported_typespec: (DD), line:50:2, endln:50:4 |vpiName:DD diff --git a/tests/ClassFuncTask/ClassFuncTask.log b/tests/ClassFuncTask/ClassFuncTask.log index 907165b8fb..150b524166 100644 --- a/tests/ClassFuncTask/ClassFuncTask.log +++ b/tests/ClassFuncTask/ClassFuncTask.log @@ -42,7 +42,7 @@ int_typespec 9 int_var 2 io_decl 2 method_func_call 1 -module 2 +module_inst 2 operation 2 package 3 param_assign 1 @@ -70,7 +70,7 @@ int_typespec 9 int_var 3 io_decl 4 method_func_call 2 -module 2 +module_inst 2 operation 2 package 3 param_assign 2 diff --git a/tests/ClassMemberRef/ClassMemberRef.log b/tests/ClassMemberRef/ClassMemberRef.log index 7d4611cc20..6616be85e5 100644 --- a/tests/ClassMemberRef/ClassMemberRef.log +++ b/tests/ClassMemberRef/ClassMemberRef.log @@ -191,7 +191,7 @@ initial 1 io_decl 3 logic_net 2 method_func_call 2 -module 3 +module_inst 3 package 3 ref_obj 9 === UHDM Object Stats End === @@ -213,7 +213,7 @@ initial 2 io_decl 6 logic_net 2 method_func_call 4 -module 3 +module_inst 3 package 3 ref_obj 19 === UHDM Object Stats End === @@ -416,7 +416,7 @@ design: (work@top) |vpiInstance: \_package: pkg (pkg::), file:${SURELOG_DIR}/tests/ClassMemberRef/dut.sv, line:1:1, endln:20:11 |uhdmallModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/ClassMemberRef/dut.sv, line:22:1, endln:29:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ClassMemberRef/dut.sv, line:22:1, endln:29:10 |vpiParent: \_design: (work@top) |vpiFullName:work@top @@ -424,13 +424,13 @@ design: (work@top) |vpiNet: \_logic_net: (work@top.printer), line:24:18, endln:24:25 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ClassMemberRef/dut.sv, line:22:1, endln:29:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ClassMemberRef/dut.sv, line:22:1, endln:29:10 |vpiName:printer |vpiFullName:work@top.printer |vpiProcess: \_initial: , line:25:1, endln:28:4 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ClassMemberRef/dut.sv, line:22:1, endln:29:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ClassMemberRef/dut.sv, line:22:1, endln:29:10 |vpiStmt: \_begin: (work@top), line:25:9, endln:28:4 |vpiParent: @@ -469,12 +469,12 @@ design: (work@top) \_ref_obj: (printer), line:27:1, endln:27:8 |vpiName:printer |uhdmtopModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/ClassMemberRef/dut.sv, line:22:1, endln:29:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ClassMemberRef/dut.sv, line:22:1, endln:29:10 |vpiName:work@top |vpiVariables: \_class_var: (work@top.printer), line:24:18, endln:24:25 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ClassMemberRef/dut.sv, line:22:1, endln:29:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ClassMemberRef/dut.sv, line:22:1, endln:29:10 |vpiTypespec: \_class_typespec: (pkg::uvm_printer), line:24:1, endln:24:6 |vpiParent: @@ -495,7 +495,7 @@ design: (work@top) |vpiProcess: \_initial: , line:25:1, endln:28:4 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ClassMemberRef/dut.sv, line:22:1, endln:29:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ClassMemberRef/dut.sv, line:22:1, endln:29:10 |vpiStmt: \_begin: (work@top), line:25:9, endln:28:4 |vpiParent: diff --git a/tests/ClassMethodCall/ClassMethodCall.log b/tests/ClassMethodCall/ClassMethodCall.log index 7548f5b156..b45b26a666 100644 --- a/tests/ClassMethodCall/ClassMethodCall.log +++ b/tests/ClassMethodCall/ClassMethodCall.log @@ -57,7 +57,7 @@ logic_net 1 logic_typespec 3 logic_var 5 method_func_call 3 -module 3 +module_inst 3 package 3 param_assign 3 parameter 3 @@ -89,7 +89,7 @@ logic_typespec 3 logic_var 8 method_func_call 5 method_task_call 1 -module 3 +module_inst 3 package 3 param_assign 6 parameter 3 @@ -461,7 +461,7 @@ design: (work@door_mod) |vpiClassDefn: \_class_defn: (pack::doorOpen), file:${SURELOG_DIR}/tests/ClassMethodCall/dut.sv, line:21:1, endln:38:9 |uhdmallModules: -\_module: work@door_mod (work@door_mod), file:${SURELOG_DIR}/tests/ClassMethodCall/dut.sv, line:43:1, endln:51:10 +\_module_inst: work@door_mod (work@door_mod), file:${SURELOG_DIR}/tests/ClassMethodCall/dut.sv, line:43:1, endln:51:10 |vpiParent: \_design: (work@door_mod) |vpiFullName:work@door_mod @@ -469,13 +469,13 @@ design: (work@door_mod) |vpiNet: \_logic_net: (work@door_mod.open), line:45:20, endln:45:24 |vpiParent: - \_module: work@door_mod (work@door_mod), file:${SURELOG_DIR}/tests/ClassMethodCall/dut.sv, line:43:1, endln:51:10 + \_module_inst: work@door_mod (work@door_mod), file:${SURELOG_DIR}/tests/ClassMethodCall/dut.sv, line:43:1, endln:51:10 |vpiName:open |vpiFullName:work@door_mod.open |vpiProcess: \_initial: , line:46:5, endln:50:8 |vpiParent: - \_module: work@door_mod (work@door_mod), file:${SURELOG_DIR}/tests/ClassMethodCall/dut.sv, line:43:1, endln:51:10 + \_module_inst: work@door_mod (work@door_mod), file:${SURELOG_DIR}/tests/ClassMethodCall/dut.sv, line:43:1, endln:51:10 |vpiStmt: \_begin: (work@door_mod), line:46:13, endln:50:8 |vpiParent: @@ -514,12 +514,12 @@ design: (work@door_mod) \_ref_obj: (open), line:49:9, endln:49:13 |vpiName:open |uhdmtopModules: -\_module: work@door_mod (work@door_mod), file:${SURELOG_DIR}/tests/ClassMethodCall/dut.sv, line:43:1, endln:51:10 +\_module_inst: work@door_mod (work@door_mod), file:${SURELOG_DIR}/tests/ClassMethodCall/dut.sv, line:43:1, endln:51:10 |vpiName:work@door_mod |vpiVariables: \_class_var: (work@door_mod.open), line:45:20, endln:45:24 |vpiParent: - \_module: work@door_mod (work@door_mod), file:${SURELOG_DIR}/tests/ClassMethodCall/dut.sv, line:43:1, endln:51:10 + \_module_inst: work@door_mod (work@door_mod), file:${SURELOG_DIR}/tests/ClassMethodCall/dut.sv, line:43:1, endln:51:10 |vpiTypespec: \_class_typespec: (pack::doorOpen), line:45:5, endln:45:11 |vpiParent: @@ -536,7 +536,7 @@ design: (work@door_mod) |vpiProcess: \_initial: , line:46:5, endln:50:8 |vpiParent: - \_module: work@door_mod (work@door_mod), file:${SURELOG_DIR}/tests/ClassMethodCall/dut.sv, line:43:1, endln:51:10 + \_module_inst: work@door_mod (work@door_mod), file:${SURELOG_DIR}/tests/ClassMethodCall/dut.sv, line:43:1, endln:51:10 |vpiStmt: \_begin: (work@door_mod), line:46:13, endln:50:8 |vpiParent: diff --git a/tests/ClassMini/ClassMini.log b/tests/ClassMini/ClassMini.log index debdfd6aba..f1f2fcf850 100644 --- a/tests/ClassMini/ClassMini.log +++ b/tests/ClassMini/ClassMini.log @@ -50,7 +50,7 @@ logic_net 1 logic_typespec 3 logic_var 3 method_func_call 2 -module 3 +module_inst 3 package 3 param_assign 3 parameter 3 @@ -79,7 +79,7 @@ logic_typespec 3 logic_var 6 method_func_call 3 method_task_call 1 -module 3 +module_inst 3 package 3 param_assign 6 parameter 3 @@ -348,7 +348,7 @@ design: (work@door_mod) \_design: (work@door_mod) |vpiName:work@toto |uhdmallModules: -\_module: work@door_mod (work@door_mod), file:${SURELOG_DIR}/tests/ClassMini/dut.sv, line:21:1, endln:27:10 +\_module_inst: work@door_mod (work@door_mod), file:${SURELOG_DIR}/tests/ClassMini/dut.sv, line:21:1, endln:27:10 |vpiParent: \_design: (work@door_mod) |vpiFullName:work@door_mod @@ -356,13 +356,13 @@ design: (work@door_mod) |vpiNet: \_logic_net: (work@door_mod.open), line:22:20, endln:22:24 |vpiParent: - \_module: work@door_mod (work@door_mod), file:${SURELOG_DIR}/tests/ClassMini/dut.sv, line:21:1, endln:27:10 + \_module_inst: work@door_mod (work@door_mod), file:${SURELOG_DIR}/tests/ClassMini/dut.sv, line:21:1, endln:27:10 |vpiName:open |vpiFullName:work@door_mod.open |vpiProcess: \_initial: , line:23:5, endln:26:8 |vpiParent: - \_module: work@door_mod (work@door_mod), file:${SURELOG_DIR}/tests/ClassMini/dut.sv, line:21:1, endln:27:10 + \_module_inst: work@door_mod (work@door_mod), file:${SURELOG_DIR}/tests/ClassMini/dut.sv, line:21:1, endln:27:10 |vpiStmt: \_begin: (work@door_mod), line:23:13, endln:26:8 |vpiParent: @@ -393,12 +393,12 @@ design: (work@door_mod) \_ref_obj: (open), line:25:9, endln:25:13 |vpiName:open |uhdmtopModules: -\_module: work@door_mod (work@door_mod), file:${SURELOG_DIR}/tests/ClassMini/dut.sv, line:21:1, endln:27:10 +\_module_inst: work@door_mod (work@door_mod), file:${SURELOG_DIR}/tests/ClassMini/dut.sv, line:21:1, endln:27:10 |vpiName:work@door_mod |vpiVariables: \_class_var: (work@door_mod.open), line:22:20, endln:22:24 |vpiParent: - \_module: work@door_mod (work@door_mod), file:${SURELOG_DIR}/tests/ClassMini/dut.sv, line:21:1, endln:27:10 + \_module_inst: work@door_mod (work@door_mod), file:${SURELOG_DIR}/tests/ClassMini/dut.sv, line:21:1, endln:27:10 |vpiTypespec: \_class_typespec: (pack::doorOpen), line:22:5, endln:22:11 |vpiParent: @@ -415,7 +415,7 @@ design: (work@door_mod) |vpiProcess: \_initial: , line:23:5, endln:26:8 |vpiParent: - \_module: work@door_mod (work@door_mod), file:${SURELOG_DIR}/tests/ClassMini/dut.sv, line:21:1, endln:27:10 + \_module_inst: work@door_mod (work@door_mod), file:${SURELOG_DIR}/tests/ClassMini/dut.sv, line:21:1, endln:27:10 |vpiStmt: \_begin: (work@door_mod), line:23:13, endln:26:8 |vpiParent: diff --git a/tests/ClassParam/ClassParam.log b/tests/ClassParam/ClassParam.log index 8f8c3f6c6f..8849e7efae 100644 --- a/tests/ClassParam/ClassParam.log +++ b/tests/ClassParam/ClassParam.log @@ -33,7 +33,7 @@ design 1 function 1 int_typespec 2 io_decl 1 -module 1 +module_inst 1 operation 1 package 3 param_assign 2 @@ -51,7 +51,7 @@ design 1 function 4 int_typespec 2 io_decl 4 -module 1 +module_inst 1 operation 2 package 3 param_assign 4 diff --git a/tests/ClassParamAsParam/ClassParamAsParam.log b/tests/ClassParamAsParam/ClassParamAsParam.log index 1303039166..570336cfa3 100644 --- a/tests/ClassParamAsParam/ClassParamAsParam.log +++ b/tests/ClassParamAsParam/ClassParamAsParam.log @@ -40,7 +40,7 @@ int_typespec 4 logic_net 1 long_int_typespec 1 method_func_call 1 -module 3 +module_inst 3 param_assign 2 ref_obj 1 type_parameter 6 @@ -57,7 +57,7 @@ int_typespec 4 logic_net 1 long_int_typespec 1 method_func_call 1 -module 3 +module_inst 3 param_assign 6 ref_obj 1 type_parameter 9 @@ -221,7 +221,7 @@ design: (work@top) |vpiDerivedClasses: \_class_defn: (work@config_db), file:${SURELOG_DIR}/tests/ClassParamAsParam/dut.sv, line:14:1, endln:15:9 |uhdmallModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/ClassParamAsParam/dut.sv, line:17:1, endln:19:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ClassParamAsParam/dut.sv, line:17:1, endln:19:10 |vpiParent: \_design: (work@top) |vpiFullName:work@top @@ -229,16 +229,16 @@ design: (work@top) |vpiNet: \_logic_net: (work@top.misc2), line:18:32, endln:18:37 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ClassParamAsParam/dut.sv, line:17:1, endln:19:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ClassParamAsParam/dut.sv, line:17:1, endln:19:10 |vpiName:misc2 |vpiFullName:work@top.misc2 |uhdmtopModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/ClassParamAsParam/dut.sv, line:17:1, endln:19:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ClassParamAsParam/dut.sv, line:17:1, endln:19:10 |vpiName:work@top |vpiVariables: \_class_var: (work@top.misc2), line:18:32, endln:18:43 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ClassParamAsParam/dut.sv, line:17:1, endln:19:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ClassParamAsParam/dut.sv, line:17:1, endln:19:10 |vpiTypespec: \_class_typespec: (config_db), line:18:3, endln:18:12 |vpiParent: diff --git a/tests/ClassScope/ClassScope.log b/tests/ClassScope/ClassScope.log index e43f9095f1..bf70c54489 100644 --- a/tests/ClassScope/ClassScope.log +++ b/tests/ClassScope/ClassScope.log @@ -10414,9 +10414,9 @@ gen_scope_array 16 initial 10 int_typespec 14 integer_typespec 1 -interface 49 +interface_inst 49 logic_typespec 4 -module 49 +module_inst 49 operation 118 package 3 param_assign 226 @@ -10442,9 +10442,9 @@ gen_scope_array 24 initial 114 int_typespec 14 integer_typespec 1 -interface 73 +interface_inst 73 logic_typespec 4 -module 73 +module_inst 73 operation 135 package 3 param_assign 428 @@ -10743,71 +10743,71 @@ design: (work@top) |vpiLhs: \_parameter: (work@C::E), line:5:16, endln:5:17 |uhdmallInterfaces: -\_interface: work@I (work@I), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:25:1, endln:34:13 +\_interface_inst: work@I (work@I), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:25:1, endln:34:13 |vpiParent: \_design: (work@top) |vpiFullName:work@I |vpiParameter: \_parameter: (work@I.DELAY), line:26:15, endln:26:20 |vpiParent: - \_interface: work@I (work@I), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:25:1, endln:34:13 + \_interface_inst: work@I (work@I), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:25:1, endln:34:13 |vpiName:DELAY |vpiFullName:work@I.DELAY |vpiParameter: \_parameter: (work@I.PREFIX), line:27:15, endln:27:21 |vpiParent: - \_interface: work@I (work@I), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:25:1, endln:34:13 + \_interface_inst: work@I (work@I), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:25:1, endln:34:13 |vpiName:PREFIX |vpiFullName:work@I.PREFIX |vpiParameter: \_parameter: (work@I.SUFFIX), line:28:15, endln:28:21 |vpiParent: - \_interface: work@I (work@I), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:25:1, endln:34:13 + \_interface_inst: work@I (work@I), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:25:1, endln:34:13 |vpiName:SUFFIX |vpiFullName:work@I.SUFFIX |vpiParameter: \_parameter: (work@I.E), line:29:15, endln:29:16 |vpiParent: - \_interface: work@I (work@I), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:25:1, endln:34:13 + \_interface_inst: work@I (work@I), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:25:1, endln:34:13 |vpiName:E |vpiFullName:work@I.E |vpiParameter: \_type_parameter: (work@top.genblk8.i3.T), line:30:20, endln:30:21 |vpiParent: - \_interface: work@I (work@top.genblk8.i3), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:60:13, endln:60:119 + \_interface_inst: work@I (work@top.genblk8.i3), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:60:13, endln:60:119 |vpiName:T |vpiInstance: - \_interface: work@I (work@top.genblk8.i3), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:60:13, endln:60:119 + \_interface_inst: work@I (work@top.genblk8.i3), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:60:13, endln:60:119 |vpiFullName:work@top.genblk8.i3.T |vpiParamAssign: \_param_assign: , line:26:15, endln:26:20 |vpiParent: - \_interface: work@I (work@I), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:25:1, endln:34:13 + \_interface_inst: work@I (work@I), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:25:1, endln:34:13 |vpiLhs: \_parameter: (work@I.DELAY), line:26:15, endln:26:20 |vpiParamAssign: \_param_assign: , line:27:15, endln:27:21 |vpiParent: - \_interface: work@I (work@I), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:25:1, endln:34:13 + \_interface_inst: work@I (work@I), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:25:1, endln:34:13 |vpiLhs: \_parameter: (work@I.PREFIX), line:27:15, endln:27:21 |vpiParamAssign: \_param_assign: , line:28:15, endln:28:21 |vpiParent: - \_interface: work@I (work@I), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:25:1, endln:34:13 + \_interface_inst: work@I (work@I), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:25:1, endln:34:13 |vpiLhs: \_parameter: (work@I.SUFFIX), line:28:15, endln:28:21 |vpiParamAssign: \_param_assign: , line:29:15, endln:29:16 |vpiParent: - \_interface: work@I (work@I), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:25:1, endln:34:13 + \_interface_inst: work@I (work@I), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:25:1, endln:34:13 |vpiLhs: \_parameter: (work@I.E), line:29:15, endln:29:16 |vpiDefName:work@I |vpiProcess: \_initial: , line:32:5, endln:33:54 |vpiParent: - \_interface: work@I (work@I), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:25:1, endln:34:13 + \_interface_inst: work@I (work@I), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:25:1, endln:34:13 |vpiStmt: \_delay_control: , line:32:13, endln:32:19 |vpiParent: @@ -10867,71 +10867,71 @@ design: (work@top) |vpiName:$bits |vpiName:$display |uhdmallModules: -\_module: work@M (work@M), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:14:1, endln:23:10 +\_module_inst: work@M (work@M), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:14:1, endln:23:10 |vpiParent: \_design: (work@top) |vpiFullName:work@M |vpiParameter: \_parameter: (work@M.DELAY), line:15:15, endln:15:20 |vpiParent: - \_module: work@M (work@M), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:14:1, endln:23:10 + \_module_inst: work@M (work@M), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:14:1, endln:23:10 |vpiName:DELAY |vpiFullName:work@M.DELAY |vpiParameter: \_parameter: (work@M.PREFIX), line:16:15, endln:16:21 |vpiParent: - \_module: work@M (work@M), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:14:1, endln:23:10 + \_module_inst: work@M (work@M), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:14:1, endln:23:10 |vpiName:PREFIX |vpiFullName:work@M.PREFIX |vpiParameter: \_parameter: (work@M.SUFFIX), line:17:15, endln:17:21 |vpiParent: - \_module: work@M (work@M), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:14:1, endln:23:10 + \_module_inst: work@M (work@M), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:14:1, endln:23:10 |vpiName:SUFFIX |vpiFullName:work@M.SUFFIX |vpiParameter: \_parameter: (work@M.E), line:18:15, endln:18:16 |vpiParent: - \_module: work@M (work@M), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:14:1, endln:23:10 + \_module_inst: work@M (work@M), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:14:1, endln:23:10 |vpiName:E |vpiFullName:work@M.E |vpiParameter: \_type_parameter: (work@top.genblk8.m3.T), line:19:20, endln:19:21 |vpiParent: - \_module: work@M (work@top.genblk8.m3), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:61:13, endln:61:119 + \_module_inst: work@M (work@top.genblk8.m3), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:61:13, endln:61:119 |vpiName:T |vpiInstance: - \_module: work@M (work@top.genblk8.m3), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:61:13, endln:61:119 + \_module_inst: work@M (work@top.genblk8.m3), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:61:13, endln:61:119 |vpiFullName:work@top.genblk8.m3.T |vpiParamAssign: \_param_assign: , line:15:15, endln:15:20 |vpiParent: - \_module: work@M (work@M), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:14:1, endln:23:10 + \_module_inst: work@M (work@M), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:14:1, endln:23:10 |vpiLhs: \_parameter: (work@M.DELAY), line:15:15, endln:15:20 |vpiParamAssign: \_param_assign: , line:16:15, endln:16:21 |vpiParent: - \_module: work@M (work@M), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:14:1, endln:23:10 + \_module_inst: work@M (work@M), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:14:1, endln:23:10 |vpiLhs: \_parameter: (work@M.PREFIX), line:16:15, endln:16:21 |vpiParamAssign: \_param_assign: , line:17:15, endln:17:21 |vpiParent: - \_module: work@M (work@M), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:14:1, endln:23:10 + \_module_inst: work@M (work@M), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:14:1, endln:23:10 |vpiLhs: \_parameter: (work@M.SUFFIX), line:17:15, endln:17:21 |vpiParamAssign: \_param_assign: , line:18:15, endln:18:16 |vpiParent: - \_module: work@M (work@M), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:14:1, endln:23:10 + \_module_inst: work@M (work@M), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:14:1, endln:23:10 |vpiLhs: \_parameter: (work@M.E), line:18:15, endln:18:16 |vpiDefName:work@M |vpiProcess: \_initial: , line:21:5, endln:22:54 |vpiParent: - \_module: work@M (work@M), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:14:1, endln:23:10 + \_module_inst: work@M (work@M), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:14:1, endln:23:10 |vpiStmt: \_delay_control: , line:21:13, endln:21:19 |vpiParent: @@ -10991,14 +10991,14 @@ design: (work@top) |vpiName:$bits |vpiName:$display |uhdmallModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:36:1, endln:74:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:36:1, endln:74:10 |vpiParent: \_design: (work@top) |vpiFullName:work@top |vpiParameter: \_parameter: (work@top.FLAG), line:37:15, endln:37:19 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:36:1, endln:74:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:36:1, endln:74:10 |UINT:1 |vpiTypespec: \_int_typespec: @@ -11007,7 +11007,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.E), line:39:16, endln:39:17 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:36:1, endln:74:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:36:1, endln:74:10 |UINT:3 |vpiTypespec: \_int_typespec: @@ -11017,7 +11017,7 @@ design: (work@top) |vpiParameter: \_type_parameter: (work@top.T), line:40:21, endln:40:22 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:36:1, endln:74:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:36:1, endln:74:10 |vpiName:T |vpiLocalParam:1 |vpiFullName:work@top.T @@ -11074,7 +11074,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:37:15, endln:37:23 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:36:1, endln:74:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:36:1, endln:74:10 |vpiRhs: \_constant: , line:37:22, endln:37:23 |vpiDecompile:1 @@ -11088,7 +11088,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:39:16, endln:39:21 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:36:1, endln:74:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:36:1, endln:74:10 |vpiRhs: \_constant: , line:39:20, endln:39:21 |vpiDecompile:3 @@ -11101,12 +11101,12 @@ design: (work@top) \_parameter: (work@top.E), line:39:16, endln:39:17 |vpiDefName:work@top |uhdmtopModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:36:1, endln:74:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:36:1, endln:74:10 |vpiName:work@top |vpiParameter: \_parameter: (work@top.FLAG), line:37:15, endln:37:19 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:36:1, endln:74:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:36:1, endln:74:10 |UINT:1 |vpiTypespec: \_int_typespec: @@ -11117,7 +11117,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.E), line:39:16, endln:39:17 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:36:1, endln:74:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:36:1, endln:74:10 |UINT:3 |vpiTypespec: \_int_typespec: @@ -11131,7 +11131,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:37:15, endln:37:23 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:36:1, endln:74:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:36:1, endln:74:10 |vpiRhs: \_constant: , line:37:22, endln:37:23 |vpiDecompile:1 @@ -11145,7 +11145,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:39:16, endln:39:21 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:36:1, endln:74:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:36:1, endln:74:10 |vpiRhs: \_constant: , line:39:20, endln:39:21 |vpiDecompile:3 @@ -11162,7 +11162,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.genblk1), line:43:9, endln:62:12 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:36:1, endln:74:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:36:1, endln:74:10 |vpiName:genblk1 |vpiFullName:work@top.genblk1 |vpiGenScope: @@ -11436,8 +11436,8 @@ design: (work@top) |BIN:Z |vpiConstType:3 |vpiName:$display - |vpiModule: - \_module: work@M (work@top.genblk1.m1), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:57:13, endln:57:44 + |vpiModuleInst: + \_module_inst: work@M (work@top.genblk1.m1), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:57:13, endln:57:44 |vpiParent: \_gen_scope: (work@top.genblk1) |vpiName:m1 @@ -11471,7 +11471,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:15:15, endln:15:20 |vpiParent: - \_module: work@M (work@top.genblk1.m1), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:57:13, endln:57:44 + \_module_inst: work@M (work@top.genblk1.m1), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:57:13, endln:57:44 |vpiOverriden:1 |vpiRhs: \_constant: @@ -11484,7 +11484,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:16:15, endln:16:21 |vpiParent: - \_module: work@M (work@top.genblk1.m1), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:57:13, endln:57:44 + \_module_inst: work@M (work@top.genblk1.m1), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:57:13, endln:57:44 |vpiOverriden:1 |vpiRhs: \_constant: @@ -11495,7 +11495,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:17:15, endln:17:21 |vpiParent: - \_module: work@M (work@top.genblk1.m1), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:57:13, endln:57:44 + \_module_inst: work@M (work@top.genblk1.m1), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:57:13, endln:57:44 |vpiOverriden:1 |vpiRhs: \_constant: @@ -11506,7 +11506,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:18:15, endln:18:16 |vpiParent: - \_module: work@M (work@top.genblk1.m1), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:57:13, endln:57:44 + \_module_inst: work@M (work@top.genblk1.m1), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:57:13, endln:57:44 |vpiOverriden:1 |vpiRhs: \_constant: @@ -11522,7 +11522,7 @@ design: (work@top) |vpiProcess: \_initial: , line:21:5, endln:22:54 |vpiParent: - \_module: work@M (work@top.genblk1.m1), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:57:13, endln:57:44 + \_module_inst: work@M (work@top.genblk1.m1), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:57:13, endln:57:44 |vpiStmt: \_delay_control: , line:21:13, endln:21:19 |vpiParent: @@ -11587,8 +11587,8 @@ design: (work@top) \_type_parameter: (work@top.genblk8.m3.T), line:19:20, endln:19:21 |vpiName:$bits |vpiName:$display - |vpiModule: - \_module: work@M (work@top.genblk1.m2), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:59:13, endln:59:53 + |vpiModuleInst: + \_module_inst: work@M (work@top.genblk1.m2), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:59:13, endln:59:53 |vpiParent: \_gen_scope: (work@top.genblk1) |vpiName:m2 @@ -11622,7 +11622,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:15:15, endln:15:20 |vpiParent: - \_module: work@M (work@top.genblk1.m2), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:59:13, endln:59:53 + \_module_inst: work@M (work@top.genblk1.m2), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:59:13, endln:59:53 |vpiOverriden:1 |vpiRhs: \_constant: @@ -11635,7 +11635,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:16:15, endln:16:21 |vpiParent: - \_module: work@M (work@top.genblk1.m2), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:59:13, endln:59:53 + \_module_inst: work@M (work@top.genblk1.m2), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:59:13, endln:59:53 |vpiOverriden:1 |vpiRhs: \_constant: @@ -11646,7 +11646,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:17:15, endln:17:21 |vpiParent: - \_module: work@M (work@top.genblk1.m2), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:59:13, endln:59:53 + \_module_inst: work@M (work@top.genblk1.m2), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:59:13, endln:59:53 |vpiOverriden:1 |vpiRhs: \_constant: @@ -11659,7 +11659,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:18:15, endln:18:16 |vpiParent: - \_module: work@M (work@top.genblk1.m2), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:59:13, endln:59:53 + \_module_inst: work@M (work@top.genblk1.m2), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:59:13, endln:59:53 |vpiOverriden:1 |vpiRhs: \_constant: @@ -11675,7 +11675,7 @@ design: (work@top) |vpiProcess: \_initial: , line:21:5, endln:22:54 |vpiParent: - \_module: work@M (work@top.genblk1.m2), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:59:13, endln:59:53 + \_module_inst: work@M (work@top.genblk1.m2), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:59:13, endln:59:53 |vpiStmt: \_delay_control: , line:21:13, endln:21:19 |vpiParent: @@ -11740,8 +11740,8 @@ design: (work@top) \_type_parameter: (work@top.genblk8.m3.T), line:19:20, endln:19:21 |vpiName:$bits |vpiName:$display - |vpiModule: - \_module: work@M (work@top.genblk1.m3), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:61:13, endln:61:59 + |vpiModuleInst: + \_module_inst: work@M (work@top.genblk1.m3), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:61:13, endln:61:59 |vpiParent: \_gen_scope: (work@top.genblk1) |vpiName:m3 @@ -11775,7 +11775,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:15:15, endln:15:20 |vpiParent: - \_module: work@M (work@top.genblk1.m3), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:61:13, endln:61:59 + \_module_inst: work@M (work@top.genblk1.m3), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:61:13, endln:61:59 |vpiOverriden:1 |vpiRhs: \_constant: @@ -11788,7 +11788,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:16:15, endln:16:21 |vpiParent: - \_module: work@M (work@top.genblk1.m3), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:61:13, endln:61:59 + \_module_inst: work@M (work@top.genblk1.m3), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:61:13, endln:61:59 |vpiOverriden:1 |vpiRhs: \_constant: @@ -11799,7 +11799,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:17:15, endln:17:21 |vpiParent: - \_module: work@M (work@top.genblk1.m3), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:61:13, endln:61:59 + \_module_inst: work@M (work@top.genblk1.m3), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:61:13, endln:61:59 |vpiOverriden:1 |vpiRhs: \_constant: @@ -11812,7 +11812,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:18:15, endln:18:16 |vpiParent: - \_module: work@M (work@top.genblk1.m3), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:61:13, endln:61:59 + \_module_inst: work@M (work@top.genblk1.m3), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:61:13, endln:61:59 |vpiOverriden:1 |vpiRhs: \_constant: @@ -11828,7 +11828,7 @@ design: (work@top) |vpiProcess: \_initial: , line:21:5, endln:22:54 |vpiParent: - \_module: work@M (work@top.genblk1.m3), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:61:13, endln:61:59 + \_module_inst: work@M (work@top.genblk1.m3), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:61:13, endln:61:59 |vpiStmt: \_delay_control: , line:21:13, endln:21:19 |vpiParent: @@ -11893,8 +11893,8 @@ design: (work@top) \_type_parameter: (work@top.genblk8.m3.T), line:19:20, endln:19:21 |vpiName:$bits |vpiName:$display - |vpiInterface: - \_interface: work@I (work@top.genblk1.i1), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:56:13, endln:56:44 + |vpiInterfaceInst: + \_interface_inst: work@I (work@top.genblk1.i1), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:56:13, endln:56:44 |vpiParent: \_gen_scope: (work@top.genblk1) |vpiName:i1 @@ -11902,25 +11902,25 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.genblk1.i1.DELAY), line:26:15, endln:26:20 |vpiParent: - \_interface: work@I (work@top.genblk1.i1), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:56:13, endln:56:44 + \_interface_inst: work@I (work@top.genblk1.i1), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:56:13, endln:56:44 |vpiName:DELAY |vpiFullName:work@top.genblk1.i1.DELAY |vpiParameter: \_parameter: (work@top.genblk1.i1.PREFIX), line:27:15, endln:27:21 |vpiParent: - \_interface: work@I (work@top.genblk1.i1), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:56:13, endln:56:44 + \_interface_inst: work@I (work@top.genblk1.i1), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:56:13, endln:56:44 |vpiName:PREFIX |vpiFullName:work@top.genblk1.i1.PREFIX |vpiParameter: \_parameter: (work@top.genblk1.i1.SUFFIX), line:28:15, endln:28:21 |vpiParent: - \_interface: work@I (work@top.genblk1.i1), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:56:13, endln:56:44 + \_interface_inst: work@I (work@top.genblk1.i1), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:56:13, endln:56:44 |vpiName:SUFFIX |vpiFullName:work@top.genblk1.i1.SUFFIX |vpiParameter: \_parameter: (work@top.genblk1.i1.E), line:29:15, endln:29:16 |vpiParent: - \_interface: work@I (work@top.genblk1.i1), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:56:13, endln:56:44 + \_interface_inst: work@I (work@top.genblk1.i1), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:56:13, endln:56:44 |vpiName:E |vpiFullName:work@top.genblk1.i1.E |vpiParameter: @@ -11928,7 +11928,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:26:15, endln:26:20 |vpiParent: - \_interface: work@I (work@top.genblk1.i1), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:56:13, endln:56:44 + \_interface_inst: work@I (work@top.genblk1.i1), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:56:13, endln:56:44 |vpiOverriden:1 |vpiRhs: \_constant: @@ -11945,7 +11945,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:27:15, endln:27:21 |vpiParent: - \_interface: work@I (work@top.genblk1.i1), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:56:13, endln:56:44 + \_interface_inst: work@I (work@top.genblk1.i1), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:56:13, endln:56:44 |vpiOverriden:1 |vpiRhs: \_constant: @@ -11960,7 +11960,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:28:15, endln:28:21 |vpiParent: - \_interface: work@I (work@top.genblk1.i1), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:56:13, endln:56:44 + \_interface_inst: work@I (work@top.genblk1.i1), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:56:13, endln:56:44 |vpiOverriden:1 |vpiRhs: \_constant: @@ -11975,7 +11975,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:29:15, endln:29:16 |vpiParent: - \_interface: work@I (work@top.genblk1.i1), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:56:13, endln:56:44 + \_interface_inst: work@I (work@top.genblk1.i1), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:56:13, endln:56:44 |vpiOverriden:1 |vpiRhs: \_constant: @@ -11995,7 +11995,7 @@ design: (work@top) |vpiProcess: \_initial: , line:32:5, endln:33:54 |vpiParent: - \_interface: work@I (work@top.genblk1.i1), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:56:13, endln:56:44 + \_interface_inst: work@I (work@top.genblk1.i1), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:56:13, endln:56:44 |vpiStmt: \_delay_control: , line:32:13, endln:32:19 |vpiParent: @@ -12060,8 +12060,8 @@ design: (work@top) \_type_parameter: (work@top.genblk8.i3.T), line:30:20, endln:30:21 |vpiName:$bits |vpiName:$display - |vpiInterface: - \_interface: work@I (work@top.genblk1.i2), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:58:13, endln:58:53 + |vpiInterfaceInst: + \_interface_inst: work@I (work@top.genblk1.i2), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:58:13, endln:58:53 |vpiParent: \_gen_scope: (work@top.genblk1) |vpiName:i2 @@ -12069,25 +12069,25 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.genblk1.i2.DELAY), line:26:15, endln:26:20 |vpiParent: - \_interface: work@I (work@top.genblk1.i2), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:58:13, endln:58:53 + \_interface_inst: work@I (work@top.genblk1.i2), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:58:13, endln:58:53 |vpiName:DELAY |vpiFullName:work@top.genblk1.i2.DELAY |vpiParameter: \_parameter: (work@top.genblk1.i2.PREFIX), line:27:15, endln:27:21 |vpiParent: - \_interface: work@I (work@top.genblk1.i2), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:58:13, endln:58:53 + \_interface_inst: work@I (work@top.genblk1.i2), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:58:13, endln:58:53 |vpiName:PREFIX |vpiFullName:work@top.genblk1.i2.PREFIX |vpiParameter: \_parameter: (work@top.genblk1.i2.SUFFIX), line:28:15, endln:28:21 |vpiParent: - \_interface: work@I (work@top.genblk1.i2), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:58:13, endln:58:53 + \_interface_inst: work@I (work@top.genblk1.i2), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:58:13, endln:58:53 |vpiName:SUFFIX |vpiFullName:work@top.genblk1.i2.SUFFIX |vpiParameter: \_parameter: (work@top.genblk1.i2.E), line:29:15, endln:29:16 |vpiParent: - \_interface: work@I (work@top.genblk1.i2), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:58:13, endln:58:53 + \_interface_inst: work@I (work@top.genblk1.i2), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:58:13, endln:58:53 |vpiName:E |vpiFullName:work@top.genblk1.i2.E |vpiParameter: @@ -12095,7 +12095,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:26:15, endln:26:20 |vpiParent: - \_interface: work@I (work@top.genblk1.i2), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:58:13, endln:58:53 + \_interface_inst: work@I (work@top.genblk1.i2), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:58:13, endln:58:53 |vpiOverriden:1 |vpiRhs: \_constant: @@ -12112,7 +12112,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:27:15, endln:27:21 |vpiParent: - \_interface: work@I (work@top.genblk1.i2), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:58:13, endln:58:53 + \_interface_inst: work@I (work@top.genblk1.i2), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:58:13, endln:58:53 |vpiOverriden:1 |vpiRhs: \_constant: @@ -12127,7 +12127,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:28:15, endln:28:21 |vpiParent: - \_interface: work@I (work@top.genblk1.i2), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:58:13, endln:58:53 + \_interface_inst: work@I (work@top.genblk1.i2), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:58:13, endln:58:53 |vpiOverriden:1 |vpiRhs: \_constant: @@ -12144,7 +12144,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:29:15, endln:29:16 |vpiParent: - \_interface: work@I (work@top.genblk1.i2), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:58:13, endln:58:53 + \_interface_inst: work@I (work@top.genblk1.i2), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:58:13, endln:58:53 |vpiOverriden:1 |vpiRhs: \_constant: @@ -12164,7 +12164,7 @@ design: (work@top) |vpiProcess: \_initial: , line:32:5, endln:33:54 |vpiParent: - \_interface: work@I (work@top.genblk1.i2), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:58:13, endln:58:53 + \_interface_inst: work@I (work@top.genblk1.i2), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:58:13, endln:58:53 |vpiStmt: \_delay_control: , line:32:13, endln:32:19 |vpiParent: @@ -12229,8 +12229,8 @@ design: (work@top) \_type_parameter: (work@top.genblk8.i3.T), line:30:20, endln:30:21 |vpiName:$bits |vpiName:$display - |vpiInterface: - \_interface: work@I (work@top.genblk1.i3), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:60:13, endln:60:59 + |vpiInterfaceInst: + \_interface_inst: work@I (work@top.genblk1.i3), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:60:13, endln:60:59 |vpiParent: \_gen_scope: (work@top.genblk1) |vpiName:i3 @@ -12238,25 +12238,25 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.genblk1.i3.DELAY), line:26:15, endln:26:20 |vpiParent: - \_interface: work@I (work@top.genblk1.i3), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:60:13, endln:60:59 + \_interface_inst: work@I (work@top.genblk1.i3), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:60:13, endln:60:59 |vpiName:DELAY |vpiFullName:work@top.genblk1.i3.DELAY |vpiParameter: \_parameter: (work@top.genblk1.i3.PREFIX), line:27:15, endln:27:21 |vpiParent: - \_interface: work@I (work@top.genblk1.i3), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:60:13, endln:60:59 + \_interface_inst: work@I (work@top.genblk1.i3), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:60:13, endln:60:59 |vpiName:PREFIX |vpiFullName:work@top.genblk1.i3.PREFIX |vpiParameter: \_parameter: (work@top.genblk1.i3.SUFFIX), line:28:15, endln:28:21 |vpiParent: - \_interface: work@I (work@top.genblk1.i3), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:60:13, endln:60:59 + \_interface_inst: work@I (work@top.genblk1.i3), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:60:13, endln:60:59 |vpiName:SUFFIX |vpiFullName:work@top.genblk1.i3.SUFFIX |vpiParameter: \_parameter: (work@top.genblk1.i3.E), line:29:15, endln:29:16 |vpiParent: - \_interface: work@I (work@top.genblk1.i3), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:60:13, endln:60:59 + \_interface_inst: work@I (work@top.genblk1.i3), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:60:13, endln:60:59 |vpiName:E |vpiFullName:work@top.genblk1.i3.E |vpiParameter: @@ -12264,7 +12264,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:26:15, endln:26:20 |vpiParent: - \_interface: work@I (work@top.genblk1.i3), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:60:13, endln:60:59 + \_interface_inst: work@I (work@top.genblk1.i3), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:60:13, endln:60:59 |vpiOverriden:1 |vpiRhs: \_constant: @@ -12281,7 +12281,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:27:15, endln:27:21 |vpiParent: - \_interface: work@I (work@top.genblk1.i3), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:60:13, endln:60:59 + \_interface_inst: work@I (work@top.genblk1.i3), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:60:13, endln:60:59 |vpiOverriden:1 |vpiRhs: \_constant: @@ -12296,7 +12296,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:28:15, endln:28:21 |vpiParent: - \_interface: work@I (work@top.genblk1.i3), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:60:13, endln:60:59 + \_interface_inst: work@I (work@top.genblk1.i3), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:60:13, endln:60:59 |vpiOverriden:1 |vpiRhs: \_constant: @@ -12313,7 +12313,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:29:15, endln:29:16 |vpiParent: - \_interface: work@I (work@top.genblk1.i3), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:60:13, endln:60:59 + \_interface_inst: work@I (work@top.genblk1.i3), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:60:13, endln:60:59 |vpiOverriden:1 |vpiRhs: \_constant: @@ -12333,7 +12333,7 @@ design: (work@top) |vpiProcess: \_initial: , line:32:5, endln:33:54 |vpiParent: - \_interface: work@I (work@top.genblk1.i3), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:60:13, endln:60:59 + \_interface_inst: work@I (work@top.genblk1.i3), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:60:13, endln:60:59 |vpiStmt: \_delay_control: , line:32:13, endln:32:19 |vpiParent: @@ -12401,7 +12401,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.genblk2), line:43:9, endln:62:12 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:36:1, endln:74:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:36:1, endln:74:10 |vpiName:genblk2 |vpiFullName:work@top.genblk2 |vpiGenScope: @@ -12675,8 +12675,8 @@ design: (work@top) |BIN:Z |vpiConstType:3 |vpiName:$display - |vpiModule: - \_module: work@M (work@top.genblk2.m1), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:57:13, endln:57:53 + |vpiModuleInst: + \_module_inst: work@M (work@top.genblk2.m1), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:57:13, endln:57:53 |vpiParent: \_gen_scope: (work@top.genblk2) |vpiName:m1 @@ -12710,7 +12710,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:15:15, endln:15:20 |vpiParent: - \_module: work@M (work@top.genblk2.m1), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:57:13, endln:57:53 + \_module_inst: work@M (work@top.genblk2.m1), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:57:13, endln:57:53 |vpiOverriden:1 |vpiRhs: \_constant: @@ -12723,7 +12723,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:16:15, endln:16:21 |vpiParent: - \_module: work@M (work@top.genblk2.m1), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:57:13, endln:57:53 + \_module_inst: work@M (work@top.genblk2.m1), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:57:13, endln:57:53 |vpiOverriden:1 |vpiRhs: \_constant: @@ -12736,7 +12736,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:17:15, endln:17:21 |vpiParent: - \_module: work@M (work@top.genblk2.m1), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:57:13, endln:57:53 + \_module_inst: work@M (work@top.genblk2.m1), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:57:13, endln:57:53 |vpiOverriden:1 |vpiRhs: \_constant: @@ -12747,7 +12747,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:18:15, endln:18:16 |vpiParent: - \_module: work@M (work@top.genblk2.m1), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:57:13, endln:57:53 + \_module_inst: work@M (work@top.genblk2.m1), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:57:13, endln:57:53 |vpiOverriden:1 |vpiRhs: \_constant: @@ -12763,7 +12763,7 @@ design: (work@top) |vpiProcess: \_initial: , line:21:5, endln:22:54 |vpiParent: - \_module: work@M (work@top.genblk2.m1), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:57:13, endln:57:53 + \_module_inst: work@M (work@top.genblk2.m1), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:57:13, endln:57:53 |vpiStmt: \_delay_control: , line:21:13, endln:21:19 |vpiParent: @@ -12828,8 +12828,8 @@ design: (work@top) \_type_parameter: (work@top.genblk8.m3.T), line:19:20, endln:19:21 |vpiName:$bits |vpiName:$display - |vpiModule: - \_module: work@M (work@top.genblk2.m2), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:59:13, endln:59:62 + |vpiModuleInst: + \_module_inst: work@M (work@top.genblk2.m2), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:59:13, endln:59:62 |vpiParent: \_gen_scope: (work@top.genblk2) |vpiName:m2 @@ -12863,7 +12863,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:15:15, endln:15:20 |vpiParent: - \_module: work@M (work@top.genblk2.m2), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:59:13, endln:59:62 + \_module_inst: work@M (work@top.genblk2.m2), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:59:13, endln:59:62 |vpiOverriden:1 |vpiRhs: \_constant: @@ -12876,7 +12876,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:16:15, endln:16:21 |vpiParent: - \_module: work@M (work@top.genblk2.m2), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:59:13, endln:59:62 + \_module_inst: work@M (work@top.genblk2.m2), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:59:13, endln:59:62 |vpiOverriden:1 |vpiRhs: \_constant: @@ -12889,7 +12889,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:17:15, endln:17:21 |vpiParent: - \_module: work@M (work@top.genblk2.m2), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:59:13, endln:59:62 + \_module_inst: work@M (work@top.genblk2.m2), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:59:13, endln:59:62 |vpiOverriden:1 |vpiRhs: \_constant: @@ -12902,7 +12902,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:18:15, endln:18:16 |vpiParent: - \_module: work@M (work@top.genblk2.m2), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:59:13, endln:59:62 + \_module_inst: work@M (work@top.genblk2.m2), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:59:13, endln:59:62 |vpiLhs: \_parameter: (work@top.genblk2.m2.E), line:18:15, endln:18:16 |vpiDefName:work@M @@ -12911,7 +12911,7 @@ design: (work@top) |vpiProcess: \_initial: , line:21:5, endln:22:54 |vpiParent: - \_module: work@M (work@top.genblk2.m2), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:59:13, endln:59:62 + \_module_inst: work@M (work@top.genblk2.m2), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:59:13, endln:59:62 |vpiStmt: \_delay_control: , line:21:13, endln:21:19 |vpiParent: @@ -12976,8 +12976,8 @@ design: (work@top) \_type_parameter: (work@top.genblk8.m3.T), line:19:20, endln:19:21 |vpiName:$bits |vpiName:$display - |vpiModule: - \_module: work@M (work@top.genblk2.m3), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:61:13, endln:61:68 + |vpiModuleInst: + \_module_inst: work@M (work@top.genblk2.m3), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:61:13, endln:61:68 |vpiParent: \_gen_scope: (work@top.genblk2) |vpiName:m3 @@ -13011,7 +13011,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:15:15, endln:15:20 |vpiParent: - \_module: work@M (work@top.genblk2.m3), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:61:13, endln:61:68 + \_module_inst: work@M (work@top.genblk2.m3), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:61:13, endln:61:68 |vpiOverriden:1 |vpiRhs: \_constant: @@ -13024,7 +13024,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:16:15, endln:16:21 |vpiParent: - \_module: work@M (work@top.genblk2.m3), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:61:13, endln:61:68 + \_module_inst: work@M (work@top.genblk2.m3), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:61:13, endln:61:68 |vpiOverriden:1 |vpiRhs: \_constant: @@ -13037,7 +13037,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:17:15, endln:17:21 |vpiParent: - \_module: work@M (work@top.genblk2.m3), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:61:13, endln:61:68 + \_module_inst: work@M (work@top.genblk2.m3), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:61:13, endln:61:68 |vpiOverriden:1 |vpiRhs: \_constant: @@ -13050,7 +13050,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:18:15, endln:18:16 |vpiParent: - \_module: work@M (work@top.genblk2.m3), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:61:13, endln:61:68 + \_module_inst: work@M (work@top.genblk2.m3), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:61:13, endln:61:68 |vpiOverriden:1 |vpiRhs: \_constant: @@ -13066,7 +13066,7 @@ design: (work@top) |vpiProcess: \_initial: , line:21:5, endln:22:54 |vpiParent: - \_module: work@M (work@top.genblk2.m3), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:61:13, endln:61:68 + \_module_inst: work@M (work@top.genblk2.m3), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:61:13, endln:61:68 |vpiStmt: \_delay_control: , line:21:13, endln:21:19 |vpiParent: @@ -13131,8 +13131,8 @@ design: (work@top) \_type_parameter: (work@top.genblk8.m3.T), line:19:20, endln:19:21 |vpiName:$bits |vpiName:$display - |vpiInterface: - \_interface: work@I (work@top.genblk2.i1), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:56:13, endln:56:53 + |vpiInterfaceInst: + \_interface_inst: work@I (work@top.genblk2.i1), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:56:13, endln:56:53 |vpiParent: \_gen_scope: (work@top.genblk2) |vpiName:i1 @@ -13140,25 +13140,25 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.genblk2.i1.DELAY), line:26:15, endln:26:20 |vpiParent: - \_interface: work@I (work@top.genblk2.i1), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:56:13, endln:56:53 + \_interface_inst: work@I (work@top.genblk2.i1), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:56:13, endln:56:53 |vpiName:DELAY |vpiFullName:work@top.genblk2.i1.DELAY |vpiParameter: \_parameter: (work@top.genblk2.i1.PREFIX), line:27:15, endln:27:21 |vpiParent: - \_interface: work@I (work@top.genblk2.i1), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:56:13, endln:56:53 + \_interface_inst: work@I (work@top.genblk2.i1), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:56:13, endln:56:53 |vpiName:PREFIX |vpiFullName:work@top.genblk2.i1.PREFIX |vpiParameter: \_parameter: (work@top.genblk2.i1.SUFFIX), line:28:15, endln:28:21 |vpiParent: - \_interface: work@I (work@top.genblk2.i1), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:56:13, endln:56:53 + \_interface_inst: work@I (work@top.genblk2.i1), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:56:13, endln:56:53 |vpiName:SUFFIX |vpiFullName:work@top.genblk2.i1.SUFFIX |vpiParameter: \_parameter: (work@top.genblk2.i1.E), line:29:15, endln:29:16 |vpiParent: - \_interface: work@I (work@top.genblk2.i1), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:56:13, endln:56:53 + \_interface_inst: work@I (work@top.genblk2.i1), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:56:13, endln:56:53 |vpiName:E |vpiFullName:work@top.genblk2.i1.E |vpiParameter: @@ -13166,7 +13166,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:26:15, endln:26:20 |vpiParent: - \_interface: work@I (work@top.genblk2.i1), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:56:13, endln:56:53 + \_interface_inst: work@I (work@top.genblk2.i1), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:56:13, endln:56:53 |vpiOverriden:1 |vpiRhs: \_constant: @@ -13183,7 +13183,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:27:15, endln:27:21 |vpiParent: - \_interface: work@I (work@top.genblk2.i1), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:56:13, endln:56:53 + \_interface_inst: work@I (work@top.genblk2.i1), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:56:13, endln:56:53 |vpiOverriden:1 |vpiRhs: \_constant: @@ -13200,7 +13200,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:28:15, endln:28:21 |vpiParent: - \_interface: work@I (work@top.genblk2.i1), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:56:13, endln:56:53 + \_interface_inst: work@I (work@top.genblk2.i1), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:56:13, endln:56:53 |vpiOverriden:1 |vpiRhs: \_constant: @@ -13215,7 +13215,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:29:15, endln:29:16 |vpiParent: - \_interface: work@I (work@top.genblk2.i1), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:56:13, endln:56:53 + \_interface_inst: work@I (work@top.genblk2.i1), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:56:13, endln:56:53 |vpiOverriden:1 |vpiRhs: \_constant: @@ -13235,7 +13235,7 @@ design: (work@top) |vpiProcess: \_initial: , line:32:5, endln:33:54 |vpiParent: - \_interface: work@I (work@top.genblk2.i1), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:56:13, endln:56:53 + \_interface_inst: work@I (work@top.genblk2.i1), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:56:13, endln:56:53 |vpiStmt: \_delay_control: , line:32:13, endln:32:19 |vpiParent: @@ -13300,8 +13300,8 @@ design: (work@top) \_type_parameter: (work@top.genblk8.i3.T), line:30:20, endln:30:21 |vpiName:$bits |vpiName:$display - |vpiInterface: - \_interface: work@I (work@top.genblk2.i2), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:58:13, endln:58:62 + |vpiInterfaceInst: + \_interface_inst: work@I (work@top.genblk2.i2), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:58:13, endln:58:62 |vpiParent: \_gen_scope: (work@top.genblk2) |vpiName:i2 @@ -13309,25 +13309,25 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.genblk2.i2.DELAY), line:26:15, endln:26:20 |vpiParent: - \_interface: work@I (work@top.genblk2.i2), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:58:13, endln:58:62 + \_interface_inst: work@I (work@top.genblk2.i2), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:58:13, endln:58:62 |vpiName:DELAY |vpiFullName:work@top.genblk2.i2.DELAY |vpiParameter: \_parameter: (work@top.genblk2.i2.PREFIX), line:27:15, endln:27:21 |vpiParent: - \_interface: work@I (work@top.genblk2.i2), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:58:13, endln:58:62 + \_interface_inst: work@I (work@top.genblk2.i2), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:58:13, endln:58:62 |vpiName:PREFIX |vpiFullName:work@top.genblk2.i2.PREFIX |vpiParameter: \_parameter: (work@top.genblk2.i2.SUFFIX), line:28:15, endln:28:21 |vpiParent: - \_interface: work@I (work@top.genblk2.i2), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:58:13, endln:58:62 + \_interface_inst: work@I (work@top.genblk2.i2), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:58:13, endln:58:62 |vpiName:SUFFIX |vpiFullName:work@top.genblk2.i2.SUFFIX |vpiParameter: \_parameter: (work@top.genblk2.i2.E), line:29:15, endln:29:16 |vpiParent: - \_interface: work@I (work@top.genblk2.i2), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:58:13, endln:58:62 + \_interface_inst: work@I (work@top.genblk2.i2), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:58:13, endln:58:62 |vpiName:E |vpiFullName:work@top.genblk2.i2.E |vpiParameter: @@ -13335,7 +13335,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:26:15, endln:26:20 |vpiParent: - \_interface: work@I (work@top.genblk2.i2), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:58:13, endln:58:62 + \_interface_inst: work@I (work@top.genblk2.i2), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:58:13, endln:58:62 |vpiOverriden:1 |vpiRhs: \_constant: @@ -13352,7 +13352,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:27:15, endln:27:21 |vpiParent: - \_interface: work@I (work@top.genblk2.i2), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:58:13, endln:58:62 + \_interface_inst: work@I (work@top.genblk2.i2), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:58:13, endln:58:62 |vpiOverriden:1 |vpiRhs: \_constant: @@ -13369,7 +13369,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:28:15, endln:28:21 |vpiParent: - \_interface: work@I (work@top.genblk2.i2), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:58:13, endln:58:62 + \_interface_inst: work@I (work@top.genblk2.i2), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:58:13, endln:58:62 |vpiOverriden:1 |vpiRhs: \_constant: @@ -13386,7 +13386,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:29:15, endln:29:16 |vpiParent: - \_interface: work@I (work@top.genblk2.i2), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:58:13, endln:58:62 + \_interface_inst: work@I (work@top.genblk2.i2), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:58:13, endln:58:62 |vpiRhs: \_constant: |vpiDecompile:3 @@ -13405,7 +13405,7 @@ design: (work@top) |vpiProcess: \_initial: , line:32:5, endln:33:54 |vpiParent: - \_interface: work@I (work@top.genblk2.i2), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:58:13, endln:58:62 + \_interface_inst: work@I (work@top.genblk2.i2), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:58:13, endln:58:62 |vpiStmt: \_delay_control: , line:32:13, endln:32:19 |vpiParent: @@ -13470,8 +13470,8 @@ design: (work@top) \_type_parameter: (work@top.genblk8.i3.T), line:30:20, endln:30:21 |vpiName:$bits |vpiName:$display - |vpiInterface: - \_interface: work@I (work@top.genblk2.i3), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:60:13, endln:60:68 + |vpiInterfaceInst: + \_interface_inst: work@I (work@top.genblk2.i3), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:60:13, endln:60:68 |vpiParent: \_gen_scope: (work@top.genblk2) |vpiName:i3 @@ -13479,25 +13479,25 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.genblk2.i3.DELAY), line:26:15, endln:26:20 |vpiParent: - \_interface: work@I (work@top.genblk2.i3), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:60:13, endln:60:68 + \_interface_inst: work@I (work@top.genblk2.i3), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:60:13, endln:60:68 |vpiName:DELAY |vpiFullName:work@top.genblk2.i3.DELAY |vpiParameter: \_parameter: (work@top.genblk2.i3.PREFIX), line:27:15, endln:27:21 |vpiParent: - \_interface: work@I (work@top.genblk2.i3), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:60:13, endln:60:68 + \_interface_inst: work@I (work@top.genblk2.i3), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:60:13, endln:60:68 |vpiName:PREFIX |vpiFullName:work@top.genblk2.i3.PREFIX |vpiParameter: \_parameter: (work@top.genblk2.i3.SUFFIX), line:28:15, endln:28:21 |vpiParent: - \_interface: work@I (work@top.genblk2.i3), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:60:13, endln:60:68 + \_interface_inst: work@I (work@top.genblk2.i3), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:60:13, endln:60:68 |vpiName:SUFFIX |vpiFullName:work@top.genblk2.i3.SUFFIX |vpiParameter: \_parameter: (work@top.genblk2.i3.E), line:29:15, endln:29:16 |vpiParent: - \_interface: work@I (work@top.genblk2.i3), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:60:13, endln:60:68 + \_interface_inst: work@I (work@top.genblk2.i3), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:60:13, endln:60:68 |vpiName:E |vpiFullName:work@top.genblk2.i3.E |vpiParameter: @@ -13505,7 +13505,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:26:15, endln:26:20 |vpiParent: - \_interface: work@I (work@top.genblk2.i3), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:60:13, endln:60:68 + \_interface_inst: work@I (work@top.genblk2.i3), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:60:13, endln:60:68 |vpiOverriden:1 |vpiRhs: \_constant: @@ -13522,7 +13522,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:27:15, endln:27:21 |vpiParent: - \_interface: work@I (work@top.genblk2.i3), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:60:13, endln:60:68 + \_interface_inst: work@I (work@top.genblk2.i3), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:60:13, endln:60:68 |vpiOverriden:1 |vpiRhs: \_constant: @@ -13539,7 +13539,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:28:15, endln:28:21 |vpiParent: - \_interface: work@I (work@top.genblk2.i3), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:60:13, endln:60:68 + \_interface_inst: work@I (work@top.genblk2.i3), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:60:13, endln:60:68 |vpiOverriden:1 |vpiRhs: \_constant: @@ -13556,7 +13556,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:29:15, endln:29:16 |vpiParent: - \_interface: work@I (work@top.genblk2.i3), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:60:13, endln:60:68 + \_interface_inst: work@I (work@top.genblk2.i3), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:60:13, endln:60:68 |vpiOverriden:1 |vpiRhs: \_constant: @@ -13576,7 +13576,7 @@ design: (work@top) |vpiProcess: \_initial: , line:32:5, endln:33:54 |vpiParent: - \_interface: work@I (work@top.genblk2.i3), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:60:13, endln:60:68 + \_interface_inst: work@I (work@top.genblk2.i3), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:60:13, endln:60:68 |vpiStmt: \_delay_control: , line:32:13, endln:32:19 |vpiParent: @@ -13644,7 +13644,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.genblk3), line:43:9, endln:62:12 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:36:1, endln:74:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:36:1, endln:74:10 |vpiName:genblk3 |vpiFullName:work@top.genblk3 |vpiGenScope: @@ -13903,8 +13903,8 @@ design: (work@top) |BIN:Z |vpiConstType:3 |vpiName:$display - |vpiModule: - \_module: work@M (work@top.genblk3.m1), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:57:13, endln:57:62 + |vpiModuleInst: + \_module_inst: work@M (work@top.genblk3.m1), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:57:13, endln:57:62 |vpiParent: \_gen_scope: (work@top.genblk3) |vpiName:m1 @@ -13938,7 +13938,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:15:15, endln:15:20 |vpiParent: - \_module: work@M (work@top.genblk3.m1), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:57:13, endln:57:62 + \_module_inst: work@M (work@top.genblk3.m1), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:57:13, endln:57:62 |vpiOverriden:1 |vpiRhs: \_constant: @@ -13951,7 +13951,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:16:15, endln:16:21 |vpiParent: - \_module: work@M (work@top.genblk3.m1), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:57:13, endln:57:62 + \_module_inst: work@M (work@top.genblk3.m1), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:57:13, endln:57:62 |vpiOverriden:1 |vpiRhs: \_constant: @@ -13964,7 +13964,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:17:15, endln:17:21 |vpiParent: - \_module: work@M (work@top.genblk3.m1), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:57:13, endln:57:62 + \_module_inst: work@M (work@top.genblk3.m1), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:57:13, endln:57:62 |vpiOverriden:1 |vpiRhs: \_constant: @@ -13975,7 +13975,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:18:15, endln:18:16 |vpiParent: - \_module: work@M (work@top.genblk3.m1), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:57:13, endln:57:62 + \_module_inst: work@M (work@top.genblk3.m1), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:57:13, endln:57:62 |vpiLhs: \_parameter: (work@top.genblk3.m1.E), line:18:15, endln:18:16 |vpiDefName:work@M @@ -13984,7 +13984,7 @@ design: (work@top) |vpiProcess: \_initial: , line:21:5, endln:22:54 |vpiParent: - \_module: work@M (work@top.genblk3.m1), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:57:13, endln:57:62 + \_module_inst: work@M (work@top.genblk3.m1), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:57:13, endln:57:62 |vpiStmt: \_delay_control: , line:21:13, endln:21:19 |vpiParent: @@ -14049,8 +14049,8 @@ design: (work@top) \_type_parameter: (work@top.genblk8.m3.T), line:19:20, endln:19:21 |vpiName:$bits |vpiName:$display - |vpiModule: - \_module: work@M (work@top.genblk3.m2), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:59:13, endln:59:71 + |vpiModuleInst: + \_module_inst: work@M (work@top.genblk3.m2), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:59:13, endln:59:71 |vpiParent: \_gen_scope: (work@top.genblk3) |vpiName:m2 @@ -14084,7 +14084,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:15:15, endln:15:20 |vpiParent: - \_module: work@M (work@top.genblk3.m2), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:59:13, endln:59:71 + \_module_inst: work@M (work@top.genblk3.m2), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:59:13, endln:59:71 |vpiOverriden:1 |vpiRhs: \_constant: @@ -14097,7 +14097,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:16:15, endln:16:21 |vpiParent: - \_module: work@M (work@top.genblk3.m2), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:59:13, endln:59:71 + \_module_inst: work@M (work@top.genblk3.m2), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:59:13, endln:59:71 |vpiOverriden:1 |vpiRhs: \_constant: @@ -14110,7 +14110,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:17:15, endln:17:21 |vpiParent: - \_module: work@M (work@top.genblk3.m2), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:59:13, endln:59:71 + \_module_inst: work@M (work@top.genblk3.m2), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:59:13, endln:59:71 |vpiOverriden:1 |vpiRhs: \_constant: @@ -14123,7 +14123,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:18:15, endln:18:16 |vpiParent: - \_module: work@M (work@top.genblk3.m2), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:59:13, endln:59:71 + \_module_inst: work@M (work@top.genblk3.m2), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:59:13, endln:59:71 |vpiLhs: \_parameter: (work@top.genblk3.m2.E), line:18:15, endln:18:16 |vpiDefName:work@M @@ -14132,7 +14132,7 @@ design: (work@top) |vpiProcess: \_initial: , line:21:5, endln:22:54 |vpiParent: - \_module: work@M (work@top.genblk3.m2), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:59:13, endln:59:71 + \_module_inst: work@M (work@top.genblk3.m2), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:59:13, endln:59:71 |vpiStmt: \_delay_control: , line:21:13, endln:21:19 |vpiParent: @@ -14197,8 +14197,8 @@ design: (work@top) \_type_parameter: (work@top.genblk8.m3.T), line:19:20, endln:19:21 |vpiName:$bits |vpiName:$display - |vpiModule: - \_module: work@M (work@top.genblk3.m3), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:61:13, endln:61:77 + |vpiModuleInst: + \_module_inst: work@M (work@top.genblk3.m3), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:61:13, endln:61:77 |vpiParent: \_gen_scope: (work@top.genblk3) |vpiName:m3 @@ -14232,7 +14232,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:15:15, endln:15:20 |vpiParent: - \_module: work@M (work@top.genblk3.m3), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:61:13, endln:61:77 + \_module_inst: work@M (work@top.genblk3.m3), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:61:13, endln:61:77 |vpiOverriden:1 |vpiRhs: \_constant: @@ -14245,7 +14245,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:16:15, endln:16:21 |vpiParent: - \_module: work@M (work@top.genblk3.m3), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:61:13, endln:61:77 + \_module_inst: work@M (work@top.genblk3.m3), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:61:13, endln:61:77 |vpiOverriden:1 |vpiRhs: \_constant: @@ -14258,7 +14258,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:17:15, endln:17:21 |vpiParent: - \_module: work@M (work@top.genblk3.m3), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:61:13, endln:61:77 + \_module_inst: work@M (work@top.genblk3.m3), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:61:13, endln:61:77 |vpiOverriden:1 |vpiRhs: \_constant: @@ -14271,7 +14271,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:18:15, endln:18:16 |vpiParent: - \_module: work@M (work@top.genblk3.m3), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:61:13, endln:61:77 + \_module_inst: work@M (work@top.genblk3.m3), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:61:13, endln:61:77 |vpiLhs: \_parameter: (work@top.genblk3.m3.E), line:18:15, endln:18:16 |vpiDefName:work@M @@ -14280,7 +14280,7 @@ design: (work@top) |vpiProcess: \_initial: , line:21:5, endln:22:54 |vpiParent: - \_module: work@M (work@top.genblk3.m3), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:61:13, endln:61:77 + \_module_inst: work@M (work@top.genblk3.m3), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:61:13, endln:61:77 |vpiStmt: \_delay_control: , line:21:13, endln:21:19 |vpiParent: @@ -14345,8 +14345,8 @@ design: (work@top) \_type_parameter: (work@top.genblk8.m3.T), line:19:20, endln:19:21 |vpiName:$bits |vpiName:$display - |vpiInterface: - \_interface: work@I (work@top.genblk3.i1), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:56:13, endln:56:62 + |vpiInterfaceInst: + \_interface_inst: work@I (work@top.genblk3.i1), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:56:13, endln:56:62 |vpiParent: \_gen_scope: (work@top.genblk3) |vpiName:i1 @@ -14354,25 +14354,25 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.genblk3.i1.DELAY), line:26:15, endln:26:20 |vpiParent: - \_interface: work@I (work@top.genblk3.i1), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:56:13, endln:56:62 + \_interface_inst: work@I (work@top.genblk3.i1), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:56:13, endln:56:62 |vpiName:DELAY |vpiFullName:work@top.genblk3.i1.DELAY |vpiParameter: \_parameter: (work@top.genblk3.i1.PREFIX), line:27:15, endln:27:21 |vpiParent: - \_interface: work@I (work@top.genblk3.i1), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:56:13, endln:56:62 + \_interface_inst: work@I (work@top.genblk3.i1), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:56:13, endln:56:62 |vpiName:PREFIX |vpiFullName:work@top.genblk3.i1.PREFIX |vpiParameter: \_parameter: (work@top.genblk3.i1.SUFFIX), line:28:15, endln:28:21 |vpiParent: - \_interface: work@I (work@top.genblk3.i1), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:56:13, endln:56:62 + \_interface_inst: work@I (work@top.genblk3.i1), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:56:13, endln:56:62 |vpiName:SUFFIX |vpiFullName:work@top.genblk3.i1.SUFFIX |vpiParameter: \_parameter: (work@top.genblk3.i1.E), line:29:15, endln:29:16 |vpiParent: - \_interface: work@I (work@top.genblk3.i1), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:56:13, endln:56:62 + \_interface_inst: work@I (work@top.genblk3.i1), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:56:13, endln:56:62 |vpiName:E |vpiFullName:work@top.genblk3.i1.E |vpiParameter: @@ -14380,7 +14380,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:26:15, endln:26:20 |vpiParent: - \_interface: work@I (work@top.genblk3.i1), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:56:13, endln:56:62 + \_interface_inst: work@I (work@top.genblk3.i1), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:56:13, endln:56:62 |vpiOverriden:1 |vpiRhs: \_constant: @@ -14397,7 +14397,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:27:15, endln:27:21 |vpiParent: - \_interface: work@I (work@top.genblk3.i1), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:56:13, endln:56:62 + \_interface_inst: work@I (work@top.genblk3.i1), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:56:13, endln:56:62 |vpiOverriden:1 |vpiRhs: \_constant: @@ -14414,7 +14414,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:28:15, endln:28:21 |vpiParent: - \_interface: work@I (work@top.genblk3.i1), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:56:13, endln:56:62 + \_interface_inst: work@I (work@top.genblk3.i1), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:56:13, endln:56:62 |vpiOverriden:1 |vpiRhs: \_constant: @@ -14429,7 +14429,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:29:15, endln:29:16 |vpiParent: - \_interface: work@I (work@top.genblk3.i1), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:56:13, endln:56:62 + \_interface_inst: work@I (work@top.genblk3.i1), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:56:13, endln:56:62 |vpiRhs: \_constant: |vpiDecompile:3 @@ -14448,7 +14448,7 @@ design: (work@top) |vpiProcess: \_initial: , line:32:5, endln:33:54 |vpiParent: - \_interface: work@I (work@top.genblk3.i1), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:56:13, endln:56:62 + \_interface_inst: work@I (work@top.genblk3.i1), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:56:13, endln:56:62 |vpiStmt: \_delay_control: , line:32:13, endln:32:19 |vpiParent: @@ -14513,8 +14513,8 @@ design: (work@top) \_type_parameter: (work@top.genblk8.i3.T), line:30:20, endln:30:21 |vpiName:$bits |vpiName:$display - |vpiInterface: - \_interface: work@I (work@top.genblk3.i2), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:58:13, endln:58:71 + |vpiInterfaceInst: + \_interface_inst: work@I (work@top.genblk3.i2), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:58:13, endln:58:71 |vpiParent: \_gen_scope: (work@top.genblk3) |vpiName:i2 @@ -14522,25 +14522,25 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.genblk3.i2.DELAY), line:26:15, endln:26:20 |vpiParent: - \_interface: work@I (work@top.genblk3.i2), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:58:13, endln:58:71 + \_interface_inst: work@I (work@top.genblk3.i2), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:58:13, endln:58:71 |vpiName:DELAY |vpiFullName:work@top.genblk3.i2.DELAY |vpiParameter: \_parameter: (work@top.genblk3.i2.PREFIX), line:27:15, endln:27:21 |vpiParent: - \_interface: work@I (work@top.genblk3.i2), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:58:13, endln:58:71 + \_interface_inst: work@I (work@top.genblk3.i2), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:58:13, endln:58:71 |vpiName:PREFIX |vpiFullName:work@top.genblk3.i2.PREFIX |vpiParameter: \_parameter: (work@top.genblk3.i2.SUFFIX), line:28:15, endln:28:21 |vpiParent: - \_interface: work@I (work@top.genblk3.i2), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:58:13, endln:58:71 + \_interface_inst: work@I (work@top.genblk3.i2), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:58:13, endln:58:71 |vpiName:SUFFIX |vpiFullName:work@top.genblk3.i2.SUFFIX |vpiParameter: \_parameter: (work@top.genblk3.i2.E), line:29:15, endln:29:16 |vpiParent: - \_interface: work@I (work@top.genblk3.i2), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:58:13, endln:58:71 + \_interface_inst: work@I (work@top.genblk3.i2), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:58:13, endln:58:71 |vpiName:E |vpiFullName:work@top.genblk3.i2.E |vpiParameter: @@ -14548,7 +14548,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:26:15, endln:26:20 |vpiParent: - \_interface: work@I (work@top.genblk3.i2), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:58:13, endln:58:71 + \_interface_inst: work@I (work@top.genblk3.i2), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:58:13, endln:58:71 |vpiOverriden:1 |vpiRhs: \_constant: @@ -14565,7 +14565,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:27:15, endln:27:21 |vpiParent: - \_interface: work@I (work@top.genblk3.i2), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:58:13, endln:58:71 + \_interface_inst: work@I (work@top.genblk3.i2), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:58:13, endln:58:71 |vpiOverriden:1 |vpiRhs: \_constant: @@ -14582,7 +14582,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:28:15, endln:28:21 |vpiParent: - \_interface: work@I (work@top.genblk3.i2), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:58:13, endln:58:71 + \_interface_inst: work@I (work@top.genblk3.i2), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:58:13, endln:58:71 |vpiOverriden:1 |vpiRhs: \_constant: @@ -14599,7 +14599,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:29:15, endln:29:16 |vpiParent: - \_interface: work@I (work@top.genblk3.i2), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:58:13, endln:58:71 + \_interface_inst: work@I (work@top.genblk3.i2), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:58:13, endln:58:71 |vpiRhs: \_constant: |vpiDecompile:3 @@ -14618,7 +14618,7 @@ design: (work@top) |vpiProcess: \_initial: , line:32:5, endln:33:54 |vpiParent: - \_interface: work@I (work@top.genblk3.i2), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:58:13, endln:58:71 + \_interface_inst: work@I (work@top.genblk3.i2), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:58:13, endln:58:71 |vpiStmt: \_delay_control: , line:32:13, endln:32:19 |vpiParent: @@ -14683,8 +14683,8 @@ design: (work@top) \_type_parameter: (work@top.genblk8.i3.T), line:30:20, endln:30:21 |vpiName:$bits |vpiName:$display - |vpiInterface: - \_interface: work@I (work@top.genblk3.i3), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:60:13, endln:60:77 + |vpiInterfaceInst: + \_interface_inst: work@I (work@top.genblk3.i3), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:60:13, endln:60:77 |vpiParent: \_gen_scope: (work@top.genblk3) |vpiName:i3 @@ -14692,25 +14692,25 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.genblk3.i3.DELAY), line:26:15, endln:26:20 |vpiParent: - \_interface: work@I (work@top.genblk3.i3), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:60:13, endln:60:77 + \_interface_inst: work@I (work@top.genblk3.i3), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:60:13, endln:60:77 |vpiName:DELAY |vpiFullName:work@top.genblk3.i3.DELAY |vpiParameter: \_parameter: (work@top.genblk3.i3.PREFIX), line:27:15, endln:27:21 |vpiParent: - \_interface: work@I (work@top.genblk3.i3), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:60:13, endln:60:77 + \_interface_inst: work@I (work@top.genblk3.i3), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:60:13, endln:60:77 |vpiName:PREFIX |vpiFullName:work@top.genblk3.i3.PREFIX |vpiParameter: \_parameter: (work@top.genblk3.i3.SUFFIX), line:28:15, endln:28:21 |vpiParent: - \_interface: work@I (work@top.genblk3.i3), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:60:13, endln:60:77 + \_interface_inst: work@I (work@top.genblk3.i3), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:60:13, endln:60:77 |vpiName:SUFFIX |vpiFullName:work@top.genblk3.i3.SUFFIX |vpiParameter: \_parameter: (work@top.genblk3.i3.E), line:29:15, endln:29:16 |vpiParent: - \_interface: work@I (work@top.genblk3.i3), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:60:13, endln:60:77 + \_interface_inst: work@I (work@top.genblk3.i3), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:60:13, endln:60:77 |vpiName:E |vpiFullName:work@top.genblk3.i3.E |vpiParameter: @@ -14718,7 +14718,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:26:15, endln:26:20 |vpiParent: - \_interface: work@I (work@top.genblk3.i3), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:60:13, endln:60:77 + \_interface_inst: work@I (work@top.genblk3.i3), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:60:13, endln:60:77 |vpiOverriden:1 |vpiRhs: \_constant: @@ -14735,7 +14735,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:27:15, endln:27:21 |vpiParent: - \_interface: work@I (work@top.genblk3.i3), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:60:13, endln:60:77 + \_interface_inst: work@I (work@top.genblk3.i3), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:60:13, endln:60:77 |vpiOverriden:1 |vpiRhs: \_constant: @@ -14752,7 +14752,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:28:15, endln:28:21 |vpiParent: - \_interface: work@I (work@top.genblk3.i3), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:60:13, endln:60:77 + \_interface_inst: work@I (work@top.genblk3.i3), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:60:13, endln:60:77 |vpiOverriden:1 |vpiRhs: \_constant: @@ -14769,7 +14769,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:29:15, endln:29:16 |vpiParent: - \_interface: work@I (work@top.genblk3.i3), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:60:13, endln:60:77 + \_interface_inst: work@I (work@top.genblk3.i3), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:60:13, endln:60:77 |vpiRhs: \_constant: |vpiDecompile:3 @@ -14788,7 +14788,7 @@ design: (work@top) |vpiProcess: \_initial: , line:32:5, endln:33:54 |vpiParent: - \_interface: work@I (work@top.genblk3.i3), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:60:13, endln:60:77 + \_interface_inst: work@I (work@top.genblk3.i3), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:60:13, endln:60:77 |vpiStmt: \_delay_control: , line:32:13, endln:32:19 |vpiParent: @@ -14856,7 +14856,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.genblk4), line:43:9, endln:62:12 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:36:1, endln:74:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:36:1, endln:74:10 |vpiName:genblk4 |vpiFullName:work@top.genblk4 |vpiGenScope: @@ -15115,8 +15115,8 @@ design: (work@top) |BIN:Z |vpiConstType:3 |vpiName:$display - |vpiModule: - \_module: work@M (work@top.genblk4.m1), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:57:13, endln:57:74 + |vpiModuleInst: + \_module_inst: work@M (work@top.genblk4.m1), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:57:13, endln:57:74 |vpiParent: \_gen_scope: (work@top.genblk4) |vpiName:m1 @@ -15150,7 +15150,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:15:15, endln:15:20 |vpiParent: - \_module: work@M (work@top.genblk4.m1), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:57:13, endln:57:74 + \_module_inst: work@M (work@top.genblk4.m1), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:57:13, endln:57:74 |vpiOverriden:1 |vpiRhs: \_constant: @@ -15163,7 +15163,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:16:15, endln:16:21 |vpiParent: - \_module: work@M (work@top.genblk4.m1), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:57:13, endln:57:74 + \_module_inst: work@M (work@top.genblk4.m1), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:57:13, endln:57:74 |vpiOverriden:1 |vpiRhs: \_constant: @@ -15176,7 +15176,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:17:15, endln:17:21 |vpiParent: - \_module: work@M (work@top.genblk4.m1), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:57:13, endln:57:74 + \_module_inst: work@M (work@top.genblk4.m1), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:57:13, endln:57:74 |vpiOverriden:1 |vpiRhs: \_constant: @@ -15187,7 +15187,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:18:15, endln:18:16 |vpiParent: - \_module: work@M (work@top.genblk4.m1), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:57:13, endln:57:74 + \_module_inst: work@M (work@top.genblk4.m1), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:57:13, endln:57:74 |vpiLhs: \_parameter: (work@top.genblk4.m1.E), line:18:15, endln:18:16 |vpiDefName:work@M @@ -15196,7 +15196,7 @@ design: (work@top) |vpiProcess: \_initial: , line:21:5, endln:22:54 |vpiParent: - \_module: work@M (work@top.genblk4.m1), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:57:13, endln:57:74 + \_module_inst: work@M (work@top.genblk4.m1), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:57:13, endln:57:74 |vpiStmt: \_delay_control: , line:21:13, endln:21:19 |vpiParent: @@ -15261,8 +15261,8 @@ design: (work@top) \_type_parameter: (work@top.genblk8.m3.T), line:19:20, endln:19:21 |vpiName:$bits |vpiName:$display - |vpiModule: - \_module: work@M (work@top.genblk4.m2), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:59:13, endln:59:83 + |vpiModuleInst: + \_module_inst: work@M (work@top.genblk4.m2), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:59:13, endln:59:83 |vpiParent: \_gen_scope: (work@top.genblk4) |vpiName:m2 @@ -15296,7 +15296,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:15:15, endln:15:20 |vpiParent: - \_module: work@M (work@top.genblk4.m2), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:59:13, endln:59:83 + \_module_inst: work@M (work@top.genblk4.m2), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:59:13, endln:59:83 |vpiOverriden:1 |vpiRhs: \_constant: @@ -15309,7 +15309,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:16:15, endln:16:21 |vpiParent: - \_module: work@M (work@top.genblk4.m2), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:59:13, endln:59:83 + \_module_inst: work@M (work@top.genblk4.m2), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:59:13, endln:59:83 |vpiOverriden:1 |vpiRhs: \_constant: @@ -15322,7 +15322,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:17:15, endln:17:21 |vpiParent: - \_module: work@M (work@top.genblk4.m2), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:59:13, endln:59:83 + \_module_inst: work@M (work@top.genblk4.m2), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:59:13, endln:59:83 |vpiOverriden:1 |vpiRhs: \_constant: @@ -15335,7 +15335,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:18:15, endln:18:16 |vpiParent: - \_module: work@M (work@top.genblk4.m2), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:59:13, endln:59:83 + \_module_inst: work@M (work@top.genblk4.m2), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:59:13, endln:59:83 |vpiLhs: \_parameter: (work@top.genblk4.m2.E), line:18:15, endln:18:16 |vpiDefName:work@M @@ -15344,7 +15344,7 @@ design: (work@top) |vpiProcess: \_initial: , line:21:5, endln:22:54 |vpiParent: - \_module: work@M (work@top.genblk4.m2), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:59:13, endln:59:83 + \_module_inst: work@M (work@top.genblk4.m2), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:59:13, endln:59:83 |vpiStmt: \_delay_control: , line:21:13, endln:21:19 |vpiParent: @@ -15409,8 +15409,8 @@ design: (work@top) \_type_parameter: (work@top.genblk8.m3.T), line:19:20, endln:19:21 |vpiName:$bits |vpiName:$display - |vpiModule: - \_module: work@M (work@top.genblk4.m3), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:61:13, endln:61:89 + |vpiModuleInst: + \_module_inst: work@M (work@top.genblk4.m3), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:61:13, endln:61:89 |vpiParent: \_gen_scope: (work@top.genblk4) |vpiName:m3 @@ -15444,7 +15444,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:15:15, endln:15:20 |vpiParent: - \_module: work@M (work@top.genblk4.m3), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:61:13, endln:61:89 + \_module_inst: work@M (work@top.genblk4.m3), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:61:13, endln:61:89 |vpiOverriden:1 |vpiRhs: \_constant: @@ -15457,7 +15457,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:16:15, endln:16:21 |vpiParent: - \_module: work@M (work@top.genblk4.m3), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:61:13, endln:61:89 + \_module_inst: work@M (work@top.genblk4.m3), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:61:13, endln:61:89 |vpiOverriden:1 |vpiRhs: \_constant: @@ -15470,7 +15470,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:17:15, endln:17:21 |vpiParent: - \_module: work@M (work@top.genblk4.m3), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:61:13, endln:61:89 + \_module_inst: work@M (work@top.genblk4.m3), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:61:13, endln:61:89 |vpiOverriden:1 |vpiRhs: \_constant: @@ -15483,7 +15483,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:18:15, endln:18:16 |vpiParent: - \_module: work@M (work@top.genblk4.m3), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:61:13, endln:61:89 + \_module_inst: work@M (work@top.genblk4.m3), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:61:13, endln:61:89 |vpiLhs: \_parameter: (work@top.genblk4.m3.E), line:18:15, endln:18:16 |vpiDefName:work@M @@ -15492,7 +15492,7 @@ design: (work@top) |vpiProcess: \_initial: , line:21:5, endln:22:54 |vpiParent: - \_module: work@M (work@top.genblk4.m3), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:61:13, endln:61:89 + \_module_inst: work@M (work@top.genblk4.m3), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:61:13, endln:61:89 |vpiStmt: \_delay_control: , line:21:13, endln:21:19 |vpiParent: @@ -15557,8 +15557,8 @@ design: (work@top) \_type_parameter: (work@top.genblk8.m3.T), line:19:20, endln:19:21 |vpiName:$bits |vpiName:$display - |vpiInterface: - \_interface: work@I (work@top.genblk4.i1), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:56:13, endln:56:74 + |vpiInterfaceInst: + \_interface_inst: work@I (work@top.genblk4.i1), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:56:13, endln:56:74 |vpiParent: \_gen_scope: (work@top.genblk4) |vpiName:i1 @@ -15566,25 +15566,25 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.genblk4.i1.DELAY), line:26:15, endln:26:20 |vpiParent: - \_interface: work@I (work@top.genblk4.i1), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:56:13, endln:56:74 + \_interface_inst: work@I (work@top.genblk4.i1), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:56:13, endln:56:74 |vpiName:DELAY |vpiFullName:work@top.genblk4.i1.DELAY |vpiParameter: \_parameter: (work@top.genblk4.i1.PREFIX), line:27:15, endln:27:21 |vpiParent: - \_interface: work@I (work@top.genblk4.i1), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:56:13, endln:56:74 + \_interface_inst: work@I (work@top.genblk4.i1), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:56:13, endln:56:74 |vpiName:PREFIX |vpiFullName:work@top.genblk4.i1.PREFIX |vpiParameter: \_parameter: (work@top.genblk4.i1.SUFFIX), line:28:15, endln:28:21 |vpiParent: - \_interface: work@I (work@top.genblk4.i1), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:56:13, endln:56:74 + \_interface_inst: work@I (work@top.genblk4.i1), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:56:13, endln:56:74 |vpiName:SUFFIX |vpiFullName:work@top.genblk4.i1.SUFFIX |vpiParameter: \_parameter: (work@top.genblk4.i1.E), line:29:15, endln:29:16 |vpiParent: - \_interface: work@I (work@top.genblk4.i1), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:56:13, endln:56:74 + \_interface_inst: work@I (work@top.genblk4.i1), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:56:13, endln:56:74 |vpiName:E |vpiFullName:work@top.genblk4.i1.E |vpiParameter: @@ -15592,7 +15592,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:26:15, endln:26:20 |vpiParent: - \_interface: work@I (work@top.genblk4.i1), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:56:13, endln:56:74 + \_interface_inst: work@I (work@top.genblk4.i1), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:56:13, endln:56:74 |vpiOverriden:1 |vpiRhs: \_constant: @@ -15609,7 +15609,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:27:15, endln:27:21 |vpiParent: - \_interface: work@I (work@top.genblk4.i1), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:56:13, endln:56:74 + \_interface_inst: work@I (work@top.genblk4.i1), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:56:13, endln:56:74 |vpiOverriden:1 |vpiRhs: \_constant: @@ -15626,7 +15626,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:28:15, endln:28:21 |vpiParent: - \_interface: work@I (work@top.genblk4.i1), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:56:13, endln:56:74 + \_interface_inst: work@I (work@top.genblk4.i1), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:56:13, endln:56:74 |vpiOverriden:1 |vpiRhs: \_constant: @@ -15641,7 +15641,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:29:15, endln:29:16 |vpiParent: - \_interface: work@I (work@top.genblk4.i1), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:56:13, endln:56:74 + \_interface_inst: work@I (work@top.genblk4.i1), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:56:13, endln:56:74 |vpiRhs: \_constant: |vpiDecompile:3 @@ -15660,7 +15660,7 @@ design: (work@top) |vpiProcess: \_initial: , line:32:5, endln:33:54 |vpiParent: - \_interface: work@I (work@top.genblk4.i1), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:56:13, endln:56:74 + \_interface_inst: work@I (work@top.genblk4.i1), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:56:13, endln:56:74 |vpiStmt: \_delay_control: , line:32:13, endln:32:19 |vpiParent: @@ -15725,8 +15725,8 @@ design: (work@top) \_type_parameter: (work@top.genblk8.i3.T), line:30:20, endln:30:21 |vpiName:$bits |vpiName:$display - |vpiInterface: - \_interface: work@I (work@top.genblk4.i2), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:58:13, endln:58:83 + |vpiInterfaceInst: + \_interface_inst: work@I (work@top.genblk4.i2), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:58:13, endln:58:83 |vpiParent: \_gen_scope: (work@top.genblk4) |vpiName:i2 @@ -15734,25 +15734,25 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.genblk4.i2.DELAY), line:26:15, endln:26:20 |vpiParent: - \_interface: work@I (work@top.genblk4.i2), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:58:13, endln:58:83 + \_interface_inst: work@I (work@top.genblk4.i2), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:58:13, endln:58:83 |vpiName:DELAY |vpiFullName:work@top.genblk4.i2.DELAY |vpiParameter: \_parameter: (work@top.genblk4.i2.PREFIX), line:27:15, endln:27:21 |vpiParent: - \_interface: work@I (work@top.genblk4.i2), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:58:13, endln:58:83 + \_interface_inst: work@I (work@top.genblk4.i2), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:58:13, endln:58:83 |vpiName:PREFIX |vpiFullName:work@top.genblk4.i2.PREFIX |vpiParameter: \_parameter: (work@top.genblk4.i2.SUFFIX), line:28:15, endln:28:21 |vpiParent: - \_interface: work@I (work@top.genblk4.i2), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:58:13, endln:58:83 + \_interface_inst: work@I (work@top.genblk4.i2), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:58:13, endln:58:83 |vpiName:SUFFIX |vpiFullName:work@top.genblk4.i2.SUFFIX |vpiParameter: \_parameter: (work@top.genblk4.i2.E), line:29:15, endln:29:16 |vpiParent: - \_interface: work@I (work@top.genblk4.i2), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:58:13, endln:58:83 + \_interface_inst: work@I (work@top.genblk4.i2), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:58:13, endln:58:83 |vpiName:E |vpiFullName:work@top.genblk4.i2.E |vpiParameter: @@ -15760,7 +15760,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:26:15, endln:26:20 |vpiParent: - \_interface: work@I (work@top.genblk4.i2), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:58:13, endln:58:83 + \_interface_inst: work@I (work@top.genblk4.i2), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:58:13, endln:58:83 |vpiOverriden:1 |vpiRhs: \_constant: @@ -15777,7 +15777,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:27:15, endln:27:21 |vpiParent: - \_interface: work@I (work@top.genblk4.i2), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:58:13, endln:58:83 + \_interface_inst: work@I (work@top.genblk4.i2), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:58:13, endln:58:83 |vpiOverriden:1 |vpiRhs: \_constant: @@ -15794,7 +15794,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:28:15, endln:28:21 |vpiParent: - \_interface: work@I (work@top.genblk4.i2), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:58:13, endln:58:83 + \_interface_inst: work@I (work@top.genblk4.i2), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:58:13, endln:58:83 |vpiOverriden:1 |vpiRhs: \_constant: @@ -15811,7 +15811,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:29:15, endln:29:16 |vpiParent: - \_interface: work@I (work@top.genblk4.i2), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:58:13, endln:58:83 + \_interface_inst: work@I (work@top.genblk4.i2), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:58:13, endln:58:83 |vpiRhs: \_constant: |vpiDecompile:3 @@ -15830,7 +15830,7 @@ design: (work@top) |vpiProcess: \_initial: , line:32:5, endln:33:54 |vpiParent: - \_interface: work@I (work@top.genblk4.i2), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:58:13, endln:58:83 + \_interface_inst: work@I (work@top.genblk4.i2), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:58:13, endln:58:83 |vpiStmt: \_delay_control: , line:32:13, endln:32:19 |vpiParent: @@ -15895,8 +15895,8 @@ design: (work@top) \_type_parameter: (work@top.genblk8.i3.T), line:30:20, endln:30:21 |vpiName:$bits |vpiName:$display - |vpiInterface: - \_interface: work@I (work@top.genblk4.i3), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:60:13, endln:60:89 + |vpiInterfaceInst: + \_interface_inst: work@I (work@top.genblk4.i3), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:60:13, endln:60:89 |vpiParent: \_gen_scope: (work@top.genblk4) |vpiName:i3 @@ -15904,25 +15904,25 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.genblk4.i3.DELAY), line:26:15, endln:26:20 |vpiParent: - \_interface: work@I (work@top.genblk4.i3), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:60:13, endln:60:89 + \_interface_inst: work@I (work@top.genblk4.i3), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:60:13, endln:60:89 |vpiName:DELAY |vpiFullName:work@top.genblk4.i3.DELAY |vpiParameter: \_parameter: (work@top.genblk4.i3.PREFIX), line:27:15, endln:27:21 |vpiParent: - \_interface: work@I (work@top.genblk4.i3), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:60:13, endln:60:89 + \_interface_inst: work@I (work@top.genblk4.i3), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:60:13, endln:60:89 |vpiName:PREFIX |vpiFullName:work@top.genblk4.i3.PREFIX |vpiParameter: \_parameter: (work@top.genblk4.i3.SUFFIX), line:28:15, endln:28:21 |vpiParent: - \_interface: work@I (work@top.genblk4.i3), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:60:13, endln:60:89 + \_interface_inst: work@I (work@top.genblk4.i3), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:60:13, endln:60:89 |vpiName:SUFFIX |vpiFullName:work@top.genblk4.i3.SUFFIX |vpiParameter: \_parameter: (work@top.genblk4.i3.E), line:29:15, endln:29:16 |vpiParent: - \_interface: work@I (work@top.genblk4.i3), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:60:13, endln:60:89 + \_interface_inst: work@I (work@top.genblk4.i3), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:60:13, endln:60:89 |vpiName:E |vpiFullName:work@top.genblk4.i3.E |vpiParameter: @@ -15930,7 +15930,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:26:15, endln:26:20 |vpiParent: - \_interface: work@I (work@top.genblk4.i3), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:60:13, endln:60:89 + \_interface_inst: work@I (work@top.genblk4.i3), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:60:13, endln:60:89 |vpiOverriden:1 |vpiRhs: \_constant: @@ -15947,7 +15947,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:27:15, endln:27:21 |vpiParent: - \_interface: work@I (work@top.genblk4.i3), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:60:13, endln:60:89 + \_interface_inst: work@I (work@top.genblk4.i3), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:60:13, endln:60:89 |vpiOverriden:1 |vpiRhs: \_constant: @@ -15964,7 +15964,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:28:15, endln:28:21 |vpiParent: - \_interface: work@I (work@top.genblk4.i3), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:60:13, endln:60:89 + \_interface_inst: work@I (work@top.genblk4.i3), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:60:13, endln:60:89 |vpiOverriden:1 |vpiRhs: \_constant: @@ -15981,7 +15981,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:29:15, endln:29:16 |vpiParent: - \_interface: work@I (work@top.genblk4.i3), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:60:13, endln:60:89 + \_interface_inst: work@I (work@top.genblk4.i3), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:60:13, endln:60:89 |vpiRhs: \_constant: |vpiDecompile:3 @@ -16000,7 +16000,7 @@ design: (work@top) |vpiProcess: \_initial: , line:32:5, endln:33:54 |vpiParent: - \_interface: work@I (work@top.genblk4.i3), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:60:13, endln:60:89 + \_interface_inst: work@I (work@top.genblk4.i3), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:60:13, endln:60:89 |vpiStmt: \_delay_control: , line:32:13, endln:32:19 |vpiParent: @@ -16068,7 +16068,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.genblk5), line:43:9, endln:62:12 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:36:1, endln:74:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:36:1, endln:74:10 |vpiName:genblk5 |vpiFullName:work@top.genblk5 |vpiGenScope: @@ -16327,8 +16327,8 @@ design: (work@top) |BIN:Z |vpiConstType:3 |vpiName:$display - |vpiModule: - \_module: work@M (work@top.genblk5.m1), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:57:13, endln:57:92 + |vpiModuleInst: + \_module_inst: work@M (work@top.genblk5.m1), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:57:13, endln:57:92 |vpiParent: \_gen_scope: (work@top.genblk5) |vpiName:m1 @@ -16362,7 +16362,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:15:15, endln:15:20 |vpiParent: - \_module: work@M (work@top.genblk5.m1), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:57:13, endln:57:92 + \_module_inst: work@M (work@top.genblk5.m1), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:57:13, endln:57:92 |vpiOverriden:1 |vpiRhs: \_constant: @@ -16375,7 +16375,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:16:15, endln:16:21 |vpiParent: - \_module: work@M (work@top.genblk5.m1), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:57:13, endln:57:92 + \_module_inst: work@M (work@top.genblk5.m1), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:57:13, endln:57:92 |vpiOverriden:1 |vpiRhs: \_constant: @@ -16388,7 +16388,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:17:15, endln:17:21 |vpiParent: - \_module: work@M (work@top.genblk5.m1), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:57:13, endln:57:92 + \_module_inst: work@M (work@top.genblk5.m1), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:57:13, endln:57:92 |vpiOverriden:1 |vpiRhs: \_constant: @@ -16399,7 +16399,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:18:15, endln:18:16 |vpiParent: - \_module: work@M (work@top.genblk5.m1), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:57:13, endln:57:92 + \_module_inst: work@M (work@top.genblk5.m1), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:57:13, endln:57:92 |vpiLhs: \_parameter: (work@top.genblk5.m1.E), line:18:15, endln:18:16 |vpiDefName:work@M @@ -16408,7 +16408,7 @@ design: (work@top) |vpiProcess: \_initial: , line:21:5, endln:22:54 |vpiParent: - \_module: work@M (work@top.genblk5.m1), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:57:13, endln:57:92 + \_module_inst: work@M (work@top.genblk5.m1), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:57:13, endln:57:92 |vpiStmt: \_delay_control: , line:21:13, endln:21:19 |vpiParent: @@ -16473,8 +16473,8 @@ design: (work@top) \_type_parameter: (work@top.genblk8.m3.T), line:19:20, endln:19:21 |vpiName:$bits |vpiName:$display - |vpiModule: - \_module: work@M (work@top.genblk5.m2), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:59:13, endln:59:101 + |vpiModuleInst: + \_module_inst: work@M (work@top.genblk5.m2), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:59:13, endln:59:101 |vpiParent: \_gen_scope: (work@top.genblk5) |vpiName:m2 @@ -16508,7 +16508,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:15:15, endln:15:20 |vpiParent: - \_module: work@M (work@top.genblk5.m2), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:59:13, endln:59:101 + \_module_inst: work@M (work@top.genblk5.m2), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:59:13, endln:59:101 |vpiOverriden:1 |vpiRhs: \_constant: @@ -16521,7 +16521,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:16:15, endln:16:21 |vpiParent: - \_module: work@M (work@top.genblk5.m2), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:59:13, endln:59:101 + \_module_inst: work@M (work@top.genblk5.m2), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:59:13, endln:59:101 |vpiOverriden:1 |vpiRhs: \_constant: @@ -16534,7 +16534,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:17:15, endln:17:21 |vpiParent: - \_module: work@M (work@top.genblk5.m2), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:59:13, endln:59:101 + \_module_inst: work@M (work@top.genblk5.m2), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:59:13, endln:59:101 |vpiOverriden:1 |vpiRhs: \_constant: @@ -16547,7 +16547,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:18:15, endln:18:16 |vpiParent: - \_module: work@M (work@top.genblk5.m2), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:59:13, endln:59:101 + \_module_inst: work@M (work@top.genblk5.m2), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:59:13, endln:59:101 |vpiLhs: \_parameter: (work@top.genblk5.m2.E), line:18:15, endln:18:16 |vpiDefName:work@M @@ -16556,7 +16556,7 @@ design: (work@top) |vpiProcess: \_initial: , line:21:5, endln:22:54 |vpiParent: - \_module: work@M (work@top.genblk5.m2), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:59:13, endln:59:101 + \_module_inst: work@M (work@top.genblk5.m2), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:59:13, endln:59:101 |vpiStmt: \_delay_control: , line:21:13, endln:21:19 |vpiParent: @@ -16621,8 +16621,8 @@ design: (work@top) \_type_parameter: (work@top.genblk8.m3.T), line:19:20, endln:19:21 |vpiName:$bits |vpiName:$display - |vpiModule: - \_module: work@M (work@top.genblk5.m3), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:61:13, endln:61:107 + |vpiModuleInst: + \_module_inst: work@M (work@top.genblk5.m3), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:61:13, endln:61:107 |vpiParent: \_gen_scope: (work@top.genblk5) |vpiName:m3 @@ -16656,7 +16656,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:15:15, endln:15:20 |vpiParent: - \_module: work@M (work@top.genblk5.m3), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:61:13, endln:61:107 + \_module_inst: work@M (work@top.genblk5.m3), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:61:13, endln:61:107 |vpiOverriden:1 |vpiRhs: \_constant: @@ -16669,7 +16669,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:16:15, endln:16:21 |vpiParent: - \_module: work@M (work@top.genblk5.m3), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:61:13, endln:61:107 + \_module_inst: work@M (work@top.genblk5.m3), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:61:13, endln:61:107 |vpiOverriden:1 |vpiRhs: \_constant: @@ -16682,7 +16682,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:17:15, endln:17:21 |vpiParent: - \_module: work@M (work@top.genblk5.m3), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:61:13, endln:61:107 + \_module_inst: work@M (work@top.genblk5.m3), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:61:13, endln:61:107 |vpiOverriden:1 |vpiRhs: \_constant: @@ -16695,7 +16695,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:18:15, endln:18:16 |vpiParent: - \_module: work@M (work@top.genblk5.m3), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:61:13, endln:61:107 + \_module_inst: work@M (work@top.genblk5.m3), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:61:13, endln:61:107 |vpiLhs: \_parameter: (work@top.genblk5.m3.E), line:18:15, endln:18:16 |vpiDefName:work@M @@ -16704,7 +16704,7 @@ design: (work@top) |vpiProcess: \_initial: , line:21:5, endln:22:54 |vpiParent: - \_module: work@M (work@top.genblk5.m3), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:61:13, endln:61:107 + \_module_inst: work@M (work@top.genblk5.m3), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:61:13, endln:61:107 |vpiStmt: \_delay_control: , line:21:13, endln:21:19 |vpiParent: @@ -16769,8 +16769,8 @@ design: (work@top) \_type_parameter: (work@top.genblk8.m3.T), line:19:20, endln:19:21 |vpiName:$bits |vpiName:$display - |vpiInterface: - \_interface: work@I (work@top.genblk5.i1), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:56:13, endln:56:92 + |vpiInterfaceInst: + \_interface_inst: work@I (work@top.genblk5.i1), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:56:13, endln:56:92 |vpiParent: \_gen_scope: (work@top.genblk5) |vpiName:i1 @@ -16778,25 +16778,25 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.genblk5.i1.DELAY), line:26:15, endln:26:20 |vpiParent: - \_interface: work@I (work@top.genblk5.i1), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:56:13, endln:56:92 + \_interface_inst: work@I (work@top.genblk5.i1), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:56:13, endln:56:92 |vpiName:DELAY |vpiFullName:work@top.genblk5.i1.DELAY |vpiParameter: \_parameter: (work@top.genblk5.i1.PREFIX), line:27:15, endln:27:21 |vpiParent: - \_interface: work@I (work@top.genblk5.i1), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:56:13, endln:56:92 + \_interface_inst: work@I (work@top.genblk5.i1), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:56:13, endln:56:92 |vpiName:PREFIX |vpiFullName:work@top.genblk5.i1.PREFIX |vpiParameter: \_parameter: (work@top.genblk5.i1.SUFFIX), line:28:15, endln:28:21 |vpiParent: - \_interface: work@I (work@top.genblk5.i1), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:56:13, endln:56:92 + \_interface_inst: work@I (work@top.genblk5.i1), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:56:13, endln:56:92 |vpiName:SUFFIX |vpiFullName:work@top.genblk5.i1.SUFFIX |vpiParameter: \_parameter: (work@top.genblk5.i1.E), line:29:15, endln:29:16 |vpiParent: - \_interface: work@I (work@top.genblk5.i1), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:56:13, endln:56:92 + \_interface_inst: work@I (work@top.genblk5.i1), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:56:13, endln:56:92 |vpiName:E |vpiFullName:work@top.genblk5.i1.E |vpiParameter: @@ -16804,7 +16804,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:26:15, endln:26:20 |vpiParent: - \_interface: work@I (work@top.genblk5.i1), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:56:13, endln:56:92 + \_interface_inst: work@I (work@top.genblk5.i1), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:56:13, endln:56:92 |vpiOverriden:1 |vpiRhs: \_constant: @@ -16821,7 +16821,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:27:15, endln:27:21 |vpiParent: - \_interface: work@I (work@top.genblk5.i1), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:56:13, endln:56:92 + \_interface_inst: work@I (work@top.genblk5.i1), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:56:13, endln:56:92 |vpiOverriden:1 |vpiRhs: \_constant: @@ -16838,7 +16838,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:28:15, endln:28:21 |vpiParent: - \_interface: work@I (work@top.genblk5.i1), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:56:13, endln:56:92 + \_interface_inst: work@I (work@top.genblk5.i1), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:56:13, endln:56:92 |vpiOverriden:1 |vpiRhs: \_constant: @@ -16853,7 +16853,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:29:15, endln:29:16 |vpiParent: - \_interface: work@I (work@top.genblk5.i1), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:56:13, endln:56:92 + \_interface_inst: work@I (work@top.genblk5.i1), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:56:13, endln:56:92 |vpiRhs: \_constant: |vpiDecompile:3 @@ -16872,7 +16872,7 @@ design: (work@top) |vpiProcess: \_initial: , line:32:5, endln:33:54 |vpiParent: - \_interface: work@I (work@top.genblk5.i1), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:56:13, endln:56:92 + \_interface_inst: work@I (work@top.genblk5.i1), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:56:13, endln:56:92 |vpiStmt: \_delay_control: , line:32:13, endln:32:19 |vpiParent: @@ -16937,8 +16937,8 @@ design: (work@top) \_type_parameter: (work@top.genblk8.i3.T), line:30:20, endln:30:21 |vpiName:$bits |vpiName:$display - |vpiInterface: - \_interface: work@I (work@top.genblk5.i2), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:58:13, endln:58:101 + |vpiInterfaceInst: + \_interface_inst: work@I (work@top.genblk5.i2), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:58:13, endln:58:101 |vpiParent: \_gen_scope: (work@top.genblk5) |vpiName:i2 @@ -16946,25 +16946,25 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.genblk5.i2.DELAY), line:26:15, endln:26:20 |vpiParent: - \_interface: work@I (work@top.genblk5.i2), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:58:13, endln:58:101 + \_interface_inst: work@I (work@top.genblk5.i2), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:58:13, endln:58:101 |vpiName:DELAY |vpiFullName:work@top.genblk5.i2.DELAY |vpiParameter: \_parameter: (work@top.genblk5.i2.PREFIX), line:27:15, endln:27:21 |vpiParent: - \_interface: work@I (work@top.genblk5.i2), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:58:13, endln:58:101 + \_interface_inst: work@I (work@top.genblk5.i2), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:58:13, endln:58:101 |vpiName:PREFIX |vpiFullName:work@top.genblk5.i2.PREFIX |vpiParameter: \_parameter: (work@top.genblk5.i2.SUFFIX), line:28:15, endln:28:21 |vpiParent: - \_interface: work@I (work@top.genblk5.i2), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:58:13, endln:58:101 + \_interface_inst: work@I (work@top.genblk5.i2), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:58:13, endln:58:101 |vpiName:SUFFIX |vpiFullName:work@top.genblk5.i2.SUFFIX |vpiParameter: \_parameter: (work@top.genblk5.i2.E), line:29:15, endln:29:16 |vpiParent: - \_interface: work@I (work@top.genblk5.i2), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:58:13, endln:58:101 + \_interface_inst: work@I (work@top.genblk5.i2), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:58:13, endln:58:101 |vpiName:E |vpiFullName:work@top.genblk5.i2.E |vpiParameter: @@ -16972,7 +16972,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:26:15, endln:26:20 |vpiParent: - \_interface: work@I (work@top.genblk5.i2), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:58:13, endln:58:101 + \_interface_inst: work@I (work@top.genblk5.i2), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:58:13, endln:58:101 |vpiOverriden:1 |vpiRhs: \_constant: @@ -16989,7 +16989,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:27:15, endln:27:21 |vpiParent: - \_interface: work@I (work@top.genblk5.i2), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:58:13, endln:58:101 + \_interface_inst: work@I (work@top.genblk5.i2), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:58:13, endln:58:101 |vpiOverriden:1 |vpiRhs: \_constant: @@ -17006,7 +17006,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:28:15, endln:28:21 |vpiParent: - \_interface: work@I (work@top.genblk5.i2), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:58:13, endln:58:101 + \_interface_inst: work@I (work@top.genblk5.i2), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:58:13, endln:58:101 |vpiOverriden:1 |vpiRhs: \_constant: @@ -17023,7 +17023,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:29:15, endln:29:16 |vpiParent: - \_interface: work@I (work@top.genblk5.i2), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:58:13, endln:58:101 + \_interface_inst: work@I (work@top.genblk5.i2), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:58:13, endln:58:101 |vpiRhs: \_constant: |vpiDecompile:3 @@ -17042,7 +17042,7 @@ design: (work@top) |vpiProcess: \_initial: , line:32:5, endln:33:54 |vpiParent: - \_interface: work@I (work@top.genblk5.i2), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:58:13, endln:58:101 + \_interface_inst: work@I (work@top.genblk5.i2), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:58:13, endln:58:101 |vpiStmt: \_delay_control: , line:32:13, endln:32:19 |vpiParent: @@ -17107,8 +17107,8 @@ design: (work@top) \_type_parameter: (work@top.genblk8.i3.T), line:30:20, endln:30:21 |vpiName:$bits |vpiName:$display - |vpiInterface: - \_interface: work@I (work@top.genblk5.i3), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:60:13, endln:60:107 + |vpiInterfaceInst: + \_interface_inst: work@I (work@top.genblk5.i3), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:60:13, endln:60:107 |vpiParent: \_gen_scope: (work@top.genblk5) |vpiName:i3 @@ -17116,25 +17116,25 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.genblk5.i3.DELAY), line:26:15, endln:26:20 |vpiParent: - \_interface: work@I (work@top.genblk5.i3), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:60:13, endln:60:107 + \_interface_inst: work@I (work@top.genblk5.i3), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:60:13, endln:60:107 |vpiName:DELAY |vpiFullName:work@top.genblk5.i3.DELAY |vpiParameter: \_parameter: (work@top.genblk5.i3.PREFIX), line:27:15, endln:27:21 |vpiParent: - \_interface: work@I (work@top.genblk5.i3), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:60:13, endln:60:107 + \_interface_inst: work@I (work@top.genblk5.i3), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:60:13, endln:60:107 |vpiName:PREFIX |vpiFullName:work@top.genblk5.i3.PREFIX |vpiParameter: \_parameter: (work@top.genblk5.i3.SUFFIX), line:28:15, endln:28:21 |vpiParent: - \_interface: work@I (work@top.genblk5.i3), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:60:13, endln:60:107 + \_interface_inst: work@I (work@top.genblk5.i3), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:60:13, endln:60:107 |vpiName:SUFFIX |vpiFullName:work@top.genblk5.i3.SUFFIX |vpiParameter: \_parameter: (work@top.genblk5.i3.E), line:29:15, endln:29:16 |vpiParent: - \_interface: work@I (work@top.genblk5.i3), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:60:13, endln:60:107 + \_interface_inst: work@I (work@top.genblk5.i3), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:60:13, endln:60:107 |vpiName:E |vpiFullName:work@top.genblk5.i3.E |vpiParameter: @@ -17142,7 +17142,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:26:15, endln:26:20 |vpiParent: - \_interface: work@I (work@top.genblk5.i3), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:60:13, endln:60:107 + \_interface_inst: work@I (work@top.genblk5.i3), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:60:13, endln:60:107 |vpiOverriden:1 |vpiRhs: \_constant: @@ -17159,7 +17159,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:27:15, endln:27:21 |vpiParent: - \_interface: work@I (work@top.genblk5.i3), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:60:13, endln:60:107 + \_interface_inst: work@I (work@top.genblk5.i3), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:60:13, endln:60:107 |vpiOverriden:1 |vpiRhs: \_constant: @@ -17176,7 +17176,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:28:15, endln:28:21 |vpiParent: - \_interface: work@I (work@top.genblk5.i3), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:60:13, endln:60:107 + \_interface_inst: work@I (work@top.genblk5.i3), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:60:13, endln:60:107 |vpiOverriden:1 |vpiRhs: \_constant: @@ -17193,7 +17193,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:29:15, endln:29:16 |vpiParent: - \_interface: work@I (work@top.genblk5.i3), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:60:13, endln:60:107 + \_interface_inst: work@I (work@top.genblk5.i3), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:60:13, endln:60:107 |vpiRhs: \_constant: |vpiDecompile:3 @@ -17212,7 +17212,7 @@ design: (work@top) |vpiProcess: \_initial: , line:32:5, endln:33:54 |vpiParent: - \_interface: work@I (work@top.genblk5.i3), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:60:13, endln:60:107 + \_interface_inst: work@I (work@top.genblk5.i3), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:60:13, endln:60:107 |vpiStmt: \_delay_control: , line:32:13, endln:32:19 |vpiParent: @@ -17280,7 +17280,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.genblk6), line:43:9, endln:62:12 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:36:1, endln:74:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:36:1, endln:74:10 |vpiName:genblk6 |vpiFullName:work@top.genblk6 |vpiGenScope: @@ -17539,8 +17539,8 @@ design: (work@top) |BIN:Z |vpiConstType:3 |vpiName:$display - |vpiModule: - \_module: work@M (work@top.genblk6.m1), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:57:13, endln:57:134 + |vpiModuleInst: + \_module_inst: work@M (work@top.genblk6.m1), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:57:13, endln:57:134 |vpiParent: \_gen_scope: (work@top.genblk6) |vpiName:m1 @@ -17574,7 +17574,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:15:15, endln:15:20 |vpiParent: - \_module: work@M (work@top.genblk6.m1), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:57:13, endln:57:134 + \_module_inst: work@M (work@top.genblk6.m1), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:57:13, endln:57:134 |vpiOverriden:1 |vpiRhs: \_constant: @@ -17587,7 +17587,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:16:15, endln:16:21 |vpiParent: - \_module: work@M (work@top.genblk6.m1), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:57:13, endln:57:134 + \_module_inst: work@M (work@top.genblk6.m1), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:57:13, endln:57:134 |vpiOverriden:1 |vpiRhs: \_constant: @@ -17600,7 +17600,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:17:15, endln:17:21 |vpiParent: - \_module: work@M (work@top.genblk6.m1), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:57:13, endln:57:134 + \_module_inst: work@M (work@top.genblk6.m1), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:57:13, endln:57:134 |vpiOverriden:1 |vpiRhs: \_constant: @@ -17611,7 +17611,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:18:15, endln:18:16 |vpiParent: - \_module: work@M (work@top.genblk6.m1), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:57:13, endln:57:134 + \_module_inst: work@M (work@top.genblk6.m1), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:57:13, endln:57:134 |vpiLhs: \_parameter: (work@top.genblk6.m1.E), line:18:15, endln:18:16 |vpiDefName:work@M @@ -17620,7 +17620,7 @@ design: (work@top) |vpiProcess: \_initial: , line:21:5, endln:22:54 |vpiParent: - \_module: work@M (work@top.genblk6.m1), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:57:13, endln:57:134 + \_module_inst: work@M (work@top.genblk6.m1), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:57:13, endln:57:134 |vpiStmt: \_delay_control: , line:21:13, endln:21:19 |vpiParent: @@ -17685,8 +17685,8 @@ design: (work@top) \_type_parameter: (work@top.genblk8.m3.T), line:19:20, endln:19:21 |vpiName:$bits |vpiName:$display - |vpiModule: - \_module: work@M (work@top.genblk6.m2), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:59:13, endln:59:143 + |vpiModuleInst: + \_module_inst: work@M (work@top.genblk6.m2), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:59:13, endln:59:143 |vpiParent: \_gen_scope: (work@top.genblk6) |vpiName:m2 @@ -17720,7 +17720,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:15:15, endln:15:20 |vpiParent: - \_module: work@M (work@top.genblk6.m2), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:59:13, endln:59:143 + \_module_inst: work@M (work@top.genblk6.m2), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:59:13, endln:59:143 |vpiOverriden:1 |vpiRhs: \_constant: @@ -17733,7 +17733,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:16:15, endln:16:21 |vpiParent: - \_module: work@M (work@top.genblk6.m2), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:59:13, endln:59:143 + \_module_inst: work@M (work@top.genblk6.m2), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:59:13, endln:59:143 |vpiOverriden:1 |vpiRhs: \_constant: @@ -17746,7 +17746,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:17:15, endln:17:21 |vpiParent: - \_module: work@M (work@top.genblk6.m2), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:59:13, endln:59:143 + \_module_inst: work@M (work@top.genblk6.m2), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:59:13, endln:59:143 |vpiOverriden:1 |vpiRhs: \_constant: @@ -17759,7 +17759,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:18:15, endln:18:16 |vpiParent: - \_module: work@M (work@top.genblk6.m2), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:59:13, endln:59:143 + \_module_inst: work@M (work@top.genblk6.m2), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:59:13, endln:59:143 |vpiLhs: \_parameter: (work@top.genblk6.m2.E), line:18:15, endln:18:16 |vpiDefName:work@M @@ -17768,7 +17768,7 @@ design: (work@top) |vpiProcess: \_initial: , line:21:5, endln:22:54 |vpiParent: - \_module: work@M (work@top.genblk6.m2), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:59:13, endln:59:143 + \_module_inst: work@M (work@top.genblk6.m2), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:59:13, endln:59:143 |vpiStmt: \_delay_control: , line:21:13, endln:21:19 |vpiParent: @@ -17833,8 +17833,8 @@ design: (work@top) \_type_parameter: (work@top.genblk8.m3.T), line:19:20, endln:19:21 |vpiName:$bits |vpiName:$display - |vpiModule: - \_module: work@M (work@top.genblk6.m3), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:61:13, endln:61:149 + |vpiModuleInst: + \_module_inst: work@M (work@top.genblk6.m3), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:61:13, endln:61:149 |vpiParent: \_gen_scope: (work@top.genblk6) |vpiName:m3 @@ -17868,7 +17868,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:15:15, endln:15:20 |vpiParent: - \_module: work@M (work@top.genblk6.m3), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:61:13, endln:61:149 + \_module_inst: work@M (work@top.genblk6.m3), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:61:13, endln:61:149 |vpiOverriden:1 |vpiRhs: \_constant: @@ -17881,7 +17881,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:16:15, endln:16:21 |vpiParent: - \_module: work@M (work@top.genblk6.m3), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:61:13, endln:61:149 + \_module_inst: work@M (work@top.genblk6.m3), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:61:13, endln:61:149 |vpiOverriden:1 |vpiRhs: \_constant: @@ -17894,7 +17894,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:17:15, endln:17:21 |vpiParent: - \_module: work@M (work@top.genblk6.m3), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:61:13, endln:61:149 + \_module_inst: work@M (work@top.genblk6.m3), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:61:13, endln:61:149 |vpiOverriden:1 |vpiRhs: \_constant: @@ -17907,7 +17907,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:18:15, endln:18:16 |vpiParent: - \_module: work@M (work@top.genblk6.m3), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:61:13, endln:61:149 + \_module_inst: work@M (work@top.genblk6.m3), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:61:13, endln:61:149 |vpiLhs: \_parameter: (work@top.genblk6.m3.E), line:18:15, endln:18:16 |vpiDefName:work@M @@ -17916,7 +17916,7 @@ design: (work@top) |vpiProcess: \_initial: , line:21:5, endln:22:54 |vpiParent: - \_module: work@M (work@top.genblk6.m3), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:61:13, endln:61:149 + \_module_inst: work@M (work@top.genblk6.m3), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:61:13, endln:61:149 |vpiStmt: \_delay_control: , line:21:13, endln:21:19 |vpiParent: @@ -17981,8 +17981,8 @@ design: (work@top) \_type_parameter: (work@top.genblk8.m3.T), line:19:20, endln:19:21 |vpiName:$bits |vpiName:$display - |vpiInterface: - \_interface: work@I (work@top.genblk6.i1), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:56:13, endln:56:134 + |vpiInterfaceInst: + \_interface_inst: work@I (work@top.genblk6.i1), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:56:13, endln:56:134 |vpiParent: \_gen_scope: (work@top.genblk6) |vpiName:i1 @@ -17990,25 +17990,25 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.genblk6.i1.DELAY), line:26:15, endln:26:20 |vpiParent: - \_interface: work@I (work@top.genblk6.i1), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:56:13, endln:56:134 + \_interface_inst: work@I (work@top.genblk6.i1), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:56:13, endln:56:134 |vpiName:DELAY |vpiFullName:work@top.genblk6.i1.DELAY |vpiParameter: \_parameter: (work@top.genblk6.i1.PREFIX), line:27:15, endln:27:21 |vpiParent: - \_interface: work@I (work@top.genblk6.i1), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:56:13, endln:56:134 + \_interface_inst: work@I (work@top.genblk6.i1), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:56:13, endln:56:134 |vpiName:PREFIX |vpiFullName:work@top.genblk6.i1.PREFIX |vpiParameter: \_parameter: (work@top.genblk6.i1.SUFFIX), line:28:15, endln:28:21 |vpiParent: - \_interface: work@I (work@top.genblk6.i1), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:56:13, endln:56:134 + \_interface_inst: work@I (work@top.genblk6.i1), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:56:13, endln:56:134 |vpiName:SUFFIX |vpiFullName:work@top.genblk6.i1.SUFFIX |vpiParameter: \_parameter: (work@top.genblk6.i1.E), line:29:15, endln:29:16 |vpiParent: - \_interface: work@I (work@top.genblk6.i1), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:56:13, endln:56:134 + \_interface_inst: work@I (work@top.genblk6.i1), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:56:13, endln:56:134 |vpiName:E |vpiFullName:work@top.genblk6.i1.E |vpiParameter: @@ -18016,7 +18016,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:26:15, endln:26:20 |vpiParent: - \_interface: work@I (work@top.genblk6.i1), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:56:13, endln:56:134 + \_interface_inst: work@I (work@top.genblk6.i1), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:56:13, endln:56:134 |vpiOverriden:1 |vpiRhs: \_constant: @@ -18033,7 +18033,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:27:15, endln:27:21 |vpiParent: - \_interface: work@I (work@top.genblk6.i1), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:56:13, endln:56:134 + \_interface_inst: work@I (work@top.genblk6.i1), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:56:13, endln:56:134 |vpiOverriden:1 |vpiRhs: \_constant: @@ -18050,7 +18050,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:28:15, endln:28:21 |vpiParent: - \_interface: work@I (work@top.genblk6.i1), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:56:13, endln:56:134 + \_interface_inst: work@I (work@top.genblk6.i1), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:56:13, endln:56:134 |vpiOverriden:1 |vpiRhs: \_constant: @@ -18065,7 +18065,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:29:15, endln:29:16 |vpiParent: - \_interface: work@I (work@top.genblk6.i1), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:56:13, endln:56:134 + \_interface_inst: work@I (work@top.genblk6.i1), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:56:13, endln:56:134 |vpiRhs: \_constant: |vpiDecompile:3 @@ -18084,7 +18084,7 @@ design: (work@top) |vpiProcess: \_initial: , line:32:5, endln:33:54 |vpiParent: - \_interface: work@I (work@top.genblk6.i1), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:56:13, endln:56:134 + \_interface_inst: work@I (work@top.genblk6.i1), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:56:13, endln:56:134 |vpiStmt: \_delay_control: , line:32:13, endln:32:19 |vpiParent: @@ -18149,8 +18149,8 @@ design: (work@top) \_type_parameter: (work@top.genblk8.i3.T), line:30:20, endln:30:21 |vpiName:$bits |vpiName:$display - |vpiInterface: - \_interface: work@I (work@top.genblk6.i2), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:58:13, endln:58:143 + |vpiInterfaceInst: + \_interface_inst: work@I (work@top.genblk6.i2), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:58:13, endln:58:143 |vpiParent: \_gen_scope: (work@top.genblk6) |vpiName:i2 @@ -18158,25 +18158,25 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.genblk6.i2.DELAY), line:26:15, endln:26:20 |vpiParent: - \_interface: work@I (work@top.genblk6.i2), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:58:13, endln:58:143 + \_interface_inst: work@I (work@top.genblk6.i2), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:58:13, endln:58:143 |vpiName:DELAY |vpiFullName:work@top.genblk6.i2.DELAY |vpiParameter: \_parameter: (work@top.genblk6.i2.PREFIX), line:27:15, endln:27:21 |vpiParent: - \_interface: work@I (work@top.genblk6.i2), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:58:13, endln:58:143 + \_interface_inst: work@I (work@top.genblk6.i2), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:58:13, endln:58:143 |vpiName:PREFIX |vpiFullName:work@top.genblk6.i2.PREFIX |vpiParameter: \_parameter: (work@top.genblk6.i2.SUFFIX), line:28:15, endln:28:21 |vpiParent: - \_interface: work@I (work@top.genblk6.i2), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:58:13, endln:58:143 + \_interface_inst: work@I (work@top.genblk6.i2), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:58:13, endln:58:143 |vpiName:SUFFIX |vpiFullName:work@top.genblk6.i2.SUFFIX |vpiParameter: \_parameter: (work@top.genblk6.i2.E), line:29:15, endln:29:16 |vpiParent: - \_interface: work@I (work@top.genblk6.i2), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:58:13, endln:58:143 + \_interface_inst: work@I (work@top.genblk6.i2), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:58:13, endln:58:143 |vpiName:E |vpiFullName:work@top.genblk6.i2.E |vpiParameter: @@ -18184,7 +18184,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:26:15, endln:26:20 |vpiParent: - \_interface: work@I (work@top.genblk6.i2), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:58:13, endln:58:143 + \_interface_inst: work@I (work@top.genblk6.i2), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:58:13, endln:58:143 |vpiOverriden:1 |vpiRhs: \_constant: @@ -18201,7 +18201,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:27:15, endln:27:21 |vpiParent: - \_interface: work@I (work@top.genblk6.i2), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:58:13, endln:58:143 + \_interface_inst: work@I (work@top.genblk6.i2), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:58:13, endln:58:143 |vpiOverriden:1 |vpiRhs: \_constant: @@ -18218,7 +18218,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:28:15, endln:28:21 |vpiParent: - \_interface: work@I (work@top.genblk6.i2), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:58:13, endln:58:143 + \_interface_inst: work@I (work@top.genblk6.i2), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:58:13, endln:58:143 |vpiOverriden:1 |vpiRhs: \_constant: @@ -18235,7 +18235,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:29:15, endln:29:16 |vpiParent: - \_interface: work@I (work@top.genblk6.i2), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:58:13, endln:58:143 + \_interface_inst: work@I (work@top.genblk6.i2), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:58:13, endln:58:143 |vpiRhs: \_constant: |vpiDecompile:3 @@ -18254,7 +18254,7 @@ design: (work@top) |vpiProcess: \_initial: , line:32:5, endln:33:54 |vpiParent: - \_interface: work@I (work@top.genblk6.i2), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:58:13, endln:58:143 + \_interface_inst: work@I (work@top.genblk6.i2), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:58:13, endln:58:143 |vpiStmt: \_delay_control: , line:32:13, endln:32:19 |vpiParent: @@ -18319,8 +18319,8 @@ design: (work@top) \_type_parameter: (work@top.genblk8.i3.T), line:30:20, endln:30:21 |vpiName:$bits |vpiName:$display - |vpiInterface: - \_interface: work@I (work@top.genblk6.i3), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:60:13, endln:60:149 + |vpiInterfaceInst: + \_interface_inst: work@I (work@top.genblk6.i3), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:60:13, endln:60:149 |vpiParent: \_gen_scope: (work@top.genblk6) |vpiName:i3 @@ -18328,25 +18328,25 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.genblk6.i3.DELAY), line:26:15, endln:26:20 |vpiParent: - \_interface: work@I (work@top.genblk6.i3), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:60:13, endln:60:149 + \_interface_inst: work@I (work@top.genblk6.i3), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:60:13, endln:60:149 |vpiName:DELAY |vpiFullName:work@top.genblk6.i3.DELAY |vpiParameter: \_parameter: (work@top.genblk6.i3.PREFIX), line:27:15, endln:27:21 |vpiParent: - \_interface: work@I (work@top.genblk6.i3), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:60:13, endln:60:149 + \_interface_inst: work@I (work@top.genblk6.i3), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:60:13, endln:60:149 |vpiName:PREFIX |vpiFullName:work@top.genblk6.i3.PREFIX |vpiParameter: \_parameter: (work@top.genblk6.i3.SUFFIX), line:28:15, endln:28:21 |vpiParent: - \_interface: work@I (work@top.genblk6.i3), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:60:13, endln:60:149 + \_interface_inst: work@I (work@top.genblk6.i3), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:60:13, endln:60:149 |vpiName:SUFFIX |vpiFullName:work@top.genblk6.i3.SUFFIX |vpiParameter: \_parameter: (work@top.genblk6.i3.E), line:29:15, endln:29:16 |vpiParent: - \_interface: work@I (work@top.genblk6.i3), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:60:13, endln:60:149 + \_interface_inst: work@I (work@top.genblk6.i3), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:60:13, endln:60:149 |vpiName:E |vpiFullName:work@top.genblk6.i3.E |vpiParameter: @@ -18354,7 +18354,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:26:15, endln:26:20 |vpiParent: - \_interface: work@I (work@top.genblk6.i3), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:60:13, endln:60:149 + \_interface_inst: work@I (work@top.genblk6.i3), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:60:13, endln:60:149 |vpiOverriden:1 |vpiRhs: \_constant: @@ -18371,7 +18371,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:27:15, endln:27:21 |vpiParent: - \_interface: work@I (work@top.genblk6.i3), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:60:13, endln:60:149 + \_interface_inst: work@I (work@top.genblk6.i3), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:60:13, endln:60:149 |vpiOverriden:1 |vpiRhs: \_constant: @@ -18388,7 +18388,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:28:15, endln:28:21 |vpiParent: - \_interface: work@I (work@top.genblk6.i3), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:60:13, endln:60:149 + \_interface_inst: work@I (work@top.genblk6.i3), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:60:13, endln:60:149 |vpiOverriden:1 |vpiRhs: \_constant: @@ -18405,7 +18405,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:29:15, endln:29:16 |vpiParent: - \_interface: work@I (work@top.genblk6.i3), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:60:13, endln:60:149 + \_interface_inst: work@I (work@top.genblk6.i3), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:60:13, endln:60:149 |vpiRhs: \_constant: |vpiDecompile:3 @@ -18424,7 +18424,7 @@ design: (work@top) |vpiProcess: \_initial: , line:32:5, endln:33:54 |vpiParent: - \_interface: work@I (work@top.genblk6.i3), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:60:13, endln:60:149 + \_interface_inst: work@I (work@top.genblk6.i3), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:60:13, endln:60:149 |vpiStmt: \_delay_control: , line:32:13, endln:32:19 |vpiParent: @@ -18492,7 +18492,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.genblk7), line:43:9, endln:62:12 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:36:1, endln:74:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:36:1, endln:74:10 |vpiName:genblk7 |vpiFullName:work@top.genblk7 |vpiGenScope: @@ -18751,8 +18751,8 @@ design: (work@top) |BIN:Z |vpiConstType:3 |vpiName:$display - |vpiModule: - \_module: work@M (work@top.genblk7.m1), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:57:13, endln:57:92 + |vpiModuleInst: + \_module_inst: work@M (work@top.genblk7.m1), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:57:13, endln:57:92 |vpiParent: \_gen_scope: (work@top.genblk7) |vpiName:m1 @@ -18786,7 +18786,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:15:15, endln:15:20 |vpiParent: - \_module: work@M (work@top.genblk7.m1), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:57:13, endln:57:92 + \_module_inst: work@M (work@top.genblk7.m1), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:57:13, endln:57:92 |vpiOverriden:1 |vpiRhs: \_constant: @@ -18799,7 +18799,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:16:15, endln:16:21 |vpiParent: - \_module: work@M (work@top.genblk7.m1), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:57:13, endln:57:92 + \_module_inst: work@M (work@top.genblk7.m1), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:57:13, endln:57:92 |vpiOverriden:1 |vpiRhs: \_constant: @@ -18812,7 +18812,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:17:15, endln:17:21 |vpiParent: - \_module: work@M (work@top.genblk7.m1), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:57:13, endln:57:92 + \_module_inst: work@M (work@top.genblk7.m1), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:57:13, endln:57:92 |vpiOverriden:1 |vpiRhs: \_constant: @@ -18823,7 +18823,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:18:15, endln:18:16 |vpiParent: - \_module: work@M (work@top.genblk7.m1), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:57:13, endln:57:92 + \_module_inst: work@M (work@top.genblk7.m1), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:57:13, endln:57:92 |vpiLhs: \_parameter: (work@top.genblk7.m1.E), line:18:15, endln:18:16 |vpiDefName:work@M @@ -18832,7 +18832,7 @@ design: (work@top) |vpiProcess: \_initial: , line:21:5, endln:22:54 |vpiParent: - \_module: work@M (work@top.genblk7.m1), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:57:13, endln:57:92 + \_module_inst: work@M (work@top.genblk7.m1), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:57:13, endln:57:92 |vpiStmt: \_delay_control: , line:21:13, endln:21:19 |vpiParent: @@ -18897,8 +18897,8 @@ design: (work@top) \_type_parameter: (work@top.genblk8.m3.T), line:19:20, endln:19:21 |vpiName:$bits |vpiName:$display - |vpiModule: - \_module: work@M (work@top.genblk7.m2), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:59:13, endln:59:101 + |vpiModuleInst: + \_module_inst: work@M (work@top.genblk7.m2), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:59:13, endln:59:101 |vpiParent: \_gen_scope: (work@top.genblk7) |vpiName:m2 @@ -18932,7 +18932,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:15:15, endln:15:20 |vpiParent: - \_module: work@M (work@top.genblk7.m2), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:59:13, endln:59:101 + \_module_inst: work@M (work@top.genblk7.m2), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:59:13, endln:59:101 |vpiOverriden:1 |vpiRhs: \_constant: @@ -18945,7 +18945,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:16:15, endln:16:21 |vpiParent: - \_module: work@M (work@top.genblk7.m2), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:59:13, endln:59:101 + \_module_inst: work@M (work@top.genblk7.m2), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:59:13, endln:59:101 |vpiOverriden:1 |vpiRhs: \_constant: @@ -18958,7 +18958,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:17:15, endln:17:21 |vpiParent: - \_module: work@M (work@top.genblk7.m2), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:59:13, endln:59:101 + \_module_inst: work@M (work@top.genblk7.m2), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:59:13, endln:59:101 |vpiOverriden:1 |vpiRhs: \_constant: @@ -18971,7 +18971,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:18:15, endln:18:16 |vpiParent: - \_module: work@M (work@top.genblk7.m2), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:59:13, endln:59:101 + \_module_inst: work@M (work@top.genblk7.m2), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:59:13, endln:59:101 |vpiLhs: \_parameter: (work@top.genblk7.m2.E), line:18:15, endln:18:16 |vpiDefName:work@M @@ -18980,7 +18980,7 @@ design: (work@top) |vpiProcess: \_initial: , line:21:5, endln:22:54 |vpiParent: - \_module: work@M (work@top.genblk7.m2), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:59:13, endln:59:101 + \_module_inst: work@M (work@top.genblk7.m2), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:59:13, endln:59:101 |vpiStmt: \_delay_control: , line:21:13, endln:21:19 |vpiParent: @@ -19045,8 +19045,8 @@ design: (work@top) \_type_parameter: (work@top.genblk8.m3.T), line:19:20, endln:19:21 |vpiName:$bits |vpiName:$display - |vpiModule: - \_module: work@M (work@top.genblk7.m3), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:61:13, endln:61:107 + |vpiModuleInst: + \_module_inst: work@M (work@top.genblk7.m3), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:61:13, endln:61:107 |vpiParent: \_gen_scope: (work@top.genblk7) |vpiName:m3 @@ -19080,7 +19080,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:15:15, endln:15:20 |vpiParent: - \_module: work@M (work@top.genblk7.m3), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:61:13, endln:61:107 + \_module_inst: work@M (work@top.genblk7.m3), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:61:13, endln:61:107 |vpiOverriden:1 |vpiRhs: \_constant: @@ -19093,7 +19093,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:16:15, endln:16:21 |vpiParent: - \_module: work@M (work@top.genblk7.m3), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:61:13, endln:61:107 + \_module_inst: work@M (work@top.genblk7.m3), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:61:13, endln:61:107 |vpiOverriden:1 |vpiRhs: \_constant: @@ -19106,7 +19106,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:17:15, endln:17:21 |vpiParent: - \_module: work@M (work@top.genblk7.m3), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:61:13, endln:61:107 + \_module_inst: work@M (work@top.genblk7.m3), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:61:13, endln:61:107 |vpiOverriden:1 |vpiRhs: \_constant: @@ -19119,7 +19119,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:18:15, endln:18:16 |vpiParent: - \_module: work@M (work@top.genblk7.m3), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:61:13, endln:61:107 + \_module_inst: work@M (work@top.genblk7.m3), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:61:13, endln:61:107 |vpiLhs: \_parameter: (work@top.genblk7.m3.E), line:18:15, endln:18:16 |vpiDefName:work@M @@ -19128,7 +19128,7 @@ design: (work@top) |vpiProcess: \_initial: , line:21:5, endln:22:54 |vpiParent: - \_module: work@M (work@top.genblk7.m3), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:61:13, endln:61:107 + \_module_inst: work@M (work@top.genblk7.m3), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:61:13, endln:61:107 |vpiStmt: \_delay_control: , line:21:13, endln:21:19 |vpiParent: @@ -19193,8 +19193,8 @@ design: (work@top) \_type_parameter: (work@top.genblk8.m3.T), line:19:20, endln:19:21 |vpiName:$bits |vpiName:$display - |vpiInterface: - \_interface: work@I (work@top.genblk7.i1), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:56:13, endln:56:92 + |vpiInterfaceInst: + \_interface_inst: work@I (work@top.genblk7.i1), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:56:13, endln:56:92 |vpiParent: \_gen_scope: (work@top.genblk7) |vpiName:i1 @@ -19202,25 +19202,25 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.genblk7.i1.DELAY), line:26:15, endln:26:20 |vpiParent: - \_interface: work@I (work@top.genblk7.i1), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:56:13, endln:56:92 + \_interface_inst: work@I (work@top.genblk7.i1), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:56:13, endln:56:92 |vpiName:DELAY |vpiFullName:work@top.genblk7.i1.DELAY |vpiParameter: \_parameter: (work@top.genblk7.i1.PREFIX), line:27:15, endln:27:21 |vpiParent: - \_interface: work@I (work@top.genblk7.i1), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:56:13, endln:56:92 + \_interface_inst: work@I (work@top.genblk7.i1), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:56:13, endln:56:92 |vpiName:PREFIX |vpiFullName:work@top.genblk7.i1.PREFIX |vpiParameter: \_parameter: (work@top.genblk7.i1.SUFFIX), line:28:15, endln:28:21 |vpiParent: - \_interface: work@I (work@top.genblk7.i1), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:56:13, endln:56:92 + \_interface_inst: work@I (work@top.genblk7.i1), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:56:13, endln:56:92 |vpiName:SUFFIX |vpiFullName:work@top.genblk7.i1.SUFFIX |vpiParameter: \_parameter: (work@top.genblk7.i1.E), line:29:15, endln:29:16 |vpiParent: - \_interface: work@I (work@top.genblk7.i1), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:56:13, endln:56:92 + \_interface_inst: work@I (work@top.genblk7.i1), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:56:13, endln:56:92 |vpiName:E |vpiFullName:work@top.genblk7.i1.E |vpiParameter: @@ -19228,7 +19228,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:26:15, endln:26:20 |vpiParent: - \_interface: work@I (work@top.genblk7.i1), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:56:13, endln:56:92 + \_interface_inst: work@I (work@top.genblk7.i1), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:56:13, endln:56:92 |vpiOverriden:1 |vpiRhs: \_constant: @@ -19245,7 +19245,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:27:15, endln:27:21 |vpiParent: - \_interface: work@I (work@top.genblk7.i1), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:56:13, endln:56:92 + \_interface_inst: work@I (work@top.genblk7.i1), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:56:13, endln:56:92 |vpiOverriden:1 |vpiRhs: \_constant: @@ -19262,7 +19262,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:28:15, endln:28:21 |vpiParent: - \_interface: work@I (work@top.genblk7.i1), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:56:13, endln:56:92 + \_interface_inst: work@I (work@top.genblk7.i1), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:56:13, endln:56:92 |vpiOverriden:1 |vpiRhs: \_constant: @@ -19277,7 +19277,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:29:15, endln:29:16 |vpiParent: - \_interface: work@I (work@top.genblk7.i1), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:56:13, endln:56:92 + \_interface_inst: work@I (work@top.genblk7.i1), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:56:13, endln:56:92 |vpiRhs: \_constant: |vpiDecompile:3 @@ -19296,7 +19296,7 @@ design: (work@top) |vpiProcess: \_initial: , line:32:5, endln:33:54 |vpiParent: - \_interface: work@I (work@top.genblk7.i1), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:56:13, endln:56:92 + \_interface_inst: work@I (work@top.genblk7.i1), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:56:13, endln:56:92 |vpiStmt: \_delay_control: , line:32:13, endln:32:19 |vpiParent: @@ -19361,8 +19361,8 @@ design: (work@top) \_type_parameter: (work@top.genblk8.i3.T), line:30:20, endln:30:21 |vpiName:$bits |vpiName:$display - |vpiInterface: - \_interface: work@I (work@top.genblk7.i2), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:58:13, endln:58:101 + |vpiInterfaceInst: + \_interface_inst: work@I (work@top.genblk7.i2), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:58:13, endln:58:101 |vpiParent: \_gen_scope: (work@top.genblk7) |vpiName:i2 @@ -19370,25 +19370,25 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.genblk7.i2.DELAY), line:26:15, endln:26:20 |vpiParent: - \_interface: work@I (work@top.genblk7.i2), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:58:13, endln:58:101 + \_interface_inst: work@I (work@top.genblk7.i2), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:58:13, endln:58:101 |vpiName:DELAY |vpiFullName:work@top.genblk7.i2.DELAY |vpiParameter: \_parameter: (work@top.genblk7.i2.PREFIX), line:27:15, endln:27:21 |vpiParent: - \_interface: work@I (work@top.genblk7.i2), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:58:13, endln:58:101 + \_interface_inst: work@I (work@top.genblk7.i2), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:58:13, endln:58:101 |vpiName:PREFIX |vpiFullName:work@top.genblk7.i2.PREFIX |vpiParameter: \_parameter: (work@top.genblk7.i2.SUFFIX), line:28:15, endln:28:21 |vpiParent: - \_interface: work@I (work@top.genblk7.i2), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:58:13, endln:58:101 + \_interface_inst: work@I (work@top.genblk7.i2), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:58:13, endln:58:101 |vpiName:SUFFIX |vpiFullName:work@top.genblk7.i2.SUFFIX |vpiParameter: \_parameter: (work@top.genblk7.i2.E), line:29:15, endln:29:16 |vpiParent: - \_interface: work@I (work@top.genblk7.i2), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:58:13, endln:58:101 + \_interface_inst: work@I (work@top.genblk7.i2), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:58:13, endln:58:101 |vpiName:E |vpiFullName:work@top.genblk7.i2.E |vpiParameter: @@ -19396,7 +19396,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:26:15, endln:26:20 |vpiParent: - \_interface: work@I (work@top.genblk7.i2), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:58:13, endln:58:101 + \_interface_inst: work@I (work@top.genblk7.i2), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:58:13, endln:58:101 |vpiOverriden:1 |vpiRhs: \_constant: @@ -19413,7 +19413,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:27:15, endln:27:21 |vpiParent: - \_interface: work@I (work@top.genblk7.i2), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:58:13, endln:58:101 + \_interface_inst: work@I (work@top.genblk7.i2), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:58:13, endln:58:101 |vpiOverriden:1 |vpiRhs: \_constant: @@ -19430,7 +19430,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:28:15, endln:28:21 |vpiParent: - \_interface: work@I (work@top.genblk7.i2), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:58:13, endln:58:101 + \_interface_inst: work@I (work@top.genblk7.i2), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:58:13, endln:58:101 |vpiOverriden:1 |vpiRhs: \_constant: @@ -19447,7 +19447,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:29:15, endln:29:16 |vpiParent: - \_interface: work@I (work@top.genblk7.i2), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:58:13, endln:58:101 + \_interface_inst: work@I (work@top.genblk7.i2), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:58:13, endln:58:101 |vpiRhs: \_constant: |vpiDecompile:3 @@ -19466,7 +19466,7 @@ design: (work@top) |vpiProcess: \_initial: , line:32:5, endln:33:54 |vpiParent: - \_interface: work@I (work@top.genblk7.i2), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:58:13, endln:58:101 + \_interface_inst: work@I (work@top.genblk7.i2), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:58:13, endln:58:101 |vpiStmt: \_delay_control: , line:32:13, endln:32:19 |vpiParent: @@ -19531,8 +19531,8 @@ design: (work@top) \_type_parameter: (work@top.genblk8.i3.T), line:30:20, endln:30:21 |vpiName:$bits |vpiName:$display - |vpiInterface: - \_interface: work@I (work@top.genblk7.i3), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:60:13, endln:60:107 + |vpiInterfaceInst: + \_interface_inst: work@I (work@top.genblk7.i3), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:60:13, endln:60:107 |vpiParent: \_gen_scope: (work@top.genblk7) |vpiName:i3 @@ -19540,25 +19540,25 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.genblk7.i3.DELAY), line:26:15, endln:26:20 |vpiParent: - \_interface: work@I (work@top.genblk7.i3), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:60:13, endln:60:107 + \_interface_inst: work@I (work@top.genblk7.i3), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:60:13, endln:60:107 |vpiName:DELAY |vpiFullName:work@top.genblk7.i3.DELAY |vpiParameter: \_parameter: (work@top.genblk7.i3.PREFIX), line:27:15, endln:27:21 |vpiParent: - \_interface: work@I (work@top.genblk7.i3), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:60:13, endln:60:107 + \_interface_inst: work@I (work@top.genblk7.i3), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:60:13, endln:60:107 |vpiName:PREFIX |vpiFullName:work@top.genblk7.i3.PREFIX |vpiParameter: \_parameter: (work@top.genblk7.i3.SUFFIX), line:28:15, endln:28:21 |vpiParent: - \_interface: work@I (work@top.genblk7.i3), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:60:13, endln:60:107 + \_interface_inst: work@I (work@top.genblk7.i3), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:60:13, endln:60:107 |vpiName:SUFFIX |vpiFullName:work@top.genblk7.i3.SUFFIX |vpiParameter: \_parameter: (work@top.genblk7.i3.E), line:29:15, endln:29:16 |vpiParent: - \_interface: work@I (work@top.genblk7.i3), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:60:13, endln:60:107 + \_interface_inst: work@I (work@top.genblk7.i3), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:60:13, endln:60:107 |vpiName:E |vpiFullName:work@top.genblk7.i3.E |vpiParameter: @@ -19566,7 +19566,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:26:15, endln:26:20 |vpiParent: - \_interface: work@I (work@top.genblk7.i3), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:60:13, endln:60:107 + \_interface_inst: work@I (work@top.genblk7.i3), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:60:13, endln:60:107 |vpiOverriden:1 |vpiRhs: \_constant: @@ -19583,7 +19583,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:27:15, endln:27:21 |vpiParent: - \_interface: work@I (work@top.genblk7.i3), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:60:13, endln:60:107 + \_interface_inst: work@I (work@top.genblk7.i3), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:60:13, endln:60:107 |vpiOverriden:1 |vpiRhs: \_constant: @@ -19600,7 +19600,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:28:15, endln:28:21 |vpiParent: - \_interface: work@I (work@top.genblk7.i3), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:60:13, endln:60:107 + \_interface_inst: work@I (work@top.genblk7.i3), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:60:13, endln:60:107 |vpiOverriden:1 |vpiRhs: \_constant: @@ -19617,7 +19617,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:29:15, endln:29:16 |vpiParent: - \_interface: work@I (work@top.genblk7.i3), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:60:13, endln:60:107 + \_interface_inst: work@I (work@top.genblk7.i3), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:60:13, endln:60:107 |vpiRhs: \_constant: |vpiDecompile:3 @@ -19636,7 +19636,7 @@ design: (work@top) |vpiProcess: \_initial: , line:32:5, endln:33:54 |vpiParent: - \_interface: work@I (work@top.genblk7.i3), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:60:13, endln:60:107 + \_interface_inst: work@I (work@top.genblk7.i3), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:60:13, endln:60:107 |vpiStmt: \_delay_control: , line:32:13, endln:32:19 |vpiParent: @@ -19704,7 +19704,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.genblk8), line:43:9, endln:62:12 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:36:1, endln:74:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:36:1, endln:74:10 |vpiName:genblk8 |vpiFullName:work@top.genblk8 |vpiGenScope: @@ -19963,8 +19963,8 @@ design: (work@top) |BIN:Z |vpiConstType:3 |vpiName:$display - |vpiModule: - \_module: work@M (work@top.genblk8.m1), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:57:13, endln:57:104 + |vpiModuleInst: + \_module_inst: work@M (work@top.genblk8.m1), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:57:13, endln:57:104 |vpiParent: \_gen_scope: (work@top.genblk8) |vpiName:m1 @@ -19998,7 +19998,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:15:15, endln:15:20 |vpiParent: - \_module: work@M (work@top.genblk8.m1), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:57:13, endln:57:104 + \_module_inst: work@M (work@top.genblk8.m1), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:57:13, endln:57:104 |vpiOverriden:1 |vpiRhs: \_constant: @@ -20011,7 +20011,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:16:15, endln:16:21 |vpiParent: - \_module: work@M (work@top.genblk8.m1), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:57:13, endln:57:104 + \_module_inst: work@M (work@top.genblk8.m1), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:57:13, endln:57:104 |vpiOverriden:1 |vpiRhs: \_constant: @@ -20024,7 +20024,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:17:15, endln:17:21 |vpiParent: - \_module: work@M (work@top.genblk8.m1), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:57:13, endln:57:104 + \_module_inst: work@M (work@top.genblk8.m1), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:57:13, endln:57:104 |vpiOverriden:1 |vpiRhs: \_constant: @@ -20035,7 +20035,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:18:15, endln:18:16 |vpiParent: - \_module: work@M (work@top.genblk8.m1), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:57:13, endln:57:104 + \_module_inst: work@M (work@top.genblk8.m1), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:57:13, endln:57:104 |vpiLhs: \_parameter: (work@top.genblk8.m1.E), line:18:15, endln:18:16 |vpiDefName:work@M @@ -20044,7 +20044,7 @@ design: (work@top) |vpiProcess: \_initial: , line:21:5, endln:22:54 |vpiParent: - \_module: work@M (work@top.genblk8.m1), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:57:13, endln:57:104 + \_module_inst: work@M (work@top.genblk8.m1), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:57:13, endln:57:104 |vpiStmt: \_delay_control: , line:21:13, endln:21:19 |vpiParent: @@ -20109,8 +20109,8 @@ design: (work@top) \_type_parameter: (work@top.genblk8.m3.T), line:19:20, endln:19:21 |vpiName:$bits |vpiName:$display - |vpiModule: - \_module: work@M (work@top.genblk8.m2), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:59:13, endln:59:113 + |vpiModuleInst: + \_module_inst: work@M (work@top.genblk8.m2), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:59:13, endln:59:113 |vpiParent: \_gen_scope: (work@top.genblk8) |vpiName:m2 @@ -20144,7 +20144,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:15:15, endln:15:20 |vpiParent: - \_module: work@M (work@top.genblk8.m2), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:59:13, endln:59:113 + \_module_inst: work@M (work@top.genblk8.m2), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:59:13, endln:59:113 |vpiOverriden:1 |vpiRhs: \_constant: @@ -20157,7 +20157,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:16:15, endln:16:21 |vpiParent: - \_module: work@M (work@top.genblk8.m2), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:59:13, endln:59:113 + \_module_inst: work@M (work@top.genblk8.m2), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:59:13, endln:59:113 |vpiOverriden:1 |vpiRhs: \_constant: @@ -20170,7 +20170,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:17:15, endln:17:21 |vpiParent: - \_module: work@M (work@top.genblk8.m2), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:59:13, endln:59:113 + \_module_inst: work@M (work@top.genblk8.m2), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:59:13, endln:59:113 |vpiOverriden:1 |vpiRhs: \_constant: @@ -20183,7 +20183,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:18:15, endln:18:16 |vpiParent: - \_module: work@M (work@top.genblk8.m2), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:59:13, endln:59:113 + \_module_inst: work@M (work@top.genblk8.m2), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:59:13, endln:59:113 |vpiLhs: \_parameter: (work@top.genblk8.m2.E), line:18:15, endln:18:16 |vpiDefName:work@M @@ -20192,7 +20192,7 @@ design: (work@top) |vpiProcess: \_initial: , line:21:5, endln:22:54 |vpiParent: - \_module: work@M (work@top.genblk8.m2), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:59:13, endln:59:113 + \_module_inst: work@M (work@top.genblk8.m2), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:59:13, endln:59:113 |vpiStmt: \_delay_control: , line:21:13, endln:21:19 |vpiParent: @@ -20257,8 +20257,8 @@ design: (work@top) \_type_parameter: (work@top.genblk8.m3.T), line:19:20, endln:19:21 |vpiName:$bits |vpiName:$display - |vpiModule: - \_module: work@M (work@top.genblk8.m3), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:61:13, endln:61:119 + |vpiModuleInst: + \_module_inst: work@M (work@top.genblk8.m3), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:61:13, endln:61:119 |vpiParent: \_gen_scope: (work@top.genblk8) |vpiName:m3 @@ -20292,7 +20292,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:15:15, endln:15:20 |vpiParent: - \_module: work@M (work@top.genblk8.m3), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:61:13, endln:61:119 + \_module_inst: work@M (work@top.genblk8.m3), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:61:13, endln:61:119 |vpiOverriden:1 |vpiRhs: \_constant: @@ -20305,7 +20305,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:16:15, endln:16:21 |vpiParent: - \_module: work@M (work@top.genblk8.m3), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:61:13, endln:61:119 + \_module_inst: work@M (work@top.genblk8.m3), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:61:13, endln:61:119 |vpiOverriden:1 |vpiRhs: \_constant: @@ -20318,7 +20318,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:17:15, endln:17:21 |vpiParent: - \_module: work@M (work@top.genblk8.m3), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:61:13, endln:61:119 + \_module_inst: work@M (work@top.genblk8.m3), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:61:13, endln:61:119 |vpiOverriden:1 |vpiRhs: \_constant: @@ -20331,7 +20331,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:18:15, endln:18:16 |vpiParent: - \_module: work@M (work@top.genblk8.m3), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:61:13, endln:61:119 + \_module_inst: work@M (work@top.genblk8.m3), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:61:13, endln:61:119 |vpiLhs: \_parameter: (work@top.genblk8.m3.E), line:18:15, endln:18:16 |vpiDefName:work@M @@ -20340,7 +20340,7 @@ design: (work@top) |vpiProcess: \_initial: , line:21:5, endln:22:54 |vpiParent: - \_module: work@M (work@top.genblk8.m3), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:61:13, endln:61:119 + \_module_inst: work@M (work@top.genblk8.m3), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:61:13, endln:61:119 |vpiStmt: \_delay_control: , line:21:13, endln:21:19 |vpiParent: @@ -20405,8 +20405,8 @@ design: (work@top) \_type_parameter: (work@top.genblk8.m3.T), line:19:20, endln:19:21 |vpiName:$bits |vpiName:$display - |vpiInterface: - \_interface: work@I (work@top.genblk8.i1), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:56:13, endln:56:104 + |vpiInterfaceInst: + \_interface_inst: work@I (work@top.genblk8.i1), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:56:13, endln:56:104 |vpiParent: \_gen_scope: (work@top.genblk8) |vpiName:i1 @@ -20414,25 +20414,25 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.genblk8.i1.DELAY), line:26:15, endln:26:20 |vpiParent: - \_interface: work@I (work@top.genblk8.i1), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:56:13, endln:56:104 + \_interface_inst: work@I (work@top.genblk8.i1), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:56:13, endln:56:104 |vpiName:DELAY |vpiFullName:work@top.genblk8.i1.DELAY |vpiParameter: \_parameter: (work@top.genblk8.i1.PREFIX), line:27:15, endln:27:21 |vpiParent: - \_interface: work@I (work@top.genblk8.i1), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:56:13, endln:56:104 + \_interface_inst: work@I (work@top.genblk8.i1), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:56:13, endln:56:104 |vpiName:PREFIX |vpiFullName:work@top.genblk8.i1.PREFIX |vpiParameter: \_parameter: (work@top.genblk8.i1.SUFFIX), line:28:15, endln:28:21 |vpiParent: - \_interface: work@I (work@top.genblk8.i1), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:56:13, endln:56:104 + \_interface_inst: work@I (work@top.genblk8.i1), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:56:13, endln:56:104 |vpiName:SUFFIX |vpiFullName:work@top.genblk8.i1.SUFFIX |vpiParameter: \_parameter: (work@top.genblk8.i1.E), line:29:15, endln:29:16 |vpiParent: - \_interface: work@I (work@top.genblk8.i1), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:56:13, endln:56:104 + \_interface_inst: work@I (work@top.genblk8.i1), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:56:13, endln:56:104 |vpiName:E |vpiFullName:work@top.genblk8.i1.E |vpiParameter: @@ -20440,7 +20440,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:26:15, endln:26:20 |vpiParent: - \_interface: work@I (work@top.genblk8.i1), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:56:13, endln:56:104 + \_interface_inst: work@I (work@top.genblk8.i1), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:56:13, endln:56:104 |vpiOverriden:1 |vpiRhs: \_constant: @@ -20457,7 +20457,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:27:15, endln:27:21 |vpiParent: - \_interface: work@I (work@top.genblk8.i1), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:56:13, endln:56:104 + \_interface_inst: work@I (work@top.genblk8.i1), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:56:13, endln:56:104 |vpiOverriden:1 |vpiRhs: \_constant: @@ -20474,7 +20474,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:28:15, endln:28:21 |vpiParent: - \_interface: work@I (work@top.genblk8.i1), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:56:13, endln:56:104 + \_interface_inst: work@I (work@top.genblk8.i1), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:56:13, endln:56:104 |vpiOverriden:1 |vpiRhs: \_constant: @@ -20489,7 +20489,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:29:15, endln:29:16 |vpiParent: - \_interface: work@I (work@top.genblk8.i1), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:56:13, endln:56:104 + \_interface_inst: work@I (work@top.genblk8.i1), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:56:13, endln:56:104 |vpiRhs: \_constant: |vpiDecompile:3 @@ -20508,7 +20508,7 @@ design: (work@top) |vpiProcess: \_initial: , line:32:5, endln:33:54 |vpiParent: - \_interface: work@I (work@top.genblk8.i1), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:56:13, endln:56:104 + \_interface_inst: work@I (work@top.genblk8.i1), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:56:13, endln:56:104 |vpiStmt: \_delay_control: , line:32:13, endln:32:19 |vpiParent: @@ -20573,8 +20573,8 @@ design: (work@top) \_type_parameter: (work@top.genblk8.i3.T), line:30:20, endln:30:21 |vpiName:$bits |vpiName:$display - |vpiInterface: - \_interface: work@I (work@top.genblk8.i2), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:58:13, endln:58:113 + |vpiInterfaceInst: + \_interface_inst: work@I (work@top.genblk8.i2), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:58:13, endln:58:113 |vpiParent: \_gen_scope: (work@top.genblk8) |vpiName:i2 @@ -20582,25 +20582,25 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.genblk8.i2.DELAY), line:26:15, endln:26:20 |vpiParent: - \_interface: work@I (work@top.genblk8.i2), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:58:13, endln:58:113 + \_interface_inst: work@I (work@top.genblk8.i2), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:58:13, endln:58:113 |vpiName:DELAY |vpiFullName:work@top.genblk8.i2.DELAY |vpiParameter: \_parameter: (work@top.genblk8.i2.PREFIX), line:27:15, endln:27:21 |vpiParent: - \_interface: work@I (work@top.genblk8.i2), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:58:13, endln:58:113 + \_interface_inst: work@I (work@top.genblk8.i2), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:58:13, endln:58:113 |vpiName:PREFIX |vpiFullName:work@top.genblk8.i2.PREFIX |vpiParameter: \_parameter: (work@top.genblk8.i2.SUFFIX), line:28:15, endln:28:21 |vpiParent: - \_interface: work@I (work@top.genblk8.i2), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:58:13, endln:58:113 + \_interface_inst: work@I (work@top.genblk8.i2), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:58:13, endln:58:113 |vpiName:SUFFIX |vpiFullName:work@top.genblk8.i2.SUFFIX |vpiParameter: \_parameter: (work@top.genblk8.i2.E), line:29:15, endln:29:16 |vpiParent: - \_interface: work@I (work@top.genblk8.i2), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:58:13, endln:58:113 + \_interface_inst: work@I (work@top.genblk8.i2), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:58:13, endln:58:113 |vpiName:E |vpiFullName:work@top.genblk8.i2.E |vpiParameter: @@ -20608,7 +20608,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:26:15, endln:26:20 |vpiParent: - \_interface: work@I (work@top.genblk8.i2), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:58:13, endln:58:113 + \_interface_inst: work@I (work@top.genblk8.i2), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:58:13, endln:58:113 |vpiOverriden:1 |vpiRhs: \_constant: @@ -20625,7 +20625,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:27:15, endln:27:21 |vpiParent: - \_interface: work@I (work@top.genblk8.i2), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:58:13, endln:58:113 + \_interface_inst: work@I (work@top.genblk8.i2), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:58:13, endln:58:113 |vpiOverriden:1 |vpiRhs: \_constant: @@ -20642,7 +20642,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:28:15, endln:28:21 |vpiParent: - \_interface: work@I (work@top.genblk8.i2), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:58:13, endln:58:113 + \_interface_inst: work@I (work@top.genblk8.i2), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:58:13, endln:58:113 |vpiOverriden:1 |vpiRhs: \_constant: @@ -20659,7 +20659,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:29:15, endln:29:16 |vpiParent: - \_interface: work@I (work@top.genblk8.i2), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:58:13, endln:58:113 + \_interface_inst: work@I (work@top.genblk8.i2), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:58:13, endln:58:113 |vpiRhs: \_constant: |vpiDecompile:3 @@ -20678,7 +20678,7 @@ design: (work@top) |vpiProcess: \_initial: , line:32:5, endln:33:54 |vpiParent: - \_interface: work@I (work@top.genblk8.i2), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:58:13, endln:58:113 + \_interface_inst: work@I (work@top.genblk8.i2), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:58:13, endln:58:113 |vpiStmt: \_delay_control: , line:32:13, endln:32:19 |vpiParent: @@ -20743,8 +20743,8 @@ design: (work@top) \_type_parameter: (work@top.genblk8.i3.T), line:30:20, endln:30:21 |vpiName:$bits |vpiName:$display - |vpiInterface: - \_interface: work@I (work@top.genblk8.i3), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:60:13, endln:60:119 + |vpiInterfaceInst: + \_interface_inst: work@I (work@top.genblk8.i3), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:60:13, endln:60:119 |vpiParent: \_gen_scope: (work@top.genblk8) |vpiName:i3 @@ -20752,25 +20752,25 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.genblk8.i3.DELAY), line:26:15, endln:26:20 |vpiParent: - \_interface: work@I (work@top.genblk8.i3), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:60:13, endln:60:119 + \_interface_inst: work@I (work@top.genblk8.i3), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:60:13, endln:60:119 |vpiName:DELAY |vpiFullName:work@top.genblk8.i3.DELAY |vpiParameter: \_parameter: (work@top.genblk8.i3.PREFIX), line:27:15, endln:27:21 |vpiParent: - \_interface: work@I (work@top.genblk8.i3), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:60:13, endln:60:119 + \_interface_inst: work@I (work@top.genblk8.i3), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:60:13, endln:60:119 |vpiName:PREFIX |vpiFullName:work@top.genblk8.i3.PREFIX |vpiParameter: \_parameter: (work@top.genblk8.i3.SUFFIX), line:28:15, endln:28:21 |vpiParent: - \_interface: work@I (work@top.genblk8.i3), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:60:13, endln:60:119 + \_interface_inst: work@I (work@top.genblk8.i3), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:60:13, endln:60:119 |vpiName:SUFFIX |vpiFullName:work@top.genblk8.i3.SUFFIX |vpiParameter: \_parameter: (work@top.genblk8.i3.E), line:29:15, endln:29:16 |vpiParent: - \_interface: work@I (work@top.genblk8.i3), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:60:13, endln:60:119 + \_interface_inst: work@I (work@top.genblk8.i3), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:60:13, endln:60:119 |vpiName:E |vpiFullName:work@top.genblk8.i3.E |vpiParameter: @@ -20778,7 +20778,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:26:15, endln:26:20 |vpiParent: - \_interface: work@I (work@top.genblk8.i3), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:60:13, endln:60:119 + \_interface_inst: work@I (work@top.genblk8.i3), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:60:13, endln:60:119 |vpiOverriden:1 |vpiRhs: \_constant: @@ -20795,7 +20795,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:27:15, endln:27:21 |vpiParent: - \_interface: work@I (work@top.genblk8.i3), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:60:13, endln:60:119 + \_interface_inst: work@I (work@top.genblk8.i3), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:60:13, endln:60:119 |vpiOverriden:1 |vpiRhs: \_constant: @@ -20812,7 +20812,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:28:15, endln:28:21 |vpiParent: - \_interface: work@I (work@top.genblk8.i3), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:60:13, endln:60:119 + \_interface_inst: work@I (work@top.genblk8.i3), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:60:13, endln:60:119 |vpiOverriden:1 |vpiRhs: \_constant: @@ -20829,7 +20829,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:29:15, endln:29:16 |vpiParent: - \_interface: work@I (work@top.genblk8.i3), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:60:13, endln:60:119 + \_interface_inst: work@I (work@top.genblk8.i3), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:60:13, endln:60:119 |vpiRhs: \_constant: |vpiDecompile:3 @@ -20848,7 +20848,7 @@ design: (work@top) |vpiProcess: \_initial: , line:32:5, endln:33:54 |vpiParent: - \_interface: work@I (work@top.genblk8.i3), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:60:13, endln:60:119 + \_interface_inst: work@I (work@top.genblk8.i3), file:${SURELOG_DIR}/tests/ClassScope/dut.sv, line:60:13, endln:60:119 |vpiStmt: \_delay_control: , line:32:13, endln:32:19 |vpiParent: diff --git a/tests/ClassTypeParam/ClassTypeParam.log b/tests/ClassTypeParam/ClassTypeParam.log index 9b3ddcbd17..6356e0b3a4 100644 --- a/tests/ClassTypeParam/ClassTypeParam.log +++ b/tests/ClassTypeParam/ClassTypeParam.log @@ -41,7 +41,7 @@ int_typespec 4 io_decl 1 logic_net 3 method_func_call 2 -module 4 +module_inst 4 param_assign 4 ref_obj 3 string_typespec 3 @@ -60,7 +60,7 @@ int_typespec 4 io_decl 2 logic_net 3 method_func_call 2 -module 4 +module_inst 4 param_assign 16 ref_obj 3 string_typespec 3 @@ -284,7 +284,7 @@ design: (work@top) |vpiDerivedClasses: \_class_defn: (work@uvm_config_db), file:${SURELOG_DIR}/tests/ClassTypeParam/dut.sv, line:16:1, endln:17:9 |uhdmallModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/ClassTypeParam/dut.sv, line:22:1, endln:27:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ClassTypeParam/dut.sv, line:22:1, endln:27:10 |vpiParent: \_design: (work@top) |vpiFullName:work@top @@ -292,13 +292,13 @@ design: (work@top) |vpiNet: \_logic_net: (work@top.misc1), line:24:25, endln:24:30 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ClassTypeParam/dut.sv, line:22:1, endln:27:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ClassTypeParam/dut.sv, line:22:1, endln:27:10 |vpiName:misc1 |vpiFullName:work@top.misc1 |vpiNet: \_logic_net: (work@top.misc2), line:26:38, endln:26:43 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ClassTypeParam/dut.sv, line:22:1, endln:27:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ClassTypeParam/dut.sv, line:22:1, endln:27:10 |vpiName:misc2 |vpiFullName:work@top.misc2 |vpiTypedef: @@ -339,12 +339,12 @@ design: (work@top) |vpiClassDefn: \_class_defn: (work@uvm_config_db), file:${SURELOG_DIR}/tests/ClassTypeParam/dut.sv, line:16:1, endln:17:9 |uhdmtopModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/ClassTypeParam/dut.sv, line:22:1, endln:27:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ClassTypeParam/dut.sv, line:22:1, endln:27:10 |vpiName:work@top |vpiVariables: \_class_var: (work@top.misc1), line:24:25, endln:24:36 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ClassTypeParam/dut.sv, line:22:1, endln:27:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ClassTypeParam/dut.sv, line:22:1, endln:27:10 |vpiTypespec: \_class_typespec: (m_uvm_config_obj_misc), line:20:9, endln:20:22 |vpiParent: @@ -407,7 +407,7 @@ design: (work@top) |vpiVariables: \_class_var: (work@top.misc2), line:26:38, endln:26:49 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ClassTypeParam/dut.sv, line:22:1, endln:27:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ClassTypeParam/dut.sv, line:22:1, endln:27:10 |vpiTypespec: \_class_typespec: (uvm_config_db), line:26:3, endln:26:16 |vpiParent: diff --git a/tests/ClockingBlock/ClockingBlock.log b/tests/ClockingBlock/ClockingBlock.log index 01d4d3d301..6cc72d8ba9 100644 --- a/tests/ClockingBlock/ClockingBlock.log +++ b/tests/ClockingBlock/ClockingBlock.log @@ -400,7 +400,7 @@ io_decl 11 logic_net 2 logic_typespec 3 logic_var 1 -module 2 +module_inst 2 operation 3 package 2 port 2 @@ -430,7 +430,7 @@ io_decl 22 logic_net 2 logic_typespec 3 logic_var 1 -module 2 +module_inst 2 operation 6 package 2 port 3 @@ -927,7 +927,7 @@ design: (work@top) \_int_typespec: |vpiSigned:1 |uhdmallModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/ClockingBlock/dut.sv, line:1:1, endln:17:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ClockingBlock/dut.sv, line:1:1, endln:17:10 |vpiParent: \_design: (work@top) |vpiFullName:work@top @@ -935,7 +935,7 @@ design: (work@top) |vpiNet: \_logic_net: (work@top.clk), line:2:8, endln:2:11 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ClockingBlock/dut.sv, line:1:1, endln:17:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ClockingBlock/dut.sv, line:1:1, endln:17:10 |vpiName:clk |vpiFullName:work@top.clk |vpiGlobalClocking: @@ -979,7 +979,7 @@ design: (work@top) |vpiPort: \_port: (clk), line:2:8, endln:2:11 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ClockingBlock/dut.sv, line:1:1, endln:17:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ClockingBlock/dut.sv, line:1:1, endln:17:10 |vpiName:clk |vpiDirection:1 |vpiLowConn: @@ -1037,14 +1037,14 @@ design: (work@top) \_ref_obj: (to), line:14:33, endln:14:35 |vpiName:to |uhdmtopModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/ClockingBlock/dut.sv, line:1:1, endln:17:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ClockingBlock/dut.sv, line:1:1, endln:17:10 |vpiName:work@top |vpiDefName:work@top |vpiTop:1 |vpiNet: \_logic_net: (work@top.clk), line:2:8, endln:2:11 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ClockingBlock/dut.sv, line:1:1, endln:17:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ClockingBlock/dut.sv, line:1:1, endln:17:10 |vpiTypespec: \_logic_typespec: , line:2:8, endln:2:8 |vpiName:clk @@ -1053,7 +1053,7 @@ design: (work@top) |vpiGlobalClocking: \_clocking_block: (work@top.cb), line:9:3, endln:9:49 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ClockingBlock/dut.sv, line:1:1, endln:17:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ClockingBlock/dut.sv, line:1:1, endln:17:10 |vpiName:cb |vpiFullName:work@top.cb |vpiClockingEvent: @@ -1074,11 +1074,11 @@ design: (work@top) |vpiActual: \_logic_net: (work@top.clk), line:2:8, endln:2:11 |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ClockingBlock/dut.sv, line:1:1, endln:17:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ClockingBlock/dut.sv, line:1:1, endln:17:10 |vpiDefaultClocking: \_clocking_block: (work@top.unnamed_clocking_block), line:5:3, endln:7:14 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ClockingBlock/dut.sv, line:1:1, endln:17:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ClockingBlock/dut.sv, line:1:1, endln:17:10 |vpiName:unnamed_clocking_block |vpiFullName:work@top.unnamed_clocking_block |vpiOutputEdge:50 @@ -1105,11 +1105,11 @@ design: (work@top) |vpiActual: \_logic_net: (work@top.clk), line:2:8, endln:2:11 |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ClockingBlock/dut.sv, line:1:1, endln:17:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ClockingBlock/dut.sv, line:1:1, endln:17:10 |vpiPort: \_port: (clk), line:2:8, endln:2:11 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ClockingBlock/dut.sv, line:1:1, endln:17:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ClockingBlock/dut.sv, line:1:1, endln:17:10 |vpiName:clk |vpiDirection:1 |vpiLowConn: @@ -1123,11 +1123,11 @@ design: (work@top) |vpiTypedef: \_logic_typespec: , line:2:8, endln:2:8 |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ClockingBlock/dut.sv, line:1:1, endln:17:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ClockingBlock/dut.sv, line:1:1, endln:17:10 |vpiClockingBlock: \_clocking_block: (work@top.cb1), line:11:3, endln:15:14 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ClockingBlock/dut.sv, line:1:1, endln:17:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ClockingBlock/dut.sv, line:1:1, endln:17:10 |vpiName:cb1 |vpiFullName:work@top.cb1 |vpiInputSkew: @@ -1158,7 +1158,7 @@ design: (work@top) |vpiActual: \_logic_net: (work@top.clk), line:2:8, endln:2:11 |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ClockingBlock/dut.sv, line:1:1, endln:17:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ClockingBlock/dut.sv, line:1:1, endln:17:10 |vpiClockingIODecl: \_clocking_io_decl: (from_Dut), line:13:14, endln:13:22 |vpiParent: @@ -1188,7 +1188,7 @@ design: (work@top) \_hier_path: (top.to), line:14:29, endln:14:35 |vpiName:top |vpiActual: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ClockingBlock/dut.sv, line:1:1, endln:17:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ClockingBlock/dut.sv, line:1:1, endln:17:10 |vpiActual: \_ref_obj: (to), line:14:33, endln:14:35 |vpiParent: diff --git a/tests/ClockingDrive/ClockingDrive.log b/tests/ClockingDrive/ClockingDrive.log index fe394ba08c..f89cdd4744 100644 --- a/tests/ClockingDrive/ClockingDrive.log +++ b/tests/ClockingDrive/ClockingDrive.log @@ -381,7 +381,7 @@ event_control 2 hier_path 16 initial 2 logic_net 7 -module 2 +module_inst 2 operation 1 ref_obj 41 === UHDM Object Stats End === @@ -399,7 +399,7 @@ event_control 4 hier_path 32 initial 4 logic_net 7 -module 2 +module_inst 2 operation 2 ref_obj 82 === UHDM Object Stats End === @@ -440,7 +440,7 @@ design: (work@main) |vpiElaborated:1 |vpiName:work@main |uhdmallModules: -\_module: work@main (work@main), file:${SURELOG_DIR}/tests/ClockingDrive/dut.sv, line:3:1, endln:36:10 +\_module_inst: work@main (work@main), file:${SURELOG_DIR}/tests/ClockingDrive/dut.sv, line:3:1, endln:36:10 |vpiParent: \_design: (work@main) |vpiFullName:work@main @@ -469,7 +469,7 @@ design: (work@main) |vpiProcess: \_initial: , line:9:1, endln:11:4 |vpiParent: - \_module: work@main (work@main), file:${SURELOG_DIR}/tests/ClockingDrive/dut.sv, line:3:1, endln:36:10 + \_module_inst: work@main (work@main), file:${SURELOG_DIR}/tests/ClockingDrive/dut.sv, line:3:1, endln:36:10 |vpiStmt: \_begin: (work@main), line:9:9, endln:11:4 |vpiParent: @@ -509,7 +509,7 @@ design: (work@main) |vpiProcess: \_initial: , line:12:1, endln:35:8 |vpiParent: - \_module: work@main (work@main), file:${SURELOG_DIR}/tests/ClockingDrive/dut.sv, line:3:1, endln:36:10 + \_module_inst: work@main (work@main), file:${SURELOG_DIR}/tests/ClockingDrive/dut.sv, line:3:1, endln:36:10 |vpiStmt: \_begin: (work@main), line:12:9, endln:35:8 |vpiParent: @@ -947,7 +947,7 @@ design: (work@main) \_ref_obj: (nibble) |vpiName:nibble |uhdmtopModules: -\_module: work@main (work@main), file:${SURELOG_DIR}/tests/ClockingDrive/dut.sv, line:3:1, endln:36:10 +\_module_inst: work@main (work@main), file:${SURELOG_DIR}/tests/ClockingDrive/dut.sv, line:3:1, endln:36:10 |vpiName:work@main |vpiDefName:work@main |vpiTop:1 @@ -983,7 +983,7 @@ design: (work@main) |vpiDefaultClocking: \_clocking_block: (work@main.cb), line:6:1, endln:8:12 |vpiParent: - \_module: work@main (work@main), file:${SURELOG_DIR}/tests/ClockingDrive/dut.sv, line:3:1, endln:36:10 + \_module_inst: work@main (work@main), file:${SURELOG_DIR}/tests/ClockingDrive/dut.sv, line:3:1, endln:36:10 |vpiName:cb |vpiFullName:work@main.cb |vpiClockingEvent: @@ -1004,7 +1004,7 @@ design: (work@main) |vpiActual: \_logic_net: (clk) |vpiInstance: - \_module: work@main (work@main), file:${SURELOG_DIR}/tests/ClockingDrive/dut.sv, line:3:1, endln:36:10 + \_module_inst: work@main (work@main), file:${SURELOG_DIR}/tests/ClockingDrive/dut.sv, line:3:1, endln:36:10 |vpiClockingIODecl: \_clocking_io_decl: (v), line:7:8, endln:7:9 |vpiParent: @@ -1014,7 +1014,7 @@ design: (work@main) |vpiProcess: \_initial: , line:9:1, endln:11:4 |vpiParent: - \_module: work@main (work@main), file:${SURELOG_DIR}/tests/ClockingDrive/dut.sv, line:3:1, endln:36:10 + \_module_inst: work@main (work@main), file:${SURELOG_DIR}/tests/ClockingDrive/dut.sv, line:3:1, endln:36:10 |vpiStmt: \_begin: (work@main), line:9:9, endln:11:4 |vpiParent: @@ -1060,7 +1060,7 @@ design: (work@main) |vpiProcess: \_initial: , line:12:1, endln:35:8 |vpiParent: - \_module: work@main (work@main), file:${SURELOG_DIR}/tests/ClockingDrive/dut.sv, line:3:1, endln:36:10 + \_module_inst: work@main (work@main), file:${SURELOG_DIR}/tests/ClockingDrive/dut.sv, line:3:1, endln:36:10 |vpiStmt: \_begin: (work@main), line:12:9, endln:35:8 |vpiParent: diff --git a/tests/ClockingSntx/ClockingSntx.log b/tests/ClockingSntx/ClockingSntx.log index 27b0fc5c6f..cea30a9f2a 100644 --- a/tests/ClockingSntx/ClockingSntx.log +++ b/tests/ClockingSntx/ClockingSntx.log @@ -272,7 +272,7 @@ hier_path 1 initial 1 logic_net 17 logic_typespec 19 -module 3 +module_inst 3 operation 5 part_select 1 port 12 @@ -294,7 +294,7 @@ hier_path 2 initial 2 logic_net 17 logic_typespec 19 -module 3 +module_inst 3 operation 9 part_select 2 port 18 @@ -316,7 +316,7 @@ design: (work@top) |vpiElaborated:1 |vpiName:work@top |uhdmallModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/ClockingSntx/dut.sv, line:1:1, endln:27:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ClockingSntx/dut.sv, line:1:1, endln:27:10 |vpiParent: \_design: (work@top) |vpiFullName:work@top @@ -324,51 +324,51 @@ design: (work@top) |vpiNet: \_logic_net: (work@top.phi1), line:8:9, endln:8:13 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ClockingSntx/dut.sv, line:1:1, endln:27:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ClockingSntx/dut.sv, line:1:1, endln:27:10 |vpiName:phi1 |vpiFullName:work@top.phi1 |vpiNet: \_logic_net: (work@top.data), line:8:28, endln:8:32 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ClockingSntx/dut.sv, line:1:1, endln:27:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ClockingSntx/dut.sv, line:1:1, endln:27:10 |vpiName:data |vpiFullName:work@top.data |vpiNet: \_logic_net: (work@top.write), line:8:47, endln:8:52 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ClockingSntx/dut.sv, line:1:1, endln:27:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ClockingSntx/dut.sv, line:1:1, endln:27:10 |vpiName:write |vpiFullName:work@top.write |vpiNetType:36 |vpiNet: \_logic_net: (work@top.phi2), line:9:9, endln:9:13 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ClockingSntx/dut.sv, line:1:1, endln:27:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ClockingSntx/dut.sv, line:1:1, endln:27:10 |vpiName:phi2 |vpiFullName:work@top.phi2 |vpiNet: \_logic_net: (work@top.cmd), line:9:27, endln:9:30 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ClockingSntx/dut.sv, line:1:1, endln:27:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ClockingSntx/dut.sv, line:1:1, endln:27:10 |vpiName:cmd |vpiFullName:work@top.cmd |vpiNet: \_logic_net: (work@top.enable), line:9:38, endln:9:44 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ClockingSntx/dut.sv, line:1:1, endln:27:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ClockingSntx/dut.sv, line:1:1, endln:27:10 |vpiName:enable |vpiFullName:work@top.enable |vpiNet: \_logic_net: (work@top.cmd_reg), line:11:12, endln:11:19 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ClockingSntx/dut.sv, line:1:1, endln:27:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ClockingSntx/dut.sv, line:1:1, endln:27:10 |vpiName:cmd_reg |vpiFullName:work@top.cmd_reg |vpiNetType:48 |vpiPort: \_port: (phi1), line:8:9, endln:8:13 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ClockingSntx/dut.sv, line:1:1, endln:27:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ClockingSntx/dut.sv, line:1:1, endln:27:10 |vpiName:phi1 |vpiDirection:1 |vpiLowConn: @@ -380,7 +380,7 @@ design: (work@top) |vpiPort: \_port: (data), line:8:28, endln:8:32 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ClockingSntx/dut.sv, line:1:1, endln:27:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ClockingSntx/dut.sv, line:1:1, endln:27:10 |vpiName:data |vpiDirection:1 |vpiLowConn: @@ -410,7 +410,7 @@ design: (work@top) |vpiPort: \_port: (write), line:8:47, endln:8:52 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ClockingSntx/dut.sv, line:1:1, endln:27:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ClockingSntx/dut.sv, line:1:1, endln:27:10 |vpiName:write |vpiDirection:2 |vpiLowConn: @@ -422,7 +422,7 @@ design: (work@top) |vpiPort: \_port: (phi2), line:9:9, endln:9:13 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ClockingSntx/dut.sv, line:1:1, endln:27:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ClockingSntx/dut.sv, line:1:1, endln:27:10 |vpiName:phi2 |vpiDirection:1 |vpiLowConn: @@ -434,7 +434,7 @@ design: (work@top) |vpiPort: \_port: (cmd), line:9:27, endln:9:30 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ClockingSntx/dut.sv, line:1:1, endln:27:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ClockingSntx/dut.sv, line:1:1, endln:27:10 |vpiName:cmd |vpiDirection:3 |vpiLowConn: @@ -464,7 +464,7 @@ design: (work@top) |vpiPort: \_port: (enable), line:9:38, endln:9:44 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ClockingSntx/dut.sv, line:1:1, endln:27:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ClockingSntx/dut.sv, line:1:1, endln:27:10 |vpiName:enable |vpiDirection:1 |vpiLowConn: @@ -476,7 +476,7 @@ design: (work@top) |vpiProcess: \_initial: , line:22:2, endln:23:5 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ClockingSntx/dut.sv, line:1:1, endln:27:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ClockingSntx/dut.sv, line:1:1, endln:27:10 |vpiStmt: \_begin: (work@top), line:22:10, endln:23:5 |vpiParent: @@ -485,7 +485,7 @@ design: (work@top) |vpiContAssign: \_cont_assign: , line:25:9, endln:25:35 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ClockingSntx/dut.sv, line:1:1, endln:27:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ClockingSntx/dut.sv, line:1:1, endln:27:10 |vpiRhs: \_operation: , line:25:15, endln:25:35 |vpiParent: @@ -656,14 +656,14 @@ design: (work@top) |vpiDirection:1 |vpiName:enable |uhdmtopModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/ClockingSntx/dut.sv, line:1:1, endln:27:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ClockingSntx/dut.sv, line:1:1, endln:27:10 |vpiName:work@top |vpiDefName:work@top |vpiTop:1 |vpiNet: \_logic_net: (work@top.phi1), line:8:9, endln:8:13 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ClockingSntx/dut.sv, line:1:1, endln:27:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ClockingSntx/dut.sv, line:1:1, endln:27:10 |vpiTypespec: \_logic_typespec: , line:8:9, endln:8:9 |vpiName:phi1 @@ -671,7 +671,7 @@ design: (work@top) |vpiNet: \_logic_net: (work@top.data), line:8:28, endln:8:32 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ClockingSntx/dut.sv, line:1:1, endln:27:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ClockingSntx/dut.sv, line:1:1, endln:27:10 |vpiTypespec: \_logic_typespec: , line:8:21, endln:8:27 |vpiRange: @@ -697,7 +697,7 @@ design: (work@top) |vpiNet: \_logic_net: (work@top.write), line:8:47, endln:8:52 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ClockingSntx/dut.sv, line:1:1, endln:27:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ClockingSntx/dut.sv, line:1:1, endln:27:10 |vpiTypespec: \_logic_typespec: , line:8:41, endln:8:46 |vpiName:write @@ -706,7 +706,7 @@ design: (work@top) |vpiNet: \_logic_net: (work@top.phi2), line:9:9, endln:9:13 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ClockingSntx/dut.sv, line:1:1, endln:27:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ClockingSntx/dut.sv, line:1:1, endln:27:10 |vpiTypespec: \_logic_typespec: , line:9:9, endln:9:9 |vpiName:phi2 @@ -714,7 +714,7 @@ design: (work@top) |vpiNet: \_logic_net: (work@top.cmd), line:9:27, endln:9:30 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ClockingSntx/dut.sv, line:1:1, endln:27:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ClockingSntx/dut.sv, line:1:1, endln:27:10 |vpiTypespec: \_logic_typespec: , line:9:21, endln:9:26 |vpiRange: @@ -740,7 +740,7 @@ design: (work@top) |vpiNet: \_logic_net: (work@top.enable), line:9:38, endln:9:44 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ClockingSntx/dut.sv, line:1:1, endln:27:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ClockingSntx/dut.sv, line:1:1, endln:27:10 |vpiTypespec: \_logic_typespec: , line:9:38, endln:9:38 |vpiName:enable @@ -748,7 +748,7 @@ design: (work@top) |vpiNet: \_logic_net: (work@top.cmd_reg), line:11:12, endln:11:19 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ClockingSntx/dut.sv, line:1:1, endln:27:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ClockingSntx/dut.sv, line:1:1, endln:27:10 |vpiTypespec: \_logic_typespec: , line:11:2, endln:11:11 |vpiRange: @@ -788,7 +788,7 @@ design: (work@top) |vpiPort: \_port: (phi1), line:8:9, endln:8:13 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ClockingSntx/dut.sv, line:1:1, endln:27:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ClockingSntx/dut.sv, line:1:1, endln:27:10 |vpiName:phi1 |vpiDirection:1 |vpiLowConn: @@ -802,11 +802,11 @@ design: (work@top) |vpiTypedef: \_logic_typespec: , line:8:9, endln:8:9 |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ClockingSntx/dut.sv, line:1:1, endln:27:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ClockingSntx/dut.sv, line:1:1, endln:27:10 |vpiPort: \_port: (data), line:8:28, endln:8:32 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ClockingSntx/dut.sv, line:1:1, endln:27:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ClockingSntx/dut.sv, line:1:1, endln:27:10 |vpiName:data |vpiDirection:1 |vpiLowConn: @@ -840,11 +840,11 @@ design: (work@top) |UINT:0 |vpiConstType:9 |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ClockingSntx/dut.sv, line:1:1, endln:27:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ClockingSntx/dut.sv, line:1:1, endln:27:10 |vpiPort: \_port: (write), line:8:47, endln:8:52 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ClockingSntx/dut.sv, line:1:1, endln:27:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ClockingSntx/dut.sv, line:1:1, endln:27:10 |vpiName:write |vpiDirection:2 |vpiLowConn: @@ -858,11 +858,11 @@ design: (work@top) |vpiTypedef: \_logic_typespec: , line:8:41, endln:8:46 |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ClockingSntx/dut.sv, line:1:1, endln:27:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ClockingSntx/dut.sv, line:1:1, endln:27:10 |vpiPort: \_port: (phi2), line:9:9, endln:9:13 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ClockingSntx/dut.sv, line:1:1, endln:27:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ClockingSntx/dut.sv, line:1:1, endln:27:10 |vpiName:phi2 |vpiDirection:1 |vpiLowConn: @@ -876,11 +876,11 @@ design: (work@top) |vpiTypedef: \_logic_typespec: , line:9:9, endln:9:9 |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ClockingSntx/dut.sv, line:1:1, endln:27:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ClockingSntx/dut.sv, line:1:1, endln:27:10 |vpiPort: \_port: (cmd), line:9:27, endln:9:30 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ClockingSntx/dut.sv, line:1:1, endln:27:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ClockingSntx/dut.sv, line:1:1, endln:27:10 |vpiName:cmd |vpiDirection:3 |vpiLowConn: @@ -914,11 +914,11 @@ design: (work@top) |UINT:1 |vpiConstType:9 |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ClockingSntx/dut.sv, line:1:1, endln:27:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ClockingSntx/dut.sv, line:1:1, endln:27:10 |vpiPort: \_port: (enable), line:9:38, endln:9:44 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ClockingSntx/dut.sv, line:1:1, endln:27:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ClockingSntx/dut.sv, line:1:1, endln:27:10 |vpiName:enable |vpiDirection:1 |vpiLowConn: @@ -932,11 +932,11 @@ design: (work@top) |vpiTypedef: \_logic_typespec: , line:9:38, endln:9:38 |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ClockingSntx/dut.sv, line:1:1, endln:27:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ClockingSntx/dut.sv, line:1:1, endln:27:10 |vpiProcess: \_initial: , line:22:2, endln:23:5 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ClockingSntx/dut.sv, line:1:1, endln:27:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ClockingSntx/dut.sv, line:1:1, endln:27:10 |vpiStmt: \_begin: (work@top), line:22:10, endln:23:5 |vpiParent: @@ -945,7 +945,7 @@ design: (work@top) |vpiContAssign: \_cont_assign: , line:25:9, endln:25:35 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ClockingSntx/dut.sv, line:1:1, endln:27:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ClockingSntx/dut.sv, line:1:1, endln:27:10 |vpiRhs: \_operation: , line:25:15, endln:25:35 |vpiParent: @@ -984,7 +984,7 @@ design: (work@top) |vpiClockingBlock: \_clocking_block: (work@top.mem), line:2:2, endln:4:13 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ClockingSntx/dut.sv, line:1:1, endln:27:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ClockingSntx/dut.sv, line:1:1, endln:27:10 |vpiName:mem |vpiFullName:work@top.mem |vpiClockingEvent: @@ -1000,7 +1000,7 @@ design: (work@top) |vpiActual: \_logic_net: (clock) |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ClockingSntx/dut.sv, line:1:1, endln:27:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ClockingSntx/dut.sv, line:1:1, endln:27:10 |vpiClockingIODecl: \_clocking_io_decl: (instruction), line:3:8, endln:3:49 |vpiParent: @@ -1045,7 +1045,7 @@ design: (work@top) |vpiClockingBlock: \_clocking_block: (work@top.cd1), line:12:2, endln:16:13 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ClockingSntx/dut.sv, line:1:1, endln:27:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ClockingSntx/dut.sv, line:1:1, endln:27:10 |vpiName:cd1 |vpiFullName:work@top.cd1 |vpiClockingEvent: @@ -1066,7 +1066,7 @@ design: (work@top) |vpiActual: \_logic_net: (work@top.phi1), line:8:9, endln:8:13 |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ClockingSntx/dut.sv, line:1:1, endln:27:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ClockingSntx/dut.sv, line:1:1, endln:27:10 |vpiClockingIODecl: \_clocking_io_decl: (data), line:13:9, endln:13:13 |vpiParent: @@ -1096,7 +1096,7 @@ design: (work@top) \_hier_path: (top.cpu1.state), line:15:17, endln:15:31 |vpiName:top |vpiActual: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ClockingSntx/dut.sv, line:1:1, endln:27:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ClockingSntx/dut.sv, line:1:1, endln:27:10 |vpiActual: \_ref_obj: (cpu1), line:15:21, endln:15:25 |vpiParent: @@ -1110,7 +1110,7 @@ design: (work@top) |vpiClockingBlock: \_clocking_block: (work@top.cd2), line:18:2, endln:21:13 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ClockingSntx/dut.sv, line:1:1, endln:27:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ClockingSntx/dut.sv, line:1:1, endln:27:10 |vpiName:cd2 |vpiFullName:work@top.cd2 |vpiClockingEvent: @@ -1131,7 +1131,7 @@ design: (work@top) |vpiActual: \_logic_net: (work@top.phi2), line:9:9, endln:9:13 |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ClockingSntx/dut.sv, line:1:1, endln:27:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ClockingSntx/dut.sv, line:1:1, endln:27:10 |vpiClockingIODecl: \_clocking_io_decl: (cmd), line:19:24, endln:19:27 |vpiParent: diff --git a/tests/ClogCast/ClogCast.log b/tests/ClogCast/ClogCast.log index 74ebbb4f99..c3eb3496e3 100644 --- a/tests/ClogCast/ClogCast.log +++ b/tests/ClogCast/ClogCast.log @@ -694,7 +694,7 @@ io_decl 11 logic_net 10 logic_typespec 14 logic_var 3 -module 5 +module_inst 5 named_begin 1 operation 10 package 2 @@ -732,7 +732,7 @@ io_decl 22 logic_net 10 logic_typespec 14 logic_var 3 -module 5 +module_inst 5 named_begin 2 operation 15 package 2 @@ -1233,14 +1233,14 @@ design: (work@debug_rom) \_int_typespec: |vpiSigned:1 |uhdmallModules: -\_module: work@debug_rom (work@debug_rom), file:${SURELOG_DIR}/tests/ClogCast/dut.sv, line:3:2, endln:51:11 +\_module_inst: work@debug_rom (work@debug_rom), file:${SURELOG_DIR}/tests/ClogCast/dut.sv, line:3:2, endln:51:11 |vpiParent: \_design: (work@debug_rom) |vpiFullName:work@debug_rom |vpiParameter: \_parameter: (work@debug_rom.RomSize), line:10:28, endln:10:35 |vpiParent: - \_module: work@debug_rom (work@debug_rom), file:${SURELOG_DIR}/tests/ClogCast/dut.sv, line:3:2, endln:51:11 + \_module_inst: work@debug_rom (work@debug_rom), file:${SURELOG_DIR}/tests/ClogCast/dut.sv, line:3:2, endln:51:11 |UINT:19 |vpiTypespec: \_int_typespec: , line:10:15, endln:10:27 @@ -1252,7 +1252,7 @@ design: (work@debug_rom) |vpiParamAssign: \_param_assign: , line:10:28, endln:10:40 |vpiParent: - \_module: work@debug_rom (work@debug_rom), file:${SURELOG_DIR}/tests/ClogCast/dut.sv, line:3:2, endln:51:11 + \_module_inst: work@debug_rom (work@debug_rom), file:${SURELOG_DIR}/tests/ClogCast/dut.sv, line:3:2, endln:51:11 |vpiRhs: \_constant: , line:10:38, endln:10:40 |vpiDecompile:19 @@ -1267,49 +1267,49 @@ design: (work@debug_rom) |vpiNet: \_logic_net: (work@debug_rom.clk_i), line:4:25, endln:4:30 |vpiParent: - \_module: work@debug_rom (work@debug_rom), file:${SURELOG_DIR}/tests/ClogCast/dut.sv, line:3:2, endln:51:11 + \_module_inst: work@debug_rom (work@debug_rom), file:${SURELOG_DIR}/tests/ClogCast/dut.sv, line:3:2, endln:51:11 |vpiName:clk_i |vpiFullName:work@debug_rom.clk_i |vpiNetType:36 |vpiNet: \_logic_net: (work@debug_rom.req_i), line:5:25, endln:5:30 |vpiParent: - \_module: work@debug_rom (work@debug_rom), file:${SURELOG_DIR}/tests/ClogCast/dut.sv, line:3:2, endln:51:11 + \_module_inst: work@debug_rom (work@debug_rom), file:${SURELOG_DIR}/tests/ClogCast/dut.sv, line:3:2, endln:51:11 |vpiName:req_i |vpiFullName:work@debug_rom.req_i |vpiNetType:36 |vpiNet: \_logic_net: (work@debug_rom.addr_i), line:6:25, endln:6:31 |vpiParent: - \_module: work@debug_rom (work@debug_rom), file:${SURELOG_DIR}/tests/ClogCast/dut.sv, line:3:2, endln:51:11 + \_module_inst: work@debug_rom (work@debug_rom), file:${SURELOG_DIR}/tests/ClogCast/dut.sv, line:3:2, endln:51:11 |vpiName:addr_i |vpiFullName:work@debug_rom.addr_i |vpiNetType:36 |vpiNet: \_logic_net: (work@debug_rom.rdata_o), line:7:25, endln:7:32 |vpiParent: - \_module: work@debug_rom (work@debug_rom), file:${SURELOG_DIR}/tests/ClogCast/dut.sv, line:3:2, endln:51:11 + \_module_inst: work@debug_rom (work@debug_rom), file:${SURELOG_DIR}/tests/ClogCast/dut.sv, line:3:2, endln:51:11 |vpiName:rdata_o |vpiFullName:work@debug_rom.rdata_o |vpiNetType:36 |vpiNet: \_logic_net: (work@debug_rom.mem), line:12:36, endln:12:39 |vpiParent: - \_module: work@debug_rom (work@debug_rom), file:${SURELOG_DIR}/tests/ClogCast/dut.sv, line:3:2, endln:51:11 + \_module_inst: work@debug_rom (work@debug_rom), file:${SURELOG_DIR}/tests/ClogCast/dut.sv, line:3:2, endln:51:11 |vpiName:mem |vpiFullName:work@debug_rom.mem |vpiNetType:36 |vpiNet: \_logic_net: (work@debug_rom.addr_q), line:34:32, endln:34:38 |vpiParent: - \_module: work@debug_rom (work@debug_rom), file:${SURELOG_DIR}/tests/ClogCast/dut.sv, line:3:2, endln:51:11 + \_module_inst: work@debug_rom (work@debug_rom), file:${SURELOG_DIR}/tests/ClogCast/dut.sv, line:3:2, endln:51:11 |vpiName:addr_q |vpiFullName:work@debug_rom.addr_q |vpiNetType:36 |vpiPort: \_port: (clk_i), line:4:25, endln:4:30 |vpiParent: - \_module: work@debug_rom (work@debug_rom), file:${SURELOG_DIR}/tests/ClogCast/dut.sv, line:3:2, endln:51:11 + \_module_inst: work@debug_rom (work@debug_rom), file:${SURELOG_DIR}/tests/ClogCast/dut.sv, line:3:2, endln:51:11 |vpiName:clk_i |vpiDirection:1 |vpiLowConn: @@ -1321,7 +1321,7 @@ design: (work@debug_rom) |vpiPort: \_port: (req_i), line:5:25, endln:5:30 |vpiParent: - \_module: work@debug_rom (work@debug_rom), file:${SURELOG_DIR}/tests/ClogCast/dut.sv, line:3:2, endln:51:11 + \_module_inst: work@debug_rom (work@debug_rom), file:${SURELOG_DIR}/tests/ClogCast/dut.sv, line:3:2, endln:51:11 |vpiName:req_i |vpiDirection:1 |vpiLowConn: @@ -1333,7 +1333,7 @@ design: (work@debug_rom) |vpiPort: \_port: (addr_i), line:6:25, endln:6:31 |vpiParent: - \_module: work@debug_rom (work@debug_rom), file:${SURELOG_DIR}/tests/ClogCast/dut.sv, line:3:2, endln:51:11 + \_module_inst: work@debug_rom (work@debug_rom), file:${SURELOG_DIR}/tests/ClogCast/dut.sv, line:3:2, endln:51:11 |vpiName:addr_i |vpiDirection:1 |vpiLowConn: @@ -1363,7 +1363,7 @@ design: (work@debug_rom) |vpiPort: \_port: (rdata_o), line:7:25, endln:7:32 |vpiParent: - \_module: work@debug_rom (work@debug_rom), file:${SURELOG_DIR}/tests/ClogCast/dut.sv, line:3:2, endln:51:11 + \_module_inst: work@debug_rom (work@debug_rom), file:${SURELOG_DIR}/tests/ClogCast/dut.sv, line:3:2, endln:51:11 |vpiName:rdata_o |vpiDirection:2 |vpiLowConn: @@ -1393,7 +1393,7 @@ design: (work@debug_rom) |vpiProcess: \_always: , line:36:4, endln:40:7 |vpiParent: - \_module: work@debug_rom (work@debug_rom), file:${SURELOG_DIR}/tests/ClogCast/dut.sv, line:3:2, endln:51:11 + \_module_inst: work@debug_rom (work@debug_rom), file:${SURELOG_DIR}/tests/ClogCast/dut.sv, line:3:2, endln:51:11 |vpiStmt: \_event_control: , line:36:14, endln:36:30 |vpiParent: @@ -1503,7 +1503,7 @@ design: (work@debug_rom) |vpiProcess: \_always: , line:44:4, endln:49:7 |vpiParent: - \_module: work@debug_rom (work@debug_rom), file:${SURELOG_DIR}/tests/ClogCast/dut.sv, line:3:2, endln:51:11 + \_module_inst: work@debug_rom (work@debug_rom), file:${SURELOG_DIR}/tests/ClogCast/dut.sv, line:3:2, endln:51:11 |vpiStmt: \_named_begin: (work@debug_rom.p_outmux), line:44:16, endln:49:7 |vpiParent: @@ -1611,12 +1611,12 @@ design: (work@debug_rom) \_logic_net: (work@debug_rom.rdata_o), line:7:25, endln:7:32 |vpiAlwaysType:2 |uhdmtopModules: -\_module: work@debug_rom (work@debug_rom), file:${SURELOG_DIR}/tests/ClogCast/dut.sv, line:3:2, endln:51:11 +\_module_inst: work@debug_rom (work@debug_rom), file:${SURELOG_DIR}/tests/ClogCast/dut.sv, line:3:2, endln:51:11 |vpiName:work@debug_rom |vpiVariables: \_logic_var: (work@debug_rom.mem), line:12:36, endln:32:5 |vpiParent: - \_module: work@debug_rom (work@debug_rom), file:${SURELOG_DIR}/tests/ClogCast/dut.sv, line:3:2, endln:51:11 + \_module_inst: work@debug_rom (work@debug_rom), file:${SURELOG_DIR}/tests/ClogCast/dut.sv, line:3:2, endln:51:11 |vpiTypespec: \_logic_typespec: , line:12:10, endln:12:35 |vpiRange: @@ -1853,7 +1853,7 @@ design: (work@debug_rom) |vpiVariables: \_logic_var: (work@debug_rom.addr_q), line:34:32, endln:34:38 |vpiParent: - \_module: work@debug_rom (work@debug_rom), file:${SURELOG_DIR}/tests/ClogCast/dut.sv, line:3:2, endln:51:11 + \_module_inst: work@debug_rom (work@debug_rom), file:${SURELOG_DIR}/tests/ClogCast/dut.sv, line:3:2, endln:51:11 |vpiTypespec: \_logic_typespec: , line:34:4, endln:34:31 |vpiRange: @@ -1898,7 +1898,7 @@ design: (work@debug_rom) |vpiParameter: \_parameter: (work@debug_rom.RomSize), line:10:28, endln:10:35 |vpiParent: - \_module: work@debug_rom (work@debug_rom), file:${SURELOG_DIR}/tests/ClogCast/dut.sv, line:3:2, endln:51:11 + \_module_inst: work@debug_rom (work@debug_rom), file:${SURELOG_DIR}/tests/ClogCast/dut.sv, line:3:2, endln:51:11 |UINT:19 |vpiTypespec: \_int_typespec: , line:10:15, endln:10:27 @@ -1910,7 +1910,7 @@ design: (work@debug_rom) |vpiParamAssign: \_param_assign: , line:10:28, endln:10:40 |vpiParent: - \_module: work@debug_rom (work@debug_rom), file:${SURELOG_DIR}/tests/ClogCast/dut.sv, line:3:2, endln:51:11 + \_module_inst: work@debug_rom (work@debug_rom), file:${SURELOG_DIR}/tests/ClogCast/dut.sv, line:3:2, endln:51:11 |vpiRhs: \_constant: , line:10:38, endln:10:40 |vpiDecompile:19 @@ -1926,7 +1926,7 @@ design: (work@debug_rom) |vpiNet: \_logic_net: (work@debug_rom.clk_i), line:4:25, endln:4:30 |vpiParent: - \_module: work@debug_rom (work@debug_rom), file:${SURELOG_DIR}/tests/ClogCast/dut.sv, line:3:2, endln:51:11 + \_module_inst: work@debug_rom (work@debug_rom), file:${SURELOG_DIR}/tests/ClogCast/dut.sv, line:3:2, endln:51:11 |vpiTypespec: \_logic_typespec: , line:4:11, endln:4:16 |vpiName:clk_i @@ -1935,7 +1935,7 @@ design: (work@debug_rom) |vpiNet: \_logic_net: (work@debug_rom.req_i), line:5:25, endln:5:30 |vpiParent: - \_module: work@debug_rom (work@debug_rom), file:${SURELOG_DIR}/tests/ClogCast/dut.sv, line:3:2, endln:51:11 + \_module_inst: work@debug_rom (work@debug_rom), file:${SURELOG_DIR}/tests/ClogCast/dut.sv, line:3:2, endln:51:11 |vpiTypespec: \_logic_typespec: , line:5:11, endln:5:16 |vpiName:req_i @@ -1944,7 +1944,7 @@ design: (work@debug_rom) |vpiNet: \_logic_net: (work@debug_rom.addr_i), line:6:25, endln:6:31 |vpiParent: - \_module: work@debug_rom (work@debug_rom), file:${SURELOG_DIR}/tests/ClogCast/dut.sv, line:3:2, endln:51:11 + \_module_inst: work@debug_rom (work@debug_rom), file:${SURELOG_DIR}/tests/ClogCast/dut.sv, line:3:2, endln:51:11 |vpiTypespec: \_logic_typespec: , line:6:11, endln:6:23 |vpiRange: @@ -1971,7 +1971,7 @@ design: (work@debug_rom) |vpiNet: \_logic_net: (work@debug_rom.rdata_o), line:7:25, endln:7:32 |vpiParent: - \_module: work@debug_rom (work@debug_rom), file:${SURELOG_DIR}/tests/ClogCast/dut.sv, line:3:2, endln:51:11 + \_module_inst: work@debug_rom (work@debug_rom), file:${SURELOG_DIR}/tests/ClogCast/dut.sv, line:3:2, endln:51:11 |vpiTypespec: \_logic_typespec: , line:7:11, endln:7:23 |vpiRange: @@ -1999,7 +1999,7 @@ design: (work@debug_rom) |vpiPort: \_port: (clk_i), line:4:25, endln:4:30 |vpiParent: - \_module: work@debug_rom (work@debug_rom), file:${SURELOG_DIR}/tests/ClogCast/dut.sv, line:3:2, endln:51:11 + \_module_inst: work@debug_rom (work@debug_rom), file:${SURELOG_DIR}/tests/ClogCast/dut.sv, line:3:2, endln:51:11 |vpiName:clk_i |vpiDirection:1 |vpiLowConn: @@ -2013,11 +2013,11 @@ design: (work@debug_rom) |vpiTypedef: \_logic_typespec: , line:4:11, endln:4:16 |vpiInstance: - \_module: work@debug_rom (work@debug_rom), file:${SURELOG_DIR}/tests/ClogCast/dut.sv, line:3:2, endln:51:11 + \_module_inst: work@debug_rom (work@debug_rom), file:${SURELOG_DIR}/tests/ClogCast/dut.sv, line:3:2, endln:51:11 |vpiPort: \_port: (req_i), line:5:25, endln:5:30 |vpiParent: - \_module: work@debug_rom (work@debug_rom), file:${SURELOG_DIR}/tests/ClogCast/dut.sv, line:3:2, endln:51:11 + \_module_inst: work@debug_rom (work@debug_rom), file:${SURELOG_DIR}/tests/ClogCast/dut.sv, line:3:2, endln:51:11 |vpiName:req_i |vpiDirection:1 |vpiLowConn: @@ -2031,11 +2031,11 @@ design: (work@debug_rom) |vpiTypedef: \_logic_typespec: , line:5:11, endln:5:16 |vpiInstance: - \_module: work@debug_rom (work@debug_rom), file:${SURELOG_DIR}/tests/ClogCast/dut.sv, line:3:2, endln:51:11 + \_module_inst: work@debug_rom (work@debug_rom), file:${SURELOG_DIR}/tests/ClogCast/dut.sv, line:3:2, endln:51:11 |vpiPort: \_port: (addr_i), line:6:25, endln:6:31 |vpiParent: - \_module: work@debug_rom (work@debug_rom), file:${SURELOG_DIR}/tests/ClogCast/dut.sv, line:3:2, endln:51:11 + \_module_inst: work@debug_rom (work@debug_rom), file:${SURELOG_DIR}/tests/ClogCast/dut.sv, line:3:2, endln:51:11 |vpiName:addr_i |vpiDirection:1 |vpiLowConn: @@ -2069,11 +2069,11 @@ design: (work@debug_rom) |UINT:0 |vpiConstType:9 |vpiInstance: - \_module: work@debug_rom (work@debug_rom), file:${SURELOG_DIR}/tests/ClogCast/dut.sv, line:3:2, endln:51:11 + \_module_inst: work@debug_rom (work@debug_rom), file:${SURELOG_DIR}/tests/ClogCast/dut.sv, line:3:2, endln:51:11 |vpiPort: \_port: (rdata_o), line:7:25, endln:7:32 |vpiParent: - \_module: work@debug_rom (work@debug_rom), file:${SURELOG_DIR}/tests/ClogCast/dut.sv, line:3:2, endln:51:11 + \_module_inst: work@debug_rom (work@debug_rom), file:${SURELOG_DIR}/tests/ClogCast/dut.sv, line:3:2, endln:51:11 |vpiName:rdata_o |vpiDirection:2 |vpiLowConn: @@ -2107,11 +2107,11 @@ design: (work@debug_rom) |UINT:0 |vpiConstType:9 |vpiInstance: - \_module: work@debug_rom (work@debug_rom), file:${SURELOG_DIR}/tests/ClogCast/dut.sv, line:3:2, endln:51:11 + \_module_inst: work@debug_rom (work@debug_rom), file:${SURELOG_DIR}/tests/ClogCast/dut.sv, line:3:2, endln:51:11 |vpiProcess: \_always: , line:36:4, endln:40:7 |vpiParent: - \_module: work@debug_rom (work@debug_rom), file:${SURELOG_DIR}/tests/ClogCast/dut.sv, line:3:2, endln:51:11 + \_module_inst: work@debug_rom (work@debug_rom), file:${SURELOG_DIR}/tests/ClogCast/dut.sv, line:3:2, endln:51:11 |vpiStmt: \_event_control: , line:36:14, endln:36:30 |vpiParent: @@ -2209,7 +2209,7 @@ design: (work@debug_rom) |vpiProcess: \_always: , line:44:4, endln:49:7 |vpiParent: - \_module: work@debug_rom (work@debug_rom), file:${SURELOG_DIR}/tests/ClogCast/dut.sv, line:3:2, endln:51:11 + \_module_inst: work@debug_rom (work@debug_rom), file:${SURELOG_DIR}/tests/ClogCast/dut.sv, line:3:2, endln:51:11 |vpiStmt: \_named_begin: (work@debug_rom.p_outmux), line:44:16, endln:49:7 |vpiParent: diff --git a/tests/ClogParam/ClogParam.log b/tests/ClogParam/ClogParam.log index 348d45f234..62e319f795 100644 --- a/tests/ClogParam/ClogParam.log +++ b/tests/ClogParam/ClogParam.log @@ -215,7 +215,7 @@ hier_path 6 int_typespec 38 int_var 2 logic_net 2 -module 9 +module_inst 9 operation 24 param_assign 8 parameter 8 @@ -235,7 +235,7 @@ hier_path 6 int_typespec 38 int_var 2 logic_net 2 -module 9 +module_inst 9 operation 24 param_assign 8 parameter 8 @@ -258,14 +258,14 @@ design: (work@top) |vpiElaborated:1 |vpiName:work@top |uhdmallModules: -\_module: work@otp_ctrl_ecc_reg (work@otp_ctrl_ecc_reg), file:${SURELOG_DIR}/tests/ClogParam/dut.sv, line:1:1, endln:5:29 +\_module_inst: work@otp_ctrl_ecc_reg (work@otp_ctrl_ecc_reg), file:${SURELOG_DIR}/tests/ClogParam/dut.sv, line:1:1, endln:5:29 |vpiParent: \_design: (work@top) |vpiFullName:work@otp_ctrl_ecc_reg |vpiParameter: \_parameter: (work@otp_ctrl_ecc_reg.Depth), line:2:19, endln:2:24 |vpiParent: - \_module: work@otp_ctrl_ecc_reg (work@otp_ctrl_ecc_reg), file:${SURELOG_DIR}/tests/ClogParam/dut.sv, line:1:1, endln:5:29 + \_module_inst: work@otp_ctrl_ecc_reg (work@otp_ctrl_ecc_reg), file:${SURELOG_DIR}/tests/ClogParam/dut.sv, line:1:1, endln:5:29 |UINT:999 |vpiTypespec: \_int_typespec: , line:2:15, endln:2:18 @@ -278,7 +278,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@otp_ctrl_ecc_reg.Aw), line:3:19, endln:3:21 |vpiParent: - \_module: work@otp_ctrl_ecc_reg (work@otp_ctrl_ecc_reg), file:${SURELOG_DIR}/tests/ClogParam/dut.sv, line:1:1, endln:5:29 + \_module_inst: work@otp_ctrl_ecc_reg (work@otp_ctrl_ecc_reg), file:${SURELOG_DIR}/tests/ClogParam/dut.sv, line:1:1, endln:5:29 |vpiTypespec: \_int_typespec: , line:3:15, endln:3:18 |vpiParent: @@ -291,7 +291,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:2:19, endln:2:30 |vpiParent: - \_module: work@otp_ctrl_ecc_reg (work@otp_ctrl_ecc_reg), file:${SURELOG_DIR}/tests/ClogParam/dut.sv, line:1:1, endln:5:29 + \_module_inst: work@otp_ctrl_ecc_reg (work@otp_ctrl_ecc_reg), file:${SURELOG_DIR}/tests/ClogParam/dut.sv, line:1:1, endln:5:29 |vpiRhs: \_constant: , line:2:27, endln:2:30 |vpiDecompile:999 @@ -305,7 +305,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:3:19, endln:3:37 |vpiParent: - \_module: work@otp_ctrl_ecc_reg (work@otp_ctrl_ecc_reg), file:${SURELOG_DIR}/tests/ClogParam/dut.sv, line:1:1, endln:5:29 + \_module_inst: work@otp_ctrl_ecc_reg (work@otp_ctrl_ecc_reg), file:${SURELOG_DIR}/tests/ClogParam/dut.sv, line:1:1, endln:5:29 |vpiRhs: \_sys_func_call: ($clog2), line:3:24, endln:3:37 |vpiArgument: @@ -320,13 +320,13 @@ design: (work@top) |vpiNet: \_logic_net: (work@otp_ctrl_ecc_reg.a), line:1:36, endln:1:37 |vpiParent: - \_module: work@otp_ctrl_ecc_reg (work@otp_ctrl_ecc_reg), file:${SURELOG_DIR}/tests/ClogParam/dut.sv, line:1:1, endln:5:29 + \_module_inst: work@otp_ctrl_ecc_reg (work@otp_ctrl_ecc_reg), file:${SURELOG_DIR}/tests/ClogParam/dut.sv, line:1:1, endln:5:29 |vpiName:a |vpiFullName:work@otp_ctrl_ecc_reg.a |vpiPort: \_port: (a), line:1:36, endln:1:37 |vpiParent: - \_module: work@otp_ctrl_ecc_reg (work@otp_ctrl_ecc_reg), file:${SURELOG_DIR}/tests/ClogParam/dut.sv, line:1:1, endln:5:29 + \_module_inst: work@otp_ctrl_ecc_reg (work@otp_ctrl_ecc_reg), file:${SURELOG_DIR}/tests/ClogParam/dut.sv, line:1:1, endln:5:29 |vpiName:a |vpiDirection:2 |vpiLowConn: @@ -339,7 +339,7 @@ design: (work@top) |vpiContAssign: \_cont_assign: , line:4:11, endln:4:17 |vpiParent: - \_module: work@otp_ctrl_ecc_reg (work@otp_ctrl_ecc_reg), file:${SURELOG_DIR}/tests/ClogParam/dut.sv, line:1:1, endln:5:29 + \_module_inst: work@otp_ctrl_ecc_reg (work@otp_ctrl_ecc_reg), file:${SURELOG_DIR}/tests/ClogParam/dut.sv, line:1:1, endln:5:29 |vpiRhs: \_ref_obj: (work@otp_ctrl_ecc_reg.Aw), line:4:15, endln:4:17 |vpiParent: @@ -355,21 +355,21 @@ design: (work@top) |vpiActual: \_int_var: (work@top.u_otp_ctrl_ecc_reg.a), line:1:36, endln:1:37 |uhdmallModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/ClogParam/dut.sv, line:7:1, endln:19:16 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ClogParam/dut.sv, line:7:1, endln:19:16 |vpiParent: \_design: (work@top) |vpiFullName:work@top |vpiParameter: \_parameter: (work@top.Info), line:12:26, endln:12:30 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ClogParam/dut.sv, line:7:1, endln:19:16 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ClogParam/dut.sv, line:7:1, endln:19:16 |vpiTypespec: \_struct_typespec: (part_info_t), line:8:12, endln:8:18 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ClogParam/dut.sv, line:7:1, endln:19:16 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ClogParam/dut.sv, line:7:1, endln:19:16 |vpiName:part_info_t |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ClogParam/dut.sv, line:7:1, endln:19:16 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ClogParam/dut.sv, line:7:1, endln:19:16 |vpiPacked:1 |vpiTypespecMember: \_typespec_member: (x), line:9:11, endln:9:12 @@ -391,7 +391,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.NumScrmblBlocks), line:13:19, endln:13:34 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ClogParam/dut.sv, line:7:1, endln:19:16 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ClogParam/dut.sv, line:7:1, endln:19:16 |vpiTypespec: \_int_typespec: , line:13:15, endln:13:18 |vpiParent: @@ -404,7 +404,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:12:26, endln:12:49 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ClogParam/dut.sv, line:7:1, endln:19:16 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ClogParam/dut.sv, line:7:1, endln:19:16 |vpiRhs: \_operation: , line:12:33, endln:12:49 |vpiTypespec: @@ -423,7 +423,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:13:19, endln:13:43 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ClogParam/dut.sv, line:7:1, endln:19:16 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ClogParam/dut.sv, line:7:1, endln:19:16 |vpiRhs: \_hier_path: (Info.x), line:13:37, endln:13:43 |vpiName:Info.x @@ -443,13 +443,13 @@ design: (work@top) |vpiNet: \_logic_net: (work@top.o), line:7:23, endln:7:24 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ClogParam/dut.sv, line:7:1, endln:19:16 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ClogParam/dut.sv, line:7:1, endln:19:16 |vpiName:o |vpiFullName:work@top.o |vpiPort: \_port: (o), line:7:23, endln:7:24 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ClogParam/dut.sv, line:7:1, endln:19:16 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ClogParam/dut.sv, line:7:1, endln:19:16 |vpiName:o |vpiDirection:2 |vpiLowConn: @@ -460,12 +460,12 @@ design: (work@top) \_int_typespec: , line:7:19, endln:7:22 |vpiSigned:1 |uhdmtopModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/ClogParam/dut.sv, line:7:1, endln:19:16 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ClogParam/dut.sv, line:7:1, endln:19:16 |vpiName:work@top |vpiVariables: \_int_var: (work@top.o), line:7:23, endln:7:24 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ClogParam/dut.sv, line:7:1, endln:19:16 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ClogParam/dut.sv, line:7:1, endln:19:16 |vpiTypespec: \_int_typespec: , line:7:19, endln:7:22 |vpiSigned:1 @@ -476,14 +476,14 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.Info), line:12:26, endln:12:30 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ClogParam/dut.sv, line:7:1, endln:19:16 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ClogParam/dut.sv, line:7:1, endln:19:16 |vpiTypespec: \_struct_typespec: (part_info_t), line:8:12, endln:8:18 |vpiParent: \_parameter: (work@top.Info), line:12:26, endln:12:30 |vpiName:part_info_t |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ClogParam/dut.sv, line:7:1, endln:19:16 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ClogParam/dut.sv, line:7:1, endln:19:16 |vpiPacked:1 |vpiTypespecMember: \_typespec_member: (x), line:9:11, endln:9:12 @@ -505,7 +505,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.NumScrmblBlocks), line:13:19, endln:13:34 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ClogParam/dut.sv, line:7:1, endln:19:16 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ClogParam/dut.sv, line:7:1, endln:19:16 |vpiTypespec: \_int_typespec: , line:13:15, endln:13:18 |vpiParent: @@ -518,7 +518,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:12:26, endln:12:49 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ClogParam/dut.sv, line:7:1, endln:19:16 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ClogParam/dut.sv, line:7:1, endln:19:16 |vpiRhs: \_operation: , line:12:33, endln:12:49 |vpiTypespec: @@ -537,7 +537,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:13:19, endln:13:43 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ClogParam/dut.sv, line:7:1, endln:19:16 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ClogParam/dut.sv, line:7:1, endln:19:16 |vpiRhs: \_hier_path: (Info.x), line:13:37, endln:13:43 |vpiName:Info.x @@ -561,7 +561,7 @@ design: (work@top) |vpiPort: \_port: (o), line:7:23, endln:7:24 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ClogParam/dut.sv, line:7:1, endln:19:16 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ClogParam/dut.sv, line:7:1, endln:19:16 |vpiName:o |vpiDirection:2 |vpiLowConn: @@ -576,17 +576,17 @@ design: (work@top) \_int_typespec: , line:7:19, endln:7:22 |vpiSigned:1 |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ClogParam/dut.sv, line:7:1, endln:19:16 - |vpiModule: - \_module: work@otp_ctrl_ecc_reg (work@top.u_otp_ctrl_ecc_reg), file:${SURELOG_DIR}/tests/ClogParam/dut.sv, line:15:4, endln:18:14 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ClogParam/dut.sv, line:7:1, endln:19:16 + |vpiModuleInst: + \_module_inst: work@otp_ctrl_ecc_reg (work@top.u_otp_ctrl_ecc_reg), file:${SURELOG_DIR}/tests/ClogParam/dut.sv, line:15:4, endln:18:14 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ClogParam/dut.sv, line:7:1, endln:19:16 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ClogParam/dut.sv, line:7:1, endln:19:16 |vpiName:u_otp_ctrl_ecc_reg |vpiFullName:work@top.u_otp_ctrl_ecc_reg |vpiVariables: \_int_var: (work@top.u_otp_ctrl_ecc_reg.a), line:1:36, endln:1:37 |vpiParent: - \_module: work@otp_ctrl_ecc_reg (work@top.u_otp_ctrl_ecc_reg), file:${SURELOG_DIR}/tests/ClogParam/dut.sv, line:15:4, endln:18:14 + \_module_inst: work@otp_ctrl_ecc_reg (work@top.u_otp_ctrl_ecc_reg), file:${SURELOG_DIR}/tests/ClogParam/dut.sv, line:15:4, endln:18:14 |vpiTypespec: \_int_typespec: , line:1:32, endln:1:35 |vpiSigned:1 @@ -597,7 +597,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.u_otp_ctrl_ecc_reg.Depth), line:2:19, endln:2:24 |vpiParent: - \_module: work@otp_ctrl_ecc_reg (work@top.u_otp_ctrl_ecc_reg), file:${SURELOG_DIR}/tests/ClogParam/dut.sv, line:15:4, endln:18:14 + \_module_inst: work@otp_ctrl_ecc_reg (work@top.u_otp_ctrl_ecc_reg), file:${SURELOG_DIR}/tests/ClogParam/dut.sv, line:15:4, endln:18:14 |UINT:999 |vpiTypespec: \_int_typespec: , line:2:15, endln:2:18 @@ -610,7 +610,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.u_otp_ctrl_ecc_reg.Aw), line:3:19, endln:3:21 |vpiParent: - \_module: work@otp_ctrl_ecc_reg (work@top.u_otp_ctrl_ecc_reg), file:${SURELOG_DIR}/tests/ClogParam/dut.sv, line:15:4, endln:18:14 + \_module_inst: work@otp_ctrl_ecc_reg (work@top.u_otp_ctrl_ecc_reg), file:${SURELOG_DIR}/tests/ClogParam/dut.sv, line:15:4, endln:18:14 |vpiTypespec: \_int_typespec: , line:3:15, endln:3:18 |vpiParent: @@ -623,7 +623,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:2:19, endln:2:30 |vpiParent: - \_module: work@otp_ctrl_ecc_reg (work@top.u_otp_ctrl_ecc_reg), file:${SURELOG_DIR}/tests/ClogParam/dut.sv, line:15:4, endln:18:14 + \_module_inst: work@otp_ctrl_ecc_reg (work@top.u_otp_ctrl_ecc_reg), file:${SURELOG_DIR}/tests/ClogParam/dut.sv, line:15:4, endln:18:14 |vpiOverriden:1 |vpiRhs: \_hier_path: (Info.x), line:16:15, endln:16:30 @@ -649,7 +649,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:3:19, endln:3:37 |vpiParent: - \_module: work@otp_ctrl_ecc_reg (work@top.u_otp_ctrl_ecc_reg), file:${SURELOG_DIR}/tests/ClogParam/dut.sv, line:15:4, endln:18:14 + \_module_inst: work@otp_ctrl_ecc_reg (work@top.u_otp_ctrl_ecc_reg), file:${SURELOG_DIR}/tests/ClogParam/dut.sv, line:15:4, endln:18:14 |vpiRhs: \_sys_func_call: ($clog2), line:3:24, endln:3:37 |vpiArgument: @@ -681,11 +681,11 @@ design: (work@top) |vpiDefFile:${SURELOG_DIR}/tests/ClogParam/dut.sv |vpiDefLineNo:1 |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ClogParam/dut.sv, line:7:1, endln:19:16 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ClogParam/dut.sv, line:7:1, endln:19:16 |vpiPort: \_port: (a), line:1:36, endln:1:37 |vpiParent: - \_module: work@otp_ctrl_ecc_reg (work@top.u_otp_ctrl_ecc_reg), file:${SURELOG_DIR}/tests/ClogParam/dut.sv, line:15:4, endln:18:14 + \_module_inst: work@otp_ctrl_ecc_reg (work@top.u_otp_ctrl_ecc_reg), file:${SURELOG_DIR}/tests/ClogParam/dut.sv, line:15:4, endln:18:14 |vpiName:a |vpiDirection:2 |vpiHighConn: @@ -708,11 +708,11 @@ design: (work@top) \_int_typespec: , line:1:32, endln:1:35 |vpiSigned:1 |vpiInstance: - \_module: work@otp_ctrl_ecc_reg (work@top.u_otp_ctrl_ecc_reg), file:${SURELOG_DIR}/tests/ClogParam/dut.sv, line:15:4, endln:18:14 + \_module_inst: work@otp_ctrl_ecc_reg (work@top.u_otp_ctrl_ecc_reg), file:${SURELOG_DIR}/tests/ClogParam/dut.sv, line:15:4, endln:18:14 |vpiContAssign: \_cont_assign: , line:4:11, endln:4:17 |vpiParent: - \_module: work@otp_ctrl_ecc_reg (work@top.u_otp_ctrl_ecc_reg), file:${SURELOG_DIR}/tests/ClogParam/dut.sv, line:15:4, endln:18:14 + \_module_inst: work@otp_ctrl_ecc_reg (work@top.u_otp_ctrl_ecc_reg), file:${SURELOG_DIR}/tests/ClogParam/dut.sv, line:15:4, endln:18:14 |vpiRhs: \_ref_obj: (work@top.u_otp_ctrl_ecc_reg.Aw), line:4:15, endln:4:17 |vpiParent: diff --git a/tests/CmdLineOverride/CmdLineOverride.log b/tests/CmdLineOverride/CmdLineOverride.log index c881725132..902d7b5a09 100644 --- a/tests/CmdLineOverride/CmdLineOverride.log +++ b/tests/CmdLineOverride/CmdLineOverride.log @@ -68,7 +68,7 @@ n<> u<31> t c<1> l<1:1> el<8:1> constant 2 design 1 int_typespec 1 -module 5 +module_inst 5 param_assign 2 parameter 2 === UHDM Object Stats End === @@ -78,7 +78,7 @@ parameter 2 constant 2 design 1 int_typespec 1 -module 5 +module_inst 5 param_assign 2 parameter 2 === UHDM Object Stats End === @@ -95,20 +95,20 @@ design: (work@foo) |vpiElaborated:1 |vpiName:work@foo |uhdmallModules: -\_module: work@baz (work@baz), file:${SURELOG_DIR}/tests/CmdLineOverride/dut.sv, line:5:1, endln:6:10 +\_module_inst: work@baz (work@baz), file:${SURELOG_DIR}/tests/CmdLineOverride/dut.sv, line:5:1, endln:6:10 |vpiParent: \_design: (work@foo) |vpiFullName:work@baz |vpiDefName:work@baz |uhdmallModules: -\_module: work@foo (work@foo), file:${SURELOG_DIR}/tests/CmdLineOverride/dut.sv, line:1:1, endln:3:10 +\_module_inst: work@foo (work@foo), file:${SURELOG_DIR}/tests/CmdLineOverride/dut.sv, line:1:1, endln:3:10 |vpiParent: \_design: (work@foo) |vpiFullName:work@foo |vpiParameter: \_parameter: (work@foo.bar), line:2:17, endln:2:20 |vpiParent: - \_module: work@foo (work@foo), file:${SURELOG_DIR}/tests/CmdLineOverride/dut.sv, line:1:1, endln:3:10 + \_module_inst: work@foo (work@foo), file:${SURELOG_DIR}/tests/CmdLineOverride/dut.sv, line:1:1, endln:3:10 |UINT:0 |vpiSigned:1 |vpiName:bar @@ -116,7 +116,7 @@ design: (work@foo) |vpiParamAssign: \_param_assign: , line:2:17, endln:2:24 |vpiParent: - \_module: work@foo (work@foo), file:${SURELOG_DIR}/tests/CmdLineOverride/dut.sv, line:1:1, endln:3:10 + \_module_inst: work@foo (work@foo), file:${SURELOG_DIR}/tests/CmdLineOverride/dut.sv, line:1:1, endln:3:10 |vpiRhs: \_constant: , line:2:23, endln:2:24 |vpiDecompile:0 @@ -132,12 +132,12 @@ design: (work@foo) \_parameter: (work@foo.bar), line:2:17, endln:2:20 |vpiDefName:work@foo |uhdmtopModules: -\_module: work@foo (work@foo), file:${SURELOG_DIR}/tests/CmdLineOverride/dut.sv, line:1:1, endln:3:10 +\_module_inst: work@foo (work@foo), file:${SURELOG_DIR}/tests/CmdLineOverride/dut.sv, line:1:1, endln:3:10 |vpiName:work@foo |vpiParameter: \_parameter: (work@foo.bar), line:2:17, endln:2:20 |vpiParent: - \_module: work@foo (work@foo), file:${SURELOG_DIR}/tests/CmdLineOverride/dut.sv, line:1:1, endln:3:10 + \_module_inst: work@foo (work@foo), file:${SURELOG_DIR}/tests/CmdLineOverride/dut.sv, line:1:1, endln:3:10 |UINT:0 |vpiSigned:1 |vpiName:bar @@ -145,7 +145,7 @@ design: (work@foo) |vpiParamAssign: \_param_assign: , line:2:17, endln:2:24 |vpiParent: - \_module: work@foo (work@foo), file:${SURELOG_DIR}/tests/CmdLineOverride/dut.sv, line:1:1, endln:3:10 + \_module_inst: work@foo (work@foo), file:${SURELOG_DIR}/tests/CmdLineOverride/dut.sv, line:1:1, endln:3:10 |vpiRhs: \_constant: , line:2:23, endln:2:24 |vpiDecompile:1 @@ -158,7 +158,7 @@ design: (work@foo) |vpiTop:1 |vpiTopModule:1 |uhdmtopModules: -\_module: work@baz (work@baz), file:${SURELOG_DIR}/tests/CmdLineOverride/dut.sv, line:5:1, endln:6:10 +\_module_inst: work@baz (work@baz), file:${SURELOG_DIR}/tests/CmdLineOverride/dut.sv, line:5:1, endln:6:10 |vpiName:work@baz |vpiDefName:work@baz |vpiTop:1 diff --git a/tests/ComplexBitSelect/ComplexBitSelect.log b/tests/ComplexBitSelect/ComplexBitSelect.log index 3ccf062590..6b1a8c178c 100644 --- a/tests/ComplexBitSelect/ComplexBitSelect.log +++ b/tests/ComplexBitSelect/ComplexBitSelect.log @@ -511,7 +511,7 @@ int_typespec 70 int_var 4 io_decl 11 logic_var 1 -module 8 +module_inst 8 operation 47 package 5 param_assign 20 @@ -542,7 +542,7 @@ int_typespec 70 int_var 4 io_decl 22 logic_var 1 -module 8 +module_inst 8 operation 47 package 5 param_assign 20 @@ -1327,14 +1327,14 @@ design: (work@flash_ctrl_info_cfg) \_int_typespec: |vpiSigned:1 |uhdmallModules: -\_module: work@flash_ctrl_info_cfg (work@flash_ctrl_info_cfg), file:${SURELOG_DIR}/tests/ComplexBitSelect/dut.sv, line:12:1, endln:24:10 +\_module_inst: work@flash_ctrl_info_cfg (work@flash_ctrl_info_cfg), file:${SURELOG_DIR}/tests/ComplexBitSelect/dut.sv, line:12:1, endln:24:10 |vpiParent: \_design: (work@flash_ctrl_info_cfg) |vpiFullName:work@flash_ctrl_info_cfg |vpiParameter: \_parameter: (work@flash_ctrl_info_cfg.InfoTypeSize), line:3:17, endln:3:29 |vpiParent: - \_module: work@flash_ctrl_info_cfg (work@flash_ctrl_info_cfg), file:${SURELOG_DIR}/tests/ComplexBitSelect/dut.sv, line:12:1, endln:24:10 + \_module_inst: work@flash_ctrl_info_cfg (work@flash_ctrl_info_cfg), file:${SURELOG_DIR}/tests/ComplexBitSelect/dut.sv, line:12:1, endln:24:10 |vpiSize:1 |vpiTypespec: \_array_typespec: @@ -1432,7 +1432,7 @@ design: (work@flash_ctrl_info_cfg) |vpiParameter: \_parameter: (work@flash_ctrl_info_cfg.InfoTypes), line:2:17, endln:2:26 |vpiParent: - \_module: work@flash_ctrl_info_cfg (work@flash_ctrl_info_cfg), file:${SURELOG_DIR}/tests/ComplexBitSelect/dut.sv, line:12:1, endln:24:10 + \_module_inst: work@flash_ctrl_info_cfg (work@flash_ctrl_info_cfg), file:${SURELOG_DIR}/tests/ComplexBitSelect/dut.sv, line:12:1, endln:24:10 |UINT:3 |vpiTypespec: \_int_typespec: , line:2:13, endln:2:16 @@ -1448,7 +1448,7 @@ design: (work@flash_ctrl_info_cfg) |vpiParameter: \_parameter: (work@flash_ctrl_info_cfg.InfosPerBank), line:8:17, endln:8:29 |vpiParent: - \_module: work@flash_ctrl_info_cfg (work@flash_ctrl_info_cfg), file:${SURELOG_DIR}/tests/ComplexBitSelect/dut.sv, line:12:1, endln:24:10 + \_module_inst: work@flash_ctrl_info_cfg (work@flash_ctrl_info_cfg), file:${SURELOG_DIR}/tests/ComplexBitSelect/dut.sv, line:12:1, endln:24:10 |UINT:10 |vpiTypespec: \_int_typespec: , line:8:13, endln:8:16 @@ -1464,7 +1464,7 @@ design: (work@flash_ctrl_info_cfg) |vpiParameter: \_parameter: (work@flash_ctrl_info_cfg.InfoSel), line:14:17, endln:14:24 |vpiParent: - \_module: work@flash_ctrl_info_cfg (work@flash_ctrl_info_cfg), file:${SURELOG_DIR}/tests/ComplexBitSelect/dut.sv, line:12:1, endln:24:10 + \_module_inst: work@flash_ctrl_info_cfg (work@flash_ctrl_info_cfg), file:${SURELOG_DIR}/tests/ComplexBitSelect/dut.sv, line:12:1, endln:24:10 |UINT:2 |vpiTypespec: \_int_typespec: , line:14:13, endln:14:16 @@ -1477,7 +1477,7 @@ design: (work@flash_ctrl_info_cfg) |vpiParamAssign: \_param_assign: , line:2:17, endln:2:36 |vpiParent: - \_module: work@flash_ctrl_info_cfg (work@flash_ctrl_info_cfg), file:${SURELOG_DIR}/tests/ComplexBitSelect/dut.sv, line:12:1, endln:24:10 + \_module_inst: work@flash_ctrl_info_cfg (work@flash_ctrl_info_cfg), file:${SURELOG_DIR}/tests/ComplexBitSelect/dut.sv, line:12:1, endln:24:10 |vpiRhs: \_constant: , line:2:35, endln:2:36 |vpiParent: @@ -1512,7 +1512,7 @@ design: (work@flash_ctrl_info_cfg) |vpiParamAssign: \_param_assign: , line:3:17, endln:7:4 |vpiParent: - \_module: work@flash_ctrl_info_cfg (work@flash_ctrl_info_cfg), file:${SURELOG_DIR}/tests/ComplexBitSelect/dut.sv, line:12:1, endln:24:10 + \_module_inst: work@flash_ctrl_info_cfg (work@flash_ctrl_info_cfg), file:${SURELOG_DIR}/tests/ComplexBitSelect/dut.sv, line:12:1, endln:24:10 |vpiRhs: \_operation: , line:3:44, endln:7:4 |vpiParent: @@ -1643,7 +1643,7 @@ design: (work@flash_ctrl_info_cfg) |vpiParamAssign: \_param_assign: , line:8:17, endln:8:37 |vpiParent: - \_module: work@flash_ctrl_info_cfg (work@flash_ctrl_info_cfg), file:${SURELOG_DIR}/tests/ComplexBitSelect/dut.sv, line:12:1, endln:24:10 + \_module_inst: work@flash_ctrl_info_cfg (work@flash_ctrl_info_cfg), file:${SURELOG_DIR}/tests/ComplexBitSelect/dut.sv, line:12:1, endln:24:10 |vpiRhs: \_constant: , line:8:35, endln:8:37 |vpiParent: @@ -1678,7 +1678,7 @@ design: (work@flash_ctrl_info_cfg) |vpiParamAssign: \_param_assign: , line:14:17, endln:14:28 |vpiParent: - \_module: work@flash_ctrl_info_cfg (work@flash_ctrl_info_cfg), file:${SURELOG_DIR}/tests/ComplexBitSelect/dut.sv, line:12:1, endln:24:10 + \_module_inst: work@flash_ctrl_info_cfg (work@flash_ctrl_info_cfg), file:${SURELOG_DIR}/tests/ComplexBitSelect/dut.sv, line:12:1, endln:24:10 |vpiRhs: \_constant: , line:14:27, endln:14:28 |vpiDecompile:2 @@ -1693,12 +1693,12 @@ design: (work@flash_ctrl_info_cfg) \_import_typespec: (flash_ctrl_pkg), line:12:35, endln:12:52 |vpiDefName:work@flash_ctrl_info_cfg |uhdmtopModules: -\_module: work@flash_ctrl_info_cfg (work@flash_ctrl_info_cfg), file:${SURELOG_DIR}/tests/ComplexBitSelect/dut.sv, line:12:1, endln:24:10 +\_module_inst: work@flash_ctrl_info_cfg (work@flash_ctrl_info_cfg), file:${SURELOG_DIR}/tests/ComplexBitSelect/dut.sv, line:12:1, endln:24:10 |vpiName:work@flash_ctrl_info_cfg |vpiParameter: \_parameter: (work@flash_ctrl_info_cfg.InfoTypeSize), line:3:17, endln:3:29 |vpiParent: - \_module: work@flash_ctrl_info_cfg (work@flash_ctrl_info_cfg), file:${SURELOG_DIR}/tests/ComplexBitSelect/dut.sv, line:12:1, endln:24:10 + \_module_inst: work@flash_ctrl_info_cfg (work@flash_ctrl_info_cfg), file:${SURELOG_DIR}/tests/ComplexBitSelect/dut.sv, line:12:1, endln:24:10 |vpiSize:1 |vpiTypespec: \_array_typespec: @@ -1796,7 +1796,7 @@ design: (work@flash_ctrl_info_cfg) |vpiParameter: \_parameter: (work@flash_ctrl_info_cfg.InfoTypes), line:2:17, endln:2:26 |vpiParent: - \_module: work@flash_ctrl_info_cfg (work@flash_ctrl_info_cfg), file:${SURELOG_DIR}/tests/ComplexBitSelect/dut.sv, line:12:1, endln:24:10 + \_module_inst: work@flash_ctrl_info_cfg (work@flash_ctrl_info_cfg), file:${SURELOG_DIR}/tests/ComplexBitSelect/dut.sv, line:12:1, endln:24:10 |UINT:3 |vpiTypespec: \_int_typespec: , line:2:13, endln:2:16 @@ -1812,7 +1812,7 @@ design: (work@flash_ctrl_info_cfg) |vpiParameter: \_parameter: (work@flash_ctrl_info_cfg.InfosPerBank), line:8:17, endln:8:29 |vpiParent: - \_module: work@flash_ctrl_info_cfg (work@flash_ctrl_info_cfg), file:${SURELOG_DIR}/tests/ComplexBitSelect/dut.sv, line:12:1, endln:24:10 + \_module_inst: work@flash_ctrl_info_cfg (work@flash_ctrl_info_cfg), file:${SURELOG_DIR}/tests/ComplexBitSelect/dut.sv, line:12:1, endln:24:10 |UINT:10 |vpiTypespec: \_int_typespec: , line:8:13, endln:8:16 @@ -1828,7 +1828,7 @@ design: (work@flash_ctrl_info_cfg) |vpiParameter: \_parameter: (work@flash_ctrl_info_cfg.InfoSel), line:14:17, endln:14:24 |vpiParent: - \_module: work@flash_ctrl_info_cfg (work@flash_ctrl_info_cfg), file:${SURELOG_DIR}/tests/ComplexBitSelect/dut.sv, line:12:1, endln:24:10 + \_module_inst: work@flash_ctrl_info_cfg (work@flash_ctrl_info_cfg), file:${SURELOG_DIR}/tests/ComplexBitSelect/dut.sv, line:12:1, endln:24:10 |UINT:2 |vpiTypespec: \_int_typespec: , line:14:13, endln:14:16 @@ -1841,7 +1841,7 @@ design: (work@flash_ctrl_info_cfg) |vpiParamAssign: \_param_assign: , line:2:17, endln:2:36 |vpiParent: - \_module: work@flash_ctrl_info_cfg (work@flash_ctrl_info_cfg), file:${SURELOG_DIR}/tests/ComplexBitSelect/dut.sv, line:12:1, endln:24:10 + \_module_inst: work@flash_ctrl_info_cfg (work@flash_ctrl_info_cfg), file:${SURELOG_DIR}/tests/ComplexBitSelect/dut.sv, line:12:1, endln:24:10 |vpiRhs: \_constant: , line:2:35, endln:2:36 |vpiDecompile:3 @@ -1855,7 +1855,7 @@ design: (work@flash_ctrl_info_cfg) |vpiParamAssign: \_param_assign: , line:3:17, endln:7:4 |vpiParent: - \_module: work@flash_ctrl_info_cfg (work@flash_ctrl_info_cfg), file:${SURELOG_DIR}/tests/ComplexBitSelect/dut.sv, line:12:1, endln:24:10 + \_module_inst: work@flash_ctrl_info_cfg (work@flash_ctrl_info_cfg), file:${SURELOG_DIR}/tests/ComplexBitSelect/dut.sv, line:12:1, endln:24:10 |vpiRhs: \_operation: , line:3:44, endln:7:4 |vpiParent: @@ -1940,7 +1940,7 @@ design: (work@flash_ctrl_info_cfg) |vpiParamAssign: \_param_assign: , line:8:17, endln:8:37 |vpiParent: - \_module: work@flash_ctrl_info_cfg (work@flash_ctrl_info_cfg), file:${SURELOG_DIR}/tests/ComplexBitSelect/dut.sv, line:12:1, endln:24:10 + \_module_inst: work@flash_ctrl_info_cfg (work@flash_ctrl_info_cfg), file:${SURELOG_DIR}/tests/ComplexBitSelect/dut.sv, line:12:1, endln:24:10 |vpiRhs: \_constant: , line:8:35, endln:8:37 |vpiDecompile:10 @@ -1954,7 +1954,7 @@ design: (work@flash_ctrl_info_cfg) |vpiParamAssign: \_param_assign: , line:14:17, endln:14:28 |vpiParent: - \_module: work@flash_ctrl_info_cfg (work@flash_ctrl_info_cfg), file:${SURELOG_DIR}/tests/ComplexBitSelect/dut.sv, line:12:1, endln:24:10 + \_module_inst: work@flash_ctrl_info_cfg (work@flash_ctrl_info_cfg), file:${SURELOG_DIR}/tests/ComplexBitSelect/dut.sv, line:12:1, endln:24:10 |vpiRhs: \_constant: , line:14:27, endln:14:28 |vpiDecompile:2 @@ -1973,7 +1973,7 @@ design: (work@flash_ctrl_info_cfg) |vpiGenScopeArray: \_gen_scope_array: (work@flash_ctrl_info_cfg.gen_info_priv[0]), line:16:44, endln:22:6 |vpiParent: - \_module: work@flash_ctrl_info_cfg (work@flash_ctrl_info_cfg), file:${SURELOG_DIR}/tests/ComplexBitSelect/dut.sv, line:12:1, endln:24:10 + \_module_inst: work@flash_ctrl_info_cfg (work@flash_ctrl_info_cfg), file:${SURELOG_DIR}/tests/ComplexBitSelect/dut.sv, line:12:1, endln:24:10 |vpiName:gen_info_priv[0] |vpiFullName:work@flash_ctrl_info_cfg.gen_info_priv[0] |vpiGenScope: @@ -1994,7 +1994,7 @@ design: (work@flash_ctrl_info_cfg) |vpiGenScopeArray: \_gen_scope_array: (work@flash_ctrl_info_cfg.gen_info_priv[1]), line:16:44, endln:22:6 |vpiParent: - \_module: work@flash_ctrl_info_cfg (work@flash_ctrl_info_cfg), file:${SURELOG_DIR}/tests/ComplexBitSelect/dut.sv, line:12:1, endln:24:10 + \_module_inst: work@flash_ctrl_info_cfg (work@flash_ctrl_info_cfg), file:${SURELOG_DIR}/tests/ComplexBitSelect/dut.sv, line:12:1, endln:24:10 |vpiName:gen_info_priv[1] |vpiFullName:work@flash_ctrl_info_cfg.gen_info_priv[1] |vpiGenScope: @@ -2015,7 +2015,7 @@ design: (work@flash_ctrl_info_cfg) |vpiGenScopeArray: \_gen_scope_array: (work@flash_ctrl_info_cfg.gen_info_priv[2]), line:16:44, endln:22:6 |vpiParent: - \_module: work@flash_ctrl_info_cfg (work@flash_ctrl_info_cfg), file:${SURELOG_DIR}/tests/ComplexBitSelect/dut.sv, line:12:1, endln:24:10 + \_module_inst: work@flash_ctrl_info_cfg (work@flash_ctrl_info_cfg), file:${SURELOG_DIR}/tests/ComplexBitSelect/dut.sv, line:12:1, endln:24:10 |vpiName:gen_info_priv[2] |vpiFullName:work@flash_ctrl_info_cfg.gen_info_priv[2] |vpiGenScope: @@ -2036,7 +2036,7 @@ design: (work@flash_ctrl_info_cfg) |vpiGenScopeArray: \_gen_scope_array: (work@flash_ctrl_info_cfg.gen_info_priv[3]), line:16:44, endln:22:6 |vpiParent: - \_module: work@flash_ctrl_info_cfg (work@flash_ctrl_info_cfg), file:${SURELOG_DIR}/tests/ComplexBitSelect/dut.sv, line:12:1, endln:24:10 + \_module_inst: work@flash_ctrl_info_cfg (work@flash_ctrl_info_cfg), file:${SURELOG_DIR}/tests/ComplexBitSelect/dut.sv, line:12:1, endln:24:10 |vpiName:gen_info_priv[3] |vpiFullName:work@flash_ctrl_info_cfg.gen_info_priv[3] |vpiGenScope: @@ -2098,7 +2098,7 @@ design: (work@flash_ctrl_info_cfg) |vpiGenScopeArray: \_gen_scope_array: (work@flash_ctrl_info_cfg.gen_info_priv[4]), line:16:44, endln:22:6 |vpiParent: - \_module: work@flash_ctrl_info_cfg (work@flash_ctrl_info_cfg), file:${SURELOG_DIR}/tests/ComplexBitSelect/dut.sv, line:12:1, endln:24:10 + \_module_inst: work@flash_ctrl_info_cfg (work@flash_ctrl_info_cfg), file:${SURELOG_DIR}/tests/ComplexBitSelect/dut.sv, line:12:1, endln:24:10 |vpiName:gen_info_priv[4] |vpiFullName:work@flash_ctrl_info_cfg.gen_info_priv[4] |vpiGenScope: @@ -2160,7 +2160,7 @@ design: (work@flash_ctrl_info_cfg) |vpiGenScopeArray: \_gen_scope_array: (work@flash_ctrl_info_cfg.gen_info_priv[5]), line:16:44, endln:22:6 |vpiParent: - \_module: work@flash_ctrl_info_cfg (work@flash_ctrl_info_cfg), file:${SURELOG_DIR}/tests/ComplexBitSelect/dut.sv, line:12:1, endln:24:10 + \_module_inst: work@flash_ctrl_info_cfg (work@flash_ctrl_info_cfg), file:${SURELOG_DIR}/tests/ComplexBitSelect/dut.sv, line:12:1, endln:24:10 |vpiName:gen_info_priv[5] |vpiFullName:work@flash_ctrl_info_cfg.gen_info_priv[5] |vpiGenScope: @@ -2222,7 +2222,7 @@ design: (work@flash_ctrl_info_cfg) |vpiGenScopeArray: \_gen_scope_array: (work@flash_ctrl_info_cfg.gen_info_priv[6]), line:16:44, endln:22:6 |vpiParent: - \_module: work@flash_ctrl_info_cfg (work@flash_ctrl_info_cfg), file:${SURELOG_DIR}/tests/ComplexBitSelect/dut.sv, line:12:1, endln:24:10 + \_module_inst: work@flash_ctrl_info_cfg (work@flash_ctrl_info_cfg), file:${SURELOG_DIR}/tests/ComplexBitSelect/dut.sv, line:12:1, endln:24:10 |vpiName:gen_info_priv[6] |vpiFullName:work@flash_ctrl_info_cfg.gen_info_priv[6] |vpiGenScope: @@ -2284,7 +2284,7 @@ design: (work@flash_ctrl_info_cfg) |vpiGenScopeArray: \_gen_scope_array: (work@flash_ctrl_info_cfg.gen_info_priv[7]), line:16:44, endln:22:6 |vpiParent: - \_module: work@flash_ctrl_info_cfg (work@flash_ctrl_info_cfg), file:${SURELOG_DIR}/tests/ComplexBitSelect/dut.sv, line:12:1, endln:24:10 + \_module_inst: work@flash_ctrl_info_cfg (work@flash_ctrl_info_cfg), file:${SURELOG_DIR}/tests/ComplexBitSelect/dut.sv, line:12:1, endln:24:10 |vpiName:gen_info_priv[7] |vpiFullName:work@flash_ctrl_info_cfg.gen_info_priv[7] |vpiGenScope: @@ -2346,7 +2346,7 @@ design: (work@flash_ctrl_info_cfg) |vpiGenScopeArray: \_gen_scope_array: (work@flash_ctrl_info_cfg.gen_info_priv[8]), line:16:44, endln:22:6 |vpiParent: - \_module: work@flash_ctrl_info_cfg (work@flash_ctrl_info_cfg), file:${SURELOG_DIR}/tests/ComplexBitSelect/dut.sv, line:12:1, endln:24:10 + \_module_inst: work@flash_ctrl_info_cfg (work@flash_ctrl_info_cfg), file:${SURELOG_DIR}/tests/ComplexBitSelect/dut.sv, line:12:1, endln:24:10 |vpiName:gen_info_priv[8] |vpiFullName:work@flash_ctrl_info_cfg.gen_info_priv[8] |vpiGenScope: @@ -2408,7 +2408,7 @@ design: (work@flash_ctrl_info_cfg) |vpiGenScopeArray: \_gen_scope_array: (work@flash_ctrl_info_cfg.gen_info_priv[9]), line:16:44, endln:22:6 |vpiParent: - \_module: work@flash_ctrl_info_cfg (work@flash_ctrl_info_cfg), file:${SURELOG_DIR}/tests/ComplexBitSelect/dut.sv, line:12:1, endln:24:10 + \_module_inst: work@flash_ctrl_info_cfg (work@flash_ctrl_info_cfg), file:${SURELOG_DIR}/tests/ComplexBitSelect/dut.sv, line:12:1, endln:24:10 |vpiName:gen_info_priv[9] |vpiFullName:work@flash_ctrl_info_cfg.gen_info_priv[9] |vpiGenScope: diff --git a/tests/ComplexEscaped/ComplexEscaped.log b/tests/ComplexEscaped/ComplexEscaped.log index 0659c4173a..565c386af9 100644 --- a/tests/ComplexEscaped/ComplexEscaped.log +++ b/tests/ComplexEscaped/ComplexEscaped.log @@ -115,7 +115,7 @@ constant 1 design 1 initial 1 logic_net 1 -module 2 +module_inst 2 port 2 ref_obj 3 string_typespec 3 @@ -130,7 +130,7 @@ constant 1 design 1 initial 2 logic_net 1 -module 2 +module_inst 2 port 3 ref_obj 5 string_typespec 3 @@ -149,7 +149,7 @@ design: (work@top) |vpiElaborated:1 |vpiName:work@top |uhdmallModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/ComplexEscaped/dut.sv, line:1:1, endln:5:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ComplexEscaped/dut.sv, line:1:1, endln:5:10 |vpiParent: \_design: (work@top) |vpiFullName:work@top @@ -157,13 +157,13 @@ design: (work@top) |vpiNet: \_logic_net: (work@top.o), line:1:26, endln:1:27 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ComplexEscaped/dut.sv, line:1:1, endln:5:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ComplexEscaped/dut.sv, line:1:1, endln:5:10 |vpiName:o |vpiFullName:work@top.o |vpiPort: \_port: (o), line:1:26, endln:1:27 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ComplexEscaped/dut.sv, line:1:1, endln:5:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ComplexEscaped/dut.sv, line:1:1, endln:5:10 |vpiName:o |vpiDirection:2 |vpiLowConn: @@ -175,7 +175,7 @@ design: (work@top) |vpiProcess: \_initial: , line:2:4, endln:4:7 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ComplexEscaped/dut.sv, line:1:1, endln:5:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ComplexEscaped/dut.sv, line:1:1, endln:5:10 |vpiStmt: \_begin: (work@top), line:2:12, endln:4:7 |vpiParent: @@ -204,12 +204,12 @@ design: (work@top) |vpiActual: \_string_var: (work@top.o), line:1:26, endln:1:27 |uhdmtopModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/ComplexEscaped/dut.sv, line:1:1, endln:5:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ComplexEscaped/dut.sv, line:1:1, endln:5:10 |vpiName:work@top |vpiVariables: \_string_var: (work@top.o), line:1:26, endln:1:27 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ComplexEscaped/dut.sv, line:1:1, endln:5:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ComplexEscaped/dut.sv, line:1:1, endln:5:10 |vpiTypespec: \_string_typespec: , line:1:19, endln:1:25 |vpiName:o @@ -221,7 +221,7 @@ design: (work@top) |vpiPort: \_port: (o), line:1:26, endln:1:27 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ComplexEscaped/dut.sv, line:1:1, endln:5:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ComplexEscaped/dut.sv, line:1:1, endln:5:10 |vpiName:o |vpiDirection:2 |vpiLowConn: @@ -235,11 +235,11 @@ design: (work@top) |vpiTypedef: \_string_typespec: , line:1:19, endln:1:25 |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ComplexEscaped/dut.sv, line:1:1, endln:5:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ComplexEscaped/dut.sv, line:1:1, endln:5:10 |vpiProcess: \_initial: , line:2:4, endln:4:7 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ComplexEscaped/dut.sv, line:1:1, endln:5:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ComplexEscaped/dut.sv, line:1:1, endln:5:10 |vpiStmt: \_begin: (work@top), line:2:12, endln:4:7 |vpiParent: diff --git a/tests/ComplexParamOverload/ComplexParamOverload.log b/tests/ComplexParamOverload/ComplexParamOverload.log index 10297a0b04..e19ab0c66a 100644 --- a/tests/ComplexParamOverload/ComplexParamOverload.log +++ b/tests/ComplexParamOverload/ComplexParamOverload.log @@ -429,7 +429,7 @@ hier_path 1 import_typespec 3 int_typespec 16 logic_net 1 -module 22 +module_inst 22 package 3 param_assign 12 parameter 12 @@ -449,7 +449,7 @@ hier_path 1 import_typespec 3 int_typespec 16 logic_net 1 -module 22 +module_inst 22 package 3 param_assign 12 parameter 12 @@ -599,7 +599,7 @@ design: (work@top) |vpiTypedef: \_enum_typespec: (pinmux_pkg::enum1_e), line:2:4, endln:4:14 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ComplexParamOverload/dut.sv, line:65:1, endln:74:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ComplexParamOverload/dut.sv, line:65:1, endln:74:10 |vpiName:pinmux_pkg::enum1_e |vpiInstance: \_package: pinmux_pkg (pinmux_pkg::), file:${SURELOG_DIR}/tests/ComplexParamOverload/dut.sv, line:1:1, endln:25:11 @@ -617,7 +617,7 @@ design: (work@top) |vpiTypedef: \_enum_typespec: (pinmux_pkg::enum2_e), line:10:4, endln:12:14 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ComplexParamOverload/dut.sv, line:65:1, endln:74:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ComplexParamOverload/dut.sv, line:65:1, endln:74:10 |vpiName:pinmux_pkg::enum2_e |vpiInstance: \_package: pinmux_pkg (pinmux_pkg::), file:${SURELOG_DIR}/tests/ComplexParamOverload/dut.sv, line:1:1, endln:25:11 @@ -635,7 +635,7 @@ design: (work@top) |vpiTypedef: \_enum_typespec: (pinmux_pkg::enum3_e), line:18:4, endln:20:14 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ComplexParamOverload/dut.sv, line:65:1, endln:74:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ComplexParamOverload/dut.sv, line:65:1, endln:74:10 |vpiName:pinmux_pkg::enum3_e |vpiInstance: \_package: pinmux_pkg (pinmux_pkg::), file:${SURELOG_DIR}/tests/ComplexParamOverload/dut.sv, line:1:1, endln:25:11 @@ -653,7 +653,7 @@ design: (work@top) |vpiTypedef: \_struct_typespec: (pinmux_pkg::struct1_t), line:6:12, endln:6:18 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ComplexParamOverload/dut.sv, line:65:1, endln:74:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ComplexParamOverload/dut.sv, line:65:1, endln:74:10 |vpiName:pinmux_pkg::struct1_t |vpiInstance: \_package: pinmux_pkg (pinmux_pkg::), file:${SURELOG_DIR}/tests/ComplexParamOverload/dut.sv, line:1:1, endln:25:11 @@ -673,7 +673,7 @@ design: (work@top) |vpiTypedef: \_struct_typespec: (pinmux_pkg::struct2_t), line:14:12, endln:14:18 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ComplexParamOverload/dut.sv, line:65:1, endln:74:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ComplexParamOverload/dut.sv, line:65:1, endln:74:10 |vpiName:pinmux_pkg::struct2_t |vpiInstance: \_package: pinmux_pkg (pinmux_pkg::), file:${SURELOG_DIR}/tests/ComplexParamOverload/dut.sv, line:1:1, endln:25:11 @@ -693,7 +693,7 @@ design: (work@top) |vpiTypedef: \_struct_typespec: (pinmux_pkg::struct3_t), line:22:12, endln:22:18 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ComplexParamOverload/dut.sv, line:65:1, endln:74:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ComplexParamOverload/dut.sv, line:65:1, endln:74:10 |vpiName:pinmux_pkg::struct3_t |vpiInstance: \_package: pinmux_pkg (pinmux_pkg::), file:${SURELOG_DIR}/tests/ComplexParamOverload/dut.sv, line:1:1, endln:25:11 @@ -713,14 +713,14 @@ design: (work@top) |vpiDefName:pinmux_pkg |vpiTop:1 |uhdmallModules: -\_module: work@almost_top (work@almost_top), file:${SURELOG_DIR}/tests/ComplexParamOverload/dut.sv, line:54:1, endln:63:10 +\_module_inst: work@almost_top (work@almost_top), file:${SURELOG_DIR}/tests/ComplexParamOverload/dut.sv, line:54:1, endln:63:10 |vpiParent: \_design: (work@top) |vpiFullName:work@almost_top |vpiParameter: \_parameter: (work@almost_top.TargetCfg), line:56:24, endln:56:33 |vpiParent: - \_module: work@almost_top (work@almost_top), file:${SURELOG_DIR}/tests/ComplexParamOverload/dut.sv, line:54:1, endln:63:10 + \_module_inst: work@almost_top (work@almost_top), file:${SURELOG_DIR}/tests/ComplexParamOverload/dut.sv, line:54:1, endln:63:10 |UINT:1 |vpiTypespec: \_struct_typespec: (pinmux_pkg::struct1_t), line:6:12, endln:6:18 @@ -729,7 +729,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:56:24, endln:56:37 |vpiParent: - \_module: work@almost_top (work@almost_top), file:${SURELOG_DIR}/tests/ComplexParamOverload/dut.sv, line:54:1, endln:63:10 + \_module_inst: work@almost_top (work@almost_top), file:${SURELOG_DIR}/tests/ComplexParamOverload/dut.sv, line:54:1, endln:63:10 |vpiRhs: \_constant: , line:56:36, endln:56:37 |vpiDecompile:1 @@ -756,14 +756,14 @@ design: (work@top) \_import_typespec: (pinmux_pkg), line:55:11, endln:55:24 |vpiDefName:work@almost_top |uhdmallModules: -\_module: work@prim_generic (work@prim_generic), file:${SURELOG_DIR}/tests/ComplexParamOverload/dut.sv, line:27:1, endln:30:10 +\_module_inst: work@prim_generic (work@prim_generic), file:${SURELOG_DIR}/tests/ComplexParamOverload/dut.sv, line:27:1, endln:30:10 |vpiParent: \_design: (work@top) |vpiFullName:work@prim_generic |vpiParameter: \_parameter: (work@prim_generic.PadTypeInGeneric), line:28:18, endln:28:34 |vpiParent: - \_module: work@prim_generic (work@prim_generic), file:${SURELOG_DIR}/tests/ComplexParamOverload/dut.sv, line:27:1, endln:30:10 + \_module_inst: work@prim_generic (work@prim_generic), file:${SURELOG_DIR}/tests/ComplexParamOverload/dut.sv, line:27:1, endln:30:10 |UINT:0 |vpiTypespec: \_int_typespec: , line:28:14, endln:28:17 @@ -776,7 +776,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:28:18, endln:28:38 |vpiParent: - \_module: work@prim_generic (work@prim_generic), file:${SURELOG_DIR}/tests/ComplexParamOverload/dut.sv, line:27:1, endln:30:10 + \_module_inst: work@prim_generic (work@prim_generic), file:${SURELOG_DIR}/tests/ComplexParamOverload/dut.sv, line:27:1, endln:30:10 |vpiRhs: \_constant: , line:28:37, endln:28:38 |vpiDecompile:0 @@ -791,7 +791,7 @@ design: (work@top) |vpiContAssign: \_cont_assign: , line:29:11, endln:29:31 |vpiParent: - \_module: work@prim_generic (work@prim_generic), file:${SURELOG_DIR}/tests/ComplexParamOverload/dut.sv, line:27:1, endln:30:10 + \_module_inst: work@prim_generic (work@prim_generic), file:${SURELOG_DIR}/tests/ComplexParamOverload/dut.sv, line:27:1, endln:30:10 |vpiRhs: \_ref_obj: (work@prim_generic.PadTypeInGeneric), line:29:15, endln:29:31 |vpiParent: @@ -807,14 +807,14 @@ design: (work@top) |vpiActual: \_logic_net: (o) |uhdmallModules: -\_module: work@prim_pad_attr (work@prim_pad_attr), file:${SURELOG_DIR}/tests/ComplexParamOverload/dut.sv, line:42:1, endln:52:10 +\_module_inst: work@prim_pad_attr (work@prim_pad_attr), file:${SURELOG_DIR}/tests/ComplexParamOverload/dut.sv, line:42:1, endln:52:10 |vpiParent: \_design: (work@top) |vpiFullName:work@prim_pad_attr |vpiParameter: \_parameter: (work@prim_pad_attr.TargetCfg), line:44:24, endln:44:33 |vpiParent: - \_module: work@prim_pad_attr (work@prim_pad_attr), file:${SURELOG_DIR}/tests/ComplexParamOverload/dut.sv, line:42:1, endln:52:10 + \_module_inst: work@prim_pad_attr (work@prim_pad_attr), file:${SURELOG_DIR}/tests/ComplexParamOverload/dut.sv, line:42:1, endln:52:10 |UINT:77 |vpiTypespec: \_struct_typespec: (pinmux_pkg::struct3_t), line:22:12, endln:22:18 @@ -823,7 +823,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@prim_pad_attr.PadType), line:45:18, endln:45:25 |vpiParent: - \_module: work@prim_pad_attr (work@prim_pad_attr), file:${SURELOG_DIR}/tests/ComplexParamOverload/dut.sv, line:42:1, endln:52:10 + \_module_inst: work@prim_pad_attr (work@prim_pad_attr), file:${SURELOG_DIR}/tests/ComplexParamOverload/dut.sv, line:42:1, endln:52:10 |UINT:0 |vpiTypespec: \_int_typespec: , line:45:14, endln:45:17 @@ -836,7 +836,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:44:24, endln:44:38 |vpiParent: - \_module: work@prim_pad_attr (work@prim_pad_attr), file:${SURELOG_DIR}/tests/ComplexParamOverload/dut.sv, line:42:1, endln:52:10 + \_module_inst: work@prim_pad_attr (work@prim_pad_attr), file:${SURELOG_DIR}/tests/ComplexParamOverload/dut.sv, line:42:1, endln:52:10 |vpiRhs: \_constant: , line:44:36, endln:44:38 |vpiDecompile:77 @@ -850,7 +850,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:45:18, endln:45:29 |vpiParent: - \_module: work@prim_pad_attr (work@prim_pad_attr), file:${SURELOG_DIR}/tests/ComplexParamOverload/dut.sv, line:42:1, endln:52:10 + \_module_inst: work@prim_pad_attr (work@prim_pad_attr), file:${SURELOG_DIR}/tests/ComplexParamOverload/dut.sv, line:42:1, endln:52:10 |vpiRhs: \_constant: , line:45:28, endln:45:29 |vpiDecompile:0 @@ -877,14 +877,14 @@ design: (work@top) \_import_typespec: (pinmux_pkg), line:43:11, endln:43:24 |vpiDefName:work@prim_pad_attr |uhdmallModules: -\_module: work@prim_submodule (work@prim_submodule), file:${SURELOG_DIR}/tests/ComplexParamOverload/dut.sv, line:32:1, endln:40:10 +\_module_inst: work@prim_submodule (work@prim_submodule), file:${SURELOG_DIR}/tests/ComplexParamOverload/dut.sv, line:32:1, endln:40:10 |vpiParent: \_design: (work@top) |vpiFullName:work@prim_submodule |vpiParameter: \_parameter: (work@prim_submodule.PadType), line:33:18, endln:33:25 |vpiParent: - \_module: work@prim_submodule (work@prim_submodule), file:${SURELOG_DIR}/tests/ComplexParamOverload/dut.sv, line:32:1, endln:40:10 + \_module_inst: work@prim_submodule (work@prim_submodule), file:${SURELOG_DIR}/tests/ComplexParamOverload/dut.sv, line:32:1, endln:40:10 |UINT:0 |vpiTypespec: \_int_typespec: , line:33:14, endln:33:17 @@ -897,7 +897,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:33:18, endln:33:29 |vpiParent: - \_module: work@prim_submodule (work@prim_submodule), file:${SURELOG_DIR}/tests/ComplexParamOverload/dut.sv, line:32:1, endln:40:10 + \_module_inst: work@prim_submodule (work@prim_submodule), file:${SURELOG_DIR}/tests/ComplexParamOverload/dut.sv, line:32:1, endln:40:10 |vpiRhs: \_constant: , line:33:28, endln:33:29 |vpiDecompile:0 @@ -910,14 +910,14 @@ design: (work@top) \_parameter: (work@prim_submodule.PadType), line:33:18, endln:33:25 |vpiDefName:work@prim_submodule |uhdmallModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/ComplexParamOverload/dut.sv, line:65:1, endln:74:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ComplexParamOverload/dut.sv, line:65:1, endln:74:10 |vpiParent: \_design: (work@top) |vpiFullName:work@top |vpiParameter: \_parameter: (work@top.TargetCfg), line:67:24, endln:67:33 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ComplexParamOverload/dut.sv, line:65:1, endln:74:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ComplexParamOverload/dut.sv, line:65:1, endln:74:10 |UINT:20 |vpiTypespec: \_struct_typespec: (pinmux_pkg::struct2_t), line:14:12, endln:14:18 @@ -926,7 +926,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:67:24, endln:67:38 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ComplexParamOverload/dut.sv, line:65:1, endln:74:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ComplexParamOverload/dut.sv, line:65:1, endln:74:10 |vpiRhs: \_constant: , line:67:36, endln:67:38 |vpiDecompile:20 @@ -953,12 +953,12 @@ design: (work@top) \_import_typespec: (pinmux_pkg), line:66:11, endln:66:24 |vpiDefName:work@top |uhdmtopModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/ComplexParamOverload/dut.sv, line:65:1, endln:74:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ComplexParamOverload/dut.sv, line:65:1, endln:74:10 |vpiName:work@top |vpiParameter: \_parameter: (work@top.TargetCfg), line:67:24, endln:67:33 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ComplexParamOverload/dut.sv, line:65:1, endln:74:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ComplexParamOverload/dut.sv, line:65:1, endln:74:10 |UINT:20 |vpiTypespec: \_struct_typespec: (pinmux_pkg::struct2_t), line:14:12, endln:14:18 @@ -1005,7 +1005,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:67:24, endln:67:38 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ComplexParamOverload/dut.sv, line:65:1, endln:74:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ComplexParamOverload/dut.sv, line:65:1, endln:74:10 |vpiRhs: \_constant: , line:67:36, endln:67:38 |vpiDecompile:20 @@ -1031,16 +1031,16 @@ design: (work@top) |vpiDefName:work@top |vpiTop:1 |vpiTopModule:1 - |vpiModule: - \_module: work@almost_top (work@top.u_top), file:${SURELOG_DIR}/tests/ComplexParamOverload/dut.sv, line:69:4, endln:73:6 + |vpiModuleInst: + \_module_inst: work@almost_top (work@top.u_top), file:${SURELOG_DIR}/tests/ComplexParamOverload/dut.sv, line:69:4, endln:73:6 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ComplexParamOverload/dut.sv, line:65:1, endln:74:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ComplexParamOverload/dut.sv, line:65:1, endln:74:10 |vpiName:u_top |vpiFullName:work@top.u_top |vpiParameter: \_parameter: (work@top.u_top.TargetCfg), line:56:24, endln:56:33 |vpiParent: - \_module: work@almost_top (work@top.u_top), file:${SURELOG_DIR}/tests/ComplexParamOverload/dut.sv, line:69:4, endln:73:6 + \_module_inst: work@almost_top (work@top.u_top), file:${SURELOG_DIR}/tests/ComplexParamOverload/dut.sv, line:69:4, endln:73:6 |UINT:1 |vpiTypespec: \_struct_typespec: (pinmux_pkg::struct1_t), line:6:12, endln:6:18 @@ -1087,7 +1087,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:56:24, endln:56:37 |vpiParent: - \_module: work@almost_top (work@top.u_top), file:${SURELOG_DIR}/tests/ComplexParamOverload/dut.sv, line:69:4, endln:73:6 + \_module_inst: work@almost_top (work@top.u_top), file:${SURELOG_DIR}/tests/ComplexParamOverload/dut.sv, line:69:4, endln:73:6 |vpiOverriden:1 |vpiRhs: \_constant: , line:56:36, endln:56:37 @@ -1117,17 +1117,17 @@ design: (work@top) |vpiDefFile:${SURELOG_DIR}/tests/ComplexParamOverload/dut.sv |vpiDefLineNo:54 |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ComplexParamOverload/dut.sv, line:65:1, endln:74:10 - |vpiModule: - \_module: work@prim_pad_attr (work@top.u_top.u_prim_pad_attr), file:${SURELOG_DIR}/tests/ComplexParamOverload/dut.sv, line:58:4, endln:62:6 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ComplexParamOverload/dut.sv, line:65:1, endln:74:10 + |vpiModuleInst: + \_module_inst: work@prim_pad_attr (work@top.u_top.u_prim_pad_attr), file:${SURELOG_DIR}/tests/ComplexParamOverload/dut.sv, line:58:4, endln:62:6 |vpiParent: - \_module: work@almost_top (work@top.u_top), file:${SURELOG_DIR}/tests/ComplexParamOverload/dut.sv, line:69:4, endln:73:6 + \_module_inst: work@almost_top (work@top.u_top), file:${SURELOG_DIR}/tests/ComplexParamOverload/dut.sv, line:69:4, endln:73:6 |vpiName:u_prim_pad_attr |vpiFullName:work@top.u_top.u_prim_pad_attr |vpiParameter: \_parameter: (work@top.u_top.u_prim_pad_attr.TargetCfg), line:44:24, endln:44:33 |vpiParent: - \_module: work@prim_pad_attr (work@top.u_top.u_prim_pad_attr), file:${SURELOG_DIR}/tests/ComplexParamOverload/dut.sv, line:58:4, endln:62:6 + \_module_inst: work@prim_pad_attr (work@top.u_top.u_prim_pad_attr), file:${SURELOG_DIR}/tests/ComplexParamOverload/dut.sv, line:58:4, endln:62:6 |UINT:77 |vpiTypespec: \_struct_typespec: (pinmux_pkg::struct3_t), line:22:12, endln:22:18 @@ -1174,7 +1174,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.u_top.u_prim_pad_attr.PadType), line:45:18, endln:45:25 |vpiParent: - \_module: work@prim_pad_attr (work@top.u_top.u_prim_pad_attr), file:${SURELOG_DIR}/tests/ComplexParamOverload/dut.sv, line:58:4, endln:62:6 + \_module_inst: work@prim_pad_attr (work@top.u_top.u_prim_pad_attr), file:${SURELOG_DIR}/tests/ComplexParamOverload/dut.sv, line:58:4, endln:62:6 |UINT:0 |vpiTypespec: \_int_typespec: , line:45:14, endln:45:17 @@ -1187,7 +1187,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:44:24, endln:44:38 |vpiParent: - \_module: work@prim_pad_attr (work@top.u_top.u_prim_pad_attr), file:${SURELOG_DIR}/tests/ComplexParamOverload/dut.sv, line:58:4, endln:62:6 + \_module_inst: work@prim_pad_attr (work@top.u_top.u_prim_pad_attr), file:${SURELOG_DIR}/tests/ComplexParamOverload/dut.sv, line:58:4, endln:62:6 |vpiRhs: \_constant: , line:44:36, endln:44:38 |vpiDecompile:77 @@ -1199,7 +1199,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:45:18, endln:45:29 |vpiParent: - \_module: work@prim_pad_attr (work@top.u_top.u_prim_pad_attr), file:${SURELOG_DIR}/tests/ComplexParamOverload/dut.sv, line:58:4, endln:62:6 + \_module_inst: work@prim_pad_attr (work@top.u_top.u_prim_pad_attr), file:${SURELOG_DIR}/tests/ComplexParamOverload/dut.sv, line:58:4, endln:62:6 |vpiOverriden:1 |vpiRhs: \_constant: , line:45:28, endln:45:29 @@ -1229,17 +1229,17 @@ design: (work@top) |vpiDefFile:${SURELOG_DIR}/tests/ComplexParamOverload/dut.sv |vpiDefLineNo:42 |vpiInstance: - \_module: work@almost_top (work@top.u_top), file:${SURELOG_DIR}/tests/ComplexParamOverload/dut.sv, line:69:4, endln:73:6 - |vpiModule: - \_module: work@prim_submodule (work@top.u_top.u_prim_pad_attr.u_submodule), file:${SURELOG_DIR}/tests/ComplexParamOverload/dut.sv, line:47:4, endln:51:6 + \_module_inst: work@almost_top (work@top.u_top), file:${SURELOG_DIR}/tests/ComplexParamOverload/dut.sv, line:69:4, endln:73:6 + |vpiModuleInst: + \_module_inst: work@prim_submodule (work@top.u_top.u_prim_pad_attr.u_submodule), file:${SURELOG_DIR}/tests/ComplexParamOverload/dut.sv, line:47:4, endln:51:6 |vpiParent: - \_module: work@prim_pad_attr (work@top.u_top.u_prim_pad_attr), file:${SURELOG_DIR}/tests/ComplexParamOverload/dut.sv, line:58:4, endln:62:6 + \_module_inst: work@prim_pad_attr (work@top.u_top.u_prim_pad_attr), file:${SURELOG_DIR}/tests/ComplexParamOverload/dut.sv, line:58:4, endln:62:6 |vpiName:u_submodule |vpiFullName:work@top.u_top.u_prim_pad_attr.u_submodule |vpiParameter: \_parameter: (work@top.u_top.u_prim_pad_attr.u_submodule.PadType), line:33:18, endln:33:25 |vpiParent: - \_module: work@prim_submodule (work@top.u_top.u_prim_pad_attr.u_submodule), file:${SURELOG_DIR}/tests/ComplexParamOverload/dut.sv, line:47:4, endln:51:6 + \_module_inst: work@prim_submodule (work@top.u_top.u_prim_pad_attr.u_submodule), file:${SURELOG_DIR}/tests/ComplexParamOverload/dut.sv, line:47:4, endln:51:6 |UINT:0 |vpiTypespec: \_int_typespec: , line:33:14, endln:33:17 @@ -1252,7 +1252,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:33:18, endln:33:29 |vpiParent: - \_module: work@prim_submodule (work@top.u_top.u_prim_pad_attr.u_submodule), file:${SURELOG_DIR}/tests/ComplexParamOverload/dut.sv, line:47:4, endln:51:6 + \_module_inst: work@prim_submodule (work@top.u_top.u_prim_pad_attr.u_submodule), file:${SURELOG_DIR}/tests/ComplexParamOverload/dut.sv, line:47:4, endln:51:6 |vpiOverriden:1 |vpiRhs: \_constant: , line:33:28, endln:33:29 @@ -1268,17 +1268,17 @@ design: (work@top) |vpiDefFile:${SURELOG_DIR}/tests/ComplexParamOverload/dut.sv |vpiDefLineNo:32 |vpiInstance: - \_module: work@prim_pad_attr (work@top.u_top.u_prim_pad_attr), file:${SURELOG_DIR}/tests/ComplexParamOverload/dut.sv, line:58:4, endln:62:6 - |vpiModule: - \_module: work@prim_generic (work@top.u_top.u_prim_pad_attr.u_submodule.u_impl_generic), file:${SURELOG_DIR}/tests/ComplexParamOverload/dut.sv, line:35:4, endln:39:6 + \_module_inst: work@prim_pad_attr (work@top.u_top.u_prim_pad_attr), file:${SURELOG_DIR}/tests/ComplexParamOverload/dut.sv, line:58:4, endln:62:6 + |vpiModuleInst: + \_module_inst: work@prim_generic (work@top.u_top.u_prim_pad_attr.u_submodule.u_impl_generic), file:${SURELOG_DIR}/tests/ComplexParamOverload/dut.sv, line:35:4, endln:39:6 |vpiParent: - \_module: work@prim_submodule (work@top.u_top.u_prim_pad_attr.u_submodule), file:${SURELOG_DIR}/tests/ComplexParamOverload/dut.sv, line:47:4, endln:51:6 + \_module_inst: work@prim_submodule (work@top.u_top.u_prim_pad_attr.u_submodule), file:${SURELOG_DIR}/tests/ComplexParamOverload/dut.sv, line:47:4, endln:51:6 |vpiName:u_impl_generic |vpiFullName:work@top.u_top.u_prim_pad_attr.u_submodule.u_impl_generic |vpiParameter: \_parameter: (work@top.u_top.u_prim_pad_attr.u_submodule.u_impl_generic.PadTypeInGeneric), line:28:18, endln:28:34 |vpiParent: - \_module: work@prim_generic (work@top.u_top.u_prim_pad_attr.u_submodule.u_impl_generic), file:${SURELOG_DIR}/tests/ComplexParamOverload/dut.sv, line:35:4, endln:39:6 + \_module_inst: work@prim_generic (work@top.u_top.u_prim_pad_attr.u_submodule.u_impl_generic), file:${SURELOG_DIR}/tests/ComplexParamOverload/dut.sv, line:35:4, endln:39:6 |UINT:0 |vpiTypespec: \_int_typespec: , line:28:14, endln:28:17 @@ -1291,7 +1291,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:28:18, endln:28:38 |vpiParent: - \_module: work@prim_generic (work@top.u_top.u_prim_pad_attr.u_submodule.u_impl_generic), file:${SURELOG_DIR}/tests/ComplexParamOverload/dut.sv, line:35:4, endln:39:6 + \_module_inst: work@prim_generic (work@top.u_top.u_prim_pad_attr.u_submodule.u_impl_generic), file:${SURELOG_DIR}/tests/ComplexParamOverload/dut.sv, line:35:4, endln:39:6 |vpiOverriden:1 |vpiRhs: \_constant: , line:28:37, endln:28:38 @@ -1313,11 +1313,11 @@ design: (work@top) |vpiName:o |vpiNetType:1 |vpiInstance: - \_module: work@prim_submodule (work@top.u_top.u_prim_pad_attr.u_submodule), file:${SURELOG_DIR}/tests/ComplexParamOverload/dut.sv, line:47:4, endln:51:6 + \_module_inst: work@prim_submodule (work@top.u_top.u_prim_pad_attr.u_submodule), file:${SURELOG_DIR}/tests/ComplexParamOverload/dut.sv, line:47:4, endln:51:6 |vpiContAssign: \_cont_assign: , line:29:11, endln:29:31 |vpiParent: - \_module: work@prim_generic (work@top.u_top.u_prim_pad_attr.u_submodule.u_impl_generic), file:${SURELOG_DIR}/tests/ComplexParamOverload/dut.sv, line:35:4, endln:39:6 + \_module_inst: work@prim_generic (work@top.u_top.u_prim_pad_attr.u_submodule.u_impl_generic), file:${SURELOG_DIR}/tests/ComplexParamOverload/dut.sv, line:35:4, endln:39:6 |vpiRhs: \_constant: , line:28:37, endln:28:38 |vpiLhs: diff --git a/tests/ComplexParamOverload2/ComplexParamOverload2.log b/tests/ComplexParamOverload2/ComplexParamOverload2.log index a6147f191a..0368975423 100644 --- a/tests/ComplexParamOverload2/ComplexParamOverload2.log +++ b/tests/ComplexParamOverload2/ComplexParamOverload2.log @@ -387,7 +387,7 @@ import_typespec 2 int_typespec 18 int_var 2 logic_net 3 -module 22 +module_inst 22 package 3 param_assign 10 parameter 10 @@ -409,7 +409,7 @@ import_typespec 2 int_typespec 18 int_var 2 logic_net 3 -module 22 +module_inst 22 package 3 param_assign 10 parameter 10 @@ -522,7 +522,7 @@ design: (work@top) |vpiTypedef: \_enum_typespec: (pinmux_pkg::enum1_e), line:2:4, endln:4:14 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ComplexParamOverload2/dut.sv, line:57:1, endln:66:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ComplexParamOverload2/dut.sv, line:57:1, endln:66:10 |vpiName:pinmux_pkg::enum1_e |vpiInstance: \_package: pinmux_pkg (pinmux_pkg::), file:${SURELOG_DIR}/tests/ComplexParamOverload2/dut.sv, line:1:1, endln:17:24 @@ -540,7 +540,7 @@ design: (work@top) |vpiTypedef: \_enum_typespec: (pinmux_pkg::enum2_e), line:10:4, endln:12:14 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ComplexParamOverload2/dut.sv, line:57:1, endln:66:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ComplexParamOverload2/dut.sv, line:57:1, endln:66:10 |vpiName:pinmux_pkg::enum2_e |vpiInstance: \_package: pinmux_pkg (pinmux_pkg::), file:${SURELOG_DIR}/tests/ComplexParamOverload2/dut.sv, line:1:1, endln:17:24 @@ -558,7 +558,7 @@ design: (work@top) |vpiTypedef: \_struct_typespec: (pinmux_pkg::struct1_t), line:6:12, endln:6:18 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ComplexParamOverload2/dut.sv, line:57:1, endln:66:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ComplexParamOverload2/dut.sv, line:57:1, endln:66:10 |vpiName:pinmux_pkg::struct1_t |vpiInstance: \_package: pinmux_pkg (pinmux_pkg::), file:${SURELOG_DIR}/tests/ComplexParamOverload2/dut.sv, line:1:1, endln:17:24 @@ -578,7 +578,7 @@ design: (work@top) |vpiTypedef: \_struct_typespec: (pinmux_pkg::struct2_t), line:14:12, endln:14:18 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ComplexParamOverload2/dut.sv, line:57:1, endln:66:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ComplexParamOverload2/dut.sv, line:57:1, endln:66:10 |vpiName:pinmux_pkg::struct2_t |vpiInstance: \_package: pinmux_pkg (pinmux_pkg::), file:${SURELOG_DIR}/tests/ComplexParamOverload2/dut.sv, line:1:1, endln:17:24 @@ -598,14 +598,14 @@ design: (work@top) |vpiDefName:pinmux_pkg |vpiTop:1 |uhdmallModules: -\_module: work@almost_top (work@almost_top), file:${SURELOG_DIR}/tests/ComplexParamOverload2/dut.sv, line:46:1, endln:55:10 +\_module_inst: work@almost_top (work@almost_top), file:${SURELOG_DIR}/tests/ComplexParamOverload2/dut.sv, line:46:1, endln:55:10 |vpiParent: \_design: (work@top) |vpiFullName:work@almost_top |vpiParameter: \_parameter: (work@almost_top.TargetCfg), line:48:24, endln:48:33 |vpiParent: - \_module: work@almost_top (work@almost_top), file:${SURELOG_DIR}/tests/ComplexParamOverload2/dut.sv, line:46:1, endln:55:10 + \_module_inst: work@almost_top (work@almost_top), file:${SURELOG_DIR}/tests/ComplexParamOverload2/dut.sv, line:46:1, endln:55:10 |UINT:1 |vpiTypespec: \_struct_typespec: (pinmux_pkg::struct1_t), line:6:12, endln:6:18 @@ -614,7 +614,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:48:24, endln:48:37 |vpiParent: - \_module: work@almost_top (work@almost_top), file:${SURELOG_DIR}/tests/ComplexParamOverload2/dut.sv, line:46:1, endln:55:10 + \_module_inst: work@almost_top (work@almost_top), file:${SURELOG_DIR}/tests/ComplexParamOverload2/dut.sv, line:46:1, endln:55:10 |vpiRhs: \_constant: , line:48:36, endln:48:37 |vpiDecompile:1 @@ -637,14 +637,14 @@ design: (work@top) \_import_typespec: (pinmux_pkg), line:47:11, endln:47:24 |vpiDefName:work@almost_top |uhdmallModules: -\_module: work@prim_generic_pad_attr (work@prim_generic_pad_attr), file:${SURELOG_DIR}/tests/ComplexParamOverload2/dut.sv, line:19:1, endln:22:34 +\_module_inst: work@prim_generic_pad_attr (work@prim_generic_pad_attr), file:${SURELOG_DIR}/tests/ComplexParamOverload2/dut.sv, line:19:1, endln:22:34 |vpiParent: \_design: (work@top) |vpiFullName:work@prim_generic_pad_attr |vpiParameter: \_parameter: (work@prim_generic_pad_attr.PadTypeInGeneric), line:20:18, endln:20:34 |vpiParent: - \_module: work@prim_generic_pad_attr (work@prim_generic_pad_attr), file:${SURELOG_DIR}/tests/ComplexParamOverload2/dut.sv, line:19:1, endln:22:34 + \_module_inst: work@prim_generic_pad_attr (work@prim_generic_pad_attr), file:${SURELOG_DIR}/tests/ComplexParamOverload2/dut.sv, line:19:1, endln:22:34 |UINT:0 |vpiTypespec: \_int_typespec: , line:20:14, endln:20:17 @@ -657,7 +657,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:20:18, endln:20:38 |vpiParent: - \_module: work@prim_generic_pad_attr (work@prim_generic_pad_attr), file:${SURELOG_DIR}/tests/ComplexParamOverload2/dut.sv, line:19:1, endln:22:34 + \_module_inst: work@prim_generic_pad_attr (work@prim_generic_pad_attr), file:${SURELOG_DIR}/tests/ComplexParamOverload2/dut.sv, line:19:1, endln:22:34 |vpiRhs: \_constant: , line:20:37, endln:20:38 |vpiDecompile:0 @@ -672,13 +672,13 @@ design: (work@top) |vpiNet: \_logic_net: (work@prim_generic_pad_attr.o), line:19:41, endln:19:42 |vpiParent: - \_module: work@prim_generic_pad_attr (work@prim_generic_pad_attr), file:${SURELOG_DIR}/tests/ComplexParamOverload2/dut.sv, line:19:1, endln:22:34 + \_module_inst: work@prim_generic_pad_attr (work@prim_generic_pad_attr), file:${SURELOG_DIR}/tests/ComplexParamOverload2/dut.sv, line:19:1, endln:22:34 |vpiName:o |vpiFullName:work@prim_generic_pad_attr.o |vpiPort: \_port: (o), line:19:41, endln:19:42 |vpiParent: - \_module: work@prim_generic_pad_attr (work@prim_generic_pad_attr), file:${SURELOG_DIR}/tests/ComplexParamOverload2/dut.sv, line:19:1, endln:22:34 + \_module_inst: work@prim_generic_pad_attr (work@prim_generic_pad_attr), file:${SURELOG_DIR}/tests/ComplexParamOverload2/dut.sv, line:19:1, endln:22:34 |vpiName:o |vpiDirection:2 |vpiLowConn: @@ -691,7 +691,7 @@ design: (work@top) |vpiContAssign: \_cont_assign: , line:21:11, endln:21:31 |vpiParent: - \_module: work@prim_generic_pad_attr (work@prim_generic_pad_attr), file:${SURELOG_DIR}/tests/ComplexParamOverload2/dut.sv, line:19:1, endln:22:34 + \_module_inst: work@prim_generic_pad_attr (work@prim_generic_pad_attr), file:${SURELOG_DIR}/tests/ComplexParamOverload2/dut.sv, line:19:1, endln:22:34 |vpiRhs: \_ref_obj: (work@prim_generic_pad_attr.PadTypeInGeneric), line:21:15, endln:21:31 |vpiParent: @@ -707,14 +707,14 @@ design: (work@top) |vpiActual: \_int_var: (work@top.u_top.u_prim_pad_attr.u_submodule.u_impl_generic.o), line:19:41, endln:19:42 |uhdmallModules: -\_module: work@prim_pad_attr (work@prim_pad_attr), file:${SURELOG_DIR}/tests/ComplexParamOverload2/dut.sv, line:35:1, endln:44:10 +\_module_inst: work@prim_pad_attr (work@prim_pad_attr), file:${SURELOG_DIR}/tests/ComplexParamOverload2/dut.sv, line:35:1, endln:44:10 |vpiParent: \_design: (work@top) |vpiFullName:work@prim_pad_attr |vpiParameter: \_parameter: (work@prim_pad_attr.PadType), line:36:18, endln:36:25 |vpiParent: - \_module: work@prim_pad_attr (work@prim_pad_attr), file:${SURELOG_DIR}/tests/ComplexParamOverload2/dut.sv, line:35:1, endln:44:10 + \_module_inst: work@prim_pad_attr (work@prim_pad_attr), file:${SURELOG_DIR}/tests/ComplexParamOverload2/dut.sv, line:35:1, endln:44:10 |UINT:0 |vpiTypespec: \_int_typespec: , line:36:14, endln:36:17 @@ -727,7 +727,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:36:18, endln:36:29 |vpiParent: - \_module: work@prim_pad_attr (work@prim_pad_attr), file:${SURELOG_DIR}/tests/ComplexParamOverload2/dut.sv, line:35:1, endln:44:10 + \_module_inst: work@prim_pad_attr (work@prim_pad_attr), file:${SURELOG_DIR}/tests/ComplexParamOverload2/dut.sv, line:35:1, endln:44:10 |vpiRhs: \_constant: , line:36:28, endln:36:29 |vpiDecompile:0 @@ -740,14 +740,14 @@ design: (work@top) \_parameter: (work@prim_pad_attr.PadType), line:36:18, endln:36:25 |vpiDefName:work@prim_pad_attr |uhdmallModules: -\_module: work@prim_submodule (work@prim_submodule), file:${SURELOG_DIR}/tests/ComplexParamOverload2/dut.sv, line:24:1, endln:32:10 +\_module_inst: work@prim_submodule (work@prim_submodule), file:${SURELOG_DIR}/tests/ComplexParamOverload2/dut.sv, line:24:1, endln:32:10 |vpiParent: \_design: (work@top) |vpiFullName:work@prim_submodule |vpiParameter: \_parameter: (work@prim_submodule.PadType), line:25:18, endln:25:25 |vpiParent: - \_module: work@prim_submodule (work@prim_submodule), file:${SURELOG_DIR}/tests/ComplexParamOverload2/dut.sv, line:24:1, endln:32:10 + \_module_inst: work@prim_submodule (work@prim_submodule), file:${SURELOG_DIR}/tests/ComplexParamOverload2/dut.sv, line:24:1, endln:32:10 |UINT:0 |vpiTypespec: \_int_typespec: , line:25:14, endln:25:17 @@ -760,7 +760,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:25:18, endln:25:29 |vpiParent: - \_module: work@prim_submodule (work@prim_submodule), file:${SURELOG_DIR}/tests/ComplexParamOverload2/dut.sv, line:24:1, endln:32:10 + \_module_inst: work@prim_submodule (work@prim_submodule), file:${SURELOG_DIR}/tests/ComplexParamOverload2/dut.sv, line:24:1, endln:32:10 |vpiRhs: \_constant: , line:25:28, endln:25:29 |vpiDecompile:0 @@ -775,13 +775,13 @@ design: (work@top) |vpiNet: \_logic_net: (work@prim_submodule.o), line:24:34, endln:24:35 |vpiParent: - \_module: work@prim_submodule (work@prim_submodule), file:${SURELOG_DIR}/tests/ComplexParamOverload2/dut.sv, line:24:1, endln:32:10 + \_module_inst: work@prim_submodule (work@prim_submodule), file:${SURELOG_DIR}/tests/ComplexParamOverload2/dut.sv, line:24:1, endln:32:10 |vpiName:o |vpiFullName:work@prim_submodule.o |vpiPort: \_port: (o), line:24:34, endln:24:35 |vpiParent: - \_module: work@prim_submodule (work@prim_submodule), file:${SURELOG_DIR}/tests/ComplexParamOverload2/dut.sv, line:24:1, endln:32:10 + \_module_inst: work@prim_submodule (work@prim_submodule), file:${SURELOG_DIR}/tests/ComplexParamOverload2/dut.sv, line:24:1, endln:32:10 |vpiName:o |vpiDirection:2 |vpiLowConn: @@ -792,14 +792,14 @@ design: (work@top) \_int_typespec: , line:24:30, endln:24:33 |vpiSigned:1 |uhdmallModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/ComplexParamOverload2/dut.sv, line:57:1, endln:66:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ComplexParamOverload2/dut.sv, line:57:1, endln:66:10 |vpiParent: \_design: (work@top) |vpiFullName:work@top |vpiParameter: \_parameter: (work@top.TargetCfg), line:59:24, endln:59:33 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ComplexParamOverload2/dut.sv, line:57:1, endln:66:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ComplexParamOverload2/dut.sv, line:57:1, endln:66:10 |UINT:2 |vpiTypespec: \_struct_typespec: (pinmux_pkg::struct2_t), line:14:12, endln:14:18 @@ -808,7 +808,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:59:24, endln:59:37 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ComplexParamOverload2/dut.sv, line:57:1, endln:66:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ComplexParamOverload2/dut.sv, line:57:1, endln:66:10 |vpiRhs: \_constant: , line:59:36, endln:59:37 |vpiDecompile:2 @@ -831,12 +831,12 @@ design: (work@top) \_import_typespec: (pinmux_pkg), line:58:11, endln:58:24 |vpiDefName:work@top |uhdmtopModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/ComplexParamOverload2/dut.sv, line:57:1, endln:66:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ComplexParamOverload2/dut.sv, line:57:1, endln:66:10 |vpiName:work@top |vpiParameter: \_parameter: (work@top.TargetCfg), line:59:24, endln:59:33 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ComplexParamOverload2/dut.sv, line:57:1, endln:66:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ComplexParamOverload2/dut.sv, line:57:1, endln:66:10 |UINT:2 |vpiTypespec: \_struct_typespec: (pinmux_pkg::struct2_t), line:14:12, endln:14:18 @@ -883,7 +883,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:59:24, endln:59:37 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ComplexParamOverload2/dut.sv, line:57:1, endln:66:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ComplexParamOverload2/dut.sv, line:57:1, endln:66:10 |vpiRhs: \_constant: , line:59:36, endln:59:37 |vpiDecompile:2 @@ -905,16 +905,16 @@ design: (work@top) |vpiDefName:work@top |vpiTop:1 |vpiTopModule:1 - |vpiModule: - \_module: work@almost_top (work@top.u_top), file:${SURELOG_DIR}/tests/ComplexParamOverload2/dut.sv, line:61:4, endln:65:6 + |vpiModuleInst: + \_module_inst: work@almost_top (work@top.u_top), file:${SURELOG_DIR}/tests/ComplexParamOverload2/dut.sv, line:61:4, endln:65:6 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ComplexParamOverload2/dut.sv, line:57:1, endln:66:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ComplexParamOverload2/dut.sv, line:57:1, endln:66:10 |vpiName:u_top |vpiFullName:work@top.u_top |vpiParameter: \_parameter: (work@top.u_top.TargetCfg), line:48:24, endln:48:33 |vpiParent: - \_module: work@almost_top (work@top.u_top), file:${SURELOG_DIR}/tests/ComplexParamOverload2/dut.sv, line:61:4, endln:65:6 + \_module_inst: work@almost_top (work@top.u_top), file:${SURELOG_DIR}/tests/ComplexParamOverload2/dut.sv, line:61:4, endln:65:6 |UINT:1 |vpiTypespec: \_struct_typespec: (pinmux_pkg::struct1_t), line:6:12, endln:6:18 @@ -961,7 +961,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:48:24, endln:48:37 |vpiParent: - \_module: work@almost_top (work@top.u_top), file:${SURELOG_DIR}/tests/ComplexParamOverload2/dut.sv, line:61:4, endln:65:6 + \_module_inst: work@almost_top (work@top.u_top), file:${SURELOG_DIR}/tests/ComplexParamOverload2/dut.sv, line:61:4, endln:65:6 |vpiRhs: \_constant: , line:48:36, endln:48:37 |vpiDecompile:1 @@ -984,17 +984,17 @@ design: (work@top) |vpiDefFile:${SURELOG_DIR}/tests/ComplexParamOverload2/dut.sv |vpiDefLineNo:46 |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ComplexParamOverload2/dut.sv, line:57:1, endln:66:10 - |vpiModule: - \_module: work@prim_pad_attr (work@top.u_top.u_prim_pad_attr), file:${SURELOG_DIR}/tests/ComplexParamOverload2/dut.sv, line:50:4, endln:54:6 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ComplexParamOverload2/dut.sv, line:57:1, endln:66:10 + |vpiModuleInst: + \_module_inst: work@prim_pad_attr (work@top.u_top.u_prim_pad_attr), file:${SURELOG_DIR}/tests/ComplexParamOverload2/dut.sv, line:50:4, endln:54:6 |vpiParent: - \_module: work@almost_top (work@top.u_top), file:${SURELOG_DIR}/tests/ComplexParamOverload2/dut.sv, line:61:4, endln:65:6 + \_module_inst: work@almost_top (work@top.u_top), file:${SURELOG_DIR}/tests/ComplexParamOverload2/dut.sv, line:61:4, endln:65:6 |vpiName:u_prim_pad_attr |vpiFullName:work@top.u_top.u_prim_pad_attr |vpiParameter: \_parameter: (work@top.u_top.u_prim_pad_attr.PadType), line:36:18, endln:36:25 |vpiParent: - \_module: work@prim_pad_attr (work@top.u_top.u_prim_pad_attr), file:${SURELOG_DIR}/tests/ComplexParamOverload2/dut.sv, line:50:4, endln:54:6 + \_module_inst: work@prim_pad_attr (work@top.u_top.u_prim_pad_attr), file:${SURELOG_DIR}/tests/ComplexParamOverload2/dut.sv, line:50:4, endln:54:6 |UINT:0 |vpiTypespec: \_int_typespec: , line:36:14, endln:36:17 @@ -1007,7 +1007,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:36:18, endln:36:29 |vpiParent: - \_module: work@prim_pad_attr (work@top.u_top.u_prim_pad_attr), file:${SURELOG_DIR}/tests/ComplexParamOverload2/dut.sv, line:50:4, endln:54:6 + \_module_inst: work@prim_pad_attr (work@top.u_top.u_prim_pad_attr), file:${SURELOG_DIR}/tests/ComplexParamOverload2/dut.sv, line:50:4, endln:54:6 |vpiOverriden:1 |vpiRhs: \_constant: , line:36:28, endln:36:29 @@ -1025,22 +1025,22 @@ design: (work@top) |vpiNet: \_logic_net: (work@top.u_top.u_prim_pad_attr.o), line:41:10, endln:41:11 |vpiParent: - \_module: work@prim_pad_attr (work@top.u_top.u_prim_pad_attr), file:${SURELOG_DIR}/tests/ComplexParamOverload2/dut.sv, line:50:4, endln:54:6 + \_module_inst: work@prim_pad_attr (work@top.u_top.u_prim_pad_attr), file:${SURELOG_DIR}/tests/ComplexParamOverload2/dut.sv, line:50:4, endln:54:6 |vpiName:o |vpiFullName:work@top.u_top.u_prim_pad_attr.o |vpiNetType:1 |vpiInstance: - \_module: work@almost_top (work@top.u_top), file:${SURELOG_DIR}/tests/ComplexParamOverload2/dut.sv, line:61:4, endln:65:6 - |vpiModule: - \_module: work@prim_submodule (work@top.u_top.u_prim_pad_attr.u_submodule), file:${SURELOG_DIR}/tests/ComplexParamOverload2/dut.sv, line:38:4, endln:42:6 + \_module_inst: work@almost_top (work@top.u_top), file:${SURELOG_DIR}/tests/ComplexParamOverload2/dut.sv, line:61:4, endln:65:6 + |vpiModuleInst: + \_module_inst: work@prim_submodule (work@top.u_top.u_prim_pad_attr.u_submodule), file:${SURELOG_DIR}/tests/ComplexParamOverload2/dut.sv, line:38:4, endln:42:6 |vpiParent: - \_module: work@prim_pad_attr (work@top.u_top.u_prim_pad_attr), file:${SURELOG_DIR}/tests/ComplexParamOverload2/dut.sv, line:50:4, endln:54:6 + \_module_inst: work@prim_pad_attr (work@top.u_top.u_prim_pad_attr), file:${SURELOG_DIR}/tests/ComplexParamOverload2/dut.sv, line:50:4, endln:54:6 |vpiName:u_submodule |vpiFullName:work@top.u_top.u_prim_pad_attr.u_submodule |vpiVariables: \_int_var: (work@top.u_top.u_prim_pad_attr.u_submodule.o), line:24:34, endln:24:35 |vpiParent: - \_module: work@prim_submodule (work@top.u_top.u_prim_pad_attr.u_submodule), file:${SURELOG_DIR}/tests/ComplexParamOverload2/dut.sv, line:38:4, endln:42:6 + \_module_inst: work@prim_submodule (work@top.u_top.u_prim_pad_attr.u_submodule), file:${SURELOG_DIR}/tests/ComplexParamOverload2/dut.sv, line:38:4, endln:42:6 |vpiTypespec: \_int_typespec: , line:24:30, endln:24:33 |vpiSigned:1 @@ -1051,7 +1051,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.u_top.u_prim_pad_attr.u_submodule.PadType), line:25:18, endln:25:25 |vpiParent: - \_module: work@prim_submodule (work@top.u_top.u_prim_pad_attr.u_submodule), file:${SURELOG_DIR}/tests/ComplexParamOverload2/dut.sv, line:38:4, endln:42:6 + \_module_inst: work@prim_submodule (work@top.u_top.u_prim_pad_attr.u_submodule), file:${SURELOG_DIR}/tests/ComplexParamOverload2/dut.sv, line:38:4, endln:42:6 |UINT:0 |vpiTypespec: \_int_typespec: , line:25:14, endln:25:17 @@ -1064,7 +1064,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:25:18, endln:25:29 |vpiParent: - \_module: work@prim_submodule (work@top.u_top.u_prim_pad_attr.u_submodule), file:${SURELOG_DIR}/tests/ComplexParamOverload2/dut.sv, line:38:4, endln:42:6 + \_module_inst: work@prim_submodule (work@top.u_top.u_prim_pad_attr.u_submodule), file:${SURELOG_DIR}/tests/ComplexParamOverload2/dut.sv, line:38:4, endln:42:6 |vpiOverriden:1 |vpiRhs: \_constant: , line:25:28, endln:25:29 @@ -1080,11 +1080,11 @@ design: (work@top) |vpiDefFile:${SURELOG_DIR}/tests/ComplexParamOverload2/dut.sv |vpiDefLineNo:24 |vpiInstance: - \_module: work@prim_pad_attr (work@top.u_top.u_prim_pad_attr), file:${SURELOG_DIR}/tests/ComplexParamOverload2/dut.sv, line:50:4, endln:54:6 + \_module_inst: work@prim_pad_attr (work@top.u_top.u_prim_pad_attr), file:${SURELOG_DIR}/tests/ComplexParamOverload2/dut.sv, line:50:4, endln:54:6 |vpiPort: \_port: (o), line:24:34, endln:24:35 |vpiParent: - \_module: work@prim_submodule (work@top.u_top.u_prim_pad_attr.u_submodule), file:${SURELOG_DIR}/tests/ComplexParamOverload2/dut.sv, line:38:4, endln:42:6 + \_module_inst: work@prim_submodule (work@top.u_top.u_prim_pad_attr.u_submodule), file:${SURELOG_DIR}/tests/ComplexParamOverload2/dut.sv, line:38:4, endln:42:6 |vpiName:o |vpiDirection:2 |vpiHighConn: @@ -1107,17 +1107,17 @@ design: (work@top) \_int_typespec: , line:24:30, endln:24:33 |vpiSigned:1 |vpiInstance: - \_module: work@prim_submodule (work@top.u_top.u_prim_pad_attr.u_submodule), file:${SURELOG_DIR}/tests/ComplexParamOverload2/dut.sv, line:38:4, endln:42:6 - |vpiModule: - \_module: work@prim_generic_pad_attr (work@top.u_top.u_prim_pad_attr.u_submodule.u_impl_generic), file:${SURELOG_DIR}/tests/ComplexParamOverload2/dut.sv, line:27:4, endln:31:6 + \_module_inst: work@prim_submodule (work@top.u_top.u_prim_pad_attr.u_submodule), file:${SURELOG_DIR}/tests/ComplexParamOverload2/dut.sv, line:38:4, endln:42:6 + |vpiModuleInst: + \_module_inst: work@prim_generic_pad_attr (work@top.u_top.u_prim_pad_attr.u_submodule.u_impl_generic), file:${SURELOG_DIR}/tests/ComplexParamOverload2/dut.sv, line:27:4, endln:31:6 |vpiParent: - \_module: work@prim_submodule (work@top.u_top.u_prim_pad_attr.u_submodule), file:${SURELOG_DIR}/tests/ComplexParamOverload2/dut.sv, line:38:4, endln:42:6 + \_module_inst: work@prim_submodule (work@top.u_top.u_prim_pad_attr.u_submodule), file:${SURELOG_DIR}/tests/ComplexParamOverload2/dut.sv, line:38:4, endln:42:6 |vpiName:u_impl_generic |vpiFullName:work@top.u_top.u_prim_pad_attr.u_submodule.u_impl_generic |vpiVariables: \_int_var: (work@top.u_top.u_prim_pad_attr.u_submodule.u_impl_generic.o), line:19:41, endln:19:42 |vpiParent: - \_module: work@prim_generic_pad_attr (work@top.u_top.u_prim_pad_attr.u_submodule.u_impl_generic), file:${SURELOG_DIR}/tests/ComplexParamOverload2/dut.sv, line:27:4, endln:31:6 + \_module_inst: work@prim_generic_pad_attr (work@top.u_top.u_prim_pad_attr.u_submodule.u_impl_generic), file:${SURELOG_DIR}/tests/ComplexParamOverload2/dut.sv, line:27:4, endln:31:6 |vpiTypespec: \_int_typespec: , line:19:37, endln:19:40 |vpiSigned:1 @@ -1128,7 +1128,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.u_top.u_prim_pad_attr.u_submodule.u_impl_generic.PadTypeInGeneric), line:20:18, endln:20:34 |vpiParent: - \_module: work@prim_generic_pad_attr (work@top.u_top.u_prim_pad_attr.u_submodule.u_impl_generic), file:${SURELOG_DIR}/tests/ComplexParamOverload2/dut.sv, line:27:4, endln:31:6 + \_module_inst: work@prim_generic_pad_attr (work@top.u_top.u_prim_pad_attr.u_submodule.u_impl_generic), file:${SURELOG_DIR}/tests/ComplexParamOverload2/dut.sv, line:27:4, endln:31:6 |UINT:0 |vpiTypespec: \_int_typespec: , line:20:14, endln:20:17 @@ -1141,7 +1141,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:20:18, endln:20:38 |vpiParent: - \_module: work@prim_generic_pad_attr (work@top.u_top.u_prim_pad_attr.u_submodule.u_impl_generic), file:${SURELOG_DIR}/tests/ComplexParamOverload2/dut.sv, line:27:4, endln:31:6 + \_module_inst: work@prim_generic_pad_attr (work@top.u_top.u_prim_pad_attr.u_submodule.u_impl_generic), file:${SURELOG_DIR}/tests/ComplexParamOverload2/dut.sv, line:27:4, endln:31:6 |vpiOverriden:1 |vpiRhs: \_constant: , line:20:37, endln:20:38 @@ -1159,11 +1159,11 @@ design: (work@top) |vpiDefFile:${SURELOG_DIR}/tests/ComplexParamOverload2/dut.sv |vpiDefLineNo:19 |vpiInstance: - \_module: work@prim_submodule (work@top.u_top.u_prim_pad_attr.u_submodule), file:${SURELOG_DIR}/tests/ComplexParamOverload2/dut.sv, line:38:4, endln:42:6 + \_module_inst: work@prim_submodule (work@top.u_top.u_prim_pad_attr.u_submodule), file:${SURELOG_DIR}/tests/ComplexParamOverload2/dut.sv, line:38:4, endln:42:6 |vpiPort: \_port: (o), line:19:41, endln:19:42 |vpiParent: - \_module: work@prim_generic_pad_attr (work@top.u_top.u_prim_pad_attr.u_submodule.u_impl_generic), file:${SURELOG_DIR}/tests/ComplexParamOverload2/dut.sv, line:27:4, endln:31:6 + \_module_inst: work@prim_generic_pad_attr (work@top.u_top.u_prim_pad_attr.u_submodule.u_impl_generic), file:${SURELOG_DIR}/tests/ComplexParamOverload2/dut.sv, line:27:4, endln:31:6 |vpiName:o |vpiDirection:2 |vpiHighConn: @@ -1186,11 +1186,11 @@ design: (work@top) \_int_typespec: , line:19:37, endln:19:40 |vpiSigned:1 |vpiInstance: - \_module: work@prim_generic_pad_attr (work@top.u_top.u_prim_pad_attr.u_submodule.u_impl_generic), file:${SURELOG_DIR}/tests/ComplexParamOverload2/dut.sv, line:27:4, endln:31:6 + \_module_inst: work@prim_generic_pad_attr (work@top.u_top.u_prim_pad_attr.u_submodule.u_impl_generic), file:${SURELOG_DIR}/tests/ComplexParamOverload2/dut.sv, line:27:4, endln:31:6 |vpiContAssign: \_cont_assign: , line:21:11, endln:21:31 |vpiParent: - \_module: work@prim_generic_pad_attr (work@top.u_top.u_prim_pad_attr.u_submodule.u_impl_generic), file:${SURELOG_DIR}/tests/ComplexParamOverload2/dut.sv, line:27:4, endln:31:6 + \_module_inst: work@prim_generic_pad_attr (work@top.u_top.u_prim_pad_attr.u_submodule.u_impl_generic), file:${SURELOG_DIR}/tests/ComplexParamOverload2/dut.sv, line:27:4, endln:31:6 |vpiRhs: \_constant: , line:20:37, endln:20:38 |vpiLhs: diff --git a/tests/ComplexVarSelect/ComplexVarSelect.log b/tests/ComplexVarSelect/ComplexVarSelect.log index 50dee4941e..e0a6d51b8d 100644 --- a/tests/ComplexVarSelect/ComplexVarSelect.log +++ b/tests/ComplexVarSelect/ComplexVarSelect.log @@ -198,7 +198,7 @@ design 1 logic_net 4 logic_typespec 4 logic_var 4 -module 3 +module_inst 3 part_select 3 range 10 ref_obj 4 @@ -213,7 +213,7 @@ design 1 logic_net 4 logic_typespec 4 logic_var 4 -module 3 +module_inst 3 part_select 3 range 10 ref_obj 4 @@ -232,7 +232,7 @@ design: (work@top) |vpiElaborated:1 |vpiName:work@top |uhdmallModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/ComplexVarSelect/dut.sv, line:1:1, endln:7:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ComplexVarSelect/dut.sv, line:1:1, endln:7:10 |vpiParent: \_design: (work@top) |vpiFullName:work@top @@ -240,38 +240,38 @@ design: (work@top) |vpiNet: \_logic_net: (work@top.iccm_bank_dout_hi), line:2:21, endln:2:38 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ComplexVarSelect/dut.sv, line:1:1, endln:7:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ComplexVarSelect/dut.sv, line:1:1, endln:7:10 |vpiName:iccm_bank_dout_hi |vpiFullName:work@top.iccm_bank_dout_hi |vpiNetType:36 |vpiNet: \_logic_net: (work@top.iccm_rw_addr_q), line:3:16, endln:3:30 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ComplexVarSelect/dut.sv, line:1:1, endln:7:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ComplexVarSelect/dut.sv, line:1:1, endln:7:10 |vpiName:iccm_rw_addr_q |vpiFullName:work@top.iccm_rw_addr_q |vpiNetType:36 |vpiNet: \_logic_net: (work@top.x), line:5:16, endln:5:17 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ComplexVarSelect/dut.sv, line:1:1, endln:7:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ComplexVarSelect/dut.sv, line:1:1, endln:7:10 |vpiName:x |vpiFullName:work@top.x |vpiNetType:36 |vpiNet: \_logic_net: (work@top.y), line:6:16, endln:6:17 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ComplexVarSelect/dut.sv, line:1:1, endln:7:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ComplexVarSelect/dut.sv, line:1:1, endln:7:10 |vpiName:y |vpiFullName:work@top.y |vpiNetType:36 |uhdmtopModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/ComplexVarSelect/dut.sv, line:1:1, endln:7:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ComplexVarSelect/dut.sv, line:1:1, endln:7:10 |vpiName:work@top |vpiVariables: \_logic_var: (work@top.iccm_bank_dout_hi), line:2:21, endln:2:48 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ComplexVarSelect/dut.sv, line:1:1, endln:7:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ComplexVarSelect/dut.sv, line:1:1, endln:7:10 |vpiTypespec: \_logic_typespec: , line:2:4, endln:2:20 |vpiRange: @@ -358,7 +358,7 @@ design: (work@top) |vpiVariables: \_logic_var: (work@top.iccm_rw_addr_q), line:3:16, endln:3:38 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ComplexVarSelect/dut.sv, line:1:1, endln:7:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ComplexVarSelect/dut.sv, line:1:1, endln:7:10 |vpiTypespec: \_logic_typespec: , line:3:4, endln:3:15 |vpiRange: @@ -409,7 +409,7 @@ design: (work@top) |vpiVariables: \_logic_var: (work@top.x), line:5:16, endln:5:63 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ComplexVarSelect/dut.sv, line:1:1, endln:7:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ComplexVarSelect/dut.sv, line:1:1, endln:7:10 |vpiTypespec: \_logic_typespec: , line:5:4, endln:5:15 |vpiRange: @@ -493,7 +493,7 @@ design: (work@top) |vpiVariables: \_logic_var: (work@top.y), line:6:16, endln:6:58 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ComplexVarSelect/dut.sv, line:1:1, endln:7:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ComplexVarSelect/dut.sv, line:1:1, endln:7:10 |vpiTypespec: \_logic_typespec: , line:6:4, endln:6:15 |vpiRange: diff --git a/tests/ConcatOrder/ConcatOrder.log b/tests/ConcatOrder/ConcatOrder.log index 39db4430cf..d2d288775b 100644 --- a/tests/ConcatOrder/ConcatOrder.log +++ b/tests/ConcatOrder/ConcatOrder.log @@ -366,7 +366,7 @@ hier_path 2 import_typespec 1 int_typespec 17 integer_typespec 34 -module 8 +module_inst 8 operation 50 package 3 packed_array_typespec 8 @@ -395,7 +395,7 @@ hier_path 2 import_typespec 1 int_typespec 17 integer_typespec 34 -module 9 +module_inst 9 operation 50 package 3 packed_array_typespec 8 @@ -764,7 +764,7 @@ design: (work@testbench) |vpiTypespec: \_struct_typespec: (bp_common_pkg::bp_proc_param_s), line:5:10, endln:5:16 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/ConcatOrder/dut.sv, line:39:2, endln:54:11 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/ConcatOrder/dut.sv, line:39:2, endln:54:11 |vpiName:bp_common_pkg::bp_proc_param_s |vpiInstance: \_package: bp_common_pkg (bp_common_pkg::), file:${SURELOG_DIR}/tests/ConcatOrder/dut.sv, line:1:1, endln:32:11 @@ -944,7 +944,7 @@ design: (work@testbench) |vpiTypedef: \_enum_typespec: (bp_common_pkg::bp_params_e), line:19:3, endln:23:17 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/ConcatOrder/dut.sv, line:39:2, endln:54:11 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/ConcatOrder/dut.sv, line:39:2, endln:54:11 |vpiName:bp_common_pkg::bp_params_e |vpiInstance: \_package: bp_common_pkg (bp_common_pkg::), file:${SURELOG_DIR}/tests/ConcatOrder/dut.sv, line:1:1, endln:32:11 @@ -988,20 +988,20 @@ design: (work@testbench) |vpiDefName:bp_common_pkg |vpiTop:1 |uhdmallModules: -\_module: work@GOOD (work@GOOD), file:${SURELOG_DIR}/tests/ConcatOrder/dut.sv, line:35:1, endln:37:10 +\_module_inst: work@GOOD (work@GOOD), file:${SURELOG_DIR}/tests/ConcatOrder/dut.sv, line:35:1, endln:37:10 |vpiParent: \_design: (work@testbench) |vpiFullName:work@GOOD |vpiDefName:work@GOOD |uhdmallModules: -\_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/ConcatOrder/dut.sv, line:39:2, endln:54:11 +\_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/ConcatOrder/dut.sv, line:39:2, endln:54:11 |vpiParent: \_design: (work@testbench) |vpiFullName:work@testbench |vpiParameter: \_parameter: (work@testbench.all_cfgs_gp), line:13:42, endln:13:53 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/ConcatOrder/dut.sv, line:39:2, endln:54:11 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/ConcatOrder/dut.sv, line:39:2, endln:54:11 |vpiTypespec: \_packed_array_typespec: , line:13:11, endln:13:26 |vpiParent: @@ -1058,7 +1058,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.bp_default_cfg_p), line:25:28, endln:25:44 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/ConcatOrder/dut.sv, line:39:2, endln:54:11 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/ConcatOrder/dut.sv, line:39:2, endln:54:11 |vpiTypespec: \_struct_typespec: (bp_common_pkg::bp_proc_param_s), line:5:10, endln:5:16 |vpiParent: @@ -1090,7 +1090,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.bp_multicore_1_cce_ucode_cfg_p), line:10:31, endln:10:61 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/ConcatOrder/dut.sv, line:39:2, endln:54:11 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/ConcatOrder/dut.sv, line:39:2, endln:54:11 |vpiTypespec: \_struct_typespec: (bp_common_pkg::bp_proc_param_s), line:5:10, endln:5:16 |vpiParent: @@ -1122,7 +1122,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.bp_unicore_cfg_p), line:30:28, endln:30:44 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/ConcatOrder/dut.sv, line:39:2, endln:54:11 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/ConcatOrder/dut.sv, line:39:2, endln:54:11 |vpiTypespec: \_struct_typespec: (bp_common_pkg::bp_proc_param_s), line:5:10, endln:5:16 |vpiParent: @@ -1154,7 +1154,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.lg_max_cfgs), line:3:14, endln:3:25 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/ConcatOrder/dut.sv, line:39:2, endln:54:11 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/ConcatOrder/dut.sv, line:39:2, endln:54:11 |INT:1 |vpiTypespec: \_int_typespec: @@ -1167,7 +1167,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.max_cfgs), line:2:14, endln:2:22 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/ConcatOrder/dut.sv, line:39:2, endln:54:11 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/ConcatOrder/dut.sv, line:39:2, endln:54:11 |UINT:2 |vpiTypespec: \_int_typespec: @@ -1180,7 +1180,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.bp_params_p), line:41:26, endln:41:37 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/ConcatOrder/dut.sv, line:39:2, endln:54:11 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/ConcatOrder/dut.sv, line:39:2, endln:54:11 |vpiTypespec: \_enum_typespec: (bp_common_pkg::bp_params_e), line:19:3, endln:23:17 |vpiName:bp_params_p @@ -1188,7 +1188,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.proc_param_lp), line:43:34, endln:43:47 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/ConcatOrder/dut.sv, line:39:2, endln:54:11 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/ConcatOrder/dut.sv, line:39:2, endln:54:11 |vpiTypespec: \_struct_typespec: (bp_common_pkg::bp_proc_param_s), line:5:10, endln:5:16 |vpiLocalParam:1 @@ -1197,14 +1197,14 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.cce_ucode_p), line:44:18, endln:44:29 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/ConcatOrder/dut.sv, line:39:2, endln:54:11 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/ConcatOrder/dut.sv, line:39:2, endln:54:11 |vpiLocalParam:1 |vpiName:cce_ucode_p |vpiFullName:work@testbench.cce_ucode_p |vpiParamAssign: \_param_assign: , line:2:14, endln:2:29 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/ConcatOrder/dut.sv, line:39:2, endln:54:11 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/ConcatOrder/dut.sv, line:39:2, endln:54:11 |vpiRhs: \_constant: , line:2:28, endln:2:29 |vpiParent: @@ -1233,7 +1233,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:3:14, endln:3:71 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/ConcatOrder/dut.sv, line:39:2, endln:54:11 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/ConcatOrder/dut.sv, line:39:2, endln:54:11 |vpiRhs: \_constant: , line:3:30, endln:3:45 |vpiParent: @@ -1262,7 +1262,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:10:31, endln:11:27 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/ConcatOrder/dut.sv, line:39:2, endln:54:11 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/ConcatOrder/dut.sv, line:39:2, endln:54:11 |vpiRhs: \_operation: , line:11:7, endln:11:27 |vpiParent: @@ -1320,7 +1320,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:13:42, endln:17:4 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/ConcatOrder/dut.sv, line:39:2, endln:54:11 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/ConcatOrder/dut.sv, line:39:2, endln:54:11 |vpiRhs: \_operation: , line:14:3, endln:17:4 |vpiParent: @@ -1399,7 +1399,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:25:28, endln:28:8 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/ConcatOrder/dut.sv, line:39:2, endln:54:11 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/ConcatOrder/dut.sv, line:39:2, endln:54:11 |vpiRhs: \_operation: , line:26:5, endln:28:8 |vpiParent: @@ -1457,7 +1457,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:30:28, endln:30:63 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/ConcatOrder/dut.sv, line:39:2, endln:54:11 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/ConcatOrder/dut.sv, line:39:2, endln:54:11 |vpiRhs: \_ref_obj: (work@testbench.bp_default_cfg_p), line:30:47, endln:30:63 |vpiParent: @@ -1499,7 +1499,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:41:26, endln:41:70 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/ConcatOrder/dut.sv, line:39:2, endln:54:11 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/ConcatOrder/dut.sv, line:39:2, endln:54:11 |vpiRhs: \_ref_obj: (e_bp_multicore_1_cce_ucode_cfg), line:41:40, endln:41:70 |vpiName:e_bp_multicore_1_cce_ucode_cfg @@ -1510,7 +1510,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:43:34, endln:43:74 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/ConcatOrder/dut.sv, line:39:2, endln:54:11 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/ConcatOrder/dut.sv, line:39:2, endln:54:11 |vpiRhs: \_bit_select: (all_cfgs_gp), line:43:50, endln:43:74 |vpiParent: @@ -1528,7 +1528,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:44:18, endln:44:70 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/ConcatOrder/dut.sv, line:39:2, endln:54:11 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/ConcatOrder/dut.sv, line:39:2, endln:54:11 |vpiRhs: \_hier_path: (proc_param_lp.cce_ucode), line:44:47, endln:44:70 |vpiName:proc_param_lp.cce_ucode @@ -1550,12 +1550,12 @@ design: (work@testbench) \_import_typespec: (bp_common_pkg), line:40:9, endln:40:25 |vpiDefName:work@testbench |uhdmtopModules: -\_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/ConcatOrder/dut.sv, line:39:2, endln:54:11 +\_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/ConcatOrder/dut.sv, line:39:2, endln:54:11 |vpiName:work@testbench |vpiParameter: \_parameter: (work@testbench.all_cfgs_gp), line:13:42, endln:13:53 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/ConcatOrder/dut.sv, line:39:2, endln:54:11 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/ConcatOrder/dut.sv, line:39:2, endln:54:11 |vpiTypespec: \_packed_array_typespec: , line:13:11, endln:13:26 |vpiParent: @@ -1612,7 +1612,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.bp_default_cfg_p), line:25:28, endln:25:44 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/ConcatOrder/dut.sv, line:39:2, endln:54:11 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/ConcatOrder/dut.sv, line:39:2, endln:54:11 |vpiTypespec: \_struct_typespec: (bp_common_pkg::bp_proc_param_s), line:5:10, endln:5:16 |vpiParent: @@ -1644,7 +1644,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.bp_multicore_1_cce_ucode_cfg_p), line:10:31, endln:10:61 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/ConcatOrder/dut.sv, line:39:2, endln:54:11 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/ConcatOrder/dut.sv, line:39:2, endln:54:11 |vpiTypespec: \_struct_typespec: (bp_common_pkg::bp_proc_param_s), line:5:10, endln:5:16 |vpiParent: @@ -1676,7 +1676,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.bp_unicore_cfg_p), line:30:28, endln:30:44 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/ConcatOrder/dut.sv, line:39:2, endln:54:11 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/ConcatOrder/dut.sv, line:39:2, endln:54:11 |vpiTypespec: \_struct_typespec: (bp_common_pkg::bp_proc_param_s), line:5:10, endln:5:16 |vpiParent: @@ -1708,7 +1708,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.lg_max_cfgs), line:3:14, endln:3:25 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/ConcatOrder/dut.sv, line:39:2, endln:54:11 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/ConcatOrder/dut.sv, line:39:2, endln:54:11 |INT:1 |vpiTypespec: \_int_typespec: @@ -1721,7 +1721,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.max_cfgs), line:2:14, endln:2:22 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/ConcatOrder/dut.sv, line:39:2, endln:54:11 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/ConcatOrder/dut.sv, line:39:2, endln:54:11 |UINT:2 |vpiTypespec: \_int_typespec: @@ -1734,7 +1734,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.bp_params_p), line:41:26, endln:41:37 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/ConcatOrder/dut.sv, line:39:2, endln:54:11 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/ConcatOrder/dut.sv, line:39:2, endln:54:11 |vpiTypespec: \_enum_typespec: (bp_common_pkg::bp_params_e), line:19:3, endln:23:17 |vpiParent: @@ -1790,7 +1790,7 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.proc_param_lp), line:43:34, endln:43:47 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/ConcatOrder/dut.sv, line:39:2, endln:54:11 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/ConcatOrder/dut.sv, line:39:2, endln:54:11 |vpiTypespec: \_struct_typespec: (bp_common_pkg::bp_proc_param_s), line:5:10, endln:5:16 |vpiParent: @@ -1821,14 +1821,14 @@ design: (work@testbench) |vpiParameter: \_parameter: (work@testbench.cce_ucode_p), line:44:18, endln:44:29 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/ConcatOrder/dut.sv, line:39:2, endln:54:11 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/ConcatOrder/dut.sv, line:39:2, endln:54:11 |vpiLocalParam:1 |vpiName:cce_ucode_p |vpiFullName:work@testbench.cce_ucode_p |vpiParamAssign: \_param_assign: , line:41:26, endln:41:70 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/ConcatOrder/dut.sv, line:39:2, endln:54:11 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/ConcatOrder/dut.sv, line:39:2, endln:54:11 |vpiRhs: \_constant: , line:41:40, endln:41:70 |vpiDecompile:1 @@ -1842,7 +1842,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:43:34, endln:43:74 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/ConcatOrder/dut.sv, line:39:2, endln:54:11 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/ConcatOrder/dut.sv, line:39:2, endln:54:11 |vpiRhs: \_bit_select: (all_cfgs_gp), line:43:50, endln:43:74 |vpiParent: @@ -1912,7 +1912,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:44:18, endln:44:70 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/ConcatOrder/dut.sv, line:39:2, endln:54:11 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/ConcatOrder/dut.sv, line:39:2, endln:54:11 |vpiRhs: \_constant: , line:44:47, endln:44:70 |vpiDecompile:1 @@ -1924,7 +1924,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:2:14, endln:2:29 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/ConcatOrder/dut.sv, line:39:2, endln:54:11 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/ConcatOrder/dut.sv, line:39:2, endln:54:11 |vpiRhs: \_constant: , line:2:28, endln:2:29 |vpiDecompile:2 @@ -1938,7 +1938,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:3:14, endln:3:71 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/ConcatOrder/dut.sv, line:39:2, endln:54:11 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/ConcatOrder/dut.sv, line:39:2, endln:54:11 |vpiRhs: \_constant: , line:3:28, endln:3:71 |vpiDecompile:1 @@ -1952,7 +1952,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:10:31, endln:11:27 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/ConcatOrder/dut.sv, line:39:2, endln:54:11 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/ConcatOrder/dut.sv, line:39:2, endln:54:11 |vpiRhs: \_operation: , line:11:7, endln:11:27 |vpiParent: @@ -1995,7 +1995,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:13:42, endln:17:4 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/ConcatOrder/dut.sv, line:39:2, endln:54:11 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/ConcatOrder/dut.sv, line:39:2, endln:54:11 |vpiRhs: \_operation: , line:14:3, endln:17:4 |vpiTypespec: @@ -2069,7 +2069,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:25:28, endln:28:8 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/ConcatOrder/dut.sv, line:39:2, endln:54:11 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/ConcatOrder/dut.sv, line:39:2, endln:54:11 |vpiRhs: \_operation: , line:26:5, endln:28:8 |vpiParent: @@ -2112,7 +2112,7 @@ design: (work@testbench) |vpiParamAssign: \_param_assign: , line:30:28, endln:30:63 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/ConcatOrder/dut.sv, line:39:2, endln:54:11 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/ConcatOrder/dut.sv, line:39:2, endln:54:11 |vpiRhs: \_ref_obj: (bp_default_cfg_p), line:30:47, endln:30:63 |vpiName:bp_default_cfg_p @@ -2132,7 +2132,7 @@ design: (work@testbench) |vpiGenScopeArray: \_gen_scope_array: (work@testbench.genblk1), line:48:2, endln:52:5 |vpiParent: - \_module: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/ConcatOrder/dut.sv, line:39:2, endln:54:11 + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/ConcatOrder/dut.sv, line:39:2, endln:54:11 |vpiName:genblk1 |vpiFullName:work@testbench.genblk1 |vpiGenScope: @@ -2140,8 +2140,8 @@ design: (work@testbench) |vpiParent: \_gen_scope_array: (work@testbench.genblk1), line:48:2, endln:52:5 |vpiFullName:work@testbench.genblk1 - |vpiModule: - \_module: work@GOOD (work@testbench.genblk1.good), file:${SURELOG_DIR}/tests/ConcatOrder/dut.sv, line:49:6, endln:49:18 + |vpiModuleInst: + \_module_inst: work@GOOD (work@testbench.genblk1.good), file:${SURELOG_DIR}/tests/ConcatOrder/dut.sv, line:49:6, endln:49:18 |vpiParent: \_gen_scope: (work@testbench.genblk1) |vpiName:good diff --git a/tests/ConcatRadix/ConcatRadix.log b/tests/ConcatRadix/ConcatRadix.log index 925483ef2f..71edc03b26 100644 --- a/tests/ConcatRadix/ConcatRadix.log +++ b/tests/ConcatRadix/ConcatRadix.log @@ -121,7 +121,7 @@ design 1 gen_scope 2 gen_scope_array 2 int_typespec 2 -module 5 +module_inst 5 operation 3 param_assign 2 parameter 2 @@ -135,7 +135,7 @@ design 1 gen_scope 3 gen_scope_array 3 int_typespec 2 -module 6 +module_inst 6 operation 3 param_assign 2 parameter 2 @@ -154,14 +154,14 @@ design: (work@test) |vpiElaborated:1 |vpiName:work@test |uhdmallModules: -\_module: work@test (work@test), file:${SURELOG_DIR}/tests/ConcatRadix/dut.sv, line:1:1, endln:9:10 +\_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/ConcatRadix/dut.sv, line:1:1, endln:9:10 |vpiParent: \_design: (work@test) |vpiFullName:work@test |vpiParameter: \_parameter: (work@test.foo), line:3:17, endln:3:20 |vpiParent: - \_module: work@test (work@test), file:${SURELOG_DIR}/tests/ConcatRadix/dut.sv, line:1:1, endln:9:10 + \_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/ConcatRadix/dut.sv, line:1:1, endln:9:10 |vpiTypespec: \_int_typespec: , line:3:11, endln:3:16 |vpiParent: @@ -189,7 +189,7 @@ design: (work@test) |vpiParamAssign: \_param_assign: , line:3:17, endln:3:35 |vpiParent: - \_module: work@test (work@test), file:${SURELOG_DIR}/tests/ConcatRadix/dut.sv, line:1:1, endln:9:10 + \_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/ConcatRadix/dut.sv, line:1:1, endln:9:10 |vpiRhs: \_operation: , line:3:23, endln:3:35 |vpiOpType:33 @@ -213,12 +213,12 @@ design: (work@test) \_parameter: (work@test.foo), line:3:17, endln:3:20 |vpiDefName:work@test |uhdmtopModules: -\_module: work@test (work@test), file:${SURELOG_DIR}/tests/ConcatRadix/dut.sv, line:1:1, endln:9:10 +\_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/ConcatRadix/dut.sv, line:1:1, endln:9:10 |vpiName:work@test |vpiParameter: \_parameter: (work@test.foo), line:3:17, endln:3:20 |vpiParent: - \_module: work@test (work@test), file:${SURELOG_DIR}/tests/ConcatRadix/dut.sv, line:1:1, endln:9:10 + \_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/ConcatRadix/dut.sv, line:1:1, endln:9:10 |vpiTypespec: \_int_typespec: , line:3:11, endln:3:16 |vpiParent: @@ -248,7 +248,7 @@ design: (work@test) |vpiParamAssign: \_param_assign: , line:3:17, endln:3:35 |vpiParent: - \_module: work@test (work@test), file:${SURELOG_DIR}/tests/ConcatRadix/dut.sv, line:1:1, endln:9:10 + \_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/ConcatRadix/dut.sv, line:1:1, endln:9:10 |vpiRhs: \_constant: , line:3:23, endln:3:35 |vpiDecompile:2'b01 @@ -265,7 +265,7 @@ design: (work@test) |vpiGenScopeArray: \_gen_scope_array: (work@test.genblk1), line:5:1, endln:7:4 |vpiParent: - \_module: work@test (work@test), file:${SURELOG_DIR}/tests/ConcatRadix/dut.sv, line:1:1, endln:9:10 + \_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/ConcatRadix/dut.sv, line:1:1, endln:9:10 |vpiName:genblk1 |vpiFullName:work@test.genblk1 |vpiGenScope: @@ -273,8 +273,8 @@ design: (work@test) |vpiParent: \_gen_scope_array: (work@test.genblk1), line:5:1, endln:7:4 |vpiFullName:work@test.genblk1 - |vpiModule: - \_module: work@test.genblk1::bar (work@test.genblk1.mybar), file:${SURELOG_DIR}/tests/ConcatRadix/dut.sv, line:6:5, endln:6:17 + |vpiModuleInst: + \_module_inst: work@test.genblk1::bar (work@test.genblk1.mybar), file:${SURELOG_DIR}/tests/ConcatRadix/dut.sv, line:6:5, endln:6:17 |vpiParent: \_gen_scope: (work@test.genblk1) |vpiName:mybar diff --git a/tests/ConcatVal/ConcatVal.log b/tests/ConcatVal/ConcatVal.log index 203f57d642..61668c55f8 100644 --- a/tests/ConcatVal/ConcatVal.log +++ b/tests/ConcatVal/ConcatVal.log @@ -510,7 +510,7 @@ io_decl 13 logic_net 2 logic_typespec 6 logic_var 2 -module 6 +module_inst 6 operation 8 package 2 param_assign 4 @@ -540,7 +540,7 @@ io_decl 26 logic_net 2 logic_typespec 6 logic_var 2 -module 6 +module_inst 6 operation 8 package 2 param_assign 4 @@ -1037,14 +1037,14 @@ design: (work@dut) \_int_typespec: |vpiSigned:1 |uhdmallModules: -\_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/ConcatVal/dut.sv, line:1:1, endln:15:10 +\_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/ConcatVal/dut.sv, line:1:1, endln:15:10 |vpiParent: \_design: (work@dut) |vpiFullName:work@dut |vpiParameter: \_parameter: (work@dut.PRESENT_SBOX4), line:2:31, endln:2:44 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/ConcatVal/dut.sv, line:1:1, endln:15:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/ConcatVal/dut.sv, line:1:1, endln:15:10 |vpiTypespec: \_logic_typespec: , line:2:13, endln:2:30 |vpiParent: @@ -1090,7 +1090,7 @@ design: (work@dut) |vpiParamAssign: \_param_assign: , line:2:31, endln:2:59 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/ConcatVal/dut.sv, line:1:1, endln:15:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/ConcatVal/dut.sv, line:1:1, endln:15:10 |vpiRhs: \_operation: , line:2:47, endln:2:59 |vpiOpType:33 @@ -1115,10 +1115,10 @@ design: (work@dut) |vpiTypedef: \_enum_typespec: (exc_cause_e), line:7:3, endln:11:17 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/ConcatVal/dut.sv, line:1:1, endln:15:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/ConcatVal/dut.sv, line:1:1, endln:15:10 |vpiName:exc_cause_e |vpiInstance: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/ConcatVal/dut.sv, line:1:1, endln:15:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/ConcatVal/dut.sv, line:1:1, endln:15:10 |vpiBaseTypespec: \_logic_typespec: , line:7:16, endln:7:27 |vpiRange: @@ -1161,7 +1161,7 @@ design: (work@dut) |vpiTaskFunc: \_function: (work@dut.sbox4_64bit), line:4:2, endln:5:28 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/ConcatVal/dut.sv, line:1:1, endln:15:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/ConcatVal/dut.sv, line:1:1, endln:15:10 |vpiName:sbox4_64bit |vpiFullName:work@dut.sbox4_64bit |vpiVisibility:1 @@ -1189,7 +1189,7 @@ design: (work@dut) |UINT:0 |vpiConstType:9 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/ConcatVal/dut.sv, line:1:1, endln:15:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/ConcatVal/dut.sv, line:1:1, endln:15:10 |vpiIODecl: \_io_decl: (state_in), line:4:59, endln:4:67 |vpiDirection:1 @@ -1262,11 +1262,11 @@ design: (work@dut) \_function: (work@dut.sbox4_64bit), line:4:2, endln:5:28 |vpiFullName:work@dut.sbox4_64bit |vpiInstance: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/ConcatVal/dut.sv, line:1:1, endln:15:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/ConcatVal/dut.sv, line:1:1, endln:15:10 |vpiContAssign: \_cont_assign: , line:14:10, endln:14:70 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/ConcatVal/dut.sv, line:1:1, endln:15:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/ConcatVal/dut.sv, line:1:1, endln:15:10 |vpiRhs: \_func_call: (sbox4_64bit), line:14:28, endln:14:70 |vpiParent: @@ -1299,12 +1299,12 @@ design: (work@dut) |vpiActual: \_logic_net: (data_state_sbox) |uhdmtopModules: -\_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/ConcatVal/dut.sv, line:1:1, endln:15:10 +\_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/ConcatVal/dut.sv, line:1:1, endln:15:10 |vpiName:work@dut |vpiParameter: \_parameter: (work@dut.PRESENT_SBOX4), line:2:31, endln:2:44 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/ConcatVal/dut.sv, line:1:1, endln:15:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/ConcatVal/dut.sv, line:1:1, endln:15:10 |vpiTypespec: \_logic_typespec: , line:2:13, endln:2:30 |vpiParent: @@ -1354,7 +1354,7 @@ design: (work@dut) |vpiParamAssign: \_param_assign: , line:2:31, endln:2:59 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/ConcatVal/dut.sv, line:1:1, endln:15:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/ConcatVal/dut.sv, line:1:1, endln:15:10 |vpiRhs: \_operation: , line:2:47, endln:2:59 |vpiTypespec: @@ -1386,7 +1386,7 @@ design: (work@dut) |vpiTaskFunc: \_function: (work@dut.sbox4_64bit), line:4:2, endln:5:28 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/ConcatVal/dut.sv, line:1:1, endln:15:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/ConcatVal/dut.sv, line:1:1, endln:15:10 |vpiName:sbox4_64bit |vpiFullName:work@dut.sbox4_64bit |vpiVisibility:1 @@ -1394,7 +1394,7 @@ design: (work@dut) |vpiReturn: \_logic_var: , line:4:21, endln:4:33 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/ConcatVal/dut.sv, line:1:1, endln:15:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/ConcatVal/dut.sv, line:1:1, endln:15:10 |vpiIODecl: \_io_decl: (state_in), line:4:59, endln:4:67 |vpiParent: @@ -1417,7 +1417,7 @@ design: (work@dut) \_function: (work@dut.sbox4_64bit), line:4:2, endln:5:28 |vpiFullName:work@dut.sbox4_64bit |vpiInstance: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/ConcatVal/dut.sv, line:1:1, endln:15:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/ConcatVal/dut.sv, line:1:1, endln:15:10 |vpiNet: \_logic_net: (data_state_sbox) |vpiName:data_state_sbox @@ -1430,7 +1430,7 @@ design: (work@dut) |vpiContAssign: \_cont_assign: , line:14:10, endln:14:70 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/ConcatVal/dut.sv, line:1:1, endln:15:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/ConcatVal/dut.sv, line:1:1, endln:15:10 |vpiRhs: \_func_call: (sbox4_64bit), line:14:28, endln:14:70 |vpiParent: diff --git a/tests/ConcatWidth/ConcatWidth.log b/tests/ConcatWidth/ConcatWidth.log index d07055ba91..76ac0f2506 100644 --- a/tests/ConcatWidth/ConcatWidth.log +++ b/tests/ConcatWidth/ConcatWidth.log @@ -524,7 +524,7 @@ io_decl 11 logic_net 6 logic_typespec 8 logic_var 3 -module 6 +module_inst 6 operation 13 package 2 param_assign 2 @@ -559,7 +559,7 @@ io_decl 22 logic_net 6 logic_typespec 8 logic_var 3 -module 6 +module_inst 6 operation 20 package 2 param_assign 2 @@ -1058,14 +1058,14 @@ design: (work@top) \_int_typespec: |vpiSigned:1 |uhdmallModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/ConcatWidth/dut.sv, line:1:1, endln:18:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ConcatWidth/dut.sv, line:1:1, endln:18:10 |vpiParent: \_design: (work@top) |vpiFullName:work@top |vpiParameter: \_parameter: (work@top.CounterWidth), line:2:19, endln:2:31 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ConcatWidth/dut.sv, line:1:1, endln:18:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ConcatWidth/dut.sv, line:1:1, endln:18:10 |UINT:32 |vpiTypespec: \_int_typespec: , line:2:15, endln:2:18 @@ -1078,7 +1078,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:2:19, endln:2:36 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ConcatWidth/dut.sv, line:1:1, endln:18:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ConcatWidth/dut.sv, line:1:1, endln:18:10 |vpiRhs: \_constant: , line:2:34, endln:2:36 |vpiDecompile:32 @@ -1093,35 +1093,35 @@ design: (work@top) |vpiNet: \_logic_net: (work@top.clk), line:4:17, endln:4:20 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ConcatWidth/dut.sv, line:1:1, endln:18:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ConcatWidth/dut.sv, line:1:1, endln:18:10 |vpiName:clk |vpiFullName:work@top.clk |vpiNetType:36 |vpiNet: \_logic_net: (work@top.out), line:5:37, endln:5:40 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ConcatWidth/dut.sv, line:1:1, endln:18:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ConcatWidth/dut.sv, line:1:1, endln:18:10 |vpiName:out |vpiFullName:work@top.out |vpiNetType:36 |vpiNet: \_logic_net: (work@top.counter), line:8:18, endln:8:25 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ConcatWidth/dut.sv, line:1:1, endln:18:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ConcatWidth/dut.sv, line:1:1, endln:18:10 |vpiName:counter |vpiFullName:work@top.counter |vpiNetType:36 |vpiNet: \_logic_net: (work@top.counter_upd), line:9:30, endln:9:41 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ConcatWidth/dut.sv, line:1:1, endln:18:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ConcatWidth/dut.sv, line:1:1, endln:18:10 |vpiName:counter_upd |vpiFullName:work@top.counter_upd |vpiNetType:36 |vpiPort: \_port: (clk), line:4:17, endln:4:20 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ConcatWidth/dut.sv, line:1:1, endln:18:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ConcatWidth/dut.sv, line:1:1, endln:18:10 |vpiName:clk |vpiDirection:1 |vpiLowConn: @@ -1133,7 +1133,7 @@ design: (work@top) |vpiPort: \_port: (out), line:5:37, endln:5:40 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ConcatWidth/dut.sv, line:1:1, endln:18:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ConcatWidth/dut.sv, line:1:1, endln:18:10 |vpiName:out |vpiDirection:2 |vpiLowConn: @@ -1173,7 +1173,7 @@ design: (work@top) |vpiProcess: \_initial: , line:11:5, endln:12:21 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ConcatWidth/dut.sv, line:1:1, endln:18:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ConcatWidth/dut.sv, line:1:1, endln:18:10 |vpiStmt: \_assignment: , line:12:9, endln:12:20 |vpiParent: @@ -1199,7 +1199,7 @@ design: (work@top) |vpiProcess: \_always: , line:13:5, endln:15:8 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ConcatWidth/dut.sv, line:1:1, endln:18:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ConcatWidth/dut.sv, line:1:1, endln:18:10 |vpiStmt: \_event_control: , line:13:12, endln:13:26 |vpiParent: @@ -1328,7 +1328,7 @@ design: (work@top) |vpiContAssign: \_cont_assign: , line:16:12, endln:16:29 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ConcatWidth/dut.sv, line:1:1, endln:18:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ConcatWidth/dut.sv, line:1:1, endln:18:10 |vpiRhs: \_ref_obj: (work@top.counter_upd), line:16:18, endln:16:29 |vpiParent: @@ -1346,12 +1346,12 @@ design: (work@top) |vpiActual: \_logic_net: (work@top.out), line:5:37, endln:5:40 |uhdmtopModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/ConcatWidth/dut.sv, line:1:1, endln:18:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ConcatWidth/dut.sv, line:1:1, endln:18:10 |vpiName:work@top |vpiVariables: \_logic_var: (work@top.counter), line:8:18, endln:8:25 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ConcatWidth/dut.sv, line:1:1, endln:18:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ConcatWidth/dut.sv, line:1:1, endln:18:10 |vpiTypespec: \_logic_typespec: , line:8:5, endln:8:17 |vpiRange: @@ -1396,7 +1396,7 @@ design: (work@top) |vpiVariables: \_logic_var: (work@top.counter_upd), line:9:30, endln:9:41 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ConcatWidth/dut.sv, line:1:1, endln:18:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ConcatWidth/dut.sv, line:1:1, endln:18:10 |vpiTypespec: \_logic_typespec: , line:9:5, endln:9:29 |vpiRange: @@ -1441,7 +1441,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.CounterWidth), line:2:19, endln:2:31 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ConcatWidth/dut.sv, line:1:1, endln:18:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ConcatWidth/dut.sv, line:1:1, endln:18:10 |UINT:32 |vpiTypespec: \_int_typespec: , line:2:15, endln:2:18 @@ -1454,7 +1454,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:2:19, endln:2:36 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ConcatWidth/dut.sv, line:1:1, endln:18:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ConcatWidth/dut.sv, line:1:1, endln:18:10 |vpiRhs: \_constant: , line:2:34, endln:2:36 |vpiDecompile:32 @@ -1470,7 +1470,7 @@ design: (work@top) |vpiNet: \_logic_net: (work@top.clk), line:4:17, endln:4:20 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ConcatWidth/dut.sv, line:1:1, endln:18:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ConcatWidth/dut.sv, line:1:1, endln:18:10 |vpiTypespec: \_logic_typespec: , line:4:11, endln:4:16 |vpiName:clk @@ -1479,7 +1479,7 @@ design: (work@top) |vpiNet: \_logic_net: (work@top.out), line:5:37, endln:5:40 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ConcatWidth/dut.sv, line:1:1, endln:18:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ConcatWidth/dut.sv, line:1:1, endln:18:10 |vpiTypespec: \_logic_typespec: , line:5:12, endln:5:36 |vpiRange: @@ -1507,7 +1507,7 @@ design: (work@top) |vpiPort: \_port: (clk), line:4:17, endln:4:20 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ConcatWidth/dut.sv, line:1:1, endln:18:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ConcatWidth/dut.sv, line:1:1, endln:18:10 |vpiName:clk |vpiDirection:1 |vpiLowConn: @@ -1521,11 +1521,11 @@ design: (work@top) |vpiTypedef: \_logic_typespec: , line:4:11, endln:4:16 |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ConcatWidth/dut.sv, line:1:1, endln:18:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ConcatWidth/dut.sv, line:1:1, endln:18:10 |vpiPort: \_port: (out), line:5:37, endln:5:40 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ConcatWidth/dut.sv, line:1:1, endln:18:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ConcatWidth/dut.sv, line:1:1, endln:18:10 |vpiName:out |vpiDirection:2 |vpiLowConn: @@ -1559,11 +1559,11 @@ design: (work@top) |UINT:0 |vpiConstType:9 |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ConcatWidth/dut.sv, line:1:1, endln:18:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ConcatWidth/dut.sv, line:1:1, endln:18:10 |vpiProcess: \_initial: , line:11:5, endln:12:21 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ConcatWidth/dut.sv, line:1:1, endln:18:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ConcatWidth/dut.sv, line:1:1, endln:18:10 |vpiStmt: \_assignment: , line:12:9, endln:12:20 |vpiParent: @@ -1583,7 +1583,7 @@ design: (work@top) |vpiProcess: \_always: , line:13:5, endln:15:8 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ConcatWidth/dut.sv, line:1:1, endln:18:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ConcatWidth/dut.sv, line:1:1, endln:18:10 |vpiStmt: \_event_control: , line:13:12, endln:13:26 |vpiParent: @@ -1692,7 +1692,7 @@ design: (work@top) |vpiContAssign: \_cont_assign: , line:16:12, endln:16:29 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ConcatWidth/dut.sv, line:1:1, endln:18:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ConcatWidth/dut.sv, line:1:1, endln:18:10 |vpiRhs: \_ref_obj: (work@top.counter_upd), line:16:18, endln:16:29 |vpiParent: diff --git a/tests/CondOpPrec/CondOpPred.log b/tests/CondOpPrec/CondOpPred.log index bc82a56e13..eb80d41e5a 100644 --- a/tests/CondOpPrec/CondOpPred.log +++ b/tests/CondOpPrec/CondOpPred.log @@ -158,7 +158,7 @@ gen_scope_array 2 int_typespec 7 logic_net 2 logic_typespec 3 -module 7 +module_inst 7 operation 9 param_assign 4 parameter 4 @@ -175,7 +175,7 @@ gen_scope_array 3 int_typespec 7 logic_net 2 logic_typespec 3 -module 8 +module_inst 8 operation 9 param_assign 4 parameter 4 @@ -195,20 +195,20 @@ design: (work@top) |vpiElaborated:1 |vpiName:work@top |uhdmallModules: -\_module: work@GOOD (work@GOOD), file:${SURELOG_DIR}/tests/CondOpPrec/dut.sv, line:1:1, endln:3:10 +\_module_inst: work@GOOD (work@GOOD), file:${SURELOG_DIR}/tests/CondOpPrec/dut.sv, line:1:1, endln:3:10 |vpiParent: \_design: (work@top) |vpiFullName:work@GOOD |vpiDefName:work@GOOD |uhdmallModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/CondOpPrec/dut.sv, line:5:1, endln:17:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/CondOpPrec/dut.sv, line:5:1, endln:17:10 |vpiParent: \_design: (work@top) |vpiFullName:work@top |vpiParameter: \_parameter: (work@top.Width), line:6:18, endln:6:23 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/CondOpPrec/dut.sv, line:5:1, endln:17:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/CondOpPrec/dut.sv, line:5:1, endln:17:10 |UINT:16 |vpiTypespec: \_int_typespec: , line:6:14, endln:6:17 @@ -221,7 +221,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.ParWidth), line:10:18, endln:10:26 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/CondOpPrec/dut.sv, line:5:1, endln:17:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/CondOpPrec/dut.sv, line:5:1, endln:17:10 |vpiTypespec: \_int_typespec: , line:10:14, endln:10:17 |vpiParent: @@ -234,7 +234,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:6:18, endln:6:28 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/CondOpPrec/dut.sv, line:5:1, endln:17:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/CondOpPrec/dut.sv, line:5:1, endln:17:10 |vpiRhs: \_constant: , line:6:26, endln:6:28 |vpiDecompile:16 @@ -248,7 +248,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:10:18, endln:11:51 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/CondOpPrec/dut.sv, line:5:1, endln:17:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/CondOpPrec/dut.sv, line:5:1, endln:17:10 |vpiRhs: \_operation: , line:10:29, endln:11:51 |vpiOpType:32 @@ -323,14 +323,14 @@ design: (work@top) |vpiNet: \_logic_net: (work@top.o), line:8:17, endln:8:18 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/CondOpPrec/dut.sv, line:5:1, endln:17:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/CondOpPrec/dut.sv, line:5:1, endln:17:10 |vpiName:o |vpiFullName:work@top.o |vpiNetType:36 |vpiPort: \_port: (o), line:8:17, endln:8:18 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/CondOpPrec/dut.sv, line:5:1, endln:17:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/CondOpPrec/dut.sv, line:5:1, endln:17:10 |vpiName:o |vpiDirection:2 |vpiLowConn: @@ -340,12 +340,12 @@ design: (work@top) |vpiTypedef: \_logic_typespec: , line:8:11, endln:8:16 |uhdmtopModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/CondOpPrec/dut.sv, line:5:1, endln:17:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/CondOpPrec/dut.sv, line:5:1, endln:17:10 |vpiName:work@top |vpiParameter: \_parameter: (work@top.Width), line:6:18, endln:6:23 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/CondOpPrec/dut.sv, line:5:1, endln:17:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/CondOpPrec/dut.sv, line:5:1, endln:17:10 |UINT:16 |vpiTypespec: \_int_typespec: , line:6:14, endln:6:17 @@ -358,7 +358,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.ParWidth), line:10:18, endln:10:26 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/CondOpPrec/dut.sv, line:5:1, endln:17:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/CondOpPrec/dut.sv, line:5:1, endln:17:10 |vpiTypespec: \_int_typespec: , line:10:14, endln:10:17 |vpiParent: @@ -371,7 +371,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:6:18, endln:6:28 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/CondOpPrec/dut.sv, line:5:1, endln:17:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/CondOpPrec/dut.sv, line:5:1, endln:17:10 |vpiRhs: \_constant: , line:6:26, endln:6:28 |vpiDecompile:16 @@ -385,7 +385,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:10:18, endln:11:51 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/CondOpPrec/dut.sv, line:5:1, endln:17:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/CondOpPrec/dut.sv, line:5:1, endln:17:10 |vpiRhs: \_constant: , line:10:29, endln:11:51 |vpiDecompile:6 @@ -401,7 +401,7 @@ design: (work@top) |vpiNet: \_logic_net: (work@top.o), line:8:17, endln:8:18 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/CondOpPrec/dut.sv, line:5:1, endln:17:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/CondOpPrec/dut.sv, line:5:1, endln:17:10 |vpiTypespec: \_logic_typespec: , line:8:11, endln:8:16 |vpiName:o @@ -411,7 +411,7 @@ design: (work@top) |vpiPort: \_port: (o), line:8:17, endln:8:18 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/CondOpPrec/dut.sv, line:5:1, endln:17:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/CondOpPrec/dut.sv, line:5:1, endln:17:10 |vpiName:o |vpiDirection:2 |vpiLowConn: @@ -425,11 +425,11 @@ design: (work@top) |vpiTypedef: \_logic_typespec: , line:8:11, endln:8:16 |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/CondOpPrec/dut.sv, line:5:1, endln:17:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/CondOpPrec/dut.sv, line:5:1, endln:17:10 |vpiGenScopeArray: \_gen_scope_array: (work@top.genblk1), line:13:3, endln:15:6 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/CondOpPrec/dut.sv, line:5:1, endln:17:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/CondOpPrec/dut.sv, line:5:1, endln:17:10 |vpiName:genblk1 |vpiFullName:work@top.genblk1 |vpiGenScope: @@ -437,8 +437,8 @@ design: (work@top) |vpiParent: \_gen_scope_array: (work@top.genblk1), line:13:3, endln:15:6 |vpiFullName:work@top.genblk1 - |vpiModule: - \_module: work@GOOD (work@top.genblk1.good), file:${SURELOG_DIR}/tests/CondOpPrec/dut.sv, line:14:6, endln:14:18 + |vpiModuleInst: + \_module_inst: work@GOOD (work@top.genblk1.good), file:${SURELOG_DIR}/tests/CondOpPrec/dut.sv, line:14:6, endln:14:18 |vpiParent: \_gen_scope: (work@top.genblk1) |vpiName:good diff --git a/tests/ConditionalOp/ConditionalOp.log b/tests/ConditionalOp/ConditionalOp.log index 13e7ceb7dc..94f752a982 100644 --- a/tests/ConditionalOp/ConditionalOp.log +++ b/tests/ConditionalOp/ConditionalOp.log @@ -687,7 +687,7 @@ io_decl 11 logic_net 3 logic_typespec 3 logic_var 4 -module 9 +module_inst 9 operation 26 package 2 param_assign 18 @@ -716,7 +716,7 @@ io_decl 22 logic_net 3 logic_typespec 3 logic_var 4 -module 9 +module_inst 9 operation 26 package 2 param_assign 18 @@ -1214,14 +1214,14 @@ design: (work@top) \_int_typespec: |vpiSigned:1 |uhdmallModules: -\_module: work@ibex_register_file (work@ibex_register_file), file:${SURELOG_DIR}/tests/ConditionalOp/dut.sv, line:14:1, endln:24:10 +\_module_inst: work@ibex_register_file (work@ibex_register_file), file:${SURELOG_DIR}/tests/ConditionalOp/dut.sv, line:14:1, endln:24:10 |vpiParent: \_design: (work@top) |vpiFullName:work@ibex_register_file |vpiParameter: \_parameter: (work@ibex_register_file.RV32E), line:15:28, endln:15:33 |vpiParent: - \_module: work@ibex_register_file (work@ibex_register_file), file:${SURELOG_DIR}/tests/ConditionalOp/dut.sv, line:14:1, endln:24:10 + \_module_inst: work@ibex_register_file (work@ibex_register_file), file:${SURELOG_DIR}/tests/ConditionalOp/dut.sv, line:14:1, endln:24:10 |UINT:0 |vpiTypespec: \_bit_typespec: , line:15:15, endln:15:18 @@ -1233,7 +1233,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@ibex_register_file.DataWidth), line:16:28, endln:16:37 |vpiParent: - \_module: work@ibex_register_file (work@ibex_register_file), file:${SURELOG_DIR}/tests/ConditionalOp/dut.sv, line:14:1, endln:24:10 + \_module_inst: work@ibex_register_file (work@ibex_register_file), file:${SURELOG_DIR}/tests/ConditionalOp/dut.sv, line:14:1, endln:24:10 |UINT:32 |vpiTypespec: \_int_typespec: , line:16:15, endln:16:27 @@ -1244,7 +1244,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@ibex_register_file.ADDR_WIDTH), line:18:27, endln:18:37 |vpiParent: - \_module: work@ibex_register_file (work@ibex_register_file), file:${SURELOG_DIR}/tests/ConditionalOp/dut.sv, line:14:1, endln:24:10 + \_module_inst: work@ibex_register_file (work@ibex_register_file), file:${SURELOG_DIR}/tests/ConditionalOp/dut.sv, line:14:1, endln:24:10 |vpiTypespec: \_int_typespec: , line:18:14, endln:18:26 |vpiParent: @@ -1255,7 +1255,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@ibex_register_file.NUM_WORDS), line:19:27, endln:19:36 |vpiParent: - \_module: work@ibex_register_file (work@ibex_register_file), file:${SURELOG_DIR}/tests/ConditionalOp/dut.sv, line:14:1, endln:24:10 + \_module_inst: work@ibex_register_file (work@ibex_register_file), file:${SURELOG_DIR}/tests/ConditionalOp/dut.sv, line:14:1, endln:24:10 |vpiTypespec: \_int_typespec: , line:19:14, endln:19:26 |vpiParent: @@ -1266,7 +1266,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:15:28, endln:15:49 |vpiParent: - \_module: work@ibex_register_file (work@ibex_register_file), file:${SURELOG_DIR}/tests/ConditionalOp/dut.sv, line:14:1, endln:24:10 + \_module_inst: work@ibex_register_file (work@ibex_register_file), file:${SURELOG_DIR}/tests/ConditionalOp/dut.sv, line:14:1, endln:24:10 |vpiRhs: \_constant: , line:15:48, endln:15:49 |vpiDecompile:0 @@ -1280,7 +1280,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:16:28, endln:16:50 |vpiParent: - \_module: work@ibex_register_file (work@ibex_register_file), file:${SURELOG_DIR}/tests/ConditionalOp/dut.sv, line:14:1, endln:24:10 + \_module_inst: work@ibex_register_file (work@ibex_register_file), file:${SURELOG_DIR}/tests/ConditionalOp/dut.sv, line:14:1, endln:24:10 |vpiRhs: \_constant: , line:16:48, endln:16:50 |vpiDecompile:32 @@ -1294,7 +1294,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:18:27, endln:18:53 |vpiParent: - \_module: work@ibex_register_file (work@ibex_register_file), file:${SURELOG_DIR}/tests/ConditionalOp/dut.sv, line:14:1, endln:24:10 + \_module_inst: work@ibex_register_file (work@ibex_register_file), file:${SURELOG_DIR}/tests/ConditionalOp/dut.sv, line:14:1, endln:24:10 |vpiRhs: \_operation: , line:18:40, endln:18:53 |vpiOpType:32 @@ -1324,7 +1324,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:19:27, endln:19:53 |vpiParent: - \_module: work@ibex_register_file (work@ibex_register_file), file:${SURELOG_DIR}/tests/ConditionalOp/dut.sv, line:14:1, endln:24:10 + \_module_inst: work@ibex_register_file (work@ibex_register_file), file:${SURELOG_DIR}/tests/ConditionalOp/dut.sv, line:14:1, endln:24:10 |vpiRhs: \_operation: , line:19:40, endln:19:53 |vpiOpType:43 @@ -1347,33 +1347,33 @@ design: (work@top) |vpiNet: \_logic_net: (work@ibex_register_file.rf_reg), line:21:40, endln:21:46 |vpiParent: - \_module: work@ibex_register_file (work@ibex_register_file), file:${SURELOG_DIR}/tests/ConditionalOp/dut.sv, line:14:1, endln:24:10 + \_module_inst: work@ibex_register_file (work@ibex_register_file), file:${SURELOG_DIR}/tests/ConditionalOp/dut.sv, line:14:1, endln:24:10 |vpiName:rf_reg |vpiFullName:work@ibex_register_file.rf_reg |vpiNetType:36 |vpiNet: \_logic_net: (work@ibex_register_file.rf_reg_q), line:22:40, endln:22:48 |vpiParent: - \_module: work@ibex_register_file (work@ibex_register_file), file:${SURELOG_DIR}/tests/ConditionalOp/dut.sv, line:14:1, endln:24:10 + \_module_inst: work@ibex_register_file (work@ibex_register_file), file:${SURELOG_DIR}/tests/ConditionalOp/dut.sv, line:14:1, endln:24:10 |vpiName:rf_reg_q |vpiFullName:work@ibex_register_file.rf_reg_q |vpiNetType:36 |vpiNet: \_logic_net: (work@ibex_register_file.we_a_dec), line:23:40, endln:23:48 |vpiParent: - \_module: work@ibex_register_file (work@ibex_register_file), file:${SURELOG_DIR}/tests/ConditionalOp/dut.sv, line:14:1, endln:24:10 + \_module_inst: work@ibex_register_file (work@ibex_register_file), file:${SURELOG_DIR}/tests/ConditionalOp/dut.sv, line:14:1, endln:24:10 |vpiName:we_a_dec |vpiFullName:work@ibex_register_file.we_a_dec |vpiNetType:36 |uhdmallModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/ConditionalOp/dut.sv, line:1:1, endln:12:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ConditionalOp/dut.sv, line:1:1, endln:12:10 |vpiParent: \_design: (work@top) |vpiFullName:work@top |vpiParameter: \_parameter: (work@top.NrHarts), line:2:33, endln:2:40 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ConditionalOp/dut.sv, line:1:1, endln:12:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ConditionalOp/dut.sv, line:1:1, endln:12:10 |UINT:1 |vpiTypespec: \_int_typespec: , line:2:20, endln:2:32 @@ -1385,7 +1385,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.NrHarts2), line:4:26, endln:4:34 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ConditionalOp/dut.sv, line:1:1, endln:12:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ConditionalOp/dut.sv, line:1:1, endln:12:10 |UINT:8 |vpiTypespec: \_int_typespec: , line:4:13, endln:4:25 @@ -1397,7 +1397,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.HartSelLen1), line:6:26, endln:6:37 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ConditionalOp/dut.sv, line:1:1, endln:12:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ConditionalOp/dut.sv, line:1:1, endln:12:10 |vpiTypespec: \_int_typespec: , line:6:13, endln:6:25 |vpiParent: @@ -1408,7 +1408,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.HartSelLen2), line:8:26, endln:8:37 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ConditionalOp/dut.sv, line:1:1, endln:12:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ConditionalOp/dut.sv, line:1:1, endln:12:10 |vpiTypespec: \_int_typespec: , line:8:13, endln:8:25 |vpiParent: @@ -1419,7 +1419,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.HartSelLen3), line:10:26, endln:10:37 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ConditionalOp/dut.sv, line:1:1, endln:12:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ConditionalOp/dut.sv, line:1:1, endln:12:10 |vpiTypespec: \_int_typespec: , line:10:13, endln:10:25 |vpiParent: @@ -1430,7 +1430,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:2:33, endln:2:44 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ConditionalOp/dut.sv, line:1:1, endln:12:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ConditionalOp/dut.sv, line:1:1, endln:12:10 |vpiRhs: \_constant: , line:2:43, endln:2:44 |vpiDecompile:1 @@ -1444,7 +1444,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:4:26, endln:4:38 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ConditionalOp/dut.sv, line:1:1, endln:12:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ConditionalOp/dut.sv, line:1:1, endln:12:10 |vpiRhs: \_constant: , line:4:37, endln:4:38 |vpiDecompile:8 @@ -1458,7 +1458,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:6:26, endln:6:76 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ConditionalOp/dut.sv, line:1:1, endln:12:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ConditionalOp/dut.sv, line:1:1, endln:12:10 |vpiRhs: \_operation: , line:6:40, endln:6:76 |vpiOpType:32 @@ -1503,7 +1503,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:8:26, endln:8:62 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ConditionalOp/dut.sv, line:1:1, endln:12:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ConditionalOp/dut.sv, line:1:1, endln:12:10 |vpiRhs: \_operation: , line:8:40, endln:8:62 |vpiOpType:32 @@ -1546,7 +1546,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:10:26, endln:10:77 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ConditionalOp/dut.sv, line:1:1, endln:12:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ConditionalOp/dut.sv, line:1:1, endln:12:10 |vpiRhs: \_operation: , line:10:40, endln:10:77 |vpiOpType:32 @@ -1590,12 +1590,12 @@ design: (work@top) \_parameter: (work@top.HartSelLen3), line:10:26, endln:10:37 |vpiDefName:work@top |uhdmtopModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/ConditionalOp/dut.sv, line:1:1, endln:12:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ConditionalOp/dut.sv, line:1:1, endln:12:10 |vpiName:work@top |vpiParameter: \_parameter: (work@top.NrHarts), line:2:33, endln:2:40 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ConditionalOp/dut.sv, line:1:1, endln:12:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ConditionalOp/dut.sv, line:1:1, endln:12:10 |UINT:1 |vpiTypespec: \_int_typespec: , line:2:20, endln:2:32 @@ -1607,7 +1607,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.NrHarts2), line:4:26, endln:4:34 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ConditionalOp/dut.sv, line:1:1, endln:12:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ConditionalOp/dut.sv, line:1:1, endln:12:10 |UINT:8 |vpiTypespec: \_int_typespec: , line:4:13, endln:4:25 @@ -1619,7 +1619,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.HartSelLen1), line:6:26, endln:6:37 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ConditionalOp/dut.sv, line:1:1, endln:12:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ConditionalOp/dut.sv, line:1:1, endln:12:10 |vpiTypespec: \_int_typespec: , line:6:13, endln:6:25 |vpiParent: @@ -1630,7 +1630,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.HartSelLen2), line:8:26, endln:8:37 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ConditionalOp/dut.sv, line:1:1, endln:12:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ConditionalOp/dut.sv, line:1:1, endln:12:10 |vpiTypespec: \_int_typespec: , line:8:13, endln:8:25 |vpiParent: @@ -1641,7 +1641,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.HartSelLen3), line:10:26, endln:10:37 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ConditionalOp/dut.sv, line:1:1, endln:12:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ConditionalOp/dut.sv, line:1:1, endln:12:10 |vpiTypespec: \_int_typespec: , line:10:13, endln:10:25 |vpiParent: @@ -1652,7 +1652,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:2:33, endln:2:44 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ConditionalOp/dut.sv, line:1:1, endln:12:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ConditionalOp/dut.sv, line:1:1, endln:12:10 |vpiRhs: \_constant: , line:2:43, endln:2:44 |vpiDecompile:1 @@ -1666,7 +1666,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:4:26, endln:4:38 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ConditionalOp/dut.sv, line:1:1, endln:12:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ConditionalOp/dut.sv, line:1:1, endln:12:10 |vpiRhs: \_constant: , line:4:37, endln:4:38 |vpiDecompile:8 @@ -1680,7 +1680,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:6:26, endln:6:76 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ConditionalOp/dut.sv, line:1:1, endln:12:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ConditionalOp/dut.sv, line:1:1, endln:12:10 |vpiRhs: \_constant: , line:6:40, endln:6:76 |vpiDecompile:1 @@ -1694,7 +1694,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:8:26, endln:8:62 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ConditionalOp/dut.sv, line:1:1, endln:12:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ConditionalOp/dut.sv, line:1:1, endln:12:10 |vpiRhs: \_constant: , line:8:40, endln:8:62 |vpiDecompile:1 @@ -1708,7 +1708,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:10:26, endln:10:77 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ConditionalOp/dut.sv, line:1:1, endln:12:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ConditionalOp/dut.sv, line:1:1, endln:12:10 |vpiRhs: \_constant: , line:10:40, endln:10:77 |vpiDecompile:1 @@ -1723,12 +1723,12 @@ design: (work@top) |vpiTop:1 |vpiTopModule:1 |uhdmtopModules: -\_module: work@ibex_register_file (work@ibex_register_file), file:${SURELOG_DIR}/tests/ConditionalOp/dut.sv, line:14:1, endln:24:10 +\_module_inst: work@ibex_register_file (work@ibex_register_file), file:${SURELOG_DIR}/tests/ConditionalOp/dut.sv, line:14:1, endln:24:10 |vpiName:work@ibex_register_file |vpiVariables: \_logic_var: (work@ibex_register_file.rf_reg), line:21:40, endln:21:46 |vpiParent: - \_module: work@ibex_register_file (work@ibex_register_file), file:${SURELOG_DIR}/tests/ConditionalOp/dut.sv, line:14:1, endln:24:10 + \_module_inst: work@ibex_register_file (work@ibex_register_file), file:${SURELOG_DIR}/tests/ConditionalOp/dut.sv, line:14:1, endln:24:10 |vpiTypespec: \_logic_typespec: , line:21:3, endln:21:39 |vpiRange: @@ -1809,7 +1809,7 @@ design: (work@top) |vpiVariables: \_logic_var: (work@ibex_register_file.rf_reg_q), line:22:40, endln:22:48 |vpiParent: - \_module: work@ibex_register_file (work@ibex_register_file), file:${SURELOG_DIR}/tests/ConditionalOp/dut.sv, line:14:1, endln:24:10 + \_module_inst: work@ibex_register_file (work@ibex_register_file), file:${SURELOG_DIR}/tests/ConditionalOp/dut.sv, line:14:1, endln:24:10 |vpiTypespec: \_logic_typespec: , line:22:3, endln:22:39 |vpiRange: @@ -1890,7 +1890,7 @@ design: (work@top) |vpiVariables: \_logic_var: (work@ibex_register_file.we_a_dec), line:23:40, endln:23:48 |vpiParent: - \_module: work@ibex_register_file (work@ibex_register_file), file:${SURELOG_DIR}/tests/ConditionalOp/dut.sv, line:14:1, endln:24:10 + \_module_inst: work@ibex_register_file (work@ibex_register_file), file:${SURELOG_DIR}/tests/ConditionalOp/dut.sv, line:14:1, endln:24:10 |vpiTypespec: \_logic_typespec: , line:23:3, endln:23:24 |vpiRange: @@ -1935,7 +1935,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@ibex_register_file.RV32E), line:15:28, endln:15:33 |vpiParent: - \_module: work@ibex_register_file (work@ibex_register_file), file:${SURELOG_DIR}/tests/ConditionalOp/dut.sv, line:14:1, endln:24:10 + \_module_inst: work@ibex_register_file (work@ibex_register_file), file:${SURELOG_DIR}/tests/ConditionalOp/dut.sv, line:14:1, endln:24:10 |UINT:0 |vpiTypespec: \_bit_typespec: , line:15:15, endln:15:18 @@ -1947,7 +1947,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@ibex_register_file.DataWidth), line:16:28, endln:16:37 |vpiParent: - \_module: work@ibex_register_file (work@ibex_register_file), file:${SURELOG_DIR}/tests/ConditionalOp/dut.sv, line:14:1, endln:24:10 + \_module_inst: work@ibex_register_file (work@ibex_register_file), file:${SURELOG_DIR}/tests/ConditionalOp/dut.sv, line:14:1, endln:24:10 |UINT:32 |vpiTypespec: \_int_typespec: , line:16:15, endln:16:27 @@ -1958,7 +1958,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@ibex_register_file.ADDR_WIDTH), line:18:27, endln:18:37 |vpiParent: - \_module: work@ibex_register_file (work@ibex_register_file), file:${SURELOG_DIR}/tests/ConditionalOp/dut.sv, line:14:1, endln:24:10 + \_module_inst: work@ibex_register_file (work@ibex_register_file), file:${SURELOG_DIR}/tests/ConditionalOp/dut.sv, line:14:1, endln:24:10 |vpiTypespec: \_int_typespec: , line:18:14, endln:18:26 |vpiParent: @@ -1969,7 +1969,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@ibex_register_file.NUM_WORDS), line:19:27, endln:19:36 |vpiParent: - \_module: work@ibex_register_file (work@ibex_register_file), file:${SURELOG_DIR}/tests/ConditionalOp/dut.sv, line:14:1, endln:24:10 + \_module_inst: work@ibex_register_file (work@ibex_register_file), file:${SURELOG_DIR}/tests/ConditionalOp/dut.sv, line:14:1, endln:24:10 |vpiTypespec: \_int_typespec: , line:19:14, endln:19:26 |vpiParent: @@ -1980,7 +1980,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:15:28, endln:15:49 |vpiParent: - \_module: work@ibex_register_file (work@ibex_register_file), file:${SURELOG_DIR}/tests/ConditionalOp/dut.sv, line:14:1, endln:24:10 + \_module_inst: work@ibex_register_file (work@ibex_register_file), file:${SURELOG_DIR}/tests/ConditionalOp/dut.sv, line:14:1, endln:24:10 |vpiRhs: \_constant: , line:15:48, endln:15:49 |vpiDecompile:0 @@ -1994,7 +1994,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:16:28, endln:16:50 |vpiParent: - \_module: work@ibex_register_file (work@ibex_register_file), file:${SURELOG_DIR}/tests/ConditionalOp/dut.sv, line:14:1, endln:24:10 + \_module_inst: work@ibex_register_file (work@ibex_register_file), file:${SURELOG_DIR}/tests/ConditionalOp/dut.sv, line:14:1, endln:24:10 |vpiRhs: \_constant: , line:16:48, endln:16:50 |vpiDecompile:32 @@ -2008,7 +2008,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:18:27, endln:18:53 |vpiParent: - \_module: work@ibex_register_file (work@ibex_register_file), file:${SURELOG_DIR}/tests/ConditionalOp/dut.sv, line:14:1, endln:24:10 + \_module_inst: work@ibex_register_file (work@ibex_register_file), file:${SURELOG_DIR}/tests/ConditionalOp/dut.sv, line:14:1, endln:24:10 |vpiRhs: \_constant: , line:18:40, endln:18:53 |vpiDecompile:5 @@ -2022,7 +2022,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:19:27, endln:19:53 |vpiParent: - \_module: work@ibex_register_file (work@ibex_register_file), file:${SURELOG_DIR}/tests/ConditionalOp/dut.sv, line:14:1, endln:24:10 + \_module_inst: work@ibex_register_file (work@ibex_register_file), file:${SURELOG_DIR}/tests/ConditionalOp/dut.sv, line:14:1, endln:24:10 |vpiRhs: \_constant: , line:19:40, endln:19:53 |vpiDecompile:32 diff --git a/tests/Connection/Connection.log b/tests/Connection/Connection.log index dc2d3c3800..e3da99783c 100644 --- a/tests/Connection/Connection.log +++ b/tests/Connection/Connection.log @@ -60,7 +60,7 @@ io_decl 11 logic_net 12 logic_typespec 12 logic_var 1 -module 5 +module_inst 5 operation 1 package 2 port 12 @@ -489,7 +489,7 @@ design: (work@top) \_int_typespec: |vpiSigned:1 |uhdmallModules: -\_module: work@ibex_csr (work@ibex_csr), file:${SURELOG_DIR}/tests/Connection/dut.sv, line:12:1, endln:19:10 +\_module_inst: work@ibex_csr (work@ibex_csr), file:${SURELOG_DIR}/tests/Connection/dut.sv, line:12:1, endln:19:10 |vpiParent: \_design: (work@top) |vpiFullName:work@ibex_csr @@ -497,35 +497,35 @@ design: (work@top) |vpiNet: \_logic_net: (work@ibex_csr.rd_const_conn), line:14:20, endln:14:33 |vpiParent: - \_module: work@ibex_csr (work@ibex_csr), file:${SURELOG_DIR}/tests/Connection/dut.sv, line:12:1, endln:19:10 + \_module_inst: work@ibex_csr (work@ibex_csr), file:${SURELOG_DIR}/tests/Connection/dut.sv, line:12:1, endln:19:10 |vpiName:rd_const_conn |vpiFullName:work@ibex_csr.rd_const_conn |vpiNetType:36 |vpiNet: \_logic_net: (work@ibex_csr.rd_impl_conn), line:15:21, endln:15:33 |vpiParent: - \_module: work@ibex_csr (work@ibex_csr), file:${SURELOG_DIR}/tests/Connection/dut.sv, line:12:1, endln:19:10 + \_module_inst: work@ibex_csr (work@ibex_csr), file:${SURELOG_DIR}/tests/Connection/dut.sv, line:12:1, endln:19:10 |vpiName:rd_impl_conn |vpiFullName:work@ibex_csr.rd_impl_conn |vpiNetType:36 |vpiNet: \_logic_net: (work@ibex_csr.rd_name_conn), line:15:35, endln:15:47 |vpiParent: - \_module: work@ibex_csr (work@ibex_csr), file:${SURELOG_DIR}/tests/Connection/dut.sv, line:12:1, endln:19:10 + \_module_inst: work@ibex_csr (work@ibex_csr), file:${SURELOG_DIR}/tests/Connection/dut.sv, line:12:1, endln:19:10 |vpiName:rd_name_conn |vpiFullName:work@ibex_csr.rd_name_conn |vpiNetType:36 |vpiNet: \_logic_net: (work@ibex_csr.rd_disconn), line:15:49, endln:15:59 |vpiParent: - \_module: work@ibex_csr (work@ibex_csr), file:${SURELOG_DIR}/tests/Connection/dut.sv, line:12:1, endln:19:10 + \_module_inst: work@ibex_csr (work@ibex_csr), file:${SURELOG_DIR}/tests/Connection/dut.sv, line:12:1, endln:19:10 |vpiName:rd_disconn |vpiFullName:work@ibex_csr.rd_disconn |vpiNetType:36 |vpiPort: \_port: (rd_const_conn), line:14:20, endln:14:33 |vpiParent: - \_module: work@ibex_csr (work@ibex_csr), file:${SURELOG_DIR}/tests/Connection/dut.sv, line:12:1, endln:19:10 + \_module_inst: work@ibex_csr (work@ibex_csr), file:${SURELOG_DIR}/tests/Connection/dut.sv, line:12:1, endln:19:10 |vpiName:rd_const_conn |vpiDirection:1 |vpiLowConn: @@ -537,7 +537,7 @@ design: (work@top) |vpiPort: \_port: (rd_impl_conn), line:15:21, endln:15:33 |vpiParent: - \_module: work@ibex_csr (work@ibex_csr), file:${SURELOG_DIR}/tests/Connection/dut.sv, line:12:1, endln:19:10 + \_module_inst: work@ibex_csr (work@ibex_csr), file:${SURELOG_DIR}/tests/Connection/dut.sv, line:12:1, endln:19:10 |vpiName:rd_impl_conn |vpiDirection:2 |vpiLowConn: @@ -549,7 +549,7 @@ design: (work@top) |vpiPort: \_port: (rd_name_conn), line:15:35, endln:15:47 |vpiParent: - \_module: work@ibex_csr (work@ibex_csr), file:${SURELOG_DIR}/tests/Connection/dut.sv, line:12:1, endln:19:10 + \_module_inst: work@ibex_csr (work@ibex_csr), file:${SURELOG_DIR}/tests/Connection/dut.sv, line:12:1, endln:19:10 |vpiName:rd_name_conn |vpiDirection:2 |vpiLowConn: @@ -561,7 +561,7 @@ design: (work@top) |vpiPort: \_port: (rd_disconn), line:15:49, endln:15:59 |vpiParent: - \_module: work@ibex_csr (work@ibex_csr), file:${SURELOG_DIR}/tests/Connection/dut.sv, line:12:1, endln:19:10 + \_module_inst: work@ibex_csr (work@ibex_csr), file:${SURELOG_DIR}/tests/Connection/dut.sv, line:12:1, endln:19:10 |vpiName:rd_disconn |vpiDirection:2 |vpiLowConn: @@ -571,7 +571,7 @@ design: (work@top) |vpiTypedef: \_logic_typespec: , line:15:15, endln:15:20 |uhdmallModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/Connection/dut.sv, line:1:1, endln:10:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/Connection/dut.sv, line:1:1, endln:10:10 |vpiParent: \_design: (work@top) |vpiFullName:work@top @@ -579,19 +579,19 @@ design: (work@top) |vpiNet: \_logic_net: (work@top.rd_impl_conn), line:1:18, endln:1:30 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/Connection/dut.sv, line:1:1, endln:10:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/Connection/dut.sv, line:1:1, endln:10:10 |vpiName:rd_impl_conn |vpiFullName:work@top.rd_impl_conn |vpiNet: \_logic_net: (work@top.rd_name_conn), line:1:32, endln:1:44 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/Connection/dut.sv, line:1:1, endln:10:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/Connection/dut.sv, line:1:1, endln:10:10 |vpiName:rd_name_conn |vpiFullName:work@top.rd_name_conn |vpiPort: \_port: (rd_impl_conn), line:1:18, endln:1:30 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/Connection/dut.sv, line:1:1, endln:10:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/Connection/dut.sv, line:1:1, endln:10:10 |vpiName:rd_impl_conn |vpiDirection:1 |vpiLowConn: @@ -603,7 +603,7 @@ design: (work@top) |vpiPort: \_port: (rd_name_conn), line:1:32, endln:1:44 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/Connection/dut.sv, line:1:1, endln:10:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/Connection/dut.sv, line:1:1, endln:10:10 |vpiName:rd_name_conn |vpiDirection:1 |vpiLowConn: @@ -613,14 +613,14 @@ design: (work@top) |vpiTypedef: \_logic_typespec: , line:1:18, endln:1:18 |uhdmtopModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/Connection/dut.sv, line:1:1, endln:10:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/Connection/dut.sv, line:1:1, endln:10:10 |vpiName:work@top |vpiDefName:work@top |vpiTop:1 |vpiNet: \_logic_net: (work@top.rd_impl_conn), line:1:18, endln:1:30 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/Connection/dut.sv, line:1:1, endln:10:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/Connection/dut.sv, line:1:1, endln:10:10 |vpiTypespec: \_logic_typespec: , line:1:18, endln:1:18 |vpiName:rd_impl_conn @@ -628,7 +628,7 @@ design: (work@top) |vpiNet: \_logic_net: (work@top.rd_name_conn), line:1:32, endln:1:44 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/Connection/dut.sv, line:1:1, endln:10:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/Connection/dut.sv, line:1:1, endln:10:10 |vpiTypespec: \_logic_typespec: , line:1:18, endln:1:18 |vpiName:rd_name_conn @@ -637,7 +637,7 @@ design: (work@top) |vpiPort: \_port: (rd_impl_conn), line:1:18, endln:1:30 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/Connection/dut.sv, line:1:1, endln:10:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/Connection/dut.sv, line:1:1, endln:10:10 |vpiName:rd_impl_conn |vpiDirection:1 |vpiLowConn: @@ -651,7 +651,7 @@ design: (work@top) |vpiPort: \_port: (rd_name_conn), line:1:32, endln:1:44 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/Connection/dut.sv, line:1:1, endln:10:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/Connection/dut.sv, line:1:1, endln:10:10 |vpiName:rd_name_conn |vpiDirection:1 |vpiLowConn: @@ -662,10 +662,10 @@ design: (work@top) \_logic_net: (work@top.rd_name_conn), line:1:32, endln:1:44 |vpiTypedef: \_logic_typespec: , line:1:18, endln:1:18 - |vpiModule: - \_module: work@ibex_csr (work@top.u_mie_csr), file:${SURELOG_DIR}/tests/Connection/dut.sv, line:2:4, endln:8:6 + |vpiModuleInst: + \_module_inst: work@ibex_csr (work@top.u_mie_csr), file:${SURELOG_DIR}/tests/Connection/dut.sv, line:2:4, endln:8:6 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/Connection/dut.sv, line:1:1, endln:10:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/Connection/dut.sv, line:1:1, endln:10:10 |vpiName:u_mie_csr |vpiFullName:work@top.u_mie_csr |vpiDefName:work@ibex_csr @@ -674,7 +674,7 @@ design: (work@top) |vpiNet: \_logic_net: (work@top.u_mie_csr.rd_const_conn), line:14:20, endln:14:33 |vpiParent: - \_module: work@ibex_csr (work@top.u_mie_csr), file:${SURELOG_DIR}/tests/Connection/dut.sv, line:2:4, endln:8:6 + \_module_inst: work@ibex_csr (work@top.u_mie_csr), file:${SURELOG_DIR}/tests/Connection/dut.sv, line:2:4, endln:8:6 |vpiTypespec: \_logic_typespec: , line:14:14, endln:14:19 |vpiName:rd_const_conn @@ -683,7 +683,7 @@ design: (work@top) |vpiNet: \_logic_net: (work@top.u_mie_csr.rd_impl_conn), line:15:21, endln:15:33 |vpiParent: - \_module: work@ibex_csr (work@top.u_mie_csr), file:${SURELOG_DIR}/tests/Connection/dut.sv, line:2:4, endln:8:6 + \_module_inst: work@ibex_csr (work@top.u_mie_csr), file:${SURELOG_DIR}/tests/Connection/dut.sv, line:2:4, endln:8:6 |vpiTypespec: \_logic_typespec: , line:15:15, endln:15:20 |vpiName:rd_impl_conn @@ -692,7 +692,7 @@ design: (work@top) |vpiNet: \_logic_net: (work@top.u_mie_csr.rd_name_conn), line:15:35, endln:15:47 |vpiParent: - \_module: work@ibex_csr (work@top.u_mie_csr), file:${SURELOG_DIR}/tests/Connection/dut.sv, line:2:4, endln:8:6 + \_module_inst: work@ibex_csr (work@top.u_mie_csr), file:${SURELOG_DIR}/tests/Connection/dut.sv, line:2:4, endln:8:6 |vpiTypespec: \_logic_typespec: , line:15:15, endln:15:20 |vpiName:rd_name_conn @@ -701,18 +701,18 @@ design: (work@top) |vpiNet: \_logic_net: (work@top.u_mie_csr.rd_disconn), line:15:49, endln:15:59 |vpiParent: - \_module: work@ibex_csr (work@top.u_mie_csr), file:${SURELOG_DIR}/tests/Connection/dut.sv, line:2:4, endln:8:6 + \_module_inst: work@ibex_csr (work@top.u_mie_csr), file:${SURELOG_DIR}/tests/Connection/dut.sv, line:2:4, endln:8:6 |vpiTypespec: \_logic_typespec: , line:15:15, endln:15:20 |vpiName:rd_disconn |vpiFullName:work@top.u_mie_csr.rd_disconn |vpiNetType:36 |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/Connection/dut.sv, line:1:1, endln:10:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/Connection/dut.sv, line:1:1, endln:10:10 |vpiPort: \_port: (rd_const_conn), line:14:20, endln:14:33 |vpiParent: - \_module: work@ibex_csr (work@top.u_mie_csr), file:${SURELOG_DIR}/tests/Connection/dut.sv, line:2:4, endln:8:6 + \_module_inst: work@ibex_csr (work@top.u_mie_csr), file:${SURELOG_DIR}/tests/Connection/dut.sv, line:2:4, endln:8:6 |vpiName:rd_const_conn |vpiDirection:1 |vpiHighConn: @@ -732,7 +732,7 @@ design: (work@top) |vpiPort: \_port: (rd_impl_conn), line:15:21, endln:15:33 |vpiParent: - \_module: work@ibex_csr (work@top.u_mie_csr), file:${SURELOG_DIR}/tests/Connection/dut.sv, line:2:4, endln:8:6 + \_module_inst: work@ibex_csr (work@top.u_mie_csr), file:${SURELOG_DIR}/tests/Connection/dut.sv, line:2:4, endln:8:6 |vpiName:rd_impl_conn |vpiDirection:2 |vpiHighConn: @@ -752,7 +752,7 @@ design: (work@top) |vpiPort: \_port: (rd_name_conn), line:15:35, endln:15:47 |vpiParent: - \_module: work@ibex_csr (work@top.u_mie_csr), file:${SURELOG_DIR}/tests/Connection/dut.sv, line:2:4, endln:8:6 + \_module_inst: work@ibex_csr (work@top.u_mie_csr), file:${SURELOG_DIR}/tests/Connection/dut.sv, line:2:4, endln:8:6 |vpiName:rd_name_conn |vpiDirection:2 |vpiHighConn: @@ -772,7 +772,7 @@ design: (work@top) |vpiPort: \_port: (rd_disconn), line:15:49, endln:15:59 |vpiParent: - \_module: work@ibex_csr (work@top.u_mie_csr), file:${SURELOG_DIR}/tests/Connection/dut.sv, line:2:4, endln:8:6 + \_module_inst: work@ibex_csr (work@top.u_mie_csr), file:${SURELOG_DIR}/tests/Connection/dut.sv, line:2:4, endln:8:6 |vpiName:rd_disconn |vpiDirection:2 |vpiHighConn: diff --git a/tests/ConstCapital/ConstCapital.log b/tests/ConstCapital/ConstCapital.log index 4ff5adc116..dfab804365 100644 --- a/tests/ConstCapital/ConstCapital.log +++ b/tests/ConstCapital/ConstCapital.log @@ -141,7 +141,7 @@ gen_scope 4 gen_scope_array 4 int_typespec 7 logic_net 2 -module 7 +module_inst 7 operation 2 param_assign 4 parameter 4 @@ -156,7 +156,7 @@ gen_scope 6 gen_scope_array 6 int_typespec 7 logic_net 2 -module 9 +module_inst 9 operation 2 param_assign 4 parameter 4 @@ -175,13 +175,13 @@ design: (work@test) |vpiElaborated:1 |vpiName:work@test |uhdmallModules: -\_module: work@GOOD (work@GOOD), file:${SURELOG_DIR}/tests/ConstCapital/dut.sv, line:4:1, endln:5:10 +\_module_inst: work@GOOD (work@GOOD), file:${SURELOG_DIR}/tests/ConstCapital/dut.sv, line:4:1, endln:5:10 |vpiParent: \_design: (work@test) |vpiFullName:work@GOOD |vpiDefName:work@GOOD |uhdmallModules: -\_module: work@test (work@test), file:${SURELOG_DIR}/tests/ConstCapital/dut.sv, line:8:1, endln:19:10 +\_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/ConstCapital/dut.sv, line:8:1, endln:19:10 |vpiParent: \_design: (work@test) |vpiFullName:work@test @@ -239,7 +239,7 @@ design: (work@test) |vpiLhs: \_parameter: (foo2), line:2:15, endln:2:19 |uhdmtopModules: -\_module: work@test (work@test), file:${SURELOG_DIR}/tests/ConstCapital/dut.sv, line:8:1, endln:19:10 +\_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/ConstCapital/dut.sv, line:8:1, endln:19:10 |vpiName:work@test |vpiDefName:work@test |vpiTop:1 @@ -255,7 +255,7 @@ design: (work@test) |vpiGenScopeArray: \_gen_scope_array: (work@test.genblk1), line:10:1, endln:12:4 |vpiParent: - \_module: work@test (work@test), file:${SURELOG_DIR}/tests/ConstCapital/dut.sv, line:8:1, endln:19:10 + \_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/ConstCapital/dut.sv, line:8:1, endln:19:10 |vpiName:genblk1 |vpiFullName:work@test.genblk1 |vpiGenScope: @@ -263,8 +263,8 @@ design: (work@test) |vpiParent: \_gen_scope_array: (work@test.genblk1), line:10:1, endln:12:4 |vpiFullName:work@test.genblk1 - |vpiModule: - \_module: work@GOOD (work@test.genblk1.good1), file:${SURELOG_DIR}/tests/ConstCapital/dut.sv, line:11:9, endln:11:22 + |vpiModuleInst: + \_module_inst: work@GOOD (work@test.genblk1.good1), file:${SURELOG_DIR}/tests/ConstCapital/dut.sv, line:11:9, endln:11:22 |vpiParent: \_gen_scope: (work@test.genblk1) |vpiName:good1 @@ -275,7 +275,7 @@ design: (work@test) |vpiGenScopeArray: \_gen_scope_array: (work@test.genblk2), line:15:1, endln:17:4 |vpiParent: - \_module: work@test (work@test), file:${SURELOG_DIR}/tests/ConstCapital/dut.sv, line:8:1, endln:19:10 + \_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/ConstCapital/dut.sv, line:8:1, endln:19:10 |vpiName:genblk2 |vpiFullName:work@test.genblk2 |vpiGenScope: @@ -283,8 +283,8 @@ design: (work@test) |vpiParent: \_gen_scope_array: (work@test.genblk2), line:15:1, endln:17:4 |vpiFullName:work@test.genblk2 - |vpiModule: - \_module: work@GOOD (work@test.genblk2.good2), file:${SURELOG_DIR}/tests/ConstCapital/dut.sv, line:16:9, endln:16:22 + |vpiModuleInst: + \_module_inst: work@GOOD (work@test.genblk2.good2), file:${SURELOG_DIR}/tests/ConstCapital/dut.sv, line:16:9, endln:16:22 |vpiParent: \_gen_scope: (work@test.genblk2) |vpiName:good2 diff --git a/tests/ConstExpand/ConstExpand.log b/tests/ConstExpand/ConstExpand.log index 3e58dd2819..50b911a57c 100644 --- a/tests/ConstExpand/ConstExpand.log +++ b/tests/ConstExpand/ConstExpand.log @@ -177,7 +177,7 @@ indexed_part_select 1 int_typespec 5 int_var 1 logic_net 2 -module 3 +module_inst 3 operation 2 port 2 ref_obj 6 @@ -202,7 +202,7 @@ indexed_part_select 2 int_typespec 5 int_var 1 logic_net 2 -module 3 +module_inst 3 operation 2 port 3 ref_obj 11 @@ -225,17 +225,17 @@ design: (work@top) |vpiElaborated:1 |vpiName:work@top |uhdmallModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/ConstExpand/dut.sv, line:1:1, endln:15:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ConstExpand/dut.sv, line:1:1, endln:15:10 |vpiParent: \_design: (work@top) |vpiFullName:work@top |vpiTypedef: \_struct_typespec: (mac_bignum_operation_t), line:2:12, endln:2:18 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ConstExpand/dut.sv, line:1:1, endln:15:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ConstExpand/dut.sv, line:1:1, endln:15:10 |vpiName:mac_bignum_operation_t |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ConstExpand/dut.sv, line:1:1, endln:15:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ConstExpand/dut.sv, line:1:1, endln:15:10 |vpiPacked:1 |vpiTypespecMember: \_typespec_member: (operand_a), line:3:11, endln:3:20 @@ -271,19 +271,19 @@ design: (work@top) |vpiNet: \_logic_net: (work@top.o), line:1:23, endln:1:24 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ConstExpand/dut.sv, line:1:1, endln:15:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ConstExpand/dut.sv, line:1:1, endln:15:10 |vpiName:o |vpiFullName:work@top.o |vpiNet: \_logic_net: (work@top.operation_i), line:7:27, endln:7:38 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ConstExpand/dut.sv, line:1:1, endln:15:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ConstExpand/dut.sv, line:1:1, endln:15:10 |vpiName:operation_i |vpiFullName:work@top.operation_i |vpiPort: \_port: (o), line:1:23, endln:1:24 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ConstExpand/dut.sv, line:1:1, endln:15:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ConstExpand/dut.sv, line:1:1, endln:15:10 |vpiName:o |vpiDirection:2 |vpiLowConn: @@ -296,7 +296,7 @@ design: (work@top) |vpiProcess: \_always: , line:9:4, endln:14:7 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ConstExpand/dut.sv, line:1:1, endln:15:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ConstExpand/dut.sv, line:1:1, endln:15:10 |vpiStmt: \_begin: (work@top), line:9:16, endln:14:7 |vpiParent: @@ -399,12 +399,12 @@ design: (work@top) \_int_var: (work@top.o), line:1:23, endln:1:24 |vpiAlwaysType:2 |uhdmtopModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/ConstExpand/dut.sv, line:1:1, endln:15:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ConstExpand/dut.sv, line:1:1, endln:15:10 |vpiName:work@top |vpiVariables: \_int_var: (work@top.o), line:1:23, endln:1:24 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ConstExpand/dut.sv, line:1:1, endln:15:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ConstExpand/dut.sv, line:1:1, endln:15:10 |vpiTypespec: \_int_typespec: , line:1:19, endln:1:22 |vpiSigned:1 @@ -415,7 +415,7 @@ design: (work@top) |vpiVariables: \_struct_var: (work@top.operation_i), line:7:27, endln:7:38 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ConstExpand/dut.sv, line:1:1, endln:15:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ConstExpand/dut.sv, line:1:1, endln:15:10 |vpiTypespec: \_struct_typespec: (mac_bignum_operation_t), line:2:12, endln:2:18 |vpiName:operation_i @@ -446,7 +446,7 @@ design: (work@top) |vpiPort: \_port: (o), line:1:23, endln:1:24 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ConstExpand/dut.sv, line:1:1, endln:15:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ConstExpand/dut.sv, line:1:1, endln:15:10 |vpiName:o |vpiDirection:2 |vpiLowConn: @@ -461,11 +461,11 @@ design: (work@top) \_int_typespec: , line:1:19, endln:1:22 |vpiSigned:1 |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ConstExpand/dut.sv, line:1:1, endln:15:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ConstExpand/dut.sv, line:1:1, endln:15:10 |vpiProcess: \_always: , line:9:4, endln:14:7 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ConstExpand/dut.sv, line:1:1, endln:15:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ConstExpand/dut.sv, line:1:1, endln:15:10 |vpiStmt: \_begin: (work@top), line:9:16, endln:14:7 |vpiParent: diff --git a/tests/ConstHighConn/ConstHighConn.log b/tests/ConstHighConn/ConstHighConn.log index aaabc53f68..daf0f94c95 100644 --- a/tests/ConstHighConn/ConstHighConn.log +++ b/tests/ConstHighConn/ConstHighConn.log @@ -95,7 +95,7 @@ cont_assign 2 design 1 logic_net 4 logic_typespec 6 -module 6 +module_inst 6 port 4 ref_obj 6 === UHDM Object Stats End === @@ -107,7 +107,7 @@ cont_assign 3 design 1 logic_net 4 logic_typespec 6 -module 6 +module_inst 6 port 6 ref_obj 9 === UHDM Object Stats End === @@ -124,7 +124,7 @@ design: (work@top) |vpiElaborated:1 |vpiName:work@top |uhdmallModules: -\_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/ConstHighConn/dut.sv, line:1:1, endln:3:10 +\_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/ConstHighConn/dut.sv, line:1:1, endln:3:10 |vpiParent: \_design: (work@top) |vpiFullName:work@dut @@ -132,14 +132,14 @@ design: (work@top) |vpiNet: \_logic_net: (work@dut.o), line:1:26, endln:1:27 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/ConstHighConn/dut.sv, line:1:1, endln:3:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/ConstHighConn/dut.sv, line:1:1, endln:3:10 |vpiName:o |vpiFullName:work@dut.o |vpiNetType:36 |vpiPort: \_port: (o), line:1:26, endln:1:27 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/ConstHighConn/dut.sv, line:1:1, endln:3:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/ConstHighConn/dut.sv, line:1:1, endln:3:10 |vpiName:o |vpiDirection:2 |vpiLowConn: @@ -151,7 +151,7 @@ design: (work@top) |vpiContAssign: \_cont_assign: , line:2:11, endln:2:19 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/ConstHighConn/dut.sv, line:1:1, endln:3:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/ConstHighConn/dut.sv, line:1:1, endln:3:10 |vpiRhs: \_constant: , line:2:15, endln:2:19 |vpiParent: @@ -169,7 +169,7 @@ design: (work@top) |vpiActual: \_logic_net: (work@top.d.o), line:1:26, endln:1:27 |uhdmallModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/ConstHighConn/dut.sv, line:5:1, endln:9:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ConstHighConn/dut.sv, line:5:1, endln:9:10 |vpiParent: \_design: (work@top) |vpiFullName:work@top @@ -177,14 +177,14 @@ design: (work@top) |vpiNet: \_logic_net: (work@top.o), line:5:26, endln:5:27 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ConstHighConn/dut.sv, line:5:1, endln:9:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ConstHighConn/dut.sv, line:5:1, endln:9:10 |vpiName:o |vpiFullName:work@top.o |vpiNetType:36 |vpiPort: \_port: (o), line:5:26, endln:5:27 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ConstHighConn/dut.sv, line:5:1, endln:9:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ConstHighConn/dut.sv, line:5:1, endln:9:10 |vpiName:o |vpiDirection:2 |vpiLowConn: @@ -194,14 +194,14 @@ design: (work@top) |vpiTypedef: \_logic_typespec: , line:5:20, endln:5:25 |uhdmtopModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/ConstHighConn/dut.sv, line:5:1, endln:9:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ConstHighConn/dut.sv, line:5:1, endln:9:10 |vpiName:work@top |vpiDefName:work@top |vpiTop:1 |vpiNet: \_logic_net: (work@top.o), line:5:26, endln:5:27 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ConstHighConn/dut.sv, line:5:1, endln:9:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ConstHighConn/dut.sv, line:5:1, endln:9:10 |vpiTypespec: \_logic_typespec: , line:5:20, endln:5:25 |vpiName:o @@ -211,7 +211,7 @@ design: (work@top) |vpiPort: \_port: (o), line:5:26, endln:5:27 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ConstHighConn/dut.sv, line:5:1, endln:9:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ConstHighConn/dut.sv, line:5:1, endln:9:10 |vpiName:o |vpiDirection:2 |vpiLowConn: @@ -225,11 +225,11 @@ design: (work@top) |vpiTypedef: \_logic_typespec: , line:5:20, endln:5:25 |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ConstHighConn/dut.sv, line:5:1, endln:9:10 - |vpiModule: - \_module: work@dut (work@top.d), file:${SURELOG_DIR}/tests/ConstHighConn/dut.sv, line:7:4, endln:7:21 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ConstHighConn/dut.sv, line:5:1, endln:9:10 + |vpiModuleInst: + \_module_inst: work@dut (work@top.d), file:${SURELOG_DIR}/tests/ConstHighConn/dut.sv, line:7:4, endln:7:21 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ConstHighConn/dut.sv, line:5:1, endln:9:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ConstHighConn/dut.sv, line:5:1, endln:9:10 |vpiName:d |vpiFullName:work@top.d |vpiDefName:work@dut @@ -238,18 +238,18 @@ design: (work@top) |vpiNet: \_logic_net: (work@top.d.o), line:1:26, endln:1:27 |vpiParent: - \_module: work@dut (work@top.d), file:${SURELOG_DIR}/tests/ConstHighConn/dut.sv, line:7:4, endln:7:21 + \_module_inst: work@dut (work@top.d), file:${SURELOG_DIR}/tests/ConstHighConn/dut.sv, line:7:4, endln:7:21 |vpiTypespec: \_logic_typespec: , line:1:20, endln:1:25 |vpiName:o |vpiFullName:work@top.d.o |vpiNetType:36 |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ConstHighConn/dut.sv, line:5:1, endln:9:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ConstHighConn/dut.sv, line:5:1, endln:9:10 |vpiPort: \_port: (o), line:1:26, endln:1:27 |vpiParent: - \_module: work@dut (work@top.d), file:${SURELOG_DIR}/tests/ConstHighConn/dut.sv, line:7:4, endln:7:21 + \_module_inst: work@dut (work@top.d), file:${SURELOG_DIR}/tests/ConstHighConn/dut.sv, line:7:4, endln:7:21 |vpiName:o |vpiDirection:2 |vpiHighConn: @@ -269,11 +269,11 @@ design: (work@top) |vpiTypedef: \_logic_typespec: , line:1:20, endln:1:25 |vpiInstance: - \_module: work@dut (work@top.d), file:${SURELOG_DIR}/tests/ConstHighConn/dut.sv, line:7:4, endln:7:21 + \_module_inst: work@dut (work@top.d), file:${SURELOG_DIR}/tests/ConstHighConn/dut.sv, line:7:4, endln:7:21 |vpiContAssign: \_cont_assign: , line:2:11, endln:2:19 |vpiParent: - \_module: work@dut (work@top.d), file:${SURELOG_DIR}/tests/ConstHighConn/dut.sv, line:7:4, endln:7:21 + \_module_inst: work@dut (work@top.d), file:${SURELOG_DIR}/tests/ConstHighConn/dut.sv, line:7:4, endln:7:21 |vpiRhs: \_constant: , line:2:15, endln:2:19 |vpiLhs: diff --git a/tests/ConstPort/ConstPort.log b/tests/ConstPort/ConstPort.log index 365c404fae..b8941d0a91 100644 --- a/tests/ConstPort/ConstPort.log +++ b/tests/ConstPort/ConstPort.log @@ -37,7 +37,7 @@ enum_var 2 import_typespec 1 logic_net 2 logic_typespec 2 -module 7 +module_inst 7 package 3 port 4 ref_obj 4 @@ -53,7 +53,7 @@ enum_var 2 import_typespec 1 logic_net 2 logic_typespec 2 -module 7 +module_inst 7 package 3 port 6 ref_obj 6 @@ -109,7 +109,7 @@ design: (work@cipher_core) |vpiTypedef: \_enum_typespec: (aes_pkg::ciph_op_e), line:2:1, endln:5:13 |vpiParent: - \_module: work@cipher_core (work@cipher_core), file:${SURELOG_DIR}/tests/ConstPort/dut.sv, line:13:1, endln:20:10 + \_module_inst: work@cipher_core (work@cipher_core), file:${SURELOG_DIR}/tests/ConstPort/dut.sv, line:13:1, endln:20:10 |vpiName:aes_pkg::ciph_op_e |vpiInstance: \_package: aes_pkg (aes_pkg::), file:${SURELOG_DIR}/tests/ConstPort/dut.sv, line:1:1, endln:6:11 @@ -132,7 +132,7 @@ design: (work@cipher_core) |vpiDefName:aes_pkg |vpiTop:1 |uhdmallModules: -\_module: work@cipher_core (work@cipher_core), file:${SURELOG_DIR}/tests/ConstPort/dut.sv, line:13:1, endln:20:10 +\_module_inst: work@cipher_core (work@cipher_core), file:${SURELOG_DIR}/tests/ConstPort/dut.sv, line:13:1, endln:20:10 |vpiParent: \_design: (work@cipher_core) |vpiFullName:work@cipher_core @@ -144,13 +144,13 @@ design: (work@cipher_core) |vpiNet: \_logic_net: (work@cipher_core.op_i), line:14:32, endln:14:36 |vpiParent: - \_module: work@cipher_core (work@cipher_core), file:${SURELOG_DIR}/tests/ConstPort/dut.sv, line:13:1, endln:20:10 + \_module_inst: work@cipher_core (work@cipher_core), file:${SURELOG_DIR}/tests/ConstPort/dut.sv, line:13:1, endln:20:10 |vpiName:op_i |vpiFullName:work@cipher_core.op_i |vpiPort: \_port: (op_i), line:14:32, endln:14:36 |vpiParent: - \_module: work@cipher_core (work@cipher_core), file:${SURELOG_DIR}/tests/ConstPort/dut.sv, line:13:1, endln:20:10 + \_module_inst: work@cipher_core (work@cipher_core), file:${SURELOG_DIR}/tests/ConstPort/dut.sv, line:13:1, endln:20:10 |vpiName:op_i |vpiDirection:1 |vpiLowConn: @@ -160,7 +160,7 @@ design: (work@cipher_core) |vpiTypedef: \_enum_typespec: (aes_pkg::ciph_op_e), line:2:1, endln:5:13 |uhdmallModules: -\_module: work@mix_columns (work@mix_columns), file:${SURELOG_DIR}/tests/ConstPort/dut.sv, line:8:1, endln:11:10 +\_module_inst: work@mix_columns (work@mix_columns), file:${SURELOG_DIR}/tests/ConstPort/dut.sv, line:8:1, endln:11:10 |vpiParent: \_design: (work@cipher_core) |vpiFullName:work@mix_columns @@ -168,13 +168,13 @@ design: (work@cipher_core) |vpiNet: \_logic_net: (work@mix_columns.op_i), line:9:32, endln:9:36 |vpiParent: - \_module: work@mix_columns (work@mix_columns), file:${SURELOG_DIR}/tests/ConstPort/dut.sv, line:8:1, endln:11:10 + \_module_inst: work@mix_columns (work@mix_columns), file:${SURELOG_DIR}/tests/ConstPort/dut.sv, line:8:1, endln:11:10 |vpiName:op_i |vpiFullName:work@mix_columns.op_i |vpiPort: \_port: (op_i), line:9:32, endln:9:36 |vpiParent: - \_module: work@mix_columns (work@mix_columns), file:${SURELOG_DIR}/tests/ConstPort/dut.sv, line:8:1, endln:11:10 + \_module_inst: work@mix_columns (work@mix_columns), file:${SURELOG_DIR}/tests/ConstPort/dut.sv, line:8:1, endln:11:10 |vpiName:op_i |vpiDirection:1 |vpiLowConn: @@ -184,12 +184,12 @@ design: (work@cipher_core) |vpiTypedef: \_enum_typespec: (aes_pkg::ciph_op_e), line:2:1, endln:5:13 |uhdmtopModules: -\_module: work@cipher_core (work@cipher_core), file:${SURELOG_DIR}/tests/ConstPort/dut.sv, line:13:1, endln:20:10 +\_module_inst: work@cipher_core (work@cipher_core), file:${SURELOG_DIR}/tests/ConstPort/dut.sv, line:13:1, endln:20:10 |vpiName:work@cipher_core |vpiVariables: \_enum_var: (work@cipher_core.op_i), line:14:32, endln:14:36 |vpiParent: - \_module: work@cipher_core (work@cipher_core), file:${SURELOG_DIR}/tests/ConstPort/dut.sv, line:13:1, endln:20:10 + \_module_inst: work@cipher_core (work@cipher_core), file:${SURELOG_DIR}/tests/ConstPort/dut.sv, line:13:1, endln:20:10 |vpiTypespec: \_enum_typespec: (aes_pkg::ciph_op_e), line:2:1, endln:5:13 |vpiName:op_i @@ -205,7 +205,7 @@ design: (work@cipher_core) |vpiPort: \_port: (op_i), line:14:32, endln:14:36 |vpiParent: - \_module: work@cipher_core (work@cipher_core), file:${SURELOG_DIR}/tests/ConstPort/dut.sv, line:13:1, endln:20:10 + \_module_inst: work@cipher_core (work@cipher_core), file:${SURELOG_DIR}/tests/ConstPort/dut.sv, line:13:1, endln:20:10 |vpiName:op_i |vpiDirection:1 |vpiLowConn: @@ -219,17 +219,17 @@ design: (work@cipher_core) |vpiTypedef: \_enum_typespec: (aes_pkg::ciph_op_e), line:2:1, endln:5:13 |vpiInstance: - \_module: work@cipher_core (work@cipher_core), file:${SURELOG_DIR}/tests/ConstPort/dut.sv, line:13:1, endln:20:10 - |vpiModule: - \_module: work@mix_columns (work@cipher_core.key_mix_columns), file:${SURELOG_DIR}/tests/ConstPort/dut.sv, line:17:3, endln:19:5 + \_module_inst: work@cipher_core (work@cipher_core), file:${SURELOG_DIR}/tests/ConstPort/dut.sv, line:13:1, endln:20:10 + |vpiModuleInst: + \_module_inst: work@mix_columns (work@cipher_core.key_mix_columns), file:${SURELOG_DIR}/tests/ConstPort/dut.sv, line:17:3, endln:19:5 |vpiParent: - \_module: work@cipher_core (work@cipher_core), file:${SURELOG_DIR}/tests/ConstPort/dut.sv, line:13:1, endln:20:10 + \_module_inst: work@cipher_core (work@cipher_core), file:${SURELOG_DIR}/tests/ConstPort/dut.sv, line:13:1, endln:20:10 |vpiName:key_mix_columns |vpiFullName:work@cipher_core.key_mix_columns |vpiVariables: \_enum_var: (work@cipher_core.key_mix_columns.op_i), line:9:32, endln:9:36 |vpiParent: - \_module: work@mix_columns (work@cipher_core.key_mix_columns), file:${SURELOG_DIR}/tests/ConstPort/dut.sv, line:17:3, endln:19:5 + \_module_inst: work@mix_columns (work@cipher_core.key_mix_columns), file:${SURELOG_DIR}/tests/ConstPort/dut.sv, line:17:3, endln:19:5 |vpiTypespec: \_enum_typespec: (aes_pkg::ciph_op_e), line:2:1, endln:5:13 |vpiName:op_i @@ -239,11 +239,11 @@ design: (work@cipher_core) |vpiDefFile:${SURELOG_DIR}/tests/ConstPort/dut.sv |vpiDefLineNo:8 |vpiInstance: - \_module: work@cipher_core (work@cipher_core), file:${SURELOG_DIR}/tests/ConstPort/dut.sv, line:13:1, endln:20:10 + \_module_inst: work@cipher_core (work@cipher_core), file:${SURELOG_DIR}/tests/ConstPort/dut.sv, line:13:1, endln:20:10 |vpiPort: \_port: (op_i), line:9:32, endln:9:36 |vpiParent: - \_module: work@mix_columns (work@cipher_core.key_mix_columns), file:${SURELOG_DIR}/tests/ConstPort/dut.sv, line:17:3, endln:19:5 + \_module_inst: work@mix_columns (work@cipher_core.key_mix_columns), file:${SURELOG_DIR}/tests/ConstPort/dut.sv, line:17:3, endln:19:5 |vpiName:op_i |vpiDirection:1 |vpiHighConn: @@ -263,7 +263,7 @@ design: (work@cipher_core) |vpiTypedef: \_enum_typespec: (aes_pkg::ciph_op_e), line:2:1, endln:5:13 |vpiInstance: - \_module: work@mix_columns (work@cipher_core.key_mix_columns), file:${SURELOG_DIR}/tests/ConstPort/dut.sv, line:17:3, endln:19:5 + \_module_inst: work@mix_columns (work@cipher_core.key_mix_columns), file:${SURELOG_DIR}/tests/ConstPort/dut.sv, line:17:3, endln:19:5 =================== [ FATAL] : 0 [ SYNTAX] : 0 diff --git a/tests/ConstantBits/ConstantBits.log b/tests/ConstantBits/ConstantBits.log index 5cd5f63956..b26bf0f623 100644 --- a/tests/ConstantBits/ConstantBits.log +++ b/tests/ConstantBits/ConstantBits.log @@ -169,7 +169,7 @@ design 1 logic_net 2 logic_typespec 9 logic_var 1 -module 4 +module_inst 4 operation 4 part_select 2 range 4 @@ -187,7 +187,7 @@ design 1 logic_net 2 logic_typespec 9 logic_var 1 -module 4 +module_inst 4 operation 6 part_select 3 range 4 @@ -209,17 +209,17 @@ design: (work@dut) |vpiElaborated:1 |vpiName:work@dut |uhdmallModules: -\_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/ConstantBits/dut.sv, line:1:1, endln:12:10 +\_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/ConstantBits/dut.sv, line:1:1, endln:12:10 |vpiParent: \_design: (work@dut) |vpiFullName:work@dut |vpiTypedef: \_struct_typespec: (cpu_ctrl_t), line:3:17, endln:3:23 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/ConstantBits/dut.sv, line:1:1, endln:12:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/ConstantBits/dut.sv, line:1:1, endln:12:10 |vpiName:cpu_ctrl_t |vpiInstance: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/ConstantBits/dut.sv, line:1:1, endln:12:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/ConstantBits/dut.sv, line:1:1, endln:12:10 |vpiPacked:1 |vpiTypespecMember: \_typespec_member: (dummy_instr_mask), line:4:24, endln:4:40 @@ -301,20 +301,20 @@ design: (work@dut) |vpiNet: \_logic_net: (work@dut.cpuctrl_wdata), line:9:22, endln:9:35 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/ConstantBits/dut.sv, line:1:1, endln:12:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/ConstantBits/dut.sv, line:1:1, endln:12:10 |vpiName:cpuctrl_wdata |vpiFullName:work@dut.cpuctrl_wdata |vpiNet: \_logic_net: (work@dut.csr_wdata_int), line:10:22, endln:10:35 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/ConstantBits/dut.sv, line:1:1, endln:12:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/ConstantBits/dut.sv, line:1:1, endln:12:10 |vpiName:csr_wdata_int |vpiFullName:work@dut.csr_wdata_int |vpiNetType:36 |vpiContAssign: \_cont_assign: , line:11:16, endln:11:81 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/ConstantBits/dut.sv, line:1:1, endln:12:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/ConstantBits/dut.sv, line:1:1, endln:12:10 |vpiRhs: \_operation: , line:11:32, endln:11:81 |vpiParent: @@ -366,12 +366,12 @@ design: (work@dut) |vpiActual: \_struct_net: (work@dut.cpuctrl_wdata), line:9:22, endln:9:35 |uhdmtopModules: -\_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/ConstantBits/dut.sv, line:1:1, endln:12:10 +\_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/ConstantBits/dut.sv, line:1:1, endln:12:10 |vpiName:work@dut |vpiVariables: \_logic_var: (work@dut.csr_wdata_int), line:10:22, endln:10:35 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/ConstantBits/dut.sv, line:1:1, endln:12:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/ConstantBits/dut.sv, line:1:1, endln:12:10 |vpiTypespec: \_logic_typespec: , line:10:9, endln:10:21 |vpiRange: @@ -420,7 +420,7 @@ design: (work@dut) |vpiNet: \_struct_net: (work@dut.cpuctrl_wdata), line:9:22, endln:9:35 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/ConstantBits/dut.sv, line:1:1, endln:12:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/ConstantBits/dut.sv, line:1:1, endln:12:10 |vpiTypespec: \_struct_typespec: (cpu_ctrl_t), line:3:17, endln:3:23 |vpiName:cpuctrl_wdata @@ -429,7 +429,7 @@ design: (work@dut) |vpiContAssign: \_cont_assign: , line:11:16, endln:11:81 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/ConstantBits/dut.sv, line:1:1, endln:12:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/ConstantBits/dut.sv, line:1:1, endln:12:10 |vpiRhs: \_operation: , line:11:32, endln:11:81 |vpiParent: @@ -440,7 +440,7 @@ design: (work@dut) \_operation: , line:11:32, endln:11:81 |vpiName:cpu_ctrl_t |vpiInstance: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/ConstantBits/dut.sv, line:1:1, endln:12:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/ConstantBits/dut.sv, line:1:1, endln:12:10 |vpiPacked:1 |vpiTypespecMember: \_typespec_member: (dummy_instr_mask), line:4:24, endln:4:40 diff --git a/tests/ConstantRange/ConstantRange.log b/tests/ConstantRange/ConstantRange.log index 077d5635f3..c1ed29a417 100644 --- a/tests/ConstantRange/ConstantRange.log +++ b/tests/ConstantRange/ConstantRange.log @@ -261,7 +261,7 @@ gen_scope 24 gen_scope_array 24 int_typespec 23 logic_typespec 21 -module 10 +module_inst 10 operation 21 param_assign 6 parameter 14 @@ -278,7 +278,7 @@ gen_scope 36 gen_scope_array 36 int_typespec 23 logic_typespec 21 -module 14 +module_inst 14 operation 21 param_assign 6 parameter 14 @@ -298,20 +298,20 @@ design: (work@dut) |vpiElaborated:1 |vpiName:work@dut |uhdmallModules: -\_module: work@GOOD (work@GOOD), file:${SURELOG_DIR}/tests/ConstantRange/dut.sv, line:1:1, endln:3:10 +\_module_inst: work@GOOD (work@GOOD), file:${SURELOG_DIR}/tests/ConstantRange/dut.sv, line:1:1, endln:3:10 |vpiParent: \_design: (work@dut) |vpiFullName:work@GOOD |vpiDefName:work@GOOD |uhdmallModules: -\_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/ConstantRange/dut.sv, line:6:1, endln:21:10 +\_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/ConstantRange/dut.sv, line:6:1, endln:21:10 |vpiParent: \_design: (work@dut) |vpiFullName:work@dut |vpiParameter: \_parameter: (work@dut.NMioPads), line:7:15, endln:7:23 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/ConstantRange/dut.sv, line:6:1, endln:21:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/ConstantRange/dut.sv, line:6:1, endln:21:10 |UINT:8 |vpiTypespec: \_int_typespec: , line:7:11, endln:7:14 @@ -324,7 +324,7 @@ design: (work@dut) |vpiParameter: \_parameter: (work@dut.ConnectDioIn), line:8:34, endln:8:46 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/ConstantRange/dut.sv, line:6:1, endln:21:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/ConstantRange/dut.sv, line:6:1, endln:21:10 |BIN:11110000 |vpiTypespec: \_logic_typespec: , line:8:11, endln:8:33 @@ -363,7 +363,7 @@ design: (work@dut) |vpiParameter: \_parameter: (work@dut.ConnectDioOut), line:9:34, endln:9:47 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/ConstantRange/dut.sv, line:6:1, endln:21:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/ConstantRange/dut.sv, line:6:1, endln:21:10 |BIN:11110000 |vpiTypespec: \_logic_typespec: , line:9:11, endln:9:33 @@ -402,7 +402,7 @@ design: (work@dut) |vpiParamAssign: \_param_assign: , line:7:15, endln:7:27 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/ConstantRange/dut.sv, line:6:1, endln:21:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/ConstantRange/dut.sv, line:6:1, endln:21:10 |vpiRhs: \_constant: , line:7:26, endln:7:27 |vpiDecompile:8 @@ -416,7 +416,7 @@ design: (work@dut) |vpiParamAssign: \_param_assign: , line:8:34, endln:8:60 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/ConstantRange/dut.sv, line:6:1, endln:21:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/ConstantRange/dut.sv, line:6:1, endln:21:10 |vpiRhs: \_constant: , line:8:49, endln:8:60 |vpiDecompile:8'b11110000 @@ -430,7 +430,7 @@ design: (work@dut) |vpiParamAssign: \_param_assign: , line:9:34, endln:9:61 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/ConstantRange/dut.sv, line:6:1, endln:21:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/ConstantRange/dut.sv, line:6:1, endln:21:10 |vpiRhs: \_constant: , line:9:50, endln:9:61 |vpiDecompile:8'b11110000 @@ -443,12 +443,12 @@ design: (work@dut) \_parameter: (work@dut.ConnectDioOut), line:9:34, endln:9:47 |vpiDefName:work@dut |uhdmtopModules: -\_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/ConstantRange/dut.sv, line:6:1, endln:21:10 +\_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/ConstantRange/dut.sv, line:6:1, endln:21:10 |vpiName:work@dut |vpiParameter: \_parameter: (work@dut.NMioPads), line:7:15, endln:7:23 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/ConstantRange/dut.sv, line:6:1, endln:21:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/ConstantRange/dut.sv, line:6:1, endln:21:10 |UINT:8 |vpiTypespec: \_int_typespec: , line:7:11, endln:7:14 @@ -461,7 +461,7 @@ design: (work@dut) |vpiParameter: \_parameter: (work@dut.ConnectDioIn), line:8:34, endln:8:46 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/ConstantRange/dut.sv, line:6:1, endln:21:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/ConstantRange/dut.sv, line:6:1, endln:21:10 |BIN:11110000 |vpiTypespec: \_logic_typespec: , line:8:11, endln:8:33 @@ -505,7 +505,7 @@ design: (work@dut) |vpiParameter: \_parameter: (work@dut.ConnectDioOut), line:9:34, endln:9:47 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/ConstantRange/dut.sv, line:6:1, endln:21:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/ConstantRange/dut.sv, line:6:1, endln:21:10 |BIN:11110000 |vpiTypespec: \_logic_typespec: , line:9:11, endln:9:33 @@ -549,7 +549,7 @@ design: (work@dut) |vpiParamAssign: \_param_assign: , line:7:15, endln:7:27 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/ConstantRange/dut.sv, line:6:1, endln:21:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/ConstantRange/dut.sv, line:6:1, endln:21:10 |vpiRhs: \_constant: , line:7:26, endln:7:27 |vpiDecompile:8 @@ -563,7 +563,7 @@ design: (work@dut) |vpiParamAssign: \_param_assign: , line:8:34, endln:8:60 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/ConstantRange/dut.sv, line:6:1, endln:21:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/ConstantRange/dut.sv, line:6:1, endln:21:10 |vpiRhs: \_constant: , line:8:49, endln:8:60 |vpiDecompile:8'b11110000 @@ -585,7 +585,7 @@ design: (work@dut) |vpiParamAssign: \_param_assign: , line:9:34, endln:9:61 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/ConstantRange/dut.sv, line:6:1, endln:21:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/ConstantRange/dut.sv, line:6:1, endln:21:10 |vpiRhs: \_constant: , line:9:50, endln:9:61 |vpiDecompile:8'b11110000 @@ -610,7 +610,7 @@ design: (work@dut) |vpiGenScopeArray: \_gen_scope_array: (work@dut.gen_mio_pads[0]), line:11:39, endln:15:4 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/ConstantRange/dut.sv, line:6:1, endln:21:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/ConstantRange/dut.sv, line:6:1, endln:21:10 |vpiName:gen_mio_pads[0] |vpiFullName:work@dut.gen_mio_pads[0] |vpiGenScope: @@ -631,7 +631,7 @@ design: (work@dut) |vpiGenScopeArray: \_gen_scope_array: (work@dut.gen_mio_pads[1]), line:11:39, endln:15:4 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/ConstantRange/dut.sv, line:6:1, endln:21:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/ConstantRange/dut.sv, line:6:1, endln:21:10 |vpiName:gen_mio_pads[1] |vpiFullName:work@dut.gen_mio_pads[1] |vpiGenScope: @@ -652,7 +652,7 @@ design: (work@dut) |vpiGenScopeArray: \_gen_scope_array: (work@dut.gen_mio_pads[2]), line:11:39, endln:15:4 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/ConstantRange/dut.sv, line:6:1, endln:21:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/ConstantRange/dut.sv, line:6:1, endln:21:10 |vpiName:gen_mio_pads[2] |vpiFullName:work@dut.gen_mio_pads[2] |vpiGenScope: @@ -673,7 +673,7 @@ design: (work@dut) |vpiGenScopeArray: \_gen_scope_array: (work@dut.gen_mio_pads[3]), line:11:39, endln:15:4 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/ConstantRange/dut.sv, line:6:1, endln:21:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/ConstantRange/dut.sv, line:6:1, endln:21:10 |vpiName:gen_mio_pads[3] |vpiFullName:work@dut.gen_mio_pads[3] |vpiGenScope: @@ -694,7 +694,7 @@ design: (work@dut) |vpiGenScopeArray: \_gen_scope_array: (work@dut.gen_mio_pads[4]), line:11:39, endln:15:4 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/ConstantRange/dut.sv, line:6:1, endln:21:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/ConstantRange/dut.sv, line:6:1, endln:21:10 |vpiName:gen_mio_pads[4] |vpiFullName:work@dut.gen_mio_pads[4] |vpiGenScope: @@ -723,8 +723,8 @@ design: (work@dut) |vpiParent: \_gen_scope_array: (work@dut.gen_mio_pads[4].gen_mio_inout), line:12:6, endln:14:9 |vpiFullName:work@dut.gen_mio_pads[4].gen_mio_inout - |vpiModule: - \_module: work@GOOD (work@dut.gen_mio_pads[4].gen_mio_inout.good), file:${SURELOG_DIR}/tests/ConstantRange/dut.sv, line:13:14, endln:13:26 + |vpiModuleInst: + \_module_inst: work@GOOD (work@dut.gen_mio_pads[4].gen_mio_inout.good), file:${SURELOG_DIR}/tests/ConstantRange/dut.sv, line:13:14, endln:13:26 |vpiParent: \_gen_scope: (work@dut.gen_mio_pads[4].gen_mio_inout) |vpiName:good @@ -735,7 +735,7 @@ design: (work@dut) |vpiGenScopeArray: \_gen_scope_array: (work@dut.gen_mio_pads[5]), line:11:39, endln:15:4 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/ConstantRange/dut.sv, line:6:1, endln:21:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/ConstantRange/dut.sv, line:6:1, endln:21:10 |vpiName:gen_mio_pads[5] |vpiFullName:work@dut.gen_mio_pads[5] |vpiGenScope: @@ -764,8 +764,8 @@ design: (work@dut) |vpiParent: \_gen_scope_array: (work@dut.gen_mio_pads[5].gen_mio_inout), line:12:6, endln:14:9 |vpiFullName:work@dut.gen_mio_pads[5].gen_mio_inout - |vpiModule: - \_module: work@GOOD (work@dut.gen_mio_pads[5].gen_mio_inout.good), file:${SURELOG_DIR}/tests/ConstantRange/dut.sv, line:13:14, endln:13:26 + |vpiModuleInst: + \_module_inst: work@GOOD (work@dut.gen_mio_pads[5].gen_mio_inout.good), file:${SURELOG_DIR}/tests/ConstantRange/dut.sv, line:13:14, endln:13:26 |vpiParent: \_gen_scope: (work@dut.gen_mio_pads[5].gen_mio_inout) |vpiName:good @@ -776,7 +776,7 @@ design: (work@dut) |vpiGenScopeArray: \_gen_scope_array: (work@dut.gen_mio_pads[6]), line:11:39, endln:15:4 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/ConstantRange/dut.sv, line:6:1, endln:21:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/ConstantRange/dut.sv, line:6:1, endln:21:10 |vpiName:gen_mio_pads[6] |vpiFullName:work@dut.gen_mio_pads[6] |vpiGenScope: @@ -805,8 +805,8 @@ design: (work@dut) |vpiParent: \_gen_scope_array: (work@dut.gen_mio_pads[6].gen_mio_inout), line:12:6, endln:14:9 |vpiFullName:work@dut.gen_mio_pads[6].gen_mio_inout - |vpiModule: - \_module: work@GOOD (work@dut.gen_mio_pads[6].gen_mio_inout.good), file:${SURELOG_DIR}/tests/ConstantRange/dut.sv, line:13:14, endln:13:26 + |vpiModuleInst: + \_module_inst: work@GOOD (work@dut.gen_mio_pads[6].gen_mio_inout.good), file:${SURELOG_DIR}/tests/ConstantRange/dut.sv, line:13:14, endln:13:26 |vpiParent: \_gen_scope: (work@dut.gen_mio_pads[6].gen_mio_inout) |vpiName:good @@ -817,7 +817,7 @@ design: (work@dut) |vpiGenScopeArray: \_gen_scope_array: (work@dut.gen_mio_pads[7]), line:11:39, endln:15:4 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/ConstantRange/dut.sv, line:6:1, endln:21:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/ConstantRange/dut.sv, line:6:1, endln:21:10 |vpiName:gen_mio_pads[7] |vpiFullName:work@dut.gen_mio_pads[7] |vpiGenScope: @@ -846,8 +846,8 @@ design: (work@dut) |vpiParent: \_gen_scope_array: (work@dut.gen_mio_pads[7].gen_mio_inout), line:12:6, endln:14:9 |vpiFullName:work@dut.gen_mio_pads[7].gen_mio_inout - |vpiModule: - \_module: work@GOOD (work@dut.gen_mio_pads[7].gen_mio_inout.good), file:${SURELOG_DIR}/tests/ConstantRange/dut.sv, line:13:14, endln:13:26 + |vpiModuleInst: + \_module_inst: work@GOOD (work@dut.gen_mio_pads[7].gen_mio_inout.good), file:${SURELOG_DIR}/tests/ConstantRange/dut.sv, line:13:14, endln:13:26 |vpiParent: \_gen_scope: (work@dut.gen_mio_pads[7].gen_mio_inout) |vpiName:good diff --git a/tests/ContAssign/ContAssign.log b/tests/ContAssign/ContAssign.log index 491fbd551f..d1093973c2 100644 --- a/tests/ContAssign/ContAssign.log +++ b/tests/ContAssign/ContAssign.log @@ -392,7 +392,7 @@ io_decl 11 logic_net 13 logic_typespec 4 logic_var 1 -module 4 +module_inst 4 operation 3 package 2 range 1 @@ -420,7 +420,7 @@ io_decl 22 logic_net 13 logic_typespec 4 logic_var 1 -module 4 +module_inst 4 operation 4 package 2 range 1 @@ -916,7 +916,7 @@ design: (work@top) \_int_typespec: |vpiSigned:1 |uhdmallModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/ContAssign/dut.sv, line:1:1, endln:14:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ContAssign/dut.sv, line:1:1, endln:14:10 |vpiParent: \_design: (work@top) |vpiFullName:work@top @@ -924,35 +924,35 @@ design: (work@top) |vpiNet: \_logic_net: (work@top.intf2), line:3:13, endln:3:18 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ContAssign/dut.sv, line:1:1, endln:14:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ContAssign/dut.sv, line:1:1, endln:14:10 |vpiName:intf2 |vpiFullName:work@top.intf2 |vpiNetType:1 |vpiNet: \_logic_net: (work@top.ena), line:5:8, endln:5:11 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ContAssign/dut.sv, line:1:1, endln:14:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ContAssign/dut.sv, line:1:1, endln:14:10 |vpiName:ena |vpiFullName:work@top.ena |vpiNetType:1 |vpiNet: \_logic_net: (work@top.__debug_req_ready), line:7:13, endln:7:30 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ContAssign/dut.sv, line:1:1, endln:14:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ContAssign/dut.sv, line:1:1, endln:14:10 |vpiName:__debug_req_ready |vpiFullName:work@top.__debug_req_ready |vpiNetType:1 |vpiNet: \_logic_net: (work@top.toto), line:9:8, endln:9:12 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ContAssign/dut.sv, line:1:1, endln:14:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ContAssign/dut.sv, line:1:1, endln:14:10 |vpiName:toto |vpiFullName:work@top.toto |vpiNetType:1 |vpiContAssign: \_cont_assign: , line:11:10, endln:11:15 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ContAssign/dut.sv, line:1:1, endln:14:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ContAssign/dut.sv, line:1:1, endln:14:10 |vpiRhs: \_ref_obj: (work@top.b), line:11:14, endln:11:15 |vpiParent: @@ -970,14 +970,14 @@ design: (work@top) |vpiActual: \_logic_net: (a) |uhdmtopModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/ContAssign/dut.sv, line:1:1, endln:14:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ContAssign/dut.sv, line:1:1, endln:14:10 |vpiName:work@top |vpiDefName:work@top |vpiTop:1 |vpiNet: \_logic_net: (work@top.ena), line:5:8, endln:5:11 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ContAssign/dut.sv, line:1:1, endln:14:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ContAssign/dut.sv, line:1:1, endln:14:10 |vpiTypespec: \_logic_typespec: , line:5:3, endln:5:7 |vpiName:ena @@ -986,7 +986,7 @@ design: (work@top) |vpiNet: \_logic_net: (work@top.__debug_req_ready), line:7:13, endln:7:30 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ContAssign/dut.sv, line:1:1, endln:14:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ContAssign/dut.sv, line:1:1, endln:14:10 |vpiTypespec: \_logic_typespec: , line:7:3, endln:7:7 |vpiName:__debug_req_ready @@ -995,7 +995,7 @@ design: (work@top) |vpiNet: \_logic_net: (work@top.toto), line:9:8, endln:9:12 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ContAssign/dut.sv, line:1:1, endln:14:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ContAssign/dut.sv, line:1:1, endln:14:10 |vpiTypespec: \_logic_typespec: , line:9:3, endln:9:7 |vpiName:toto @@ -1020,7 +1020,7 @@ design: (work@top) |vpiArrayNet: \_array_net: (work@top.intf2), line:3:13, endln:3:18 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ContAssign/dut.sv, line:1:1, endln:14:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ContAssign/dut.sv, line:1:1, endln:14:10 |vpiSize:2 |vpiName:intf2 |vpiFullName:work@top.intf2 @@ -1063,7 +1063,7 @@ design: (work@top) |vpiContAssign: \_cont_assign: , line:5:8, endln:5:11 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ContAssign/dut.sv, line:1:1, endln:14:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ContAssign/dut.sv, line:1:1, endln:14:10 |vpiNetDeclAssign:1 |vpiRhs: \_operation: , line:5:14, endln:5:22 @@ -1083,7 +1083,7 @@ design: (work@top) |vpiContAssign: \_cont_assign: , line:7:13, endln:7:30 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ContAssign/dut.sv, line:1:1, endln:14:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ContAssign/dut.sv, line:1:1, endln:14:10 |vpiNetDeclAssign:1 |vpiDelay: \_constant: , line:7:8, endln:7:12 @@ -1104,7 +1104,7 @@ design: (work@top) |vpiContAssign: \_cont_assign: , line:11:10, endln:11:15 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ContAssign/dut.sv, line:1:1, endln:14:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ContAssign/dut.sv, line:1:1, endln:14:10 |vpiRhs: \_ref_obj: (work@top.b), line:11:14, endln:11:15 |vpiParent: diff --git a/tests/Context/Context.log b/tests/Context/Context.log index 1ba22ca682..4cf804cb5f 100644 --- a/tests/Context/Context.log +++ b/tests/Context/Context.log @@ -64,7 +64,7 @@ int_typespec 4 int_var 1 io_decl 1 logic_net 1 -module 2 +module_inst 2 port 2 ref_obj 2 task 1 @@ -77,7 +77,7 @@ int_typespec 4 int_var 1 io_decl 2 logic_net 1 -module 2 +module_inst 2 port 3 ref_obj 3 task 2 @@ -95,7 +95,7 @@ design: (work@top) |vpiElaborated:1 |vpiName:work@top |uhdmallModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/Context/dut.sv, line:1:1, endln:3:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/Context/dut.sv, line:1:1, endln:3:10 |vpiParent: \_design: (work@top) |vpiFullName:work@top @@ -103,7 +103,7 @@ design: (work@top) |vpiTaskFunc: \_task: (work@top.get_2), line:2:4, endln:2:52 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/Context/dut.sv, line:1:1, endln:3:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/Context/dut.sv, line:1:1, endln:3:10 |vpiName:get_2 |vpiFullName:work@top.get_2 |vpiAccessType:4 @@ -111,7 +111,7 @@ design: (work@top) |vpiDPIContext:1 |vpiDPICStr:2 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/Context/dut.sv, line:1:1, endln:3:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/Context/dut.sv, line:1:1, endln:3:10 |vpiIODecl: \_io_decl: (x), line:2:49, endln:2:50 |vpiDirection:2 @@ -120,17 +120,17 @@ design: (work@top) \_int_typespec: , line:2:45, endln:2:48 |vpiSigned:1 |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/Context/dut.sv, line:1:1, endln:3:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/Context/dut.sv, line:1:1, endln:3:10 |vpiNet: \_logic_net: (work@top.a), line:1:23, endln:1:24 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/Context/dut.sv, line:1:1, endln:3:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/Context/dut.sv, line:1:1, endln:3:10 |vpiName:a |vpiFullName:work@top.a |vpiPort: \_port: (a), line:1:23, endln:1:24 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/Context/dut.sv, line:1:1, endln:3:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/Context/dut.sv, line:1:1, endln:3:10 |vpiName:a |vpiDirection:2 |vpiLowConn: @@ -141,12 +141,12 @@ design: (work@top) \_int_typespec: , line:1:19, endln:1:22 |vpiSigned:1 |uhdmtopModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/Context/dut.sv, line:1:1, endln:3:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/Context/dut.sv, line:1:1, endln:3:10 |vpiName:work@top |vpiVariables: \_int_var: (work@top.a), line:1:23, endln:1:24 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/Context/dut.sv, line:1:1, endln:3:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/Context/dut.sv, line:1:1, endln:3:10 |vpiTypespec: \_int_typespec: , line:1:19, endln:1:22 |vpiSigned:1 @@ -159,7 +159,7 @@ design: (work@top) |vpiTaskFunc: \_task: (work@top.get_2), line:2:4, endln:2:52 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/Context/dut.sv, line:1:1, endln:3:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/Context/dut.sv, line:1:1, endln:3:10 |vpiName:get_2 |vpiFullName:work@top.get_2 |vpiAccessType:4 @@ -167,7 +167,7 @@ design: (work@top) |vpiDPIContext:1 |vpiDPICStr:2 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/Context/dut.sv, line:1:1, endln:3:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/Context/dut.sv, line:1:1, endln:3:10 |vpiIODecl: \_io_decl: (x), line:2:49, endln:2:50 |vpiParent: @@ -177,12 +177,12 @@ design: (work@top) |vpiTypedef: \_int_typespec: , line:2:45, endln:2:48 |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/Context/dut.sv, line:1:1, endln:3:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/Context/dut.sv, line:1:1, endln:3:10 |vpiTopModule:1 |vpiPort: \_port: (a), line:1:23, endln:1:24 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/Context/dut.sv, line:1:1, endln:3:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/Context/dut.sv, line:1:1, endln:3:10 |vpiName:a |vpiDirection:2 |vpiLowConn: @@ -197,7 +197,7 @@ design: (work@top) \_int_typespec: , line:1:19, endln:1:22 |vpiSigned:1 |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/Context/dut.sv, line:1:1, endln:3:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/Context/dut.sv, line:1:1, endln:3:10 =================== [ FATAL] : 0 [ SYNTAX] : 0 diff --git a/tests/CovMacro/CovMacro.log b/tests/CovMacro/CovMacro.log index 7a0cc669f3..2522ae3d02 100644 --- a/tests/CovMacro/CovMacro.log +++ b/tests/CovMacro/CovMacro.log @@ -726,7 +726,7 @@ int_var 5 io_decl 11 logic_net 2 logic_var 1 -module 5 +module_inst 5 package 2 real_typespec 1 real_var 1 @@ -755,7 +755,7 @@ int_var 5 io_decl 22 logic_net 2 logic_var 1 -module 5 +module_inst 5 package 2 real_typespec 1 real_var 1 @@ -1251,13 +1251,13 @@ design: (work@top) \_int_typespec: |vpiSigned:1 |uhdmallModules: -\_module: work@DUT (work@DUT), file:${SURELOG_DIR}/tests/CovMacro/dut.sv, line:2:1, endln:3:10 +\_module_inst: work@DUT (work@DUT), file:${SURELOG_DIR}/tests/CovMacro/dut.sv, line:2:1, endln:3:10 |vpiParent: \_design: (work@top) |vpiFullName:work@DUT |vpiDefName:work@DUT |uhdmallModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/CovMacro/dut.sv, line:5:1, endln:25:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/CovMacro/dut.sv, line:5:1, endln:25:10 |vpiParent: \_design: (work@top) |vpiFullName:work@top @@ -1265,19 +1265,19 @@ design: (work@top) |vpiNet: \_logic_net: (work@top.i), line:6:18, endln:6:19 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/CovMacro/dut.sv, line:5:1, endln:25:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/CovMacro/dut.sv, line:5:1, endln:25:10 |vpiName:i |vpiFullName:work@top.i |vpiNet: \_logic_net: (work@top.r), line:7:10, endln:7:11 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/CovMacro/dut.sv, line:5:1, endln:25:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/CovMacro/dut.sv, line:5:1, endln:25:10 |vpiName:r |vpiFullName:work@top.r |vpiProcess: \_initial: , line:11:5, endln:24:8 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/CovMacro/dut.sv, line:5:1, endln:25:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/CovMacro/dut.sv, line:5:1, endln:25:10 |vpiStmt: \_begin: (work@top), line:11:13, endln:24:8 |vpiParent: @@ -1765,12 +1765,12 @@ design: (work@top) |vpiActual: \_real_var: (work@top.r), line:7:10, endln:7:11 |uhdmtopModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/CovMacro/dut.sv, line:5:1, endln:25:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/CovMacro/dut.sv, line:5:1, endln:25:10 |vpiName:work@top |vpiVariables: \_int_var: (work@top.i), line:6:18, endln:6:19 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/CovMacro/dut.sv, line:5:1, endln:25:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/CovMacro/dut.sv, line:5:1, endln:25:10 |vpiTypespec: \_int_typespec: , line:6:5, endln:6:17 |vpiName:i @@ -1779,7 +1779,7 @@ design: (work@top) |vpiVariables: \_real_var: (work@top.r), line:7:10, endln:7:11 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/CovMacro/dut.sv, line:5:1, endln:25:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/CovMacro/dut.sv, line:5:1, endln:25:10 |vpiTypespec: \_real_typespec: , line:7:5, endln:7:9 |vpiName:r @@ -1791,7 +1791,7 @@ design: (work@top) |vpiProcess: \_initial: , line:11:5, endln:24:8 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/CovMacro/dut.sv, line:5:1, endln:25:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/CovMacro/dut.sv, line:5:1, endln:25:10 |vpiStmt: \_begin: (work@top), line:11:13, endln:24:8 |vpiParent: @@ -1830,7 +1830,7 @@ design: (work@top) \_hier_path: (work@top.$root.top), line:12:42, endln:12:51 |vpiName:top |vpiActual: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/CovMacro/dut.sv, line:5:1, endln:25:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/CovMacro/dut.sv, line:5:1, endln:25:10 |vpiName:$coverage_control |vpiLhs: \_ref_obj: (work@top.i), line:12:9, endln:12:10 @@ -1900,14 +1900,14 @@ design: (work@top) \_hier_path: (work@top.$root.top.unit1), line:14:42, endln:14:57 |vpiName:top |vpiActual: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/CovMacro/dut.sv, line:5:1, endln:25:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/CovMacro/dut.sv, line:5:1, endln:25:10 |vpiActual: \_ref_obj: (unit1) |vpiParent: \_hier_path: (work@top.$root.top.unit1), line:14:42, endln:14:57 |vpiName:unit1 |vpiActual: - \_module: work@DUT (work@top.unit1), file:${SURELOG_DIR}/tests/CovMacro/dut.sv, line:8:5, endln:8:17 + \_module_inst: work@DUT (work@top.unit1), file:${SURELOG_DIR}/tests/CovMacro/dut.sv, line:8:5, endln:8:17 |vpiName:$coverage_control |vpiLhs: \_ref_obj: (work@top.i), line:14:9, endln:14:10 @@ -1950,14 +1950,14 @@ design: (work@top) \_hier_path: (work@top.$root.top.unit2), line:15:43, endln:15:58 |vpiName:top |vpiActual: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/CovMacro/dut.sv, line:5:1, endln:25:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/CovMacro/dut.sv, line:5:1, endln:25:10 |vpiActual: \_ref_obj: (unit2) |vpiParent: \_hier_path: (work@top.$root.top.unit2), line:15:43, endln:15:58 |vpiName:unit2 |vpiActual: - \_module: work@DUT (work@top.unit2), file:${SURELOG_DIR}/tests/CovMacro/dut.sv, line:9:5, endln:9:17 + \_module_inst: work@DUT (work@top.unit2), file:${SURELOG_DIR}/tests/CovMacro/dut.sv, line:9:5, endln:9:17 |vpiName:$coverage_control |vpiLhs: \_ref_obj: (work@top.i), line:15:9, endln:15:10 @@ -2050,14 +2050,14 @@ design: (work@top) \_hier_path: (work@top.$root.top.unit1), line:18:35, endln:18:50 |vpiName:top |vpiActual: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/CovMacro/dut.sv, line:5:1, endln:25:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/CovMacro/dut.sv, line:5:1, endln:25:10 |vpiActual: \_ref_obj: (unit1) |vpiParent: \_hier_path: (work@top.$root.top.unit1), line:18:35, endln:18:50 |vpiName:unit1 |vpiActual: - \_module: work@DUT (work@top.unit1), file:${SURELOG_DIR}/tests/CovMacro/dut.sv, line:8:5, endln:8:17 + \_module_inst: work@DUT (work@top.unit1), file:${SURELOG_DIR}/tests/CovMacro/dut.sv, line:8:5, endln:8:17 |vpiName:$coverage_get |vpiLhs: \_ref_obj: (work@top.r), line:18:9, endln:18:10 @@ -2146,28 +2146,28 @@ design: (work@top) |vpiFullName:work@top.r |vpiActual: \_real_var: (work@top.r), line:7:10, endln:7:11 - |vpiModule: - \_module: work@DUT (work@top.unit1), file:${SURELOG_DIR}/tests/CovMacro/dut.sv, line:8:5, endln:8:17 + |vpiModuleInst: + \_module_inst: work@DUT (work@top.unit1), file:${SURELOG_DIR}/tests/CovMacro/dut.sv, line:8:5, endln:8:17 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/CovMacro/dut.sv, line:5:1, endln:25:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/CovMacro/dut.sv, line:5:1, endln:25:10 |vpiName:unit1 |vpiFullName:work@top.unit1 |vpiDefName:work@DUT |vpiDefFile:${SURELOG_DIR}/tests/CovMacro/dut.sv |vpiDefLineNo:2 |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/CovMacro/dut.sv, line:5:1, endln:25:10 - |vpiModule: - \_module: work@DUT (work@top.unit2), file:${SURELOG_DIR}/tests/CovMacro/dut.sv, line:9:5, endln:9:17 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/CovMacro/dut.sv, line:5:1, endln:25:10 + |vpiModuleInst: + \_module_inst: work@DUT (work@top.unit2), file:${SURELOG_DIR}/tests/CovMacro/dut.sv, line:9:5, endln:9:17 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/CovMacro/dut.sv, line:5:1, endln:25:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/CovMacro/dut.sv, line:5:1, endln:25:10 |vpiName:unit2 |vpiFullName:work@top.unit2 |vpiDefName:work@DUT |vpiDefFile:${SURELOG_DIR}/tests/CovMacro/dut.sv |vpiDefLineNo:2 |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/CovMacro/dut.sv, line:5:1, endln:25:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/CovMacro/dut.sv, line:5:1, endln:25:10 =================== [ FATAL] : 0 [ SYNTAX] : 0 diff --git a/tests/CrossFunc/CrossFunc.log b/tests/CrossFunc/CrossFunc.log index 458941c053..232e6780e7 100644 --- a/tests/CrossFunc/CrossFunc.log +++ b/tests/CrossFunc/CrossFunc.log @@ -368,7 +368,7 @@ logic_net 3 logic_typespec 3 logic_var 4 method_func_call 3 -module 4 +module_inst 4 operation 8 range 6 ref_obj 12 @@ -391,7 +391,7 @@ logic_net 3 logic_typespec 3 logic_var 5 method_func_call 3 -module 4 +module_inst 4 operation 16 range 6 ref_obj 22 @@ -411,7 +411,7 @@ design: (work@mod_m) |vpiElaborated:1 |vpiName:work@mod_m |uhdmallModules: -\_module: work@mod_m (work@mod_m), file:${SURELOG_DIR}/tests/CrossFunc/dut.sv, line:1:1, endln:32:10 +\_module_inst: work@mod_m (work@mod_m), file:${SURELOG_DIR}/tests/CrossFunc/dut.sv, line:1:1, endln:32:10 |vpiParent: \_design: (work@mod_m) |vpiFullName:work@mod_m @@ -419,7 +419,7 @@ design: (work@mod_m) |vpiTaskFunc: \_function: (work@mod_m.myFunc1), line:9:3, endln:12:14 |vpiParent: - \_module: work@mod_m (work@mod_m), file:${SURELOG_DIR}/tests/CrossFunc/dut.sv, line:1:1, endln:32:10 + \_module_inst: work@mod_m (work@mod_m), file:${SURELOG_DIR}/tests/CrossFunc/dut.sv, line:1:1, endln:32:10 |vpiName:myFunc1 |vpiFullName:work@mod_m.myFunc1 |vpiVisibility:1 @@ -429,7 +429,7 @@ design: (work@mod_m) \_unsupported_typespec: (CrossQueueType), line:9:12, endln:9:26 |vpiName:CrossQueueType |vpiParent: - \_module: work@mod_m (work@mod_m), file:${SURELOG_DIR}/tests/CrossFunc/dut.sv, line:1:1, endln:32:10 + \_module_inst: work@mod_m (work@mod_m), file:${SURELOG_DIR}/tests/CrossFunc/dut.sv, line:1:1, endln:32:10 |vpiIODecl: \_io_decl: (f_lim), line:9:39, endln:9:44 |vpiDirection:1 @@ -527,11 +527,11 @@ design: (work@mod_m) |vpiFunction: \_function: (work@mod_m.myFunc1), line:9:3, endln:12:14 |vpiInstance: - \_module: work@mod_m (work@mod_m), file:${SURELOG_DIR}/tests/CrossFunc/dut.sv, line:1:1, endln:32:10 + \_module_inst: work@mod_m (work@mod_m), file:${SURELOG_DIR}/tests/CrossFunc/dut.sv, line:1:1, endln:32:10 |vpiTaskFunc: \_function: (work@mod_m.myFunc2), line:17:3, endln:20:14 |vpiParent: - \_module: work@mod_m (work@mod_m), file:${SURELOG_DIR}/tests/CrossFunc/dut.sv, line:1:1, endln:32:10 + \_module_inst: work@mod_m (work@mod_m), file:${SURELOG_DIR}/tests/CrossFunc/dut.sv, line:1:1, endln:32:10 |vpiName:myFunc2 |vpiFullName:work@mod_m.myFunc2 |vpiVisibility:1 @@ -541,7 +541,7 @@ design: (work@mod_m) \_unsupported_typespec: (CrossQueueType), line:17:12, endln:17:26 |vpiName:CrossQueueType |vpiParent: - \_module: work@mod_m (work@mod_m), file:${SURELOG_DIR}/tests/CrossFunc/dut.sv, line:1:1, endln:32:10 + \_module_inst: work@mod_m (work@mod_m), file:${SURELOG_DIR}/tests/CrossFunc/dut.sv, line:1:1, endln:32:10 |vpiIODecl: \_io_decl: (f_lim), line:17:48, endln:17:53 |vpiDirection:1 @@ -700,34 +700,34 @@ design: (work@mod_m) |vpiFunction: \_function: (work@mod_m.myFunc2), line:17:3, endln:20:14 |vpiInstance: - \_module: work@mod_m (work@mod_m), file:${SURELOG_DIR}/tests/CrossFunc/dut.sv, line:1:1, endln:32:10 + \_module_inst: work@mod_m (work@mod_m), file:${SURELOG_DIR}/tests/CrossFunc/dut.sv, line:1:1, endln:32:10 |vpiNet: \_logic_net: (work@mod_m.a), line:2:15, endln:2:16 |vpiParent: - \_module: work@mod_m (work@mod_m), file:${SURELOG_DIR}/tests/CrossFunc/dut.sv, line:1:1, endln:32:10 + \_module_inst: work@mod_m (work@mod_m), file:${SURELOG_DIR}/tests/CrossFunc/dut.sv, line:1:1, endln:32:10 |vpiName:a |vpiFullName:work@mod_m.a |vpiNetType:36 |vpiNet: \_logic_net: (work@mod_m.b), line:2:18, endln:2:19 |vpiParent: - \_module: work@mod_m (work@mod_m), file:${SURELOG_DIR}/tests/CrossFunc/dut.sv, line:1:1, endln:32:10 + \_module_inst: work@mod_m (work@mod_m), file:${SURELOG_DIR}/tests/CrossFunc/dut.sv, line:1:1, endln:32:10 |vpiName:b |vpiFullName:work@mod_m.b |vpiNetType:36 |vpiNet: \_logic_net: (work@mod_m.cg_inst), line:24:5, endln:24:12 |vpiParent: - \_module: work@mod_m (work@mod_m), file:${SURELOG_DIR}/tests/CrossFunc/dut.sv, line:1:1, endln:32:10 + \_module_inst: work@mod_m (work@mod_m), file:${SURELOG_DIR}/tests/CrossFunc/dut.sv, line:1:1, endln:32:10 |vpiName:cg_inst |vpiFullName:work@mod_m.cg_inst |uhdmtopModules: -\_module: work@mod_m (work@mod_m), file:${SURELOG_DIR}/tests/CrossFunc/dut.sv, line:1:1, endln:32:10 +\_module_inst: work@mod_m (work@mod_m), file:${SURELOG_DIR}/tests/CrossFunc/dut.sv, line:1:1, endln:32:10 |vpiName:work@mod_m |vpiVariables: \_logic_var: (work@mod_m.a), line:2:15, endln:2:16 |vpiParent: - \_module: work@mod_m (work@mod_m), file:${SURELOG_DIR}/tests/CrossFunc/dut.sv, line:1:1, endln:32:10 + \_module_inst: work@mod_m (work@mod_m), file:${SURELOG_DIR}/tests/CrossFunc/dut.sv, line:1:1, endln:32:10 |vpiTypespec: \_logic_typespec: , line:2:2, endln:2:14 |vpiRange: @@ -772,7 +772,7 @@ design: (work@mod_m) |vpiVariables: \_logic_var: (work@mod_m.b), line:2:18, endln:2:19 |vpiParent: - \_module: work@mod_m (work@mod_m), file:${SURELOG_DIR}/tests/CrossFunc/dut.sv, line:1:1, endln:32:10 + \_module_inst: work@mod_m (work@mod_m), file:${SURELOG_DIR}/tests/CrossFunc/dut.sv, line:1:1, endln:32:10 |vpiTypespec: \_logic_typespec: , line:2:2, endln:2:14 |vpiName:b @@ -799,7 +799,7 @@ design: (work@mod_m) |vpiVariables: \_logic_var: (work@mod_m.cg_inst), line:24:5, endln:24:21 |vpiParent: - \_module: work@mod_m (work@mod_m), file:${SURELOG_DIR}/tests/CrossFunc/dut.sv, line:1:1, endln:32:10 + \_module_inst: work@mod_m (work@mod_m), file:${SURELOG_DIR}/tests/CrossFunc/dut.sv, line:1:1, endln:32:10 |vpiName:cg_inst |vpiFullName:work@mod_m.cg_inst |vpiVisibility:1 @@ -819,14 +819,14 @@ design: (work@mod_m) |vpiTaskFunc: \_function: (work@mod_m.myFunc1), line:9:3, endln:12:14 |vpiParent: - \_module: work@mod_m (work@mod_m), file:${SURELOG_DIR}/tests/CrossFunc/dut.sv, line:1:1, endln:32:10 + \_module_inst: work@mod_m (work@mod_m), file:${SURELOG_DIR}/tests/CrossFunc/dut.sv, line:1:1, endln:32:10 |vpiName:myFunc1 |vpiFullName:work@mod_m.myFunc1 |vpiVisibility:1 |vpiReturn: \_ref_var: , line:9:12, endln:9:26 |vpiParent: - \_module: work@mod_m (work@mod_m), file:${SURELOG_DIR}/tests/CrossFunc/dut.sv, line:1:1, endln:32:10 + \_module_inst: work@mod_m (work@mod_m), file:${SURELOG_DIR}/tests/CrossFunc/dut.sv, line:1:1, endln:32:10 |vpiIODecl: \_io_decl: (f_lim), line:9:39, endln:9:44 |vpiParent: @@ -918,18 +918,18 @@ design: (work@mod_m) |vpiFunction: \_function: (work@mod_m.myFunc1), line:9:3, endln:12:14 |vpiInstance: - \_module: work@mod_m (work@mod_m), file:${SURELOG_DIR}/tests/CrossFunc/dut.sv, line:1:1, endln:32:10 + \_module_inst: work@mod_m (work@mod_m), file:${SURELOG_DIR}/tests/CrossFunc/dut.sv, line:1:1, endln:32:10 |vpiTaskFunc: \_function: (work@mod_m.myFunc2), line:17:3, endln:20:14 |vpiParent: - \_module: work@mod_m (work@mod_m), file:${SURELOG_DIR}/tests/CrossFunc/dut.sv, line:1:1, endln:32:10 + \_module_inst: work@mod_m (work@mod_m), file:${SURELOG_DIR}/tests/CrossFunc/dut.sv, line:1:1, endln:32:10 |vpiName:myFunc2 |vpiFullName:work@mod_m.myFunc2 |vpiVisibility:1 |vpiReturn: \_ref_var: , line:17:12, endln:17:26 |vpiParent: - \_module: work@mod_m (work@mod_m), file:${SURELOG_DIR}/tests/CrossFunc/dut.sv, line:1:1, endln:32:10 + \_module_inst: work@mod_m (work@mod_m), file:${SURELOG_DIR}/tests/CrossFunc/dut.sv, line:1:1, endln:32:10 |vpiIODecl: \_io_decl: (f_lim), line:17:48, endln:17:53 |vpiParent: @@ -1034,7 +1034,7 @@ design: (work@mod_m) |vpiFunction: \_function: (work@mod_m.myFunc2), line:17:3, endln:20:14 |vpiInstance: - \_module: work@mod_m (work@mod_m), file:${SURELOG_DIR}/tests/CrossFunc/dut.sv, line:1:1, endln:32:10 + \_module_inst: work@mod_m (work@mod_m), file:${SURELOG_DIR}/tests/CrossFunc/dut.sv, line:1:1, endln:32:10 |vpiTopModule:1 =================== [ FATAL] : 0 diff --git a/tests/CrossItem/CrossItem.log b/tests/CrossItem/CrossItem.log index d0b01dd814..576e092d69 100644 --- a/tests/CrossItem/CrossItem.log +++ b/tests/CrossItem/CrossItem.log @@ -258,7 +258,7 @@ bit_var 2 constant 6 design 1 logic_net 2 -module 3 +module_inst 3 range 3 === UHDM Object Stats End === [INF:UH0707] Elaborating UHDM... @@ -269,7 +269,7 @@ bit_var 2 constant 6 design 1 logic_net 2 -module 3 +module_inst 3 range 3 === UHDM Object Stats End === [INF:UH0708] Writing UHDM DB: ${SURELOG_DIR}/build/regression/CrossItem/slpp_all/surelog.uhdm ... @@ -285,7 +285,7 @@ design: (work@top) |vpiElaborated:1 |vpiName:work@top |uhdmallModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/CrossItem/dut.sv, line:1:1, endln:25:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/CrossItem/dut.sv, line:1:1, endln:25:10 |vpiParent: \_design: (work@top) |vpiFullName:work@top @@ -293,22 +293,22 @@ design: (work@top) |vpiNet: \_logic_net: (work@top.v_a), line:2:12, endln:2:15 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/CrossItem/dut.sv, line:1:1, endln:25:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/CrossItem/dut.sv, line:1:1, endln:25:10 |vpiName:v_a |vpiFullName:work@top.v_a |vpiNet: \_logic_net: (work@top.v_b), line:2:17, endln:2:20 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/CrossItem/dut.sv, line:1:1, endln:25:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/CrossItem/dut.sv, line:1:1, endln:25:10 |vpiName:v_b |vpiFullName:work@top.v_b |uhdmtopModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/CrossItem/dut.sv, line:1:1, endln:25:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/CrossItem/dut.sv, line:1:1, endln:25:10 |vpiName:work@top |vpiVariables: \_bit_var: (work@top.v_a), line:2:12, endln:2:15 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/CrossItem/dut.sv, line:1:1, endln:25:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/CrossItem/dut.sv, line:1:1, endln:25:10 |vpiTypespec: \_bit_typespec: , line:2:2, endln:2:11 |vpiRange: @@ -336,7 +336,7 @@ design: (work@top) |vpiVariables: \_bit_var: (work@top.v_b), line:2:17, endln:2:20 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/CrossItem/dut.sv, line:1:1, endln:25:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/CrossItem/dut.sv, line:1:1, endln:25:10 |vpiTypespec: \_bit_typespec: , line:2:2, endln:2:11 |vpiName:v_b diff --git a/tests/DataAttrib/DataAttrib.log b/tests/DataAttrib/DataAttrib.log index 3f189dfce7..d8128a39d9 100644 --- a/tests/DataAttrib/DataAttrib.log +++ b/tests/DataAttrib/DataAttrib.log @@ -70,7 +70,7 @@ attribute 1 design 1 logic_net 6 logic_typespec 2 -module 2 +module_inst 2 === UHDM Object Stats End === [INF:UH0707] Elaborating UHDM... @@ -79,7 +79,7 @@ attribute 1 design 1 logic_net 6 logic_typespec 2 -module 2 +module_inst 2 === UHDM Object Stats End === [INF:UH0708] Writing UHDM DB: ${SURELOG_DIR}/build/regression/DataAttrib/slpp_all/surelog.uhdm ... @@ -94,7 +94,7 @@ design: (work@top) |vpiElaborated:1 |vpiName:work@top |uhdmallModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/DataAttrib/dut.sv, line:1:1, endln:7:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/DataAttrib/dut.sv, line:1:1, endln:7:10 |vpiParent: \_design: (work@top) |vpiFullName:work@top @@ -102,33 +102,33 @@ design: (work@top) |vpiNet: \_logic_net: (work@top.my_reg1), line:3:20, endln:3:27 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/DataAttrib/dut.sv, line:1:1, endln:7:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/DataAttrib/dut.sv, line:1:1, endln:7:10 |vpiName:my_reg1 |vpiFullName:work@top.my_reg1 |vpiNetType:48 |vpiNet: \_logic_net: (work@top.my_reg2), line:3:29, endln:3:36 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/DataAttrib/dut.sv, line:1:1, endln:7:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/DataAttrib/dut.sv, line:1:1, endln:7:10 |vpiName:my_reg2 |vpiFullName:work@top.my_reg2 |vpiNetType:48 |vpiNet: \_logic_net: (work@top.no_attrib), line:5:5, endln:5:14 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/DataAttrib/dut.sv, line:1:1, endln:7:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/DataAttrib/dut.sv, line:1:1, endln:7:10 |vpiName:no_attrib |vpiFullName:work@top.no_attrib |vpiNetType:48 |uhdmtopModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/DataAttrib/dut.sv, line:1:1, endln:7:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/DataAttrib/dut.sv, line:1:1, endln:7:10 |vpiName:work@top |vpiDefName:work@top |vpiTop:1 |vpiNet: \_logic_net: (work@top.my_reg1), line:3:20, endln:3:27 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/DataAttrib/dut.sv, line:1:1, endln:7:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/DataAttrib/dut.sv, line:1:1, endln:7:10 |vpiTypespec: \_logic_typespec: , line:3:16, endln:3:19 |vpiName:my_reg1 @@ -140,7 +140,7 @@ design: (work@top) |vpiNet: \_logic_net: (work@top.my_reg2), line:3:29, endln:3:36 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/DataAttrib/dut.sv, line:1:1, endln:7:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/DataAttrib/dut.sv, line:1:1, endln:7:10 |vpiTypespec: \_logic_typespec: , line:3:16, endln:3:19 |vpiName:my_reg2 @@ -151,7 +151,7 @@ design: (work@top) |vpiNet: \_logic_net: (work@top.no_attrib), line:5:5, endln:5:14 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/DataAttrib/dut.sv, line:1:1, endln:7:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/DataAttrib/dut.sv, line:1:1, endln:7:10 |vpiTypespec: \_logic_typespec: , line:5:1, endln:5:4 |vpiName:no_attrib diff --git a/tests/DecValue/DecValue.log b/tests/DecValue/DecValue.log index f9d825f0ec..b49c1e68f7 100644 --- a/tests/DecValue/DecValue.log +++ b/tests/DecValue/DecValue.log @@ -125,7 +125,7 @@ design 1 int_typespec 9 int_var 1 logic_net 1 -module 4 +module_inst 4 operation 4 param_assign 6 parameter 6 @@ -141,7 +141,7 @@ design 1 int_typespec 9 int_var 1 logic_net 1 -module 4 +module_inst 4 operation 5 param_assign 6 parameter 6 @@ -161,28 +161,28 @@ design: (work@top) |vpiElaborated:1 |vpiName:work@top |uhdmallModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/DecValue/dut.sv, line:1:1, endln:7:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/DecValue/dut.sv, line:1:1, endln:7:10 |vpiParent: \_design: (work@top) |vpiFullName:work@top |vpiParameter: \_parameter: (work@top.A), line:2:14, endln:2:15 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/DecValue/dut.sv, line:1:1, endln:7:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/DecValue/dut.sv, line:1:1, endln:7:10 |BIN:X |vpiName:A |vpiFullName:work@top.A |vpiParameter: \_parameter: (work@top.B), line:3:14, endln:3:15 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/DecValue/dut.sv, line:1:1, endln:7:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/DecValue/dut.sv, line:1:1, endln:7:10 |BIN:X |vpiName:B |vpiFullName:work@top.B |vpiParameter: \_parameter: (work@top.C), line:4:19, endln:4:20 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/DecValue/dut.sv, line:1:1, endln:7:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/DecValue/dut.sv, line:1:1, endln:7:10 |vpiTypespec: \_int_typespec: , line:4:15, endln:4:18 |vpiParent: @@ -195,7 +195,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:2:14, endln:2:20 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/DecValue/dut.sv, line:1:1, endln:7:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/DecValue/dut.sv, line:1:1, endln:7:10 |vpiRhs: \_constant: , line:2:18, endln:2:20 |vpiDecompile:'X @@ -207,7 +207,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:3:14, endln:3:20 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/DecValue/dut.sv, line:1:1, endln:7:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/DecValue/dut.sv, line:1:1, endln:7:10 |vpiRhs: \_constant: , line:3:18, endln:3:20 |vpiDecompile:'X @@ -219,7 +219,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:4:19, endln:4:28 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/DecValue/dut.sv, line:1:1, endln:7:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/DecValue/dut.sv, line:1:1, endln:7:10 |vpiRhs: \_operation: , line:4:23, endln:4:28 |vpiOpType:12 @@ -239,13 +239,13 @@ design: (work@top) |vpiNet: \_logic_net: (work@top.o), line:1:23, endln:1:24 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/DecValue/dut.sv, line:1:1, endln:7:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/DecValue/dut.sv, line:1:1, endln:7:10 |vpiName:o |vpiFullName:work@top.o |vpiPort: \_port: (o), line:1:23, endln:1:24 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/DecValue/dut.sv, line:1:1, endln:7:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/DecValue/dut.sv, line:1:1, endln:7:10 |vpiName:o |vpiDirection:2 |vpiLowConn: @@ -258,7 +258,7 @@ design: (work@top) |vpiContAssign: \_cont_assign: , line:6:11, endln:6:22 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/DecValue/dut.sv, line:1:1, endln:7:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/DecValue/dut.sv, line:1:1, endln:7:10 |vpiRhs: \_operation: , line:6:15, endln:6:22 |vpiParent: @@ -282,12 +282,12 @@ design: (work@top) |vpiActual: \_int_var: (work@top.o), line:1:23, endln:1:24 |uhdmtopModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/DecValue/dut.sv, line:1:1, endln:7:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/DecValue/dut.sv, line:1:1, endln:7:10 |vpiName:work@top |vpiVariables: \_int_var: (work@top.o), line:1:23, endln:1:24 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/DecValue/dut.sv, line:1:1, endln:7:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/DecValue/dut.sv, line:1:1, endln:7:10 |vpiTypespec: \_int_typespec: , line:1:19, endln:1:22 |vpiSigned:1 @@ -298,21 +298,21 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.A), line:2:14, endln:2:15 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/DecValue/dut.sv, line:1:1, endln:7:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/DecValue/dut.sv, line:1:1, endln:7:10 |BIN:X |vpiName:A |vpiFullName:work@top.A |vpiParameter: \_parameter: (work@top.B), line:3:14, endln:3:15 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/DecValue/dut.sv, line:1:1, endln:7:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/DecValue/dut.sv, line:1:1, endln:7:10 |BIN:X |vpiName:B |vpiFullName:work@top.B |vpiParameter: \_parameter: (work@top.C), line:4:19, endln:4:20 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/DecValue/dut.sv, line:1:1, endln:7:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/DecValue/dut.sv, line:1:1, endln:7:10 |vpiTypespec: \_int_typespec: , line:4:15, endln:4:18 |vpiParent: @@ -325,7 +325,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:2:14, endln:2:20 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/DecValue/dut.sv, line:1:1, endln:7:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/DecValue/dut.sv, line:1:1, endln:7:10 |vpiRhs: \_constant: , line:2:18, endln:2:20 |vpiDecompile:7200 @@ -336,7 +336,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:3:14, endln:3:20 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/DecValue/dut.sv, line:1:1, endln:7:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/DecValue/dut.sv, line:1:1, endln:7:10 |vpiRhs: \_constant: , line:3:18, endln:3:20 |vpiDecompile:1800 @@ -347,7 +347,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:4:19, endln:4:28 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/DecValue/dut.sv, line:1:1, endln:7:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/DecValue/dut.sv, line:1:1, endln:7:10 |vpiRhs: \_constant: , line:4:23, endln:4:28 |vpiDecompile:4 @@ -364,7 +364,7 @@ design: (work@top) |vpiPort: \_port: (o), line:1:23, endln:1:24 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/DecValue/dut.sv, line:1:1, endln:7:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/DecValue/dut.sv, line:1:1, endln:7:10 |vpiName:o |vpiDirection:2 |vpiLowConn: @@ -379,11 +379,11 @@ design: (work@top) \_int_typespec: , line:1:19, endln:1:22 |vpiSigned:1 |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/DecValue/dut.sv, line:1:1, endln:7:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/DecValue/dut.sv, line:1:1, endln:7:10 |vpiContAssign: \_cont_assign: , line:6:11, endln:6:22 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/DecValue/dut.sv, line:1:1, endln:7:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/DecValue/dut.sv, line:1:1, endln:7:10 |vpiRhs: \_operation: , line:6:15, endln:6:22 |vpiParent: diff --git a/tests/DefParamIndex/DefParamIndex.log b/tests/DefParamIndex/DefParamIndex.log index 87b90857bb..142af4d3fd 100644 --- a/tests/DefParamIndex/DefParamIndex.log +++ b/tests/DefParamIndex/DefParamIndex.log @@ -314,7 +314,7 @@ design 1 gen_scope 10 gen_scope_array 10 int_typespec 5 -module 14 +module_inst 14 operation 9 param_assign 3 parameter 5 @@ -328,7 +328,7 @@ design 1 gen_scope 31 gen_scope_array 31 int_typespec 5 -module 35 +module_inst 35 operation 9 param_assign 9 parameter 5 @@ -347,26 +347,26 @@ design: (work@hierdefparam_top) |vpiElaborated:1 |vpiName:work@hierdefparam_top |uhdmallModules: -\_module: work@GOOD (work@GOOD), file:${SURELOG_DIR}/tests/DefParamIndex/dut.sv, line:1:1, endln:2:10 +\_module_inst: work@GOOD (work@GOOD), file:${SURELOG_DIR}/tests/DefParamIndex/dut.sv, line:1:1, endln:2:10 |vpiParent: \_design: (work@hierdefparam_top) |vpiFullName:work@GOOD |vpiDefName:work@GOOD |uhdmallModules: -\_module: work@hierdefparam_a (work@hierdefparam_a), file:${SURELOG_DIR}/tests/DefParamIndex/dut.sv, line:12:1, endln:20:10 +\_module_inst: work@hierdefparam_a (work@hierdefparam_a), file:${SURELOG_DIR}/tests/DefParamIndex/dut.sv, line:12:1, endln:20:10 |vpiParent: \_design: (work@hierdefparam_top) |vpiFullName:work@hierdefparam_a |vpiDefName:work@hierdefparam_a |uhdmallModules: -\_module: work@hierdefparam_b (work@hierdefparam_b), file:${SURELOG_DIR}/tests/DefParamIndex/dut.sv, line:22:1, endln:33:10 +\_module_inst: work@hierdefparam_b (work@hierdefparam_b), file:${SURELOG_DIR}/tests/DefParamIndex/dut.sv, line:22:1, endln:33:10 |vpiParent: \_design: (work@hierdefparam_top) |vpiFullName:work@hierdefparam_b |vpiParameter: \_parameter: (work@hierdefparam_b.addvalue), line:23:19, endln:23:27 |vpiParent: - \_module: work@hierdefparam_b (work@hierdefparam_b), file:${SURELOG_DIR}/tests/DefParamIndex/dut.sv, line:22:1, endln:33:10 + \_module_inst: work@hierdefparam_b (work@hierdefparam_b), file:${SURELOG_DIR}/tests/DefParamIndex/dut.sv, line:22:1, endln:33:10 |UINT:44 |vpiTypespec: \_int_typespec: , line:23:13, endln:23:18 @@ -395,7 +395,7 @@ design: (work@hierdefparam_top) |vpiParamAssign: \_param_assign: , line:23:19, endln:23:32 |vpiParent: - \_module: work@hierdefparam_b (work@hierdefparam_b), file:${SURELOG_DIR}/tests/DefParamIndex/dut.sv, line:22:1, endln:33:10 + \_module_inst: work@hierdefparam_b (work@hierdefparam_b), file:${SURELOG_DIR}/tests/DefParamIndex/dut.sv, line:22:1, endln:33:10 |vpiRhs: \_constant: , line:23:30, endln:23:32 |vpiDecompile:44 @@ -408,13 +408,13 @@ design: (work@hierdefparam_top) \_parameter: (work@hierdefparam_b.addvalue), line:23:19, endln:23:27 |vpiDefName:work@hierdefparam_b |uhdmallModules: -\_module: work@hierdefparam_top (work@hierdefparam_top), file:${SURELOG_DIR}/tests/DefParamIndex/dut.sv, line:4:1, endln:10:10 +\_module_inst: work@hierdefparam_top (work@hierdefparam_top), file:${SURELOG_DIR}/tests/DefParamIndex/dut.sv, line:4:1, endln:10:10 |vpiParent: \_design: (work@hierdefparam_top) |vpiFullName:work@hierdefparam_top |vpiDefName:work@hierdefparam_top |uhdmtopModules: -\_module: work@hierdefparam_top (work@hierdefparam_top), file:${SURELOG_DIR}/tests/DefParamIndex/dut.sv, line:4:1, endln:10:10 +\_module_inst: work@hierdefparam_top (work@hierdefparam_top), file:${SURELOG_DIR}/tests/DefParamIndex/dut.sv, line:4:1, endln:10:10 |vpiName:work@hierdefparam_top |vpiDefName:work@hierdefparam_top |vpiTop:1 @@ -422,7 +422,7 @@ design: (work@hierdefparam_top) |vpiGenScopeArray: \_gen_scope_array: (work@hierdefparam_top.foo), line:5:3, endln:7:18 |vpiParent: - \_module: work@hierdefparam_top (work@hierdefparam_top), file:${SURELOG_DIR}/tests/DefParamIndex/dut.sv, line:4:1, endln:10:10 + \_module_inst: work@hierdefparam_top (work@hierdefparam_top), file:${SURELOG_DIR}/tests/DefParamIndex/dut.sv, line:4:1, endln:10:10 |vpiName:foo |vpiFullName:work@hierdefparam_top.foo |vpiGenScope: @@ -430,8 +430,8 @@ design: (work@hierdefparam_top) |vpiParent: \_gen_scope_array: (work@hierdefparam_top.foo), line:5:3, endln:7:18 |vpiFullName:work@hierdefparam_top.foo - |vpiModule: - \_module: work@hierdefparam_a (work@hierdefparam_top.foo.mod_a), file:${SURELOG_DIR}/tests/DefParamIndex/dut.sv, line:6:5, endln:6:28 + |vpiModuleInst: + \_module_inst: work@hierdefparam_a (work@hierdefparam_top.foo.mod_a), file:${SURELOG_DIR}/tests/DefParamIndex/dut.sv, line:6:5, endln:6:28 |vpiParent: \_gen_scope: (work@hierdefparam_top.foo) |vpiName:mod_a @@ -442,7 +442,7 @@ design: (work@hierdefparam_top) |vpiGenScopeArray: \_gen_scope_array: (work@hierdefparam_top.foo.mod_a.bar[0]), line:15:31, endln:17:8 |vpiParent: - \_module: work@hierdefparam_a (work@hierdefparam_top.foo.mod_a), file:${SURELOG_DIR}/tests/DefParamIndex/dut.sv, line:6:5, endln:6:28 + \_module_inst: work@hierdefparam_a (work@hierdefparam_top.foo.mod_a), file:${SURELOG_DIR}/tests/DefParamIndex/dut.sv, line:6:5, endln:6:28 |vpiName:bar[0] |vpiFullName:work@hierdefparam_top.foo.mod_a.bar[0] |vpiGenScope: @@ -460,8 +460,8 @@ design: (work@hierdefparam_top) |vpiLocalParam:1 |vpiName:i |vpiFullName:work@hierdefparam_top.foo.mod_a.bar[0].i - |vpiModule: - \_module: work@hierdefparam_b (work@hierdefparam_top.foo.mod_a.bar[0].mod_b), file:${SURELOG_DIR}/tests/DefParamIndex/dut.sv, line:16:7, endln:16:30 + |vpiModuleInst: + \_module_inst: work@hierdefparam_b (work@hierdefparam_top.foo.mod_a.bar[0].mod_b), file:${SURELOG_DIR}/tests/DefParamIndex/dut.sv, line:16:7, endln:16:30 |vpiParent: \_gen_scope: (work@hierdefparam_top.foo.mod_a.bar[0]) |vpiName:mod_b @@ -500,7 +500,7 @@ design: (work@hierdefparam_top) |vpiParamAssign: \_param_assign: , line:23:19, endln:23:32 |vpiParent: - \_module: work@hierdefparam_b (work@hierdefparam_top.foo.mod_a.bar[0].mod_b), file:${SURELOG_DIR}/tests/DefParamIndex/dut.sv, line:16:7, endln:16:30 + \_module_inst: work@hierdefparam_b (work@hierdefparam_top.foo.mod_a.bar[0].mod_b), file:${SURELOG_DIR}/tests/DefParamIndex/dut.sv, line:16:7, endln:16:30 |vpiRhs: \_constant: , line:23:30, endln:23:32 |vpiDecompile:42 @@ -517,7 +517,7 @@ design: (work@hierdefparam_top) |vpiGenScopeArray: \_gen_scope_array: (work@hierdefparam_top.foo.mod_a.bar[0].mod_b.genblk1), line:24:3, endln:26:6 |vpiParent: - \_module: work@hierdefparam_b (work@hierdefparam_top.foo.mod_a.bar[0].mod_b), file:${SURELOG_DIR}/tests/DefParamIndex/dut.sv, line:16:7, endln:16:30 + \_module_inst: work@hierdefparam_b (work@hierdefparam_top.foo.mod_a.bar[0].mod_b), file:${SURELOG_DIR}/tests/DefParamIndex/dut.sv, line:16:7, endln:16:30 |vpiName:genblk1 |vpiFullName:work@hierdefparam_top.foo.mod_a.bar[0].mod_b.genblk1 |vpiGenScope: @@ -525,8 +525,8 @@ design: (work@hierdefparam_top) |vpiParent: \_gen_scope_array: (work@hierdefparam_top.foo.mod_a.bar[0].mod_b.genblk1), line:24:3, endln:26:6 |vpiFullName:work@hierdefparam_top.foo.mod_a.bar[0].mod_b.genblk1 - |vpiModule: - \_module: work@GOOD (work@hierdefparam_top.foo.mod_a.bar[0].mod_b.genblk1.good0), file:${SURELOG_DIR}/tests/DefParamIndex/dut.sv, line:25:2, endln:25:15 + |vpiModuleInst: + \_module_inst: work@GOOD (work@hierdefparam_top.foo.mod_a.bar[0].mod_b.genblk1.good0), file:${SURELOG_DIR}/tests/DefParamIndex/dut.sv, line:25:2, endln:25:15 |vpiParent: \_gen_scope: (work@hierdefparam_top.foo.mod_a.bar[0].mod_b.genblk1) |vpiName:good0 @@ -537,7 +537,7 @@ design: (work@hierdefparam_top) |vpiGenScopeArray: \_gen_scope_array: (work@hierdefparam_top.foo.mod_a.bar[1]), line:15:31, endln:17:8 |vpiParent: - \_module: work@hierdefparam_a (work@hierdefparam_top.foo.mod_a), file:${SURELOG_DIR}/tests/DefParamIndex/dut.sv, line:6:5, endln:6:28 + \_module_inst: work@hierdefparam_a (work@hierdefparam_top.foo.mod_a), file:${SURELOG_DIR}/tests/DefParamIndex/dut.sv, line:6:5, endln:6:28 |vpiName:bar[1] |vpiFullName:work@hierdefparam_top.foo.mod_a.bar[1] |vpiGenScope: @@ -555,8 +555,8 @@ design: (work@hierdefparam_top) |vpiLocalParam:1 |vpiName:i |vpiFullName:work@hierdefparam_top.foo.mod_a.bar[1].i - |vpiModule: - \_module: work@hierdefparam_b (work@hierdefparam_top.foo.mod_a.bar[1].mod_b), file:${SURELOG_DIR}/tests/DefParamIndex/dut.sv, line:16:7, endln:16:30 + |vpiModuleInst: + \_module_inst: work@hierdefparam_b (work@hierdefparam_top.foo.mod_a.bar[1].mod_b), file:${SURELOG_DIR}/tests/DefParamIndex/dut.sv, line:16:7, endln:16:30 |vpiParent: \_gen_scope: (work@hierdefparam_top.foo.mod_a.bar[1]) |vpiName:mod_b @@ -595,7 +595,7 @@ design: (work@hierdefparam_top) |vpiParamAssign: \_param_assign: , line:23:19, endln:23:32 |vpiParent: - \_module: work@hierdefparam_b (work@hierdefparam_top.foo.mod_a.bar[1].mod_b), file:${SURELOG_DIR}/tests/DefParamIndex/dut.sv, line:16:7, endln:16:30 + \_module_inst: work@hierdefparam_b (work@hierdefparam_top.foo.mod_a.bar[1].mod_b), file:${SURELOG_DIR}/tests/DefParamIndex/dut.sv, line:16:7, endln:16:30 |vpiRhs: \_constant: , line:23:30, endln:23:32 |vpiDecompile:43 @@ -612,7 +612,7 @@ design: (work@hierdefparam_top) |vpiGenScopeArray: \_gen_scope_array: (work@hierdefparam_top.foo.mod_a.bar[1].mod_b.genblk2), line:27:3, endln:29:6 |vpiParent: - \_module: work@hierdefparam_b (work@hierdefparam_top.foo.mod_a.bar[1].mod_b), file:${SURELOG_DIR}/tests/DefParamIndex/dut.sv, line:16:7, endln:16:30 + \_module_inst: work@hierdefparam_b (work@hierdefparam_top.foo.mod_a.bar[1].mod_b), file:${SURELOG_DIR}/tests/DefParamIndex/dut.sv, line:16:7, endln:16:30 |vpiName:genblk2 |vpiFullName:work@hierdefparam_top.foo.mod_a.bar[1].mod_b.genblk2 |vpiGenScope: @@ -620,8 +620,8 @@ design: (work@hierdefparam_top) |vpiParent: \_gen_scope_array: (work@hierdefparam_top.foo.mod_a.bar[1].mod_b.genblk2), line:27:3, endln:29:6 |vpiFullName:work@hierdefparam_top.foo.mod_a.bar[1].mod_b.genblk2 - |vpiModule: - \_module: work@GOOD (work@hierdefparam_top.foo.mod_a.bar[1].mod_b.genblk2.good1), file:${SURELOG_DIR}/tests/DefParamIndex/dut.sv, line:28:6, endln:28:19 + |vpiModuleInst: + \_module_inst: work@GOOD (work@hierdefparam_top.foo.mod_a.bar[1].mod_b.genblk2.good1), file:${SURELOG_DIR}/tests/DefParamIndex/dut.sv, line:28:6, endln:28:19 |vpiParent: \_gen_scope: (work@hierdefparam_top.foo.mod_a.bar[1].mod_b.genblk2) |vpiName:good1 diff --git a/tests/DefaultNetType/DefaultNetType.log b/tests/DefaultNetType/DefaultNetType.log index 7f30360dbf..3ff04eb0f2 100644 --- a/tests/DefaultNetType/DefaultNetType.log +++ b/tests/DefaultNetType/DefaultNetType.log @@ -436,7 +436,7 @@ io_decl 1 logic_net 10 logic_typespec 9 logic_var 2 -module 11 +module_inst 11 operation 1 port 2 range 4 @@ -463,7 +463,7 @@ io_decl 2 logic_net 10 logic_typespec 9 logic_var 2 -module 11 +module_inst 11 operation 2 port 3 range 4 @@ -482,7 +482,7 @@ design: (work@ok) |vpiElaborated:1 |vpiName:work@ok |uhdmallModules: -\_module: work@M1 (work@M1), file:${SURELOG_DIR}/tests/DefaultNetType/dut.sv, line:11:1, endln:12:10 +\_module_inst: work@M1 (work@M1), file:${SURELOG_DIR}/tests/DefaultNetType/dut.sv, line:11:1, endln:12:10 |vpiParent: \_design: (work@ok) |vpiFullName:work@M1 @@ -490,13 +490,13 @@ design: (work@ok) |vpiNet: \_logic_net: (work@M1.b), line:11:17, endln:11:18 |vpiParent: - \_module: work@M1 (work@M1), file:${SURELOG_DIR}/tests/DefaultNetType/dut.sv, line:11:1, endln:12:10 + \_module_inst: work@M1 (work@M1), file:${SURELOG_DIR}/tests/DefaultNetType/dut.sv, line:11:1, endln:12:10 |vpiName:b |vpiFullName:work@M1.b |vpiPort: \_port: (b), line:11:17, endln:11:18 |vpiParent: - \_module: work@M1 (work@M1), file:${SURELOG_DIR}/tests/DefaultNetType/dut.sv, line:11:1, endln:12:10 + \_module_inst: work@M1 (work@M1), file:${SURELOG_DIR}/tests/DefaultNetType/dut.sv, line:11:1, endln:12:10 |vpiName:b |vpiDirection:1 |vpiLowConn: @@ -506,7 +506,7 @@ design: (work@ok) |vpiTypedef: \_logic_typespec: , line:11:17, endln:11:17 |uhdmallModules: -\_module: work@bad1 (work@bad1), file:${SURELOG_DIR}/tests/DefaultNetType/dut.sv, line:14:1, endln:22:10 +\_module_inst: work@bad1 (work@bad1), file:${SURELOG_DIR}/tests/DefaultNetType/dut.sv, line:14:1, endln:22:10 |vpiParent: \_design: (work@ok) |vpiFullName:work@bad1 @@ -514,7 +514,7 @@ design: (work@ok) |vpiTaskFunc: \_function: (work@bad1.__truncate_to_2_bits), line:18:1, endln:20:12 |vpiParent: - \_module: work@bad1 (work@bad1), file:${SURELOG_DIR}/tests/DefaultNetType/dut.sv, line:14:1, endln:22:10 + \_module_inst: work@bad1 (work@bad1), file:${SURELOG_DIR}/tests/DefaultNetType/dut.sv, line:14:1, endln:22:10 |vpiName:__truncate_to_2_bits |vpiFullName:work@bad1.__truncate_to_2_bits |vpiVisibility:1 @@ -541,7 +541,7 @@ design: (work@ok) |UINT:0 |vpiConstType:9 |vpiParent: - \_module: work@bad1 (work@bad1), file:${SURELOG_DIR}/tests/DefaultNetType/dut.sv, line:14:1, endln:22:10 + \_module_inst: work@bad1 (work@bad1), file:${SURELOG_DIR}/tests/DefaultNetType/dut.sv, line:14:1, endln:22:10 |vpiIODecl: \_io_decl: (i), line:18:49, endln:18:50 |vpiDirection:1 @@ -589,18 +589,18 @@ design: (work@ok) |vpiActual: \_logic_var: (__truncate_to_2_bits), line:18:10, endln:18:15 |vpiInstance: - \_module: work@bad1 (work@bad1), file:${SURELOG_DIR}/tests/DefaultNetType/dut.sv, line:14:1, endln:22:10 + \_module_inst: work@bad1 (work@bad1), file:${SURELOG_DIR}/tests/DefaultNetType/dut.sv, line:14:1, endln:22:10 |vpiNet: \_logic_net: (work@bad1.a), line:15:5, endln:15:6 |vpiParent: - \_module: work@bad1 (work@bad1), file:${SURELOG_DIR}/tests/DefaultNetType/dut.sv, line:14:1, endln:22:10 + \_module_inst: work@bad1 (work@bad1), file:${SURELOG_DIR}/tests/DefaultNetType/dut.sv, line:14:1, endln:22:10 |vpiName:a |vpiFullName:work@bad1.a |vpiNetType:48 |vpiContAssign: \_cont_assign: , line:16:8, endln:16:11 |vpiParent: - \_module: work@bad1 (work@bad1), file:${SURELOG_DIR}/tests/DefaultNetType/dut.sv, line:14:1, endln:22:10 + \_module_inst: work@bad1 (work@bad1), file:${SURELOG_DIR}/tests/DefaultNetType/dut.sv, line:14:1, endln:22:10 |vpiRhs: \_ref_obj: (work@bad1.a), line:16:10, endln:16:11 |vpiParent: @@ -616,7 +616,7 @@ design: (work@ok) |vpiName:b |vpiFullName:work@bad1.b |uhdmallModules: -\_module: work@bad2 (work@bad2), file:${SURELOG_DIR}/tests/DefaultNetType/dut.sv, line:28:1, endln:49:10 +\_module_inst: work@bad2 (work@bad2), file:${SURELOG_DIR}/tests/DefaultNetType/dut.sv, line:28:1, endln:49:10 |vpiParent: \_design: (work@ok) |vpiFullName:work@bad2 @@ -624,19 +624,19 @@ design: (work@ok) |vpiNet: \_logic_net: (work@bad2.currentState), line:30:22, endln:30:34 |vpiParent: - \_module: work@bad2 (work@bad2), file:${SURELOG_DIR}/tests/DefaultNetType/dut.sv, line:28:1, endln:49:10 + \_module_inst: work@bad2 (work@bad2), file:${SURELOG_DIR}/tests/DefaultNetType/dut.sv, line:28:1, endln:49:10 |vpiName:currentState |vpiFullName:work@bad2.currentState |vpiNet: \_logic_net: (work@bad2.nextState), line:30:36, endln:30:45 |vpiParent: - \_module: work@bad2 (work@bad2), file:${SURELOG_DIR}/tests/DefaultNetType/dut.sv, line:28:1, endln:49:10 + \_module_inst: work@bad2 (work@bad2), file:${SURELOG_DIR}/tests/DefaultNetType/dut.sv, line:28:1, endln:49:10 |vpiName:nextState |vpiFullName:work@bad2.nextState |vpiProcess: \_always: , line:32:1, endln:37:4 |vpiParent: - \_module: work@bad2 (work@bad2), file:${SURELOG_DIR}/tests/DefaultNetType/dut.sv, line:28:1, endln:49:10 + \_module_inst: work@bad2 (work@bad2), file:${SURELOG_DIR}/tests/DefaultNetType/dut.sv, line:28:1, endln:49:10 |vpiStmt: \_event_control: , line:32:11, endln:32:27 |vpiParent: @@ -718,7 +718,7 @@ design: (work@ok) |vpiProcess: \_always: , line:39:3, endln:45:8 |vpiParent: - \_module: work@bad2 (work@bad2), file:${SURELOG_DIR}/tests/DefaultNetType/dut.sv, line:28:1, endln:49:10 + \_module_inst: work@bad2 (work@bad2), file:${SURELOG_DIR}/tests/DefaultNetType/dut.sv, line:28:1, endln:49:10 |vpiStmt: \_begin: (work@bad2), line:39:15, endln:45:8 |vpiParent: @@ -825,7 +825,7 @@ design: (work@ok) |vpiFullName:work@bad2.operation |vpiAlwaysType:2 |uhdmallModules: -\_module: work@ok (work@ok), file:${SURELOG_DIR}/tests/DefaultNetType/dut.sv, line:3:1, endln:7:10 +\_module_inst: work@ok (work@ok), file:${SURELOG_DIR}/tests/DefaultNetType/dut.sv, line:3:1, endln:7:10 |vpiParent: \_design: (work@ok) |vpiFullName:work@ok @@ -833,14 +833,14 @@ design: (work@ok) |vpiNet: \_logic_net: (work@ok.a), line:4:5, endln:4:6 |vpiParent: - \_module: work@ok (work@ok), file:${SURELOG_DIR}/tests/DefaultNetType/dut.sv, line:3:1, endln:7:10 + \_module_inst: work@ok (work@ok), file:${SURELOG_DIR}/tests/DefaultNetType/dut.sv, line:3:1, endln:7:10 |vpiName:a |vpiFullName:work@ok.a |vpiNetType:48 |vpiContAssign: \_cont_assign: , line:5:8, endln:5:11 |vpiParent: - \_module: work@ok (work@ok), file:${SURELOG_DIR}/tests/DefaultNetType/dut.sv, line:3:1, endln:7:10 + \_module_inst: work@ok (work@ok), file:${SURELOG_DIR}/tests/DefaultNetType/dut.sv, line:3:1, endln:7:10 |vpiRhs: \_ref_obj: (work@ok.a), line:5:10, endln:5:11 |vpiParent: @@ -922,14 +922,14 @@ design: (work@ok) |vpiDecompile:2'd0 |vpiSize:2 |uhdmtopModules: -\_module: work@ok (work@ok), file:${SURELOG_DIR}/tests/DefaultNetType/dut.sv, line:3:1, endln:7:10 +\_module_inst: work@ok (work@ok), file:${SURELOG_DIR}/tests/DefaultNetType/dut.sv, line:3:1, endln:7:10 |vpiName:work@ok |vpiDefName:work@ok |vpiTop:1 |vpiNet: \_logic_net: (work@ok.a), line:4:5, endln:4:6 |vpiParent: - \_module: work@ok (work@ok), file:${SURELOG_DIR}/tests/DefaultNetType/dut.sv, line:3:1, endln:7:10 + \_module_inst: work@ok (work@ok), file:${SURELOG_DIR}/tests/DefaultNetType/dut.sv, line:3:1, endln:7:10 |vpiTypespec: \_logic_typespec: , line:4:1, endln:4:4 |vpiName:a @@ -943,7 +943,7 @@ design: (work@ok) |vpiContAssign: \_cont_assign: , line:5:8, endln:5:11 |vpiParent: - \_module: work@ok (work@ok), file:${SURELOG_DIR}/tests/DefaultNetType/dut.sv, line:3:1, endln:7:10 + \_module_inst: work@ok (work@ok), file:${SURELOG_DIR}/tests/DefaultNetType/dut.sv, line:3:1, endln:7:10 |vpiRhs: \_ref_obj: (work@ok.a), line:5:10, endln:5:11 |vpiParent: @@ -961,21 +961,21 @@ design: (work@ok) |vpiActual: \_logic_net: (b) |uhdmtopModules: -\_module: work@bad1 (work@bad1), file:${SURELOG_DIR}/tests/DefaultNetType/dut.sv, line:14:1, endln:22:10 +\_module_inst: work@bad1 (work@bad1), file:${SURELOG_DIR}/tests/DefaultNetType/dut.sv, line:14:1, endln:22:10 |vpiName:work@bad1 |vpiDefName:work@bad1 |vpiTop:1 |vpiTaskFunc: \_function: (work@bad1.__truncate_to_2_bits), line:18:1, endln:20:12 |vpiParent: - \_module: work@bad1 (work@bad1), file:${SURELOG_DIR}/tests/DefaultNetType/dut.sv, line:14:1, endln:22:10 + \_module_inst: work@bad1 (work@bad1), file:${SURELOG_DIR}/tests/DefaultNetType/dut.sv, line:14:1, endln:22:10 |vpiName:__truncate_to_2_bits |vpiFullName:work@bad1.__truncate_to_2_bits |vpiVisibility:1 |vpiReturn: \_logic_var: , line:18:10, endln:18:15 |vpiParent: - \_module: work@bad1 (work@bad1), file:${SURELOG_DIR}/tests/DefaultNetType/dut.sv, line:14:1, endln:22:10 + \_module_inst: work@bad1 (work@bad1), file:${SURELOG_DIR}/tests/DefaultNetType/dut.sv, line:14:1, endln:22:10 |vpiIODecl: \_io_decl: (i), line:18:49, endln:18:50 |vpiParent: @@ -1007,11 +1007,11 @@ design: (work@ok) |vpiActual: \_logic_var: , line:18:10, endln:18:15 |vpiInstance: - \_module: work@bad1 (work@bad1), file:${SURELOG_DIR}/tests/DefaultNetType/dut.sv, line:14:1, endln:22:10 + \_module_inst: work@bad1 (work@bad1), file:${SURELOG_DIR}/tests/DefaultNetType/dut.sv, line:14:1, endln:22:10 |vpiNet: \_logic_net: (work@bad1.a), line:15:5, endln:15:6 |vpiParent: - \_module: work@bad1 (work@bad1), file:${SURELOG_DIR}/tests/DefaultNetType/dut.sv, line:14:1, endln:22:10 + \_module_inst: work@bad1 (work@bad1), file:${SURELOG_DIR}/tests/DefaultNetType/dut.sv, line:14:1, endln:22:10 |vpiTypespec: \_logic_typespec: , line:15:1, endln:15:4 |vpiName:a @@ -1021,7 +1021,7 @@ design: (work@ok) |vpiContAssign: \_cont_assign: , line:16:8, endln:16:11 |vpiParent: - \_module: work@bad1 (work@bad1), file:${SURELOG_DIR}/tests/DefaultNetType/dut.sv, line:14:1, endln:22:10 + \_module_inst: work@bad1 (work@bad1), file:${SURELOG_DIR}/tests/DefaultNetType/dut.sv, line:14:1, endln:22:10 |vpiRhs: \_ref_obj: (work@bad1.a), line:16:10, endln:16:11 |vpiParent: @@ -1037,12 +1037,12 @@ design: (work@ok) |vpiName:b |vpiFullName:work@bad1.b |uhdmtopModules: -\_module: work@bad2 (work@bad2), file:${SURELOG_DIR}/tests/DefaultNetType/dut.sv, line:28:1, endln:49:10 +\_module_inst: work@bad2 (work@bad2), file:${SURELOG_DIR}/tests/DefaultNetType/dut.sv, line:28:1, endln:49:10 |vpiName:work@bad2 |vpiVariables: \_enum_var: (work@bad2.currentState), line:30:22, endln:30:34 |vpiParent: - \_module: work@bad2 (work@bad2), file:${SURELOG_DIR}/tests/DefaultNetType/dut.sv, line:28:1, endln:49:10 + \_module_inst: work@bad2 (work@bad2), file:${SURELOG_DIR}/tests/DefaultNetType/dut.sv, line:28:1, endln:49:10 |vpiTypespec: \_enum_typespec: |vpiEnumConst: @@ -1075,7 +1075,7 @@ design: (work@ok) |vpiVariables: \_enum_var: (work@bad2.nextState), line:30:36, endln:30:45 |vpiParent: - \_module: work@bad2 (work@bad2), file:${SURELOG_DIR}/tests/DefaultNetType/dut.sv, line:28:1, endln:49:10 + \_module_inst: work@bad2 (work@bad2), file:${SURELOG_DIR}/tests/DefaultNetType/dut.sv, line:28:1, endln:49:10 |vpiTypespec: \_enum_typespec: |vpiName:nextState @@ -1086,14 +1086,14 @@ design: (work@ok) |vpiNet: \_logic_net: (work@bad2.b), line:47:7, endln:47:8 |vpiParent: - \_module: work@bad2 (work@bad2), file:${SURELOG_DIR}/tests/DefaultNetType/dut.sv, line:28:1, endln:49:10 + \_module_inst: work@bad2 (work@bad2), file:${SURELOG_DIR}/tests/DefaultNetType/dut.sv, line:28:1, endln:49:10 |vpiName:b |vpiFullName:work@bad2.b |vpiTopModule:1 |vpiProcess: \_always: , line:32:1, endln:37:4 |vpiParent: - \_module: work@bad2 (work@bad2), file:${SURELOG_DIR}/tests/DefaultNetType/dut.sv, line:28:1, endln:49:10 + \_module_inst: work@bad2 (work@bad2), file:${SURELOG_DIR}/tests/DefaultNetType/dut.sv, line:28:1, endln:49:10 |vpiStmt: \_event_control: , line:32:11, endln:32:27 |vpiParent: @@ -1175,7 +1175,7 @@ design: (work@ok) |vpiProcess: \_always: , line:39:3, endln:45:8 |vpiParent: - \_module: work@bad2 (work@bad2), file:${SURELOG_DIR}/tests/DefaultNetType/dut.sv, line:28:1, endln:49:10 + \_module_inst: work@bad2 (work@bad2), file:${SURELOG_DIR}/tests/DefaultNetType/dut.sv, line:28:1, endln:49:10 |vpiStmt: \_begin: (work@bad2), line:39:15, endln:45:8 |vpiParent: @@ -1281,10 +1281,10 @@ design: (work@ok) |vpiName:operation |vpiFullName:work@bad2.operation |vpiAlwaysType:2 - |vpiModule: - \_module: work@M1 (work@bad2.m1), file:${SURELOG_DIR}/tests/DefaultNetType/dut.sv, line:47:1, endln:47:10 + |vpiModuleInst: + \_module_inst: work@M1 (work@bad2.m1), file:${SURELOG_DIR}/tests/DefaultNetType/dut.sv, line:47:1, endln:47:10 |vpiParent: - \_module: work@bad2 (work@bad2), file:${SURELOG_DIR}/tests/DefaultNetType/dut.sv, line:28:1, endln:49:10 + \_module_inst: work@bad2 (work@bad2), file:${SURELOG_DIR}/tests/DefaultNetType/dut.sv, line:28:1, endln:49:10 |vpiName:m1 |vpiFullName:work@bad2.m1 |vpiDefName:work@M1 @@ -1293,17 +1293,17 @@ design: (work@ok) |vpiNet: \_logic_net: (work@bad2.m1.b), line:11:17, endln:11:18 |vpiParent: - \_module: work@M1 (work@bad2.m1), file:${SURELOG_DIR}/tests/DefaultNetType/dut.sv, line:47:1, endln:47:10 + \_module_inst: work@M1 (work@bad2.m1), file:${SURELOG_DIR}/tests/DefaultNetType/dut.sv, line:47:1, endln:47:10 |vpiTypespec: \_logic_typespec: , line:11:17, endln:11:17 |vpiName:b |vpiFullName:work@bad2.m1.b |vpiInstance: - \_module: work@bad2 (work@bad2), file:${SURELOG_DIR}/tests/DefaultNetType/dut.sv, line:28:1, endln:49:10 + \_module_inst: work@bad2 (work@bad2), file:${SURELOG_DIR}/tests/DefaultNetType/dut.sv, line:28:1, endln:49:10 |vpiPort: \_port: (b), line:11:17, endln:11:18 |vpiParent: - \_module: work@M1 (work@bad2.m1), file:${SURELOG_DIR}/tests/DefaultNetType/dut.sv, line:47:1, endln:47:10 + \_module_inst: work@M1 (work@bad2.m1), file:${SURELOG_DIR}/tests/DefaultNetType/dut.sv, line:47:1, endln:47:10 |vpiName:b |vpiDirection:1 |vpiHighConn: @@ -1325,7 +1325,7 @@ design: (work@ok) |vpiTypedef: \_logic_typespec: , line:11:17, endln:11:17 |vpiInstance: - \_module: work@M1 (work@bad2.m1), file:${SURELOG_DIR}/tests/DefaultNetType/dut.sv, line:47:1, endln:47:10 + \_module_inst: work@M1 (work@bad2.m1), file:${SURELOG_DIR}/tests/DefaultNetType/dut.sv, line:47:1, endln:47:10 =================== [ FATAL] : 0 [ SYNTAX] : 0 diff --git a/tests/DefaultTag/DefaultTag.log b/tests/DefaultTag/DefaultTag.log index 65acf2ffe9..ab4efd6f2d 100644 --- a/tests/DefaultTag/DefaultTag.log +++ b/tests/DefaultTag/DefaultTag.log @@ -156,7 +156,7 @@ n<> u<129> t c<1> l<1:1> el<11:1> constant 75 design 1 logic_typespec 24 -module 4 +module_inst 4 operation 7 param_assign 2 parameter 3 @@ -172,7 +172,7 @@ typespec_member 24 constant 75 design 1 logic_typespec 24 -module 4 +module_inst 4 operation 7 param_assign 2 parameter 3 @@ -195,21 +195,21 @@ design: (work@top) |vpiElaborated:1 |vpiName:work@top |uhdmallModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/DefaultTag/dut.sv, line:1:1, endln:9:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/DefaultTag/dut.sv, line:1:1, endln:9:10 |vpiParent: \_design: (work@top) |vpiFullName:work@top |vpiParameter: \_parameter: (work@top.X), line:8:23, endln:8:24 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/DefaultTag/dut.sv, line:1:1, endln:9:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/DefaultTag/dut.sv, line:1:1, endln:9:10 |vpiTypespec: \_struct_typespec: (struct_1), line:2:12, endln:2:18 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/DefaultTag/dut.sv, line:1:1, endln:9:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/DefaultTag/dut.sv, line:1:1, endln:9:10 |vpiName:struct_1 |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/DefaultTag/dut.sv, line:1:1, endln:9:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/DefaultTag/dut.sv, line:1:1, endln:9:10 |vpiPacked:1 |vpiTypespecMember: \_typespec_member: (a), line:3:19, endln:3:20 @@ -352,7 +352,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:8:23, endln:8:55 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/DefaultTag/dut.sv, line:1:1, endln:9:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/DefaultTag/dut.sv, line:1:1, endln:9:10 |vpiRhs: \_operation: , line:8:27, endln:8:55 |vpiOpType:75 @@ -395,19 +395,19 @@ design: (work@top) \_struct_typespec: (struct_1), line:2:12, endln:2:18 |vpiDefName:work@top |uhdmtopModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/DefaultTag/dut.sv, line:1:1, endln:9:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/DefaultTag/dut.sv, line:1:1, endln:9:10 |vpiName:work@top |vpiParameter: \_parameter: (work@top.X), line:8:23, endln:8:24 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/DefaultTag/dut.sv, line:1:1, endln:9:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/DefaultTag/dut.sv, line:1:1, endln:9:10 |vpiTypespec: \_struct_typespec: (struct_1), line:2:12, endln:2:18 |vpiParent: \_parameter: (work@top.X), line:8:23, endln:8:24 |vpiName:struct_1 |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/DefaultTag/dut.sv, line:1:1, endln:9:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/DefaultTag/dut.sv, line:1:1, endln:9:10 |vpiPacked:1 |vpiTypespecMember: \_typespec_member: (a), line:3:19, endln:3:20 @@ -550,7 +550,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:8:23, endln:8:55 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/DefaultTag/dut.sv, line:1:1, endln:9:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/DefaultTag/dut.sv, line:1:1, endln:9:10 |vpiRhs: \_operation: , line:8:27, endln:8:55 |vpiParent: diff --git a/tests/DeferAssert/DeferAssert.log b/tests/DeferAssert/DeferAssert.log index 4b07cbf403..1068524c09 100644 --- a/tests/DeferAssert/DeferAssert.log +++ b/tests/DeferAssert/DeferAssert.log @@ -30,7 +30,7 @@ initial 1 logic_net 1 logic_typespec 1 logic_var 1 -module 3 +module_inst 3 operation 1 ref_obj 1 === UHDM Object Stats End === @@ -44,7 +44,7 @@ initial 2 logic_net 1 logic_typespec 1 logic_var 1 -module 3 +module_inst 3 operation 2 ref_obj 2 === UHDM Object Stats End === @@ -61,7 +61,7 @@ design: (work@top) |vpiElaborated:1 |vpiName:work@top |uhdmallModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/DeferAssert/dut.sv, line:1:1, endln:4:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/DeferAssert/dut.sv, line:1:1, endln:4:10 |vpiParent: \_design: (work@top) |vpiFullName:work@top @@ -69,14 +69,14 @@ design: (work@top) |vpiNet: \_logic_net: (work@top.a), line:2:9, endln:2:10 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/DeferAssert/dut.sv, line:1:1, endln:4:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/DeferAssert/dut.sv, line:1:1, endln:4:10 |vpiName:a |vpiFullName:work@top.a |vpiNetType:36 |vpiProcess: \_initial: , line:3:3, endln:3:31 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/DeferAssert/dut.sv, line:1:1, endln:4:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/DeferAssert/dut.sv, line:1:1, endln:4:10 |vpiStmt: \_immediate_assert: , line:3:11, endln:3:31 |vpiParent: @@ -104,12 +104,12 @@ design: (work@top) |UINT:0 |vpiConstType:9 |uhdmtopModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/DeferAssert/dut.sv, line:1:1, endln:4:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/DeferAssert/dut.sv, line:1:1, endln:4:10 |vpiName:work@top |vpiVariables: \_logic_var: (work@top.a), line:2:9, endln:2:14 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/DeferAssert/dut.sv, line:1:1, endln:4:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/DeferAssert/dut.sv, line:1:1, endln:4:10 |vpiTypespec: \_logic_typespec: , line:2:3, endln:2:8 |vpiName:a @@ -127,7 +127,7 @@ design: (work@top) |vpiProcess: \_initial: , line:3:3, endln:3:31 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/DeferAssert/dut.sv, line:1:1, endln:4:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/DeferAssert/dut.sv, line:1:1, endln:4:10 |vpiStmt: \_immediate_assert: , line:3:11, endln:3:31 |vpiParent: diff --git a/tests/Delay2Param/Delay2Param.log b/tests/Delay2Param/Delay2Param.log index 0402d66f2c..235283104c 100644 --- a/tests/Delay2Param/Delay2Param.log +++ b/tests/Delay2Param/Delay2Param.log @@ -431,7 +431,7 @@ int_typespec 10 io_decl 2 logic_net 18 logic_typespec 3 -module 14 +module_inst 14 operation 15 param_assign 16 parameter 16 @@ -452,7 +452,7 @@ int_typespec 10 io_decl 2 logic_net 18 logic_typespec 3 -module 14 +module_inst 14 operation 15 param_assign 16 parameter 16 @@ -518,14 +518,14 @@ design: (work@iNToRecFN) |vpiSize:1 |STRING:1 : 1 |uhdmallModules: -\_module: work@iNToRawFN (work@iNToRawFN), file:${SURELOG_DIR}/tests/Delay2Param/dut.sv, line:1:1, endln:4:10 +\_module_inst: work@iNToRawFN (work@iNToRawFN), file:${SURELOG_DIR}/tests/Delay2Param/dut.sv, line:1:1, endln:4:10 |vpiParent: \_design: (work@iNToRecFN) |vpiFullName:work@iNToRawFN |vpiParameter: \_parameter: (work@iNToRawFN.intWidth), line:1:29, endln:1:37 |vpiParent: - \_module: work@iNToRawFN (work@iNToRawFN), file:${SURELOG_DIR}/tests/Delay2Param/dut.sv, line:1:1, endln:4:10 + \_module_inst: work@iNToRawFN (work@iNToRawFN), file:${SURELOG_DIR}/tests/Delay2Param/dut.sv, line:1:1, endln:4:10 |UINT:1 |vpiTypespec: \_int_typespec: @@ -534,14 +534,14 @@ design: (work@iNToRecFN) |vpiParameter: \_parameter: (work@iNToRawFN.expWidth), line:2:16, endln:2:24 |vpiParent: - \_module: work@iNToRawFN (work@iNToRawFN), file:${SURELOG_DIR}/tests/Delay2Param/dut.sv, line:1:1, endln:4:10 + \_module_inst: work@iNToRawFN (work@iNToRawFN), file:${SURELOG_DIR}/tests/Delay2Param/dut.sv, line:1:1, endln:4:10 |vpiLocalParam:1 |vpiName:expWidth |vpiFullName:work@iNToRawFN.expWidth |vpiParamAssign: \_param_assign: , line:1:29, endln:1:41 |vpiParent: - \_module: work@iNToRawFN (work@iNToRawFN), file:${SURELOG_DIR}/tests/Delay2Param/dut.sv, line:1:1, endln:4:10 + \_module_inst: work@iNToRawFN (work@iNToRawFN), file:${SURELOG_DIR}/tests/Delay2Param/dut.sv, line:1:1, endln:4:10 |vpiRhs: \_constant: , line:1:40, endln:1:41 |vpiDecompile:1 @@ -555,7 +555,7 @@ design: (work@iNToRecFN) |vpiParamAssign: \_param_assign: , line:2:16, endln:2:46 |vpiParent: - \_module: work@iNToRawFN (work@iNToRawFN), file:${SURELOG_DIR}/tests/Delay2Param/dut.sv, line:1:1, endln:4:10 + \_module_inst: work@iNToRawFN (work@iNToRawFN), file:${SURELOG_DIR}/tests/Delay2Param/dut.sv, line:1:1, endln:4:10 |vpiRhs: \_operation: , line:2:27, endln:2:46 |vpiOpType:24 @@ -583,26 +583,26 @@ design: (work@iNToRecFN) |vpiNet: \_logic_net: (work@iNToRawFN.adjustedNormDist), line:3:29, endln:3:45 |vpiParent: - \_module: work@iNToRawFN (work@iNToRawFN), file:${SURELOG_DIR}/tests/Delay2Param/dut.sv, line:1:1, endln:4:10 + \_module_inst: work@iNToRawFN (work@iNToRawFN), file:${SURELOG_DIR}/tests/Delay2Param/dut.sv, line:1:1, endln:4:10 |vpiName:adjustedNormDist |vpiFullName:work@iNToRawFN.adjustedNormDist |vpiNetType:1 |vpiNet: \_logic_net: (work@iNToRawFN.signedIn), line:1:44, endln:1:52 |vpiParent: - \_module: work@iNToRawFN (work@iNToRawFN), file:${SURELOG_DIR}/tests/Delay2Param/dut.sv, line:1:1, endln:4:10 + \_module_inst: work@iNToRawFN (work@iNToRawFN), file:${SURELOG_DIR}/tests/Delay2Param/dut.sv, line:1:1, endln:4:10 |vpiName:signedIn |vpiFullName:work@iNToRawFN.signedIn |vpiNet: \_logic_net: (work@iNToRawFN.sExp), line:1:54, endln:1:58 |vpiParent: - \_module: work@iNToRawFN (work@iNToRawFN), file:${SURELOG_DIR}/tests/Delay2Param/dut.sv, line:1:1, endln:4:10 + \_module_inst: work@iNToRawFN (work@iNToRawFN), file:${SURELOG_DIR}/tests/Delay2Param/dut.sv, line:1:1, endln:4:10 |vpiName:sExp |vpiFullName:work@iNToRawFN.sExp |vpiPort: \_port: (signedIn), line:1:44, endln:1:52 |vpiParent: - \_module: work@iNToRawFN (work@iNToRawFN), file:${SURELOG_DIR}/tests/Delay2Param/dut.sv, line:1:1, endln:4:10 + \_module_inst: work@iNToRawFN (work@iNToRawFN), file:${SURELOG_DIR}/tests/Delay2Param/dut.sv, line:1:1, endln:4:10 |vpiName:signedIn |vpiDirection:3 |vpiLowConn: @@ -612,7 +612,7 @@ design: (work@iNToRecFN) |vpiPort: \_port: (sExp), line:1:54, endln:1:58 |vpiParent: - \_module: work@iNToRawFN (work@iNToRawFN), file:${SURELOG_DIR}/tests/Delay2Param/dut.sv, line:1:1, endln:4:10 + \_module_inst: work@iNToRawFN (work@iNToRawFN), file:${SURELOG_DIR}/tests/Delay2Param/dut.sv, line:1:1, endln:4:10 |vpiName:sExp |vpiDirection:3 |vpiLowConn: @@ -620,14 +620,14 @@ design: (work@iNToRecFN) |vpiActual: \_logic_net: (work@iNToRawFN.sExp), line:1:54, endln:1:58 |uhdmallModules: -\_module: work@iNToRawFN3 (work@iNToRawFN3), file:${SURELOG_DIR}/tests/Delay2Param/dut.sv, line:6:1, endln:11:10 +\_module_inst: work@iNToRawFN3 (work@iNToRawFN3), file:${SURELOG_DIR}/tests/Delay2Param/dut.sv, line:6:1, endln:11:10 |vpiParent: \_design: (work@iNToRecFN) |vpiFullName:work@iNToRawFN3 |vpiParameter: \_parameter: (work@iNToRawFN3.intWidth), line:6:30, endln:6:38 |vpiParent: - \_module: work@iNToRawFN3 (work@iNToRawFN3), file:${SURELOG_DIR}/tests/Delay2Param/dut.sv, line:6:1, endln:11:10 + \_module_inst: work@iNToRawFN3 (work@iNToRawFN3), file:${SURELOG_DIR}/tests/Delay2Param/dut.sv, line:6:1, endln:11:10 |UINT:1 |vpiTypespec: \_int_typespec: @@ -636,7 +636,7 @@ design: (work@iNToRecFN) |vpiParameter: \_parameter: (work@iNToRawFN3.intWidth2), line:6:54, endln:6:63 |vpiParent: - \_module: work@iNToRawFN3 (work@iNToRawFN3), file:${SURELOG_DIR}/tests/Delay2Param/dut.sv, line:6:1, endln:11:10 + \_module_inst: work@iNToRawFN3 (work@iNToRawFN3), file:${SURELOG_DIR}/tests/Delay2Param/dut.sv, line:6:1, endln:11:10 |UINT:1 |vpiTypespec: \_int_typespec: @@ -645,21 +645,21 @@ design: (work@iNToRecFN) |vpiParameter: \_parameter: (work@iNToRawFN3.expWidth), line:7:16, endln:7:24 |vpiParent: - \_module: work@iNToRawFN3 (work@iNToRawFN3), file:${SURELOG_DIR}/tests/Delay2Param/dut.sv, line:6:1, endln:11:10 + \_module_inst: work@iNToRawFN3 (work@iNToRawFN3), file:${SURELOG_DIR}/tests/Delay2Param/dut.sv, line:6:1, endln:11:10 |vpiLocalParam:1 |vpiName:expWidth |vpiFullName:work@iNToRawFN3.expWidth |vpiParameter: \_parameter: (work@iNToRawFN3.expWidth2), line:8:16, endln:8:25 |vpiParent: - \_module: work@iNToRawFN3 (work@iNToRawFN3), file:${SURELOG_DIR}/tests/Delay2Param/dut.sv, line:6:1, endln:11:10 + \_module_inst: work@iNToRawFN3 (work@iNToRawFN3), file:${SURELOG_DIR}/tests/Delay2Param/dut.sv, line:6:1, endln:11:10 |vpiLocalParam:1 |vpiName:expWidth2 |vpiFullName:work@iNToRawFN3.expWidth2 |vpiParamAssign: \_param_assign: , line:6:30, endln:6:42 |vpiParent: - \_module: work@iNToRawFN3 (work@iNToRawFN3), file:${SURELOG_DIR}/tests/Delay2Param/dut.sv, line:6:1, endln:11:10 + \_module_inst: work@iNToRawFN3 (work@iNToRawFN3), file:${SURELOG_DIR}/tests/Delay2Param/dut.sv, line:6:1, endln:11:10 |vpiRhs: \_constant: , line:6:41, endln:6:42 |vpiDecompile:1 @@ -673,7 +673,7 @@ design: (work@iNToRecFN) |vpiParamAssign: \_param_assign: , line:6:54, endln:6:67 |vpiParent: - \_module: work@iNToRawFN3 (work@iNToRawFN3), file:${SURELOG_DIR}/tests/Delay2Param/dut.sv, line:6:1, endln:11:10 + \_module_inst: work@iNToRawFN3 (work@iNToRawFN3), file:${SURELOG_DIR}/tests/Delay2Param/dut.sv, line:6:1, endln:11:10 |vpiRhs: \_constant: , line:6:66, endln:6:67 |vpiDecompile:1 @@ -687,7 +687,7 @@ design: (work@iNToRecFN) |vpiParamAssign: \_param_assign: , line:7:16, endln:7:46 |vpiParent: - \_module: work@iNToRawFN3 (work@iNToRawFN3), file:${SURELOG_DIR}/tests/Delay2Param/dut.sv, line:6:1, endln:11:10 + \_module_inst: work@iNToRawFN3 (work@iNToRawFN3), file:${SURELOG_DIR}/tests/Delay2Param/dut.sv, line:6:1, endln:11:10 |vpiRhs: \_operation: , line:7:27, endln:7:46 |vpiOpType:24 @@ -714,7 +714,7 @@ design: (work@iNToRecFN) |vpiParamAssign: \_param_assign: , line:8:16, endln:8:48 |vpiParent: - \_module: work@iNToRawFN3 (work@iNToRawFN3), file:${SURELOG_DIR}/tests/Delay2Param/dut.sv, line:6:1, endln:11:10 + \_module_inst: work@iNToRawFN3 (work@iNToRawFN3), file:${SURELOG_DIR}/tests/Delay2Param/dut.sv, line:6:1, endln:11:10 |vpiRhs: \_operation: , line:8:28, endln:8:48 |vpiOpType:24 @@ -742,33 +742,33 @@ design: (work@iNToRecFN) |vpiNet: \_logic_net: (work@iNToRawFN3.adjustedNormDist), line:9:29, endln:9:45 |vpiParent: - \_module: work@iNToRawFN3 (work@iNToRawFN3), file:${SURELOG_DIR}/tests/Delay2Param/dut.sv, line:6:1, endln:11:10 + \_module_inst: work@iNToRawFN3 (work@iNToRawFN3), file:${SURELOG_DIR}/tests/Delay2Param/dut.sv, line:6:1, endln:11:10 |vpiName:adjustedNormDist |vpiFullName:work@iNToRawFN3.adjustedNormDist |vpiNetType:1 |vpiNet: \_logic_net: (work@iNToRawFN3.adjustedNormDist2), line:10:30, endln:10:47 |vpiParent: - \_module: work@iNToRawFN3 (work@iNToRawFN3), file:${SURELOG_DIR}/tests/Delay2Param/dut.sv, line:6:1, endln:11:10 + \_module_inst: work@iNToRawFN3 (work@iNToRawFN3), file:${SURELOG_DIR}/tests/Delay2Param/dut.sv, line:6:1, endln:11:10 |vpiName:adjustedNormDist2 |vpiFullName:work@iNToRawFN3.adjustedNormDist2 |vpiNetType:1 |vpiNet: \_logic_net: (work@iNToRawFN3.signedIn), line:6:70, endln:6:78 |vpiParent: - \_module: work@iNToRawFN3 (work@iNToRawFN3), file:${SURELOG_DIR}/tests/Delay2Param/dut.sv, line:6:1, endln:11:10 + \_module_inst: work@iNToRawFN3 (work@iNToRawFN3), file:${SURELOG_DIR}/tests/Delay2Param/dut.sv, line:6:1, endln:11:10 |vpiName:signedIn |vpiFullName:work@iNToRawFN3.signedIn |vpiNet: \_logic_net: (work@iNToRawFN3.sExp), line:6:80, endln:6:84 |vpiParent: - \_module: work@iNToRawFN3 (work@iNToRawFN3), file:${SURELOG_DIR}/tests/Delay2Param/dut.sv, line:6:1, endln:11:10 + \_module_inst: work@iNToRawFN3 (work@iNToRawFN3), file:${SURELOG_DIR}/tests/Delay2Param/dut.sv, line:6:1, endln:11:10 |vpiName:sExp |vpiFullName:work@iNToRawFN3.sExp |vpiPort: \_port: (signedIn), line:6:70, endln:6:78 |vpiParent: - \_module: work@iNToRawFN3 (work@iNToRawFN3), file:${SURELOG_DIR}/tests/Delay2Param/dut.sv, line:6:1, endln:11:10 + \_module_inst: work@iNToRawFN3 (work@iNToRawFN3), file:${SURELOG_DIR}/tests/Delay2Param/dut.sv, line:6:1, endln:11:10 |vpiName:signedIn |vpiDirection:3 |vpiLowConn: @@ -778,7 +778,7 @@ design: (work@iNToRecFN) |vpiPort: \_port: (sExp), line:6:80, endln:6:84 |vpiParent: - \_module: work@iNToRawFN3 (work@iNToRawFN3), file:${SURELOG_DIR}/tests/Delay2Param/dut.sv, line:6:1, endln:11:10 + \_module_inst: work@iNToRawFN3 (work@iNToRawFN3), file:${SURELOG_DIR}/tests/Delay2Param/dut.sv, line:6:1, endln:11:10 |vpiName:sExp |vpiDirection:3 |vpiLowConn: @@ -786,14 +786,14 @@ design: (work@iNToRecFN) |vpiActual: \_logic_net: (work@iNToRawFN3.sExp), line:6:80, endln:6:84 |uhdmallModules: -\_module: work@iNToRecFN (work@iNToRecFN), file:${SURELOG_DIR}/tests/Delay2Param/dut.sv, line:23:1, endln:29:10 +\_module_inst: work@iNToRecFN (work@iNToRecFN), file:${SURELOG_DIR}/tests/Delay2Param/dut.sv, line:23:1, endln:29:10 |vpiParent: \_design: (work@iNToRecFN) |vpiFullName:work@iNToRecFN |vpiParameter: \_parameter: (work@iNToRecFN.intWidth), line:23:30, endln:23:38 |vpiParent: - \_module: work@iNToRecFN (work@iNToRecFN), file:${SURELOG_DIR}/tests/Delay2Param/dut.sv, line:23:1, endln:29:10 + \_module_inst: work@iNToRecFN (work@iNToRecFN), file:${SURELOG_DIR}/tests/Delay2Param/dut.sv, line:23:1, endln:29:10 |UINT:64 |vpiTypespec: \_int_typespec: @@ -802,7 +802,7 @@ design: (work@iNToRecFN) |vpiParameter: \_parameter: (work@iNToRecFN.intWidth2), line:23:55, endln:23:64 |vpiParent: - \_module: work@iNToRecFN (work@iNToRecFN), file:${SURELOG_DIR}/tests/Delay2Param/dut.sv, line:23:1, endln:29:10 + \_module_inst: work@iNToRecFN (work@iNToRecFN), file:${SURELOG_DIR}/tests/Delay2Param/dut.sv, line:23:1, endln:29:10 |UINT:64 |vpiTypespec: \_int_typespec: @@ -811,7 +811,7 @@ design: (work@iNToRecFN) |vpiParamAssign: \_param_assign: , line:23:30, endln:23:43 |vpiParent: - \_module: work@iNToRecFN (work@iNToRecFN), file:${SURELOG_DIR}/tests/Delay2Param/dut.sv, line:23:1, endln:29:10 + \_module_inst: work@iNToRecFN (work@iNToRecFN), file:${SURELOG_DIR}/tests/Delay2Param/dut.sv, line:23:1, endln:29:10 |vpiRhs: \_constant: , line:23:41, endln:23:43 |vpiDecompile:64 @@ -825,7 +825,7 @@ design: (work@iNToRecFN) |vpiParamAssign: \_param_assign: , line:23:55, endln:23:69 |vpiParent: - \_module: work@iNToRecFN (work@iNToRecFN), file:${SURELOG_DIR}/tests/Delay2Param/dut.sv, line:23:1, endln:29:10 + \_module_inst: work@iNToRecFN (work@iNToRecFN), file:${SURELOG_DIR}/tests/Delay2Param/dut.sv, line:23:1, endln:29:10 |vpiRhs: \_constant: , line:23:67, endln:23:69 |vpiDecompile:64 @@ -838,12 +838,12 @@ design: (work@iNToRecFN) \_parameter: (work@iNToRecFN.intWidth2), line:23:55, endln:23:64 |vpiDefName:work@iNToRecFN |uhdmtopModules: -\_module: work@iNToRecFN (work@iNToRecFN), file:${SURELOG_DIR}/tests/Delay2Param/dut.sv, line:23:1, endln:29:10 +\_module_inst: work@iNToRecFN (work@iNToRecFN), file:${SURELOG_DIR}/tests/Delay2Param/dut.sv, line:23:1, endln:29:10 |vpiName:work@iNToRecFN |vpiParameter: \_parameter: (work@iNToRecFN.intWidth), line:23:30, endln:23:38 |vpiParent: - \_module: work@iNToRecFN (work@iNToRecFN), file:${SURELOG_DIR}/tests/Delay2Param/dut.sv, line:23:1, endln:29:10 + \_module_inst: work@iNToRecFN (work@iNToRecFN), file:${SURELOG_DIR}/tests/Delay2Param/dut.sv, line:23:1, endln:29:10 |UINT:64 |vpiTypespec: \_int_typespec: @@ -854,7 +854,7 @@ design: (work@iNToRecFN) |vpiParameter: \_parameter: (work@iNToRecFN.intWidth2), line:23:55, endln:23:64 |vpiParent: - \_module: work@iNToRecFN (work@iNToRecFN), file:${SURELOG_DIR}/tests/Delay2Param/dut.sv, line:23:1, endln:29:10 + \_module_inst: work@iNToRecFN (work@iNToRecFN), file:${SURELOG_DIR}/tests/Delay2Param/dut.sv, line:23:1, endln:29:10 |UINT:64 |vpiTypespec: \_int_typespec: @@ -865,7 +865,7 @@ design: (work@iNToRecFN) |vpiParamAssign: \_param_assign: , line:23:30, endln:23:43 |vpiParent: - \_module: work@iNToRecFN (work@iNToRecFN), file:${SURELOG_DIR}/tests/Delay2Param/dut.sv, line:23:1, endln:29:10 + \_module_inst: work@iNToRecFN (work@iNToRecFN), file:${SURELOG_DIR}/tests/Delay2Param/dut.sv, line:23:1, endln:29:10 |vpiRhs: \_constant: , line:23:41, endln:23:43 |vpiDecompile:64 @@ -879,7 +879,7 @@ design: (work@iNToRecFN) |vpiParamAssign: \_param_assign: , line:23:55, endln:23:69 |vpiParent: - \_module: work@iNToRecFN (work@iNToRecFN), file:${SURELOG_DIR}/tests/Delay2Param/dut.sv, line:23:1, endln:29:10 + \_module_inst: work@iNToRecFN (work@iNToRecFN), file:${SURELOG_DIR}/tests/Delay2Param/dut.sv, line:23:1, endln:29:10 |vpiRhs: \_constant: , line:23:67, endln:23:69 |vpiDecompile:64 @@ -895,28 +895,28 @@ design: (work@iNToRecFN) |vpiNet: \_logic_net: (work@iNToRecFN.signedIn), line:24:33, endln:24:41 |vpiParent: - \_module: work@iNToRecFN (work@iNToRecFN), file:${SURELOG_DIR}/tests/Delay2Param/dut.sv, line:23:1, endln:29:10 + \_module_inst: work@iNToRecFN (work@iNToRecFN), file:${SURELOG_DIR}/tests/Delay2Param/dut.sv, line:23:1, endln:29:10 |vpiName:signedIn |vpiFullName:work@iNToRecFN.signedIn |vpiNetType:1 |vpiNet: \_logic_net: (work@iNToRecFN.sExp), line:24:43, endln:24:47 |vpiParent: - \_module: work@iNToRecFN (work@iNToRecFN), file:${SURELOG_DIR}/tests/Delay2Param/dut.sv, line:23:1, endln:29:10 + \_module_inst: work@iNToRecFN (work@iNToRecFN), file:${SURELOG_DIR}/tests/Delay2Param/dut.sv, line:23:1, endln:29:10 |vpiName:sExp |vpiFullName:work@iNToRecFN.sExp |vpiNetType:1 |vpiTopModule:1 - |vpiModule: - \_module: work@iNToRawFN (work@iNToRecFN.iNToRawFN), file:${SURELOG_DIR}/tests/Delay2Param/dut.sv, line:24:2, endln:24:49 + |vpiModuleInst: + \_module_inst: work@iNToRawFN (work@iNToRecFN.iNToRawFN), file:${SURELOG_DIR}/tests/Delay2Param/dut.sv, line:24:2, endln:24:49 |vpiParent: - \_module: work@iNToRecFN (work@iNToRecFN), file:${SURELOG_DIR}/tests/Delay2Param/dut.sv, line:23:1, endln:29:10 + \_module_inst: work@iNToRecFN (work@iNToRecFN), file:${SURELOG_DIR}/tests/Delay2Param/dut.sv, line:23:1, endln:29:10 |vpiName:iNToRawFN |vpiFullName:work@iNToRecFN.iNToRawFN |vpiParameter: \_parameter: (work@iNToRecFN.iNToRawFN.intWidth), line:1:29, endln:1:37 |vpiParent: - \_module: work@iNToRawFN (work@iNToRecFN.iNToRawFN), file:${SURELOG_DIR}/tests/Delay2Param/dut.sv, line:24:2, endln:24:49 + \_module_inst: work@iNToRawFN (work@iNToRecFN.iNToRawFN), file:${SURELOG_DIR}/tests/Delay2Param/dut.sv, line:24:2, endln:24:49 |UINT:1 |vpiTypespec: \_int_typespec: @@ -927,14 +927,14 @@ design: (work@iNToRecFN) |vpiParameter: \_parameter: (work@iNToRecFN.iNToRawFN.expWidth), line:2:16, endln:2:24 |vpiParent: - \_module: work@iNToRawFN (work@iNToRecFN.iNToRawFN), file:${SURELOG_DIR}/tests/Delay2Param/dut.sv, line:24:2, endln:24:49 + \_module_inst: work@iNToRawFN (work@iNToRecFN.iNToRawFN), file:${SURELOG_DIR}/tests/Delay2Param/dut.sv, line:24:2, endln:24:49 |vpiLocalParam:1 |vpiName:expWidth |vpiFullName:work@iNToRecFN.iNToRawFN.expWidth |vpiParamAssign: \_param_assign: , line:1:29, endln:1:41 |vpiParent: - \_module: work@iNToRawFN (work@iNToRecFN.iNToRawFN), file:${SURELOG_DIR}/tests/Delay2Param/dut.sv, line:24:2, endln:24:49 + \_module_inst: work@iNToRawFN (work@iNToRecFN.iNToRawFN), file:${SURELOG_DIR}/tests/Delay2Param/dut.sv, line:24:2, endln:24:49 |vpiOverriden:1 |vpiRhs: \_constant: , line:1:40, endln:1:41 @@ -949,7 +949,7 @@ design: (work@iNToRecFN) |vpiParamAssign: \_param_assign: , line:2:16, endln:2:46 |vpiParent: - \_module: work@iNToRawFN (work@iNToRecFN.iNToRawFN), file:${SURELOG_DIR}/tests/Delay2Param/dut.sv, line:24:2, endln:24:49 + \_module_inst: work@iNToRawFN (work@iNToRecFN.iNToRawFN), file:${SURELOG_DIR}/tests/Delay2Param/dut.sv, line:24:2, endln:24:49 |vpiRhs: \_constant: , line:2:27, endln:2:46 |vpiDecompile:7 @@ -964,7 +964,7 @@ design: (work@iNToRecFN) |vpiNet: \_logic_net: (work@iNToRecFN.iNToRawFN.adjustedNormDist), line:3:29, endln:3:45 |vpiParent: - \_module: work@iNToRawFN (work@iNToRecFN.iNToRawFN), file:${SURELOG_DIR}/tests/Delay2Param/dut.sv, line:24:2, endln:24:49 + \_module_inst: work@iNToRawFN (work@iNToRecFN.iNToRawFN), file:${SURELOG_DIR}/tests/Delay2Param/dut.sv, line:24:2, endln:24:49 |vpiTypespec: \_logic_typespec: , line:3:5, endln:3:28 |vpiRange: @@ -991,21 +991,21 @@ design: (work@iNToRecFN) |vpiNet: \_logic_net: (work@iNToRecFN.iNToRawFN.signedIn), line:1:44, endln:1:52 |vpiParent: - \_module: work@iNToRawFN (work@iNToRecFN.iNToRawFN), file:${SURELOG_DIR}/tests/Delay2Param/dut.sv, line:24:2, endln:24:49 + \_module_inst: work@iNToRawFN (work@iNToRecFN.iNToRawFN), file:${SURELOG_DIR}/tests/Delay2Param/dut.sv, line:24:2, endln:24:49 |vpiName:signedIn |vpiFullName:work@iNToRecFN.iNToRawFN.signedIn |vpiNet: \_logic_net: (work@iNToRecFN.iNToRawFN.sExp), line:1:54, endln:1:58 |vpiParent: - \_module: work@iNToRawFN (work@iNToRecFN.iNToRawFN), file:${SURELOG_DIR}/tests/Delay2Param/dut.sv, line:24:2, endln:24:49 + \_module_inst: work@iNToRawFN (work@iNToRecFN.iNToRawFN), file:${SURELOG_DIR}/tests/Delay2Param/dut.sv, line:24:2, endln:24:49 |vpiName:sExp |vpiFullName:work@iNToRecFN.iNToRawFN.sExp |vpiInstance: - \_module: work@iNToRecFN (work@iNToRecFN), file:${SURELOG_DIR}/tests/Delay2Param/dut.sv, line:23:1, endln:29:10 + \_module_inst: work@iNToRecFN (work@iNToRecFN), file:${SURELOG_DIR}/tests/Delay2Param/dut.sv, line:23:1, endln:29:10 |vpiPort: \_port: (signedIn), line:1:44, endln:1:52 |vpiParent: - \_module: work@iNToRawFN (work@iNToRecFN.iNToRawFN), file:${SURELOG_DIR}/tests/Delay2Param/dut.sv, line:24:2, endln:24:49 + \_module_inst: work@iNToRawFN (work@iNToRecFN.iNToRawFN), file:${SURELOG_DIR}/tests/Delay2Param/dut.sv, line:24:2, endln:24:49 |vpiName:signedIn |vpiDirection:3 |vpiHighConn: @@ -1025,11 +1025,11 @@ design: (work@iNToRecFN) |vpiActual: \_logic_net: (work@iNToRecFN.iNToRawFN.signedIn), line:1:44, endln:1:52 |vpiInstance: - \_module: work@iNToRawFN (work@iNToRecFN.iNToRawFN), file:${SURELOG_DIR}/tests/Delay2Param/dut.sv, line:24:2, endln:24:49 + \_module_inst: work@iNToRawFN (work@iNToRecFN.iNToRawFN), file:${SURELOG_DIR}/tests/Delay2Param/dut.sv, line:24:2, endln:24:49 |vpiPort: \_port: (sExp), line:1:54, endln:1:58 |vpiParent: - \_module: work@iNToRawFN (work@iNToRecFN.iNToRawFN), file:${SURELOG_DIR}/tests/Delay2Param/dut.sv, line:24:2, endln:24:49 + \_module_inst: work@iNToRawFN (work@iNToRecFN.iNToRawFN), file:${SURELOG_DIR}/tests/Delay2Param/dut.sv, line:24:2, endln:24:49 |vpiName:sExp |vpiDirection:3 |vpiHighConn: @@ -1049,17 +1049,17 @@ design: (work@iNToRecFN) |vpiActual: \_logic_net: (work@iNToRecFN.iNToRawFN.sExp), line:1:54, endln:1:58 |vpiInstance: - \_module: work@iNToRawFN (work@iNToRecFN.iNToRawFN), file:${SURELOG_DIR}/tests/Delay2Param/dut.sv, line:24:2, endln:24:49 - |vpiModule: - \_module: work@iNToRawFN3 (work@iNToRecFN.iNToRawFN3), file:${SURELOG_DIR}/tests/Delay2Param/dut.sv, line:25:2, endln:25:62 + \_module_inst: work@iNToRawFN (work@iNToRecFN.iNToRawFN), file:${SURELOG_DIR}/tests/Delay2Param/dut.sv, line:24:2, endln:24:49 + |vpiModuleInst: + \_module_inst: work@iNToRawFN3 (work@iNToRecFN.iNToRawFN3), file:${SURELOG_DIR}/tests/Delay2Param/dut.sv, line:25:2, endln:25:62 |vpiParent: - \_module: work@iNToRecFN (work@iNToRecFN), file:${SURELOG_DIR}/tests/Delay2Param/dut.sv, line:23:1, endln:29:10 + \_module_inst: work@iNToRecFN (work@iNToRecFN), file:${SURELOG_DIR}/tests/Delay2Param/dut.sv, line:23:1, endln:29:10 |vpiName:iNToRawFN3 |vpiFullName:work@iNToRecFN.iNToRawFN3 |vpiParameter: \_parameter: (work@iNToRecFN.iNToRawFN3.intWidth), line:6:30, endln:6:38 |vpiParent: - \_module: work@iNToRawFN3 (work@iNToRecFN.iNToRawFN3), file:${SURELOG_DIR}/tests/Delay2Param/dut.sv, line:25:2, endln:25:62 + \_module_inst: work@iNToRawFN3 (work@iNToRecFN.iNToRawFN3), file:${SURELOG_DIR}/tests/Delay2Param/dut.sv, line:25:2, endln:25:62 |UINT:1 |vpiTypespec: \_int_typespec: @@ -1070,7 +1070,7 @@ design: (work@iNToRecFN) |vpiParameter: \_parameter: (work@iNToRecFN.iNToRawFN3.intWidth2), line:6:54, endln:6:63 |vpiParent: - \_module: work@iNToRawFN3 (work@iNToRecFN.iNToRawFN3), file:${SURELOG_DIR}/tests/Delay2Param/dut.sv, line:25:2, endln:25:62 + \_module_inst: work@iNToRawFN3 (work@iNToRecFN.iNToRawFN3), file:${SURELOG_DIR}/tests/Delay2Param/dut.sv, line:25:2, endln:25:62 |UINT:1 |vpiTypespec: \_int_typespec: @@ -1081,21 +1081,21 @@ design: (work@iNToRecFN) |vpiParameter: \_parameter: (work@iNToRecFN.iNToRawFN3.expWidth), line:7:16, endln:7:24 |vpiParent: - \_module: work@iNToRawFN3 (work@iNToRecFN.iNToRawFN3), file:${SURELOG_DIR}/tests/Delay2Param/dut.sv, line:25:2, endln:25:62 + \_module_inst: work@iNToRawFN3 (work@iNToRecFN.iNToRawFN3), file:${SURELOG_DIR}/tests/Delay2Param/dut.sv, line:25:2, endln:25:62 |vpiLocalParam:1 |vpiName:expWidth |vpiFullName:work@iNToRecFN.iNToRawFN3.expWidth |vpiParameter: \_parameter: (work@iNToRecFN.iNToRawFN3.expWidth2), line:8:16, endln:8:25 |vpiParent: - \_module: work@iNToRawFN3 (work@iNToRecFN.iNToRawFN3), file:${SURELOG_DIR}/tests/Delay2Param/dut.sv, line:25:2, endln:25:62 + \_module_inst: work@iNToRawFN3 (work@iNToRecFN.iNToRawFN3), file:${SURELOG_DIR}/tests/Delay2Param/dut.sv, line:25:2, endln:25:62 |vpiLocalParam:1 |vpiName:expWidth2 |vpiFullName:work@iNToRecFN.iNToRawFN3.expWidth2 |vpiParamAssign: \_param_assign: , line:6:30, endln:6:42 |vpiParent: - \_module: work@iNToRawFN3 (work@iNToRecFN.iNToRawFN3), file:${SURELOG_DIR}/tests/Delay2Param/dut.sv, line:25:2, endln:25:62 + \_module_inst: work@iNToRawFN3 (work@iNToRecFN.iNToRawFN3), file:${SURELOG_DIR}/tests/Delay2Param/dut.sv, line:25:2, endln:25:62 |vpiOverriden:1 |vpiRhs: \_constant: , line:6:41, endln:6:42 @@ -1110,7 +1110,7 @@ design: (work@iNToRecFN) |vpiParamAssign: \_param_assign: , line:6:54, endln:6:67 |vpiParent: - \_module: work@iNToRawFN3 (work@iNToRecFN.iNToRawFN3), file:${SURELOG_DIR}/tests/Delay2Param/dut.sv, line:25:2, endln:25:62 + \_module_inst: work@iNToRawFN3 (work@iNToRecFN.iNToRawFN3), file:${SURELOG_DIR}/tests/Delay2Param/dut.sv, line:25:2, endln:25:62 |vpiOverriden:1 |vpiRhs: \_constant: , line:6:66, endln:6:67 @@ -1125,7 +1125,7 @@ design: (work@iNToRecFN) |vpiParamAssign: \_param_assign: , line:7:16, endln:7:46 |vpiParent: - \_module: work@iNToRawFN3 (work@iNToRecFN.iNToRawFN3), file:${SURELOG_DIR}/tests/Delay2Param/dut.sv, line:25:2, endln:25:62 + \_module_inst: work@iNToRawFN3 (work@iNToRecFN.iNToRawFN3), file:${SURELOG_DIR}/tests/Delay2Param/dut.sv, line:25:2, endln:25:62 |vpiRhs: \_constant: , line:7:27, endln:7:46 |vpiDecompile:7 @@ -1137,7 +1137,7 @@ design: (work@iNToRecFN) |vpiParamAssign: \_param_assign: , line:8:16, endln:8:48 |vpiParent: - \_module: work@iNToRawFN3 (work@iNToRecFN.iNToRawFN3), file:${SURELOG_DIR}/tests/Delay2Param/dut.sv, line:25:2, endln:25:62 + \_module_inst: work@iNToRawFN3 (work@iNToRecFN.iNToRawFN3), file:${SURELOG_DIR}/tests/Delay2Param/dut.sv, line:25:2, endln:25:62 |vpiRhs: \_constant: , line:8:28, endln:8:48 |vpiDecompile:7 @@ -1152,7 +1152,7 @@ design: (work@iNToRecFN) |vpiNet: \_logic_net: (work@iNToRecFN.iNToRawFN3.adjustedNormDist), line:9:29, endln:9:45 |vpiParent: - \_module: work@iNToRawFN3 (work@iNToRecFN.iNToRawFN3), file:${SURELOG_DIR}/tests/Delay2Param/dut.sv, line:25:2, endln:25:62 + \_module_inst: work@iNToRawFN3 (work@iNToRecFN.iNToRawFN3), file:${SURELOG_DIR}/tests/Delay2Param/dut.sv, line:25:2, endln:25:62 |vpiTypespec: \_logic_typespec: , line:9:5, endln:9:28 |vpiRange: @@ -1179,7 +1179,7 @@ design: (work@iNToRecFN) |vpiNet: \_logic_net: (work@iNToRecFN.iNToRawFN3.adjustedNormDist2), line:10:30, endln:10:47 |vpiParent: - \_module: work@iNToRawFN3 (work@iNToRecFN.iNToRawFN3), file:${SURELOG_DIR}/tests/Delay2Param/dut.sv, line:25:2, endln:25:62 + \_module_inst: work@iNToRawFN3 (work@iNToRecFN.iNToRawFN3), file:${SURELOG_DIR}/tests/Delay2Param/dut.sv, line:25:2, endln:25:62 |vpiTypespec: \_logic_typespec: , line:10:5, endln:10:29 |vpiRange: @@ -1206,21 +1206,21 @@ design: (work@iNToRecFN) |vpiNet: \_logic_net: (work@iNToRecFN.iNToRawFN3.signedIn), line:6:70, endln:6:78 |vpiParent: - \_module: work@iNToRawFN3 (work@iNToRecFN.iNToRawFN3), file:${SURELOG_DIR}/tests/Delay2Param/dut.sv, line:25:2, endln:25:62 + \_module_inst: work@iNToRawFN3 (work@iNToRecFN.iNToRawFN3), file:${SURELOG_DIR}/tests/Delay2Param/dut.sv, line:25:2, endln:25:62 |vpiName:signedIn |vpiFullName:work@iNToRecFN.iNToRawFN3.signedIn |vpiNet: \_logic_net: (work@iNToRecFN.iNToRawFN3.sExp), line:6:80, endln:6:84 |vpiParent: - \_module: work@iNToRawFN3 (work@iNToRecFN.iNToRawFN3), file:${SURELOG_DIR}/tests/Delay2Param/dut.sv, line:25:2, endln:25:62 + \_module_inst: work@iNToRawFN3 (work@iNToRecFN.iNToRawFN3), file:${SURELOG_DIR}/tests/Delay2Param/dut.sv, line:25:2, endln:25:62 |vpiName:sExp |vpiFullName:work@iNToRecFN.iNToRawFN3.sExp |vpiInstance: - \_module: work@iNToRecFN (work@iNToRecFN), file:${SURELOG_DIR}/tests/Delay2Param/dut.sv, line:23:1, endln:29:10 + \_module_inst: work@iNToRecFN (work@iNToRecFN), file:${SURELOG_DIR}/tests/Delay2Param/dut.sv, line:23:1, endln:29:10 |vpiPort: \_port: (signedIn), line:6:70, endln:6:78 |vpiParent: - \_module: work@iNToRawFN3 (work@iNToRecFN.iNToRawFN3), file:${SURELOG_DIR}/tests/Delay2Param/dut.sv, line:25:2, endln:25:62 + \_module_inst: work@iNToRawFN3 (work@iNToRecFN.iNToRawFN3), file:${SURELOG_DIR}/tests/Delay2Param/dut.sv, line:25:2, endln:25:62 |vpiName:signedIn |vpiDirection:3 |vpiHighConn: @@ -1240,11 +1240,11 @@ design: (work@iNToRecFN) |vpiActual: \_logic_net: (work@iNToRecFN.iNToRawFN3.signedIn), line:6:70, endln:6:78 |vpiInstance: - \_module: work@iNToRawFN3 (work@iNToRecFN.iNToRawFN3), file:${SURELOG_DIR}/tests/Delay2Param/dut.sv, line:25:2, endln:25:62 + \_module_inst: work@iNToRawFN3 (work@iNToRecFN.iNToRawFN3), file:${SURELOG_DIR}/tests/Delay2Param/dut.sv, line:25:2, endln:25:62 |vpiPort: \_port: (sExp), line:6:80, endln:6:84 |vpiParent: - \_module: work@iNToRawFN3 (work@iNToRecFN.iNToRawFN3), file:${SURELOG_DIR}/tests/Delay2Param/dut.sv, line:25:2, endln:25:62 + \_module_inst: work@iNToRawFN3 (work@iNToRecFN.iNToRawFN3), file:${SURELOG_DIR}/tests/Delay2Param/dut.sv, line:25:2, endln:25:62 |vpiName:sExp |vpiDirection:3 |vpiHighConn: @@ -1264,11 +1264,11 @@ design: (work@iNToRecFN) |vpiActual: \_logic_net: (work@iNToRecFN.iNToRawFN3.sExp), line:6:80, endln:6:84 |vpiInstance: - \_module: work@iNToRawFN3 (work@iNToRecFN.iNToRawFN3), file:${SURELOG_DIR}/tests/Delay2Param/dut.sv, line:25:2, endln:25:62 + \_module_inst: work@iNToRawFN3 (work@iNToRecFN.iNToRawFN3), file:${SURELOG_DIR}/tests/Delay2Param/dut.sv, line:25:2, endln:25:62 |vpiPrimitive: \_udp: work@BUFG (work@iNToRecFN.), file:${SURELOG_DIR}/tests/Delay2Param/dut.sv, line:27:1, endln:27:21 |vpiParent: - \_module: work@iNToRecFN (work@iNToRecFN), file:${SURELOG_DIR}/tests/Delay2Param/dut.sv, line:23:1, endln:29:10 + \_module_inst: work@iNToRecFN (work@iNToRecFN), file:${SURELOG_DIR}/tests/Delay2Param/dut.sv, line:23:1, endln:29:10 |vpiDefName:work@BUFG |vpiFullName:work@iNToRecFN. |vpiDelay: diff --git a/tests/DelayAssign/DelayAssign.log b/tests/DelayAssign/DelayAssign.log index 78a2dce4ed..84087bd781 100644 --- a/tests/DelayAssign/DelayAssign.log +++ b/tests/DelayAssign/DelayAssign.log @@ -999,7 +999,7 @@ io_decl 11 logic_net 40 logic_typespec 41 logic_var 1 -module 4 +module_inst 4 operation 4 package 2 part_select 3 @@ -1035,7 +1035,7 @@ io_decl 22 logic_net 40 logic_typespec 41 logic_var 1 -module 4 +module_inst 4 operation 7 package 2 part_select 6 @@ -1532,7 +1532,7 @@ design: (work@SimDTM) \_int_typespec: |vpiSigned:1 |uhdmallModules: -\_module: work@SimDTM (work@SimDTM), file:${SURELOG_DIR}/tests/DelayAssign/dut.sv, line:16:1, endln:79:10 +\_module_inst: work@SimDTM (work@SimDTM), file:${SURELOG_DIR}/tests/DelayAssign/dut.sv, line:16:1, endln:79:10 |vpiParent: \_design: (work@SimDTM) |vpiFullName:work@SimDTM @@ -1540,149 +1540,149 @@ design: (work@SimDTM) |vpiNet: \_logic_net: (work@SimDTM.clk), line:17:9, endln:17:12 |vpiParent: - \_module: work@SimDTM (work@SimDTM), file:${SURELOG_DIR}/tests/DelayAssign/dut.sv, line:16:1, endln:79:10 + \_module_inst: work@SimDTM (work@SimDTM), file:${SURELOG_DIR}/tests/DelayAssign/dut.sv, line:16:1, endln:79:10 |vpiName:clk |vpiFullName:work@SimDTM.clk |vpiNet: \_logic_net: (work@SimDTM.reset), line:18:9, endln:18:14 |vpiParent: - \_module: work@SimDTM (work@SimDTM), file:${SURELOG_DIR}/tests/DelayAssign/dut.sv, line:16:1, endln:79:10 + \_module_inst: work@SimDTM (work@SimDTM), file:${SURELOG_DIR}/tests/DelayAssign/dut.sv, line:16:1, endln:79:10 |vpiName:reset |vpiFullName:work@SimDTM.reset |vpiNet: \_logic_net: (work@SimDTM.debug_req_valid), line:20:17, endln:20:32 |vpiParent: - \_module: work@SimDTM (work@SimDTM), file:${SURELOG_DIR}/tests/DelayAssign/dut.sv, line:16:1, endln:79:10 + \_module_inst: work@SimDTM (work@SimDTM), file:${SURELOG_DIR}/tests/DelayAssign/dut.sv, line:16:1, endln:79:10 |vpiName:debug_req_valid |vpiFullName:work@SimDTM.debug_req_valid |vpiNet: \_logic_net: (work@SimDTM.debug_req_ready), line:21:17, endln:21:32 |vpiParent: - \_module: work@SimDTM (work@SimDTM), file:${SURELOG_DIR}/tests/DelayAssign/dut.sv, line:16:1, endln:79:10 + \_module_inst: work@SimDTM (work@SimDTM), file:${SURELOG_DIR}/tests/DelayAssign/dut.sv, line:16:1, endln:79:10 |vpiName:debug_req_ready |vpiFullName:work@SimDTM.debug_req_ready |vpiNet: \_logic_net: (work@SimDTM.debug_req_bits_addr), line:22:17, endln:22:36 |vpiParent: - \_module: work@SimDTM (work@SimDTM), file:${SURELOG_DIR}/tests/DelayAssign/dut.sv, line:16:1, endln:79:10 + \_module_inst: work@SimDTM (work@SimDTM), file:${SURELOG_DIR}/tests/DelayAssign/dut.sv, line:16:1, endln:79:10 |vpiName:debug_req_bits_addr |vpiFullName:work@SimDTM.debug_req_bits_addr |vpiNet: \_logic_net: (work@SimDTM.debug_req_bits_op), line:23:17, endln:23:34 |vpiParent: - \_module: work@SimDTM (work@SimDTM), file:${SURELOG_DIR}/tests/DelayAssign/dut.sv, line:16:1, endln:79:10 + \_module_inst: work@SimDTM (work@SimDTM), file:${SURELOG_DIR}/tests/DelayAssign/dut.sv, line:16:1, endln:79:10 |vpiName:debug_req_bits_op |vpiFullName:work@SimDTM.debug_req_bits_op |vpiNet: \_logic_net: (work@SimDTM.debug_req_bits_data), line:24:17, endln:24:36 |vpiParent: - \_module: work@SimDTM (work@SimDTM), file:${SURELOG_DIR}/tests/DelayAssign/dut.sv, line:16:1, endln:79:10 + \_module_inst: work@SimDTM (work@SimDTM), file:${SURELOG_DIR}/tests/DelayAssign/dut.sv, line:16:1, endln:79:10 |vpiName:debug_req_bits_data |vpiFullName:work@SimDTM.debug_req_bits_data |vpiNet: \_logic_net: (work@SimDTM.debug_resp_valid), line:26:17, endln:26:33 |vpiParent: - \_module: work@SimDTM (work@SimDTM), file:${SURELOG_DIR}/tests/DelayAssign/dut.sv, line:16:1, endln:79:10 + \_module_inst: work@SimDTM (work@SimDTM), file:${SURELOG_DIR}/tests/DelayAssign/dut.sv, line:16:1, endln:79:10 |vpiName:debug_resp_valid |vpiFullName:work@SimDTM.debug_resp_valid |vpiNet: \_logic_net: (work@SimDTM.debug_resp_ready), line:27:17, endln:27:33 |vpiParent: - \_module: work@SimDTM (work@SimDTM), file:${SURELOG_DIR}/tests/DelayAssign/dut.sv, line:16:1, endln:79:10 + \_module_inst: work@SimDTM (work@SimDTM), file:${SURELOG_DIR}/tests/DelayAssign/dut.sv, line:16:1, endln:79:10 |vpiName:debug_resp_ready |vpiFullName:work@SimDTM.debug_resp_ready |vpiNet: \_logic_net: (work@SimDTM.debug_resp_bits_resp), line:28:17, endln:28:37 |vpiParent: - \_module: work@SimDTM (work@SimDTM), file:${SURELOG_DIR}/tests/DelayAssign/dut.sv, line:16:1, endln:79:10 + \_module_inst: work@SimDTM (work@SimDTM), file:${SURELOG_DIR}/tests/DelayAssign/dut.sv, line:16:1, endln:79:10 |vpiName:debug_resp_bits_resp |vpiFullName:work@SimDTM.debug_resp_bits_resp |vpiNet: \_logic_net: (work@SimDTM.debug_resp_bits_data), line:29:17, endln:29:37 |vpiParent: - \_module: work@SimDTM (work@SimDTM), file:${SURELOG_DIR}/tests/DelayAssign/dut.sv, line:16:1, endln:79:10 + \_module_inst: work@SimDTM (work@SimDTM), file:${SURELOG_DIR}/tests/DelayAssign/dut.sv, line:16:1, endln:79:10 |vpiName:debug_resp_bits_data |vpiFullName:work@SimDTM.debug_resp_bits_data |vpiNet: \_logic_net: (work@SimDTM.exit), line:31:17, endln:31:21 |vpiParent: - \_module: work@SimDTM (work@SimDTM), file:${SURELOG_DIR}/tests/DelayAssign/dut.sv, line:16:1, endln:79:10 + \_module_inst: work@SimDTM (work@SimDTM), file:${SURELOG_DIR}/tests/DelayAssign/dut.sv, line:16:1, endln:79:10 |vpiName:exit |vpiFullName:work@SimDTM.exit |vpiNet: \_logic_net: (work@SimDTM.r_reset), line:34:7, endln:34:14 |vpiParent: - \_module: work@SimDTM (work@SimDTM), file:${SURELOG_DIR}/tests/DelayAssign/dut.sv, line:16:1, endln:79:10 + \_module_inst: work@SimDTM (work@SimDTM), file:${SURELOG_DIR}/tests/DelayAssign/dut.sv, line:16:1, endln:79:10 |vpiName:r_reset |vpiFullName:work@SimDTM.r_reset |vpiNet: \_logic_net: (work@SimDTM.__debug_req_ready), line:36:13, endln:36:30 |vpiParent: - \_module: work@SimDTM (work@SimDTM), file:${SURELOG_DIR}/tests/DelayAssign/dut.sv, line:16:1, endln:79:10 + \_module_inst: work@SimDTM (work@SimDTM), file:${SURELOG_DIR}/tests/DelayAssign/dut.sv, line:16:1, endln:79:10 |vpiName:__debug_req_ready |vpiFullName:work@SimDTM.__debug_req_ready |vpiNetType:1 |vpiNet: \_logic_net: (work@SimDTM.__debug_resp_valid), line:37:13, endln:37:31 |vpiParent: - \_module: work@SimDTM (work@SimDTM), file:${SURELOG_DIR}/tests/DelayAssign/dut.sv, line:16:1, endln:79:10 + \_module_inst: work@SimDTM (work@SimDTM), file:${SURELOG_DIR}/tests/DelayAssign/dut.sv, line:16:1, endln:79:10 |vpiName:__debug_resp_valid |vpiFullName:work@SimDTM.__debug_resp_valid |vpiNetType:1 |vpiNet: \_logic_net: (work@SimDTM.__debug_resp_bits_resp), line:38:20, endln:38:42 |vpiParent: - \_module: work@SimDTM (work@SimDTM), file:${SURELOG_DIR}/tests/DelayAssign/dut.sv, line:16:1, endln:79:10 + \_module_inst: work@SimDTM (work@SimDTM), file:${SURELOG_DIR}/tests/DelayAssign/dut.sv, line:16:1, endln:79:10 |vpiName:__debug_resp_bits_resp |vpiFullName:work@SimDTM.__debug_resp_bits_resp |vpiNetType:1 |vpiNet: \_logic_net: (work@SimDTM.__debug_resp_bits_data), line:39:20, endln:39:42 |vpiParent: - \_module: work@SimDTM (work@SimDTM), file:${SURELOG_DIR}/tests/DelayAssign/dut.sv, line:16:1, endln:79:10 + \_module_inst: work@SimDTM (work@SimDTM), file:${SURELOG_DIR}/tests/DelayAssign/dut.sv, line:16:1, endln:79:10 |vpiName:__debug_resp_bits_data |vpiFullName:work@SimDTM.__debug_resp_bits_data |vpiNetType:1 |vpiNet: \_logic_net: (work@SimDTM.__debug_req_valid), line:41:7, endln:41:24 |vpiParent: - \_module: work@SimDTM (work@SimDTM), file:${SURELOG_DIR}/tests/DelayAssign/dut.sv, line:16:1, endln:79:10 + \_module_inst: work@SimDTM (work@SimDTM), file:${SURELOG_DIR}/tests/DelayAssign/dut.sv, line:16:1, endln:79:10 |vpiName:__debug_req_valid |vpiFullName:work@SimDTM.__debug_req_valid |vpiNet: \_logic_net: (work@SimDTM.__debug_req_bits_addr), line:42:7, endln:42:28 |vpiParent: - \_module: work@SimDTM (work@SimDTM), file:${SURELOG_DIR}/tests/DelayAssign/dut.sv, line:16:1, endln:79:10 + \_module_inst: work@SimDTM (work@SimDTM), file:${SURELOG_DIR}/tests/DelayAssign/dut.sv, line:16:1, endln:79:10 |vpiName:__debug_req_bits_addr |vpiFullName:work@SimDTM.__debug_req_bits_addr |vpiNet: \_logic_net: (work@SimDTM.__debug_req_bits_op), line:43:7, endln:43:26 |vpiParent: - \_module: work@SimDTM (work@SimDTM), file:${SURELOG_DIR}/tests/DelayAssign/dut.sv, line:16:1, endln:79:10 + \_module_inst: work@SimDTM (work@SimDTM), file:${SURELOG_DIR}/tests/DelayAssign/dut.sv, line:16:1, endln:79:10 |vpiName:__debug_req_bits_op |vpiFullName:work@SimDTM.__debug_req_bits_op |vpiNet: \_logic_net: (work@SimDTM.__debug_req_bits_data), line:44:7, endln:44:28 |vpiParent: - \_module: work@SimDTM (work@SimDTM), file:${SURELOG_DIR}/tests/DelayAssign/dut.sv, line:16:1, endln:79:10 + \_module_inst: work@SimDTM (work@SimDTM), file:${SURELOG_DIR}/tests/DelayAssign/dut.sv, line:16:1, endln:79:10 |vpiName:__debug_req_bits_data |vpiFullName:work@SimDTM.__debug_req_bits_data |vpiNet: \_logic_net: (work@SimDTM.__debug_resp_ready), line:45:7, endln:45:25 |vpiParent: - \_module: work@SimDTM (work@SimDTM), file:${SURELOG_DIR}/tests/DelayAssign/dut.sv, line:16:1, endln:79:10 + \_module_inst: work@SimDTM (work@SimDTM), file:${SURELOG_DIR}/tests/DelayAssign/dut.sv, line:16:1, endln:79:10 |vpiName:__debug_resp_ready |vpiFullName:work@SimDTM.__debug_resp_ready |vpiNet: \_logic_net: (work@SimDTM.__exit), line:46:7, endln:46:13 |vpiParent: - \_module: work@SimDTM (work@SimDTM), file:${SURELOG_DIR}/tests/DelayAssign/dut.sv, line:16:1, endln:79:10 + \_module_inst: work@SimDTM (work@SimDTM), file:${SURELOG_DIR}/tests/DelayAssign/dut.sv, line:16:1, endln:79:10 |vpiName:__exit |vpiFullName:work@SimDTM.__exit |vpiPort: \_port: (clk), line:17:9, endln:17:12 |vpiParent: - \_module: work@SimDTM (work@SimDTM), file:${SURELOG_DIR}/tests/DelayAssign/dut.sv, line:16:1, endln:79:10 + \_module_inst: work@SimDTM (work@SimDTM), file:${SURELOG_DIR}/tests/DelayAssign/dut.sv, line:16:1, endln:79:10 |vpiName:clk |vpiDirection:1 |vpiLowConn: @@ -1694,7 +1694,7 @@ design: (work@SimDTM) |vpiPort: \_port: (reset), line:18:9, endln:18:14 |vpiParent: - \_module: work@SimDTM (work@SimDTM), file:${SURELOG_DIR}/tests/DelayAssign/dut.sv, line:16:1, endln:79:10 + \_module_inst: work@SimDTM (work@SimDTM), file:${SURELOG_DIR}/tests/DelayAssign/dut.sv, line:16:1, endln:79:10 |vpiName:reset |vpiDirection:1 |vpiLowConn: @@ -1706,7 +1706,7 @@ design: (work@SimDTM) |vpiPort: \_port: (debug_req_valid), line:20:17, endln:20:32 |vpiParent: - \_module: work@SimDTM (work@SimDTM), file:${SURELOG_DIR}/tests/DelayAssign/dut.sv, line:16:1, endln:79:10 + \_module_inst: work@SimDTM (work@SimDTM), file:${SURELOG_DIR}/tests/DelayAssign/dut.sv, line:16:1, endln:79:10 |vpiName:debug_req_valid |vpiDirection:2 |vpiLowConn: @@ -1718,7 +1718,7 @@ design: (work@SimDTM) |vpiPort: \_port: (debug_req_ready), line:21:17, endln:21:32 |vpiParent: - \_module: work@SimDTM (work@SimDTM), file:${SURELOG_DIR}/tests/DelayAssign/dut.sv, line:16:1, endln:79:10 + \_module_inst: work@SimDTM (work@SimDTM), file:${SURELOG_DIR}/tests/DelayAssign/dut.sv, line:16:1, endln:79:10 |vpiName:debug_req_ready |vpiDirection:1 |vpiLowConn: @@ -1730,7 +1730,7 @@ design: (work@SimDTM) |vpiPort: \_port: (debug_req_bits_addr), line:22:17, endln:22:36 |vpiParent: - \_module: work@SimDTM (work@SimDTM), file:${SURELOG_DIR}/tests/DelayAssign/dut.sv, line:16:1, endln:79:10 + \_module_inst: work@SimDTM (work@SimDTM), file:${SURELOG_DIR}/tests/DelayAssign/dut.sv, line:16:1, endln:79:10 |vpiName:debug_req_bits_addr |vpiDirection:2 |vpiLowConn: @@ -1760,7 +1760,7 @@ design: (work@SimDTM) |vpiPort: \_port: (debug_req_bits_op), line:23:17, endln:23:34 |vpiParent: - \_module: work@SimDTM (work@SimDTM), file:${SURELOG_DIR}/tests/DelayAssign/dut.sv, line:16:1, endln:79:10 + \_module_inst: work@SimDTM (work@SimDTM), file:${SURELOG_DIR}/tests/DelayAssign/dut.sv, line:16:1, endln:79:10 |vpiName:debug_req_bits_op |vpiDirection:2 |vpiLowConn: @@ -1790,7 +1790,7 @@ design: (work@SimDTM) |vpiPort: \_port: (debug_req_bits_data), line:24:17, endln:24:36 |vpiParent: - \_module: work@SimDTM (work@SimDTM), file:${SURELOG_DIR}/tests/DelayAssign/dut.sv, line:16:1, endln:79:10 + \_module_inst: work@SimDTM (work@SimDTM), file:${SURELOG_DIR}/tests/DelayAssign/dut.sv, line:16:1, endln:79:10 |vpiName:debug_req_bits_data |vpiDirection:2 |vpiLowConn: @@ -1820,7 +1820,7 @@ design: (work@SimDTM) |vpiPort: \_port: (debug_resp_valid), line:26:17, endln:26:33 |vpiParent: - \_module: work@SimDTM (work@SimDTM), file:${SURELOG_DIR}/tests/DelayAssign/dut.sv, line:16:1, endln:79:10 + \_module_inst: work@SimDTM (work@SimDTM), file:${SURELOG_DIR}/tests/DelayAssign/dut.sv, line:16:1, endln:79:10 |vpiName:debug_resp_valid |vpiDirection:1 |vpiLowConn: @@ -1832,7 +1832,7 @@ design: (work@SimDTM) |vpiPort: \_port: (debug_resp_ready), line:27:17, endln:27:33 |vpiParent: - \_module: work@SimDTM (work@SimDTM), file:${SURELOG_DIR}/tests/DelayAssign/dut.sv, line:16:1, endln:79:10 + \_module_inst: work@SimDTM (work@SimDTM), file:${SURELOG_DIR}/tests/DelayAssign/dut.sv, line:16:1, endln:79:10 |vpiName:debug_resp_ready |vpiDirection:2 |vpiLowConn: @@ -1844,7 +1844,7 @@ design: (work@SimDTM) |vpiPort: \_port: (debug_resp_bits_resp), line:28:17, endln:28:37 |vpiParent: - \_module: work@SimDTM (work@SimDTM), file:${SURELOG_DIR}/tests/DelayAssign/dut.sv, line:16:1, endln:79:10 + \_module_inst: work@SimDTM (work@SimDTM), file:${SURELOG_DIR}/tests/DelayAssign/dut.sv, line:16:1, endln:79:10 |vpiName:debug_resp_bits_resp |vpiDirection:1 |vpiLowConn: @@ -1874,7 +1874,7 @@ design: (work@SimDTM) |vpiPort: \_port: (debug_resp_bits_data), line:29:17, endln:29:37 |vpiParent: - \_module: work@SimDTM (work@SimDTM), file:${SURELOG_DIR}/tests/DelayAssign/dut.sv, line:16:1, endln:79:10 + \_module_inst: work@SimDTM (work@SimDTM), file:${SURELOG_DIR}/tests/DelayAssign/dut.sv, line:16:1, endln:79:10 |vpiName:debug_resp_bits_data |vpiDirection:1 |vpiLowConn: @@ -1904,7 +1904,7 @@ design: (work@SimDTM) |vpiPort: \_port: (exit), line:31:17, endln:31:21 |vpiParent: - \_module: work@SimDTM (work@SimDTM), file:${SURELOG_DIR}/tests/DelayAssign/dut.sv, line:16:1, endln:79:10 + \_module_inst: work@SimDTM (work@SimDTM), file:${SURELOG_DIR}/tests/DelayAssign/dut.sv, line:16:1, endln:79:10 |vpiName:exit |vpiDirection:2 |vpiLowConn: @@ -1934,7 +1934,7 @@ design: (work@SimDTM) |vpiProcess: \_always: , line:55:3, endln:78:6 |vpiParent: - \_module: work@SimDTM (work@SimDTM), file:${SURELOG_DIR}/tests/DelayAssign/dut.sv, line:16:1, endln:79:10 + \_module_inst: work@SimDTM (work@SimDTM), file:${SURELOG_DIR}/tests/DelayAssign/dut.sv, line:16:1, endln:79:10 |vpiStmt: \_event_control: , line:55:10, endln:55:24 |vpiParent: @@ -2174,7 +2174,7 @@ design: (work@SimDTM) |vpiContAssign: \_cont_assign: , line:48:15, endln:48:50 |vpiParent: - \_module: work@SimDTM (work@SimDTM), file:${SURELOG_DIR}/tests/DelayAssign/dut.sv, line:16:1, endln:79:10 + \_module_inst: work@SimDTM (work@SimDTM), file:${SURELOG_DIR}/tests/DelayAssign/dut.sv, line:16:1, endln:79:10 |vpiDelay: \_constant: , line:48:10, endln:48:14 |vpiDecompile:#0.1 @@ -2200,7 +2200,7 @@ design: (work@SimDTM) |vpiContAssign: \_cont_assign: , line:49:15, endln:49:63 |vpiParent: - \_module: work@SimDTM (work@SimDTM), file:${SURELOG_DIR}/tests/DelayAssign/dut.sv, line:16:1, endln:79:10 + \_module_inst: work@SimDTM (work@SimDTM), file:${SURELOG_DIR}/tests/DelayAssign/dut.sv, line:16:1, endln:79:10 |vpiDelay: \_constant: , line:49:10, endln:49:14 |vpiDecompile:#0.1 @@ -2240,7 +2240,7 @@ design: (work@SimDTM) |vpiContAssign: \_cont_assign: , line:50:15, endln:50:59 |vpiParent: - \_module: work@SimDTM (work@SimDTM), file:${SURELOG_DIR}/tests/DelayAssign/dut.sv, line:16:1, endln:79:10 + \_module_inst: work@SimDTM (work@SimDTM), file:${SURELOG_DIR}/tests/DelayAssign/dut.sv, line:16:1, endln:79:10 |vpiDelay: \_constant: , line:50:10, endln:50:14 |vpiDecompile:#0.1 @@ -2280,7 +2280,7 @@ design: (work@SimDTM) |vpiContAssign: \_cont_assign: , line:51:15, endln:51:64 |vpiParent: - \_module: work@SimDTM (work@SimDTM), file:${SURELOG_DIR}/tests/DelayAssign/dut.sv, line:16:1, endln:79:10 + \_module_inst: work@SimDTM (work@SimDTM), file:${SURELOG_DIR}/tests/DelayAssign/dut.sv, line:16:1, endln:79:10 |vpiDelay: \_constant: , line:51:10, endln:51:14 |vpiDecompile:#0.1 @@ -2320,7 +2320,7 @@ design: (work@SimDTM) |vpiContAssign: \_cont_assign: , line:52:15, endln:52:52 |vpiParent: - \_module: work@SimDTM (work@SimDTM), file:${SURELOG_DIR}/tests/DelayAssign/dut.sv, line:16:1, endln:79:10 + \_module_inst: work@SimDTM (work@SimDTM), file:${SURELOG_DIR}/tests/DelayAssign/dut.sv, line:16:1, endln:79:10 |vpiDelay: \_constant: , line:52:10, endln:52:14 |vpiDecompile:#0.1 @@ -2346,7 +2346,7 @@ design: (work@SimDTM) |vpiContAssign: \_cont_assign: , line:53:15, endln:53:28 |vpiParent: - \_module: work@SimDTM (work@SimDTM), file:${SURELOG_DIR}/tests/DelayAssign/dut.sv, line:16:1, endln:79:10 + \_module_inst: work@SimDTM (work@SimDTM), file:${SURELOG_DIR}/tests/DelayAssign/dut.sv, line:16:1, endln:79:10 |vpiDelay: \_constant: , line:53:10, endln:53:14 |vpiDecompile:#0.1 @@ -2370,12 +2370,12 @@ design: (work@SimDTM) |vpiActual: \_logic_net: (work@SimDTM.exit), line:31:17, endln:31:21 |uhdmtopModules: -\_module: work@SimDTM (work@SimDTM), file:${SURELOG_DIR}/tests/DelayAssign/dut.sv, line:16:1, endln:79:10 +\_module_inst: work@SimDTM (work@SimDTM), file:${SURELOG_DIR}/tests/DelayAssign/dut.sv, line:16:1, endln:79:10 |vpiName:work@SimDTM |vpiVariables: \_bit_var: (work@SimDTM.r_reset), line:34:7, endln:34:14 |vpiParent: - \_module: work@SimDTM (work@SimDTM), file:${SURELOG_DIR}/tests/DelayAssign/dut.sv, line:16:1, endln:79:10 + \_module_inst: work@SimDTM (work@SimDTM), file:${SURELOG_DIR}/tests/DelayAssign/dut.sv, line:16:1, endln:79:10 |vpiTypespec: \_bit_typespec: , line:34:3, endln:34:6 |vpiSigned:1 @@ -2385,7 +2385,7 @@ design: (work@SimDTM) |vpiVariables: \_bit_var: (work@SimDTM.__debug_req_valid), line:41:7, endln:41:24 |vpiParent: - \_module: work@SimDTM (work@SimDTM), file:${SURELOG_DIR}/tests/DelayAssign/dut.sv, line:16:1, endln:79:10 + \_module_inst: work@SimDTM (work@SimDTM), file:${SURELOG_DIR}/tests/DelayAssign/dut.sv, line:16:1, endln:79:10 |vpiTypespec: \_bit_typespec: , line:41:3, endln:41:6 |vpiSigned:1 @@ -2395,7 +2395,7 @@ design: (work@SimDTM) |vpiVariables: \_int_var: (work@SimDTM.__debug_req_bits_addr), line:42:7, endln:42:28 |vpiParent: - \_module: work@SimDTM (work@SimDTM), file:${SURELOG_DIR}/tests/DelayAssign/dut.sv, line:16:1, endln:79:10 + \_module_inst: work@SimDTM (work@SimDTM), file:${SURELOG_DIR}/tests/DelayAssign/dut.sv, line:16:1, endln:79:10 |vpiTypespec: \_int_typespec: , line:42:3, endln:42:6 |vpiSigned:1 @@ -2405,7 +2405,7 @@ design: (work@SimDTM) |vpiVariables: \_int_var: (work@SimDTM.__debug_req_bits_op), line:43:7, endln:43:26 |vpiParent: - \_module: work@SimDTM (work@SimDTM), file:${SURELOG_DIR}/tests/DelayAssign/dut.sv, line:16:1, endln:79:10 + \_module_inst: work@SimDTM (work@SimDTM), file:${SURELOG_DIR}/tests/DelayAssign/dut.sv, line:16:1, endln:79:10 |vpiTypespec: \_int_typespec: , line:43:3, endln:43:6 |vpiSigned:1 @@ -2415,7 +2415,7 @@ design: (work@SimDTM) |vpiVariables: \_int_var: (work@SimDTM.__debug_req_bits_data), line:44:7, endln:44:28 |vpiParent: - \_module: work@SimDTM (work@SimDTM), file:${SURELOG_DIR}/tests/DelayAssign/dut.sv, line:16:1, endln:79:10 + \_module_inst: work@SimDTM (work@SimDTM), file:${SURELOG_DIR}/tests/DelayAssign/dut.sv, line:16:1, endln:79:10 |vpiTypespec: \_int_typespec: , line:44:3, endln:44:6 |vpiSigned:1 @@ -2425,7 +2425,7 @@ design: (work@SimDTM) |vpiVariables: \_bit_var: (work@SimDTM.__debug_resp_ready), line:45:7, endln:45:25 |vpiParent: - \_module: work@SimDTM (work@SimDTM), file:${SURELOG_DIR}/tests/DelayAssign/dut.sv, line:16:1, endln:79:10 + \_module_inst: work@SimDTM (work@SimDTM), file:${SURELOG_DIR}/tests/DelayAssign/dut.sv, line:16:1, endln:79:10 |vpiTypespec: \_bit_typespec: , line:45:3, endln:45:6 |vpiSigned:1 @@ -2435,7 +2435,7 @@ design: (work@SimDTM) |vpiVariables: \_int_var: (work@SimDTM.__exit), line:46:7, endln:46:13 |vpiParent: - \_module: work@SimDTM (work@SimDTM), file:${SURELOG_DIR}/tests/DelayAssign/dut.sv, line:16:1, endln:79:10 + \_module_inst: work@SimDTM (work@SimDTM), file:${SURELOG_DIR}/tests/DelayAssign/dut.sv, line:16:1, endln:79:10 |vpiTypespec: \_int_typespec: , line:46:3, endln:46:6 |vpiSigned:1 @@ -2447,7 +2447,7 @@ design: (work@SimDTM) |vpiNet: \_logic_net: (work@SimDTM.clk), line:17:9, endln:17:12 |vpiParent: - \_module: work@SimDTM (work@SimDTM), file:${SURELOG_DIR}/tests/DelayAssign/dut.sv, line:16:1, endln:79:10 + \_module_inst: work@SimDTM (work@SimDTM), file:${SURELOG_DIR}/tests/DelayAssign/dut.sv, line:16:1, endln:79:10 |vpiTypespec: \_logic_typespec: , line:17:9, endln:17:9 |vpiName:clk @@ -2455,7 +2455,7 @@ design: (work@SimDTM) |vpiNet: \_logic_net: (work@SimDTM.reset), line:18:9, endln:18:14 |vpiParent: - \_module: work@SimDTM (work@SimDTM), file:${SURELOG_DIR}/tests/DelayAssign/dut.sv, line:16:1, endln:79:10 + \_module_inst: work@SimDTM (work@SimDTM), file:${SURELOG_DIR}/tests/DelayAssign/dut.sv, line:16:1, endln:79:10 |vpiTypespec: \_logic_typespec: , line:18:9, endln:18:9 |vpiName:reset @@ -2463,7 +2463,7 @@ design: (work@SimDTM) |vpiNet: \_logic_net: (work@SimDTM.debug_req_valid), line:20:17, endln:20:32 |vpiParent: - \_module: work@SimDTM (work@SimDTM), file:${SURELOG_DIR}/tests/DelayAssign/dut.sv, line:16:1, endln:79:10 + \_module_inst: work@SimDTM (work@SimDTM), file:${SURELOG_DIR}/tests/DelayAssign/dut.sv, line:16:1, endln:79:10 |vpiTypespec: \_logic_typespec: , line:20:17, endln:20:17 |vpiName:debug_req_valid @@ -2471,7 +2471,7 @@ design: (work@SimDTM) |vpiNet: \_logic_net: (work@SimDTM.debug_req_ready), line:21:17, endln:21:32 |vpiParent: - \_module: work@SimDTM (work@SimDTM), file:${SURELOG_DIR}/tests/DelayAssign/dut.sv, line:16:1, endln:79:10 + \_module_inst: work@SimDTM (work@SimDTM), file:${SURELOG_DIR}/tests/DelayAssign/dut.sv, line:16:1, endln:79:10 |vpiTypespec: \_logic_typespec: , line:21:17, endln:21:17 |vpiName:debug_req_ready @@ -2479,7 +2479,7 @@ design: (work@SimDTM) |vpiNet: \_logic_net: (work@SimDTM.debug_req_bits_addr), line:22:17, endln:22:36 |vpiParent: - \_module: work@SimDTM (work@SimDTM), file:${SURELOG_DIR}/tests/DelayAssign/dut.sv, line:16:1, endln:79:10 + \_module_inst: work@SimDTM (work@SimDTM), file:${SURELOG_DIR}/tests/DelayAssign/dut.sv, line:16:1, endln:79:10 |vpiTypespec: \_logic_typespec: , line:22:10, endln:22:16 |vpiRange: @@ -2505,7 +2505,7 @@ design: (work@SimDTM) |vpiNet: \_logic_net: (work@SimDTM.debug_req_bits_op), line:23:17, endln:23:34 |vpiParent: - \_module: work@SimDTM (work@SimDTM), file:${SURELOG_DIR}/tests/DelayAssign/dut.sv, line:16:1, endln:79:10 + \_module_inst: work@SimDTM (work@SimDTM), file:${SURELOG_DIR}/tests/DelayAssign/dut.sv, line:16:1, endln:79:10 |vpiTypespec: \_logic_typespec: , line:23:10, endln:23:16 |vpiRange: @@ -2531,7 +2531,7 @@ design: (work@SimDTM) |vpiNet: \_logic_net: (work@SimDTM.debug_req_bits_data), line:24:17, endln:24:36 |vpiParent: - \_module: work@SimDTM (work@SimDTM), file:${SURELOG_DIR}/tests/DelayAssign/dut.sv, line:16:1, endln:79:10 + \_module_inst: work@SimDTM (work@SimDTM), file:${SURELOG_DIR}/tests/DelayAssign/dut.sv, line:16:1, endln:79:10 |vpiTypespec: \_logic_typespec: , line:24:10, endln:24:16 |vpiRange: @@ -2557,7 +2557,7 @@ design: (work@SimDTM) |vpiNet: \_logic_net: (work@SimDTM.debug_resp_valid), line:26:17, endln:26:33 |vpiParent: - \_module: work@SimDTM (work@SimDTM), file:${SURELOG_DIR}/tests/DelayAssign/dut.sv, line:16:1, endln:79:10 + \_module_inst: work@SimDTM (work@SimDTM), file:${SURELOG_DIR}/tests/DelayAssign/dut.sv, line:16:1, endln:79:10 |vpiTypespec: \_logic_typespec: , line:26:17, endln:26:17 |vpiName:debug_resp_valid @@ -2565,7 +2565,7 @@ design: (work@SimDTM) |vpiNet: \_logic_net: (work@SimDTM.debug_resp_ready), line:27:17, endln:27:33 |vpiParent: - \_module: work@SimDTM (work@SimDTM), file:${SURELOG_DIR}/tests/DelayAssign/dut.sv, line:16:1, endln:79:10 + \_module_inst: work@SimDTM (work@SimDTM), file:${SURELOG_DIR}/tests/DelayAssign/dut.sv, line:16:1, endln:79:10 |vpiTypespec: \_logic_typespec: , line:27:17, endln:27:17 |vpiName:debug_resp_ready @@ -2573,7 +2573,7 @@ design: (work@SimDTM) |vpiNet: \_logic_net: (work@SimDTM.debug_resp_bits_resp), line:28:17, endln:28:37 |vpiParent: - \_module: work@SimDTM (work@SimDTM), file:${SURELOG_DIR}/tests/DelayAssign/dut.sv, line:16:1, endln:79:10 + \_module_inst: work@SimDTM (work@SimDTM), file:${SURELOG_DIR}/tests/DelayAssign/dut.sv, line:16:1, endln:79:10 |vpiTypespec: \_logic_typespec: , line:28:10, endln:28:16 |vpiRange: @@ -2599,7 +2599,7 @@ design: (work@SimDTM) |vpiNet: \_logic_net: (work@SimDTM.debug_resp_bits_data), line:29:17, endln:29:37 |vpiParent: - \_module: work@SimDTM (work@SimDTM), file:${SURELOG_DIR}/tests/DelayAssign/dut.sv, line:16:1, endln:79:10 + \_module_inst: work@SimDTM (work@SimDTM), file:${SURELOG_DIR}/tests/DelayAssign/dut.sv, line:16:1, endln:79:10 |vpiTypespec: \_logic_typespec: , line:29:10, endln:29:16 |vpiRange: @@ -2625,7 +2625,7 @@ design: (work@SimDTM) |vpiNet: \_logic_net: (work@SimDTM.exit), line:31:17, endln:31:21 |vpiParent: - \_module: work@SimDTM (work@SimDTM), file:${SURELOG_DIR}/tests/DelayAssign/dut.sv, line:16:1, endln:79:10 + \_module_inst: work@SimDTM (work@SimDTM), file:${SURELOG_DIR}/tests/DelayAssign/dut.sv, line:16:1, endln:79:10 |vpiTypespec: \_logic_typespec: , line:31:10, endln:31:16 |vpiRange: @@ -2651,7 +2651,7 @@ design: (work@SimDTM) |vpiNet: \_logic_net: (work@SimDTM.__debug_req_ready), line:36:13, endln:36:30 |vpiParent: - \_module: work@SimDTM (work@SimDTM), file:${SURELOG_DIR}/tests/DelayAssign/dut.sv, line:16:1, endln:79:10 + \_module_inst: work@SimDTM (work@SimDTM), file:${SURELOG_DIR}/tests/DelayAssign/dut.sv, line:16:1, endln:79:10 |vpiTypespec: \_logic_typespec: , line:36:3, endln:36:7 |vpiName:__debug_req_ready @@ -2660,7 +2660,7 @@ design: (work@SimDTM) |vpiNet: \_logic_net: (work@SimDTM.__debug_resp_valid), line:37:13, endln:37:31 |vpiParent: - \_module: work@SimDTM (work@SimDTM), file:${SURELOG_DIR}/tests/DelayAssign/dut.sv, line:16:1, endln:79:10 + \_module_inst: work@SimDTM (work@SimDTM), file:${SURELOG_DIR}/tests/DelayAssign/dut.sv, line:16:1, endln:79:10 |vpiTypespec: \_logic_typespec: , line:37:3, endln:37:7 |vpiName:__debug_resp_valid @@ -2669,7 +2669,7 @@ design: (work@SimDTM) |vpiNet: \_logic_net: (work@SimDTM.__debug_resp_bits_resp), line:38:20, endln:38:42 |vpiParent: - \_module: work@SimDTM (work@SimDTM), file:${SURELOG_DIR}/tests/DelayAssign/dut.sv, line:16:1, endln:79:10 + \_module_inst: work@SimDTM (work@SimDTM), file:${SURELOG_DIR}/tests/DelayAssign/dut.sv, line:16:1, endln:79:10 |vpiTypespec: \_logic_typespec: , line:38:3, endln:38:14 |vpiRange: @@ -2696,7 +2696,7 @@ design: (work@SimDTM) |vpiNet: \_logic_net: (work@SimDTM.__debug_resp_bits_data), line:39:20, endln:39:42 |vpiParent: - \_module: work@SimDTM (work@SimDTM), file:${SURELOG_DIR}/tests/DelayAssign/dut.sv, line:16:1, endln:79:10 + \_module_inst: work@SimDTM (work@SimDTM), file:${SURELOG_DIR}/tests/DelayAssign/dut.sv, line:16:1, endln:79:10 |vpiTypespec: \_logic_typespec: , line:39:3, endln:39:14 |vpiRange: @@ -2724,7 +2724,7 @@ design: (work@SimDTM) |vpiPort: \_port: (clk), line:17:9, endln:17:12 |vpiParent: - \_module: work@SimDTM (work@SimDTM), file:${SURELOG_DIR}/tests/DelayAssign/dut.sv, line:16:1, endln:79:10 + \_module_inst: work@SimDTM (work@SimDTM), file:${SURELOG_DIR}/tests/DelayAssign/dut.sv, line:16:1, endln:79:10 |vpiName:clk |vpiDirection:1 |vpiLowConn: @@ -2738,11 +2738,11 @@ design: (work@SimDTM) |vpiTypedef: \_logic_typespec: , line:17:9, endln:17:9 |vpiInstance: - \_module: work@SimDTM (work@SimDTM), file:${SURELOG_DIR}/tests/DelayAssign/dut.sv, line:16:1, endln:79:10 + \_module_inst: work@SimDTM (work@SimDTM), file:${SURELOG_DIR}/tests/DelayAssign/dut.sv, line:16:1, endln:79:10 |vpiPort: \_port: (reset), line:18:9, endln:18:14 |vpiParent: - \_module: work@SimDTM (work@SimDTM), file:${SURELOG_DIR}/tests/DelayAssign/dut.sv, line:16:1, endln:79:10 + \_module_inst: work@SimDTM (work@SimDTM), file:${SURELOG_DIR}/tests/DelayAssign/dut.sv, line:16:1, endln:79:10 |vpiName:reset |vpiDirection:1 |vpiLowConn: @@ -2756,11 +2756,11 @@ design: (work@SimDTM) |vpiTypedef: \_logic_typespec: , line:18:9, endln:18:9 |vpiInstance: - \_module: work@SimDTM (work@SimDTM), file:${SURELOG_DIR}/tests/DelayAssign/dut.sv, line:16:1, endln:79:10 + \_module_inst: work@SimDTM (work@SimDTM), file:${SURELOG_DIR}/tests/DelayAssign/dut.sv, line:16:1, endln:79:10 |vpiPort: \_port: (debug_req_valid), line:20:17, endln:20:32 |vpiParent: - \_module: work@SimDTM (work@SimDTM), file:${SURELOG_DIR}/tests/DelayAssign/dut.sv, line:16:1, endln:79:10 + \_module_inst: work@SimDTM (work@SimDTM), file:${SURELOG_DIR}/tests/DelayAssign/dut.sv, line:16:1, endln:79:10 |vpiName:debug_req_valid |vpiDirection:2 |vpiLowConn: @@ -2774,11 +2774,11 @@ design: (work@SimDTM) |vpiTypedef: \_logic_typespec: , line:20:17, endln:20:17 |vpiInstance: - \_module: work@SimDTM (work@SimDTM), file:${SURELOG_DIR}/tests/DelayAssign/dut.sv, line:16:1, endln:79:10 + \_module_inst: work@SimDTM (work@SimDTM), file:${SURELOG_DIR}/tests/DelayAssign/dut.sv, line:16:1, endln:79:10 |vpiPort: \_port: (debug_req_ready), line:21:17, endln:21:32 |vpiParent: - \_module: work@SimDTM (work@SimDTM), file:${SURELOG_DIR}/tests/DelayAssign/dut.sv, line:16:1, endln:79:10 + \_module_inst: work@SimDTM (work@SimDTM), file:${SURELOG_DIR}/tests/DelayAssign/dut.sv, line:16:1, endln:79:10 |vpiName:debug_req_ready |vpiDirection:1 |vpiLowConn: @@ -2792,11 +2792,11 @@ design: (work@SimDTM) |vpiTypedef: \_logic_typespec: , line:21:17, endln:21:17 |vpiInstance: - \_module: work@SimDTM (work@SimDTM), file:${SURELOG_DIR}/tests/DelayAssign/dut.sv, line:16:1, endln:79:10 + \_module_inst: work@SimDTM (work@SimDTM), file:${SURELOG_DIR}/tests/DelayAssign/dut.sv, line:16:1, endln:79:10 |vpiPort: \_port: (debug_req_bits_addr), line:22:17, endln:22:36 |vpiParent: - \_module: work@SimDTM (work@SimDTM), file:${SURELOG_DIR}/tests/DelayAssign/dut.sv, line:16:1, endln:79:10 + \_module_inst: work@SimDTM (work@SimDTM), file:${SURELOG_DIR}/tests/DelayAssign/dut.sv, line:16:1, endln:79:10 |vpiName:debug_req_bits_addr |vpiDirection:2 |vpiLowConn: @@ -2830,11 +2830,11 @@ design: (work@SimDTM) |UINT:0 |vpiConstType:9 |vpiInstance: - \_module: work@SimDTM (work@SimDTM), file:${SURELOG_DIR}/tests/DelayAssign/dut.sv, line:16:1, endln:79:10 + \_module_inst: work@SimDTM (work@SimDTM), file:${SURELOG_DIR}/tests/DelayAssign/dut.sv, line:16:1, endln:79:10 |vpiPort: \_port: (debug_req_bits_op), line:23:17, endln:23:34 |vpiParent: - \_module: work@SimDTM (work@SimDTM), file:${SURELOG_DIR}/tests/DelayAssign/dut.sv, line:16:1, endln:79:10 + \_module_inst: work@SimDTM (work@SimDTM), file:${SURELOG_DIR}/tests/DelayAssign/dut.sv, line:16:1, endln:79:10 |vpiName:debug_req_bits_op |vpiDirection:2 |vpiLowConn: @@ -2868,11 +2868,11 @@ design: (work@SimDTM) |UINT:0 |vpiConstType:9 |vpiInstance: - \_module: work@SimDTM (work@SimDTM), file:${SURELOG_DIR}/tests/DelayAssign/dut.sv, line:16:1, endln:79:10 + \_module_inst: work@SimDTM (work@SimDTM), file:${SURELOG_DIR}/tests/DelayAssign/dut.sv, line:16:1, endln:79:10 |vpiPort: \_port: (debug_req_bits_data), line:24:17, endln:24:36 |vpiParent: - \_module: work@SimDTM (work@SimDTM), file:${SURELOG_DIR}/tests/DelayAssign/dut.sv, line:16:1, endln:79:10 + \_module_inst: work@SimDTM (work@SimDTM), file:${SURELOG_DIR}/tests/DelayAssign/dut.sv, line:16:1, endln:79:10 |vpiName:debug_req_bits_data |vpiDirection:2 |vpiLowConn: @@ -2906,11 +2906,11 @@ design: (work@SimDTM) |UINT:0 |vpiConstType:9 |vpiInstance: - \_module: work@SimDTM (work@SimDTM), file:${SURELOG_DIR}/tests/DelayAssign/dut.sv, line:16:1, endln:79:10 + \_module_inst: work@SimDTM (work@SimDTM), file:${SURELOG_DIR}/tests/DelayAssign/dut.sv, line:16:1, endln:79:10 |vpiPort: \_port: (debug_resp_valid), line:26:17, endln:26:33 |vpiParent: - \_module: work@SimDTM (work@SimDTM), file:${SURELOG_DIR}/tests/DelayAssign/dut.sv, line:16:1, endln:79:10 + \_module_inst: work@SimDTM (work@SimDTM), file:${SURELOG_DIR}/tests/DelayAssign/dut.sv, line:16:1, endln:79:10 |vpiName:debug_resp_valid |vpiDirection:1 |vpiLowConn: @@ -2924,11 +2924,11 @@ design: (work@SimDTM) |vpiTypedef: \_logic_typespec: , line:26:17, endln:26:17 |vpiInstance: - \_module: work@SimDTM (work@SimDTM), file:${SURELOG_DIR}/tests/DelayAssign/dut.sv, line:16:1, endln:79:10 + \_module_inst: work@SimDTM (work@SimDTM), file:${SURELOG_DIR}/tests/DelayAssign/dut.sv, line:16:1, endln:79:10 |vpiPort: \_port: (debug_resp_ready), line:27:17, endln:27:33 |vpiParent: - \_module: work@SimDTM (work@SimDTM), file:${SURELOG_DIR}/tests/DelayAssign/dut.sv, line:16:1, endln:79:10 + \_module_inst: work@SimDTM (work@SimDTM), file:${SURELOG_DIR}/tests/DelayAssign/dut.sv, line:16:1, endln:79:10 |vpiName:debug_resp_ready |vpiDirection:2 |vpiLowConn: @@ -2942,11 +2942,11 @@ design: (work@SimDTM) |vpiTypedef: \_logic_typespec: , line:27:17, endln:27:17 |vpiInstance: - \_module: work@SimDTM (work@SimDTM), file:${SURELOG_DIR}/tests/DelayAssign/dut.sv, line:16:1, endln:79:10 + \_module_inst: work@SimDTM (work@SimDTM), file:${SURELOG_DIR}/tests/DelayAssign/dut.sv, line:16:1, endln:79:10 |vpiPort: \_port: (debug_resp_bits_resp), line:28:17, endln:28:37 |vpiParent: - \_module: work@SimDTM (work@SimDTM), file:${SURELOG_DIR}/tests/DelayAssign/dut.sv, line:16:1, endln:79:10 + \_module_inst: work@SimDTM (work@SimDTM), file:${SURELOG_DIR}/tests/DelayAssign/dut.sv, line:16:1, endln:79:10 |vpiName:debug_resp_bits_resp |vpiDirection:1 |vpiLowConn: @@ -2980,11 +2980,11 @@ design: (work@SimDTM) |UINT:0 |vpiConstType:9 |vpiInstance: - \_module: work@SimDTM (work@SimDTM), file:${SURELOG_DIR}/tests/DelayAssign/dut.sv, line:16:1, endln:79:10 + \_module_inst: work@SimDTM (work@SimDTM), file:${SURELOG_DIR}/tests/DelayAssign/dut.sv, line:16:1, endln:79:10 |vpiPort: \_port: (debug_resp_bits_data), line:29:17, endln:29:37 |vpiParent: - \_module: work@SimDTM (work@SimDTM), file:${SURELOG_DIR}/tests/DelayAssign/dut.sv, line:16:1, endln:79:10 + \_module_inst: work@SimDTM (work@SimDTM), file:${SURELOG_DIR}/tests/DelayAssign/dut.sv, line:16:1, endln:79:10 |vpiName:debug_resp_bits_data |vpiDirection:1 |vpiLowConn: @@ -3018,11 +3018,11 @@ design: (work@SimDTM) |UINT:0 |vpiConstType:9 |vpiInstance: - \_module: work@SimDTM (work@SimDTM), file:${SURELOG_DIR}/tests/DelayAssign/dut.sv, line:16:1, endln:79:10 + \_module_inst: work@SimDTM (work@SimDTM), file:${SURELOG_DIR}/tests/DelayAssign/dut.sv, line:16:1, endln:79:10 |vpiPort: \_port: (exit), line:31:17, endln:31:21 |vpiParent: - \_module: work@SimDTM (work@SimDTM), file:${SURELOG_DIR}/tests/DelayAssign/dut.sv, line:16:1, endln:79:10 + \_module_inst: work@SimDTM (work@SimDTM), file:${SURELOG_DIR}/tests/DelayAssign/dut.sv, line:16:1, endln:79:10 |vpiName:exit |vpiDirection:2 |vpiLowConn: @@ -3056,11 +3056,11 @@ design: (work@SimDTM) |UINT:0 |vpiConstType:9 |vpiInstance: - \_module: work@SimDTM (work@SimDTM), file:${SURELOG_DIR}/tests/DelayAssign/dut.sv, line:16:1, endln:79:10 + \_module_inst: work@SimDTM (work@SimDTM), file:${SURELOG_DIR}/tests/DelayAssign/dut.sv, line:16:1, endln:79:10 |vpiProcess: \_always: , line:55:3, endln:78:6 |vpiParent: - \_module: work@SimDTM (work@SimDTM), file:${SURELOG_DIR}/tests/DelayAssign/dut.sv, line:16:1, endln:79:10 + \_module_inst: work@SimDTM (work@SimDTM), file:${SURELOG_DIR}/tests/DelayAssign/dut.sv, line:16:1, endln:79:10 |vpiStmt: \_event_control: , line:55:10, endln:55:24 |vpiParent: @@ -3282,7 +3282,7 @@ design: (work@SimDTM) |vpiContAssign: \_cont_assign: , line:36:13, endln:36:30 |vpiParent: - \_module: work@SimDTM (work@SimDTM), file:${SURELOG_DIR}/tests/DelayAssign/dut.sv, line:16:1, endln:79:10 + \_module_inst: work@SimDTM (work@SimDTM), file:${SURELOG_DIR}/tests/DelayAssign/dut.sv, line:16:1, endln:79:10 |vpiNetDeclAssign:1 |vpiDelay: \_constant: , line:36:8, endln:36:12 @@ -3303,7 +3303,7 @@ design: (work@SimDTM) |vpiContAssign: \_cont_assign: , line:37:13, endln:37:31 |vpiParent: - \_module: work@SimDTM (work@SimDTM), file:${SURELOG_DIR}/tests/DelayAssign/dut.sv, line:16:1, endln:79:10 + \_module_inst: work@SimDTM (work@SimDTM), file:${SURELOG_DIR}/tests/DelayAssign/dut.sv, line:16:1, endln:79:10 |vpiNetDeclAssign:1 |vpiDelay: \_constant: , line:37:8, endln:37:12 @@ -3324,7 +3324,7 @@ design: (work@SimDTM) |vpiContAssign: \_cont_assign: , line:38:20, endln:38:42 |vpiParent: - \_module: work@SimDTM (work@SimDTM), file:${SURELOG_DIR}/tests/DelayAssign/dut.sv, line:16:1, endln:79:10 + \_module_inst: work@SimDTM (work@SimDTM), file:${SURELOG_DIR}/tests/DelayAssign/dut.sv, line:16:1, endln:79:10 |vpiNetDeclAssign:1 |vpiDelay: \_constant: , line:38:15, endln:38:19 @@ -3360,7 +3360,7 @@ design: (work@SimDTM) |vpiContAssign: \_cont_assign: , line:39:20, endln:39:42 |vpiParent: - \_module: work@SimDTM (work@SimDTM), file:${SURELOG_DIR}/tests/DelayAssign/dut.sv, line:16:1, endln:79:10 + \_module_inst: work@SimDTM (work@SimDTM), file:${SURELOG_DIR}/tests/DelayAssign/dut.sv, line:16:1, endln:79:10 |vpiNetDeclAssign:1 |vpiDelay: \_constant: , line:39:15, endln:39:19 @@ -3381,7 +3381,7 @@ design: (work@SimDTM) |vpiContAssign: \_cont_assign: , line:48:15, endln:48:50 |vpiParent: - \_module: work@SimDTM (work@SimDTM), file:${SURELOG_DIR}/tests/DelayAssign/dut.sv, line:16:1, endln:79:10 + \_module_inst: work@SimDTM (work@SimDTM), file:${SURELOG_DIR}/tests/DelayAssign/dut.sv, line:16:1, endln:79:10 |vpiDelay: \_constant: , line:48:10, endln:48:14 |vpiRhs: @@ -3403,7 +3403,7 @@ design: (work@SimDTM) |vpiContAssign: \_cont_assign: , line:49:15, endln:49:63 |vpiParent: - \_module: work@SimDTM (work@SimDTM), file:${SURELOG_DIR}/tests/DelayAssign/dut.sv, line:16:1, endln:79:10 + \_module_inst: work@SimDTM (work@SimDTM), file:${SURELOG_DIR}/tests/DelayAssign/dut.sv, line:16:1, endln:79:10 |vpiDelay: \_constant: , line:49:10, endln:49:14 |vpiRhs: @@ -3433,7 +3433,7 @@ design: (work@SimDTM) |vpiContAssign: \_cont_assign: , line:50:15, endln:50:59 |vpiParent: - \_module: work@SimDTM (work@SimDTM), file:${SURELOG_DIR}/tests/DelayAssign/dut.sv, line:16:1, endln:79:10 + \_module_inst: work@SimDTM (work@SimDTM), file:${SURELOG_DIR}/tests/DelayAssign/dut.sv, line:16:1, endln:79:10 |vpiDelay: \_constant: , line:50:10, endln:50:14 |vpiRhs: @@ -3463,7 +3463,7 @@ design: (work@SimDTM) |vpiContAssign: \_cont_assign: , line:51:15, endln:51:64 |vpiParent: - \_module: work@SimDTM (work@SimDTM), file:${SURELOG_DIR}/tests/DelayAssign/dut.sv, line:16:1, endln:79:10 + \_module_inst: work@SimDTM (work@SimDTM), file:${SURELOG_DIR}/tests/DelayAssign/dut.sv, line:16:1, endln:79:10 |vpiDelay: \_constant: , line:51:10, endln:51:14 |vpiRhs: @@ -3493,7 +3493,7 @@ design: (work@SimDTM) |vpiContAssign: \_cont_assign: , line:52:15, endln:52:52 |vpiParent: - \_module: work@SimDTM (work@SimDTM), file:${SURELOG_DIR}/tests/DelayAssign/dut.sv, line:16:1, endln:79:10 + \_module_inst: work@SimDTM (work@SimDTM), file:${SURELOG_DIR}/tests/DelayAssign/dut.sv, line:16:1, endln:79:10 |vpiDelay: \_constant: , line:52:10, endln:52:14 |vpiRhs: @@ -3515,7 +3515,7 @@ design: (work@SimDTM) |vpiContAssign: \_cont_assign: , line:53:15, endln:53:28 |vpiParent: - \_module: work@SimDTM (work@SimDTM), file:${SURELOG_DIR}/tests/DelayAssign/dut.sv, line:16:1, endln:79:10 + \_module_inst: work@SimDTM (work@SimDTM), file:${SURELOG_DIR}/tests/DelayAssign/dut.sv, line:16:1, endln:79:10 |vpiDelay: \_constant: , line:53:10, endln:53:14 |vpiRhs: diff --git a/tests/Disable/Disable.log b/tests/Disable/Disable.log index 164bcb245c..15ed562e67 100644 --- a/tests/Disable/Disable.log +++ b/tests/Disable/Disable.log @@ -68,7 +68,7 @@ disable_fork 1 forever_stmt 1 initial 1 logic_net 1 -module 2 +module_inst 2 named_begin 1 ref_obj 1 === UHDM Object Stats End === @@ -82,7 +82,7 @@ disable_fork 2 forever_stmt 2 initial 2 logic_net 1 -module 2 +module_inst 2 named_begin 2 ref_obj 1 === UHDM Object Stats End === @@ -99,7 +99,7 @@ design: (work@top) |vpiElaborated:1 |vpiName:work@top |uhdmallModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/Disable/dut.sv, line:1:1, endln:8:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/Disable/dut.sv, line:1:1, endln:8:10 |vpiParent: \_design: (work@top) |vpiFullName:work@top @@ -107,7 +107,7 @@ design: (work@top) |vpiProcess: \_initial: , line:2:4, endln:7:7 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/Disable/dut.sv, line:1:1, endln:8:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/Disable/dut.sv, line:1:1, endln:8:10 |vpiStmt: \_begin: (work@top), line:2:12, endln:7:7 |vpiParent: @@ -134,7 +134,7 @@ design: (work@top) |vpiParent: \_named_begin: (work@top.loop), line:3:15, endln:6:10 |uhdmtopModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/Disable/dut.sv, line:1:1, endln:8:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/Disable/dut.sv, line:1:1, endln:8:10 |vpiName:work@top |vpiDefName:work@top |vpiTop:1 @@ -146,7 +146,7 @@ design: (work@top) |vpiProcess: \_initial: , line:2:4, endln:7:7 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/Disable/dut.sv, line:1:1, endln:8:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/Disable/dut.sv, line:1:1, endln:8:10 |vpiStmt: \_begin: (work@top), line:2:12, endln:7:7 |vpiParent: diff --git a/tests/DollarBits/DollarBits.log b/tests/DollarBits/DollarBits.log index 69fa822978..b2e19d5d72 100644 --- a/tests/DollarBits/DollarBits.log +++ b/tests/DollarBits/DollarBits.log @@ -209,7 +209,7 @@ design 1 int_typespec 2 logic_net 8 logic_typespec 13 -module 9 +module_inst 9 operation 8 param_assign 2 parameter 2 @@ -226,7 +226,7 @@ design 1 int_typespec 2 logic_net 8 logic_typespec 13 -module 9 +module_inst 9 operation 8 param_assign 2 parameter 2 @@ -247,7 +247,7 @@ design: (work@dut) |vpiElaborated:1 |vpiName:work@dut |uhdmallModules: -\_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/DollarBits/dut.sv, line:7:1, endln:9:10 +\_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/DollarBits/dut.sv, line:7:1, endln:9:10 |vpiParent: \_design: (work@dut) |vpiFullName:work@dut @@ -255,21 +255,21 @@ design: (work@dut) |vpiNet: \_logic_net: (work@dut.in), line:7:30, endln:7:32 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/DollarBits/dut.sv, line:7:1, endln:9:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/DollarBits/dut.sv, line:7:1, endln:9:10 |vpiName:in |vpiFullName:work@dut.in |vpiNetType:36 |vpiNet: \_logic_net: (work@dut.out), line:7:52, endln:7:55 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/DollarBits/dut.sv, line:7:1, endln:9:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/DollarBits/dut.sv, line:7:1, endln:9:10 |vpiName:out |vpiFullName:work@dut.out |vpiNetType:36 |vpiPort: \_port: (in), line:7:30, endln:7:32 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/DollarBits/dut.sv, line:7:1, endln:9:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/DollarBits/dut.sv, line:7:1, endln:9:10 |vpiName:in |vpiDirection:1 |vpiLowConn: @@ -299,7 +299,7 @@ design: (work@dut) |vpiPort: \_port: (out), line:7:52, endln:7:55 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/DollarBits/dut.sv, line:7:1, endln:9:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/DollarBits/dut.sv, line:7:1, endln:9:10 |vpiName:out |vpiDirection:2 |vpiLowConn: @@ -327,14 +327,14 @@ design: (work@dut) |UINT:0 |vpiConstType:9 |uhdmallModules: -\_module: work@other (work@other), file:${SURELOG_DIR}/tests/DollarBits/dut.sv, line:1:1, endln:5:10 +\_module_inst: work@other (work@other), file:${SURELOG_DIR}/tests/DollarBits/dut.sv, line:1:1, endln:5:10 |vpiParent: \_design: (work@dut) |vpiFullName:work@other |vpiParameter: \_parameter: (work@other.Width), line:2:19, endln:2:24 |vpiParent: - \_module: work@other (work@other), file:${SURELOG_DIR}/tests/DollarBits/dut.sv, line:1:1, endln:5:10 + \_module_inst: work@other (work@other), file:${SURELOG_DIR}/tests/DollarBits/dut.sv, line:1:1, endln:5:10 |UINT:1 |vpiTypespec: \_int_typespec: , line:2:15, endln:2:18 @@ -347,7 +347,7 @@ design: (work@dut) |vpiParamAssign: \_param_assign: , line:2:19, endln:2:28 |vpiParent: - \_module: work@other (work@other), file:${SURELOG_DIR}/tests/DollarBits/dut.sv, line:1:1, endln:5:10 + \_module_inst: work@other (work@other), file:${SURELOG_DIR}/tests/DollarBits/dut.sv, line:1:1, endln:5:10 |vpiRhs: \_constant: , line:2:27, endln:2:28 |vpiDecompile:1 @@ -362,21 +362,21 @@ design: (work@dut) |vpiNet: \_logic_net: (work@other.in), line:3:27, endln:3:29 |vpiParent: - \_module: work@other (work@other), file:${SURELOG_DIR}/tests/DollarBits/dut.sv, line:1:1, endln:5:10 + \_module_inst: work@other (work@other), file:${SURELOG_DIR}/tests/DollarBits/dut.sv, line:1:1, endln:5:10 |vpiName:in |vpiFullName:work@other.in |vpiNetType:36 |vpiNet: \_logic_net: (work@other.out), line:3:55, endln:3:58 |vpiParent: - \_module: work@other (work@other), file:${SURELOG_DIR}/tests/DollarBits/dut.sv, line:1:1, endln:5:10 + \_module_inst: work@other (work@other), file:${SURELOG_DIR}/tests/DollarBits/dut.sv, line:1:1, endln:5:10 |vpiName:out |vpiFullName:work@other.out |vpiNetType:36 |vpiPort: \_port: (in), line:3:27, endln:3:29 |vpiParent: - \_module: work@other (work@other), file:${SURELOG_DIR}/tests/DollarBits/dut.sv, line:1:1, endln:5:10 + \_module_inst: work@other (work@other), file:${SURELOG_DIR}/tests/DollarBits/dut.sv, line:1:1, endln:5:10 |vpiName:in |vpiDirection:1 |vpiLowConn: @@ -416,7 +416,7 @@ design: (work@dut) |vpiPort: \_port: (out), line:3:55, endln:3:58 |vpiParent: - \_module: work@other (work@other), file:${SURELOG_DIR}/tests/DollarBits/dut.sv, line:1:1, endln:5:10 + \_module_inst: work@other (work@other), file:${SURELOG_DIR}/tests/DollarBits/dut.sv, line:1:1, endln:5:10 |vpiName:out |vpiDirection:2 |vpiLowConn: @@ -456,7 +456,7 @@ design: (work@dut) |vpiContAssign: \_cont_assign: , line:4:11, endln:4:19 |vpiParent: - \_module: work@other (work@other), file:${SURELOG_DIR}/tests/DollarBits/dut.sv, line:1:1, endln:5:10 + \_module_inst: work@other (work@other), file:${SURELOG_DIR}/tests/DollarBits/dut.sv, line:1:1, endln:5:10 |vpiRhs: \_ref_obj: (work@other.in), line:4:17, endln:4:19 |vpiParent: @@ -474,14 +474,14 @@ design: (work@dut) |vpiActual: \_logic_net: (work@dut.oth.out), line:3:55, endln:3:58 |uhdmtopModules: -\_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/DollarBits/dut.sv, line:7:1, endln:9:10 +\_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/DollarBits/dut.sv, line:7:1, endln:9:10 |vpiName:work@dut |vpiDefName:work@dut |vpiTop:1 |vpiNet: \_logic_net: (work@dut.in), line:7:30, endln:7:32 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/DollarBits/dut.sv, line:7:1, endln:9:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/DollarBits/dut.sv, line:7:1, endln:9:10 |vpiTypespec: \_logic_typespec: , line:7:19, endln:7:29 |vpiRange: @@ -508,7 +508,7 @@ design: (work@dut) |vpiNet: \_logic_net: (work@dut.out), line:7:52, endln:7:55 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/DollarBits/dut.sv, line:7:1, endln:9:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/DollarBits/dut.sv, line:7:1, endln:9:10 |vpiTypespec: \_logic_typespec: , line:7:41, endln:7:51 |vpiRange: @@ -536,7 +536,7 @@ design: (work@dut) |vpiPort: \_port: (in), line:7:30, endln:7:32 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/DollarBits/dut.sv, line:7:1, endln:9:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/DollarBits/dut.sv, line:7:1, endln:9:10 |vpiName:in |vpiDirection:1 |vpiLowConn: @@ -570,11 +570,11 @@ design: (work@dut) |UINT:0 |vpiConstType:9 |vpiInstance: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/DollarBits/dut.sv, line:7:1, endln:9:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/DollarBits/dut.sv, line:7:1, endln:9:10 |vpiPort: \_port: (out), line:7:52, endln:7:55 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/DollarBits/dut.sv, line:7:1, endln:9:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/DollarBits/dut.sv, line:7:1, endln:9:10 |vpiName:out |vpiDirection:2 |vpiLowConn: @@ -608,17 +608,17 @@ design: (work@dut) |UINT:0 |vpiConstType:9 |vpiInstance: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/DollarBits/dut.sv, line:7:1, endln:9:10 - |vpiModule: - \_module: work@other (work@dut.oth), file:${SURELOG_DIR}/tests/DollarBits/dut.sv, line:8:4, endln:8:57 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/DollarBits/dut.sv, line:7:1, endln:9:10 + |vpiModuleInst: + \_module_inst: work@other (work@dut.oth), file:${SURELOG_DIR}/tests/DollarBits/dut.sv, line:8:4, endln:8:57 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/DollarBits/dut.sv, line:7:1, endln:9:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/DollarBits/dut.sv, line:7:1, endln:9:10 |vpiName:oth |vpiFullName:work@dut.oth |vpiParameter: \_parameter: (work@dut.oth.Width), line:2:19, endln:2:24 |vpiParent: - \_module: work@other (work@dut.oth), file:${SURELOG_DIR}/tests/DollarBits/dut.sv, line:8:4, endln:8:57 + \_module_inst: work@other (work@dut.oth), file:${SURELOG_DIR}/tests/DollarBits/dut.sv, line:8:4, endln:8:57 |UINT:1 |vpiTypespec: \_int_typespec: , line:2:15, endln:2:18 @@ -631,7 +631,7 @@ design: (work@dut) |vpiParamAssign: \_param_assign: , line:2:19, endln:2:28 |vpiParent: - \_module: work@other (work@dut.oth), file:${SURELOG_DIR}/tests/DollarBits/dut.sv, line:8:4, endln:8:57 + \_module_inst: work@other (work@dut.oth), file:${SURELOG_DIR}/tests/DollarBits/dut.sv, line:8:4, endln:8:57 |vpiOverriden:1 |vpiRhs: \_constant: , line:2:27, endln:2:28 @@ -649,7 +649,7 @@ design: (work@dut) |vpiNet: \_logic_net: (work@dut.oth.in), line:3:27, endln:3:29 |vpiParent: - \_module: work@other (work@dut.oth), file:${SURELOG_DIR}/tests/DollarBits/dut.sv, line:8:4, endln:8:57 + \_module_inst: work@other (work@dut.oth), file:${SURELOG_DIR}/tests/DollarBits/dut.sv, line:8:4, endln:8:57 |vpiTypespec: \_logic_typespec: , line:3:10, endln:3:26 |vpiRange: @@ -676,7 +676,7 @@ design: (work@dut) |vpiNet: \_logic_net: (work@dut.oth.out), line:3:55, endln:3:58 |vpiParent: - \_module: work@other (work@dut.oth), file:${SURELOG_DIR}/tests/DollarBits/dut.sv, line:8:4, endln:8:57 + \_module_inst: work@other (work@dut.oth), file:${SURELOG_DIR}/tests/DollarBits/dut.sv, line:8:4, endln:8:57 |vpiTypespec: \_logic_typespec: , line:3:38, endln:3:54 |vpiRange: @@ -701,11 +701,11 @@ design: (work@dut) |vpiFullName:work@dut.oth.out |vpiNetType:36 |vpiInstance: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/DollarBits/dut.sv, line:7:1, endln:9:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/DollarBits/dut.sv, line:7:1, endln:9:10 |vpiPort: \_port: (in), line:3:27, endln:3:29 |vpiParent: - \_module: work@other (work@dut.oth), file:${SURELOG_DIR}/tests/DollarBits/dut.sv, line:8:4, endln:8:57 + \_module_inst: work@other (work@dut.oth), file:${SURELOG_DIR}/tests/DollarBits/dut.sv, line:8:4, endln:8:57 |vpiName:in |vpiDirection:1 |vpiHighConn: @@ -747,11 +747,11 @@ design: (work@dut) |UINT:0 |vpiConstType:9 |vpiInstance: - \_module: work@other (work@dut.oth), file:${SURELOG_DIR}/tests/DollarBits/dut.sv, line:8:4, endln:8:57 + \_module_inst: work@other (work@dut.oth), file:${SURELOG_DIR}/tests/DollarBits/dut.sv, line:8:4, endln:8:57 |vpiPort: \_port: (out), line:3:55, endln:3:58 |vpiParent: - \_module: work@other (work@dut.oth), file:${SURELOG_DIR}/tests/DollarBits/dut.sv, line:8:4, endln:8:57 + \_module_inst: work@other (work@dut.oth), file:${SURELOG_DIR}/tests/DollarBits/dut.sv, line:8:4, endln:8:57 |vpiName:out |vpiDirection:2 |vpiHighConn: @@ -793,11 +793,11 @@ design: (work@dut) |UINT:0 |vpiConstType:9 |vpiInstance: - \_module: work@other (work@dut.oth), file:${SURELOG_DIR}/tests/DollarBits/dut.sv, line:8:4, endln:8:57 + \_module_inst: work@other (work@dut.oth), file:${SURELOG_DIR}/tests/DollarBits/dut.sv, line:8:4, endln:8:57 |vpiContAssign: \_cont_assign: , line:4:11, endln:4:19 |vpiParent: - \_module: work@other (work@dut.oth), file:${SURELOG_DIR}/tests/DollarBits/dut.sv, line:8:4, endln:8:57 + \_module_inst: work@other (work@dut.oth), file:${SURELOG_DIR}/tests/DollarBits/dut.sv, line:8:4, endln:8:57 |vpiRhs: \_ref_obj: (work@dut.oth.in), line:4:17, endln:4:19 |vpiParent: diff --git a/tests/DollarBitsUnary/DollarBitsUnary.log b/tests/DollarBitsUnary/DollarBitsUnary.log index 4f4d47355c..44f917955c 100644 --- a/tests/DollarBitsUnary/DollarBitsUnary.log +++ b/tests/DollarBitsUnary/DollarBitsUnary.log @@ -161,7 +161,7 @@ design 1 logic_net 3 logic_typespec 5 logic_var 1 -module 4 +module_inst 4 operation 4 part_select 1 port 2 @@ -180,7 +180,7 @@ design 1 logic_net 3 logic_typespec 5 logic_var 1 -module 4 +module_inst 4 operation 6 part_select 2 port 3 @@ -203,17 +203,17 @@ design: (work@top) |vpiElaborated:1 |vpiName:work@top |uhdmallModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/DollarBitsUnary/dut.sv, line:1:1, endln:9:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/DollarBitsUnary/dut.sv, line:1:1, endln:9:10 |vpiParent: \_design: (work@top) |vpiFullName:work@top |vpiTypedef: \_struct_typespec: (dmi_t), line:2:12, endln:2:18 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/DollarBitsUnary/dut.sv, line:1:1, endln:9:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/DollarBitsUnary/dut.sv, line:1:1, endln:9:10 |vpiName:dmi_t |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/DollarBitsUnary/dut.sv, line:1:1, endln:9:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/DollarBitsUnary/dut.sv, line:1:1, endln:9:10 |vpiPacked:1 |vpiTypespecMember: \_typespec_member: (data), line:3:20, endln:3:24 @@ -253,21 +253,21 @@ design: (work@top) |vpiNet: \_logic_net: (work@top.o), line:1:32, endln:1:33 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/DollarBitsUnary/dut.sv, line:1:1, endln:9:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/DollarBitsUnary/dut.sv, line:1:1, endln:9:10 |vpiName:o |vpiFullName:work@top.o |vpiNetType:36 |vpiNet: \_logic_net: (work@top.dr_q), line:6:28, endln:6:32 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/DollarBitsUnary/dut.sv, line:1:1, endln:9:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/DollarBitsUnary/dut.sv, line:1:1, endln:9:10 |vpiName:dr_q |vpiFullName:work@top.dr_q |vpiNetType:36 |vpiPort: \_port: (o), line:1:32, endln:1:33 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/DollarBitsUnary/dut.sv, line:1:1, endln:9:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/DollarBitsUnary/dut.sv, line:1:1, endln:9:10 |vpiName:o |vpiDirection:2 |vpiLowConn: @@ -297,7 +297,7 @@ design: (work@top) |vpiContAssign: \_cont_assign: , line:8:11, endln:8:37 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/DollarBitsUnary/dut.sv, line:1:1, endln:9:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/DollarBitsUnary/dut.sv, line:1:1, endln:9:10 |vpiRhs: \_part_select: , line:8:15, endln:8:37 |vpiParent: @@ -351,12 +351,12 @@ design: (work@top) |vpiActual: \_logic_net: (work@top.o), line:1:32, endln:1:33 |uhdmtopModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/DollarBitsUnary/dut.sv, line:1:1, endln:9:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/DollarBitsUnary/dut.sv, line:1:1, endln:9:10 |vpiName:work@top |vpiVariables: \_logic_var: (work@top.dr_q), line:6:28, endln:6:32 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/DollarBitsUnary/dut.sv, line:1:1, endln:9:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/DollarBitsUnary/dut.sv, line:1:1, endln:9:10 |vpiTypespec: \_logic_typespec: , line:6:3, endln:6:27 |vpiRange: @@ -405,7 +405,7 @@ design: (work@top) |vpiNet: \_logic_net: (work@top.o), line:1:32, endln:1:33 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/DollarBitsUnary/dut.sv, line:1:1, endln:9:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/DollarBitsUnary/dut.sv, line:1:1, endln:9:10 |vpiTypespec: \_logic_typespec: , line:1:19, endln:1:31 |vpiRange: @@ -433,7 +433,7 @@ design: (work@top) |vpiPort: \_port: (o), line:1:32, endln:1:33 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/DollarBitsUnary/dut.sv, line:1:1, endln:9:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/DollarBitsUnary/dut.sv, line:1:1, endln:9:10 |vpiName:o |vpiDirection:2 |vpiLowConn: @@ -467,11 +467,11 @@ design: (work@top) |UINT:0 |vpiConstType:9 |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/DollarBitsUnary/dut.sv, line:1:1, endln:9:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/DollarBitsUnary/dut.sv, line:1:1, endln:9:10 |vpiContAssign: \_cont_assign: , line:8:11, endln:8:37 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/DollarBitsUnary/dut.sv, line:1:1, endln:9:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/DollarBitsUnary/dut.sv, line:1:1, endln:9:10 |vpiRhs: \_part_select: , line:8:15, endln:8:37 |vpiParent: diff --git a/tests/DollarRoot/DollarRoot.log b/tests/DollarRoot/DollarRoot.log index 23ead11daf..88d2e08dcd 100644 --- a/tests/DollarRoot/DollarRoot.log +++ b/tests/DollarRoot/DollarRoot.log @@ -6786,7 +6786,7 @@ logic_net 18 logic_typespec 25 logic_var 9 method_func_call 13 -module 10 +module_inst 10 named_event 1 operation 113 package 2 @@ -6851,7 +6851,7 @@ logic_net 18 logic_typespec 25 logic_var 19 method_func_call 26 -module 10 +module_inst 10 named_event 1 operation 195 package 2 @@ -7411,14 +7411,14 @@ design: (work@top) \_int_typespec: |vpiSigned:1 |uhdmallModules: -\_module: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 +\_module_inst: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 |vpiParent: \_design: (work@top) |vpiFullName:work@test_program |vpiParameter: \_parameter: (work@test_program.ADDR_W), line:13:15, endln:13:21 |vpiParent: - \_module: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 + \_module_inst: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 |UINT:13 |vpiTypespec: \_int_typespec: @@ -7428,7 +7428,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@test_program.SYMBOL_W), line:15:15, endln:15:23 |vpiParent: - \_module: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 + \_module_inst: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 |UINT:8 |vpiTypespec: \_int_typespec: @@ -7438,7 +7438,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@test_program.NUM_SYMBOLS), line:16:15, endln:16:26 |vpiParent: - \_module: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 + \_module_inst: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 |UINT:4 |vpiTypespec: \_int_typespec: @@ -7448,14 +7448,14 @@ design: (work@top) |vpiParameter: \_parameter: (work@test_program.DATA_W), line:17:15, endln:17:21 |vpiParent: - \_module: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 + \_module_inst: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 |vpiLocalParam:1 |vpiName:DATA_W |vpiFullName:work@test_program.DATA_W |vpiParameter: \_parameter: (work@test_program.BURST_W), line:19:15, endln:19:22 |vpiParent: - \_module: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 + \_module_inst: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 |UINT:4 |vpiTypespec: \_int_typespec: @@ -7465,7 +7465,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@test_program.MAX_BURST), line:20:15, endln:20:24 |vpiParent: - \_module: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 + \_module_inst: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 |UINT:8 |vpiTypespec: \_int_typespec: @@ -7475,7 +7475,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@test_program.SLAVE_SPAN), line:22:15, endln:22:25 |vpiParent: - \_module: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 + \_module_inst: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 |HEX:1000 |vpiTypespec: \_int_typespec: @@ -7493,7 +7493,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@test_program.MAX_COMMAND_IDLE), line:24:15, endln:24:31 |vpiParent: - \_module: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 + \_module_inst: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 |UINT:5 |vpiTypespec: \_int_typespec: @@ -7503,7 +7503,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@test_program.MAX_COMMAND_BACKPRESSURE), line:25:15, endln:25:39 |vpiParent: - \_module: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 + \_module_inst: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 |UINT:2 |vpiTypespec: \_int_typespec: @@ -7513,7 +7513,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@test_program.MAX_DATA_IDLE), line:26:15, endln:26:28 |vpiParent: - \_module: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 + \_module_inst: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 |UINT:3 |vpiTypespec: \_int_typespec: @@ -7523,7 +7523,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:13:15, endln:13:44 |vpiParent: - \_module: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 + \_module_inst: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 |vpiRhs: \_constant: , line:13:42, endln:13:44 |vpiDecompile:13 @@ -7537,7 +7537,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:15:15, endln:15:43 |vpiParent: - \_module: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 + \_module_inst: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 |vpiRhs: \_constant: , line:15:42, endln:15:43 |vpiDecompile:8 @@ -7551,7 +7551,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:16:15, endln:16:43 |vpiParent: - \_module: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 + \_module_inst: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 |vpiRhs: \_constant: , line:16:42, endln:16:43 |vpiDecompile:4 @@ -7565,7 +7565,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:17:15, endln:17:64 |vpiParent: - \_module: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 + \_module_inst: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 |vpiRhs: \_operation: , line:17:42, endln:17:64 |vpiOpType:25 @@ -7584,7 +7584,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:19:15, endln:19:43 |vpiParent: - \_module: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 + \_module_inst: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 |vpiRhs: \_constant: , line:19:42, endln:19:43 |vpiDecompile:4 @@ -7598,7 +7598,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:20:15, endln:20:43 |vpiParent: - \_module: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 + \_module_inst: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 |vpiRhs: \_constant: , line:20:42, endln:20:43 |vpiDecompile:8 @@ -7612,7 +7612,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:22:15, endln:22:50 |vpiParent: - \_module: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 + \_module_inst: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 |vpiRhs: \_constant: , line:22:42, endln:22:50 |vpiDecompile:32'h1000 @@ -7626,7 +7626,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:24:15, endln:24:43 |vpiParent: - \_module: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 + \_module_inst: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 |vpiRhs: \_constant: , line:24:42, endln:24:43 |vpiDecompile:5 @@ -7640,7 +7640,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:25:15, endln:25:43 |vpiParent: - \_module: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 + \_module_inst: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 |vpiRhs: \_constant: , line:25:42, endln:25:43 |vpiDecompile:2 @@ -7654,7 +7654,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:26:15, endln:26:43 |vpiParent: - \_module: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 + \_module_inst: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 |vpiRhs: \_constant: , line:26:42, endln:26:43 |vpiDecompile:3 @@ -7668,10 +7668,10 @@ design: (work@top) |vpiTypedef: \_logic_typespec: (Burstcount), line:31:12, endln:31:31 |vpiParent: - \_module: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 + \_module_inst: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 |vpiName:Burstcount |vpiInstance: - \_module: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 + \_module_inst: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 |vpiRange: \_range: , line:31:18, endln:31:31 |vpiLeftRange: @@ -7705,10 +7705,10 @@ design: (work@top) |vpiTypedef: \_enum_typespec: (Burstmode), line:39:4, endln:43:16 |vpiParent: - \_module: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 + \_module_inst: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 |vpiName:Burstmode |vpiInstance: - \_module: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 + \_module_inst: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 |vpiBaseTypespec: \_bit_typespec: , line:39:17, endln:39:20 |vpiSigned:1 @@ -7727,10 +7727,10 @@ design: (work@top) |vpiTypedef: \_struct_typespec: (Command), line:45:12, endln:45:18 |vpiParent: - \_module: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 + \_module_inst: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 |vpiName:Command |vpiInstance: - \_module: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 + \_module_inst: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 |vpiTypespecMember: \_typespec_member: (trans), line:47:37, endln:47:42 |vpiParent: @@ -7739,10 +7739,10 @@ design: (work@top) |vpiTypespec: \_enum_typespec: (Transaction), line:33:4, endln:37:18 |vpiParent: - \_module: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 + \_module_inst: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 |vpiName:Transaction |vpiInstance: - \_module: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 + \_module_inst: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 |vpiBaseTypespec: \_bit_typespec: , line:33:17, endln:33:20 |vpiSigned:1 @@ -8027,10 +8027,10 @@ design: (work@top) |vpiTypedef: \_struct_typespec: (Response), line:56:12, endln:56:18 |vpiParent: - \_module: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 + \_module_inst: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 |vpiName:Response |vpiInstance: - \_module: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 + \_module_inst: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 |vpiTypespecMember: \_typespec_member: (burstcount), line:58:37, endln:58:47 |vpiParent: @@ -8173,13 +8173,13 @@ design: (work@top) |vpiTaskFunc: \_task: (work@test_program.configure_and_push_command_to_master_0), line:224:4, endln:245:11 |vpiParent: - \_module: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 + \_module_inst: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 |vpiName:configure_and_push_command_to_master_0 |vpiFullName:work@test_program.configure_and_push_command_to_master_0 |vpiVisibility:1 |vpiAutomatic:1 |vpiParent: - \_module: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 + \_module_inst: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 |vpiIODecl: \_io_decl: (cmd), line:225:16, endln:225:19 |vpiDirection:1 @@ -8584,11 +8584,11 @@ design: (work@top) \_begin: (work@test_program.configure_and_push_command_to_master_0) |vpiName:$root.tb.dut.master_0.push_command |vpiInstance: - \_module: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 + \_module_inst: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 |vpiTaskFunc: \_function: (work@test_program.get_read_response_from_master_0), line:266:4, endln:277:15 |vpiParent: - \_module: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 + \_module_inst: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 |vpiName:get_read_response_from_master_0 |vpiFullName:work@test_program.get_read_response_from_master_0 |vpiVariables: @@ -8606,7 +8606,7 @@ design: (work@top) |vpiTypespec: \_struct_typespec: (Response), line:56:12, endln:56:18 |vpiParent: - \_module: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 + \_module_inst: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 |vpiStmt: \_begin: (work@test_program.get_read_response_from_master_0) |vpiParent: @@ -8804,11 +8804,11 @@ design: (work@top) |vpiActual: \_struct_var: (work@test_program.get_read_response_from_master_0.rsp), line:268:16, endln:268:19 |vpiInstance: - \_module: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 + \_module_inst: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 |vpiTaskFunc: \_function: (work@test_program.get_command_from_slave_0), line:309:4, endln:328:15 |vpiParent: - \_module: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 + \_module_inst: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 |vpiName:get_command_from_slave_0 |vpiFullName:work@test_program.get_command_from_slave_0 |vpiVariables: @@ -8826,7 +8826,7 @@ design: (work@top) |vpiTypespec: \_struct_typespec: (Command), line:45:12, endln:45:18 |vpiParent: - \_module: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 + \_module_inst: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 |vpiStmt: \_begin: (work@test_program.get_command_from_slave_0) |vpiParent: @@ -9229,11 +9229,11 @@ design: (work@top) |vpiActual: \_struct_var: (work@test_program.get_command_from_slave_0.cmd), line:311:15, endln:311:18 |vpiInstance: - \_module: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 + \_module_inst: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 |vpiTaskFunc: \_task: (work@test_program.configure_and_push_response_to_slave_0), line:340:1, endln:362:11 |vpiParent: - \_module: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 + \_module_inst: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 |vpiName:configure_and_push_response_to_slave_0 |vpiFullName:work@test_program.configure_and_push_response_to_slave_0 |vpiVariables: @@ -9249,7 +9249,7 @@ design: (work@top) |vpiVisibility:1 |vpiAutomatic:1 |vpiParent: - \_module: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 + \_module_inst: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 |vpiIODecl: \_io_decl: (rsp), line:341:16, endln:341:19 |vpiDirection:1 @@ -9716,17 +9716,17 @@ design: (work@top) |vpiActual: \_int_var: (work@test_program.pending_read_cycles_slave_0), line:332:8, endln:332:39 |vpiInstance: - \_module: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 + \_module_inst: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 |vpiTaskFunc: \_task: (work@test_program.configure_and_push_command_to_master_1), line:367:4, endln:388:11 |vpiParent: - \_module: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 + \_module_inst: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 |vpiName:configure_and_push_command_to_master_1 |vpiFullName:work@test_program.configure_and_push_command_to_master_1 |vpiVisibility:1 |vpiAutomatic:1 |vpiParent: - \_module: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 + \_module_inst: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 |vpiIODecl: \_io_decl: (cmd), line:368:16, endln:368:19 |vpiDirection:1 @@ -10131,11 +10131,11 @@ design: (work@top) \_begin: (work@test_program.configure_and_push_command_to_master_1) |vpiName:$root.tb.dut.master_1.push_command |vpiInstance: - \_module: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 + \_module_inst: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 |vpiTaskFunc: \_function: (work@test_program.get_read_response_from_master_1), line:409:4, endln:420:15 |vpiParent: - \_module: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 + \_module_inst: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 |vpiName:get_read_response_from_master_1 |vpiFullName:work@test_program.get_read_response_from_master_1 |vpiVariables: @@ -10153,7 +10153,7 @@ design: (work@top) |vpiTypespec: \_struct_typespec: (Response), line:56:12, endln:56:18 |vpiParent: - \_module: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 + \_module_inst: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 |vpiStmt: \_begin: (work@test_program.get_read_response_from_master_1) |vpiParent: @@ -10351,11 +10351,11 @@ design: (work@top) |vpiActual: \_struct_var: (work@test_program.get_read_response_from_master_1.rsp), line:411:16, endln:411:19 |vpiInstance: - \_module: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 + \_module_inst: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 |vpiTaskFunc: \_function: (work@test_program.get_command_from_slave_1), line:452:4, endln:471:15 |vpiParent: - \_module: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 + \_module_inst: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 |vpiName:get_command_from_slave_1 |vpiFullName:work@test_program.get_command_from_slave_1 |vpiVariables: @@ -10373,7 +10373,7 @@ design: (work@top) |vpiTypespec: \_struct_typespec: (Command), line:45:12, endln:45:18 |vpiParent: - \_module: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 + \_module_inst: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 |vpiStmt: \_begin: (work@test_program.get_command_from_slave_1) |vpiParent: @@ -10776,11 +10776,11 @@ design: (work@top) |vpiActual: \_struct_var: (work@test_program.get_command_from_slave_1.cmd), line:454:15, endln:454:18 |vpiInstance: - \_module: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 + \_module_inst: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 |vpiTaskFunc: \_task: (work@test_program.configure_and_push_response_to_slave_1), line:483:1, endln:505:11 |vpiParent: - \_module: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 + \_module_inst: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 |vpiName:configure_and_push_response_to_slave_1 |vpiFullName:work@test_program.configure_and_push_response_to_slave_1 |vpiVariables: @@ -10796,7 +10796,7 @@ design: (work@top) |vpiVisibility:1 |vpiAutomatic:1 |vpiParent: - \_module: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 + \_module_inst: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 |vpiIODecl: \_io_decl: (rsp), line:484:16, endln:484:19 |vpiDirection:1 @@ -11263,11 +11263,11 @@ design: (work@top) |vpiActual: \_int_var: (work@test_program.pending_read_cycles_slave_1), line:475:8, endln:475:39 |vpiInstance: - \_module: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 + \_module_inst: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 |vpiTaskFunc: \_task: (work@test_program.master_send_commands), line:544:4, endln:568:11 |vpiParent: - \_module: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 + \_module_inst: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 |vpiName:master_send_commands |vpiFullName:work@test_program.master_send_commands |vpiVariables: @@ -11317,7 +11317,7 @@ design: (work@top) |vpiVisibility:1 |vpiAutomatic:1 |vpiParent: - \_module: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 + \_module_inst: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 |vpiIODecl: \_io_decl: (num_command), line:545:22, endln:545:33 |vpiDirection:1 @@ -11591,11 +11591,11 @@ design: (work@top) |vpiTask: \_task: (work@test_program.queue_command), line:620:4, endln:629:11 |vpiInstance: - \_module: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 + \_module_inst: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 |vpiTaskFunc: \_function: (work@test_program.create_command), line:570:4, endln:599:15 |vpiParent: - \_module: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 + \_module_inst: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 |vpiName:create_command |vpiFullName:work@test_program.create_command |vpiVariables: @@ -11613,7 +11613,7 @@ design: (work@top) |vpiTypespec: \_struct_typespec: (Command), line:45:12, endln:45:18 |vpiParent: - \_module: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 + \_module_inst: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 |vpiIODecl: \_io_decl: (trans), line:571:22, endln:571:27 |vpiDirection:1 @@ -12169,11 +12169,11 @@ design: (work@top) |vpiActual: \_struct_var: (work@test_program.create_command.cmd), line:576:15, endln:576:18 |vpiInstance: - \_module: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 + \_module_inst: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 |vpiTaskFunc: \_function: (work@test_program.randomize_burstcount), line:601:4, endln:607:15 |vpiParent: - \_module: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 + \_module_inst: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 |vpiName:randomize_burstcount |vpiFullName:work@test_program.randomize_burstcount |vpiVariables: @@ -12263,7 +12263,7 @@ design: (work@top) |UINT:0 |vpiConstType:9 |vpiParent: - \_module: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 + \_module_inst: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 |vpiStmt: \_begin: (work@test_program.randomize_burstcount) |vpiParent: @@ -12317,11 +12317,11 @@ design: (work@top) |vpiActual: \_logic_var: (work@test_program.randomize_burstcount.burstcount), line:603:18, endln:603:28 |vpiInstance: - \_module: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 + \_module_inst: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 |vpiTaskFunc: \_function: (work@test_program.generate_random_aligned_address), line:609:4, endln:618:15 |vpiParent: - \_module: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 + \_module_inst: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 |vpiName:generate_random_aligned_address |vpiFullName:work@test_program.generate_random_aligned_address |vpiVariables: @@ -12443,7 +12443,7 @@ design: (work@top) |UINT:0 |vpiConstType:9 |vpiParent: - \_module: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 + \_module_inst: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 |vpiIODecl: \_io_decl: (slave_id), line:610:11, endln:610:19 |vpiDirection:1 @@ -12571,17 +12571,17 @@ design: (work@top) |vpiName:NUM_SYMBOLS |vpiFullName:work@test_program.generate_random_aligned_address.NUM_SYMBOLS |vpiInstance: - \_module: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 + \_module_inst: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 |vpiTaskFunc: \_task: (work@test_program.queue_command), line:620:4, endln:629:11 |vpiParent: - \_module: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 + \_module_inst: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 |vpiName:queue_command |vpiFullName:work@test_program.queue_command |vpiVisibility:1 |vpiAutomatic:1 |vpiParent: - \_module: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 + \_module_inst: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 |vpiIODecl: \_io_decl: (cmd), line:621:16, endln:621:19 |vpiDirection:1 @@ -12677,17 +12677,17 @@ design: (work@top) |vpiTask: \_task: (work@test_program.configure_and_push_command_to_master), line:670:4, endln:680:11 |vpiInstance: - \_module: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 + \_module_inst: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 |vpiTaskFunc: \_task: (work@test_program.save_command_master), line:631:4, endln:642:11 |vpiParent: - \_module: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 + \_module_inst: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 |vpiName:save_command_master |vpiFullName:work@test_program.save_command_master |vpiVisibility:1 |vpiAutomatic:1 |vpiParent: - \_module: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 + \_module_inst: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 |vpiIODecl: \_io_decl: (cmd), line:632:16, endln:632:19 |vpiDirection:1 @@ -12776,17 +12776,17 @@ design: (work@top) \_ref_obj: (read_command_queue_master), line:639:13, endln:639:38 |vpiName:read_command_queue_master |vpiInstance: - \_module: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 + \_module_inst: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 |vpiTaskFunc: \_task: (work@test_program.save_command_slave), line:644:4, endln:656:11 |vpiParent: - \_module: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 + \_module_inst: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 |vpiName:save_command_slave |vpiFullName:work@test_program.save_command_slave |vpiVisibility:1 |vpiAutomatic:1 |vpiParent: - \_module: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 + \_module_inst: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 |vpiIODecl: \_io_decl: (cmd), line:645:16, endln:645:19 |vpiDirection:1 @@ -12923,11 +12923,11 @@ design: (work@top) \_ref_obj: (read_command_queue_slave), line:653:10, endln:653:34 |vpiName:read_command_queue_slave |vpiInstance: - \_module: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 + \_module_inst: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 |vpiTaskFunc: \_function: (work@test_program.translate_master_to_slave_address), line:658:4, endln:668:15 |vpiParent: - \_module: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 + \_module_inst: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 |vpiName:translate_master_to_slave_address |vpiFullName:work@test_program.translate_master_to_slave_address |vpiVariables: @@ -13059,7 +13059,7 @@ design: (work@top) |UINT:0 |vpiConstType:9 |vpiParent: - \_module: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 + \_module_inst: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 |vpiIODecl: \_io_decl: (addr), line:659:28, endln:659:32 |vpiDirection:1 @@ -13224,17 +13224,17 @@ design: (work@top) |vpiName:NUM_SYMBOLS |vpiFullName:work@test_program.translate_master_to_slave_address.NUM_SYMBOLS |vpiInstance: - \_module: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 + \_module_inst: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 |vpiTaskFunc: \_task: (work@test_program.configure_and_push_command_to_master), line:670:4, endln:680:11 |vpiParent: - \_module: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 + \_module_inst: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 |vpiName:configure_and_push_command_to_master |vpiFullName:work@test_program.configure_and_push_command_to_master |vpiVisibility:1 |vpiAutomatic:1 |vpiParent: - \_module: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 + \_module_inst: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 |vpiIODecl: \_io_decl: (cmd), line:671:16, endln:671:19 |vpiDirection:1 @@ -13339,11 +13339,11 @@ design: (work@top) |vpiTask: \_task: (work@test_program.configure_and_push_command_to_master_1), line:367:4, endln:388:11 |vpiInstance: - \_module: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 + \_module_inst: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 |vpiTaskFunc: \_function: (work@test_program.get_expected_command_for_slave), line:682:4, endln:717:15 |vpiParent: - \_module: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 + \_module_inst: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 |vpiName:get_expected_command_for_slave |vpiFullName:work@test_program.get_expected_command_for_slave |vpiVariables: @@ -13371,7 +13371,7 @@ design: (work@top) |vpiTypespec: \_struct_typespec: (Command), line:45:12, endln:45:18 |vpiParent: - \_module: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 + \_module_inst: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 |vpiIODecl: \_io_decl: (cmd), line:683:15, endln:683:18 |vpiDirection:1 @@ -13969,17 +13969,17 @@ design: (work@top) |vpiActual: \_struct_var: (work@test_program.get_expected_command_for_slave.exp_cmd), line:687:15, endln:687:22 |vpiInstance: - \_module: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 + \_module_inst: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 |vpiTaskFunc: \_task: (work@test_program.verify_command), line:719:4, endln:733:11 |vpiParent: - \_module: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 + \_module_inst: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 |vpiName:verify_command |vpiFullName:work@test_program.verify_command |vpiVisibility:1 |vpiAutomatic:1 |vpiParent: - \_module: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 + \_module_inst: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 |vpiIODecl: \_io_decl: (actual_cmd), line:720:15, endln:720:25 |vpiDirection:1 @@ -14344,11 +14344,11 @@ design: (work@top) |vpiTask: \_task: (work@test_program.assert_equals), line:735:4, endln:757:11 |vpiInstance: - \_module: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 + \_module_inst: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 |vpiTaskFunc: \_task: (work@test_program.assert_equals), line:735:4, endln:757:11 |vpiParent: - \_module: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 + \_module_inst: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 |vpiName:assert_equals |vpiFullName:work@test_program.assert_equals |vpiVariables: @@ -14362,7 +14362,7 @@ design: (work@top) |vpiVisibility:1 |vpiAutomatic:1 |vpiParent: - \_module: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 + \_module_inst: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 |vpiIODecl: \_io_decl: (message), line:736:14, endln:736:21 |vpiDirection:1 @@ -14559,11 +14559,11 @@ design: (work@top) |vpiName:assert_fail |vpiBlocking:1 |vpiInstance: - \_module: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 + \_module_inst: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 |vpiTaskFunc: \_function: (work@test_program.create_response), line:759:4, endln:772:15 |vpiParent: - \_module: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 + \_module_inst: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 |vpiName:create_response |vpiFullName:work@test_program.create_response |vpiVariables: @@ -14581,7 +14581,7 @@ design: (work@top) |vpiTypespec: \_struct_typespec: (Response), line:56:12, endln:56:18 |vpiParent: - \_module: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 + \_module_inst: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 |vpiIODecl: \_io_decl: (burstcount), line:760:18, endln:760:28 |vpiDirection:1 @@ -14837,11 +14837,11 @@ design: (work@top) |vpiActual: \_struct_var: (work@test_program.create_response.rsp), line:763:16, endln:763:19 |vpiInstance: - \_module: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 + \_module_inst: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 |vpiTaskFunc: \_function: (work@test_program.get_expected_read_response), line:774:4, endln:784:15 |vpiParent: - \_module: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 + \_module_inst: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 |vpiName:get_expected_read_response |vpiFullName:work@test_program.get_expected_read_response |vpiVariables: @@ -14869,7 +14869,7 @@ design: (work@top) |vpiTypespec: \_struct_typespec: (Response), line:56:12, endln:56:18 |vpiParent: - \_module: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 + \_module_inst: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 |vpiIODecl: \_io_decl: (cmd), line:775:15, endln:775:18 |vpiDirection:1 @@ -14969,17 +14969,17 @@ design: (work@top) |vpiActual: \_struct_var: (work@test_program.get_expected_read_response.rsp), line:778:16, endln:778:19 |vpiInstance: - \_module: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 + \_module_inst: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 |vpiTaskFunc: \_task: (work@test_program.verify_response), line:786:4, endln:795:11 |vpiParent: - \_module: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 + \_module_inst: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 |vpiName:verify_response |vpiFullName:work@test_program.verify_response |vpiVisibility:1 |vpiAutomatic:1 |vpiParent: - \_module: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 + \_module_inst: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 |vpiIODecl: \_io_decl: (actual_rsp), line:787:16, endln:787:26 |vpiDirection:1 @@ -15189,65 +15189,65 @@ design: (work@top) |vpiTask: \_task: (work@test_program.assert_equals), line:735:4, endln:757:11 |vpiInstance: - \_module: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 + \_module_inst: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 |vpiNet: \_logic_net: (work@test_program.write_command_queue_master), line:67:10, endln:67:36 |vpiParent: - \_module: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 + \_module_inst: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 |vpiName:write_command_queue_master |vpiFullName:work@test_program.write_command_queue_master |vpiNet: \_logic_net: (work@test_program.read_command_queue_master), line:68:10, endln:68:35 |vpiParent: - \_module: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 + \_module_inst: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 |vpiName:read_command_queue_master |vpiFullName:work@test_program.read_command_queue_master |vpiNet: \_logic_net: (work@test_program.write_command_queue_slave), line:71:10, endln:71:35 |vpiParent: - \_module: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 + \_module_inst: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 |vpiName:write_command_queue_slave |vpiFullName:work@test_program.write_command_queue_slave |vpiNet: \_logic_net: (work@test_program.read_command_queue_slave), line:72:10, endln:72:34 |vpiParent: - \_module: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 + \_module_inst: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 |vpiName:read_command_queue_slave |vpiFullName:work@test_program.read_command_queue_slave |vpiNet: \_logic_net: (work@test_program.read_response_queue_slave), line:75:10, endln:75:35 |vpiParent: - \_module: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 + \_module_inst: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 |vpiName:read_response_queue_slave |vpiFullName:work@test_program.read_response_queue_slave |vpiNet: \_logic_net: (work@test_program.pending_read_cycles_slave_0), line:332:8, endln:332:35 |vpiParent: - \_module: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 + \_module_inst: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 |vpiName:pending_read_cycles_slave_0 |vpiFullName:work@test_program.pending_read_cycles_slave_0 |vpiNet: \_logic_net: (work@test_program.pending_read_cycles_slave_1), line:475:8, endln:475:35 |vpiParent: - \_module: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 + \_module_inst: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 |vpiName:pending_read_cycles_slave_1 |vpiFullName:work@test_program.pending_read_cycles_slave_1 |vpiNet: \_logic_net: (work@test_program.test_success), line:511:5, endln:511:17 |vpiParent: - \_module: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 + \_module_inst: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 |vpiName:test_success |vpiFullName:work@test_program.test_success |vpiNet: \_logic_net: (work@test_program.assert_fail), line:517:7, endln:517:18 |vpiParent: - \_module: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 + \_module_inst: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 |vpiName:assert_fail |vpiFullName:work@test_program.assert_fail |vpiProcess: \_always: , line:249:4, endln:258:7 |vpiParent: - \_module: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 + \_module_inst: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 |vpiStmt: \_event_control: , line:249:11, endln:249:65 |vpiParent: @@ -15416,7 +15416,7 @@ design: (work@top) |vpiProcess: \_always: , line:261:4, endln:263:7 |vpiParent: - \_module: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 + \_module_inst: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 |vpiStmt: \_event_control: , line:261:11, endln:261:66 |vpiParent: @@ -15456,7 +15456,7 @@ design: (work@top) |vpiProcess: \_always: , line:282:4, endln:305:7 |vpiParent: - \_module: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 + \_module_inst: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 |vpiStmt: \_event_control: , line:282:11, endln:282:58 |vpiParent: @@ -15829,7 +15829,7 @@ design: (work@top) |vpiProcess: \_always: , line:333:4, endln:337:7 |vpiParent: - \_module: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 + \_module_inst: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 |vpiStmt: \_event_control: , line:333:11, endln:333:42 |vpiParent: @@ -15906,7 +15906,7 @@ design: (work@top) |vpiProcess: \_always: , line:392:4, endln:401:7 |vpiParent: - \_module: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 + \_module_inst: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 |vpiStmt: \_event_control: , line:392:11, endln:392:65 |vpiParent: @@ -16075,7 +16075,7 @@ design: (work@top) |vpiProcess: \_always: , line:404:4, endln:406:7 |vpiParent: - \_module: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 + \_module_inst: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 |vpiStmt: \_event_control: , line:404:11, endln:404:66 |vpiParent: @@ -16115,7 +16115,7 @@ design: (work@top) |vpiProcess: \_always: , line:425:4, endln:448:7 |vpiParent: - \_module: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 + \_module_inst: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 |vpiStmt: \_event_control: , line:425:11, endln:425:58 |vpiParent: @@ -16488,7 +16488,7 @@ design: (work@top) |vpiProcess: \_always: , line:476:4, endln:480:7 |vpiParent: - \_module: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 + \_module_inst: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 |vpiStmt: \_event_control: , line:476:11, endln:476:42 |vpiParent: @@ -16565,7 +16565,7 @@ design: (work@top) |vpiProcess: \_initial: , line:523:4, endln:542:7 |vpiParent: - \_module: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 + \_module_inst: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 |vpiStmt: \_begin: (work@test_program), line:523:12, endln:542:7 |vpiParent: @@ -16822,7 +16822,7 @@ design: (work@top) |vpiConstType:6 |vpiName:$display |uhdmallModules: -\_module: work@test_program1 (work@test_program1), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:800:1, endln:806:10 +\_module_inst: work@test_program1 (work@test_program1), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:800:1, endln:806:10 |vpiParent: \_design: (work@top) |vpiFullName:work@test_program1 @@ -16830,7 +16830,7 @@ design: (work@top) |vpiProcess: \_always: , line:802:4, endln:804:7 |vpiParent: - \_module: work@test_program1 (work@test_program1), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:800:1, endln:806:10 + \_module_inst: work@test_program1 (work@test_program1), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:800:1, endln:806:10 |vpiStmt: \_event_control: , line:802:11, endln:802:69 |vpiParent: @@ -16884,7 +16884,7 @@ design: (work@top) |vpiName:$root.tb.dut.master_0[3].pop_response |vpiAlwaysType:1 |uhdmallModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:1:1, endln:3:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:1:1, endln:3:10 |vpiParent: \_design: (work@top) |vpiFullName:work@top @@ -16892,21 +16892,21 @@ design: (work@top) |vpiNet: \_logic_net: (work@top.b), line:1:25, endln:1:26 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:1:1, endln:3:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:1:1, endln:3:10 |vpiName:b |vpiFullName:work@top.b |vpiNetType:36 |vpiNet: \_logic_net: (work@top.a), line:1:41, endln:1:42 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:1:1, endln:3:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:1:1, endln:3:10 |vpiName:a |vpiFullName:work@top.a |vpiNetType:36 |vpiPort: \_port: (b), line:1:25, endln:1:26 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:1:1, endln:3:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:1:1, endln:3:10 |vpiName:b |vpiDirection:1 |vpiLowConn: @@ -16918,7 +16918,7 @@ design: (work@top) |vpiPort: \_port: (a), line:1:41, endln:1:42 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:1:1, endln:3:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:1:1, endln:3:10 |vpiName:a |vpiDirection:2 |vpiLowConn: @@ -16930,7 +16930,7 @@ design: (work@top) |vpiContAssign: \_cont_assign: , line:2:11, endln:2:26 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:1:1, endln:3:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:1:1, endln:3:10 |vpiRhs: \_ref_obj: (work@top.b), line:2:25, endln:2:26 |vpiParent: @@ -16955,14 +16955,14 @@ design: (work@top) \_ref_obj: (a) |vpiName:a |uhdmtopModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:1:1, endln:3:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:1:1, endln:3:10 |vpiName:work@top |vpiDefName:work@top |vpiTop:1 |vpiNet: \_logic_net: (work@top.b), line:1:25, endln:1:26 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:1:1, endln:3:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:1:1, endln:3:10 |vpiTypespec: \_logic_typespec: , line:1:19, endln:1:24 |vpiName:b @@ -16971,7 +16971,7 @@ design: (work@top) |vpiNet: \_logic_net: (work@top.a), line:1:41, endln:1:42 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:1:1, endln:3:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:1:1, endln:3:10 |vpiTypespec: \_logic_typespec: , line:1:35, endln:1:40 |vpiName:a @@ -16981,7 +16981,7 @@ design: (work@top) |vpiPort: \_port: (b), line:1:25, endln:1:26 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:1:1, endln:3:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:1:1, endln:3:10 |vpiName:b |vpiDirection:1 |vpiLowConn: @@ -16995,11 +16995,11 @@ design: (work@top) |vpiTypedef: \_logic_typespec: , line:1:19, endln:1:24 |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:1:1, endln:3:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:1:1, endln:3:10 |vpiPort: \_port: (a), line:1:41, endln:1:42 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:1:1, endln:3:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:1:1, endln:3:10 |vpiName:a |vpiDirection:2 |vpiLowConn: @@ -17013,11 +17013,11 @@ design: (work@top) |vpiTypedef: \_logic_typespec: , line:1:35, endln:1:40 |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:1:1, endln:3:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:1:1, endln:3:10 |vpiContAssign: \_cont_assign: , line:2:11, endln:2:26 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:1:1, endln:3:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:1:1, endln:3:10 |vpiRhs: \_ref_obj: (work@top.b), line:2:25, endln:2:26 |vpiParent: @@ -17043,7 +17043,7 @@ design: (work@top) \_hier_path: (work@top.$root.top.a), line:2:11, endln:2:17 |vpiName:top |vpiActual: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:1:1, endln:3:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:1:1, endln:3:10 |vpiActual: \_ref_obj: (a) |vpiParent: @@ -17052,18 +17052,18 @@ design: (work@top) |vpiActual: \_logic_net: (work@top.a), line:1:41, endln:1:42 |uhdmtopModules: -\_module: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 +\_module_inst: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 |vpiName:work@test_program |vpiNamedEvent: \_named_event: (work@test_program.assert_fail), line:517:7, endln:517:18 |vpiParent: - \_module: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 + \_module_inst: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 |vpiName:assert_fail |vpiFullName:work@test_program.assert_fail |vpiVariables: \_array_var: (work@test_program.write_command_queue_master), line:67:10, endln:67:39 |vpiParent: - \_module: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 + \_module_inst: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 |vpiSize:2 |vpiTypespec: \_array_typespec: @@ -17106,7 +17106,7 @@ design: (work@top) |vpiVariables: \_array_var: (work@test_program.read_command_queue_master), line:68:10, endln:68:38 |vpiParent: - \_module: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 + \_module_inst: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 |vpiSize:2 |vpiTypespec: \_array_typespec: @@ -17149,7 +17149,7 @@ design: (work@top) |vpiVariables: \_array_var: (work@test_program.write_command_queue_slave), line:71:10, endln:71:38 |vpiParent: - \_module: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 + \_module_inst: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 |vpiSize:2 |vpiTypespec: \_array_typespec: @@ -17161,7 +17161,7 @@ design: (work@top) |vpiVariables: \_array_var: (work@test_program.read_command_queue_slave), line:72:10, endln:72:37 |vpiParent: - \_module: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 + \_module_inst: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 |vpiSize:2 |vpiTypespec: \_array_typespec: @@ -17173,7 +17173,7 @@ design: (work@top) |vpiVariables: \_array_var: (work@test_program.read_response_queue_slave), line:75:10, endln:75:38 |vpiParent: - \_module: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 + \_module_inst: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 |vpiSize:2 |vpiTypespec: \_array_typespec: @@ -17216,7 +17216,7 @@ design: (work@top) |vpiVariables: \_int_var: (work@test_program.pending_read_cycles_slave_0), line:332:8, endln:332:39 |vpiParent: - \_module: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 + \_module_inst: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 |vpiTypespec: \_int_typespec: , line:332:4, endln:332:7 |vpiSigned:1 @@ -17232,7 +17232,7 @@ design: (work@top) |vpiVariables: \_int_var: (work@test_program.pending_read_cycles_slave_1), line:475:8, endln:475:39 |vpiParent: - \_module: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 + \_module_inst: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 |vpiTypespec: \_int_typespec: , line:475:4, endln:475:7 |vpiSigned:1 @@ -17248,7 +17248,7 @@ design: (work@top) |vpiVariables: \_bit_var: (work@test_program.test_success), line:511:5, endln:511:21 |vpiParent: - \_module: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 + \_module_inst: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 |vpiTypespec: \_bit_typespec: , line:511:1, endln:511:4 |vpiSigned:1 @@ -17264,7 +17264,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@test_program.ADDR_W), line:13:15, endln:13:21 |vpiParent: - \_module: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 + \_module_inst: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 |UINT:13 |vpiTypespec: \_int_typespec: @@ -17276,7 +17276,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@test_program.SYMBOL_W), line:15:15, endln:15:23 |vpiParent: - \_module: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 + \_module_inst: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 |UINT:8 |vpiTypespec: \_int_typespec: @@ -17288,7 +17288,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@test_program.NUM_SYMBOLS), line:16:15, endln:16:26 |vpiParent: - \_module: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 + \_module_inst: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 |UINT:4 |vpiTypespec: \_int_typespec: @@ -17300,14 +17300,14 @@ design: (work@top) |vpiParameter: \_parameter: (work@test_program.DATA_W), line:17:15, endln:17:21 |vpiParent: - \_module: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 + \_module_inst: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 |vpiLocalParam:1 |vpiName:DATA_W |vpiFullName:work@test_program.DATA_W |vpiParameter: \_parameter: (work@test_program.BURST_W), line:19:15, endln:19:22 |vpiParent: - \_module: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 + \_module_inst: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 |UINT:4 |vpiTypespec: \_int_typespec: @@ -17319,7 +17319,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@test_program.MAX_BURST), line:20:15, endln:20:24 |vpiParent: - \_module: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 + \_module_inst: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 |UINT:8 |vpiTypespec: \_int_typespec: @@ -17331,7 +17331,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@test_program.SLAVE_SPAN), line:22:15, endln:22:25 |vpiParent: - \_module: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 + \_module_inst: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 |HEX:1000 |vpiTypespec: \_int_typespec: @@ -17357,7 +17357,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@test_program.MAX_COMMAND_IDLE), line:24:15, endln:24:31 |vpiParent: - \_module: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 + \_module_inst: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 |UINT:5 |vpiTypespec: \_int_typespec: @@ -17369,7 +17369,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@test_program.MAX_COMMAND_BACKPRESSURE), line:25:15, endln:25:39 |vpiParent: - \_module: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 + \_module_inst: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 |UINT:2 |vpiTypespec: \_int_typespec: @@ -17381,7 +17381,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@test_program.MAX_DATA_IDLE), line:26:15, endln:26:28 |vpiParent: - \_module: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 + \_module_inst: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 |UINT:3 |vpiTypespec: \_int_typespec: @@ -17393,7 +17393,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:13:15, endln:13:44 |vpiParent: - \_module: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 + \_module_inst: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 |vpiRhs: \_constant: , line:13:42, endln:13:44 |vpiDecompile:13 @@ -17407,7 +17407,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:15:15, endln:15:43 |vpiParent: - \_module: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 + \_module_inst: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 |vpiRhs: \_constant: , line:15:42, endln:15:43 |vpiDecompile:8 @@ -17421,7 +17421,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:16:15, endln:16:43 |vpiParent: - \_module: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 + \_module_inst: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 |vpiRhs: \_constant: , line:16:42, endln:16:43 |vpiDecompile:4 @@ -17435,7 +17435,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:17:15, endln:17:64 |vpiParent: - \_module: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 + \_module_inst: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 |vpiRhs: \_constant: , line:17:42, endln:17:64 |vpiDecompile:32 @@ -17447,7 +17447,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:19:15, endln:19:43 |vpiParent: - \_module: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 + \_module_inst: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 |vpiRhs: \_constant: , line:19:42, endln:19:43 |vpiDecompile:4 @@ -17461,7 +17461,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:20:15, endln:20:43 |vpiParent: - \_module: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 + \_module_inst: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 |vpiRhs: \_constant: , line:20:42, endln:20:43 |vpiDecompile:8 @@ -17475,7 +17475,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:22:15, endln:22:50 |vpiParent: - \_module: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 + \_module_inst: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 |vpiRhs: \_constant: , line:22:42, endln:22:50 |vpiDecompile:32'h1000 @@ -17489,7 +17489,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:24:15, endln:24:43 |vpiParent: - \_module: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 + \_module_inst: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 |vpiRhs: \_constant: , line:24:42, endln:24:43 |vpiDecompile:5 @@ -17503,7 +17503,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:25:15, endln:25:43 |vpiParent: - \_module: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 + \_module_inst: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 |vpiRhs: \_constant: , line:25:42, endln:25:43 |vpiDecompile:2 @@ -17517,7 +17517,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:26:15, endln:26:43 |vpiParent: - \_module: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 + \_module_inst: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 |vpiRhs: \_constant: , line:26:42, endln:26:43 |vpiDecompile:3 @@ -17547,13 +17547,13 @@ design: (work@top) |vpiTaskFunc: \_task: (work@test_program.configure_and_push_command_to_master_0), line:224:4, endln:245:11 |vpiParent: - \_module: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 + \_module_inst: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 |vpiName:configure_and_push_command_to_master_0 |vpiFullName:work@test_program.configure_and_push_command_to_master_0 |vpiVisibility:1 |vpiAutomatic:1 |vpiParent: - \_module: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 + \_module_inst: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 |vpiIODecl: \_io_decl: (cmd), line:225:16, endln:225:19 |vpiParent: @@ -17975,11 +17975,11 @@ design: (work@top) \_begin: (work@test_program.configure_and_push_command_to_master_0) |vpiName:$root.tb.dut.master_0.push_command |vpiInstance: - \_module: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 + \_module_inst: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 |vpiTaskFunc: \_function: (work@test_program.get_read_response_from_master_0), line:266:4, endln:277:15 |vpiParent: - \_module: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 + \_module_inst: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 |vpiName:get_read_response_from_master_0 |vpiFullName:work@test_program.get_read_response_from_master_0 |vpiVariables: @@ -17995,7 +17995,7 @@ design: (work@top) |vpiReturn: \_struct_var: , line:266:23, endln:266:31 |vpiParent: - \_module: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 + \_module_inst: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 |vpiStmt: \_begin: (work@test_program.get_read_response_from_master_0) |vpiParent: @@ -18224,11 +18224,11 @@ design: (work@top) |vpiActual: \_struct_var: (work@test_program.get_read_response_from_master_0.rsp), line:268:16, endln:268:19 |vpiInstance: - \_module: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 + \_module_inst: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 |vpiTaskFunc: \_function: (work@test_program.get_command_from_slave_0), line:309:4, endln:328:15 |vpiParent: - \_module: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 + \_module_inst: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 |vpiName:get_command_from_slave_0 |vpiFullName:work@test_program.get_command_from_slave_0 |vpiVariables: @@ -18244,7 +18244,7 @@ design: (work@top) |vpiReturn: \_struct_var: , line:309:23, endln:309:30 |vpiParent: - \_module: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 + \_module_inst: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 |vpiStmt: \_begin: (work@test_program.get_command_from_slave_0) |vpiParent: @@ -18724,11 +18724,11 @@ design: (work@top) |vpiActual: \_struct_var: (work@test_program.get_command_from_slave_0.cmd), line:311:15, endln:311:18 |vpiInstance: - \_module: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 + \_module_inst: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 |vpiTaskFunc: \_task: (work@test_program.configure_and_push_response_to_slave_0), line:340:1, endln:362:11 |vpiParent: - \_module: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 + \_module_inst: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 |vpiName:configure_and_push_response_to_slave_0 |vpiFullName:work@test_program.configure_and_push_response_to_slave_0 |vpiVariables: @@ -18743,7 +18743,7 @@ design: (work@top) |vpiVisibility:1 |vpiAutomatic:1 |vpiParent: - \_module: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 + \_module_inst: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 |vpiIODecl: \_io_decl: (rsp), line:341:16, endln:341:19 |vpiParent: @@ -19222,17 +19222,17 @@ design: (work@top) |vpiActual: \_int_var: (work@test_program.pending_read_cycles_slave_0), line:332:8, endln:332:39 |vpiInstance: - \_module: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 + \_module_inst: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 |vpiTaskFunc: \_task: (work@test_program.configure_and_push_command_to_master_1), line:367:4, endln:388:11 |vpiParent: - \_module: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 + \_module_inst: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 |vpiName:configure_and_push_command_to_master_1 |vpiFullName:work@test_program.configure_and_push_command_to_master_1 |vpiVisibility:1 |vpiAutomatic:1 |vpiParent: - \_module: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 + \_module_inst: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 |vpiIODecl: \_io_decl: (cmd), line:368:16, endln:368:19 |vpiParent: @@ -19654,11 +19654,11 @@ design: (work@top) \_begin: (work@test_program.configure_and_push_command_to_master_1) |vpiName:$root.tb.dut.master_1.push_command |vpiInstance: - \_module: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 + \_module_inst: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 |vpiTaskFunc: \_function: (work@test_program.get_read_response_from_master_1), line:409:4, endln:420:15 |vpiParent: - \_module: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 + \_module_inst: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 |vpiName:get_read_response_from_master_1 |vpiFullName:work@test_program.get_read_response_from_master_1 |vpiVariables: @@ -19674,7 +19674,7 @@ design: (work@top) |vpiReturn: \_struct_var: , line:409:23, endln:409:31 |vpiParent: - \_module: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 + \_module_inst: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 |vpiStmt: \_begin: (work@test_program.get_read_response_from_master_1) |vpiParent: @@ -19903,11 +19903,11 @@ design: (work@top) |vpiActual: \_struct_var: (work@test_program.get_read_response_from_master_1.rsp), line:411:16, endln:411:19 |vpiInstance: - \_module: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 + \_module_inst: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 |vpiTaskFunc: \_function: (work@test_program.get_command_from_slave_1), line:452:4, endln:471:15 |vpiParent: - \_module: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 + \_module_inst: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 |vpiName:get_command_from_slave_1 |vpiFullName:work@test_program.get_command_from_slave_1 |vpiVariables: @@ -19923,7 +19923,7 @@ design: (work@top) |vpiReturn: \_struct_var: , line:452:23, endln:452:30 |vpiParent: - \_module: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 + \_module_inst: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 |vpiStmt: \_begin: (work@test_program.get_command_from_slave_1) |vpiParent: @@ -20403,11 +20403,11 @@ design: (work@top) |vpiActual: \_struct_var: (work@test_program.get_command_from_slave_1.cmd), line:454:15, endln:454:18 |vpiInstance: - \_module: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 + \_module_inst: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 |vpiTaskFunc: \_task: (work@test_program.configure_and_push_response_to_slave_1), line:483:1, endln:505:11 |vpiParent: - \_module: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 + \_module_inst: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 |vpiName:configure_and_push_response_to_slave_1 |vpiFullName:work@test_program.configure_and_push_response_to_slave_1 |vpiVariables: @@ -20422,7 +20422,7 @@ design: (work@top) |vpiVisibility:1 |vpiAutomatic:1 |vpiParent: - \_module: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 + \_module_inst: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 |vpiIODecl: \_io_decl: (rsp), line:484:16, endln:484:19 |vpiParent: @@ -20901,11 +20901,11 @@ design: (work@top) |vpiActual: \_int_var: (work@test_program.pending_read_cycles_slave_1), line:475:8, endln:475:39 |vpiInstance: - \_module: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 + \_module_inst: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 |vpiTaskFunc: \_task: (work@test_program.master_send_commands), line:544:4, endln:568:11 |vpiParent: - \_module: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 + \_module_inst: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 |vpiName:master_send_commands |vpiFullName:work@test_program.master_send_commands |vpiVariables: @@ -20953,7 +20953,7 @@ design: (work@top) |vpiVisibility:1 |vpiAutomatic:1 |vpiParent: - \_module: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 + \_module_inst: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 |vpiIODecl: \_io_decl: (num_command), line:545:22, endln:545:33 |vpiParent: @@ -21221,11 +21221,11 @@ design: (work@top) |vpiTask: \_task: (work@test_program.queue_command), line:620:4, endln:629:11 |vpiInstance: - \_module: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 + \_module_inst: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 |vpiTaskFunc: \_function: (work@test_program.create_command), line:570:4, endln:599:15 |vpiParent: - \_module: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 + \_module_inst: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 |vpiName:create_command |vpiFullName:work@test_program.create_command |vpiVariables: @@ -21241,7 +21241,7 @@ design: (work@top) |vpiReturn: \_struct_var: , line:570:23, endln:570:30 |vpiParent: - \_module: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 + \_module_inst: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 |vpiIODecl: \_io_decl: (trans), line:571:22, endln:571:27 |vpiParent: @@ -21813,11 +21813,11 @@ design: (work@top) |vpiActual: \_struct_var: (work@test_program.create_command.cmd), line:576:15, endln:576:18 |vpiInstance: - \_module: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 + \_module_inst: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 |vpiTaskFunc: \_function: (work@test_program.randomize_burstcount), line:601:4, endln:607:15 |vpiParent: - \_module: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 + \_module_inst: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 |vpiName:randomize_burstcount |vpiFullName:work@test_program.randomize_burstcount |vpiVariables: @@ -21833,7 +21833,7 @@ design: (work@top) |vpiReturn: \_logic_var: , line:601:23, endln:601:33 |vpiParent: - \_module: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 + \_module_inst: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 |vpiStmt: \_begin: (work@test_program.randomize_burstcount) |vpiParent: @@ -21889,11 +21889,11 @@ design: (work@top) |vpiActual: \_logic_var: (work@test_program.randomize_burstcount.burstcount), line:603:18, endln:603:28 |vpiInstance: - \_module: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 + \_module_inst: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 |vpiTaskFunc: \_function: (work@test_program.generate_random_aligned_address), line:609:4, endln:618:15 |vpiParent: - \_module: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 + \_module_inst: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 |vpiName:generate_random_aligned_address |vpiFullName:work@test_program.generate_random_aligned_address |vpiVariables: @@ -21917,7 +21917,7 @@ design: (work@top) |vpiReturn: \_logic_var: , line:609:23, endln:609:42 |vpiParent: - \_module: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 + \_module_inst: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 |vpiIODecl: \_io_decl: (slave_id), line:610:11, endln:610:19 |vpiParent: @@ -22066,17 +22066,17 @@ design: (work@top) |vpiActual: \_parameter: (work@test_program.NUM_SYMBOLS), line:16:15, endln:16:26 |vpiInstance: - \_module: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 + \_module_inst: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 |vpiTaskFunc: \_task: (work@test_program.queue_command), line:620:4, endln:629:11 |vpiParent: - \_module: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 + \_module_inst: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 |vpiName:queue_command |vpiFullName:work@test_program.queue_command |vpiVisibility:1 |vpiAutomatic:1 |vpiParent: - \_module: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 + \_module_inst: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 |vpiIODecl: \_io_decl: (cmd), line:621:16, endln:621:19 |vpiParent: @@ -22176,17 +22176,17 @@ design: (work@top) |vpiTask: \_task: (work@test_program.configure_and_push_command_to_master), line:670:4, endln:680:11 |vpiInstance: - \_module: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 + \_module_inst: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 |vpiTaskFunc: \_task: (work@test_program.save_command_master), line:631:4, endln:642:11 |vpiParent: - \_module: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 + \_module_inst: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 |vpiName:save_command_master |vpiFullName:work@test_program.save_command_master |vpiVisibility:1 |vpiAutomatic:1 |vpiParent: - \_module: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 + \_module_inst: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 |vpiIODecl: \_io_decl: (cmd), line:632:16, endln:632:19 |vpiParent: @@ -22292,17 +22292,17 @@ design: (work@top) |vpiActual: \_array_var: (work@test_program.read_command_queue_master), line:68:10, endln:68:38 |vpiInstance: - \_module: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 + \_module_inst: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 |vpiTaskFunc: \_task: (work@test_program.save_command_slave), line:644:4, endln:656:11 |vpiParent: - \_module: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 + \_module_inst: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 |vpiName:save_command_slave |vpiFullName:work@test_program.save_command_slave |vpiVisibility:1 |vpiAutomatic:1 |vpiParent: - \_module: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 + \_module_inst: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 |vpiIODecl: \_io_decl: (cmd), line:645:16, endln:645:19 |vpiParent: @@ -22464,11 +22464,11 @@ design: (work@top) |vpiActual: \_array_var: (work@test_program.read_command_queue_slave), line:72:10, endln:72:37 |vpiInstance: - \_module: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 + \_module_inst: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 |vpiTaskFunc: \_function: (work@test_program.translate_master_to_slave_address), line:658:4, endln:668:15 |vpiParent: - \_module: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 + \_module_inst: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 |vpiName:translate_master_to_slave_address |vpiFullName:work@test_program.translate_master_to_slave_address |vpiVariables: @@ -22501,7 +22501,7 @@ design: (work@top) |vpiReturn: \_logic_var: , line:658:23, endln:658:42 |vpiParent: - \_module: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 + \_module_inst: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 |vpiIODecl: \_io_decl: (addr), line:659:28, endln:659:32 |vpiParent: @@ -22670,17 +22670,17 @@ design: (work@top) |vpiActual: \_parameter: (work@test_program.NUM_SYMBOLS), line:16:15, endln:16:26 |vpiInstance: - \_module: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 + \_module_inst: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 |vpiTaskFunc: \_task: (work@test_program.configure_and_push_command_to_master), line:670:4, endln:680:11 |vpiParent: - \_module: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 + \_module_inst: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 |vpiName:configure_and_push_command_to_master |vpiFullName:work@test_program.configure_and_push_command_to_master |vpiVisibility:1 |vpiAutomatic:1 |vpiParent: - \_module: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 + \_module_inst: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 |vpiIODecl: \_io_decl: (cmd), line:671:16, endln:671:19 |vpiParent: @@ -22776,11 +22776,11 @@ design: (work@top) |vpiTask: \_task: (work@test_program.configure_and_push_command_to_master_1), line:367:4, endln:388:11 |vpiInstance: - \_module: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 + \_module_inst: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 |vpiTaskFunc: \_function: (work@test_program.get_expected_command_for_slave), line:682:4, endln:717:15 |vpiParent: - \_module: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 + \_module_inst: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 |vpiName:get_expected_command_for_slave |vpiFullName:work@test_program.get_expected_command_for_slave |vpiVariables: @@ -22805,7 +22805,7 @@ design: (work@top) |vpiReturn: \_struct_var: , line:682:23, endln:682:30 |vpiParent: - \_module: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 + \_module_inst: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 |vpiIODecl: \_io_decl: (cmd), line:683:15, endln:683:18 |vpiParent: @@ -23386,17 +23386,17 @@ design: (work@top) |vpiActual: \_struct_var: (work@test_program.get_expected_command_for_slave.exp_cmd), line:687:15, endln:687:22 |vpiInstance: - \_module: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 + \_module_inst: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 |vpiTaskFunc: \_task: (work@test_program.verify_command), line:719:4, endln:733:11 |vpiParent: - \_module: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 + \_module_inst: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 |vpiName:verify_command |vpiFullName:work@test_program.verify_command |vpiVisibility:1 |vpiAutomatic:1 |vpiParent: - \_module: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 + \_module_inst: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 |vpiIODecl: \_io_decl: (actual_cmd), line:720:15, endln:720:25 |vpiParent: @@ -23766,11 +23766,11 @@ design: (work@top) |vpiTask: \_task: (work@test_program.assert_equals), line:735:4, endln:757:11 |vpiInstance: - \_module: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 + \_module_inst: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 |vpiTaskFunc: \_task: (work@test_program.assert_equals), line:735:4, endln:757:11 |vpiParent: - \_module: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 + \_module_inst: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 |vpiName:assert_equals |vpiFullName:work@test_program.assert_equals |vpiVariables: @@ -23784,7 +23784,7 @@ design: (work@top) |vpiVisibility:1 |vpiAutomatic:1 |vpiParent: - \_module: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 + \_module_inst: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 |vpiIODecl: \_io_decl: (message), line:736:14, endln:736:21 |vpiParent: @@ -23945,11 +23945,11 @@ design: (work@top) |vpiName:assert_fail |vpiBlocking:1 |vpiInstance: - \_module: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 + \_module_inst: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 |vpiTaskFunc: \_function: (work@test_program.create_response), line:759:4, endln:772:15 |vpiParent: - \_module: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 + \_module_inst: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 |vpiName:create_response |vpiFullName:work@test_program.create_response |vpiVariables: @@ -23965,7 +23965,7 @@ design: (work@top) |vpiReturn: \_struct_var: , line:759:23, endln:759:31 |vpiParent: - \_module: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 + \_module_inst: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 |vpiIODecl: \_io_decl: (burstcount), line:760:18, endln:760:28 |vpiParent: @@ -24192,11 +24192,11 @@ design: (work@top) |vpiActual: \_struct_var: (work@test_program.create_response.rsp), line:763:16, endln:763:19 |vpiInstance: - \_module: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 + \_module_inst: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 |vpiTaskFunc: \_function: (work@test_program.get_expected_read_response), line:774:4, endln:784:15 |vpiParent: - \_module: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 + \_module_inst: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 |vpiName:get_expected_read_response |vpiFullName:work@test_program.get_expected_read_response |vpiVariables: @@ -24221,7 +24221,7 @@ design: (work@top) |vpiReturn: \_struct_var: , line:774:23, endln:774:31 |vpiParent: - \_module: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 + \_module_inst: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 |vpiIODecl: \_io_decl: (cmd), line:775:15, endln:775:18 |vpiParent: @@ -24353,17 +24353,17 @@ design: (work@top) |vpiActual: \_struct_var: (work@test_program.get_expected_read_response.rsp), line:778:16, endln:778:19 |vpiInstance: - \_module: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 + \_module_inst: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 |vpiTaskFunc: \_task: (work@test_program.verify_response), line:786:4, endln:795:11 |vpiParent: - \_module: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 + \_module_inst: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 |vpiName:verify_response |vpiFullName:work@test_program.verify_response |vpiVisibility:1 |vpiAutomatic:1 |vpiParent: - \_module: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 + \_module_inst: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 |vpiIODecl: \_io_decl: (actual_rsp), line:787:16, endln:787:26 |vpiParent: @@ -24574,7 +24574,7 @@ design: (work@top) |vpiTask: \_task: (work@test_program.assert_equals), line:735:4, endln:757:11 |vpiInstance: - \_module: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 + \_module_inst: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 |vpiNet: \_logic_net: (REQ_WRITE) |vpiName:REQ_WRITE @@ -24599,7 +24599,7 @@ design: (work@top) |vpiProcess: \_always: , line:249:4, endln:258:7 |vpiParent: - \_module: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 + \_module_inst: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 |vpiStmt: \_event_control: , line:249:11, endln:249:65 |vpiParent: @@ -24778,7 +24778,7 @@ design: (work@top) |vpiProcess: \_always: , line:261:4, endln:263:7 |vpiParent: - \_module: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 + \_module_inst: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 |vpiStmt: \_event_control: , line:261:11, endln:261:66 |vpiParent: @@ -24828,7 +24828,7 @@ design: (work@top) |vpiProcess: \_always: , line:282:4, endln:305:7 |vpiParent: - \_module: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 + \_module_inst: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 |vpiStmt: \_event_control: , line:282:11, endln:282:58 |vpiParent: @@ -25208,7 +25208,7 @@ design: (work@top) |vpiProcess: \_always: , line:333:4, endln:337:7 |vpiParent: - \_module: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 + \_module_inst: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 |vpiStmt: \_event_control: , line:333:11, endln:333:42 |vpiParent: @@ -25290,7 +25290,7 @@ design: (work@top) |vpiProcess: \_always: , line:392:4, endln:401:7 |vpiParent: - \_module: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 + \_module_inst: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 |vpiStmt: \_event_control: , line:392:11, endln:392:65 |vpiParent: @@ -25469,7 +25469,7 @@ design: (work@top) |vpiProcess: \_always: , line:404:4, endln:406:7 |vpiParent: - \_module: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 + \_module_inst: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 |vpiStmt: \_event_control: , line:404:11, endln:404:66 |vpiParent: @@ -25519,7 +25519,7 @@ design: (work@top) |vpiProcess: \_always: , line:425:4, endln:448:7 |vpiParent: - \_module: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 + \_module_inst: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 |vpiStmt: \_event_control: , line:425:11, endln:425:58 |vpiParent: @@ -25899,7 +25899,7 @@ design: (work@top) |vpiProcess: \_always: , line:476:4, endln:480:7 |vpiParent: - \_module: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 + \_module_inst: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 |vpiStmt: \_event_control: , line:476:11, endln:476:42 |vpiParent: @@ -25981,7 +25981,7 @@ design: (work@top) |vpiProcess: \_initial: , line:523:4, endln:542:7 |vpiParent: - \_module: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 + \_module_inst: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 |vpiStmt: \_begin: (work@test_program), line:523:12, endln:542:7 |vpiParent: @@ -26180,7 +26180,7 @@ design: (work@top) \_constant: , line:541:16, endln:541:50 |vpiName:$display |uhdmtopModules: -\_module: work@test_program1 (work@test_program1), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:800:1, endln:806:10 +\_module_inst: work@test_program1 (work@test_program1), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:800:1, endln:806:10 |vpiName:work@test_program1 |vpiDefName:work@test_program1 |vpiTop:1 @@ -26188,7 +26188,7 @@ design: (work@top) |vpiProcess: \_always: , line:802:4, endln:804:7 |vpiParent: - \_module: work@test_program1 (work@test_program1), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:800:1, endln:806:10 + \_module_inst: work@test_program1 (work@test_program1), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:800:1, endln:806:10 |vpiStmt: \_event_control: , line:802:11, endln:802:69 |vpiParent: diff --git a/tests/DoublePres/DoublePres.log b/tests/DoublePres/DoublePres.log index 732be4b461..bc8348d310 100644 --- a/tests/DoublePres/DoublePres.log +++ b/tests/DoublePres/DoublePres.log @@ -1140,7 +1140,7 @@ integer_var 1 logic_net 8 logic_typespec 12 logic_var 2 -module 22 +module_inst 22 operation 63 param_assign 43 parameter 43 @@ -1166,7 +1166,7 @@ integer_var 2 logic_net 8 logic_typespec 12 logic_var 2 -module 36 +module_inst 36 operation 64 param_assign 43 parameter 43 @@ -1188,14 +1188,14 @@ design: (work@top) |vpiElaborated:1 |vpiName:work@top |uhdmallModules: -\_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/DoublePres/dut.sv, line:8:1, endln:111:10 +\_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/DoublePres/dut.sv, line:8:1, endln:111:10 |vpiParent: \_design: (work@top) |vpiFullName:work@dut |vpiParameter: \_parameter: (work@dut.CLKFBOUT_PHASE), line:9:18, endln:9:32 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/DoublePres/dut.sv, line:8:1, endln:111:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/DoublePres/dut.sv, line:8:1, endln:111:10 |REAL:1142.500000 |vpiTypespec: \_real_typespec: , line:9:13, endln:9:17 @@ -1206,13 +1206,13 @@ design: (work@top) |vpiParameter: \_parameter: (work@dut.err), line:12:13, endln:12:16 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/DoublePres/dut.sv, line:8:1, endln:111:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/DoublePres/dut.sv, line:8:1, endln:111:10 |vpiName:err |vpiFullName:work@dut.err |vpiParameter: \_parameter: (work@dut.f), line:14:11, endln:14:12 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/DoublePres/dut.sv, line:8:1, endln:111:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/DoublePres/dut.sv, line:8:1, endln:111:10 |UINT:9 |vpiTypespec: \_int_typespec: @@ -1221,7 +1221,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@dut.r), line:15:11, endln:15:12 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/DoublePres/dut.sv, line:8:1, endln:111:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/DoublePres/dut.sv, line:8:1, endln:111:10 |REAL:5.700000 |vpiTypespec: \_real_typespec: @@ -1230,103 +1230,103 @@ design: (work@top) |vpiParameter: \_parameter: (work@dut.average_delay), line:16:11, endln:16:24 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/DoublePres/dut.sv, line:8:1, endln:111:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/DoublePres/dut.sv, line:8:1, endln:111:10 |vpiName:average_delay |vpiFullName:work@dut.average_delay |vpiParameter: \_parameter: (work@dut.A1), line:18:11, endln:18:13 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/DoublePres/dut.sv, line:8:1, endln:111:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/DoublePres/dut.sv, line:8:1, endln:111:10 |vpiName:A1 |vpiFullName:work@dut.A1 |vpiParameter: \_parameter: (work@dut.A2), line:20:11, endln:20:13 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/DoublePres/dut.sv, line:8:1, endln:111:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/DoublePres/dut.sv, line:8:1, endln:111:10 |vpiName:A2 |vpiFullName:work@dut.A2 |vpiParameter: \_parameter: (work@dut.A3), line:22:11, endln:22:13 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/DoublePres/dut.sv, line:8:1, endln:111:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/DoublePres/dut.sv, line:8:1, endln:111:10 |vpiName:A3 |vpiFullName:work@dut.A3 |vpiParameter: \_parameter: (work@dut.A4), line:24:11, endln:24:13 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/DoublePres/dut.sv, line:8:1, endln:111:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/DoublePres/dut.sv, line:8:1, endln:111:10 |vpiName:A4 |vpiFullName:work@dut.A4 |vpiParameter: \_parameter: (work@dut.A5), line:26:11, endln:26:13 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/DoublePres/dut.sv, line:8:1, endln:111:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/DoublePres/dut.sv, line:8:1, endln:111:10 |vpiName:A5 |vpiFullName:work@dut.A5 |vpiParameter: \_parameter: (work@dut.A6), line:28:11, endln:28:13 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/DoublePres/dut.sv, line:8:1, endln:111:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/DoublePres/dut.sv, line:8:1, endln:111:10 |vpiName:A6 |vpiFullName:work@dut.A6 |vpiParameter: \_parameter: (work@dut.A7), line:30:11, endln:30:13 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/DoublePres/dut.sv, line:8:1, endln:111:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/DoublePres/dut.sv, line:8:1, endln:111:10 |vpiName:A7 |vpiFullName:work@dut.A7 |vpiParameter: \_parameter: (work@dut.A8), line:32:11, endln:32:13 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/DoublePres/dut.sv, line:8:1, endln:111:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/DoublePres/dut.sv, line:8:1, endln:111:10 |vpiName:A8 |vpiFullName:work@dut.A8 |vpiParameter: \_parameter: (work@dut.A9), line:34:11, endln:34:13 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/DoublePres/dut.sv, line:8:1, endln:111:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/DoublePres/dut.sv, line:8:1, endln:111:10 |vpiName:A9 |vpiFullName:work@dut.A9 |vpiParameter: \_parameter: (work@dut.A10), line:36:11, endln:36:14 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/DoublePres/dut.sv, line:8:1, endln:111:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/DoublePres/dut.sv, line:8:1, endln:111:10 |vpiName:A10 |vpiFullName:work@dut.A10 |vpiParameter: \_parameter: (work@dut.A11), line:38:11, endln:38:14 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/DoublePres/dut.sv, line:8:1, endln:111:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/DoublePres/dut.sv, line:8:1, endln:111:10 |vpiName:A11 |vpiFullName:work@dut.A11 |vpiParameter: \_parameter: (work@dut.A12), line:40:11, endln:40:14 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/DoublePres/dut.sv, line:8:1, endln:111:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/DoublePres/dut.sv, line:8:1, endln:111:10 |vpiName:A12 |vpiFullName:work@dut.A12 |vpiParameter: \_parameter: (work@dut.A13), line:42:11, endln:42:14 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/DoublePres/dut.sv, line:8:1, endln:111:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/DoublePres/dut.sv, line:8:1, endln:111:10 |vpiName:A13 |vpiFullName:work@dut.A13 |vpiParameter: \_parameter: (work@dut.A14), line:44:11, endln:44:14 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/DoublePres/dut.sv, line:8:1, endln:111:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/DoublePres/dut.sv, line:8:1, endln:111:10 |vpiName:A14 |vpiFullName:work@dut.A14 |vpiParameter: \_parameter: (work@dut.A15), line:53:11, endln:53:14 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/DoublePres/dut.sv, line:8:1, endln:111:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/DoublePres/dut.sv, line:8:1, endln:111:10 |vpiName:A15 |vpiFullName:work@dut.A15 |vpiParamAssign: \_param_assign: , line:9:18, endln:9:43 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/DoublePres/dut.sv, line:8:1, endln:111:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/DoublePres/dut.sv, line:8:1, endln:111:10 |vpiRhs: \_constant: , line:9:35, endln:9:43 |vpiDecompile:1142.500 @@ -1340,7 +1340,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:12:13, endln:12:37 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/DoublePres/dut.sv, line:8:1, endln:111:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/DoublePres/dut.sv, line:8:1, endln:111:10 |vpiRhs: \_operation: , line:12:19, endln:12:37 |vpiOpType:12 @@ -1362,7 +1362,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:14:11, endln:14:16 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/DoublePres/dut.sv, line:8:1, endln:111:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/DoublePres/dut.sv, line:8:1, endln:111:10 |vpiRhs: \_constant: , line:14:15, endln:14:16 |vpiDecompile:9 @@ -1376,7 +1376,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:15:11, endln:15:18 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/DoublePres/dut.sv, line:8:1, endln:111:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/DoublePres/dut.sv, line:8:1, endln:111:10 |vpiRhs: \_constant: , line:15:15, endln:15:18 |vpiDecompile:5.7 @@ -1390,7 +1390,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:16:11, endln:16:36 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/DoublePres/dut.sv, line:8:1, endln:111:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/DoublePres/dut.sv, line:8:1, endln:111:10 |vpiRhs: \_operation: , line:16:27, endln:16:36 |vpiOpType:12 @@ -1422,7 +1422,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:18:11, endln:18:25 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/DoublePres/dut.sv, line:8:1, endln:111:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/DoublePres/dut.sv, line:8:1, endln:111:10 |vpiRhs: \_operation: , line:18:16, endln:18:25 |vpiOpType:25 @@ -1447,7 +1447,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:20:11, endln:20:25 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/DoublePres/dut.sv, line:8:1, endln:111:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/DoublePres/dut.sv, line:8:1, endln:111:10 |vpiRhs: \_operation: , line:20:16, endln:20:25 |vpiOpType:11 @@ -1472,7 +1472,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:22:11, endln:22:21 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/DoublePres/dut.sv, line:8:1, endln:111:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/DoublePres/dut.sv, line:8:1, endln:111:10 |vpiRhs: \_operation: , line:22:16, endln:22:21 |vpiOpType:1 @@ -1487,7 +1487,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:24:11, endln:24:21 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/DoublePres/dut.sv, line:8:1, endln:111:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/DoublePres/dut.sv, line:8:1, endln:111:10 |vpiRhs: \_operation: , line:24:16, endln:24:21 |vpiOpType:24 @@ -1512,7 +1512,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:26:11, endln:26:21 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/DoublePres/dut.sv, line:8:1, endln:111:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/DoublePres/dut.sv, line:8:1, endln:111:10 |vpiRhs: \_operation: , line:26:16, endln:26:21 |vpiOpType:11 @@ -1537,7 +1537,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:28:11, endln:28:21 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/DoublePres/dut.sv, line:8:1, endln:111:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/DoublePres/dut.sv, line:8:1, endln:111:10 |vpiRhs: \_operation: , line:28:16, endln:28:21 |vpiOpType:25 @@ -1562,7 +1562,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:30:11, endln:30:21 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/DoublePres/dut.sv, line:8:1, endln:111:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/DoublePres/dut.sv, line:8:1, endln:111:10 |vpiRhs: \_operation: , line:30:16, endln:30:21 |vpiOpType:12 @@ -1587,7 +1587,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:32:11, endln:32:22 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/DoublePres/dut.sv, line:8:1, endln:111:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/DoublePres/dut.sv, line:8:1, endln:111:10 |vpiRhs: \_operation: , line:32:16, endln:32:22 |vpiOpType:13 @@ -1612,7 +1612,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:34:11, endln:34:26 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/DoublePres/dut.sv, line:8:1, endln:111:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/DoublePres/dut.sv, line:8:1, endln:111:10 |vpiRhs: \_operation: , line:34:16, endln:34:26 |vpiOpType:13 @@ -1637,7 +1637,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:36:11, endln:36:25 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/DoublePres/dut.sv, line:8:1, endln:111:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/DoublePres/dut.sv, line:8:1, endln:111:10 |vpiRhs: \_operation: , line:36:17, endln:36:25 |vpiOpType:13 @@ -1662,7 +1662,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:38:11, endln:38:23 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/DoublePres/dut.sv, line:8:1, endln:111:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/DoublePres/dut.sv, line:8:1, endln:111:10 |vpiRhs: \_operation: , line:38:17, endln:38:23 |vpiOpType:43 @@ -1687,7 +1687,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:40:11, endln:40:25 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/DoublePres/dut.sv, line:8:1, endln:111:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/DoublePres/dut.sv, line:8:1, endln:111:10 |vpiRhs: \_operation: , line:40:17, endln:40:25 |vpiOpType:43 @@ -1712,7 +1712,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:42:11, endln:42:32 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/DoublePres/dut.sv, line:8:1, endln:111:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/DoublePres/dut.sv, line:8:1, endln:111:10 |vpiRhs: \_operation: , line:42:18, endln:42:32 |vpiOpType:32 @@ -1736,7 +1736,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:44:11, endln:44:23 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/DoublePres/dut.sv, line:8:1, endln:111:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/DoublePres/dut.sv, line:8:1, endln:111:10 |vpiRhs: \_operation: , line:44:17, endln:44:23 |vpiOpType:13 @@ -1761,7 +1761,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:53:11, endln:53:25 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/DoublePres/dut.sv, line:8:1, endln:111:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/DoublePres/dut.sv, line:8:1, endln:111:10 |vpiRhs: \_func_call: (incr_d), line:53:17, endln:53:23 |vpiName:incr_d @@ -1773,7 +1773,7 @@ design: (work@top) |vpiTaskFunc: \_function: (work@dut.incr_d), line:46:1, endln:51:12 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/DoublePres/dut.sv, line:8:1, endln:111:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/DoublePres/dut.sv, line:8:1, endln:111:10 |vpiName:incr_d |vpiFullName:work@dut.incr_d |vpiVariables: @@ -1788,7 +1788,7 @@ design: (work@top) |vpiReturn: \_logic_var: |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/DoublePres/dut.sv, line:8:1, endln:111:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/DoublePres/dut.sv, line:8:1, endln:111:10 |vpiStmt: \_begin: (work@dut.incr_d) |vpiParent: @@ -1842,23 +1842,23 @@ design: (work@top) |vpiActual: \_logic_var: (incr_d) |vpiInstance: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/DoublePres/dut.sv, line:8:1, endln:111:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/DoublePres/dut.sv, line:8:1, endln:111:10 |vpiNet: \_logic_net: (work@dut.a), line:10:10, endln:10:11 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/DoublePres/dut.sv, line:8:1, endln:111:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/DoublePres/dut.sv, line:8:1, endln:111:10 |vpiName:a |vpiFullName:work@dut.a |vpiNet: \_logic_net: (work@dut.b), line:10:20, endln:10:21 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/DoublePres/dut.sv, line:8:1, endln:111:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/DoublePres/dut.sv, line:8:1, endln:111:10 |vpiName:b |vpiFullName:work@dut.b |vpiPort: \_port: (a), line:10:10, endln:10:11 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/DoublePres/dut.sv, line:8:1, endln:111:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/DoublePres/dut.sv, line:8:1, endln:111:10 |vpiName:a |vpiDirection:1 |vpiLowConn: @@ -1870,7 +1870,7 @@ design: (work@top) |vpiPort: \_port: (b), line:10:20, endln:10:21 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/DoublePres/dut.sv, line:8:1, endln:111:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/DoublePres/dut.sv, line:8:1, endln:111:10 |vpiName:b |vpiDirection:2 |vpiLowConn: @@ -1880,7 +1880,7 @@ design: (work@top) |vpiTypedef: \_logic_typespec: , line:10:20, endln:10:20 |uhdmallModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/DoublePres/dut.sv, line:1:1, endln:6:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/DoublePres/dut.sv, line:1:1, endln:6:10 |vpiParent: \_design: (work@top) |vpiFullName:work@top @@ -1888,19 +1888,19 @@ design: (work@top) |vpiNet: \_logic_net: (work@top.clk_i), line:1:18, endln:1:23 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/DoublePres/dut.sv, line:1:1, endln:6:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/DoublePres/dut.sv, line:1:1, endln:6:10 |vpiName:clk_i |vpiFullName:work@top.clk_i |vpiNet: \_logic_net: (work@top.b), line:1:32, endln:1:33 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/DoublePres/dut.sv, line:1:1, endln:6:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/DoublePres/dut.sv, line:1:1, endln:6:10 |vpiName:b |vpiFullName:work@top.b |vpiPort: \_port: (clk_i), line:1:18, endln:1:23 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/DoublePres/dut.sv, line:1:1, endln:6:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/DoublePres/dut.sv, line:1:1, endln:6:10 |vpiName:clk_i |vpiDirection:1 |vpiLowConn: @@ -1912,7 +1912,7 @@ design: (work@top) |vpiPort: \_port: (b), line:1:32, endln:1:33 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/DoublePres/dut.sv, line:1:1, endln:6:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/DoublePres/dut.sv, line:1:1, endln:6:10 |vpiName:b |vpiDirection:2 |vpiLowConn: @@ -1922,14 +1922,14 @@ design: (work@top) |vpiTypedef: \_logic_typespec: , line:1:32, endln:1:32 |uhdmtopModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/DoublePres/dut.sv, line:1:1, endln:6:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/DoublePres/dut.sv, line:1:1, endln:6:10 |vpiName:work@top |vpiDefName:work@top |vpiTop:1 |vpiNet: \_logic_net: (work@top.clk_i), line:1:18, endln:1:23 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/DoublePres/dut.sv, line:1:1, endln:6:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/DoublePres/dut.sv, line:1:1, endln:6:10 |vpiTypespec: \_logic_typespec: , line:1:18, endln:1:18 |vpiName:clk_i @@ -1937,7 +1937,7 @@ design: (work@top) |vpiNet: \_logic_net: (work@top.b), line:1:32, endln:1:33 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/DoublePres/dut.sv, line:1:1, endln:6:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/DoublePres/dut.sv, line:1:1, endln:6:10 |vpiTypespec: \_logic_typespec: , line:1:32, endln:1:32 |vpiName:b @@ -1946,7 +1946,7 @@ design: (work@top) |vpiPort: \_port: (clk_i), line:1:18, endln:1:23 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/DoublePres/dut.sv, line:1:1, endln:6:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/DoublePres/dut.sv, line:1:1, endln:6:10 |vpiName:clk_i |vpiDirection:1 |vpiLowConn: @@ -1960,11 +1960,11 @@ design: (work@top) |vpiTypedef: \_logic_typespec: , line:1:18, endln:1:18 |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/DoublePres/dut.sv, line:1:1, endln:6:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/DoublePres/dut.sv, line:1:1, endln:6:10 |vpiPort: \_port: (b), line:1:32, endln:1:33 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/DoublePres/dut.sv, line:1:1, endln:6:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/DoublePres/dut.sv, line:1:1, endln:6:10 |vpiName:b |vpiDirection:2 |vpiLowConn: @@ -1978,17 +1978,17 @@ design: (work@top) |vpiTypedef: \_logic_typespec: , line:1:32, endln:1:32 |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/DoublePres/dut.sv, line:1:1, endln:6:10 - |vpiModule: - \_module: work@dut (work@top.d), file:${SURELOG_DIR}/tests/DoublePres/dut.sv, line:3:3, endln:5:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/DoublePres/dut.sv, line:1:1, endln:6:10 + |vpiModuleInst: + \_module_inst: work@dut (work@top.d), file:${SURELOG_DIR}/tests/DoublePres/dut.sv, line:3:3, endln:5:10 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/DoublePres/dut.sv, line:1:1, endln:6:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/DoublePres/dut.sv, line:1:1, endln:6:10 |vpiName:d |vpiFullName:work@top.d |vpiParameter: \_parameter: (work@top.d.CLKFBOUT_PHASE), line:9:18, endln:9:32 |vpiParent: - \_module: work@dut (work@top.d), file:${SURELOG_DIR}/tests/DoublePres/dut.sv, line:3:3, endln:5:10 + \_module_inst: work@dut (work@top.d), file:${SURELOG_DIR}/tests/DoublePres/dut.sv, line:3:3, endln:5:10 |REAL:1142.500000 |vpiTypespec: \_real_typespec: , line:9:13, endln:9:17 @@ -1999,13 +1999,13 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.d.err), line:12:13, endln:12:16 |vpiParent: - \_module: work@dut (work@top.d), file:${SURELOG_DIR}/tests/DoublePres/dut.sv, line:3:3, endln:5:10 + \_module_inst: work@dut (work@top.d), file:${SURELOG_DIR}/tests/DoublePres/dut.sv, line:3:3, endln:5:10 |vpiName:err |vpiFullName:work@top.d.err |vpiParameter: \_parameter: (work@top.d.f), line:14:11, endln:14:12 |vpiParent: - \_module: work@dut (work@top.d), file:${SURELOG_DIR}/tests/DoublePres/dut.sv, line:3:3, endln:5:10 + \_module_inst: work@dut (work@top.d), file:${SURELOG_DIR}/tests/DoublePres/dut.sv, line:3:3, endln:5:10 |UINT:9 |vpiTypespec: \_int_typespec: @@ -2016,7 +2016,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.d.r), line:15:11, endln:15:12 |vpiParent: - \_module: work@dut (work@top.d), file:${SURELOG_DIR}/tests/DoublePres/dut.sv, line:3:3, endln:5:10 + \_module_inst: work@dut (work@top.d), file:${SURELOG_DIR}/tests/DoublePres/dut.sv, line:3:3, endln:5:10 |REAL:5.700000 |vpiTypespec: \_real_typespec: @@ -2027,103 +2027,103 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.d.average_delay), line:16:11, endln:16:24 |vpiParent: - \_module: work@dut (work@top.d), file:${SURELOG_DIR}/tests/DoublePres/dut.sv, line:3:3, endln:5:10 + \_module_inst: work@dut (work@top.d), file:${SURELOG_DIR}/tests/DoublePres/dut.sv, line:3:3, endln:5:10 |vpiName:average_delay |vpiFullName:work@top.d.average_delay |vpiParameter: \_parameter: (work@top.d.A1), line:18:11, endln:18:13 |vpiParent: - \_module: work@dut (work@top.d), file:${SURELOG_DIR}/tests/DoublePres/dut.sv, line:3:3, endln:5:10 + \_module_inst: work@dut (work@top.d), file:${SURELOG_DIR}/tests/DoublePres/dut.sv, line:3:3, endln:5:10 |vpiName:A1 |vpiFullName:work@top.d.A1 |vpiParameter: \_parameter: (work@top.d.A2), line:20:11, endln:20:13 |vpiParent: - \_module: work@dut (work@top.d), file:${SURELOG_DIR}/tests/DoublePres/dut.sv, line:3:3, endln:5:10 + \_module_inst: work@dut (work@top.d), file:${SURELOG_DIR}/tests/DoublePres/dut.sv, line:3:3, endln:5:10 |vpiName:A2 |vpiFullName:work@top.d.A2 |vpiParameter: \_parameter: (work@top.d.A3), line:22:11, endln:22:13 |vpiParent: - \_module: work@dut (work@top.d), file:${SURELOG_DIR}/tests/DoublePres/dut.sv, line:3:3, endln:5:10 + \_module_inst: work@dut (work@top.d), file:${SURELOG_DIR}/tests/DoublePres/dut.sv, line:3:3, endln:5:10 |vpiName:A3 |vpiFullName:work@top.d.A3 |vpiParameter: \_parameter: (work@top.d.A4), line:24:11, endln:24:13 |vpiParent: - \_module: work@dut (work@top.d), file:${SURELOG_DIR}/tests/DoublePres/dut.sv, line:3:3, endln:5:10 + \_module_inst: work@dut (work@top.d), file:${SURELOG_DIR}/tests/DoublePres/dut.sv, line:3:3, endln:5:10 |vpiName:A4 |vpiFullName:work@top.d.A4 |vpiParameter: \_parameter: (work@top.d.A5), line:26:11, endln:26:13 |vpiParent: - \_module: work@dut (work@top.d), file:${SURELOG_DIR}/tests/DoublePres/dut.sv, line:3:3, endln:5:10 + \_module_inst: work@dut (work@top.d), file:${SURELOG_DIR}/tests/DoublePres/dut.sv, line:3:3, endln:5:10 |vpiName:A5 |vpiFullName:work@top.d.A5 |vpiParameter: \_parameter: (work@top.d.A6), line:28:11, endln:28:13 |vpiParent: - \_module: work@dut (work@top.d), file:${SURELOG_DIR}/tests/DoublePres/dut.sv, line:3:3, endln:5:10 + \_module_inst: work@dut (work@top.d), file:${SURELOG_DIR}/tests/DoublePres/dut.sv, line:3:3, endln:5:10 |vpiName:A6 |vpiFullName:work@top.d.A6 |vpiParameter: \_parameter: (work@top.d.A7), line:30:11, endln:30:13 |vpiParent: - \_module: work@dut (work@top.d), file:${SURELOG_DIR}/tests/DoublePres/dut.sv, line:3:3, endln:5:10 + \_module_inst: work@dut (work@top.d), file:${SURELOG_DIR}/tests/DoublePres/dut.sv, line:3:3, endln:5:10 |vpiName:A7 |vpiFullName:work@top.d.A7 |vpiParameter: \_parameter: (work@top.d.A8), line:32:11, endln:32:13 |vpiParent: - \_module: work@dut (work@top.d), file:${SURELOG_DIR}/tests/DoublePres/dut.sv, line:3:3, endln:5:10 + \_module_inst: work@dut (work@top.d), file:${SURELOG_DIR}/tests/DoublePres/dut.sv, line:3:3, endln:5:10 |vpiName:A8 |vpiFullName:work@top.d.A8 |vpiParameter: \_parameter: (work@top.d.A9), line:34:11, endln:34:13 |vpiParent: - \_module: work@dut (work@top.d), file:${SURELOG_DIR}/tests/DoublePres/dut.sv, line:3:3, endln:5:10 + \_module_inst: work@dut (work@top.d), file:${SURELOG_DIR}/tests/DoublePres/dut.sv, line:3:3, endln:5:10 |vpiName:A9 |vpiFullName:work@top.d.A9 |vpiParameter: \_parameter: (work@top.d.A10), line:36:11, endln:36:14 |vpiParent: - \_module: work@dut (work@top.d), file:${SURELOG_DIR}/tests/DoublePres/dut.sv, line:3:3, endln:5:10 + \_module_inst: work@dut (work@top.d), file:${SURELOG_DIR}/tests/DoublePres/dut.sv, line:3:3, endln:5:10 |vpiName:A10 |vpiFullName:work@top.d.A10 |vpiParameter: \_parameter: (work@top.d.A11), line:38:11, endln:38:14 |vpiParent: - \_module: work@dut (work@top.d), file:${SURELOG_DIR}/tests/DoublePres/dut.sv, line:3:3, endln:5:10 + \_module_inst: work@dut (work@top.d), file:${SURELOG_DIR}/tests/DoublePres/dut.sv, line:3:3, endln:5:10 |vpiName:A11 |vpiFullName:work@top.d.A11 |vpiParameter: \_parameter: (work@top.d.A12), line:40:11, endln:40:14 |vpiParent: - \_module: work@dut (work@top.d), file:${SURELOG_DIR}/tests/DoublePres/dut.sv, line:3:3, endln:5:10 + \_module_inst: work@dut (work@top.d), file:${SURELOG_DIR}/tests/DoublePres/dut.sv, line:3:3, endln:5:10 |vpiName:A12 |vpiFullName:work@top.d.A12 |vpiParameter: \_parameter: (work@top.d.A13), line:42:11, endln:42:14 |vpiParent: - \_module: work@dut (work@top.d), file:${SURELOG_DIR}/tests/DoublePres/dut.sv, line:3:3, endln:5:10 + \_module_inst: work@dut (work@top.d), file:${SURELOG_DIR}/tests/DoublePres/dut.sv, line:3:3, endln:5:10 |vpiName:A13 |vpiFullName:work@top.d.A13 |vpiParameter: \_parameter: (work@top.d.A14), line:44:11, endln:44:14 |vpiParent: - \_module: work@dut (work@top.d), file:${SURELOG_DIR}/tests/DoublePres/dut.sv, line:3:3, endln:5:10 + \_module_inst: work@dut (work@top.d), file:${SURELOG_DIR}/tests/DoublePres/dut.sv, line:3:3, endln:5:10 |vpiName:A14 |vpiFullName:work@top.d.A14 |vpiParameter: \_parameter: (work@top.d.A15), line:53:11, endln:53:14 |vpiParent: - \_module: work@dut (work@top.d), file:${SURELOG_DIR}/tests/DoublePres/dut.sv, line:3:3, endln:5:10 + \_module_inst: work@dut (work@top.d), file:${SURELOG_DIR}/tests/DoublePres/dut.sv, line:3:3, endln:5:10 |vpiName:A15 |vpiFullName:work@top.d.A15 |vpiParamAssign: \_param_assign: , line:9:18, endln:9:43 |vpiParent: - \_module: work@dut (work@top.d), file:${SURELOG_DIR}/tests/DoublePres/dut.sv, line:3:3, endln:5:10 + \_module_inst: work@dut (work@top.d), file:${SURELOG_DIR}/tests/DoublePres/dut.sv, line:3:3, endln:5:10 |vpiOverriden:1 |vpiRhs: \_constant: , line:9:35, endln:9:43 @@ -2138,7 +2138,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:12:13, endln:12:37 |vpiParent: - \_module: work@dut (work@top.d), file:${SURELOG_DIR}/tests/DoublePres/dut.sv, line:3:3, endln:5:10 + \_module_inst: work@dut (work@top.d), file:${SURELOG_DIR}/tests/DoublePres/dut.sv, line:3:3, endln:5:10 |vpiRhs: \_operation: , line:12:19, endln:12:37 |vpiOpType:12 @@ -2163,7 +2163,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:14:11, endln:14:16 |vpiParent: - \_module: work@dut (work@top.d), file:${SURELOG_DIR}/tests/DoublePres/dut.sv, line:3:3, endln:5:10 + \_module_inst: work@dut (work@top.d), file:${SURELOG_DIR}/tests/DoublePres/dut.sv, line:3:3, endln:5:10 |vpiRhs: \_constant: , line:14:15, endln:14:16 |vpiDecompile:9 @@ -2177,7 +2177,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:15:11, endln:15:18 |vpiParent: - \_module: work@dut (work@top.d), file:${SURELOG_DIR}/tests/DoublePres/dut.sv, line:3:3, endln:5:10 + \_module_inst: work@dut (work@top.d), file:${SURELOG_DIR}/tests/DoublePres/dut.sv, line:3:3, endln:5:10 |vpiRhs: \_constant: , line:15:15, endln:15:18 |vpiDecompile:5.700000 @@ -2191,7 +2191,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:16:11, endln:16:36 |vpiParent: - \_module: work@dut (work@top.d), file:${SURELOG_DIR}/tests/DoublePres/dut.sv, line:3:3, endln:5:10 + \_module_inst: work@dut (work@top.d), file:${SURELOG_DIR}/tests/DoublePres/dut.sv, line:3:3, endln:5:10 |vpiRhs: \_constant: , line:16:27, endln:16:36 |vpiDecompile:7.350000 @@ -2203,7 +2203,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:18:11, endln:18:25 |vpiParent: - \_module: work@dut (work@top.d), file:${SURELOG_DIR}/tests/DoublePres/dut.sv, line:3:3, endln:5:10 + \_module_inst: work@dut (work@top.d), file:${SURELOG_DIR}/tests/DoublePres/dut.sv, line:3:3, endln:5:10 |vpiRhs: \_constant: , line:18:16, endln:18:25 |vpiDecompile:0.050000 @@ -2215,7 +2215,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:20:11, endln:20:25 |vpiParent: - \_module: work@dut (work@top.d), file:${SURELOG_DIR}/tests/DoublePres/dut.sv, line:3:3, endln:5:10 + \_module_inst: work@dut (work@top.d), file:${SURELOG_DIR}/tests/DoublePres/dut.sv, line:3:3, endln:5:10 |vpiRhs: \_constant: , line:20:16, endln:20:25 |vpiDecompile:-0.400000 @@ -2227,7 +2227,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:22:11, endln:22:21 |vpiParent: - \_module: work@dut (work@top.d), file:${SURELOG_DIR}/tests/DoublePres/dut.sv, line:3:3, endln:5:10 + \_module_inst: work@dut (work@top.d), file:${SURELOG_DIR}/tests/DoublePres/dut.sv, line:3:3, endln:5:10 |vpiRhs: \_constant: , line:22:16, endln:22:21 |vpiDecompile:-0.600000 @@ -2239,7 +2239,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:24:11, endln:24:21 |vpiParent: - \_module: work@dut (work@top.d), file:${SURELOG_DIR}/tests/DoublePres/dut.sv, line:3:3, endln:5:10 + \_module_inst: work@dut (work@top.d), file:${SURELOG_DIR}/tests/DoublePres/dut.sv, line:3:3, endln:5:10 |vpiRhs: \_constant: , line:24:16, endln:24:21 |vpiDecompile:6 @@ -2251,7 +2251,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:26:11, endln:26:21 |vpiParent: - \_module: work@dut (work@top.d), file:${SURELOG_DIR}/tests/DoublePres/dut.sv, line:3:3, endln:5:10 + \_module_inst: work@dut (work@top.d), file:${SURELOG_DIR}/tests/DoublePres/dut.sv, line:3:3, endln:5:10 |vpiRhs: \_constant: , line:26:16, endln:26:21 |vpiDecompile:-4 @@ -2263,7 +2263,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:28:11, endln:28:21 |vpiParent: - \_module: work@dut (work@top.d), file:${SURELOG_DIR}/tests/DoublePres/dut.sv, line:3:3, endln:5:10 + \_module_inst: work@dut (work@top.d), file:${SURELOG_DIR}/tests/DoublePres/dut.sv, line:3:3, endln:5:10 |vpiRhs: \_constant: , line:28:16, endln:28:21 |vpiDecompile:10 @@ -2275,7 +2275,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:30:11, endln:30:21 |vpiParent: - \_module: work@dut (work@top.d), file:${SURELOG_DIR}/tests/DoublePres/dut.sv, line:3:3, endln:5:10 + \_module_inst: work@dut (work@top.d), file:${SURELOG_DIR}/tests/DoublePres/dut.sv, line:3:3, endln:5:10 |vpiRhs: \_constant: , line:30:16, endln:30:21 |vpiDecompile:2 @@ -2287,7 +2287,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:32:11, endln:32:22 |vpiParent: - \_module: work@dut (work@top.d), file:${SURELOG_DIR}/tests/DoublePres/dut.sv, line:3:3, endln:5:10 + \_module_inst: work@dut (work@top.d), file:${SURELOG_DIR}/tests/DoublePres/dut.sv, line:3:3, endln:5:10 |vpiRhs: \_constant: , line:32:16, endln:32:22 |vpiDecompile:1 @@ -2299,7 +2299,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:34:11, endln:34:26 |vpiParent: - \_module: work@dut (work@top.d), file:${SURELOG_DIR}/tests/DoublePres/dut.sv, line:3:3, endln:5:10 + \_module_inst: work@dut (work@top.d), file:${SURELOG_DIR}/tests/DoublePres/dut.sv, line:3:3, endln:5:10 |vpiRhs: \_constant: , line:34:16, endln:34:26 |vpiDecompile:1.900000 @@ -2311,7 +2311,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:36:11, endln:36:25 |vpiParent: - \_module: work@dut (work@top.d), file:${SURELOG_DIR}/tests/DoublePres/dut.sv, line:3:3, endln:5:10 + \_module_inst: work@dut (work@top.d), file:${SURELOG_DIR}/tests/DoublePres/dut.sv, line:3:3, endln:5:10 |vpiRhs: \_constant: , line:36:17, endln:36:25 |vpiDecompile:0.300000 @@ -2323,7 +2323,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:38:11, endln:38:23 |vpiParent: - \_module: work@dut (work@top.d), file:${SURELOG_DIR}/tests/DoublePres/dut.sv, line:3:3, endln:5:10 + \_module_inst: work@dut (work@top.d), file:${SURELOG_DIR}/tests/DoublePres/dut.sv, line:3:3, endln:5:10 |vpiRhs: \_constant: , line:38:17, endln:38:23 |vpiDecompile:256 @@ -2335,7 +2335,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:40:11, endln:40:25 |vpiParent: - \_module: work@dut (work@top.d), file:${SURELOG_DIR}/tests/DoublePres/dut.sv, line:3:3, endln:5:10 + \_module_inst: work@dut (work@top.d), file:${SURELOG_DIR}/tests/DoublePres/dut.sv, line:3:3, endln:5:10 |vpiRhs: \_constant: , line:40:17, endln:40:25 |vpiDecompile:378.228594 @@ -2347,7 +2347,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:42:11, endln:42:32 |vpiParent: - \_module: work@dut (work@top.d), file:${SURELOG_DIR}/tests/DoublePres/dut.sv, line:3:3, endln:5:10 + \_module_inst: work@dut (work@top.d), file:${SURELOG_DIR}/tests/DoublePres/dut.sv, line:3:3, endln:5:10 |vpiRhs: \_constant: , line:42:18, endln:42:32 |vpiDecompile:378.228594 @@ -2359,7 +2359,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:44:11, endln:44:23 |vpiParent: - \_module: work@dut (work@top.d), file:${SURELOG_DIR}/tests/DoublePres/dut.sv, line:3:3, endln:5:10 + \_module_inst: work@dut (work@top.d), file:${SURELOG_DIR}/tests/DoublePres/dut.sv, line:3:3, endln:5:10 |vpiRhs: \_operation: , line:44:17, endln:44:23 |vpiOpType:13 @@ -2384,7 +2384,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:53:11, endln:53:25 |vpiParent: - \_module: work@dut (work@top.d), file:${SURELOG_DIR}/tests/DoublePres/dut.sv, line:3:3, endln:5:10 + \_module_inst: work@dut (work@top.d), file:${SURELOG_DIR}/tests/DoublePres/dut.sv, line:3:3, endln:5:10 |vpiRhs: \_constant: , line:53:17, endln:53:25 |vpiDecompile:11.100000 @@ -2399,7 +2399,7 @@ design: (work@top) |vpiTaskFunc: \_function: (work@top.d.incr_d), line:46:1, endln:51:12 |vpiParent: - \_module: work@dut (work@top.d), file:${SURELOG_DIR}/tests/DoublePres/dut.sv, line:3:3, endln:5:10 + \_module_inst: work@dut (work@top.d), file:${SURELOG_DIR}/tests/DoublePres/dut.sv, line:3:3, endln:5:10 |vpiName:incr_d |vpiFullName:work@top.d.incr_d |vpiVariables: @@ -2416,7 +2416,7 @@ design: (work@top) |vpiReturn: \_logic_var: |vpiParent: - \_module: work@dut (work@top.d), file:${SURELOG_DIR}/tests/DoublePres/dut.sv, line:3:3, endln:5:10 + \_module_inst: work@dut (work@top.d), file:${SURELOG_DIR}/tests/DoublePres/dut.sv, line:3:3, endln:5:10 |vpiStmt: \_begin: (work@top.d.incr_d) |vpiParent: @@ -2464,11 +2464,11 @@ design: (work@top) |vpiActual: \_integer_var: (work@top.d.incr_d.incr_d), line:47:4, endln:47:11 |vpiInstance: - \_module: work@dut (work@top.d), file:${SURELOG_DIR}/tests/DoublePres/dut.sv, line:3:3, endln:5:10 + \_module_inst: work@dut (work@top.d), file:${SURELOG_DIR}/tests/DoublePres/dut.sv, line:3:3, endln:5:10 |vpiNet: \_logic_net: (work@top.d.a), line:10:10, endln:10:11 |vpiParent: - \_module: work@dut (work@top.d), file:${SURELOG_DIR}/tests/DoublePres/dut.sv, line:3:3, endln:5:10 + \_module_inst: work@dut (work@top.d), file:${SURELOG_DIR}/tests/DoublePres/dut.sv, line:3:3, endln:5:10 |vpiTypespec: \_logic_typespec: , line:10:10, endln:10:10 |vpiName:a @@ -2476,17 +2476,17 @@ design: (work@top) |vpiNet: \_logic_net: (work@top.d.b), line:10:20, endln:10:21 |vpiParent: - \_module: work@dut (work@top.d), file:${SURELOG_DIR}/tests/DoublePres/dut.sv, line:3:3, endln:5:10 + \_module_inst: work@dut (work@top.d), file:${SURELOG_DIR}/tests/DoublePres/dut.sv, line:3:3, endln:5:10 |vpiTypespec: \_logic_typespec: , line:10:20, endln:10:20 |vpiName:b |vpiFullName:work@top.d.b |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/DoublePres/dut.sv, line:1:1, endln:6:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/DoublePres/dut.sv, line:1:1, endln:6:10 |vpiPort: \_port: (a), line:10:10, endln:10:11 |vpiParent: - \_module: work@dut (work@top.d), file:${SURELOG_DIR}/tests/DoublePres/dut.sv, line:3:3, endln:5:10 + \_module_inst: work@dut (work@top.d), file:${SURELOG_DIR}/tests/DoublePres/dut.sv, line:3:3, endln:5:10 |vpiName:a |vpiDirection:1 |vpiHighConn: @@ -2508,11 +2508,11 @@ design: (work@top) |vpiTypedef: \_logic_typespec: , line:10:10, endln:10:10 |vpiInstance: - \_module: work@dut (work@top.d), file:${SURELOG_DIR}/tests/DoublePres/dut.sv, line:3:3, endln:5:10 + \_module_inst: work@dut (work@top.d), file:${SURELOG_DIR}/tests/DoublePres/dut.sv, line:3:3, endln:5:10 |vpiPort: \_port: (b), line:10:20, endln:10:21 |vpiParent: - \_module: work@dut (work@top.d), file:${SURELOG_DIR}/tests/DoublePres/dut.sv, line:3:3, endln:5:10 + \_module_inst: work@dut (work@top.d), file:${SURELOG_DIR}/tests/DoublePres/dut.sv, line:3:3, endln:5:10 |vpiName:b |vpiDirection:2 |vpiHighConn: @@ -2534,11 +2534,11 @@ design: (work@top) |vpiTypedef: \_logic_typespec: , line:10:20, endln:10:20 |vpiInstance: - \_module: work@dut (work@top.d), file:${SURELOG_DIR}/tests/DoublePres/dut.sv, line:3:3, endln:5:10 + \_module_inst: work@dut (work@top.d), file:${SURELOG_DIR}/tests/DoublePres/dut.sv, line:3:3, endln:5:10 |vpiGenScopeArray: \_gen_scope_array: (work@top.d.genblk1), line:55:4, endln:57:7 |vpiParent: - \_module: work@dut (work@top.d), file:${SURELOG_DIR}/tests/DoublePres/dut.sv, line:3:3, endln:5:10 + \_module_inst: work@dut (work@top.d), file:${SURELOG_DIR}/tests/DoublePres/dut.sv, line:3:3, endln:5:10 |vpiName:genblk1 |vpiFullName:work@top.d.genblk1 |vpiGenScope: @@ -2546,8 +2546,8 @@ design: (work@top) |vpiParent: \_gen_scope_array: (work@top.d.genblk1), line:55:4, endln:57:7 |vpiFullName:work@top.d.genblk1 - |vpiModule: - \_module: work@top.d.genblk1::GOOD (work@top.d.genblk1.good1), file:${SURELOG_DIR}/tests/DoublePres/dut.sv, line:56:7, endln:56:20 + |vpiModuleInst: + \_module_inst: work@top.d.genblk1::GOOD (work@top.d.genblk1.good1), file:${SURELOG_DIR}/tests/DoublePres/dut.sv, line:56:7, endln:56:20 |vpiParent: \_gen_scope: (work@top.d.genblk1) |vpiName:good1 @@ -2556,7 +2556,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.d.genblk2), line:59:4, endln:61:7 |vpiParent: - \_module: work@dut (work@top.d), file:${SURELOG_DIR}/tests/DoublePres/dut.sv, line:3:3, endln:5:10 + \_module_inst: work@dut (work@top.d), file:${SURELOG_DIR}/tests/DoublePres/dut.sv, line:3:3, endln:5:10 |vpiName:genblk2 |vpiFullName:work@top.d.genblk2 |vpiGenScope: @@ -2564,8 +2564,8 @@ design: (work@top) |vpiParent: \_gen_scope_array: (work@top.d.genblk2), line:59:4, endln:61:7 |vpiFullName:work@top.d.genblk2 - |vpiModule: - \_module: work@top.d.genblk2::GOOD (work@top.d.genblk2.good2), file:${SURELOG_DIR}/tests/DoublePres/dut.sv, line:60:7, endln:60:20 + |vpiModuleInst: + \_module_inst: work@top.d.genblk2::GOOD (work@top.d.genblk2.good2), file:${SURELOG_DIR}/tests/DoublePres/dut.sv, line:60:7, endln:60:20 |vpiParent: \_gen_scope: (work@top.d.genblk2) |vpiName:good2 @@ -2574,7 +2574,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.d.genblk3), line:63:4, endln:65:7 |vpiParent: - \_module: work@dut (work@top.d), file:${SURELOG_DIR}/tests/DoublePres/dut.sv, line:3:3, endln:5:10 + \_module_inst: work@dut (work@top.d), file:${SURELOG_DIR}/tests/DoublePres/dut.sv, line:3:3, endln:5:10 |vpiName:genblk3 |vpiFullName:work@top.d.genblk3 |vpiGenScope: @@ -2582,8 +2582,8 @@ design: (work@top) |vpiParent: \_gen_scope_array: (work@top.d.genblk3), line:63:4, endln:65:7 |vpiFullName:work@top.d.genblk3 - |vpiModule: - \_module: work@top.d.genblk3::GOOD (work@top.d.genblk3.good3), file:${SURELOG_DIR}/tests/DoublePres/dut.sv, line:64:7, endln:64:20 + |vpiModuleInst: + \_module_inst: work@top.d.genblk3::GOOD (work@top.d.genblk3.good3), file:${SURELOG_DIR}/tests/DoublePres/dut.sv, line:64:7, endln:64:20 |vpiParent: \_gen_scope: (work@top.d.genblk3) |vpiName:good3 @@ -2592,7 +2592,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.d.genblk4), line:67:4, endln:69:7 |vpiParent: - \_module: work@dut (work@top.d), file:${SURELOG_DIR}/tests/DoublePres/dut.sv, line:3:3, endln:5:10 + \_module_inst: work@dut (work@top.d), file:${SURELOG_DIR}/tests/DoublePres/dut.sv, line:3:3, endln:5:10 |vpiName:genblk4 |vpiFullName:work@top.d.genblk4 |vpiGenScope: @@ -2600,8 +2600,8 @@ design: (work@top) |vpiParent: \_gen_scope_array: (work@top.d.genblk4), line:67:4, endln:69:7 |vpiFullName:work@top.d.genblk4 - |vpiModule: - \_module: work@top.d.genblk4::GOOD (work@top.d.genblk4.good4), file:${SURELOG_DIR}/tests/DoublePres/dut.sv, line:68:7, endln:68:20 + |vpiModuleInst: + \_module_inst: work@top.d.genblk4::GOOD (work@top.d.genblk4.good4), file:${SURELOG_DIR}/tests/DoublePres/dut.sv, line:68:7, endln:68:20 |vpiParent: \_gen_scope: (work@top.d.genblk4) |vpiName:good4 @@ -2610,7 +2610,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.d.genblk5), line:71:4, endln:73:7 |vpiParent: - \_module: work@dut (work@top.d), file:${SURELOG_DIR}/tests/DoublePres/dut.sv, line:3:3, endln:5:10 + \_module_inst: work@dut (work@top.d), file:${SURELOG_DIR}/tests/DoublePres/dut.sv, line:3:3, endln:5:10 |vpiName:genblk5 |vpiFullName:work@top.d.genblk5 |vpiGenScope: @@ -2618,8 +2618,8 @@ design: (work@top) |vpiParent: \_gen_scope_array: (work@top.d.genblk5), line:71:4, endln:73:7 |vpiFullName:work@top.d.genblk5 - |vpiModule: - \_module: work@top.d.genblk5::GOOD (work@top.d.genblk5.good5), file:${SURELOG_DIR}/tests/DoublePres/dut.sv, line:72:7, endln:72:20 + |vpiModuleInst: + \_module_inst: work@top.d.genblk5::GOOD (work@top.d.genblk5.good5), file:${SURELOG_DIR}/tests/DoublePres/dut.sv, line:72:7, endln:72:20 |vpiParent: \_gen_scope: (work@top.d.genblk5) |vpiName:good5 @@ -2628,7 +2628,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.d.genblk6), line:75:4, endln:77:7 |vpiParent: - \_module: work@dut (work@top.d), file:${SURELOG_DIR}/tests/DoublePres/dut.sv, line:3:3, endln:5:10 + \_module_inst: work@dut (work@top.d), file:${SURELOG_DIR}/tests/DoublePres/dut.sv, line:3:3, endln:5:10 |vpiName:genblk6 |vpiFullName:work@top.d.genblk6 |vpiGenScope: @@ -2636,8 +2636,8 @@ design: (work@top) |vpiParent: \_gen_scope_array: (work@top.d.genblk6), line:75:4, endln:77:7 |vpiFullName:work@top.d.genblk6 - |vpiModule: - \_module: work@top.d.genblk6::GOOD (work@top.d.genblk6.good6), file:${SURELOG_DIR}/tests/DoublePres/dut.sv, line:76:7, endln:76:20 + |vpiModuleInst: + \_module_inst: work@top.d.genblk6::GOOD (work@top.d.genblk6.good6), file:${SURELOG_DIR}/tests/DoublePres/dut.sv, line:76:7, endln:76:20 |vpiParent: \_gen_scope: (work@top.d.genblk6) |vpiName:good6 @@ -2646,7 +2646,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.d.genblk7), line:79:4, endln:81:7 |vpiParent: - \_module: work@dut (work@top.d), file:${SURELOG_DIR}/tests/DoublePres/dut.sv, line:3:3, endln:5:10 + \_module_inst: work@dut (work@top.d), file:${SURELOG_DIR}/tests/DoublePres/dut.sv, line:3:3, endln:5:10 |vpiName:genblk7 |vpiFullName:work@top.d.genblk7 |vpiGenScope: @@ -2654,8 +2654,8 @@ design: (work@top) |vpiParent: \_gen_scope_array: (work@top.d.genblk7), line:79:4, endln:81:7 |vpiFullName:work@top.d.genblk7 - |vpiModule: - \_module: work@top.d.genblk7::GOOD (work@top.d.genblk7.good7), file:${SURELOG_DIR}/tests/DoublePres/dut.sv, line:80:7, endln:80:20 + |vpiModuleInst: + \_module_inst: work@top.d.genblk7::GOOD (work@top.d.genblk7.good7), file:${SURELOG_DIR}/tests/DoublePres/dut.sv, line:80:7, endln:80:20 |vpiParent: \_gen_scope: (work@top.d.genblk7) |vpiName:good7 @@ -2664,7 +2664,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.d.genblk8), line:83:2, endln:85:5 |vpiParent: - \_module: work@dut (work@top.d), file:${SURELOG_DIR}/tests/DoublePres/dut.sv, line:3:3, endln:5:10 + \_module_inst: work@dut (work@top.d), file:${SURELOG_DIR}/tests/DoublePres/dut.sv, line:3:3, endln:5:10 |vpiName:genblk8 |vpiFullName:work@top.d.genblk8 |vpiGenScope: @@ -2672,8 +2672,8 @@ design: (work@top) |vpiParent: \_gen_scope_array: (work@top.d.genblk8), line:83:2, endln:85:5 |vpiFullName:work@top.d.genblk8 - |vpiModule: - \_module: work@top.d.genblk8::GOOD (work@top.d.genblk8.good8), file:${SURELOG_DIR}/tests/DoublePres/dut.sv, line:84:7, endln:84:20 + |vpiModuleInst: + \_module_inst: work@top.d.genblk8::GOOD (work@top.d.genblk8.good8), file:${SURELOG_DIR}/tests/DoublePres/dut.sv, line:84:7, endln:84:20 |vpiParent: \_gen_scope: (work@top.d.genblk8) |vpiName:good8 @@ -2682,7 +2682,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.d.genblk9), line:87:3, endln:89:6 |vpiParent: - \_module: work@dut (work@top.d), file:${SURELOG_DIR}/tests/DoublePres/dut.sv, line:3:3, endln:5:10 + \_module_inst: work@dut (work@top.d), file:${SURELOG_DIR}/tests/DoublePres/dut.sv, line:3:3, endln:5:10 |vpiName:genblk9 |vpiFullName:work@top.d.genblk9 |vpiGenScope: @@ -2690,8 +2690,8 @@ design: (work@top) |vpiParent: \_gen_scope_array: (work@top.d.genblk9), line:87:3, endln:89:6 |vpiFullName:work@top.d.genblk9 - |vpiModule: - \_module: work@top.d.genblk9::GOOD (work@top.d.genblk9.good9), file:${SURELOG_DIR}/tests/DoublePres/dut.sv, line:88:6, endln:88:19 + |vpiModuleInst: + \_module_inst: work@top.d.genblk9::GOOD (work@top.d.genblk9.good9), file:${SURELOG_DIR}/tests/DoublePres/dut.sv, line:88:6, endln:88:19 |vpiParent: \_gen_scope: (work@top.d.genblk9) |vpiName:good9 @@ -2700,7 +2700,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.d.genblk10), line:91:3, endln:93:6 |vpiParent: - \_module: work@dut (work@top.d), file:${SURELOG_DIR}/tests/DoublePres/dut.sv, line:3:3, endln:5:10 + \_module_inst: work@dut (work@top.d), file:${SURELOG_DIR}/tests/DoublePres/dut.sv, line:3:3, endln:5:10 |vpiName:genblk10 |vpiFullName:work@top.d.genblk10 |vpiGenScope: @@ -2708,8 +2708,8 @@ design: (work@top) |vpiParent: \_gen_scope_array: (work@top.d.genblk10), line:91:3, endln:93:6 |vpiFullName:work@top.d.genblk10 - |vpiModule: - \_module: work@top.d.genblk10::GOOD (work@top.d.genblk10.good10), file:${SURELOG_DIR}/tests/DoublePres/dut.sv, line:92:6, endln:92:20 + |vpiModuleInst: + \_module_inst: work@top.d.genblk10::GOOD (work@top.d.genblk10.good10), file:${SURELOG_DIR}/tests/DoublePres/dut.sv, line:92:6, endln:92:20 |vpiParent: \_gen_scope: (work@top.d.genblk10) |vpiName:good10 @@ -2718,7 +2718,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.d.genblk11), line:95:3, endln:97:6 |vpiParent: - \_module: work@dut (work@top.d), file:${SURELOG_DIR}/tests/DoublePres/dut.sv, line:3:3, endln:5:10 + \_module_inst: work@dut (work@top.d), file:${SURELOG_DIR}/tests/DoublePres/dut.sv, line:3:3, endln:5:10 |vpiName:genblk11 |vpiFullName:work@top.d.genblk11 |vpiGenScope: @@ -2726,8 +2726,8 @@ design: (work@top) |vpiParent: \_gen_scope_array: (work@top.d.genblk11), line:95:3, endln:97:6 |vpiFullName:work@top.d.genblk11 - |vpiModule: - \_module: work@top.d.genblk11::GOOD (work@top.d.genblk11.good11), file:${SURELOG_DIR}/tests/DoublePres/dut.sv, line:96:6, endln:96:20 + |vpiModuleInst: + \_module_inst: work@top.d.genblk11::GOOD (work@top.d.genblk11.good11), file:${SURELOG_DIR}/tests/DoublePres/dut.sv, line:96:6, endln:96:20 |vpiParent: \_gen_scope: (work@top.d.genblk11) |vpiName:good11 @@ -2736,7 +2736,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.d.genblk12), line:99:3, endln:101:6 |vpiParent: - \_module: work@dut (work@top.d), file:${SURELOG_DIR}/tests/DoublePres/dut.sv, line:3:3, endln:5:10 + \_module_inst: work@dut (work@top.d), file:${SURELOG_DIR}/tests/DoublePres/dut.sv, line:3:3, endln:5:10 |vpiName:genblk12 |vpiFullName:work@top.d.genblk12 |vpiGenScope: @@ -2744,8 +2744,8 @@ design: (work@top) |vpiParent: \_gen_scope_array: (work@top.d.genblk12), line:99:3, endln:101:6 |vpiFullName:work@top.d.genblk12 - |vpiModule: - \_module: work@top.d.genblk12::GOOD (work@top.d.genblk12.good12), file:${SURELOG_DIR}/tests/DoublePres/dut.sv, line:100:6, endln:100:20 + |vpiModuleInst: + \_module_inst: work@top.d.genblk12::GOOD (work@top.d.genblk12.good12), file:${SURELOG_DIR}/tests/DoublePres/dut.sv, line:100:6, endln:100:20 |vpiParent: \_gen_scope: (work@top.d.genblk12) |vpiName:good12 @@ -2754,7 +2754,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.d.genblk13), line:103:3, endln:105:6 |vpiParent: - \_module: work@dut (work@top.d), file:${SURELOG_DIR}/tests/DoublePres/dut.sv, line:3:3, endln:5:10 + \_module_inst: work@dut (work@top.d), file:${SURELOG_DIR}/tests/DoublePres/dut.sv, line:3:3, endln:5:10 |vpiName:genblk13 |vpiFullName:work@top.d.genblk13 |vpiGenScope: @@ -2762,8 +2762,8 @@ design: (work@top) |vpiParent: \_gen_scope_array: (work@top.d.genblk13), line:103:3, endln:105:6 |vpiFullName:work@top.d.genblk13 - |vpiModule: - \_module: work@top.d.genblk13::GOOD (work@top.d.genblk13.good13), file:${SURELOG_DIR}/tests/DoublePres/dut.sv, line:104:6, endln:104:20 + |vpiModuleInst: + \_module_inst: work@top.d.genblk13::GOOD (work@top.d.genblk13.good13), file:${SURELOG_DIR}/tests/DoublePres/dut.sv, line:104:6, endln:104:20 |vpiParent: \_gen_scope: (work@top.d.genblk13) |vpiName:good13 @@ -2772,7 +2772,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.d.genblk14), line:107:2, endln:109:6 |vpiParent: - \_module: work@dut (work@top.d), file:${SURELOG_DIR}/tests/DoublePres/dut.sv, line:3:3, endln:5:10 + \_module_inst: work@dut (work@top.d), file:${SURELOG_DIR}/tests/DoublePres/dut.sv, line:3:3, endln:5:10 |vpiName:genblk14 |vpiFullName:work@top.d.genblk14 |vpiGenScope: @@ -2780,8 +2780,8 @@ design: (work@top) |vpiParent: \_gen_scope_array: (work@top.d.genblk14), line:107:2, endln:109:6 |vpiFullName:work@top.d.genblk14 - |vpiModule: - \_module: work@top.d.genblk14::GOOD (work@top.d.genblk14.good15), file:${SURELOG_DIR}/tests/DoublePres/dut.sv, line:108:6, endln:108:20 + |vpiModuleInst: + \_module_inst: work@top.d.genblk14::GOOD (work@top.d.genblk14.good15), file:${SURELOG_DIR}/tests/DoublePres/dut.sv, line:108:6, endln:108:20 |vpiParent: \_gen_scope: (work@top.d.genblk14) |vpiName:good15 diff --git a/tests/DpiChandle/DpiChandle.log b/tests/DpiChandle/DpiChandle.log index 946c1a210d..1836b8418b 100644 --- a/tests/DpiChandle/DpiChandle.log +++ b/tests/DpiChandle/DpiChandle.log @@ -338,7 +338,7 @@ int_typespec 9 int_var 4 io_decl 12 logic_var 1 -module 2 +module_inst 2 package 2 task 9 === UHDM Object Stats End === @@ -360,7 +360,7 @@ int_typespec 9 int_var 4 io_decl 24 logic_var 1 -module 2 +module_inst 2 package 2 task 18 === UHDM Object Stats End === @@ -852,7 +852,7 @@ design: (work@top) \_int_typespec: |vpiSigned:1 |uhdmallModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/DpiChandle/dut.sv, line:1:1, endln:7:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/DpiChandle/dut.sv, line:1:1, endln:7:10 |vpiParent: \_design: (work@top) |vpiFullName:work@top @@ -860,7 +860,7 @@ design: (work@top) |vpiTaskFunc: \_function: (work@top.test_output), line:2:4, endln:3:28 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/DpiChandle/dut.sv, line:1:1, endln:7:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/DpiChandle/dut.sv, line:1:1, endln:7:10 |vpiName:test_output |vpiFullName:work@top.test_output |vpiAccessType:4 @@ -871,20 +871,20 @@ design: (work@top) |vpiTypespec: \_chandle_typespec: , line:3:6, endln:3:13 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/DpiChandle/dut.sv, line:1:1, endln:7:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/DpiChandle/dut.sv, line:1:1, endln:7:10 |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/DpiChandle/dut.sv, line:1:1, endln:7:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/DpiChandle/dut.sv, line:1:1, endln:7:10 |vpiTaskFunc: \_function: (work@top.test_input), line:5:4, endln:6:40 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/DpiChandle/dut.sv, line:1:1, endln:7:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/DpiChandle/dut.sv, line:1:1, endln:7:10 |vpiName:test_input |vpiFullName:work@top.test_input |vpiAccessType:4 |vpiVisibility:1 |vpiDPICStr:2 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/DpiChandle/dut.sv, line:1:1, endln:7:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/DpiChandle/dut.sv, line:1:1, endln:7:10 |vpiIODecl: \_io_decl: (in), line:6:36, endln:6:38 |vpiDirection:1 @@ -892,16 +892,16 @@ design: (work@top) |vpiTypedef: \_chandle_typespec: , line:6:28, endln:6:35 |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/DpiChandle/dut.sv, line:1:1, endln:7:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/DpiChandle/dut.sv, line:1:1, endln:7:10 |uhdmtopModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/DpiChandle/dut.sv, line:1:1, endln:7:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/DpiChandle/dut.sv, line:1:1, endln:7:10 |vpiName:work@top |vpiDefName:work@top |vpiTop:1 |vpiTaskFunc: \_function: (work@top.test_output), line:2:4, endln:3:28 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/DpiChandle/dut.sv, line:1:1, endln:7:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/DpiChandle/dut.sv, line:1:1, endln:7:10 |vpiName:test_output |vpiFullName:work@top.test_output |vpiAccessType:4 @@ -910,20 +910,20 @@ design: (work@top) |vpiReturn: \_chandle_var: , line:3:6, endln:3:13 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/DpiChandle/dut.sv, line:1:1, endln:7:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/DpiChandle/dut.sv, line:1:1, endln:7:10 |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/DpiChandle/dut.sv, line:1:1, endln:7:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/DpiChandle/dut.sv, line:1:1, endln:7:10 |vpiTaskFunc: \_function: (work@top.test_input), line:5:4, endln:6:40 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/DpiChandle/dut.sv, line:1:1, endln:7:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/DpiChandle/dut.sv, line:1:1, endln:7:10 |vpiName:test_input |vpiFullName:work@top.test_input |vpiAccessType:4 |vpiVisibility:1 |vpiDPICStr:2 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/DpiChandle/dut.sv, line:1:1, endln:7:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/DpiChandle/dut.sv, line:1:1, endln:7:10 |vpiIODecl: \_io_decl: (in), line:6:36, endln:6:38 |vpiParent: @@ -933,7 +933,7 @@ design: (work@top) |vpiTypedef: \_chandle_typespec: , line:6:28, endln:6:35 |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/DpiChandle/dut.sv, line:1:1, endln:7:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/DpiChandle/dut.sv, line:1:1, endln:7:10 |vpiTopModule:1 =================== [ FATAL] : 0 diff --git a/tests/DpiFunc/DpiFunc.log b/tests/DpiFunc/DpiFunc.log index b74ce3492d..90a388103a 100644 --- a/tests/DpiFunc/DpiFunc.log +++ b/tests/DpiFunc/DpiFunc.log @@ -339,7 +339,7 @@ int_typespec 10 int_var 5 io_decl 11 logic_var 1 -module 2 +module_inst 2 package 2 return_stmt 1 task 9 @@ -360,7 +360,7 @@ int_typespec 10 int_var 5 io_decl 22 logic_var 1 -module 2 +module_inst 2 package 2 return_stmt 2 task 18 @@ -853,7 +853,7 @@ design: (work@top) \_int_typespec: |vpiSigned:1 |uhdmallModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/DpiFunc/dut.sv, line:1:1, endln:6:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/DpiFunc/dut.sv, line:1:1, endln:6:10 |vpiParent: \_design: (work@top) |vpiFullName:work@top @@ -861,7 +861,7 @@ design: (work@top) |vpiTaskFunc: \_function: (work@top.func_1), line:2:3, endln:2:34 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/DpiFunc/dut.sv, line:1:1, endln:6:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/DpiFunc/dut.sv, line:1:1, endln:6:10 |vpiName:func_1 |vpiFullName:work@top.func_1 |vpiAccessType:3 @@ -874,7 +874,7 @@ design: (work@top) |vpiSigned:1 |vpiSigned:1 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/DpiFunc/dut.sv, line:1:1, endln:6:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/DpiFunc/dut.sv, line:1:1, endln:6:10 |vpiStmt: \_return_stmt: , line:4:5, endln:4:11 |vpiParent: @@ -888,16 +888,16 @@ design: (work@top) |UINT:1 |vpiConstType:9 |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/DpiFunc/dut.sv, line:1:1, endln:6:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/DpiFunc/dut.sv, line:1:1, endln:6:10 |uhdmtopModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/DpiFunc/dut.sv, line:1:1, endln:6:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/DpiFunc/dut.sv, line:1:1, endln:6:10 |vpiName:work@top |vpiDefName:work@top |vpiTop:1 |vpiTaskFunc: \_function: (work@top.func_1), line:2:3, endln:2:34 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/DpiFunc/dut.sv, line:1:1, endln:6:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/DpiFunc/dut.sv, line:1:1, endln:6:10 |vpiName:func_1 |vpiFullName:work@top.func_1 |vpiAccessType:3 @@ -906,7 +906,7 @@ design: (work@top) |vpiReturn: \_int_var: , line:3:12, endln:3:15 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/DpiFunc/dut.sv, line:1:1, endln:6:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/DpiFunc/dut.sv, line:1:1, endln:6:10 |vpiStmt: \_return_stmt: , line:4:5, endln:4:11 |vpiParent: @@ -914,7 +914,7 @@ design: (work@top) |vpiCondition: \_constant: , line:4:12, endln:4:13 |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/DpiFunc/dut.sv, line:1:1, endln:6:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/DpiFunc/dut.sv, line:1:1, endln:6:10 |vpiTopModule:1 =================== [ FATAL] : 0 diff --git a/tests/DpiTask/DpiTask.log b/tests/DpiTask/DpiTask.log index f222d04fc0..bc15ece1ea 100644 --- a/tests/DpiTask/DpiTask.log +++ b/tests/DpiTask/DpiTask.log @@ -349,7 +349,7 @@ int_typespec 10 int_var 4 io_decl 12 logic_var 1 -module 2 +module_inst 2 package 2 ref_obj 1 task 9 @@ -371,7 +371,7 @@ int_typespec 10 int_var 4 io_decl 24 logic_var 1 -module 2 +module_inst 2 package 2 ref_obj 2 task 18 @@ -864,7 +864,7 @@ design: (work@top) \_int_typespec: |vpiSigned:1 |uhdmallModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/DpiTask/dut.sv, line:1:1, endln:8:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/DpiTask/dut.sv, line:1:1, endln:8:10 |vpiParent: \_design: (work@top) |vpiFullName:work@top @@ -872,14 +872,14 @@ design: (work@top) |vpiTaskFunc: \_function: (work@top.task_1), line:4:3, endln:6:10 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/DpiTask/dut.sv, line:1:1, endln:8:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/DpiTask/dut.sv, line:1:1, endln:8:10 |vpiName:task_1 |vpiFullName:work@top.task_1 |vpiAccessType:3 |vpiVisibility:1 |vpiDPICStr:2 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/DpiTask/dut.sv, line:1:1, endln:8:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/DpiTask/dut.sv, line:1:1, endln:8:10 |vpiIODecl: \_io_decl: (ret), line:4:26, endln:4:29 |vpiDirection:2 @@ -910,23 +910,23 @@ design: (work@top) |vpiActual: \_io_decl: (ret), line:4:26, endln:4:29 |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/DpiTask/dut.sv, line:1:1, endln:8:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/DpiTask/dut.sv, line:1:1, endln:8:10 |uhdmtopModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/DpiTask/dut.sv, line:1:1, endln:8:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/DpiTask/dut.sv, line:1:1, endln:8:10 |vpiName:work@top |vpiDefName:work@top |vpiTop:1 |vpiTaskFunc: \_function: (work@top.task_1), line:4:3, endln:6:10 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/DpiTask/dut.sv, line:1:1, endln:8:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/DpiTask/dut.sv, line:1:1, endln:8:10 |vpiName:task_1 |vpiFullName:work@top.task_1 |vpiAccessType:3 |vpiVisibility:1 |vpiDPICStr:2 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/DpiTask/dut.sv, line:1:1, endln:8:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/DpiTask/dut.sv, line:1:1, endln:8:10 |vpiIODecl: \_io_decl: (ret), line:4:26, endln:4:29 |vpiParent: @@ -952,7 +952,7 @@ design: (work@top) |vpiActual: \_io_decl: (ret), line:4:26, endln:4:29 |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/DpiTask/dut.sv, line:1:1, endln:8:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/DpiTask/dut.sv, line:1:1, endln:8:10 |vpiTopModule:1 =================== [ FATAL] : 0 diff --git a/tests/DynArrayKind/DynArrayKind.log b/tests/DynArrayKind/DynArrayKind.log index 2717732544..bce5f4dc8b 100644 --- a/tests/DynArrayKind/DynArrayKind.log +++ b/tests/DynArrayKind/DynArrayKind.log @@ -186,7 +186,7 @@ design 1 int_typespec 10 int_var 7 logic_net 7 -module 3 +module_inst 3 range 11 string_typespec 1 === UHDM Object Stats End === @@ -200,7 +200,7 @@ design 1 int_typespec 10 int_var 7 logic_net 7 -module 3 +module_inst 3 range 11 string_typespec 1 === UHDM Object Stats End === @@ -217,7 +217,7 @@ design: (work@top) |vpiElaborated:1 |vpiName:work@top |uhdmallModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/DynArrayKind/dut.sv, line:1:1, endln:9:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/DynArrayKind/dut.sv, line:1:1, endln:9:10 |vpiParent: \_design: (work@top) |vpiFullName:work@top @@ -225,52 +225,52 @@ design: (work@top) |vpiNet: \_logic_net: (work@top.dynamic1), line:2:8, endln:2:16 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/DynArrayKind/dut.sv, line:1:1, endln:9:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/DynArrayKind/dut.sv, line:1:1, endln:9:10 |vpiName:dynamic1 |vpiFullName:work@top.dynamic1 |vpiNet: \_logic_net: (work@top.dynamic2), line:3:8, endln:3:16 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/DynArrayKind/dut.sv, line:1:1, endln:9:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/DynArrayKind/dut.sv, line:1:1, endln:9:10 |vpiName:dynamic2 |vpiFullName:work@top.dynamic2 |vpiNet: \_logic_net: (work@top.dynamic3), line:4:8, endln:4:16 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/DynArrayKind/dut.sv, line:1:1, endln:9:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/DynArrayKind/dut.sv, line:1:1, endln:9:10 |vpiName:dynamic3 |vpiFullName:work@top.dynamic3 |vpiNet: \_logic_net: (work@top.dynamic4), line:5:8, endln:5:16 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/DynArrayKind/dut.sv, line:1:1, endln:9:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/DynArrayKind/dut.sv, line:1:1, endln:9:10 |vpiName:dynamic4 |vpiFullName:work@top.dynamic4 |vpiNet: \_logic_net: (work@top.assoc), line:6:8, endln:6:13 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/DynArrayKind/dut.sv, line:1:1, endln:9:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/DynArrayKind/dut.sv, line:1:1, endln:9:10 |vpiName:assoc |vpiFullName:work@top.assoc |vpiNet: \_logic_net: (work@top.assoc_string), line:7:8, endln:7:20 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/DynArrayKind/dut.sv, line:1:1, endln:9:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/DynArrayKind/dut.sv, line:1:1, endln:9:10 |vpiName:assoc_string |vpiFullName:work@top.assoc_string |vpiNet: \_logic_net: (work@top.queue), line:8:8, endln:8:13 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/DynArrayKind/dut.sv, line:1:1, endln:9:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/DynArrayKind/dut.sv, line:1:1, endln:9:10 |vpiName:queue |vpiFullName:work@top.queue |uhdmtopModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/DynArrayKind/dut.sv, line:1:1, endln:9:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/DynArrayKind/dut.sv, line:1:1, endln:9:10 |vpiName:work@top |vpiVariables: \_array_var: (work@top.dynamic1), line:2:8, endln:2:19 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/DynArrayKind/dut.sv, line:1:1, endln:9:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/DynArrayKind/dut.sv, line:1:1, endln:9:10 |vpiSize:1 |vpiTypespec: \_array_typespec: @@ -290,7 +290,7 @@ design: (work@top) |vpiVariables: \_array_var: (work@top.dynamic2), line:3:8, endln:3:19 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/DynArrayKind/dut.sv, line:1:1, endln:9:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/DynArrayKind/dut.sv, line:1:1, endln:9:10 |vpiSize:2 |vpiTypespec: \_array_typespec: @@ -328,7 +328,7 @@ design: (work@top) |vpiVariables: \_array_var: (work@top.dynamic3), line:4:8, endln:4:22 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/DynArrayKind/dut.sv, line:1:1, endln:9:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/DynArrayKind/dut.sv, line:1:1, endln:9:10 |vpiSize:2 |vpiTypespec: \_array_typespec: @@ -363,7 +363,7 @@ design: (work@top) |vpiVariables: \_array_var: (work@top.dynamic4), line:5:8, endln:5:22 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/DynArrayKind/dut.sv, line:1:1, endln:9:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/DynArrayKind/dut.sv, line:1:1, endln:9:10 |vpiSize:6 |vpiTypespec: \_array_typespec: @@ -416,7 +416,7 @@ design: (work@top) |vpiVariables: \_array_var: (work@top.assoc), line:6:8, endln:6:19 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/DynArrayKind/dut.sv, line:1:1, endln:9:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/DynArrayKind/dut.sv, line:1:1, endln:9:10 |vpiSize:1 |vpiTypespec: \_array_typespec: @@ -439,7 +439,7 @@ design: (work@top) |vpiVariables: \_array_var: (work@top.assoc_string), line:7:8, endln:7:29 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/DynArrayKind/dut.sv, line:1:1, endln:9:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/DynArrayKind/dut.sv, line:1:1, endln:9:10 |vpiSize:1 |vpiTypespec: \_array_typespec: @@ -461,7 +461,7 @@ design: (work@top) |vpiVariables: \_array_var: (work@top.queue), line:8:8, endln:8:17 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/DynArrayKind/dut.sv, line:1:1, endln:9:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/DynArrayKind/dut.sv, line:1:1, endln:9:10 |vpiSize:1 |vpiTypespec: \_array_typespec: diff --git a/tests/EarlgreyPackParam/EarlgreyPackParam.log b/tests/EarlgreyPackParam/EarlgreyPackParam.log index f5fca67b84..edbac84b15 100644 --- a/tests/EarlgreyPackParam/EarlgreyPackParam.log +++ b/tests/EarlgreyPackParam/EarlgreyPackParam.log @@ -439,7 +439,7 @@ gen_scope 16 gen_scope_array 16 int_typespec 9 logic_typespec 8 -module 33 +module_inst 33 operation 12 package 3 param_assign 27 @@ -459,7 +459,7 @@ gen_scope 32 gen_scope_array 32 int_typespec 9 logic_typespec 8 -module 47 +module_inst 47 operation 12 package 3 param_assign 39 @@ -656,20 +656,20 @@ design: (work@test) |vpiDefName:alert_handler_reg_pkg |vpiTop:1 |uhdmallModules: -\_module: work@GOOD (work@GOOD), file:${SURELOG_DIR}/tests/EarlgreyPackParam/dut.sv, line:28:1, endln:29:10 +\_module_inst: work@GOOD (work@GOOD), file:${SURELOG_DIR}/tests/EarlgreyPackParam/dut.sv, line:28:1, endln:29:10 |vpiParent: \_design: (work@test) |vpiFullName:work@GOOD |vpiDefName:work@GOOD |uhdmallModules: -\_module: work@aes (work@aes), file:${SURELOG_DIR}/tests/EarlgreyPackParam/dut.sv, line:49:1, endln:60:10 +\_module_inst: work@aes (work@aes), file:${SURELOG_DIR}/tests/EarlgreyPackParam/dut.sv, line:49:1, endln:60:10 |vpiParent: \_design: (work@test) |vpiFullName:work@aes |vpiParameter: \_parameter: (work@aes.AlertAsyncOn), line:50:28, endln:50:40 |vpiParent: - \_module: work@aes (work@aes), file:${SURELOG_DIR}/tests/EarlgreyPackParam/dut.sv, line:49:1, endln:60:10 + \_module_inst: work@aes (work@aes), file:${SURELOG_DIR}/tests/EarlgreyPackParam/dut.sv, line:49:1, endln:60:10 |vpiTypespec: \_logic_typespec: , line:50:14, endln:50:27 |vpiParent: @@ -710,7 +710,7 @@ design: (work@test) |vpiParamAssign: \_param_assign: , line:50:28, endln:50:52 |vpiParent: - \_module: work@aes (work@aes), file:${SURELOG_DIR}/tests/EarlgreyPackParam/dut.sv, line:49:1, endln:60:10 + \_module_inst: work@aes (work@aes), file:${SURELOG_DIR}/tests/EarlgreyPackParam/dut.sv, line:49:1, endln:60:10 |vpiRhs: \_operation: , line:50:43, endln:50:52 |vpiOpType:34 @@ -737,14 +737,14 @@ design: (work@test) \_parameter: (work@aes.AlertAsyncOn), line:50:28, endln:50:40 |vpiDefName:work@aes |uhdmallModules: -\_module: work@prim_alert_sender (work@prim_alert_sender), file:${SURELOG_DIR}/tests/EarlgreyPackParam/dut.sv, line:13:1, endln:26:11 +\_module_inst: work@prim_alert_sender (work@prim_alert_sender), file:${SURELOG_DIR}/tests/EarlgreyPackParam/dut.sv, line:13:1, endln:26:11 |vpiParent: \_design: (work@test) |vpiFullName:work@prim_alert_sender |vpiParameter: \_parameter: (work@prim_alert_sender.AsyncOn), line:15:17, endln:15:24 |vpiParent: - \_module: work@prim_alert_sender (work@prim_alert_sender), file:${SURELOG_DIR}/tests/EarlgreyPackParam/dut.sv, line:13:1, endln:26:11 + \_module_inst: work@prim_alert_sender (work@prim_alert_sender), file:${SURELOG_DIR}/tests/EarlgreyPackParam/dut.sv, line:13:1, endln:26:11 |BIN:1 |vpiTypespec: \_bit_typespec: , line:15:13, endln:15:16 @@ -756,7 +756,7 @@ design: (work@test) |vpiParameter: \_parameter: (work@prim_alert_sender.IsFatal), line:16:17, endln:16:24 |vpiParent: - \_module: work@prim_alert_sender (work@prim_alert_sender), file:${SURELOG_DIR}/tests/EarlgreyPackParam/dut.sv, line:13:1, endln:26:11 + \_module_inst: work@prim_alert_sender (work@prim_alert_sender), file:${SURELOG_DIR}/tests/EarlgreyPackParam/dut.sv, line:13:1, endln:26:11 |BIN:0 |vpiTypespec: \_bit_typespec: , line:16:13, endln:16:16 @@ -768,7 +768,7 @@ design: (work@test) |vpiParamAssign: \_param_assign: , line:15:17, endln:15:31 |vpiParent: - \_module: work@prim_alert_sender (work@prim_alert_sender), file:${SURELOG_DIR}/tests/EarlgreyPackParam/dut.sv, line:13:1, endln:26:11 + \_module_inst: work@prim_alert_sender (work@prim_alert_sender), file:${SURELOG_DIR}/tests/EarlgreyPackParam/dut.sv, line:13:1, endln:26:11 |vpiRhs: \_constant: , line:15:27, endln:15:31 |vpiDecompile:1'b1 @@ -782,7 +782,7 @@ design: (work@test) |vpiParamAssign: \_param_assign: , line:16:17, endln:16:31 |vpiParent: - \_module: work@prim_alert_sender (work@prim_alert_sender), file:${SURELOG_DIR}/tests/EarlgreyPackParam/dut.sv, line:13:1, endln:26:11 + \_module_inst: work@prim_alert_sender (work@prim_alert_sender), file:${SURELOG_DIR}/tests/EarlgreyPackParam/dut.sv, line:13:1, endln:26:11 |vpiRhs: \_constant: , line:16:27, endln:16:31 |vpiDecompile:1'b0 @@ -795,14 +795,14 @@ design: (work@test) \_parameter: (work@prim_alert_sender.IsFatal), line:16:17, endln:16:24 |vpiDefName:work@prim_alert_sender |uhdmallModules: -\_module: work@prim_diff_decode (work@prim_diff_decode), file:${SURELOG_DIR}/tests/EarlgreyPackParam/dut.sv, line:31:1, endln:39:10 +\_module_inst: work@prim_diff_decode (work@prim_diff_decode), file:${SURELOG_DIR}/tests/EarlgreyPackParam/dut.sv, line:31:1, endln:39:10 |vpiParent: \_design: (work@test) |vpiFullName:work@prim_diff_decode |vpiParameter: \_parameter: (work@prim_diff_decode.AsyncOn), line:32:17, endln:32:24 |vpiParent: - \_module: work@prim_diff_decode (work@prim_diff_decode), file:${SURELOG_DIR}/tests/EarlgreyPackParam/dut.sv, line:31:1, endln:39:10 + \_module_inst: work@prim_diff_decode (work@prim_diff_decode), file:${SURELOG_DIR}/tests/EarlgreyPackParam/dut.sv, line:31:1, endln:39:10 |BIN:0 |vpiTypespec: \_bit_typespec: , line:32:13, endln:32:16 @@ -814,7 +814,7 @@ design: (work@test) |vpiParamAssign: \_param_assign: , line:32:17, endln:32:31 |vpiParent: - \_module: work@prim_diff_decode (work@prim_diff_decode), file:${SURELOG_DIR}/tests/EarlgreyPackParam/dut.sv, line:31:1, endln:39:10 + \_module_inst: work@prim_diff_decode (work@prim_diff_decode), file:${SURELOG_DIR}/tests/EarlgreyPackParam/dut.sv, line:31:1, endln:39:10 |vpiRhs: \_constant: , line:32:27, endln:32:31 |vpiDecompile:1'b0 @@ -827,20 +827,20 @@ design: (work@test) \_parameter: (work@prim_diff_decode.AsyncOn), line:32:17, endln:32:24 |vpiDefName:work@prim_diff_decode |uhdmallModules: -\_module: work@test (work@test), file:${SURELOG_DIR}/tests/EarlgreyPackParam/dut.sv, line:7:1, endln:10:10 +\_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/EarlgreyPackParam/dut.sv, line:7:1, endln:10:10 |vpiParent: \_design: (work@test) |vpiFullName:work@test |vpiParameter: \_parameter: (work@test.Toto), line:9:12, endln:9:16 |vpiParent: - \_module: work@test (work@test), file:${SURELOG_DIR}/tests/EarlgreyPackParam/dut.sv, line:7:1, endln:10:10 + \_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/EarlgreyPackParam/dut.sv, line:7:1, endln:10:10 |vpiName:Toto |vpiFullName:work@test.Toto |vpiParamAssign: \_param_assign: , line:9:12, endln:9:56 |vpiParent: - \_module: work@test (work@test), file:${SURELOG_DIR}/tests/EarlgreyPackParam/dut.sv, line:7:1, endln:10:10 + \_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/EarlgreyPackParam/dut.sv, line:7:1, endln:10:10 |vpiRhs: \_part_select: , line:9:50, endln:9:55 |vpiParent: @@ -864,24 +864,24 @@ design: (work@test) \_parameter: (work@test.Toto), line:9:12, endln:9:16 |vpiDefName:work@test |uhdmallModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/EarlgreyPackParam/dut.sv, line:41:1, endln:47:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/EarlgreyPackParam/dut.sv, line:41:1, endln:47:10 |vpiParent: \_design: (work@test) |vpiFullName:work@top |vpiDefName:work@top |uhdmtopModules: -\_module: work@test (work@test), file:${SURELOG_DIR}/tests/EarlgreyPackParam/dut.sv, line:7:1, endln:10:10 +\_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/EarlgreyPackParam/dut.sv, line:7:1, endln:10:10 |vpiName:work@test |vpiParameter: \_parameter: (work@test.Toto), line:9:12, endln:9:16 |vpiParent: - \_module: work@test (work@test), file:${SURELOG_DIR}/tests/EarlgreyPackParam/dut.sv, line:7:1, endln:10:10 + \_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/EarlgreyPackParam/dut.sv, line:7:1, endln:10:10 |vpiName:Toto |vpiFullName:work@test.Toto |vpiParamAssign: \_param_assign: , line:9:12, endln:9:56 |vpiParent: - \_module: work@test (work@test), file:${SURELOG_DIR}/tests/EarlgreyPackParam/dut.sv, line:7:1, endln:10:10 + \_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/EarlgreyPackParam/dut.sv, line:7:1, endln:10:10 |vpiRhs: \_constant: , line:9:19, endln:9:56 |vpiDecompile:2'b11 @@ -894,21 +894,21 @@ design: (work@test) |vpiTop:1 |vpiTopModule:1 |uhdmtopModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/EarlgreyPackParam/dut.sv, line:41:1, endln:47:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/EarlgreyPackParam/dut.sv, line:41:1, endln:47:10 |vpiName:work@top |vpiDefName:work@top |vpiTop:1 |vpiTopModule:1 - |vpiModule: - \_module: work@aes (work@top.u_aes), file:${SURELOG_DIR}/tests/EarlgreyPackParam/dut.sv, line:43:3, endln:45:13 + |vpiModuleInst: + \_module_inst: work@aes (work@top.u_aes), file:${SURELOG_DIR}/tests/EarlgreyPackParam/dut.sv, line:43:3, endln:45:13 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/EarlgreyPackParam/dut.sv, line:41:1, endln:47:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/EarlgreyPackParam/dut.sv, line:41:1, endln:47:10 |vpiName:u_aes |vpiFullName:work@top.u_aes |vpiParameter: \_parameter: (work@top.u_aes.AlertAsyncOn), line:50:28, endln:50:40 |vpiParent: - \_module: work@aes (work@top.u_aes), file:${SURELOG_DIR}/tests/EarlgreyPackParam/dut.sv, line:43:3, endln:45:13 + \_module_inst: work@aes (work@top.u_aes), file:${SURELOG_DIR}/tests/EarlgreyPackParam/dut.sv, line:43:3, endln:45:13 |vpiTypespec: \_logic_typespec: , line:50:14, endln:50:27 |vpiParent: @@ -951,7 +951,7 @@ design: (work@test) |vpiParamAssign: \_param_assign: , line:50:28, endln:50:52 |vpiParent: - \_module: work@aes (work@top.u_aes), file:${SURELOG_DIR}/tests/EarlgreyPackParam/dut.sv, line:43:3, endln:45:13 + \_module_inst: work@aes (work@top.u_aes), file:${SURELOG_DIR}/tests/EarlgreyPackParam/dut.sv, line:43:3, endln:45:13 |vpiOverriden:1 |vpiRhs: \_constant: , line:50:43, endln:50:52 @@ -967,11 +967,11 @@ design: (work@test) |vpiDefFile:${SURELOG_DIR}/tests/EarlgreyPackParam/dut.sv |vpiDefLineNo:49 |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/EarlgreyPackParam/dut.sv, line:41:1, endln:47:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/EarlgreyPackParam/dut.sv, line:41:1, endln:47:10 |vpiGenScopeArray: \_gen_scope_array: (work@top.u_aes.gen_alert_tx[0]), line:52:35, endln:58:6 |vpiParent: - \_module: work@aes (work@top.u_aes), file:${SURELOG_DIR}/tests/EarlgreyPackParam/dut.sv, line:43:3, endln:45:13 + \_module_inst: work@aes (work@top.u_aes), file:${SURELOG_DIR}/tests/EarlgreyPackParam/dut.sv, line:43:3, endln:45:13 |vpiName:gen_alert_tx[0] |vpiFullName:work@top.u_aes.gen_alert_tx[0] |vpiGenScope: @@ -989,8 +989,8 @@ design: (work@test) |vpiLocalParam:1 |vpiName:i |vpiFullName:work@top.u_aes.gen_alert_tx[0].i - |vpiModule: - \_module: work@prim_alert_sender (work@top.u_aes.gen_alert_tx[0].alert_sender), file:${SURELOG_DIR}/tests/EarlgreyPackParam/dut.sv, line:53:5, endln:57:7 + |vpiModuleInst: + \_module_inst: work@prim_alert_sender (work@top.u_aes.gen_alert_tx[0].alert_sender), file:${SURELOG_DIR}/tests/EarlgreyPackParam/dut.sv, line:53:5, endln:57:7 |vpiParent: \_gen_scope: (work@top.u_aes.gen_alert_tx[0]) |vpiName:alert_sender @@ -1022,7 +1022,7 @@ design: (work@test) |vpiParamAssign: \_param_assign: , line:15:17, endln:15:31 |vpiParent: - \_module: work@prim_alert_sender (work@top.u_aes.gen_alert_tx[0].alert_sender), file:${SURELOG_DIR}/tests/EarlgreyPackParam/dut.sv, line:53:5, endln:57:7 + \_module_inst: work@prim_alert_sender (work@top.u_aes.gen_alert_tx[0].alert_sender), file:${SURELOG_DIR}/tests/EarlgreyPackParam/dut.sv, line:53:5, endln:57:7 |vpiOverriden:1 |vpiRhs: \_constant: , line:15:27, endln:15:31 @@ -1037,7 +1037,7 @@ design: (work@test) |vpiParamAssign: \_param_assign: , line:16:17, endln:16:31 |vpiParent: - \_module: work@prim_alert_sender (work@top.u_aes.gen_alert_tx[0].alert_sender), file:${SURELOG_DIR}/tests/EarlgreyPackParam/dut.sv, line:53:5, endln:57:7 + \_module_inst: work@prim_alert_sender (work@top.u_aes.gen_alert_tx[0].alert_sender), file:${SURELOG_DIR}/tests/EarlgreyPackParam/dut.sv, line:53:5, endln:57:7 |vpiOverriden:1 |vpiRhs: \_constant: , line:16:27, endln:16:31 @@ -1052,10 +1052,10 @@ design: (work@test) |vpiDefName:work@prim_alert_sender |vpiDefFile:${SURELOG_DIR}/tests/EarlgreyPackParam/dut.sv |vpiDefLineNo:13 - |vpiModule: - \_module: work@prim_diff_decode (work@top.u_aes.gen_alert_tx[0].alert_sender.dec_ack), file:${SURELOG_DIR}/tests/EarlgreyPackParam/dut.sv, line:19:3, endln:21:16 + |vpiModuleInst: + \_module_inst: work@prim_diff_decode (work@top.u_aes.gen_alert_tx[0].alert_sender.dec_ack), file:${SURELOG_DIR}/tests/EarlgreyPackParam/dut.sv, line:19:3, endln:21:16 |vpiParent: - \_module: work@prim_alert_sender (work@top.u_aes.gen_alert_tx[0].alert_sender), file:${SURELOG_DIR}/tests/EarlgreyPackParam/dut.sv, line:53:5, endln:57:7 + \_module_inst: work@prim_alert_sender (work@top.u_aes.gen_alert_tx[0].alert_sender), file:${SURELOG_DIR}/tests/EarlgreyPackParam/dut.sv, line:53:5, endln:57:7 |vpiName:dec_ack |vpiFullName:work@top.u_aes.gen_alert_tx[0].alert_sender.dec_ack |vpiParameter: @@ -1073,7 +1073,7 @@ design: (work@test) |vpiParamAssign: \_param_assign: , line:32:17, endln:32:31 |vpiParent: - \_module: work@prim_diff_decode (work@top.u_aes.gen_alert_tx[0].alert_sender.dec_ack), file:${SURELOG_DIR}/tests/EarlgreyPackParam/dut.sv, line:19:3, endln:21:16 + \_module_inst: work@prim_diff_decode (work@top.u_aes.gen_alert_tx[0].alert_sender.dec_ack), file:${SURELOG_DIR}/tests/EarlgreyPackParam/dut.sv, line:19:3, endln:21:16 |vpiOverriden:1 |vpiRhs: \_constant: , line:32:27, endln:32:31 @@ -1089,11 +1089,11 @@ design: (work@test) |vpiDefFile:${SURELOG_DIR}/tests/EarlgreyPackParam/dut.sv |vpiDefLineNo:31 |vpiInstance: - \_module: work@prim_alert_sender (work@top.u_aes.gen_alert_tx[0].alert_sender), file:${SURELOG_DIR}/tests/EarlgreyPackParam/dut.sv, line:53:5, endln:57:7 + \_module_inst: work@prim_alert_sender (work@top.u_aes.gen_alert_tx[0].alert_sender), file:${SURELOG_DIR}/tests/EarlgreyPackParam/dut.sv, line:53:5, endln:57:7 |vpiGenScopeArray: \_gen_scope_array: (work@top.u_aes.gen_alert_tx[0].alert_sender.dec_ack.gen_async), line:35:3, endln:37:6 |vpiParent: - \_module: work@prim_diff_decode (work@top.u_aes.gen_alert_tx[0].alert_sender.dec_ack), file:${SURELOG_DIR}/tests/EarlgreyPackParam/dut.sv, line:19:3, endln:21:16 + \_module_inst: work@prim_diff_decode (work@top.u_aes.gen_alert_tx[0].alert_sender.dec_ack), file:${SURELOG_DIR}/tests/EarlgreyPackParam/dut.sv, line:19:3, endln:21:16 |vpiName:gen_async |vpiFullName:work@top.u_aes.gen_alert_tx[0].alert_sender.dec_ack.gen_async |vpiGenScope: @@ -1101,8 +1101,8 @@ design: (work@test) |vpiParent: \_gen_scope_array: (work@top.u_aes.gen_alert_tx[0].alert_sender.dec_ack.gen_async), line:35:3, endln:37:6 |vpiFullName:work@top.u_aes.gen_alert_tx[0].alert_sender.dec_ack.gen_async - |vpiModule: - \_module: work@GOOD (work@top.u_aes.gen_alert_tx[0].alert_sender.dec_ack.gen_async.good), file:${SURELOG_DIR}/tests/EarlgreyPackParam/dut.sv, line:36:6, endln:36:18 + |vpiModuleInst: + \_module_inst: work@GOOD (work@top.u_aes.gen_alert_tx[0].alert_sender.dec_ack.gen_async.good), file:${SURELOG_DIR}/tests/EarlgreyPackParam/dut.sv, line:36:6, endln:36:18 |vpiParent: \_gen_scope: (work@top.u_aes.gen_alert_tx[0].alert_sender.dec_ack.gen_async) |vpiName:good @@ -1113,7 +1113,7 @@ design: (work@test) |vpiGenScopeArray: \_gen_scope_array: (work@top.u_aes.gen_alert_tx[0].alert_sender.gen_async_assert), line:23:5, endln:24:8 |vpiParent: - \_module: work@prim_alert_sender (work@top.u_aes.gen_alert_tx[0].alert_sender), file:${SURELOG_DIR}/tests/EarlgreyPackParam/dut.sv, line:53:5, endln:57:7 + \_module_inst: work@prim_alert_sender (work@top.u_aes.gen_alert_tx[0].alert_sender), file:${SURELOG_DIR}/tests/EarlgreyPackParam/dut.sv, line:53:5, endln:57:7 |vpiName:gen_async_assert |vpiFullName:work@top.u_aes.gen_alert_tx[0].alert_sender.gen_async_assert |vpiGenScope: @@ -1124,7 +1124,7 @@ design: (work@test) |vpiGenScopeArray: \_gen_scope_array: (work@top.u_aes.gen_alert_tx[1]), line:52:35, endln:58:6 |vpiParent: - \_module: work@aes (work@top.u_aes), file:${SURELOG_DIR}/tests/EarlgreyPackParam/dut.sv, line:43:3, endln:45:13 + \_module_inst: work@aes (work@top.u_aes), file:${SURELOG_DIR}/tests/EarlgreyPackParam/dut.sv, line:43:3, endln:45:13 |vpiName:gen_alert_tx[1] |vpiFullName:work@top.u_aes.gen_alert_tx[1] |vpiGenScope: @@ -1142,8 +1142,8 @@ design: (work@test) |vpiLocalParam:1 |vpiName:i |vpiFullName:work@top.u_aes.gen_alert_tx[1].i - |vpiModule: - \_module: work@prim_alert_sender (work@top.u_aes.gen_alert_tx[1].alert_sender), file:${SURELOG_DIR}/tests/EarlgreyPackParam/dut.sv, line:53:5, endln:57:7 + |vpiModuleInst: + \_module_inst: work@prim_alert_sender (work@top.u_aes.gen_alert_tx[1].alert_sender), file:${SURELOG_DIR}/tests/EarlgreyPackParam/dut.sv, line:53:5, endln:57:7 |vpiParent: \_gen_scope: (work@top.u_aes.gen_alert_tx[1]) |vpiName:alert_sender @@ -1175,7 +1175,7 @@ design: (work@test) |vpiParamAssign: \_param_assign: , line:15:17, endln:15:31 |vpiParent: - \_module: work@prim_alert_sender (work@top.u_aes.gen_alert_tx[1].alert_sender), file:${SURELOG_DIR}/tests/EarlgreyPackParam/dut.sv, line:53:5, endln:57:7 + \_module_inst: work@prim_alert_sender (work@top.u_aes.gen_alert_tx[1].alert_sender), file:${SURELOG_DIR}/tests/EarlgreyPackParam/dut.sv, line:53:5, endln:57:7 |vpiOverriden:1 |vpiRhs: \_constant: , line:15:27, endln:15:31 @@ -1190,7 +1190,7 @@ design: (work@test) |vpiParamAssign: \_param_assign: , line:16:17, endln:16:31 |vpiParent: - \_module: work@prim_alert_sender (work@top.u_aes.gen_alert_tx[1].alert_sender), file:${SURELOG_DIR}/tests/EarlgreyPackParam/dut.sv, line:53:5, endln:57:7 + \_module_inst: work@prim_alert_sender (work@top.u_aes.gen_alert_tx[1].alert_sender), file:${SURELOG_DIR}/tests/EarlgreyPackParam/dut.sv, line:53:5, endln:57:7 |vpiOverriden:1 |vpiRhs: \_constant: , line:16:27, endln:16:31 @@ -1205,10 +1205,10 @@ design: (work@test) |vpiDefName:work@prim_alert_sender |vpiDefFile:${SURELOG_DIR}/tests/EarlgreyPackParam/dut.sv |vpiDefLineNo:13 - |vpiModule: - \_module: work@prim_diff_decode (work@top.u_aes.gen_alert_tx[1].alert_sender.dec_ack), file:${SURELOG_DIR}/tests/EarlgreyPackParam/dut.sv, line:19:3, endln:21:16 + |vpiModuleInst: + \_module_inst: work@prim_diff_decode (work@top.u_aes.gen_alert_tx[1].alert_sender.dec_ack), file:${SURELOG_DIR}/tests/EarlgreyPackParam/dut.sv, line:19:3, endln:21:16 |vpiParent: - \_module: work@prim_alert_sender (work@top.u_aes.gen_alert_tx[1].alert_sender), file:${SURELOG_DIR}/tests/EarlgreyPackParam/dut.sv, line:53:5, endln:57:7 + \_module_inst: work@prim_alert_sender (work@top.u_aes.gen_alert_tx[1].alert_sender), file:${SURELOG_DIR}/tests/EarlgreyPackParam/dut.sv, line:53:5, endln:57:7 |vpiName:dec_ack |vpiFullName:work@top.u_aes.gen_alert_tx[1].alert_sender.dec_ack |vpiParameter: @@ -1226,7 +1226,7 @@ design: (work@test) |vpiParamAssign: \_param_assign: , line:32:17, endln:32:31 |vpiParent: - \_module: work@prim_diff_decode (work@top.u_aes.gen_alert_tx[1].alert_sender.dec_ack), file:${SURELOG_DIR}/tests/EarlgreyPackParam/dut.sv, line:19:3, endln:21:16 + \_module_inst: work@prim_diff_decode (work@top.u_aes.gen_alert_tx[1].alert_sender.dec_ack), file:${SURELOG_DIR}/tests/EarlgreyPackParam/dut.sv, line:19:3, endln:21:16 |vpiOverriden:1 |vpiRhs: \_constant: , line:32:27, endln:32:31 @@ -1242,11 +1242,11 @@ design: (work@test) |vpiDefFile:${SURELOG_DIR}/tests/EarlgreyPackParam/dut.sv |vpiDefLineNo:31 |vpiInstance: - \_module: work@prim_alert_sender (work@top.u_aes.gen_alert_tx[1].alert_sender), file:${SURELOG_DIR}/tests/EarlgreyPackParam/dut.sv, line:53:5, endln:57:7 + \_module_inst: work@prim_alert_sender (work@top.u_aes.gen_alert_tx[1].alert_sender), file:${SURELOG_DIR}/tests/EarlgreyPackParam/dut.sv, line:53:5, endln:57:7 |vpiGenScopeArray: \_gen_scope_array: (work@top.u_aes.gen_alert_tx[1].alert_sender.dec_ack.gen_async), line:35:3, endln:37:6 |vpiParent: - \_module: work@prim_diff_decode (work@top.u_aes.gen_alert_tx[1].alert_sender.dec_ack), file:${SURELOG_DIR}/tests/EarlgreyPackParam/dut.sv, line:19:3, endln:21:16 + \_module_inst: work@prim_diff_decode (work@top.u_aes.gen_alert_tx[1].alert_sender.dec_ack), file:${SURELOG_DIR}/tests/EarlgreyPackParam/dut.sv, line:19:3, endln:21:16 |vpiName:gen_async |vpiFullName:work@top.u_aes.gen_alert_tx[1].alert_sender.dec_ack.gen_async |vpiGenScope: @@ -1254,8 +1254,8 @@ design: (work@test) |vpiParent: \_gen_scope_array: (work@top.u_aes.gen_alert_tx[1].alert_sender.dec_ack.gen_async), line:35:3, endln:37:6 |vpiFullName:work@top.u_aes.gen_alert_tx[1].alert_sender.dec_ack.gen_async - |vpiModule: - \_module: work@GOOD (work@top.u_aes.gen_alert_tx[1].alert_sender.dec_ack.gen_async.good), file:${SURELOG_DIR}/tests/EarlgreyPackParam/dut.sv, line:36:6, endln:36:18 + |vpiModuleInst: + \_module_inst: work@GOOD (work@top.u_aes.gen_alert_tx[1].alert_sender.dec_ack.gen_async.good), file:${SURELOG_DIR}/tests/EarlgreyPackParam/dut.sv, line:36:6, endln:36:18 |vpiParent: \_gen_scope: (work@top.u_aes.gen_alert_tx[1].alert_sender.dec_ack.gen_async) |vpiName:good @@ -1266,7 +1266,7 @@ design: (work@test) |vpiGenScopeArray: \_gen_scope_array: (work@top.u_aes.gen_alert_tx[1].alert_sender.gen_async_assert), line:23:5, endln:24:8 |vpiParent: - \_module: work@prim_alert_sender (work@top.u_aes.gen_alert_tx[1].alert_sender), file:${SURELOG_DIR}/tests/EarlgreyPackParam/dut.sv, line:53:5, endln:57:7 + \_module_inst: work@prim_alert_sender (work@top.u_aes.gen_alert_tx[1].alert_sender), file:${SURELOG_DIR}/tests/EarlgreyPackParam/dut.sv, line:53:5, endln:57:7 |vpiName:gen_async_assert |vpiFullName:work@top.u_aes.gen_alert_tx[1].alert_sender.gen_async_assert |vpiGenScope: @@ -1277,7 +1277,7 @@ design: (work@test) |vpiGenScopeArray: \_gen_scope_array: (work@top.u_aes.gen_alert_tx[2]), line:52:35, endln:58:6 |vpiParent: - \_module: work@aes (work@top.u_aes), file:${SURELOG_DIR}/tests/EarlgreyPackParam/dut.sv, line:43:3, endln:45:13 + \_module_inst: work@aes (work@top.u_aes), file:${SURELOG_DIR}/tests/EarlgreyPackParam/dut.sv, line:43:3, endln:45:13 |vpiName:gen_alert_tx[2] |vpiFullName:work@top.u_aes.gen_alert_tx[2] |vpiGenScope: @@ -1295,8 +1295,8 @@ design: (work@test) |vpiLocalParam:1 |vpiName:i |vpiFullName:work@top.u_aes.gen_alert_tx[2].i - |vpiModule: - \_module: work@prim_alert_sender (work@top.u_aes.gen_alert_tx[2].alert_sender), file:${SURELOG_DIR}/tests/EarlgreyPackParam/dut.sv, line:53:5, endln:57:7 + |vpiModuleInst: + \_module_inst: work@prim_alert_sender (work@top.u_aes.gen_alert_tx[2].alert_sender), file:${SURELOG_DIR}/tests/EarlgreyPackParam/dut.sv, line:53:5, endln:57:7 |vpiParent: \_gen_scope: (work@top.u_aes.gen_alert_tx[2]) |vpiName:alert_sender @@ -1328,7 +1328,7 @@ design: (work@test) |vpiParamAssign: \_param_assign: , line:15:17, endln:15:31 |vpiParent: - \_module: work@prim_alert_sender (work@top.u_aes.gen_alert_tx[2].alert_sender), file:${SURELOG_DIR}/tests/EarlgreyPackParam/dut.sv, line:53:5, endln:57:7 + \_module_inst: work@prim_alert_sender (work@top.u_aes.gen_alert_tx[2].alert_sender), file:${SURELOG_DIR}/tests/EarlgreyPackParam/dut.sv, line:53:5, endln:57:7 |vpiOverriden:1 |vpiRhs: \_constant: , line:15:27, endln:15:31 @@ -1343,7 +1343,7 @@ design: (work@test) |vpiParamAssign: \_param_assign: , line:16:17, endln:16:31 |vpiParent: - \_module: work@prim_alert_sender (work@top.u_aes.gen_alert_tx[2].alert_sender), file:${SURELOG_DIR}/tests/EarlgreyPackParam/dut.sv, line:53:5, endln:57:7 + \_module_inst: work@prim_alert_sender (work@top.u_aes.gen_alert_tx[2].alert_sender), file:${SURELOG_DIR}/tests/EarlgreyPackParam/dut.sv, line:53:5, endln:57:7 |vpiOverriden:1 |vpiRhs: \_constant: , line:16:27, endln:16:31 @@ -1358,10 +1358,10 @@ design: (work@test) |vpiDefName:work@prim_alert_sender |vpiDefFile:${SURELOG_DIR}/tests/EarlgreyPackParam/dut.sv |vpiDefLineNo:13 - |vpiModule: - \_module: work@prim_diff_decode (work@top.u_aes.gen_alert_tx[2].alert_sender.dec_ack), file:${SURELOG_DIR}/tests/EarlgreyPackParam/dut.sv, line:19:3, endln:21:16 + |vpiModuleInst: + \_module_inst: work@prim_diff_decode (work@top.u_aes.gen_alert_tx[2].alert_sender.dec_ack), file:${SURELOG_DIR}/tests/EarlgreyPackParam/dut.sv, line:19:3, endln:21:16 |vpiParent: - \_module: work@prim_alert_sender (work@top.u_aes.gen_alert_tx[2].alert_sender), file:${SURELOG_DIR}/tests/EarlgreyPackParam/dut.sv, line:53:5, endln:57:7 + \_module_inst: work@prim_alert_sender (work@top.u_aes.gen_alert_tx[2].alert_sender), file:${SURELOG_DIR}/tests/EarlgreyPackParam/dut.sv, line:53:5, endln:57:7 |vpiName:dec_ack |vpiFullName:work@top.u_aes.gen_alert_tx[2].alert_sender.dec_ack |vpiParameter: @@ -1379,7 +1379,7 @@ design: (work@test) |vpiParamAssign: \_param_assign: , line:32:17, endln:32:31 |vpiParent: - \_module: work@prim_diff_decode (work@top.u_aes.gen_alert_tx[2].alert_sender.dec_ack), file:${SURELOG_DIR}/tests/EarlgreyPackParam/dut.sv, line:19:3, endln:21:16 + \_module_inst: work@prim_diff_decode (work@top.u_aes.gen_alert_tx[2].alert_sender.dec_ack), file:${SURELOG_DIR}/tests/EarlgreyPackParam/dut.sv, line:19:3, endln:21:16 |vpiOverriden:1 |vpiRhs: \_constant: , line:32:27, endln:32:31 @@ -1395,11 +1395,11 @@ design: (work@test) |vpiDefFile:${SURELOG_DIR}/tests/EarlgreyPackParam/dut.sv |vpiDefLineNo:31 |vpiInstance: - \_module: work@prim_alert_sender (work@top.u_aes.gen_alert_tx[2].alert_sender), file:${SURELOG_DIR}/tests/EarlgreyPackParam/dut.sv, line:53:5, endln:57:7 + \_module_inst: work@prim_alert_sender (work@top.u_aes.gen_alert_tx[2].alert_sender), file:${SURELOG_DIR}/tests/EarlgreyPackParam/dut.sv, line:53:5, endln:57:7 |vpiGenScopeArray: \_gen_scope_array: (work@top.u_aes.gen_alert_tx[3]), line:52:35, endln:58:6 |vpiParent: - \_module: work@aes (work@top.u_aes), file:${SURELOG_DIR}/tests/EarlgreyPackParam/dut.sv, line:43:3, endln:45:13 + \_module_inst: work@aes (work@top.u_aes), file:${SURELOG_DIR}/tests/EarlgreyPackParam/dut.sv, line:43:3, endln:45:13 |vpiName:gen_alert_tx[3] |vpiFullName:work@top.u_aes.gen_alert_tx[3] |vpiGenScope: @@ -1417,8 +1417,8 @@ design: (work@test) |vpiLocalParam:1 |vpiName:i |vpiFullName:work@top.u_aes.gen_alert_tx[3].i - |vpiModule: - \_module: work@prim_alert_sender (work@top.u_aes.gen_alert_tx[3].alert_sender), file:${SURELOG_DIR}/tests/EarlgreyPackParam/dut.sv, line:53:5, endln:57:7 + |vpiModuleInst: + \_module_inst: work@prim_alert_sender (work@top.u_aes.gen_alert_tx[3].alert_sender), file:${SURELOG_DIR}/tests/EarlgreyPackParam/dut.sv, line:53:5, endln:57:7 |vpiParent: \_gen_scope: (work@top.u_aes.gen_alert_tx[3]) |vpiName:alert_sender @@ -1450,7 +1450,7 @@ design: (work@test) |vpiParamAssign: \_param_assign: , line:15:17, endln:15:31 |vpiParent: - \_module: work@prim_alert_sender (work@top.u_aes.gen_alert_tx[3].alert_sender), file:${SURELOG_DIR}/tests/EarlgreyPackParam/dut.sv, line:53:5, endln:57:7 + \_module_inst: work@prim_alert_sender (work@top.u_aes.gen_alert_tx[3].alert_sender), file:${SURELOG_DIR}/tests/EarlgreyPackParam/dut.sv, line:53:5, endln:57:7 |vpiOverriden:1 |vpiRhs: \_constant: , line:15:27, endln:15:31 @@ -1465,7 +1465,7 @@ design: (work@test) |vpiParamAssign: \_param_assign: , line:16:17, endln:16:31 |vpiParent: - \_module: work@prim_alert_sender (work@top.u_aes.gen_alert_tx[3].alert_sender), file:${SURELOG_DIR}/tests/EarlgreyPackParam/dut.sv, line:53:5, endln:57:7 + \_module_inst: work@prim_alert_sender (work@top.u_aes.gen_alert_tx[3].alert_sender), file:${SURELOG_DIR}/tests/EarlgreyPackParam/dut.sv, line:53:5, endln:57:7 |vpiOverriden:1 |vpiRhs: \_constant: , line:16:27, endln:16:31 @@ -1480,10 +1480,10 @@ design: (work@test) |vpiDefName:work@prim_alert_sender |vpiDefFile:${SURELOG_DIR}/tests/EarlgreyPackParam/dut.sv |vpiDefLineNo:13 - |vpiModule: - \_module: work@prim_diff_decode (work@top.u_aes.gen_alert_tx[3].alert_sender.dec_ack), file:${SURELOG_DIR}/tests/EarlgreyPackParam/dut.sv, line:19:3, endln:21:16 + |vpiModuleInst: + \_module_inst: work@prim_diff_decode (work@top.u_aes.gen_alert_tx[3].alert_sender.dec_ack), file:${SURELOG_DIR}/tests/EarlgreyPackParam/dut.sv, line:19:3, endln:21:16 |vpiParent: - \_module: work@prim_alert_sender (work@top.u_aes.gen_alert_tx[3].alert_sender), file:${SURELOG_DIR}/tests/EarlgreyPackParam/dut.sv, line:53:5, endln:57:7 + \_module_inst: work@prim_alert_sender (work@top.u_aes.gen_alert_tx[3].alert_sender), file:${SURELOG_DIR}/tests/EarlgreyPackParam/dut.sv, line:53:5, endln:57:7 |vpiName:dec_ack |vpiFullName:work@top.u_aes.gen_alert_tx[3].alert_sender.dec_ack |vpiParameter: @@ -1501,7 +1501,7 @@ design: (work@test) |vpiParamAssign: \_param_assign: , line:32:17, endln:32:31 |vpiParent: - \_module: work@prim_diff_decode (work@top.u_aes.gen_alert_tx[3].alert_sender.dec_ack), file:${SURELOG_DIR}/tests/EarlgreyPackParam/dut.sv, line:19:3, endln:21:16 + \_module_inst: work@prim_diff_decode (work@top.u_aes.gen_alert_tx[3].alert_sender.dec_ack), file:${SURELOG_DIR}/tests/EarlgreyPackParam/dut.sv, line:19:3, endln:21:16 |vpiOverriden:1 |vpiRhs: \_constant: , line:32:27, endln:32:31 @@ -1517,7 +1517,7 @@ design: (work@test) |vpiDefFile:${SURELOG_DIR}/tests/EarlgreyPackParam/dut.sv |vpiDefLineNo:31 |vpiInstance: - \_module: work@prim_alert_sender (work@top.u_aes.gen_alert_tx[3].alert_sender), file:${SURELOG_DIR}/tests/EarlgreyPackParam/dut.sv, line:53:5, endln:57:7 + \_module_inst: work@prim_alert_sender (work@top.u_aes.gen_alert_tx[3].alert_sender), file:${SURELOG_DIR}/tests/EarlgreyPackParam/dut.sv, line:53:5, endln:57:7 =================== [ FATAL] : 0 [ SYNTAX] : 0 diff --git a/tests/ElabCParam/ElabCParam.log b/tests/ElabCParam/ElabCParam.log index 1e51a93639..8268bbbae4 100644 --- a/tests/ElabCParam/ElabCParam.log +++ b/tests/ElabCParam/ElabCParam.log @@ -893,7 +893,7 @@ int_var 4 io_decl 11 logic_typespec 6 logic_var 1 -module 34 +module_inst 34 operation 38 package 2 param_assign 30 @@ -924,7 +924,7 @@ int_var 4 io_decl 22 logic_typespec 6 logic_var 1 -module 42 +module_inst 42 operation 38 package 2 param_assign 44 @@ -1421,14 +1421,14 @@ design: (work@socket_1n) \_int_typespec: |vpiSigned:1 |uhdmallModules: -\_module: work@all_zero (work@all_zero), file:${SURELOG_DIR}/tests/ElabCParam/dut.sv, line:54:1, endln:67:10 +\_module_inst: work@all_zero (work@all_zero), file:${SURELOG_DIR}/tests/ElabCParam/dut.sv, line:54:1, endln:67:10 |vpiParent: \_design: (work@socket_1n) |vpiFullName:work@all_zero |vpiParameter: \_parameter: (work@all_zero.N), line:55:27, endln:55:28 |vpiParent: - \_module: work@all_zero (work@all_zero), file:${SURELOG_DIR}/tests/ElabCParam/dut.sv, line:54:1, endln:67:10 + \_module_inst: work@all_zero (work@all_zero), file:${SURELOG_DIR}/tests/ElabCParam/dut.sv, line:54:1, endln:67:10 |UINT:2 |vpiTypespec: \_int_typespec: , line:55:13, endln:55:25 @@ -1439,7 +1439,7 @@ design: (work@socket_1n) |vpiParameter: \_parameter: (work@all_zero.DReqDepth), line:56:23, endln:56:32 |vpiParent: - \_module: work@all_zero (work@all_zero), file:${SURELOG_DIR}/tests/ElabCParam/dut.sv, line:54:1, endln:67:10 + \_module_inst: work@all_zero (work@all_zero), file:${SURELOG_DIR}/tests/ElabCParam/dut.sv, line:54:1, endln:67:10 |vpiTypespec: \_bit_typespec: , line:56:13, endln:56:22 |vpiParent: @@ -1468,7 +1468,7 @@ design: (work@socket_1n) |vpiParameter: \_parameter: (work@all_zero.AA), line:57:23, endln:57:25 |vpiParent: - \_module: work@all_zero (work@all_zero), file:${SURELOG_DIR}/tests/ElabCParam/dut.sv, line:54:1, endln:67:10 + \_module_inst: work@all_zero (work@all_zero), file:${SURELOG_DIR}/tests/ElabCParam/dut.sv, line:54:1, endln:67:10 |vpiTypespec: \_bit_typespec: , line:57:13, endln:57:22 |vpiParent: @@ -1497,7 +1497,7 @@ design: (work@socket_1n) |vpiParameter: \_parameter: (work@all_zero.BB), line:58:23, endln:58:25 |vpiParent: - \_module: work@all_zero (work@all_zero), file:${SURELOG_DIR}/tests/ElabCParam/dut.sv, line:54:1, endln:67:10 + \_module_inst: work@all_zero (work@all_zero), file:${SURELOG_DIR}/tests/ElabCParam/dut.sv, line:54:1, endln:67:10 |vpiTypespec: \_bit_typespec: , line:58:13, endln:58:22 |vpiParent: @@ -1526,7 +1526,7 @@ design: (work@socket_1n) |vpiParamAssign: \_param_assign: , line:55:27, endln:55:40 |vpiParent: - \_module: work@all_zero (work@all_zero), file:${SURELOG_DIR}/tests/ElabCParam/dut.sv, line:54:1, endln:67:10 + \_module_inst: work@all_zero (work@all_zero), file:${SURELOG_DIR}/tests/ElabCParam/dut.sv, line:54:1, endln:67:10 |vpiRhs: \_constant: , line:55:39, endln:55:40 |vpiDecompile:2 @@ -1540,7 +1540,7 @@ design: (work@socket_1n) |vpiParamAssign: \_param_assign: , line:56:23, endln:56:44 |vpiParent: - \_module: work@all_zero (work@all_zero), file:${SURELOG_DIR}/tests/ElabCParam/dut.sv, line:54:1, endln:67:10 + \_module_inst: work@all_zero (work@all_zero), file:${SURELOG_DIR}/tests/ElabCParam/dut.sv, line:54:1, endln:67:10 |vpiRhs: \_operation: , line:56:35, endln:56:44 |vpiOpType:34 @@ -1568,7 +1568,7 @@ design: (work@socket_1n) |vpiParamAssign: \_param_assign: , line:57:23, endln:57:41 |vpiParent: - \_module: work@all_zero (work@all_zero), file:${SURELOG_DIR}/tests/ElabCParam/dut.sv, line:54:1, endln:67:10 + \_module_inst: work@all_zero (work@all_zero), file:${SURELOG_DIR}/tests/ElabCParam/dut.sv, line:54:1, endln:67:10 |vpiRhs: \_operation: , line:57:28, endln:57:41 |vpiOpType:25 @@ -1590,7 +1590,7 @@ design: (work@socket_1n) |vpiParamAssign: \_param_assign: , line:58:23, endln:58:45 |vpiParent: - \_module: work@all_zero (work@all_zero), file:${SURELOG_DIR}/tests/ElabCParam/dut.sv, line:54:1, endln:67:10 + \_module_inst: work@all_zero (work@all_zero), file:${SURELOG_DIR}/tests/ElabCParam/dut.sv, line:54:1, endln:67:10 |vpiRhs: \_indexed_part_select: , line:58:28, endln:58:45 |vpiParent: @@ -1628,14 +1628,14 @@ design: (work@socket_1n) \_parameter: (work@all_zero.BB), line:58:23, endln:58:25 |vpiDefName:work@all_zero |uhdmallModules: -\_module: work@fifo_sync (work@fifo_sync), file:${SURELOG_DIR}/tests/ElabCParam/dut.sv, line:24:1, endln:33:10 +\_module_inst: work@fifo_sync (work@fifo_sync), file:${SURELOG_DIR}/tests/ElabCParam/dut.sv, line:24:1, endln:33:10 |vpiParent: \_design: (work@socket_1n) |vpiFullName:work@fifo_sync |vpiParameter: \_parameter: (work@fifo_sync.ReqDepth), line:25:26, endln:25:34 |vpiParent: - \_module: work@fifo_sync (work@fifo_sync), file:${SURELOG_DIR}/tests/ElabCParam/dut.sv, line:24:1, endln:33:10 + \_module_inst: work@fifo_sync (work@fifo_sync), file:${SURELOG_DIR}/tests/ElabCParam/dut.sv, line:24:1, endln:33:10 |UINT:6 |vpiTypespec: \_int_typespec: , line:25:13, endln:25:25 @@ -1646,7 +1646,7 @@ design: (work@socket_1n) |vpiParamAssign: \_param_assign: , line:25:26, endln:25:38 |vpiParent: - \_module: work@fifo_sync (work@fifo_sync), file:${SURELOG_DIR}/tests/ElabCParam/dut.sv, line:24:1, endln:33:10 + \_module_inst: work@fifo_sync (work@fifo_sync), file:${SURELOG_DIR}/tests/ElabCParam/dut.sv, line:24:1, endln:33:10 |vpiRhs: \_constant: , line:25:37, endln:25:38 |vpiDecompile:6 @@ -1659,14 +1659,14 @@ design: (work@socket_1n) \_parameter: (work@fifo_sync.ReqDepth), line:25:26, endln:25:34 |vpiDefName:work@fifo_sync |uhdmallModules: -\_module: work@prim_fifo_sync (work@prim_fifo_sync), file:${SURELOG_DIR}/tests/ElabCParam/dut.sv, line:2:1, endln:21:10 +\_module_inst: work@prim_fifo_sync (work@prim_fifo_sync), file:${SURELOG_DIR}/tests/ElabCParam/dut.sv, line:2:1, endln:21:10 |vpiParent: \_design: (work@socket_1n) |vpiFullName:work@prim_fifo_sync |vpiParameter: \_parameter: (work@prim_fifo_sync.Depth), line:3:26, endln:3:31 |vpiParent: - \_module: work@prim_fifo_sync (work@prim_fifo_sync), file:${SURELOG_DIR}/tests/ElabCParam/dut.sv, line:2:1, endln:21:10 + \_module_inst: work@prim_fifo_sync (work@prim_fifo_sync), file:${SURELOG_DIR}/tests/ElabCParam/dut.sv, line:2:1, endln:21:10 |UINT:4 |vpiTypespec: \_int_typespec: , line:3:13, endln:3:25 @@ -1677,7 +1677,7 @@ design: (work@socket_1n) |vpiParamAssign: \_param_assign: , line:3:26, endln:3:41 |vpiParent: - \_module: work@prim_fifo_sync (work@prim_fifo_sync), file:${SURELOG_DIR}/tests/ElabCParam/dut.sv, line:2:1, endln:21:10 + \_module_inst: work@prim_fifo_sync (work@prim_fifo_sync), file:${SURELOG_DIR}/tests/ElabCParam/dut.sv, line:2:1, endln:21:10 |vpiRhs: \_constant: , line:3:40, endln:3:41 |vpiDecompile:4 @@ -1690,14 +1690,14 @@ design: (work@socket_1n) \_parameter: (work@prim_fifo_sync.Depth), line:3:26, endln:3:31 |vpiDefName:work@prim_fifo_sync |uhdmallModules: -\_module: work@socket_1n (work@socket_1n), file:${SURELOG_DIR}/tests/ElabCParam/dut.sv, line:38:1, endln:51:10 +\_module_inst: work@socket_1n (work@socket_1n), file:${SURELOG_DIR}/tests/ElabCParam/dut.sv, line:38:1, endln:51:10 |vpiParent: \_design: (work@socket_1n) |vpiFullName:work@socket_1n |vpiParameter: \_parameter: (work@socket_1n.N), line:39:27, endln:39:28 |vpiParent: - \_module: work@socket_1n (work@socket_1n), file:${SURELOG_DIR}/tests/ElabCParam/dut.sv, line:38:1, endln:51:10 + \_module_inst: work@socket_1n (work@socket_1n), file:${SURELOG_DIR}/tests/ElabCParam/dut.sv, line:38:1, endln:51:10 |UINT:2 |vpiTypespec: \_int_typespec: , line:39:13, endln:39:25 @@ -1708,7 +1708,7 @@ design: (work@socket_1n) |vpiParameter: \_parameter: (work@socket_1n.DReqDepth), line:40:23, endln:40:32 |vpiParent: - \_module: work@socket_1n (work@socket_1n), file:${SURELOG_DIR}/tests/ElabCParam/dut.sv, line:38:1, endln:51:10 + \_module_inst: work@socket_1n (work@socket_1n), file:${SURELOG_DIR}/tests/ElabCParam/dut.sv, line:38:1, endln:51:10 |vpiTypespec: \_bit_typespec: , line:40:13, endln:40:22 |vpiParent: @@ -1737,7 +1737,7 @@ design: (work@socket_1n) |vpiParameter: \_parameter: (work@socket_1n.AA), line:41:23, endln:41:25 |vpiParent: - \_module: work@socket_1n (work@socket_1n), file:${SURELOG_DIR}/tests/ElabCParam/dut.sv, line:38:1, endln:51:10 + \_module_inst: work@socket_1n (work@socket_1n), file:${SURELOG_DIR}/tests/ElabCParam/dut.sv, line:38:1, endln:51:10 |vpiTypespec: \_bit_typespec: , line:41:13, endln:41:22 |vpiParent: @@ -1766,7 +1766,7 @@ design: (work@socket_1n) |vpiParameter: \_parameter: (work@socket_1n.BB), line:42:23, endln:42:25 |vpiParent: - \_module: work@socket_1n (work@socket_1n), file:${SURELOG_DIR}/tests/ElabCParam/dut.sv, line:38:1, endln:51:10 + \_module_inst: work@socket_1n (work@socket_1n), file:${SURELOG_DIR}/tests/ElabCParam/dut.sv, line:38:1, endln:51:10 |vpiTypespec: \_bit_typespec: , line:42:13, endln:42:22 |vpiParent: @@ -1795,7 +1795,7 @@ design: (work@socket_1n) |vpiParamAssign: \_param_assign: , line:39:27, endln:39:40 |vpiParent: - \_module: work@socket_1n (work@socket_1n), file:${SURELOG_DIR}/tests/ElabCParam/dut.sv, line:38:1, endln:51:10 + \_module_inst: work@socket_1n (work@socket_1n), file:${SURELOG_DIR}/tests/ElabCParam/dut.sv, line:38:1, endln:51:10 |vpiRhs: \_constant: , line:39:39, endln:39:40 |vpiDecompile:2 @@ -1809,7 +1809,7 @@ design: (work@socket_1n) |vpiParamAssign: \_param_assign: , line:40:23, endln:40:44 |vpiParent: - \_module: work@socket_1n (work@socket_1n), file:${SURELOG_DIR}/tests/ElabCParam/dut.sv, line:38:1, endln:51:10 + \_module_inst: work@socket_1n (work@socket_1n), file:${SURELOG_DIR}/tests/ElabCParam/dut.sv, line:38:1, endln:51:10 |vpiRhs: \_operation: , line:40:35, endln:40:44 |vpiOpType:34 @@ -1834,7 +1834,7 @@ design: (work@socket_1n) |vpiParamAssign: \_param_assign: , line:41:23, endln:41:41 |vpiParent: - \_module: work@socket_1n (work@socket_1n), file:${SURELOG_DIR}/tests/ElabCParam/dut.sv, line:38:1, endln:51:10 + \_module_inst: work@socket_1n (work@socket_1n), file:${SURELOG_DIR}/tests/ElabCParam/dut.sv, line:38:1, endln:51:10 |vpiRhs: \_operation: , line:41:28, endln:41:41 |vpiOpType:25 @@ -1856,7 +1856,7 @@ design: (work@socket_1n) |vpiParamAssign: \_param_assign: , line:42:23, endln:42:45 |vpiParent: - \_module: work@socket_1n (work@socket_1n), file:${SURELOG_DIR}/tests/ElabCParam/dut.sv, line:38:1, endln:51:10 + \_module_inst: work@socket_1n (work@socket_1n), file:${SURELOG_DIR}/tests/ElabCParam/dut.sv, line:38:1, endln:51:10 |vpiRhs: \_indexed_part_select: , line:42:28, endln:42:45 |vpiParent: @@ -1894,12 +1894,12 @@ design: (work@socket_1n) \_parameter: (work@socket_1n.BB), line:42:23, endln:42:25 |vpiDefName:work@socket_1n |uhdmtopModules: -\_module: work@socket_1n (work@socket_1n), file:${SURELOG_DIR}/tests/ElabCParam/dut.sv, line:38:1, endln:51:10 +\_module_inst: work@socket_1n (work@socket_1n), file:${SURELOG_DIR}/tests/ElabCParam/dut.sv, line:38:1, endln:51:10 |vpiName:work@socket_1n |vpiParameter: \_parameter: (work@socket_1n.N), line:39:27, endln:39:28 |vpiParent: - \_module: work@socket_1n (work@socket_1n), file:${SURELOG_DIR}/tests/ElabCParam/dut.sv, line:38:1, endln:51:10 + \_module_inst: work@socket_1n (work@socket_1n), file:${SURELOG_DIR}/tests/ElabCParam/dut.sv, line:38:1, endln:51:10 |UINT:2 |vpiTypespec: \_int_typespec: , line:39:13, endln:39:25 @@ -1910,7 +1910,7 @@ design: (work@socket_1n) |vpiParameter: \_parameter: (work@socket_1n.DReqDepth), line:40:23, endln:40:32 |vpiParent: - \_module: work@socket_1n (work@socket_1n), file:${SURELOG_DIR}/tests/ElabCParam/dut.sv, line:38:1, endln:51:10 + \_module_inst: work@socket_1n (work@socket_1n), file:${SURELOG_DIR}/tests/ElabCParam/dut.sv, line:38:1, endln:51:10 |vpiTypespec: \_bit_typespec: , line:40:13, endln:40:22 |vpiParent: @@ -1941,7 +1941,7 @@ design: (work@socket_1n) |vpiParameter: \_parameter: (work@socket_1n.AA), line:41:23, endln:41:25 |vpiParent: - \_module: work@socket_1n (work@socket_1n), file:${SURELOG_DIR}/tests/ElabCParam/dut.sv, line:38:1, endln:51:10 + \_module_inst: work@socket_1n (work@socket_1n), file:${SURELOG_DIR}/tests/ElabCParam/dut.sv, line:38:1, endln:51:10 |vpiTypespec: \_bit_typespec: , line:41:13, endln:41:22 |vpiParent: @@ -1972,7 +1972,7 @@ design: (work@socket_1n) |vpiParameter: \_parameter: (work@socket_1n.BB), line:42:23, endln:42:25 |vpiParent: - \_module: work@socket_1n (work@socket_1n), file:${SURELOG_DIR}/tests/ElabCParam/dut.sv, line:38:1, endln:51:10 + \_module_inst: work@socket_1n (work@socket_1n), file:${SURELOG_DIR}/tests/ElabCParam/dut.sv, line:38:1, endln:51:10 |vpiTypespec: \_bit_typespec: , line:42:13, endln:42:22 |vpiParent: @@ -2003,7 +2003,7 @@ design: (work@socket_1n) |vpiParamAssign: \_param_assign: , line:39:27, endln:39:40 |vpiParent: - \_module: work@socket_1n (work@socket_1n), file:${SURELOG_DIR}/tests/ElabCParam/dut.sv, line:38:1, endln:51:10 + \_module_inst: work@socket_1n (work@socket_1n), file:${SURELOG_DIR}/tests/ElabCParam/dut.sv, line:38:1, endln:51:10 |vpiRhs: \_constant: , line:39:39, endln:39:40 |vpiDecompile:2 @@ -2017,7 +2017,7 @@ design: (work@socket_1n) |vpiParamAssign: \_param_assign: , line:40:23, endln:40:44 |vpiParent: - \_module: work@socket_1n (work@socket_1n), file:${SURELOG_DIR}/tests/ElabCParam/dut.sv, line:38:1, endln:51:10 + \_module_inst: work@socket_1n (work@socket_1n), file:${SURELOG_DIR}/tests/ElabCParam/dut.sv, line:38:1, endln:51:10 |vpiRhs: \_constant: , line:40:35, endln:40:44 |vpiDecompile:8'b00100010 @@ -2039,7 +2039,7 @@ design: (work@socket_1n) |vpiParamAssign: \_param_assign: , line:41:23, endln:41:41 |vpiParent: - \_module: work@socket_1n (work@socket_1n), file:${SURELOG_DIR}/tests/ElabCParam/dut.sv, line:38:1, endln:51:10 + \_module_inst: work@socket_1n (work@socket_1n), file:${SURELOG_DIR}/tests/ElabCParam/dut.sv, line:38:1, endln:51:10 |vpiRhs: \_constant: , line:41:28, endln:41:41 |vpiDecompile:68 @@ -2053,7 +2053,7 @@ design: (work@socket_1n) |vpiParamAssign: \_param_assign: , line:42:23, endln:42:45 |vpiParent: - \_module: work@socket_1n (work@socket_1n), file:${SURELOG_DIR}/tests/ElabCParam/dut.sv, line:38:1, endln:51:10 + \_module_inst: work@socket_1n (work@socket_1n), file:${SURELOG_DIR}/tests/ElabCParam/dut.sv, line:38:1, endln:51:10 |vpiRhs: \_constant: , line:42:28, endln:42:45 |vpiDecompile:2 @@ -2070,7 +2070,7 @@ design: (work@socket_1n) |vpiGenScopeArray: \_gen_scope_array: (work@socket_1n.gen_dfifo[0]), line:44:36, endln:48:6 |vpiParent: - \_module: work@socket_1n (work@socket_1n), file:${SURELOG_DIR}/tests/ElabCParam/dut.sv, line:38:1, endln:51:10 + \_module_inst: work@socket_1n (work@socket_1n), file:${SURELOG_DIR}/tests/ElabCParam/dut.sv, line:38:1, endln:51:10 |vpiName:gen_dfifo[0] |vpiFullName:work@socket_1n.gen_dfifo[0] |vpiGenScope: @@ -2088,8 +2088,8 @@ design: (work@socket_1n) |vpiLocalParam:1 |vpiName:i |vpiFullName:work@socket_1n.gen_dfifo[0].i - |vpiModule: - \_module: work@fifo_sync (work@socket_1n.gen_dfifo[0].fifo_d), file:${SURELOG_DIR}/tests/ElabCParam/dut.sv, line:45:5, endln:47:17 + |vpiModuleInst: + \_module_inst: work@fifo_sync (work@socket_1n.gen_dfifo[0].fifo_d), file:${SURELOG_DIR}/tests/ElabCParam/dut.sv, line:45:5, endln:47:17 |vpiParent: \_gen_scope: (work@socket_1n.gen_dfifo[0]) |vpiName:fifo_d @@ -2108,7 +2108,7 @@ design: (work@socket_1n) |vpiParamAssign: \_param_assign: , line:25:26, endln:25:38 |vpiParent: - \_module: work@fifo_sync (work@socket_1n.gen_dfifo[0].fifo_d), file:${SURELOG_DIR}/tests/ElabCParam/dut.sv, line:45:5, endln:47:17 + \_module_inst: work@fifo_sync (work@socket_1n.gen_dfifo[0].fifo_d), file:${SURELOG_DIR}/tests/ElabCParam/dut.sv, line:45:5, endln:47:17 |vpiOverriden:1 |vpiRhs: \_constant: , line:25:37, endln:25:38 @@ -2123,10 +2123,10 @@ design: (work@socket_1n) |vpiDefName:work@fifo_sync |vpiDefFile:${SURELOG_DIR}/tests/ElabCParam/dut.sv |vpiDefLineNo:24 - |vpiModule: - \_module: work@prim_fifo_sync (work@socket_1n.gen_dfifo[0].fifo_d.reqfifo), file:${SURELOG_DIR}/tests/ElabCParam/dut.sv, line:30:3, endln:30:49 + |vpiModuleInst: + \_module_inst: work@prim_fifo_sync (work@socket_1n.gen_dfifo[0].fifo_d.reqfifo), file:${SURELOG_DIR}/tests/ElabCParam/dut.sv, line:30:3, endln:30:49 |vpiParent: - \_module: work@fifo_sync (work@socket_1n.gen_dfifo[0].fifo_d), file:${SURELOG_DIR}/tests/ElabCParam/dut.sv, line:45:5, endln:47:17 + \_module_inst: work@fifo_sync (work@socket_1n.gen_dfifo[0].fifo_d), file:${SURELOG_DIR}/tests/ElabCParam/dut.sv, line:45:5, endln:47:17 |vpiName:reqfifo |vpiFullName:work@socket_1n.gen_dfifo[0].fifo_d.reqfifo |vpiParameter: @@ -2143,7 +2143,7 @@ design: (work@socket_1n) |vpiParamAssign: \_param_assign: , line:3:26, endln:3:41 |vpiParent: - \_module: work@prim_fifo_sync (work@socket_1n.gen_dfifo[0].fifo_d.reqfifo), file:${SURELOG_DIR}/tests/ElabCParam/dut.sv, line:30:3, endln:30:49 + \_module_inst: work@prim_fifo_sync (work@socket_1n.gen_dfifo[0].fifo_d.reqfifo), file:${SURELOG_DIR}/tests/ElabCParam/dut.sv, line:30:3, endln:30:49 |vpiOverriden:1 |vpiRhs: \_constant: , line:3:40, endln:3:41 @@ -2159,11 +2159,11 @@ design: (work@socket_1n) |vpiDefFile:${SURELOG_DIR}/tests/ElabCParam/dut.sv |vpiDefLineNo:2 |vpiInstance: - \_module: work@fifo_sync (work@socket_1n.gen_dfifo[0].fifo_d), file:${SURELOG_DIR}/tests/ElabCParam/dut.sv, line:45:5, endln:47:17 + \_module_inst: work@fifo_sync (work@socket_1n.gen_dfifo[0].fifo_d), file:${SURELOG_DIR}/tests/ElabCParam/dut.sv, line:45:5, endln:47:17 |vpiGenScopeArray: \_gen_scope_array: (work@socket_1n.gen_dfifo[0].fifo_d.reqfifo.gen_normal), line:15:12, endln:20:6 |vpiParent: - \_module: work@prim_fifo_sync (work@socket_1n.gen_dfifo[0].fifo_d.reqfifo), file:${SURELOG_DIR}/tests/ElabCParam/dut.sv, line:30:3, endln:30:49 + \_module_inst: work@prim_fifo_sync (work@socket_1n.gen_dfifo[0].fifo_d.reqfifo), file:${SURELOG_DIR}/tests/ElabCParam/dut.sv, line:30:3, endln:30:49 |vpiName:gen_normal |vpiFullName:work@socket_1n.gen_dfifo[0].fifo_d.reqfifo.gen_normal |vpiGenScope: @@ -2202,7 +2202,7 @@ design: (work@socket_1n) |vpiGenScopeArray: \_gen_scope_array: (work@socket_1n.gen_dfifo[1]), line:44:36, endln:48:6 |vpiParent: - \_module: work@socket_1n (work@socket_1n), file:${SURELOG_DIR}/tests/ElabCParam/dut.sv, line:38:1, endln:51:10 + \_module_inst: work@socket_1n (work@socket_1n), file:${SURELOG_DIR}/tests/ElabCParam/dut.sv, line:38:1, endln:51:10 |vpiName:gen_dfifo[1] |vpiFullName:work@socket_1n.gen_dfifo[1] |vpiGenScope: @@ -2220,8 +2220,8 @@ design: (work@socket_1n) |vpiLocalParam:1 |vpiName:i |vpiFullName:work@socket_1n.gen_dfifo[1].i - |vpiModule: - \_module: work@fifo_sync (work@socket_1n.gen_dfifo[1].fifo_d), file:${SURELOG_DIR}/tests/ElabCParam/dut.sv, line:45:5, endln:47:17 + |vpiModuleInst: + \_module_inst: work@fifo_sync (work@socket_1n.gen_dfifo[1].fifo_d), file:${SURELOG_DIR}/tests/ElabCParam/dut.sv, line:45:5, endln:47:17 |vpiParent: \_gen_scope: (work@socket_1n.gen_dfifo[1]) |vpiName:fifo_d @@ -2240,7 +2240,7 @@ design: (work@socket_1n) |vpiParamAssign: \_param_assign: , line:25:26, endln:25:38 |vpiParent: - \_module: work@fifo_sync (work@socket_1n.gen_dfifo[1].fifo_d), file:${SURELOG_DIR}/tests/ElabCParam/dut.sv, line:45:5, endln:47:17 + \_module_inst: work@fifo_sync (work@socket_1n.gen_dfifo[1].fifo_d), file:${SURELOG_DIR}/tests/ElabCParam/dut.sv, line:45:5, endln:47:17 |vpiOverriden:1 |vpiRhs: \_constant: , line:25:37, endln:25:38 @@ -2255,10 +2255,10 @@ design: (work@socket_1n) |vpiDefName:work@fifo_sync |vpiDefFile:${SURELOG_DIR}/tests/ElabCParam/dut.sv |vpiDefLineNo:24 - |vpiModule: - \_module: work@prim_fifo_sync (work@socket_1n.gen_dfifo[1].fifo_d.reqfifo), file:${SURELOG_DIR}/tests/ElabCParam/dut.sv, line:30:3, endln:30:49 + |vpiModuleInst: + \_module_inst: work@prim_fifo_sync (work@socket_1n.gen_dfifo[1].fifo_d.reqfifo), file:${SURELOG_DIR}/tests/ElabCParam/dut.sv, line:30:3, endln:30:49 |vpiParent: - \_module: work@fifo_sync (work@socket_1n.gen_dfifo[1].fifo_d), file:${SURELOG_DIR}/tests/ElabCParam/dut.sv, line:45:5, endln:47:17 + \_module_inst: work@fifo_sync (work@socket_1n.gen_dfifo[1].fifo_d), file:${SURELOG_DIR}/tests/ElabCParam/dut.sv, line:45:5, endln:47:17 |vpiName:reqfifo |vpiFullName:work@socket_1n.gen_dfifo[1].fifo_d.reqfifo |vpiParameter: @@ -2275,7 +2275,7 @@ design: (work@socket_1n) |vpiParamAssign: \_param_assign: , line:3:26, endln:3:41 |vpiParent: - \_module: work@prim_fifo_sync (work@socket_1n.gen_dfifo[1].fifo_d.reqfifo), file:${SURELOG_DIR}/tests/ElabCParam/dut.sv, line:30:3, endln:30:49 + \_module_inst: work@prim_fifo_sync (work@socket_1n.gen_dfifo[1].fifo_d.reqfifo), file:${SURELOG_DIR}/tests/ElabCParam/dut.sv, line:30:3, endln:30:49 |vpiOverriden:1 |vpiRhs: \_constant: , line:3:40, endln:3:41 @@ -2291,11 +2291,11 @@ design: (work@socket_1n) |vpiDefFile:${SURELOG_DIR}/tests/ElabCParam/dut.sv |vpiDefLineNo:2 |vpiInstance: - \_module: work@fifo_sync (work@socket_1n.gen_dfifo[1].fifo_d), file:${SURELOG_DIR}/tests/ElabCParam/dut.sv, line:45:5, endln:47:17 + \_module_inst: work@fifo_sync (work@socket_1n.gen_dfifo[1].fifo_d), file:${SURELOG_DIR}/tests/ElabCParam/dut.sv, line:45:5, endln:47:17 |vpiGenScopeArray: \_gen_scope_array: (work@socket_1n.gen_dfifo[1].fifo_d.reqfifo.gen_normal), line:15:12, endln:20:6 |vpiParent: - \_module: work@prim_fifo_sync (work@socket_1n.gen_dfifo[1].fifo_d.reqfifo), file:${SURELOG_DIR}/tests/ElabCParam/dut.sv, line:30:3, endln:30:49 + \_module_inst: work@prim_fifo_sync (work@socket_1n.gen_dfifo[1].fifo_d.reqfifo), file:${SURELOG_DIR}/tests/ElabCParam/dut.sv, line:30:3, endln:30:49 |vpiName:gen_normal |vpiFullName:work@socket_1n.gen_dfifo[1].fifo_d.reqfifo.gen_normal |vpiGenScope: @@ -2332,12 +2332,12 @@ design: (work@socket_1n) |vpiLhs: \_parameter: (work@socket_1n.gen_dfifo[1].fifo_d.reqfifo.gen_normal.PTRV_W), line:18:29, endln:18:35 |uhdmtopModules: -\_module: work@all_zero (work@all_zero), file:${SURELOG_DIR}/tests/ElabCParam/dut.sv, line:54:1, endln:67:10 +\_module_inst: work@all_zero (work@all_zero), file:${SURELOG_DIR}/tests/ElabCParam/dut.sv, line:54:1, endln:67:10 |vpiName:work@all_zero |vpiParameter: \_parameter: (work@all_zero.N), line:55:27, endln:55:28 |vpiParent: - \_module: work@all_zero (work@all_zero), file:${SURELOG_DIR}/tests/ElabCParam/dut.sv, line:54:1, endln:67:10 + \_module_inst: work@all_zero (work@all_zero), file:${SURELOG_DIR}/tests/ElabCParam/dut.sv, line:54:1, endln:67:10 |UINT:2 |vpiTypespec: \_int_typespec: , line:55:13, endln:55:25 @@ -2348,7 +2348,7 @@ design: (work@socket_1n) |vpiParameter: \_parameter: (work@all_zero.DReqDepth), line:56:23, endln:56:32 |vpiParent: - \_module: work@all_zero (work@all_zero), file:${SURELOG_DIR}/tests/ElabCParam/dut.sv, line:54:1, endln:67:10 + \_module_inst: work@all_zero (work@all_zero), file:${SURELOG_DIR}/tests/ElabCParam/dut.sv, line:54:1, endln:67:10 |vpiTypespec: \_bit_typespec: , line:56:13, endln:56:22 |vpiParent: @@ -2379,7 +2379,7 @@ design: (work@socket_1n) |vpiParameter: \_parameter: (work@all_zero.AA), line:57:23, endln:57:25 |vpiParent: - \_module: work@all_zero (work@all_zero), file:${SURELOG_DIR}/tests/ElabCParam/dut.sv, line:54:1, endln:67:10 + \_module_inst: work@all_zero (work@all_zero), file:${SURELOG_DIR}/tests/ElabCParam/dut.sv, line:54:1, endln:67:10 |vpiTypespec: \_bit_typespec: , line:57:13, endln:57:22 |vpiParent: @@ -2410,7 +2410,7 @@ design: (work@socket_1n) |vpiParameter: \_parameter: (work@all_zero.BB), line:58:23, endln:58:25 |vpiParent: - \_module: work@all_zero (work@all_zero), file:${SURELOG_DIR}/tests/ElabCParam/dut.sv, line:54:1, endln:67:10 + \_module_inst: work@all_zero (work@all_zero), file:${SURELOG_DIR}/tests/ElabCParam/dut.sv, line:54:1, endln:67:10 |vpiTypespec: \_bit_typespec: , line:58:13, endln:58:22 |vpiParent: @@ -2441,7 +2441,7 @@ design: (work@socket_1n) |vpiParamAssign: \_param_assign: , line:55:27, endln:55:40 |vpiParent: - \_module: work@all_zero (work@all_zero), file:${SURELOG_DIR}/tests/ElabCParam/dut.sv, line:54:1, endln:67:10 + \_module_inst: work@all_zero (work@all_zero), file:${SURELOG_DIR}/tests/ElabCParam/dut.sv, line:54:1, endln:67:10 |vpiRhs: \_constant: , line:55:39, endln:55:40 |vpiDecompile:2 @@ -2455,7 +2455,7 @@ design: (work@socket_1n) |vpiParamAssign: \_param_assign: , line:56:23, endln:56:44 |vpiParent: - \_module: work@all_zero (work@all_zero), file:${SURELOG_DIR}/tests/ElabCParam/dut.sv, line:54:1, endln:67:10 + \_module_inst: work@all_zero (work@all_zero), file:${SURELOG_DIR}/tests/ElabCParam/dut.sv, line:54:1, endln:67:10 |vpiRhs: \_constant: , line:56:35, endln:56:44 |vpiDecompile:8'b00000000 @@ -2477,7 +2477,7 @@ design: (work@socket_1n) |vpiParamAssign: \_param_assign: , line:57:23, endln:57:41 |vpiParent: - \_module: work@all_zero (work@all_zero), file:${SURELOG_DIR}/tests/ElabCParam/dut.sv, line:54:1, endln:67:10 + \_module_inst: work@all_zero (work@all_zero), file:${SURELOG_DIR}/tests/ElabCParam/dut.sv, line:54:1, endln:67:10 |vpiRhs: \_constant: , line:57:28, endln:57:41 |vpiDecompile:0 @@ -2491,7 +2491,7 @@ design: (work@socket_1n) |vpiParamAssign: \_param_assign: , line:58:23, endln:58:45 |vpiParent: - \_module: work@all_zero (work@all_zero), file:${SURELOG_DIR}/tests/ElabCParam/dut.sv, line:54:1, endln:67:10 + \_module_inst: work@all_zero (work@all_zero), file:${SURELOG_DIR}/tests/ElabCParam/dut.sv, line:54:1, endln:67:10 |vpiRhs: \_constant: , line:58:28, endln:58:45 |vpiDecompile:0 @@ -2508,7 +2508,7 @@ design: (work@socket_1n) |vpiGenScopeArray: \_gen_scope_array: (work@all_zero.gen_dfifo[0]), line:60:36, endln:64:6 |vpiParent: - \_module: work@all_zero (work@all_zero), file:${SURELOG_DIR}/tests/ElabCParam/dut.sv, line:54:1, endln:67:10 + \_module_inst: work@all_zero (work@all_zero), file:${SURELOG_DIR}/tests/ElabCParam/dut.sv, line:54:1, endln:67:10 |vpiName:gen_dfifo[0] |vpiFullName:work@all_zero.gen_dfifo[0] |vpiGenScope: @@ -2526,8 +2526,8 @@ design: (work@socket_1n) |vpiLocalParam:1 |vpiName:i |vpiFullName:work@all_zero.gen_dfifo[0].i - |vpiModule: - \_module: work@fifo_sync (work@all_zero.gen_dfifo[0].fifo_d), file:${SURELOG_DIR}/tests/ElabCParam/dut.sv, line:61:5, endln:63:17 + |vpiModuleInst: + \_module_inst: work@fifo_sync (work@all_zero.gen_dfifo[0].fifo_d), file:${SURELOG_DIR}/tests/ElabCParam/dut.sv, line:61:5, endln:63:17 |vpiParent: \_gen_scope: (work@all_zero.gen_dfifo[0]) |vpiName:fifo_d @@ -2546,7 +2546,7 @@ design: (work@socket_1n) |vpiParamAssign: \_param_assign: , line:25:26, endln:25:38 |vpiParent: - \_module: work@fifo_sync (work@all_zero.gen_dfifo[0].fifo_d), file:${SURELOG_DIR}/tests/ElabCParam/dut.sv, line:61:5, endln:63:17 + \_module_inst: work@fifo_sync (work@all_zero.gen_dfifo[0].fifo_d), file:${SURELOG_DIR}/tests/ElabCParam/dut.sv, line:61:5, endln:63:17 |vpiOverriden:1 |vpiRhs: \_constant: , line:25:37, endln:25:38 @@ -2561,10 +2561,10 @@ design: (work@socket_1n) |vpiDefName:work@fifo_sync |vpiDefFile:${SURELOG_DIR}/tests/ElabCParam/dut.sv |vpiDefLineNo:24 - |vpiModule: - \_module: work@prim_fifo_sync (work@all_zero.gen_dfifo[0].fifo_d.reqfifo), file:${SURELOG_DIR}/tests/ElabCParam/dut.sv, line:30:3, endln:30:49 + |vpiModuleInst: + \_module_inst: work@prim_fifo_sync (work@all_zero.gen_dfifo[0].fifo_d.reqfifo), file:${SURELOG_DIR}/tests/ElabCParam/dut.sv, line:30:3, endln:30:49 |vpiParent: - \_module: work@fifo_sync (work@all_zero.gen_dfifo[0].fifo_d), file:${SURELOG_DIR}/tests/ElabCParam/dut.sv, line:61:5, endln:63:17 + \_module_inst: work@fifo_sync (work@all_zero.gen_dfifo[0].fifo_d), file:${SURELOG_DIR}/tests/ElabCParam/dut.sv, line:61:5, endln:63:17 |vpiName:reqfifo |vpiFullName:work@all_zero.gen_dfifo[0].fifo_d.reqfifo |vpiParameter: @@ -2581,7 +2581,7 @@ design: (work@socket_1n) |vpiParamAssign: \_param_assign: , line:3:26, endln:3:41 |vpiParent: - \_module: work@prim_fifo_sync (work@all_zero.gen_dfifo[0].fifo_d.reqfifo), file:${SURELOG_DIR}/tests/ElabCParam/dut.sv, line:30:3, endln:30:49 + \_module_inst: work@prim_fifo_sync (work@all_zero.gen_dfifo[0].fifo_d.reqfifo), file:${SURELOG_DIR}/tests/ElabCParam/dut.sv, line:30:3, endln:30:49 |vpiOverriden:1 |vpiRhs: \_constant: , line:3:40, endln:3:41 @@ -2597,11 +2597,11 @@ design: (work@socket_1n) |vpiDefFile:${SURELOG_DIR}/tests/ElabCParam/dut.sv |vpiDefLineNo:2 |vpiInstance: - \_module: work@fifo_sync (work@all_zero.gen_dfifo[0].fifo_d), file:${SURELOG_DIR}/tests/ElabCParam/dut.sv, line:61:5, endln:63:17 + \_module_inst: work@fifo_sync (work@all_zero.gen_dfifo[0].fifo_d), file:${SURELOG_DIR}/tests/ElabCParam/dut.sv, line:61:5, endln:63:17 |vpiGenScopeArray: \_gen_scope_array: (work@all_zero.gen_dfifo[0].fifo_d.reqfifo.gen_passthru), line:8:3, endln:20:6 |vpiParent: - \_module: work@prim_fifo_sync (work@all_zero.gen_dfifo[0].fifo_d.reqfifo), file:${SURELOG_DIR}/tests/ElabCParam/dut.sv, line:30:3, endln:30:49 + \_module_inst: work@prim_fifo_sync (work@all_zero.gen_dfifo[0].fifo_d.reqfifo), file:${SURELOG_DIR}/tests/ElabCParam/dut.sv, line:30:3, endln:30:49 |vpiName:gen_passthru |vpiFullName:work@all_zero.gen_dfifo[0].fifo_d.reqfifo.gen_passthru |vpiGenScope: @@ -2630,7 +2630,7 @@ design: (work@socket_1n) |vpiGenScopeArray: \_gen_scope_array: (work@all_zero.gen_dfifo[1]), line:60:36, endln:64:6 |vpiParent: - \_module: work@all_zero (work@all_zero), file:${SURELOG_DIR}/tests/ElabCParam/dut.sv, line:54:1, endln:67:10 + \_module_inst: work@all_zero (work@all_zero), file:${SURELOG_DIR}/tests/ElabCParam/dut.sv, line:54:1, endln:67:10 |vpiName:gen_dfifo[1] |vpiFullName:work@all_zero.gen_dfifo[1] |vpiGenScope: @@ -2648,8 +2648,8 @@ design: (work@socket_1n) |vpiLocalParam:1 |vpiName:i |vpiFullName:work@all_zero.gen_dfifo[1].i - |vpiModule: - \_module: work@fifo_sync (work@all_zero.gen_dfifo[1].fifo_d), file:${SURELOG_DIR}/tests/ElabCParam/dut.sv, line:61:5, endln:63:17 + |vpiModuleInst: + \_module_inst: work@fifo_sync (work@all_zero.gen_dfifo[1].fifo_d), file:${SURELOG_DIR}/tests/ElabCParam/dut.sv, line:61:5, endln:63:17 |vpiParent: \_gen_scope: (work@all_zero.gen_dfifo[1]) |vpiName:fifo_d @@ -2668,7 +2668,7 @@ design: (work@socket_1n) |vpiParamAssign: \_param_assign: , line:25:26, endln:25:38 |vpiParent: - \_module: work@fifo_sync (work@all_zero.gen_dfifo[1].fifo_d), file:${SURELOG_DIR}/tests/ElabCParam/dut.sv, line:61:5, endln:63:17 + \_module_inst: work@fifo_sync (work@all_zero.gen_dfifo[1].fifo_d), file:${SURELOG_DIR}/tests/ElabCParam/dut.sv, line:61:5, endln:63:17 |vpiOverriden:1 |vpiRhs: \_constant: , line:25:37, endln:25:38 @@ -2683,10 +2683,10 @@ design: (work@socket_1n) |vpiDefName:work@fifo_sync |vpiDefFile:${SURELOG_DIR}/tests/ElabCParam/dut.sv |vpiDefLineNo:24 - |vpiModule: - \_module: work@prim_fifo_sync (work@all_zero.gen_dfifo[1].fifo_d.reqfifo), file:${SURELOG_DIR}/tests/ElabCParam/dut.sv, line:30:3, endln:30:49 + |vpiModuleInst: + \_module_inst: work@prim_fifo_sync (work@all_zero.gen_dfifo[1].fifo_d.reqfifo), file:${SURELOG_DIR}/tests/ElabCParam/dut.sv, line:30:3, endln:30:49 |vpiParent: - \_module: work@fifo_sync (work@all_zero.gen_dfifo[1].fifo_d), file:${SURELOG_DIR}/tests/ElabCParam/dut.sv, line:61:5, endln:63:17 + \_module_inst: work@fifo_sync (work@all_zero.gen_dfifo[1].fifo_d), file:${SURELOG_DIR}/tests/ElabCParam/dut.sv, line:61:5, endln:63:17 |vpiName:reqfifo |vpiFullName:work@all_zero.gen_dfifo[1].fifo_d.reqfifo |vpiParameter: @@ -2703,7 +2703,7 @@ design: (work@socket_1n) |vpiParamAssign: \_param_assign: , line:3:26, endln:3:41 |vpiParent: - \_module: work@prim_fifo_sync (work@all_zero.gen_dfifo[1].fifo_d.reqfifo), file:${SURELOG_DIR}/tests/ElabCParam/dut.sv, line:30:3, endln:30:49 + \_module_inst: work@prim_fifo_sync (work@all_zero.gen_dfifo[1].fifo_d.reqfifo), file:${SURELOG_DIR}/tests/ElabCParam/dut.sv, line:30:3, endln:30:49 |vpiOverriden:1 |vpiRhs: \_constant: , line:3:40, endln:3:41 @@ -2719,11 +2719,11 @@ design: (work@socket_1n) |vpiDefFile:${SURELOG_DIR}/tests/ElabCParam/dut.sv |vpiDefLineNo:2 |vpiInstance: - \_module: work@fifo_sync (work@all_zero.gen_dfifo[1].fifo_d), file:${SURELOG_DIR}/tests/ElabCParam/dut.sv, line:61:5, endln:63:17 + \_module_inst: work@fifo_sync (work@all_zero.gen_dfifo[1].fifo_d), file:${SURELOG_DIR}/tests/ElabCParam/dut.sv, line:61:5, endln:63:17 |vpiGenScopeArray: \_gen_scope_array: (work@all_zero.gen_dfifo[1].fifo_d.reqfifo.gen_passthru), line:8:3, endln:20:6 |vpiParent: - \_module: work@prim_fifo_sync (work@all_zero.gen_dfifo[1].fifo_d.reqfifo), file:${SURELOG_DIR}/tests/ElabCParam/dut.sv, line:30:3, endln:30:49 + \_module_inst: work@prim_fifo_sync (work@all_zero.gen_dfifo[1].fifo_d.reqfifo), file:${SURELOG_DIR}/tests/ElabCParam/dut.sv, line:30:3, endln:30:49 |vpiName:gen_passthru |vpiFullName:work@all_zero.gen_dfifo[1].fifo_d.reqfifo.gen_passthru |vpiGenScope: diff --git a/tests/ElabIf/ElabIf.log b/tests/ElabIf/ElabIf.log index 3c99e7ce1b..8a852c0ce7 100644 --- a/tests/ElabIf/ElabIf.log +++ b/tests/ElabIf/ElabIf.log @@ -61,7 +61,7 @@ int_typespec 15 int_var 4 io_decl 11 logic_var 1 -module 16 +module_inst 16 operation 3 package 2 param_assign 6 @@ -88,7 +88,7 @@ int_typespec 15 int_var 4 io_decl 22 logic_var 1 -module 16 +module_inst 16 operation 4 package 2 param_assign 6 @@ -584,14 +584,14 @@ design: (work@top) \_int_typespec: |vpiSigned:1 |uhdmallModules: -\_module: work@assigner (work@assigner), file:${SURELOG_DIR}/tests/ElabIf/dut.sv, line:6:1, endln:11:10 +\_module_inst: work@assigner (work@assigner), file:${SURELOG_DIR}/tests/ElabIf/dut.sv, line:6:1, endln:11:10 |vpiParent: \_design: (work@top) |vpiFullName:work@assigner |vpiParameter: \_parameter: (work@assigner.invert), line:6:29, endln:6:35 |vpiParent: - \_module: work@assigner (work@assigner), file:${SURELOG_DIR}/tests/ElabIf/dut.sv, line:6:1, endln:11:10 + \_module_inst: work@assigner (work@assigner), file:${SURELOG_DIR}/tests/ElabIf/dut.sv, line:6:1, endln:11:10 |UINT:0 |vpiTypespec: \_int_typespec: @@ -600,7 +600,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:6:29, endln:6:39 |vpiParent: - \_module: work@assigner (work@assigner), file:${SURELOG_DIR}/tests/ElabIf/dut.sv, line:6:1, endln:11:10 + \_module_inst: work@assigner (work@assigner), file:${SURELOG_DIR}/tests/ElabIf/dut.sv, line:6:1, endln:11:10 |vpiRhs: \_constant: , line:6:38, endln:6:39 |vpiDecompile:0 @@ -613,14 +613,14 @@ design: (work@top) \_parameter: (work@assigner.invert), line:6:29, endln:6:35 |vpiDefName:work@assigner |uhdmallModules: -\_module: work@middleman (work@middleman), file:${SURELOG_DIR}/tests/ElabIf/dut.sv, line:13:1, endln:15:10 +\_module_inst: work@middleman (work@middleman), file:${SURELOG_DIR}/tests/ElabIf/dut.sv, line:13:1, endln:15:10 |vpiParent: \_design: (work@top) |vpiFullName:work@middleman |vpiParameter: \_parameter: (work@middleman.invert), line:13:30, endln:13:36 |vpiParent: - \_module: work@middleman (work@middleman), file:${SURELOG_DIR}/tests/ElabIf/dut.sv, line:13:1, endln:15:10 + \_module_inst: work@middleman (work@middleman), file:${SURELOG_DIR}/tests/ElabIf/dut.sv, line:13:1, endln:15:10 |UINT:0 |vpiTypespec: \_int_typespec: @@ -629,7 +629,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:13:30, endln:13:40 |vpiParent: - \_module: work@middleman (work@middleman), file:${SURELOG_DIR}/tests/ElabIf/dut.sv, line:13:1, endln:15:10 + \_module_inst: work@middleman (work@middleman), file:${SURELOG_DIR}/tests/ElabIf/dut.sv, line:13:1, endln:15:10 |vpiRhs: \_constant: , line:13:39, endln:13:40 |vpiDecompile:0 @@ -642,27 +642,27 @@ design: (work@top) \_parameter: (work@middleman.invert), line:13:30, endln:13:36 |vpiDefName:work@middleman |uhdmallModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/ElabIf/dut.sv, line:1:1, endln:4:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ElabIf/dut.sv, line:1:1, endln:4:10 |vpiParent: \_design: (work@top) |vpiFullName:work@top |vpiDefName:work@top |uhdmtopModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/ElabIf/dut.sv, line:1:1, endln:4:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ElabIf/dut.sv, line:1:1, endln:4:10 |vpiName:work@top |vpiDefName:work@top |vpiTop:1 |vpiTopModule:1 - |vpiModule: - \_module: work@middleman (work@top.mdl1), file:${SURELOG_DIR}/tests/ElabIf/dut.sv, line:2:4, endln:2:35 + |vpiModuleInst: + \_module_inst: work@middleman (work@top.mdl1), file:${SURELOG_DIR}/tests/ElabIf/dut.sv, line:2:4, endln:2:35 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ElabIf/dut.sv, line:1:1, endln:4:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ElabIf/dut.sv, line:1:1, endln:4:10 |vpiName:mdl1 |vpiFullName:work@top.mdl1 |vpiParameter: \_parameter: (work@top.mdl1.invert), line:13:30, endln:13:36 |vpiParent: - \_module: work@middleman (work@top.mdl1), file:${SURELOG_DIR}/tests/ElabIf/dut.sv, line:2:4, endln:2:35 + \_module_inst: work@middleman (work@top.mdl1), file:${SURELOG_DIR}/tests/ElabIf/dut.sv, line:2:4, endln:2:35 |UINT:0 |vpiTypespec: \_int_typespec: @@ -673,7 +673,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:13:30, endln:13:40 |vpiParent: - \_module: work@middleman (work@top.mdl1), file:${SURELOG_DIR}/tests/ElabIf/dut.sv, line:2:4, endln:2:35 + \_module_inst: work@middleman (work@top.mdl1), file:${SURELOG_DIR}/tests/ElabIf/dut.sv, line:2:4, endln:2:35 |vpiOverriden:1 |vpiRhs: \_constant: , line:13:39, endln:13:40 @@ -689,17 +689,17 @@ design: (work@top) |vpiDefFile:${SURELOG_DIR}/tests/ElabIf/dut.sv |vpiDefLineNo:13 |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ElabIf/dut.sv, line:1:1, endln:4:10 - |vpiModule: - \_module: work@assigner (work@top.mdl1.asgn), file:${SURELOG_DIR}/tests/ElabIf/dut.sv, line:14:4, endln:14:39 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ElabIf/dut.sv, line:1:1, endln:4:10 + |vpiModuleInst: + \_module_inst: work@assigner (work@top.mdl1.asgn), file:${SURELOG_DIR}/tests/ElabIf/dut.sv, line:14:4, endln:14:39 |vpiParent: - \_module: work@middleman (work@top.mdl1), file:${SURELOG_DIR}/tests/ElabIf/dut.sv, line:2:4, endln:2:35 + \_module_inst: work@middleman (work@top.mdl1), file:${SURELOG_DIR}/tests/ElabIf/dut.sv, line:2:4, endln:2:35 |vpiName:asgn |vpiFullName:work@top.mdl1.asgn |vpiParameter: \_parameter: (work@top.mdl1.asgn.invert), line:6:29, endln:6:35 |vpiParent: - \_module: work@assigner (work@top.mdl1.asgn), file:${SURELOG_DIR}/tests/ElabIf/dut.sv, line:14:4, endln:14:39 + \_module_inst: work@assigner (work@top.mdl1.asgn), file:${SURELOG_DIR}/tests/ElabIf/dut.sv, line:14:4, endln:14:39 |UINT:0 |vpiTypespec: \_int_typespec: @@ -710,7 +710,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:6:29, endln:6:39 |vpiParent: - \_module: work@assigner (work@top.mdl1.asgn), file:${SURELOG_DIR}/tests/ElabIf/dut.sv, line:14:4, endln:14:39 + \_module_inst: work@assigner (work@top.mdl1.asgn), file:${SURELOG_DIR}/tests/ElabIf/dut.sv, line:14:4, endln:14:39 |vpiOverriden:1 |vpiRhs: \_constant: , line:6:38, endln:6:39 @@ -726,11 +726,11 @@ design: (work@top) |vpiDefFile:${SURELOG_DIR}/tests/ElabIf/dut.sv |vpiDefLineNo:6 |vpiInstance: - \_module: work@middleman (work@top.mdl1), file:${SURELOG_DIR}/tests/ElabIf/dut.sv, line:2:4, endln:2:35 + \_module_inst: work@middleman (work@top.mdl1), file:${SURELOG_DIR}/tests/ElabIf/dut.sv, line:2:4, endln:2:35 |vpiGenScopeArray: \_gen_scope_array: (work@top.mdl1.asgn.genblk2), line:9:3, endln:10:23 |vpiParent: - \_module: work@assigner (work@top.mdl1.asgn), file:${SURELOG_DIR}/tests/ElabIf/dut.sv, line:14:4, endln:14:39 + \_module_inst: work@assigner (work@top.mdl1.asgn), file:${SURELOG_DIR}/tests/ElabIf/dut.sv, line:14:4, endln:14:39 |vpiName:genblk2 |vpiFullName:work@top.mdl1.asgn.genblk2 |vpiGenScope: @@ -759,16 +759,16 @@ design: (work@top) \_cont_assign: , line:10:12, endln:10:22 |vpiName:out |vpiFullName:work@top.mdl1.asgn.genblk2.out - |vpiModule: - \_module: work@middleman (work@top.mdl0), file:${SURELOG_DIR}/tests/ElabIf/dut.sv, line:3:4, endln:3:35 + |vpiModuleInst: + \_module_inst: work@middleman (work@top.mdl0), file:${SURELOG_DIR}/tests/ElabIf/dut.sv, line:3:4, endln:3:35 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ElabIf/dut.sv, line:1:1, endln:4:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ElabIf/dut.sv, line:1:1, endln:4:10 |vpiName:mdl0 |vpiFullName:work@top.mdl0 |vpiParameter: \_parameter: (work@top.mdl0.invert), line:13:30, endln:13:36 |vpiParent: - \_module: work@middleman (work@top.mdl0), file:${SURELOG_DIR}/tests/ElabIf/dut.sv, line:3:4, endln:3:35 + \_module_inst: work@middleman (work@top.mdl0), file:${SURELOG_DIR}/tests/ElabIf/dut.sv, line:3:4, endln:3:35 |UINT:0 |vpiTypespec: \_int_typespec: @@ -779,7 +779,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:13:30, endln:13:40 |vpiParent: - \_module: work@middleman (work@top.mdl0), file:${SURELOG_DIR}/tests/ElabIf/dut.sv, line:3:4, endln:3:35 + \_module_inst: work@middleman (work@top.mdl0), file:${SURELOG_DIR}/tests/ElabIf/dut.sv, line:3:4, endln:3:35 |vpiOverriden:1 |vpiRhs: \_constant: , line:13:39, endln:13:40 @@ -795,17 +795,17 @@ design: (work@top) |vpiDefFile:${SURELOG_DIR}/tests/ElabIf/dut.sv |vpiDefLineNo:13 |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ElabIf/dut.sv, line:1:1, endln:4:10 - |vpiModule: - \_module: work@assigner (work@top.mdl0.asgn), file:${SURELOG_DIR}/tests/ElabIf/dut.sv, line:14:4, endln:14:39 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ElabIf/dut.sv, line:1:1, endln:4:10 + |vpiModuleInst: + \_module_inst: work@assigner (work@top.mdl0.asgn), file:${SURELOG_DIR}/tests/ElabIf/dut.sv, line:14:4, endln:14:39 |vpiParent: - \_module: work@middleman (work@top.mdl0), file:${SURELOG_DIR}/tests/ElabIf/dut.sv, line:3:4, endln:3:35 + \_module_inst: work@middleman (work@top.mdl0), file:${SURELOG_DIR}/tests/ElabIf/dut.sv, line:3:4, endln:3:35 |vpiName:asgn |vpiFullName:work@top.mdl0.asgn |vpiParameter: \_parameter: (work@top.mdl0.asgn.invert), line:6:29, endln:6:35 |vpiParent: - \_module: work@assigner (work@top.mdl0.asgn), file:${SURELOG_DIR}/tests/ElabIf/dut.sv, line:14:4, endln:14:39 + \_module_inst: work@assigner (work@top.mdl0.asgn), file:${SURELOG_DIR}/tests/ElabIf/dut.sv, line:14:4, endln:14:39 |UINT:0 |vpiTypespec: \_int_typespec: @@ -816,7 +816,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:6:29, endln:6:39 |vpiParent: - \_module: work@assigner (work@top.mdl0.asgn), file:${SURELOG_DIR}/tests/ElabIf/dut.sv, line:14:4, endln:14:39 + \_module_inst: work@assigner (work@top.mdl0.asgn), file:${SURELOG_DIR}/tests/ElabIf/dut.sv, line:14:4, endln:14:39 |vpiOverriden:1 |vpiRhs: \_constant: , line:6:38, endln:6:39 @@ -832,11 +832,11 @@ design: (work@top) |vpiDefFile:${SURELOG_DIR}/tests/ElabIf/dut.sv |vpiDefLineNo:6 |vpiInstance: - \_module: work@middleman (work@top.mdl0), file:${SURELOG_DIR}/tests/ElabIf/dut.sv, line:3:4, endln:3:35 + \_module_inst: work@middleman (work@top.mdl0), file:${SURELOG_DIR}/tests/ElabIf/dut.sv, line:3:4, endln:3:35 |vpiGenScopeArray: \_gen_scope_array: (work@top.mdl0.asgn.genblk1), line:7:3, endln:8:22 |vpiParent: - \_module: work@assigner (work@top.mdl0.asgn), file:${SURELOG_DIR}/tests/ElabIf/dut.sv, line:14:4, endln:14:39 + \_module_inst: work@assigner (work@top.mdl0.asgn), file:${SURELOG_DIR}/tests/ElabIf/dut.sv, line:14:4, endln:14:39 |vpiName:genblk1 |vpiFullName:work@top.mdl0.asgn.genblk1 |vpiGenScope: diff --git a/tests/ElabParam/ElabParam.log b/tests/ElabParam/ElabParam.log index 57eb9a3142..8ff9fd3dd3 100644 --- a/tests/ElabParam/ElabParam.log +++ b/tests/ElabParam/ElabParam.log @@ -504,7 +504,7 @@ io_decl 11 logic_net 4 logic_typespec 8 logic_var 1 -module 5 +module_inst 5 operation 8 package 5 param_assign 4 @@ -534,7 +534,7 @@ io_decl 22 logic_net 4 logic_typespec 8 logic_var 1 -module 5 +module_inst 5 operation 12 package 5 param_assign 4 @@ -1183,7 +1183,7 @@ design: (work@dut) \_int_typespec: |vpiSigned:1 |uhdmallModules: -\_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/ElabParam/dut.sv, line:11:2, endln:18:11 +\_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/ElabParam/dut.sv, line:11:2, endln:18:11 |vpiParent: \_design: (work@dut) |vpiFullName:work@dut @@ -1191,21 +1191,21 @@ design: (work@dut) |vpiNet: \_logic_net: (work@dut.a), line:14:15, endln:14:16 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/ElabParam/dut.sv, line:11:2, endln:18:11 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/ElabParam/dut.sv, line:11:2, endln:18:11 |vpiName:a |vpiFullName:work@dut.a |vpiNetType:1 |vpiNet: \_logic_net: (work@dut.b), line:15:14, endln:15:15 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/ElabParam/dut.sv, line:11:2, endln:18:11 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/ElabParam/dut.sv, line:11:2, endln:18:11 |vpiName:b |vpiFullName:work@dut.b |vpiNetType:48 |vpiPort: \_port: (a), line:11:14, endln:11:15 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/ElabParam/dut.sv, line:11:2, endln:18:11 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/ElabParam/dut.sv, line:11:2, endln:18:11 |vpiName:a |vpiDirection:1 |vpiLowConn: @@ -1235,7 +1235,7 @@ design: (work@dut) |vpiPort: \_port: (b), line:11:17, endln:11:18 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/ElabParam/dut.sv, line:11:2, endln:18:11 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/ElabParam/dut.sv, line:11:2, endln:18:11 |vpiName:b |vpiDirection:2 |vpiLowConn: @@ -1265,7 +1265,7 @@ design: (work@dut) |vpiContAssign: \_cont_assign: , line:16:11, endln:17:46 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/ElabParam/dut.sv, line:11:2, endln:18:11 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/ElabParam/dut.sv, line:11:2, endln:18:11 |vpiRhs: \_operation: , line:16:15, endln:17:46 |vpiParent: @@ -1325,14 +1325,14 @@ design: (work@dut) |vpiActual: \_logic_net: (work@dut.b), line:15:14, endln:15:15 |uhdmtopModules: -\_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/ElabParam/dut.sv, line:11:2, endln:18:11 +\_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/ElabParam/dut.sv, line:11:2, endln:18:11 |vpiName:work@dut |vpiDefName:work@dut |vpiTop:1 |vpiNet: \_logic_net: (work@dut.a), line:14:15, endln:14:16 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/ElabParam/dut.sv, line:11:2, endln:18:11 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/ElabParam/dut.sv, line:11:2, endln:18:11 |vpiTypespec: \_logic_typespec: , line:14:4, endln:14:14 |vpiRange: @@ -1359,7 +1359,7 @@ design: (work@dut) |vpiNet: \_logic_net: (work@dut.b), line:15:14, endln:15:15 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/ElabParam/dut.sv, line:11:2, endln:18:11 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/ElabParam/dut.sv, line:11:2, endln:18:11 |vpiTypespec: \_logic_typespec: , line:15:4, endln:15:13 |vpiRange: @@ -1387,7 +1387,7 @@ design: (work@dut) |vpiPort: \_port: (a), line:11:14, endln:11:15 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/ElabParam/dut.sv, line:11:2, endln:18:11 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/ElabParam/dut.sv, line:11:2, endln:18:11 |vpiName:a |vpiDirection:1 |vpiLowConn: @@ -1421,11 +1421,11 @@ design: (work@dut) |UINT:0 |vpiConstType:9 |vpiInstance: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/ElabParam/dut.sv, line:11:2, endln:18:11 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/ElabParam/dut.sv, line:11:2, endln:18:11 |vpiPort: \_port: (b), line:11:17, endln:11:18 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/ElabParam/dut.sv, line:11:2, endln:18:11 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/ElabParam/dut.sv, line:11:2, endln:18:11 |vpiName:b |vpiDirection:2 |vpiLowConn: @@ -1459,11 +1459,11 @@ design: (work@dut) |UINT:0 |vpiConstType:9 |vpiInstance: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/ElabParam/dut.sv, line:11:2, endln:18:11 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/ElabParam/dut.sv, line:11:2, endln:18:11 |vpiContAssign: \_cont_assign: , line:16:11, endln:17:46 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/ElabParam/dut.sv, line:11:2, endln:18:11 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/ElabParam/dut.sv, line:11:2, endln:18:11 |vpiRhs: \_operation: , line:16:15, endln:17:46 |vpiParent: diff --git a/tests/EmptyAssign/EmptyAssign.log b/tests/EmptyAssign/EmptyAssign.log index 8383a7b0b7..6f9b64041b 100644 --- a/tests/EmptyAssign/EmptyAssign.log +++ b/tests/EmptyAssign/EmptyAssign.log @@ -189,7 +189,7 @@ design 1 if_else 1 initial 1 int_typespec 6 -module 7 +module_inst 7 operation 1 param_assign 6 parameter 6 @@ -205,7 +205,7 @@ design 1 if_else 2 initial 2 int_typespec 6 -module 7 +module_inst 7 operation 2 param_assign 6 parameter 6 @@ -225,14 +225,14 @@ design: (work@top) |vpiElaborated:1 |vpiName:work@top |uhdmallModules: -\_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/EmptyAssign/dut.sv, line:1:1, endln:11:10 +\_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/EmptyAssign/dut.sv, line:1:1, endln:11:10 |vpiParent: \_design: (work@top) |vpiFullName:work@dut |vpiParameter: \_parameter: (work@dut.a), line:1:24, endln:1:25 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/EmptyAssign/dut.sv, line:1:1, endln:11:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/EmptyAssign/dut.sv, line:1:1, endln:11:10 |UINT:1 |vpiTypespec: \_int_typespec: @@ -241,7 +241,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@dut.b), line:1:31, endln:1:32 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/EmptyAssign/dut.sv, line:1:1, endln:11:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/EmptyAssign/dut.sv, line:1:1, endln:11:10 |UINT:2 |vpiTypespec: \_int_typespec: @@ -250,7 +250,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@dut.c), line:1:38, endln:1:39 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/EmptyAssign/dut.sv, line:1:1, endln:11:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/EmptyAssign/dut.sv, line:1:1, endln:11:10 |UINT:3 |vpiTypespec: \_int_typespec: @@ -259,7 +259,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:1:24, endln:1:29 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/EmptyAssign/dut.sv, line:1:1, endln:11:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/EmptyAssign/dut.sv, line:1:1, endln:11:10 |vpiRhs: \_constant: , line:1:28, endln:1:29 |vpiDecompile:1 @@ -273,7 +273,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:1:31, endln:1:36 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/EmptyAssign/dut.sv, line:1:1, endln:11:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/EmptyAssign/dut.sv, line:1:1, endln:11:10 |vpiRhs: \_constant: , line:1:35, endln:1:36 |vpiDecompile:2 @@ -287,7 +287,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:1:38, endln:1:43 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/EmptyAssign/dut.sv, line:1:1, endln:11:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/EmptyAssign/dut.sv, line:1:1, endln:11:10 |vpiRhs: \_constant: , line:1:42, endln:1:43 |vpiDecompile:3 @@ -302,7 +302,7 @@ design: (work@top) |vpiProcess: \_initial: , line:3:1, endln:9:4 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/EmptyAssign/dut.sv, line:1:1, endln:11:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/EmptyAssign/dut.sv, line:1:1, endln:11:10 |vpiStmt: \_begin: (work@dut), line:3:9, endln:9:4 |vpiParent: @@ -389,27 +389,27 @@ design: (work@top) |vpiConstType:6 |vpiName:$display |uhdmallModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/EmptyAssign/dut.sv, line:13:1, endln:17:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/EmptyAssign/dut.sv, line:13:1, endln:17:10 |vpiParent: \_design: (work@top) |vpiFullName:work@top |vpiDefName:work@top |uhdmtopModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/EmptyAssign/dut.sv, line:13:1, endln:17:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/EmptyAssign/dut.sv, line:13:1, endln:17:10 |vpiName:work@top |vpiDefName:work@top |vpiTop:1 |vpiTopModule:1 - |vpiModule: - \_module: work@dut (work@top.dut), file:${SURELOG_DIR}/tests/EmptyAssign/dut.sv, line:15:1, endln:15:33 + |vpiModuleInst: + \_module_inst: work@dut (work@top.dut), file:${SURELOG_DIR}/tests/EmptyAssign/dut.sv, line:15:1, endln:15:33 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/EmptyAssign/dut.sv, line:13:1, endln:17:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/EmptyAssign/dut.sv, line:13:1, endln:17:10 |vpiName:dut |vpiFullName:work@top.dut |vpiParameter: \_parameter: (work@top.dut.a), line:1:24, endln:1:25 |vpiParent: - \_module: work@dut (work@top.dut), file:${SURELOG_DIR}/tests/EmptyAssign/dut.sv, line:15:1, endln:15:33 + \_module_inst: work@dut (work@top.dut), file:${SURELOG_DIR}/tests/EmptyAssign/dut.sv, line:15:1, endln:15:33 |UINT:1 |vpiTypespec: \_int_typespec: @@ -420,7 +420,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.dut.b), line:1:31, endln:1:32 |vpiParent: - \_module: work@dut (work@top.dut), file:${SURELOG_DIR}/tests/EmptyAssign/dut.sv, line:15:1, endln:15:33 + \_module_inst: work@dut (work@top.dut), file:${SURELOG_DIR}/tests/EmptyAssign/dut.sv, line:15:1, endln:15:33 |UINT:2 |vpiTypespec: \_int_typespec: @@ -431,7 +431,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.dut.c), line:1:38, endln:1:39 |vpiParent: - \_module: work@dut (work@top.dut), file:${SURELOG_DIR}/tests/EmptyAssign/dut.sv, line:15:1, endln:15:33 + \_module_inst: work@dut (work@top.dut), file:${SURELOG_DIR}/tests/EmptyAssign/dut.sv, line:15:1, endln:15:33 |UINT:3 |vpiTypespec: \_int_typespec: @@ -442,7 +442,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:1:24, endln:1:29 |vpiParent: - \_module: work@dut (work@top.dut), file:${SURELOG_DIR}/tests/EmptyAssign/dut.sv, line:15:1, endln:15:33 + \_module_inst: work@dut (work@top.dut), file:${SURELOG_DIR}/tests/EmptyAssign/dut.sv, line:15:1, endln:15:33 |vpiOverriden:1 |vpiRhs: \_constant: , line:1:28, endln:1:29 @@ -457,7 +457,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:1:31, endln:1:36 |vpiParent: - \_module: work@dut (work@top.dut), file:${SURELOG_DIR}/tests/EmptyAssign/dut.sv, line:15:1, endln:15:33 + \_module_inst: work@dut (work@top.dut), file:${SURELOG_DIR}/tests/EmptyAssign/dut.sv, line:15:1, endln:15:33 |vpiRhs: \_constant: , line:1:35, endln:1:36 |vpiDecompile:2 @@ -471,7 +471,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:1:38, endln:1:43 |vpiParent: - \_module: work@dut (work@top.dut), file:${SURELOG_DIR}/tests/EmptyAssign/dut.sv, line:15:1, endln:15:33 + \_module_inst: work@dut (work@top.dut), file:${SURELOG_DIR}/tests/EmptyAssign/dut.sv, line:15:1, endln:15:33 |vpiOverriden:1 |vpiRhs: \_constant: , line:1:42, endln:1:43 @@ -487,11 +487,11 @@ design: (work@top) |vpiDefFile:${SURELOG_DIR}/tests/EmptyAssign/dut.sv |vpiDefLineNo:1 |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/EmptyAssign/dut.sv, line:13:1, endln:17:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/EmptyAssign/dut.sv, line:13:1, endln:17:10 |vpiProcess: \_initial: , line:3:1, endln:9:4 |vpiParent: - \_module: work@dut (work@top.dut), file:${SURELOG_DIR}/tests/EmptyAssign/dut.sv, line:15:1, endln:15:33 + \_module_inst: work@dut (work@top.dut), file:${SURELOG_DIR}/tests/EmptyAssign/dut.sv, line:15:1, endln:15:33 |vpiStmt: \_begin: (work@top.dut), line:3:9, endln:9:4 |vpiParent: diff --git a/tests/EnumConcat/EnumConcat.log b/tests/EnumConcat/EnumConcat.log index 5b4c18287c..589421f3a9 100644 --- a/tests/EnumConcat/EnumConcat.log +++ b/tests/EnumConcat/EnumConcat.log @@ -118,7 +118,7 @@ enum_typespec 1 gen_scope 2 gen_scope_array 2 logic_typespec 1 -module 6 +module_inst 6 operation 3 range 1 === UHDM Object Stats End === @@ -132,7 +132,7 @@ enum_typespec 1 gen_scope 3 gen_scope_array 3 logic_typespec 1 -module 7 +module_inst 7 operation 3 range 1 === UHDM Object Stats End === @@ -149,23 +149,23 @@ design: (work@dut) |vpiElaborated:1 |vpiName:work@dut |uhdmallModules: -\_module: work@GOOD (work@GOOD), file:${SURELOG_DIR}/tests/EnumConcat/dut.sv, line:2:1, endln:3:10 +\_module_inst: work@GOOD (work@GOOD), file:${SURELOG_DIR}/tests/EnumConcat/dut.sv, line:2:1, endln:3:10 |vpiParent: \_design: (work@dut) |vpiFullName:work@GOOD |vpiDefName:work@GOOD |uhdmallModules: -\_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/EnumConcat/dut.sv, line:6:1, endln:15:10 +\_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/EnumConcat/dut.sv, line:6:1, endln:15:10 |vpiParent: \_design: (work@dut) |vpiFullName:work@dut |vpiTypedef: \_enum_typespec: (exc_cause_e), line:7:1, endln:9:15 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/EnumConcat/dut.sv, line:6:1, endln:15:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/EnumConcat/dut.sv, line:6:1, endln:15:10 |vpiName:exc_cause_e |vpiInstance: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/EnumConcat/dut.sv, line:6:1, endln:15:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/EnumConcat/dut.sv, line:6:1, endln:15:10 |vpiBaseTypespec: \_logic_typespec: , line:7:14, endln:7:25 |vpiRange: @@ -194,7 +194,7 @@ design: (work@dut) |vpiSize:6 |vpiDefName:work@dut |uhdmtopModules: -\_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/EnumConcat/dut.sv, line:6:1, endln:15:10 +\_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/EnumConcat/dut.sv, line:6:1, endln:15:10 |vpiName:work@dut |vpiTypedef: \_enum_typespec: (exc_cause_e), line:7:1, endln:9:15 @@ -204,7 +204,7 @@ design: (work@dut) |vpiGenScopeArray: \_gen_scope_array: (work@dut.genblk1), line:11:3, endln:13:6 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/EnumConcat/dut.sv, line:6:1, endln:15:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/EnumConcat/dut.sv, line:6:1, endln:15:10 |vpiName:genblk1 |vpiFullName:work@dut.genblk1 |vpiGenScope: @@ -212,8 +212,8 @@ design: (work@dut) |vpiParent: \_gen_scope_array: (work@dut.genblk1), line:11:3, endln:13:6 |vpiFullName:work@dut.genblk1 - |vpiModule: - \_module: work@GOOD (work@dut.genblk1.good), file:${SURELOG_DIR}/tests/EnumConcat/dut.sv, line:12:5, endln:12:17 + |vpiModuleInst: + \_module_inst: work@GOOD (work@dut.genblk1.good), file:${SURELOG_DIR}/tests/EnumConcat/dut.sv, line:12:5, endln:12:17 |vpiParent: \_gen_scope: (work@dut.genblk1) |vpiName:good diff --git a/tests/EnumConst/EnumConst.log b/tests/EnumConst/EnumConst.log index 0ef0e2b928..7a78836469 100644 --- a/tests/EnumConst/EnumConst.log +++ b/tests/EnumConst/EnumConst.log @@ -89,7 +89,7 @@ design 1 enum_const 2 enum_typespec 1 logic_typespec 1 -module 3 +module_inst 3 operation 4 range 1 === UHDM Object Stats End === @@ -105,17 +105,17 @@ range 1 design: (work@dut) |vpiName:work@dut |uhdmallModules: -\_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/EnumConst/dut.sv, line:1:1, endln:7:10 +\_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/EnumConst/dut.sv, line:1:1, endln:7:10 |vpiParent: \_design: (work@dut) |vpiFullName:work@dut |vpiTypedef: \_enum_typespec: (exc_cause_e), line:2:1, endln:5:15 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/EnumConst/dut.sv, line:1:1, endln:7:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/EnumConst/dut.sv, line:1:1, endln:7:10 |vpiName:exc_cause_e |vpiInstance: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/EnumConst/dut.sv, line:1:1, endln:7:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/EnumConst/dut.sv, line:1:1, endln:7:10 |vpiBaseTypespec: \_logic_typespec: , line:2:14, endln:2:25 |vpiRange: @@ -150,7 +150,7 @@ design: (work@dut) |vpiSize:6 |vpiDefName:work@dut |uhdmtopModules: -\_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/EnumConst/dut.sv, line:1:1, endln:7:10 +\_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/EnumConst/dut.sv, line:1:1, endln:7:10 |vpiName:work@dut |vpiTypedef: \_enum_typespec: (exc_cause_e), line:2:1, endln:5:15 diff --git a/tests/EnumConstConcat/EnumConstConcat.log b/tests/EnumConstConcat/EnumConstConcat.log index d5e68dec85..7aa8e1e6e5 100644 --- a/tests/EnumConstConcat/EnumConstConcat.log +++ b/tests/EnumConstConcat/EnumConstConcat.log @@ -190,7 +190,7 @@ gen_scope 2 gen_scope_array 2 int_typespec 5 logic_typespec 4 -module 9 +module_inst 9 operation 7 package 6 param_assign 4 @@ -209,7 +209,7 @@ gen_scope 3 gen_scope_array 3 int_typespec 5 logic_typespec 4 -module 10 +module_inst 10 operation 7 package 6 param_assign 4 @@ -481,19 +481,19 @@ design: (work@top) |vpiDefName:pkg |vpiTop:1 |uhdmallModules: -\_module: work@GOOD (work@GOOD), file:${SURELOG_DIR}/tests/EnumConstConcat/dut.sv, line:19:1, endln:20:10 +\_module_inst: work@GOOD (work@GOOD), file:${SURELOG_DIR}/tests/EnumConstConcat/dut.sv, line:19:1, endln:20:10 |vpiParent: \_design: (work@top) |vpiFullName:work@GOOD |vpiDefName:work@GOOD |uhdmallModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/EnumConstConcat/dut.sv, line:22:1, endln:28:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/EnumConstConcat/dut.sv, line:22:1, endln:28:10 |vpiParent: \_design: (work@top) |vpiFullName:work@top |vpiDefName:work@top |uhdmtopModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/EnumConstConcat/dut.sv, line:22:1, endln:28:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/EnumConstConcat/dut.sv, line:22:1, endln:28:10 |vpiName:work@top |vpiDefName:work@top |vpiTop:1 @@ -501,7 +501,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.genblk1), line:24:4, endln:26:7 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/EnumConstConcat/dut.sv, line:22:1, endln:28:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/EnumConstConcat/dut.sv, line:22:1, endln:28:10 |vpiName:genblk1 |vpiFullName:work@top.genblk1 |vpiGenScope: @@ -509,8 +509,8 @@ design: (work@top) |vpiParent: \_gen_scope_array: (work@top.genblk1), line:24:4, endln:26:7 |vpiFullName:work@top.genblk1 - |vpiModule: - \_module: work@GOOD (work@top.genblk1.good), file:${SURELOG_DIR}/tests/EnumConstConcat/dut.sv, line:25:7, endln:25:19 + |vpiModuleInst: + \_module_inst: work@GOOD (work@top.genblk1.good), file:${SURELOG_DIR}/tests/EnumConstConcat/dut.sv, line:25:7, endln:25:19 |vpiParent: \_gen_scope: (work@top.genblk1) |vpiName:good diff --git a/tests/EnumConstElab/EnumConstElab.log b/tests/EnumConstElab/EnumConstElab.log index 84df60cca9..7c6e9e21b5 100644 --- a/tests/EnumConstElab/EnumConstElab.log +++ b/tests/EnumConstElab/EnumConstElab.log @@ -355,7 +355,7 @@ int_typespec 2 int_var 1 logic_net 1 logic_typespec 38 -module 13 +module_inst 13 operation 17 param_assign 6 parameter 9 @@ -377,7 +377,7 @@ int_typespec 2 int_var 1 logic_net 1 logic_typespec 38 -module 13 +module_inst 13 operation 17 param_assign 6 parameter 9 @@ -401,14 +401,14 @@ design: (work@top) |vpiElaborated:1 |vpiName:work@top |uhdmallModules: -\_module: work@prim_subreg (work@prim_subreg), file:${SURELOG_DIR}/tests/EnumConstElab/dut.sv, line:1:1, endln:4:10 +\_module_inst: work@prim_subreg (work@prim_subreg), file:${SURELOG_DIR}/tests/EnumConstElab/dut.sv, line:1:1, endln:4:10 |vpiParent: \_design: (work@top) |vpiFullName:work@prim_subreg |vpiParameter: \_parameter: (work@prim_subreg.RESVAL), line:2:26, endln:2:32 |vpiParent: - \_module: work@prim_subreg (work@prim_subreg), file:${SURELOG_DIR}/tests/EnumConstElab/dut.sv, line:1:1, endln:4:10 + \_module_inst: work@prim_subreg (work@prim_subreg), file:${SURELOG_DIR}/tests/EnumConstElab/dut.sv, line:1:1, endln:4:10 |BIN:0 |vpiTypespec: \_logic_typespec: , line:2:14, endln:2:25 @@ -437,7 +437,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:2:26, endln:2:37 |vpiParent: - \_module: work@prim_subreg (work@prim_subreg), file:${SURELOG_DIR}/tests/EnumConstElab/dut.sv, line:1:1, endln:4:10 + \_module_inst: work@prim_subreg (work@prim_subreg), file:${SURELOG_DIR}/tests/EnumConstElab/dut.sv, line:1:1, endln:4:10 |vpiRhs: \_constant: , line:2:35, endln:2:37 |vpiDecompile:'0 @@ -452,25 +452,25 @@ design: (work@top) |vpiNet: \_logic_net: (work@prim_subreg.a), line:3:8, endln:3:9 |vpiParent: - \_module: work@prim_subreg (work@prim_subreg), file:${SURELOG_DIR}/tests/EnumConstElab/dut.sv, line:1:1, endln:4:10 + \_module_inst: work@prim_subreg (work@prim_subreg), file:${SURELOG_DIR}/tests/EnumConstElab/dut.sv, line:1:1, endln:4:10 |vpiName:a |vpiFullName:work@prim_subreg.a |uhdmallModules: -\_module: work@prim_subreg_shadow (work@prim_subreg_shadow), file:${SURELOG_DIR}/tests/EnumConstElab/dut.sv, line:6:1, endln:24:10 +\_module_inst: work@prim_subreg_shadow (work@prim_subreg_shadow), file:${SURELOG_DIR}/tests/EnumConstElab/dut.sv, line:6:1, endln:24:10 |vpiParent: \_design: (work@top) |vpiFullName:work@prim_subreg_shadow |vpiParameter: \_parameter: (work@prim_subreg_shadow.RESVAL), line:16:23, endln:16:29 |vpiParent: - \_module: work@prim_subreg_shadow (work@prim_subreg_shadow), file:${SURELOG_DIR}/tests/EnumConstElab/dut.sv, line:6:1, endln:24:10 + \_module_inst: work@prim_subreg_shadow (work@prim_subreg_shadow), file:${SURELOG_DIR}/tests/EnumConstElab/dut.sv, line:6:1, endln:24:10 |vpiTypespec: \_struct_typespec: (struct_t), line:7:12, endln:7:18 |vpiParent: - \_module: work@prim_subreg_shadow (work@prim_subreg_shadow), file:${SURELOG_DIR}/tests/EnumConstElab/dut.sv, line:6:1, endln:24:10 + \_module_inst: work@prim_subreg_shadow (work@prim_subreg_shadow), file:${SURELOG_DIR}/tests/EnumConstElab/dut.sv, line:6:1, endln:24:10 |vpiName:struct_t |vpiInstance: - \_module: work@prim_subreg_shadow (work@prim_subreg_shadow), file:${SURELOG_DIR}/tests/EnumConstElab/dut.sv, line:6:1, endln:24:10 + \_module_inst: work@prim_subreg_shadow (work@prim_subreg_shadow), file:${SURELOG_DIR}/tests/EnumConstElab/dut.sv, line:6:1, endln:24:10 |vpiPacked:1 |vpiTypespecMember: \_typespec_member: (a), line:8:19, endln:8:20 @@ -545,7 +545,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:16:23, endln:19:5 |vpiParent: - \_module: work@prim_subreg_shadow (work@prim_subreg_shadow), file:${SURELOG_DIR}/tests/EnumConstElab/dut.sv, line:6:1, endln:24:10 + \_module_inst: work@prim_subreg_shadow (work@prim_subreg_shadow), file:${SURELOG_DIR}/tests/EnumConstElab/dut.sv, line:6:1, endln:24:10 |vpiRhs: \_operation: , line:16:32, endln:19:5 |vpiOpType:75 @@ -576,10 +576,10 @@ design: (work@top) |vpiTypedef: \_enum_typespec: (enum_t), line:12:4, endln:14:13 |vpiParent: - \_module: work@prim_subreg_shadow (work@prim_subreg_shadow), file:${SURELOG_DIR}/tests/EnumConstElab/dut.sv, line:6:1, endln:24:10 + \_module_inst: work@prim_subreg_shadow (work@prim_subreg_shadow), file:${SURELOG_DIR}/tests/EnumConstElab/dut.sv, line:6:1, endln:24:10 |vpiName:enum_t |vpiInstance: - \_module: work@prim_subreg_shadow (work@prim_subreg_shadow), file:${SURELOG_DIR}/tests/EnumConstElab/dut.sv, line:6:1, endln:24:10 + \_module_inst: work@prim_subreg_shadow (work@prim_subreg_shadow), file:${SURELOG_DIR}/tests/EnumConstElab/dut.sv, line:6:1, endln:24:10 |vpiBaseTypespec: \_logic_typespec: , line:12:17, endln:12:28 |vpiRange: @@ -610,21 +610,21 @@ design: (work@top) \_struct_typespec: (struct_t), line:7:12, endln:7:18 |vpiDefName:work@prim_subreg_shadow |uhdmallModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/EnumConstElab/dut.sv, line:26:1, endln:44:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/EnumConstElab/dut.sv, line:26:1, endln:44:10 |vpiParent: \_design: (work@top) |vpiFullName:work@top |vpiParameter: \_parameter: (work@top.CTRL_RESET), line:36:23, endln:36:33 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/EnumConstElab/dut.sv, line:26:1, endln:44:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/EnumConstElab/dut.sv, line:26:1, endln:44:10 |vpiTypespec: \_struct_typespec: (struct_t), line:27:12, endln:27:18 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/EnumConstElab/dut.sv, line:26:1, endln:44:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/EnumConstElab/dut.sv, line:26:1, endln:44:10 |vpiName:struct_t |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/EnumConstElab/dut.sv, line:26:1, endln:44:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/EnumConstElab/dut.sv, line:26:1, endln:44:10 |vpiPacked:1 |vpiTypespecMember: \_typespec_member: (a), line:28:19, endln:28:20 @@ -699,7 +699,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:36:23, endln:39:5 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/EnumConstElab/dut.sv, line:26:1, endln:44:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/EnumConstElab/dut.sv, line:26:1, endln:44:10 |vpiRhs: \_operation: , line:36:36, endln:39:5 |vpiOpType:75 @@ -730,10 +730,10 @@ design: (work@top) |vpiTypedef: \_enum_typespec: (enum_t), line:32:4, endln:34:13 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/EnumConstElab/dut.sv, line:26:1, endln:44:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/EnumConstElab/dut.sv, line:26:1, endln:44:10 |vpiName:enum_t |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/EnumConstElab/dut.sv, line:26:1, endln:44:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/EnumConstElab/dut.sv, line:26:1, endln:44:10 |vpiBaseTypespec: \_logic_typespec: , line:32:17, endln:32:28 |vpiRange: @@ -764,19 +764,19 @@ design: (work@top) \_struct_typespec: (struct_t), line:27:12, endln:27:18 |vpiDefName:work@top |uhdmtopModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/EnumConstElab/dut.sv, line:26:1, endln:44:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/EnumConstElab/dut.sv, line:26:1, endln:44:10 |vpiName:work@top |vpiParameter: \_parameter: (work@top.CTRL_RESET), line:36:23, endln:36:33 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/EnumConstElab/dut.sv, line:26:1, endln:44:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/EnumConstElab/dut.sv, line:26:1, endln:44:10 |vpiTypespec: \_struct_typespec: (struct_t), line:27:12, endln:27:18 |vpiParent: \_parameter: (work@top.CTRL_RESET), line:36:23, endln:36:33 |vpiName:struct_t |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/EnumConstElab/dut.sv, line:26:1, endln:44:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/EnumConstElab/dut.sv, line:26:1, endln:44:10 |vpiPacked:1 |vpiTypespecMember: \_typespec_member: (a), line:28:19, endln:28:20 @@ -851,7 +851,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:36:23, endln:39:5 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/EnumConstElab/dut.sv, line:26:1, endln:44:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/EnumConstElab/dut.sv, line:26:1, endln:44:10 |vpiRhs: \_operation: , line:36:36, endln:39:5 |vpiParent: @@ -956,23 +956,23 @@ design: (work@top) |vpiDefName:work@top |vpiTop:1 |vpiTopModule:1 - |vpiModule: - \_module: work@prim_subreg_shadow (work@top.u_ctrl_reg_shadowed), file:${SURELOG_DIR}/tests/EnumConstElab/dut.sv, line:41:4, endln:43:29 + |vpiModuleInst: + \_module_inst: work@prim_subreg_shadow (work@top.u_ctrl_reg_shadowed), file:${SURELOG_DIR}/tests/EnumConstElab/dut.sv, line:41:4, endln:43:29 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/EnumConstElab/dut.sv, line:26:1, endln:44:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/EnumConstElab/dut.sv, line:26:1, endln:44:10 |vpiName:u_ctrl_reg_shadowed |vpiFullName:work@top.u_ctrl_reg_shadowed |vpiParameter: \_parameter: (work@top.u_ctrl_reg_shadowed.RESVAL), line:16:23, endln:16:29 |vpiParent: - \_module: work@prim_subreg_shadow (work@top.u_ctrl_reg_shadowed), file:${SURELOG_DIR}/tests/EnumConstElab/dut.sv, line:41:4, endln:43:29 + \_module_inst: work@prim_subreg_shadow (work@top.u_ctrl_reg_shadowed), file:${SURELOG_DIR}/tests/EnumConstElab/dut.sv, line:41:4, endln:43:29 |vpiTypespec: \_struct_typespec: (struct_t), line:7:12, endln:7:18 |vpiParent: \_parameter: (work@top.u_ctrl_reg_shadowed.RESVAL), line:16:23, endln:16:29 |vpiName:struct_t |vpiInstance: - \_module: work@prim_subreg_shadow (work@prim_subreg_shadow), file:${SURELOG_DIR}/tests/EnumConstElab/dut.sv, line:6:1, endln:24:10 + \_module_inst: work@prim_subreg_shadow (work@prim_subreg_shadow), file:${SURELOG_DIR}/tests/EnumConstElab/dut.sv, line:6:1, endln:24:10 |vpiPacked:1 |vpiTypespecMember: \_typespec_member: (a), line:8:19, endln:8:20 @@ -1047,7 +1047,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:16:23, endln:19:5 |vpiParent: - \_module: work@prim_subreg_shadow (work@top.u_ctrl_reg_shadowed), file:${SURELOG_DIR}/tests/EnumConstElab/dut.sv, line:41:4, endln:43:29 + \_module_inst: work@prim_subreg_shadow (work@top.u_ctrl_reg_shadowed), file:${SURELOG_DIR}/tests/EnumConstElab/dut.sv, line:41:4, endln:43:29 |vpiOverriden:1 |vpiRhs: \_operation: , line:42:15, endln:42:25 @@ -1154,17 +1154,17 @@ design: (work@top) |vpiDefFile:${SURELOG_DIR}/tests/EnumConstElab/dut.sv |vpiDefLineNo:6 |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/EnumConstElab/dut.sv, line:26:1, endln:44:10 - |vpiModule: - \_module: work@prim_subreg (work@top.u_ctrl_reg_shadowed.staged_reg), file:${SURELOG_DIR}/tests/EnumConstElab/dut.sv, line:21:4, endln:23:20 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/EnumConstElab/dut.sv, line:26:1, endln:44:10 + |vpiModuleInst: + \_module_inst: work@prim_subreg (work@top.u_ctrl_reg_shadowed.staged_reg), file:${SURELOG_DIR}/tests/EnumConstElab/dut.sv, line:21:4, endln:23:20 |vpiParent: - \_module: work@prim_subreg_shadow (work@top.u_ctrl_reg_shadowed), file:${SURELOG_DIR}/tests/EnumConstElab/dut.sv, line:41:4, endln:43:29 + \_module_inst: work@prim_subreg_shadow (work@top.u_ctrl_reg_shadowed), file:${SURELOG_DIR}/tests/EnumConstElab/dut.sv, line:41:4, endln:43:29 |vpiName:staged_reg |vpiFullName:work@top.u_ctrl_reg_shadowed.staged_reg |vpiVariables: \_int_var: (work@top.u_ctrl_reg_shadowed.staged_reg.a), line:3:8, endln:3:24 |vpiParent: - \_module: work@prim_subreg (work@top.u_ctrl_reg_shadowed.staged_reg), file:${SURELOG_DIR}/tests/EnumConstElab/dut.sv, line:21:4, endln:23:20 + \_module_inst: work@prim_subreg (work@top.u_ctrl_reg_shadowed.staged_reg), file:${SURELOG_DIR}/tests/EnumConstElab/dut.sv, line:21:4, endln:23:20 |vpiTypespec: \_int_typespec: , line:3:4, endln:3:7 |vpiSigned:1 @@ -1211,7 +1211,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.u_ctrl_reg_shadowed.staged_reg.RESVAL), line:2:26, endln:2:32 |vpiParent: - \_module: work@prim_subreg (work@top.u_ctrl_reg_shadowed.staged_reg), file:${SURELOG_DIR}/tests/EnumConstElab/dut.sv, line:21:4, endln:23:20 + \_module_inst: work@prim_subreg (work@top.u_ctrl_reg_shadowed.staged_reg), file:${SURELOG_DIR}/tests/EnumConstElab/dut.sv, line:21:4, endln:23:20 |BIN:0 |vpiTypespec: \_logic_typespec: , line:2:14, endln:2:25 @@ -1242,7 +1242,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:2:26, endln:2:37 |vpiParent: - \_module: work@prim_subreg (work@top.u_ctrl_reg_shadowed.staged_reg), file:${SURELOG_DIR}/tests/EnumConstElab/dut.sv, line:21:4, endln:23:20 + \_module_inst: work@prim_subreg (work@top.u_ctrl_reg_shadowed.staged_reg), file:${SURELOG_DIR}/tests/EnumConstElab/dut.sv, line:21:4, endln:23:20 |vpiOverriden:1 |vpiRhs: \_constant: , line:22:15, endln:22:21 @@ -1255,7 +1255,7 @@ design: (work@top) |vpiDefFile:${SURELOG_DIR}/tests/EnumConstElab/dut.sv |vpiDefLineNo:1 |vpiInstance: - \_module: work@prim_subreg_shadow (work@top.u_ctrl_reg_shadowed), file:${SURELOG_DIR}/tests/EnumConstElab/dut.sv, line:41:4, endln:43:29 + \_module_inst: work@prim_subreg_shadow (work@top.u_ctrl_reg_shadowed), file:${SURELOG_DIR}/tests/EnumConstElab/dut.sv, line:41:4, endln:43:29 =================== [ FATAL] : 0 [ SYNTAX] : 0 diff --git a/tests/EnumVal/EnumVal.log b/tests/EnumVal/EnumVal.log index 0a1ae3c9f2..a50a79b893 100644 --- a/tests/EnumVal/EnumVal.log +++ b/tests/EnumVal/EnumVal.log @@ -214,7 +214,7 @@ design 1 enum_const 12 enum_typespec 1 logic_typespec 1 -module 3 +module_inst 3 operation 24 range 1 === UHDM Object Stats End === @@ -226,7 +226,7 @@ design 1 enum_const 12 enum_typespec 1 logic_typespec 1 -module 3 +module_inst 3 operation 24 range 1 === UHDM Object Stats End === @@ -243,17 +243,17 @@ design: (work@top) |vpiElaborated:1 |vpiName:work@top |uhdmallModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/EnumVal/dut.sv, line:1:1, endln:16:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/EnumVal/dut.sv, line:1:1, endln:16:10 |vpiParent: \_design: (work@top) |vpiFullName:work@top |vpiTypedef: \_enum_typespec: (exc_cause_e), line:2:5, endln:15:19 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/EnumVal/dut.sv, line:1:1, endln:16:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/EnumVal/dut.sv, line:1:1, endln:16:10 |vpiName:exc_cause_e |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/EnumVal/dut.sv, line:1:1, endln:16:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/EnumVal/dut.sv, line:1:1, endln:16:10 |vpiBaseTypespec: \_logic_typespec: , line:2:18, endln:2:29 |vpiRange: @@ -348,7 +348,7 @@ design: (work@top) |vpiSize:6 |vpiDefName:work@top |uhdmtopModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/EnumVal/dut.sv, line:1:1, endln:16:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/EnumVal/dut.sv, line:1:1, endln:16:10 |vpiName:work@top |vpiTypedef: \_enum_typespec: (exc_cause_e), line:2:5, endln:15:19 diff --git a/tests/EnumVar/EnumVar.log b/tests/EnumVar/EnumVar.log index da07c67dcd..262921241c 100644 --- a/tests/EnumVar/EnumVar.log +++ b/tests/EnumVar/EnumVar.log @@ -112,7 +112,7 @@ enum_typespec 3 enum_var 2 logic_net 2 logic_typespec 3 -module 4 +module_inst 4 package 3 range 3 === UHDM Object Stats End === @@ -126,7 +126,7 @@ enum_typespec 3 enum_var 2 logic_net 2 logic_typespec 3 -module 4 +module_inst 4 package 3 range 3 === UHDM Object Stats End === @@ -311,7 +311,7 @@ design: (work@dut) |vpiDefName:pkg |vpiTop:1 |uhdmallModules: -\_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/EnumVar/dut.sv, line:11:1, endln:14:10 +\_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/EnumVar/dut.sv, line:11:1, endln:14:10 |vpiParent: \_design: (work@dut) |vpiFullName:work@dut @@ -319,22 +319,22 @@ design: (work@dut) |vpiNet: \_logic_net: (work@dut.a), line:12:15, endln:12:16 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/EnumVar/dut.sv, line:11:1, endln:14:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/EnumVar/dut.sv, line:11:1, endln:14:10 |vpiName:a |vpiFullName:work@dut.a |vpiNet: \_logic_net: (work@dut.b), line:13:16, endln:13:17 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/EnumVar/dut.sv, line:11:1, endln:14:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/EnumVar/dut.sv, line:11:1, endln:14:10 |vpiName:b |vpiFullName:work@dut.b |uhdmtopModules: -\_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/EnumVar/dut.sv, line:11:1, endln:14:10 +\_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/EnumVar/dut.sv, line:11:1, endln:14:10 |vpiName:work@dut |vpiVariables: \_enum_var: (work@dut.a), line:12:15, endln:12:16 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/EnumVar/dut.sv, line:11:1, endln:14:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/EnumVar/dut.sv, line:11:1, endln:14:10 |vpiTypespec: \_enum_typespec: (pkg::enum_t), line:2:3, endln:6:12 |vpiName:a @@ -343,7 +343,7 @@ design: (work@dut) |vpiVariables: \_enum_var: (work@dut.b), line:13:16, endln:13:17 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/EnumVar/dut.sv, line:11:1, endln:14:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/EnumVar/dut.sv, line:11:1, endln:14:10 |vpiTypespec: \_enum_typespec: (pkg::alias_t), line:2:3, endln:6:12 |vpiName:b diff --git a/tests/EnumVarNoTypedef/EnumVarNoTypedef.log b/tests/EnumVarNoTypedef/EnumVarNoTypedef.log index d4a9b18bae..5003315186 100644 --- a/tests/EnumVarNoTypedef/EnumVarNoTypedef.log +++ b/tests/EnumVarNoTypedef/EnumVarNoTypedef.log @@ -71,7 +71,7 @@ enum_typespec 1 enum_var 1 logic_net 1 logic_typespec 1 -module 3 +module_inst 3 range 1 === UHDM Object Stats End === [ERR:UH0721] ${SURELOG_DIR}/tests/EnumVarNoTypedef/dut.sv:4:4: Enum const size does not match base type size "Global", @@ -87,7 +87,7 @@ enum_typespec 1 enum_var 1 logic_net 1 logic_typespec 1 -module 3 +module_inst 3 range 1 === UHDM Object Stats End === [INF:UH0708] Writing UHDM DB: ${SURELOG_DIR}/build/regression/EnumVarNoTypedef/slpp_all/surelog.uhdm ... @@ -103,7 +103,7 @@ design: (work@top) |vpiElaborated:1 |vpiName:work@top |uhdmallModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/EnumVarNoTypedef/dut.sv, line:1:1, endln:7:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/EnumVarNoTypedef/dut.sv, line:1:1, endln:7:10 |vpiParent: \_design: (work@top) |vpiFullName:work@top @@ -111,16 +111,16 @@ design: (work@top) |vpiNet: \_logic_net: (work@top.myenum), line:5:4, endln:5:10 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/EnumVarNoTypedef/dut.sv, line:1:1, endln:7:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/EnumVarNoTypedef/dut.sv, line:1:1, endln:7:10 |vpiName:myenum |vpiFullName:work@top.myenum |uhdmtopModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/EnumVarNoTypedef/dut.sv, line:1:1, endln:7:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/EnumVarNoTypedef/dut.sv, line:1:1, endln:7:10 |vpiName:work@top |vpiVariables: \_enum_var: (work@top.myenum), line:5:4, endln:5:10 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/EnumVarNoTypedef/dut.sv, line:1:1, endln:7:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/EnumVarNoTypedef/dut.sv, line:1:1, endln:7:10 |vpiTypespec: \_enum_typespec: |vpiBaseTypespec: diff --git a/tests/Escape/Escape.log b/tests/Escape/Escape.log index 0f3ef7a73c..f57c5562bf 100644 --- a/tests/Escape/Escape.log +++ b/tests/Escape/Escape.log @@ -105,12 +105,12 @@ gate 1 immediate_assert 1 int_typespec 9 int_var 4 -interface 3 +interface_inst 3 io_decl 12 logic_net 25 logic_typespec 19 logic_var 1 -module 15 +module_inst 15 operation 2 package 2 port 18 diff --git a/tests/EvalFunc/EvalFunc.log b/tests/EvalFunc/EvalFunc.log index 83dc4b802b..2f6a15d6e3 100644 --- a/tests/EvalFunc/EvalFunc.log +++ b/tests/EvalFunc/EvalFunc.log @@ -761,7 +761,7 @@ integer_var 16 io_decl 8 logic_typespec 2 logic_var 1 -module 11 +module_inst 11 operation 23 package 3 param_assign 60 @@ -791,7 +791,7 @@ integer_var 21 io_decl 16 logic_typespec 2 logic_var 2 -module 11 +module_inst 11 operation 46 package 3 param_assign 60 @@ -1462,14 +1462,14 @@ design: (work@top) |vpiInstance: \_package: prim_util_pkg (prim_util_pkg::), file:${SURELOG_DIR}/tests/EvalFunc/dut.sv, line:1:1, endln:18:11 |uhdmallModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/EvalFunc/dut.sv, line:22:1, endln:68:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/EvalFunc/dut.sv, line:22:1, endln:68:10 |vpiParent: \_design: (work@top) |vpiFullName:work@top |vpiParameter: \_parameter: (work@top.RATIO), line:63:12, endln:63:17 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/EvalFunc/dut.sv, line:22:1, endln:68:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/EvalFunc/dut.sv, line:22:1, endln:68:10 |UINT:30 |vpiTypespec: \_int_typespec: @@ -1479,35 +1479,35 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.log2RATIO1), line:64:12, endln:64:22 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/EvalFunc/dut.sv, line:22:1, endln:68:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/EvalFunc/dut.sv, line:22:1, endln:68:10 |vpiLocalParam:1 |vpiName:log2RATIO1 |vpiFullName:work@top.log2RATIO1 |vpiParameter: \_parameter: (work@top.log2RATIO2), line:65:12, endln:65:22 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/EvalFunc/dut.sv, line:22:1, endln:68:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/EvalFunc/dut.sv, line:22:1, endln:68:10 |vpiLocalParam:1 |vpiName:log2RATIO2 |vpiFullName:work@top.log2RATIO2 |vpiParameter: \_parameter: (work@top.log2RATIO3), line:66:12, endln:66:22 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/EvalFunc/dut.sv, line:22:1, endln:68:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/EvalFunc/dut.sv, line:22:1, endln:68:10 |vpiLocalParam:1 |vpiName:log2RATIO3 |vpiFullName:work@top.log2RATIO3 |vpiParameter: \_parameter: (work@top.log2RATIO4), line:67:12, endln:67:22 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/EvalFunc/dut.sv, line:22:1, endln:68:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/EvalFunc/dut.sv, line:22:1, endln:68:10 |vpiLocalParam:1 |vpiName:log2RATIO4 |vpiFullName:work@top.log2RATIO4 |vpiParamAssign: \_param_assign: , line:63:12, endln:63:22 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/EvalFunc/dut.sv, line:22:1, endln:68:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/EvalFunc/dut.sv, line:22:1, endln:68:10 |vpiRhs: \_constant: , line:63:20, endln:63:22 |vpiDecompile:30 @@ -1521,7 +1521,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:64:12, endln:64:36 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/EvalFunc/dut.sv, line:22:1, endln:68:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/EvalFunc/dut.sv, line:22:1, endln:68:10 |vpiRhs: \_func_call: (log2), line:64:25, endln:64:29 |vpiArgument: @@ -1537,7 +1537,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:65:12, endln:65:37 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/EvalFunc/dut.sv, line:22:1, endln:68:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/EvalFunc/dut.sv, line:22:1, endln:68:10 |vpiRhs: \_func_call: (vbits), line:65:25, endln:65:30 |vpiArgument: @@ -1553,7 +1553,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:66:12, endln:66:38 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/EvalFunc/dut.sv, line:22:1, endln:68:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/EvalFunc/dut.sv, line:22:1, endln:68:10 |vpiRhs: \_func_call: (log2_2), line:66:25, endln:66:31 |vpiArgument: @@ -1569,7 +1569,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:67:12, endln:67:52 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/EvalFunc/dut.sv, line:22:1, endln:68:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/EvalFunc/dut.sv, line:22:1, endln:68:10 |vpiRhs: \_func_call: (prim_util_pkg::vbits), line:67:25, endln:67:40 |vpiArgument: @@ -1586,7 +1586,7 @@ design: (work@top) |vpiTaskFunc: \_function: (work@top.vbits), line:24:1, endln:26:12 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/EvalFunc/dut.sv, line:22:1, endln:68:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/EvalFunc/dut.sv, line:22:1, endln:68:10 |vpiName:vbits |vpiFullName:work@top.vbits |vpiVisibility:1 @@ -1598,7 +1598,7 @@ design: (work@top) |vpiSigned:1 |vpiSigned:1 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/EvalFunc/dut.sv, line:22:1, endln:68:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/EvalFunc/dut.sv, line:22:1, endln:68:10 |vpiIODecl: \_io_decl: (value), line:24:42, endln:24:47 |vpiDirection:1 @@ -1658,11 +1658,11 @@ design: (work@top) \_io_decl: (value), line:24:42, endln:24:47 |vpiName:$clog2 |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/EvalFunc/dut.sv, line:22:1, endln:68:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/EvalFunc/dut.sv, line:22:1, endln:68:10 |vpiTaskFunc: \_function: (work@top.foo), line:28:1, endln:31:12 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/EvalFunc/dut.sv, line:22:1, endln:68:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/EvalFunc/dut.sv, line:22:1, endln:68:10 |vpiName:foo |vpiFullName:work@top.foo |vpiVisibility:1 @@ -1673,7 +1673,7 @@ design: (work@top) |vpiSigned:1 |vpiSigned:1 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/EvalFunc/dut.sv, line:22:1, endln:68:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/EvalFunc/dut.sv, line:22:1, endln:68:10 |vpiIODecl: \_io_decl: (value), line:29:15, endln:29:20 |vpiParent: @@ -1696,11 +1696,11 @@ design: (work@top) |vpiActual: \_io_decl: (value), line:29:15, endln:29:20 |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/EvalFunc/dut.sv, line:22:1, endln:68:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/EvalFunc/dut.sv, line:22:1, endln:68:10 |vpiTaskFunc: \_function: (work@top.log2), line:33:1, endln:48:12 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/EvalFunc/dut.sv, line:22:1, endln:68:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/EvalFunc/dut.sv, line:22:1, endln:68:10 |vpiName:log2 |vpiFullName:work@top.log2 |vpiVariables: @@ -1745,7 +1745,7 @@ design: (work@top) |vpiSigned:1 |vpiSigned:1 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/EvalFunc/dut.sv, line:22:1, endln:68:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/EvalFunc/dut.sv, line:22:1, endln:68:10 |vpiIODecl: \_io_decl: (value), line:34:15, endln:34:20 |vpiParent: @@ -1984,11 +1984,11 @@ design: (work@top) |vpiActual: \_integer_var: (log2), line:33:10, endln:33:17 |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/EvalFunc/dut.sv, line:22:1, endln:68:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/EvalFunc/dut.sv, line:22:1, endln:68:10 |vpiTaskFunc: \_function: (work@top.log2_2), line:51:1, endln:61:12 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/EvalFunc/dut.sv, line:22:1, endln:68:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/EvalFunc/dut.sv, line:22:1, endln:68:10 |vpiName:log2_2 |vpiFullName:work@top.log2_2 |vpiVisibility:1 @@ -1999,7 +1999,7 @@ design: (work@top) |vpiSigned:1 |vpiSigned:1 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/EvalFunc/dut.sv, line:22:1, endln:68:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/EvalFunc/dut.sv, line:22:1, endln:68:10 |vpiIODecl: \_io_decl: (value), line:52:15, endln:52:20 |vpiParent: @@ -2192,14 +2192,14 @@ design: (work@top) |vpiActual: \_io_decl: (value), line:52:15, endln:52:20 |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/EvalFunc/dut.sv, line:22:1, endln:68:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/EvalFunc/dut.sv, line:22:1, endln:68:10 |uhdmtopModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/EvalFunc/dut.sv, line:22:1, endln:68:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/EvalFunc/dut.sv, line:22:1, endln:68:10 |vpiName:work@top |vpiParameter: \_parameter: (work@top.RATIO), line:63:12, endln:63:17 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/EvalFunc/dut.sv, line:22:1, endln:68:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/EvalFunc/dut.sv, line:22:1, endln:68:10 |UINT:30 |vpiTypespec: \_int_typespec: @@ -2211,35 +2211,35 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.log2RATIO1), line:64:12, endln:64:22 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/EvalFunc/dut.sv, line:22:1, endln:68:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/EvalFunc/dut.sv, line:22:1, endln:68:10 |vpiLocalParam:1 |vpiName:log2RATIO1 |vpiFullName:work@top.log2RATIO1 |vpiParameter: \_parameter: (work@top.log2RATIO2), line:65:12, endln:65:22 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/EvalFunc/dut.sv, line:22:1, endln:68:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/EvalFunc/dut.sv, line:22:1, endln:68:10 |vpiLocalParam:1 |vpiName:log2RATIO2 |vpiFullName:work@top.log2RATIO2 |vpiParameter: \_parameter: (work@top.log2RATIO3), line:66:12, endln:66:22 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/EvalFunc/dut.sv, line:22:1, endln:68:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/EvalFunc/dut.sv, line:22:1, endln:68:10 |vpiLocalParam:1 |vpiName:log2RATIO3 |vpiFullName:work@top.log2RATIO3 |vpiParameter: \_parameter: (work@top.log2RATIO4), line:67:12, endln:67:22 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/EvalFunc/dut.sv, line:22:1, endln:68:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/EvalFunc/dut.sv, line:22:1, endln:68:10 |vpiLocalParam:1 |vpiName:log2RATIO4 |vpiFullName:work@top.log2RATIO4 |vpiParamAssign: \_param_assign: , line:63:12, endln:63:22 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/EvalFunc/dut.sv, line:22:1, endln:68:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/EvalFunc/dut.sv, line:22:1, endln:68:10 |vpiRhs: \_constant: , line:63:20, endln:63:22 |vpiDecompile:30 @@ -2253,7 +2253,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:64:12, endln:64:36 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/EvalFunc/dut.sv, line:22:1, endln:68:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/EvalFunc/dut.sv, line:22:1, endln:68:10 |vpiRhs: \_constant: , line:64:25, endln:64:36 |vpiDecompile:5 @@ -2265,7 +2265,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:65:12, endln:65:37 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/EvalFunc/dut.sv, line:22:1, endln:68:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/EvalFunc/dut.sv, line:22:1, endln:68:10 |vpiRhs: \_constant: , line:65:25, endln:65:37 |vpiDecompile:5 @@ -2277,7 +2277,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:66:12, endln:66:38 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/EvalFunc/dut.sv, line:22:1, endln:68:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/EvalFunc/dut.sv, line:22:1, endln:68:10 |vpiRhs: \_constant: , line:66:25, endln:66:38 |vpiDecompile:5 @@ -2289,7 +2289,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:67:12, endln:67:52 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/EvalFunc/dut.sv, line:22:1, endln:68:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/EvalFunc/dut.sv, line:22:1, endln:68:10 |vpiRhs: \_constant: , line:67:25, endln:67:52 |vpiDecompile:5 @@ -2303,7 +2303,7 @@ design: (work@top) |vpiTaskFunc: \_function: (work@top.vbits), line:24:1, endln:26:12 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/EvalFunc/dut.sv, line:22:1, endln:68:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/EvalFunc/dut.sv, line:22:1, endln:68:10 |vpiName:vbits |vpiFullName:work@top.vbits |vpiVisibility:1 @@ -2311,7 +2311,7 @@ design: (work@top) |vpiReturn: \_integer_var: , line:24:20, endln:24:27 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/EvalFunc/dut.sv, line:22:1, endln:68:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/EvalFunc/dut.sv, line:22:1, endln:68:10 |vpiIODecl: \_io_decl: (value), line:24:42, endln:24:47 |vpiParent: @@ -2360,18 +2360,18 @@ design: (work@top) \_io_decl: (value), line:24:42, endln:24:47 |vpiName:$clog2 |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/EvalFunc/dut.sv, line:22:1, endln:68:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/EvalFunc/dut.sv, line:22:1, endln:68:10 |vpiTaskFunc: \_function: (work@top.foo), line:28:1, endln:31:12 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/EvalFunc/dut.sv, line:22:1, endln:68:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/EvalFunc/dut.sv, line:22:1, endln:68:10 |vpiName:foo |vpiFullName:work@top.foo |vpiVisibility:1 |vpiReturn: \_integer_var: , line:28:10, endln:28:17 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/EvalFunc/dut.sv, line:22:1, endln:68:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/EvalFunc/dut.sv, line:22:1, endln:68:10 |vpiIODecl: \_io_decl: (value), line:29:15, endln:29:20 |vpiParent: @@ -2393,11 +2393,11 @@ design: (work@top) |vpiActual: \_io_decl: (value), line:29:15, endln:29:20 |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/EvalFunc/dut.sv, line:22:1, endln:68:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/EvalFunc/dut.sv, line:22:1, endln:68:10 |vpiTaskFunc: \_function: (work@top.log2), line:33:1, endln:48:12 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/EvalFunc/dut.sv, line:22:1, endln:68:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/EvalFunc/dut.sv, line:22:1, endln:68:10 |vpiName:log2 |vpiFullName:work@top.log2 |vpiVariables: @@ -2423,7 +2423,7 @@ design: (work@top) |vpiReturn: \_integer_var: , line:33:10, endln:33:17 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/EvalFunc/dut.sv, line:22:1, endln:68:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/EvalFunc/dut.sv, line:22:1, endln:68:10 |vpiIODecl: \_io_decl: (value), line:34:15, endln:34:20 |vpiParent: @@ -2627,18 +2627,18 @@ design: (work@top) |vpiActual: \_integer_var: , line:33:10, endln:33:17 |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/EvalFunc/dut.sv, line:22:1, endln:68:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/EvalFunc/dut.sv, line:22:1, endln:68:10 |vpiTaskFunc: \_function: (work@top.log2_2), line:51:1, endln:61:12 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/EvalFunc/dut.sv, line:22:1, endln:68:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/EvalFunc/dut.sv, line:22:1, endln:68:10 |vpiName:log2_2 |vpiFullName:work@top.log2_2 |vpiVisibility:1 |vpiReturn: \_integer_var: , line:51:10, endln:51:17 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/EvalFunc/dut.sv, line:22:1, endln:68:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/EvalFunc/dut.sv, line:22:1, endln:68:10 |vpiIODecl: \_io_decl: (value), line:52:15, endln:52:20 |vpiParent: @@ -2800,7 +2800,7 @@ design: (work@top) |vpiActual: \_io_decl: (value), line:52:15, endln:52:20 |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/EvalFunc/dut.sv, line:22:1, endln:68:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/EvalFunc/dut.sv, line:22:1, endln:68:10 |vpiTopModule:1 =================== [ FATAL] : 0 diff --git a/tests/EvalFuncArray/EvalFuncArray.log b/tests/EvalFuncArray/EvalFuncArray.log index 7ae72150a6..2208c15c61 100644 --- a/tests/EvalFuncArray/EvalFuncArray.log +++ b/tests/EvalFuncArray/EvalFuncArray.log @@ -495,7 +495,7 @@ integer_typespec 2 integer_var 2 io_decl 13 logic_var 1 -module 11 +module_inst 11 operation 14 package 5 param_assign 20 @@ -530,7 +530,7 @@ integer_typespec 2 integer_var 2 io_decl 26 logic_var 1 -module 11 +module_inst 11 operation 22 package 5 param_assign 20 diff --git a/tests/EvalFuncCont/EvalFuncCont.log b/tests/EvalFuncCont/EvalFuncCont.log index 3e79be6ff6..aa33198884 100644 --- a/tests/EvalFuncCont/EvalFuncCont.log +++ b/tests/EvalFuncCont/EvalFuncCont.log @@ -600,7 +600,7 @@ io_decl 12 logic_net 4 logic_typespec 5 logic_var 1 -module 6 +module_inst 6 operation 10 package 2 param_assign 10 @@ -638,7 +638,7 @@ io_decl 24 logic_net 4 logic_typespec 5 logic_var 1 -module 6 +module_inst 6 operation 17 package 2 param_assign 10 @@ -1138,14 +1138,14 @@ design: (work@t) \_int_typespec: |vpiSigned:1 |uhdmallModules: -\_module: work@t (work@t), file:${SURELOG_DIR}/tests/EvalFuncCont/dut.sv, line:8:1, endln:35:10 +\_module_inst: work@t (work@t), file:${SURELOG_DIR}/tests/EvalFuncCont/dut.sv, line:8:1, endln:35:10 |vpiParent: \_design: (work@t) |vpiFullName:work@t |vpiParameter: \_parameter: (work@t.WIDTH), line:14:15, endln:14:20 |vpiParent: - \_module: work@t (work@t), file:${SURELOG_DIR}/tests/EvalFuncCont/dut.sv, line:8:1, endln:35:10 + \_module_inst: work@t (work@t), file:${SURELOG_DIR}/tests/EvalFuncCont/dut.sv, line:8:1, endln:35:10 |UINT:33 |vpiTypespec: \_int_typespec: @@ -1154,7 +1154,7 @@ design: (work@t) |vpiParameter: \_parameter: (work@t.MAX_WIDTH), line:15:15, endln:15:24 |vpiParent: - \_module: work@t (work@t), file:${SURELOG_DIR}/tests/EvalFuncCont/dut.sv, line:8:1, endln:35:10 + \_module_inst: work@t (work@t), file:${SURELOG_DIR}/tests/EvalFuncCont/dut.sv, line:8:1, endln:35:10 |UINT:11 |vpiTypespec: \_int_typespec: @@ -1164,14 +1164,14 @@ design: (work@t) |vpiParameter: \_parameter: (work@t.NUM_OUT), line:16:15, endln:16:22 |vpiParent: - \_module: work@t (work@t), file:${SURELOG_DIR}/tests/EvalFuncCont/dut.sv, line:8:1, endln:35:10 + \_module_inst: work@t (work@t), file:${SURELOG_DIR}/tests/EvalFuncCont/dut.sv, line:8:1, endln:35:10 |vpiLocalParam:1 |vpiName:NUM_OUT |vpiFullName:work@t.NUM_OUT |vpiParamAssign: \_param_assign: , line:14:15, endln:14:25 |vpiParent: - \_module: work@t (work@t), file:${SURELOG_DIR}/tests/EvalFuncCont/dut.sv, line:8:1, endln:35:10 + \_module_inst: work@t (work@t), file:${SURELOG_DIR}/tests/EvalFuncCont/dut.sv, line:8:1, endln:35:10 |vpiRhs: \_constant: , line:14:23, endln:14:25 |vpiDecompile:33 @@ -1185,7 +1185,7 @@ design: (work@t) |vpiParamAssign: \_param_assign: , line:15:15, endln:15:29 |vpiParent: - \_module: work@t (work@t), file:${SURELOG_DIR}/tests/EvalFuncCont/dut.sv, line:8:1, endln:35:10 + \_module_inst: work@t (work@t), file:${SURELOG_DIR}/tests/EvalFuncCont/dut.sv, line:8:1, endln:35:10 |vpiRhs: \_constant: , line:15:27, endln:15:29 |vpiDecompile:11 @@ -1199,7 +1199,7 @@ design: (work@t) |vpiParamAssign: \_param_assign: , line:16:15, endln:16:39 |vpiParent: - \_module: work@t (work@t), file:${SURELOG_DIR}/tests/EvalFuncCont/dut.sv, line:8:1, endln:35:10 + \_module_inst: work@t (work@t), file:${SURELOG_DIR}/tests/EvalFuncCont/dut.sv, line:8:1, endln:35:10 |vpiRhs: \_func_call: (num_out), line:16:25, endln:16:32 |vpiArgument: @@ -1216,7 +1216,7 @@ design: (work@t) |vpiTaskFunc: \_function: (work@t.num_out), line:20:4, endln:27:15 |vpiParent: - \_module: work@t (work@t), file:${SURELOG_DIR}/tests/EvalFuncCont/dut.sv, line:8:1, endln:35:10 + \_module_inst: work@t (work@t), file:${SURELOG_DIR}/tests/EvalFuncCont/dut.sv, line:8:1, endln:35:10 |vpiName:num_out |vpiFullName:work@t.num_out |vpiVisibility:1 @@ -1227,7 +1227,7 @@ design: (work@t) |vpiSigned:1 |vpiSigned:1 |vpiParent: - \_module: work@t (work@t), file:${SURELOG_DIR}/tests/EvalFuncCont/dut.sv, line:8:1, endln:35:10 + \_module_inst: work@t (work@t), file:${SURELOG_DIR}/tests/EvalFuncCont/dut.sv, line:8:1, endln:35:10 |vpiIODecl: \_io_decl: (width), line:21:21, endln:21:26 |vpiParent: @@ -1371,24 +1371,24 @@ design: (work@t) |vpiParent: \_begin: (work@t.num_out), line:23:59, endln:26:10 |vpiInstance: - \_module: work@t (work@t), file:${SURELOG_DIR}/tests/EvalFuncCont/dut.sv, line:8:1, endln:35:10 + \_module_inst: work@t (work@t), file:${SURELOG_DIR}/tests/EvalFuncCont/dut.sv, line:8:1, endln:35:10 |vpiNet: \_logic_net: (work@t.z), line:18:23, endln:18:24 |vpiParent: - \_module: work@t (work@t), file:${SURELOG_DIR}/tests/EvalFuncCont/dut.sv, line:8:1, endln:35:10 + \_module_inst: work@t (work@t), file:${SURELOG_DIR}/tests/EvalFuncCont/dut.sv, line:8:1, endln:35:10 |vpiName:z |vpiFullName:work@t.z |vpiNetType:1 |vpiNet: \_logic_net: (work@t.clk), line:10:4, endln:10:7 |vpiParent: - \_module: work@t (work@t), file:${SURELOG_DIR}/tests/EvalFuncCont/dut.sv, line:8:1, endln:35:10 + \_module_inst: work@t (work@t), file:${SURELOG_DIR}/tests/EvalFuncCont/dut.sv, line:8:1, endln:35:10 |vpiName:clk |vpiFullName:work@t.clk |vpiPort: \_port: (clk), line:10:4, endln:10:7 |vpiParent: - \_module: work@t (work@t), file:${SURELOG_DIR}/tests/EvalFuncCont/dut.sv, line:8:1, endln:35:10 + \_module_inst: work@t (work@t), file:${SURELOG_DIR}/tests/EvalFuncCont/dut.sv, line:8:1, endln:35:10 |vpiName:clk |vpiDirection:1 |vpiLowConn: @@ -1400,7 +1400,7 @@ design: (work@t) |vpiProcess: \_initial: , line:29:4, endln:34:7 |vpiParent: - \_module: work@t (work@t), file:${SURELOG_DIR}/tests/EvalFuncCont/dut.sv, line:8:1, endln:35:10 + \_module_inst: work@t (work@t), file:${SURELOG_DIR}/tests/EvalFuncCont/dut.sv, line:8:1, endln:35:10 |vpiStmt: \_begin: (work@t), line:29:12, endln:34:7 |vpiParent: @@ -1488,12 +1488,12 @@ design: (work@t) \_begin: (work@t), line:29:12, endln:34:7 |vpiName:$finish |uhdmtopModules: -\_module: work@t (work@t), file:${SURELOG_DIR}/tests/EvalFuncCont/dut.sv, line:8:1, endln:35:10 +\_module_inst: work@t (work@t), file:${SURELOG_DIR}/tests/EvalFuncCont/dut.sv, line:8:1, endln:35:10 |vpiName:work@t |vpiParameter: \_parameter: (work@t.WIDTH), line:14:15, endln:14:20 |vpiParent: - \_module: work@t (work@t), file:${SURELOG_DIR}/tests/EvalFuncCont/dut.sv, line:8:1, endln:35:10 + \_module_inst: work@t (work@t), file:${SURELOG_DIR}/tests/EvalFuncCont/dut.sv, line:8:1, endln:35:10 |UINT:33 |vpiTypespec: \_int_typespec: @@ -1504,7 +1504,7 @@ design: (work@t) |vpiParameter: \_parameter: (work@t.MAX_WIDTH), line:15:15, endln:15:24 |vpiParent: - \_module: work@t (work@t), file:${SURELOG_DIR}/tests/EvalFuncCont/dut.sv, line:8:1, endln:35:10 + \_module_inst: work@t (work@t), file:${SURELOG_DIR}/tests/EvalFuncCont/dut.sv, line:8:1, endln:35:10 |UINT:11 |vpiTypespec: \_int_typespec: @@ -1516,14 +1516,14 @@ design: (work@t) |vpiParameter: \_parameter: (work@t.NUM_OUT), line:16:15, endln:16:22 |vpiParent: - \_module: work@t (work@t), file:${SURELOG_DIR}/tests/EvalFuncCont/dut.sv, line:8:1, endln:35:10 + \_module_inst: work@t (work@t), file:${SURELOG_DIR}/tests/EvalFuncCont/dut.sv, line:8:1, endln:35:10 |vpiLocalParam:1 |vpiName:NUM_OUT |vpiFullName:work@t.NUM_OUT |vpiParamAssign: \_param_assign: , line:14:15, endln:14:25 |vpiParent: - \_module: work@t (work@t), file:${SURELOG_DIR}/tests/EvalFuncCont/dut.sv, line:8:1, endln:35:10 + \_module_inst: work@t (work@t), file:${SURELOG_DIR}/tests/EvalFuncCont/dut.sv, line:8:1, endln:35:10 |vpiRhs: \_constant: , line:14:23, endln:14:25 |vpiDecompile:33 @@ -1537,7 +1537,7 @@ design: (work@t) |vpiParamAssign: \_param_assign: , line:15:15, endln:15:29 |vpiParent: - \_module: work@t (work@t), file:${SURELOG_DIR}/tests/EvalFuncCont/dut.sv, line:8:1, endln:35:10 + \_module_inst: work@t (work@t), file:${SURELOG_DIR}/tests/EvalFuncCont/dut.sv, line:8:1, endln:35:10 |vpiRhs: \_constant: , line:15:27, endln:15:29 |vpiDecompile:11 @@ -1551,7 +1551,7 @@ design: (work@t) |vpiParamAssign: \_param_assign: , line:16:15, endln:16:39 |vpiParent: - \_module: work@t (work@t), file:${SURELOG_DIR}/tests/EvalFuncCont/dut.sv, line:8:1, endln:35:10 + \_module_inst: work@t (work@t), file:${SURELOG_DIR}/tests/EvalFuncCont/dut.sv, line:8:1, endln:35:10 |vpiRhs: \_constant: , line:16:25, endln:16:39 |vpiDecompile:4 @@ -1565,14 +1565,14 @@ design: (work@t) |vpiTaskFunc: \_function: (work@t.num_out), line:20:4, endln:27:15 |vpiParent: - \_module: work@t (work@t), file:${SURELOG_DIR}/tests/EvalFuncCont/dut.sv, line:8:1, endln:35:10 + \_module_inst: work@t (work@t), file:${SURELOG_DIR}/tests/EvalFuncCont/dut.sv, line:8:1, endln:35:10 |vpiName:num_out |vpiFullName:work@t.num_out |vpiVisibility:1 |vpiReturn: \_integer_var: , line:20:13, endln:20:20 |vpiParent: - \_module: work@t (work@t), file:${SURELOG_DIR}/tests/EvalFuncCont/dut.sv, line:8:1, endln:35:10 + \_module_inst: work@t (work@t), file:${SURELOG_DIR}/tests/EvalFuncCont/dut.sv, line:8:1, endln:35:10 |vpiIODecl: \_io_decl: (width), line:21:21, endln:21:26 |vpiParent: @@ -1699,11 +1699,11 @@ design: (work@t) |vpiParent: \_begin: (work@t.num_out), line:23:59, endln:26:10 |vpiInstance: - \_module: work@t (work@t), file:${SURELOG_DIR}/tests/EvalFuncCont/dut.sv, line:8:1, endln:35:10 + \_module_inst: work@t (work@t), file:${SURELOG_DIR}/tests/EvalFuncCont/dut.sv, line:8:1, endln:35:10 |vpiNet: \_logic_net: (work@t.z), line:18:23, endln:18:24 |vpiParent: - \_module: work@t (work@t), file:${SURELOG_DIR}/tests/EvalFuncCont/dut.sv, line:8:1, endln:35:10 + \_module_inst: work@t (work@t), file:${SURELOG_DIR}/tests/EvalFuncCont/dut.sv, line:8:1, endln:35:10 |vpiTypespec: \_logic_typespec: , line:18:4, endln:18:22 |vpiRange: @@ -1730,7 +1730,7 @@ design: (work@t) |vpiNet: \_logic_net: (work@t.clk), line:10:4, endln:10:7 |vpiParent: - \_module: work@t (work@t), file:${SURELOG_DIR}/tests/EvalFuncCont/dut.sv, line:8:1, endln:35:10 + \_module_inst: work@t (work@t), file:${SURELOG_DIR}/tests/EvalFuncCont/dut.sv, line:8:1, endln:35:10 |vpiTypespec: \_logic_typespec: , line:12:10, endln:12:10 |vpiName:clk @@ -1739,7 +1739,7 @@ design: (work@t) |vpiPort: \_port: (clk), line:10:4, endln:10:7 |vpiParent: - \_module: work@t (work@t), file:${SURELOG_DIR}/tests/EvalFuncCont/dut.sv, line:8:1, endln:35:10 + \_module_inst: work@t (work@t), file:${SURELOG_DIR}/tests/EvalFuncCont/dut.sv, line:8:1, endln:35:10 |vpiName:clk |vpiDirection:1 |vpiLowConn: @@ -1753,11 +1753,11 @@ design: (work@t) |vpiTypedef: \_logic_typespec: , line:12:10, endln:12:10 |vpiInstance: - \_module: work@t (work@t), file:${SURELOG_DIR}/tests/EvalFuncCont/dut.sv, line:8:1, endln:35:10 + \_module_inst: work@t (work@t), file:${SURELOG_DIR}/tests/EvalFuncCont/dut.sv, line:8:1, endln:35:10 |vpiProcess: \_initial: , line:29:4, endln:34:7 |vpiParent: - \_module: work@t (work@t), file:${SURELOG_DIR}/tests/EvalFuncCont/dut.sv, line:8:1, endln:35:10 + \_module_inst: work@t (work@t), file:${SURELOG_DIR}/tests/EvalFuncCont/dut.sv, line:8:1, endln:35:10 |vpiStmt: \_begin: (work@t), line:29:12, endln:34:7 |vpiParent: diff --git a/tests/EvalFuncNamed/EvalFuncNamed.log b/tests/EvalFuncNamed/EvalFuncNamed.log index 462b030002..f58c9c1505 100644 --- a/tests/EvalFuncNamed/EvalFuncNamed.log +++ b/tests/EvalFuncNamed/EvalFuncNamed.log @@ -531,7 +531,7 @@ io_decl 27 logic_net 6 logic_typespec 9 logic_var 1 -module 9 +module_inst 9 operation 12 package 8 param_assign 28 @@ -563,7 +563,7 @@ io_decl 58 logic_net 6 logic_typespec 9 logic_var 1 -module 9 +module_inst 9 operation 17 package 8 param_assign 28 @@ -1857,14 +1857,14 @@ design: (work@t) \_int_typespec: |vpiSigned:1 |uhdmallModules: -\_module: work@t (work@t), file:${SURELOG_DIR}/tests/EvalFuncNamed/dut.sv, line:23:1, endln:31:10 +\_module_inst: work@t (work@t), file:${SURELOG_DIR}/tests/EvalFuncNamed/dut.sv, line:23:1, endln:31:10 |vpiParent: \_design: (work@t) |vpiFullName:work@t |vpiParameter: \_parameter: (work@t.MY_PARAM), line:19:15, endln:19:23 |vpiParent: - \_module: work@t (work@t), file:${SURELOG_DIR}/tests/EvalFuncNamed/dut.sv, line:23:1, endln:31:10 + \_module_inst: work@t (work@t), file:${SURELOG_DIR}/tests/EvalFuncNamed/dut.sv, line:23:1, endln:31:10 |UINT:3 |vpiTypespec: \_int_typespec: @@ -1877,7 +1877,7 @@ design: (work@t) |vpiParameter: \_parameter: (work@t.MY_PARAM2), line:20:15, endln:20:24 |vpiParent: - \_module: work@t (work@t), file:${SURELOG_DIR}/tests/EvalFuncNamed/dut.sv, line:23:1, endln:31:10 + \_module_inst: work@t (work@t), file:${SURELOG_DIR}/tests/EvalFuncNamed/dut.sv, line:23:1, endln:31:10 |INT:12 |vpiTypespec: \_int_typespec: @@ -1890,7 +1890,7 @@ design: (work@t) |vpiParamAssign: \_param_assign: , line:19:15, endln:19:27 |vpiParent: - \_module: work@t (work@t), file:${SURELOG_DIR}/tests/EvalFuncNamed/dut.sv, line:23:1, endln:31:10 + \_module_inst: work@t (work@t), file:${SURELOG_DIR}/tests/EvalFuncNamed/dut.sv, line:23:1, endln:31:10 |vpiRhs: \_constant: , line:19:26, endln:19:27 |vpiParent: @@ -1919,7 +1919,7 @@ design: (work@t) |vpiParamAssign: \_param_assign: , line:20:15, endln:20:64 |vpiParent: - \_module: work@t (work@t), file:${SURELOG_DIR}/tests/EvalFuncNamed/dut.sv, line:23:1, endln:31:10 + \_module_inst: work@t (work@t), file:${SURELOG_DIR}/tests/EvalFuncNamed/dut.sv, line:23:1, endln:31:10 |vpiRhs: \_constant: , line:20:27, endln:20:64 |vpiParent: @@ -2093,26 +2093,26 @@ design: (work@t) |vpiNet: \_logic_net: (work@t.i_clk), line:26:14, endln:26:19 |vpiParent: - \_module: work@t (work@t), file:${SURELOG_DIR}/tests/EvalFuncNamed/dut.sv, line:23:1, endln:31:10 + \_module_inst: work@t (work@t), file:${SURELOG_DIR}/tests/EvalFuncNamed/dut.sv, line:23:1, endln:31:10 |vpiName:i_clk |vpiFullName:work@t.i_clk |vpiNet: \_logic_net: (work@t.i_d), line:27:27, endln:27:30 |vpiParent: - \_module: work@t (work@t), file:${SURELOG_DIR}/tests/EvalFuncNamed/dut.sv, line:23:1, endln:31:10 + \_module_inst: work@t (work@t), file:${SURELOG_DIR}/tests/EvalFuncNamed/dut.sv, line:23:1, endln:31:10 |vpiName:i_d |vpiFullName:work@t.i_d |vpiNet: \_logic_net: (work@t.o_q), line:28:33, endln:28:36 |vpiParent: - \_module: work@t (work@t), file:${SURELOG_DIR}/tests/EvalFuncNamed/dut.sv, line:23:1, endln:31:10 + \_module_inst: work@t (work@t), file:${SURELOG_DIR}/tests/EvalFuncNamed/dut.sv, line:23:1, endln:31:10 |vpiName:o_q |vpiFullName:work@t.o_q |vpiNetType:36 |vpiPort: \_port: (i_clk), line:26:14, endln:26:19 |vpiParent: - \_module: work@t (work@t), file:${SURELOG_DIR}/tests/EvalFuncNamed/dut.sv, line:23:1, endln:31:10 + \_module_inst: work@t (work@t), file:${SURELOG_DIR}/tests/EvalFuncNamed/dut.sv, line:23:1, endln:31:10 |vpiName:i_clk |vpiDirection:1 |vpiLowConn: @@ -2124,7 +2124,7 @@ design: (work@t) |vpiPort: \_port: (i_d), line:27:27, endln:27:30 |vpiParent: - \_module: work@t (work@t), file:${SURELOG_DIR}/tests/EvalFuncNamed/dut.sv, line:23:1, endln:31:10 + \_module_inst: work@t (work@t), file:${SURELOG_DIR}/tests/EvalFuncNamed/dut.sv, line:23:1, endln:31:10 |vpiName:i_d |vpiDirection:1 |vpiLowConn: @@ -2171,7 +2171,7 @@ design: (work@t) |vpiPort: \_port: (o_q), line:28:33, endln:28:36 |vpiParent: - \_module: work@t (work@t), file:${SURELOG_DIR}/tests/EvalFuncNamed/dut.sv, line:23:1, endln:31:10 + \_module_inst: work@t (work@t), file:${SURELOG_DIR}/tests/EvalFuncNamed/dut.sv, line:23:1, endln:31:10 |vpiName:o_q |vpiDirection:2 |vpiLowConn: @@ -2216,12 +2216,12 @@ design: (work@t) |UINT:0 |vpiConstType:9 |uhdmtopModules: -\_module: work@t (work@t), file:${SURELOG_DIR}/tests/EvalFuncNamed/dut.sv, line:23:1, endln:31:10 +\_module_inst: work@t (work@t), file:${SURELOG_DIR}/tests/EvalFuncNamed/dut.sv, line:23:1, endln:31:10 |vpiName:work@t |vpiParameter: \_parameter: (work@t.MY_PARAM), line:19:15, endln:19:23 |vpiParent: - \_module: work@t (work@t), file:${SURELOG_DIR}/tests/EvalFuncNamed/dut.sv, line:23:1, endln:31:10 + \_module_inst: work@t (work@t), file:${SURELOG_DIR}/tests/EvalFuncNamed/dut.sv, line:23:1, endln:31:10 |UINT:3 |vpiTypespec: \_int_typespec: @@ -2234,7 +2234,7 @@ design: (work@t) |vpiParameter: \_parameter: (work@t.MY_PARAM2), line:20:15, endln:20:24 |vpiParent: - \_module: work@t (work@t), file:${SURELOG_DIR}/tests/EvalFuncNamed/dut.sv, line:23:1, endln:31:10 + \_module_inst: work@t (work@t), file:${SURELOG_DIR}/tests/EvalFuncNamed/dut.sv, line:23:1, endln:31:10 |INT:12 |vpiTypespec: \_int_typespec: @@ -2247,7 +2247,7 @@ design: (work@t) |vpiParamAssign: \_param_assign: , line:19:15, endln:19:27 |vpiParent: - \_module: work@t (work@t), file:${SURELOG_DIR}/tests/EvalFuncNamed/dut.sv, line:23:1, endln:31:10 + \_module_inst: work@t (work@t), file:${SURELOG_DIR}/tests/EvalFuncNamed/dut.sv, line:23:1, endln:31:10 |vpiRhs: \_constant: , line:19:26, endln:19:27 |vpiDecompile:3 @@ -2261,7 +2261,7 @@ design: (work@t) |vpiParamAssign: \_param_assign: , line:20:15, endln:20:64 |vpiParent: - \_module: work@t (work@t), file:${SURELOG_DIR}/tests/EvalFuncNamed/dut.sv, line:23:1, endln:31:10 + \_module_inst: work@t (work@t), file:${SURELOG_DIR}/tests/EvalFuncNamed/dut.sv, line:23:1, endln:31:10 |vpiRhs: \_constant: , line:20:27, endln:20:64 |vpiDecompile:12 @@ -2279,7 +2279,7 @@ design: (work@t) |vpiTaskFunc: \_function: (my_module_types::simple_minus), line:3:4, endln:7:15 |vpiParent: - \_module: work@t (work@t), file:${SURELOG_DIR}/tests/EvalFuncNamed/dut.sv, line:23:1, endln:31:10 + \_module_inst: work@t (work@t), file:${SURELOG_DIR}/tests/EvalFuncNamed/dut.sv, line:23:1, endln:31:10 |vpiName:simple_minus |vpiFullName:my_module_types::simple_minus |vpiVisibility:1 @@ -2287,7 +2287,7 @@ design: (work@t) |vpiReturn: \_int_var: , line:3:23, endln:3:26 |vpiParent: - \_module: work@t (work@t), file:${SURELOG_DIR}/tests/EvalFuncNamed/dut.sv, line:23:1, endln:31:10 + \_module_inst: work@t (work@t), file:${SURELOG_DIR}/tests/EvalFuncNamed/dut.sv, line:23:1, endln:31:10 |vpiIODecl: \_io_decl: (value1), line:3:51, endln:3:57 |vpiParent: @@ -2345,11 +2345,11 @@ design: (work@t) |vpiActual: \_int_var: , line:3:23, endln:3:26 |vpiInstance: - \_module: work@t (work@t), file:${SURELOG_DIR}/tests/EvalFuncNamed/dut.sv, line:23:1, endln:31:10 + \_module_inst: work@t (work@t), file:${SURELOG_DIR}/tests/EvalFuncNamed/dut.sv, line:23:1, endln:31:10 |vpiTaskFunc: \_function: (my_module_types::simple_func), line:9:4, endln:13:15 |vpiParent: - \_module: work@t (work@t), file:${SURELOG_DIR}/tests/EvalFuncNamed/dut.sv, line:23:1, endln:31:10 + \_module_inst: work@t (work@t), file:${SURELOG_DIR}/tests/EvalFuncNamed/dut.sv, line:23:1, endln:31:10 |vpiName:simple_func |vpiFullName:my_module_types::simple_func |vpiVisibility:1 @@ -2357,7 +2357,7 @@ design: (work@t) |vpiReturn: \_int_var: , line:9:23, endln:9:26 |vpiParent: - \_module: work@t (work@t), file:${SURELOG_DIR}/tests/EvalFuncNamed/dut.sv, line:23:1, endln:31:10 + \_module_inst: work@t (work@t), file:${SURELOG_DIR}/tests/EvalFuncNamed/dut.sv, line:23:1, endln:31:10 |vpiIODecl: \_io_decl: (value1), line:9:50, endln:9:56 |vpiParent: @@ -2417,11 +2417,11 @@ design: (work@t) |vpiActual: \_int_var: , line:9:23, endln:9:26 |vpiInstance: - \_module: work@t (work@t), file:${SURELOG_DIR}/tests/EvalFuncNamed/dut.sv, line:23:1, endln:31:10 + \_module_inst: work@t (work@t), file:${SURELOG_DIR}/tests/EvalFuncNamed/dut.sv, line:23:1, endln:31:10 |vpiNet: \_logic_net: (work@t.i_clk), line:26:14, endln:26:19 |vpiParent: - \_module: work@t (work@t), file:${SURELOG_DIR}/tests/EvalFuncNamed/dut.sv, line:23:1, endln:31:10 + \_module_inst: work@t (work@t), file:${SURELOG_DIR}/tests/EvalFuncNamed/dut.sv, line:23:1, endln:31:10 |vpiTypespec: \_logic_typespec: , line:26:14, endln:26:14 |vpiName:i_clk @@ -2429,7 +2429,7 @@ design: (work@t) |vpiNet: \_logic_net: (work@t.i_d), line:27:27, endln:27:30 |vpiParent: - \_module: work@t (work@t), file:${SURELOG_DIR}/tests/EvalFuncNamed/dut.sv, line:23:1, endln:31:10 + \_module_inst: work@t (work@t), file:${SURELOG_DIR}/tests/EvalFuncNamed/dut.sv, line:23:1, endln:31:10 |vpiTypespec: \_logic_typespec: , line:27:11, endln:27:25 |vpiRange: @@ -2455,7 +2455,7 @@ design: (work@t) |vpiNet: \_logic_net: (work@t.o_q), line:28:33, endln:28:36 |vpiParent: - \_module: work@t (work@t), file:${SURELOG_DIR}/tests/EvalFuncNamed/dut.sv, line:23:1, endln:31:10 + \_module_inst: work@t (work@t), file:${SURELOG_DIR}/tests/EvalFuncNamed/dut.sv, line:23:1, endln:31:10 |vpiTypespec: \_logic_typespec: , line:28:12, endln:28:32 |vpiRange: @@ -2483,7 +2483,7 @@ design: (work@t) |vpiPort: \_port: (i_clk), line:26:14, endln:26:19 |vpiParent: - \_module: work@t (work@t), file:${SURELOG_DIR}/tests/EvalFuncNamed/dut.sv, line:23:1, endln:31:10 + \_module_inst: work@t (work@t), file:${SURELOG_DIR}/tests/EvalFuncNamed/dut.sv, line:23:1, endln:31:10 |vpiName:i_clk |vpiDirection:1 |vpiLowConn: @@ -2497,11 +2497,11 @@ design: (work@t) |vpiTypedef: \_logic_typespec: , line:26:14, endln:26:14 |vpiInstance: - \_module: work@t (work@t), file:${SURELOG_DIR}/tests/EvalFuncNamed/dut.sv, line:23:1, endln:31:10 + \_module_inst: work@t (work@t), file:${SURELOG_DIR}/tests/EvalFuncNamed/dut.sv, line:23:1, endln:31:10 |vpiPort: \_port: (i_d), line:27:27, endln:27:30 |vpiParent: - \_module: work@t (work@t), file:${SURELOG_DIR}/tests/EvalFuncNamed/dut.sv, line:23:1, endln:31:10 + \_module_inst: work@t (work@t), file:${SURELOG_DIR}/tests/EvalFuncNamed/dut.sv, line:23:1, endln:31:10 |vpiName:i_d |vpiDirection:1 |vpiLowConn: @@ -2535,11 +2535,11 @@ design: (work@t) |UINT:0 |vpiConstType:9 |vpiInstance: - \_module: work@t (work@t), file:${SURELOG_DIR}/tests/EvalFuncNamed/dut.sv, line:23:1, endln:31:10 + \_module_inst: work@t (work@t), file:${SURELOG_DIR}/tests/EvalFuncNamed/dut.sv, line:23:1, endln:31:10 |vpiPort: \_port: (o_q), line:28:33, endln:28:36 |vpiParent: - \_module: work@t (work@t), file:${SURELOG_DIR}/tests/EvalFuncNamed/dut.sv, line:23:1, endln:31:10 + \_module_inst: work@t (work@t), file:${SURELOG_DIR}/tests/EvalFuncNamed/dut.sv, line:23:1, endln:31:10 |vpiName:o_q |vpiDirection:2 |vpiLowConn: @@ -2573,7 +2573,7 @@ design: (work@t) |UINT:0 |vpiConstType:9 |vpiInstance: - \_module: work@t (work@t), file:${SURELOG_DIR}/tests/EvalFuncNamed/dut.sv, line:23:1, endln:31:10 + \_module_inst: work@t (work@t), file:${SURELOG_DIR}/tests/EvalFuncNamed/dut.sv, line:23:1, endln:31:10 =================== [ FATAL] : 0 [ SYNTAX] : 0 diff --git a/tests/EvalFuncPack/EvalFuncPack.log b/tests/EvalFuncPack/EvalFuncPack.log index 0ad6228455..05bc7e1044 100644 --- a/tests/EvalFuncPack/EvalFuncPack.log +++ b/tests/EvalFuncPack/EvalFuncPack.log @@ -781,7 +781,7 @@ io_decl 19 logic_net 1 logic_typespec 1 logic_var 2 -module 57 +module_inst 57 operation 34 package 11 param_assign 70 @@ -820,7 +820,7 @@ io_decl 39 logic_net 1 logic_typespec 1 logic_var 2 -module 57 +module_inst 57 operation 62 package 11 param_assign 70 @@ -2948,14 +2948,14 @@ design: (work@flash_ctrl_info_cfg) \_int_typespec: |vpiSigned:1 |uhdmallModules: -\_module: work@flash_ctrl_info_cfg (work@flash_ctrl_info_cfg), file:${SURELOG_DIR}/tests/EvalFuncPack/dut.sv, line:59:1, endln:63:10 +\_module_inst: work@flash_ctrl_info_cfg (work@flash_ctrl_info_cfg), file:${SURELOG_DIR}/tests/EvalFuncPack/dut.sv, line:59:1, endln:63:10 |vpiParent: \_design: (work@flash_ctrl_info_cfg) |vpiFullName:work@flash_ctrl_info_cfg |vpiParameter: \_parameter: (work@flash_ctrl_info_cfg.InfoPageW), line:33:16, endln:33:25 |vpiParent: - \_module: work@flash_ctrl_info_cfg (work@flash_ctrl_info_cfg), file:${SURELOG_DIR}/tests/EvalFuncPack/dut.sv, line:59:1, endln:63:10 + \_module_inst: work@flash_ctrl_info_cfg (work@flash_ctrl_info_cfg), file:${SURELOG_DIR}/tests/EvalFuncPack/dut.sv, line:59:1, endln:63:10 |vpiTypespec: \_int_typespec: , line:33:12, endln:33:15 |vpiParent: @@ -2970,7 +2970,7 @@ design: (work@flash_ctrl_info_cfg) |vpiParameter: \_parameter: (work@flash_ctrl_info_cfg.InfoTypes), line:26:15, endln:26:24 |vpiParent: - \_module: work@flash_ctrl_info_cfg (work@flash_ctrl_info_cfg), file:${SURELOG_DIR}/tests/EvalFuncPack/dut.sv, line:59:1, endln:63:10 + \_module_inst: work@flash_ctrl_info_cfg (work@flash_ctrl_info_cfg), file:${SURELOG_DIR}/tests/EvalFuncPack/dut.sv, line:59:1, endln:63:10 |UINT:3 |vpiTypespec: \_int_typespec: , line:26:11, endln:26:14 @@ -2986,7 +2986,7 @@ design: (work@flash_ctrl_info_cfg) |vpiParameter: \_parameter: (work@flash_ctrl_info_cfg.InfosPerBank), line:27:15, endln:27:27 |vpiParent: - \_module: work@flash_ctrl_info_cfg (work@flash_ctrl_info_cfg), file:${SURELOG_DIR}/tests/EvalFuncPack/dut.sv, line:59:1, endln:63:10 + \_module_inst: work@flash_ctrl_info_cfg (work@flash_ctrl_info_cfg), file:${SURELOG_DIR}/tests/EvalFuncPack/dut.sv, line:59:1, endln:63:10 |vpiTypespec: \_int_typespec: , line:27:11, endln:27:14 |vpiParent: @@ -3001,7 +3001,7 @@ design: (work@flash_ctrl_info_cfg) |vpiParamAssign: \_param_assign: , line:26:15, endln:26:28 |vpiParent: - \_module: work@flash_ctrl_info_cfg (work@flash_ctrl_info_cfg), file:${SURELOG_DIR}/tests/EvalFuncPack/dut.sv, line:59:1, endln:63:10 + \_module_inst: work@flash_ctrl_info_cfg (work@flash_ctrl_info_cfg), file:${SURELOG_DIR}/tests/EvalFuncPack/dut.sv, line:59:1, endln:63:10 |vpiRhs: \_constant: , line:26:27, endln:26:28 |vpiParent: @@ -3036,7 +3036,7 @@ design: (work@flash_ctrl_info_cfg) |vpiParamAssign: \_param_assign: , line:27:15, endln:31:5 |vpiParent: - \_module: work@flash_ctrl_info_cfg (work@flash_ctrl_info_cfg), file:${SURELOG_DIR}/tests/EvalFuncPack/dut.sv, line:59:1, endln:63:10 + \_module_inst: work@flash_ctrl_info_cfg (work@flash_ctrl_info_cfg), file:${SURELOG_DIR}/tests/EvalFuncPack/dut.sv, line:59:1, endln:63:10 |vpiRhs: \_constant: , line:28:5, endln:28:7 |vpiParent: @@ -3063,7 +3063,7 @@ design: (work@flash_ctrl_info_cfg) |vpiParamAssign: \_param_assign: , line:33:16, endln:33:68 |vpiParent: - \_module: work@flash_ctrl_info_cfg (work@flash_ctrl_info_cfg), file:${SURELOG_DIR}/tests/EvalFuncPack/dut.sv, line:59:1, endln:63:10 + \_module_inst: work@flash_ctrl_info_cfg (work@flash_ctrl_info_cfg), file:${SURELOG_DIR}/tests/EvalFuncPack/dut.sv, line:59:1, endln:63:10 |vpiRhs: \_constant: |vpiParent: @@ -3296,17 +3296,17 @@ design: (work@flash_ctrl_info_cfg) |vpiNet: \_logic_net: (work@flash_ctrl_info_cfg.CurPage), line:61:23, endln:61:30 |vpiParent: - \_module: work@flash_ctrl_info_cfg (work@flash_ctrl_info_cfg), file:${SURELOG_DIR}/tests/EvalFuncPack/dut.sv, line:59:1, endln:63:10 + \_module_inst: work@flash_ctrl_info_cfg (work@flash_ctrl_info_cfg), file:${SURELOG_DIR}/tests/EvalFuncPack/dut.sv, line:59:1, endln:63:10 |vpiName:CurPage |vpiFullName:work@flash_ctrl_info_cfg.CurPage |vpiNetType:36 |uhdmtopModules: -\_module: work@flash_ctrl_info_cfg (work@flash_ctrl_info_cfg), file:${SURELOG_DIR}/tests/EvalFuncPack/dut.sv, line:59:1, endln:63:10 +\_module_inst: work@flash_ctrl_info_cfg (work@flash_ctrl_info_cfg), file:${SURELOG_DIR}/tests/EvalFuncPack/dut.sv, line:59:1, endln:63:10 |vpiName:work@flash_ctrl_info_cfg |vpiVariables: \_logic_var: (work@flash_ctrl_info_cfg.CurPage), line:61:23, endln:61:30 |vpiParent: - \_module: work@flash_ctrl_info_cfg (work@flash_ctrl_info_cfg), file:${SURELOG_DIR}/tests/EvalFuncPack/dut.sv, line:59:1, endln:63:10 + \_module_inst: work@flash_ctrl_info_cfg (work@flash_ctrl_info_cfg), file:${SURELOG_DIR}/tests/EvalFuncPack/dut.sv, line:59:1, endln:63:10 |vpiTypespec: \_logic_typespec: , line:61:1, endln:61:22 |vpiRange: @@ -3351,7 +3351,7 @@ design: (work@flash_ctrl_info_cfg) |vpiParameter: \_parameter: (work@flash_ctrl_info_cfg.InfoPageW), line:33:16, endln:33:25 |vpiParent: - \_module: work@flash_ctrl_info_cfg (work@flash_ctrl_info_cfg), file:${SURELOG_DIR}/tests/EvalFuncPack/dut.sv, line:59:1, endln:63:10 + \_module_inst: work@flash_ctrl_info_cfg (work@flash_ctrl_info_cfg), file:${SURELOG_DIR}/tests/EvalFuncPack/dut.sv, line:59:1, endln:63:10 |vpiTypespec: \_int_typespec: , line:33:12, endln:33:15 |vpiParent: @@ -3366,7 +3366,7 @@ design: (work@flash_ctrl_info_cfg) |vpiParameter: \_parameter: (work@flash_ctrl_info_cfg.InfoTypes), line:26:15, endln:26:24 |vpiParent: - \_module: work@flash_ctrl_info_cfg (work@flash_ctrl_info_cfg), file:${SURELOG_DIR}/tests/EvalFuncPack/dut.sv, line:59:1, endln:63:10 + \_module_inst: work@flash_ctrl_info_cfg (work@flash_ctrl_info_cfg), file:${SURELOG_DIR}/tests/EvalFuncPack/dut.sv, line:59:1, endln:63:10 |UINT:3 |vpiTypespec: \_int_typespec: , line:26:11, endln:26:14 @@ -3382,7 +3382,7 @@ design: (work@flash_ctrl_info_cfg) |vpiParameter: \_parameter: (work@flash_ctrl_info_cfg.InfosPerBank), line:27:15, endln:27:27 |vpiParent: - \_module: work@flash_ctrl_info_cfg (work@flash_ctrl_info_cfg), file:${SURELOG_DIR}/tests/EvalFuncPack/dut.sv, line:59:1, endln:63:10 + \_module_inst: work@flash_ctrl_info_cfg (work@flash_ctrl_info_cfg), file:${SURELOG_DIR}/tests/EvalFuncPack/dut.sv, line:59:1, endln:63:10 |vpiTypespec: \_int_typespec: , line:27:11, endln:27:14 |vpiParent: @@ -3397,7 +3397,7 @@ design: (work@flash_ctrl_info_cfg) |vpiParamAssign: \_param_assign: , line:26:15, endln:26:28 |vpiParent: - \_module: work@flash_ctrl_info_cfg (work@flash_ctrl_info_cfg), file:${SURELOG_DIR}/tests/EvalFuncPack/dut.sv, line:59:1, endln:63:10 + \_module_inst: work@flash_ctrl_info_cfg (work@flash_ctrl_info_cfg), file:${SURELOG_DIR}/tests/EvalFuncPack/dut.sv, line:59:1, endln:63:10 |vpiRhs: \_constant: , line:26:27, endln:26:28 |vpiDecompile:3 @@ -3411,7 +3411,7 @@ design: (work@flash_ctrl_info_cfg) |vpiParamAssign: \_param_assign: , line:27:15, endln:31:5 |vpiParent: - \_module: work@flash_ctrl_info_cfg (work@flash_ctrl_info_cfg), file:${SURELOG_DIR}/tests/EvalFuncPack/dut.sv, line:59:1, endln:63:10 + \_module_inst: work@flash_ctrl_info_cfg (work@flash_ctrl_info_cfg), file:${SURELOG_DIR}/tests/EvalFuncPack/dut.sv, line:59:1, endln:63:10 |vpiRhs: \_constant: , line:27:33, endln:31:5 |vpiDecompile:10 @@ -3425,7 +3425,7 @@ design: (work@flash_ctrl_info_cfg) |vpiParamAssign: \_param_assign: , line:33:16, endln:33:68 |vpiParent: - \_module: work@flash_ctrl_info_cfg (work@flash_ctrl_info_cfg), file:${SURELOG_DIR}/tests/EvalFuncPack/dut.sv, line:59:1, endln:63:10 + \_module_inst: work@flash_ctrl_info_cfg (work@flash_ctrl_info_cfg), file:${SURELOG_DIR}/tests/EvalFuncPack/dut.sv, line:59:1, endln:63:10 |vpiRhs: \_constant: , line:33:34, endln:33:68 |vpiDecompile:4 @@ -3443,7 +3443,7 @@ design: (work@flash_ctrl_info_cfg) |vpiTaskFunc: \_function: (flash_ctrl_pkg::max_info_pages), line:35:1, endln:43:14 |vpiParent: - \_module: work@flash_ctrl_info_cfg (work@flash_ctrl_info_cfg), file:${SURELOG_DIR}/tests/EvalFuncPack/dut.sv, line:59:1, endln:63:10 + \_module_inst: work@flash_ctrl_info_cfg (work@flash_ctrl_info_cfg), file:${SURELOG_DIR}/tests/EvalFuncPack/dut.sv, line:59:1, endln:63:10 |vpiName:max_info_pages |vpiFullName:flash_ctrl_pkg::max_info_pages |vpiVariables: @@ -3460,7 +3460,7 @@ design: (work@flash_ctrl_info_cfg) |vpiReturn: \_integer_var: , line:35:20, endln:35:27 |vpiParent: - \_module: work@flash_ctrl_info_cfg (work@flash_ctrl_info_cfg), file:${SURELOG_DIR}/tests/EvalFuncPack/dut.sv, line:59:1, endln:63:10 + \_module_inst: work@flash_ctrl_info_cfg (work@flash_ctrl_info_cfg), file:${SURELOG_DIR}/tests/EvalFuncPack/dut.sv, line:59:1, endln:63:10 |vpiIODecl: \_io_decl: (infos), line:35:47, endln:35:52 |vpiParent: @@ -3671,7 +3671,7 @@ design: (work@flash_ctrl_info_cfg) |vpiActual: \_int_var: (flash_ctrl_pkg::max_info_pages::current_max), line:36:9, endln:36:20 |vpiInstance: - \_module: work@flash_ctrl_info_cfg (work@flash_ctrl_info_cfg), file:${SURELOG_DIR}/tests/EvalFuncPack/dut.sv, line:59:1, endln:63:10 + \_module_inst: work@flash_ctrl_info_cfg (work@flash_ctrl_info_cfg), file:${SURELOG_DIR}/tests/EvalFuncPack/dut.sv, line:59:1, endln:63:10 |vpiTopModule:1 =================== [ FATAL] : 0 diff --git a/tests/Event/Event.log b/tests/Event/Event.log index 7d6e9e3971..dc958f5f64 100644 --- a/tests/Event/Event.log +++ b/tests/Event/Event.log @@ -47,7 +47,7 @@ n<> u<20> t c<1> l<1:1> el<5:1> design 1 event_typespec 1 logic_net 1 -module 2 +module_inst 2 named_event 1 === UHDM Object Stats End === [INF:UH0707] Elaborating UHDM... @@ -56,7 +56,7 @@ named_event 1 design 1 event_typespec 1 logic_net 1 -module 2 +module_inst 2 named_event 1 === UHDM Object Stats End === [INF:UH0708] Writing UHDM DB: ${SURELOG_DIR}/build/regression/Event/slpp_all/surelog.uhdm ... @@ -72,7 +72,7 @@ design: (work@t) |vpiElaborated:1 |vpiName:work@t |uhdmallModules: -\_module: work@t (work@t), file:${SURELOG_DIR}/tests/Event/dut.sv, line:1:1, endln:3:10 +\_module_inst: work@t (work@t), file:${SURELOG_DIR}/tests/Event/dut.sv, line:1:1, endln:3:10 |vpiParent: \_design: (work@t) |vpiFullName:work@t @@ -80,16 +80,16 @@ design: (work@t) |vpiNet: \_logic_net: (work@t.e), line:2:11, endln:2:12 |vpiParent: - \_module: work@t (work@t), file:${SURELOG_DIR}/tests/Event/dut.sv, line:1:1, endln:3:10 + \_module_inst: work@t (work@t), file:${SURELOG_DIR}/tests/Event/dut.sv, line:1:1, endln:3:10 |vpiName:e |vpiFullName:work@t.e |uhdmtopModules: -\_module: work@t (work@t), file:${SURELOG_DIR}/tests/Event/dut.sv, line:1:1, endln:3:10 +\_module_inst: work@t (work@t), file:${SURELOG_DIR}/tests/Event/dut.sv, line:1:1, endln:3:10 |vpiName:work@t |vpiNamedEvent: \_named_event: (work@t.e), line:2:11, endln:2:12 |vpiParent: - \_module: work@t (work@t), file:${SURELOG_DIR}/tests/Event/dut.sv, line:1:1, endln:3:10 + \_module_inst: work@t (work@t), file:${SURELOG_DIR}/tests/Event/dut.sv, line:1:1, endln:3:10 |vpiName:e |vpiFullName:work@t.e |vpiDefName:work@t diff --git a/tests/ExpectStmt/ExpectStmt.log b/tests/ExpectStmt/ExpectStmt.log index 0e91381065..fd86042f22 100644 --- a/tests/ExpectStmt/ExpectStmt.log +++ b/tests/ExpectStmt/ExpectStmt.log @@ -121,7 +121,7 @@ initial 1 logic_net 3 logic_typespec 3 logic_var 3 -module 2 +module_inst 2 operation 2 property_spec 1 ref_obj 3 @@ -137,7 +137,7 @@ initial 2 logic_net 3 logic_typespec 3 logic_var 3 -module 2 +module_inst 2 operation 4 property_spec 2 ref_obj 6 @@ -155,7 +155,7 @@ design: (work@top) |vpiElaborated:1 |vpiName:work@top |uhdmallModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/ExpectStmt/dut.sv, line:1:1, endln:11:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ExpectStmt/dut.sv, line:1:1, endln:11:10 |vpiParent: \_design: (work@top) |vpiFullName:work@top @@ -163,28 +163,28 @@ design: (work@top) |vpiNet: \_logic_net: (work@top.clk), line:3:7, endln:3:10 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ExpectStmt/dut.sv, line:1:1, endln:11:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ExpectStmt/dut.sv, line:1:1, endln:11:10 |vpiName:clk |vpiFullName:work@top.clk |vpiNetType:36 |vpiNet: \_logic_net: (work@top.a), line:4:7, endln:4:8 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ExpectStmt/dut.sv, line:1:1, endln:11:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ExpectStmt/dut.sv, line:1:1, endln:11:10 |vpiName:a |vpiFullName:work@top.a |vpiNetType:36 |vpiNet: \_logic_net: (work@top.b), line:5:7, endln:5:8 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ExpectStmt/dut.sv, line:1:1, endln:11:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ExpectStmt/dut.sv, line:1:1, endln:11:10 |vpiName:b |vpiFullName:work@top.b |vpiNetType:36 |vpiProcess: \_initial: , line:7:1, endln:9:4 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ExpectStmt/dut.sv, line:1:1, endln:11:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ExpectStmt/dut.sv, line:1:1, endln:11:10 |vpiStmt: \_begin: (work@top), line:7:9, endln:9:4 |vpiParent: @@ -229,12 +229,12 @@ design: (work@top) |vpiActual: \_logic_var: (work@top.b), line:5:7, endln:5:8 |uhdmtopModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/ExpectStmt/dut.sv, line:1:1, endln:11:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ExpectStmt/dut.sv, line:1:1, endln:11:10 |vpiName:work@top |vpiVariables: \_logic_var: (work@top.clk), line:3:7, endln:3:10 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ExpectStmt/dut.sv, line:1:1, endln:11:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ExpectStmt/dut.sv, line:1:1, endln:11:10 |vpiTypespec: \_logic_typespec: , line:3:1, endln:3:6 |vpiName:clk @@ -243,7 +243,7 @@ design: (work@top) |vpiVariables: \_logic_var: (work@top.a), line:4:7, endln:4:8 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ExpectStmt/dut.sv, line:1:1, endln:11:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ExpectStmt/dut.sv, line:1:1, endln:11:10 |vpiTypespec: \_logic_typespec: , line:4:1, endln:4:6 |vpiName:a @@ -252,7 +252,7 @@ design: (work@top) |vpiVariables: \_logic_var: (work@top.b), line:5:7, endln:5:8 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ExpectStmt/dut.sv, line:1:1, endln:11:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ExpectStmt/dut.sv, line:1:1, endln:11:10 |vpiTypespec: \_logic_typespec: , line:5:1, endln:5:6 |vpiName:b @@ -264,7 +264,7 @@ design: (work@top) |vpiProcess: \_initial: , line:7:1, endln:9:4 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ExpectStmt/dut.sv, line:1:1, endln:11:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ExpectStmt/dut.sv, line:1:1, endln:11:10 |vpiStmt: \_begin: (work@top), line:7:9, endln:9:4 |vpiParent: diff --git a/tests/ExponTimeIfElseGen/ExponTimeIfElseGen.log b/tests/ExponTimeIfElseGen/ExponTimeIfElseGen.log index db90448f45..1e0c005fb4 100644 --- a/tests/ExponTimeIfElseGen/ExponTimeIfElseGen.log +++ b/tests/ExponTimeIfElseGen/ExponTimeIfElseGen.log @@ -991,7 +991,7 @@ gen_scope 40 gen_scope_array 40 if_stmt 1 int_typespec 20 -module 5 +module_inst 5 operation 194 param_assign 2 parameter 20 @@ -1011,7 +1011,7 @@ gen_scope 60 gen_scope_array 60 if_stmt 2 int_typespec 20 -module 5 +module_inst 5 operation 196 param_assign 2 parameter 20 @@ -1030,14 +1030,14 @@ design: (work@Foo) |vpiElaborated:1 |vpiName:work@Foo |uhdmallModules: -\_module: work@Foo (work@Foo), file:${SURELOG_DIR}/tests/ExponTimeIfElseGen/dut.sv, line:1:1, endln:91:10 +\_module_inst: work@Foo (work@Foo), file:${SURELOG_DIR}/tests/ExponTimeIfElseGen/dut.sv, line:1:1, endln:91:10 |vpiParent: \_design: (work@Foo) |vpiFullName:work@Foo |vpiParameter: \_parameter: (work@Foo.ADDR_OFFSET_PART_1), line:2:14, endln:2:32 |vpiParent: - \_module: work@Foo (work@Foo), file:${SURELOG_DIR}/tests/ExponTimeIfElseGen/dut.sv, line:1:1, endln:91:10 + \_module_inst: work@Foo (work@Foo), file:${SURELOG_DIR}/tests/ExponTimeIfElseGen/dut.sv, line:1:1, endln:91:10 |UINT:1 |vpiTypespec: \_int_typespec: @@ -1046,7 +1046,7 @@ design: (work@Foo) |vpiParamAssign: \_param_assign: , line:2:14, endln:2:36 |vpiParent: - \_module: work@Foo (work@Foo), file:${SURELOG_DIR}/tests/ExponTimeIfElseGen/dut.sv, line:1:1, endln:91:10 + \_module_inst: work@Foo (work@Foo), file:${SURELOG_DIR}/tests/ExponTimeIfElseGen/dut.sv, line:1:1, endln:91:10 |vpiRhs: \_constant: , line:2:35, endln:2:36 |vpiDecompile:1 @@ -1059,12 +1059,12 @@ design: (work@Foo) \_parameter: (work@Foo.ADDR_OFFSET_PART_1), line:2:14, endln:2:32 |vpiDefName:work@Foo |uhdmtopModules: -\_module: work@Foo (work@Foo), file:${SURELOG_DIR}/tests/ExponTimeIfElseGen/dut.sv, line:1:1, endln:91:10 +\_module_inst: work@Foo (work@Foo), file:${SURELOG_DIR}/tests/ExponTimeIfElseGen/dut.sv, line:1:1, endln:91:10 |vpiName:work@Foo |vpiParameter: \_parameter: (work@Foo.ADDR_OFFSET_PART_1), line:2:14, endln:2:32 |vpiParent: - \_module: work@Foo (work@Foo), file:${SURELOG_DIR}/tests/ExponTimeIfElseGen/dut.sv, line:1:1, endln:91:10 + \_module_inst: work@Foo (work@Foo), file:${SURELOG_DIR}/tests/ExponTimeIfElseGen/dut.sv, line:1:1, endln:91:10 |UINT:1 |vpiTypespec: \_int_typespec: @@ -1075,7 +1075,7 @@ design: (work@Foo) |vpiParamAssign: \_param_assign: , line:2:14, endln:2:36 |vpiParent: - \_module: work@Foo (work@Foo), file:${SURELOG_DIR}/tests/ExponTimeIfElseGen/dut.sv, line:1:1, endln:91:10 + \_module_inst: work@Foo (work@Foo), file:${SURELOG_DIR}/tests/ExponTimeIfElseGen/dut.sv, line:1:1, endln:91:10 |vpiRhs: \_constant: , line:2:35, endln:2:36 |vpiDecompile:1 @@ -1092,7 +1092,7 @@ design: (work@Foo) |vpiGenScopeArray: \_gen_scope_array: (work@Foo.genblk1[0]), line:5:45, endln:87:12 |vpiParent: - \_module: work@Foo (work@Foo), file:${SURELOG_DIR}/tests/ExponTimeIfElseGen/dut.sv, line:1:1, endln:91:10 + \_module_inst: work@Foo (work@Foo), file:${SURELOG_DIR}/tests/ExponTimeIfElseGen/dut.sv, line:1:1, endln:91:10 |vpiName:genblk1[0] |vpiFullName:work@Foo.genblk1[0] |vpiGenScope: @@ -1113,7 +1113,7 @@ design: (work@Foo) |vpiGenScopeArray: \_gen_scope_array: (work@Foo.genblk1[1]), line:5:45, endln:87:12 |vpiParent: - \_module: work@Foo (work@Foo), file:${SURELOG_DIR}/tests/ExponTimeIfElseGen/dut.sv, line:1:1, endln:91:10 + \_module_inst: work@Foo (work@Foo), file:${SURELOG_DIR}/tests/ExponTimeIfElseGen/dut.sv, line:1:1, endln:91:10 |vpiName:genblk1[1] |vpiFullName:work@Foo.genblk1[1] |vpiGenScope: @@ -1250,7 +1250,7 @@ design: (work@Foo) |vpiGenScopeArray: \_gen_scope_array: (work@Foo.genblk1[2]), line:5:45, endln:87:12 |vpiParent: - \_module: work@Foo (work@Foo), file:${SURELOG_DIR}/tests/ExponTimeIfElseGen/dut.sv, line:1:1, endln:91:10 + \_module_inst: work@Foo (work@Foo), file:${SURELOG_DIR}/tests/ExponTimeIfElseGen/dut.sv, line:1:1, endln:91:10 |vpiName:genblk1[2] |vpiFullName:work@Foo.genblk1[2] |vpiGenScope: @@ -1271,7 +1271,7 @@ design: (work@Foo) |vpiGenScopeArray: \_gen_scope_array: (work@Foo.genblk1[3]), line:5:45, endln:87:12 |vpiParent: - \_module: work@Foo (work@Foo), file:${SURELOG_DIR}/tests/ExponTimeIfElseGen/dut.sv, line:1:1, endln:91:10 + \_module_inst: work@Foo (work@Foo), file:${SURELOG_DIR}/tests/ExponTimeIfElseGen/dut.sv, line:1:1, endln:91:10 |vpiName:genblk1[3] |vpiFullName:work@Foo.genblk1[3] |vpiGenScope: @@ -1292,7 +1292,7 @@ design: (work@Foo) |vpiGenScopeArray: \_gen_scope_array: (work@Foo.genblk1[4]), line:5:45, endln:87:12 |vpiParent: - \_module: work@Foo (work@Foo), file:${SURELOG_DIR}/tests/ExponTimeIfElseGen/dut.sv, line:1:1, endln:91:10 + \_module_inst: work@Foo (work@Foo), file:${SURELOG_DIR}/tests/ExponTimeIfElseGen/dut.sv, line:1:1, endln:91:10 |vpiName:genblk1[4] |vpiFullName:work@Foo.genblk1[4] |vpiGenScope: @@ -1313,7 +1313,7 @@ design: (work@Foo) |vpiGenScopeArray: \_gen_scope_array: (work@Foo.genblk1[5]), line:5:45, endln:87:12 |vpiParent: - \_module: work@Foo (work@Foo), file:${SURELOG_DIR}/tests/ExponTimeIfElseGen/dut.sv, line:1:1, endln:91:10 + \_module_inst: work@Foo (work@Foo), file:${SURELOG_DIR}/tests/ExponTimeIfElseGen/dut.sv, line:1:1, endln:91:10 |vpiName:genblk1[5] |vpiFullName:work@Foo.genblk1[5] |vpiGenScope: @@ -1334,7 +1334,7 @@ design: (work@Foo) |vpiGenScopeArray: \_gen_scope_array: (work@Foo.genblk1[6]), line:5:45, endln:87:12 |vpiParent: - \_module: work@Foo (work@Foo), file:${SURELOG_DIR}/tests/ExponTimeIfElseGen/dut.sv, line:1:1, endln:91:10 + \_module_inst: work@Foo (work@Foo), file:${SURELOG_DIR}/tests/ExponTimeIfElseGen/dut.sv, line:1:1, endln:91:10 |vpiName:genblk1[6] |vpiFullName:work@Foo.genblk1[6] |vpiGenScope: @@ -1355,7 +1355,7 @@ design: (work@Foo) |vpiGenScopeArray: \_gen_scope_array: (work@Foo.genblk1[7]), line:5:45, endln:87:12 |vpiParent: - \_module: work@Foo (work@Foo), file:${SURELOG_DIR}/tests/ExponTimeIfElseGen/dut.sv, line:1:1, endln:91:10 + \_module_inst: work@Foo (work@Foo), file:${SURELOG_DIR}/tests/ExponTimeIfElseGen/dut.sv, line:1:1, endln:91:10 |vpiName:genblk1[7] |vpiFullName:work@Foo.genblk1[7] |vpiGenScope: @@ -1376,7 +1376,7 @@ design: (work@Foo) |vpiGenScopeArray: \_gen_scope_array: (work@Foo.genblk1[8]), line:5:45, endln:87:12 |vpiParent: - \_module: work@Foo (work@Foo), file:${SURELOG_DIR}/tests/ExponTimeIfElseGen/dut.sv, line:1:1, endln:91:10 + \_module_inst: work@Foo (work@Foo), file:${SURELOG_DIR}/tests/ExponTimeIfElseGen/dut.sv, line:1:1, endln:91:10 |vpiName:genblk1[8] |vpiFullName:work@Foo.genblk1[8] |vpiGenScope: @@ -1397,7 +1397,7 @@ design: (work@Foo) |vpiGenScopeArray: \_gen_scope_array: (work@Foo.genblk1[9]), line:5:45, endln:87:12 |vpiParent: - \_module: work@Foo (work@Foo), file:${SURELOG_DIR}/tests/ExponTimeIfElseGen/dut.sv, line:1:1, endln:91:10 + \_module_inst: work@Foo (work@Foo), file:${SURELOG_DIR}/tests/ExponTimeIfElseGen/dut.sv, line:1:1, endln:91:10 |vpiName:genblk1[9] |vpiFullName:work@Foo.genblk1[9] |vpiGenScope: @@ -1418,7 +1418,7 @@ design: (work@Foo) |vpiGenScopeArray: \_gen_scope_array: (work@Foo.genblk1[10]), line:5:45, endln:87:12 |vpiParent: - \_module: work@Foo (work@Foo), file:${SURELOG_DIR}/tests/ExponTimeIfElseGen/dut.sv, line:1:1, endln:91:10 + \_module_inst: work@Foo (work@Foo), file:${SURELOG_DIR}/tests/ExponTimeIfElseGen/dut.sv, line:1:1, endln:91:10 |vpiName:genblk1[10] |vpiFullName:work@Foo.genblk1[10] |vpiGenScope: @@ -1439,7 +1439,7 @@ design: (work@Foo) |vpiGenScopeArray: \_gen_scope_array: (work@Foo.genblk1[11]), line:5:45, endln:87:12 |vpiParent: - \_module: work@Foo (work@Foo), file:${SURELOG_DIR}/tests/ExponTimeIfElseGen/dut.sv, line:1:1, endln:91:10 + \_module_inst: work@Foo (work@Foo), file:${SURELOG_DIR}/tests/ExponTimeIfElseGen/dut.sv, line:1:1, endln:91:10 |vpiName:genblk1[11] |vpiFullName:work@Foo.genblk1[11] |vpiGenScope: @@ -1460,7 +1460,7 @@ design: (work@Foo) |vpiGenScopeArray: \_gen_scope_array: (work@Foo.genblk1[12]), line:5:45, endln:87:12 |vpiParent: - \_module: work@Foo (work@Foo), file:${SURELOG_DIR}/tests/ExponTimeIfElseGen/dut.sv, line:1:1, endln:91:10 + \_module_inst: work@Foo (work@Foo), file:${SURELOG_DIR}/tests/ExponTimeIfElseGen/dut.sv, line:1:1, endln:91:10 |vpiName:genblk1[12] |vpiFullName:work@Foo.genblk1[12] |vpiGenScope: @@ -1481,7 +1481,7 @@ design: (work@Foo) |vpiGenScopeArray: \_gen_scope_array: (work@Foo.genblk1[13]), line:5:45, endln:87:12 |vpiParent: - \_module: work@Foo (work@Foo), file:${SURELOG_DIR}/tests/ExponTimeIfElseGen/dut.sv, line:1:1, endln:91:10 + \_module_inst: work@Foo (work@Foo), file:${SURELOG_DIR}/tests/ExponTimeIfElseGen/dut.sv, line:1:1, endln:91:10 |vpiName:genblk1[13] |vpiFullName:work@Foo.genblk1[13] |vpiGenScope: @@ -1502,7 +1502,7 @@ design: (work@Foo) |vpiGenScopeArray: \_gen_scope_array: (work@Foo.genblk1[14]), line:5:45, endln:87:12 |vpiParent: - \_module: work@Foo (work@Foo), file:${SURELOG_DIR}/tests/ExponTimeIfElseGen/dut.sv, line:1:1, endln:91:10 + \_module_inst: work@Foo (work@Foo), file:${SURELOG_DIR}/tests/ExponTimeIfElseGen/dut.sv, line:1:1, endln:91:10 |vpiName:genblk1[14] |vpiFullName:work@Foo.genblk1[14] |vpiGenScope: @@ -1523,7 +1523,7 @@ design: (work@Foo) |vpiGenScopeArray: \_gen_scope_array: (work@Foo.genblk1[15]), line:5:45, endln:87:12 |vpiParent: - \_module: work@Foo (work@Foo), file:${SURELOG_DIR}/tests/ExponTimeIfElseGen/dut.sv, line:1:1, endln:91:10 + \_module_inst: work@Foo (work@Foo), file:${SURELOG_DIR}/tests/ExponTimeIfElseGen/dut.sv, line:1:1, endln:91:10 |vpiName:genblk1[15] |vpiFullName:work@Foo.genblk1[15] |vpiGenScope: @@ -1544,7 +1544,7 @@ design: (work@Foo) |vpiGenScopeArray: \_gen_scope_array: (work@Foo.genblk1[16]), line:5:45, endln:87:12 |vpiParent: - \_module: work@Foo (work@Foo), file:${SURELOG_DIR}/tests/ExponTimeIfElseGen/dut.sv, line:1:1, endln:91:10 + \_module_inst: work@Foo (work@Foo), file:${SURELOG_DIR}/tests/ExponTimeIfElseGen/dut.sv, line:1:1, endln:91:10 |vpiName:genblk1[16] |vpiFullName:work@Foo.genblk1[16] |vpiGenScope: @@ -1565,7 +1565,7 @@ design: (work@Foo) |vpiGenScopeArray: \_gen_scope_array: (work@Foo.genblk1[17]), line:5:45, endln:87:12 |vpiParent: - \_module: work@Foo (work@Foo), file:${SURELOG_DIR}/tests/ExponTimeIfElseGen/dut.sv, line:1:1, endln:91:10 + \_module_inst: work@Foo (work@Foo), file:${SURELOG_DIR}/tests/ExponTimeIfElseGen/dut.sv, line:1:1, endln:91:10 |vpiName:genblk1[17] |vpiFullName:work@Foo.genblk1[17] |vpiGenScope: diff --git a/tests/ExtendClassMember/ExtendClassMember.log b/tests/ExtendClassMember/ExtendClassMember.log index e34baee835..1f1ae29bfd 100644 --- a/tests/ExtendClassMember/ExtendClassMember.log +++ b/tests/ExtendClassMember/ExtendClassMember.log @@ -153,7 +153,7 @@ design 1 extends 1 function 2 hier_path 2 -module 1 +module_inst 1 package 3 ref_obj 4 type_parameter 3 @@ -173,7 +173,7 @@ design 1 extends 3 function 4 hier_path 4 -module 1 +module_inst 1 package 3 ref_obj 8 type_parameter 3 diff --git a/tests/FSM2Always/FSM2Always.log b/tests/FSM2Always/FSM2Always.log index 09a7d9a344..9b1984d908 100644 --- a/tests/FSM2Always/FSM2Always.log +++ b/tests/FSM2Always/FSM2Always.log @@ -1145,7 +1145,7 @@ io_decl 11 logic_net 16 logic_typespec 12 logic_var 1 -module 5 +module_inst 5 named_begin 3 operation 14 package 2 @@ -1182,7 +1182,7 @@ io_decl 22 logic_net 16 logic_typespec 12 logic_var 1 -module 5 +module_inst 5 named_begin 6 operation 24 package 2 @@ -1681,14 +1681,14 @@ design: (work@fsm_using_always) \_int_typespec: |vpiSigned:1 |uhdmallModules: -\_module: work@fsm_using_always (work@fsm_using_always), file:${SURELOG_DIR}/tests/FSM2Always/top.sv, line:6:1, endln:91:10 +\_module_inst: work@fsm_using_always (work@fsm_using_always), file:${SURELOG_DIR}/tests/FSM2Always/top.sv, line:6:1, endln:91:10 |vpiParent: \_design: (work@fsm_using_always) |vpiFullName:work@fsm_using_always |vpiParameter: \_parameter: (work@fsm_using_always.SIZE), line:23:11, endln:23:15 |vpiParent: - \_module: work@fsm_using_always (work@fsm_using_always), file:${SURELOG_DIR}/tests/FSM2Always/top.sv, line:6:1, endln:91:10 + \_module_inst: work@fsm_using_always (work@fsm_using_always), file:${SURELOG_DIR}/tests/FSM2Always/top.sv, line:6:1, endln:91:10 |UINT:3 |vpiTypespec: \_int_typespec: @@ -1697,7 +1697,7 @@ design: (work@fsm_using_always) |vpiParameter: \_parameter: (work@fsm_using_always.IDLE), line:24:11, endln:24:15 |vpiParent: - \_module: work@fsm_using_always (work@fsm_using_always), file:${SURELOG_DIR}/tests/FSM2Always/top.sv, line:6:1, endln:91:10 + \_module_inst: work@fsm_using_always (work@fsm_using_always), file:${SURELOG_DIR}/tests/FSM2Always/top.sv, line:6:1, endln:91:10 |BIN:001 |vpiTypespec: \_int_typespec: @@ -1714,7 +1714,7 @@ design: (work@fsm_using_always) |vpiParameter: \_parameter: (work@fsm_using_always.GNT0), line:24:26, endln:24:30 |vpiParent: - \_module: work@fsm_using_always (work@fsm_using_always), file:${SURELOG_DIR}/tests/FSM2Always/top.sv, line:6:1, endln:91:10 + \_module_inst: work@fsm_using_always (work@fsm_using_always), file:${SURELOG_DIR}/tests/FSM2Always/top.sv, line:6:1, endln:91:10 |BIN:010 |vpiTypespec: \_int_typespec: @@ -1731,7 +1731,7 @@ design: (work@fsm_using_always) |vpiParameter: \_parameter: (work@fsm_using_always.GNT1), line:24:40, endln:24:44 |vpiParent: - \_module: work@fsm_using_always (work@fsm_using_always), file:${SURELOG_DIR}/tests/FSM2Always/top.sv, line:6:1, endln:91:10 + \_module_inst: work@fsm_using_always (work@fsm_using_always), file:${SURELOG_DIR}/tests/FSM2Always/top.sv, line:6:1, endln:91:10 |BIN:100 |vpiTypespec: \_int_typespec: @@ -1748,7 +1748,7 @@ design: (work@fsm_using_always) |vpiParamAssign: \_param_assign: , line:23:11, endln:23:19 |vpiParent: - \_module: work@fsm_using_always (work@fsm_using_always), file:${SURELOG_DIR}/tests/FSM2Always/top.sv, line:6:1, endln:91:10 + \_module_inst: work@fsm_using_always (work@fsm_using_always), file:${SURELOG_DIR}/tests/FSM2Always/top.sv, line:6:1, endln:91:10 |vpiRhs: \_constant: , line:23:18, endln:23:19 |vpiDecompile:3 @@ -1762,7 +1762,7 @@ design: (work@fsm_using_always) |vpiParamAssign: \_param_assign: , line:24:11, endln:24:25 |vpiParent: - \_module: work@fsm_using_always (work@fsm_using_always), file:${SURELOG_DIR}/tests/FSM2Always/top.sv, line:6:1, endln:91:10 + \_module_inst: work@fsm_using_always (work@fsm_using_always), file:${SURELOG_DIR}/tests/FSM2Always/top.sv, line:6:1, endln:91:10 |vpiRhs: \_constant: , line:24:19, endln:24:25 |vpiDecompile:3'b001 @@ -1776,7 +1776,7 @@ design: (work@fsm_using_always) |vpiParamAssign: \_param_assign: , line:24:26, endln:24:39 |vpiParent: - \_module: work@fsm_using_always (work@fsm_using_always), file:${SURELOG_DIR}/tests/FSM2Always/top.sv, line:6:1, endln:91:10 + \_module_inst: work@fsm_using_always (work@fsm_using_always), file:${SURELOG_DIR}/tests/FSM2Always/top.sv, line:6:1, endln:91:10 |vpiRhs: \_constant: , line:24:33, endln:24:39 |vpiDecompile:3'b010 @@ -1790,7 +1790,7 @@ design: (work@fsm_using_always) |vpiParamAssign: \_param_assign: , line:24:40, endln:24:53 |vpiParent: - \_module: work@fsm_using_always (work@fsm_using_always), file:${SURELOG_DIR}/tests/FSM2Always/top.sv, line:6:1, endln:91:10 + \_module_inst: work@fsm_using_always (work@fsm_using_always), file:${SURELOG_DIR}/tests/FSM2Always/top.sv, line:6:1, endln:91:10 |vpiRhs: \_constant: , line:24:47, endln:24:53 |vpiDecompile:3'b100 @@ -1805,63 +1805,63 @@ design: (work@fsm_using_always) |vpiNet: \_logic_net: (work@fsm_using_always.clock), line:19:9, endln:19:14 |vpiParent: - \_module: work@fsm_using_always (work@fsm_using_always), file:${SURELOG_DIR}/tests/FSM2Always/top.sv, line:6:1, endln:91:10 + \_module_inst: work@fsm_using_always (work@fsm_using_always), file:${SURELOG_DIR}/tests/FSM2Always/top.sv, line:6:1, endln:91:10 |vpiName:clock |vpiFullName:work@fsm_using_always.clock |vpiNetType:1 |vpiNet: \_logic_net: (work@fsm_using_always.reset), line:19:15, endln:19:20 |vpiParent: - \_module: work@fsm_using_always (work@fsm_using_always), file:${SURELOG_DIR}/tests/FSM2Always/top.sv, line:6:1, endln:91:10 + \_module_inst: work@fsm_using_always (work@fsm_using_always), file:${SURELOG_DIR}/tests/FSM2Always/top.sv, line:6:1, endln:91:10 |vpiName:reset |vpiFullName:work@fsm_using_always.reset |vpiNetType:1 |vpiNet: \_logic_net: (work@fsm_using_always.req_0), line:19:21, endln:19:26 |vpiParent: - \_module: work@fsm_using_always (work@fsm_using_always), file:${SURELOG_DIR}/tests/FSM2Always/top.sv, line:6:1, endln:91:10 + \_module_inst: work@fsm_using_always (work@fsm_using_always), file:${SURELOG_DIR}/tests/FSM2Always/top.sv, line:6:1, endln:91:10 |vpiName:req_0 |vpiFullName:work@fsm_using_always.req_0 |vpiNetType:1 |vpiNet: \_logic_net: (work@fsm_using_always.req_1), line:19:27, endln:19:32 |vpiParent: - \_module: work@fsm_using_always (work@fsm_using_always), file:${SURELOG_DIR}/tests/FSM2Always/top.sv, line:6:1, endln:91:10 + \_module_inst: work@fsm_using_always (work@fsm_using_always), file:${SURELOG_DIR}/tests/FSM2Always/top.sv, line:6:1, endln:91:10 |vpiName:req_1 |vpiFullName:work@fsm_using_always.req_1 |vpiNetType:1 |vpiNet: \_logic_net: (work@fsm_using_always.gnt_0), line:21:9, endln:21:14 |vpiParent: - \_module: work@fsm_using_always (work@fsm_using_always), file:${SURELOG_DIR}/tests/FSM2Always/top.sv, line:6:1, endln:91:10 + \_module_inst: work@fsm_using_always (work@fsm_using_always), file:${SURELOG_DIR}/tests/FSM2Always/top.sv, line:6:1, endln:91:10 |vpiName:gnt_0 |vpiFullName:work@fsm_using_always.gnt_0 |vpiNetType:48 |vpiNet: \_logic_net: (work@fsm_using_always.gnt_1), line:21:15, endln:21:20 |vpiParent: - \_module: work@fsm_using_always (work@fsm_using_always), file:${SURELOG_DIR}/tests/FSM2Always/top.sv, line:6:1, endln:91:10 + \_module_inst: work@fsm_using_always (work@fsm_using_always), file:${SURELOG_DIR}/tests/FSM2Always/top.sv, line:6:1, endln:91:10 |vpiName:gnt_1 |vpiFullName:work@fsm_using_always.gnt_1 |vpiNetType:48 |vpiNet: \_logic_net: (work@fsm_using_always.state), line:26:27, endln:26:32 |vpiParent: - \_module: work@fsm_using_always (work@fsm_using_always), file:${SURELOG_DIR}/tests/FSM2Always/top.sv, line:6:1, endln:91:10 + \_module_inst: work@fsm_using_always (work@fsm_using_always), file:${SURELOG_DIR}/tests/FSM2Always/top.sv, line:6:1, endln:91:10 |vpiName:state |vpiFullName:work@fsm_using_always.state |vpiNetType:48 |vpiNet: \_logic_net: (work@fsm_using_always.next_state), line:27:27, endln:27:37 |vpiParent: - \_module: work@fsm_using_always (work@fsm_using_always), file:${SURELOG_DIR}/tests/FSM2Always/top.sv, line:6:1, endln:91:10 + \_module_inst: work@fsm_using_always (work@fsm_using_always), file:${SURELOG_DIR}/tests/FSM2Always/top.sv, line:6:1, endln:91:10 |vpiName:next_state |vpiFullName:work@fsm_using_always.next_state |vpiNetType:48 |vpiPort: \_port: (clock), line:7:1, endln:7:6 |vpiParent: - \_module: work@fsm_using_always (work@fsm_using_always), file:${SURELOG_DIR}/tests/FSM2Always/top.sv, line:6:1, endln:91:10 + \_module_inst: work@fsm_using_always (work@fsm_using_always), file:${SURELOG_DIR}/tests/FSM2Always/top.sv, line:6:1, endln:91:10 |vpiName:clock |vpiDirection:1 |vpiLowConn: @@ -1873,7 +1873,7 @@ design: (work@fsm_using_always) |vpiPort: \_port: (reset), line:8:1, endln:8:6 |vpiParent: - \_module: work@fsm_using_always (work@fsm_using_always), file:${SURELOG_DIR}/tests/FSM2Always/top.sv, line:6:1, endln:91:10 + \_module_inst: work@fsm_using_always (work@fsm_using_always), file:${SURELOG_DIR}/tests/FSM2Always/top.sv, line:6:1, endln:91:10 |vpiName:reset |vpiDirection:1 |vpiLowConn: @@ -1885,7 +1885,7 @@ design: (work@fsm_using_always) |vpiPort: \_port: (req_0), line:9:1, endln:9:6 |vpiParent: - \_module: work@fsm_using_always (work@fsm_using_always), file:${SURELOG_DIR}/tests/FSM2Always/top.sv, line:6:1, endln:91:10 + \_module_inst: work@fsm_using_always (work@fsm_using_always), file:${SURELOG_DIR}/tests/FSM2Always/top.sv, line:6:1, endln:91:10 |vpiName:req_0 |vpiDirection:1 |vpiLowConn: @@ -1897,7 +1897,7 @@ design: (work@fsm_using_always) |vpiPort: \_port: (req_1), line:10:1, endln:10:6 |vpiParent: - \_module: work@fsm_using_always (work@fsm_using_always), file:${SURELOG_DIR}/tests/FSM2Always/top.sv, line:6:1, endln:91:10 + \_module_inst: work@fsm_using_always (work@fsm_using_always), file:${SURELOG_DIR}/tests/FSM2Always/top.sv, line:6:1, endln:91:10 |vpiName:req_1 |vpiDirection:1 |vpiLowConn: @@ -1909,7 +1909,7 @@ design: (work@fsm_using_always) |vpiPort: \_port: (gnt_0), line:11:1, endln:11:6 |vpiParent: - \_module: work@fsm_using_always (work@fsm_using_always), file:${SURELOG_DIR}/tests/FSM2Always/top.sv, line:6:1, endln:91:10 + \_module_inst: work@fsm_using_always (work@fsm_using_always), file:${SURELOG_DIR}/tests/FSM2Always/top.sv, line:6:1, endln:91:10 |vpiName:gnt_0 |vpiDirection:2 |vpiLowConn: @@ -1921,7 +1921,7 @@ design: (work@fsm_using_always) |vpiPort: \_port: (gnt_1), line:12:1, endln:12:6 |vpiParent: - \_module: work@fsm_using_always (work@fsm_using_always), file:${SURELOG_DIR}/tests/FSM2Always/top.sv, line:6:1, endln:91:10 + \_module_inst: work@fsm_using_always (work@fsm_using_always), file:${SURELOG_DIR}/tests/FSM2Always/top.sv, line:6:1, endln:91:10 |vpiName:gnt_1 |vpiDirection:2 |vpiLowConn: @@ -1933,7 +1933,7 @@ design: (work@fsm_using_always) |vpiProcess: \_always: , line:29:1, endln:52:4 |vpiParent: - \_module: work@fsm_using_always (work@fsm_using_always), file:${SURELOG_DIR}/tests/FSM2Always/top.sv, line:6:1, endln:91:10 + \_module_inst: work@fsm_using_always (work@fsm_using_always), file:${SURELOG_DIR}/tests/FSM2Always/top.sv, line:6:1, endln:91:10 |vpiStmt: \_event_control: , line:29:8, endln:29:35 |vpiParent: @@ -2335,7 +2335,7 @@ design: (work@fsm_using_always) |vpiProcess: \_always: , line:54:1, endln:61:4 |vpiParent: - \_module: work@fsm_using_always (work@fsm_using_always), file:${SURELOG_DIR}/tests/FSM2Always/top.sv, line:6:1, endln:91:10 + \_module_inst: work@fsm_using_always (work@fsm_using_always), file:${SURELOG_DIR}/tests/FSM2Always/top.sv, line:6:1, endln:91:10 |vpiStmt: \_event_control: , line:54:8, endln:54:25 |vpiParent: @@ -2448,7 +2448,7 @@ design: (work@fsm_using_always) |vpiProcess: \_always: , line:63:1, endln:89:4 |vpiParent: - \_module: work@fsm_using_always (work@fsm_using_always), file:${SURELOG_DIR}/tests/FSM2Always/top.sv, line:6:1, endln:91:10 + \_module_inst: work@fsm_using_always (work@fsm_using_always), file:${SURELOG_DIR}/tests/FSM2Always/top.sv, line:6:1, endln:91:10 |vpiStmt: \_event_control: , line:63:8, endln:63:25 |vpiParent: @@ -2836,12 +2836,12 @@ design: (work@fsm_using_always) |#1 |vpiAlwaysType:1 |uhdmtopModules: -\_module: work@fsm_using_always (work@fsm_using_always), file:${SURELOG_DIR}/tests/FSM2Always/top.sv, line:6:1, endln:91:10 +\_module_inst: work@fsm_using_always (work@fsm_using_always), file:${SURELOG_DIR}/tests/FSM2Always/top.sv, line:6:1, endln:91:10 |vpiName:work@fsm_using_always |vpiParameter: \_parameter: (work@fsm_using_always.SIZE), line:23:11, endln:23:15 |vpiParent: - \_module: work@fsm_using_always (work@fsm_using_always), file:${SURELOG_DIR}/tests/FSM2Always/top.sv, line:6:1, endln:91:10 + \_module_inst: work@fsm_using_always (work@fsm_using_always), file:${SURELOG_DIR}/tests/FSM2Always/top.sv, line:6:1, endln:91:10 |UINT:3 |vpiTypespec: \_int_typespec: @@ -2852,7 +2852,7 @@ design: (work@fsm_using_always) |vpiParameter: \_parameter: (work@fsm_using_always.IDLE), line:24:11, endln:24:15 |vpiParent: - \_module: work@fsm_using_always (work@fsm_using_always), file:${SURELOG_DIR}/tests/FSM2Always/top.sv, line:6:1, endln:91:10 + \_module_inst: work@fsm_using_always (work@fsm_using_always), file:${SURELOG_DIR}/tests/FSM2Always/top.sv, line:6:1, endln:91:10 |BIN:001 |vpiTypespec: \_int_typespec: @@ -2877,7 +2877,7 @@ design: (work@fsm_using_always) |vpiParameter: \_parameter: (work@fsm_using_always.GNT0), line:24:26, endln:24:30 |vpiParent: - \_module: work@fsm_using_always (work@fsm_using_always), file:${SURELOG_DIR}/tests/FSM2Always/top.sv, line:6:1, endln:91:10 + \_module_inst: work@fsm_using_always (work@fsm_using_always), file:${SURELOG_DIR}/tests/FSM2Always/top.sv, line:6:1, endln:91:10 |BIN:010 |vpiTypespec: \_int_typespec: @@ -2902,7 +2902,7 @@ design: (work@fsm_using_always) |vpiParameter: \_parameter: (work@fsm_using_always.GNT1), line:24:40, endln:24:44 |vpiParent: - \_module: work@fsm_using_always (work@fsm_using_always), file:${SURELOG_DIR}/tests/FSM2Always/top.sv, line:6:1, endln:91:10 + \_module_inst: work@fsm_using_always (work@fsm_using_always), file:${SURELOG_DIR}/tests/FSM2Always/top.sv, line:6:1, endln:91:10 |BIN:100 |vpiTypespec: \_int_typespec: @@ -2927,7 +2927,7 @@ design: (work@fsm_using_always) |vpiParamAssign: \_param_assign: , line:23:11, endln:23:19 |vpiParent: - \_module: work@fsm_using_always (work@fsm_using_always), file:${SURELOG_DIR}/tests/FSM2Always/top.sv, line:6:1, endln:91:10 + \_module_inst: work@fsm_using_always (work@fsm_using_always), file:${SURELOG_DIR}/tests/FSM2Always/top.sv, line:6:1, endln:91:10 |vpiRhs: \_constant: , line:23:18, endln:23:19 |vpiDecompile:3 @@ -2941,7 +2941,7 @@ design: (work@fsm_using_always) |vpiParamAssign: \_param_assign: , line:24:11, endln:24:25 |vpiParent: - \_module: work@fsm_using_always (work@fsm_using_always), file:${SURELOG_DIR}/tests/FSM2Always/top.sv, line:6:1, endln:91:10 + \_module_inst: work@fsm_using_always (work@fsm_using_always), file:${SURELOG_DIR}/tests/FSM2Always/top.sv, line:6:1, endln:91:10 |vpiRhs: \_constant: , line:24:19, endln:24:25 |vpiDecompile:3'b001 @@ -2955,7 +2955,7 @@ design: (work@fsm_using_always) |vpiParamAssign: \_param_assign: , line:24:26, endln:24:39 |vpiParent: - \_module: work@fsm_using_always (work@fsm_using_always), file:${SURELOG_DIR}/tests/FSM2Always/top.sv, line:6:1, endln:91:10 + \_module_inst: work@fsm_using_always (work@fsm_using_always), file:${SURELOG_DIR}/tests/FSM2Always/top.sv, line:6:1, endln:91:10 |vpiRhs: \_constant: , line:24:33, endln:24:39 |vpiDecompile:3'b010 @@ -2969,7 +2969,7 @@ design: (work@fsm_using_always) |vpiParamAssign: \_param_assign: , line:24:40, endln:24:53 |vpiParent: - \_module: work@fsm_using_always (work@fsm_using_always), file:${SURELOG_DIR}/tests/FSM2Always/top.sv, line:6:1, endln:91:10 + \_module_inst: work@fsm_using_always (work@fsm_using_always), file:${SURELOG_DIR}/tests/FSM2Always/top.sv, line:6:1, endln:91:10 |vpiRhs: \_constant: , line:24:47, endln:24:53 |vpiDecompile:3'b100 @@ -2985,7 +2985,7 @@ design: (work@fsm_using_always) |vpiNet: \_logic_net: (work@fsm_using_always.clock), line:19:9, endln:19:14 |vpiParent: - \_module: work@fsm_using_always (work@fsm_using_always), file:${SURELOG_DIR}/tests/FSM2Always/top.sv, line:6:1, endln:91:10 + \_module_inst: work@fsm_using_always (work@fsm_using_always), file:${SURELOG_DIR}/tests/FSM2Always/top.sv, line:6:1, endln:91:10 |vpiTypespec: \_logic_typespec: , line:19:1, endln:19:5 |vpiName:clock @@ -2994,7 +2994,7 @@ design: (work@fsm_using_always) |vpiNet: \_logic_net: (work@fsm_using_always.reset), line:19:15, endln:19:20 |vpiParent: - \_module: work@fsm_using_always (work@fsm_using_always), file:${SURELOG_DIR}/tests/FSM2Always/top.sv, line:6:1, endln:91:10 + \_module_inst: work@fsm_using_always (work@fsm_using_always), file:${SURELOG_DIR}/tests/FSM2Always/top.sv, line:6:1, endln:91:10 |vpiTypespec: \_logic_typespec: , line:19:1, endln:19:5 |vpiName:reset @@ -3003,7 +3003,7 @@ design: (work@fsm_using_always) |vpiNet: \_logic_net: (work@fsm_using_always.req_0), line:19:21, endln:19:26 |vpiParent: - \_module: work@fsm_using_always (work@fsm_using_always), file:${SURELOG_DIR}/tests/FSM2Always/top.sv, line:6:1, endln:91:10 + \_module_inst: work@fsm_using_always (work@fsm_using_always), file:${SURELOG_DIR}/tests/FSM2Always/top.sv, line:6:1, endln:91:10 |vpiTypespec: \_logic_typespec: , line:19:1, endln:19:5 |vpiName:req_0 @@ -3012,7 +3012,7 @@ design: (work@fsm_using_always) |vpiNet: \_logic_net: (work@fsm_using_always.req_1), line:19:27, endln:19:32 |vpiParent: - \_module: work@fsm_using_always (work@fsm_using_always), file:${SURELOG_DIR}/tests/FSM2Always/top.sv, line:6:1, endln:91:10 + \_module_inst: work@fsm_using_always (work@fsm_using_always), file:${SURELOG_DIR}/tests/FSM2Always/top.sv, line:6:1, endln:91:10 |vpiTypespec: \_logic_typespec: , line:19:1, endln:19:5 |vpiName:req_1 @@ -3021,7 +3021,7 @@ design: (work@fsm_using_always) |vpiNet: \_logic_net: (work@fsm_using_always.gnt_0), line:21:9, endln:21:14 |vpiParent: - \_module: work@fsm_using_always (work@fsm_using_always), file:${SURELOG_DIR}/tests/FSM2Always/top.sv, line:6:1, endln:91:10 + \_module_inst: work@fsm_using_always (work@fsm_using_always), file:${SURELOG_DIR}/tests/FSM2Always/top.sv, line:6:1, endln:91:10 |vpiTypespec: \_logic_typespec: , line:21:1, endln:21:4 |vpiName:gnt_0 @@ -3030,7 +3030,7 @@ design: (work@fsm_using_always) |vpiNet: \_logic_net: (work@fsm_using_always.gnt_1), line:21:15, endln:21:20 |vpiParent: - \_module: work@fsm_using_always (work@fsm_using_always), file:${SURELOG_DIR}/tests/FSM2Always/top.sv, line:6:1, endln:91:10 + \_module_inst: work@fsm_using_always (work@fsm_using_always), file:${SURELOG_DIR}/tests/FSM2Always/top.sv, line:6:1, endln:91:10 |vpiTypespec: \_logic_typespec: , line:21:1, endln:21:4 |vpiName:gnt_1 @@ -3039,7 +3039,7 @@ design: (work@fsm_using_always) |vpiNet: \_logic_net: (work@fsm_using_always.state), line:26:27, endln:26:32 |vpiParent: - \_module: work@fsm_using_always (work@fsm_using_always), file:${SURELOG_DIR}/tests/FSM2Always/top.sv, line:6:1, endln:91:10 + \_module_inst: work@fsm_using_always (work@fsm_using_always), file:${SURELOG_DIR}/tests/FSM2Always/top.sv, line:6:1, endln:91:10 |vpiTypespec: \_logic_typespec: , line:26:1, endln:26:17 |vpiRange: @@ -3066,7 +3066,7 @@ design: (work@fsm_using_always) |vpiNet: \_logic_net: (work@fsm_using_always.next_state), line:27:27, endln:27:37 |vpiParent: - \_module: work@fsm_using_always (work@fsm_using_always), file:${SURELOG_DIR}/tests/FSM2Always/top.sv, line:6:1, endln:91:10 + \_module_inst: work@fsm_using_always (work@fsm_using_always), file:${SURELOG_DIR}/tests/FSM2Always/top.sv, line:6:1, endln:91:10 |vpiTypespec: \_logic_typespec: , line:27:1, endln:27:17 |vpiRange: @@ -3094,7 +3094,7 @@ design: (work@fsm_using_always) |vpiPort: \_port: (clock), line:7:1, endln:7:6 |vpiParent: - \_module: work@fsm_using_always (work@fsm_using_always), file:${SURELOG_DIR}/tests/FSM2Always/top.sv, line:6:1, endln:91:10 + \_module_inst: work@fsm_using_always (work@fsm_using_always), file:${SURELOG_DIR}/tests/FSM2Always/top.sv, line:6:1, endln:91:10 |vpiName:clock |vpiDirection:1 |vpiLowConn: @@ -3108,11 +3108,11 @@ design: (work@fsm_using_always) |vpiTypedef: \_logic_typespec: , line:15:9, endln:15:9 |vpiInstance: - \_module: work@fsm_using_always (work@fsm_using_always), file:${SURELOG_DIR}/tests/FSM2Always/top.sv, line:6:1, endln:91:10 + \_module_inst: work@fsm_using_always (work@fsm_using_always), file:${SURELOG_DIR}/tests/FSM2Always/top.sv, line:6:1, endln:91:10 |vpiPort: \_port: (reset), line:8:1, endln:8:6 |vpiParent: - \_module: work@fsm_using_always (work@fsm_using_always), file:${SURELOG_DIR}/tests/FSM2Always/top.sv, line:6:1, endln:91:10 + \_module_inst: work@fsm_using_always (work@fsm_using_always), file:${SURELOG_DIR}/tests/FSM2Always/top.sv, line:6:1, endln:91:10 |vpiName:reset |vpiDirection:1 |vpiLowConn: @@ -3126,11 +3126,11 @@ design: (work@fsm_using_always) |vpiTypedef: \_logic_typespec: , line:15:9, endln:15:9 |vpiInstance: - \_module: work@fsm_using_always (work@fsm_using_always), file:${SURELOG_DIR}/tests/FSM2Always/top.sv, line:6:1, endln:91:10 + \_module_inst: work@fsm_using_always (work@fsm_using_always), file:${SURELOG_DIR}/tests/FSM2Always/top.sv, line:6:1, endln:91:10 |vpiPort: \_port: (req_0), line:9:1, endln:9:6 |vpiParent: - \_module: work@fsm_using_always (work@fsm_using_always), file:${SURELOG_DIR}/tests/FSM2Always/top.sv, line:6:1, endln:91:10 + \_module_inst: work@fsm_using_always (work@fsm_using_always), file:${SURELOG_DIR}/tests/FSM2Always/top.sv, line:6:1, endln:91:10 |vpiName:req_0 |vpiDirection:1 |vpiLowConn: @@ -3144,11 +3144,11 @@ design: (work@fsm_using_always) |vpiTypedef: \_logic_typespec: , line:15:9, endln:15:9 |vpiInstance: - \_module: work@fsm_using_always (work@fsm_using_always), file:${SURELOG_DIR}/tests/FSM2Always/top.sv, line:6:1, endln:91:10 + \_module_inst: work@fsm_using_always (work@fsm_using_always), file:${SURELOG_DIR}/tests/FSM2Always/top.sv, line:6:1, endln:91:10 |vpiPort: \_port: (req_1), line:10:1, endln:10:6 |vpiParent: - \_module: work@fsm_using_always (work@fsm_using_always), file:${SURELOG_DIR}/tests/FSM2Always/top.sv, line:6:1, endln:91:10 + \_module_inst: work@fsm_using_always (work@fsm_using_always), file:${SURELOG_DIR}/tests/FSM2Always/top.sv, line:6:1, endln:91:10 |vpiName:req_1 |vpiDirection:1 |vpiLowConn: @@ -3162,11 +3162,11 @@ design: (work@fsm_using_always) |vpiTypedef: \_logic_typespec: , line:15:9, endln:15:9 |vpiInstance: - \_module: work@fsm_using_always (work@fsm_using_always), file:${SURELOG_DIR}/tests/FSM2Always/top.sv, line:6:1, endln:91:10 + \_module_inst: work@fsm_using_always (work@fsm_using_always), file:${SURELOG_DIR}/tests/FSM2Always/top.sv, line:6:1, endln:91:10 |vpiPort: \_port: (gnt_0), line:11:1, endln:11:6 |vpiParent: - \_module: work@fsm_using_always (work@fsm_using_always), file:${SURELOG_DIR}/tests/FSM2Always/top.sv, line:6:1, endln:91:10 + \_module_inst: work@fsm_using_always (work@fsm_using_always), file:${SURELOG_DIR}/tests/FSM2Always/top.sv, line:6:1, endln:91:10 |vpiName:gnt_0 |vpiDirection:2 |vpiLowConn: @@ -3180,11 +3180,11 @@ design: (work@fsm_using_always) |vpiTypedef: \_logic_typespec: , line:17:9, endln:17:9 |vpiInstance: - \_module: work@fsm_using_always (work@fsm_using_always), file:${SURELOG_DIR}/tests/FSM2Always/top.sv, line:6:1, endln:91:10 + \_module_inst: work@fsm_using_always (work@fsm_using_always), file:${SURELOG_DIR}/tests/FSM2Always/top.sv, line:6:1, endln:91:10 |vpiPort: \_port: (gnt_1), line:12:1, endln:12:6 |vpiParent: - \_module: work@fsm_using_always (work@fsm_using_always), file:${SURELOG_DIR}/tests/FSM2Always/top.sv, line:6:1, endln:91:10 + \_module_inst: work@fsm_using_always (work@fsm_using_always), file:${SURELOG_DIR}/tests/FSM2Always/top.sv, line:6:1, endln:91:10 |vpiName:gnt_1 |vpiDirection:2 |vpiLowConn: @@ -3198,11 +3198,11 @@ design: (work@fsm_using_always) |vpiTypedef: \_logic_typespec: , line:17:9, endln:17:9 |vpiInstance: - \_module: work@fsm_using_always (work@fsm_using_always), file:${SURELOG_DIR}/tests/FSM2Always/top.sv, line:6:1, endln:91:10 + \_module_inst: work@fsm_using_always (work@fsm_using_always), file:${SURELOG_DIR}/tests/FSM2Always/top.sv, line:6:1, endln:91:10 |vpiProcess: \_always: , line:29:1, endln:52:4 |vpiParent: - \_module: work@fsm_using_always (work@fsm_using_always), file:${SURELOG_DIR}/tests/FSM2Always/top.sv, line:6:1, endln:91:10 + \_module_inst: work@fsm_using_always (work@fsm_using_always), file:${SURELOG_DIR}/tests/FSM2Always/top.sv, line:6:1, endln:91:10 |vpiStmt: \_event_control: , line:29:8, endln:29:35 |vpiParent: @@ -3607,7 +3607,7 @@ design: (work@fsm_using_always) |vpiProcess: \_always: , line:54:1, endln:61:4 |vpiParent: - \_module: work@fsm_using_always (work@fsm_using_always), file:${SURELOG_DIR}/tests/FSM2Always/top.sv, line:6:1, endln:91:10 + \_module_inst: work@fsm_using_always (work@fsm_using_always), file:${SURELOG_DIR}/tests/FSM2Always/top.sv, line:6:1, endln:91:10 |vpiStmt: \_event_control: , line:54:8, endln:54:25 |vpiParent: @@ -3716,7 +3716,7 @@ design: (work@fsm_using_always) |vpiProcess: \_always: , line:63:1, endln:89:4 |vpiParent: - \_module: work@fsm_using_always (work@fsm_using_always), file:${SURELOG_DIR}/tests/FSM2Always/top.sv, line:6:1, endln:91:10 + \_module_inst: work@fsm_using_always (work@fsm_using_always), file:${SURELOG_DIR}/tests/FSM2Always/top.sv, line:6:1, endln:91:10 |vpiStmt: \_event_control: , line:63:8, endln:63:25 |vpiParent: diff --git a/tests/FSMBsp13/FSMBsp13.log b/tests/FSMBsp13/FSMBsp13.log index 8a2d8a9e2e..4907abec7e 100644 --- a/tests/FSMBsp13/FSMBsp13.log +++ b/tests/FSMBsp13/FSMBsp13.log @@ -6411,7 +6411,7 @@ io_decl 11 logic_net 114 logic_typespec 36 logic_var 1 -module 16 +module_inst 16 named_begin 6 operation 116 package 2 @@ -6454,7 +6454,7 @@ io_decl 22 logic_net 114 logic_typespec 36 logic_var 1 -module 16 +module_inst 16 named_begin 12 operation 232 package 2 @@ -6955,14 +6955,14 @@ design: (work@top) \_int_typespec: |vpiSigned:1 |uhdmallModules: -\_module: work@FSM1 (work@FSM1), file:${SURELOG_DIR}/tests/FSMBsp13/fsm1.v, line:1:1, endln:158:10 +\_module_inst: work@FSM1 (work@FSM1), file:${SURELOG_DIR}/tests/FSMBsp13/fsm1.v, line:1:1, endln:158:10 |vpiParent: \_design: (work@top) |vpiFullName:work@FSM1 |vpiParameter: \_parameter: (work@FSM1.ST_Read), line:7:17, endln:7:24 |vpiParent: - \_module: work@FSM1 (work@FSM1), file:${SURELOG_DIR}/tests/FSMBsp13/fsm1.v, line:1:1, endln:158:10 + \_module_inst: work@FSM1 (work@FSM1), file:${SURELOG_DIR}/tests/FSMBsp13/fsm1.v, line:1:1, endln:158:10 |UINT:0 |vpiTypespec: \_int_typespec: , line:7:11, endln:7:16 @@ -6991,7 +6991,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@FSM1.ST_Write), line:7:30, endln:7:38 |vpiParent: - \_module: work@FSM1 (work@FSM1), file:${SURELOG_DIR}/tests/FSMBsp13/fsm1.v, line:1:1, endln:158:10 + \_module_inst: work@FSM1 (work@FSM1), file:${SURELOG_DIR}/tests/FSMBsp13/fsm1.v, line:1:1, endln:158:10 |UINT:1 |vpiTypespec: \_int_typespec: , line:7:11, endln:7:16 @@ -7020,7 +7020,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@FSM1.ST_Delay), line:7:44, endln:7:52 |vpiParent: - \_module: work@FSM1 (work@FSM1), file:${SURELOG_DIR}/tests/FSMBsp13/fsm1.v, line:1:1, endln:158:10 + \_module_inst: work@FSM1 (work@FSM1), file:${SURELOG_DIR}/tests/FSMBsp13/fsm1.v, line:1:1, endln:158:10 |UINT:2 |vpiTypespec: \_int_typespec: , line:7:11, endln:7:16 @@ -7049,7 +7049,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@FSM1.ST_Trx), line:8:17, endln:8:23 |vpiParent: - \_module: work@FSM1 (work@FSM1), file:${SURELOG_DIR}/tests/FSMBsp13/fsm1.v, line:1:1, endln:158:10 + \_module_inst: work@FSM1 (work@FSM1), file:${SURELOG_DIR}/tests/FSMBsp13/fsm1.v, line:1:1, endln:158:10 |UINT:3 |vpiTypespec: \_int_typespec: , line:7:11, endln:7:16 @@ -7078,7 +7078,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@FSM1.ST_Hold), line:8:29, endln:8:36 |vpiParent: - \_module: work@FSM1 (work@FSM1), file:${SURELOG_DIR}/tests/FSMBsp13/fsm1.v, line:1:1, endln:158:10 + \_module_inst: work@FSM1 (work@FSM1), file:${SURELOG_DIR}/tests/FSMBsp13/fsm1.v, line:1:1, endln:158:10 |UINT:4 |vpiTypespec: \_int_typespec: , line:7:11, endln:7:16 @@ -7107,7 +7107,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@FSM1.ST_Block), line:8:42, endln:8:50 |vpiParent: - \_module: work@FSM1 (work@FSM1), file:${SURELOG_DIR}/tests/FSMBsp13/fsm1.v, line:1:1, endln:158:10 + \_module_inst: work@FSM1 (work@FSM1), file:${SURELOG_DIR}/tests/FSMBsp13/fsm1.v, line:1:1, endln:158:10 |UINT:5 |vpiTypespec: \_int_typespec: , line:7:11, endln:7:16 @@ -7136,7 +7136,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@FSM1.ST_Wait), line:9:17, endln:9:24 |vpiParent: - \_module: work@FSM1 (work@FSM1), file:${SURELOG_DIR}/tests/FSMBsp13/fsm1.v, line:1:1, endln:158:10 + \_module_inst: work@FSM1 (work@FSM1), file:${SURELOG_DIR}/tests/FSMBsp13/fsm1.v, line:1:1, endln:158:10 |UINT:6 |vpiTypespec: \_int_typespec: , line:7:11, endln:7:16 @@ -7165,7 +7165,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@FSM1.ST_Turn), line:9:30, endln:9:37 |vpiParent: - \_module: work@FSM1 (work@FSM1), file:${SURELOG_DIR}/tests/FSMBsp13/fsm1.v, line:1:1, endln:158:10 + \_module_inst: work@FSM1 (work@FSM1), file:${SURELOG_DIR}/tests/FSMBsp13/fsm1.v, line:1:1, endln:158:10 |UINT:7 |vpiTypespec: \_int_typespec: , line:7:11, endln:7:16 @@ -7194,7 +7194,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@FSM1.ST_Quit), line:9:43, endln:9:50 |vpiParent: - \_module: work@FSM1 (work@FSM1), file:${SURELOG_DIR}/tests/FSMBsp13/fsm1.v, line:1:1, endln:158:10 + \_module_inst: work@FSM1 (work@FSM1), file:${SURELOG_DIR}/tests/FSMBsp13/fsm1.v, line:1:1, endln:158:10 |UINT:8 |vpiTypespec: \_int_typespec: , line:7:11, endln:7:16 @@ -7223,7 +7223,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@FSM1.ST_Exit), line:10:17, endln:10:24 |vpiParent: - \_module: work@FSM1 (work@FSM1), file:${SURELOG_DIR}/tests/FSMBsp13/fsm1.v, line:1:1, endln:158:10 + \_module_inst: work@FSM1 (work@FSM1), file:${SURELOG_DIR}/tests/FSMBsp13/fsm1.v, line:1:1, endln:158:10 |UINT:9 |vpiTypespec: \_int_typespec: , line:7:11, endln:7:16 @@ -7252,7 +7252,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@FSM1.ST_Done), line:10:30, endln:10:37 |vpiParent: - \_module: work@FSM1 (work@FSM1), file:${SURELOG_DIR}/tests/FSMBsp13/fsm1.v, line:1:1, endln:158:10 + \_module_inst: work@FSM1 (work@FSM1), file:${SURELOG_DIR}/tests/FSMBsp13/fsm1.v, line:1:1, endln:158:10 |UINT:10 |vpiTypespec: \_int_typespec: , line:7:11, endln:7:16 @@ -7281,7 +7281,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:7:17, endln:7:28 |vpiParent: - \_module: work@FSM1 (work@FSM1), file:${SURELOG_DIR}/tests/FSMBsp13/fsm1.v, line:1:1, endln:158:10 + \_module_inst: work@FSM1 (work@FSM1), file:${SURELOG_DIR}/tests/FSMBsp13/fsm1.v, line:1:1, endln:158:10 |vpiRhs: \_constant: , line:7:27, endln:7:28 |vpiDecompile:0 @@ -7295,7 +7295,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:7:30, endln:7:42 |vpiParent: - \_module: work@FSM1 (work@FSM1), file:${SURELOG_DIR}/tests/FSMBsp13/fsm1.v, line:1:1, endln:158:10 + \_module_inst: work@FSM1 (work@FSM1), file:${SURELOG_DIR}/tests/FSMBsp13/fsm1.v, line:1:1, endln:158:10 |vpiRhs: \_constant: , line:7:41, endln:7:42 |vpiDecompile:1 @@ -7309,7 +7309,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:7:44, endln:7:56 |vpiParent: - \_module: work@FSM1 (work@FSM1), file:${SURELOG_DIR}/tests/FSMBsp13/fsm1.v, line:1:1, endln:158:10 + \_module_inst: work@FSM1 (work@FSM1), file:${SURELOG_DIR}/tests/FSMBsp13/fsm1.v, line:1:1, endln:158:10 |vpiRhs: \_constant: , line:7:55, endln:7:56 |vpiDecompile:2 @@ -7323,7 +7323,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:8:17, endln:8:27 |vpiParent: - \_module: work@FSM1 (work@FSM1), file:${SURELOG_DIR}/tests/FSMBsp13/fsm1.v, line:1:1, endln:158:10 + \_module_inst: work@FSM1 (work@FSM1), file:${SURELOG_DIR}/tests/FSMBsp13/fsm1.v, line:1:1, endln:158:10 |vpiRhs: \_constant: , line:8:26, endln:8:27 |vpiDecompile:3 @@ -7337,7 +7337,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:8:29, endln:8:40 |vpiParent: - \_module: work@FSM1 (work@FSM1), file:${SURELOG_DIR}/tests/FSMBsp13/fsm1.v, line:1:1, endln:158:10 + \_module_inst: work@FSM1 (work@FSM1), file:${SURELOG_DIR}/tests/FSMBsp13/fsm1.v, line:1:1, endln:158:10 |vpiRhs: \_constant: , line:8:39, endln:8:40 |vpiDecompile:4 @@ -7351,7 +7351,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:8:42, endln:8:54 |vpiParent: - \_module: work@FSM1 (work@FSM1), file:${SURELOG_DIR}/tests/FSMBsp13/fsm1.v, line:1:1, endln:158:10 + \_module_inst: work@FSM1 (work@FSM1), file:${SURELOG_DIR}/tests/FSMBsp13/fsm1.v, line:1:1, endln:158:10 |vpiRhs: \_constant: , line:8:53, endln:8:54 |vpiDecompile:5 @@ -7365,7 +7365,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:9:17, endln:9:28 |vpiParent: - \_module: work@FSM1 (work@FSM1), file:${SURELOG_DIR}/tests/FSMBsp13/fsm1.v, line:1:1, endln:158:10 + \_module_inst: work@FSM1 (work@FSM1), file:${SURELOG_DIR}/tests/FSMBsp13/fsm1.v, line:1:1, endln:158:10 |vpiRhs: \_constant: , line:9:27, endln:9:28 |vpiDecompile:6 @@ -7379,7 +7379,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:9:30, endln:9:41 |vpiParent: - \_module: work@FSM1 (work@FSM1), file:${SURELOG_DIR}/tests/FSMBsp13/fsm1.v, line:1:1, endln:158:10 + \_module_inst: work@FSM1 (work@FSM1), file:${SURELOG_DIR}/tests/FSMBsp13/fsm1.v, line:1:1, endln:158:10 |vpiRhs: \_constant: , line:9:40, endln:9:41 |vpiDecompile:7 @@ -7393,7 +7393,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:9:43, endln:9:54 |vpiParent: - \_module: work@FSM1 (work@FSM1), file:${SURELOG_DIR}/tests/FSMBsp13/fsm1.v, line:1:1, endln:158:10 + \_module_inst: work@FSM1 (work@FSM1), file:${SURELOG_DIR}/tests/FSMBsp13/fsm1.v, line:1:1, endln:158:10 |vpiRhs: \_constant: , line:9:53, endln:9:54 |vpiDecompile:8 @@ -7407,7 +7407,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:10:17, endln:10:28 |vpiParent: - \_module: work@FSM1 (work@FSM1), file:${SURELOG_DIR}/tests/FSMBsp13/fsm1.v, line:1:1, endln:158:10 + \_module_inst: work@FSM1 (work@FSM1), file:${SURELOG_DIR}/tests/FSMBsp13/fsm1.v, line:1:1, endln:158:10 |vpiRhs: \_constant: , line:10:27, endln:10:28 |vpiDecompile:9 @@ -7421,7 +7421,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:10:30, endln:10:42 |vpiParent: - \_module: work@FSM1 (work@FSM1), file:${SURELOG_DIR}/tests/FSMBsp13/fsm1.v, line:1:1, endln:158:10 + \_module_inst: work@FSM1 (work@FSM1), file:${SURELOG_DIR}/tests/FSMBsp13/fsm1.v, line:1:1, endln:158:10 |vpiRhs: \_constant: , line:10:40, endln:10:42 |vpiDecompile:10 @@ -7436,67 +7436,67 @@ design: (work@top) |vpiNet: \_logic_net: (work@FSM1.Read), line:5:5, endln:5:9 |vpiParent: - \_module: work@FSM1 (work@FSM1), file:${SURELOG_DIR}/tests/FSMBsp13/fsm1.v, line:1:1, endln:158:10 + \_module_inst: work@FSM1 (work@FSM1), file:${SURELOG_DIR}/tests/FSMBsp13/fsm1.v, line:1:1, endln:158:10 |vpiName:Read |vpiFullName:work@FSM1.Read |vpiNetType:48 |vpiNet: \_logic_net: (work@FSM1.Write), line:5:11, endln:5:16 |vpiParent: - \_module: work@FSM1 (work@FSM1), file:${SURELOG_DIR}/tests/FSMBsp13/fsm1.v, line:1:1, endln:158:10 + \_module_inst: work@FSM1 (work@FSM1), file:${SURELOG_DIR}/tests/FSMBsp13/fsm1.v, line:1:1, endln:158:10 |vpiName:Write |vpiFullName:work@FSM1.Write |vpiNetType:48 |vpiNet: \_logic_net: (work@FSM1.Wait), line:5:18, endln:5:22 |vpiParent: - \_module: work@FSM1 (work@FSM1), file:${SURELOG_DIR}/tests/FSMBsp13/fsm1.v, line:1:1, endln:158:10 + \_module_inst: work@FSM1 (work@FSM1), file:${SURELOG_DIR}/tests/FSMBsp13/fsm1.v, line:1:1, endln:158:10 |vpiName:Wait |vpiFullName:work@FSM1.Wait |vpiNetType:48 |vpiNet: \_logic_net: (work@FSM1.Delay), line:5:24, endln:5:29 |vpiParent: - \_module: work@FSM1 (work@FSM1), file:${SURELOG_DIR}/tests/FSMBsp13/fsm1.v, line:1:1, endln:158:10 + \_module_inst: work@FSM1 (work@FSM1), file:${SURELOG_DIR}/tests/FSMBsp13/fsm1.v, line:1:1, endln:158:10 |vpiName:Delay |vpiFullName:work@FSM1.Delay |vpiNetType:48 |vpiNet: \_logic_net: (work@FSM1.CurState), line:11:17, endln:11:25 |vpiParent: - \_module: work@FSM1 (work@FSM1), file:${SURELOG_DIR}/tests/FSMBsp13/fsm1.v, line:1:1, endln:158:10 + \_module_inst: work@FSM1 (work@FSM1), file:${SURELOG_DIR}/tests/FSMBsp13/fsm1.v, line:1:1, endln:158:10 |vpiName:CurState |vpiFullName:work@FSM1.CurState |vpiNetType:48 |vpiNet: \_logic_net: (work@FSM1.NextState), line:11:27, endln:11:36 |vpiParent: - \_module: work@FSM1 (work@FSM1), file:${SURELOG_DIR}/tests/FSMBsp13/fsm1.v, line:1:1, endln:158:10 + \_module_inst: work@FSM1 (work@FSM1), file:${SURELOG_DIR}/tests/FSMBsp13/fsm1.v, line:1:1, endln:158:10 |vpiName:NextState |vpiFullName:work@FSM1.NextState |vpiNetType:48 |vpiNet: \_logic_net: (work@FSM1.Clk), line:1:14, endln:1:17 |vpiParent: - \_module: work@FSM1 (work@FSM1), file:${SURELOG_DIR}/tests/FSMBsp13/fsm1.v, line:1:1, endln:158:10 + \_module_inst: work@FSM1 (work@FSM1), file:${SURELOG_DIR}/tests/FSMBsp13/fsm1.v, line:1:1, endln:158:10 |vpiName:Clk |vpiFullName:work@FSM1.Clk |vpiNet: \_logic_net: (work@FSM1.Reset), line:1:19, endln:1:24 |vpiParent: - \_module: work@FSM1 (work@FSM1), file:${SURELOG_DIR}/tests/FSMBsp13/fsm1.v, line:1:1, endln:158:10 + \_module_inst: work@FSM1 (work@FSM1), file:${SURELOG_DIR}/tests/FSMBsp13/fsm1.v, line:1:1, endln:158:10 |vpiName:Reset |vpiFullName:work@FSM1.Reset |vpiNet: \_logic_net: (work@FSM1.SlowRam), line:1:26, endln:1:33 |vpiParent: - \_module: work@FSM1 (work@FSM1), file:${SURELOG_DIR}/tests/FSMBsp13/fsm1.v, line:1:1, endln:158:10 + \_module_inst: work@FSM1 (work@FSM1), file:${SURELOG_DIR}/tests/FSMBsp13/fsm1.v, line:1:1, endln:158:10 |vpiName:SlowRam |vpiFullName:work@FSM1.SlowRam |vpiPort: \_port: (Clk), line:1:14, endln:1:17 |vpiParent: - \_module: work@FSM1 (work@FSM1), file:${SURELOG_DIR}/tests/FSMBsp13/fsm1.v, line:1:1, endln:158:10 + \_module_inst: work@FSM1 (work@FSM1), file:${SURELOG_DIR}/tests/FSMBsp13/fsm1.v, line:1:1, endln:158:10 |vpiName:Clk |vpiDirection:1 |vpiLowConn: @@ -7508,7 +7508,7 @@ design: (work@top) |vpiPort: \_port: (Reset), line:1:19, endln:1:24 |vpiParent: - \_module: work@FSM1 (work@FSM1), file:${SURELOG_DIR}/tests/FSMBsp13/fsm1.v, line:1:1, endln:158:10 + \_module_inst: work@FSM1 (work@FSM1), file:${SURELOG_DIR}/tests/FSMBsp13/fsm1.v, line:1:1, endln:158:10 |vpiName:Reset |vpiDirection:1 |vpiLowConn: @@ -7520,7 +7520,7 @@ design: (work@top) |vpiPort: \_port: (SlowRam), line:1:26, endln:1:33 |vpiParent: - \_module: work@FSM1 (work@FSM1), file:${SURELOG_DIR}/tests/FSMBsp13/fsm1.v, line:1:1, endln:158:10 + \_module_inst: work@FSM1 (work@FSM1), file:${SURELOG_DIR}/tests/FSMBsp13/fsm1.v, line:1:1, endln:158:10 |vpiName:SlowRam |vpiDirection:1 |vpiLowConn: @@ -7532,7 +7532,7 @@ design: (work@top) |vpiPort: \_port: (Read), line:1:35, endln:1:39 |vpiParent: - \_module: work@FSM1 (work@FSM1), file:${SURELOG_DIR}/tests/FSMBsp13/fsm1.v, line:1:1, endln:158:10 + \_module_inst: work@FSM1 (work@FSM1), file:${SURELOG_DIR}/tests/FSMBsp13/fsm1.v, line:1:1, endln:158:10 |vpiName:Read |vpiDirection:2 |vpiLowConn: @@ -7544,7 +7544,7 @@ design: (work@top) |vpiPort: \_port: (Write), line:1:41, endln:1:46 |vpiParent: - \_module: work@FSM1 (work@FSM1), file:${SURELOG_DIR}/tests/FSMBsp13/fsm1.v, line:1:1, endln:158:10 + \_module_inst: work@FSM1 (work@FSM1), file:${SURELOG_DIR}/tests/FSMBsp13/fsm1.v, line:1:1, endln:158:10 |vpiName:Write |vpiDirection:2 |vpiLowConn: @@ -7556,7 +7556,7 @@ design: (work@top) |vpiProcess: \_always: , line:14:1, endln:19:4 |vpiParent: - \_module: work@FSM1 (work@FSM1), file:${SURELOG_DIR}/tests/FSMBsp13/fsm1.v, line:1:1, endln:158:10 + \_module_inst: work@FSM1 (work@FSM1), file:${SURELOG_DIR}/tests/FSMBsp13/fsm1.v, line:1:1, endln:158:10 |vpiStmt: \_event_control: , line:14:8, endln:14:22 |vpiParent: @@ -7638,7 +7638,7 @@ design: (work@top) |vpiProcess: \_initial: , line:21:1, endln:26:4 |vpiParent: - \_module: work@FSM1 (work@FSM1), file:${SURELOG_DIR}/tests/FSMBsp13/fsm1.v, line:1:1, endln:158:10 + \_module_inst: work@FSM1 (work@FSM1), file:${SURELOG_DIR}/tests/FSMBsp13/fsm1.v, line:1:1, endln:158:10 |vpiStmt: \_begin: (work@FSM1), line:21:9, endln:26:4 |vpiParent: @@ -7735,7 +7735,7 @@ design: (work@top) |vpiProcess: \_always: , line:28:1, endln:156:4 |vpiParent: - \_module: work@FSM1 (work@FSM1), file:${SURELOG_DIR}/tests/FSMBsp13/fsm1.v, line:1:1, endln:158:10 + \_module_inst: work@FSM1 (work@FSM1), file:${SURELOG_DIR}/tests/FSMBsp13/fsm1.v, line:1:1, endln:158:10 |vpiStmt: \_event_control: , line:28:8, endln:28:19 |vpiParent: @@ -10596,14 +10596,14 @@ design: (work@top) \_logic_net: (work@top.F1.NextState), line:11:27, endln:11:36 |vpiAlwaysType:1 |uhdmallModules: -\_module: work@FSM2 (work@FSM2), file:${SURELOG_DIR}/tests/FSMBsp13/fsm2.v, line:1:1, endln:135:10 +\_module_inst: work@FSM2 (work@FSM2), file:${SURELOG_DIR}/tests/FSMBsp13/fsm2.v, line:1:1, endln:135:10 |vpiParent: \_design: (work@top) |vpiFullName:work@FSM2 |vpiParameter: \_parameter: (work@FSM2.ST0), line:6:17, endln:6:20 |vpiParent: - \_module: work@FSM2 (work@FSM2), file:${SURELOG_DIR}/tests/FSMBsp13/fsm2.v, line:1:1, endln:135:10 + \_module_inst: work@FSM2 (work@FSM2), file:${SURELOG_DIR}/tests/FSMBsp13/fsm2.v, line:1:1, endln:135:10 |UINT:0 |vpiTypespec: \_int_typespec: , line:6:11, endln:6:16 @@ -10632,7 +10632,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@FSM2.ST1), line:6:25, endln:6:28 |vpiParent: - \_module: work@FSM2 (work@FSM2), file:${SURELOG_DIR}/tests/FSMBsp13/fsm2.v, line:1:1, endln:135:10 + \_module_inst: work@FSM2 (work@FSM2), file:${SURELOG_DIR}/tests/FSMBsp13/fsm2.v, line:1:1, endln:135:10 |UINT:1 |vpiTypespec: \_int_typespec: , line:6:11, endln:6:16 @@ -10661,7 +10661,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@FSM2.ST2), line:6:32, endln:6:35 |vpiParent: - \_module: work@FSM2 (work@FSM2), file:${SURELOG_DIR}/tests/FSMBsp13/fsm2.v, line:1:1, endln:135:10 + \_module_inst: work@FSM2 (work@FSM2), file:${SURELOG_DIR}/tests/FSMBsp13/fsm2.v, line:1:1, endln:135:10 |UINT:2 |vpiTypespec: \_int_typespec: , line:6:11, endln:6:16 @@ -10690,7 +10690,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@FSM2.ST3), line:6:39, endln:6:42 |vpiParent: - \_module: work@FSM2 (work@FSM2), file:${SURELOG_DIR}/tests/FSMBsp13/fsm2.v, line:1:1, endln:135:10 + \_module_inst: work@FSM2 (work@FSM2), file:${SURELOG_DIR}/tests/FSMBsp13/fsm2.v, line:1:1, endln:135:10 |UINT:3 |vpiTypespec: \_int_typespec: , line:6:11, endln:6:16 @@ -10719,7 +10719,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@FSM2.ST4), line:6:46, endln:6:49 |vpiParent: - \_module: work@FSM2 (work@FSM2), file:${SURELOG_DIR}/tests/FSMBsp13/fsm2.v, line:1:1, endln:135:10 + \_module_inst: work@FSM2 (work@FSM2), file:${SURELOG_DIR}/tests/FSMBsp13/fsm2.v, line:1:1, endln:135:10 |UINT:4 |vpiTypespec: \_int_typespec: , line:6:11, endln:6:16 @@ -10748,7 +10748,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@FSM2.ST5), line:6:53, endln:6:56 |vpiParent: - \_module: work@FSM2 (work@FSM2), file:${SURELOG_DIR}/tests/FSMBsp13/fsm2.v, line:1:1, endln:135:10 + \_module_inst: work@FSM2 (work@FSM2), file:${SURELOG_DIR}/tests/FSMBsp13/fsm2.v, line:1:1, endln:135:10 |UINT:5 |vpiTypespec: \_int_typespec: , line:6:11, endln:6:16 @@ -10777,7 +10777,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@FSM2.ST6), line:6:60, endln:6:63 |vpiParent: - \_module: work@FSM2 (work@FSM2), file:${SURELOG_DIR}/tests/FSMBsp13/fsm2.v, line:1:1, endln:135:10 + \_module_inst: work@FSM2 (work@FSM2), file:${SURELOG_DIR}/tests/FSMBsp13/fsm2.v, line:1:1, endln:135:10 |UINT:6 |vpiTypespec: \_int_typespec: , line:6:11, endln:6:16 @@ -10806,7 +10806,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@FSM2.ST7), line:6:66, endln:6:69 |vpiParent: - \_module: work@FSM2 (work@FSM2), file:${SURELOG_DIR}/tests/FSMBsp13/fsm2.v, line:1:1, endln:135:10 + \_module_inst: work@FSM2 (work@FSM2), file:${SURELOG_DIR}/tests/FSMBsp13/fsm2.v, line:1:1, endln:135:10 |UINT:7 |vpiTypespec: \_int_typespec: , line:6:11, endln:6:16 @@ -10835,7 +10835,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@FSM2.ST8), line:7:17, endln:7:20 |vpiParent: - \_module: work@FSM2 (work@FSM2), file:${SURELOG_DIR}/tests/FSMBsp13/fsm2.v, line:1:1, endln:135:10 + \_module_inst: work@FSM2 (work@FSM2), file:${SURELOG_DIR}/tests/FSMBsp13/fsm2.v, line:1:1, endln:135:10 |UINT:8 |vpiTypespec: \_int_typespec: , line:6:11, endln:6:16 @@ -10864,7 +10864,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@FSM2.ST9), line:7:24, endln:7:27 |vpiParent: - \_module: work@FSM2 (work@FSM2), file:${SURELOG_DIR}/tests/FSMBsp13/fsm2.v, line:1:1, endln:135:10 + \_module_inst: work@FSM2 (work@FSM2), file:${SURELOG_DIR}/tests/FSMBsp13/fsm2.v, line:1:1, endln:135:10 |UINT:9 |vpiTypespec: \_int_typespec: , line:6:11, endln:6:16 @@ -10893,7 +10893,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@FSM2.ST10), line:7:31, endln:7:35 |vpiParent: - \_module: work@FSM2 (work@FSM2), file:${SURELOG_DIR}/tests/FSMBsp13/fsm2.v, line:1:1, endln:135:10 + \_module_inst: work@FSM2 (work@FSM2), file:${SURELOG_DIR}/tests/FSMBsp13/fsm2.v, line:1:1, endln:135:10 |UINT:10 |vpiTypespec: \_int_typespec: , line:6:11, endln:6:16 @@ -10922,7 +10922,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:6:17, endln:6:23 |vpiParent: - \_module: work@FSM2 (work@FSM2), file:${SURELOG_DIR}/tests/FSMBsp13/fsm2.v, line:1:1, endln:135:10 + \_module_inst: work@FSM2 (work@FSM2), file:${SURELOG_DIR}/tests/FSMBsp13/fsm2.v, line:1:1, endln:135:10 |vpiRhs: \_constant: , line:6:22, endln:6:23 |vpiDecompile:0 @@ -10936,7 +10936,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:6:25, endln:6:30 |vpiParent: - \_module: work@FSM2 (work@FSM2), file:${SURELOG_DIR}/tests/FSMBsp13/fsm2.v, line:1:1, endln:135:10 + \_module_inst: work@FSM2 (work@FSM2), file:${SURELOG_DIR}/tests/FSMBsp13/fsm2.v, line:1:1, endln:135:10 |vpiRhs: \_constant: , line:6:29, endln:6:30 |vpiDecompile:1 @@ -10950,7 +10950,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:6:32, endln:6:37 |vpiParent: - \_module: work@FSM2 (work@FSM2), file:${SURELOG_DIR}/tests/FSMBsp13/fsm2.v, line:1:1, endln:135:10 + \_module_inst: work@FSM2 (work@FSM2), file:${SURELOG_DIR}/tests/FSMBsp13/fsm2.v, line:1:1, endln:135:10 |vpiRhs: \_constant: , line:6:36, endln:6:37 |vpiDecompile:2 @@ -10964,7 +10964,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:6:39, endln:6:44 |vpiParent: - \_module: work@FSM2 (work@FSM2), file:${SURELOG_DIR}/tests/FSMBsp13/fsm2.v, line:1:1, endln:135:10 + \_module_inst: work@FSM2 (work@FSM2), file:${SURELOG_DIR}/tests/FSMBsp13/fsm2.v, line:1:1, endln:135:10 |vpiRhs: \_constant: , line:6:43, endln:6:44 |vpiDecompile:3 @@ -10978,7 +10978,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:6:46, endln:6:51 |vpiParent: - \_module: work@FSM2 (work@FSM2), file:${SURELOG_DIR}/tests/FSMBsp13/fsm2.v, line:1:1, endln:135:10 + \_module_inst: work@FSM2 (work@FSM2), file:${SURELOG_DIR}/tests/FSMBsp13/fsm2.v, line:1:1, endln:135:10 |vpiRhs: \_constant: , line:6:50, endln:6:51 |vpiDecompile:4 @@ -10992,7 +10992,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:6:53, endln:6:58 |vpiParent: - \_module: work@FSM2 (work@FSM2), file:${SURELOG_DIR}/tests/FSMBsp13/fsm2.v, line:1:1, endln:135:10 + \_module_inst: work@FSM2 (work@FSM2), file:${SURELOG_DIR}/tests/FSMBsp13/fsm2.v, line:1:1, endln:135:10 |vpiRhs: \_constant: , line:6:57, endln:6:58 |vpiDecompile:5 @@ -11006,7 +11006,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:6:60, endln:6:65 |vpiParent: - \_module: work@FSM2 (work@FSM2), file:${SURELOG_DIR}/tests/FSMBsp13/fsm2.v, line:1:1, endln:135:10 + \_module_inst: work@FSM2 (work@FSM2), file:${SURELOG_DIR}/tests/FSMBsp13/fsm2.v, line:1:1, endln:135:10 |vpiRhs: \_constant: , line:6:64, endln:6:65 |vpiDecompile:6 @@ -11020,7 +11020,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:6:66, endln:6:71 |vpiParent: - \_module: work@FSM2 (work@FSM2), file:${SURELOG_DIR}/tests/FSMBsp13/fsm2.v, line:1:1, endln:135:10 + \_module_inst: work@FSM2 (work@FSM2), file:${SURELOG_DIR}/tests/FSMBsp13/fsm2.v, line:1:1, endln:135:10 |vpiRhs: \_constant: , line:6:70, endln:6:71 |vpiDecompile:7 @@ -11034,7 +11034,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:7:17, endln:7:22 |vpiParent: - \_module: work@FSM2 (work@FSM2), file:${SURELOG_DIR}/tests/FSMBsp13/fsm2.v, line:1:1, endln:135:10 + \_module_inst: work@FSM2 (work@FSM2), file:${SURELOG_DIR}/tests/FSMBsp13/fsm2.v, line:1:1, endln:135:10 |vpiRhs: \_constant: , line:7:21, endln:7:22 |vpiDecompile:8 @@ -11048,7 +11048,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:7:24, endln:7:29 |vpiParent: - \_module: work@FSM2 (work@FSM2), file:${SURELOG_DIR}/tests/FSMBsp13/fsm2.v, line:1:1, endln:135:10 + \_module_inst: work@FSM2 (work@FSM2), file:${SURELOG_DIR}/tests/FSMBsp13/fsm2.v, line:1:1, endln:135:10 |vpiRhs: \_constant: , line:7:28, endln:7:29 |vpiDecompile:9 @@ -11062,7 +11062,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:7:31, endln:7:38 |vpiParent: - \_module: work@FSM2 (work@FSM2), file:${SURELOG_DIR}/tests/FSMBsp13/fsm2.v, line:1:1, endln:135:10 + \_module_inst: work@FSM2 (work@FSM2), file:${SURELOG_DIR}/tests/FSMBsp13/fsm2.v, line:1:1, endln:135:10 |vpiRhs: \_constant: , line:7:36, endln:7:38 |vpiDecompile:10 @@ -11077,12 +11077,12 @@ design: (work@top) |vpiTaskFunc: \_task: (work@FSM2.SwitchCtrl), line:23:1, endln:33:8 |vpiParent: - \_module: work@FSM2 (work@FSM2), file:${SURELOG_DIR}/tests/FSMBsp13/fsm2.v, line:1:1, endln:135:10 + \_module_inst: work@FSM2 (work@FSM2), file:${SURELOG_DIR}/tests/FSMBsp13/fsm2.v, line:1:1, endln:135:10 |vpiName:SwitchCtrl |vpiFullName:work@FSM2.SwitchCtrl |vpiVisibility:1 |vpiParent: - \_module: work@FSM2 (work@FSM2), file:${SURELOG_DIR}/tests/FSMBsp13/fsm2.v, line:1:1, endln:135:10 + \_module_inst: work@FSM2 (work@FSM2), file:${SURELOG_DIR}/tests/FSMBsp13/fsm2.v, line:1:1, endln:135:10 |vpiStmt: \_begin: (work@FSM2.SwitchCtrl), line:24:1, endln:32:4 |vpiParent: @@ -11278,99 +11278,99 @@ design: (work@top) |vpiActual: \_logic_net: (work@top.F2.Ctrl7), line:10:41, endln:10:46 |vpiInstance: - \_module: work@FSM2 (work@FSM2), file:${SURELOG_DIR}/tests/FSMBsp13/fsm2.v, line:1:1, endln:135:10 + \_module_inst: work@FSM2 (work@FSM2), file:${SURELOG_DIR}/tests/FSMBsp13/fsm2.v, line:1:1, endln:135:10 |vpiNet: \_logic_net: (work@FSM2.y), line:4:11, endln:4:12 |vpiParent: - \_module: work@FSM2 (work@FSM2), file:${SURELOG_DIR}/tests/FSMBsp13/fsm2.v, line:1:1, endln:135:10 + \_module_inst: work@FSM2 (work@FSM2), file:${SURELOG_DIR}/tests/FSMBsp13/fsm2.v, line:1:1, endln:135:10 |vpiName:y |vpiFullName:work@FSM2.y |vpiNetType:48 |vpiNet: \_logic_net: (work@FSM2.CurrentState), line:8:11, endln:8:23 |vpiParent: - \_module: work@FSM2 (work@FSM2), file:${SURELOG_DIR}/tests/FSMBsp13/fsm2.v, line:1:1, endln:135:10 + \_module_inst: work@FSM2 (work@FSM2), file:${SURELOG_DIR}/tests/FSMBsp13/fsm2.v, line:1:1, endln:135:10 |vpiName:CurrentState |vpiFullName:work@FSM2.CurrentState |vpiNetType:48 |vpiNet: \_logic_net: (work@FSM2.NextState), line:8:25, endln:8:34 |vpiParent: - \_module: work@FSM2 (work@FSM2), file:${SURELOG_DIR}/tests/FSMBsp13/fsm2.v, line:1:1, endln:135:10 + \_module_inst: work@FSM2 (work@FSM2), file:${SURELOG_DIR}/tests/FSMBsp13/fsm2.v, line:1:1, endln:135:10 |vpiName:NextState |vpiFullName:work@FSM2.NextState |vpiNetType:48 |vpiNet: \_logic_net: (work@FSM2.Ctrl1), line:10:5, endln:10:10 |vpiParent: - \_module: work@FSM2 (work@FSM2), file:${SURELOG_DIR}/tests/FSMBsp13/fsm2.v, line:1:1, endln:135:10 + \_module_inst: work@FSM2 (work@FSM2), file:${SURELOG_DIR}/tests/FSMBsp13/fsm2.v, line:1:1, endln:135:10 |vpiName:Ctrl1 |vpiFullName:work@FSM2.Ctrl1 |vpiNetType:48 |vpiNet: \_logic_net: (work@FSM2.Ctrl2), line:10:11, endln:10:16 |vpiParent: - \_module: work@FSM2 (work@FSM2), file:${SURELOG_DIR}/tests/FSMBsp13/fsm2.v, line:1:1, endln:135:10 + \_module_inst: work@FSM2 (work@FSM2), file:${SURELOG_DIR}/tests/FSMBsp13/fsm2.v, line:1:1, endln:135:10 |vpiName:Ctrl2 |vpiFullName:work@FSM2.Ctrl2 |vpiNetType:48 |vpiNet: \_logic_net: (work@FSM2.Ctrl3), line:10:17, endln:10:22 |vpiParent: - \_module: work@FSM2 (work@FSM2), file:${SURELOG_DIR}/tests/FSMBsp13/fsm2.v, line:1:1, endln:135:10 + \_module_inst: work@FSM2 (work@FSM2), file:${SURELOG_DIR}/tests/FSMBsp13/fsm2.v, line:1:1, endln:135:10 |vpiName:Ctrl3 |vpiFullName:work@FSM2.Ctrl3 |vpiNetType:48 |vpiNet: \_logic_net: (work@FSM2.Ctrl4), line:10:23, endln:10:28 |vpiParent: - \_module: work@FSM2 (work@FSM2), file:${SURELOG_DIR}/tests/FSMBsp13/fsm2.v, line:1:1, endln:135:10 + \_module_inst: work@FSM2 (work@FSM2), file:${SURELOG_DIR}/tests/FSMBsp13/fsm2.v, line:1:1, endln:135:10 |vpiName:Ctrl4 |vpiFullName:work@FSM2.Ctrl4 |vpiNetType:48 |vpiNet: \_logic_net: (work@FSM2.Ctrl5), line:10:29, endln:10:34 |vpiParent: - \_module: work@FSM2 (work@FSM2), file:${SURELOG_DIR}/tests/FSMBsp13/fsm2.v, line:1:1, endln:135:10 + \_module_inst: work@FSM2 (work@FSM2), file:${SURELOG_DIR}/tests/FSMBsp13/fsm2.v, line:1:1, endln:135:10 |vpiName:Ctrl5 |vpiFullName:work@FSM2.Ctrl5 |vpiNetType:48 |vpiNet: \_logic_net: (work@FSM2.Ctrl6), line:10:35, endln:10:40 |vpiParent: - \_module: work@FSM2 (work@FSM2), file:${SURELOG_DIR}/tests/FSMBsp13/fsm2.v, line:1:1, endln:135:10 + \_module_inst: work@FSM2 (work@FSM2), file:${SURELOG_DIR}/tests/FSMBsp13/fsm2.v, line:1:1, endln:135:10 |vpiName:Ctrl6 |vpiFullName:work@FSM2.Ctrl6 |vpiNetType:48 |vpiNet: \_logic_net: (work@FSM2.Ctrl7), line:10:41, endln:10:46 |vpiParent: - \_module: work@FSM2 (work@FSM2), file:${SURELOG_DIR}/tests/FSMBsp13/fsm2.v, line:1:1, endln:135:10 + \_module_inst: work@FSM2 (work@FSM2), file:${SURELOG_DIR}/tests/FSMBsp13/fsm2.v, line:1:1, endln:135:10 |vpiName:Ctrl7 |vpiFullName:work@FSM2.Ctrl7 |vpiNetType:48 |vpiNet: \_logic_net: (work@FSM2.clock), line:1:13, endln:1:18 |vpiParent: - \_module: work@FSM2 (work@FSM2), file:${SURELOG_DIR}/tests/FSMBsp13/fsm2.v, line:1:1, endln:135:10 + \_module_inst: work@FSM2 (work@FSM2), file:${SURELOG_DIR}/tests/FSMBsp13/fsm2.v, line:1:1, endln:135:10 |vpiName:clock |vpiFullName:work@FSM2.clock |vpiNet: \_logic_net: (work@FSM2.reset), line:1:20, endln:1:25 |vpiParent: - \_module: work@FSM2 (work@FSM2), file:${SURELOG_DIR}/tests/FSMBsp13/fsm2.v, line:1:1, endln:135:10 + \_module_inst: work@FSM2 (work@FSM2), file:${SURELOG_DIR}/tests/FSMBsp13/fsm2.v, line:1:1, endln:135:10 |vpiName:reset |vpiFullName:work@FSM2.reset |vpiNet: \_logic_net: (work@FSM2.control), line:1:27, endln:1:34 |vpiParent: - \_module: work@FSM2 (work@FSM2), file:${SURELOG_DIR}/tests/FSMBsp13/fsm2.v, line:1:1, endln:135:10 + \_module_inst: work@FSM2 (work@FSM2), file:${SURELOG_DIR}/tests/FSMBsp13/fsm2.v, line:1:1, endln:135:10 |vpiName:control |vpiFullName:work@FSM2.control |vpiPort: \_port: (clock), line:1:13, endln:1:18 |vpiParent: - \_module: work@FSM2 (work@FSM2), file:${SURELOG_DIR}/tests/FSMBsp13/fsm2.v, line:1:1, endln:135:10 + \_module_inst: work@FSM2 (work@FSM2), file:${SURELOG_DIR}/tests/FSMBsp13/fsm2.v, line:1:1, endln:135:10 |vpiName:clock |vpiDirection:1 |vpiLowConn: @@ -11382,7 +11382,7 @@ design: (work@top) |vpiPort: \_port: (reset), line:1:20, endln:1:25 |vpiParent: - \_module: work@FSM2 (work@FSM2), file:${SURELOG_DIR}/tests/FSMBsp13/fsm2.v, line:1:1, endln:135:10 + \_module_inst: work@FSM2 (work@FSM2), file:${SURELOG_DIR}/tests/FSMBsp13/fsm2.v, line:1:1, endln:135:10 |vpiName:reset |vpiDirection:1 |vpiLowConn: @@ -11394,7 +11394,7 @@ design: (work@top) |vpiPort: \_port: (control), line:1:27, endln:1:34 |vpiParent: - \_module: work@FSM2 (work@FSM2), file:${SURELOG_DIR}/tests/FSMBsp13/fsm2.v, line:1:1, endln:135:10 + \_module_inst: work@FSM2 (work@FSM2), file:${SURELOG_DIR}/tests/FSMBsp13/fsm2.v, line:1:1, endln:135:10 |vpiName:control |vpiDirection:1 |vpiLowConn: @@ -11406,7 +11406,7 @@ design: (work@top) |vpiPort: \_port: (y), line:1:36, endln:1:37 |vpiParent: - \_module: work@FSM2 (work@FSM2), file:${SURELOG_DIR}/tests/FSMBsp13/fsm2.v, line:1:1, endln:135:10 + \_module_inst: work@FSM2 (work@FSM2), file:${SURELOG_DIR}/tests/FSMBsp13/fsm2.v, line:1:1, endln:135:10 |vpiName:y |vpiDirection:2 |vpiLowConn: @@ -11436,7 +11436,7 @@ design: (work@top) |vpiProcess: \_initial: , line:12:1, endln:20:4 |vpiParent: - \_module: work@FSM2 (work@FSM2), file:${SURELOG_DIR}/tests/FSMBsp13/fsm2.v, line:1:1, endln:135:10 + \_module_inst: work@FSM2 (work@FSM2), file:${SURELOG_DIR}/tests/FSMBsp13/fsm2.v, line:1:1, endln:135:10 |vpiStmt: \_begin: (work@FSM2), line:12:9, endln:20:4 |vpiParent: @@ -11599,7 +11599,7 @@ design: (work@top) |vpiProcess: \_always: , line:36:1, endln:113:4 |vpiParent: - \_module: work@FSM2 (work@FSM2), file:${SURELOG_DIR}/tests/FSMBsp13/fsm2.v, line:1:1, endln:135:10 + \_module_inst: work@FSM2 (work@FSM2), file:${SURELOG_DIR}/tests/FSMBsp13/fsm2.v, line:1:1, endln:135:10 |vpiStmt: \_event_control: , line:36:8, endln:36:34 |vpiParent: @@ -12756,7 +12756,7 @@ design: (work@top) |vpiProcess: \_always: , line:116:1, endln:121:4 |vpiParent: - \_module: work@FSM2 (work@FSM2), file:${SURELOG_DIR}/tests/FSMBsp13/fsm2.v, line:1:1, endln:135:10 + \_module_inst: work@FSM2 (work@FSM2), file:${SURELOG_DIR}/tests/FSMBsp13/fsm2.v, line:1:1, endln:135:10 |vpiStmt: \_event_control: , line:116:8, endln:116:41 |vpiParent: @@ -12852,7 +12852,7 @@ design: (work@top) |vpiProcess: \_always: , line:124:1, endln:132:4 |vpiParent: - \_module: work@FSM2 (work@FSM2), file:${SURELOG_DIR}/tests/FSMBsp13/fsm2.v, line:1:1, endln:135:10 + \_module_inst: work@FSM2 (work@FSM2), file:${SURELOG_DIR}/tests/FSMBsp13/fsm2.v, line:1:1, endln:135:10 |vpiStmt: \_event_control: , line:124:8, endln:124:23 |vpiParent: @@ -13048,14 +13048,14 @@ design: (work@top) \_logic_net: (work@top.F2.y), line:4:11, endln:4:12 |vpiAlwaysType:1 |uhdmallModules: -\_module: work@FSM3 (work@FSM3), file:${SURELOG_DIR}/tests/FSMBsp13/fsm3.v, line:1:1, endln:64:10 +\_module_inst: work@FSM3 (work@FSM3), file:${SURELOG_DIR}/tests/FSMBsp13/fsm3.v, line:1:1, endln:64:10 |vpiParent: \_design: (work@top) |vpiFullName:work@FSM3 |vpiParameter: \_parameter: (work@FSM3.Stop), line:8:11, endln:8:15 |vpiParent: - \_module: work@FSM3 (work@FSM3), file:${SURELOG_DIR}/tests/FSMBsp13/fsm3.v, line:1:1, endln:64:10 + \_module_inst: work@FSM3 (work@FSM3), file:${SURELOG_DIR}/tests/FSMBsp13/fsm3.v, line:1:1, endln:64:10 |BIN:0000 |vpiTypespec: \_int_typespec: @@ -13072,7 +13072,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@FSM3.Move), line:9:11, endln:9:15 |vpiParent: - \_module: work@FSM3 (work@FSM3), file:${SURELOG_DIR}/tests/FSMBsp13/fsm3.v, line:1:1, endln:64:10 + \_module_inst: work@FSM3 (work@FSM3), file:${SURELOG_DIR}/tests/FSMBsp13/fsm3.v, line:1:1, endln:64:10 |BIN:0001 |vpiTypespec: \_int_typespec: @@ -13089,7 +13089,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@FSM3.Turn), line:10:11, endln:10:15 |vpiParent: - \_module: work@FSM3 (work@FSM3), file:${SURELOG_DIR}/tests/FSMBsp13/fsm3.v, line:1:1, endln:64:10 + \_module_inst: work@FSM3 (work@FSM3), file:${SURELOG_DIR}/tests/FSMBsp13/fsm3.v, line:1:1, endln:64:10 |BIN:0010 |vpiTypespec: \_int_typespec: @@ -13106,7 +13106,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@FSM3.Slow), line:11:11, endln:11:15 |vpiParent: - \_module: work@FSM3 (work@FSM3), file:${SURELOG_DIR}/tests/FSMBsp13/fsm3.v, line:1:1, endln:64:10 + \_module_inst: work@FSM3 (work@FSM3), file:${SURELOG_DIR}/tests/FSMBsp13/fsm3.v, line:1:1, endln:64:10 |BIN:0011 |vpiTypespec: \_int_typespec: @@ -13123,7 +13123,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@FSM3.Medium), line:12:11, endln:12:17 |vpiParent: - \_module: work@FSM3 (work@FSM3), file:${SURELOG_DIR}/tests/FSMBsp13/fsm3.v, line:1:1, endln:64:10 + \_module_inst: work@FSM3 (work@FSM3), file:${SURELOG_DIR}/tests/FSMBsp13/fsm3.v, line:1:1, endln:64:10 |BIN:0100 |vpiTypespec: \_int_typespec: @@ -13140,7 +13140,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@FSM3.Fast), line:13:11, endln:13:15 |vpiParent: - \_module: work@FSM3 (work@FSM3), file:${SURELOG_DIR}/tests/FSMBsp13/fsm3.v, line:1:1, endln:64:10 + \_module_inst: work@FSM3 (work@FSM3), file:${SURELOG_DIR}/tests/FSMBsp13/fsm3.v, line:1:1, endln:64:10 |BIN:0101 |vpiTypespec: \_int_typespec: @@ -13157,7 +13157,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@FSM3.Faster), line:14:11, endln:14:17 |vpiParent: - \_module: work@FSM3 (work@FSM3), file:${SURELOG_DIR}/tests/FSMBsp13/fsm3.v, line:1:1, endln:64:10 + \_module_inst: work@FSM3 (work@FSM3), file:${SURELOG_DIR}/tests/FSMBsp13/fsm3.v, line:1:1, endln:64:10 |BIN:0110 |vpiTypespec: \_int_typespec: @@ -13174,7 +13174,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:8:11, endln:8:28 |vpiParent: - \_module: work@FSM3 (work@FSM3), file:${SURELOG_DIR}/tests/FSMBsp13/fsm3.v, line:1:1, endln:64:10 + \_module_inst: work@FSM3 (work@FSM3), file:${SURELOG_DIR}/tests/FSMBsp13/fsm3.v, line:1:1, endln:64:10 |vpiRhs: \_constant: , line:8:21, endln:8:28 |vpiDecompile:4'b0000 @@ -13188,7 +13188,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:9:11, endln:9:28 |vpiParent: - \_module: work@FSM3 (work@FSM3), file:${SURELOG_DIR}/tests/FSMBsp13/fsm3.v, line:1:1, endln:64:10 + \_module_inst: work@FSM3 (work@FSM3), file:${SURELOG_DIR}/tests/FSMBsp13/fsm3.v, line:1:1, endln:64:10 |vpiRhs: \_constant: , line:9:21, endln:9:28 |vpiDecompile:4'b0001 @@ -13202,7 +13202,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:10:11, endln:10:28 |vpiParent: - \_module: work@FSM3 (work@FSM3), file:${SURELOG_DIR}/tests/FSMBsp13/fsm3.v, line:1:1, endln:64:10 + \_module_inst: work@FSM3 (work@FSM3), file:${SURELOG_DIR}/tests/FSMBsp13/fsm3.v, line:1:1, endln:64:10 |vpiRhs: \_constant: , line:10:21, endln:10:28 |vpiDecompile:4'b0010 @@ -13216,7 +13216,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:11:11, endln:11:28 |vpiParent: - \_module: work@FSM3 (work@FSM3), file:${SURELOG_DIR}/tests/FSMBsp13/fsm3.v, line:1:1, endln:64:10 + \_module_inst: work@FSM3 (work@FSM3), file:${SURELOG_DIR}/tests/FSMBsp13/fsm3.v, line:1:1, endln:64:10 |vpiRhs: \_constant: , line:11:21, endln:11:28 |vpiDecompile:4'b0011 @@ -13230,7 +13230,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:12:11, endln:12:28 |vpiParent: - \_module: work@FSM3 (work@FSM3), file:${SURELOG_DIR}/tests/FSMBsp13/fsm3.v, line:1:1, endln:64:10 + \_module_inst: work@FSM3 (work@FSM3), file:${SURELOG_DIR}/tests/FSMBsp13/fsm3.v, line:1:1, endln:64:10 |vpiRhs: \_constant: , line:12:21, endln:12:28 |vpiDecompile:4'b0100 @@ -13244,7 +13244,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:13:11, endln:13:28 |vpiParent: - \_module: work@FSM3 (work@FSM3), file:${SURELOG_DIR}/tests/FSMBsp13/fsm3.v, line:1:1, endln:64:10 + \_module_inst: work@FSM3 (work@FSM3), file:${SURELOG_DIR}/tests/FSMBsp13/fsm3.v, line:1:1, endln:64:10 |vpiRhs: \_constant: , line:13:21, endln:13:28 |vpiDecompile:4'b0101 @@ -13258,7 +13258,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:14:11, endln:14:28 |vpiParent: - \_module: work@FSM3 (work@FSM3), file:${SURELOG_DIR}/tests/FSMBsp13/fsm3.v, line:1:1, endln:64:10 + \_module_inst: work@FSM3 (work@FSM3), file:${SURELOG_DIR}/tests/FSMBsp13/fsm3.v, line:1:1, endln:64:10 |vpiRhs: \_constant: , line:14:21, endln:14:28 |vpiDecompile:4'b0110 @@ -13273,59 +13273,59 @@ design: (work@top) |vpiNet: \_logic_net: (work@FSM3.Speed), line:4:11, endln:4:16 |vpiParent: - \_module: work@FSM3 (work@FSM3), file:${SURELOG_DIR}/tests/FSMBsp13/fsm3.v, line:1:1, endln:64:10 + \_module_inst: work@FSM3 (work@FSM3), file:${SURELOG_DIR}/tests/FSMBsp13/fsm3.v, line:1:1, endln:64:10 |vpiName:Speed |vpiFullName:work@FSM3.Speed |vpiNetType:48 |vpiNet: \_logic_net: (work@FSM3.Ctrl1), line:6:5, endln:6:10 |vpiParent: - \_module: work@FSM3 (work@FSM3), file:${SURELOG_DIR}/tests/FSMBsp13/fsm3.v, line:1:1, endln:64:10 + \_module_inst: work@FSM3 (work@FSM3), file:${SURELOG_DIR}/tests/FSMBsp13/fsm3.v, line:1:1, endln:64:10 |vpiName:Ctrl1 |vpiFullName:work@FSM3.Ctrl1 |vpiNetType:48 |vpiNet: \_logic_net: (work@FSM3.Ctrl2), line:6:12, endln:6:17 |vpiParent: - \_module: work@FSM3 (work@FSM3), file:${SURELOG_DIR}/tests/FSMBsp13/fsm3.v, line:1:1, endln:64:10 + \_module_inst: work@FSM3 (work@FSM3), file:${SURELOG_DIR}/tests/FSMBsp13/fsm3.v, line:1:1, endln:64:10 |vpiName:Ctrl2 |vpiFullName:work@FSM3.Ctrl2 |vpiNetType:48 |vpiNet: \_logic_net: (work@FSM3.Ctrl3), line:6:19, endln:6:24 |vpiParent: - \_module: work@FSM3 (work@FSM3), file:${SURELOG_DIR}/tests/FSMBsp13/fsm3.v, line:1:1, endln:64:10 + \_module_inst: work@FSM3 (work@FSM3), file:${SURELOG_DIR}/tests/FSMBsp13/fsm3.v, line:1:1, endln:64:10 |vpiName:Ctrl3 |vpiFullName:work@FSM3.Ctrl3 |vpiNetType:48 |vpiNet: \_logic_net: (work@FSM3.clock), line:1:13, endln:1:18 |vpiParent: - \_module: work@FSM3 (work@FSM3), file:${SURELOG_DIR}/tests/FSMBsp13/fsm3.v, line:1:1, endln:64:10 + \_module_inst: work@FSM3 (work@FSM3), file:${SURELOG_DIR}/tests/FSMBsp13/fsm3.v, line:1:1, endln:64:10 |vpiName:clock |vpiFullName:work@FSM3.clock |vpiNet: \_logic_net: (work@FSM3.keys), line:1:20, endln:1:24 |vpiParent: - \_module: work@FSM3 (work@FSM3), file:${SURELOG_DIR}/tests/FSMBsp13/fsm3.v, line:1:1, endln:64:10 + \_module_inst: work@FSM3 (work@FSM3), file:${SURELOG_DIR}/tests/FSMBsp13/fsm3.v, line:1:1, endln:64:10 |vpiName:keys |vpiFullName:work@FSM3.keys |vpiNet: \_logic_net: (work@FSM3.brake), line:1:26, endln:1:31 |vpiParent: - \_module: work@FSM3 (work@FSM3), file:${SURELOG_DIR}/tests/FSMBsp13/fsm3.v, line:1:1, endln:64:10 + \_module_inst: work@FSM3 (work@FSM3), file:${SURELOG_DIR}/tests/FSMBsp13/fsm3.v, line:1:1, endln:64:10 |vpiName:brake |vpiFullName:work@FSM3.brake |vpiNet: \_logic_net: (work@FSM3.accelerate), line:1:33, endln:1:43 |vpiParent: - \_module: work@FSM3 (work@FSM3), file:${SURELOG_DIR}/tests/FSMBsp13/fsm3.v, line:1:1, endln:64:10 + \_module_inst: work@FSM3 (work@FSM3), file:${SURELOG_DIR}/tests/FSMBsp13/fsm3.v, line:1:1, endln:64:10 |vpiName:accelerate |vpiFullName:work@FSM3.accelerate |vpiPort: \_port: (clock), line:1:13, endln:1:18 |vpiParent: - \_module: work@FSM3 (work@FSM3), file:${SURELOG_DIR}/tests/FSMBsp13/fsm3.v, line:1:1, endln:64:10 + \_module_inst: work@FSM3 (work@FSM3), file:${SURELOG_DIR}/tests/FSMBsp13/fsm3.v, line:1:1, endln:64:10 |vpiName:clock |vpiDirection:1 |vpiLowConn: @@ -13337,7 +13337,7 @@ design: (work@top) |vpiPort: \_port: (keys), line:1:20, endln:1:24 |vpiParent: - \_module: work@FSM3 (work@FSM3), file:${SURELOG_DIR}/tests/FSMBsp13/fsm3.v, line:1:1, endln:64:10 + \_module_inst: work@FSM3 (work@FSM3), file:${SURELOG_DIR}/tests/FSMBsp13/fsm3.v, line:1:1, endln:64:10 |vpiName:keys |vpiDirection:1 |vpiLowConn: @@ -13349,7 +13349,7 @@ design: (work@top) |vpiPort: \_port: (brake), line:1:26, endln:1:31 |vpiParent: - \_module: work@FSM3 (work@FSM3), file:${SURELOG_DIR}/tests/FSMBsp13/fsm3.v, line:1:1, endln:64:10 + \_module_inst: work@FSM3 (work@FSM3), file:${SURELOG_DIR}/tests/FSMBsp13/fsm3.v, line:1:1, endln:64:10 |vpiName:brake |vpiDirection:1 |vpiLowConn: @@ -13361,7 +13361,7 @@ design: (work@top) |vpiPort: \_port: (accelerate), line:1:33, endln:1:43 |vpiParent: - \_module: work@FSM3 (work@FSM3), file:${SURELOG_DIR}/tests/FSMBsp13/fsm3.v, line:1:1, endln:64:10 + \_module_inst: work@FSM3 (work@FSM3), file:${SURELOG_DIR}/tests/FSMBsp13/fsm3.v, line:1:1, endln:64:10 |vpiName:accelerate |vpiDirection:1 |vpiLowConn: @@ -13373,7 +13373,7 @@ design: (work@top) |vpiPort: \_port: (Speed), line:1:45, endln:1:50 |vpiParent: - \_module: work@FSM3 (work@FSM3), file:${SURELOG_DIR}/tests/FSMBsp13/fsm3.v, line:1:1, endln:64:10 + \_module_inst: work@FSM3 (work@FSM3), file:${SURELOG_DIR}/tests/FSMBsp13/fsm3.v, line:1:1, endln:64:10 |vpiName:Speed |vpiDirection:2 |vpiLowConn: @@ -13403,7 +13403,7 @@ design: (work@top) |vpiProcess: \_initial: , line:16:1, endln:20:4 |vpiParent: - \_module: work@FSM3 (work@FSM3), file:${SURELOG_DIR}/tests/FSMBsp13/fsm3.v, line:1:1, endln:64:10 + \_module_inst: work@FSM3 (work@FSM3), file:${SURELOG_DIR}/tests/FSMBsp13/fsm3.v, line:1:1, endln:64:10 |vpiStmt: \_begin: (work@FSM3), line:16:9, endln:20:4 |vpiParent: @@ -13478,7 +13478,7 @@ design: (work@top) |vpiProcess: \_always: , line:22:1, endln:62:5 |vpiParent: - \_module: work@FSM3 (work@FSM3), file:${SURELOG_DIR}/tests/FSMBsp13/fsm3.v, line:1:1, endln:64:10 + \_module_inst: work@FSM3 (work@FSM3), file:${SURELOG_DIR}/tests/FSMBsp13/fsm3.v, line:1:1, endln:64:10 |vpiStmt: \_event_control: , line:22:8, endln:22:40 |vpiParent: @@ -14243,7 +14243,7 @@ design: (work@top) \_logic_net: (work@top.F3.Ctrl3), line:6:19, endln:6:24 |vpiAlwaysType:1 |uhdmallModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:1:1, endln:146:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:1:1, endln:146:10 |vpiParent: \_design: (work@top) |vpiFullName:work@top @@ -14251,196 +14251,196 @@ design: (work@top) |vpiNet: \_logic_net: (work@top.fsm1clk), line:3:5, endln:3:12 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:1:1, endln:146:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:1:1, endln:146:10 |vpiName:fsm1clk |vpiFullName:work@top.fsm1clk |vpiNetType:48 |vpiNet: \_logic_net: (work@top.fsm2clk), line:3:14, endln:3:21 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:1:1, endln:146:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:1:1, endln:146:10 |vpiName:fsm2clk |vpiFullName:work@top.fsm2clk |vpiNetType:48 |vpiNet: \_logic_net: (work@top.fsm3clk), line:3:23, endln:3:30 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:1:1, endln:146:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:1:1, endln:146:10 |vpiName:fsm3clk |vpiFullName:work@top.fsm3clk |vpiNetType:48 |vpiNet: \_logic_net: (work@top.fsm1rst), line:3:32, endln:3:39 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:1:1, endln:146:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:1:1, endln:146:10 |vpiName:fsm1rst |vpiFullName:work@top.fsm1rst |vpiNetType:48 |vpiNet: \_logic_net: (work@top.SlowRam), line:3:41, endln:3:48 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:1:1, endln:146:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:1:1, endln:146:10 |vpiName:SlowRam |vpiFullName:work@top.SlowRam |vpiNetType:48 |vpiNet: \_logic_net: (work@top.fsm2rst), line:3:50, endln:3:57 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:1:1, endln:146:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:1:1, endln:146:10 |vpiName:fsm2rst |vpiFullName:work@top.fsm2rst |vpiNetType:48 |vpiNet: \_logic_net: (work@top.ctrl), line:4:5, endln:4:9 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:1:1, endln:146:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:1:1, endln:146:10 |vpiName:ctrl |vpiFullName:work@top.ctrl |vpiNetType:48 |vpiNet: \_logic_net: (work@top.keys), line:5:5, endln:5:9 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:1:1, endln:146:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:1:1, endln:146:10 |vpiName:keys |vpiFullName:work@top.keys |vpiNetType:48 |vpiNet: \_logic_net: (work@top.brake), line:5:11, endln:5:16 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:1:1, endln:146:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:1:1, endln:146:10 |vpiName:brake |vpiFullName:work@top.brake |vpiNetType:48 |vpiNet: \_logic_net: (work@top.a), line:5:18, endln:5:19 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:1:1, endln:146:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:1:1, endln:146:10 |vpiName:a |vpiFullName:work@top.a |vpiNetType:48 |vpiNet: \_logic_net: (work@top.b), line:5:21, endln:5:22 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:1:1, endln:146:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:1:1, endln:146:10 |vpiName:b |vpiFullName:work@top.b |vpiNetType:48 |vpiNet: \_logic_net: (work@top.c), line:5:24, endln:5:25 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:1:1, endln:146:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:1:1, endln:146:10 |vpiName:c |vpiFullName:work@top.c |vpiNetType:48 |vpiNet: \_logic_net: (work@top.accelerate), line:5:27, endln:5:37 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:1:1, endln:146:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:1:1, endln:146:10 |vpiName:accelerate |vpiFullName:work@top.accelerate |vpiNetType:48 |vpiNet: \_logic_net: (work@top.m), line:5:39, endln:5:40 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:1:1, endln:146:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:1:1, endln:146:10 |vpiName:m |vpiFullName:work@top.m |vpiNetType:48 |vpiNet: \_logic_net: (work@top.n), line:5:42, endln:5:43 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:1:1, endln:146:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:1:1, endln:146:10 |vpiName:n |vpiFullName:work@top.n |vpiNetType:48 |vpiNet: \_logic_net: (work@top.o), line:5:45, endln:5:46 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:1:1, endln:146:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:1:1, endln:146:10 |vpiName:o |vpiFullName:work@top.o |vpiNetType:48 |vpiNet: \_logic_net: (work@top.p), line:5:48, endln:5:49 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:1:1, endln:146:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:1:1, endln:146:10 |vpiName:p |vpiFullName:work@top.p |vpiNetType:48 |vpiNet: \_logic_net: (work@top.q), line:5:51, endln:5:52 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:1:1, endln:146:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:1:1, endln:146:10 |vpiName:q |vpiFullName:work@top.q |vpiNetType:48 |vpiNet: \_logic_net: (work@top.r), line:5:54, endln:5:55 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:1:1, endln:146:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:1:1, endln:146:10 |vpiName:r |vpiFullName:work@top.r |vpiNetType:48 |vpiNet: \_logic_net: (work@top.s), line:5:57, endln:5:58 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:1:1, endln:146:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:1:1, endln:146:10 |vpiName:s |vpiFullName:work@top.s |vpiNetType:48 |vpiNet: \_logic_net: (work@top.t), line:5:60, endln:5:61 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:1:1, endln:146:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:1:1, endln:146:10 |vpiName:t |vpiFullName:work@top.t |vpiNetType:48 |vpiNet: \_logic_net: (work@top.u), line:5:63, endln:5:64 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:1:1, endln:146:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:1:1, endln:146:10 |vpiName:u |vpiFullName:work@top.u |vpiNetType:48 |vpiNet: \_logic_net: (work@top.v), line:5:66, endln:5:67 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:1:1, endln:146:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:1:1, endln:146:10 |vpiName:v |vpiFullName:work@top.v |vpiNetType:48 |vpiNet: \_logic_net: (work@top.rd), line:7:6, endln:7:8 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:1:1, endln:146:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:1:1, endln:146:10 |vpiName:rd |vpiFullName:work@top.rd |vpiNetType:1 |vpiNet: \_logic_net: (work@top.wr), line:7:10, endln:7:12 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:1:1, endln:146:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:1:1, endln:146:10 |vpiName:wr |vpiFullName:work@top.wr |vpiNetType:1 |vpiNet: \_logic_net: (work@top.Fsm2Out), line:8:12, endln:8:19 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:1:1, endln:146:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:1:1, endln:146:10 |vpiName:Fsm2Out |vpiFullName:work@top.Fsm2Out |vpiNetType:1 |vpiNet: \_logic_net: (work@top.speed), line:9:12, endln:9:17 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:1:1, endln:146:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:1:1, endln:146:10 |vpiName:speed |vpiFullName:work@top.speed |vpiNetType:1 |vpiProcess: \_initial: , line:29:1, endln:32:4 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:1:1, endln:146:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:1:1, endln:146:10 |vpiStmt: \_begin: (work@top), line:29:9, endln:32:4 |vpiParent: @@ -14507,7 +14507,7 @@ design: (work@top) |vpiProcess: \_initial: , line:36:1, endln:69:4 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:1:1, endln:146:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:1:1, endln:146:10 |vpiStmt: \_begin: (work@top), line:36:9, endln:69:4 |vpiParent: @@ -15352,7 +15352,7 @@ design: (work@top) |vpiProcess: \_initial: , line:72:1, endln:76:4 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:1:1, endln:146:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:1:1, endln:146:10 |vpiStmt: \_begin: (work@top), line:72:9, endln:76:4 |vpiParent: @@ -15424,7 +15424,7 @@ design: (work@top) |vpiProcess: \_initial: , line:79:1, endln:83:4 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:1:1, endln:146:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:1:1, endln:146:10 |vpiStmt: \_begin: (work@top), line:79:9, endln:83:4 |vpiParent: @@ -15496,7 +15496,7 @@ design: (work@top) |vpiProcess: \_initial: , line:86:1, endln:89:4 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:1:1, endln:146:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:1:1, endln:146:10 |vpiStmt: \_begin: (work@top), line:86:9, endln:89:4 |vpiParent: @@ -15563,7 +15563,7 @@ design: (work@top) |vpiProcess: \_initial: , line:92:1, endln:97:4 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:1:1, endln:146:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:1:1, endln:146:10 |vpiStmt: \_begin: (work@top), line:92:9, endln:97:4 |vpiParent: @@ -15684,7 +15684,7 @@ design: (work@top) |vpiProcess: \_initial: , line:100:1, endln:106:4 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:1:1, endln:146:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:1:1, endln:146:10 |vpiStmt: \_begin: (work@top), line:100:9, endln:106:4 |vpiParent: @@ -15810,7 +15810,7 @@ design: (work@top) |vpiProcess: \_initial: , line:109:1, endln:113:4 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:1:1, endln:146:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:1:1, endln:146:10 |vpiStmt: \_begin: (work@top), line:109:9, endln:113:4 |vpiParent: @@ -15882,7 +15882,7 @@ design: (work@top) |vpiProcess: \_initial: , line:116:1, endln:128:4 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:1:1, endln:146:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:1:1, endln:146:10 |vpiStmt: \_begin: (work@top), line:116:9, endln:128:4 |vpiParent: @@ -15927,7 +15927,7 @@ design: (work@top) |vpiProcess: \_initial: , line:131:1, endln:142:4 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:1:1, endln:146:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:1:1, endln:146:10 |vpiStmt: \_begin: (work@top), line:131:9, endln:142:4 |vpiParent: @@ -16095,14 +16095,14 @@ design: (work@top) |vpiActual: \_logic_net: (work@top.keys), line:5:5, endln:5:9 |uhdmtopModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:1:1, endln:146:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:1:1, endln:146:10 |vpiName:work@top |vpiDefName:work@top |vpiTop:1 |vpiNet: \_logic_net: (work@top.fsm1clk), line:3:5, endln:3:12 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:1:1, endln:146:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:1:1, endln:146:10 |vpiTypespec: \_logic_typespec: , line:3:1, endln:3:4 |vpiName:fsm1clk @@ -16111,7 +16111,7 @@ design: (work@top) |vpiNet: \_logic_net: (work@top.fsm2clk), line:3:14, endln:3:21 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:1:1, endln:146:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:1:1, endln:146:10 |vpiTypespec: \_logic_typespec: , line:3:1, endln:3:4 |vpiName:fsm2clk @@ -16120,7 +16120,7 @@ design: (work@top) |vpiNet: \_logic_net: (work@top.fsm3clk), line:3:23, endln:3:30 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:1:1, endln:146:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:1:1, endln:146:10 |vpiTypespec: \_logic_typespec: , line:3:1, endln:3:4 |vpiName:fsm3clk @@ -16129,7 +16129,7 @@ design: (work@top) |vpiNet: \_logic_net: (work@top.fsm1rst), line:3:32, endln:3:39 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:1:1, endln:146:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:1:1, endln:146:10 |vpiTypespec: \_logic_typespec: , line:3:1, endln:3:4 |vpiName:fsm1rst @@ -16138,7 +16138,7 @@ design: (work@top) |vpiNet: \_logic_net: (work@top.SlowRam), line:3:41, endln:3:48 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:1:1, endln:146:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:1:1, endln:146:10 |vpiTypespec: \_logic_typespec: , line:3:1, endln:3:4 |vpiName:SlowRam @@ -16147,7 +16147,7 @@ design: (work@top) |vpiNet: \_logic_net: (work@top.fsm2rst), line:3:50, endln:3:57 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:1:1, endln:146:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:1:1, endln:146:10 |vpiTypespec: \_logic_typespec: , line:3:1, endln:3:4 |vpiName:fsm2rst @@ -16156,7 +16156,7 @@ design: (work@top) |vpiNet: \_logic_net: (work@top.ctrl), line:4:5, endln:4:9 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:1:1, endln:146:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:1:1, endln:146:10 |vpiTypespec: \_logic_typespec: , line:4:1, endln:4:4 |vpiName:ctrl @@ -16165,7 +16165,7 @@ design: (work@top) |vpiNet: \_logic_net: (work@top.keys), line:5:5, endln:5:9 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:1:1, endln:146:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:1:1, endln:146:10 |vpiTypespec: \_logic_typespec: , line:5:1, endln:5:4 |vpiName:keys @@ -16174,7 +16174,7 @@ design: (work@top) |vpiNet: \_logic_net: (work@top.brake), line:5:11, endln:5:16 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:1:1, endln:146:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:1:1, endln:146:10 |vpiTypespec: \_logic_typespec: , line:5:1, endln:5:4 |vpiName:brake @@ -16183,7 +16183,7 @@ design: (work@top) |vpiNet: \_logic_net: (work@top.a), line:5:18, endln:5:19 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:1:1, endln:146:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:1:1, endln:146:10 |vpiTypespec: \_logic_typespec: , line:5:1, endln:5:4 |vpiName:a @@ -16192,7 +16192,7 @@ design: (work@top) |vpiNet: \_logic_net: (work@top.b), line:5:21, endln:5:22 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:1:1, endln:146:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:1:1, endln:146:10 |vpiTypespec: \_logic_typespec: , line:5:1, endln:5:4 |vpiName:b @@ -16201,7 +16201,7 @@ design: (work@top) |vpiNet: \_logic_net: (work@top.c), line:5:24, endln:5:25 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:1:1, endln:146:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:1:1, endln:146:10 |vpiTypespec: \_logic_typespec: , line:5:1, endln:5:4 |vpiName:c @@ -16210,7 +16210,7 @@ design: (work@top) |vpiNet: \_logic_net: (work@top.accelerate), line:5:27, endln:5:37 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:1:1, endln:146:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:1:1, endln:146:10 |vpiTypespec: \_logic_typespec: , line:5:1, endln:5:4 |vpiName:accelerate @@ -16219,7 +16219,7 @@ design: (work@top) |vpiNet: \_logic_net: (work@top.m), line:5:39, endln:5:40 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:1:1, endln:146:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:1:1, endln:146:10 |vpiTypespec: \_logic_typespec: , line:5:1, endln:5:4 |vpiName:m @@ -16228,7 +16228,7 @@ design: (work@top) |vpiNet: \_logic_net: (work@top.n), line:5:42, endln:5:43 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:1:1, endln:146:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:1:1, endln:146:10 |vpiTypespec: \_logic_typespec: , line:5:1, endln:5:4 |vpiName:n @@ -16237,7 +16237,7 @@ design: (work@top) |vpiNet: \_logic_net: (work@top.o), line:5:45, endln:5:46 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:1:1, endln:146:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:1:1, endln:146:10 |vpiTypespec: \_logic_typespec: , line:5:1, endln:5:4 |vpiName:o @@ -16246,7 +16246,7 @@ design: (work@top) |vpiNet: \_logic_net: (work@top.p), line:5:48, endln:5:49 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:1:1, endln:146:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:1:1, endln:146:10 |vpiTypespec: \_logic_typespec: , line:5:1, endln:5:4 |vpiName:p @@ -16255,7 +16255,7 @@ design: (work@top) |vpiNet: \_logic_net: (work@top.q), line:5:51, endln:5:52 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:1:1, endln:146:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:1:1, endln:146:10 |vpiTypespec: \_logic_typespec: , line:5:1, endln:5:4 |vpiName:q @@ -16264,7 +16264,7 @@ design: (work@top) |vpiNet: \_logic_net: (work@top.r), line:5:54, endln:5:55 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:1:1, endln:146:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:1:1, endln:146:10 |vpiTypespec: \_logic_typespec: , line:5:1, endln:5:4 |vpiName:r @@ -16273,7 +16273,7 @@ design: (work@top) |vpiNet: \_logic_net: (work@top.s), line:5:57, endln:5:58 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:1:1, endln:146:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:1:1, endln:146:10 |vpiTypespec: \_logic_typespec: , line:5:1, endln:5:4 |vpiName:s @@ -16282,7 +16282,7 @@ design: (work@top) |vpiNet: \_logic_net: (work@top.t), line:5:60, endln:5:61 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:1:1, endln:146:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:1:1, endln:146:10 |vpiTypespec: \_logic_typespec: , line:5:1, endln:5:4 |vpiName:t @@ -16291,7 +16291,7 @@ design: (work@top) |vpiNet: \_logic_net: (work@top.u), line:5:63, endln:5:64 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:1:1, endln:146:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:1:1, endln:146:10 |vpiTypespec: \_logic_typespec: , line:5:1, endln:5:4 |vpiName:u @@ -16300,7 +16300,7 @@ design: (work@top) |vpiNet: \_logic_net: (work@top.v), line:5:66, endln:5:67 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:1:1, endln:146:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:1:1, endln:146:10 |vpiTypespec: \_logic_typespec: , line:5:1, endln:5:4 |vpiName:v @@ -16309,7 +16309,7 @@ design: (work@top) |vpiNet: \_logic_net: (work@top.rd), line:7:6, endln:7:8 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:1:1, endln:146:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:1:1, endln:146:10 |vpiTypespec: \_logic_typespec: , line:7:1, endln:7:5 |vpiName:rd @@ -16318,7 +16318,7 @@ design: (work@top) |vpiNet: \_logic_net: (work@top.wr), line:7:10, endln:7:12 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:1:1, endln:146:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:1:1, endln:146:10 |vpiTypespec: \_logic_typespec: , line:7:1, endln:7:5 |vpiName:wr @@ -16327,7 +16327,7 @@ design: (work@top) |vpiNet: \_logic_net: (work@top.Fsm2Out), line:8:12, endln:8:19 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:1:1, endln:146:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:1:1, endln:146:10 |vpiTypespec: \_logic_typespec: , line:8:1, endln:8:11 |vpiRange: @@ -16354,7 +16354,7 @@ design: (work@top) |vpiNet: \_logic_net: (work@top.speed), line:9:12, endln:9:17 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:1:1, endln:146:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:1:1, endln:146:10 |vpiTypespec: \_logic_typespec: , line:9:1, endln:9:11 |vpiRange: @@ -16382,7 +16382,7 @@ design: (work@top) |vpiProcess: \_initial: , line:29:1, endln:32:4 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:1:1, endln:146:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:1:1, endln:146:10 |vpiStmt: \_begin: (work@top), line:29:9, endln:32:4 |vpiParent: @@ -16443,7 +16443,7 @@ design: (work@top) |vpiProcess: \_initial: , line:36:1, endln:69:4 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:1:1, endln:146:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:1:1, endln:146:10 |vpiStmt: \_begin: (work@top), line:36:9, endln:69:4 |vpiParent: @@ -17210,7 +17210,7 @@ design: (work@top) |vpiProcess: \_initial: , line:72:1, endln:76:4 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:1:1, endln:146:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:1:1, endln:146:10 |vpiStmt: \_begin: (work@top), line:72:9, endln:76:4 |vpiParent: @@ -17276,7 +17276,7 @@ design: (work@top) |vpiProcess: \_initial: , line:79:1, endln:83:4 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:1:1, endln:146:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:1:1, endln:146:10 |vpiStmt: \_begin: (work@top), line:79:9, endln:83:4 |vpiParent: @@ -17342,7 +17342,7 @@ design: (work@top) |vpiProcess: \_initial: , line:86:1, endln:89:4 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:1:1, endln:146:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:1:1, endln:146:10 |vpiStmt: \_begin: (work@top), line:86:9, endln:89:4 |vpiParent: @@ -17403,7 +17403,7 @@ design: (work@top) |vpiProcess: \_initial: , line:92:1, endln:97:4 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:1:1, endln:146:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:1:1, endln:146:10 |vpiStmt: \_begin: (work@top), line:92:9, endln:97:4 |vpiParent: @@ -17506,7 +17506,7 @@ design: (work@top) |vpiProcess: \_initial: , line:100:1, endln:106:4 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:1:1, endln:146:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:1:1, endln:146:10 |vpiStmt: \_begin: (work@top), line:100:9, endln:106:4 |vpiParent: @@ -17614,7 +17614,7 @@ design: (work@top) |vpiProcess: \_initial: , line:109:1, endln:113:4 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:1:1, endln:146:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:1:1, endln:146:10 |vpiStmt: \_begin: (work@top), line:109:9, endln:113:4 |vpiParent: @@ -17680,7 +17680,7 @@ design: (work@top) |vpiProcess: \_initial: , line:116:1, endln:128:4 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:1:1, endln:146:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:1:1, endln:146:10 |vpiStmt: \_begin: (work@top), line:116:9, endln:128:4 |vpiParent: @@ -17703,14 +17703,14 @@ design: (work@top) \_hier_path: (top.F2), line:121:17, endln:121:23 |vpiName:top |vpiActual: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:1:1, endln:146:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:1:1, endln:146:10 |vpiActual: \_ref_obj: (F2), line:121:21, endln:121:23 |vpiParent: \_hier_path: (top.F2), line:121:17, endln:121:23 |vpiName:F2 |vpiActual: - \_module: work@FSM2 (work@top.F2), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:17:1, endln:20:22 + \_module_inst: work@FSM2 (work@top.F2), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:17:1, endln:20:22 |vpiName:$vtDumpvars |vpiStmt: \_delay_control: , line:126:3, endln:126:11 @@ -17725,7 +17725,7 @@ design: (work@top) |vpiProcess: \_initial: , line:131:1, endln:142:4 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:1:1, endln:146:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:1:1, endln:146:10 |vpiStmt: \_begin: (work@top), line:131:9, endln:142:4 |vpiParent: @@ -17856,16 +17856,16 @@ design: (work@top) |vpiFullName:work@top.keys |vpiActual: \_logic_net: (work@top.keys), line:5:5, endln:5:9 - |vpiModule: - \_module: work@FSM1 (work@top.F1), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:11:1, endln:15:21 + |vpiModuleInst: + \_module_inst: work@FSM1 (work@top.F1), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:11:1, endln:15:21 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:1:1, endln:146:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:1:1, endln:146:10 |vpiName:F1 |vpiFullName:work@top.F1 |vpiParameter: \_parameter: (work@top.F1.ST_Read), line:7:17, endln:7:24 |vpiParent: - \_module: work@FSM1 (work@top.F1), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:11:1, endln:15:21 + \_module_inst: work@FSM1 (work@top.F1), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:11:1, endln:15:21 |UINT:0 |vpiTypespec: \_int_typespec: , line:7:11, endln:7:16 @@ -17896,7 +17896,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.F1.ST_Write), line:7:30, endln:7:38 |vpiParent: - \_module: work@FSM1 (work@top.F1), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:11:1, endln:15:21 + \_module_inst: work@FSM1 (work@top.F1), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:11:1, endln:15:21 |UINT:1 |vpiTypespec: \_int_typespec: , line:7:11, endln:7:16 @@ -17927,7 +17927,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.F1.ST_Delay), line:7:44, endln:7:52 |vpiParent: - \_module: work@FSM1 (work@top.F1), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:11:1, endln:15:21 + \_module_inst: work@FSM1 (work@top.F1), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:11:1, endln:15:21 |UINT:2 |vpiTypespec: \_int_typespec: , line:7:11, endln:7:16 @@ -17958,7 +17958,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.F1.ST_Trx), line:8:17, endln:8:23 |vpiParent: - \_module: work@FSM1 (work@top.F1), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:11:1, endln:15:21 + \_module_inst: work@FSM1 (work@top.F1), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:11:1, endln:15:21 |UINT:3 |vpiTypespec: \_int_typespec: , line:7:11, endln:7:16 @@ -17989,7 +17989,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.F1.ST_Hold), line:8:29, endln:8:36 |vpiParent: - \_module: work@FSM1 (work@top.F1), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:11:1, endln:15:21 + \_module_inst: work@FSM1 (work@top.F1), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:11:1, endln:15:21 |UINT:4 |vpiTypespec: \_int_typespec: , line:7:11, endln:7:16 @@ -18020,7 +18020,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.F1.ST_Block), line:8:42, endln:8:50 |vpiParent: - \_module: work@FSM1 (work@top.F1), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:11:1, endln:15:21 + \_module_inst: work@FSM1 (work@top.F1), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:11:1, endln:15:21 |UINT:5 |vpiTypespec: \_int_typespec: , line:7:11, endln:7:16 @@ -18051,7 +18051,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.F1.ST_Wait), line:9:17, endln:9:24 |vpiParent: - \_module: work@FSM1 (work@top.F1), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:11:1, endln:15:21 + \_module_inst: work@FSM1 (work@top.F1), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:11:1, endln:15:21 |UINT:6 |vpiTypespec: \_int_typespec: , line:7:11, endln:7:16 @@ -18082,7 +18082,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.F1.ST_Turn), line:9:30, endln:9:37 |vpiParent: - \_module: work@FSM1 (work@top.F1), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:11:1, endln:15:21 + \_module_inst: work@FSM1 (work@top.F1), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:11:1, endln:15:21 |UINT:7 |vpiTypespec: \_int_typespec: , line:7:11, endln:7:16 @@ -18113,7 +18113,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.F1.ST_Quit), line:9:43, endln:9:50 |vpiParent: - \_module: work@FSM1 (work@top.F1), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:11:1, endln:15:21 + \_module_inst: work@FSM1 (work@top.F1), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:11:1, endln:15:21 |UINT:8 |vpiTypespec: \_int_typespec: , line:7:11, endln:7:16 @@ -18144,7 +18144,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.F1.ST_Exit), line:10:17, endln:10:24 |vpiParent: - \_module: work@FSM1 (work@top.F1), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:11:1, endln:15:21 + \_module_inst: work@FSM1 (work@top.F1), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:11:1, endln:15:21 |UINT:9 |vpiTypespec: \_int_typespec: , line:7:11, endln:7:16 @@ -18175,7 +18175,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.F1.ST_Done), line:10:30, endln:10:37 |vpiParent: - \_module: work@FSM1 (work@top.F1), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:11:1, endln:15:21 + \_module_inst: work@FSM1 (work@top.F1), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:11:1, endln:15:21 |UINT:10 |vpiTypespec: \_int_typespec: , line:7:11, endln:7:16 @@ -18206,7 +18206,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:7:17, endln:7:28 |vpiParent: - \_module: work@FSM1 (work@top.F1), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:11:1, endln:15:21 + \_module_inst: work@FSM1 (work@top.F1), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:11:1, endln:15:21 |vpiRhs: \_constant: , line:7:27, endln:7:28 |vpiDecompile:0 @@ -18220,7 +18220,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:7:30, endln:7:42 |vpiParent: - \_module: work@FSM1 (work@top.F1), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:11:1, endln:15:21 + \_module_inst: work@FSM1 (work@top.F1), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:11:1, endln:15:21 |vpiRhs: \_constant: , line:7:41, endln:7:42 |vpiDecompile:1 @@ -18234,7 +18234,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:7:44, endln:7:56 |vpiParent: - \_module: work@FSM1 (work@top.F1), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:11:1, endln:15:21 + \_module_inst: work@FSM1 (work@top.F1), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:11:1, endln:15:21 |vpiRhs: \_constant: , line:7:55, endln:7:56 |vpiDecompile:2 @@ -18248,7 +18248,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:8:17, endln:8:27 |vpiParent: - \_module: work@FSM1 (work@top.F1), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:11:1, endln:15:21 + \_module_inst: work@FSM1 (work@top.F1), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:11:1, endln:15:21 |vpiRhs: \_constant: , line:8:26, endln:8:27 |vpiDecompile:3 @@ -18262,7 +18262,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:8:29, endln:8:40 |vpiParent: - \_module: work@FSM1 (work@top.F1), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:11:1, endln:15:21 + \_module_inst: work@FSM1 (work@top.F1), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:11:1, endln:15:21 |vpiRhs: \_constant: , line:8:39, endln:8:40 |vpiDecompile:4 @@ -18276,7 +18276,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:8:42, endln:8:54 |vpiParent: - \_module: work@FSM1 (work@top.F1), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:11:1, endln:15:21 + \_module_inst: work@FSM1 (work@top.F1), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:11:1, endln:15:21 |vpiRhs: \_constant: , line:8:53, endln:8:54 |vpiDecompile:5 @@ -18290,7 +18290,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:9:17, endln:9:28 |vpiParent: - \_module: work@FSM1 (work@top.F1), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:11:1, endln:15:21 + \_module_inst: work@FSM1 (work@top.F1), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:11:1, endln:15:21 |vpiRhs: \_constant: , line:9:27, endln:9:28 |vpiDecompile:6 @@ -18304,7 +18304,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:9:30, endln:9:41 |vpiParent: - \_module: work@FSM1 (work@top.F1), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:11:1, endln:15:21 + \_module_inst: work@FSM1 (work@top.F1), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:11:1, endln:15:21 |vpiRhs: \_constant: , line:9:40, endln:9:41 |vpiDecompile:7 @@ -18318,7 +18318,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:9:43, endln:9:54 |vpiParent: - \_module: work@FSM1 (work@top.F1), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:11:1, endln:15:21 + \_module_inst: work@FSM1 (work@top.F1), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:11:1, endln:15:21 |vpiRhs: \_constant: , line:9:53, endln:9:54 |vpiDecompile:8 @@ -18332,7 +18332,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:10:17, endln:10:28 |vpiParent: - \_module: work@FSM1 (work@top.F1), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:11:1, endln:15:21 + \_module_inst: work@FSM1 (work@top.F1), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:11:1, endln:15:21 |vpiRhs: \_constant: , line:10:27, endln:10:28 |vpiDecompile:9 @@ -18346,7 +18346,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:10:30, endln:10:42 |vpiParent: - \_module: work@FSM1 (work@top.F1), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:11:1, endln:15:21 + \_module_inst: work@FSM1 (work@top.F1), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:11:1, endln:15:21 |vpiRhs: \_constant: , line:10:40, endln:10:42 |vpiDecompile:10 @@ -18363,7 +18363,7 @@ design: (work@top) |vpiNet: \_logic_net: (work@top.F1.Read), line:5:5, endln:5:9 |vpiParent: - \_module: work@FSM1 (work@top.F1), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:11:1, endln:15:21 + \_module_inst: work@FSM1 (work@top.F1), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:11:1, endln:15:21 |vpiTypespec: \_logic_typespec: , line:5:1, endln:5:4 |vpiName:Read @@ -18372,7 +18372,7 @@ design: (work@top) |vpiNet: \_logic_net: (work@top.F1.Write), line:5:11, endln:5:16 |vpiParent: - \_module: work@FSM1 (work@top.F1), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:11:1, endln:15:21 + \_module_inst: work@FSM1 (work@top.F1), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:11:1, endln:15:21 |vpiTypespec: \_logic_typespec: , line:5:1, endln:5:4 |vpiName:Write @@ -18381,7 +18381,7 @@ design: (work@top) |vpiNet: \_logic_net: (work@top.F1.Wait), line:5:18, endln:5:22 |vpiParent: - \_module: work@FSM1 (work@top.F1), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:11:1, endln:15:21 + \_module_inst: work@FSM1 (work@top.F1), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:11:1, endln:15:21 |vpiTypespec: \_logic_typespec: , line:5:1, endln:5:4 |vpiName:Wait @@ -18390,7 +18390,7 @@ design: (work@top) |vpiNet: \_logic_net: (work@top.F1.Delay), line:5:24, endln:5:29 |vpiParent: - \_module: work@FSM1 (work@top.F1), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:11:1, endln:15:21 + \_module_inst: work@FSM1 (work@top.F1), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:11:1, endln:15:21 |vpiTypespec: \_logic_typespec: , line:5:1, endln:5:4 |vpiName:Delay @@ -18399,7 +18399,7 @@ design: (work@top) |vpiNet: \_logic_net: (work@top.F1.CurState), line:11:17, endln:11:25 |vpiParent: - \_module: work@FSM1 (work@top.F1), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:11:1, endln:15:21 + \_module_inst: work@FSM1 (work@top.F1), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:11:1, endln:15:21 |vpiTypespec: \_logic_typespec: , line:11:1, endln:11:16 |vpiRange: @@ -18426,7 +18426,7 @@ design: (work@top) |vpiNet: \_logic_net: (work@top.F1.NextState), line:11:27, endln:11:36 |vpiParent: - \_module: work@FSM1 (work@top.F1), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:11:1, endln:15:21 + \_module_inst: work@FSM1 (work@top.F1), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:11:1, endln:15:21 |vpiTypespec: \_logic_typespec: , line:11:1, endln:11:16 |vpiName:NextState @@ -18435,7 +18435,7 @@ design: (work@top) |vpiNet: \_logic_net: (work@top.F1.Clk), line:1:14, endln:1:17 |vpiParent: - \_module: work@FSM1 (work@top.F1), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:11:1, endln:15:21 + \_module_inst: work@FSM1 (work@top.F1), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:11:1, endln:15:21 |vpiTypespec: \_logic_typespec: , line:2:7, endln:2:7 |vpiName:Clk @@ -18443,7 +18443,7 @@ design: (work@top) |vpiNet: \_logic_net: (work@top.F1.Reset), line:1:19, endln:1:24 |vpiParent: - \_module: work@FSM1 (work@top.F1), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:11:1, endln:15:21 + \_module_inst: work@FSM1 (work@top.F1), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:11:1, endln:15:21 |vpiTypespec: \_logic_typespec: , line:2:7, endln:2:7 |vpiName:Reset @@ -18451,17 +18451,17 @@ design: (work@top) |vpiNet: \_logic_net: (work@top.F1.SlowRam), line:1:26, endln:1:33 |vpiParent: - \_module: work@FSM1 (work@top.F1), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:11:1, endln:15:21 + \_module_inst: work@FSM1 (work@top.F1), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:11:1, endln:15:21 |vpiTypespec: \_logic_typespec: , line:2:7, endln:2:7 |vpiName:SlowRam |vpiFullName:work@top.F1.SlowRam |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:1:1, endln:146:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:1:1, endln:146:10 |vpiPort: \_port: (Clk), line:1:14, endln:1:17 |vpiParent: - \_module: work@FSM1 (work@top.F1), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:11:1, endln:15:21 + \_module_inst: work@FSM1 (work@top.F1), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:11:1, endln:15:21 |vpiName:Clk |vpiDirection:1 |vpiHighConn: @@ -18483,11 +18483,11 @@ design: (work@top) |vpiTypedef: \_logic_typespec: , line:2:7, endln:2:7 |vpiInstance: - \_module: work@FSM1 (work@top.F1), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:11:1, endln:15:21 + \_module_inst: work@FSM1 (work@top.F1), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:11:1, endln:15:21 |vpiPort: \_port: (Reset), line:1:19, endln:1:24 |vpiParent: - \_module: work@FSM1 (work@top.F1), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:11:1, endln:15:21 + \_module_inst: work@FSM1 (work@top.F1), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:11:1, endln:15:21 |vpiName:Reset |vpiDirection:1 |vpiHighConn: @@ -18509,11 +18509,11 @@ design: (work@top) |vpiTypedef: \_logic_typespec: , line:2:7, endln:2:7 |vpiInstance: - \_module: work@FSM1 (work@top.F1), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:11:1, endln:15:21 + \_module_inst: work@FSM1 (work@top.F1), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:11:1, endln:15:21 |vpiPort: \_port: (SlowRam), line:1:26, endln:1:33 |vpiParent: - \_module: work@FSM1 (work@top.F1), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:11:1, endln:15:21 + \_module_inst: work@FSM1 (work@top.F1), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:11:1, endln:15:21 |vpiName:SlowRam |vpiDirection:1 |vpiHighConn: @@ -18535,11 +18535,11 @@ design: (work@top) |vpiTypedef: \_logic_typespec: , line:2:7, endln:2:7 |vpiInstance: - \_module: work@FSM1 (work@top.F1), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:11:1, endln:15:21 + \_module_inst: work@FSM1 (work@top.F1), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:11:1, endln:15:21 |vpiPort: \_port: (Read), line:1:35, endln:1:39 |vpiParent: - \_module: work@FSM1 (work@top.F1), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:11:1, endln:15:21 + \_module_inst: work@FSM1 (work@top.F1), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:11:1, endln:15:21 |vpiName:Read |vpiDirection:2 |vpiHighConn: @@ -18561,11 +18561,11 @@ design: (work@top) |vpiTypedef: \_logic_typespec: , line:3:8, endln:3:8 |vpiInstance: - \_module: work@FSM1 (work@top.F1), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:11:1, endln:15:21 + \_module_inst: work@FSM1 (work@top.F1), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:11:1, endln:15:21 |vpiPort: \_port: (Write), line:1:41, endln:1:46 |vpiParent: - \_module: work@FSM1 (work@top.F1), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:11:1, endln:15:21 + \_module_inst: work@FSM1 (work@top.F1), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:11:1, endln:15:21 |vpiName:Write |vpiDirection:2 |vpiHighConn: @@ -18587,11 +18587,11 @@ design: (work@top) |vpiTypedef: \_logic_typespec: , line:3:8, endln:3:8 |vpiInstance: - \_module: work@FSM1 (work@top.F1), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:11:1, endln:15:21 + \_module_inst: work@FSM1 (work@top.F1), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:11:1, endln:15:21 |vpiProcess: \_always: , line:14:1, endln:19:4 |vpiParent: - \_module: work@FSM1 (work@top.F1), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:11:1, endln:15:21 + \_module_inst: work@FSM1 (work@top.F1), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:11:1, endln:15:21 |vpiStmt: \_event_control: , line:14:8, endln:14:22 |vpiParent: @@ -18675,7 +18675,7 @@ design: (work@top) |vpiProcess: \_initial: , line:21:1, endln:26:4 |vpiParent: - \_module: work@FSM1 (work@top.F1), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:11:1, endln:15:21 + \_module_inst: work@FSM1 (work@top.F1), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:11:1, endln:15:21 |vpiStmt: \_begin: (work@top.F1), line:21:9, endln:26:4 |vpiParent: @@ -18748,7 +18748,7 @@ design: (work@top) |vpiProcess: \_always: , line:28:1, endln:156:4 |vpiParent: - \_module: work@FSM1 (work@top.F1), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:11:1, endln:15:21 + \_module_inst: work@FSM1 (work@top.F1), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:11:1, endln:15:21 |vpiStmt: \_event_control: , line:28:8, endln:28:19 |vpiParent: @@ -21508,16 +21508,16 @@ design: (work@top) |vpiActual: \_logic_net: (work@top.F1.NextState), line:11:27, endln:11:36 |vpiAlwaysType:1 - |vpiModule: - \_module: work@FSM2 (work@top.F2), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:17:1, endln:20:22 + |vpiModuleInst: + \_module_inst: work@FSM2 (work@top.F2), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:17:1, endln:20:22 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:1:1, endln:146:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:1:1, endln:146:10 |vpiName:F2 |vpiFullName:work@top.F2 |vpiParameter: \_parameter: (work@top.F2.ST0), line:6:17, endln:6:20 |vpiParent: - \_module: work@FSM2 (work@top.F2), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:17:1, endln:20:22 + \_module_inst: work@FSM2 (work@top.F2), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:17:1, endln:20:22 |UINT:0 |vpiTypespec: \_int_typespec: , line:6:11, endln:6:16 @@ -21548,7 +21548,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.F2.ST1), line:6:25, endln:6:28 |vpiParent: - \_module: work@FSM2 (work@top.F2), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:17:1, endln:20:22 + \_module_inst: work@FSM2 (work@top.F2), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:17:1, endln:20:22 |UINT:1 |vpiTypespec: \_int_typespec: , line:6:11, endln:6:16 @@ -21579,7 +21579,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.F2.ST2), line:6:32, endln:6:35 |vpiParent: - \_module: work@FSM2 (work@top.F2), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:17:1, endln:20:22 + \_module_inst: work@FSM2 (work@top.F2), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:17:1, endln:20:22 |UINT:2 |vpiTypespec: \_int_typespec: , line:6:11, endln:6:16 @@ -21610,7 +21610,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.F2.ST3), line:6:39, endln:6:42 |vpiParent: - \_module: work@FSM2 (work@top.F2), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:17:1, endln:20:22 + \_module_inst: work@FSM2 (work@top.F2), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:17:1, endln:20:22 |UINT:3 |vpiTypespec: \_int_typespec: , line:6:11, endln:6:16 @@ -21641,7 +21641,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.F2.ST4), line:6:46, endln:6:49 |vpiParent: - \_module: work@FSM2 (work@top.F2), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:17:1, endln:20:22 + \_module_inst: work@FSM2 (work@top.F2), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:17:1, endln:20:22 |UINT:4 |vpiTypespec: \_int_typespec: , line:6:11, endln:6:16 @@ -21672,7 +21672,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.F2.ST5), line:6:53, endln:6:56 |vpiParent: - \_module: work@FSM2 (work@top.F2), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:17:1, endln:20:22 + \_module_inst: work@FSM2 (work@top.F2), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:17:1, endln:20:22 |UINT:5 |vpiTypespec: \_int_typespec: , line:6:11, endln:6:16 @@ -21703,7 +21703,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.F2.ST6), line:6:60, endln:6:63 |vpiParent: - \_module: work@FSM2 (work@top.F2), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:17:1, endln:20:22 + \_module_inst: work@FSM2 (work@top.F2), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:17:1, endln:20:22 |UINT:6 |vpiTypespec: \_int_typespec: , line:6:11, endln:6:16 @@ -21734,7 +21734,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.F2.ST7), line:6:66, endln:6:69 |vpiParent: - \_module: work@FSM2 (work@top.F2), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:17:1, endln:20:22 + \_module_inst: work@FSM2 (work@top.F2), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:17:1, endln:20:22 |UINT:7 |vpiTypespec: \_int_typespec: , line:6:11, endln:6:16 @@ -21765,7 +21765,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.F2.ST8), line:7:17, endln:7:20 |vpiParent: - \_module: work@FSM2 (work@top.F2), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:17:1, endln:20:22 + \_module_inst: work@FSM2 (work@top.F2), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:17:1, endln:20:22 |UINT:8 |vpiTypespec: \_int_typespec: , line:6:11, endln:6:16 @@ -21796,7 +21796,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.F2.ST9), line:7:24, endln:7:27 |vpiParent: - \_module: work@FSM2 (work@top.F2), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:17:1, endln:20:22 + \_module_inst: work@FSM2 (work@top.F2), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:17:1, endln:20:22 |UINT:9 |vpiTypespec: \_int_typespec: , line:6:11, endln:6:16 @@ -21827,7 +21827,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.F2.ST10), line:7:31, endln:7:35 |vpiParent: - \_module: work@FSM2 (work@top.F2), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:17:1, endln:20:22 + \_module_inst: work@FSM2 (work@top.F2), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:17:1, endln:20:22 |UINT:10 |vpiTypespec: \_int_typespec: , line:6:11, endln:6:16 @@ -21858,7 +21858,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:6:17, endln:6:23 |vpiParent: - \_module: work@FSM2 (work@top.F2), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:17:1, endln:20:22 + \_module_inst: work@FSM2 (work@top.F2), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:17:1, endln:20:22 |vpiRhs: \_constant: , line:6:22, endln:6:23 |vpiDecompile:0 @@ -21872,7 +21872,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:6:25, endln:6:30 |vpiParent: - \_module: work@FSM2 (work@top.F2), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:17:1, endln:20:22 + \_module_inst: work@FSM2 (work@top.F2), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:17:1, endln:20:22 |vpiRhs: \_constant: , line:6:29, endln:6:30 |vpiDecompile:1 @@ -21886,7 +21886,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:6:32, endln:6:37 |vpiParent: - \_module: work@FSM2 (work@top.F2), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:17:1, endln:20:22 + \_module_inst: work@FSM2 (work@top.F2), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:17:1, endln:20:22 |vpiRhs: \_constant: , line:6:36, endln:6:37 |vpiDecompile:2 @@ -21900,7 +21900,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:6:39, endln:6:44 |vpiParent: - \_module: work@FSM2 (work@top.F2), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:17:1, endln:20:22 + \_module_inst: work@FSM2 (work@top.F2), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:17:1, endln:20:22 |vpiRhs: \_constant: , line:6:43, endln:6:44 |vpiDecompile:3 @@ -21914,7 +21914,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:6:46, endln:6:51 |vpiParent: - \_module: work@FSM2 (work@top.F2), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:17:1, endln:20:22 + \_module_inst: work@FSM2 (work@top.F2), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:17:1, endln:20:22 |vpiRhs: \_constant: , line:6:50, endln:6:51 |vpiDecompile:4 @@ -21928,7 +21928,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:6:53, endln:6:58 |vpiParent: - \_module: work@FSM2 (work@top.F2), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:17:1, endln:20:22 + \_module_inst: work@FSM2 (work@top.F2), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:17:1, endln:20:22 |vpiRhs: \_constant: , line:6:57, endln:6:58 |vpiDecompile:5 @@ -21942,7 +21942,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:6:60, endln:6:65 |vpiParent: - \_module: work@FSM2 (work@top.F2), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:17:1, endln:20:22 + \_module_inst: work@FSM2 (work@top.F2), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:17:1, endln:20:22 |vpiRhs: \_constant: , line:6:64, endln:6:65 |vpiDecompile:6 @@ -21956,7 +21956,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:6:66, endln:6:71 |vpiParent: - \_module: work@FSM2 (work@top.F2), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:17:1, endln:20:22 + \_module_inst: work@FSM2 (work@top.F2), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:17:1, endln:20:22 |vpiRhs: \_constant: , line:6:70, endln:6:71 |vpiDecompile:7 @@ -21970,7 +21970,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:7:17, endln:7:22 |vpiParent: - \_module: work@FSM2 (work@top.F2), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:17:1, endln:20:22 + \_module_inst: work@FSM2 (work@top.F2), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:17:1, endln:20:22 |vpiRhs: \_constant: , line:7:21, endln:7:22 |vpiDecompile:8 @@ -21984,7 +21984,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:7:24, endln:7:29 |vpiParent: - \_module: work@FSM2 (work@top.F2), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:17:1, endln:20:22 + \_module_inst: work@FSM2 (work@top.F2), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:17:1, endln:20:22 |vpiRhs: \_constant: , line:7:28, endln:7:29 |vpiDecompile:9 @@ -21998,7 +21998,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:7:31, endln:7:38 |vpiParent: - \_module: work@FSM2 (work@top.F2), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:17:1, endln:20:22 + \_module_inst: work@FSM2 (work@top.F2), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:17:1, endln:20:22 |vpiRhs: \_constant: , line:7:36, endln:7:38 |vpiDecompile:10 @@ -22015,12 +22015,12 @@ design: (work@top) |vpiTaskFunc: \_task: (work@top.F2.SwitchCtrl), line:23:1, endln:33:8 |vpiParent: - \_module: work@FSM2 (work@top.F2), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:17:1, endln:20:22 + \_module_inst: work@FSM2 (work@top.F2), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:17:1, endln:20:22 |vpiName:SwitchCtrl |vpiFullName:work@top.F2.SwitchCtrl |vpiVisibility:1 |vpiParent: - \_module: work@FSM2 (work@top.F2), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:17:1, endln:20:22 + \_module_inst: work@FSM2 (work@top.F2), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:17:1, endln:20:22 |vpiStmt: \_begin: (work@top.F2.SwitchCtrl), line:24:1, endln:32:4 |vpiParent: @@ -22216,11 +22216,11 @@ design: (work@top) |vpiActual: \_logic_net: (work@top.F2.Ctrl7), line:10:41, endln:10:46 |vpiInstance: - \_module: work@FSM2 (work@top.F2), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:17:1, endln:20:22 + \_module_inst: work@FSM2 (work@top.F2), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:17:1, endln:20:22 |vpiNet: \_logic_net: (work@top.F2.y), line:4:11, endln:4:12 |vpiParent: - \_module: work@FSM2 (work@top.F2), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:17:1, endln:20:22 + \_module_inst: work@FSM2 (work@top.F2), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:17:1, endln:20:22 |vpiTypespec: \_logic_typespec: , line:4:1, endln:4:10 |vpiRange: @@ -22247,7 +22247,7 @@ design: (work@top) |vpiNet: \_logic_net: (work@top.F2.CurrentState), line:8:11, endln:8:23 |vpiParent: - \_module: work@FSM2 (work@top.F2), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:17:1, endln:20:22 + \_module_inst: work@FSM2 (work@top.F2), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:17:1, endln:20:22 |vpiTypespec: \_logic_typespec: , line:8:1, endln:8:10 |vpiRange: @@ -22274,7 +22274,7 @@ design: (work@top) |vpiNet: \_logic_net: (work@top.F2.NextState), line:8:25, endln:8:34 |vpiParent: - \_module: work@FSM2 (work@top.F2), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:17:1, endln:20:22 + \_module_inst: work@FSM2 (work@top.F2), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:17:1, endln:20:22 |vpiTypespec: \_logic_typespec: , line:8:1, endln:8:10 |vpiName:NextState @@ -22283,7 +22283,7 @@ design: (work@top) |vpiNet: \_logic_net: (work@top.F2.Ctrl1), line:10:5, endln:10:10 |vpiParent: - \_module: work@FSM2 (work@top.F2), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:17:1, endln:20:22 + \_module_inst: work@FSM2 (work@top.F2), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:17:1, endln:20:22 |vpiTypespec: \_logic_typespec: , line:10:1, endln:10:4 |vpiName:Ctrl1 @@ -22292,7 +22292,7 @@ design: (work@top) |vpiNet: \_logic_net: (work@top.F2.Ctrl2), line:10:11, endln:10:16 |vpiParent: - \_module: work@FSM2 (work@top.F2), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:17:1, endln:20:22 + \_module_inst: work@FSM2 (work@top.F2), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:17:1, endln:20:22 |vpiTypespec: \_logic_typespec: , line:10:1, endln:10:4 |vpiName:Ctrl2 @@ -22301,7 +22301,7 @@ design: (work@top) |vpiNet: \_logic_net: (work@top.F2.Ctrl3), line:10:17, endln:10:22 |vpiParent: - \_module: work@FSM2 (work@top.F2), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:17:1, endln:20:22 + \_module_inst: work@FSM2 (work@top.F2), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:17:1, endln:20:22 |vpiTypespec: \_logic_typespec: , line:10:1, endln:10:4 |vpiName:Ctrl3 @@ -22310,7 +22310,7 @@ design: (work@top) |vpiNet: \_logic_net: (work@top.F2.Ctrl4), line:10:23, endln:10:28 |vpiParent: - \_module: work@FSM2 (work@top.F2), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:17:1, endln:20:22 + \_module_inst: work@FSM2 (work@top.F2), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:17:1, endln:20:22 |vpiTypespec: \_logic_typespec: , line:10:1, endln:10:4 |vpiName:Ctrl4 @@ -22319,7 +22319,7 @@ design: (work@top) |vpiNet: \_logic_net: (work@top.F2.Ctrl5), line:10:29, endln:10:34 |vpiParent: - \_module: work@FSM2 (work@top.F2), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:17:1, endln:20:22 + \_module_inst: work@FSM2 (work@top.F2), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:17:1, endln:20:22 |vpiTypespec: \_logic_typespec: , line:10:1, endln:10:4 |vpiName:Ctrl5 @@ -22328,7 +22328,7 @@ design: (work@top) |vpiNet: \_logic_net: (work@top.F2.Ctrl6), line:10:35, endln:10:40 |vpiParent: - \_module: work@FSM2 (work@top.F2), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:17:1, endln:20:22 + \_module_inst: work@FSM2 (work@top.F2), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:17:1, endln:20:22 |vpiTypespec: \_logic_typespec: , line:10:1, endln:10:4 |vpiName:Ctrl6 @@ -22337,7 +22337,7 @@ design: (work@top) |vpiNet: \_logic_net: (work@top.F2.Ctrl7), line:10:41, endln:10:46 |vpiParent: - \_module: work@FSM2 (work@top.F2), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:17:1, endln:20:22 + \_module_inst: work@FSM2 (work@top.F2), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:17:1, endln:20:22 |vpiTypespec: \_logic_typespec: , line:10:1, endln:10:4 |vpiName:Ctrl7 @@ -22346,7 +22346,7 @@ design: (work@top) |vpiNet: \_logic_net: (work@top.F2.clock), line:1:13, endln:1:18 |vpiParent: - \_module: work@FSM2 (work@top.F2), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:17:1, endln:20:22 + \_module_inst: work@FSM2 (work@top.F2), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:17:1, endln:20:22 |vpiTypespec: \_logic_typespec: , line:2:7, endln:2:7 |vpiName:clock @@ -22354,7 +22354,7 @@ design: (work@top) |vpiNet: \_logic_net: (work@top.F2.reset), line:1:20, endln:1:25 |vpiParent: - \_module: work@FSM2 (work@top.F2), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:17:1, endln:20:22 + \_module_inst: work@FSM2 (work@top.F2), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:17:1, endln:20:22 |vpiTypespec: \_logic_typespec: , line:2:7, endln:2:7 |vpiName:reset @@ -22362,17 +22362,17 @@ design: (work@top) |vpiNet: \_logic_net: (work@top.F2.control), line:1:27, endln:1:34 |vpiParent: - \_module: work@FSM2 (work@top.F2), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:17:1, endln:20:22 + \_module_inst: work@FSM2 (work@top.F2), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:17:1, endln:20:22 |vpiTypespec: \_logic_typespec: , line:2:7, endln:2:7 |vpiName:control |vpiFullName:work@top.F2.control |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:1:1, endln:146:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:1:1, endln:146:10 |vpiPort: \_port: (clock), line:1:13, endln:1:18 |vpiParent: - \_module: work@FSM2 (work@top.F2), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:17:1, endln:20:22 + \_module_inst: work@FSM2 (work@top.F2), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:17:1, endln:20:22 |vpiName:clock |vpiDirection:1 |vpiHighConn: @@ -22394,11 +22394,11 @@ design: (work@top) |vpiTypedef: \_logic_typespec: , line:2:7, endln:2:7 |vpiInstance: - \_module: work@FSM2 (work@top.F2), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:17:1, endln:20:22 + \_module_inst: work@FSM2 (work@top.F2), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:17:1, endln:20:22 |vpiPort: \_port: (reset), line:1:20, endln:1:25 |vpiParent: - \_module: work@FSM2 (work@top.F2), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:17:1, endln:20:22 + \_module_inst: work@FSM2 (work@top.F2), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:17:1, endln:20:22 |vpiName:reset |vpiDirection:1 |vpiHighConn: @@ -22420,11 +22420,11 @@ design: (work@top) |vpiTypedef: \_logic_typespec: , line:2:7, endln:2:7 |vpiInstance: - \_module: work@FSM2 (work@top.F2), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:17:1, endln:20:22 + \_module_inst: work@FSM2 (work@top.F2), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:17:1, endln:20:22 |vpiPort: \_port: (control), line:1:27, endln:1:34 |vpiParent: - \_module: work@FSM2 (work@top.F2), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:17:1, endln:20:22 + \_module_inst: work@FSM2 (work@top.F2), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:17:1, endln:20:22 |vpiName:control |vpiDirection:1 |vpiHighConn: @@ -22446,11 +22446,11 @@ design: (work@top) |vpiTypedef: \_logic_typespec: , line:2:7, endln:2:7 |vpiInstance: - \_module: work@FSM2 (work@top.F2), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:17:1, endln:20:22 + \_module_inst: work@FSM2 (work@top.F2), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:17:1, endln:20:22 |vpiPort: \_port: (y), line:1:36, endln:1:37 |vpiParent: - \_module: work@FSM2 (work@top.F2), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:17:1, endln:20:22 + \_module_inst: work@FSM2 (work@top.F2), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:17:1, endln:20:22 |vpiName:y |vpiDirection:2 |vpiHighConn: @@ -22492,11 +22492,11 @@ design: (work@top) |UINT:0 |vpiConstType:9 |vpiInstance: - \_module: work@FSM2 (work@top.F2), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:17:1, endln:20:22 + \_module_inst: work@FSM2 (work@top.F2), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:17:1, endln:20:22 |vpiProcess: \_initial: , line:12:1, endln:20:4 |vpiParent: - \_module: work@FSM2 (work@top.F2), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:17:1, endln:20:22 + \_module_inst: work@FSM2 (work@top.F2), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:17:1, endln:20:22 |vpiStmt: \_begin: (work@top.F2), line:12:9, endln:20:4 |vpiParent: @@ -22617,7 +22617,7 @@ design: (work@top) |vpiProcess: \_always: , line:36:1, endln:113:4 |vpiParent: - \_module: work@FSM2 (work@top.F2), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:17:1, endln:20:22 + \_module_inst: work@FSM2 (work@top.F2), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:17:1, endln:20:22 |vpiStmt: \_event_control: , line:36:8, endln:36:34 |vpiParent: @@ -23780,7 +23780,7 @@ design: (work@top) |vpiProcess: \_always: , line:116:1, endln:121:4 |vpiParent: - \_module: work@FSM2 (work@top.F2), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:17:1, endln:20:22 + \_module_inst: work@FSM2 (work@top.F2), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:17:1, endln:20:22 |vpiStmt: \_event_control: , line:116:8, endln:116:41 |vpiParent: @@ -23882,7 +23882,7 @@ design: (work@top) |vpiProcess: \_always: , line:124:1, endln:132:4 |vpiParent: - \_module: work@FSM2 (work@top.F2), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:17:1, endln:20:22 + \_module_inst: work@FSM2 (work@top.F2), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:17:1, endln:20:22 |vpiStmt: \_event_control: , line:124:8, endln:124:23 |vpiParent: @@ -24047,16 +24047,16 @@ design: (work@top) |vpiActual: \_logic_net: (work@top.F2.y), line:4:11, endln:4:12 |vpiAlwaysType:1 - |vpiModule: - \_module: work@FSM3 (work@top.F3), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:22:1, endln:26:24 + |vpiModuleInst: + \_module_inst: work@FSM3 (work@top.F3), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:22:1, endln:26:24 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:1:1, endln:146:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:1:1, endln:146:10 |vpiName:F3 |vpiFullName:work@top.F3 |vpiParameter: \_parameter: (work@top.F3.Stop), line:8:11, endln:8:15 |vpiParent: - \_module: work@FSM3 (work@top.F3), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:22:1, endln:26:24 + \_module_inst: work@FSM3 (work@top.F3), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:22:1, endln:26:24 |BIN:0000 |vpiTypespec: \_int_typespec: @@ -24081,7 +24081,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.F3.Move), line:9:11, endln:9:15 |vpiParent: - \_module: work@FSM3 (work@top.F3), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:22:1, endln:26:24 + \_module_inst: work@FSM3 (work@top.F3), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:22:1, endln:26:24 |BIN:0001 |vpiTypespec: \_int_typespec: @@ -24106,7 +24106,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.F3.Turn), line:10:11, endln:10:15 |vpiParent: - \_module: work@FSM3 (work@top.F3), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:22:1, endln:26:24 + \_module_inst: work@FSM3 (work@top.F3), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:22:1, endln:26:24 |BIN:0010 |vpiTypespec: \_int_typespec: @@ -24131,7 +24131,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.F3.Slow), line:11:11, endln:11:15 |vpiParent: - \_module: work@FSM3 (work@top.F3), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:22:1, endln:26:24 + \_module_inst: work@FSM3 (work@top.F3), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:22:1, endln:26:24 |BIN:0011 |vpiTypespec: \_int_typespec: @@ -24156,7 +24156,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.F3.Medium), line:12:11, endln:12:17 |vpiParent: - \_module: work@FSM3 (work@top.F3), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:22:1, endln:26:24 + \_module_inst: work@FSM3 (work@top.F3), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:22:1, endln:26:24 |BIN:0100 |vpiTypespec: \_int_typespec: @@ -24181,7 +24181,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.F3.Fast), line:13:11, endln:13:15 |vpiParent: - \_module: work@FSM3 (work@top.F3), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:22:1, endln:26:24 + \_module_inst: work@FSM3 (work@top.F3), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:22:1, endln:26:24 |BIN:0101 |vpiTypespec: \_int_typespec: @@ -24206,7 +24206,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.F3.Faster), line:14:11, endln:14:17 |vpiParent: - \_module: work@FSM3 (work@top.F3), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:22:1, endln:26:24 + \_module_inst: work@FSM3 (work@top.F3), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:22:1, endln:26:24 |BIN:0110 |vpiTypespec: \_int_typespec: @@ -24231,7 +24231,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:8:11, endln:8:28 |vpiParent: - \_module: work@FSM3 (work@top.F3), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:22:1, endln:26:24 + \_module_inst: work@FSM3 (work@top.F3), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:22:1, endln:26:24 |vpiRhs: \_constant: , line:8:21, endln:8:28 |vpiDecompile:4'b0000 @@ -24245,7 +24245,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:9:11, endln:9:28 |vpiParent: - \_module: work@FSM3 (work@top.F3), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:22:1, endln:26:24 + \_module_inst: work@FSM3 (work@top.F3), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:22:1, endln:26:24 |vpiRhs: \_constant: , line:9:21, endln:9:28 |vpiDecompile:4'b0001 @@ -24259,7 +24259,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:10:11, endln:10:28 |vpiParent: - \_module: work@FSM3 (work@top.F3), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:22:1, endln:26:24 + \_module_inst: work@FSM3 (work@top.F3), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:22:1, endln:26:24 |vpiRhs: \_constant: , line:10:21, endln:10:28 |vpiDecompile:4'b0010 @@ -24273,7 +24273,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:11:11, endln:11:28 |vpiParent: - \_module: work@FSM3 (work@top.F3), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:22:1, endln:26:24 + \_module_inst: work@FSM3 (work@top.F3), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:22:1, endln:26:24 |vpiRhs: \_constant: , line:11:21, endln:11:28 |vpiDecompile:4'b0011 @@ -24287,7 +24287,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:12:11, endln:12:28 |vpiParent: - \_module: work@FSM3 (work@top.F3), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:22:1, endln:26:24 + \_module_inst: work@FSM3 (work@top.F3), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:22:1, endln:26:24 |vpiRhs: \_constant: , line:12:21, endln:12:28 |vpiDecompile:4'b0100 @@ -24301,7 +24301,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:13:11, endln:13:28 |vpiParent: - \_module: work@FSM3 (work@top.F3), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:22:1, endln:26:24 + \_module_inst: work@FSM3 (work@top.F3), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:22:1, endln:26:24 |vpiRhs: \_constant: , line:13:21, endln:13:28 |vpiDecompile:4'b0101 @@ -24315,7 +24315,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:14:11, endln:14:28 |vpiParent: - \_module: work@FSM3 (work@top.F3), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:22:1, endln:26:24 + \_module_inst: work@FSM3 (work@top.F3), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:22:1, endln:26:24 |vpiRhs: \_constant: , line:14:21, endln:14:28 |vpiDecompile:4'b0110 @@ -24332,7 +24332,7 @@ design: (work@top) |vpiNet: \_logic_net: (work@top.F3.Speed), line:4:11, endln:4:16 |vpiParent: - \_module: work@FSM3 (work@top.F3), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:22:1, endln:26:24 + \_module_inst: work@FSM3 (work@top.F3), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:22:1, endln:26:24 |vpiTypespec: \_logic_typespec: , line:4:1, endln:4:10 |vpiRange: @@ -24359,7 +24359,7 @@ design: (work@top) |vpiNet: \_logic_net: (work@top.F3.Ctrl1), line:6:5, endln:6:10 |vpiParent: - \_module: work@FSM3 (work@top.F3), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:22:1, endln:26:24 + \_module_inst: work@FSM3 (work@top.F3), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:22:1, endln:26:24 |vpiTypespec: \_logic_typespec: , line:6:1, endln:6:4 |vpiName:Ctrl1 @@ -24368,7 +24368,7 @@ design: (work@top) |vpiNet: \_logic_net: (work@top.F3.Ctrl2), line:6:12, endln:6:17 |vpiParent: - \_module: work@FSM3 (work@top.F3), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:22:1, endln:26:24 + \_module_inst: work@FSM3 (work@top.F3), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:22:1, endln:26:24 |vpiTypespec: \_logic_typespec: , line:6:1, endln:6:4 |vpiName:Ctrl2 @@ -24377,7 +24377,7 @@ design: (work@top) |vpiNet: \_logic_net: (work@top.F3.Ctrl3), line:6:19, endln:6:24 |vpiParent: - \_module: work@FSM3 (work@top.F3), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:22:1, endln:26:24 + \_module_inst: work@FSM3 (work@top.F3), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:22:1, endln:26:24 |vpiTypespec: \_logic_typespec: , line:6:1, endln:6:4 |vpiName:Ctrl3 @@ -24386,7 +24386,7 @@ design: (work@top) |vpiNet: \_logic_net: (work@top.F3.clock), line:1:13, endln:1:18 |vpiParent: - \_module: work@FSM3 (work@top.F3), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:22:1, endln:26:24 + \_module_inst: work@FSM3 (work@top.F3), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:22:1, endln:26:24 |vpiTypespec: \_logic_typespec: , line:2:7, endln:2:7 |vpiName:clock @@ -24394,7 +24394,7 @@ design: (work@top) |vpiNet: \_logic_net: (work@top.F3.keys), line:1:20, endln:1:24 |vpiParent: - \_module: work@FSM3 (work@top.F3), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:22:1, endln:26:24 + \_module_inst: work@FSM3 (work@top.F3), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:22:1, endln:26:24 |vpiTypespec: \_logic_typespec: , line:2:7, endln:2:7 |vpiName:keys @@ -24402,7 +24402,7 @@ design: (work@top) |vpiNet: \_logic_net: (work@top.F3.brake), line:1:26, endln:1:31 |vpiParent: - \_module: work@FSM3 (work@top.F3), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:22:1, endln:26:24 + \_module_inst: work@FSM3 (work@top.F3), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:22:1, endln:26:24 |vpiTypespec: \_logic_typespec: , line:2:7, endln:2:7 |vpiName:brake @@ -24410,17 +24410,17 @@ design: (work@top) |vpiNet: \_logic_net: (work@top.F3.accelerate), line:1:33, endln:1:43 |vpiParent: - \_module: work@FSM3 (work@top.F3), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:22:1, endln:26:24 + \_module_inst: work@FSM3 (work@top.F3), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:22:1, endln:26:24 |vpiTypespec: \_logic_typespec: , line:2:7, endln:2:7 |vpiName:accelerate |vpiFullName:work@top.F3.accelerate |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:1:1, endln:146:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:1:1, endln:146:10 |vpiPort: \_port: (clock), line:1:13, endln:1:18 |vpiParent: - \_module: work@FSM3 (work@top.F3), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:22:1, endln:26:24 + \_module_inst: work@FSM3 (work@top.F3), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:22:1, endln:26:24 |vpiName:clock |vpiDirection:1 |vpiHighConn: @@ -24442,11 +24442,11 @@ design: (work@top) |vpiTypedef: \_logic_typespec: , line:2:7, endln:2:7 |vpiInstance: - \_module: work@FSM3 (work@top.F3), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:22:1, endln:26:24 + \_module_inst: work@FSM3 (work@top.F3), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:22:1, endln:26:24 |vpiPort: \_port: (keys), line:1:20, endln:1:24 |vpiParent: - \_module: work@FSM3 (work@top.F3), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:22:1, endln:26:24 + \_module_inst: work@FSM3 (work@top.F3), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:22:1, endln:26:24 |vpiName:keys |vpiDirection:1 |vpiHighConn: @@ -24468,11 +24468,11 @@ design: (work@top) |vpiTypedef: \_logic_typespec: , line:2:7, endln:2:7 |vpiInstance: - \_module: work@FSM3 (work@top.F3), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:22:1, endln:26:24 + \_module_inst: work@FSM3 (work@top.F3), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:22:1, endln:26:24 |vpiPort: \_port: (brake), line:1:26, endln:1:31 |vpiParent: - \_module: work@FSM3 (work@top.F3), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:22:1, endln:26:24 + \_module_inst: work@FSM3 (work@top.F3), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:22:1, endln:26:24 |vpiName:brake |vpiDirection:1 |vpiHighConn: @@ -24494,11 +24494,11 @@ design: (work@top) |vpiTypedef: \_logic_typespec: , line:2:7, endln:2:7 |vpiInstance: - \_module: work@FSM3 (work@top.F3), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:22:1, endln:26:24 + \_module_inst: work@FSM3 (work@top.F3), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:22:1, endln:26:24 |vpiPort: \_port: (accelerate), line:1:33, endln:1:43 |vpiParent: - \_module: work@FSM3 (work@top.F3), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:22:1, endln:26:24 + \_module_inst: work@FSM3 (work@top.F3), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:22:1, endln:26:24 |vpiName:accelerate |vpiDirection:1 |vpiHighConn: @@ -24520,11 +24520,11 @@ design: (work@top) |vpiTypedef: \_logic_typespec: , line:2:7, endln:2:7 |vpiInstance: - \_module: work@FSM3 (work@top.F3), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:22:1, endln:26:24 + \_module_inst: work@FSM3 (work@top.F3), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:22:1, endln:26:24 |vpiPort: \_port: (Speed), line:1:45, endln:1:50 |vpiParent: - \_module: work@FSM3 (work@top.F3), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:22:1, endln:26:24 + \_module_inst: work@FSM3 (work@top.F3), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:22:1, endln:26:24 |vpiName:Speed |vpiDirection:2 |vpiHighConn: @@ -24566,11 +24566,11 @@ design: (work@top) |UINT:0 |vpiConstType:9 |vpiInstance: - \_module: work@FSM3 (work@top.F3), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:22:1, endln:26:24 + \_module_inst: work@FSM3 (work@top.F3), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:22:1, endln:26:24 |vpiProcess: \_initial: , line:16:1, endln:20:4 |vpiParent: - \_module: work@FSM3 (work@top.F3), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:22:1, endln:26:24 + \_module_inst: work@FSM3 (work@top.F3), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:22:1, endln:26:24 |vpiStmt: \_begin: (work@top.F3), line:16:9, endln:20:4 |vpiParent: @@ -24627,7 +24627,7 @@ design: (work@top) |vpiProcess: \_always: , line:22:1, endln:62:5 |vpiParent: - \_module: work@FSM3 (work@top.F3), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:22:1, endln:26:24 + \_module_inst: work@FSM3 (work@top.F3), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:22:1, endln:26:24 |vpiStmt: \_event_control: , line:22:8, endln:22:40 |vpiParent: diff --git a/tests/FSMFunction/FSMFunction.log b/tests/FSMFunction/FSMFunction.log index 42a3109f18..5e01f24f94 100644 --- a/tests/FSMFunction/FSMFunction.log +++ b/tests/FSMFunction/FSMFunction.log @@ -1187,7 +1187,7 @@ io_decl 14 logic_net 16 logic_typespec 22 logic_var 10 -module 7 +module_inst 7 named_begin 2 operation 22 package 2 @@ -1226,7 +1226,7 @@ io_decl 28 logic_net 16 logic_typespec 22 logic_var 10 -module 7 +module_inst 7 named_begin 4 operation 30 package 2 @@ -1725,14 +1725,14 @@ design: (work@fsm_using_function) \_int_typespec: |vpiSigned:1 |uhdmallModules: -\_module: work@fsm_using_function (work@fsm_using_function), file:${SURELOG_DIR}/tests/FSMFunction/top.sv, line:6:1, endln:94:10 +\_module_inst: work@fsm_using_function (work@fsm_using_function), file:${SURELOG_DIR}/tests/FSMFunction/top.sv, line:6:1, endln:94:10 |vpiParent: \_design: (work@fsm_using_function) |vpiFullName:work@fsm_using_function |vpiParameter: \_parameter: (work@fsm_using_function.SIZE), line:23:11, endln:23:15 |vpiParent: - \_module: work@fsm_using_function (work@fsm_using_function), file:${SURELOG_DIR}/tests/FSMFunction/top.sv, line:6:1, endln:94:10 + \_module_inst: work@fsm_using_function (work@fsm_using_function), file:${SURELOG_DIR}/tests/FSMFunction/top.sv, line:6:1, endln:94:10 |UINT:3 |vpiTypespec: \_int_typespec: @@ -1741,7 +1741,7 @@ design: (work@fsm_using_function) |vpiParameter: \_parameter: (work@fsm_using_function.IDLE), line:24:11, endln:24:15 |vpiParent: - \_module: work@fsm_using_function (work@fsm_using_function), file:${SURELOG_DIR}/tests/FSMFunction/top.sv, line:6:1, endln:94:10 + \_module_inst: work@fsm_using_function (work@fsm_using_function), file:${SURELOG_DIR}/tests/FSMFunction/top.sv, line:6:1, endln:94:10 |BIN:001 |vpiTypespec: \_int_typespec: @@ -1758,7 +1758,7 @@ design: (work@fsm_using_function) |vpiParameter: \_parameter: (work@fsm_using_function.GNT0), line:24:26, endln:24:30 |vpiParent: - \_module: work@fsm_using_function (work@fsm_using_function), file:${SURELOG_DIR}/tests/FSMFunction/top.sv, line:6:1, endln:94:10 + \_module_inst: work@fsm_using_function (work@fsm_using_function), file:${SURELOG_DIR}/tests/FSMFunction/top.sv, line:6:1, endln:94:10 |BIN:010 |vpiTypespec: \_int_typespec: @@ -1775,7 +1775,7 @@ design: (work@fsm_using_function) |vpiParameter: \_parameter: (work@fsm_using_function.GNT1), line:24:40, endln:24:44 |vpiParent: - \_module: work@fsm_using_function (work@fsm_using_function), file:${SURELOG_DIR}/tests/FSMFunction/top.sv, line:6:1, endln:94:10 + \_module_inst: work@fsm_using_function (work@fsm_using_function), file:${SURELOG_DIR}/tests/FSMFunction/top.sv, line:6:1, endln:94:10 |BIN:100 |vpiTypespec: \_int_typespec: @@ -1792,7 +1792,7 @@ design: (work@fsm_using_function) |vpiParamAssign: \_param_assign: , line:23:11, endln:23:19 |vpiParent: - \_module: work@fsm_using_function (work@fsm_using_function), file:${SURELOG_DIR}/tests/FSMFunction/top.sv, line:6:1, endln:94:10 + \_module_inst: work@fsm_using_function (work@fsm_using_function), file:${SURELOG_DIR}/tests/FSMFunction/top.sv, line:6:1, endln:94:10 |vpiRhs: \_constant: , line:23:18, endln:23:19 |vpiDecompile:3 @@ -1806,7 +1806,7 @@ design: (work@fsm_using_function) |vpiParamAssign: \_param_assign: , line:24:11, endln:24:25 |vpiParent: - \_module: work@fsm_using_function (work@fsm_using_function), file:${SURELOG_DIR}/tests/FSMFunction/top.sv, line:6:1, endln:94:10 + \_module_inst: work@fsm_using_function (work@fsm_using_function), file:${SURELOG_DIR}/tests/FSMFunction/top.sv, line:6:1, endln:94:10 |vpiRhs: \_constant: , line:24:19, endln:24:25 |vpiDecompile:3'b001 @@ -1820,7 +1820,7 @@ design: (work@fsm_using_function) |vpiParamAssign: \_param_assign: , line:24:26, endln:24:39 |vpiParent: - \_module: work@fsm_using_function (work@fsm_using_function), file:${SURELOG_DIR}/tests/FSMFunction/top.sv, line:6:1, endln:94:10 + \_module_inst: work@fsm_using_function (work@fsm_using_function), file:${SURELOG_DIR}/tests/FSMFunction/top.sv, line:6:1, endln:94:10 |vpiRhs: \_constant: , line:24:33, endln:24:39 |vpiDecompile:3'b010 @@ -1834,7 +1834,7 @@ design: (work@fsm_using_function) |vpiParamAssign: \_param_assign: , line:24:40, endln:24:53 |vpiParent: - \_module: work@fsm_using_function (work@fsm_using_function), file:${SURELOG_DIR}/tests/FSMFunction/top.sv, line:6:1, endln:94:10 + \_module_inst: work@fsm_using_function (work@fsm_using_function), file:${SURELOG_DIR}/tests/FSMFunction/top.sv, line:6:1, endln:94:10 |vpiRhs: \_constant: , line:24:47, endln:24:53 |vpiDecompile:3'b100 @@ -1849,7 +1849,7 @@ design: (work@fsm_using_function) |vpiTaskFunc: \_function: (work@fsm_using_function.fsm_function), line:31:1, endln:55:12 |vpiParent: - \_module: work@fsm_using_function (work@fsm_using_function), file:${SURELOG_DIR}/tests/FSMFunction/top.sv, line:6:1, endln:94:10 + \_module_inst: work@fsm_using_function (work@fsm_using_function), file:${SURELOG_DIR}/tests/FSMFunction/top.sv, line:6:1, endln:94:10 |vpiName:fsm_function |vpiFullName:work@fsm_using_function.fsm_function |vpiVisibility:1 @@ -1888,7 +1888,7 @@ design: (work@fsm_using_function) |UINT:0 |vpiConstType:9 |vpiParent: - \_module: work@fsm_using_function (work@fsm_using_function), file:${SURELOG_DIR}/tests/FSMFunction/top.sv, line:6:1, endln:94:10 + \_module_inst: work@fsm_using_function (work@fsm_using_function), file:${SURELOG_DIR}/tests/FSMFunction/top.sv, line:6:1, endln:94:10 |vpiIODecl: \_io_decl: (state), line:32:22, endln:32:27 |vpiParent: @@ -2285,67 +2285,67 @@ design: (work@fsm_using_function) |vpiActual: \_logic_var: (fsm_function), line:31:10, endln:31:20 |vpiInstance: - \_module: work@fsm_using_function (work@fsm_using_function), file:${SURELOG_DIR}/tests/FSMFunction/top.sv, line:6:1, endln:94:10 + \_module_inst: work@fsm_using_function (work@fsm_using_function), file:${SURELOG_DIR}/tests/FSMFunction/top.sv, line:6:1, endln:94:10 |vpiNet: \_logic_net: (work@fsm_using_function.clock), line:19:9, endln:19:14 |vpiParent: - \_module: work@fsm_using_function (work@fsm_using_function), file:${SURELOG_DIR}/tests/FSMFunction/top.sv, line:6:1, endln:94:10 + \_module_inst: work@fsm_using_function (work@fsm_using_function), file:${SURELOG_DIR}/tests/FSMFunction/top.sv, line:6:1, endln:94:10 |vpiName:clock |vpiFullName:work@fsm_using_function.clock |vpiNetType:1 |vpiNet: \_logic_net: (work@fsm_using_function.reset), line:19:15, endln:19:20 |vpiParent: - \_module: work@fsm_using_function (work@fsm_using_function), file:${SURELOG_DIR}/tests/FSMFunction/top.sv, line:6:1, endln:94:10 + \_module_inst: work@fsm_using_function (work@fsm_using_function), file:${SURELOG_DIR}/tests/FSMFunction/top.sv, line:6:1, endln:94:10 |vpiName:reset |vpiFullName:work@fsm_using_function.reset |vpiNetType:1 |vpiNet: \_logic_net: (work@fsm_using_function.req_0), line:19:21, endln:19:26 |vpiParent: - \_module: work@fsm_using_function (work@fsm_using_function), file:${SURELOG_DIR}/tests/FSMFunction/top.sv, line:6:1, endln:94:10 + \_module_inst: work@fsm_using_function (work@fsm_using_function), file:${SURELOG_DIR}/tests/FSMFunction/top.sv, line:6:1, endln:94:10 |vpiName:req_0 |vpiFullName:work@fsm_using_function.req_0 |vpiNetType:1 |vpiNet: \_logic_net: (work@fsm_using_function.req_1), line:19:27, endln:19:32 |vpiParent: - \_module: work@fsm_using_function (work@fsm_using_function), file:${SURELOG_DIR}/tests/FSMFunction/top.sv, line:6:1, endln:94:10 + \_module_inst: work@fsm_using_function (work@fsm_using_function), file:${SURELOG_DIR}/tests/FSMFunction/top.sv, line:6:1, endln:94:10 |vpiName:req_1 |vpiFullName:work@fsm_using_function.req_1 |vpiNetType:1 |vpiNet: \_logic_net: (work@fsm_using_function.gnt_0), line:21:9, endln:21:14 |vpiParent: - \_module: work@fsm_using_function (work@fsm_using_function), file:${SURELOG_DIR}/tests/FSMFunction/top.sv, line:6:1, endln:94:10 + \_module_inst: work@fsm_using_function (work@fsm_using_function), file:${SURELOG_DIR}/tests/FSMFunction/top.sv, line:6:1, endln:94:10 |vpiName:gnt_0 |vpiFullName:work@fsm_using_function.gnt_0 |vpiNetType:48 |vpiNet: \_logic_net: (work@fsm_using_function.gnt_1), line:21:15, endln:21:20 |vpiParent: - \_module: work@fsm_using_function (work@fsm_using_function), file:${SURELOG_DIR}/tests/FSMFunction/top.sv, line:6:1, endln:94:10 + \_module_inst: work@fsm_using_function (work@fsm_using_function), file:${SURELOG_DIR}/tests/FSMFunction/top.sv, line:6:1, endln:94:10 |vpiName:gnt_1 |vpiFullName:work@fsm_using_function.gnt_1 |vpiNetType:48 |vpiNet: \_logic_net: (work@fsm_using_function.state), line:26:27, endln:26:32 |vpiParent: - \_module: work@fsm_using_function (work@fsm_using_function), file:${SURELOG_DIR}/tests/FSMFunction/top.sv, line:6:1, endln:94:10 + \_module_inst: work@fsm_using_function (work@fsm_using_function), file:${SURELOG_DIR}/tests/FSMFunction/top.sv, line:6:1, endln:94:10 |vpiName:state |vpiFullName:work@fsm_using_function.state |vpiNetType:48 |vpiNet: \_logic_net: (work@fsm_using_function.next_state), line:27:27, endln:27:37 |vpiParent: - \_module: work@fsm_using_function (work@fsm_using_function), file:${SURELOG_DIR}/tests/FSMFunction/top.sv, line:6:1, endln:94:10 + \_module_inst: work@fsm_using_function (work@fsm_using_function), file:${SURELOG_DIR}/tests/FSMFunction/top.sv, line:6:1, endln:94:10 |vpiName:next_state |vpiFullName:work@fsm_using_function.next_state |vpiNetType:1 |vpiPort: \_port: (clock), line:7:1, endln:7:6 |vpiParent: - \_module: work@fsm_using_function (work@fsm_using_function), file:${SURELOG_DIR}/tests/FSMFunction/top.sv, line:6:1, endln:94:10 + \_module_inst: work@fsm_using_function (work@fsm_using_function), file:${SURELOG_DIR}/tests/FSMFunction/top.sv, line:6:1, endln:94:10 |vpiName:clock |vpiDirection:1 |vpiLowConn: @@ -2357,7 +2357,7 @@ design: (work@fsm_using_function) |vpiPort: \_port: (reset), line:8:1, endln:8:6 |vpiParent: - \_module: work@fsm_using_function (work@fsm_using_function), file:${SURELOG_DIR}/tests/FSMFunction/top.sv, line:6:1, endln:94:10 + \_module_inst: work@fsm_using_function (work@fsm_using_function), file:${SURELOG_DIR}/tests/FSMFunction/top.sv, line:6:1, endln:94:10 |vpiName:reset |vpiDirection:1 |vpiLowConn: @@ -2369,7 +2369,7 @@ design: (work@fsm_using_function) |vpiPort: \_port: (req_0), line:9:1, endln:9:6 |vpiParent: - \_module: work@fsm_using_function (work@fsm_using_function), file:${SURELOG_DIR}/tests/FSMFunction/top.sv, line:6:1, endln:94:10 + \_module_inst: work@fsm_using_function (work@fsm_using_function), file:${SURELOG_DIR}/tests/FSMFunction/top.sv, line:6:1, endln:94:10 |vpiName:req_0 |vpiDirection:1 |vpiLowConn: @@ -2381,7 +2381,7 @@ design: (work@fsm_using_function) |vpiPort: \_port: (req_1), line:10:1, endln:10:6 |vpiParent: - \_module: work@fsm_using_function (work@fsm_using_function), file:${SURELOG_DIR}/tests/FSMFunction/top.sv, line:6:1, endln:94:10 + \_module_inst: work@fsm_using_function (work@fsm_using_function), file:${SURELOG_DIR}/tests/FSMFunction/top.sv, line:6:1, endln:94:10 |vpiName:req_1 |vpiDirection:1 |vpiLowConn: @@ -2393,7 +2393,7 @@ design: (work@fsm_using_function) |vpiPort: \_port: (gnt_0), line:11:1, endln:11:6 |vpiParent: - \_module: work@fsm_using_function (work@fsm_using_function), file:${SURELOG_DIR}/tests/FSMFunction/top.sv, line:6:1, endln:94:10 + \_module_inst: work@fsm_using_function (work@fsm_using_function), file:${SURELOG_DIR}/tests/FSMFunction/top.sv, line:6:1, endln:94:10 |vpiName:gnt_0 |vpiDirection:2 |vpiLowConn: @@ -2405,7 +2405,7 @@ design: (work@fsm_using_function) |vpiPort: \_port: (gnt_1), line:12:1, endln:12:6 |vpiParent: - \_module: work@fsm_using_function (work@fsm_using_function), file:${SURELOG_DIR}/tests/FSMFunction/top.sv, line:6:1, endln:94:10 + \_module_inst: work@fsm_using_function (work@fsm_using_function), file:${SURELOG_DIR}/tests/FSMFunction/top.sv, line:6:1, endln:94:10 |vpiName:gnt_1 |vpiDirection:2 |vpiLowConn: @@ -2417,7 +2417,7 @@ design: (work@fsm_using_function) |vpiProcess: \_always: , line:57:1, endln:64:4 |vpiParent: - \_module: work@fsm_using_function (work@fsm_using_function), file:${SURELOG_DIR}/tests/FSMFunction/top.sv, line:6:1, endln:94:10 + \_module_inst: work@fsm_using_function (work@fsm_using_function), file:${SURELOG_DIR}/tests/FSMFunction/top.sv, line:6:1, endln:94:10 |vpiStmt: \_event_control: , line:57:8, endln:57:25 |vpiParent: @@ -2530,7 +2530,7 @@ design: (work@fsm_using_function) |vpiProcess: \_always: , line:66:1, endln:92:4 |vpiParent: - \_module: work@fsm_using_function (work@fsm_using_function), file:${SURELOG_DIR}/tests/FSMFunction/top.sv, line:6:1, endln:94:10 + \_module_inst: work@fsm_using_function (work@fsm_using_function), file:${SURELOG_DIR}/tests/FSMFunction/top.sv, line:6:1, endln:94:10 |vpiStmt: \_event_control: , line:66:8, endln:66:25 |vpiParent: @@ -2920,7 +2920,7 @@ design: (work@fsm_using_function) |vpiContAssign: \_cont_assign: , line:29:8, endln:29:54 |vpiParent: - \_module: work@fsm_using_function (work@fsm_using_function), file:${SURELOG_DIR}/tests/FSMFunction/top.sv, line:6:1, endln:94:10 + \_module_inst: work@fsm_using_function (work@fsm_using_function), file:${SURELOG_DIR}/tests/FSMFunction/top.sv, line:6:1, endln:94:10 |vpiRhs: \_func_call: (fsm_function), line:29:21, endln:29:54 |vpiParent: @@ -2963,12 +2963,12 @@ design: (work@fsm_using_function) |vpiActual: \_logic_net: (work@fsm_using_function.next_state), line:27:27, endln:27:37 |uhdmtopModules: -\_module: work@fsm_using_function (work@fsm_using_function), file:${SURELOG_DIR}/tests/FSMFunction/top.sv, line:6:1, endln:94:10 +\_module_inst: work@fsm_using_function (work@fsm_using_function), file:${SURELOG_DIR}/tests/FSMFunction/top.sv, line:6:1, endln:94:10 |vpiName:work@fsm_using_function |vpiParameter: \_parameter: (work@fsm_using_function.SIZE), line:23:11, endln:23:15 |vpiParent: - \_module: work@fsm_using_function (work@fsm_using_function), file:${SURELOG_DIR}/tests/FSMFunction/top.sv, line:6:1, endln:94:10 + \_module_inst: work@fsm_using_function (work@fsm_using_function), file:${SURELOG_DIR}/tests/FSMFunction/top.sv, line:6:1, endln:94:10 |UINT:3 |vpiTypespec: \_int_typespec: @@ -2979,7 +2979,7 @@ design: (work@fsm_using_function) |vpiParameter: \_parameter: (work@fsm_using_function.IDLE), line:24:11, endln:24:15 |vpiParent: - \_module: work@fsm_using_function (work@fsm_using_function), file:${SURELOG_DIR}/tests/FSMFunction/top.sv, line:6:1, endln:94:10 + \_module_inst: work@fsm_using_function (work@fsm_using_function), file:${SURELOG_DIR}/tests/FSMFunction/top.sv, line:6:1, endln:94:10 |BIN:001 |vpiTypespec: \_int_typespec: @@ -3004,7 +3004,7 @@ design: (work@fsm_using_function) |vpiParameter: \_parameter: (work@fsm_using_function.GNT0), line:24:26, endln:24:30 |vpiParent: - \_module: work@fsm_using_function (work@fsm_using_function), file:${SURELOG_DIR}/tests/FSMFunction/top.sv, line:6:1, endln:94:10 + \_module_inst: work@fsm_using_function (work@fsm_using_function), file:${SURELOG_DIR}/tests/FSMFunction/top.sv, line:6:1, endln:94:10 |BIN:010 |vpiTypespec: \_int_typespec: @@ -3029,7 +3029,7 @@ design: (work@fsm_using_function) |vpiParameter: \_parameter: (work@fsm_using_function.GNT1), line:24:40, endln:24:44 |vpiParent: - \_module: work@fsm_using_function (work@fsm_using_function), file:${SURELOG_DIR}/tests/FSMFunction/top.sv, line:6:1, endln:94:10 + \_module_inst: work@fsm_using_function (work@fsm_using_function), file:${SURELOG_DIR}/tests/FSMFunction/top.sv, line:6:1, endln:94:10 |BIN:100 |vpiTypespec: \_int_typespec: @@ -3054,7 +3054,7 @@ design: (work@fsm_using_function) |vpiParamAssign: \_param_assign: , line:23:11, endln:23:19 |vpiParent: - \_module: work@fsm_using_function (work@fsm_using_function), file:${SURELOG_DIR}/tests/FSMFunction/top.sv, line:6:1, endln:94:10 + \_module_inst: work@fsm_using_function (work@fsm_using_function), file:${SURELOG_DIR}/tests/FSMFunction/top.sv, line:6:1, endln:94:10 |vpiRhs: \_constant: , line:23:18, endln:23:19 |vpiDecompile:3 @@ -3068,7 +3068,7 @@ design: (work@fsm_using_function) |vpiParamAssign: \_param_assign: , line:24:11, endln:24:25 |vpiParent: - \_module: work@fsm_using_function (work@fsm_using_function), file:${SURELOG_DIR}/tests/FSMFunction/top.sv, line:6:1, endln:94:10 + \_module_inst: work@fsm_using_function (work@fsm_using_function), file:${SURELOG_DIR}/tests/FSMFunction/top.sv, line:6:1, endln:94:10 |vpiRhs: \_constant: , line:24:19, endln:24:25 |vpiDecompile:3'b001 @@ -3082,7 +3082,7 @@ design: (work@fsm_using_function) |vpiParamAssign: \_param_assign: , line:24:26, endln:24:39 |vpiParent: - \_module: work@fsm_using_function (work@fsm_using_function), file:${SURELOG_DIR}/tests/FSMFunction/top.sv, line:6:1, endln:94:10 + \_module_inst: work@fsm_using_function (work@fsm_using_function), file:${SURELOG_DIR}/tests/FSMFunction/top.sv, line:6:1, endln:94:10 |vpiRhs: \_constant: , line:24:33, endln:24:39 |vpiDecompile:3'b010 @@ -3096,7 +3096,7 @@ design: (work@fsm_using_function) |vpiParamAssign: \_param_assign: , line:24:40, endln:24:53 |vpiParent: - \_module: work@fsm_using_function (work@fsm_using_function), file:${SURELOG_DIR}/tests/FSMFunction/top.sv, line:6:1, endln:94:10 + \_module_inst: work@fsm_using_function (work@fsm_using_function), file:${SURELOG_DIR}/tests/FSMFunction/top.sv, line:6:1, endln:94:10 |vpiRhs: \_constant: , line:24:47, endln:24:53 |vpiDecompile:3'b100 @@ -3112,14 +3112,14 @@ design: (work@fsm_using_function) |vpiTaskFunc: \_function: (work@fsm_using_function.fsm_function), line:31:1, endln:55:12 |vpiParent: - \_module: work@fsm_using_function (work@fsm_using_function), file:${SURELOG_DIR}/tests/FSMFunction/top.sv, line:6:1, endln:94:10 + \_module_inst: work@fsm_using_function (work@fsm_using_function), file:${SURELOG_DIR}/tests/FSMFunction/top.sv, line:6:1, endln:94:10 |vpiName:fsm_function |vpiFullName:work@fsm_using_function.fsm_function |vpiVisibility:1 |vpiReturn: \_logic_var: , line:31:10, endln:31:20 |vpiParent: - \_module: work@fsm_using_function (work@fsm_using_function), file:${SURELOG_DIR}/tests/FSMFunction/top.sv, line:6:1, endln:94:10 + \_module_inst: work@fsm_using_function (work@fsm_using_function), file:${SURELOG_DIR}/tests/FSMFunction/top.sv, line:6:1, endln:94:10 |vpiIODecl: \_io_decl: (state), line:32:22, endln:32:27 |vpiParent: @@ -3481,11 +3481,11 @@ design: (work@fsm_using_function) |vpiActual: \_logic_var: , line:31:10, endln:31:20 |vpiInstance: - \_module: work@fsm_using_function (work@fsm_using_function), file:${SURELOG_DIR}/tests/FSMFunction/top.sv, line:6:1, endln:94:10 + \_module_inst: work@fsm_using_function (work@fsm_using_function), file:${SURELOG_DIR}/tests/FSMFunction/top.sv, line:6:1, endln:94:10 |vpiNet: \_logic_net: (work@fsm_using_function.clock), line:19:9, endln:19:14 |vpiParent: - \_module: work@fsm_using_function (work@fsm_using_function), file:${SURELOG_DIR}/tests/FSMFunction/top.sv, line:6:1, endln:94:10 + \_module_inst: work@fsm_using_function (work@fsm_using_function), file:${SURELOG_DIR}/tests/FSMFunction/top.sv, line:6:1, endln:94:10 |vpiTypespec: \_logic_typespec: , line:19:1, endln:19:5 |vpiName:clock @@ -3494,7 +3494,7 @@ design: (work@fsm_using_function) |vpiNet: \_logic_net: (work@fsm_using_function.reset), line:19:15, endln:19:20 |vpiParent: - \_module: work@fsm_using_function (work@fsm_using_function), file:${SURELOG_DIR}/tests/FSMFunction/top.sv, line:6:1, endln:94:10 + \_module_inst: work@fsm_using_function (work@fsm_using_function), file:${SURELOG_DIR}/tests/FSMFunction/top.sv, line:6:1, endln:94:10 |vpiTypespec: \_logic_typespec: , line:19:1, endln:19:5 |vpiName:reset @@ -3503,7 +3503,7 @@ design: (work@fsm_using_function) |vpiNet: \_logic_net: (work@fsm_using_function.req_0), line:19:21, endln:19:26 |vpiParent: - \_module: work@fsm_using_function (work@fsm_using_function), file:${SURELOG_DIR}/tests/FSMFunction/top.sv, line:6:1, endln:94:10 + \_module_inst: work@fsm_using_function (work@fsm_using_function), file:${SURELOG_DIR}/tests/FSMFunction/top.sv, line:6:1, endln:94:10 |vpiTypespec: \_logic_typespec: , line:19:1, endln:19:5 |vpiName:req_0 @@ -3512,7 +3512,7 @@ design: (work@fsm_using_function) |vpiNet: \_logic_net: (work@fsm_using_function.req_1), line:19:27, endln:19:32 |vpiParent: - \_module: work@fsm_using_function (work@fsm_using_function), file:${SURELOG_DIR}/tests/FSMFunction/top.sv, line:6:1, endln:94:10 + \_module_inst: work@fsm_using_function (work@fsm_using_function), file:${SURELOG_DIR}/tests/FSMFunction/top.sv, line:6:1, endln:94:10 |vpiTypespec: \_logic_typespec: , line:19:1, endln:19:5 |vpiName:req_1 @@ -3521,7 +3521,7 @@ design: (work@fsm_using_function) |vpiNet: \_logic_net: (work@fsm_using_function.gnt_0), line:21:9, endln:21:14 |vpiParent: - \_module: work@fsm_using_function (work@fsm_using_function), file:${SURELOG_DIR}/tests/FSMFunction/top.sv, line:6:1, endln:94:10 + \_module_inst: work@fsm_using_function (work@fsm_using_function), file:${SURELOG_DIR}/tests/FSMFunction/top.sv, line:6:1, endln:94:10 |vpiTypespec: \_logic_typespec: , line:21:1, endln:21:4 |vpiName:gnt_0 @@ -3530,7 +3530,7 @@ design: (work@fsm_using_function) |vpiNet: \_logic_net: (work@fsm_using_function.gnt_1), line:21:15, endln:21:20 |vpiParent: - \_module: work@fsm_using_function (work@fsm_using_function), file:${SURELOG_DIR}/tests/FSMFunction/top.sv, line:6:1, endln:94:10 + \_module_inst: work@fsm_using_function (work@fsm_using_function), file:${SURELOG_DIR}/tests/FSMFunction/top.sv, line:6:1, endln:94:10 |vpiTypespec: \_logic_typespec: , line:21:1, endln:21:4 |vpiName:gnt_1 @@ -3539,7 +3539,7 @@ design: (work@fsm_using_function) |vpiNet: \_logic_net: (work@fsm_using_function.state), line:26:27, endln:26:32 |vpiParent: - \_module: work@fsm_using_function (work@fsm_using_function), file:${SURELOG_DIR}/tests/FSMFunction/top.sv, line:6:1, endln:94:10 + \_module_inst: work@fsm_using_function (work@fsm_using_function), file:${SURELOG_DIR}/tests/FSMFunction/top.sv, line:6:1, endln:94:10 |vpiTypespec: \_logic_typespec: , line:26:1, endln:26:17 |vpiRange: @@ -3566,7 +3566,7 @@ design: (work@fsm_using_function) |vpiNet: \_logic_net: (work@fsm_using_function.next_state), line:27:27, endln:27:37 |vpiParent: - \_module: work@fsm_using_function (work@fsm_using_function), file:${SURELOG_DIR}/tests/FSMFunction/top.sv, line:6:1, endln:94:10 + \_module_inst: work@fsm_using_function (work@fsm_using_function), file:${SURELOG_DIR}/tests/FSMFunction/top.sv, line:6:1, endln:94:10 |vpiTypespec: \_logic_typespec: , line:27:1, endln:27:17 |vpiRange: @@ -3594,7 +3594,7 @@ design: (work@fsm_using_function) |vpiPort: \_port: (clock), line:7:1, endln:7:6 |vpiParent: - \_module: work@fsm_using_function (work@fsm_using_function), file:${SURELOG_DIR}/tests/FSMFunction/top.sv, line:6:1, endln:94:10 + \_module_inst: work@fsm_using_function (work@fsm_using_function), file:${SURELOG_DIR}/tests/FSMFunction/top.sv, line:6:1, endln:94:10 |vpiName:clock |vpiDirection:1 |vpiLowConn: @@ -3608,11 +3608,11 @@ design: (work@fsm_using_function) |vpiTypedef: \_logic_typespec: , line:15:9, endln:15:9 |vpiInstance: - \_module: work@fsm_using_function (work@fsm_using_function), file:${SURELOG_DIR}/tests/FSMFunction/top.sv, line:6:1, endln:94:10 + \_module_inst: work@fsm_using_function (work@fsm_using_function), file:${SURELOG_DIR}/tests/FSMFunction/top.sv, line:6:1, endln:94:10 |vpiPort: \_port: (reset), line:8:1, endln:8:6 |vpiParent: - \_module: work@fsm_using_function (work@fsm_using_function), file:${SURELOG_DIR}/tests/FSMFunction/top.sv, line:6:1, endln:94:10 + \_module_inst: work@fsm_using_function (work@fsm_using_function), file:${SURELOG_DIR}/tests/FSMFunction/top.sv, line:6:1, endln:94:10 |vpiName:reset |vpiDirection:1 |vpiLowConn: @@ -3626,11 +3626,11 @@ design: (work@fsm_using_function) |vpiTypedef: \_logic_typespec: , line:15:9, endln:15:9 |vpiInstance: - \_module: work@fsm_using_function (work@fsm_using_function), file:${SURELOG_DIR}/tests/FSMFunction/top.sv, line:6:1, endln:94:10 + \_module_inst: work@fsm_using_function (work@fsm_using_function), file:${SURELOG_DIR}/tests/FSMFunction/top.sv, line:6:1, endln:94:10 |vpiPort: \_port: (req_0), line:9:1, endln:9:6 |vpiParent: - \_module: work@fsm_using_function (work@fsm_using_function), file:${SURELOG_DIR}/tests/FSMFunction/top.sv, line:6:1, endln:94:10 + \_module_inst: work@fsm_using_function (work@fsm_using_function), file:${SURELOG_DIR}/tests/FSMFunction/top.sv, line:6:1, endln:94:10 |vpiName:req_0 |vpiDirection:1 |vpiLowConn: @@ -3644,11 +3644,11 @@ design: (work@fsm_using_function) |vpiTypedef: \_logic_typespec: , line:15:9, endln:15:9 |vpiInstance: - \_module: work@fsm_using_function (work@fsm_using_function), file:${SURELOG_DIR}/tests/FSMFunction/top.sv, line:6:1, endln:94:10 + \_module_inst: work@fsm_using_function (work@fsm_using_function), file:${SURELOG_DIR}/tests/FSMFunction/top.sv, line:6:1, endln:94:10 |vpiPort: \_port: (req_1), line:10:1, endln:10:6 |vpiParent: - \_module: work@fsm_using_function (work@fsm_using_function), file:${SURELOG_DIR}/tests/FSMFunction/top.sv, line:6:1, endln:94:10 + \_module_inst: work@fsm_using_function (work@fsm_using_function), file:${SURELOG_DIR}/tests/FSMFunction/top.sv, line:6:1, endln:94:10 |vpiName:req_1 |vpiDirection:1 |vpiLowConn: @@ -3662,11 +3662,11 @@ design: (work@fsm_using_function) |vpiTypedef: \_logic_typespec: , line:15:9, endln:15:9 |vpiInstance: - \_module: work@fsm_using_function (work@fsm_using_function), file:${SURELOG_DIR}/tests/FSMFunction/top.sv, line:6:1, endln:94:10 + \_module_inst: work@fsm_using_function (work@fsm_using_function), file:${SURELOG_DIR}/tests/FSMFunction/top.sv, line:6:1, endln:94:10 |vpiPort: \_port: (gnt_0), line:11:1, endln:11:6 |vpiParent: - \_module: work@fsm_using_function (work@fsm_using_function), file:${SURELOG_DIR}/tests/FSMFunction/top.sv, line:6:1, endln:94:10 + \_module_inst: work@fsm_using_function (work@fsm_using_function), file:${SURELOG_DIR}/tests/FSMFunction/top.sv, line:6:1, endln:94:10 |vpiName:gnt_0 |vpiDirection:2 |vpiLowConn: @@ -3680,11 +3680,11 @@ design: (work@fsm_using_function) |vpiTypedef: \_logic_typespec: , line:17:9, endln:17:9 |vpiInstance: - \_module: work@fsm_using_function (work@fsm_using_function), file:${SURELOG_DIR}/tests/FSMFunction/top.sv, line:6:1, endln:94:10 + \_module_inst: work@fsm_using_function (work@fsm_using_function), file:${SURELOG_DIR}/tests/FSMFunction/top.sv, line:6:1, endln:94:10 |vpiPort: \_port: (gnt_1), line:12:1, endln:12:6 |vpiParent: - \_module: work@fsm_using_function (work@fsm_using_function), file:${SURELOG_DIR}/tests/FSMFunction/top.sv, line:6:1, endln:94:10 + \_module_inst: work@fsm_using_function (work@fsm_using_function), file:${SURELOG_DIR}/tests/FSMFunction/top.sv, line:6:1, endln:94:10 |vpiName:gnt_1 |vpiDirection:2 |vpiLowConn: @@ -3698,11 +3698,11 @@ design: (work@fsm_using_function) |vpiTypedef: \_logic_typespec: , line:17:9, endln:17:9 |vpiInstance: - \_module: work@fsm_using_function (work@fsm_using_function), file:${SURELOG_DIR}/tests/FSMFunction/top.sv, line:6:1, endln:94:10 + \_module_inst: work@fsm_using_function (work@fsm_using_function), file:${SURELOG_DIR}/tests/FSMFunction/top.sv, line:6:1, endln:94:10 |vpiProcess: \_always: , line:57:1, endln:64:4 |vpiParent: - \_module: work@fsm_using_function (work@fsm_using_function), file:${SURELOG_DIR}/tests/FSMFunction/top.sv, line:6:1, endln:94:10 + \_module_inst: work@fsm_using_function (work@fsm_using_function), file:${SURELOG_DIR}/tests/FSMFunction/top.sv, line:6:1, endln:94:10 |vpiStmt: \_event_control: , line:57:8, endln:57:25 |vpiParent: @@ -3811,7 +3811,7 @@ design: (work@fsm_using_function) |vpiProcess: \_always: , line:66:1, endln:92:4 |vpiParent: - \_module: work@fsm_using_function (work@fsm_using_function), file:${SURELOG_DIR}/tests/FSMFunction/top.sv, line:6:1, endln:94:10 + \_module_inst: work@fsm_using_function (work@fsm_using_function), file:${SURELOG_DIR}/tests/FSMFunction/top.sv, line:6:1, endln:94:10 |vpiStmt: \_event_control: , line:66:8, endln:66:25 |vpiParent: @@ -4141,7 +4141,7 @@ design: (work@fsm_using_function) |vpiContAssign: \_cont_assign: , line:29:8, endln:29:54 |vpiParent: - \_module: work@fsm_using_function (work@fsm_using_function), file:${SURELOG_DIR}/tests/FSMFunction/top.sv, line:6:1, endln:94:10 + \_module_inst: work@fsm_using_function (work@fsm_using_function), file:${SURELOG_DIR}/tests/FSMFunction/top.sv, line:6:1, endln:94:10 |vpiRhs: \_func_call: (fsm_function), line:29:21, endln:29:54 |vpiParent: diff --git a/tests/FSMSingleAlways/FSMSingleAlways.log b/tests/FSMSingleAlways/FSMSingleAlways.log index fec858f53b..728c2a005f 100644 --- a/tests/FSMSingleAlways/FSMSingleAlways.log +++ b/tests/FSMSingleAlways/FSMSingleAlways.log @@ -903,7 +903,7 @@ io_decl 11 logic_net 16 logic_typespec 12 logic_var 1 -module 5 +module_inst 5 named_begin 1 operation 10 package 2 @@ -940,7 +940,7 @@ io_decl 22 logic_net 16 logic_typespec 12 logic_var 1 -module 5 +module_inst 5 named_begin 2 operation 16 package 2 @@ -1439,14 +1439,14 @@ design: (work@fsm_using_single_always) \_int_typespec: |vpiSigned:1 |uhdmallModules: -\_module: work@fsm_using_single_always (work@fsm_using_single_always), file:${SURELOG_DIR}/tests/FSMSingleAlways/top.sv, line:7:1, endln:63:10 +\_module_inst: work@fsm_using_single_always (work@fsm_using_single_always), file:${SURELOG_DIR}/tests/FSMSingleAlways/top.sv, line:7:1, endln:63:10 |vpiParent: \_design: (work@fsm_using_single_always) |vpiFullName:work@fsm_using_single_always |vpiParameter: \_parameter: (work@fsm_using_single_always.SIZE), line:24:11, endln:24:15 |vpiParent: - \_module: work@fsm_using_single_always (work@fsm_using_single_always), file:${SURELOG_DIR}/tests/FSMSingleAlways/top.sv, line:7:1, endln:63:10 + \_module_inst: work@fsm_using_single_always (work@fsm_using_single_always), file:${SURELOG_DIR}/tests/FSMSingleAlways/top.sv, line:7:1, endln:63:10 |UINT:3 |vpiTypespec: \_int_typespec: @@ -1455,7 +1455,7 @@ design: (work@fsm_using_single_always) |vpiParameter: \_parameter: (work@fsm_using_single_always.IDLE), line:25:11, endln:25:15 |vpiParent: - \_module: work@fsm_using_single_always (work@fsm_using_single_always), file:${SURELOG_DIR}/tests/FSMSingleAlways/top.sv, line:7:1, endln:63:10 + \_module_inst: work@fsm_using_single_always (work@fsm_using_single_always), file:${SURELOG_DIR}/tests/FSMSingleAlways/top.sv, line:7:1, endln:63:10 |BIN:001 |vpiTypespec: \_int_typespec: @@ -1472,7 +1472,7 @@ design: (work@fsm_using_single_always) |vpiParameter: \_parameter: (work@fsm_using_single_always.GNT0), line:25:26, endln:25:30 |vpiParent: - \_module: work@fsm_using_single_always (work@fsm_using_single_always), file:${SURELOG_DIR}/tests/FSMSingleAlways/top.sv, line:7:1, endln:63:10 + \_module_inst: work@fsm_using_single_always (work@fsm_using_single_always), file:${SURELOG_DIR}/tests/FSMSingleAlways/top.sv, line:7:1, endln:63:10 |BIN:010 |vpiTypespec: \_int_typespec: @@ -1489,7 +1489,7 @@ design: (work@fsm_using_single_always) |vpiParameter: \_parameter: (work@fsm_using_single_always.GNT1), line:25:40, endln:25:44 |vpiParent: - \_module: work@fsm_using_single_always (work@fsm_using_single_always), file:${SURELOG_DIR}/tests/FSMSingleAlways/top.sv, line:7:1, endln:63:10 + \_module_inst: work@fsm_using_single_always (work@fsm_using_single_always), file:${SURELOG_DIR}/tests/FSMSingleAlways/top.sv, line:7:1, endln:63:10 |BIN:100 |vpiTypespec: \_int_typespec: @@ -1506,7 +1506,7 @@ design: (work@fsm_using_single_always) |vpiParamAssign: \_param_assign: , line:24:11, endln:24:19 |vpiParent: - \_module: work@fsm_using_single_always (work@fsm_using_single_always), file:${SURELOG_DIR}/tests/FSMSingleAlways/top.sv, line:7:1, endln:63:10 + \_module_inst: work@fsm_using_single_always (work@fsm_using_single_always), file:${SURELOG_DIR}/tests/FSMSingleAlways/top.sv, line:7:1, endln:63:10 |vpiRhs: \_constant: , line:24:18, endln:24:19 |vpiDecompile:3 @@ -1520,7 +1520,7 @@ design: (work@fsm_using_single_always) |vpiParamAssign: \_param_assign: , line:25:11, endln:25:25 |vpiParent: - \_module: work@fsm_using_single_always (work@fsm_using_single_always), file:${SURELOG_DIR}/tests/FSMSingleAlways/top.sv, line:7:1, endln:63:10 + \_module_inst: work@fsm_using_single_always (work@fsm_using_single_always), file:${SURELOG_DIR}/tests/FSMSingleAlways/top.sv, line:7:1, endln:63:10 |vpiRhs: \_constant: , line:25:19, endln:25:25 |vpiDecompile:3'b001 @@ -1534,7 +1534,7 @@ design: (work@fsm_using_single_always) |vpiParamAssign: \_param_assign: , line:25:26, endln:25:39 |vpiParent: - \_module: work@fsm_using_single_always (work@fsm_using_single_always), file:${SURELOG_DIR}/tests/FSMSingleAlways/top.sv, line:7:1, endln:63:10 + \_module_inst: work@fsm_using_single_always (work@fsm_using_single_always), file:${SURELOG_DIR}/tests/FSMSingleAlways/top.sv, line:7:1, endln:63:10 |vpiRhs: \_constant: , line:25:33, endln:25:39 |vpiDecompile:3'b010 @@ -1548,7 +1548,7 @@ design: (work@fsm_using_single_always) |vpiParamAssign: \_param_assign: , line:25:40, endln:25:53 |vpiParent: - \_module: work@fsm_using_single_always (work@fsm_using_single_always), file:${SURELOG_DIR}/tests/FSMSingleAlways/top.sv, line:7:1, endln:63:10 + \_module_inst: work@fsm_using_single_always (work@fsm_using_single_always), file:${SURELOG_DIR}/tests/FSMSingleAlways/top.sv, line:7:1, endln:63:10 |vpiRhs: \_constant: , line:25:47, endln:25:53 |vpiDecompile:3'b100 @@ -1563,63 +1563,63 @@ design: (work@fsm_using_single_always) |vpiNet: \_logic_net: (work@fsm_using_single_always.clock), line:20:9, endln:20:14 |vpiParent: - \_module: work@fsm_using_single_always (work@fsm_using_single_always), file:${SURELOG_DIR}/tests/FSMSingleAlways/top.sv, line:7:1, endln:63:10 + \_module_inst: work@fsm_using_single_always (work@fsm_using_single_always), file:${SURELOG_DIR}/tests/FSMSingleAlways/top.sv, line:7:1, endln:63:10 |vpiName:clock |vpiFullName:work@fsm_using_single_always.clock |vpiNetType:1 |vpiNet: \_logic_net: (work@fsm_using_single_always.reset), line:20:15, endln:20:20 |vpiParent: - \_module: work@fsm_using_single_always (work@fsm_using_single_always), file:${SURELOG_DIR}/tests/FSMSingleAlways/top.sv, line:7:1, endln:63:10 + \_module_inst: work@fsm_using_single_always (work@fsm_using_single_always), file:${SURELOG_DIR}/tests/FSMSingleAlways/top.sv, line:7:1, endln:63:10 |vpiName:reset |vpiFullName:work@fsm_using_single_always.reset |vpiNetType:1 |vpiNet: \_logic_net: (work@fsm_using_single_always.req_0), line:20:21, endln:20:26 |vpiParent: - \_module: work@fsm_using_single_always (work@fsm_using_single_always), file:${SURELOG_DIR}/tests/FSMSingleAlways/top.sv, line:7:1, endln:63:10 + \_module_inst: work@fsm_using_single_always (work@fsm_using_single_always), file:${SURELOG_DIR}/tests/FSMSingleAlways/top.sv, line:7:1, endln:63:10 |vpiName:req_0 |vpiFullName:work@fsm_using_single_always.req_0 |vpiNetType:1 |vpiNet: \_logic_net: (work@fsm_using_single_always.req_1), line:20:27, endln:20:32 |vpiParent: - \_module: work@fsm_using_single_always (work@fsm_using_single_always), file:${SURELOG_DIR}/tests/FSMSingleAlways/top.sv, line:7:1, endln:63:10 + \_module_inst: work@fsm_using_single_always (work@fsm_using_single_always), file:${SURELOG_DIR}/tests/FSMSingleAlways/top.sv, line:7:1, endln:63:10 |vpiName:req_1 |vpiFullName:work@fsm_using_single_always.req_1 |vpiNetType:1 |vpiNet: \_logic_net: (work@fsm_using_single_always.gnt_0), line:22:9, endln:22:14 |vpiParent: - \_module: work@fsm_using_single_always (work@fsm_using_single_always), file:${SURELOG_DIR}/tests/FSMSingleAlways/top.sv, line:7:1, endln:63:10 + \_module_inst: work@fsm_using_single_always (work@fsm_using_single_always), file:${SURELOG_DIR}/tests/FSMSingleAlways/top.sv, line:7:1, endln:63:10 |vpiName:gnt_0 |vpiFullName:work@fsm_using_single_always.gnt_0 |vpiNetType:48 |vpiNet: \_logic_net: (work@fsm_using_single_always.gnt_1), line:22:15, endln:22:20 |vpiParent: - \_module: work@fsm_using_single_always (work@fsm_using_single_always), file:${SURELOG_DIR}/tests/FSMSingleAlways/top.sv, line:7:1, endln:63:10 + \_module_inst: work@fsm_using_single_always (work@fsm_using_single_always), file:${SURELOG_DIR}/tests/FSMSingleAlways/top.sv, line:7:1, endln:63:10 |vpiName:gnt_1 |vpiFullName:work@fsm_using_single_always.gnt_1 |vpiNetType:48 |vpiNet: \_logic_net: (work@fsm_using_single_always.state), line:27:27, endln:27:32 |vpiParent: - \_module: work@fsm_using_single_always (work@fsm_using_single_always), file:${SURELOG_DIR}/tests/FSMSingleAlways/top.sv, line:7:1, endln:63:10 + \_module_inst: work@fsm_using_single_always (work@fsm_using_single_always), file:${SURELOG_DIR}/tests/FSMSingleAlways/top.sv, line:7:1, endln:63:10 |vpiName:state |vpiFullName:work@fsm_using_single_always.state |vpiNetType:48 |vpiNet: \_logic_net: (work@fsm_using_single_always.next_state), line:28:27, endln:28:37 |vpiParent: - \_module: work@fsm_using_single_always (work@fsm_using_single_always), file:${SURELOG_DIR}/tests/FSMSingleAlways/top.sv, line:7:1, endln:63:10 + \_module_inst: work@fsm_using_single_always (work@fsm_using_single_always), file:${SURELOG_DIR}/tests/FSMSingleAlways/top.sv, line:7:1, endln:63:10 |vpiName:next_state |vpiFullName:work@fsm_using_single_always.next_state |vpiNetType:48 |vpiPort: \_port: (clock), line:8:1, endln:8:6 |vpiParent: - \_module: work@fsm_using_single_always (work@fsm_using_single_always), file:${SURELOG_DIR}/tests/FSMSingleAlways/top.sv, line:7:1, endln:63:10 + \_module_inst: work@fsm_using_single_always (work@fsm_using_single_always), file:${SURELOG_DIR}/tests/FSMSingleAlways/top.sv, line:7:1, endln:63:10 |vpiName:clock |vpiDirection:1 |vpiLowConn: @@ -1631,7 +1631,7 @@ design: (work@fsm_using_single_always) |vpiPort: \_port: (reset), line:9:1, endln:9:6 |vpiParent: - \_module: work@fsm_using_single_always (work@fsm_using_single_always), file:${SURELOG_DIR}/tests/FSMSingleAlways/top.sv, line:7:1, endln:63:10 + \_module_inst: work@fsm_using_single_always (work@fsm_using_single_always), file:${SURELOG_DIR}/tests/FSMSingleAlways/top.sv, line:7:1, endln:63:10 |vpiName:reset |vpiDirection:1 |vpiLowConn: @@ -1643,7 +1643,7 @@ design: (work@fsm_using_single_always) |vpiPort: \_port: (req_0), line:10:1, endln:10:6 |vpiParent: - \_module: work@fsm_using_single_always (work@fsm_using_single_always), file:${SURELOG_DIR}/tests/FSMSingleAlways/top.sv, line:7:1, endln:63:10 + \_module_inst: work@fsm_using_single_always (work@fsm_using_single_always), file:${SURELOG_DIR}/tests/FSMSingleAlways/top.sv, line:7:1, endln:63:10 |vpiName:req_0 |vpiDirection:1 |vpiLowConn: @@ -1655,7 +1655,7 @@ design: (work@fsm_using_single_always) |vpiPort: \_port: (req_1), line:11:1, endln:11:6 |vpiParent: - \_module: work@fsm_using_single_always (work@fsm_using_single_always), file:${SURELOG_DIR}/tests/FSMSingleAlways/top.sv, line:7:1, endln:63:10 + \_module_inst: work@fsm_using_single_always (work@fsm_using_single_always), file:${SURELOG_DIR}/tests/FSMSingleAlways/top.sv, line:7:1, endln:63:10 |vpiName:req_1 |vpiDirection:1 |vpiLowConn: @@ -1667,7 +1667,7 @@ design: (work@fsm_using_single_always) |vpiPort: \_port: (gnt_0), line:12:1, endln:12:6 |vpiParent: - \_module: work@fsm_using_single_always (work@fsm_using_single_always), file:${SURELOG_DIR}/tests/FSMSingleAlways/top.sv, line:7:1, endln:63:10 + \_module_inst: work@fsm_using_single_always (work@fsm_using_single_always), file:${SURELOG_DIR}/tests/FSMSingleAlways/top.sv, line:7:1, endln:63:10 |vpiName:gnt_0 |vpiDirection:2 |vpiLowConn: @@ -1679,7 +1679,7 @@ design: (work@fsm_using_single_always) |vpiPort: \_port: (gnt_1), line:13:1, endln:13:6 |vpiParent: - \_module: work@fsm_using_single_always (work@fsm_using_single_always), file:${SURELOG_DIR}/tests/FSMSingleAlways/top.sv, line:7:1, endln:63:10 + \_module_inst: work@fsm_using_single_always (work@fsm_using_single_always), file:${SURELOG_DIR}/tests/FSMSingleAlways/top.sv, line:7:1, endln:63:10 |vpiName:gnt_1 |vpiDirection:2 |vpiLowConn: @@ -1691,7 +1691,7 @@ design: (work@fsm_using_single_always) |vpiProcess: \_always: , line:30:1, endln:61:4 |vpiParent: - \_module: work@fsm_using_single_always (work@fsm_using_single_always), file:${SURELOG_DIR}/tests/FSMSingleAlways/top.sv, line:7:1, endln:63:10 + \_module_inst: work@fsm_using_single_always (work@fsm_using_single_always), file:${SURELOG_DIR}/tests/FSMSingleAlways/top.sv, line:7:1, endln:63:10 |vpiStmt: \_event_control: , line:30:8, endln:30:25 |vpiParent: @@ -2271,12 +2271,12 @@ design: (work@fsm_using_single_always) |#1 |vpiAlwaysType:1 |uhdmtopModules: -\_module: work@fsm_using_single_always (work@fsm_using_single_always), file:${SURELOG_DIR}/tests/FSMSingleAlways/top.sv, line:7:1, endln:63:10 +\_module_inst: work@fsm_using_single_always (work@fsm_using_single_always), file:${SURELOG_DIR}/tests/FSMSingleAlways/top.sv, line:7:1, endln:63:10 |vpiName:work@fsm_using_single_always |vpiParameter: \_parameter: (work@fsm_using_single_always.SIZE), line:24:11, endln:24:15 |vpiParent: - \_module: work@fsm_using_single_always (work@fsm_using_single_always), file:${SURELOG_DIR}/tests/FSMSingleAlways/top.sv, line:7:1, endln:63:10 + \_module_inst: work@fsm_using_single_always (work@fsm_using_single_always), file:${SURELOG_DIR}/tests/FSMSingleAlways/top.sv, line:7:1, endln:63:10 |UINT:3 |vpiTypespec: \_int_typespec: @@ -2287,7 +2287,7 @@ design: (work@fsm_using_single_always) |vpiParameter: \_parameter: (work@fsm_using_single_always.IDLE), line:25:11, endln:25:15 |vpiParent: - \_module: work@fsm_using_single_always (work@fsm_using_single_always), file:${SURELOG_DIR}/tests/FSMSingleAlways/top.sv, line:7:1, endln:63:10 + \_module_inst: work@fsm_using_single_always (work@fsm_using_single_always), file:${SURELOG_DIR}/tests/FSMSingleAlways/top.sv, line:7:1, endln:63:10 |BIN:001 |vpiTypespec: \_int_typespec: @@ -2312,7 +2312,7 @@ design: (work@fsm_using_single_always) |vpiParameter: \_parameter: (work@fsm_using_single_always.GNT0), line:25:26, endln:25:30 |vpiParent: - \_module: work@fsm_using_single_always (work@fsm_using_single_always), file:${SURELOG_DIR}/tests/FSMSingleAlways/top.sv, line:7:1, endln:63:10 + \_module_inst: work@fsm_using_single_always (work@fsm_using_single_always), file:${SURELOG_DIR}/tests/FSMSingleAlways/top.sv, line:7:1, endln:63:10 |BIN:010 |vpiTypespec: \_int_typespec: @@ -2337,7 +2337,7 @@ design: (work@fsm_using_single_always) |vpiParameter: \_parameter: (work@fsm_using_single_always.GNT1), line:25:40, endln:25:44 |vpiParent: - \_module: work@fsm_using_single_always (work@fsm_using_single_always), file:${SURELOG_DIR}/tests/FSMSingleAlways/top.sv, line:7:1, endln:63:10 + \_module_inst: work@fsm_using_single_always (work@fsm_using_single_always), file:${SURELOG_DIR}/tests/FSMSingleAlways/top.sv, line:7:1, endln:63:10 |BIN:100 |vpiTypespec: \_int_typespec: @@ -2362,7 +2362,7 @@ design: (work@fsm_using_single_always) |vpiParamAssign: \_param_assign: , line:24:11, endln:24:19 |vpiParent: - \_module: work@fsm_using_single_always (work@fsm_using_single_always), file:${SURELOG_DIR}/tests/FSMSingleAlways/top.sv, line:7:1, endln:63:10 + \_module_inst: work@fsm_using_single_always (work@fsm_using_single_always), file:${SURELOG_DIR}/tests/FSMSingleAlways/top.sv, line:7:1, endln:63:10 |vpiRhs: \_constant: , line:24:18, endln:24:19 |vpiDecompile:3 @@ -2376,7 +2376,7 @@ design: (work@fsm_using_single_always) |vpiParamAssign: \_param_assign: , line:25:11, endln:25:25 |vpiParent: - \_module: work@fsm_using_single_always (work@fsm_using_single_always), file:${SURELOG_DIR}/tests/FSMSingleAlways/top.sv, line:7:1, endln:63:10 + \_module_inst: work@fsm_using_single_always (work@fsm_using_single_always), file:${SURELOG_DIR}/tests/FSMSingleAlways/top.sv, line:7:1, endln:63:10 |vpiRhs: \_constant: , line:25:19, endln:25:25 |vpiDecompile:3'b001 @@ -2390,7 +2390,7 @@ design: (work@fsm_using_single_always) |vpiParamAssign: \_param_assign: , line:25:26, endln:25:39 |vpiParent: - \_module: work@fsm_using_single_always (work@fsm_using_single_always), file:${SURELOG_DIR}/tests/FSMSingleAlways/top.sv, line:7:1, endln:63:10 + \_module_inst: work@fsm_using_single_always (work@fsm_using_single_always), file:${SURELOG_DIR}/tests/FSMSingleAlways/top.sv, line:7:1, endln:63:10 |vpiRhs: \_constant: , line:25:33, endln:25:39 |vpiDecompile:3'b010 @@ -2404,7 +2404,7 @@ design: (work@fsm_using_single_always) |vpiParamAssign: \_param_assign: , line:25:40, endln:25:53 |vpiParent: - \_module: work@fsm_using_single_always (work@fsm_using_single_always), file:${SURELOG_DIR}/tests/FSMSingleAlways/top.sv, line:7:1, endln:63:10 + \_module_inst: work@fsm_using_single_always (work@fsm_using_single_always), file:${SURELOG_DIR}/tests/FSMSingleAlways/top.sv, line:7:1, endln:63:10 |vpiRhs: \_constant: , line:25:47, endln:25:53 |vpiDecompile:3'b100 @@ -2420,7 +2420,7 @@ design: (work@fsm_using_single_always) |vpiNet: \_logic_net: (work@fsm_using_single_always.clock), line:20:9, endln:20:14 |vpiParent: - \_module: work@fsm_using_single_always (work@fsm_using_single_always), file:${SURELOG_DIR}/tests/FSMSingleAlways/top.sv, line:7:1, endln:63:10 + \_module_inst: work@fsm_using_single_always (work@fsm_using_single_always), file:${SURELOG_DIR}/tests/FSMSingleAlways/top.sv, line:7:1, endln:63:10 |vpiTypespec: \_logic_typespec: , line:20:1, endln:20:5 |vpiName:clock @@ -2429,7 +2429,7 @@ design: (work@fsm_using_single_always) |vpiNet: \_logic_net: (work@fsm_using_single_always.reset), line:20:15, endln:20:20 |vpiParent: - \_module: work@fsm_using_single_always (work@fsm_using_single_always), file:${SURELOG_DIR}/tests/FSMSingleAlways/top.sv, line:7:1, endln:63:10 + \_module_inst: work@fsm_using_single_always (work@fsm_using_single_always), file:${SURELOG_DIR}/tests/FSMSingleAlways/top.sv, line:7:1, endln:63:10 |vpiTypespec: \_logic_typespec: , line:20:1, endln:20:5 |vpiName:reset @@ -2438,7 +2438,7 @@ design: (work@fsm_using_single_always) |vpiNet: \_logic_net: (work@fsm_using_single_always.req_0), line:20:21, endln:20:26 |vpiParent: - \_module: work@fsm_using_single_always (work@fsm_using_single_always), file:${SURELOG_DIR}/tests/FSMSingleAlways/top.sv, line:7:1, endln:63:10 + \_module_inst: work@fsm_using_single_always (work@fsm_using_single_always), file:${SURELOG_DIR}/tests/FSMSingleAlways/top.sv, line:7:1, endln:63:10 |vpiTypespec: \_logic_typespec: , line:20:1, endln:20:5 |vpiName:req_0 @@ -2447,7 +2447,7 @@ design: (work@fsm_using_single_always) |vpiNet: \_logic_net: (work@fsm_using_single_always.req_1), line:20:27, endln:20:32 |vpiParent: - \_module: work@fsm_using_single_always (work@fsm_using_single_always), file:${SURELOG_DIR}/tests/FSMSingleAlways/top.sv, line:7:1, endln:63:10 + \_module_inst: work@fsm_using_single_always (work@fsm_using_single_always), file:${SURELOG_DIR}/tests/FSMSingleAlways/top.sv, line:7:1, endln:63:10 |vpiTypespec: \_logic_typespec: , line:20:1, endln:20:5 |vpiName:req_1 @@ -2456,7 +2456,7 @@ design: (work@fsm_using_single_always) |vpiNet: \_logic_net: (work@fsm_using_single_always.gnt_0), line:22:9, endln:22:14 |vpiParent: - \_module: work@fsm_using_single_always (work@fsm_using_single_always), file:${SURELOG_DIR}/tests/FSMSingleAlways/top.sv, line:7:1, endln:63:10 + \_module_inst: work@fsm_using_single_always (work@fsm_using_single_always), file:${SURELOG_DIR}/tests/FSMSingleAlways/top.sv, line:7:1, endln:63:10 |vpiTypespec: \_logic_typespec: , line:22:1, endln:22:4 |vpiName:gnt_0 @@ -2465,7 +2465,7 @@ design: (work@fsm_using_single_always) |vpiNet: \_logic_net: (work@fsm_using_single_always.gnt_1), line:22:15, endln:22:20 |vpiParent: - \_module: work@fsm_using_single_always (work@fsm_using_single_always), file:${SURELOG_DIR}/tests/FSMSingleAlways/top.sv, line:7:1, endln:63:10 + \_module_inst: work@fsm_using_single_always (work@fsm_using_single_always), file:${SURELOG_DIR}/tests/FSMSingleAlways/top.sv, line:7:1, endln:63:10 |vpiTypespec: \_logic_typespec: , line:22:1, endln:22:4 |vpiName:gnt_1 @@ -2474,7 +2474,7 @@ design: (work@fsm_using_single_always) |vpiNet: \_logic_net: (work@fsm_using_single_always.state), line:27:27, endln:27:32 |vpiParent: - \_module: work@fsm_using_single_always (work@fsm_using_single_always), file:${SURELOG_DIR}/tests/FSMSingleAlways/top.sv, line:7:1, endln:63:10 + \_module_inst: work@fsm_using_single_always (work@fsm_using_single_always), file:${SURELOG_DIR}/tests/FSMSingleAlways/top.sv, line:7:1, endln:63:10 |vpiTypespec: \_logic_typespec: , line:27:1, endln:27:17 |vpiRange: @@ -2501,7 +2501,7 @@ design: (work@fsm_using_single_always) |vpiNet: \_logic_net: (work@fsm_using_single_always.next_state), line:28:27, endln:28:37 |vpiParent: - \_module: work@fsm_using_single_always (work@fsm_using_single_always), file:${SURELOG_DIR}/tests/FSMSingleAlways/top.sv, line:7:1, endln:63:10 + \_module_inst: work@fsm_using_single_always (work@fsm_using_single_always), file:${SURELOG_DIR}/tests/FSMSingleAlways/top.sv, line:7:1, endln:63:10 |vpiTypespec: \_logic_typespec: , line:28:1, endln:28:17 |vpiRange: @@ -2529,7 +2529,7 @@ design: (work@fsm_using_single_always) |vpiPort: \_port: (clock), line:8:1, endln:8:6 |vpiParent: - \_module: work@fsm_using_single_always (work@fsm_using_single_always), file:${SURELOG_DIR}/tests/FSMSingleAlways/top.sv, line:7:1, endln:63:10 + \_module_inst: work@fsm_using_single_always (work@fsm_using_single_always), file:${SURELOG_DIR}/tests/FSMSingleAlways/top.sv, line:7:1, endln:63:10 |vpiName:clock |vpiDirection:1 |vpiLowConn: @@ -2543,11 +2543,11 @@ design: (work@fsm_using_single_always) |vpiTypedef: \_logic_typespec: , line:16:9, endln:16:9 |vpiInstance: - \_module: work@fsm_using_single_always (work@fsm_using_single_always), file:${SURELOG_DIR}/tests/FSMSingleAlways/top.sv, line:7:1, endln:63:10 + \_module_inst: work@fsm_using_single_always (work@fsm_using_single_always), file:${SURELOG_DIR}/tests/FSMSingleAlways/top.sv, line:7:1, endln:63:10 |vpiPort: \_port: (reset), line:9:1, endln:9:6 |vpiParent: - \_module: work@fsm_using_single_always (work@fsm_using_single_always), file:${SURELOG_DIR}/tests/FSMSingleAlways/top.sv, line:7:1, endln:63:10 + \_module_inst: work@fsm_using_single_always (work@fsm_using_single_always), file:${SURELOG_DIR}/tests/FSMSingleAlways/top.sv, line:7:1, endln:63:10 |vpiName:reset |vpiDirection:1 |vpiLowConn: @@ -2561,11 +2561,11 @@ design: (work@fsm_using_single_always) |vpiTypedef: \_logic_typespec: , line:16:9, endln:16:9 |vpiInstance: - \_module: work@fsm_using_single_always (work@fsm_using_single_always), file:${SURELOG_DIR}/tests/FSMSingleAlways/top.sv, line:7:1, endln:63:10 + \_module_inst: work@fsm_using_single_always (work@fsm_using_single_always), file:${SURELOG_DIR}/tests/FSMSingleAlways/top.sv, line:7:1, endln:63:10 |vpiPort: \_port: (req_0), line:10:1, endln:10:6 |vpiParent: - \_module: work@fsm_using_single_always (work@fsm_using_single_always), file:${SURELOG_DIR}/tests/FSMSingleAlways/top.sv, line:7:1, endln:63:10 + \_module_inst: work@fsm_using_single_always (work@fsm_using_single_always), file:${SURELOG_DIR}/tests/FSMSingleAlways/top.sv, line:7:1, endln:63:10 |vpiName:req_0 |vpiDirection:1 |vpiLowConn: @@ -2579,11 +2579,11 @@ design: (work@fsm_using_single_always) |vpiTypedef: \_logic_typespec: , line:16:9, endln:16:9 |vpiInstance: - \_module: work@fsm_using_single_always (work@fsm_using_single_always), file:${SURELOG_DIR}/tests/FSMSingleAlways/top.sv, line:7:1, endln:63:10 + \_module_inst: work@fsm_using_single_always (work@fsm_using_single_always), file:${SURELOG_DIR}/tests/FSMSingleAlways/top.sv, line:7:1, endln:63:10 |vpiPort: \_port: (req_1), line:11:1, endln:11:6 |vpiParent: - \_module: work@fsm_using_single_always (work@fsm_using_single_always), file:${SURELOG_DIR}/tests/FSMSingleAlways/top.sv, line:7:1, endln:63:10 + \_module_inst: work@fsm_using_single_always (work@fsm_using_single_always), file:${SURELOG_DIR}/tests/FSMSingleAlways/top.sv, line:7:1, endln:63:10 |vpiName:req_1 |vpiDirection:1 |vpiLowConn: @@ -2597,11 +2597,11 @@ design: (work@fsm_using_single_always) |vpiTypedef: \_logic_typespec: , line:16:9, endln:16:9 |vpiInstance: - \_module: work@fsm_using_single_always (work@fsm_using_single_always), file:${SURELOG_DIR}/tests/FSMSingleAlways/top.sv, line:7:1, endln:63:10 + \_module_inst: work@fsm_using_single_always (work@fsm_using_single_always), file:${SURELOG_DIR}/tests/FSMSingleAlways/top.sv, line:7:1, endln:63:10 |vpiPort: \_port: (gnt_0), line:12:1, endln:12:6 |vpiParent: - \_module: work@fsm_using_single_always (work@fsm_using_single_always), file:${SURELOG_DIR}/tests/FSMSingleAlways/top.sv, line:7:1, endln:63:10 + \_module_inst: work@fsm_using_single_always (work@fsm_using_single_always), file:${SURELOG_DIR}/tests/FSMSingleAlways/top.sv, line:7:1, endln:63:10 |vpiName:gnt_0 |vpiDirection:2 |vpiLowConn: @@ -2615,11 +2615,11 @@ design: (work@fsm_using_single_always) |vpiTypedef: \_logic_typespec: , line:18:9, endln:18:9 |vpiInstance: - \_module: work@fsm_using_single_always (work@fsm_using_single_always), file:${SURELOG_DIR}/tests/FSMSingleAlways/top.sv, line:7:1, endln:63:10 + \_module_inst: work@fsm_using_single_always (work@fsm_using_single_always), file:${SURELOG_DIR}/tests/FSMSingleAlways/top.sv, line:7:1, endln:63:10 |vpiPort: \_port: (gnt_1), line:13:1, endln:13:6 |vpiParent: - \_module: work@fsm_using_single_always (work@fsm_using_single_always), file:${SURELOG_DIR}/tests/FSMSingleAlways/top.sv, line:7:1, endln:63:10 + \_module_inst: work@fsm_using_single_always (work@fsm_using_single_always), file:${SURELOG_DIR}/tests/FSMSingleAlways/top.sv, line:7:1, endln:63:10 |vpiName:gnt_1 |vpiDirection:2 |vpiLowConn: @@ -2633,11 +2633,11 @@ design: (work@fsm_using_single_always) |vpiTypedef: \_logic_typespec: , line:18:9, endln:18:9 |vpiInstance: - \_module: work@fsm_using_single_always (work@fsm_using_single_always), file:${SURELOG_DIR}/tests/FSMSingleAlways/top.sv, line:7:1, endln:63:10 + \_module_inst: work@fsm_using_single_always (work@fsm_using_single_always), file:${SURELOG_DIR}/tests/FSMSingleAlways/top.sv, line:7:1, endln:63:10 |vpiProcess: \_always: , line:30:1, endln:61:4 |vpiParent: - \_module: work@fsm_using_single_always (work@fsm_using_single_always), file:${SURELOG_DIR}/tests/FSMSingleAlways/top.sv, line:7:1, endln:63:10 + \_module_inst: work@fsm_using_single_always (work@fsm_using_single_always), file:${SURELOG_DIR}/tests/FSMSingleAlways/top.sv, line:7:1, endln:63:10 |vpiStmt: \_event_control: , line:30:8, endln:30:25 |vpiParent: diff --git a/tests/FileList/FileList.log b/tests/FileList/FileList.log index 717bf8343c..b42f292c3b 100644 --- a/tests/FileList/FileList.log +++ b/tests/FileList/FileList.log @@ -232,7 +232,7 @@ io_decl 2 logic_net 5 logic_typespec 7 logic_var 1 -module 6 +module_inst 6 operation 8 package 3 param_assign 4 @@ -263,7 +263,7 @@ io_decl 5 logic_net 5 logic_typespec 7 logic_var 1 -module 6 +module_inst 6 operation 16 package 3 param_assign 4 @@ -466,7 +466,7 @@ design: (work@foo) |vpiInstance: \_package: prim_util_pkg (prim_util_pkg::), file:${SURELOG_DIR}/tests/FileList/pack.sv, line:1:1, endln:7:11 |uhdmallModules: -\_module: work@foo (work@foo), file:${SURELOG_DIR}/tests/FileList/dut.sv, line:1:1, endln:11:10 +\_module_inst: work@foo (work@foo), file:${SURELOG_DIR}/tests/FileList/dut.sv, line:1:1, endln:11:10 |vpiParent: \_design: (work@foo) |vpiFullName:work@foo @@ -535,26 +535,26 @@ design: (work@foo) |vpiNet: \_logic_net: (work@foo.clk), line:2:11, endln:2:14 |vpiParent: - \_module: work@foo (work@foo), file:${SURELOG_DIR}/tests/FileList/dut.sv, line:1:1, endln:11:10 + \_module_inst: work@foo (work@foo), file:${SURELOG_DIR}/tests/FileList/dut.sv, line:1:1, endln:11:10 |vpiName:clk |vpiFullName:work@foo.clk |vpiNet: \_logic_net: (work@foo.out), line:3:12, endln:3:15 |vpiParent: - \_module: work@foo (work@foo), file:${SURELOG_DIR}/tests/FileList/dut.sv, line:1:1, endln:11:10 + \_module_inst: work@foo (work@foo), file:${SURELOG_DIR}/tests/FileList/dut.sv, line:1:1, endln:11:10 |vpiName:out |vpiFullName:work@foo.out |vpiNet: \_logic_net: (work@foo.a), line:6:22, endln:6:23 |vpiParent: - \_module: work@foo (work@foo), file:${SURELOG_DIR}/tests/FileList/dut.sv, line:1:1, endln:11:10 + \_module_inst: work@foo (work@foo), file:${SURELOG_DIR}/tests/FileList/dut.sv, line:1:1, endln:11:10 |vpiName:a |vpiFullName:work@foo.a |vpiNetType:36 |vpiPort: \_port: (clk), line:2:11, endln:2:14 |vpiParent: - \_module: work@foo (work@foo), file:${SURELOG_DIR}/tests/FileList/dut.sv, line:1:1, endln:11:10 + \_module_inst: work@foo (work@foo), file:${SURELOG_DIR}/tests/FileList/dut.sv, line:1:1, endln:11:10 |vpiName:clk |vpiDirection:1 |vpiLowConn: @@ -566,7 +566,7 @@ design: (work@foo) |vpiPort: \_port: (out), line:3:12, endln:3:15 |vpiParent: - \_module: work@foo (work@foo), file:${SURELOG_DIR}/tests/FileList/dut.sv, line:1:1, endln:11:10 + \_module_inst: work@foo (work@foo), file:${SURELOG_DIR}/tests/FileList/dut.sv, line:1:1, endln:11:10 |vpiName:out |vpiDirection:2 |vpiLowConn: @@ -578,7 +578,7 @@ design: (work@foo) |vpiProcess: \_always: , line:7:1, endln:9:4 |vpiParent: - \_module: work@foo (work@foo), file:${SURELOG_DIR}/tests/FileList/dut.sv, line:1:1, endln:11:10 + \_module_inst: work@foo (work@foo), file:${SURELOG_DIR}/tests/FileList/dut.sv, line:1:1, endln:11:10 |vpiStmt: \_event_control: , line:7:8, endln:7:22 |vpiParent: @@ -639,7 +639,7 @@ design: (work@foo) |vpiContAssign: \_cont_assign: , line:10:8, endln:10:18 |vpiParent: - \_module: work@foo (work@foo), file:${SURELOG_DIR}/tests/FileList/dut.sv, line:1:1, endln:11:10 + \_module_inst: work@foo (work@foo), file:${SURELOG_DIR}/tests/FileList/dut.sv, line:1:1, endln:11:10 |vpiRhs: \_bit_select: (work@foo.a), line:10:14, endln:10:18 |vpiParent: @@ -667,12 +667,12 @@ design: (work@foo) |vpiActual: \_logic_net: (work@foo.out), line:3:12, endln:3:15 |uhdmtopModules: -\_module: work@foo (work@foo), file:${SURELOG_DIR}/tests/FileList/dut.sv, line:1:1, endln:11:10 +\_module_inst: work@foo (work@foo), file:${SURELOG_DIR}/tests/FileList/dut.sv, line:1:1, endln:11:10 |vpiName:work@foo |vpiVariables: \_logic_var: (work@foo.a), line:6:22, endln:6:23 |vpiParent: - \_module: work@foo (work@foo), file:${SURELOG_DIR}/tests/FileList/dut.sv, line:1:1, endln:11:10 + \_module_inst: work@foo (work@foo), file:${SURELOG_DIR}/tests/FileList/dut.sv, line:1:1, endln:11:10 |vpiTypespec: \_logic_typespec: , line:6:1, endln:6:21 |vpiRange: @@ -721,7 +721,7 @@ design: (work@foo) |vpiTaskFunc: \_function: (prim_util_pkg::vbits), line:3:2, endln:5:14 |vpiParent: - \_module: work@foo (work@foo), file:${SURELOG_DIR}/tests/FileList/dut.sv, line:1:1, endln:11:10 + \_module_inst: work@foo (work@foo), file:${SURELOG_DIR}/tests/FileList/dut.sv, line:1:1, endln:11:10 |vpiName:vbits |vpiFullName:prim_util_pkg::vbits |vpiVisibility:1 @@ -729,7 +729,7 @@ design: (work@foo) |vpiReturn: \_integer_var: , line:3:21, endln:3:28 |vpiParent: - \_module: work@foo (work@foo), file:${SURELOG_DIR}/tests/FileList/dut.sv, line:1:1, endln:11:10 + \_module_inst: work@foo (work@foo), file:${SURELOG_DIR}/tests/FileList/dut.sv, line:1:1, endln:11:10 |vpiIODecl: \_io_decl: (value), line:3:43, endln:3:48 |vpiParent: @@ -778,11 +778,11 @@ design: (work@foo) \_io_decl: (value), line:3:43, endln:3:48 |vpiName:$clog2 |vpiInstance: - \_module: work@foo (work@foo), file:${SURELOG_DIR}/tests/FileList/dut.sv, line:1:1, endln:11:10 + \_module_inst: work@foo (work@foo), file:${SURELOG_DIR}/tests/FileList/dut.sv, line:1:1, endln:11:10 |vpiNet: \_logic_net: (work@foo.clk), line:2:11, endln:2:14 |vpiParent: - \_module: work@foo (work@foo), file:${SURELOG_DIR}/tests/FileList/dut.sv, line:1:1, endln:11:10 + \_module_inst: work@foo (work@foo), file:${SURELOG_DIR}/tests/FileList/dut.sv, line:1:1, endln:11:10 |vpiTypespec: \_logic_typespec: , line:2:11, endln:2:11 |vpiName:clk @@ -790,7 +790,7 @@ design: (work@foo) |vpiNet: \_logic_net: (work@foo.out), line:3:12, endln:3:15 |vpiParent: - \_module: work@foo (work@foo), file:${SURELOG_DIR}/tests/FileList/dut.sv, line:1:1, endln:11:10 + \_module_inst: work@foo (work@foo), file:${SURELOG_DIR}/tests/FileList/dut.sv, line:1:1, endln:11:10 |vpiTypespec: \_logic_typespec: , line:3:12, endln:3:12 |vpiName:out @@ -799,7 +799,7 @@ design: (work@foo) |vpiPort: \_port: (clk), line:2:11, endln:2:14 |vpiParent: - \_module: work@foo (work@foo), file:${SURELOG_DIR}/tests/FileList/dut.sv, line:1:1, endln:11:10 + \_module_inst: work@foo (work@foo), file:${SURELOG_DIR}/tests/FileList/dut.sv, line:1:1, endln:11:10 |vpiName:clk |vpiDirection:1 |vpiLowConn: @@ -813,11 +813,11 @@ design: (work@foo) |vpiTypedef: \_logic_typespec: , line:2:11, endln:2:11 |vpiInstance: - \_module: work@foo (work@foo), file:${SURELOG_DIR}/tests/FileList/dut.sv, line:1:1, endln:11:10 + \_module_inst: work@foo (work@foo), file:${SURELOG_DIR}/tests/FileList/dut.sv, line:1:1, endln:11:10 |vpiPort: \_port: (out), line:3:12, endln:3:15 |vpiParent: - \_module: work@foo (work@foo), file:${SURELOG_DIR}/tests/FileList/dut.sv, line:1:1, endln:11:10 + \_module_inst: work@foo (work@foo), file:${SURELOG_DIR}/tests/FileList/dut.sv, line:1:1, endln:11:10 |vpiName:out |vpiDirection:2 |vpiLowConn: @@ -831,11 +831,11 @@ design: (work@foo) |vpiTypedef: \_logic_typespec: , line:3:12, endln:3:12 |vpiInstance: - \_module: work@foo (work@foo), file:${SURELOG_DIR}/tests/FileList/dut.sv, line:1:1, endln:11:10 + \_module_inst: work@foo (work@foo), file:${SURELOG_DIR}/tests/FileList/dut.sv, line:1:1, endln:11:10 |vpiProcess: \_always: , line:7:1, endln:9:4 |vpiParent: - \_module: work@foo (work@foo), file:${SURELOG_DIR}/tests/FileList/dut.sv, line:1:1, endln:11:10 + \_module_inst: work@foo (work@foo), file:${SURELOG_DIR}/tests/FileList/dut.sv, line:1:1, endln:11:10 |vpiStmt: \_event_control: , line:7:8, endln:7:22 |vpiParent: @@ -890,7 +890,7 @@ design: (work@foo) |vpiContAssign: \_cont_assign: , line:10:8, endln:10:18 |vpiParent: - \_module: work@foo (work@foo), file:${SURELOG_DIR}/tests/FileList/dut.sv, line:1:1, endln:11:10 + \_module_inst: work@foo (work@foo), file:${SURELOG_DIR}/tests/FileList/dut.sv, line:1:1, endln:11:10 |vpiRhs: \_bit_select: (work@foo.a), line:10:14, endln:10:18 |vpiParent: diff --git a/tests/FileParam/FileParam.log b/tests/FileParam/FileParam.log index b012a17b83..3126c34821 100644 --- a/tests/FileParam/FileParam.log +++ b/tests/FileParam/FileParam.log @@ -101,7 +101,7 @@ design 1 enum_const 2 enum_typespec 1 int_typespec 7 -module 3 +module_inst 3 operation 5 param_assign 4 parameter 4 @@ -115,7 +115,7 @@ design 1 enum_const 2 enum_typespec 1 int_typespec 7 -module 3 +module_inst 3 operation 5 param_assign 4 parameter 4 @@ -134,7 +134,7 @@ design: (work@top) |vpiElaborated:1 |vpiName:work@top |uhdmallModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/FileParam/dut.sv, line:12:1, endln:13:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/FileParam/dut.sv, line:12:1, endln:13:10 |vpiParent: \_design: (work@top) |vpiFullName:work@top @@ -207,7 +207,7 @@ design: (work@top) |vpiLhs: \_parameter: (P2), line:3:12, endln:3:14 |uhdmtopModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/FileParam/dut.sv, line:12:1, endln:13:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/FileParam/dut.sv, line:12:1, endln:13:10 |vpiName:work@top |vpiDefName:work@top |vpiTop:1 diff --git a/tests/ForElab/ForElab.log b/tests/ForElab/ForElab.log index 5e69d0f8ee..952fc5c642 100644 --- a/tests/ForElab/ForElab.log +++ b/tests/ForElab/ForElab.log @@ -85,7 +85,7 @@ int_typespec 21 logic_net 15 logic_typespec 7 logic_var 1 -module 17 +module_inst 17 operation 43 package 3 param_assign 24 @@ -170,14 +170,14 @@ design: (work@tlul_socket_m1) |vpiDefName:tlul_pkg |vpiTop:1 |uhdmallModules: -\_module: work@prim_arbiter_tree (work@prim_arbiter_tree), file:${SURELOG_DIR}/tests/ForElab/top.v, line:16:1, endln:47:10 +\_module_inst: work@prim_arbiter_tree (work@prim_arbiter_tree), file:${SURELOG_DIR}/tests/ForElab/top.v, line:16:1, endln:47:10 |vpiParent: \_design: (work@tlul_socket_m1) |vpiFullName:work@prim_arbiter_tree |vpiParameter: \_parameter: (work@prim_arbiter_tree.N), line:17:26, endln:17:27 |vpiParent: - \_module: work@prim_arbiter_tree (work@prim_arbiter_tree), file:${SURELOG_DIR}/tests/ForElab/top.v, line:16:1, endln:47:10 + \_module_inst: work@prim_arbiter_tree (work@prim_arbiter_tree), file:${SURELOG_DIR}/tests/ForElab/top.v, line:16:1, endln:47:10 |UINT:4 |vpiTypespec: \_int_typespec: , line:17:13, endln:17:25 @@ -188,7 +188,7 @@ design: (work@tlul_socket_m1) |vpiParameter: \_parameter: (work@prim_arbiter_tree.DW), line:18:26, endln:18:28 |vpiParent: - \_module: work@prim_arbiter_tree (work@prim_arbiter_tree), file:${SURELOG_DIR}/tests/ForElab/top.v, line:16:1, endln:47:10 + \_module_inst: work@prim_arbiter_tree (work@prim_arbiter_tree), file:${SURELOG_DIR}/tests/ForElab/top.v, line:16:1, endln:47:10 |UINT:32 |vpiTypespec: \_int_typespec: , line:18:13, endln:18:25 @@ -199,7 +199,7 @@ design: (work@tlul_socket_m1) |vpiParameter: \_parameter: (work@prim_arbiter_tree.Lock), line:19:17, endln:19:21 |vpiParent: - \_module: work@prim_arbiter_tree (work@prim_arbiter_tree), file:${SURELOG_DIR}/tests/ForElab/top.v, line:16:1, endln:47:10 + \_module_inst: work@prim_arbiter_tree (work@prim_arbiter_tree), file:${SURELOG_DIR}/tests/ForElab/top.v, line:16:1, endln:47:10 |BIN:1 |vpiTypespec: \_bit_typespec: , line:19:13, endln:19:16 @@ -211,7 +211,7 @@ design: (work@tlul_socket_m1) |vpiParamAssign: \_param_assign: , line:17:26, endln:17:32 |vpiParent: - \_module: work@prim_arbiter_tree (work@prim_arbiter_tree), file:${SURELOG_DIR}/tests/ForElab/top.v, line:16:1, endln:47:10 + \_module_inst: work@prim_arbiter_tree (work@prim_arbiter_tree), file:${SURELOG_DIR}/tests/ForElab/top.v, line:16:1, endln:47:10 |vpiRhs: \_constant: , line:17:31, endln:17:32 |vpiDecompile:4 @@ -225,7 +225,7 @@ design: (work@tlul_socket_m1) |vpiParamAssign: \_param_assign: , line:18:26, endln:18:33 |vpiParent: - \_module: work@prim_arbiter_tree (work@prim_arbiter_tree), file:${SURELOG_DIR}/tests/ForElab/top.v, line:16:1, endln:47:10 + \_module_inst: work@prim_arbiter_tree (work@prim_arbiter_tree), file:${SURELOG_DIR}/tests/ForElab/top.v, line:16:1, endln:47:10 |vpiRhs: \_constant: , line:18:31, endln:18:33 |vpiDecompile:32 @@ -239,7 +239,7 @@ design: (work@tlul_socket_m1) |vpiParamAssign: \_param_assign: , line:19:17, endln:19:33 |vpiParent: - \_module: work@prim_arbiter_tree (work@prim_arbiter_tree), file:${SURELOG_DIR}/tests/ForElab/top.v, line:16:1, endln:47:10 + \_module_inst: work@prim_arbiter_tree (work@prim_arbiter_tree), file:${SURELOG_DIR}/tests/ForElab/top.v, line:16:1, endln:47:10 |vpiRhs: \_constant: , line:19:29, endln:19:33 |vpiDecompile:1'b1 @@ -254,19 +254,19 @@ design: (work@tlul_socket_m1) |vpiNet: \_logic_net: (work@prim_arbiter_tree.clk_i), line:21:9, endln:21:14 |vpiParent: - \_module: work@prim_arbiter_tree (work@prim_arbiter_tree), file:${SURELOG_DIR}/tests/ForElab/top.v, line:16:1, endln:47:10 + \_module_inst: work@prim_arbiter_tree (work@prim_arbiter_tree), file:${SURELOG_DIR}/tests/ForElab/top.v, line:16:1, endln:47:10 |vpiName:clk_i |vpiFullName:work@prim_arbiter_tree.clk_i |vpiNet: \_logic_net: (work@prim_arbiter_tree.rst_ni), line:22:9, endln:22:15 |vpiParent: - \_module: work@prim_arbiter_tree (work@prim_arbiter_tree), file:${SURELOG_DIR}/tests/ForElab/top.v, line:16:1, endln:47:10 + \_module_inst: work@prim_arbiter_tree (work@prim_arbiter_tree), file:${SURELOG_DIR}/tests/ForElab/top.v, line:16:1, endln:47:10 |vpiName:rst_ni |vpiFullName:work@prim_arbiter_tree.rst_ni |vpiPort: \_port: (clk_i), line:21:9, endln:21:14 |vpiParent: - \_module: work@prim_arbiter_tree (work@prim_arbiter_tree), file:${SURELOG_DIR}/tests/ForElab/top.v, line:16:1, endln:47:10 + \_module_inst: work@prim_arbiter_tree (work@prim_arbiter_tree), file:${SURELOG_DIR}/tests/ForElab/top.v, line:16:1, endln:47:10 |vpiName:clk_i |vpiDirection:1 |vpiLowConn: @@ -278,7 +278,7 @@ design: (work@tlul_socket_m1) |vpiPort: \_port: (rst_ni), line:22:9, endln:22:15 |vpiParent: - \_module: work@prim_arbiter_tree (work@prim_arbiter_tree), file:${SURELOG_DIR}/tests/ForElab/top.v, line:16:1, endln:47:10 + \_module_inst: work@prim_arbiter_tree (work@prim_arbiter_tree), file:${SURELOG_DIR}/tests/ForElab/top.v, line:16:1, endln:47:10 |vpiName:rst_ni |vpiDirection:1 |vpiLowConn: @@ -288,13 +288,13 @@ design: (work@tlul_socket_m1) |vpiTypedef: \_logic_typespec: , line:22:9, endln:22:9 |uhdmallModules: -\_module: work@tlul_socket_m1 (work@tlul_socket_m1), file:${SURELOG_DIR}/tests/ForElab/top.v, line:49:1, endln:68:10 +\_module_inst: work@tlul_socket_m1 (work@tlul_socket_m1), file:${SURELOG_DIR}/tests/ForElab/top.v, line:49:1, endln:68:10 |vpiParent: \_design: (work@tlul_socket_m1) |vpiFullName:work@tlul_socket_m1 |vpiDefName:work@tlul_socket_m1 |uhdmtopModules: -\_module: work@tlul_socket_m1 (work@tlul_socket_m1), file:${SURELOG_DIR}/tests/ForElab/top.v, line:49:1, endln:68:10 +\_module_inst: work@tlul_socket_m1 (work@tlul_socket_m1), file:${SURELOG_DIR}/tests/ForElab/top.v, line:49:1, endln:68:10 |vpiName:work@tlul_socket_m1 |vpiDefName:work@tlul_socket_m1 |vpiTop:1 @@ -302,7 +302,7 @@ design: (work@tlul_socket_m1) |vpiGenScopeArray: \_gen_scope_array: (work@tlul_socket_m1.gen_tree_arb), line:55:5, endln:61:7 |vpiParent: - \_module: work@tlul_socket_m1 (work@tlul_socket_m1), file:${SURELOG_DIR}/tests/ForElab/top.v, line:49:1, endln:68:10 + \_module_inst: work@tlul_socket_m1 (work@tlul_socket_m1), file:${SURELOG_DIR}/tests/ForElab/top.v, line:49:1, endln:68:10 |vpiName:gen_tree_arb |vpiFullName:work@tlul_socket_m1.gen_tree_arb |vpiGenScope: @@ -324,8 +324,8 @@ design: (work@tlul_socket_m1) |vpiName:rst_ni |vpiFullName:work@tlul_socket_m1.gen_tree_arb.rst_ni |vpiNetType:1 - |vpiModule: - \_module: work@prim_arbiter_tree (work@tlul_socket_m1.gen_tree_arb.u_reqarb), file:${SURELOG_DIR}/tests/ForElab/top.v, line:55:5, endln:61:7 + |vpiModuleInst: + \_module_inst: work@prim_arbiter_tree (work@tlul_socket_m1.gen_tree_arb.u_reqarb), file:${SURELOG_DIR}/tests/ForElab/top.v, line:55:5, endln:61:7 |vpiParent: \_gen_scope: (work@tlul_socket_m1.gen_tree_arb) |vpiName:u_reqarb @@ -333,7 +333,7 @@ design: (work@tlul_socket_m1) |vpiParameter: \_parameter: (work@tlul_socket_m1.gen_tree_arb.u_reqarb.N), line:17:26, endln:17:27 |vpiParent: - \_module: work@prim_arbiter_tree (work@tlul_socket_m1.gen_tree_arb.u_reqarb), file:${SURELOG_DIR}/tests/ForElab/top.v, line:55:5, endln:61:7 + \_module_inst: work@prim_arbiter_tree (work@tlul_socket_m1.gen_tree_arb.u_reqarb), file:${SURELOG_DIR}/tests/ForElab/top.v, line:55:5, endln:61:7 |UINT:4 |vpiTypespec: \_int_typespec: , line:17:13, endln:17:25 @@ -344,7 +344,7 @@ design: (work@tlul_socket_m1) |vpiParameter: \_parameter: (work@tlul_socket_m1.gen_tree_arb.u_reqarb.DW), line:18:26, endln:18:28 |vpiParent: - \_module: work@prim_arbiter_tree (work@tlul_socket_m1.gen_tree_arb.u_reqarb), file:${SURELOG_DIR}/tests/ForElab/top.v, line:55:5, endln:61:7 + \_module_inst: work@prim_arbiter_tree (work@tlul_socket_m1.gen_tree_arb.u_reqarb), file:${SURELOG_DIR}/tests/ForElab/top.v, line:55:5, endln:61:7 |UINT:32 |vpiTypespec: \_int_typespec: , line:18:13, endln:18:25 @@ -355,7 +355,7 @@ design: (work@tlul_socket_m1) |vpiParameter: \_parameter: (work@tlul_socket_m1.gen_tree_arb.u_reqarb.Lock), line:19:17, endln:19:21 |vpiParent: - \_module: work@prim_arbiter_tree (work@tlul_socket_m1.gen_tree_arb.u_reqarb), file:${SURELOG_DIR}/tests/ForElab/top.v, line:55:5, endln:61:7 + \_module_inst: work@prim_arbiter_tree (work@tlul_socket_m1.gen_tree_arb.u_reqarb), file:${SURELOG_DIR}/tests/ForElab/top.v, line:55:5, endln:61:7 |BIN:1 |vpiTypespec: \_bit_typespec: , line:19:13, endln:19:16 @@ -367,7 +367,7 @@ design: (work@tlul_socket_m1) |vpiParamAssign: \_param_assign: , line:17:26, endln:17:32 |vpiParent: - \_module: work@prim_arbiter_tree (work@tlul_socket_m1.gen_tree_arb.u_reqarb), file:${SURELOG_DIR}/tests/ForElab/top.v, line:55:5, endln:61:7 + \_module_inst: work@prim_arbiter_tree (work@tlul_socket_m1.gen_tree_arb.u_reqarb), file:${SURELOG_DIR}/tests/ForElab/top.v, line:55:5, endln:61:7 |vpiOverriden:1 |vpiRhs: \_constant: , line:17:31, endln:17:32 @@ -382,7 +382,7 @@ design: (work@tlul_socket_m1) |vpiParamAssign: \_param_assign: , line:18:26, endln:18:33 |vpiParent: - \_module: work@prim_arbiter_tree (work@tlul_socket_m1.gen_tree_arb.u_reqarb), file:${SURELOG_DIR}/tests/ForElab/top.v, line:55:5, endln:61:7 + \_module_inst: work@prim_arbiter_tree (work@tlul_socket_m1.gen_tree_arb.u_reqarb), file:${SURELOG_DIR}/tests/ForElab/top.v, line:55:5, endln:61:7 |vpiOverriden:1 |vpiRhs: \_constant: , line:18:31, endln:18:33 @@ -397,7 +397,7 @@ design: (work@tlul_socket_m1) |vpiParamAssign: \_param_assign: , line:19:17, endln:19:33 |vpiParent: - \_module: work@prim_arbiter_tree (work@tlul_socket_m1.gen_tree_arb.u_reqarb), file:${SURELOG_DIR}/tests/ForElab/top.v, line:55:5, endln:61:7 + \_module_inst: work@prim_arbiter_tree (work@tlul_socket_m1.gen_tree_arb.u_reqarb), file:${SURELOG_DIR}/tests/ForElab/top.v, line:55:5, endln:61:7 |vpiRhs: \_constant: , line:19:29, endln:19:33 |vpiDecompile:1'b1 @@ -414,7 +414,7 @@ design: (work@tlul_socket_m1) |vpiNet: \_logic_net: (work@tlul_socket_m1.gen_tree_arb.u_reqarb.clk_i), line:21:9, endln:21:14 |vpiParent: - \_module: work@prim_arbiter_tree (work@tlul_socket_m1.gen_tree_arb.u_reqarb), file:${SURELOG_DIR}/tests/ForElab/top.v, line:55:5, endln:61:7 + \_module_inst: work@prim_arbiter_tree (work@tlul_socket_m1.gen_tree_arb.u_reqarb), file:${SURELOG_DIR}/tests/ForElab/top.v, line:55:5, endln:61:7 |vpiTypespec: \_logic_typespec: , line:21:9, endln:21:9 |vpiName:clk_i @@ -422,7 +422,7 @@ design: (work@tlul_socket_m1) |vpiNet: \_logic_net: (work@tlul_socket_m1.gen_tree_arb.u_reqarb.rst_ni), line:22:9, endln:22:15 |vpiParent: - \_module: work@prim_arbiter_tree (work@tlul_socket_m1.gen_tree_arb.u_reqarb), file:${SURELOG_DIR}/tests/ForElab/top.v, line:55:5, endln:61:7 + \_module_inst: work@prim_arbiter_tree (work@tlul_socket_m1.gen_tree_arb.u_reqarb), file:${SURELOG_DIR}/tests/ForElab/top.v, line:55:5, endln:61:7 |vpiTypespec: \_logic_typespec: , line:22:9, endln:22:9 |vpiName:rst_ni @@ -430,7 +430,7 @@ design: (work@tlul_socket_m1) |vpiPort: \_port: (clk_i), line:21:9, endln:21:14 |vpiParent: - \_module: work@prim_arbiter_tree (work@tlul_socket_m1.gen_tree_arb.u_reqarb), file:${SURELOG_DIR}/tests/ForElab/top.v, line:55:5, endln:61:7 + \_module_inst: work@prim_arbiter_tree (work@tlul_socket_m1.gen_tree_arb.u_reqarb), file:${SURELOG_DIR}/tests/ForElab/top.v, line:55:5, endln:61:7 |vpiName:clk_i |vpiDirection:1 |vpiHighConn: @@ -450,7 +450,7 @@ design: (work@tlul_socket_m1) |vpiPort: \_port: (rst_ni), line:22:9, endln:22:15 |vpiParent: - \_module: work@prim_arbiter_tree (work@tlul_socket_m1.gen_tree_arb.u_reqarb), file:${SURELOG_DIR}/tests/ForElab/top.v, line:55:5, endln:61:7 + \_module_inst: work@prim_arbiter_tree (work@tlul_socket_m1.gen_tree_arb.u_reqarb), file:${SURELOG_DIR}/tests/ForElab/top.v, line:55:5, endln:61:7 |vpiName:rst_ni |vpiDirection:1 |vpiHighConn: @@ -470,7 +470,7 @@ design: (work@tlul_socket_m1) |vpiGenScopeArray: \_gen_scope_array: (work@tlul_socket_m1.gen_tree_arb.u_reqarb.gen_normal_case), line:32:12, endln:45:6 |vpiParent: - \_module: work@prim_arbiter_tree (work@tlul_socket_m1.gen_tree_arb.u_reqarb), file:${SURELOG_DIR}/tests/ForElab/top.v, line:55:5, endln:61:7 + \_module_inst: work@prim_arbiter_tree (work@tlul_socket_m1.gen_tree_arb.u_reqarb), file:${SURELOG_DIR}/tests/ForElab/top.v, line:55:5, endln:61:7 |vpiName:gen_normal_case |vpiFullName:work@tlul_socket_m1.gen_tree_arb.u_reqarb.gen_normal_case |vpiGenScope: diff --git a/tests/ForLoop/ForLoop.log b/tests/ForLoop/ForLoop.log index e2aa7164f6..97b1a0ca1f 100644 --- a/tests/ForLoop/ForLoop.log +++ b/tests/ForLoop/ForLoop.log @@ -1094,7 +1094,7 @@ integer_var 14 io_decl 11 logic_net 2 logic_var 1 -module 2 +module_inst 2 operation 33 package 2 ref_obj 51 @@ -1126,7 +1126,7 @@ integer_var 26 io_decl 22 logic_net 2 logic_var 1 -module 2 +module_inst 2 operation 66 package 2 ref_obj 102 @@ -1622,7 +1622,7 @@ design: (work@t) \_int_typespec: |vpiSigned:1 |uhdmallModules: -\_module: work@t (work@t), file:${SURELOG_DIR}/tests/ForLoop/dut.sv, line:1:1, endln:28:10 +\_module_inst: work@t (work@t), file:${SURELOG_DIR}/tests/ForLoop/dut.sv, line:1:1, endln:28:10 |vpiParent: \_design: (work@t) |vpiFullName:work@t @@ -1630,19 +1630,19 @@ design: (work@t) |vpiNet: \_logic_net: (work@t.a), line:3:11, endln:3:12 |vpiParent: - \_module: work@t (work@t), file:${SURELOG_DIR}/tests/ForLoop/dut.sv, line:1:1, endln:28:10 + \_module_inst: work@t (work@t), file:${SURELOG_DIR}/tests/ForLoop/dut.sv, line:1:1, endln:28:10 |vpiName:a |vpiFullName:work@t.a |vpiNet: \_logic_net: (work@t.b), line:3:14, endln:3:15 |vpiParent: - \_module: work@t (work@t), file:${SURELOG_DIR}/tests/ForLoop/dut.sv, line:1:1, endln:28:10 + \_module_inst: work@t (work@t), file:${SURELOG_DIR}/tests/ForLoop/dut.sv, line:1:1, endln:28:10 |vpiName:b |vpiFullName:work@t.b |vpiProcess: \_initial: , line:5:3, endln:26:6 |vpiParent: - \_module: work@t (work@t), file:${SURELOG_DIR}/tests/ForLoop/dut.sv, line:1:1, endln:28:10 + \_module_inst: work@t (work@t), file:${SURELOG_DIR}/tests/ForLoop/dut.sv, line:1:1, endln:28:10 |vpiStmt: \_begin: (work@t), line:5:11, endln:26:6 |vpiParent: @@ -3020,12 +3020,12 @@ design: (work@t) \_begin: (work@t), line:5:11, endln:26:6 |vpiName:$finish |uhdmtopModules: -\_module: work@t (work@t), file:${SURELOG_DIR}/tests/ForLoop/dut.sv, line:1:1, endln:28:10 +\_module_inst: work@t (work@t), file:${SURELOG_DIR}/tests/ForLoop/dut.sv, line:1:1, endln:28:10 |vpiName:work@t |vpiVariables: \_integer_var: (work@t.a), line:3:11, endln:3:12 |vpiParent: - \_module: work@t (work@t), file:${SURELOG_DIR}/tests/ForLoop/dut.sv, line:1:1, endln:28:10 + \_module_inst: work@t (work@t), file:${SURELOG_DIR}/tests/ForLoop/dut.sv, line:1:1, endln:28:10 |vpiTypespec: \_integer_typespec: , line:3:3, endln:3:10 |vpiSigned:1 @@ -3035,7 +3035,7 @@ design: (work@t) |vpiVariables: \_integer_var: (work@t.b), line:3:14, endln:3:15 |vpiParent: - \_module: work@t (work@t), file:${SURELOG_DIR}/tests/ForLoop/dut.sv, line:1:1, endln:28:10 + \_module_inst: work@t (work@t), file:${SURELOG_DIR}/tests/ForLoop/dut.sv, line:1:1, endln:28:10 |vpiTypespec: \_integer_typespec: , line:3:3, endln:3:10 |vpiName:b @@ -3047,7 +3047,7 @@ design: (work@t) |vpiProcess: \_initial: , line:5:3, endln:26:6 |vpiParent: - \_module: work@t (work@t), file:${SURELOG_DIR}/tests/ForLoop/dut.sv, line:1:1, endln:28:10 + \_module_inst: work@t (work@t), file:${SURELOG_DIR}/tests/ForLoop/dut.sv, line:1:1, endln:28:10 |vpiStmt: \_begin: (work@t), line:5:11, endln:26:6 |vpiParent: diff --git a/tests/ForLoopBind/ForLoopBind.log b/tests/ForLoopBind/ForLoopBind.log index 9bc29df68d..ed614b35c4 100644 --- a/tests/ForLoopBind/ForLoopBind.log +++ b/tests/ForLoopBind/ForLoopBind.log @@ -513,7 +513,7 @@ int_typespec 12 int_var 7 io_decl 11 logic_var 1 -module 2 +module_inst 2 operation 2 package 5 range 1 @@ -546,7 +546,7 @@ int_typespec 12 int_var 8 io_decl 22 logic_var 1 -module 2 +module_inst 2 operation 4 package 5 range 1 diff --git a/tests/ForeachArray/ForeachArray.log b/tests/ForeachArray/ForeachArray.log index e963334186..fb850f3821 100644 --- a/tests/ForeachArray/ForeachArray.log +++ b/tests/ForeachArray/ForeachArray.log @@ -99,7 +99,7 @@ initial 1 int_typespec 2 int_var 2 logic_net 1 -module 4 +module_inst 4 operation 1 range 1 ref_obj 4 @@ -122,7 +122,7 @@ initial 2 int_typespec 2 int_var 3 logic_net 1 -module 4 +module_inst 4 operation 1 range 1 ref_obj 7 @@ -142,7 +142,7 @@ design: (work@dut) |vpiElaborated:1 |vpiName:work@dut |uhdmallModules: -\_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/ForeachArray/dut.sv, line:1:1, endln:10:10 +\_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/ForeachArray/dut.sv, line:1:1, endln:10:10 |vpiParent: \_design: (work@dut) |vpiFullName:work@dut @@ -150,13 +150,13 @@ design: (work@dut) |vpiNet: \_logic_net: (work@dut.array), line:3:9, endln:3:14 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/ForeachArray/dut.sv, line:1:1, endln:10:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/ForeachArray/dut.sv, line:1:1, endln:10:10 |vpiName:array |vpiFullName:work@dut.array |vpiProcess: \_initial: , line:5:5, endln:8:8 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/ForeachArray/dut.sv, line:1:1, endln:10:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/ForeachArray/dut.sv, line:1:1, endln:10:10 |vpiStmt: \_begin: (work@dut), line:5:13, endln:8:8 |vpiParent: @@ -214,12 +214,12 @@ design: (work@dut) |vpiActual: \_int_var: (i), line:6:23, endln:6:24 |uhdmtopModules: -\_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/ForeachArray/dut.sv, line:1:1, endln:10:10 +\_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/ForeachArray/dut.sv, line:1:1, endln:10:10 |vpiName:work@dut |vpiVariables: \_array_var: (work@dut.array), line:3:9, endln:3:18 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/ForeachArray/dut.sv, line:1:1, endln:10:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/ForeachArray/dut.sv, line:1:1, endln:10:10 |vpiSize:16 |vpiTypespec: \_array_typespec: @@ -268,7 +268,7 @@ design: (work@dut) |vpiProcess: \_initial: , line:5:5, endln:8:8 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/ForeachArray/dut.sv, line:1:1, endln:10:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/ForeachArray/dut.sv, line:1:1, endln:10:10 |vpiStmt: \_begin: (work@dut), line:5:13, endln:8:8 |vpiParent: diff --git a/tests/ForeachClass/ForeachClass.log b/tests/ForeachClass/ForeachClass.log index 972a9e78d2..f6c09472b1 100644 --- a/tests/ForeachClass/ForeachClass.log +++ b/tests/ForeachClass/ForeachClass.log @@ -151,7 +151,7 @@ hier_path 6 if_stmt 2 logic_typespec 1 logic_var 3 -module 2 +module_inst 2 operation 7 package 3 range 1 @@ -179,7 +179,7 @@ hier_path 12 if_stmt 4 logic_typespec 1 logic_var 4 -module 2 +module_inst 2 operation 14 package 3 range 2 diff --git a/tests/ForeachClassParent/ForeachClassParent.log b/tests/ForeachClassParent/ForeachClassParent.log index 1b75f5aae1..127e7e81b0 100644 --- a/tests/ForeachClassParent/ForeachClassParent.log +++ b/tests/ForeachClassParent/ForeachClassParent.log @@ -101,7 +101,7 @@ extends 1 foreach_stmt 2 function 2 hier_path 1 -module 2 +module_inst 2 package 3 range 1 ref_obj 1 @@ -123,7 +123,7 @@ extends 3 foreach_stmt 5 function 5 hier_path 1 -module 2 +module_inst 2 package 3 range 1 ref_obj 1 diff --git a/tests/ForeachForeach/ForeachForeach.log b/tests/ForeachForeach/ForeachForeach.log index 5158e4c586..ff3a49307f 100644 --- a/tests/ForeachForeach/ForeachForeach.log +++ b/tests/ForeachForeach/ForeachForeach.log @@ -140,7 +140,7 @@ design 1 foreach_stmt 4 function 2 hier_path 3 -module 4 +module_inst 4 package 3 range 6 ref_obj 15 @@ -166,7 +166,7 @@ design 1 foreach_stmt 8 function 4 hier_path 5 -module 4 +module_inst 4 package 3 range 6 ref_obj 23 diff --git a/tests/ForeachFunction/ForeachFunction.log b/tests/ForeachFunction/ForeachFunction.log index 3c8735d86b..dd7ab5bfc2 100644 --- a/tests/ForeachFunction/ForeachFunction.log +++ b/tests/ForeachFunction/ForeachFunction.log @@ -93,7 +93,7 @@ hier_path 1 int_typespec 3 int_var 2 io_decl 1 -module 3 +module_inst 3 operation 1 range 1 ref_obj 1 @@ -115,7 +115,7 @@ hier_path 1 int_typespec 3 int_var 4 io_decl 2 -module 3 +module_inst 3 operation 1 range 1 ref_obj 1 @@ -135,7 +135,7 @@ design: (work@dut) |vpiElaborated:1 |vpiName:work@dut |uhdmallModules: -\_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/ForeachFunction/dut.sv, line:1:1, endln:10:10 +\_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/ForeachFunction/dut.sv, line:1:1, endln:10:10 |vpiParent: \_design: (work@dut) |vpiFullName:work@dut @@ -143,7 +143,7 @@ design: (work@dut) |vpiTaskFunc: \_function: (work@dut.get_expected_command), line:3:3, endln:8:13 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/ForeachFunction/dut.sv, line:1:1, endln:10:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/ForeachFunction/dut.sv, line:1:1, endln:10:10 |vpiName:get_expected_command |vpiFullName:work@dut.get_expected_command |vpiVariables: @@ -198,7 +198,7 @@ design: (work@dut) |vpiSigned:1 |vpiSigned:1 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/ForeachFunction/dut.sv, line:1:1, endln:10:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/ForeachFunction/dut.sv, line:1:1, endln:10:10 |vpiIODecl: \_io_decl: (slave_id), line:3:52, endln:3:60 |vpiDirection:1 @@ -245,16 +245,16 @@ design: (work@dut) \_foreach_stmt: (work@dut.get_expected_command), line:6:6, endln:6:13 |vpiFullName:work@dut.get_expected_command |vpiInstance: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/ForeachFunction/dut.sv, line:1:1, endln:10:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/ForeachFunction/dut.sv, line:1:1, endln:10:10 |uhdmtopModules: -\_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/ForeachFunction/dut.sv, line:1:1, endln:10:10 +\_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/ForeachFunction/dut.sv, line:1:1, endln:10:10 |vpiName:work@dut |vpiDefName:work@dut |vpiTop:1 |vpiTaskFunc: \_function: (work@dut.get_expected_command), line:3:3, endln:8:13 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/ForeachFunction/dut.sv, line:1:1, endln:10:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/ForeachFunction/dut.sv, line:1:1, endln:10:10 |vpiName:get_expected_command |vpiFullName:work@dut.get_expected_command |vpiVariables: @@ -279,7 +279,7 @@ design: (work@dut) |vpiReturn: \_int_var: , line:3:22, endln:3:25 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/ForeachFunction/dut.sv, line:1:1, endln:10:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/ForeachFunction/dut.sv, line:1:1, endln:10:10 |vpiIODecl: \_io_decl: (slave_id), line:3:52, endln:3:60 |vpiParent: @@ -349,7 +349,7 @@ design: (work@dut) \_foreach_stmt: (work@dut.get_expected_command), line:6:6, endln:6:13 |vpiFullName:work@dut.get_expected_command |vpiInstance: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/ForeachFunction/dut.sv, line:1:1, endln:10:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/ForeachFunction/dut.sv, line:1:1, endln:10:10 |vpiTopModule:1 =================== [ FATAL] : 0 diff --git a/tests/ForeachSquare/ForeachSquare.log b/tests/ForeachSquare/ForeachSquare.log index b0190fddf3..049492acb9 100644 --- a/tests/ForeachSquare/ForeachSquare.log +++ b/tests/ForeachSquare/ForeachSquare.log @@ -123,7 +123,7 @@ initial 1 int_typespec 3 int_var 3 logic_net 1 -module 4 +module_inst 4 operation 3 range 2 ref_obj 6 @@ -146,7 +146,7 @@ initial 2 int_typespec 3 int_var 5 logic_net 1 -module 4 +module_inst 4 operation 4 range 2 ref_obj 10 @@ -167,7 +167,7 @@ design: (work@dut) |vpiElaborated:1 |vpiName:work@dut |uhdmallModules: -\_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/ForeachSquare/dut.sv, line:1:1, endln:11:10 +\_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/ForeachSquare/dut.sv, line:1:1, endln:11:10 |vpiParent: \_design: (work@dut) |vpiFullName:work@dut @@ -175,13 +175,13 @@ design: (work@dut) |vpiNet: \_logic_net: (work@dut.array), line:3:9, endln:3:14 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/ForeachSquare/dut.sv, line:1:1, endln:11:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/ForeachSquare/dut.sv, line:1:1, endln:11:10 |vpiName:array |vpiFullName:work@dut.array |vpiProcess: \_initial: , line:5:5, endln:9:8 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/ForeachSquare/dut.sv, line:1:1, endln:11:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/ForeachSquare/dut.sv, line:1:1, endln:11:10 |vpiStmt: \_begin: (work@dut), line:5:13, endln:9:8 |vpiParent: @@ -283,12 +283,12 @@ design: (work@dut) |vpiActual: \_int_var: (j), line:7:30, endln:7:31 |uhdmtopModules: -\_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/ForeachSquare/dut.sv, line:1:1, endln:11:10 +\_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/ForeachSquare/dut.sv, line:1:1, endln:11:10 |vpiName:work@dut |vpiVariables: \_array_var: (work@dut.array), line:3:9, endln:3:18 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/ForeachSquare/dut.sv, line:1:1, endln:11:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/ForeachSquare/dut.sv, line:1:1, endln:11:10 |vpiSize:256 |vpiTypespec: \_array_typespec: @@ -363,7 +363,7 @@ design: (work@dut) |vpiProcess: \_initial: , line:5:5, endln:9:8 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/ForeachSquare/dut.sv, line:1:1, endln:11:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/ForeachSquare/dut.sv, line:1:1, endln:11:10 |vpiStmt: \_begin: (work@dut), line:5:13, endln:9:8 |vpiParent: diff --git a/tests/FuncArgDirection/FuncArgDirection.log b/tests/FuncArgDirection/FuncArgDirection.log index fe684e9e8f..be2eb59ed3 100644 --- a/tests/FuncArgDirection/FuncArgDirection.log +++ b/tests/FuncArgDirection/FuncArgDirection.log @@ -513,7 +513,7 @@ io_decl 12 logic_net 2 logic_typespec 4 logic_var 5 -module 5 +module_inst 5 operation 3 package 2 param_assign 1 @@ -548,7 +548,7 @@ io_decl 24 logic_net 2 logic_typespec 4 logic_var 7 -module 5 +module_inst 5 operation 6 package 2 param_assign 1 @@ -1046,7 +1046,7 @@ design: (work@dut) \_int_typespec: |vpiSigned:1 |uhdmallModules: -\_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/FuncArgDirection/dut.sv, line:1:1, endln:15:10 +\_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/FuncArgDirection/dut.sv, line:1:1, endln:15:10 |vpiParent: \_design: (work@dut) |vpiFullName:work@dut @@ -1054,7 +1054,7 @@ design: (work@dut) |vpiTaskFunc: \_function: (work@dut.aes_rev_order_bit), line:2:1, endln:8:12 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/FuncArgDirection/dut.sv, line:1:1, endln:15:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/FuncArgDirection/dut.sv, line:1:1, endln:15:10 |vpiName:aes_rev_order_bit |vpiFullName:work@dut.aes_rev_order_bit |vpiVariables: @@ -1110,7 +1110,7 @@ design: (work@dut) |UINT:0 |vpiConstType:9 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/FuncArgDirection/dut.sv, line:1:1, endln:15:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/FuncArgDirection/dut.sv, line:1:1, endln:15:10 |vpiIODecl: \_io_decl: (in), line:2:62, endln:2:64 |vpiDirection:1 @@ -1276,25 +1276,25 @@ design: (work@dut) |vpiActual: \_logic_var: (work@dut.aes_rev_order_bit.out), line:3:15, endln:3:18 |vpiInstance: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/FuncArgDirection/dut.sv, line:1:1, endln:15:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/FuncArgDirection/dut.sv, line:1:1, endln:15:10 |vpiNet: \_logic_net: (work@dut.ctr_we_o_rev), line:10:19, endln:10:31 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/FuncArgDirection/dut.sv, line:1:1, endln:15:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/FuncArgDirection/dut.sv, line:1:1, endln:15:10 |vpiName:ctr_we_o_rev |vpiFullName:work@dut.ctr_we_o_rev |vpiNetType:36 |vpiNet: \_logic_net: (work@dut.ctr_we_o), line:10:33, endln:10:41 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/FuncArgDirection/dut.sv, line:1:1, endln:15:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/FuncArgDirection/dut.sv, line:1:1, endln:15:10 |vpiName:ctr_we_o |vpiFullName:work@dut.ctr_we_o |vpiNetType:36 |vpiContAssign: \_cont_assign: , line:12:8, endln:12:34 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/FuncArgDirection/dut.sv, line:1:1, endln:15:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/FuncArgDirection/dut.sv, line:1:1, endln:15:10 |vpiRhs: \_constant: , line:12:23, endln:12:34 |vpiParent: @@ -1314,7 +1314,7 @@ design: (work@dut) |vpiContAssign: \_cont_assign: , line:14:8, endln:14:50 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/FuncArgDirection/dut.sv, line:1:1, endln:15:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/FuncArgDirection/dut.sv, line:1:1, endln:15:10 |vpiRhs: \_func_call: (aes_rev_order_bit), line:14:19, endln:14:50 |vpiParent: @@ -1341,12 +1341,12 @@ design: (work@dut) |vpiActual: \_logic_var: (work@dut.ctr_we_o), line:10:33, endln:10:41 |uhdmtopModules: -\_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/FuncArgDirection/dut.sv, line:1:1, endln:15:10 +\_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/FuncArgDirection/dut.sv, line:1:1, endln:15:10 |vpiName:work@dut |vpiVariables: \_logic_var: (work@dut.ctr_we_o_rev), line:10:19, endln:10:31 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/FuncArgDirection/dut.sv, line:1:1, endln:15:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/FuncArgDirection/dut.sv, line:1:1, endln:15:10 |vpiTypespec: \_logic_typespec: , line:10:1, endln:10:12 |vpiRange: @@ -1391,7 +1391,7 @@ design: (work@dut) |vpiVariables: \_logic_var: (work@dut.ctr_we_o), line:10:33, endln:10:41 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/FuncArgDirection/dut.sv, line:1:1, endln:15:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/FuncArgDirection/dut.sv, line:1:1, endln:15:10 |vpiTypespec: \_logic_typespec: , line:10:1, endln:10:12 |vpiName:ctr_we_o @@ -1420,7 +1420,7 @@ design: (work@dut) |vpiTaskFunc: \_function: (work@dut.aes_rev_order_bit), line:2:1, endln:8:12 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/FuncArgDirection/dut.sv, line:1:1, endln:15:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/FuncArgDirection/dut.sv, line:1:1, endln:15:10 |vpiName:aes_rev_order_bit |vpiFullName:work@dut.aes_rev_order_bit |vpiVariables: @@ -1436,7 +1436,7 @@ design: (work@dut) |vpiReturn: \_logic_var: , line:2:20, endln:2:31 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/FuncArgDirection/dut.sv, line:1:1, endln:15:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/FuncArgDirection/dut.sv, line:1:1, endln:15:10 |vpiIODecl: \_io_decl: (in), line:2:62, endln:2:64 |vpiParent: @@ -1581,12 +1581,12 @@ design: (work@dut) |vpiActual: \_logic_var: (work@dut.aes_rev_order_bit.out), line:3:15, endln:3:18 |vpiInstance: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/FuncArgDirection/dut.sv, line:1:1, endln:15:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/FuncArgDirection/dut.sv, line:1:1, endln:15:10 |vpiTopModule:1 |vpiContAssign: \_cont_assign: , line:12:8, endln:12:34 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/FuncArgDirection/dut.sv, line:1:1, endln:15:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/FuncArgDirection/dut.sv, line:1:1, endln:15:10 |vpiRhs: \_constant: , line:12:23, endln:12:34 |vpiLhs: @@ -1600,7 +1600,7 @@ design: (work@dut) |vpiContAssign: \_cont_assign: , line:14:8, endln:14:50 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/FuncArgDirection/dut.sv, line:1:1, endln:15:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/FuncArgDirection/dut.sv, line:1:1, endln:15:10 |vpiRhs: \_func_call: (aes_rev_order_bit), line:14:19, endln:14:50 |vpiParent: diff --git a/tests/FuncArgs/FuncArgs.log b/tests/FuncArgs/FuncArgs.log index dff0c503d1..4e4f90fc09 100644 --- a/tests/FuncArgs/FuncArgs.log +++ b/tests/FuncArgs/FuncArgs.log @@ -356,7 +356,7 @@ io_decl 4 logic_net 6 logic_typespec 21 logic_var 6 -module 8 +module_inst 8 operation 6 param_assign 19 parameter 19 @@ -379,7 +379,7 @@ io_decl 8 logic_net 6 logic_typespec 21 logic_var 6 -module 8 +module_inst 8 operation 12 param_assign 19 parameter 19 @@ -400,7 +400,7 @@ design: (work@dut) |vpiElaborated:1 |vpiName:work@dut |uhdmallModules: -\_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/FuncArgs/dut.sv, line:1:1, endln:25:10 +\_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/FuncArgs/dut.sv, line:1:1, endln:25:10 |vpiParent: \_design: (work@dut) |vpiFullName:work@dut @@ -408,7 +408,7 @@ design: (work@dut) |vpiTaskFunc: \_function: (work@dut.pow_a), line:5:9, endln:12:20 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/FuncArgs/dut.sv, line:1:1, endln:25:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/FuncArgs/dut.sv, line:1:1, endln:25:10 |vpiName:pow_a |vpiFullName:work@dut.pow_a |vpiVisibility:1 @@ -436,7 +436,7 @@ design: (work@dut) |UINT:0 |vpiConstType:9 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/FuncArgs/dut.sv, line:1:1, endln:25:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/FuncArgs/dut.sv, line:1:1, endln:25:10 |vpiIODecl: \_io_decl: (base), line:6:29, endln:6:33 |vpiParent: @@ -589,11 +589,11 @@ design: (work@dut) |vpiActual: \_logic_var: (pow_a), line:5:28, endln:5:33 |vpiInstance: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/FuncArgs/dut.sv, line:1:1, endln:25:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/FuncArgs/dut.sv, line:1:1, endln:25:10 |vpiTaskFunc: \_function: (work@dut.pow_b), line:14:9, endln:21:20 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/FuncArgs/dut.sv, line:1:1, endln:25:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/FuncArgs/dut.sv, line:1:1, endln:25:10 |vpiName:pow_b |vpiFullName:work@dut.pow_b |vpiVisibility:1 @@ -621,7 +621,7 @@ design: (work@dut) |UINT:0 |vpiConstType:9 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/FuncArgs/dut.sv, line:1:1, endln:25:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/FuncArgs/dut.sv, line:1:1, endln:25:10 |vpiIODecl: \_io_decl: (base), line:15:29, endln:15:33 |vpiParent: @@ -774,32 +774,32 @@ design: (work@dut) |vpiActual: \_logic_var: (pow_b), line:14:28, endln:14:33 |vpiInstance: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/FuncArgs/dut.sv, line:1:1, endln:25:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/FuncArgs/dut.sv, line:1:1, endln:25:10 |vpiNet: \_logic_net: (work@dut.inp), line:2:26, endln:2:29 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/FuncArgs/dut.sv, line:1:1, endln:25:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/FuncArgs/dut.sv, line:1:1, endln:25:10 |vpiName:inp |vpiFullName:work@dut.inp |vpiNetType:1 |vpiNet: \_logic_net: (work@dut.out1), line:3:27, endln:3:31 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/FuncArgs/dut.sv, line:1:1, endln:25:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/FuncArgs/dut.sv, line:1:1, endln:25:10 |vpiName:out1 |vpiFullName:work@dut.out1 |vpiNetType:1 |vpiNet: \_logic_net: (work@dut.out2), line:3:33, endln:3:37 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/FuncArgs/dut.sv, line:1:1, endln:25:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/FuncArgs/dut.sv, line:1:1, endln:25:10 |vpiName:out2 |vpiFullName:work@dut.out2 |vpiNetType:1 |vpiPort: \_port: (inp), line:2:26, endln:2:29 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/FuncArgs/dut.sv, line:1:1, endln:25:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/FuncArgs/dut.sv, line:1:1, endln:25:10 |vpiName:inp |vpiDirection:1 |vpiLowConn: @@ -829,7 +829,7 @@ design: (work@dut) |vpiPort: \_port: (out1), line:3:27, endln:3:31 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/FuncArgs/dut.sv, line:1:1, endln:25:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/FuncArgs/dut.sv, line:1:1, endln:25:10 |vpiName:out1 |vpiDirection:2 |vpiLowConn: @@ -859,7 +859,7 @@ design: (work@dut) |vpiPort: \_port: (out2), line:3:33, endln:3:37 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/FuncArgs/dut.sv, line:1:1, endln:25:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/FuncArgs/dut.sv, line:1:1, endln:25:10 |vpiName:out2 |vpiDirection:2 |vpiLowConn: @@ -889,7 +889,7 @@ design: (work@dut) |vpiContAssign: \_cont_assign: , line:23:16, endln:23:36 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/FuncArgs/dut.sv, line:1:1, endln:25:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/FuncArgs/dut.sv, line:1:1, endln:25:10 |vpiRhs: \_func_call: (pow_a), line:23:23, endln:23:36 |vpiParent: @@ -928,7 +928,7 @@ design: (work@dut) |vpiContAssign: \_cont_assign: , line:24:16, endln:24:34 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/FuncArgs/dut.sv, line:1:1, endln:25:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/FuncArgs/dut.sv, line:1:1, endln:25:10 |vpiRhs: \_func_call: (pow_b), line:24:23, endln:24:34 |vpiParent: @@ -965,14 +965,14 @@ design: (work@dut) |vpiActual: \_logic_net: (work@dut.out2), line:3:33, endln:3:37 |uhdmtopModules: -\_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/FuncArgs/dut.sv, line:1:1, endln:25:10 +\_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/FuncArgs/dut.sv, line:1:1, endln:25:10 |vpiName:work@dut |vpiDefName:work@dut |vpiTop:1 |vpiTaskFunc: \_function: (work@dut.pow_a), line:5:9, endln:12:20 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/FuncArgs/dut.sv, line:1:1, endln:25:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/FuncArgs/dut.sv, line:1:1, endln:25:10 |vpiName:pow_a |vpiFullName:work@dut.pow_a |vpiVisibility:1 @@ -980,7 +980,7 @@ design: (work@dut) |vpiReturn: \_logic_var: , line:5:28, endln:5:33 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/FuncArgs/dut.sv, line:1:1, endln:25:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/FuncArgs/dut.sv, line:1:1, endln:25:10 |vpiIODecl: \_io_decl: (base), line:6:29, endln:6:33 |vpiParent: @@ -1095,11 +1095,11 @@ design: (work@dut) |vpiActual: \_logic_var: , line:5:28, endln:5:33 |vpiInstance: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/FuncArgs/dut.sv, line:1:1, endln:25:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/FuncArgs/dut.sv, line:1:1, endln:25:10 |vpiTaskFunc: \_function: (work@dut.pow_b), line:14:9, endln:21:20 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/FuncArgs/dut.sv, line:1:1, endln:25:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/FuncArgs/dut.sv, line:1:1, endln:25:10 |vpiName:pow_b |vpiFullName:work@dut.pow_b |vpiVisibility:1 @@ -1107,7 +1107,7 @@ design: (work@dut) |vpiReturn: \_logic_var: , line:14:28, endln:14:33 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/FuncArgs/dut.sv, line:1:1, endln:25:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/FuncArgs/dut.sv, line:1:1, endln:25:10 |vpiIODecl: \_io_decl: (base), line:15:29, endln:15:33 |vpiParent: @@ -1222,11 +1222,11 @@ design: (work@dut) |vpiActual: \_logic_var: , line:14:28, endln:14:33 |vpiInstance: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/FuncArgs/dut.sv, line:1:1, endln:25:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/FuncArgs/dut.sv, line:1:1, endln:25:10 |vpiNet: \_logic_net: (work@dut.inp), line:2:26, endln:2:29 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/FuncArgs/dut.sv, line:1:1, endln:25:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/FuncArgs/dut.sv, line:1:1, endln:25:10 |vpiTypespec: \_logic_typespec: , line:2:15, endln:2:25 |vpiRange: @@ -1253,7 +1253,7 @@ design: (work@dut) |vpiNet: \_logic_net: (work@dut.out1), line:3:27, endln:3:31 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/FuncArgs/dut.sv, line:1:1, endln:25:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/FuncArgs/dut.sv, line:1:1, endln:25:10 |vpiTypespec: \_logic_typespec: , line:3:16, endln:3:26 |vpiRange: @@ -1280,7 +1280,7 @@ design: (work@dut) |vpiNet: \_logic_net: (work@dut.out2), line:3:33, endln:3:37 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/FuncArgs/dut.sv, line:1:1, endln:25:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/FuncArgs/dut.sv, line:1:1, endln:25:10 |vpiTypespec: \_logic_typespec: , line:3:16, endln:3:26 |vpiName:out2 @@ -1290,7 +1290,7 @@ design: (work@dut) |vpiPort: \_port: (inp), line:2:26, endln:2:29 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/FuncArgs/dut.sv, line:1:1, endln:25:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/FuncArgs/dut.sv, line:1:1, endln:25:10 |vpiName:inp |vpiDirection:1 |vpiLowConn: @@ -1324,11 +1324,11 @@ design: (work@dut) |UINT:0 |vpiConstType:9 |vpiInstance: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/FuncArgs/dut.sv, line:1:1, endln:25:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/FuncArgs/dut.sv, line:1:1, endln:25:10 |vpiPort: \_port: (out1), line:3:27, endln:3:31 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/FuncArgs/dut.sv, line:1:1, endln:25:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/FuncArgs/dut.sv, line:1:1, endln:25:10 |vpiName:out1 |vpiDirection:2 |vpiLowConn: @@ -1362,11 +1362,11 @@ design: (work@dut) |UINT:0 |vpiConstType:9 |vpiInstance: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/FuncArgs/dut.sv, line:1:1, endln:25:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/FuncArgs/dut.sv, line:1:1, endln:25:10 |vpiPort: \_port: (out2), line:3:33, endln:3:37 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/FuncArgs/dut.sv, line:1:1, endln:25:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/FuncArgs/dut.sv, line:1:1, endln:25:10 |vpiName:out2 |vpiDirection:2 |vpiLowConn: @@ -1380,11 +1380,11 @@ design: (work@dut) |vpiTypedef: \_logic_typespec: , line:3:16, endln:3:26 |vpiInstance: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/FuncArgs/dut.sv, line:1:1, endln:25:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/FuncArgs/dut.sv, line:1:1, endln:25:10 |vpiContAssign: \_cont_assign: , line:23:16, endln:23:36 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/FuncArgs/dut.sv, line:1:1, endln:25:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/FuncArgs/dut.sv, line:1:1, endln:25:10 |vpiRhs: \_func_call: (pow_a), line:23:23, endln:23:36 |vpiParent: @@ -1415,7 +1415,7 @@ design: (work@dut) |vpiContAssign: \_cont_assign: , line:24:16, endln:24:34 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/FuncArgs/dut.sv, line:1:1, endln:25:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/FuncArgs/dut.sv, line:1:1, endln:25:10 |vpiRhs: \_constant: |vpiParent: diff --git a/tests/FuncArgsByName/FuncArgsByName.log b/tests/FuncArgsByName/FuncArgsByName.log index bd8b022a4a..3b558495fb 100644 --- a/tests/FuncArgsByName/FuncArgsByName.log +++ b/tests/FuncArgsByName/FuncArgsByName.log @@ -396,7 +396,7 @@ int_typespec 9 int_var 4 io_decl 13 logic_var 1 -module 2 +module_inst 2 package 2 string_typespec 2 task 9 @@ -421,7 +421,7 @@ int_typespec 9 int_var 4 io_decl 26 logic_var 1 -module 2 +module_inst 2 package 2 string_typespec 2 task 18 @@ -914,7 +914,7 @@ design: (work@top) \_int_typespec: |vpiSigned:1 |uhdmallModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/FuncArgsByName/dut.sv, line:1:1, endln:18:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/FuncArgsByName/dut.sv, line:1:1, endln:18:10 |vpiParent: \_design: (work@top) |vpiFullName:work@top @@ -922,7 +922,7 @@ design: (work@top) |vpiTaskFunc: \_function: (work@top.m_matches_type_pair), line:3:4, endln:5:15 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/FuncArgsByName/dut.sv, line:1:1, endln:18:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/FuncArgsByName/dut.sv, line:1:1, endln:18:10 |vpiName:m_matches_type_pair |vpiFullName:work@top.m_matches_type_pair |vpiVisibility:1 @@ -932,7 +932,7 @@ design: (work@top) \_bit_typespec: , line:3:13, endln:3:16 |vpiSigned:1 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/FuncArgsByName/dut.sv, line:1:1, endln:18:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/FuncArgsByName/dut.sv, line:1:1, endln:18:10 |vpiIODecl: \_io_decl: (match_type_pair), line:3:44, endln:3:59 |vpiDirection:1 @@ -946,16 +946,16 @@ design: (work@top) |vpiTypedef: \_string_typespec: , line:4:7, endln:4:13 |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/FuncArgsByName/dut.sv, line:1:1, endln:18:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/FuncArgsByName/dut.sv, line:1:1, endln:18:10 |vpiTaskFunc: \_function: (work@top.func), line:7:4, endln:16:15 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/FuncArgsByName/dut.sv, line:1:1, endln:18:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/FuncArgsByName/dut.sv, line:1:1, endln:18:10 |vpiName:func |vpiFullName:work@top.func |vpiVisibility:1 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/FuncArgsByName/dut.sv, line:1:1, endln:18:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/FuncArgsByName/dut.sv, line:1:1, endln:18:10 |vpiStmt: \_begin: (work@top.func) |vpiParent: @@ -1031,23 +1031,23 @@ design: (work@top) |vpiFunction: \_function: (work@top.m_matches_type_pair), line:3:4, endln:5:15 |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/FuncArgsByName/dut.sv, line:1:1, endln:18:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/FuncArgsByName/dut.sv, line:1:1, endln:18:10 |uhdmtopModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/FuncArgsByName/dut.sv, line:1:1, endln:18:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/FuncArgsByName/dut.sv, line:1:1, endln:18:10 |vpiName:work@top |vpiDefName:work@top |vpiTop:1 |vpiTaskFunc: \_function: (work@top.m_matches_type_pair), line:3:4, endln:5:15 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/FuncArgsByName/dut.sv, line:1:1, endln:18:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/FuncArgsByName/dut.sv, line:1:1, endln:18:10 |vpiName:m_matches_type_pair |vpiFullName:work@top.m_matches_type_pair |vpiVisibility:1 |vpiReturn: \_bit_var: , line:3:13, endln:3:16 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/FuncArgsByName/dut.sv, line:1:1, endln:18:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/FuncArgsByName/dut.sv, line:1:1, endln:18:10 |vpiIODecl: \_io_decl: (match_type_pair), line:3:44, endln:3:59 |vpiParent: @@ -1065,16 +1065,16 @@ design: (work@top) |vpiTypedef: \_string_typespec: , line:4:7, endln:4:13 |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/FuncArgsByName/dut.sv, line:1:1, endln:18:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/FuncArgsByName/dut.sv, line:1:1, endln:18:10 |vpiTaskFunc: \_function: (work@top.func), line:7:4, endln:16:15 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/FuncArgsByName/dut.sv, line:1:1, endln:18:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/FuncArgsByName/dut.sv, line:1:1, endln:18:10 |vpiName:func |vpiFullName:work@top.func |vpiVisibility:1 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/FuncArgsByName/dut.sv, line:1:1, endln:18:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/FuncArgsByName/dut.sv, line:1:1, endln:18:10 |vpiStmt: \_begin: (work@top.func) |vpiParent: @@ -1114,7 +1114,7 @@ design: (work@top) |vpiFunction: \_function: (work@top.m_matches_type_pair), line:3:4, endln:5:15 |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/FuncArgsByName/dut.sv, line:1:1, endln:18:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/FuncArgsByName/dut.sv, line:1:1, endln:18:10 |vpiTopModule:1 =================== [ FATAL] : 0 diff --git a/tests/FuncAttrib/FuncAttrib.log b/tests/FuncAttrib/FuncAttrib.log index c1ecde7272..02eed9fd63 100644 --- a/tests/FuncAttrib/FuncAttrib.log +++ b/tests/FuncAttrib/FuncAttrib.log @@ -285,7 +285,7 @@ io_decl 2 logic_net 10 logic_typespec 18 logic_var 1 -module 3 +module_inst 3 operation 2 port 10 range 15 @@ -307,7 +307,7 @@ io_decl 2 logic_net 10 logic_typespec 18 logic_var 1 -module 3 +module_inst 3 operation 3 port 15 range 15 @@ -326,7 +326,7 @@ design: (work@foo) |vpiElaborated:1 |vpiName:work@foo |uhdmallModules: -\_module: work@foo (work@foo), file:${SURELOG_DIR}/tests/FuncAttrib/dut.sv, line:9:1, endln:22:10 +\_module_inst: work@foo (work@foo), file:${SURELOG_DIR}/tests/FuncAttrib/dut.sv, line:9:1, endln:22:10 |vpiParent: \_design: (work@foo) |vpiFullName:work@foo @@ -334,42 +334,42 @@ design: (work@foo) |vpiNet: \_logic_net: (work@foo.clk), line:9:12, endln:9:15 |vpiParent: - \_module: work@foo (work@foo), file:${SURELOG_DIR}/tests/FuncAttrib/dut.sv, line:9:1, endln:22:10 + \_module_inst: work@foo (work@foo), file:${SURELOG_DIR}/tests/FuncAttrib/dut.sv, line:9:1, endln:22:10 |vpiName:clk |vpiFullName:work@foo.clk |vpiNetType:1 |vpiNet: \_logic_net: (work@foo.rst), line:9:17, endln:9:20 |vpiParent: - \_module: work@foo (work@foo), file:${SURELOG_DIR}/tests/FuncAttrib/dut.sv, line:9:1, endln:22:10 + \_module_inst: work@foo (work@foo), file:${SURELOG_DIR}/tests/FuncAttrib/dut.sv, line:9:1, endln:22:10 |vpiName:rst |vpiFullName:work@foo.rst |vpiNetType:1 |vpiNet: \_logic_net: (work@foo.inp_a), line:9:22, endln:9:27 |vpiParent: - \_module: work@foo (work@foo), file:${SURELOG_DIR}/tests/FuncAttrib/dut.sv, line:9:1, endln:22:10 + \_module_inst: work@foo (work@foo), file:${SURELOG_DIR}/tests/FuncAttrib/dut.sv, line:9:1, endln:22:10 |vpiName:inp_a |vpiFullName:work@foo.inp_a |vpiNetType:1 |vpiNet: \_logic_net: (work@foo.inp_b), line:9:29, endln:9:34 |vpiParent: - \_module: work@foo (work@foo), file:${SURELOG_DIR}/tests/FuncAttrib/dut.sv, line:9:1, endln:22:10 + \_module_inst: work@foo (work@foo), file:${SURELOG_DIR}/tests/FuncAttrib/dut.sv, line:9:1, endln:22:10 |vpiName:inp_b |vpiFullName:work@foo.inp_b |vpiNetType:1 |vpiNet: \_logic_net: (work@foo.out), line:9:36, endln:9:39 |vpiParent: - \_module: work@foo (work@foo), file:${SURELOG_DIR}/tests/FuncAttrib/dut.sv, line:9:1, endln:22:10 + \_module_inst: work@foo (work@foo), file:${SURELOG_DIR}/tests/FuncAttrib/dut.sv, line:9:1, endln:22:10 |vpiName:out |vpiFullName:work@foo.out |vpiNetType:48 |vpiPort: \_port: (clk), line:9:12, endln:9:15 |vpiParent: - \_module: work@foo (work@foo), file:${SURELOG_DIR}/tests/FuncAttrib/dut.sv, line:9:1, endln:22:10 + \_module_inst: work@foo (work@foo), file:${SURELOG_DIR}/tests/FuncAttrib/dut.sv, line:9:1, endln:22:10 |vpiName:clk |vpiDirection:1 |vpiLowConn: @@ -381,7 +381,7 @@ design: (work@foo) |vpiPort: \_port: (rst), line:9:17, endln:9:20 |vpiParent: - \_module: work@foo (work@foo), file:${SURELOG_DIR}/tests/FuncAttrib/dut.sv, line:9:1, endln:22:10 + \_module_inst: work@foo (work@foo), file:${SURELOG_DIR}/tests/FuncAttrib/dut.sv, line:9:1, endln:22:10 |vpiName:rst |vpiDirection:1 |vpiLowConn: @@ -393,7 +393,7 @@ design: (work@foo) |vpiPort: \_port: (inp_a), line:9:22, endln:9:27 |vpiParent: - \_module: work@foo (work@foo), file:${SURELOG_DIR}/tests/FuncAttrib/dut.sv, line:9:1, endln:22:10 + \_module_inst: work@foo (work@foo), file:${SURELOG_DIR}/tests/FuncAttrib/dut.sv, line:9:1, endln:22:10 |vpiName:inp_a |vpiDirection:1 |vpiLowConn: @@ -423,7 +423,7 @@ design: (work@foo) |vpiPort: \_port: (inp_b), line:9:29, endln:9:34 |vpiParent: - \_module: work@foo (work@foo), file:${SURELOG_DIR}/tests/FuncAttrib/dut.sv, line:9:1, endln:22:10 + \_module_inst: work@foo (work@foo), file:${SURELOG_DIR}/tests/FuncAttrib/dut.sv, line:9:1, endln:22:10 |vpiName:inp_b |vpiDirection:1 |vpiLowConn: @@ -453,7 +453,7 @@ design: (work@foo) |vpiPort: \_port: (out), line:9:36, endln:9:39 |vpiParent: - \_module: work@foo (work@foo), file:${SURELOG_DIR}/tests/FuncAttrib/dut.sv, line:9:1, endln:22:10 + \_module_inst: work@foo (work@foo), file:${SURELOG_DIR}/tests/FuncAttrib/dut.sv, line:9:1, endln:22:10 |vpiName:out |vpiDirection:2 |vpiLowConn: @@ -483,7 +483,7 @@ design: (work@foo) |vpiProcess: \_always: , line:16:1, endln:20:53 |vpiParent: - \_module: work@foo (work@foo), file:${SURELOG_DIR}/tests/FuncAttrib/dut.sv, line:9:1, endln:22:10 + \_module_inst: work@foo (work@foo), file:${SURELOG_DIR}/tests/FuncAttrib/dut.sv, line:9:1, endln:22:10 |vpiStmt: \_event_control: , line:16:8, endln:16:22 |vpiParent: @@ -694,14 +694,14 @@ design: (work@foo) |vpiActual: \_logic_var: , line:1:10, endln:1:15 |uhdmtopModules: -\_module: work@foo (work@foo), file:${SURELOG_DIR}/tests/FuncAttrib/dut.sv, line:9:1, endln:22:10 +\_module_inst: work@foo (work@foo), file:${SURELOG_DIR}/tests/FuncAttrib/dut.sv, line:9:1, endln:22:10 |vpiName:work@foo |vpiDefName:work@foo |vpiTop:1 |vpiNet: \_logic_net: (work@foo.clk), line:9:12, endln:9:15 |vpiParent: - \_module: work@foo (work@foo), file:${SURELOG_DIR}/tests/FuncAttrib/dut.sv, line:9:1, endln:22:10 + \_module_inst: work@foo (work@foo), file:${SURELOG_DIR}/tests/FuncAttrib/dut.sv, line:9:1, endln:22:10 |vpiTypespec: \_logic_typespec: , line:10:8, endln:10:12 |vpiName:clk @@ -710,7 +710,7 @@ design: (work@foo) |vpiNet: \_logic_net: (work@foo.rst), line:9:17, endln:9:20 |vpiParent: - \_module: work@foo (work@foo), file:${SURELOG_DIR}/tests/FuncAttrib/dut.sv, line:9:1, endln:22:10 + \_module_inst: work@foo (work@foo), file:${SURELOG_DIR}/tests/FuncAttrib/dut.sv, line:9:1, endln:22:10 |vpiTypespec: \_logic_typespec: , line:11:8, endln:11:12 |vpiName:rst @@ -719,7 +719,7 @@ design: (work@foo) |vpiNet: \_logic_net: (work@foo.inp_a), line:9:22, endln:9:27 |vpiParent: - \_module: work@foo (work@foo), file:${SURELOG_DIR}/tests/FuncAttrib/dut.sv, line:9:1, endln:22:10 + \_module_inst: work@foo (work@foo), file:${SURELOG_DIR}/tests/FuncAttrib/dut.sv, line:9:1, endln:22:10 |vpiTypespec: \_logic_typespec: , line:12:8, endln:12:18 |vpiRange: @@ -746,7 +746,7 @@ design: (work@foo) |vpiNet: \_logic_net: (work@foo.inp_b), line:9:29, endln:9:34 |vpiParent: - \_module: work@foo (work@foo), file:${SURELOG_DIR}/tests/FuncAttrib/dut.sv, line:9:1, endln:22:10 + \_module_inst: work@foo (work@foo), file:${SURELOG_DIR}/tests/FuncAttrib/dut.sv, line:9:1, endln:22:10 |vpiTypespec: \_logic_typespec: , line:13:8, endln:13:18 |vpiRange: @@ -773,7 +773,7 @@ design: (work@foo) |vpiNet: \_logic_net: (work@foo.out), line:9:36, endln:9:39 |vpiParent: - \_module: work@foo (work@foo), file:${SURELOG_DIR}/tests/FuncAttrib/dut.sv, line:9:1, endln:22:10 + \_module_inst: work@foo (work@foo), file:${SURELOG_DIR}/tests/FuncAttrib/dut.sv, line:9:1, endln:22:10 |vpiTypespec: \_logic_typespec: , line:14:8, endln:14:18 |vpiRange: @@ -801,7 +801,7 @@ design: (work@foo) |vpiPort: \_port: (clk), line:9:12, endln:9:15 |vpiParent: - \_module: work@foo (work@foo), file:${SURELOG_DIR}/tests/FuncAttrib/dut.sv, line:9:1, endln:22:10 + \_module_inst: work@foo (work@foo), file:${SURELOG_DIR}/tests/FuncAttrib/dut.sv, line:9:1, endln:22:10 |vpiName:clk |vpiDirection:1 |vpiLowConn: @@ -815,11 +815,11 @@ design: (work@foo) |vpiTypedef: \_logic_typespec: , line:10:8, endln:10:12 |vpiInstance: - \_module: work@foo (work@foo), file:${SURELOG_DIR}/tests/FuncAttrib/dut.sv, line:9:1, endln:22:10 + \_module_inst: work@foo (work@foo), file:${SURELOG_DIR}/tests/FuncAttrib/dut.sv, line:9:1, endln:22:10 |vpiPort: \_port: (rst), line:9:17, endln:9:20 |vpiParent: - \_module: work@foo (work@foo), file:${SURELOG_DIR}/tests/FuncAttrib/dut.sv, line:9:1, endln:22:10 + \_module_inst: work@foo (work@foo), file:${SURELOG_DIR}/tests/FuncAttrib/dut.sv, line:9:1, endln:22:10 |vpiName:rst |vpiDirection:1 |vpiLowConn: @@ -833,11 +833,11 @@ design: (work@foo) |vpiTypedef: \_logic_typespec: , line:11:8, endln:11:12 |vpiInstance: - \_module: work@foo (work@foo), file:${SURELOG_DIR}/tests/FuncAttrib/dut.sv, line:9:1, endln:22:10 + \_module_inst: work@foo (work@foo), file:${SURELOG_DIR}/tests/FuncAttrib/dut.sv, line:9:1, endln:22:10 |vpiPort: \_port: (inp_a), line:9:22, endln:9:27 |vpiParent: - \_module: work@foo (work@foo), file:${SURELOG_DIR}/tests/FuncAttrib/dut.sv, line:9:1, endln:22:10 + \_module_inst: work@foo (work@foo), file:${SURELOG_DIR}/tests/FuncAttrib/dut.sv, line:9:1, endln:22:10 |vpiName:inp_a |vpiDirection:1 |vpiLowConn: @@ -871,11 +871,11 @@ design: (work@foo) |UINT:0 |vpiConstType:9 |vpiInstance: - \_module: work@foo (work@foo), file:${SURELOG_DIR}/tests/FuncAttrib/dut.sv, line:9:1, endln:22:10 + \_module_inst: work@foo (work@foo), file:${SURELOG_DIR}/tests/FuncAttrib/dut.sv, line:9:1, endln:22:10 |vpiPort: \_port: (inp_b), line:9:29, endln:9:34 |vpiParent: - \_module: work@foo (work@foo), file:${SURELOG_DIR}/tests/FuncAttrib/dut.sv, line:9:1, endln:22:10 + \_module_inst: work@foo (work@foo), file:${SURELOG_DIR}/tests/FuncAttrib/dut.sv, line:9:1, endln:22:10 |vpiName:inp_b |vpiDirection:1 |vpiLowConn: @@ -909,11 +909,11 @@ design: (work@foo) |UINT:0 |vpiConstType:9 |vpiInstance: - \_module: work@foo (work@foo), file:${SURELOG_DIR}/tests/FuncAttrib/dut.sv, line:9:1, endln:22:10 + \_module_inst: work@foo (work@foo), file:${SURELOG_DIR}/tests/FuncAttrib/dut.sv, line:9:1, endln:22:10 |vpiPort: \_port: (out), line:9:36, endln:9:39 |vpiParent: - \_module: work@foo (work@foo), file:${SURELOG_DIR}/tests/FuncAttrib/dut.sv, line:9:1, endln:22:10 + \_module_inst: work@foo (work@foo), file:${SURELOG_DIR}/tests/FuncAttrib/dut.sv, line:9:1, endln:22:10 |vpiName:out |vpiDirection:2 |vpiLowConn: @@ -947,11 +947,11 @@ design: (work@foo) |UINT:0 |vpiConstType:9 |vpiInstance: - \_module: work@foo (work@foo), file:${SURELOG_DIR}/tests/FuncAttrib/dut.sv, line:9:1, endln:22:10 + \_module_inst: work@foo (work@foo), file:${SURELOG_DIR}/tests/FuncAttrib/dut.sv, line:9:1, endln:22:10 |vpiProcess: \_always: , line:16:1, endln:20:53 |vpiParent: - \_module: work@foo (work@foo), file:${SURELOG_DIR}/tests/FuncAttrib/dut.sv, line:9:1, endln:22:10 + \_module_inst: work@foo (work@foo), file:${SURELOG_DIR}/tests/FuncAttrib/dut.sv, line:9:1, endln:22:10 |vpiStmt: \_event_control: , line:16:8, endln:16:22 |vpiParent: diff --git a/tests/FuncBindGen/FuncBindGen.log b/tests/FuncBindGen/FuncBindGen.log index 902c9a1b41..5bf57180af 100644 --- a/tests/FuncBindGen/FuncBindGen.log +++ b/tests/FuncBindGen/FuncBindGen.log @@ -212,7 +212,7 @@ integer_typespec 1 logic_net 1 logic_typespec 2 logic_var 2 -module 5 +module_inst 5 operation 7 param_assign 4 parameter 4 @@ -239,7 +239,7 @@ integer_typespec 1 logic_net 1 logic_typespec 2 logic_var 5 -module 5 +module_inst 5 operation 9 param_assign 4 parameter 4 @@ -261,14 +261,14 @@ design: (work@top) |vpiElaborated:1 |vpiName:work@top |uhdmallModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/FuncBindGen/dut.sv, line:1:1, endln:14:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/FuncBindGen/dut.sv, line:1:1, endln:14:10 |vpiParent: \_design: (work@top) |vpiFullName:work@top |vpiParameter: \_parameter: (work@top.Depth), line:2:28, endln:2:33 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/FuncBindGen/dut.sv, line:1:1, endln:14:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/FuncBindGen/dut.sv, line:1:1, endln:14:10 |UINT:500 |vpiTypespec: \_int_typespec: , line:2:15, endln:2:27 @@ -279,7 +279,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.PTR_WIDTH), line:3:28, endln:3:37 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/FuncBindGen/dut.sv, line:1:1, endln:14:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/FuncBindGen/dut.sv, line:1:1, endln:14:10 |UINT:3 |vpiTypespec: \_int_typespec: , line:3:15, endln:3:27 @@ -291,7 +291,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:2:28, endln:2:40 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/FuncBindGen/dut.sv, line:1:1, endln:14:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/FuncBindGen/dut.sv, line:1:1, endln:14:10 |vpiRhs: \_constant: , line:2:37, endln:2:40 |vpiDecompile:500 @@ -305,7 +305,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:3:28, endln:3:41 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/FuncBindGen/dut.sv, line:1:1, endln:14:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/FuncBindGen/dut.sv, line:1:1, endln:14:10 |vpiRhs: \_constant: , line:3:40, endln:3:41 |vpiDecompile:3 @@ -320,13 +320,13 @@ design: (work@top) |vpiNet: \_logic_net: (work@top.o), line:1:23, endln:1:24 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/FuncBindGen/dut.sv, line:1:1, endln:14:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/FuncBindGen/dut.sv, line:1:1, endln:14:10 |vpiName:o |vpiFullName:work@top.o |vpiPort: \_port: (o), line:1:23, endln:1:24 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/FuncBindGen/dut.sv, line:1:1, endln:14:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/FuncBindGen/dut.sv, line:1:1, endln:14:10 |vpiName:o |vpiDirection:2 |vpiLowConn: @@ -337,12 +337,12 @@ design: (work@top) \_int_typespec: , line:1:19, endln:1:22 |vpiSigned:1 |uhdmtopModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/FuncBindGen/dut.sv, line:1:1, endln:14:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/FuncBindGen/dut.sv, line:1:1, endln:14:10 |vpiName:work@top |vpiVariables: \_int_var: (work@top.o), line:1:23, endln:1:24 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/FuncBindGen/dut.sv, line:1:1, endln:14:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/FuncBindGen/dut.sv, line:1:1, endln:14:10 |vpiTypespec: \_int_typespec: , line:1:19, endln:1:22 |vpiSigned:1 @@ -353,7 +353,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.Depth), line:2:28, endln:2:33 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/FuncBindGen/dut.sv, line:1:1, endln:14:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/FuncBindGen/dut.sv, line:1:1, endln:14:10 |UINT:500 |vpiTypespec: \_int_typespec: , line:2:15, endln:2:27 @@ -364,7 +364,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.PTR_WIDTH), line:3:28, endln:3:37 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/FuncBindGen/dut.sv, line:1:1, endln:14:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/FuncBindGen/dut.sv, line:1:1, endln:14:10 |UINT:3 |vpiTypespec: \_int_typespec: , line:3:15, endln:3:27 @@ -376,7 +376,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:2:28, endln:2:40 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/FuncBindGen/dut.sv, line:1:1, endln:14:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/FuncBindGen/dut.sv, line:1:1, endln:14:10 |vpiRhs: \_constant: , line:2:37, endln:2:40 |vpiDecompile:500 @@ -390,7 +390,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:3:28, endln:3:41 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/FuncBindGen/dut.sv, line:1:1, endln:14:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/FuncBindGen/dut.sv, line:1:1, endln:14:10 |vpiRhs: \_constant: , line:3:40, endln:3:41 |vpiDecompile:3 @@ -407,7 +407,7 @@ design: (work@top) |vpiPort: \_port: (o), line:1:23, endln:1:24 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/FuncBindGen/dut.sv, line:1:1, endln:14:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/FuncBindGen/dut.sv, line:1:1, endln:14:10 |vpiName:o |vpiDirection:2 |vpiLowConn: @@ -422,11 +422,11 @@ design: (work@top) \_int_typespec: , line:1:19, endln:1:22 |vpiSigned:1 |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/FuncBindGen/dut.sv, line:1:1, endln:14:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/FuncBindGen/dut.sv, line:1:1, endln:14:10 |vpiGenScopeArray: \_gen_scope_array: (work@top.gen_block), line:5:4, endln:12:7 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/FuncBindGen/dut.sv, line:1:1, endln:14:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/FuncBindGen/dut.sv, line:1:1, endln:14:10 |vpiName:gen_block |vpiFullName:work@top.gen_block |vpiGenScope: diff --git a/tests/FuncBinding/FuncBinding.log b/tests/FuncBinding/FuncBinding.log index 1b5deb2f6e..576507618e 100644 --- a/tests/FuncBinding/FuncBinding.log +++ b/tests/FuncBinding/FuncBinding.log @@ -45,7 +45,7 @@ io_decl 4 logic_net 8 logic_typespec 3 logic_var 1 -module 3 +module_inst 3 named_begin 2 operation 7 port 12 @@ -77,7 +77,7 @@ io_decl 8 logic_net 8 logic_typespec 3 logic_var 1 -module 3 +module_inst 3 named_begin 4 operation 14 port 18 @@ -97,17 +97,17 @@ design: (work@fsm_using_function) |vpiElaborated:1 |vpiName:work@fsm_using_function |uhdmallModules: -\_module: work@fsm_using_function (work@fsm_using_function), file:${SURELOG_DIR}/tests/FuncBinding/dut.sv, line:1:1, endln:53:10 +\_module_inst: work@fsm_using_function (work@fsm_using_function), file:${SURELOG_DIR}/tests/FuncBinding/dut.sv, line:1:1, endln:53:10 |vpiParent: \_design: (work@fsm_using_function) |vpiFullName:work@fsm_using_function |vpiTypedef: \_enum_typespec: (state), line:11:1, endln:11:61 |vpiParent: - \_module: work@fsm_using_function (work@fsm_using_function), file:${SURELOG_DIR}/tests/FuncBinding/dut.sv, line:1:1, endln:53:10 + \_module_inst: work@fsm_using_function (work@fsm_using_function), file:${SURELOG_DIR}/tests/FuncBinding/dut.sv, line:1:1, endln:53:10 |vpiName:state |vpiInstance: - \_module: work@fsm_using_function (work@fsm_using_function), file:${SURELOG_DIR}/tests/FuncBinding/dut.sv, line:1:1, endln:53:10 + \_module_inst: work@fsm_using_function (work@fsm_using_function), file:${SURELOG_DIR}/tests/FuncBinding/dut.sv, line:1:1, endln:53:10 |vpiBaseTypespec: \_logic_typespec: , line:11:14, endln:11:25 |vpiRange: @@ -150,14 +150,14 @@ design: (work@fsm_using_function) |vpiTaskFunc: \_function: (work@fsm_using_function.fsm_function), line:21:1, endln:42:12 |vpiParent: - \_module: work@fsm_using_function (work@fsm_using_function), file:${SURELOG_DIR}/tests/FuncBinding/dut.sv, line:1:1, endln:53:10 + \_module_inst: work@fsm_using_function (work@fsm_using_function), file:${SURELOG_DIR}/tests/FuncBinding/dut.sv, line:1:1, endln:53:10 |vpiName:fsm_function |vpiFullName:work@fsm_using_function.fsm_function |vpiVisibility:1 |vpiReturn: \_logic_var: |vpiParent: - \_module: work@fsm_using_function (work@fsm_using_function), file:${SURELOG_DIR}/tests/FuncBinding/dut.sv, line:1:1, endln:53:10 + \_module_inst: work@fsm_using_function (work@fsm_using_function), file:${SURELOG_DIR}/tests/FuncBinding/dut.sv, line:1:1, endln:53:10 |vpiIODecl: \_io_decl: (state), line:21:41, endln:21:46 |vpiDirection:1 @@ -585,59 +585,59 @@ design: (work@fsm_using_function) |vpiActual: \_io_decl: (future_state), line:21:100, endln:21:112 |vpiInstance: - \_module: work@fsm_using_function (work@fsm_using_function), file:${SURELOG_DIR}/tests/FuncBinding/dut.sv, line:1:1, endln:53:10 + \_module_inst: work@fsm_using_function (work@fsm_using_function), file:${SURELOG_DIR}/tests/FuncBinding/dut.sv, line:1:1, endln:53:10 |vpiNet: \_logic_net: (work@fsm_using_function.clock), line:2:11, endln:2:16 |vpiParent: - \_module: work@fsm_using_function (work@fsm_using_function), file:${SURELOG_DIR}/tests/FuncBinding/dut.sv, line:1:1, endln:53:10 + \_module_inst: work@fsm_using_function (work@fsm_using_function), file:${SURELOG_DIR}/tests/FuncBinding/dut.sv, line:1:1, endln:53:10 |vpiName:clock |vpiFullName:work@fsm_using_function.clock |vpiNet: \_logic_net: (work@fsm_using_function.reset), line:3:11, endln:3:16 |vpiParent: - \_module: work@fsm_using_function (work@fsm_using_function), file:${SURELOG_DIR}/tests/FuncBinding/dut.sv, line:1:1, endln:53:10 + \_module_inst: work@fsm_using_function (work@fsm_using_function), file:${SURELOG_DIR}/tests/FuncBinding/dut.sv, line:1:1, endln:53:10 |vpiName:reset |vpiFullName:work@fsm_using_function.reset |vpiNet: \_logic_net: (work@fsm_using_function.req_0), line:4:11, endln:4:16 |vpiParent: - \_module: work@fsm_using_function (work@fsm_using_function), file:${SURELOG_DIR}/tests/FuncBinding/dut.sv, line:1:1, endln:53:10 + \_module_inst: work@fsm_using_function (work@fsm_using_function), file:${SURELOG_DIR}/tests/FuncBinding/dut.sv, line:1:1, endln:53:10 |vpiName:req_0 |vpiFullName:work@fsm_using_function.req_0 |vpiNet: \_logic_net: (work@fsm_using_function.req_1), line:5:11, endln:5:16 |vpiParent: - \_module: work@fsm_using_function (work@fsm_using_function), file:${SURELOG_DIR}/tests/FuncBinding/dut.sv, line:1:1, endln:53:10 + \_module_inst: work@fsm_using_function (work@fsm_using_function), file:${SURELOG_DIR}/tests/FuncBinding/dut.sv, line:1:1, endln:53:10 |vpiName:req_1 |vpiFullName:work@fsm_using_function.req_1 |vpiNet: \_logic_net: (work@fsm_using_function.gnt_0), line:6:12, endln:6:17 |vpiParent: - \_module: work@fsm_using_function (work@fsm_using_function), file:${SURELOG_DIR}/tests/FuncBinding/dut.sv, line:1:1, endln:53:10 + \_module_inst: work@fsm_using_function (work@fsm_using_function), file:${SURELOG_DIR}/tests/FuncBinding/dut.sv, line:1:1, endln:53:10 |vpiName:gnt_0 |vpiFullName:work@fsm_using_function.gnt_0 |vpiNet: \_logic_net: (work@fsm_using_function.gnt_1), line:7:12, endln:7:17 |vpiParent: - \_module: work@fsm_using_function (work@fsm_using_function), file:${SURELOG_DIR}/tests/FuncBinding/dut.sv, line:1:1, endln:53:10 + \_module_inst: work@fsm_using_function (work@fsm_using_function), file:${SURELOG_DIR}/tests/FuncBinding/dut.sv, line:1:1, endln:53:10 |vpiName:gnt_1 |vpiFullName:work@fsm_using_function.gnt_1 |vpiNet: \_logic_net: (work@fsm_using_function.curr_state), line:12:7, endln:12:17 |vpiParent: - \_module: work@fsm_using_function (work@fsm_using_function), file:${SURELOG_DIR}/tests/FuncBinding/dut.sv, line:1:1, endln:53:10 + \_module_inst: work@fsm_using_function (work@fsm_using_function), file:${SURELOG_DIR}/tests/FuncBinding/dut.sv, line:1:1, endln:53:10 |vpiName:curr_state |vpiFullName:work@fsm_using_function.curr_state |vpiNet: \_logic_net: (work@fsm_using_function.next_state), line:12:19, endln:12:29 |vpiParent: - \_module: work@fsm_using_function (work@fsm_using_function), file:${SURELOG_DIR}/tests/FuncBinding/dut.sv, line:1:1, endln:53:10 + \_module_inst: work@fsm_using_function (work@fsm_using_function), file:${SURELOG_DIR}/tests/FuncBinding/dut.sv, line:1:1, endln:53:10 |vpiName:next_state |vpiFullName:work@fsm_using_function.next_state |vpiPort: \_port: (clock), line:2:11, endln:2:16 |vpiParent: - \_module: work@fsm_using_function (work@fsm_using_function), file:${SURELOG_DIR}/tests/FuncBinding/dut.sv, line:1:1, endln:53:10 + \_module_inst: work@fsm_using_function (work@fsm_using_function), file:${SURELOG_DIR}/tests/FuncBinding/dut.sv, line:1:1, endln:53:10 |vpiName:clock |vpiDirection:1 |vpiLowConn: @@ -650,7 +650,7 @@ design: (work@fsm_using_function) |vpiPort: \_port: (reset), line:3:11, endln:3:16 |vpiParent: - \_module: work@fsm_using_function (work@fsm_using_function), file:${SURELOG_DIR}/tests/FuncBinding/dut.sv, line:1:1, endln:53:10 + \_module_inst: work@fsm_using_function (work@fsm_using_function), file:${SURELOG_DIR}/tests/FuncBinding/dut.sv, line:1:1, endln:53:10 |vpiName:reset |vpiDirection:1 |vpiLowConn: @@ -663,7 +663,7 @@ design: (work@fsm_using_function) |vpiPort: \_port: (req_0), line:4:11, endln:4:16 |vpiParent: - \_module: work@fsm_using_function (work@fsm_using_function), file:${SURELOG_DIR}/tests/FuncBinding/dut.sv, line:1:1, endln:53:10 + \_module_inst: work@fsm_using_function (work@fsm_using_function), file:${SURELOG_DIR}/tests/FuncBinding/dut.sv, line:1:1, endln:53:10 |vpiName:req_0 |vpiDirection:1 |vpiLowConn: @@ -676,7 +676,7 @@ design: (work@fsm_using_function) |vpiPort: \_port: (req_1), line:5:11, endln:5:16 |vpiParent: - \_module: work@fsm_using_function (work@fsm_using_function), file:${SURELOG_DIR}/tests/FuncBinding/dut.sv, line:1:1, endln:53:10 + \_module_inst: work@fsm_using_function (work@fsm_using_function), file:${SURELOG_DIR}/tests/FuncBinding/dut.sv, line:1:1, endln:53:10 |vpiName:req_1 |vpiDirection:1 |vpiLowConn: @@ -689,7 +689,7 @@ design: (work@fsm_using_function) |vpiPort: \_port: (gnt_0), line:6:12, endln:6:17 |vpiParent: - \_module: work@fsm_using_function (work@fsm_using_function), file:${SURELOG_DIR}/tests/FuncBinding/dut.sv, line:1:1, endln:53:10 + \_module_inst: work@fsm_using_function (work@fsm_using_function), file:${SURELOG_DIR}/tests/FuncBinding/dut.sv, line:1:1, endln:53:10 |vpiName:gnt_0 |vpiDirection:2 |vpiLowConn: @@ -702,7 +702,7 @@ design: (work@fsm_using_function) |vpiPort: \_port: (gnt_1), line:7:12, endln:7:17 |vpiParent: - \_module: work@fsm_using_function (work@fsm_using_function), file:${SURELOG_DIR}/tests/FuncBinding/dut.sv, line:1:1, endln:53:10 + \_module_inst: work@fsm_using_function (work@fsm_using_function), file:${SURELOG_DIR}/tests/FuncBinding/dut.sv, line:1:1, endln:53:10 |vpiName:gnt_1 |vpiDirection:2 |vpiLowConn: @@ -715,7 +715,7 @@ design: (work@fsm_using_function) |vpiProcess: \_always: , line:15:1, endln:18:4 |vpiParent: - \_module: work@fsm_using_function (work@fsm_using_function), file:${SURELOG_DIR}/tests/FuncBinding/dut.sv, line:1:1, endln:53:10 + \_module_inst: work@fsm_using_function (work@fsm_using_function), file:${SURELOG_DIR}/tests/FuncBinding/dut.sv, line:1:1, endln:53:10 |vpiStmt: \_event_control: , line:15:8, endln:15:25 |vpiParent: @@ -794,7 +794,7 @@ design: (work@fsm_using_function) |vpiProcess: \_always: , line:45:1, endln:52:4 |vpiParent: - \_module: work@fsm_using_function (work@fsm_using_function), file:${SURELOG_DIR}/tests/FuncBinding/dut.sv, line:1:1, endln:53:10 + \_module_inst: work@fsm_using_function (work@fsm_using_function), file:${SURELOG_DIR}/tests/FuncBinding/dut.sv, line:1:1, endln:53:10 |vpiStmt: \_event_control: , line:45:8, endln:45:25 |vpiParent: @@ -907,12 +907,12 @@ design: (work@fsm_using_function) |#1 |vpiAlwaysType:1 |uhdmtopModules: -\_module: work@fsm_using_function (work@fsm_using_function), file:${SURELOG_DIR}/tests/FuncBinding/dut.sv, line:1:1, endln:53:10 +\_module_inst: work@fsm_using_function (work@fsm_using_function), file:${SURELOG_DIR}/tests/FuncBinding/dut.sv, line:1:1, endln:53:10 |vpiName:work@fsm_using_function |vpiVariables: \_bit_var: (work@fsm_using_function.clock), line:2:11, endln:2:16 |vpiParent: - \_module: work@fsm_using_function (work@fsm_using_function), file:${SURELOG_DIR}/tests/FuncBinding/dut.sv, line:1:1, endln:53:10 + \_module_inst: work@fsm_using_function (work@fsm_using_function), file:${SURELOG_DIR}/tests/FuncBinding/dut.sv, line:1:1, endln:53:10 |vpiTypespec: \_bit_typespec: , line:2:7, endln:2:10 |vpiSigned:1 @@ -922,7 +922,7 @@ design: (work@fsm_using_function) |vpiVariables: \_bit_var: (work@fsm_using_function.reset), line:3:11, endln:3:16 |vpiParent: - \_module: work@fsm_using_function (work@fsm_using_function), file:${SURELOG_DIR}/tests/FuncBinding/dut.sv, line:1:1, endln:53:10 + \_module_inst: work@fsm_using_function (work@fsm_using_function), file:${SURELOG_DIR}/tests/FuncBinding/dut.sv, line:1:1, endln:53:10 |vpiTypespec: \_bit_typespec: , line:3:7, endln:3:10 |vpiSigned:1 @@ -932,7 +932,7 @@ design: (work@fsm_using_function) |vpiVariables: \_bit_var: (work@fsm_using_function.req_0), line:4:11, endln:4:16 |vpiParent: - \_module: work@fsm_using_function (work@fsm_using_function), file:${SURELOG_DIR}/tests/FuncBinding/dut.sv, line:1:1, endln:53:10 + \_module_inst: work@fsm_using_function (work@fsm_using_function), file:${SURELOG_DIR}/tests/FuncBinding/dut.sv, line:1:1, endln:53:10 |vpiTypespec: \_bit_typespec: , line:4:7, endln:4:10 |vpiSigned:1 @@ -942,7 +942,7 @@ design: (work@fsm_using_function) |vpiVariables: \_bit_var: (work@fsm_using_function.req_1), line:5:11, endln:5:16 |vpiParent: - \_module: work@fsm_using_function (work@fsm_using_function), file:${SURELOG_DIR}/tests/FuncBinding/dut.sv, line:1:1, endln:53:10 + \_module_inst: work@fsm_using_function (work@fsm_using_function), file:${SURELOG_DIR}/tests/FuncBinding/dut.sv, line:1:1, endln:53:10 |vpiTypespec: \_bit_typespec: , line:5:7, endln:5:10 |vpiSigned:1 @@ -952,7 +952,7 @@ design: (work@fsm_using_function) |vpiVariables: \_bit_var: (work@fsm_using_function.gnt_0), line:6:12, endln:6:17 |vpiParent: - \_module: work@fsm_using_function (work@fsm_using_function), file:${SURELOG_DIR}/tests/FuncBinding/dut.sv, line:1:1, endln:53:10 + \_module_inst: work@fsm_using_function (work@fsm_using_function), file:${SURELOG_DIR}/tests/FuncBinding/dut.sv, line:1:1, endln:53:10 |vpiTypespec: \_bit_typespec: , line:6:8, endln:6:11 |vpiSigned:1 @@ -962,7 +962,7 @@ design: (work@fsm_using_function) |vpiVariables: \_bit_var: (work@fsm_using_function.gnt_1), line:7:12, endln:7:17 |vpiParent: - \_module: work@fsm_using_function (work@fsm_using_function), file:${SURELOG_DIR}/tests/FuncBinding/dut.sv, line:1:1, endln:53:10 + \_module_inst: work@fsm_using_function (work@fsm_using_function), file:${SURELOG_DIR}/tests/FuncBinding/dut.sv, line:1:1, endln:53:10 |vpiTypespec: \_bit_typespec: , line:7:8, endln:7:11 |vpiSigned:1 @@ -972,7 +972,7 @@ design: (work@fsm_using_function) |vpiVariables: \_enum_var: (work@fsm_using_function.curr_state), line:12:7, endln:12:17 |vpiParent: - \_module: work@fsm_using_function (work@fsm_using_function), file:${SURELOG_DIR}/tests/FuncBinding/dut.sv, line:1:1, endln:53:10 + \_module_inst: work@fsm_using_function (work@fsm_using_function), file:${SURELOG_DIR}/tests/FuncBinding/dut.sv, line:1:1, endln:53:10 |vpiTypespec: \_enum_typespec: (state), line:11:1, endln:11:61 |vpiName:curr_state @@ -981,7 +981,7 @@ design: (work@fsm_using_function) |vpiVariables: \_enum_var: (work@fsm_using_function.next_state), line:12:19, endln:12:29 |vpiParent: - \_module: work@fsm_using_function (work@fsm_using_function), file:${SURELOG_DIR}/tests/FuncBinding/dut.sv, line:1:1, endln:53:10 + \_module_inst: work@fsm_using_function (work@fsm_using_function), file:${SURELOG_DIR}/tests/FuncBinding/dut.sv, line:1:1, endln:53:10 |vpiTypespec: \_enum_typespec: (state), line:11:1, endln:11:61 |vpiName:next_state @@ -994,14 +994,14 @@ design: (work@fsm_using_function) |vpiTaskFunc: \_function: (work@fsm_using_function.fsm_function), line:21:1, endln:42:12 |vpiParent: - \_module: work@fsm_using_function (work@fsm_using_function), file:${SURELOG_DIR}/tests/FuncBinding/dut.sv, line:1:1, endln:53:10 + \_module_inst: work@fsm_using_function (work@fsm_using_function), file:${SURELOG_DIR}/tests/FuncBinding/dut.sv, line:1:1, endln:53:10 |vpiName:fsm_function |vpiFullName:work@fsm_using_function.fsm_function |vpiVisibility:1 |vpiReturn: \_logic_var: |vpiParent: - \_module: work@fsm_using_function (work@fsm_using_function), file:${SURELOG_DIR}/tests/FuncBinding/dut.sv, line:1:1, endln:53:10 + \_module_inst: work@fsm_using_function (work@fsm_using_function), file:${SURELOG_DIR}/tests/FuncBinding/dut.sv, line:1:1, endln:53:10 |vpiIODecl: \_io_decl: (state), line:21:41, endln:21:46 |vpiParent: @@ -1375,12 +1375,12 @@ design: (work@fsm_using_function) |vpiActual: \_io_decl: (future_state), line:21:100, endln:21:112 |vpiInstance: - \_module: work@fsm_using_function (work@fsm_using_function), file:${SURELOG_DIR}/tests/FuncBinding/dut.sv, line:1:1, endln:53:10 + \_module_inst: work@fsm_using_function (work@fsm_using_function), file:${SURELOG_DIR}/tests/FuncBinding/dut.sv, line:1:1, endln:53:10 |vpiTopModule:1 |vpiPort: \_port: (clock), line:2:11, endln:2:16 |vpiParent: - \_module: work@fsm_using_function (work@fsm_using_function), file:${SURELOG_DIR}/tests/FuncBinding/dut.sv, line:1:1, endln:53:10 + \_module_inst: work@fsm_using_function (work@fsm_using_function), file:${SURELOG_DIR}/tests/FuncBinding/dut.sv, line:1:1, endln:53:10 |vpiName:clock |vpiDirection:1 |vpiLowConn: @@ -1395,11 +1395,11 @@ design: (work@fsm_using_function) \_bit_typespec: , line:2:7, endln:2:10 |vpiSigned:1 |vpiInstance: - \_module: work@fsm_using_function (work@fsm_using_function), file:${SURELOG_DIR}/tests/FuncBinding/dut.sv, line:1:1, endln:53:10 + \_module_inst: work@fsm_using_function (work@fsm_using_function), file:${SURELOG_DIR}/tests/FuncBinding/dut.sv, line:1:1, endln:53:10 |vpiPort: \_port: (reset), line:3:11, endln:3:16 |vpiParent: - \_module: work@fsm_using_function (work@fsm_using_function), file:${SURELOG_DIR}/tests/FuncBinding/dut.sv, line:1:1, endln:53:10 + \_module_inst: work@fsm_using_function (work@fsm_using_function), file:${SURELOG_DIR}/tests/FuncBinding/dut.sv, line:1:1, endln:53:10 |vpiName:reset |vpiDirection:1 |vpiLowConn: @@ -1414,11 +1414,11 @@ design: (work@fsm_using_function) \_bit_typespec: , line:3:7, endln:3:10 |vpiSigned:1 |vpiInstance: - \_module: work@fsm_using_function (work@fsm_using_function), file:${SURELOG_DIR}/tests/FuncBinding/dut.sv, line:1:1, endln:53:10 + \_module_inst: work@fsm_using_function (work@fsm_using_function), file:${SURELOG_DIR}/tests/FuncBinding/dut.sv, line:1:1, endln:53:10 |vpiPort: \_port: (req_0), line:4:11, endln:4:16 |vpiParent: - \_module: work@fsm_using_function (work@fsm_using_function), file:${SURELOG_DIR}/tests/FuncBinding/dut.sv, line:1:1, endln:53:10 + \_module_inst: work@fsm_using_function (work@fsm_using_function), file:${SURELOG_DIR}/tests/FuncBinding/dut.sv, line:1:1, endln:53:10 |vpiName:req_0 |vpiDirection:1 |vpiLowConn: @@ -1433,11 +1433,11 @@ design: (work@fsm_using_function) \_bit_typespec: , line:4:7, endln:4:10 |vpiSigned:1 |vpiInstance: - \_module: work@fsm_using_function (work@fsm_using_function), file:${SURELOG_DIR}/tests/FuncBinding/dut.sv, line:1:1, endln:53:10 + \_module_inst: work@fsm_using_function (work@fsm_using_function), file:${SURELOG_DIR}/tests/FuncBinding/dut.sv, line:1:1, endln:53:10 |vpiPort: \_port: (req_1), line:5:11, endln:5:16 |vpiParent: - \_module: work@fsm_using_function (work@fsm_using_function), file:${SURELOG_DIR}/tests/FuncBinding/dut.sv, line:1:1, endln:53:10 + \_module_inst: work@fsm_using_function (work@fsm_using_function), file:${SURELOG_DIR}/tests/FuncBinding/dut.sv, line:1:1, endln:53:10 |vpiName:req_1 |vpiDirection:1 |vpiLowConn: @@ -1452,11 +1452,11 @@ design: (work@fsm_using_function) \_bit_typespec: , line:5:7, endln:5:10 |vpiSigned:1 |vpiInstance: - \_module: work@fsm_using_function (work@fsm_using_function), file:${SURELOG_DIR}/tests/FuncBinding/dut.sv, line:1:1, endln:53:10 + \_module_inst: work@fsm_using_function (work@fsm_using_function), file:${SURELOG_DIR}/tests/FuncBinding/dut.sv, line:1:1, endln:53:10 |vpiPort: \_port: (gnt_0), line:6:12, endln:6:17 |vpiParent: - \_module: work@fsm_using_function (work@fsm_using_function), file:${SURELOG_DIR}/tests/FuncBinding/dut.sv, line:1:1, endln:53:10 + \_module_inst: work@fsm_using_function (work@fsm_using_function), file:${SURELOG_DIR}/tests/FuncBinding/dut.sv, line:1:1, endln:53:10 |vpiName:gnt_0 |vpiDirection:2 |vpiLowConn: @@ -1471,11 +1471,11 @@ design: (work@fsm_using_function) \_bit_typespec: , line:6:8, endln:6:11 |vpiSigned:1 |vpiInstance: - \_module: work@fsm_using_function (work@fsm_using_function), file:${SURELOG_DIR}/tests/FuncBinding/dut.sv, line:1:1, endln:53:10 + \_module_inst: work@fsm_using_function (work@fsm_using_function), file:${SURELOG_DIR}/tests/FuncBinding/dut.sv, line:1:1, endln:53:10 |vpiPort: \_port: (gnt_1), line:7:12, endln:7:17 |vpiParent: - \_module: work@fsm_using_function (work@fsm_using_function), file:${SURELOG_DIR}/tests/FuncBinding/dut.sv, line:1:1, endln:53:10 + \_module_inst: work@fsm_using_function (work@fsm_using_function), file:${SURELOG_DIR}/tests/FuncBinding/dut.sv, line:1:1, endln:53:10 |vpiName:gnt_1 |vpiDirection:2 |vpiLowConn: @@ -1490,11 +1490,11 @@ design: (work@fsm_using_function) \_bit_typespec: , line:7:8, endln:7:11 |vpiSigned:1 |vpiInstance: - \_module: work@fsm_using_function (work@fsm_using_function), file:${SURELOG_DIR}/tests/FuncBinding/dut.sv, line:1:1, endln:53:10 + \_module_inst: work@fsm_using_function (work@fsm_using_function), file:${SURELOG_DIR}/tests/FuncBinding/dut.sv, line:1:1, endln:53:10 |vpiProcess: \_always: , line:15:1, endln:18:4 |vpiParent: - \_module: work@fsm_using_function (work@fsm_using_function), file:${SURELOG_DIR}/tests/FuncBinding/dut.sv, line:1:1, endln:53:10 + \_module_inst: work@fsm_using_function (work@fsm_using_function), file:${SURELOG_DIR}/tests/FuncBinding/dut.sv, line:1:1, endln:53:10 |vpiStmt: \_event_control: , line:15:8, endln:15:25 |vpiParent: @@ -1573,7 +1573,7 @@ design: (work@fsm_using_function) |vpiProcess: \_always: , line:45:1, endln:52:4 |vpiParent: - \_module: work@fsm_using_function (work@fsm_using_function), file:${SURELOG_DIR}/tests/FuncBinding/dut.sv, line:1:1, endln:53:10 + \_module_inst: work@fsm_using_function (work@fsm_using_function), file:${SURELOG_DIR}/tests/FuncBinding/dut.sv, line:1:1, endln:53:10 |vpiStmt: \_event_control: , line:45:8, endln:45:25 |vpiParent: diff --git a/tests/FuncBinding2/FuncBinding2.log b/tests/FuncBinding2/FuncBinding2.log index 26b55bd56d..3beeefd613 100644 --- a/tests/FuncBinding2/FuncBinding2.log +++ b/tests/FuncBinding2/FuncBinding2.log @@ -40,7 +40,7 @@ io_decl 1 logic_net 6 logic_typespec 11 logic_var 3 -module 5 +module_inst 5 operation 2 param_assign 2 parameter 2 @@ -68,7 +68,7 @@ io_decl 2 logic_net 6 logic_typespec 11 logic_var 4 -module 5 +module_inst 5 operation 4 param_assign 2 parameter 2 @@ -89,14 +89,14 @@ design: (work@vend) |vpiElaborated:1 |vpiName:work@vend |uhdmallModules: -\_module: work@vend (work@vend), file:${SURELOG_DIR}/tests/FuncBinding2/dut.sv, line:1:1, endln:33:10 +\_module_inst: work@vend (work@vend), file:${SURELOG_DIR}/tests/FuncBinding2/dut.sv, line:1:1, endln:33:10 |vpiParent: \_design: (work@vend) |vpiFullName:work@vend |vpiParameter: \_parameter: (work@vend.s0), line:7:11, endln:7:13 |vpiParent: - \_module: work@vend (work@vend), file:${SURELOG_DIR}/tests/FuncBinding2/dut.sv, line:1:1, endln:33:10 + \_module_inst: work@vend (work@vend), file:${SURELOG_DIR}/tests/FuncBinding2/dut.sv, line:1:1, endln:33:10 |BIN:00 |vpiTypespec: \_int_typespec: @@ -113,7 +113,7 @@ design: (work@vend) |vpiParamAssign: \_param_assign: , line:7:11, endln:7:21 |vpiParent: - \_module: work@vend (work@vend), file:${SURELOG_DIR}/tests/FuncBinding2/dut.sv, line:1:1, endln:33:10 + \_module_inst: work@vend (work@vend), file:${SURELOG_DIR}/tests/FuncBinding2/dut.sv, line:1:1, endln:33:10 |vpiRhs: \_constant: , line:7:16, endln:7:21 |vpiDecompile:2'b00 @@ -128,7 +128,7 @@ design: (work@vend) |vpiTaskFunc: \_function: (work@vend.fsm), line:10:1, endln:26:12 |vpiParent: - \_module: work@vend (work@vend), file:${SURELOG_DIR}/tests/FuncBinding2/dut.sv, line:1:1, endln:33:10 + \_module_inst: work@vend (work@vend), file:${SURELOG_DIR}/tests/FuncBinding2/dut.sv, line:1:1, endln:33:10 |vpiName:fsm |vpiFullName:work@vend.fsm |vpiVariables: @@ -161,7 +161,7 @@ design: (work@vend) |UINT:0 |vpiConstType:9 |vpiParent: - \_module: work@vend (work@vend), file:${SURELOG_DIR}/tests/FuncBinding2/dut.sv, line:1:1, endln:33:10 + \_module_inst: work@vend (work@vend), file:${SURELOG_DIR}/tests/FuncBinding2/dut.sv, line:1:1, endln:33:10 |vpiIODecl: \_io_decl: (fsm_PRES_STATE), line:11:13, endln:11:27 |vpiParent: @@ -298,24 +298,24 @@ design: (work@vend) |vpiActual: \_logic_var: (fsm), line:10:10, endln:10:15 |vpiInstance: - \_module: work@vend (work@vend), file:${SURELOG_DIR}/tests/FuncBinding2/dut.sv, line:1:1, endln:33:10 + \_module_inst: work@vend (work@vend), file:${SURELOG_DIR}/tests/FuncBinding2/dut.sv, line:1:1, endln:33:10 |vpiNet: \_logic_net: (work@vend.newspaper), line:5:6, endln:5:15 |vpiParent: - \_module: work@vend (work@vend), file:${SURELOG_DIR}/tests/FuncBinding2/dut.sv, line:1:1, endln:33:10 + \_module_inst: work@vend (work@vend), file:${SURELOG_DIR}/tests/FuncBinding2/dut.sv, line:1:1, endln:33:10 |vpiName:newspaper |vpiFullName:work@vend.newspaper |vpiNetType:1 |vpiNet: \_logic_net: (work@vend.clock), line:1:13, endln:1:18 |vpiParent: - \_module: work@vend (work@vend), file:${SURELOG_DIR}/tests/FuncBinding2/dut.sv, line:1:1, endln:33:10 + \_module_inst: work@vend (work@vend), file:${SURELOG_DIR}/tests/FuncBinding2/dut.sv, line:1:1, endln:33:10 |vpiName:clock |vpiFullName:work@vend.clock |vpiPort: \_port: (clock), line:1:13, endln:1:18 |vpiParent: - \_module: work@vend (work@vend), file:${SURELOG_DIR}/tests/FuncBinding2/dut.sv, line:1:1, endln:33:10 + \_module_inst: work@vend (work@vend), file:${SURELOG_DIR}/tests/FuncBinding2/dut.sv, line:1:1, endln:33:10 |vpiName:clock |vpiDirection:1 |vpiLowConn: @@ -327,7 +327,7 @@ design: (work@vend) |vpiPort: \_port: (newspaper), line:1:20, endln:1:29 |vpiParent: - \_module: work@vend (work@vend), file:${SURELOG_DIR}/tests/FuncBinding2/dut.sv, line:1:1, endln:33:10 + \_module_inst: work@vend (work@vend), file:${SURELOG_DIR}/tests/FuncBinding2/dut.sv, line:1:1, endln:33:10 |vpiName:newspaper |vpiDirection:2 |vpiLowConn: @@ -339,7 +339,7 @@ design: (work@vend) |vpiProcess: \_always: , line:28:1, endln:31:4 |vpiParent: - \_module: work@vend (work@vend), file:${SURELOG_DIR}/tests/FuncBinding2/dut.sv, line:1:1, endln:33:10 + \_module_inst: work@vend (work@vend), file:${SURELOG_DIR}/tests/FuncBinding2/dut.sv, line:1:1, endln:33:10 |vpiStmt: \_event_control: , line:28:8, endln:28:24 |vpiParent: @@ -391,12 +391,12 @@ design: (work@vend) \_logic_net: (work@vend.newspaper), line:5:6, endln:5:15 |vpiAlwaysType:1 |uhdmtopModules: -\_module: work@vend (work@vend), file:${SURELOG_DIR}/tests/FuncBinding2/dut.sv, line:1:1, endln:33:10 +\_module_inst: work@vend (work@vend), file:${SURELOG_DIR}/tests/FuncBinding2/dut.sv, line:1:1, endln:33:10 |vpiName:work@vend |vpiParameter: \_parameter: (work@vend.s0), line:7:11, endln:7:13 |vpiParent: - \_module: work@vend (work@vend), file:${SURELOG_DIR}/tests/FuncBinding2/dut.sv, line:1:1, endln:33:10 + \_module_inst: work@vend (work@vend), file:${SURELOG_DIR}/tests/FuncBinding2/dut.sv, line:1:1, endln:33:10 |BIN:00 |vpiTypespec: \_int_typespec: @@ -421,7 +421,7 @@ design: (work@vend) |vpiParamAssign: \_param_assign: , line:7:11, endln:7:21 |vpiParent: - \_module: work@vend (work@vend), file:${SURELOG_DIR}/tests/FuncBinding2/dut.sv, line:1:1, endln:33:10 + \_module_inst: work@vend (work@vend), file:${SURELOG_DIR}/tests/FuncBinding2/dut.sv, line:1:1, endln:33:10 |vpiRhs: \_constant: , line:7:16, endln:7:21 |vpiDecompile:2'b00 @@ -437,7 +437,7 @@ design: (work@vend) |vpiTaskFunc: \_function: (work@vend.fsm), line:10:1, endln:26:12 |vpiParent: - \_module: work@vend (work@vend), file:${SURELOG_DIR}/tests/FuncBinding2/dut.sv, line:1:1, endln:33:10 + \_module_inst: work@vend (work@vend), file:${SURELOG_DIR}/tests/FuncBinding2/dut.sv, line:1:1, endln:33:10 |vpiName:fsm |vpiFullName:work@vend.fsm |vpiVariables: @@ -453,7 +453,7 @@ design: (work@vend) |vpiReturn: \_logic_var: , line:10:10, endln:10:15 |vpiParent: - \_module: work@vend (work@vend), file:${SURELOG_DIR}/tests/FuncBinding2/dut.sv, line:1:1, endln:33:10 + \_module_inst: work@vend (work@vend), file:${SURELOG_DIR}/tests/FuncBinding2/dut.sv, line:1:1, endln:33:10 |vpiIODecl: \_io_decl: (fsm_PRES_STATE), line:11:13, endln:11:27 |vpiParent: @@ -560,11 +560,11 @@ design: (work@vend) |vpiActual: \_logic_var: , line:10:10, endln:10:15 |vpiInstance: - \_module: work@vend (work@vend), file:${SURELOG_DIR}/tests/FuncBinding2/dut.sv, line:1:1, endln:33:10 + \_module_inst: work@vend (work@vend), file:${SURELOG_DIR}/tests/FuncBinding2/dut.sv, line:1:1, endln:33:10 |vpiNet: \_logic_net: (work@vend.newspaper), line:5:6, endln:5:15 |vpiParent: - \_module: work@vend (work@vend), file:${SURELOG_DIR}/tests/FuncBinding2/dut.sv, line:1:1, endln:33:10 + \_module_inst: work@vend (work@vend), file:${SURELOG_DIR}/tests/FuncBinding2/dut.sv, line:1:1, endln:33:10 |vpiTypespec: \_logic_typespec: , line:5:1, endln:5:5 |vpiName:newspaper @@ -573,7 +573,7 @@ design: (work@vend) |vpiNet: \_logic_net: (work@vend.clock), line:1:13, endln:1:18 |vpiParent: - \_module: work@vend (work@vend), file:${SURELOG_DIR}/tests/FuncBinding2/dut.sv, line:1:1, endln:33:10 + \_module_inst: work@vend (work@vend), file:${SURELOG_DIR}/tests/FuncBinding2/dut.sv, line:1:1, endln:33:10 |vpiTypespec: \_logic_typespec: , line:3:7, endln:3:7 |vpiName:clock @@ -590,7 +590,7 @@ design: (work@vend) |vpiPort: \_port: (clock), line:1:13, endln:1:18 |vpiParent: - \_module: work@vend (work@vend), file:${SURELOG_DIR}/tests/FuncBinding2/dut.sv, line:1:1, endln:33:10 + \_module_inst: work@vend (work@vend), file:${SURELOG_DIR}/tests/FuncBinding2/dut.sv, line:1:1, endln:33:10 |vpiName:clock |vpiDirection:1 |vpiLowConn: @@ -604,11 +604,11 @@ design: (work@vend) |vpiTypedef: \_logic_typespec: , line:3:7, endln:3:7 |vpiInstance: - \_module: work@vend (work@vend), file:${SURELOG_DIR}/tests/FuncBinding2/dut.sv, line:1:1, endln:33:10 + \_module_inst: work@vend (work@vend), file:${SURELOG_DIR}/tests/FuncBinding2/dut.sv, line:1:1, endln:33:10 |vpiPort: \_port: (newspaper), line:1:20, endln:1:29 |vpiParent: - \_module: work@vend (work@vend), file:${SURELOG_DIR}/tests/FuncBinding2/dut.sv, line:1:1, endln:33:10 + \_module_inst: work@vend (work@vend), file:${SURELOG_DIR}/tests/FuncBinding2/dut.sv, line:1:1, endln:33:10 |vpiName:newspaper |vpiDirection:2 |vpiLowConn: @@ -622,11 +622,11 @@ design: (work@vend) |vpiTypedef: \_logic_typespec: , line:4:8, endln:4:8 |vpiInstance: - \_module: work@vend (work@vend), file:${SURELOG_DIR}/tests/FuncBinding2/dut.sv, line:1:1, endln:33:10 + \_module_inst: work@vend (work@vend), file:${SURELOG_DIR}/tests/FuncBinding2/dut.sv, line:1:1, endln:33:10 |vpiProcess: \_always: , line:28:1, endln:31:4 |vpiParent: - \_module: work@vend (work@vend), file:${SURELOG_DIR}/tests/FuncBinding2/dut.sv, line:1:1, endln:33:10 + \_module_inst: work@vend (work@vend), file:${SURELOG_DIR}/tests/FuncBinding2/dut.sv, line:1:1, endln:33:10 |vpiStmt: \_event_control: , line:28:8, endln:28:24 |vpiParent: diff --git a/tests/FuncCase/FuncCase.log b/tests/FuncCase/FuncCase.log index 8d113a6307..d8134a9cdf 100644 --- a/tests/FuncCase/FuncCase.log +++ b/tests/FuncCase/FuncCase.log @@ -63,7 +63,7 @@ int_typespec 2 int_var 2 io_decl 2 logic_typespec 2 -module 8 +module_inst 8 operation 1 package 3 param_assign 4 @@ -302,7 +302,7 @@ design: (work@top) |vpiTypedef: \_enum_typespec: (fpnew_pkg::opgroup_e), line:2:1, endln:4:15 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/FuncCase/dut.sv, line:22:1, endln:30:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/FuncCase/dut.sv, line:22:1, endln:30:10 |vpiName:fpnew_pkg::opgroup_e |vpiInstance: \_package: fpnew_pkg (fpnew_pkg::), file:${SURELOG_DIR}/tests/FuncCase/dut.sv, line:1:1, endln:17:11 @@ -505,26 +505,26 @@ design: (work@top) |vpiInstance: \_package: fpnew_pkg (fpnew_pkg::), file:${SURELOG_DIR}/tests/FuncCase/dut.sv, line:1:1, endln:17:11 |uhdmallModules: -\_module: work@GOOD (work@GOOD), file:${SURELOG_DIR}/tests/FuncCase/dut.sv, line:19:1, endln:20:10 +\_module_inst: work@GOOD (work@GOOD), file:${SURELOG_DIR}/tests/FuncCase/dut.sv, line:19:1, endln:20:10 |vpiParent: \_design: (work@top) |vpiFullName:work@GOOD |vpiDefName:work@GOOD |uhdmallModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/FuncCase/dut.sv, line:22:1, endln:30:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/FuncCase/dut.sv, line:22:1, endln:30:10 |vpiParent: \_design: (work@top) |vpiFullName:work@top |vpiParameter: \_parameter: (work@top.p), line:25:14, endln:25:15 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/FuncCase/dut.sv, line:22:1, endln:30:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/FuncCase/dut.sv, line:22:1, endln:30:10 |vpiName:p |vpiFullName:work@top.p |vpiParamAssign: \_param_assign: , line:25:14, endln:25:39 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/FuncCase/dut.sv, line:22:1, endln:30:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/FuncCase/dut.sv, line:22:1, endln:30:10 |vpiRhs: \_func_call: (num_operands), line:25:18, endln:25:30 |vpiArgument: @@ -547,18 +547,18 @@ design: (work@top) |vpiTaskFunc: \_function: (fpnew_pkg::num_operands), line:7:1, endln:15:14 |uhdmtopModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/FuncCase/dut.sv, line:22:1, endln:30:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/FuncCase/dut.sv, line:22:1, endln:30:10 |vpiName:work@top |vpiParameter: \_parameter: (work@top.p), line:25:14, endln:25:15 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/FuncCase/dut.sv, line:22:1, endln:30:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/FuncCase/dut.sv, line:22:1, endln:30:10 |vpiName:p |vpiFullName:work@top.p |vpiParamAssign: \_param_assign: , line:25:14, endln:25:39 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/FuncCase/dut.sv, line:22:1, endln:30:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/FuncCase/dut.sv, line:22:1, endln:30:10 |vpiRhs: \_constant: , line:25:18, endln:25:39 |vpiDecompile:2 @@ -579,7 +579,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.genblk1), line:27:4, endln:29:7 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/FuncCase/dut.sv, line:22:1, endln:30:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/FuncCase/dut.sv, line:22:1, endln:30:10 |vpiName:genblk1 |vpiFullName:work@top.genblk1 |vpiGenScope: @@ -587,8 +587,8 @@ design: (work@top) |vpiParent: \_gen_scope_array: (work@top.genblk1), line:27:4, endln:29:7 |vpiFullName:work@top.genblk1 - |vpiModule: - \_module: work@GOOD (work@top.genblk1.good), file:${SURELOG_DIR}/tests/FuncCase/dut.sv, line:28:6, endln:28:18 + |vpiModuleInst: + \_module_inst: work@GOOD (work@top.genblk1.good), file:${SURELOG_DIR}/tests/FuncCase/dut.sv, line:28:6, endln:28:18 |vpiParent: \_gen_scope: (work@top.genblk1) |vpiName:good diff --git a/tests/FuncDeclScope/FuncDeclScope.log b/tests/FuncDeclScope/FuncDeclScope.log index 5dc08f4a3e..7396335e89 100644 --- a/tests/FuncDeclScope/FuncDeclScope.log +++ b/tests/FuncDeclScope/FuncDeclScope.log @@ -329,9 +329,9 @@ gen_scope 4 gen_scope_array 4 int_typespec 9 int_var 5 -interface 3 +interface_inst 3 logic_net 2 -module 10 +module_inst 10 operation 2 param_assign 6 parameter 6 @@ -350,9 +350,9 @@ gen_scope 5 gen_scope_array 5 int_typespec 9 int_var 5 -interface 3 +interface_inst 3 logic_net 2 -module 10 +module_inst 10 operation 2 param_assign 6 parameter 6 @@ -372,14 +372,14 @@ design: (work@top) |vpiElaborated:1 |vpiName:work@top |uhdmallInterfaces: -\_interface: work@intf (work@intf), file:${SURELOG_DIR}/tests/FuncDeclScope/dut.sv, line:1:1, endln:18:13 +\_interface_inst: work@intf (work@intf), file:${SURELOG_DIR}/tests/FuncDeclScope/dut.sv, line:1:1, endln:18:13 |vpiParent: \_design: (work@top) |vpiFullName:work@intf |vpiParameter: \_parameter: (work@intf.Depth), line:2:27, endln:2:32 |vpiParent: - \_interface: work@intf (work@intf), file:${SURELOG_DIR}/tests/FuncDeclScope/dut.sv, line:1:1, endln:18:13 + \_interface_inst: work@intf (work@intf), file:${SURELOG_DIR}/tests/FuncDeclScope/dut.sv, line:1:1, endln:18:13 |UINT:4 |vpiTypespec: \_int_typespec: , line:2:14, endln:2:26 @@ -390,7 +390,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:2:27, endln:2:36 |vpiParent: - \_interface: work@intf (work@intf), file:${SURELOG_DIR}/tests/FuncDeclScope/dut.sv, line:1:1, endln:18:13 + \_interface_inst: work@intf (work@intf), file:${SURELOG_DIR}/tests/FuncDeclScope/dut.sv, line:1:1, endln:18:13 |vpiRhs: \_constant: , line:2:35, endln:2:36 |vpiDecompile:4 @@ -405,28 +405,28 @@ design: (work@top) |vpiTaskFunc: \_function: (work@intf.get2), line:5:4, endln:7:18 |vpiParent: - \_interface: work@intf (work@intf), file:${SURELOG_DIR}/tests/FuncDeclScope/dut.sv, line:1:1, endln:18:13 + \_interface_inst: work@intf (work@intf), file:${SURELOG_DIR}/tests/FuncDeclScope/dut.sv, line:1:1, endln:18:13 |vpiName:get2 |vpiFullName:work@intf.get2 |vpiParent: - \_interface: work@intf (work@intf), file:${SURELOG_DIR}/tests/FuncDeclScope/dut.sv, line:1:1, endln:18:13 + \_interface_inst: work@intf (work@intf), file:${SURELOG_DIR}/tests/FuncDeclScope/dut.sv, line:1:1, endln:18:13 |vpiInstance: - \_interface: work@intf (work@intf), file:${SURELOG_DIR}/tests/FuncDeclScope/dut.sv, line:1:1, endln:18:13 + \_interface_inst: work@intf (work@intf), file:${SURELOG_DIR}/tests/FuncDeclScope/dut.sv, line:1:1, endln:18:13 |vpiNet: \_logic_net: (work@intf.o), line:3:27, endln:3:28 |vpiParent: - \_interface: work@intf (work@intf), file:${SURELOG_DIR}/tests/FuncDeclScope/dut.sv, line:1:1, endln:18:13 + \_interface_inst: work@intf (work@intf), file:${SURELOG_DIR}/tests/FuncDeclScope/dut.sv, line:1:1, endln:18:13 |vpiName:o |vpiFullName:work@intf.o |uhdmallModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/FuncDeclScope/dut.sv, line:21:1, endln:40:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/FuncDeclScope/dut.sv, line:21:1, endln:40:10 |vpiParent: \_design: (work@top) |vpiFullName:work@top |vpiParameter: \_parameter: (work@top.Depth), line:22:27, endln:22:32 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/FuncDeclScope/dut.sv, line:21:1, endln:40:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/FuncDeclScope/dut.sv, line:21:1, endln:40:10 |UINT:4 |vpiTypespec: \_int_typespec: , line:22:14, endln:22:26 @@ -437,7 +437,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:22:27, endln:22:36 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/FuncDeclScope/dut.sv, line:21:1, endln:40:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/FuncDeclScope/dut.sv, line:21:1, endln:40:10 |vpiRhs: \_constant: , line:22:35, endln:22:36 |vpiDecompile:4 @@ -452,7 +452,7 @@ design: (work@top) |vpiTaskFunc: \_function: (work@top.get4), line:25:4, endln:27:18 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/FuncDeclScope/dut.sv, line:21:1, endln:40:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/FuncDeclScope/dut.sv, line:21:1, endln:40:10 |vpiName:get4 |vpiFullName:work@top.get4 |vpiVisibility:1 @@ -464,7 +464,7 @@ design: (work@top) |vpiSigned:1 |vpiSigned:1 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/FuncDeclScope/dut.sv, line:21:1, endln:40:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/FuncDeclScope/dut.sv, line:21:1, endln:40:10 |vpiStmt: \_return_stmt: , line:26:10, endln:26:16 |vpiParent: @@ -478,20 +478,20 @@ design: (work@top) |UINT:1 |vpiConstType:9 |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/FuncDeclScope/dut.sv, line:21:1, endln:40:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/FuncDeclScope/dut.sv, line:21:1, endln:40:10 |vpiNet: \_logic_net: (work@top.o), line:23:27, endln:23:28 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/FuncDeclScope/dut.sv, line:21:1, endln:40:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/FuncDeclScope/dut.sv, line:21:1, endln:40:10 |vpiName:o |vpiFullName:work@top.o |uhdmtopModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/FuncDeclScope/dut.sv, line:21:1, endln:40:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/FuncDeclScope/dut.sv, line:21:1, endln:40:10 |vpiName:work@top |vpiVariables: \_int_var: (work@top.o), line:23:27, endln:23:28 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/FuncDeclScope/dut.sv, line:21:1, endln:40:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/FuncDeclScope/dut.sv, line:21:1, endln:40:10 |vpiTypespec: \_int_typespec: , line:23:4, endln:23:7 |vpiSigned:1 @@ -501,7 +501,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.Depth), line:22:27, endln:22:32 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/FuncDeclScope/dut.sv, line:21:1, endln:40:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/FuncDeclScope/dut.sv, line:21:1, endln:40:10 |UINT:4 |vpiTypespec: \_int_typespec: , line:22:14, endln:22:26 @@ -512,7 +512,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:22:27, endln:22:36 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/FuncDeclScope/dut.sv, line:21:1, endln:40:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/FuncDeclScope/dut.sv, line:21:1, endln:40:10 |vpiRhs: \_constant: , line:22:35, endln:22:36 |vpiDecompile:4 @@ -528,7 +528,7 @@ design: (work@top) |vpiTaskFunc: \_function: (work@top.get4), line:25:4, endln:27:18 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/FuncDeclScope/dut.sv, line:21:1, endln:40:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/FuncDeclScope/dut.sv, line:21:1, endln:40:10 |vpiName:get4 |vpiFullName:work@top.get4 |vpiVisibility:1 @@ -536,7 +536,7 @@ design: (work@top) |vpiReturn: \_int_var: , line:25:23, endln:25:26 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/FuncDeclScope/dut.sv, line:21:1, endln:40:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/FuncDeclScope/dut.sv, line:21:1, endln:40:10 |vpiStmt: \_return_stmt: , line:26:10, endln:26:16 |vpiParent: @@ -544,18 +544,18 @@ design: (work@top) |vpiCondition: \_constant: , line:26:17, endln:26:18 |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/FuncDeclScope/dut.sv, line:21:1, endln:40:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/FuncDeclScope/dut.sv, line:21:1, endln:40:10 |vpiTopModule:1 - |vpiInterface: - \_interface: work@intf (work@top.interf), file:${SURELOG_DIR}/tests/FuncDeclScope/dut.sv, line:28:3, endln:28:17 + |vpiInterfaceInst: + \_interface_inst: work@intf (work@top.interf), file:${SURELOG_DIR}/tests/FuncDeclScope/dut.sv, line:28:3, endln:28:17 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/FuncDeclScope/dut.sv, line:21:1, endln:40:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/FuncDeclScope/dut.sv, line:21:1, endln:40:10 |vpiName:interf |vpiFullName:work@top.interf |vpiVariables: \_int_var: (work@top.interf.o), line:3:27, endln:3:28 |vpiParent: - \_interface: work@intf (work@top.interf), file:${SURELOG_DIR}/tests/FuncDeclScope/dut.sv, line:28:3, endln:28:17 + \_interface_inst: work@intf (work@top.interf), file:${SURELOG_DIR}/tests/FuncDeclScope/dut.sv, line:28:3, endln:28:17 |vpiTypespec: \_int_typespec: , line:3:4, endln:3:7 |vpiSigned:1 @@ -565,7 +565,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.interf.Depth), line:2:27, endln:2:32 |vpiParent: - \_interface: work@intf (work@top.interf), file:${SURELOG_DIR}/tests/FuncDeclScope/dut.sv, line:28:3, endln:28:17 + \_interface_inst: work@intf (work@top.interf), file:${SURELOG_DIR}/tests/FuncDeclScope/dut.sv, line:28:3, endln:28:17 |UINT:4 |vpiTypespec: \_int_typespec: , line:2:14, endln:2:26 @@ -576,7 +576,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:2:27, endln:2:36 |vpiParent: - \_interface: work@intf (work@top.interf), file:${SURELOG_DIR}/tests/FuncDeclScope/dut.sv, line:28:3, endln:28:17 + \_interface_inst: work@intf (work@top.interf), file:${SURELOG_DIR}/tests/FuncDeclScope/dut.sv, line:28:3, endln:28:17 |vpiRhs: \_constant: , line:2:35, endln:2:36 |vpiDecompile:4 @@ -593,11 +593,11 @@ design: (work@top) |vpiTaskFunc: \_function: (work@intf.get2), line:5:4, endln:7:18 |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/FuncDeclScope/dut.sv, line:21:1, endln:40:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/FuncDeclScope/dut.sv, line:21:1, endln:40:10 |vpiGenScopeArray: \_gen_scope_array: (work@top.interf.gen_block), line:9:4, endln:17:19 |vpiParent: - \_interface: work@intf (work@top.interf), file:${SURELOG_DIR}/tests/FuncDeclScope/dut.sv, line:28:3, endln:28:17 + \_interface_inst: work@intf (work@top.interf), file:${SURELOG_DIR}/tests/FuncDeclScope/dut.sv, line:28:3, endln:28:17 |vpiName:gen_block |vpiFullName:work@top.interf.gen_block |vpiGenScope: @@ -656,7 +656,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.gen_block), line:29:4, endln:37:19 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/FuncDeclScope/dut.sv, line:21:1, endln:40:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/FuncDeclScope/dut.sv, line:21:1, endln:40:10 |vpiName:gen_block |vpiFullName:work@top.gen_block |vpiGenScope: diff --git a/tests/FuncDef/FuncDef.log b/tests/FuncDef/FuncDef.log index e0b0b5fd16..5e72c71b66 100644 --- a/tests/FuncDef/FuncDef.log +++ b/tests/FuncDef/FuncDef.log @@ -207,7 +207,7 @@ integer_typespec 4 integer_var 3 io_decl 1 logic_net 1 -module 8 +module_inst 8 operation 6 param_assign 8 parameter 8 @@ -229,7 +229,7 @@ integer_typespec 4 integer_var 3 io_decl 2 logic_net 1 -module 8 +module_inst 8 operation 10 param_assign 8 parameter 8 @@ -249,7 +249,7 @@ design: (work@mulAddRecFNToRaw_preMul) |vpiElaborated:1 |vpiName:work@mulAddRecFNToRaw_preMul |uhdmallModules: -\_module: work@mulAddRecFNToRaw_preMul (work@mulAddRecFNToRaw_preMul), file:${SURELOG_DIR}/tests/FuncDef/dut.sv, line:1:1, endln:16:10 +\_module_inst: work@mulAddRecFNToRaw_preMul (work@mulAddRecFNToRaw_preMul), file:${SURELOG_DIR}/tests/FuncDef/dut.sv, line:1:1, endln:16:10 |vpiParent: \_design: (work@mulAddRecFNToRaw_preMul) |vpiFullName:work@mulAddRecFNToRaw_preMul @@ -257,7 +257,7 @@ design: (work@mulAddRecFNToRaw_preMul) |vpiTaskFunc: \_function: (work@mulAddRecFNToRaw_preMul.clog2), line:3:1, endln:11:12 |vpiParent: - \_module: work@mulAddRecFNToRaw_preMul (work@mulAddRecFNToRaw_preMul), file:${SURELOG_DIR}/tests/FuncDef/dut.sv, line:1:1, endln:16:10 + \_module_inst: work@mulAddRecFNToRaw_preMul (work@mulAddRecFNToRaw_preMul), file:${SURELOG_DIR}/tests/FuncDef/dut.sv, line:1:1, endln:16:10 |vpiName:clog2 |vpiFullName:work@mulAddRecFNToRaw_preMul.clog2 |vpiVisibility:1 @@ -268,7 +268,7 @@ design: (work@mulAddRecFNToRaw_preMul) |vpiSigned:1 |vpiSigned:1 |vpiParent: - \_module: work@mulAddRecFNToRaw_preMul (work@mulAddRecFNToRaw_preMul), file:${SURELOG_DIR}/tests/FuncDef/dut.sv, line:1:1, endln:16:10 + \_module_inst: work@mulAddRecFNToRaw_preMul (work@mulAddRecFNToRaw_preMul), file:${SURELOG_DIR}/tests/FuncDef/dut.sv, line:1:1, endln:16:10 |vpiIODecl: \_io_decl: (a), line:4:19, endln:4:20 |vpiParent: @@ -433,23 +433,23 @@ design: (work@mulAddRecFNToRaw_preMul) |vpiActual: \_io_decl: (a), line:4:19, endln:4:20 |vpiInstance: - \_module: work@mulAddRecFNToRaw_preMul (work@mulAddRecFNToRaw_preMul), file:${SURELOG_DIR}/tests/FuncDef/dut.sv, line:1:1, endln:16:10 + \_module_inst: work@mulAddRecFNToRaw_preMul (work@mulAddRecFNToRaw_preMul), file:${SURELOG_DIR}/tests/FuncDef/dut.sv, line:1:1, endln:16:10 |uhdmtopModules: -\_module: work@mulAddRecFNToRaw_preMul (work@mulAddRecFNToRaw_preMul), file:${SURELOG_DIR}/tests/FuncDef/dut.sv, line:1:1, endln:16:10 +\_module_inst: work@mulAddRecFNToRaw_preMul (work@mulAddRecFNToRaw_preMul), file:${SURELOG_DIR}/tests/FuncDef/dut.sv, line:1:1, endln:16:10 |vpiName:work@mulAddRecFNToRaw_preMul |vpiDefName:work@mulAddRecFNToRaw_preMul |vpiTop:1 |vpiTaskFunc: \_function: (work@mulAddRecFNToRaw_preMul.clog2), line:3:1, endln:11:12 |vpiParent: - \_module: work@mulAddRecFNToRaw_preMul (work@mulAddRecFNToRaw_preMul), file:${SURELOG_DIR}/tests/FuncDef/dut.sv, line:1:1, endln:16:10 + \_module_inst: work@mulAddRecFNToRaw_preMul (work@mulAddRecFNToRaw_preMul), file:${SURELOG_DIR}/tests/FuncDef/dut.sv, line:1:1, endln:16:10 |vpiName:clog2 |vpiFullName:work@mulAddRecFNToRaw_preMul.clog2 |vpiVisibility:1 |vpiReturn: \_integer_var: , line:3:10, endln:3:17 |vpiParent: - \_module: work@mulAddRecFNToRaw_preMul (work@mulAddRecFNToRaw_preMul), file:${SURELOG_DIR}/tests/FuncDef/dut.sv, line:1:1, endln:16:10 + \_module_inst: work@mulAddRecFNToRaw_preMul (work@mulAddRecFNToRaw_preMul), file:${SURELOG_DIR}/tests/FuncDef/dut.sv, line:1:1, endln:16:10 |vpiIODecl: \_io_decl: (a), line:4:19, endln:4:20 |vpiParent: @@ -585,21 +585,21 @@ design: (work@mulAddRecFNToRaw_preMul) |vpiActual: \_io_decl: (a), line:4:19, endln:4:20 |vpiInstance: - \_module: work@mulAddRecFNToRaw_preMul (work@mulAddRecFNToRaw_preMul), file:${SURELOG_DIR}/tests/FuncDef/dut.sv, line:1:1, endln:16:10 + \_module_inst: work@mulAddRecFNToRaw_preMul (work@mulAddRecFNToRaw_preMul), file:${SURELOG_DIR}/tests/FuncDef/dut.sv, line:1:1, endln:16:10 |vpiNet: \_logic_net: (prodWidth) |vpiName:prodWidth |vpiNetType:1 |vpiTopModule:1 - |vpiModule: - \_module: work@mulAddRecFNToRaw_preMul::countLeadingZeros (work@mulAddRecFNToRaw_preMul.countLeadingZeros_notCDom), file:${SURELOG_DIR}/tests/FuncDef/dut.sv, line:13:5, endln:15:66 + |vpiModuleInst: + \_module_inst: work@mulAddRecFNToRaw_preMul::countLeadingZeros (work@mulAddRecFNToRaw_preMul.countLeadingZeros_notCDom), file:${SURELOG_DIR}/tests/FuncDef/dut.sv, line:13:5, endln:15:66 |vpiParent: - \_module: work@mulAddRecFNToRaw_preMul (work@mulAddRecFNToRaw_preMul), file:${SURELOG_DIR}/tests/FuncDef/dut.sv, line:1:1, endln:16:10 + \_module_inst: work@mulAddRecFNToRaw_preMul (work@mulAddRecFNToRaw_preMul), file:${SURELOG_DIR}/tests/FuncDef/dut.sv, line:1:1, endln:16:10 |vpiName:countLeadingZeros_notCDom |vpiFullName:work@mulAddRecFNToRaw_preMul.countLeadingZeros_notCDom |vpiDefName:work@mulAddRecFNToRaw_preMul::countLeadingZeros |vpiInstance: - \_module: work@mulAddRecFNToRaw_preMul (work@mulAddRecFNToRaw_preMul), file:${SURELOG_DIR}/tests/FuncDef/dut.sv, line:1:1, endln:16:10 + \_module_inst: work@mulAddRecFNToRaw_preMul (work@mulAddRecFNToRaw_preMul), file:${SURELOG_DIR}/tests/FuncDef/dut.sv, line:1:1, endln:16:10 =================== [ FATAL] : 0 [ SYNTAX] : 0 diff --git a/tests/FuncDef2/FuncDef2.log b/tests/FuncDef2/FuncDef2.log index 29335b08a9..c45c790c3f 100644 --- a/tests/FuncDef2/FuncDef2.log +++ b/tests/FuncDef2/FuncDef2.log @@ -3675,7 +3675,7 @@ io_decl 72 logic_net 6 logic_typespec 26 logic_var 14 -module 8 +module_inst 8 operation 118 package 3 param_assign 34 @@ -3723,7 +3723,7 @@ io_decl 180 logic_net 6 logic_typespec 26 logic_var 14 -module 8 +module_inst 8 operation 268 package 3 param_assign 34 @@ -9164,7 +9164,7 @@ design: (work@tnoc_vc_splitter) |vpiTypespec: \_struct_typespec: (tnoc_pkg::tnoc_packet_config), line:44:11, endln:44:17 |vpiParent: - \_module: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 + \_module_inst: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 |vpiName:tnoc_pkg::tnoc_packet_config |vpiInstance: \_package: tnoc_pkg (tnoc_pkg::), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:40:1, endln:400:11 @@ -9498,7 +9498,7 @@ design: (work@tnoc_vc_splitter) |vpiTypedef: \_enum_typespec: (tnoc_pkg::tnoc_burst_type), line:187:3, endln:191:21 |vpiParent: - \_module: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 + \_module_inst: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 |vpiName:tnoc_pkg::tnoc_burst_type |vpiInstance: \_package: tnoc_pkg (tnoc_pkg::), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:40:1, endln:400:11 @@ -9545,7 +9545,7 @@ design: (work@tnoc_vc_splitter) |vpiTypedef: \_enum_typespec: (tnoc_pkg::tnoc_flit_type), line:309:3, endln:312:20 |vpiParent: - \_module: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 + \_module_inst: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 |vpiName:tnoc_pkg::tnoc_flit_type |vpiInstance: \_package: tnoc_pkg (tnoc_pkg::), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:40:1, endln:400:11 @@ -9570,7 +9570,7 @@ design: (work@tnoc_vc_splitter) |vpiTypedef: \_enum_typespec: (tnoc_pkg::tnoc_packet_type), line:174:3, endln:181:22 |vpiParent: - \_module: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 + \_module_inst: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 |vpiName:tnoc_pkg::tnoc_packet_type |vpiInstance: \_package: tnoc_pkg (tnoc_pkg::), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:40:1, endln:400:11 @@ -9635,7 +9635,7 @@ design: (work@tnoc_vc_splitter) |vpiTypedef: \_enum_typespec: (tnoc_pkg::tnoc_port_type), line:373:3, endln:376:20 |vpiParent: - \_module: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 + \_module_inst: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 |vpiName:tnoc_pkg::tnoc_port_type |vpiInstance: \_package: tnoc_pkg (tnoc_pkg::), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:40:1, endln:400:11 @@ -9659,7 +9659,7 @@ design: (work@tnoc_vc_splitter) |vpiTypedef: \_struct_typespec: (tnoc_pkg::tnoc_response_status), line:193:11, endln:193:17 |vpiParent: - \_module: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 + \_module_inst: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 |vpiName:tnoc_pkg::tnoc_response_status |vpiInstance: \_package: tnoc_pkg (tnoc_pkg::), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:40:1, endln:400:11 @@ -14537,14 +14537,14 @@ design: (work@tnoc_vc_splitter) |vpiInstance: \_package: tnoc_pkg (tnoc_pkg::), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:40:1, endln:400:11 |uhdmallModules: -\_module: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 +\_module_inst: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 |vpiParent: \_design: (work@tnoc_vc_splitter) |vpiFullName:work@tnoc_vc_splitter |vpiParameter: \_parameter: (work@tnoc_vc_splitter.TNOC_DEFAULT_PACKET_CONFIG), line:55:35, endln:55:61 |vpiParent: - \_module: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 + \_module_inst: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 |vpiTypespec: \_struct_typespec: (tnoc_pkg::tnoc_packet_config), line:44:11, endln:44:17 |vpiParent: @@ -14696,7 +14696,7 @@ design: (work@tnoc_vc_splitter) |vpiParameter: \_parameter: (work@tnoc_vc_splitter.TNOC_PACKET_TYPE_NON_POSTED_BIT), line:185:19, endln:185:50 |vpiParent: - \_module: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 + \_module_inst: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 |UINT:5 |vpiTypespec: \_int_typespec: , line:185:15, endln:185:18 @@ -14713,7 +14713,7 @@ design: (work@tnoc_vc_splitter) |vpiParameter: \_parameter: (work@tnoc_vc_splitter.TNOC_PACKET_TYPE_PAYLOAD_BIT), line:184:19, endln:184:47 |vpiParent: - \_module: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 + \_module_inst: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 |UINT:6 |vpiTypespec: \_int_typespec: , line:184:15, endln:184:18 @@ -14730,7 +14730,7 @@ design: (work@tnoc_vc_splitter) |vpiParameter: \_parameter: (work@tnoc_vc_splitter.TNOC_PACKET_TYPE_RESPONSE_BIT), line:183:19, endln:183:48 |vpiParent: - \_module: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 + \_module_inst: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 |UINT:7 |vpiTypespec: \_int_typespec: , line:183:15, endln:183:18 @@ -14747,7 +14747,7 @@ design: (work@tnoc_vc_splitter) |vpiParameter: \_parameter: (work@tnoc_vc_splitter.PACKET_CONFIG), line:407:35, endln:407:48 |vpiParent: - \_module: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 + \_module_inst: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 |vpiTypespec: \_struct_typespec: (tnoc_pkg::tnoc_packet_config), line:44:11, endln:44:17 |vpiName:PACKET_CONFIG @@ -14755,7 +14755,7 @@ design: (work@tnoc_vc_splitter) |vpiParameter: \_parameter: (work@tnoc_vc_splitter.PORT_TYPE), line:408:35, endln:408:44 |vpiParent: - \_module: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 + \_module_inst: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 |vpiTypespec: \_enum_typespec: (tnoc_pkg::tnoc_port_type), line:373:3, endln:376:20 |vpiName:PORT_TYPE @@ -14763,7 +14763,7 @@ design: (work@tnoc_vc_splitter) |vpiParameter: \_parameter: (work@tnoc_vc_splitter.CHANNELS), line:409:35, endln:409:43 |vpiParent: - \_module: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 + \_module_inst: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 |vpiTypespec: \_int_typespec: , line:409:15, endln:409:18 |vpiParent: @@ -14776,7 +14776,7 @@ design: (work@tnoc_vc_splitter) |vpiParamAssign: \_param_assign: , line:55:35, endln:64:4 |vpiParent: - \_module: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 + \_module_inst: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 |vpiRhs: \_operation: , line:55:65, endln:64:4 |vpiParent: @@ -15073,7 +15073,7 @@ design: (work@tnoc_vc_splitter) |vpiParamAssign: \_param_assign: , line:183:19, endln:183:54 |vpiParent: - \_module: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 + \_module_inst: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 |vpiRhs: \_constant: , line:183:53, endln:183:54 |vpiParent: @@ -15109,7 +15109,7 @@ design: (work@tnoc_vc_splitter) |vpiParamAssign: \_param_assign: , line:184:19, endln:184:54 |vpiParent: - \_module: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 + \_module_inst: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 |vpiRhs: \_constant: , line:184:53, endln:184:54 |vpiParent: @@ -15145,7 +15145,7 @@ design: (work@tnoc_vc_splitter) |vpiParamAssign: \_param_assign: , line:185:19, endln:185:54 |vpiParent: - \_module: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 + \_module_inst: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 |vpiRhs: \_constant: , line:185:53, endln:185:54 |vpiParent: @@ -15181,7 +15181,7 @@ design: (work@tnoc_vc_splitter) |vpiParamAssign: \_param_assign: , line:407:35, endln:407:77 |vpiParent: - \_module: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 + \_module_inst: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 |vpiRhs: \_ref_obj: (TNOC_DEFAULT_PACKET_CONFIG), line:407:51, endln:407:77 |vpiName:TNOC_DEFAULT_PACKET_CONFIG @@ -15190,7 +15190,7 @@ design: (work@tnoc_vc_splitter) |vpiParamAssign: \_param_assign: , line:408:35, endln:408:66 |vpiParent: - \_module: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 + \_module_inst: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 |vpiRhs: \_ref_obj: (TNOC_LOCAL_PORT), line:408:51, endln:408:66 |vpiName:TNOC_LOCAL_PORT @@ -15201,7 +15201,7 @@ design: (work@tnoc_vc_splitter) |vpiParamAssign: \_param_assign: , line:409:35, endln:409:81 |vpiParent: - \_module: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 + \_module_inst: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 |vpiRhs: \_hier_path: (PACKET_CONFIG.virtual_channels), line:409:51, endln:409:81 |vpiName:PACKET_CONFIG.virtual_channels @@ -19177,25 +19177,25 @@ design: (work@tnoc_vc_splitter) |vpiNet: \_logic_net: (work@tnoc_vc_splitter.types), line:411:25, endln:411:30 |vpiParent: - \_module: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 + \_module_inst: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 |vpiName:types |vpiFullName:work@tnoc_vc_splitter.types |vpiNet: \_logic_net: (work@tnoc_vc_splitter.receiver_if), line:412:25, endln:412:36 |vpiParent: - \_module: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 + \_module_inst: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 |vpiName:receiver_if |vpiFullName:work@tnoc_vc_splitter.receiver_if |vpiNet: \_logic_net: (work@tnoc_vc_splitter.sender_if), line:413:25, endln:413:34 |vpiParent: - \_module: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 + \_module_inst: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 |vpiName:sender_if |vpiFullName:work@tnoc_vc_splitter.sender_if |vpiPort: \_port: (types), line:411:25, endln:411:30 |vpiParent: - \_module: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 + \_module_inst: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 |vpiName:types |vpiDirection:3 |vpiLowConn: @@ -19208,7 +19208,7 @@ design: (work@tnoc_vc_splitter) |vpiPort: \_port: (receiver_if), line:412:25, endln:412:36 |vpiParent: - \_module: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 + \_module_inst: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 |vpiName:receiver_if |vpiDirection:3 |vpiLowConn: @@ -19221,7 +19221,7 @@ design: (work@tnoc_vc_splitter) |vpiPort: \_port: (sender_if), line:413:25, endln:413:34 |vpiParent: - \_module: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 + \_module_inst: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 |vpiName:sender_if |vpiDirection:3 |vpiLowConn: @@ -19260,12 +19260,12 @@ design: (work@tnoc_vc_splitter) \_unsupported_typespec: (tnoc_flit_if), line:413:3, endln:413:15 |vpiName:tnoc_flit_if |uhdmtopModules: -\_module: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 +\_module_inst: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 |vpiName:work@tnoc_vc_splitter |vpiParameter: \_parameter: (work@tnoc_vc_splitter.TNOC_DEFAULT_PACKET_CONFIG), line:55:35, endln:55:61 |vpiParent: - \_module: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 + \_module_inst: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 |vpiTypespec: \_struct_typespec: (tnoc_pkg::tnoc_packet_config), line:44:11, endln:44:17 |vpiParent: @@ -19417,7 +19417,7 @@ design: (work@tnoc_vc_splitter) |vpiParameter: \_parameter: (work@tnoc_vc_splitter.TNOC_PACKET_TYPE_NON_POSTED_BIT), line:185:19, endln:185:50 |vpiParent: - \_module: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 + \_module_inst: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 |UINT:5 |vpiTypespec: \_int_typespec: , line:185:15, endln:185:18 @@ -19434,7 +19434,7 @@ design: (work@tnoc_vc_splitter) |vpiParameter: \_parameter: (work@tnoc_vc_splitter.TNOC_PACKET_TYPE_PAYLOAD_BIT), line:184:19, endln:184:47 |vpiParent: - \_module: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 + \_module_inst: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 |UINT:6 |vpiTypespec: \_int_typespec: , line:184:15, endln:184:18 @@ -19451,7 +19451,7 @@ design: (work@tnoc_vc_splitter) |vpiParameter: \_parameter: (work@tnoc_vc_splitter.TNOC_PACKET_TYPE_RESPONSE_BIT), line:183:19, endln:183:48 |vpiParent: - \_module: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 + \_module_inst: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 |UINT:7 |vpiTypespec: \_int_typespec: , line:183:15, endln:183:18 @@ -19468,7 +19468,7 @@ design: (work@tnoc_vc_splitter) |vpiParameter: \_parameter: (work@tnoc_vc_splitter.PACKET_CONFIG), line:407:35, endln:407:48 |vpiParent: - \_module: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 + \_module_inst: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 |vpiTypespec: \_struct_typespec: (tnoc_pkg::tnoc_packet_config), line:44:11, endln:44:17 |vpiParent: @@ -19618,7 +19618,7 @@ design: (work@tnoc_vc_splitter) |vpiParameter: \_parameter: (work@tnoc_vc_splitter.PORT_TYPE), line:408:35, endln:408:44 |vpiParent: - \_module: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 + \_module_inst: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 |vpiTypespec: \_enum_typespec: (tnoc_pkg::tnoc_port_type), line:373:3, endln:376:20 |vpiParent: @@ -19654,7 +19654,7 @@ design: (work@tnoc_vc_splitter) |vpiParameter: \_parameter: (work@tnoc_vc_splitter.CHANNELS), line:409:35, endln:409:43 |vpiParent: - \_module: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 + \_module_inst: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 |vpiTypespec: \_int_typespec: , line:409:15, endln:409:18 |vpiParent: @@ -19667,7 +19667,7 @@ design: (work@tnoc_vc_splitter) |vpiParamAssign: \_param_assign: , line:407:35, endln:407:77 |vpiParent: - \_module: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 + \_module_inst: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 |vpiRhs: \_ref_obj: (TNOC_DEFAULT_PACKET_CONFIG), line:407:51, endln:407:77 |vpiName:TNOC_DEFAULT_PACKET_CONFIG @@ -19678,7 +19678,7 @@ design: (work@tnoc_vc_splitter) |vpiParamAssign: \_param_assign: , line:408:35, endln:408:66 |vpiParent: - \_module: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 + \_module_inst: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 |vpiRhs: \_constant: , line:408:51, endln:408:66 |vpiDecompile:1'b0 @@ -19692,7 +19692,7 @@ design: (work@tnoc_vc_splitter) |vpiParamAssign: \_param_assign: , line:409:35, endln:409:81 |vpiParent: - \_module: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 + \_module_inst: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 |vpiRhs: \_constant: , line:409:51, endln:409:81 |vpiDecompile:2 @@ -19706,7 +19706,7 @@ design: (work@tnoc_vc_splitter) |vpiParamAssign: \_param_assign: , line:55:35, endln:64:4 |vpiParent: - \_module: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 + \_module_inst: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 |vpiRhs: \_operation: , line:55:65, endln:64:4 |vpiParent: @@ -19930,7 +19930,7 @@ design: (work@tnoc_vc_splitter) |vpiParamAssign: \_param_assign: , line:183:19, endln:183:54 |vpiParent: - \_module: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 + \_module_inst: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 |vpiRhs: \_constant: , line:183:53, endln:183:54 |vpiDecompile:7 @@ -19944,7 +19944,7 @@ design: (work@tnoc_vc_splitter) |vpiParamAssign: \_param_assign: , line:184:19, endln:184:54 |vpiParent: - \_module: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 + \_module_inst: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 |vpiRhs: \_constant: , line:184:53, endln:184:54 |vpiDecompile:6 @@ -19958,7 +19958,7 @@ design: (work@tnoc_vc_splitter) |vpiParamAssign: \_param_assign: , line:185:19, endln:185:54 |vpiParent: - \_module: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 + \_module_inst: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 |vpiRhs: \_constant: , line:185:53, endln:185:54 |vpiDecompile:5 @@ -19988,7 +19988,7 @@ design: (work@tnoc_vc_splitter) |vpiTaskFunc: \_function: (tnoc_pkg::tnoc_clog2), line:66:3, endln:83:14 |vpiParent: - \_module: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 + \_module_inst: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 |vpiName:tnoc_clog2 |vpiFullName:tnoc_pkg::tnoc_clog2 |vpiVariables: @@ -20005,7 +20005,7 @@ design: (work@tnoc_vc_splitter) |vpiReturn: \_int_var: , line:66:22, endln:66:25 |vpiParent: - \_module: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 + \_module_inst: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 |vpiIODecl: \_io_decl: (n), line:66:48, endln:66:49 |vpiParent: @@ -20225,11 +20225,11 @@ design: (work@tnoc_vc_splitter) |vpiOperand: \_constant: , line:81:23, endln:81:24 |vpiInstance: - \_module: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 + \_module_inst: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 |vpiTaskFunc: \_function: (tnoc_pkg::get_id_x_width), line:85:3, endln:92:14 |vpiParent: - \_module: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 + \_module_inst: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 |vpiName:get_id_x_width |vpiFullName:tnoc_pkg::get_id_x_width |vpiVisibility:1 @@ -20237,7 +20237,7 @@ design: (work@tnoc_vc_splitter) |vpiReturn: \_int_var: , line:85:22, endln:85:25 |vpiParent: - \_module: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 + \_module_inst: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 |vpiIODecl: \_io_decl: (packet_config), line:85:60, endln:85:73 |vpiParent: @@ -20323,11 +20323,11 @@ design: (work@tnoc_vc_splitter) |vpiCondition: \_constant: , line:90:14, endln:90:15 |vpiInstance: - \_module: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 + \_module_inst: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 |vpiTaskFunc: \_function: (tnoc_pkg::get_id_y_width), line:94:3, endln:101:14 |vpiParent: - \_module: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 + \_module_inst: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 |vpiName:get_id_y_width |vpiFullName:tnoc_pkg::get_id_y_width |vpiVisibility:1 @@ -20335,7 +20335,7 @@ design: (work@tnoc_vc_splitter) |vpiReturn: \_int_var: , line:94:22, endln:94:25 |vpiParent: - \_module: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 + \_module_inst: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 |vpiIODecl: \_io_decl: (packet_config), line:94:60, endln:94:73 |vpiParent: @@ -20421,11 +20421,11 @@ design: (work@tnoc_vc_splitter) |vpiCondition: \_constant: , line:99:14, endln:99:15 |vpiInstance: - \_module: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 + \_module_inst: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 |vpiTaskFunc: \_function: (tnoc_pkg::get_location_id_width), line:103:3, endln:105:14 |vpiParent: - \_module: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 + \_module_inst: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 |vpiName:get_location_id_width |vpiFullName:tnoc_pkg::get_location_id_width |vpiVisibility:1 @@ -20433,7 +20433,7 @@ design: (work@tnoc_vc_splitter) |vpiReturn: \_int_var: , line:103:22, endln:103:25 |vpiParent: - \_module: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 + \_module_inst: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 |vpiIODecl: \_io_decl: (packet_config), line:103:67, endln:103:80 |vpiParent: @@ -20482,11 +20482,11 @@ design: (work@tnoc_vc_splitter) |vpiFunction: \_function: (tnoc_pkg::get_id_y_width), line:94:3, endln:101:14 |vpiInstance: - \_module: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 + \_module_inst: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 |vpiTaskFunc: \_function: (tnoc_pkg::get_vc_width), line:107:3, endln:114:14 |vpiParent: - \_module: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 + \_module_inst: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 |vpiName:get_vc_width |vpiFullName:tnoc_pkg::get_vc_width |vpiVisibility:1 @@ -20494,7 +20494,7 @@ design: (work@tnoc_vc_splitter) |vpiReturn: \_int_var: , line:107:22, endln:107:25 |vpiParent: - \_module: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 + \_module_inst: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 |vpiIODecl: \_io_decl: (packet_config), line:107:58, endln:107:71 |vpiParent: @@ -20580,11 +20580,11 @@ design: (work@tnoc_vc_splitter) |vpiCondition: \_constant: , line:112:14, endln:112:15 |vpiInstance: - \_module: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 + \_module_inst: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 |vpiTaskFunc: \_function: (tnoc_pkg::get_tag_width), line:116:3, endln:123:14 |vpiParent: - \_module: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 + \_module_inst: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 |vpiName:get_tag_width |vpiFullName:tnoc_pkg::get_tag_width |vpiVisibility:1 @@ -20592,7 +20592,7 @@ design: (work@tnoc_vc_splitter) |vpiReturn: \_int_var: , line:116:22, endln:116:25 |vpiParent: - \_module: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 + \_module_inst: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 |vpiIODecl: \_io_decl: (packet_config), line:116:59, endln:116:72 |vpiParent: @@ -20678,11 +20678,11 @@ design: (work@tnoc_vc_splitter) |vpiCondition: \_constant: , line:121:14, endln:121:15 |vpiInstance: - \_module: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 + \_module_inst: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 |vpiTaskFunc: \_function: (tnoc_pkg::get_byte_size_width), line:125:3, endln:132:14 |vpiParent: - \_module: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 + \_module_inst: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 |vpiName:get_byte_size_width |vpiFullName:tnoc_pkg::get_byte_size_width |vpiVisibility:1 @@ -20690,7 +20690,7 @@ design: (work@tnoc_vc_splitter) |vpiReturn: \_int_var: , line:125:22, endln:125:25 |vpiParent: - \_module: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 + \_module_inst: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 |vpiIODecl: \_io_decl: (packet_config), line:125:65, endln:125:78 |vpiParent: @@ -20797,11 +20797,11 @@ design: (work@tnoc_vc_splitter) |vpiCondition: \_constant: , line:130:14, endln:130:15 |vpiInstance: - \_module: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 + \_module_inst: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 |vpiTaskFunc: \_function: (tnoc_pkg::get_byte_length_width), line:134:3, endln:136:14 |vpiParent: - \_module: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 + \_module_inst: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 |vpiName:get_byte_length_width |vpiFullName:tnoc_pkg::get_byte_length_width |vpiVisibility:1 @@ -20809,7 +20809,7 @@ design: (work@tnoc_vc_splitter) |vpiReturn: \_int_var: , line:134:22, endln:134:25 |vpiParent: - \_module: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 + \_module_inst: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 |vpiIODecl: \_io_decl: (packet_config), line:134:67, endln:134:80 |vpiParent: @@ -20856,11 +20856,11 @@ design: (work@tnoc_vc_splitter) |vpiFunction: \_function: (tnoc_pkg::tnoc_clog2), line:66:3, endln:83:14 |vpiInstance: - \_module: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 + \_module_inst: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 |vpiTaskFunc: \_function: (tnoc_pkg::get_packed_byte_length_width), line:138:3, endln:145:14 |vpiParent: - \_module: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 + \_module_inst: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 |vpiName:get_packed_byte_length_width |vpiFullName:tnoc_pkg::get_packed_byte_length_width |vpiVisibility:1 @@ -20868,7 +20868,7 @@ design: (work@tnoc_vc_splitter) |vpiReturn: \_int_var: , line:138:22, endln:138:25 |vpiParent: - \_module: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 + \_module_inst: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 |vpiIODecl: \_io_decl: (packet_config), line:138:74, endln:138:87 |vpiParent: @@ -20954,11 +20954,11 @@ design: (work@tnoc_vc_splitter) |vpiCondition: \_constant: , line:143:14, endln:143:15 |vpiInstance: - \_module: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 + \_module_inst: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 |vpiTaskFunc: \_function: (tnoc_pkg::get_byte_offset_width), line:147:3, endln:154:14 |vpiParent: - \_module: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 + \_module_inst: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 |vpiName:get_byte_offset_width |vpiFullName:tnoc_pkg::get_byte_offset_width |vpiVisibility:1 @@ -20966,7 +20966,7 @@ design: (work@tnoc_vc_splitter) |vpiReturn: \_int_var: , line:147:22, endln:147:25 |vpiParent: - \_module: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 + \_module_inst: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 |vpiIODecl: \_io_decl: (packet_config), line:147:67, endln:147:80 |vpiParent: @@ -21059,11 +21059,11 @@ design: (work@tnoc_vc_splitter) |vpiCondition: \_constant: , line:152:14, endln:152:15 |vpiInstance: - \_module: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 + \_module_inst: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 |vpiTaskFunc: \_function: (tnoc_pkg::get_byte_end_width), line:156:3, endln:163:14 |vpiParent: - \_module: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 + \_module_inst: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 |vpiName:get_byte_end_width |vpiFullName:tnoc_pkg::get_byte_end_width |vpiVisibility:1 @@ -21071,7 +21071,7 @@ design: (work@tnoc_vc_splitter) |vpiReturn: \_int_var: , line:156:22, endln:156:25 |vpiParent: - \_module: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 + \_module_inst: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 |vpiIODecl: \_io_decl: (packet_config), line:156:64, endln:156:77 |vpiParent: @@ -21164,11 +21164,11 @@ design: (work@tnoc_vc_splitter) |vpiCondition: \_constant: , line:161:14, endln:161:15 |vpiInstance: - \_module: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 + \_module_inst: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 |vpiTaskFunc: \_function: (tnoc_pkg::get_burst_length_width), line:165:3, endln:169:14 |vpiParent: - \_module: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 + \_module_inst: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 |vpiName:get_burst_length_width |vpiFullName:tnoc_pkg::get_burst_length_width |vpiVariables: @@ -21185,7 +21185,7 @@ design: (work@tnoc_vc_splitter) |vpiReturn: \_int_var: , line:165:22, endln:165:25 |vpiParent: - \_module: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 + \_module_inst: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 |vpiIODecl: \_io_decl: (packet_config), line:165:68, endln:165:81 |vpiParent: @@ -21299,11 +21299,11 @@ design: (work@tnoc_vc_splitter) |vpiFunction: \_function: (tnoc_pkg::tnoc_clog2), line:66:3, endln:83:14 |vpiInstance: - \_module: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 + \_module_inst: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 |vpiTaskFunc: \_function: (tnoc_pkg::is_valid_packet_type), line:199:3, endln:201:14 |vpiParent: - \_module: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 + \_module_inst: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 |vpiName:is_valid_packet_type |vpiFullName:tnoc_pkg::is_valid_packet_type |vpiVisibility:1 @@ -21311,7 +21311,7 @@ design: (work@tnoc_vc_splitter) |vpiReturn: \_logic_var: , line:199:22, endln:199:27 |vpiParent: - \_module: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 + \_module_inst: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 |vpiIODecl: \_io_decl: (packet_type), line:199:66, endln:199:77 |vpiParent: @@ -21346,11 +21346,11 @@ design: (work@tnoc_vc_splitter) |vpiActual: \_enum_const: (TNOC_INVALID_PACKET), line:175:5, endln:175:42 |vpiInstance: - \_module: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 + \_module_inst: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 |vpiTaskFunc: \_function: (tnoc_pkg::is_request_packet_type), line:203:3, endln:205:14 |vpiParent: - \_module: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 + \_module_inst: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 |vpiName:is_request_packet_type |vpiFullName:tnoc_pkg::is_request_packet_type |vpiVisibility:1 @@ -21358,7 +21358,7 @@ design: (work@tnoc_vc_splitter) |vpiReturn: \_logic_var: , line:203:22, endln:203:27 |vpiParent: - \_module: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 + \_module_inst: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 |vpiIODecl: \_io_decl: (packet_type), line:203:68, endln:203:79 |vpiParent: @@ -21419,11 +21419,11 @@ design: (work@tnoc_vc_splitter) |vpiActual: \_io_decl: (packet_type), line:203:68, endln:203:79 |vpiInstance: - \_module: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 + \_module_inst: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 |vpiTaskFunc: \_function: (tnoc_pkg::is_response_packet_type), line:207:3, endln:209:14 |vpiParent: - \_module: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 + \_module_inst: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 |vpiName:is_response_packet_type |vpiFullName:tnoc_pkg::is_response_packet_type |vpiVisibility:1 @@ -21431,7 +21431,7 @@ design: (work@tnoc_vc_splitter) |vpiReturn: \_logic_var: , line:207:22, endln:207:27 |vpiParent: - \_module: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 + \_module_inst: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 |vpiIODecl: \_io_decl: (packet_type), line:207:69, endln:207:80 |vpiParent: @@ -21487,11 +21487,11 @@ design: (work@tnoc_vc_splitter) |vpiActual: \_io_decl: (packet_type), line:207:69, endln:207:80 |vpiInstance: - \_module: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 + \_module_inst: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 |vpiTaskFunc: \_function: (tnoc_pkg::is_packet_with_payload_type), line:211:3, endln:213:14 |vpiParent: - \_module: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 + \_module_inst: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 |vpiName:is_packet_with_payload_type |vpiFullName:tnoc_pkg::is_packet_with_payload_type |vpiVisibility:1 @@ -21499,7 +21499,7 @@ design: (work@tnoc_vc_splitter) |vpiReturn: \_logic_var: , line:211:22, endln:211:27 |vpiParent: - \_module: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 + \_module_inst: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 |vpiIODecl: \_io_decl: (packet_type), line:211:73, endln:211:84 |vpiParent: @@ -21555,11 +21555,11 @@ design: (work@tnoc_vc_splitter) |vpiActual: \_io_decl: (packet_type), line:211:73, endln:211:84 |vpiInstance: - \_module: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 + \_module_inst: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 |vpiTaskFunc: \_function: (tnoc_pkg::is_header_only_packet_type), line:215:3, endln:217:14 |vpiParent: - \_module: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 + \_module_inst: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 |vpiName:is_header_only_packet_type |vpiFullName:tnoc_pkg::is_header_only_packet_type |vpiVisibility:1 @@ -21567,7 +21567,7 @@ design: (work@tnoc_vc_splitter) |vpiReturn: \_logic_var: , line:215:22, endln:215:27 |vpiParent: - \_module: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 + \_module_inst: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 |vpiIODecl: \_io_decl: (packet_type), line:215:72, endln:215:83 |vpiParent: @@ -21628,11 +21628,11 @@ design: (work@tnoc_vc_splitter) |vpiActual: \_io_decl: (packet_type), line:215:72, endln:215:83 |vpiInstance: - \_module: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 + \_module_inst: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 |vpiTaskFunc: \_function: (tnoc_pkg::is_posted_request_packet_type), line:219:3, endln:221:14 |vpiParent: - \_module: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 + \_module_inst: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 |vpiName:is_posted_request_packet_type |vpiFullName:tnoc_pkg::is_posted_request_packet_type |vpiVisibility:1 @@ -21640,7 +21640,7 @@ design: (work@tnoc_vc_splitter) |vpiReturn: \_logic_var: , line:219:22, endln:219:27 |vpiParent: - \_module: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 + \_module_inst: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 |vpiIODecl: \_io_decl: (packet_type), line:219:75, endln:219:86 |vpiParent: @@ -21701,11 +21701,11 @@ design: (work@tnoc_vc_splitter) |vpiActual: \_io_decl: (packet_type), line:219:75, endln:219:86 |vpiInstance: - \_module: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 + \_module_inst: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 |vpiTaskFunc: \_function: (tnoc_pkg::is_non_posted_request_packet_type), line:223:3, endln:225:14 |vpiParent: - \_module: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 + \_module_inst: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 |vpiName:is_non_posted_request_packet_type |vpiFullName:tnoc_pkg::is_non_posted_request_packet_type |vpiVisibility:1 @@ -21713,7 +21713,7 @@ design: (work@tnoc_vc_splitter) |vpiReturn: \_logic_var: , line:223:22, endln:223:27 |vpiParent: - \_module: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 + \_module_inst: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 |vpiIODecl: \_io_decl: (packet_type), line:223:79, endln:223:90 |vpiParent: @@ -21769,11 +21769,11 @@ design: (work@tnoc_vc_splitter) |vpiActual: \_io_decl: (packet_type), line:223:79, endln:223:90 |vpiInstance: - \_module: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 + \_module_inst: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 |vpiTaskFunc: \_function: (tnoc_pkg::get_common_header_field_width), line:227:3, endln:237:14 |vpiParent: - \_module: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 + \_module_inst: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 |vpiName:get_common_header_field_width |vpiFullName:tnoc_pkg::get_common_header_field_width |vpiVariables: @@ -21790,7 +21790,7 @@ design: (work@tnoc_vc_splitter) |vpiReturn: \_int_var: , line:227:22, endln:227:25 |vpiParent: - \_module: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 + \_module_inst: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 |vpiIODecl: \_io_decl: (packet_config), line:227:75, endln:227:88 |vpiParent: @@ -21990,11 +21990,11 @@ design: (work@tnoc_vc_splitter) |vpiActual: \_int_var: (tnoc_pkg::get_common_header_field_width::width), line:228:9, endln:228:14 |vpiInstance: - \_module: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 + \_module_inst: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 |vpiTaskFunc: \_function: (tnoc_pkg::get_request_header_width), line:239:3, endln:248:14 |vpiParent: - \_module: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 + \_module_inst: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 |vpiName:get_request_header_width |vpiFullName:tnoc_pkg::get_request_header_width |vpiVariables: @@ -22011,7 +22011,7 @@ design: (work@tnoc_vc_splitter) |vpiReturn: \_int_var: , line:239:22, endln:239:25 |vpiParent: - \_module: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 + \_module_inst: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 |vpiIODecl: \_io_decl: (packet_config), line:239:70, endln:239:83 |vpiParent: @@ -22199,11 +22199,11 @@ design: (work@tnoc_vc_splitter) |vpiActual: \_int_var: (tnoc_pkg::get_request_header_width::width), line:240:9, endln:240:14 |vpiInstance: - \_module: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 + \_module_inst: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 |vpiTaskFunc: \_function: (tnoc_pkg::get_response_header_width), line:250:3, endln:258:14 |vpiParent: - \_module: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 + \_module_inst: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 |vpiName:get_response_header_width |vpiFullName:tnoc_pkg::get_response_header_width |vpiVariables: @@ -22220,7 +22220,7 @@ design: (work@tnoc_vc_splitter) |vpiReturn: \_int_var: , line:250:22, endln:250:25 |vpiParent: - \_module: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 + \_module_inst: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 |vpiIODecl: \_io_decl: (packet_config), line:250:71, endln:250:84 |vpiParent: @@ -22375,11 +22375,11 @@ design: (work@tnoc_vc_splitter) |vpiActual: \_int_var: (tnoc_pkg::get_response_header_width::width), line:251:9, endln:251:14 |vpiInstance: - \_module: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 + \_module_inst: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 |vpiTaskFunc: \_function: (tnoc_pkg::get_header_width), line:260:3, endln:272:14 |vpiParent: - \_module: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 + \_module_inst: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 |vpiName:get_header_width |vpiFullName:tnoc_pkg::get_header_width |vpiVariables: @@ -22396,7 +22396,7 @@ design: (work@tnoc_vc_splitter) |vpiReturn: \_int_var: , line:260:22, endln:260:25 |vpiParent: - \_module: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 + \_module_inst: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 |vpiIODecl: \_io_decl: (packet_config), line:260:62, endln:260:75 |vpiParent: @@ -22580,11 +22580,11 @@ design: (work@tnoc_vc_splitter) |vpiActual: \_int_var: (tnoc_pkg::get_header_width::width), line:261:9, endln:261:14 |vpiInstance: - \_module: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 + \_module_inst: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 |vpiTaskFunc: \_function: (tnoc_pkg::get_request_payload_width), line:274:3, endln:280:14 |vpiParent: - \_module: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 + \_module_inst: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 |vpiName:get_request_payload_width |vpiFullName:tnoc_pkg::get_request_payload_width |vpiVariables: @@ -22601,7 +22601,7 @@ design: (work@tnoc_vc_splitter) |vpiReturn: \_int_var: , line:274:22, endln:274:25 |vpiParent: - \_module: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 + \_module_inst: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 |vpiIODecl: \_io_decl: (packet_config), line:274:71, endln:274:84 |vpiParent: @@ -22726,11 +22726,11 @@ design: (work@tnoc_vc_splitter) |vpiActual: \_int_var: (tnoc_pkg::get_request_payload_width::width), line:275:9, endln:275:14 |vpiInstance: - \_module: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 + \_module_inst: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 |vpiTaskFunc: \_function: (tnoc_pkg::get_response_payload_width), line:282:3, endln:290:14 |vpiParent: - \_module: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 + \_module_inst: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 |vpiName:get_response_payload_width |vpiFullName:tnoc_pkg::get_response_payload_width |vpiVariables: @@ -22747,7 +22747,7 @@ design: (work@tnoc_vc_splitter) |vpiReturn: \_int_var: , line:282:22, endln:282:25 |vpiParent: - \_module: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 + \_module_inst: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 |vpiIODecl: \_io_decl: (packet_config), line:282:72, endln:282:85 |vpiParent: @@ -22893,11 +22893,11 @@ design: (work@tnoc_vc_splitter) |vpiActual: \_int_var: (tnoc_pkg::get_response_payload_width::width), line:283:9, endln:283:14 |vpiInstance: - \_module: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 + \_module_inst: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 |vpiTaskFunc: \_function: (tnoc_pkg::get_payload_width), line:292:3, endln:304:14 |vpiParent: - \_module: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 + \_module_inst: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 |vpiName:get_payload_width |vpiFullName:tnoc_pkg::get_payload_width |vpiVariables: @@ -22914,7 +22914,7 @@ design: (work@tnoc_vc_splitter) |vpiReturn: \_int_var: , line:292:22, endln:292:25 |vpiParent: - \_module: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 + \_module_inst: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 |vpiIODecl: \_io_decl: (packet_config), line:292:63, endln:292:76 |vpiParent: @@ -23098,11 +23098,11 @@ design: (work@tnoc_vc_splitter) |vpiActual: \_int_var: (tnoc_pkg::get_payload_width::width), line:293:9, endln:293:14 |vpiInstance: - \_module: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 + \_module_inst: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 |vpiTaskFunc: \_function: (tnoc_pkg::get_flit_data_width), line:314:3, endln:326:14 |vpiParent: - \_module: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 + \_module_inst: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 |vpiName:get_flit_data_width |vpiFullName:tnoc_pkg::get_flit_data_width |vpiVariables: @@ -23119,7 +23119,7 @@ design: (work@tnoc_vc_splitter) |vpiReturn: \_int_var: , line:314:22, endln:314:25 |vpiParent: - \_module: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 + \_module_inst: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 |vpiIODecl: \_io_decl: (packet_config), line:314:65, endln:314:78 |vpiParent: @@ -23303,11 +23303,11 @@ design: (work@tnoc_vc_splitter) |vpiActual: \_int_var: (tnoc_pkg::get_flit_data_width::width), line:315:9, endln:315:14 |vpiInstance: - \_module: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 + \_module_inst: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 |vpiTaskFunc: \_function: (tnoc_pkg::get_flit_width), line:328:3, endln:338:14 |vpiParent: - \_module: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 + \_module_inst: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 |vpiName:get_flit_width |vpiFullName:tnoc_pkg::get_flit_width |vpiVariables: @@ -23324,7 +23324,7 @@ design: (work@tnoc_vc_splitter) |vpiReturn: \_int_var: , line:328:22, endln:328:25 |vpiParent: - \_module: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 + \_module_inst: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 |vpiIODecl: \_io_decl: (packet_config), line:328:60, endln:328:73 |vpiParent: @@ -23453,11 +23453,11 @@ design: (work@tnoc_vc_splitter) |vpiActual: \_int_var: (tnoc_pkg::get_flit_width::width), line:329:9, endln:329:14 |vpiInstance: - \_module: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 + \_module_inst: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 |vpiTaskFunc: \_function: (tnoc_pkg::get_request_header_flits), line:340:3, endln:346:14 |vpiParent: - \_module: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 + \_module_inst: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 |vpiName:get_request_header_flits |vpiFullName:tnoc_pkg::get_request_header_flits |vpiVariables: @@ -23483,7 +23483,7 @@ design: (work@tnoc_vc_splitter) |vpiReturn: \_int_var: , line:340:22, endln:340:25 |vpiParent: - \_module: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 + \_module_inst: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 |vpiIODecl: \_io_decl: (packet_config), line:340:70, endln:340:83 |vpiParent: @@ -23619,11 +23619,11 @@ design: (work@tnoc_vc_splitter) |vpiActual: \_int_var: (tnoc_pkg::get_request_header_flits::flit_width), line:342:9, endln:342:19 |vpiInstance: - \_module: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 + \_module_inst: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 |vpiTaskFunc: \_function: (tnoc_pkg::get_response_header_flits), line:348:3, endln:354:14 |vpiParent: - \_module: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 + \_module_inst: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 |vpiName:get_response_header_flits |vpiFullName:tnoc_pkg::get_response_header_flits |vpiVariables: @@ -23649,7 +23649,7 @@ design: (work@tnoc_vc_splitter) |vpiReturn: \_int_var: , line:348:22, endln:348:25 |vpiParent: - \_module: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 + \_module_inst: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 |vpiIODecl: \_io_decl: (packet_config), line:348:71, endln:348:84 |vpiParent: @@ -23785,11 +23785,11 @@ design: (work@tnoc_vc_splitter) |vpiActual: \_int_var: (tnoc_pkg::get_response_header_flits::flit_width), line:350:9, endln:350:19 |vpiInstance: - \_module: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 + \_module_inst: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 |vpiTaskFunc: \_function: (tnoc_pkg::get_header_flits), line:356:3, endln:368:14 |vpiParent: - \_module: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 + \_module_inst: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 |vpiName:get_header_flits |vpiFullName:tnoc_pkg::get_header_flits |vpiVariables: @@ -23806,7 +23806,7 @@ design: (work@tnoc_vc_splitter) |vpiReturn: \_int_var: , line:356:22, endln:356:25 |vpiParent: - \_module: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 + \_module_inst: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 |vpiIODecl: \_io_decl: (packet_config), line:356:62, endln:356:75 |vpiParent: @@ -23990,11 +23990,11 @@ design: (work@tnoc_vc_splitter) |vpiActual: \_int_var: (tnoc_pkg::get_header_flits::flits), line:357:9, endln:357:14 |vpiInstance: - \_module: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 + \_module_inst: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 |vpiTaskFunc: \_function: (tnoc_pkg::is_local_port), line:378:3, endln:380:14 |vpiParent: - \_module: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 + \_module_inst: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 |vpiName:is_local_port |vpiFullName:tnoc_pkg::is_local_port |vpiVisibility:1 @@ -24002,7 +24002,7 @@ design: (work@tnoc_vc_splitter) |vpiReturn: \_bit_var: , line:378:22, endln:378:25 |vpiParent: - \_module: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 + \_module_inst: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 |vpiIODecl: \_io_decl: (port_type), line:378:55, endln:378:64 |vpiParent: @@ -24037,11 +24037,11 @@ design: (work@tnoc_vc_splitter) |vpiActual: \_enum_const: (TNOC_LOCAL_PORT), line:374:5, endln:374:31 |vpiInstance: - \_module: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 + \_module_inst: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 |vpiTaskFunc: \_function: (tnoc_pkg::is_interna_port), line:382:3, endln:384:14 |vpiParent: - \_module: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 + \_module_inst: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 |vpiName:is_interna_port |vpiFullName:tnoc_pkg::is_interna_port |vpiVisibility:1 @@ -24049,7 +24049,7 @@ design: (work@tnoc_vc_splitter) |vpiReturn: \_bit_var: , line:382:22, endln:382:25 |vpiParent: - \_module: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 + \_module_inst: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 |vpiIODecl: \_io_decl: (port_type), line:382:57, endln:382:66 |vpiParent: @@ -24084,11 +24084,11 @@ design: (work@tnoc_vc_splitter) |vpiActual: \_enum_const: (TNOC_INTERNAL_PORT), line:375:5, endln:375:31 |vpiInstance: - \_module: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 + \_module_inst: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 |vpiTaskFunc: \_function: (tnoc_pkg::get_port_flit_width), line:386:3, endln:399:14 |vpiParent: - \_module: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 + \_module_inst: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 |vpiName:get_port_flit_width |vpiFullName:tnoc_pkg::get_port_flit_width |vpiVariables: @@ -24105,7 +24105,7 @@ design: (work@tnoc_vc_splitter) |vpiReturn: \_int_var: , line:386:22, endln:386:25 |vpiParent: - \_module: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 + \_module_inst: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 |vpiIODecl: \_io_decl: (packet_config), line:387:25, endln:387:38 |vpiParent: @@ -24240,11 +24240,11 @@ design: (work@tnoc_vc_splitter) |vpiActual: \_int_var: (tnoc_pkg::get_port_flit_width::flit_width), line:391:9, endln:391:19 |vpiInstance: - \_module: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 + \_module_inst: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 |vpiNet: \_logic_net: (work@tnoc_vc_splitter.types), line:411:25, endln:411:30 |vpiParent: - \_module: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 + \_module_inst: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 |vpiTypespec: \_unsupported_typespec: (tnoc_types), line:411:3, endln:411:13 |vpiName:tnoc_types @@ -24253,7 +24253,7 @@ design: (work@tnoc_vc_splitter) |vpiNet: \_logic_net: (work@tnoc_vc_splitter.receiver_if), line:412:25, endln:412:36 |vpiParent: - \_module: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 + \_module_inst: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 |vpiTypespec: \_unsupported_typespec: (tnoc_flit_if), line:412:3, endln:412:15 |vpiName:tnoc_flit_if @@ -24262,7 +24262,7 @@ design: (work@tnoc_vc_splitter) |vpiArrayNet: \_array_net: (work@tnoc_vc_splitter.sender_if), line:413:25, endln:413:34 |vpiParent: - \_module: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 + \_module_inst: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 |vpiSize:1 |vpiName:sender_if |vpiFullName:work@tnoc_vc_splitter.sender_if @@ -24307,7 +24307,7 @@ design: (work@tnoc_vc_splitter) |vpiPort: \_port: (types), line:411:25, endln:411:30 |vpiParent: - \_module: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 + \_module_inst: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 |vpiName:types |vpiDirection:3 |vpiLowConn: @@ -24322,11 +24322,11 @@ design: (work@tnoc_vc_splitter) \_unsupported_typespec: (tnoc_types), line:411:3, endln:411:13 |vpiName:tnoc_types |vpiInstance: - \_module: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 + \_module_inst: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 |vpiPort: \_port: (receiver_if), line:412:25, endln:412:36 |vpiParent: - \_module: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 + \_module_inst: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 |vpiName:receiver_if |vpiDirection:3 |vpiLowConn: @@ -24341,11 +24341,11 @@ design: (work@tnoc_vc_splitter) \_unsupported_typespec: (tnoc_flit_if), line:412:3, endln:412:15 |vpiName:tnoc_flit_if |vpiInstance: - \_module: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 + \_module_inst: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 |vpiPort: \_port: (sender_if), line:413:25, endln:413:34 |vpiParent: - \_module: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 + \_module_inst: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 |vpiName:sender_if |vpiDirection:3 |vpiLowConn: @@ -24360,11 +24360,11 @@ design: (work@tnoc_vc_splitter) \_unsupported_typespec: (tnoc_flit_if), line:413:3, endln:413:15 |vpiName:tnoc_flit_if |vpiInstance: - \_module: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 + \_module_inst: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 |vpiGenScopeArray: \_gen_scope_array: (work@tnoc_vc_splitter.g[0]), line:415:39, endln:432:6 |vpiParent: - \_module: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 + \_module_inst: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 |vpiName:g[0] |vpiFullName:work@tnoc_vc_splitter.g[0] |vpiGenScope: @@ -24674,7 +24674,7 @@ design: (work@tnoc_vc_splitter) |vpiGenScopeArray: \_gen_scope_array: (work@tnoc_vc_splitter.g[1]), line:415:39, endln:432:6 |vpiParent: - \_module: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 + \_module_inst: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 |vpiName:g[1] |vpiFullName:work@tnoc_vc_splitter.g[1] |vpiGenScope: diff --git a/tests/FuncDefaultVal/FuncDefaultVal.log b/tests/FuncDefaultVal/FuncDefaultVal.log index 8c0eb9b46f..fc1bc45dfa 100644 --- a/tests/FuncDefaultVal/FuncDefaultVal.log +++ b/tests/FuncDefaultVal/FuncDefaultVal.log @@ -216,7 +216,7 @@ function 1 if_stmt 1 io_decl 1 logic_net 5 -module 3 +module_inst 3 operation 3 part_select 1 range 5 @@ -241,7 +241,7 @@ function 2 if_stmt 2 io_decl 2 logic_net 5 -module 3 +module_inst 3 operation 5 part_select 2 range 5 @@ -263,7 +263,7 @@ design: (work@top) |vpiElaborated:1 |vpiName:work@top |uhdmallModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/FuncDefaultVal/dut.sv, line:1:1, endln:10:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/FuncDefaultVal/dut.sv, line:1:1, endln:10:10 |vpiParent: \_design: (work@top) |vpiFullName:work@top @@ -271,7 +271,7 @@ design: (work@top) |vpiTaskFunc: \_function: (work@top.dasm), line:5:1, endln:8:12 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/FuncDefaultVal/dut.sv, line:1:1, endln:10:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/FuncDefaultVal/dut.sv, line:1:1, endln:10:10 |vpiName:dasm |vpiFullName:work@top.dasm |vpiVisibility:1 @@ -280,7 +280,7 @@ design: (work@top) |vpiTypespec: \_string_typespec: , line:5:10, endln:5:16 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/FuncDefaultVal/dut.sv, line:1:1, endln:10:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/FuncDefaultVal/dut.sv, line:1:1, endln:10:10 |vpiIODecl: \_io_decl: (tid), line:5:29, endln:5:32 |vpiDirection:1 @@ -457,20 +457,20 @@ design: (work@top) |vpiActual: \_logic_net: (regn) |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/FuncDefaultVal/dut.sv, line:1:1, endln:10:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/FuncDefaultVal/dut.sv, line:1:1, endln:10:10 |vpiNet: \_logic_net: (work@top.gpr), line:3:18, endln:3:21 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/FuncDefaultVal/dut.sv, line:1:1, endln:10:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/FuncDefaultVal/dut.sv, line:1:1, endln:10:10 |vpiName:gpr |vpiFullName:work@top.gpr |uhdmtopModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/FuncDefaultVal/dut.sv, line:1:1, endln:10:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/FuncDefaultVal/dut.sv, line:1:1, endln:10:10 |vpiName:work@top |vpiVariables: \_array_var: (work@top.gpr), line:3:18, endln:3:24 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/FuncDefaultVal/dut.sv, line:1:1, endln:10:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/FuncDefaultVal/dut.sv, line:1:1, endln:10:10 |vpiSize:2 |vpiTypespec: \_array_typespec: @@ -556,14 +556,14 @@ design: (work@top) |vpiTaskFunc: \_function: (work@top.dasm), line:5:1, endln:8:12 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/FuncDefaultVal/dut.sv, line:1:1, endln:10:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/FuncDefaultVal/dut.sv, line:1:1, endln:10:10 |vpiName:dasm |vpiFullName:work@top.dasm |vpiVisibility:1 |vpiReturn: \_string_var: , line:5:10, endln:5:16 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/FuncDefaultVal/dut.sv, line:1:1, endln:10:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/FuncDefaultVal/dut.sv, line:1:1, endln:10:10 |vpiIODecl: \_io_decl: (tid), line:5:29, endln:5:32 |vpiParent: @@ -726,7 +726,7 @@ design: (work@top) |vpiActual: \_logic_net: (regn) |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/FuncDefaultVal/dut.sv, line:1:1, endln:10:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/FuncDefaultVal/dut.sv, line:1:1, endln:10:10 |vpiNet: \_logic_net: (opcode) |vpiName:opcode diff --git a/tests/FuncIoTypespec/FuncIoTypespec.log b/tests/FuncIoTypespec/FuncIoTypespec.log index f443f2e1fd..b9dc488d60 100644 --- a/tests/FuncIoTypespec/FuncIoTypespec.log +++ b/tests/FuncIoTypespec/FuncIoTypespec.log @@ -1550,7 +1550,7 @@ io_decl 12 logic_net 12 logic_typespec 45 logic_var 14 -module 11 +module_inst 11 operation 76 param_assign 23 parameter 23 @@ -1579,7 +1579,7 @@ io_decl 24 logic_net 12 logic_typespec 45 logic_var 19 -module 11 +module_inst 11 operation 102 param_assign 29 parameter 35 @@ -1602,14 +1602,14 @@ design: (work@top) |vpiElaborated:1 |vpiName:work@top |uhdmallModules: -\_module: work@shift (work@shift), file:${SURELOG_DIR}/tests/FuncIoTypespec/dut.sv, line:1:1, endln:81:10 +\_module_inst: work@shift (work@shift), file:${SURELOG_DIR}/tests/FuncIoTypespec/dut.sv, line:1:1, endln:81:10 |vpiParent: \_design: (work@top) |vpiFullName:work@shift |vpiParameter: \_parameter: (work@shift.width_a), line:2:16, endln:2:23 |vpiParent: - \_module: work@shift (work@shift), file:${SURELOG_DIR}/tests/FuncIoTypespec/dut.sv, line:1:1, endln:81:10 + \_module_inst: work@shift (work@shift), file:${SURELOG_DIR}/tests/FuncIoTypespec/dut.sv, line:1:1, endln:81:10 |UINT:4 |vpiTypespec: \_int_typespec: @@ -1618,7 +1618,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@shift.signd_a), line:3:16, endln:3:23 |vpiParent: - \_module: work@shift (work@shift), file:${SURELOG_DIR}/tests/FuncIoTypespec/dut.sv, line:1:1, endln:81:10 + \_module_inst: work@shift (work@shift), file:${SURELOG_DIR}/tests/FuncIoTypespec/dut.sv, line:1:1, endln:81:10 |UINT:1 |vpiTypespec: \_int_typespec: @@ -1627,7 +1627,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@shift.width_s), line:4:16, endln:4:23 |vpiParent: - \_module: work@shift (work@shift), file:${SURELOG_DIR}/tests/FuncIoTypespec/dut.sv, line:1:1, endln:81:10 + \_module_inst: work@shift (work@shift), file:${SURELOG_DIR}/tests/FuncIoTypespec/dut.sv, line:1:1, endln:81:10 |UINT:2 |vpiTypespec: \_int_typespec: @@ -1636,7 +1636,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@shift.width_z), line:5:16, endln:5:23 |vpiParent: - \_module: work@shift (work@shift), file:${SURELOG_DIR}/tests/FuncIoTypespec/dut.sv, line:1:1, endln:81:10 + \_module_inst: work@shift (work@shift), file:${SURELOG_DIR}/tests/FuncIoTypespec/dut.sv, line:1:1, endln:81:10 |UINT:8 |vpiTypespec: \_int_typespec: @@ -1645,7 +1645,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:2:16, endln:2:27 |vpiParent: - \_module: work@shift (work@shift), file:${SURELOG_DIR}/tests/FuncIoTypespec/dut.sv, line:1:1, endln:81:10 + \_module_inst: work@shift (work@shift), file:${SURELOG_DIR}/tests/FuncIoTypespec/dut.sv, line:1:1, endln:81:10 |vpiRhs: \_constant: , line:2:26, endln:2:27 |vpiDecompile:4 @@ -1659,7 +1659,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:3:16, endln:3:27 |vpiParent: - \_module: work@shift (work@shift), file:${SURELOG_DIR}/tests/FuncIoTypespec/dut.sv, line:1:1, endln:81:10 + \_module_inst: work@shift (work@shift), file:${SURELOG_DIR}/tests/FuncIoTypespec/dut.sv, line:1:1, endln:81:10 |vpiRhs: \_constant: , line:3:26, endln:3:27 |vpiDecompile:1 @@ -1673,7 +1673,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:4:16, endln:4:27 |vpiParent: - \_module: work@shift (work@shift), file:${SURELOG_DIR}/tests/FuncIoTypespec/dut.sv, line:1:1, endln:81:10 + \_module_inst: work@shift (work@shift), file:${SURELOG_DIR}/tests/FuncIoTypespec/dut.sv, line:1:1, endln:81:10 |vpiRhs: \_constant: , line:4:26, endln:4:27 |vpiDecompile:2 @@ -1687,7 +1687,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:5:16, endln:5:27 |vpiParent: - \_module: work@shift (work@shift), file:${SURELOG_DIR}/tests/FuncIoTypespec/dut.sv, line:1:1, endln:81:10 + \_module_inst: work@shift (work@shift), file:${SURELOG_DIR}/tests/FuncIoTypespec/dut.sv, line:1:1, endln:81:10 |vpiRhs: \_constant: , line:5:26, endln:5:27 |vpiDecompile:8 @@ -1702,7 +1702,7 @@ design: (work@top) |vpiTaskFunc: \_function: (work@shift.fshl_u_1), line:21:3, endln:36:14 |vpiParent: - \_module: work@shift (work@shift), file:${SURELOG_DIR}/tests/FuncIoTypespec/dut.sv, line:1:1, endln:81:10 + \_module_inst: work@shift (work@shift), file:${SURELOG_DIR}/tests/FuncIoTypespec/dut.sv, line:1:1, endln:81:10 |vpiName:fshl_u_1 |vpiFullName:work@shift.fshl_u_1 |vpiVariables: @@ -1887,7 +1887,7 @@ design: (work@top) |UINT:0 |vpiConstType:9 |vpiParent: - \_module: work@shift (work@shift), file:${SURELOG_DIR}/tests/FuncIoTypespec/dut.sv, line:1:1, endln:81:10 + \_module_inst: work@shift (work@shift), file:${SURELOG_DIR}/tests/FuncIoTypespec/dut.sv, line:1:1, endln:81:10 |vpiIODecl: \_io_decl: (arg1), line:22:26, endln:22:30 |vpiParent: @@ -2146,11 +2146,11 @@ design: (work@top) |vpiActual: \_logic_var: (fshl_u_1), line:21:12, endln:21:25 |vpiInstance: - \_module: work@shift (work@shift), file:${SURELOG_DIR}/tests/FuncIoTypespec/dut.sv, line:1:1, endln:81:10 + \_module_inst: work@shift (work@shift), file:${SURELOG_DIR}/tests/FuncIoTypespec/dut.sv, line:1:1, endln:81:10 |vpiTaskFunc: \_function: (work@shift.fshl_u), line:38:3, endln:43:14 |vpiParent: - \_module: work@shift (work@shift), file:${SURELOG_DIR}/tests/FuncIoTypespec/dut.sv, line:1:1, endln:81:10 + \_module_inst: work@shift (work@shift), file:${SURELOG_DIR}/tests/FuncIoTypespec/dut.sv, line:1:1, endln:81:10 |vpiName:fshl_u |vpiFullName:work@shift.fshl_u |vpiVisibility:1 @@ -2189,7 +2189,7 @@ design: (work@top) |UINT:0 |vpiConstType:9 |vpiParent: - \_module: work@shift (work@shift), file:${SURELOG_DIR}/tests/FuncIoTypespec/dut.sv, line:1:1, endln:81:10 + \_module_inst: work@shift (work@shift), file:${SURELOG_DIR}/tests/FuncIoTypespec/dut.sv, line:1:1, endln:81:10 |vpiIODecl: \_io_decl: (arg1), line:39:26, endln:39:30 |vpiParent: @@ -2337,11 +2337,11 @@ design: (work@top) |vpiActual: \_logic_var: (fshl_u), line:38:12, endln:38:25 |vpiInstance: - \_module: work@shift (work@shift), file:${SURELOG_DIR}/tests/FuncIoTypespec/dut.sv, line:1:1, endln:81:10 + \_module_inst: work@shift (work@shift), file:${SURELOG_DIR}/tests/FuncIoTypespec/dut.sv, line:1:1, endln:81:10 |vpiTaskFunc: \_function: (work@shift.fshr_u), line:45:3, endln:60:14 |vpiParent: - \_module: work@shift (work@shift), file:${SURELOG_DIR}/tests/FuncIoTypespec/dut.sv, line:1:1, endln:81:10 + \_module_inst: work@shift (work@shift), file:${SURELOG_DIR}/tests/FuncIoTypespec/dut.sv, line:1:1, endln:81:10 |vpiName:fshr_u |vpiFullName:work@shift.fshr_u |vpiVariables: @@ -2543,7 +2543,7 @@ design: (work@top) |UINT:0 |vpiConstType:9 |vpiParent: - \_module: work@shift (work@shift), file:${SURELOG_DIR}/tests/FuncIoTypespec/dut.sv, line:1:1, endln:81:10 + \_module_inst: work@shift (work@shift), file:${SURELOG_DIR}/tests/FuncIoTypespec/dut.sv, line:1:1, endln:81:10 |vpiIODecl: \_io_decl: (arg1), line:46:26, endln:46:30 |vpiParent: @@ -2818,11 +2818,11 @@ design: (work@top) |vpiActual: \_logic_var: (fshr_u), line:45:12, endln:45:25 |vpiInstance: - \_module: work@shift (work@shift), file:${SURELOG_DIR}/tests/FuncIoTypespec/dut.sv, line:1:1, endln:81:10 + \_module_inst: work@shift (work@shift), file:${SURELOG_DIR}/tests/FuncIoTypespec/dut.sv, line:1:1, endln:81:10 |vpiTaskFunc: \_function: (work@shift.fshl_s), line:62:3, endln:80:14 |vpiParent: - \_module: work@shift (work@shift), file:${SURELOG_DIR}/tests/FuncIoTypespec/dut.sv, line:1:1, endln:81:10 + \_module_inst: work@shift (work@shift), file:${SURELOG_DIR}/tests/FuncIoTypespec/dut.sv, line:1:1, endln:81:10 |vpiName:fshl_s |vpiFullName:work@shift.fshl_s |vpiVariables: @@ -2887,7 +2887,7 @@ design: (work@top) |UINT:0 |vpiConstType:9 |vpiParent: - \_module: work@shift (work@shift), file:${SURELOG_DIR}/tests/FuncIoTypespec/dut.sv, line:1:1, endln:81:10 + \_module_inst: work@shift (work@shift), file:${SURELOG_DIR}/tests/FuncIoTypespec/dut.sv, line:1:1, endln:81:10 |vpiIODecl: \_io_decl: (arg1), line:63:26, endln:63:30 |vpiParent: @@ -3286,29 +3286,29 @@ design: (work@top) |vpiActual: \_logic_var: (fshl_s), line:62:12, endln:62:25 |vpiInstance: - \_module: work@shift (work@shift), file:${SURELOG_DIR}/tests/FuncIoTypespec/dut.sv, line:1:1, endln:81:10 + \_module_inst: work@shift (work@shift), file:${SURELOG_DIR}/tests/FuncIoTypespec/dut.sv, line:1:1, endln:81:10 |vpiNet: \_logic_net: (work@shift.a), line:1:14, endln:1:15 |vpiParent: - \_module: work@shift (work@shift), file:${SURELOG_DIR}/tests/FuncIoTypespec/dut.sv, line:1:1, endln:81:10 + \_module_inst: work@shift (work@shift), file:${SURELOG_DIR}/tests/FuncIoTypespec/dut.sv, line:1:1, endln:81:10 |vpiName:a |vpiFullName:work@shift.a |vpiNet: \_logic_net: (work@shift.s), line:1:16, endln:1:17 |vpiParent: - \_module: work@shift (work@shift), file:${SURELOG_DIR}/tests/FuncIoTypespec/dut.sv, line:1:1, endln:81:10 + \_module_inst: work@shift (work@shift), file:${SURELOG_DIR}/tests/FuncIoTypespec/dut.sv, line:1:1, endln:81:10 |vpiName:s |vpiFullName:work@shift.s |vpiNet: \_logic_net: (work@shift.z), line:1:18, endln:1:19 |vpiParent: - \_module: work@shift (work@shift), file:${SURELOG_DIR}/tests/FuncIoTypespec/dut.sv, line:1:1, endln:81:10 + \_module_inst: work@shift (work@shift), file:${SURELOG_DIR}/tests/FuncIoTypespec/dut.sv, line:1:1, endln:81:10 |vpiName:z |vpiFullName:work@shift.z |vpiPort: \_port: (a), line:1:14, endln:1:15 |vpiParent: - \_module: work@shift (work@shift), file:${SURELOG_DIR}/tests/FuncIoTypespec/dut.sv, line:1:1, endln:81:10 + \_module_inst: work@shift (work@shift), file:${SURELOG_DIR}/tests/FuncIoTypespec/dut.sv, line:1:1, endln:81:10 |vpiName:a |vpiDirection:1 |vpiLowConn: @@ -3348,7 +3348,7 @@ design: (work@top) |vpiPort: \_port: (s), line:1:16, endln:1:17 |vpiParent: - \_module: work@shift (work@shift), file:${SURELOG_DIR}/tests/FuncIoTypespec/dut.sv, line:1:1, endln:81:10 + \_module_inst: work@shift (work@shift), file:${SURELOG_DIR}/tests/FuncIoTypespec/dut.sv, line:1:1, endln:81:10 |vpiName:s |vpiDirection:1 |vpiLowConn: @@ -3388,7 +3388,7 @@ design: (work@top) |vpiPort: \_port: (z), line:1:18, endln:1:19 |vpiParent: - \_module: work@shift (work@shift), file:${SURELOG_DIR}/tests/FuncIoTypespec/dut.sv, line:1:1, endln:81:10 + \_module_inst: work@shift (work@shift), file:${SURELOG_DIR}/tests/FuncIoTypespec/dut.sv, line:1:1, endln:81:10 |vpiName:z |vpiDirection:2 |vpiLowConn: @@ -3426,14 +3426,14 @@ design: (work@top) |UINT:0 |vpiConstType:9 |uhdmallModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/FuncIoTypespec/dut.sv, line:83:1, endln:102:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/FuncIoTypespec/dut.sv, line:83:1, endln:102:10 |vpiParent: \_design: (work@top) |vpiFullName:work@top |vpiParameter: \_parameter: (work@top.width_a), line:85:13, endln:85:20 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/FuncIoTypespec/dut.sv, line:83:1, endln:102:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/FuncIoTypespec/dut.sv, line:83:1, endln:102:10 |UINT:240 |vpiTypespec: \_int_typespec: @@ -3442,7 +3442,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.width_s), line:86:13, endln:86:20 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/FuncIoTypespec/dut.sv, line:83:1, endln:102:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/FuncIoTypespec/dut.sv, line:83:1, endln:102:10 |UINT:9 |vpiTypespec: \_int_typespec: @@ -3451,7 +3451,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.width_z), line:87:13, endln:87:20 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/FuncIoTypespec/dut.sv, line:83:1, endln:102:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/FuncIoTypespec/dut.sv, line:83:1, endln:102:10 |UINT:240 |vpiTypespec: \_int_typespec: @@ -3460,7 +3460,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:85:13, endln:85:26 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/FuncIoTypespec/dut.sv, line:83:1, endln:102:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/FuncIoTypespec/dut.sv, line:83:1, endln:102:10 |vpiRhs: \_constant: , line:85:23, endln:85:26 |vpiDecompile:240 @@ -3474,7 +3474,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:86:13, endln:86:24 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/FuncIoTypespec/dut.sv, line:83:1, endln:102:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/FuncIoTypespec/dut.sv, line:83:1, endln:102:10 |vpiRhs: \_constant: , line:86:23, endln:86:24 |vpiDecompile:9 @@ -3488,7 +3488,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:87:13, endln:87:26 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/FuncIoTypespec/dut.sv, line:83:1, endln:102:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/FuncIoTypespec/dut.sv, line:83:1, endln:102:10 |vpiRhs: \_constant: , line:87:23, endln:87:26 |vpiDecompile:240 @@ -3503,25 +3503,25 @@ design: (work@top) |vpiNet: \_logic_net: (work@top.a), line:83:13, endln:83:14 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/FuncIoTypespec/dut.sv, line:83:1, endln:102:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/FuncIoTypespec/dut.sv, line:83:1, endln:102:10 |vpiName:a |vpiFullName:work@top.a |vpiNet: \_logic_net: (work@top.s), line:83:15, endln:83:16 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/FuncIoTypespec/dut.sv, line:83:1, endln:102:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/FuncIoTypespec/dut.sv, line:83:1, endln:102:10 |vpiName:s |vpiFullName:work@top.s |vpiNet: \_logic_net: (work@top.z), line:83:17, endln:83:18 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/FuncIoTypespec/dut.sv, line:83:1, endln:102:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/FuncIoTypespec/dut.sv, line:83:1, endln:102:10 |vpiName:z |vpiFullName:work@top.z |vpiPort: \_port: (a), line:83:13, endln:83:14 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/FuncIoTypespec/dut.sv, line:83:1, endln:102:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/FuncIoTypespec/dut.sv, line:83:1, endln:102:10 |vpiName:a |vpiDirection:1 |vpiLowConn: @@ -3561,7 +3561,7 @@ design: (work@top) |vpiPort: \_port: (s), line:83:15, endln:83:16 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/FuncIoTypespec/dut.sv, line:83:1, endln:102:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/FuncIoTypespec/dut.sv, line:83:1, endln:102:10 |vpiName:s |vpiDirection:1 |vpiLowConn: @@ -3601,7 +3601,7 @@ design: (work@top) |vpiPort: \_port: (z), line:83:17, endln:83:18 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/FuncIoTypespec/dut.sv, line:83:1, endln:102:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/FuncIoTypespec/dut.sv, line:83:1, endln:102:10 |vpiName:z |vpiDirection:2 |vpiLowConn: @@ -3639,12 +3639,12 @@ design: (work@top) |UINT:0 |vpiConstType:9 |uhdmtopModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/FuncIoTypespec/dut.sv, line:83:1, endln:102:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/FuncIoTypespec/dut.sv, line:83:1, endln:102:10 |vpiName:work@top |vpiParameter: \_parameter: (work@top.width_a), line:85:13, endln:85:20 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/FuncIoTypespec/dut.sv, line:83:1, endln:102:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/FuncIoTypespec/dut.sv, line:83:1, endln:102:10 |UINT:240 |vpiTypespec: \_int_typespec: @@ -3655,7 +3655,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.width_s), line:86:13, endln:86:20 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/FuncIoTypespec/dut.sv, line:83:1, endln:102:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/FuncIoTypespec/dut.sv, line:83:1, endln:102:10 |UINT:9 |vpiTypespec: \_int_typespec: @@ -3666,7 +3666,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.width_z), line:87:13, endln:87:20 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/FuncIoTypespec/dut.sv, line:83:1, endln:102:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/FuncIoTypespec/dut.sv, line:83:1, endln:102:10 |UINT:240 |vpiTypespec: \_int_typespec: @@ -3677,7 +3677,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:85:13, endln:85:26 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/FuncIoTypespec/dut.sv, line:83:1, endln:102:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/FuncIoTypespec/dut.sv, line:83:1, endln:102:10 |vpiRhs: \_constant: , line:85:23, endln:85:26 |vpiDecompile:240 @@ -3691,7 +3691,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:86:13, endln:86:24 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/FuncIoTypespec/dut.sv, line:83:1, endln:102:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/FuncIoTypespec/dut.sv, line:83:1, endln:102:10 |vpiRhs: \_constant: , line:86:23, endln:86:24 |vpiDecompile:9 @@ -3705,7 +3705,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:87:13, endln:87:26 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/FuncIoTypespec/dut.sv, line:83:1, endln:102:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/FuncIoTypespec/dut.sv, line:83:1, endln:102:10 |vpiRhs: \_constant: , line:87:23, endln:87:26 |vpiDecompile:240 @@ -3721,7 +3721,7 @@ design: (work@top) |vpiNet: \_logic_net: (work@top.a), line:83:13, endln:83:14 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/FuncIoTypespec/dut.sv, line:83:1, endln:102:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/FuncIoTypespec/dut.sv, line:83:1, endln:102:10 |vpiTypespec: \_logic_typespec: , line:89:9, endln:89:22 |vpiRange: @@ -3747,7 +3747,7 @@ design: (work@top) |vpiNet: \_logic_net: (work@top.s), line:83:15, endln:83:16 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/FuncIoTypespec/dut.sv, line:83:1, endln:102:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/FuncIoTypespec/dut.sv, line:83:1, endln:102:10 |vpiTypespec: \_logic_typespec: , line:90:9, endln:90:22 |vpiRange: @@ -3773,7 +3773,7 @@ design: (work@top) |vpiNet: \_logic_net: (work@top.z), line:83:17, endln:83:18 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/FuncIoTypespec/dut.sv, line:83:1, endln:102:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/FuncIoTypespec/dut.sv, line:83:1, endln:102:10 |vpiTypespec: \_logic_typespec: , line:91:10, endln:91:23 |vpiRange: @@ -3800,7 +3800,7 @@ design: (work@top) |vpiPort: \_port: (a), line:83:13, endln:83:14 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/FuncIoTypespec/dut.sv, line:83:1, endln:102:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/FuncIoTypespec/dut.sv, line:83:1, endln:102:10 |vpiName:a |vpiDirection:1 |vpiLowConn: @@ -3834,11 +3834,11 @@ design: (work@top) |UINT:0 |vpiConstType:9 |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/FuncIoTypespec/dut.sv, line:83:1, endln:102:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/FuncIoTypespec/dut.sv, line:83:1, endln:102:10 |vpiPort: \_port: (s), line:83:15, endln:83:16 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/FuncIoTypespec/dut.sv, line:83:1, endln:102:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/FuncIoTypespec/dut.sv, line:83:1, endln:102:10 |vpiName:s |vpiDirection:1 |vpiLowConn: @@ -3872,11 +3872,11 @@ design: (work@top) |UINT:0 |vpiConstType:9 |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/FuncIoTypespec/dut.sv, line:83:1, endln:102:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/FuncIoTypespec/dut.sv, line:83:1, endln:102:10 |vpiPort: \_port: (z), line:83:17, endln:83:18 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/FuncIoTypespec/dut.sv, line:83:1, endln:102:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/FuncIoTypespec/dut.sv, line:83:1, endln:102:10 |vpiName:z |vpiDirection:2 |vpiLowConn: @@ -3910,17 +3910,17 @@ design: (work@top) |UINT:0 |vpiConstType:9 |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/FuncIoTypespec/dut.sv, line:83:1, endln:102:10 - |vpiModule: - \_module: work@shift (work@top.inst), file:${SURELOG_DIR}/tests/FuncIoTypespec/dut.sv, line:93:3, endln:101:5 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/FuncIoTypespec/dut.sv, line:83:1, endln:102:10 + |vpiModuleInst: + \_module_inst: work@shift (work@top.inst), file:${SURELOG_DIR}/tests/FuncIoTypespec/dut.sv, line:93:3, endln:101:5 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/FuncIoTypespec/dut.sv, line:83:1, endln:102:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/FuncIoTypespec/dut.sv, line:83:1, endln:102:10 |vpiName:inst |vpiFullName:work@top.inst |vpiParameter: \_parameter: (work@top.inst.width_a), line:2:16, endln:2:23 |vpiParent: - \_module: work@shift (work@top.inst), file:${SURELOG_DIR}/tests/FuncIoTypespec/dut.sv, line:93:3, endln:101:5 + \_module_inst: work@shift (work@top.inst), file:${SURELOG_DIR}/tests/FuncIoTypespec/dut.sv, line:93:3, endln:101:5 |UINT:4 |vpiTypespec: \_int_typespec: @@ -3931,7 +3931,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.inst.signd_a), line:3:16, endln:3:23 |vpiParent: - \_module: work@shift (work@top.inst), file:${SURELOG_DIR}/tests/FuncIoTypespec/dut.sv, line:93:3, endln:101:5 + \_module_inst: work@shift (work@top.inst), file:${SURELOG_DIR}/tests/FuncIoTypespec/dut.sv, line:93:3, endln:101:5 |UINT:1 |vpiTypespec: \_int_typespec: @@ -3942,7 +3942,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.inst.width_s), line:4:16, endln:4:23 |vpiParent: - \_module: work@shift (work@top.inst), file:${SURELOG_DIR}/tests/FuncIoTypespec/dut.sv, line:93:3, endln:101:5 + \_module_inst: work@shift (work@top.inst), file:${SURELOG_DIR}/tests/FuncIoTypespec/dut.sv, line:93:3, endln:101:5 |UINT:2 |vpiTypespec: \_int_typespec: @@ -3953,7 +3953,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.inst.width_z), line:5:16, endln:5:23 |vpiParent: - \_module: work@shift (work@top.inst), file:${SURELOG_DIR}/tests/FuncIoTypespec/dut.sv, line:93:3, endln:101:5 + \_module_inst: work@shift (work@top.inst), file:${SURELOG_DIR}/tests/FuncIoTypespec/dut.sv, line:93:3, endln:101:5 |UINT:8 |vpiTypespec: \_int_typespec: @@ -3964,7 +3964,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:2:16, endln:2:27 |vpiParent: - \_module: work@shift (work@top.inst), file:${SURELOG_DIR}/tests/FuncIoTypespec/dut.sv, line:93:3, endln:101:5 + \_module_inst: work@shift (work@top.inst), file:${SURELOG_DIR}/tests/FuncIoTypespec/dut.sv, line:93:3, endln:101:5 |vpiOverriden:1 |vpiRhs: \_constant: , line:2:26, endln:2:27 @@ -3979,7 +3979,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:3:16, endln:3:27 |vpiParent: - \_module: work@shift (work@top.inst), file:${SURELOG_DIR}/tests/FuncIoTypespec/dut.sv, line:93:3, endln:101:5 + \_module_inst: work@shift (work@top.inst), file:${SURELOG_DIR}/tests/FuncIoTypespec/dut.sv, line:93:3, endln:101:5 |vpiRhs: \_constant: , line:3:26, endln:3:27 |vpiDecompile:1 @@ -3993,7 +3993,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:4:16, endln:4:27 |vpiParent: - \_module: work@shift (work@top.inst), file:${SURELOG_DIR}/tests/FuncIoTypespec/dut.sv, line:93:3, endln:101:5 + \_module_inst: work@shift (work@top.inst), file:${SURELOG_DIR}/tests/FuncIoTypespec/dut.sv, line:93:3, endln:101:5 |vpiOverriden:1 |vpiRhs: \_constant: , line:4:26, endln:4:27 @@ -4008,7 +4008,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:5:16, endln:5:27 |vpiParent: - \_module: work@shift (work@top.inst), file:${SURELOG_DIR}/tests/FuncIoTypespec/dut.sv, line:93:3, endln:101:5 + \_module_inst: work@shift (work@top.inst), file:${SURELOG_DIR}/tests/FuncIoTypespec/dut.sv, line:93:3, endln:101:5 |vpiOverriden:1 |vpiRhs: \_constant: , line:5:26, endln:5:27 @@ -4026,7 +4026,7 @@ design: (work@top) |vpiTaskFunc: \_function: (work@top.inst.fshl_u_1), line:21:3, endln:36:14 |vpiParent: - \_module: work@shift (work@top.inst), file:${SURELOG_DIR}/tests/FuncIoTypespec/dut.sv, line:93:3, endln:101:5 + \_module_inst: work@shift (work@top.inst), file:${SURELOG_DIR}/tests/FuncIoTypespec/dut.sv, line:93:3, endln:101:5 |vpiName:fshl_u_1 |vpiFullName:work@top.inst.fshl_u_1 |vpiVariables: @@ -4156,7 +4156,7 @@ design: (work@top) |vpiReturn: \_logic_var: , line:21:12, endln:21:25 |vpiParent: - \_module: work@shift (work@top.inst), file:${SURELOG_DIR}/tests/FuncIoTypespec/dut.sv, line:93:3, endln:101:5 + \_module_inst: work@shift (work@top.inst), file:${SURELOG_DIR}/tests/FuncIoTypespec/dut.sv, line:93:3, endln:101:5 |vpiIODecl: \_io_decl: (arg1), line:22:26, endln:22:30 |vpiParent: @@ -4346,18 +4346,18 @@ design: (work@top) |vpiActual: \_logic_var: , line:21:12, endln:21:25 |vpiInstance: - \_module: work@shift (work@top.inst), file:${SURELOG_DIR}/tests/FuncIoTypespec/dut.sv, line:93:3, endln:101:5 + \_module_inst: work@shift (work@top.inst), file:${SURELOG_DIR}/tests/FuncIoTypespec/dut.sv, line:93:3, endln:101:5 |vpiTaskFunc: \_function: (work@top.inst.fshl_u), line:38:3, endln:43:14 |vpiParent: - \_module: work@shift (work@top.inst), file:${SURELOG_DIR}/tests/FuncIoTypespec/dut.sv, line:93:3, endln:101:5 + \_module_inst: work@shift (work@top.inst), file:${SURELOG_DIR}/tests/FuncIoTypespec/dut.sv, line:93:3, endln:101:5 |vpiName:fshl_u |vpiFullName:work@top.inst.fshl_u |vpiVisibility:1 |vpiReturn: \_logic_var: , line:38:12, endln:38:25 |vpiParent: - \_module: work@shift (work@top.inst), file:${SURELOG_DIR}/tests/FuncIoTypespec/dut.sv, line:93:3, endln:101:5 + \_module_inst: work@shift (work@top.inst), file:${SURELOG_DIR}/tests/FuncIoTypespec/dut.sv, line:93:3, endln:101:5 |vpiIODecl: \_io_decl: (arg1), line:39:26, endln:39:30 |vpiParent: @@ -4439,11 +4439,11 @@ design: (work@top) |vpiActual: \_logic_var: , line:38:12, endln:38:25 |vpiInstance: - \_module: work@shift (work@top.inst), file:${SURELOG_DIR}/tests/FuncIoTypespec/dut.sv, line:93:3, endln:101:5 + \_module_inst: work@shift (work@top.inst), file:${SURELOG_DIR}/tests/FuncIoTypespec/dut.sv, line:93:3, endln:101:5 |vpiTaskFunc: \_function: (work@top.inst.fshr_u), line:45:3, endln:60:14 |vpiParent: - \_module: work@shift (work@top.inst), file:${SURELOG_DIR}/tests/FuncIoTypespec/dut.sv, line:93:3, endln:101:5 + \_module_inst: work@shift (work@top.inst), file:${SURELOG_DIR}/tests/FuncIoTypespec/dut.sv, line:93:3, endln:101:5 |vpiName:fshr_u |vpiFullName:work@top.inst.fshr_u |vpiVariables: @@ -4594,7 +4594,7 @@ design: (work@top) |vpiReturn: \_logic_var: , line:45:12, endln:45:25 |vpiParent: - \_module: work@shift (work@top.inst), file:${SURELOG_DIR}/tests/FuncIoTypespec/dut.sv, line:93:3, endln:101:5 + \_module_inst: work@shift (work@top.inst), file:${SURELOG_DIR}/tests/FuncIoTypespec/dut.sv, line:93:3, endln:101:5 |vpiIODecl: \_io_decl: (arg1), line:46:26, endln:46:30 |vpiParent: @@ -4789,11 +4789,11 @@ design: (work@top) |vpiActual: \_logic_var: , line:45:12, endln:45:25 |vpiInstance: - \_module: work@shift (work@top.inst), file:${SURELOG_DIR}/tests/FuncIoTypespec/dut.sv, line:93:3, endln:101:5 + \_module_inst: work@shift (work@top.inst), file:${SURELOG_DIR}/tests/FuncIoTypespec/dut.sv, line:93:3, endln:101:5 |vpiTaskFunc: \_function: (work@top.inst.fshl_s), line:62:3, endln:80:14 |vpiParent: - \_module: work@shift (work@top.inst), file:${SURELOG_DIR}/tests/FuncIoTypespec/dut.sv, line:93:3, endln:101:5 + \_module_inst: work@shift (work@top.inst), file:${SURELOG_DIR}/tests/FuncIoTypespec/dut.sv, line:93:3, endln:101:5 |vpiName:fshl_s |vpiFullName:work@top.inst.fshl_s |vpiVariables: @@ -4809,7 +4809,7 @@ design: (work@top) |vpiReturn: \_logic_var: , line:62:12, endln:62:25 |vpiParent: - \_module: work@shift (work@top.inst), file:${SURELOG_DIR}/tests/FuncIoTypespec/dut.sv, line:93:3, endln:101:5 + \_module_inst: work@shift (work@top.inst), file:${SURELOG_DIR}/tests/FuncIoTypespec/dut.sv, line:93:3, endln:101:5 |vpiIODecl: \_io_decl: (arg1), line:63:26, endln:63:30 |vpiParent: @@ -5131,11 +5131,11 @@ design: (work@top) |vpiActual: \_logic_var: , line:62:12, endln:62:25 |vpiInstance: - \_module: work@shift (work@top.inst), file:${SURELOG_DIR}/tests/FuncIoTypespec/dut.sv, line:93:3, endln:101:5 + \_module_inst: work@shift (work@top.inst), file:${SURELOG_DIR}/tests/FuncIoTypespec/dut.sv, line:93:3, endln:101:5 |vpiNet: \_logic_net: (work@top.inst.a), line:1:14, endln:1:15 |vpiParent: - \_module: work@shift (work@top.inst), file:${SURELOG_DIR}/tests/FuncIoTypespec/dut.sv, line:93:3, endln:101:5 + \_module_inst: work@shift (work@top.inst), file:${SURELOG_DIR}/tests/FuncIoTypespec/dut.sv, line:93:3, endln:101:5 |vpiTypespec: \_logic_typespec: , line:7:9, endln:7:22 |vpiRange: @@ -5161,7 +5161,7 @@ design: (work@top) |vpiNet: \_logic_net: (work@top.inst.s), line:1:16, endln:1:17 |vpiParent: - \_module: work@shift (work@top.inst), file:${SURELOG_DIR}/tests/FuncIoTypespec/dut.sv, line:93:3, endln:101:5 + \_module_inst: work@shift (work@top.inst), file:${SURELOG_DIR}/tests/FuncIoTypespec/dut.sv, line:93:3, endln:101:5 |vpiTypespec: \_logic_typespec: , line:8:9, endln:8:22 |vpiRange: @@ -5187,7 +5187,7 @@ design: (work@top) |vpiNet: \_logic_net: (work@top.inst.z), line:1:18, endln:1:19 |vpiParent: - \_module: work@shift (work@top.inst), file:${SURELOG_DIR}/tests/FuncIoTypespec/dut.sv, line:93:3, endln:101:5 + \_module_inst: work@shift (work@top.inst), file:${SURELOG_DIR}/tests/FuncIoTypespec/dut.sv, line:93:3, endln:101:5 |vpiTypespec: \_logic_typespec: , line:9:10, endln:9:24 |vpiRange: @@ -5211,11 +5211,11 @@ design: (work@top) |vpiName:z |vpiFullName:work@top.inst.z |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/FuncIoTypespec/dut.sv, line:83:1, endln:102:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/FuncIoTypespec/dut.sv, line:83:1, endln:102:10 |vpiPort: \_port: (a), line:1:14, endln:1:15 |vpiParent: - \_module: work@shift (work@top.inst), file:${SURELOG_DIR}/tests/FuncIoTypespec/dut.sv, line:93:3, endln:101:5 + \_module_inst: work@shift (work@top.inst), file:${SURELOG_DIR}/tests/FuncIoTypespec/dut.sv, line:93:3, endln:101:5 |vpiName:a |vpiDirection:1 |vpiHighConn: @@ -5257,11 +5257,11 @@ design: (work@top) |UINT:0 |vpiConstType:9 |vpiInstance: - \_module: work@shift (work@top.inst), file:${SURELOG_DIR}/tests/FuncIoTypespec/dut.sv, line:93:3, endln:101:5 + \_module_inst: work@shift (work@top.inst), file:${SURELOG_DIR}/tests/FuncIoTypespec/dut.sv, line:93:3, endln:101:5 |vpiPort: \_port: (s), line:1:16, endln:1:17 |vpiParent: - \_module: work@shift (work@top.inst), file:${SURELOG_DIR}/tests/FuncIoTypespec/dut.sv, line:93:3, endln:101:5 + \_module_inst: work@shift (work@top.inst), file:${SURELOG_DIR}/tests/FuncIoTypespec/dut.sv, line:93:3, endln:101:5 |vpiName:s |vpiDirection:1 |vpiHighConn: @@ -5303,11 +5303,11 @@ design: (work@top) |UINT:0 |vpiConstType:9 |vpiInstance: - \_module: work@shift (work@top.inst), file:${SURELOG_DIR}/tests/FuncIoTypespec/dut.sv, line:93:3, endln:101:5 + \_module_inst: work@shift (work@top.inst), file:${SURELOG_DIR}/tests/FuncIoTypespec/dut.sv, line:93:3, endln:101:5 |vpiPort: \_port: (z), line:1:18, endln:1:19 |vpiParent: - \_module: work@shift (work@top.inst), file:${SURELOG_DIR}/tests/FuncIoTypespec/dut.sv, line:93:3, endln:101:5 + \_module_inst: work@shift (work@top.inst), file:${SURELOG_DIR}/tests/FuncIoTypespec/dut.sv, line:93:3, endln:101:5 |vpiName:z |vpiDirection:2 |vpiHighConn: @@ -5349,11 +5349,11 @@ design: (work@top) |UINT:0 |vpiConstType:9 |vpiInstance: - \_module: work@shift (work@top.inst), file:${SURELOG_DIR}/tests/FuncIoTypespec/dut.sv, line:93:3, endln:101:5 + \_module_inst: work@shift (work@top.inst), file:${SURELOG_DIR}/tests/FuncIoTypespec/dut.sv, line:93:3, endln:101:5 |vpiGenScopeArray: \_gen_scope_array: (work@top.inst.SGNED), line:11:12, endln:18:6 |vpiParent: - \_module: work@shift (work@top.inst), file:${SURELOG_DIR}/tests/FuncIoTypespec/dut.sv, line:93:3, endln:101:5 + \_module_inst: work@shift (work@top.inst), file:${SURELOG_DIR}/tests/FuncIoTypespec/dut.sv, line:93:3, endln:101:5 |vpiName:SGNED |vpiFullName:work@top.inst.SGNED |vpiGenScope: diff --git a/tests/FuncNoArgs/FuncNoArgs.log b/tests/FuncNoArgs/FuncNoArgs.log index a6e2fd9e70..27f73abb50 100644 --- a/tests/FuncNoArgs/FuncNoArgs.log +++ b/tests/FuncNoArgs/FuncNoArgs.log @@ -556,7 +556,7 @@ io_decl 11 logic_net 2 logic_typespec 3 logic_var 1 -module 7 +module_inst 7 operation 8 package 2 param_assign 14 @@ -593,7 +593,7 @@ io_decl 22 logic_net 2 logic_typespec 3 logic_var 1 -module 7 +module_inst 7 operation 12 package 2 param_assign 14 @@ -1091,14 +1091,14 @@ design: (work@my_opt_reduce_or) \_int_typespec: |vpiSigned:1 |uhdmallModules: -\_module: work@my_opt_reduce_or (work@my_opt_reduce_or), file:${SURELOG_DIR}/tests/FuncNoArgs/dut.sv, line:1:1, endln:31:10 +\_module_inst: work@my_opt_reduce_or (work@my_opt_reduce_or), file:${SURELOG_DIR}/tests/FuncNoArgs/dut.sv, line:1:1, endln:31:10 |vpiParent: \_design: (work@my_opt_reduce_or) |vpiFullName:work@my_opt_reduce_or |vpiParameter: \_parameter: (work@my_opt_reduce_or.A_SIGNED), line:2:15, endln:2:23 |vpiParent: - \_module: work@my_opt_reduce_or (work@my_opt_reduce_or), file:${SURELOG_DIR}/tests/FuncNoArgs/dut.sv, line:1:1, endln:31:10 + \_module_inst: work@my_opt_reduce_or (work@my_opt_reduce_or), file:${SURELOG_DIR}/tests/FuncNoArgs/dut.sv, line:1:1, endln:31:10 |UINT:0 |vpiTypespec: \_int_typespec: @@ -1107,7 +1107,7 @@ design: (work@my_opt_reduce_or) |vpiParameter: \_parameter: (work@my_opt_reduce_or.A_WIDTH), line:3:15, endln:3:22 |vpiParent: - \_module: work@my_opt_reduce_or (work@my_opt_reduce_or), file:${SURELOG_DIR}/tests/FuncNoArgs/dut.sv, line:1:1, endln:31:10 + \_module_inst: work@my_opt_reduce_or (work@my_opt_reduce_or), file:${SURELOG_DIR}/tests/FuncNoArgs/dut.sv, line:1:1, endln:31:10 |UINT:1 |vpiTypespec: \_int_typespec: @@ -1116,7 +1116,7 @@ design: (work@my_opt_reduce_or) |vpiParameter: \_parameter: (work@my_opt_reduce_or._TECHMAP_CONSTMSK_A_), line:5:32, endln:5:52 |vpiParent: - \_module: work@my_opt_reduce_or (work@my_opt_reduce_or), file:${SURELOG_DIR}/tests/FuncNoArgs/dut.sv, line:1:1, endln:31:10 + \_module_inst: work@my_opt_reduce_or (work@my_opt_reduce_or), file:${SURELOG_DIR}/tests/FuncNoArgs/dut.sv, line:1:1, endln:31:10 |vpiTypespec: \_logic_typespec: , line:5:15, endln:5:31 |vpiParent: @@ -1162,7 +1162,7 @@ design: (work@my_opt_reduce_or) |vpiParamAssign: \_param_assign: , line:2:15, endln:2:27 |vpiParent: - \_module: work@my_opt_reduce_or (work@my_opt_reduce_or), file:${SURELOG_DIR}/tests/FuncNoArgs/dut.sv, line:1:1, endln:31:10 + \_module_inst: work@my_opt_reduce_or (work@my_opt_reduce_or), file:${SURELOG_DIR}/tests/FuncNoArgs/dut.sv, line:1:1, endln:31:10 |vpiRhs: \_constant: , line:2:26, endln:2:27 |vpiDecompile:0 @@ -1176,7 +1176,7 @@ design: (work@my_opt_reduce_or) |vpiParamAssign: \_param_assign: , line:3:15, endln:3:26 |vpiParent: - \_module: work@my_opt_reduce_or (work@my_opt_reduce_or), file:${SURELOG_DIR}/tests/FuncNoArgs/dut.sv, line:1:1, endln:31:10 + \_module_inst: work@my_opt_reduce_or (work@my_opt_reduce_or), file:${SURELOG_DIR}/tests/FuncNoArgs/dut.sv, line:1:1, endln:31:10 |vpiRhs: \_constant: , line:3:25, endln:3:26 |vpiDecompile:1 @@ -1190,7 +1190,7 @@ design: (work@my_opt_reduce_or) |vpiParamAssign: \_param_assign: , line:5:32, endln:5:62 |vpiParent: - \_module: work@my_opt_reduce_or (work@my_opt_reduce_or), file:${SURELOG_DIR}/tests/FuncNoArgs/dut.sv, line:1:1, endln:31:10 + \_module_inst: work@my_opt_reduce_or (work@my_opt_reduce_or), file:${SURELOG_DIR}/tests/FuncNoArgs/dut.sv, line:1:1, endln:31:10 |vpiRhs: \_operation: , line:5:55, endln:5:62 |vpiOpType:75 @@ -1212,7 +1212,7 @@ design: (work@my_opt_reduce_or) |vpiTaskFunc: \_function: (work@my_opt_reduce_or.count_nonconst_bits), line:7:5, endln:15:16 |vpiParent: - \_module: work@my_opt_reduce_or (work@my_opt_reduce_or), file:${SURELOG_DIR}/tests/FuncNoArgs/dut.sv, line:1:1, endln:31:10 + \_module_inst: work@my_opt_reduce_or (work@my_opt_reduce_or), file:${SURELOG_DIR}/tests/FuncNoArgs/dut.sv, line:1:1, endln:31:10 |vpiName:count_nonconst_bits |vpiFullName:work@my_opt_reduce_or.count_nonconst_bits |vpiVariables: @@ -1231,7 +1231,7 @@ design: (work@my_opt_reduce_or) |vpiSigned:1 |vpiSigned:1 |vpiParent: - \_module: work@my_opt_reduce_or (work@my_opt_reduce_or), file:${SURELOG_DIR}/tests/FuncNoArgs/dut.sv, line:1:1, endln:31:10 + \_module_inst: work@my_opt_reduce_or (work@my_opt_reduce_or), file:${SURELOG_DIR}/tests/FuncNoArgs/dut.sv, line:1:1, endln:31:10 |vpiStmt: \_begin: (work@my_opt_reduce_or.count_nonconst_bits), line:9:9, endln:14:12 |vpiParent: @@ -1399,21 +1399,21 @@ design: (work@my_opt_reduce_or) |vpiActual: \_integer_var: (count_nonconst_bits), line:7:14, endln:7:21 |vpiInstance: - \_module: work@my_opt_reduce_or (work@my_opt_reduce_or), file:${SURELOG_DIR}/tests/FuncNoArgs/dut.sv, line:1:1, endln:31:10 + \_module_inst: work@my_opt_reduce_or (work@my_opt_reduce_or), file:${SURELOG_DIR}/tests/FuncNoArgs/dut.sv, line:1:1, endln:31:10 |vpiNet: \_logic_net: (work@my_opt_reduce_or.tmp), line:28:37, endln:28:40 |vpiParent: - \_module: work@my_opt_reduce_or (work@my_opt_reduce_or), file:${SURELOG_DIR}/tests/FuncNoArgs/dut.sv, line:1:1, endln:31:10 + \_module_inst: work@my_opt_reduce_or (work@my_opt_reduce_or), file:${SURELOG_DIR}/tests/FuncNoArgs/dut.sv, line:1:1, endln:31:10 |vpiName:tmp |vpiFullName:work@my_opt_reduce_or.tmp |vpiNetType:48 |uhdmtopModules: -\_module: work@my_opt_reduce_or (work@my_opt_reduce_or), file:${SURELOG_DIR}/tests/FuncNoArgs/dut.sv, line:1:1, endln:31:10 +\_module_inst: work@my_opt_reduce_or (work@my_opt_reduce_or), file:${SURELOG_DIR}/tests/FuncNoArgs/dut.sv, line:1:1, endln:31:10 |vpiName:work@my_opt_reduce_or |vpiParameter: \_parameter: (work@my_opt_reduce_or.A_SIGNED), line:2:15, endln:2:23 |vpiParent: - \_module: work@my_opt_reduce_or (work@my_opt_reduce_or), file:${SURELOG_DIR}/tests/FuncNoArgs/dut.sv, line:1:1, endln:31:10 + \_module_inst: work@my_opt_reduce_or (work@my_opt_reduce_or), file:${SURELOG_DIR}/tests/FuncNoArgs/dut.sv, line:1:1, endln:31:10 |UINT:0 |vpiTypespec: \_int_typespec: @@ -1424,7 +1424,7 @@ design: (work@my_opt_reduce_or) |vpiParameter: \_parameter: (work@my_opt_reduce_or.A_WIDTH), line:3:15, endln:3:22 |vpiParent: - \_module: work@my_opt_reduce_or (work@my_opt_reduce_or), file:${SURELOG_DIR}/tests/FuncNoArgs/dut.sv, line:1:1, endln:31:10 + \_module_inst: work@my_opt_reduce_or (work@my_opt_reduce_or), file:${SURELOG_DIR}/tests/FuncNoArgs/dut.sv, line:1:1, endln:31:10 |UINT:1 |vpiTypespec: \_int_typespec: @@ -1435,7 +1435,7 @@ design: (work@my_opt_reduce_or) |vpiParameter: \_parameter: (work@my_opt_reduce_or._TECHMAP_CONSTMSK_A_), line:5:32, endln:5:52 |vpiParent: - \_module: work@my_opt_reduce_or (work@my_opt_reduce_or), file:${SURELOG_DIR}/tests/FuncNoArgs/dut.sv, line:1:1, endln:31:10 + \_module_inst: work@my_opt_reduce_or (work@my_opt_reduce_or), file:${SURELOG_DIR}/tests/FuncNoArgs/dut.sv, line:1:1, endln:31:10 |vpiTypespec: \_logic_typespec: , line:5:15, endln:5:31 |vpiParent: @@ -1485,7 +1485,7 @@ design: (work@my_opt_reduce_or) |vpiParamAssign: \_param_assign: , line:2:15, endln:2:27 |vpiParent: - \_module: work@my_opt_reduce_or (work@my_opt_reduce_or), file:${SURELOG_DIR}/tests/FuncNoArgs/dut.sv, line:1:1, endln:31:10 + \_module_inst: work@my_opt_reduce_or (work@my_opt_reduce_or), file:${SURELOG_DIR}/tests/FuncNoArgs/dut.sv, line:1:1, endln:31:10 |vpiRhs: \_constant: , line:2:26, endln:2:27 |vpiDecompile:0 @@ -1499,7 +1499,7 @@ design: (work@my_opt_reduce_or) |vpiParamAssign: \_param_assign: , line:3:15, endln:3:26 |vpiParent: - \_module: work@my_opt_reduce_or (work@my_opt_reduce_or), file:${SURELOG_DIR}/tests/FuncNoArgs/dut.sv, line:1:1, endln:31:10 + \_module_inst: work@my_opt_reduce_or (work@my_opt_reduce_or), file:${SURELOG_DIR}/tests/FuncNoArgs/dut.sv, line:1:1, endln:31:10 |vpiRhs: \_constant: , line:3:25, endln:3:26 |vpiDecompile:1 @@ -1513,7 +1513,7 @@ design: (work@my_opt_reduce_or) |vpiParamAssign: \_param_assign: , line:5:32, endln:5:62 |vpiParent: - \_module: work@my_opt_reduce_or (work@my_opt_reduce_or), file:${SURELOG_DIR}/tests/FuncNoArgs/dut.sv, line:1:1, endln:31:10 + \_module_inst: work@my_opt_reduce_or (work@my_opt_reduce_or), file:${SURELOG_DIR}/tests/FuncNoArgs/dut.sv, line:1:1, endln:31:10 |vpiRhs: \_constant: , line:5:55, endln:5:62 |vpiDecompile:6'd0 @@ -1526,7 +1526,7 @@ design: (work@my_opt_reduce_or) |vpiTaskFunc: \_function: (work@my_opt_reduce_or.count_nonconst_bits), line:7:5, endln:15:16 |vpiParent: - \_module: work@my_opt_reduce_or (work@my_opt_reduce_or), file:${SURELOG_DIR}/tests/FuncNoArgs/dut.sv, line:1:1, endln:31:10 + \_module_inst: work@my_opt_reduce_or (work@my_opt_reduce_or), file:${SURELOG_DIR}/tests/FuncNoArgs/dut.sv, line:1:1, endln:31:10 |vpiName:count_nonconst_bits |vpiFullName:work@my_opt_reduce_or.count_nonconst_bits |vpiVariables: @@ -1543,7 +1543,7 @@ design: (work@my_opt_reduce_or) |vpiReturn: \_integer_var: , line:7:14, endln:7:21 |vpiParent: - \_module: work@my_opt_reduce_or (work@my_opt_reduce_or), file:${SURELOG_DIR}/tests/FuncNoArgs/dut.sv, line:1:1, endln:31:10 + \_module_inst: work@my_opt_reduce_or (work@my_opt_reduce_or), file:${SURELOG_DIR}/tests/FuncNoArgs/dut.sv, line:1:1, endln:31:10 |vpiStmt: \_begin: (work@my_opt_reduce_or.count_nonconst_bits), line:9:9, endln:14:12 |vpiParent: @@ -1695,11 +1695,11 @@ design: (work@my_opt_reduce_or) |vpiActual: \_integer_var: , line:7:14, endln:7:21 |vpiInstance: - \_module: work@my_opt_reduce_or (work@my_opt_reduce_or), file:${SURELOG_DIR}/tests/FuncNoArgs/dut.sv, line:1:1, endln:31:10 + \_module_inst: work@my_opt_reduce_or (work@my_opt_reduce_or), file:${SURELOG_DIR}/tests/FuncNoArgs/dut.sv, line:1:1, endln:31:10 |vpiNet: \_logic_net: (work@my_opt_reduce_or.tmp), line:28:37, endln:28:40 |vpiParent: - \_module: work@my_opt_reduce_or (work@my_opt_reduce_or), file:${SURELOG_DIR}/tests/FuncNoArgs/dut.sv, line:1:1, endln:31:10 + \_module_inst: work@my_opt_reduce_or (work@my_opt_reduce_or), file:${SURELOG_DIR}/tests/FuncNoArgs/dut.sv, line:1:1, endln:31:10 |vpiTypespec: \_logic_typespec: , line:28:5, endln:28:36 |vpiRange: diff --git a/tests/FuncParam/FuncParam.log b/tests/FuncParam/FuncParam.log index afd0ac08e2..726c8590e8 100644 --- a/tests/FuncParam/FuncParam.log +++ b/tests/FuncParam/FuncParam.log @@ -53,7 +53,7 @@ int_var 4 io_decl 11 logic_typespec 2 logic_var 3 -module 9 +module_inst 9 operation 4 package 2 param_assign 3 @@ -82,7 +82,7 @@ int_var 4 io_decl 22 logic_typespec 2 logic_var 7 -module 9 +module_inst 9 operation 4 package 2 param_assign 3 @@ -580,20 +580,20 @@ design: (work@aes_prng) \_int_typespec: |vpiSigned:1 |uhdmallModules: -\_module: work@aes_prng (work@aes_prng), file:${SURELOG_DIR}/tests/FuncParam/dut.sv, line:10:1, endln:19:10 +\_module_inst: work@aes_prng (work@aes_prng), file:${SURELOG_DIR}/tests/FuncParam/dut.sv, line:10:1, endln:19:10 |vpiParent: \_design: (work@aes_prng) |vpiFullName:work@aes_prng |vpiDefName:work@aes_prng |uhdmallModules: -\_module: work@prim_lfsr (work@prim_lfsr), file:${SURELOG_DIR}/tests/FuncParam/dut.sv, line:1:1, endln:8:10 +\_module_inst: work@prim_lfsr (work@prim_lfsr), file:${SURELOG_DIR}/tests/FuncParam/dut.sv, line:1:1, endln:8:10 |vpiParent: \_design: (work@aes_prng) |vpiFullName:work@prim_lfsr |vpiParameter: \_parameter: (work@prim_lfsr.LfsrDw), line:2:27, endln:2:33 |vpiParent: - \_module: work@prim_lfsr (work@prim_lfsr), file:${SURELOG_DIR}/tests/FuncParam/dut.sv, line:1:1, endln:8:10 + \_module_inst: work@prim_lfsr (work@prim_lfsr), file:${SURELOG_DIR}/tests/FuncParam/dut.sv, line:1:1, endln:8:10 |UINT:12 |vpiTypespec: \_int_typespec: , line:2:14, endln:2:26 @@ -604,7 +604,7 @@ design: (work@aes_prng) |vpiParamAssign: \_param_assign: , line:2:27, endln:2:38 |vpiParent: - \_module: work@prim_lfsr (work@prim_lfsr), file:${SURELOG_DIR}/tests/FuncParam/dut.sv, line:1:1, endln:8:10 + \_module_inst: work@prim_lfsr (work@prim_lfsr), file:${SURELOG_DIR}/tests/FuncParam/dut.sv, line:1:1, endln:8:10 |vpiRhs: \_constant: , line:2:36, endln:2:38 |vpiDecompile:12 @@ -619,7 +619,7 @@ design: (work@aes_prng) |vpiTaskFunc: \_function: (work@prim_lfsr.compute), line:3:4, endln:6:15 |vpiParent: - \_module: work@prim_lfsr (work@prim_lfsr), file:${SURELOG_DIR}/tests/FuncParam/dut.sv, line:1:1, endln:8:10 + \_module_inst: work@prim_lfsr (work@prim_lfsr), file:${SURELOG_DIR}/tests/FuncParam/dut.sv, line:1:1, endln:8:10 |vpiName:compute |vpiFullName:work@prim_lfsr.compute |vpiVariables: @@ -700,7 +700,7 @@ design: (work@aes_prng) |UINT:0 |vpiConstType:9 |vpiParent: - \_module: work@prim_lfsr (work@prim_lfsr), file:${SURELOG_DIR}/tests/FuncParam/dut.sv, line:1:1, endln:8:10 + \_module_inst: work@prim_lfsr (work@prim_lfsr), file:${SURELOG_DIR}/tests/FuncParam/dut.sv, line:1:1, endln:8:10 |vpiStmt: \_begin: (work@prim_lfsr.compute) |vpiParent: @@ -721,23 +721,23 @@ design: (work@aes_prng) |vpiActual: \_logic_var: (work@prim_lfsr.compute.next_state), line:4:26, endln:4:36 |vpiInstance: - \_module: work@prim_lfsr (work@prim_lfsr), file:${SURELOG_DIR}/tests/FuncParam/dut.sv, line:1:1, endln:8:10 + \_module_inst: work@prim_lfsr (work@prim_lfsr), file:${SURELOG_DIR}/tests/FuncParam/dut.sv, line:1:1, endln:8:10 |uhdmtopModules: -\_module: work@aes_prng (work@aes_prng), file:${SURELOG_DIR}/tests/FuncParam/dut.sv, line:10:1, endln:19:10 +\_module_inst: work@aes_prng (work@aes_prng), file:${SURELOG_DIR}/tests/FuncParam/dut.sv, line:10:1, endln:19:10 |vpiName:work@aes_prng |vpiDefName:work@aes_prng |vpiTop:1 |vpiTopModule:1 - |vpiModule: - \_module: work@prim_lfsr (work@aes_prng.u_lfsr16), file:${SURELOG_DIR}/tests/FuncParam/dut.sv, line:11:4, endln:13:17 + |vpiModuleInst: + \_module_inst: work@prim_lfsr (work@aes_prng.u_lfsr16), file:${SURELOG_DIR}/tests/FuncParam/dut.sv, line:11:4, endln:13:17 |vpiParent: - \_module: work@aes_prng (work@aes_prng), file:${SURELOG_DIR}/tests/FuncParam/dut.sv, line:10:1, endln:19:10 + \_module_inst: work@aes_prng (work@aes_prng), file:${SURELOG_DIR}/tests/FuncParam/dut.sv, line:10:1, endln:19:10 |vpiName:u_lfsr16 |vpiFullName:work@aes_prng.u_lfsr16 |vpiParameter: \_parameter: (work@aes_prng.u_lfsr16.LfsrDw), line:2:27, endln:2:33 |vpiParent: - \_module: work@prim_lfsr (work@aes_prng.u_lfsr16), file:${SURELOG_DIR}/tests/FuncParam/dut.sv, line:11:4, endln:13:17 + \_module_inst: work@prim_lfsr (work@aes_prng.u_lfsr16), file:${SURELOG_DIR}/tests/FuncParam/dut.sv, line:11:4, endln:13:17 |UINT:12 |vpiTypespec: \_int_typespec: , line:2:14, endln:2:26 @@ -748,7 +748,7 @@ design: (work@aes_prng) |vpiParamAssign: \_param_assign: , line:2:27, endln:2:38 |vpiParent: - \_module: work@prim_lfsr (work@aes_prng.u_lfsr16), file:${SURELOG_DIR}/tests/FuncParam/dut.sv, line:11:4, endln:13:17 + \_module_inst: work@prim_lfsr (work@aes_prng.u_lfsr16), file:${SURELOG_DIR}/tests/FuncParam/dut.sv, line:11:4, endln:13:17 |vpiOverriden:1 |vpiRhs: \_constant: , line:2:36, endln:2:38 @@ -766,7 +766,7 @@ design: (work@aes_prng) |vpiTaskFunc: \_function: (work@aes_prng.u_lfsr16.compute), line:3:4, endln:6:15 |vpiParent: - \_module: work@prim_lfsr (work@aes_prng.u_lfsr16), file:${SURELOG_DIR}/tests/FuncParam/dut.sv, line:11:4, endln:13:17 + \_module_inst: work@prim_lfsr (work@aes_prng.u_lfsr16), file:${SURELOG_DIR}/tests/FuncParam/dut.sv, line:11:4, endln:13:17 |vpiName:compute |vpiFullName:work@aes_prng.u_lfsr16.compute |vpiVariables: @@ -782,7 +782,7 @@ design: (work@aes_prng) |vpiReturn: \_logic_var: , line:3:23, endln:3:41 |vpiParent: - \_module: work@prim_lfsr (work@aes_prng.u_lfsr16), file:${SURELOG_DIR}/tests/FuncParam/dut.sv, line:11:4, endln:13:17 + \_module_inst: work@prim_lfsr (work@aes_prng.u_lfsr16), file:${SURELOG_DIR}/tests/FuncParam/dut.sv, line:11:4, endln:13:17 |vpiStmt: \_begin: (work@aes_prng.u_lfsr16.compute) |vpiParent: @@ -809,19 +809,19 @@ design: (work@aes_prng) |vpiActual: \_logic_var: (work@prim_lfsr.compute.next_state), line:4:26, endln:4:36 |vpiInstance: - \_module: work@prim_lfsr (work@aes_prng.u_lfsr16), file:${SURELOG_DIR}/tests/FuncParam/dut.sv, line:11:4, endln:13:17 + \_module_inst: work@prim_lfsr (work@aes_prng.u_lfsr16), file:${SURELOG_DIR}/tests/FuncParam/dut.sv, line:11:4, endln:13:17 |vpiInstance: - \_module: work@aes_prng (work@aes_prng), file:${SURELOG_DIR}/tests/FuncParam/dut.sv, line:10:1, endln:19:10 - |vpiModule: - \_module: work@prim_lfsr (work@aes_prng.u_lfsr18), file:${SURELOG_DIR}/tests/FuncParam/dut.sv, line:15:3, endln:17:17 + \_module_inst: work@aes_prng (work@aes_prng), file:${SURELOG_DIR}/tests/FuncParam/dut.sv, line:10:1, endln:19:10 + |vpiModuleInst: + \_module_inst: work@prim_lfsr (work@aes_prng.u_lfsr18), file:${SURELOG_DIR}/tests/FuncParam/dut.sv, line:15:3, endln:17:17 |vpiParent: - \_module: work@aes_prng (work@aes_prng), file:${SURELOG_DIR}/tests/FuncParam/dut.sv, line:10:1, endln:19:10 + \_module_inst: work@aes_prng (work@aes_prng), file:${SURELOG_DIR}/tests/FuncParam/dut.sv, line:10:1, endln:19:10 |vpiName:u_lfsr18 |vpiFullName:work@aes_prng.u_lfsr18 |vpiParameter: \_parameter: (work@aes_prng.u_lfsr18.LfsrDw), line:2:27, endln:2:33 |vpiParent: - \_module: work@prim_lfsr (work@aes_prng.u_lfsr18), file:${SURELOG_DIR}/tests/FuncParam/dut.sv, line:15:3, endln:17:17 + \_module_inst: work@prim_lfsr (work@aes_prng.u_lfsr18), file:${SURELOG_DIR}/tests/FuncParam/dut.sv, line:15:3, endln:17:17 |UINT:12 |vpiTypespec: \_int_typespec: , line:2:14, endln:2:26 @@ -832,7 +832,7 @@ design: (work@aes_prng) |vpiParamAssign: \_param_assign: , line:2:27, endln:2:38 |vpiParent: - \_module: work@prim_lfsr (work@aes_prng.u_lfsr18), file:${SURELOG_DIR}/tests/FuncParam/dut.sv, line:15:3, endln:17:17 + \_module_inst: work@prim_lfsr (work@aes_prng.u_lfsr18), file:${SURELOG_DIR}/tests/FuncParam/dut.sv, line:15:3, endln:17:17 |vpiOverriden:1 |vpiRhs: \_constant: , line:2:36, endln:2:38 @@ -850,7 +850,7 @@ design: (work@aes_prng) |vpiTaskFunc: \_function: (work@aes_prng.u_lfsr18.compute), line:3:4, endln:6:15 |vpiParent: - \_module: work@prim_lfsr (work@aes_prng.u_lfsr18), file:${SURELOG_DIR}/tests/FuncParam/dut.sv, line:15:3, endln:17:17 + \_module_inst: work@prim_lfsr (work@aes_prng.u_lfsr18), file:${SURELOG_DIR}/tests/FuncParam/dut.sv, line:15:3, endln:17:17 |vpiName:compute |vpiFullName:work@aes_prng.u_lfsr18.compute |vpiVariables: @@ -866,7 +866,7 @@ design: (work@aes_prng) |vpiReturn: \_logic_var: , line:3:23, endln:3:41 |vpiParent: - \_module: work@prim_lfsr (work@aes_prng.u_lfsr18), file:${SURELOG_DIR}/tests/FuncParam/dut.sv, line:15:3, endln:17:17 + \_module_inst: work@prim_lfsr (work@aes_prng.u_lfsr18), file:${SURELOG_DIR}/tests/FuncParam/dut.sv, line:15:3, endln:17:17 |vpiStmt: \_begin: (work@aes_prng.u_lfsr18.compute) |vpiParent: @@ -893,9 +893,9 @@ design: (work@aes_prng) |vpiActual: \_logic_var: (work@prim_lfsr.compute.next_state), line:4:26, endln:4:36 |vpiInstance: - \_module: work@prim_lfsr (work@aes_prng.u_lfsr18), file:${SURELOG_DIR}/tests/FuncParam/dut.sv, line:15:3, endln:17:17 + \_module_inst: work@prim_lfsr (work@aes_prng.u_lfsr18), file:${SURELOG_DIR}/tests/FuncParam/dut.sv, line:15:3, endln:17:17 |vpiInstance: - \_module: work@aes_prng (work@aes_prng), file:${SURELOG_DIR}/tests/FuncParam/dut.sv, line:10:1, endln:19:10 + \_module_inst: work@aes_prng (work@aes_prng), file:${SURELOG_DIR}/tests/FuncParam/dut.sv, line:10:1, endln:19:10 =================== [ FATAL] : 0 [ SYNTAX] : 0 diff --git a/tests/FuncParam2/FuncParam2.log b/tests/FuncParam2/FuncParam2.log index 5c86788666..3c20fa580e 100644 --- a/tests/FuncParam2/FuncParam2.log +++ b/tests/FuncParam2/FuncParam2.log @@ -46,7 +46,7 @@ int_typespec 9 int_var 4 io_decl 11 logic_var 2 -module 2 +module_inst 2 operation 2 package 2 param_assign 2 @@ -69,7 +69,7 @@ int_typespec 9 int_var 4 io_decl 22 logic_var 2 -module 2 +module_inst 2 operation 4 package 2 param_assign 4 @@ -564,7 +564,7 @@ design: (work@top) \_int_typespec: |vpiSigned:1 |uhdmallModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/FuncParam2/dut.sv, line:1:1, endln:6:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/FuncParam2/dut.sv, line:1:1, endln:6:10 |vpiParent: \_design: (work@top) |vpiFullName:work@top @@ -572,7 +572,7 @@ design: (work@top) |vpiTaskFunc: \_function: (work@top.func), line:2:1, endln:5:12 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/FuncParam2/dut.sv, line:1:1, endln:6:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/FuncParam2/dut.sv, line:1:1, endln:6:10 |vpiName:func |vpiFullName:work@top.func |vpiParameter: @@ -632,18 +632,18 @@ design: (work@top) |vpiReturn: \_logic_var: |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/FuncParam2/dut.sv, line:1:1, endln:6:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/FuncParam2/dut.sv, line:1:1, endln:6:10 |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/FuncParam2/dut.sv, line:1:1, endln:6:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/FuncParam2/dut.sv, line:1:1, endln:6:10 |uhdmtopModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/FuncParam2/dut.sv, line:1:1, endln:6:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/FuncParam2/dut.sv, line:1:1, endln:6:10 |vpiName:work@top |vpiDefName:work@top |vpiTop:1 |vpiTaskFunc: \_function: (work@top.func), line:2:1, endln:5:12 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/FuncParam2/dut.sv, line:1:1, endln:6:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/FuncParam2/dut.sv, line:1:1, endln:6:10 |vpiName:func |vpiFullName:work@top.func |vpiParameter: @@ -702,9 +702,9 @@ design: (work@top) |vpiReturn: \_logic_var: |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/FuncParam2/dut.sv, line:1:1, endln:6:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/FuncParam2/dut.sv, line:1:1, endln:6:10 |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/FuncParam2/dut.sv, line:1:1, endln:6:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/FuncParam2/dut.sv, line:1:1, endln:6:10 |vpiTopModule:1 =================== [ FATAL] : 0 diff --git a/tests/FuncReturnRange/FuncReturnRange.log b/tests/FuncReturnRange/FuncReturnRange.log index c839071f3a..8740925db2 100644 --- a/tests/FuncReturnRange/FuncReturnRange.log +++ b/tests/FuncReturnRange/FuncReturnRange.log @@ -305,7 +305,7 @@ io_decl 1 logic_net 10 logic_typespec 12 logic_var 2 -module 9 +module_inst 9 operation 8 param_assign 7 parameter 7 @@ -327,7 +327,7 @@ io_decl 2 logic_net 10 logic_typespec 12 logic_var 2 -module 9 +module_inst 9 operation 9 param_assign 7 parameter 7 @@ -348,14 +348,14 @@ design: (work@func_width_scope_top) |vpiElaborated:1 |vpiName:work@func_width_scope_top |uhdmallModules: -\_module: work@func_width_scope_top (work@func_width_scope_top), file:${SURELOG_DIR}/tests/FuncReturnRange/dut.sv, line:1:1, endln:18:10 +\_module_inst: work@func_width_scope_top (work@func_width_scope_top), file:${SURELOG_DIR}/tests/FuncReturnRange/dut.sv, line:1:1, endln:18:10 |vpiParent: \_design: (work@func_width_scope_top) |vpiFullName:work@func_width_scope_top |vpiParameter: \_parameter: (work@func_width_scope_top.WIDTH_A), line:4:16, endln:4:23 |vpiParent: - \_module: work@func_width_scope_top (work@func_width_scope_top), file:${SURELOG_DIR}/tests/FuncReturnRange/dut.sv, line:1:1, endln:18:10 + \_module_inst: work@func_width_scope_top (work@func_width_scope_top), file:${SURELOG_DIR}/tests/FuncReturnRange/dut.sv, line:1:1, endln:18:10 |UINT:5 |vpiTypespec: \_int_typespec: @@ -365,7 +365,7 @@ design: (work@func_width_scope_top) |vpiParamAssign: \_param_assign: , line:4:16, endln:4:27 |vpiParent: - \_module: work@func_width_scope_top (work@func_width_scope_top), file:${SURELOG_DIR}/tests/FuncReturnRange/dut.sv, line:1:1, endln:18:10 + \_module_inst: work@func_width_scope_top (work@func_width_scope_top), file:${SURELOG_DIR}/tests/FuncReturnRange/dut.sv, line:1:1, endln:18:10 |vpiRhs: \_constant: , line:4:26, endln:4:27 |vpiDecompile:5 @@ -380,7 +380,7 @@ design: (work@func_width_scope_top) |vpiTaskFunc: \_function: (work@func_width_scope_top.func1), line:5:5, endln:8:16 |vpiParent: - \_module: work@func_width_scope_top (work@func_width_scope_top), file:${SURELOG_DIR}/tests/FuncReturnRange/dut.sv, line:1:1, endln:18:10 + \_module_inst: work@func_width_scope_top (work@func_width_scope_top), file:${SURELOG_DIR}/tests/FuncReturnRange/dut.sv, line:1:1, endln:18:10 |vpiName:func1 |vpiFullName:work@func_width_scope_top.func1 |vpiVisibility:1 @@ -420,7 +420,7 @@ design: (work@func_width_scope_top) |UINT:0 |vpiConstType:9 |vpiParent: - \_module: work@func_width_scope_top (work@func_width_scope_top), file:${SURELOG_DIR}/tests/FuncReturnRange/dut.sv, line:1:1, endln:18:10 + \_module_inst: work@func_width_scope_top (work@func_width_scope_top), file:${SURELOG_DIR}/tests/FuncReturnRange/dut.sv, line:1:1, endln:18:10 |vpiIODecl: \_io_decl: (s), line:6:33, endln:6:34 |vpiParent: @@ -477,46 +477,46 @@ design: (work@func_width_scope_top) |vpiActual: \_logic_var: (func1), line:5:24, endln:5:37 |vpiInstance: - \_module: work@func_width_scope_top (work@func_width_scope_top), file:${SURELOG_DIR}/tests/FuncReturnRange/dut.sv, line:1:1, endln:18:10 + \_module_inst: work@func_width_scope_top (work@func_width_scope_top), file:${SURELOG_DIR}/tests/FuncReturnRange/dut.sv, line:1:1, endln:18:10 |vpiNet: \_logic_net: (work@func_width_scope_top.xc), line:9:25, endln:9:27 |vpiParent: - \_module: work@func_width_scope_top (work@func_width_scope_top), file:${SURELOG_DIR}/tests/FuncReturnRange/dut.sv, line:1:1, endln:18:10 + \_module_inst: work@func_width_scope_top (work@func_width_scope_top), file:${SURELOG_DIR}/tests/FuncReturnRange/dut.sv, line:1:1, endln:18:10 |vpiName:xc |vpiFullName:work@func_width_scope_top.xc |vpiNetType:1 |vpiNet: \_logic_net: (work@func_width_scope_top.xn), line:13:24, endln:13:26 |vpiParent: - \_module: work@func_width_scope_top (work@func_width_scope_top), file:${SURELOG_DIR}/tests/FuncReturnRange/dut.sv, line:1:1, endln:18:10 + \_module_inst: work@func_width_scope_top (work@func_width_scope_top), file:${SURELOG_DIR}/tests/FuncReturnRange/dut.sv, line:1:1, endln:18:10 |vpiName:xn |vpiFullName:work@func_width_scope_top.xn |vpiNetType:1 |vpiNet: \_logic_net: (work@func_width_scope_top.inp), line:1:29, endln:1:32 |vpiParent: - \_module: work@func_width_scope_top (work@func_width_scope_top), file:${SURELOG_DIR}/tests/FuncReturnRange/dut.sv, line:1:1, endln:18:10 + \_module_inst: work@func_width_scope_top (work@func_width_scope_top), file:${SURELOG_DIR}/tests/FuncReturnRange/dut.sv, line:1:1, endln:18:10 |vpiName:inp |vpiFullName:work@func_width_scope_top.inp |vpiNetType:1 |vpiNet: \_logic_net: (work@func_width_scope_top.out1), line:1:34, endln:1:38 |vpiParent: - \_module: work@func_width_scope_top (work@func_width_scope_top), file:${SURELOG_DIR}/tests/FuncReturnRange/dut.sv, line:1:1, endln:18:10 + \_module_inst: work@func_width_scope_top (work@func_width_scope_top), file:${SURELOG_DIR}/tests/FuncReturnRange/dut.sv, line:1:1, endln:18:10 |vpiName:out1 |vpiFullName:work@func_width_scope_top.out1 |vpiNetType:1 |vpiNet: \_logic_net: (work@func_width_scope_top.out2), line:1:40, endln:1:44 |vpiParent: - \_module: work@func_width_scope_top (work@func_width_scope_top), file:${SURELOG_DIR}/tests/FuncReturnRange/dut.sv, line:1:1, endln:18:10 + \_module_inst: work@func_width_scope_top (work@func_width_scope_top), file:${SURELOG_DIR}/tests/FuncReturnRange/dut.sv, line:1:1, endln:18:10 |vpiName:out2 |vpiFullName:work@func_width_scope_top.out2 |vpiNetType:1 |vpiPort: \_port: (inp), line:1:29, endln:1:32 |vpiParent: - \_module: work@func_width_scope_top (work@func_width_scope_top), file:${SURELOG_DIR}/tests/FuncReturnRange/dut.sv, line:1:1, endln:18:10 + \_module_inst: work@func_width_scope_top (work@func_width_scope_top), file:${SURELOG_DIR}/tests/FuncReturnRange/dut.sv, line:1:1, endln:18:10 |vpiName:inp |vpiDirection:1 |vpiLowConn: @@ -528,7 +528,7 @@ design: (work@func_width_scope_top) |vpiPort: \_port: (out1), line:1:34, endln:1:38 |vpiParent: - \_module: work@func_width_scope_top (work@func_width_scope_top), file:${SURELOG_DIR}/tests/FuncReturnRange/dut.sv, line:1:1, endln:18:10 + \_module_inst: work@func_width_scope_top (work@func_width_scope_top), file:${SURELOG_DIR}/tests/FuncReturnRange/dut.sv, line:1:1, endln:18:10 |vpiName:out1 |vpiDirection:2 |vpiLowConn: @@ -558,7 +558,7 @@ design: (work@func_width_scope_top) |vpiPort: \_port: (out2), line:1:40, endln:1:44 |vpiParent: - \_module: work@func_width_scope_top (work@func_width_scope_top), file:${SURELOG_DIR}/tests/FuncReturnRange/dut.sv, line:1:1, endln:18:10 + \_module_inst: work@func_width_scope_top (work@func_width_scope_top), file:${SURELOG_DIR}/tests/FuncReturnRange/dut.sv, line:1:1, endln:18:10 |vpiName:out2 |vpiDirection:2 |vpiLowConn: @@ -588,7 +588,7 @@ design: (work@func_width_scope_top) |vpiContAssign: \_cont_assign: , line:10:12, endln:10:22 |vpiParent: - \_module: work@func_width_scope_top (work@func_width_scope_top), file:${SURELOG_DIR}/tests/FuncReturnRange/dut.sv, line:1:1, endln:18:10 + \_module_inst: work@func_width_scope_top (work@func_width_scope_top), file:${SURELOG_DIR}/tests/FuncReturnRange/dut.sv, line:1:1, endln:18:10 |vpiRhs: \_constant: , line:10:17, endln:10:22 |vpiParent: @@ -611,7 +611,7 @@ design: (work@func_width_scope_top) |vpiContAssign: \_cont_assign: , line:14:12, endln:14:27 |vpiParent: - \_module: work@func_width_scope_top (work@func_width_scope_top), file:${SURELOG_DIR}/tests/FuncReturnRange/dut.sv, line:1:1, endln:18:10 + \_module_inst: work@func_width_scope_top (work@func_width_scope_top), file:${SURELOG_DIR}/tests/FuncReturnRange/dut.sv, line:1:1, endln:18:10 |vpiRhs: \_func_call: (func1), line:14:17, endln:14:27 |vpiParent: @@ -640,7 +640,7 @@ design: (work@func_width_scope_top) |vpiContAssign: \_cont_assign: , line:15:12, endln:15:21 |vpiParent: - \_module: work@func_width_scope_top (work@func_width_scope_top), file:${SURELOG_DIR}/tests/FuncReturnRange/dut.sv, line:1:1, endln:18:10 + \_module_inst: work@func_width_scope_top (work@func_width_scope_top), file:${SURELOG_DIR}/tests/FuncReturnRange/dut.sv, line:1:1, endln:18:10 |vpiRhs: \_ref_obj: (work@func_width_scope_top.xn), line:15:19, endln:15:21 |vpiParent: @@ -660,7 +660,7 @@ design: (work@func_width_scope_top) |vpiContAssign: \_cont_assign: , line:16:12, endln:16:21 |vpiParent: - \_module: work@func_width_scope_top (work@func_width_scope_top), file:${SURELOG_DIR}/tests/FuncReturnRange/dut.sv, line:1:1, endln:18:10 + \_module_inst: work@func_width_scope_top (work@func_width_scope_top), file:${SURELOG_DIR}/tests/FuncReturnRange/dut.sv, line:1:1, endln:18:10 |vpiRhs: \_ref_obj: (work@func_width_scope_top.xc), line:16:19, endln:16:21 |vpiParent: @@ -678,12 +678,12 @@ design: (work@func_width_scope_top) |vpiActual: \_logic_net: (work@func_width_scope_top.out2), line:1:40, endln:1:44 |uhdmtopModules: -\_module: work@func_width_scope_top (work@func_width_scope_top), file:${SURELOG_DIR}/tests/FuncReturnRange/dut.sv, line:1:1, endln:18:10 +\_module_inst: work@func_width_scope_top (work@func_width_scope_top), file:${SURELOG_DIR}/tests/FuncReturnRange/dut.sv, line:1:1, endln:18:10 |vpiName:work@func_width_scope_top |vpiParameter: \_parameter: (work@func_width_scope_top.WIDTH_A), line:4:16, endln:4:23 |vpiParent: - \_module: work@func_width_scope_top (work@func_width_scope_top), file:${SURELOG_DIR}/tests/FuncReturnRange/dut.sv, line:1:1, endln:18:10 + \_module_inst: work@func_width_scope_top (work@func_width_scope_top), file:${SURELOG_DIR}/tests/FuncReturnRange/dut.sv, line:1:1, endln:18:10 |UINT:5 |vpiTypespec: \_int_typespec: @@ -695,7 +695,7 @@ design: (work@func_width_scope_top) |vpiParamAssign: \_param_assign: , line:4:16, endln:4:27 |vpiParent: - \_module: work@func_width_scope_top (work@func_width_scope_top), file:${SURELOG_DIR}/tests/FuncReturnRange/dut.sv, line:1:1, endln:18:10 + \_module_inst: work@func_width_scope_top (work@func_width_scope_top), file:${SURELOG_DIR}/tests/FuncReturnRange/dut.sv, line:1:1, endln:18:10 |vpiRhs: \_constant: , line:4:26, endln:4:27 |vpiDecompile:5 @@ -711,7 +711,7 @@ design: (work@func_width_scope_top) |vpiTaskFunc: \_function: (work@func_width_scope_top.func1), line:5:5, endln:8:16 |vpiParent: - \_module: work@func_width_scope_top (work@func_width_scope_top), file:${SURELOG_DIR}/tests/FuncReturnRange/dut.sv, line:1:1, endln:18:10 + \_module_inst: work@func_width_scope_top (work@func_width_scope_top), file:${SURELOG_DIR}/tests/FuncReturnRange/dut.sv, line:1:1, endln:18:10 |vpiName:func1 |vpiFullName:work@func_width_scope_top.func1 |vpiVisibility:1 @@ -719,7 +719,7 @@ design: (work@func_width_scope_top) |vpiReturn: \_logic_var: , line:5:24, endln:5:37 |vpiParent: - \_module: work@func_width_scope_top (work@func_width_scope_top), file:${SURELOG_DIR}/tests/FuncReturnRange/dut.sv, line:1:1, endln:18:10 + \_module_inst: work@func_width_scope_top (work@func_width_scope_top), file:${SURELOG_DIR}/tests/FuncReturnRange/dut.sv, line:1:1, endln:18:10 |vpiIODecl: \_io_decl: (s), line:6:33, endln:6:34 |vpiParent: @@ -756,11 +756,11 @@ design: (work@func_width_scope_top) |vpiActual: \_logic_var: , line:5:24, endln:5:37 |vpiInstance: - \_module: work@func_width_scope_top (work@func_width_scope_top), file:${SURELOG_DIR}/tests/FuncReturnRange/dut.sv, line:1:1, endln:18:10 + \_module_inst: work@func_width_scope_top (work@func_width_scope_top), file:${SURELOG_DIR}/tests/FuncReturnRange/dut.sv, line:1:1, endln:18:10 |vpiNet: \_logic_net: (work@func_width_scope_top.xc), line:9:25, endln:9:27 |vpiParent: - \_module: work@func_width_scope_top (work@func_width_scope_top), file:${SURELOG_DIR}/tests/FuncReturnRange/dut.sv, line:1:1, endln:18:10 + \_module_inst: work@func_width_scope_top (work@func_width_scope_top), file:${SURELOG_DIR}/tests/FuncReturnRange/dut.sv, line:1:1, endln:18:10 |vpiTypespec: \_logic_typespec: , line:9:5, endln:9:24 |vpiRange: @@ -787,7 +787,7 @@ design: (work@func_width_scope_top) |vpiNet: \_logic_net: (work@func_width_scope_top.xn), line:13:24, endln:13:26 |vpiParent: - \_module: work@func_width_scope_top (work@func_width_scope_top), file:${SURELOG_DIR}/tests/FuncReturnRange/dut.sv, line:1:1, endln:18:10 + \_module_inst: work@func_width_scope_top (work@func_width_scope_top), file:${SURELOG_DIR}/tests/FuncReturnRange/dut.sv, line:1:1, endln:18:10 |vpiTypespec: \_logic_typespec: , line:13:5, endln:13:23 |vpiRange: @@ -814,7 +814,7 @@ design: (work@func_width_scope_top) |vpiNet: \_logic_net: (work@func_width_scope_top.inp), line:1:29, endln:1:32 |vpiParent: - \_module: work@func_width_scope_top (work@func_width_scope_top), file:${SURELOG_DIR}/tests/FuncReturnRange/dut.sv, line:1:1, endln:18:10 + \_module_inst: work@func_width_scope_top (work@func_width_scope_top), file:${SURELOG_DIR}/tests/FuncReturnRange/dut.sv, line:1:1, endln:18:10 |vpiTypespec: \_logic_typespec: , line:2:11, endln:2:15 |vpiName:inp @@ -823,7 +823,7 @@ design: (work@func_width_scope_top) |vpiNet: \_logic_net: (work@func_width_scope_top.out1), line:1:34, endln:1:38 |vpiParent: - \_module: work@func_width_scope_top (work@func_width_scope_top), file:${SURELOG_DIR}/tests/FuncReturnRange/dut.sv, line:1:1, endln:18:10 + \_module_inst: work@func_width_scope_top (work@func_width_scope_top), file:${SURELOG_DIR}/tests/FuncReturnRange/dut.sv, line:1:1, endln:18:10 |vpiTypespec: \_logic_typespec: , line:12:12, endln:12:25 |vpiRange: @@ -850,7 +850,7 @@ design: (work@func_width_scope_top) |vpiNet: \_logic_net: (work@func_width_scope_top.out2), line:1:40, endln:1:44 |vpiParent: - \_module: work@func_width_scope_top (work@func_width_scope_top), file:${SURELOG_DIR}/tests/FuncReturnRange/dut.sv, line:1:1, endln:18:10 + \_module_inst: work@func_width_scope_top (work@func_width_scope_top), file:${SURELOG_DIR}/tests/FuncReturnRange/dut.sv, line:1:1, endln:18:10 |vpiTypespec: \_logic_typespec: , line:12:12, endln:12:25 |vpiName:out2 @@ -860,7 +860,7 @@ design: (work@func_width_scope_top) |vpiPort: \_port: (inp), line:1:29, endln:1:32 |vpiParent: - \_module: work@func_width_scope_top (work@func_width_scope_top), file:${SURELOG_DIR}/tests/FuncReturnRange/dut.sv, line:1:1, endln:18:10 + \_module_inst: work@func_width_scope_top (work@func_width_scope_top), file:${SURELOG_DIR}/tests/FuncReturnRange/dut.sv, line:1:1, endln:18:10 |vpiName:inp |vpiDirection:1 |vpiLowConn: @@ -874,11 +874,11 @@ design: (work@func_width_scope_top) |vpiTypedef: \_logic_typespec: , line:2:11, endln:2:15 |vpiInstance: - \_module: work@func_width_scope_top (work@func_width_scope_top), file:${SURELOG_DIR}/tests/FuncReturnRange/dut.sv, line:1:1, endln:18:10 + \_module_inst: work@func_width_scope_top (work@func_width_scope_top), file:${SURELOG_DIR}/tests/FuncReturnRange/dut.sv, line:1:1, endln:18:10 |vpiPort: \_port: (out1), line:1:34, endln:1:38 |vpiParent: - \_module: work@func_width_scope_top (work@func_width_scope_top), file:${SURELOG_DIR}/tests/FuncReturnRange/dut.sv, line:1:1, endln:18:10 + \_module_inst: work@func_width_scope_top (work@func_width_scope_top), file:${SURELOG_DIR}/tests/FuncReturnRange/dut.sv, line:1:1, endln:18:10 |vpiName:out1 |vpiDirection:2 |vpiLowConn: @@ -912,11 +912,11 @@ design: (work@func_width_scope_top) |UINT:0 |vpiConstType:9 |vpiInstance: - \_module: work@func_width_scope_top (work@func_width_scope_top), file:${SURELOG_DIR}/tests/FuncReturnRange/dut.sv, line:1:1, endln:18:10 + \_module_inst: work@func_width_scope_top (work@func_width_scope_top), file:${SURELOG_DIR}/tests/FuncReturnRange/dut.sv, line:1:1, endln:18:10 |vpiPort: \_port: (out2), line:1:40, endln:1:44 |vpiParent: - \_module: work@func_width_scope_top (work@func_width_scope_top), file:${SURELOG_DIR}/tests/FuncReturnRange/dut.sv, line:1:1, endln:18:10 + \_module_inst: work@func_width_scope_top (work@func_width_scope_top), file:${SURELOG_DIR}/tests/FuncReturnRange/dut.sv, line:1:1, endln:18:10 |vpiName:out2 |vpiDirection:2 |vpiLowConn: @@ -930,11 +930,11 @@ design: (work@func_width_scope_top) |vpiTypedef: \_logic_typespec: , line:12:12, endln:12:25 |vpiInstance: - \_module: work@func_width_scope_top (work@func_width_scope_top), file:${SURELOG_DIR}/tests/FuncReturnRange/dut.sv, line:1:1, endln:18:10 + \_module_inst: work@func_width_scope_top (work@func_width_scope_top), file:${SURELOG_DIR}/tests/FuncReturnRange/dut.sv, line:1:1, endln:18:10 |vpiContAssign: \_cont_assign: , line:10:12, endln:10:22 |vpiParent: - \_module: work@func_width_scope_top (work@func_width_scope_top), file:${SURELOG_DIR}/tests/FuncReturnRange/dut.sv, line:1:1, endln:18:10 + \_module_inst: work@func_width_scope_top (work@func_width_scope_top), file:${SURELOG_DIR}/tests/FuncReturnRange/dut.sv, line:1:1, endln:18:10 |vpiRhs: \_constant: , line:10:17, endln:10:22 |vpiParent: @@ -959,7 +959,7 @@ design: (work@func_width_scope_top) |vpiContAssign: \_cont_assign: , line:14:12, endln:14:27 |vpiParent: - \_module: work@func_width_scope_top (work@func_width_scope_top), file:${SURELOG_DIR}/tests/FuncReturnRange/dut.sv, line:1:1, endln:18:10 + \_module_inst: work@func_width_scope_top (work@func_width_scope_top), file:${SURELOG_DIR}/tests/FuncReturnRange/dut.sv, line:1:1, endln:18:10 |vpiRhs: \_func_call: (func1), line:14:17, endln:14:27 |vpiParent: @@ -988,7 +988,7 @@ design: (work@func_width_scope_top) |vpiContAssign: \_cont_assign: , line:15:12, endln:15:21 |vpiParent: - \_module: work@func_width_scope_top (work@func_width_scope_top), file:${SURELOG_DIR}/tests/FuncReturnRange/dut.sv, line:1:1, endln:18:10 + \_module_inst: work@func_width_scope_top (work@func_width_scope_top), file:${SURELOG_DIR}/tests/FuncReturnRange/dut.sv, line:1:1, endln:18:10 |vpiRhs: \_ref_obj: (work@func_width_scope_top.xn), line:15:19, endln:15:21 |vpiParent: @@ -1008,7 +1008,7 @@ design: (work@func_width_scope_top) |vpiContAssign: \_cont_assign: , line:16:12, endln:16:21 |vpiParent: - \_module: work@func_width_scope_top (work@func_width_scope_top), file:${SURELOG_DIR}/tests/FuncReturnRange/dut.sv, line:1:1, endln:18:10 + \_module_inst: work@func_width_scope_top (work@func_width_scope_top), file:${SURELOG_DIR}/tests/FuncReturnRange/dut.sv, line:1:1, endln:18:10 |vpiRhs: \_ref_obj: (work@func_width_scope_top.xc), line:16:19, endln:16:21 |vpiParent: diff --git a/tests/FuncStatic/FuncStatic.log b/tests/FuncStatic/FuncStatic.log index 1c904c50ae..29e4662c2a 100644 --- a/tests/FuncStatic/FuncStatic.log +++ b/tests/FuncStatic/FuncStatic.log @@ -263,7 +263,7 @@ int_var 2 integer_typespec 4 integer_var 2 io_decl 2 -module 7 +module_inst 7 operation 2 param_assign 24 parameter 24 @@ -285,7 +285,7 @@ int_var 8 integer_typespec 4 integer_var 2 io_decl 4 -module 7 +module_inst 7 operation 4 param_assign 24 parameter 24 @@ -305,42 +305,42 @@ design: (work@test) |vpiElaborated:1 |vpiName:work@test |uhdmallModules: -\_module: work@test (work@test), file:${SURELOG_DIR}/tests/FuncStatic/dut.sv, line:1:1, endln:20:10 +\_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/FuncStatic/dut.sv, line:1:1, endln:20:10 |vpiParent: \_design: (work@test) |vpiFullName:work@test |vpiParameter: \_parameter: (work@test.value1), line:15:12, endln:15:18 |vpiParent: - \_module: work@test (work@test), file:${SURELOG_DIR}/tests/FuncStatic/dut.sv, line:1:1, endln:20:10 + \_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/FuncStatic/dut.sv, line:1:1, endln:20:10 |vpiLocalParam:1 |vpiName:value1 |vpiFullName:work@test.value1 |vpiParameter: \_parameter: (work@test.value2), line:16:12, endln:16:18 |vpiParent: - \_module: work@test (work@test), file:${SURELOG_DIR}/tests/FuncStatic/dut.sv, line:1:1, endln:20:10 + \_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/FuncStatic/dut.sv, line:1:1, endln:20:10 |vpiLocalParam:1 |vpiName:value2 |vpiFullName:work@test.value2 |vpiParameter: \_parameter: (work@test.value3), line:17:12, endln:17:18 |vpiParent: - \_module: work@test (work@test), file:${SURELOG_DIR}/tests/FuncStatic/dut.sv, line:1:1, endln:20:10 + \_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/FuncStatic/dut.sv, line:1:1, endln:20:10 |vpiLocalParam:1 |vpiName:value3 |vpiFullName:work@test.value3 |vpiParameter: \_parameter: (work@test.value4), line:18:12, endln:18:18 |vpiParent: - \_module: work@test (work@test), file:${SURELOG_DIR}/tests/FuncStatic/dut.sv, line:1:1, endln:20:10 + \_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/FuncStatic/dut.sv, line:1:1, endln:20:10 |vpiLocalParam:1 |vpiName:value4 |vpiFullName:work@test.value4 |vpiParamAssign: \_param_assign: , line:15:12, endln:15:35 |vpiParent: - \_module: work@test (work@test), file:${SURELOG_DIR}/tests/FuncStatic/dut.sv, line:1:1, endln:20:10 + \_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/FuncStatic/dut.sv, line:1:1, endln:20:10 |vpiRhs: \_func_call: (accumulate1), line:15:21, endln:15:32 |vpiArgument: @@ -359,7 +359,7 @@ design: (work@test) |vpiParamAssign: \_param_assign: , line:16:12, endln:16:35 |vpiParent: - \_module: work@test (work@test), file:${SURELOG_DIR}/tests/FuncStatic/dut.sv, line:1:1, endln:20:10 + \_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/FuncStatic/dut.sv, line:1:1, endln:20:10 |vpiRhs: \_func_call: (accumulate1), line:16:21, endln:16:32 |vpiArgument: @@ -378,7 +378,7 @@ design: (work@test) |vpiParamAssign: \_param_assign: , line:17:12, endln:17:35 |vpiParent: - \_module: work@test (work@test), file:${SURELOG_DIR}/tests/FuncStatic/dut.sv, line:1:1, endln:20:10 + \_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/FuncStatic/dut.sv, line:1:1, endln:20:10 |vpiRhs: \_func_call: (accumulate2), line:17:21, endln:17:32 |vpiArgument: @@ -397,7 +397,7 @@ design: (work@test) |vpiParamAssign: \_param_assign: , line:18:12, endln:18:35 |vpiParent: - \_module: work@test (work@test), file:${SURELOG_DIR}/tests/FuncStatic/dut.sv, line:1:1, endln:20:10 + \_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/FuncStatic/dut.sv, line:1:1, endln:20:10 |vpiRhs: \_func_call: (accumulate2), line:18:21, endln:18:32 |vpiArgument: @@ -417,7 +417,7 @@ design: (work@test) |vpiTaskFunc: \_function: (work@test.accumulate1), line:3:1, endln:7:12 |vpiParent: - \_module: work@test (work@test), file:${SURELOG_DIR}/tests/FuncStatic/dut.sv, line:1:1, endln:20:10 + \_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/FuncStatic/dut.sv, line:1:1, endln:20:10 |vpiName:accumulate1 |vpiFullName:work@test.accumulate1 |vpiVariables: @@ -438,7 +438,7 @@ design: (work@test) |vpiSigned:1 |vpiSigned:1 |vpiParent: - \_module: work@test (work@test), file:${SURELOG_DIR}/tests/FuncStatic/dut.sv, line:1:1, endln:20:10 + \_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/FuncStatic/dut.sv, line:1:1, endln:20:10 |vpiIODecl: \_io_decl: (value), line:3:51, endln:3:56 |vpiDirection:1 @@ -515,11 +515,11 @@ design: (work@test) |vpiActual: \_int_var: (work@test.accumulate1.acc), line:4:14, endln:4:17 |vpiInstance: - \_module: work@test (work@test), file:${SURELOG_DIR}/tests/FuncStatic/dut.sv, line:1:1, endln:20:10 + \_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/FuncStatic/dut.sv, line:1:1, endln:20:10 |vpiTaskFunc: \_function: (work@test.accumulate2), line:9:1, endln:13:12 |vpiParent: - \_module: work@test (work@test), file:${SURELOG_DIR}/tests/FuncStatic/dut.sv, line:1:1, endln:20:10 + \_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/FuncStatic/dut.sv, line:1:1, endln:20:10 |vpiName:accumulate2 |vpiFullName:work@test.accumulate2 |vpiVariables: @@ -540,7 +540,7 @@ design: (work@test) |vpiSigned:1 |vpiSigned:1 |vpiParent: - \_module: work@test (work@test), file:${SURELOG_DIR}/tests/FuncStatic/dut.sv, line:1:1, endln:20:10 + \_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/FuncStatic/dut.sv, line:1:1, endln:20:10 |vpiIODecl: \_io_decl: (value), line:9:44, endln:9:49 |vpiDirection:1 @@ -617,42 +617,42 @@ design: (work@test) |vpiActual: \_int_var: (work@test.accumulate2.acc), line:10:7, endln:10:10 |vpiInstance: - \_module: work@test (work@test), file:${SURELOG_DIR}/tests/FuncStatic/dut.sv, line:1:1, endln:20:10 + \_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/FuncStatic/dut.sv, line:1:1, endln:20:10 |uhdmtopModules: -\_module: work@test (work@test), file:${SURELOG_DIR}/tests/FuncStatic/dut.sv, line:1:1, endln:20:10 +\_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/FuncStatic/dut.sv, line:1:1, endln:20:10 |vpiName:work@test |vpiParameter: \_parameter: (work@test.value1), line:15:12, endln:15:18 |vpiParent: - \_module: work@test (work@test), file:${SURELOG_DIR}/tests/FuncStatic/dut.sv, line:1:1, endln:20:10 + \_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/FuncStatic/dut.sv, line:1:1, endln:20:10 |vpiLocalParam:1 |vpiName:value1 |vpiFullName:work@test.value1 |vpiParameter: \_parameter: (work@test.value2), line:16:12, endln:16:18 |vpiParent: - \_module: work@test (work@test), file:${SURELOG_DIR}/tests/FuncStatic/dut.sv, line:1:1, endln:20:10 + \_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/FuncStatic/dut.sv, line:1:1, endln:20:10 |vpiLocalParam:1 |vpiName:value2 |vpiFullName:work@test.value2 |vpiParameter: \_parameter: (work@test.value3), line:17:12, endln:17:18 |vpiParent: - \_module: work@test (work@test), file:${SURELOG_DIR}/tests/FuncStatic/dut.sv, line:1:1, endln:20:10 + \_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/FuncStatic/dut.sv, line:1:1, endln:20:10 |vpiLocalParam:1 |vpiName:value3 |vpiFullName:work@test.value3 |vpiParameter: \_parameter: (work@test.value4), line:18:12, endln:18:18 |vpiParent: - \_module: work@test (work@test), file:${SURELOG_DIR}/tests/FuncStatic/dut.sv, line:1:1, endln:20:10 + \_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/FuncStatic/dut.sv, line:1:1, endln:20:10 |vpiLocalParam:1 |vpiName:value4 |vpiFullName:work@test.value4 |vpiParamAssign: \_param_assign: , line:15:12, endln:15:35 |vpiParent: - \_module: work@test (work@test), file:${SURELOG_DIR}/tests/FuncStatic/dut.sv, line:1:1, endln:20:10 + \_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/FuncStatic/dut.sv, line:1:1, endln:20:10 |vpiRhs: \_constant: , line:15:21, endln:15:35 |vpiDecompile:3 @@ -664,7 +664,7 @@ design: (work@test) |vpiParamAssign: \_param_assign: , line:16:12, endln:16:35 |vpiParent: - \_module: work@test (work@test), file:${SURELOG_DIR}/tests/FuncStatic/dut.sv, line:1:1, endln:20:10 + \_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/FuncStatic/dut.sv, line:1:1, endln:20:10 |vpiRhs: \_constant: , line:16:21, endln:16:35 |vpiDecompile:4 @@ -676,7 +676,7 @@ design: (work@test) |vpiParamAssign: \_param_assign: , line:17:12, endln:17:35 |vpiParent: - \_module: work@test (work@test), file:${SURELOG_DIR}/tests/FuncStatic/dut.sv, line:1:1, endln:20:10 + \_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/FuncStatic/dut.sv, line:1:1, endln:20:10 |vpiRhs: \_constant: , line:17:21, endln:17:35 |vpiDecompile:3 @@ -688,7 +688,7 @@ design: (work@test) |vpiParamAssign: \_param_assign: , line:18:12, endln:18:35 |vpiParent: - \_module: work@test (work@test), file:${SURELOG_DIR}/tests/FuncStatic/dut.sv, line:1:1, endln:20:10 + \_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/FuncStatic/dut.sv, line:1:1, endln:20:10 |vpiRhs: \_constant: , line:18:21, endln:18:35 |vpiDecompile:4 @@ -702,7 +702,7 @@ design: (work@test) |vpiTaskFunc: \_function: (work@test.accumulate1), line:3:1, endln:7:12 |vpiParent: - \_module: work@test (work@test), file:${SURELOG_DIR}/tests/FuncStatic/dut.sv, line:1:1, endln:20:10 + \_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/FuncStatic/dut.sv, line:1:1, endln:20:10 |vpiName:accumulate1 |vpiFullName:work@test.accumulate1 |vpiVariables: @@ -718,7 +718,7 @@ design: (work@test) |vpiReturn: \_integer_var: , line:3:17, endln:3:24 |vpiParent: - \_module: work@test (work@test), file:${SURELOG_DIR}/tests/FuncStatic/dut.sv, line:1:1, endln:20:10 + \_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/FuncStatic/dut.sv, line:1:1, endln:20:10 |vpiIODecl: \_io_decl: (value), line:3:51, endln:3:56 |vpiParent: @@ -804,11 +804,11 @@ design: (work@test) |vpiActual: \_int_var: (work@test.accumulate1.acc), line:4:14, endln:4:17 |vpiInstance: - \_module: work@test (work@test), file:${SURELOG_DIR}/tests/FuncStatic/dut.sv, line:1:1, endln:20:10 + \_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/FuncStatic/dut.sv, line:1:1, endln:20:10 |vpiTaskFunc: \_function: (work@test.accumulate2), line:9:1, endln:13:12 |vpiParent: - \_module: work@test (work@test), file:${SURELOG_DIR}/tests/FuncStatic/dut.sv, line:1:1, endln:20:10 + \_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/FuncStatic/dut.sv, line:1:1, endln:20:10 |vpiName:accumulate2 |vpiFullName:work@test.accumulate2 |vpiVariables: @@ -824,7 +824,7 @@ design: (work@test) |vpiReturn: \_integer_var: , line:9:10, endln:9:17 |vpiParent: - \_module: work@test (work@test), file:${SURELOG_DIR}/tests/FuncStatic/dut.sv, line:1:1, endln:20:10 + \_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/FuncStatic/dut.sv, line:1:1, endln:20:10 |vpiIODecl: \_io_decl: (value), line:9:44, endln:9:49 |vpiParent: @@ -910,7 +910,7 @@ design: (work@test) |vpiActual: \_int_var: (work@test.accumulate2.acc), line:10:7, endln:10:10 |vpiInstance: - \_module: work@test (work@test), file:${SURELOG_DIR}/tests/FuncStatic/dut.sv, line:1:1, endln:20:10 + \_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/FuncStatic/dut.sv, line:1:1, endln:20:10 |vpiTopModule:1 =================== [ FATAL] : 0 diff --git a/tests/FuncStruct/FuncStruct.log b/tests/FuncStruct/FuncStruct.log index ea34ac62cc..13f086160a 100644 --- a/tests/FuncStruct/FuncStruct.log +++ b/tests/FuncStruct/FuncStruct.log @@ -267,7 +267,7 @@ io_decl 4 logic_net 2 logic_typespec 20 logic_var 6 -module 6 +module_inst 6 package 3 packed_array_typespec 2 param_assign 2 @@ -292,7 +292,7 @@ io_decl 10 logic_net 2 logic_typespec 20 logic_var 12 -module 6 +module_inst 6 package 3 packed_array_typespec 2 param_assign 2 @@ -616,7 +616,7 @@ design: (work@dut) |vpiTypedef: \_logic_typespec: (hmac_pkg::sha_word_t), line:2:9, endln:2:21 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/FuncStruct/dut.sv, line:12:1, endln:19:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/FuncStruct/dut.sv, line:12:1, endln:19:10 |vpiName:hmac_pkg::sha_word_t |vpiInstance: \_package: hmac_pkg (hmac_pkg::), file:${SURELOG_DIR}/tests/FuncStruct/dut.sv, line:1:1, endln:9:11 @@ -904,7 +904,7 @@ design: (work@dut) |vpiInstance: \_package: hmac_pkg (hmac_pkg::), file:${SURELOG_DIR}/tests/FuncStruct/dut.sv, line:1:1, endln:9:11 |uhdmallModules: -\_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/FuncStruct/dut.sv, line:12:1, endln:19:10 +\_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/FuncStruct/dut.sv, line:12:1, endln:19:10 |vpiParent: \_design: (work@dut) |vpiFullName:work@dut @@ -1002,21 +1002,21 @@ design: (work@dut) |vpiNet: \_logic_net: (work@dut.w), line:14:19, endln:14:20 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/FuncStruct/dut.sv, line:12:1, endln:19:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/FuncStruct/dut.sv, line:12:1, endln:19:10 |vpiName:w |vpiFullName:work@dut.w |vpiNetType:36 |vpiNet: \_logic_net: (work@dut.hash), line:15:18, endln:15:22 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/FuncStruct/dut.sv, line:12:1, endln:19:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/FuncStruct/dut.sv, line:12:1, endln:19:10 |vpiName:hash |vpiFullName:work@dut.hash |vpiNetType:36 |vpiContAssign: \_cont_assign: , line:16:8, endln:16:27 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/FuncStruct/dut.sv, line:12:1, endln:19:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/FuncStruct/dut.sv, line:12:1, endln:19:10 |vpiRhs: \_constant: , line:16:15, endln:16:27 |vpiParent: @@ -1046,7 +1046,7 @@ design: (work@dut) |vpiContAssign: \_cont_assign: , line:17:8, endln:17:35 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/FuncStruct/dut.sv, line:12:1, endln:19:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/FuncStruct/dut.sv, line:12:1, endln:19:10 |vpiRhs: \_func_call: (compress), line:17:15, endln:17:35 |vpiParent: @@ -1093,12 +1093,12 @@ design: (work@dut) |vpiActual: \_logic_var: (work@dut.hash), line:15:18, endln:15:22 |uhdmtopModules: -\_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/FuncStruct/dut.sv, line:12:1, endln:19:10 +\_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/FuncStruct/dut.sv, line:12:1, endln:19:10 |vpiName:work@dut |vpiVariables: \_logic_var: (work@dut.w), line:14:19, endln:14:20 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/FuncStruct/dut.sv, line:12:1, endln:19:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/FuncStruct/dut.sv, line:12:1, endln:19:10 |vpiTypespec: \_logic_typespec: (sha_word_t), line:2:9, endln:2:21 |vpiName:sha_word_t @@ -1130,7 +1130,7 @@ design: (work@dut) |vpiVariables: \_logic_var: (work@dut.hash), line:15:18, endln:15:22 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/FuncStruct/dut.sv, line:12:1, endln:19:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/FuncStruct/dut.sv, line:12:1, endln:19:10 |vpiTypespec: \_logic_typespec: (sha_word_t), line:2:9, endln:2:21 |vpiName:sha_word_t @@ -1168,7 +1168,7 @@ design: (work@dut) |vpiTaskFunc: \_function: (hmac_pkg::compress), line:3:1, endln:8:12 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/FuncStruct/dut.sv, line:12:1, endln:19:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/FuncStruct/dut.sv, line:12:1, endln:19:10 |vpiName:compress |vpiFullName:hmac_pkg::compress |vpiVariables: @@ -1185,7 +1185,7 @@ design: (work@dut) |vpiReturn: \_logic_var: , line:3:20, endln:3:36 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/FuncStruct/dut.sv, line:12:1, endln:19:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/FuncStruct/dut.sv, line:12:1, endln:19:10 |vpiIODecl: \_io_decl: (w), line:3:64, endln:3:65 |vpiParent: @@ -1265,12 +1265,12 @@ design: (work@dut) |vpiActual: \_logic_var: , line:3:20, endln:3:36 |vpiInstance: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/FuncStruct/dut.sv, line:12:1, endln:19:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/FuncStruct/dut.sv, line:12:1, endln:19:10 |vpiTopModule:1 |vpiContAssign: \_cont_assign: , line:16:8, endln:16:27 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/FuncStruct/dut.sv, line:12:1, endln:19:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/FuncStruct/dut.sv, line:12:1, endln:19:10 |vpiRhs: \_constant: , line:16:15, endln:16:27 |vpiLhs: @@ -1298,7 +1298,7 @@ design: (work@dut) |vpiContAssign: \_cont_assign: , line:17:8, endln:17:35 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/FuncStruct/dut.sv, line:12:1, endln:19:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/FuncStruct/dut.sv, line:12:1, endln:19:10 |vpiRhs: \_func_call: (compress), line:17:15, endln:17:35 |vpiParent: diff --git a/tests/GateLevel/GateLevel.log b/tests/GateLevel/GateLevel.log index d51eda1030..8216958b3c 100644 --- a/tests/GateLevel/GateLevel.log +++ b/tests/GateLevel/GateLevel.log @@ -787,7 +787,7 @@ io_decl 11 logic_net 30 logic_typespec 15 logic_var 1 -module 7 +module_inst 7 operation 15 package 2 port 64 @@ -815,7 +815,7 @@ io_decl 22 logic_net 30 logic_typespec 15 logic_var 1 -module 7 +module_inst 7 operation 15 package 2 port 76 @@ -1312,7 +1312,7 @@ design: (work@LogicGates) \_int_typespec: |vpiSigned:1 |uhdmallModules: -\_module: work@LogicGates (work@LogicGates), file:${SURELOG_DIR}/tests/GateLevel/dut.sv, line:1:1, endln:20:10 +\_module_inst: work@LogicGates (work@LogicGates), file:${SURELOG_DIR}/tests/GateLevel/dut.sv, line:1:1, endln:20:10 |vpiParent: \_design: (work@LogicGates) |vpiFullName:work@LogicGates @@ -1320,79 +1320,79 @@ design: (work@LogicGates) |vpiNet: \_logic_net: (work@LogicGates.a), line:1:19, endln:1:20 |vpiParent: - \_module: work@LogicGates (work@LogicGates), file:${SURELOG_DIR}/tests/GateLevel/dut.sv, line:1:1, endln:20:10 + \_module_inst: work@LogicGates (work@LogicGates), file:${SURELOG_DIR}/tests/GateLevel/dut.sv, line:1:1, endln:20:10 |vpiName:a |vpiFullName:work@LogicGates.a |vpiNet: \_logic_net: (work@LogicGates.b), line:1:21, endln:1:22 |vpiParent: - \_module: work@LogicGates (work@LogicGates), file:${SURELOG_DIR}/tests/GateLevel/dut.sv, line:1:1, endln:20:10 + \_module_inst: work@LogicGates (work@LogicGates), file:${SURELOG_DIR}/tests/GateLevel/dut.sv, line:1:1, endln:20:10 |vpiName:b |vpiFullName:work@LogicGates.b |vpiNet: \_logic_net: (work@LogicGates.y1), line:1:23, endln:1:25 |vpiParent: - \_module: work@LogicGates (work@LogicGates), file:${SURELOG_DIR}/tests/GateLevel/dut.sv, line:1:1, endln:20:10 + \_module_inst: work@LogicGates (work@LogicGates), file:${SURELOG_DIR}/tests/GateLevel/dut.sv, line:1:1, endln:20:10 |vpiName:y1 |vpiFullName:work@LogicGates.y1 |vpiNet: \_logic_net: (work@LogicGates.y2), line:1:26, endln:1:28 |vpiParent: - \_module: work@LogicGates (work@LogicGates), file:${SURELOG_DIR}/tests/GateLevel/dut.sv, line:1:1, endln:20:10 + \_module_inst: work@LogicGates (work@LogicGates), file:${SURELOG_DIR}/tests/GateLevel/dut.sv, line:1:1, endln:20:10 |vpiName:y2 |vpiFullName:work@LogicGates.y2 |vpiNet: \_logic_net: (work@LogicGates.y3), line:1:29, endln:1:31 |vpiParent: - \_module: work@LogicGates (work@LogicGates), file:${SURELOG_DIR}/tests/GateLevel/dut.sv, line:1:1, endln:20:10 + \_module_inst: work@LogicGates (work@LogicGates), file:${SURELOG_DIR}/tests/GateLevel/dut.sv, line:1:1, endln:20:10 |vpiName:y3 |vpiFullName:work@LogicGates.y3 |vpiNet: \_logic_net: (work@LogicGates.y4), line:1:32, endln:1:34 |vpiParent: - \_module: work@LogicGates (work@LogicGates), file:${SURELOG_DIR}/tests/GateLevel/dut.sv, line:1:1, endln:20:10 + \_module_inst: work@LogicGates (work@LogicGates), file:${SURELOG_DIR}/tests/GateLevel/dut.sv, line:1:1, endln:20:10 |vpiName:y4 |vpiFullName:work@LogicGates.y4 |vpiNet: \_logic_net: (work@LogicGates.y5), line:1:35, endln:1:37 |vpiParent: - \_module: work@LogicGates (work@LogicGates), file:${SURELOG_DIR}/tests/GateLevel/dut.sv, line:1:1, endln:20:10 + \_module_inst: work@LogicGates (work@LogicGates), file:${SURELOG_DIR}/tests/GateLevel/dut.sv, line:1:1, endln:20:10 |vpiName:y5 |vpiFullName:work@LogicGates.y5 |vpiNet: \_logic_net: (work@LogicGates.y6), line:1:38, endln:1:40 |vpiParent: - \_module: work@LogicGates (work@LogicGates), file:${SURELOG_DIR}/tests/GateLevel/dut.sv, line:1:1, endln:20:10 + \_module_inst: work@LogicGates (work@LogicGates), file:${SURELOG_DIR}/tests/GateLevel/dut.sv, line:1:1, endln:20:10 |vpiName:y6 |vpiFullName:work@LogicGates.y6 |vpiNet: \_logic_net: (work@LogicGates.y7), line:1:41, endln:1:43 |vpiParent: - \_module: work@LogicGates (work@LogicGates), file:${SURELOG_DIR}/tests/GateLevel/dut.sv, line:1:1, endln:20:10 + \_module_inst: work@LogicGates (work@LogicGates), file:${SURELOG_DIR}/tests/GateLevel/dut.sv, line:1:1, endln:20:10 |vpiName:y7 |vpiFullName:work@LogicGates.y7 |vpiNet: \_logic_net: (work@LogicGates.y8), line:1:45, endln:1:47 |vpiParent: - \_module: work@LogicGates (work@LogicGates), file:${SURELOG_DIR}/tests/GateLevel/dut.sv, line:1:1, endln:20:10 + \_module_inst: work@LogicGates (work@LogicGates), file:${SURELOG_DIR}/tests/GateLevel/dut.sv, line:1:1, endln:20:10 |vpiName:y8 |vpiFullName:work@LogicGates.y8 |vpiNet: \_logic_net: (work@LogicGates.y9), line:1:49, endln:1:51 |vpiParent: - \_module: work@LogicGates (work@LogicGates), file:${SURELOG_DIR}/tests/GateLevel/dut.sv, line:1:1, endln:20:10 + \_module_inst: work@LogicGates (work@LogicGates), file:${SURELOG_DIR}/tests/GateLevel/dut.sv, line:1:1, endln:20:10 |vpiName:y9 |vpiFullName:work@LogicGates.y9 |vpiNet: \_logic_net: (work@LogicGates.y10), line:1:53, endln:1:56 |vpiParent: - \_module: work@LogicGates (work@LogicGates), file:${SURELOG_DIR}/tests/GateLevel/dut.sv, line:1:1, endln:20:10 + \_module_inst: work@LogicGates (work@LogicGates), file:${SURELOG_DIR}/tests/GateLevel/dut.sv, line:1:1, endln:20:10 |vpiName:y10 |vpiFullName:work@LogicGates.y10 |vpiPort: \_port: (a), line:1:19, endln:1:20 |vpiParent: - \_module: work@LogicGates (work@LogicGates), file:${SURELOG_DIR}/tests/GateLevel/dut.sv, line:1:1, endln:20:10 + \_module_inst: work@LogicGates (work@LogicGates), file:${SURELOG_DIR}/tests/GateLevel/dut.sv, line:1:1, endln:20:10 |vpiName:a |vpiDirection:1 |vpiLowConn: @@ -1404,7 +1404,7 @@ design: (work@LogicGates) |vpiPort: \_port: (b), line:1:21, endln:1:22 |vpiParent: - \_module: work@LogicGates (work@LogicGates), file:${SURELOG_DIR}/tests/GateLevel/dut.sv, line:1:1, endln:20:10 + \_module_inst: work@LogicGates (work@LogicGates), file:${SURELOG_DIR}/tests/GateLevel/dut.sv, line:1:1, endln:20:10 |vpiName:b |vpiDirection:1 |vpiLowConn: @@ -1416,7 +1416,7 @@ design: (work@LogicGates) |vpiPort: \_port: (y1), line:1:23, endln:1:25 |vpiParent: - \_module: work@LogicGates (work@LogicGates), file:${SURELOG_DIR}/tests/GateLevel/dut.sv, line:1:1, endln:20:10 + \_module_inst: work@LogicGates (work@LogicGates), file:${SURELOG_DIR}/tests/GateLevel/dut.sv, line:1:1, endln:20:10 |vpiName:y1 |vpiDirection:2 |vpiLowConn: @@ -1428,7 +1428,7 @@ design: (work@LogicGates) |vpiPort: \_port: (y2), line:1:26, endln:1:28 |vpiParent: - \_module: work@LogicGates (work@LogicGates), file:${SURELOG_DIR}/tests/GateLevel/dut.sv, line:1:1, endln:20:10 + \_module_inst: work@LogicGates (work@LogicGates), file:${SURELOG_DIR}/tests/GateLevel/dut.sv, line:1:1, endln:20:10 |vpiName:y2 |vpiDirection:2 |vpiLowConn: @@ -1440,7 +1440,7 @@ design: (work@LogicGates) |vpiPort: \_port: (y3), line:1:29, endln:1:31 |vpiParent: - \_module: work@LogicGates (work@LogicGates), file:${SURELOG_DIR}/tests/GateLevel/dut.sv, line:1:1, endln:20:10 + \_module_inst: work@LogicGates (work@LogicGates), file:${SURELOG_DIR}/tests/GateLevel/dut.sv, line:1:1, endln:20:10 |vpiName:y3 |vpiDirection:2 |vpiLowConn: @@ -1452,7 +1452,7 @@ design: (work@LogicGates) |vpiPort: \_port: (y4), line:1:32, endln:1:34 |vpiParent: - \_module: work@LogicGates (work@LogicGates), file:${SURELOG_DIR}/tests/GateLevel/dut.sv, line:1:1, endln:20:10 + \_module_inst: work@LogicGates (work@LogicGates), file:${SURELOG_DIR}/tests/GateLevel/dut.sv, line:1:1, endln:20:10 |vpiName:y4 |vpiDirection:2 |vpiLowConn: @@ -1464,7 +1464,7 @@ design: (work@LogicGates) |vpiPort: \_port: (y5), line:1:35, endln:1:37 |vpiParent: - \_module: work@LogicGates (work@LogicGates), file:${SURELOG_DIR}/tests/GateLevel/dut.sv, line:1:1, endln:20:10 + \_module_inst: work@LogicGates (work@LogicGates), file:${SURELOG_DIR}/tests/GateLevel/dut.sv, line:1:1, endln:20:10 |vpiName:y5 |vpiDirection:2 |vpiLowConn: @@ -1476,7 +1476,7 @@ design: (work@LogicGates) |vpiPort: \_port: (y6), line:1:38, endln:1:40 |vpiParent: - \_module: work@LogicGates (work@LogicGates), file:${SURELOG_DIR}/tests/GateLevel/dut.sv, line:1:1, endln:20:10 + \_module_inst: work@LogicGates (work@LogicGates), file:${SURELOG_DIR}/tests/GateLevel/dut.sv, line:1:1, endln:20:10 |vpiName:y6 |vpiDirection:2 |vpiLowConn: @@ -1488,7 +1488,7 @@ design: (work@LogicGates) |vpiPort: \_port: (y7), line:1:41, endln:1:43 |vpiParent: - \_module: work@LogicGates (work@LogicGates), file:${SURELOG_DIR}/tests/GateLevel/dut.sv, line:1:1, endln:20:10 + \_module_inst: work@LogicGates (work@LogicGates), file:${SURELOG_DIR}/tests/GateLevel/dut.sv, line:1:1, endln:20:10 |vpiName:y7 |vpiDirection:2 |vpiLowConn: @@ -1500,7 +1500,7 @@ design: (work@LogicGates) |vpiPort: \_port: (y8), line:1:45, endln:1:47 |vpiParent: - \_module: work@LogicGates (work@LogicGates), file:${SURELOG_DIR}/tests/GateLevel/dut.sv, line:1:1, endln:20:10 + \_module_inst: work@LogicGates (work@LogicGates), file:${SURELOG_DIR}/tests/GateLevel/dut.sv, line:1:1, endln:20:10 |vpiName:y8 |vpiDirection:2 |vpiLowConn: @@ -1512,7 +1512,7 @@ design: (work@LogicGates) |vpiPort: \_port: (y9), line:1:49, endln:1:51 |vpiParent: - \_module: work@LogicGates (work@LogicGates), file:${SURELOG_DIR}/tests/GateLevel/dut.sv, line:1:1, endln:20:10 + \_module_inst: work@LogicGates (work@LogicGates), file:${SURELOG_DIR}/tests/GateLevel/dut.sv, line:1:1, endln:20:10 |vpiName:y9 |vpiDirection:2 |vpiLowConn: @@ -1524,7 +1524,7 @@ design: (work@LogicGates) |vpiPort: \_port: (y10), line:1:53, endln:1:56 |vpiParent: - \_module: work@LogicGates (work@LogicGates), file:${SURELOG_DIR}/tests/GateLevel/dut.sv, line:1:1, endln:20:10 + \_module_inst: work@LogicGates (work@LogicGates), file:${SURELOG_DIR}/tests/GateLevel/dut.sv, line:1:1, endln:20:10 |vpiName:y10 |vpiDirection:2 |vpiLowConn: @@ -1532,14 +1532,14 @@ design: (work@LogicGates) |vpiActual: \_logic_net: (work@LogicGates.y10), line:1:53, endln:1:56 |uhdmtopModules: -\_module: work@LogicGates (work@LogicGates), file:${SURELOG_DIR}/tests/GateLevel/dut.sv, line:1:1, endln:20:10 +\_module_inst: work@LogicGates (work@LogicGates), file:${SURELOG_DIR}/tests/GateLevel/dut.sv, line:1:1, endln:20:10 |vpiName:work@LogicGates |vpiDefName:work@LogicGates |vpiTop:1 |vpiNet: \_logic_net: (work@LogicGates.a), line:1:19, endln:1:20 |vpiParent: - \_module: work@LogicGates (work@LogicGates), file:${SURELOG_DIR}/tests/GateLevel/dut.sv, line:1:1, endln:20:10 + \_module_inst: work@LogicGates (work@LogicGates), file:${SURELOG_DIR}/tests/GateLevel/dut.sv, line:1:1, endln:20:10 |vpiTypespec: \_logic_typespec: , line:2:9, endln:2:9 |vpiName:a @@ -1547,7 +1547,7 @@ design: (work@LogicGates) |vpiNet: \_logic_net: (work@LogicGates.b), line:1:21, endln:1:22 |vpiParent: - \_module: work@LogicGates (work@LogicGates), file:${SURELOG_DIR}/tests/GateLevel/dut.sv, line:1:1, endln:20:10 + \_module_inst: work@LogicGates (work@LogicGates), file:${SURELOG_DIR}/tests/GateLevel/dut.sv, line:1:1, endln:20:10 |vpiTypespec: \_logic_typespec: , line:2:9, endln:2:9 |vpiName:b @@ -1555,7 +1555,7 @@ design: (work@LogicGates) |vpiNet: \_logic_net: (work@LogicGates.y1), line:1:23, endln:1:25 |vpiParent: - \_module: work@LogicGates (work@LogicGates), file:${SURELOG_DIR}/tests/GateLevel/dut.sv, line:1:1, endln:20:10 + \_module_inst: work@LogicGates (work@LogicGates), file:${SURELOG_DIR}/tests/GateLevel/dut.sv, line:1:1, endln:20:10 |vpiTypespec: \_logic_typespec: , line:3:10, endln:3:10 |vpiName:y1 @@ -1563,7 +1563,7 @@ design: (work@LogicGates) |vpiNet: \_logic_net: (work@LogicGates.y2), line:1:26, endln:1:28 |vpiParent: - \_module: work@LogicGates (work@LogicGates), file:${SURELOG_DIR}/tests/GateLevel/dut.sv, line:1:1, endln:20:10 + \_module_inst: work@LogicGates (work@LogicGates), file:${SURELOG_DIR}/tests/GateLevel/dut.sv, line:1:1, endln:20:10 |vpiTypespec: \_logic_typespec: , line:3:10, endln:3:10 |vpiName:y2 @@ -1571,7 +1571,7 @@ design: (work@LogicGates) |vpiNet: \_logic_net: (work@LogicGates.y3), line:1:29, endln:1:31 |vpiParent: - \_module: work@LogicGates (work@LogicGates), file:${SURELOG_DIR}/tests/GateLevel/dut.sv, line:1:1, endln:20:10 + \_module_inst: work@LogicGates (work@LogicGates), file:${SURELOG_DIR}/tests/GateLevel/dut.sv, line:1:1, endln:20:10 |vpiTypespec: \_logic_typespec: , line:3:10, endln:3:10 |vpiName:y3 @@ -1579,7 +1579,7 @@ design: (work@LogicGates) |vpiNet: \_logic_net: (work@LogicGates.y4), line:1:32, endln:1:34 |vpiParent: - \_module: work@LogicGates (work@LogicGates), file:${SURELOG_DIR}/tests/GateLevel/dut.sv, line:1:1, endln:20:10 + \_module_inst: work@LogicGates (work@LogicGates), file:${SURELOG_DIR}/tests/GateLevel/dut.sv, line:1:1, endln:20:10 |vpiTypespec: \_logic_typespec: , line:3:10, endln:3:10 |vpiName:y4 @@ -1587,7 +1587,7 @@ design: (work@LogicGates) |vpiNet: \_logic_net: (work@LogicGates.y5), line:1:35, endln:1:37 |vpiParent: - \_module: work@LogicGates (work@LogicGates), file:${SURELOG_DIR}/tests/GateLevel/dut.sv, line:1:1, endln:20:10 + \_module_inst: work@LogicGates (work@LogicGates), file:${SURELOG_DIR}/tests/GateLevel/dut.sv, line:1:1, endln:20:10 |vpiTypespec: \_logic_typespec: , line:3:10, endln:3:10 |vpiName:y5 @@ -1595,7 +1595,7 @@ design: (work@LogicGates) |vpiNet: \_logic_net: (work@LogicGates.y6), line:1:38, endln:1:40 |vpiParent: - \_module: work@LogicGates (work@LogicGates), file:${SURELOG_DIR}/tests/GateLevel/dut.sv, line:1:1, endln:20:10 + \_module_inst: work@LogicGates (work@LogicGates), file:${SURELOG_DIR}/tests/GateLevel/dut.sv, line:1:1, endln:20:10 |vpiTypespec: \_logic_typespec: , line:3:10, endln:3:10 |vpiName:y6 @@ -1603,7 +1603,7 @@ design: (work@LogicGates) |vpiNet: \_logic_net: (work@LogicGates.y7), line:1:41, endln:1:43 |vpiParent: - \_module: work@LogicGates (work@LogicGates), file:${SURELOG_DIR}/tests/GateLevel/dut.sv, line:1:1, endln:20:10 + \_module_inst: work@LogicGates (work@LogicGates), file:${SURELOG_DIR}/tests/GateLevel/dut.sv, line:1:1, endln:20:10 |vpiTypespec: \_logic_typespec: , line:3:10, endln:3:10 |vpiName:y7 @@ -1611,7 +1611,7 @@ design: (work@LogicGates) |vpiNet: \_logic_net: (work@LogicGates.y8), line:1:45, endln:1:47 |vpiParent: - \_module: work@LogicGates (work@LogicGates), file:${SURELOG_DIR}/tests/GateLevel/dut.sv, line:1:1, endln:20:10 + \_module_inst: work@LogicGates (work@LogicGates), file:${SURELOG_DIR}/tests/GateLevel/dut.sv, line:1:1, endln:20:10 |vpiTypespec: \_logic_typespec: , line:3:10, endln:3:10 |vpiName:y8 @@ -1619,7 +1619,7 @@ design: (work@LogicGates) |vpiNet: \_logic_net: (work@LogicGates.y9), line:1:49, endln:1:51 |vpiParent: - \_module: work@LogicGates (work@LogicGates), file:${SURELOG_DIR}/tests/GateLevel/dut.sv, line:1:1, endln:20:10 + \_module_inst: work@LogicGates (work@LogicGates), file:${SURELOG_DIR}/tests/GateLevel/dut.sv, line:1:1, endln:20:10 |vpiTypespec: \_logic_typespec: , line:3:10, endln:3:10 |vpiName:y9 @@ -1627,48 +1627,48 @@ design: (work@LogicGates) |vpiNet: \_logic_net: (work@LogicGates.y10), line:1:53, endln:1:56 |vpiParent: - \_module: work@LogicGates (work@LogicGates), file:${SURELOG_DIR}/tests/GateLevel/dut.sv, line:1:1, endln:20:10 + \_module_inst: work@LogicGates (work@LogicGates), file:${SURELOG_DIR}/tests/GateLevel/dut.sv, line:1:1, endln:20:10 |vpiName:y10 |vpiFullName:work@LogicGates.y10 |vpiNet: \_logic_net: (work@LogicGates.nn), line:15:29, endln:15:31 |vpiParent: - \_module: work@LogicGates (work@LogicGates), file:${SURELOG_DIR}/tests/GateLevel/dut.sv, line:1:1, endln:20:10 + \_module_inst: work@LogicGates (work@LogicGates), file:${SURELOG_DIR}/tests/GateLevel/dut.sv, line:1:1, endln:20:10 |vpiName:nn |vpiFullName:work@LogicGates.nn |vpiNetType:1 |vpiNet: \_logic_net: (work@LogicGates.out2), line:16:25, endln:16:29 |vpiParent: - \_module: work@LogicGates (work@LogicGates), file:${SURELOG_DIR}/tests/GateLevel/dut.sv, line:1:1, endln:20:10 + \_module_inst: work@LogicGates (work@LogicGates), file:${SURELOG_DIR}/tests/GateLevel/dut.sv, line:1:1, endln:20:10 |vpiName:out2 |vpiFullName:work@LogicGates.out2 |vpiNetType:1 |vpiNet: \_logic_net: (work@LogicGates.out3), line:17:37, endln:17:41 |vpiParent: - \_module: work@LogicGates (work@LogicGates), file:${SURELOG_DIR}/tests/GateLevel/dut.sv, line:1:1, endln:20:10 + \_module_inst: work@LogicGates (work@LogicGates), file:${SURELOG_DIR}/tests/GateLevel/dut.sv, line:1:1, endln:20:10 |vpiName:out3 |vpiFullName:work@LogicGates.out3 |vpiNetType:1 |vpiNet: \_logic_net: (work@LogicGates.p1), line:18:12, endln:18:14 |vpiParent: - \_module: work@LogicGates (work@LogicGates), file:${SURELOG_DIR}/tests/GateLevel/dut.sv, line:1:1, endln:20:10 + \_module_inst: work@LogicGates (work@LogicGates), file:${SURELOG_DIR}/tests/GateLevel/dut.sv, line:1:1, endln:20:10 |vpiName:p1 |vpiFullName:work@LogicGates.p1 |vpiNetType:1 |vpiNet: \_logic_net: (work@LogicGates.p2), line:18:15, endln:18:17 |vpiParent: - \_module: work@LogicGates (work@LogicGates), file:${SURELOG_DIR}/tests/GateLevel/dut.sv, line:1:1, endln:20:10 + \_module_inst: work@LogicGates (work@LogicGates), file:${SURELOG_DIR}/tests/GateLevel/dut.sv, line:1:1, endln:20:10 |vpiName:p2 |vpiFullName:work@LogicGates.p2 |vpiNetType:1 |vpiNet: \_logic_net: (work@LogicGates.p3), line:18:18, endln:18:20 |vpiParent: - \_module: work@LogicGates (work@LogicGates), file:${SURELOG_DIR}/tests/GateLevel/dut.sv, line:1:1, endln:20:10 + \_module_inst: work@LogicGates (work@LogicGates), file:${SURELOG_DIR}/tests/GateLevel/dut.sv, line:1:1, endln:20:10 |vpiName:p3 |vpiFullName:work@LogicGates.p3 |vpiNetType:1 @@ -1676,7 +1676,7 @@ design: (work@LogicGates) |vpiPort: \_port: (a), line:1:19, endln:1:20 |vpiParent: - \_module: work@LogicGates (work@LogicGates), file:${SURELOG_DIR}/tests/GateLevel/dut.sv, line:1:1, endln:20:10 + \_module_inst: work@LogicGates (work@LogicGates), file:${SURELOG_DIR}/tests/GateLevel/dut.sv, line:1:1, endln:20:10 |vpiName:a |vpiDirection:1 |vpiLowConn: @@ -1690,11 +1690,11 @@ design: (work@LogicGates) |vpiTypedef: \_logic_typespec: , line:2:9, endln:2:9 |vpiInstance: - \_module: work@LogicGates (work@LogicGates), file:${SURELOG_DIR}/tests/GateLevel/dut.sv, line:1:1, endln:20:10 + \_module_inst: work@LogicGates (work@LogicGates), file:${SURELOG_DIR}/tests/GateLevel/dut.sv, line:1:1, endln:20:10 |vpiPort: \_port: (b), line:1:21, endln:1:22 |vpiParent: - \_module: work@LogicGates (work@LogicGates), file:${SURELOG_DIR}/tests/GateLevel/dut.sv, line:1:1, endln:20:10 + \_module_inst: work@LogicGates (work@LogicGates), file:${SURELOG_DIR}/tests/GateLevel/dut.sv, line:1:1, endln:20:10 |vpiName:b |vpiDirection:1 |vpiLowConn: @@ -1708,11 +1708,11 @@ design: (work@LogicGates) |vpiTypedef: \_logic_typespec: , line:2:9, endln:2:9 |vpiInstance: - \_module: work@LogicGates (work@LogicGates), file:${SURELOG_DIR}/tests/GateLevel/dut.sv, line:1:1, endln:20:10 + \_module_inst: work@LogicGates (work@LogicGates), file:${SURELOG_DIR}/tests/GateLevel/dut.sv, line:1:1, endln:20:10 |vpiPort: \_port: (y1), line:1:23, endln:1:25 |vpiParent: - \_module: work@LogicGates (work@LogicGates), file:${SURELOG_DIR}/tests/GateLevel/dut.sv, line:1:1, endln:20:10 + \_module_inst: work@LogicGates (work@LogicGates), file:${SURELOG_DIR}/tests/GateLevel/dut.sv, line:1:1, endln:20:10 |vpiName:y1 |vpiDirection:2 |vpiLowConn: @@ -1726,11 +1726,11 @@ design: (work@LogicGates) |vpiTypedef: \_logic_typespec: , line:3:10, endln:3:10 |vpiInstance: - \_module: work@LogicGates (work@LogicGates), file:${SURELOG_DIR}/tests/GateLevel/dut.sv, line:1:1, endln:20:10 + \_module_inst: work@LogicGates (work@LogicGates), file:${SURELOG_DIR}/tests/GateLevel/dut.sv, line:1:1, endln:20:10 |vpiPort: \_port: (y2), line:1:26, endln:1:28 |vpiParent: - \_module: work@LogicGates (work@LogicGates), file:${SURELOG_DIR}/tests/GateLevel/dut.sv, line:1:1, endln:20:10 + \_module_inst: work@LogicGates (work@LogicGates), file:${SURELOG_DIR}/tests/GateLevel/dut.sv, line:1:1, endln:20:10 |vpiName:y2 |vpiDirection:2 |vpiLowConn: @@ -1744,11 +1744,11 @@ design: (work@LogicGates) |vpiTypedef: \_logic_typespec: , line:3:10, endln:3:10 |vpiInstance: - \_module: work@LogicGates (work@LogicGates), file:${SURELOG_DIR}/tests/GateLevel/dut.sv, line:1:1, endln:20:10 + \_module_inst: work@LogicGates (work@LogicGates), file:${SURELOG_DIR}/tests/GateLevel/dut.sv, line:1:1, endln:20:10 |vpiPort: \_port: (y3), line:1:29, endln:1:31 |vpiParent: - \_module: work@LogicGates (work@LogicGates), file:${SURELOG_DIR}/tests/GateLevel/dut.sv, line:1:1, endln:20:10 + \_module_inst: work@LogicGates (work@LogicGates), file:${SURELOG_DIR}/tests/GateLevel/dut.sv, line:1:1, endln:20:10 |vpiName:y3 |vpiDirection:2 |vpiLowConn: @@ -1762,11 +1762,11 @@ design: (work@LogicGates) |vpiTypedef: \_logic_typespec: , line:3:10, endln:3:10 |vpiInstance: - \_module: work@LogicGates (work@LogicGates), file:${SURELOG_DIR}/tests/GateLevel/dut.sv, line:1:1, endln:20:10 + \_module_inst: work@LogicGates (work@LogicGates), file:${SURELOG_DIR}/tests/GateLevel/dut.sv, line:1:1, endln:20:10 |vpiPort: \_port: (y4), line:1:32, endln:1:34 |vpiParent: - \_module: work@LogicGates (work@LogicGates), file:${SURELOG_DIR}/tests/GateLevel/dut.sv, line:1:1, endln:20:10 + \_module_inst: work@LogicGates (work@LogicGates), file:${SURELOG_DIR}/tests/GateLevel/dut.sv, line:1:1, endln:20:10 |vpiName:y4 |vpiDirection:2 |vpiLowConn: @@ -1780,11 +1780,11 @@ design: (work@LogicGates) |vpiTypedef: \_logic_typespec: , line:3:10, endln:3:10 |vpiInstance: - \_module: work@LogicGates (work@LogicGates), file:${SURELOG_DIR}/tests/GateLevel/dut.sv, line:1:1, endln:20:10 + \_module_inst: work@LogicGates (work@LogicGates), file:${SURELOG_DIR}/tests/GateLevel/dut.sv, line:1:1, endln:20:10 |vpiPort: \_port: (y5), line:1:35, endln:1:37 |vpiParent: - \_module: work@LogicGates (work@LogicGates), file:${SURELOG_DIR}/tests/GateLevel/dut.sv, line:1:1, endln:20:10 + \_module_inst: work@LogicGates (work@LogicGates), file:${SURELOG_DIR}/tests/GateLevel/dut.sv, line:1:1, endln:20:10 |vpiName:y5 |vpiDirection:2 |vpiLowConn: @@ -1798,11 +1798,11 @@ design: (work@LogicGates) |vpiTypedef: \_logic_typespec: , line:3:10, endln:3:10 |vpiInstance: - \_module: work@LogicGates (work@LogicGates), file:${SURELOG_DIR}/tests/GateLevel/dut.sv, line:1:1, endln:20:10 + \_module_inst: work@LogicGates (work@LogicGates), file:${SURELOG_DIR}/tests/GateLevel/dut.sv, line:1:1, endln:20:10 |vpiPort: \_port: (y6), line:1:38, endln:1:40 |vpiParent: - \_module: work@LogicGates (work@LogicGates), file:${SURELOG_DIR}/tests/GateLevel/dut.sv, line:1:1, endln:20:10 + \_module_inst: work@LogicGates (work@LogicGates), file:${SURELOG_DIR}/tests/GateLevel/dut.sv, line:1:1, endln:20:10 |vpiName:y6 |vpiDirection:2 |vpiLowConn: @@ -1816,11 +1816,11 @@ design: (work@LogicGates) |vpiTypedef: \_logic_typespec: , line:3:10, endln:3:10 |vpiInstance: - \_module: work@LogicGates (work@LogicGates), file:${SURELOG_DIR}/tests/GateLevel/dut.sv, line:1:1, endln:20:10 + \_module_inst: work@LogicGates (work@LogicGates), file:${SURELOG_DIR}/tests/GateLevel/dut.sv, line:1:1, endln:20:10 |vpiPort: \_port: (y7), line:1:41, endln:1:43 |vpiParent: - \_module: work@LogicGates (work@LogicGates), file:${SURELOG_DIR}/tests/GateLevel/dut.sv, line:1:1, endln:20:10 + \_module_inst: work@LogicGates (work@LogicGates), file:${SURELOG_DIR}/tests/GateLevel/dut.sv, line:1:1, endln:20:10 |vpiName:y7 |vpiDirection:2 |vpiLowConn: @@ -1834,11 +1834,11 @@ design: (work@LogicGates) |vpiTypedef: \_logic_typespec: , line:3:10, endln:3:10 |vpiInstance: - \_module: work@LogicGates (work@LogicGates), file:${SURELOG_DIR}/tests/GateLevel/dut.sv, line:1:1, endln:20:10 + \_module_inst: work@LogicGates (work@LogicGates), file:${SURELOG_DIR}/tests/GateLevel/dut.sv, line:1:1, endln:20:10 |vpiPort: \_port: (y8), line:1:45, endln:1:47 |vpiParent: - \_module: work@LogicGates (work@LogicGates), file:${SURELOG_DIR}/tests/GateLevel/dut.sv, line:1:1, endln:20:10 + \_module_inst: work@LogicGates (work@LogicGates), file:${SURELOG_DIR}/tests/GateLevel/dut.sv, line:1:1, endln:20:10 |vpiName:y8 |vpiDirection:2 |vpiLowConn: @@ -1852,11 +1852,11 @@ design: (work@LogicGates) |vpiTypedef: \_logic_typespec: , line:3:10, endln:3:10 |vpiInstance: - \_module: work@LogicGates (work@LogicGates), file:${SURELOG_DIR}/tests/GateLevel/dut.sv, line:1:1, endln:20:10 + \_module_inst: work@LogicGates (work@LogicGates), file:${SURELOG_DIR}/tests/GateLevel/dut.sv, line:1:1, endln:20:10 |vpiPort: \_port: (y9), line:1:49, endln:1:51 |vpiParent: - \_module: work@LogicGates (work@LogicGates), file:${SURELOG_DIR}/tests/GateLevel/dut.sv, line:1:1, endln:20:10 + \_module_inst: work@LogicGates (work@LogicGates), file:${SURELOG_DIR}/tests/GateLevel/dut.sv, line:1:1, endln:20:10 |vpiName:y9 |vpiDirection:2 |vpiLowConn: @@ -1870,11 +1870,11 @@ design: (work@LogicGates) |vpiTypedef: \_logic_typespec: , line:3:10, endln:3:10 |vpiInstance: - \_module: work@LogicGates (work@LogicGates), file:${SURELOG_DIR}/tests/GateLevel/dut.sv, line:1:1, endln:20:10 + \_module_inst: work@LogicGates (work@LogicGates), file:${SURELOG_DIR}/tests/GateLevel/dut.sv, line:1:1, endln:20:10 |vpiPort: \_port: (y10), line:1:53, endln:1:56 |vpiParent: - \_module: work@LogicGates (work@LogicGates), file:${SURELOG_DIR}/tests/GateLevel/dut.sv, line:1:1, endln:20:10 + \_module_inst: work@LogicGates (work@LogicGates), file:${SURELOG_DIR}/tests/GateLevel/dut.sv, line:1:1, endln:20:10 |vpiName:y10 |vpiDirection:2 |vpiLowConn: @@ -1886,11 +1886,11 @@ design: (work@LogicGates) |vpiActual: \_logic_net: (work@LogicGates.y10), line:1:53, endln:1:56 |vpiInstance: - \_module: work@LogicGates (work@LogicGates), file:${SURELOG_DIR}/tests/GateLevel/dut.sv, line:1:1, endln:20:10 + \_module_inst: work@LogicGates (work@LogicGates), file:${SURELOG_DIR}/tests/GateLevel/dut.sv, line:1:1, endln:20:10 |vpiPrimitive: \_gate: work@and (work@LogicGates.), line:5:6, endln:5:14 |vpiParent: - \_module: work@LogicGates (work@LogicGates), file:${SURELOG_DIR}/tests/GateLevel/dut.sv, line:1:1, endln:20:10 + \_module_inst: work@LogicGates (work@LogicGates), file:${SURELOG_DIR}/tests/GateLevel/dut.sv, line:1:1, endln:20:10 |vpiDefName:work@and |vpiFullName:work@LogicGates. |vpiPrimType:1 @@ -1938,7 +1938,7 @@ design: (work@LogicGates) |vpiPrimitive: \_gate: work@or (work@LogicGates.), line:6:5, endln:6:13 |vpiParent: - \_module: work@LogicGates (work@LogicGates), file:${SURELOG_DIR}/tests/GateLevel/dut.sv, line:1:1, endln:20:10 + \_module_inst: work@LogicGates (work@LogicGates), file:${SURELOG_DIR}/tests/GateLevel/dut.sv, line:1:1, endln:20:10 |vpiDefName:work@or |vpiFullName:work@LogicGates. |vpiPrimType:4 @@ -1986,7 +1986,7 @@ design: (work@LogicGates) |vpiPrimitive: \_gate: work@not (work@LogicGates.), line:7:6, endln:7:12 |vpiParent: - \_module: work@LogicGates (work@LogicGates), file:${SURELOG_DIR}/tests/GateLevel/dut.sv, line:1:1, endln:20:10 + \_module_inst: work@LogicGates (work@LogicGates), file:${SURELOG_DIR}/tests/GateLevel/dut.sv, line:1:1, endln:20:10 |vpiDefName:work@not |vpiFullName:work@LogicGates. |vpiPrimType:8 @@ -2020,7 +2020,7 @@ design: (work@LogicGates) |vpiPrimitive: \_gate: work@nand (work@LogicGates.), line:8:7, endln:8:15 |vpiParent: - \_module: work@LogicGates (work@LogicGates), file:${SURELOG_DIR}/tests/GateLevel/dut.sv, line:1:1, endln:20:10 + \_module_inst: work@LogicGates (work@LogicGates), file:${SURELOG_DIR}/tests/GateLevel/dut.sv, line:1:1, endln:20:10 |vpiDefName:work@nand |vpiFullName:work@LogicGates. |vpiPrimType:2 @@ -2068,7 +2068,7 @@ design: (work@LogicGates) |vpiPrimitive: \_gate: work@nor (work@LogicGates.), line:9:6, endln:9:14 |vpiParent: - \_module: work@LogicGates (work@LogicGates), file:${SURELOG_DIR}/tests/GateLevel/dut.sv, line:1:1, endln:20:10 + \_module_inst: work@LogicGates (work@LogicGates), file:${SURELOG_DIR}/tests/GateLevel/dut.sv, line:1:1, endln:20:10 |vpiDefName:work@nor |vpiFullName:work@LogicGates. |vpiPrimType:3 @@ -2116,7 +2116,7 @@ design: (work@LogicGates) |vpiPrimitive: \_gate: work@xor (work@LogicGates.), line:10:6, endln:10:14 |vpiParent: - \_module: work@LogicGates (work@LogicGates), file:${SURELOG_DIR}/tests/GateLevel/dut.sv, line:1:1, endln:20:10 + \_module_inst: work@LogicGates (work@LogicGates), file:${SURELOG_DIR}/tests/GateLevel/dut.sv, line:1:1, endln:20:10 |vpiDefName:work@xor |vpiFullName:work@LogicGates. |vpiPrimType:5 @@ -2164,7 +2164,7 @@ design: (work@LogicGates) |vpiPrimitive: \_gate: work@xnor (work@LogicGates.), line:11:7, endln:11:15 |vpiParent: - \_module: work@LogicGates (work@LogicGates), file:${SURELOG_DIR}/tests/GateLevel/dut.sv, line:1:1, endln:20:10 + \_module_inst: work@LogicGates (work@LogicGates), file:${SURELOG_DIR}/tests/GateLevel/dut.sv, line:1:1, endln:20:10 |vpiDefName:work@xnor |vpiFullName:work@LogicGates. |vpiPrimType:6 @@ -2212,7 +2212,7 @@ design: (work@LogicGates) |vpiPrimitive: \_gate: work@and (work@LogicGates.a1), line:13:14, endln:13:25 |vpiParent: - \_module: work@LogicGates (work@LogicGates), file:${SURELOG_DIR}/tests/GateLevel/dut.sv, line:1:1, endln:20:10 + \_module_inst: work@LogicGates (work@LogicGates), file:${SURELOG_DIR}/tests/GateLevel/dut.sv, line:1:1, endln:20:10 |vpiDefName:work@and |vpiName:a1 |vpiFullName:work@LogicGates.a1 @@ -2267,7 +2267,7 @@ design: (work@LogicGates) |vpiPrimitive: \_gate: work@or (work@LogicGates.a2), line:14:13, endln:14:31 |vpiParent: - \_module: work@LogicGates (work@LogicGates), file:${SURELOG_DIR}/tests/GateLevel/dut.sv, line:1:1, endln:20:10 + \_module_inst: work@LogicGates (work@LogicGates), file:${SURELOG_DIR}/tests/GateLevel/dut.sv, line:1:1, endln:20:10 |vpiDefName:work@or |vpiName:a2 |vpiFullName:work@LogicGates.a2 @@ -2364,7 +2364,7 @@ design: (work@LogicGates) |vpiPrimitive: \_gate: work@nand (work@LogicGates.a3), line:15:25, endln:15:38 |vpiParent: - \_module: work@LogicGates (work@LogicGates), file:${SURELOG_DIR}/tests/GateLevel/dut.sv, line:1:1, endln:20:10 + \_module_inst: work@LogicGates (work@LogicGates), file:${SURELOG_DIR}/tests/GateLevel/dut.sv, line:1:1, endln:20:10 |vpiDefName:work@nand |vpiName:a3 |vpiFullName:work@LogicGates.a3 @@ -2458,7 +2458,7 @@ design: (work@LogicGates) |vpiPrimitive: \_gate: work@bufif0 (work@LogicGates.a4), line:16:21, endln:16:36 |vpiParent: - \_module: work@LogicGates (work@LogicGates), file:${SURELOG_DIR}/tests/GateLevel/dut.sv, line:1:1, endln:20:10 + \_module_inst: work@LogicGates (work@LogicGates), file:${SURELOG_DIR}/tests/GateLevel/dut.sv, line:1:1, endln:20:10 |vpiDefName:work@bufif0 |vpiName:a4 |vpiFullName:work@LogicGates.a4 @@ -2537,7 +2537,7 @@ design: (work@LogicGates) |vpiPrimitive: \_gate: work@bufif0 (work@LogicGates.a5), line:17:33, endln:17:48 |vpiParent: - \_module: work@LogicGates (work@LogicGates), file:${SURELOG_DIR}/tests/GateLevel/dut.sv, line:1:1, endln:20:10 + \_module_inst: work@LogicGates (work@LogicGates), file:${SURELOG_DIR}/tests/GateLevel/dut.sv, line:1:1, endln:20:10 |vpiDefName:work@bufif0 |vpiName:a5 |vpiFullName:work@LogicGates.a5 @@ -2652,7 +2652,7 @@ design: (work@LogicGates) |vpiPrimitive: \_switch_tran: work@pmos (work@LogicGates.a6), line:18:8, endln:18:21 |vpiParent: - \_module: work@LogicGates (work@LogicGates), file:${SURELOG_DIR}/tests/GateLevel/dut.sv, line:1:1, endln:20:10 + \_module_inst: work@LogicGates (work@LogicGates), file:${SURELOG_DIR}/tests/GateLevel/dut.sv, line:1:1, endln:20:10 |vpiDefName:work@pmos |vpiName:a6 |vpiFullName:work@LogicGates.a6 @@ -2701,7 +2701,7 @@ design: (work@LogicGates) |vpiPrimitive: \_gate: work@pullup (work@LogicGates.a7), line:19:10, endln:19:17 |vpiParent: - \_module: work@LogicGates (work@LogicGates), file:${SURELOG_DIR}/tests/GateLevel/dut.sv, line:1:1, endln:20:10 + \_module_inst: work@LogicGates (work@LogicGates), file:${SURELOG_DIR}/tests/GateLevel/dut.sv, line:1:1, endln:20:10 |vpiDefName:work@pullup |vpiName:a7 |vpiFullName:work@LogicGates.a7 diff --git a/tests/Gates/Gates.log b/tests/Gates/Gates.log index ecc604745f..b2aa5c2824 100644 --- a/tests/Gates/Gates.log +++ b/tests/Gates/Gates.log @@ -3162,7 +3162,7 @@ io_decl 11 logic_net 136 logic_typespec 29 logic_var 1 -module 32 +module_inst 32 operation 21 package 2 port 124 @@ -3198,7 +3198,7 @@ io_decl 22 logic_net 136 logic_typespec 29 logic_var 1 -module 32 +module_inst 32 operation 27 package 2 port 128 @@ -3697,7 +3697,7 @@ design: (work@gates) \_int_typespec: |vpiSigned:1 |uhdmallModules: -\_module: work@and_from_nand (work@and_from_nand), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:124:1, endln:143:10 +\_module_inst: work@and_from_nand (work@and_from_nand), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:124:1, endln:143:10 |vpiParent: \_design: (work@gates) |vpiFullName:work@and_from_nand @@ -3705,35 +3705,35 @@ design: (work@gates) |vpiNet: \_logic_net: (work@and_from_nand.X), line:126:5, endln:126:6 |vpiParent: - \_module: work@and_from_nand (work@and_from_nand), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:124:1, endln:143:10 + \_module_inst: work@and_from_nand (work@and_from_nand), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:124:1, endln:143:10 |vpiName:X |vpiFullName:work@and_from_nand.X |vpiNetType:48 |vpiNet: \_logic_net: (work@and_from_nand.Y), line:126:8, endln:126:9 |vpiParent: - \_module: work@and_from_nand (work@and_from_nand), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:124:1, endln:143:10 + \_module_inst: work@and_from_nand (work@and_from_nand), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:124:1, endln:143:10 |vpiName:Y |vpiFullName:work@and_from_nand.Y |vpiNetType:48 |vpiNet: \_logic_net: (work@and_from_nand.F), line:127:6, endln:127:7 |vpiParent: - \_module: work@and_from_nand (work@and_from_nand), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:124:1, endln:143:10 + \_module_inst: work@and_from_nand (work@and_from_nand), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:124:1, endln:143:10 |vpiName:F |vpiFullName:work@and_from_nand.F |vpiNetType:1 |vpiNet: \_logic_net: (work@and_from_nand.W), line:127:9, endln:127:10 |vpiParent: - \_module: work@and_from_nand (work@and_from_nand), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:124:1, endln:143:10 + \_module_inst: work@and_from_nand (work@and_from_nand), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:124:1, endln:143:10 |vpiName:W |vpiFullName:work@and_from_nand.W |vpiNetType:1 |vpiProcess: \_initial: , line:133:1, endln:141:4 |vpiParent: - \_module: work@and_from_nand (work@and_from_nand), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:124:1, endln:143:10 + \_module_inst: work@and_from_nand (work@and_from_nand), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:124:1, endln:143:10 |vpiStmt: \_begin: (work@and_from_nand), line:133:9, endln:141:4 |vpiParent: @@ -3912,7 +3912,7 @@ design: (work@gates) \_delay_control: , line:140:3, endln:140:5 |vpiName:$finish |uhdmallModules: -\_module: work@delay_example (work@delay_example), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:145:1, endln:176:10 +\_module_inst: work@delay_example (work@delay_example), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:145:1, endln:176:10 |vpiParent: \_design: (work@gates) |vpiFullName:work@delay_example @@ -3920,63 +3920,63 @@ design: (work@gates) |vpiNet: \_logic_net: (work@delay_example.out1), line:147:6, endln:147:10 |vpiParent: - \_module: work@delay_example (work@delay_example), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:145:1, endln:176:10 + \_module_inst: work@delay_example (work@delay_example), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:145:1, endln:176:10 |vpiName:out1 |vpiFullName:work@delay_example.out1 |vpiNetType:1 |vpiNet: \_logic_net: (work@delay_example.out2), line:147:11, endln:147:15 |vpiParent: - \_module: work@delay_example (work@delay_example), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:145:1, endln:176:10 + \_module_inst: work@delay_example (work@delay_example), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:145:1, endln:176:10 |vpiName:out2 |vpiFullName:work@delay_example.out2 |vpiNetType:1 |vpiNet: \_logic_net: (work@delay_example.out3), line:147:16, endln:147:20 |vpiParent: - \_module: work@delay_example (work@delay_example), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:145:1, endln:176:10 + \_module_inst: work@delay_example (work@delay_example), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:145:1, endln:176:10 |vpiName:out3 |vpiFullName:work@delay_example.out3 |vpiNetType:1 |vpiNet: \_logic_net: (work@delay_example.out4), line:147:21, endln:147:25 |vpiParent: - \_module: work@delay_example (work@delay_example), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:145:1, endln:176:10 + \_module_inst: work@delay_example (work@delay_example), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:145:1, endln:176:10 |vpiName:out4 |vpiFullName:work@delay_example.out4 |vpiNetType:1 |vpiNet: \_logic_net: (work@delay_example.out5), line:147:26, endln:147:30 |vpiParent: - \_module: work@delay_example (work@delay_example), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:145:1, endln:176:10 + \_module_inst: work@delay_example (work@delay_example), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:145:1, endln:176:10 |vpiName:out5 |vpiFullName:work@delay_example.out5 |vpiNetType:1 |vpiNet: \_logic_net: (work@delay_example.out6), line:147:31, endln:147:35 |vpiParent: - \_module: work@delay_example (work@delay_example), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:145:1, endln:176:10 + \_module_inst: work@delay_example (work@delay_example), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:145:1, endln:176:10 |vpiName:out6 |vpiFullName:work@delay_example.out6 |vpiNetType:1 |vpiNet: \_logic_net: (work@delay_example.b), line:148:5, endln:148:6 |vpiParent: - \_module: work@delay_example (work@delay_example), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:145:1, endln:176:10 + \_module_inst: work@delay_example (work@delay_example), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:145:1, endln:176:10 |vpiName:b |vpiFullName:work@delay_example.b |vpiNetType:48 |vpiNet: \_logic_net: (work@delay_example.c), line:148:7, endln:148:8 |vpiParent: - \_module: work@delay_example (work@delay_example), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:145:1, endln:176:10 + \_module_inst: work@delay_example (work@delay_example), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:145:1, endln:176:10 |vpiName:c |vpiFullName:work@delay_example.c |vpiNetType:48 |vpiProcess: \_initial: , line:164:1, endln:174:4 |vpiParent: - \_module: work@delay_example (work@delay_example), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:145:1, endln:176:10 + \_module_inst: work@delay_example (work@delay_example), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:145:1, endln:176:10 |vpiStmt: \_begin: (work@delay_example), line:164:9, endln:174:4 |vpiParent: @@ -4200,7 +4200,7 @@ design: (work@gates) \_delay_control: , line:173:3, endln:173:6 |vpiName:$finish |uhdmallModules: -\_module: work@dff_from_nand (work@dff_from_nand), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:62:1, endln:83:10 +\_module_inst: work@dff_from_nand (work@dff_from_nand), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:62:1, endln:83:10 |vpiParent: \_design: (work@gates) |vpiFullName:work@dff_from_nand @@ -4208,35 +4208,35 @@ design: (work@gates) |vpiNet: \_logic_net: (work@dff_from_nand.Q), line:63:6, endln:63:7 |vpiParent: - \_module: work@dff_from_nand (work@dff_from_nand), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:62:1, endln:83:10 + \_module_inst: work@dff_from_nand (work@dff_from_nand), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:62:1, endln:83:10 |vpiName:Q |vpiFullName:work@dff_from_nand.Q |vpiNetType:1 |vpiNet: \_logic_net: (work@dff_from_nand.Q_BAR), line:63:8, endln:63:13 |vpiParent: - \_module: work@dff_from_nand (work@dff_from_nand), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:62:1, endln:83:10 + \_module_inst: work@dff_from_nand (work@dff_from_nand), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:62:1, endln:83:10 |vpiName:Q_BAR |vpiFullName:work@dff_from_nand.Q_BAR |vpiNetType:1 |vpiNet: \_logic_net: (work@dff_from_nand.D), line:64:5, endln:64:6 |vpiParent: - \_module: work@dff_from_nand (work@dff_from_nand), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:62:1, endln:83:10 + \_module_inst: work@dff_from_nand (work@dff_from_nand), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:62:1, endln:83:10 |vpiName:D |vpiFullName:work@dff_from_nand.D |vpiNetType:48 |vpiNet: \_logic_net: (work@dff_from_nand.CLK), line:64:7, endln:64:10 |vpiParent: - \_module: work@dff_from_nand (work@dff_from_nand), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:62:1, endln:83:10 + \_module_inst: work@dff_from_nand (work@dff_from_nand), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:62:1, endln:83:10 |vpiName:CLK |vpiFullName:work@dff_from_nand.CLK |vpiNetType:48 |vpiProcess: \_initial: , line:72:1, endln:79:4 |vpiParent: - \_module: work@dff_from_nand (work@dff_from_nand), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:62:1, endln:83:10 + \_module_inst: work@dff_from_nand (work@dff_from_nand), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:62:1, endln:83:10 |vpiStmt: \_begin: (work@dff_from_nand), line:72:9, endln:79:4 |vpiParent: @@ -4398,7 +4398,7 @@ design: (work@gates) |vpiProcess: \_always: , line:81:1, endln:81:22 |vpiParent: - \_module: work@dff_from_nand (work@dff_from_nand), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:62:1, endln:83:10 + \_module_inst: work@dff_from_nand (work@dff_from_nand), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:62:1, endln:83:10 |vpiStmt: \_delay_control: , line:81:8, endln:81:10 |vpiParent: @@ -4433,7 +4433,7 @@ design: (work@gates) \_logic_net: (work@dff_from_nand.CLK), line:64:7, endln:64:10 |vpiAlwaysType:1 |uhdmallModules: -\_module: work@gate_array (work@gate_array), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:230:1, endln:235:10 +\_module_inst: work@gate_array (work@gate_array), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:230:1, endln:235:10 |vpiParent: \_design: (work@gates) |vpiFullName:work@gate_array @@ -4441,26 +4441,26 @@ design: (work@gates) |vpiNet: \_logic_net: (work@gate_array.out), line:232:12, endln:232:15 |vpiParent: - \_module: work@gate_array (work@gate_array), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:230:1, endln:235:10 + \_module_inst: work@gate_array (work@gate_array), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:230:1, endln:235:10 |vpiName:out |vpiFullName:work@gate_array.out |vpiNetType:1 |vpiNet: \_logic_net: (work@gate_array.in1), line:232:17, endln:232:20 |vpiParent: - \_module: work@gate_array (work@gate_array), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:230:1, endln:235:10 + \_module_inst: work@gate_array (work@gate_array), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:230:1, endln:235:10 |vpiName:in1 |vpiFullName:work@gate_array.in1 |vpiNetType:1 |vpiNet: \_logic_net: (work@gate_array.in2), line:232:22, endln:232:25 |vpiParent: - \_module: work@gate_array (work@gate_array), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:230:1, endln:235:10 + \_module_inst: work@gate_array (work@gate_array), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:230:1, endln:235:10 |vpiName:in2 |vpiFullName:work@gate_array.in2 |vpiNetType:1 |uhdmallModules: -\_module: work@gates (work@gates), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:1:1, endln:27:10 +\_module_inst: work@gates (work@gates), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:1:1, endln:27:10 |vpiParent: \_design: (work@gates) |vpiFullName:work@gates @@ -4468,56 +4468,56 @@ design: (work@gates) |vpiNet: \_logic_net: (work@gates.out0), line:3:6, endln:3:10 |vpiParent: - \_module: work@gates (work@gates), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:1:1, endln:27:10 + \_module_inst: work@gates (work@gates), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:1:1, endln:27:10 |vpiName:out0 |vpiFullName:work@gates.out0 |vpiNetType:1 |vpiNet: \_logic_net: (work@gates.out1), line:4:6, endln:4:10 |vpiParent: - \_module: work@gates (work@gates), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:1:1, endln:27:10 + \_module_inst: work@gates (work@gates), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:1:1, endln:27:10 |vpiName:out1 |vpiFullName:work@gates.out1 |vpiNetType:1 |vpiNet: \_logic_net: (work@gates.out2), line:5:6, endln:5:10 |vpiParent: - \_module: work@gates (work@gates), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:1:1, endln:27:10 + \_module_inst: work@gates (work@gates), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:1:1, endln:27:10 |vpiName:out2 |vpiFullName:work@gates.out2 |vpiNetType:1 |vpiNet: \_logic_net: (work@gates.in1), line:6:6, endln:6:9 |vpiParent: - \_module: work@gates (work@gates), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:1:1, endln:27:10 + \_module_inst: work@gates (work@gates), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:1:1, endln:27:10 |vpiName:in1 |vpiFullName:work@gates.in1 |vpiNetType:48 |vpiNet: \_logic_net: (work@gates.in2), line:6:10, endln:6:13 |vpiParent: - \_module: work@gates (work@gates), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:1:1, endln:27:10 + \_module_inst: work@gates (work@gates), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:1:1, endln:27:10 |vpiName:in2 |vpiFullName:work@gates.in2 |vpiNetType:48 |vpiNet: \_logic_net: (work@gates.in3), line:6:14, endln:6:17 |vpiParent: - \_module: work@gates (work@gates), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:1:1, endln:27:10 + \_module_inst: work@gates (work@gates), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:1:1, endln:27:10 |vpiName:in3 |vpiFullName:work@gates.in3 |vpiNetType:48 |vpiNet: \_logic_net: (work@gates.in4), line:6:18, endln:6:21 |vpiParent: - \_module: work@gates (work@gates), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:1:1, endln:27:10 + \_module_inst: work@gates (work@gates), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:1:1, endln:27:10 |vpiName:in4 |vpiFullName:work@gates.in4 |vpiNetType:48 |vpiProcess: \_initial: , line:12:1, endln:25:4 |vpiParent: - \_module: work@gates (work@gates), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:1:1, endln:27:10 + \_module_inst: work@gates (work@gates), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:1:1, endln:27:10 |vpiStmt: \_begin: (work@gates), line:12:9, endln:25:4 |vpiParent: @@ -4799,7 +4799,7 @@ design: (work@gates) \_delay_control: , line:24:3, endln:24:5 |vpiName:$finish |uhdmallModules: -\_module: work@half_adder (work@half_adder), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:222:1, endln:227:10 +\_module_inst: work@half_adder (work@half_adder), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:222:1, endln:227:10 |vpiParent: \_design: (work@gates) |vpiFullName:work@half_adder @@ -4807,33 +4807,33 @@ design: (work@gates) |vpiNet: \_logic_net: (work@half_adder.Sum), line:222:19, endln:222:22 |vpiParent: - \_module: work@half_adder (work@half_adder), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:222:1, endln:227:10 + \_module_inst: work@half_adder (work@half_adder), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:222:1, endln:227:10 |vpiName:Sum |vpiFullName:work@half_adder.Sum |vpiNetType:1 |vpiNet: \_logic_net: (work@half_adder.Carry), line:222:24, endln:222:29 |vpiParent: - \_module: work@half_adder (work@half_adder), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:222:1, endln:227:10 + \_module_inst: work@half_adder (work@half_adder), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:222:1, endln:227:10 |vpiName:Carry |vpiFullName:work@half_adder.Carry |vpiNetType:1 |vpiNet: \_logic_net: (work@half_adder.A), line:222:31, endln:222:32 |vpiParent: - \_module: work@half_adder (work@half_adder), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:222:1, endln:227:10 + \_module_inst: work@half_adder (work@half_adder), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:222:1, endln:227:10 |vpiName:A |vpiFullName:work@half_adder.A |vpiNet: \_logic_net: (work@half_adder.B), line:222:34, endln:222:35 |vpiParent: - \_module: work@half_adder (work@half_adder), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:222:1, endln:227:10 + \_module_inst: work@half_adder (work@half_adder), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:222:1, endln:227:10 |vpiName:B |vpiFullName:work@half_adder.B |vpiPort: \_port: (Sum), line:222:19, endln:222:22 |vpiParent: - \_module: work@half_adder (work@half_adder), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:222:1, endln:227:10 + \_module_inst: work@half_adder (work@half_adder), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:222:1, endln:227:10 |vpiName:Sum |vpiDirection:2 |vpiLowConn: @@ -4845,7 +4845,7 @@ design: (work@gates) |vpiPort: \_port: (Carry), line:222:24, endln:222:29 |vpiParent: - \_module: work@half_adder (work@half_adder), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:222:1, endln:227:10 + \_module_inst: work@half_adder (work@half_adder), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:222:1, endln:227:10 |vpiName:Carry |vpiDirection:2 |vpiLowConn: @@ -4857,7 +4857,7 @@ design: (work@gates) |vpiPort: \_port: (A), line:222:31, endln:222:32 |vpiParent: - \_module: work@half_adder (work@half_adder), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:222:1, endln:227:10 + \_module_inst: work@half_adder (work@half_adder), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:222:1, endln:227:10 |vpiName:A |vpiDirection:1 |vpiLowConn: @@ -4869,7 +4869,7 @@ design: (work@gates) |vpiPort: \_port: (B), line:222:34, endln:222:35 |vpiParent: - \_module: work@half_adder (work@half_adder), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:222:1, endln:227:10 + \_module_inst: work@half_adder (work@half_adder), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:222:1, endln:227:10 |vpiName:B |vpiDirection:1 |vpiLowConn: @@ -4879,7 +4879,7 @@ design: (work@gates) |vpiTypedef: \_logic_typespec: , line:223:8, endln:223:8 |uhdmallModules: -\_module: work@mux_from_gates (work@mux_from_gates), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:85:1, endln:121:10 +\_module_inst: work@mux_from_gates (work@mux_from_gates), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:85:1, endln:121:10 |vpiParent: \_design: (work@gates) |vpiFullName:work@mux_from_gates @@ -4887,56 +4887,56 @@ design: (work@gates) |vpiNet: \_logic_net: (work@mux_from_gates.c0), line:86:5, endln:86:7 |vpiParent: - \_module: work@mux_from_gates (work@mux_from_gates), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:85:1, endln:121:10 + \_module_inst: work@mux_from_gates (work@mux_from_gates), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:85:1, endln:121:10 |vpiName:c0 |vpiFullName:work@mux_from_gates.c0 |vpiNetType:48 |vpiNet: \_logic_net: (work@mux_from_gates.c1), line:86:8, endln:86:10 |vpiParent: - \_module: work@mux_from_gates (work@mux_from_gates), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:85:1, endln:121:10 + \_module_inst: work@mux_from_gates (work@mux_from_gates), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:85:1, endln:121:10 |vpiName:c1 |vpiFullName:work@mux_from_gates.c1 |vpiNetType:48 |vpiNet: \_logic_net: (work@mux_from_gates.c2), line:86:11, endln:86:13 |vpiParent: - \_module: work@mux_from_gates (work@mux_from_gates), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:85:1, endln:121:10 + \_module_inst: work@mux_from_gates (work@mux_from_gates), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:85:1, endln:121:10 |vpiName:c2 |vpiFullName:work@mux_from_gates.c2 |vpiNetType:48 |vpiNet: \_logic_net: (work@mux_from_gates.c3), line:86:14, endln:86:16 |vpiParent: - \_module: work@mux_from_gates (work@mux_from_gates), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:85:1, endln:121:10 + \_module_inst: work@mux_from_gates (work@mux_from_gates), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:85:1, endln:121:10 |vpiName:c3 |vpiFullName:work@mux_from_gates.c3 |vpiNetType:48 |vpiNet: \_logic_net: (work@mux_from_gates.A), line:86:17, endln:86:18 |vpiParent: - \_module: work@mux_from_gates (work@mux_from_gates), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:85:1, endln:121:10 + \_module_inst: work@mux_from_gates (work@mux_from_gates), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:85:1, endln:121:10 |vpiName:A |vpiFullName:work@mux_from_gates.A |vpiNetType:48 |vpiNet: \_logic_net: (work@mux_from_gates.B), line:86:19, endln:86:20 |vpiParent: - \_module: work@mux_from_gates (work@mux_from_gates), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:85:1, endln:121:10 + \_module_inst: work@mux_from_gates (work@mux_from_gates), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:85:1, endln:121:10 |vpiName:B |vpiFullName:work@mux_from_gates.B |vpiNetType:48 |vpiNet: \_logic_net: (work@mux_from_gates.Y), line:87:6, endln:87:7 |vpiParent: - \_module: work@mux_from_gates (work@mux_from_gates), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:85:1, endln:121:10 + \_module_inst: work@mux_from_gates (work@mux_from_gates), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:85:1, endln:121:10 |vpiName:Y |vpiFullName:work@mux_from_gates.Y |vpiNetType:1 |vpiProcess: \_initial: , line:100:1, endln:114:4 |vpiParent: - \_module: work@mux_from_gates (work@mux_from_gates), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:85:1, endln:121:10 + \_module_inst: work@mux_from_gates (work@mux_from_gates), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:85:1, endln:121:10 |vpiStmt: \_begin: (work@mux_from_gates), line:100:9, endln:114:4 |vpiParent: @@ -5237,7 +5237,7 @@ design: (work@gates) |vpiProcess: \_always: , line:116:1, endln:116:20 |vpiParent: - \_module: work@mux_from_gates (work@mux_from_gates), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:85:1, endln:121:10 + \_module_inst: work@mux_from_gates (work@mux_from_gates), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:85:1, endln:121:10 |vpiStmt: \_delay_control: , line:116:8, endln:116:10 |vpiParent: @@ -5274,7 +5274,7 @@ design: (work@gates) |vpiProcess: \_always: , line:117:1, endln:117:20 |vpiParent: - \_module: work@mux_from_gates (work@mux_from_gates), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:85:1, endln:121:10 + \_module_inst: work@mux_from_gates (work@mux_from_gates), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:85:1, endln:121:10 |vpiStmt: \_delay_control: , line:117:8, endln:117:10 |vpiParent: @@ -5311,7 +5311,7 @@ design: (work@gates) |vpiProcess: \_always: , line:118:1, endln:118:20 |vpiParent: - \_module: work@mux_from_gates (work@mux_from_gates), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:85:1, endln:121:10 + \_module_inst: work@mux_from_gates (work@mux_from_gates), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:85:1, endln:121:10 |vpiStmt: \_delay_control: , line:118:8, endln:118:10 |vpiParent: @@ -5348,7 +5348,7 @@ design: (work@gates) |vpiProcess: \_always: , line:119:1, endln:119:20 |vpiParent: - \_module: work@mux_from_gates (work@mux_from_gates), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:85:1, endln:121:10 + \_module_inst: work@mux_from_gates (work@mux_from_gates), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:85:1, endln:121:10 |vpiStmt: \_delay_control: , line:119:8, endln:119:10 |vpiParent: @@ -5383,7 +5383,7 @@ design: (work@gates) \_logic_net: (work@mux_from_gates.c3), line:86:14, endln:86:16 |vpiAlwaysType:1 |uhdmallModules: -\_module: work@n_in_primitive (work@n_in_primitive), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:178:1, endln:206:10 +\_module_inst: work@n_in_primitive (work@n_in_primitive), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:178:1, endln:206:10 |vpiParent: \_design: (work@gates) |vpiFullName:work@n_in_primitive @@ -5391,56 +5391,56 @@ design: (work@gates) |vpiNet: \_logic_net: (work@n_in_primitive.out1), line:180:6, endln:180:10 |vpiParent: - \_module: work@n_in_primitive (work@n_in_primitive), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:178:1, endln:206:10 + \_module_inst: work@n_in_primitive (work@n_in_primitive), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:178:1, endln:206:10 |vpiName:out1 |vpiFullName:work@n_in_primitive.out1 |vpiNetType:1 |vpiNet: \_logic_net: (work@n_in_primitive.out2), line:180:11, endln:180:15 |vpiParent: - \_module: work@n_in_primitive (work@n_in_primitive), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:178:1, endln:206:10 + \_module_inst: work@n_in_primitive (work@n_in_primitive), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:178:1, endln:206:10 |vpiName:out2 |vpiFullName:work@n_in_primitive.out2 |vpiNetType:1 |vpiNet: \_logic_net: (work@n_in_primitive.out3), line:180:16, endln:180:20 |vpiParent: - \_module: work@n_in_primitive (work@n_in_primitive), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:178:1, endln:206:10 + \_module_inst: work@n_in_primitive (work@n_in_primitive), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:178:1, endln:206:10 |vpiName:out3 |vpiFullName:work@n_in_primitive.out3 |vpiNetType:1 |vpiNet: \_logic_net: (work@n_in_primitive.in1), line:181:5, endln:181:8 |vpiParent: - \_module: work@n_in_primitive (work@n_in_primitive), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:178:1, endln:206:10 + \_module_inst: work@n_in_primitive (work@n_in_primitive), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:178:1, endln:206:10 |vpiName:in1 |vpiFullName:work@n_in_primitive.in1 |vpiNetType:48 |vpiNet: \_logic_net: (work@n_in_primitive.in2), line:181:9, endln:181:12 |vpiParent: - \_module: work@n_in_primitive (work@n_in_primitive), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:178:1, endln:206:10 + \_module_inst: work@n_in_primitive (work@n_in_primitive), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:178:1, endln:206:10 |vpiName:in2 |vpiFullName:work@n_in_primitive.in2 |vpiNetType:48 |vpiNet: \_logic_net: (work@n_in_primitive.in3), line:181:13, endln:181:16 |vpiParent: - \_module: work@n_in_primitive (work@n_in_primitive), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:178:1, endln:206:10 + \_module_inst: work@n_in_primitive (work@n_in_primitive), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:178:1, endln:206:10 |vpiName:in3 |vpiFullName:work@n_in_primitive.in3 |vpiNetType:48 |vpiNet: \_logic_net: (work@n_in_primitive.in4), line:181:17, endln:181:20 |vpiParent: - \_module: work@n_in_primitive (work@n_in_primitive), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:178:1, endln:206:10 + \_module_inst: work@n_in_primitive (work@n_in_primitive), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:178:1, endln:206:10 |vpiName:in4 |vpiFullName:work@n_in_primitive.in4 |vpiNetType:48 |vpiProcess: \_initial: , line:191:1, endln:204:4 |vpiParent: - \_module: work@n_in_primitive (work@n_in_primitive), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:178:1, endln:206:10 + \_module_inst: work@n_in_primitive (work@n_in_primitive), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:178:1, endln:206:10 |vpiStmt: \_begin: (work@n_in_primitive), line:191:9, endln:204:4 |vpiParent: @@ -5722,7 +5722,7 @@ design: (work@gates) \_delay_control: , line:203:3, endln:203:5 |vpiName:$finish |uhdmallModules: -\_module: work@n_out_primitive (work@n_out_primitive), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:208:1, endln:220:10 +\_module_inst: work@n_out_primitive (work@n_out_primitive), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:208:1, endln:220:10 |vpiParent: \_design: (work@gates) |vpiFullName:work@n_out_primitive @@ -5730,68 +5730,68 @@ design: (work@gates) |vpiNet: \_logic_net: (work@n_out_primitive.out), line:210:6, endln:210:9 |vpiParent: - \_module: work@n_out_primitive (work@n_out_primitive), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:208:1, endln:220:10 + \_module_inst: work@n_out_primitive (work@n_out_primitive), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:208:1, endln:220:10 |vpiName:out |vpiFullName:work@n_out_primitive.out |vpiNetType:1 |vpiNet: \_logic_net: (work@n_out_primitive.out_0), line:210:10, endln:210:15 |vpiParent: - \_module: work@n_out_primitive (work@n_out_primitive), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:208:1, endln:220:10 + \_module_inst: work@n_out_primitive (work@n_out_primitive), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:208:1, endln:220:10 |vpiName:out_0 |vpiFullName:work@n_out_primitive.out_0 |vpiNetType:1 |vpiNet: \_logic_net: (work@n_out_primitive.out_1), line:210:16, endln:210:21 |vpiParent: - \_module: work@n_out_primitive (work@n_out_primitive), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:208:1, endln:220:10 + \_module_inst: work@n_out_primitive (work@n_out_primitive), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:208:1, endln:220:10 |vpiName:out_1 |vpiFullName:work@n_out_primitive.out_1 |vpiNetType:1 |vpiNet: \_logic_net: (work@n_out_primitive.out_2), line:210:22, endln:210:27 |vpiParent: - \_module: work@n_out_primitive (work@n_out_primitive), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:208:1, endln:220:10 + \_module_inst: work@n_out_primitive (work@n_out_primitive), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:208:1, endln:220:10 |vpiName:out_2 |vpiFullName:work@n_out_primitive.out_2 |vpiNetType:1 |vpiNet: \_logic_net: (work@n_out_primitive.out_3), line:210:28, endln:210:33 |vpiParent: - \_module: work@n_out_primitive (work@n_out_primitive), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:208:1, endln:220:10 + \_module_inst: work@n_out_primitive (work@n_out_primitive), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:208:1, endln:220:10 |vpiName:out_3 |vpiFullName:work@n_out_primitive.out_3 |vpiNetType:1 |vpiNet: \_logic_net: (work@n_out_primitive.out_a), line:210:34, endln:210:39 |vpiParent: - \_module: work@n_out_primitive (work@n_out_primitive), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:208:1, endln:220:10 + \_module_inst: work@n_out_primitive (work@n_out_primitive), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:208:1, endln:220:10 |vpiName:out_a |vpiFullName:work@n_out_primitive.out_a |vpiNetType:1 |vpiNet: \_logic_net: (work@n_out_primitive.out_b), line:210:40, endln:210:45 |vpiParent: - \_module: work@n_out_primitive (work@n_out_primitive), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:208:1, endln:220:10 + \_module_inst: work@n_out_primitive (work@n_out_primitive), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:208:1, endln:220:10 |vpiName:out_b |vpiFullName:work@n_out_primitive.out_b |vpiNetType:1 |vpiNet: \_logic_net: (work@n_out_primitive.out_c), line:210:46, endln:210:51 |vpiParent: - \_module: work@n_out_primitive (work@n_out_primitive), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:208:1, endln:220:10 + \_module_inst: work@n_out_primitive (work@n_out_primitive), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:208:1, endln:220:10 |vpiName:out_c |vpiFullName:work@n_out_primitive.out_c |vpiNetType:1 |vpiNet: \_logic_net: (work@n_out_primitive.in), line:211:6, endln:211:8 |vpiParent: - \_module: work@n_out_primitive (work@n_out_primitive), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:208:1, endln:220:10 + \_module_inst: work@n_out_primitive (work@n_out_primitive), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:208:1, endln:220:10 |vpiName:in |vpiFullName:work@n_out_primitive.in |vpiNetType:1 |uhdmallModules: -\_module: work@switch_primitives (work@switch_primitives), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:52:1, endln:60:10 +\_module_inst: work@switch_primitives (work@switch_primitives), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:52:1, endln:60:10 |vpiParent: \_design: (work@gates) |vpiFullName:work@switch_primitives @@ -5799,47 +5799,47 @@ design: (work@gates) |vpiNet: \_logic_net: (work@switch_primitives.net1), line:54:7, endln:54:11 |vpiParent: - \_module: work@switch_primitives (work@switch_primitives), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:52:1, endln:60:10 + \_module_inst: work@switch_primitives (work@switch_primitives), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:52:1, endln:60:10 |vpiName:net1 |vpiFullName:work@switch_primitives.net1 |vpiNetType:1 |vpiNet: \_logic_net: (work@switch_primitives.net2), line:54:13, endln:54:17 |vpiParent: - \_module: work@switch_primitives (work@switch_primitives), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:52:1, endln:60:10 + \_module_inst: work@switch_primitives (work@switch_primitives), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:52:1, endln:60:10 |vpiName:net2 |vpiFullName:work@switch_primitives.net2 |vpiNetType:1 |vpiNet: \_logic_net: (work@switch_primitives.net3), line:54:19, endln:54:23 |vpiParent: - \_module: work@switch_primitives (work@switch_primitives), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:52:1, endln:60:10 + \_module_inst: work@switch_primitives (work@switch_primitives), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:52:1, endln:60:10 |vpiName:net3 |vpiFullName:work@switch_primitives.net3 |vpiNetType:1 |vpiNet: \_logic_net: (work@switch_primitives.net4), line:55:7, endln:55:11 |vpiParent: - \_module: work@switch_primitives (work@switch_primitives), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:52:1, endln:60:10 + \_module_inst: work@switch_primitives (work@switch_primitives), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:52:1, endln:60:10 |vpiName:net4 |vpiFullName:work@switch_primitives.net4 |vpiNetType:1 |vpiNet: \_logic_net: (work@switch_primitives.net5), line:55:13, endln:55:17 |vpiParent: - \_module: work@switch_primitives (work@switch_primitives), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:52:1, endln:60:10 + \_module_inst: work@switch_primitives (work@switch_primitives), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:52:1, endln:60:10 |vpiName:net5 |vpiFullName:work@switch_primitives.net5 |vpiNetType:1 |vpiNet: \_logic_net: (work@switch_primitives.net6), line:55:19, endln:55:23 |vpiParent: - \_module: work@switch_primitives (work@switch_primitives), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:52:1, endln:60:10 + \_module_inst: work@switch_primitives (work@switch_primitives), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:52:1, endln:60:10 |vpiName:net6 |vpiFullName:work@switch_primitives.net6 |vpiNetType:1 |uhdmallModules: -\_module: work@transmission_gates (work@transmission_gates), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:29:1, endln:50:10 +\_module_inst: work@transmission_gates (work@transmission_gates), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:29:1, endln:50:10 |vpiParent: \_design: (work@gates) |vpiFullName:work@transmission_gates @@ -5847,42 +5847,42 @@ design: (work@gates) |vpiNet: \_logic_net: (work@transmission_gates.data_enable_low), line:31:5, endln:31:20 |vpiParent: - \_module: work@transmission_gates (work@transmission_gates), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:29:1, endln:50:10 + \_module_inst: work@transmission_gates (work@transmission_gates), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:29:1, endln:50:10 |vpiName:data_enable_low |vpiFullName:work@transmission_gates.data_enable_low |vpiNetType:48 |vpiNet: \_logic_net: (work@transmission_gates.in), line:31:22, endln:31:24 |vpiParent: - \_module: work@transmission_gates (work@transmission_gates), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:29:1, endln:50:10 + \_module_inst: work@transmission_gates (work@transmission_gates), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:29:1, endln:50:10 |vpiName:in |vpiFullName:work@transmission_gates.in |vpiNetType:48 |vpiNet: \_logic_net: (work@transmission_gates.data_bus), line:32:6, endln:32:14 |vpiParent: - \_module: work@transmission_gates (work@transmission_gates), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:29:1, endln:50:10 + \_module_inst: work@transmission_gates (work@transmission_gates), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:29:1, endln:50:10 |vpiName:data_bus |vpiFullName:work@transmission_gates.data_bus |vpiNetType:1 |vpiNet: \_logic_net: (work@transmission_gates.out1), line:32:16, endln:32:20 |vpiParent: - \_module: work@transmission_gates (work@transmission_gates), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:29:1, endln:50:10 + \_module_inst: work@transmission_gates (work@transmission_gates), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:29:1, endln:50:10 |vpiName:out1 |vpiFullName:work@transmission_gates.out1 |vpiNetType:1 |vpiNet: \_logic_net: (work@transmission_gates.out2), line:32:22, endln:32:26 |vpiParent: - \_module: work@transmission_gates (work@transmission_gates), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:29:1, endln:50:10 + \_module_inst: work@transmission_gates (work@transmission_gates), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:29:1, endln:50:10 |vpiName:out2 |vpiFullName:work@transmission_gates.out2 |vpiNetType:1 |vpiProcess: \_initial: , line:38:1, endln:46:4 |vpiParent: - \_module: work@transmission_gates (work@transmission_gates), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:29:1, endln:50:10 + \_module_inst: work@transmission_gates (work@transmission_gates), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:29:1, endln:50:10 |vpiStmt: \_begin: (work@transmission_gates), line:38:9, endln:46:4 |vpiParent: @@ -6030,7 +6030,7 @@ design: (work@gates) |vpiProcess: \_always: , line:48:1, endln:48:20 |vpiParent: - \_module: work@transmission_gates (work@transmission_gates), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:29:1, endln:50:10 + \_module_inst: work@transmission_gates (work@transmission_gates), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:29:1, endln:50:10 |vpiStmt: \_delay_control: , line:48:8, endln:48:10 |vpiParent: @@ -6065,14 +6065,14 @@ design: (work@gates) \_logic_net: (work@transmission_gates.in), line:31:22, endln:31:24 |vpiAlwaysType:1 |uhdmtopModules: -\_module: work@gates (work@gates), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:1:1, endln:27:10 +\_module_inst: work@gates (work@gates), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:1:1, endln:27:10 |vpiName:work@gates |vpiDefName:work@gates |vpiTop:1 |vpiNet: \_logic_net: (work@gates.out0), line:3:6, endln:3:10 |vpiParent: - \_module: work@gates (work@gates), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:1:1, endln:27:10 + \_module_inst: work@gates (work@gates), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:1:1, endln:27:10 |vpiTypespec: \_logic_typespec: , line:3:1, endln:3:5 |vpiName:out0 @@ -6081,7 +6081,7 @@ design: (work@gates) |vpiNet: \_logic_net: (work@gates.out1), line:4:6, endln:4:10 |vpiParent: - \_module: work@gates (work@gates), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:1:1, endln:27:10 + \_module_inst: work@gates (work@gates), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:1:1, endln:27:10 |vpiTypespec: \_logic_typespec: , line:4:1, endln:4:5 |vpiName:out1 @@ -6090,7 +6090,7 @@ design: (work@gates) |vpiNet: \_logic_net: (work@gates.out2), line:5:6, endln:5:10 |vpiParent: - \_module: work@gates (work@gates), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:1:1, endln:27:10 + \_module_inst: work@gates (work@gates), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:1:1, endln:27:10 |vpiTypespec: \_logic_typespec: , line:5:1, endln:5:5 |vpiName:out2 @@ -6099,7 +6099,7 @@ design: (work@gates) |vpiNet: \_logic_net: (work@gates.in1), line:6:6, endln:6:9 |vpiParent: - \_module: work@gates (work@gates), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:1:1, endln:27:10 + \_module_inst: work@gates (work@gates), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:1:1, endln:27:10 |vpiTypespec: \_logic_typespec: , line:6:1, endln:6:4 |vpiName:in1 @@ -6108,7 +6108,7 @@ design: (work@gates) |vpiNet: \_logic_net: (work@gates.in2), line:6:10, endln:6:13 |vpiParent: - \_module: work@gates (work@gates), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:1:1, endln:27:10 + \_module_inst: work@gates (work@gates), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:1:1, endln:27:10 |vpiTypespec: \_logic_typespec: , line:6:1, endln:6:4 |vpiName:in2 @@ -6117,7 +6117,7 @@ design: (work@gates) |vpiNet: \_logic_net: (work@gates.in3), line:6:14, endln:6:17 |vpiParent: - \_module: work@gates (work@gates), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:1:1, endln:27:10 + \_module_inst: work@gates (work@gates), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:1:1, endln:27:10 |vpiTypespec: \_logic_typespec: , line:6:1, endln:6:4 |vpiName:in3 @@ -6126,7 +6126,7 @@ design: (work@gates) |vpiNet: \_logic_net: (work@gates.in4), line:6:18, endln:6:21 |vpiParent: - \_module: work@gates (work@gates), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:1:1, endln:27:10 + \_module_inst: work@gates (work@gates), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:1:1, endln:27:10 |vpiTypespec: \_logic_typespec: , line:6:1, endln:6:4 |vpiName:in4 @@ -6136,7 +6136,7 @@ design: (work@gates) |vpiProcess: \_initial: , line:12:1, endln:25:4 |vpiParent: - \_module: work@gates (work@gates), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:1:1, endln:27:10 + \_module_inst: work@gates (work@gates), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:1:1, endln:27:10 |vpiStmt: \_begin: (work@gates), line:12:9, endln:25:4 |vpiParent: @@ -6366,7 +6366,7 @@ design: (work@gates) |vpiPrimitive: \_gate: work@not (work@gates.U1), line:8:5, endln:8:17 |vpiParent: - \_module: work@gates (work@gates), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:1:1, endln:27:10 + \_module_inst: work@gates (work@gates), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:1:1, endln:27:10 |vpiDefName:work@not |vpiName:U1 |vpiFullName:work@gates.U1 @@ -6401,7 +6401,7 @@ design: (work@gates) |vpiPrimitive: \_gate: work@and (work@gates.U2), line:9:5, endln:9:29 |vpiParent: - \_module: work@gates (work@gates), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:1:1, endln:27:10 + \_module_inst: work@gates (work@gates), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:1:1, endln:27:10 |vpiDefName:work@and |vpiName:U2 |vpiFullName:work@gates.U2 @@ -6478,7 +6478,7 @@ design: (work@gates) |vpiPrimitive: \_gate: work@xor (work@gates.U3), line:10:5, endln:10:25 |vpiParent: - \_module: work@gates (work@gates), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:1:1, endln:27:10 + \_module_inst: work@gates (work@gates), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:1:1, endln:27:10 |vpiDefName:work@xor |vpiName:U3 |vpiFullName:work@gates.U3 @@ -6539,14 +6539,14 @@ design: (work@gates) |vpiActual: \_logic_net: (work@gates.in3), line:6:14, endln:6:17 |uhdmtopModules: -\_module: work@transmission_gates (work@transmission_gates), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:29:1, endln:50:10 +\_module_inst: work@transmission_gates (work@transmission_gates), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:29:1, endln:50:10 |vpiName:work@transmission_gates |vpiDefName:work@transmission_gates |vpiTop:1 |vpiNet: \_logic_net: (work@transmission_gates.data_enable_low), line:31:5, endln:31:20 |vpiParent: - \_module: work@transmission_gates (work@transmission_gates), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:29:1, endln:50:10 + \_module_inst: work@transmission_gates (work@transmission_gates), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:29:1, endln:50:10 |vpiTypespec: \_logic_typespec: , line:31:1, endln:31:4 |vpiName:data_enable_low @@ -6555,7 +6555,7 @@ design: (work@gates) |vpiNet: \_logic_net: (work@transmission_gates.in), line:31:22, endln:31:24 |vpiParent: - \_module: work@transmission_gates (work@transmission_gates), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:29:1, endln:50:10 + \_module_inst: work@transmission_gates (work@transmission_gates), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:29:1, endln:50:10 |vpiTypespec: \_logic_typespec: , line:31:1, endln:31:4 |vpiName:in @@ -6564,7 +6564,7 @@ design: (work@gates) |vpiNet: \_logic_net: (work@transmission_gates.data_bus), line:32:6, endln:32:14 |vpiParent: - \_module: work@transmission_gates (work@transmission_gates), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:29:1, endln:50:10 + \_module_inst: work@transmission_gates (work@transmission_gates), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:29:1, endln:50:10 |vpiTypespec: \_logic_typespec: , line:32:1, endln:32:5 |vpiName:data_bus @@ -6573,7 +6573,7 @@ design: (work@gates) |vpiNet: \_logic_net: (work@transmission_gates.out1), line:32:16, endln:32:20 |vpiParent: - \_module: work@transmission_gates (work@transmission_gates), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:29:1, endln:50:10 + \_module_inst: work@transmission_gates (work@transmission_gates), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:29:1, endln:50:10 |vpiTypespec: \_logic_typespec: , line:32:1, endln:32:5 |vpiName:out1 @@ -6582,7 +6582,7 @@ design: (work@gates) |vpiNet: \_logic_net: (work@transmission_gates.out2), line:32:22, endln:32:26 |vpiParent: - \_module: work@transmission_gates (work@transmission_gates), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:29:1, endln:50:10 + \_module_inst: work@transmission_gates (work@transmission_gates), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:29:1, endln:50:10 |vpiTypespec: \_logic_typespec: , line:32:1, endln:32:5 |vpiName:out2 @@ -6592,7 +6592,7 @@ design: (work@gates) |vpiProcess: \_initial: , line:38:1, endln:46:4 |vpiParent: - \_module: work@transmission_gates (work@transmission_gates), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:29:1, endln:50:10 + \_module_inst: work@transmission_gates (work@transmission_gates), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:29:1, endln:50:10 |vpiStmt: \_begin: (work@transmission_gates), line:38:9, endln:46:4 |vpiParent: @@ -6716,7 +6716,7 @@ design: (work@gates) |vpiProcess: \_always: , line:48:1, endln:48:20 |vpiParent: - \_module: work@transmission_gates (work@transmission_gates), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:29:1, endln:50:10 + \_module_inst: work@transmission_gates (work@transmission_gates), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:29:1, endln:50:10 |vpiStmt: \_delay_control: , line:48:8, endln:48:10 |vpiParent: @@ -6753,7 +6753,7 @@ design: (work@gates) |vpiPrimitive: \_gate: work@bufif0 (work@transmission_gates.U1), line:34:8, endln:34:40 |vpiParent: - \_module: work@transmission_gates (work@transmission_gates), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:29:1, endln:50:10 + \_module_inst: work@transmission_gates (work@transmission_gates), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:29:1, endln:50:10 |vpiDefName:work@bufif0 |vpiName:U1 |vpiFullName:work@transmission_gates.U1 @@ -6802,7 +6802,7 @@ design: (work@gates) |vpiPrimitive: \_gate: work@buf (work@transmission_gates.U2), line:35:6, endln:35:17 |vpiParent: - \_module: work@transmission_gates (work@transmission_gates), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:29:1, endln:50:10 + \_module_inst: work@transmission_gates (work@transmission_gates), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:29:1, endln:50:10 |vpiDefName:work@buf |vpiName:U2 |vpiFullName:work@transmission_gates.U2 @@ -6837,7 +6837,7 @@ design: (work@gates) |vpiPrimitive: \_gate: work@not (work@transmission_gates.U3), line:36:5, endln:36:16 |vpiParent: - \_module: work@transmission_gates (work@transmission_gates), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:29:1, endln:50:10 + \_module_inst: work@transmission_gates (work@transmission_gates), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:29:1, endln:50:10 |vpiDefName:work@not |vpiName:U3 |vpiFullName:work@transmission_gates.U3 @@ -6870,14 +6870,14 @@ design: (work@gates) |vpiActual: \_logic_net: (work@transmission_gates.in), line:31:22, endln:31:24 |uhdmtopModules: -\_module: work@switch_primitives (work@switch_primitives), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:52:1, endln:60:10 +\_module_inst: work@switch_primitives (work@switch_primitives), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:52:1, endln:60:10 |vpiName:work@switch_primitives |vpiDefName:work@switch_primitives |vpiTop:1 |vpiNet: \_logic_net: (work@switch_primitives.net1), line:54:7, endln:54:11 |vpiParent: - \_module: work@switch_primitives (work@switch_primitives), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:52:1, endln:60:10 + \_module_inst: work@switch_primitives (work@switch_primitives), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:52:1, endln:60:10 |vpiTypespec: \_logic_typespec: , line:54:1, endln:54:5 |vpiName:net1 @@ -6886,7 +6886,7 @@ design: (work@gates) |vpiNet: \_logic_net: (work@switch_primitives.net2), line:54:13, endln:54:17 |vpiParent: - \_module: work@switch_primitives (work@switch_primitives), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:52:1, endln:60:10 + \_module_inst: work@switch_primitives (work@switch_primitives), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:52:1, endln:60:10 |vpiTypespec: \_logic_typespec: , line:54:1, endln:54:5 |vpiName:net2 @@ -6895,7 +6895,7 @@ design: (work@gates) |vpiNet: \_logic_net: (work@switch_primitives.net3), line:54:19, endln:54:23 |vpiParent: - \_module: work@switch_primitives (work@switch_primitives), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:52:1, endln:60:10 + \_module_inst: work@switch_primitives (work@switch_primitives), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:52:1, endln:60:10 |vpiTypespec: \_logic_typespec: , line:54:1, endln:54:5 |vpiName:net3 @@ -6904,7 +6904,7 @@ design: (work@gates) |vpiNet: \_logic_net: (work@switch_primitives.net4), line:55:7, endln:55:11 |vpiParent: - \_module: work@switch_primitives (work@switch_primitives), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:52:1, endln:60:10 + \_module_inst: work@switch_primitives (work@switch_primitives), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:52:1, endln:60:10 |vpiTypespec: \_logic_typespec: , line:55:1, endln:55:5 |vpiName:net4 @@ -6913,7 +6913,7 @@ design: (work@gates) |vpiNet: \_logic_net: (work@switch_primitives.net5), line:55:13, endln:55:17 |vpiParent: - \_module: work@switch_primitives (work@switch_primitives), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:52:1, endln:60:10 + \_module_inst: work@switch_primitives (work@switch_primitives), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:52:1, endln:60:10 |vpiTypespec: \_logic_typespec: , line:55:1, endln:55:5 |vpiName:net5 @@ -6922,7 +6922,7 @@ design: (work@gates) |vpiNet: \_logic_net: (work@switch_primitives.net6), line:55:19, endln:55:23 |vpiParent: - \_module: work@switch_primitives (work@switch_primitives), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:52:1, endln:60:10 + \_module_inst: work@switch_primitives (work@switch_primitives), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:52:1, endln:60:10 |vpiTypespec: \_logic_typespec: , line:55:1, endln:55:5 |vpiName:net6 @@ -6932,7 +6932,7 @@ design: (work@gates) |vpiPrimitive: \_switch_tran: work@tranif0 (work@switch_primitives.my_gate1), line:57:9, endln:57:36 |vpiParent: - \_module: work@switch_primitives (work@switch_primitives), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:52:1, endln:60:10 + \_module_inst: work@switch_primitives (work@switch_primitives), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:52:1, endln:60:10 |vpiDefName:work@tranif0 |vpiName:my_gate1 |vpiFullName:work@switch_primitives.my_gate1 @@ -6981,7 +6981,7 @@ design: (work@gates) |vpiPrimitive: \_switch_tran: work@rtranif1 (work@switch_primitives.my_gate2), line:58:10, endln:58:37 |vpiParent: - \_module: work@switch_primitives (work@switch_primitives), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:52:1, endln:60:10 + \_module_inst: work@switch_primitives (work@switch_primitives), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:52:1, endln:60:10 |vpiDefName:work@rtranif1 |vpiName:my_gate2 |vpiFullName:work@switch_primitives.my_gate2 @@ -7028,14 +7028,14 @@ design: (work@gates) |vpiActual: \_logic_net: (work@switch_primitives.net6), line:55:19, endln:55:23 |uhdmtopModules: -\_module: work@dff_from_nand (work@dff_from_nand), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:62:1, endln:83:10 +\_module_inst: work@dff_from_nand (work@dff_from_nand), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:62:1, endln:83:10 |vpiName:work@dff_from_nand |vpiDefName:work@dff_from_nand |vpiTop:1 |vpiNet: \_logic_net: (work@dff_from_nand.Q), line:63:6, endln:63:7 |vpiParent: - \_module: work@dff_from_nand (work@dff_from_nand), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:62:1, endln:83:10 + \_module_inst: work@dff_from_nand (work@dff_from_nand), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:62:1, endln:83:10 |vpiTypespec: \_logic_typespec: , line:63:1, endln:63:5 |vpiName:Q @@ -7044,7 +7044,7 @@ design: (work@gates) |vpiNet: \_logic_net: (work@dff_from_nand.Q_BAR), line:63:8, endln:63:13 |vpiParent: - \_module: work@dff_from_nand (work@dff_from_nand), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:62:1, endln:83:10 + \_module_inst: work@dff_from_nand (work@dff_from_nand), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:62:1, endln:83:10 |vpiTypespec: \_logic_typespec: , line:63:1, endln:63:5 |vpiName:Q_BAR @@ -7053,7 +7053,7 @@ design: (work@gates) |vpiNet: \_logic_net: (work@dff_from_nand.D), line:64:5, endln:64:6 |vpiParent: - \_module: work@dff_from_nand (work@dff_from_nand), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:62:1, endln:83:10 + \_module_inst: work@dff_from_nand (work@dff_from_nand), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:62:1, endln:83:10 |vpiTypespec: \_logic_typespec: , line:64:1, endln:64:4 |vpiName:D @@ -7062,7 +7062,7 @@ design: (work@gates) |vpiNet: \_logic_net: (work@dff_from_nand.CLK), line:64:7, endln:64:10 |vpiParent: - \_module: work@dff_from_nand (work@dff_from_nand), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:62:1, endln:83:10 + \_module_inst: work@dff_from_nand (work@dff_from_nand), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:62:1, endln:83:10 |vpiTypespec: \_logic_typespec: , line:64:1, endln:64:4 |vpiName:CLK @@ -7071,14 +7071,14 @@ design: (work@gates) |vpiNet: \_logic_net: (work@dff_from_nand.X), line:66:10, endln:66:11 |vpiParent: - \_module: work@dff_from_nand (work@dff_from_nand), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:62:1, endln:83:10 + \_module_inst: work@dff_from_nand (work@dff_from_nand), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:62:1, endln:83:10 |vpiName:X |vpiFullName:work@dff_from_nand.X |vpiNetType:1 |vpiNet: \_logic_net: (work@dff_from_nand.Y), line:67:10, endln:67:11 |vpiParent: - \_module: work@dff_from_nand (work@dff_from_nand), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:62:1, endln:83:10 + \_module_inst: work@dff_from_nand (work@dff_from_nand), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:62:1, endln:83:10 |vpiName:Y |vpiFullName:work@dff_from_nand.Y |vpiNetType:1 @@ -7086,7 +7086,7 @@ design: (work@gates) |vpiProcess: \_initial: , line:72:1, endln:79:4 |vpiParent: - \_module: work@dff_from_nand (work@dff_from_nand), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:62:1, endln:83:10 + \_module_inst: work@dff_from_nand (work@dff_from_nand), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:62:1, endln:83:10 |vpiStmt: \_begin: (work@dff_from_nand), line:72:9, endln:79:4 |vpiParent: @@ -7218,7 +7218,7 @@ design: (work@gates) |vpiProcess: \_always: , line:81:1, endln:81:22 |vpiParent: - \_module: work@dff_from_nand (work@dff_from_nand), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:62:1, endln:83:10 + \_module_inst: work@dff_from_nand (work@dff_from_nand), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:62:1, endln:83:10 |vpiStmt: \_delay_control: , line:81:8, endln:81:10 |vpiParent: @@ -7255,7 +7255,7 @@ design: (work@gates) |vpiPrimitive: \_gate: work@nand (work@dff_from_nand.U1), line:66:6, endln:66:18 |vpiParent: - \_module: work@dff_from_nand (work@dff_from_nand), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:62:1, endln:83:10 + \_module_inst: work@dff_from_nand (work@dff_from_nand), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:62:1, endln:83:10 |vpiDefName:work@nand |vpiName:U1 |vpiFullName:work@dff_from_nand.U1 @@ -7304,7 +7304,7 @@ design: (work@gates) |vpiPrimitive: \_gate: work@nand (work@dff_from_nand.U2), line:67:6, endln:67:18 |vpiParent: - \_module: work@dff_from_nand (work@dff_from_nand), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:62:1, endln:83:10 + \_module_inst: work@dff_from_nand (work@dff_from_nand), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:62:1, endln:83:10 |vpiDefName:work@nand |vpiName:U2 |vpiFullName:work@dff_from_nand.U2 @@ -7353,7 +7353,7 @@ design: (work@gates) |vpiPrimitive: \_gate: work@nand (work@dff_from_nand.U3), line:68:6, endln:68:20 |vpiParent: - \_module: work@dff_from_nand (work@dff_from_nand), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:62:1, endln:83:10 + \_module_inst: work@dff_from_nand (work@dff_from_nand), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:62:1, endln:83:10 |vpiDefName:work@nand |vpiName:U3 |vpiFullName:work@dff_from_nand.U3 @@ -7402,7 +7402,7 @@ design: (work@gates) |vpiPrimitive: \_gate: work@nand (work@dff_from_nand.U4), line:69:6, endln:69:20 |vpiParent: - \_module: work@dff_from_nand (work@dff_from_nand), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:62:1, endln:83:10 + \_module_inst: work@dff_from_nand (work@dff_from_nand), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:62:1, endln:83:10 |vpiDefName:work@nand |vpiName:U4 |vpiFullName:work@dff_from_nand.U4 @@ -7449,14 +7449,14 @@ design: (work@gates) |vpiActual: \_logic_net: (work@dff_from_nand.Y), line:67:10, endln:67:11 |uhdmtopModules: -\_module: work@mux_from_gates (work@mux_from_gates), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:85:1, endln:121:10 +\_module_inst: work@mux_from_gates (work@mux_from_gates), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:85:1, endln:121:10 |vpiName:work@mux_from_gates |vpiDefName:work@mux_from_gates |vpiTop:1 |vpiNet: \_logic_net: (work@mux_from_gates.c0), line:86:5, endln:86:7 |vpiParent: - \_module: work@mux_from_gates (work@mux_from_gates), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:85:1, endln:121:10 + \_module_inst: work@mux_from_gates (work@mux_from_gates), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:85:1, endln:121:10 |vpiTypespec: \_logic_typespec: , line:86:1, endln:86:4 |vpiName:c0 @@ -7465,7 +7465,7 @@ design: (work@gates) |vpiNet: \_logic_net: (work@mux_from_gates.c1), line:86:8, endln:86:10 |vpiParent: - \_module: work@mux_from_gates (work@mux_from_gates), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:85:1, endln:121:10 + \_module_inst: work@mux_from_gates (work@mux_from_gates), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:85:1, endln:121:10 |vpiTypespec: \_logic_typespec: , line:86:1, endln:86:4 |vpiName:c1 @@ -7474,7 +7474,7 @@ design: (work@gates) |vpiNet: \_logic_net: (work@mux_from_gates.c2), line:86:11, endln:86:13 |vpiParent: - \_module: work@mux_from_gates (work@mux_from_gates), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:85:1, endln:121:10 + \_module_inst: work@mux_from_gates (work@mux_from_gates), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:85:1, endln:121:10 |vpiTypespec: \_logic_typespec: , line:86:1, endln:86:4 |vpiName:c2 @@ -7483,7 +7483,7 @@ design: (work@gates) |vpiNet: \_logic_net: (work@mux_from_gates.c3), line:86:14, endln:86:16 |vpiParent: - \_module: work@mux_from_gates (work@mux_from_gates), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:85:1, endln:121:10 + \_module_inst: work@mux_from_gates (work@mux_from_gates), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:85:1, endln:121:10 |vpiTypespec: \_logic_typespec: , line:86:1, endln:86:4 |vpiName:c3 @@ -7492,7 +7492,7 @@ design: (work@gates) |vpiNet: \_logic_net: (work@mux_from_gates.A), line:86:17, endln:86:18 |vpiParent: - \_module: work@mux_from_gates (work@mux_from_gates), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:85:1, endln:121:10 + \_module_inst: work@mux_from_gates (work@mux_from_gates), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:85:1, endln:121:10 |vpiTypespec: \_logic_typespec: , line:86:1, endln:86:4 |vpiName:A @@ -7501,7 +7501,7 @@ design: (work@gates) |vpiNet: \_logic_net: (work@mux_from_gates.B), line:86:19, endln:86:20 |vpiParent: - \_module: work@mux_from_gates (work@mux_from_gates), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:85:1, endln:121:10 + \_module_inst: work@mux_from_gates (work@mux_from_gates), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:85:1, endln:121:10 |vpiTypespec: \_logic_typespec: , line:86:1, endln:86:4 |vpiName:B @@ -7510,7 +7510,7 @@ design: (work@gates) |vpiNet: \_logic_net: (work@mux_from_gates.Y), line:87:6, endln:87:7 |vpiParent: - \_module: work@mux_from_gates (work@mux_from_gates), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:85:1, endln:121:10 + \_module_inst: work@mux_from_gates (work@mux_from_gates), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:85:1, endln:121:10 |vpiTypespec: \_logic_typespec: , line:87:1, endln:87:5 |vpiName:Y @@ -7519,42 +7519,42 @@ design: (work@gates) |vpiNet: \_logic_net: (work@mux_from_gates.a_inv), line:89:6, endln:89:11 |vpiParent: - \_module: work@mux_from_gates (work@mux_from_gates), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:85:1, endln:121:10 + \_module_inst: work@mux_from_gates (work@mux_from_gates), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:85:1, endln:121:10 |vpiName:a_inv |vpiFullName:work@mux_from_gates.a_inv |vpiNetType:1 |vpiNet: \_logic_net: (work@mux_from_gates.b_inv), line:90:6, endln:90:11 |vpiParent: - \_module: work@mux_from_gates (work@mux_from_gates), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:85:1, endln:121:10 + \_module_inst: work@mux_from_gates (work@mux_from_gates), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:85:1, endln:121:10 |vpiName:b_inv |vpiFullName:work@mux_from_gates.b_inv |vpiNetType:1 |vpiNet: \_logic_net: (work@mux_from_gates.y0), line:92:6, endln:92:8 |vpiParent: - \_module: work@mux_from_gates (work@mux_from_gates), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:85:1, endln:121:10 + \_module_inst: work@mux_from_gates (work@mux_from_gates), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:85:1, endln:121:10 |vpiName:y0 |vpiFullName:work@mux_from_gates.y0 |vpiNetType:1 |vpiNet: \_logic_net: (work@mux_from_gates.y1), line:93:6, endln:93:8 |vpiParent: - \_module: work@mux_from_gates (work@mux_from_gates), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:85:1, endln:121:10 + \_module_inst: work@mux_from_gates (work@mux_from_gates), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:85:1, endln:121:10 |vpiName:y1 |vpiFullName:work@mux_from_gates.y1 |vpiNetType:1 |vpiNet: \_logic_net: (work@mux_from_gates.y2), line:94:6, endln:94:8 |vpiParent: - \_module: work@mux_from_gates (work@mux_from_gates), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:85:1, endln:121:10 + \_module_inst: work@mux_from_gates (work@mux_from_gates), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:85:1, endln:121:10 |vpiName:y2 |vpiFullName:work@mux_from_gates.y2 |vpiNetType:1 |vpiNet: \_logic_net: (work@mux_from_gates.y3), line:95:6, endln:95:8 |vpiParent: - \_module: work@mux_from_gates (work@mux_from_gates), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:85:1, endln:121:10 + \_module_inst: work@mux_from_gates (work@mux_from_gates), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:85:1, endln:121:10 |vpiName:y3 |vpiFullName:work@mux_from_gates.y3 |vpiNetType:1 @@ -7562,7 +7562,7 @@ design: (work@gates) |vpiProcess: \_initial: , line:100:1, endln:114:4 |vpiParent: - \_module: work@mux_from_gates (work@mux_from_gates), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:85:1, endln:121:10 + \_module_inst: work@mux_from_gates (work@mux_from_gates), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:85:1, endln:121:10 |vpiStmt: \_begin: (work@mux_from_gates), line:100:9, endln:114:4 |vpiParent: @@ -7803,7 +7803,7 @@ design: (work@gates) |vpiProcess: \_always: , line:116:1, endln:116:20 |vpiParent: - \_module: work@mux_from_gates (work@mux_from_gates), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:85:1, endln:121:10 + \_module_inst: work@mux_from_gates (work@mux_from_gates), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:85:1, endln:121:10 |vpiStmt: \_delay_control: , line:116:8, endln:116:10 |vpiParent: @@ -7840,7 +7840,7 @@ design: (work@gates) |vpiProcess: \_always: , line:117:1, endln:117:20 |vpiParent: - \_module: work@mux_from_gates (work@mux_from_gates), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:85:1, endln:121:10 + \_module_inst: work@mux_from_gates (work@mux_from_gates), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:85:1, endln:121:10 |vpiStmt: \_delay_control: , line:117:8, endln:117:10 |vpiParent: @@ -7877,7 +7877,7 @@ design: (work@gates) |vpiProcess: \_always: , line:118:1, endln:118:20 |vpiParent: - \_module: work@mux_from_gates (work@mux_from_gates), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:85:1, endln:121:10 + \_module_inst: work@mux_from_gates (work@mux_from_gates), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:85:1, endln:121:10 |vpiStmt: \_delay_control: , line:118:8, endln:118:10 |vpiParent: @@ -7914,7 +7914,7 @@ design: (work@gates) |vpiProcess: \_always: , line:119:1, endln:119:20 |vpiParent: - \_module: work@mux_from_gates (work@mux_from_gates), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:85:1, endln:121:10 + \_module_inst: work@mux_from_gates (work@mux_from_gates), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:85:1, endln:121:10 |vpiStmt: \_delay_control: , line:119:8, endln:119:10 |vpiParent: @@ -7951,7 +7951,7 @@ design: (work@gates) |vpiPrimitive: \_gate: work@not (work@mux_from_gates.), line:89:5, endln:89:15 |vpiParent: - \_module: work@mux_from_gates (work@mux_from_gates), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:85:1, endln:121:10 + \_module_inst: work@mux_from_gates (work@mux_from_gates), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:85:1, endln:121:10 |vpiDefName:work@not |vpiFullName:work@mux_from_gates. |vpiPrimType:8 @@ -7985,7 +7985,7 @@ design: (work@gates) |vpiPrimitive: \_gate: work@not (work@mux_from_gates.), line:90:5, endln:90:15 |vpiParent: - \_module: work@mux_from_gates (work@mux_from_gates), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:85:1, endln:121:10 + \_module_inst: work@mux_from_gates (work@mux_from_gates), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:85:1, endln:121:10 |vpiDefName:work@not |vpiFullName:work@mux_from_gates. |vpiPrimType:8 @@ -8019,7 +8019,7 @@ design: (work@gates) |vpiPrimitive: \_gate: work@and (work@mux_from_gates.), line:92:5, endln:92:24 |vpiParent: - \_module: work@mux_from_gates (work@mux_from_gates), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:85:1, endln:121:10 + \_module_inst: work@mux_from_gates (work@mux_from_gates), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:85:1, endln:121:10 |vpiDefName:work@and |vpiFullName:work@mux_from_gates. |vpiPrimType:1 @@ -8081,7 +8081,7 @@ design: (work@gates) |vpiPrimitive: \_gate: work@and (work@mux_from_gates.), line:93:5, endln:93:20 |vpiParent: - \_module: work@mux_from_gates (work@mux_from_gates), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:85:1, endln:121:10 + \_module_inst: work@mux_from_gates (work@mux_from_gates), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:85:1, endln:121:10 |vpiDefName:work@and |vpiFullName:work@mux_from_gates. |vpiPrimType:1 @@ -8143,7 +8143,7 @@ design: (work@gates) |vpiPrimitive: \_gate: work@and (work@mux_from_gates.), line:94:5, endln:94:20 |vpiParent: - \_module: work@mux_from_gates (work@mux_from_gates), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:85:1, endln:121:10 + \_module_inst: work@mux_from_gates (work@mux_from_gates), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:85:1, endln:121:10 |vpiDefName:work@and |vpiFullName:work@mux_from_gates. |vpiPrimType:1 @@ -8205,7 +8205,7 @@ design: (work@gates) |vpiPrimitive: \_gate: work@and (work@mux_from_gates.), line:95:5, endln:95:16 |vpiParent: - \_module: work@mux_from_gates (work@mux_from_gates), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:85:1, endln:121:10 + \_module_inst: work@mux_from_gates (work@mux_from_gates), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:85:1, endln:121:10 |vpiDefName:work@and |vpiFullName:work@mux_from_gates. |vpiPrimType:1 @@ -8267,7 +8267,7 @@ design: (work@gates) |vpiPrimitive: \_gate: work@or (work@mux_from_gates.), line:97:4, endln:97:20 |vpiParent: - \_module: work@mux_from_gates (work@mux_from_gates), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:85:1, endln:121:10 + \_module_inst: work@mux_from_gates (work@mux_from_gates), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:85:1, endln:121:10 |vpiDefName:work@or |vpiFullName:work@mux_from_gates. |vpiPrimType:4 @@ -8341,14 +8341,14 @@ design: (work@gates) |vpiActual: \_logic_net: (work@mux_from_gates.y3), line:95:6, endln:95:8 |uhdmtopModules: -\_module: work@and_from_nand (work@and_from_nand), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:124:1, endln:143:10 +\_module_inst: work@and_from_nand (work@and_from_nand), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:124:1, endln:143:10 |vpiName:work@and_from_nand |vpiDefName:work@and_from_nand |vpiTop:1 |vpiNet: \_logic_net: (work@and_from_nand.X), line:126:5, endln:126:6 |vpiParent: - \_module: work@and_from_nand (work@and_from_nand), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:124:1, endln:143:10 + \_module_inst: work@and_from_nand (work@and_from_nand), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:124:1, endln:143:10 |vpiTypespec: \_logic_typespec: , line:126:1, endln:126:4 |vpiName:X @@ -8357,7 +8357,7 @@ design: (work@gates) |vpiNet: \_logic_net: (work@and_from_nand.Y), line:126:8, endln:126:9 |vpiParent: - \_module: work@and_from_nand (work@and_from_nand), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:124:1, endln:143:10 + \_module_inst: work@and_from_nand (work@and_from_nand), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:124:1, endln:143:10 |vpiTypespec: \_logic_typespec: , line:126:1, endln:126:4 |vpiName:Y @@ -8366,7 +8366,7 @@ design: (work@gates) |vpiNet: \_logic_net: (work@and_from_nand.F), line:127:6, endln:127:7 |vpiParent: - \_module: work@and_from_nand (work@and_from_nand), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:124:1, endln:143:10 + \_module_inst: work@and_from_nand (work@and_from_nand), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:124:1, endln:143:10 |vpiTypespec: \_logic_typespec: , line:127:1, endln:127:5 |vpiName:F @@ -8375,7 +8375,7 @@ design: (work@gates) |vpiNet: \_logic_net: (work@and_from_nand.W), line:127:9, endln:127:10 |vpiParent: - \_module: work@and_from_nand (work@and_from_nand), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:124:1, endln:143:10 + \_module_inst: work@and_from_nand (work@and_from_nand), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:124:1, endln:143:10 |vpiTypespec: \_logic_typespec: , line:127:1, endln:127:5 |vpiName:W @@ -8385,7 +8385,7 @@ design: (work@gates) |vpiProcess: \_initial: , line:133:1, endln:141:4 |vpiParent: - \_module: work@and_from_nand (work@and_from_nand), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:124:1, endln:143:10 + \_module_inst: work@and_from_nand (work@and_from_nand), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:124:1, endln:143:10 |vpiStmt: \_begin: (work@and_from_nand), line:133:9, endln:141:4 |vpiParent: @@ -8530,7 +8530,7 @@ design: (work@gates) |vpiPrimitive: \_gate: work@nand (work@and_from_nand.U1), line:129:6, endln:129:16 |vpiParent: - \_module: work@and_from_nand (work@and_from_nand), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:124:1, endln:143:10 + \_module_inst: work@and_from_nand (work@and_from_nand), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:124:1, endln:143:10 |vpiDefName:work@nand |vpiName:U1 |vpiFullName:work@and_from_nand.U1 @@ -8579,7 +8579,7 @@ design: (work@gates) |vpiPrimitive: \_gate: work@nand (work@and_from_nand.U2), line:130:6, endln:130:17 |vpiParent: - \_module: work@and_from_nand (work@and_from_nand), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:124:1, endln:143:10 + \_module_inst: work@and_from_nand (work@and_from_nand), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:124:1, endln:143:10 |vpiDefName:work@nand |vpiName:U2 |vpiFullName:work@and_from_nand.U2 @@ -8626,14 +8626,14 @@ design: (work@gates) |vpiActual: \_logic_net: (work@and_from_nand.W), line:127:9, endln:127:10 |uhdmtopModules: -\_module: work@delay_example (work@delay_example), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:145:1, endln:176:10 +\_module_inst: work@delay_example (work@delay_example), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:145:1, endln:176:10 |vpiName:work@delay_example |vpiDefName:work@delay_example |vpiTop:1 |vpiNet: \_logic_net: (work@delay_example.out1), line:147:6, endln:147:10 |vpiParent: - \_module: work@delay_example (work@delay_example), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:145:1, endln:176:10 + \_module_inst: work@delay_example (work@delay_example), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:145:1, endln:176:10 |vpiTypespec: \_logic_typespec: , line:147:1, endln:147:5 |vpiName:out1 @@ -8642,7 +8642,7 @@ design: (work@gates) |vpiNet: \_logic_net: (work@delay_example.out2), line:147:11, endln:147:15 |vpiParent: - \_module: work@delay_example (work@delay_example), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:145:1, endln:176:10 + \_module_inst: work@delay_example (work@delay_example), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:145:1, endln:176:10 |vpiTypespec: \_logic_typespec: , line:147:1, endln:147:5 |vpiName:out2 @@ -8651,7 +8651,7 @@ design: (work@gates) |vpiNet: \_logic_net: (work@delay_example.out3), line:147:16, endln:147:20 |vpiParent: - \_module: work@delay_example (work@delay_example), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:145:1, endln:176:10 + \_module_inst: work@delay_example (work@delay_example), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:145:1, endln:176:10 |vpiTypespec: \_logic_typespec: , line:147:1, endln:147:5 |vpiName:out3 @@ -8660,7 +8660,7 @@ design: (work@gates) |vpiNet: \_logic_net: (work@delay_example.out4), line:147:21, endln:147:25 |vpiParent: - \_module: work@delay_example (work@delay_example), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:145:1, endln:176:10 + \_module_inst: work@delay_example (work@delay_example), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:145:1, endln:176:10 |vpiTypespec: \_logic_typespec: , line:147:1, endln:147:5 |vpiName:out4 @@ -8669,7 +8669,7 @@ design: (work@gates) |vpiNet: \_logic_net: (work@delay_example.out5), line:147:26, endln:147:30 |vpiParent: - \_module: work@delay_example (work@delay_example), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:145:1, endln:176:10 + \_module_inst: work@delay_example (work@delay_example), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:145:1, endln:176:10 |vpiTypespec: \_logic_typespec: , line:147:1, endln:147:5 |vpiName:out5 @@ -8678,7 +8678,7 @@ design: (work@gates) |vpiNet: \_logic_net: (work@delay_example.out6), line:147:31, endln:147:35 |vpiParent: - \_module: work@delay_example (work@delay_example), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:145:1, endln:176:10 + \_module_inst: work@delay_example (work@delay_example), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:145:1, endln:176:10 |vpiTypespec: \_logic_typespec: , line:147:1, endln:147:5 |vpiName:out6 @@ -8687,7 +8687,7 @@ design: (work@gates) |vpiNet: \_logic_net: (work@delay_example.b), line:148:5, endln:148:6 |vpiParent: - \_module: work@delay_example (work@delay_example), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:145:1, endln:176:10 + \_module_inst: work@delay_example (work@delay_example), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:145:1, endln:176:10 |vpiTypespec: \_logic_typespec: , line:148:1, endln:148:4 |vpiName:b @@ -8696,7 +8696,7 @@ design: (work@gates) |vpiNet: \_logic_net: (work@delay_example.c), line:148:7, endln:148:8 |vpiParent: - \_module: work@delay_example (work@delay_example), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:145:1, endln:176:10 + \_module_inst: work@delay_example (work@delay_example), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:145:1, endln:176:10 |vpiTypespec: \_logic_typespec: , line:148:1, endln:148:4 |vpiName:c @@ -8706,7 +8706,7 @@ design: (work@gates) |vpiProcess: \_initial: , line:164:1, endln:174:4 |vpiParent: - \_module: work@delay_example (work@delay_example), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:145:1, endln:176:10 + \_module_inst: work@delay_example (work@delay_example), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:145:1, endln:176:10 |vpiStmt: \_begin: (work@delay_example), line:164:9, endln:174:4 |vpiParent: @@ -8896,7 +8896,7 @@ design: (work@gates) |vpiPrimitive: \_gate: work@or (work@delay_example.), line:151:38, endln:151:48 |vpiParent: - \_module: work@delay_example (work@delay_example), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:145:1, endln:176:10 + \_module_inst: work@delay_example (work@delay_example), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:145:1, endln:176:10 |vpiDefName:work@or |vpiFullName:work@delay_example. |vpiPrimType:4 @@ -8950,7 +8950,7 @@ design: (work@gates) |vpiPrimitive: \_gate: work@and (work@delay_example.u_and), line:153:29, endln:153:48 |vpiParent: - \_module: work@delay_example (work@delay_example), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:145:1, endln:176:10 + \_module_inst: work@delay_example (work@delay_example), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:145:1, endln:176:10 |vpiDefName:work@and |vpiName:u_and |vpiFullName:work@delay_example.u_and @@ -9020,7 +9020,7 @@ design: (work@gates) |vpiPrimitive: \_gate: work@bufif1 (work@delay_example.u_nor), line:155:32, endln:155:51 |vpiParent: - \_module: work@delay_example (work@delay_example), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:145:1, endln:176:10 + \_module_inst: work@delay_example (work@delay_example), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:145:1, endln:176:10 |vpiDefName:work@bufif1 |vpiName:u_nor |vpiFullName:work@delay_example.u_nor @@ -9099,7 +9099,7 @@ design: (work@gates) |vpiPrimitive: \_gate: work@nand (work@delay_example.u_nand), line:157:29, endln:157:48 |vpiParent: - \_module: work@delay_example (work@delay_example), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:145:1, endln:176:10 + \_module_inst: work@delay_example (work@delay_example), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:145:1, endln:176:10 |vpiDefName:work@nand |vpiName:u_nand |vpiFullName:work@delay_example.u_nand @@ -9169,7 +9169,7 @@ design: (work@gates) |vpiPrimitive: \_gate: work@buf (work@delay_example.u_buf), line:159:29, endln:159:46 |vpiParent: - \_module: work@delay_example (work@delay_example), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:145:1, endln:176:10 + \_module_inst: work@delay_example (work@delay_example), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:145:1, endln:176:10 |vpiDefName:work@buf |vpiName:u_buf |vpiFullName:work@delay_example.u_buf @@ -9249,7 +9249,7 @@ design: (work@gates) |vpiPrimitive: \_gate: work@notif1 (work@delay_example.u_notif1), line:161:29, endln:161:48 |vpiParent: - \_module: work@delay_example (work@delay_example), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:145:1, endln:176:10 + \_module_inst: work@delay_example (work@delay_example), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:145:1, endln:176:10 |vpiDefName:work@notif1 |vpiName:u_notif1 |vpiFullName:work@delay_example.u_notif1 @@ -9362,14 +9362,14 @@ design: (work@gates) |vpiActual: \_logic_net: (work@delay_example.c), line:148:7, endln:148:8 |uhdmtopModules: -\_module: work@n_in_primitive (work@n_in_primitive), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:178:1, endln:206:10 +\_module_inst: work@n_in_primitive (work@n_in_primitive), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:178:1, endln:206:10 |vpiName:work@n_in_primitive |vpiDefName:work@n_in_primitive |vpiTop:1 |vpiNet: \_logic_net: (work@n_in_primitive.out1), line:180:6, endln:180:10 |vpiParent: - \_module: work@n_in_primitive (work@n_in_primitive), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:178:1, endln:206:10 + \_module_inst: work@n_in_primitive (work@n_in_primitive), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:178:1, endln:206:10 |vpiTypespec: \_logic_typespec: , line:180:1, endln:180:5 |vpiName:out1 @@ -9378,7 +9378,7 @@ design: (work@gates) |vpiNet: \_logic_net: (work@n_in_primitive.out2), line:180:11, endln:180:15 |vpiParent: - \_module: work@n_in_primitive (work@n_in_primitive), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:178:1, endln:206:10 + \_module_inst: work@n_in_primitive (work@n_in_primitive), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:178:1, endln:206:10 |vpiTypespec: \_logic_typespec: , line:180:1, endln:180:5 |vpiName:out2 @@ -9387,7 +9387,7 @@ design: (work@gates) |vpiNet: \_logic_net: (work@n_in_primitive.out3), line:180:16, endln:180:20 |vpiParent: - \_module: work@n_in_primitive (work@n_in_primitive), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:178:1, endln:206:10 + \_module_inst: work@n_in_primitive (work@n_in_primitive), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:178:1, endln:206:10 |vpiTypespec: \_logic_typespec: , line:180:1, endln:180:5 |vpiName:out3 @@ -9396,7 +9396,7 @@ design: (work@gates) |vpiNet: \_logic_net: (work@n_in_primitive.in1), line:181:5, endln:181:8 |vpiParent: - \_module: work@n_in_primitive (work@n_in_primitive), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:178:1, endln:206:10 + \_module_inst: work@n_in_primitive (work@n_in_primitive), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:178:1, endln:206:10 |vpiTypespec: \_logic_typespec: , line:181:1, endln:181:4 |vpiName:in1 @@ -9405,7 +9405,7 @@ design: (work@gates) |vpiNet: \_logic_net: (work@n_in_primitive.in2), line:181:9, endln:181:12 |vpiParent: - \_module: work@n_in_primitive (work@n_in_primitive), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:178:1, endln:206:10 + \_module_inst: work@n_in_primitive (work@n_in_primitive), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:178:1, endln:206:10 |vpiTypespec: \_logic_typespec: , line:181:1, endln:181:4 |vpiName:in2 @@ -9414,7 +9414,7 @@ design: (work@gates) |vpiNet: \_logic_net: (work@n_in_primitive.in3), line:181:13, endln:181:16 |vpiParent: - \_module: work@n_in_primitive (work@n_in_primitive), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:178:1, endln:206:10 + \_module_inst: work@n_in_primitive (work@n_in_primitive), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:178:1, endln:206:10 |vpiTypespec: \_logic_typespec: , line:181:1, endln:181:4 |vpiName:in3 @@ -9423,7 +9423,7 @@ design: (work@gates) |vpiNet: \_logic_net: (work@n_in_primitive.in4), line:181:17, endln:181:20 |vpiParent: - \_module: work@n_in_primitive (work@n_in_primitive), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:178:1, endln:206:10 + \_module_inst: work@n_in_primitive (work@n_in_primitive), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:178:1, endln:206:10 |vpiTypespec: \_logic_typespec: , line:181:1, endln:181:4 |vpiName:in4 @@ -9433,7 +9433,7 @@ design: (work@gates) |vpiProcess: \_initial: , line:191:1, endln:204:4 |vpiParent: - \_module: work@n_in_primitive (work@n_in_primitive), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:178:1, endln:206:10 + \_module_inst: work@n_in_primitive (work@n_in_primitive), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:178:1, endln:206:10 |vpiStmt: \_begin: (work@n_in_primitive), line:191:9, endln:204:4 |vpiParent: @@ -9663,7 +9663,7 @@ design: (work@gates) |vpiPrimitive: \_gate: work@and (work@n_in_primitive.u_and1), line:184:5, endln:184:28 |vpiParent: - \_module: work@n_in_primitive (work@n_in_primitive), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:178:1, endln:206:10 + \_module_inst: work@n_in_primitive (work@n_in_primitive), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:178:1, endln:206:10 |vpiDefName:work@and |vpiName:u_and1 |vpiFullName:work@n_in_primitive.u_and1 @@ -9712,7 +9712,7 @@ design: (work@gates) |vpiPrimitive: \_gate: work@and (work@n_in_primitive.u_and2), line:186:5, endln:186:38 |vpiParent: - \_module: work@n_in_primitive (work@n_in_primitive), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:178:1, endln:206:10 + \_module_inst: work@n_in_primitive (work@n_in_primitive), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:178:1, endln:206:10 |vpiDefName:work@and |vpiName:u_and2 |vpiFullName:work@n_in_primitive.u_and2 @@ -9789,7 +9789,7 @@ design: (work@gates) |vpiPrimitive: \_gate: work@xnor (work@n_in_primitive.u_xnor1), line:188:6, endln:188:35 |vpiParent: - \_module: work@n_in_primitive (work@n_in_primitive), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:178:1, endln:206:10 + \_module_inst: work@n_in_primitive (work@n_in_primitive), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:178:1, endln:206:10 |vpiDefName:work@xnor |vpiName:u_xnor1 |vpiFullName:work@n_in_primitive.u_xnor1 @@ -9850,14 +9850,14 @@ design: (work@gates) |vpiActual: \_logic_net: (work@n_in_primitive.in3), line:181:13, endln:181:16 |uhdmtopModules: -\_module: work@n_out_primitive (work@n_out_primitive), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:208:1, endln:220:10 +\_module_inst: work@n_out_primitive (work@n_out_primitive), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:208:1, endln:220:10 |vpiName:work@n_out_primitive |vpiDefName:work@n_out_primitive |vpiTop:1 |vpiNet: \_logic_net: (work@n_out_primitive.out), line:210:6, endln:210:9 |vpiParent: - \_module: work@n_out_primitive (work@n_out_primitive), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:208:1, endln:220:10 + \_module_inst: work@n_out_primitive (work@n_out_primitive), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:208:1, endln:220:10 |vpiTypespec: \_logic_typespec: , line:210:1, endln:210:5 |vpiName:out @@ -9866,7 +9866,7 @@ design: (work@gates) |vpiNet: \_logic_net: (work@n_out_primitive.out_0), line:210:10, endln:210:15 |vpiParent: - \_module: work@n_out_primitive (work@n_out_primitive), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:208:1, endln:220:10 + \_module_inst: work@n_out_primitive (work@n_out_primitive), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:208:1, endln:220:10 |vpiTypespec: \_logic_typespec: , line:210:1, endln:210:5 |vpiName:out_0 @@ -9875,7 +9875,7 @@ design: (work@gates) |vpiNet: \_logic_net: (work@n_out_primitive.out_1), line:210:16, endln:210:21 |vpiParent: - \_module: work@n_out_primitive (work@n_out_primitive), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:208:1, endln:220:10 + \_module_inst: work@n_out_primitive (work@n_out_primitive), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:208:1, endln:220:10 |vpiTypespec: \_logic_typespec: , line:210:1, endln:210:5 |vpiName:out_1 @@ -9884,7 +9884,7 @@ design: (work@gates) |vpiNet: \_logic_net: (work@n_out_primitive.out_2), line:210:22, endln:210:27 |vpiParent: - \_module: work@n_out_primitive (work@n_out_primitive), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:208:1, endln:220:10 + \_module_inst: work@n_out_primitive (work@n_out_primitive), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:208:1, endln:220:10 |vpiTypespec: \_logic_typespec: , line:210:1, endln:210:5 |vpiName:out_2 @@ -9893,7 +9893,7 @@ design: (work@gates) |vpiNet: \_logic_net: (work@n_out_primitive.out_3), line:210:28, endln:210:33 |vpiParent: - \_module: work@n_out_primitive (work@n_out_primitive), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:208:1, endln:220:10 + \_module_inst: work@n_out_primitive (work@n_out_primitive), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:208:1, endln:220:10 |vpiTypespec: \_logic_typespec: , line:210:1, endln:210:5 |vpiName:out_3 @@ -9902,7 +9902,7 @@ design: (work@gates) |vpiNet: \_logic_net: (work@n_out_primitive.out_a), line:210:34, endln:210:39 |vpiParent: - \_module: work@n_out_primitive (work@n_out_primitive), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:208:1, endln:220:10 + \_module_inst: work@n_out_primitive (work@n_out_primitive), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:208:1, endln:220:10 |vpiTypespec: \_logic_typespec: , line:210:1, endln:210:5 |vpiName:out_a @@ -9911,7 +9911,7 @@ design: (work@gates) |vpiNet: \_logic_net: (work@n_out_primitive.out_b), line:210:40, endln:210:45 |vpiParent: - \_module: work@n_out_primitive (work@n_out_primitive), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:208:1, endln:220:10 + \_module_inst: work@n_out_primitive (work@n_out_primitive), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:208:1, endln:220:10 |vpiTypespec: \_logic_typespec: , line:210:1, endln:210:5 |vpiName:out_b @@ -9920,7 +9920,7 @@ design: (work@gates) |vpiNet: \_logic_net: (work@n_out_primitive.out_c), line:210:46, endln:210:51 |vpiParent: - \_module: work@n_out_primitive (work@n_out_primitive), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:208:1, endln:220:10 + \_module_inst: work@n_out_primitive (work@n_out_primitive), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:208:1, endln:220:10 |vpiTypespec: \_logic_typespec: , line:210:1, endln:210:5 |vpiName:out_c @@ -9929,7 +9929,7 @@ design: (work@gates) |vpiNet: \_logic_net: (work@n_out_primitive.in), line:211:6, endln:211:8 |vpiParent: - \_module: work@n_out_primitive (work@n_out_primitive), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:208:1, endln:220:10 + \_module_inst: work@n_out_primitive (work@n_out_primitive), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:208:1, endln:220:10 |vpiTypespec: \_logic_typespec: , line:211:1, endln:211:5 |vpiName:in @@ -9939,7 +9939,7 @@ design: (work@gates) |vpiPrimitive: \_gate: work@buf (work@n_out_primitive.u_buf0), line:214:5, endln:214:20 |vpiParent: - \_module: work@n_out_primitive (work@n_out_primitive), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:208:1, endln:220:10 + \_module_inst: work@n_out_primitive (work@n_out_primitive), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:208:1, endln:220:10 |vpiDefName:work@buf |vpiName:u_buf0 |vpiFullName:work@n_out_primitive.u_buf0 @@ -9974,7 +9974,7 @@ design: (work@gates) |vpiPrimitive: \_gate: work@buf (work@n_out_primitive.u_buf1), line:216:5, endln:216:44 |vpiParent: - \_module: work@n_out_primitive (work@n_out_primitive), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:208:1, endln:220:10 + \_module_inst: work@n_out_primitive (work@n_out_primitive), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:208:1, endln:220:10 |vpiDefName:work@buf |vpiName:u_buf1 |vpiFullName:work@n_out_primitive.u_buf1 @@ -10051,7 +10051,7 @@ design: (work@gates) |vpiPrimitive: \_gate: work@not (work@n_out_primitive.u_not0), line:218:5, endln:218:37 |vpiParent: - \_module: work@n_out_primitive (work@n_out_primitive), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:208:1, endln:220:10 + \_module_inst: work@n_out_primitive (work@n_out_primitive), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:208:1, endln:220:10 |vpiDefName:work@not |vpiName:u_not0 |vpiFullName:work@n_out_primitive.u_not0 @@ -10112,14 +10112,14 @@ design: (work@gates) |vpiActual: \_logic_net: (work@n_out_primitive.in), line:211:6, endln:211:8 |uhdmtopModules: -\_module: work@half_adder (work@half_adder), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:222:1, endln:227:10 +\_module_inst: work@half_adder (work@half_adder), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:222:1, endln:227:10 |vpiName:work@half_adder |vpiDefName:work@half_adder |vpiTop:1 |vpiNet: \_logic_net: (work@half_adder.Sum), line:222:19, endln:222:22 |vpiParent: - \_module: work@half_adder (work@half_adder), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:222:1, endln:227:10 + \_module_inst: work@half_adder (work@half_adder), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:222:1, endln:227:10 |vpiTypespec: \_logic_typespec: , line:224:9, endln:224:13 |vpiName:Sum @@ -10128,7 +10128,7 @@ design: (work@gates) |vpiNet: \_logic_net: (work@half_adder.Carry), line:222:24, endln:222:29 |vpiParent: - \_module: work@half_adder (work@half_adder), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:222:1, endln:227:10 + \_module_inst: work@half_adder (work@half_adder), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:222:1, endln:227:10 |vpiTypespec: \_logic_typespec: , line:224:9, endln:224:13 |vpiName:Carry @@ -10137,7 +10137,7 @@ design: (work@gates) |vpiNet: \_logic_net: (work@half_adder.A), line:222:31, endln:222:32 |vpiParent: - \_module: work@half_adder (work@half_adder), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:222:1, endln:227:10 + \_module_inst: work@half_adder (work@half_adder), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:222:1, endln:227:10 |vpiTypespec: \_logic_typespec: , line:223:8, endln:223:8 |vpiName:A @@ -10145,7 +10145,7 @@ design: (work@gates) |vpiNet: \_logic_net: (work@half_adder.B), line:222:34, endln:222:35 |vpiParent: - \_module: work@half_adder (work@half_adder), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:222:1, endln:227:10 + \_module_inst: work@half_adder (work@half_adder), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:222:1, endln:227:10 |vpiTypespec: \_logic_typespec: , line:223:8, endln:223:8 |vpiName:B @@ -10154,7 +10154,7 @@ design: (work@gates) |vpiPort: \_port: (Sum), line:222:19, endln:222:22 |vpiParent: - \_module: work@half_adder (work@half_adder), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:222:1, endln:227:10 + \_module_inst: work@half_adder (work@half_adder), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:222:1, endln:227:10 |vpiName:Sum |vpiDirection:2 |vpiLowConn: @@ -10168,11 +10168,11 @@ design: (work@gates) |vpiTypedef: \_logic_typespec: , line:224:9, endln:224:13 |vpiInstance: - \_module: work@half_adder (work@half_adder), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:222:1, endln:227:10 + \_module_inst: work@half_adder (work@half_adder), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:222:1, endln:227:10 |vpiPort: \_port: (Carry), line:222:24, endln:222:29 |vpiParent: - \_module: work@half_adder (work@half_adder), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:222:1, endln:227:10 + \_module_inst: work@half_adder (work@half_adder), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:222:1, endln:227:10 |vpiName:Carry |vpiDirection:2 |vpiLowConn: @@ -10186,11 +10186,11 @@ design: (work@gates) |vpiTypedef: \_logic_typespec: , line:224:9, endln:224:13 |vpiInstance: - \_module: work@half_adder (work@half_adder), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:222:1, endln:227:10 + \_module_inst: work@half_adder (work@half_adder), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:222:1, endln:227:10 |vpiPort: \_port: (A), line:222:31, endln:222:32 |vpiParent: - \_module: work@half_adder (work@half_adder), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:222:1, endln:227:10 + \_module_inst: work@half_adder (work@half_adder), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:222:1, endln:227:10 |vpiName:A |vpiDirection:1 |vpiLowConn: @@ -10204,11 +10204,11 @@ design: (work@gates) |vpiTypedef: \_logic_typespec: , line:223:8, endln:223:8 |vpiInstance: - \_module: work@half_adder (work@half_adder), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:222:1, endln:227:10 + \_module_inst: work@half_adder (work@half_adder), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:222:1, endln:227:10 |vpiPort: \_port: (B), line:222:34, endln:222:35 |vpiParent: - \_module: work@half_adder (work@half_adder), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:222:1, endln:227:10 + \_module_inst: work@half_adder (work@half_adder), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:222:1, endln:227:10 |vpiName:B |vpiDirection:1 |vpiLowConn: @@ -10222,11 +10222,11 @@ design: (work@gates) |vpiTypedef: \_logic_typespec: , line:223:8, endln:223:8 |vpiInstance: - \_module: work@half_adder (work@half_adder), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:222:1, endln:227:10 + \_module_inst: work@half_adder (work@half_adder), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:222:1, endln:227:10 |vpiPrimitive: \_gate: work@xor (work@half_adder.), line:225:12, endln:225:23 |vpiParent: - \_module: work@half_adder (work@half_adder), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:222:1, endln:227:10 + \_module_inst: work@half_adder (work@half_adder), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:222:1, endln:227:10 |vpiDefName:work@xor |vpiFullName:work@half_adder. |vpiPrimType:5 @@ -10280,7 +10280,7 @@ design: (work@gates) |vpiPrimitive: \_gate: work@and (work@half_adder.), line:226:12, endln:226:25 |vpiParent: - \_module: work@half_adder (work@half_adder), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:222:1, endln:227:10 + \_module_inst: work@half_adder (work@half_adder), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:222:1, endln:227:10 |vpiDefName:work@and |vpiFullName:work@half_adder. |vpiPrimType:1 @@ -10332,14 +10332,14 @@ design: (work@gates) |vpiActual: \_logic_net: (work@half_adder.B), line:222:34, endln:222:35 |uhdmtopModules: -\_module: work@gate_array (work@gate_array), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:230:1, endln:235:10 +\_module_inst: work@gate_array (work@gate_array), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:230:1, endln:235:10 |vpiName:work@gate_array |vpiDefName:work@gate_array |vpiTop:1 |vpiNet: \_logic_net: (work@gate_array.out), line:232:12, endln:232:15 |vpiParent: - \_module: work@gate_array (work@gate_array), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:230:1, endln:235:10 + \_module_inst: work@gate_array (work@gate_array), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:230:1, endln:235:10 |vpiTypespec: \_logic_typespec: , line:232:1, endln:232:11 |vpiRange: @@ -10366,7 +10366,7 @@ design: (work@gates) |vpiNet: \_logic_net: (work@gate_array.in1), line:232:17, endln:232:20 |vpiParent: - \_module: work@gate_array (work@gate_array), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:230:1, endln:235:10 + \_module_inst: work@gate_array (work@gate_array), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:230:1, endln:235:10 |vpiTypespec: \_logic_typespec: , line:232:1, endln:232:11 |vpiName:in1 @@ -10375,7 +10375,7 @@ design: (work@gates) |vpiNet: \_logic_net: (work@gate_array.in2), line:232:22, endln:232:25 |vpiParent: - \_module: work@gate_array (work@gate_array), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:230:1, endln:235:10 + \_module_inst: work@gate_array (work@gate_array), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:230:1, endln:235:10 |vpiTypespec: \_logic_typespec: , line:232:1, endln:232:11 |vpiName:in2 @@ -10407,7 +10407,7 @@ design: (work@gates) |vpiPrimitive: \_gate: work@nand (work@gate_array.n_gate), line:233:6, endln:233:34 |vpiParent: - \_module: work@gate_array (work@gate_array), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:230:1, endln:235:10 + \_module_inst: work@gate_array (work@gate_array), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:230:1, endln:235:10 |vpiDefName:work@nand |vpiName:n_gate |vpiFullName:work@gate_array.n_gate diff --git a/tests/GenBlock/GenBlock.log b/tests/GenBlock/GenBlock.log index f5ef4c3f34..d8be7ab42e 100644 --- a/tests/GenBlock/GenBlock.log +++ b/tests/GenBlock/GenBlock.log @@ -163,7 +163,7 @@ design 1 gen_scope 2 gen_scope_array 2 int_typespec 2 -module 7 +module_inst 7 operation 3 param_assign 6 parameter 6 @@ -178,7 +178,7 @@ design 1 gen_scope 3 gen_scope_array 3 int_typespec 2 -module 8 +module_inst 8 operation 3 param_assign 6 parameter 6 @@ -198,20 +198,20 @@ design: (work@axi) |vpiElaborated:1 |vpiName:work@axi |uhdmallModules: -\_module: work@GOOD (work@GOOD), file:${SURELOG_DIR}/tests/GenBlock/dut.sv, line:1:1, endln:2:10 +\_module_inst: work@GOOD (work@GOOD), file:${SURELOG_DIR}/tests/GenBlock/dut.sv, line:1:1, endln:2:10 |vpiParent: \_design: (work@axi) |vpiFullName:work@GOOD |vpiDefName:work@GOOD |uhdmallModules: -\_module: work@axi (work@axi), file:${SURELOG_DIR}/tests/GenBlock/dut.sv, line:4:1, endln:22:10 +\_module_inst: work@axi (work@axi), file:${SURELOG_DIR}/tests/GenBlock/dut.sv, line:4:1, endln:22:10 |vpiParent: \_design: (work@axi) |vpiFullName:work@axi |vpiParameter: \_parameter: (work@axi.N_MASTER), line:6:15, endln:6:23 |vpiParent: - \_module: work@axi (work@axi), file:${SURELOG_DIR}/tests/GenBlock/dut.sv, line:4:1, endln:22:10 + \_module_inst: work@axi (work@axi), file:${SURELOG_DIR}/tests/GenBlock/dut.sv, line:4:1, endln:22:10 |UINT:8 |vpiTypespec: \_int_typespec: @@ -220,20 +220,20 @@ design: (work@axi) |vpiParameter: \_parameter: (work@axi.LOG_MASTER), line:7:15, endln:7:25 |vpiParent: - \_module: work@axi (work@axi), file:${SURELOG_DIR}/tests/GenBlock/dut.sv, line:4:1, endln:22:10 + \_module_inst: work@axi (work@axi), file:${SURELOG_DIR}/tests/GenBlock/dut.sv, line:4:1, endln:22:10 |vpiName:LOG_MASTER |vpiFullName:work@axi.LOG_MASTER |vpiParameter: \_parameter: (work@axi.TOTAL_N_MASTER), line:8:16, endln:8:30 |vpiParent: - \_module: work@axi (work@axi), file:${SURELOG_DIR}/tests/GenBlock/dut.sv, line:4:1, endln:22:10 + \_module_inst: work@axi (work@axi), file:${SURELOG_DIR}/tests/GenBlock/dut.sv, line:4:1, endln:22:10 |vpiLocalParam:1 |vpiName:TOTAL_N_MASTER |vpiFullName:work@axi.TOTAL_N_MASTER |vpiParamAssign: \_param_assign: , line:6:15, endln:6:34 |vpiParent: - \_module: work@axi (work@axi), file:${SURELOG_DIR}/tests/GenBlock/dut.sv, line:4:1, endln:22:10 + \_module_inst: work@axi (work@axi), file:${SURELOG_DIR}/tests/GenBlock/dut.sv, line:4:1, endln:22:10 |vpiRhs: \_constant: , line:6:33, endln:6:34 |vpiDecompile:8 @@ -247,7 +247,7 @@ design: (work@axi) |vpiParamAssign: \_param_assign: , line:7:15, endln:7:49 |vpiParent: - \_module: work@axi (work@axi), file:${SURELOG_DIR}/tests/GenBlock/dut.sv, line:4:1, endln:22:10 + \_module_inst: work@axi (work@axi), file:${SURELOG_DIR}/tests/GenBlock/dut.sv, line:4:1, endln:22:10 |vpiRhs: \_sys_func_call: ($clog2), line:7:33, endln:7:49 |vpiArgument: @@ -261,7 +261,7 @@ design: (work@axi) |vpiParamAssign: \_param_assign: , line:8:16, endln:8:49 |vpiParent: - \_module: work@axi (work@axi), file:${SURELOG_DIR}/tests/GenBlock/dut.sv, line:4:1, endln:22:10 + \_module_inst: work@axi (work@axi), file:${SURELOG_DIR}/tests/GenBlock/dut.sv, line:4:1, endln:22:10 |vpiRhs: \_operation: , line:8:36, endln:8:49 |vpiOpType:43 @@ -282,12 +282,12 @@ design: (work@axi) \_parameter: (work@axi.TOTAL_N_MASTER), line:8:16, endln:8:30 |vpiDefName:work@axi |uhdmtopModules: -\_module: work@axi (work@axi), file:${SURELOG_DIR}/tests/GenBlock/dut.sv, line:4:1, endln:22:10 +\_module_inst: work@axi (work@axi), file:${SURELOG_DIR}/tests/GenBlock/dut.sv, line:4:1, endln:22:10 |vpiName:work@axi |vpiParameter: \_parameter: (work@axi.N_MASTER), line:6:15, endln:6:23 |vpiParent: - \_module: work@axi (work@axi), file:${SURELOG_DIR}/tests/GenBlock/dut.sv, line:4:1, endln:22:10 + \_module_inst: work@axi (work@axi), file:${SURELOG_DIR}/tests/GenBlock/dut.sv, line:4:1, endln:22:10 |UINT:8 |vpiTypespec: \_int_typespec: @@ -298,20 +298,20 @@ design: (work@axi) |vpiParameter: \_parameter: (work@axi.LOG_MASTER), line:7:15, endln:7:25 |vpiParent: - \_module: work@axi (work@axi), file:${SURELOG_DIR}/tests/GenBlock/dut.sv, line:4:1, endln:22:10 + \_module_inst: work@axi (work@axi), file:${SURELOG_DIR}/tests/GenBlock/dut.sv, line:4:1, endln:22:10 |vpiName:LOG_MASTER |vpiFullName:work@axi.LOG_MASTER |vpiParameter: \_parameter: (work@axi.TOTAL_N_MASTER), line:8:16, endln:8:30 |vpiParent: - \_module: work@axi (work@axi), file:${SURELOG_DIR}/tests/GenBlock/dut.sv, line:4:1, endln:22:10 + \_module_inst: work@axi (work@axi), file:${SURELOG_DIR}/tests/GenBlock/dut.sv, line:4:1, endln:22:10 |vpiLocalParam:1 |vpiName:TOTAL_N_MASTER |vpiFullName:work@axi.TOTAL_N_MASTER |vpiParamAssign: \_param_assign: , line:6:15, endln:6:34 |vpiParent: - \_module: work@axi (work@axi), file:${SURELOG_DIR}/tests/GenBlock/dut.sv, line:4:1, endln:22:10 + \_module_inst: work@axi (work@axi), file:${SURELOG_DIR}/tests/GenBlock/dut.sv, line:4:1, endln:22:10 |vpiRhs: \_constant: , line:6:33, endln:6:34 |vpiDecompile:8 @@ -325,7 +325,7 @@ design: (work@axi) |vpiParamAssign: \_param_assign: , line:7:15, endln:7:49 |vpiParent: - \_module: work@axi (work@axi), file:${SURELOG_DIR}/tests/GenBlock/dut.sv, line:4:1, endln:22:10 + \_module_inst: work@axi (work@axi), file:${SURELOG_DIR}/tests/GenBlock/dut.sv, line:4:1, endln:22:10 |vpiRhs: \_constant: , line:7:33, endln:7:49 |vpiDecompile:3 @@ -337,7 +337,7 @@ design: (work@axi) |vpiParamAssign: \_param_assign: , line:8:16, endln:8:49 |vpiParent: - \_module: work@axi (work@axi), file:${SURELOG_DIR}/tests/GenBlock/dut.sv, line:4:1, endln:22:10 + \_module_inst: work@axi (work@axi), file:${SURELOG_DIR}/tests/GenBlock/dut.sv, line:4:1, endln:22:10 |vpiRhs: \_constant: , line:8:36, endln:8:49 |vpiDecompile:8 @@ -352,7 +352,7 @@ design: (work@axi) |vpiGenScopeArray: \_gen_scope_array: (work@axi.ARRAY_INT), line:17:7, endln:19:10 |vpiParent: - \_module: work@axi (work@axi), file:${SURELOG_DIR}/tests/GenBlock/dut.sv, line:4:1, endln:22:10 + \_module_inst: work@axi (work@axi), file:${SURELOG_DIR}/tests/GenBlock/dut.sv, line:4:1, endln:22:10 |vpiName:ARRAY_INT |vpiFullName:work@axi.ARRAY_INT |vpiGenScope: @@ -360,8 +360,8 @@ design: (work@axi) |vpiParent: \_gen_scope_array: (work@axi.ARRAY_INT), line:17:7, endln:19:10 |vpiFullName:work@axi.ARRAY_INT - |vpiModule: - \_module: work@GOOD (work@axi.ARRAY_INT.good), file:${SURELOG_DIR}/tests/GenBlock/dut.sv, line:18:9, endln:18:21 + |vpiModuleInst: + \_module_inst: work@GOOD (work@axi.ARRAY_INT.good), file:${SURELOG_DIR}/tests/GenBlock/dut.sv, line:18:9, endln:18:21 |vpiParent: \_gen_scope: (work@axi.ARRAY_INT) |vpiName:good diff --git a/tests/GenBlockVar/GenBlockVar.log b/tests/GenBlockVar/GenBlockVar.log index 02ac3fba95..947a6bd16b 100644 --- a/tests/GenBlockVar/GenBlockVar.log +++ b/tests/GenBlockVar/GenBlockVar.log @@ -364,7 +364,7 @@ int_var 4 io_decl 11 logic_typespec 1 logic_var 3 -module 5 +module_inst 5 package 2 param_assign 2 parameter 2 @@ -390,7 +390,7 @@ int_var 4 io_decl 22 logic_typespec 1 logic_var 5 -module 5 +module_inst 5 package 2 param_assign 2 parameter 2 @@ -884,14 +884,14 @@ design: (work@top) \_int_typespec: |vpiSigned:1 |uhdmallModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/GenBlockVar/dut.sv, line:1:1, endln:12:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/GenBlockVar/dut.sv, line:1:1, endln:12:10 |vpiParent: \_design: (work@top) |vpiFullName:work@top |vpiParameter: \_parameter: (work@top.AsyncOn), line:3:17, endln:3:24 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/GenBlockVar/dut.sv, line:1:1, endln:12:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/GenBlockVar/dut.sv, line:1:1, endln:12:10 |BIN:0 |vpiTypespec: \_bit_typespec: , line:3:13, endln:3:16 @@ -903,7 +903,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:3:17, endln:3:31 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/GenBlockVar/dut.sv, line:1:1, endln:12:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/GenBlockVar/dut.sv, line:1:1, endln:12:10 |vpiRhs: \_constant: , line:3:27, endln:3:31 |vpiDecompile:1'b0 @@ -916,12 +916,12 @@ design: (work@top) \_parameter: (work@top.AsyncOn), line:3:17, endln:3:24 |vpiDefName:work@top |uhdmtopModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/GenBlockVar/dut.sv, line:1:1, endln:12:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/GenBlockVar/dut.sv, line:1:1, endln:12:10 |vpiName:work@top |vpiParameter: \_parameter: (work@top.AsyncOn), line:3:17, endln:3:24 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/GenBlockVar/dut.sv, line:1:1, endln:12:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/GenBlockVar/dut.sv, line:1:1, endln:12:10 |BIN:0 |vpiTypespec: \_bit_typespec: , line:3:13, endln:3:16 @@ -933,7 +933,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:3:17, endln:3:31 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/GenBlockVar/dut.sv, line:1:1, endln:12:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/GenBlockVar/dut.sv, line:1:1, endln:12:10 |vpiRhs: \_constant: , line:3:27, endln:3:31 |vpiDecompile:1'b0 @@ -950,7 +950,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.gen_no_async), line:7:12, endln:10:6 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/GenBlockVar/dut.sv, line:1:1, endln:12:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/GenBlockVar/dut.sv, line:1:1, endln:12:10 |vpiName:gen_no_async |vpiFullName:work@top.gen_no_async |vpiGenScope: diff --git a/tests/GenCaseStmt/GenCaseStmt.log b/tests/GenCaseStmt/GenCaseStmt.log index da486c80b0..61708400b6 100644 --- a/tests/GenCaseStmt/GenCaseStmt.log +++ b/tests/GenCaseStmt/GenCaseStmt.log @@ -291,7 +291,7 @@ gen_scope 6 gen_scope_array 6 int_typespec 24 logic_typespec 2 -module 9 +module_inst 9 param_assign 8 parameter 8 range 2 @@ -306,7 +306,7 @@ gen_scope 9 gen_scope_array 9 int_typespec 24 logic_typespec 2 -module 12 +module_inst 12 param_assign 8 parameter 8 range 2 @@ -324,20 +324,20 @@ design: (work@top) |vpiElaborated:1 |vpiName:work@top |uhdmallModules: -\_module: work@GOOD (work@GOOD), file:${SURELOG_DIR}/tests/GenCaseStmt/dut.sv, line:3:1, endln:4:10 +\_module_inst: work@GOOD (work@GOOD), file:${SURELOG_DIR}/tests/GenCaseStmt/dut.sv, line:3:1, endln:4:10 |vpiParent: \_design: (work@top) |vpiFullName:work@GOOD |vpiDefName:work@GOOD |uhdmallModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/GenCaseStmt/dut.sv, line:6:1, endln:30:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/GenCaseStmt/dut.sv, line:6:1, endln:30:10 |vpiParent: \_design: (work@top) |vpiFullName:work@top |vpiParameter: \_parameter: (work@top.x_1b0), line:7:26, endln:7:31 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/GenCaseStmt/dut.sv, line:6:1, endln:30:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/GenCaseStmt/dut.sv, line:6:1, endln:30:10 |BIN:0 |vpiTypespec: \_bit_typespec: , line:7:13, endln:7:16 @@ -348,7 +348,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.x_1sb0), line:8:24, endln:8:30 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/GenCaseStmt/dut.sv, line:6:1, endln:30:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/GenCaseStmt/dut.sv, line:6:1, endln:30:10 |BIN:0 |vpiTypespec: \_bit_typespec: , line:8:13, endln:8:16 @@ -361,7 +361,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.x_1sb1), line:9:24, endln:9:30 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/GenCaseStmt/dut.sv, line:6:1, endln:30:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/GenCaseStmt/dut.sv, line:6:1, endln:30:10 |BIN:1 |vpiTypespec: \_bit_typespec: , line:9:13, endln:9:16 @@ -374,7 +374,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.x_2sb11), line:10:32, endln:10:39 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/GenCaseStmt/dut.sv, line:6:1, endln:30:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/GenCaseStmt/dut.sv, line:6:1, endln:30:10 |BIN:11 |vpiTypespec: \_logic_typespec: , line:10:13, endln:10:31 @@ -405,7 +405,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:7:26, endln:7:38 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/GenCaseStmt/dut.sv, line:6:1, endln:30:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/GenCaseStmt/dut.sv, line:6:1, endln:30:10 |vpiRhs: \_constant: , line:7:34, endln:7:38 |vpiDecompile:1'b0 @@ -419,7 +419,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:8:24, endln:8:38 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/GenCaseStmt/dut.sv, line:6:1, endln:30:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/GenCaseStmt/dut.sv, line:6:1, endln:30:10 |vpiRhs: \_constant: , line:8:33, endln:8:38 |vpiDecompile:1'sb0 @@ -433,7 +433,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:9:24, endln:9:38 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/GenCaseStmt/dut.sv, line:6:1, endln:30:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/GenCaseStmt/dut.sv, line:6:1, endln:30:10 |vpiRhs: \_constant: , line:9:33, endln:9:38 |vpiDecompile:1'sb1 @@ -447,7 +447,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:10:32, endln:10:48 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/GenCaseStmt/dut.sv, line:6:1, endln:30:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/GenCaseStmt/dut.sv, line:6:1, endln:30:10 |vpiRhs: \_constant: , line:10:42, endln:10:48 |vpiDecompile:2'sb11 @@ -460,12 +460,12 @@ design: (work@top) \_parameter: (work@top.x_2sb11), line:10:32, endln:10:39 |vpiDefName:work@top |uhdmtopModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/GenCaseStmt/dut.sv, line:6:1, endln:30:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/GenCaseStmt/dut.sv, line:6:1, endln:30:10 |vpiName:work@top |vpiParameter: \_parameter: (work@top.x_1b0), line:7:26, endln:7:31 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/GenCaseStmt/dut.sv, line:6:1, endln:30:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/GenCaseStmt/dut.sv, line:6:1, endln:30:10 |BIN:0 |vpiTypespec: \_bit_typespec: , line:7:13, endln:7:16 @@ -476,7 +476,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.x_1sb0), line:8:24, endln:8:30 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/GenCaseStmt/dut.sv, line:6:1, endln:30:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/GenCaseStmt/dut.sv, line:6:1, endln:30:10 |BIN:0 |vpiTypespec: \_bit_typespec: , line:8:13, endln:8:16 @@ -489,7 +489,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.x_1sb1), line:9:24, endln:9:30 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/GenCaseStmt/dut.sv, line:6:1, endln:30:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/GenCaseStmt/dut.sv, line:6:1, endln:30:10 |BIN:1 |vpiTypespec: \_bit_typespec: , line:9:13, endln:9:16 @@ -502,7 +502,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.x_2sb11), line:10:32, endln:10:39 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/GenCaseStmt/dut.sv, line:6:1, endln:30:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/GenCaseStmt/dut.sv, line:6:1, endln:30:10 |BIN:11 |vpiTypespec: \_logic_typespec: , line:10:13, endln:10:31 @@ -535,7 +535,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:7:26, endln:7:38 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/GenCaseStmt/dut.sv, line:6:1, endln:30:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/GenCaseStmt/dut.sv, line:6:1, endln:30:10 |vpiRhs: \_constant: , line:7:34, endln:7:38 |vpiDecompile:1'b0 @@ -549,7 +549,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:8:24, endln:8:38 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/GenCaseStmt/dut.sv, line:6:1, endln:30:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/GenCaseStmt/dut.sv, line:6:1, endln:30:10 |vpiRhs: \_constant: , line:8:33, endln:8:38 |vpiDecompile:1'b0 @@ -563,7 +563,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:9:24, endln:9:38 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/GenCaseStmt/dut.sv, line:6:1, endln:30:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/GenCaseStmt/dut.sv, line:6:1, endln:30:10 |vpiRhs: \_constant: , line:9:33, endln:9:38 |vpiDecompile:1'b1 @@ -577,7 +577,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:10:32, endln:10:48 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/GenCaseStmt/dut.sv, line:6:1, endln:30:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/GenCaseStmt/dut.sv, line:6:1, endln:30:10 |vpiRhs: \_constant: , line:10:42, endln:10:48 |vpiDecompile:2'b11 @@ -594,7 +594,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.genblk1), line:12:3, endln:15:10 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/GenCaseStmt/dut.sv, line:6:1, endln:30:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/GenCaseStmt/dut.sv, line:6:1, endln:30:10 |vpiName:genblk1 |vpiFullName:work@top.genblk1 |vpiGenScope: @@ -602,8 +602,8 @@ design: (work@top) |vpiParent: \_gen_scope_array: (work@top.genblk1), line:12:3, endln:15:10 |vpiFullName:work@top.genblk1 - |vpiModule: - \_module: work@GOOD (work@top.genblk1.u3), file:${SURELOG_DIR}/tests/GenCaseStmt/dut.sv, line:14:14, endln:14:24 + |vpiModuleInst: + \_module_inst: work@GOOD (work@top.genblk1.u3), file:${SURELOG_DIR}/tests/GenCaseStmt/dut.sv, line:14:14, endln:14:24 |vpiParent: \_gen_scope: (work@top.genblk1) |vpiName:u3 @@ -614,7 +614,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.genblk2), line:18:3, endln:22:10 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/GenCaseStmt/dut.sv, line:6:1, endln:30:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/GenCaseStmt/dut.sv, line:6:1, endln:30:10 |vpiName:genblk2 |vpiFullName:work@top.genblk2 |vpiGenScope: @@ -622,8 +622,8 @@ design: (work@top) |vpiParent: \_gen_scope_array: (work@top.genblk2), line:18:3, endln:22:10 |vpiFullName:work@top.genblk2 - |vpiModule: - \_module: work@GOOD (work@top.genblk2.u3), file:${SURELOG_DIR}/tests/GenCaseStmt/dut.sv, line:21:14, endln:21:24 + |vpiModuleInst: + \_module_inst: work@GOOD (work@top.genblk2.u3), file:${SURELOG_DIR}/tests/GenCaseStmt/dut.sv, line:21:14, endln:21:24 |vpiParent: \_gen_scope: (work@top.genblk2) |vpiName:u3 @@ -634,7 +634,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.genblk3), line:24:3, endln:28:10 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/GenCaseStmt/dut.sv, line:6:1, endln:30:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/GenCaseStmt/dut.sv, line:6:1, endln:30:10 |vpiName:genblk3 |vpiFullName:work@top.genblk3 |vpiGenScope: @@ -642,8 +642,8 @@ design: (work@top) |vpiParent: \_gen_scope_array: (work@top.genblk3), line:24:3, endln:28:10 |vpiFullName:work@top.genblk3 - |vpiModule: - \_module: work@GOOD (work@top.genblk3.u2), file:${SURELOG_DIR}/tests/GenCaseStmt/dut.sv, line:26:13, endln:26:23 + |vpiModuleInst: + \_module_inst: work@GOOD (work@top.genblk3.u2), file:${SURELOG_DIR}/tests/GenCaseStmt/dut.sv, line:26:13, endln:26:23 |vpiParent: \_gen_scope: (work@top.genblk3) |vpiName:u2 diff --git a/tests/GenIf/GenIf.log b/tests/GenIf/GenIf.log index b522899a6b..36bf8c7d6f 100644 --- a/tests/GenIf/GenIf.log +++ b/tests/GenIf/GenIf.log @@ -415,7 +415,7 @@ int_typespec 11 int_var 4 io_decl 11 logic_var 1 -module 4 +module_inst 4 operation 5 package 2 parameter 2 @@ -441,7 +441,7 @@ int_typespec 11 int_var 4 io_decl 22 logic_var 1 -module 4 +module_inst 4 operation 5 package 2 parameter 2 @@ -936,13 +936,13 @@ design: (work@gen_test4) \_int_typespec: |vpiSigned:1 |uhdmallModules: -\_module: work@gen_test4 (work@gen_test4), file:${SURELOG_DIR}/tests/GenIf/dut.sv, line:1:1, endln:14:10 +\_module_inst: work@gen_test4 (work@gen_test4), file:${SURELOG_DIR}/tests/GenIf/dut.sv, line:1:1, endln:14:10 |vpiParent: \_design: (work@gen_test4) |vpiFullName:work@gen_test4 |vpiDefName:work@gen_test4 |uhdmtopModules: -\_module: work@gen_test4 (work@gen_test4), file:${SURELOG_DIR}/tests/GenIf/dut.sv, line:1:1, endln:14:10 +\_module_inst: work@gen_test4 (work@gen_test4), file:${SURELOG_DIR}/tests/GenIf/dut.sv, line:1:1, endln:14:10 |vpiName:work@gen_test4 |vpiDefName:work@gen_test4 |vpiTop:1 @@ -950,7 +950,7 @@ design: (work@gen_test4) |vpiGenScopeArray: \_gen_scope_array: (work@gen_test4.foo[0]), line:7:33, endln:12:12 |vpiParent: - \_module: work@gen_test4 (work@gen_test4), file:${SURELOG_DIR}/tests/GenIf/dut.sv, line:1:1, endln:14:10 + \_module_inst: work@gen_test4 (work@gen_test4), file:${SURELOG_DIR}/tests/GenIf/dut.sv, line:1:1, endln:14:10 |vpiName:foo[0] |vpiFullName:work@gen_test4.foo[0] |vpiGenScope: @@ -998,7 +998,7 @@ design: (work@gen_test4) |vpiGenScopeArray: \_gen_scope_array: (work@gen_test4.foo[1]), line:7:33, endln:12:12 |vpiParent: - \_module: work@gen_test4 (work@gen_test4), file:${SURELOG_DIR}/tests/GenIf/dut.sv, line:1:1, endln:14:10 + \_module_inst: work@gen_test4 (work@gen_test4), file:${SURELOG_DIR}/tests/GenIf/dut.sv, line:1:1, endln:14:10 |vpiName:foo[1] |vpiFullName:work@gen_test4.foo[1] |vpiGenScope: diff --git a/tests/GenModHierPath/GenModHierPath.log b/tests/GenModHierPath/GenModHierPath.log index 91dcc611ec..a4e261f9ba 100644 --- a/tests/GenModHierPath/GenModHierPath.log +++ b/tests/GenModHierPath/GenModHierPath.log @@ -134,7 +134,7 @@ hier_path 1 int_typespec 1 int_var 1 logic_net 1 -module 6 +module_inst 6 operation 1 range 1 ref_obj 3 @@ -154,7 +154,7 @@ hier_path 2 int_typespec 1 int_var 2 logic_net 1 -module 7 +module_inst 7 operation 2 range 2 ref_obj 6 @@ -173,7 +173,7 @@ design: (work@InitializedBlockRAM) |vpiElaborated:1 |vpiName:work@InitializedBlockRAM |uhdmallModules: -\_module: work@ForNarrowRequest (work@ForNarrowRequest), file:${SURELOG_DIR}/tests/GenModHierPath/dut.sv, line:1:1, endln:5:10 +\_module_inst: work@ForNarrowRequest (work@ForNarrowRequest), file:${SURELOG_DIR}/tests/GenModHierPath/dut.sv, line:1:1, endln:5:10 |vpiParent: \_design: (work@InitializedBlockRAM) |vpiFullName:work@ForNarrowRequest @@ -181,11 +181,11 @@ design: (work@InitializedBlockRAM) |vpiNet: \_logic_net: (work@ForNarrowRequest.array), line:3:7, endln:3:12 |vpiParent: - \_module: work@ForNarrowRequest (work@ForNarrowRequest), file:${SURELOG_DIR}/tests/GenModHierPath/dut.sv, line:1:1, endln:5:10 + \_module_inst: work@ForNarrowRequest (work@ForNarrowRequest), file:${SURELOG_DIR}/tests/GenModHierPath/dut.sv, line:1:1, endln:5:10 |vpiName:array |vpiFullName:work@ForNarrowRequest.array |uhdmallModules: -\_module: work@InitializedBlockRAM (work@InitializedBlockRAM), file:${SURELOG_DIR}/tests/GenModHierPath/dut.sv, line:8:1, endln:20:10 +\_module_inst: work@InitializedBlockRAM (work@InitializedBlockRAM), file:${SURELOG_DIR}/tests/GenModHierPath/dut.sv, line:8:1, endln:20:10 |vpiParent: \_design: (work@InitializedBlockRAM) |vpiFullName:work@InitializedBlockRAM @@ -193,13 +193,13 @@ design: (work@InitializedBlockRAM) |vpiTaskFunc: \_function: (work@InitializedBlockRAM.InitializeMemory), line:16:3, endln:18:14 |vpiParent: - \_module: work@InitializedBlockRAM (work@InitializedBlockRAM), file:${SURELOG_DIR}/tests/GenModHierPath/dut.sv, line:8:1, endln:20:10 + \_module_inst: work@InitializedBlockRAM (work@InitializedBlockRAM), file:${SURELOG_DIR}/tests/GenModHierPath/dut.sv, line:8:1, endln:20:10 |vpiName:InitializeMemory |vpiFullName:work@InitializedBlockRAM.InitializeMemory |vpiVisibility:1 |vpiAutomatic:1 |vpiParent: - \_module: work@InitializedBlockRAM (work@InitializedBlockRAM), file:${SURELOG_DIR}/tests/GenModHierPath/dut.sv, line:8:1, endln:20:10 + \_module_inst: work@InitializedBlockRAM (work@InitializedBlockRAM), file:${SURELOG_DIR}/tests/GenModHierPath/dut.sv, line:8:1, endln:20:10 |vpiStmt: \_sys_func_call: ($readmemh), line:17:5, endln:17:30 |vpiParent: @@ -224,22 +224,22 @@ design: (work@InitializedBlockRAM) |vpiName:array |vpiName:$readmemh |vpiInstance: - \_module: work@InitializedBlockRAM (work@InitializedBlockRAM), file:${SURELOG_DIR}/tests/GenModHierPath/dut.sv, line:8:1, endln:20:10 + \_module_inst: work@InitializedBlockRAM (work@InitializedBlockRAM), file:${SURELOG_DIR}/tests/GenModHierPath/dut.sv, line:8:1, endln:20:10 |uhdmtopModules: -\_module: work@InitializedBlockRAM (work@InitializedBlockRAM), file:${SURELOG_DIR}/tests/GenModHierPath/dut.sv, line:8:1, endln:20:10 +\_module_inst: work@InitializedBlockRAM (work@InitializedBlockRAM), file:${SURELOG_DIR}/tests/GenModHierPath/dut.sv, line:8:1, endln:20:10 |vpiName:work@InitializedBlockRAM |vpiDefName:work@InitializedBlockRAM |vpiTop:1 |vpiTaskFunc: \_function: (work@InitializedBlockRAM.InitializeMemory), line:16:3, endln:18:14 |vpiParent: - \_module: work@InitializedBlockRAM (work@InitializedBlockRAM), file:${SURELOG_DIR}/tests/GenModHierPath/dut.sv, line:8:1, endln:20:10 + \_module_inst: work@InitializedBlockRAM (work@InitializedBlockRAM), file:${SURELOG_DIR}/tests/GenModHierPath/dut.sv, line:8:1, endln:20:10 |vpiName:InitializeMemory |vpiFullName:work@InitializedBlockRAM.InitializeMemory |vpiVisibility:1 |vpiAutomatic:1 |vpiParent: - \_module: work@InitializedBlockRAM (work@InitializedBlockRAM), file:${SURELOG_DIR}/tests/GenModHierPath/dut.sv, line:8:1, endln:20:10 + \_module_inst: work@InitializedBlockRAM (work@InitializedBlockRAM), file:${SURELOG_DIR}/tests/GenModHierPath/dut.sv, line:8:1, endln:20:10 |vpiStmt: \_sys_func_call: ($readmemh), line:17:5, endln:17:30 |vpiParent: @@ -262,7 +262,7 @@ design: (work@InitializedBlockRAM) \_hier_path: (body.ram.array), line:17:15, endln:17:29 |vpiName:ram |vpiActual: - \_module: work@ForNarrowRequest (work@InitializedBlockRAM.body.ram), file:${SURELOG_DIR}/tests/GenModHierPath/dut.sv, line:12:9, endln:12:33 + \_module_inst: work@ForNarrowRequest (work@InitializedBlockRAM.body.ram), file:${SURELOG_DIR}/tests/GenModHierPath/dut.sv, line:12:9, endln:12:33 |vpiActual: \_ref_obj: (array), line:17:24, endln:17:29 |vpiParent: @@ -272,12 +272,12 @@ design: (work@InitializedBlockRAM) \_array_var: (work@InitializedBlockRAM.body.ram.array), line:3:7, endln:3:16 |vpiName:$readmemh |vpiInstance: - \_module: work@InitializedBlockRAM (work@InitializedBlockRAM), file:${SURELOG_DIR}/tests/GenModHierPath/dut.sv, line:8:1, endln:20:10 + \_module_inst: work@InitializedBlockRAM (work@InitializedBlockRAM), file:${SURELOG_DIR}/tests/GenModHierPath/dut.sv, line:8:1, endln:20:10 |vpiTopModule:1 |vpiGenScopeArray: \_gen_scope_array: (work@InitializedBlockRAM.body), line:11:5, endln:13:8 |vpiParent: - \_module: work@InitializedBlockRAM (work@InitializedBlockRAM), file:${SURELOG_DIR}/tests/GenModHierPath/dut.sv, line:8:1, endln:20:10 + \_module_inst: work@InitializedBlockRAM (work@InitializedBlockRAM), file:${SURELOG_DIR}/tests/GenModHierPath/dut.sv, line:8:1, endln:20:10 |vpiName:body |vpiFullName:work@InitializedBlockRAM.body |vpiGenScope: @@ -285,8 +285,8 @@ design: (work@InitializedBlockRAM) |vpiParent: \_gen_scope_array: (work@InitializedBlockRAM.body), line:11:5, endln:13:8 |vpiFullName:work@InitializedBlockRAM.body - |vpiModule: - \_module: work@ForNarrowRequest (work@InitializedBlockRAM.body.ram), file:${SURELOG_DIR}/tests/GenModHierPath/dut.sv, line:12:9, endln:12:33 + |vpiModuleInst: + \_module_inst: work@ForNarrowRequest (work@InitializedBlockRAM.body.ram), file:${SURELOG_DIR}/tests/GenModHierPath/dut.sv, line:12:9, endln:12:33 |vpiParent: \_gen_scope: (work@InitializedBlockRAM.body) |vpiName:ram @@ -294,7 +294,7 @@ design: (work@InitializedBlockRAM) |vpiVariables: \_array_var: (work@InitializedBlockRAM.body.ram.array), line:3:7, endln:3:16 |vpiParent: - \_module: work@ForNarrowRequest (work@InitializedBlockRAM.body.ram), file:${SURELOG_DIR}/tests/GenModHierPath/dut.sv, line:12:9, endln:12:33 + \_module_inst: work@ForNarrowRequest (work@InitializedBlockRAM.body.ram), file:${SURELOG_DIR}/tests/GenModHierPath/dut.sv, line:12:9, endln:12:33 |vpiSize:10 |vpiTypespec: \_array_typespec: @@ -303,7 +303,7 @@ design: (work@InitializedBlockRAM) |vpiRandType:1 |vpiVisibility:1 |vpiInstance: - \_module: work@ForNarrowRequest (work@InitializedBlockRAM.body.ram), file:${SURELOG_DIR}/tests/GenModHierPath/dut.sv, line:12:9, endln:12:33 + \_module_inst: work@ForNarrowRequest (work@InitializedBlockRAM.body.ram), file:${SURELOG_DIR}/tests/GenModHierPath/dut.sv, line:12:9, endln:12:33 |vpiArrayType:1 |vpiRange: \_range: , line:3:13, endln:3:15 diff --git a/tests/GenNet/GenNet.log b/tests/GenNet/GenNet.log index cbbfe4cd1e..75819d3029 100644 --- a/tests/GenNet/GenNet.log +++ b/tests/GenNet/GenNet.log @@ -278,7 +278,7 @@ int_typespec 2 logic_net 2 logic_typespec 4 logic_var 1 -module 9 +module_inst 9 operation 10 param_assign 4 parameter 4 @@ -299,7 +299,7 @@ int_typespec 2 logic_net 2 logic_typespec 4 logic_var 2 -module 9 +module_inst 9 operation 10 param_assign 4 parameter 4 @@ -321,20 +321,20 @@ design: (work@dut) |vpiElaborated:1 |vpiName:work@dut |uhdmallModules: -\_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/GenNet/dut.sv, line:17:1, endln:23:10 +\_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/GenNet/dut.sv, line:17:1, endln:23:10 |vpiParent: \_design: (work@dut) |vpiFullName:work@dut |vpiDefName:work@dut |uhdmallModules: -\_module: work@prim_subreg_arb (work@prim_subreg_arb), file:${SURELOG_DIR}/tests/GenNet/dut.sv, line:1:1, endln:15:10 +\_module_inst: work@prim_subreg_arb (work@prim_subreg_arb), file:${SURELOG_DIR}/tests/GenNet/dut.sv, line:1:1, endln:15:10 |vpiParent: \_design: (work@dut) |vpiFullName:work@prim_subreg_arb |vpiParameter: \_parameter: (work@prim_subreg_arb.DW), line:2:17, endln:2:19 |vpiParent: - \_module: work@prim_subreg_arb (work@prim_subreg_arb), file:${SURELOG_DIR}/tests/GenNet/dut.sv, line:1:1, endln:15:10 + \_module_inst: work@prim_subreg_arb (work@prim_subreg_arb), file:${SURELOG_DIR}/tests/GenNet/dut.sv, line:1:1, endln:15:10 |UINT:32 |vpiTypespec: \_int_typespec: , line:2:13, endln:2:16 @@ -347,7 +347,7 @@ design: (work@dut) |vpiParameter: \_parameter: (work@prim_subreg_arb.SWACCESS), line:3:17, endln:3:25 |vpiParent: - \_module: work@prim_subreg_arb (work@prim_subreg_arb), file:${SURELOG_DIR}/tests/GenNet/dut.sv, line:1:1, endln:15:10 + \_module_inst: work@prim_subreg_arb (work@prim_subreg_arb), file:${SURELOG_DIR}/tests/GenNet/dut.sv, line:1:1, endln:15:10 |STRING:RW |vpiTypespec: \_string_typespec: @@ -356,7 +356,7 @@ design: (work@dut) |vpiParamAssign: \_param_assign: , line:2:17, endln:2:30 |vpiParent: - \_module: work@prim_subreg_arb (work@prim_subreg_arb), file:${SURELOG_DIR}/tests/GenNet/dut.sv, line:1:1, endln:15:10 + \_module_inst: work@prim_subreg_arb (work@prim_subreg_arb), file:${SURELOG_DIR}/tests/GenNet/dut.sv, line:1:1, endln:15:10 |vpiRhs: \_constant: , line:2:28, endln:2:30 |vpiDecompile:32 @@ -370,7 +370,7 @@ design: (work@dut) |vpiParamAssign: \_param_assign: , line:3:17, endln:3:32 |vpiParent: - \_module: work@prim_subreg_arb (work@prim_subreg_arb), file:${SURELOG_DIR}/tests/GenNet/dut.sv, line:1:1, endln:15:10 + \_module_inst: work@prim_subreg_arb (work@prim_subreg_arb), file:${SURELOG_DIR}/tests/GenNet/dut.sv, line:1:1, endln:15:10 |vpiRhs: \_constant: , line:3:28, endln:3:32 |vpiDecompile:RW @@ -385,13 +385,13 @@ design: (work@dut) |vpiNet: \_logic_net: (work@prim_subreg_arb.q), line:5:18, endln:5:19 |vpiParent: - \_module: work@prim_subreg_arb (work@prim_subreg_arb), file:${SURELOG_DIR}/tests/GenNet/dut.sv, line:1:1, endln:15:10 + \_module_inst: work@prim_subreg_arb (work@prim_subreg_arb), file:${SURELOG_DIR}/tests/GenNet/dut.sv, line:1:1, endln:15:10 |vpiName:q |vpiFullName:work@prim_subreg_arb.q |vpiPort: \_port: (q), line:5:18, endln:5:19 |vpiParent: - \_module: work@prim_subreg_arb (work@prim_subreg_arb), file:${SURELOG_DIR}/tests/GenNet/dut.sv, line:1:1, endln:15:10 + \_module_inst: work@prim_subreg_arb (work@prim_subreg_arb), file:${SURELOG_DIR}/tests/GenNet/dut.sv, line:1:1, endln:15:10 |vpiName:q |vpiDirection:1 |vpiLowConn: @@ -429,21 +429,21 @@ design: (work@dut) |UINT:0 |vpiConstType:9 |uhdmtopModules: -\_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/GenNet/dut.sv, line:17:1, endln:23:10 +\_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/GenNet/dut.sv, line:17:1, endln:23:10 |vpiName:work@dut |vpiDefName:work@dut |vpiTop:1 |vpiTopModule:1 - |vpiModule: - \_module: work@prim_subreg_arb (work@dut.m1), file:${SURELOG_DIR}/tests/GenNet/dut.sv, line:19:2, endln:22:9 + |vpiModuleInst: + \_module_inst: work@prim_subreg_arb (work@dut.m1), file:${SURELOG_DIR}/tests/GenNet/dut.sv, line:19:2, endln:22:9 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/GenNet/dut.sv, line:17:1, endln:23:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/GenNet/dut.sv, line:17:1, endln:23:10 |vpiName:m1 |vpiFullName:work@dut.m1 |vpiParameter: \_parameter: (work@dut.m1.DW), line:2:17, endln:2:19 |vpiParent: - \_module: work@prim_subreg_arb (work@dut.m1), file:${SURELOG_DIR}/tests/GenNet/dut.sv, line:19:2, endln:22:9 + \_module_inst: work@prim_subreg_arb (work@dut.m1), file:${SURELOG_DIR}/tests/GenNet/dut.sv, line:19:2, endln:22:9 |UINT:32 |vpiTypespec: \_int_typespec: , line:2:13, endln:2:16 @@ -456,7 +456,7 @@ design: (work@dut) |vpiParameter: \_parameter: (work@dut.m1.SWACCESS), line:3:17, endln:3:25 |vpiParent: - \_module: work@prim_subreg_arb (work@dut.m1), file:${SURELOG_DIR}/tests/GenNet/dut.sv, line:19:2, endln:22:9 + \_module_inst: work@prim_subreg_arb (work@dut.m1), file:${SURELOG_DIR}/tests/GenNet/dut.sv, line:19:2, endln:22:9 |STRING:RW |vpiTypespec: \_string_typespec: @@ -467,7 +467,7 @@ design: (work@dut) |vpiParamAssign: \_param_assign: , line:2:17, endln:2:30 |vpiParent: - \_module: work@prim_subreg_arb (work@dut.m1), file:${SURELOG_DIR}/tests/GenNet/dut.sv, line:19:2, endln:22:9 + \_module_inst: work@prim_subreg_arb (work@dut.m1), file:${SURELOG_DIR}/tests/GenNet/dut.sv, line:19:2, endln:22:9 |vpiOverriden:1 |vpiRhs: \_constant: , line:2:28, endln:2:30 @@ -482,7 +482,7 @@ design: (work@dut) |vpiParamAssign: \_param_assign: , line:3:17, endln:3:32 |vpiParent: - \_module: work@prim_subreg_arb (work@dut.m1), file:${SURELOG_DIR}/tests/GenNet/dut.sv, line:19:2, endln:22:9 + \_module_inst: work@prim_subreg_arb (work@dut.m1), file:${SURELOG_DIR}/tests/GenNet/dut.sv, line:19:2, endln:22:9 |vpiOverriden:1 |vpiRhs: \_constant: , line:3:28, endln:3:32 @@ -500,7 +500,7 @@ design: (work@dut) |vpiNet: \_logic_net: (work@dut.m1.q), line:5:18, endln:5:19 |vpiParent: - \_module: work@prim_subreg_arb (work@dut.m1), file:${SURELOG_DIR}/tests/GenNet/dut.sv, line:19:2, endln:22:9 + \_module_inst: work@prim_subreg_arb (work@dut.m1), file:${SURELOG_DIR}/tests/GenNet/dut.sv, line:19:2, endln:22:9 |vpiTypespec: \_logic_typespec: , line:5:9, endln:5:17 |vpiRange: @@ -524,11 +524,11 @@ design: (work@dut) |vpiName:q |vpiFullName:work@dut.m1.q |vpiInstance: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/GenNet/dut.sv, line:17:1, endln:23:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/GenNet/dut.sv, line:17:1, endln:23:10 |vpiPort: \_port: (q), line:5:18, endln:5:19 |vpiParent: - \_module: work@prim_subreg_arb (work@dut.m1), file:${SURELOG_DIR}/tests/GenNet/dut.sv, line:19:2, endln:22:9 + \_module_inst: work@prim_subreg_arb (work@dut.m1), file:${SURELOG_DIR}/tests/GenNet/dut.sv, line:19:2, endln:22:9 |vpiName:q |vpiDirection:1 |vpiLowConn: @@ -562,11 +562,11 @@ design: (work@dut) |UINT:0 |vpiConstType:9 |vpiInstance: - \_module: work@prim_subreg_arb (work@dut.m1), file:${SURELOG_DIR}/tests/GenNet/dut.sv, line:19:2, endln:22:9 + \_module_inst: work@prim_subreg_arb (work@dut.m1), file:${SURELOG_DIR}/tests/GenNet/dut.sv, line:19:2, endln:22:9 |vpiGenScopeArray: \_gen_scope_array: (work@dut.m1.gen_ro), line:12:5, endln:12:32 |vpiParent: - \_module: work@prim_subreg_arb (work@dut.m1), file:${SURELOG_DIR}/tests/GenNet/dut.sv, line:19:2, endln:22:9 + \_module_inst: work@prim_subreg_arb (work@dut.m1), file:${SURELOG_DIR}/tests/GenNet/dut.sv, line:19:2, endln:22:9 |vpiName:gen_ro |vpiFullName:work@dut.m1.gen_ro |vpiGenScope: diff --git a/tests/GenScopeFullName/GenScopeFullName.log b/tests/GenScopeFullName/GenScopeFullName.log index 02dd34fdeb..729014e966 100644 --- a/tests/GenScopeFullName/GenScopeFullName.log +++ b/tests/GenScopeFullName/GenScopeFullName.log @@ -136,7 +136,7 @@ int_typespec 1 logic_net 3 logic_typespec 4 logic_var 1 -module 7 +module_inst 7 operation 2 parameter 1 port 2 @@ -155,7 +155,7 @@ int_typespec 1 logic_net 3 logic_typespec 4 logic_var 1 -module 8 +module_inst 8 operation 2 parameter 1 port 5 @@ -175,7 +175,7 @@ design: (work@dut) |vpiElaborated:1 |vpiName:work@dut |uhdmallModules: -\_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/GenScopeFullName/dut.sv, line:1:1, endln:10:10 +\_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/GenScopeFullName/dut.sv, line:1:1, endln:10:10 |vpiParent: \_design: (work@dut) |vpiFullName:work@dut @@ -183,12 +183,12 @@ design: (work@dut) |vpiNet: \_logic_net: (work@dut.a), line:2:16, endln:2:17 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/GenScopeFullName/dut.sv, line:1:1, endln:10:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/GenScopeFullName/dut.sv, line:1:1, endln:10:10 |vpiName:a |vpiFullName:work@dut.a |vpiNetType:36 |uhdmallModules: -\_module: work@ibex_counter (work@ibex_counter), file:${SURELOG_DIR}/tests/GenScopeFullName/dut.sv, line:12:1, endln:14:10 +\_module_inst: work@ibex_counter (work@ibex_counter), file:${SURELOG_DIR}/tests/GenScopeFullName/dut.sv, line:12:1, endln:14:10 |vpiParent: \_design: (work@dut) |vpiFullName:work@ibex_counter @@ -196,14 +196,14 @@ design: (work@dut) |vpiNet: \_logic_net: (work@ibex_counter.b), line:12:33, endln:12:34 |vpiParent: - \_module: work@ibex_counter (work@ibex_counter), file:${SURELOG_DIR}/tests/GenScopeFullName/dut.sv, line:12:1, endln:14:10 + \_module_inst: work@ibex_counter (work@ibex_counter), file:${SURELOG_DIR}/tests/GenScopeFullName/dut.sv, line:12:1, endln:14:10 |vpiName:b |vpiFullName:work@ibex_counter.b |vpiNetType:36 |vpiPort: \_port: (b), line:12:33, endln:12:34 |vpiParent: - \_module: work@ibex_counter (work@ibex_counter), file:${SURELOG_DIR}/tests/GenScopeFullName/dut.sv, line:12:1, endln:14:10 + \_module_inst: work@ibex_counter (work@ibex_counter), file:${SURELOG_DIR}/tests/GenScopeFullName/dut.sv, line:12:1, endln:14:10 |vpiName:b |vpiDirection:1 |vpiLowConn: @@ -213,12 +213,12 @@ design: (work@dut) |vpiTypedef: \_logic_typespec: , line:12:27, endln:12:32 |uhdmtopModules: -\_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/GenScopeFullName/dut.sv, line:1:1, endln:10:10 +\_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/GenScopeFullName/dut.sv, line:1:1, endln:10:10 |vpiName:work@dut |vpiVariables: \_logic_var: (work@dut.a), line:2:16, endln:2:17 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/GenScopeFullName/dut.sv, line:1:1, endln:10:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/GenScopeFullName/dut.sv, line:1:1, endln:10:10 |vpiTypespec: \_logic_typespec: , line:2:4, endln:2:15 |vpiRange: @@ -266,7 +266,7 @@ design: (work@dut) |vpiGenScopeArray: \_gen_scope_array: (work@dut.gen_modules[0]), line:4:34, endln:8:7 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/GenScopeFullName/dut.sv, line:1:1, endln:10:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/GenScopeFullName/dut.sv, line:1:1, endln:10:10 |vpiName:gen_modules[0] |vpiFullName:work@dut.gen_modules[0] |vpiGenScope: @@ -284,8 +284,8 @@ design: (work@dut) |vpiLocalParam:1 |vpiName:i |vpiFullName:work@dut.gen_modules[0].i - |vpiModule: - \_module: work@ibex_counter (work@dut.gen_modules[0].module_in_genscope), file:${SURELOG_DIR}/tests/GenScopeFullName/dut.sv, line:5:7, endln:5:49 + |vpiModuleInst: + \_module_inst: work@ibex_counter (work@dut.gen_modules[0].module_in_genscope), file:${SURELOG_DIR}/tests/GenScopeFullName/dut.sv, line:5:7, endln:5:49 |vpiParent: \_gen_scope: (work@dut.gen_modules[0]) |vpiName:module_in_genscope @@ -296,7 +296,7 @@ design: (work@dut) |vpiNet: \_logic_net: (work@dut.gen_modules[0].module_in_genscope.b), line:12:33, endln:12:34 |vpiParent: - \_module: work@ibex_counter (work@dut.gen_modules[0].module_in_genscope), file:${SURELOG_DIR}/tests/GenScopeFullName/dut.sv, line:5:7, endln:5:49 + \_module_inst: work@ibex_counter (work@dut.gen_modules[0].module_in_genscope), file:${SURELOG_DIR}/tests/GenScopeFullName/dut.sv, line:5:7, endln:5:49 |vpiTypespec: \_logic_typespec: , line:12:27, endln:12:32 |vpiName:b @@ -305,7 +305,7 @@ design: (work@dut) |vpiPort: \_port: (b), line:12:33, endln:12:34 |vpiParent: - \_module: work@ibex_counter (work@dut.gen_modules[0].module_in_genscope), file:${SURELOG_DIR}/tests/GenScopeFullName/dut.sv, line:5:7, endln:5:49 + \_module_inst: work@ibex_counter (work@dut.gen_modules[0].module_in_genscope), file:${SURELOG_DIR}/tests/GenScopeFullName/dut.sv, line:5:7, endln:5:49 |vpiName:b |vpiDirection:1 |vpiHighConn: @@ -341,7 +341,7 @@ design: (work@dut) |vpiTypedef: \_logic_typespec: , line:12:27, endln:12:32 |vpiInstance: - \_module: work@ibex_counter (work@dut.gen_modules[0].module_in_genscope), file:${SURELOG_DIR}/tests/GenScopeFullName/dut.sv, line:5:7, endln:5:49 + \_module_inst: work@ibex_counter (work@dut.gen_modules[0].module_in_genscope), file:${SURELOG_DIR}/tests/GenScopeFullName/dut.sv, line:5:7, endln:5:49 =================== [ FATAL] : 0 [ SYNTAX] : 0 diff --git a/tests/GenScopeFunc/GenScopeFunc.log b/tests/GenScopeFunc/GenScopeFunc.log index ef98cda788..e612f6bfbc 100644 --- a/tests/GenScopeFunc/GenScopeFunc.log +++ b/tests/GenScopeFunc/GenScopeFunc.log @@ -151,7 +151,7 @@ logic_net 2 logic_typespec 2 logic_var 2 method_func_call 1 -module 6 +module_inst 6 operation 1 ref_obj 5 === UHDM Object Stats End === @@ -171,7 +171,7 @@ logic_net 2 logic_typespec 2 logic_var 2 method_func_call 2 -module 6 +module_inst 6 operation 2 ref_obj 10 === UHDM Object Stats End === @@ -188,7 +188,7 @@ design: (work@top) |vpiElaborated:1 |vpiName:work@top |uhdmallModules: -\_module: work@mod (work@mod), file:${SURELOG_DIR}/tests/GenScopeFunc/dut.sv, line:1:1, endln:12:10 +\_module_inst: work@mod (work@mod), file:${SURELOG_DIR}/tests/GenScopeFunc/dut.sv, line:1:1, endln:12:10 |vpiParent: \_design: (work@top) |vpiFullName:work@mod @@ -196,7 +196,7 @@ design: (work@top) |vpiContAssign: \_cont_assign: , line:11:10, endln:11:46 |vpiParent: - \_module: work@mod (work@mod), file:${SURELOG_DIR}/tests/GenScopeFunc/dut.sv, line:1:1, endln:12:10 + \_module_inst: work@mod (work@mod), file:${SURELOG_DIR}/tests/GenScopeFunc/dut.sv, line:1:1, endln:12:10 |vpiRhs: \_hier_path: (cscope.local_function), line:11:16, endln:11:46 |vpiParent: @@ -226,21 +226,21 @@ design: (work@top) |vpiActual: \_logic_net: (foo) |uhdmallModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/GenScopeFunc/dut.sv, line:14:1, endln:16:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/GenScopeFunc/dut.sv, line:14:1, endln:16:10 |vpiParent: \_design: (work@top) |vpiFullName:work@top |vpiDefName:work@top |uhdmtopModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/GenScopeFunc/dut.sv, line:14:1, endln:16:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/GenScopeFunc/dut.sv, line:14:1, endln:16:10 |vpiName:work@top |vpiDefName:work@top |vpiTop:1 |vpiTopModule:1 - |vpiModule: - \_module: work@mod (work@top.c), file:${SURELOG_DIR}/tests/GenScopeFunc/dut.sv, line:15:3, endln:15:13 + |vpiModuleInst: + \_module_inst: work@mod (work@top.c), file:${SURELOG_DIR}/tests/GenScopeFunc/dut.sv, line:15:3, endln:15:13 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/GenScopeFunc/dut.sv, line:14:1, endln:16:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/GenScopeFunc/dut.sv, line:14:1, endln:16:10 |vpiName:c |vpiFullName:work@top.c |vpiDefName:work@mod @@ -255,11 +255,11 @@ design: (work@top) |vpiName:counter |vpiNetType:1 |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/GenScopeFunc/dut.sv, line:14:1, endln:16:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/GenScopeFunc/dut.sv, line:14:1, endln:16:10 |vpiGenScopeArray: \_gen_scope_array: (work@top.c.cscope), line:4:5, endln:8:8 |vpiParent: - \_module: work@mod (work@top.c), file:${SURELOG_DIR}/tests/GenScopeFunc/dut.sv, line:15:3, endln:15:13 + \_module_inst: work@mod (work@top.c), file:${SURELOG_DIR}/tests/GenScopeFunc/dut.sv, line:15:3, endln:15:13 |vpiName:cscope |vpiFullName:work@top.c.cscope |vpiGenScope: @@ -325,7 +325,7 @@ design: (work@top) |vpiContAssign: \_cont_assign: , line:11:10, endln:11:46 |vpiParent: - \_module: work@mod (work@top.c), file:${SURELOG_DIR}/tests/GenScopeFunc/dut.sv, line:15:3, endln:15:13 + \_module_inst: work@mod (work@top.c), file:${SURELOG_DIR}/tests/GenScopeFunc/dut.sv, line:15:3, endln:15:13 |vpiRhs: \_hier_path: (cscope.local_function), line:11:16, endln:11:46 |vpiParent: diff --git a/tests/GenScopeHierPath/GenScopeHierPath.log b/tests/GenScopeHierPath/GenScopeHierPath.log index d373b17ed9..e711761857 100644 --- a/tests/GenScopeHierPath/GenScopeHierPath.log +++ b/tests/GenScopeHierPath/GenScopeHierPath.log @@ -465,7 +465,7 @@ int_typespec 52 int_var 9 logic_net 3 logic_typespec 21 -module 27 +module_inst 27 operation 36 package 6 packed_array_typespec 13 @@ -496,7 +496,7 @@ int_typespec 52 int_var 25 logic_net 3 logic_typespec 21 -module 43 +module_inst 43 operation 36 package 6 packed_array_typespec 13 @@ -650,7 +650,7 @@ design: (work@top) |vpiElemTypespec: \_enum_typespec: (prim_pad_wrapper_pkg::pad_type_e), line:2:4, endln:5:17 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/GenScopeHierPath/dut.sv, line:44:1, endln:53:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/GenScopeHierPath/dut.sv, line:44:1, endln:53:10 |vpiName:prim_pad_wrapper_pkg::pad_type_e |vpiInstance: \_package: pinmux_pkg (pinmux_pkg::), file:${SURELOG_DIR}/tests/GenScopeHierPath/dut.sv, line:8:1, endln:20:24 @@ -777,7 +777,7 @@ design: (work@top) |vpiTypespec: \_struct_typespec: (pinmux_pkg::target_cfg_t), line:13:12, endln:13:18 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/GenScopeHierPath/dut.sv, line:44:1, endln:53:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/GenScopeHierPath/dut.sv, line:44:1, endln:53:10 |vpiName:pinmux_pkg::target_cfg_t |vpiInstance: \_package: pinmux_pkg (pinmux_pkg::), file:${SURELOG_DIR}/tests/GenScopeHierPath/dut.sv, line:8:1, endln:20:24 @@ -868,14 +868,14 @@ design: (work@top) |vpiDefName:pinmux_pkg |vpiTop:1 |uhdmallModules: -\_module: work@prim_generic_pad_attr (work@prim_generic_pad_attr), file:${SURELOG_DIR}/tests/GenScopeHierPath/dut.sv, line:23:1, endln:29:34 +\_module_inst: work@prim_generic_pad_attr (work@prim_generic_pad_attr), file:${SURELOG_DIR}/tests/GenScopeHierPath/dut.sv, line:23:1, endln:29:34 |vpiParent: \_design: (work@top) |vpiFullName:work@prim_generic_pad_attr |vpiParameter: \_parameter: (work@prim_generic_pad_attr.PadType), line:25:25, endln:25:32 |vpiParent: - \_module: work@prim_generic_pad_attr (work@prim_generic_pad_attr), file:${SURELOG_DIR}/tests/GenScopeHierPath/dut.sv, line:23:1, endln:29:34 + \_module_inst: work@prim_generic_pad_attr (work@prim_generic_pad_attr), file:${SURELOG_DIR}/tests/GenScopeHierPath/dut.sv, line:23:1, endln:29:34 |vpiTypespec: \_enum_typespec: (prim_pad_wrapper_pkg::pad_type_e), line:2:4, endln:5:17 |vpiName:PadType @@ -883,7 +883,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:25:25, endln:25:36 |vpiParent: - \_module: work@prim_generic_pad_attr (work@prim_generic_pad_attr), file:${SURELOG_DIR}/tests/GenScopeHierPath/dut.sv, line:23:1, endln:29:34 + \_module_inst: work@prim_generic_pad_attr (work@prim_generic_pad_attr), file:${SURELOG_DIR}/tests/GenScopeHierPath/dut.sv, line:23:1, endln:29:34 |vpiRhs: \_ref_obj: (A), line:25:35, endln:25:36 |vpiName:A @@ -899,13 +899,13 @@ design: (work@top) |vpiNet: \_logic_net: (work@prim_generic_pad_attr.a), line:23:41, endln:23:42 |vpiParent: - \_module: work@prim_generic_pad_attr (work@prim_generic_pad_attr), file:${SURELOG_DIR}/tests/GenScopeHierPath/dut.sv, line:23:1, endln:29:34 + \_module_inst: work@prim_generic_pad_attr (work@prim_generic_pad_attr), file:${SURELOG_DIR}/tests/GenScopeHierPath/dut.sv, line:23:1, endln:29:34 |vpiName:a |vpiFullName:work@prim_generic_pad_attr.a |vpiPort: \_port: (a), line:23:41, endln:23:42 |vpiParent: - \_module: work@prim_generic_pad_attr (work@prim_generic_pad_attr), file:${SURELOG_DIR}/tests/GenScopeHierPath/dut.sv, line:23:1, endln:29:34 + \_module_inst: work@prim_generic_pad_attr (work@prim_generic_pad_attr), file:${SURELOG_DIR}/tests/GenScopeHierPath/dut.sv, line:23:1, endln:29:34 |vpiName:a |vpiDirection:2 |vpiLowConn: @@ -916,14 +916,14 @@ design: (work@top) \_int_typespec: , line:23:37, endln:23:40 |vpiSigned:1 |uhdmallModules: -\_module: work@prim_pad_attr (work@prim_pad_attr), file:${SURELOG_DIR}/tests/GenScopeHierPath/dut.sv, line:32:1, endln:42:10 +\_module_inst: work@prim_pad_attr (work@prim_pad_attr), file:${SURELOG_DIR}/tests/GenScopeHierPath/dut.sv, line:32:1, endln:42:10 |vpiParent: \_design: (work@top) |vpiFullName:work@prim_pad_attr |vpiParameter: \_parameter: (work@prim_pad_attr.PadType), line:34:25, endln:34:32 |vpiParent: - \_module: work@prim_pad_attr (work@prim_pad_attr), file:${SURELOG_DIR}/tests/GenScopeHierPath/dut.sv, line:32:1, endln:42:10 + \_module_inst: work@prim_pad_attr (work@prim_pad_attr), file:${SURELOG_DIR}/tests/GenScopeHierPath/dut.sv, line:32:1, endln:42:10 |vpiTypespec: \_enum_typespec: (prim_pad_wrapper_pkg::pad_type_e), line:2:4, endln:5:17 |vpiName:PadType @@ -931,7 +931,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:34:25, endln:34:36 |vpiParent: - \_module: work@prim_pad_attr (work@prim_pad_attr), file:${SURELOG_DIR}/tests/GenScopeHierPath/dut.sv, line:32:1, endln:42:10 + \_module_inst: work@prim_pad_attr (work@prim_pad_attr), file:${SURELOG_DIR}/tests/GenScopeHierPath/dut.sv, line:32:1, endln:42:10 |vpiRhs: \_ref_obj: (A), line:34:35, endln:34:36 |vpiName:A @@ -947,13 +947,13 @@ design: (work@top) |vpiNet: \_logic_net: (work@prim_pad_attr.b), line:32:33, endln:32:34 |vpiParent: - \_module: work@prim_pad_attr (work@prim_pad_attr), file:${SURELOG_DIR}/tests/GenScopeHierPath/dut.sv, line:32:1, endln:42:10 + \_module_inst: work@prim_pad_attr (work@prim_pad_attr), file:${SURELOG_DIR}/tests/GenScopeHierPath/dut.sv, line:32:1, endln:42:10 |vpiName:b |vpiFullName:work@prim_pad_attr.b |vpiPort: \_port: (b), line:32:33, endln:32:34 |vpiParent: - \_module: work@prim_pad_attr (work@prim_pad_attr), file:${SURELOG_DIR}/tests/GenScopeHierPath/dut.sv, line:32:1, endln:42:10 + \_module_inst: work@prim_pad_attr (work@prim_pad_attr), file:${SURELOG_DIR}/tests/GenScopeHierPath/dut.sv, line:32:1, endln:42:10 |vpiName:b |vpiDirection:2 |vpiLowConn: @@ -964,14 +964,14 @@ design: (work@top) \_int_typespec: , line:32:29, endln:32:32 |vpiSigned:1 |uhdmallModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/GenScopeHierPath/dut.sv, line:44:1, endln:53:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/GenScopeHierPath/dut.sv, line:44:1, endln:53:10 |vpiParent: \_design: (work@top) |vpiFullName:work@top |vpiParameter: \_parameter: (work@top.DefaultTargetCfg), line:17:27, endln:17:43 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/GenScopeHierPath/dut.sv, line:44:1, endln:53:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/GenScopeHierPath/dut.sv, line:44:1, endln:53:10 |vpiTypespec: \_struct_typespec: (pinmux_pkg::target_cfg_t), line:13:12, endln:13:18 |vpiParent: @@ -1071,7 +1071,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.NDioPads), line:11:18, endln:11:26 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/GenScopeHierPath/dut.sv, line:44:1, endln:53:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/GenScopeHierPath/dut.sv, line:44:1, endln:53:10 |UINT:4 |vpiTypespec: \_int_typespec: , line:11:14, endln:11:17 @@ -1087,7 +1087,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.TargetCfg), line:46:27, endln:46:36 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/GenScopeHierPath/dut.sv, line:44:1, endln:53:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/GenScopeHierPath/dut.sv, line:44:1, endln:53:10 |vpiTypespec: \_struct_typespec: (pinmux_pkg::target_cfg_t), line:13:12, endln:13:18 |vpiName:TargetCfg @@ -1095,7 +1095,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:11:18, endln:11:30 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/GenScopeHierPath/dut.sv, line:44:1, endln:53:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/GenScopeHierPath/dut.sv, line:44:1, endln:53:10 |vpiRhs: \_constant: , line:11:29, endln:11:30 |vpiParent: @@ -1130,7 +1130,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:17:27, endln:19:5 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/GenScopeHierPath/dut.sv, line:44:1, endln:53:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/GenScopeHierPath/dut.sv, line:44:1, endln:53:10 |vpiRhs: \_operation: , line:17:46, endln:19:5 |vpiParent: @@ -1261,7 +1261,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:46:27, endln:46:55 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/GenScopeHierPath/dut.sv, line:44:1, endln:53:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/GenScopeHierPath/dut.sv, line:44:1, endln:53:10 |vpiRhs: \_ref_obj: (DefaultTargetCfg), line:46:39, endln:46:55 |vpiName:DefaultTargetCfg @@ -1277,13 +1277,13 @@ design: (work@top) |vpiNet: \_logic_net: (work@top.o), line:44:23, endln:44:24 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/GenScopeHierPath/dut.sv, line:44:1, endln:53:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/GenScopeHierPath/dut.sv, line:44:1, endln:53:10 |vpiName:o |vpiFullName:work@top.o |vpiPort: \_port: (o), line:44:23, endln:44:24 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/GenScopeHierPath/dut.sv, line:44:1, endln:53:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/GenScopeHierPath/dut.sv, line:44:1, endln:53:10 |vpiName:o |vpiDirection:2 |vpiLowConn: @@ -1294,12 +1294,12 @@ design: (work@top) \_int_typespec: , line:44:19, endln:44:22 |vpiSigned:1 |uhdmtopModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/GenScopeHierPath/dut.sv, line:44:1, endln:53:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/GenScopeHierPath/dut.sv, line:44:1, endln:53:10 |vpiName:work@top |vpiVariables: \_int_var: (work@top.o), line:44:23, endln:44:24 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/GenScopeHierPath/dut.sv, line:44:1, endln:53:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/GenScopeHierPath/dut.sv, line:44:1, endln:53:10 |vpiTypespec: \_int_typespec: , line:44:19, endln:44:22 |vpiSigned:1 @@ -1310,7 +1310,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.DefaultTargetCfg), line:17:27, endln:17:43 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/GenScopeHierPath/dut.sv, line:44:1, endln:53:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/GenScopeHierPath/dut.sv, line:44:1, endln:53:10 |vpiTypespec: \_struct_typespec: (pinmux_pkg::target_cfg_t), line:13:12, endln:13:18 |vpiParent: @@ -1410,7 +1410,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.NDioPads), line:11:18, endln:11:26 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/GenScopeHierPath/dut.sv, line:44:1, endln:53:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/GenScopeHierPath/dut.sv, line:44:1, endln:53:10 |UINT:4 |vpiTypespec: \_int_typespec: , line:11:14, endln:11:17 @@ -1426,7 +1426,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.TargetCfg), line:46:27, endln:46:36 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/GenScopeHierPath/dut.sv, line:44:1, endln:53:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/GenScopeHierPath/dut.sv, line:44:1, endln:53:10 |vpiTypespec: \_struct_typespec: (pinmux_pkg::target_cfg_t), line:13:12, endln:13:18 |vpiParent: @@ -1525,7 +1525,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:11:18, endln:11:30 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/GenScopeHierPath/dut.sv, line:44:1, endln:53:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/GenScopeHierPath/dut.sv, line:44:1, endln:53:10 |vpiRhs: \_constant: , line:11:29, endln:11:30 |vpiDecompile:4 @@ -1539,7 +1539,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:17:27, endln:19:5 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/GenScopeHierPath/dut.sv, line:44:1, endln:53:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/GenScopeHierPath/dut.sv, line:44:1, endln:53:10 |vpiRhs: \_operation: , line:17:46, endln:19:5 |vpiParent: @@ -1656,7 +1656,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:46:27, endln:46:55 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/GenScopeHierPath/dut.sv, line:44:1, endln:53:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/GenScopeHierPath/dut.sv, line:44:1, endln:53:10 |vpiRhs: \_ref_obj: (DefaultTargetCfg), line:46:39, endln:46:55 |vpiName:DefaultTargetCfg @@ -1676,7 +1676,7 @@ design: (work@top) |vpiPort: \_port: (o), line:44:23, endln:44:24 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/GenScopeHierPath/dut.sv, line:44:1, endln:53:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/GenScopeHierPath/dut.sv, line:44:1, endln:53:10 |vpiName:o |vpiDirection:2 |vpiLowConn: @@ -1691,11 +1691,11 @@ design: (work@top) \_int_typespec: , line:44:19, endln:44:22 |vpiSigned:1 |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/GenScopeHierPath/dut.sv, line:44:1, endln:53:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/GenScopeHierPath/dut.sv, line:44:1, endln:53:10 |vpiGenScopeArray: \_gen_scope_array: (work@top.gen_dio_attr[0]), line:48:41, endln:52:6 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/GenScopeHierPath/dut.sv, line:44:1, endln:53:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/GenScopeHierPath/dut.sv, line:44:1, endln:53:10 |vpiName:gen_dio_attr[0] |vpiFullName:work@top.gen_dio_attr[0] |vpiGenScope: @@ -1713,8 +1713,8 @@ design: (work@top) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@top.gen_dio_attr[0].k - |vpiModule: - \_module: work@prim_pad_attr (work@top.gen_dio_attr[0].u_prim_pad_attr), file:${SURELOG_DIR}/tests/GenScopeHierPath/dut.sv, line:49:6, endln:51:31 + |vpiModuleInst: + \_module_inst: work@prim_pad_attr (work@top.gen_dio_attr[0].u_prim_pad_attr), file:${SURELOG_DIR}/tests/GenScopeHierPath/dut.sv, line:49:6, endln:51:31 |vpiParent: \_gen_scope: (work@top.gen_dio_attr[0]) |vpiName:u_prim_pad_attr @@ -1722,7 +1722,7 @@ design: (work@top) |vpiVariables: \_int_var: (work@top.gen_dio_attr[0].u_prim_pad_attr.b), line:32:33, endln:32:34 |vpiParent: - \_module: work@prim_pad_attr (work@top.gen_dio_attr[0].u_prim_pad_attr), file:${SURELOG_DIR}/tests/GenScopeHierPath/dut.sv, line:49:6, endln:51:31 + \_module_inst: work@prim_pad_attr (work@top.gen_dio_attr[0].u_prim_pad_attr), file:${SURELOG_DIR}/tests/GenScopeHierPath/dut.sv, line:49:6, endln:51:31 |vpiTypespec: \_int_typespec: , line:32:29, endln:32:32 |vpiSigned:1 @@ -1731,7 +1731,7 @@ design: (work@top) |vpiSigned:1 |vpiVisibility:1 |vpiInstance: - \_module: work@prim_pad_attr (work@top.gen_dio_attr[0].u_prim_pad_attr), file:${SURELOG_DIR}/tests/GenScopeHierPath/dut.sv, line:49:6, endln:51:31 + \_module_inst: work@prim_pad_attr (work@top.gen_dio_attr[0].u_prim_pad_attr), file:${SURELOG_DIR}/tests/GenScopeHierPath/dut.sv, line:49:6, endln:51:31 |vpiParameter: \_parameter: (work@top.gen_dio_attr[0].u_prim_pad_attr.PadType), line:34:25, endln:34:32 |vpiParent: @@ -1790,7 +1790,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:34:25, endln:34:36 |vpiParent: - \_module: work@prim_pad_attr (work@top.gen_dio_attr[0].u_prim_pad_attr), file:${SURELOG_DIR}/tests/GenScopeHierPath/dut.sv, line:49:6, endln:51:31 + \_module_inst: work@prim_pad_attr (work@top.gen_dio_attr[0].u_prim_pad_attr), file:${SURELOG_DIR}/tests/GenScopeHierPath/dut.sv, line:49:6, endln:51:31 |vpiOverriden:1 |vpiRhs: \_constant: , line:34:35, endln:34:36 @@ -1812,7 +1812,7 @@ design: (work@top) |vpiPort: \_port: (b), line:32:33, endln:32:34 |vpiParent: - \_module: work@prim_pad_attr (work@top.gen_dio_attr[0].u_prim_pad_attr), file:${SURELOG_DIR}/tests/GenScopeHierPath/dut.sv, line:49:6, endln:51:31 + \_module_inst: work@prim_pad_attr (work@top.gen_dio_attr[0].u_prim_pad_attr), file:${SURELOG_DIR}/tests/GenScopeHierPath/dut.sv, line:49:6, endln:51:31 |vpiName:b |vpiDirection:2 |vpiHighConn: @@ -1835,11 +1835,11 @@ design: (work@top) \_int_typespec: , line:32:29, endln:32:32 |vpiSigned:1 |vpiInstance: - \_module: work@prim_pad_attr (work@top.gen_dio_attr[0].u_prim_pad_attr), file:${SURELOG_DIR}/tests/GenScopeHierPath/dut.sv, line:49:6, endln:51:31 + \_module_inst: work@prim_pad_attr (work@top.gen_dio_attr[0].u_prim_pad_attr), file:${SURELOG_DIR}/tests/GenScopeHierPath/dut.sv, line:49:6, endln:51:31 |vpiGenScopeArray: \_gen_scope_array: (work@top.gen_dio_attr[0].u_prim_pad_attr.gen_generic), line:36:4, endln:40:7 |vpiParent: - \_module: work@prim_pad_attr (work@top.gen_dio_attr[0].u_prim_pad_attr), file:${SURELOG_DIR}/tests/GenScopeHierPath/dut.sv, line:49:6, endln:51:31 + \_module_inst: work@prim_pad_attr (work@top.gen_dio_attr[0].u_prim_pad_attr), file:${SURELOG_DIR}/tests/GenScopeHierPath/dut.sv, line:49:6, endln:51:31 |vpiName:gen_generic |vpiFullName:work@top.gen_dio_attr[0].u_prim_pad_attr.gen_generic |vpiGenScope: @@ -1847,8 +1847,8 @@ design: (work@top) |vpiParent: \_gen_scope_array: (work@top.gen_dio_attr[0].u_prim_pad_attr.gen_generic), line:36:4, endln:40:7 |vpiFullName:work@top.gen_dio_attr[0].u_prim_pad_attr.gen_generic - |vpiModule: - \_module: work@prim_generic_pad_attr (work@top.gen_dio_attr[0].u_prim_pad_attr.gen_generic.u_impl_generic), file:${SURELOG_DIR}/tests/GenScopeHierPath/dut.sv, line:37:7, endln:39:31 + |vpiModuleInst: + \_module_inst: work@prim_generic_pad_attr (work@top.gen_dio_attr[0].u_prim_pad_attr.gen_generic.u_impl_generic), file:${SURELOG_DIR}/tests/GenScopeHierPath/dut.sv, line:37:7, endln:39:31 |vpiParent: \_gen_scope: (work@top.gen_dio_attr[0].u_prim_pad_attr.gen_generic) |vpiName:u_impl_generic @@ -1856,7 +1856,7 @@ design: (work@top) |vpiVariables: \_int_var: (work@top.gen_dio_attr[0].u_prim_pad_attr.gen_generic.u_impl_generic.a), line:23:41, endln:23:42 |vpiParent: - \_module: work@prim_generic_pad_attr (work@top.gen_dio_attr[0].u_prim_pad_attr.gen_generic.u_impl_generic), file:${SURELOG_DIR}/tests/GenScopeHierPath/dut.sv, line:37:7, endln:39:31 + \_module_inst: work@prim_generic_pad_attr (work@top.gen_dio_attr[0].u_prim_pad_attr.gen_generic.u_impl_generic), file:${SURELOG_DIR}/tests/GenScopeHierPath/dut.sv, line:37:7, endln:39:31 |vpiTypespec: \_int_typespec: , line:23:37, endln:23:40 |vpiSigned:1 @@ -1865,7 +1865,7 @@ design: (work@top) |vpiSigned:1 |vpiVisibility:1 |vpiInstance: - \_module: work@prim_generic_pad_attr (work@top.gen_dio_attr[0].u_prim_pad_attr.gen_generic.u_impl_generic), file:${SURELOG_DIR}/tests/GenScopeHierPath/dut.sv, line:37:7, endln:39:31 + \_module_inst: work@prim_generic_pad_attr (work@top.gen_dio_attr[0].u_prim_pad_attr.gen_generic.u_impl_generic), file:${SURELOG_DIR}/tests/GenScopeHierPath/dut.sv, line:37:7, endln:39:31 |vpiParameter: \_parameter: (work@top.gen_dio_attr[0].u_prim_pad_attr.gen_generic.u_impl_generic.PadType), line:25:25, endln:25:32 |vpiParent: @@ -1924,7 +1924,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:25:25, endln:25:36 |vpiParent: - \_module: work@prim_generic_pad_attr (work@top.gen_dio_attr[0].u_prim_pad_attr.gen_generic.u_impl_generic), file:${SURELOG_DIR}/tests/GenScopeHierPath/dut.sv, line:37:7, endln:39:31 + \_module_inst: work@prim_generic_pad_attr (work@top.gen_dio_attr[0].u_prim_pad_attr.gen_generic.u_impl_generic), file:${SURELOG_DIR}/tests/GenScopeHierPath/dut.sv, line:37:7, endln:39:31 |vpiOverriden:1 |vpiRhs: \_constant: , line:25:35, endln:25:36 @@ -1946,7 +1946,7 @@ design: (work@top) |vpiPort: \_port: (a), line:23:41, endln:23:42 |vpiParent: - \_module: work@prim_generic_pad_attr (work@top.gen_dio_attr[0].u_prim_pad_attr.gen_generic.u_impl_generic), file:${SURELOG_DIR}/tests/GenScopeHierPath/dut.sv, line:37:7, endln:39:31 + \_module_inst: work@prim_generic_pad_attr (work@top.gen_dio_attr[0].u_prim_pad_attr.gen_generic.u_impl_generic), file:${SURELOG_DIR}/tests/GenScopeHierPath/dut.sv, line:37:7, endln:39:31 |vpiName:a |vpiDirection:2 |vpiHighConn: @@ -1969,11 +1969,11 @@ design: (work@top) \_int_typespec: , line:23:37, endln:23:40 |vpiSigned:1 |vpiInstance: - \_module: work@prim_generic_pad_attr (work@top.gen_dio_attr[0].u_prim_pad_attr.gen_generic.u_impl_generic), file:${SURELOG_DIR}/tests/GenScopeHierPath/dut.sv, line:37:7, endln:39:31 + \_module_inst: work@prim_generic_pad_attr (work@top.gen_dio_attr[0].u_prim_pad_attr.gen_generic.u_impl_generic), file:${SURELOG_DIR}/tests/GenScopeHierPath/dut.sv, line:37:7, endln:39:31 |vpiGenScopeArray: \_gen_scope_array: (work@top.gen_dio_attr[0].u_prim_pad_attr.gen_generic.u_impl_generic.gen_assign), line:26:4, endln:28:7 |vpiParent: - \_module: work@prim_generic_pad_attr (work@top.gen_dio_attr[0].u_prim_pad_attr.gen_generic.u_impl_generic), file:${SURELOG_DIR}/tests/GenScopeHierPath/dut.sv, line:37:7, endln:39:31 + \_module_inst: work@prim_generic_pad_attr (work@top.gen_dio_attr[0].u_prim_pad_attr.gen_generic.u_impl_generic), file:${SURELOG_DIR}/tests/GenScopeHierPath/dut.sv, line:37:7, endln:39:31 |vpiName:gen_assign |vpiFullName:work@top.gen_dio_attr[0].u_prim_pad_attr.gen_generic.u_impl_generic.gen_assign |vpiGenScope: @@ -2004,7 +2004,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.gen_dio_attr[1]), line:48:41, endln:52:6 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/GenScopeHierPath/dut.sv, line:44:1, endln:53:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/GenScopeHierPath/dut.sv, line:44:1, endln:53:10 |vpiName:gen_dio_attr[1] |vpiFullName:work@top.gen_dio_attr[1] |vpiGenScope: @@ -2022,8 +2022,8 @@ design: (work@top) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@top.gen_dio_attr[1].k - |vpiModule: - \_module: work@prim_pad_attr (work@top.gen_dio_attr[1].u_prim_pad_attr), file:${SURELOG_DIR}/tests/GenScopeHierPath/dut.sv, line:49:6, endln:51:31 + |vpiModuleInst: + \_module_inst: work@prim_pad_attr (work@top.gen_dio_attr[1].u_prim_pad_attr), file:${SURELOG_DIR}/tests/GenScopeHierPath/dut.sv, line:49:6, endln:51:31 |vpiParent: \_gen_scope: (work@top.gen_dio_attr[1]) |vpiName:u_prim_pad_attr @@ -2031,7 +2031,7 @@ design: (work@top) |vpiVariables: \_int_var: (work@top.gen_dio_attr[1].u_prim_pad_attr.b), line:32:33, endln:32:34 |vpiParent: - \_module: work@prim_pad_attr (work@top.gen_dio_attr[1].u_prim_pad_attr), file:${SURELOG_DIR}/tests/GenScopeHierPath/dut.sv, line:49:6, endln:51:31 + \_module_inst: work@prim_pad_attr (work@top.gen_dio_attr[1].u_prim_pad_attr), file:${SURELOG_DIR}/tests/GenScopeHierPath/dut.sv, line:49:6, endln:51:31 |vpiTypespec: \_int_typespec: , line:32:29, endln:32:32 |vpiSigned:1 @@ -2040,7 +2040,7 @@ design: (work@top) |vpiSigned:1 |vpiVisibility:1 |vpiInstance: - \_module: work@prim_pad_attr (work@top.gen_dio_attr[1].u_prim_pad_attr), file:${SURELOG_DIR}/tests/GenScopeHierPath/dut.sv, line:49:6, endln:51:31 + \_module_inst: work@prim_pad_attr (work@top.gen_dio_attr[1].u_prim_pad_attr), file:${SURELOG_DIR}/tests/GenScopeHierPath/dut.sv, line:49:6, endln:51:31 |vpiParameter: \_parameter: (work@top.gen_dio_attr[1].u_prim_pad_attr.PadType), line:34:25, endln:34:32 |vpiParent: @@ -2099,7 +2099,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:34:25, endln:34:36 |vpiParent: - \_module: work@prim_pad_attr (work@top.gen_dio_attr[1].u_prim_pad_attr), file:${SURELOG_DIR}/tests/GenScopeHierPath/dut.sv, line:49:6, endln:51:31 + \_module_inst: work@prim_pad_attr (work@top.gen_dio_attr[1].u_prim_pad_attr), file:${SURELOG_DIR}/tests/GenScopeHierPath/dut.sv, line:49:6, endln:51:31 |vpiOverriden:1 |vpiRhs: \_constant: , line:34:35, endln:34:36 @@ -2121,7 +2121,7 @@ design: (work@top) |vpiPort: \_port: (b), line:32:33, endln:32:34 |vpiParent: - \_module: work@prim_pad_attr (work@top.gen_dio_attr[1].u_prim_pad_attr), file:${SURELOG_DIR}/tests/GenScopeHierPath/dut.sv, line:49:6, endln:51:31 + \_module_inst: work@prim_pad_attr (work@top.gen_dio_attr[1].u_prim_pad_attr), file:${SURELOG_DIR}/tests/GenScopeHierPath/dut.sv, line:49:6, endln:51:31 |vpiName:b |vpiDirection:2 |vpiHighConn: @@ -2144,11 +2144,11 @@ design: (work@top) \_int_typespec: , line:32:29, endln:32:32 |vpiSigned:1 |vpiInstance: - \_module: work@prim_pad_attr (work@top.gen_dio_attr[1].u_prim_pad_attr), file:${SURELOG_DIR}/tests/GenScopeHierPath/dut.sv, line:49:6, endln:51:31 + \_module_inst: work@prim_pad_attr (work@top.gen_dio_attr[1].u_prim_pad_attr), file:${SURELOG_DIR}/tests/GenScopeHierPath/dut.sv, line:49:6, endln:51:31 |vpiGenScopeArray: \_gen_scope_array: (work@top.gen_dio_attr[1].u_prim_pad_attr.gen_generic), line:36:4, endln:40:7 |vpiParent: - \_module: work@prim_pad_attr (work@top.gen_dio_attr[1].u_prim_pad_attr), file:${SURELOG_DIR}/tests/GenScopeHierPath/dut.sv, line:49:6, endln:51:31 + \_module_inst: work@prim_pad_attr (work@top.gen_dio_attr[1].u_prim_pad_attr), file:${SURELOG_DIR}/tests/GenScopeHierPath/dut.sv, line:49:6, endln:51:31 |vpiName:gen_generic |vpiFullName:work@top.gen_dio_attr[1].u_prim_pad_attr.gen_generic |vpiGenScope: @@ -2156,8 +2156,8 @@ design: (work@top) |vpiParent: \_gen_scope_array: (work@top.gen_dio_attr[1].u_prim_pad_attr.gen_generic), line:36:4, endln:40:7 |vpiFullName:work@top.gen_dio_attr[1].u_prim_pad_attr.gen_generic - |vpiModule: - \_module: work@prim_generic_pad_attr (work@top.gen_dio_attr[1].u_prim_pad_attr.gen_generic.u_impl_generic), file:${SURELOG_DIR}/tests/GenScopeHierPath/dut.sv, line:37:7, endln:39:31 + |vpiModuleInst: + \_module_inst: work@prim_generic_pad_attr (work@top.gen_dio_attr[1].u_prim_pad_attr.gen_generic.u_impl_generic), file:${SURELOG_DIR}/tests/GenScopeHierPath/dut.sv, line:37:7, endln:39:31 |vpiParent: \_gen_scope: (work@top.gen_dio_attr[1].u_prim_pad_attr.gen_generic) |vpiName:u_impl_generic @@ -2165,7 +2165,7 @@ design: (work@top) |vpiVariables: \_int_var: (work@top.gen_dio_attr[1].u_prim_pad_attr.gen_generic.u_impl_generic.a), line:23:41, endln:23:42 |vpiParent: - \_module: work@prim_generic_pad_attr (work@top.gen_dio_attr[1].u_prim_pad_attr.gen_generic.u_impl_generic), file:${SURELOG_DIR}/tests/GenScopeHierPath/dut.sv, line:37:7, endln:39:31 + \_module_inst: work@prim_generic_pad_attr (work@top.gen_dio_attr[1].u_prim_pad_attr.gen_generic.u_impl_generic), file:${SURELOG_DIR}/tests/GenScopeHierPath/dut.sv, line:37:7, endln:39:31 |vpiTypespec: \_int_typespec: , line:23:37, endln:23:40 |vpiSigned:1 @@ -2174,7 +2174,7 @@ design: (work@top) |vpiSigned:1 |vpiVisibility:1 |vpiInstance: - \_module: work@prim_generic_pad_attr (work@top.gen_dio_attr[1].u_prim_pad_attr.gen_generic.u_impl_generic), file:${SURELOG_DIR}/tests/GenScopeHierPath/dut.sv, line:37:7, endln:39:31 + \_module_inst: work@prim_generic_pad_attr (work@top.gen_dio_attr[1].u_prim_pad_attr.gen_generic.u_impl_generic), file:${SURELOG_DIR}/tests/GenScopeHierPath/dut.sv, line:37:7, endln:39:31 |vpiParameter: \_parameter: (work@top.gen_dio_attr[1].u_prim_pad_attr.gen_generic.u_impl_generic.PadType), line:25:25, endln:25:32 |vpiParent: @@ -2233,7 +2233,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:25:25, endln:25:36 |vpiParent: - \_module: work@prim_generic_pad_attr (work@top.gen_dio_attr[1].u_prim_pad_attr.gen_generic.u_impl_generic), file:${SURELOG_DIR}/tests/GenScopeHierPath/dut.sv, line:37:7, endln:39:31 + \_module_inst: work@prim_generic_pad_attr (work@top.gen_dio_attr[1].u_prim_pad_attr.gen_generic.u_impl_generic), file:${SURELOG_DIR}/tests/GenScopeHierPath/dut.sv, line:37:7, endln:39:31 |vpiOverriden:1 |vpiRhs: \_constant: , line:25:35, endln:25:36 @@ -2255,7 +2255,7 @@ design: (work@top) |vpiPort: \_port: (a), line:23:41, endln:23:42 |vpiParent: - \_module: work@prim_generic_pad_attr (work@top.gen_dio_attr[1].u_prim_pad_attr.gen_generic.u_impl_generic), file:${SURELOG_DIR}/tests/GenScopeHierPath/dut.sv, line:37:7, endln:39:31 + \_module_inst: work@prim_generic_pad_attr (work@top.gen_dio_attr[1].u_prim_pad_attr.gen_generic.u_impl_generic), file:${SURELOG_DIR}/tests/GenScopeHierPath/dut.sv, line:37:7, endln:39:31 |vpiName:a |vpiDirection:2 |vpiHighConn: @@ -2278,11 +2278,11 @@ design: (work@top) \_int_typespec: , line:23:37, endln:23:40 |vpiSigned:1 |vpiInstance: - \_module: work@prim_generic_pad_attr (work@top.gen_dio_attr[1].u_prim_pad_attr.gen_generic.u_impl_generic), file:${SURELOG_DIR}/tests/GenScopeHierPath/dut.sv, line:37:7, endln:39:31 + \_module_inst: work@prim_generic_pad_attr (work@top.gen_dio_attr[1].u_prim_pad_attr.gen_generic.u_impl_generic), file:${SURELOG_DIR}/tests/GenScopeHierPath/dut.sv, line:37:7, endln:39:31 |vpiGenScopeArray: \_gen_scope_array: (work@top.gen_dio_attr[1].u_prim_pad_attr.gen_generic.u_impl_generic.gen_assign), line:26:4, endln:28:7 |vpiParent: - \_module: work@prim_generic_pad_attr (work@top.gen_dio_attr[1].u_prim_pad_attr.gen_generic.u_impl_generic), file:${SURELOG_DIR}/tests/GenScopeHierPath/dut.sv, line:37:7, endln:39:31 + \_module_inst: work@prim_generic_pad_attr (work@top.gen_dio_attr[1].u_prim_pad_attr.gen_generic.u_impl_generic), file:${SURELOG_DIR}/tests/GenScopeHierPath/dut.sv, line:37:7, endln:39:31 |vpiName:gen_assign |vpiFullName:work@top.gen_dio_attr[1].u_prim_pad_attr.gen_generic.u_impl_generic.gen_assign |vpiGenScope: @@ -2313,7 +2313,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.gen_dio_attr[2]), line:48:41, endln:52:6 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/GenScopeHierPath/dut.sv, line:44:1, endln:53:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/GenScopeHierPath/dut.sv, line:44:1, endln:53:10 |vpiName:gen_dio_attr[2] |vpiFullName:work@top.gen_dio_attr[2] |vpiGenScope: @@ -2331,8 +2331,8 @@ design: (work@top) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@top.gen_dio_attr[2].k - |vpiModule: - \_module: work@prim_pad_attr (work@top.gen_dio_attr[2].u_prim_pad_attr), file:${SURELOG_DIR}/tests/GenScopeHierPath/dut.sv, line:49:6, endln:51:31 + |vpiModuleInst: + \_module_inst: work@prim_pad_attr (work@top.gen_dio_attr[2].u_prim_pad_attr), file:${SURELOG_DIR}/tests/GenScopeHierPath/dut.sv, line:49:6, endln:51:31 |vpiParent: \_gen_scope: (work@top.gen_dio_attr[2]) |vpiName:u_prim_pad_attr @@ -2340,7 +2340,7 @@ design: (work@top) |vpiVariables: \_int_var: (work@top.gen_dio_attr[2].u_prim_pad_attr.b), line:32:33, endln:32:34 |vpiParent: - \_module: work@prim_pad_attr (work@top.gen_dio_attr[2].u_prim_pad_attr), file:${SURELOG_DIR}/tests/GenScopeHierPath/dut.sv, line:49:6, endln:51:31 + \_module_inst: work@prim_pad_attr (work@top.gen_dio_attr[2].u_prim_pad_attr), file:${SURELOG_DIR}/tests/GenScopeHierPath/dut.sv, line:49:6, endln:51:31 |vpiTypespec: \_int_typespec: , line:32:29, endln:32:32 |vpiSigned:1 @@ -2349,7 +2349,7 @@ design: (work@top) |vpiSigned:1 |vpiVisibility:1 |vpiInstance: - \_module: work@prim_pad_attr (work@top.gen_dio_attr[2].u_prim_pad_attr), file:${SURELOG_DIR}/tests/GenScopeHierPath/dut.sv, line:49:6, endln:51:31 + \_module_inst: work@prim_pad_attr (work@top.gen_dio_attr[2].u_prim_pad_attr), file:${SURELOG_DIR}/tests/GenScopeHierPath/dut.sv, line:49:6, endln:51:31 |vpiParameter: \_parameter: (work@top.gen_dio_attr[2].u_prim_pad_attr.PadType), line:34:25, endln:34:32 |vpiParent: @@ -2408,7 +2408,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:34:25, endln:34:36 |vpiParent: - \_module: work@prim_pad_attr (work@top.gen_dio_attr[2].u_prim_pad_attr), file:${SURELOG_DIR}/tests/GenScopeHierPath/dut.sv, line:49:6, endln:51:31 + \_module_inst: work@prim_pad_attr (work@top.gen_dio_attr[2].u_prim_pad_attr), file:${SURELOG_DIR}/tests/GenScopeHierPath/dut.sv, line:49:6, endln:51:31 |vpiOverriden:1 |vpiRhs: \_constant: , line:34:35, endln:34:36 @@ -2430,7 +2430,7 @@ design: (work@top) |vpiPort: \_port: (b), line:32:33, endln:32:34 |vpiParent: - \_module: work@prim_pad_attr (work@top.gen_dio_attr[2].u_prim_pad_attr), file:${SURELOG_DIR}/tests/GenScopeHierPath/dut.sv, line:49:6, endln:51:31 + \_module_inst: work@prim_pad_attr (work@top.gen_dio_attr[2].u_prim_pad_attr), file:${SURELOG_DIR}/tests/GenScopeHierPath/dut.sv, line:49:6, endln:51:31 |vpiName:b |vpiDirection:2 |vpiHighConn: @@ -2453,11 +2453,11 @@ design: (work@top) \_int_typespec: , line:32:29, endln:32:32 |vpiSigned:1 |vpiInstance: - \_module: work@prim_pad_attr (work@top.gen_dio_attr[2].u_prim_pad_attr), file:${SURELOG_DIR}/tests/GenScopeHierPath/dut.sv, line:49:6, endln:51:31 + \_module_inst: work@prim_pad_attr (work@top.gen_dio_attr[2].u_prim_pad_attr), file:${SURELOG_DIR}/tests/GenScopeHierPath/dut.sv, line:49:6, endln:51:31 |vpiGenScopeArray: \_gen_scope_array: (work@top.gen_dio_attr[2].u_prim_pad_attr.gen_generic), line:36:4, endln:40:7 |vpiParent: - \_module: work@prim_pad_attr (work@top.gen_dio_attr[2].u_prim_pad_attr), file:${SURELOG_DIR}/tests/GenScopeHierPath/dut.sv, line:49:6, endln:51:31 + \_module_inst: work@prim_pad_attr (work@top.gen_dio_attr[2].u_prim_pad_attr), file:${SURELOG_DIR}/tests/GenScopeHierPath/dut.sv, line:49:6, endln:51:31 |vpiName:gen_generic |vpiFullName:work@top.gen_dio_attr[2].u_prim_pad_attr.gen_generic |vpiGenScope: @@ -2465,8 +2465,8 @@ design: (work@top) |vpiParent: \_gen_scope_array: (work@top.gen_dio_attr[2].u_prim_pad_attr.gen_generic), line:36:4, endln:40:7 |vpiFullName:work@top.gen_dio_attr[2].u_prim_pad_attr.gen_generic - |vpiModule: - \_module: work@prim_generic_pad_attr (work@top.gen_dio_attr[2].u_prim_pad_attr.gen_generic.u_impl_generic), file:${SURELOG_DIR}/tests/GenScopeHierPath/dut.sv, line:37:7, endln:39:31 + |vpiModuleInst: + \_module_inst: work@prim_generic_pad_attr (work@top.gen_dio_attr[2].u_prim_pad_attr.gen_generic.u_impl_generic), file:${SURELOG_DIR}/tests/GenScopeHierPath/dut.sv, line:37:7, endln:39:31 |vpiParent: \_gen_scope: (work@top.gen_dio_attr[2].u_prim_pad_attr.gen_generic) |vpiName:u_impl_generic @@ -2474,7 +2474,7 @@ design: (work@top) |vpiVariables: \_int_var: (work@top.gen_dio_attr[2].u_prim_pad_attr.gen_generic.u_impl_generic.a), line:23:41, endln:23:42 |vpiParent: - \_module: work@prim_generic_pad_attr (work@top.gen_dio_attr[2].u_prim_pad_attr.gen_generic.u_impl_generic), file:${SURELOG_DIR}/tests/GenScopeHierPath/dut.sv, line:37:7, endln:39:31 + \_module_inst: work@prim_generic_pad_attr (work@top.gen_dio_attr[2].u_prim_pad_attr.gen_generic.u_impl_generic), file:${SURELOG_DIR}/tests/GenScopeHierPath/dut.sv, line:37:7, endln:39:31 |vpiTypespec: \_int_typespec: , line:23:37, endln:23:40 |vpiSigned:1 @@ -2483,7 +2483,7 @@ design: (work@top) |vpiSigned:1 |vpiVisibility:1 |vpiInstance: - \_module: work@prim_generic_pad_attr (work@top.gen_dio_attr[2].u_prim_pad_attr.gen_generic.u_impl_generic), file:${SURELOG_DIR}/tests/GenScopeHierPath/dut.sv, line:37:7, endln:39:31 + \_module_inst: work@prim_generic_pad_attr (work@top.gen_dio_attr[2].u_prim_pad_attr.gen_generic.u_impl_generic), file:${SURELOG_DIR}/tests/GenScopeHierPath/dut.sv, line:37:7, endln:39:31 |vpiParameter: \_parameter: (work@top.gen_dio_attr[2].u_prim_pad_attr.gen_generic.u_impl_generic.PadType), line:25:25, endln:25:32 |vpiParent: @@ -2542,7 +2542,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:25:25, endln:25:36 |vpiParent: - \_module: work@prim_generic_pad_attr (work@top.gen_dio_attr[2].u_prim_pad_attr.gen_generic.u_impl_generic), file:${SURELOG_DIR}/tests/GenScopeHierPath/dut.sv, line:37:7, endln:39:31 + \_module_inst: work@prim_generic_pad_attr (work@top.gen_dio_attr[2].u_prim_pad_attr.gen_generic.u_impl_generic), file:${SURELOG_DIR}/tests/GenScopeHierPath/dut.sv, line:37:7, endln:39:31 |vpiOverriden:1 |vpiRhs: \_constant: , line:25:35, endln:25:36 @@ -2564,7 +2564,7 @@ design: (work@top) |vpiPort: \_port: (a), line:23:41, endln:23:42 |vpiParent: - \_module: work@prim_generic_pad_attr (work@top.gen_dio_attr[2].u_prim_pad_attr.gen_generic.u_impl_generic), file:${SURELOG_DIR}/tests/GenScopeHierPath/dut.sv, line:37:7, endln:39:31 + \_module_inst: work@prim_generic_pad_attr (work@top.gen_dio_attr[2].u_prim_pad_attr.gen_generic.u_impl_generic), file:${SURELOG_DIR}/tests/GenScopeHierPath/dut.sv, line:37:7, endln:39:31 |vpiName:a |vpiDirection:2 |vpiHighConn: @@ -2587,11 +2587,11 @@ design: (work@top) \_int_typespec: , line:23:37, endln:23:40 |vpiSigned:1 |vpiInstance: - \_module: work@prim_generic_pad_attr (work@top.gen_dio_attr[2].u_prim_pad_attr.gen_generic.u_impl_generic), file:${SURELOG_DIR}/tests/GenScopeHierPath/dut.sv, line:37:7, endln:39:31 + \_module_inst: work@prim_generic_pad_attr (work@top.gen_dio_attr[2].u_prim_pad_attr.gen_generic.u_impl_generic), file:${SURELOG_DIR}/tests/GenScopeHierPath/dut.sv, line:37:7, endln:39:31 |vpiGenScopeArray: \_gen_scope_array: (work@top.gen_dio_attr[2].u_prim_pad_attr.gen_generic.u_impl_generic.gen_assign), line:26:4, endln:28:7 |vpiParent: - \_module: work@prim_generic_pad_attr (work@top.gen_dio_attr[2].u_prim_pad_attr.gen_generic.u_impl_generic), file:${SURELOG_DIR}/tests/GenScopeHierPath/dut.sv, line:37:7, endln:39:31 + \_module_inst: work@prim_generic_pad_attr (work@top.gen_dio_attr[2].u_prim_pad_attr.gen_generic.u_impl_generic), file:${SURELOG_DIR}/tests/GenScopeHierPath/dut.sv, line:37:7, endln:39:31 |vpiName:gen_assign |vpiFullName:work@top.gen_dio_attr[2].u_prim_pad_attr.gen_generic.u_impl_generic.gen_assign |vpiGenScope: @@ -2622,7 +2622,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.gen_dio_attr[3]), line:48:41, endln:52:6 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/GenScopeHierPath/dut.sv, line:44:1, endln:53:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/GenScopeHierPath/dut.sv, line:44:1, endln:53:10 |vpiName:gen_dio_attr[3] |vpiFullName:work@top.gen_dio_attr[3] |vpiGenScope: @@ -2640,8 +2640,8 @@ design: (work@top) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@top.gen_dio_attr[3].k - |vpiModule: - \_module: work@prim_pad_attr (work@top.gen_dio_attr[3].u_prim_pad_attr), file:${SURELOG_DIR}/tests/GenScopeHierPath/dut.sv, line:49:6, endln:51:31 + |vpiModuleInst: + \_module_inst: work@prim_pad_attr (work@top.gen_dio_attr[3].u_prim_pad_attr), file:${SURELOG_DIR}/tests/GenScopeHierPath/dut.sv, line:49:6, endln:51:31 |vpiParent: \_gen_scope: (work@top.gen_dio_attr[3]) |vpiName:u_prim_pad_attr @@ -2649,7 +2649,7 @@ design: (work@top) |vpiVariables: \_int_var: (work@top.gen_dio_attr[3].u_prim_pad_attr.b), line:32:33, endln:32:34 |vpiParent: - \_module: work@prim_pad_attr (work@top.gen_dio_attr[3].u_prim_pad_attr), file:${SURELOG_DIR}/tests/GenScopeHierPath/dut.sv, line:49:6, endln:51:31 + \_module_inst: work@prim_pad_attr (work@top.gen_dio_attr[3].u_prim_pad_attr), file:${SURELOG_DIR}/tests/GenScopeHierPath/dut.sv, line:49:6, endln:51:31 |vpiTypespec: \_int_typespec: , line:32:29, endln:32:32 |vpiSigned:1 @@ -2658,7 +2658,7 @@ design: (work@top) |vpiSigned:1 |vpiVisibility:1 |vpiInstance: - \_module: work@prim_pad_attr (work@top.gen_dio_attr[3].u_prim_pad_attr), file:${SURELOG_DIR}/tests/GenScopeHierPath/dut.sv, line:49:6, endln:51:31 + \_module_inst: work@prim_pad_attr (work@top.gen_dio_attr[3].u_prim_pad_attr), file:${SURELOG_DIR}/tests/GenScopeHierPath/dut.sv, line:49:6, endln:51:31 |vpiParameter: \_parameter: (work@top.gen_dio_attr[3].u_prim_pad_attr.PadType), line:34:25, endln:34:32 |vpiParent: @@ -2717,7 +2717,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:34:25, endln:34:36 |vpiParent: - \_module: work@prim_pad_attr (work@top.gen_dio_attr[3].u_prim_pad_attr), file:${SURELOG_DIR}/tests/GenScopeHierPath/dut.sv, line:49:6, endln:51:31 + \_module_inst: work@prim_pad_attr (work@top.gen_dio_attr[3].u_prim_pad_attr), file:${SURELOG_DIR}/tests/GenScopeHierPath/dut.sv, line:49:6, endln:51:31 |vpiOverriden:1 |vpiRhs: \_constant: , line:34:35, endln:34:36 @@ -2739,7 +2739,7 @@ design: (work@top) |vpiPort: \_port: (b), line:32:33, endln:32:34 |vpiParent: - \_module: work@prim_pad_attr (work@top.gen_dio_attr[3].u_prim_pad_attr), file:${SURELOG_DIR}/tests/GenScopeHierPath/dut.sv, line:49:6, endln:51:31 + \_module_inst: work@prim_pad_attr (work@top.gen_dio_attr[3].u_prim_pad_attr), file:${SURELOG_DIR}/tests/GenScopeHierPath/dut.sv, line:49:6, endln:51:31 |vpiName:b |vpiDirection:2 |vpiHighConn: @@ -2762,11 +2762,11 @@ design: (work@top) \_int_typespec: , line:32:29, endln:32:32 |vpiSigned:1 |vpiInstance: - \_module: work@prim_pad_attr (work@top.gen_dio_attr[3].u_prim_pad_attr), file:${SURELOG_DIR}/tests/GenScopeHierPath/dut.sv, line:49:6, endln:51:31 + \_module_inst: work@prim_pad_attr (work@top.gen_dio_attr[3].u_prim_pad_attr), file:${SURELOG_DIR}/tests/GenScopeHierPath/dut.sv, line:49:6, endln:51:31 |vpiGenScopeArray: \_gen_scope_array: (work@top.gen_dio_attr[3].u_prim_pad_attr.gen_generic), line:36:4, endln:40:7 |vpiParent: - \_module: work@prim_pad_attr (work@top.gen_dio_attr[3].u_prim_pad_attr), file:${SURELOG_DIR}/tests/GenScopeHierPath/dut.sv, line:49:6, endln:51:31 + \_module_inst: work@prim_pad_attr (work@top.gen_dio_attr[3].u_prim_pad_attr), file:${SURELOG_DIR}/tests/GenScopeHierPath/dut.sv, line:49:6, endln:51:31 |vpiName:gen_generic |vpiFullName:work@top.gen_dio_attr[3].u_prim_pad_attr.gen_generic |vpiGenScope: @@ -2774,8 +2774,8 @@ design: (work@top) |vpiParent: \_gen_scope_array: (work@top.gen_dio_attr[3].u_prim_pad_attr.gen_generic), line:36:4, endln:40:7 |vpiFullName:work@top.gen_dio_attr[3].u_prim_pad_attr.gen_generic - |vpiModule: - \_module: work@prim_generic_pad_attr (work@top.gen_dio_attr[3].u_prim_pad_attr.gen_generic.u_impl_generic), file:${SURELOG_DIR}/tests/GenScopeHierPath/dut.sv, line:37:7, endln:39:31 + |vpiModuleInst: + \_module_inst: work@prim_generic_pad_attr (work@top.gen_dio_attr[3].u_prim_pad_attr.gen_generic.u_impl_generic), file:${SURELOG_DIR}/tests/GenScopeHierPath/dut.sv, line:37:7, endln:39:31 |vpiParent: \_gen_scope: (work@top.gen_dio_attr[3].u_prim_pad_attr.gen_generic) |vpiName:u_impl_generic @@ -2783,7 +2783,7 @@ design: (work@top) |vpiVariables: \_int_var: (work@top.gen_dio_attr[3].u_prim_pad_attr.gen_generic.u_impl_generic.a), line:23:41, endln:23:42 |vpiParent: - \_module: work@prim_generic_pad_attr (work@top.gen_dio_attr[3].u_prim_pad_attr.gen_generic.u_impl_generic), file:${SURELOG_DIR}/tests/GenScopeHierPath/dut.sv, line:37:7, endln:39:31 + \_module_inst: work@prim_generic_pad_attr (work@top.gen_dio_attr[3].u_prim_pad_attr.gen_generic.u_impl_generic), file:${SURELOG_DIR}/tests/GenScopeHierPath/dut.sv, line:37:7, endln:39:31 |vpiTypespec: \_int_typespec: , line:23:37, endln:23:40 |vpiSigned:1 @@ -2792,7 +2792,7 @@ design: (work@top) |vpiSigned:1 |vpiVisibility:1 |vpiInstance: - \_module: work@prim_generic_pad_attr (work@top.gen_dio_attr[3].u_prim_pad_attr.gen_generic.u_impl_generic), file:${SURELOG_DIR}/tests/GenScopeHierPath/dut.sv, line:37:7, endln:39:31 + \_module_inst: work@prim_generic_pad_attr (work@top.gen_dio_attr[3].u_prim_pad_attr.gen_generic.u_impl_generic), file:${SURELOG_DIR}/tests/GenScopeHierPath/dut.sv, line:37:7, endln:39:31 |vpiParameter: \_parameter: (work@top.gen_dio_attr[3].u_prim_pad_attr.gen_generic.u_impl_generic.PadType), line:25:25, endln:25:32 |vpiParent: @@ -2851,7 +2851,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:25:25, endln:25:36 |vpiParent: - \_module: work@prim_generic_pad_attr (work@top.gen_dio_attr[3].u_prim_pad_attr.gen_generic.u_impl_generic), file:${SURELOG_DIR}/tests/GenScopeHierPath/dut.sv, line:37:7, endln:39:31 + \_module_inst: work@prim_generic_pad_attr (work@top.gen_dio_attr[3].u_prim_pad_attr.gen_generic.u_impl_generic), file:${SURELOG_DIR}/tests/GenScopeHierPath/dut.sv, line:37:7, endln:39:31 |vpiOverriden:1 |vpiRhs: \_constant: , line:25:35, endln:25:36 @@ -2873,7 +2873,7 @@ design: (work@top) |vpiPort: \_port: (a), line:23:41, endln:23:42 |vpiParent: - \_module: work@prim_generic_pad_attr (work@top.gen_dio_attr[3].u_prim_pad_attr.gen_generic.u_impl_generic), file:${SURELOG_DIR}/tests/GenScopeHierPath/dut.sv, line:37:7, endln:39:31 + \_module_inst: work@prim_generic_pad_attr (work@top.gen_dio_attr[3].u_prim_pad_attr.gen_generic.u_impl_generic), file:${SURELOG_DIR}/tests/GenScopeHierPath/dut.sv, line:37:7, endln:39:31 |vpiName:a |vpiDirection:2 |vpiHighConn: @@ -2896,11 +2896,11 @@ design: (work@top) \_int_typespec: , line:23:37, endln:23:40 |vpiSigned:1 |vpiInstance: - \_module: work@prim_generic_pad_attr (work@top.gen_dio_attr[3].u_prim_pad_attr.gen_generic.u_impl_generic), file:${SURELOG_DIR}/tests/GenScopeHierPath/dut.sv, line:37:7, endln:39:31 + \_module_inst: work@prim_generic_pad_attr (work@top.gen_dio_attr[3].u_prim_pad_attr.gen_generic.u_impl_generic), file:${SURELOG_DIR}/tests/GenScopeHierPath/dut.sv, line:37:7, endln:39:31 |vpiGenScopeArray: \_gen_scope_array: (work@top.gen_dio_attr[3].u_prim_pad_attr.gen_generic.u_impl_generic.gen_assign), line:26:4, endln:28:7 |vpiParent: - \_module: work@prim_generic_pad_attr (work@top.gen_dio_attr[3].u_prim_pad_attr.gen_generic.u_impl_generic), file:${SURELOG_DIR}/tests/GenScopeHierPath/dut.sv, line:37:7, endln:39:31 + \_module_inst: work@prim_generic_pad_attr (work@top.gen_dio_attr[3].u_prim_pad_attr.gen_generic.u_impl_generic), file:${SURELOG_DIR}/tests/GenScopeHierPath/dut.sv, line:37:7, endln:39:31 |vpiName:gen_assign |vpiFullName:work@top.gen_dio_attr[3].u_prim_pad_attr.gen_generic.u_impl_generic.gen_assign |vpiGenScope: diff --git a/tests/GenScopeHierPath2/GenScopeHierPath2.log b/tests/GenScopeHierPath2/GenScopeHierPath2.log index e6f9196c4b..3c940e4885 100644 --- a/tests/GenScopeHierPath2/GenScopeHierPath2.log +++ b/tests/GenScopeHierPath2/GenScopeHierPath2.log @@ -377,7 +377,7 @@ hier_path 2 int_typespec 2 logic_net 3 logic_typespec 4 -module 8 +module_inst 8 operation 7 param_assign 2 parameter 2 @@ -399,7 +399,7 @@ hier_path 3 int_typespec 2 logic_net 3 logic_typespec 4 -module 8 +module_inst 8 operation 7 param_assign 2 parameter 2 @@ -421,14 +421,14 @@ design: (work@mod) |vpiElaborated:1 |vpiName:work@mod |uhdmallModules: -\_module: work@mod (work@mod), file:${SURELOG_DIR}/tests/GenScopeHierPath2/dut.sv, line:1:1, endln:25:10 +\_module_inst: work@mod (work@mod), file:${SURELOG_DIR}/tests/GenScopeHierPath2/dut.sv, line:1:1, endln:25:10 |vpiParent: \_design: (work@mod) |vpiFullName:work@mod |vpiParameter: \_parameter: (work@mod.P), line:4:15, endln:4:16 |vpiParent: - \_module: work@mod (work@mod), file:${SURELOG_DIR}/tests/GenScopeHierPath2/dut.sv, line:1:1, endln:25:10 + \_module_inst: work@mod (work@mod), file:${SURELOG_DIR}/tests/GenScopeHierPath2/dut.sv, line:1:1, endln:25:10 |UINT:0 |vpiTypespec: \_int_typespec: @@ -437,7 +437,7 @@ design: (work@mod) |vpiParamAssign: \_param_assign: , line:4:15, endln:4:20 |vpiParent: - \_module: work@mod (work@mod), file:${SURELOG_DIR}/tests/GenScopeHierPath2/dut.sv, line:1:1, endln:25:10 + \_module_inst: work@mod (work@mod), file:${SURELOG_DIR}/tests/GenScopeHierPath2/dut.sv, line:1:1, endln:25:10 |vpiRhs: \_constant: , line:4:19, endln:4:20 |vpiDecompile:0 @@ -452,14 +452,14 @@ design: (work@mod) |vpiNet: \_logic_net: (work@mod.out), line:2:24, endln:2:27 |vpiParent: - \_module: work@mod (work@mod), file:${SURELOG_DIR}/tests/GenScopeHierPath2/dut.sv, line:1:1, endln:25:10 + \_module_inst: work@mod (work@mod), file:${SURELOG_DIR}/tests/GenScopeHierPath2/dut.sv, line:1:1, endln:25:10 |vpiName:out |vpiFullName:work@mod.out |vpiNetType:1 |vpiPort: \_port: (out), line:2:24, endln:2:27 |vpiParent: - \_module: work@mod (work@mod), file:${SURELOG_DIR}/tests/GenScopeHierPath2/dut.sv, line:1:1, endln:25:10 + \_module_inst: work@mod (work@mod), file:${SURELOG_DIR}/tests/GenScopeHierPath2/dut.sv, line:1:1, endln:25:10 |vpiName:out |vpiDirection:2 |vpiLowConn: @@ -487,12 +487,12 @@ design: (work@mod) |UINT:0 |vpiConstType:9 |uhdmtopModules: -\_module: work@mod (work@mod), file:${SURELOG_DIR}/tests/GenScopeHierPath2/dut.sv, line:1:1, endln:25:10 +\_module_inst: work@mod (work@mod), file:${SURELOG_DIR}/tests/GenScopeHierPath2/dut.sv, line:1:1, endln:25:10 |vpiName:work@mod |vpiParameter: \_parameter: (work@mod.P), line:4:15, endln:4:16 |vpiParent: - \_module: work@mod (work@mod), file:${SURELOG_DIR}/tests/GenScopeHierPath2/dut.sv, line:1:1, endln:25:10 + \_module_inst: work@mod (work@mod), file:${SURELOG_DIR}/tests/GenScopeHierPath2/dut.sv, line:1:1, endln:25:10 |UINT:0 |vpiTypespec: \_int_typespec: @@ -503,7 +503,7 @@ design: (work@mod) |vpiParamAssign: \_param_assign: , line:4:15, endln:4:20 |vpiParent: - \_module: work@mod (work@mod), file:${SURELOG_DIR}/tests/GenScopeHierPath2/dut.sv, line:1:1, endln:25:10 + \_module_inst: work@mod (work@mod), file:${SURELOG_DIR}/tests/GenScopeHierPath2/dut.sv, line:1:1, endln:25:10 |vpiRhs: \_constant: , line:4:19, endln:4:20 |vpiDecompile:0 @@ -519,7 +519,7 @@ design: (work@mod) |vpiNet: \_logic_net: (work@mod.out), line:2:24, endln:2:27 |vpiParent: - \_module: work@mod (work@mod), file:${SURELOG_DIR}/tests/GenScopeHierPath2/dut.sv, line:1:1, endln:25:10 + \_module_inst: work@mod (work@mod), file:${SURELOG_DIR}/tests/GenScopeHierPath2/dut.sv, line:1:1, endln:25:10 |vpiTypespec: \_logic_typespec: , line:2:12, endln:2:23 |vpiRange: @@ -547,7 +547,7 @@ design: (work@mod) |vpiPort: \_port: (out), line:2:24, endln:2:27 |vpiParent: - \_module: work@mod (work@mod), file:${SURELOG_DIR}/tests/GenScopeHierPath2/dut.sv, line:1:1, endln:25:10 + \_module_inst: work@mod (work@mod), file:${SURELOG_DIR}/tests/GenScopeHierPath2/dut.sv, line:1:1, endln:25:10 |vpiName:out |vpiDirection:2 |vpiLowConn: @@ -581,11 +581,11 @@ design: (work@mod) |UINT:0 |vpiConstType:9 |vpiInstance: - \_module: work@mod (work@mod), file:${SURELOG_DIR}/tests/GenScopeHierPath2/dut.sv, line:1:1, endln:25:10 + \_module_inst: work@mod (work@mod), file:${SURELOG_DIR}/tests/GenScopeHierPath2/dut.sv, line:1:1, endln:25:10 |vpiGenScopeArray: \_gen_scope_array: (work@mod.blk4), line:14:10, endln:16:8 |vpiParent: - \_module: work@mod (work@mod), file:${SURELOG_DIR}/tests/GenScopeHierPath2/dut.sv, line:1:1, endln:25:10 + \_module_inst: work@mod (work@mod), file:${SURELOG_DIR}/tests/GenScopeHierPath2/dut.sv, line:1:1, endln:25:10 |vpiName:blk4 |vpiFullName:work@mod.blk4 |vpiGenScope: @@ -637,7 +637,7 @@ design: (work@mod) |vpiGenScopeArray: \_gen_scope_array: (work@mod.genblk2), line:17:5, endln:24:36 |vpiParent: - \_module: work@mod (work@mod), file:${SURELOG_DIR}/tests/GenScopeHierPath2/dut.sv, line:1:1, endln:25:10 + \_module_inst: work@mod (work@mod), file:${SURELOG_DIR}/tests/GenScopeHierPath2/dut.sv, line:1:1, endln:25:10 |vpiName:genblk2 |vpiFullName:work@mod.genblk2 |vpiGenScope: diff --git a/tests/GenerateAssigns/GenerateAssigns.log b/tests/GenerateAssigns/GenerateAssigns.log index 8a204475bf..cd7f0b8d78 100644 --- a/tests/GenerateAssigns/GenerateAssigns.log +++ b/tests/GenerateAssigns/GenerateAssigns.log @@ -580,7 +580,7 @@ io_decl 11 logic_net 6 logic_typespec 9 logic_var 1 -module 5 +module_inst 5 operation 3 package 2 param_assign 4 @@ -1011,14 +1011,14 @@ design: (work@dut) \_int_typespec: |vpiSigned:1 |uhdmallModules: -\_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/GenerateAssigns/top.v, line:1:1, endln:43:10 +\_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/GenerateAssigns/top.v, line:1:1, endln:43:10 |vpiParent: \_design: (work@dut) |vpiFullName:work@dut |vpiParameter: \_parameter: (work@dut.p), line:2:13, endln:2:14 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/GenerateAssigns/top.v, line:1:1, endln:43:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/GenerateAssigns/top.v, line:1:1, endln:43:10 |UINT:2 |vpiTypespec: \_int_typespec: @@ -1027,7 +1027,7 @@ design: (work@dut) |vpiParameter: \_parameter: (work@dut.q), line:2:20, endln:2:21 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/GenerateAssigns/top.v, line:1:1, endln:43:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/GenerateAssigns/top.v, line:1:1, endln:43:10 |UINT:4 |vpiTypespec: \_int_typespec: @@ -1036,7 +1036,7 @@ design: (work@dut) |vpiParamAssign: \_param_assign: , line:2:13, endln:2:18 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/GenerateAssigns/top.v, line:1:1, endln:43:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/GenerateAssigns/top.v, line:1:1, endln:43:10 |vpiRhs: \_constant: , line:2:17, endln:2:18 |vpiDecompile:2 @@ -1050,7 +1050,7 @@ design: (work@dut) |vpiParamAssign: \_param_assign: , line:2:20, endln:2:25 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/GenerateAssigns/top.v, line:1:1, endln:43:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/GenerateAssigns/top.v, line:1:1, endln:43:10 |vpiRhs: \_constant: , line:2:24, endln:2:25 |vpiDecompile:4 @@ -1065,25 +1065,25 @@ design: (work@dut) |vpiNet: \_logic_net: (work@dut.a), line:1:18, endln:1:19 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/GenerateAssigns/top.v, line:1:1, endln:43:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/GenerateAssigns/top.v, line:1:1, endln:43:10 |vpiName:a |vpiFullName:work@dut.a |vpiNet: \_logic_net: (work@dut.b), line:1:27, endln:1:28 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/GenerateAssigns/top.v, line:1:1, endln:43:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/GenerateAssigns/top.v, line:1:1, endln:43:10 |vpiName:b |vpiFullName:work@dut.b |vpiNet: \_logic_net: (work@dut.y), line:1:37, endln:1:38 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/GenerateAssigns/top.v, line:1:1, endln:43:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/GenerateAssigns/top.v, line:1:1, endln:43:10 |vpiName:y |vpiFullName:work@dut.y |vpiPort: \_port: (a), line:1:18, endln:1:19 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/GenerateAssigns/top.v, line:1:1, endln:43:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/GenerateAssigns/top.v, line:1:1, endln:43:10 |vpiName:a |vpiDirection:1 |vpiLowConn: @@ -1095,7 +1095,7 @@ design: (work@dut) |vpiPort: \_port: (b), line:1:27, endln:1:28 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/GenerateAssigns/top.v, line:1:1, endln:43:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/GenerateAssigns/top.v, line:1:1, endln:43:10 |vpiName:b |vpiDirection:1 |vpiLowConn: @@ -1107,7 +1107,7 @@ design: (work@dut) |vpiPort: \_port: (y), line:1:37, endln:1:38 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/GenerateAssigns/top.v, line:1:1, endln:43:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/GenerateAssigns/top.v, line:1:1, endln:43:10 |vpiName:y |vpiDirection:2 |vpiLowConn: @@ -1117,12 +1117,12 @@ design: (work@dut) |vpiTypedef: \_logic_typespec: , line:1:37, endln:1:37 |uhdmtopModules: -\_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/GenerateAssigns/top.v, line:1:1, endln:43:10 +\_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/GenerateAssigns/top.v, line:1:1, endln:43:10 |vpiName:work@dut |vpiParameter: \_parameter: (work@dut.p), line:2:13, endln:2:14 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/GenerateAssigns/top.v, line:1:1, endln:43:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/GenerateAssigns/top.v, line:1:1, endln:43:10 |UINT:2 |vpiTypespec: \_int_typespec: @@ -1133,7 +1133,7 @@ design: (work@dut) |vpiParameter: \_parameter: (work@dut.q), line:2:20, endln:2:21 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/GenerateAssigns/top.v, line:1:1, endln:43:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/GenerateAssigns/top.v, line:1:1, endln:43:10 |UINT:4 |vpiTypespec: \_int_typespec: @@ -1144,7 +1144,7 @@ design: (work@dut) |vpiParamAssign: \_param_assign: , line:2:13, endln:2:18 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/GenerateAssigns/top.v, line:1:1, endln:43:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/GenerateAssigns/top.v, line:1:1, endln:43:10 |vpiRhs: \_constant: , line:2:17, endln:2:18 |vpiDecompile:2 @@ -1158,7 +1158,7 @@ design: (work@dut) |vpiParamAssign: \_param_assign: , line:2:20, endln:2:25 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/GenerateAssigns/top.v, line:1:1, endln:43:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/GenerateAssigns/top.v, line:1:1, endln:43:10 |vpiRhs: \_constant: , line:2:24, endln:2:25 |vpiDecompile:4 @@ -1174,7 +1174,7 @@ design: (work@dut) |vpiNet: \_logic_net: (work@dut.a), line:1:18, endln:1:19 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/GenerateAssigns/top.v, line:1:1, endln:43:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/GenerateAssigns/top.v, line:1:1, endln:43:10 |vpiTypespec: \_logic_typespec: , line:1:18, endln:1:18 |vpiName:a @@ -1182,7 +1182,7 @@ design: (work@dut) |vpiNet: \_logic_net: (work@dut.b), line:1:27, endln:1:28 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/GenerateAssigns/top.v, line:1:1, endln:43:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/GenerateAssigns/top.v, line:1:1, endln:43:10 |vpiTypespec: \_logic_typespec: , line:1:27, endln:1:27 |vpiName:b @@ -1190,7 +1190,7 @@ design: (work@dut) |vpiNet: \_logic_net: (work@dut.y), line:1:37, endln:1:38 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/GenerateAssigns/top.v, line:1:1, endln:43:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/GenerateAssigns/top.v, line:1:1, endln:43:10 |vpiTypespec: \_logic_typespec: , line:1:37, endln:1:37 |vpiName:y @@ -1199,7 +1199,7 @@ design: (work@dut) |vpiPort: \_port: (a), line:1:18, endln:1:19 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/GenerateAssigns/top.v, line:1:1, endln:43:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/GenerateAssigns/top.v, line:1:1, endln:43:10 |vpiName:a |vpiDirection:1 |vpiLowConn: @@ -1213,7 +1213,7 @@ design: (work@dut) |vpiPort: \_port: (b), line:1:27, endln:1:28 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/GenerateAssigns/top.v, line:1:1, endln:43:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/GenerateAssigns/top.v, line:1:1, endln:43:10 |vpiName:b |vpiDirection:1 |vpiLowConn: @@ -1227,7 +1227,7 @@ design: (work@dut) |vpiPort: \_port: (y), line:1:37, endln:1:38 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/GenerateAssigns/top.v, line:1:1, endln:43:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/GenerateAssigns/top.v, line:1:1, endln:43:10 |vpiName:y |vpiDirection:2 |vpiLowConn: @@ -1241,7 +1241,7 @@ design: (work@dut) |vpiGenScopeArray: \_gen_scope_array: (work@dut.u2), line:28:5, endln:41:8 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/GenerateAssigns/top.v, line:1:1, endln:43:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/GenerateAssigns/top.v, line:1:1, endln:43:10 |vpiName:u2 |vpiFullName:work@dut.u2 |vpiGenScope: diff --git a/tests/GenerateBlock/GenerateBlock.log b/tests/GenerateBlock/GenerateBlock.log index 0382ba68e9..f0f4b30f82 100644 --- a/tests/GenerateBlock/GenerateBlock.log +++ b/tests/GenerateBlock/GenerateBlock.log @@ -199,7 +199,7 @@ gen_scope_array 6 hier_path 2 logic_net 8 logic_typespec 7 -module 7 +module_inst 7 operation 2 range 11 ref_obj 5 @@ -215,7 +215,7 @@ gen_scope_array 9 hier_path 4 logic_net 8 logic_typespec 7 -module 7 +module_inst 7 operation 4 range 11 ref_obj 10 @@ -233,7 +233,7 @@ design: (work@gen_test9) |vpiElaborated:1 |vpiName:work@gen_test9 |uhdmallModules: -\_module: work@gen_test9 (work@gen_test9), file:${SURELOG_DIR}/tests/GenerateBlock/dut.sv, line:1:1, endln:19:10 +\_module_inst: work@gen_test9 (work@gen_test9), file:${SURELOG_DIR}/tests/GenerateBlock/dut.sv, line:1:1, endln:19:10 |vpiParent: \_design: (work@gen_test9) |vpiFullName:work@gen_test9 @@ -241,19 +241,19 @@ design: (work@gen_test9) |vpiNet: \_logic_net: (work@gen_test9.w), line:2:20, endln:2:21 |vpiParent: - \_module: work@gen_test9 (work@gen_test9), file:${SURELOG_DIR}/tests/GenerateBlock/dut.sv, line:1:1, endln:19:10 + \_module_inst: work@gen_test9 (work@gen_test9), file:${SURELOG_DIR}/tests/GenerateBlock/dut.sv, line:1:1, endln:19:10 |vpiName:w |vpiFullName:work@gen_test9.w |vpiNetType:1 |uhdmtopModules: -\_module: work@gen_test9 (work@gen_test9), file:${SURELOG_DIR}/tests/GenerateBlock/dut.sv, line:1:1, endln:19:10 +\_module_inst: work@gen_test9 (work@gen_test9), file:${SURELOG_DIR}/tests/GenerateBlock/dut.sv, line:1:1, endln:19:10 |vpiName:work@gen_test9 |vpiDefName:work@gen_test9 |vpiTop:1 |vpiNet: \_logic_net: (work@gen_test9.w), line:2:20, endln:2:21 |vpiParent: - \_module: work@gen_test9 (work@gen_test9), file:${SURELOG_DIR}/tests/GenerateBlock/dut.sv, line:1:1, endln:19:10 + \_module_inst: work@gen_test9 (work@gen_test9), file:${SURELOG_DIR}/tests/GenerateBlock/dut.sv, line:1:1, endln:19:10 |vpiTypespec: \_logic_typespec: , line:2:9, endln:2:19 |vpiRange: @@ -281,7 +281,7 @@ design: (work@gen_test9) |vpiGenScopeArray: \_gen_scope_array: (work@gen_test9.A), line:3:9, endln:18:20 |vpiParent: - \_module: work@gen_test9 (work@gen_test9), file:${SURELOG_DIR}/tests/GenerateBlock/dut.sv, line:1:1, endln:19:10 + \_module_inst: work@gen_test9 (work@gen_test9), file:${SURELOG_DIR}/tests/GenerateBlock/dut.sv, line:1:1, endln:19:10 |vpiName:A |vpiFullName:work@gen_test9.A |vpiGenScope: @@ -493,7 +493,7 @@ design: (work@gen_test9) |vpiContAssign: \_cont_assign: , line:2:20, endln:2:21 |vpiParent: - \_module: work@gen_test9 (work@gen_test9), file:${SURELOG_DIR}/tests/GenerateBlock/dut.sv, line:1:1, endln:19:10 + \_module_inst: work@gen_test9 (work@gen_test9), file:${SURELOG_DIR}/tests/GenerateBlock/dut.sv, line:1:1, endln:19:10 |vpiNetDeclAssign:1 |vpiRhs: \_constant: , line:2:24, endln:2:29 diff --git a/tests/GenerateInterface/GenerateInterface.log b/tests/GenerateInterface/GenerateInterface.log index 54be8b71eb..ac72500019 100644 --- a/tests/GenerateInterface/GenerateInterface.log +++ b/tests/GenerateInterface/GenerateInterface.log @@ -797,12 +797,12 @@ gen_scope 14 gen_scope_array 14 int_typespec 38 int_var 4 -interface 6 +interface_inst 6 io_decl 11 logic_net 7 logic_typespec 8 logic_var 4 -module 12 +module_inst 12 operation 30 package 2 param_assign 6 @@ -1234,14 +1234,14 @@ design: (work@top) \_int_typespec: |vpiSigned:1 |uhdmallInterfaces: -\_interface: work@abc_if (work@abc_if), file:${SURELOG_DIR}/tests/GenerateInterface/top.sv, line:1:1, endln:13:13 +\_interface_inst: work@abc_if (work@abc_if), file:${SURELOG_DIR}/tests/GenerateInterface/top.sv, line:1:1, endln:13:13 |vpiParent: \_design: (work@top) |vpiFullName:work@abc_if |vpiParameter: \_parameter: (work@abc_if.NO_Input), line:1:24, endln:1:32 |vpiParent: - \_interface: work@abc_if (work@abc_if), file:${SURELOG_DIR}/tests/GenerateInterface/top.sv, line:1:1, endln:13:13 + \_interface_inst: work@abc_if (work@abc_if), file:${SURELOG_DIR}/tests/GenerateInterface/top.sv, line:1:1, endln:13:13 |UINT:3 |vpiTypespec: \_int_typespec: , line:1:20, endln:1:23 @@ -1253,7 +1253,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:1:24, endln:1:34 |vpiParent: - \_interface: work@abc_if (work@abc_if), file:${SURELOG_DIR}/tests/GenerateInterface/top.sv, line:1:1, endln:13:13 + \_interface_inst: work@abc_if (work@abc_if), file:${SURELOG_DIR}/tests/GenerateInterface/top.sv, line:1:1, endln:13:13 |vpiRhs: \_constant: , line:1:33, endln:1:34 |vpiDecompile:3 @@ -1268,26 +1268,26 @@ design: (work@top) |vpiNet: \_logic_net: (work@abc_if.xyz_o), line:3:26, endln:3:31 |vpiParent: - \_interface: work@abc_if (work@abc_if), file:${SURELOG_DIR}/tests/GenerateInterface/top.sv, line:1:1, endln:13:13 + \_interface_inst: work@abc_if (work@abc_if), file:${SURELOG_DIR}/tests/GenerateInterface/top.sv, line:1:1, endln:13:13 |vpiName:xyz_o |vpiFullName:work@abc_if.xyz_o |vpiNetType:36 |vpiNet: \_logic_net: (work@abc_if.clk_i), line:4:26, endln:4:31 |vpiParent: - \_interface: work@abc_if (work@abc_if), file:${SURELOG_DIR}/tests/GenerateInterface/top.sv, line:1:1, endln:13:13 + \_interface_inst: work@abc_if (work@abc_if), file:${SURELOG_DIR}/tests/GenerateInterface/top.sv, line:1:1, endln:13:13 |vpiName:clk_i |vpiFullName:work@abc_if.clk_i |vpiNetType:36 |uhdmallInterfaces: -\_interface: work@pins_if (work@pins_if), file:${SURELOG_DIR}/tests/GenerateInterface/top.sv, line:22:1, endln:32:13 +\_interface_inst: work@pins_if (work@pins_if), file:${SURELOG_DIR}/tests/GenerateInterface/top.sv, line:22:1, endln:32:13 |vpiParent: \_design: (work@top) |vpiFullName:work@pins_if |vpiParameter: \_parameter: (work@pins_if.Width), line:22:36, endln:22:41 |vpiParent: - \_interface: work@pins_if (work@pins_if), file:${SURELOG_DIR}/tests/GenerateInterface/top.sv, line:22:1, endln:32:13 + \_interface_inst: work@pins_if (work@pins_if), file:${SURELOG_DIR}/tests/GenerateInterface/top.sv, line:22:1, endln:32:13 |UINT:1 |vpiTypespec: \_int_typespec: , line:22:32, endln:22:35 @@ -1300,7 +1300,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:22:36, endln:22:45 |vpiParent: - \_interface: work@pins_if (work@pins_if), file:${SURELOG_DIR}/tests/GenerateInterface/top.sv, line:22:1, endln:32:13 + \_interface_inst: work@pins_if (work@pins_if), file:${SURELOG_DIR}/tests/GenerateInterface/top.sv, line:22:1, endln:32:13 |vpiRhs: \_constant: , line:22:44, endln:22:45 |vpiDecompile:1 @@ -1315,20 +1315,20 @@ design: (work@top) |vpiNet: \_logic_net: (work@pins_if.pins), line:23:21, endln:23:25 |vpiParent: - \_interface: work@pins_if (work@pins_if), file:${SURELOG_DIR}/tests/GenerateInterface/top.sv, line:22:1, endln:32:13 + \_interface_inst: work@pins_if (work@pins_if), file:${SURELOG_DIR}/tests/GenerateInterface/top.sv, line:22:1, endln:32:13 |vpiName:pins |vpiFullName:work@pins_if.pins |vpiNet: \_logic_net: (work@pins_if.pins_o), line:25:21, endln:25:27 |vpiParent: - \_interface: work@pins_if (work@pins_if), file:${SURELOG_DIR}/tests/GenerateInterface/top.sv, line:22:1, endln:32:13 + \_interface_inst: work@pins_if (work@pins_if), file:${SURELOG_DIR}/tests/GenerateInterface/top.sv, line:22:1, endln:32:13 |vpiName:pins_o |vpiFullName:work@pins_if.pins_o |vpiNetType:36 |vpiPort: \_port: (pins), line:23:21, endln:23:25 |vpiParent: - \_interface: work@pins_if (work@pins_if), file:${SURELOG_DIR}/tests/GenerateInterface/top.sv, line:22:1, endln:32:13 + \_interface_inst: work@pins_if (work@pins_if), file:${SURELOG_DIR}/tests/GenerateInterface/top.sv, line:22:1, endln:32:13 |vpiName:pins |vpiDirection:3 |vpiLowConn: @@ -1336,20 +1336,20 @@ design: (work@top) |vpiActual: \_logic_net: (work@pins_if.pins), line:23:21, endln:23:25 |uhdmallModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/GenerateInterface/top.sv, line:16:1, endln:19:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/GenerateInterface/top.sv, line:16:1, endln:19:10 |vpiParent: \_design: (work@top) |vpiFullName:work@top |vpiDefName:work@top |uhdmallModules: -\_module: work@top2 (work@top2), file:${SURELOG_DIR}/tests/GenerateInterface/top.sv, line:34:1, endln:43:10 +\_module_inst: work@top2 (work@top2), file:${SURELOG_DIR}/tests/GenerateInterface/top.sv, line:34:1, endln:43:10 |vpiParent: \_design: (work@top) |vpiFullName:work@top2 |vpiParameter: \_parameter: (work@top2.Width), line:34:30, endln:34:35 |vpiParent: - \_module: work@top2 (work@top2), file:${SURELOG_DIR}/tests/GenerateInterface/top.sv, line:34:1, endln:43:10 + \_module_inst: work@top2 (work@top2), file:${SURELOG_DIR}/tests/GenerateInterface/top.sv, line:34:1, endln:43:10 |UINT:2 |vpiTypespec: \_int_typespec: , line:34:26, endln:34:29 @@ -1362,7 +1362,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:34:30, endln:34:39 |vpiParent: - \_module: work@top2 (work@top2), file:${SURELOG_DIR}/tests/GenerateInterface/top.sv, line:34:1, endln:43:10 + \_module_inst: work@top2 (work@top2), file:${SURELOG_DIR}/tests/GenerateInterface/top.sv, line:34:1, endln:43:10 |vpiRhs: \_constant: , line:34:38, endln:34:39 |vpiDecompile:2 @@ -1377,13 +1377,13 @@ design: (work@top) |vpiNet: \_logic_net: (work@top2.pins), line:34:61, endln:34:65 |vpiParent: - \_module: work@top2 (work@top2), file:${SURELOG_DIR}/tests/GenerateInterface/top.sv, line:34:1, endln:43:10 + \_module_inst: work@top2 (work@top2), file:${SURELOG_DIR}/tests/GenerateInterface/top.sv, line:34:1, endln:43:10 |vpiName:pins |vpiFullName:work@top2.pins |vpiPort: \_port: (pins), line:34:61, endln:34:65 |vpiParent: - \_module: work@top2 (work@top2), file:${SURELOG_DIR}/tests/GenerateInterface/top.sv, line:34:1, endln:43:10 + \_module_inst: work@top2 (work@top2), file:${SURELOG_DIR}/tests/GenerateInterface/top.sv, line:34:1, endln:43:10 |vpiName:pins |vpiDirection:3 |vpiLowConn: @@ -1421,21 +1421,21 @@ design: (work@top) |UINT:0 |vpiConstType:9 |uhdmtopModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/GenerateInterface/top.sv, line:16:1, endln:19:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/GenerateInterface/top.sv, line:16:1, endln:19:10 |vpiName:work@top |vpiDefName:work@top |vpiTop:1 |vpiTopModule:1 - |vpiInterface: - \_interface: work@abc_if (work@top.intf), file:${SURELOG_DIR}/tests/GenerateInterface/top.sv, line:17:3, endln:17:17 + |vpiInterfaceInst: + \_interface_inst: work@abc_if (work@top.intf), file:${SURELOG_DIR}/tests/GenerateInterface/top.sv, line:17:3, endln:17:17 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/GenerateInterface/top.sv, line:16:1, endln:19:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/GenerateInterface/top.sv, line:16:1, endln:19:10 |vpiName:intf |vpiFullName:work@top.intf |vpiVariables: \_logic_var: (work@top.intf.xyz_o), line:3:26, endln:3:31 |vpiParent: - \_interface: work@abc_if (work@top.intf), file:${SURELOG_DIR}/tests/GenerateInterface/top.sv, line:17:3, endln:17:17 + \_interface_inst: work@abc_if (work@top.intf), file:${SURELOG_DIR}/tests/GenerateInterface/top.sv, line:17:3, endln:17:17 |vpiTypespec: \_logic_typespec: , line:3:3, endln:3:25 |vpiRange: @@ -1480,7 +1480,7 @@ design: (work@top) |vpiVariables: \_logic_var: (work@top.intf.clk_i), line:4:26, endln:4:31 |vpiParent: - \_interface: work@abc_if (work@top.intf), file:${SURELOG_DIR}/tests/GenerateInterface/top.sv, line:17:3, endln:17:17 + \_interface_inst: work@abc_if (work@top.intf), file:${SURELOG_DIR}/tests/GenerateInterface/top.sv, line:17:3, endln:17:17 |vpiTypespec: \_logic_typespec: , line:4:3, endln:4:25 |vpiRange: @@ -1525,7 +1525,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.intf.NO_Input), line:1:24, endln:1:32 |vpiParent: - \_interface: work@abc_if (work@top.intf), file:${SURELOG_DIR}/tests/GenerateInterface/top.sv, line:17:3, endln:17:17 + \_interface_inst: work@abc_if (work@top.intf), file:${SURELOG_DIR}/tests/GenerateInterface/top.sv, line:17:3, endln:17:17 |UINT:3 |vpiTypespec: \_int_typespec: , line:1:20, endln:1:23 @@ -1537,7 +1537,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:1:24, endln:1:34 |vpiParent: - \_interface: work@abc_if (work@top.intf), file:${SURELOG_DIR}/tests/GenerateInterface/top.sv, line:17:3, endln:17:17 + \_interface_inst: work@abc_if (work@top.intf), file:${SURELOG_DIR}/tests/GenerateInterface/top.sv, line:17:3, endln:17:17 |vpiRhs: \_constant: , line:1:33, endln:1:34 |vpiDecompile:3 @@ -1552,11 +1552,11 @@ design: (work@top) |vpiDefFile:${SURELOG_DIR}/tests/GenerateInterface/top.sv |vpiDefLineNo:1 |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/GenerateInterface/top.sv, line:16:1, endln:19:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/GenerateInterface/top.sv, line:16:1, endln:19:10 |vpiGenScopeArray: \_gen_scope_array: (work@top.intf.block[0]), line:6:34, endln:10:15 |vpiParent: - \_interface: work@abc_if (work@top.intf), file:${SURELOG_DIR}/tests/GenerateInterface/top.sv, line:17:3, endln:17:17 + \_interface_inst: work@abc_if (work@top.intf), file:${SURELOG_DIR}/tests/GenerateInterface/top.sv, line:17:3, endln:17:17 |vpiName:block[0] |vpiFullName:work@top.intf.block[0] |vpiGenScope: @@ -1600,7 +1600,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.intf.block[1]), line:6:34, endln:10:15 |vpiParent: - \_interface: work@abc_if (work@top.intf), file:${SURELOG_DIR}/tests/GenerateInterface/top.sv, line:17:3, endln:17:17 + \_interface_inst: work@abc_if (work@top.intf), file:${SURELOG_DIR}/tests/GenerateInterface/top.sv, line:17:3, endln:17:17 |vpiName:block[1] |vpiFullName:work@top.intf.block[1] |vpiGenScope: @@ -1644,7 +1644,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.intf.block[2]), line:6:34, endln:10:15 |vpiParent: - \_interface: work@abc_if (work@top.intf), file:${SURELOG_DIR}/tests/GenerateInterface/top.sv, line:17:3, endln:17:17 + \_interface_inst: work@abc_if (work@top.intf), file:${SURELOG_DIR}/tests/GenerateInterface/top.sv, line:17:3, endln:17:17 |vpiName:block[2] |vpiFullName:work@top.intf.block[2] |vpiGenScope: @@ -1686,12 +1686,12 @@ design: (work@top) \_operation: , line:7:25, endln:7:41 |vpiName:i |uhdmtopModules: -\_module: work@top2 (work@top2), file:${SURELOG_DIR}/tests/GenerateInterface/top.sv, line:34:1, endln:43:10 +\_module_inst: work@top2 (work@top2), file:${SURELOG_DIR}/tests/GenerateInterface/top.sv, line:34:1, endln:43:10 |vpiName:work@top2 |vpiParameter: \_parameter: (work@top2.Width), line:34:30, endln:34:35 |vpiParent: - \_module: work@top2 (work@top2), file:${SURELOG_DIR}/tests/GenerateInterface/top.sv, line:34:1, endln:43:10 + \_module_inst: work@top2 (work@top2), file:${SURELOG_DIR}/tests/GenerateInterface/top.sv, line:34:1, endln:43:10 |UINT:2 |vpiTypespec: \_int_typespec: , line:34:26, endln:34:29 @@ -1704,7 +1704,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:34:30, endln:34:39 |vpiParent: - \_module: work@top2 (work@top2), file:${SURELOG_DIR}/tests/GenerateInterface/top.sv, line:34:1, endln:43:10 + \_module_inst: work@top2 (work@top2), file:${SURELOG_DIR}/tests/GenerateInterface/top.sv, line:34:1, endln:43:10 |vpiRhs: \_constant: , line:34:38, endln:34:39 |vpiDecompile:2 @@ -1720,7 +1720,7 @@ design: (work@top) |vpiNet: \_logic_net: (work@top2.pins), line:34:61, endln:34:65 |vpiParent: - \_module: work@top2 (work@top2), file:${SURELOG_DIR}/tests/GenerateInterface/top.sv, line:34:1, endln:43:10 + \_module_inst: work@top2 (work@top2), file:${SURELOG_DIR}/tests/GenerateInterface/top.sv, line:34:1, endln:43:10 |vpiTypespec: \_logic_typespec: , line:34:49, endln:34:60 |vpiRange: @@ -1747,7 +1747,7 @@ design: (work@top) |vpiPort: \_port: (pins), line:34:61, endln:34:65 |vpiParent: - \_module: work@top2 (work@top2), file:${SURELOG_DIR}/tests/GenerateInterface/top.sv, line:34:1, endln:43:10 + \_module_inst: work@top2 (work@top2), file:${SURELOG_DIR}/tests/GenerateInterface/top.sv, line:34:1, endln:43:10 |vpiName:pins |vpiDirection:3 |vpiLowConn: @@ -1778,16 +1778,16 @@ design: (work@top) |vpiSize:64 |UINT:0 |vpiConstType:9 - |vpiInterface: - \_interface: work@pins_if (work@top2.intf), file:${SURELOG_DIR}/tests/GenerateInterface/top.sv, line:35:1, endln:35:39 + |vpiInterfaceInst: + \_interface_inst: work@pins_if (work@top2.intf), file:${SURELOG_DIR}/tests/GenerateInterface/top.sv, line:35:1, endln:35:39 |vpiParent: - \_module: work@top2 (work@top2), file:${SURELOG_DIR}/tests/GenerateInterface/top.sv, line:34:1, endln:43:10 + \_module_inst: work@top2 (work@top2), file:${SURELOG_DIR}/tests/GenerateInterface/top.sv, line:34:1, endln:43:10 |vpiName:intf |vpiFullName:work@top2.intf |vpiVariables: \_logic_var: (work@top2.intf.pins_o), line:25:21, endln:25:27 |vpiParent: - \_interface: work@pins_if (work@top2.intf), file:${SURELOG_DIR}/tests/GenerateInterface/top.sv, line:35:1, endln:35:39 + \_interface_inst: work@pins_if (work@top2.intf), file:${SURELOG_DIR}/tests/GenerateInterface/top.sv, line:35:1, endln:35:39 |vpiTypespec: \_logic_typespec: , line:25:3, endln:25:20 |vpiRange: @@ -1832,7 +1832,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top2.intf.Width), line:22:36, endln:22:41 |vpiParent: - \_interface: work@pins_if (work@top2.intf), file:${SURELOG_DIR}/tests/GenerateInterface/top.sv, line:35:1, endln:35:39 + \_interface_inst: work@pins_if (work@top2.intf), file:${SURELOG_DIR}/tests/GenerateInterface/top.sv, line:35:1, endln:35:39 |UINT:1 |vpiTypespec: \_int_typespec: , line:22:32, endln:22:35 @@ -1845,7 +1845,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:22:36, endln:22:45 |vpiParent: - \_interface: work@pins_if (work@top2.intf), file:${SURELOG_DIR}/tests/GenerateInterface/top.sv, line:35:1, endln:35:39 + \_interface_inst: work@pins_if (work@top2.intf), file:${SURELOG_DIR}/tests/GenerateInterface/top.sv, line:35:1, endln:35:39 |vpiOverriden:1 |vpiRhs: \_constant: , line:22:44, endln:22:45 @@ -1863,7 +1863,7 @@ design: (work@top) |vpiNet: \_logic_net: (work@top2.intf.pins), line:23:21, endln:23:25 |vpiParent: - \_interface: work@pins_if (work@top2.intf), file:${SURELOG_DIR}/tests/GenerateInterface/top.sv, line:35:1, endln:35:39 + \_interface_inst: work@pins_if (work@top2.intf), file:${SURELOG_DIR}/tests/GenerateInterface/top.sv, line:35:1, endln:35:39 |vpiTypespec: \_logic_typespec: , line:23:9, endln:23:20 |vpiRange: @@ -1887,11 +1887,11 @@ design: (work@top) |vpiName:pins |vpiFullName:work@top2.intf.pins |vpiInstance: - \_module: work@top2 (work@top2), file:${SURELOG_DIR}/tests/GenerateInterface/top.sv, line:34:1, endln:43:10 + \_module_inst: work@top2 (work@top2), file:${SURELOG_DIR}/tests/GenerateInterface/top.sv, line:34:1, endln:43:10 |vpiPort: \_port: (pins), line:23:21, endln:23:25 |vpiParent: - \_interface: work@pins_if (work@top2.intf), file:${SURELOG_DIR}/tests/GenerateInterface/top.sv, line:35:1, endln:35:39 + \_interface_inst: work@pins_if (work@top2.intf), file:${SURELOG_DIR}/tests/GenerateInterface/top.sv, line:35:1, endln:35:39 |vpiName:pins |vpiDirection:3 |vpiHighConn: @@ -1931,7 +1931,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top2.intf.each_pin_intf[0]), line:28:40, endln:30:8 |vpiParent: - \_interface: work@pins_if (work@top2.intf), file:${SURELOG_DIR}/tests/GenerateInterface/top.sv, line:35:1, endln:35:39 + \_interface_inst: work@pins_if (work@top2.intf), file:${SURELOG_DIR}/tests/GenerateInterface/top.sv, line:35:1, endln:35:39 |vpiName:each_pin_intf[0] |vpiFullName:work@top2.intf.each_pin_intf[0] |vpiGenScope: @@ -2017,7 +2017,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top2.intf.each_pin_intf[1]), line:28:40, endln:30:8 |vpiParent: - \_interface: work@pins_if (work@top2.intf), file:${SURELOG_DIR}/tests/GenerateInterface/top.sv, line:35:1, endln:35:39 + \_interface_inst: work@pins_if (work@top2.intf), file:${SURELOG_DIR}/tests/GenerateInterface/top.sv, line:35:1, endln:35:39 |vpiName:each_pin_intf[1] |vpiFullName:work@top2.intf.each_pin_intf[1] |vpiGenScope: @@ -2103,7 +2103,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top2.each_pin[0]), line:38:40, endln:40:8 |vpiParent: - \_module: work@top2 (work@top2), file:${SURELOG_DIR}/tests/GenerateInterface/top.sv, line:34:1, endln:43:10 + \_module_inst: work@top2 (work@top2), file:${SURELOG_DIR}/tests/GenerateInterface/top.sv, line:34:1, endln:43:10 |vpiName:each_pin[0] |vpiFullName:work@top2.each_pin[0] |vpiGenScope: @@ -2189,7 +2189,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top2.each_pin[1]), line:38:40, endln:40:8 |vpiParent: - \_module: work@top2 (work@top2), file:${SURELOG_DIR}/tests/GenerateInterface/top.sv, line:34:1, endln:43:10 + \_module_inst: work@top2 (work@top2), file:${SURELOG_DIR}/tests/GenerateInterface/top.sv, line:34:1, endln:43:10 |vpiName:each_pin[1] |vpiFullName:work@top2.each_pin[1] |vpiGenScope: diff --git a/tests/GenerateModule/GenerateModule.log b/tests/GenerateModule/GenerateModule.log index de83330ac9..c762ba3ecc 100644 --- a/tests/GenerateModule/GenerateModule.log +++ b/tests/GenerateModule/GenerateModule.log @@ -790,7 +790,7 @@ io_decl 11 logic_net 4 logic_typespec 6 logic_var 1 -module 25 +module_inst 25 operation 32 package 2 param_assign 4 @@ -1222,14 +1222,14 @@ design: (work@small_test) \_int_typespec: |vpiSigned:1 |uhdmallModules: -\_module: work@small_test (work@small_test), file:${SURELOG_DIR}/tests/GenerateModule/top.v, line:1:1, endln:19:10 +\_module_inst: work@small_test (work@small_test), file:${SURELOG_DIR}/tests/GenerateModule/top.v, line:1:1, endln:19:10 |vpiParent: \_design: (work@small_test) |vpiFullName:work@small_test |vpiParameter: \_parameter: (work@small_test.SIZE), line:3:26, endln:3:30 |vpiParent: - \_module: work@small_test (work@small_test), file:${SURELOG_DIR}/tests/GenerateModule/top.v, line:1:1, endln:19:10 + \_module_inst: work@small_test (work@small_test), file:${SURELOG_DIR}/tests/GenerateModule/top.v, line:1:1, endln:19:10 |UINT:5 |vpiTypespec: \_int_typespec: , line:3:13, endln:3:19 @@ -1259,7 +1259,7 @@ design: (work@small_test) |vpiParamAssign: \_param_assign: , line:3:26, endln:3:34 |vpiParent: - \_module: work@small_test (work@small_test), file:${SURELOG_DIR}/tests/GenerateModule/top.v, line:1:1, endln:19:10 + \_module_inst: work@small_test (work@small_test), file:${SURELOG_DIR}/tests/GenerateModule/top.v, line:1:1, endln:19:10 |vpiRhs: \_constant: , line:3:33, endln:3:34 |vpiDecompile:5 @@ -1272,14 +1272,14 @@ design: (work@small_test) \_parameter: (work@small_test.SIZE), line:3:26, endln:3:30 |vpiDefName:work@small_test |uhdmallModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/GenerateModule/top.v, line:21:1, endln:26:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/GenerateModule/top.v, line:21:1, endln:26:10 |vpiParent: \_design: (work@small_test) |vpiFullName:work@top |vpiParameter: \_parameter: (work@top.toto), line:22:13, endln:22:17 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/GenerateModule/top.v, line:21:1, endln:26:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/GenerateModule/top.v, line:21:1, endln:26:10 |BIN:1 |vpiTypespec: \_int_typespec: @@ -1296,7 +1296,7 @@ design: (work@small_test) |vpiParamAssign: \_param_assign: , line:22:13, endln:22:24 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/GenerateModule/top.v, line:21:1, endln:26:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/GenerateModule/top.v, line:21:1, endln:26:10 |vpiRhs: \_constant: , line:22:20, endln:22:24 |vpiDecompile:1'b1 @@ -1311,19 +1311,19 @@ design: (work@small_test) |vpiNet: \_logic_net: (work@top.a), line:21:24, endln:21:25 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/GenerateModule/top.v, line:21:1, endln:26:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/GenerateModule/top.v, line:21:1, endln:26:10 |vpiName:a |vpiFullName:work@top.a |vpiNet: \_logic_net: (work@top.b), line:21:40, endln:21:41 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/GenerateModule/top.v, line:21:1, endln:26:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/GenerateModule/top.v, line:21:1, endln:26:10 |vpiName:b |vpiFullName:work@top.b |vpiPort: \_port: (a), line:21:24, endln:21:25 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/GenerateModule/top.v, line:21:1, endln:26:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/GenerateModule/top.v, line:21:1, endln:26:10 |vpiName:a |vpiDirection:1 |vpiLowConn: @@ -1353,7 +1353,7 @@ design: (work@small_test) |vpiPort: \_port: (b), line:21:40, endln:21:41 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/GenerateModule/top.v, line:21:1, endln:26:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/GenerateModule/top.v, line:21:1, endln:26:10 |vpiName:b |vpiDirection:2 |vpiLowConn: @@ -1381,12 +1381,12 @@ design: (work@small_test) |UINT:0 |vpiConstType:9 |uhdmtopModules: -\_module: work@small_test (work@small_test), file:${SURELOG_DIR}/tests/GenerateModule/top.v, line:1:1, endln:19:10 +\_module_inst: work@small_test (work@small_test), file:${SURELOG_DIR}/tests/GenerateModule/top.v, line:1:1, endln:19:10 |vpiName:work@small_test |vpiParameter: \_parameter: (work@small_test.SIZE), line:3:26, endln:3:30 |vpiParent: - \_module: work@small_test (work@small_test), file:${SURELOG_DIR}/tests/GenerateModule/top.v, line:1:1, endln:19:10 + \_module_inst: work@small_test (work@small_test), file:${SURELOG_DIR}/tests/GenerateModule/top.v, line:1:1, endln:19:10 |UINT:5 |vpiTypespec: \_int_typespec: , line:3:13, endln:3:19 @@ -1418,7 +1418,7 @@ design: (work@small_test) |vpiParamAssign: \_param_assign: , line:3:26, endln:3:34 |vpiParent: - \_module: work@small_test (work@small_test), file:${SURELOG_DIR}/tests/GenerateModule/top.v, line:1:1, endln:19:10 + \_module_inst: work@small_test (work@small_test), file:${SURELOG_DIR}/tests/GenerateModule/top.v, line:1:1, endln:19:10 |vpiRhs: \_constant: , line:3:33, endln:3:34 |vpiDecompile:5 @@ -1435,7 +1435,7 @@ design: (work@small_test) |vpiGenScopeArray: \_gen_scope_array: (work@small_test.B1[0]), line:7:30, endln:16:8 |vpiParent: - \_module: work@small_test (work@small_test), file:${SURELOG_DIR}/tests/GenerateModule/top.v, line:1:1, endln:19:10 + \_module_inst: work@small_test (work@small_test), file:${SURELOG_DIR}/tests/GenerateModule/top.v, line:1:1, endln:19:10 |vpiName:B1[0] |vpiFullName:work@small_test.B1[0] |vpiGenScope: @@ -1453,8 +1453,8 @@ design: (work@small_test) |vpiLocalParam:1 |vpiName:i |vpiFullName:work@small_test.B1[0].i - |vpiModule: - \_module: work@small_test.B1[0]::M1 (work@small_test.B1[0].N1), file:${SURELOG_DIR}/tests/GenerateModule/top.v, line:9:9, endln:9:17 + |vpiModuleInst: + \_module_inst: work@small_test.B1[0]::M1 (work@small_test.B1[0].N1), file:${SURELOG_DIR}/tests/GenerateModule/top.v, line:9:9, endln:9:17 |vpiParent: \_gen_scope: (work@small_test.B1[0]) |vpiName:N1 @@ -1463,7 +1463,7 @@ design: (work@small_test) |vpiGenScopeArray: \_gen_scope_array: (work@small_test.B1[1]), line:7:30, endln:16:8 |vpiParent: - \_module: work@small_test (work@small_test), file:${SURELOG_DIR}/tests/GenerateModule/top.v, line:1:1, endln:19:10 + \_module_inst: work@small_test (work@small_test), file:${SURELOG_DIR}/tests/GenerateModule/top.v, line:1:1, endln:19:10 |vpiName:B1[1] |vpiFullName:work@small_test.B1[1] |vpiGenScope: @@ -1481,8 +1481,8 @@ design: (work@small_test) |vpiLocalParam:1 |vpiName:i |vpiFullName:work@small_test.B1[1].i - |vpiModule: - \_module: work@small_test.B1[1]::M1 (work@small_test.B1[1].N1), file:${SURELOG_DIR}/tests/GenerateModule/top.v, line:9:9, endln:9:17 + |vpiModuleInst: + \_module_inst: work@small_test.B1[1]::M1 (work@small_test.B1[1].N1), file:${SURELOG_DIR}/tests/GenerateModule/top.v, line:9:9, endln:9:17 |vpiParent: \_gen_scope: (work@small_test.B1[1]) |vpiName:N1 @@ -1520,8 +1520,8 @@ design: (work@small_test) |vpiLocalParam:1 |vpiName:m |vpiFullName:work@small_test.B1[1].B4.B5[1].m - |vpiModule: - \_module: work@small_test.B1[1].B4.B5[1]::M4 (work@small_test.B1[1].B4.B5[1].N4), file:${SURELOG_DIR}/tests/GenerateModule/top.v, line:13:17, endln:13:25 + |vpiModuleInst: + \_module_inst: work@small_test.B1[1].B4.B5[1]::M4 (work@small_test.B1[1].B4.B5[1].N4), file:${SURELOG_DIR}/tests/GenerateModule/top.v, line:13:17, endln:13:25 |vpiParent: \_gen_scope: (work@small_test.B1[1].B4.B5[1]) |vpiName:N4 @@ -1548,8 +1548,8 @@ design: (work@small_test) |vpiLocalParam:1 |vpiName:m |vpiFullName:work@small_test.B1[1].B4.B5[2].m - |vpiModule: - \_module: work@small_test.B1[1].B4.B5[2]::M4 (work@small_test.B1[1].B4.B5[2].N4), file:${SURELOG_DIR}/tests/GenerateModule/top.v, line:13:17, endln:13:25 + |vpiModuleInst: + \_module_inst: work@small_test.B1[1].B4.B5[2]::M4 (work@small_test.B1[1].B4.B5[2].N4), file:${SURELOG_DIR}/tests/GenerateModule/top.v, line:13:17, endln:13:25 |vpiParent: \_gen_scope: (work@small_test.B1[1].B4.B5[2]) |vpiName:N4 @@ -1576,8 +1576,8 @@ design: (work@small_test) |vpiLocalParam:1 |vpiName:m |vpiFullName:work@small_test.B1[1].B4.B5[3].m - |vpiModule: - \_module: work@small_test.B1[1].B4.B5[3]::M4 (work@small_test.B1[1].B4.B5[3].N4), file:${SURELOG_DIR}/tests/GenerateModule/top.v, line:13:17, endln:13:25 + |vpiModuleInst: + \_module_inst: work@small_test.B1[1].B4.B5[3]::M4 (work@small_test.B1[1].B4.B5[3].N4), file:${SURELOG_DIR}/tests/GenerateModule/top.v, line:13:17, endln:13:25 |vpiParent: \_gen_scope: (work@small_test.B1[1].B4.B5[3]) |vpiName:N4 @@ -1604,8 +1604,8 @@ design: (work@small_test) |vpiLocalParam:1 |vpiName:m |vpiFullName:work@small_test.B1[1].B4.B5[4].m - |vpiModule: - \_module: work@small_test.B1[1].B4.B5[4]::M4 (work@small_test.B1[1].B4.B5[4].N4), file:${SURELOG_DIR}/tests/GenerateModule/top.v, line:13:17, endln:13:25 + |vpiModuleInst: + \_module_inst: work@small_test.B1[1].B4.B5[4]::M4 (work@small_test.B1[1].B4.B5[4].N4), file:${SURELOG_DIR}/tests/GenerateModule/top.v, line:13:17, endln:13:25 |vpiParent: \_gen_scope: (work@small_test.B1[1].B4.B5[4]) |vpiName:N4 @@ -1614,7 +1614,7 @@ design: (work@small_test) |vpiGenScopeArray: \_gen_scope_array: (work@small_test.B1[2]), line:7:30, endln:16:8 |vpiParent: - \_module: work@small_test (work@small_test), file:${SURELOG_DIR}/tests/GenerateModule/top.v, line:1:1, endln:19:10 + \_module_inst: work@small_test (work@small_test), file:${SURELOG_DIR}/tests/GenerateModule/top.v, line:1:1, endln:19:10 |vpiName:B1[2] |vpiFullName:work@small_test.B1[2] |vpiGenScope: @@ -1632,8 +1632,8 @@ design: (work@small_test) |vpiLocalParam:1 |vpiName:i |vpiFullName:work@small_test.B1[2].i - |vpiModule: - \_module: work@small_test.B1[2]::M1 (work@small_test.B1[2].N1), file:${SURELOG_DIR}/tests/GenerateModule/top.v, line:9:9, endln:9:17 + |vpiModuleInst: + \_module_inst: work@small_test.B1[2]::M1 (work@small_test.B1[2].N1), file:${SURELOG_DIR}/tests/GenerateModule/top.v, line:9:9, endln:9:17 |vpiParent: \_gen_scope: (work@small_test.B1[2]) |vpiName:N1 @@ -1671,8 +1671,8 @@ design: (work@small_test) |vpiLocalParam:1 |vpiName:m |vpiFullName:work@small_test.B1[2].B4.B5[2].m - |vpiModule: - \_module: work@small_test.B1[2].B4.B5[2]::M4 (work@small_test.B1[2].B4.B5[2].N4), file:${SURELOG_DIR}/tests/GenerateModule/top.v, line:13:17, endln:13:25 + |vpiModuleInst: + \_module_inst: work@small_test.B1[2].B4.B5[2]::M4 (work@small_test.B1[2].B4.B5[2].N4), file:${SURELOG_DIR}/tests/GenerateModule/top.v, line:13:17, endln:13:25 |vpiParent: \_gen_scope: (work@small_test.B1[2].B4.B5[2]) |vpiName:N4 @@ -1699,8 +1699,8 @@ design: (work@small_test) |vpiLocalParam:1 |vpiName:m |vpiFullName:work@small_test.B1[2].B4.B5[3].m - |vpiModule: - \_module: work@small_test.B1[2].B4.B5[3]::M4 (work@small_test.B1[2].B4.B5[3].N4), file:${SURELOG_DIR}/tests/GenerateModule/top.v, line:13:17, endln:13:25 + |vpiModuleInst: + \_module_inst: work@small_test.B1[2].B4.B5[3]::M4 (work@small_test.B1[2].B4.B5[3].N4), file:${SURELOG_DIR}/tests/GenerateModule/top.v, line:13:17, endln:13:25 |vpiParent: \_gen_scope: (work@small_test.B1[2].B4.B5[3]) |vpiName:N4 @@ -1727,8 +1727,8 @@ design: (work@small_test) |vpiLocalParam:1 |vpiName:m |vpiFullName:work@small_test.B1[2].B4.B5[4].m - |vpiModule: - \_module: work@small_test.B1[2].B4.B5[4]::M4 (work@small_test.B1[2].B4.B5[4].N4), file:${SURELOG_DIR}/tests/GenerateModule/top.v, line:13:17, endln:13:25 + |vpiModuleInst: + \_module_inst: work@small_test.B1[2].B4.B5[4]::M4 (work@small_test.B1[2].B4.B5[4].N4), file:${SURELOG_DIR}/tests/GenerateModule/top.v, line:13:17, endln:13:25 |vpiParent: \_gen_scope: (work@small_test.B1[2].B4.B5[4]) |vpiName:N4 @@ -1737,7 +1737,7 @@ design: (work@small_test) |vpiGenScopeArray: \_gen_scope_array: (work@small_test.B1[3]), line:7:30, endln:16:8 |vpiParent: - \_module: work@small_test (work@small_test), file:${SURELOG_DIR}/tests/GenerateModule/top.v, line:1:1, endln:19:10 + \_module_inst: work@small_test (work@small_test), file:${SURELOG_DIR}/tests/GenerateModule/top.v, line:1:1, endln:19:10 |vpiName:B1[3] |vpiFullName:work@small_test.B1[3] |vpiGenScope: @@ -1755,8 +1755,8 @@ design: (work@small_test) |vpiLocalParam:1 |vpiName:i |vpiFullName:work@small_test.B1[3].i - |vpiModule: - \_module: work@small_test.B1[3]::M1 (work@small_test.B1[3].N1), file:${SURELOG_DIR}/tests/GenerateModule/top.v, line:9:9, endln:9:17 + |vpiModuleInst: + \_module_inst: work@small_test.B1[3]::M1 (work@small_test.B1[3].N1), file:${SURELOG_DIR}/tests/GenerateModule/top.v, line:9:9, endln:9:17 |vpiParent: \_gen_scope: (work@small_test.B1[3]) |vpiName:N1 @@ -1794,8 +1794,8 @@ design: (work@small_test) |vpiLocalParam:1 |vpiName:m |vpiFullName:work@small_test.B1[3].B4.B5[3].m - |vpiModule: - \_module: work@small_test.B1[3].B4.B5[3]::M4 (work@small_test.B1[3].B4.B5[3].N4), file:${SURELOG_DIR}/tests/GenerateModule/top.v, line:13:17, endln:13:25 + |vpiModuleInst: + \_module_inst: work@small_test.B1[3].B4.B5[3]::M4 (work@small_test.B1[3].B4.B5[3].N4), file:${SURELOG_DIR}/tests/GenerateModule/top.v, line:13:17, endln:13:25 |vpiParent: \_gen_scope: (work@small_test.B1[3].B4.B5[3]) |vpiName:N4 @@ -1822,8 +1822,8 @@ design: (work@small_test) |vpiLocalParam:1 |vpiName:m |vpiFullName:work@small_test.B1[3].B4.B5[4].m - |vpiModule: - \_module: work@small_test.B1[3].B4.B5[4]::M4 (work@small_test.B1[3].B4.B5[4].N4), file:${SURELOG_DIR}/tests/GenerateModule/top.v, line:13:17, endln:13:25 + |vpiModuleInst: + \_module_inst: work@small_test.B1[3].B4.B5[4]::M4 (work@small_test.B1[3].B4.B5[4].N4), file:${SURELOG_DIR}/tests/GenerateModule/top.v, line:13:17, endln:13:25 |vpiParent: \_gen_scope: (work@small_test.B1[3].B4.B5[4]) |vpiName:N4 @@ -1832,7 +1832,7 @@ design: (work@small_test) |vpiGenScopeArray: \_gen_scope_array: (work@small_test.B1[4]), line:7:30, endln:16:8 |vpiParent: - \_module: work@small_test (work@small_test), file:${SURELOG_DIR}/tests/GenerateModule/top.v, line:1:1, endln:19:10 + \_module_inst: work@small_test (work@small_test), file:${SURELOG_DIR}/tests/GenerateModule/top.v, line:1:1, endln:19:10 |vpiName:B1[4] |vpiFullName:work@small_test.B1[4] |vpiGenScope: @@ -1850,8 +1850,8 @@ design: (work@small_test) |vpiLocalParam:1 |vpiName:i |vpiFullName:work@small_test.B1[4].i - |vpiModule: - \_module: work@small_test.B1[4]::M1 (work@small_test.B1[4].N1), file:${SURELOG_DIR}/tests/GenerateModule/top.v, line:9:9, endln:9:17 + |vpiModuleInst: + \_module_inst: work@small_test.B1[4]::M1 (work@small_test.B1[4].N1), file:${SURELOG_DIR}/tests/GenerateModule/top.v, line:9:9, endln:9:17 |vpiParent: \_gen_scope: (work@small_test.B1[4]) |vpiName:N1 @@ -1889,20 +1889,20 @@ design: (work@small_test) |vpiLocalParam:1 |vpiName:m |vpiFullName:work@small_test.B1[4].B4.B5[4].m - |vpiModule: - \_module: work@small_test.B1[4].B4.B5[4]::M4 (work@small_test.B1[4].B4.B5[4].N4), file:${SURELOG_DIR}/tests/GenerateModule/top.v, line:13:17, endln:13:25 + |vpiModuleInst: + \_module_inst: work@small_test.B1[4].B4.B5[4]::M4 (work@small_test.B1[4].B4.B5[4].N4), file:${SURELOG_DIR}/tests/GenerateModule/top.v, line:13:17, endln:13:25 |vpiParent: \_gen_scope: (work@small_test.B1[4].B4.B5[4]) |vpiName:N4 |vpiFullName:work@small_test.B1[4].B4.B5[4].N4 |vpiDefName:work@small_test.B1[4].B4.B5[4]::M4 |uhdmtopModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/GenerateModule/top.v, line:21:1, endln:26:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/GenerateModule/top.v, line:21:1, endln:26:10 |vpiName:work@top |vpiParameter: \_parameter: (work@top.toto), line:22:13, endln:22:17 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/GenerateModule/top.v, line:21:1, endln:26:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/GenerateModule/top.v, line:21:1, endln:26:10 |BIN:1 |vpiTypespec: \_int_typespec: @@ -1927,7 +1927,7 @@ design: (work@small_test) |vpiParamAssign: \_param_assign: , line:22:13, endln:22:24 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/GenerateModule/top.v, line:21:1, endln:26:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/GenerateModule/top.v, line:21:1, endln:26:10 |vpiRhs: \_constant: , line:22:20, endln:22:24 |vpiDecompile:1'b1 @@ -1943,7 +1943,7 @@ design: (work@small_test) |vpiNet: \_logic_net: (work@top.a), line:21:24, endln:21:25 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/GenerateModule/top.v, line:21:1, endln:26:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/GenerateModule/top.v, line:21:1, endln:26:10 |vpiTypespec: \_logic_typespec: , line:21:18, endln:21:23 |vpiRange: @@ -1969,7 +1969,7 @@ design: (work@small_test) |vpiNet: \_logic_net: (work@top.b), line:21:40, endln:21:41 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/GenerateModule/top.v, line:21:1, endln:26:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/GenerateModule/top.v, line:21:1, endln:26:10 |vpiTypespec: \_logic_typespec: , line:21:34, endln:21:39 |vpiRange: @@ -1996,7 +1996,7 @@ design: (work@small_test) |vpiPort: \_port: (a), line:21:24, endln:21:25 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/GenerateModule/top.v, line:21:1, endln:26:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/GenerateModule/top.v, line:21:1, endln:26:10 |vpiName:a |vpiDirection:1 |vpiLowConn: @@ -2030,7 +2030,7 @@ design: (work@small_test) |vpiPort: \_port: (b), line:21:40, endln:21:41 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/GenerateModule/top.v, line:21:1, endln:26:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/GenerateModule/top.v, line:21:1, endln:26:10 |vpiName:b |vpiDirection:2 |vpiLowConn: @@ -2064,7 +2064,7 @@ design: (work@small_test) |vpiGenScopeArray: \_gen_scope_array: (work@top.genblk1[0]), line:23:30, endln:25:6 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/GenerateModule/top.v, line:21:1, endln:26:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/GenerateModule/top.v, line:21:1, endln:26:10 |vpiName:genblk1[0] |vpiFullName:work@top.genblk1[0] |vpiGenScope: @@ -2134,7 +2134,7 @@ design: (work@small_test) |vpiGenScopeArray: \_gen_scope_array: (work@top.genblk1[1]), line:23:30, endln:25:6 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/GenerateModule/top.v, line:21:1, endln:26:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/GenerateModule/top.v, line:21:1, endln:26:10 |vpiName:genblk1[1] |vpiFullName:work@top.genblk1[1] |vpiGenScope: @@ -2204,7 +2204,7 @@ design: (work@small_test) |vpiGenScopeArray: \_gen_scope_array: (work@top.genblk1[2]), line:23:30, endln:25:6 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/GenerateModule/top.v, line:21:1, endln:26:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/GenerateModule/top.v, line:21:1, endln:26:10 |vpiName:genblk1[2] |vpiFullName:work@top.genblk1[2] |vpiGenScope: diff --git a/tests/GenerateRegion/GenerateRegion.log b/tests/GenerateRegion/GenerateRegion.log index 9eaffd76ba..369de4b0e6 100644 --- a/tests/GenerateRegion/GenerateRegion.log +++ b/tests/GenerateRegion/GenerateRegion.log @@ -1166,7 +1166,7 @@ if_else 1 int_typespec 36 logic_net 16 logic_typespec 17 -module 31 +module_inst 31 operation 46 param_assign 26 parameter 33 @@ -1195,7 +1195,7 @@ if_else 2 int_typespec 36 logic_net 16 logic_typespec 17 -module 35 +module_inst 35 operation 66 param_assign 26 parameter 33 @@ -1219,13 +1219,13 @@ design: (work@oh_delay) |vpiElaborated:1 |vpiName:work@oh_delay |uhdmallModules: -\_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/GenerateRegion/dut.sv, line:69:1, endln:74:10 +\_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/GenerateRegion/dut.sv, line:69:1, endln:74:10 |vpiParent: \_design: (work@oh_delay) |vpiFullName:work@dut |vpiDefName:work@dut |uhdmallModules: -\_module: work@gen_test9 (work@gen_test9), file:${SURELOG_DIR}/tests/GenerateRegion/dut.sv, line:46:1, endln:64:10 +\_module_inst: work@gen_test9 (work@gen_test9), file:${SURELOG_DIR}/tests/GenerateRegion/dut.sv, line:46:1, endln:64:10 |vpiParent: \_design: (work@oh_delay) |vpiFullName:work@gen_test9 @@ -1233,19 +1233,19 @@ design: (work@oh_delay) |vpiNet: \_logic_net: (work@gen_test9.w), line:47:20, endln:47:21 |vpiParent: - \_module: work@gen_test9 (work@gen_test9), file:${SURELOG_DIR}/tests/GenerateRegion/dut.sv, line:46:1, endln:64:10 + \_module_inst: work@gen_test9 (work@gen_test9), file:${SURELOG_DIR}/tests/GenerateRegion/dut.sv, line:46:1, endln:64:10 |vpiName:w |vpiFullName:work@gen_test9.w |vpiNetType:1 |uhdmallModules: -\_module: work@oh_delay (work@oh_delay), file:${SURELOG_DIR}/tests/GenerateRegion/dut.sv, line:1:1, endln:20:10 +\_module_inst: work@oh_delay (work@oh_delay), file:${SURELOG_DIR}/tests/GenerateRegion/dut.sv, line:1:1, endln:20:10 |vpiParent: \_design: (work@oh_delay) |vpiFullName:work@oh_delay |vpiParameter: \_parameter: (work@oh_delay.N), line:2:13, endln:2:14 |vpiParent: - \_module: work@oh_delay (work@oh_delay), file:${SURELOG_DIR}/tests/GenerateRegion/dut.sv, line:1:1, endln:20:10 + \_module_inst: work@oh_delay (work@oh_delay), file:${SURELOG_DIR}/tests/GenerateRegion/dut.sv, line:1:1, endln:20:10 |UINT:1 |vpiTypespec: \_int_typespec: @@ -1254,7 +1254,7 @@ design: (work@oh_delay) |vpiParameter: \_parameter: (work@oh_delay.MAXDELAY), line:3:13, endln:3:21 |vpiParent: - \_module: work@oh_delay (work@oh_delay), file:${SURELOG_DIR}/tests/GenerateRegion/dut.sv, line:1:1, endln:20:10 + \_module_inst: work@oh_delay (work@oh_delay), file:${SURELOG_DIR}/tests/GenerateRegion/dut.sv, line:1:1, endln:20:10 |UINT:4 |vpiTypespec: \_int_typespec: @@ -1263,13 +1263,13 @@ design: (work@oh_delay) |vpiParameter: \_parameter: (work@oh_delay.M), line:4:13, endln:4:14 |vpiParent: - \_module: work@oh_delay (work@oh_delay), file:${SURELOG_DIR}/tests/GenerateRegion/dut.sv, line:1:1, endln:20:10 + \_module_inst: work@oh_delay (work@oh_delay), file:${SURELOG_DIR}/tests/GenerateRegion/dut.sv, line:1:1, endln:20:10 |vpiName:M |vpiFullName:work@oh_delay.M |vpiParamAssign: \_param_assign: , line:2:13, endln:2:25 |vpiParent: - \_module: work@oh_delay (work@oh_delay), file:${SURELOG_DIR}/tests/GenerateRegion/dut.sv, line:1:1, endln:20:10 + \_module_inst: work@oh_delay (work@oh_delay), file:${SURELOG_DIR}/tests/GenerateRegion/dut.sv, line:1:1, endln:20:10 |vpiRhs: \_constant: , line:2:24, endln:2:25 |vpiDecompile:1 @@ -1283,7 +1283,7 @@ design: (work@oh_delay) |vpiParamAssign: \_param_assign: , line:3:13, endln:3:25 |vpiParent: - \_module: work@oh_delay (work@oh_delay), file:${SURELOG_DIR}/tests/GenerateRegion/dut.sv, line:1:1, endln:20:10 + \_module_inst: work@oh_delay (work@oh_delay), file:${SURELOG_DIR}/tests/GenerateRegion/dut.sv, line:1:1, endln:20:10 |vpiRhs: \_constant: , line:3:24, endln:3:25 |vpiDecompile:4 @@ -1297,7 +1297,7 @@ design: (work@oh_delay) |vpiParamAssign: \_param_assign: , line:4:13, endln:4:40 |vpiParent: - \_module: work@oh_delay (work@oh_delay), file:${SURELOG_DIR}/tests/GenerateRegion/dut.sv, line:1:1, endln:20:10 + \_module_inst: work@oh_delay (work@oh_delay), file:${SURELOG_DIR}/tests/GenerateRegion/dut.sv, line:1:1, endln:20:10 |vpiRhs: \_sys_func_call: ($clog2), line:4:24, endln:4:40 |vpiArgument: @@ -1312,7 +1312,7 @@ design: (work@oh_delay) |vpiProcess: \_always: , line:12:5, endln:13:31 |vpiParent: - \_module: work@oh_delay (work@oh_delay), file:${SURELOG_DIR}/tests/GenerateRegion/dut.sv, line:1:1, endln:20:10 + \_module_inst: work@oh_delay (work@oh_delay), file:${SURELOG_DIR}/tests/GenerateRegion/dut.sv, line:1:1, endln:20:10 |vpiStmt: \_event_control: , line:12:12, endln:12:27 |vpiParent: @@ -1390,14 +1390,14 @@ design: (work@oh_delay) |vpiConstType:9 |vpiAlwaysType:1 |uhdmallModules: -\_module: work@oh_rsync (work@oh_rsync), file:${SURELOG_DIR}/tests/GenerateRegion/dut.sv, line:93:1, endln:123:10 +\_module_inst: work@oh_rsync (work@oh_rsync), file:${SURELOG_DIR}/tests/GenerateRegion/dut.sv, line:93:1, endln:123:10 |vpiParent: \_design: (work@oh_delay) |vpiFullName:work@oh_rsync |vpiParameter: \_parameter: (work@oh_rsync.SYNCPIPE), line:94:15, endln:94:23 |vpiParent: - \_module: work@oh_rsync (work@oh_rsync), file:${SURELOG_DIR}/tests/GenerateRegion/dut.sv, line:93:1, endln:123:10 + \_module_inst: work@oh_rsync (work@oh_rsync), file:${SURELOG_DIR}/tests/GenerateRegion/dut.sv, line:93:1, endln:123:10 |UINT:2 |vpiTypespec: \_int_typespec: @@ -1406,7 +1406,7 @@ design: (work@oh_delay) |vpiParameter: \_parameter: (work@oh_rsync.SYN), line:95:15, endln:95:18 |vpiParent: - \_module: work@oh_rsync (work@oh_rsync), file:${SURELOG_DIR}/tests/GenerateRegion/dut.sv, line:93:1, endln:123:10 + \_module_inst: work@oh_rsync (work@oh_rsync), file:${SURELOG_DIR}/tests/GenerateRegion/dut.sv, line:93:1, endln:123:10 |STRING:TRUE |vpiTypespec: \_string_typespec: @@ -1415,7 +1415,7 @@ design: (work@oh_delay) |vpiParameter: \_parameter: (work@oh_rsync.TYPE), line:96:15, endln:96:19 |vpiParent: - \_module: work@oh_rsync (work@oh_rsync), file:${SURELOG_DIR}/tests/GenerateRegion/dut.sv, line:93:1, endln:123:10 + \_module_inst: work@oh_rsync (work@oh_rsync), file:${SURELOG_DIR}/tests/GenerateRegion/dut.sv, line:93:1, endln:123:10 |STRING:DEFAULT |vpiTypespec: \_string_typespec: @@ -1424,7 +1424,7 @@ design: (work@oh_delay) |vpiParamAssign: \_param_assign: , line:94:15, endln:94:27 |vpiParent: - \_module: work@oh_rsync (work@oh_rsync), file:${SURELOG_DIR}/tests/GenerateRegion/dut.sv, line:93:1, endln:123:10 + \_module_inst: work@oh_rsync (work@oh_rsync), file:${SURELOG_DIR}/tests/GenerateRegion/dut.sv, line:93:1, endln:123:10 |vpiRhs: \_constant: , line:94:26, endln:94:27 |vpiDecompile:2 @@ -1438,7 +1438,7 @@ design: (work@oh_delay) |vpiParamAssign: \_param_assign: , line:95:15, endln:95:32 |vpiParent: - \_module: work@oh_rsync (work@oh_rsync), file:${SURELOG_DIR}/tests/GenerateRegion/dut.sv, line:93:1, endln:123:10 + \_module_inst: work@oh_rsync (work@oh_rsync), file:${SURELOG_DIR}/tests/GenerateRegion/dut.sv, line:93:1, endln:123:10 |vpiRhs: \_constant: , line:95:26, endln:95:32 |vpiDecompile:TRUE @@ -1452,7 +1452,7 @@ design: (work@oh_delay) |vpiParamAssign: \_param_assign: , line:96:15, endln:96:35 |vpiParent: - \_module: work@oh_rsync (work@oh_rsync), file:${SURELOG_DIR}/tests/GenerateRegion/dut.sv, line:93:1, endln:123:10 + \_module_inst: work@oh_rsync (work@oh_rsync), file:${SURELOG_DIR}/tests/GenerateRegion/dut.sv, line:93:1, endln:123:10 |vpiRhs: \_constant: , line:96:26, endln:96:35 |vpiDecompile:DEFAULT @@ -1465,14 +1465,14 @@ design: (work@oh_delay) \_parameter: (work@oh_rsync.TYPE), line:96:15, endln:96:19 |vpiDefName:work@oh_rsync |uhdmallModules: -\_module: work@shift (work@shift), file:${SURELOG_DIR}/tests/GenerateRegion/dut.sv, line:24:1, endln:43:10 +\_module_inst: work@shift (work@shift), file:${SURELOG_DIR}/tests/GenerateRegion/dut.sv, line:24:1, endln:43:10 |vpiParent: \_design: (work@oh_delay) |vpiFullName:work@shift |vpiParameter: \_parameter: (work@shift.width_a), line:25:14, endln:25:21 |vpiParent: - \_module: work@shift (work@shift), file:${SURELOG_DIR}/tests/GenerateRegion/dut.sv, line:24:1, endln:43:10 + \_module_inst: work@shift (work@shift), file:${SURELOG_DIR}/tests/GenerateRegion/dut.sv, line:24:1, endln:43:10 |UINT:4 |vpiTypespec: \_int_typespec: @@ -1481,7 +1481,7 @@ design: (work@oh_delay) |vpiParameter: \_parameter: (work@shift.signd_a), line:26:14, endln:26:21 |vpiParent: - \_module: work@shift (work@shift), file:${SURELOG_DIR}/tests/GenerateRegion/dut.sv, line:24:1, endln:43:10 + \_module_inst: work@shift (work@shift), file:${SURELOG_DIR}/tests/GenerateRegion/dut.sv, line:24:1, endln:43:10 |UINT:1 |vpiTypespec: \_int_typespec: @@ -1490,7 +1490,7 @@ design: (work@oh_delay) |vpiParameter: \_parameter: (work@shift.width_s), line:27:14, endln:27:21 |vpiParent: - \_module: work@shift (work@shift), file:${SURELOG_DIR}/tests/GenerateRegion/dut.sv, line:24:1, endln:43:10 + \_module_inst: work@shift (work@shift), file:${SURELOG_DIR}/tests/GenerateRegion/dut.sv, line:24:1, endln:43:10 |UINT:2 |vpiTypespec: \_int_typespec: @@ -1499,7 +1499,7 @@ design: (work@oh_delay) |vpiParameter: \_parameter: (work@shift.width_z), line:28:14, endln:28:21 |vpiParent: - \_module: work@shift (work@shift), file:${SURELOG_DIR}/tests/GenerateRegion/dut.sv, line:24:1, endln:43:10 + \_module_inst: work@shift (work@shift), file:${SURELOG_DIR}/tests/GenerateRegion/dut.sv, line:24:1, endln:43:10 |UINT:8 |vpiTypespec: \_int_typespec: @@ -1508,7 +1508,7 @@ design: (work@oh_delay) |vpiParamAssign: \_param_assign: , line:25:14, endln:25:25 |vpiParent: - \_module: work@shift (work@shift), file:${SURELOG_DIR}/tests/GenerateRegion/dut.sv, line:24:1, endln:43:10 + \_module_inst: work@shift (work@shift), file:${SURELOG_DIR}/tests/GenerateRegion/dut.sv, line:24:1, endln:43:10 |vpiRhs: \_constant: , line:25:24, endln:25:25 |vpiDecompile:4 @@ -1522,7 +1522,7 @@ design: (work@oh_delay) |vpiParamAssign: \_param_assign: , line:26:14, endln:26:25 |vpiParent: - \_module: work@shift (work@shift), file:${SURELOG_DIR}/tests/GenerateRegion/dut.sv, line:24:1, endln:43:10 + \_module_inst: work@shift (work@shift), file:${SURELOG_DIR}/tests/GenerateRegion/dut.sv, line:24:1, endln:43:10 |vpiRhs: \_constant: , line:26:24, endln:26:25 |vpiDecompile:1 @@ -1536,7 +1536,7 @@ design: (work@oh_delay) |vpiParamAssign: \_param_assign: , line:27:14, endln:27:25 |vpiParent: - \_module: work@shift (work@shift), file:${SURELOG_DIR}/tests/GenerateRegion/dut.sv, line:24:1, endln:43:10 + \_module_inst: work@shift (work@shift), file:${SURELOG_DIR}/tests/GenerateRegion/dut.sv, line:24:1, endln:43:10 |vpiRhs: \_constant: , line:27:24, endln:27:25 |vpiDecompile:2 @@ -1550,7 +1550,7 @@ design: (work@oh_delay) |vpiParamAssign: \_param_assign: , line:28:14, endln:28:25 |vpiParent: - \_module: work@shift (work@shift), file:${SURELOG_DIR}/tests/GenerateRegion/dut.sv, line:24:1, endln:43:10 + \_module_inst: work@shift (work@shift), file:${SURELOG_DIR}/tests/GenerateRegion/dut.sv, line:24:1, endln:43:10 |vpiRhs: \_constant: , line:28:24, endln:28:25 |vpiDecompile:8 @@ -1565,25 +1565,25 @@ design: (work@oh_delay) |vpiNet: \_logic_net: (work@shift.a), line:24:14, endln:24:15 |vpiParent: - \_module: work@shift (work@shift), file:${SURELOG_DIR}/tests/GenerateRegion/dut.sv, line:24:1, endln:43:10 + \_module_inst: work@shift (work@shift), file:${SURELOG_DIR}/tests/GenerateRegion/dut.sv, line:24:1, endln:43:10 |vpiName:a |vpiFullName:work@shift.a |vpiNet: \_logic_net: (work@shift.s), line:24:16, endln:24:17 |vpiParent: - \_module: work@shift (work@shift), file:${SURELOG_DIR}/tests/GenerateRegion/dut.sv, line:24:1, endln:43:10 + \_module_inst: work@shift (work@shift), file:${SURELOG_DIR}/tests/GenerateRegion/dut.sv, line:24:1, endln:43:10 |vpiName:s |vpiFullName:work@shift.s |vpiNet: \_logic_net: (work@shift.z), line:24:18, endln:24:19 |vpiParent: - \_module: work@shift (work@shift), file:${SURELOG_DIR}/tests/GenerateRegion/dut.sv, line:24:1, endln:43:10 + \_module_inst: work@shift (work@shift), file:${SURELOG_DIR}/tests/GenerateRegion/dut.sv, line:24:1, endln:43:10 |vpiName:z |vpiFullName:work@shift.z |vpiPort: \_port: (a), line:24:14, endln:24:15 |vpiParent: - \_module: work@shift (work@shift), file:${SURELOG_DIR}/tests/GenerateRegion/dut.sv, line:24:1, endln:43:10 + \_module_inst: work@shift (work@shift), file:${SURELOG_DIR}/tests/GenerateRegion/dut.sv, line:24:1, endln:43:10 |vpiName:a |vpiDirection:1 |vpiLowConn: @@ -1623,7 +1623,7 @@ design: (work@oh_delay) |vpiPort: \_port: (s), line:24:16, endln:24:17 |vpiParent: - \_module: work@shift (work@shift), file:${SURELOG_DIR}/tests/GenerateRegion/dut.sv, line:24:1, endln:43:10 + \_module_inst: work@shift (work@shift), file:${SURELOG_DIR}/tests/GenerateRegion/dut.sv, line:24:1, endln:43:10 |vpiName:s |vpiDirection:1 |vpiLowConn: @@ -1663,7 +1663,7 @@ design: (work@oh_delay) |vpiPort: \_port: (z), line:24:18, endln:24:19 |vpiParent: - \_module: work@shift (work@shift), file:${SURELOG_DIR}/tests/GenerateRegion/dut.sv, line:24:1, endln:43:10 + \_module_inst: work@shift (work@shift), file:${SURELOG_DIR}/tests/GenerateRegion/dut.sv, line:24:1, endln:43:10 |vpiName:z |vpiDirection:2 |vpiLowConn: @@ -1701,14 +1701,14 @@ design: (work@oh_delay) |UINT:0 |vpiConstType:9 |uhdmallModules: -\_module: work@test (work@test), file:${SURELOG_DIR}/tests/GenerateRegion/dut.sv, line:76:1, endln:88:10 +\_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/GenerateRegion/dut.sv, line:76:1, endln:88:10 |vpiParent: \_design: (work@oh_delay) |vpiFullName:work@test |vpiParameter: \_parameter: (work@test.Width), line:77:16, endln:77:21 |vpiParent: - \_module: work@test (work@test), file:${SURELOG_DIR}/tests/GenerateRegion/dut.sv, line:76:1, endln:88:10 + \_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/GenerateRegion/dut.sv, line:76:1, endln:88:10 |UINT:32 |vpiTypespec: \_int_typespec: , line:77:12, endln:77:15 @@ -1721,7 +1721,7 @@ design: (work@oh_delay) |vpiParameter: \_parameter: (work@test.DataBitsPerMask), line:78:16, endln:78:31 |vpiParent: - \_module: work@test (work@test), file:${SURELOG_DIR}/tests/GenerateRegion/dut.sv, line:76:1, endln:88:10 + \_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/GenerateRegion/dut.sv, line:76:1, endln:88:10 |UINT:2 |vpiTypespec: \_int_typespec: , line:78:12, endln:78:15 @@ -1734,7 +1734,7 @@ design: (work@oh_delay) |vpiParameter: \_parameter: (work@test.MaskWidth), line:80:24, endln:80:33 |vpiParent: - \_module: work@test (work@test), file:${SURELOG_DIR}/tests/GenerateRegion/dut.sv, line:76:1, endln:88:10 + \_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/GenerateRegion/dut.sv, line:76:1, endln:88:10 |vpiTypespec: \_int_typespec: , line:80:20, endln:80:23 |vpiParent: @@ -1747,7 +1747,7 @@ design: (work@oh_delay) |vpiParamAssign: \_param_assign: , line:77:16, endln:77:36 |vpiParent: - \_module: work@test (work@test), file:${SURELOG_DIR}/tests/GenerateRegion/dut.sv, line:76:1, endln:88:10 + \_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/GenerateRegion/dut.sv, line:76:1, endln:88:10 |vpiRhs: \_constant: , line:77:34, endln:77:36 |vpiDecompile:32 @@ -1761,7 +1761,7 @@ design: (work@oh_delay) |vpiParamAssign: \_param_assign: , line:78:16, endln:78:35 |vpiParent: - \_module: work@test (work@test), file:${SURELOG_DIR}/tests/GenerateRegion/dut.sv, line:76:1, endln:88:10 + \_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/GenerateRegion/dut.sv, line:76:1, endln:88:10 |vpiRhs: \_constant: , line:78:34, endln:78:35 |vpiDecompile:2 @@ -1775,7 +1775,7 @@ design: (work@oh_delay) |vpiParamAssign: \_param_assign: , line:80:24, endln:80:59 |vpiParent: - \_module: work@test (work@test), file:${SURELOG_DIR}/tests/GenerateRegion/dut.sv, line:76:1, endln:88:10 + \_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/GenerateRegion/dut.sv, line:76:1, endln:88:10 |vpiRhs: \_operation: , line:80:36, endln:80:59 |vpiOpType:12 @@ -1793,12 +1793,12 @@ design: (work@oh_delay) \_parameter: (work@test.MaskWidth), line:80:24, endln:80:33 |vpiDefName:work@test |uhdmtopModules: -\_module: work@oh_delay (work@oh_delay), file:${SURELOG_DIR}/tests/GenerateRegion/dut.sv, line:1:1, endln:20:10 +\_module_inst: work@oh_delay (work@oh_delay), file:${SURELOG_DIR}/tests/GenerateRegion/dut.sv, line:1:1, endln:20:10 |vpiName:work@oh_delay |vpiParameter: \_parameter: (work@oh_delay.N), line:2:13, endln:2:14 |vpiParent: - \_module: work@oh_delay (work@oh_delay), file:${SURELOG_DIR}/tests/GenerateRegion/dut.sv, line:1:1, endln:20:10 + \_module_inst: work@oh_delay (work@oh_delay), file:${SURELOG_DIR}/tests/GenerateRegion/dut.sv, line:1:1, endln:20:10 |UINT:1 |vpiTypespec: \_int_typespec: @@ -1809,7 +1809,7 @@ design: (work@oh_delay) |vpiParameter: \_parameter: (work@oh_delay.MAXDELAY), line:3:13, endln:3:21 |vpiParent: - \_module: work@oh_delay (work@oh_delay), file:${SURELOG_DIR}/tests/GenerateRegion/dut.sv, line:1:1, endln:20:10 + \_module_inst: work@oh_delay (work@oh_delay), file:${SURELOG_DIR}/tests/GenerateRegion/dut.sv, line:1:1, endln:20:10 |UINT:4 |vpiTypespec: \_int_typespec: @@ -1820,13 +1820,13 @@ design: (work@oh_delay) |vpiParameter: \_parameter: (work@oh_delay.M), line:4:13, endln:4:14 |vpiParent: - \_module: work@oh_delay (work@oh_delay), file:${SURELOG_DIR}/tests/GenerateRegion/dut.sv, line:1:1, endln:20:10 + \_module_inst: work@oh_delay (work@oh_delay), file:${SURELOG_DIR}/tests/GenerateRegion/dut.sv, line:1:1, endln:20:10 |vpiName:M |vpiFullName:work@oh_delay.M |vpiParamAssign: \_param_assign: , line:2:13, endln:2:25 |vpiParent: - \_module: work@oh_delay (work@oh_delay), file:${SURELOG_DIR}/tests/GenerateRegion/dut.sv, line:1:1, endln:20:10 + \_module_inst: work@oh_delay (work@oh_delay), file:${SURELOG_DIR}/tests/GenerateRegion/dut.sv, line:1:1, endln:20:10 |vpiRhs: \_constant: , line:2:24, endln:2:25 |vpiDecompile:1 @@ -1840,7 +1840,7 @@ design: (work@oh_delay) |vpiParamAssign: \_param_assign: , line:3:13, endln:3:25 |vpiParent: - \_module: work@oh_delay (work@oh_delay), file:${SURELOG_DIR}/tests/GenerateRegion/dut.sv, line:1:1, endln:20:10 + \_module_inst: work@oh_delay (work@oh_delay), file:${SURELOG_DIR}/tests/GenerateRegion/dut.sv, line:1:1, endln:20:10 |vpiRhs: \_constant: , line:3:24, endln:3:25 |vpiDecompile:4 @@ -1854,7 +1854,7 @@ design: (work@oh_delay) |vpiParamAssign: \_param_assign: , line:4:13, endln:4:40 |vpiParent: - \_module: work@oh_delay (work@oh_delay), file:${SURELOG_DIR}/tests/GenerateRegion/dut.sv, line:1:1, endln:20:10 + \_module_inst: work@oh_delay (work@oh_delay), file:${SURELOG_DIR}/tests/GenerateRegion/dut.sv, line:1:1, endln:20:10 |vpiRhs: \_constant: , line:4:24, endln:4:40 |vpiDecompile:2 @@ -1873,7 +1873,7 @@ design: (work@oh_delay) |vpiProcess: \_always: , line:12:5, endln:13:31 |vpiParent: - \_module: work@oh_delay (work@oh_delay), file:${SURELOG_DIR}/tests/GenerateRegion/dut.sv, line:1:1, endln:20:10 + \_module_inst: work@oh_delay (work@oh_delay), file:${SURELOG_DIR}/tests/GenerateRegion/dut.sv, line:1:1, endln:20:10 |vpiStmt: \_event_control: , line:12:12, endln:12:27 |vpiParent: @@ -1939,7 +1939,7 @@ design: (work@oh_delay) |vpiGenScopeArray: \_gen_scope_array: (work@oh_delay.gen_pipe[1]), line:14:31, endln:17:8 |vpiParent: - \_module: work@oh_delay (work@oh_delay), file:${SURELOG_DIR}/tests/GenerateRegion/dut.sv, line:1:1, endln:20:10 + \_module_inst: work@oh_delay (work@oh_delay), file:${SURELOG_DIR}/tests/GenerateRegion/dut.sv, line:1:1, endln:20:10 |vpiName:gen_pipe[1] |vpiFullName:work@oh_delay.gen_pipe[1] |vpiGenScope: @@ -2036,7 +2036,7 @@ design: (work@oh_delay) |vpiGenScopeArray: \_gen_scope_array: (work@oh_delay.gen_pipe[2]), line:14:31, endln:17:8 |vpiParent: - \_module: work@oh_delay (work@oh_delay), file:${SURELOG_DIR}/tests/GenerateRegion/dut.sv, line:1:1, endln:20:10 + \_module_inst: work@oh_delay (work@oh_delay), file:${SURELOG_DIR}/tests/GenerateRegion/dut.sv, line:1:1, endln:20:10 |vpiName:gen_pipe[2] |vpiFullName:work@oh_delay.gen_pipe[2] |vpiGenScope: @@ -2133,7 +2133,7 @@ design: (work@oh_delay) |vpiGenScopeArray: \_gen_scope_array: (work@oh_delay.gen_pipe[3]), line:14:31, endln:17:8 |vpiParent: - \_module: work@oh_delay (work@oh_delay), file:${SURELOG_DIR}/tests/GenerateRegion/dut.sv, line:1:1, endln:20:10 + \_module_inst: work@oh_delay (work@oh_delay), file:${SURELOG_DIR}/tests/GenerateRegion/dut.sv, line:1:1, endln:20:10 |vpiName:gen_pipe[3] |vpiFullName:work@oh_delay.gen_pipe[3] |vpiGenScope: @@ -2228,12 +2228,12 @@ design: (work@oh_delay) \_parameter: (work@oh_delay.gen_pipe[3].i), line:14:0 |vpiAlwaysType:1 |uhdmtopModules: -\_module: work@shift (work@shift), file:${SURELOG_DIR}/tests/GenerateRegion/dut.sv, line:24:1, endln:43:10 +\_module_inst: work@shift (work@shift), file:${SURELOG_DIR}/tests/GenerateRegion/dut.sv, line:24:1, endln:43:10 |vpiName:work@shift |vpiParameter: \_parameter: (work@shift.width_a), line:25:14, endln:25:21 |vpiParent: - \_module: work@shift (work@shift), file:${SURELOG_DIR}/tests/GenerateRegion/dut.sv, line:24:1, endln:43:10 + \_module_inst: work@shift (work@shift), file:${SURELOG_DIR}/tests/GenerateRegion/dut.sv, line:24:1, endln:43:10 |UINT:4 |vpiTypespec: \_int_typespec: @@ -2244,7 +2244,7 @@ design: (work@oh_delay) |vpiParameter: \_parameter: (work@shift.signd_a), line:26:14, endln:26:21 |vpiParent: - \_module: work@shift (work@shift), file:${SURELOG_DIR}/tests/GenerateRegion/dut.sv, line:24:1, endln:43:10 + \_module_inst: work@shift (work@shift), file:${SURELOG_DIR}/tests/GenerateRegion/dut.sv, line:24:1, endln:43:10 |UINT:1 |vpiTypespec: \_int_typespec: @@ -2255,7 +2255,7 @@ design: (work@oh_delay) |vpiParameter: \_parameter: (work@shift.width_s), line:27:14, endln:27:21 |vpiParent: - \_module: work@shift (work@shift), file:${SURELOG_DIR}/tests/GenerateRegion/dut.sv, line:24:1, endln:43:10 + \_module_inst: work@shift (work@shift), file:${SURELOG_DIR}/tests/GenerateRegion/dut.sv, line:24:1, endln:43:10 |UINT:2 |vpiTypespec: \_int_typespec: @@ -2266,7 +2266,7 @@ design: (work@oh_delay) |vpiParameter: \_parameter: (work@shift.width_z), line:28:14, endln:28:21 |vpiParent: - \_module: work@shift (work@shift), file:${SURELOG_DIR}/tests/GenerateRegion/dut.sv, line:24:1, endln:43:10 + \_module_inst: work@shift (work@shift), file:${SURELOG_DIR}/tests/GenerateRegion/dut.sv, line:24:1, endln:43:10 |UINT:8 |vpiTypespec: \_int_typespec: @@ -2277,7 +2277,7 @@ design: (work@oh_delay) |vpiParamAssign: \_param_assign: , line:25:14, endln:25:25 |vpiParent: - \_module: work@shift (work@shift), file:${SURELOG_DIR}/tests/GenerateRegion/dut.sv, line:24:1, endln:43:10 + \_module_inst: work@shift (work@shift), file:${SURELOG_DIR}/tests/GenerateRegion/dut.sv, line:24:1, endln:43:10 |vpiRhs: \_constant: , line:25:24, endln:25:25 |vpiDecompile:4 @@ -2291,7 +2291,7 @@ design: (work@oh_delay) |vpiParamAssign: \_param_assign: , line:26:14, endln:26:25 |vpiParent: - \_module: work@shift (work@shift), file:${SURELOG_DIR}/tests/GenerateRegion/dut.sv, line:24:1, endln:43:10 + \_module_inst: work@shift (work@shift), file:${SURELOG_DIR}/tests/GenerateRegion/dut.sv, line:24:1, endln:43:10 |vpiRhs: \_constant: , line:26:24, endln:26:25 |vpiDecompile:1 @@ -2305,7 +2305,7 @@ design: (work@oh_delay) |vpiParamAssign: \_param_assign: , line:27:14, endln:27:25 |vpiParent: - \_module: work@shift (work@shift), file:${SURELOG_DIR}/tests/GenerateRegion/dut.sv, line:24:1, endln:43:10 + \_module_inst: work@shift (work@shift), file:${SURELOG_DIR}/tests/GenerateRegion/dut.sv, line:24:1, endln:43:10 |vpiRhs: \_constant: , line:27:24, endln:27:25 |vpiDecompile:2 @@ -2319,7 +2319,7 @@ design: (work@oh_delay) |vpiParamAssign: \_param_assign: , line:28:14, endln:28:25 |vpiParent: - \_module: work@shift (work@shift), file:${SURELOG_DIR}/tests/GenerateRegion/dut.sv, line:24:1, endln:43:10 + \_module_inst: work@shift (work@shift), file:${SURELOG_DIR}/tests/GenerateRegion/dut.sv, line:24:1, endln:43:10 |vpiRhs: \_constant: , line:28:24, endln:28:25 |vpiDecompile:8 @@ -2335,7 +2335,7 @@ design: (work@oh_delay) |vpiNet: \_logic_net: (work@shift.a), line:24:14, endln:24:15 |vpiParent: - \_module: work@shift (work@shift), file:${SURELOG_DIR}/tests/GenerateRegion/dut.sv, line:24:1, endln:43:10 + \_module_inst: work@shift (work@shift), file:${SURELOG_DIR}/tests/GenerateRegion/dut.sv, line:24:1, endln:43:10 |vpiTypespec: \_logic_typespec: , line:30:7, endln:30:20 |vpiRange: @@ -2361,7 +2361,7 @@ design: (work@oh_delay) |vpiNet: \_logic_net: (work@shift.s), line:24:16, endln:24:17 |vpiParent: - \_module: work@shift (work@shift), file:${SURELOG_DIR}/tests/GenerateRegion/dut.sv, line:24:1, endln:43:10 + \_module_inst: work@shift (work@shift), file:${SURELOG_DIR}/tests/GenerateRegion/dut.sv, line:24:1, endln:43:10 |vpiTypespec: \_logic_typespec: , line:31:7, endln:31:20 |vpiRange: @@ -2387,7 +2387,7 @@ design: (work@oh_delay) |vpiNet: \_logic_net: (work@shift.z), line:24:18, endln:24:19 |vpiParent: - \_module: work@shift (work@shift), file:${SURELOG_DIR}/tests/GenerateRegion/dut.sv, line:24:1, endln:43:10 + \_module_inst: work@shift (work@shift), file:${SURELOG_DIR}/tests/GenerateRegion/dut.sv, line:24:1, endln:43:10 |vpiTypespec: \_logic_typespec: , line:32:8, endln:32:22 |vpiRange: @@ -2414,7 +2414,7 @@ design: (work@oh_delay) |vpiPort: \_port: (a), line:24:14, endln:24:15 |vpiParent: - \_module: work@shift (work@shift), file:${SURELOG_DIR}/tests/GenerateRegion/dut.sv, line:24:1, endln:43:10 + \_module_inst: work@shift (work@shift), file:${SURELOG_DIR}/tests/GenerateRegion/dut.sv, line:24:1, endln:43:10 |vpiName:a |vpiDirection:1 |vpiLowConn: @@ -2448,11 +2448,11 @@ design: (work@oh_delay) |UINT:0 |vpiConstType:9 |vpiInstance: - \_module: work@shift (work@shift), file:${SURELOG_DIR}/tests/GenerateRegion/dut.sv, line:24:1, endln:43:10 + \_module_inst: work@shift (work@shift), file:${SURELOG_DIR}/tests/GenerateRegion/dut.sv, line:24:1, endln:43:10 |vpiPort: \_port: (s), line:24:16, endln:24:17 |vpiParent: - \_module: work@shift (work@shift), file:${SURELOG_DIR}/tests/GenerateRegion/dut.sv, line:24:1, endln:43:10 + \_module_inst: work@shift (work@shift), file:${SURELOG_DIR}/tests/GenerateRegion/dut.sv, line:24:1, endln:43:10 |vpiName:s |vpiDirection:1 |vpiLowConn: @@ -2486,11 +2486,11 @@ design: (work@oh_delay) |UINT:0 |vpiConstType:9 |vpiInstance: - \_module: work@shift (work@shift), file:${SURELOG_DIR}/tests/GenerateRegion/dut.sv, line:24:1, endln:43:10 + \_module_inst: work@shift (work@shift), file:${SURELOG_DIR}/tests/GenerateRegion/dut.sv, line:24:1, endln:43:10 |vpiPort: \_port: (z), line:24:18, endln:24:19 |vpiParent: - \_module: work@shift (work@shift), file:${SURELOG_DIR}/tests/GenerateRegion/dut.sv, line:24:1, endln:43:10 + \_module_inst: work@shift (work@shift), file:${SURELOG_DIR}/tests/GenerateRegion/dut.sv, line:24:1, endln:43:10 |vpiName:z |vpiDirection:2 |vpiLowConn: @@ -2524,11 +2524,11 @@ design: (work@oh_delay) |UINT:0 |vpiConstType:9 |vpiInstance: - \_module: work@shift (work@shift), file:${SURELOG_DIR}/tests/GenerateRegion/dut.sv, line:24:1, endln:43:10 + \_module_inst: work@shift (work@shift), file:${SURELOG_DIR}/tests/GenerateRegion/dut.sv, line:24:1, endln:43:10 |vpiGenScopeArray: \_gen_scope_array: (work@shift.SGNED), line:34:10, endln:41:4 |vpiParent: - \_module: work@shift (work@shift), file:${SURELOG_DIR}/tests/GenerateRegion/dut.sv, line:24:1, endln:43:10 + \_module_inst: work@shift (work@shift), file:${SURELOG_DIR}/tests/GenerateRegion/dut.sv, line:24:1, endln:43:10 |vpiName:SGNED |vpiFullName:work@shift.SGNED |vpiGenScope: @@ -2605,14 +2605,14 @@ design: (work@oh_delay) |vpiActual: \_logic_net: (work@shift.z), line:24:18, endln:24:19 |uhdmtopModules: -\_module: work@gen_test9 (work@gen_test9), file:${SURELOG_DIR}/tests/GenerateRegion/dut.sv, line:46:1, endln:64:10 +\_module_inst: work@gen_test9 (work@gen_test9), file:${SURELOG_DIR}/tests/GenerateRegion/dut.sv, line:46:1, endln:64:10 |vpiName:work@gen_test9 |vpiDefName:work@gen_test9 |vpiTop:1 |vpiNet: \_logic_net: (work@gen_test9.w), line:47:20, endln:47:21 |vpiParent: - \_module: work@gen_test9 (work@gen_test9), file:${SURELOG_DIR}/tests/GenerateRegion/dut.sv, line:46:1, endln:64:10 + \_module_inst: work@gen_test9 (work@gen_test9), file:${SURELOG_DIR}/tests/GenerateRegion/dut.sv, line:46:1, endln:64:10 |vpiTypespec: \_logic_typespec: , line:47:9, endln:47:19 |vpiRange: @@ -2640,7 +2640,7 @@ design: (work@oh_delay) |vpiGenScopeArray: \_gen_scope_array: (work@gen_test9.A), line:48:9, endln:63:20 |vpiParent: - \_module: work@gen_test9 (work@gen_test9), file:${SURELOG_DIR}/tests/GenerateRegion/dut.sv, line:46:1, endln:64:10 + \_module_inst: work@gen_test9 (work@gen_test9), file:${SURELOG_DIR}/tests/GenerateRegion/dut.sv, line:46:1, endln:64:10 |vpiName:A |vpiFullName:work@gen_test9.A |vpiGenScope: @@ -2852,7 +2852,7 @@ design: (work@oh_delay) |vpiContAssign: \_cont_assign: , line:47:20, endln:47:21 |vpiParent: - \_module: work@gen_test9 (work@gen_test9), file:${SURELOG_DIR}/tests/GenerateRegion/dut.sv, line:46:1, endln:64:10 + \_module_inst: work@gen_test9 (work@gen_test9), file:${SURELOG_DIR}/tests/GenerateRegion/dut.sv, line:46:1, endln:64:10 |vpiNetDeclAssign:1 |vpiRhs: \_constant: , line:47:24, endln:47:29 @@ -2865,21 +2865,21 @@ design: (work@oh_delay) |vpiLhs: \_logic_net: (work@gen_test9.w), line:47:20, endln:47:21 |uhdmtopModules: -\_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/GenerateRegion/dut.sv, line:69:1, endln:74:10 +\_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/GenerateRegion/dut.sv, line:69:1, endln:74:10 |vpiName:work@dut |vpiDefName:work@dut |vpiTop:1 |vpiTopModule:1 - |vpiModule: - \_module: work@test (work@dut.t), file:${SURELOG_DIR}/tests/GenerateRegion/dut.sv, line:70:9, endln:73:16 + |vpiModuleInst: + \_module_inst: work@test (work@dut.t), file:${SURELOG_DIR}/tests/GenerateRegion/dut.sv, line:70:9, endln:73:16 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/GenerateRegion/dut.sv, line:69:1, endln:74:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/GenerateRegion/dut.sv, line:69:1, endln:74:10 |vpiName:t |vpiFullName:work@dut.t |vpiParameter: \_parameter: (work@dut.t.Width), line:77:16, endln:77:21 |vpiParent: - \_module: work@test (work@dut.t), file:${SURELOG_DIR}/tests/GenerateRegion/dut.sv, line:70:9, endln:73:16 + \_module_inst: work@test (work@dut.t), file:${SURELOG_DIR}/tests/GenerateRegion/dut.sv, line:70:9, endln:73:16 |UINT:32 |vpiTypespec: \_int_typespec: , line:77:12, endln:77:15 @@ -2892,7 +2892,7 @@ design: (work@oh_delay) |vpiParameter: \_parameter: (work@dut.t.DataBitsPerMask), line:78:16, endln:78:31 |vpiParent: - \_module: work@test (work@dut.t), file:${SURELOG_DIR}/tests/GenerateRegion/dut.sv, line:70:9, endln:73:16 + \_module_inst: work@test (work@dut.t), file:${SURELOG_DIR}/tests/GenerateRegion/dut.sv, line:70:9, endln:73:16 |UINT:2 |vpiTypespec: \_int_typespec: , line:78:12, endln:78:15 @@ -2905,7 +2905,7 @@ design: (work@oh_delay) |vpiParameter: \_parameter: (work@dut.t.MaskWidth), line:80:24, endln:80:33 |vpiParent: - \_module: work@test (work@dut.t), file:${SURELOG_DIR}/tests/GenerateRegion/dut.sv, line:70:9, endln:73:16 + \_module_inst: work@test (work@dut.t), file:${SURELOG_DIR}/tests/GenerateRegion/dut.sv, line:70:9, endln:73:16 |vpiTypespec: \_int_typespec: , line:80:20, endln:80:23 |vpiParent: @@ -2918,7 +2918,7 @@ design: (work@oh_delay) |vpiParamAssign: \_param_assign: , line:77:16, endln:77:36 |vpiParent: - \_module: work@test (work@dut.t), file:${SURELOG_DIR}/tests/GenerateRegion/dut.sv, line:70:9, endln:73:16 + \_module_inst: work@test (work@dut.t), file:${SURELOG_DIR}/tests/GenerateRegion/dut.sv, line:70:9, endln:73:16 |vpiOverriden:1 |vpiRhs: \_constant: , line:77:34, endln:77:36 @@ -2933,7 +2933,7 @@ design: (work@oh_delay) |vpiParamAssign: \_param_assign: , line:78:16, endln:78:35 |vpiParent: - \_module: work@test (work@dut.t), file:${SURELOG_DIR}/tests/GenerateRegion/dut.sv, line:70:9, endln:73:16 + \_module_inst: work@test (work@dut.t), file:${SURELOG_DIR}/tests/GenerateRegion/dut.sv, line:70:9, endln:73:16 |vpiOverriden:1 |vpiRhs: \_constant: , line:78:34, endln:78:35 @@ -2948,7 +2948,7 @@ design: (work@oh_delay) |vpiParamAssign: \_param_assign: , line:80:24, endln:80:59 |vpiParent: - \_module: work@test (work@dut.t), file:${SURELOG_DIR}/tests/GenerateRegion/dut.sv, line:70:9, endln:73:16 + \_module_inst: work@test (work@dut.t), file:${SURELOG_DIR}/tests/GenerateRegion/dut.sv, line:70:9, endln:73:16 |vpiRhs: \_constant: , line:80:36, endln:80:59 |vpiDecompile:4 @@ -2963,11 +2963,11 @@ design: (work@oh_delay) |vpiDefFile:${SURELOG_DIR}/tests/GenerateRegion/dut.sv |vpiDefLineNo:76 |vpiInstance: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/GenerateRegion/dut.sv, line:69:1, endln:74:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/GenerateRegion/dut.sv, line:69:1, endln:74:10 |vpiGenScopeArray: \_gen_scope_array: (work@dut.t.genblk1[0]), line:83:36, endln:85:7 |vpiParent: - \_module: work@test (work@dut.t), file:${SURELOG_DIR}/tests/GenerateRegion/dut.sv, line:70:9, endln:73:16 + \_module_inst: work@test (work@dut.t), file:${SURELOG_DIR}/tests/GenerateRegion/dut.sv, line:70:9, endln:73:16 |vpiName:genblk1[0] |vpiFullName:work@dut.t.genblk1[0] |vpiGenScope: @@ -2985,8 +2985,8 @@ design: (work@oh_delay) |vpiLocalParam:1 |vpiName:i |vpiFullName:work@dut.t.genblk1[0].i - |vpiModule: - \_module: work@dut.t.genblk1[0]::G1 (work@dut.t.genblk1[0].u), file:${SURELOG_DIR}/tests/GenerateRegion/dut.sv, line:84:7, endln:84:14 + |vpiModuleInst: + \_module_inst: work@dut.t.genblk1[0]::G1 (work@dut.t.genblk1[0].u), file:${SURELOG_DIR}/tests/GenerateRegion/dut.sv, line:84:7, endln:84:14 |vpiParent: \_gen_scope: (work@dut.t.genblk1[0]) |vpiName:u @@ -2995,7 +2995,7 @@ design: (work@oh_delay) |vpiGenScopeArray: \_gen_scope_array: (work@dut.t.genblk1[1]), line:83:36, endln:85:7 |vpiParent: - \_module: work@test (work@dut.t), file:${SURELOG_DIR}/tests/GenerateRegion/dut.sv, line:70:9, endln:73:16 + \_module_inst: work@test (work@dut.t), file:${SURELOG_DIR}/tests/GenerateRegion/dut.sv, line:70:9, endln:73:16 |vpiName:genblk1[1] |vpiFullName:work@dut.t.genblk1[1] |vpiGenScope: @@ -3013,8 +3013,8 @@ design: (work@oh_delay) |vpiLocalParam:1 |vpiName:i |vpiFullName:work@dut.t.genblk1[1].i - |vpiModule: - \_module: work@dut.t.genblk1[1]::G1 (work@dut.t.genblk1[1].u), file:${SURELOG_DIR}/tests/GenerateRegion/dut.sv, line:84:7, endln:84:14 + |vpiModuleInst: + \_module_inst: work@dut.t.genblk1[1]::G1 (work@dut.t.genblk1[1].u), file:${SURELOG_DIR}/tests/GenerateRegion/dut.sv, line:84:7, endln:84:14 |vpiParent: \_gen_scope: (work@dut.t.genblk1[1]) |vpiName:u @@ -3023,7 +3023,7 @@ design: (work@oh_delay) |vpiGenScopeArray: \_gen_scope_array: (work@dut.t.genblk1[2]), line:83:36, endln:85:7 |vpiParent: - \_module: work@test (work@dut.t), file:${SURELOG_DIR}/tests/GenerateRegion/dut.sv, line:70:9, endln:73:16 + \_module_inst: work@test (work@dut.t), file:${SURELOG_DIR}/tests/GenerateRegion/dut.sv, line:70:9, endln:73:16 |vpiName:genblk1[2] |vpiFullName:work@dut.t.genblk1[2] |vpiGenScope: @@ -3041,8 +3041,8 @@ design: (work@oh_delay) |vpiLocalParam:1 |vpiName:i |vpiFullName:work@dut.t.genblk1[2].i - |vpiModule: - \_module: work@dut.t.genblk1[2]::G1 (work@dut.t.genblk1[2].u), file:${SURELOG_DIR}/tests/GenerateRegion/dut.sv, line:84:7, endln:84:14 + |vpiModuleInst: + \_module_inst: work@dut.t.genblk1[2]::G1 (work@dut.t.genblk1[2].u), file:${SURELOG_DIR}/tests/GenerateRegion/dut.sv, line:84:7, endln:84:14 |vpiParent: \_gen_scope: (work@dut.t.genblk1[2]) |vpiName:u @@ -3051,7 +3051,7 @@ design: (work@oh_delay) |vpiGenScopeArray: \_gen_scope_array: (work@dut.t.genblk1[3]), line:83:36, endln:85:7 |vpiParent: - \_module: work@test (work@dut.t), file:${SURELOG_DIR}/tests/GenerateRegion/dut.sv, line:70:9, endln:73:16 + \_module_inst: work@test (work@dut.t), file:${SURELOG_DIR}/tests/GenerateRegion/dut.sv, line:70:9, endln:73:16 |vpiName:genblk1[3] |vpiFullName:work@dut.t.genblk1[3] |vpiGenScope: @@ -3069,20 +3069,20 @@ design: (work@oh_delay) |vpiLocalParam:1 |vpiName:i |vpiFullName:work@dut.t.genblk1[3].i - |vpiModule: - \_module: work@dut.t.genblk1[3]::G1 (work@dut.t.genblk1[3].u), file:${SURELOG_DIR}/tests/GenerateRegion/dut.sv, line:84:7, endln:84:14 + |vpiModuleInst: + \_module_inst: work@dut.t.genblk1[3]::G1 (work@dut.t.genblk1[3].u), file:${SURELOG_DIR}/tests/GenerateRegion/dut.sv, line:84:7, endln:84:14 |vpiParent: \_gen_scope: (work@dut.t.genblk1[3]) |vpiName:u |vpiFullName:work@dut.t.genblk1[3].u |vpiDefName:work@dut.t.genblk1[3]::G1 |uhdmtopModules: -\_module: work@oh_rsync (work@oh_rsync), file:${SURELOG_DIR}/tests/GenerateRegion/dut.sv, line:93:1, endln:123:10 +\_module_inst: work@oh_rsync (work@oh_rsync), file:${SURELOG_DIR}/tests/GenerateRegion/dut.sv, line:93:1, endln:123:10 |vpiName:work@oh_rsync |vpiParameter: \_parameter: (work@oh_rsync.SYNCPIPE), line:94:15, endln:94:23 |vpiParent: - \_module: work@oh_rsync (work@oh_rsync), file:${SURELOG_DIR}/tests/GenerateRegion/dut.sv, line:93:1, endln:123:10 + \_module_inst: work@oh_rsync (work@oh_rsync), file:${SURELOG_DIR}/tests/GenerateRegion/dut.sv, line:93:1, endln:123:10 |UINT:2 |vpiTypespec: \_int_typespec: @@ -3093,7 +3093,7 @@ design: (work@oh_delay) |vpiParameter: \_parameter: (work@oh_rsync.SYN), line:95:15, endln:95:18 |vpiParent: - \_module: work@oh_rsync (work@oh_rsync), file:${SURELOG_DIR}/tests/GenerateRegion/dut.sv, line:93:1, endln:123:10 + \_module_inst: work@oh_rsync (work@oh_rsync), file:${SURELOG_DIR}/tests/GenerateRegion/dut.sv, line:93:1, endln:123:10 |STRING:TRUE |vpiTypespec: \_string_typespec: @@ -3104,7 +3104,7 @@ design: (work@oh_delay) |vpiParameter: \_parameter: (work@oh_rsync.TYPE), line:96:15, endln:96:19 |vpiParent: - \_module: work@oh_rsync (work@oh_rsync), file:${SURELOG_DIR}/tests/GenerateRegion/dut.sv, line:93:1, endln:123:10 + \_module_inst: work@oh_rsync (work@oh_rsync), file:${SURELOG_DIR}/tests/GenerateRegion/dut.sv, line:93:1, endln:123:10 |STRING:DEFAULT |vpiTypespec: \_string_typespec: @@ -3115,7 +3115,7 @@ design: (work@oh_delay) |vpiParamAssign: \_param_assign: , line:94:15, endln:94:27 |vpiParent: - \_module: work@oh_rsync (work@oh_rsync), file:${SURELOG_DIR}/tests/GenerateRegion/dut.sv, line:93:1, endln:123:10 + \_module_inst: work@oh_rsync (work@oh_rsync), file:${SURELOG_DIR}/tests/GenerateRegion/dut.sv, line:93:1, endln:123:10 |vpiRhs: \_constant: , line:94:26, endln:94:27 |vpiDecompile:2 @@ -3129,7 +3129,7 @@ design: (work@oh_delay) |vpiParamAssign: \_param_assign: , line:95:15, endln:95:32 |vpiParent: - \_module: work@oh_rsync (work@oh_rsync), file:${SURELOG_DIR}/tests/GenerateRegion/dut.sv, line:93:1, endln:123:10 + \_module_inst: work@oh_rsync (work@oh_rsync), file:${SURELOG_DIR}/tests/GenerateRegion/dut.sv, line:93:1, endln:123:10 |vpiRhs: \_constant: , line:95:26, endln:95:32 |vpiDecompile:TRUE @@ -3143,7 +3143,7 @@ design: (work@oh_delay) |vpiParamAssign: \_param_assign: , line:96:15, endln:96:35 |vpiParent: - \_module: work@oh_rsync (work@oh_rsync), file:${SURELOG_DIR}/tests/GenerateRegion/dut.sv, line:93:1, endln:123:10 + \_module_inst: work@oh_rsync (work@oh_rsync), file:${SURELOG_DIR}/tests/GenerateRegion/dut.sv, line:93:1, endln:123:10 |vpiRhs: \_constant: , line:96:26, endln:96:35 |vpiDecompile:DEFAULT @@ -3160,7 +3160,7 @@ design: (work@oh_delay) |vpiGenScopeArray: \_gen_scope_array: (work@oh_rsync.genblk1), line:103:7, endln:121:5 |vpiParent: - \_module: work@oh_rsync (work@oh_rsync), file:${SURELOG_DIR}/tests/GenerateRegion/dut.sv, line:93:1, endln:123:10 + \_module_inst: work@oh_rsync (work@oh_rsync), file:${SURELOG_DIR}/tests/GenerateRegion/dut.sv, line:93:1, endln:123:10 |vpiName:genblk1 |vpiFullName:work@oh_rsync.genblk1 |vpiGenScope: diff --git a/tests/GenerateUnnamed/GenerateUnnamed.log b/tests/GenerateUnnamed/GenerateUnnamed.log index 9f8a6794be..01d4d5aaf6 100644 --- a/tests/GenerateUnnamed/GenerateUnnamed.log +++ b/tests/GenerateUnnamed/GenerateUnnamed.log @@ -1056,7 +1056,7 @@ io_decl 11 logic_net 12 logic_typespec 2 logic_var 1 -module 9 +module_inst 9 operation 5 package 2 param_assign 8 @@ -1488,14 +1488,14 @@ design: (work@test1) \_int_typespec: |vpiSigned:1 |uhdmallModules: -\_module: work@test1 (work@test1), file:${SURELOG_DIR}/tests/GenerateUnnamed/top.v, line:1:1, endln:56:10 +\_module_inst: work@test1 (work@test1), file:${SURELOG_DIR}/tests/GenerateUnnamed/top.v, line:1:1, endln:56:10 |vpiParent: \_design: (work@test1) |vpiFullName:work@test1 |vpiParameter: \_parameter: (work@test1.p), line:2:13, endln:2:14 |vpiParent: - \_module: work@test1 (work@test1), file:${SURELOG_DIR}/tests/GenerateUnnamed/top.v, line:1:1, endln:56:10 + \_module_inst: work@test1 (work@test1), file:${SURELOG_DIR}/tests/GenerateUnnamed/top.v, line:1:1, endln:56:10 |UINT:2 |vpiTypespec: \_int_typespec: @@ -1504,7 +1504,7 @@ design: (work@test1) |vpiParameter: \_parameter: (work@test1.q), line:2:20, endln:2:21 |vpiParent: - \_module: work@test1 (work@test1), file:${SURELOG_DIR}/tests/GenerateUnnamed/top.v, line:1:1, endln:56:10 + \_module_inst: work@test1 (work@test1), file:${SURELOG_DIR}/tests/GenerateUnnamed/top.v, line:1:1, endln:56:10 |UINT:4 |vpiTypespec: \_int_typespec: @@ -1513,7 +1513,7 @@ design: (work@test1) |vpiParamAssign: \_param_assign: , line:2:13, endln:2:18 |vpiParent: - \_module: work@test1 (work@test1), file:${SURELOG_DIR}/tests/GenerateUnnamed/top.v, line:1:1, endln:56:10 + \_module_inst: work@test1 (work@test1), file:${SURELOG_DIR}/tests/GenerateUnnamed/top.v, line:1:1, endln:56:10 |vpiRhs: \_constant: , line:2:17, endln:2:18 |vpiDecompile:2 @@ -1527,7 +1527,7 @@ design: (work@test1) |vpiParamAssign: \_param_assign: , line:2:20, endln:2:25 |vpiParent: - \_module: work@test1 (work@test1), file:${SURELOG_DIR}/tests/GenerateUnnamed/top.v, line:1:1, endln:56:10 + \_module_inst: work@test1 (work@test1), file:${SURELOG_DIR}/tests/GenerateUnnamed/top.v, line:1:1, endln:56:10 |vpiRhs: \_constant: , line:2:24, endln:2:25 |vpiDecompile:4 @@ -1542,33 +1542,33 @@ design: (work@test1) |vpiNet: \_logic_net: (work@test1.a), line:3:8, endln:3:9 |vpiParent: - \_module: work@test1 (work@test1), file:${SURELOG_DIR}/tests/GenerateUnnamed/top.v, line:1:1, endln:56:10 + \_module_inst: work@test1 (work@test1), file:${SURELOG_DIR}/tests/GenerateUnnamed/top.v, line:1:1, endln:56:10 |vpiName:a |vpiFullName:work@test1.a |vpiNetType:1 |vpiNet: \_logic_net: (work@test1.b), line:3:11, endln:3:12 |vpiParent: - \_module: work@test1 (work@test1), file:${SURELOG_DIR}/tests/GenerateUnnamed/top.v, line:1:1, endln:56:10 + \_module_inst: work@test1 (work@test1), file:${SURELOG_DIR}/tests/GenerateUnnamed/top.v, line:1:1, endln:56:10 |vpiName:b |vpiFullName:work@test1.b |vpiNetType:1 |vpiNet: \_logic_net: (work@test1.c), line:3:14, endln:3:15 |vpiParent: - \_module: work@test1 (work@test1), file:${SURELOG_DIR}/tests/GenerateUnnamed/top.v, line:1:1, endln:56:10 + \_module_inst: work@test1 (work@test1), file:${SURELOG_DIR}/tests/GenerateUnnamed/top.v, line:1:1, endln:56:10 |vpiName:c |vpiFullName:work@test1.c |vpiNetType:1 |uhdmallModules: -\_module: work@test2 (work@test2), file:${SURELOG_DIR}/tests/GenerateUnnamed/top.v, line:60:1, endln:115:10 +\_module_inst: work@test2 (work@test2), file:${SURELOG_DIR}/tests/GenerateUnnamed/top.v, line:60:1, endln:115:10 |vpiParent: \_design: (work@test1) |vpiFullName:work@test2 |vpiParameter: \_parameter: (work@test2.p), line:61:13, endln:61:14 |vpiParent: - \_module: work@test2 (work@test2), file:${SURELOG_DIR}/tests/GenerateUnnamed/top.v, line:60:1, endln:115:10 + \_module_inst: work@test2 (work@test2), file:${SURELOG_DIR}/tests/GenerateUnnamed/top.v, line:60:1, endln:115:10 |UINT:2 |vpiTypespec: \_int_typespec: @@ -1577,7 +1577,7 @@ design: (work@test1) |vpiParameter: \_parameter: (work@test2.q), line:61:20, endln:61:21 |vpiParent: - \_module: work@test2 (work@test2), file:${SURELOG_DIR}/tests/GenerateUnnamed/top.v, line:60:1, endln:115:10 + \_module_inst: work@test2 (work@test2), file:${SURELOG_DIR}/tests/GenerateUnnamed/top.v, line:60:1, endln:115:10 |UINT:4 |vpiTypespec: \_int_typespec: @@ -1586,7 +1586,7 @@ design: (work@test1) |vpiParamAssign: \_param_assign: , line:61:13, endln:61:18 |vpiParent: - \_module: work@test2 (work@test2), file:${SURELOG_DIR}/tests/GenerateUnnamed/top.v, line:60:1, endln:115:10 + \_module_inst: work@test2 (work@test2), file:${SURELOG_DIR}/tests/GenerateUnnamed/top.v, line:60:1, endln:115:10 |vpiRhs: \_constant: , line:61:17, endln:61:18 |vpiDecompile:2 @@ -1600,7 +1600,7 @@ design: (work@test1) |vpiParamAssign: \_param_assign: , line:61:20, endln:61:25 |vpiParent: - \_module: work@test2 (work@test2), file:${SURELOG_DIR}/tests/GenerateUnnamed/top.v, line:60:1, endln:115:10 + \_module_inst: work@test2 (work@test2), file:${SURELOG_DIR}/tests/GenerateUnnamed/top.v, line:60:1, endln:115:10 |vpiRhs: \_constant: , line:61:24, endln:61:25 |vpiDecompile:4 @@ -1615,31 +1615,31 @@ design: (work@test1) |vpiNet: \_logic_net: (work@test2.a), line:62:8, endln:62:9 |vpiParent: - \_module: work@test2 (work@test2), file:${SURELOG_DIR}/tests/GenerateUnnamed/top.v, line:60:1, endln:115:10 + \_module_inst: work@test2 (work@test2), file:${SURELOG_DIR}/tests/GenerateUnnamed/top.v, line:60:1, endln:115:10 |vpiName:a |vpiFullName:work@test2.a |vpiNetType:1 |vpiNet: \_logic_net: (work@test2.b), line:62:11, endln:62:12 |vpiParent: - \_module: work@test2 (work@test2), file:${SURELOG_DIR}/tests/GenerateUnnamed/top.v, line:60:1, endln:115:10 + \_module_inst: work@test2 (work@test2), file:${SURELOG_DIR}/tests/GenerateUnnamed/top.v, line:60:1, endln:115:10 |vpiName:b |vpiFullName:work@test2.b |vpiNetType:1 |vpiNet: \_logic_net: (work@test2.c), line:62:14, endln:62:15 |vpiParent: - \_module: work@test2 (work@test2), file:${SURELOG_DIR}/tests/GenerateUnnamed/top.v, line:60:1, endln:115:10 + \_module_inst: work@test2 (work@test2), file:${SURELOG_DIR}/tests/GenerateUnnamed/top.v, line:60:1, endln:115:10 |vpiName:c |vpiFullName:work@test2.c |vpiNetType:1 |uhdmtopModules: -\_module: work@test1 (work@test1), file:${SURELOG_DIR}/tests/GenerateUnnamed/top.v, line:1:1, endln:56:10 +\_module_inst: work@test1 (work@test1), file:${SURELOG_DIR}/tests/GenerateUnnamed/top.v, line:1:1, endln:56:10 |vpiName:work@test1 |vpiParameter: \_parameter: (work@test1.p), line:2:13, endln:2:14 |vpiParent: - \_module: work@test1 (work@test1), file:${SURELOG_DIR}/tests/GenerateUnnamed/top.v, line:1:1, endln:56:10 + \_module_inst: work@test1 (work@test1), file:${SURELOG_DIR}/tests/GenerateUnnamed/top.v, line:1:1, endln:56:10 |UINT:2 |vpiTypespec: \_int_typespec: @@ -1650,7 +1650,7 @@ design: (work@test1) |vpiParameter: \_parameter: (work@test1.q), line:2:20, endln:2:21 |vpiParent: - \_module: work@test1 (work@test1), file:${SURELOG_DIR}/tests/GenerateUnnamed/top.v, line:1:1, endln:56:10 + \_module_inst: work@test1 (work@test1), file:${SURELOG_DIR}/tests/GenerateUnnamed/top.v, line:1:1, endln:56:10 |UINT:4 |vpiTypespec: \_int_typespec: @@ -1661,7 +1661,7 @@ design: (work@test1) |vpiParamAssign: \_param_assign: , line:2:13, endln:2:18 |vpiParent: - \_module: work@test1 (work@test1), file:${SURELOG_DIR}/tests/GenerateUnnamed/top.v, line:1:1, endln:56:10 + \_module_inst: work@test1 (work@test1), file:${SURELOG_DIR}/tests/GenerateUnnamed/top.v, line:1:1, endln:56:10 |vpiRhs: \_constant: , line:2:17, endln:2:18 |vpiDecompile:2 @@ -1675,7 +1675,7 @@ design: (work@test1) |vpiParamAssign: \_param_assign: , line:2:20, endln:2:25 |vpiParent: - \_module: work@test1 (work@test1), file:${SURELOG_DIR}/tests/GenerateUnnamed/top.v, line:1:1, endln:56:10 + \_module_inst: work@test1 (work@test1), file:${SURELOG_DIR}/tests/GenerateUnnamed/top.v, line:1:1, endln:56:10 |vpiRhs: \_constant: , line:2:24, endln:2:25 |vpiDecompile:4 @@ -1691,7 +1691,7 @@ design: (work@test1) |vpiNet: \_logic_net: (work@test1.a), line:3:8, endln:3:9 |vpiParent: - \_module: work@test1 (work@test1), file:${SURELOG_DIR}/tests/GenerateUnnamed/top.v, line:1:1, endln:56:10 + \_module_inst: work@test1 (work@test1), file:${SURELOG_DIR}/tests/GenerateUnnamed/top.v, line:1:1, endln:56:10 |vpiTypespec: \_logic_typespec: , line:3:3, endln:3:7 |vpiName:a @@ -1700,7 +1700,7 @@ design: (work@test1) |vpiNet: \_logic_net: (work@test1.b), line:3:11, endln:3:12 |vpiParent: - \_module: work@test1 (work@test1), file:${SURELOG_DIR}/tests/GenerateUnnamed/top.v, line:1:1, endln:56:10 + \_module_inst: work@test1 (work@test1), file:${SURELOG_DIR}/tests/GenerateUnnamed/top.v, line:1:1, endln:56:10 |vpiTypespec: \_logic_typespec: , line:3:3, endln:3:7 |vpiName:b @@ -1709,7 +1709,7 @@ design: (work@test1) |vpiNet: \_logic_net: (work@test1.c), line:3:14, endln:3:15 |vpiParent: - \_module: work@test1 (work@test1), file:${SURELOG_DIR}/tests/GenerateUnnamed/top.v, line:1:1, endln:56:10 + \_module_inst: work@test1 (work@test1), file:${SURELOG_DIR}/tests/GenerateUnnamed/top.v, line:1:1, endln:56:10 |vpiTypespec: \_logic_typespec: , line:3:3, endln:3:7 |vpiName:c @@ -1719,7 +1719,7 @@ design: (work@test1) |vpiGenScopeArray: \_gen_scope_array: (work@test1.genblk1), line:29:8, endln:54:6 |vpiParent: - \_module: work@test1 (work@test1), file:${SURELOG_DIR}/tests/GenerateUnnamed/top.v, line:1:1, endln:56:10 + \_module_inst: work@test1 (work@test1), file:${SURELOG_DIR}/tests/GenerateUnnamed/top.v, line:1:1, endln:56:10 |vpiName:genblk1 |vpiFullName:work@test1.genblk1 |vpiGenScope: @@ -1910,7 +1910,7 @@ design: (work@test1) |vpiPrimitive: \_gate: work@or (work@test1.sg1), line:11:6, endln:11:18 |vpiParent: - \_module: work@test1 (work@test1), file:${SURELOG_DIR}/tests/GenerateUnnamed/top.v, line:1:1, endln:56:10 + \_module_inst: work@test1 (work@test1), file:${SURELOG_DIR}/tests/GenerateUnnamed/top.v, line:1:1, endln:56:10 |vpiDefName:work@or |vpiName:sg1 |vpiFullName:work@test1.sg1 @@ -1957,12 +1957,12 @@ design: (work@test1) |vpiActual: \_logic_net: (work@test1.c), line:3:14, endln:3:15 |uhdmtopModules: -\_module: work@test2 (work@test2), file:${SURELOG_DIR}/tests/GenerateUnnamed/top.v, line:60:1, endln:115:10 +\_module_inst: work@test2 (work@test2), file:${SURELOG_DIR}/tests/GenerateUnnamed/top.v, line:60:1, endln:115:10 |vpiName:work@test2 |vpiParameter: \_parameter: (work@test2.p), line:61:13, endln:61:14 |vpiParent: - \_module: work@test2 (work@test2), file:${SURELOG_DIR}/tests/GenerateUnnamed/top.v, line:60:1, endln:115:10 + \_module_inst: work@test2 (work@test2), file:${SURELOG_DIR}/tests/GenerateUnnamed/top.v, line:60:1, endln:115:10 |UINT:2 |vpiTypespec: \_int_typespec: @@ -1973,7 +1973,7 @@ design: (work@test1) |vpiParameter: \_parameter: (work@test2.q), line:61:20, endln:61:21 |vpiParent: - \_module: work@test2 (work@test2), file:${SURELOG_DIR}/tests/GenerateUnnamed/top.v, line:60:1, endln:115:10 + \_module_inst: work@test2 (work@test2), file:${SURELOG_DIR}/tests/GenerateUnnamed/top.v, line:60:1, endln:115:10 |UINT:4 |vpiTypespec: \_int_typespec: @@ -1984,7 +1984,7 @@ design: (work@test1) |vpiParamAssign: \_param_assign: , line:61:13, endln:61:18 |vpiParent: - \_module: work@test2 (work@test2), file:${SURELOG_DIR}/tests/GenerateUnnamed/top.v, line:60:1, endln:115:10 + \_module_inst: work@test2 (work@test2), file:${SURELOG_DIR}/tests/GenerateUnnamed/top.v, line:60:1, endln:115:10 |vpiRhs: \_constant: , line:61:17, endln:61:18 |vpiDecompile:2 @@ -1998,7 +1998,7 @@ design: (work@test1) |vpiParamAssign: \_param_assign: , line:61:20, endln:61:25 |vpiParent: - \_module: work@test2 (work@test2), file:${SURELOG_DIR}/tests/GenerateUnnamed/top.v, line:60:1, endln:115:10 + \_module_inst: work@test2 (work@test2), file:${SURELOG_DIR}/tests/GenerateUnnamed/top.v, line:60:1, endln:115:10 |vpiRhs: \_constant: , line:61:24, endln:61:25 |vpiDecompile:4 @@ -2014,7 +2014,7 @@ design: (work@test1) |vpiNet: \_logic_net: (work@test2.a), line:62:8, endln:62:9 |vpiParent: - \_module: work@test2 (work@test2), file:${SURELOG_DIR}/tests/GenerateUnnamed/top.v, line:60:1, endln:115:10 + \_module_inst: work@test2 (work@test2), file:${SURELOG_DIR}/tests/GenerateUnnamed/top.v, line:60:1, endln:115:10 |vpiTypespec: \_logic_typespec: , line:62:3, endln:62:7 |vpiName:a @@ -2023,7 +2023,7 @@ design: (work@test1) |vpiNet: \_logic_net: (work@test2.b), line:62:11, endln:62:12 |vpiParent: - \_module: work@test2 (work@test2), file:${SURELOG_DIR}/tests/GenerateUnnamed/top.v, line:60:1, endln:115:10 + \_module_inst: work@test2 (work@test2), file:${SURELOG_DIR}/tests/GenerateUnnamed/top.v, line:60:1, endln:115:10 |vpiTypespec: \_logic_typespec: , line:62:3, endln:62:7 |vpiName:b @@ -2032,7 +2032,7 @@ design: (work@test1) |vpiNet: \_logic_net: (work@test2.c), line:62:14, endln:62:15 |vpiParent: - \_module: work@test2 (work@test2), file:${SURELOG_DIR}/tests/GenerateUnnamed/top.v, line:60:1, endln:115:10 + \_module_inst: work@test2 (work@test2), file:${SURELOG_DIR}/tests/GenerateUnnamed/top.v, line:60:1, endln:115:10 |vpiTypespec: \_logic_typespec: , line:62:3, endln:62:7 |vpiName:c @@ -2042,7 +2042,7 @@ design: (work@test1) |vpiGenScopeArray: \_gen_scope_array: (work@test2.pp2), line:89:5, endln:100:12 |vpiParent: - \_module: work@test2 (work@test2), file:${SURELOG_DIR}/tests/GenerateUnnamed/top.v, line:60:1, endln:115:10 + \_module_inst: work@test2 (work@test2), file:${SURELOG_DIR}/tests/GenerateUnnamed/top.v, line:60:1, endln:115:10 |vpiName:pp2 |vpiFullName:work@test2.pp2 |vpiGenScope: @@ -2233,7 +2233,7 @@ design: (work@test1) |vpiPrimitive: \_gate: work@or (work@test2.sg1), line:70:6, endln:70:18 |vpiParent: - \_module: work@test2 (work@test2), file:${SURELOG_DIR}/tests/GenerateUnnamed/top.v, line:60:1, endln:115:10 + \_module_inst: work@test2 (work@test2), file:${SURELOG_DIR}/tests/GenerateUnnamed/top.v, line:60:1, endln:115:10 |vpiDefName:work@or |vpiName:sg1 |vpiFullName:work@test2.sg1 diff --git a/tests/HierBitSelect/HierBitSelect.log b/tests/HierBitSelect/HierBitSelect.log index e1cc71d291..27fe5496fc 100644 --- a/tests/HierBitSelect/HierBitSelect.log +++ b/tests/HierBitSelect/HierBitSelect.log @@ -24,7 +24,7 @@ constant 26 cont_assign 6 design 1 -module 3 +module_inst 3 part_select 4 ref_obj 4 var_select 4 @@ -35,7 +35,7 @@ var_select 4 constant 26 cont_assign 9 design 1 -module 3 +module_inst 3 part_select 6 ref_obj 6 var_select 6 @@ -53,7 +53,7 @@ design: (work@dut) |vpiElaborated:1 |vpiName:work@dut |uhdmallModules: -\_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/HierBitSelect/dut.sv, line:1:1, endln:6:10 +\_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/HierBitSelect/dut.sv, line:1:1, endln:6:10 |vpiParent: \_design: (work@dut) |vpiFullName:work@dut @@ -61,7 +61,7 @@ design: (work@dut) |vpiContAssign: \_cont_assign: , line:3:8, endln:3:37 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/HierBitSelect/dut.sv, line:1:1, endln:6:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/HierBitSelect/dut.sv, line:1:1, endln:6:10 |vpiRhs: \_constant: , line:3:33, endln:3:37 |vpiParent: @@ -103,7 +103,7 @@ design: (work@dut) |vpiContAssign: \_cont_assign: , line:4:8, endln:4:43 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/HierBitSelect/dut.sv, line:1:1, endln:6:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/HierBitSelect/dut.sv, line:1:1, endln:6:10 |vpiRhs: \_constant: , line:4:32, endln:4:43 |vpiParent: @@ -162,7 +162,7 @@ design: (work@dut) |vpiContAssign: \_cont_assign: , line:5:8, endln:5:37 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/HierBitSelect/dut.sv, line:1:1, endln:6:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/HierBitSelect/dut.sv, line:1:1, endln:6:10 |vpiRhs: \_constant: , line:5:26, endln:5:37 |vpiParent: @@ -194,7 +194,7 @@ design: (work@dut) |UINT:11 |vpiConstType:9 |uhdmtopModules: -\_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/HierBitSelect/dut.sv, line:1:1, endln:6:10 +\_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/HierBitSelect/dut.sv, line:1:1, endln:6:10 |vpiName:work@dut |vpiDefName:work@dut |vpiTop:1 @@ -202,7 +202,7 @@ design: (work@dut) |vpiContAssign: \_cont_assign: , line:3:8, endln:3:37 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/HierBitSelect/dut.sv, line:1:1, endln:6:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/HierBitSelect/dut.sv, line:1:1, endln:6:10 |vpiRhs: \_constant: , line:3:33, endln:3:37 |vpiLhs: @@ -238,7 +238,7 @@ design: (work@dut) |vpiContAssign: \_cont_assign: , line:4:8, endln:4:43 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/HierBitSelect/dut.sv, line:1:1, endln:6:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/HierBitSelect/dut.sv, line:1:1, endln:6:10 |vpiRhs: \_constant: , line:4:32, endln:4:43 |vpiLhs: @@ -299,7 +299,7 @@ design: (work@dut) |vpiContAssign: \_cont_assign: , line:5:8, endln:5:37 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/HierBitSelect/dut.sv, line:1:1, endln:6:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/HierBitSelect/dut.sv, line:1:1, endln:6:10 |vpiRhs: \_constant: , line:5:26, endln:5:37 |vpiLhs: diff --git a/tests/HierBitSlice/HierBitSlice.log b/tests/HierBitSlice/HierBitSlice.log index d0670adb43..01c35aa5c0 100644 --- a/tests/HierBitSlice/HierBitSlice.log +++ b/tests/HierBitSlice/HierBitSlice.log @@ -4627,7 +4627,7 @@ integer_typespec 2 logic_net 55 logic_typespec 122 logic_var 43 -module 13 +module_inst 13 operation 232 packed_array_typespec 2 parameter 2 @@ -4667,7 +4667,7 @@ integer_typespec 2 logic_net 55 logic_typespec 122 logic_var 73 -module 15 +module_inst 15 operation 430 packed_array_typespec 2 parameter 2 @@ -4695,7 +4695,7 @@ design: (work@int_execute_stage) |vpiElaborated:1 |vpiName:work@int_execute_stage |uhdmallModules: -\_module: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 +\_module_inst: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 |vpiParent: \_design: (work@int_execute_stage) |vpiFullName:work@int_execute_stage @@ -4703,211 +4703,211 @@ design: (work@int_execute_stage) |vpiNet: \_logic_net: (work@int_execute_stage.clk), line:54:39, endln:54:42 |vpiParent: - \_module: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 + \_module_inst: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 |vpiName:clk |vpiFullName:work@int_execute_stage.clk |vpiNet: \_logic_net: (work@int_execute_stage.reset), line:55:39, endln:55:44 |vpiParent: - \_module: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 + \_module_inst: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 |vpiName:reset |vpiFullName:work@int_execute_stage.reset |vpiNet: \_logic_net: (work@int_execute_stage.of_operand1), line:58:39, endln:58:50 |vpiParent: - \_module: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 + \_module_inst: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 |vpiName:of_operand1 |vpiFullName:work@int_execute_stage.of_operand1 |vpiNetType:36 |vpiNet: \_logic_net: (work@int_execute_stage.of_operand2), line:59:39, endln:59:50 |vpiParent: - \_module: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 + \_module_inst: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 |vpiName:of_operand2 |vpiFullName:work@int_execute_stage.of_operand2 |vpiNetType:36 |vpiNet: \_logic_net: (work@int_execute_stage.of_mask_value), line:60:39, endln:60:52 |vpiParent: - \_module: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 + \_module_inst: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 |vpiName:of_mask_value |vpiFullName:work@int_execute_stage.of_mask_value |vpiNet: \_logic_net: (work@int_execute_stage.of_instruction_valid), line:61:39, endln:61:59 |vpiParent: - \_module: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 + \_module_inst: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 |vpiName:of_instruction_valid |vpiFullName:work@int_execute_stage.of_instruction_valid |vpiNet: \_logic_net: (work@int_execute_stage.of_instruction), line:62:39, endln:62:53 |vpiParent: - \_module: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 + \_module_inst: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 |vpiName:of_instruction |vpiFullName:work@int_execute_stage.of_instruction |vpiNet: \_logic_net: (work@int_execute_stage.of_thread_idx), line:63:39, endln:63:52 |vpiParent: - \_module: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 + \_module_inst: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 |vpiName:of_thread_idx |vpiFullName:work@int_execute_stage.of_thread_idx |vpiNet: \_logic_net: (work@int_execute_stage.of_subcycle), line:64:39, endln:64:50 |vpiParent: - \_module: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 + \_module_inst: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 |vpiName:of_subcycle |vpiFullName:work@int_execute_stage.of_subcycle |vpiNet: \_logic_net: (work@int_execute_stage.wb_rollback_en), line:67:39, endln:67:53 |vpiParent: - \_module: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 + \_module_inst: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 |vpiName:wb_rollback_en |vpiFullName:work@int_execute_stage.wb_rollback_en |vpiNetType:36 |vpiNet: \_logic_net: (work@int_execute_stage.wb_rollback_thread_idx), line:68:39, endln:68:61 |vpiParent: - \_module: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 + \_module_inst: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 |vpiName:wb_rollback_thread_idx |vpiFullName:work@int_execute_stage.wb_rollback_thread_idx |vpiNet: \_logic_net: (work@int_execute_stage.ix_instruction_valid), line:71:39, endln:71:59 |vpiParent: - \_module: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 + \_module_inst: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 |vpiName:ix_instruction_valid |vpiFullName:work@int_execute_stage.ix_instruction_valid |vpiNetType:36 |vpiNet: \_logic_net: (work@int_execute_stage.ix_instruction), line:72:39, endln:72:53 |vpiParent: - \_module: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 + \_module_inst: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 |vpiName:ix_instruction |vpiFullName:work@int_execute_stage.ix_instruction |vpiNet: \_logic_net: (work@int_execute_stage.ix_result), line:73:39, endln:73:48 |vpiParent: - \_module: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 + \_module_inst: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 |vpiName:ix_result |vpiFullName:work@int_execute_stage.ix_result |vpiNetType:36 |vpiNet: \_logic_net: (work@int_execute_stage.ix_mask_value), line:74:39, endln:74:52 |vpiParent: - \_module: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 + \_module_inst: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 |vpiName:ix_mask_value |vpiFullName:work@int_execute_stage.ix_mask_value |vpiNet: \_logic_net: (work@int_execute_stage.ix_thread_idx), line:75:39, endln:75:52 |vpiParent: - \_module: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 + \_module_inst: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 |vpiName:ix_thread_idx |vpiFullName:work@int_execute_stage.ix_thread_idx |vpiNet: \_logic_net: (work@int_execute_stage.ix_rollback_en), line:76:39, endln:76:53 |vpiParent: - \_module: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 + \_module_inst: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 |vpiName:ix_rollback_en |vpiFullName:work@int_execute_stage.ix_rollback_en |vpiNetType:36 |vpiNet: \_logic_net: (work@int_execute_stage.ix_rollback_pc), line:77:39, endln:77:53 |vpiParent: - \_module: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 + \_module_inst: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 |vpiName:ix_rollback_pc |vpiFullName:work@int_execute_stage.ix_rollback_pc |vpiNetType:36 |vpiNet: \_logic_net: (work@int_execute_stage.ix_subcycle), line:78:39, endln:78:50 |vpiParent: - \_module: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 + \_module_inst: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 |vpiName:ix_subcycle |vpiFullName:work@int_execute_stage.ix_subcycle |vpiNet: \_logic_net: (work@int_execute_stage.ix_privileged_op_fault), line:79:39, endln:79:61 |vpiParent: - \_module: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 + \_module_inst: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 |vpiName:ix_privileged_op_fault |vpiFullName:work@int_execute_stage.ix_privileged_op_fault |vpiNetType:36 |vpiNet: \_logic_net: (work@int_execute_stage.cr_eret_address), line:82:39, endln:82:54 |vpiParent: - \_module: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 + \_module_inst: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 |vpiName:cr_eret_address |vpiFullName:work@int_execute_stage.cr_eret_address |vpiNetType:36 |vpiNet: \_logic_net: (work@int_execute_stage.cr_supervisor_en), line:83:39, endln:83:55 |vpiParent: - \_module: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 + \_module_inst: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 |vpiName:cr_supervisor_en |vpiFullName:work@int_execute_stage.cr_supervisor_en |vpiNet: \_logic_net: (work@int_execute_stage.ix_perf_uncond_branch), line:86:39, endln:86:60 |vpiParent: - \_module: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 + \_module_inst: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 |vpiName:ix_perf_uncond_branch |vpiFullName:work@int_execute_stage.ix_perf_uncond_branch |vpiNetType:36 |vpiNet: \_logic_net: (work@int_execute_stage.ix_perf_cond_branch_taken), line:87:39, endln:87:64 |vpiParent: - \_module: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 + \_module_inst: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 |vpiName:ix_perf_cond_branch_taken |vpiFullName:work@int_execute_stage.ix_perf_cond_branch_taken |vpiNetType:36 |vpiNet: \_logic_net: (work@int_execute_stage.ix_perf_cond_branch_not_taken), line:88:39, endln:88:68 |vpiParent: - \_module: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 + \_module_inst: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 |vpiName:ix_perf_cond_branch_not_taken |vpiFullName:work@int_execute_stage.ix_perf_cond_branch_not_taken |vpiNetType:36 |vpiNet: \_logic_net: (work@int_execute_stage.vector_result), line:90:14, endln:90:27 |vpiParent: - \_module: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 + \_module_inst: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 |vpiName:vector_result |vpiFullName:work@int_execute_stage.vector_result |vpiNetType:36 |vpiNet: \_logic_net: (work@int_execute_stage.eret), line:91:11, endln:91:15 |vpiParent: - \_module: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 + \_module_inst: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 |vpiName:eret |vpiFullName:work@int_execute_stage.eret |vpiNetType:36 |vpiNet: \_logic_net: (work@int_execute_stage.privileged_op_fault), line:92:11, endln:92:30 |vpiParent: - \_module: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 + \_module_inst: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 |vpiName:privileged_op_fault |vpiFullName:work@int_execute_stage.privileged_op_fault |vpiNetType:36 |vpiNet: \_logic_net: (work@int_execute_stage.branch_taken), line:93:11, endln:93:23 |vpiParent: - \_module: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 + \_module_inst: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 |vpiName:branch_taken |vpiFullName:work@int_execute_stage.branch_taken |vpiNetType:36 |vpiNet: \_logic_net: (work@int_execute_stage.conditional_branch), line:94:11, endln:94:29 |vpiParent: - \_module: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 + \_module_inst: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 |vpiName:conditional_branch |vpiFullName:work@int_execute_stage.conditional_branch |vpiNetType:36 |vpiNet: \_logic_net: (work@int_execute_stage.valid_instruction), line:95:11, endln:95:28 |vpiParent: - \_module: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 + \_module_inst: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 |vpiName:valid_instruction |vpiFullName:work@int_execute_stage.valid_instruction |vpiNetType:36 |vpiPort: \_port: (clk), line:54:39, endln:54:42 |vpiParent: - \_module: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 + \_module_inst: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 |vpiName:clk |vpiDirection:1 |vpiLowConn: @@ -4919,7 +4919,7 @@ design: (work@int_execute_stage) |vpiPort: \_port: (reset), line:55:39, endln:55:44 |vpiParent: - \_module: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 + \_module_inst: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 |vpiName:reset |vpiDirection:1 |vpiLowConn: @@ -4931,7 +4931,7 @@ design: (work@int_execute_stage) |vpiPort: \_port: (of_operand1), line:58:39, endln:58:50 |vpiParent: - \_module: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 + \_module_inst: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 |vpiName:of_operand1 |vpiDirection:1 |vpiLowConn: @@ -5024,7 +5024,7 @@ design: (work@int_execute_stage) |vpiPort: \_port: (of_operand2), line:59:39, endln:59:50 |vpiParent: - \_module: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 + \_module_inst: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 |vpiName:of_operand2 |vpiDirection:1 |vpiLowConn: @@ -5036,7 +5036,7 @@ design: (work@int_execute_stage) |vpiPort: \_port: (of_mask_value), line:60:39, endln:60:52 |vpiParent: - \_module: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 + \_module_inst: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 |vpiName:of_mask_value |vpiDirection:1 |vpiLowConn: @@ -5049,7 +5049,7 @@ design: (work@int_execute_stage) |vpiPort: \_port: (of_instruction_valid), line:61:39, endln:61:59 |vpiParent: - \_module: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 + \_module_inst: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 |vpiName:of_instruction_valid |vpiDirection:1 |vpiLowConn: @@ -5061,7 +5061,7 @@ design: (work@int_execute_stage) |vpiPort: \_port: (of_instruction), line:62:39, endln:62:53 |vpiParent: - \_module: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 + \_module_inst: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 |vpiName:of_instruction |vpiDirection:1 |vpiLowConn: @@ -5559,7 +5559,7 @@ design: (work@int_execute_stage) |vpiPort: \_port: (of_thread_idx), line:63:39, endln:63:52 |vpiParent: - \_module: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 + \_module_inst: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 |vpiName:of_thread_idx |vpiDirection:1 |vpiLowConn: @@ -5572,7 +5572,7 @@ design: (work@int_execute_stage) |vpiPort: \_port: (of_subcycle), line:64:39, endln:64:50 |vpiParent: - \_module: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 + \_module_inst: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 |vpiName:of_subcycle |vpiDirection:1 |vpiLowConn: @@ -5585,7 +5585,7 @@ design: (work@int_execute_stage) |vpiPort: \_port: (wb_rollback_en), line:67:39, endln:67:53 |vpiParent: - \_module: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 + \_module_inst: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 |vpiName:wb_rollback_en |vpiDirection:1 |vpiLowConn: @@ -5597,7 +5597,7 @@ design: (work@int_execute_stage) |vpiPort: \_port: (wb_rollback_thread_idx), line:68:39, endln:68:61 |vpiParent: - \_module: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 + \_module_inst: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 |vpiName:wb_rollback_thread_idx |vpiDirection:1 |vpiLowConn: @@ -5610,7 +5610,7 @@ design: (work@int_execute_stage) |vpiPort: \_port: (ix_instruction_valid), line:71:39, endln:71:59 |vpiParent: - \_module: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 + \_module_inst: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 |vpiName:ix_instruction_valid |vpiDirection:2 |vpiLowConn: @@ -5622,7 +5622,7 @@ design: (work@int_execute_stage) |vpiPort: \_port: (ix_instruction), line:72:39, endln:72:53 |vpiParent: - \_module: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 + \_module_inst: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 |vpiName:ix_instruction |vpiDirection:2 |vpiLowConn: @@ -5634,7 +5634,7 @@ design: (work@int_execute_stage) |vpiPort: \_port: (ix_result), line:73:39, endln:73:48 |vpiParent: - \_module: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 + \_module_inst: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 |vpiName:ix_result |vpiDirection:2 |vpiLowConn: @@ -5646,7 +5646,7 @@ design: (work@int_execute_stage) |vpiPort: \_port: (ix_mask_value), line:74:39, endln:74:52 |vpiParent: - \_module: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 + \_module_inst: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 |vpiName:ix_mask_value |vpiDirection:2 |vpiLowConn: @@ -5659,7 +5659,7 @@ design: (work@int_execute_stage) |vpiPort: \_port: (ix_thread_idx), line:75:39, endln:75:52 |vpiParent: - \_module: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 + \_module_inst: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 |vpiName:ix_thread_idx |vpiDirection:2 |vpiLowConn: @@ -5672,7 +5672,7 @@ design: (work@int_execute_stage) |vpiPort: \_port: (ix_rollback_en), line:76:39, endln:76:53 |vpiParent: - \_module: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 + \_module_inst: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 |vpiName:ix_rollback_en |vpiDirection:2 |vpiLowConn: @@ -5684,7 +5684,7 @@ design: (work@int_execute_stage) |vpiPort: \_port: (ix_rollback_pc), line:77:39, endln:77:53 |vpiParent: - \_module: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 + \_module_inst: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 |vpiName:ix_rollback_pc |vpiDirection:2 |vpiLowConn: @@ -5721,7 +5721,7 @@ design: (work@int_execute_stage) |vpiPort: \_port: (ix_subcycle), line:78:39, endln:78:50 |vpiParent: - \_module: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 + \_module_inst: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 |vpiName:ix_subcycle |vpiDirection:2 |vpiLowConn: @@ -5734,7 +5734,7 @@ design: (work@int_execute_stage) |vpiPort: \_port: (ix_privileged_op_fault), line:79:39, endln:79:61 |vpiParent: - \_module: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 + \_module_inst: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 |vpiName:ix_privileged_op_fault |vpiDirection:2 |vpiLowConn: @@ -5746,7 +5746,7 @@ design: (work@int_execute_stage) |vpiPort: \_port: (cr_eret_address), line:82:39, endln:82:54 |vpiParent: - \_module: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 + \_module_inst: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 |vpiName:cr_eret_address |vpiDirection:1 |vpiLowConn: @@ -5814,7 +5814,7 @@ design: (work@int_execute_stage) |vpiPort: \_port: (cr_supervisor_en), line:83:39, endln:83:55 |vpiParent: - \_module: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 + \_module_inst: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 |vpiName:cr_supervisor_en |vpiDirection:1 |vpiLowConn: @@ -5857,7 +5857,7 @@ design: (work@int_execute_stage) |vpiPort: \_port: (ix_perf_uncond_branch), line:86:39, endln:86:60 |vpiParent: - \_module: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 + \_module_inst: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 |vpiName:ix_perf_uncond_branch |vpiDirection:2 |vpiLowConn: @@ -5869,7 +5869,7 @@ design: (work@int_execute_stage) |vpiPort: \_port: (ix_perf_cond_branch_taken), line:87:39, endln:87:64 |vpiParent: - \_module: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 + \_module_inst: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 |vpiName:ix_perf_cond_branch_taken |vpiDirection:2 |vpiLowConn: @@ -5881,7 +5881,7 @@ design: (work@int_execute_stage) |vpiPort: \_port: (ix_perf_cond_branch_not_taken), line:88:39, endln:88:68 |vpiParent: - \_module: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 + \_module_inst: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 |vpiName:ix_perf_cond_branch_not_taken |vpiDirection:2 |vpiLowConn: @@ -5893,7 +5893,7 @@ design: (work@int_execute_stage) |vpiProcess: \_always: , line:285:5, endln:320:8 |vpiParent: - \_module: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 + \_module_inst: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 |vpiStmt: \_begin: (work@int_execute_stage), line:286:5, endln:320:8 |vpiParent: @@ -6262,7 +6262,7 @@ design: (work@int_execute_stage) |vpiProcess: \_always: , line:323:5, endln:339:8 |vpiParent: - \_module: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 + \_module_inst: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 |vpiStmt: \_event_control: , line:323:15, endln:323:29 |vpiParent: @@ -6555,7 +6555,7 @@ design: (work@int_execute_stage) |vpiProcess: \_always: , line:341:5, endln:373:8 |vpiParent: - \_module: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 + \_module_inst: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 |vpiStmt: \_event_control: , line:341:15, endln:341:44 |vpiParent: @@ -6981,7 +6981,7 @@ design: (work@int_execute_stage) |vpiContAssign: \_cont_assign: , line:277:12, endln:279:57 |vpiParent: - \_module: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 + \_module_inst: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 |vpiRhs: \_operation: , line:277:32, endln:279:57 |vpiParent: @@ -7076,7 +7076,7 @@ design: (work@int_execute_stage) |vpiContAssign: \_cont_assign: , line:280:12, endln:282:53 |vpiParent: - \_module: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 + \_module_inst: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 |vpiRhs: \_operation: , line:280:19, endln:282:53 |vpiParent: @@ -7145,7 +7145,7 @@ design: (work@int_execute_stage) |vpiContAssign: \_cont_assign: , line:283:12, endln:283:74 |vpiParent: - \_module: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 + \_module_inst: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 |vpiRhs: \_operation: , line:283:34, endln:283:74 |vpiParent: @@ -7309,19 +7309,19 @@ design: (work@int_execute_stage) |vpiTypedef: \_logic_typespec: (vector_t), line:51:9, endln:51:17 |uhdmtopModules: -\_module: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 +\_module_inst: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 |vpiName:work@int_execute_stage |vpiVariables: \_logic_var: (work@int_execute_stage.of_mask_value), line:60:39, endln:60:52 |vpiParent: - \_module: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 + \_module_inst: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 |vpiName:of_mask_value |vpiFullName:work@int_execute_stage.of_mask_value |vpiVisibility:1 |vpiVariables: \_struct_var: (work@int_execute_stage.of_instruction), line:62:39, endln:62:53 |vpiParent: - \_module: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 + \_module_inst: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 |vpiTypespec: \_struct_typespec: (decoded_instruction_t), line:8:9, endln:8:15 |vpiName:of_instruction @@ -7330,28 +7330,28 @@ design: (work@int_execute_stage) |vpiVariables: \_logic_var: (work@int_execute_stage.of_thread_idx), line:63:39, endln:63:52 |vpiParent: - \_module: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 + \_module_inst: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 |vpiName:of_thread_idx |vpiFullName:work@int_execute_stage.of_thread_idx |vpiVisibility:1 |vpiVariables: \_logic_var: (work@int_execute_stage.of_subcycle), line:64:39, endln:64:50 |vpiParent: - \_module: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 + \_module_inst: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 |vpiName:of_subcycle |vpiFullName:work@int_execute_stage.of_subcycle |vpiVisibility:1 |vpiVariables: \_logic_var: (work@int_execute_stage.wb_rollback_thread_idx), line:68:39, endln:68:61 |vpiParent: - \_module: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 + \_module_inst: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 |vpiName:wb_rollback_thread_idx |vpiFullName:work@int_execute_stage.wb_rollback_thread_idx |vpiVisibility:1 |vpiVariables: \_struct_var: (work@int_execute_stage.ix_instruction), line:72:39, endln:72:53 |vpiParent: - \_module: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 + \_module_inst: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 |vpiTypespec: \_struct_typespec: (decoded_instruction_t), line:8:9, endln:8:15 |vpiName:ix_instruction @@ -7360,28 +7360,28 @@ design: (work@int_execute_stage) |vpiVariables: \_logic_var: (work@int_execute_stage.ix_mask_value), line:74:39, endln:74:52 |vpiParent: - \_module: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 + \_module_inst: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 |vpiName:ix_mask_value |vpiFullName:work@int_execute_stage.ix_mask_value |vpiVisibility:1 |vpiVariables: \_logic_var: (work@int_execute_stage.ix_thread_idx), line:75:39, endln:75:52 |vpiParent: - \_module: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 + \_module_inst: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 |vpiName:ix_thread_idx |vpiFullName:work@int_execute_stage.ix_thread_idx |vpiVisibility:1 |vpiVariables: \_logic_var: (work@int_execute_stage.ix_subcycle), line:78:39, endln:78:50 |vpiParent: - \_module: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 + \_module_inst: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 |vpiName:ix_subcycle |vpiFullName:work@int_execute_stage.ix_subcycle |vpiVisibility:1 |vpiVariables: \_logic_var: (work@int_execute_stage.vector_result), line:90:14, endln:90:27 |vpiParent: - \_module: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 + \_module_inst: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 |vpiTypespec: \_logic_typespec: (scalar_t), line:50:9, endln:50:20 |vpiName:scalar_t @@ -7411,7 +7411,7 @@ design: (work@int_execute_stage) |vpiVariables: \_logic_var: (work@int_execute_stage.eret), line:91:11, endln:91:15 |vpiParent: - \_module: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 + \_module_inst: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 |vpiTypespec: \_logic_typespec: , line:91:5, endln:91:10 |vpiName:eret @@ -7420,7 +7420,7 @@ design: (work@int_execute_stage) |vpiVariables: \_logic_var: (work@int_execute_stage.privileged_op_fault), line:92:11, endln:92:30 |vpiParent: - \_module: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 + \_module_inst: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 |vpiTypespec: \_logic_typespec: , line:92:5, endln:92:10 |vpiName:privileged_op_fault @@ -7429,7 +7429,7 @@ design: (work@int_execute_stage) |vpiVariables: \_logic_var: (work@int_execute_stage.branch_taken), line:93:11, endln:93:23 |vpiParent: - \_module: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 + \_module_inst: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 |vpiTypespec: \_logic_typespec: , line:93:5, endln:93:10 |vpiName:branch_taken @@ -7438,7 +7438,7 @@ design: (work@int_execute_stage) |vpiVariables: \_logic_var: (work@int_execute_stage.conditional_branch), line:94:11, endln:94:29 |vpiParent: - \_module: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 + \_module_inst: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 |vpiTypespec: \_logic_typespec: , line:94:5, endln:94:10 |vpiName:conditional_branch @@ -7447,7 +7447,7 @@ design: (work@int_execute_stage) |vpiVariables: \_logic_var: (work@int_execute_stage.valid_instruction), line:95:11, endln:95:28 |vpiParent: - \_module: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 + \_module_inst: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 |vpiTypespec: \_logic_typespec: , line:95:5, endln:95:10 |vpiName:valid_instruction @@ -7458,7 +7458,7 @@ design: (work@int_execute_stage) |vpiNet: \_logic_net: (work@int_execute_stage.clk), line:54:39, endln:54:42 |vpiParent: - \_module: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 + \_module_inst: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 |vpiTypespec: \_logic_typespec: , line:54:39, endln:54:39 |vpiName:clk @@ -7466,7 +7466,7 @@ design: (work@int_execute_stage) |vpiNet: \_logic_net: (work@int_execute_stage.reset), line:55:39, endln:55:44 |vpiParent: - \_module: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 + \_module_inst: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 |vpiTypespec: \_logic_typespec: , line:55:39, endln:55:39 |vpiName:reset @@ -7474,7 +7474,7 @@ design: (work@int_execute_stage) |vpiNet: \_logic_net: (work@int_execute_stage.of_operand1), line:58:39, endln:58:50 |vpiParent: - \_module: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 + \_module_inst: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 |vpiTypespec: \_logic_typespec: (scalar_t), line:50:9, endln:50:20 |vpiName:of_operand1 @@ -7483,7 +7483,7 @@ design: (work@int_execute_stage) |vpiNet: \_logic_net: (work@int_execute_stage.of_operand2), line:59:39, endln:59:50 |vpiParent: - \_module: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 + \_module_inst: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 |vpiTypespec: \_logic_typespec: (scalar_t), line:50:9, endln:50:20 |vpiName:of_operand2 @@ -7492,7 +7492,7 @@ design: (work@int_execute_stage) |vpiNet: \_logic_net: (work@int_execute_stage.of_instruction_valid), line:61:39, endln:61:59 |vpiParent: - \_module: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 + \_module_inst: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 |vpiTypespec: \_logic_typespec: , line:61:39, endln:61:39 |vpiName:of_instruction_valid @@ -7500,7 +7500,7 @@ design: (work@int_execute_stage) |vpiNet: \_logic_net: (work@int_execute_stage.wb_rollback_en), line:67:39, endln:67:53 |vpiParent: - \_module: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 + \_module_inst: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 |vpiTypespec: \_logic_typespec: , line:67:11, endln:67:16 |vpiName:wb_rollback_en @@ -7509,7 +7509,7 @@ design: (work@int_execute_stage) |vpiNet: \_logic_net: (work@int_execute_stage.ix_instruction_valid), line:71:39, endln:71:59 |vpiParent: - \_module: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 + \_module_inst: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 |vpiTypespec: \_logic_typespec: , line:71:12, endln:71:17 |vpiName:ix_instruction_valid @@ -7518,7 +7518,7 @@ design: (work@int_execute_stage) |vpiNet: \_logic_net: (work@int_execute_stage.ix_result), line:73:39, endln:73:48 |vpiParent: - \_module: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 + \_module_inst: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 |vpiTypespec: \_logic_typespec: (scalar_t), line:50:9, endln:50:20 |vpiName:ix_result @@ -7527,7 +7527,7 @@ design: (work@int_execute_stage) |vpiNet: \_logic_net: (work@int_execute_stage.ix_rollback_en), line:76:39, endln:76:53 |vpiParent: - \_module: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 + \_module_inst: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 |vpiTypespec: \_logic_typespec: , line:76:12, endln:76:17 |vpiName:ix_rollback_en @@ -7536,7 +7536,7 @@ design: (work@int_execute_stage) |vpiNet: \_logic_net: (work@int_execute_stage.ix_rollback_pc), line:77:39, endln:77:53 |vpiParent: - \_module: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 + \_module_inst: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 |vpiTypespec: \_logic_typespec: (scalar_t), line:50:9, endln:50:20 |vpiName:ix_rollback_pc @@ -7545,7 +7545,7 @@ design: (work@int_execute_stage) |vpiNet: \_logic_net: (work@int_execute_stage.ix_privileged_op_fault), line:79:39, endln:79:61 |vpiParent: - \_module: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 + \_module_inst: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 |vpiTypespec: \_logic_typespec: , line:79:12, endln:79:17 |vpiName:ix_privileged_op_fault @@ -7554,7 +7554,7 @@ design: (work@int_execute_stage) |vpiNet: \_logic_net: (work@int_execute_stage.ix_perf_uncond_branch), line:86:39, endln:86:60 |vpiParent: - \_module: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 + \_module_inst: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 |vpiTypespec: \_logic_typespec: , line:86:12, endln:86:17 |vpiName:ix_perf_uncond_branch @@ -7563,7 +7563,7 @@ design: (work@int_execute_stage) |vpiNet: \_logic_net: (work@int_execute_stage.ix_perf_cond_branch_taken), line:87:39, endln:87:64 |vpiParent: - \_module: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 + \_module_inst: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 |vpiTypespec: \_logic_typespec: , line:87:12, endln:87:17 |vpiName:ix_perf_cond_branch_taken @@ -7572,7 +7572,7 @@ design: (work@int_execute_stage) |vpiNet: \_logic_net: (work@int_execute_stage.ix_perf_cond_branch_not_taken), line:88:39, endln:88:68 |vpiParent: - \_module: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 + \_module_inst: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 |vpiTypespec: \_logic_typespec: , line:88:12, endln:88:17 |vpiName:ix_perf_cond_branch_not_taken @@ -7613,7 +7613,7 @@ design: (work@int_execute_stage) |vpiArrayNet: \_array_net: (work@int_execute_stage.cr_eret_address), line:82:39, endln:82:54 |vpiParent: - \_module: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 + \_module_inst: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 |vpiSize:8 |vpiName:cr_eret_address |vpiFullName:work@int_execute_stage.cr_eret_address @@ -7655,7 +7655,7 @@ design: (work@int_execute_stage) |vpiArrayNet: \_array_net: (work@int_execute_stage.cr_supervisor_en), line:83:39, endln:83:55 |vpiParent: - \_module: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 + \_module_inst: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 |vpiSize:8 |vpiName:cr_supervisor_en |vpiFullName:work@int_execute_stage.cr_supervisor_en @@ -7696,7 +7696,7 @@ design: (work@int_execute_stage) |vpiPort: \_port: (clk), line:54:39, endln:54:42 |vpiParent: - \_module: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 + \_module_inst: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 |vpiName:clk |vpiDirection:1 |vpiLowConn: @@ -7710,11 +7710,11 @@ design: (work@int_execute_stage) |vpiTypedef: \_logic_typespec: , line:54:39, endln:54:39 |vpiInstance: - \_module: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 + \_module_inst: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 |vpiPort: \_port: (reset), line:55:39, endln:55:44 |vpiParent: - \_module: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 + \_module_inst: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 |vpiName:reset |vpiDirection:1 |vpiLowConn: @@ -7728,11 +7728,11 @@ design: (work@int_execute_stage) |vpiTypedef: \_logic_typespec: , line:55:39, endln:55:39 |vpiInstance: - \_module: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 + \_module_inst: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 |vpiPort: \_port: (of_operand1), line:58:39, endln:58:50 |vpiParent: - \_module: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 + \_module_inst: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 |vpiName:of_operand1 |vpiDirection:1 |vpiLowConn: @@ -7746,11 +7746,11 @@ design: (work@int_execute_stage) |vpiTypedef: \_logic_typespec: (vector_t), line:51:9, endln:51:17 |vpiInstance: - \_module: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 + \_module_inst: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 |vpiPort: \_port: (of_operand2), line:59:39, endln:59:50 |vpiParent: - \_module: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 + \_module_inst: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 |vpiName:of_operand2 |vpiDirection:1 |vpiLowConn: @@ -7764,11 +7764,11 @@ design: (work@int_execute_stage) |vpiTypedef: \_logic_typespec: (vector_t), line:51:9, endln:51:17 |vpiInstance: - \_module: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 + \_module_inst: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 |vpiPort: \_port: (of_mask_value), line:60:39, endln:60:52 |vpiParent: - \_module: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 + \_module_inst: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 |vpiName:of_mask_value |vpiDirection:1 |vpiLowConn: @@ -7783,11 +7783,11 @@ design: (work@int_execute_stage) \_unsupported_typespec: (vector_mask_t), line:60:11, endln:60:24 |vpiName:vector_mask_t |vpiInstance: - \_module: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 + \_module_inst: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 |vpiPort: \_port: (of_instruction_valid), line:61:39, endln:61:59 |vpiParent: - \_module: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 + \_module_inst: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 |vpiName:of_instruction_valid |vpiDirection:1 |vpiLowConn: @@ -7801,11 +7801,11 @@ design: (work@int_execute_stage) |vpiTypedef: \_logic_typespec: , line:61:39, endln:61:39 |vpiInstance: - \_module: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 + \_module_inst: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 |vpiPort: \_port: (of_instruction), line:62:39, endln:62:53 |vpiParent: - \_module: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 + \_module_inst: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 |vpiName:of_instruction |vpiDirection:1 |vpiLowConn: @@ -7819,11 +7819,11 @@ design: (work@int_execute_stage) |vpiTypedef: \_struct_typespec: (decoded_instruction_t), line:8:9, endln:8:15 |vpiInstance: - \_module: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 + \_module_inst: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 |vpiPort: \_port: (of_thread_idx), line:63:39, endln:63:52 |vpiParent: - \_module: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 + \_module_inst: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 |vpiName:of_thread_idx |vpiDirection:1 |vpiLowConn: @@ -7838,11 +7838,11 @@ design: (work@int_execute_stage) \_unsupported_typespec: (local_thread_idx_t), line:63:11, endln:63:29 |vpiName:local_thread_idx_t |vpiInstance: - \_module: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 + \_module_inst: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 |vpiPort: \_port: (of_subcycle), line:64:39, endln:64:50 |vpiParent: - \_module: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 + \_module_inst: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 |vpiName:of_subcycle |vpiDirection:1 |vpiLowConn: @@ -7857,11 +7857,11 @@ design: (work@int_execute_stage) \_unsupported_typespec: (subcycle_t), line:64:11, endln:64:21 |vpiName:subcycle_t |vpiInstance: - \_module: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 + \_module_inst: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 |vpiPort: \_port: (wb_rollback_en), line:67:39, endln:67:53 |vpiParent: - \_module: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 + \_module_inst: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 |vpiName:wb_rollback_en |vpiDirection:1 |vpiLowConn: @@ -7875,11 +7875,11 @@ design: (work@int_execute_stage) |vpiTypedef: \_logic_typespec: , line:67:11, endln:67:16 |vpiInstance: - \_module: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 + \_module_inst: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 |vpiPort: \_port: (wb_rollback_thread_idx), line:68:39, endln:68:61 |vpiParent: - \_module: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 + \_module_inst: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 |vpiName:wb_rollback_thread_idx |vpiDirection:1 |vpiLowConn: @@ -7894,11 +7894,11 @@ design: (work@int_execute_stage) \_unsupported_typespec: (local_thread_idx_t), line:68:11, endln:68:29 |vpiName:local_thread_idx_t |vpiInstance: - \_module: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 + \_module_inst: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 |vpiPort: \_port: (ix_instruction_valid), line:71:39, endln:71:59 |vpiParent: - \_module: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 + \_module_inst: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 |vpiName:ix_instruction_valid |vpiDirection:2 |vpiLowConn: @@ -7912,11 +7912,11 @@ design: (work@int_execute_stage) |vpiTypedef: \_logic_typespec: , line:71:12, endln:71:17 |vpiInstance: - \_module: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 + \_module_inst: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 |vpiPort: \_port: (ix_instruction), line:72:39, endln:72:53 |vpiParent: - \_module: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 + \_module_inst: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 |vpiName:ix_instruction |vpiDirection:2 |vpiLowConn: @@ -7930,11 +7930,11 @@ design: (work@int_execute_stage) |vpiTypedef: \_struct_typespec: (decoded_instruction_t), line:8:9, endln:8:15 |vpiInstance: - \_module: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 + \_module_inst: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 |vpiPort: \_port: (ix_result), line:73:39, endln:73:48 |vpiParent: - \_module: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 + \_module_inst: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 |vpiName:ix_result |vpiDirection:2 |vpiLowConn: @@ -7948,11 +7948,11 @@ design: (work@int_execute_stage) |vpiTypedef: \_logic_typespec: (vector_t), line:51:9, endln:51:17 |vpiInstance: - \_module: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 + \_module_inst: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 |vpiPort: \_port: (ix_mask_value), line:74:39, endln:74:52 |vpiParent: - \_module: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 + \_module_inst: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 |vpiName:ix_mask_value |vpiDirection:2 |vpiLowConn: @@ -7967,11 +7967,11 @@ design: (work@int_execute_stage) \_unsupported_typespec: (vector_mask_t), line:74:12, endln:74:25 |vpiName:vector_mask_t |vpiInstance: - \_module: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 + \_module_inst: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 |vpiPort: \_port: (ix_thread_idx), line:75:39, endln:75:52 |vpiParent: - \_module: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 + \_module_inst: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 |vpiName:ix_thread_idx |vpiDirection:2 |vpiLowConn: @@ -7986,11 +7986,11 @@ design: (work@int_execute_stage) \_unsupported_typespec: (local_thread_idx_t), line:75:12, endln:75:30 |vpiName:local_thread_idx_t |vpiInstance: - \_module: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 + \_module_inst: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 |vpiPort: \_port: (ix_rollback_en), line:76:39, endln:76:53 |vpiParent: - \_module: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 + \_module_inst: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 |vpiName:ix_rollback_en |vpiDirection:2 |vpiLowConn: @@ -8004,11 +8004,11 @@ design: (work@int_execute_stage) |vpiTypedef: \_logic_typespec: , line:76:12, endln:76:17 |vpiInstance: - \_module: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 + \_module_inst: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 |vpiPort: \_port: (ix_rollback_pc), line:77:39, endln:77:53 |vpiParent: - \_module: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 + \_module_inst: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 |vpiName:ix_rollback_pc |vpiDirection:2 |vpiLowConn: @@ -8045,11 +8045,11 @@ design: (work@int_execute_stage) |UINT:0 |vpiConstType:9 |vpiInstance: - \_module: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 + \_module_inst: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 |vpiPort: \_port: (ix_subcycle), line:78:39, endln:78:50 |vpiParent: - \_module: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 + \_module_inst: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 |vpiName:ix_subcycle |vpiDirection:2 |vpiLowConn: @@ -8064,11 +8064,11 @@ design: (work@int_execute_stage) \_unsupported_typespec: (subcycle_t), line:78:12, endln:78:22 |vpiName:subcycle_t |vpiInstance: - \_module: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 + \_module_inst: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 |vpiPort: \_port: (ix_privileged_op_fault), line:79:39, endln:79:61 |vpiParent: - \_module: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 + \_module_inst: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 |vpiName:ix_privileged_op_fault |vpiDirection:2 |vpiLowConn: @@ -8082,11 +8082,11 @@ design: (work@int_execute_stage) |vpiTypedef: \_logic_typespec: , line:79:12, endln:79:17 |vpiInstance: - \_module: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 + \_module_inst: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 |vpiPort: \_port: (cr_eret_address), line:82:39, endln:82:54 |vpiParent: - \_module: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 + \_module_inst: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 |vpiName:cr_eret_address |vpiDirection:1 |vpiLowConn: @@ -8123,11 +8123,11 @@ design: (work@int_execute_stage) |UINT:0 |vpiConstType:9 |vpiInstance: - \_module: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 + \_module_inst: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 |vpiPort: \_port: (cr_supervisor_en), line:83:39, endln:83:55 |vpiParent: - \_module: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 + \_module_inst: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 |vpiName:cr_supervisor_en |vpiDirection:1 |vpiLowConn: @@ -8141,11 +8141,11 @@ design: (work@int_execute_stage) |vpiTypedef: \_logic_typespec: , line:83:39, endln:83:39 |vpiInstance: - \_module: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 + \_module_inst: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 |vpiPort: \_port: (ix_perf_uncond_branch), line:86:39, endln:86:60 |vpiParent: - \_module: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 + \_module_inst: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 |vpiName:ix_perf_uncond_branch |vpiDirection:2 |vpiLowConn: @@ -8159,11 +8159,11 @@ design: (work@int_execute_stage) |vpiTypedef: \_logic_typespec: , line:86:12, endln:86:17 |vpiInstance: - \_module: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 + \_module_inst: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 |vpiPort: \_port: (ix_perf_cond_branch_taken), line:87:39, endln:87:64 |vpiParent: - \_module: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 + \_module_inst: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 |vpiName:ix_perf_cond_branch_taken |vpiDirection:2 |vpiLowConn: @@ -8177,11 +8177,11 @@ design: (work@int_execute_stage) |vpiTypedef: \_logic_typespec: , line:87:12, endln:87:17 |vpiInstance: - \_module: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 + \_module_inst: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 |vpiPort: \_port: (ix_perf_cond_branch_not_taken), line:88:39, endln:88:68 |vpiParent: - \_module: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 + \_module_inst: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 |vpiName:ix_perf_cond_branch_not_taken |vpiDirection:2 |vpiLowConn: @@ -8195,11 +8195,11 @@ design: (work@int_execute_stage) |vpiTypedef: \_logic_typespec: , line:88:12, endln:88:17 |vpiInstance: - \_module: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 + \_module_inst: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 |vpiProcess: \_always: , line:285:5, endln:320:8 |vpiParent: - \_module: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 + \_module_inst: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 |vpiStmt: \_begin: (work@int_execute_stage), line:286:5, endln:320:8 |vpiParent: @@ -8534,7 +8534,7 @@ design: (work@int_execute_stage) |vpiProcess: \_always: , line:323:5, endln:339:8 |vpiParent: - \_module: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 + \_module_inst: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 |vpiStmt: \_event_control: , line:323:15, endln:323:29 |vpiParent: @@ -8847,7 +8847,7 @@ design: (work@int_execute_stage) |vpiProcess: \_always: , line:341:5, endln:373:8 |vpiParent: - \_module: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 + \_module_inst: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 |vpiStmt: \_event_control: , line:341:15, endln:341:44 |vpiParent: @@ -9261,7 +9261,7 @@ design: (work@int_execute_stage) |vpiGenScopeArray: \_gen_scope_array: (work@int_execute_stage.lane_alu_gen[0]), line:100:9, endln:274:12 |vpiParent: - \_module: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 + \_module_inst: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 |vpiName:lane_alu_gen[0] |vpiFullName:work@int_execute_stage.lane_alu_gen[0] |vpiGenScope: @@ -14623,8 +14623,8 @@ design: (work@int_execute_stage) \_parameter: (work@int_execute_stage.lane_alu_gen[0].lane), line:99:0 |vpiActual: \_logic_var: (work@int_execute_stage.vector_result), line:90:14, endln:90:27 - |vpiModule: - \_module: work@int_execute_stage.lane_alu_gen[0]::reciprocal_rom (work@int_execute_stage.lane_alu_gen[0].rom), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:214:13, endln:216:39 + |vpiModuleInst: + \_module_inst: work@int_execute_stage.lane_alu_gen[0]::reciprocal_rom (work@int_execute_stage.lane_alu_gen[0].rom), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:214:13, endln:216:39 |vpiParent: \_gen_scope: (work@int_execute_stage.lane_alu_gen[0]) |vpiName:rom @@ -14633,7 +14633,7 @@ design: (work@int_execute_stage) |vpiPort: \_port: (significand), line:215:18, endln:215:29 |vpiParent: - \_module: work@int_execute_stage.lane_alu_gen[0]::reciprocal_rom (work@int_execute_stage.lane_alu_gen[0].rom), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:214:13, endln:216:39 + \_module_inst: work@int_execute_stage.lane_alu_gen[0]::reciprocal_rom (work@int_execute_stage.lane_alu_gen[0].rom), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:214:13, endln:216:39 |vpiName:significand |vpiHighConn: \_hier_path: (fp_operand.significand[22:17]), line:215:30, endln:215:59 @@ -14675,11 +14675,11 @@ design: (work@int_execute_stage) |vpiExpr: \_struct_net: (work@int_execute_stage.lane_alu_gen[0].fp_operand), line:113:23, endln:113:33 |vpiInstance: - \_module: work@int_execute_stage.lane_alu_gen[0]::reciprocal_rom (work@int_execute_stage.lane_alu_gen[0].rom), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:214:13, endln:216:39 + \_module_inst: work@int_execute_stage.lane_alu_gen[0]::reciprocal_rom (work@int_execute_stage.lane_alu_gen[0].rom), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:214:13, endln:216:39 |vpiPort: \_port: (reciprocal_estimate), line:216:18, endln:216:37 |vpiParent: - \_module: work@int_execute_stage.lane_alu_gen[0]::reciprocal_rom (work@int_execute_stage.lane_alu_gen[0].rom), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:214:13, endln:216:39 + \_module_inst: work@int_execute_stage.lane_alu_gen[0]::reciprocal_rom (work@int_execute_stage.lane_alu_gen[0].rom), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:214:13, endln:216:39 |vpiName:reciprocal_estimate |vpiHighConn: \_ref_obj: (work@int_execute_stage.lane_alu_gen[0].reciprocal_estimate), line:216:18, endln:216:37 @@ -14690,11 +14690,11 @@ design: (work@int_execute_stage) |vpiActual: \_logic_var: (work@int_execute_stage.lane_alu_gen[0].reciprocal_estimate), line:114:24, endln:114:43 |vpiInstance: - \_module: work@int_execute_stage.lane_alu_gen[0]::reciprocal_rom (work@int_execute_stage.lane_alu_gen[0].rom), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:214:13, endln:216:39 + \_module_inst: work@int_execute_stage.lane_alu_gen[0]::reciprocal_rom (work@int_execute_stage.lane_alu_gen[0].rom), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:214:13, endln:216:39 |vpiGenScopeArray: \_gen_scope_array: (work@int_execute_stage.lane_alu_gen[1]), line:100:9, endln:274:12 |vpiParent: - \_module: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 + \_module_inst: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 |vpiName:lane_alu_gen[1] |vpiFullName:work@int_execute_stage.lane_alu_gen[1] |vpiGenScope: @@ -20056,8 +20056,8 @@ design: (work@int_execute_stage) \_parameter: (work@int_execute_stage.lane_alu_gen[1].lane), line:99:0 |vpiActual: \_logic_var: (work@int_execute_stage.vector_result), line:90:14, endln:90:27 - |vpiModule: - \_module: work@int_execute_stage.lane_alu_gen[1]::reciprocal_rom (work@int_execute_stage.lane_alu_gen[1].rom), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:214:13, endln:216:39 + |vpiModuleInst: + \_module_inst: work@int_execute_stage.lane_alu_gen[1]::reciprocal_rom (work@int_execute_stage.lane_alu_gen[1].rom), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:214:13, endln:216:39 |vpiParent: \_gen_scope: (work@int_execute_stage.lane_alu_gen[1]) |vpiName:rom @@ -20066,7 +20066,7 @@ design: (work@int_execute_stage) |vpiPort: \_port: (significand), line:215:18, endln:215:29 |vpiParent: - \_module: work@int_execute_stage.lane_alu_gen[1]::reciprocal_rom (work@int_execute_stage.lane_alu_gen[1].rom), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:214:13, endln:216:39 + \_module_inst: work@int_execute_stage.lane_alu_gen[1]::reciprocal_rom (work@int_execute_stage.lane_alu_gen[1].rom), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:214:13, endln:216:39 |vpiName:significand |vpiHighConn: \_hier_path: (fp_operand.significand[22:17]), line:215:30, endln:215:59 @@ -20108,11 +20108,11 @@ design: (work@int_execute_stage) |vpiExpr: \_struct_net: (work@int_execute_stage.lane_alu_gen[1].fp_operand), line:113:23, endln:113:33 |vpiInstance: - \_module: work@int_execute_stage.lane_alu_gen[1]::reciprocal_rom (work@int_execute_stage.lane_alu_gen[1].rom), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:214:13, endln:216:39 + \_module_inst: work@int_execute_stage.lane_alu_gen[1]::reciprocal_rom (work@int_execute_stage.lane_alu_gen[1].rom), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:214:13, endln:216:39 |vpiPort: \_port: (reciprocal_estimate), line:216:18, endln:216:37 |vpiParent: - \_module: work@int_execute_stage.lane_alu_gen[1]::reciprocal_rom (work@int_execute_stage.lane_alu_gen[1].rom), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:214:13, endln:216:39 + \_module_inst: work@int_execute_stage.lane_alu_gen[1]::reciprocal_rom (work@int_execute_stage.lane_alu_gen[1].rom), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:214:13, endln:216:39 |vpiName:reciprocal_estimate |vpiHighConn: \_ref_obj: (work@int_execute_stage.lane_alu_gen[1].reciprocal_estimate), line:216:18, endln:216:37 @@ -20123,11 +20123,11 @@ design: (work@int_execute_stage) |vpiActual: \_logic_var: (work@int_execute_stage.lane_alu_gen[1].reciprocal_estimate), line:114:24, endln:114:43 |vpiInstance: - \_module: work@int_execute_stage.lane_alu_gen[1]::reciprocal_rom (work@int_execute_stage.lane_alu_gen[1].rom), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:214:13, endln:216:39 + \_module_inst: work@int_execute_stage.lane_alu_gen[1]::reciprocal_rom (work@int_execute_stage.lane_alu_gen[1].rom), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:214:13, endln:216:39 |vpiContAssign: \_cont_assign: , line:277:12, endln:279:57 |vpiParent: - \_module: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 + \_module_inst: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 |vpiRhs: \_operation: , line:277:32, endln:279:57 |vpiParent: @@ -20228,7 +20228,7 @@ design: (work@int_execute_stage) |vpiContAssign: \_cont_assign: , line:280:12, endln:282:53 |vpiParent: - \_module: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 + \_module_inst: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 |vpiRhs: \_operation: , line:280:19, endln:282:53 |vpiParent: @@ -20309,7 +20309,7 @@ design: (work@int_execute_stage) |vpiContAssign: \_cont_assign: , line:283:12, endln:283:74 |vpiParent: - \_module: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 + \_module_inst: work@int_execute_stage (work@int_execute_stage), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:53:1, endln:374:10 |vpiRhs: \_operation: , line:283:34, endln:283:74 |vpiParent: diff --git a/tests/HierMultiSelect/HierMultiSelect.log b/tests/HierMultiSelect/HierMultiSelect.log index f39eb0dc95..a93c4b57e0 100644 --- a/tests/HierMultiSelect/HierMultiSelect.log +++ b/tests/HierMultiSelect/HierMultiSelect.log @@ -241,7 +241,7 @@ logic_net 3 logic_typespec 1 logic_var 1 method_func_call 1 -module 3 +module_inst 3 operation 6 ref_obj 20 === UHDM Object Stats End === @@ -260,7 +260,7 @@ logic_net 3 logic_typespec 1 logic_var 1 method_func_call 1 -module 3 +module_inst 3 operation 11 ref_obj 34 === UHDM Object Stats End === @@ -287,7 +287,7 @@ design: (work@dm_csrs) |vpiElaborated:1 |vpiName:work@dm_csrs |uhdmallModules: -\_module: work@dm_csrs (work@dm_csrs), file:${SURELOG_DIR}/tests/HierMultiSelect/dut.sv, line:1:1, endln:8:10 +\_module_inst: work@dm_csrs (work@dm_csrs), file:${SURELOG_DIR}/tests/HierMultiSelect/dut.sv, line:1:1, endln:8:10 |vpiParent: \_design: (work@dm_csrs) |vpiFullName:work@dm_csrs @@ -295,20 +295,20 @@ design: (work@dm_csrs) |vpiNet: \_logic_net: (work@dm_csrs.c), line:6:9, endln:6:10 |vpiParent: - \_module: work@dm_csrs (work@dm_csrs), file:${SURELOG_DIR}/tests/HierMultiSelect/dut.sv, line:1:1, endln:8:10 + \_module_inst: work@dm_csrs (work@dm_csrs), file:${SURELOG_DIR}/tests/HierMultiSelect/dut.sv, line:1:1, endln:8:10 |vpiName:c |vpiFullName:work@dm_csrs.c |vpiNetType:36 |vpiNet: \_logic_net: (work@dm_csrs.o), line:7:8, endln:7:9 |vpiParent: - \_module: work@dm_csrs (work@dm_csrs), file:${SURELOG_DIR}/tests/HierMultiSelect/dut.sv, line:1:1, endln:8:10 + \_module_inst: work@dm_csrs (work@dm_csrs), file:${SURELOG_DIR}/tests/HierMultiSelect/dut.sv, line:1:1, endln:8:10 |vpiName:o |vpiFullName:work@dm_csrs.o |vpiContAssign: \_cont_assign: , line:2:10, endln:2:43 |vpiParent: - \_module: work@dm_csrs (work@dm_csrs), file:${SURELOG_DIR}/tests/HierMultiSelect/dut.sv, line:1:1, endln:8:10 + \_module_inst: work@dm_csrs (work@dm_csrs), file:${SURELOG_DIR}/tests/HierMultiSelect/dut.sv, line:1:1, endln:8:10 |vpiRhs: \_hier_path: (dmi_req_i.addr2), line:2:28, endln:2:43 |vpiParent: @@ -338,7 +338,7 @@ design: (work@dm_csrs) |vpiContAssign: \_cont_assign: , line:3:10, endln:3:58 |vpiParent: - \_module: work@dm_csrs (work@dm_csrs), file:${SURELOG_DIR}/tests/HierMultiSelect/dut.sv, line:1:1, endln:8:10 + \_module_inst: work@dm_csrs (work@dm_csrs), file:${SURELOG_DIR}/tests/HierMultiSelect/dut.sv, line:1:1, endln:8:10 |vpiRhs: \_operation: , line:3:32, endln:3:58 |vpiParent: @@ -416,7 +416,7 @@ design: (work@dm_csrs) |vpiContAssign: \_cont_assign: , line:4:10, endln:4:47 |vpiParent: - \_module: work@dm_csrs (work@dm_csrs), file:${SURELOG_DIR}/tests/HierMultiSelect/dut.sv, line:1:1, endln:8:10 + \_module_inst: work@dm_csrs (work@dm_csrs), file:${SURELOG_DIR}/tests/HierMultiSelect/dut.sv, line:1:1, endln:8:10 |vpiRhs: \_hier_path: (keymgr_key_i.key[0][+:32]), line:4:14, endln:4:47 |vpiParent: @@ -482,7 +482,7 @@ design: (work@dm_csrs) |vpiContAssign: \_cont_assign: , line:5:10, endln:5:39 |vpiParent: - \_module: work@dm_csrs (work@dm_csrs), file:${SURELOG_DIR}/tests/HierMultiSelect/dut.sv, line:1:1, endln:8:10 + \_module_inst: work@dm_csrs (work@dm_csrs), file:${SURELOG_DIR}/tests/HierMultiSelect/dut.sv, line:1:1, endln:8:10 |vpiRhs: \_constant: , line:5:38, endln:5:39 |vpiParent: @@ -530,12 +530,12 @@ design: (work@dm_csrs) \_hier_path: (sram_otp_key_o[...].nonce), line:5:10, endln:5:24 |vpiName:nonce |uhdmtopModules: -\_module: work@dm_csrs (work@dm_csrs), file:${SURELOG_DIR}/tests/HierMultiSelect/dut.sv, line:1:1, endln:8:10 +\_module_inst: work@dm_csrs (work@dm_csrs), file:${SURELOG_DIR}/tests/HierMultiSelect/dut.sv, line:1:1, endln:8:10 |vpiName:work@dm_csrs |vpiVariables: \_logic_var: (work@dm_csrs.c), line:6:9, endln:6:32 |vpiParent: - \_module: work@dm_csrs (work@dm_csrs), file:${SURELOG_DIR}/tests/HierMultiSelect/dut.sv, line:1:1, endln:8:10 + \_module_inst: work@dm_csrs (work@dm_csrs), file:${SURELOG_DIR}/tests/HierMultiSelect/dut.sv, line:1:1, endln:8:10 |vpiTypespec: \_logic_typespec: , line:6:3, endln:6:8 |vpiName:c @@ -580,7 +580,7 @@ design: (work@dm_csrs) |vpiVariables: \_byte_var: (work@dm_csrs.o), line:7:8, endln:7:17 |vpiParent: - \_module: work@dm_csrs (work@dm_csrs), file:${SURELOG_DIR}/tests/HierMultiSelect/dut.sv, line:1:1, endln:8:10 + \_module_inst: work@dm_csrs (work@dm_csrs), file:${SURELOG_DIR}/tests/HierMultiSelect/dut.sv, line:1:1, endln:8:10 |vpiTypespec: \_byte_typespec: , line:7:3, endln:7:7 |vpiSigned:1 @@ -606,7 +606,7 @@ design: (work@dm_csrs) |vpiContAssign: \_cont_assign: , line:2:10, endln:2:43 |vpiParent: - \_module: work@dm_csrs (work@dm_csrs), file:${SURELOG_DIR}/tests/HierMultiSelect/dut.sv, line:1:1, endln:8:10 + \_module_inst: work@dm_csrs (work@dm_csrs), file:${SURELOG_DIR}/tests/HierMultiSelect/dut.sv, line:1:1, endln:8:10 |vpiRhs: \_hier_path: (dmi_req_i.addr2), line:2:28, endln:2:43 |vpiParent: @@ -640,7 +640,7 @@ design: (work@dm_csrs) |vpiContAssign: \_cont_assign: , line:3:10, endln:3:58 |vpiParent: - \_module: work@dm_csrs (work@dm_csrs), file:${SURELOG_DIR}/tests/HierMultiSelect/dut.sv, line:1:1, endln:8:10 + \_module_inst: work@dm_csrs (work@dm_csrs), file:${SURELOG_DIR}/tests/HierMultiSelect/dut.sv, line:1:1, endln:8:10 |vpiRhs: \_operation: , line:3:32, endln:3:58 |vpiParent: @@ -711,7 +711,7 @@ design: (work@dm_csrs) |vpiContAssign: \_cont_assign: , line:4:10, endln:4:47 |vpiParent: - \_module: work@dm_csrs (work@dm_csrs), file:${SURELOG_DIR}/tests/HierMultiSelect/dut.sv, line:1:1, endln:8:10 + \_module_inst: work@dm_csrs (work@dm_csrs), file:${SURELOG_DIR}/tests/HierMultiSelect/dut.sv, line:1:1, endln:8:10 |vpiRhs: \_hier_path: (keymgr_key_i.key[0][+:32]), line:4:14, endln:4:47 |vpiParent: @@ -759,7 +759,7 @@ design: (work@dm_csrs) |vpiContAssign: \_cont_assign: , line:5:10, endln:5:39 |vpiParent: - \_module: work@dm_csrs (work@dm_csrs), file:${SURELOG_DIR}/tests/HierMultiSelect/dut.sv, line:1:1, endln:8:10 + \_module_inst: work@dm_csrs (work@dm_csrs), file:${SURELOG_DIR}/tests/HierMultiSelect/dut.sv, line:1:1, endln:8:10 |vpiRhs: \_constant: , line:5:38, endln:5:39 |vpiLhs: diff --git a/tests/HierPathBeginBlock/HierPathBeginBlock.log b/tests/HierPathBeginBlock/HierPathBeginBlock.log index 1d98b1b50c..0d2718d524 100644 --- a/tests/HierPathBeginBlock/HierPathBeginBlock.log +++ b/tests/HierPathBeginBlock/HierPathBeginBlock.log @@ -326,7 +326,7 @@ initial 1 logic_net 10 logic_typespec 10 logic_var 2 -module 5 +module_inst 5 named_begin 2 port 8 range 10 @@ -348,7 +348,7 @@ initial 2 logic_net 10 logic_typespec 10 logic_var 4 -module 5 +module_inst 5 named_begin 4 port 12 range 10 @@ -367,7 +367,7 @@ design: (work@matching_end_labels_top) |vpiElaborated:1 |vpiName:work@matching_end_labels_top |uhdmallModules: -\_module: work@matching_end_labels_top (work@matching_end_labels_top), file:${SURELOG_DIR}/tests/HierPathBeginBlock/dut.sv, line:1:1, endln:33:10 +\_module_inst: work@matching_end_labels_top (work@matching_end_labels_top), file:${SURELOG_DIR}/tests/HierPathBeginBlock/dut.sv, line:1:1, endln:33:10 |vpiParent: \_design: (work@matching_end_labels_top) |vpiFullName:work@matching_end_labels_top @@ -375,35 +375,35 @@ design: (work@matching_end_labels_top) |vpiNet: \_logic_net: (work@matching_end_labels_top.out1), line:3:5, endln:3:9 |vpiParent: - \_module: work@matching_end_labels_top (work@matching_end_labels_top), file:${SURELOG_DIR}/tests/HierPathBeginBlock/dut.sv, line:1:1, endln:33:10 + \_module_inst: work@matching_end_labels_top (work@matching_end_labels_top), file:${SURELOG_DIR}/tests/HierPathBeginBlock/dut.sv, line:1:1, endln:33:10 |vpiName:out1 |vpiFullName:work@matching_end_labels_top.out1 |vpiNetType:48 |vpiNet: \_logic_net: (work@matching_end_labels_top.out2), line:3:11, endln:3:15 |vpiParent: - \_module: work@matching_end_labels_top (work@matching_end_labels_top), file:${SURELOG_DIR}/tests/HierPathBeginBlock/dut.sv, line:1:1, endln:33:10 + \_module_inst: work@matching_end_labels_top (work@matching_end_labels_top), file:${SURELOG_DIR}/tests/HierPathBeginBlock/dut.sv, line:1:1, endln:33:10 |vpiName:out2 |vpiFullName:work@matching_end_labels_top.out2 |vpiNetType:48 |vpiNet: \_logic_net: (work@matching_end_labels_top.out3), line:3:17, endln:3:21 |vpiParent: - \_module: work@matching_end_labels_top (work@matching_end_labels_top), file:${SURELOG_DIR}/tests/HierPathBeginBlock/dut.sv, line:1:1, endln:33:10 + \_module_inst: work@matching_end_labels_top (work@matching_end_labels_top), file:${SURELOG_DIR}/tests/HierPathBeginBlock/dut.sv, line:1:1, endln:33:10 |vpiName:out3 |vpiFullName:work@matching_end_labels_top.out3 |vpiNetType:48 |vpiNet: \_logic_net: (work@matching_end_labels_top.out4), line:3:23, endln:3:27 |vpiParent: - \_module: work@matching_end_labels_top (work@matching_end_labels_top), file:${SURELOG_DIR}/tests/HierPathBeginBlock/dut.sv, line:1:1, endln:33:10 + \_module_inst: work@matching_end_labels_top (work@matching_end_labels_top), file:${SURELOG_DIR}/tests/HierPathBeginBlock/dut.sv, line:1:1, endln:33:10 |vpiName:out4 |vpiFullName:work@matching_end_labels_top.out4 |vpiNetType:48 |vpiPort: \_port: (out1), line:3:5, endln:3:9 |vpiParent: - \_module: work@matching_end_labels_top (work@matching_end_labels_top), file:${SURELOG_DIR}/tests/HierPathBeginBlock/dut.sv, line:1:1, endln:33:10 + \_module_inst: work@matching_end_labels_top (work@matching_end_labels_top), file:${SURELOG_DIR}/tests/HierPathBeginBlock/dut.sv, line:1:1, endln:33:10 |vpiName:out1 |vpiDirection:2 |vpiLowConn: @@ -433,7 +433,7 @@ design: (work@matching_end_labels_top) |vpiPort: \_port: (out2), line:3:11, endln:3:15 |vpiParent: - \_module: work@matching_end_labels_top (work@matching_end_labels_top), file:${SURELOG_DIR}/tests/HierPathBeginBlock/dut.sv, line:1:1, endln:33:10 + \_module_inst: work@matching_end_labels_top (work@matching_end_labels_top), file:${SURELOG_DIR}/tests/HierPathBeginBlock/dut.sv, line:1:1, endln:33:10 |vpiName:out2 |vpiDirection:2 |vpiLowConn: @@ -463,7 +463,7 @@ design: (work@matching_end_labels_top) |vpiPort: \_port: (out3), line:3:17, endln:3:21 |vpiParent: - \_module: work@matching_end_labels_top (work@matching_end_labels_top), file:${SURELOG_DIR}/tests/HierPathBeginBlock/dut.sv, line:1:1, endln:33:10 + \_module_inst: work@matching_end_labels_top (work@matching_end_labels_top), file:${SURELOG_DIR}/tests/HierPathBeginBlock/dut.sv, line:1:1, endln:33:10 |vpiName:out3 |vpiDirection:2 |vpiLowConn: @@ -493,7 +493,7 @@ design: (work@matching_end_labels_top) |vpiPort: \_port: (out4), line:3:23, endln:3:27 |vpiParent: - \_module: work@matching_end_labels_top (work@matching_end_labels_top), file:${SURELOG_DIR}/tests/HierPathBeginBlock/dut.sv, line:1:1, endln:33:10 + \_module_inst: work@matching_end_labels_top (work@matching_end_labels_top), file:${SURELOG_DIR}/tests/HierPathBeginBlock/dut.sv, line:1:1, endln:33:10 |vpiName:out4 |vpiDirection:2 |vpiLowConn: @@ -523,7 +523,7 @@ design: (work@matching_end_labels_top) |vpiProcess: \_initial: , line:5:5, endln:18:8 |vpiParent: - \_module: work@matching_end_labels_top (work@matching_end_labels_top), file:${SURELOG_DIR}/tests/HierPathBeginBlock/dut.sv, line:1:1, endln:33:10 + \_module_inst: work@matching_end_labels_top (work@matching_end_labels_top), file:${SURELOG_DIR}/tests/HierPathBeginBlock/dut.sv, line:1:1, endln:33:10 |vpiStmt: \_begin: (work@matching_end_labels_top), line:5:13, endln:18:8 |vpiParent: @@ -660,14 +660,14 @@ design: (work@matching_end_labels_top) |vpiActual: \_logic_net: (work@matching_end_labels_top.out2), line:3:11, endln:3:15 |uhdmtopModules: -\_module: work@matching_end_labels_top (work@matching_end_labels_top), file:${SURELOG_DIR}/tests/HierPathBeginBlock/dut.sv, line:1:1, endln:33:10 +\_module_inst: work@matching_end_labels_top (work@matching_end_labels_top), file:${SURELOG_DIR}/tests/HierPathBeginBlock/dut.sv, line:1:1, endln:33:10 |vpiName:work@matching_end_labels_top |vpiDefName:work@matching_end_labels_top |vpiTop:1 |vpiNet: \_logic_net: (work@matching_end_labels_top.out1), line:3:5, endln:3:9 |vpiParent: - \_module: work@matching_end_labels_top (work@matching_end_labels_top), file:${SURELOG_DIR}/tests/HierPathBeginBlock/dut.sv, line:1:1, endln:33:10 + \_module_inst: work@matching_end_labels_top (work@matching_end_labels_top), file:${SURELOG_DIR}/tests/HierPathBeginBlock/dut.sv, line:1:1, endln:33:10 |vpiTypespec: \_logic_typespec: , line:2:12, endln:2:21 |vpiRange: @@ -694,7 +694,7 @@ design: (work@matching_end_labels_top) |vpiNet: \_logic_net: (work@matching_end_labels_top.out2), line:3:11, endln:3:15 |vpiParent: - \_module: work@matching_end_labels_top (work@matching_end_labels_top), file:${SURELOG_DIR}/tests/HierPathBeginBlock/dut.sv, line:1:1, endln:33:10 + \_module_inst: work@matching_end_labels_top (work@matching_end_labels_top), file:${SURELOG_DIR}/tests/HierPathBeginBlock/dut.sv, line:1:1, endln:33:10 |vpiTypespec: \_logic_typespec: , line:2:12, endln:2:21 |vpiName:out2 @@ -703,7 +703,7 @@ design: (work@matching_end_labels_top) |vpiNet: \_logic_net: (work@matching_end_labels_top.out3), line:3:17, endln:3:21 |vpiParent: - \_module: work@matching_end_labels_top (work@matching_end_labels_top), file:${SURELOG_DIR}/tests/HierPathBeginBlock/dut.sv, line:1:1, endln:33:10 + \_module_inst: work@matching_end_labels_top (work@matching_end_labels_top), file:${SURELOG_DIR}/tests/HierPathBeginBlock/dut.sv, line:1:1, endln:33:10 |vpiTypespec: \_logic_typespec: , line:2:12, endln:2:21 |vpiName:out3 @@ -712,7 +712,7 @@ design: (work@matching_end_labels_top) |vpiNet: \_logic_net: (work@matching_end_labels_top.out4), line:3:23, endln:3:27 |vpiParent: - \_module: work@matching_end_labels_top (work@matching_end_labels_top), file:${SURELOG_DIR}/tests/HierPathBeginBlock/dut.sv, line:1:1, endln:33:10 + \_module_inst: work@matching_end_labels_top (work@matching_end_labels_top), file:${SURELOG_DIR}/tests/HierPathBeginBlock/dut.sv, line:1:1, endln:33:10 |vpiTypespec: \_logic_typespec: , line:2:12, endln:2:21 |vpiName:out4 @@ -722,7 +722,7 @@ design: (work@matching_end_labels_top) |vpiPort: \_port: (out1), line:3:5, endln:3:9 |vpiParent: - \_module: work@matching_end_labels_top (work@matching_end_labels_top), file:${SURELOG_DIR}/tests/HierPathBeginBlock/dut.sv, line:1:1, endln:33:10 + \_module_inst: work@matching_end_labels_top (work@matching_end_labels_top), file:${SURELOG_DIR}/tests/HierPathBeginBlock/dut.sv, line:1:1, endln:33:10 |vpiName:out1 |vpiDirection:2 |vpiLowConn: @@ -756,11 +756,11 @@ design: (work@matching_end_labels_top) |UINT:0 |vpiConstType:9 |vpiInstance: - \_module: work@matching_end_labels_top (work@matching_end_labels_top), file:${SURELOG_DIR}/tests/HierPathBeginBlock/dut.sv, line:1:1, endln:33:10 + \_module_inst: work@matching_end_labels_top (work@matching_end_labels_top), file:${SURELOG_DIR}/tests/HierPathBeginBlock/dut.sv, line:1:1, endln:33:10 |vpiPort: \_port: (out2), line:3:11, endln:3:15 |vpiParent: - \_module: work@matching_end_labels_top (work@matching_end_labels_top), file:${SURELOG_DIR}/tests/HierPathBeginBlock/dut.sv, line:1:1, endln:33:10 + \_module_inst: work@matching_end_labels_top (work@matching_end_labels_top), file:${SURELOG_DIR}/tests/HierPathBeginBlock/dut.sv, line:1:1, endln:33:10 |vpiName:out2 |vpiDirection:2 |vpiLowConn: @@ -774,11 +774,11 @@ design: (work@matching_end_labels_top) |vpiTypedef: \_logic_typespec: , line:2:12, endln:2:21 |vpiInstance: - \_module: work@matching_end_labels_top (work@matching_end_labels_top), file:${SURELOG_DIR}/tests/HierPathBeginBlock/dut.sv, line:1:1, endln:33:10 + \_module_inst: work@matching_end_labels_top (work@matching_end_labels_top), file:${SURELOG_DIR}/tests/HierPathBeginBlock/dut.sv, line:1:1, endln:33:10 |vpiPort: \_port: (out3), line:3:17, endln:3:21 |vpiParent: - \_module: work@matching_end_labels_top (work@matching_end_labels_top), file:${SURELOG_DIR}/tests/HierPathBeginBlock/dut.sv, line:1:1, endln:33:10 + \_module_inst: work@matching_end_labels_top (work@matching_end_labels_top), file:${SURELOG_DIR}/tests/HierPathBeginBlock/dut.sv, line:1:1, endln:33:10 |vpiName:out3 |vpiDirection:2 |vpiLowConn: @@ -792,11 +792,11 @@ design: (work@matching_end_labels_top) |vpiTypedef: \_logic_typespec: , line:2:12, endln:2:21 |vpiInstance: - \_module: work@matching_end_labels_top (work@matching_end_labels_top), file:${SURELOG_DIR}/tests/HierPathBeginBlock/dut.sv, line:1:1, endln:33:10 + \_module_inst: work@matching_end_labels_top (work@matching_end_labels_top), file:${SURELOG_DIR}/tests/HierPathBeginBlock/dut.sv, line:1:1, endln:33:10 |vpiPort: \_port: (out4), line:3:23, endln:3:27 |vpiParent: - \_module: work@matching_end_labels_top (work@matching_end_labels_top), file:${SURELOG_DIR}/tests/HierPathBeginBlock/dut.sv, line:1:1, endln:33:10 + \_module_inst: work@matching_end_labels_top (work@matching_end_labels_top), file:${SURELOG_DIR}/tests/HierPathBeginBlock/dut.sv, line:1:1, endln:33:10 |vpiName:out4 |vpiDirection:2 |vpiLowConn: @@ -810,11 +810,11 @@ design: (work@matching_end_labels_top) |vpiTypedef: \_logic_typespec: , line:2:12, endln:2:21 |vpiInstance: - \_module: work@matching_end_labels_top (work@matching_end_labels_top), file:${SURELOG_DIR}/tests/HierPathBeginBlock/dut.sv, line:1:1, endln:33:10 + \_module_inst: work@matching_end_labels_top (work@matching_end_labels_top), file:${SURELOG_DIR}/tests/HierPathBeginBlock/dut.sv, line:1:1, endln:33:10 |vpiProcess: \_initial: , line:5:5, endln:18:8 |vpiParent: - \_module: work@matching_end_labels_top (work@matching_end_labels_top), file:${SURELOG_DIR}/tests/HierPathBeginBlock/dut.sv, line:1:1, endln:33:10 + \_module_inst: work@matching_end_labels_top (work@matching_end_labels_top), file:${SURELOG_DIR}/tests/HierPathBeginBlock/dut.sv, line:1:1, endln:33:10 |vpiStmt: \_begin: (work@matching_end_labels_top), line:5:13, endln:18:8 |vpiParent: @@ -949,7 +949,7 @@ design: (work@matching_end_labels_top) |vpiGenScopeArray: \_gen_scope_array: (work@matching_end_labels_top.genblk2), line:20:5, endln:31:8 |vpiParent: - \_module: work@matching_end_labels_top (work@matching_end_labels_top), file:${SURELOG_DIR}/tests/HierPathBeginBlock/dut.sv, line:1:1, endln:33:10 + \_module_inst: work@matching_end_labels_top (work@matching_end_labels_top), file:${SURELOG_DIR}/tests/HierPathBeginBlock/dut.sv, line:1:1, endln:33:10 |vpiName:genblk2 |vpiFullName:work@matching_end_labels_top.genblk2 |vpiGenScope: diff --git a/tests/HierPathBind/HierPathBind.log b/tests/HierPathBind/HierPathBind.log index 9a72a386a4..8811a6d2a9 100644 --- a/tests/HierPathBind/HierPathBind.log +++ b/tests/HierPathBind/HierPathBind.log @@ -146,7 +146,7 @@ design 1 hier_path 2 logic_net 5 logic_typespec 7 -module 6 +module_inst 6 port 4 ref_obj 11 struct_net 1 @@ -162,7 +162,7 @@ design 1 hier_path 4 logic_net 5 logic_typespec 7 -module 6 +module_inst 6 port 6 ref_obj 19 struct_net 1 @@ -182,7 +182,7 @@ design: (work@top) |vpiElaborated:1 |vpiName:work@top |uhdmallModules: -\_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/HierPathBind/dut.sv, line:1:1, endln:3:10 +\_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/HierPathBind/dut.sv, line:1:1, endln:3:10 |vpiParent: \_design: (work@top) |vpiFullName:work@dut @@ -190,14 +190,14 @@ design: (work@top) |vpiNet: \_logic_net: (work@dut.o), line:1:26, endln:1:27 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/HierPathBind/dut.sv, line:1:1, endln:3:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/HierPathBind/dut.sv, line:1:1, endln:3:10 |vpiName:o |vpiFullName:work@dut.o |vpiNetType:36 |vpiPort: \_port: (o), line:1:26, endln:1:27 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/HierPathBind/dut.sv, line:1:1, endln:3:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/HierPathBind/dut.sv, line:1:1, endln:3:10 |vpiName:o |vpiDirection:2 |vpiLowConn: @@ -209,7 +209,7 @@ design: (work@top) |vpiContAssign: \_cont_assign: , line:2:11, endln:2:19 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/HierPathBind/dut.sv, line:1:1, endln:3:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/HierPathBind/dut.sv, line:1:1, endln:3:10 |vpiRhs: \_constant: , line:2:15, endln:2:19 |vpiParent: @@ -227,17 +227,17 @@ design: (work@top) |vpiActual: \_logic_net: (work@top.d.o), line:1:26, endln:1:27 |uhdmallModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/HierPathBind/dut.sv, line:5:1, endln:15:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/HierPathBind/dut.sv, line:5:1, endln:15:10 |vpiParent: \_design: (work@top) |vpiFullName:work@top |vpiTypedef: \_struct_typespec: (alert_rx_t), line:6:12, endln:6:18 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/HierPathBind/dut.sv, line:5:1, endln:15:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/HierPathBind/dut.sv, line:5:1, endln:15:10 |vpiName:alert_rx_t |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/HierPathBind/dut.sv, line:5:1, endln:15:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/HierPathBind/dut.sv, line:5:1, endln:15:10 |vpiPacked:1 |vpiTypespecMember: \_typespec_member: (ping_p), line:7:16, endln:7:22 @@ -257,20 +257,20 @@ design: (work@top) |vpiNet: \_logic_net: (work@top.o), line:5:26, endln:5:27 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/HierPathBind/dut.sv, line:5:1, endln:15:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/HierPathBind/dut.sv, line:5:1, endln:15:10 |vpiName:o |vpiFullName:work@top.o |vpiNetType:36 |vpiNet: \_logic_net: (work@top.alert_rx_i), line:10:16, endln:10:26 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/HierPathBind/dut.sv, line:5:1, endln:15:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/HierPathBind/dut.sv, line:5:1, endln:15:10 |vpiName:alert_rx_i |vpiFullName:work@top.alert_rx_i |vpiPort: \_port: (o), line:5:26, endln:5:27 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/HierPathBind/dut.sv, line:5:1, endln:15:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/HierPathBind/dut.sv, line:5:1, endln:15:10 |vpiName:o |vpiDirection:2 |vpiLowConn: @@ -282,7 +282,7 @@ design: (work@top) |vpiContAssign: \_cont_assign: , line:14:11, endln:14:32 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/HierPathBind/dut.sv, line:5:1, endln:15:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/HierPathBind/dut.sv, line:5:1, endln:15:10 |vpiRhs: \_hier_path: (alert_rx_i.ping_p), line:14:15, endln:14:32 |vpiParent: @@ -305,7 +305,7 @@ design: (work@top) |vpiActual: \_logic_net: (work@top.o), line:5:26, endln:5:27 |uhdmtopModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/HierPathBind/dut.sv, line:5:1, endln:15:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/HierPathBind/dut.sv, line:5:1, endln:15:10 |vpiName:work@top |vpiTypedef: \_struct_typespec: (alert_rx_t), line:6:12, endln:6:18 @@ -314,7 +314,7 @@ design: (work@top) |vpiNet: \_logic_net: (work@top.o), line:5:26, endln:5:27 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/HierPathBind/dut.sv, line:5:1, endln:15:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/HierPathBind/dut.sv, line:5:1, endln:15:10 |vpiTypespec: \_logic_typespec: , line:5:20, endln:5:25 |vpiName:o @@ -323,7 +323,7 @@ design: (work@top) |vpiNet: \_struct_net: (work@top.alert_rx_i), line:10:16, endln:10:26 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/HierPathBind/dut.sv, line:5:1, endln:15:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/HierPathBind/dut.sv, line:5:1, endln:15:10 |vpiTypespec: \_struct_typespec: (alert_rx_t), line:6:12, endln:6:18 |vpiName:alert_rx_i @@ -332,7 +332,7 @@ design: (work@top) |vpiPort: \_port: (o), line:5:26, endln:5:27 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/HierPathBind/dut.sv, line:5:1, endln:15:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/HierPathBind/dut.sv, line:5:1, endln:15:10 |vpiName:o |vpiDirection:2 |vpiLowConn: @@ -346,11 +346,11 @@ design: (work@top) |vpiTypedef: \_logic_typespec: , line:5:20, endln:5:25 |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/HierPathBind/dut.sv, line:5:1, endln:15:10 - |vpiModule: - \_module: work@dut (work@top.d), file:${SURELOG_DIR}/tests/HierPathBind/dut.sv, line:12:4, endln:12:33 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/HierPathBind/dut.sv, line:5:1, endln:15:10 + |vpiModuleInst: + \_module_inst: work@dut (work@top.d), file:${SURELOG_DIR}/tests/HierPathBind/dut.sv, line:12:4, endln:12:33 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/HierPathBind/dut.sv, line:5:1, endln:15:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/HierPathBind/dut.sv, line:5:1, endln:15:10 |vpiName:d |vpiFullName:work@top.d |vpiDefName:work@dut @@ -359,18 +359,18 @@ design: (work@top) |vpiNet: \_logic_net: (work@top.d.o), line:1:26, endln:1:27 |vpiParent: - \_module: work@dut (work@top.d), file:${SURELOG_DIR}/tests/HierPathBind/dut.sv, line:12:4, endln:12:33 + \_module_inst: work@dut (work@top.d), file:${SURELOG_DIR}/tests/HierPathBind/dut.sv, line:12:4, endln:12:33 |vpiTypespec: \_logic_typespec: , line:1:20, endln:1:25 |vpiName:o |vpiFullName:work@top.d.o |vpiNetType:36 |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/HierPathBind/dut.sv, line:5:1, endln:15:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/HierPathBind/dut.sv, line:5:1, endln:15:10 |vpiPort: \_port: (o), line:1:26, endln:1:27 |vpiParent: - \_module: work@dut (work@top.d), file:${SURELOG_DIR}/tests/HierPathBind/dut.sv, line:12:4, endln:12:33 + \_module_inst: work@dut (work@top.d), file:${SURELOG_DIR}/tests/HierPathBind/dut.sv, line:12:4, endln:12:33 |vpiName:o |vpiDirection:2 |vpiHighConn: @@ -409,11 +409,11 @@ design: (work@top) |vpiTypedef: \_logic_typespec: , line:1:20, endln:1:25 |vpiInstance: - \_module: work@dut (work@top.d), file:${SURELOG_DIR}/tests/HierPathBind/dut.sv, line:12:4, endln:12:33 + \_module_inst: work@dut (work@top.d), file:${SURELOG_DIR}/tests/HierPathBind/dut.sv, line:12:4, endln:12:33 |vpiContAssign: \_cont_assign: , line:2:11, endln:2:19 |vpiParent: - \_module: work@dut (work@top.d), file:${SURELOG_DIR}/tests/HierPathBind/dut.sv, line:12:4, endln:12:33 + \_module_inst: work@dut (work@top.d), file:${SURELOG_DIR}/tests/HierPathBind/dut.sv, line:12:4, endln:12:33 |vpiRhs: \_constant: , line:2:15, endln:2:19 |vpiLhs: @@ -427,7 +427,7 @@ design: (work@top) |vpiContAssign: \_cont_assign: , line:14:11, endln:14:32 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/HierPathBind/dut.sv, line:5:1, endln:15:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/HierPathBind/dut.sv, line:5:1, endln:15:10 |vpiRhs: \_hier_path: (alert_rx_i.ping_p), line:14:15, endln:14:32 |vpiParent: diff --git a/tests/HierPathEval/HierPathEval.log b/tests/HierPathEval/HierPathEval.log index 139f0ad3b3..825e4d19ac 100644 --- a/tests/HierPathEval/HierPathEval.log +++ b/tests/HierPathEval/HierPathEval.log @@ -322,7 +322,7 @@ gen_scope_array 4 hier_path 1 import_typespec 5 logic_typespec 8 -module 16 +module_inst 16 operation 1 package 6 param_assign 6 @@ -343,7 +343,7 @@ gen_scope_array 8 hier_path 1 import_typespec 5 logic_typespec 8 -module 20 +module_inst 20 operation 1 package 6 param_assign 7 @@ -397,7 +397,7 @@ design: (work@top) |vpiTypedef: \_enum_typespec: (prim_pad_wrapper_pkg::pad_type_e), line:2:4, endln:4:17 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/HierPathEval/dut.sv, line:46:1, endln:55:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/HierPathEval/dut.sv, line:46:1, endln:55:10 |vpiName:prim_pad_wrapper_pkg::pad_type_e |vpiInstance: \_package: pinmux_pkg (pinmux_pkg::), file:${SURELOG_DIR}/tests/HierPathEval/dut.sv, line:7:1, endln:13:24 @@ -471,7 +471,7 @@ design: (work@top) |vpiTypedef: \_struct_typespec: (pinmux_pkg::target_cfg_t), line:9:12, endln:9:18 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/HierPathEval/dut.sv, line:46:1, endln:55:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/HierPathEval/dut.sv, line:46:1, endln:55:10 |vpiName:pinmux_pkg::target_cfg_t |vpiInstance: \_package: pinmux_pkg (pinmux_pkg::), file:${SURELOG_DIR}/tests/HierPathEval/dut.sv, line:7:1, endln:13:24 @@ -509,20 +509,20 @@ design: (work@top) |vpiDefName:pinmux_pkg |vpiTop:1 |uhdmallModules: -\_module: work@GOOD (work@GOOD), file:${SURELOG_DIR}/tests/HierPathEval/dut.sv, line:16:1, endln:17:10 +\_module_inst: work@GOOD (work@GOOD), file:${SURELOG_DIR}/tests/HierPathEval/dut.sv, line:16:1, endln:17:10 |vpiParent: \_design: (work@top) |vpiFullName:work@GOOD |vpiDefName:work@GOOD |uhdmallModules: -\_module: work@prim_generic_pad_attr (work@prim_generic_pad_attr), file:${SURELOG_DIR}/tests/HierPathEval/dut.sv, line:19:1, endln:30:34 +\_module_inst: work@prim_generic_pad_attr (work@prim_generic_pad_attr), file:${SURELOG_DIR}/tests/HierPathEval/dut.sv, line:19:1, endln:30:34 |vpiParent: \_design: (work@top) |vpiFullName:work@prim_generic_pad_attr |vpiParameter: \_parameter: (work@prim_generic_pad_attr.PadTypeInGeneric), line:21:25, endln:21:41 |vpiParent: - \_module: work@prim_generic_pad_attr (work@prim_generic_pad_attr), file:${SURELOG_DIR}/tests/HierPathEval/dut.sv, line:19:1, endln:30:34 + \_module_inst: work@prim_generic_pad_attr (work@prim_generic_pad_attr), file:${SURELOG_DIR}/tests/HierPathEval/dut.sv, line:19:1, endln:30:34 |UINT:0 |vpiTypespec: \_enum_typespec: (prim_pad_wrapper_pkg::pad_type_e), line:2:4, endln:4:17 @@ -531,7 +531,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:21:25, endln:21:45 |vpiParent: - \_module: work@prim_generic_pad_attr (work@prim_generic_pad_attr), file:${SURELOG_DIR}/tests/HierPathEval/dut.sv, line:19:1, endln:30:34 + \_module_inst: work@prim_generic_pad_attr (work@prim_generic_pad_attr), file:${SURELOG_DIR}/tests/HierPathEval/dut.sv, line:19:1, endln:30:34 |vpiRhs: \_constant: , line:21:44, endln:21:45 |vpiDecompile:0 @@ -548,14 +548,14 @@ design: (work@top) \_import_typespec: (prim_pad_wrapper_pkg), line:20:11, endln:20:34 |vpiDefName:work@prim_generic_pad_attr |uhdmallModules: -\_module: work@prim_pad_attr (work@prim_pad_attr), file:${SURELOG_DIR}/tests/HierPathEval/dut.sv, line:33:1, endln:44:10 +\_module_inst: work@prim_pad_attr (work@prim_pad_attr), file:${SURELOG_DIR}/tests/HierPathEval/dut.sv, line:33:1, endln:44:10 |vpiParent: \_design: (work@top) |vpiFullName:work@prim_pad_attr |vpiParameter: \_parameter: (work@prim_pad_attr.PadType), line:35:25, endln:35:32 |vpiParent: - \_module: work@prim_pad_attr (work@prim_pad_attr), file:${SURELOG_DIR}/tests/HierPathEval/dut.sv, line:33:1, endln:44:10 + \_module_inst: work@prim_pad_attr (work@prim_pad_attr), file:${SURELOG_DIR}/tests/HierPathEval/dut.sv, line:33:1, endln:44:10 |UINT:0 |vpiTypespec: \_enum_typespec: (prim_pad_wrapper_pkg::pad_type_e), line:2:4, endln:4:17 @@ -564,7 +564,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:35:25, endln:35:36 |vpiParent: - \_module: work@prim_pad_attr (work@prim_pad_attr), file:${SURELOG_DIR}/tests/HierPathEval/dut.sv, line:33:1, endln:44:10 + \_module_inst: work@prim_pad_attr (work@prim_pad_attr), file:${SURELOG_DIR}/tests/HierPathEval/dut.sv, line:33:1, endln:44:10 |vpiRhs: \_constant: , line:35:35, endln:35:36 |vpiDecompile:0 @@ -581,14 +581,14 @@ design: (work@top) \_import_typespec: (prim_pad_wrapper_pkg), line:34:11, endln:34:34 |vpiDefName:work@prim_pad_attr |uhdmallModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/HierPathEval/dut.sv, line:46:1, endln:55:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/HierPathEval/dut.sv, line:46:1, endln:55:10 |vpiParent: \_design: (work@top) |vpiFullName:work@top |vpiParameter: \_parameter: (work@top.TargetCfg), line:48:27, endln:48:36 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/HierPathEval/dut.sv, line:46:1, endln:55:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/HierPathEval/dut.sv, line:46:1, endln:55:10 |UINT:2 |vpiTypespec: \_struct_typespec: (pinmux_pkg::target_cfg_t), line:9:12, endln:9:18 @@ -597,7 +597,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:48:27, endln:48:40 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/HierPathEval/dut.sv, line:46:1, endln:55:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/HierPathEval/dut.sv, line:46:1, endln:55:10 |vpiRhs: \_constant: , line:48:39, endln:48:40 |vpiDecompile:2 @@ -616,12 +616,12 @@ design: (work@top) \_import_typespec: (pinmux_pkg), line:47:11, endln:47:24 |vpiDefName:work@top |uhdmtopModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/HierPathEval/dut.sv, line:46:1, endln:55:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/HierPathEval/dut.sv, line:46:1, endln:55:10 |vpiName:work@top |vpiParameter: \_parameter: (work@top.TargetCfg), line:48:27, endln:48:36 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/HierPathEval/dut.sv, line:46:1, endln:55:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/HierPathEval/dut.sv, line:46:1, endln:55:10 |UINT:2 |vpiTypespec: \_struct_typespec: (pinmux_pkg::target_cfg_t), line:9:12, endln:9:18 @@ -683,7 +683,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:48:27, endln:48:40 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/HierPathEval/dut.sv, line:46:1, endln:55:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/HierPathEval/dut.sv, line:46:1, endln:55:10 |vpiRhs: \_constant: , line:48:39, endln:48:40 |vpiDecompile:2 @@ -701,16 +701,16 @@ design: (work@top) |vpiDefName:work@top |vpiTop:1 |vpiTopModule:1 - |vpiModule: - \_module: work@prim_pad_attr (work@top.u_prim_pad_attr), file:${SURELOG_DIR}/tests/HierPathEval/dut.sv, line:50:4, endln:54:6 + |vpiModuleInst: + \_module_inst: work@prim_pad_attr (work@top.u_prim_pad_attr), file:${SURELOG_DIR}/tests/HierPathEval/dut.sv, line:50:4, endln:54:6 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/HierPathEval/dut.sv, line:46:1, endln:55:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/HierPathEval/dut.sv, line:46:1, endln:55:10 |vpiName:u_prim_pad_attr |vpiFullName:work@top.u_prim_pad_attr |vpiParameter: \_parameter: (work@top.u_prim_pad_attr.PadType), line:35:25, endln:35:32 |vpiParent: - \_module: work@prim_pad_attr (work@top.u_prim_pad_attr), file:${SURELOG_DIR}/tests/HierPathEval/dut.sv, line:50:4, endln:54:6 + \_module_inst: work@prim_pad_attr (work@top.u_prim_pad_attr), file:${SURELOG_DIR}/tests/HierPathEval/dut.sv, line:50:4, endln:54:6 |UINT:0 |vpiTypespec: \_enum_typespec: (prim_pad_wrapper_pkg::pad_type_e), line:2:4, endln:4:17 @@ -738,7 +738,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:35:25, endln:35:36 |vpiParent: - \_module: work@prim_pad_attr (work@top.u_prim_pad_attr), file:${SURELOG_DIR}/tests/HierPathEval/dut.sv, line:50:4, endln:54:6 + \_module_inst: work@prim_pad_attr (work@top.u_prim_pad_attr), file:${SURELOG_DIR}/tests/HierPathEval/dut.sv, line:50:4, endln:54:6 |vpiOverriden:1 |vpiRhs: \_constant: , line:35:35, endln:35:36 @@ -758,11 +758,11 @@ design: (work@top) |vpiDefFile:${SURELOG_DIR}/tests/HierPathEval/dut.sv |vpiDefLineNo:33 |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/HierPathEval/dut.sv, line:46:1, endln:55:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/HierPathEval/dut.sv, line:46:1, endln:55:10 |vpiGenScopeArray: \_gen_scope_array: (work@top.u_prim_pad_attr.gen_outer_if), line:37:4, endln:43:7 |vpiParent: - \_module: work@prim_pad_attr (work@top.u_prim_pad_attr), file:${SURELOG_DIR}/tests/HierPathEval/dut.sv, line:50:4, endln:54:6 + \_module_inst: work@prim_pad_attr (work@top.u_prim_pad_attr), file:${SURELOG_DIR}/tests/HierPathEval/dut.sv, line:50:4, endln:54:6 |vpiName:gen_outer_if |vpiFullName:work@top.u_prim_pad_attr.gen_outer_if |vpiGenScope: @@ -770,8 +770,8 @@ design: (work@top) |vpiParent: \_gen_scope_array: (work@top.u_prim_pad_attr.gen_outer_if), line:37:4, endln:43:7 |vpiFullName:work@top.u_prim_pad_attr.gen_outer_if - |vpiModule: - \_module: work@prim_generic_pad_attr (work@top.u_prim_pad_attr.gen_outer_if.u_impl_generic), file:${SURELOG_DIR}/tests/HierPathEval/dut.sv, line:38:8, endln:42:10 + |vpiModuleInst: + \_module_inst: work@prim_generic_pad_attr (work@top.u_prim_pad_attr.gen_outer_if.u_impl_generic), file:${SURELOG_DIR}/tests/HierPathEval/dut.sv, line:38:8, endln:42:10 |vpiParent: \_gen_scope: (work@top.u_prim_pad_attr.gen_outer_if) |vpiName:u_impl_generic @@ -807,7 +807,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:21:25, endln:21:45 |vpiParent: - \_module: work@prim_generic_pad_attr (work@top.u_prim_pad_attr.gen_outer_if.u_impl_generic), file:${SURELOG_DIR}/tests/HierPathEval/dut.sv, line:38:8, endln:42:10 + \_module_inst: work@prim_generic_pad_attr (work@top.u_prim_pad_attr.gen_outer_if.u_impl_generic), file:${SURELOG_DIR}/tests/HierPathEval/dut.sv, line:38:8, endln:42:10 |vpiOverriden:1 |vpiRhs: \_constant: , line:21:44, endln:21:45 @@ -829,7 +829,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.u_prim_pad_attr.gen_outer_if.u_impl_generic.gen_inner_if_true), line:22:4, endln:29:9 |vpiParent: - \_module: work@prim_generic_pad_attr (work@top.u_prim_pad_attr.gen_outer_if.u_impl_generic), file:${SURELOG_DIR}/tests/HierPathEval/dut.sv, line:38:8, endln:42:10 + \_module_inst: work@prim_generic_pad_attr (work@top.u_prim_pad_attr.gen_outer_if.u_impl_generic), file:${SURELOG_DIR}/tests/HierPathEval/dut.sv, line:38:8, endln:42:10 |vpiName:gen_inner_if_true |vpiFullName:work@top.u_prim_pad_attr.gen_outer_if.u_impl_generic.gen_inner_if_true |vpiGenScope: @@ -837,8 +837,8 @@ design: (work@top) |vpiParent: \_gen_scope_array: (work@top.u_prim_pad_attr.gen_outer_if.u_impl_generic.gen_inner_if_true), line:22:4, endln:29:9 |vpiFullName:work@top.u_prim_pad_attr.gen_outer_if.u_impl_generic.gen_inner_if_true - |vpiModule: - \_module: work@GOOD (work@top.u_prim_pad_attr.gen_outer_if.u_impl_generic.gen_inner_if_true.good), file:${SURELOG_DIR}/tests/HierPathEval/dut.sv, line:24:9, endln:24:21 + |vpiModuleInst: + \_module_inst: work@GOOD (work@top.u_prim_pad_attr.gen_outer_if.u_impl_generic.gen_inner_if_true.good), file:${SURELOG_DIR}/tests/HierPathEval/dut.sv, line:24:9, endln:24:21 |vpiParent: \_gen_scope: (work@top.u_prim_pad_attr.gen_outer_if.u_impl_generic.gen_inner_if_true) |vpiName:good diff --git a/tests/HierPathLhs/HierPathLhs.log b/tests/HierPathLhs/HierPathLhs.log index 19175447f1..c132abd36a 100644 --- a/tests/HierPathLhs/HierPathLhs.log +++ b/tests/HierPathLhs/HierPathLhs.log @@ -185,7 +185,7 @@ gen_scope_array 2 hier_path 5 int_typespec 2 logic_net 1 -module 7 +module_inst 7 operation 2 packed_array_typespec 1 packed_array_var 1 @@ -208,7 +208,7 @@ gen_scope_array 3 hier_path 7 int_typespec 2 logic_net 1 -module 7 +module_inst 7 operation 2 packed_array_typespec 1 packed_array_var 1 @@ -234,23 +234,23 @@ design: (work@alert_handler_reg_wrap) |vpiElaborated:1 |vpiName:work@alert_handler_reg_wrap |uhdmallModules: -\_module: work@alert_handler_reg_wrap (work@alert_handler_reg_wrap), file:${SURELOG_DIR}/tests/HierPathLhs/dut.sv, line:1:1, endln:5:10 +\_module_inst: work@alert_handler_reg_wrap (work@alert_handler_reg_wrap), file:${SURELOG_DIR}/tests/HierPathLhs/dut.sv, line:1:1, endln:5:10 |vpiParent: \_design: (work@alert_handler_reg_wrap) |vpiFullName:work@alert_handler_reg_wrap |vpiDefName:work@alert_handler_reg_wrap |uhdmallModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/HierPathLhs/dut.sv, line:8:1, endln:16:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/HierPathLhs/dut.sv, line:8:1, endln:16:10 |vpiParent: \_design: (work@alert_handler_reg_wrap) |vpiFullName:work@top |vpiTypedef: \_struct_typespec: (struct_t), line:9:11, endln:9:17 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/HierPathLhs/dut.sv, line:8:1, endln:16:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/HierPathLhs/dut.sv, line:8:1, endln:16:10 |vpiName:struct_t |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/HierPathLhs/dut.sv, line:8:1, endln:16:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/HierPathLhs/dut.sv, line:8:1, endln:16:10 |vpiPacked:1 |vpiTypespecMember: \_typespec_member: (x), line:10:9, endln:10:10 @@ -271,13 +271,13 @@ design: (work@alert_handler_reg_wrap) |vpiNet: \_logic_net: (work@top.a), line:13:23, endln:13:24 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/HierPathLhs/dut.sv, line:8:1, endln:16:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/HierPathLhs/dut.sv, line:8:1, endln:16:10 |vpiName:a |vpiFullName:work@top.a |vpiContAssign: \_cont_assign: , line:15:10, endln:15:26 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/HierPathLhs/dut.sv, line:8:1, endln:16:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/HierPathLhs/dut.sv, line:8:1, endln:16:10 |vpiRhs: \_constant: , line:15:25, endln:15:26 |vpiParent: @@ -332,7 +332,7 @@ design: (work@alert_handler_reg_wrap) |UINT:0 |vpiConstType:9 |uhdmtopModules: -\_module: work@alert_handler_reg_wrap (work@alert_handler_reg_wrap), file:${SURELOG_DIR}/tests/HierPathLhs/dut.sv, line:1:1, endln:5:10 +\_module_inst: work@alert_handler_reg_wrap (work@alert_handler_reg_wrap), file:${SURELOG_DIR}/tests/HierPathLhs/dut.sv, line:1:1, endln:5:10 |vpiName:work@alert_handler_reg_wrap |vpiDefName:work@alert_handler_reg_wrap |vpiTop:1 @@ -340,7 +340,7 @@ design: (work@alert_handler_reg_wrap) |vpiGenScopeArray: \_gen_scope_array: (work@alert_handler_reg_wrap.gen_alert_cause[0]), line:2:34, endln:4:6 |vpiParent: - \_module: work@alert_handler_reg_wrap (work@alert_handler_reg_wrap), file:${SURELOG_DIR}/tests/HierPathLhs/dut.sv, line:1:1, endln:5:10 + \_module_inst: work@alert_handler_reg_wrap (work@alert_handler_reg_wrap), file:${SURELOG_DIR}/tests/HierPathLhs/dut.sv, line:1:1, endln:5:10 |vpiName:gen_alert_cause[0] |vpiFullName:work@alert_handler_reg_wrap.gen_alert_cause[0] |vpiGenScope: @@ -403,12 +403,12 @@ design: (work@alert_handler_reg_wrap) \_hier_path: (hw2reg.alert_cause[k].d), line:3:12, endln:3:35 |vpiName:d |uhdmtopModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/HierPathLhs/dut.sv, line:8:1, endln:16:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/HierPathLhs/dut.sv, line:8:1, endln:16:10 |vpiName:work@top |vpiVariables: \_packed_array_var: (work@top.a), line:13:23, endln:13:24 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/HierPathLhs/dut.sv, line:8:1, endln:16:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/HierPathLhs/dut.sv, line:8:1, endln:16:10 |vpiName:a |vpiFullName:work@top.a |vpiVisibility:1 @@ -463,7 +463,7 @@ design: (work@alert_handler_reg_wrap) |vpiContAssign: \_cont_assign: , line:15:10, endln:15:26 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/HierPathLhs/dut.sv, line:8:1, endln:16:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/HierPathLhs/dut.sv, line:8:1, endln:16:10 |vpiRhs: \_constant: , line:15:25, endln:15:26 |vpiLhs: diff --git a/tests/HierPathOverride/HierPathOverride.log b/tests/HierPathOverride/HierPathOverride.log index e5c24e8cba..35a0295cfc 100644 --- a/tests/HierPathOverride/HierPathOverride.log +++ b/tests/HierPathOverride/HierPathOverride.log @@ -390,7 +390,7 @@ hier_path 1 import_typespec 5 int_typespec 43 logic_typespec 15 -module 15 +module_inst 15 operation 28 package 6 packed_array_typespec 13 @@ -418,7 +418,7 @@ hier_path 1 import_typespec 5 int_typespec 43 logic_typespec 15 -module 16 +module_inst 16 operation 28 package 6 packed_array_typespec 13 @@ -608,7 +608,7 @@ design: (work@top) |vpiElemTypespec: \_enum_typespec: (prim_pad_wrapper_pkg::pad_type_e), line:4:4, endln:7:17 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/HierPathOverride/dut.sv, line:44:1, endln:50:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/HierPathOverride/dut.sv, line:44:1, endln:50:10 |vpiName:prim_pad_wrapper_pkg::pad_type_e |vpiInstance: \_package: pinmux_pkg (pinmux_pkg::), file:${SURELOG_DIR}/tests/HierPathOverride/dut.sv, line:10:1, endln:20:24 @@ -786,7 +786,7 @@ design: (work@top) |vpiTypespec: \_struct_typespec: (pinmux_pkg::target_cfg_t), line:13:12, endln:13:18 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/HierPathOverride/dut.sv, line:44:1, endln:50:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/HierPathOverride/dut.sv, line:44:1, endln:50:10 |vpiName:pinmux_pkg::target_cfg_t |vpiInstance: \_package: pinmux_pkg (pinmux_pkg::), file:${SURELOG_DIR}/tests/HierPathOverride/dut.sv, line:10:1, endln:20:24 @@ -898,14 +898,14 @@ design: (work@top) |vpiDefName:pinmux_pkg |vpiTop:1 |uhdmallModules: -\_module: work@prim_generic_pad_attr (work@prim_generic_pad_attr), file:${SURELOG_DIR}/tests/HierPathOverride/dut.sv, line:23:1, endln:29:34 +\_module_inst: work@prim_generic_pad_attr (work@prim_generic_pad_attr), file:${SURELOG_DIR}/tests/HierPathOverride/dut.sv, line:23:1, endln:29:34 |vpiParent: \_design: (work@top) |vpiFullName:work@prim_generic_pad_attr |vpiParameter: \_parameter: (work@prim_generic_pad_attr.NDioPads), line:2:18, endln:2:26 |vpiParent: - \_module: work@prim_generic_pad_attr (work@prim_generic_pad_attr), file:${SURELOG_DIR}/tests/HierPathOverride/dut.sv, line:23:1, endln:29:34 + \_module_inst: work@prim_generic_pad_attr (work@prim_generic_pad_attr), file:${SURELOG_DIR}/tests/HierPathOverride/dut.sv, line:23:1, endln:29:34 |UINT:24 |vpiTypespec: \_int_typespec: , line:2:14, endln:2:17 @@ -921,7 +921,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@prim_generic_pad_attr.PadType), line:25:25, endln:25:32 |vpiParent: - \_module: work@prim_generic_pad_attr (work@prim_generic_pad_attr), file:${SURELOG_DIR}/tests/HierPathOverride/dut.sv, line:23:1, endln:29:34 + \_module_inst: work@prim_generic_pad_attr (work@prim_generic_pad_attr), file:${SURELOG_DIR}/tests/HierPathOverride/dut.sv, line:23:1, endln:29:34 |vpiTypespec: \_enum_typespec: (prim_pad_wrapper_pkg::pad_type_e), line:4:4, endln:7:17 |vpiName:PadType @@ -929,7 +929,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:2:18, endln:2:31 |vpiParent: - \_module: work@prim_generic_pad_attr (work@prim_generic_pad_attr), file:${SURELOG_DIR}/tests/HierPathOverride/dut.sv, line:23:1, endln:29:34 + \_module_inst: work@prim_generic_pad_attr (work@prim_generic_pad_attr), file:${SURELOG_DIR}/tests/HierPathOverride/dut.sv, line:23:1, endln:29:34 |vpiRhs: \_constant: , line:2:29, endln:2:31 |vpiParent: @@ -964,7 +964,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:25:25, endln:25:36 |vpiParent: - \_module: work@prim_generic_pad_attr (work@prim_generic_pad_attr), file:${SURELOG_DIR}/tests/HierPathOverride/dut.sv, line:23:1, endln:29:34 + \_module_inst: work@prim_generic_pad_attr (work@prim_generic_pad_attr), file:${SURELOG_DIR}/tests/HierPathOverride/dut.sv, line:23:1, endln:29:34 |vpiRhs: \_ref_obj: (A), line:25:35, endln:25:36 |vpiName:A @@ -978,14 +978,14 @@ design: (work@top) \_import_typespec: (prim_pad_wrapper_pkg), line:24:11, endln:24:34 |vpiDefName:work@prim_generic_pad_attr |uhdmallModules: -\_module: work@prim_pad_attr (work@prim_pad_attr), file:${SURELOG_DIR}/tests/HierPathOverride/dut.sv, line:32:1, endln:42:10 +\_module_inst: work@prim_pad_attr (work@prim_pad_attr), file:${SURELOG_DIR}/tests/HierPathOverride/dut.sv, line:32:1, endln:42:10 |vpiParent: \_design: (work@top) |vpiFullName:work@prim_pad_attr |vpiParameter: \_parameter: (work@prim_pad_attr.NDioPads), line:2:18, endln:2:26 |vpiParent: - \_module: work@prim_pad_attr (work@prim_pad_attr), file:${SURELOG_DIR}/tests/HierPathOverride/dut.sv, line:32:1, endln:42:10 + \_module_inst: work@prim_pad_attr (work@prim_pad_attr), file:${SURELOG_DIR}/tests/HierPathOverride/dut.sv, line:32:1, endln:42:10 |UINT:24 |vpiTypespec: \_int_typespec: , line:2:14, endln:2:17 @@ -1001,7 +1001,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@prim_pad_attr.PadType), line:34:25, endln:34:32 |vpiParent: - \_module: work@prim_pad_attr (work@prim_pad_attr), file:${SURELOG_DIR}/tests/HierPathOverride/dut.sv, line:32:1, endln:42:10 + \_module_inst: work@prim_pad_attr (work@prim_pad_attr), file:${SURELOG_DIR}/tests/HierPathOverride/dut.sv, line:32:1, endln:42:10 |vpiTypespec: \_enum_typespec: (prim_pad_wrapper_pkg::pad_type_e), line:4:4, endln:7:17 |vpiName:PadType @@ -1009,7 +1009,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:2:18, endln:2:31 |vpiParent: - \_module: work@prim_pad_attr (work@prim_pad_attr), file:${SURELOG_DIR}/tests/HierPathOverride/dut.sv, line:32:1, endln:42:10 + \_module_inst: work@prim_pad_attr (work@prim_pad_attr), file:${SURELOG_DIR}/tests/HierPathOverride/dut.sv, line:32:1, endln:42:10 |vpiRhs: \_constant: , line:2:29, endln:2:31 |vpiParent: @@ -1044,7 +1044,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:34:25, endln:34:36 |vpiParent: - \_module: work@prim_pad_attr (work@prim_pad_attr), file:${SURELOG_DIR}/tests/HierPathOverride/dut.sv, line:32:1, endln:42:10 + \_module_inst: work@prim_pad_attr (work@prim_pad_attr), file:${SURELOG_DIR}/tests/HierPathOverride/dut.sv, line:32:1, endln:42:10 |vpiRhs: \_ref_obj: (A), line:34:35, endln:34:36 |vpiName:A @@ -1058,14 +1058,14 @@ design: (work@top) \_import_typespec: (prim_pad_wrapper_pkg), line:33:11, endln:33:34 |vpiDefName:work@prim_pad_attr |uhdmallModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/HierPathOverride/dut.sv, line:44:1, endln:50:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/HierPathOverride/dut.sv, line:44:1, endln:50:10 |vpiParent: \_design: (work@top) |vpiFullName:work@top |vpiParameter: \_parameter: (work@top.DefaultTargetCfg), line:17:27, endln:17:43 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/HierPathOverride/dut.sv, line:44:1, endln:50:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/HierPathOverride/dut.sv, line:44:1, endln:50:10 |vpiTypespec: \_struct_typespec: (pinmux_pkg::target_cfg_t), line:13:12, endln:13:18 |vpiParent: @@ -1165,7 +1165,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.NDioPads), line:2:18, endln:2:26 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/HierPathOverride/dut.sv, line:44:1, endln:50:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/HierPathOverride/dut.sv, line:44:1, endln:50:10 |UINT:24 |vpiTypespec: \_int_typespec: , line:2:14, endln:2:17 @@ -1181,7 +1181,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.TargetCfg), line:46:27, endln:46:36 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/HierPathOverride/dut.sv, line:44:1, endln:50:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/HierPathOverride/dut.sv, line:44:1, endln:50:10 |vpiTypespec: \_struct_typespec: (pinmux_pkg::target_cfg_t), line:13:12, endln:13:18 |vpiName:TargetCfg @@ -1189,7 +1189,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:2:18, endln:2:31 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/HierPathOverride/dut.sv, line:44:1, endln:50:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/HierPathOverride/dut.sv, line:44:1, endln:50:10 |vpiRhs: \_constant: , line:2:29, endln:2:31 |vpiParent: @@ -1224,7 +1224,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:17:27, endln:19:5 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/HierPathOverride/dut.sv, line:44:1, endln:50:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/HierPathOverride/dut.sv, line:44:1, endln:50:10 |vpiRhs: \_operation: , line:17:46, endln:19:5 |vpiParent: @@ -1355,7 +1355,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:46:27, endln:46:55 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/HierPathOverride/dut.sv, line:44:1, endln:50:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/HierPathOverride/dut.sv, line:44:1, endln:50:10 |vpiRhs: \_ref_obj: (DefaultTargetCfg), line:46:39, endln:46:55 |vpiName:DefaultTargetCfg @@ -1369,12 +1369,12 @@ design: (work@top) \_import_typespec: (pinmux_pkg), line:45:11, endln:45:24 |vpiDefName:work@top |uhdmtopModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/HierPathOverride/dut.sv, line:44:1, endln:50:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/HierPathOverride/dut.sv, line:44:1, endln:50:10 |vpiName:work@top |vpiParameter: \_parameter: (work@top.DefaultTargetCfg), line:17:27, endln:17:43 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/HierPathOverride/dut.sv, line:44:1, endln:50:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/HierPathOverride/dut.sv, line:44:1, endln:50:10 |vpiTypespec: \_struct_typespec: (pinmux_pkg::target_cfg_t), line:13:12, endln:13:18 |vpiParent: @@ -1474,7 +1474,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.NDioPads), line:2:18, endln:2:26 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/HierPathOverride/dut.sv, line:44:1, endln:50:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/HierPathOverride/dut.sv, line:44:1, endln:50:10 |UINT:24 |vpiTypespec: \_int_typespec: , line:2:14, endln:2:17 @@ -1490,7 +1490,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.TargetCfg), line:46:27, endln:46:36 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/HierPathOverride/dut.sv, line:44:1, endln:50:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/HierPathOverride/dut.sv, line:44:1, endln:50:10 |vpiTypespec: \_struct_typespec: (pinmux_pkg::target_cfg_t), line:13:12, endln:13:18 |vpiParent: @@ -1589,7 +1589,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:2:18, endln:2:31 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/HierPathOverride/dut.sv, line:44:1, endln:50:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/HierPathOverride/dut.sv, line:44:1, endln:50:10 |vpiRhs: \_constant: , line:2:29, endln:2:31 |vpiDecompile:24 @@ -1603,7 +1603,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:17:27, endln:19:5 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/HierPathOverride/dut.sv, line:44:1, endln:50:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/HierPathOverride/dut.sv, line:44:1, endln:50:10 |vpiRhs: \_operation: , line:17:46, endln:19:5 |vpiParent: @@ -1720,7 +1720,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:46:27, endln:46:55 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/HierPathOverride/dut.sv, line:44:1, endln:50:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/HierPathOverride/dut.sv, line:44:1, endln:50:10 |vpiRhs: \_ref_obj: (DefaultTargetCfg), line:46:39, endln:46:55 |vpiName:DefaultTargetCfg @@ -1737,16 +1737,16 @@ design: (work@top) |vpiDefName:work@top |vpiTop:1 |vpiTopModule:1 - |vpiModule: - \_module: work@prim_pad_attr (work@top.u_prim_pad_attr), file:${SURELOG_DIR}/tests/HierPathOverride/dut.sv, line:47:5, endln:49:25 + |vpiModuleInst: + \_module_inst: work@prim_pad_attr (work@top.u_prim_pad_attr), file:${SURELOG_DIR}/tests/HierPathOverride/dut.sv, line:47:5, endln:49:25 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/HierPathOverride/dut.sv, line:44:1, endln:50:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/HierPathOverride/dut.sv, line:44:1, endln:50:10 |vpiName:u_prim_pad_attr |vpiFullName:work@top.u_prim_pad_attr |vpiParameter: \_parameter: (work@top.u_prim_pad_attr.NDioPads), line:2:18, endln:2:26 |vpiParent: - \_module: work@prim_pad_attr (work@top.u_prim_pad_attr), file:${SURELOG_DIR}/tests/HierPathOverride/dut.sv, line:47:5, endln:49:25 + \_module_inst: work@prim_pad_attr (work@top.u_prim_pad_attr), file:${SURELOG_DIR}/tests/HierPathOverride/dut.sv, line:47:5, endln:49:25 |UINT:24 |vpiTypespec: \_int_typespec: , line:2:14, endln:2:17 @@ -1762,7 +1762,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.u_prim_pad_attr.PadType), line:34:25, endln:34:32 |vpiParent: - \_module: work@prim_pad_attr (work@top.u_prim_pad_attr), file:${SURELOG_DIR}/tests/HierPathOverride/dut.sv, line:47:5, endln:49:25 + \_module_inst: work@prim_pad_attr (work@top.u_prim_pad_attr), file:${SURELOG_DIR}/tests/HierPathOverride/dut.sv, line:47:5, endln:49:25 |vpiTypespec: \_enum_typespec: (prim_pad_wrapper_pkg::pad_type_e), line:4:4, endln:7:17 |vpiParent: @@ -1817,7 +1817,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:2:18, endln:2:31 |vpiParent: - \_module: work@prim_pad_attr (work@top.u_prim_pad_attr), file:${SURELOG_DIR}/tests/HierPathOverride/dut.sv, line:47:5, endln:49:25 + \_module_inst: work@prim_pad_attr (work@top.u_prim_pad_attr), file:${SURELOG_DIR}/tests/HierPathOverride/dut.sv, line:47:5, endln:49:25 |vpiRhs: \_constant: , line:2:29, endln:2:31 |vpiDecompile:24 @@ -1831,7 +1831,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:34:25, endln:34:36 |vpiParent: - \_module: work@prim_pad_attr (work@top.u_prim_pad_attr), file:${SURELOG_DIR}/tests/HierPathOverride/dut.sv, line:47:5, endln:49:25 + \_module_inst: work@prim_pad_attr (work@top.u_prim_pad_attr), file:${SURELOG_DIR}/tests/HierPathOverride/dut.sv, line:47:5, endln:49:25 |vpiOverriden:1 |vpiRhs: \_constant: , line:34:35, endln:34:36 @@ -1851,11 +1851,11 @@ design: (work@top) |vpiDefFile:${SURELOG_DIR}/tests/HierPathOverride/dut.sv |vpiDefLineNo:32 |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/HierPathOverride/dut.sv, line:44:1, endln:50:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/HierPathOverride/dut.sv, line:44:1, endln:50:10 |vpiGenScopeArray: \_gen_scope_array: (work@top.u_prim_pad_attr.gen_generic), line:36:4, endln:40:7 |vpiParent: - \_module: work@prim_pad_attr (work@top.u_prim_pad_attr), file:${SURELOG_DIR}/tests/HierPathOverride/dut.sv, line:47:5, endln:49:25 + \_module_inst: work@prim_pad_attr (work@top.u_prim_pad_attr), file:${SURELOG_DIR}/tests/HierPathOverride/dut.sv, line:47:5, endln:49:25 |vpiName:gen_generic |vpiFullName:work@top.u_prim_pad_attr.gen_generic |vpiGenScope: @@ -1863,8 +1863,8 @@ design: (work@top) |vpiParent: \_gen_scope_array: (work@top.u_prim_pad_attr.gen_generic), line:36:4, endln:40:7 |vpiFullName:work@top.u_prim_pad_attr.gen_generic - |vpiModule: - \_module: work@prim_generic_pad_attr (work@top.u_prim_pad_attr.gen_generic.u_impl_generic), file:${SURELOG_DIR}/tests/HierPathOverride/dut.sv, line:37:7, endln:39:26 + |vpiModuleInst: + \_module_inst: work@prim_generic_pad_attr (work@top.u_prim_pad_attr.gen_generic.u_impl_generic), file:${SURELOG_DIR}/tests/HierPathOverride/dut.sv, line:37:7, endln:39:26 |vpiParent: \_gen_scope: (work@top.u_prim_pad_attr.gen_generic) |vpiName:u_impl_generic @@ -1943,7 +1943,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:2:18, endln:2:31 |vpiParent: - \_module: work@prim_generic_pad_attr (work@top.u_prim_pad_attr.gen_generic.u_impl_generic), file:${SURELOG_DIR}/tests/HierPathOverride/dut.sv, line:37:7, endln:39:26 + \_module_inst: work@prim_generic_pad_attr (work@top.u_prim_pad_attr.gen_generic.u_impl_generic), file:${SURELOG_DIR}/tests/HierPathOverride/dut.sv, line:37:7, endln:39:26 |vpiRhs: \_constant: , line:2:29, endln:2:31 |vpiDecompile:24 @@ -1957,7 +1957,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:25:25, endln:25:36 |vpiParent: - \_module: work@prim_generic_pad_attr (work@top.u_prim_pad_attr.gen_generic.u_impl_generic), file:${SURELOG_DIR}/tests/HierPathOverride/dut.sv, line:37:7, endln:39:26 + \_module_inst: work@prim_generic_pad_attr (work@top.u_prim_pad_attr.gen_generic.u_impl_generic), file:${SURELOG_DIR}/tests/HierPathOverride/dut.sv, line:37:7, endln:39:26 |vpiOverriden:1 |vpiRhs: \_constant: , line:25:35, endln:25:36 @@ -1979,7 +1979,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.u_prim_pad_attr.gen_generic.u_impl_generic.gen_assign), line:26:4, endln:28:7 |vpiParent: - \_module: work@prim_generic_pad_attr (work@top.u_prim_pad_attr.gen_generic.u_impl_generic), file:${SURELOG_DIR}/tests/HierPathOverride/dut.sv, line:37:7, endln:39:26 + \_module_inst: work@prim_generic_pad_attr (work@top.u_prim_pad_attr.gen_generic.u_impl_generic), file:${SURELOG_DIR}/tests/HierPathOverride/dut.sv, line:37:7, endln:39:26 |vpiName:gen_assign |vpiFullName:work@top.u_prim_pad_attr.gen_generic.u_impl_generic.gen_assign |vpiGenScope: diff --git a/tests/HierPathPackedArrayNet/HierPathPackedArrayNet.log b/tests/HierPathPackedArrayNet/HierPathPackedArrayNet.log index 8b7847e300..f0840b8158 100644 --- a/tests/HierPathPackedArrayNet/HierPathPackedArrayNet.log +++ b/tests/HierPathPackedArrayNet/HierPathPackedArrayNet.log @@ -238,7 +238,7 @@ int_typespec 8 int_var 1 logic_net 2 logic_typespec 2 -module 7 +module_inst 7 operation 6 package 3 packed_array_net 1 @@ -268,7 +268,7 @@ int_typespec 8 int_var 2 logic_net 2 logic_typespec 2 -module 7 +module_inst 7 operation 9 package 3 packed_array_net 1 @@ -506,14 +506,14 @@ design: (work@rvfi_tracer) |vpiDefName:rvfi_pkg |vpiTop:1 |uhdmallModules: -\_module: work@rvfi_tracer (work@rvfi_tracer), file:${SURELOG_DIR}/tests/HierPathPackedArrayNet/dut.sv, line:11:1, endln:22:10 +\_module_inst: work@rvfi_tracer (work@rvfi_tracer), file:${SURELOG_DIR}/tests/HierPathPackedArrayNet/dut.sv, line:11:1, endln:22:10 |vpiParent: \_design: (work@rvfi_tracer) |vpiFullName:work@rvfi_tracer |vpiParameter: \_parameter: (work@rvfi_tracer.NR_COMMIT_PORTS), line:12:26, endln:12:41 |vpiParent: - \_module: work@rvfi_tracer (work@rvfi_tracer), file:${SURELOG_DIR}/tests/HierPathPackedArrayNet/dut.sv, line:11:1, endln:22:10 + \_module_inst: work@rvfi_tracer (work@rvfi_tracer), file:${SURELOG_DIR}/tests/HierPathPackedArrayNet/dut.sv, line:11:1, endln:22:10 |UINT:2 |vpiTypespec: \_int_typespec: , line:12:13, endln:12:25 @@ -524,7 +524,7 @@ design: (work@rvfi_tracer) |vpiParamAssign: \_param_assign: , line:12:26, endln:12:45 |vpiParent: - \_module: work@rvfi_tracer (work@rvfi_tracer), file:${SURELOG_DIR}/tests/HierPathPackedArrayNet/dut.sv, line:11:1, endln:22:10 + \_module_inst: work@rvfi_tracer (work@rvfi_tracer), file:${SURELOG_DIR}/tests/HierPathPackedArrayNet/dut.sv, line:11:1, endln:22:10 |vpiRhs: \_constant: , line:12:44, endln:12:45 |vpiDecompile:2 @@ -539,14 +539,14 @@ design: (work@rvfi_tracer) |vpiNet: \_logic_net: (work@rvfi_tracer.rvfi_i), line:14:63, endln:14:69 |vpiParent: - \_module: work@rvfi_tracer (work@rvfi_tracer), file:${SURELOG_DIR}/tests/HierPathPackedArrayNet/dut.sv, line:11:1, endln:22:10 + \_module_inst: work@rvfi_tracer (work@rvfi_tracer), file:${SURELOG_DIR}/tests/HierPathPackedArrayNet/dut.sv, line:11:1, endln:22:10 |vpiName:rvfi_i |vpiFullName:work@rvfi_tracer.rvfi_i |vpiNetType:1 |vpiPort: \_port: (rvfi_i), line:14:63, endln:14:69 |vpiParent: - \_module: work@rvfi_tracer (work@rvfi_tracer), file:${SURELOG_DIR}/tests/HierPathPackedArrayNet/dut.sv, line:11:1, endln:22:10 + \_module_inst: work@rvfi_tracer (work@rvfi_tracer), file:${SURELOG_DIR}/tests/HierPathPackedArrayNet/dut.sv, line:11:1, endln:22:10 |vpiName:rvfi_i |vpiDirection:1 |vpiLowConn: @@ -558,7 +558,7 @@ design: (work@rvfi_tracer) |vpiProcess: \_always: , line:16:1, endln:21:4 |vpiParent: - \_module: work@rvfi_tracer (work@rvfi_tracer), file:${SURELOG_DIR}/tests/HierPathPackedArrayNet/dut.sv, line:11:1, endln:22:10 + \_module_inst: work@rvfi_tracer (work@rvfi_tracer), file:${SURELOG_DIR}/tests/HierPathPackedArrayNet/dut.sv, line:11:1, endln:22:10 |vpiStmt: \_event_control: , line:16:11, endln:16:27 |vpiParent: @@ -681,12 +681,12 @@ design: (work@rvfi_tracer) |vpiFullName:work@rvfi_tracer |vpiAlwaysType:3 |uhdmtopModules: -\_module: work@rvfi_tracer (work@rvfi_tracer), file:${SURELOG_DIR}/tests/HierPathPackedArrayNet/dut.sv, line:11:1, endln:22:10 +\_module_inst: work@rvfi_tracer (work@rvfi_tracer), file:${SURELOG_DIR}/tests/HierPathPackedArrayNet/dut.sv, line:11:1, endln:22:10 |vpiName:work@rvfi_tracer |vpiParameter: \_parameter: (work@rvfi_tracer.NR_COMMIT_PORTS), line:12:26, endln:12:41 |vpiParent: - \_module: work@rvfi_tracer (work@rvfi_tracer), file:${SURELOG_DIR}/tests/HierPathPackedArrayNet/dut.sv, line:11:1, endln:22:10 + \_module_inst: work@rvfi_tracer (work@rvfi_tracer), file:${SURELOG_DIR}/tests/HierPathPackedArrayNet/dut.sv, line:11:1, endln:22:10 |UINT:2 |vpiTypespec: \_int_typespec: , line:12:13, endln:12:25 @@ -697,7 +697,7 @@ design: (work@rvfi_tracer) |vpiParamAssign: \_param_assign: , line:12:26, endln:12:45 |vpiParent: - \_module: work@rvfi_tracer (work@rvfi_tracer), file:${SURELOG_DIR}/tests/HierPathPackedArrayNet/dut.sv, line:11:1, endln:22:10 + \_module_inst: work@rvfi_tracer (work@rvfi_tracer), file:${SURELOG_DIR}/tests/HierPathPackedArrayNet/dut.sv, line:11:1, endln:22:10 |vpiRhs: \_constant: , line:12:44, endln:12:45 |vpiDecompile:2 @@ -713,7 +713,7 @@ design: (work@rvfi_tracer) |vpiNet: \_packed_array_net: (work@rvfi_tracer.rvfi_i), line:14:63, endln:14:69 |vpiParent: - \_module: work@rvfi_tracer (work@rvfi_tracer), file:${SURELOG_DIR}/tests/HierPathPackedArrayNet/dut.sv, line:11:1, endln:22:10 + \_module_inst: work@rvfi_tracer (work@rvfi_tracer), file:${SURELOG_DIR}/tests/HierPathPackedArrayNet/dut.sv, line:11:1, endln:22:10 |vpiName:rvfi_i |vpiFullName:work@rvfi_tracer.rvfi_i |vpiNetType:1 @@ -748,7 +748,7 @@ design: (work@rvfi_tracer) |vpiPort: \_port: (rvfi_i), line:14:63, endln:14:69 |vpiParent: - \_module: work@rvfi_tracer (work@rvfi_tracer), file:${SURELOG_DIR}/tests/HierPathPackedArrayNet/dut.sv, line:11:1, endln:22:10 + \_module_inst: work@rvfi_tracer (work@rvfi_tracer), file:${SURELOG_DIR}/tests/HierPathPackedArrayNet/dut.sv, line:11:1, endln:22:10 |vpiName:rvfi_i |vpiDirection:1 |vpiLowConn: @@ -762,11 +762,11 @@ design: (work@rvfi_tracer) |vpiTypedef: \_struct_typespec: (rvfi_pkg::rvfi_instr_t), line:5:9, endln:5:15 |vpiInstance: - \_module: work@rvfi_tracer (work@rvfi_tracer), file:${SURELOG_DIR}/tests/HierPathPackedArrayNet/dut.sv, line:11:1, endln:22:10 + \_module_inst: work@rvfi_tracer (work@rvfi_tracer), file:${SURELOG_DIR}/tests/HierPathPackedArrayNet/dut.sv, line:11:1, endln:22:10 |vpiProcess: \_always: , line:16:1, endln:21:4 |vpiParent: - \_module: work@rvfi_tracer (work@rvfi_tracer), file:${SURELOG_DIR}/tests/HierPathPackedArrayNet/dut.sv, line:11:1, endln:22:10 + \_module_inst: work@rvfi_tracer (work@rvfi_tracer), file:${SURELOG_DIR}/tests/HierPathPackedArrayNet/dut.sv, line:11:1, endln:22:10 |vpiStmt: \_event_control: , line:16:11, endln:16:27 |vpiParent: diff --git a/tests/HierPathPackedVar/HierPathPackedVar.log b/tests/HierPathPackedVar/HierPathPackedVar.log index c475c63d6b..9a2eecd0b9 100644 --- a/tests/HierPathPackedVar/HierPathPackedVar.log +++ b/tests/HierPathPackedVar/HierPathPackedVar.log @@ -297,7 +297,7 @@ if_stmt 1 int_typespec 2 logic_net 5 logic_typespec 15 -module 6 +module_inst 6 operation 5 package 3 packed_array_var 1 @@ -326,7 +326,7 @@ if_stmt 2 int_typespec 2 logic_net 5 logic_typespec 15 -module 6 +module_inst 6 operation 6 package 3 packed_array_var 1 @@ -877,14 +877,14 @@ design: (work@axi_adapter_arbiter) |vpiDefName:std_cache_pkg |vpiTop:1 |uhdmallModules: -\_module: work@axi_adapter_arbiter (work@axi_adapter_arbiter), file:${SURELOG_DIR}/tests/HierPathPackedVar/dut.sv, line:16:1, endln:26:10 +\_module_inst: work@axi_adapter_arbiter (work@axi_adapter_arbiter), file:${SURELOG_DIR}/tests/HierPathPackedVar/dut.sv, line:16:1, endln:26:10 |vpiParent: \_design: (work@axi_adapter_arbiter) |vpiFullName:work@axi_adapter_arbiter |vpiParameter: \_parameter: (work@axi_adapter_arbiter.NR_PORTS), line:17:15, endln:17:23 |vpiParent: - \_module: work@axi_adapter_arbiter (work@axi_adapter_arbiter), file:${SURELOG_DIR}/tests/HierPathPackedVar/dut.sv, line:16:1, endln:26:10 + \_module_inst: work@axi_adapter_arbiter (work@axi_adapter_arbiter), file:${SURELOG_DIR}/tests/HierPathPackedVar/dut.sv, line:16:1, endln:26:10 |UINT:4 |vpiTypespec: \_int_typespec: @@ -893,7 +893,7 @@ design: (work@axi_adapter_arbiter) |vpiParameter: \_type_parameter: (work@axi_adapter_arbiter.req_t), line:18:20, endln:18:25 |vpiParent: - \_module: work@axi_adapter_arbiter (work@axi_adapter_arbiter), file:${SURELOG_DIR}/tests/HierPathPackedVar/dut.sv, line:16:1, endln:26:10 + \_module_inst: work@axi_adapter_arbiter (work@axi_adapter_arbiter), file:${SURELOG_DIR}/tests/HierPathPackedVar/dut.sv, line:16:1, endln:26:10 |vpiName:req_t |vpiFullName:work@axi_adapter_arbiter.req_t |vpiTypespec: @@ -901,7 +901,7 @@ design: (work@axi_adapter_arbiter) |vpiParamAssign: \_param_assign: , line:17:15, endln:17:27 |vpiParent: - \_module: work@axi_adapter_arbiter (work@axi_adapter_arbiter), file:${SURELOG_DIR}/tests/HierPathPackedVar/dut.sv, line:16:1, endln:26:10 + \_module_inst: work@axi_adapter_arbiter (work@axi_adapter_arbiter), file:${SURELOG_DIR}/tests/HierPathPackedVar/dut.sv, line:16:1, endln:26:10 |vpiRhs: \_constant: , line:17:26, endln:17:27 |vpiDecompile:4 @@ -916,20 +916,20 @@ design: (work@axi_adapter_arbiter) |vpiNet: \_logic_net: (work@axi_adapter_arbiter.req_i), line:19:34, endln:19:39 |vpiParent: - \_module: work@axi_adapter_arbiter (work@axi_adapter_arbiter), file:${SURELOG_DIR}/tests/HierPathPackedVar/dut.sv, line:16:1, endln:26:10 + \_module_inst: work@axi_adapter_arbiter (work@axi_adapter_arbiter), file:${SURELOG_DIR}/tests/HierPathPackedVar/dut.sv, line:16:1, endln:26:10 |vpiName:req_i |vpiFullName:work@axi_adapter_arbiter.req_i |vpiNet: \_logic_net: (work@axi_adapter_arbiter.state_d), line:20:9, endln:20:16 |vpiParent: - \_module: work@axi_adapter_arbiter (work@axi_adapter_arbiter), file:${SURELOG_DIR}/tests/HierPathPackedVar/dut.sv, line:16:1, endln:26:10 + \_module_inst: work@axi_adapter_arbiter (work@axi_adapter_arbiter), file:${SURELOG_DIR}/tests/HierPathPackedVar/dut.sv, line:16:1, endln:26:10 |vpiName:state_d |vpiFullName:work@axi_adapter_arbiter.state_d |vpiNetType:48 |vpiPort: \_port: (req_i), line:19:34, endln:19:39 |vpiParent: - \_module: work@axi_adapter_arbiter (work@axi_adapter_arbiter), file:${SURELOG_DIR}/tests/HierPathPackedVar/dut.sv, line:16:1, endln:26:10 + \_module_inst: work@axi_adapter_arbiter (work@axi_adapter_arbiter), file:${SURELOG_DIR}/tests/HierPathPackedVar/dut.sv, line:16:1, endln:26:10 |vpiName:req_i |vpiDirection:1 |vpiLowConn: @@ -941,7 +941,7 @@ design: (work@axi_adapter_arbiter) |vpiProcess: \_always: , line:21:5, endln:25:8 |vpiParent: - \_module: work@axi_adapter_arbiter (work@axi_adapter_arbiter), file:${SURELOG_DIR}/tests/HierPathPackedVar/dut.sv, line:16:1, endln:26:10 + \_module_inst: work@axi_adapter_arbiter (work@axi_adapter_arbiter), file:${SURELOG_DIR}/tests/HierPathPackedVar/dut.sv, line:16:1, endln:26:10 |vpiStmt: \_begin: (work@axi_adapter_arbiter), line:21:17, endln:25:8 |vpiParent: @@ -1018,12 +1018,12 @@ design: (work@axi_adapter_arbiter) \_logic_net: (work@axi_adapter_arbiter.state_d), line:20:9, endln:20:16 |vpiAlwaysType:2 |uhdmtopModules: -\_module: work@axi_adapter_arbiter (work@axi_adapter_arbiter), file:${SURELOG_DIR}/tests/HierPathPackedVar/dut.sv, line:16:1, endln:26:10 +\_module_inst: work@axi_adapter_arbiter (work@axi_adapter_arbiter), file:${SURELOG_DIR}/tests/HierPathPackedVar/dut.sv, line:16:1, endln:26:10 |vpiName:work@axi_adapter_arbiter |vpiVariables: \_packed_array_var: (work@axi_adapter_arbiter.req_i), line:19:34, endln:19:39 |vpiParent: - \_module: work@axi_adapter_arbiter (work@axi_adapter_arbiter), file:${SURELOG_DIR}/tests/HierPathPackedVar/dut.sv, line:16:1, endln:26:10 + \_module_inst: work@axi_adapter_arbiter (work@axi_adapter_arbiter), file:${SURELOG_DIR}/tests/HierPathPackedVar/dut.sv, line:16:1, endln:26:10 |vpiTypespec: \_struct_typespec: (std_cache_pkg::bypass_req_t), line:2:12, endln:2:18 |vpiName:req_i @@ -1054,7 +1054,7 @@ design: (work@axi_adapter_arbiter) |vpiParameter: \_parameter: (work@axi_adapter_arbiter.NR_PORTS), line:17:15, endln:17:23 |vpiParent: - \_module: work@axi_adapter_arbiter (work@axi_adapter_arbiter), file:${SURELOG_DIR}/tests/HierPathPackedVar/dut.sv, line:16:1, endln:26:10 + \_module_inst: work@axi_adapter_arbiter (work@axi_adapter_arbiter), file:${SURELOG_DIR}/tests/HierPathPackedVar/dut.sv, line:16:1, endln:26:10 |UINT:4 |vpiTypespec: \_int_typespec: @@ -1067,7 +1067,7 @@ design: (work@axi_adapter_arbiter) |vpiParamAssign: \_param_assign: , line:17:15, endln:17:27 |vpiParent: - \_module: work@axi_adapter_arbiter (work@axi_adapter_arbiter), file:${SURELOG_DIR}/tests/HierPathPackedVar/dut.sv, line:16:1, endln:26:10 + \_module_inst: work@axi_adapter_arbiter (work@axi_adapter_arbiter), file:${SURELOG_DIR}/tests/HierPathPackedVar/dut.sv, line:16:1, endln:26:10 |vpiRhs: \_constant: , line:17:26, endln:17:27 |vpiDecompile:4 @@ -1083,7 +1083,7 @@ design: (work@axi_adapter_arbiter) |vpiNet: \_logic_net: (work@axi_adapter_arbiter.state_d), line:20:9, endln:20:16 |vpiParent: - \_module: work@axi_adapter_arbiter (work@axi_adapter_arbiter), file:${SURELOG_DIR}/tests/HierPathPackedVar/dut.sv, line:16:1, endln:26:10 + \_module_inst: work@axi_adapter_arbiter (work@axi_adapter_arbiter), file:${SURELOG_DIR}/tests/HierPathPackedVar/dut.sv, line:16:1, endln:26:10 |vpiTypespec: \_logic_typespec: , line:20:5, endln:20:8 |vpiName:state_d @@ -1101,7 +1101,7 @@ design: (work@axi_adapter_arbiter) |vpiPort: \_port: (req_i), line:19:34, endln:19:39 |vpiParent: - \_module: work@axi_adapter_arbiter (work@axi_adapter_arbiter), file:${SURELOG_DIR}/tests/HierPathPackedVar/dut.sv, line:16:1, endln:26:10 + \_module_inst: work@axi_adapter_arbiter (work@axi_adapter_arbiter), file:${SURELOG_DIR}/tests/HierPathPackedVar/dut.sv, line:16:1, endln:26:10 |vpiName:req_i |vpiDirection:1 |vpiLowConn: @@ -1115,11 +1115,11 @@ design: (work@axi_adapter_arbiter) |vpiTypedef: \_struct_typespec: (std_cache_pkg::bypass_req_t), line:2:12, endln:2:18 |vpiInstance: - \_module: work@axi_adapter_arbiter (work@axi_adapter_arbiter), file:${SURELOG_DIR}/tests/HierPathPackedVar/dut.sv, line:16:1, endln:26:10 + \_module_inst: work@axi_adapter_arbiter (work@axi_adapter_arbiter), file:${SURELOG_DIR}/tests/HierPathPackedVar/dut.sv, line:16:1, endln:26:10 |vpiProcess: \_always: , line:21:5, endln:25:8 |vpiParent: - \_module: work@axi_adapter_arbiter (work@axi_adapter_arbiter), file:${SURELOG_DIR}/tests/HierPathPackedVar/dut.sv, line:16:1, endln:26:10 + \_module_inst: work@axi_adapter_arbiter (work@axi_adapter_arbiter), file:${SURELOG_DIR}/tests/HierPathPackedVar/dut.sv, line:16:1, endln:26:10 |vpiStmt: \_begin: (work@axi_adapter_arbiter), line:21:17, endln:25:8 |vpiParent: diff --git a/tests/HierPathSelect/HierPathSelect.log b/tests/HierPathSelect/HierPathSelect.log index ce99f990cb..d5012b3a9a 100644 --- a/tests/HierPathSelect/HierPathSelect.log +++ b/tests/HierPathSelect/HierPathSelect.log @@ -101,7 +101,7 @@ design 1 hier_path 2 logic_net 1 logic_typespec 1 -module 3 +module_inst 3 range 1 ref_obj 4 struct_net 1 @@ -118,7 +118,7 @@ design 1 hier_path 3 logic_net 1 logic_typespec 1 -module 3 +module_inst 3 range 1 ref_obj 6 struct_net 1 @@ -138,17 +138,17 @@ design: (work@dut2) |vpiElaborated:1 |vpiName:work@dut2 |uhdmallModules: -\_module: work@dut2 (work@dut2), file:${SURELOG_DIR}/tests/HierPathSelect/dut.sv, line:1:1, endln:10:10 +\_module_inst: work@dut2 (work@dut2), file:${SURELOG_DIR}/tests/HierPathSelect/dut.sv, line:1:1, endln:10:10 |vpiParent: \_design: (work@dut2) |vpiFullName:work@dut2 |vpiTypedef: \_struct_typespec: (struct_typedef), line:3:9, endln:3:15 |vpiParent: - \_module: work@dut2 (work@dut2), file:${SURELOG_DIR}/tests/HierPathSelect/dut.sv, line:1:1, endln:10:10 + \_module_inst: work@dut2 (work@dut2), file:${SURELOG_DIR}/tests/HierPathSelect/dut.sv, line:1:1, endln:10:10 |vpiName:struct_typedef |vpiInstance: - \_module: work@dut2 (work@dut2), file:${SURELOG_DIR}/tests/HierPathSelect/dut.sv, line:1:1, endln:10:10 + \_module_inst: work@dut2 (work@dut2), file:${SURELOG_DIR}/tests/HierPathSelect/dut.sv, line:1:1, endln:10:10 |vpiPacked:1 |vpiTypespecMember: \_typespec_member: (q), line:4:15, endln:4:16 @@ -188,13 +188,13 @@ design: (work@dut2) |vpiNet: \_logic_net: (work@dut2.read_buf), line:6:16, endln:6:24 |vpiParent: - \_module: work@dut2 (work@dut2), file:${SURELOG_DIR}/tests/HierPathSelect/dut.sv, line:1:1, endln:10:10 + \_module_inst: work@dut2 (work@dut2), file:${SURELOG_DIR}/tests/HierPathSelect/dut.sv, line:1:1, endln:10:10 |vpiName:read_buf |vpiFullName:work@dut2.read_buf |vpiContAssign: \_cont_assign: , line:8:8, endln:8:28 |vpiParent: - \_module: work@dut2 (work@dut2), file:${SURELOG_DIR}/tests/HierPathSelect/dut.sv, line:1:1, endln:10:10 + \_module_inst: work@dut2 (work@dut2), file:${SURELOG_DIR}/tests/HierPathSelect/dut.sv, line:1:1, endln:10:10 |vpiRhs: \_constant: , line:8:24, endln:8:28 |vpiParent: @@ -232,7 +232,7 @@ design: (work@dut2) |UINT:1 |vpiConstType:9 |uhdmtopModules: -\_module: work@dut2 (work@dut2), file:${SURELOG_DIR}/tests/HierPathSelect/dut.sv, line:1:1, endln:10:10 +\_module_inst: work@dut2 (work@dut2), file:${SURELOG_DIR}/tests/HierPathSelect/dut.sv, line:1:1, endln:10:10 |vpiName:work@dut2 |vpiTypedef: \_struct_typespec: (struct_typedef), line:3:9, endln:3:15 @@ -241,7 +241,7 @@ design: (work@dut2) |vpiNet: \_struct_net: (work@dut2.read_buf), line:6:16, endln:6:24 |vpiParent: - \_module: work@dut2 (work@dut2), file:${SURELOG_DIR}/tests/HierPathSelect/dut.sv, line:1:1, endln:10:10 + \_module_inst: work@dut2 (work@dut2), file:${SURELOG_DIR}/tests/HierPathSelect/dut.sv, line:1:1, endln:10:10 |vpiTypespec: \_struct_typespec: (struct_typedef), line:3:9, endln:3:15 |vpiName:read_buf @@ -250,7 +250,7 @@ design: (work@dut2) |vpiContAssign: \_cont_assign: , line:8:8, endln:8:28 |vpiParent: - \_module: work@dut2 (work@dut2), file:${SURELOG_DIR}/tests/HierPathSelect/dut.sv, line:1:1, endln:10:10 + \_module_inst: work@dut2 (work@dut2), file:${SURELOG_DIR}/tests/HierPathSelect/dut.sv, line:1:1, endln:10:10 |vpiRhs: \_constant: , line:8:24, endln:8:28 |vpiLhs: diff --git a/tests/HierPathStruct/HierPathStruct.log b/tests/HierPathStruct/HierPathStruct.log index 452aad2d3a..62cf37bb58 100644 --- a/tests/HierPathStruct/HierPathStruct.log +++ b/tests/HierPathStruct/HierPathStruct.log @@ -136,7 +136,7 @@ hier_path 2 import_typespec 1 logic_net 1 logic_typespec 4 -module 4 +module_inst 4 package 3 range 2 ref_obj 6 @@ -154,7 +154,7 @@ hier_path 3 import_typespec 1 logic_net 1 logic_typespec 4 -module 4 +module_inst 4 package 3 range 2 ref_obj 9 @@ -270,7 +270,7 @@ design: (work@dut) |vpiTypedef: \_struct_typespec: (gpio_reg_pkg::gpio_hw2reg_t), line:7:11, endln:7:17 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/HierPathStruct/dut.sv, line:13:1, endln:19:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/HierPathStruct/dut.sv, line:13:1, endln:19:10 |vpiName:gpio_reg_pkg::gpio_hw2reg_t |vpiInstance: \_package: gpio_reg_pkg (gpio_reg_pkg::), file:${SURELOG_DIR}/tests/HierPathStruct/dut.sv, line:1:1, endln:11:11 @@ -283,7 +283,7 @@ design: (work@dut) |vpiTypespec: \_struct_typespec: (gpio_reg_pkg::gpio_hw2reg_tt), line:2:11, endln:2:17 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/HierPathStruct/dut.sv, line:13:1, endln:19:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/HierPathStruct/dut.sv, line:13:1, endln:19:10 |vpiName:gpio_reg_pkg::gpio_hw2reg_tt |vpiInstance: \_package: gpio_reg_pkg (gpio_reg_pkg::), file:${SURELOG_DIR}/tests/HierPathStruct/dut.sv, line:1:1, endln:11:11 @@ -350,7 +350,7 @@ design: (work@dut) |vpiDefName:gpio_reg_pkg |vpiTop:1 |uhdmallModules: -\_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/HierPathStruct/dut.sv, line:13:1, endln:19:10 +\_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/HierPathStruct/dut.sv, line:13:1, endln:19:10 |vpiParent: \_design: (work@dut) |vpiFullName:work@dut @@ -364,13 +364,13 @@ design: (work@dut) |vpiNet: \_logic_net: (work@dut.hw2reg), line:16:15, endln:16:21 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/HierPathStruct/dut.sv, line:13:1, endln:19:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/HierPathStruct/dut.sv, line:13:1, endln:19:10 |vpiName:hw2reg |vpiFullName:work@dut.hw2reg |vpiContAssign: \_cont_assign: , line:17:8, endln:17:32 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/HierPathStruct/dut.sv, line:13:1, endln:19:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/HierPathStruct/dut.sv, line:13:1, endln:19:10 |vpiRhs: \_constant: , line:17:28, endln:17:32 |vpiParent: @@ -396,7 +396,7 @@ design: (work@dut) \_ref_obj: (de) |vpiName:de |uhdmtopModules: -\_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/HierPathStruct/dut.sv, line:13:1, endln:19:10 +\_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/HierPathStruct/dut.sv, line:13:1, endln:19:10 |vpiName:work@dut |vpiTypedef: \_struct_typespec: (gpio_reg_pkg::gpio_hw2reg_t), line:7:11, endln:7:17 @@ -409,7 +409,7 @@ design: (work@dut) |vpiNet: \_struct_net: (work@dut.hw2reg), line:16:15, endln:16:21 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/HierPathStruct/dut.sv, line:13:1, endln:19:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/HierPathStruct/dut.sv, line:13:1, endln:19:10 |vpiTypespec: \_struct_typespec: (gpio_reg_pkg::gpio_hw2reg_t), line:7:11, endln:7:17 |vpiName:hw2reg @@ -418,7 +418,7 @@ design: (work@dut) |vpiContAssign: \_cont_assign: , line:17:8, endln:17:32 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/HierPathStruct/dut.sv, line:13:1, endln:19:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/HierPathStruct/dut.sv, line:13:1, endln:19:10 |vpiRhs: \_constant: , line:17:28, endln:17:32 |vpiLhs: diff --git a/tests/HighConnPart/HighConnPart.log b/tests/HighConnPart/HighConnPart.log index 785d6b0540..9f614083d3 100644 --- a/tests/HighConnPart/HighConnPart.log +++ b/tests/HighConnPart/HighConnPart.log @@ -265,7 +265,7 @@ cont_assign 3 design 1 logic_net 15 logic_typespec 18 -module 8 +module_inst 8 operation 3 part_select 4 port 13 @@ -280,7 +280,7 @@ cont_assign 5 design 1 logic_net 15 logic_typespec 18 -module 8 +module_inst 8 operation 5 part_select 8 port 21 @@ -300,7 +300,7 @@ design: (work@Device) |vpiElaborated:1 |vpiName:work@Device |uhdmallModules: -\_module: work@Device (work@Device), file:${SURELOG_DIR}/tests/HighConnPart/dut.sv, line:3:1, endln:19:10 +\_module_inst: work@Device (work@Device), file:${SURELOG_DIR}/tests/HighConnPart/dut.sv, line:3:1, endln:19:10 |vpiParent: \_design: (work@Device) |vpiFullName:work@Device @@ -308,28 +308,28 @@ design: (work@Device) |vpiNet: \_logic_net: (work@Device.doubleNibble), line:4:22, endln:4:34 |vpiParent: - \_module: work@Device (work@Device), file:${SURELOG_DIR}/tests/HighConnPart/dut.sv, line:3:1, endln:19:10 + \_module_inst: work@Device (work@Device), file:${SURELOG_DIR}/tests/HighConnPart/dut.sv, line:3:1, endln:19:10 |vpiName:doubleNibble |vpiFullName:work@Device.doubleNibble |vpiNetType:1 |vpiNet: \_logic_net: (work@Device.sum), line:5:23, endln:5:26 |vpiParent: - \_module: work@Device (work@Device), file:${SURELOG_DIR}/tests/HighConnPart/dut.sv, line:3:1, endln:19:10 + \_module_inst: work@Device (work@Device), file:${SURELOG_DIR}/tests/HighConnPart/dut.sv, line:3:1, endln:19:10 |vpiName:sum |vpiFullName:work@Device.sum |vpiNetType:1 |vpiNet: \_logic_net: (work@Device.ignored), line:11:16, endln:11:23 |vpiParent: - \_module: work@Device (work@Device), file:${SURELOG_DIR}/tests/HighConnPart/dut.sv, line:3:1, endln:19:10 + \_module_inst: work@Device (work@Device), file:${SURELOG_DIR}/tests/HighConnPart/dut.sv, line:3:1, endln:19:10 |vpiName:ignored |vpiFullName:work@Device.ignored |vpiNetType:1 |vpiPort: \_port: (doubleNibble), line:4:22, endln:4:34 |vpiParent: - \_module: work@Device (work@Device), file:${SURELOG_DIR}/tests/HighConnPart/dut.sv, line:3:1, endln:19:10 + \_module_inst: work@Device (work@Device), file:${SURELOG_DIR}/tests/HighConnPart/dut.sv, line:3:1, endln:19:10 |vpiName:doubleNibble |vpiDirection:1 |vpiLowConn: @@ -359,7 +359,7 @@ design: (work@Device) |vpiPort: \_port: (sum), line:5:23, endln:5:26 |vpiParent: - \_module: work@Device (work@Device), file:${SURELOG_DIR}/tests/HighConnPart/dut.sv, line:3:1, endln:19:10 + \_module_inst: work@Device (work@Device), file:${SURELOG_DIR}/tests/HighConnPart/dut.sv, line:3:1, endln:19:10 |vpiName:sum |vpiDirection:2 |vpiLowConn: @@ -387,7 +387,7 @@ design: (work@Device) |UINT:0 |vpiConstType:9 |uhdmallModules: -\_module: work@Helper (work@Helper), file:${SURELOG_DIR}/tests/HighConnPart/dut.sv, line:21:1, endln:28:10 +\_module_inst: work@Helper (work@Helper), file:${SURELOG_DIR}/tests/HighConnPart/dut.sv, line:21:1, endln:28:10 |vpiParent: \_design: (work@Device) |vpiFullName:work@Helper @@ -395,28 +395,28 @@ design: (work@Device) |vpiNet: \_logic_net: (work@Helper.a), line:22:22, endln:22:23 |vpiParent: - \_module: work@Helper (work@Helper), file:${SURELOG_DIR}/tests/HighConnPart/dut.sv, line:21:1, endln:28:10 + \_module_inst: work@Helper (work@Helper), file:${SURELOG_DIR}/tests/HighConnPart/dut.sv, line:21:1, endln:28:10 |vpiName:a |vpiFullName:work@Helper.a |vpiNetType:1 |vpiNet: \_logic_net: (work@Helper.b), line:22:25, endln:22:26 |vpiParent: - \_module: work@Helper (work@Helper), file:${SURELOG_DIR}/tests/HighConnPart/dut.sv, line:21:1, endln:28:10 + \_module_inst: work@Helper (work@Helper), file:${SURELOG_DIR}/tests/HighConnPart/dut.sv, line:21:1, endln:28:10 |vpiName:b |vpiFullName:work@Helper.b |vpiNetType:1 |vpiNet: \_logic_net: (work@Helper.result), line:23:23, endln:23:29 |vpiParent: - \_module: work@Helper (work@Helper), file:${SURELOG_DIR}/tests/HighConnPart/dut.sv, line:21:1, endln:28:10 + \_module_inst: work@Helper (work@Helper), file:${SURELOG_DIR}/tests/HighConnPart/dut.sv, line:21:1, endln:28:10 |vpiName:result |vpiFullName:work@Helper.result |vpiNetType:1 |vpiPort: \_port: (a), line:22:22, endln:22:23 |vpiParent: - \_module: work@Helper (work@Helper), file:${SURELOG_DIR}/tests/HighConnPart/dut.sv, line:21:1, endln:28:10 + \_module_inst: work@Helper (work@Helper), file:${SURELOG_DIR}/tests/HighConnPart/dut.sv, line:21:1, endln:28:10 |vpiName:a |vpiDirection:1 |vpiLowConn: @@ -446,7 +446,7 @@ design: (work@Device) |vpiPort: \_port: (b), line:22:25, endln:22:26 |vpiParent: - \_module: work@Helper (work@Helper), file:${SURELOG_DIR}/tests/HighConnPart/dut.sv, line:21:1, endln:28:10 + \_module_inst: work@Helper (work@Helper), file:${SURELOG_DIR}/tests/HighConnPart/dut.sv, line:21:1, endln:28:10 |vpiName:b |vpiDirection:1 |vpiLowConn: @@ -476,7 +476,7 @@ design: (work@Device) |vpiPort: \_port: (result), line:23:23, endln:23:29 |vpiParent: - \_module: work@Helper (work@Helper), file:${SURELOG_DIR}/tests/HighConnPart/dut.sv, line:21:1, endln:28:10 + \_module_inst: work@Helper (work@Helper), file:${SURELOG_DIR}/tests/HighConnPart/dut.sv, line:21:1, endln:28:10 |vpiName:result |vpiDirection:2 |vpiLowConn: @@ -506,7 +506,7 @@ design: (work@Device) |vpiContAssign: \_cont_assign: , line:26:12, endln:26:26 |vpiParent: - \_module: work@Helper (work@Helper), file:${SURELOG_DIR}/tests/HighConnPart/dut.sv, line:21:1, endln:28:10 + \_module_inst: work@Helper (work@Helper), file:${SURELOG_DIR}/tests/HighConnPart/dut.sv, line:21:1, endln:28:10 |vpiRhs: \_operation: , line:26:21, endln:26:26 |vpiParent: @@ -537,14 +537,14 @@ design: (work@Device) |vpiActual: \_logic_net: (work@Device.instance1.result), line:23:23, endln:23:29 |uhdmtopModules: -\_module: work@Device (work@Device), file:${SURELOG_DIR}/tests/HighConnPart/dut.sv, line:3:1, endln:19:10 +\_module_inst: work@Device (work@Device), file:${SURELOG_DIR}/tests/HighConnPart/dut.sv, line:3:1, endln:19:10 |vpiName:work@Device |vpiDefName:work@Device |vpiTop:1 |vpiNet: \_logic_net: (work@Device.doubleNibble), line:4:22, endln:4:34 |vpiParent: - \_module: work@Device (work@Device), file:${SURELOG_DIR}/tests/HighConnPart/dut.sv, line:3:1, endln:19:10 + \_module_inst: work@Device (work@Device), file:${SURELOG_DIR}/tests/HighConnPart/dut.sv, line:3:1, endln:19:10 |vpiTypespec: \_logic_typespec: , line:4:11, endln:4:21 |vpiRange: @@ -571,7 +571,7 @@ design: (work@Device) |vpiNet: \_logic_net: (work@Device.sum), line:5:23, endln:5:26 |vpiParent: - \_module: work@Device (work@Device), file:${SURELOG_DIR}/tests/HighConnPart/dut.sv, line:3:1, endln:19:10 + \_module_inst: work@Device (work@Device), file:${SURELOG_DIR}/tests/HighConnPart/dut.sv, line:3:1, endln:19:10 |vpiTypespec: \_logic_typespec: , line:5:12, endln:5:22 |vpiRange: @@ -598,7 +598,7 @@ design: (work@Device) |vpiNet: \_logic_net: (work@Device.ignored), line:11:16, endln:11:23 |vpiParent: - \_module: work@Device (work@Device), file:${SURELOG_DIR}/tests/HighConnPart/dut.sv, line:3:1, endln:19:10 + \_module_inst: work@Device (work@Device), file:${SURELOG_DIR}/tests/HighConnPart/dut.sv, line:3:1, endln:19:10 |vpiTypespec: \_logic_typespec: , line:11:5, endln:11:15 |vpiRange: @@ -626,7 +626,7 @@ design: (work@Device) |vpiPort: \_port: (doubleNibble), line:4:22, endln:4:34 |vpiParent: - \_module: work@Device (work@Device), file:${SURELOG_DIR}/tests/HighConnPart/dut.sv, line:3:1, endln:19:10 + \_module_inst: work@Device (work@Device), file:${SURELOG_DIR}/tests/HighConnPart/dut.sv, line:3:1, endln:19:10 |vpiName:doubleNibble |vpiDirection:1 |vpiLowConn: @@ -660,11 +660,11 @@ design: (work@Device) |UINT:0 |vpiConstType:9 |vpiInstance: - \_module: work@Device (work@Device), file:${SURELOG_DIR}/tests/HighConnPart/dut.sv, line:3:1, endln:19:10 + \_module_inst: work@Device (work@Device), file:${SURELOG_DIR}/tests/HighConnPart/dut.sv, line:3:1, endln:19:10 |vpiPort: \_port: (sum), line:5:23, endln:5:26 |vpiParent: - \_module: work@Device (work@Device), file:${SURELOG_DIR}/tests/HighConnPart/dut.sv, line:3:1, endln:19:10 + \_module_inst: work@Device (work@Device), file:${SURELOG_DIR}/tests/HighConnPart/dut.sv, line:3:1, endln:19:10 |vpiName:sum |vpiDirection:2 |vpiLowConn: @@ -698,11 +698,11 @@ design: (work@Device) |UINT:0 |vpiConstType:9 |vpiInstance: - \_module: work@Device (work@Device), file:${SURELOG_DIR}/tests/HighConnPart/dut.sv, line:3:1, endln:19:10 - |vpiModule: - \_module: work@Helper (work@Device.instance1), file:${SURELOG_DIR}/tests/HighConnPart/dut.sv, line:9:5, endln:9:65 + \_module_inst: work@Device (work@Device), file:${SURELOG_DIR}/tests/HighConnPart/dut.sv, line:3:1, endln:19:10 + |vpiModuleInst: + \_module_inst: work@Helper (work@Device.instance1), file:${SURELOG_DIR}/tests/HighConnPart/dut.sv, line:9:5, endln:9:65 |vpiParent: - \_module: work@Device (work@Device), file:${SURELOG_DIR}/tests/HighConnPart/dut.sv, line:3:1, endln:19:10 + \_module_inst: work@Device (work@Device), file:${SURELOG_DIR}/tests/HighConnPart/dut.sv, line:3:1, endln:19:10 |vpiName:instance1 |vpiFullName:work@Device.instance1 |vpiDefName:work@Helper @@ -711,7 +711,7 @@ design: (work@Device) |vpiNet: \_logic_net: (work@Device.instance1.a), line:22:22, endln:22:23 |vpiParent: - \_module: work@Helper (work@Device.instance1), file:${SURELOG_DIR}/tests/HighConnPart/dut.sv, line:9:5, endln:9:65 + \_module_inst: work@Helper (work@Device.instance1), file:${SURELOG_DIR}/tests/HighConnPart/dut.sv, line:9:5, endln:9:65 |vpiTypespec: \_logic_typespec: , line:22:11, endln:22:21 |vpiRange: @@ -738,7 +738,7 @@ design: (work@Device) |vpiNet: \_logic_net: (work@Device.instance1.b), line:22:25, endln:22:26 |vpiParent: - \_module: work@Helper (work@Device.instance1), file:${SURELOG_DIR}/tests/HighConnPart/dut.sv, line:9:5, endln:9:65 + \_module_inst: work@Helper (work@Device.instance1), file:${SURELOG_DIR}/tests/HighConnPart/dut.sv, line:9:5, endln:9:65 |vpiTypespec: \_logic_typespec: , line:22:11, endln:22:21 |vpiName:b @@ -747,7 +747,7 @@ design: (work@Device) |vpiNet: \_logic_net: (work@Device.instance1.result), line:23:23, endln:23:29 |vpiParent: - \_module: work@Helper (work@Device.instance1), file:${SURELOG_DIR}/tests/HighConnPart/dut.sv, line:9:5, endln:9:65 + \_module_inst: work@Helper (work@Device.instance1), file:${SURELOG_DIR}/tests/HighConnPart/dut.sv, line:9:5, endln:9:65 |vpiTypespec: \_logic_typespec: , line:23:12, endln:23:22 |vpiRange: @@ -772,11 +772,11 @@ design: (work@Device) |vpiFullName:work@Device.instance1.result |vpiNetType:1 |vpiInstance: - \_module: work@Device (work@Device), file:${SURELOG_DIR}/tests/HighConnPart/dut.sv, line:3:1, endln:19:10 + \_module_inst: work@Device (work@Device), file:${SURELOG_DIR}/tests/HighConnPart/dut.sv, line:3:1, endln:19:10 |vpiPort: \_port: (a), line:22:22, endln:22:23 |vpiParent: - \_module: work@Helper (work@Device.instance1), file:${SURELOG_DIR}/tests/HighConnPart/dut.sv, line:9:5, endln:9:65 + \_module_inst: work@Helper (work@Device.instance1), file:${SURELOG_DIR}/tests/HighConnPart/dut.sv, line:9:5, endln:9:65 |vpiName:a |vpiDirection:1 |vpiHighConn: @@ -834,11 +834,11 @@ design: (work@Device) |UINT:0 |vpiConstType:9 |vpiInstance: - \_module: work@Helper (work@Device.instance1), file:${SURELOG_DIR}/tests/HighConnPart/dut.sv, line:9:5, endln:9:65 + \_module_inst: work@Helper (work@Device.instance1), file:${SURELOG_DIR}/tests/HighConnPart/dut.sv, line:9:5, endln:9:65 |vpiPort: \_port: (b), line:22:25, endln:22:26 |vpiParent: - \_module: work@Helper (work@Device.instance1), file:${SURELOG_DIR}/tests/HighConnPart/dut.sv, line:9:5, endln:9:65 + \_module_inst: work@Helper (work@Device.instance1), file:${SURELOG_DIR}/tests/HighConnPart/dut.sv, line:9:5, endln:9:65 |vpiName:b |vpiDirection:1 |vpiHighConn: @@ -876,11 +876,11 @@ design: (work@Device) |vpiTypedef: \_logic_typespec: , line:22:11, endln:22:21 |vpiInstance: - \_module: work@Helper (work@Device.instance1), file:${SURELOG_DIR}/tests/HighConnPart/dut.sv, line:9:5, endln:9:65 + \_module_inst: work@Helper (work@Device.instance1), file:${SURELOG_DIR}/tests/HighConnPart/dut.sv, line:9:5, endln:9:65 |vpiPort: \_port: (result), line:23:23, endln:23:29 |vpiParent: - \_module: work@Helper (work@Device.instance1), file:${SURELOG_DIR}/tests/HighConnPart/dut.sv, line:9:5, endln:9:65 + \_module_inst: work@Helper (work@Device.instance1), file:${SURELOG_DIR}/tests/HighConnPart/dut.sv, line:9:5, endln:9:65 |vpiName:result |vpiDirection:2 |vpiHighConn: @@ -922,11 +922,11 @@ design: (work@Device) |UINT:0 |vpiConstType:9 |vpiInstance: - \_module: work@Helper (work@Device.instance1), file:${SURELOG_DIR}/tests/HighConnPart/dut.sv, line:9:5, endln:9:65 + \_module_inst: work@Helper (work@Device.instance1), file:${SURELOG_DIR}/tests/HighConnPart/dut.sv, line:9:5, endln:9:65 |vpiContAssign: \_cont_assign: , line:26:12, endln:26:26 |vpiParent: - \_module: work@Helper (work@Device.instance1), file:${SURELOG_DIR}/tests/HighConnPart/dut.sv, line:9:5, endln:9:65 + \_module_inst: work@Helper (work@Device.instance1), file:${SURELOG_DIR}/tests/HighConnPart/dut.sv, line:9:5, endln:9:65 |vpiRhs: \_operation: , line:26:21, endln:26:26 |vpiParent: @@ -956,10 +956,10 @@ design: (work@Device) |vpiFullName:work@Device.instance1.result |vpiActual: \_logic_net: (work@Device.instance1.result), line:23:23, endln:23:29 - |vpiModule: - \_module: work@Helper (work@Device.instance2), file:${SURELOG_DIR}/tests/HighConnPart/dut.sv, line:12:5, endln:16:7 + |vpiModuleInst: + \_module_inst: work@Helper (work@Device.instance2), file:${SURELOG_DIR}/tests/HighConnPart/dut.sv, line:12:5, endln:16:7 |vpiParent: - \_module: work@Device (work@Device), file:${SURELOG_DIR}/tests/HighConnPart/dut.sv, line:3:1, endln:19:10 + \_module_inst: work@Device (work@Device), file:${SURELOG_DIR}/tests/HighConnPart/dut.sv, line:3:1, endln:19:10 |vpiName:instance2 |vpiFullName:work@Device.instance2 |vpiDefName:work@Helper @@ -968,7 +968,7 @@ design: (work@Device) |vpiNet: \_logic_net: (work@Device.instance2.a), line:22:22, endln:22:23 |vpiParent: - \_module: work@Helper (work@Device.instance2), file:${SURELOG_DIR}/tests/HighConnPart/dut.sv, line:12:5, endln:16:7 + \_module_inst: work@Helper (work@Device.instance2), file:${SURELOG_DIR}/tests/HighConnPart/dut.sv, line:12:5, endln:16:7 |vpiTypespec: \_logic_typespec: , line:22:11, endln:22:21 |vpiRange: @@ -995,7 +995,7 @@ design: (work@Device) |vpiNet: \_logic_net: (work@Device.instance2.b), line:22:25, endln:22:26 |vpiParent: - \_module: work@Helper (work@Device.instance2), file:${SURELOG_DIR}/tests/HighConnPart/dut.sv, line:12:5, endln:16:7 + \_module_inst: work@Helper (work@Device.instance2), file:${SURELOG_DIR}/tests/HighConnPart/dut.sv, line:12:5, endln:16:7 |vpiTypespec: \_logic_typespec: , line:22:11, endln:22:21 |vpiName:b @@ -1004,7 +1004,7 @@ design: (work@Device) |vpiNet: \_logic_net: (work@Device.instance2.result), line:23:23, endln:23:29 |vpiParent: - \_module: work@Helper (work@Device.instance2), file:${SURELOG_DIR}/tests/HighConnPart/dut.sv, line:12:5, endln:16:7 + \_module_inst: work@Helper (work@Device.instance2), file:${SURELOG_DIR}/tests/HighConnPart/dut.sv, line:12:5, endln:16:7 |vpiTypespec: \_logic_typespec: , line:23:12, endln:23:22 |vpiRange: @@ -1029,11 +1029,11 @@ design: (work@Device) |vpiFullName:work@Device.instance2.result |vpiNetType:1 |vpiInstance: - \_module: work@Device (work@Device), file:${SURELOG_DIR}/tests/HighConnPart/dut.sv, line:3:1, endln:19:10 + \_module_inst: work@Device (work@Device), file:${SURELOG_DIR}/tests/HighConnPart/dut.sv, line:3:1, endln:19:10 |vpiPort: \_port: (a), line:22:22, endln:22:23 |vpiParent: - \_module: work@Helper (work@Device.instance2), file:${SURELOG_DIR}/tests/HighConnPart/dut.sv, line:12:5, endln:16:7 + \_module_inst: work@Helper (work@Device.instance2), file:${SURELOG_DIR}/tests/HighConnPart/dut.sv, line:12:5, endln:16:7 |vpiName:a |vpiDirection:1 |vpiHighConn: @@ -1091,11 +1091,11 @@ design: (work@Device) |UINT:0 |vpiConstType:9 |vpiInstance: - \_module: work@Helper (work@Device.instance2), file:${SURELOG_DIR}/tests/HighConnPart/dut.sv, line:12:5, endln:16:7 + \_module_inst: work@Helper (work@Device.instance2), file:${SURELOG_DIR}/tests/HighConnPart/dut.sv, line:12:5, endln:16:7 |vpiPort: \_port: (b), line:22:25, endln:22:26 |vpiParent: - \_module: work@Helper (work@Device.instance2), file:${SURELOG_DIR}/tests/HighConnPart/dut.sv, line:12:5, endln:16:7 + \_module_inst: work@Helper (work@Device.instance2), file:${SURELOG_DIR}/tests/HighConnPart/dut.sv, line:12:5, endln:16:7 |vpiName:b |vpiDirection:1 |vpiHighConn: @@ -1133,11 +1133,11 @@ design: (work@Device) |vpiTypedef: \_logic_typespec: , line:22:11, endln:22:21 |vpiInstance: - \_module: work@Helper (work@Device.instance2), file:${SURELOG_DIR}/tests/HighConnPart/dut.sv, line:12:5, endln:16:7 + \_module_inst: work@Helper (work@Device.instance2), file:${SURELOG_DIR}/tests/HighConnPart/dut.sv, line:12:5, endln:16:7 |vpiPort: \_port: (result), line:23:23, endln:23:29 |vpiParent: - \_module: work@Helper (work@Device.instance2), file:${SURELOG_DIR}/tests/HighConnPart/dut.sv, line:12:5, endln:16:7 + \_module_inst: work@Helper (work@Device.instance2), file:${SURELOG_DIR}/tests/HighConnPart/dut.sv, line:12:5, endln:16:7 |vpiName:result |vpiDirection:2 |vpiHighConn: @@ -1179,11 +1179,11 @@ design: (work@Device) |UINT:0 |vpiConstType:9 |vpiInstance: - \_module: work@Helper (work@Device.instance2), file:${SURELOG_DIR}/tests/HighConnPart/dut.sv, line:12:5, endln:16:7 + \_module_inst: work@Helper (work@Device.instance2), file:${SURELOG_DIR}/tests/HighConnPart/dut.sv, line:12:5, endln:16:7 |vpiContAssign: \_cont_assign: , line:26:12, endln:26:26 |vpiParent: - \_module: work@Helper (work@Device.instance2), file:${SURELOG_DIR}/tests/HighConnPart/dut.sv, line:12:5, endln:16:7 + \_module_inst: work@Helper (work@Device.instance2), file:${SURELOG_DIR}/tests/HighConnPart/dut.sv, line:12:5, endln:16:7 |vpiRhs: \_operation: , line:26:21, endln:26:26 |vpiParent: diff --git a/tests/HighLow/HighLow.log b/tests/HighLow/HighLow.log index 6434924e06..f1e4054d54 100644 --- a/tests/HighLow/HighLow.log +++ b/tests/HighLow/HighLow.log @@ -318,7 +318,7 @@ gen_scope_array 8 int_typespec 6 logic_net 1 logic_typespec 1 -module 11 +module_inst 11 operation 4 param_assign 10 parameter 10 @@ -337,7 +337,7 @@ gen_scope_array 12 int_typespec 6 logic_net 1 logic_typespec 1 -module 15 +module_inst 15 operation 4 param_assign 10 parameter 10 @@ -358,20 +358,20 @@ design: (work@top) |vpiElaborated:1 |vpiName:work@top |uhdmallModules: -\_module: work@GOOD (work@GOOD), file:${SURELOG_DIR}/tests/HighLow/dut.sv, line:1:1, endln:2:10 +\_module_inst: work@GOOD (work@GOOD), file:${SURELOG_DIR}/tests/HighLow/dut.sv, line:1:1, endln:2:10 |vpiParent: \_design: (work@top) |vpiFullName:work@GOOD |vpiDefName:work@GOOD |uhdmallModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/HighLow/dut.sv, line:4:1, endln:26:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/HighLow/dut.sv, line:4:1, endln:26:10 |vpiParent: \_design: (work@top) |vpiFullName:work@top |vpiParameter: \_parameter: (work@top.a), line:6:19, endln:6:20 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/HighLow/dut.sv, line:4:1, endln:26:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/HighLow/dut.sv, line:4:1, endln:26:10 |UINT:10 |vpiTypespec: \_int_typespec: , line:6:13, endln:6:18 @@ -400,31 +400,31 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.high), line:7:14, endln:7:18 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/HighLow/dut.sv, line:4:1, endln:26:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/HighLow/dut.sv, line:4:1, endln:26:10 |vpiName:high |vpiFullName:work@top.high |vpiParameter: \_parameter: (work@top.low), line:8:14, endln:8:17 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/HighLow/dut.sv, line:4:1, endln:26:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/HighLow/dut.sv, line:4:1, endln:26:10 |vpiName:low |vpiFullName:work@top.low |vpiParameter: \_parameter: (work@top.left), line:9:14, endln:9:18 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/HighLow/dut.sv, line:4:1, endln:26:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/HighLow/dut.sv, line:4:1, endln:26:10 |vpiName:left |vpiFullName:work@top.left |vpiParameter: \_parameter: (work@top.right), line:10:14, endln:10:19 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/HighLow/dut.sv, line:4:1, endln:26:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/HighLow/dut.sv, line:4:1, endln:26:10 |vpiName:right |vpiFullName:work@top.right |vpiParamAssign: \_param_assign: , line:6:19, endln:6:25 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/HighLow/dut.sv, line:4:1, endln:26:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/HighLow/dut.sv, line:4:1, endln:26:10 |vpiRhs: \_constant: , line:6:23, endln:6:25 |vpiDecompile:10 @@ -438,7 +438,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:7:14, endln:7:29 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/HighLow/dut.sv, line:4:1, endln:26:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/HighLow/dut.sv, line:4:1, endln:26:10 |vpiRhs: \_sys_func_call: ($high), line:7:21, endln:7:29 |vpiArgument: @@ -452,7 +452,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:8:14, endln:8:27 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/HighLow/dut.sv, line:4:1, endln:26:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/HighLow/dut.sv, line:4:1, endln:26:10 |vpiRhs: \_sys_func_call: ($low), line:8:20, endln:8:27 |vpiArgument: @@ -466,7 +466,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:9:14, endln:9:29 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/HighLow/dut.sv, line:4:1, endln:26:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/HighLow/dut.sv, line:4:1, endln:26:10 |vpiRhs: \_sys_func_call: ($left), line:9:21, endln:9:29 |vpiArgument: @@ -480,7 +480,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:10:14, endln:10:31 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/HighLow/dut.sv, line:4:1, endln:26:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/HighLow/dut.sv, line:4:1, endln:26:10 |vpiRhs: \_sys_func_call: ($right), line:10:22, endln:10:31 |vpiArgument: @@ -495,7 +495,7 @@ design: (work@top) |vpiContAssign: \_cont_assign: , line:12:10, endln:12:24 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/HighLow/dut.sv, line:4:1, endln:26:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/HighLow/dut.sv, line:4:1, endln:26:10 |vpiRhs: \_sys_func_call: ($high), line:12:16, endln:12:24 |vpiParent: @@ -516,12 +516,12 @@ design: (work@top) |vpiActual: \_logic_net: (ccc) |uhdmtopModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/HighLow/dut.sv, line:4:1, endln:26:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/HighLow/dut.sv, line:4:1, endln:26:10 |vpiName:work@top |vpiParameter: \_parameter: (work@top.a), line:6:19, endln:6:20 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/HighLow/dut.sv, line:4:1, endln:26:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/HighLow/dut.sv, line:4:1, endln:26:10 |UINT:10 |vpiTypespec: \_int_typespec: , line:6:13, endln:6:18 @@ -552,31 +552,31 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.high), line:7:14, endln:7:18 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/HighLow/dut.sv, line:4:1, endln:26:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/HighLow/dut.sv, line:4:1, endln:26:10 |vpiName:high |vpiFullName:work@top.high |vpiParameter: \_parameter: (work@top.low), line:8:14, endln:8:17 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/HighLow/dut.sv, line:4:1, endln:26:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/HighLow/dut.sv, line:4:1, endln:26:10 |vpiName:low |vpiFullName:work@top.low |vpiParameter: \_parameter: (work@top.left), line:9:14, endln:9:18 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/HighLow/dut.sv, line:4:1, endln:26:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/HighLow/dut.sv, line:4:1, endln:26:10 |vpiName:left |vpiFullName:work@top.left |vpiParameter: \_parameter: (work@top.right), line:10:14, endln:10:19 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/HighLow/dut.sv, line:4:1, endln:26:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/HighLow/dut.sv, line:4:1, endln:26:10 |vpiName:right |vpiFullName:work@top.right |vpiParamAssign: \_param_assign: , line:6:19, endln:6:25 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/HighLow/dut.sv, line:4:1, endln:26:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/HighLow/dut.sv, line:4:1, endln:26:10 |vpiRhs: \_constant: , line:6:23, endln:6:25 |vpiDecompile:2 @@ -598,7 +598,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:7:14, endln:7:29 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/HighLow/dut.sv, line:4:1, endln:26:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/HighLow/dut.sv, line:4:1, endln:26:10 |vpiRhs: \_constant: , line:6:14, endln:6:15 |vpiParent: @@ -612,7 +612,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:8:14, endln:8:27 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/HighLow/dut.sv, line:4:1, endln:26:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/HighLow/dut.sv, line:4:1, endln:26:10 |vpiRhs: \_constant: , line:6:16, endln:6:17 |vpiParent: @@ -626,7 +626,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:9:14, endln:9:29 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/HighLow/dut.sv, line:4:1, endln:26:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/HighLow/dut.sv, line:4:1, endln:26:10 |vpiRhs: \_constant: , line:6:14, endln:6:15 |vpiParent: @@ -640,7 +640,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:10:14, endln:10:31 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/HighLow/dut.sv, line:4:1, endln:26:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/HighLow/dut.sv, line:4:1, endln:26:10 |vpiRhs: \_constant: , line:6:16, endln:6:17 |vpiParent: @@ -661,7 +661,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.genblk1), line:14:3, endln:16:6 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/HighLow/dut.sv, line:4:1, endln:26:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/HighLow/dut.sv, line:4:1, endln:26:10 |vpiName:genblk1 |vpiFullName:work@top.genblk1 |vpiGenScope: @@ -669,8 +669,8 @@ design: (work@top) |vpiParent: \_gen_scope_array: (work@top.genblk1), line:14:3, endln:16:6 |vpiFullName:work@top.genblk1 - |vpiModule: - \_module: work@GOOD (work@top.genblk1.good1), file:${SURELOG_DIR}/tests/HighLow/dut.sv, line:15:5, endln:15:18 + |vpiModuleInst: + \_module_inst: work@GOOD (work@top.genblk1.good1), file:${SURELOG_DIR}/tests/HighLow/dut.sv, line:15:5, endln:15:18 |vpiParent: \_gen_scope: (work@top.genblk1) |vpiName:good1 @@ -681,7 +681,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.genblk2), line:17:3, endln:19:6 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/HighLow/dut.sv, line:4:1, endln:26:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/HighLow/dut.sv, line:4:1, endln:26:10 |vpiName:genblk2 |vpiFullName:work@top.genblk2 |vpiGenScope: @@ -689,8 +689,8 @@ design: (work@top) |vpiParent: \_gen_scope_array: (work@top.genblk2), line:17:3, endln:19:6 |vpiFullName:work@top.genblk2 - |vpiModule: - \_module: work@GOOD (work@top.genblk2.good2), file:${SURELOG_DIR}/tests/HighLow/dut.sv, line:18:5, endln:18:18 + |vpiModuleInst: + \_module_inst: work@GOOD (work@top.genblk2.good2), file:${SURELOG_DIR}/tests/HighLow/dut.sv, line:18:5, endln:18:18 |vpiParent: \_gen_scope: (work@top.genblk2) |vpiName:good2 @@ -701,7 +701,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.genblk3), line:20:3, endln:22:6 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/HighLow/dut.sv, line:4:1, endln:26:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/HighLow/dut.sv, line:4:1, endln:26:10 |vpiName:genblk3 |vpiFullName:work@top.genblk3 |vpiGenScope: @@ -709,8 +709,8 @@ design: (work@top) |vpiParent: \_gen_scope_array: (work@top.genblk3), line:20:3, endln:22:6 |vpiFullName:work@top.genblk3 - |vpiModule: - \_module: work@GOOD (work@top.genblk3.good3), file:${SURELOG_DIR}/tests/HighLow/dut.sv, line:21:5, endln:21:18 + |vpiModuleInst: + \_module_inst: work@GOOD (work@top.genblk3.good3), file:${SURELOG_DIR}/tests/HighLow/dut.sv, line:21:5, endln:21:18 |vpiParent: \_gen_scope: (work@top.genblk3) |vpiName:good3 @@ -721,7 +721,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.genblk4), line:23:3, endln:25:6 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/HighLow/dut.sv, line:4:1, endln:26:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/HighLow/dut.sv, line:4:1, endln:26:10 |vpiName:genblk4 |vpiFullName:work@top.genblk4 |vpiGenScope: @@ -729,8 +729,8 @@ design: (work@top) |vpiParent: \_gen_scope_array: (work@top.genblk4), line:23:3, endln:25:6 |vpiFullName:work@top.genblk4 - |vpiModule: - \_module: work@GOOD (work@top.genblk4.good4), file:${SURELOG_DIR}/tests/HighLow/dut.sv, line:24:5, endln:24:18 + |vpiModuleInst: + \_module_inst: work@GOOD (work@top.genblk4.good4), file:${SURELOG_DIR}/tests/HighLow/dut.sv, line:24:5, endln:24:18 |vpiParent: \_gen_scope: (work@top.genblk4) |vpiName:good4 @@ -741,7 +741,7 @@ design: (work@top) |vpiContAssign: \_cont_assign: , line:12:10, endln:12:24 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/HighLow/dut.sv, line:4:1, endln:26:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/HighLow/dut.sv, line:4:1, endln:26:10 |vpiRhs: \_constant: |vpiParent: diff --git a/tests/IODataTypes/IODataTypes.log b/tests/IODataTypes/IODataTypes.log index 471ee7f8b4..50d6116e30 100644 --- a/tests/IODataTypes/IODataTypes.log +++ b/tests/IODataTypes/IODataTypes.log @@ -99,7 +99,7 @@ integer_var 1 logic_net 6 long_int_typespec 3 long_int_var 1 -module 2 +module_inst 2 port 12 ref_obj 12 short_int_typespec 6 @@ -118,7 +118,7 @@ integer_var 1 logic_net 6 long_int_typespec 3 long_int_var 1 -module 2 +module_inst 2 port 18 ref_obj 18 short_int_typespec 6 @@ -137,7 +137,7 @@ design: (work@dff_diffDataTypes) |vpiElaborated:1 |vpiName:work@dff_diffDataTypes |uhdmallModules: -\_module: work@dff_diffDataTypes (work@dff_diffDataTypes), file:${SURELOG_DIR}/tests/IODataTypes/dut.sv, line:1:1, endln:9:10 +\_module_inst: work@dff_diffDataTypes (work@dff_diffDataTypes), file:${SURELOG_DIR}/tests/IODataTypes/dut.sv, line:1:1, endln:9:10 |vpiParent: \_design: (work@dff_diffDataTypes) |vpiFullName:work@dff_diffDataTypes @@ -145,43 +145,43 @@ design: (work@dff_diffDataTypes) |vpiNet: \_logic_net: (work@dff_diffDataTypes.a), line:2:11, endln:2:12 |vpiParent: - \_module: work@dff_diffDataTypes (work@dff_diffDataTypes), file:${SURELOG_DIR}/tests/IODataTypes/dut.sv, line:1:1, endln:9:10 + \_module_inst: work@dff_diffDataTypes (work@dff_diffDataTypes), file:${SURELOG_DIR}/tests/IODataTypes/dut.sv, line:1:1, endln:9:10 |vpiName:a |vpiFullName:work@dff_diffDataTypes.a |vpiNet: \_logic_net: (work@dff_diffDataTypes.b), line:3:12, endln:3:13 |vpiParent: - \_module: work@dff_diffDataTypes (work@dff_diffDataTypes), file:${SURELOG_DIR}/tests/IODataTypes/dut.sv, line:1:1, endln:9:10 + \_module_inst: work@dff_diffDataTypes (work@dff_diffDataTypes), file:${SURELOG_DIR}/tests/IODataTypes/dut.sv, line:1:1, endln:9:10 |vpiName:b |vpiFullName:work@dff_diffDataTypes.b |vpiNet: \_logic_net: (work@dff_diffDataTypes.c), line:4:16, endln:4:17 |vpiParent: - \_module: work@dff_diffDataTypes (work@dff_diffDataTypes), file:${SURELOG_DIR}/tests/IODataTypes/dut.sv, line:1:1, endln:9:10 + \_module_inst: work@dff_diffDataTypes (work@dff_diffDataTypes), file:${SURELOG_DIR}/tests/IODataTypes/dut.sv, line:1:1, endln:9:10 |vpiName:c |vpiFullName:work@dff_diffDataTypes.c |vpiNet: \_logic_net: (work@dff_diffDataTypes.d), line:5:15, endln:5:16 |vpiParent: - \_module: work@dff_diffDataTypes (work@dff_diffDataTypes), file:${SURELOG_DIR}/tests/IODataTypes/dut.sv, line:1:1, endln:9:10 + \_module_inst: work@dff_diffDataTypes (work@dff_diffDataTypes), file:${SURELOG_DIR}/tests/IODataTypes/dut.sv, line:1:1, endln:9:10 |vpiName:d |vpiFullName:work@dff_diffDataTypes.d |vpiNet: \_logic_net: (work@dff_diffDataTypes.e), line:6:15, endln:6:16 |vpiParent: - \_module: work@dff_diffDataTypes (work@dff_diffDataTypes), file:${SURELOG_DIR}/tests/IODataTypes/dut.sv, line:1:1, endln:9:10 + \_module_inst: work@dff_diffDataTypes (work@dff_diffDataTypes), file:${SURELOG_DIR}/tests/IODataTypes/dut.sv, line:1:1, endln:9:10 |vpiName:e |vpiFullName:work@dff_diffDataTypes.e |vpiNet: \_logic_net: (work@dff_diffDataTypes.f), line:7:23, endln:7:24 |vpiParent: - \_module: work@dff_diffDataTypes (work@dff_diffDataTypes), file:${SURELOG_DIR}/tests/IODataTypes/dut.sv, line:1:1, endln:9:10 + \_module_inst: work@dff_diffDataTypes (work@dff_diffDataTypes), file:${SURELOG_DIR}/tests/IODataTypes/dut.sv, line:1:1, endln:9:10 |vpiName:f |vpiFullName:work@dff_diffDataTypes.f |vpiPort: \_port: (a), line:2:11, endln:2:12 |vpiParent: - \_module: work@dff_diffDataTypes (work@dff_diffDataTypes), file:${SURELOG_DIR}/tests/IODataTypes/dut.sv, line:1:1, endln:9:10 + \_module_inst: work@dff_diffDataTypes (work@dff_diffDataTypes), file:${SURELOG_DIR}/tests/IODataTypes/dut.sv, line:1:1, endln:9:10 |vpiName:a |vpiDirection:1 |vpiLowConn: @@ -194,7 +194,7 @@ design: (work@dff_diffDataTypes) |vpiPort: \_port: (b), line:3:12, endln:3:13 |vpiParent: - \_module: work@dff_diffDataTypes (work@dff_diffDataTypes), file:${SURELOG_DIR}/tests/IODataTypes/dut.sv, line:1:1, endln:9:10 + \_module_inst: work@dff_diffDataTypes (work@dff_diffDataTypes), file:${SURELOG_DIR}/tests/IODataTypes/dut.sv, line:1:1, endln:9:10 |vpiName:b |vpiDirection:1 |vpiLowConn: @@ -207,7 +207,7 @@ design: (work@dff_diffDataTypes) |vpiPort: \_port: (c), line:4:16, endln:4:17 |vpiParent: - \_module: work@dff_diffDataTypes (work@dff_diffDataTypes), file:${SURELOG_DIR}/tests/IODataTypes/dut.sv, line:1:1, endln:9:10 + \_module_inst: work@dff_diffDataTypes (work@dff_diffDataTypes), file:${SURELOG_DIR}/tests/IODataTypes/dut.sv, line:1:1, endln:9:10 |vpiName:c |vpiDirection:1 |vpiLowConn: @@ -220,7 +220,7 @@ design: (work@dff_diffDataTypes) |vpiPort: \_port: (d), line:5:15, endln:5:16 |vpiParent: - \_module: work@dff_diffDataTypes (work@dff_diffDataTypes), file:${SURELOG_DIR}/tests/IODataTypes/dut.sv, line:1:1, endln:9:10 + \_module_inst: work@dff_diffDataTypes (work@dff_diffDataTypes), file:${SURELOG_DIR}/tests/IODataTypes/dut.sv, line:1:1, endln:9:10 |vpiName:d |vpiDirection:1 |vpiLowConn: @@ -233,7 +233,7 @@ design: (work@dff_diffDataTypes) |vpiPort: \_port: (e), line:6:15, endln:6:16 |vpiParent: - \_module: work@dff_diffDataTypes (work@dff_diffDataTypes), file:${SURELOG_DIR}/tests/IODataTypes/dut.sv, line:1:1, endln:9:10 + \_module_inst: work@dff_diffDataTypes (work@dff_diffDataTypes), file:${SURELOG_DIR}/tests/IODataTypes/dut.sv, line:1:1, endln:9:10 |vpiName:e |vpiDirection:1 |vpiLowConn: @@ -246,7 +246,7 @@ design: (work@dff_diffDataTypes) |vpiPort: \_port: (f), line:7:23, endln:7:24 |vpiParent: - \_module: work@dff_diffDataTypes (work@dff_diffDataTypes), file:${SURELOG_DIR}/tests/IODataTypes/dut.sv, line:1:1, endln:9:10 + \_module_inst: work@dff_diffDataTypes (work@dff_diffDataTypes), file:${SURELOG_DIR}/tests/IODataTypes/dut.sv, line:1:1, endln:9:10 |vpiName:f |vpiDirection:1 |vpiLowConn: @@ -257,12 +257,12 @@ design: (work@dff_diffDataTypes) \_short_int_typespec: , line:7:7, endln:7:15 |vpiSigned:1 |uhdmtopModules: -\_module: work@dff_diffDataTypes (work@dff_diffDataTypes), file:${SURELOG_DIR}/tests/IODataTypes/dut.sv, line:1:1, endln:9:10 +\_module_inst: work@dff_diffDataTypes (work@dff_diffDataTypes), file:${SURELOG_DIR}/tests/IODataTypes/dut.sv, line:1:1, endln:9:10 |vpiName:work@dff_diffDataTypes |vpiVariables: \_int_var: (work@dff_diffDataTypes.a), line:2:11, endln:2:12 |vpiParent: - \_module: work@dff_diffDataTypes (work@dff_diffDataTypes), file:${SURELOG_DIR}/tests/IODataTypes/dut.sv, line:1:1, endln:9:10 + \_module_inst: work@dff_diffDataTypes (work@dff_diffDataTypes), file:${SURELOG_DIR}/tests/IODataTypes/dut.sv, line:1:1, endln:9:10 |vpiTypespec: \_int_typespec: , line:2:7, endln:2:10 |vpiSigned:1 @@ -273,7 +273,7 @@ design: (work@dff_diffDataTypes) |vpiVariables: \_byte_var: (work@dff_diffDataTypes.b), line:3:12, endln:3:13 |vpiParent: - \_module: work@dff_diffDataTypes (work@dff_diffDataTypes), file:${SURELOG_DIR}/tests/IODataTypes/dut.sv, line:1:1, endln:9:10 + \_module_inst: work@dff_diffDataTypes (work@dff_diffDataTypes), file:${SURELOG_DIR}/tests/IODataTypes/dut.sv, line:1:1, endln:9:10 |vpiTypespec: \_byte_typespec: , line:3:7, endln:3:11 |vpiSigned:1 @@ -284,7 +284,7 @@ design: (work@dff_diffDataTypes) |vpiVariables: \_short_int_var: (work@dff_diffDataTypes.c), line:4:16, endln:4:17 |vpiParent: - \_module: work@dff_diffDataTypes (work@dff_diffDataTypes), file:${SURELOG_DIR}/tests/IODataTypes/dut.sv, line:1:1, endln:9:10 + \_module_inst: work@dff_diffDataTypes (work@dff_diffDataTypes), file:${SURELOG_DIR}/tests/IODataTypes/dut.sv, line:1:1, endln:9:10 |vpiTypespec: \_short_int_typespec: , line:4:7, endln:4:15 |vpiSigned:1 @@ -295,7 +295,7 @@ design: (work@dff_diffDataTypes) |vpiVariables: \_long_int_var: (work@dff_diffDataTypes.d), line:5:15, endln:5:16 |vpiParent: - \_module: work@dff_diffDataTypes (work@dff_diffDataTypes), file:${SURELOG_DIR}/tests/IODataTypes/dut.sv, line:1:1, endln:9:10 + \_module_inst: work@dff_diffDataTypes (work@dff_diffDataTypes), file:${SURELOG_DIR}/tests/IODataTypes/dut.sv, line:1:1, endln:9:10 |vpiTypespec: \_long_int_typespec: , line:5:7, endln:5:14 |vpiSigned:1 @@ -306,7 +306,7 @@ design: (work@dff_diffDataTypes) |vpiVariables: \_integer_var: (work@dff_diffDataTypes.e), line:6:15, endln:6:16 |vpiParent: - \_module: work@dff_diffDataTypes (work@dff_diffDataTypes), file:${SURELOG_DIR}/tests/IODataTypes/dut.sv, line:1:1, endln:9:10 + \_module_inst: work@dff_diffDataTypes (work@dff_diffDataTypes), file:${SURELOG_DIR}/tests/IODataTypes/dut.sv, line:1:1, endln:9:10 |vpiTypespec: \_integer_typespec: , line:6:7, endln:6:14 |vpiSigned:1 @@ -317,7 +317,7 @@ design: (work@dff_diffDataTypes) |vpiVariables: \_short_int_var: (work@dff_diffDataTypes.f), line:7:23, endln:7:24 |vpiParent: - \_module: work@dff_diffDataTypes (work@dff_diffDataTypes), file:${SURELOG_DIR}/tests/IODataTypes/dut.sv, line:1:1, endln:9:10 + \_module_inst: work@dff_diffDataTypes (work@dff_diffDataTypes), file:${SURELOG_DIR}/tests/IODataTypes/dut.sv, line:1:1, endln:9:10 |vpiTypespec: \_short_int_typespec: , line:7:7, endln:7:15 |vpiSigned:1 @@ -331,7 +331,7 @@ design: (work@dff_diffDataTypes) |vpiPort: \_port: (a), line:2:11, endln:2:12 |vpiParent: - \_module: work@dff_diffDataTypes (work@dff_diffDataTypes), file:${SURELOG_DIR}/tests/IODataTypes/dut.sv, line:1:1, endln:9:10 + \_module_inst: work@dff_diffDataTypes (work@dff_diffDataTypes), file:${SURELOG_DIR}/tests/IODataTypes/dut.sv, line:1:1, endln:9:10 |vpiName:a |vpiDirection:1 |vpiLowConn: @@ -346,11 +346,11 @@ design: (work@dff_diffDataTypes) \_int_typespec: , line:2:7, endln:2:10 |vpiSigned:1 |vpiInstance: - \_module: work@dff_diffDataTypes (work@dff_diffDataTypes), file:${SURELOG_DIR}/tests/IODataTypes/dut.sv, line:1:1, endln:9:10 + \_module_inst: work@dff_diffDataTypes (work@dff_diffDataTypes), file:${SURELOG_DIR}/tests/IODataTypes/dut.sv, line:1:1, endln:9:10 |vpiPort: \_port: (b), line:3:12, endln:3:13 |vpiParent: - \_module: work@dff_diffDataTypes (work@dff_diffDataTypes), file:${SURELOG_DIR}/tests/IODataTypes/dut.sv, line:1:1, endln:9:10 + \_module_inst: work@dff_diffDataTypes (work@dff_diffDataTypes), file:${SURELOG_DIR}/tests/IODataTypes/dut.sv, line:1:1, endln:9:10 |vpiName:b |vpiDirection:1 |vpiLowConn: @@ -365,11 +365,11 @@ design: (work@dff_diffDataTypes) \_byte_typespec: , line:3:7, endln:3:11 |vpiSigned:1 |vpiInstance: - \_module: work@dff_diffDataTypes (work@dff_diffDataTypes), file:${SURELOG_DIR}/tests/IODataTypes/dut.sv, line:1:1, endln:9:10 + \_module_inst: work@dff_diffDataTypes (work@dff_diffDataTypes), file:${SURELOG_DIR}/tests/IODataTypes/dut.sv, line:1:1, endln:9:10 |vpiPort: \_port: (c), line:4:16, endln:4:17 |vpiParent: - \_module: work@dff_diffDataTypes (work@dff_diffDataTypes), file:${SURELOG_DIR}/tests/IODataTypes/dut.sv, line:1:1, endln:9:10 + \_module_inst: work@dff_diffDataTypes (work@dff_diffDataTypes), file:${SURELOG_DIR}/tests/IODataTypes/dut.sv, line:1:1, endln:9:10 |vpiName:c |vpiDirection:1 |vpiLowConn: @@ -384,11 +384,11 @@ design: (work@dff_diffDataTypes) \_short_int_typespec: , line:4:7, endln:4:15 |vpiSigned:1 |vpiInstance: - \_module: work@dff_diffDataTypes (work@dff_diffDataTypes), file:${SURELOG_DIR}/tests/IODataTypes/dut.sv, line:1:1, endln:9:10 + \_module_inst: work@dff_diffDataTypes (work@dff_diffDataTypes), file:${SURELOG_DIR}/tests/IODataTypes/dut.sv, line:1:1, endln:9:10 |vpiPort: \_port: (d), line:5:15, endln:5:16 |vpiParent: - \_module: work@dff_diffDataTypes (work@dff_diffDataTypes), file:${SURELOG_DIR}/tests/IODataTypes/dut.sv, line:1:1, endln:9:10 + \_module_inst: work@dff_diffDataTypes (work@dff_diffDataTypes), file:${SURELOG_DIR}/tests/IODataTypes/dut.sv, line:1:1, endln:9:10 |vpiName:d |vpiDirection:1 |vpiLowConn: @@ -403,11 +403,11 @@ design: (work@dff_diffDataTypes) \_long_int_typespec: , line:5:7, endln:5:14 |vpiSigned:1 |vpiInstance: - \_module: work@dff_diffDataTypes (work@dff_diffDataTypes), file:${SURELOG_DIR}/tests/IODataTypes/dut.sv, line:1:1, endln:9:10 + \_module_inst: work@dff_diffDataTypes (work@dff_diffDataTypes), file:${SURELOG_DIR}/tests/IODataTypes/dut.sv, line:1:1, endln:9:10 |vpiPort: \_port: (e), line:6:15, endln:6:16 |vpiParent: - \_module: work@dff_diffDataTypes (work@dff_diffDataTypes), file:${SURELOG_DIR}/tests/IODataTypes/dut.sv, line:1:1, endln:9:10 + \_module_inst: work@dff_diffDataTypes (work@dff_diffDataTypes), file:${SURELOG_DIR}/tests/IODataTypes/dut.sv, line:1:1, endln:9:10 |vpiName:e |vpiDirection:1 |vpiLowConn: @@ -422,11 +422,11 @@ design: (work@dff_diffDataTypes) \_integer_typespec: , line:6:7, endln:6:14 |vpiSigned:1 |vpiInstance: - \_module: work@dff_diffDataTypes (work@dff_diffDataTypes), file:${SURELOG_DIR}/tests/IODataTypes/dut.sv, line:1:1, endln:9:10 + \_module_inst: work@dff_diffDataTypes (work@dff_diffDataTypes), file:${SURELOG_DIR}/tests/IODataTypes/dut.sv, line:1:1, endln:9:10 |vpiPort: \_port: (f), line:7:23, endln:7:24 |vpiParent: - \_module: work@dff_diffDataTypes (work@dff_diffDataTypes), file:${SURELOG_DIR}/tests/IODataTypes/dut.sv, line:1:1, endln:9:10 + \_module_inst: work@dff_diffDataTypes (work@dff_diffDataTypes), file:${SURELOG_DIR}/tests/IODataTypes/dut.sv, line:1:1, endln:9:10 |vpiName:f |vpiDirection:1 |vpiLowConn: @@ -441,7 +441,7 @@ design: (work@dff_diffDataTypes) \_short_int_typespec: , line:7:7, endln:7:15 |vpiSigned:1 |vpiInstance: - \_module: work@dff_diffDataTypes (work@dff_diffDataTypes), file:${SURELOG_DIR}/tests/IODataTypes/dut.sv, line:1:1, endln:9:10 + \_module_inst: work@dff_diffDataTypes (work@dff_diffDataTypes), file:${SURELOG_DIR}/tests/IODataTypes/dut.sv, line:1:1, endln:9:10 =================== [ FATAL] : 0 [ SYNTAX] : 0 diff --git a/tests/IfElseGen/IfElseGen.log b/tests/IfElseGen/IfElseGen.log index a1eff2ba8b..adc9bcc02a 100644 --- a/tests/IfElseGen/IfElseGen.log +++ b/tests/IfElseGen/IfElseGen.log @@ -195,7 +195,7 @@ design 1 gen_scope 4 gen_scope_array 4 int_typespec 2 -module 13 +module_inst 13 param_assign 4 parameter 4 === UHDM Object Stats End === @@ -208,7 +208,7 @@ design 1 gen_scope 6 gen_scope_array 6 int_typespec 2 -module 15 +module_inst 15 param_assign 4 parameter 4 === UHDM Object Stats End === @@ -225,26 +225,26 @@ design: (work@dut1) |vpiElaborated:1 |vpiName:work@dut1 |uhdmallModules: -\_module: work@GOOD1 (work@GOOD1), file:${SURELOG_DIR}/tests/IfElseGen/dut.sv, line:1:1, endln:2:10 +\_module_inst: work@GOOD1 (work@GOOD1), file:${SURELOG_DIR}/tests/IfElseGen/dut.sv, line:1:1, endln:2:10 |vpiParent: \_design: (work@dut1) |vpiFullName:work@GOOD1 |vpiDefName:work@GOOD1 |uhdmallModules: -\_module: work@GOOD2 (work@GOOD2), file:${SURELOG_DIR}/tests/IfElseGen/dut.sv, line:4:1, endln:5:10 +\_module_inst: work@GOOD2 (work@GOOD2), file:${SURELOG_DIR}/tests/IfElseGen/dut.sv, line:4:1, endln:5:10 |vpiParent: \_design: (work@dut1) |vpiFullName:work@GOOD2 |vpiDefName:work@GOOD2 |uhdmallModules: -\_module: work@dut1 (work@dut1), file:${SURELOG_DIR}/tests/IfElseGen/dut.sv, line:7:1, endln:14:10 +\_module_inst: work@dut1 (work@dut1), file:${SURELOG_DIR}/tests/IfElseGen/dut.sv, line:7:1, endln:14:10 |vpiParent: \_design: (work@dut1) |vpiFullName:work@dut1 |vpiParameter: \_parameter: (work@dut1.HasSndScratch), line:8:25, endln:8:38 |vpiParent: - \_module: work@dut1 (work@dut1), file:${SURELOG_DIR}/tests/IfElseGen/dut.sv, line:7:1, endln:14:10 + \_module_inst: work@dut1 (work@dut1), file:${SURELOG_DIR}/tests/IfElseGen/dut.sv, line:7:1, endln:14:10 |BIN:1 |vpiTypespec: \_bit_typespec: , line:8:12, endln:8:15 @@ -257,7 +257,7 @@ design: (work@dut1) |vpiParamAssign: \_param_assign: , line:8:25, endln:8:46 |vpiParent: - \_module: work@dut1 (work@dut1), file:${SURELOG_DIR}/tests/IfElseGen/dut.sv, line:7:1, endln:14:10 + \_module_inst: work@dut1 (work@dut1), file:${SURELOG_DIR}/tests/IfElseGen/dut.sv, line:7:1, endln:14:10 |vpiRhs: \_constant: , line:8:42, endln:8:46 |vpiDecompile:1'b1 @@ -270,14 +270,14 @@ design: (work@dut1) \_parameter: (work@dut1.HasSndScratch), line:8:25, endln:8:38 |vpiDefName:work@dut1 |uhdmallModules: -\_module: work@dut2 (work@dut2), file:${SURELOG_DIR}/tests/IfElseGen/dut.sv, line:17:1, endln:24:10 +\_module_inst: work@dut2 (work@dut2), file:${SURELOG_DIR}/tests/IfElseGen/dut.sv, line:17:1, endln:24:10 |vpiParent: \_design: (work@dut1) |vpiFullName:work@dut2 |vpiParameter: \_parameter: (work@dut2.HasSndScratch), line:18:25, endln:18:38 |vpiParent: - \_module: work@dut2 (work@dut2), file:${SURELOG_DIR}/tests/IfElseGen/dut.sv, line:17:1, endln:24:10 + \_module_inst: work@dut2 (work@dut2), file:${SURELOG_DIR}/tests/IfElseGen/dut.sv, line:17:1, endln:24:10 |BIN:0 |vpiTypespec: \_bit_typespec: , line:18:12, endln:18:15 @@ -290,7 +290,7 @@ design: (work@dut1) |vpiParamAssign: \_param_assign: , line:18:25, endln:18:46 |vpiParent: - \_module: work@dut2 (work@dut2), file:${SURELOG_DIR}/tests/IfElseGen/dut.sv, line:17:1, endln:24:10 + \_module_inst: work@dut2 (work@dut2), file:${SURELOG_DIR}/tests/IfElseGen/dut.sv, line:17:1, endln:24:10 |vpiRhs: \_constant: , line:18:42, endln:18:46 |vpiDecompile:1'b0 @@ -303,12 +303,12 @@ design: (work@dut1) \_parameter: (work@dut2.HasSndScratch), line:18:25, endln:18:38 |vpiDefName:work@dut2 |uhdmtopModules: -\_module: work@dut1 (work@dut1), file:${SURELOG_DIR}/tests/IfElseGen/dut.sv, line:7:1, endln:14:10 +\_module_inst: work@dut1 (work@dut1), file:${SURELOG_DIR}/tests/IfElseGen/dut.sv, line:7:1, endln:14:10 |vpiName:work@dut1 |vpiParameter: \_parameter: (work@dut1.HasSndScratch), line:8:25, endln:8:38 |vpiParent: - \_module: work@dut1 (work@dut1), file:${SURELOG_DIR}/tests/IfElseGen/dut.sv, line:7:1, endln:14:10 + \_module_inst: work@dut1 (work@dut1), file:${SURELOG_DIR}/tests/IfElseGen/dut.sv, line:7:1, endln:14:10 |BIN:1 |vpiTypespec: \_bit_typespec: , line:8:12, endln:8:15 @@ -321,7 +321,7 @@ design: (work@dut1) |vpiParamAssign: \_param_assign: , line:8:25, endln:8:46 |vpiParent: - \_module: work@dut1 (work@dut1), file:${SURELOG_DIR}/tests/IfElseGen/dut.sv, line:7:1, endln:14:10 + \_module_inst: work@dut1 (work@dut1), file:${SURELOG_DIR}/tests/IfElseGen/dut.sv, line:7:1, endln:14:10 |vpiRhs: \_constant: , line:8:42, endln:8:46 |vpiDecompile:1'b1 @@ -338,7 +338,7 @@ design: (work@dut1) |vpiGenScopeArray: \_gen_scope_array: (work@dut1.gen_rom_snd_scratch), line:9:1, endln:13:4 |vpiParent: - \_module: work@dut1 (work@dut1), file:${SURELOG_DIR}/tests/IfElseGen/dut.sv, line:7:1, endln:14:10 + \_module_inst: work@dut1 (work@dut1), file:${SURELOG_DIR}/tests/IfElseGen/dut.sv, line:7:1, endln:14:10 |vpiName:gen_rom_snd_scratch |vpiFullName:work@dut1.gen_rom_snd_scratch |vpiGenScope: @@ -346,8 +346,8 @@ design: (work@dut1) |vpiParent: \_gen_scope_array: (work@dut1.gen_rom_snd_scratch), line:9:1, endln:13:4 |vpiFullName:work@dut1.gen_rom_snd_scratch - |vpiModule: - \_module: work@GOOD1 (work@dut1.gen_rom_snd_scratch.cond_module), file:${SURELOG_DIR}/tests/IfElseGen/dut.sv, line:10:3, endln:10:23 + |vpiModuleInst: + \_module_inst: work@GOOD1 (work@dut1.gen_rom_snd_scratch.cond_module), file:${SURELOG_DIR}/tests/IfElseGen/dut.sv, line:10:3, endln:10:23 |vpiParent: \_gen_scope: (work@dut1.gen_rom_snd_scratch) |vpiName:cond_module @@ -356,12 +356,12 @@ design: (work@dut1) |vpiDefFile:${SURELOG_DIR}/tests/IfElseGen/dut.sv |vpiDefLineNo:1 |uhdmtopModules: -\_module: work@dut2 (work@dut2), file:${SURELOG_DIR}/tests/IfElseGen/dut.sv, line:17:1, endln:24:10 +\_module_inst: work@dut2 (work@dut2), file:${SURELOG_DIR}/tests/IfElseGen/dut.sv, line:17:1, endln:24:10 |vpiName:work@dut2 |vpiParameter: \_parameter: (work@dut2.HasSndScratch), line:18:25, endln:18:38 |vpiParent: - \_module: work@dut2 (work@dut2), file:${SURELOG_DIR}/tests/IfElseGen/dut.sv, line:17:1, endln:24:10 + \_module_inst: work@dut2 (work@dut2), file:${SURELOG_DIR}/tests/IfElseGen/dut.sv, line:17:1, endln:24:10 |BIN:0 |vpiTypespec: \_bit_typespec: , line:18:12, endln:18:15 @@ -374,7 +374,7 @@ design: (work@dut1) |vpiParamAssign: \_param_assign: , line:18:25, endln:18:46 |vpiParent: - \_module: work@dut2 (work@dut2), file:${SURELOG_DIR}/tests/IfElseGen/dut.sv, line:17:1, endln:24:10 + \_module_inst: work@dut2 (work@dut2), file:${SURELOG_DIR}/tests/IfElseGen/dut.sv, line:17:1, endln:24:10 |vpiRhs: \_constant: , line:18:42, endln:18:46 |vpiDecompile:1'b0 @@ -391,7 +391,7 @@ design: (work@dut1) |vpiGenScopeArray: \_gen_scope_array: (work@dut2.gen_rom_one_scratch), line:21:10, endln:23:4 |vpiParent: - \_module: work@dut2 (work@dut2), file:${SURELOG_DIR}/tests/IfElseGen/dut.sv, line:17:1, endln:24:10 + \_module_inst: work@dut2 (work@dut2), file:${SURELOG_DIR}/tests/IfElseGen/dut.sv, line:17:1, endln:24:10 |vpiName:gen_rom_one_scratch |vpiFullName:work@dut2.gen_rom_one_scratch |vpiGenScope: @@ -399,8 +399,8 @@ design: (work@dut1) |vpiParent: \_gen_scope_array: (work@dut2.gen_rom_one_scratch), line:21:10, endln:23:4 |vpiFullName:work@dut2.gen_rom_one_scratch - |vpiModule: - \_module: work@GOOD2 (work@dut2.gen_rom_one_scratch.cond_module), file:${SURELOG_DIR}/tests/IfElseGen/dut.sv, line:22:3, endln:22:23 + |vpiModuleInst: + \_module_inst: work@GOOD2 (work@dut2.gen_rom_one_scratch.cond_module), file:${SURELOG_DIR}/tests/IfElseGen/dut.sv, line:22:3, endln:22:23 |vpiParent: \_gen_scope: (work@dut2.gen_rom_one_scratch) |vpiName:cond_module diff --git a/tests/IfElseIf/test1/IfElseIf1.log b/tests/IfElseIf/test1/IfElseIf1.log index 355b787d9b..ebb2f89bfb 100644 --- a/tests/IfElseIf/test1/IfElseIf1.log +++ b/tests/IfElseIf/test1/IfElseIf1.log @@ -162,7 +162,7 @@ design 1 gen_scope 2 gen_scope_array 2 int_typespec 4 -module 7 +module_inst 7 operation 3 param_assign 4 parameter 4 @@ -175,7 +175,7 @@ design 1 gen_scope 3 gen_scope_array 3 int_typespec 4 -module 8 +module_inst 8 operation 3 param_assign 4 parameter 4 @@ -193,20 +193,20 @@ design: (work@axi) |vpiElaborated:1 |vpiName:work@axi |uhdmallModules: -\_module: work@GOOD (work@GOOD), file:${SURELOG_DIR}/tests/IfElseIf/test1/dut.sv, line:1:1, endln:2:10 +\_module_inst: work@GOOD (work@GOOD), file:${SURELOG_DIR}/tests/IfElseIf/test1/dut.sv, line:1:1, endln:2:10 |vpiParent: \_design: (work@axi) |vpiFullName:work@GOOD |vpiDefName:work@GOOD |uhdmallModules: -\_module: work@axi (work@axi), file:${SURELOG_DIR}/tests/IfElseIf/test1/dut.sv, line:4:1, endln:21:10 +\_module_inst: work@axi (work@axi), file:${SURELOG_DIR}/tests/IfElseIf/test1/dut.sv, line:4:1, endln:21:10 |vpiParent: \_design: (work@axi) |vpiFullName:work@axi |vpiParameter: \_parameter: (work@axi.j), line:6:15, endln:6:16 |vpiParent: - \_module: work@axi (work@axi), file:${SURELOG_DIR}/tests/IfElseIf/test1/dut.sv, line:4:1, endln:21:10 + \_module_inst: work@axi (work@axi), file:${SURELOG_DIR}/tests/IfElseIf/test1/dut.sv, line:4:1, endln:21:10 |UINT:6 |vpiTypespec: \_int_typespec: @@ -215,7 +215,7 @@ design: (work@axi) |vpiParameter: \_parameter: (work@axi.LOG_MASTER), line:7:15, endln:7:25 |vpiParent: - \_module: work@axi (work@axi), file:${SURELOG_DIR}/tests/IfElseIf/test1/dut.sv, line:4:1, endln:21:10 + \_module_inst: work@axi (work@axi), file:${SURELOG_DIR}/tests/IfElseIf/test1/dut.sv, line:4:1, endln:21:10 |UINT:5 |vpiTypespec: \_int_typespec: @@ -224,7 +224,7 @@ design: (work@axi) |vpiParamAssign: \_param_assign: , line:6:15, endln:6:20 |vpiParent: - \_module: work@axi (work@axi), file:${SURELOG_DIR}/tests/IfElseIf/test1/dut.sv, line:4:1, endln:21:10 + \_module_inst: work@axi (work@axi), file:${SURELOG_DIR}/tests/IfElseIf/test1/dut.sv, line:4:1, endln:21:10 |vpiRhs: \_constant: , line:6:19, endln:6:20 |vpiDecompile:6 @@ -238,7 +238,7 @@ design: (work@axi) |vpiParamAssign: \_param_assign: , line:7:15, endln:7:34 |vpiParent: - \_module: work@axi (work@axi), file:${SURELOG_DIR}/tests/IfElseIf/test1/dut.sv, line:4:1, endln:21:10 + \_module_inst: work@axi (work@axi), file:${SURELOG_DIR}/tests/IfElseIf/test1/dut.sv, line:4:1, endln:21:10 |vpiRhs: \_constant: , line:7:33, endln:7:34 |vpiDecompile:5 @@ -251,12 +251,12 @@ design: (work@axi) \_parameter: (work@axi.LOG_MASTER), line:7:15, endln:7:25 |vpiDefName:work@axi |uhdmtopModules: -\_module: work@axi (work@axi), file:${SURELOG_DIR}/tests/IfElseIf/test1/dut.sv, line:4:1, endln:21:10 +\_module_inst: work@axi (work@axi), file:${SURELOG_DIR}/tests/IfElseIf/test1/dut.sv, line:4:1, endln:21:10 |vpiName:work@axi |vpiParameter: \_parameter: (work@axi.j), line:6:15, endln:6:16 |vpiParent: - \_module: work@axi (work@axi), file:${SURELOG_DIR}/tests/IfElseIf/test1/dut.sv, line:4:1, endln:21:10 + \_module_inst: work@axi (work@axi), file:${SURELOG_DIR}/tests/IfElseIf/test1/dut.sv, line:4:1, endln:21:10 |UINT:6 |vpiTypespec: \_int_typespec: @@ -267,7 +267,7 @@ design: (work@axi) |vpiParameter: \_parameter: (work@axi.LOG_MASTER), line:7:15, endln:7:25 |vpiParent: - \_module: work@axi (work@axi), file:${SURELOG_DIR}/tests/IfElseIf/test1/dut.sv, line:4:1, endln:21:10 + \_module_inst: work@axi (work@axi), file:${SURELOG_DIR}/tests/IfElseIf/test1/dut.sv, line:4:1, endln:21:10 |UINT:5 |vpiTypespec: \_int_typespec: @@ -278,7 +278,7 @@ design: (work@axi) |vpiParamAssign: \_param_assign: , line:6:15, endln:6:20 |vpiParent: - \_module: work@axi (work@axi), file:${SURELOG_DIR}/tests/IfElseIf/test1/dut.sv, line:4:1, endln:21:10 + \_module_inst: work@axi (work@axi), file:${SURELOG_DIR}/tests/IfElseIf/test1/dut.sv, line:4:1, endln:21:10 |vpiRhs: \_constant: , line:6:19, endln:6:20 |vpiDecompile:6 @@ -292,7 +292,7 @@ design: (work@axi) |vpiParamAssign: \_param_assign: , line:7:15, endln:7:34 |vpiParent: - \_module: work@axi (work@axi), file:${SURELOG_DIR}/tests/IfElseIf/test1/dut.sv, line:4:1, endln:21:10 + \_module_inst: work@axi (work@axi), file:${SURELOG_DIR}/tests/IfElseIf/test1/dut.sv, line:4:1, endln:21:10 |vpiRhs: \_constant: , line:7:33, endln:7:34 |vpiDecompile:5 @@ -309,7 +309,7 @@ design: (work@axi) |vpiGenScopeArray: \_gen_scope_array: (work@axi.LEAF_NODES), line:16:16, endln:18:14 |vpiParent: - \_module: work@axi (work@axi), file:${SURELOG_DIR}/tests/IfElseIf/test1/dut.sv, line:4:1, endln:21:10 + \_module_inst: work@axi (work@axi), file:${SURELOG_DIR}/tests/IfElseIf/test1/dut.sv, line:4:1, endln:21:10 |vpiName:LEAF_NODES |vpiFullName:work@axi.LEAF_NODES |vpiGenScope: @@ -317,8 +317,8 @@ design: (work@axi) |vpiParent: \_gen_scope_array: (work@axi.LEAF_NODES), line:16:16, endln:18:14 |vpiFullName:work@axi.LEAF_NODES - |vpiModule: - \_module: work@GOOD (work@axi.LEAF_NODES.good), file:${SURELOG_DIR}/tests/IfElseIf/test1/dut.sv, line:17:14, endln:17:26 + |vpiModuleInst: + \_module_inst: work@GOOD (work@axi.LEAF_NODES.good), file:${SURELOG_DIR}/tests/IfElseIf/test1/dut.sv, line:17:14, endln:17:26 |vpiParent: \_gen_scope: (work@axi.LEAF_NODES) |vpiName:good diff --git a/tests/IfElseIf/test2/IfElseIf2.log b/tests/IfElseIf/test2/IfElseIf2.log index da32c37a3f..78b69baab3 100644 --- a/tests/IfElseIf/test2/IfElseIf2.log +++ b/tests/IfElseIf/test2/IfElseIf2.log @@ -162,7 +162,7 @@ design 1 gen_scope 2 gen_scope_array 2 int_typespec 4 -module 7 +module_inst 7 operation 3 param_assign 4 parameter 4 @@ -175,7 +175,7 @@ design 1 gen_scope 3 gen_scope_array 3 int_typespec 4 -module 8 +module_inst 8 operation 3 param_assign 4 parameter 4 @@ -193,20 +193,20 @@ design: (work@axi) |vpiElaborated:1 |vpiName:work@axi |uhdmallModules: -\_module: work@GOOD (work@GOOD), file:${SURELOG_DIR}/tests/IfElseIf/test2/dut.sv, line:1:1, endln:2:10 +\_module_inst: work@GOOD (work@GOOD), file:${SURELOG_DIR}/tests/IfElseIf/test2/dut.sv, line:1:1, endln:2:10 |vpiParent: \_design: (work@axi) |vpiFullName:work@GOOD |vpiDefName:work@GOOD |uhdmallModules: -\_module: work@axi (work@axi), file:${SURELOG_DIR}/tests/IfElseIf/test2/dut.sv, line:4:1, endln:20:10 +\_module_inst: work@axi (work@axi), file:${SURELOG_DIR}/tests/IfElseIf/test2/dut.sv, line:4:1, endln:20:10 |vpiParent: \_design: (work@axi) |vpiFullName:work@axi |vpiParameter: \_parameter: (work@axi.j), line:6:15, endln:6:16 |vpiParent: - \_module: work@axi (work@axi), file:${SURELOG_DIR}/tests/IfElseIf/test2/dut.sv, line:4:1, endln:20:10 + \_module_inst: work@axi (work@axi), file:${SURELOG_DIR}/tests/IfElseIf/test2/dut.sv, line:4:1, endln:20:10 |UINT:3 |vpiTypespec: \_int_typespec: @@ -215,7 +215,7 @@ design: (work@axi) |vpiParameter: \_parameter: (work@axi.LOG_MASTER), line:7:15, endln:7:25 |vpiParent: - \_module: work@axi (work@axi), file:${SURELOG_DIR}/tests/IfElseIf/test2/dut.sv, line:4:1, endln:20:10 + \_module_inst: work@axi (work@axi), file:${SURELOG_DIR}/tests/IfElseIf/test2/dut.sv, line:4:1, endln:20:10 |UINT:5 |vpiTypespec: \_int_typespec: @@ -224,7 +224,7 @@ design: (work@axi) |vpiParamAssign: \_param_assign: , line:6:15, endln:6:20 |vpiParent: - \_module: work@axi (work@axi), file:${SURELOG_DIR}/tests/IfElseIf/test2/dut.sv, line:4:1, endln:20:10 + \_module_inst: work@axi (work@axi), file:${SURELOG_DIR}/tests/IfElseIf/test2/dut.sv, line:4:1, endln:20:10 |vpiRhs: \_constant: , line:6:19, endln:6:20 |vpiDecompile:3 @@ -238,7 +238,7 @@ design: (work@axi) |vpiParamAssign: \_param_assign: , line:7:15, endln:7:34 |vpiParent: - \_module: work@axi (work@axi), file:${SURELOG_DIR}/tests/IfElseIf/test2/dut.sv, line:4:1, endln:20:10 + \_module_inst: work@axi (work@axi), file:${SURELOG_DIR}/tests/IfElseIf/test2/dut.sv, line:4:1, endln:20:10 |vpiRhs: \_constant: , line:7:33, endln:7:34 |vpiDecompile:5 @@ -251,12 +251,12 @@ design: (work@axi) \_parameter: (work@axi.LOG_MASTER), line:7:15, endln:7:25 |vpiDefName:work@axi |uhdmtopModules: -\_module: work@axi (work@axi), file:${SURELOG_DIR}/tests/IfElseIf/test2/dut.sv, line:4:1, endln:20:10 +\_module_inst: work@axi (work@axi), file:${SURELOG_DIR}/tests/IfElseIf/test2/dut.sv, line:4:1, endln:20:10 |vpiName:work@axi |vpiParameter: \_parameter: (work@axi.j), line:6:15, endln:6:16 |vpiParent: - \_module: work@axi (work@axi), file:${SURELOG_DIR}/tests/IfElseIf/test2/dut.sv, line:4:1, endln:20:10 + \_module_inst: work@axi (work@axi), file:${SURELOG_DIR}/tests/IfElseIf/test2/dut.sv, line:4:1, endln:20:10 |UINT:3 |vpiTypespec: \_int_typespec: @@ -267,7 +267,7 @@ design: (work@axi) |vpiParameter: \_parameter: (work@axi.LOG_MASTER), line:7:15, endln:7:25 |vpiParent: - \_module: work@axi (work@axi), file:${SURELOG_DIR}/tests/IfElseIf/test2/dut.sv, line:4:1, endln:20:10 + \_module_inst: work@axi (work@axi), file:${SURELOG_DIR}/tests/IfElseIf/test2/dut.sv, line:4:1, endln:20:10 |UINT:5 |vpiTypespec: \_int_typespec: @@ -278,7 +278,7 @@ design: (work@axi) |vpiParamAssign: \_param_assign: , line:6:15, endln:6:20 |vpiParent: - \_module: work@axi (work@axi), file:${SURELOG_DIR}/tests/IfElseIf/test2/dut.sv, line:4:1, endln:20:10 + \_module_inst: work@axi (work@axi), file:${SURELOG_DIR}/tests/IfElseIf/test2/dut.sv, line:4:1, endln:20:10 |vpiRhs: \_constant: , line:6:19, endln:6:20 |vpiDecompile:3 @@ -292,7 +292,7 @@ design: (work@axi) |vpiParamAssign: \_param_assign: , line:7:15, endln:7:34 |vpiParent: - \_module: work@axi (work@axi), file:${SURELOG_DIR}/tests/IfElseIf/test2/dut.sv, line:4:1, endln:20:10 + \_module_inst: work@axi (work@axi), file:${SURELOG_DIR}/tests/IfElseIf/test2/dut.sv, line:4:1, endln:20:10 |vpiRhs: \_constant: , line:7:33, endln:7:34 |vpiDecompile:5 @@ -309,7 +309,7 @@ design: (work@axi) |vpiGenScopeArray: \_gen_scope_array: (work@axi.MIDDLE_NODES), line:14:13, endln:14:25 |vpiParent: - \_module: work@axi (work@axi), file:${SURELOG_DIR}/tests/IfElseIf/test2/dut.sv, line:4:1, endln:20:10 + \_module_inst: work@axi (work@axi), file:${SURELOG_DIR}/tests/IfElseIf/test2/dut.sv, line:4:1, endln:20:10 |vpiName:MIDDLE_NODES |vpiFullName:work@axi.MIDDLE_NODES |vpiGenScope: @@ -317,8 +317,8 @@ design: (work@axi) |vpiParent: \_gen_scope_array: (work@axi.MIDDLE_NODES), line:14:13, endln:14:25 |vpiFullName:work@axi.MIDDLE_NODES - |vpiModule: - \_module: work@GOOD (work@axi.MIDDLE_NODES.good), file:${SURELOG_DIR}/tests/IfElseIf/test2/dut.sv, line:14:13, endln:14:25 + |vpiModuleInst: + \_module_inst: work@GOOD (work@axi.MIDDLE_NODES.good), file:${SURELOG_DIR}/tests/IfElseIf/test2/dut.sv, line:14:13, endln:14:25 |vpiParent: \_gen_scope: (work@axi.MIDDLE_NODES) |vpiName:good diff --git a/tests/IfElseIf/test3/IfElseIf3.log b/tests/IfElseIf/test3/IfElseIf3.log index 021210be82..4854b8b907 100644 --- a/tests/IfElseIf/test3/IfElseIf3.log +++ b/tests/IfElseIf/test3/IfElseIf3.log @@ -162,7 +162,7 @@ design 1 gen_scope 2 gen_scope_array 2 int_typespec 4 -module 7 +module_inst 7 operation 1 param_assign 4 parameter 4 @@ -175,7 +175,7 @@ design 1 gen_scope 3 gen_scope_array 3 int_typespec 4 -module 8 +module_inst 8 operation 1 param_assign 4 parameter 4 @@ -193,20 +193,20 @@ design: (work@axi) |vpiElaborated:1 |vpiName:work@axi |uhdmallModules: -\_module: work@GOOD (work@GOOD), file:${SURELOG_DIR}/tests/IfElseIf/test3/dut.sv, line:1:1, endln:2:10 +\_module_inst: work@GOOD (work@GOOD), file:${SURELOG_DIR}/tests/IfElseIf/test3/dut.sv, line:1:1, endln:2:10 |vpiParent: \_design: (work@axi) |vpiFullName:work@GOOD |vpiDefName:work@GOOD |uhdmallModules: -\_module: work@axi (work@axi), file:${SURELOG_DIR}/tests/IfElseIf/test3/dut.sv, line:4:1, endln:19:10 +\_module_inst: work@axi (work@axi), file:${SURELOG_DIR}/tests/IfElseIf/test3/dut.sv, line:4:1, endln:19:10 |vpiParent: \_design: (work@axi) |vpiFullName:work@axi |vpiParameter: \_parameter: (work@axi.j), line:6:15, endln:6:16 |vpiParent: - \_module: work@axi (work@axi), file:${SURELOG_DIR}/tests/IfElseIf/test3/dut.sv, line:4:1, endln:19:10 + \_module_inst: work@axi (work@axi), file:${SURELOG_DIR}/tests/IfElseIf/test3/dut.sv, line:4:1, endln:19:10 |UINT:0 |vpiTypespec: \_int_typespec: @@ -215,7 +215,7 @@ design: (work@axi) |vpiParameter: \_parameter: (work@axi.LOG_MASTER), line:7:15, endln:7:25 |vpiParent: - \_module: work@axi (work@axi), file:${SURELOG_DIR}/tests/IfElseIf/test3/dut.sv, line:4:1, endln:19:10 + \_module_inst: work@axi (work@axi), file:${SURELOG_DIR}/tests/IfElseIf/test3/dut.sv, line:4:1, endln:19:10 |UINT:5 |vpiTypespec: \_int_typespec: @@ -224,7 +224,7 @@ design: (work@axi) |vpiParamAssign: \_param_assign: , line:6:15, endln:6:20 |vpiParent: - \_module: work@axi (work@axi), file:${SURELOG_DIR}/tests/IfElseIf/test3/dut.sv, line:4:1, endln:19:10 + \_module_inst: work@axi (work@axi), file:${SURELOG_DIR}/tests/IfElseIf/test3/dut.sv, line:4:1, endln:19:10 |vpiRhs: \_constant: , line:6:19, endln:6:20 |vpiDecompile:0 @@ -238,7 +238,7 @@ design: (work@axi) |vpiParamAssign: \_param_assign: , line:7:15, endln:7:34 |vpiParent: - \_module: work@axi (work@axi), file:${SURELOG_DIR}/tests/IfElseIf/test3/dut.sv, line:4:1, endln:19:10 + \_module_inst: work@axi (work@axi), file:${SURELOG_DIR}/tests/IfElseIf/test3/dut.sv, line:4:1, endln:19:10 |vpiRhs: \_constant: , line:7:33, endln:7:34 |vpiDecompile:5 @@ -251,12 +251,12 @@ design: (work@axi) \_parameter: (work@axi.LOG_MASTER), line:7:15, endln:7:25 |vpiDefName:work@axi |uhdmtopModules: -\_module: work@axi (work@axi), file:${SURELOG_DIR}/tests/IfElseIf/test3/dut.sv, line:4:1, endln:19:10 +\_module_inst: work@axi (work@axi), file:${SURELOG_DIR}/tests/IfElseIf/test3/dut.sv, line:4:1, endln:19:10 |vpiName:work@axi |vpiParameter: \_parameter: (work@axi.j), line:6:15, endln:6:16 |vpiParent: - \_module: work@axi (work@axi), file:${SURELOG_DIR}/tests/IfElseIf/test3/dut.sv, line:4:1, endln:19:10 + \_module_inst: work@axi (work@axi), file:${SURELOG_DIR}/tests/IfElseIf/test3/dut.sv, line:4:1, endln:19:10 |UINT:0 |vpiTypespec: \_int_typespec: @@ -267,7 +267,7 @@ design: (work@axi) |vpiParameter: \_parameter: (work@axi.LOG_MASTER), line:7:15, endln:7:25 |vpiParent: - \_module: work@axi (work@axi), file:${SURELOG_DIR}/tests/IfElseIf/test3/dut.sv, line:4:1, endln:19:10 + \_module_inst: work@axi (work@axi), file:${SURELOG_DIR}/tests/IfElseIf/test3/dut.sv, line:4:1, endln:19:10 |UINT:5 |vpiTypespec: \_int_typespec: @@ -278,7 +278,7 @@ design: (work@axi) |vpiParamAssign: \_param_assign: , line:6:15, endln:6:20 |vpiParent: - \_module: work@axi (work@axi), file:${SURELOG_DIR}/tests/IfElseIf/test3/dut.sv, line:4:1, endln:19:10 + \_module_inst: work@axi (work@axi), file:${SURELOG_DIR}/tests/IfElseIf/test3/dut.sv, line:4:1, endln:19:10 |vpiRhs: \_constant: , line:6:19, endln:6:20 |vpiDecompile:0 @@ -292,7 +292,7 @@ design: (work@axi) |vpiParamAssign: \_param_assign: , line:7:15, endln:7:34 |vpiParent: - \_module: work@axi (work@axi), file:${SURELOG_DIR}/tests/IfElseIf/test3/dut.sv, line:4:1, endln:19:10 + \_module_inst: work@axi (work@axi), file:${SURELOG_DIR}/tests/IfElseIf/test3/dut.sv, line:4:1, endln:19:10 |vpiRhs: \_constant: , line:7:33, endln:7:34 |vpiDecompile:5 @@ -309,7 +309,7 @@ design: (work@axi) |vpiGenScopeArray: \_gen_scope_array: (work@axi.LAST_NODE), line:11:7, endln:16:10 |vpiParent: - \_module: work@axi (work@axi), file:${SURELOG_DIR}/tests/IfElseIf/test3/dut.sv, line:4:1, endln:19:10 + \_module_inst: work@axi (work@axi), file:${SURELOG_DIR}/tests/IfElseIf/test3/dut.sv, line:4:1, endln:19:10 |vpiName:LAST_NODE |vpiFullName:work@axi.LAST_NODE |vpiGenScope: @@ -317,8 +317,8 @@ design: (work@axi) |vpiParent: \_gen_scope_array: (work@axi.LAST_NODE), line:11:7, endln:16:10 |vpiFullName:work@axi.LAST_NODE - |vpiModule: - \_module: work@GOOD (work@axi.LAST_NODE.good), file:${SURELOG_DIR}/tests/IfElseIf/test3/dut.sv, line:12:10, endln:12:22 + |vpiModuleInst: + \_module_inst: work@GOOD (work@axi.LAST_NODE.good), file:${SURELOG_DIR}/tests/IfElseIf/test3/dut.sv, line:12:10, endln:12:22 |vpiParent: \_gen_scope: (work@axi.LAST_NODE) |vpiName:good diff --git a/tests/IfGenTypeBinding/IfGenTypeBinding.log b/tests/IfGenTypeBinding/IfGenTypeBinding.log index e7d5a28c9a..cecfdef697 100644 --- a/tests/IfGenTypeBinding/IfGenTypeBinding.log +++ b/tests/IfGenTypeBinding/IfGenTypeBinding.log @@ -447,7 +447,7 @@ io_decl 11 logic_net 1 logic_typespec 8 logic_var 1 -module 6 +module_inst 6 operation 2 package 5 param_assign 4 @@ -481,7 +481,7 @@ io_decl 22 logic_net 1 logic_typespec 8 logic_var 1 -module 6 +module_inst 6 operation 2 package 5 param_assign 4 @@ -637,7 +637,7 @@ design: (work@top) |vpiTypedef: \_struct_typespec: (ibex_pkg::pmp_cfg_t), line:3:11, endln:3:17 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/IfGenTypeBinding/dut.sv, line:13:1, endln:24:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/IfGenTypeBinding/dut.sv, line:13:1, endln:24:10 |vpiName:ibex_pkg::pmp_cfg_t |vpiInstance: \_package: ibex_pkg (ibex_pkg::), file:${SURELOG_DIR}/tests/IfGenTypeBinding/dut.sv, line:1:1, endln:11:11 @@ -1139,14 +1139,14 @@ design: (work@top) \_int_typespec: |vpiSigned:1 |uhdmallModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/IfGenTypeBinding/dut.sv, line:13:1, endln:24:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/IfGenTypeBinding/dut.sv, line:13:1, endln:24:10 |vpiParent: \_design: (work@top) |vpiFullName:work@top |vpiParameter: \_parameter: (work@top.PMPEnable), line:13:27, endln:13:36 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/IfGenTypeBinding/dut.sv, line:13:1, endln:24:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/IfGenTypeBinding/dut.sv, line:13:1, endln:24:10 |UINT:1 |vpiTypespec: \_bit_typespec: , line:13:23, endln:13:26 @@ -1158,7 +1158,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.PMPNumRegions), line:15:20, endln:15:33 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/IfGenTypeBinding/dut.sv, line:13:1, endln:24:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/IfGenTypeBinding/dut.sv, line:13:1, endln:24:10 |UINT:2 |vpiTypespec: \_int_typespec: , line:15:16, endln:15:19 @@ -1172,7 +1172,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:13:27, endln:13:40 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/IfGenTypeBinding/dut.sv, line:13:1, endln:24:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/IfGenTypeBinding/dut.sv, line:13:1, endln:24:10 |vpiRhs: \_constant: , line:13:39, endln:13:40 |vpiDecompile:1 @@ -1186,7 +1186,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:15:20, endln:15:37 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/IfGenTypeBinding/dut.sv, line:13:1, endln:24:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/IfGenTypeBinding/dut.sv, line:13:1, endln:24:10 |vpiRhs: \_constant: , line:15:36, endln:15:37 |vpiDecompile:2 @@ -1205,16 +1205,16 @@ design: (work@top) |vpiNet: \_logic_net: (work@top.pmp_cfg1), line:18:34, endln:18:42 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/IfGenTypeBinding/dut.sv, line:13:1, endln:24:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/IfGenTypeBinding/dut.sv, line:13:1, endln:24:10 |vpiName:pmp_cfg1 |vpiFullName:work@top.pmp_cfg1 |uhdmtopModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/IfGenTypeBinding/dut.sv, line:13:1, endln:24:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/IfGenTypeBinding/dut.sv, line:13:1, endln:24:10 |vpiName:work@top |vpiParameter: \_parameter: (work@top.PMPEnable), line:13:27, endln:13:36 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/IfGenTypeBinding/dut.sv, line:13:1, endln:24:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/IfGenTypeBinding/dut.sv, line:13:1, endln:24:10 |UINT:1 |vpiTypespec: \_bit_typespec: , line:13:23, endln:13:26 @@ -1226,7 +1226,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.PMPNumRegions), line:15:20, endln:15:33 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/IfGenTypeBinding/dut.sv, line:13:1, endln:24:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/IfGenTypeBinding/dut.sv, line:13:1, endln:24:10 |UINT:2 |vpiTypespec: \_int_typespec: , line:15:16, endln:15:19 @@ -1240,7 +1240,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:13:27, endln:13:40 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/IfGenTypeBinding/dut.sv, line:13:1, endln:24:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/IfGenTypeBinding/dut.sv, line:13:1, endln:24:10 |vpiRhs: \_constant: , line:13:39, endln:13:40 |vpiDecompile:1 @@ -1254,7 +1254,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:15:20, endln:15:37 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/IfGenTypeBinding/dut.sv, line:13:1, endln:24:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/IfGenTypeBinding/dut.sv, line:13:1, endln:24:10 |vpiRhs: \_constant: , line:15:36, endln:15:37 |vpiDecompile:2 @@ -1274,7 +1274,7 @@ design: (work@top) |vpiArrayNet: \_array_net: (work@top.pmp_cfg1), line:18:34, endln:18:42 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/IfGenTypeBinding/dut.sv, line:13:1, endln:24:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/IfGenTypeBinding/dut.sv, line:13:1, endln:24:10 |vpiSize:1 |vpiName:pmp_cfg1 |vpiFullName:work@top.pmp_cfg1 @@ -1319,7 +1319,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.g_pmp_registers), line:20:4, endln:22:7 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/IfGenTypeBinding/dut.sv, line:13:1, endln:24:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/IfGenTypeBinding/dut.sv, line:13:1, endln:24:10 |vpiName:g_pmp_registers |vpiFullName:work@top.g_pmp_registers |vpiGenScope: diff --git a/tests/IfGenenerate/test1/IfGen1.log b/tests/IfGenenerate/test1/IfGen1.log index f9e476f505..54134f9987 100644 --- a/tests/IfGenenerate/test1/IfGen1.log +++ b/tests/IfGenenerate/test1/IfGen1.log @@ -221,7 +221,7 @@ design 1 gen_scope 34 gen_scope_array 34 int_typespec 45 -module 7 +module_inst 7 operation 38 param_assign 8 parameter 24 @@ -236,7 +236,7 @@ design 1 gen_scope 51 gen_scope_array 51 int_typespec 45 -module 7 +module_inst 7 operation 38 param_assign 9 parameter 24 @@ -256,14 +256,14 @@ design: (work@lzc) |vpiElaborated:1 |vpiName:work@lzc |uhdmallModules: -\_module: work@lzc (work@lzc), file:${SURELOG_DIR}/tests/IfGenenerate/test1/dut1.sv, line:1:1, endln:19:16 +\_module_inst: work@lzc (work@lzc), file:${SURELOG_DIR}/tests/IfGenenerate/test1/dut1.sv, line:1:1, endln:19:16 |vpiParent: \_design: (work@lzc) |vpiFullName:work@lzc |vpiParameter: \_parameter: (work@lzc.WIDTH), line:2:26, endln:2:31 |vpiParent: - \_module: work@lzc (work@lzc), file:${SURELOG_DIR}/tests/IfGenenerate/test1/dut1.sv, line:1:1, endln:19:16 + \_module_inst: work@lzc (work@lzc), file:${SURELOG_DIR}/tests/IfGenenerate/test1/dut1.sv, line:1:1, endln:19:16 |UINT:64 |vpiTypespec: \_int_typespec: , line:2:13, endln:2:25 @@ -274,7 +274,7 @@ design: (work@lzc) |vpiParameter: \_parameter: (work@lzc.NUM_LEVELS), line:7:18, endln:7:28 |vpiParent: - \_module: work@lzc (work@lzc), file:${SURELOG_DIR}/tests/IfGenenerate/test1/dut1.sv, line:1:1, endln:19:16 + \_module_inst: work@lzc (work@lzc), file:${SURELOG_DIR}/tests/IfGenenerate/test1/dut1.sv, line:1:1, endln:19:16 |vpiTypespec: \_int_typespec: , line:7:14, endln:7:17 |vpiParent: @@ -287,7 +287,7 @@ design: (work@lzc) |vpiParameter: \_parameter: (work@lzc.level), line:8:19, endln:8:24 |vpiParent: - \_module: work@lzc (work@lzc), file:${SURELOG_DIR}/tests/IfGenenerate/test1/dut1.sv, line:1:1, endln:19:16 + \_module_inst: work@lzc (work@lzc), file:${SURELOG_DIR}/tests/IfGenenerate/test1/dut1.sv, line:1:1, endln:19:16 |UINT:4 |vpiTypespec: \_int_typespec: , line:8:14, endln:8:17 @@ -301,7 +301,7 @@ design: (work@lzc) |vpiParamAssign: \_param_assign: , line:2:26, endln:2:36 |vpiParent: - \_module: work@lzc (work@lzc), file:${SURELOG_DIR}/tests/IfGenenerate/test1/dut1.sv, line:1:1, endln:19:16 + \_module_inst: work@lzc (work@lzc), file:${SURELOG_DIR}/tests/IfGenenerate/test1/dut1.sv, line:1:1, endln:19:16 |vpiRhs: \_constant: , line:2:34, endln:2:36 |vpiDecompile:64 @@ -315,7 +315,7 @@ design: (work@lzc) |vpiParamAssign: \_param_assign: , line:7:18, endln:7:44 |vpiParent: - \_module: work@lzc (work@lzc), file:${SURELOG_DIR}/tests/IfGenenerate/test1/dut1.sv, line:1:1, endln:19:16 + \_module_inst: work@lzc (work@lzc), file:${SURELOG_DIR}/tests/IfGenenerate/test1/dut1.sv, line:1:1, endln:19:16 |vpiRhs: \_sys_func_call: ($clog2), line:7:31, endln:7:44 |vpiArgument: @@ -329,7 +329,7 @@ design: (work@lzc) |vpiParamAssign: \_param_assign: , line:8:19, endln:8:28 |vpiParent: - \_module: work@lzc (work@lzc), file:${SURELOG_DIR}/tests/IfGenenerate/test1/dut1.sv, line:1:1, endln:19:16 + \_module_inst: work@lzc (work@lzc), file:${SURELOG_DIR}/tests/IfGenenerate/test1/dut1.sv, line:1:1, endln:19:16 |vpiRhs: \_constant: , line:8:27, endln:8:28 |vpiDecompile:4 @@ -342,12 +342,12 @@ design: (work@lzc) \_parameter: (work@lzc.level), line:8:19, endln:8:24 |vpiDefName:work@lzc |uhdmtopModules: -\_module: work@lzc (work@lzc), file:${SURELOG_DIR}/tests/IfGenenerate/test1/dut1.sv, line:1:1, endln:19:16 +\_module_inst: work@lzc (work@lzc), file:${SURELOG_DIR}/tests/IfGenenerate/test1/dut1.sv, line:1:1, endln:19:16 |vpiName:work@lzc |vpiParameter: \_parameter: (work@lzc.WIDTH), line:2:26, endln:2:31 |vpiParent: - \_module: work@lzc (work@lzc), file:${SURELOG_DIR}/tests/IfGenenerate/test1/dut1.sv, line:1:1, endln:19:16 + \_module_inst: work@lzc (work@lzc), file:${SURELOG_DIR}/tests/IfGenenerate/test1/dut1.sv, line:1:1, endln:19:16 |UINT:64 |vpiTypespec: \_int_typespec: , line:2:13, endln:2:25 @@ -358,7 +358,7 @@ design: (work@lzc) |vpiParameter: \_parameter: (work@lzc.NUM_LEVELS), line:7:18, endln:7:28 |vpiParent: - \_module: work@lzc (work@lzc), file:${SURELOG_DIR}/tests/IfGenenerate/test1/dut1.sv, line:1:1, endln:19:16 + \_module_inst: work@lzc (work@lzc), file:${SURELOG_DIR}/tests/IfGenenerate/test1/dut1.sv, line:1:1, endln:19:16 |vpiTypespec: \_int_typespec: , line:7:14, endln:7:17 |vpiParent: @@ -371,7 +371,7 @@ design: (work@lzc) |vpiParameter: \_parameter: (work@lzc.level), line:8:19, endln:8:24 |vpiParent: - \_module: work@lzc (work@lzc), file:${SURELOG_DIR}/tests/IfGenenerate/test1/dut1.sv, line:1:1, endln:19:16 + \_module_inst: work@lzc (work@lzc), file:${SURELOG_DIR}/tests/IfGenenerate/test1/dut1.sv, line:1:1, endln:19:16 |UINT:4 |vpiTypespec: \_int_typespec: , line:8:14, endln:8:17 @@ -385,7 +385,7 @@ design: (work@lzc) |vpiParamAssign: \_param_assign: , line:2:26, endln:2:36 |vpiParent: - \_module: work@lzc (work@lzc), file:${SURELOG_DIR}/tests/IfGenenerate/test1/dut1.sv, line:1:1, endln:19:16 + \_module_inst: work@lzc (work@lzc), file:${SURELOG_DIR}/tests/IfGenenerate/test1/dut1.sv, line:1:1, endln:19:16 |vpiRhs: \_constant: , line:2:34, endln:2:36 |vpiDecompile:64 @@ -399,7 +399,7 @@ design: (work@lzc) |vpiParamAssign: \_param_assign: , line:7:18, endln:7:44 |vpiParent: - \_module: work@lzc (work@lzc), file:${SURELOG_DIR}/tests/IfGenenerate/test1/dut1.sv, line:1:1, endln:19:16 + \_module_inst: work@lzc (work@lzc), file:${SURELOG_DIR}/tests/IfGenenerate/test1/dut1.sv, line:1:1, endln:19:16 |vpiRhs: \_constant: , line:7:31, endln:7:44 |vpiDecompile:6 @@ -413,7 +413,7 @@ design: (work@lzc) |vpiParamAssign: \_param_assign: , line:8:19, endln:8:28 |vpiParent: - \_module: work@lzc (work@lzc), file:${SURELOG_DIR}/tests/IfGenenerate/test1/dut1.sv, line:1:1, endln:19:16 + \_module_inst: work@lzc (work@lzc), file:${SURELOG_DIR}/tests/IfGenenerate/test1/dut1.sv, line:1:1, endln:19:16 |vpiRhs: \_constant: , line:8:27, endln:8:28 |vpiDecompile:4 @@ -430,7 +430,7 @@ design: (work@lzc) |vpiGenScopeArray: \_gen_scope_array: (work@lzc.g_last_level), line:11:15, endln:16:8 |vpiParent: - \_module: work@lzc (work@lzc), file:${SURELOG_DIR}/tests/IfGenenerate/test1/dut1.sv, line:1:1, endln:19:16 + \_module_inst: work@lzc (work@lzc), file:${SURELOG_DIR}/tests/IfGenenerate/test1/dut1.sv, line:1:1, endln:19:16 |vpiName:g_last_level |vpiFullName:work@lzc.g_last_level |vpiGenScope: diff --git a/tests/IfGenenerate/test2/IfGen2.log b/tests/IfGenenerate/test2/IfGen2.log index d09c265473..a1b947ee83 100644 --- a/tests/IfGenenerate/test2/IfGen2.log +++ b/tests/IfGenenerate/test2/IfGen2.log @@ -222,7 +222,7 @@ design 1 gen_scope 34 gen_scope_array 34 int_typespec 45 -module 7 +module_inst 7 operation 38 param_assign 8 parameter 24 @@ -237,7 +237,7 @@ design 1 gen_scope 51 gen_scope_array 51 int_typespec 45 -module 7 +module_inst 7 operation 38 param_assign 9 parameter 24 @@ -257,14 +257,14 @@ design: (work@lzc) |vpiElaborated:1 |vpiName:work@lzc |uhdmallModules: -\_module: work@lzc (work@lzc), file:${SURELOG_DIR}/tests/IfGenenerate/test2/dut2.sv, line:1:1, endln:17:16 +\_module_inst: work@lzc (work@lzc), file:${SURELOG_DIR}/tests/IfGenenerate/test2/dut2.sv, line:1:1, endln:17:16 |vpiParent: \_design: (work@lzc) |vpiFullName:work@lzc |vpiParameter: \_parameter: (work@lzc.WIDTH), line:2:26, endln:2:31 |vpiParent: - \_module: work@lzc (work@lzc), file:${SURELOG_DIR}/tests/IfGenenerate/test2/dut2.sv, line:1:1, endln:17:16 + \_module_inst: work@lzc (work@lzc), file:${SURELOG_DIR}/tests/IfGenenerate/test2/dut2.sv, line:1:1, endln:17:16 |UINT:64 |vpiTypespec: \_int_typespec: , line:2:13, endln:2:25 @@ -275,7 +275,7 @@ design: (work@lzc) |vpiParameter: \_parameter: (work@lzc.NUM_LEVELS), line:7:18, endln:7:28 |vpiParent: - \_module: work@lzc (work@lzc), file:${SURELOG_DIR}/tests/IfGenenerate/test2/dut2.sv, line:1:1, endln:17:16 + \_module_inst: work@lzc (work@lzc), file:${SURELOG_DIR}/tests/IfGenenerate/test2/dut2.sv, line:1:1, endln:17:16 |vpiTypespec: \_int_typespec: , line:7:14, endln:7:17 |vpiParent: @@ -288,7 +288,7 @@ design: (work@lzc) |vpiParameter: \_parameter: (work@lzc.level), line:8:19, endln:8:24 |vpiParent: - \_module: work@lzc (work@lzc), file:${SURELOG_DIR}/tests/IfGenenerate/test2/dut2.sv, line:1:1, endln:17:16 + \_module_inst: work@lzc (work@lzc), file:${SURELOG_DIR}/tests/IfGenenerate/test2/dut2.sv, line:1:1, endln:17:16 |UINT:4 |vpiTypespec: \_int_typespec: , line:8:14, endln:8:17 @@ -302,7 +302,7 @@ design: (work@lzc) |vpiParamAssign: \_param_assign: , line:2:26, endln:2:36 |vpiParent: - \_module: work@lzc (work@lzc), file:${SURELOG_DIR}/tests/IfGenenerate/test2/dut2.sv, line:1:1, endln:17:16 + \_module_inst: work@lzc (work@lzc), file:${SURELOG_DIR}/tests/IfGenenerate/test2/dut2.sv, line:1:1, endln:17:16 |vpiRhs: \_constant: , line:2:34, endln:2:36 |vpiDecompile:64 @@ -316,7 +316,7 @@ design: (work@lzc) |vpiParamAssign: \_param_assign: , line:7:18, endln:7:44 |vpiParent: - \_module: work@lzc (work@lzc), file:${SURELOG_DIR}/tests/IfGenenerate/test2/dut2.sv, line:1:1, endln:17:16 + \_module_inst: work@lzc (work@lzc), file:${SURELOG_DIR}/tests/IfGenenerate/test2/dut2.sv, line:1:1, endln:17:16 |vpiRhs: \_sys_func_call: ($clog2), line:7:31, endln:7:44 |vpiArgument: @@ -330,7 +330,7 @@ design: (work@lzc) |vpiParamAssign: \_param_assign: , line:8:19, endln:8:28 |vpiParent: - \_module: work@lzc (work@lzc), file:${SURELOG_DIR}/tests/IfGenenerate/test2/dut2.sv, line:1:1, endln:17:16 + \_module_inst: work@lzc (work@lzc), file:${SURELOG_DIR}/tests/IfGenenerate/test2/dut2.sv, line:1:1, endln:17:16 |vpiRhs: \_constant: , line:8:27, endln:8:28 |vpiDecompile:4 @@ -343,12 +343,12 @@ design: (work@lzc) \_parameter: (work@lzc.level), line:8:19, endln:8:24 |vpiDefName:work@lzc |uhdmtopModules: -\_module: work@lzc (work@lzc), file:${SURELOG_DIR}/tests/IfGenenerate/test2/dut2.sv, line:1:1, endln:17:16 +\_module_inst: work@lzc (work@lzc), file:${SURELOG_DIR}/tests/IfGenenerate/test2/dut2.sv, line:1:1, endln:17:16 |vpiName:work@lzc |vpiParameter: \_parameter: (work@lzc.WIDTH), line:2:26, endln:2:31 |vpiParent: - \_module: work@lzc (work@lzc), file:${SURELOG_DIR}/tests/IfGenenerate/test2/dut2.sv, line:1:1, endln:17:16 + \_module_inst: work@lzc (work@lzc), file:${SURELOG_DIR}/tests/IfGenenerate/test2/dut2.sv, line:1:1, endln:17:16 |UINT:64 |vpiTypespec: \_int_typespec: , line:2:13, endln:2:25 @@ -359,7 +359,7 @@ design: (work@lzc) |vpiParameter: \_parameter: (work@lzc.NUM_LEVELS), line:7:18, endln:7:28 |vpiParent: - \_module: work@lzc (work@lzc), file:${SURELOG_DIR}/tests/IfGenenerate/test2/dut2.sv, line:1:1, endln:17:16 + \_module_inst: work@lzc (work@lzc), file:${SURELOG_DIR}/tests/IfGenenerate/test2/dut2.sv, line:1:1, endln:17:16 |vpiTypespec: \_int_typespec: , line:7:14, endln:7:17 |vpiParent: @@ -372,7 +372,7 @@ design: (work@lzc) |vpiParameter: \_parameter: (work@lzc.level), line:8:19, endln:8:24 |vpiParent: - \_module: work@lzc (work@lzc), file:${SURELOG_DIR}/tests/IfGenenerate/test2/dut2.sv, line:1:1, endln:17:16 + \_module_inst: work@lzc (work@lzc), file:${SURELOG_DIR}/tests/IfGenenerate/test2/dut2.sv, line:1:1, endln:17:16 |UINT:4 |vpiTypespec: \_int_typespec: , line:8:14, endln:8:17 @@ -386,7 +386,7 @@ design: (work@lzc) |vpiParamAssign: \_param_assign: , line:2:26, endln:2:36 |vpiParent: - \_module: work@lzc (work@lzc), file:${SURELOG_DIR}/tests/IfGenenerate/test2/dut2.sv, line:1:1, endln:17:16 + \_module_inst: work@lzc (work@lzc), file:${SURELOG_DIR}/tests/IfGenenerate/test2/dut2.sv, line:1:1, endln:17:16 |vpiRhs: \_constant: , line:2:34, endln:2:36 |vpiDecompile:64 @@ -400,7 +400,7 @@ design: (work@lzc) |vpiParamAssign: \_param_assign: , line:7:18, endln:7:44 |vpiParent: - \_module: work@lzc (work@lzc), file:${SURELOG_DIR}/tests/IfGenenerate/test2/dut2.sv, line:1:1, endln:17:16 + \_module_inst: work@lzc (work@lzc), file:${SURELOG_DIR}/tests/IfGenenerate/test2/dut2.sv, line:1:1, endln:17:16 |vpiRhs: \_constant: , line:7:31, endln:7:44 |vpiDecompile:6 @@ -414,7 +414,7 @@ design: (work@lzc) |vpiParamAssign: \_param_assign: , line:8:19, endln:8:28 |vpiParent: - \_module: work@lzc (work@lzc), file:${SURELOG_DIR}/tests/IfGenenerate/test2/dut2.sv, line:1:1, endln:17:16 + \_module_inst: work@lzc (work@lzc), file:${SURELOG_DIR}/tests/IfGenenerate/test2/dut2.sv, line:1:1, endln:17:16 |vpiRhs: \_constant: , line:8:27, endln:8:28 |vpiDecompile:4 @@ -431,7 +431,7 @@ design: (work@lzc) |vpiGenScopeArray: \_gen_scope_array: (work@lzc.else_level), line:11:15, endln:15:8 |vpiParent: - \_module: work@lzc (work@lzc), file:${SURELOG_DIR}/tests/IfGenenerate/test2/dut2.sv, line:1:1, endln:17:16 + \_module_inst: work@lzc (work@lzc), file:${SURELOG_DIR}/tests/IfGenenerate/test2/dut2.sv, line:1:1, endln:17:16 |vpiName:else_level |vpiFullName:work@lzc.else_level |vpiGenScope: diff --git a/tests/IfGenenerate/test3/IfGen3.log b/tests/IfGenenerate/test3/IfGen3.log index 45d0762740..871334af43 100644 --- a/tests/IfGenenerate/test3/IfGen3.log +++ b/tests/IfGenenerate/test3/IfGen3.log @@ -235,7 +235,7 @@ design 1 gen_scope 34 gen_scope_array 34 int_typespec 46 -module 7 +module_inst 7 operation 39 param_assign 8 parameter 24 @@ -250,7 +250,7 @@ design 1 gen_scope 51 gen_scope_array 51 int_typespec 46 -module 7 +module_inst 7 operation 39 param_assign 9 parameter 24 @@ -270,14 +270,14 @@ design: (work@lzc) |vpiElaborated:1 |vpiName:work@lzc |uhdmallModules: -\_module: work@lzc (work@lzc), file:${SURELOG_DIR}/tests/IfGenenerate/test3/dut3.sv, line:3:1, endln:21:16 +\_module_inst: work@lzc (work@lzc), file:${SURELOG_DIR}/tests/IfGenenerate/test3/dut3.sv, line:3:1, endln:21:16 |vpiParent: \_design: (work@lzc) |vpiFullName:work@lzc |vpiParameter: \_parameter: (work@lzc.WIDTH), line:4:26, endln:4:31 |vpiParent: - \_module: work@lzc (work@lzc), file:${SURELOG_DIR}/tests/IfGenenerate/test3/dut3.sv, line:3:1, endln:21:16 + \_module_inst: work@lzc (work@lzc), file:${SURELOG_DIR}/tests/IfGenenerate/test3/dut3.sv, line:3:1, endln:21:16 |UINT:64 |vpiTypespec: \_int_typespec: , line:4:13, endln:4:25 @@ -288,7 +288,7 @@ design: (work@lzc) |vpiParameter: \_parameter: (work@lzc.NUM_LEVELS), line:9:18, endln:9:28 |vpiParent: - \_module: work@lzc (work@lzc), file:${SURELOG_DIR}/tests/IfGenenerate/test3/dut3.sv, line:3:1, endln:21:16 + \_module_inst: work@lzc (work@lzc), file:${SURELOG_DIR}/tests/IfGenenerate/test3/dut3.sv, line:3:1, endln:21:16 |vpiTypespec: \_int_typespec: , line:9:14, endln:9:17 |vpiParent: @@ -301,7 +301,7 @@ design: (work@lzc) |vpiParameter: \_parameter: (work@lzc.level), line:10:19, endln:10:24 |vpiParent: - \_module: work@lzc (work@lzc), file:${SURELOG_DIR}/tests/IfGenenerate/test3/dut3.sv, line:3:1, endln:21:16 + \_module_inst: work@lzc (work@lzc), file:${SURELOG_DIR}/tests/IfGenenerate/test3/dut3.sv, line:3:1, endln:21:16 |UINT:4 |vpiTypespec: \_int_typespec: , line:10:14, endln:10:17 @@ -315,7 +315,7 @@ design: (work@lzc) |vpiParamAssign: \_param_assign: , line:4:26, endln:4:36 |vpiParent: - \_module: work@lzc (work@lzc), file:${SURELOG_DIR}/tests/IfGenenerate/test3/dut3.sv, line:3:1, endln:21:16 + \_module_inst: work@lzc (work@lzc), file:${SURELOG_DIR}/tests/IfGenenerate/test3/dut3.sv, line:3:1, endln:21:16 |vpiRhs: \_constant: , line:4:34, endln:4:36 |vpiDecompile:64 @@ -329,7 +329,7 @@ design: (work@lzc) |vpiParamAssign: \_param_assign: , line:9:18, endln:9:44 |vpiParent: - \_module: work@lzc (work@lzc), file:${SURELOG_DIR}/tests/IfGenenerate/test3/dut3.sv, line:3:1, endln:21:16 + \_module_inst: work@lzc (work@lzc), file:${SURELOG_DIR}/tests/IfGenenerate/test3/dut3.sv, line:3:1, endln:21:16 |vpiRhs: \_sys_func_call: ($clog2), line:9:31, endln:9:44 |vpiArgument: @@ -343,7 +343,7 @@ design: (work@lzc) |vpiParamAssign: \_param_assign: , line:10:19, endln:10:28 |vpiParent: - \_module: work@lzc (work@lzc), file:${SURELOG_DIR}/tests/IfGenenerate/test3/dut3.sv, line:3:1, endln:21:16 + \_module_inst: work@lzc (work@lzc), file:${SURELOG_DIR}/tests/IfGenenerate/test3/dut3.sv, line:3:1, endln:21:16 |vpiRhs: \_constant: , line:10:27, endln:10:28 |vpiDecompile:4 @@ -356,12 +356,12 @@ design: (work@lzc) \_parameter: (work@lzc.level), line:10:19, endln:10:24 |vpiDefName:work@lzc |uhdmtopModules: -\_module: work@lzc (work@lzc), file:${SURELOG_DIR}/tests/IfGenenerate/test3/dut3.sv, line:3:1, endln:21:16 +\_module_inst: work@lzc (work@lzc), file:${SURELOG_DIR}/tests/IfGenenerate/test3/dut3.sv, line:3:1, endln:21:16 |vpiName:work@lzc |vpiParameter: \_parameter: (work@lzc.WIDTH), line:4:26, endln:4:31 |vpiParent: - \_module: work@lzc (work@lzc), file:${SURELOG_DIR}/tests/IfGenenerate/test3/dut3.sv, line:3:1, endln:21:16 + \_module_inst: work@lzc (work@lzc), file:${SURELOG_DIR}/tests/IfGenenerate/test3/dut3.sv, line:3:1, endln:21:16 |UINT:64 |vpiTypespec: \_int_typespec: , line:4:13, endln:4:25 @@ -372,7 +372,7 @@ design: (work@lzc) |vpiParameter: \_parameter: (work@lzc.NUM_LEVELS), line:9:18, endln:9:28 |vpiParent: - \_module: work@lzc (work@lzc), file:${SURELOG_DIR}/tests/IfGenenerate/test3/dut3.sv, line:3:1, endln:21:16 + \_module_inst: work@lzc (work@lzc), file:${SURELOG_DIR}/tests/IfGenenerate/test3/dut3.sv, line:3:1, endln:21:16 |vpiTypespec: \_int_typespec: , line:9:14, endln:9:17 |vpiParent: @@ -385,7 +385,7 @@ design: (work@lzc) |vpiParameter: \_parameter: (work@lzc.level), line:10:19, endln:10:24 |vpiParent: - \_module: work@lzc (work@lzc), file:${SURELOG_DIR}/tests/IfGenenerate/test3/dut3.sv, line:3:1, endln:21:16 + \_module_inst: work@lzc (work@lzc), file:${SURELOG_DIR}/tests/IfGenenerate/test3/dut3.sv, line:3:1, endln:21:16 |UINT:4 |vpiTypespec: \_int_typespec: , line:10:14, endln:10:17 @@ -399,7 +399,7 @@ design: (work@lzc) |vpiParamAssign: \_param_assign: , line:4:26, endln:4:36 |vpiParent: - \_module: work@lzc (work@lzc), file:${SURELOG_DIR}/tests/IfGenenerate/test3/dut3.sv, line:3:1, endln:21:16 + \_module_inst: work@lzc (work@lzc), file:${SURELOG_DIR}/tests/IfGenenerate/test3/dut3.sv, line:3:1, endln:21:16 |vpiRhs: \_constant: , line:4:34, endln:4:36 |vpiDecompile:64 @@ -413,7 +413,7 @@ design: (work@lzc) |vpiParamAssign: \_param_assign: , line:9:18, endln:9:44 |vpiParent: - \_module: work@lzc (work@lzc), file:${SURELOG_DIR}/tests/IfGenenerate/test3/dut3.sv, line:3:1, endln:21:16 + \_module_inst: work@lzc (work@lzc), file:${SURELOG_DIR}/tests/IfGenenerate/test3/dut3.sv, line:3:1, endln:21:16 |vpiRhs: \_constant: , line:9:31, endln:9:44 |vpiDecompile:6 @@ -427,7 +427,7 @@ design: (work@lzc) |vpiParamAssign: \_param_assign: , line:10:19, endln:10:28 |vpiParent: - \_module: work@lzc (work@lzc), file:${SURELOG_DIR}/tests/IfGenenerate/test3/dut3.sv, line:3:1, endln:21:16 + \_module_inst: work@lzc (work@lzc), file:${SURELOG_DIR}/tests/IfGenenerate/test3/dut3.sv, line:3:1, endln:21:16 |vpiRhs: \_constant: , line:10:27, endln:10:28 |vpiDecompile:4 @@ -444,7 +444,7 @@ design: (work@lzc) |vpiGenScopeArray: \_gen_scope_array: (work@lzc.all_true), line:15:7, endln:15:40 |vpiParent: - \_module: work@lzc (work@lzc), file:${SURELOG_DIR}/tests/IfGenenerate/test3/dut3.sv, line:3:1, endln:21:16 + \_module_inst: work@lzc (work@lzc), file:${SURELOG_DIR}/tests/IfGenenerate/test3/dut3.sv, line:3:1, endln:21:16 |vpiName:all_true |vpiFullName:work@lzc.all_true |vpiGenScope: diff --git a/tests/Iff/Iff.log b/tests/Iff/Iff.log index 685d1571bb..b2f3b88e58 100644 --- a/tests/Iff/Iff.log +++ b/tests/Iff/Iff.log @@ -144,7 +144,7 @@ design 1 event_control 1 logic_net 11 logic_typespec 7 -module 3 +module_inst 3 operation 3 ref_obj 4 === UHDM Object Stats End === @@ -159,7 +159,7 @@ design 1 event_control 2 logic_net 11 logic_typespec 7 -module 3 +module_inst 3 operation 6 ref_obj 8 === UHDM Object Stats End === @@ -176,7 +176,7 @@ design: (work@block_tb) |vpiElaborated:1 |vpiName:work@block_tb |uhdmallModules: -\_module: work@block_tb (work@block_tb), file:${SURELOG_DIR}/tests/Iff/dut.sv, line:1:1, endln:8:10 +\_module_inst: work@block_tb (work@block_tb), file:${SURELOG_DIR}/tests/Iff/dut.sv, line:1:1, endln:8:10 |vpiParent: \_design: (work@block_tb) |vpiFullName:work@block_tb @@ -184,35 +184,35 @@ design: (work@block_tb) |vpiNet: \_logic_net: (work@block_tb.clk), line:2:7, endln:2:10 |vpiParent: - \_module: work@block_tb (work@block_tb), file:${SURELOG_DIR}/tests/Iff/dut.sv, line:1:1, endln:8:10 + \_module_inst: work@block_tb (work@block_tb), file:${SURELOG_DIR}/tests/Iff/dut.sv, line:1:1, endln:8:10 |vpiName:clk |vpiFullName:work@block_tb.clk |vpiNetType:1 |vpiNet: \_logic_net: (work@block_tb.en), line:3:7, endln:3:9 |vpiParent: - \_module: work@block_tb (work@block_tb), file:${SURELOG_DIR}/tests/Iff/dut.sv, line:1:1, endln:8:10 + \_module_inst: work@block_tb (work@block_tb), file:${SURELOG_DIR}/tests/Iff/dut.sv, line:1:1, endln:8:10 |vpiName:en |vpiFullName:work@block_tb.en |vpiNetType:1 |vpiNet: \_logic_net: (work@block_tb.a), line:4:7, endln:4:8 |vpiParent: - \_module: work@block_tb (work@block_tb), file:${SURELOG_DIR}/tests/Iff/dut.sv, line:1:1, endln:8:10 + \_module_inst: work@block_tb (work@block_tb), file:${SURELOG_DIR}/tests/Iff/dut.sv, line:1:1, endln:8:10 |vpiName:a |vpiFullName:work@block_tb.a |vpiNetType:1 |vpiNet: \_logic_net: (work@block_tb.y), line:5:6, endln:5:7 |vpiParent: - \_module: work@block_tb (work@block_tb), file:${SURELOG_DIR}/tests/Iff/dut.sv, line:1:1, endln:8:10 + \_module_inst: work@block_tb (work@block_tb), file:${SURELOG_DIR}/tests/Iff/dut.sv, line:1:1, endln:8:10 |vpiName:y |vpiFullName:work@block_tb.y |vpiNetType:48 |vpiProcess: \_always: , line:6:2, endln:7:18 |vpiParent: - \_module: work@block_tb (work@block_tb), file:${SURELOG_DIR}/tests/Iff/dut.sv, line:1:1, endln:8:10 + \_module_inst: work@block_tb (work@block_tb), file:${SURELOG_DIR}/tests/Iff/dut.sv, line:1:1, endln:8:10 |vpiStmt: \_event_control: , line:6:9, endln:6:35 |vpiParent: @@ -279,14 +279,14 @@ design: (work@block_tb) \_logic_net: (work@block_tb.y), line:5:6, endln:5:7 |vpiAlwaysType:1 |uhdmtopModules: -\_module: work@block_tb (work@block_tb), file:${SURELOG_DIR}/tests/Iff/dut.sv, line:1:1, endln:8:10 +\_module_inst: work@block_tb (work@block_tb), file:${SURELOG_DIR}/tests/Iff/dut.sv, line:1:1, endln:8:10 |vpiName:work@block_tb |vpiDefName:work@block_tb |vpiTop:1 |vpiNet: \_logic_net: (work@block_tb.clk), line:2:7, endln:2:10 |vpiParent: - \_module: work@block_tb (work@block_tb), file:${SURELOG_DIR}/tests/Iff/dut.sv, line:1:1, endln:8:10 + \_module_inst: work@block_tb (work@block_tb), file:${SURELOG_DIR}/tests/Iff/dut.sv, line:1:1, endln:8:10 |vpiTypespec: \_logic_typespec: , line:2:2, endln:2:6 |vpiName:clk @@ -295,7 +295,7 @@ design: (work@block_tb) |vpiNet: \_logic_net: (work@block_tb.en), line:3:7, endln:3:9 |vpiParent: - \_module: work@block_tb (work@block_tb), file:${SURELOG_DIR}/tests/Iff/dut.sv, line:1:1, endln:8:10 + \_module_inst: work@block_tb (work@block_tb), file:${SURELOG_DIR}/tests/Iff/dut.sv, line:1:1, endln:8:10 |vpiTypespec: \_logic_typespec: , line:3:2, endln:3:6 |vpiName:en @@ -304,7 +304,7 @@ design: (work@block_tb) |vpiNet: \_logic_net: (work@block_tb.a), line:4:7, endln:4:8 |vpiParent: - \_module: work@block_tb (work@block_tb), file:${SURELOG_DIR}/tests/Iff/dut.sv, line:1:1, endln:8:10 + \_module_inst: work@block_tb (work@block_tb), file:${SURELOG_DIR}/tests/Iff/dut.sv, line:1:1, endln:8:10 |vpiTypespec: \_logic_typespec: , line:4:2, endln:4:6 |vpiName:a @@ -313,7 +313,7 @@ design: (work@block_tb) |vpiNet: \_logic_net: (work@block_tb.y), line:5:6, endln:5:7 |vpiParent: - \_module: work@block_tb (work@block_tb), file:${SURELOG_DIR}/tests/Iff/dut.sv, line:1:1, endln:8:10 + \_module_inst: work@block_tb (work@block_tb), file:${SURELOG_DIR}/tests/Iff/dut.sv, line:1:1, endln:8:10 |vpiTypespec: \_logic_typespec: , line:5:2, endln:5:5 |vpiName:y @@ -323,7 +323,7 @@ design: (work@block_tb) |vpiProcess: \_always: , line:6:2, endln:7:18 |vpiParent: - \_module: work@block_tb (work@block_tb), file:${SURELOG_DIR}/tests/Iff/dut.sv, line:1:1, endln:8:10 + \_module_inst: work@block_tb (work@block_tb), file:${SURELOG_DIR}/tests/Iff/dut.sv, line:1:1, endln:8:10 |vpiStmt: \_event_control: , line:6:9, endln:6:35 |vpiParent: @@ -386,7 +386,7 @@ design: (work@block_tb) |vpiContAssign: \_cont_assign: , line:2:7, endln:2:10 |vpiParent: - \_module: work@block_tb (work@block_tb), file:${SURELOG_DIR}/tests/Iff/dut.sv, line:1:1, endln:8:10 + \_module_inst: work@block_tb (work@block_tb), file:${SURELOG_DIR}/tests/Iff/dut.sv, line:1:1, endln:8:10 |vpiNetDeclAssign:1 |vpiRhs: \_constant: , line:2:13, endln:2:14 @@ -401,7 +401,7 @@ design: (work@block_tb) |vpiContAssign: \_cont_assign: , line:3:7, endln:3:9 |vpiParent: - \_module: work@block_tb (work@block_tb), file:${SURELOG_DIR}/tests/Iff/dut.sv, line:1:1, endln:8:10 + \_module_inst: work@block_tb (work@block_tb), file:${SURELOG_DIR}/tests/Iff/dut.sv, line:1:1, endln:8:10 |vpiNetDeclAssign:1 |vpiRhs: \_constant: , line:3:12, endln:3:13 @@ -416,7 +416,7 @@ design: (work@block_tb) |vpiContAssign: \_cont_assign: , line:4:7, endln:4:8 |vpiParent: - \_module: work@block_tb (work@block_tb), file:${SURELOG_DIR}/tests/Iff/dut.sv, line:1:1, endln:8:10 + \_module_inst: work@block_tb (work@block_tb), file:${SURELOG_DIR}/tests/Iff/dut.sv, line:1:1, endln:8:10 |vpiNetDeclAssign:1 |vpiRhs: \_constant: , line:4:11, endln:4:12 diff --git a/tests/IllegalZeroValue/IllegalZeroValue.log b/tests/IllegalZeroValue/IllegalZeroValue.log index 0e3e4b58d2..e3a6c9c6f4 100644 --- a/tests/IllegalZeroValue/IllegalZeroValue.log +++ b/tests/IllegalZeroValue/IllegalZeroValue.log @@ -62,7 +62,7 @@ constant 3 design 1 logic_net 2 logic_typespec 1 -module 3 +module_inst 3 operation 1 range 1 === UHDM Object Stats End === @@ -74,7 +74,7 @@ constant 3 design 1 logic_net 2 logic_typespec 1 -module 3 +module_inst 3 operation 1 range 1 === UHDM Object Stats End === @@ -91,7 +91,7 @@ design: (work@test) |vpiElaborated:1 |vpiName:work@test |uhdmallModules: -\_module: work@test (work@test), file:${SURELOG_DIR}/tests/IllegalZeroValue/dut.sv, line:1:1, endln:5:10 +\_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/IllegalZeroValue/dut.sv, line:1:1, endln:5:10 |vpiParent: \_design: (work@test) |vpiFullName:work@test @@ -99,19 +99,19 @@ design: (work@test) |vpiNet: \_logic_net: (work@test.illegal), line:3:5, endln:3:12 |vpiParent: - \_module: work@test (work@test), file:${SURELOG_DIR}/tests/IllegalZeroValue/dut.sv, line:1:1, endln:5:10 + \_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/IllegalZeroValue/dut.sv, line:1:1, endln:5:10 |vpiName:illegal |vpiFullName:work@test.illegal |vpiNetType:48 |uhdmtopModules: -\_module: work@test (work@test), file:${SURELOG_DIR}/tests/IllegalZeroValue/dut.sv, line:1:1, endln:5:10 +\_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/IllegalZeroValue/dut.sv, line:1:1, endln:5:10 |vpiName:work@test |vpiDefName:work@test |vpiTop:1 |vpiArrayNet: \_array_net: (work@test.illegal), line:3:5, endln:3:12 |vpiParent: - \_module: work@test (work@test), file:${SURELOG_DIR}/tests/IllegalZeroValue/dut.sv, line:1:1, endln:5:10 + \_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/IllegalZeroValue/dut.sv, line:1:1, endln:5:10 |vpiName:illegal |vpiFullName:work@test.illegal |vpiRange: diff --git a/tests/ImplFuncArg/ImplFuncArg.log b/tests/ImplFuncArg/ImplFuncArg.log index b67f97cd3d..b09b8a4a7d 100644 --- a/tests/ImplFuncArg/ImplFuncArg.log +++ b/tests/ImplFuncArg/ImplFuncArg.log @@ -352,7 +352,7 @@ int_var 4 io_decl 13 logic_typespec 1 logic_var 2 -module 2 +module_inst 2 package 2 range 1 ref_obj 2 @@ -376,7 +376,7 @@ int_var 4 io_decl 26 logic_typespec 1 logic_var 2 -module 2 +module_inst 2 package 2 range 1 ref_obj 4 @@ -870,7 +870,7 @@ design: (work@fsm_2_always_block) \_int_typespec: |vpiSigned:1 |uhdmallModules: -\_module: work@fsm_2_always_block (work@fsm_2_always_block), file:${SURELOG_DIR}/tests/ImplFuncArg/dut.sv, line:1:1, endln:8:10 +\_module_inst: work@fsm_2_always_block (work@fsm_2_always_block), file:${SURELOG_DIR}/tests/ImplFuncArg/dut.sv, line:1:1, endln:8:10 |vpiParent: \_design: (work@fsm_2_always_block) |vpiFullName:work@fsm_2_always_block @@ -878,14 +878,14 @@ design: (work@fsm_2_always_block) |vpiTaskFunc: \_function: (work@fsm_2_always_block.stateAsmt), line:4:1, endln:6:12 |vpiParent: - \_module: work@fsm_2_always_block (work@fsm_2_always_block), file:${SURELOG_DIR}/tests/ImplFuncArg/dut.sv, line:1:1, endln:8:10 + \_module_inst: work@fsm_2_always_block (work@fsm_2_always_block), file:${SURELOG_DIR}/tests/ImplFuncArg/dut.sv, line:1:1, endln:8:10 |vpiName:stateAsmt |vpiFullName:work@fsm_2_always_block.stateAsmt |vpiVisibility:1 |vpiReturn: \_logic_var: |vpiParent: - \_module: work@fsm_2_always_block (work@fsm_2_always_block), file:${SURELOG_DIR}/tests/ImplFuncArg/dut.sv, line:1:1, endln:8:10 + \_module_inst: work@fsm_2_always_block (work@fsm_2_always_block), file:${SURELOG_DIR}/tests/ImplFuncArg/dut.sv, line:1:1, endln:8:10 |vpiIODecl: \_io_decl: (curr_state), line:4:30, endln:4:40 |vpiDirection:1 @@ -939,23 +939,23 @@ design: (work@fsm_2_always_block) |vpiActual: \_io_decl: (curr_state), line:4:30, endln:4:40 |vpiInstance: - \_module: work@fsm_2_always_block (work@fsm_2_always_block), file:${SURELOG_DIR}/tests/ImplFuncArg/dut.sv, line:1:1, endln:8:10 + \_module_inst: work@fsm_2_always_block (work@fsm_2_always_block), file:${SURELOG_DIR}/tests/ImplFuncArg/dut.sv, line:1:1, endln:8:10 |uhdmtopModules: -\_module: work@fsm_2_always_block (work@fsm_2_always_block), file:${SURELOG_DIR}/tests/ImplFuncArg/dut.sv, line:1:1, endln:8:10 +\_module_inst: work@fsm_2_always_block (work@fsm_2_always_block), file:${SURELOG_DIR}/tests/ImplFuncArg/dut.sv, line:1:1, endln:8:10 |vpiName:work@fsm_2_always_block |vpiDefName:work@fsm_2_always_block |vpiTop:1 |vpiTaskFunc: \_function: (work@fsm_2_always_block.stateAsmt), line:4:1, endln:6:12 |vpiParent: - \_module: work@fsm_2_always_block (work@fsm_2_always_block), file:${SURELOG_DIR}/tests/ImplFuncArg/dut.sv, line:1:1, endln:8:10 + \_module_inst: work@fsm_2_always_block (work@fsm_2_always_block), file:${SURELOG_DIR}/tests/ImplFuncArg/dut.sv, line:1:1, endln:8:10 |vpiName:stateAsmt |vpiFullName:work@fsm_2_always_block.stateAsmt |vpiVisibility:1 |vpiReturn: \_logic_var: |vpiParent: - \_module: work@fsm_2_always_block (work@fsm_2_always_block), file:${SURELOG_DIR}/tests/ImplFuncArg/dut.sv, line:1:1, endln:8:10 + \_module_inst: work@fsm_2_always_block (work@fsm_2_always_block), file:${SURELOG_DIR}/tests/ImplFuncArg/dut.sv, line:1:1, endln:8:10 |vpiIODecl: \_io_decl: (curr_state), line:4:30, endln:4:40 |vpiParent: @@ -995,7 +995,7 @@ design: (work@fsm_2_always_block) |vpiActual: \_io_decl: (curr_state), line:4:30, endln:4:40 |vpiInstance: - \_module: work@fsm_2_always_block (work@fsm_2_always_block), file:${SURELOG_DIR}/tests/ImplFuncArg/dut.sv, line:1:1, endln:8:10 + \_module_inst: work@fsm_2_always_block (work@fsm_2_always_block), file:${SURELOG_DIR}/tests/ImplFuncArg/dut.sv, line:1:1, endln:8:10 |vpiTopModule:1 =================== [ FATAL] : 0 diff --git a/tests/Implicit/Implicit.log b/tests/Implicit/Implicit.log index 30f77e82b6..b0b9d92297 100644 --- a/tests/Implicit/Implicit.log +++ b/tests/Implicit/Implicit.log @@ -103,7 +103,7 @@ design 1 gate 2 logic_net 10 logic_typespec 2 -module 2 +module_inst 2 port 5 prim_term 5 ref_obj 5 @@ -115,7 +115,7 @@ design 1 gate 2 logic_net 10 logic_typespec 2 -module 2 +module_inst 2 port 5 prim_term 5 ref_obj 5 @@ -133,7 +133,7 @@ design: (work@dff_from_nand), id:18 |vpiElaborated:1 |vpiName:work@dff_from_nand |uhdmallModules: -\_module: work@dff_from_nand (work@dff_from_nand), id:19, file:${SURELOG_DIR}/tests/Implicit/dut.sv, line:2:1, endln:8:10 +\_module_inst: work@dff_from_nand (work@dff_from_nand), id:19, file:${SURELOG_DIR}/tests/Implicit/dut.sv, line:2:1, endln:8:10 |vpiParent: \_design: (work@dff_from_nand), id:18 |vpiFullName:work@dff_from_nand @@ -141,40 +141,40 @@ design: (work@dff_from_nand), id:18 |vpiNet: \_logic_net: (work@dff_from_nand.Q), id:20, line:3:6, endln:3:7 |vpiParent: - \_module: work@dff_from_nand (work@dff_from_nand), id:19, file:${SURELOG_DIR}/tests/Implicit/dut.sv, line:2:1, endln:8:10 + \_module_inst: work@dff_from_nand (work@dff_from_nand), id:19, file:${SURELOG_DIR}/tests/Implicit/dut.sv, line:2:1, endln:8:10 |vpiName:Q |vpiFullName:work@dff_from_nand.Q |vpiNetType:1 |vpiNet: \_logic_net: (work@dff_from_nand.Q_BAR), id:21, line:3:8, endln:3:13 |vpiParent: - \_module: work@dff_from_nand (work@dff_from_nand), id:19, file:${SURELOG_DIR}/tests/Implicit/dut.sv, line:2:1, endln:8:10 + \_module_inst: work@dff_from_nand (work@dff_from_nand), id:19, file:${SURELOG_DIR}/tests/Implicit/dut.sv, line:2:1, endln:8:10 |vpiName:Q_BAR |vpiFullName:work@dff_from_nand.Q_BAR |vpiNetType:1 |vpiNet: \_logic_net: (work@dff_from_nand.D), id:22, line:4:6, endln:4:7 |vpiParent: - \_module: work@dff_from_nand (work@dff_from_nand), id:19, file:${SURELOG_DIR}/tests/Implicit/dut.sv, line:2:1, endln:8:10 + \_module_inst: work@dff_from_nand (work@dff_from_nand), id:19, file:${SURELOG_DIR}/tests/Implicit/dut.sv, line:2:1, endln:8:10 |vpiName:D |vpiFullName:work@dff_from_nand.D |vpiNetType:48 |vpiNet: \_logic_net: (work@dff_from_nand.CLK), id:23, line:4:8, endln:4:11 |vpiParent: - \_module: work@dff_from_nand (work@dff_from_nand), id:19, file:${SURELOG_DIR}/tests/Implicit/dut.sv, line:2:1, endln:8:10 + \_module_inst: work@dff_from_nand (work@dff_from_nand), id:19, file:${SURELOG_DIR}/tests/Implicit/dut.sv, line:2:1, endln:8:10 |vpiName:CLK |vpiFullName:work@dff_from_nand.CLK |vpiNetType:48 |uhdmtopModules: -\_module: work@dff_from_nand (work@dff_from_nand), id:24, file:${SURELOG_DIR}/tests/Implicit/dut.sv, line:2:1, endln:8:10 +\_module_inst: work@dff_from_nand (work@dff_from_nand), id:24, file:${SURELOG_DIR}/tests/Implicit/dut.sv, line:2:1, endln:8:10 |vpiName:work@dff_from_nand |vpiDefName:work@dff_from_nand |vpiTop:1 |vpiNet: \_logic_net: (work@dff_from_nand.Q), id:1, line:3:6, endln:3:7 |vpiParent: - \_module: work@dff_from_nand (work@dff_from_nand), id:24, file:${SURELOG_DIR}/tests/Implicit/dut.sv, line:2:1, endln:8:10 + \_module_inst: work@dff_from_nand (work@dff_from_nand), id:24, file:${SURELOG_DIR}/tests/Implicit/dut.sv, line:2:1, endln:8:10 |vpiTypespec: \_logic_typespec: , id:0, line:3:1, endln:3:5 |vpiName:Q @@ -183,7 +183,7 @@ design: (work@dff_from_nand), id:18 |vpiNet: \_logic_net: (work@dff_from_nand.Q_BAR), id:2, line:3:8, endln:3:13 |vpiParent: - \_module: work@dff_from_nand (work@dff_from_nand), id:24, file:${SURELOG_DIR}/tests/Implicit/dut.sv, line:2:1, endln:8:10 + \_module_inst: work@dff_from_nand (work@dff_from_nand), id:24, file:${SURELOG_DIR}/tests/Implicit/dut.sv, line:2:1, endln:8:10 |vpiTypespec: \_logic_typespec: , id:0, line:3:1, endln:3:5 |vpiName:Q_BAR @@ -192,7 +192,7 @@ design: (work@dff_from_nand), id:18 |vpiNet: \_logic_net: (work@dff_from_nand.D), id:4, line:4:6, endln:4:7 |vpiParent: - \_module: work@dff_from_nand (work@dff_from_nand), id:24, file:${SURELOG_DIR}/tests/Implicit/dut.sv, line:2:1, endln:8:10 + \_module_inst: work@dff_from_nand (work@dff_from_nand), id:24, file:${SURELOG_DIR}/tests/Implicit/dut.sv, line:2:1, endln:8:10 |vpiTypespec: \_logic_typespec: , id:3, line:4:1, endln:4:4 |vpiName:D @@ -201,7 +201,7 @@ design: (work@dff_from_nand), id:18 |vpiNet: \_logic_net: (work@dff_from_nand.CLK), id:5, line:4:8, endln:4:11 |vpiParent: - \_module: work@dff_from_nand (work@dff_from_nand), id:24, file:${SURELOG_DIR}/tests/Implicit/dut.sv, line:2:1, endln:8:10 + \_module_inst: work@dff_from_nand (work@dff_from_nand), id:24, file:${SURELOG_DIR}/tests/Implicit/dut.sv, line:2:1, endln:8:10 |vpiTypespec: \_logic_typespec: , id:3, line:4:1, endln:4:4 |vpiName:CLK @@ -210,14 +210,14 @@ design: (work@dff_from_nand), id:18 |vpiNet: \_logic_net: (work@dff_from_nand.X), id:8, line:6:10, endln:6:11 |vpiParent: - \_module: work@dff_from_nand (work@dff_from_nand), id:24, file:${SURELOG_DIR}/tests/Implicit/dut.sv, line:2:1, endln:8:10 + \_module_inst: work@dff_from_nand (work@dff_from_nand), id:24, file:${SURELOG_DIR}/tests/Implicit/dut.sv, line:2:1, endln:8:10 |vpiName:X |vpiFullName:work@dff_from_nand.X |vpiNetType:1 |vpiNet: \_logic_net: (work@dff_from_nand.X_BAR), id:15, line:7:6, endln:7:11 |vpiParent: - \_module: work@dff_from_nand (work@dff_from_nand), id:24, file:${SURELOG_DIR}/tests/Implicit/dut.sv, line:2:1, endln:8:10 + \_module_inst: work@dff_from_nand (work@dff_from_nand), id:24, file:${SURELOG_DIR}/tests/Implicit/dut.sv, line:2:1, endln:8:10 |vpiName:X_BAR |vpiFullName:work@dff_from_nand.X_BAR |vpiNetType:1 @@ -225,7 +225,7 @@ design: (work@dff_from_nand), id:18 |vpiPrimitive: \_gate: work@nand (work@dff_from_nand.U1), id:25, line:6:6, endln:6:18 |vpiParent: - \_module: work@dff_from_nand (work@dff_from_nand), id:24, file:${SURELOG_DIR}/tests/Implicit/dut.sv, line:2:1, endln:8:10 + \_module_inst: work@dff_from_nand (work@dff_from_nand), id:24, file:${SURELOG_DIR}/tests/Implicit/dut.sv, line:2:1, endln:8:10 |vpiDefName:work@nand |vpiName:U1 |vpiFullName:work@dff_from_nand.U1 @@ -274,7 +274,7 @@ design: (work@dff_from_nand), id:18 |vpiPrimitive: \_gate: work@not (work@dff_from_nand.), id:29, line:7:5, endln:7:15 |vpiParent: - \_module: work@dff_from_nand (work@dff_from_nand), id:24, file:${SURELOG_DIR}/tests/Implicit/dut.sv, line:2:1, endln:8:10 + \_module_inst: work@dff_from_nand (work@dff_from_nand), id:24, file:${SURELOG_DIR}/tests/Implicit/dut.sv, line:2:1, endln:8:10 |vpiDefName:work@not |vpiFullName:work@dff_from_nand. |vpiPrimType:8 diff --git a/tests/ImplicitArg/ImplicitArg.log b/tests/ImplicitArg/ImplicitArg.log index 5ab4a1e8a7..eee9a66938 100644 --- a/tests/ImplicitArg/ImplicitArg.log +++ b/tests/ImplicitArg/ImplicitArg.log @@ -78,7 +78,7 @@ function 1 io_decl 1 logic_typespec 2 logic_var 1 -module 2 +module_inst 2 range 1 return_stmt 1 === UHDM Object Stats End === @@ -91,7 +91,7 @@ function 2 io_decl 2 logic_typespec 2 logic_var 1 -module 2 +module_inst 2 range 1 return_stmt 2 === UHDM Object Stats End === @@ -108,7 +108,7 @@ design: (work@top) |vpiElaborated:1 |vpiName:work@top |uhdmallModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/ImplicitArg/dut.sv, line:1:1, endln:9:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ImplicitArg/dut.sv, line:1:1, endln:9:10 |vpiParent: \_design: (work@top) |vpiFullName:work@top @@ -116,7 +116,7 @@ design: (work@top) |vpiTaskFunc: \_function: (work@top.bsg_mul_booth), line:3:1, endln:7:12 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ImplicitArg/dut.sv, line:1:1, endln:9:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ImplicitArg/dut.sv, line:1:1, endln:9:10 |vpiName:bsg_mul_booth |vpiFullName:work@top.bsg_mul_booth |vpiVisibility:1 @@ -126,7 +126,7 @@ design: (work@top) |vpiTypespec: \_logic_typespec: , line:3:20, endln:3:25 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ImplicitArg/dut.sv, line:1:1, endln:9:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ImplicitArg/dut.sv, line:1:1, endln:9:10 |vpiIODecl: \_io_decl: (sdn), line:5:9, endln:5:12 |vpiDirection:1 @@ -164,16 +164,16 @@ design: (work@top) |UINT:1 |vpiConstType:9 |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ImplicitArg/dut.sv, line:1:1, endln:9:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ImplicitArg/dut.sv, line:1:1, endln:9:10 |uhdmtopModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/ImplicitArg/dut.sv, line:1:1, endln:9:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ImplicitArg/dut.sv, line:1:1, endln:9:10 |vpiName:work@top |vpiDefName:work@top |vpiTop:1 |vpiTaskFunc: \_function: (work@top.bsg_mul_booth), line:3:1, endln:7:12 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ImplicitArg/dut.sv, line:1:1, endln:9:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ImplicitArg/dut.sv, line:1:1, endln:9:10 |vpiName:bsg_mul_booth |vpiFullName:work@top.bsg_mul_booth |vpiVisibility:1 @@ -181,7 +181,7 @@ design: (work@top) |vpiReturn: \_logic_var: , line:3:20, endln:3:25 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ImplicitArg/dut.sv, line:1:1, endln:9:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ImplicitArg/dut.sv, line:1:1, endln:9:10 |vpiIODecl: \_io_decl: (sdn), line:5:9, endln:5:12 |vpiParent: @@ -197,7 +197,7 @@ design: (work@top) |vpiCondition: \_constant: , line:6:10, endln:6:11 |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ImplicitArg/dut.sv, line:1:1, endln:9:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ImplicitArg/dut.sv, line:1:1, endln:9:10 |vpiTopModule:1 =================== [ FATAL] : 0 diff --git a/tests/ImplicitFunc/ImplicitFunc.log b/tests/ImplicitFunc/ImplicitFunc.log index ab4b44ee45..d81b54e901 100644 --- a/tests/ImplicitFunc/ImplicitFunc.log +++ b/tests/ImplicitFunc/ImplicitFunc.log @@ -67,7 +67,7 @@ design 1 function 2 logic_typespec 1 logic_var 2 -module 2 +module_inst 2 range 1 === UHDM Object Stats End === [INF:UH0707] Elaborating UHDM... @@ -78,7 +78,7 @@ design 1 function 4 logic_typespec 1 logic_var 2 -module 2 +module_inst 2 range 1 === UHDM Object Stats End === [INF:UH0708] Writing UHDM DB: ${SURELOG_DIR}/build/regression/ImplicitFunc/slpp_all/surelog.uhdm ... @@ -94,7 +94,7 @@ design: (work@dut) |vpiElaborated:1 |vpiName:work@dut |uhdmallModules: -\_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/ImplicitFunc/dut.sv, line:1:1, endln:11:10 +\_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/ImplicitFunc/dut.sv, line:1:1, endln:11:10 |vpiParent: \_design: (work@dut) |vpiFullName:work@dut @@ -102,7 +102,7 @@ design: (work@dut) |vpiTaskFunc: \_function: (work@dut.foo), line:3:4, endln:5:15 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/ImplicitFunc/dut.sv, line:1:1, endln:11:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/ImplicitFunc/dut.sv, line:1:1, endln:11:10 |vpiName:foo |vpiFullName:work@dut.foo |vpiVisibility:1 @@ -129,53 +129,53 @@ design: (work@dut) |UINT:0 |vpiConstType:9 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/ImplicitFunc/dut.sv, line:1:1, endln:11:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/ImplicitFunc/dut.sv, line:1:1, endln:11:10 |vpiInstance: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/ImplicitFunc/dut.sv, line:1:1, endln:11:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/ImplicitFunc/dut.sv, line:1:1, endln:11:10 |vpiTaskFunc: \_function: (work@dut.bar), line:7:4, endln:9:15 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/ImplicitFunc/dut.sv, line:1:1, endln:11:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/ImplicitFunc/dut.sv, line:1:1, endln:11:10 |vpiName:bar |vpiFullName:work@dut.bar |vpiVisibility:1 |vpiReturn: \_logic_var: |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/ImplicitFunc/dut.sv, line:1:1, endln:11:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/ImplicitFunc/dut.sv, line:1:1, endln:11:10 |vpiInstance: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/ImplicitFunc/dut.sv, line:1:1, endln:11:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/ImplicitFunc/dut.sv, line:1:1, endln:11:10 |uhdmtopModules: -\_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/ImplicitFunc/dut.sv, line:1:1, endln:11:10 +\_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/ImplicitFunc/dut.sv, line:1:1, endln:11:10 |vpiName:work@dut |vpiDefName:work@dut |vpiTop:1 |vpiTaskFunc: \_function: (work@dut.foo), line:3:4, endln:5:15 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/ImplicitFunc/dut.sv, line:1:1, endln:11:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/ImplicitFunc/dut.sv, line:1:1, endln:11:10 |vpiName:foo |vpiFullName:work@dut.foo |vpiVisibility:1 |vpiReturn: \_logic_var: , line:3:13, endln:3:18 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/ImplicitFunc/dut.sv, line:1:1, endln:11:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/ImplicitFunc/dut.sv, line:1:1, endln:11:10 |vpiInstance: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/ImplicitFunc/dut.sv, line:1:1, endln:11:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/ImplicitFunc/dut.sv, line:1:1, endln:11:10 |vpiTaskFunc: \_function: (work@dut.bar), line:7:4, endln:9:15 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/ImplicitFunc/dut.sv, line:1:1, endln:11:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/ImplicitFunc/dut.sv, line:1:1, endln:11:10 |vpiName:bar |vpiFullName:work@dut.bar |vpiVisibility:1 |vpiReturn: \_logic_var: |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/ImplicitFunc/dut.sv, line:1:1, endln:11:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/ImplicitFunc/dut.sv, line:1:1, endln:11:10 |vpiInstance: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/ImplicitFunc/dut.sv, line:1:1, endln:11:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/ImplicitFunc/dut.sv, line:1:1, endln:11:10 |vpiTopModule:1 =================== [ FATAL] : 0 diff --git a/tests/ImplicitParam/ImplicitParam.log b/tests/ImplicitParam/ImplicitParam.log index 0f24632c50..9fc48a4011 100644 --- a/tests/ImplicitParam/ImplicitParam.log +++ b/tests/ImplicitParam/ImplicitParam.log @@ -90,7 +90,7 @@ design 1 int_typespec 7 int_var 1 logic_net 1 -module 5 +module_inst 5 param_assign 4 parameter 4 port 2 @@ -105,7 +105,7 @@ design 1 int_typespec 7 int_var 1 logic_net 1 -module 5 +module_inst 5 param_assign 4 parameter 4 port 3 @@ -125,14 +125,14 @@ design: (work@top) |vpiElaborated:1 |vpiName:work@top |uhdmallModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/ImplicitParam/dut.sv, line:1:1, endln:4:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ImplicitParam/dut.sv, line:1:1, endln:4:10 |vpiParent: \_design: (work@top) |vpiFullName:work@top |vpiParameter: \_parameter: (work@top.P), line:2:24, endln:2:25 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ImplicitParam/dut.sv, line:1:1, endln:4:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ImplicitParam/dut.sv, line:1:1, endln:4:10 |UINT:15 |vpiTypespec: \_int_typespec: , line:2:15, endln:2:23 @@ -144,7 +144,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.n), line:3:29, endln:3:30 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ImplicitParam/dut.sv, line:1:1, endln:4:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ImplicitParam/dut.sv, line:1:1, endln:4:10 |HEX:80000000 |vpiTypespec: \_int_typespec: , line:3:15, endln:3:21 @@ -175,7 +175,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:2:24, endln:2:30 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ImplicitParam/dut.sv, line:1:1, endln:4:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ImplicitParam/dut.sv, line:1:1, endln:4:10 |vpiRhs: \_constant: , line:2:28, endln:2:30 |vpiDecompile:15 @@ -189,7 +189,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:3:29, endln:3:46 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ImplicitParam/dut.sv, line:1:1, endln:4:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ImplicitParam/dut.sv, line:1:1, endln:4:10 |vpiRhs: \_constant: , line:3:33, endln:3:46 |vpiDecompile:32'h8000_0000 @@ -204,13 +204,13 @@ design: (work@top) |vpiNet: \_logic_net: (work@top.o), line:1:23, endln:1:24 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ImplicitParam/dut.sv, line:1:1, endln:4:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ImplicitParam/dut.sv, line:1:1, endln:4:10 |vpiName:o |vpiFullName:work@top.o |vpiPort: \_port: (o), line:1:23, endln:1:24 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ImplicitParam/dut.sv, line:1:1, endln:4:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ImplicitParam/dut.sv, line:1:1, endln:4:10 |vpiName:o |vpiDirection:2 |vpiLowConn: @@ -221,12 +221,12 @@ design: (work@top) \_int_typespec: , line:1:19, endln:1:22 |vpiSigned:1 |uhdmtopModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/ImplicitParam/dut.sv, line:1:1, endln:4:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ImplicitParam/dut.sv, line:1:1, endln:4:10 |vpiName:work@top |vpiVariables: \_int_var: (work@top.o), line:1:23, endln:1:24 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ImplicitParam/dut.sv, line:1:1, endln:4:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ImplicitParam/dut.sv, line:1:1, endln:4:10 |vpiTypespec: \_int_typespec: , line:1:19, endln:1:22 |vpiSigned:1 @@ -237,7 +237,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.P), line:2:24, endln:2:25 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ImplicitParam/dut.sv, line:1:1, endln:4:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ImplicitParam/dut.sv, line:1:1, endln:4:10 |UINT:15 |vpiTypespec: \_int_typespec: , line:2:15, endln:2:23 @@ -249,7 +249,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.n), line:3:29, endln:3:30 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ImplicitParam/dut.sv, line:1:1, endln:4:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ImplicitParam/dut.sv, line:1:1, endln:4:10 |HEX:80000000 |vpiTypespec: \_int_typespec: , line:3:15, endln:3:21 @@ -282,7 +282,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:2:24, endln:2:30 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ImplicitParam/dut.sv, line:1:1, endln:4:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ImplicitParam/dut.sv, line:1:1, endln:4:10 |vpiRhs: \_constant: , line:2:28, endln:2:30 |vpiDecompile:15 @@ -296,7 +296,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:3:29, endln:3:46 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ImplicitParam/dut.sv, line:1:1, endln:4:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ImplicitParam/dut.sv, line:1:1, endln:4:10 |vpiRhs: \_constant: , line:3:33, endln:3:46 |vpiDecompile:64'h80000000 @@ -313,7 +313,7 @@ design: (work@top) |vpiPort: \_port: (o), line:1:23, endln:1:24 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ImplicitParam/dut.sv, line:1:1, endln:4:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ImplicitParam/dut.sv, line:1:1, endln:4:10 |vpiName:o |vpiDirection:2 |vpiLowConn: @@ -328,7 +328,7 @@ design: (work@top) \_int_typespec: , line:1:19, endln:1:22 |vpiSigned:1 |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ImplicitParam/dut.sv, line:1:1, endln:4:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ImplicitParam/dut.sv, line:1:1, endln:4:10 =================== [ FATAL] : 0 [ SYNTAX] : 0 diff --git a/tests/ImplicitPort/ImplicitPort.log b/tests/ImplicitPort/ImplicitPort.log index 96b4b5b270..1ee997b9be 100644 --- a/tests/ImplicitPort/ImplicitPort.log +++ b/tests/ImplicitPort/ImplicitPort.log @@ -368,7 +368,7 @@ io_decl 11 logic_net 6 logic_typespec 7 logic_var 1 -module 3 +module_inst 3 operation 2 package 2 port 6 @@ -395,7 +395,7 @@ io_decl 22 logic_net 6 logic_typespec 7 logic_var 1 -module 3 +module_inst 3 operation 3 package 2 port 9 @@ -891,7 +891,7 @@ design: (work@add) \_int_typespec: |vpiSigned:1 |uhdmallModules: -\_module: work@add (work@add), file:${SURELOG_DIR}/tests/ImplicitPort/dut.sv, line:1:1, endln:6:10 +\_module_inst: work@add (work@add), file:${SURELOG_DIR}/tests/ImplicitPort/dut.sv, line:1:1, endln:6:10 |vpiParent: \_design: (work@add) |vpiFullName:work@add @@ -899,25 +899,25 @@ design: (work@add) |vpiNet: \_logic_net: (work@add.a), line:2:16, endln:2:17 |vpiParent: - \_module: work@add (work@add), file:${SURELOG_DIR}/tests/ImplicitPort/dut.sv, line:1:1, endln:6:10 + \_module_inst: work@add (work@add), file:${SURELOG_DIR}/tests/ImplicitPort/dut.sv, line:1:1, endln:6:10 |vpiName:a |vpiFullName:work@add.a |vpiNet: \_logic_net: (work@add.b), line:2:18, endln:2:19 |vpiParent: - \_module: work@add (work@add), file:${SURELOG_DIR}/tests/ImplicitPort/dut.sv, line:1:1, endln:6:10 + \_module_inst: work@add (work@add), file:${SURELOG_DIR}/tests/ImplicitPort/dut.sv, line:1:1, endln:6:10 |vpiName:b |vpiFullName:work@add.b |vpiNet: \_logic_net: (work@add.sum), line:3:24, endln:3:27 |vpiParent: - \_module: work@add (work@add), file:${SURELOG_DIR}/tests/ImplicitPort/dut.sv, line:1:1, endln:6:10 + \_module_inst: work@add (work@add), file:${SURELOG_DIR}/tests/ImplicitPort/dut.sv, line:1:1, endln:6:10 |vpiName:sum |vpiFullName:work@add.sum |vpiPort: \_port: (a), line:2:16, endln:2:17 |vpiParent: - \_module: work@add (work@add), file:${SURELOG_DIR}/tests/ImplicitPort/dut.sv, line:1:1, endln:6:10 + \_module_inst: work@add (work@add), file:${SURELOG_DIR}/tests/ImplicitPort/dut.sv, line:1:1, endln:6:10 |vpiName:a |vpiDirection:1 |vpiLowConn: @@ -947,7 +947,7 @@ design: (work@add) |vpiPort: \_port: (b), line:2:18, endln:2:19 |vpiParent: - \_module: work@add (work@add), file:${SURELOG_DIR}/tests/ImplicitPort/dut.sv, line:1:1, endln:6:10 + \_module_inst: work@add (work@add), file:${SURELOG_DIR}/tests/ImplicitPort/dut.sv, line:1:1, endln:6:10 |vpiName:b |vpiDirection:1 |vpiLowConn: @@ -977,7 +977,7 @@ design: (work@add) |vpiPort: \_port: (sum), line:3:24, endln:3:27 |vpiParent: - \_module: work@add (work@add), file:${SURELOG_DIR}/tests/ImplicitPort/dut.sv, line:1:1, endln:6:10 + \_module_inst: work@add (work@add), file:${SURELOG_DIR}/tests/ImplicitPort/dut.sv, line:1:1, endln:6:10 |vpiName:sum |vpiDirection:2 |vpiLowConn: @@ -1008,7 +1008,7 @@ design: (work@add) |vpiContAssign: \_cont_assign: , line:5:8, endln:5:19 |vpiParent: - \_module: work@add (work@add), file:${SURELOG_DIR}/tests/ImplicitPort/dut.sv, line:1:1, endln:6:10 + \_module_inst: work@add (work@add), file:${SURELOG_DIR}/tests/ImplicitPort/dut.sv, line:1:1, endln:6:10 |vpiRhs: \_operation: , line:5:14, endln:5:19 |vpiParent: @@ -1039,14 +1039,14 @@ design: (work@add) |vpiActual: \_logic_net: (work@add.sum), line:3:24, endln:3:27 |uhdmtopModules: -\_module: work@add (work@add), file:${SURELOG_DIR}/tests/ImplicitPort/dut.sv, line:1:1, endln:6:10 +\_module_inst: work@add (work@add), file:${SURELOG_DIR}/tests/ImplicitPort/dut.sv, line:1:1, endln:6:10 |vpiName:work@add |vpiDefName:work@add |vpiTop:1 |vpiNet: \_logic_net: (work@add.a), line:2:16, endln:2:17 |vpiParent: - \_module: work@add (work@add), file:${SURELOG_DIR}/tests/ImplicitPort/dut.sv, line:1:1, endln:6:10 + \_module_inst: work@add (work@add), file:${SURELOG_DIR}/tests/ImplicitPort/dut.sv, line:1:1, endln:6:10 |vpiTypespec: \_logic_typespec: , line:2:9, endln:2:15 |vpiRange: @@ -1072,7 +1072,7 @@ design: (work@add) |vpiNet: \_logic_net: (work@add.b), line:2:18, endln:2:19 |vpiParent: - \_module: work@add (work@add), file:${SURELOG_DIR}/tests/ImplicitPort/dut.sv, line:1:1, endln:6:10 + \_module_inst: work@add (work@add), file:${SURELOG_DIR}/tests/ImplicitPort/dut.sv, line:1:1, endln:6:10 |vpiTypespec: \_logic_typespec: , line:2:9, endln:2:15 |vpiName:b @@ -1080,7 +1080,7 @@ design: (work@add) |vpiNet: \_logic_net: (work@add.sum), line:3:24, endln:3:27 |vpiParent: - \_module: work@add (work@add), file:${SURELOG_DIR}/tests/ImplicitPort/dut.sv, line:1:1, endln:6:10 + \_module_inst: work@add (work@add), file:${SURELOG_DIR}/tests/ImplicitPort/dut.sv, line:1:1, endln:6:10 |vpiTypespec: \_logic_typespec: , line:3:10, endln:3:16 |vpiRange: @@ -1109,7 +1109,7 @@ design: (work@add) |vpiPort: \_port: (a), line:2:16, endln:2:17 |vpiParent: - \_module: work@add (work@add), file:${SURELOG_DIR}/tests/ImplicitPort/dut.sv, line:1:1, endln:6:10 + \_module_inst: work@add (work@add), file:${SURELOG_DIR}/tests/ImplicitPort/dut.sv, line:1:1, endln:6:10 |vpiName:a |vpiDirection:1 |vpiLowConn: @@ -1143,11 +1143,11 @@ design: (work@add) |UINT:0 |vpiConstType:9 |vpiInstance: - \_module: work@add (work@add), file:${SURELOG_DIR}/tests/ImplicitPort/dut.sv, line:1:1, endln:6:10 + \_module_inst: work@add (work@add), file:${SURELOG_DIR}/tests/ImplicitPort/dut.sv, line:1:1, endln:6:10 |vpiPort: \_port: (b), line:2:18, endln:2:19 |vpiParent: - \_module: work@add (work@add), file:${SURELOG_DIR}/tests/ImplicitPort/dut.sv, line:1:1, endln:6:10 + \_module_inst: work@add (work@add), file:${SURELOG_DIR}/tests/ImplicitPort/dut.sv, line:1:1, endln:6:10 |vpiName:b |vpiDirection:1 |vpiLowConn: @@ -1161,11 +1161,11 @@ design: (work@add) |vpiTypedef: \_logic_typespec: , line:2:9, endln:2:15 |vpiInstance: - \_module: work@add (work@add), file:${SURELOG_DIR}/tests/ImplicitPort/dut.sv, line:1:1, endln:6:10 + \_module_inst: work@add (work@add), file:${SURELOG_DIR}/tests/ImplicitPort/dut.sv, line:1:1, endln:6:10 |vpiPort: \_port: (sum), line:3:24, endln:3:27 |vpiParent: - \_module: work@add (work@add), file:${SURELOG_DIR}/tests/ImplicitPort/dut.sv, line:1:1, endln:6:10 + \_module_inst: work@add (work@add), file:${SURELOG_DIR}/tests/ImplicitPort/dut.sv, line:1:1, endln:6:10 |vpiName:sum |vpiDirection:2 |vpiLowConn: @@ -1200,11 +1200,11 @@ design: (work@add) |vpiConstType:9 |vpiSigned:1 |vpiInstance: - \_module: work@add (work@add), file:${SURELOG_DIR}/tests/ImplicitPort/dut.sv, line:1:1, endln:6:10 + \_module_inst: work@add (work@add), file:${SURELOG_DIR}/tests/ImplicitPort/dut.sv, line:1:1, endln:6:10 |vpiContAssign: \_cont_assign: , line:5:8, endln:5:19 |vpiParent: - \_module: work@add (work@add), file:${SURELOG_DIR}/tests/ImplicitPort/dut.sv, line:1:1, endln:6:10 + \_module_inst: work@add (work@add), file:${SURELOG_DIR}/tests/ImplicitPort/dut.sv, line:1:1, endln:6:10 |vpiRhs: \_operation: , line:5:14, endln:5:19 |vpiParent: diff --git a/tests/ImplicitPorts2/ImplicitPorts2.log b/tests/ImplicitPorts2/ImplicitPorts2.log index 27061ae981..86f65edd04 100644 --- a/tests/ImplicitPorts2/ImplicitPorts2.log +++ b/tests/ImplicitPorts2/ImplicitPorts2.log @@ -140,7 +140,7 @@ n<> u<107> t c<1> l<1:1> el<16:1> design 1 logic_net 10 logic_typespec 10 -module 5 +module_inst 5 port 6 ref_obj 9 === UHDM Object Stats End === @@ -150,7 +150,7 @@ ref_obj 9 design 1 logic_net 10 logic_typespec 10 -module 5 +module_inst 5 port 9 ref_obj 14 === UHDM Object Stats End === @@ -167,7 +167,7 @@ design: (work@implicit) |vpiElaborated:1 |vpiName:work@implicit |uhdmallModules: -\_module: work@dff (work@dff), file:${SURELOG_DIR}/tests/ImplicitPorts2/dut.sv, line:11:1, endln:15:10 +\_module_inst: work@dff (work@dff), file:${SURELOG_DIR}/tests/ImplicitPorts2/dut.sv, line:11:1, endln:15:10 |vpiParent: \_design: (work@implicit) |vpiFullName:work@dff @@ -175,26 +175,26 @@ design: (work@implicit) |vpiNet: \_logic_net: (work@dff.q), line:14:7, endln:14:8 |vpiParent: - \_module: work@dff (work@dff), file:${SURELOG_DIR}/tests/ImplicitPorts2/dut.sv, line:11:1, endln:15:10 + \_module_inst: work@dff (work@dff), file:${SURELOG_DIR}/tests/ImplicitPorts2/dut.sv, line:11:1, endln:15:10 |vpiName:q |vpiFullName:work@dff.q |vpiNetType:48 |vpiNet: \_logic_net: (work@dff.q_bar), line:11:16, endln:11:21 |vpiParent: - \_module: work@dff (work@dff), file:${SURELOG_DIR}/tests/ImplicitPorts2/dut.sv, line:11:1, endln:15:10 + \_module_inst: work@dff (work@dff), file:${SURELOG_DIR}/tests/ImplicitPorts2/dut.sv, line:11:1, endln:15:10 |vpiName:q_bar |vpiFullName:work@dff.q_bar |vpiNet: \_logic_net: (work@dff.clk), line:11:23, endln:11:26 |vpiParent: - \_module: work@dff (work@dff), file:${SURELOG_DIR}/tests/ImplicitPorts2/dut.sv, line:11:1, endln:15:10 + \_module_inst: work@dff (work@dff), file:${SURELOG_DIR}/tests/ImplicitPorts2/dut.sv, line:11:1, endln:15:10 |vpiName:clk |vpiFullName:work@dff.clk |vpiPort: \_port: (q), line:11:13, endln:11:14 |vpiParent: - \_module: work@dff (work@dff), file:${SURELOG_DIR}/tests/ImplicitPorts2/dut.sv, line:11:1, endln:15:10 + \_module_inst: work@dff (work@dff), file:${SURELOG_DIR}/tests/ImplicitPorts2/dut.sv, line:11:1, endln:15:10 |vpiName:q |vpiDirection:2 |vpiLowConn: @@ -206,7 +206,7 @@ design: (work@implicit) |vpiPort: \_port: (q_bar), line:11:16, endln:11:21 |vpiParent: - \_module: work@dff (work@dff), file:${SURELOG_DIR}/tests/ImplicitPorts2/dut.sv, line:11:1, endln:15:10 + \_module_inst: work@dff (work@dff), file:${SURELOG_DIR}/tests/ImplicitPorts2/dut.sv, line:11:1, endln:15:10 |vpiName:q_bar |vpiDirection:2 |vpiLowConn: @@ -218,7 +218,7 @@ design: (work@implicit) |vpiPort: \_port: (clk), line:11:23, endln:11:26 |vpiParent: - \_module: work@dff (work@dff), file:${SURELOG_DIR}/tests/ImplicitPorts2/dut.sv, line:11:1, endln:15:10 + \_module_inst: work@dff (work@dff), file:${SURELOG_DIR}/tests/ImplicitPorts2/dut.sv, line:11:1, endln:15:10 |vpiName:clk |vpiDirection:1 |vpiLowConn: @@ -228,7 +228,7 @@ design: (work@implicit) |vpiTypedef: \_logic_typespec: , line:12:9, endln:12:9 |uhdmallModules: -\_module: work@implicit (work@implicit), file:${SURELOG_DIR}/tests/ImplicitPorts2/dut.sv, line:1:1, endln:8:10 +\_module_inst: work@implicit (work@implicit), file:${SURELOG_DIR}/tests/ImplicitPorts2/dut.sv, line:1:1, endln:8:10 |vpiParent: \_design: (work@implicit) |vpiFullName:work@implicit @@ -236,26 +236,26 @@ design: (work@implicit) |vpiNet: \_logic_net: (work@implicit.clk), line:2:7, endln:2:10 |vpiParent: - \_module: work@implicit (work@implicit), file:${SURELOG_DIR}/tests/ImplicitPorts2/dut.sv, line:1:1, endln:8:10 + \_module_inst: work@implicit (work@implicit), file:${SURELOG_DIR}/tests/ImplicitPorts2/dut.sv, line:1:1, endln:8:10 |vpiName:clk |vpiFullName:work@implicit.clk |vpiNetType:48 |vpiNet: \_logic_net: (work@implicit.q), line:3:8, endln:3:9 |vpiParent: - \_module: work@implicit (work@implicit), file:${SURELOG_DIR}/tests/ImplicitPorts2/dut.sv, line:1:1, endln:8:10 + \_module_inst: work@implicit (work@implicit), file:${SURELOG_DIR}/tests/ImplicitPorts2/dut.sv, line:1:1, endln:8:10 |vpiName:q |vpiFullName:work@implicit.q |vpiNetType:1 |uhdmtopModules: -\_module: work@implicit (work@implicit), file:${SURELOG_DIR}/tests/ImplicitPorts2/dut.sv, line:1:1, endln:8:10 +\_module_inst: work@implicit (work@implicit), file:${SURELOG_DIR}/tests/ImplicitPorts2/dut.sv, line:1:1, endln:8:10 |vpiName:work@implicit |vpiDefName:work@implicit |vpiTop:1 |vpiNet: \_logic_net: (work@implicit.clk), line:2:7, endln:2:10 |vpiParent: - \_module: work@implicit (work@implicit), file:${SURELOG_DIR}/tests/ImplicitPorts2/dut.sv, line:1:1, endln:8:10 + \_module_inst: work@implicit (work@implicit), file:${SURELOG_DIR}/tests/ImplicitPorts2/dut.sv, line:1:1, endln:8:10 |vpiTypespec: \_logic_typespec: , line:2:3, endln:2:6 |vpiName:clk @@ -264,17 +264,17 @@ design: (work@implicit) |vpiNet: \_logic_net: (work@implicit.q), line:3:8, endln:3:9 |vpiParent: - \_module: work@implicit (work@implicit), file:${SURELOG_DIR}/tests/ImplicitPorts2/dut.sv, line:1:1, endln:8:10 + \_module_inst: work@implicit (work@implicit), file:${SURELOG_DIR}/tests/ImplicitPorts2/dut.sv, line:1:1, endln:8:10 |vpiTypespec: \_logic_typespec: , line:3:3, endln:3:7 |vpiName:q |vpiFullName:work@implicit.q |vpiNetType:1 |vpiTopModule:1 - |vpiModule: - \_module: work@dff (work@implicit.u0), file:${SURELOG_DIR}/tests/ImplicitPorts2/dut.sv, line:6:3, endln:6:20 + |vpiModuleInst: + \_module_inst: work@dff (work@implicit.u0), file:${SURELOG_DIR}/tests/ImplicitPorts2/dut.sv, line:6:3, endln:6:20 |vpiParent: - \_module: work@implicit (work@implicit), file:${SURELOG_DIR}/tests/ImplicitPorts2/dut.sv, line:1:1, endln:8:10 + \_module_inst: work@implicit (work@implicit), file:${SURELOG_DIR}/tests/ImplicitPorts2/dut.sv, line:1:1, endln:8:10 |vpiName:u0 |vpiFullName:work@implicit.u0 |vpiDefName:work@dff @@ -283,7 +283,7 @@ design: (work@implicit) |vpiNet: \_logic_net: (work@implicit.u0.q), line:14:7, endln:14:8 |vpiParent: - \_module: work@dff (work@implicit.u0), file:${SURELOG_DIR}/tests/ImplicitPorts2/dut.sv, line:6:3, endln:6:20 + \_module_inst: work@dff (work@implicit.u0), file:${SURELOG_DIR}/tests/ImplicitPorts2/dut.sv, line:6:3, endln:6:20 |vpiTypespec: \_logic_typespec: , line:14:3, endln:14:6 |vpiName:q @@ -292,7 +292,7 @@ design: (work@implicit) |vpiNet: \_logic_net: (work@implicit.u0.q_bar), line:11:16, endln:11:21 |vpiParent: - \_module: work@dff (work@implicit.u0), file:${SURELOG_DIR}/tests/ImplicitPorts2/dut.sv, line:6:3, endln:6:20 + \_module_inst: work@dff (work@implicit.u0), file:${SURELOG_DIR}/tests/ImplicitPorts2/dut.sv, line:6:3, endln:6:20 |vpiTypespec: \_logic_typespec: , line:13:10, endln:13:10 |vpiName:q_bar @@ -300,17 +300,17 @@ design: (work@implicit) |vpiNet: \_logic_net: (work@implicit.u0.clk), line:11:23, endln:11:26 |vpiParent: - \_module: work@dff (work@implicit.u0), file:${SURELOG_DIR}/tests/ImplicitPorts2/dut.sv, line:6:3, endln:6:20 + \_module_inst: work@dff (work@implicit.u0), file:${SURELOG_DIR}/tests/ImplicitPorts2/dut.sv, line:6:3, endln:6:20 |vpiTypespec: \_logic_typespec: , line:12:9, endln:12:9 |vpiName:clk |vpiFullName:work@implicit.u0.clk |vpiInstance: - \_module: work@implicit (work@implicit), file:${SURELOG_DIR}/tests/ImplicitPorts2/dut.sv, line:1:1, endln:8:10 + \_module_inst: work@implicit (work@implicit), file:${SURELOG_DIR}/tests/ImplicitPorts2/dut.sv, line:1:1, endln:8:10 |vpiPort: \_port: (q), line:11:13, endln:11:14 |vpiParent: - \_module: work@dff (work@implicit.u0), file:${SURELOG_DIR}/tests/ImplicitPorts2/dut.sv, line:6:3, endln:6:20 + \_module_inst: work@dff (work@implicit.u0), file:${SURELOG_DIR}/tests/ImplicitPorts2/dut.sv, line:6:3, endln:6:20 |vpiName:q |vpiDirection:2 |vpiHighConn: @@ -332,11 +332,11 @@ design: (work@implicit) |vpiTypedef: \_logic_typespec: , line:13:10, endln:13:10 |vpiInstance: - \_module: work@dff (work@implicit.u0), file:${SURELOG_DIR}/tests/ImplicitPorts2/dut.sv, line:6:3, endln:6:20 + \_module_inst: work@dff (work@implicit.u0), file:${SURELOG_DIR}/tests/ImplicitPorts2/dut.sv, line:6:3, endln:6:20 |vpiPort: \_port: (q_bar), line:11:16, endln:11:21 |vpiParent: - \_module: work@dff (work@implicit.u0), file:${SURELOG_DIR}/tests/ImplicitPorts2/dut.sv, line:6:3, endln:6:20 + \_module_inst: work@dff (work@implicit.u0), file:${SURELOG_DIR}/tests/ImplicitPorts2/dut.sv, line:6:3, endln:6:20 |vpiName:q_bar |vpiDirection:2 |vpiLowConn: @@ -350,11 +350,11 @@ design: (work@implicit) |vpiTypedef: \_logic_typespec: , line:13:10, endln:13:10 |vpiInstance: - \_module: work@dff (work@implicit.u0), file:${SURELOG_DIR}/tests/ImplicitPorts2/dut.sv, line:6:3, endln:6:20 + \_module_inst: work@dff (work@implicit.u0), file:${SURELOG_DIR}/tests/ImplicitPorts2/dut.sv, line:6:3, endln:6:20 |vpiPort: \_port: (clk), line:11:23, endln:11:26 |vpiParent: - \_module: work@dff (work@implicit.u0), file:${SURELOG_DIR}/tests/ImplicitPorts2/dut.sv, line:6:3, endln:6:20 + \_module_inst: work@dff (work@implicit.u0), file:${SURELOG_DIR}/tests/ImplicitPorts2/dut.sv, line:6:3, endln:6:20 |vpiName:clk |vpiDirection:1 |vpiHighConn: @@ -376,7 +376,7 @@ design: (work@implicit) |vpiTypedef: \_logic_typespec: , line:12:9, endln:12:9 |vpiInstance: - \_module: work@dff (work@implicit.u0), file:${SURELOG_DIR}/tests/ImplicitPorts2/dut.sv, line:6:3, endln:6:20 + \_module_inst: work@dff (work@implicit.u0), file:${SURELOG_DIR}/tests/ImplicitPorts2/dut.sv, line:6:3, endln:6:20 =================== [ FATAL] : 0 [ SYNTAX] : 0 diff --git a/tests/ImplicitVarType/ImplicitVarType.log b/tests/ImplicitVarType/ImplicitVarType.log index 37e6b9b90a..8634dccb3e 100644 --- a/tests/ImplicitVarType/ImplicitVarType.log +++ b/tests/ImplicitVarType/ImplicitVarType.log @@ -39,7 +39,7 @@ design 1 function 1 io_decl 1 logic_typespec 1 -module 2 +module_inst 2 range 1 === UHDM Object Stats End === [INF:UH0708] Writing UHDM DB: ${SURELOG_DIR}/build/regression/ImplicitVarType/slpp_unit/surelog.uhdm ... @@ -54,7 +54,7 @@ range 1 design: (work@spidpi) |vpiName:work@spidpi |uhdmallModules: -\_module: work@spidpi (work@spidpi), file:${SURELOG_DIR}/tests/ImplicitVarType/dut.sv, line:1:1, endln:4:10 +\_module_inst: work@spidpi (work@spidpi), file:${SURELOG_DIR}/tests/ImplicitVarType/dut.sv, line:1:1, endln:4:10 |vpiParent: \_design: (work@spidpi) |vpiFullName:work@spidpi @@ -62,7 +62,7 @@ design: (work@spidpi) |vpiTaskFunc: \_function: (work@spidpi.tick), line:2:3, endln:3:37 |vpiParent: - \_module: work@spidpi (work@spidpi), file:${SURELOG_DIR}/tests/ImplicitVarType/dut.sv, line:1:1, endln:4:10 + \_module_inst: work@spidpi (work@spidpi), file:${SURELOG_DIR}/tests/ImplicitVarType/dut.sv, line:1:1, endln:4:10 |vpiName:tick |vpiFullName:work@spidpi.tick |vpiAccessType:4 @@ -75,7 +75,7 @@ design: (work@spidpi) |vpiSigned:1 |vpiSigned:1 |vpiParent: - \_module: work@spidpi (work@spidpi), file:${SURELOG_DIR}/tests/ImplicitVarType/dut.sv, line:1:1, endln:4:10 + \_module_inst: work@spidpi (work@spidpi), file:${SURELOG_DIR}/tests/ImplicitVarType/dut.sv, line:1:1, endln:4:10 |vpiIODecl: \_io_decl: (d2p_data), line:3:27, endln:3:35 |vpiDirection:1 @@ -101,9 +101,9 @@ design: (work@spidpi) |UINT:0 |vpiConstType:9 |vpiInstance: - \_module: work@spidpi (work@spidpi), file:${SURELOG_DIR}/tests/ImplicitVarType/dut.sv, line:1:1, endln:4:10 + \_module_inst: work@spidpi (work@spidpi), file:${SURELOG_DIR}/tests/ImplicitVarType/dut.sv, line:1:1, endln:4:10 |uhdmtopModules: -\_module: work@spidpi (work@spidpi), file:${SURELOG_DIR}/tests/ImplicitVarType/dut.sv, line:1:1, endln:4:10 +\_module_inst: work@spidpi (work@spidpi), file:${SURELOG_DIR}/tests/ImplicitVarType/dut.sv, line:1:1, endln:4:10 |vpiName:work@spidpi |vpiDefName:work@spidpi |vpiTop:1 diff --git a/tests/ImportBinding/ImportBinding.log b/tests/ImportBinding/ImportBinding.log index 424ca8bf30..d5f0906e32 100644 --- a/tests/ImportBinding/ImportBinding.log +++ b/tests/ImportBinding/ImportBinding.log @@ -133,7 +133,7 @@ enum_typespec 13 import_typespec 1 int_typespec 9 logic_typespec 13 -module 5 +module_inst 5 operation 2 package 3 param_assign 12 @@ -152,7 +152,7 @@ enum_typespec 13 import_typespec 1 int_typespec 9 logic_typespec 13 -module 5 +module_inst 5 operation 2 package 3 param_assign 12 @@ -201,12 +201,12 @@ design: (work@top) |vpiTypespec: \_enum_typespec: (lc_ctrl_pkg::lc_tx_t), line:4:4, endln:7:15 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ImportBinding/dut.sv, line:15:1, endln:19:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ImportBinding/dut.sv, line:15:1, endln:19:10 |vpiName:lc_ctrl_pkg::lc_tx_t |vpiTypedefAlias: \_enum_typespec: (lc_ctrl_pkg::lc_tx_e), line:4:4, endln:7:15 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ImportBinding/dut.sv, line:15:1, endln:19:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ImportBinding/dut.sv, line:15:1, endln:19:10 |vpiName:lc_ctrl_pkg::lc_tx_e |vpiInstance: \_package: lc_ctrl_pkg (lc_ctrl_pkg::), file:${SURELOG_DIR}/tests/ImportBinding/dut.sv, line:1:1, endln:13:11 @@ -434,14 +434,14 @@ design: (work@top) |vpiDefName:lc_ctrl_pkg |vpiTop:1 |uhdmallModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/ImportBinding/dut.sv, line:15:1, endln:19:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ImportBinding/dut.sv, line:15:1, endln:19:10 |vpiParent: \_design: (work@top) |vpiFullName:work@top |vpiParameter: \_parameter: (work@top.LC_TX_DEFAULT), line:11:23, endln:11:36 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ImportBinding/dut.sv, line:15:1, endln:19:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ImportBinding/dut.sv, line:15:1, endln:19:10 |BIN:0101 |vpiTypespec: \_enum_typespec: (lc_tx_t), line:4:4, endln:7:15 @@ -547,7 +547,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.TxWidth), line:3:18, endln:3:25 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ImportBinding/dut.sv, line:15:1, endln:19:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ImportBinding/dut.sv, line:15:1, endln:19:10 |UINT:4 |vpiTypespec: \_int_typespec: , line:3:14, endln:3:17 @@ -563,7 +563,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:3:18, endln:3:29 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ImportBinding/dut.sv, line:15:1, endln:19:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ImportBinding/dut.sv, line:15:1, endln:19:10 |vpiRhs: \_constant: , line:3:28, endln:3:29 |vpiParent: @@ -598,7 +598,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:11:23, endln:11:42 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ImportBinding/dut.sv, line:15:1, endln:19:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ImportBinding/dut.sv, line:15:1, endln:19:10 |vpiRhs: \_constant: , line:11:39, endln:11:42 |vpiParent: @@ -819,12 +819,12 @@ design: (work@top) \_import_typespec: (lc_ctrl_pkg), line:16:8, endln:16:22 |vpiDefName:work@top |uhdmtopModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/ImportBinding/dut.sv, line:15:1, endln:19:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ImportBinding/dut.sv, line:15:1, endln:19:10 |vpiName:work@top |vpiParameter: \_parameter: (work@top.LC_TX_DEFAULT), line:11:23, endln:11:36 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ImportBinding/dut.sv, line:15:1, endln:19:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ImportBinding/dut.sv, line:15:1, endln:19:10 |BIN:0101 |vpiTypespec: \_enum_typespec: (lc_tx_t), line:4:4, endln:7:15 @@ -930,7 +930,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.TxWidth), line:3:18, endln:3:25 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ImportBinding/dut.sv, line:15:1, endln:19:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ImportBinding/dut.sv, line:15:1, endln:19:10 |UINT:4 |vpiTypespec: \_int_typespec: , line:3:14, endln:3:17 @@ -946,7 +946,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:3:18, endln:3:29 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ImportBinding/dut.sv, line:15:1, endln:19:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ImportBinding/dut.sv, line:15:1, endln:19:10 |vpiRhs: \_constant: , line:3:28, endln:3:29 |vpiDecompile:4 @@ -960,7 +960,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:11:23, endln:11:42 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ImportBinding/dut.sv, line:15:1, endln:19:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ImportBinding/dut.sv, line:15:1, endln:19:10 |vpiRhs: \_constant: , line:11:39, endln:11:42 |vpiDecompile:4'b0101 diff --git a/tests/ImportPackage/ImportPackage.log b/tests/ImportPackage/ImportPackage.log index a1cb49b968..84c73fc845 100644 --- a/tests/ImportPackage/ImportPackage.log +++ b/tests/ImportPackage/ImportPackage.log @@ -186,7 +186,7 @@ int_typespec 10 int_var 1 logic_net 1 logic_typespec 2 -module 10 +module_inst 10 operation 5 package 3 packed_array_typespec 2 @@ -208,7 +208,7 @@ int_typespec 10 int_var 1 logic_net 1 logic_typespec 2 -module 11 +module_inst 11 operation 5 package 3 packed_array_typespec 2 @@ -340,7 +340,7 @@ design: (work@top) |vpiTypedef: \_logic_typespec: (lc_ctrl_pkg::unused_type_t), line:6:12, endln:6:31 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ImportPackage/dut.sv, line:9:1, endln:19:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ImportPackage/dut.sv, line:9:1, endln:19:10 |vpiName:lc_ctrl_pkg::unused_type_t |vpiInstance: \_package: lc_ctrl_pkg (lc_ctrl_pkg::), file:${SURELOG_DIR}/tests/ImportPackage/dut.sv, line:4:1, endln:7:25 @@ -365,20 +365,20 @@ design: (work@top) |vpiDefName:lc_ctrl_pkg |vpiTop:1 |uhdmallModules: -\_module: work@GOOD (work@GOOD), file:${SURELOG_DIR}/tests/ImportPackage/dut.sv, line:1:1, endln:2:10 +\_module_inst: work@GOOD (work@GOOD), file:${SURELOG_DIR}/tests/ImportPackage/dut.sv, line:1:1, endln:2:10 |vpiParent: \_design: (work@top) |vpiFullName:work@GOOD |vpiDefName:work@GOOD |uhdmallModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/ImportPackage/dut.sv, line:9:1, endln:19:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ImportPackage/dut.sv, line:9:1, endln:19:10 |vpiParent: \_design: (work@top) |vpiFullName:work@top |vpiParameter: \_parameter: (work@top.TxWidth), line:11:18, endln:11:25 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ImportPackage/dut.sv, line:9:1, endln:19:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ImportPackage/dut.sv, line:9:1, endln:19:10 |UINT:1 |vpiTypespec: \_int_typespec: , line:11:14, endln:11:17 @@ -391,7 +391,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:11:18, endln:11:29 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ImportPackage/dut.sv, line:9:1, endln:19:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ImportPackage/dut.sv, line:9:1, endln:19:10 |vpiRhs: \_constant: , line:11:28, endln:11:29 |vpiDecompile:1 @@ -410,13 +410,13 @@ design: (work@top) |vpiNet: \_logic_net: (work@top.o), line:12:18, endln:12:19 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ImportPackage/dut.sv, line:9:1, endln:19:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ImportPackage/dut.sv, line:9:1, endln:19:10 |vpiName:o |vpiFullName:work@top.o |vpiContAssign: \_cont_assign: , line:13:11, endln:13:22 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ImportPackage/dut.sv, line:9:1, endln:19:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ImportPackage/dut.sv, line:9:1, endln:19:10 |vpiRhs: \_ref_obj: (work@top.TxWidth), line:13:15, endln:13:22 |vpiParent: @@ -432,12 +432,12 @@ design: (work@top) |vpiActual: \_int_var: (work@top.o), line:12:18, endln:12:19 |uhdmtopModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/ImportPackage/dut.sv, line:9:1, endln:19:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ImportPackage/dut.sv, line:9:1, endln:19:10 |vpiName:work@top |vpiVariables: \_int_var: (work@top.o), line:12:18, endln:12:19 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ImportPackage/dut.sv, line:9:1, endln:19:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ImportPackage/dut.sv, line:9:1, endln:19:10 |vpiTypespec: \_int_typespec: , line:12:4, endln:12:7 |vpiSigned:1 @@ -447,7 +447,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.TxWidth), line:11:18, endln:11:25 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ImportPackage/dut.sv, line:9:1, endln:19:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ImportPackage/dut.sv, line:9:1, endln:19:10 |UINT:1 |vpiTypespec: \_int_typespec: , line:11:14, endln:11:17 @@ -460,7 +460,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:11:18, endln:11:29 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ImportPackage/dut.sv, line:9:1, endln:19:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ImportPackage/dut.sv, line:9:1, endln:19:10 |vpiRhs: \_constant: , line:11:28, endln:11:29 |vpiParent: @@ -483,7 +483,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.genblk1), line:15:3, endln:17:6 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ImportPackage/dut.sv, line:9:1, endln:19:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ImportPackage/dut.sv, line:9:1, endln:19:10 |vpiName:genblk1 |vpiFullName:work@top.genblk1 |vpiGenScope: @@ -491,8 +491,8 @@ design: (work@top) |vpiParent: \_gen_scope_array: (work@top.genblk1), line:15:3, endln:17:6 |vpiFullName:work@top.genblk1 - |vpiModule: - \_module: work@GOOD (work@top.genblk1.good), file:${SURELOG_DIR}/tests/ImportPackage/dut.sv, line:16:6, endln:16:18 + |vpiModuleInst: + \_module_inst: work@GOOD (work@top.genblk1.good), file:${SURELOG_DIR}/tests/ImportPackage/dut.sv, line:16:6, endln:16:18 |vpiParent: \_gen_scope: (work@top.genblk1) |vpiName:good @@ -503,7 +503,7 @@ design: (work@top) |vpiContAssign: \_cont_assign: , line:13:11, endln:13:22 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ImportPackage/dut.sv, line:9:1, endln:19:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ImportPackage/dut.sv, line:9:1, endln:19:10 |vpiRhs: \_constant: , line:11:28, endln:11:29 |vpiLhs: diff --git a/tests/ImportedTypespec/ImportedTypespec.log b/tests/ImportedTypespec/ImportedTypespec.log index ec0d05f19b..31fb4c913c 100644 --- a/tests/ImportedTypespec/ImportedTypespec.log +++ b/tests/ImportedTypespec/ImportedTypespec.log @@ -127,7 +127,7 @@ int_typespec 13 int_var 1 logic_net 1 logic_typespec 2 -module 7 +module_inst 7 operation 4 package 3 packed_array_typespec 2 @@ -148,7 +148,7 @@ int_typespec 13 int_var 1 logic_net 1 logic_typespec 2 -module 7 +module_inst 7 operation 4 package 3 packed_array_typespec 2 @@ -277,7 +277,7 @@ design: (work@top) |vpiTypedef: \_logic_typespec: (spi_device_pkg::sram_addr_t), line:3:12, endln:3:30 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ImportedTypespec/dut.sv, line:6:1, endln:10:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ImportedTypespec/dut.sv, line:6:1, endln:10:10 |vpiName:spi_device_pkg::sram_addr_t |vpiInstance: \_package: spi_device_pkg (spi_device_pkg::), file:${SURELOG_DIR}/tests/ImportedTypespec/dut.sv, line:1:1, endln:4:11 @@ -302,14 +302,14 @@ design: (work@top) |vpiDefName:spi_device_pkg |vpiTop:1 |uhdmallModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/ImportedTypespec/dut.sv, line:6:1, endln:10:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ImportedTypespec/dut.sv, line:6:1, endln:10:10 |vpiParent: \_design: (work@top) |vpiFullName:work@top |vpiParameter: \_parameter: (work@top.SramAw), line:2:27, endln:2:33 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ImportedTypespec/dut.sv, line:6:1, endln:10:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ImportedTypespec/dut.sv, line:6:1, endln:10:10 |UINT:10 |vpiTypespec: \_int_typespec: , line:2:14, endln:2:26 @@ -323,7 +323,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:2:27, endln:2:38 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ImportedTypespec/dut.sv, line:6:1, endln:10:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ImportedTypespec/dut.sv, line:6:1, endln:10:10 |vpiRhs: \_constant: , line:2:36, endln:2:38 |vpiParent: @@ -360,13 +360,13 @@ design: (work@top) |vpiNet: \_logic_net: (work@top.o), line:6:23, endln:6:24 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ImportedTypespec/dut.sv, line:6:1, endln:10:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ImportedTypespec/dut.sv, line:6:1, endln:10:10 |vpiName:o |vpiFullName:work@top.o |vpiPort: \_port: (o), line:6:23, endln:6:24 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ImportedTypespec/dut.sv, line:6:1, endln:10:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ImportedTypespec/dut.sv, line:6:1, endln:10:10 |vpiName:o |vpiDirection:2 |vpiLowConn: @@ -379,7 +379,7 @@ design: (work@top) |vpiContAssign: \_cont_assign: , line:9:11, endln:9:33 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ImportedTypespec/dut.sv, line:6:1, endln:10:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ImportedTypespec/dut.sv, line:6:1, endln:10:10 |vpiRhs: \_constant: , line:9:15, endln:9:33 |vpiParent: @@ -397,12 +397,12 @@ design: (work@top) |vpiActual: \_int_var: (work@top.o), line:6:23, endln:6:24 |uhdmtopModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/ImportedTypespec/dut.sv, line:6:1, endln:10:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ImportedTypespec/dut.sv, line:6:1, endln:10:10 |vpiName:work@top |vpiVariables: \_int_var: (work@top.o), line:6:23, endln:6:24 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ImportedTypespec/dut.sv, line:6:1, endln:10:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ImportedTypespec/dut.sv, line:6:1, endln:10:10 |vpiTypespec: \_int_typespec: , line:6:19, endln:6:22 |vpiSigned:1 @@ -413,7 +413,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.SramAw), line:2:27, endln:2:33 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ImportedTypespec/dut.sv, line:6:1, endln:10:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ImportedTypespec/dut.sv, line:6:1, endln:10:10 |UINT:10 |vpiTypespec: \_int_typespec: , line:2:14, endln:2:26 @@ -427,7 +427,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:2:27, endln:2:38 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ImportedTypespec/dut.sv, line:6:1, endln:10:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ImportedTypespec/dut.sv, line:6:1, endln:10:10 |vpiRhs: \_constant: , line:2:36, endln:2:38 |vpiDecompile:10 @@ -448,7 +448,7 @@ design: (work@top) |vpiPort: \_port: (o), line:6:23, endln:6:24 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ImportedTypespec/dut.sv, line:6:1, endln:10:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ImportedTypespec/dut.sv, line:6:1, endln:10:10 |vpiName:o |vpiDirection:2 |vpiLowConn: @@ -463,11 +463,11 @@ design: (work@top) \_int_typespec: , line:6:19, endln:6:22 |vpiSigned:1 |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ImportedTypespec/dut.sv, line:6:1, endln:10:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ImportedTypespec/dut.sv, line:6:1, endln:10:10 |vpiContAssign: \_cont_assign: , line:9:11, endln:9:33 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ImportedTypespec/dut.sv, line:6:1, endln:10:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ImportedTypespec/dut.sv, line:6:1, endln:10:10 |vpiRhs: \_constant: , line:9:15, endln:9:33 |vpiParent: diff --git a/tests/IndexAssign/IndexAssign.log b/tests/IndexAssign/IndexAssign.log index adf849aba6..69919f4755 100644 --- a/tests/IndexAssign/IndexAssign.log +++ b/tests/IndexAssign/IndexAssign.log @@ -31,7 +31,7 @@ int_typespec 2 logic_net 1 logic_typespec 1 logic_var 1 -module 6 +module_inst 6 operation 4 param_assign 2 parameter 2 @@ -49,7 +49,7 @@ int_typespec 2 logic_net 1 logic_typespec 1 logic_var 1 -module 6 +module_inst 6 operation 5 param_assign 2 parameter 2 @@ -69,14 +69,14 @@ design: (work@t) |vpiElaborated:1 |vpiName:work@t |uhdmallModules: -\_module: work@t (work@t), file:${SURELOG_DIR}/tests/IndexAssign/dut.sv, line:1:1, endln:5:10 +\_module_inst: work@t (work@t), file:${SURELOG_DIR}/tests/IndexAssign/dut.sv, line:1:1, endln:5:10 |vpiParent: \_design: (work@t) |vpiFullName:work@t |vpiParameter: \_parameter: (work@t.I), line:2:27, endln:2:28 |vpiParent: - \_module: work@t (work@t), file:${SURELOG_DIR}/tests/IndexAssign/dut.sv, line:1:1, endln:5:10 + \_module_inst: work@t (work@t), file:${SURELOG_DIR}/tests/IndexAssign/dut.sv, line:1:1, endln:5:10 |UINT:9 |vpiTypespec: \_int_typespec: , line:2:14, endln:2:26 @@ -88,7 +88,7 @@ design: (work@t) |vpiParamAssign: \_param_assign: , line:2:27, endln:2:32 |vpiParent: - \_module: work@t (work@t), file:${SURELOG_DIR}/tests/IndexAssign/dut.sv, line:1:1, endln:5:10 + \_module_inst: work@t (work@t), file:${SURELOG_DIR}/tests/IndexAssign/dut.sv, line:1:1, endln:5:10 |vpiRhs: \_constant: , line:2:31, endln:2:32 |vpiDecompile:9 @@ -103,14 +103,14 @@ design: (work@t) |vpiNet: \_logic_net: (work@t.sig), line:3:17, endln:3:20 |vpiParent: - \_module: work@t (work@t), file:${SURELOG_DIR}/tests/IndexAssign/dut.sv, line:1:1, endln:5:10 + \_module_inst: work@t (work@t), file:${SURELOG_DIR}/tests/IndexAssign/dut.sv, line:1:1, endln:5:10 |vpiName:sig |vpiFullName:work@t.sig |vpiNetType:36 |vpiContAssign: \_cont_assign: , line:4:10, endln:4:22 |vpiParent: - \_module: work@t (work@t), file:${SURELOG_DIR}/tests/IndexAssign/dut.sv, line:1:1, endln:5:10 + \_module_inst: work@t (work@t), file:${SURELOG_DIR}/tests/IndexAssign/dut.sv, line:1:1, endln:5:10 |vpiRhs: \_constant: , line:4:21, endln:4:22 |vpiParent: @@ -149,12 +149,12 @@ design: (work@t) |UINT:7 |vpiConstType:9 |uhdmtopModules: -\_module: work@t (work@t), file:${SURELOG_DIR}/tests/IndexAssign/dut.sv, line:1:1, endln:5:10 +\_module_inst: work@t (work@t), file:${SURELOG_DIR}/tests/IndexAssign/dut.sv, line:1:1, endln:5:10 |vpiName:work@t |vpiVariables: \_logic_var: (work@t.sig), line:3:17, endln:3:20 |vpiParent: - \_module: work@t (work@t), file:${SURELOG_DIR}/tests/IndexAssign/dut.sv, line:1:1, endln:5:10 + \_module_inst: work@t (work@t), file:${SURELOG_DIR}/tests/IndexAssign/dut.sv, line:1:1, endln:5:10 |vpiTypespec: \_logic_typespec: , line:3:3, endln:3:16 |vpiRange: @@ -199,7 +199,7 @@ design: (work@t) |vpiParameter: \_parameter: (work@t.I), line:2:27, endln:2:28 |vpiParent: - \_module: work@t (work@t), file:${SURELOG_DIR}/tests/IndexAssign/dut.sv, line:1:1, endln:5:10 + \_module_inst: work@t (work@t), file:${SURELOG_DIR}/tests/IndexAssign/dut.sv, line:1:1, endln:5:10 |UINT:9 |vpiTypespec: \_int_typespec: , line:2:14, endln:2:26 @@ -211,7 +211,7 @@ design: (work@t) |vpiParamAssign: \_param_assign: , line:2:27, endln:2:32 |vpiParent: - \_module: work@t (work@t), file:${SURELOG_DIR}/tests/IndexAssign/dut.sv, line:1:1, endln:5:10 + \_module_inst: work@t (work@t), file:${SURELOG_DIR}/tests/IndexAssign/dut.sv, line:1:1, endln:5:10 |vpiRhs: \_constant: , line:2:31, endln:2:32 |vpiDecompile:9 @@ -228,7 +228,7 @@ design: (work@t) |vpiContAssign: \_cont_assign: , line:4:10, endln:4:22 |vpiParent: - \_module: work@t (work@t), file:${SURELOG_DIR}/tests/IndexAssign/dut.sv, line:1:1, endln:5:10 + \_module_inst: work@t (work@t), file:${SURELOG_DIR}/tests/IndexAssign/dut.sv, line:1:1, endln:5:10 |vpiRhs: \_constant: , line:4:21, endln:4:22 |vpiLhs: diff --git a/tests/IndexPartSel/IndexPartSel.log b/tests/IndexPartSel/IndexPartSel.log index dbc8be5c9a..c0024cc3cc 100644 --- a/tests/IndexPartSel/IndexPartSel.log +++ b/tests/IndexPartSel/IndexPartSel.log @@ -176,7 +176,7 @@ design 1 indexed_part_select 2 logic_net 6 logic_typespec 3 -module 4 +module_inst 4 operation 2 range 6 ref_obj 4 @@ -191,7 +191,7 @@ design 1 indexed_part_select 4 logic_net 6 logic_typespec 3 -module 4 +module_inst 4 operation 4 range 6 ref_obj 8 @@ -209,7 +209,7 @@ design: (work@dut) |vpiElaborated:1 |vpiName:work@dut |uhdmallModules: -\_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/IndexPartSel/dut.sv, line:2:1, endln:8:10 +\_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/IndexPartSel/dut.sv, line:2:1, endln:8:10 |vpiParent: \_design: (work@dut) |vpiFullName:work@dut @@ -217,28 +217,28 @@ design: (work@dut) |vpiNet: \_logic_net: (work@dut.hw2reg_wrap), line:3:14, endln:3:25 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/IndexPartSel/dut.sv, line:2:1, endln:8:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/IndexPartSel/dut.sv, line:2:1, endln:8:10 |vpiName:hw2reg_wrap |vpiFullName:work@dut.hw2reg_wrap |vpiNetType:1 |vpiNet: \_logic_net: (work@dut.notworking_indexed_part_select), line:4:14, endln:4:44 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/IndexPartSel/dut.sv, line:2:1, endln:8:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/IndexPartSel/dut.sv, line:2:1, endln:8:10 |vpiName:notworking_indexed_part_select |vpiFullName:work@dut.notworking_indexed_part_select |vpiNetType:1 |vpiNet: \_logic_net: (work@dut.working_bitselect), line:5:13, endln:5:30 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/IndexPartSel/dut.sv, line:2:1, endln:8:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/IndexPartSel/dut.sv, line:2:1, endln:8:10 |vpiName:working_bitselect |vpiFullName:work@dut.working_bitselect |vpiNetType:1 |vpiContAssign: \_cont_assign: , line:6:8, endln:6:49 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/IndexPartSel/dut.sv, line:2:1, endln:8:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/IndexPartSel/dut.sv, line:2:1, endln:8:10 |vpiRhs: \_bit_select: (work@dut.hw2reg_wrap), line:6:33, endln:6:49 |vpiParent: @@ -283,7 +283,7 @@ design: (work@dut) |vpiContAssign: \_cont_assign: , line:7:8, endln:7:71 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/IndexPartSel/dut.sv, line:2:1, endln:8:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/IndexPartSel/dut.sv, line:2:1, endln:8:10 |vpiRhs: \_indexed_part_select: , line:7:63, endln:7:70 |vpiParent: @@ -336,14 +336,14 @@ design: (work@dut) |UINT:16 |vpiConstType:9 |uhdmtopModules: -\_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/IndexPartSel/dut.sv, line:2:1, endln:8:10 +\_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/IndexPartSel/dut.sv, line:2:1, endln:8:10 |vpiName:work@dut |vpiDefName:work@dut |vpiTop:1 |vpiNet: \_logic_net: (work@dut.hw2reg_wrap), line:3:14, endln:3:25 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/IndexPartSel/dut.sv, line:2:1, endln:8:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/IndexPartSel/dut.sv, line:2:1, endln:8:10 |vpiTypespec: \_logic_typespec: , line:3:1, endln:3:13 |vpiRange: @@ -370,7 +370,7 @@ design: (work@dut) |vpiNet: \_logic_net: (work@dut.notworking_indexed_part_select), line:4:14, endln:4:44 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/IndexPartSel/dut.sv, line:2:1, endln:8:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/IndexPartSel/dut.sv, line:2:1, endln:8:10 |vpiTypespec: \_logic_typespec: , line:4:1, endln:4:13 |vpiRange: @@ -397,7 +397,7 @@ design: (work@dut) |vpiNet: \_logic_net: (work@dut.working_bitselect), line:5:13, endln:5:30 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/IndexPartSel/dut.sv, line:2:1, endln:8:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/IndexPartSel/dut.sv, line:2:1, endln:8:10 |vpiTypespec: \_logic_typespec: , line:5:1, endln:5:12 |vpiRange: @@ -425,7 +425,7 @@ design: (work@dut) |vpiContAssign: \_cont_assign: , line:6:8, endln:6:49 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/IndexPartSel/dut.sv, line:2:1, endln:8:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/IndexPartSel/dut.sv, line:2:1, endln:8:10 |vpiRhs: \_bit_select: (work@dut.hw2reg_wrap), line:6:33, endln:6:49 |vpiParent: @@ -466,7 +466,7 @@ design: (work@dut) |vpiContAssign: \_cont_assign: , line:7:8, endln:7:71 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/IndexPartSel/dut.sv, line:2:1, endln:8:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/IndexPartSel/dut.sv, line:2:1, endln:8:10 |vpiRhs: \_indexed_part_select: , line:7:63, endln:7:70 |vpiParent: diff --git a/tests/InsideOp/InsideOp.log b/tests/InsideOp/InsideOp.log index ce0ac0624b..9632038084 100644 --- a/tests/InsideOp/InsideOp.log +++ b/tests/InsideOp/InsideOp.log @@ -326,7 +326,7 @@ import_typespec 1 int_typespec 6 int_var 1 logic_net 1 -module 9 +module_inst 9 operation 3 package 3 param_assign 2 @@ -348,7 +348,7 @@ import_typespec 1 int_typespec 6 int_var 1 logic_net 1 -module 10 +module_inst 10 operation 3 package 3 param_assign 2 @@ -432,7 +432,7 @@ design: (work@top) |vpiTypedef: \_enum_typespec: (my_pkg::get_e), line:3:3, endln:10:11 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/InsideOp/dut.sv, line:17:1, endln:38:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/InsideOp/dut.sv, line:17:1, endln:38:10 |vpiName:my_pkg::get_e |vpiInstance: \_package: my_pkg (my_pkg::), file:${SURELOG_DIR}/tests/InsideOp/dut.sv, line:1:1, endln:12:11 @@ -480,20 +480,20 @@ design: (work@top) |vpiDefName:my_pkg |vpiTop:1 |uhdmallModules: -\_module: work@GOOD (work@GOOD), file:${SURELOG_DIR}/tests/InsideOp/dut.sv, line:14:1, endln:15:10 +\_module_inst: work@GOOD (work@GOOD), file:${SURELOG_DIR}/tests/InsideOp/dut.sv, line:14:1, endln:15:10 |vpiParent: \_design: (work@top) |vpiFullName:work@GOOD |vpiDefName:work@GOOD |uhdmallModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/InsideOp/dut.sv, line:17:1, endln:38:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/InsideOp/dut.sv, line:17:1, endln:38:10 |vpiParent: \_design: (work@top) |vpiFullName:work@top |vpiParameter: \_parameter: (work@top.GetWhat), line:20:21, endln:20:28 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/InsideOp/dut.sv, line:17:1, endln:38:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/InsideOp/dut.sv, line:17:1, endln:38:10 |vpiTypespec: \_enum_typespec: (my_pkg::get_e), line:3:3, endln:10:11 |vpiName:GetWhat @@ -501,7 +501,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:20:21, endln:20:35 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/InsideOp/dut.sv, line:17:1, endln:38:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/InsideOp/dut.sv, line:17:1, endln:38:10 |vpiRhs: \_ref_obj: (Get3), line:20:31, endln:20:35 |vpiName:Get3 @@ -517,13 +517,13 @@ design: (work@top) |vpiNet: \_logic_net: (work@top.out), line:22:16, endln:22:19 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/InsideOp/dut.sv, line:17:1, endln:38:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/InsideOp/dut.sv, line:17:1, endln:38:10 |vpiName:out |vpiFullName:work@top.out |vpiPort: \_port: (out), line:22:16, endln:22:19 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/InsideOp/dut.sv, line:17:1, endln:38:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/InsideOp/dut.sv, line:17:1, endln:38:10 |vpiName:out |vpiDirection:2 |vpiLowConn: @@ -534,12 +534,12 @@ design: (work@top) \_int_typespec: , line:22:12, endln:22:15 |vpiSigned:1 |uhdmtopModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/InsideOp/dut.sv, line:17:1, endln:38:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/InsideOp/dut.sv, line:17:1, endln:38:10 |vpiName:work@top |vpiVariables: \_int_var: (work@top.out), line:22:16, endln:22:19 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/InsideOp/dut.sv, line:17:1, endln:38:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/InsideOp/dut.sv, line:17:1, endln:38:10 |vpiTypespec: \_int_typespec: , line:22:12, endln:22:15 |vpiSigned:1 @@ -550,7 +550,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.GetWhat), line:20:21, endln:20:28 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/InsideOp/dut.sv, line:17:1, endln:38:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/InsideOp/dut.sv, line:17:1, endln:38:10 |vpiTypespec: \_enum_typespec: (my_pkg::get_e), line:3:3, endln:10:11 |vpiParent: @@ -618,7 +618,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:20:21, endln:20:35 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/InsideOp/dut.sv, line:17:1, endln:38:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/InsideOp/dut.sv, line:17:1, endln:38:10 |vpiRhs: \_constant: , line:20:31, endln:20:35 |vpiDecompile:3 @@ -639,7 +639,7 @@ design: (work@top) |vpiPort: \_port: (out), line:22:16, endln:22:19 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/InsideOp/dut.sv, line:17:1, endln:38:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/InsideOp/dut.sv, line:17:1, endln:38:10 |vpiName:out |vpiDirection:2 |vpiLowConn: @@ -654,11 +654,11 @@ design: (work@top) \_int_typespec: , line:22:12, endln:22:15 |vpiSigned:1 |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/InsideOp/dut.sv, line:17:1, endln:38:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/InsideOp/dut.sv, line:17:1, endln:38:10 |vpiGenScopeArray: \_gen_scope_array: (work@top.gen_two), line:30:5, endln:30:20 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/InsideOp/dut.sv, line:17:1, endln:38:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/InsideOp/dut.sv, line:17:1, endln:38:10 |vpiName:gen_two |vpiFullName:work@top.gen_two |vpiGenScope: @@ -686,8 +686,8 @@ design: (work@top) |vpiFullName:work@top.gen_two.out |vpiActual: \_int_var: (work@top.out), line:22:16, endln:22:19 - |vpiModule: - \_module: work@GOOD (work@top.gen_two.good), file:${SURELOG_DIR}/tests/InsideOp/dut.sv, line:31:5, endln:31:17 + |vpiModuleInst: + \_module_inst: work@GOOD (work@top.gen_two.good), file:${SURELOG_DIR}/tests/InsideOp/dut.sv, line:31:5, endln:31:17 |vpiParent: \_gen_scope: (work@top.gen_two) |vpiName:good diff --git a/tests/IntegerConcat/IntegerConcat.log b/tests/IntegerConcat/IntegerConcat.log index 243f55cf25..1ed7cae698 100644 --- a/tests/IntegerConcat/IntegerConcat.log +++ b/tests/IntegerConcat/IntegerConcat.log @@ -258,7 +258,7 @@ design 1 import_typespec 1 int_typespec 54 logic_typespec 11 -module 9 +module_inst 9 operation 15 package 3 param_assign 44 @@ -275,7 +275,7 @@ design 1 import_typespec 1 int_typespec 54 logic_typespec 11 -module 9 +module_inst 9 operation 15 package 3 param_assign 44 @@ -826,14 +826,14 @@ design: (work@dut) |vpiDefName:pkg |vpiTop:1 |uhdmallModules: -\_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/IntegerConcat/dut.sv, line:22:1, endln:26:10 +\_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/IntegerConcat/dut.sv, line:22:1, endln:26:10 |vpiParent: \_design: (work@dut) |vpiFullName:work@dut |vpiParameter: \_parameter: (work@dut.CreatorInfoPage), line:6:15, endln:6:30 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/IntegerConcat/dut.sv, line:22:1, endln:26:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/IntegerConcat/dut.sv, line:22:1, endln:26:10 |UINT:1 |vpiTypespec: \_int_typespec: , line:6:11, endln:6:14 @@ -849,7 +849,7 @@ design: (work@dut) |vpiParameter: \_parameter: (work@dut.FLASH_INFO_PER_BANK), line:2:16, endln:2:35 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/IntegerConcat/dut.sv, line:22:1, endln:26:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/IntegerConcat/dut.sv, line:22:1, endln:26:10 |UINT:4 |vpiTypespec: \_int_typespec: , line:2:12, endln:2:15 @@ -866,7 +866,7 @@ design: (work@dut) |vpiParameter: \_parameter: (work@dut.InfoPageW), line:4:15, endln:4:24 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/IntegerConcat/dut.sv, line:22:1, endln:26:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/IntegerConcat/dut.sv, line:22:1, endln:26:10 |UINT:2 |vpiTypespec: \_int_typespec: , line:4:11, endln:4:14 @@ -882,7 +882,7 @@ design: (work@dut) |vpiParameter: \_parameter: (work@dut.InfosPerBank), line:3:15, endln:3:27 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/IntegerConcat/dut.sv, line:22:1, endln:26:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/IntegerConcat/dut.sv, line:22:1, endln:26:10 |UINT:4 |vpiTypespec: \_int_typespec: , line:3:11, endln:3:14 @@ -898,7 +898,7 @@ design: (work@dut) |vpiParameter: \_parameter: (work@dut.NumSeeds), line:5:15, endln:5:23 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/IntegerConcat/dut.sv, line:22:1, endln:26:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/IntegerConcat/dut.sv, line:22:1, endln:26:10 |UINT:2 |vpiTypespec: \_int_typespec: , line:5:11, endln:5:14 @@ -914,7 +914,7 @@ design: (work@dut) |vpiParameter: \_parameter: (work@dut.OwnerInfoPage), line:7:15, endln:7:28 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/IntegerConcat/dut.sv, line:22:1, endln:26:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/IntegerConcat/dut.sv, line:22:1, endln:26:10 |UINT:2 |vpiTypespec: \_int_typespec: , line:7:11, endln:7:14 @@ -930,7 +930,7 @@ design: (work@dut) |vpiParameter: \_parameter: (work@dut.SeedInfoPageSel), line:8:47, endln:8:62 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/IntegerConcat/dut.sv, line:22:1, endln:26:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/IntegerConcat/dut.sv, line:22:1, endln:26:10 |vpiTypespec: \_logic_typespec: , line:8:11, endln:8:46 |vpiParent: @@ -983,7 +983,7 @@ design: (work@dut) |vpiParamAssign: \_param_assign: , line:2:16, endln:2:37 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/IntegerConcat/dut.sv, line:22:1, endln:26:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/IntegerConcat/dut.sv, line:22:1, endln:26:10 |vpiRhs: \_constant: , line:2:36, endln:2:37 |vpiParent: @@ -1019,7 +1019,7 @@ design: (work@dut) |vpiParamAssign: \_param_assign: , line:3:15, endln:3:52 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/IntegerConcat/dut.sv, line:22:1, endln:26:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/IntegerConcat/dut.sv, line:22:1, endln:26:10 |vpiRhs: \_constant: , line:3:33, endln:3:52 |vpiParent: @@ -1054,7 +1054,7 @@ design: (work@dut) |vpiParamAssign: \_param_assign: , line:4:15, endln:4:53 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/IntegerConcat/dut.sv, line:22:1, endln:26:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/IntegerConcat/dut.sv, line:22:1, endln:26:10 |vpiRhs: \_constant: , line:4:33, endln:4:53 |vpiParent: @@ -1089,7 +1089,7 @@ design: (work@dut) |vpiParamAssign: \_param_assign: , line:5:15, endln:5:27 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/IntegerConcat/dut.sv, line:22:1, endln:26:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/IntegerConcat/dut.sv, line:22:1, endln:26:10 |vpiRhs: \_constant: , line:5:26, endln:5:27 |vpiParent: @@ -1124,7 +1124,7 @@ design: (work@dut) |vpiParamAssign: \_param_assign: , line:6:15, endln:6:34 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/IntegerConcat/dut.sv, line:22:1, endln:26:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/IntegerConcat/dut.sv, line:22:1, endln:26:10 |vpiRhs: \_constant: , line:6:33, endln:6:34 |vpiParent: @@ -1159,7 +1159,7 @@ design: (work@dut) |vpiParamAssign: \_param_assign: , line:7:15, endln:7:32 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/IntegerConcat/dut.sv, line:22:1, endln:26:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/IntegerConcat/dut.sv, line:22:1, endln:26:10 |vpiRhs: \_constant: , line:7:31, endln:7:32 |vpiParent: @@ -1194,7 +1194,7 @@ design: (work@dut) |vpiParamAssign: \_param_assign: , line:8:47, endln:12:2 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/IntegerConcat/dut.sv, line:22:1, endln:26:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/IntegerConcat/dut.sv, line:22:1, endln:26:10 |vpiRhs: \_operation: , line:9:1, endln:12:2 |vpiParent: @@ -1270,14 +1270,14 @@ design: (work@dut) \_import_typespec: (pkg), line:23:8, endln:23:14 |vpiDefName:work@dut |uhdmallModules: -\_module: work@test (work@test), file:${SURELOG_DIR}/tests/IntegerConcat/dut.sv, line:16:1, endln:20:10 +\_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/IntegerConcat/dut.sv, line:16:1, endln:20:10 |vpiParent: \_design: (work@dut) |vpiFullName:work@test |vpiParameter: \_parameter: (work@test.p), line:17:25, endln:17:26 |vpiParent: - \_module: work@test (work@test), file:${SURELOG_DIR}/tests/IntegerConcat/dut.sv, line:16:1, endln:20:10 + \_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/IntegerConcat/dut.sv, line:16:1, endln:20:10 |vpiTypespec: \_logic_typespec: , line:17:13, endln:17:24 |vpiParent: @@ -1305,17 +1305,17 @@ design: (work@dut) |vpiParamAssign: \_param_assign: , line:17:25, endln:17:26 |vpiParent: - \_module: work@test (work@test), file:${SURELOG_DIR}/tests/IntegerConcat/dut.sv, line:16:1, endln:20:10 + \_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/IntegerConcat/dut.sv, line:16:1, endln:20:10 |vpiLhs: \_parameter: (work@test.p), line:17:25, endln:17:26 |vpiDefName:work@test |uhdmtopModules: -\_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/IntegerConcat/dut.sv, line:22:1, endln:26:10 +\_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/IntegerConcat/dut.sv, line:22:1, endln:26:10 |vpiName:work@dut |vpiParameter: \_parameter: (work@dut.CreatorInfoPage), line:6:15, endln:6:30 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/IntegerConcat/dut.sv, line:22:1, endln:26:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/IntegerConcat/dut.sv, line:22:1, endln:26:10 |UINT:1 |vpiTypespec: \_int_typespec: , line:6:11, endln:6:14 @@ -1331,7 +1331,7 @@ design: (work@dut) |vpiParameter: \_parameter: (work@dut.FLASH_INFO_PER_BANK), line:2:16, endln:2:35 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/IntegerConcat/dut.sv, line:22:1, endln:26:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/IntegerConcat/dut.sv, line:22:1, endln:26:10 |UINT:4 |vpiTypespec: \_int_typespec: , line:2:12, endln:2:15 @@ -1348,7 +1348,7 @@ design: (work@dut) |vpiParameter: \_parameter: (work@dut.InfoPageW), line:4:15, endln:4:24 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/IntegerConcat/dut.sv, line:22:1, endln:26:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/IntegerConcat/dut.sv, line:22:1, endln:26:10 |UINT:2 |vpiTypespec: \_int_typespec: , line:4:11, endln:4:14 @@ -1364,7 +1364,7 @@ design: (work@dut) |vpiParameter: \_parameter: (work@dut.InfosPerBank), line:3:15, endln:3:27 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/IntegerConcat/dut.sv, line:22:1, endln:26:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/IntegerConcat/dut.sv, line:22:1, endln:26:10 |UINT:4 |vpiTypespec: \_int_typespec: , line:3:11, endln:3:14 @@ -1380,7 +1380,7 @@ design: (work@dut) |vpiParameter: \_parameter: (work@dut.NumSeeds), line:5:15, endln:5:23 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/IntegerConcat/dut.sv, line:22:1, endln:26:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/IntegerConcat/dut.sv, line:22:1, endln:26:10 |UINT:2 |vpiTypespec: \_int_typespec: , line:5:11, endln:5:14 @@ -1396,7 +1396,7 @@ design: (work@dut) |vpiParameter: \_parameter: (work@dut.OwnerInfoPage), line:7:15, endln:7:28 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/IntegerConcat/dut.sv, line:22:1, endln:26:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/IntegerConcat/dut.sv, line:22:1, endln:26:10 |UINT:2 |vpiTypespec: \_int_typespec: , line:7:11, endln:7:14 @@ -1412,7 +1412,7 @@ design: (work@dut) |vpiParameter: \_parameter: (work@dut.SeedInfoPageSel), line:8:47, endln:8:62 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/IntegerConcat/dut.sv, line:22:1, endln:26:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/IntegerConcat/dut.sv, line:22:1, endln:26:10 |vpiTypespec: \_logic_typespec: , line:8:11, endln:8:46 |vpiParent: @@ -1465,7 +1465,7 @@ design: (work@dut) |vpiParamAssign: \_param_assign: , line:2:16, endln:2:37 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/IntegerConcat/dut.sv, line:22:1, endln:26:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/IntegerConcat/dut.sv, line:22:1, endln:26:10 |vpiRhs: \_constant: , line:2:36, endln:2:37 |vpiDecompile:4 @@ -1479,7 +1479,7 @@ design: (work@dut) |vpiParamAssign: \_param_assign: , line:3:15, endln:3:52 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/IntegerConcat/dut.sv, line:22:1, endln:26:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/IntegerConcat/dut.sv, line:22:1, endln:26:10 |vpiRhs: \_constant: , line:3:33, endln:3:52 |vpiDecompile:4 @@ -1493,7 +1493,7 @@ design: (work@dut) |vpiParamAssign: \_param_assign: , line:4:15, endln:4:53 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/IntegerConcat/dut.sv, line:22:1, endln:26:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/IntegerConcat/dut.sv, line:22:1, endln:26:10 |vpiRhs: \_constant: , line:4:33, endln:4:53 |vpiDecompile:2 @@ -1507,7 +1507,7 @@ design: (work@dut) |vpiParamAssign: \_param_assign: , line:5:15, endln:5:27 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/IntegerConcat/dut.sv, line:22:1, endln:26:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/IntegerConcat/dut.sv, line:22:1, endln:26:10 |vpiRhs: \_constant: , line:5:26, endln:5:27 |vpiDecompile:2 @@ -1521,7 +1521,7 @@ design: (work@dut) |vpiParamAssign: \_param_assign: , line:6:15, endln:6:34 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/IntegerConcat/dut.sv, line:22:1, endln:26:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/IntegerConcat/dut.sv, line:22:1, endln:26:10 |vpiRhs: \_constant: , line:6:33, endln:6:34 |vpiDecompile:1 @@ -1535,7 +1535,7 @@ design: (work@dut) |vpiParamAssign: \_param_assign: , line:7:15, endln:7:32 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/IntegerConcat/dut.sv, line:22:1, endln:26:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/IntegerConcat/dut.sv, line:22:1, endln:26:10 |vpiRhs: \_constant: , line:7:31, endln:7:32 |vpiDecompile:2 @@ -1549,7 +1549,7 @@ design: (work@dut) |vpiParamAssign: \_param_assign: , line:8:47, endln:12:2 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/IntegerConcat/dut.sv, line:22:1, endln:26:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/IntegerConcat/dut.sv, line:22:1, endln:26:10 |vpiRhs: \_operation: , line:9:1, endln:12:2 |vpiTypespec: @@ -1621,16 +1621,16 @@ design: (work@dut) |vpiDefName:work@dut |vpiTop:1 |vpiTopModule:1 - |vpiModule: - \_module: work@test (work@dut.t), file:${SURELOG_DIR}/tests/IntegerConcat/dut.sv, line:25:1, endln:25:33 + |vpiModuleInst: + \_module_inst: work@test (work@dut.t), file:${SURELOG_DIR}/tests/IntegerConcat/dut.sv, line:25:1, endln:25:33 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/IntegerConcat/dut.sv, line:22:1, endln:26:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/IntegerConcat/dut.sv, line:22:1, endln:26:10 |vpiName:t |vpiFullName:work@dut.t |vpiParameter: \_parameter: (work@dut.t.p), line:17:25, endln:17:26 |vpiParent: - \_module: work@test (work@dut.t), file:${SURELOG_DIR}/tests/IntegerConcat/dut.sv, line:25:1, endln:25:33 + \_module_inst: work@test (work@dut.t), file:${SURELOG_DIR}/tests/IntegerConcat/dut.sv, line:25:1, endln:25:33 |vpiTypespec: \_logic_typespec: , line:17:13, endln:17:24 |vpiParent: @@ -1660,7 +1660,7 @@ design: (work@dut) |vpiParamAssign: \_param_assign: , line:17:25, endln:17:26 |vpiParent: - \_module: work@test (work@dut.t), file:${SURELOG_DIR}/tests/IntegerConcat/dut.sv, line:25:1, endln:25:33 + \_module_inst: work@test (work@dut.t), file:${SURELOG_DIR}/tests/IntegerConcat/dut.sv, line:25:1, endln:25:33 |vpiOverriden:1 |vpiRhs: \_constant: @@ -1676,7 +1676,7 @@ design: (work@dut) |vpiDefFile:${SURELOG_DIR}/tests/IntegerConcat/dut.sv |vpiDefLineNo:16 |vpiInstance: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/IntegerConcat/dut.sv, line:22:1, endln:26:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/IntegerConcat/dut.sv, line:22:1, endln:26:10 =================== [ FATAL] : 0 [ SYNTAX] : 0 diff --git a/tests/InterfAlways/InterfAlways.log b/tests/InterfAlways/InterfAlways.log index 3442087188..e2f3a7dd6f 100644 --- a/tests/InterfAlways/InterfAlways.log +++ b/tests/InterfAlways/InterfAlways.log @@ -108,9 +108,9 @@ constant 1 design 1 int_typespec 5 int_var 2 -interface 3 +interface_inst 3 logic_net 2 -module 3 +module_inst 3 port 4 ref_obj 6 === UHDM Object Stats End === @@ -124,9 +124,9 @@ constant 1 design 1 int_typespec 5 int_var 2 -interface 3 +interface_inst 3 logic_net 2 -module 3 +module_inst 3 port 5 ref_obj 7 === UHDM Object Stats End === @@ -143,7 +143,7 @@ design: (work@top) |vpiElaborated:1 |vpiName:work@top |uhdmallInterfaces: -\_interface: work@sw_test_status_if (work@sw_test_status_if), file:${SURELOG_DIR}/tests/InterfAlways/dut.sv, line:1:1, endln:5:13 +\_interface_inst: work@sw_test_status_if (work@sw_test_status_if), file:${SURELOG_DIR}/tests/InterfAlways/dut.sv, line:1:1, endln:5:13 |vpiParent: \_design: (work@top) |vpiFullName:work@sw_test_status_if @@ -151,13 +151,13 @@ design: (work@top) |vpiNet: \_logic_net: (work@sw_test_status_if.x), line:1:40, endln:1:41 |vpiParent: - \_interface: work@sw_test_status_if (work@sw_test_status_if), file:${SURELOG_DIR}/tests/InterfAlways/dut.sv, line:1:1, endln:5:13 + \_interface_inst: work@sw_test_status_if (work@sw_test_status_if), file:${SURELOG_DIR}/tests/InterfAlways/dut.sv, line:1:1, endln:5:13 |vpiName:x |vpiFullName:work@sw_test_status_if.x |vpiProcess: \_always: , line:2:4, endln:4:7 |vpiParent: - \_interface: work@sw_test_status_if (work@sw_test_status_if), file:${SURELOG_DIR}/tests/InterfAlways/dut.sv, line:1:1, endln:5:13 + \_interface_inst: work@sw_test_status_if (work@sw_test_status_if), file:${SURELOG_DIR}/tests/InterfAlways/dut.sv, line:1:1, endln:5:13 |vpiStmt: \_begin: (work@sw_test_status_if), line:2:11, endln:4:7 |vpiParent: @@ -189,7 +189,7 @@ design: (work@top) |vpiPort: \_port: (x), line:1:40, endln:1:41 |vpiParent: - \_interface: work@sw_test_status_if (work@sw_test_status_if), file:${SURELOG_DIR}/tests/InterfAlways/dut.sv, line:1:1, endln:5:13 + \_interface_inst: work@sw_test_status_if (work@sw_test_status_if), file:${SURELOG_DIR}/tests/InterfAlways/dut.sv, line:1:1, endln:5:13 |vpiName:x |vpiDirection:2 |vpiLowConn: @@ -197,7 +197,7 @@ design: (work@top) |vpiActual: \_logic_net: (work@sw_test_status_if.x), line:1:40, endln:1:41 |uhdmallModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/InterfAlways/dut.sv, line:7:1, endln:9:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/InterfAlways/dut.sv, line:7:1, endln:9:10 |vpiParent: \_design: (work@top) |vpiFullName:work@top @@ -205,13 +205,13 @@ design: (work@top) |vpiNet: \_logic_net: (work@top.o), line:7:23, endln:7:24 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/InterfAlways/dut.sv, line:7:1, endln:9:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/InterfAlways/dut.sv, line:7:1, endln:9:10 |vpiName:o |vpiFullName:work@top.o |vpiPort: \_port: (o), line:7:23, endln:7:24 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/InterfAlways/dut.sv, line:7:1, endln:9:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/InterfAlways/dut.sv, line:7:1, endln:9:10 |vpiName:o |vpiDirection:2 |vpiLowConn: @@ -222,12 +222,12 @@ design: (work@top) \_int_typespec: , line:7:19, endln:7:22 |vpiSigned:1 |uhdmtopModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/InterfAlways/dut.sv, line:7:1, endln:9:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/InterfAlways/dut.sv, line:7:1, endln:9:10 |vpiName:work@top |vpiVariables: \_int_var: (work@top.o), line:7:23, endln:7:24 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/InterfAlways/dut.sv, line:7:1, endln:9:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/InterfAlways/dut.sv, line:7:1, endln:9:10 |vpiTypespec: \_int_typespec: , line:7:19, endln:7:22 |vpiSigned:1 @@ -241,7 +241,7 @@ design: (work@top) |vpiPort: \_port: (o), line:7:23, endln:7:24 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/InterfAlways/dut.sv, line:7:1, endln:9:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/InterfAlways/dut.sv, line:7:1, endln:9:10 |vpiName:o |vpiDirection:2 |vpiLowConn: @@ -256,17 +256,17 @@ design: (work@top) \_int_typespec: , line:7:19, endln:7:22 |vpiSigned:1 |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/InterfAlways/dut.sv, line:7:1, endln:9:10 - |vpiInterface: - \_interface: work@sw_test_status_if (work@top.u_sw), file:${SURELOG_DIR}/tests/InterfAlways/dut.sv, line:8:4, endln:8:34 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/InterfAlways/dut.sv, line:7:1, endln:9:10 + |vpiInterfaceInst: + \_interface_inst: work@sw_test_status_if (work@top.u_sw), file:${SURELOG_DIR}/tests/InterfAlways/dut.sv, line:8:4, endln:8:34 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/InterfAlways/dut.sv, line:7:1, endln:9:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/InterfAlways/dut.sv, line:7:1, endln:9:10 |vpiName:u_sw |vpiFullName:work@top.u_sw |vpiVariables: \_int_var: (work@top.u_sw.x), line:1:40, endln:1:41 |vpiParent: - \_interface: work@sw_test_status_if (work@top.u_sw), file:${SURELOG_DIR}/tests/InterfAlways/dut.sv, line:8:4, endln:8:34 + \_interface_inst: work@sw_test_status_if (work@top.u_sw), file:${SURELOG_DIR}/tests/InterfAlways/dut.sv, line:8:4, endln:8:34 |vpiTypespec: \_int_typespec: , line:1:36, endln:1:39 |vpiSigned:1 @@ -278,13 +278,13 @@ design: (work@top) |vpiDefFile:${SURELOG_DIR}/tests/InterfAlways/dut.sv |vpiDefLineNo:1 |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/InterfAlways/dut.sv, line:7:1, endln:9:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/InterfAlways/dut.sv, line:7:1, endln:9:10 |vpiProcess: \_always: , line:2:4, endln:4:7 |vpiPort: \_port: (x), line:1:40, endln:1:41 |vpiParent: - \_interface: work@sw_test_status_if (work@top.u_sw), file:${SURELOG_DIR}/tests/InterfAlways/dut.sv, line:8:4, endln:8:34 + \_interface_inst: work@sw_test_status_if (work@top.u_sw), file:${SURELOG_DIR}/tests/InterfAlways/dut.sv, line:8:4, endln:8:34 |vpiName:x |vpiDirection:2 |vpiHighConn: diff --git a/tests/InterfArrayBind/InterfArrayBind.log b/tests/InterfArrayBind/InterfArrayBind.log index e9e5b69750..fadf5663c4 100644 --- a/tests/InterfArrayBind/InterfArrayBind.log +++ b/tests/InterfArrayBind/InterfArrayBind.log @@ -236,11 +236,11 @@ gen_scope 4 gen_scope_array 4 hier_path 6 int_typespec 4 -interface 5 +interface_inst 5 logic_net 2 logic_typespec 3 logic_var 2 -module 8 +module_inst 8 operation 7 param_assign 2 parameter 4 @@ -261,11 +261,11 @@ gen_scope 6 gen_scope_array 6 hier_path 9 int_typespec 4 -interface 5 +interface_inst 5 logic_net 2 logic_typespec 3 logic_var 2 -module 8 +module_inst 8 operation 7 param_assign 2 parameter 4 @@ -285,7 +285,7 @@ design: (work@soc_tb) |vpiElaborated:1 |vpiName:work@soc_tb |uhdmallInterfaces: -\_interface: work@io_bus_interface (work@io_bus_interface), file:${SURELOG_DIR}/tests/InterfArrayBind/dut.sv, line:1:1, endln:4:13 +\_interface_inst: work@io_bus_interface (work@io_bus_interface), file:${SURELOG_DIR}/tests/InterfArrayBind/dut.sv, line:1:1, endln:4:13 |vpiParent: \_design: (work@soc_tb) |vpiFullName:work@io_bus_interface @@ -293,19 +293,19 @@ design: (work@soc_tb) |vpiNet: \_logic_net: (work@io_bus_interface.write_en), line:2:11, endln:2:19 |vpiParent: - \_interface: work@io_bus_interface (work@io_bus_interface), file:${SURELOG_DIR}/tests/InterfArrayBind/dut.sv, line:1:1, endln:4:13 + \_interface_inst: work@io_bus_interface (work@io_bus_interface), file:${SURELOG_DIR}/tests/InterfArrayBind/dut.sv, line:1:1, endln:4:13 |vpiName:write_en |vpiFullName:work@io_bus_interface.write_en |vpiNetType:36 |uhdmallModules: -\_module: work@soc_tb (work@soc_tb), file:${SURELOG_DIR}/tests/InterfArrayBind/dut.sv, line:6:1, endln:26:10 +\_module_inst: work@soc_tb (work@soc_tb), file:${SURELOG_DIR}/tests/InterfArrayBind/dut.sv, line:6:1, endln:26:10 |vpiParent: \_design: (work@soc_tb) |vpiFullName:work@soc_tb |vpiParameter: \_parameter: (work@soc_tb.NUM_PERIPHERALS), line:8:16, endln:8:31 |vpiParent: - \_module: work@soc_tb (work@soc_tb), file:${SURELOG_DIR}/tests/InterfArrayBind/dut.sv, line:6:1, endln:26:10 + \_module_inst: work@soc_tb (work@soc_tb), file:${SURELOG_DIR}/tests/InterfArrayBind/dut.sv, line:6:1, endln:26:10 |UINT:2 |vpiTypespec: \_int_typespec: @@ -315,7 +315,7 @@ design: (work@soc_tb) |vpiParamAssign: \_param_assign: , line:8:16, endln:8:35 |vpiParent: - \_module: work@soc_tb (work@soc_tb), file:${SURELOG_DIR}/tests/InterfArrayBind/dut.sv, line:6:1, endln:26:10 + \_module_inst: work@soc_tb (work@soc_tb), file:${SURELOG_DIR}/tests/InterfArrayBind/dut.sv, line:6:1, endln:26:10 |vpiRhs: \_constant: , line:8:34, endln:8:35 |vpiDecompile:2 @@ -330,13 +330,13 @@ design: (work@soc_tb) |vpiNet: \_logic_net: (work@soc_tb.io_bus_source), line:12:7, endln:12:20 |vpiParent: - \_module: work@soc_tb (work@soc_tb), file:${SURELOG_DIR}/tests/InterfArrayBind/dut.sv, line:6:1, endln:26:10 + \_module_inst: work@soc_tb (work@soc_tb), file:${SURELOG_DIR}/tests/InterfArrayBind/dut.sv, line:6:1, endln:26:10 |vpiName:io_bus_source |vpiFullName:work@soc_tb.io_bus_source |vpiContAssign: \_cont_assign: , line:16:12, endln:16:62 |vpiParent: - \_module: work@soc_tb (work@soc_tb), file:${SURELOG_DIR}/tests/InterfArrayBind/dut.sv, line:6:1, endln:26:10 + \_module_inst: work@soc_tb (work@soc_tb), file:${SURELOG_DIR}/tests/InterfArrayBind/dut.sv, line:6:1, endln:26:10 |vpiRhs: \_constant: , line:16:50, endln:16:62 |vpiParent: @@ -370,12 +370,12 @@ design: (work@soc_tb) \_hier_path: (peripheral_io_bus[IO_ONES].write_en), line:16:12, endln:16:29 |vpiName:write_en |uhdmtopModules: -\_module: work@soc_tb (work@soc_tb), file:${SURELOG_DIR}/tests/InterfArrayBind/dut.sv, line:6:1, endln:26:10 +\_module_inst: work@soc_tb (work@soc_tb), file:${SURELOG_DIR}/tests/InterfArrayBind/dut.sv, line:6:1, endln:26:10 |vpiName:work@soc_tb |vpiVariables: \_enum_var: (work@soc_tb.io_bus_source), line:12:7, endln:12:20 |vpiParent: - \_module: work@soc_tb (work@soc_tb), file:${SURELOG_DIR}/tests/InterfArrayBind/dut.sv, line:6:1, endln:26:10 + \_module_inst: work@soc_tb (work@soc_tb), file:${SURELOG_DIR}/tests/InterfArrayBind/dut.sv, line:6:1, endln:26:10 |vpiTypespec: \_enum_typespec: |vpiBaseTypespec: @@ -412,7 +412,7 @@ design: (work@soc_tb) |vpiParameter: \_parameter: (work@soc_tb.NUM_PERIPHERALS), line:8:16, endln:8:31 |vpiParent: - \_module: work@soc_tb (work@soc_tb), file:${SURELOG_DIR}/tests/InterfArrayBind/dut.sv, line:6:1, endln:26:10 + \_module_inst: work@soc_tb (work@soc_tb), file:${SURELOG_DIR}/tests/InterfArrayBind/dut.sv, line:6:1, endln:26:10 |UINT:2 |vpiTypespec: \_int_typespec: @@ -424,7 +424,7 @@ design: (work@soc_tb) |vpiParamAssign: \_param_assign: , line:8:16, endln:8:35 |vpiParent: - \_module: work@soc_tb (work@soc_tb), file:${SURELOG_DIR}/tests/InterfArrayBind/dut.sv, line:6:1, endln:26:10 + \_module_inst: work@soc_tb (work@soc_tb), file:${SURELOG_DIR}/tests/InterfArrayBind/dut.sv, line:6:1, endln:26:10 |vpiRhs: \_constant: , line:8:34, endln:8:35 |vpiDecompile:2 @@ -438,16 +438,16 @@ design: (work@soc_tb) |vpiDefName:work@soc_tb |vpiTop:1 |vpiTopModule:1 - |vpiInterface: - \_interface: work@io_bus_interface (work@soc_tb.peripheral_io_bus[0]), file:${SURELOG_DIR}/tests/InterfArrayBind/dut.sv, line:14:5, endln:14:65 + |vpiInterfaceInst: + \_interface_inst: work@io_bus_interface (work@soc_tb.peripheral_io_bus[0]), file:${SURELOG_DIR}/tests/InterfArrayBind/dut.sv, line:14:5, endln:14:65 |vpiParent: - \_module: work@soc_tb (work@soc_tb), file:${SURELOG_DIR}/tests/InterfArrayBind/dut.sv, line:6:1, endln:26:10 + \_module_inst: work@soc_tb (work@soc_tb), file:${SURELOG_DIR}/tests/InterfArrayBind/dut.sv, line:6:1, endln:26:10 |vpiName:peripheral_io_bus[0] |vpiFullName:work@soc_tb.peripheral_io_bus[0] |vpiVariables: \_logic_var: (work@soc_tb.peripheral_io_bus[0].write_en), line:2:11, endln:2:19 |vpiParent: - \_interface: work@io_bus_interface (work@soc_tb.peripheral_io_bus[0]), file:${SURELOG_DIR}/tests/InterfArrayBind/dut.sv, line:14:5, endln:14:65 + \_interface_inst: work@io_bus_interface (work@soc_tb.peripheral_io_bus[0]), file:${SURELOG_DIR}/tests/InterfArrayBind/dut.sv, line:14:5, endln:14:65 |vpiTypespec: \_logic_typespec: , line:2:5, endln:2:10 |vpiName:write_en @@ -457,17 +457,17 @@ design: (work@soc_tb) |vpiDefFile:${SURELOG_DIR}/tests/InterfArrayBind/dut.sv |vpiDefLineNo:1 |vpiInstance: - \_module: work@soc_tb (work@soc_tb), file:${SURELOG_DIR}/tests/InterfArrayBind/dut.sv, line:6:1, endln:26:10 - |vpiInterface: - \_interface: work@io_bus_interface (work@soc_tb.peripheral_io_bus[1]), file:${SURELOG_DIR}/tests/InterfArrayBind/dut.sv, line:14:5, endln:14:65 + \_module_inst: work@soc_tb (work@soc_tb), file:${SURELOG_DIR}/tests/InterfArrayBind/dut.sv, line:6:1, endln:26:10 + |vpiInterfaceInst: + \_interface_inst: work@io_bus_interface (work@soc_tb.peripheral_io_bus[1]), file:${SURELOG_DIR}/tests/InterfArrayBind/dut.sv, line:14:5, endln:14:65 |vpiParent: - \_module: work@soc_tb (work@soc_tb), file:${SURELOG_DIR}/tests/InterfArrayBind/dut.sv, line:6:1, endln:26:10 + \_module_inst: work@soc_tb (work@soc_tb), file:${SURELOG_DIR}/tests/InterfArrayBind/dut.sv, line:6:1, endln:26:10 |vpiName:peripheral_io_bus[1] |vpiFullName:work@soc_tb.peripheral_io_bus[1] |vpiVariables: \_logic_var: (work@soc_tb.peripheral_io_bus[1].write_en), line:2:11, endln:2:19 |vpiParent: - \_interface: work@io_bus_interface (work@soc_tb.peripheral_io_bus[1]), file:${SURELOG_DIR}/tests/InterfArrayBind/dut.sv, line:14:5, endln:14:65 + \_interface_inst: work@io_bus_interface (work@soc_tb.peripheral_io_bus[1]), file:${SURELOG_DIR}/tests/InterfArrayBind/dut.sv, line:14:5, endln:14:65 |vpiTypespec: \_logic_typespec: , line:2:5, endln:2:10 |vpiName:write_en @@ -477,11 +477,11 @@ design: (work@soc_tb) |vpiDefFile:${SURELOG_DIR}/tests/InterfArrayBind/dut.sv |vpiDefLineNo:1 |vpiInstance: - \_module: work@soc_tb (work@soc_tb), file:${SURELOG_DIR}/tests/InterfArrayBind/dut.sv, line:6:1, endln:26:10 + \_module_inst: work@soc_tb (work@soc_tb), file:${SURELOG_DIR}/tests/InterfArrayBind/dut.sv, line:6:1, endln:26:10 |vpiGenScopeArray: \_gen_scope_array: (work@soc_tb.io_gen[0]), line:21:9, endln:23:12 |vpiParent: - \_module: work@soc_tb (work@soc_tb), file:${SURELOG_DIR}/tests/InterfArrayBind/dut.sv, line:6:1, endln:26:10 + \_module_inst: work@soc_tb (work@soc_tb), file:${SURELOG_DIR}/tests/InterfArrayBind/dut.sv, line:6:1, endln:26:10 |vpiName:io_gen[0] |vpiFullName:work@soc_tb.io_gen[0] |vpiGenScope: @@ -534,7 +534,7 @@ design: (work@soc_tb) |vpiActual: \_parameter: (work@soc_tb.io_gen[0].io_idx), line:20:0 |vpiActual: - \_interface: work@io_bus_interface (work@soc_tb.peripheral_io_bus[0]), file:${SURELOG_DIR}/tests/InterfArrayBind/dut.sv, line:14:5, endln:14:65 + \_interface_inst: work@io_bus_interface (work@soc_tb.peripheral_io_bus[0]), file:${SURELOG_DIR}/tests/InterfArrayBind/dut.sv, line:14:5, endln:14:65 |vpiActual: \_ref_obj: (write_en) |vpiParent: @@ -545,7 +545,7 @@ design: (work@soc_tb) |vpiGenScopeArray: \_gen_scope_array: (work@soc_tb.io_gen[1]), line:21:9, endln:23:12 |vpiParent: - \_module: work@soc_tb (work@soc_tb), file:${SURELOG_DIR}/tests/InterfArrayBind/dut.sv, line:6:1, endln:26:10 + \_module_inst: work@soc_tb (work@soc_tb), file:${SURELOG_DIR}/tests/InterfArrayBind/dut.sv, line:6:1, endln:26:10 |vpiName:io_gen[1] |vpiFullName:work@soc_tb.io_gen[1] |vpiGenScope: @@ -598,7 +598,7 @@ design: (work@soc_tb) |vpiActual: \_parameter: (work@soc_tb.io_gen[1].io_idx), line:20:0 |vpiActual: - \_interface: work@io_bus_interface (work@soc_tb.peripheral_io_bus[1]), file:${SURELOG_DIR}/tests/InterfArrayBind/dut.sv, line:14:5, endln:14:65 + \_interface_inst: work@io_bus_interface (work@soc_tb.peripheral_io_bus[1]), file:${SURELOG_DIR}/tests/InterfArrayBind/dut.sv, line:14:5, endln:14:65 |vpiActual: \_ref_obj: (write_en) |vpiParent: @@ -609,7 +609,7 @@ design: (work@soc_tb) |vpiContAssign: \_cont_assign: , line:16:12, endln:16:62 |vpiParent: - \_module: work@soc_tb (work@soc_tb), file:${SURELOG_DIR}/tests/InterfArrayBind/dut.sv, line:6:1, endln:26:10 + \_module_inst: work@soc_tb (work@soc_tb), file:${SURELOG_DIR}/tests/InterfArrayBind/dut.sv, line:6:1, endln:26:10 |vpiRhs: \_constant: , line:16:50, endln:16:62 |vpiLhs: @@ -635,7 +635,7 @@ design: (work@soc_tb) |vpiActual: \_enum_const: (IO_ONES), line:11:7, endln:11:14 |vpiActual: - \_interface: work@io_bus_interface (work@soc_tb.peripheral_io_bus[0]), file:${SURELOG_DIR}/tests/InterfArrayBind/dut.sv, line:14:5, endln:14:65 + \_interface_inst: work@io_bus_interface (work@soc_tb.peripheral_io_bus[0]), file:${SURELOG_DIR}/tests/InterfArrayBind/dut.sv, line:14:5, endln:14:65 |vpiActual: \_ref_obj: (write_en) |vpiParent: diff --git a/tests/InterfBinding/InterfBinding.log b/tests/InterfBinding/InterfBinding.log index 443c0ecd8f..d9de060bb8 100644 --- a/tests/InterfBinding/InterfBinding.log +++ b/tests/InterfBinding/InterfBinding.log @@ -145,14 +145,14 @@ n<> u<110> t c<1> l<1:1> el<37:1> cont_assign 1 design 1 hier_path 1 -interface 2 +interface_inst 2 interface_typespec 6 io_decl 2 logic_net 6 logic_typespec 7 logic_var 1 modport 2 -module 3 +module_inst 3 package 3 port 6 ref_obj 9 @@ -166,14 +166,14 @@ typespec_member 4 cont_assign 2 design 1 hier_path 2 -interface 2 +interface_inst 2 interface_typespec 6 io_decl 2 logic_net 6 logic_typespec 7 logic_var 1 modport 2 -module 3 +module_inst 3 package 3 port 7 ref_obj 13 @@ -202,7 +202,7 @@ design: (work@BypassNetwork) |vpiTypedef: \_struct_typespec: (pack::PipelineControll), line:2:9, endln:2:15 |vpiParent: - \_module: work@BypassNetwork (work@BypassNetwork), file:${SURELOG_DIR}/tests/InterfBinding/dut.sv, line:29:1, endln:36:10 + \_module_inst: work@BypassNetwork (work@BypassNetwork), file:${SURELOG_DIR}/tests/InterfBinding/dut.sv, line:29:1, endln:36:10 |vpiName:pack::PipelineControll |vpiInstance: \_package: pack (pack::), file:${SURELOG_DIR}/tests/InterfBinding/dut.sv, line:1:1, endln:8:11 @@ -251,7 +251,7 @@ design: (work@BypassNetwork) |vpiDefName:pack |vpiTop:1 |uhdmallInterfaces: -\_interface: work@ControllerIF (work@ControllerIF), file:${SURELOG_DIR}/tests/InterfBinding/dut.sv, line:12:1, endln:25:13 +\_interface_inst: work@ControllerIF (work@ControllerIF), file:${SURELOG_DIR}/tests/InterfBinding/dut.sv, line:12:1, endln:25:13 |vpiParent: \_design: (work@BypassNetwork) |vpiFullName:work@ControllerIF @@ -261,27 +261,27 @@ design: (work@BypassNetwork) |vpiNet: \_logic_net: (work@ControllerIF.clk), line:14:14, endln:14:17 |vpiParent: - \_interface: work@ControllerIF (work@ControllerIF), file:${SURELOG_DIR}/tests/InterfBinding/dut.sv, line:12:1, endln:25:13 + \_interface_inst: work@ControllerIF (work@ControllerIF), file:${SURELOG_DIR}/tests/InterfBinding/dut.sv, line:12:1, endln:25:13 |vpiName:clk |vpiFullName:work@ControllerIF.clk |vpiNetType:36 |vpiNet: \_logic_net: (work@ControllerIF.backEnd), line:18:21, endln:18:28 |vpiParent: - \_interface: work@ControllerIF (work@ControllerIF), file:${SURELOG_DIR}/tests/InterfBinding/dut.sv, line:12:1, endln:25:13 + \_interface_inst: work@ControllerIF (work@ControllerIF), file:${SURELOG_DIR}/tests/InterfBinding/dut.sv, line:12:1, endln:25:13 |vpiName:backEnd |vpiFullName:work@ControllerIF.backEnd |vpiNet: \_logic_net: (work@ControllerIF.rst), line:15:14, endln:15:17 |vpiParent: - \_interface: work@ControllerIF (work@ControllerIF), file:${SURELOG_DIR}/tests/InterfBinding/dut.sv, line:12:1, endln:25:13 + \_interface_inst: work@ControllerIF (work@ControllerIF), file:${SURELOG_DIR}/tests/InterfBinding/dut.sv, line:12:1, endln:25:13 |vpiName:rst |vpiFullName:work@ControllerIF.rst |vpiNetType:36 |vpiModport: \_modport: (BypassNetwork), line:20:12, endln:20:25 |vpiParent: - \_interface: work@ControllerIF (work@ControllerIF), file:${SURELOG_DIR}/tests/InterfBinding/dut.sv, line:12:1, endln:25:13 + \_interface_inst: work@ControllerIF (work@ControllerIF), file:${SURELOG_DIR}/tests/InterfBinding/dut.sv, line:12:1, endln:25:13 |vpiName:BypassNetwork |vpiIODecl: \_io_decl: (backEnd), line:22:11, endln:22:18 @@ -290,7 +290,7 @@ design: (work@BypassNetwork) |vpiPort: \_port: (clk), line:14:14, endln:14:17 |vpiParent: - \_interface: work@ControllerIF (work@ControllerIF), file:${SURELOG_DIR}/tests/InterfBinding/dut.sv, line:12:1, endln:25:13 + \_interface_inst: work@ControllerIF (work@ControllerIF), file:${SURELOG_DIR}/tests/InterfBinding/dut.sv, line:12:1, endln:25:13 |vpiName:clk |vpiDirection:1 |vpiLowConn: @@ -300,7 +300,7 @@ design: (work@BypassNetwork) |vpiPort: \_port: (rst), line:15:14, endln:15:17 |vpiParent: - \_interface: work@ControllerIF (work@ControllerIF), file:${SURELOG_DIR}/tests/InterfBinding/dut.sv, line:12:1, endln:25:13 + \_interface_inst: work@ControllerIF (work@ControllerIF), file:${SURELOG_DIR}/tests/InterfBinding/dut.sv, line:12:1, endln:25:13 |vpiName:rst |vpiDirection:1 |vpiLowConn: @@ -308,7 +308,7 @@ design: (work@BypassNetwork) |vpiActual: \_logic_net: (work@ControllerIF.rst), line:15:14, endln:15:17 |uhdmallModules: -\_module: work@BypassNetwork (work@BypassNetwork), file:${SURELOG_DIR}/tests/InterfBinding/dut.sv, line:29:1, endln:36:10 +\_module_inst: work@BypassNetwork (work@BypassNetwork), file:${SURELOG_DIR}/tests/InterfBinding/dut.sv, line:29:1, endln:36:10 |vpiParent: \_design: (work@BypassNetwork) |vpiFullName:work@BypassNetwork @@ -318,13 +318,13 @@ design: (work@BypassNetwork) |vpiNet: \_logic_net: (work@BypassNetwork.ctrl), line:30:32, endln:30:36 |vpiParent: - \_module: work@BypassNetwork (work@BypassNetwork), file:${SURELOG_DIR}/tests/InterfBinding/dut.sv, line:29:1, endln:36:10 + \_module_inst: work@BypassNetwork (work@BypassNetwork), file:${SURELOG_DIR}/tests/InterfBinding/dut.sv, line:29:1, endln:36:10 |vpiName:ctrl |vpiFullName:work@BypassNetwork.ctrl |vpiPort: \_port: (ctrl), line:30:32, endln:30:36 |vpiParent: - \_module: work@BypassNetwork (work@BypassNetwork), file:${SURELOG_DIR}/tests/InterfBinding/dut.sv, line:29:1, endln:36:10 + \_module_inst: work@BypassNetwork (work@BypassNetwork), file:${SURELOG_DIR}/tests/InterfBinding/dut.sv, line:29:1, endln:36:10 |vpiName:ctrl |vpiDirection:3 |vpiLowConn: @@ -340,7 +340,7 @@ design: (work@BypassNetwork) |vpiContAssign: \_cont_assign: , line:33:9, endln:33:25 |vpiParent: - \_module: work@BypassNetwork (work@BypassNetwork), file:${SURELOG_DIR}/tests/InterfBinding/dut.sv, line:29:1, endln:36:10 + \_module_inst: work@BypassNetwork (work@BypassNetwork), file:${SURELOG_DIR}/tests/InterfBinding/dut.sv, line:29:1, endln:36:10 |vpiRhs: \_hier_path: (ctrl.backEnd), line:33:13, endln:33:25 |vpiParent: @@ -363,7 +363,7 @@ design: (work@BypassNetwork) |vpiActual: \_logic_net: (o) |uhdmtopModules: -\_module: work@BypassNetwork (work@BypassNetwork), file:${SURELOG_DIR}/tests/InterfBinding/dut.sv, line:29:1, endln:36:10 +\_module_inst: work@BypassNetwork (work@BypassNetwork), file:${SURELOG_DIR}/tests/InterfBinding/dut.sv, line:29:1, endln:36:10 |vpiName:work@BypassNetwork |vpiTypedef: \_struct_typespec: (pack::PipelineControll), line:2:9, endln:2:15 @@ -377,7 +377,7 @@ design: (work@BypassNetwork) |vpiPort: \_port: (ctrl), line:30:32, endln:30:36 |vpiParent: - \_module: work@BypassNetwork (work@BypassNetwork), file:${SURELOG_DIR}/tests/InterfBinding/dut.sv, line:29:1, endln:36:10 + \_module_inst: work@BypassNetwork (work@BypassNetwork), file:${SURELOG_DIR}/tests/InterfBinding/dut.sv, line:29:1, endln:36:10 |vpiName:ctrl |vpiDirection:3 |vpiLowConn: @@ -394,18 +394,18 @@ design: (work@BypassNetwork) |vpiName:BypassNetwork |vpiIsModPort:1 |vpiInstance: - \_module: work@BypassNetwork (work@BypassNetwork), file:${SURELOG_DIR}/tests/InterfBinding/dut.sv, line:29:1, endln:36:10 - |vpiInterface: - \_interface: work@ControllerIF (work@BypassNetwork.ctrl), file:${SURELOG_DIR}/tests/InterfBinding/dut.sv, line:29:0 + \_module_inst: work@BypassNetwork (work@BypassNetwork), file:${SURELOG_DIR}/tests/InterfBinding/dut.sv, line:29:1, endln:36:10 + |vpiInterfaceInst: + \_interface_inst: work@ControllerIF (work@BypassNetwork.ctrl), file:${SURELOG_DIR}/tests/InterfBinding/dut.sv, line:29:0 |vpiParent: - \_module: work@BypassNetwork (work@BypassNetwork), file:${SURELOG_DIR}/tests/InterfBinding/dut.sv, line:29:1, endln:36:10 + \_module_inst: work@BypassNetwork (work@BypassNetwork), file:${SURELOG_DIR}/tests/InterfBinding/dut.sv, line:29:1, endln:36:10 |vpiName:ctrl |vpiFullName:work@BypassNetwork.ctrl |vpiDefName:work@ControllerIF |vpiModport: \_modport: (BypassNetwork), line:20:12, endln:20:25 |vpiParent: - \_interface: work@ControllerIF (work@BypassNetwork.ctrl), file:${SURELOG_DIR}/tests/InterfBinding/dut.sv, line:29:0 + \_interface_inst: work@ControllerIF (work@BypassNetwork.ctrl), file:${SURELOG_DIR}/tests/InterfBinding/dut.sv, line:29:0 |vpiName:BypassNetwork |vpiIODecl: \_io_decl: (backEnd), line:22:11, endln:22:18 @@ -416,12 +416,12 @@ design: (work@BypassNetwork) |vpiTypespec: \_struct_typespec: (pack::PipelineControll), line:2:9, endln:2:15 |vpiName:backEnd - |vpiInterface: - \_interface: work@ControllerIF (work@BypassNetwork.ctrl), file:${SURELOG_DIR}/tests/InterfBinding/dut.sv, line:29:0 + |vpiInterfaceInst: + \_interface_inst: work@ControllerIF (work@BypassNetwork.ctrl), file:${SURELOG_DIR}/tests/InterfBinding/dut.sv, line:29:0 |vpiContAssign: \_cont_assign: , line:33:9, endln:33:25 |vpiParent: - \_module: work@BypassNetwork (work@BypassNetwork), file:${SURELOG_DIR}/tests/InterfBinding/dut.sv, line:29:1, endln:36:10 + \_module_inst: work@BypassNetwork (work@BypassNetwork), file:${SURELOG_DIR}/tests/InterfBinding/dut.sv, line:29:1, endln:36:10 |vpiRhs: \_hier_path: (ctrl.backEnd), line:33:13, endln:33:25 |vpiParent: @@ -433,7 +433,7 @@ design: (work@BypassNetwork) \_hier_path: (ctrl.backEnd), line:33:13, endln:33:25 |vpiName:ctrl |vpiActual: - \_interface: work@ControllerIF (work@BypassNetwork.ctrl), file:${SURELOG_DIR}/tests/InterfBinding/dut.sv, line:29:0 + \_interface_inst: work@ControllerIF (work@BypassNetwork.ctrl), file:${SURELOG_DIR}/tests/InterfBinding/dut.sv, line:29:0 |vpiActual: \_ref_obj: (backEnd), line:33:18, endln:33:25 |vpiParent: diff --git a/tests/InterfHierPath/InterfHierPath.log b/tests/InterfHierPath/InterfHierPath.log index 5b686705a7..b93b71e2fb 100644 --- a/tests/InterfHierPath/InterfHierPath.log +++ b/tests/InterfHierPath/InterfHierPath.log @@ -113,11 +113,11 @@ constant 12 cont_assign 1 design 1 hier_path 1 -interface 3 +interface_inst 3 logic_net 3 logic_typespec 4 logic_var 1 -module 5 +module_inst 5 port 2 range 6 ref_obj 5 @@ -129,11 +129,11 @@ constant 12 cont_assign 2 design 1 hier_path 2 -interface 3 +interface_inst 3 logic_net 3 logic_typespec 4 logic_var 1 -module 5 +module_inst 5 port 3 range 6 ref_obj 9 @@ -151,7 +151,7 @@ design: (work@or_ex) |vpiElaborated:1 |vpiName:work@or_ex |uhdmallInterfaces: -\_interface: work@logic_gate_if (work@logic_gate_if), file:${SURELOG_DIR}/tests/InterfHierPath/dut.sv, line:1:1, endln:5:13 +\_interface_inst: work@logic_gate_if (work@logic_gate_if), file:${SURELOG_DIR}/tests/InterfHierPath/dut.sv, line:1:1, endln:5:13 |vpiParent: \_design: (work@or_ex) |vpiFullName:work@logic_gate_if @@ -159,12 +159,12 @@ design: (work@or_ex) |vpiNet: \_logic_net: (work@logic_gate_if.a), line:3:12, endln:3:13 |vpiParent: - \_interface: work@logic_gate_if (work@logic_gate_if), file:${SURELOG_DIR}/tests/InterfHierPath/dut.sv, line:1:1, endln:5:13 + \_interface_inst: work@logic_gate_if (work@logic_gate_if), file:${SURELOG_DIR}/tests/InterfHierPath/dut.sv, line:1:1, endln:5:13 |vpiName:a |vpiFullName:work@logic_gate_if.a |vpiNetType:36 |uhdmallModules: -\_module: work@or_ex (work@or_ex), file:${SURELOG_DIR}/tests/InterfHierPath/dut.sv, line:8:1, endln:16:10 +\_module_inst: work@or_ex (work@or_ex), file:${SURELOG_DIR}/tests/InterfHierPath/dut.sv, line:8:1, endln:16:10 |vpiParent: \_design: (work@or_ex) |vpiFullName:work@or_ex @@ -172,14 +172,14 @@ design: (work@or_ex) |vpiNet: \_logic_net: (work@or_ex.a), line:9:22, endln:9:23 |vpiParent: - \_module: work@or_ex (work@or_ex), file:${SURELOG_DIR}/tests/InterfHierPath/dut.sv, line:8:1, endln:16:10 + \_module_inst: work@or_ex (work@or_ex), file:${SURELOG_DIR}/tests/InterfHierPath/dut.sv, line:8:1, endln:16:10 |vpiName:a |vpiFullName:work@or_ex.a |vpiNetType:36 |vpiPort: \_port: (a), line:9:22, endln:9:23 |vpiParent: - \_module: work@or_ex (work@or_ex), file:${SURELOG_DIR}/tests/InterfHierPath/dut.sv, line:8:1, endln:16:10 + \_module_inst: work@or_ex (work@or_ex), file:${SURELOG_DIR}/tests/InterfHierPath/dut.sv, line:8:1, endln:16:10 |vpiName:a |vpiDirection:1 |vpiLowConn: @@ -209,7 +209,7 @@ design: (work@or_ex) |vpiContAssign: \_cont_assign: , line:14:10, endln:14:18 |vpiParent: - \_module: work@or_ex (work@or_ex), file:${SURELOG_DIR}/tests/InterfHierPath/dut.sv, line:8:1, endln:16:10 + \_module_inst: work@or_ex (work@or_ex), file:${SURELOG_DIR}/tests/InterfHierPath/dut.sv, line:8:1, endln:16:10 |vpiRhs: \_ref_obj: (work@or_ex.a), line:14:17, endln:14:18 |vpiParent: @@ -232,14 +232,14 @@ design: (work@or_ex) \_ref_obj: (a) |vpiName:a |uhdmtopModules: -\_module: work@or_ex (work@or_ex), file:${SURELOG_DIR}/tests/InterfHierPath/dut.sv, line:8:1, endln:16:10 +\_module_inst: work@or_ex (work@or_ex), file:${SURELOG_DIR}/tests/InterfHierPath/dut.sv, line:8:1, endln:16:10 |vpiName:work@or_ex |vpiDefName:work@or_ex |vpiTop:1 |vpiNet: \_logic_net: (work@or_ex.a), line:9:22, endln:9:23 |vpiParent: - \_module: work@or_ex (work@or_ex), file:${SURELOG_DIR}/tests/InterfHierPath/dut.sv, line:8:1, endln:16:10 + \_module_inst: work@or_ex (work@or_ex), file:${SURELOG_DIR}/tests/InterfHierPath/dut.sv, line:8:1, endln:16:10 |vpiTypespec: \_logic_typespec: , line:9:11, endln:9:21 |vpiRange: @@ -267,7 +267,7 @@ design: (work@or_ex) |vpiPort: \_port: (a), line:9:22, endln:9:23 |vpiParent: - \_module: work@or_ex (work@or_ex), file:${SURELOG_DIR}/tests/InterfHierPath/dut.sv, line:8:1, endln:16:10 + \_module_inst: work@or_ex (work@or_ex), file:${SURELOG_DIR}/tests/InterfHierPath/dut.sv, line:8:1, endln:16:10 |vpiName:a |vpiDirection:1 |vpiLowConn: @@ -301,17 +301,17 @@ design: (work@or_ex) |UINT:0 |vpiConstType:9 |vpiInstance: - \_module: work@or_ex (work@or_ex), file:${SURELOG_DIR}/tests/InterfHierPath/dut.sv, line:8:1, endln:16:10 - |vpiInterface: - \_interface: work@logic_gate_if (work@or_ex.lg), file:${SURELOG_DIR}/tests/InterfHierPath/dut.sv, line:12:3, endln:12:23 + \_module_inst: work@or_ex (work@or_ex), file:${SURELOG_DIR}/tests/InterfHierPath/dut.sv, line:8:1, endln:16:10 + |vpiInterfaceInst: + \_interface_inst: work@logic_gate_if (work@or_ex.lg), file:${SURELOG_DIR}/tests/InterfHierPath/dut.sv, line:12:3, endln:12:23 |vpiParent: - \_module: work@or_ex (work@or_ex), file:${SURELOG_DIR}/tests/InterfHierPath/dut.sv, line:8:1, endln:16:10 + \_module_inst: work@or_ex (work@or_ex), file:${SURELOG_DIR}/tests/InterfHierPath/dut.sv, line:8:1, endln:16:10 |vpiName:lg |vpiFullName:work@or_ex.lg |vpiVariables: \_logic_var: (work@or_ex.lg.a), line:3:12, endln:3:13 |vpiParent: - \_interface: work@logic_gate_if (work@or_ex.lg), file:${SURELOG_DIR}/tests/InterfHierPath/dut.sv, line:12:3, endln:12:23 + \_interface_inst: work@logic_gate_if (work@or_ex.lg), file:${SURELOG_DIR}/tests/InterfHierPath/dut.sv, line:12:3, endln:12:23 |vpiTypespec: \_logic_typespec: , line:3:1, endln:3:11 |vpiRange: @@ -357,11 +357,11 @@ design: (work@or_ex) |vpiDefFile:${SURELOG_DIR}/tests/InterfHierPath/dut.sv |vpiDefLineNo:1 |vpiInstance: - \_module: work@or_ex (work@or_ex), file:${SURELOG_DIR}/tests/InterfHierPath/dut.sv, line:8:1, endln:16:10 + \_module_inst: work@or_ex (work@or_ex), file:${SURELOG_DIR}/tests/InterfHierPath/dut.sv, line:8:1, endln:16:10 |vpiContAssign: \_cont_assign: , line:14:10, endln:14:18 |vpiParent: - \_module: work@or_ex (work@or_ex), file:${SURELOG_DIR}/tests/InterfHierPath/dut.sv, line:8:1, endln:16:10 + \_module_inst: work@or_ex (work@or_ex), file:${SURELOG_DIR}/tests/InterfHierPath/dut.sv, line:8:1, endln:16:10 |vpiRhs: \_ref_obj: (work@or_ex.a), line:14:17, endln:14:18 |vpiParent: @@ -381,7 +381,7 @@ design: (work@or_ex) \_hier_path: (lg.a), line:14:10, endln:14:14 |vpiName:lg |vpiActual: - \_interface: work@logic_gate_if (work@or_ex.lg), file:${SURELOG_DIR}/tests/InterfHierPath/dut.sv, line:12:3, endln:12:23 + \_interface_inst: work@logic_gate_if (work@or_ex.lg), file:${SURELOG_DIR}/tests/InterfHierPath/dut.sv, line:12:3, endln:12:23 |vpiActual: \_ref_obj: (a) |vpiParent: diff --git a/tests/InterfImport/InterfImport.log b/tests/InterfImport/InterfImport.log index be60df4902..3a09f53d55 100644 --- a/tests/InterfImport/InterfImport.log +++ b/tests/InterfImport/InterfImport.log @@ -295,11 +295,11 @@ design 1 hier_path 1 import_typespec 1 int_typespec 7 -interface 1 +interface_inst 1 io_decl 10 logic_net 5 modport 2 -module 3 +module_inst 3 package 3 param_assign 7 parameter 8 @@ -314,11 +314,11 @@ design 1 hier_path 1 import_typespec 1 int_typespec 7 -interface 1 +interface_inst 1 io_decl 10 logic_net 5 modport 2 -module 3 +module_inst 3 package 3 param_assign 7 parameter 8 @@ -401,14 +401,14 @@ design: (unnamed) |vpiDefName:tnoc_pkg |vpiTop:1 |uhdmallInterfaces: -\_interface: work@tnoc_port_control_if (work@tnoc_port_control_if), file:${SURELOG_DIR}/tests/InterfImport/dut.sv, line:6:1, endln:34:13 +\_interface_inst: work@tnoc_port_control_if (work@tnoc_port_control_if), file:${SURELOG_DIR}/tests/InterfImport/dut.sv, line:6:1, endln:34:13 |vpiParent: \_design: (unnamed) |vpiFullName:work@tnoc_port_control_if |vpiParameter: \_parameter: (work@tnoc_port_control_if.TNOC_DEFAULT_PACKET_CONFIG), line:2:15, endln:2:41 |vpiParent: - \_interface: work@tnoc_port_control_if (work@tnoc_port_control_if), file:${SURELOG_DIR}/tests/InterfImport/dut.sv, line:6:1, endln:34:13 + \_interface_inst: work@tnoc_port_control_if (work@tnoc_port_control_if), file:${SURELOG_DIR}/tests/InterfImport/dut.sv, line:6:1, endln:34:13 |UINT:1 |vpiTypespec: \_int_typespec: @@ -421,7 +421,7 @@ design: (unnamed) |vpiParameter: \_parameter: (work@tnoc_port_control_if.PACKET_CONFIG), line:9:33, endln:9:46 |vpiParent: - \_interface: work@tnoc_port_control_if (work@tnoc_port_control_if), file:${SURELOG_DIR}/tests/InterfImport/dut.sv, line:6:1, endln:34:13 + \_interface_inst: work@tnoc_port_control_if (work@tnoc_port_control_if), file:${SURELOG_DIR}/tests/InterfImport/dut.sv, line:6:1, endln:34:13 |UINT:1 |vpiTypespec: \_unsupported_typespec: (tnoc_packet_config), line:9:13, endln:9:31 @@ -433,7 +433,7 @@ design: (unnamed) |vpiParameter: \_parameter: (work@tnoc_port_control_if.CHANNELS), line:11:19, endln:11:27 |vpiParent: - \_interface: work@tnoc_port_control_if (work@tnoc_port_control_if), file:${SURELOG_DIR}/tests/InterfImport/dut.sv, line:6:1, endln:34:13 + \_interface_inst: work@tnoc_port_control_if (work@tnoc_port_control_if), file:${SURELOG_DIR}/tests/InterfImport/dut.sv, line:6:1, endln:34:13 |vpiTypespec: \_int_typespec: , line:11:15, endln:11:18 |vpiParent: @@ -446,7 +446,7 @@ design: (unnamed) |vpiParamAssign: \_param_assign: , line:2:15, endln:2:46 |vpiParent: - \_interface: work@tnoc_port_control_if (work@tnoc_port_control_if), file:${SURELOG_DIR}/tests/InterfImport/dut.sv, line:6:1, endln:34:13 + \_interface_inst: work@tnoc_port_control_if (work@tnoc_port_control_if), file:${SURELOG_DIR}/tests/InterfImport/dut.sv, line:6:1, endln:34:13 |vpiRhs: \_constant: , line:2:45, endln:2:46 |vpiParent: @@ -475,7 +475,7 @@ design: (unnamed) |vpiParamAssign: \_param_assign: , line:9:33, endln:9:76 |vpiParent: - \_interface: work@tnoc_port_control_if (work@tnoc_port_control_if), file:${SURELOG_DIR}/tests/InterfImport/dut.sv, line:6:1, endln:34:13 + \_interface_inst: work@tnoc_port_control_if (work@tnoc_port_control_if), file:${SURELOG_DIR}/tests/InterfImport/dut.sv, line:6:1, endln:34:13 |vpiRhs: \_constant: , line:9:50, endln:9:76 |vpiDecompile:1 @@ -489,7 +489,7 @@ design: (unnamed) |vpiParamAssign: \_param_assign: , line:11:19, endln:11:61 |vpiParent: - \_interface: work@tnoc_port_control_if (work@tnoc_port_control_if), file:${SURELOG_DIR}/tests/InterfImport/dut.sv, line:6:1, endln:34:13 + \_interface_inst: work@tnoc_port_control_if (work@tnoc_port_control_if), file:${SURELOG_DIR}/tests/InterfImport/dut.sv, line:6:1, endln:34:13 |vpiRhs: \_hier_path: (PACKET_CONFIG.virtual_channels), line:11:31, endln:11:61 |vpiName:PACKET_CONFIG.virtual_channels @@ -509,42 +509,42 @@ design: (unnamed) |vpiNet: \_logic_net: (work@tnoc_port_control_if.request), line:13:25, endln:13:32 |vpiParent: - \_interface: work@tnoc_port_control_if (work@tnoc_port_control_if), file:${SURELOG_DIR}/tests/InterfImport/dut.sv, line:6:1, endln:34:13 + \_interface_inst: work@tnoc_port_control_if (work@tnoc_port_control_if), file:${SURELOG_DIR}/tests/InterfImport/dut.sv, line:6:1, endln:34:13 |vpiName:request |vpiFullName:work@tnoc_port_control_if.request |vpiNetType:36 |vpiNet: \_logic_net: (work@tnoc_port_control_if.grant), line:14:25, endln:14:30 |vpiParent: - \_interface: work@tnoc_port_control_if (work@tnoc_port_control_if), file:${SURELOG_DIR}/tests/InterfImport/dut.sv, line:6:1, endln:34:13 + \_interface_inst: work@tnoc_port_control_if (work@tnoc_port_control_if), file:${SURELOG_DIR}/tests/InterfImport/dut.sv, line:6:1, endln:34:13 |vpiName:grant |vpiFullName:work@tnoc_port_control_if.grant |vpiNetType:36 |vpiNet: \_logic_net: (work@tnoc_port_control_if.free), line:15:25, endln:15:29 |vpiParent: - \_interface: work@tnoc_port_control_if (work@tnoc_port_control_if), file:${SURELOG_DIR}/tests/InterfImport/dut.sv, line:6:1, endln:34:13 + \_interface_inst: work@tnoc_port_control_if (work@tnoc_port_control_if), file:${SURELOG_DIR}/tests/InterfImport/dut.sv, line:6:1, endln:34:13 |vpiName:free |vpiFullName:work@tnoc_port_control_if.free |vpiNetType:36 |vpiNet: \_logic_net: (work@tnoc_port_control_if.start_of_packet), line:16:25, endln:16:40 |vpiParent: - \_interface: work@tnoc_port_control_if (work@tnoc_port_control_if), file:${SURELOG_DIR}/tests/InterfImport/dut.sv, line:6:1, endln:34:13 + \_interface_inst: work@tnoc_port_control_if (work@tnoc_port_control_if), file:${SURELOG_DIR}/tests/InterfImport/dut.sv, line:6:1, endln:34:13 |vpiName:start_of_packet |vpiFullName:work@tnoc_port_control_if.start_of_packet |vpiNetType:36 |vpiNet: \_logic_net: (work@tnoc_port_control_if.end_of_packet), line:17:25, endln:17:38 |vpiParent: - \_interface: work@tnoc_port_control_if (work@tnoc_port_control_if), file:${SURELOG_DIR}/tests/InterfImport/dut.sv, line:6:1, endln:34:13 + \_interface_inst: work@tnoc_port_control_if (work@tnoc_port_control_if), file:${SURELOG_DIR}/tests/InterfImport/dut.sv, line:6:1, endln:34:13 |vpiName:end_of_packet |vpiFullName:work@tnoc_port_control_if.end_of_packet |vpiNetType:36 |vpiModport: \_modport: (controller), line:27:11, endln:27:21 |vpiParent: - \_interface: work@tnoc_port_control_if (work@tnoc_port_control_if), file:${SURELOG_DIR}/tests/InterfImport/dut.sv, line:6:1, endln:34:13 + \_interface_inst: work@tnoc_port_control_if (work@tnoc_port_control_if), file:${SURELOG_DIR}/tests/InterfImport/dut.sv, line:6:1, endln:34:13 |vpiName:controller |vpiIODecl: \_io_decl: (request), line:28:13, endln:28:20 @@ -569,7 +569,7 @@ design: (unnamed) |vpiModport: \_modport: (requester), line:19:11, endln:19:20 |vpiParent: - \_interface: work@tnoc_port_control_if (work@tnoc_port_control_if), file:${SURELOG_DIR}/tests/InterfImport/dut.sv, line:6:1, endln:34:13 + \_interface_inst: work@tnoc_port_control_if (work@tnoc_port_control_if), file:${SURELOG_DIR}/tests/InterfImport/dut.sv, line:6:1, endln:34:13 |vpiName:requester |vpiIODecl: \_io_decl: (request), line:20:13, endln:20:20 diff --git a/tests/InterfType/InterfType.log b/tests/InterfType/InterfType.log index 3039485a5d..0e0761f48d 100644 --- a/tests/InterfType/InterfType.log +++ b/tests/InterfType/InterfType.log @@ -115,10 +115,10 @@ n<> u<80> t c<1> l<1:1> el<20:1> constant 3 design 1 int_typespec 2 -interface 7 +interface_inst 7 interface_typespec 2 logic_net 1 -module 6 +module_inst 6 param_assign 2 parameter 2 port 2 @@ -130,10 +130,10 @@ ref_obj 3 constant 3 design 1 int_typespec 2 -interface 7 +interface_inst 7 interface_typespec 2 logic_net 1 -module 6 +module_inst 6 param_assign 2 parameter 2 port 2 @@ -152,7 +152,7 @@ design: (work@dut) |vpiElaborated:1 |vpiName:work@dut |uhdmallInterfaces: -\_interface: work@tnoc_flit_if (work@tnoc_flit_if), file:${SURELOG_DIR}/tests/InterfType/dut.sv, line:6:1, endln:10:13 +\_interface_inst: work@tnoc_flit_if (work@tnoc_flit_if), file:${SURELOG_DIR}/tests/InterfType/dut.sv, line:6:1, endln:10:13 |vpiParent: \_design: (work@dut) |vpiFullName:work@tnoc_flit_if @@ -160,13 +160,13 @@ design: (work@dut) |vpiNet: \_logic_net: (work@tnoc_flit_if.types), line:7:15, endln:7:20 |vpiParent: - \_interface: work@tnoc_flit_if (work@tnoc_flit_if), file:${SURELOG_DIR}/tests/InterfType/dut.sv, line:6:1, endln:10:13 + \_interface_inst: work@tnoc_flit_if (work@tnoc_flit_if), file:${SURELOG_DIR}/tests/InterfType/dut.sv, line:6:1, endln:10:13 |vpiName:types |vpiFullName:work@tnoc_flit_if.types |vpiPort: \_port: (types), line:7:15, endln:7:20 |vpiParent: - \_interface: work@tnoc_flit_if (work@tnoc_flit_if), file:${SURELOG_DIR}/tests/InterfType/dut.sv, line:6:1, endln:10:13 + \_interface_inst: work@tnoc_flit_if (work@tnoc_flit_if), file:${SURELOG_DIR}/tests/InterfType/dut.sv, line:6:1, endln:10:13 |vpiName:types |vpiDirection:3 |vpiLowConn: @@ -174,14 +174,14 @@ design: (work@dut) |vpiActual: \_logic_net: (work@tnoc_flit_if.types), line:7:15, endln:7:20 |uhdmallInterfaces: -\_interface: work@tnoc_types (work@tnoc_types), file:${SURELOG_DIR}/tests/InterfType/dut.sv, line:1:1, endln:4:13 +\_interface_inst: work@tnoc_types (work@tnoc_types), file:${SURELOG_DIR}/tests/InterfType/dut.sv, line:1:1, endln:4:13 |vpiParent: \_design: (work@dut) |vpiFullName:work@tnoc_types |vpiParameter: \_parameter: (work@tnoc_types.PACKET_CONFIG), line:2:18, endln:2:31 |vpiParent: - \_interface: work@tnoc_types (work@tnoc_types), file:${SURELOG_DIR}/tests/InterfType/dut.sv, line:1:1, endln:4:13 + \_interface_inst: work@tnoc_types (work@tnoc_types), file:${SURELOG_DIR}/tests/InterfType/dut.sv, line:1:1, endln:4:13 |UINT:1 |vpiTypespec: \_int_typespec: , line:2:13, endln:2:16 @@ -194,7 +194,7 @@ design: (work@dut) |vpiParamAssign: \_param_assign: , line:2:18, endln:2:35 |vpiParent: - \_interface: work@tnoc_types (work@tnoc_types), file:${SURELOG_DIR}/tests/InterfType/dut.sv, line:1:1, endln:4:13 + \_interface_inst: work@tnoc_types (work@tnoc_types), file:${SURELOG_DIR}/tests/InterfType/dut.sv, line:1:1, endln:4:13 |vpiRhs: \_constant: , line:2:34, endln:2:35 |vpiDecompile:1 @@ -207,27 +207,27 @@ design: (work@dut) \_parameter: (work@tnoc_types.PACKET_CONFIG), line:2:18, endln:2:31 |vpiDefName:work@tnoc_types |uhdmallModules: -\_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/InterfType/dut.sv, line:13:1, endln:18:10 +\_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/InterfType/dut.sv, line:13:1, endln:18:10 |vpiParent: \_design: (work@dut) |vpiFullName:work@dut |vpiDefName:work@dut |uhdmtopModules: -\_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/InterfType/dut.sv, line:13:1, endln:18:10 +\_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/InterfType/dut.sv, line:13:1, endln:18:10 |vpiName:work@dut |vpiDefName:work@dut |vpiTop:1 |vpiTopModule:1 - |vpiInterface: - \_interface: work@tnoc_types (work@dut.i_types), file:${SURELOG_DIR}/tests/InterfType/dut.sv, line:15:1, endln:15:26 + |vpiInterfaceInst: + \_interface_inst: work@tnoc_types (work@dut.i_types), file:${SURELOG_DIR}/tests/InterfType/dut.sv, line:15:1, endln:15:26 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/InterfType/dut.sv, line:13:1, endln:18:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/InterfType/dut.sv, line:13:1, endln:18:10 |vpiName:i_types |vpiFullName:work@dut.i_types |vpiParameter: \_parameter: (work@dut.i_types.PACKET_CONFIG), line:2:18, endln:2:31 |vpiParent: - \_interface: work@tnoc_types (work@dut.i_types), file:${SURELOG_DIR}/tests/InterfType/dut.sv, line:15:1, endln:15:26 + \_interface_inst: work@tnoc_types (work@dut.i_types), file:${SURELOG_DIR}/tests/InterfType/dut.sv, line:15:1, endln:15:26 |UINT:1 |vpiTypespec: \_int_typespec: , line:2:13, endln:2:16 @@ -240,7 +240,7 @@ design: (work@dut) |vpiParamAssign: \_param_assign: , line:2:18, endln:2:35 |vpiParent: - \_interface: work@tnoc_types (work@dut.i_types), file:${SURELOG_DIR}/tests/InterfType/dut.sv, line:15:1, endln:15:26 + \_interface_inst: work@tnoc_types (work@dut.i_types), file:${SURELOG_DIR}/tests/InterfType/dut.sv, line:15:1, endln:15:26 |vpiOverriden:1 |vpiRhs: \_constant: , line:2:34, endln:2:35 @@ -256,29 +256,29 @@ design: (work@dut) |vpiDefFile:${SURELOG_DIR}/tests/InterfType/dut.sv |vpiDefLineNo:1 |vpiInstance: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/InterfType/dut.sv, line:13:1, endln:18:10 - |vpiInterface: - \_interface: work@tnoc_flit_if (work@dut.tnoc), file:${SURELOG_DIR}/tests/InterfType/dut.sv, line:16:1, endln:16:29 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/InterfType/dut.sv, line:13:1, endln:18:10 + |vpiInterfaceInst: + \_interface_inst: work@tnoc_flit_if (work@dut.tnoc), file:${SURELOG_DIR}/tests/InterfType/dut.sv, line:16:1, endln:16:29 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/InterfType/dut.sv, line:13:1, endln:18:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/InterfType/dut.sv, line:13:1, endln:18:10 |vpiName:tnoc |vpiFullName:work@dut.tnoc |vpiDefName:work@tnoc_flit_if |vpiDefFile:${SURELOG_DIR}/tests/InterfType/dut.sv |vpiDefLineNo:6 |vpiInstance: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/InterfType/dut.sv, line:13:1, endln:18:10 - |vpiInterface: - \_interface: work@tnoc_types (work@dut.tnoc.types), file:${SURELOG_DIR}/tests/InterfType/dut.sv, line:13:0 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/InterfType/dut.sv, line:13:1, endln:18:10 + |vpiInterfaceInst: + \_interface_inst: work@tnoc_types (work@dut.tnoc.types), file:${SURELOG_DIR}/tests/InterfType/dut.sv, line:13:0 |vpiParent: - \_interface: work@tnoc_flit_if (work@dut.tnoc), file:${SURELOG_DIR}/tests/InterfType/dut.sv, line:16:1, endln:16:29 + \_interface_inst: work@tnoc_flit_if (work@dut.tnoc), file:${SURELOG_DIR}/tests/InterfType/dut.sv, line:16:1, endln:16:29 |vpiName:types |vpiFullName:work@dut.tnoc.types |vpiDefName:work@tnoc_types |vpiPort: \_port: (types), line:7:15, endln:7:20 |vpiParent: - \_interface: work@tnoc_flit_if (work@dut.tnoc), file:${SURELOG_DIR}/tests/InterfType/dut.sv, line:16:1, endln:16:29 + \_interface_inst: work@tnoc_flit_if (work@dut.tnoc), file:${SURELOG_DIR}/tests/InterfType/dut.sv, line:16:1, endln:16:29 |vpiName:types |vpiDirection:3 |vpiHighConn: @@ -286,12 +286,12 @@ design: (work@dut) |vpiName:i_types |vpiFullName:work@dut.i_types |vpiActual: - \_interface: work@tnoc_types (work@dut.i_types), file:${SURELOG_DIR}/tests/InterfType/dut.sv, line:15:0 + \_interface_inst: work@tnoc_types (work@dut.i_types), file:${SURELOG_DIR}/tests/InterfType/dut.sv, line:15:0 |vpiLowConn: \_ref_obj: (work@dut.types), line:16:20, endln:16:27 |vpiFullName:work@dut.types |vpiActual: - \_interface: work@tnoc_types (work@dut.tnoc.types), file:${SURELOG_DIR}/tests/InterfType/dut.sv, line:13:0 + \_interface_inst: work@tnoc_types (work@dut.tnoc.types), file:${SURELOG_DIR}/tests/InterfType/dut.sv, line:13:0 |vpiTypedef: \_interface_typespec: (tnoc_types), line:7:3, endln:7:13 |vpiName:tnoc_types diff --git a/tests/InterfTypeBad/InterfTypeBad.log b/tests/InterfTypeBad/InterfTypeBad.log index 8a3540613f..d5f2bcfc78 100644 --- a/tests/InterfTypeBad/InterfTypeBad.log +++ b/tests/InterfTypeBad/InterfTypeBad.log @@ -115,10 +115,10 @@ n<> u<78> t c<1> l<1:1> el<20:1> constant 1 design 1 int_typespec 1 -interface 5 +interface_inst 5 interface_typespec 3 logic_net 3 -module 4 +module_inst 4 param_assign 1 parameter 1 port 2 @@ -130,10 +130,10 @@ ref_obj 3 constant 1 design 1 int_typespec 1 -interface 5 +interface_inst 5 interface_typespec 3 logic_net 3 -module 4 +module_inst 4 param_assign 1 parameter 1 port 2 @@ -152,7 +152,7 @@ design: (work@dut) |vpiElaborated:1 |vpiName:work@dut |uhdmallInterfaces: -\_interface: work@tnoc_flit_if (work@tnoc_flit_if), file:${SURELOG_DIR}/tests/InterfTypeBad/dut.sv, line:6:1, endln:10:13 +\_interface_inst: work@tnoc_flit_if (work@tnoc_flit_if), file:${SURELOG_DIR}/tests/InterfTypeBad/dut.sv, line:6:1, endln:10:13 |vpiParent: \_design: (work@dut) |vpiFullName:work@tnoc_flit_if @@ -160,13 +160,13 @@ design: (work@dut) |vpiNet: \_logic_net: (work@tnoc_flit_if.types), line:7:15, endln:7:20 |vpiParent: - \_interface: work@tnoc_flit_if (work@tnoc_flit_if), file:${SURELOG_DIR}/tests/InterfTypeBad/dut.sv, line:6:1, endln:10:13 + \_interface_inst: work@tnoc_flit_if (work@tnoc_flit_if), file:${SURELOG_DIR}/tests/InterfTypeBad/dut.sv, line:6:1, endln:10:13 |vpiName:types |vpiFullName:work@tnoc_flit_if.types |vpiPort: \_port: (types), line:7:15, endln:7:20 |vpiParent: - \_interface: work@tnoc_flit_if (work@tnoc_flit_if), file:${SURELOG_DIR}/tests/InterfTypeBad/dut.sv, line:6:1, endln:10:13 + \_interface_inst: work@tnoc_flit_if (work@tnoc_flit_if), file:${SURELOG_DIR}/tests/InterfTypeBad/dut.sv, line:6:1, endln:10:13 |vpiName:types |vpiDirection:3 |vpiLowConn: @@ -174,14 +174,14 @@ design: (work@dut) |vpiActual: \_logic_net: (work@tnoc_flit_if.types), line:7:15, endln:7:20 |uhdmallInterfaces: -\_interface: work@tnoc_types (work@tnoc_types), file:${SURELOG_DIR}/tests/InterfTypeBad/dut.sv, line:1:1, endln:4:13 +\_interface_inst: work@tnoc_types (work@tnoc_types), file:${SURELOG_DIR}/tests/InterfTypeBad/dut.sv, line:1:1, endln:4:13 |vpiParent: \_design: (work@dut) |vpiFullName:work@tnoc_types |vpiParameter: \_parameter: (work@tnoc_types.PACKET_CONFIG), line:2:18, endln:2:31 |vpiParent: - \_interface: work@tnoc_types (work@tnoc_types), file:${SURELOG_DIR}/tests/InterfTypeBad/dut.sv, line:1:1, endln:4:13 + \_interface_inst: work@tnoc_types (work@tnoc_types), file:${SURELOG_DIR}/tests/InterfTypeBad/dut.sv, line:1:1, endln:4:13 |UINT:1 |vpiTypespec: \_int_typespec: , line:2:13, endln:2:16 @@ -194,7 +194,7 @@ design: (work@dut) |vpiParamAssign: \_param_assign: , line:2:18, endln:2:35 |vpiParent: - \_interface: work@tnoc_types (work@tnoc_types), file:${SURELOG_DIR}/tests/InterfTypeBad/dut.sv, line:1:1, endln:4:13 + \_interface_inst: work@tnoc_types (work@tnoc_types), file:${SURELOG_DIR}/tests/InterfTypeBad/dut.sv, line:1:1, endln:4:13 |vpiRhs: \_constant: , line:2:34, endln:2:35 |vpiDecompile:1 @@ -207,7 +207,7 @@ design: (work@dut) \_parameter: (work@tnoc_types.PACKET_CONFIG), line:2:18, endln:2:31 |vpiDefName:work@tnoc_types |uhdmallModules: -\_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/InterfTypeBad/dut.sv, line:13:1, endln:18:10 +\_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/InterfTypeBad/dut.sv, line:13:1, endln:18:10 |vpiParent: \_design: (work@dut) |vpiFullName:work@dut @@ -215,44 +215,44 @@ design: (work@dut) |vpiNet: \_logic_net: (work@dut.i_types), line:15:16, endln:15:23 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/InterfTypeBad/dut.sv, line:13:1, endln:18:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/InterfTypeBad/dut.sv, line:13:1, endln:18:10 |vpiName:i_types |vpiFullName:work@dut.i_types |uhdmtopModules: -\_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/InterfTypeBad/dut.sv, line:13:1, endln:18:10 +\_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/InterfTypeBad/dut.sv, line:13:1, endln:18:10 |vpiName:work@dut |vpiDefName:work@dut |vpiTop:1 |vpiNet: \_logic_net: (work@dut.i_types), line:16:20, endln:16:27 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/InterfTypeBad/dut.sv, line:13:1, endln:18:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/InterfTypeBad/dut.sv, line:13:1, endln:18:10 |vpiName:i_types |vpiFullName:work@dut.i_types |vpiNetType:1 |vpiTopModule:1 - |vpiInterface: - \_interface: work@tnoc_flit_if (work@dut.tnoc), file:${SURELOG_DIR}/tests/InterfTypeBad/dut.sv, line:16:1, endln:16:29 + |vpiInterfaceInst: + \_interface_inst: work@tnoc_flit_if (work@dut.tnoc), file:${SURELOG_DIR}/tests/InterfTypeBad/dut.sv, line:16:1, endln:16:29 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/InterfTypeBad/dut.sv, line:13:1, endln:18:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/InterfTypeBad/dut.sv, line:13:1, endln:18:10 |vpiName:tnoc |vpiFullName:work@dut.tnoc |vpiDefName:work@tnoc_flit_if |vpiDefFile:${SURELOG_DIR}/tests/InterfTypeBad/dut.sv |vpiDefLineNo:6 |vpiInstance: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/InterfTypeBad/dut.sv, line:13:1, endln:18:10 - |vpiInterface: - \_interface: work@tnoc_types (work@dut.tnoc.types), file:${SURELOG_DIR}/tests/InterfTypeBad/dut.sv, line:13:0 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/InterfTypeBad/dut.sv, line:13:1, endln:18:10 + |vpiInterfaceInst: + \_interface_inst: work@tnoc_types (work@dut.tnoc.types), file:${SURELOG_DIR}/tests/InterfTypeBad/dut.sv, line:13:0 |vpiParent: - \_interface: work@tnoc_flit_if (work@dut.tnoc), file:${SURELOG_DIR}/tests/InterfTypeBad/dut.sv, line:16:1, endln:16:29 + \_interface_inst: work@tnoc_flit_if (work@dut.tnoc), file:${SURELOG_DIR}/tests/InterfTypeBad/dut.sv, line:16:1, endln:16:29 |vpiName:types |vpiFullName:work@dut.tnoc.types |vpiDefName:work@tnoc_types |vpiPort: \_port: (types), line:7:15, endln:7:20 |vpiParent: - \_interface: work@tnoc_flit_if (work@dut.tnoc), file:${SURELOG_DIR}/tests/InterfTypeBad/dut.sv, line:16:1, endln:16:29 + \_interface_inst: work@tnoc_flit_if (work@dut.tnoc), file:${SURELOG_DIR}/tests/InterfTypeBad/dut.sv, line:16:1, endln:16:29 |vpiName:types |vpiDirection:3 |vpiHighConn: @@ -265,7 +265,7 @@ design: (work@dut) \_ref_obj: (work@dut.types), line:16:20, endln:16:27 |vpiFullName:work@dut.types |vpiActual: - \_interface: work@tnoc_types (work@dut.tnoc.types), file:${SURELOG_DIR}/tests/InterfTypeBad/dut.sv, line:13:0 + \_interface_inst: work@tnoc_types (work@dut.tnoc.types), file:${SURELOG_DIR}/tests/InterfTypeBad/dut.sv, line:13:0 |vpiTypedef: \_interface_typespec: (tnoc_types), line:7:3, endln:7:13 |vpiName:tnoc_types diff --git a/tests/InterfaceElab/InterfaceElab.log b/tests/InterfaceElab/InterfaceElab.log index 0a1f79330a..7fcdc3f2fc 100644 --- a/tests/InterfaceElab/InterfaceElab.log +++ b/tests/InterfaceElab/InterfaceElab.log @@ -188,14 +188,14 @@ n<> u<149> t c<1> l<2:1> el<37:1> constant 19 design 1 int_typespec 2 -interface 4 +interface_inst 4 interface_typespec 6 io_decl 4 logic_net 6 logic_typespec 6 logic_var 2 modport 4 -module 9 +module_inst 9 operation 5 param_assign 2 parameter 2 @@ -209,14 +209,14 @@ ref_obj 7 constant 19 design 1 int_typespec 2 -interface 4 +interface_inst 4 interface_typespec 6 io_decl 4 logic_net 6 logic_typespec 6 logic_var 2 modport 4 -module 9 +module_inst 9 operation 5 param_assign 2 parameter 2 @@ -237,14 +237,14 @@ design: (work@testharness) |vpiElaborated:1 |vpiName:work@testharness |uhdmallInterfaces: -\_interface: work@REG_BUS (work@REG_BUS), file:${SURELOG_DIR}/tests/InterfaceElab/dut.sv, line:2:1, endln:13:13 +\_interface_inst: work@REG_BUS (work@REG_BUS), file:${SURELOG_DIR}/tests/InterfaceElab/dut.sv, line:2:1, endln:13:13 |vpiParent: \_design: (work@testharness) |vpiFullName:work@REG_BUS |vpiParameter: \_parameter: (work@REG_BUS.ADDR_WIDTH), line:4:17, endln:4:27 |vpiParent: - \_interface: work@REG_BUS (work@REG_BUS), file:${SURELOG_DIR}/tests/InterfaceElab/dut.sv, line:2:1, endln:13:13 + \_interface_inst: work@REG_BUS (work@REG_BUS), file:${SURELOG_DIR}/tests/InterfaceElab/dut.sv, line:2:1, endln:13:13 |vpiTypespec: \_int_typespec: , line:4:13, endln:4:16 |vpiParent: @@ -256,7 +256,7 @@ design: (work@testharness) |vpiParamAssign: \_param_assign: , line:4:17, endln:4:32 |vpiParent: - \_interface: work@REG_BUS (work@REG_BUS), file:${SURELOG_DIR}/tests/InterfaceElab/dut.sv, line:2:1, endln:13:13 + \_interface_inst: work@REG_BUS (work@REG_BUS), file:${SURELOG_DIR}/tests/InterfaceElab/dut.sv, line:2:1, endln:13:13 |vpiRhs: \_operation: , line:4:30, endln:4:32 |vpiOpType:1 @@ -272,21 +272,21 @@ design: (work@testharness) |vpiNet: \_logic_net: (work@REG_BUS.clk_i), line:6:15, endln:6:20 |vpiParent: - \_interface: work@REG_BUS (work@REG_BUS), file:${SURELOG_DIR}/tests/InterfaceElab/dut.sv, line:2:1, endln:13:13 + \_interface_inst: work@REG_BUS (work@REG_BUS), file:${SURELOG_DIR}/tests/InterfaceElab/dut.sv, line:2:1, endln:13:13 |vpiName:clk_i |vpiFullName:work@REG_BUS.clk_i |vpiNetType:36 |vpiNet: \_logic_net: (work@REG_BUS.addr), line:9:28, endln:9:32 |vpiParent: - \_interface: work@REG_BUS (work@REG_BUS), file:${SURELOG_DIR}/tests/InterfaceElab/dut.sv, line:2:1, endln:13:13 + \_interface_inst: work@REG_BUS (work@REG_BUS), file:${SURELOG_DIR}/tests/InterfaceElab/dut.sv, line:2:1, endln:13:13 |vpiName:addr |vpiFullName:work@REG_BUS.addr |vpiNetType:36 |vpiModport: \_modport: (out), line:11:11, endln:11:14 |vpiParent: - \_interface: work@REG_BUS (work@REG_BUS), file:${SURELOG_DIR}/tests/InterfaceElab/dut.sv, line:2:1, endln:13:13 + \_interface_inst: work@REG_BUS (work@REG_BUS), file:${SURELOG_DIR}/tests/InterfaceElab/dut.sv, line:2:1, endln:13:13 |vpiName:out |vpiIODecl: \_io_decl: (addr), line:11:23, endln:11:27 @@ -295,7 +295,7 @@ design: (work@testharness) |vpiPort: \_port: (clk_i), line:6:15, endln:6:20 |vpiParent: - \_interface: work@REG_BUS (work@REG_BUS), file:${SURELOG_DIR}/tests/InterfaceElab/dut.sv, line:2:1, endln:13:13 + \_interface_inst: work@REG_BUS (work@REG_BUS), file:${SURELOG_DIR}/tests/InterfaceElab/dut.sv, line:2:1, endln:13:13 |vpiName:clk_i |vpiDirection:1 |vpiLowConn: @@ -303,7 +303,7 @@ design: (work@testharness) |vpiActual: \_logic_net: (work@REG_BUS.clk_i), line:6:15, endln:6:20 |uhdmallModules: -\_module: work@apb_to_reg (work@apb_to_reg), file:${SURELOG_DIR}/tests/InterfaceElab/dut.sv, line:15:1, endln:19:10 +\_module_inst: work@apb_to_reg (work@apb_to_reg), file:${SURELOG_DIR}/tests/InterfaceElab/dut.sv, line:15:1, endln:19:10 |vpiParent: \_design: (work@testharness) |vpiFullName:work@apb_to_reg @@ -311,13 +311,13 @@ design: (work@testharness) |vpiNet: \_logic_net: (work@apb_to_reg.reg_o), line:16:16, endln:16:21 |vpiParent: - \_module: work@apb_to_reg (work@apb_to_reg), file:${SURELOG_DIR}/tests/InterfaceElab/dut.sv, line:15:1, endln:19:10 + \_module_inst: work@apb_to_reg (work@apb_to_reg), file:${SURELOG_DIR}/tests/InterfaceElab/dut.sv, line:15:1, endln:19:10 |vpiName:reg_o |vpiFullName:work@apb_to_reg.reg_o |vpiPort: \_port: (reg_o), line:16:16, endln:16:21 |vpiParent: - \_module: work@apb_to_reg (work@apb_to_reg), file:${SURELOG_DIR}/tests/InterfaceElab/dut.sv, line:15:1, endln:19:10 + \_module_inst: work@apb_to_reg (work@apb_to_reg), file:${SURELOG_DIR}/tests/InterfaceElab/dut.sv, line:15:1, endln:19:10 |vpiName:reg_o |vpiDirection:3 |vpiLowConn: @@ -331,27 +331,27 @@ design: (work@testharness) |vpiName:out |vpiIsModPort:1 |uhdmallModules: -\_module: work@peripherals (work@peripherals), file:${SURELOG_DIR}/tests/InterfaceElab/dut.sv, line:21:1, endln:29:10 +\_module_inst: work@peripherals (work@peripherals), file:${SURELOG_DIR}/tests/InterfaceElab/dut.sv, line:21:1, endln:29:10 |vpiParent: \_design: (work@testharness) |vpiFullName:work@peripherals |vpiDefName:work@peripherals |uhdmallModules: -\_module: work@testharness (work@testharness), file:${SURELOG_DIR}/tests/InterfaceElab/dut.sv, line:32:1, endln:36:10 +\_module_inst: work@testharness (work@testharness), file:${SURELOG_DIR}/tests/InterfaceElab/dut.sv, line:32:1, endln:36:10 |vpiParent: \_design: (work@testharness) |vpiFullName:work@testharness |vpiDefName:work@testharness |uhdmtopModules: -\_module: work@testharness (work@testharness), file:${SURELOG_DIR}/tests/InterfaceElab/dut.sv, line:32:1, endln:36:10 +\_module_inst: work@testharness (work@testharness), file:${SURELOG_DIR}/tests/InterfaceElab/dut.sv, line:32:1, endln:36:10 |vpiName:work@testharness |vpiDefName:work@testharness |vpiTop:1 |vpiTopModule:1 - |vpiModule: - \_module: work@peripherals (work@testharness.i_peripherals), file:${SURELOG_DIR}/tests/InterfaceElab/dut.sv, line:34:3, endln:34:33 + |vpiModuleInst: + \_module_inst: work@peripherals (work@testharness.i_peripherals), file:${SURELOG_DIR}/tests/InterfaceElab/dut.sv, line:34:3, endln:34:33 |vpiParent: - \_module: work@testharness (work@testharness), file:${SURELOG_DIR}/tests/InterfaceElab/dut.sv, line:32:1, endln:36:10 + \_module_inst: work@testharness (work@testharness), file:${SURELOG_DIR}/tests/InterfaceElab/dut.sv, line:32:1, endln:36:10 |vpiName:i_peripherals |vpiFullName:work@testharness.i_peripherals |vpiDefName:work@peripherals @@ -360,22 +360,22 @@ design: (work@testharness) |vpiNet: \_logic_net: (work@testharness.i_peripherals.clk_i), line:25:16, endln:25:21 |vpiParent: - \_module: work@peripherals (work@testharness.i_peripherals), file:${SURELOG_DIR}/tests/InterfaceElab/dut.sv, line:34:3, endln:34:33 + \_module_inst: work@peripherals (work@testharness.i_peripherals), file:${SURELOG_DIR}/tests/InterfaceElab/dut.sv, line:34:3, endln:34:33 |vpiName:clk_i |vpiFullName:work@testharness.i_peripherals.clk_i |vpiNetType:1 |vpiInstance: - \_module: work@testharness (work@testharness), file:${SURELOG_DIR}/tests/InterfaceElab/dut.sv, line:32:1, endln:36:10 - |vpiInterface: - \_interface: work@REG_BUS (work@testharness.i_peripherals.reg_bus), file:${SURELOG_DIR}/tests/InterfaceElab/dut.sv, line:23:4, endln:25:23 + \_module_inst: work@testharness (work@testharness), file:${SURELOG_DIR}/tests/InterfaceElab/dut.sv, line:32:1, endln:36:10 + |vpiInterfaceInst: + \_interface_inst: work@REG_BUS (work@testharness.i_peripherals.reg_bus), file:${SURELOG_DIR}/tests/InterfaceElab/dut.sv, line:23:4, endln:25:23 |vpiParent: - \_module: work@peripherals (work@testharness.i_peripherals), file:${SURELOG_DIR}/tests/InterfaceElab/dut.sv, line:34:3, endln:34:33 + \_module_inst: work@peripherals (work@testharness.i_peripherals), file:${SURELOG_DIR}/tests/InterfaceElab/dut.sv, line:34:3, endln:34:33 |vpiName:reg_bus |vpiFullName:work@testharness.i_peripherals.reg_bus |vpiVariables: \_logic_var: (work@testharness.i_peripherals.reg_bus.addr), line:9:28, endln:9:32 |vpiParent: - \_interface: work@REG_BUS (work@testharness.i_peripherals.reg_bus), file:${SURELOG_DIR}/tests/InterfaceElab/dut.sv, line:23:4, endln:25:23 + \_interface_inst: work@REG_BUS (work@testharness.i_peripherals.reg_bus), file:${SURELOG_DIR}/tests/InterfaceElab/dut.sv, line:23:4, endln:25:23 |vpiTypespec: \_logic_typespec: , line:9:3, endln:9:25 |vpiRange: @@ -420,7 +420,7 @@ design: (work@testharness) |vpiParameter: \_parameter: (work@testharness.i_peripherals.reg_bus.ADDR_WIDTH), line:4:17, endln:4:27 |vpiParent: - \_interface: work@REG_BUS (work@testharness.i_peripherals.reg_bus), file:${SURELOG_DIR}/tests/InterfaceElab/dut.sv, line:23:4, endln:25:23 + \_interface_inst: work@REG_BUS (work@testharness.i_peripherals.reg_bus), file:${SURELOG_DIR}/tests/InterfaceElab/dut.sv, line:23:4, endln:25:23 |vpiTypespec: \_int_typespec: , line:4:13, endln:4:16 |vpiParent: @@ -432,7 +432,7 @@ design: (work@testharness) |vpiParamAssign: \_param_assign: , line:4:17, endln:4:32 |vpiParent: - \_interface: work@REG_BUS (work@testharness.i_peripherals.reg_bus), file:${SURELOG_DIR}/tests/InterfaceElab/dut.sv, line:23:4, endln:25:23 + \_interface_inst: work@REG_BUS (work@testharness.i_peripherals.reg_bus), file:${SURELOG_DIR}/tests/InterfaceElab/dut.sv, line:23:4, endln:25:23 |vpiOverriden:1 |vpiRhs: \_constant: , line:4:30, endln:4:32 @@ -450,18 +450,18 @@ design: (work@testharness) |vpiNet: \_logic_net: (work@testharness.i_peripherals.reg_bus.clk_i), line:6:15, endln:6:20 |vpiParent: - \_interface: work@REG_BUS (work@testharness.i_peripherals.reg_bus), file:${SURELOG_DIR}/tests/InterfaceElab/dut.sv, line:23:4, endln:25:23 + \_interface_inst: work@REG_BUS (work@testharness.i_peripherals.reg_bus), file:${SURELOG_DIR}/tests/InterfaceElab/dut.sv, line:23:4, endln:25:23 |vpiTypespec: \_logic_typespec: , line:6:9, endln:6:14 |vpiName:clk_i |vpiFullName:work@testharness.i_peripherals.reg_bus.clk_i |vpiNetType:36 |vpiInstance: - \_module: work@peripherals (work@testharness.i_peripherals), file:${SURELOG_DIR}/tests/InterfaceElab/dut.sv, line:34:3, endln:34:33 + \_module_inst: work@peripherals (work@testharness.i_peripherals), file:${SURELOG_DIR}/tests/InterfaceElab/dut.sv, line:34:3, endln:34:33 |vpiModport: \_modport: (out), line:11:11, endln:11:14 |vpiParent: - \_interface: work@REG_BUS (work@testharness.i_peripherals.reg_bus), file:${SURELOG_DIR}/tests/InterfaceElab/dut.sv, line:23:4, endln:25:23 + \_interface_inst: work@REG_BUS (work@testharness.i_peripherals.reg_bus), file:${SURELOG_DIR}/tests/InterfaceElab/dut.sv, line:23:4, endln:25:23 |vpiName:out |vpiIODecl: \_io_decl: (addr), line:11:23, endln:11:27 @@ -469,12 +469,12 @@ design: (work@testharness) \_modport: (out), line:11:11, endln:11:14 |vpiDirection:2 |vpiName:addr - |vpiInterface: - \_interface: work@REG_BUS (work@testharness.i_peripherals.reg_bus), file:${SURELOG_DIR}/tests/InterfaceElab/dut.sv, line:23:4, endln:25:23 + |vpiInterfaceInst: + \_interface_inst: work@REG_BUS (work@testharness.i_peripherals.reg_bus), file:${SURELOG_DIR}/tests/InterfaceElab/dut.sv, line:23:4, endln:25:23 |vpiPort: \_port: (clk_i), line:6:15, endln:6:20 |vpiParent: - \_interface: work@REG_BUS (work@testharness.i_peripherals.reg_bus), file:${SURELOG_DIR}/tests/InterfaceElab/dut.sv, line:23:4, endln:25:23 + \_interface_inst: work@REG_BUS (work@testharness.i_peripherals.reg_bus), file:${SURELOG_DIR}/tests/InterfaceElab/dut.sv, line:23:4, endln:25:23 |vpiName:clk_i |vpiDirection:1 |vpiHighConn: @@ -491,21 +491,21 @@ design: (work@testharness) \_logic_net: (work@testharness.i_peripherals.reg_bus.clk_i), line:6:15, endln:6:20 |vpiTypedef: \_logic_typespec: , line:6:9, endln:6:14 - |vpiModule: - \_module: work@apb_to_reg (work@testharness.i_peripherals.i_apb_to_reg), file:${SURELOG_DIR}/tests/InterfaceElab/dut.sv, line:27:1, endln:27:44 + |vpiModuleInst: + \_module_inst: work@apb_to_reg (work@testharness.i_peripherals.i_apb_to_reg), file:${SURELOG_DIR}/tests/InterfaceElab/dut.sv, line:27:1, endln:27:44 |vpiParent: - \_module: work@peripherals (work@testharness.i_peripherals), file:${SURELOG_DIR}/tests/InterfaceElab/dut.sv, line:34:3, endln:34:33 + \_module_inst: work@peripherals (work@testharness.i_peripherals), file:${SURELOG_DIR}/tests/InterfaceElab/dut.sv, line:34:3, endln:34:33 |vpiName:i_apb_to_reg |vpiFullName:work@testharness.i_peripherals.i_apb_to_reg |vpiDefName:work@apb_to_reg |vpiDefFile:${SURELOG_DIR}/tests/InterfaceElab/dut.sv |vpiDefLineNo:15 |vpiInstance: - \_module: work@peripherals (work@testharness.i_peripherals), file:${SURELOG_DIR}/tests/InterfaceElab/dut.sv, line:34:3, endln:34:33 + \_module_inst: work@peripherals (work@testharness.i_peripherals), file:${SURELOG_DIR}/tests/InterfaceElab/dut.sv, line:34:3, endln:34:33 |vpiPort: \_port: (reg_o), line:16:16, endln:16:21 |vpiParent: - \_module: work@apb_to_reg (work@testharness.i_peripherals.i_apb_to_reg), file:${SURELOG_DIR}/tests/InterfaceElab/dut.sv, line:27:1, endln:27:44 + \_module_inst: work@apb_to_reg (work@testharness.i_peripherals.i_apb_to_reg), file:${SURELOG_DIR}/tests/InterfaceElab/dut.sv, line:27:1, endln:27:44 |vpiName:reg_o |vpiDirection:3 |vpiHighConn: @@ -515,7 +515,7 @@ design: (work@testharness) |vpiName:reg_bus |vpiFullName:work@testharness.i_peripherals.reg_bus |vpiActual: - \_interface: work@REG_BUS (work@testharness.i_peripherals.reg_bus), file:${SURELOG_DIR}/tests/InterfaceElab/dut.sv, line:23:4, endln:25:23 + \_interface_inst: work@REG_BUS (work@testharness.i_peripherals.reg_bus), file:${SURELOG_DIR}/tests/InterfaceElab/dut.sv, line:23:4, endln:25:23 |vpiLowConn: \_ref_obj: (work@testharness.i_peripherals.i_apb_to_reg.reg_o), line:27:27, endln:27:32 |vpiParent: @@ -530,18 +530,18 @@ design: (work@testharness) |vpiName:out |vpiIsModPort:1 |vpiInstance: - \_module: work@apb_to_reg (work@testharness.i_peripherals.i_apb_to_reg), file:${SURELOG_DIR}/tests/InterfaceElab/dut.sv, line:27:1, endln:27:44 - |vpiInterface: - \_interface: work@REG_BUS (work@testharness.i_peripherals.i_apb_to_reg.reg_o), file:${SURELOG_DIR}/tests/InterfaceElab/dut.sv, line:27:0 + \_module_inst: work@apb_to_reg (work@testharness.i_peripherals.i_apb_to_reg), file:${SURELOG_DIR}/tests/InterfaceElab/dut.sv, line:27:1, endln:27:44 + |vpiInterfaceInst: + \_interface_inst: work@REG_BUS (work@testharness.i_peripherals.i_apb_to_reg.reg_o), file:${SURELOG_DIR}/tests/InterfaceElab/dut.sv, line:27:0 |vpiParent: - \_module: work@apb_to_reg (work@testharness.i_peripherals.i_apb_to_reg), file:${SURELOG_DIR}/tests/InterfaceElab/dut.sv, line:27:1, endln:27:44 + \_module_inst: work@apb_to_reg (work@testharness.i_peripherals.i_apb_to_reg), file:${SURELOG_DIR}/tests/InterfaceElab/dut.sv, line:27:1, endln:27:44 |vpiName:reg_o |vpiFullName:work@testharness.i_peripherals.i_apb_to_reg.reg_o |vpiDefName:work@REG_BUS |vpiModport: \_modport: (out), line:11:11, endln:11:14 |vpiParent: - \_interface: work@REG_BUS (work@testharness.i_peripherals.i_apb_to_reg.reg_o), file:${SURELOG_DIR}/tests/InterfaceElab/dut.sv, line:27:0 + \_interface_inst: work@REG_BUS (work@testharness.i_peripherals.i_apb_to_reg.reg_o), file:${SURELOG_DIR}/tests/InterfaceElab/dut.sv, line:27:0 |vpiName:out |vpiIODecl: \_io_decl: (addr), line:11:23, endln:11:27 @@ -589,8 +589,8 @@ design: (work@testharness) |vpiSize:64 |UINT:0 |vpiConstType:9 - |vpiInterface: - \_interface: work@REG_BUS (work@testharness.i_peripherals.i_apb_to_reg.reg_o), file:${SURELOG_DIR}/tests/InterfaceElab/dut.sv, line:27:0 + |vpiInterfaceInst: + \_interface_inst: work@REG_BUS (work@testharness.i_peripherals.i_apb_to_reg.reg_o), file:${SURELOG_DIR}/tests/InterfaceElab/dut.sv, line:27:0 =================== [ FATAL] : 0 [ SYNTAX] : 0 diff --git a/tests/InterfaceModExp/InterfaceModExp.log b/tests/InterfaceModExp/InterfaceModExp.log index 094bcf8a3b..52856728bc 100644 --- a/tests/InterfaceModExp/InterfaceModExp.log +++ b/tests/InterfaceModExp/InterfaceModExp.log @@ -272,14 +272,14 @@ hier_path 3 initial 2 int_typespec 2 int_var 2 -interface 4 +interface_inst 4 interface_typespec 3 io_decl 24 logic_net 4 logic_typespec 6 logic_var 2 modport 8 -module 7 +module_inst 7 part_select 4 port 2 range 8 @@ -299,14 +299,14 @@ hier_path 6 initial 4 int_typespec 2 int_var 2 -interface 4 +interface_inst 4 interface_typespec 3 io_decl 24 logic_net 4 logic_typespec 6 logic_var 2 modport 8 -module 7 +module_inst 7 part_select 4 port 3 range 8 @@ -326,7 +326,7 @@ design: (work@top) |vpiElaborated:1 |vpiName:work@top |uhdmallInterfaces: -\_interface: work@I (work@I), file:${SURELOG_DIR}/tests/InterfaceModExp/dut.sv, line:1:1, endln:7:13 +\_interface_inst: work@I (work@I), file:${SURELOG_DIR}/tests/InterfaceModExp/dut.sv, line:1:1, endln:7:13 |vpiParent: \_design: (work@top) |vpiFullName:work@I @@ -334,26 +334,26 @@ design: (work@top) |vpiNet: \_logic_net: (work@I.r), line:2:13, endln:2:14 |vpiParent: - \_interface: work@I (work@I), file:${SURELOG_DIR}/tests/InterfaceModExp/dut.sv, line:1:1, endln:7:13 + \_interface_inst: work@I (work@I), file:${SURELOG_DIR}/tests/InterfaceModExp/dut.sv, line:1:1, endln:7:13 |vpiName:r |vpiFullName:work@I.r |vpiNetType:36 |vpiNet: \_logic_net: (work@I.x), line:3:11, endln:3:12 |vpiParent: - \_interface: work@I (work@I), file:${SURELOG_DIR}/tests/InterfaceModExp/dut.sv, line:1:1, endln:7:13 + \_interface_inst: work@I (work@I), file:${SURELOG_DIR}/tests/InterfaceModExp/dut.sv, line:1:1, endln:7:13 |vpiName:x |vpiFullName:work@I.x |vpiNet: \_logic_net: (work@I.R), line:4:5, endln:4:6 |vpiParent: - \_interface: work@I (work@I), file:${SURELOG_DIR}/tests/InterfaceModExp/dut.sv, line:1:1, endln:7:13 + \_interface_inst: work@I (work@I), file:${SURELOG_DIR}/tests/InterfaceModExp/dut.sv, line:1:1, endln:7:13 |vpiName:R |vpiFullName:work@I.R |vpiModport: \_modport: (A), line:5:9, endln:5:10 |vpiParent: - \_interface: work@I (work@I), file:${SURELOG_DIR}/tests/InterfaceModExp/dut.sv, line:1:1, endln:7:13 + \_interface_inst: work@I (work@I), file:${SURELOG_DIR}/tests/InterfaceModExp/dut.sv, line:1:1, endln:7:13 |vpiName:A |vpiIODecl: \_io_decl: (P), line:5:20, endln:5:21 @@ -394,7 +394,7 @@ design: (work@top) |vpiModport: \_modport: (B), line:6:9, endln:6:10 |vpiParent: - \_interface: work@I (work@I), file:${SURELOG_DIR}/tests/InterfaceModExp/dut.sv, line:1:1, endln:7:13 + \_interface_inst: work@I (work@I), file:${SURELOG_DIR}/tests/InterfaceModExp/dut.sv, line:1:1, endln:7:13 |vpiName:B |vpiIODecl: \_io_decl: (P), line:6:20, endln:6:21 @@ -434,7 +434,7 @@ design: (work@top) |vpiDirection:1 |vpiName:R |uhdmallModules: -\_module: work@sub (work@sub), file:${SURELOG_DIR}/tests/InterfaceModExp/dut.sv, line:9:1, endln:12:10 +\_module_inst: work@sub (work@sub), file:${SURELOG_DIR}/tests/InterfaceModExp/dut.sv, line:9:1, endln:12:10 |vpiParent: \_design: (work@top) |vpiFullName:work@sub @@ -442,26 +442,26 @@ design: (work@top) |vpiNet: \_logic_net: (work@sub.I), line:9:23, endln:9:24 |vpiParent: - \_module: work@sub (work@sub), file:${SURELOG_DIR}/tests/InterfaceModExp/dut.sv, line:9:1, endln:12:10 + \_module_inst: work@sub (work@sub), file:${SURELOG_DIR}/tests/InterfaceModExp/dut.sv, line:9:1, endln:12:10 |vpiName:I |vpiFullName:work@sub.I |vpiPort: \_port: (I), line:9:23, endln:9:24 |vpiParent: - \_module: work@sub (work@sub), file:${SURELOG_DIR}/tests/InterfaceModExp/dut.sv, line:9:1, endln:12:10 + \_module_inst: work@sub (work@sub), file:${SURELOG_DIR}/tests/InterfaceModExp/dut.sv, line:9:1, endln:12:10 |vpiName:I |vpiDirection:3 |vpiLowConn: \_ref_obj: |vpiActual: - \_interface: work@I (work@I), file:${SURELOG_DIR}/tests/InterfaceModExp/dut.sv, line:1:1, endln:7:13 + \_interface_inst: work@I (work@I), file:${SURELOG_DIR}/tests/InterfaceModExp/dut.sv, line:1:1, endln:7:13 |vpiTypedef: \_interface_typespec: (I), line:9:23, endln:9:24 |vpiName:I |vpiProcess: \_initial: , line:11:3, endln:11:25 |vpiParent: - \_module: work@sub (work@sub), file:${SURELOG_DIR}/tests/InterfaceModExp/dut.sv, line:9:1, endln:12:10 + \_module_inst: work@sub (work@sub), file:${SURELOG_DIR}/tests/InterfaceModExp/dut.sv, line:9:1, endln:12:10 |vpiStmt: \_assignment: , line:11:11, endln:11:24 |vpiParent: @@ -490,7 +490,7 @@ design: (work@top) \_ref_obj: (P) |vpiName:P |uhdmallModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/InterfaceModExp/dut.sv, line:14:1, endln:20:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/InterfaceModExp/dut.sv, line:14:1, endln:20:10 |vpiParent: \_design: (work@top) |vpiFullName:work@top @@ -498,7 +498,7 @@ design: (work@top) |vpiProcess: \_initial: , line:18:3, endln:18:40 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/InterfaceModExp/dut.sv, line:14:1, endln:20:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/InterfaceModExp/dut.sv, line:14:1, endln:20:10 |vpiStmt: \_delay_control: , line:18:11, endln:18:13 |vpiParent: @@ -531,21 +531,21 @@ design: (work@top) |vpiName:r |vpiName:$display |uhdmtopModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/InterfaceModExp/dut.sv, line:14:1, endln:20:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/InterfaceModExp/dut.sv, line:14:1, endln:20:10 |vpiName:work@top |vpiDefName:work@top |vpiTop:1 |vpiTopModule:1 - |vpiInterface: - \_interface: work@I (work@top.inst), file:${SURELOG_DIR}/tests/InterfaceModExp/dut.sv, line:15:3, endln:15:12 + |vpiInterfaceInst: + \_interface_inst: work@I (work@top.inst), file:${SURELOG_DIR}/tests/InterfaceModExp/dut.sv, line:15:3, endln:15:12 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/InterfaceModExp/dut.sv, line:14:1, endln:20:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/InterfaceModExp/dut.sv, line:14:1, endln:20:10 |vpiName:inst |vpiFullName:work@top.inst |vpiVariables: \_logic_var: (work@top.inst.r), line:2:13, endln:2:14 |vpiParent: - \_interface: work@I (work@top.inst), file:${SURELOG_DIR}/tests/InterfaceModExp/dut.sv, line:15:3, endln:15:12 + \_interface_inst: work@I (work@top.inst), file:${SURELOG_DIR}/tests/InterfaceModExp/dut.sv, line:15:3, endln:15:12 |vpiTypespec: \_logic_typespec: , line:2:1, endln:2:12 |vpiRange: @@ -590,7 +590,7 @@ design: (work@top) |vpiVariables: \_int_var: (work@top.inst.x), line:3:11, endln:3:14 |vpiParent: - \_interface: work@I (work@top.inst), file:${SURELOG_DIR}/tests/InterfaceModExp/dut.sv, line:15:3, endln:15:12 + \_interface_inst: work@I (work@top.inst), file:${SURELOG_DIR}/tests/InterfaceModExp/dut.sv, line:15:3, endln:15:12 |vpiTypespec: \_int_typespec: , line:3:7, endln:3:10 |vpiSigned:1 @@ -607,7 +607,7 @@ design: (work@top) |vpiVariables: \_bit_var: (work@top.inst.R), line:4:5, endln:4:6 |vpiParent: - \_interface: work@I (work@top.inst), file:${SURELOG_DIR}/tests/InterfaceModExp/dut.sv, line:15:3, endln:15:12 + \_interface_inst: work@I (work@top.inst), file:${SURELOG_DIR}/tests/InterfaceModExp/dut.sv, line:15:3, endln:15:12 |vpiTypespec: \_bit_typespec: , line:4:1, endln:4:4 |vpiSigned:1 @@ -618,11 +618,11 @@ design: (work@top) |vpiDefFile:${SURELOG_DIR}/tests/InterfaceModExp/dut.sv |vpiDefLineNo:1 |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/InterfaceModExp/dut.sv, line:14:1, endln:20:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/InterfaceModExp/dut.sv, line:14:1, endln:20:10 |vpiModport: \_modport: (A), line:5:9, endln:5:10 |vpiParent: - \_interface: work@I (work@top.inst), file:${SURELOG_DIR}/tests/InterfaceModExp/dut.sv, line:15:3, endln:15:12 + \_interface_inst: work@I (work@top.inst), file:${SURELOG_DIR}/tests/InterfaceModExp/dut.sv, line:15:3, endln:15:12 |vpiName:A |vpiIODecl: \_io_decl: (P), line:5:20, endln:5:21 @@ -663,12 +663,12 @@ design: (work@top) \_modport: (A), line:5:9, endln:5:10 |vpiDirection:1 |vpiName:R - |vpiInterface: - \_interface: work@I (work@top.inst), file:${SURELOG_DIR}/tests/InterfaceModExp/dut.sv, line:15:3, endln:15:12 + |vpiInterfaceInst: + \_interface_inst: work@I (work@top.inst), file:${SURELOG_DIR}/tests/InterfaceModExp/dut.sv, line:15:3, endln:15:12 |vpiModport: \_modport: (B), line:6:9, endln:6:10 |vpiParent: - \_interface: work@I (work@top.inst), file:${SURELOG_DIR}/tests/InterfaceModExp/dut.sv, line:15:3, endln:15:12 + \_interface_inst: work@I (work@top.inst), file:${SURELOG_DIR}/tests/InterfaceModExp/dut.sv, line:15:3, endln:15:12 |vpiName:B |vpiIODecl: \_io_decl: (P), line:6:20, endln:6:21 @@ -713,12 +713,12 @@ design: (work@top) \_modport: (B), line:6:9, endln:6:10 |vpiDirection:1 |vpiName:R - |vpiInterface: - \_interface: work@I (work@top.inst), file:${SURELOG_DIR}/tests/InterfaceModExp/dut.sv, line:15:3, endln:15:12 + |vpiInterfaceInst: + \_interface_inst: work@I (work@top.inst), file:${SURELOG_DIR}/tests/InterfaceModExp/dut.sv, line:15:3, endln:15:12 |vpiProcess: \_initial: , line:18:3, endln:18:40 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/InterfaceModExp/dut.sv, line:14:1, endln:20:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/InterfaceModExp/dut.sv, line:14:1, endln:20:10 |vpiStmt: \_delay_control: , line:18:11, endln:18:13 |vpiParent: @@ -741,7 +741,7 @@ design: (work@top) \_hier_path: (inst.r), line:18:32, endln:18:38 |vpiName:inst |vpiActual: - \_interface: work@I (work@top.inst), file:${SURELOG_DIR}/tests/InterfaceModExp/dut.sv, line:15:3, endln:15:12 + \_interface_inst: work@I (work@top.inst), file:${SURELOG_DIR}/tests/InterfaceModExp/dut.sv, line:15:3, endln:15:12 |vpiActual: \_ref_obj: (r), line:18:37, endln:18:38 |vpiParent: @@ -750,21 +750,21 @@ design: (work@top) |vpiActual: \_logic_var: (work@top.inst.r), line:2:13, endln:2:14 |vpiName:$display - |vpiModule: - \_module: work@sub (work@top.s), file:${SURELOG_DIR}/tests/InterfaceModExp/dut.sv, line:16:3, endln:16:18 + |vpiModuleInst: + \_module_inst: work@sub (work@top.s), file:${SURELOG_DIR}/tests/InterfaceModExp/dut.sv, line:16:3, endln:16:18 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/InterfaceModExp/dut.sv, line:14:1, endln:20:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/InterfaceModExp/dut.sv, line:14:1, endln:20:10 |vpiName:s |vpiFullName:work@top.s |vpiDefName:work@sub |vpiDefFile:${SURELOG_DIR}/tests/InterfaceModExp/dut.sv |vpiDefLineNo:9 |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/InterfaceModExp/dut.sv, line:14:1, endln:20:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/InterfaceModExp/dut.sv, line:14:1, endln:20:10 |vpiPort: \_port: (I), line:9:23, endln:9:24 |vpiParent: - \_module: work@sub (work@top.s), file:${SURELOG_DIR}/tests/InterfaceModExp/dut.sv, line:16:3, endln:16:18 + \_module_inst: work@sub (work@top.s), file:${SURELOG_DIR}/tests/InterfaceModExp/dut.sv, line:16:3, endln:16:18 |vpiName:I |vpiDirection:3 |vpiHighConn: @@ -778,7 +778,7 @@ design: (work@top) \_hier_path: (inst.A), line:16:10, endln:16:16 |vpiName:inst |vpiActual: - \_interface: work@I (work@top.inst), file:${SURELOG_DIR}/tests/InterfaceModExp/dut.sv, line:15:3, endln:15:12 + \_interface_inst: work@I (work@top.inst), file:${SURELOG_DIR}/tests/InterfaceModExp/dut.sv, line:15:3, endln:15:12 |vpiActual: \_ref_obj: (A), line:16:15, endln:16:16 |vpiParent: @@ -792,23 +792,23 @@ design: (work@top) \_port: (I), line:9:23, endln:9:24 |vpiFullName:work@top.s.I |vpiActual: - \_interface: work@I (work@top.s.I), file:${SURELOG_DIR}/tests/InterfaceModExp/dut.sv, line:16:0 + \_interface_inst: work@I (work@top.s.I), file:${SURELOG_DIR}/tests/InterfaceModExp/dut.sv, line:16:0 |vpiTypedef: \_interface_typespec: (I), line:9:23, endln:9:24 |vpiName:I |vpiInstance: - \_module: work@sub (work@top.s), file:${SURELOG_DIR}/tests/InterfaceModExp/dut.sv, line:16:3, endln:16:18 - |vpiInterface: - \_interface: work@I (work@top.s.I), file:${SURELOG_DIR}/tests/InterfaceModExp/dut.sv, line:16:0 + \_module_inst: work@sub (work@top.s), file:${SURELOG_DIR}/tests/InterfaceModExp/dut.sv, line:16:3, endln:16:18 + |vpiInterfaceInst: + \_interface_inst: work@I (work@top.s.I), file:${SURELOG_DIR}/tests/InterfaceModExp/dut.sv, line:16:0 |vpiParent: - \_module: work@sub (work@top.s), file:${SURELOG_DIR}/tests/InterfaceModExp/dut.sv, line:16:3, endln:16:18 + \_module_inst: work@sub (work@top.s), file:${SURELOG_DIR}/tests/InterfaceModExp/dut.sv, line:16:3, endln:16:18 |vpiName:I |vpiFullName:work@top.s.I |vpiDefName:work@I |vpiModport: \_modport: (A), line:5:9, endln:5:10 |vpiParent: - \_interface: work@I (work@top.s.I), file:${SURELOG_DIR}/tests/InterfaceModExp/dut.sv, line:16:0 + \_interface_inst: work@I (work@top.s.I), file:${SURELOG_DIR}/tests/InterfaceModExp/dut.sv, line:16:0 |vpiName:A |vpiIODecl: \_io_decl: (P), line:5:20, endln:5:21 @@ -829,12 +829,12 @@ design: (work@top) |vpiSigned:1 |vpiName:R |vpiVisibility:1 - |vpiInterface: - \_interface: work@I (work@top.s.I), file:${SURELOG_DIR}/tests/InterfaceModExp/dut.sv, line:16:0 + |vpiInterfaceInst: + \_interface_inst: work@I (work@top.s.I), file:${SURELOG_DIR}/tests/InterfaceModExp/dut.sv, line:16:0 |vpiModport: \_modport: (B), line:6:9, endln:6:10 |vpiParent: - \_interface: work@I (work@top.s.I), file:${SURELOG_DIR}/tests/InterfaceModExp/dut.sv, line:16:0 + \_interface_inst: work@I (work@top.s.I), file:${SURELOG_DIR}/tests/InterfaceModExp/dut.sv, line:16:0 |vpiName:B |vpiIODecl: \_io_decl: (P), line:6:20, endln:6:21 @@ -850,14 +850,14 @@ design: (work@top) |vpiName:R |vpiExpr: \_bit_var: (R), line:4:5, endln:4:6 - |vpiInterface: - \_interface: work@I (work@top.s.I), file:${SURELOG_DIR}/tests/InterfaceModExp/dut.sv, line:16:0 - |vpiInterface: - \_interface: work@I (work@top.s.I), file:${SURELOG_DIR}/tests/InterfaceModExp/dut.sv, line:16:0 + |vpiInterfaceInst: + \_interface_inst: work@I (work@top.s.I), file:${SURELOG_DIR}/tests/InterfaceModExp/dut.sv, line:16:0 + |vpiInterfaceInst: + \_interface_inst: work@I (work@top.s.I), file:${SURELOG_DIR}/tests/InterfaceModExp/dut.sv, line:16:0 |vpiProcess: \_initial: , line:11:3, endln:11:25 |vpiParent: - \_module: work@sub (work@top.s), file:${SURELOG_DIR}/tests/InterfaceModExp/dut.sv, line:16:3, endln:16:18 + \_module_inst: work@sub (work@top.s), file:${SURELOG_DIR}/tests/InterfaceModExp/dut.sv, line:16:3, endln:16:18 |vpiStmt: \_assignment: , line:11:11, endln:11:24 |vpiParent: @@ -877,7 +877,7 @@ design: (work@top) \_hier_path: (I.P), line:11:11, endln:11:14 |vpiName:I |vpiActual: - \_interface: work@I (work@top.s.I), file:${SURELOG_DIR}/tests/InterfaceModExp/dut.sv, line:16:0 + \_interface_inst: work@I (work@top.s.I), file:${SURELOG_DIR}/tests/InterfaceModExp/dut.sv, line:16:0 |vpiActual: \_ref_obj: (P) |vpiParent: diff --git a/tests/InterfaceModPort/InterfaceModPort.log b/tests/InterfaceModPort/InterfaceModPort.log index 1e53e79b5e..eb05a8d701 100644 --- a/tests/InterfaceModPort/InterfaceModPort.log +++ b/tests/InterfaceModPort/InterfaceModPort.log @@ -1205,14 +1205,14 @@ if_stmt 2 initial 1 int_typespec 11 int_var 4 -interface 7 +interface_inst 7 interface_typespec 14 io_decl 116 logic_net 26 logic_typespec 54 logic_var 47 modport 13 -module 12 +module_inst 12 operation 7 package 2 param_assign 2 @@ -1646,7 +1646,7 @@ design: (work@interface_modports) \_int_typespec: |vpiSigned:1 |uhdmallInterfaces: -\_interface: work@mem_if (work@mem_if), file:${SURELOG_DIR}/tests/InterfaceModPort/top.v, line:26:1, endln:57:13 +\_interface_inst: work@mem_if (work@mem_if), file:${SURELOG_DIR}/tests/InterfaceModPort/top.v, line:26:1, endln:57:13 |vpiParent: \_design: (work@interface_modports) |vpiFullName:work@mem_if @@ -1654,91 +1654,91 @@ design: (work@interface_modports) |vpiNet: \_logic_net: (work@mem_if.clk), line:26:30, endln:26:33 |vpiParent: - \_interface: work@mem_if (work@mem_if), file:${SURELOG_DIR}/tests/InterfaceModPort/top.v, line:26:1, endln:57:13 + \_interface_inst: work@mem_if (work@mem_if), file:${SURELOG_DIR}/tests/InterfaceModPort/top.v, line:26:1, endln:57:13 |vpiName:clk |vpiFullName:work@mem_if.clk |vpiNetType:1 |vpiNet: \_logic_net: (work@mem_if.reset), line:27:16, endln:27:21 |vpiParent: - \_interface: work@mem_if (work@mem_if), file:${SURELOG_DIR}/tests/InterfaceModPort/top.v, line:26:1, endln:57:13 + \_interface_inst: work@mem_if (work@mem_if), file:${SURELOG_DIR}/tests/InterfaceModPort/top.v, line:26:1, endln:57:13 |vpiName:reset |vpiFullName:work@mem_if.reset |vpiNetType:36 |vpiNet: \_logic_net: (work@mem_if.we_sys), line:28:16, endln:28:22 |vpiParent: - \_interface: work@mem_if (work@mem_if), file:${SURELOG_DIR}/tests/InterfaceModPort/top.v, line:26:1, endln:57:13 + \_interface_inst: work@mem_if (work@mem_if), file:${SURELOG_DIR}/tests/InterfaceModPort/top.v, line:26:1, endln:57:13 |vpiName:we_sys |vpiFullName:work@mem_if.we_sys |vpiNetType:36 |vpiNet: \_logic_net: (work@mem_if.cmd_valid_sys), line:29:16, endln:29:29 |vpiParent: - \_interface: work@mem_if (work@mem_if), file:${SURELOG_DIR}/tests/InterfaceModPort/top.v, line:26:1, endln:57:13 + \_interface_inst: work@mem_if (work@mem_if), file:${SURELOG_DIR}/tests/InterfaceModPort/top.v, line:26:1, endln:57:13 |vpiName:cmd_valid_sys |vpiFullName:work@mem_if.cmd_valid_sys |vpiNetType:36 |vpiNet: \_logic_net: (work@mem_if.ready_sys), line:30:16, endln:30:25 |vpiParent: - \_interface: work@mem_if (work@mem_if), file:${SURELOG_DIR}/tests/InterfaceModPort/top.v, line:26:1, endln:57:13 + \_interface_inst: work@mem_if (work@mem_if), file:${SURELOG_DIR}/tests/InterfaceModPort/top.v, line:26:1, endln:57:13 |vpiName:ready_sys |vpiFullName:work@mem_if.ready_sys |vpiNetType:36 |vpiNet: \_logic_net: (work@mem_if.data_sys), line:31:16, endln:31:24 |vpiParent: - \_interface: work@mem_if (work@mem_if), file:${SURELOG_DIR}/tests/InterfaceModPort/top.v, line:26:1, endln:57:13 + \_interface_inst: work@mem_if (work@mem_if), file:${SURELOG_DIR}/tests/InterfaceModPort/top.v, line:26:1, endln:57:13 |vpiName:data_sys |vpiFullName:work@mem_if.data_sys |vpiNetType:36 |vpiNet: \_logic_net: (work@mem_if.addr_sys), line:32:16, endln:32:24 |vpiParent: - \_interface: work@mem_if (work@mem_if), file:${SURELOG_DIR}/tests/InterfaceModPort/top.v, line:26:1, endln:57:13 + \_interface_inst: work@mem_if (work@mem_if), file:${SURELOG_DIR}/tests/InterfaceModPort/top.v, line:26:1, endln:57:13 |vpiName:addr_sys |vpiFullName:work@mem_if.addr_sys |vpiNetType:36 |vpiNet: \_logic_net: (work@mem_if.we_mem), line:33:16, endln:33:22 |vpiParent: - \_interface: work@mem_if (work@mem_if), file:${SURELOG_DIR}/tests/InterfaceModPort/top.v, line:26:1, endln:57:13 + \_interface_inst: work@mem_if (work@mem_if), file:${SURELOG_DIR}/tests/InterfaceModPort/top.v, line:26:1, endln:57:13 |vpiName:we_mem |vpiFullName:work@mem_if.we_mem |vpiNetType:36 |vpiNet: \_logic_net: (work@mem_if.ce_mem), line:34:16, endln:34:22 |vpiParent: - \_interface: work@mem_if (work@mem_if), file:${SURELOG_DIR}/tests/InterfaceModPort/top.v, line:26:1, endln:57:13 + \_interface_inst: work@mem_if (work@mem_if), file:${SURELOG_DIR}/tests/InterfaceModPort/top.v, line:26:1, endln:57:13 |vpiName:ce_mem |vpiFullName:work@mem_if.ce_mem |vpiNetType:36 |vpiNet: \_logic_net: (work@mem_if.datao_mem), line:35:16, endln:35:25 |vpiParent: - \_interface: work@mem_if (work@mem_if), file:${SURELOG_DIR}/tests/InterfaceModPort/top.v, line:26:1, endln:57:13 + \_interface_inst: work@mem_if (work@mem_if), file:${SURELOG_DIR}/tests/InterfaceModPort/top.v, line:26:1, endln:57:13 |vpiName:datao_mem |vpiFullName:work@mem_if.datao_mem |vpiNetType:36 |vpiNet: \_logic_net: (work@mem_if.datai_mem), line:36:16, endln:36:25 |vpiParent: - \_interface: work@mem_if (work@mem_if), file:${SURELOG_DIR}/tests/InterfaceModPort/top.v, line:26:1, endln:57:13 + \_interface_inst: work@mem_if (work@mem_if), file:${SURELOG_DIR}/tests/InterfaceModPort/top.v, line:26:1, endln:57:13 |vpiName:datai_mem |vpiFullName:work@mem_if.datai_mem |vpiNetType:36 |vpiNet: \_logic_net: (work@mem_if.addr_mem), line:37:16, endln:37:24 |vpiParent: - \_interface: work@mem_if (work@mem_if), file:${SURELOG_DIR}/tests/InterfaceModPort/top.v, line:26:1, endln:57:13 + \_interface_inst: work@mem_if (work@mem_if), file:${SURELOG_DIR}/tests/InterfaceModPort/top.v, line:26:1, endln:57:13 |vpiName:addr_mem |vpiFullName:work@mem_if.addr_mem |vpiNetType:36 |vpiModport: \_modport: (memory), line:48:12, endln:48:18 |vpiParent: - \_interface: work@mem_if (work@mem_if), file:${SURELOG_DIR}/tests/InterfaceModPort/top.v, line:26:1, endln:57:13 + \_interface_inst: work@mem_if (work@mem_if), file:${SURELOG_DIR}/tests/InterfaceModPort/top.v, line:26:1, endln:57:13 |vpiName:memory |vpiIODecl: \_io_decl: (clk), line:48:26, endln:48:29 @@ -1771,7 +1771,7 @@ design: (work@interface_modports) |vpiModport: \_modport: (system), line:41:12, endln:41:18 |vpiParent: - \_interface: work@mem_if (work@mem_if), file:${SURELOG_DIR}/tests/InterfaceModPort/top.v, line:26:1, endln:57:13 + \_interface_inst: work@mem_if (work@mem_if), file:${SURELOG_DIR}/tests/InterfaceModPort/top.v, line:26:1, endln:57:13 |vpiName:system |vpiIODecl: \_io_decl: (clk), line:41:26, endln:41:29 @@ -1824,7 +1824,7 @@ design: (work@interface_modports) |vpiModport: \_modport: (tb), line:53:12, endln:53:14 |vpiParent: - \_interface: work@mem_if (work@mem_if), file:${SURELOG_DIR}/tests/InterfaceModPort/top.v, line:26:1, endln:57:13 + \_interface_inst: work@mem_if (work@mem_if), file:${SURELOG_DIR}/tests/InterfaceModPort/top.v, line:26:1, endln:57:13 |vpiName:tb |vpiIODecl: \_io_decl: (clk), line:53:22, endln:53:25 @@ -1857,7 +1857,7 @@ design: (work@interface_modports) |vpiPort: \_port: (clk), line:26:30, endln:26:33 |vpiParent: - \_interface: work@mem_if (work@mem_if), file:${SURELOG_DIR}/tests/InterfaceModPort/top.v, line:26:1, endln:57:13 + \_interface_inst: work@mem_if (work@mem_if), file:${SURELOG_DIR}/tests/InterfaceModPort/top.v, line:26:1, endln:57:13 |vpiName:clk |vpiDirection:1 |vpiLowConn: @@ -1865,14 +1865,14 @@ design: (work@interface_modports) |vpiActual: \_logic_net: (work@mem_if.clk), line:26:30, endln:26:33 |uhdmallInterfaces: -\_interface: work@mem_interface (work@mem_interface), file:${SURELOG_DIR}/tests/InterfaceModPort/top.v, line:1:1, endln:21:28 +\_interface_inst: work@mem_interface (work@mem_interface), file:${SURELOG_DIR}/tests/InterfaceModPort/top.v, line:1:1, endln:21:28 |vpiParent: \_design: (work@interface_modports) |vpiFullName:work@mem_interface |vpiParameter: \_parameter: (work@mem_interface.setup_time), line:3:14, endln:3:24 |vpiParent: - \_interface: work@mem_interface (work@mem_interface), file:${SURELOG_DIR}/tests/InterfaceModPort/top.v, line:1:1, endln:21:28 + \_interface_inst: work@mem_interface (work@mem_interface), file:${SURELOG_DIR}/tests/InterfaceModPort/top.v, line:1:1, endln:21:28 |UINT:5000000 |vpiTypespec: \_int_typespec: @@ -1881,7 +1881,7 @@ design: (work@interface_modports) |vpiParameter: \_parameter: (work@mem_interface.hold_time), line:4:14, endln:4:23 |vpiParent: - \_interface: work@mem_interface (work@mem_interface), file:${SURELOG_DIR}/tests/InterfaceModPort/top.v, line:1:1, endln:21:28 + \_interface_inst: work@mem_interface (work@mem_interface), file:${SURELOG_DIR}/tests/InterfaceModPort/top.v, line:1:1, endln:21:28 |UINT:3000000 |vpiTypespec: \_int_typespec: @@ -1890,7 +1890,7 @@ design: (work@interface_modports) |vpiParamAssign: \_param_assign: , line:3:14, endln:3:30 |vpiParent: - \_interface: work@mem_interface (work@mem_interface), file:${SURELOG_DIR}/tests/InterfaceModPort/top.v, line:1:1, endln:21:28 + \_interface_inst: work@mem_interface (work@mem_interface), file:${SURELOG_DIR}/tests/InterfaceModPort/top.v, line:1:1, endln:21:28 |vpiRhs: \_constant: , line:3:27, endln:3:30 |vpiSize:32 @@ -1903,7 +1903,7 @@ design: (work@interface_modports) |vpiParamAssign: \_param_assign: , line:4:14, endln:4:29 |vpiParent: - \_interface: work@mem_interface (work@mem_interface), file:${SURELOG_DIR}/tests/InterfaceModPort/top.v, line:1:1, endln:21:28 + \_interface_inst: work@mem_interface (work@mem_interface), file:${SURELOG_DIR}/tests/InterfaceModPort/top.v, line:1:1, endln:21:28 |vpiRhs: \_constant: , line:4:26, endln:4:29 |vpiSize:32 @@ -1917,41 +1917,41 @@ design: (work@interface_modports) |vpiNet: \_logic_net: (work@mem_interface.clock), line:1:35, endln:1:40 |vpiParent: - \_interface: work@mem_interface (work@mem_interface), file:${SURELOG_DIR}/tests/InterfaceModPort/top.v, line:1:1, endln:21:28 + \_interface_inst: work@mem_interface (work@mem_interface), file:${SURELOG_DIR}/tests/InterfaceModPort/top.v, line:1:1, endln:21:28 |vpiName:clock |vpiFullName:work@mem_interface.clock |vpiNet: \_logic_net: (work@mem_interface.mem_data), line:6:15, endln:6:23 |vpiParent: - \_interface: work@mem_interface (work@mem_interface), file:${SURELOG_DIR}/tests/InterfaceModPort/top.v, line:1:1, endln:21:28 + \_interface_inst: work@mem_interface (work@mem_interface), file:${SURELOG_DIR}/tests/InterfaceModPort/top.v, line:1:1, endln:21:28 |vpiName:mem_data |vpiFullName:work@mem_interface.mem_data |vpiNetType:1 |vpiNet: \_logic_net: (work@mem_interface.mem_add), line:7:15, endln:7:22 |vpiParent: - \_interface: work@mem_interface (work@mem_interface), file:${SURELOG_DIR}/tests/InterfaceModPort/top.v, line:1:1, endln:21:28 + \_interface_inst: work@mem_interface (work@mem_interface), file:${SURELOG_DIR}/tests/InterfaceModPort/top.v, line:1:1, endln:21:28 |vpiName:mem_add |vpiFullName:work@mem_interface.mem_add |vpiNetType:1 |vpiNet: \_logic_net: (work@mem_interface.mem_en), line:8:15, endln:8:21 |vpiParent: - \_interface: work@mem_interface (work@mem_interface), file:${SURELOG_DIR}/tests/InterfaceModPort/top.v, line:1:1, endln:21:28 + \_interface_inst: work@mem_interface (work@mem_interface), file:${SURELOG_DIR}/tests/InterfaceModPort/top.v, line:1:1, endln:21:28 |vpiName:mem_en |vpiFullName:work@mem_interface.mem_en |vpiNetType:1 |vpiNet: \_logic_net: (work@mem_interface.mem_rd_wr), line:9:15, endln:9:24 |vpiParent: - \_interface: work@mem_interface (work@mem_interface), file:${SURELOG_DIR}/tests/InterfaceModPort/top.v, line:1:1, endln:21:28 + \_interface_inst: work@mem_interface (work@mem_interface), file:${SURELOG_DIR}/tests/InterfaceModPort/top.v, line:1:1, endln:21:28 |vpiName:mem_rd_wr |vpiFullName:work@mem_interface.mem_rd_wr |vpiNetType:1 |vpiModport: \_modport: (MEM), line:19:12, endln:19:15 |vpiParent: - \_interface: work@mem_interface (work@mem_interface), file:${SURELOG_DIR}/tests/InterfaceModPort/top.v, line:1:1, endln:21:28 + \_interface_inst: work@mem_interface (work@mem_interface), file:${SURELOG_DIR}/tests/InterfaceModPort/top.v, line:1:1, endln:21:28 |vpiName:MEM |vpiIODecl: \_io_decl: (clock), line:19:34, endln:19:39 @@ -1995,7 +1995,7 @@ design: (work@interface_modports) |vpiPort: \_port: (clock), line:1:35, endln:1:40 |vpiParent: - \_interface: work@mem_interface (work@mem_interface), file:${SURELOG_DIR}/tests/InterfaceModPort/top.v, line:1:1, endln:21:28 + \_interface_inst: work@mem_interface (work@mem_interface), file:${SURELOG_DIR}/tests/InterfaceModPort/top.v, line:1:1, endln:21:28 |vpiName:clock |vpiDirection:1 |vpiLowConn: @@ -2062,7 +2062,7 @@ design: (work@interface_modports) |vpiLowConn: \_ref_obj: |uhdmallModules: -\_module: work@interface_modports (work@interface_modports), file:${SURELOG_DIR}/tests/InterfaceModPort/top.v, line:112:1, endln:124:10 +\_module_inst: work@interface_modports (work@interface_modports), file:${SURELOG_DIR}/tests/InterfaceModPort/top.v, line:112:1, endln:124:10 |vpiParent: \_design: (work@interface_modports) |vpiFullName:work@interface_modports @@ -2070,14 +2070,14 @@ design: (work@interface_modports) |vpiNet: \_logic_net: (work@interface_modports.clk), line:114:7, endln:114:10 |vpiParent: - \_module: work@interface_modports (work@interface_modports), file:${SURELOG_DIR}/tests/InterfaceModPort/top.v, line:112:1, endln:124:10 + \_module_inst: work@interface_modports (work@interface_modports), file:${SURELOG_DIR}/tests/InterfaceModPort/top.v, line:112:1, endln:124:10 |vpiName:clk |vpiFullName:work@interface_modports.clk |vpiNetType:36 |vpiProcess: \_always: , line:115:1, endln:115:18 |vpiParent: - \_module: work@interface_modports (work@interface_modports), file:${SURELOG_DIR}/tests/InterfaceModPort/top.v, line:112:1, endln:124:10 + \_module_inst: work@interface_modports (work@interface_modports), file:${SURELOG_DIR}/tests/InterfaceModPort/top.v, line:112:1, endln:124:10 |vpiStmt: \_delay_control: , line:115:8, endln:115:11 |vpiParent: @@ -2098,17 +2098,17 @@ design: (work@interface_modports) \_logic_var: (work@interface_modports.clk), line:114:7, endln:114:14 |vpiAlwaysType:1 |uhdmallModules: -\_module: work@memory_ctrl (work@memory_ctrl), file:${SURELOG_DIR}/tests/InterfaceModPort/top.v, line:87:1, endln:94:10 +\_module_inst: work@memory_ctrl (work@memory_ctrl), file:${SURELOG_DIR}/tests/InterfaceModPort/top.v, line:87:1, endln:94:10 |vpiParent: \_design: (work@interface_modports) |vpiFullName:work@memory_ctrl |vpiTypedef: \_enum_typespec: (fsm_t), line:89:1, endln:89:44 |vpiParent: - \_module: work@memory_ctrl (work@memory_ctrl), file:${SURELOG_DIR}/tests/InterfaceModPort/top.v, line:87:1, endln:94:10 + \_module_inst: work@memory_ctrl (work@memory_ctrl), file:${SURELOG_DIR}/tests/InterfaceModPort/top.v, line:87:1, endln:94:10 |vpiName:fsm_t |vpiInstance: - \_module: work@memory_ctrl (work@memory_ctrl), file:${SURELOG_DIR}/tests/InterfaceModPort/top.v, line:87:1, endln:94:10 + \_module_inst: work@memory_ctrl (work@memory_ctrl), file:${SURELOG_DIR}/tests/InterfaceModPort/top.v, line:87:1, endln:94:10 |vpiEnumConst: \_enum_const: (IDLE), line:89:16, endln:89:20 |vpiName:IDLE @@ -2137,19 +2137,19 @@ design: (work@interface_modports) |vpiNet: \_logic_net: (work@memory_ctrl.state), line:91:7, endln:91:12 |vpiParent: - \_module: work@memory_ctrl (work@memory_ctrl), file:${SURELOG_DIR}/tests/InterfaceModPort/top.v, line:87:1, endln:94:10 + \_module_inst: work@memory_ctrl (work@memory_ctrl), file:${SURELOG_DIR}/tests/InterfaceModPort/top.v, line:87:1, endln:94:10 |vpiName:state |vpiFullName:work@memory_ctrl.state |vpiNet: \_logic_net: (work@memory_ctrl.sif), line:87:35, endln:87:38 |vpiParent: - \_module: work@memory_ctrl (work@memory_ctrl), file:${SURELOG_DIR}/tests/InterfaceModPort/top.v, line:87:1, endln:94:10 + \_module_inst: work@memory_ctrl (work@memory_ctrl), file:${SURELOG_DIR}/tests/InterfaceModPort/top.v, line:87:1, endln:94:10 |vpiName:sif |vpiFullName:work@memory_ctrl.sif |vpiPort: \_port: (sif), line:87:35, endln:87:38 |vpiParent: - \_module: work@memory_ctrl (work@memory_ctrl), file:${SURELOG_DIR}/tests/InterfaceModPort/top.v, line:87:1, endln:94:10 + \_module_inst: work@memory_ctrl (work@memory_ctrl), file:${SURELOG_DIR}/tests/InterfaceModPort/top.v, line:87:1, endln:94:10 |vpiName:sif |vpiDirection:3 |vpiLowConn: @@ -2163,7 +2163,7 @@ design: (work@interface_modports) |vpiName:system |vpiIsModPort:1 |uhdmallModules: -\_module: work@memory_model (work@memory_model), file:${SURELOG_DIR}/tests/InterfaceModPort/top.v, line:62:1, endln:82:10 +\_module_inst: work@memory_model (work@memory_model), file:${SURELOG_DIR}/tests/InterfaceModPort/top.v, line:62:1, endln:82:10 |vpiParent: \_design: (work@interface_modports) |vpiFullName:work@memory_model @@ -2171,20 +2171,20 @@ design: (work@interface_modports) |vpiNet: \_logic_net: (work@memory_model.mem), line:64:13, endln:64:16 |vpiParent: - \_module: work@memory_model (work@memory_model), file:${SURELOG_DIR}/tests/InterfaceModPort/top.v, line:62:1, endln:82:10 + \_module_inst: work@memory_model (work@memory_model), file:${SURELOG_DIR}/tests/InterfaceModPort/top.v, line:62:1, endln:82:10 |vpiName:mem |vpiFullName:work@memory_model.mem |vpiNetType:36 |vpiNet: \_logic_net: (work@memory_model.mif), line:62:36, endln:62:39 |vpiParent: - \_module: work@memory_model (work@memory_model), file:${SURELOG_DIR}/tests/InterfaceModPort/top.v, line:62:1, endln:82:10 + \_module_inst: work@memory_model (work@memory_model), file:${SURELOG_DIR}/tests/InterfaceModPort/top.v, line:62:1, endln:82:10 |vpiName:mif |vpiFullName:work@memory_model.mif |vpiPort: \_port: (mif), line:62:36, endln:62:39 |vpiParent: - \_module: work@memory_model (work@memory_model), file:${SURELOG_DIR}/tests/InterfaceModPort/top.v, line:62:1, endln:82:10 + \_module_inst: work@memory_model (work@memory_model), file:${SURELOG_DIR}/tests/InterfaceModPort/top.v, line:62:1, endln:82:10 |vpiName:mif |vpiDirection:3 |vpiLowConn: @@ -2200,7 +2200,7 @@ design: (work@interface_modports) |vpiProcess: \_always: , line:69:1, endln:72:5 |vpiParent: - \_module: work@memory_model (work@memory_model), file:${SURELOG_DIR}/tests/InterfaceModPort/top.v, line:62:1, endln:82:10 + \_module_inst: work@memory_model (work@memory_model), file:${SURELOG_DIR}/tests/InterfaceModPort/top.v, line:62:1, endln:82:10 |vpiStmt: \_event_control: , line:69:8, endln:69:27 |vpiParent: @@ -2308,7 +2308,7 @@ design: (work@interface_modports) |vpiProcess: \_always: , line:77:1, endln:80:5 |vpiParent: - \_module: work@memory_model (work@memory_model), file:${SURELOG_DIR}/tests/InterfaceModPort/top.v, line:62:1, endln:82:10 + \_module_inst: work@memory_model (work@memory_model), file:${SURELOG_DIR}/tests/InterfaceModPort/top.v, line:62:1, endln:82:10 |vpiStmt: \_event_control: , line:77:8, endln:77:27 |vpiParent: @@ -2419,12 +2419,12 @@ design: (work@interface_modports) |vpiName:datao_mem |vpiAlwaysType:1 |uhdmtopModules: -\_module: work@interface_modports (work@interface_modports), file:${SURELOG_DIR}/tests/InterfaceModPort/top.v, line:112:1, endln:124:10 +\_module_inst: work@interface_modports (work@interface_modports), file:${SURELOG_DIR}/tests/InterfaceModPort/top.v, line:112:1, endln:124:10 |vpiName:work@interface_modports |vpiVariables: \_logic_var: (work@interface_modports.clk), line:114:7, endln:114:14 |vpiParent: - \_module: work@interface_modports (work@interface_modports), file:${SURELOG_DIR}/tests/InterfaceModPort/top.v, line:112:1, endln:124:10 + \_module_inst: work@interface_modports (work@interface_modports), file:${SURELOG_DIR}/tests/InterfaceModPort/top.v, line:112:1, endln:124:10 |vpiTypespec: \_logic_typespec: , line:114:1, endln:114:6 |vpiName:clk @@ -2441,14 +2441,14 @@ design: (work@interface_modports) |vpiProgram: \_program: work@test (work@interface_modports.U_test), file:${SURELOG_DIR}/tests/InterfaceModPort/top.v, line:122:1, endln:122:21 |vpiParent: - \_module: work@interface_modports (work@interface_modports), file:${SURELOG_DIR}/tests/InterfaceModPort/top.v, line:112:1, endln:124:10 + \_module_inst: work@interface_modports (work@interface_modports), file:${SURELOG_DIR}/tests/InterfaceModPort/top.v, line:112:1, endln:124:10 |vpiName:U_test |vpiFullName:work@interface_modports.U_test |vpiDefName:work@test |vpiDefFile:${SURELOG_DIR}/tests/InterfaceModPort/top.v |vpiDefLineNo:99 |vpiInstance: - \_module: work@interface_modports (work@interface_modports), file:${SURELOG_DIR}/tests/InterfaceModPort/top.v, line:112:1, endln:124:10 + \_module_inst: work@interface_modports (work@interface_modports), file:${SURELOG_DIR}/tests/InterfaceModPort/top.v, line:112:1, endln:124:10 |vpiProcess: \_initial: , line:101:4, endln:105:7 |vpiPort: @@ -2462,7 +2462,7 @@ design: (work@interface_modports) |vpiName:miff |vpiFullName:work@interface_modports.miff |vpiActual: - \_interface: work@mem_if (work@interface_modports.miff), file:${SURELOG_DIR}/tests/InterfaceModPort/top.v, line:119:0 + \_interface_inst: work@mem_if (work@interface_modports.miff), file:${SURELOG_DIR}/tests/InterfaceModPort/top.v, line:119:0 |vpiLowConn: \_ref_obj: (work@interface_modports.U_test.tif), line:122:15, endln:122:19 |vpiFullName:work@interface_modports.U_test.tif @@ -2475,16 +2475,16 @@ design: (work@interface_modports) |vpiName:tb |vpiIsModPort:1 |vpiTopModule:1 - |vpiInterface: - \_interface: work@mem_if (work@interface_modports.miff), file:${SURELOG_DIR}/tests/InterfaceModPort/top.v, line:119:1, endln:119:18 + |vpiInterfaceInst: + \_interface_inst: work@mem_if (work@interface_modports.miff), file:${SURELOG_DIR}/tests/InterfaceModPort/top.v, line:119:1, endln:119:18 |vpiParent: - \_module: work@interface_modports (work@interface_modports), file:${SURELOG_DIR}/tests/InterfaceModPort/top.v, line:112:1, endln:124:10 + \_module_inst: work@interface_modports (work@interface_modports), file:${SURELOG_DIR}/tests/InterfaceModPort/top.v, line:112:1, endln:124:10 |vpiName:miff |vpiFullName:work@interface_modports.miff |vpiVariables: \_logic_var: (work@interface_modports.miff.reset), line:27:16, endln:27:21 |vpiParent: - \_interface: work@mem_if (work@interface_modports.miff), file:${SURELOG_DIR}/tests/InterfaceModPort/top.v, line:119:1, endln:119:18 + \_interface_inst: work@mem_if (work@interface_modports.miff), file:${SURELOG_DIR}/tests/InterfaceModPort/top.v, line:119:1, endln:119:18 |vpiTypespec: \_logic_typespec: , line:27:3, endln:27:8 |vpiName:reset @@ -2493,7 +2493,7 @@ design: (work@interface_modports) |vpiVariables: \_logic_var: (work@interface_modports.miff.we_sys), line:28:16, endln:28:22 |vpiParent: - \_interface: work@mem_if (work@interface_modports.miff), file:${SURELOG_DIR}/tests/InterfaceModPort/top.v, line:119:1, endln:119:18 + \_interface_inst: work@mem_if (work@interface_modports.miff), file:${SURELOG_DIR}/tests/InterfaceModPort/top.v, line:119:1, endln:119:18 |vpiTypespec: \_logic_typespec: , line:28:3, endln:28:8 |vpiName:we_sys @@ -2502,7 +2502,7 @@ design: (work@interface_modports) |vpiVariables: \_logic_var: (work@interface_modports.miff.cmd_valid_sys), line:29:16, endln:29:29 |vpiParent: - \_interface: work@mem_if (work@interface_modports.miff), file:${SURELOG_DIR}/tests/InterfaceModPort/top.v, line:119:1, endln:119:18 + \_interface_inst: work@mem_if (work@interface_modports.miff), file:${SURELOG_DIR}/tests/InterfaceModPort/top.v, line:119:1, endln:119:18 |vpiTypespec: \_logic_typespec: , line:29:3, endln:29:8 |vpiName:cmd_valid_sys @@ -2511,7 +2511,7 @@ design: (work@interface_modports) |vpiVariables: \_logic_var: (work@interface_modports.miff.ready_sys), line:30:16, endln:30:25 |vpiParent: - \_interface: work@mem_if (work@interface_modports.miff), file:${SURELOG_DIR}/tests/InterfaceModPort/top.v, line:119:1, endln:119:18 + \_interface_inst: work@mem_if (work@interface_modports.miff), file:${SURELOG_DIR}/tests/InterfaceModPort/top.v, line:119:1, endln:119:18 |vpiTypespec: \_logic_typespec: , line:30:3, endln:30:8 |vpiName:ready_sys @@ -2520,7 +2520,7 @@ design: (work@interface_modports) |vpiVariables: \_logic_var: (work@interface_modports.miff.data_sys), line:31:16, endln:31:24 |vpiParent: - \_interface: work@mem_if (work@interface_modports.miff), file:${SURELOG_DIR}/tests/InterfaceModPort/top.v, line:119:1, endln:119:18 + \_interface_inst: work@mem_if (work@interface_modports.miff), file:${SURELOG_DIR}/tests/InterfaceModPort/top.v, line:119:1, endln:119:18 |vpiTypespec: \_logic_typespec: , line:31:3, endln:31:15 |vpiRange: @@ -2565,7 +2565,7 @@ design: (work@interface_modports) |vpiVariables: \_logic_var: (work@interface_modports.miff.addr_sys), line:32:16, endln:32:24 |vpiParent: - \_interface: work@mem_if (work@interface_modports.miff), file:${SURELOG_DIR}/tests/InterfaceModPort/top.v, line:119:1, endln:119:18 + \_interface_inst: work@mem_if (work@interface_modports.miff), file:${SURELOG_DIR}/tests/InterfaceModPort/top.v, line:119:1, endln:119:18 |vpiTypespec: \_logic_typespec: , line:32:3, endln:32:15 |vpiRange: @@ -2610,7 +2610,7 @@ design: (work@interface_modports) |vpiVariables: \_logic_var: (work@interface_modports.miff.we_mem), line:33:16, endln:33:22 |vpiParent: - \_interface: work@mem_if (work@interface_modports.miff), file:${SURELOG_DIR}/tests/InterfaceModPort/top.v, line:119:1, endln:119:18 + \_interface_inst: work@mem_if (work@interface_modports.miff), file:${SURELOG_DIR}/tests/InterfaceModPort/top.v, line:119:1, endln:119:18 |vpiTypespec: \_logic_typespec: , line:33:3, endln:33:8 |vpiName:we_mem @@ -2619,7 +2619,7 @@ design: (work@interface_modports) |vpiVariables: \_logic_var: (work@interface_modports.miff.ce_mem), line:34:16, endln:34:22 |vpiParent: - \_interface: work@mem_if (work@interface_modports.miff), file:${SURELOG_DIR}/tests/InterfaceModPort/top.v, line:119:1, endln:119:18 + \_interface_inst: work@mem_if (work@interface_modports.miff), file:${SURELOG_DIR}/tests/InterfaceModPort/top.v, line:119:1, endln:119:18 |vpiTypespec: \_logic_typespec: , line:34:3, endln:34:8 |vpiName:ce_mem @@ -2628,7 +2628,7 @@ design: (work@interface_modports) |vpiVariables: \_logic_var: (work@interface_modports.miff.datao_mem), line:35:16, endln:35:25 |vpiParent: - \_interface: work@mem_if (work@interface_modports.miff), file:${SURELOG_DIR}/tests/InterfaceModPort/top.v, line:119:1, endln:119:18 + \_interface_inst: work@mem_if (work@interface_modports.miff), file:${SURELOG_DIR}/tests/InterfaceModPort/top.v, line:119:1, endln:119:18 |vpiTypespec: \_logic_typespec: , line:35:3, endln:35:15 |vpiRange: @@ -2673,7 +2673,7 @@ design: (work@interface_modports) |vpiVariables: \_logic_var: (work@interface_modports.miff.datai_mem), line:36:16, endln:36:25 |vpiParent: - \_interface: work@mem_if (work@interface_modports.miff), file:${SURELOG_DIR}/tests/InterfaceModPort/top.v, line:119:1, endln:119:18 + \_interface_inst: work@mem_if (work@interface_modports.miff), file:${SURELOG_DIR}/tests/InterfaceModPort/top.v, line:119:1, endln:119:18 |vpiTypespec: \_logic_typespec: , line:36:3, endln:36:15 |vpiRange: @@ -2718,7 +2718,7 @@ design: (work@interface_modports) |vpiVariables: \_logic_var: (work@interface_modports.miff.addr_mem), line:37:16, endln:37:24 |vpiParent: - \_interface: work@mem_if (work@interface_modports.miff), file:${SURELOG_DIR}/tests/InterfaceModPort/top.v, line:119:1, endln:119:18 + \_interface_inst: work@mem_if (work@interface_modports.miff), file:${SURELOG_DIR}/tests/InterfaceModPort/top.v, line:119:1, endln:119:18 |vpiTypespec: \_logic_typespec: , line:37:3, endln:37:15 |vpiRange: @@ -2766,18 +2766,18 @@ design: (work@interface_modports) |vpiNet: \_logic_net: (work@interface_modports.miff.clk), line:26:30, endln:26:33 |vpiParent: - \_interface: work@mem_if (work@interface_modports.miff), file:${SURELOG_DIR}/tests/InterfaceModPort/top.v, line:119:1, endln:119:18 + \_interface_inst: work@mem_if (work@interface_modports.miff), file:${SURELOG_DIR}/tests/InterfaceModPort/top.v, line:119:1, endln:119:18 |vpiTypespec: \_logic_typespec: , line:26:25, endln:26:29 |vpiName:clk |vpiFullName:work@interface_modports.miff.clk |vpiNetType:1 |vpiInstance: - \_module: work@interface_modports (work@interface_modports), file:${SURELOG_DIR}/tests/InterfaceModPort/top.v, line:112:1, endln:124:10 + \_module_inst: work@interface_modports (work@interface_modports), file:${SURELOG_DIR}/tests/InterfaceModPort/top.v, line:112:1, endln:124:10 |vpiModport: \_modport: (memory), line:48:12, endln:48:18 |vpiParent: - \_interface: work@mem_if (work@interface_modports.miff), file:${SURELOG_DIR}/tests/InterfaceModPort/top.v, line:119:1, endln:119:18 + \_interface_inst: work@mem_if (work@interface_modports.miff), file:${SURELOG_DIR}/tests/InterfaceModPort/top.v, line:119:1, endln:119:18 |vpiName:memory |vpiIODecl: \_io_decl: (clk), line:48:26, endln:48:29 @@ -2821,12 +2821,12 @@ design: (work@interface_modports) \_modport: (memory), line:48:12, endln:48:18 |vpiDirection:2 |vpiName:datao_mem - |vpiInterface: - \_interface: work@mem_if (work@interface_modports.miff), file:${SURELOG_DIR}/tests/InterfaceModPort/top.v, line:119:1, endln:119:18 + |vpiInterfaceInst: + \_interface_inst: work@mem_if (work@interface_modports.miff), file:${SURELOG_DIR}/tests/InterfaceModPort/top.v, line:119:1, endln:119:18 |vpiModport: \_modport: (system), line:41:12, endln:41:18 |vpiParent: - \_interface: work@mem_if (work@interface_modports.miff), file:${SURELOG_DIR}/tests/InterfaceModPort/top.v, line:119:1, endln:119:18 + \_interface_inst: work@mem_if (work@interface_modports.miff), file:${SURELOG_DIR}/tests/InterfaceModPort/top.v, line:119:1, endln:119:18 |vpiName:system |vpiIODecl: \_io_decl: (clk), line:41:26, endln:41:29 @@ -2900,12 +2900,12 @@ design: (work@interface_modports) \_modport: (system), line:41:12, endln:41:18 |vpiDirection:3 |vpiName:data_sys - |vpiInterface: - \_interface: work@mem_if (work@interface_modports.miff), file:${SURELOG_DIR}/tests/InterfaceModPort/top.v, line:119:1, endln:119:18 + |vpiInterfaceInst: + \_interface_inst: work@mem_if (work@interface_modports.miff), file:${SURELOG_DIR}/tests/InterfaceModPort/top.v, line:119:1, endln:119:18 |vpiModport: \_modport: (tb), line:53:12, endln:53:14 |vpiParent: - \_interface: work@mem_if (work@interface_modports.miff), file:${SURELOG_DIR}/tests/InterfaceModPort/top.v, line:119:1, endln:119:18 + \_interface_inst: work@mem_if (work@interface_modports.miff), file:${SURELOG_DIR}/tests/InterfaceModPort/top.v, line:119:1, endln:119:18 |vpiName:tb |vpiIODecl: \_io_decl: (clk), line:53:22, endln:53:25 @@ -2949,12 +2949,12 @@ design: (work@interface_modports) \_modport: (tb), line:53:12, endln:53:14 |vpiDirection:3 |vpiName:data_sys - |vpiInterface: - \_interface: work@mem_if (work@interface_modports.miff), file:${SURELOG_DIR}/tests/InterfaceModPort/top.v, line:119:1, endln:119:18 + |vpiInterfaceInst: + \_interface_inst: work@mem_if (work@interface_modports.miff), file:${SURELOG_DIR}/tests/InterfaceModPort/top.v, line:119:1, endln:119:18 |vpiPort: \_port: (clk), line:26:30, endln:26:33 |vpiParent: - \_interface: work@mem_if (work@interface_modports.miff), file:${SURELOG_DIR}/tests/InterfaceModPort/top.v, line:119:1, endln:119:18 + \_interface_inst: work@mem_if (work@interface_modports.miff), file:${SURELOG_DIR}/tests/InterfaceModPort/top.v, line:119:1, endln:119:18 |vpiName:clk |vpiDirection:1 |vpiHighConn: @@ -2973,16 +2973,16 @@ design: (work@interface_modports) \_logic_typespec: , line:26:25, endln:26:29 |vpiProcess: \_always: , line:115:1, endln:115:18 - |vpiModule: - \_module: work@memory_ctrl (work@interface_modports.U_ctrl), file:${SURELOG_DIR}/tests/InterfaceModPort/top.v, line:120:1, endln:120:26 + |vpiModuleInst: + \_module_inst: work@memory_ctrl (work@interface_modports.U_ctrl), file:${SURELOG_DIR}/tests/InterfaceModPort/top.v, line:120:1, endln:120:26 |vpiParent: - \_module: work@interface_modports (work@interface_modports), file:${SURELOG_DIR}/tests/InterfaceModPort/top.v, line:112:1, endln:124:10 + \_module_inst: work@interface_modports (work@interface_modports), file:${SURELOG_DIR}/tests/InterfaceModPort/top.v, line:112:1, endln:124:10 |vpiName:U_ctrl |vpiFullName:work@interface_modports.U_ctrl |vpiVariables: \_enum_var: (work@interface_modports.U_ctrl.state), line:91:7, endln:91:12 |vpiParent: - \_module: work@memory_ctrl (work@interface_modports.U_ctrl), file:${SURELOG_DIR}/tests/InterfaceModPort/top.v, line:120:1, endln:120:26 + \_module_inst: work@memory_ctrl (work@interface_modports.U_ctrl), file:${SURELOG_DIR}/tests/InterfaceModPort/top.v, line:120:1, endln:120:26 |vpiTypespec: \_enum_typespec: (fsm_t), line:89:1, endln:89:44 |vpiName:state @@ -2994,11 +2994,11 @@ design: (work@interface_modports) |vpiDefFile:${SURELOG_DIR}/tests/InterfaceModPort/top.v |vpiDefLineNo:87 |vpiInstance: - \_module: work@interface_modports (work@interface_modports), file:${SURELOG_DIR}/tests/InterfaceModPort/top.v, line:112:1, endln:124:10 + \_module_inst: work@interface_modports (work@interface_modports), file:${SURELOG_DIR}/tests/InterfaceModPort/top.v, line:112:1, endln:124:10 |vpiPort: \_port: (sif), line:87:35, endln:87:38 |vpiParent: - \_module: work@memory_ctrl (work@interface_modports.U_ctrl), file:${SURELOG_DIR}/tests/InterfaceModPort/top.v, line:120:1, endln:120:26 + \_module_inst: work@memory_ctrl (work@interface_modports.U_ctrl), file:${SURELOG_DIR}/tests/InterfaceModPort/top.v, line:120:1, endln:120:26 |vpiName:sif |vpiDirection:3 |vpiHighConn: @@ -3006,7 +3006,7 @@ design: (work@interface_modports) |vpiName:miff |vpiFullName:work@interface_modports.miff |vpiActual: - \_interface: work@mem_if (work@interface_modports.miff), file:${SURELOG_DIR}/tests/InterfaceModPort/top.v, line:119:0 + \_interface_inst: work@mem_if (work@interface_modports.miff), file:${SURELOG_DIR}/tests/InterfaceModPort/top.v, line:119:0 |vpiLowConn: \_ref_obj: (work@interface_modports.U_ctrl.sif), line:120:20, endln:120:24 |vpiFullName:work@interface_modports.U_ctrl.sif @@ -3018,17 +3018,17 @@ design: (work@interface_modports) \_interface_typespec: (mem_if), line:87:21, endln:87:27 |vpiName:system |vpiIsModPort:1 - |vpiInterface: - \_interface: work@mem_if (work@interface_modports.U_ctrl.sif), file:${SURELOG_DIR}/tests/InterfaceModPort/top.v, line:120:0 + |vpiInterfaceInst: + \_interface_inst: work@mem_if (work@interface_modports.U_ctrl.sif), file:${SURELOG_DIR}/tests/InterfaceModPort/top.v, line:120:0 |vpiParent: - \_module: work@memory_ctrl (work@interface_modports.U_ctrl), file:${SURELOG_DIR}/tests/InterfaceModPort/top.v, line:120:1, endln:120:26 + \_module_inst: work@memory_ctrl (work@interface_modports.U_ctrl), file:${SURELOG_DIR}/tests/InterfaceModPort/top.v, line:120:1, endln:120:26 |vpiName:sif |vpiFullName:work@interface_modports.U_ctrl.sif |vpiDefName:work@mem_if |vpiModport: \_modport: (system), line:41:12, endln:41:18 |vpiParent: - \_interface: work@mem_if (work@interface_modports.U_ctrl.sif), file:${SURELOG_DIR}/tests/InterfaceModPort/top.v, line:120:0 + \_interface_inst: work@mem_if (work@interface_modports.U_ctrl.sif), file:${SURELOG_DIR}/tests/InterfaceModPort/top.v, line:120:0 |vpiName:system |vpiIODecl: \_io_decl: (clk), line:41:26, endln:41:29 @@ -3330,18 +3330,18 @@ design: (work@interface_modports) |vpiSize:64 |UINT:0 |vpiConstType:9 - |vpiInterface: - \_interface: work@mem_if (work@interface_modports.U_ctrl.sif), file:${SURELOG_DIR}/tests/InterfaceModPort/top.v, line:120:0 - |vpiModule: - \_module: work@memory_model (work@interface_modports.U_model), file:${SURELOG_DIR}/tests/InterfaceModPort/top.v, line:121:1, endln:121:28 + |vpiInterfaceInst: + \_interface_inst: work@mem_if (work@interface_modports.U_ctrl.sif), file:${SURELOG_DIR}/tests/InterfaceModPort/top.v, line:120:0 + |vpiModuleInst: + \_module_inst: work@memory_model (work@interface_modports.U_model), file:${SURELOG_DIR}/tests/InterfaceModPort/top.v, line:121:1, endln:121:28 |vpiParent: - \_module: work@interface_modports (work@interface_modports), file:${SURELOG_DIR}/tests/InterfaceModPort/top.v, line:112:1, endln:124:10 + \_module_inst: work@interface_modports (work@interface_modports), file:${SURELOG_DIR}/tests/InterfaceModPort/top.v, line:112:1, endln:124:10 |vpiName:U_model |vpiFullName:work@interface_modports.U_model |vpiVariables: \_array_var: (work@interface_modports.U_model.mem), line:64:13, endln:64:24 |vpiParent: - \_module: work@memory_model (work@interface_modports.U_model), file:${SURELOG_DIR}/tests/InterfaceModPort/top.v, line:121:1, endln:121:28 + \_module_inst: work@memory_model (work@interface_modports.U_model), file:${SURELOG_DIR}/tests/InterfaceModPort/top.v, line:121:1, endln:121:28 |vpiSize:256 |vpiTypespec: \_array_typespec: @@ -3415,11 +3415,11 @@ design: (work@interface_modports) |vpiDefFile:${SURELOG_DIR}/tests/InterfaceModPort/top.v |vpiDefLineNo:62 |vpiInstance: - \_module: work@interface_modports (work@interface_modports), file:${SURELOG_DIR}/tests/InterfaceModPort/top.v, line:112:1, endln:124:10 + \_module_inst: work@interface_modports (work@interface_modports), file:${SURELOG_DIR}/tests/InterfaceModPort/top.v, line:112:1, endln:124:10 |vpiPort: \_port: (mif), line:62:36, endln:62:39 |vpiParent: - \_module: work@memory_model (work@interface_modports.U_model), file:${SURELOG_DIR}/tests/InterfaceModPort/top.v, line:121:1, endln:121:28 + \_module_inst: work@memory_model (work@interface_modports.U_model), file:${SURELOG_DIR}/tests/InterfaceModPort/top.v, line:121:1, endln:121:28 |vpiName:mif |vpiDirection:3 |vpiHighConn: @@ -3427,7 +3427,7 @@ design: (work@interface_modports) |vpiName:miff |vpiFullName:work@interface_modports.miff |vpiActual: - \_interface: work@mem_if (work@interface_modports.miff), file:${SURELOG_DIR}/tests/InterfaceModPort/top.v, line:119:0 + \_interface_inst: work@mem_if (work@interface_modports.miff), file:${SURELOG_DIR}/tests/InterfaceModPort/top.v, line:119:0 |vpiLowConn: \_ref_obj: (work@interface_modports.U_model.mif), line:121:22, endln:121:26 |vpiFullName:work@interface_modports.U_model.mif @@ -3439,17 +3439,17 @@ design: (work@interface_modports) \_interface_typespec: (mem_if), line:62:22, endln:62:28 |vpiName:memory |vpiIsModPort:1 - |vpiInterface: - \_interface: work@mem_if (work@interface_modports.U_model.mif), file:${SURELOG_DIR}/tests/InterfaceModPort/top.v, line:121:0 + |vpiInterfaceInst: + \_interface_inst: work@mem_if (work@interface_modports.U_model.mif), file:${SURELOG_DIR}/tests/InterfaceModPort/top.v, line:121:0 |vpiParent: - \_module: work@memory_model (work@interface_modports.U_model), file:${SURELOG_DIR}/tests/InterfaceModPort/top.v, line:121:1, endln:121:28 + \_module_inst: work@memory_model (work@interface_modports.U_model), file:${SURELOG_DIR}/tests/InterfaceModPort/top.v, line:121:1, endln:121:28 |vpiName:mif |vpiFullName:work@interface_modports.U_model.mif |vpiDefName:work@mem_if |vpiModport: \_modport: (memory), line:48:12, endln:48:18 |vpiParent: - \_interface: work@mem_if (work@interface_modports.U_model.mif), file:${SURELOG_DIR}/tests/InterfaceModPort/top.v, line:121:0 + \_interface_inst: work@mem_if (work@interface_modports.U_model.mif), file:${SURELOG_DIR}/tests/InterfaceModPort/top.v, line:121:0 |vpiName:memory |vpiIODecl: \_io_decl: (clk), line:48:26, endln:48:29 @@ -3629,8 +3629,8 @@ design: (work@interface_modports) |vpiSize:64 |UINT:0 |vpiConstType:9 - |vpiInterface: - \_interface: work@mem_if (work@interface_modports.U_model.mif), file:${SURELOG_DIR}/tests/InterfaceModPort/top.v, line:121:0 + |vpiInterfaceInst: + \_interface_inst: work@mem_if (work@interface_modports.U_model.mif), file:${SURELOG_DIR}/tests/InterfaceModPort/top.v, line:121:0 |vpiProcess: \_always: , line:69:1, endln:72:5 |vpiProcess: diff --git a/tests/InterfaceProcess/InterfaceProcess.log b/tests/InterfaceProcess/InterfaceProcess.log index 0561d02388..a9a5b0b902 100644 --- a/tests/InterfaceProcess/InterfaceProcess.log +++ b/tests/InterfaceProcess/InterfaceProcess.log @@ -123,11 +123,11 @@ constant 3 cont_assign 2 design 1 initial 1 -interface 3 +interface_inst 3 logic_net 2 logic_typespec 1 logic_var 1 -module 3 +module_inst 3 ref_obj 3 === UHDM Object Stats End === [INF:UH0707] Elaborating UHDM... @@ -141,11 +141,11 @@ constant 3 cont_assign 2 design 1 initial 1 -interface 3 +interface_inst 3 logic_net 2 logic_typespec 1 logic_var 1 -module 3 +module_inst 3 ref_obj 3 === UHDM Object Stats End === [INF:UH0708] Writing UHDM DB: ${SURELOG_DIR}/build/regression/InterfaceProcess/slpp_all/surelog.uhdm ... @@ -161,7 +161,7 @@ design: (work@top) |vpiElaborated:1 |vpiName:work@top |uhdmallInterfaces: -\_interface: work@sw_test_status_if (work@sw_test_status_if), file:${SURELOG_DIR}/tests/InterfaceProcess/dut.sv, line:1:1, endln:11:13 +\_interface_inst: work@sw_test_status_if (work@sw_test_status_if), file:${SURELOG_DIR}/tests/InterfaceProcess/dut.sv, line:1:1, endln:11:13 |vpiParent: \_design: (work@top) |vpiFullName:work@sw_test_status_if @@ -169,20 +169,20 @@ design: (work@top) |vpiNet: \_logic_net: (work@sw_test_status_if.data_valid), line:2:9, endln:2:19 |vpiParent: - \_interface: work@sw_test_status_if (work@sw_test_status_if), file:${SURELOG_DIR}/tests/InterfaceProcess/dut.sv, line:1:1, endln:11:13 + \_interface_inst: work@sw_test_status_if (work@sw_test_status_if), file:${SURELOG_DIR}/tests/InterfaceProcess/dut.sv, line:1:1, endln:11:13 |vpiName:data_valid |vpiFullName:work@sw_test_status_if.data_valid |vpiNetType:36 |vpiNet: \_logic_net: (work@sw_test_status_if.sw_test_done), line:5:7, endln:5:19 |vpiParent: - \_interface: work@sw_test_status_if (work@sw_test_status_if), file:${SURELOG_DIR}/tests/InterfaceProcess/dut.sv, line:1:1, endln:11:13 + \_interface_inst: work@sw_test_status_if (work@sw_test_status_if), file:${SURELOG_DIR}/tests/InterfaceProcess/dut.sv, line:1:1, endln:11:13 |vpiName:sw_test_done |vpiFullName:work@sw_test_status_if.sw_test_done |vpiContAssign: \_cont_assign: , line:3:10, endln:3:27 |vpiParent: - \_interface: work@sw_test_status_if (work@sw_test_status_if), file:${SURELOG_DIR}/tests/InterfaceProcess/dut.sv, line:1:1, endln:11:13 + \_interface_inst: work@sw_test_status_if (work@sw_test_status_if), file:${SURELOG_DIR}/tests/InterfaceProcess/dut.sv, line:1:1, endln:11:13 |vpiRhs: \_constant: , line:3:23, endln:3:27 |vpiParent: @@ -202,7 +202,7 @@ design: (work@top) |vpiProcess: \_initial: , line:6:3, endln:8:6 |vpiParent: - \_interface: work@sw_test_status_if (work@sw_test_status_if), file:${SURELOG_DIR}/tests/InterfaceProcess/dut.sv, line:1:1, endln:11:13 + \_interface_inst: work@sw_test_status_if (work@sw_test_status_if), file:${SURELOG_DIR}/tests/InterfaceProcess/dut.sv, line:1:1, endln:11:13 |vpiStmt: \_begin: (work@sw_test_status_if), line:6:11, endln:8:6 |vpiParent: @@ -231,27 +231,27 @@ design: (work@top) |vpiActual: \_bit_var: (work@top.u_sw.sw_test_done), line:5:7, endln:5:19 |uhdmallModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/InterfaceProcess/dut.sv, line:13:1, endln:15:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/InterfaceProcess/dut.sv, line:13:1, endln:15:10 |vpiParent: \_design: (work@top) |vpiFullName:work@top |vpiDefName:work@top |uhdmtopModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/InterfaceProcess/dut.sv, line:13:1, endln:15:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/InterfaceProcess/dut.sv, line:13:1, endln:15:10 |vpiName:work@top |vpiDefName:work@top |vpiTop:1 |vpiTopModule:1 - |vpiInterface: - \_interface: work@sw_test_status_if (work@top.u_sw), file:${SURELOG_DIR}/tests/InterfaceProcess/dut.sv, line:14:4, endln:14:29 + |vpiInterfaceInst: + \_interface_inst: work@sw_test_status_if (work@top.u_sw), file:${SURELOG_DIR}/tests/InterfaceProcess/dut.sv, line:14:4, endln:14:29 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/InterfaceProcess/dut.sv, line:13:1, endln:15:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/InterfaceProcess/dut.sv, line:13:1, endln:15:10 |vpiName:u_sw |vpiFullName:work@top.u_sw |vpiVariables: \_logic_var: (work@top.u_sw.data_valid), line:2:9, endln:2:19 |vpiParent: - \_interface: work@sw_test_status_if (work@top.u_sw), file:${SURELOG_DIR}/tests/InterfaceProcess/dut.sv, line:14:4, endln:14:29 + \_interface_inst: work@sw_test_status_if (work@top.u_sw), file:${SURELOG_DIR}/tests/InterfaceProcess/dut.sv, line:14:4, endln:14:29 |vpiTypespec: \_logic_typespec: , line:2:3, endln:2:8 |vpiName:data_valid @@ -260,7 +260,7 @@ design: (work@top) |vpiVariables: \_bit_var: (work@top.u_sw.sw_test_done), line:5:7, endln:5:19 |vpiParent: - \_interface: work@sw_test_status_if (work@top.u_sw), file:${SURELOG_DIR}/tests/InterfaceProcess/dut.sv, line:14:4, endln:14:29 + \_interface_inst: work@sw_test_status_if (work@top.u_sw), file:${SURELOG_DIR}/tests/InterfaceProcess/dut.sv, line:14:4, endln:14:29 |vpiTypespec: \_bit_typespec: , line:5:3, endln:5:6 |vpiSigned:1 @@ -271,7 +271,7 @@ design: (work@top) |vpiDefFile:${SURELOG_DIR}/tests/InterfaceProcess/dut.sv |vpiDefLineNo:1 |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/InterfaceProcess/dut.sv, line:13:1, endln:15:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/InterfaceProcess/dut.sv, line:13:1, endln:15:10 |vpiContAssign: \_cont_assign: , line:3:10, endln:3:27 |vpiRhs: diff --git a/tests/InterpElab1/InterpElab1.log b/tests/InterpElab1/InterpElab1.log index 7b887a9076..a734367835 100644 --- a/tests/InterpElab1/InterpElab1.log +++ b/tests/InterpElab1/InterpElab1.log @@ -47,7 +47,7 @@ int_var 4 io_decl 11 logic_typespec 4 logic_var 1 -module 5 +module_inst 5 operation 3 package 2 param_assign 6 @@ -76,7 +76,7 @@ int_var 4 io_decl 22 logic_typespec 4 logic_var 1 -module 5 +module_inst 5 operation 3 package 2 param_assign 6 @@ -576,14 +576,14 @@ design: (work@dut) \_int_typespec: |vpiSigned:1 |uhdmallModules: -\_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/InterpElab1/dut.sv, line:1:1, endln:21:10 +\_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/InterpElab1/dut.sv, line:1:1, endln:21:10 |vpiParent: \_design: (work@dut) |vpiFullName:work@dut |vpiParameter: \_parameter: (work@dut.TIMEOUT_CNT_W), line:3:28, endln:3:41 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/InterpElab1/dut.sv, line:1:1, endln:21:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/InterpElab1/dut.sv, line:1:1, endln:21:10 |UINT:5 |vpiTypespec: \_int_typespec: , line:3:15, endln:3:27 @@ -595,7 +595,7 @@ design: (work@dut) |vpiParameter: \_parameter: (work@dut.OP_W), line:4:28, endln:4:32 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/InterpElab1/dut.sv, line:1:1, endln:21:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/InterpElab1/dut.sv, line:1:1, endln:21:10 |UINT:5 |vpiTypespec: \_int_typespec: , line:4:15, endln:4:27 @@ -607,7 +607,7 @@ design: (work@dut) |vpiParameter: \_parameter: (work@dut.LFSR_OUT_W), line:19:29, endln:19:39 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/InterpElab1/dut.sv, line:1:1, endln:21:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/InterpElab1/dut.sv, line:1:1, endln:21:10 |vpiTypespec: \_int_typespec: , line:19:16, endln:19:28 |vpiParent: @@ -618,7 +618,7 @@ design: (work@dut) |vpiParamAssign: \_param_assign: , line:3:28, endln:3:45 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/InterpElab1/dut.sv, line:1:1, endln:21:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/InterpElab1/dut.sv, line:1:1, endln:21:10 |vpiRhs: \_constant: , line:3:44, endln:3:45 |vpiDecompile:5 @@ -632,7 +632,7 @@ design: (work@dut) |vpiParamAssign: \_param_assign: , line:4:28, endln:4:45 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/InterpElab1/dut.sv, line:1:1, endln:21:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/InterpElab1/dut.sv, line:1:1, endln:21:10 |vpiRhs: \_constant: , line:4:44, endln:4:45 |vpiDecompile:5 @@ -646,7 +646,7 @@ design: (work@dut) |vpiParamAssign: \_param_assign: , line:19:29, endln:19:60 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/InterpElab1/dut.sv, line:1:1, endln:21:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/InterpElab1/dut.sv, line:1:1, endln:21:10 |vpiRhs: \_sys_func_call: ($bits), line:19:42, endln:19:60 |vpiArgument: @@ -660,10 +660,10 @@ design: (work@dut) |vpiTypedef: \_enum_typespec: (dummy_instr_e), line:6:5, endln:11:21 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/InterpElab1/dut.sv, line:1:1, endln:21:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/InterpElab1/dut.sv, line:1:1, endln:21:10 |vpiName:dummy_instr_e |vpiInstance: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/InterpElab1/dut.sv, line:1:1, endln:21:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/InterpElab1/dut.sv, line:1:1, endln:21:10 |vpiBaseTypespec: \_logic_typespec: , line:6:18, endln:6:29 |vpiRange: @@ -711,10 +711,10 @@ design: (work@dut) |vpiTypedef: \_struct_typespec: (lfsr_data_t), line:13:13, endln:13:19 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/InterpElab1/dut.sv, line:1:1, endln:21:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/InterpElab1/dut.sv, line:1:1, endln:21:10 |vpiName:lfsr_data_t |vpiInstance: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/InterpElab1/dut.sv, line:1:1, endln:21:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/InterpElab1/dut.sv, line:1:1, endln:21:10 |vpiPacked:1 |vpiTypespecMember: \_typespec_member: (instr_type), line:14:33, endln:14:43 @@ -871,12 +871,12 @@ design: (work@dut) |vpiRefEndColumnNo:32 |vpiDefName:work@dut |uhdmtopModules: -\_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/InterpElab1/dut.sv, line:1:1, endln:21:10 +\_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/InterpElab1/dut.sv, line:1:1, endln:21:10 |vpiName:work@dut |vpiParameter: \_parameter: (work@dut.TIMEOUT_CNT_W), line:3:28, endln:3:41 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/InterpElab1/dut.sv, line:1:1, endln:21:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/InterpElab1/dut.sv, line:1:1, endln:21:10 |UINT:5 |vpiTypespec: \_int_typespec: , line:3:15, endln:3:27 @@ -888,7 +888,7 @@ design: (work@dut) |vpiParameter: \_parameter: (work@dut.OP_W), line:4:28, endln:4:32 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/InterpElab1/dut.sv, line:1:1, endln:21:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/InterpElab1/dut.sv, line:1:1, endln:21:10 |UINT:5 |vpiTypespec: \_int_typespec: , line:4:15, endln:4:27 @@ -900,7 +900,7 @@ design: (work@dut) |vpiParameter: \_parameter: (work@dut.LFSR_OUT_W), line:19:29, endln:19:39 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/InterpElab1/dut.sv, line:1:1, endln:21:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/InterpElab1/dut.sv, line:1:1, endln:21:10 |vpiTypespec: \_int_typespec: , line:19:16, endln:19:28 |vpiParent: @@ -911,7 +911,7 @@ design: (work@dut) |vpiParamAssign: \_param_assign: , line:3:28, endln:3:45 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/InterpElab1/dut.sv, line:1:1, endln:21:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/InterpElab1/dut.sv, line:1:1, endln:21:10 |vpiRhs: \_constant: , line:3:44, endln:3:45 |vpiDecompile:5 @@ -925,7 +925,7 @@ design: (work@dut) |vpiParamAssign: \_param_assign: , line:4:28, endln:4:45 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/InterpElab1/dut.sv, line:1:1, endln:21:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/InterpElab1/dut.sv, line:1:1, endln:21:10 |vpiRhs: \_constant: , line:4:44, endln:4:45 |vpiDecompile:5 @@ -939,7 +939,7 @@ design: (work@dut) |vpiParamAssign: \_param_assign: , line:19:29, endln:19:60 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/InterpElab1/dut.sv, line:1:1, endln:21:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/InterpElab1/dut.sv, line:1:1, endln:21:10 |vpiRhs: \_constant: , line:19:42, endln:19:60 |vpiDecompile:17 diff --git a/tests/InvalidTypeParam/InvalidTypeParam.log b/tests/InvalidTypeParam/InvalidTypeParam.log index 32198653bc..345728c074 100644 --- a/tests/InvalidTypeParam/InvalidTypeParam.log +++ b/tests/InvalidTypeParam/InvalidTypeParam.log @@ -84,10 +84,10 @@ n<> u<53> t c<1> l<1:1> el<8:1> constant 2 design 1 integer_typespec 1 -interface 3 +interface_inst 3 logic_net 1 logic_var 1 -module 3 +module_inst 3 type_parameter 1 === UHDM Object Stats End === [INF:UH0707] Elaborating UHDM... @@ -96,10 +96,10 @@ type_parameter 1 constant 2 design 1 integer_typespec 1 -interface 3 +interface_inst 3 logic_net 1 logic_var 1 -module 3 +module_inst 3 type_parameter 1 === UHDM Object Stats End === [INF:UH0708] Writing UHDM DB: ${SURELOG_DIR}/build/regression/InvalidTypeParam/slpp_all/surelog.uhdm ... @@ -115,45 +115,45 @@ design: (work@top) |vpiElaborated:1 |vpiName:work@top |uhdmallInterfaces: -\_interface: work@Interface (work@Interface), file:${SURELOG_DIR}/tests/InvalidTypeParam/dut.sv, line:1:1, endln:4:13 +\_interface_inst: work@Interface (work@Interface), file:${SURELOG_DIR}/tests/InvalidTypeParam/dut.sv, line:1:1, endln:4:13 |vpiParent: \_design: (work@top) |vpiFullName:work@Interface |vpiParameter: \_type_parameter: (work@Interface.P), line:2:20, endln:2:21 |vpiParent: - \_interface: work@Interface (work@Interface), file:${SURELOG_DIR}/tests/InvalidTypeParam/dut.sv, line:1:1, endln:4:13 + \_interface_inst: work@Interface (work@Interface), file:${SURELOG_DIR}/tests/InvalidTypeParam/dut.sv, line:1:1, endln:4:13 |vpiName:P |vpiFullName:work@Interface.P |vpiDefName:work@Interface |vpiNet: \_logic_net: (work@Interface.x), line:3:7, endln:3:8 |vpiParent: - \_interface: work@Interface (work@Interface), file:${SURELOG_DIR}/tests/InvalidTypeParam/dut.sv, line:1:1, endln:4:13 + \_interface_inst: work@Interface (work@Interface), file:${SURELOG_DIR}/tests/InvalidTypeParam/dut.sv, line:1:1, endln:4:13 |vpiName:x |vpiFullName:work@Interface.x |uhdmallModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/InvalidTypeParam/dut.sv, line:5:1, endln:7:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/InvalidTypeParam/dut.sv, line:5:1, endln:7:10 |vpiParent: \_design: (work@top) |vpiFullName:work@top |vpiDefName:work@top |uhdmtopModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/InvalidTypeParam/dut.sv, line:5:1, endln:7:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/InvalidTypeParam/dut.sv, line:5:1, endln:7:10 |vpiName:work@top |vpiDefName:work@top |vpiTop:1 |vpiTopModule:1 - |vpiInterface: - \_interface: work@Interface (work@top.intf), file:${SURELOG_DIR}/tests/InvalidTypeParam/dut.sv, line:6:5, endln:6:27 + |vpiInterfaceInst: + \_interface_inst: work@Interface (work@top.intf), file:${SURELOG_DIR}/tests/InvalidTypeParam/dut.sv, line:6:5, endln:6:27 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/InvalidTypeParam/dut.sv, line:5:1, endln:7:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/InvalidTypeParam/dut.sv, line:5:1, endln:7:10 |vpiName:intf |vpiFullName:work@top.intf |vpiVariables: \_logic_var: (work@top.intf.x), line:3:7, endln:3:8 |vpiParent: - \_interface: work@Interface (work@top.intf), file:${SURELOG_DIR}/tests/InvalidTypeParam/dut.sv, line:6:5, endln:6:27 + \_interface_inst: work@Interface (work@top.intf), file:${SURELOG_DIR}/tests/InvalidTypeParam/dut.sv, line:6:5, endln:6:27 |vpiName:x |vpiFullName:work@top.intf.x |vpiVisibility:1 @@ -163,7 +163,7 @@ design: (work@top) |vpiDefFile:${SURELOG_DIR}/tests/InvalidTypeParam/dut.sv |vpiDefLineNo:1 |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/InvalidTypeParam/dut.sv, line:5:1, endln:7:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/InvalidTypeParam/dut.sv, line:5:1, endln:7:10 =================== [ FATAL] : 0 [ SYNTAX] : 0 diff --git a/tests/Inverter/Inverter.log b/tests/Inverter/Inverter.log index 7a781c4900..4edc55a39d 100644 --- a/tests/Inverter/Inverter.log +++ b/tests/Inverter/Inverter.log @@ -124,7 +124,7 @@ cont_assign 3 design 1 logic_net 11 logic_typespec 16 -module 5 +module_inst 5 operation 3 port 10 ref_obj 20 @@ -136,7 +136,7 @@ cont_assign 5 design 1 logic_net 11 logic_typespec 16 -module 5 +module_inst 5 operation 5 port 16 ref_obj 34 @@ -154,7 +154,7 @@ design: (work@top) |vpiElaborated:1 |vpiName:work@top |uhdmallModules: -\_module: work@inverter (work@inverter), file:${SURELOG_DIR}/tests/Inverter/dut.sv, line:7:1, endln:12:10 +\_module_inst: work@inverter (work@inverter), file:${SURELOG_DIR}/tests/Inverter/dut.sv, line:7:1, endln:12:10 |vpiParent: \_design: (work@top) |vpiFullName:work@inverter @@ -162,21 +162,21 @@ design: (work@top) |vpiNet: \_logic_net: (work@inverter.a), line:8:13, endln:8:14 |vpiParent: - \_module: work@inverter (work@inverter), file:${SURELOG_DIR}/tests/Inverter/dut.sv, line:7:1, endln:12:10 + \_module_inst: work@inverter (work@inverter), file:${SURELOG_DIR}/tests/Inverter/dut.sv, line:7:1, endln:12:10 |vpiName:a |vpiFullName:work@inverter.a |vpiNetType:1 |vpiNet: \_logic_net: (work@inverter.b), line:9:14, endln:9:15 |vpiParent: - \_module: work@inverter (work@inverter), file:${SURELOG_DIR}/tests/Inverter/dut.sv, line:7:1, endln:12:10 + \_module_inst: work@inverter (work@inverter), file:${SURELOG_DIR}/tests/Inverter/dut.sv, line:7:1, endln:12:10 |vpiName:b |vpiFullName:work@inverter.b |vpiNetType:1 |vpiPort: \_port: (a), line:8:13, endln:8:14 |vpiParent: - \_module: work@inverter (work@inverter), file:${SURELOG_DIR}/tests/Inverter/dut.sv, line:7:1, endln:12:10 + \_module_inst: work@inverter (work@inverter), file:${SURELOG_DIR}/tests/Inverter/dut.sv, line:7:1, endln:12:10 |vpiName:a |vpiDirection:1 |vpiLowConn: @@ -188,7 +188,7 @@ design: (work@top) |vpiPort: \_port: (b), line:9:14, endln:9:15 |vpiParent: - \_module: work@inverter (work@inverter), file:${SURELOG_DIR}/tests/Inverter/dut.sv, line:7:1, endln:12:10 + \_module_inst: work@inverter (work@inverter), file:${SURELOG_DIR}/tests/Inverter/dut.sv, line:7:1, endln:12:10 |vpiName:b |vpiDirection:2 |vpiLowConn: @@ -200,7 +200,7 @@ design: (work@top) |vpiContAssign: \_cont_assign: , line:11:8, endln:11:12 |vpiParent: - \_module: work@inverter (work@inverter), file:${SURELOG_DIR}/tests/Inverter/dut.sv, line:7:1, endln:12:10 + \_module_inst: work@inverter (work@inverter), file:${SURELOG_DIR}/tests/Inverter/dut.sv, line:7:1, endln:12:10 |vpiRhs: \_operation: , line:11:10, endln:11:12 |vpiParent: @@ -223,7 +223,7 @@ design: (work@top) |vpiActual: \_logic_net: (work@top.i1.b), line:9:14, endln:9:15 |uhdmallModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/Inverter/dut.sv, line:1:1, endln:5:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/Inverter/dut.sv, line:1:1, endln:5:10 |vpiParent: \_design: (work@top) |vpiFullName:work@top @@ -231,21 +231,21 @@ design: (work@top) |vpiNet: \_logic_net: (work@top.a), line:1:23, endln:1:24 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/Inverter/dut.sv, line:1:1, endln:5:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/Inverter/dut.sv, line:1:1, endln:5:10 |vpiName:a |vpiFullName:work@top.a |vpiNetType:1 |vpiNet: \_logic_net: (work@top.b), line:2:14, endln:2:15 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/Inverter/dut.sv, line:1:1, endln:5:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/Inverter/dut.sv, line:1:1, endln:5:10 |vpiName:b |vpiFullName:work@top.b |vpiNetType:1 |vpiPort: \_port: (a), line:1:23, endln:1:24 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/Inverter/dut.sv, line:1:1, endln:5:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/Inverter/dut.sv, line:1:1, endln:5:10 |vpiName:a |vpiDirection:1 |vpiLowConn: @@ -257,7 +257,7 @@ design: (work@top) |vpiPort: \_port: (b), line:2:14, endln:2:15 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/Inverter/dut.sv, line:1:1, endln:5:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/Inverter/dut.sv, line:1:1, endln:5:10 |vpiName:b |vpiDirection:2 |vpiLowConn: @@ -267,14 +267,14 @@ design: (work@top) |vpiTypedef: \_logic_typespec: , line:2:9, endln:2:13 |uhdmtopModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/Inverter/dut.sv, line:1:1, endln:5:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/Inverter/dut.sv, line:1:1, endln:5:10 |vpiName:work@top |vpiDefName:work@top |vpiTop:1 |vpiNet: \_logic_net: (work@top.a), line:1:23, endln:1:24 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/Inverter/dut.sv, line:1:1, endln:5:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/Inverter/dut.sv, line:1:1, endln:5:10 |vpiTypespec: \_logic_typespec: , line:1:18, endln:1:22 |vpiName:a @@ -283,7 +283,7 @@ design: (work@top) |vpiNet: \_logic_net: (work@top.b), line:2:14, endln:2:15 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/Inverter/dut.sv, line:1:1, endln:5:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/Inverter/dut.sv, line:1:1, endln:5:10 |vpiTypespec: \_logic_typespec: , line:2:9, endln:2:13 |vpiName:b @@ -292,7 +292,7 @@ design: (work@top) |vpiNet: \_logic_net: (work@top.tmp), line:3:17, endln:3:20 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/Inverter/dut.sv, line:1:1, endln:5:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/Inverter/dut.sv, line:1:1, endln:5:10 |vpiName:tmp |vpiFullName:work@top.tmp |vpiNetType:1 @@ -300,7 +300,7 @@ design: (work@top) |vpiPort: \_port: (a), line:1:23, endln:1:24 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/Inverter/dut.sv, line:1:1, endln:5:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/Inverter/dut.sv, line:1:1, endln:5:10 |vpiName:a |vpiDirection:1 |vpiLowConn: @@ -314,11 +314,11 @@ design: (work@top) |vpiTypedef: \_logic_typespec: , line:1:18, endln:1:22 |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/Inverter/dut.sv, line:1:1, endln:5:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/Inverter/dut.sv, line:1:1, endln:5:10 |vpiPort: \_port: (b), line:2:14, endln:2:15 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/Inverter/dut.sv, line:1:1, endln:5:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/Inverter/dut.sv, line:1:1, endln:5:10 |vpiName:b |vpiDirection:2 |vpiLowConn: @@ -332,11 +332,11 @@ design: (work@top) |vpiTypedef: \_logic_typespec: , line:2:9, endln:2:13 |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/Inverter/dut.sv, line:1:1, endln:5:10 - |vpiModule: - \_module: work@inverter (work@top.i1), file:${SURELOG_DIR}/tests/Inverter/dut.sv, line:3:3, endln:3:22 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/Inverter/dut.sv, line:1:1, endln:5:10 + |vpiModuleInst: + \_module_inst: work@inverter (work@top.i1), file:${SURELOG_DIR}/tests/Inverter/dut.sv, line:3:3, endln:3:22 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/Inverter/dut.sv, line:1:1, endln:5:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/Inverter/dut.sv, line:1:1, endln:5:10 |vpiName:i1 |vpiFullName:work@top.i1 |vpiDefName:work@inverter @@ -345,7 +345,7 @@ design: (work@top) |vpiNet: \_logic_net: (work@top.i1.a), line:8:13, endln:8:14 |vpiParent: - \_module: work@inverter (work@top.i1), file:${SURELOG_DIR}/tests/Inverter/dut.sv, line:3:3, endln:3:22 + \_module_inst: work@inverter (work@top.i1), file:${SURELOG_DIR}/tests/Inverter/dut.sv, line:3:3, endln:3:22 |vpiTypespec: \_logic_typespec: , line:8:8, endln:8:12 |vpiName:a @@ -354,18 +354,18 @@ design: (work@top) |vpiNet: \_logic_net: (work@top.i1.b), line:9:14, endln:9:15 |vpiParent: - \_module: work@inverter (work@top.i1), file:${SURELOG_DIR}/tests/Inverter/dut.sv, line:3:3, endln:3:22 + \_module_inst: work@inverter (work@top.i1), file:${SURELOG_DIR}/tests/Inverter/dut.sv, line:3:3, endln:3:22 |vpiTypespec: \_logic_typespec: , line:9:9, endln:9:13 |vpiName:b |vpiFullName:work@top.i1.b |vpiNetType:1 |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/Inverter/dut.sv, line:1:1, endln:5:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/Inverter/dut.sv, line:1:1, endln:5:10 |vpiPort: \_port: (a), line:8:13, endln:8:14 |vpiParent: - \_module: work@inverter (work@top.i1), file:${SURELOG_DIR}/tests/Inverter/dut.sv, line:3:3, endln:3:22 + \_module_inst: work@inverter (work@top.i1), file:${SURELOG_DIR}/tests/Inverter/dut.sv, line:3:3, endln:3:22 |vpiName:a |vpiDirection:1 |vpiHighConn: @@ -387,11 +387,11 @@ design: (work@top) |vpiTypedef: \_logic_typespec: , line:8:8, endln:8:12 |vpiInstance: - \_module: work@inverter (work@top.i1), file:${SURELOG_DIR}/tests/Inverter/dut.sv, line:3:3, endln:3:22 + \_module_inst: work@inverter (work@top.i1), file:${SURELOG_DIR}/tests/Inverter/dut.sv, line:3:3, endln:3:22 |vpiPort: \_port: (b), line:9:14, endln:9:15 |vpiParent: - \_module: work@inverter (work@top.i1), file:${SURELOG_DIR}/tests/Inverter/dut.sv, line:3:3, endln:3:22 + \_module_inst: work@inverter (work@top.i1), file:${SURELOG_DIR}/tests/Inverter/dut.sv, line:3:3, endln:3:22 |vpiName:b |vpiDirection:2 |vpiHighConn: @@ -413,11 +413,11 @@ design: (work@top) |vpiTypedef: \_logic_typespec: , line:9:9, endln:9:13 |vpiInstance: - \_module: work@inverter (work@top.i1), file:${SURELOG_DIR}/tests/Inverter/dut.sv, line:3:3, endln:3:22 + \_module_inst: work@inverter (work@top.i1), file:${SURELOG_DIR}/tests/Inverter/dut.sv, line:3:3, endln:3:22 |vpiContAssign: \_cont_assign: , line:11:8, endln:11:12 |vpiParent: - \_module: work@inverter (work@top.i1), file:${SURELOG_DIR}/tests/Inverter/dut.sv, line:3:3, endln:3:22 + \_module_inst: work@inverter (work@top.i1), file:${SURELOG_DIR}/tests/Inverter/dut.sv, line:3:3, endln:3:22 |vpiRhs: \_operation: , line:11:10, endln:11:12 |vpiParent: @@ -439,10 +439,10 @@ design: (work@top) |vpiFullName:work@top.i1.b |vpiActual: \_logic_net: (work@top.i1.b), line:9:14, endln:9:15 - |vpiModule: - \_module: work@inverter (work@top.i2), file:${SURELOG_DIR}/tests/Inverter/dut.sv, line:4:3, endln:4:22 + |vpiModuleInst: + \_module_inst: work@inverter (work@top.i2), file:${SURELOG_DIR}/tests/Inverter/dut.sv, line:4:3, endln:4:22 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/Inverter/dut.sv, line:1:1, endln:5:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/Inverter/dut.sv, line:1:1, endln:5:10 |vpiName:i2 |vpiFullName:work@top.i2 |vpiDefName:work@inverter @@ -451,7 +451,7 @@ design: (work@top) |vpiNet: \_logic_net: (work@top.i2.a), line:8:13, endln:8:14 |vpiParent: - \_module: work@inverter (work@top.i2), file:${SURELOG_DIR}/tests/Inverter/dut.sv, line:4:3, endln:4:22 + \_module_inst: work@inverter (work@top.i2), file:${SURELOG_DIR}/tests/Inverter/dut.sv, line:4:3, endln:4:22 |vpiTypespec: \_logic_typespec: , line:8:8, endln:8:12 |vpiName:a @@ -460,18 +460,18 @@ design: (work@top) |vpiNet: \_logic_net: (work@top.i2.b), line:9:14, endln:9:15 |vpiParent: - \_module: work@inverter (work@top.i2), file:${SURELOG_DIR}/tests/Inverter/dut.sv, line:4:3, endln:4:22 + \_module_inst: work@inverter (work@top.i2), file:${SURELOG_DIR}/tests/Inverter/dut.sv, line:4:3, endln:4:22 |vpiTypespec: \_logic_typespec: , line:9:9, endln:9:13 |vpiName:b |vpiFullName:work@top.i2.b |vpiNetType:1 |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/Inverter/dut.sv, line:1:1, endln:5:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/Inverter/dut.sv, line:1:1, endln:5:10 |vpiPort: \_port: (a), line:8:13, endln:8:14 |vpiParent: - \_module: work@inverter (work@top.i2), file:${SURELOG_DIR}/tests/Inverter/dut.sv, line:4:3, endln:4:22 + \_module_inst: work@inverter (work@top.i2), file:${SURELOG_DIR}/tests/Inverter/dut.sv, line:4:3, endln:4:22 |vpiName:a |vpiDirection:1 |vpiHighConn: @@ -493,11 +493,11 @@ design: (work@top) |vpiTypedef: \_logic_typespec: , line:8:8, endln:8:12 |vpiInstance: - \_module: work@inverter (work@top.i2), file:${SURELOG_DIR}/tests/Inverter/dut.sv, line:4:3, endln:4:22 + \_module_inst: work@inverter (work@top.i2), file:${SURELOG_DIR}/tests/Inverter/dut.sv, line:4:3, endln:4:22 |vpiPort: \_port: (b), line:9:14, endln:9:15 |vpiParent: - \_module: work@inverter (work@top.i2), file:${SURELOG_DIR}/tests/Inverter/dut.sv, line:4:3, endln:4:22 + \_module_inst: work@inverter (work@top.i2), file:${SURELOG_DIR}/tests/Inverter/dut.sv, line:4:3, endln:4:22 |vpiName:b |vpiDirection:2 |vpiHighConn: @@ -519,11 +519,11 @@ design: (work@top) |vpiTypedef: \_logic_typespec: , line:9:9, endln:9:13 |vpiInstance: - \_module: work@inverter (work@top.i2), file:${SURELOG_DIR}/tests/Inverter/dut.sv, line:4:3, endln:4:22 + \_module_inst: work@inverter (work@top.i2), file:${SURELOG_DIR}/tests/Inverter/dut.sv, line:4:3, endln:4:22 |vpiContAssign: \_cont_assign: , line:11:8, endln:11:12 |vpiParent: - \_module: work@inverter (work@top.i2), file:${SURELOG_DIR}/tests/Inverter/dut.sv, line:4:3, endln:4:22 + \_module_inst: work@inverter (work@top.i2), file:${SURELOG_DIR}/tests/Inverter/dut.sv, line:4:3, endln:4:22 |vpiRhs: \_operation: , line:11:10, endln:11:12 |vpiParent: diff --git a/tests/JKFlipflop/JKFlipflop.log b/tests/JKFlipflop/JKFlipflop.log index 8d621ac7e9..d595bf5a8d 100644 --- a/tests/JKFlipflop/JKFlipflop.log +++ b/tests/JKFlipflop/JKFlipflop.log @@ -56,7 +56,7 @@ io_decl 11 logic_net 20 logic_typespec 18 logic_var 1 -module 4 +module_inst 4 operation 11 package 2 port 18 @@ -87,7 +87,7 @@ io_decl 22 logic_net 20 logic_typespec 18 logic_var 1 -module 4 +module_inst 4 operation 17 package 2 port 27 @@ -582,7 +582,7 @@ design: (work@JKFlipflop) \_int_typespec: |vpiSigned:1 |uhdmallModules: -\_module: work@D_Flipflop (work@D_Flipflop), file:${SURELOG_DIR}/tests/JKFlipflop/dut.sv, line:9:1, endln:19:10 +\_module_inst: work@D_Flipflop (work@D_Flipflop), file:${SURELOG_DIR}/tests/JKFlipflop/dut.sv, line:9:1, endln:19:10 |vpiParent: \_design: (work@JKFlipflop) |vpiFullName:work@D_Flipflop @@ -590,32 +590,32 @@ design: (work@JKFlipflop) |vpiNet: \_logic_net: (work@D_Flipflop.Din), line:9:19, endln:9:22 |vpiParent: - \_module: work@D_Flipflop (work@D_Flipflop), file:${SURELOG_DIR}/tests/JKFlipflop/dut.sv, line:9:1, endln:19:10 + \_module_inst: work@D_Flipflop (work@D_Flipflop), file:${SURELOG_DIR}/tests/JKFlipflop/dut.sv, line:9:1, endln:19:10 |vpiName:Din |vpiFullName:work@D_Flipflop.Din |vpiNet: \_logic_net: (work@D_Flipflop.clk), line:9:23, endln:9:26 |vpiParent: - \_module: work@D_Flipflop (work@D_Flipflop), file:${SURELOG_DIR}/tests/JKFlipflop/dut.sv, line:9:1, endln:19:10 + \_module_inst: work@D_Flipflop (work@D_Flipflop), file:${SURELOG_DIR}/tests/JKFlipflop/dut.sv, line:9:1, endln:19:10 |vpiName:clk |vpiFullName:work@D_Flipflop.clk |vpiNet: \_logic_net: (work@D_Flipflop.reset), line:9:27, endln:9:32 |vpiParent: - \_module: work@D_Flipflop (work@D_Flipflop), file:${SURELOG_DIR}/tests/JKFlipflop/dut.sv, line:9:1, endln:19:10 + \_module_inst: work@D_Flipflop (work@D_Flipflop), file:${SURELOG_DIR}/tests/JKFlipflop/dut.sv, line:9:1, endln:19:10 |vpiName:reset |vpiFullName:work@D_Flipflop.reset |vpiNet: \_logic_net: (work@D_Flipflop.q), line:9:33, endln:9:34 |vpiParent: - \_module: work@D_Flipflop (work@D_Flipflop), file:${SURELOG_DIR}/tests/JKFlipflop/dut.sv, line:9:1, endln:19:10 + \_module_inst: work@D_Flipflop (work@D_Flipflop), file:${SURELOG_DIR}/tests/JKFlipflop/dut.sv, line:9:1, endln:19:10 |vpiName:q |vpiFullName:work@D_Flipflop.q |vpiNetType:48 |vpiPort: \_port: (Din), line:9:19, endln:9:22 |vpiParent: - \_module: work@D_Flipflop (work@D_Flipflop), file:${SURELOG_DIR}/tests/JKFlipflop/dut.sv, line:9:1, endln:19:10 + \_module_inst: work@D_Flipflop (work@D_Flipflop), file:${SURELOG_DIR}/tests/JKFlipflop/dut.sv, line:9:1, endln:19:10 |vpiName:Din |vpiDirection:1 |vpiLowConn: @@ -627,7 +627,7 @@ design: (work@JKFlipflop) |vpiPort: \_port: (clk), line:9:23, endln:9:26 |vpiParent: - \_module: work@D_Flipflop (work@D_Flipflop), file:${SURELOG_DIR}/tests/JKFlipflop/dut.sv, line:9:1, endln:19:10 + \_module_inst: work@D_Flipflop (work@D_Flipflop), file:${SURELOG_DIR}/tests/JKFlipflop/dut.sv, line:9:1, endln:19:10 |vpiName:clk |vpiDirection:1 |vpiLowConn: @@ -639,7 +639,7 @@ design: (work@JKFlipflop) |vpiPort: \_port: (reset), line:9:27, endln:9:32 |vpiParent: - \_module: work@D_Flipflop (work@D_Flipflop), file:${SURELOG_DIR}/tests/JKFlipflop/dut.sv, line:9:1, endln:19:10 + \_module_inst: work@D_Flipflop (work@D_Flipflop), file:${SURELOG_DIR}/tests/JKFlipflop/dut.sv, line:9:1, endln:19:10 |vpiName:reset |vpiDirection:1 |vpiLowConn: @@ -651,7 +651,7 @@ design: (work@JKFlipflop) |vpiPort: \_port: (q), line:9:33, endln:9:34 |vpiParent: - \_module: work@D_Flipflop (work@D_Flipflop), file:${SURELOG_DIR}/tests/JKFlipflop/dut.sv, line:9:1, endln:19:10 + \_module_inst: work@D_Flipflop (work@D_Flipflop), file:${SURELOG_DIR}/tests/JKFlipflop/dut.sv, line:9:1, endln:19:10 |vpiName:q |vpiDirection:2 |vpiLowConn: @@ -663,7 +663,7 @@ design: (work@JKFlipflop) |vpiProcess: \_always: , line:12:5, endln:18:8 |vpiParent: - \_module: work@D_Flipflop (work@D_Flipflop), file:${SURELOG_DIR}/tests/JKFlipflop/dut.sv, line:9:1, endln:19:10 + \_module_inst: work@D_Flipflop (work@D_Flipflop), file:${SURELOG_DIR}/tests/JKFlipflop/dut.sv, line:9:1, endln:19:10 |vpiStmt: \_event_control: , line:12:11, endln:12:25 |vpiParent: @@ -744,7 +744,7 @@ design: (work@JKFlipflop) \_logic_net: (work@JKFlipflop.dff.q), line:9:33, endln:9:34 |vpiAlwaysType:1 |uhdmallModules: -\_module: work@JKFlipflop (work@JKFlipflop), file:${SURELOG_DIR}/tests/JKFlipflop/dut.sv, line:1:1, endln:7:10 +\_module_inst: work@JKFlipflop (work@JKFlipflop), file:${SURELOG_DIR}/tests/JKFlipflop/dut.sv, line:1:1, endln:7:10 |vpiParent: \_design: (work@JKFlipflop) |vpiFullName:work@JKFlipflop @@ -752,44 +752,44 @@ design: (work@JKFlipflop) |vpiNet: \_logic_net: (work@JKFlipflop.w), line:4:8, endln:4:9 |vpiParent: - \_module: work@JKFlipflop (work@JKFlipflop), file:${SURELOG_DIR}/tests/JKFlipflop/dut.sv, line:1:1, endln:7:10 + \_module_inst: work@JKFlipflop (work@JKFlipflop), file:${SURELOG_DIR}/tests/JKFlipflop/dut.sv, line:1:1, endln:7:10 |vpiName:w |vpiFullName:work@JKFlipflop.w |vpiNetType:1 |vpiNet: \_logic_net: (work@JKFlipflop.J), line:1:19, endln:1:20 |vpiParent: - \_module: work@JKFlipflop (work@JKFlipflop), file:${SURELOG_DIR}/tests/JKFlipflop/dut.sv, line:1:1, endln:7:10 + \_module_inst: work@JKFlipflop (work@JKFlipflop), file:${SURELOG_DIR}/tests/JKFlipflop/dut.sv, line:1:1, endln:7:10 |vpiName:J |vpiFullName:work@JKFlipflop.J |vpiNet: \_logic_net: (work@JKFlipflop.K), line:1:21, endln:1:22 |vpiParent: - \_module: work@JKFlipflop (work@JKFlipflop), file:${SURELOG_DIR}/tests/JKFlipflop/dut.sv, line:1:1, endln:7:10 + \_module_inst: work@JKFlipflop (work@JKFlipflop), file:${SURELOG_DIR}/tests/JKFlipflop/dut.sv, line:1:1, endln:7:10 |vpiName:K |vpiFullName:work@JKFlipflop.K |vpiNet: \_logic_net: (work@JKFlipflop.clk), line:1:23, endln:1:26 |vpiParent: - \_module: work@JKFlipflop (work@JKFlipflop), file:${SURELOG_DIR}/tests/JKFlipflop/dut.sv, line:1:1, endln:7:10 + \_module_inst: work@JKFlipflop (work@JKFlipflop), file:${SURELOG_DIR}/tests/JKFlipflop/dut.sv, line:1:1, endln:7:10 |vpiName:clk |vpiFullName:work@JKFlipflop.clk |vpiNet: \_logic_net: (work@JKFlipflop.reset), line:1:27, endln:1:32 |vpiParent: - \_module: work@JKFlipflop (work@JKFlipflop), file:${SURELOG_DIR}/tests/JKFlipflop/dut.sv, line:1:1, endln:7:10 + \_module_inst: work@JKFlipflop (work@JKFlipflop), file:${SURELOG_DIR}/tests/JKFlipflop/dut.sv, line:1:1, endln:7:10 |vpiName:reset |vpiFullName:work@JKFlipflop.reset |vpiNet: \_logic_net: (work@JKFlipflop.q), line:1:33, endln:1:34 |vpiParent: - \_module: work@JKFlipflop (work@JKFlipflop), file:${SURELOG_DIR}/tests/JKFlipflop/dut.sv, line:1:1, endln:7:10 + \_module_inst: work@JKFlipflop (work@JKFlipflop), file:${SURELOG_DIR}/tests/JKFlipflop/dut.sv, line:1:1, endln:7:10 |vpiName:q |vpiFullName:work@JKFlipflop.q |vpiPort: \_port: (J), line:1:19, endln:1:20 |vpiParent: - \_module: work@JKFlipflop (work@JKFlipflop), file:${SURELOG_DIR}/tests/JKFlipflop/dut.sv, line:1:1, endln:7:10 + \_module_inst: work@JKFlipflop (work@JKFlipflop), file:${SURELOG_DIR}/tests/JKFlipflop/dut.sv, line:1:1, endln:7:10 |vpiName:J |vpiDirection:1 |vpiLowConn: @@ -801,7 +801,7 @@ design: (work@JKFlipflop) |vpiPort: \_port: (K), line:1:21, endln:1:22 |vpiParent: - \_module: work@JKFlipflop (work@JKFlipflop), file:${SURELOG_DIR}/tests/JKFlipflop/dut.sv, line:1:1, endln:7:10 + \_module_inst: work@JKFlipflop (work@JKFlipflop), file:${SURELOG_DIR}/tests/JKFlipflop/dut.sv, line:1:1, endln:7:10 |vpiName:K |vpiDirection:1 |vpiLowConn: @@ -813,7 +813,7 @@ design: (work@JKFlipflop) |vpiPort: \_port: (clk), line:1:23, endln:1:26 |vpiParent: - \_module: work@JKFlipflop (work@JKFlipflop), file:${SURELOG_DIR}/tests/JKFlipflop/dut.sv, line:1:1, endln:7:10 + \_module_inst: work@JKFlipflop (work@JKFlipflop), file:${SURELOG_DIR}/tests/JKFlipflop/dut.sv, line:1:1, endln:7:10 |vpiName:clk |vpiDirection:1 |vpiLowConn: @@ -825,7 +825,7 @@ design: (work@JKFlipflop) |vpiPort: \_port: (reset), line:1:27, endln:1:32 |vpiParent: - \_module: work@JKFlipflop (work@JKFlipflop), file:${SURELOG_DIR}/tests/JKFlipflop/dut.sv, line:1:1, endln:7:10 + \_module_inst: work@JKFlipflop (work@JKFlipflop), file:${SURELOG_DIR}/tests/JKFlipflop/dut.sv, line:1:1, endln:7:10 |vpiName:reset |vpiDirection:1 |vpiLowConn: @@ -837,7 +837,7 @@ design: (work@JKFlipflop) |vpiPort: \_port: (q), line:1:33, endln:1:34 |vpiParent: - \_module: work@JKFlipflop (work@JKFlipflop), file:${SURELOG_DIR}/tests/JKFlipflop/dut.sv, line:1:1, endln:7:10 + \_module_inst: work@JKFlipflop (work@JKFlipflop), file:${SURELOG_DIR}/tests/JKFlipflop/dut.sv, line:1:1, endln:7:10 |vpiName:q |vpiDirection:2 |vpiLowConn: @@ -849,7 +849,7 @@ design: (work@JKFlipflop) |vpiContAssign: \_cont_assign: , line:5:10, endln:5:25 |vpiParent: - \_module: work@JKFlipflop (work@JKFlipflop), file:${SURELOG_DIR}/tests/JKFlipflop/dut.sv, line:1:1, endln:7:10 + \_module_inst: work@JKFlipflop (work@JKFlipflop), file:${SURELOG_DIR}/tests/JKFlipflop/dut.sv, line:1:1, endln:7:10 |vpiRhs: \_operation: , line:5:12, endln:5:25 |vpiParent: @@ -916,14 +916,14 @@ design: (work@JKFlipflop) |vpiActual: \_logic_net: (work@JKFlipflop.w), line:4:8, endln:4:9 |uhdmtopModules: -\_module: work@JKFlipflop (work@JKFlipflop), file:${SURELOG_DIR}/tests/JKFlipflop/dut.sv, line:1:1, endln:7:10 +\_module_inst: work@JKFlipflop (work@JKFlipflop), file:${SURELOG_DIR}/tests/JKFlipflop/dut.sv, line:1:1, endln:7:10 |vpiName:work@JKFlipflop |vpiDefName:work@JKFlipflop |vpiTop:1 |vpiNet: \_logic_net: (work@JKFlipflop.w), line:4:8, endln:4:9 |vpiParent: - \_module: work@JKFlipflop (work@JKFlipflop), file:${SURELOG_DIR}/tests/JKFlipflop/dut.sv, line:1:1, endln:7:10 + \_module_inst: work@JKFlipflop (work@JKFlipflop), file:${SURELOG_DIR}/tests/JKFlipflop/dut.sv, line:1:1, endln:7:10 |vpiTypespec: \_logic_typespec: , line:4:3, endln:4:7 |vpiName:w @@ -932,7 +932,7 @@ design: (work@JKFlipflop) |vpiNet: \_logic_net: (work@JKFlipflop.J), line:1:19, endln:1:20 |vpiParent: - \_module: work@JKFlipflop (work@JKFlipflop), file:${SURELOG_DIR}/tests/JKFlipflop/dut.sv, line:1:1, endln:7:10 + \_module_inst: work@JKFlipflop (work@JKFlipflop), file:${SURELOG_DIR}/tests/JKFlipflop/dut.sv, line:1:1, endln:7:10 |vpiTypespec: \_logic_typespec: , line:2:9, endln:2:9 |vpiName:J @@ -940,7 +940,7 @@ design: (work@JKFlipflop) |vpiNet: \_logic_net: (work@JKFlipflop.K), line:1:21, endln:1:22 |vpiParent: - \_module: work@JKFlipflop (work@JKFlipflop), file:${SURELOG_DIR}/tests/JKFlipflop/dut.sv, line:1:1, endln:7:10 + \_module_inst: work@JKFlipflop (work@JKFlipflop), file:${SURELOG_DIR}/tests/JKFlipflop/dut.sv, line:1:1, endln:7:10 |vpiTypespec: \_logic_typespec: , line:2:9, endln:2:9 |vpiName:K @@ -948,7 +948,7 @@ design: (work@JKFlipflop) |vpiNet: \_logic_net: (work@JKFlipflop.clk), line:1:23, endln:1:26 |vpiParent: - \_module: work@JKFlipflop (work@JKFlipflop), file:${SURELOG_DIR}/tests/JKFlipflop/dut.sv, line:1:1, endln:7:10 + \_module_inst: work@JKFlipflop (work@JKFlipflop), file:${SURELOG_DIR}/tests/JKFlipflop/dut.sv, line:1:1, endln:7:10 |vpiTypespec: \_logic_typespec: , line:2:9, endln:2:9 |vpiName:clk @@ -956,7 +956,7 @@ design: (work@JKFlipflop) |vpiNet: \_logic_net: (work@JKFlipflop.reset), line:1:27, endln:1:32 |vpiParent: - \_module: work@JKFlipflop (work@JKFlipflop), file:${SURELOG_DIR}/tests/JKFlipflop/dut.sv, line:1:1, endln:7:10 + \_module_inst: work@JKFlipflop (work@JKFlipflop), file:${SURELOG_DIR}/tests/JKFlipflop/dut.sv, line:1:1, endln:7:10 |vpiTypespec: \_logic_typespec: , line:2:9, endln:2:9 |vpiName:reset @@ -964,7 +964,7 @@ design: (work@JKFlipflop) |vpiNet: \_logic_net: (work@JKFlipflop.q), line:1:33, endln:1:34 |vpiParent: - \_module: work@JKFlipflop (work@JKFlipflop), file:${SURELOG_DIR}/tests/JKFlipflop/dut.sv, line:1:1, endln:7:10 + \_module_inst: work@JKFlipflop (work@JKFlipflop), file:${SURELOG_DIR}/tests/JKFlipflop/dut.sv, line:1:1, endln:7:10 |vpiTypespec: \_logic_typespec: , line:3:10, endln:3:10 |vpiName:q @@ -973,7 +973,7 @@ design: (work@JKFlipflop) |vpiPort: \_port: (J), line:1:19, endln:1:20 |vpiParent: - \_module: work@JKFlipflop (work@JKFlipflop), file:${SURELOG_DIR}/tests/JKFlipflop/dut.sv, line:1:1, endln:7:10 + \_module_inst: work@JKFlipflop (work@JKFlipflop), file:${SURELOG_DIR}/tests/JKFlipflop/dut.sv, line:1:1, endln:7:10 |vpiName:J |vpiDirection:1 |vpiLowConn: @@ -987,11 +987,11 @@ design: (work@JKFlipflop) |vpiTypedef: \_logic_typespec: , line:2:9, endln:2:9 |vpiInstance: - \_module: work@JKFlipflop (work@JKFlipflop), file:${SURELOG_DIR}/tests/JKFlipflop/dut.sv, line:1:1, endln:7:10 + \_module_inst: work@JKFlipflop (work@JKFlipflop), file:${SURELOG_DIR}/tests/JKFlipflop/dut.sv, line:1:1, endln:7:10 |vpiPort: \_port: (K), line:1:21, endln:1:22 |vpiParent: - \_module: work@JKFlipflop (work@JKFlipflop), file:${SURELOG_DIR}/tests/JKFlipflop/dut.sv, line:1:1, endln:7:10 + \_module_inst: work@JKFlipflop (work@JKFlipflop), file:${SURELOG_DIR}/tests/JKFlipflop/dut.sv, line:1:1, endln:7:10 |vpiName:K |vpiDirection:1 |vpiLowConn: @@ -1005,11 +1005,11 @@ design: (work@JKFlipflop) |vpiTypedef: \_logic_typespec: , line:2:9, endln:2:9 |vpiInstance: - \_module: work@JKFlipflop (work@JKFlipflop), file:${SURELOG_DIR}/tests/JKFlipflop/dut.sv, line:1:1, endln:7:10 + \_module_inst: work@JKFlipflop (work@JKFlipflop), file:${SURELOG_DIR}/tests/JKFlipflop/dut.sv, line:1:1, endln:7:10 |vpiPort: \_port: (clk), line:1:23, endln:1:26 |vpiParent: - \_module: work@JKFlipflop (work@JKFlipflop), file:${SURELOG_DIR}/tests/JKFlipflop/dut.sv, line:1:1, endln:7:10 + \_module_inst: work@JKFlipflop (work@JKFlipflop), file:${SURELOG_DIR}/tests/JKFlipflop/dut.sv, line:1:1, endln:7:10 |vpiName:clk |vpiDirection:1 |vpiLowConn: @@ -1023,11 +1023,11 @@ design: (work@JKFlipflop) |vpiTypedef: \_logic_typespec: , line:2:9, endln:2:9 |vpiInstance: - \_module: work@JKFlipflop (work@JKFlipflop), file:${SURELOG_DIR}/tests/JKFlipflop/dut.sv, line:1:1, endln:7:10 + \_module_inst: work@JKFlipflop (work@JKFlipflop), file:${SURELOG_DIR}/tests/JKFlipflop/dut.sv, line:1:1, endln:7:10 |vpiPort: \_port: (reset), line:1:27, endln:1:32 |vpiParent: - \_module: work@JKFlipflop (work@JKFlipflop), file:${SURELOG_DIR}/tests/JKFlipflop/dut.sv, line:1:1, endln:7:10 + \_module_inst: work@JKFlipflop (work@JKFlipflop), file:${SURELOG_DIR}/tests/JKFlipflop/dut.sv, line:1:1, endln:7:10 |vpiName:reset |vpiDirection:1 |vpiLowConn: @@ -1041,11 +1041,11 @@ design: (work@JKFlipflop) |vpiTypedef: \_logic_typespec: , line:2:9, endln:2:9 |vpiInstance: - \_module: work@JKFlipflop (work@JKFlipflop), file:${SURELOG_DIR}/tests/JKFlipflop/dut.sv, line:1:1, endln:7:10 + \_module_inst: work@JKFlipflop (work@JKFlipflop), file:${SURELOG_DIR}/tests/JKFlipflop/dut.sv, line:1:1, endln:7:10 |vpiPort: \_port: (q), line:1:33, endln:1:34 |vpiParent: - \_module: work@JKFlipflop (work@JKFlipflop), file:${SURELOG_DIR}/tests/JKFlipflop/dut.sv, line:1:1, endln:7:10 + \_module_inst: work@JKFlipflop (work@JKFlipflop), file:${SURELOG_DIR}/tests/JKFlipflop/dut.sv, line:1:1, endln:7:10 |vpiName:q |vpiDirection:2 |vpiLowConn: @@ -1059,11 +1059,11 @@ design: (work@JKFlipflop) |vpiTypedef: \_logic_typespec: , line:3:10, endln:3:10 |vpiInstance: - \_module: work@JKFlipflop (work@JKFlipflop), file:${SURELOG_DIR}/tests/JKFlipflop/dut.sv, line:1:1, endln:7:10 - |vpiModule: - \_module: work@D_Flipflop (work@JKFlipflop.dff), file:${SURELOG_DIR}/tests/JKFlipflop/dut.sv, line:6:3, endln:6:33 + \_module_inst: work@JKFlipflop (work@JKFlipflop), file:${SURELOG_DIR}/tests/JKFlipflop/dut.sv, line:1:1, endln:7:10 + |vpiModuleInst: + \_module_inst: work@D_Flipflop (work@JKFlipflop.dff), file:${SURELOG_DIR}/tests/JKFlipflop/dut.sv, line:6:3, endln:6:33 |vpiParent: - \_module: work@JKFlipflop (work@JKFlipflop), file:${SURELOG_DIR}/tests/JKFlipflop/dut.sv, line:1:1, endln:7:10 + \_module_inst: work@JKFlipflop (work@JKFlipflop), file:${SURELOG_DIR}/tests/JKFlipflop/dut.sv, line:1:1, endln:7:10 |vpiName:dff |vpiFullName:work@JKFlipflop.dff |vpiDefName:work@D_Flipflop @@ -1072,7 +1072,7 @@ design: (work@JKFlipflop) |vpiNet: \_logic_net: (work@JKFlipflop.dff.Din), line:9:19, endln:9:22 |vpiParent: - \_module: work@D_Flipflop (work@JKFlipflop.dff), file:${SURELOG_DIR}/tests/JKFlipflop/dut.sv, line:6:3, endln:6:33 + \_module_inst: work@D_Flipflop (work@JKFlipflop.dff), file:${SURELOG_DIR}/tests/JKFlipflop/dut.sv, line:6:3, endln:6:33 |vpiTypespec: \_logic_typespec: , line:10:11, endln:10:11 |vpiName:Din @@ -1080,7 +1080,7 @@ design: (work@JKFlipflop) |vpiNet: \_logic_net: (work@JKFlipflop.dff.clk), line:9:23, endln:9:26 |vpiParent: - \_module: work@D_Flipflop (work@JKFlipflop.dff), file:${SURELOG_DIR}/tests/JKFlipflop/dut.sv, line:6:3, endln:6:33 + \_module_inst: work@D_Flipflop (work@JKFlipflop.dff), file:${SURELOG_DIR}/tests/JKFlipflop/dut.sv, line:6:3, endln:6:33 |vpiTypespec: \_logic_typespec: , line:10:11, endln:10:11 |vpiName:clk @@ -1088,7 +1088,7 @@ design: (work@JKFlipflop) |vpiNet: \_logic_net: (work@JKFlipflop.dff.reset), line:9:27, endln:9:32 |vpiParent: - \_module: work@D_Flipflop (work@JKFlipflop.dff), file:${SURELOG_DIR}/tests/JKFlipflop/dut.sv, line:6:3, endln:6:33 + \_module_inst: work@D_Flipflop (work@JKFlipflop.dff), file:${SURELOG_DIR}/tests/JKFlipflop/dut.sv, line:6:3, endln:6:33 |vpiTypespec: \_logic_typespec: , line:10:11, endln:10:11 |vpiName:reset @@ -1096,18 +1096,18 @@ design: (work@JKFlipflop) |vpiNet: \_logic_net: (work@JKFlipflop.dff.q), line:9:33, endln:9:34 |vpiParent: - \_module: work@D_Flipflop (work@JKFlipflop.dff), file:${SURELOG_DIR}/tests/JKFlipflop/dut.sv, line:6:3, endln:6:33 + \_module_inst: work@D_Flipflop (work@JKFlipflop.dff), file:${SURELOG_DIR}/tests/JKFlipflop/dut.sv, line:6:3, endln:6:33 |vpiTypespec: \_logic_typespec: , line:11:12, endln:11:15 |vpiName:q |vpiFullName:work@JKFlipflop.dff.q |vpiNetType:48 |vpiInstance: - \_module: work@JKFlipflop (work@JKFlipflop), file:${SURELOG_DIR}/tests/JKFlipflop/dut.sv, line:1:1, endln:7:10 + \_module_inst: work@JKFlipflop (work@JKFlipflop), file:${SURELOG_DIR}/tests/JKFlipflop/dut.sv, line:1:1, endln:7:10 |vpiPort: \_port: (Din), line:9:19, endln:9:22 |vpiParent: - \_module: work@D_Flipflop (work@JKFlipflop.dff), file:${SURELOG_DIR}/tests/JKFlipflop/dut.sv, line:6:3, endln:6:33 + \_module_inst: work@D_Flipflop (work@JKFlipflop.dff), file:${SURELOG_DIR}/tests/JKFlipflop/dut.sv, line:6:3, endln:6:33 |vpiName:Din |vpiDirection:1 |vpiHighConn: @@ -1129,11 +1129,11 @@ design: (work@JKFlipflop) |vpiTypedef: \_logic_typespec: , line:10:11, endln:10:11 |vpiInstance: - \_module: work@D_Flipflop (work@JKFlipflop.dff), file:${SURELOG_DIR}/tests/JKFlipflop/dut.sv, line:6:3, endln:6:33 + \_module_inst: work@D_Flipflop (work@JKFlipflop.dff), file:${SURELOG_DIR}/tests/JKFlipflop/dut.sv, line:6:3, endln:6:33 |vpiPort: \_port: (clk), line:9:23, endln:9:26 |vpiParent: - \_module: work@D_Flipflop (work@JKFlipflop.dff), file:${SURELOG_DIR}/tests/JKFlipflop/dut.sv, line:6:3, endln:6:33 + \_module_inst: work@D_Flipflop (work@JKFlipflop.dff), file:${SURELOG_DIR}/tests/JKFlipflop/dut.sv, line:6:3, endln:6:33 |vpiName:clk |vpiDirection:1 |vpiHighConn: @@ -1155,11 +1155,11 @@ design: (work@JKFlipflop) |vpiTypedef: \_logic_typespec: , line:10:11, endln:10:11 |vpiInstance: - \_module: work@D_Flipflop (work@JKFlipflop.dff), file:${SURELOG_DIR}/tests/JKFlipflop/dut.sv, line:6:3, endln:6:33 + \_module_inst: work@D_Flipflop (work@JKFlipflop.dff), file:${SURELOG_DIR}/tests/JKFlipflop/dut.sv, line:6:3, endln:6:33 |vpiPort: \_port: (reset), line:9:27, endln:9:32 |vpiParent: - \_module: work@D_Flipflop (work@JKFlipflop.dff), file:${SURELOG_DIR}/tests/JKFlipflop/dut.sv, line:6:3, endln:6:33 + \_module_inst: work@D_Flipflop (work@JKFlipflop.dff), file:${SURELOG_DIR}/tests/JKFlipflop/dut.sv, line:6:3, endln:6:33 |vpiName:reset |vpiDirection:1 |vpiHighConn: @@ -1181,11 +1181,11 @@ design: (work@JKFlipflop) |vpiTypedef: \_logic_typespec: , line:10:11, endln:10:11 |vpiInstance: - \_module: work@D_Flipflop (work@JKFlipflop.dff), file:${SURELOG_DIR}/tests/JKFlipflop/dut.sv, line:6:3, endln:6:33 + \_module_inst: work@D_Flipflop (work@JKFlipflop.dff), file:${SURELOG_DIR}/tests/JKFlipflop/dut.sv, line:6:3, endln:6:33 |vpiPort: \_port: (q), line:9:33, endln:9:34 |vpiParent: - \_module: work@D_Flipflop (work@JKFlipflop.dff), file:${SURELOG_DIR}/tests/JKFlipflop/dut.sv, line:6:3, endln:6:33 + \_module_inst: work@D_Flipflop (work@JKFlipflop.dff), file:${SURELOG_DIR}/tests/JKFlipflop/dut.sv, line:6:3, endln:6:33 |vpiName:q |vpiDirection:2 |vpiHighConn: @@ -1207,11 +1207,11 @@ design: (work@JKFlipflop) |vpiTypedef: \_logic_typespec: , line:11:12, endln:11:15 |vpiInstance: - \_module: work@D_Flipflop (work@JKFlipflop.dff), file:${SURELOG_DIR}/tests/JKFlipflop/dut.sv, line:6:3, endln:6:33 + \_module_inst: work@D_Flipflop (work@JKFlipflop.dff), file:${SURELOG_DIR}/tests/JKFlipflop/dut.sv, line:6:3, endln:6:33 |vpiProcess: \_always: , line:12:5, endln:18:8 |vpiParent: - \_module: work@D_Flipflop (work@JKFlipflop.dff), file:${SURELOG_DIR}/tests/JKFlipflop/dut.sv, line:6:3, endln:6:33 + \_module_inst: work@D_Flipflop (work@JKFlipflop.dff), file:${SURELOG_DIR}/tests/JKFlipflop/dut.sv, line:6:3, endln:6:33 |vpiStmt: \_event_control: , line:12:11, endln:12:25 |vpiParent: @@ -1288,7 +1288,7 @@ design: (work@JKFlipflop) |vpiContAssign: \_cont_assign: , line:5:10, endln:5:25 |vpiParent: - \_module: work@JKFlipflop (work@JKFlipflop), file:${SURELOG_DIR}/tests/JKFlipflop/dut.sv, line:1:1, endln:7:10 + \_module_inst: work@JKFlipflop (work@JKFlipflop), file:${SURELOG_DIR}/tests/JKFlipflop/dut.sv, line:1:1, endln:7:10 |vpiRhs: \_operation: , line:5:12, endln:5:25 |vpiParent: diff --git a/tests/LargeConst/LargeConst.log b/tests/LargeConst/LargeConst.log index 5cb5259d0d..9c3bf31b65 100644 --- a/tests/LargeConst/LargeConst.log +++ b/tests/LargeConst/LargeConst.log @@ -121,7 +121,7 @@ cont_assign 10 design 1 int_typespec 2 logic_net 5 -module 3 +module_inst 3 operation 2 ref_obj 10 === UHDM Object Stats End === @@ -133,7 +133,7 @@ cont_assign 15 design 1 int_typespec 3 logic_net 5 -module 3 +module_inst 3 operation 3 ref_obj 15 === UHDM Object Stats End === @@ -150,7 +150,7 @@ design: (work@dut) |vpiElaborated:1 |vpiName:work@dut |uhdmallModules: -\_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/LargeConst/dut.sv, line:1:1, endln:8:10 +\_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/LargeConst/dut.sv, line:1:1, endln:8:10 |vpiParent: \_design: (work@dut) |vpiFullName:work@dut @@ -158,7 +158,7 @@ design: (work@dut) |vpiContAssign: \_cont_assign: , line:2:11, endln:2:39 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/LargeConst/dut.sv, line:1:1, endln:8:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/LargeConst/dut.sv, line:1:1, endln:8:10 |vpiRhs: \_constant: , line:2:18, endln:2:39 |vpiParent: @@ -178,7 +178,7 @@ design: (work@dut) |vpiContAssign: \_cont_assign: , line:3:11, endln:3:39 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/LargeConst/dut.sv, line:1:1, endln:8:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/LargeConst/dut.sv, line:1:1, endln:8:10 |vpiRhs: \_constant: , line:3:15, endln:3:39 |vpiParent: @@ -201,7 +201,7 @@ design: (work@dut) |vpiContAssign: \_cont_assign: , line:4:11, endln:4:39 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/LargeConst/dut.sv, line:1:1, endln:8:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/LargeConst/dut.sv, line:1:1, endln:8:10 |vpiRhs: \_constant: , line:4:19, endln:4:39 |vpiParent: @@ -221,7 +221,7 @@ design: (work@dut) |vpiContAssign: \_cont_assign: , line:5:11, endln:5:39 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/LargeConst/dut.sv, line:1:1, endln:8:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/LargeConst/dut.sv, line:1:1, endln:8:10 |vpiRhs: \_constant: , line:5:19, endln:5:39 |vpiParent: @@ -241,7 +241,7 @@ design: (work@dut) |vpiContAssign: \_cont_assign: , line:6:11, endln:6:39 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/LargeConst/dut.sv, line:1:1, endln:8:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/LargeConst/dut.sv, line:1:1, endln:8:10 |vpiRhs: \_operation: , line:6:18, endln:6:39 |vpiParent: @@ -262,7 +262,7 @@ design: (work@dut) |vpiActual: \_logic_net: (e) |uhdmtopModules: -\_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/LargeConst/dut.sv, line:1:1, endln:8:10 +\_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/LargeConst/dut.sv, line:1:1, endln:8:10 |vpiName:work@dut |vpiDefName:work@dut |vpiTop:1 @@ -290,7 +290,7 @@ design: (work@dut) |vpiContAssign: \_cont_assign: , line:2:11, endln:2:39 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/LargeConst/dut.sv, line:1:1, endln:8:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/LargeConst/dut.sv, line:1:1, endln:8:10 |vpiRhs: \_constant: , line:2:18, endln:2:39 |vpiParent: @@ -310,7 +310,7 @@ design: (work@dut) |vpiContAssign: \_cont_assign: , line:3:11, endln:3:39 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/LargeConst/dut.sv, line:1:1, endln:8:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/LargeConst/dut.sv, line:1:1, endln:8:10 |vpiRhs: \_constant: , line:3:15, endln:3:39 |vpiParent: @@ -335,7 +335,7 @@ design: (work@dut) |vpiContAssign: \_cont_assign: , line:4:11, endln:4:39 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/LargeConst/dut.sv, line:1:1, endln:8:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/LargeConst/dut.sv, line:1:1, endln:8:10 |vpiRhs: \_constant: , line:4:19, endln:4:39 |vpiLhs: @@ -349,7 +349,7 @@ design: (work@dut) |vpiContAssign: \_cont_assign: , line:5:11, endln:5:39 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/LargeConst/dut.sv, line:1:1, endln:8:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/LargeConst/dut.sv, line:1:1, endln:8:10 |vpiRhs: \_constant: , line:5:19, endln:5:39 |vpiParent: @@ -369,7 +369,7 @@ design: (work@dut) |vpiContAssign: \_cont_assign: , line:6:11, endln:6:39 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/LargeConst/dut.sv, line:1:1, endln:8:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/LargeConst/dut.sv, line:1:1, endln:8:10 |vpiRhs: \_operation: , line:6:18, endln:6:39 |vpiParent: diff --git a/tests/LargeHex/LargeHex.log b/tests/LargeHex/LargeHex.log index 07db0737ad..c8e3c46ca7 100644 --- a/tests/LargeHex/LargeHex.log +++ b/tests/LargeHex/LargeHex.log @@ -555,7 +555,7 @@ io_decl 11 logic_net 3 logic_typespec 6 logic_var 4 -module 9 +module_inst 9 operation 8 package 2 param_assign 8 @@ -584,7 +584,7 @@ io_decl 22 logic_net 3 logic_typespec 6 logic_var 4 -module 9 +module_inst 9 operation 8 package 2 param_assign 8 @@ -1081,14 +1081,14 @@ design: (work@tlul_socket_1n) \_int_typespec: |vpiSigned:1 |uhdmallModules: -\_module: work@tlul_fifo_sync (work@tlul_fifo_sync), file:${SURELOG_DIR}/tests/LargeHex/dut.sv, line:1:1, endln:3:10 +\_module_inst: work@tlul_fifo_sync (work@tlul_fifo_sync), file:${SURELOG_DIR}/tests/LargeHex/dut.sv, line:1:1, endln:3:10 |vpiParent: \_design: (work@tlul_socket_1n) |vpiFullName:work@tlul_fifo_sync |vpiParameter: \_parameter: (work@tlul_fifo_sync.ReqDepth), line:1:48, endln:1:56 |vpiParent: - \_module: work@tlul_fifo_sync (work@tlul_fifo_sync), file:${SURELOG_DIR}/tests/LargeHex/dut.sv, line:1:1, endln:3:10 + \_module_inst: work@tlul_fifo_sync (work@tlul_fifo_sync), file:${SURELOG_DIR}/tests/LargeHex/dut.sv, line:1:1, endln:3:10 |UINT:2 |vpiTypespec: \_int_typespec: , line:1:35, endln:1:47 @@ -1099,7 +1099,7 @@ design: (work@tlul_socket_1n) |vpiParamAssign: \_param_assign: , line:1:48, endln:1:60 |vpiParent: - \_module: work@tlul_fifo_sync (work@tlul_fifo_sync), file:${SURELOG_DIR}/tests/LargeHex/dut.sv, line:1:1, endln:3:10 + \_module_inst: work@tlul_fifo_sync (work@tlul_fifo_sync), file:${SURELOG_DIR}/tests/LargeHex/dut.sv, line:1:1, endln:3:10 |vpiRhs: \_constant: , line:1:59, endln:1:60 |vpiDecompile:2 @@ -1114,19 +1114,19 @@ design: (work@tlul_socket_1n) |vpiNet: \_logic_net: (work@tlul_fifo_sync.storage), line:2:25, endln:2:32 |vpiParent: - \_module: work@tlul_fifo_sync (work@tlul_fifo_sync), file:${SURELOG_DIR}/tests/LargeHex/dut.sv, line:1:1, endln:3:10 + \_module_inst: work@tlul_fifo_sync (work@tlul_fifo_sync), file:${SURELOG_DIR}/tests/LargeHex/dut.sv, line:1:1, endln:3:10 |vpiName:storage |vpiFullName:work@tlul_fifo_sync.storage |vpiNetType:36 |uhdmallModules: -\_module: work@tlul_socket_1n (work@tlul_socket_1n), file:${SURELOG_DIR}/tests/LargeHex/dut.sv, line:6:1, endln:18:10 +\_module_inst: work@tlul_socket_1n (work@tlul_socket_1n), file:${SURELOG_DIR}/tests/LargeHex/dut.sv, line:6:1, endln:18:10 |vpiParent: \_design: (work@tlul_socket_1n) |vpiFullName:work@tlul_socket_1n |vpiParameter: \_parameter: (work@tlul_socket_1n.DReqDepth), line:7:27, endln:7:36 |vpiParent: - \_module: work@tlul_socket_1n (work@tlul_socket_1n), file:${SURELOG_DIR}/tests/LargeHex/dut.sv, line:6:1, endln:18:10 + \_module_inst: work@tlul_socket_1n (work@tlul_socket_1n), file:${SURELOG_DIR}/tests/LargeHex/dut.sv, line:6:1, endln:18:10 |HEX:2000000000000000F |vpiTypespec: \_bit_typespec: , line:7:16, endln:7:26 @@ -1156,7 +1156,7 @@ design: (work@tlul_socket_1n) |vpiParameter: \_parameter: (work@tlul_socket_1n.ReqDepthKO), line:8:29, endln:8:39 |vpiParent: - \_module: work@tlul_socket_1n (work@tlul_socket_1n), file:${SURELOG_DIR}/tests/LargeHex/dut.sv, line:6:1, endln:18:10 + \_module_inst: work@tlul_socket_1n (work@tlul_socket_1n), file:${SURELOG_DIR}/tests/LargeHex/dut.sv, line:6:1, endln:18:10 |vpiTypespec: \_int_typespec: , line:8:16, endln:8:28 |vpiParent: @@ -1166,7 +1166,7 @@ design: (work@tlul_socket_1n) |vpiParameter: \_parameter: (work@tlul_socket_1n.ReqDepthOK), line:11:29, endln:11:39 |vpiParent: - \_module: work@tlul_socket_1n (work@tlul_socket_1n), file:${SURELOG_DIR}/tests/LargeHex/dut.sv, line:6:1, endln:18:10 + \_module_inst: work@tlul_socket_1n (work@tlul_socket_1n), file:${SURELOG_DIR}/tests/LargeHex/dut.sv, line:6:1, endln:18:10 |vpiTypespec: \_int_typespec: , line:11:16, endln:11:28 |vpiParent: @@ -1176,7 +1176,7 @@ design: (work@tlul_socket_1n) |vpiParamAssign: \_param_assign: , line:7:27, endln:7:60 |vpiParent: - \_module: work@tlul_socket_1n (work@tlul_socket_1n), file:${SURELOG_DIR}/tests/LargeHex/dut.sv, line:6:1, endln:18:10 + \_module_inst: work@tlul_socket_1n (work@tlul_socket_1n), file:${SURELOG_DIR}/tests/LargeHex/dut.sv, line:6:1, endln:18:10 |vpiRhs: \_constant: , line:7:39, endln:7:60 |vpiDecompile:76'h2000000000000000F @@ -1190,7 +1190,7 @@ design: (work@tlul_socket_1n) |vpiParamAssign: \_param_assign: , line:8:29, endln:8:59 |vpiParent: - \_module: work@tlul_socket_1n (work@tlul_socket_1n), file:${SURELOG_DIR}/tests/LargeHex/dut.sv, line:6:1, endln:18:10 + \_module_inst: work@tlul_socket_1n (work@tlul_socket_1n), file:${SURELOG_DIR}/tests/LargeHex/dut.sv, line:6:1, endln:18:10 |vpiRhs: \_indexed_part_select: , line:8:42, endln:8:59 |vpiParent: @@ -1229,7 +1229,7 @@ design: (work@tlul_socket_1n) |vpiParamAssign: \_param_assign: , line:11:29, endln:11:57 |vpiParent: - \_module: work@tlul_socket_1n (work@tlul_socket_1n), file:${SURELOG_DIR}/tests/LargeHex/dut.sv, line:6:1, endln:18:10 + \_module_inst: work@tlul_socket_1n (work@tlul_socket_1n), file:${SURELOG_DIR}/tests/LargeHex/dut.sv, line:6:1, endln:18:10 |vpiRhs: \_indexed_part_select: , line:11:42, endln:11:57 |vpiParent: @@ -1256,24 +1256,24 @@ design: (work@tlul_socket_1n) |vpiNet: \_logic_net: (work@tlul_socket_1n.storageKO), line:9:29, endln:9:38 |vpiParent: - \_module: work@tlul_socket_1n (work@tlul_socket_1n), file:${SURELOG_DIR}/tests/LargeHex/dut.sv, line:6:1, endln:18:10 + \_module_inst: work@tlul_socket_1n (work@tlul_socket_1n), file:${SURELOG_DIR}/tests/LargeHex/dut.sv, line:6:1, endln:18:10 |vpiName:storageKO |vpiFullName:work@tlul_socket_1n.storageKO |vpiNetType:36 |vpiNet: \_logic_net: (work@tlul_socket_1n.storageOK), line:12:29, endln:12:38 |vpiParent: - \_module: work@tlul_socket_1n (work@tlul_socket_1n), file:${SURELOG_DIR}/tests/LargeHex/dut.sv, line:6:1, endln:18:10 + \_module_inst: work@tlul_socket_1n (work@tlul_socket_1n), file:${SURELOG_DIR}/tests/LargeHex/dut.sv, line:6:1, endln:18:10 |vpiName:storageOK |vpiFullName:work@tlul_socket_1n.storageOK |vpiNetType:36 |uhdmtopModules: -\_module: work@tlul_socket_1n (work@tlul_socket_1n), file:${SURELOG_DIR}/tests/LargeHex/dut.sv, line:6:1, endln:18:10 +\_module_inst: work@tlul_socket_1n (work@tlul_socket_1n), file:${SURELOG_DIR}/tests/LargeHex/dut.sv, line:6:1, endln:18:10 |vpiName:work@tlul_socket_1n |vpiVariables: \_logic_var: (work@tlul_socket_1n.storageKO), line:9:29, endln:9:38 |vpiParent: - \_module: work@tlul_socket_1n (work@tlul_socket_1n), file:${SURELOG_DIR}/tests/LargeHex/dut.sv, line:6:1, endln:18:10 + \_module_inst: work@tlul_socket_1n (work@tlul_socket_1n), file:${SURELOG_DIR}/tests/LargeHex/dut.sv, line:6:1, endln:18:10 |vpiTypespec: \_logic_typespec: , line:9:6, endln:9:28 |vpiRange: @@ -1318,7 +1318,7 @@ design: (work@tlul_socket_1n) |vpiVariables: \_logic_var: (work@tlul_socket_1n.storageOK), line:12:29, endln:12:38 |vpiParent: - \_module: work@tlul_socket_1n (work@tlul_socket_1n), file:${SURELOG_DIR}/tests/LargeHex/dut.sv, line:6:1, endln:18:10 + \_module_inst: work@tlul_socket_1n (work@tlul_socket_1n), file:${SURELOG_DIR}/tests/LargeHex/dut.sv, line:6:1, endln:18:10 |vpiTypespec: \_logic_typespec: , line:12:6, endln:12:28 |vpiRange: @@ -1363,7 +1363,7 @@ design: (work@tlul_socket_1n) |vpiParameter: \_parameter: (work@tlul_socket_1n.DReqDepth), line:7:27, endln:7:36 |vpiParent: - \_module: work@tlul_socket_1n (work@tlul_socket_1n), file:${SURELOG_DIR}/tests/LargeHex/dut.sv, line:6:1, endln:18:10 + \_module_inst: work@tlul_socket_1n (work@tlul_socket_1n), file:${SURELOG_DIR}/tests/LargeHex/dut.sv, line:6:1, endln:18:10 |HEX:2000000000000000F |vpiTypespec: \_bit_typespec: , line:7:16, endln:7:26 @@ -1395,7 +1395,7 @@ design: (work@tlul_socket_1n) |vpiParameter: \_parameter: (work@tlul_socket_1n.ReqDepthKO), line:8:29, endln:8:39 |vpiParent: - \_module: work@tlul_socket_1n (work@tlul_socket_1n), file:${SURELOG_DIR}/tests/LargeHex/dut.sv, line:6:1, endln:18:10 + \_module_inst: work@tlul_socket_1n (work@tlul_socket_1n), file:${SURELOG_DIR}/tests/LargeHex/dut.sv, line:6:1, endln:18:10 |vpiTypespec: \_int_typespec: , line:8:16, endln:8:28 |vpiParent: @@ -1405,7 +1405,7 @@ design: (work@tlul_socket_1n) |vpiParameter: \_parameter: (work@tlul_socket_1n.ReqDepthOK), line:11:29, endln:11:39 |vpiParent: - \_module: work@tlul_socket_1n (work@tlul_socket_1n), file:${SURELOG_DIR}/tests/LargeHex/dut.sv, line:6:1, endln:18:10 + \_module_inst: work@tlul_socket_1n (work@tlul_socket_1n), file:${SURELOG_DIR}/tests/LargeHex/dut.sv, line:6:1, endln:18:10 |vpiTypespec: \_int_typespec: , line:11:16, endln:11:28 |vpiParent: @@ -1415,7 +1415,7 @@ design: (work@tlul_socket_1n) |vpiParamAssign: \_param_assign: , line:7:27, endln:7:60 |vpiParent: - \_module: work@tlul_socket_1n (work@tlul_socket_1n), file:${SURELOG_DIR}/tests/LargeHex/dut.sv, line:6:1, endln:18:10 + \_module_inst: work@tlul_socket_1n (work@tlul_socket_1n), file:${SURELOG_DIR}/tests/LargeHex/dut.sv, line:6:1, endln:18:10 |vpiRhs: \_constant: , line:7:39, endln:7:60 |vpiDecompile:76'h2000000000000000F @@ -1437,7 +1437,7 @@ design: (work@tlul_socket_1n) |vpiParamAssign: \_param_assign: , line:8:29, endln:8:59 |vpiParent: - \_module: work@tlul_socket_1n (work@tlul_socket_1n), file:${SURELOG_DIR}/tests/LargeHex/dut.sv, line:6:1, endln:18:10 + \_module_inst: work@tlul_socket_1n (work@tlul_socket_1n), file:${SURELOG_DIR}/tests/LargeHex/dut.sv, line:6:1, endln:18:10 |vpiRhs: \_constant: , line:8:42, endln:8:59 |vpiDecompile:0 @@ -1451,7 +1451,7 @@ design: (work@tlul_socket_1n) |vpiParamAssign: \_param_assign: , line:11:29, endln:11:57 |vpiParent: - \_module: work@tlul_socket_1n (work@tlul_socket_1n), file:${SURELOG_DIR}/tests/LargeHex/dut.sv, line:6:1, endln:18:10 + \_module_inst: work@tlul_socket_1n (work@tlul_socket_1n), file:${SURELOG_DIR}/tests/LargeHex/dut.sv, line:6:1, endln:18:10 |vpiRhs: \_constant: , line:11:42, endln:11:57 |vpiDecompile:15 @@ -1465,16 +1465,16 @@ design: (work@tlul_socket_1n) |vpiDefName:work@tlul_socket_1n |vpiTop:1 |vpiTopModule:1 - |vpiModule: - \_module: work@tlul_fifo_sync (work@tlul_socket_1n.fifo_d), file:${SURELOG_DIR}/tests/LargeHex/dut.sv, line:14:5, endln:16:17 + |vpiModuleInst: + \_module_inst: work@tlul_fifo_sync (work@tlul_socket_1n.fifo_d), file:${SURELOG_DIR}/tests/LargeHex/dut.sv, line:14:5, endln:16:17 |vpiParent: - \_module: work@tlul_socket_1n (work@tlul_socket_1n), file:${SURELOG_DIR}/tests/LargeHex/dut.sv, line:6:1, endln:18:10 + \_module_inst: work@tlul_socket_1n (work@tlul_socket_1n), file:${SURELOG_DIR}/tests/LargeHex/dut.sv, line:6:1, endln:18:10 |vpiName:fifo_d |vpiFullName:work@tlul_socket_1n.fifo_d |vpiVariables: \_logic_var: (work@tlul_socket_1n.fifo_d.storage), line:2:25, endln:2:32 |vpiParent: - \_module: work@tlul_fifo_sync (work@tlul_socket_1n.fifo_d), file:${SURELOG_DIR}/tests/LargeHex/dut.sv, line:14:5, endln:16:17 + \_module_inst: work@tlul_fifo_sync (work@tlul_socket_1n.fifo_d), file:${SURELOG_DIR}/tests/LargeHex/dut.sv, line:14:5, endln:16:17 |vpiTypespec: \_logic_typespec: , line:2:4, endln:2:24 |vpiRange: @@ -1519,7 +1519,7 @@ design: (work@tlul_socket_1n) |vpiParameter: \_parameter: (work@tlul_socket_1n.fifo_d.ReqDepth), line:1:48, endln:1:56 |vpiParent: - \_module: work@tlul_fifo_sync (work@tlul_socket_1n.fifo_d), file:${SURELOG_DIR}/tests/LargeHex/dut.sv, line:14:5, endln:16:17 + \_module_inst: work@tlul_fifo_sync (work@tlul_socket_1n.fifo_d), file:${SURELOG_DIR}/tests/LargeHex/dut.sv, line:14:5, endln:16:17 |UINT:2 |vpiTypespec: \_int_typespec: , line:1:35, endln:1:47 @@ -1530,7 +1530,7 @@ design: (work@tlul_socket_1n) |vpiParamAssign: \_param_assign: , line:1:48, endln:1:60 |vpiParent: - \_module: work@tlul_fifo_sync (work@tlul_socket_1n.fifo_d), file:${SURELOG_DIR}/tests/LargeHex/dut.sv, line:14:5, endln:16:17 + \_module_inst: work@tlul_fifo_sync (work@tlul_socket_1n.fifo_d), file:${SURELOG_DIR}/tests/LargeHex/dut.sv, line:14:5, endln:16:17 |vpiOverriden:1 |vpiRhs: \_constant: , line:1:59, endln:1:60 @@ -1546,7 +1546,7 @@ design: (work@tlul_socket_1n) |vpiDefFile:${SURELOG_DIR}/tests/LargeHex/dut.sv |vpiDefLineNo:1 |vpiInstance: - \_module: work@tlul_socket_1n (work@tlul_socket_1n), file:${SURELOG_DIR}/tests/LargeHex/dut.sv, line:6:1, endln:18:10 + \_module_inst: work@tlul_socket_1n (work@tlul_socket_1n), file:${SURELOG_DIR}/tests/LargeHex/dut.sv, line:6:1, endln:18:10 =================== [ FATAL] : 0 [ SYNTAX] : 0 diff --git a/tests/LargeHexCast/LargeHexCast.log b/tests/LargeHexCast/LargeHexCast.log index 4ab5ef97d9..2bdd206e22 100644 --- a/tests/LargeHexCast/LargeHexCast.log +++ b/tests/LargeHexCast/LargeHexCast.log @@ -402,7 +402,7 @@ integer_typespec 12 io_decl 11 logic_typespec 22 logic_var 1 -module 5 +module_inst 5 operation 36 package 5 param_assign 12 @@ -433,7 +433,7 @@ integer_typespec 12 io_decl 22 logic_typespec 22 logic_var 1 -module 5 +module_inst 5 operation 36 package 5 param_assign 12 @@ -632,7 +632,7 @@ design: (work@kmac_entropy) |vpiTypespec: \_struct_typespec: (kmac_pkg::app_config_t), line:2:12, endln:2:18 |vpiParent: - \_module: work@kmac_entropy (work@kmac_entropy), file:${SURELOG_DIR}/tests/LargeHexCast/dut.sv, line:15:1, endln:17:25 + \_module_inst: work@kmac_entropy (work@kmac_entropy), file:${SURELOG_DIR}/tests/LargeHexCast/dut.sv, line:15:1, endln:17:25 |vpiName:kmac_pkg::app_config_t |vpiInstance: \_package: kmac_pkg (kmac_pkg::), file:${SURELOG_DIR}/tests/LargeHexCast/dut.sv, line:1:1, endln:13:22 @@ -1168,14 +1168,14 @@ design: (work@kmac_entropy) \_int_typespec: |vpiSigned:1 |uhdmallModules: -\_module: work@kmac_entropy (work@kmac_entropy), file:${SURELOG_DIR}/tests/LargeHexCast/dut.sv, line:15:1, endln:17:25 +\_module_inst: work@kmac_entropy (work@kmac_entropy), file:${SURELOG_DIR}/tests/LargeHexCast/dut.sv, line:15:1, endln:17:25 |vpiParent: \_design: (work@kmac_entropy) |vpiFullName:work@kmac_entropy |vpiParameter: \_parameter: (work@kmac_entropy.A), line:6:27, endln:6:28 |vpiParent: - \_module: work@kmac_entropy (work@kmac_entropy), file:${SURELOG_DIR}/tests/LargeHexCast/dut.sv, line:15:1, endln:17:25 + \_module_inst: work@kmac_entropy (work@kmac_entropy), file:${SURELOG_DIR}/tests/LargeHexCast/dut.sv, line:15:1, endln:17:25 |vpiTypespec: \_struct_typespec: (kmac_pkg::app_config_t), line:2:12, endln:2:18 |vpiParent: @@ -1226,7 +1226,7 @@ design: (work@kmac_entropy) |vpiParameter: \_parameter: (work@kmac_entropy.B), line:10:27, endln:10:28 |vpiParent: - \_module: work@kmac_entropy (work@kmac_entropy), file:${SURELOG_DIR}/tests/LargeHexCast/dut.sv, line:15:1, endln:17:25 + \_module_inst: work@kmac_entropy (work@kmac_entropy), file:${SURELOG_DIR}/tests/LargeHexCast/dut.sv, line:15:1, endln:17:25 |vpiTypespec: \_struct_typespec: (kmac_pkg::app_config_t), line:2:12, endln:2:18 |vpiParent: @@ -1277,7 +1277,7 @@ design: (work@kmac_entropy) |vpiParamAssign: \_param_assign: , line:6:27, endln:8:5 |vpiParent: - \_module: work@kmac_entropy (work@kmac_entropy), file:${SURELOG_DIR}/tests/LargeHexCast/dut.sv, line:15:1, endln:17:25 + \_module_inst: work@kmac_entropy (work@kmac_entropy), file:${SURELOG_DIR}/tests/LargeHexCast/dut.sv, line:15:1, endln:17:25 |vpiRhs: \_operation: , line:6:31, endln:8:5 |vpiParent: @@ -1366,7 +1366,7 @@ design: (work@kmac_entropy) |vpiParamAssign: \_param_assign: , line:10:27, endln:12:5 |vpiParent: - \_module: work@kmac_entropy (work@kmac_entropy), file:${SURELOG_DIR}/tests/LargeHexCast/dut.sv, line:15:1, endln:17:25 + \_module_inst: work@kmac_entropy (work@kmac_entropy), file:${SURELOG_DIR}/tests/LargeHexCast/dut.sv, line:15:1, endln:17:25 |vpiRhs: \_operation: , line:10:31, endln:12:5 |vpiParent: @@ -1446,12 +1446,12 @@ design: (work@kmac_entropy) \_import_typespec: (kmac_pkg), line:16:11, endln:16:22 |vpiDefName:work@kmac_entropy |uhdmtopModules: -\_module: work@kmac_entropy (work@kmac_entropy), file:${SURELOG_DIR}/tests/LargeHexCast/dut.sv, line:15:1, endln:17:25 +\_module_inst: work@kmac_entropy (work@kmac_entropy), file:${SURELOG_DIR}/tests/LargeHexCast/dut.sv, line:15:1, endln:17:25 |vpiName:work@kmac_entropy |vpiParameter: \_parameter: (work@kmac_entropy.A), line:6:27, endln:6:28 |vpiParent: - \_module: work@kmac_entropy (work@kmac_entropy), file:${SURELOG_DIR}/tests/LargeHexCast/dut.sv, line:15:1, endln:17:25 + \_module_inst: work@kmac_entropy (work@kmac_entropy), file:${SURELOG_DIR}/tests/LargeHexCast/dut.sv, line:15:1, endln:17:25 |vpiTypespec: \_struct_typespec: (kmac_pkg::app_config_t), line:2:12, endln:2:18 |vpiParent: @@ -1502,7 +1502,7 @@ design: (work@kmac_entropy) |vpiParameter: \_parameter: (work@kmac_entropy.B), line:10:27, endln:10:28 |vpiParent: - \_module: work@kmac_entropy (work@kmac_entropy), file:${SURELOG_DIR}/tests/LargeHexCast/dut.sv, line:15:1, endln:17:25 + \_module_inst: work@kmac_entropy (work@kmac_entropy), file:${SURELOG_DIR}/tests/LargeHexCast/dut.sv, line:15:1, endln:17:25 |vpiTypespec: \_struct_typespec: (kmac_pkg::app_config_t), line:2:12, endln:2:18 |vpiParent: @@ -1553,7 +1553,7 @@ design: (work@kmac_entropy) |vpiParamAssign: \_param_assign: , line:6:27, endln:8:5 |vpiParent: - \_module: work@kmac_entropy (work@kmac_entropy), file:${SURELOG_DIR}/tests/LargeHexCast/dut.sv, line:15:1, endln:17:25 + \_module_inst: work@kmac_entropy (work@kmac_entropy), file:${SURELOG_DIR}/tests/LargeHexCast/dut.sv, line:15:1, endln:17:25 |vpiRhs: \_operation: , line:6:31, endln:8:5 |vpiParent: @@ -1629,7 +1629,7 @@ design: (work@kmac_entropy) |vpiParamAssign: \_param_assign: , line:10:27, endln:12:5 |vpiParent: - \_module: work@kmac_entropy (work@kmac_entropy), file:${SURELOG_DIR}/tests/LargeHexCast/dut.sv, line:15:1, endln:17:25 + \_module_inst: work@kmac_entropy (work@kmac_entropy), file:${SURELOG_DIR}/tests/LargeHexCast/dut.sv, line:15:1, endln:17:25 |vpiRhs: \_operation: , line:10:31, endln:12:5 |vpiParent: diff --git a/tests/LeftPadding/LeftPadding.log b/tests/LeftPadding/LeftPadding.log index b6833495a1..f922e75d20 100644 --- a/tests/LeftPadding/LeftPadding.log +++ b/tests/LeftPadding/LeftPadding.log @@ -269,7 +269,7 @@ design 1 gen_scope 2 gen_scope_array 2 int_typespec 11 -module 5 +module_inst 5 operation 23 param_assign 8 parameter 8 @@ -284,7 +284,7 @@ design 1 gen_scope 3 gen_scope_array 3 int_typespec 11 -module 6 +module_inst 6 operation 23 param_assign 8 parameter 8 @@ -303,14 +303,14 @@ design: (work@socket_1n) |vpiElaborated:1 |vpiName:work@socket_1n |uhdmallModules: -\_module: work@socket_1n (work@socket_1n), file:${SURELOG_DIR}/tests/LeftPadding/dut.sv, line:1:1, endln:11:10 +\_module_inst: work@socket_1n (work@socket_1n), file:${SURELOG_DIR}/tests/LeftPadding/dut.sv, line:1:1, endln:11:10 |vpiParent: \_design: (work@socket_1n) |vpiFullName:work@socket_1n |vpiParameter: \_parameter: (work@socket_1n.P1), line:2:23, endln:2:25 |vpiParent: - \_module: work@socket_1n (work@socket_1n), file:${SURELOG_DIR}/tests/LeftPadding/dut.sv, line:1:1, endln:11:10 + \_module_inst: work@socket_1n (work@socket_1n), file:${SURELOG_DIR}/tests/LeftPadding/dut.sv, line:1:1, endln:11:10 |vpiTypespec: \_bit_typespec: , line:2:13, endln:2:22 |vpiParent: @@ -339,7 +339,7 @@ design: (work@socket_1n) |vpiParameter: \_parameter: (work@socket_1n.P2), line:3:23, endln:3:25 |vpiParent: - \_module: work@socket_1n (work@socket_1n), file:${SURELOG_DIR}/tests/LeftPadding/dut.sv, line:1:1, endln:11:10 + \_module_inst: work@socket_1n (work@socket_1n), file:${SURELOG_DIR}/tests/LeftPadding/dut.sv, line:1:1, endln:11:10 |vpiTypespec: \_bit_typespec: , line:3:13, endln:3:22 |vpiParent: @@ -368,7 +368,7 @@ design: (work@socket_1n) |vpiParameter: \_parameter: (work@socket_1n.P3), line:4:23, endln:4:25 |vpiParent: - \_module: work@socket_1n (work@socket_1n), file:${SURELOG_DIR}/tests/LeftPadding/dut.sv, line:1:1, endln:11:10 + \_module_inst: work@socket_1n (work@socket_1n), file:${SURELOG_DIR}/tests/LeftPadding/dut.sv, line:1:1, endln:11:10 |vpiTypespec: \_bit_typespec: , line:4:13, endln:4:22 |vpiParent: @@ -397,7 +397,7 @@ design: (work@socket_1n) |vpiParameter: \_parameter: (work@socket_1n.P4), line:5:23, endln:5:25 |vpiParent: - \_module: work@socket_1n (work@socket_1n), file:${SURELOG_DIR}/tests/LeftPadding/dut.sv, line:1:1, endln:11:10 + \_module_inst: work@socket_1n (work@socket_1n), file:${SURELOG_DIR}/tests/LeftPadding/dut.sv, line:1:1, endln:11:10 |vpiTypespec: \_bit_typespec: , line:5:13, endln:5:22 |vpiParent: @@ -426,7 +426,7 @@ design: (work@socket_1n) |vpiParamAssign: \_param_assign: , line:2:23, endln:2:43 |vpiParent: - \_module: work@socket_1n (work@socket_1n), file:${SURELOG_DIR}/tests/LeftPadding/dut.sv, line:1:1, endln:11:10 + \_module_inst: work@socket_1n (work@socket_1n), file:${SURELOG_DIR}/tests/LeftPadding/dut.sv, line:1:1, endln:11:10 |vpiRhs: \_operation: , line:2:28, endln:2:43 |vpiOpType:34 @@ -460,7 +460,7 @@ design: (work@socket_1n) |vpiParamAssign: \_param_assign: , line:3:23, endln:3:37 |vpiParent: - \_module: work@socket_1n (work@socket_1n), file:${SURELOG_DIR}/tests/LeftPadding/dut.sv, line:1:1, endln:11:10 + \_module_inst: work@socket_1n (work@socket_1n), file:${SURELOG_DIR}/tests/LeftPadding/dut.sv, line:1:1, endln:11:10 |vpiRhs: \_operation: , line:3:28, endln:3:37 |vpiOpType:34 @@ -488,7 +488,7 @@ design: (work@socket_1n) |vpiParamAssign: \_param_assign: , line:4:23, endln:4:44 |vpiParent: - \_module: work@socket_1n (work@socket_1n), file:${SURELOG_DIR}/tests/LeftPadding/dut.sv, line:1:1, endln:11:10 + \_module_inst: work@socket_1n (work@socket_1n), file:${SURELOG_DIR}/tests/LeftPadding/dut.sv, line:1:1, endln:11:10 |vpiRhs: \_operation: , line:4:28, endln:4:44 |vpiOpType:34 @@ -522,7 +522,7 @@ design: (work@socket_1n) |vpiParamAssign: \_param_assign: , line:5:23, endln:5:38 |vpiParent: - \_module: work@socket_1n (work@socket_1n), file:${SURELOG_DIR}/tests/LeftPadding/dut.sv, line:1:1, endln:11:10 + \_module_inst: work@socket_1n (work@socket_1n), file:${SURELOG_DIR}/tests/LeftPadding/dut.sv, line:1:1, endln:11:10 |vpiRhs: \_operation: , line:5:28, endln:5:38 |vpiOpType:34 @@ -549,12 +549,12 @@ design: (work@socket_1n) \_parameter: (work@socket_1n.P4), line:5:23, endln:5:25 |vpiDefName:work@socket_1n |uhdmtopModules: -\_module: work@socket_1n (work@socket_1n), file:${SURELOG_DIR}/tests/LeftPadding/dut.sv, line:1:1, endln:11:10 +\_module_inst: work@socket_1n (work@socket_1n), file:${SURELOG_DIR}/tests/LeftPadding/dut.sv, line:1:1, endln:11:10 |vpiName:work@socket_1n |vpiParameter: \_parameter: (work@socket_1n.P1), line:2:23, endln:2:25 |vpiParent: - \_module: work@socket_1n (work@socket_1n), file:${SURELOG_DIR}/tests/LeftPadding/dut.sv, line:1:1, endln:11:10 + \_module_inst: work@socket_1n (work@socket_1n), file:${SURELOG_DIR}/tests/LeftPadding/dut.sv, line:1:1, endln:11:10 |vpiTypespec: \_bit_typespec: , line:2:13, endln:2:22 |vpiParent: @@ -585,7 +585,7 @@ design: (work@socket_1n) |vpiParameter: \_parameter: (work@socket_1n.P2), line:3:23, endln:3:25 |vpiParent: - \_module: work@socket_1n (work@socket_1n), file:${SURELOG_DIR}/tests/LeftPadding/dut.sv, line:1:1, endln:11:10 + \_module_inst: work@socket_1n (work@socket_1n), file:${SURELOG_DIR}/tests/LeftPadding/dut.sv, line:1:1, endln:11:10 |vpiTypespec: \_bit_typespec: , line:3:13, endln:3:22 |vpiParent: @@ -616,7 +616,7 @@ design: (work@socket_1n) |vpiParameter: \_parameter: (work@socket_1n.P3), line:4:23, endln:4:25 |vpiParent: - \_module: work@socket_1n (work@socket_1n), file:${SURELOG_DIR}/tests/LeftPadding/dut.sv, line:1:1, endln:11:10 + \_module_inst: work@socket_1n (work@socket_1n), file:${SURELOG_DIR}/tests/LeftPadding/dut.sv, line:1:1, endln:11:10 |vpiTypespec: \_bit_typespec: , line:4:13, endln:4:22 |vpiParent: @@ -647,7 +647,7 @@ design: (work@socket_1n) |vpiParameter: \_parameter: (work@socket_1n.P4), line:5:23, endln:5:25 |vpiParent: - \_module: work@socket_1n (work@socket_1n), file:${SURELOG_DIR}/tests/LeftPadding/dut.sv, line:1:1, endln:11:10 + \_module_inst: work@socket_1n (work@socket_1n), file:${SURELOG_DIR}/tests/LeftPadding/dut.sv, line:1:1, endln:11:10 |vpiTypespec: \_bit_typespec: , line:5:13, endln:5:22 |vpiParent: @@ -678,7 +678,7 @@ design: (work@socket_1n) |vpiParamAssign: \_param_assign: , line:2:23, endln:2:43 |vpiParent: - \_module: work@socket_1n (work@socket_1n), file:${SURELOG_DIR}/tests/LeftPadding/dut.sv, line:1:1, endln:11:10 + \_module_inst: work@socket_1n (work@socket_1n), file:${SURELOG_DIR}/tests/LeftPadding/dut.sv, line:1:1, endln:11:10 |vpiRhs: \_constant: , line:2:28, endln:2:43 |vpiDecompile:8'b00100010 @@ -692,7 +692,7 @@ design: (work@socket_1n) |vpiParamAssign: \_param_assign: , line:3:23, endln:3:37 |vpiParent: - \_module: work@socket_1n (work@socket_1n), file:${SURELOG_DIR}/tests/LeftPadding/dut.sv, line:1:1, endln:11:10 + \_module_inst: work@socket_1n (work@socket_1n), file:${SURELOG_DIR}/tests/LeftPadding/dut.sv, line:1:1, endln:11:10 |vpiRhs: \_constant: , line:3:28, endln:3:37 |vpiDecompile:8'b00100010 @@ -706,7 +706,7 @@ design: (work@socket_1n) |vpiParamAssign: \_param_assign: , line:4:23, endln:4:44 |vpiParent: - \_module: work@socket_1n (work@socket_1n), file:${SURELOG_DIR}/tests/LeftPadding/dut.sv, line:1:1, endln:11:10 + \_module_inst: work@socket_1n (work@socket_1n), file:${SURELOG_DIR}/tests/LeftPadding/dut.sv, line:1:1, endln:11:10 |vpiRhs: \_constant: , line:4:28, endln:4:44 |vpiDecompile:8'b00100010 @@ -720,7 +720,7 @@ design: (work@socket_1n) |vpiParamAssign: \_param_assign: , line:5:23, endln:5:38 |vpiParent: - \_module: work@socket_1n (work@socket_1n), file:${SURELOG_DIR}/tests/LeftPadding/dut.sv, line:1:1, endln:11:10 + \_module_inst: work@socket_1n (work@socket_1n), file:${SURELOG_DIR}/tests/LeftPadding/dut.sv, line:1:1, endln:11:10 |vpiRhs: \_constant: , line:5:28, endln:5:38 |vpiDecompile:8'b00100010 @@ -737,7 +737,7 @@ design: (work@socket_1n) |vpiGenScopeArray: \_gen_scope_array: (work@socket_1n.genblk1), line:7:3, endln:9:6 |vpiParent: - \_module: work@socket_1n (work@socket_1n), file:${SURELOG_DIR}/tests/LeftPadding/dut.sv, line:1:1, endln:11:10 + \_module_inst: work@socket_1n (work@socket_1n), file:${SURELOG_DIR}/tests/LeftPadding/dut.sv, line:1:1, endln:11:10 |vpiName:genblk1 |vpiFullName:work@socket_1n.genblk1 |vpiGenScope: @@ -745,8 +745,8 @@ design: (work@socket_1n) |vpiParent: \_gen_scope_array: (work@socket_1n.genblk1), line:7:3, endln:9:6 |vpiFullName:work@socket_1n.genblk1 - |vpiModule: - \_module: work@socket_1n.genblk1::GOOD (work@socket_1n.genblk1.good), file:${SURELOG_DIR}/tests/LeftPadding/dut.sv, line:8:5, endln:8:17 + |vpiModuleInst: + \_module_inst: work@socket_1n.genblk1::GOOD (work@socket_1n.genblk1.good), file:${SURELOG_DIR}/tests/LeftPadding/dut.sv, line:8:5, endln:8:17 |vpiParent: \_gen_scope: (work@socket_1n.genblk1) |vpiName:good diff --git a/tests/LetExpr/LetExpr.log b/tests/LetExpr/LetExpr.log index 00a02a5713..f98cf3e194 100644 --- a/tests/LetExpr/LetExpr.log +++ b/tests/LetExpr/LetExpr.log @@ -207,7 +207,7 @@ let_expr 3 logic_net 3 logic_typespec 1 logic_var 1 -module 2 +module_inst 2 operation 1 ref_obj 7 seq_formal_decl 3 @@ -227,7 +227,7 @@ let_expr 6 logic_net 3 logic_typespec 1 logic_var 1 -module 2 +module_inst 2 operation 3 ref_obj 18 seq_formal_decl 3 @@ -246,7 +246,7 @@ design: (work@m) |vpiElaborated:1 |vpiName:work@m |uhdmallModules: -\_module: work@m (work@m), file:${SURELOG_DIR}/tests/LetExpr/dut.sv, line:2:1, endln:16:14 +\_module_inst: work@m (work@m), file:${SURELOG_DIR}/tests/LetExpr/dut.sv, line:2:1, endln:16:14 |vpiParent: \_design: (work@m) |vpiFullName:work@m @@ -317,14 +317,14 @@ design: (work@m) |vpiNet: \_logic_net: (work@m.a), line:3:7, endln:3:8 |vpiParent: - \_module: work@m (work@m), file:${SURELOG_DIR}/tests/LetExpr/dut.sv, line:2:1, endln:16:14 + \_module_inst: work@m (work@m), file:${SURELOG_DIR}/tests/LetExpr/dut.sv, line:2:1, endln:16:14 |vpiName:a |vpiFullName:work@m.a |vpiNetType:36 |vpiProcess: \_always: , line:9:1, endln:13:4 |vpiParent: - \_module: work@m (work@m), file:${SURELOG_DIR}/tests/LetExpr/dut.sv, line:2:1, endln:16:14 + \_module_inst: work@m (work@m), file:${SURELOG_DIR}/tests/LetExpr/dut.sv, line:2:1, endln:16:14 |vpiStmt: \_begin: (work@m), line:9:13, endln:13:4 |vpiParent: @@ -380,12 +380,12 @@ design: (work@m) \_let_decl: (s), line:7:1, endln:7:24 |vpiAlwaysType:2 |uhdmtopModules: -\_module: work@m (work@m), file:${SURELOG_DIR}/tests/LetExpr/dut.sv, line:2:1, endln:16:14 +\_module_inst: work@m (work@m), file:${SURELOG_DIR}/tests/LetExpr/dut.sv, line:2:1, endln:16:14 |vpiName:work@m |vpiVariables: \_logic_var: (work@m.a), line:3:7, endln:3:8 |vpiParent: - \_module: work@m (work@m), file:${SURELOG_DIR}/tests/LetExpr/dut.sv, line:2:1, endln:16:14 + \_module_inst: work@m (work@m), file:${SURELOG_DIR}/tests/LetExpr/dut.sv, line:2:1, endln:16:14 |vpiTypespec: \_logic_typespec: , line:3:1, endln:3:6 |vpiName:a @@ -394,7 +394,7 @@ design: (work@m) |vpiLetDecl: \_let_decl: (p1), line:4:1, endln:4:22 |vpiParent: - \_module: work@m (work@m), file:${SURELOG_DIR}/tests/LetExpr/dut.sv, line:2:1, endln:16:14 + \_module_inst: work@m (work@m), file:${SURELOG_DIR}/tests/LetExpr/dut.sv, line:2:1, endln:16:14 |vpiExpr: \_sys_func_call: ($past), line:4:13, endln:4:21 |vpiParent: @@ -412,7 +412,7 @@ design: (work@m) |vpiLetDecl: \_let_decl: (p2), line:6:1, endln:6:41 |vpiParent: - \_module: work@m (work@m), file:${SURELOG_DIR}/tests/LetExpr/dut.sv, line:2:1, endln:16:14 + \_module_inst: work@m (work@m), file:${SURELOG_DIR}/tests/LetExpr/dut.sv, line:2:1, endln:16:14 |vpiExpr: \_sys_func_call: ($past), line:6:13, endln:6:18 |vpiParent: @@ -447,7 +447,7 @@ design: (work@m) |vpiLetDecl: \_let_decl: (s), line:7:1, endln:7:24 |vpiParent: - \_module: work@m (work@m), file:${SURELOG_DIR}/tests/LetExpr/dut.sv, line:2:1, endln:16:14 + \_module_inst: work@m (work@m), file:${SURELOG_DIR}/tests/LetExpr/dut.sv, line:2:1, endln:16:14 |vpiExpr: \_sys_func_call: ($sampled), line:7:12, endln:7:23 |vpiParent: @@ -476,7 +476,7 @@ design: (work@m) |vpiProcess: \_always: , line:9:1, endln:13:4 |vpiParent: - \_module: work@m (work@m), file:${SURELOG_DIR}/tests/LetExpr/dut.sv, line:2:1, endln:16:14 + \_module_inst: work@m (work@m), file:${SURELOG_DIR}/tests/LetExpr/dut.sv, line:2:1, endln:16:14 |vpiStmt: \_begin: (work@m), line:9:13, endln:13:4 |vpiParent: diff --git a/tests/LetInlined/LetInlined.log b/tests/LetInlined/LetInlined.log index 27961718b4..28ac998f01 100644 --- a/tests/LetInlined/LetInlined.log +++ b/tests/LetInlined/LetInlined.log @@ -207,7 +207,7 @@ let_decl 3 logic_net 3 logic_typespec 1 logic_var 1 -module 5 +module_inst 5 operation 1 param_assign 3 parameter 3 @@ -229,7 +229,7 @@ let_decl 6 logic_net 3 logic_typespec 1 logic_var 1 -module 5 +module_inst 5 operation 3 param_assign 3 parameter 3 @@ -250,7 +250,7 @@ design: (work@m) |vpiElaborated:1 |vpiName:work@m |uhdmallModules: -\_module: work@m (work@m), file:${SURELOG_DIR}/tests/LetInlined/dut.sv, line:2:1, endln:16:14 +\_module_inst: work@m (work@m), file:${SURELOG_DIR}/tests/LetInlined/dut.sv, line:2:1, endln:16:14 |vpiParent: \_design: (work@m) |vpiFullName:work@m @@ -331,14 +331,14 @@ design: (work@m) |vpiNet: \_logic_net: (work@m.a), line:3:7, endln:3:8 |vpiParent: - \_module: work@m (work@m), file:${SURELOG_DIR}/tests/LetInlined/dut.sv, line:2:1, endln:16:14 + \_module_inst: work@m (work@m), file:${SURELOG_DIR}/tests/LetInlined/dut.sv, line:2:1, endln:16:14 |vpiName:a |vpiFullName:work@m.a |vpiNetType:36 |vpiProcess: \_always: , line:9:1, endln:13:4 |vpiParent: - \_module: work@m (work@m), file:${SURELOG_DIR}/tests/LetInlined/dut.sv, line:2:1, endln:16:14 + \_module_inst: work@m (work@m), file:${SURELOG_DIR}/tests/LetInlined/dut.sv, line:2:1, endln:16:14 |vpiStmt: \_begin: (work@m), line:9:13, endln:13:4 |vpiParent: @@ -367,12 +367,12 @@ design: (work@m) \_sys_func_call: ($sampled), line:7:12, endln:7:23 |vpiAlwaysType:2 |uhdmtopModules: -\_module: work@m (work@m), file:${SURELOG_DIR}/tests/LetInlined/dut.sv, line:2:1, endln:16:14 +\_module_inst: work@m (work@m), file:${SURELOG_DIR}/tests/LetInlined/dut.sv, line:2:1, endln:16:14 |vpiName:work@m |vpiVariables: \_logic_var: (work@m.a), line:3:7, endln:3:8 |vpiParent: - \_module: work@m (work@m), file:${SURELOG_DIR}/tests/LetInlined/dut.sv, line:2:1, endln:16:14 + \_module_inst: work@m (work@m), file:${SURELOG_DIR}/tests/LetInlined/dut.sv, line:2:1, endln:16:14 |vpiTypespec: \_logic_typespec: , line:3:1, endln:3:6 |vpiName:a @@ -381,7 +381,7 @@ design: (work@m) |vpiLetDecl: \_let_decl: (p1), line:4:1, endln:4:22 |vpiParent: - \_module: work@m (work@m), file:${SURELOG_DIR}/tests/LetInlined/dut.sv, line:2:1, endln:16:14 + \_module_inst: work@m (work@m), file:${SURELOG_DIR}/tests/LetInlined/dut.sv, line:2:1, endln:16:14 |vpiExpr: \_sys_func_call: ($past), line:4:13, endln:4:21 |vpiParent: @@ -399,7 +399,7 @@ design: (work@m) |vpiLetDecl: \_let_decl: (p2), line:6:1, endln:6:41 |vpiParent: - \_module: work@m (work@m), file:${SURELOG_DIR}/tests/LetInlined/dut.sv, line:2:1, endln:16:14 + \_module_inst: work@m (work@m), file:${SURELOG_DIR}/tests/LetInlined/dut.sv, line:2:1, endln:16:14 |vpiExpr: \_sys_func_call: ($past), line:6:13, endln:6:18 |vpiParent: @@ -434,7 +434,7 @@ design: (work@m) |vpiLetDecl: \_let_decl: (s), line:7:1, endln:7:24 |vpiParent: - \_module: work@m (work@m), file:${SURELOG_DIR}/tests/LetInlined/dut.sv, line:2:1, endln:16:14 + \_module_inst: work@m (work@m), file:${SURELOG_DIR}/tests/LetInlined/dut.sv, line:2:1, endln:16:14 |vpiExpr: \_sys_func_call: ($sampled), line:7:12, endln:7:23 |vpiParent: @@ -463,7 +463,7 @@ design: (work@m) |vpiProcess: \_always: , line:9:1, endln:13:4 |vpiParent: - \_module: work@m (work@m), file:${SURELOG_DIR}/tests/LetInlined/dut.sv, line:2:1, endln:16:14 + \_module_inst: work@m (work@m), file:${SURELOG_DIR}/tests/LetInlined/dut.sv, line:2:1, endln:16:14 |vpiStmt: \_begin: (work@m), line:9:13, endln:13:4 |vpiParent: diff --git a/tests/LhsHierPath/LhsHierPath.log b/tests/LhsHierPath/LhsHierPath.log index b2f9ba9cbe..b336539865 100644 --- a/tests/LhsHierPath/LhsHierPath.log +++ b/tests/LhsHierPath/LhsHierPath.log @@ -171,7 +171,7 @@ design 1 hier_path 3 logic_net 3 logic_typespec 5 -module 4 +module_inst 4 package 3 packed_array_typespec 2 port 2 @@ -194,7 +194,7 @@ design 1 hier_path 5 logic_net 3 logic_typespec 5 -module 4 +module_inst 4 package 3 packed_array_typespec 2 port 3 @@ -372,7 +372,7 @@ design: (work@top) |vpiDefName:my_pkg |vpiTop:1 |uhdmallModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/LhsHierPath/dut.sv, line:11:1, endln:17:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/LhsHierPath/dut.sv, line:11:1, endln:17:10 |vpiParent: \_design: (work@top) |vpiFullName:work@top @@ -380,19 +380,19 @@ design: (work@top) |vpiNet: \_logic_net: (work@top.o), line:11:19, endln:11:20 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/LhsHierPath/dut.sv, line:11:1, endln:17:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/LhsHierPath/dut.sv, line:11:1, endln:17:10 |vpiName:o |vpiFullName:work@top.o |vpiNet: \_logic_net: (work@top.ast_alert_o), line:12:28, endln:12:39 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/LhsHierPath/dut.sv, line:11:1, endln:17:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/LhsHierPath/dut.sv, line:11:1, endln:17:10 |vpiName:ast_alert_o |vpiFullName:work@top.ast_alert_o |vpiPort: \_port: (o), line:11:19, endln:11:20 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/LhsHierPath/dut.sv, line:11:1, endln:17:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/LhsHierPath/dut.sv, line:11:1, endln:17:10 |vpiName:o |vpiDirection:2 |vpiLowConn: @@ -404,7 +404,7 @@ design: (work@top) |vpiProcess: \_always: , line:13:4, endln:15:7 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/LhsHierPath/dut.sv, line:11:1, endln:17:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/LhsHierPath/dut.sv, line:11:1, endln:17:10 |vpiStmt: \_begin: (work@top), line:13:16, endln:15:7 |vpiParent: @@ -458,7 +458,7 @@ design: (work@top) |vpiContAssign: \_cont_assign: , line:16:11, endln:16:42 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/LhsHierPath/dut.sv, line:11:1, endln:17:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/LhsHierPath/dut.sv, line:11:1, endln:17:10 |vpiRhs: \_hier_path: (ast_alert_o.alerts_ack[0].p), line:16:15, endln:16:42 |vpiParent: @@ -496,12 +496,12 @@ design: (work@top) |vpiActual: \_logic_net: (work@top.o), line:11:19, endln:11:20 |uhdmtopModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/LhsHierPath/dut.sv, line:11:1, endln:17:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/LhsHierPath/dut.sv, line:11:1, endln:17:10 |vpiName:work@top |vpiVariables: \_struct_var: (work@top.ast_alert_o), line:12:28, endln:12:39 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/LhsHierPath/dut.sv, line:11:1, endln:17:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/LhsHierPath/dut.sv, line:11:1, endln:17:10 |vpiTypespec: \_struct_typespec: (my_pkg::ast_alert_rsp_t), line:6:12, endln:6:18 |vpiName:ast_alert_o @@ -512,7 +512,7 @@ design: (work@top) |vpiNet: \_logic_net: (work@top.o), line:11:19, endln:11:20 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/LhsHierPath/dut.sv, line:11:1, endln:17:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/LhsHierPath/dut.sv, line:11:1, endln:17:10 |vpiTypespec: \_logic_typespec: , line:11:19, endln:11:19 |vpiName:o @@ -521,7 +521,7 @@ design: (work@top) |vpiPort: \_port: (o), line:11:19, endln:11:20 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/LhsHierPath/dut.sv, line:11:1, endln:17:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/LhsHierPath/dut.sv, line:11:1, endln:17:10 |vpiName:o |vpiDirection:2 |vpiLowConn: @@ -535,11 +535,11 @@ design: (work@top) |vpiTypedef: \_logic_typespec: , line:11:19, endln:11:19 |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/LhsHierPath/dut.sv, line:11:1, endln:17:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/LhsHierPath/dut.sv, line:11:1, endln:17:10 |vpiProcess: \_always: , line:13:4, endln:15:7 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/LhsHierPath/dut.sv, line:11:1, endln:17:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/LhsHierPath/dut.sv, line:11:1, endln:17:10 |vpiStmt: \_begin: (work@top), line:13:16, endln:15:7 |vpiParent: @@ -591,7 +591,7 @@ design: (work@top) |vpiContAssign: \_cont_assign: , line:16:11, endln:16:42 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/LhsHierPath/dut.sv, line:11:1, endln:17:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/LhsHierPath/dut.sv, line:11:1, endln:17:10 |vpiRhs: \_hier_path: (ast_alert_o.alerts_ack[0].p), line:16:15, endln:16:42 |vpiParent: diff --git a/tests/LibraryIntercon/LibraryIntercon.log b/tests/LibraryIntercon/LibraryIntercon.log index b470cae699..ce8dfb4423 100644 --- a/tests/LibraryIntercon/LibraryIntercon.log +++ b/tests/LibraryIntercon/LibraryIntercon.log @@ -9,41 +9,41 @@ LIB: work ${SURELOG_DIR}/tests/LibraryIntercon/lib.map LIB: realLib - ${SURELOG_DIR}/tests/LibraryIntercon/cmp.svr ${SURELOG_DIR}/tests/LibraryIntercon/driver.svr + ${SURELOG_DIR}/tests/LibraryIntercon/cmp.svr LIB: logicLib - ${SURELOG_DIR}/tests/LibraryIntercon/driver.sv ${SURELOG_DIR}/tests/LibraryIntercon/cmp.sv ${SURELOG_DIR}/tests/LibraryIntercon/top.sv + ${SURELOG_DIR}/tests/LibraryIntercon/driver.sv [INF:PP0122] Preprocessing source file "${SURELOG_DIR}/tests/LibraryIntercon/nets.pkg". [INF:PP0122] Preprocessing source file "${SURELOG_DIR}/tests/LibraryIntercon/lib.map". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/tests/LibraryIntercon/cmp.svr". - [INF:PP0122] Preprocessing source file "${SURELOG_DIR}/tests/LibraryIntercon/driver.svr". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/tests/LibraryIntercon/driver.sv". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/tests/LibraryIntercon/cmp.svr". [INF:PP0122] Preprocessing source file "${SURELOG_DIR}/tests/LibraryIntercon/cmp.sv". [INF:PP0122] Preprocessing source file "${SURELOG_DIR}/tests/LibraryIntercon/top.sv". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/tests/LibraryIntercon/nets.pkg". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/tests/LibraryIntercon/driver.sv". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/tests/LibraryIntercon/cmp.svr". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/tests/LibraryIntercon/nets.pkg". [INF:PA0201] Parsing source file "${SURELOG_DIR}/tests/LibraryIntercon/driver.svr". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/tests/LibraryIntercon/driver.sv". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/tests/LibraryIntercon/cmp.svr". [INF:PA0201] Parsing source file "${SURELOG_DIR}/tests/LibraryIntercon/cmp.sv". [INF:PA0201] Parsing source file "${SURELOG_DIR}/tests/LibraryIntercon/top.sv". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/tests/LibraryIntercon/driver.sv". + [WRN:PA0205] ${SURELOG_DIR}/tests/LibraryIntercon/nets.pkg:1:1: No timescale set for "NetsPkg". [WRN:PA0205] ${SURELOG_DIR}/tests/LibraryIntercon/cmp.sv:2:1: No timescale set for "cmp". @@ -184,8 +184,8 @@ io_decl 11 logic_net 22 logic_typespec 23 logic_var 10 -module 29 module_array 3 +module_inst 29 module_typespec 3 operation 11 package 5 diff --git a/tests/LocalParam/LocalParam.log b/tests/LocalParam/LocalParam.log index 300b1cc3bb..0055cb41f0 100644 --- a/tests/LocalParam/LocalParam.log +++ b/tests/LocalParam/LocalParam.log @@ -515,7 +515,7 @@ io_decl 11 logic_net 12 logic_typespec 19 logic_var 1 -module 10 +module_inst 10 operation 4 package 2 param_assign 6 @@ -545,7 +545,7 @@ io_decl 22 logic_net 12 logic_typespec 19 logic_var 1 -module 10 +module_inst 10 operation 5 package 2 param_assign 6 @@ -1042,14 +1042,14 @@ design: (work@top) \_int_typespec: |vpiSigned:1 |uhdmallModules: -\_module: work@assigner (work@assigner), file:${SURELOG_DIR}/tests/LocalParam/dut.sv, line:6:1, endln:12:10 +\_module_inst: work@assigner (work@assigner), file:${SURELOG_DIR}/tests/LocalParam/dut.sv, line:6:1, endln:12:10 |vpiParent: \_design: (work@top) |vpiFullName:work@assigner |vpiParameter: \_parameter: (work@assigner.invert), line:6:29, endln:6:35 |vpiParent: - \_module: work@assigner (work@assigner), file:${SURELOG_DIR}/tests/LocalParam/dut.sv, line:6:1, endln:12:10 + \_module_inst: work@assigner (work@assigner), file:${SURELOG_DIR}/tests/LocalParam/dut.sv, line:6:1, endln:12:10 |UINT:0 |vpiTypespec: \_int_typespec: @@ -1058,7 +1058,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@assigner.do_invert), line:7:17, endln:7:26 |vpiParent: - \_module: work@assigner (work@assigner), file:${SURELOG_DIR}/tests/LocalParam/dut.sv, line:6:1, endln:12:10 + \_module_inst: work@assigner (work@assigner), file:${SURELOG_DIR}/tests/LocalParam/dut.sv, line:6:1, endln:12:10 |UINT:0 |vpiTypespec: \_int_typespec: , line:7:13, endln:7:16 @@ -1072,7 +1072,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:6:29, endln:6:39 |vpiParent: - \_module: work@assigner (work@assigner), file:${SURELOG_DIR}/tests/LocalParam/dut.sv, line:6:1, endln:12:10 + \_module_inst: work@assigner (work@assigner), file:${SURELOG_DIR}/tests/LocalParam/dut.sv, line:6:1, endln:12:10 |vpiRhs: \_constant: , line:6:38, endln:6:39 |vpiDecompile:0 @@ -1086,7 +1086,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:7:17, endln:7:30 |vpiParent: - \_module: work@assigner (work@assigner), file:${SURELOG_DIR}/tests/LocalParam/dut.sv, line:6:1, endln:12:10 + \_module_inst: work@assigner (work@assigner), file:${SURELOG_DIR}/tests/LocalParam/dut.sv, line:6:1, endln:12:10 |vpiRhs: \_constant: , line:7:29, endln:7:30 |vpiDecompile:0 @@ -1101,21 +1101,21 @@ design: (work@top) |vpiNet: \_logic_net: (work@assigner.inp), line:6:53, endln:6:56 |vpiParent: - \_module: work@assigner (work@assigner), file:${SURELOG_DIR}/tests/LocalParam/dut.sv, line:6:1, endln:12:10 + \_module_inst: work@assigner (work@assigner), file:${SURELOG_DIR}/tests/LocalParam/dut.sv, line:6:1, endln:12:10 |vpiName:inp |vpiFullName:work@assigner.inp |vpiNetType:1 |vpiNet: \_logic_net: (work@assigner.out), line:6:69, endln:6:72 |vpiParent: - \_module: work@assigner (work@assigner), file:${SURELOG_DIR}/tests/LocalParam/dut.sv, line:6:1, endln:12:10 + \_module_inst: work@assigner (work@assigner), file:${SURELOG_DIR}/tests/LocalParam/dut.sv, line:6:1, endln:12:10 |vpiName:out |vpiFullName:work@assigner.out |vpiNetType:48 |vpiPort: \_port: (inp), line:6:53, endln:6:56 |vpiParent: - \_module: work@assigner (work@assigner), file:${SURELOG_DIR}/tests/LocalParam/dut.sv, line:6:1, endln:12:10 + \_module_inst: work@assigner (work@assigner), file:${SURELOG_DIR}/tests/LocalParam/dut.sv, line:6:1, endln:12:10 |vpiName:inp |vpiDirection:1 |vpiLowConn: @@ -1127,7 +1127,7 @@ design: (work@top) |vpiPort: \_port: (out), line:6:69, endln:6:72 |vpiParent: - \_module: work@assigner (work@assigner), file:${SURELOG_DIR}/tests/LocalParam/dut.sv, line:6:1, endln:12:10 + \_module_inst: work@assigner (work@assigner), file:${SURELOG_DIR}/tests/LocalParam/dut.sv, line:6:1, endln:12:10 |vpiName:out |vpiDirection:2 |vpiLowConn: @@ -1137,7 +1137,7 @@ design: (work@top) |vpiTypedef: \_logic_typespec: , line:6:65, endln:6:68 |uhdmallModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/LocalParam/dut.sv, line:1:1, endln:4:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/LocalParam/dut.sv, line:1:1, endln:4:10 |vpiParent: \_design: (work@top) |vpiFullName:work@top @@ -1145,28 +1145,28 @@ design: (work@top) |vpiNet: \_logic_net: (work@top.i), line:1:24, endln:1:25 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/LocalParam/dut.sv, line:1:1, endln:4:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/LocalParam/dut.sv, line:1:1, endln:4:10 |vpiName:i |vpiFullName:work@top.i |vpiNetType:1 |vpiNet: \_logic_net: (work@top.o1), line:1:38, endln:1:40 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/LocalParam/dut.sv, line:1:1, endln:4:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/LocalParam/dut.sv, line:1:1, endln:4:10 |vpiName:o1 |vpiFullName:work@top.o1 |vpiNetType:48 |vpiNet: \_logic_net: (work@top.o2), line:1:53, endln:1:55 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/LocalParam/dut.sv, line:1:1, endln:4:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/LocalParam/dut.sv, line:1:1, endln:4:10 |vpiName:o2 |vpiFullName:work@top.o2 |vpiNetType:48 |vpiPort: \_port: (i), line:1:24, endln:1:25 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/LocalParam/dut.sv, line:1:1, endln:4:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/LocalParam/dut.sv, line:1:1, endln:4:10 |vpiName:i |vpiDirection:1 |vpiLowConn: @@ -1178,7 +1178,7 @@ design: (work@top) |vpiPort: \_port: (o1), line:1:38, endln:1:40 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/LocalParam/dut.sv, line:1:1, endln:4:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/LocalParam/dut.sv, line:1:1, endln:4:10 |vpiName:o1 |vpiDirection:2 |vpiLowConn: @@ -1190,7 +1190,7 @@ design: (work@top) |vpiPort: \_port: (o2), line:1:53, endln:1:55 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/LocalParam/dut.sv, line:1:1, endln:4:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/LocalParam/dut.sv, line:1:1, endln:4:10 |vpiName:o2 |vpiDirection:2 |vpiLowConn: @@ -1200,14 +1200,14 @@ design: (work@top) |vpiTypedef: \_logic_typespec: , line:1:49, endln:1:52 |uhdmtopModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/LocalParam/dut.sv, line:1:1, endln:4:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/LocalParam/dut.sv, line:1:1, endln:4:10 |vpiName:work@top |vpiDefName:work@top |vpiTop:1 |vpiNet: \_logic_net: (work@top.i), line:1:24, endln:1:25 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/LocalParam/dut.sv, line:1:1, endln:4:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/LocalParam/dut.sv, line:1:1, endln:4:10 |vpiTypespec: \_logic_typespec: , line:1:19, endln:1:23 |vpiName:i @@ -1216,7 +1216,7 @@ design: (work@top) |vpiNet: \_logic_net: (work@top.o1), line:1:38, endln:1:40 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/LocalParam/dut.sv, line:1:1, endln:4:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/LocalParam/dut.sv, line:1:1, endln:4:10 |vpiTypespec: \_logic_typespec: , line:1:34, endln:1:37 |vpiName:o1 @@ -1225,7 +1225,7 @@ design: (work@top) |vpiNet: \_logic_net: (work@top.o2), line:1:53, endln:1:55 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/LocalParam/dut.sv, line:1:1, endln:4:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/LocalParam/dut.sv, line:1:1, endln:4:10 |vpiTypespec: \_logic_typespec: , line:1:49, endln:1:52 |vpiName:o2 @@ -1235,7 +1235,7 @@ design: (work@top) |vpiPort: \_port: (i), line:1:24, endln:1:25 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/LocalParam/dut.sv, line:1:1, endln:4:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/LocalParam/dut.sv, line:1:1, endln:4:10 |vpiName:i |vpiDirection:1 |vpiLowConn: @@ -1249,11 +1249,11 @@ design: (work@top) |vpiTypedef: \_logic_typespec: , line:1:19, endln:1:23 |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/LocalParam/dut.sv, line:1:1, endln:4:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/LocalParam/dut.sv, line:1:1, endln:4:10 |vpiPort: \_port: (o1), line:1:38, endln:1:40 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/LocalParam/dut.sv, line:1:1, endln:4:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/LocalParam/dut.sv, line:1:1, endln:4:10 |vpiName:o1 |vpiDirection:2 |vpiLowConn: @@ -1267,11 +1267,11 @@ design: (work@top) |vpiTypedef: \_logic_typespec: , line:1:34, endln:1:37 |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/LocalParam/dut.sv, line:1:1, endln:4:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/LocalParam/dut.sv, line:1:1, endln:4:10 |vpiPort: \_port: (o2), line:1:53, endln:1:55 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/LocalParam/dut.sv, line:1:1, endln:4:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/LocalParam/dut.sv, line:1:1, endln:4:10 |vpiName:o2 |vpiDirection:2 |vpiLowConn: @@ -1285,17 +1285,17 @@ design: (work@top) |vpiTypedef: \_logic_typespec: , line:1:49, endln:1:52 |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/LocalParam/dut.sv, line:1:1, endln:4:10 - |vpiModule: - \_module: work@assigner (work@top.asgn0), file:${SURELOG_DIR}/tests/LocalParam/dut.sv, line:2:3, endln:2:51 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/LocalParam/dut.sv, line:1:1, endln:4:10 + |vpiModuleInst: + \_module_inst: work@assigner (work@top.asgn0), file:${SURELOG_DIR}/tests/LocalParam/dut.sv, line:2:3, endln:2:51 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/LocalParam/dut.sv, line:1:1, endln:4:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/LocalParam/dut.sv, line:1:1, endln:4:10 |vpiName:asgn0 |vpiFullName:work@top.asgn0 |vpiParameter: \_parameter: (work@top.asgn0.invert), line:6:29, endln:6:35 |vpiParent: - \_module: work@assigner (work@top.asgn0), file:${SURELOG_DIR}/tests/LocalParam/dut.sv, line:2:3, endln:2:51 + \_module_inst: work@assigner (work@top.asgn0), file:${SURELOG_DIR}/tests/LocalParam/dut.sv, line:2:3, endln:2:51 |UINT:0 |vpiTypespec: \_int_typespec: @@ -1306,7 +1306,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.asgn0.do_invert), line:7:17, endln:7:26 |vpiParent: - \_module: work@assigner (work@top.asgn0), file:${SURELOG_DIR}/tests/LocalParam/dut.sv, line:2:3, endln:2:51 + \_module_inst: work@assigner (work@top.asgn0), file:${SURELOG_DIR}/tests/LocalParam/dut.sv, line:2:3, endln:2:51 |UINT:0 |vpiTypespec: \_int_typespec: , line:7:13, endln:7:16 @@ -1320,7 +1320,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:6:29, endln:6:39 |vpiParent: - \_module: work@assigner (work@top.asgn0), file:${SURELOG_DIR}/tests/LocalParam/dut.sv, line:2:3, endln:2:51 + \_module_inst: work@assigner (work@top.asgn0), file:${SURELOG_DIR}/tests/LocalParam/dut.sv, line:2:3, endln:2:51 |vpiOverriden:1 |vpiRhs: \_constant: , line:6:38, endln:6:39 @@ -1335,7 +1335,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:7:17, endln:7:30 |vpiParent: - \_module: work@assigner (work@top.asgn0), file:${SURELOG_DIR}/tests/LocalParam/dut.sv, line:2:3, endln:2:51 + \_module_inst: work@assigner (work@top.asgn0), file:${SURELOG_DIR}/tests/LocalParam/dut.sv, line:2:3, endln:2:51 |vpiRhs: \_constant: , line:7:29, endln:7:30 |vpiDecompile:0 @@ -1352,7 +1352,7 @@ design: (work@top) |vpiNet: \_logic_net: (work@top.asgn0.inp), line:6:53, endln:6:56 |vpiParent: - \_module: work@assigner (work@top.asgn0), file:${SURELOG_DIR}/tests/LocalParam/dut.sv, line:2:3, endln:2:51 + \_module_inst: work@assigner (work@top.asgn0), file:${SURELOG_DIR}/tests/LocalParam/dut.sv, line:2:3, endln:2:51 |vpiTypespec: \_logic_typespec: , line:6:48, endln:6:52 |vpiName:inp @@ -1361,18 +1361,18 @@ design: (work@top) |vpiNet: \_logic_net: (work@top.asgn0.out), line:6:69, endln:6:72 |vpiParent: - \_module: work@assigner (work@top.asgn0), file:${SURELOG_DIR}/tests/LocalParam/dut.sv, line:2:3, endln:2:51 + \_module_inst: work@assigner (work@top.asgn0), file:${SURELOG_DIR}/tests/LocalParam/dut.sv, line:2:3, endln:2:51 |vpiTypespec: \_logic_typespec: , line:6:65, endln:6:68 |vpiName:out |vpiFullName:work@top.asgn0.out |vpiNetType:48 |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/LocalParam/dut.sv, line:1:1, endln:4:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/LocalParam/dut.sv, line:1:1, endln:4:10 |vpiPort: \_port: (inp), line:6:53, endln:6:56 |vpiParent: - \_module: work@assigner (work@top.asgn0), file:${SURELOG_DIR}/tests/LocalParam/dut.sv, line:2:3, endln:2:51 + \_module_inst: work@assigner (work@top.asgn0), file:${SURELOG_DIR}/tests/LocalParam/dut.sv, line:2:3, endln:2:51 |vpiName:inp |vpiDirection:1 |vpiHighConn: @@ -1394,11 +1394,11 @@ design: (work@top) |vpiTypedef: \_logic_typespec: , line:6:48, endln:6:52 |vpiInstance: - \_module: work@assigner (work@top.asgn0), file:${SURELOG_DIR}/tests/LocalParam/dut.sv, line:2:3, endln:2:51 + \_module_inst: work@assigner (work@top.asgn0), file:${SURELOG_DIR}/tests/LocalParam/dut.sv, line:2:3, endln:2:51 |vpiPort: \_port: (out), line:6:69, endln:6:72 |vpiParent: - \_module: work@assigner (work@top.asgn0), file:${SURELOG_DIR}/tests/LocalParam/dut.sv, line:2:3, endln:2:51 + \_module_inst: work@assigner (work@top.asgn0), file:${SURELOG_DIR}/tests/LocalParam/dut.sv, line:2:3, endln:2:51 |vpiName:out |vpiDirection:2 |vpiHighConn: @@ -1420,11 +1420,11 @@ design: (work@top) |vpiTypedef: \_logic_typespec: , line:6:65, endln:6:68 |vpiInstance: - \_module: work@assigner (work@top.asgn0), file:${SURELOG_DIR}/tests/LocalParam/dut.sv, line:2:3, endln:2:51 + \_module_inst: work@assigner (work@top.asgn0), file:${SURELOG_DIR}/tests/LocalParam/dut.sv, line:2:3, endln:2:51 |vpiGenScopeArray: \_gen_scope_array: (work@top.asgn0.genblk1), line:8:2, endln:9:21 |vpiParent: - \_module: work@assigner (work@top.asgn0), file:${SURELOG_DIR}/tests/LocalParam/dut.sv, line:2:3, endln:2:51 + \_module_inst: work@assigner (work@top.asgn0), file:${SURELOG_DIR}/tests/LocalParam/dut.sv, line:2:3, endln:2:51 |vpiName:genblk1 |vpiFullName:work@top.asgn0.genblk1 |vpiGenScope: @@ -1452,16 +1452,16 @@ design: (work@top) |vpiFullName:work@top.asgn0.genblk1.out |vpiActual: \_logic_net: (work@top.asgn0.out), line:6:69, endln:6:72 - |vpiModule: - \_module: work@assigner (work@top.asgn1), file:${SURELOG_DIR}/tests/LocalParam/dut.sv, line:3:3, endln:3:51 + |vpiModuleInst: + \_module_inst: work@assigner (work@top.asgn1), file:${SURELOG_DIR}/tests/LocalParam/dut.sv, line:3:3, endln:3:51 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/LocalParam/dut.sv, line:1:1, endln:4:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/LocalParam/dut.sv, line:1:1, endln:4:10 |vpiName:asgn1 |vpiFullName:work@top.asgn1 |vpiParameter: \_parameter: (work@top.asgn1.invert), line:6:29, endln:6:35 |vpiParent: - \_module: work@assigner (work@top.asgn1), file:${SURELOG_DIR}/tests/LocalParam/dut.sv, line:3:3, endln:3:51 + \_module_inst: work@assigner (work@top.asgn1), file:${SURELOG_DIR}/tests/LocalParam/dut.sv, line:3:3, endln:3:51 |UINT:0 |vpiTypespec: \_int_typespec: @@ -1472,7 +1472,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.asgn1.do_invert), line:7:17, endln:7:26 |vpiParent: - \_module: work@assigner (work@top.asgn1), file:${SURELOG_DIR}/tests/LocalParam/dut.sv, line:3:3, endln:3:51 + \_module_inst: work@assigner (work@top.asgn1), file:${SURELOG_DIR}/tests/LocalParam/dut.sv, line:3:3, endln:3:51 |UINT:0 |vpiTypespec: \_int_typespec: , line:7:13, endln:7:16 @@ -1486,7 +1486,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:6:29, endln:6:39 |vpiParent: - \_module: work@assigner (work@top.asgn1), file:${SURELOG_DIR}/tests/LocalParam/dut.sv, line:3:3, endln:3:51 + \_module_inst: work@assigner (work@top.asgn1), file:${SURELOG_DIR}/tests/LocalParam/dut.sv, line:3:3, endln:3:51 |vpiOverriden:1 |vpiRhs: \_constant: , line:6:38, endln:6:39 @@ -1501,7 +1501,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:7:17, endln:7:30 |vpiParent: - \_module: work@assigner (work@top.asgn1), file:${SURELOG_DIR}/tests/LocalParam/dut.sv, line:3:3, endln:3:51 + \_module_inst: work@assigner (work@top.asgn1), file:${SURELOG_DIR}/tests/LocalParam/dut.sv, line:3:3, endln:3:51 |vpiRhs: \_constant: , line:7:29, endln:7:30 |vpiDecompile:0 @@ -1518,7 +1518,7 @@ design: (work@top) |vpiNet: \_logic_net: (work@top.asgn1.inp), line:6:53, endln:6:56 |vpiParent: - \_module: work@assigner (work@top.asgn1), file:${SURELOG_DIR}/tests/LocalParam/dut.sv, line:3:3, endln:3:51 + \_module_inst: work@assigner (work@top.asgn1), file:${SURELOG_DIR}/tests/LocalParam/dut.sv, line:3:3, endln:3:51 |vpiTypespec: \_logic_typespec: , line:6:48, endln:6:52 |vpiName:inp @@ -1527,18 +1527,18 @@ design: (work@top) |vpiNet: \_logic_net: (work@top.asgn1.out), line:6:69, endln:6:72 |vpiParent: - \_module: work@assigner (work@top.asgn1), file:${SURELOG_DIR}/tests/LocalParam/dut.sv, line:3:3, endln:3:51 + \_module_inst: work@assigner (work@top.asgn1), file:${SURELOG_DIR}/tests/LocalParam/dut.sv, line:3:3, endln:3:51 |vpiTypespec: \_logic_typespec: , line:6:65, endln:6:68 |vpiName:out |vpiFullName:work@top.asgn1.out |vpiNetType:48 |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/LocalParam/dut.sv, line:1:1, endln:4:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/LocalParam/dut.sv, line:1:1, endln:4:10 |vpiPort: \_port: (inp), line:6:53, endln:6:56 |vpiParent: - \_module: work@assigner (work@top.asgn1), file:${SURELOG_DIR}/tests/LocalParam/dut.sv, line:3:3, endln:3:51 + \_module_inst: work@assigner (work@top.asgn1), file:${SURELOG_DIR}/tests/LocalParam/dut.sv, line:3:3, endln:3:51 |vpiName:inp |vpiDirection:1 |vpiHighConn: @@ -1560,11 +1560,11 @@ design: (work@top) |vpiTypedef: \_logic_typespec: , line:6:48, endln:6:52 |vpiInstance: - \_module: work@assigner (work@top.asgn1), file:${SURELOG_DIR}/tests/LocalParam/dut.sv, line:3:3, endln:3:51 + \_module_inst: work@assigner (work@top.asgn1), file:${SURELOG_DIR}/tests/LocalParam/dut.sv, line:3:3, endln:3:51 |vpiPort: \_port: (out), line:6:69, endln:6:72 |vpiParent: - \_module: work@assigner (work@top.asgn1), file:${SURELOG_DIR}/tests/LocalParam/dut.sv, line:3:3, endln:3:51 + \_module_inst: work@assigner (work@top.asgn1), file:${SURELOG_DIR}/tests/LocalParam/dut.sv, line:3:3, endln:3:51 |vpiName:out |vpiDirection:2 |vpiHighConn: @@ -1586,11 +1586,11 @@ design: (work@top) |vpiTypedef: \_logic_typespec: , line:6:65, endln:6:68 |vpiInstance: - \_module: work@assigner (work@top.asgn1), file:${SURELOG_DIR}/tests/LocalParam/dut.sv, line:3:3, endln:3:51 + \_module_inst: work@assigner (work@top.asgn1), file:${SURELOG_DIR}/tests/LocalParam/dut.sv, line:3:3, endln:3:51 |vpiGenScopeArray: \_gen_scope_array: (work@top.asgn1.genblk2), line:10:2, endln:11:22 |vpiParent: - \_module: work@assigner (work@top.asgn1), file:${SURELOG_DIR}/tests/LocalParam/dut.sv, line:3:3, endln:3:51 + \_module_inst: work@assigner (work@top.asgn1), file:${SURELOG_DIR}/tests/LocalParam/dut.sv, line:3:3, endln:3:51 |vpiName:genblk2 |vpiFullName:work@top.asgn1.genblk2 |vpiGenScope: diff --git a/tests/LocalScopeAssign/LocalScopeAssign.log b/tests/LocalScopeAssign/LocalScopeAssign.log index 80ab70df98..a0ef506a57 100644 --- a/tests/LocalScopeAssign/LocalScopeAssign.log +++ b/tests/LocalScopeAssign/LocalScopeAssign.log @@ -93,7 +93,7 @@ design 1 hier_path 1 logic_net 4 logic_typespec 4 -module 4 +module_inst 4 port 4 range 6 ref_obj 7 @@ -107,7 +107,7 @@ design 1 hier_path 2 logic_net 4 logic_typespec 4 -module 4 +module_inst 4 port 6 range 6 ref_obj 12 @@ -125,7 +125,7 @@ design: (work@module_scope_Example) |vpiElaborated:1 |vpiName:work@module_scope_Example |uhdmallModules: -\_module: work@module_scope_Example (work@module_scope_Example), file:${SURELOG_DIR}/tests/LocalScopeAssign/dut.sv, line:3:1, endln:8:10 +\_module_inst: work@module_scope_Example (work@module_scope_Example), file:${SURELOG_DIR}/tests/LocalScopeAssign/dut.sv, line:3:1, endln:8:10 |vpiParent: \_design: (work@module_scope_Example) |vpiFullName:work@module_scope_Example @@ -133,21 +133,21 @@ design: (work@module_scope_Example) |vpiNet: \_logic_net: (work@module_scope_Example.o1), line:3:29, endln:3:31 |vpiParent: - \_module: work@module_scope_Example (work@module_scope_Example), file:${SURELOG_DIR}/tests/LocalScopeAssign/dut.sv, line:3:1, endln:8:10 + \_module_inst: work@module_scope_Example (work@module_scope_Example), file:${SURELOG_DIR}/tests/LocalScopeAssign/dut.sv, line:3:1, endln:8:10 |vpiName:o1 |vpiFullName:work@module_scope_Example.o1 |vpiNetType:1 |vpiNet: \_logic_net: (work@module_scope_Example.o2), line:3:33, endln:3:35 |vpiParent: - \_module: work@module_scope_Example (work@module_scope_Example), file:${SURELOG_DIR}/tests/LocalScopeAssign/dut.sv, line:3:1, endln:8:10 + \_module_inst: work@module_scope_Example (work@module_scope_Example), file:${SURELOG_DIR}/tests/LocalScopeAssign/dut.sv, line:3:1, endln:8:10 |vpiName:o2 |vpiFullName:work@module_scope_Example.o2 |vpiNetType:1 |vpiPort: \_port: (o1), line:3:29, endln:3:31 |vpiParent: - \_module: work@module_scope_Example (work@module_scope_Example), file:${SURELOG_DIR}/tests/LocalScopeAssign/dut.sv, line:3:1, endln:8:10 + \_module_inst: work@module_scope_Example (work@module_scope_Example), file:${SURELOG_DIR}/tests/LocalScopeAssign/dut.sv, line:3:1, endln:8:10 |vpiName:o1 |vpiDirection:2 |vpiLowConn: @@ -177,7 +177,7 @@ design: (work@module_scope_Example) |vpiPort: \_port: (o2), line:3:33, endln:3:35 |vpiParent: - \_module: work@module_scope_Example (work@module_scope_Example), file:${SURELOG_DIR}/tests/LocalScopeAssign/dut.sv, line:3:1, endln:8:10 + \_module_inst: work@module_scope_Example (work@module_scope_Example), file:${SURELOG_DIR}/tests/LocalScopeAssign/dut.sv, line:3:1, endln:8:10 |vpiName:o2 |vpiDirection:2 |vpiLowConn: @@ -207,7 +207,7 @@ design: (work@module_scope_Example) |vpiContAssign: \_cont_assign: , line:7:11, endln:7:39 |vpiParent: - \_module: work@module_scope_Example (work@module_scope_Example), file:${SURELOG_DIR}/tests/LocalScopeAssign/dut.sv, line:3:1, endln:8:10 + \_module_inst: work@module_scope_Example (work@module_scope_Example), file:${SURELOG_DIR}/tests/LocalScopeAssign/dut.sv, line:3:1, endln:8:10 |vpiRhs: \_ref_obj: (work@module_scope_Example.v2), line:7:37, endln:7:39 |vpiParent: @@ -228,14 +228,14 @@ design: (work@module_scope_Example) \_ref_obj: (o2) |vpiName:o2 |uhdmtopModules: -\_module: work@module_scope_Example (work@module_scope_Example), file:${SURELOG_DIR}/tests/LocalScopeAssign/dut.sv, line:3:1, endln:8:10 +\_module_inst: work@module_scope_Example (work@module_scope_Example), file:${SURELOG_DIR}/tests/LocalScopeAssign/dut.sv, line:3:1, endln:8:10 |vpiName:work@module_scope_Example |vpiDefName:work@module_scope_Example |vpiTop:1 |vpiNet: \_logic_net: (work@module_scope_Example.o1), line:3:29, endln:3:31 |vpiParent: - \_module: work@module_scope_Example (work@module_scope_Example), file:${SURELOG_DIR}/tests/LocalScopeAssign/dut.sv, line:3:1, endln:8:10 + \_module_inst: work@module_scope_Example (work@module_scope_Example), file:${SURELOG_DIR}/tests/LocalScopeAssign/dut.sv, line:3:1, endln:8:10 |vpiTypespec: \_logic_typespec: , line:4:11, endln:4:22 |vpiRange: @@ -262,7 +262,7 @@ design: (work@module_scope_Example) |vpiNet: \_logic_net: (work@module_scope_Example.o2), line:3:33, endln:3:35 |vpiParent: - \_module: work@module_scope_Example (work@module_scope_Example), file:${SURELOG_DIR}/tests/LocalScopeAssign/dut.sv, line:3:1, endln:8:10 + \_module_inst: work@module_scope_Example (work@module_scope_Example), file:${SURELOG_DIR}/tests/LocalScopeAssign/dut.sv, line:3:1, endln:8:10 |vpiTypespec: \_logic_typespec: , line:4:11, endln:4:22 |vpiName:o2 @@ -272,7 +272,7 @@ design: (work@module_scope_Example) |vpiPort: \_port: (o1), line:3:29, endln:3:31 |vpiParent: - \_module: work@module_scope_Example (work@module_scope_Example), file:${SURELOG_DIR}/tests/LocalScopeAssign/dut.sv, line:3:1, endln:8:10 + \_module_inst: work@module_scope_Example (work@module_scope_Example), file:${SURELOG_DIR}/tests/LocalScopeAssign/dut.sv, line:3:1, endln:8:10 |vpiName:o1 |vpiDirection:2 |vpiLowConn: @@ -306,11 +306,11 @@ design: (work@module_scope_Example) |UINT:0 |vpiConstType:9 |vpiInstance: - \_module: work@module_scope_Example (work@module_scope_Example), file:${SURELOG_DIR}/tests/LocalScopeAssign/dut.sv, line:3:1, endln:8:10 + \_module_inst: work@module_scope_Example (work@module_scope_Example), file:${SURELOG_DIR}/tests/LocalScopeAssign/dut.sv, line:3:1, endln:8:10 |vpiPort: \_port: (o2), line:3:33, endln:3:35 |vpiParent: - \_module: work@module_scope_Example (work@module_scope_Example), file:${SURELOG_DIR}/tests/LocalScopeAssign/dut.sv, line:3:1, endln:8:10 + \_module_inst: work@module_scope_Example (work@module_scope_Example), file:${SURELOG_DIR}/tests/LocalScopeAssign/dut.sv, line:3:1, endln:8:10 |vpiName:o2 |vpiDirection:2 |vpiLowConn: @@ -324,11 +324,11 @@ design: (work@module_scope_Example) |vpiTypedef: \_logic_typespec: , line:4:11, endln:4:22 |vpiInstance: - \_module: work@module_scope_Example (work@module_scope_Example), file:${SURELOG_DIR}/tests/LocalScopeAssign/dut.sv, line:3:1, endln:8:10 + \_module_inst: work@module_scope_Example (work@module_scope_Example), file:${SURELOG_DIR}/tests/LocalScopeAssign/dut.sv, line:3:1, endln:8:10 |vpiContAssign: \_cont_assign: , line:7:11, endln:7:39 |vpiParent: - \_module: work@module_scope_Example (work@module_scope_Example), file:${SURELOG_DIR}/tests/LocalScopeAssign/dut.sv, line:3:1, endln:8:10 + \_module_inst: work@module_scope_Example (work@module_scope_Example), file:${SURELOG_DIR}/tests/LocalScopeAssign/dut.sv, line:3:1, endln:8:10 |vpiRhs: \_ref_obj: (work@module_scope_Example.v2), line:7:37, endln:7:39 |vpiParent: @@ -346,7 +346,7 @@ design: (work@module_scope_Example) \_hier_path: (module_scope_Example.o2), line:7:11, endln:7:34 |vpiName:module_scope_Example |vpiActual: - \_module: work@module_scope_Example (work@module_scope_Example), file:${SURELOG_DIR}/tests/LocalScopeAssign/dut.sv, line:3:1, endln:8:10 + \_module_inst: work@module_scope_Example (work@module_scope_Example), file:${SURELOG_DIR}/tests/LocalScopeAssign/dut.sv, line:3:1, endln:8:10 |vpiActual: \_ref_obj: (o2) |vpiParent: diff --git a/tests/LocalVarTypespec/LocalVarTypespec.log b/tests/LocalVarTypespec/LocalVarTypespec.log index 4bc3cc4331..1cc4bcd517 100644 --- a/tests/LocalVarTypespec/LocalVarTypespec.log +++ b/tests/LocalVarTypespec/LocalVarTypespec.log @@ -146,7 +146,7 @@ design 1 function 1 logic_typespec 7 logic_var 4 -module 2 +module_inst 2 operation 9 range 9 === UHDM Object Stats End === @@ -158,7 +158,7 @@ design 1 function 2 logic_typespec 7 logic_var 7 -module 2 +module_inst 2 operation 9 range 9 === UHDM Object Stats End === @@ -175,7 +175,7 @@ design: (work@shift) |vpiElaborated:1 |vpiName:work@shift |uhdmallModules: -\_module: work@shift (work@shift), file:${SURELOG_DIR}/tests/LocalVarTypespec/dut.sv, line:1:1, endln:7:10 +\_module_inst: work@shift (work@shift), file:${SURELOG_DIR}/tests/LocalVarTypespec/dut.sv, line:1:1, endln:7:10 |vpiParent: \_design: (work@shift) |vpiFullName:work@shift @@ -183,7 +183,7 @@ design: (work@shift) |vpiTaskFunc: \_function: (work@shift.fshr_u), line:2:1, endln:6:12 |vpiParent: - \_module: work@shift (work@shift), file:${SURELOG_DIR}/tests/LocalVarTypespec/dut.sv, line:1:1, endln:7:10 + \_module_inst: work@shift (work@shift), file:${SURELOG_DIR}/tests/LocalVarTypespec/dut.sv, line:1:1, endln:7:10 |vpiName:fshr_u |vpiFullName:work@shift.fshr_u |vpiVariables: @@ -341,18 +341,18 @@ design: (work@shift) |UINT:0 |vpiConstType:9 |vpiParent: - \_module: work@shift (work@shift), file:${SURELOG_DIR}/tests/LocalVarTypespec/dut.sv, line:1:1, endln:7:10 + \_module_inst: work@shift (work@shift), file:${SURELOG_DIR}/tests/LocalVarTypespec/dut.sv, line:1:1, endln:7:10 |vpiInstance: - \_module: work@shift (work@shift), file:${SURELOG_DIR}/tests/LocalVarTypespec/dut.sv, line:1:1, endln:7:10 + \_module_inst: work@shift (work@shift), file:${SURELOG_DIR}/tests/LocalVarTypespec/dut.sv, line:1:1, endln:7:10 |uhdmtopModules: -\_module: work@shift (work@shift), file:${SURELOG_DIR}/tests/LocalVarTypespec/dut.sv, line:1:1, endln:7:10 +\_module_inst: work@shift (work@shift), file:${SURELOG_DIR}/tests/LocalVarTypespec/dut.sv, line:1:1, endln:7:10 |vpiName:work@shift |vpiDefName:work@shift |vpiTop:1 |vpiTaskFunc: \_function: (work@shift.fshr_u), line:2:1, endln:6:12 |vpiParent: - \_module: work@shift (work@shift), file:${SURELOG_DIR}/tests/LocalVarTypespec/dut.sv, line:1:1, endln:7:10 + \_module_inst: work@shift (work@shift), file:${SURELOG_DIR}/tests/LocalVarTypespec/dut.sv, line:1:1, endln:7:10 |vpiName:fshr_u |vpiFullName:work@shift.fshr_u |vpiVariables: @@ -386,9 +386,9 @@ design: (work@shift) |vpiReturn: \_logic_var: , line:2:10, endln:2:23 |vpiParent: - \_module: work@shift (work@shift), file:${SURELOG_DIR}/tests/LocalVarTypespec/dut.sv, line:1:1, endln:7:10 + \_module_inst: work@shift (work@shift), file:${SURELOG_DIR}/tests/LocalVarTypespec/dut.sv, line:1:1, endln:7:10 |vpiInstance: - \_module: work@shift (work@shift), file:${SURELOG_DIR}/tests/LocalVarTypespec/dut.sv, line:1:1, endln:7:10 + \_module_inst: work@shift (work@shift), file:${SURELOG_DIR}/tests/LocalVarTypespec/dut.sv, line:1:1, endln:7:10 |vpiTopModule:1 =================== [ FATAL] : 0 diff --git a/tests/LogicCast/LogicCast.log b/tests/LogicCast/LogicCast.log index 85ac00fe49..0027d88251 100644 --- a/tests/LogicCast/LogicCast.log +++ b/tests/LogicCast/LogicCast.log @@ -364,7 +364,7 @@ io_decl 11 logic_net 2 logic_typespec 1 logic_var 1 -module 2 +module_inst 2 named_begin 1 operation 4 package 2 @@ -393,7 +393,7 @@ io_decl 22 logic_net 2 logic_typespec 1 logic_var 1 -module 2 +module_inst 2 named_begin 2 operation 8 package 2 @@ -890,7 +890,7 @@ design: (work@top) \_int_typespec: |vpiSigned:1 |uhdmallModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/LogicCast/dut.sv, line:1:1, endln:5:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/LogicCast/dut.sv, line:1:1, endln:5:10 |vpiParent: \_design: (work@top) |vpiFullName:work@top @@ -898,7 +898,7 @@ design: (work@top) |vpiProcess: \_always: , line:2:3, endln:4:6 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/LogicCast/dut.sv, line:1:1, endln:5:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/LogicCast/dut.sv, line:1:1, endln:5:10 |vpiStmt: \_named_begin: (work@top.csr_read_write), line:2:15, endln:4:6 |vpiParent: @@ -975,7 +975,7 @@ design: (work@top) |vpiName:allnonexistent |vpiAlwaysType:2 |uhdmtopModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/LogicCast/dut.sv, line:1:1, endln:5:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/LogicCast/dut.sv, line:1:1, endln:5:10 |vpiName:work@top |vpiDefName:work@top |vpiTop:1 @@ -991,7 +991,7 @@ design: (work@top) |vpiProcess: \_always: , line:2:3, endln:4:6 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/LogicCast/dut.sv, line:1:1, endln:5:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/LogicCast/dut.sv, line:1:1, endln:5:10 |vpiStmt: \_named_begin: (work@top.csr_read_write), line:2:15, endln:4:6 |vpiParent: diff --git a/tests/LogicSize/LogicSize.log b/tests/LogicSize/LogicSize.log index e57850ade0..ac50f22d30 100644 --- a/tests/LogicSize/LogicSize.log +++ b/tests/LogicSize/LogicSize.log @@ -143,7 +143,7 @@ cont_assign 2 design 1 logic_net 4 logic_typespec 10 -module 10 +module_inst 10 operation 1 param_assign 4 parameter 4 @@ -158,7 +158,7 @@ cont_assign 3 design 1 logic_net 4 logic_typespec 10 -module 10 +module_inst 10 operation 1 param_assign 4 parameter 4 @@ -178,14 +178,14 @@ design: (work@top) |vpiElaborated:1 |vpiName:work@top |uhdmallModules: -\_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/LogicSize/dut.sv, line:1:1, endln:4:10 +\_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/LogicSize/dut.sv, line:1:1, endln:4:10 |vpiParent: \_design: (work@top) |vpiFullName:work@dut |vpiParameter: \_parameter: (work@dut.P), line:2:20, endln:2:21 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/LogicSize/dut.sv, line:1:1, endln:4:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/LogicSize/dut.sv, line:1:1, endln:4:10 |UINT:0 |vpiTypespec: \_logic_typespec: , line:2:14, endln:2:19 @@ -196,7 +196,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:2:20, endln:2:25 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/LogicSize/dut.sv, line:1:1, endln:4:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/LogicSize/dut.sv, line:1:1, endln:4:10 |vpiRhs: \_constant: , line:2:24, endln:2:25 |vpiDecompile:0 @@ -211,14 +211,14 @@ design: (work@top) |vpiNet: \_logic_net: (work@dut.a), line:1:25, endln:1:26 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/LogicSize/dut.sv, line:1:1, endln:4:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/LogicSize/dut.sv, line:1:1, endln:4:10 |vpiName:a |vpiFullName:work@dut.a |vpiNetType:36 |vpiPort: \_port: (a), line:1:25, endln:1:26 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/LogicSize/dut.sv, line:1:1, endln:4:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/LogicSize/dut.sv, line:1:1, endln:4:10 |vpiName:a |vpiDirection:2 |vpiLowConn: @@ -230,7 +230,7 @@ design: (work@top) |vpiContAssign: \_cont_assign: , line:3:11, endln:3:16 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/LogicSize/dut.sv, line:1:1, endln:4:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/LogicSize/dut.sv, line:1:1, endln:4:10 |vpiRhs: \_ref_obj: (work@dut.P), line:3:15, endln:3:16 |vpiParent: @@ -246,14 +246,14 @@ design: (work@top) |vpiActual: \_logic_net: (work@top.u_dut.a), line:1:25, endln:1:26 |uhdmallModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/LogicSize/dut.sv, line:6:1, endln:13:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/LogicSize/dut.sv, line:6:1, endln:13:10 |vpiParent: \_design: (work@top) |vpiFullName:work@top |vpiParameter: \_parameter: (work@top.X), line:7:20, endln:7:21 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/LogicSize/dut.sv, line:6:1, endln:13:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/LogicSize/dut.sv, line:6:1, endln:13:10 |UINT:0 |vpiTypespec: \_logic_typespec: , line:7:14, endln:7:19 @@ -264,7 +264,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:7:20, endln:7:25 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/LogicSize/dut.sv, line:6:1, endln:13:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/LogicSize/dut.sv, line:6:1, endln:13:10 |vpiRhs: \_constant: , line:7:24, endln:7:25 |vpiDecompile:0 @@ -279,14 +279,14 @@ design: (work@top) |vpiNet: \_logic_net: (work@top.o), line:6:25, endln:6:26 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/LogicSize/dut.sv, line:6:1, endln:13:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/LogicSize/dut.sv, line:6:1, endln:13:10 |vpiName:o |vpiFullName:work@top.o |vpiNetType:36 |vpiPort: \_port: (o), line:6:25, endln:6:26 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/LogicSize/dut.sv, line:6:1, endln:13:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/LogicSize/dut.sv, line:6:1, endln:13:10 |vpiName:o |vpiDirection:2 |vpiLowConn: @@ -296,12 +296,12 @@ design: (work@top) |vpiTypedef: \_logic_typespec: , line:6:19, endln:6:24 |uhdmtopModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/LogicSize/dut.sv, line:6:1, endln:13:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/LogicSize/dut.sv, line:6:1, endln:13:10 |vpiName:work@top |vpiParameter: \_parameter: (work@top.X), line:7:20, endln:7:21 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/LogicSize/dut.sv, line:6:1, endln:13:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/LogicSize/dut.sv, line:6:1, endln:13:10 |UINT:0 |vpiTypespec: \_logic_typespec: , line:7:14, endln:7:19 @@ -312,7 +312,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:7:20, endln:7:25 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/LogicSize/dut.sv, line:6:1, endln:13:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/LogicSize/dut.sv, line:6:1, endln:13:10 |vpiRhs: \_constant: , line:7:24, endln:7:25 |vpiDecompile:0 @@ -328,7 +328,7 @@ design: (work@top) |vpiNet: \_logic_net: (work@top.o), line:6:25, endln:6:26 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/LogicSize/dut.sv, line:6:1, endln:13:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/LogicSize/dut.sv, line:6:1, endln:13:10 |vpiTypespec: \_logic_typespec: , line:6:19, endln:6:24 |vpiName:o @@ -338,7 +338,7 @@ design: (work@top) |vpiPort: \_port: (o), line:6:25, endln:6:26 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/LogicSize/dut.sv, line:6:1, endln:13:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/LogicSize/dut.sv, line:6:1, endln:13:10 |vpiName:o |vpiDirection:2 |vpiLowConn: @@ -352,17 +352,17 @@ design: (work@top) |vpiTypedef: \_logic_typespec: , line:6:19, endln:6:24 |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/LogicSize/dut.sv, line:6:1, endln:13:10 - |vpiModule: - \_module: work@dut (work@top.u_dut), file:${SURELOG_DIR}/tests/LogicSize/dut.sv, line:8:4, endln:12:6 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/LogicSize/dut.sv, line:6:1, endln:13:10 + |vpiModuleInst: + \_module_inst: work@dut (work@top.u_dut), file:${SURELOG_DIR}/tests/LogicSize/dut.sv, line:8:4, endln:12:6 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/LogicSize/dut.sv, line:6:1, endln:13:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/LogicSize/dut.sv, line:6:1, endln:13:10 |vpiName:u_dut |vpiFullName:work@top.u_dut |vpiParameter: \_parameter: (work@top.u_dut.P), line:2:20, endln:2:21 |vpiParent: - \_module: work@dut (work@top.u_dut), file:${SURELOG_DIR}/tests/LogicSize/dut.sv, line:8:4, endln:12:6 + \_module_inst: work@dut (work@top.u_dut), file:${SURELOG_DIR}/tests/LogicSize/dut.sv, line:8:4, endln:12:6 |UINT:0 |vpiTypespec: \_logic_typespec: , line:2:14, endln:2:19 @@ -373,7 +373,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:2:20, endln:2:25 |vpiParent: - \_module: work@dut (work@top.u_dut), file:${SURELOG_DIR}/tests/LogicSize/dut.sv, line:8:4, endln:12:6 + \_module_inst: work@dut (work@top.u_dut), file:${SURELOG_DIR}/tests/LogicSize/dut.sv, line:8:4, endln:12:6 |vpiOverriden:1 |vpiRhs: \_constant: , line:2:24, endln:2:25 @@ -393,18 +393,18 @@ design: (work@top) |vpiNet: \_logic_net: (work@top.u_dut.a), line:1:25, endln:1:26 |vpiParent: - \_module: work@dut (work@top.u_dut), file:${SURELOG_DIR}/tests/LogicSize/dut.sv, line:8:4, endln:12:6 + \_module_inst: work@dut (work@top.u_dut), file:${SURELOG_DIR}/tests/LogicSize/dut.sv, line:8:4, endln:12:6 |vpiTypespec: \_logic_typespec: , line:1:19, endln:1:24 |vpiName:a |vpiFullName:work@top.u_dut.a |vpiNetType:36 |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/LogicSize/dut.sv, line:6:1, endln:13:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/LogicSize/dut.sv, line:6:1, endln:13:10 |vpiPort: \_port: (a), line:1:25, endln:1:26 |vpiParent: - \_module: work@dut (work@top.u_dut), file:${SURELOG_DIR}/tests/LogicSize/dut.sv, line:8:4, endln:12:6 + \_module_inst: work@dut (work@top.u_dut), file:${SURELOG_DIR}/tests/LogicSize/dut.sv, line:8:4, endln:12:6 |vpiName:a |vpiDirection:2 |vpiHighConn: @@ -426,11 +426,11 @@ design: (work@top) |vpiTypedef: \_logic_typespec: , line:1:19, endln:1:24 |vpiInstance: - \_module: work@dut (work@top.u_dut), file:${SURELOG_DIR}/tests/LogicSize/dut.sv, line:8:4, endln:12:6 + \_module_inst: work@dut (work@top.u_dut), file:${SURELOG_DIR}/tests/LogicSize/dut.sv, line:8:4, endln:12:6 |vpiContAssign: \_cont_assign: , line:3:11, endln:3:16 |vpiParent: - \_module: work@dut (work@top.u_dut), file:${SURELOG_DIR}/tests/LogicSize/dut.sv, line:8:4, endln:12:6 + \_module_inst: work@dut (work@top.u_dut), file:${SURELOG_DIR}/tests/LogicSize/dut.sv, line:8:4, endln:12:6 |vpiRhs: \_constant: , line:2:24, endln:2:25 |vpiLhs: diff --git a/tests/LogicTypedef/LogicTypedef.log b/tests/LogicTypedef/LogicTypedef.log index 8e9e2d3bb8..2cd845d706 100644 --- a/tests/LogicTypedef/LogicTypedef.log +++ b/tests/LogicTypedef/LogicTypedef.log @@ -30,7 +30,7 @@ design 1 logic_net 4 logic_typespec 5 logic_var 1 -module 3 +module_inst 3 packed_array_typespec 3 range 11 === UHDM Object Stats End === @@ -44,7 +44,7 @@ design 1 logic_net 4 logic_typespec 5 logic_var 1 -module 3 +module_inst 3 packed_array_typespec 3 range 11 === UHDM Object Stats End === @@ -61,17 +61,17 @@ design: (work@test) |vpiElaborated:1 |vpiName:work@test |uhdmallModules: -\_module: work@test (work@test), file:${SURELOG_DIR}/tests/LogicTypedef/dut.sv, line:1:1, endln:11:10 +\_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/LogicTypedef/dut.sv, line:1:1, endln:11:10 |vpiParent: \_design: (work@test) |vpiFullName:work@test |vpiTypedef: \_bit_typespec: (bit_two_bits), line:8:13, endln:8:22 |vpiParent: - \_module: work@test (work@test), file:${SURELOG_DIR}/tests/LogicTypedef/dut.sv, line:1:1, endln:11:10 + \_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/LogicTypedef/dut.sv, line:1:1, endln:11:10 |vpiName:bit_two_bits |vpiInstance: - \_module: work@test (work@test), file:${SURELOG_DIR}/tests/LogicTypedef/dut.sv, line:1:1, endln:11:10 + \_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/LogicTypedef/dut.sv, line:1:1, endln:11:10 |vpiRange: \_range: , line:8:17, endln:8:22 |vpiLeftRange: @@ -94,10 +94,10 @@ design: (work@test) |vpiTypedef: \_logic_typespec: (log_two_bits), line:2:13, endln:2:24 |vpiParent: - \_module: work@test (work@test), file:${SURELOG_DIR}/tests/LogicTypedef/dut.sv, line:1:1, endln:11:10 + \_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/LogicTypedef/dut.sv, line:1:1, endln:11:10 |vpiName:log_two_bits |vpiInstance: - \_module: work@test (work@test), file:${SURELOG_DIR}/tests/LogicTypedef/dut.sv, line:1:1, endln:11:10 + \_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/LogicTypedef/dut.sv, line:1:1, endln:11:10 |vpiRange: \_range: , line:2:19, endln:2:24 |vpiLeftRange: @@ -119,10 +119,10 @@ design: (work@test) |vpiTypedef: \_logic_typespec: (reg_two_bits), line:5:13, endln:5:22 |vpiParent: - \_module: work@test (work@test), file:${SURELOG_DIR}/tests/LogicTypedef/dut.sv, line:1:1, endln:11:10 + \_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/LogicTypedef/dut.sv, line:1:1, endln:11:10 |vpiName:reg_two_bits |vpiInstance: - \_module: work@test (work@test), file:${SURELOG_DIR}/tests/LogicTypedef/dut.sv, line:1:1, endln:11:10 + \_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/LogicTypedef/dut.sv, line:1:1, endln:11:10 |vpiRange: \_range: , line:5:17, endln:5:22 |vpiLeftRange: @@ -145,30 +145,30 @@ design: (work@test) |vpiNet: \_logic_net: (work@test.logn), line:3:18, endln:3:22 |vpiParent: - \_module: work@test (work@test), file:${SURELOG_DIR}/tests/LogicTypedef/dut.sv, line:1:1, endln:11:10 + \_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/LogicTypedef/dut.sv, line:1:1, endln:11:10 |vpiName:logn |vpiFullName:work@test.logn |vpiNetType:36 |vpiNet: \_logic_net: (work@test.regn), line:6:18, endln:6:22 |vpiParent: - \_module: work@test (work@test), file:${SURELOG_DIR}/tests/LogicTypedef/dut.sv, line:1:1, endln:11:10 + \_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/LogicTypedef/dut.sv, line:1:1, endln:11:10 |vpiName:regn |vpiFullName:work@test.regn |vpiNetType:48 |vpiNet: \_logic_net: (work@test.bitn), line:9:18, endln:9:22 |vpiParent: - \_module: work@test (work@test), file:${SURELOG_DIR}/tests/LogicTypedef/dut.sv, line:1:1, endln:11:10 + \_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/LogicTypedef/dut.sv, line:1:1, endln:11:10 |vpiName:bitn |vpiFullName:work@test.bitn |uhdmtopModules: -\_module: work@test (work@test), file:${SURELOG_DIR}/tests/LogicTypedef/dut.sv, line:1:1, endln:11:10 +\_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/LogicTypedef/dut.sv, line:1:1, endln:11:10 |vpiName:work@test |vpiVariables: \_logic_var: (work@test.logn), line:3:18, endln:3:22 |vpiParent: - \_module: work@test (work@test), file:${SURELOG_DIR}/tests/LogicTypedef/dut.sv, line:1:1, endln:11:10 + \_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/LogicTypedef/dut.sv, line:1:1, endln:11:10 |vpiTypespec: \_logic_typespec: (log_two_bits), line:2:13, endln:2:24 |vpiName:log_two_bits @@ -198,7 +198,7 @@ design: (work@test) |vpiVariables: \_bit_var: (work@test.bitn), line:9:18, endln:9:22 |vpiParent: - \_module: work@test (work@test), file:${SURELOG_DIR}/tests/LogicTypedef/dut.sv, line:1:1, endln:11:10 + \_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/LogicTypedef/dut.sv, line:1:1, endln:11:10 |vpiTypespec: \_bit_typespec: (bit_two_bits), line:8:13, endln:8:22 |vpiName:bit_two_bits @@ -237,7 +237,7 @@ design: (work@test) |vpiNet: \_logic_net: (work@test.regn), line:6:18, endln:6:22 |vpiParent: - \_module: work@test (work@test), file:${SURELOG_DIR}/tests/LogicTypedef/dut.sv, line:1:1, endln:11:10 + \_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/LogicTypedef/dut.sv, line:1:1, endln:11:10 |vpiTypespec: \_logic_typespec: (reg_two_bits), line:5:13, endln:5:22 |vpiName:regn diff --git a/tests/LongHex/LongHex.log b/tests/LongHex/LongHex.log index f689613198..ba07d2e490 100644 --- a/tests/LongHex/LongHex.log +++ b/tests/LongHex/LongHex.log @@ -176,7 +176,7 @@ design 1 import_typespec 2 logic_net 1 logic_typespec 14 -module 10 +module_inst 10 package 3 param_assign 10 parameter 12 @@ -193,7 +193,7 @@ design 1 import_typespec 2 logic_net 1 logic_typespec 14 -module 10 +module_inst 10 package 3 param_assign 10 parameter 12 @@ -319,14 +319,14 @@ design: (work@aes_core) |vpiDefName:aes_pkg |vpiTop:1 |uhdmallModules: -\_module: work@aes_cipher_core (work@aes_cipher_core), file:${SURELOG_DIR}/tests/LongHex/dut.sv, line:6:1, endln:9:10 +\_module_inst: work@aes_cipher_core (work@aes_cipher_core), file:${SURELOG_DIR}/tests/LongHex/dut.sv, line:6:1, endln:9:10 |vpiParent: \_design: (work@aes_core) |vpiFullName:work@aes_cipher_core |vpiParameter: \_parameter: (work@aes_cipher_core.RndCnstMaskingLfsrSeedDefault), line:2:28, endln:2:57 |vpiParent: - \_module: work@aes_cipher_core (work@aes_cipher_core), file:${SURELOG_DIR}/tests/LongHex/dut.sv, line:6:1, endln:9:10 + \_module_inst: work@aes_cipher_core (work@aes_cipher_core), file:${SURELOG_DIR}/tests/LongHex/dut.sv, line:6:1, endln:9:10 |HEX:c132b5723c5a4cf4743b3c7c32d580f74f1713a |vpiTypespec: \_logic_typespec: , line:2:14, endln:2:27 @@ -360,7 +360,7 @@ design: (work@aes_core) |vpiParameter: \_parameter: (work@aes_cipher_core.RndCnstMaskingLfsrSeed), line:7:28, endln:7:50 |vpiParent: - \_module: work@aes_cipher_core (work@aes_cipher_core), file:${SURELOG_DIR}/tests/LongHex/dut.sv, line:6:1, endln:9:10 + \_module_inst: work@aes_cipher_core (work@aes_cipher_core), file:${SURELOG_DIR}/tests/LongHex/dut.sv, line:6:1, endln:9:10 |UINT:0 |vpiTypespec: \_logic_typespec: , line:7:14, endln:7:27 @@ -389,7 +389,7 @@ design: (work@aes_core) |vpiParamAssign: \_param_assign: , line:2:28, endln:3:51 |vpiParent: - \_module: work@aes_cipher_core (work@aes_cipher_core), file:${SURELOG_DIR}/tests/LongHex/dut.sv, line:6:1, endln:9:10 + \_module_inst: work@aes_cipher_core (work@aes_cipher_core), file:${SURELOG_DIR}/tests/LongHex/dut.sv, line:6:1, endln:9:10 |vpiRhs: \_constant: , line:3:7, endln:3:51 |vpiParent: @@ -461,7 +461,7 @@ design: (work@aes_core) |vpiParamAssign: \_param_assign: , line:7:28, endln:7:54 |vpiParent: - \_module: work@aes_cipher_core (work@aes_cipher_core), file:${SURELOG_DIR}/tests/LongHex/dut.sv, line:6:1, endln:9:10 + \_module_inst: work@aes_cipher_core (work@aes_cipher_core), file:${SURELOG_DIR}/tests/LongHex/dut.sv, line:6:1, endln:9:10 |vpiRhs: \_constant: , line:7:53, endln:7:54 |vpiDecompile:0 @@ -478,7 +478,7 @@ design: (work@aes_core) |vpiContAssign: \_cont_assign: , line:8:11, endln:8:43 |vpiParent: - \_module: work@aes_cipher_core (work@aes_cipher_core), file:${SURELOG_DIR}/tests/LongHex/dut.sv, line:6:1, endln:9:10 + \_module_inst: work@aes_cipher_core (work@aes_cipher_core), file:${SURELOG_DIR}/tests/LongHex/dut.sv, line:6:1, endln:9:10 |vpiRhs: \_part_select: , line:8:15, endln:8:43 |vpiParent: @@ -510,14 +510,14 @@ design: (work@aes_core) |vpiActual: \_logic_net: (x) |uhdmallModules: -\_module: work@aes_core (work@aes_core), file:${SURELOG_DIR}/tests/LongHex/dut.sv, line:11:1, endln:15:10 +\_module_inst: work@aes_core (work@aes_core), file:${SURELOG_DIR}/tests/LongHex/dut.sv, line:11:1, endln:15:10 |vpiParent: \_design: (work@aes_core) |vpiFullName:work@aes_core |vpiParameter: \_parameter: (work@aes_core.RndCnstMaskingLfsrSeedDefault), line:2:28, endln:2:57 |vpiParent: - \_module: work@aes_core (work@aes_core), file:${SURELOG_DIR}/tests/LongHex/dut.sv, line:11:1, endln:15:10 + \_module_inst: work@aes_core (work@aes_core), file:${SURELOG_DIR}/tests/LongHex/dut.sv, line:11:1, endln:15:10 |HEX:c132b5723c5a4cf4743b3c7c32d580f74f1713a |vpiTypespec: \_logic_typespec: , line:2:14, endln:2:27 @@ -551,7 +551,7 @@ design: (work@aes_core) |vpiParamAssign: \_param_assign: , line:2:28, endln:3:51 |vpiParent: - \_module: work@aes_core (work@aes_core), file:${SURELOG_DIR}/tests/LongHex/dut.sv, line:11:1, endln:15:10 + \_module_inst: work@aes_core (work@aes_core), file:${SURELOG_DIR}/tests/LongHex/dut.sv, line:11:1, endln:15:10 |vpiRhs: \_constant: , line:3:7, endln:3:51 |vpiParent: @@ -624,12 +624,12 @@ design: (work@aes_core) \_import_typespec: (aes_pkg), line:11:24, endln:11:34 |vpiDefName:work@aes_core |uhdmtopModules: -\_module: work@aes_core (work@aes_core), file:${SURELOG_DIR}/tests/LongHex/dut.sv, line:11:1, endln:15:10 +\_module_inst: work@aes_core (work@aes_core), file:${SURELOG_DIR}/tests/LongHex/dut.sv, line:11:1, endln:15:10 |vpiName:work@aes_core |vpiParameter: \_parameter: (work@aes_core.RndCnstMaskingLfsrSeedDefault), line:2:28, endln:2:57 |vpiParent: - \_module: work@aes_core (work@aes_core), file:${SURELOG_DIR}/tests/LongHex/dut.sv, line:11:1, endln:15:10 + \_module_inst: work@aes_core (work@aes_core), file:${SURELOG_DIR}/tests/LongHex/dut.sv, line:11:1, endln:15:10 |HEX:c132b5723c5a4cf4743b3c7c32d580f74f1713a |vpiTypespec: \_logic_typespec: , line:2:14, endln:2:27 @@ -663,7 +663,7 @@ design: (work@aes_core) |vpiParamAssign: \_param_assign: , line:2:28, endln:3:51 |vpiParent: - \_module: work@aes_core (work@aes_core), file:${SURELOG_DIR}/tests/LongHex/dut.sv, line:11:1, endln:15:10 + \_module_inst: work@aes_core (work@aes_core), file:${SURELOG_DIR}/tests/LongHex/dut.sv, line:11:1, endln:15:10 |vpiRhs: \_constant: , line:3:7, endln:3:51 |vpiDecompile:160'hc132b5723c5a4cf4743b3c7c32d580f74f1713a @@ -677,16 +677,16 @@ design: (work@aes_core) |vpiDefName:work@aes_core |vpiTop:1 |vpiTopModule:1 - |vpiModule: - \_module: work@aes_cipher_core (work@aes_core.u_aes_cipher_core), file:${SURELOG_DIR}/tests/LongHex/dut.sv, line:12:4, endln:14:27 + |vpiModuleInst: + \_module_inst: work@aes_cipher_core (work@aes_core.u_aes_cipher_core), file:${SURELOG_DIR}/tests/LongHex/dut.sv, line:12:4, endln:14:27 |vpiParent: - \_module: work@aes_core (work@aes_core), file:${SURELOG_DIR}/tests/LongHex/dut.sv, line:11:1, endln:15:10 + \_module_inst: work@aes_core (work@aes_core), file:${SURELOG_DIR}/tests/LongHex/dut.sv, line:11:1, endln:15:10 |vpiName:u_aes_cipher_core |vpiFullName:work@aes_core.u_aes_cipher_core |vpiParameter: \_parameter: (work@aes_core.u_aes_cipher_core.RndCnstMaskingLfsrSeedDefault), line:2:28, endln:2:57 |vpiParent: - \_module: work@aes_cipher_core (work@aes_core.u_aes_cipher_core), file:${SURELOG_DIR}/tests/LongHex/dut.sv, line:12:4, endln:14:27 + \_module_inst: work@aes_cipher_core (work@aes_core.u_aes_cipher_core), file:${SURELOG_DIR}/tests/LongHex/dut.sv, line:12:4, endln:14:27 |HEX:c132b5723c5a4cf4743b3c7c32d580f74f1713a |vpiTypespec: \_logic_typespec: , line:2:14, endln:2:27 @@ -720,7 +720,7 @@ design: (work@aes_core) |vpiParameter: \_parameter: (work@aes_core.u_aes_cipher_core.RndCnstMaskingLfsrSeed), line:7:28, endln:7:50 |vpiParent: - \_module: work@aes_cipher_core (work@aes_core.u_aes_cipher_core), file:${SURELOG_DIR}/tests/LongHex/dut.sv, line:12:4, endln:14:27 + \_module_inst: work@aes_cipher_core (work@aes_core.u_aes_cipher_core), file:${SURELOG_DIR}/tests/LongHex/dut.sv, line:12:4, endln:14:27 |UINT:0 |vpiTypespec: \_logic_typespec: , line:7:14, endln:7:27 @@ -751,7 +751,7 @@ design: (work@aes_core) |vpiParamAssign: \_param_assign: , line:2:28, endln:3:51 |vpiParent: - \_module: work@aes_cipher_core (work@aes_core.u_aes_cipher_core), file:${SURELOG_DIR}/tests/LongHex/dut.sv, line:12:4, endln:14:27 + \_module_inst: work@aes_cipher_core (work@aes_core.u_aes_cipher_core), file:${SURELOG_DIR}/tests/LongHex/dut.sv, line:12:4, endln:14:27 |vpiRhs: \_constant: , line:3:7, endln:3:51 |vpiDecompile:160'hc132b5723c5a4cf4743b3c7c32d580f74f1713a @@ -763,7 +763,7 @@ design: (work@aes_core) |vpiParamAssign: \_param_assign: , line:7:28, endln:7:54 |vpiParent: - \_module: work@aes_cipher_core (work@aes_core.u_aes_cipher_core), file:${SURELOG_DIR}/tests/LongHex/dut.sv, line:12:4, endln:14:27 + \_module_inst: work@aes_cipher_core (work@aes_core.u_aes_cipher_core), file:${SURELOG_DIR}/tests/LongHex/dut.sv, line:12:4, endln:14:27 |vpiOverriden:1 |vpiRhs: \_constant: , line:7:53, endln:7:54 @@ -785,11 +785,11 @@ design: (work@aes_core) |vpiName:x |vpiNetType:1 |vpiInstance: - \_module: work@aes_core (work@aes_core), file:${SURELOG_DIR}/tests/LongHex/dut.sv, line:11:1, endln:15:10 + \_module_inst: work@aes_core (work@aes_core), file:${SURELOG_DIR}/tests/LongHex/dut.sv, line:11:1, endln:15:10 |vpiContAssign: \_cont_assign: , line:8:11, endln:8:43 |vpiParent: - \_module: work@aes_cipher_core (work@aes_core.u_aes_cipher_core), file:${SURELOG_DIR}/tests/LongHex/dut.sv, line:12:4, endln:14:27 + \_module_inst: work@aes_cipher_core (work@aes_core.u_aes_cipher_core), file:${SURELOG_DIR}/tests/LongHex/dut.sv, line:12:4, endln:14:27 |vpiRhs: \_constant: |vpiParent: diff --git a/tests/Loop/Loop.log b/tests/Loop/Loop.log index 940703b20e..fa945eb428 100644 --- a/tests/Loop/Loop.log +++ b/tests/Loop/Loop.log @@ -160,7 +160,7 @@ design 1 gen_scope 10 gen_scope_array 10 int_typespec 7 -module 20 +module_inst 20 operation 5 param_assign 7 parameter 7 @@ -173,7 +173,7 @@ design 1 gen_scope 67 gen_scope_array 67 int_typespec 7 -module 77 +module_inst 77 operation 5 param_assign 64 parameter 7 @@ -191,20 +191,20 @@ design: (work@top) |vpiElaborated:1 |vpiName:work@top |uhdmallModules: -\_module: work@loop (work@loop), file:${SURELOG_DIR}/tests/Loop/dut.sv, line:6:1, endln:8:10 +\_module_inst: work@loop (work@loop), file:${SURELOG_DIR}/tests/Loop/dut.sv, line:6:1, endln:8:10 |vpiParent: \_design: (work@top) |vpiFullName:work@loop |vpiDefName:work@loop |uhdmallModules: -\_module: work@test (work@test), file:${SURELOG_DIR}/tests/Loop/dut.sv, line:10:1, endln:16:10 +\_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/Loop/dut.sv, line:10:1, endln:16:10 |vpiParent: \_design: (work@top) |vpiFullName:work@test |vpiParameter: \_parameter: (work@test.bht_row_width_p), line:12:14, endln:12:29 |vpiParent: - \_module: work@test (work@test), file:${SURELOG_DIR}/tests/Loop/dut.sv, line:10:1, endln:16:10 + \_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/Loop/dut.sv, line:10:1, endln:16:10 |UINT:10 |vpiTypespec: \_int_typespec: @@ -213,7 +213,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:12:14, endln:12:34 |vpiParent: - \_module: work@test (work@test), file:${SURELOG_DIR}/tests/Loop/dut.sv, line:10:1, endln:16:10 + \_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/Loop/dut.sv, line:10:1, endln:16:10 |vpiRhs: \_constant: , line:12:32, endln:12:34 |vpiDecompile:10 @@ -226,27 +226,27 @@ design: (work@top) \_parameter: (work@test.bht_row_width_p), line:12:14, endln:12:29 |vpiDefName:work@test |uhdmallModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/Loop/dut.sv, line:1:1, endln:4:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/Loop/dut.sv, line:1:1, endln:4:10 |vpiParent: \_design: (work@top) |vpiFullName:work@top |vpiDefName:work@top |uhdmtopModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/Loop/dut.sv, line:1:1, endln:4:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/Loop/dut.sv, line:1:1, endln:4:10 |vpiName:work@top |vpiDefName:work@top |vpiTop:1 |vpiTopModule:1 - |vpiModule: - \_module: work@test (work@top.u1), file:${SURELOG_DIR}/tests/Loop/dut.sv, line:2:4, endln:2:14 + |vpiModuleInst: + \_module_inst: work@test (work@top.u1), file:${SURELOG_DIR}/tests/Loop/dut.sv, line:2:4, endln:2:14 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/Loop/dut.sv, line:1:1, endln:4:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/Loop/dut.sv, line:1:1, endln:4:10 |vpiName:u1 |vpiFullName:work@top.u1 |vpiParameter: \_parameter: (work@top.u1.bht_row_width_p), line:12:14, endln:12:29 |vpiParent: - \_module: work@test (work@top.u1), file:${SURELOG_DIR}/tests/Loop/dut.sv, line:2:4, endln:2:14 + \_module_inst: work@test (work@top.u1), file:${SURELOG_DIR}/tests/Loop/dut.sv, line:2:4, endln:2:14 |UINT:10 |vpiTypespec: \_int_typespec: @@ -257,7 +257,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:12:14, endln:12:34 |vpiParent: - \_module: work@test (work@top.u1), file:${SURELOG_DIR}/tests/Loop/dut.sv, line:2:4, endln:2:14 + \_module_inst: work@test (work@top.u1), file:${SURELOG_DIR}/tests/Loop/dut.sv, line:2:4, endln:2:14 |vpiRhs: \_constant: , line:12:32, endln:12:34 |vpiDecompile:10 @@ -272,11 +272,11 @@ design: (work@top) |vpiDefFile:${SURELOG_DIR}/tests/Loop/dut.sv |vpiDefLineNo:10 |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/Loop/dut.sv, line:1:1, endln:4:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/Loop/dut.sv, line:1:1, endln:4:10 |vpiGenScopeArray: \_gen_scope_array: (work@top.u1.genblk1), line:13:4, endln:15:7 |vpiParent: - \_module: work@test (work@top.u1), file:${SURELOG_DIR}/tests/Loop/dut.sv, line:2:4, endln:2:14 + \_module_inst: work@test (work@top.u1), file:${SURELOG_DIR}/tests/Loop/dut.sv, line:2:4, endln:2:14 |vpiName:genblk1 |vpiFullName:work@top.u1.genblk1 |vpiGenScope: @@ -284,8 +284,8 @@ design: (work@top) |vpiParent: \_gen_scope_array: (work@top.u1.genblk1), line:13:4, endln:15:7 |vpiFullName:work@top.u1.genblk1 - |vpiModule: - \_module: work@test (work@top.u1.genblk1.u), file:${SURELOG_DIR}/tests/Loop/dut.sv, line:14:6, endln:14:54 + |vpiModuleInst: + \_module_inst: work@test (work@top.u1.genblk1.u), file:${SURELOG_DIR}/tests/Loop/dut.sv, line:14:6, endln:14:54 |vpiParent: \_gen_scope: (work@top.u1.genblk1) |vpiName:u @@ -304,7 +304,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:12:14, endln:12:34 |vpiParent: - \_module: work@test (work@top.u1.genblk1.u), file:${SURELOG_DIR}/tests/Loop/dut.sv, line:14:6, endln:14:54 + \_module_inst: work@test (work@top.u1.genblk1.u), file:${SURELOG_DIR}/tests/Loop/dut.sv, line:14:6, endln:14:54 |vpiOverriden:1 |vpiRhs: \_constant: , line:12:32, endln:12:34 @@ -322,7 +322,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.u1.genblk1.u.genblk1), line:13:4, endln:15:7 |vpiParent: - \_module: work@test (work@top.u1.genblk1.u), file:${SURELOG_DIR}/tests/Loop/dut.sv, line:14:6, endln:14:54 + \_module_inst: work@test (work@top.u1.genblk1.u), file:${SURELOG_DIR}/tests/Loop/dut.sv, line:14:6, endln:14:54 |vpiName:genblk1 |vpiFullName:work@top.u1.genblk1.u.genblk1 |vpiGenScope: @@ -330,8 +330,8 @@ design: (work@top) |vpiParent: \_gen_scope_array: (work@top.u1.genblk1.u.genblk1), line:13:4, endln:15:7 |vpiFullName:work@top.u1.genblk1.u.genblk1 - |vpiModule: - \_module: work@test (work@top.u1.genblk1.u.genblk1.u), file:${SURELOG_DIR}/tests/Loop/dut.sv, line:14:6, endln:14:54 + |vpiModuleInst: + \_module_inst: work@test (work@top.u1.genblk1.u.genblk1.u), file:${SURELOG_DIR}/tests/Loop/dut.sv, line:14:6, endln:14:54 |vpiParent: \_gen_scope: (work@top.u1.genblk1.u.genblk1) |vpiName:u @@ -350,7 +350,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:12:14, endln:12:34 |vpiParent: - \_module: work@test (work@top.u1.genblk1.u.genblk1.u), file:${SURELOG_DIR}/tests/Loop/dut.sv, line:14:6, endln:14:54 + \_module_inst: work@test (work@top.u1.genblk1.u.genblk1.u), file:${SURELOG_DIR}/tests/Loop/dut.sv, line:14:6, endln:14:54 |vpiOverriden:1 |vpiRhs: \_constant: , line:12:32, endln:12:34 @@ -368,7 +368,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.u1.genblk1.u.genblk1.u.genblk1), line:13:4, endln:15:7 |vpiParent: - \_module: work@test (work@top.u1.genblk1.u.genblk1.u), file:${SURELOG_DIR}/tests/Loop/dut.sv, line:14:6, endln:14:54 + \_module_inst: work@test (work@top.u1.genblk1.u.genblk1.u), file:${SURELOG_DIR}/tests/Loop/dut.sv, line:14:6, endln:14:54 |vpiName:genblk1 |vpiFullName:work@top.u1.genblk1.u.genblk1.u.genblk1 |vpiGenScope: @@ -376,8 +376,8 @@ design: (work@top) |vpiParent: \_gen_scope_array: (work@top.u1.genblk1.u.genblk1.u.genblk1), line:13:4, endln:15:7 |vpiFullName:work@top.u1.genblk1.u.genblk1.u.genblk1 - |vpiModule: - \_module: work@test (work@top.u1.genblk1.u.genblk1.u.genblk1.u), file:${SURELOG_DIR}/tests/Loop/dut.sv, line:14:6, endln:14:54 + |vpiModuleInst: + \_module_inst: work@test (work@top.u1.genblk1.u.genblk1.u.genblk1.u), file:${SURELOG_DIR}/tests/Loop/dut.sv, line:14:6, endln:14:54 |vpiParent: \_gen_scope: (work@top.u1.genblk1.u.genblk1.u.genblk1) |vpiName:u @@ -396,7 +396,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:12:14, endln:12:34 |vpiParent: - \_module: work@test (work@top.u1.genblk1.u.genblk1.u.genblk1.u), file:${SURELOG_DIR}/tests/Loop/dut.sv, line:14:6, endln:14:54 + \_module_inst: work@test (work@top.u1.genblk1.u.genblk1.u.genblk1.u), file:${SURELOG_DIR}/tests/Loop/dut.sv, line:14:6, endln:14:54 |vpiOverriden:1 |vpiRhs: \_constant: , line:12:32, endln:12:34 @@ -414,7 +414,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.u1.genblk1.u.genblk1.u.genblk1.u.genblk1), line:13:4, endln:15:7 |vpiParent: - \_module: work@test (work@top.u1.genblk1.u.genblk1.u.genblk1.u), file:${SURELOG_DIR}/tests/Loop/dut.sv, line:14:6, endln:14:54 + \_module_inst: work@test (work@top.u1.genblk1.u.genblk1.u.genblk1.u), file:${SURELOG_DIR}/tests/Loop/dut.sv, line:14:6, endln:14:54 |vpiName:genblk1 |vpiFullName:work@top.u1.genblk1.u.genblk1.u.genblk1.u.genblk1 |vpiGenScope: @@ -422,8 +422,8 @@ design: (work@top) |vpiParent: \_gen_scope_array: (work@top.u1.genblk1.u.genblk1.u.genblk1.u.genblk1), line:13:4, endln:15:7 |vpiFullName:work@top.u1.genblk1.u.genblk1.u.genblk1.u.genblk1 - |vpiModule: - \_module: work@test (work@top.u1.genblk1.u.genblk1.u.genblk1.u.genblk1.u), file:${SURELOG_DIR}/tests/Loop/dut.sv, line:14:6, endln:14:54 + |vpiModuleInst: + \_module_inst: work@test (work@top.u1.genblk1.u.genblk1.u.genblk1.u.genblk1.u), file:${SURELOG_DIR}/tests/Loop/dut.sv, line:14:6, endln:14:54 |vpiParent: \_gen_scope: (work@top.u1.genblk1.u.genblk1.u.genblk1.u.genblk1) |vpiName:u @@ -442,7 +442,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:12:14, endln:12:34 |vpiParent: - \_module: work@test (work@top.u1.genblk1.u.genblk1.u.genblk1.u.genblk1.u), file:${SURELOG_DIR}/tests/Loop/dut.sv, line:14:6, endln:14:54 + \_module_inst: work@test (work@top.u1.genblk1.u.genblk1.u.genblk1.u.genblk1.u), file:${SURELOG_DIR}/tests/Loop/dut.sv, line:14:6, endln:14:54 |vpiOverriden:1 |vpiRhs: \_constant: , line:12:32, endln:12:34 @@ -460,7 +460,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.u1.genblk1.u.genblk1.u.genblk1.u.genblk1.u.genblk1), line:13:4, endln:15:7 |vpiParent: - \_module: work@test (work@top.u1.genblk1.u.genblk1.u.genblk1.u.genblk1.u), file:${SURELOG_DIR}/tests/Loop/dut.sv, line:14:6, endln:14:54 + \_module_inst: work@test (work@top.u1.genblk1.u.genblk1.u.genblk1.u.genblk1.u), file:${SURELOG_DIR}/tests/Loop/dut.sv, line:14:6, endln:14:54 |vpiName:genblk1 |vpiFullName:work@top.u1.genblk1.u.genblk1.u.genblk1.u.genblk1.u.genblk1 |vpiGenScope: @@ -468,8 +468,8 @@ design: (work@top) |vpiParent: \_gen_scope_array: (work@top.u1.genblk1.u.genblk1.u.genblk1.u.genblk1.u.genblk1), line:13:4, endln:15:7 |vpiFullName:work@top.u1.genblk1.u.genblk1.u.genblk1.u.genblk1.u.genblk1 - |vpiModule: - \_module: work@test (work@top.u1.genblk1.u.genblk1.u.genblk1.u.genblk1.u.genblk1.u), file:${SURELOG_DIR}/tests/Loop/dut.sv, line:14:6, endln:14:54 + |vpiModuleInst: + \_module_inst: work@test (work@top.u1.genblk1.u.genblk1.u.genblk1.u.genblk1.u.genblk1.u), file:${SURELOG_DIR}/tests/Loop/dut.sv, line:14:6, endln:14:54 |vpiParent: \_gen_scope: (work@top.u1.genblk1.u.genblk1.u.genblk1.u.genblk1.u.genblk1) |vpiName:u @@ -488,7 +488,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:12:14, endln:12:34 |vpiParent: - \_module: work@test (work@top.u1.genblk1.u.genblk1.u.genblk1.u.genblk1.u.genblk1.u), file:${SURELOG_DIR}/tests/Loop/dut.sv, line:14:6, endln:14:54 + \_module_inst: work@test (work@top.u1.genblk1.u.genblk1.u.genblk1.u.genblk1.u.genblk1.u), file:${SURELOG_DIR}/tests/Loop/dut.sv, line:14:6, endln:14:54 |vpiOverriden:1 |vpiRhs: \_constant: , line:12:32, endln:12:34 @@ -503,28 +503,28 @@ design: (work@top) |vpiDefName:work@test |vpiDefFile:${SURELOG_DIR}/tests/Loop/dut.sv |vpiDefLineNo:10 - |vpiModule: - \_module: work@loop (work@top.u2), file:${SURELOG_DIR}/tests/Loop/dut.sv, line:3:4, endln:3:14 + |vpiModuleInst: + \_module_inst: work@loop (work@top.u2), file:${SURELOG_DIR}/tests/Loop/dut.sv, line:3:4, endln:3:14 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/Loop/dut.sv, line:1:1, endln:4:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/Loop/dut.sv, line:1:1, endln:4:10 |vpiName:u2 |vpiFullName:work@top.u2 |vpiDefName:work@loop |vpiDefFile:${SURELOG_DIR}/tests/Loop/dut.sv |vpiDefLineNo:6 |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/Loop/dut.sv, line:1:1, endln:4:10 - |vpiModule: - \_module: work@loop (work@top.u2.u1), file:${SURELOG_DIR}/tests/Loop/dut.sv, line:7:4, endln:7:14 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/Loop/dut.sv, line:1:1, endln:4:10 + |vpiModuleInst: + \_module_inst: work@loop (work@top.u2.u1), file:${SURELOG_DIR}/tests/Loop/dut.sv, line:7:4, endln:7:14 |vpiParent: - \_module: work@loop (work@top.u2), file:${SURELOG_DIR}/tests/Loop/dut.sv, line:3:4, endln:3:14 + \_module_inst: work@loop (work@top.u2), file:${SURELOG_DIR}/tests/Loop/dut.sv, line:3:4, endln:3:14 |vpiName:u1 |vpiFullName:work@top.u2.u1 |vpiDefName:work@loop |vpiDefFile:${SURELOG_DIR}/tests/Loop/dut.sv |vpiDefLineNo:6 |vpiInstance: - \_module: work@loop (work@top.u2), file:${SURELOG_DIR}/tests/Loop/dut.sv, line:3:4, endln:3:14 + \_module_inst: work@loop (work@top.u2), file:${SURELOG_DIR}/tests/Loop/dut.sv, line:3:4, endln:3:14 =================== [ FATAL] : 0 [ SYNTAX] : 0 diff --git a/tests/LoopParam/LoopParam.log b/tests/LoopParam/LoopParam.log index 574408b226..4d6c33df52 100644 --- a/tests/LoopParam/LoopParam.log +++ b/tests/LoopParam/LoopParam.log @@ -73,7 +73,7 @@ n<> u<44> t c<1> l<3:1> el<9:1> === UHDM Object Stats Begin (Non-Elaborated Model) === design 1 -module 4 +module_inst 4 param_assign 4 parameter 4 ref_obj 2997 @@ -82,7 +82,7 @@ ref_obj 2997 === UHDM Object Stats Begin (Elaborated Model) === design 1 -module 4 +module_inst 4 param_assign 4 parameter 4 ref_obj 2997 @@ -100,26 +100,26 @@ design: (work@Foo) |vpiElaborated:1 |vpiName:work@Foo |uhdmallModules: -\_module: work@Foo (work@Foo), file:${SURELOG_DIR}/tests/LoopParam/dut.sv, line:3:1, endln:7:10 +\_module_inst: work@Foo (work@Foo), file:${SURELOG_DIR}/tests/LoopParam/dut.sv, line:3:1, endln:7:10 |vpiParent: \_design: (work@Foo) |vpiFullName:work@Foo |vpiParameter: \_parameter: (work@Foo.P1), line:4:12, endln:4:14 |vpiParent: - \_module: work@Foo (work@Foo), file:${SURELOG_DIR}/tests/LoopParam/dut.sv, line:3:1, endln:7:10 + \_module_inst: work@Foo (work@Foo), file:${SURELOG_DIR}/tests/LoopParam/dut.sv, line:3:1, endln:7:10 |vpiName:P1 |vpiFullName:work@Foo.P1 |vpiParameter: \_parameter: (work@Foo.P2), line:5:12, endln:5:14 |vpiParent: - \_module: work@Foo (work@Foo), file:${SURELOG_DIR}/tests/LoopParam/dut.sv, line:3:1, endln:7:10 + \_module_inst: work@Foo (work@Foo), file:${SURELOG_DIR}/tests/LoopParam/dut.sv, line:3:1, endln:7:10 |vpiName:P2 |vpiFullName:work@Foo.P2 |vpiParamAssign: \_param_assign: , line:4:12, endln:4:19 |vpiParent: - \_module: work@Foo (work@Foo), file:${SURELOG_DIR}/tests/LoopParam/dut.sv, line:3:1, endln:7:10 + \_module_inst: work@Foo (work@Foo), file:${SURELOG_DIR}/tests/LoopParam/dut.sv, line:3:1, endln:7:10 |vpiRhs: \_ref_obj: (P2), line:4:17, endln:4:19 |vpiName:P2 @@ -128,7 +128,7 @@ design: (work@Foo) |vpiParamAssign: \_param_assign: , line:5:12, endln:5:19 |vpiParent: - \_module: work@Foo (work@Foo), file:${SURELOG_DIR}/tests/LoopParam/dut.sv, line:3:1, endln:7:10 + \_module_inst: work@Foo (work@Foo), file:${SURELOG_DIR}/tests/LoopParam/dut.sv, line:3:1, endln:7:10 |vpiRhs: \_ref_obj: (P1), line:5:17, endln:5:19 |vpiName:P1 @@ -136,24 +136,24 @@ design: (work@Foo) \_parameter: (work@Foo.P2), line:5:12, endln:5:14 |vpiDefName:work@Foo |uhdmtopModules: -\_module: work@Foo (work@Foo), file:${SURELOG_DIR}/tests/LoopParam/dut.sv, line:3:1, endln:7:10 +\_module_inst: work@Foo (work@Foo), file:${SURELOG_DIR}/tests/LoopParam/dut.sv, line:3:1, endln:7:10 |vpiName:work@Foo |vpiParameter: \_parameter: (work@Foo.P1), line:4:12, endln:4:14 |vpiParent: - \_module: work@Foo (work@Foo), file:${SURELOG_DIR}/tests/LoopParam/dut.sv, line:3:1, endln:7:10 + \_module_inst: work@Foo (work@Foo), file:${SURELOG_DIR}/tests/LoopParam/dut.sv, line:3:1, endln:7:10 |vpiName:P1 |vpiFullName:work@Foo.P1 |vpiParameter: \_parameter: (work@Foo.P2), line:5:12, endln:5:14 |vpiParent: - \_module: work@Foo (work@Foo), file:${SURELOG_DIR}/tests/LoopParam/dut.sv, line:3:1, endln:7:10 + \_module_inst: work@Foo (work@Foo), file:${SURELOG_DIR}/tests/LoopParam/dut.sv, line:3:1, endln:7:10 |vpiName:P2 |vpiFullName:work@Foo.P2 |vpiParamAssign: \_param_assign: , line:4:12, endln:4:19 |vpiParent: - \_module: work@Foo (work@Foo), file:${SURELOG_DIR}/tests/LoopParam/dut.sv, line:3:1, endln:7:10 + \_module_inst: work@Foo (work@Foo), file:${SURELOG_DIR}/tests/LoopParam/dut.sv, line:3:1, endln:7:10 |vpiRhs: \_ref_obj: (P1), line:4:17, endln:4:19 |vpiName:P1 @@ -164,7 +164,7 @@ design: (work@Foo) |vpiParamAssign: \_param_assign: , line:5:12, endln:5:19 |vpiParent: - \_module: work@Foo (work@Foo), file:${SURELOG_DIR}/tests/LoopParam/dut.sv, line:3:1, endln:7:10 + \_module_inst: work@Foo (work@Foo), file:${SURELOG_DIR}/tests/LoopParam/dut.sv, line:3:1, endln:7:10 |vpiRhs: \_ref_obj: (P1), line:4:17, endln:4:19 |vpiLhs: diff --git a/tests/LoopParam/LoopParam.win.log b/tests/LoopParam/LoopParam.win.log index 8be5d9e5f2..fa1bb8cc0b 100644 --- a/tests/LoopParam/LoopParam.win.log +++ b/tests/LoopParam/LoopParam.win.log @@ -1,7 +1,7 @@ -[INF:CM0023] Creating log file ..\..\build\regression\LoopParam\slpp_all\surelog.log. +[INF:CM0023] Creating log file ${SURELOG_DIR}\build\regression\LoopParam\slpp_all\surelog.log. LIB: work -FILE: dut.sv +FILE: ${SURELOG_DIR}\tests\LoopParam\dut.sv n<> u<0> t<_INVALID_> f<0> l<0:0> n<> u<1> t p<44> s<43> l<3:1> el<1:3> n<> u<2> t p<6> s<3> l<3:1> el<3:7> @@ -47,19 +47,19 @@ n<> u<41> t p<42> c<6> l<3:1> el<7:10> n<> u<42> t p<43> c<41> l<3:1> el<7:10> n<> u<43> t p<44> c<42> l<3:1> el<7:10> n<> u<44> t c<1> l<3:1> el<9:1> -[WRN:PA0205] dut.sv:3:1: No timescale set for "Foo". +[WRN:PA0205] ${SURELOG_DIR}\tests\LoopParam\dut.sv:3:1: No timescale set for "Foo". [INF:CP0300] Compilation... -[INF:CP0303] dut.sv:3:1: Compile module "work@Foo". +[INF:CP0303] ${SURELOG_DIR}\tests\LoopParam\dut.sv:3:1: Compile module "work@Foo". [INF:EL0526] Design Elaboration... -[NTE:EL0503] dut.sv:3:1: Top level module "work@Foo". +[NTE:EL0503] ${SURELOG_DIR}\tests\LoopParam\dut.sv:3:1: Top level module "work@Foo". -[ERR:EL0542] dut.sv:4: Expression loop in instance "work@Foo". +[ERR:EL0542] ${SURELOG_DIR}\tests\LoopParam\dut.sv:4: Expression loop in instance "work@Foo". -[ERR:EL0542] dut.sv:5: Expression loop in instance "work@Foo". +[ERR:EL0542] ${SURELOG_DIR}\tests\LoopParam\dut.sv:5: Expression loop in instance "work@Foo". [NTE:EL0508] Nb Top level modules: 1. @@ -72,26 +72,26 @@ n<> u<44> t c<1> l<3:1> el<9:1> [INF:UH0706] Creating UHDM Model... === UHDM Object Stats Begin (Non-Elaborated Model) === -design 1 -module 4 -param_assign 4 -parameter 4 -ref_obj 297 +design 1 +module_inst 4 +param_assign 4 +parameter 4 +ref_obj 297 === UHDM Object Stats End === [INF:UH0707] Elaborating UHDM... === UHDM Object Stats Begin (Elaborated Model) === -design 1 -module 4 -param_assign 4 -parameter 4 -ref_obj 297 +design 1 +module_inst 4 +param_assign 4 +parameter 4 +ref_obj 297 === UHDM Object Stats End === -[INF:UH0708] Writing UHDM DB: ..\..\build\regression\LoopParam\slpp_all\surelog.uhdm ... +[INF:UH0708] Writing UHDM DB: ${SURELOG_DIR}\build\regression\LoopParam\slpp_all\surelog.uhdm ... -[INF:UH0709] Writing UHDM Html Coverage: ..\..\build\regression\LoopParam\slpp_all\surelog.uhdm.chk.html ... +[INF:UH0709] Writing UHDM Html Coverage: ${SURELOG_DIR}\build\regression\LoopParam\slpp_all\checker\surelog.chk.html ... -[INF:UH0710] Loading UHDM DB: ..\..\build\regression\LoopParam\slpp_all\surelog.uhdm ... +[INF:UH0710] Loading UHDM DB: ${SURELOG_DIR}\build\regression\LoopParam\slpp_all\surelog.uhdm ... [INF:UH0711] Decompiling UHDM... @@ -100,26 +100,26 @@ design: (work@Foo) |vpiElaborated:1 |vpiName:work@Foo |uhdmallModules: -\_module: work@Foo (work@Foo), file:dut.sv, line:3:1, endln:7:10 +\_module_inst: work@Foo (work@Foo), file:${SURELOG_DIR}\tests\LoopParam\dut.sv, line:3:1, endln:7:10 |vpiParent: \_design: (work@Foo) |vpiFullName:work@Foo |vpiParameter: \_parameter: (work@Foo.P1), line:4:12, endln:4:14 |vpiParent: - \_module: work@Foo (work@Foo), file:dut.sv, line:3:1, endln:7:10 + \_module_inst: work@Foo (work@Foo), file:${SURELOG_DIR}\tests\LoopParam\dut.sv, line:3:1, endln:7:10 |vpiName:P1 |vpiFullName:work@Foo.P1 |vpiParameter: \_parameter: (work@Foo.P2), line:5:12, endln:5:14 |vpiParent: - \_module: work@Foo (work@Foo), file:dut.sv, line:3:1, endln:7:10 + \_module_inst: work@Foo (work@Foo), file:${SURELOG_DIR}\tests\LoopParam\dut.sv, line:3:1, endln:7:10 |vpiName:P2 |vpiFullName:work@Foo.P2 |vpiParamAssign: \_param_assign: , line:4:12, endln:4:19 |vpiParent: - \_module: work@Foo (work@Foo), file:dut.sv, line:3:1, endln:7:10 + \_module_inst: work@Foo (work@Foo), file:${SURELOG_DIR}\tests\LoopParam\dut.sv, line:3:1, endln:7:10 |vpiRhs: \_ref_obj: (P2), line:4:17, endln:4:19 |vpiName:P2 @@ -128,7 +128,7 @@ design: (work@Foo) |vpiParamAssign: \_param_assign: , line:5:12, endln:5:19 |vpiParent: - \_module: work@Foo (work@Foo), file:dut.sv, line:3:1, endln:7:10 + \_module_inst: work@Foo (work@Foo), file:${SURELOG_DIR}\tests\LoopParam\dut.sv, line:3:1, endln:7:10 |vpiRhs: \_ref_obj: (P1), line:5:17, endln:5:19 |vpiName:P1 @@ -136,24 +136,24 @@ design: (work@Foo) \_parameter: (work@Foo.P2), line:5:12, endln:5:14 |vpiDefName:work@Foo |uhdmtopModules: -\_module: work@Foo (work@Foo), file:dut.sv, line:3:1, endln:7:10 +\_module_inst: work@Foo (work@Foo), file:${SURELOG_DIR}\tests\LoopParam\dut.sv, line:3:1, endln:7:10 |vpiName:work@Foo |vpiParameter: \_parameter: (work@Foo.P1), line:4:12, endln:4:14 |vpiParent: - \_module: work@Foo (work@Foo), file:dut.sv, line:3:1, endln:7:10 + \_module_inst: work@Foo (work@Foo), file:${SURELOG_DIR}\tests\LoopParam\dut.sv, line:3:1, endln:7:10 |vpiName:P1 |vpiFullName:work@Foo.P1 |vpiParameter: \_parameter: (work@Foo.P2), line:5:12, endln:5:14 |vpiParent: - \_module: work@Foo (work@Foo), file:dut.sv, line:3:1, endln:7:10 + \_module_inst: work@Foo (work@Foo), file:${SURELOG_DIR}\tests\LoopParam\dut.sv, line:3:1, endln:7:10 |vpiName:P2 |vpiFullName:work@Foo.P2 |vpiParamAssign: \_param_assign: , line:4:12, endln:4:19 |vpiParent: - \_module: work@Foo (work@Foo), file:dut.sv, line:3:1, endln:7:10 + \_module_inst: work@Foo (work@Foo), file:${SURELOG_DIR}\tests\LoopParam\dut.sv, line:3:1, endln:7:10 |vpiRhs: \_ref_obj: (P1), line:4:17, endln:4:19 |vpiName:P1 @@ -164,7 +164,7 @@ design: (work@Foo) |vpiParamAssign: \_param_assign: , line:5:12, endln:5:19 |vpiParent: - \_module: work@Foo (work@Foo), file:dut.sv, line:3:1, endln:7:10 + \_module_inst: work@Foo (work@Foo), file:${SURELOG_DIR}\tests\LoopParam\dut.sv, line:3:1, endln:7:10 |vpiRhs: \_ref_obj: (P1), line:4:17, endln:4:19 |vpiLhs: @@ -180,5 +180,4 @@ design: (work@Foo) [ NOTE] : 5 -[roundtrip]: ${SURELOG_DIR}\tests\LoopParam\dut.sv | ${SURELOG_DIR}\build\regression\LoopParam\roundtrip\dut_000.sv | 0 | 7 | - +[roundtrip]: ${SURELOG_DIR}\tests\LoopParam\dut.sv | ${SURELOG_DIR}\build\regression\LoopParam\roundtrip\dut_000.sv | 0 | 7 | \ No newline at end of file diff --git a/tests/LoopParamOver/LoopParamOver.log b/tests/LoopParamOver/LoopParamOver.log index 1f1cab71e5..4b10648bf2 100644 --- a/tests/LoopParamOver/LoopParamOver.log +++ b/tests/LoopParamOver/LoopParamOver.log @@ -169,7 +169,7 @@ n<> u<128> t c<1> l<1:1> el<15:1> constant 1 design 1 int_typespec 29 -module 8 +module_inst 8 operation 3 param_assign 10 parameter 10 @@ -181,7 +181,7 @@ ref_obj 4528 constant 1 design 1 int_typespec 29 -module 8 +module_inst 8 operation 3 param_assign 10 parameter 10 @@ -200,14 +200,14 @@ design: (work@top) |vpiElaborated:1 |vpiName:work@top |uhdmallModules: -\_module: work@Foo (work@Foo), file:${SURELOG_DIR}/tests/LoopParamOver/dut.sv, line:1:1, endln:5:10 +\_module_inst: work@Foo (work@Foo), file:${SURELOG_DIR}/tests/LoopParamOver/dut.sv, line:1:1, endln:5:10 |vpiParent: \_design: (work@top) |vpiFullName:work@Foo |vpiParameter: \_parameter: (work@Foo.P1), line:2:12, endln:2:14 |vpiParent: - \_module: work@Foo (work@Foo), file:${SURELOG_DIR}/tests/LoopParamOver/dut.sv, line:1:1, endln:5:10 + \_module_inst: work@Foo (work@Foo), file:${SURELOG_DIR}/tests/LoopParamOver/dut.sv, line:1:1, endln:5:10 |UINT:10 |vpiTypespec: \_int_typespec: @@ -216,13 +216,13 @@ design: (work@top) |vpiParameter: \_parameter: (work@Foo.P2), line:3:12, endln:3:14 |vpiParent: - \_module: work@Foo (work@Foo), file:${SURELOG_DIR}/tests/LoopParamOver/dut.sv, line:1:1, endln:5:10 + \_module_inst: work@Foo (work@Foo), file:${SURELOG_DIR}/tests/LoopParamOver/dut.sv, line:1:1, endln:5:10 |vpiName:P2 |vpiFullName:work@Foo.P2 |vpiParamAssign: \_param_assign: , line:2:12, endln:2:19 |vpiParent: - \_module: work@Foo (work@Foo), file:${SURELOG_DIR}/tests/LoopParamOver/dut.sv, line:1:1, endln:5:10 + \_module_inst: work@Foo (work@Foo), file:${SURELOG_DIR}/tests/LoopParamOver/dut.sv, line:1:1, endln:5:10 |vpiRhs: \_constant: , line:2:17, endln:2:19 |vpiDecompile:10 @@ -236,7 +236,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:3:12, endln:3:24 |vpiParent: - \_module: work@Foo (work@Foo), file:${SURELOG_DIR}/tests/LoopParamOver/dut.sv, line:1:1, endln:5:10 + \_module_inst: work@Foo (work@Foo), file:${SURELOG_DIR}/tests/LoopParamOver/dut.sv, line:1:1, endln:5:10 |vpiRhs: \_operation: , line:3:17, endln:3:24 |vpiOpType:24 @@ -254,32 +254,32 @@ design: (work@top) \_parameter: (work@Foo.P2), line:3:12, endln:3:14 |vpiDefName:work@Foo |uhdmallModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/LoopParamOver/dut.sv, line:8:1, endln:13:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/LoopParamOver/dut.sv, line:8:1, endln:13:10 |vpiParent: \_design: (work@top) |vpiFullName:work@top |vpiParameter: \_parameter: (work@top.P3), line:9:13, endln:9:15 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/LoopParamOver/dut.sv, line:8:1, endln:13:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/LoopParamOver/dut.sv, line:8:1, endln:13:10 |vpiName:P3 |vpiFullName:work@top.P3 |vpiParameter: \_parameter: (work@top.P2), line:10:13, endln:10:15 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/LoopParamOver/dut.sv, line:8:1, endln:13:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/LoopParamOver/dut.sv, line:8:1, endln:13:10 |vpiName:P2 |vpiFullName:work@top.P2 |vpiParameter: \_parameter: (work@top.P1), line:11:13, endln:11:15 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/LoopParamOver/dut.sv, line:8:1, endln:13:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/LoopParamOver/dut.sv, line:8:1, endln:13:10 |vpiName:P1 |vpiFullName:work@top.P1 |vpiParamAssign: \_param_assign: , line:9:13, endln:9:20 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/LoopParamOver/dut.sv, line:8:1, endln:13:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/LoopParamOver/dut.sv, line:8:1, endln:13:10 |vpiRhs: \_ref_obj: (P1), line:9:18, endln:9:20 |vpiName:P1 @@ -288,7 +288,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:10:13, endln:10:20 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/LoopParamOver/dut.sv, line:8:1, endln:13:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/LoopParamOver/dut.sv, line:8:1, endln:13:10 |vpiRhs: \_ref_obj: (P3), line:10:18, endln:10:20 |vpiName:P3 @@ -297,7 +297,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:11:13, endln:11:20 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/LoopParamOver/dut.sv, line:8:1, endln:13:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/LoopParamOver/dut.sv, line:8:1, endln:13:10 |vpiRhs: \_ref_obj: (P2), line:11:18, endln:11:20 |vpiName:P2 @@ -305,30 +305,30 @@ design: (work@top) \_parameter: (work@top.P1), line:11:13, endln:11:15 |vpiDefName:work@top |uhdmtopModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/LoopParamOver/dut.sv, line:8:1, endln:13:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/LoopParamOver/dut.sv, line:8:1, endln:13:10 |vpiName:work@top |vpiParameter: \_parameter: (work@top.P3), line:9:13, endln:9:15 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/LoopParamOver/dut.sv, line:8:1, endln:13:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/LoopParamOver/dut.sv, line:8:1, endln:13:10 |vpiName:P3 |vpiFullName:work@top.P3 |vpiParameter: \_parameter: (work@top.P2), line:10:13, endln:10:15 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/LoopParamOver/dut.sv, line:8:1, endln:13:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/LoopParamOver/dut.sv, line:8:1, endln:13:10 |vpiName:P2 |vpiFullName:work@top.P2 |vpiParameter: \_parameter: (work@top.P1), line:11:13, endln:11:15 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/LoopParamOver/dut.sv, line:8:1, endln:13:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/LoopParamOver/dut.sv, line:8:1, endln:13:10 |vpiName:P1 |vpiFullName:work@top.P1 |vpiParamAssign: \_param_assign: , line:9:13, endln:9:20 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/LoopParamOver/dut.sv, line:8:1, endln:13:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/LoopParamOver/dut.sv, line:8:1, endln:13:10 |vpiRhs: \_ref_obj: (P2), line:9:18, endln:9:20 |vpiName:P2 @@ -339,7 +339,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:10:13, endln:10:20 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/LoopParamOver/dut.sv, line:8:1, endln:13:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/LoopParamOver/dut.sv, line:8:1, endln:13:10 |vpiRhs: \_ref_obj: (P2), line:10:18, endln:10:20 |vpiTypespec: @@ -352,7 +352,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:11:13, endln:11:20 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/LoopParamOver/dut.sv, line:8:1, endln:13:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/LoopParamOver/dut.sv, line:8:1, endln:13:10 |vpiRhs: \_ref_obj: (P2), line:10:18, endln:10:20 |vpiLhs: @@ -360,16 +360,16 @@ design: (work@top) |vpiDefName:work@top |vpiTop:1 |vpiTopModule:1 - |vpiModule: - \_module: work@Foo (work@top.sub), file:${SURELOG_DIR}/tests/LoopParamOver/dut.sv, line:12:1, endln:12:22 + |vpiModuleInst: + \_module_inst: work@Foo (work@top.sub), file:${SURELOG_DIR}/tests/LoopParamOver/dut.sv, line:12:1, endln:12:22 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/LoopParamOver/dut.sv, line:8:1, endln:13:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/LoopParamOver/dut.sv, line:8:1, endln:13:10 |vpiName:sub |vpiFullName:work@top.sub |vpiParameter: \_parameter: (work@top.sub.P1), line:2:12, endln:2:14 |vpiParent: - \_module: work@Foo (work@top.sub), file:${SURELOG_DIR}/tests/LoopParamOver/dut.sv, line:12:1, endln:12:22 + \_module_inst: work@Foo (work@top.sub), file:${SURELOG_DIR}/tests/LoopParamOver/dut.sv, line:12:1, endln:12:22 |UINT:10 |vpiTypespec: \_int_typespec: @@ -380,13 +380,13 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.sub.P2), line:3:12, endln:3:14 |vpiParent: - \_module: work@Foo (work@top.sub), file:${SURELOG_DIR}/tests/LoopParamOver/dut.sv, line:12:1, endln:12:22 + \_module_inst: work@Foo (work@top.sub), file:${SURELOG_DIR}/tests/LoopParamOver/dut.sv, line:12:1, endln:12:22 |vpiName:P2 |vpiFullName:work@top.sub.P2 |vpiParamAssign: \_param_assign: , line:2:12, endln:2:19 |vpiParent: - \_module: work@Foo (work@top.sub), file:${SURELOG_DIR}/tests/LoopParamOver/dut.sv, line:12:1, endln:12:22 + \_module_inst: work@Foo (work@top.sub), file:${SURELOG_DIR}/tests/LoopParamOver/dut.sv, line:12:1, endln:12:22 |vpiOverriden:1 |vpiRhs: \_ref_obj: (P2), line:10:18, endln:10:20 @@ -395,7 +395,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:3:12, endln:3:24 |vpiParent: - \_module: work@Foo (work@top.sub), file:${SURELOG_DIR}/tests/LoopParamOver/dut.sv, line:12:1, endln:12:22 + \_module_inst: work@Foo (work@top.sub), file:${SURELOG_DIR}/tests/LoopParamOver/dut.sv, line:12:1, endln:12:22 |vpiOverriden:1 |vpiRhs: \_operation: , line:3:17, endln:3:24 @@ -436,7 +436,7 @@ design: (work@top) |vpiDefFile:${SURELOG_DIR}/tests/LoopParamOver/dut.sv |vpiDefLineNo:1 |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/LoopParamOver/dut.sv, line:8:1, endln:13:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/LoopParamOver/dut.sv, line:8:1, endln:13:10 =================== [ FATAL] : 0 [ SYNTAX] : 0 diff --git a/tests/LoopParamOver/LoopParamOver.win.log b/tests/LoopParamOver/LoopParamOver.win.log index baa9f0a9ef..10fcfc4792 100644 --- a/tests/LoopParamOver/LoopParamOver.win.log +++ b/tests/LoopParamOver/LoopParamOver.win.log @@ -1,7 +1,7 @@ -[INF:CM0023] Creating log file ..\..\build\regression\LoopParamOver\slpp_all\surelog.log. +[INF:CM0023] Creating log file ${SURELOG_DIR}\build\regression\LoopParamOver\slpp_all\surelog.log. LIB: work -FILE: dut.sv +FILE: ${SURELOG_DIR}\tests\LoopParamOver\dut.sv n<> u<0> t<_INVALID_> f<0> l<0:0> n<> u<1> t p<128> s<127> l<1:1> el<1:0> n<> u<2> t p<6> s<3> l<1:1> el<1:7> @@ -131,29 +131,29 @@ n<> u<125> t p<126> c<53> l<8:1> el<13:10> n<> u<126> t p<127> c<125> l<8:1> el<13:10> n<> u<127> t p<128> c<48> l<1:1> el<13:10> n<> u<128> t c<1> l<1:1> el<15:1> -[WRN:PA0205] dut.sv:1:1: No timescale set for "Foo". +[WRN:PA0205] ${SURELOG_DIR}\tests\LoopParamOver\dut.sv:1:1: No timescale set for "Foo". -[WRN:PA0205] dut.sv:8:1: No timescale set for "top". +[WRN:PA0205] ${SURELOG_DIR}\tests\LoopParamOver\dut.sv:8:1: No timescale set for "top". [INF:CP0300] Compilation... -[INF:CP0303] dut.sv:1:1: Compile module "work@Foo". +[INF:CP0303] ${SURELOG_DIR}\tests\LoopParamOver\dut.sv:1:1: Compile module "work@Foo". -[INF:CP0303] dut.sv:8:1: Compile module "work@top". +[INF:CP0303] ${SURELOG_DIR}\tests\LoopParamOver\dut.sv:8:1: Compile module "work@top". [INF:EL0526] Design Elaboration... -[NTE:EL0503] dut.sv:8:1: Top level module "work@top". +[NTE:EL0503] ${SURELOG_DIR}\tests\LoopParamOver\dut.sv:8:1: Top level module "work@top". -[ERR:EL0542] dut.sv:9: Expression loop in instance "work@top". +[ERR:EL0542] ${SURELOG_DIR}\tests\LoopParamOver\dut.sv:9: Expression loop in instance "work@top". -[ERR:EL0542] dut.sv:10: Expression loop in instance "work@top". +[ERR:EL0542] ${SURELOG_DIR}\tests\LoopParamOver\dut.sv:10: Expression loop in instance "work@top". -[ERR:EL0542] dut.sv:11: Expression loop in instance "work@top". +[ERR:EL0542] ${SURELOG_DIR}\tests\LoopParamOver\dut.sv:11: Expression loop in instance "work@top". -[ERR:EL0542] dut.sv:10: Expression loop in instance "work@top.sub". +[ERR:EL0542] ${SURELOG_DIR}\tests\LoopParamOver\dut.sv:10: Expression loop in instance "work@top.sub". -[ERR:EL0542] dut.sv:3: Expression loop in instance "work@top.sub". +[ERR:EL0542] ${SURELOG_DIR}\tests\LoopParamOver\dut.sv:3: Expression loop in instance "work@top.sub". [NTE:EL0508] Nb Top level modules: 1. @@ -166,32 +166,32 @@ n<> u<128> t c<1> l<1:1> el<15:1> [INF:UH0706] Creating UHDM Model... === UHDM Object Stats Begin (Non-Elaborated Model) === -constant 1 -design 1 -int_typespec 29 -module 8 -operation 3 -param_assign 10 -parameter 10 -ref_obj 478 +constant 1 +design 1 +int_typespec 29 +module_inst 8 +operation 3 +param_assign 10 +parameter 10 +ref_obj 478 === UHDM Object Stats End === [INF:UH0707] Elaborating UHDM... === UHDM Object Stats Begin (Elaborated Model) === -constant 1 -design 1 -int_typespec 29 -module 8 -operation 3 -param_assign 10 -parameter 10 -ref_obj 478 +constant 1 +design 1 +int_typespec 29 +module_inst 8 +operation 3 +param_assign 10 +parameter 10 +ref_obj 478 === UHDM Object Stats End === -[INF:UH0708] Writing UHDM DB: ..\..\build\regression\LoopParamOver\slpp_all\surelog.uhdm ... +[INF:UH0708] Writing UHDM DB: ${SURELOG_DIR}\build\regression\LoopParamOver\slpp_all\surelog.uhdm ... -[INF:UH0709] Writing UHDM Html Coverage: ..\..\build\regression\LoopParamOver\slpp_all\surelog.uhdm.chk.html ... +[INF:UH0709] Writing UHDM Html Coverage: ${SURELOG_DIR}\build\regression\LoopParamOver\slpp_all\checker\surelog.chk.html ... -[INF:UH0710] Loading UHDM DB: ..\..\build\regression\LoopParamOver\slpp_all\surelog.uhdm ... +[INF:UH0710] Loading UHDM DB: ${SURELOG_DIR}\build\regression\LoopParamOver\slpp_all\surelog.uhdm ... [INF:UH0711] Decompiling UHDM... @@ -200,14 +200,14 @@ design: (work@top) |vpiElaborated:1 |vpiName:work@top |uhdmallModules: -\_module: work@Foo (work@Foo), file:dut.sv, line:1:1, endln:5:10 +\_module_inst: work@Foo (work@Foo), file:${SURELOG_DIR}\tests\LoopParamOver\dut.sv, line:1:1, endln:5:10 |vpiParent: \_design: (work@top) |vpiFullName:work@Foo |vpiParameter: \_parameter: (work@Foo.P1), line:2:12, endln:2:14 |vpiParent: - \_module: work@Foo (work@Foo), file:dut.sv, line:1:1, endln:5:10 + \_module_inst: work@Foo (work@Foo), file:${SURELOG_DIR}\tests\LoopParamOver\dut.sv, line:1:1, endln:5:10 |UINT:10 |vpiTypespec: \_int_typespec: @@ -216,13 +216,13 @@ design: (work@top) |vpiParameter: \_parameter: (work@Foo.P2), line:3:12, endln:3:14 |vpiParent: - \_module: work@Foo (work@Foo), file:dut.sv, line:1:1, endln:5:10 + \_module_inst: work@Foo (work@Foo), file:${SURELOG_DIR}\tests\LoopParamOver\dut.sv, line:1:1, endln:5:10 |vpiName:P2 |vpiFullName:work@Foo.P2 |vpiParamAssign: \_param_assign: , line:2:12, endln:2:19 |vpiParent: - \_module: work@Foo (work@Foo), file:dut.sv, line:1:1, endln:5:10 + \_module_inst: work@Foo (work@Foo), file:${SURELOG_DIR}\tests\LoopParamOver\dut.sv, line:1:1, endln:5:10 |vpiRhs: \_constant: , line:2:17, endln:2:19 |vpiDecompile:10 @@ -236,7 +236,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:3:12, endln:3:24 |vpiParent: - \_module: work@Foo (work@Foo), file:dut.sv, line:1:1, endln:5:10 + \_module_inst: work@Foo (work@Foo), file:${SURELOG_DIR}\tests\LoopParamOver\dut.sv, line:1:1, endln:5:10 |vpiRhs: \_operation: , line:3:17, endln:3:24 |vpiOpType:24 @@ -254,32 +254,32 @@ design: (work@top) \_parameter: (work@Foo.P2), line:3:12, endln:3:14 |vpiDefName:work@Foo |uhdmallModules: -\_module: work@top (work@top), file:dut.sv, line:8:1, endln:13:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}\tests\LoopParamOver\dut.sv, line:8:1, endln:13:10 |vpiParent: \_design: (work@top) |vpiFullName:work@top |vpiParameter: \_parameter: (work@top.P3), line:9:13, endln:9:15 |vpiParent: - \_module: work@top (work@top), file:dut.sv, line:8:1, endln:13:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}\tests\LoopParamOver\dut.sv, line:8:1, endln:13:10 |vpiName:P3 |vpiFullName:work@top.P3 |vpiParameter: \_parameter: (work@top.P2), line:10:13, endln:10:15 |vpiParent: - \_module: work@top (work@top), file:dut.sv, line:8:1, endln:13:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}\tests\LoopParamOver\dut.sv, line:8:1, endln:13:10 |vpiName:P2 |vpiFullName:work@top.P2 |vpiParameter: \_parameter: (work@top.P1), line:11:13, endln:11:15 |vpiParent: - \_module: work@top (work@top), file:dut.sv, line:8:1, endln:13:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}\tests\LoopParamOver\dut.sv, line:8:1, endln:13:10 |vpiName:P1 |vpiFullName:work@top.P1 |vpiParamAssign: \_param_assign: , line:9:13, endln:9:20 |vpiParent: - \_module: work@top (work@top), file:dut.sv, line:8:1, endln:13:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}\tests\LoopParamOver\dut.sv, line:8:1, endln:13:10 |vpiRhs: \_ref_obj: (P1), line:9:18, endln:9:20 |vpiName:P1 @@ -288,7 +288,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:10:13, endln:10:20 |vpiParent: - \_module: work@top (work@top), file:dut.sv, line:8:1, endln:13:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}\tests\LoopParamOver\dut.sv, line:8:1, endln:13:10 |vpiRhs: \_ref_obj: (P3), line:10:18, endln:10:20 |vpiName:P3 @@ -297,7 +297,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:11:13, endln:11:20 |vpiParent: - \_module: work@top (work@top), file:dut.sv, line:8:1, endln:13:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}\tests\LoopParamOver\dut.sv, line:8:1, endln:13:10 |vpiRhs: \_ref_obj: (P2), line:11:18, endln:11:20 |vpiName:P2 @@ -305,30 +305,30 @@ design: (work@top) \_parameter: (work@top.P1), line:11:13, endln:11:15 |vpiDefName:work@top |uhdmtopModules: -\_module: work@top (work@top), file:dut.sv, line:8:1, endln:13:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}\tests\LoopParamOver\dut.sv, line:8:1, endln:13:10 |vpiName:work@top |vpiParameter: \_parameter: (work@top.P3), line:9:13, endln:9:15 |vpiParent: - \_module: work@top (work@top), file:dut.sv, line:8:1, endln:13:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}\tests\LoopParamOver\dut.sv, line:8:1, endln:13:10 |vpiName:P3 |vpiFullName:work@top.P3 |vpiParameter: \_parameter: (work@top.P2), line:10:13, endln:10:15 |vpiParent: - \_module: work@top (work@top), file:dut.sv, line:8:1, endln:13:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}\tests\LoopParamOver\dut.sv, line:8:1, endln:13:10 |vpiName:P2 |vpiFullName:work@top.P2 |vpiParameter: \_parameter: (work@top.P1), line:11:13, endln:11:15 |vpiParent: - \_module: work@top (work@top), file:dut.sv, line:8:1, endln:13:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}\tests\LoopParamOver\dut.sv, line:8:1, endln:13:10 |vpiName:P1 |vpiFullName:work@top.P1 |vpiParamAssign: \_param_assign: , line:9:13, endln:9:20 |vpiParent: - \_module: work@top (work@top), file:dut.sv, line:8:1, endln:13:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}\tests\LoopParamOver\dut.sv, line:8:1, endln:13:10 |vpiRhs: \_ref_obj: (P2), line:9:18, endln:9:20 |vpiName:P2 @@ -339,7 +339,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:10:13, endln:10:20 |vpiParent: - \_module: work@top (work@top), file:dut.sv, line:8:1, endln:13:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}\tests\LoopParamOver\dut.sv, line:8:1, endln:13:10 |vpiRhs: \_ref_obj: (P2), line:10:18, endln:10:20 |vpiTypespec: @@ -352,7 +352,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:11:13, endln:11:20 |vpiParent: - \_module: work@top (work@top), file:dut.sv, line:8:1, endln:13:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}\tests\LoopParamOver\dut.sv, line:8:1, endln:13:10 |vpiRhs: \_ref_obj: (P2), line:10:18, endln:10:20 |vpiLhs: @@ -360,16 +360,16 @@ design: (work@top) |vpiDefName:work@top |vpiTop:1 |vpiTopModule:1 - |vpiModule: - \_module: work@Foo (work@top.sub), file:dut.sv, line:12:1, endln:12:22 + |vpiModuleInst: + \_module_inst: work@Foo (work@top.sub), file:${SURELOG_DIR}\tests\LoopParamOver\dut.sv, line:12:1, endln:12:22 |vpiParent: - \_module: work@top (work@top), file:dut.sv, line:8:1, endln:13:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}\tests\LoopParamOver\dut.sv, line:8:1, endln:13:10 |vpiName:sub |vpiFullName:work@top.sub |vpiParameter: \_parameter: (work@top.sub.P1), line:2:12, endln:2:14 |vpiParent: - \_module: work@Foo (work@top.sub), file:dut.sv, line:12:1, endln:12:22 + \_module_inst: work@Foo (work@top.sub), file:${SURELOG_DIR}\tests\LoopParamOver\dut.sv, line:12:1, endln:12:22 |UINT:10 |vpiTypespec: \_int_typespec: @@ -380,13 +380,13 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.sub.P2), line:3:12, endln:3:14 |vpiParent: - \_module: work@Foo (work@top.sub), file:dut.sv, line:12:1, endln:12:22 + \_module_inst: work@Foo (work@top.sub), file:${SURELOG_DIR}\tests\LoopParamOver\dut.sv, line:12:1, endln:12:22 |vpiName:P2 |vpiFullName:work@top.sub.P2 |vpiParamAssign: \_param_assign: , line:2:12, endln:2:19 |vpiParent: - \_module: work@Foo (work@top.sub), file:dut.sv, line:12:1, endln:12:22 + \_module_inst: work@Foo (work@top.sub), file:${SURELOG_DIR}\tests\LoopParamOver\dut.sv, line:12:1, endln:12:22 |vpiOverriden:1 |vpiRhs: \_ref_obj: (P2), line:10:18, endln:10:20 @@ -395,7 +395,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:3:12, endln:3:24 |vpiParent: - \_module: work@Foo (work@top.sub), file:dut.sv, line:12:1, endln:12:22 + \_module_inst: work@Foo (work@top.sub), file:${SURELOG_DIR}\tests\LoopParamOver\dut.sv, line:12:1, endln:12:22 |vpiOverriden:1 |vpiRhs: \_operation: , line:3:17, endln:3:24 @@ -433,10 +433,10 @@ design: (work@top) |vpiLhs: \_parameter: (work@top.sub.P2), line:3:12, endln:3:14 |vpiDefName:work@Foo - |vpiDefFile:dut.sv + |vpiDefFile:${SURELOG_DIR}\tests\LoopParamOver\dut.sv |vpiDefLineNo:1 |vpiInstance: - \_module: work@top (work@top), file:dut.sv, line:8:1, endln:13:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}\tests\LoopParamOver\dut.sv, line:8:1, endln:13:10 =================== [ FATAL] : 0 [ SYNTAX] : 0 @@ -445,5 +445,4 @@ design: (work@top) [ NOTE] : 5 -[roundtrip]: ${SURELOG_DIR}\tests\LoopParamOver\dut.sv | ${SURELOG_DIR}\build\regression\LoopParamOver\roundtrip\dut_000.sv | 1 | 13 | - +[roundtrip]: ${SURELOG_DIR}\tests\LoopParamOver\dut.sv | ${SURELOG_DIR}\build\regression\LoopParamOver\roundtrip\dut_000.sv | 1 | 13 | \ No newline at end of file diff --git a/tests/LoopVar/LoopVar.log b/tests/LoopVar/LoopVar.log index d6ac880440..ff09fa633e 100644 --- a/tests/LoopVar/LoopVar.log +++ b/tests/LoopVar/LoopVar.log @@ -99,7 +99,7 @@ initial 1 int_typespec 2 int_var 2 logic_net 1 -module 4 +module_inst 4 operation 1 range 1 ref_obj 4 @@ -122,7 +122,7 @@ initial 2 int_typespec 2 int_var 3 logic_net 1 -module 4 +module_inst 4 operation 1 range 1 ref_obj 7 @@ -142,7 +142,7 @@ design: (work@dut) |vpiElaborated:1 |vpiName:work@dut |uhdmallModules: -\_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/LoopVar/dut.sv, line:1:1, endln:9:10 +\_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/LoopVar/dut.sv, line:1:1, endln:9:10 |vpiParent: \_design: (work@dut) |vpiFullName:work@dut @@ -150,13 +150,13 @@ design: (work@dut) |vpiNet: \_logic_net: (work@dut.array), line:2:9, endln:2:14 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/LoopVar/dut.sv, line:1:1, endln:9:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/LoopVar/dut.sv, line:1:1, endln:9:10 |vpiName:array |vpiFullName:work@dut.array |vpiProcess: \_initial: , line:4:5, endln:7:8 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/LoopVar/dut.sv, line:1:1, endln:9:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/LoopVar/dut.sv, line:1:1, endln:9:10 |vpiStmt: \_begin: (work@dut), line:4:13, endln:7:8 |vpiParent: @@ -214,12 +214,12 @@ design: (work@dut) |vpiActual: \_int_var: (i), line:5:23, endln:5:24 |uhdmtopModules: -\_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/LoopVar/dut.sv, line:1:1, endln:9:10 +\_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/LoopVar/dut.sv, line:1:1, endln:9:10 |vpiName:work@dut |vpiVariables: \_array_var: (work@dut.array), line:2:9, endln:2:18 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/LoopVar/dut.sv, line:1:1, endln:9:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/LoopVar/dut.sv, line:1:1, endln:9:10 |vpiSize:16 |vpiTypespec: \_array_typespec: @@ -268,7 +268,7 @@ design: (work@dut) |vpiProcess: \_initial: , line:4:5, endln:7:8 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/LoopVar/dut.sv, line:1:1, endln:9:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/LoopVar/dut.sv, line:1:1, endln:9:10 |vpiStmt: \_begin: (work@dut), line:4:13, endln:7:8 |vpiParent: diff --git a/tests/LowMemPkg/LowMemPkg.log b/tests/LowMemPkg/LowMemPkg.log index 969ea7b2d0..b2c62ddb5f 100644 --- a/tests/LowMemPkg/LowMemPkg.log +++ b/tests/LowMemPkg/LowMemPkg.log @@ -93,7 +93,7 @@ include_file_info 1 logic_net 2 logic_typespec 4 logic_var 2 -module 2 +module_inst 2 package 3 === UHDM Object Stats End === [INF:UH0707] Elaborating UHDM... @@ -104,7 +104,7 @@ include_file_info 1 logic_net 2 logic_typespec 4 logic_var 2 -module 2 +module_inst 2 package 3 === UHDM Object Stats End === [INF:UH0708] Writing UHDM DB: ${SURELOG_DIR}/build/regression/LowMemPkg/slpp_all/surelog.uhdm ... @@ -145,14 +145,14 @@ design: (work@top) |vpiTypedef: \_logic_typespec: (wddr_pkg::my_logic), line:20:9, endln:20:14 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/LowMemPkg/dut.sv, line:4:1, endln:8:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/LowMemPkg/dut.sv, line:4:1, endln:8:10 |vpiName:wddr_pkg::my_logic |vpiInstance: \_package: wddr_pkg (wddr_pkg::), file:${SURELOG_DIR}/tests/LowMemPkg/wddr_pkg.sv, line:19:1, endln:22:11 |vpiDefName:wddr_pkg |vpiTop:1 |uhdmallModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/LowMemPkg/dut.sv, line:4:1, endln:8:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/LowMemPkg/dut.sv, line:4:1, endln:8:10 |vpiParent: \_design: (work@top) |vpiFullName:work@top @@ -162,24 +162,24 @@ design: (work@top) |vpiNet: \_logic_net: (work@top.a), line:5:13, endln:5:14 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/LowMemPkg/dut.sv, line:4:1, endln:8:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/LowMemPkg/dut.sv, line:4:1, endln:8:10 |vpiName:a |vpiFullName:work@top.a |vpiNetType:36 |vpiNet: \_logic_net: (work@top.b), line:6:10, endln:6:11 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/LowMemPkg/dut.sv, line:4:1, endln:8:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/LowMemPkg/dut.sv, line:4:1, endln:8:10 |vpiName:b |vpiFullName:work@top.b |vpiNetType:36 |uhdmtopModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/LowMemPkg/dut.sv, line:4:1, endln:8:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/LowMemPkg/dut.sv, line:4:1, endln:8:10 |vpiName:work@top |vpiVariables: \_logic_var: (work@top.a), line:5:13, endln:5:14 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/LowMemPkg/dut.sv, line:4:1, endln:8:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/LowMemPkg/dut.sv, line:4:1, endln:8:10 |vpiTypespec: \_logic_typespec: (wddr_pkg::my_logic), line:20:9, endln:20:14 |vpiName:a @@ -188,7 +188,7 @@ design: (work@top) |vpiVariables: \_logic_var: (work@top.b), line:6:10, endln:6:11 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/LowMemPkg/dut.sv, line:4:1, endln:8:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/LowMemPkg/dut.sv, line:4:1, endln:8:10 |vpiTypespec: \_logic_typespec: , line:6:4, endln:6:9 |vpiName:b diff --git a/tests/MBAdder/MBadder.log b/tests/MBAdder/MBadder.log index 37b9f30db9..5ebe7028d0 100644 --- a/tests/MBAdder/MBadder.log +++ b/tests/MBAdder/MBadder.log @@ -48,7 +48,7 @@ io_decl 11 logic_net 10 logic_typespec 13 logic_var 1 -module 4 +module_inst 4 operation 3 package 2 port 10 @@ -75,7 +75,7 @@ io_decl 22 logic_net 10 logic_typespec 13 logic_var 1 -module 4 +module_inst 4 operation 6 package 2 port 15 @@ -571,7 +571,7 @@ design: (work@MultibitAdder) \_int_typespec: |vpiSigned:1 |uhdmallModules: -\_module: work@MultibitAdder (work@MultibitAdder), file:${SURELOG_DIR}/tests/MBAdder/dut.sv, line:1:1, endln:7:10 +\_module_inst: work@MultibitAdder (work@MultibitAdder), file:${SURELOG_DIR}/tests/MBAdder/dut.sv, line:1:1, endln:7:10 |vpiParent: \_design: (work@MultibitAdder) |vpiFullName:work@MultibitAdder @@ -579,37 +579,37 @@ design: (work@MultibitAdder) |vpiNet: \_logic_net: (work@MultibitAdder.a), line:1:22, endln:1:23 |vpiParent: - \_module: work@MultibitAdder (work@MultibitAdder), file:${SURELOG_DIR}/tests/MBAdder/dut.sv, line:1:1, endln:7:10 + \_module_inst: work@MultibitAdder (work@MultibitAdder), file:${SURELOG_DIR}/tests/MBAdder/dut.sv, line:1:1, endln:7:10 |vpiName:a |vpiFullName:work@MultibitAdder.a |vpiNet: \_logic_net: (work@MultibitAdder.b), line:1:24, endln:1:25 |vpiParent: - \_module: work@MultibitAdder (work@MultibitAdder), file:${SURELOG_DIR}/tests/MBAdder/dut.sv, line:1:1, endln:7:10 + \_module_inst: work@MultibitAdder (work@MultibitAdder), file:${SURELOG_DIR}/tests/MBAdder/dut.sv, line:1:1, endln:7:10 |vpiName:b |vpiFullName:work@MultibitAdder.b |vpiNet: \_logic_net: (work@MultibitAdder.cin), line:1:26, endln:1:29 |vpiParent: - \_module: work@MultibitAdder (work@MultibitAdder), file:${SURELOG_DIR}/tests/MBAdder/dut.sv, line:1:1, endln:7:10 + \_module_inst: work@MultibitAdder (work@MultibitAdder), file:${SURELOG_DIR}/tests/MBAdder/dut.sv, line:1:1, endln:7:10 |vpiName:cin |vpiFullName:work@MultibitAdder.cin |vpiNet: \_logic_net: (work@MultibitAdder.sum), line:1:30, endln:1:33 |vpiParent: - \_module: work@MultibitAdder (work@MultibitAdder), file:${SURELOG_DIR}/tests/MBAdder/dut.sv, line:1:1, endln:7:10 + \_module_inst: work@MultibitAdder (work@MultibitAdder), file:${SURELOG_DIR}/tests/MBAdder/dut.sv, line:1:1, endln:7:10 |vpiName:sum |vpiFullName:work@MultibitAdder.sum |vpiNet: \_logic_net: (work@MultibitAdder.cout), line:1:34, endln:1:38 |vpiParent: - \_module: work@MultibitAdder (work@MultibitAdder), file:${SURELOG_DIR}/tests/MBAdder/dut.sv, line:1:1, endln:7:10 + \_module_inst: work@MultibitAdder (work@MultibitAdder), file:${SURELOG_DIR}/tests/MBAdder/dut.sv, line:1:1, endln:7:10 |vpiName:cout |vpiFullName:work@MultibitAdder.cout |vpiPort: \_port: (a), line:1:22, endln:1:23 |vpiParent: - \_module: work@MultibitAdder (work@MultibitAdder), file:${SURELOG_DIR}/tests/MBAdder/dut.sv, line:1:1, endln:7:10 + \_module_inst: work@MultibitAdder (work@MultibitAdder), file:${SURELOG_DIR}/tests/MBAdder/dut.sv, line:1:1, endln:7:10 |vpiName:a |vpiDirection:1 |vpiLowConn: @@ -639,7 +639,7 @@ design: (work@MultibitAdder) |vpiPort: \_port: (b), line:1:24, endln:1:25 |vpiParent: - \_module: work@MultibitAdder (work@MultibitAdder), file:${SURELOG_DIR}/tests/MBAdder/dut.sv, line:1:1, endln:7:10 + \_module_inst: work@MultibitAdder (work@MultibitAdder), file:${SURELOG_DIR}/tests/MBAdder/dut.sv, line:1:1, endln:7:10 |vpiName:b |vpiDirection:1 |vpiLowConn: @@ -669,7 +669,7 @@ design: (work@MultibitAdder) |vpiPort: \_port: (cin), line:1:26, endln:1:29 |vpiParent: - \_module: work@MultibitAdder (work@MultibitAdder), file:${SURELOG_DIR}/tests/MBAdder/dut.sv, line:1:1, endln:7:10 + \_module_inst: work@MultibitAdder (work@MultibitAdder), file:${SURELOG_DIR}/tests/MBAdder/dut.sv, line:1:1, endln:7:10 |vpiName:cin |vpiDirection:1 |vpiLowConn: @@ -681,7 +681,7 @@ design: (work@MultibitAdder) |vpiPort: \_port: (sum), line:1:30, endln:1:33 |vpiParent: - \_module: work@MultibitAdder (work@MultibitAdder), file:${SURELOG_DIR}/tests/MBAdder/dut.sv, line:1:1, endln:7:10 + \_module_inst: work@MultibitAdder (work@MultibitAdder), file:${SURELOG_DIR}/tests/MBAdder/dut.sv, line:1:1, endln:7:10 |vpiName:sum |vpiDirection:2 |vpiLowConn: @@ -711,7 +711,7 @@ design: (work@MultibitAdder) |vpiPort: \_port: (cout), line:1:34, endln:1:38 |vpiParent: - \_module: work@MultibitAdder (work@MultibitAdder), file:${SURELOG_DIR}/tests/MBAdder/dut.sv, line:1:1, endln:7:10 + \_module_inst: work@MultibitAdder (work@MultibitAdder), file:${SURELOG_DIR}/tests/MBAdder/dut.sv, line:1:1, endln:7:10 |vpiName:cout |vpiDirection:2 |vpiLowConn: @@ -723,7 +723,7 @@ design: (work@MultibitAdder) |vpiContAssign: \_cont_assign: , line:6:9, endln:6:27 |vpiParent: - \_module: work@MultibitAdder (work@MultibitAdder), file:${SURELOG_DIR}/tests/MBAdder/dut.sv, line:1:1, endln:7:10 + \_module_inst: work@MultibitAdder (work@MultibitAdder), file:${SURELOG_DIR}/tests/MBAdder/dut.sv, line:1:1, endln:7:10 |vpiRhs: \_operation: , line:6:20, endln:6:27 |vpiParent: @@ -780,14 +780,14 @@ design: (work@MultibitAdder) |vpiActual: \_logic_net: (work@MultibitAdder.sum), line:1:30, endln:1:33 |uhdmtopModules: -\_module: work@MultibitAdder (work@MultibitAdder), file:${SURELOG_DIR}/tests/MBAdder/dut.sv, line:1:1, endln:7:10 +\_module_inst: work@MultibitAdder (work@MultibitAdder), file:${SURELOG_DIR}/tests/MBAdder/dut.sv, line:1:1, endln:7:10 |vpiName:work@MultibitAdder |vpiDefName:work@MultibitAdder |vpiTop:1 |vpiNet: \_logic_net: (work@MultibitAdder.a), line:1:22, endln:1:23 |vpiParent: - \_module: work@MultibitAdder (work@MultibitAdder), file:${SURELOG_DIR}/tests/MBAdder/dut.sv, line:1:1, endln:7:10 + \_module_inst: work@MultibitAdder (work@MultibitAdder), file:${SURELOG_DIR}/tests/MBAdder/dut.sv, line:1:1, endln:7:10 |vpiTypespec: \_logic_typespec: , line:2:8, endln:2:13 |vpiRange: @@ -813,7 +813,7 @@ design: (work@MultibitAdder) |vpiNet: \_logic_net: (work@MultibitAdder.b), line:1:24, endln:1:25 |vpiParent: - \_module: work@MultibitAdder (work@MultibitAdder), file:${SURELOG_DIR}/tests/MBAdder/dut.sv, line:1:1, endln:7:10 + \_module_inst: work@MultibitAdder (work@MultibitAdder), file:${SURELOG_DIR}/tests/MBAdder/dut.sv, line:1:1, endln:7:10 |vpiTypespec: \_logic_typespec: , line:2:8, endln:2:13 |vpiName:b @@ -821,7 +821,7 @@ design: (work@MultibitAdder) |vpiNet: \_logic_net: (work@MultibitAdder.cin), line:1:26, endln:1:29 |vpiParent: - \_module: work@MultibitAdder (work@MultibitAdder), file:${SURELOG_DIR}/tests/MBAdder/dut.sv, line:1:1, endln:7:10 + \_module_inst: work@MultibitAdder (work@MultibitAdder), file:${SURELOG_DIR}/tests/MBAdder/dut.sv, line:1:1, endln:7:10 |vpiTypespec: \_logic_typespec: , line:3:8, endln:3:8 |vpiName:cin @@ -829,7 +829,7 @@ design: (work@MultibitAdder) |vpiNet: \_logic_net: (work@MultibitAdder.sum), line:1:30, endln:1:33 |vpiParent: - \_module: work@MultibitAdder (work@MultibitAdder), file:${SURELOG_DIR}/tests/MBAdder/dut.sv, line:1:1, endln:7:10 + \_module_inst: work@MultibitAdder (work@MultibitAdder), file:${SURELOG_DIR}/tests/MBAdder/dut.sv, line:1:1, endln:7:10 |vpiTypespec: \_logic_typespec: , line:4:9, endln:4:14 |vpiRange: @@ -855,7 +855,7 @@ design: (work@MultibitAdder) |vpiNet: \_logic_net: (work@MultibitAdder.cout), line:1:34, endln:1:38 |vpiParent: - \_module: work@MultibitAdder (work@MultibitAdder), file:${SURELOG_DIR}/tests/MBAdder/dut.sv, line:1:1, endln:7:10 + \_module_inst: work@MultibitAdder (work@MultibitAdder), file:${SURELOG_DIR}/tests/MBAdder/dut.sv, line:1:1, endln:7:10 |vpiTypespec: \_logic_typespec: , line:5:9, endln:5:9 |vpiName:cout @@ -864,7 +864,7 @@ design: (work@MultibitAdder) |vpiPort: \_port: (a), line:1:22, endln:1:23 |vpiParent: - \_module: work@MultibitAdder (work@MultibitAdder), file:${SURELOG_DIR}/tests/MBAdder/dut.sv, line:1:1, endln:7:10 + \_module_inst: work@MultibitAdder (work@MultibitAdder), file:${SURELOG_DIR}/tests/MBAdder/dut.sv, line:1:1, endln:7:10 |vpiName:a |vpiDirection:1 |vpiLowConn: @@ -898,11 +898,11 @@ design: (work@MultibitAdder) |UINT:0 |vpiConstType:9 |vpiInstance: - \_module: work@MultibitAdder (work@MultibitAdder), file:${SURELOG_DIR}/tests/MBAdder/dut.sv, line:1:1, endln:7:10 + \_module_inst: work@MultibitAdder (work@MultibitAdder), file:${SURELOG_DIR}/tests/MBAdder/dut.sv, line:1:1, endln:7:10 |vpiPort: \_port: (b), line:1:24, endln:1:25 |vpiParent: - \_module: work@MultibitAdder (work@MultibitAdder), file:${SURELOG_DIR}/tests/MBAdder/dut.sv, line:1:1, endln:7:10 + \_module_inst: work@MultibitAdder (work@MultibitAdder), file:${SURELOG_DIR}/tests/MBAdder/dut.sv, line:1:1, endln:7:10 |vpiName:b |vpiDirection:1 |vpiLowConn: @@ -916,11 +916,11 @@ design: (work@MultibitAdder) |vpiTypedef: \_logic_typespec: , line:2:8, endln:2:13 |vpiInstance: - \_module: work@MultibitAdder (work@MultibitAdder), file:${SURELOG_DIR}/tests/MBAdder/dut.sv, line:1:1, endln:7:10 + \_module_inst: work@MultibitAdder (work@MultibitAdder), file:${SURELOG_DIR}/tests/MBAdder/dut.sv, line:1:1, endln:7:10 |vpiPort: \_port: (cin), line:1:26, endln:1:29 |vpiParent: - \_module: work@MultibitAdder (work@MultibitAdder), file:${SURELOG_DIR}/tests/MBAdder/dut.sv, line:1:1, endln:7:10 + \_module_inst: work@MultibitAdder (work@MultibitAdder), file:${SURELOG_DIR}/tests/MBAdder/dut.sv, line:1:1, endln:7:10 |vpiName:cin |vpiDirection:1 |vpiLowConn: @@ -934,11 +934,11 @@ design: (work@MultibitAdder) |vpiTypedef: \_logic_typespec: , line:3:8, endln:3:8 |vpiInstance: - \_module: work@MultibitAdder (work@MultibitAdder), file:${SURELOG_DIR}/tests/MBAdder/dut.sv, line:1:1, endln:7:10 + \_module_inst: work@MultibitAdder (work@MultibitAdder), file:${SURELOG_DIR}/tests/MBAdder/dut.sv, line:1:1, endln:7:10 |vpiPort: \_port: (sum), line:1:30, endln:1:33 |vpiParent: - \_module: work@MultibitAdder (work@MultibitAdder), file:${SURELOG_DIR}/tests/MBAdder/dut.sv, line:1:1, endln:7:10 + \_module_inst: work@MultibitAdder (work@MultibitAdder), file:${SURELOG_DIR}/tests/MBAdder/dut.sv, line:1:1, endln:7:10 |vpiName:sum |vpiDirection:2 |vpiLowConn: @@ -972,11 +972,11 @@ design: (work@MultibitAdder) |UINT:0 |vpiConstType:9 |vpiInstance: - \_module: work@MultibitAdder (work@MultibitAdder), file:${SURELOG_DIR}/tests/MBAdder/dut.sv, line:1:1, endln:7:10 + \_module_inst: work@MultibitAdder (work@MultibitAdder), file:${SURELOG_DIR}/tests/MBAdder/dut.sv, line:1:1, endln:7:10 |vpiPort: \_port: (cout), line:1:34, endln:1:38 |vpiParent: - \_module: work@MultibitAdder (work@MultibitAdder), file:${SURELOG_DIR}/tests/MBAdder/dut.sv, line:1:1, endln:7:10 + \_module_inst: work@MultibitAdder (work@MultibitAdder), file:${SURELOG_DIR}/tests/MBAdder/dut.sv, line:1:1, endln:7:10 |vpiName:cout |vpiDirection:2 |vpiLowConn: @@ -990,11 +990,11 @@ design: (work@MultibitAdder) |vpiTypedef: \_logic_typespec: , line:5:9, endln:5:9 |vpiInstance: - \_module: work@MultibitAdder (work@MultibitAdder), file:${SURELOG_DIR}/tests/MBAdder/dut.sv, line:1:1, endln:7:10 + \_module_inst: work@MultibitAdder (work@MultibitAdder), file:${SURELOG_DIR}/tests/MBAdder/dut.sv, line:1:1, endln:7:10 |vpiContAssign: \_cont_assign: , line:6:9, endln:6:27 |vpiParent: - \_module: work@MultibitAdder (work@MultibitAdder), file:${SURELOG_DIR}/tests/MBAdder/dut.sv, line:1:1, endln:7:10 + \_module_inst: work@MultibitAdder (work@MultibitAdder), file:${SURELOG_DIR}/tests/MBAdder/dut.sv, line:1:1, endln:7:10 |vpiRhs: \_operation: , line:6:20, endln:6:27 |vpiParent: diff --git a/tests/MacroArgMismatch/MacroArgMismatch.log b/tests/MacroArgMismatch/MacroArgMismatch.log index fd66a2a458..79f4607168 100644 --- a/tests/MacroArgMismatch/MacroArgMismatch.log +++ b/tests/MacroArgMismatch/MacroArgMismatch.log @@ -93,7 +93,7 @@ design 1 event_control 1 logic_net 4 logic_typespec 4 -module 2 +module_inst 2 operation 2 port 2 ref_obj 5 @@ -108,7 +108,7 @@ design 1 event_control 2 logic_net 4 logic_typespec 4 -module 2 +module_inst 2 operation 4 port 3 ref_obj 9 @@ -126,7 +126,7 @@ design: (work@test) |vpiElaborated:1 |vpiName:work@test |uhdmallModules: -\_module: work@test (work@test), file:${SURELOG_DIR}/tests/MacroArgMismatch/dut.sv, line:2:1, endln:6:10 +\_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/MacroArgMismatch/dut.sv, line:2:1, endln:6:10 |vpiParent: \_design: (work@test) |vpiFullName:work@test @@ -134,20 +134,20 @@ design: (work@test) |vpiNet: \_logic_net: (work@test.clk), line:2:19, endln:2:22 |vpiParent: - \_module: work@test (work@test), file:${SURELOG_DIR}/tests/MacroArgMismatch/dut.sv, line:2:1, endln:6:10 + \_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/MacroArgMismatch/dut.sv, line:2:1, endln:6:10 |vpiName:clk |vpiFullName:work@test.clk |vpiNet: \_logic_net: (work@test.d), line:3:5, endln:3:6 |vpiParent: - \_module: work@test (work@test), file:${SURELOG_DIR}/tests/MacroArgMismatch/dut.sv, line:2:1, endln:6:10 + \_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/MacroArgMismatch/dut.sv, line:2:1, endln:6:10 |vpiName:d |vpiFullName:work@test.d |vpiNetType:48 |vpiPort: \_port: (clk), line:2:19, endln:2:22 |vpiParent: - \_module: work@test (work@test), file:${SURELOG_DIR}/tests/MacroArgMismatch/dut.sv, line:2:1, endln:6:10 + \_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/MacroArgMismatch/dut.sv, line:2:1, endln:6:10 |vpiName:clk |vpiDirection:1 |vpiLowConn: @@ -159,7 +159,7 @@ design: (work@test) |vpiProcess: \_always: , line:4:1, endln:5:17 |vpiParent: - \_module: work@test (work@test), file:${SURELOG_DIR}/tests/MacroArgMismatch/dut.sv, line:2:1, endln:6:10 + \_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/MacroArgMismatch/dut.sv, line:2:1, endln:6:10 |vpiStmt: \_event_control: , line:4:8, endln:4:22 |vpiParent: @@ -210,14 +210,14 @@ design: (work@test) |#1 |vpiAlwaysType:1 |uhdmtopModules: -\_module: work@test (work@test), file:${SURELOG_DIR}/tests/MacroArgMismatch/dut.sv, line:2:1, endln:6:10 +\_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/MacroArgMismatch/dut.sv, line:2:1, endln:6:10 |vpiName:work@test |vpiDefName:work@test |vpiTop:1 |vpiNet: \_logic_net: (work@test.clk), line:2:19, endln:2:22 |vpiParent: - \_module: work@test (work@test), file:${SURELOG_DIR}/tests/MacroArgMismatch/dut.sv, line:2:1, endln:6:10 + \_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/MacroArgMismatch/dut.sv, line:2:1, endln:6:10 |vpiTypespec: \_logic_typespec: , line:2:19, endln:2:19 |vpiName:clk @@ -225,7 +225,7 @@ design: (work@test) |vpiNet: \_logic_net: (work@test.d), line:3:5, endln:3:6 |vpiParent: - \_module: work@test (work@test), file:${SURELOG_DIR}/tests/MacroArgMismatch/dut.sv, line:2:1, endln:6:10 + \_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/MacroArgMismatch/dut.sv, line:2:1, endln:6:10 |vpiTypespec: \_logic_typespec: , line:3:1, endln:3:4 |vpiName:d @@ -235,7 +235,7 @@ design: (work@test) |vpiPort: \_port: (clk), line:2:19, endln:2:22 |vpiParent: - \_module: work@test (work@test), file:${SURELOG_DIR}/tests/MacroArgMismatch/dut.sv, line:2:1, endln:6:10 + \_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/MacroArgMismatch/dut.sv, line:2:1, endln:6:10 |vpiName:clk |vpiDirection:1 |vpiLowConn: @@ -249,11 +249,11 @@ design: (work@test) |vpiTypedef: \_logic_typespec: , line:2:19, endln:2:19 |vpiInstance: - \_module: work@test (work@test), file:${SURELOG_DIR}/tests/MacroArgMismatch/dut.sv, line:2:1, endln:6:10 + \_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/MacroArgMismatch/dut.sv, line:2:1, endln:6:10 |vpiProcess: \_always: , line:4:1, endln:5:17 |vpiParent: - \_module: work@test (work@test), file:${SURELOG_DIR}/tests/MacroArgMismatch/dut.sv, line:2:1, endln:6:10 + \_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/MacroArgMismatch/dut.sv, line:2:1, endln:6:10 |vpiStmt: \_event_control: , line:4:8, endln:4:22 |vpiParent: diff --git a/tests/MaskNeg/MaskNeg.log b/tests/MaskNeg/MaskNeg.log index 6e248d9af2..cbfa2fa071 100644 --- a/tests/MaskNeg/MaskNeg.log +++ b/tests/MaskNeg/MaskNeg.log @@ -88,7 +88,7 @@ n<> u<57> t c<1> l<1:1> el<10:1> constant 7 design 1 logic_typespec 2 -module 6 +module_inst 6 operation 1 param_assign 2 parameter 2 @@ -100,7 +100,7 @@ range 2 constant 7 design 1 logic_typespec 2 -module 6 +module_inst 6 operation 1 param_assign 2 parameter 2 @@ -119,14 +119,14 @@ design: (work@top) |vpiElaborated:1 |vpiName:work@top |uhdmallModules: -\_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/MaskNeg/dut.sv, line:1:1, endln:3:10 +\_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/MaskNeg/dut.sv, line:1:1, endln:3:10 |vpiParent: \_design: (work@top) |vpiFullName:work@dut |vpiParameter: \_parameter: (work@dut.RESVAL), line:2:26, endln:2:32 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/MaskNeg/dut.sv, line:1:1, endln:3:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/MaskNeg/dut.sv, line:1:1, endln:3:10 |vpiTypespec: \_logic_typespec: , line:2:14, endln:2:25 |vpiParent: @@ -154,32 +154,32 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:2:26, endln:2:32 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/MaskNeg/dut.sv, line:1:1, endln:3:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/MaskNeg/dut.sv, line:1:1, endln:3:10 |vpiLhs: \_parameter: (work@dut.RESVAL), line:2:26, endln:2:32 |vpiDefName:work@dut |uhdmallModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/MaskNeg/dut.sv, line:5:1, endln:9:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/MaskNeg/dut.sv, line:5:1, endln:9:10 |vpiParent: \_design: (work@top) |vpiFullName:work@top |vpiDefName:work@top |uhdmtopModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/MaskNeg/dut.sv, line:5:1, endln:9:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/MaskNeg/dut.sv, line:5:1, endln:9:10 |vpiName:work@top |vpiDefName:work@top |vpiTop:1 |vpiTopModule:1 - |vpiModule: - \_module: work@dut (work@top.u_dut), file:${SURELOG_DIR}/tests/MaskNeg/dut.sv, line:6:4, endln:8:14 + |vpiModuleInst: + \_module_inst: work@dut (work@top.u_dut), file:${SURELOG_DIR}/tests/MaskNeg/dut.sv, line:6:4, endln:8:14 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/MaskNeg/dut.sv, line:5:1, endln:9:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/MaskNeg/dut.sv, line:5:1, endln:9:10 |vpiName:u_dut |vpiFullName:work@top.u_dut |vpiParameter: \_parameter: (work@top.u_dut.RESVAL), line:2:26, endln:2:32 |vpiParent: - \_module: work@dut (work@top.u_dut), file:${SURELOG_DIR}/tests/MaskNeg/dut.sv, line:6:4, endln:8:14 + \_module_inst: work@dut (work@top.u_dut), file:${SURELOG_DIR}/tests/MaskNeg/dut.sv, line:6:4, endln:8:14 |vpiTypespec: \_logic_typespec: , line:2:14, endln:2:25 |vpiParent: @@ -209,7 +209,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:2:26, endln:2:32 |vpiParent: - \_module: work@dut (work@top.u_dut), file:${SURELOG_DIR}/tests/MaskNeg/dut.sv, line:6:4, endln:8:14 + \_module_inst: work@dut (work@top.u_dut), file:${SURELOG_DIR}/tests/MaskNeg/dut.sv, line:6:4, endln:8:14 |vpiOverriden:1 |vpiRhs: \_constant: @@ -225,7 +225,7 @@ design: (work@top) |vpiDefFile:${SURELOG_DIR}/tests/MaskNeg/dut.sv |vpiDefLineNo:1 |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/MaskNeg/dut.sv, line:5:1, endln:9:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/MaskNeg/dut.sv, line:5:1, endln:9:10 =================== [ FATAL] : 0 [ SYNTAX] : 0 diff --git a/tests/MinTypMax/MinTypMax.log b/tests/MinTypMax/MinTypMax.log index 3630c7c64b..9878843e6d 100644 --- a/tests/MinTypMax/MinTypMax.log +++ b/tests/MinTypMax/MinTypMax.log @@ -77,7 +77,7 @@ n<> u<50> t c<1> l<1:1> el<5:1> constant 6 design 1 initial 1 -module 4 +module_inst 4 operation 2 param_assign 2 parameter 2 @@ -90,7 +90,7 @@ sys_func_call 1 constant 6 design 1 initial 2 -module 4 +module_inst 4 operation 2 param_assign 2 parameter 2 @@ -110,20 +110,20 @@ design: (work@top) |vpiElaborated:1 |vpiName:work@top |uhdmallModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/MinTypMax/dut.sv, line:1:1, endln:4:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/MinTypMax/dut.sv, line:1:1, endln:4:10 |vpiParent: \_design: (work@top) |vpiFullName:work@top |vpiParameter: \_parameter: (work@top.value), line:2:13, endln:2:18 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/MinTypMax/dut.sv, line:1:1, endln:4:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/MinTypMax/dut.sv, line:1:1, endln:4:10 |vpiName:value |vpiFullName:work@top.value |vpiParamAssign: \_param_assign: , line:2:13, endln:2:28 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/MinTypMax/dut.sv, line:1:1, endln:4:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/MinTypMax/dut.sv, line:1:1, endln:4:10 |vpiRhs: \_operation: , line:2:21, endln:2:28 |vpiOpType:38 @@ -151,7 +151,7 @@ design: (work@top) |vpiProcess: \_initial: , line:3:3, endln:3:27 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/MinTypMax/dut.sv, line:1:1, endln:4:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/MinTypMax/dut.sv, line:1:1, endln:4:10 |vpiStmt: \_sys_func_call: ($display), line:3:11, endln:3:26 |vpiParent: @@ -164,18 +164,18 @@ design: (work@top) |vpiFullName:work@top.value |vpiName:$display |uhdmtopModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/MinTypMax/dut.sv, line:1:1, endln:4:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/MinTypMax/dut.sv, line:1:1, endln:4:10 |vpiName:work@top |vpiParameter: \_parameter: (work@top.value), line:2:13, endln:2:18 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/MinTypMax/dut.sv, line:1:1, endln:4:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/MinTypMax/dut.sv, line:1:1, endln:4:10 |vpiName:value |vpiFullName:work@top.value |vpiParamAssign: \_param_assign: , line:2:13, endln:2:28 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/MinTypMax/dut.sv, line:1:1, endln:4:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/MinTypMax/dut.sv, line:1:1, endln:4:10 |vpiRhs: \_operation: , line:2:21, endln:2:28 |vpiOpType:38 @@ -205,7 +205,7 @@ design: (work@top) |vpiProcess: \_initial: , line:3:3, endln:3:27 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/MinTypMax/dut.sv, line:1:1, endln:4:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/MinTypMax/dut.sv, line:1:1, endln:4:10 |vpiStmt: \_sys_func_call: ($display), line:3:11, endln:3:26 |vpiParent: diff --git a/tests/ModPortArrayBind/ModPortArrayBind.log b/tests/ModPortArrayBind/ModPortArrayBind.log index 21a75c5e54..15de123858 100644 --- a/tests/ModPortArrayBind/ModPortArrayBind.log +++ b/tests/ModPortArrayBind/ModPortArrayBind.log @@ -196,15 +196,15 @@ gen_scope 4 gen_scope_array 4 hier_path 4 int_typespec 4 -interface 3 interface_array 2 +interface_inst 3 interface_typespec 7 io_decl 3 logic_net 2 logic_typespec 2 logic_var 2 modport 3 -module 6 +module_inst 6 operation 10 param_assign 2 parameter 4 @@ -224,15 +224,15 @@ gen_scope 6 gen_scope_array 6 hier_path 6 int_typespec 4 -interface 3 interface_array 2 +interface_inst 3 interface_typespec 7 io_decl 3 logic_net 2 logic_typespec 2 logic_var 2 modport 3 -module 6 +module_inst 6 operation 12 param_assign 2 parameter 4 @@ -253,7 +253,7 @@ design: (work@r5p_bus_dec) |vpiElaborated:1 |vpiName:work@r5p_bus_dec |uhdmallInterfaces: -\_interface: work@r5p_bus_if (work@r5p_bus_if), file:${SURELOG_DIR}/tests/ModPortArrayBind/dut.sv, line:2:1, endln:10:25 +\_interface_inst: work@r5p_bus_if (work@r5p_bus_if), file:${SURELOG_DIR}/tests/ModPortArrayBind/dut.sv, line:2:1, endln:10:25 |vpiParent: \_design: (work@r5p_bus_dec) |vpiFullName:work@r5p_bus_if @@ -261,28 +261,28 @@ design: (work@r5p_bus_dec) |vpiNet: \_logic_net: (work@r5p_bus_if.vld), line:4:17, endln:4:20 |vpiParent: - \_interface: work@r5p_bus_if (work@r5p_bus_if), file:${SURELOG_DIR}/tests/ModPortArrayBind/dut.sv, line:2:1, endln:10:25 + \_interface_inst: work@r5p_bus_if (work@r5p_bus_if), file:${SURELOG_DIR}/tests/ModPortArrayBind/dut.sv, line:2:1, endln:10:25 |vpiName:vld |vpiFullName:work@r5p_bus_if.vld |vpiNetType:36 |vpiModport: \_modport: (man), line:6:11, endln:6:14 |vpiParent: - \_interface: work@r5p_bus_if (work@r5p_bus_if), file:${SURELOG_DIR}/tests/ModPortArrayBind/dut.sv, line:2:1, endln:10:25 + \_interface_inst: work@r5p_bus_if (work@r5p_bus_if), file:${SURELOG_DIR}/tests/ModPortArrayBind/dut.sv, line:2:1, endln:10:25 |vpiName:man |vpiIODecl: \_io_decl: (vld), line:7:11, endln:7:14 |vpiDirection:2 |vpiName:vld |uhdmallModules: -\_module: work@r5p_bus_dec (work@r5p_bus_dec), file:${SURELOG_DIR}/tests/ModPortArrayBind/dut.sv, line:12:1, endln:29:10 +\_module_inst: work@r5p_bus_dec (work@r5p_bus_dec), file:${SURELOG_DIR}/tests/ModPortArrayBind/dut.sv, line:12:1, endln:29:10 |vpiParent: \_design: (work@r5p_bus_dec) |vpiFullName:work@r5p_bus_dec |vpiParameter: \_parameter: (work@r5p_bus_dec.BN), line:13:16, endln:13:18 |vpiParent: - \_module: work@r5p_bus_dec (work@r5p_bus_dec), file:${SURELOG_DIR}/tests/ModPortArrayBind/dut.sv, line:12:1, endln:29:10 + \_module_inst: work@r5p_bus_dec (work@r5p_bus_dec), file:${SURELOG_DIR}/tests/ModPortArrayBind/dut.sv, line:12:1, endln:29:10 |UINT:2 |vpiTypespec: \_int_typespec: , line:13:3, endln:13:15 @@ -293,7 +293,7 @@ design: (work@r5p_bus_dec) |vpiParamAssign: \_param_assign: , line:13:16, endln:13:22 |vpiParent: - \_module: work@r5p_bus_dec (work@r5p_bus_dec), file:${SURELOG_DIR}/tests/ModPortArrayBind/dut.sv, line:12:1, endln:29:10 + \_module_inst: work@r5p_bus_dec (work@r5p_bus_dec), file:${SURELOG_DIR}/tests/ModPortArrayBind/dut.sv, line:12:1, endln:29:10 |vpiRhs: \_constant: , line:13:21, endln:13:22 |vpiDecompile:2 @@ -308,13 +308,13 @@ design: (work@r5p_bus_dec) |vpiNet: \_logic_net: (work@r5p_bus_dec.m), line:15:18, endln:15:19 |vpiParent: - \_module: work@r5p_bus_dec (work@r5p_bus_dec), file:${SURELOG_DIR}/tests/ModPortArrayBind/dut.sv, line:12:1, endln:29:10 + \_module_inst: work@r5p_bus_dec (work@r5p_bus_dec), file:${SURELOG_DIR}/tests/ModPortArrayBind/dut.sv, line:12:1, endln:29:10 |vpiName:m |vpiFullName:work@r5p_bus_dec.m |vpiPort: \_port: (m), line:15:18, endln:15:19 |vpiParent: - \_module: work@r5p_bus_dec (work@r5p_bus_dec), file:${SURELOG_DIR}/tests/ModPortArrayBind/dut.sv, line:12:1, endln:29:10 + \_module_inst: work@r5p_bus_dec (work@r5p_bus_dec), file:${SURELOG_DIR}/tests/ModPortArrayBind/dut.sv, line:12:1, endln:29:10 |vpiName:m |vpiDirection:3 |vpiLowConn: @@ -363,7 +363,7 @@ design: (work@r5p_bus_dec) |vpiInterfaceArray: \_interface_array: (r5p_bus_if.man), line:15:18, endln:15:19 |vpiParent: - \_module: work@r5p_bus_dec (work@r5p_bus_dec), file:${SURELOG_DIR}/tests/ModPortArrayBind/dut.sv, line:12:1, endln:29:10 + \_module_inst: work@r5p_bus_dec (work@r5p_bus_dec), file:${SURELOG_DIR}/tests/ModPortArrayBind/dut.sv, line:12:1, endln:29:10 |vpiName:m |vpiFullName:r5p_bus_if.man |vpiRange: @@ -398,12 +398,12 @@ design: (work@r5p_bus_dec) \_interface_typespec: (r5p_bus_if.man), line:15:3, endln:15:17 |vpiName:r5p_bus_if.man |uhdmtopModules: -\_module: work@r5p_bus_dec (work@r5p_bus_dec), file:${SURELOG_DIR}/tests/ModPortArrayBind/dut.sv, line:12:1, endln:29:10 +\_module_inst: work@r5p_bus_dec (work@r5p_bus_dec), file:${SURELOG_DIR}/tests/ModPortArrayBind/dut.sv, line:12:1, endln:29:10 |vpiName:work@r5p_bus_dec |vpiParameter: \_parameter: (work@r5p_bus_dec.BN), line:13:16, endln:13:18 |vpiParent: - \_module: work@r5p_bus_dec (work@r5p_bus_dec), file:${SURELOG_DIR}/tests/ModPortArrayBind/dut.sv, line:12:1, endln:29:10 + \_module_inst: work@r5p_bus_dec (work@r5p_bus_dec), file:${SURELOG_DIR}/tests/ModPortArrayBind/dut.sv, line:12:1, endln:29:10 |UINT:2 |vpiTypespec: \_int_typespec: , line:13:3, endln:13:15 @@ -414,7 +414,7 @@ design: (work@r5p_bus_dec) |vpiParamAssign: \_param_assign: , line:13:16, endln:13:22 |vpiParent: - \_module: work@r5p_bus_dec (work@r5p_bus_dec), file:${SURELOG_DIR}/tests/ModPortArrayBind/dut.sv, line:12:1, endln:29:10 + \_module_inst: work@r5p_bus_dec (work@r5p_bus_dec), file:${SURELOG_DIR}/tests/ModPortArrayBind/dut.sv, line:12:1, endln:29:10 |vpiRhs: \_constant: , line:13:21, endln:13:22 |vpiDecompile:2 @@ -431,7 +431,7 @@ design: (work@r5p_bus_dec) |vpiPort: \_port: (m), line:15:18, endln:15:19 |vpiParent: - \_module: work@r5p_bus_dec (work@r5p_bus_dec), file:${SURELOG_DIR}/tests/ModPortArrayBind/dut.sv, line:12:1, endln:29:10 + \_module_inst: work@r5p_bus_dec (work@r5p_bus_dec), file:${SURELOG_DIR}/tests/ModPortArrayBind/dut.sv, line:12:1, endln:29:10 |vpiName:m |vpiDirection:3 |vpiLowConn: @@ -448,18 +448,18 @@ design: (work@r5p_bus_dec) |vpiName:man |vpiIsModPort:1 |vpiInstance: - \_module: work@r5p_bus_dec (work@r5p_bus_dec), file:${SURELOG_DIR}/tests/ModPortArrayBind/dut.sv, line:12:1, endln:29:10 - |vpiInterface: - \_interface: work@r5p_bus_if (work@r5p_bus_dec.m[0]), file:${SURELOG_DIR}/tests/ModPortArrayBind/dut.sv, line:12:0 + \_module_inst: work@r5p_bus_dec (work@r5p_bus_dec), file:${SURELOG_DIR}/tests/ModPortArrayBind/dut.sv, line:12:1, endln:29:10 + |vpiInterfaceInst: + \_interface_inst: work@r5p_bus_if (work@r5p_bus_dec.m[0]), file:${SURELOG_DIR}/tests/ModPortArrayBind/dut.sv, line:12:0 |vpiParent: - \_module: work@r5p_bus_dec (work@r5p_bus_dec), file:${SURELOG_DIR}/tests/ModPortArrayBind/dut.sv, line:12:1, endln:29:10 + \_module_inst: work@r5p_bus_dec (work@r5p_bus_dec), file:${SURELOG_DIR}/tests/ModPortArrayBind/dut.sv, line:12:1, endln:29:10 |vpiName:m[0] |vpiFullName:work@r5p_bus_dec.m[0] |vpiDefName:work@r5p_bus_if |vpiModport: \_modport: (man), line:6:11, endln:6:14 |vpiParent: - \_interface: work@r5p_bus_if (work@r5p_bus_dec.m[0]), file:${SURELOG_DIR}/tests/ModPortArrayBind/dut.sv, line:12:0 + \_interface_inst: work@r5p_bus_if (work@r5p_bus_dec.m[0]), file:${SURELOG_DIR}/tests/ModPortArrayBind/dut.sv, line:12:0 |vpiName:man |vpiIODecl: \_io_decl: (vld), line:7:11, endln:7:14 @@ -471,19 +471,19 @@ design: (work@r5p_bus_dec) \_logic_typespec: , line:4:2, endln:4:7 |vpiName:vld |vpiVisibility:1 - |vpiInterface: - \_interface: work@r5p_bus_if (work@r5p_bus_dec.m[0]), file:${SURELOG_DIR}/tests/ModPortArrayBind/dut.sv, line:12:0 - |vpiInterface: - \_interface: work@r5p_bus_if (work@r5p_bus_dec.m[1]), file:${SURELOG_DIR}/tests/ModPortArrayBind/dut.sv, line:12:0 + |vpiInterfaceInst: + \_interface_inst: work@r5p_bus_if (work@r5p_bus_dec.m[0]), file:${SURELOG_DIR}/tests/ModPortArrayBind/dut.sv, line:12:0 + |vpiInterfaceInst: + \_interface_inst: work@r5p_bus_if (work@r5p_bus_dec.m[1]), file:${SURELOG_DIR}/tests/ModPortArrayBind/dut.sv, line:12:0 |vpiParent: - \_module: work@r5p_bus_dec (work@r5p_bus_dec), file:${SURELOG_DIR}/tests/ModPortArrayBind/dut.sv, line:12:1, endln:29:10 + \_module_inst: work@r5p_bus_dec (work@r5p_bus_dec), file:${SURELOG_DIR}/tests/ModPortArrayBind/dut.sv, line:12:1, endln:29:10 |vpiName:m[1] |vpiFullName:work@r5p_bus_dec.m[1] |vpiDefName:work@r5p_bus_if |vpiModport: \_modport: (man), line:6:11, endln:6:14 |vpiParent: - \_interface: work@r5p_bus_if (work@r5p_bus_dec.m[1]), file:${SURELOG_DIR}/tests/ModPortArrayBind/dut.sv, line:12:0 + \_interface_inst: work@r5p_bus_if (work@r5p_bus_dec.m[1]), file:${SURELOG_DIR}/tests/ModPortArrayBind/dut.sv, line:12:0 |vpiName:man |vpiIODecl: \_io_decl: (vld), line:7:11, endln:7:14 @@ -495,12 +495,12 @@ design: (work@r5p_bus_dec) \_logic_typespec: , line:4:2, endln:4:7 |vpiName:vld |vpiVisibility:1 - |vpiInterface: - \_interface: work@r5p_bus_if (work@r5p_bus_dec.m[1]), file:${SURELOG_DIR}/tests/ModPortArrayBind/dut.sv, line:12:0 + |vpiInterfaceInst: + \_interface_inst: work@r5p_bus_if (work@r5p_bus_dec.m[1]), file:${SURELOG_DIR}/tests/ModPortArrayBind/dut.sv, line:12:0 |vpiInterfaceArray: \_interface_array: (work@r5p_bus_dec.m), line:15:18, endln:15:19 |vpiParent: - \_module: work@r5p_bus_dec (work@r5p_bus_dec), file:${SURELOG_DIR}/tests/ModPortArrayBind/dut.sv, line:12:1, endln:29:10 + \_module_inst: work@r5p_bus_dec (work@r5p_bus_dec), file:${SURELOG_DIR}/tests/ModPortArrayBind/dut.sv, line:12:1, endln:29:10 |vpiName:m |vpiFullName:work@r5p_bus_dec.m |vpiSize:2 @@ -523,13 +523,13 @@ design: (work@r5p_bus_dec) |UINT:0 |vpiConstType:9 |vpiInstance: - \_interface: work@r5p_bus_if (work@r5p_bus_dec.m[0]), file:${SURELOG_DIR}/tests/ModPortArrayBind/dut.sv, line:12:0 + \_interface_inst: work@r5p_bus_if (work@r5p_bus_dec.m[0]), file:${SURELOG_DIR}/tests/ModPortArrayBind/dut.sv, line:12:0 |vpiInstance: - \_interface: work@r5p_bus_if (work@r5p_bus_dec.m[1]), file:${SURELOG_DIR}/tests/ModPortArrayBind/dut.sv, line:12:0 + \_interface_inst: work@r5p_bus_if (work@r5p_bus_dec.m[1]), file:${SURELOG_DIR}/tests/ModPortArrayBind/dut.sv, line:12:0 |vpiGenScopeArray: \_gen_scope_array: (work@r5p_bus_dec.gen_loop[0]), line:21:22, endln:25:14 |vpiParent: - \_module: work@r5p_bus_dec (work@r5p_bus_dec), file:${SURELOG_DIR}/tests/ModPortArrayBind/dut.sv, line:12:1, endln:29:10 + \_module_inst: work@r5p_bus_dec (work@r5p_bus_dec), file:${SURELOG_DIR}/tests/ModPortArrayBind/dut.sv, line:12:1, endln:29:10 |vpiName:gen_loop[0] |vpiFullName:work@r5p_bus_dec.gen_loop[0] |vpiGenScope: @@ -611,7 +611,7 @@ design: (work@r5p_bus_dec) |vpiActual: \_parameter: (work@r5p_bus_dec.gen_loop[0].i), line:21:0 |vpiActual: - \_interface: work@r5p_bus_if (work@r5p_bus_dec.m[0]), file:${SURELOG_DIR}/tests/ModPortArrayBind/dut.sv, line:12:0 + \_interface_inst: work@r5p_bus_if (work@r5p_bus_dec.m[0]), file:${SURELOG_DIR}/tests/ModPortArrayBind/dut.sv, line:12:0 |vpiActual: \_ref_obj: (vld) |vpiParent: @@ -622,7 +622,7 @@ design: (work@r5p_bus_dec) |vpiGenScopeArray: \_gen_scope_array: (work@r5p_bus_dec.gen_loop[1]), line:21:22, endln:25:14 |vpiParent: - \_module: work@r5p_bus_dec (work@r5p_bus_dec), file:${SURELOG_DIR}/tests/ModPortArrayBind/dut.sv, line:12:1, endln:29:10 + \_module_inst: work@r5p_bus_dec (work@r5p_bus_dec), file:${SURELOG_DIR}/tests/ModPortArrayBind/dut.sv, line:12:1, endln:29:10 |vpiName:gen_loop[1] |vpiFullName:work@r5p_bus_dec.gen_loop[1] |vpiGenScope: @@ -704,7 +704,7 @@ design: (work@r5p_bus_dec) |vpiActual: \_parameter: (work@r5p_bus_dec.gen_loop[1].i), line:21:0 |vpiActual: - \_interface: work@r5p_bus_if (work@r5p_bus_dec.m[1]), file:${SURELOG_DIR}/tests/ModPortArrayBind/dut.sv, line:12:0 + \_interface_inst: work@r5p_bus_if (work@r5p_bus_dec.m[1]), file:${SURELOG_DIR}/tests/ModPortArrayBind/dut.sv, line:12:0 |vpiActual: \_ref_obj: (vld) |vpiParent: diff --git a/tests/ModPortHighConn/ModPortHighConn.log b/tests/ModPortHighConn/ModPortHighConn.log index 6c484e34ed..1dd780200d 100644 --- a/tests/ModPortHighConn/ModPortHighConn.log +++ b/tests/ModPortHighConn/ModPortHighConn.log @@ -52,7 +52,7 @@ constant 16 design 1 logic_net 14 logic_typespec 11 -module 12 +module_inst 12 operation 2 port 10 range 3 @@ -70,7 +70,7 @@ ref_obj 20 design: (work@top) |vpiName:work@top |uhdmallModules: -\_module: work@moduleA (work@moduleA), file:${SURELOG_DIR}/tests/ModPortHighConn/dut.sv, line:2:1, endln:3:10 +\_module_inst: work@moduleA (work@moduleA), file:${SURELOG_DIR}/tests/ModPortHighConn/dut.sv, line:2:1, endln:3:10 |vpiParent: \_design: (work@top) |vpiFullName:work@moduleA @@ -78,19 +78,19 @@ design: (work@top) |vpiNet: \_logic_net: (work@moduleA.port0), line:2:23, endln:2:28 |vpiParent: - \_module: work@moduleA (work@moduleA), file:${SURELOG_DIR}/tests/ModPortHighConn/dut.sv, line:2:1, endln:3:10 + \_module_inst: work@moduleA (work@moduleA), file:${SURELOG_DIR}/tests/ModPortHighConn/dut.sv, line:2:1, endln:3:10 |vpiName:port0 |vpiFullName:work@moduleA.port0 |vpiNet: \_logic_net: (work@moduleA.port1), line:2:30, endln:2:35 |vpiParent: - \_module: work@moduleA (work@moduleA), file:${SURELOG_DIR}/tests/ModPortHighConn/dut.sv, line:2:1, endln:3:10 + \_module_inst: work@moduleA (work@moduleA), file:${SURELOG_DIR}/tests/ModPortHighConn/dut.sv, line:2:1, endln:3:10 |vpiName:port1 |vpiFullName:work@moduleA.port1 |vpiPort: \_port: (port0), line:2:23, endln:2:28 |vpiParent: - \_module: work@moduleA (work@moduleA), file:${SURELOG_DIR}/tests/ModPortHighConn/dut.sv, line:2:1, endln:3:10 + \_module_inst: work@moduleA (work@moduleA), file:${SURELOG_DIR}/tests/ModPortHighConn/dut.sv, line:2:1, endln:3:10 |vpiName:port0 |vpiDirection:3 |vpiLowConn: @@ -102,7 +102,7 @@ design: (work@top) |vpiPort: \_port: (port1), line:2:30, endln:2:35 |vpiParent: - \_module: work@moduleA (work@moduleA), file:${SURELOG_DIR}/tests/ModPortHighConn/dut.sv, line:2:1, endln:3:10 + \_module_inst: work@moduleA (work@moduleA), file:${SURELOG_DIR}/tests/ModPortHighConn/dut.sv, line:2:1, endln:3:10 |vpiName:port1 |vpiDirection:3 |vpiLowConn: @@ -112,7 +112,7 @@ design: (work@top) |vpiTypedef: \_logic_typespec: , line:2:23, endln:2:23 |uhdmallModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/ModPortHighConn/dut.sv, line:5:1, endln:11:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ModPortHighConn/dut.sv, line:5:1, endln:11:10 |vpiParent: \_design: (work@top) |vpiFullName:work@top @@ -120,26 +120,26 @@ design: (work@top) |vpiNet: \_logic_net: (work@top.topA), line:6:16, endln:6:20 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ModPortHighConn/dut.sv, line:5:1, endln:11:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ModPortHighConn/dut.sv, line:5:1, endln:11:10 |vpiName:topA |vpiFullName:work@top.topA |vpiNetType:1 |vpiNet: \_logic_net: (work@top.topB), line:6:22, endln:6:26 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ModPortHighConn/dut.sv, line:5:1, endln:11:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ModPortHighConn/dut.sv, line:5:1, endln:11:10 |vpiName:topB |vpiFullName:work@top.topB |vpiNetType:1 |uhdmtopModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/ModPortHighConn/dut.sv, line:5:1, endln:11:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ModPortHighConn/dut.sv, line:5:1, endln:11:10 |vpiName:work@top |vpiDefName:work@top |vpiTop:1 |vpiNet: \_logic_net: (work@top.topA), line:6:16, endln:6:20 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ModPortHighConn/dut.sv, line:5:1, endln:11:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ModPortHighConn/dut.sv, line:5:1, endln:11:10 |vpiTypespec: \_logic_typespec: , line:6:5, endln:6:15 |vpiRange: @@ -166,17 +166,17 @@ design: (work@top) |vpiNet: \_logic_net: (work@top.topB), line:6:22, endln:6:26 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ModPortHighConn/dut.sv, line:5:1, endln:11:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ModPortHighConn/dut.sv, line:5:1, endln:11:10 |vpiTypespec: \_logic_typespec: , line:6:5, endln:6:15 |vpiName:topB |vpiFullName:work@top.topB |vpiNetType:1 |vpiTopModule:1 - |vpiModule: - \_module: work@moduleA (work@top.instanceA), file:${SURELOG_DIR}/tests/ModPortHighConn/dut.sv, line:7:5, endln:7:57 + |vpiModuleInst: + \_module_inst: work@moduleA (work@top.instanceA), file:${SURELOG_DIR}/tests/ModPortHighConn/dut.sv, line:7:5, endln:7:57 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ModPortHighConn/dut.sv, line:5:1, endln:11:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ModPortHighConn/dut.sv, line:5:1, endln:11:10 |vpiName:instanceA |vpiFullName:work@top.instanceA |vpiDefName:work@moduleA @@ -185,7 +185,7 @@ design: (work@top) |vpiNet: \_logic_net: (work@top.instanceA.port0), line:2:23, endln:2:28 |vpiParent: - \_module: work@moduleA (work@top.instanceA), file:${SURELOG_DIR}/tests/ModPortHighConn/dut.sv, line:7:5, endln:7:57 + \_module_inst: work@moduleA (work@top.instanceA), file:${SURELOG_DIR}/tests/ModPortHighConn/dut.sv, line:7:5, endln:7:57 |vpiTypespec: \_logic_typespec: , line:2:23, endln:2:23 |vpiName:port0 @@ -193,17 +193,17 @@ design: (work@top) |vpiNet: \_logic_net: (work@top.instanceA.port1), line:2:30, endln:2:35 |vpiParent: - \_module: work@moduleA (work@top.instanceA), file:${SURELOG_DIR}/tests/ModPortHighConn/dut.sv, line:7:5, endln:7:57 + \_module_inst: work@moduleA (work@top.instanceA), file:${SURELOG_DIR}/tests/ModPortHighConn/dut.sv, line:7:5, endln:7:57 |vpiTypespec: \_logic_typespec: , line:2:23, endln:2:23 |vpiName:port1 |vpiFullName:work@top.instanceA.port1 |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ModPortHighConn/dut.sv, line:5:1, endln:11:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ModPortHighConn/dut.sv, line:5:1, endln:11:10 |vpiPort: \_port: (port0), line:2:23, endln:2:28 |vpiParent: - \_module: work@moduleA (work@top.instanceA), file:${SURELOG_DIR}/tests/ModPortHighConn/dut.sv, line:7:5, endln:7:57 + \_module_inst: work@moduleA (work@top.instanceA), file:${SURELOG_DIR}/tests/ModPortHighConn/dut.sv, line:7:5, endln:7:57 |vpiName:port0 |vpiDirection:3 |vpiHighConn: @@ -231,7 +231,7 @@ design: (work@top) |vpiPort: \_port: (port1), line:2:30, endln:2:35 |vpiParent: - \_module: work@moduleA (work@top.instanceA), file:${SURELOG_DIR}/tests/ModPortHighConn/dut.sv, line:7:5, endln:7:57 + \_module_inst: work@moduleA (work@top.instanceA), file:${SURELOG_DIR}/tests/ModPortHighConn/dut.sv, line:7:5, endln:7:57 |vpiName:port1 |vpiDirection:3 |vpiHighConn: @@ -256,10 +256,10 @@ design: (work@top) \_logic_net: (work@top.instanceA.port1), line:2:30, endln:2:35 |vpiTypedef: \_logic_typespec: , line:2:23, endln:2:23 - |vpiModule: - \_module: work@moduleA (work@top.instanceB), file:${SURELOG_DIR}/tests/ModPortHighConn/dut.sv, line:8:5, endln:8:41 + |vpiModuleInst: + \_module_inst: work@moduleA (work@top.instanceB), file:${SURELOG_DIR}/tests/ModPortHighConn/dut.sv, line:8:5, endln:8:41 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ModPortHighConn/dut.sv, line:5:1, endln:11:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ModPortHighConn/dut.sv, line:5:1, endln:11:10 |vpiName:instanceB |vpiFullName:work@top.instanceB |vpiDefName:work@moduleA @@ -268,7 +268,7 @@ design: (work@top) |vpiNet: \_logic_net: (work@top.instanceB.port0), line:2:23, endln:2:28 |vpiParent: - \_module: work@moduleA (work@top.instanceB), file:${SURELOG_DIR}/tests/ModPortHighConn/dut.sv, line:8:5, endln:8:41 + \_module_inst: work@moduleA (work@top.instanceB), file:${SURELOG_DIR}/tests/ModPortHighConn/dut.sv, line:8:5, endln:8:41 |vpiTypespec: \_logic_typespec: , line:2:23, endln:2:23 |vpiName:port0 @@ -276,17 +276,17 @@ design: (work@top) |vpiNet: \_logic_net: (work@top.instanceB.port1), line:2:30, endln:2:35 |vpiParent: - \_module: work@moduleA (work@top.instanceB), file:${SURELOG_DIR}/tests/ModPortHighConn/dut.sv, line:8:5, endln:8:41 + \_module_inst: work@moduleA (work@top.instanceB), file:${SURELOG_DIR}/tests/ModPortHighConn/dut.sv, line:8:5, endln:8:41 |vpiTypespec: \_logic_typespec: , line:2:23, endln:2:23 |vpiName:port1 |vpiFullName:work@top.instanceB.port1 |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ModPortHighConn/dut.sv, line:5:1, endln:11:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ModPortHighConn/dut.sv, line:5:1, endln:11:10 |vpiPort: \_port: (port0), line:2:23, endln:2:28 |vpiParent: - \_module: work@moduleA (work@top.instanceB), file:${SURELOG_DIR}/tests/ModPortHighConn/dut.sv, line:8:5, endln:8:41 + \_module_inst: work@moduleA (work@top.instanceB), file:${SURELOG_DIR}/tests/ModPortHighConn/dut.sv, line:8:5, endln:8:41 |vpiName:port0 |vpiDirection:3 |vpiHighConn: @@ -314,7 +314,7 @@ design: (work@top) |vpiPort: \_port: (port1), line:2:30, endln:2:35 |vpiParent: - \_module: work@moduleA (work@top.instanceB), file:${SURELOG_DIR}/tests/ModPortHighConn/dut.sv, line:8:5, endln:8:41 + \_module_inst: work@moduleA (work@top.instanceB), file:${SURELOG_DIR}/tests/ModPortHighConn/dut.sv, line:8:5, endln:8:41 |vpiName:port1 |vpiDirection:3 |vpiHighConn: @@ -339,10 +339,10 @@ design: (work@top) \_logic_net: (work@top.instanceB.port1), line:2:30, endln:2:35 |vpiTypedef: \_logic_typespec: , line:2:23, endln:2:23 - |vpiModule: - \_module: work@moduleA (work@top.instanceC), file:${SURELOG_DIR}/tests/ModPortHighConn/dut.sv, line:9:5, endln:9:50 + |vpiModuleInst: + \_module_inst: work@moduleA (work@top.instanceC), file:${SURELOG_DIR}/tests/ModPortHighConn/dut.sv, line:9:5, endln:9:50 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ModPortHighConn/dut.sv, line:5:1, endln:11:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ModPortHighConn/dut.sv, line:5:1, endln:11:10 |vpiName:instanceC |vpiFullName:work@top.instanceC |vpiDefName:work@moduleA @@ -351,7 +351,7 @@ design: (work@top) |vpiNet: \_logic_net: (work@top.instanceC.port0), line:2:23, endln:2:28 |vpiParent: - \_module: work@moduleA (work@top.instanceC), file:${SURELOG_DIR}/tests/ModPortHighConn/dut.sv, line:9:5, endln:9:50 + \_module_inst: work@moduleA (work@top.instanceC), file:${SURELOG_DIR}/tests/ModPortHighConn/dut.sv, line:9:5, endln:9:50 |vpiTypespec: \_logic_typespec: , line:2:23, endln:2:23 |vpiName:port0 @@ -359,17 +359,17 @@ design: (work@top) |vpiNet: \_logic_net: (work@top.instanceC.port1), line:2:30, endln:2:35 |vpiParent: - \_module: work@moduleA (work@top.instanceC), file:${SURELOG_DIR}/tests/ModPortHighConn/dut.sv, line:9:5, endln:9:50 + \_module_inst: work@moduleA (work@top.instanceC), file:${SURELOG_DIR}/tests/ModPortHighConn/dut.sv, line:9:5, endln:9:50 |vpiTypespec: \_logic_typespec: , line:2:23, endln:2:23 |vpiName:port1 |vpiFullName:work@top.instanceC.port1 |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ModPortHighConn/dut.sv, line:5:1, endln:11:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ModPortHighConn/dut.sv, line:5:1, endln:11:10 |vpiPort: \_port: (port0), line:2:23, endln:2:28 |vpiParent: - \_module: work@moduleA (work@top.instanceC), file:${SURELOG_DIR}/tests/ModPortHighConn/dut.sv, line:9:5, endln:9:50 + \_module_inst: work@moduleA (work@top.instanceC), file:${SURELOG_DIR}/tests/ModPortHighConn/dut.sv, line:9:5, endln:9:50 |vpiName:port0 |vpiDirection:3 |vpiHighConn: @@ -397,7 +397,7 @@ design: (work@top) |vpiPort: \_port: (port1), line:2:30, endln:2:35 |vpiParent: - \_module: work@moduleA (work@top.instanceC), file:${SURELOG_DIR}/tests/ModPortHighConn/dut.sv, line:9:5, endln:9:50 + \_module_inst: work@moduleA (work@top.instanceC), file:${SURELOG_DIR}/tests/ModPortHighConn/dut.sv, line:9:5, endln:9:50 |vpiName:port1 |vpiDirection:3 |vpiHighConn: @@ -443,10 +443,10 @@ design: (work@top) \_logic_net: (work@top.instanceC.port1), line:2:30, endln:2:35 |vpiTypedef: \_logic_typespec: , line:2:23, endln:2:23 - |vpiModule: - \_module: work@moduleA (work@top.instanceD), file:${SURELOG_DIR}/tests/ModPortHighConn/dut.sv, line:10:5, endln:10:50 + |vpiModuleInst: + \_module_inst: work@moduleA (work@top.instanceD), file:${SURELOG_DIR}/tests/ModPortHighConn/dut.sv, line:10:5, endln:10:50 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ModPortHighConn/dut.sv, line:5:1, endln:11:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ModPortHighConn/dut.sv, line:5:1, endln:11:10 |vpiName:instanceD |vpiFullName:work@top.instanceD |vpiDefName:work@moduleA @@ -455,7 +455,7 @@ design: (work@top) |vpiNet: \_logic_net: (work@top.instanceD.port0), line:2:23, endln:2:28 |vpiParent: - \_module: work@moduleA (work@top.instanceD), file:${SURELOG_DIR}/tests/ModPortHighConn/dut.sv, line:10:5, endln:10:50 + \_module_inst: work@moduleA (work@top.instanceD), file:${SURELOG_DIR}/tests/ModPortHighConn/dut.sv, line:10:5, endln:10:50 |vpiTypespec: \_logic_typespec: , line:2:23, endln:2:23 |vpiName:port0 @@ -463,17 +463,17 @@ design: (work@top) |vpiNet: \_logic_net: (work@top.instanceD.port1), line:2:30, endln:2:35 |vpiParent: - \_module: work@moduleA (work@top.instanceD), file:${SURELOG_DIR}/tests/ModPortHighConn/dut.sv, line:10:5, endln:10:50 + \_module_inst: work@moduleA (work@top.instanceD), file:${SURELOG_DIR}/tests/ModPortHighConn/dut.sv, line:10:5, endln:10:50 |vpiTypespec: \_logic_typespec: , line:2:23, endln:2:23 |vpiName:port1 |vpiFullName:work@top.instanceD.port1 |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ModPortHighConn/dut.sv, line:5:1, endln:11:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ModPortHighConn/dut.sv, line:5:1, endln:11:10 |vpiPort: \_port: (port0), line:2:23, endln:2:28 |vpiParent: - \_module: work@moduleA (work@top.instanceD), file:${SURELOG_DIR}/tests/ModPortHighConn/dut.sv, line:10:5, endln:10:50 + \_module_inst: work@moduleA (work@top.instanceD), file:${SURELOG_DIR}/tests/ModPortHighConn/dut.sv, line:10:5, endln:10:50 |vpiName:port0 |vpiDirection:3 |vpiHighConn: @@ -522,7 +522,7 @@ design: (work@top) |vpiPort: \_port: (port1), line:2:30, endln:2:35 |vpiParent: - \_module: work@moduleA (work@top.instanceD), file:${SURELOG_DIR}/tests/ModPortHighConn/dut.sv, line:10:5, endln:10:50 + \_module_inst: work@moduleA (work@top.instanceD), file:${SURELOG_DIR}/tests/ModPortHighConn/dut.sv, line:10:5, endln:10:50 |vpiName:port1 |vpiDirection:3 |vpiHighConn: diff --git a/tests/ModPortParam/ModPortParam.log b/tests/ModPortParam/ModPortParam.log index 02baa95fb3..3d7d07dfa1 100644 --- a/tests/ModPortParam/ModPortParam.log +++ b/tests/ModPortParam/ModPortParam.log @@ -100,12 +100,12 @@ n<> u<65> t c<1> l<1:1> el<18:1> === UHDM Object Stats Begin (Non-Elaborated Model) === design 1 -interface 4 +interface_inst 4 interface_typespec 6 io_decl 4 logic_net 1 modport 4 -module 5 +module_inst 5 port 2 ref_obj 4 === UHDM Object Stats End === @@ -113,12 +113,12 @@ ref_obj 4 === UHDM Object Stats Begin (Elaborated Model) === design 1 -interface 4 +interface_inst 4 interface_typespec 6 io_decl 4 logic_net 1 modport 4 -module 5 +module_inst 5 port 3 ref_obj 6 === UHDM Object Stats End === @@ -135,7 +135,7 @@ design: (work@Core) |vpiElaborated:1 |vpiName:work@Core |uhdmallInterfaces: -\_interface: work@PerformanceCounterIF (work@PerformanceCounterIF), file:${SURELOG_DIR}/tests/ModPortParam/dut.sv, line:1:1, endln:6:13 +\_interface_inst: work@PerformanceCounterIF (work@PerformanceCounterIF), file:${SURELOG_DIR}/tests/ModPortParam/dut.sv, line:1:1, endln:6:13 |vpiParent: \_design: (work@Core) |vpiFullName:work@PerformanceCounterIF @@ -143,14 +143,14 @@ design: (work@Core) |vpiModport: \_modport: (CSR), line:2:13, endln:2:16 |vpiParent: - \_interface: work@PerformanceCounterIF (work@PerformanceCounterIF), file:${SURELOG_DIR}/tests/ModPortParam/dut.sv, line:1:1, endln:6:13 + \_interface_inst: work@PerformanceCounterIF (work@PerformanceCounterIF), file:${SURELOG_DIR}/tests/ModPortParam/dut.sv, line:1:1, endln:6:13 |vpiName:CSR |vpiIODecl: \_io_decl: (perfCounter), line:4:9, endln:4:20 |vpiDirection:1 |vpiName:perfCounter |uhdmallModules: -\_module: work@CSR_Unit (work@CSR_Unit), file:${SURELOG_DIR}/tests/ModPortParam/dut.sv, line:8:1, endln:11:10 +\_module_inst: work@CSR_Unit (work@CSR_Unit), file:${SURELOG_DIR}/tests/ModPortParam/dut.sv, line:8:1, endln:11:10 |vpiParent: \_design: (work@Core) |vpiFullName:work@CSR_Unit @@ -158,13 +158,13 @@ design: (work@Core) |vpiNet: \_logic_net: (work@CSR_Unit.perfCounter), line:9:30, endln:9:41 |vpiParent: - \_module: work@CSR_Unit (work@CSR_Unit), file:${SURELOG_DIR}/tests/ModPortParam/dut.sv, line:8:1, endln:11:10 + \_module_inst: work@CSR_Unit (work@CSR_Unit), file:${SURELOG_DIR}/tests/ModPortParam/dut.sv, line:8:1, endln:11:10 |vpiName:perfCounter |vpiFullName:work@CSR_Unit.perfCounter |vpiPort: \_port: (perfCounter), line:9:30, endln:9:41 |vpiParent: - \_module: work@CSR_Unit (work@CSR_Unit), file:${SURELOG_DIR}/tests/ModPortParam/dut.sv, line:8:1, endln:11:10 + \_module_inst: work@CSR_Unit (work@CSR_Unit), file:${SURELOG_DIR}/tests/ModPortParam/dut.sv, line:8:1, endln:11:10 |vpiName:perfCounter |vpiDirection:3 |vpiLowConn: @@ -178,32 +178,32 @@ design: (work@Core) |vpiName:CSR |vpiIsModPort:1 |uhdmallModules: -\_module: work@Core (work@Core), file:${SURELOG_DIR}/tests/ModPortParam/dut.sv, line:13:1, endln:17:10 +\_module_inst: work@Core (work@Core), file:${SURELOG_DIR}/tests/ModPortParam/dut.sv, line:13:1, endln:17:10 |vpiParent: \_design: (work@Core) |vpiFullName:work@Core |vpiDefName:work@Core |uhdmtopModules: -\_module: work@Core (work@Core), file:${SURELOG_DIR}/tests/ModPortParam/dut.sv, line:13:1, endln:17:10 +\_module_inst: work@Core (work@Core), file:${SURELOG_DIR}/tests/ModPortParam/dut.sv, line:13:1, endln:17:10 |vpiName:work@Core |vpiDefName:work@Core |vpiTop:1 |vpiTopModule:1 - |vpiInterface: - \_interface: work@PerformanceCounterIF (work@Core.perfCounterIF), file:${SURELOG_DIR}/tests/ModPortParam/dut.sv, line:14:2, endln:14:40 + |vpiInterfaceInst: + \_interface_inst: work@PerformanceCounterIF (work@Core.perfCounterIF), file:${SURELOG_DIR}/tests/ModPortParam/dut.sv, line:14:2, endln:14:40 |vpiParent: - \_module: work@Core (work@Core), file:${SURELOG_DIR}/tests/ModPortParam/dut.sv, line:13:1, endln:17:10 + \_module_inst: work@Core (work@Core), file:${SURELOG_DIR}/tests/ModPortParam/dut.sv, line:13:1, endln:17:10 |vpiName:perfCounterIF |vpiFullName:work@Core.perfCounterIF |vpiDefName:work@PerformanceCounterIF |vpiDefFile:${SURELOG_DIR}/tests/ModPortParam/dut.sv |vpiDefLineNo:1 |vpiInstance: - \_module: work@Core (work@Core), file:${SURELOG_DIR}/tests/ModPortParam/dut.sv, line:13:1, endln:17:10 + \_module_inst: work@Core (work@Core), file:${SURELOG_DIR}/tests/ModPortParam/dut.sv, line:13:1, endln:17:10 |vpiModport: \_modport: (CSR), line:2:13, endln:2:16 |vpiParent: - \_interface: work@PerformanceCounterIF (work@Core.perfCounterIF), file:${SURELOG_DIR}/tests/ModPortParam/dut.sv, line:14:2, endln:14:40 + \_interface_inst: work@PerformanceCounterIF (work@Core.perfCounterIF), file:${SURELOG_DIR}/tests/ModPortParam/dut.sv, line:14:2, endln:14:40 |vpiName:CSR |vpiIODecl: \_io_decl: (perfCounter), line:4:9, endln:4:20 @@ -211,23 +211,23 @@ design: (work@Core) \_modport: (CSR), line:2:13, endln:2:16 |vpiDirection:1 |vpiName:perfCounter - |vpiInterface: - \_interface: work@PerformanceCounterIF (work@Core.perfCounterIF), file:${SURELOG_DIR}/tests/ModPortParam/dut.sv, line:14:2, endln:14:40 - |vpiModule: - \_module: work@CSR_Unit (work@Core.csrUnit), file:${SURELOG_DIR}/tests/ModPortParam/dut.sv, line:16:2, endln:16:34 + |vpiInterfaceInst: + \_interface_inst: work@PerformanceCounterIF (work@Core.perfCounterIF), file:${SURELOG_DIR}/tests/ModPortParam/dut.sv, line:14:2, endln:14:40 + |vpiModuleInst: + \_module_inst: work@CSR_Unit (work@Core.csrUnit), file:${SURELOG_DIR}/tests/ModPortParam/dut.sv, line:16:2, endln:16:34 |vpiParent: - \_module: work@Core (work@Core), file:${SURELOG_DIR}/tests/ModPortParam/dut.sv, line:13:1, endln:17:10 + \_module_inst: work@Core (work@Core), file:${SURELOG_DIR}/tests/ModPortParam/dut.sv, line:13:1, endln:17:10 |vpiName:csrUnit |vpiFullName:work@Core.csrUnit |vpiDefName:work@CSR_Unit |vpiDefFile:${SURELOG_DIR}/tests/ModPortParam/dut.sv |vpiDefLineNo:8 |vpiInstance: - \_module: work@Core (work@Core), file:${SURELOG_DIR}/tests/ModPortParam/dut.sv, line:13:1, endln:17:10 + \_module_inst: work@Core (work@Core), file:${SURELOG_DIR}/tests/ModPortParam/dut.sv, line:13:1, endln:17:10 |vpiPort: \_port: (perfCounter), line:9:30, endln:9:41 |vpiParent: - \_module: work@CSR_Unit (work@Core.csrUnit), file:${SURELOG_DIR}/tests/ModPortParam/dut.sv, line:16:2, endln:16:34 + \_module_inst: work@CSR_Unit (work@Core.csrUnit), file:${SURELOG_DIR}/tests/ModPortParam/dut.sv, line:16:2, endln:16:34 |vpiName:perfCounter |vpiDirection:3 |vpiHighConn: @@ -237,7 +237,7 @@ design: (work@Core) |vpiName:perfCounterIF |vpiFullName:work@Core.perfCounterIF |vpiActual: - \_interface: work@PerformanceCounterIF (work@Core.perfCounterIF), file:${SURELOG_DIR}/tests/ModPortParam/dut.sv, line:14:2, endln:14:40 + \_interface_inst: work@PerformanceCounterIF (work@Core.perfCounterIF), file:${SURELOG_DIR}/tests/ModPortParam/dut.sv, line:14:2, endln:14:40 |vpiLowConn: \_ref_obj: (work@Core.csrUnit.perfCounter), line:16:19, endln:16:32 |vpiParent: @@ -252,18 +252,18 @@ design: (work@Core) |vpiName:CSR |vpiIsModPort:1 |vpiInstance: - \_module: work@CSR_Unit (work@Core.csrUnit), file:${SURELOG_DIR}/tests/ModPortParam/dut.sv, line:16:2, endln:16:34 - |vpiInterface: - \_interface: work@PerformanceCounterIF (work@Core.csrUnit.perfCounter), file:${SURELOG_DIR}/tests/ModPortParam/dut.sv, line:16:0 + \_module_inst: work@CSR_Unit (work@Core.csrUnit), file:${SURELOG_DIR}/tests/ModPortParam/dut.sv, line:16:2, endln:16:34 + |vpiInterfaceInst: + \_interface_inst: work@PerformanceCounterIF (work@Core.csrUnit.perfCounter), file:${SURELOG_DIR}/tests/ModPortParam/dut.sv, line:16:0 |vpiParent: - \_module: work@CSR_Unit (work@Core.csrUnit), file:${SURELOG_DIR}/tests/ModPortParam/dut.sv, line:16:2, endln:16:34 + \_module_inst: work@CSR_Unit (work@Core.csrUnit), file:${SURELOG_DIR}/tests/ModPortParam/dut.sv, line:16:2, endln:16:34 |vpiName:perfCounter |vpiFullName:work@Core.csrUnit.perfCounter |vpiDefName:work@PerformanceCounterIF |vpiModport: \_modport: (CSR), line:2:13, endln:2:16 |vpiParent: - \_interface: work@PerformanceCounterIF (work@Core.csrUnit.perfCounter), file:${SURELOG_DIR}/tests/ModPortParam/dut.sv, line:16:0 + \_interface_inst: work@PerformanceCounterIF (work@Core.csrUnit.perfCounter), file:${SURELOG_DIR}/tests/ModPortParam/dut.sv, line:16:0 |vpiName:CSR |vpiIODecl: \_io_decl: (perfCounter), line:4:9, endln:4:20 @@ -274,9 +274,9 @@ design: (work@Core) |vpiName:perfCounter |vpiFullName:work@Core.csrUnit.perfCounter |vpiActual: - \_interface: work@PerformanceCounterIF (work@Core.csrUnit.perfCounter), file:${SURELOG_DIR}/tests/ModPortParam/dut.sv, line:16:0 - |vpiInterface: - \_interface: work@PerformanceCounterIF (work@Core.csrUnit.perfCounter), file:${SURELOG_DIR}/tests/ModPortParam/dut.sv, line:16:0 + \_interface_inst: work@PerformanceCounterIF (work@Core.csrUnit.perfCounter), file:${SURELOG_DIR}/tests/ModPortParam/dut.sv, line:16:0 + |vpiInterfaceInst: + \_interface_inst: work@PerformanceCounterIF (work@Core.csrUnit.perfCounter), file:${SURELOG_DIR}/tests/ModPortParam/dut.sv, line:16:0 =================== [ FATAL] : 0 [ SYNTAX] : 0 diff --git a/tests/ModPortRange/ModPortRange.log b/tests/ModPortRange/ModPortRange.log index 0e8f8fe948..76840a1cff 100644 --- a/tests/ModPortRange/ModPortRange.log +++ b/tests/ModPortRange/ModPortRange.log @@ -59,15 +59,15 @@ array_net 1 array_typespec 5 constant 36 design 1 -interface 13 interface_array 8 +interface_inst 13 interface_typespec 40 io_decl 13 logic_net 16 logic_typespec 16 logic_var 7 modport 13 -module 11 +module_inst 11 port 23 range 18 ref_obj 23 @@ -79,15 +79,15 @@ array_net 1 array_typespec 5 constant 36 design 1 -interface 13 interface_array 8 +interface_inst 13 interface_typespec 40 io_decl 13 logic_net 16 logic_typespec 16 logic_var 7 modport 13 -module 11 +module_inst 11 port 32 range 18 ref_obj 32 @@ -105,7 +105,7 @@ design: (work@range_itf_port) |vpiElaborated:1 |vpiName:work@range_itf_port |uhdmallInterfaces: -\_interface: work@ConnectTB (work@ConnectTB), file:${SURELOG_DIR}/tests/ModPortRange/dut.sv, line:32:1, endln:33:13 +\_interface_inst: work@ConnectTB (work@ConnectTB), file:${SURELOG_DIR}/tests/ModPortRange/dut.sv, line:32:1, endln:33:13 |vpiParent: \_design: (work@range_itf_port) |vpiFullName:work@ConnectTB @@ -113,14 +113,14 @@ design: (work@range_itf_port) |vpiNet: \_logic_net: (work@ConnectTB.con_i), line:32:40, endln:32:45 |vpiParent: - \_interface: work@ConnectTB (work@ConnectTB), file:${SURELOG_DIR}/tests/ModPortRange/dut.sv, line:32:1, endln:33:13 + \_interface_inst: work@ConnectTB (work@ConnectTB), file:${SURELOG_DIR}/tests/ModPortRange/dut.sv, line:32:1, endln:33:13 |vpiName:con_i |vpiFullName:work@ConnectTB.con_i |vpiNetType:1 |vpiPort: \_port: (con_i), line:32:40, endln:32:45 |vpiParent: - \_interface: work@ConnectTB (work@ConnectTB), file:${SURELOG_DIR}/tests/ModPortRange/dut.sv, line:32:1, endln:33:13 + \_interface_inst: work@ConnectTB (work@ConnectTB), file:${SURELOG_DIR}/tests/ModPortRange/dut.sv, line:32:1, endln:33:13 |vpiName:con_i |vpiDirection:1 |vpiLowConn: @@ -128,7 +128,7 @@ design: (work@range_itf_port) |vpiActual: \_logic_net: (work@ConnectTB.con_i), line:32:40, endln:32:45 |uhdmallInterfaces: -\_interface: work@MyInterface (work@MyInterface), file:${SURELOG_DIR}/tests/ModPortRange/dut.sv, line:1:1, endln:7:13 +\_interface_inst: work@MyInterface (work@MyInterface), file:${SURELOG_DIR}/tests/ModPortRange/dut.sv, line:1:1, endln:7:13 |vpiParent: \_design: (work@range_itf_port) |vpiFullName:work@MyInterface @@ -136,21 +136,21 @@ design: (work@range_itf_port) |vpiNet: \_logic_net: (work@MyInterface.my_logic), line:2:10, endln:2:18 |vpiParent: - \_interface: work@MyInterface (work@MyInterface), file:${SURELOG_DIR}/tests/ModPortRange/dut.sv, line:1:1, endln:7:13 + \_interface_inst: work@MyInterface (work@MyInterface), file:${SURELOG_DIR}/tests/ModPortRange/dut.sv, line:1:1, endln:7:13 |vpiName:my_logic |vpiFullName:work@MyInterface.my_logic |vpiNetType:36 |vpiModport: \_modport: (MyModPort), line:3:12, endln:3:21 |vpiParent: - \_interface: work@MyInterface (work@MyInterface), file:${SURELOG_DIR}/tests/ModPortRange/dut.sv, line:1:1, endln:7:13 + \_interface_inst: work@MyInterface (work@MyInterface), file:${SURELOG_DIR}/tests/ModPortRange/dut.sv, line:1:1, endln:7:13 |vpiName:MyModPort |vpiIODecl: \_io_decl: (my_logic), line:5:19, endln:5:27 |vpiDirection:2 |vpiName:my_logic |uhdmallInterfaces: -\_interface: work@mem_if (work@mem_if), file:${SURELOG_DIR}/tests/ModPortRange/dut.sv, line:17:1, endln:22:13 +\_interface_inst: work@mem_if (work@mem_if), file:${SURELOG_DIR}/tests/ModPortRange/dut.sv, line:17:1, endln:22:13 |vpiParent: \_design: (work@range_itf_port) |vpiFullName:work@mem_if @@ -158,14 +158,14 @@ design: (work@range_itf_port) |vpiNet: \_logic_net: (work@mem_if.clk), line:17:30, endln:17:33 |vpiParent: - \_interface: work@mem_if (work@mem_if), file:${SURELOG_DIR}/tests/ModPortRange/dut.sv, line:17:1, endln:22:13 + \_interface_inst: work@mem_if (work@mem_if), file:${SURELOG_DIR}/tests/ModPortRange/dut.sv, line:17:1, endln:22:13 |vpiName:clk |vpiFullName:work@mem_if.clk |vpiNetType:1 |vpiModport: \_modport: (memory), line:20:12, endln:20:18 |vpiParent: - \_interface: work@mem_if (work@mem_if), file:${SURELOG_DIR}/tests/ModPortRange/dut.sv, line:17:1, endln:22:13 + \_interface_inst: work@mem_if (work@mem_if), file:${SURELOG_DIR}/tests/ModPortRange/dut.sv, line:17:1, endln:22:13 |vpiName:memory |vpiIODecl: \_io_decl: (clk), line:20:27, endln:20:30 @@ -174,7 +174,7 @@ design: (work@range_itf_port) |vpiModport: \_modport: (system), line:19:12, endln:19:18 |vpiParent: - \_interface: work@mem_if (work@mem_if), file:${SURELOG_DIR}/tests/ModPortRange/dut.sv, line:17:1, endln:22:13 + \_interface_inst: work@mem_if (work@mem_if), file:${SURELOG_DIR}/tests/ModPortRange/dut.sv, line:17:1, endln:22:13 |vpiName:system |vpiIODecl: \_io_decl: (clk), line:19:26, endln:19:29 @@ -183,7 +183,7 @@ design: (work@range_itf_port) |vpiPort: \_port: (clk), line:17:30, endln:17:33 |vpiParent: - \_interface: work@mem_if (work@mem_if), file:${SURELOG_DIR}/tests/ModPortRange/dut.sv, line:17:1, endln:22:13 + \_interface_inst: work@mem_if (work@mem_if), file:${SURELOG_DIR}/tests/ModPortRange/dut.sv, line:17:1, endln:22:13 |vpiName:clk |vpiDirection:1 |vpiLowConn: @@ -191,7 +191,7 @@ design: (work@range_itf_port) |vpiActual: \_logic_net: (work@mem_if.clk), line:17:30, endln:17:33 |uhdmallModules: -\_module: work@memory_ctrl1 (work@memory_ctrl1), file:${SURELOG_DIR}/tests/ModPortRange/dut.sv, line:25:1, endln:28:10 +\_module_inst: work@memory_ctrl1 (work@memory_ctrl1), file:${SURELOG_DIR}/tests/ModPortRange/dut.sv, line:25:1, endln:28:10 |vpiParent: \_design: (work@range_itf_port) |vpiFullName:work@memory_ctrl1 @@ -199,32 +199,32 @@ design: (work@range_itf_port) |vpiNet: \_logic_net: (work@memory_ctrl1.sif1), line:25:29, endln:25:33 |vpiParent: - \_module: work@memory_ctrl1 (work@memory_ctrl1), file:${SURELOG_DIR}/tests/ModPortRange/dut.sv, line:25:1, endln:28:10 + \_module_inst: work@memory_ctrl1 (work@memory_ctrl1), file:${SURELOG_DIR}/tests/ModPortRange/dut.sv, line:25:1, endln:28:10 |vpiName:sif1 |vpiFullName:work@memory_ctrl1.sif1 |vpiNet: \_logic_net: (work@memory_ctrl1.sif2), line:25:49, endln:25:53 |vpiParent: - \_module: work@memory_ctrl1 (work@memory_ctrl1), file:${SURELOG_DIR}/tests/ModPortRange/dut.sv, line:25:1, endln:28:10 + \_module_inst: work@memory_ctrl1 (work@memory_ctrl1), file:${SURELOG_DIR}/tests/ModPortRange/dut.sv, line:25:1, endln:28:10 |vpiName:sif2 |vpiFullName:work@memory_ctrl1.sif2 |vpiPort: \_port: (sif1), line:25:29, endln:25:33 |vpiParent: - \_module: work@memory_ctrl1 (work@memory_ctrl1), file:${SURELOG_DIR}/tests/ModPortRange/dut.sv, line:25:1, endln:28:10 + \_module_inst: work@memory_ctrl1 (work@memory_ctrl1), file:${SURELOG_DIR}/tests/ModPortRange/dut.sv, line:25:1, endln:28:10 |vpiName:sif1 |vpiDirection:3 |vpiLowConn: \_ref_obj: |vpiActual: - \_interface: work@mem_if (work@mem_if), file:${SURELOG_DIR}/tests/ModPortRange/dut.sv, line:17:1, endln:22:13 + \_interface_inst: work@mem_if (work@mem_if), file:${SURELOG_DIR}/tests/ModPortRange/dut.sv, line:17:1, endln:22:13 |vpiTypedef: \_interface_typespec: (mem_if), line:25:22, endln:25:28 |vpiName:mem_if |vpiPort: \_port: (sif2), line:25:49, endln:25:53 |vpiParent: - \_module: work@memory_ctrl1 (work@memory_ctrl1), file:${SURELOG_DIR}/tests/ModPortRange/dut.sv, line:25:1, endln:28:10 + \_module_inst: work@memory_ctrl1 (work@memory_ctrl1), file:${SURELOG_DIR}/tests/ModPortRange/dut.sv, line:25:1, endln:28:10 |vpiName:sif2 |vpiDirection:3 |vpiLowConn: @@ -238,7 +238,7 @@ design: (work@range_itf_port) |vpiName:system |vpiIsModPort:1 |uhdmallModules: -\_module: work@middle (work@middle), file:${SURELOG_DIR}/tests/ModPortRange/dut.sv, line:35:1, endln:36:10 +\_module_inst: work@middle (work@middle), file:${SURELOG_DIR}/tests/ModPortRange/dut.sv, line:35:1, endln:36:10 |vpiParent: \_design: (work@range_itf_port) |vpiFullName:work@middle @@ -246,19 +246,19 @@ design: (work@range_itf_port) |vpiNet: \_logic_net: (work@middle.conn1), line:35:26, endln:35:31 |vpiParent: - \_module: work@middle (work@middle), file:${SURELOG_DIR}/tests/ModPortRange/dut.sv, line:35:1, endln:36:10 + \_module_inst: work@middle (work@middle), file:${SURELOG_DIR}/tests/ModPortRange/dut.sv, line:35:1, endln:36:10 |vpiName:conn1 |vpiFullName:work@middle.conn1 |vpiPort: \_port: (conn1), line:35:26, endln:35:31 |vpiParent: - \_module: work@middle (work@middle), file:${SURELOG_DIR}/tests/ModPortRange/dut.sv, line:35:1, endln:36:10 + \_module_inst: work@middle (work@middle), file:${SURELOG_DIR}/tests/ModPortRange/dut.sv, line:35:1, endln:36:10 |vpiName:conn1 |vpiDirection:3 |vpiLowConn: \_ref_obj: |vpiActual: - \_interface: work@ConnectTB (work@ConnectTB), file:${SURELOG_DIR}/tests/ModPortRange/dut.sv, line:32:1, endln:33:13 + \_interface_inst: work@ConnectTB (work@ConnectTB), file:${SURELOG_DIR}/tests/ModPortRange/dut.sv, line:32:1, endln:33:13 |vpiTypedef: \_array_typespec: , line:35:16, endln:35:37 |vpiParent: @@ -288,7 +288,7 @@ design: (work@range_itf_port) |vpiInterfaceArray: \_interface_array: (ConnectTB), line:35:26, endln:35:31 |vpiParent: - \_module: work@middle (work@middle), file:${SURELOG_DIR}/tests/ModPortRange/dut.sv, line:35:1, endln:36:10 + \_module_inst: work@middle (work@middle), file:${SURELOG_DIR}/tests/ModPortRange/dut.sv, line:35:1, endln:36:10 |vpiName:conn1 |vpiFullName:ConnectTB |vpiRange: @@ -313,7 +313,7 @@ design: (work@range_itf_port) \_interface_typespec: (ConnectTB), line:35:16, endln:35:25 |vpiName:ConnectTB |uhdmallModules: -\_module: work@range_itf_port (work@range_itf_port), file:${SURELOG_DIR}/tests/ModPortRange/dut.sv, line:9:1, endln:13:10 +\_module_inst: work@range_itf_port (work@range_itf_port), file:${SURELOG_DIR}/tests/ModPortRange/dut.sv, line:9:1, endln:13:10 |vpiParent: \_design: (work@range_itf_port) |vpiFullName:work@range_itf_port @@ -321,20 +321,20 @@ design: (work@range_itf_port) |vpiNet: \_logic_net: (work@range_itf_port.my_port2), line:11:17, endln:11:25 |vpiParent: - \_module: work@range_itf_port (work@range_itf_port), file:${SURELOG_DIR}/tests/ModPortRange/dut.sv, line:9:1, endln:13:10 + \_module_inst: work@range_itf_port (work@range_itf_port), file:${SURELOG_DIR}/tests/ModPortRange/dut.sv, line:9:1, endln:13:10 |vpiName:my_port2 |vpiFullName:work@range_itf_port.my_port2 |vpiNetType:36 |vpiNet: \_logic_net: (work@range_itf_port.my_port1), line:10:27, endln:10:35 |vpiParent: - \_module: work@range_itf_port (work@range_itf_port), file:${SURELOG_DIR}/tests/ModPortRange/dut.sv, line:9:1, endln:13:10 + \_module_inst: work@range_itf_port (work@range_itf_port), file:${SURELOG_DIR}/tests/ModPortRange/dut.sv, line:9:1, endln:13:10 |vpiName:my_port1 |vpiFullName:work@range_itf_port.my_port1 |vpiPort: \_port: (my_port1), line:10:27, endln:10:35 |vpiParent: - \_module: work@range_itf_port (work@range_itf_port), file:${SURELOG_DIR}/tests/ModPortRange/dut.sv, line:9:1, endln:13:10 + \_module_inst: work@range_itf_port (work@range_itf_port), file:${SURELOG_DIR}/tests/ModPortRange/dut.sv, line:9:1, endln:13:10 |vpiName:my_port1 |vpiDirection:3 |vpiLowConn: @@ -373,7 +373,7 @@ design: (work@range_itf_port) |vpiPort: \_port: (my_port2), line:11:17, endln:11:25 |vpiParent: - \_module: work@range_itf_port (work@range_itf_port), file:${SURELOG_DIR}/tests/ModPortRange/dut.sv, line:9:1, endln:13:10 + \_module_inst: work@range_itf_port (work@range_itf_port), file:${SURELOG_DIR}/tests/ModPortRange/dut.sv, line:9:1, endln:13:10 |vpiName:my_port2 |vpiDirection:1 |vpiLowConn: @@ -408,7 +408,7 @@ design: (work@range_itf_port) |vpiInterfaceArray: \_interface_array: (MyInterface.MyModPort), line:10:27, endln:10:35 |vpiParent: - \_module: work@range_itf_port (work@range_itf_port), file:${SURELOG_DIR}/tests/ModPortRange/dut.sv, line:9:1, endln:13:10 + \_module_inst: work@range_itf_port (work@range_itf_port), file:${SURELOG_DIR}/tests/ModPortRange/dut.sv, line:9:1, endln:13:10 |vpiName:my_port1 |vpiFullName:MyInterface.MyModPort |vpiRange: @@ -433,7 +433,7 @@ design: (work@range_itf_port) \_interface_typespec: (MyInterface.MyModPort), line:10:5, endln:10:26 |vpiName:MyInterface.MyModPort |uhdmallModules: -\_module: work@range_itf_port2 (work@range_itf_port2), file:${SURELOG_DIR}/tests/ModPortRange/dut.sv, line:39:1, endln:46:10 +\_module_inst: work@range_itf_port2 (work@range_itf_port2), file:${SURELOG_DIR}/tests/ModPortRange/dut.sv, line:39:1, endln:46:10 |vpiParent: \_design: (work@range_itf_port) |vpiFullName:work@range_itf_port2 @@ -441,31 +441,31 @@ design: (work@range_itf_port) |vpiNet: \_logic_net: (work@range_itf_port2.my_port1), line:40:27, endln:40:35 |vpiParent: - \_module: work@range_itf_port2 (work@range_itf_port2), file:${SURELOG_DIR}/tests/ModPortRange/dut.sv, line:39:1, endln:46:10 + \_module_inst: work@range_itf_port2 (work@range_itf_port2), file:${SURELOG_DIR}/tests/ModPortRange/dut.sv, line:39:1, endln:46:10 |vpiName:my_port1 |vpiFullName:work@range_itf_port2.my_port1 |vpiNet: \_logic_net: (work@range_itf_port2.my_port2), line:41:27, endln:41:35 |vpiParent: - \_module: work@range_itf_port2 (work@range_itf_port2), file:${SURELOG_DIR}/tests/ModPortRange/dut.sv, line:39:1, endln:46:10 + \_module_inst: work@range_itf_port2 (work@range_itf_port2), file:${SURELOG_DIR}/tests/ModPortRange/dut.sv, line:39:1, endln:46:10 |vpiName:my_port2 |vpiFullName:work@range_itf_port2.my_port2 |vpiNet: \_logic_net: (work@range_itf_port2.my_port3), line:42:18, endln:42:26 |vpiParent: - \_module: work@range_itf_port2 (work@range_itf_port2), file:${SURELOG_DIR}/tests/ModPortRange/dut.sv, line:39:1, endln:46:10 + \_module_inst: work@range_itf_port2 (work@range_itf_port2), file:${SURELOG_DIR}/tests/ModPortRange/dut.sv, line:39:1, endln:46:10 |vpiName:my_port3 |vpiFullName:work@range_itf_port2.my_port3 |vpiNet: \_logic_net: (work@range_itf_port2.my_port4), line:43:18, endln:43:26 |vpiParent: - \_module: work@range_itf_port2 (work@range_itf_port2), file:${SURELOG_DIR}/tests/ModPortRange/dut.sv, line:39:1, endln:46:10 + \_module_inst: work@range_itf_port2 (work@range_itf_port2), file:${SURELOG_DIR}/tests/ModPortRange/dut.sv, line:39:1, endln:46:10 |vpiName:my_port4 |vpiFullName:work@range_itf_port2.my_port4 |vpiPort: \_port: (my_port1), line:40:27, endln:40:35 |vpiParent: - \_module: work@range_itf_port2 (work@range_itf_port2), file:${SURELOG_DIR}/tests/ModPortRange/dut.sv, line:39:1, endln:46:10 + \_module_inst: work@range_itf_port2 (work@range_itf_port2), file:${SURELOG_DIR}/tests/ModPortRange/dut.sv, line:39:1, endln:46:10 |vpiName:my_port1 |vpiDirection:3 |vpiLowConn: @@ -481,7 +481,7 @@ design: (work@range_itf_port) |vpiPort: \_port: (my_port2), line:41:27, endln:41:35 |vpiParent: - \_module: work@range_itf_port2 (work@range_itf_port2), file:${SURELOG_DIR}/tests/ModPortRange/dut.sv, line:39:1, endln:46:10 + \_module_inst: work@range_itf_port2 (work@range_itf_port2), file:${SURELOG_DIR}/tests/ModPortRange/dut.sv, line:39:1, endln:46:10 |vpiName:my_port2 |vpiDirection:3 |vpiLowConn: @@ -520,26 +520,26 @@ design: (work@range_itf_port) |vpiPort: \_port: (my_port3), line:42:18, endln:42:26 |vpiParent: - \_module: work@range_itf_port2 (work@range_itf_port2), file:${SURELOG_DIR}/tests/ModPortRange/dut.sv, line:39:1, endln:46:10 + \_module_inst: work@range_itf_port2 (work@range_itf_port2), file:${SURELOG_DIR}/tests/ModPortRange/dut.sv, line:39:1, endln:46:10 |vpiName:my_port3 |vpiDirection:3 |vpiLowConn: \_ref_obj: |vpiActual: - \_interface: work@MyInterface (work@MyInterface), file:${SURELOG_DIR}/tests/ModPortRange/dut.sv, line:1:1, endln:7:13 + \_interface_inst: work@MyInterface (work@MyInterface), file:${SURELOG_DIR}/tests/ModPortRange/dut.sv, line:1:1, endln:7:13 |vpiTypedef: \_interface_typespec: (MyInterface), line:42:5, endln:42:16 |vpiName:MyInterface |vpiPort: \_port: (my_port4), line:43:18, endln:43:26 |vpiParent: - \_module: work@range_itf_port2 (work@range_itf_port2), file:${SURELOG_DIR}/tests/ModPortRange/dut.sv, line:39:1, endln:46:10 + \_module_inst: work@range_itf_port2 (work@range_itf_port2), file:${SURELOG_DIR}/tests/ModPortRange/dut.sv, line:39:1, endln:46:10 |vpiName:my_port4 |vpiDirection:3 |vpiLowConn: \_ref_obj: |vpiActual: - \_interface: work@MyInterface (work@MyInterface), file:${SURELOG_DIR}/tests/ModPortRange/dut.sv, line:1:1, endln:7:13 + \_interface_inst: work@MyInterface (work@MyInterface), file:${SURELOG_DIR}/tests/ModPortRange/dut.sv, line:1:1, endln:7:13 |vpiTypedef: \_array_typespec: , line:43:5, endln:43:31 |vpiParent: @@ -569,7 +569,7 @@ design: (work@range_itf_port) |vpiInterfaceArray: \_interface_array: (MyInterface.MyModPort), line:41:27, endln:41:35 |vpiParent: - \_module: work@range_itf_port2 (work@range_itf_port2), file:${SURELOG_DIR}/tests/ModPortRange/dut.sv, line:39:1, endln:46:10 + \_module_inst: work@range_itf_port2 (work@range_itf_port2), file:${SURELOG_DIR}/tests/ModPortRange/dut.sv, line:39:1, endln:46:10 |vpiName:my_port2 |vpiFullName:MyInterface.MyModPort |vpiRange: @@ -596,7 +596,7 @@ design: (work@range_itf_port) |vpiInterfaceArray: \_interface_array: (MyInterface), line:43:18, endln:43:26 |vpiParent: - \_module: work@range_itf_port2 (work@range_itf_port2), file:${SURELOG_DIR}/tests/ModPortRange/dut.sv, line:39:1, endln:46:10 + \_module_inst: work@range_itf_port2 (work@range_itf_port2), file:${SURELOG_DIR}/tests/ModPortRange/dut.sv, line:39:1, endln:46:10 |vpiName:my_port4 |vpiFullName:MyInterface |vpiRange: @@ -621,14 +621,14 @@ design: (work@range_itf_port) \_interface_typespec: (MyInterface), line:43:5, endln:43:16 |vpiName:MyInterface |uhdmtopModules: -\_module: work@range_itf_port (work@range_itf_port), file:${SURELOG_DIR}/tests/ModPortRange/dut.sv, line:9:1, endln:13:10 +\_module_inst: work@range_itf_port (work@range_itf_port), file:${SURELOG_DIR}/tests/ModPortRange/dut.sv, line:9:1, endln:13:10 |vpiName:work@range_itf_port |vpiDefName:work@range_itf_port |vpiTop:1 |vpiArrayNet: \_array_net: (work@range_itf_port.my_port2), line:11:17, endln:11:25 |vpiParent: - \_module: work@range_itf_port (work@range_itf_port), file:${SURELOG_DIR}/tests/ModPortRange/dut.sv, line:9:1, endln:13:10 + \_module_inst: work@range_itf_port (work@range_itf_port), file:${SURELOG_DIR}/tests/ModPortRange/dut.sv, line:9:1, endln:13:10 |vpiSize:2 |vpiName:my_port2 |vpiFullName:work@range_itf_port.my_port2 @@ -662,7 +662,7 @@ design: (work@range_itf_port) |vpiPort: \_port: (my_port1), line:10:27, endln:10:35 |vpiParent: - \_module: work@range_itf_port (work@range_itf_port), file:${SURELOG_DIR}/tests/ModPortRange/dut.sv, line:9:1, endln:13:10 + \_module_inst: work@range_itf_port (work@range_itf_port), file:${SURELOG_DIR}/tests/ModPortRange/dut.sv, line:9:1, endln:13:10 |vpiName:my_port1 |vpiDirection:3 |vpiLowConn: @@ -679,11 +679,11 @@ design: (work@range_itf_port) |vpiName:MyModPort |vpiIsModPort:1 |vpiInstance: - \_module: work@range_itf_port (work@range_itf_port), file:${SURELOG_DIR}/tests/ModPortRange/dut.sv, line:9:1, endln:13:10 + \_module_inst: work@range_itf_port (work@range_itf_port), file:${SURELOG_DIR}/tests/ModPortRange/dut.sv, line:9:1, endln:13:10 |vpiPort: \_port: (my_port2), line:11:17, endln:11:25 |vpiParent: - \_module: work@range_itf_port (work@range_itf_port), file:${SURELOG_DIR}/tests/ModPortRange/dut.sv, line:9:1, endln:13:10 + \_module_inst: work@range_itf_port (work@range_itf_port), file:${SURELOG_DIR}/tests/ModPortRange/dut.sv, line:9:1, endln:13:10 |vpiName:my_port2 |vpiDirection:1 |vpiLowConn: @@ -697,18 +697,18 @@ design: (work@range_itf_port) |vpiTypedef: \_logic_typespec: , line:11:11, endln:11:16 |vpiInstance: - \_module: work@range_itf_port (work@range_itf_port), file:${SURELOG_DIR}/tests/ModPortRange/dut.sv, line:9:1, endln:13:10 - |vpiInterface: - \_interface: work@MyInterface (work@range_itf_port.my_port1[0]), file:${SURELOG_DIR}/tests/ModPortRange/dut.sv, line:9:0 + \_module_inst: work@range_itf_port (work@range_itf_port), file:${SURELOG_DIR}/tests/ModPortRange/dut.sv, line:9:1, endln:13:10 + |vpiInterfaceInst: + \_interface_inst: work@MyInterface (work@range_itf_port.my_port1[0]), file:${SURELOG_DIR}/tests/ModPortRange/dut.sv, line:9:0 |vpiParent: - \_module: work@range_itf_port (work@range_itf_port), file:${SURELOG_DIR}/tests/ModPortRange/dut.sv, line:9:1, endln:13:10 + \_module_inst: work@range_itf_port (work@range_itf_port), file:${SURELOG_DIR}/tests/ModPortRange/dut.sv, line:9:1, endln:13:10 |vpiName:my_port1[0] |vpiFullName:work@range_itf_port.my_port1[0] |vpiDefName:work@MyInterface |vpiModport: \_modport: (MyModPort), line:3:12, endln:3:21 |vpiParent: - \_interface: work@MyInterface (work@range_itf_port.my_port1[0]), file:${SURELOG_DIR}/tests/ModPortRange/dut.sv, line:9:0 + \_interface_inst: work@MyInterface (work@range_itf_port.my_port1[0]), file:${SURELOG_DIR}/tests/ModPortRange/dut.sv, line:9:0 |vpiName:MyModPort |vpiIODecl: \_io_decl: (my_logic), line:5:19, endln:5:27 @@ -720,19 +720,19 @@ design: (work@range_itf_port) \_logic_typespec: , line:2:4, endln:2:9 |vpiName:my_logic |vpiVisibility:1 - |vpiInterface: - \_interface: work@MyInterface (work@range_itf_port.my_port1[0]), file:${SURELOG_DIR}/tests/ModPortRange/dut.sv, line:9:0 - |vpiInterface: - \_interface: work@MyInterface (work@range_itf_port.my_port1[1]), file:${SURELOG_DIR}/tests/ModPortRange/dut.sv, line:9:0 + |vpiInterfaceInst: + \_interface_inst: work@MyInterface (work@range_itf_port.my_port1[0]), file:${SURELOG_DIR}/tests/ModPortRange/dut.sv, line:9:0 + |vpiInterfaceInst: + \_interface_inst: work@MyInterface (work@range_itf_port.my_port1[1]), file:${SURELOG_DIR}/tests/ModPortRange/dut.sv, line:9:0 |vpiParent: - \_module: work@range_itf_port (work@range_itf_port), file:${SURELOG_DIR}/tests/ModPortRange/dut.sv, line:9:1, endln:13:10 + \_module_inst: work@range_itf_port (work@range_itf_port), file:${SURELOG_DIR}/tests/ModPortRange/dut.sv, line:9:1, endln:13:10 |vpiName:my_port1[1] |vpiFullName:work@range_itf_port.my_port1[1] |vpiDefName:work@MyInterface |vpiModport: \_modport: (MyModPort), line:3:12, endln:3:21 |vpiParent: - \_interface: work@MyInterface (work@range_itf_port.my_port1[1]), file:${SURELOG_DIR}/tests/ModPortRange/dut.sv, line:9:0 + \_interface_inst: work@MyInterface (work@range_itf_port.my_port1[1]), file:${SURELOG_DIR}/tests/ModPortRange/dut.sv, line:9:0 |vpiName:MyModPort |vpiIODecl: \_io_decl: (my_logic), line:5:19, endln:5:27 @@ -744,12 +744,12 @@ design: (work@range_itf_port) \_logic_typespec: , line:2:4, endln:2:9 |vpiName:my_logic |vpiVisibility:1 - |vpiInterface: - \_interface: work@MyInterface (work@range_itf_port.my_port1[1]), file:${SURELOG_DIR}/tests/ModPortRange/dut.sv, line:9:0 + |vpiInterfaceInst: + \_interface_inst: work@MyInterface (work@range_itf_port.my_port1[1]), file:${SURELOG_DIR}/tests/ModPortRange/dut.sv, line:9:0 |vpiInterfaceArray: \_interface_array: (work@range_itf_port.my_port1), line:10:27, endln:10:35 |vpiParent: - \_module: work@range_itf_port (work@range_itf_port), file:${SURELOG_DIR}/tests/ModPortRange/dut.sv, line:9:1, endln:13:10 + \_module_inst: work@range_itf_port (work@range_itf_port), file:${SURELOG_DIR}/tests/ModPortRange/dut.sv, line:9:1, endln:13:10 |vpiName:my_port1 |vpiFullName:work@range_itf_port.my_port1 |vpiSize:2 @@ -772,11 +772,11 @@ design: (work@range_itf_port) |UINT:0 |vpiConstType:9 |vpiInstance: - \_interface: work@MyInterface (work@range_itf_port.my_port1[0]), file:${SURELOG_DIR}/tests/ModPortRange/dut.sv, line:9:0 + \_interface_inst: work@MyInterface (work@range_itf_port.my_port1[0]), file:${SURELOG_DIR}/tests/ModPortRange/dut.sv, line:9:0 |vpiInstance: - \_interface: work@MyInterface (work@range_itf_port.my_port1[1]), file:${SURELOG_DIR}/tests/ModPortRange/dut.sv, line:9:0 + \_interface_inst: work@MyInterface (work@range_itf_port.my_port1[1]), file:${SURELOG_DIR}/tests/ModPortRange/dut.sv, line:9:0 |uhdmtopModules: -\_module: work@memory_ctrl1 (work@memory_ctrl1), file:${SURELOG_DIR}/tests/ModPortRange/dut.sv, line:25:1, endln:28:10 +\_module_inst: work@memory_ctrl1 (work@memory_ctrl1), file:${SURELOG_DIR}/tests/ModPortRange/dut.sv, line:25:1, endln:28:10 |vpiName:work@memory_ctrl1 |vpiDefName:work@memory_ctrl1 |vpiTop:1 @@ -784,7 +784,7 @@ design: (work@range_itf_port) |vpiPort: \_port: (sif1), line:25:29, endln:25:33 |vpiParent: - \_module: work@memory_ctrl1 (work@memory_ctrl1), file:${SURELOG_DIR}/tests/ModPortRange/dut.sv, line:25:1, endln:28:10 + \_module_inst: work@memory_ctrl1 (work@memory_ctrl1), file:${SURELOG_DIR}/tests/ModPortRange/dut.sv, line:25:1, endln:28:10 |vpiName:sif1 |vpiDirection:3 |vpiLowConn: @@ -793,16 +793,16 @@ design: (work@range_itf_port) \_port: (sif1), line:25:29, endln:25:33 |vpiFullName:work@memory_ctrl1.sif1 |vpiActual: - \_interface: work@mem_if (work@memory_ctrl1.sif1), file:${SURELOG_DIR}/tests/ModPortRange/dut.sv, line:25:0 + \_interface_inst: work@mem_if (work@memory_ctrl1.sif1), file:${SURELOG_DIR}/tests/ModPortRange/dut.sv, line:25:0 |vpiTypedef: \_interface_typespec: (mem_if), line:25:22, endln:25:28 |vpiName:mem_if |vpiInstance: - \_module: work@memory_ctrl1 (work@memory_ctrl1), file:${SURELOG_DIR}/tests/ModPortRange/dut.sv, line:25:1, endln:28:10 + \_module_inst: work@memory_ctrl1 (work@memory_ctrl1), file:${SURELOG_DIR}/tests/ModPortRange/dut.sv, line:25:1, endln:28:10 |vpiPort: \_port: (sif2), line:25:49, endln:25:53 |vpiParent: - \_module: work@memory_ctrl1 (work@memory_ctrl1), file:${SURELOG_DIR}/tests/ModPortRange/dut.sv, line:25:1, endln:28:10 + \_module_inst: work@memory_ctrl1 (work@memory_ctrl1), file:${SURELOG_DIR}/tests/ModPortRange/dut.sv, line:25:1, endln:28:10 |vpiName:sif2 |vpiDirection:3 |vpiLowConn: @@ -819,18 +819,18 @@ design: (work@range_itf_port) |vpiName:system |vpiIsModPort:1 |vpiInstance: - \_module: work@memory_ctrl1 (work@memory_ctrl1), file:${SURELOG_DIR}/tests/ModPortRange/dut.sv, line:25:1, endln:28:10 - |vpiInterface: - \_interface: work@mem_if (work@memory_ctrl1.sif1), file:${SURELOG_DIR}/tests/ModPortRange/dut.sv, line:25:0 + \_module_inst: work@memory_ctrl1 (work@memory_ctrl1), file:${SURELOG_DIR}/tests/ModPortRange/dut.sv, line:25:1, endln:28:10 + |vpiInterfaceInst: + \_interface_inst: work@mem_if (work@memory_ctrl1.sif1), file:${SURELOG_DIR}/tests/ModPortRange/dut.sv, line:25:0 |vpiParent: - \_module: work@memory_ctrl1 (work@memory_ctrl1), file:${SURELOG_DIR}/tests/ModPortRange/dut.sv, line:25:1, endln:28:10 + \_module_inst: work@memory_ctrl1 (work@memory_ctrl1), file:${SURELOG_DIR}/tests/ModPortRange/dut.sv, line:25:1, endln:28:10 |vpiName:sif1 |vpiFullName:work@memory_ctrl1.sif1 |vpiDefName:work@mem_if |vpiModport: \_modport: (memory), line:20:12, endln:20:18 |vpiParent: - \_interface: work@mem_if (work@memory_ctrl1.sif1), file:${SURELOG_DIR}/tests/ModPortRange/dut.sv, line:25:0 + \_interface_inst: work@mem_if (work@memory_ctrl1.sif1), file:${SURELOG_DIR}/tests/ModPortRange/dut.sv, line:25:0 |vpiName:memory |vpiIODecl: \_io_decl: (clk), line:20:27, endln:20:30 @@ -842,12 +842,12 @@ design: (work@range_itf_port) \_logic_typespec: , line:17:25, endln:17:29 |vpiName:clk |vpiNetType:1 - |vpiInterface: - \_interface: work@mem_if (work@memory_ctrl1.sif1), file:${SURELOG_DIR}/tests/ModPortRange/dut.sv, line:25:0 + |vpiInterfaceInst: + \_interface_inst: work@mem_if (work@memory_ctrl1.sif1), file:${SURELOG_DIR}/tests/ModPortRange/dut.sv, line:25:0 |vpiModport: \_modport: (system), line:19:12, endln:19:18 |vpiParent: - \_interface: work@mem_if (work@memory_ctrl1.sif1), file:${SURELOG_DIR}/tests/ModPortRange/dut.sv, line:25:0 + \_interface_inst: work@mem_if (work@memory_ctrl1.sif1), file:${SURELOG_DIR}/tests/ModPortRange/dut.sv, line:25:0 |vpiName:system |vpiIODecl: \_io_decl: (clk), line:19:26, endln:19:29 @@ -855,21 +855,21 @@ design: (work@range_itf_port) |vpiName:clk |vpiExpr: \_logic_net: (clk), line:17:30, endln:17:33 - |vpiInterface: - \_interface: work@mem_if (work@memory_ctrl1.sif1), file:${SURELOG_DIR}/tests/ModPortRange/dut.sv, line:25:0 - |vpiInterface: - \_interface: work@mem_if (work@memory_ctrl1.sif1), file:${SURELOG_DIR}/tests/ModPortRange/dut.sv, line:25:0 - |vpiInterface: - \_interface: work@mem_if (work@memory_ctrl1.sif2), file:${SURELOG_DIR}/tests/ModPortRange/dut.sv, line:25:0 + |vpiInterfaceInst: + \_interface_inst: work@mem_if (work@memory_ctrl1.sif1), file:${SURELOG_DIR}/tests/ModPortRange/dut.sv, line:25:0 + |vpiInterfaceInst: + \_interface_inst: work@mem_if (work@memory_ctrl1.sif1), file:${SURELOG_DIR}/tests/ModPortRange/dut.sv, line:25:0 + |vpiInterfaceInst: + \_interface_inst: work@mem_if (work@memory_ctrl1.sif2), file:${SURELOG_DIR}/tests/ModPortRange/dut.sv, line:25:0 |vpiParent: - \_module: work@memory_ctrl1 (work@memory_ctrl1), file:${SURELOG_DIR}/tests/ModPortRange/dut.sv, line:25:1, endln:28:10 + \_module_inst: work@memory_ctrl1 (work@memory_ctrl1), file:${SURELOG_DIR}/tests/ModPortRange/dut.sv, line:25:1, endln:28:10 |vpiName:sif2 |vpiFullName:work@memory_ctrl1.sif2 |vpiDefName:work@mem_if |vpiModport: \_modport: (system), line:19:12, endln:19:18 |vpiParent: - \_interface: work@mem_if (work@memory_ctrl1.sif2), file:${SURELOG_DIR}/tests/ModPortRange/dut.sv, line:25:0 + \_interface_inst: work@mem_if (work@memory_ctrl1.sif2), file:${SURELOG_DIR}/tests/ModPortRange/dut.sv, line:25:0 |vpiName:system |vpiIODecl: \_io_decl: (clk), line:19:26, endln:19:29 @@ -881,10 +881,10 @@ design: (work@range_itf_port) \_logic_typespec: , line:17:25, endln:17:29 |vpiName:clk |vpiNetType:1 - |vpiInterface: - \_interface: work@mem_if (work@memory_ctrl1.sif2), file:${SURELOG_DIR}/tests/ModPortRange/dut.sv, line:25:0 + |vpiInterfaceInst: + \_interface_inst: work@mem_if (work@memory_ctrl1.sif2), file:${SURELOG_DIR}/tests/ModPortRange/dut.sv, line:25:0 |uhdmtopModules: -\_module: work@middle (work@middle), file:${SURELOG_DIR}/tests/ModPortRange/dut.sv, line:35:1, endln:36:10 +\_module_inst: work@middle (work@middle), file:${SURELOG_DIR}/tests/ModPortRange/dut.sv, line:35:1, endln:36:10 |vpiName:work@middle |vpiDefName:work@middle |vpiTop:1 @@ -892,7 +892,7 @@ design: (work@range_itf_port) |vpiPort: \_port: (conn1), line:35:26, endln:35:31 |vpiParent: - \_module: work@middle (work@middle), file:${SURELOG_DIR}/tests/ModPortRange/dut.sv, line:35:1, endln:36:10 + \_module_inst: work@middle (work@middle), file:${SURELOG_DIR}/tests/ModPortRange/dut.sv, line:35:1, endln:36:10 |vpiName:conn1 |vpiDirection:3 |vpiLowConn: @@ -906,18 +906,18 @@ design: (work@range_itf_port) \_interface_typespec: (ConnectTB), line:35:16, endln:35:25 |vpiName:ConnectTB |vpiInstance: - \_module: work@middle (work@middle), file:${SURELOG_DIR}/tests/ModPortRange/dut.sv, line:35:1, endln:36:10 - |vpiInterface: - \_interface: work@ConnectTB (work@middle.conn1), file:${SURELOG_DIR}/tests/ModPortRange/dut.sv, line:35:0 + \_module_inst: work@middle (work@middle), file:${SURELOG_DIR}/tests/ModPortRange/dut.sv, line:35:1, endln:36:10 + |vpiInterfaceInst: + \_interface_inst: work@ConnectTB (work@middle.conn1), file:${SURELOG_DIR}/tests/ModPortRange/dut.sv, line:35:0 |vpiParent: - \_module: work@middle (work@middle), file:${SURELOG_DIR}/tests/ModPortRange/dut.sv, line:35:1, endln:36:10 + \_module_inst: work@middle (work@middle), file:${SURELOG_DIR}/tests/ModPortRange/dut.sv, line:35:1, endln:36:10 |vpiName:conn1 |vpiFullName:work@middle.conn1 |vpiDefName:work@ConnectTB |vpiInterfaceArray: \_interface_array: (work@middle.conn1) |vpiParent: - \_module: work@middle (work@middle), file:${SURELOG_DIR}/tests/ModPortRange/dut.sv, line:35:1, endln:36:10 + \_module_inst: work@middle (work@middle), file:${SURELOG_DIR}/tests/ModPortRange/dut.sv, line:35:1, endln:36:10 |vpiName:conn1 |vpiFullName:work@middle.conn1 |vpiSize:2 @@ -940,9 +940,9 @@ design: (work@range_itf_port) |UINT:0 |vpiConstType:9 |vpiInstance: - \_interface: work@ConnectTB (work@middle.conn1), file:${SURELOG_DIR}/tests/ModPortRange/dut.sv, line:35:0 + \_interface_inst: work@ConnectTB (work@middle.conn1), file:${SURELOG_DIR}/tests/ModPortRange/dut.sv, line:35:0 |uhdmtopModules: -\_module: work@range_itf_port2 (work@range_itf_port2), file:${SURELOG_DIR}/tests/ModPortRange/dut.sv, line:39:1, endln:46:10 +\_module_inst: work@range_itf_port2 (work@range_itf_port2), file:${SURELOG_DIR}/tests/ModPortRange/dut.sv, line:39:1, endln:46:10 |vpiName:work@range_itf_port2 |vpiDefName:work@range_itf_port2 |vpiTop:1 @@ -950,7 +950,7 @@ design: (work@range_itf_port) |vpiPort: \_port: (my_port1), line:40:27, endln:40:35 |vpiParent: - \_module: work@range_itf_port2 (work@range_itf_port2), file:${SURELOG_DIR}/tests/ModPortRange/dut.sv, line:39:1, endln:46:10 + \_module_inst: work@range_itf_port2 (work@range_itf_port2), file:${SURELOG_DIR}/tests/ModPortRange/dut.sv, line:39:1, endln:46:10 |vpiName:my_port1 |vpiDirection:3 |vpiLowConn: @@ -967,11 +967,11 @@ design: (work@range_itf_port) |vpiName:MyModPort |vpiIsModPort:1 |vpiInstance: - \_module: work@range_itf_port2 (work@range_itf_port2), file:${SURELOG_DIR}/tests/ModPortRange/dut.sv, line:39:1, endln:46:10 + \_module_inst: work@range_itf_port2 (work@range_itf_port2), file:${SURELOG_DIR}/tests/ModPortRange/dut.sv, line:39:1, endln:46:10 |vpiPort: \_port: (my_port2), line:41:27, endln:41:35 |vpiParent: - \_module: work@range_itf_port2 (work@range_itf_port2), file:${SURELOG_DIR}/tests/ModPortRange/dut.sv, line:39:1, endln:46:10 + \_module_inst: work@range_itf_port2 (work@range_itf_port2), file:${SURELOG_DIR}/tests/ModPortRange/dut.sv, line:39:1, endln:46:10 |vpiName:my_port2 |vpiDirection:3 |vpiLowConn: @@ -988,11 +988,11 @@ design: (work@range_itf_port) |vpiName:MyModPort |vpiIsModPort:1 |vpiInstance: - \_module: work@range_itf_port2 (work@range_itf_port2), file:${SURELOG_DIR}/tests/ModPortRange/dut.sv, line:39:1, endln:46:10 + \_module_inst: work@range_itf_port2 (work@range_itf_port2), file:${SURELOG_DIR}/tests/ModPortRange/dut.sv, line:39:1, endln:46:10 |vpiPort: \_port: (my_port3), line:42:18, endln:42:26 |vpiParent: - \_module: work@range_itf_port2 (work@range_itf_port2), file:${SURELOG_DIR}/tests/ModPortRange/dut.sv, line:39:1, endln:46:10 + \_module_inst: work@range_itf_port2 (work@range_itf_port2), file:${SURELOG_DIR}/tests/ModPortRange/dut.sv, line:39:1, endln:46:10 |vpiName:my_port3 |vpiDirection:3 |vpiLowConn: @@ -1001,16 +1001,16 @@ design: (work@range_itf_port) \_port: (my_port3), line:42:18, endln:42:26 |vpiFullName:work@range_itf_port2.my_port3 |vpiActual: - \_interface: work@MyInterface (work@range_itf_port2.my_port3), file:${SURELOG_DIR}/tests/ModPortRange/dut.sv, line:39:0 + \_interface_inst: work@MyInterface (work@range_itf_port2.my_port3), file:${SURELOG_DIR}/tests/ModPortRange/dut.sv, line:39:0 |vpiTypedef: \_interface_typespec: (MyInterface), line:42:5, endln:42:16 |vpiName:MyInterface |vpiInstance: - \_module: work@range_itf_port2 (work@range_itf_port2), file:${SURELOG_DIR}/tests/ModPortRange/dut.sv, line:39:1, endln:46:10 + \_module_inst: work@range_itf_port2 (work@range_itf_port2), file:${SURELOG_DIR}/tests/ModPortRange/dut.sv, line:39:1, endln:46:10 |vpiPort: \_port: (my_port4), line:43:18, endln:43:26 |vpiParent: - \_module: work@range_itf_port2 (work@range_itf_port2), file:${SURELOG_DIR}/tests/ModPortRange/dut.sv, line:39:1, endln:46:10 + \_module_inst: work@range_itf_port2 (work@range_itf_port2), file:${SURELOG_DIR}/tests/ModPortRange/dut.sv, line:39:1, endln:46:10 |vpiName:my_port4 |vpiDirection:3 |vpiLowConn: @@ -1024,18 +1024,18 @@ design: (work@range_itf_port) \_interface_typespec: (MyInterface), line:43:5, endln:43:16 |vpiName:MyInterface |vpiInstance: - \_module: work@range_itf_port2 (work@range_itf_port2), file:${SURELOG_DIR}/tests/ModPortRange/dut.sv, line:39:1, endln:46:10 - |vpiInterface: - \_interface: work@MyInterface (work@range_itf_port2.my_port1), file:${SURELOG_DIR}/tests/ModPortRange/dut.sv, line:39:0 + \_module_inst: work@range_itf_port2 (work@range_itf_port2), file:${SURELOG_DIR}/tests/ModPortRange/dut.sv, line:39:1, endln:46:10 + |vpiInterfaceInst: + \_interface_inst: work@MyInterface (work@range_itf_port2.my_port1), file:${SURELOG_DIR}/tests/ModPortRange/dut.sv, line:39:0 |vpiParent: - \_module: work@range_itf_port2 (work@range_itf_port2), file:${SURELOG_DIR}/tests/ModPortRange/dut.sv, line:39:1, endln:46:10 + \_module_inst: work@range_itf_port2 (work@range_itf_port2), file:${SURELOG_DIR}/tests/ModPortRange/dut.sv, line:39:1, endln:46:10 |vpiName:my_port1 |vpiFullName:work@range_itf_port2.my_port1 |vpiDefName:work@MyInterface |vpiModport: \_modport: (MyModPort), line:3:12, endln:3:21 |vpiParent: - \_interface: work@MyInterface (work@range_itf_port2.my_port1), file:${SURELOG_DIR}/tests/ModPortRange/dut.sv, line:39:0 + \_interface_inst: work@MyInterface (work@range_itf_port2.my_port1), file:${SURELOG_DIR}/tests/ModPortRange/dut.sv, line:39:0 |vpiName:MyModPort |vpiIODecl: \_io_decl: (my_logic), line:5:19, endln:5:27 @@ -1047,19 +1047,19 @@ design: (work@range_itf_port) \_logic_typespec: , line:2:4, endln:2:9 |vpiName:my_logic |vpiVisibility:1 - |vpiInterface: - \_interface: work@MyInterface (work@range_itf_port2.my_port1), file:${SURELOG_DIR}/tests/ModPortRange/dut.sv, line:39:0 - |vpiInterface: - \_interface: work@MyInterface (work@range_itf_port2.my_port2[0]), file:${SURELOG_DIR}/tests/ModPortRange/dut.sv, line:39:0 + |vpiInterfaceInst: + \_interface_inst: work@MyInterface (work@range_itf_port2.my_port1), file:${SURELOG_DIR}/tests/ModPortRange/dut.sv, line:39:0 + |vpiInterfaceInst: + \_interface_inst: work@MyInterface (work@range_itf_port2.my_port2[0]), file:${SURELOG_DIR}/tests/ModPortRange/dut.sv, line:39:0 |vpiParent: - \_module: work@range_itf_port2 (work@range_itf_port2), file:${SURELOG_DIR}/tests/ModPortRange/dut.sv, line:39:1, endln:46:10 + \_module_inst: work@range_itf_port2 (work@range_itf_port2), file:${SURELOG_DIR}/tests/ModPortRange/dut.sv, line:39:1, endln:46:10 |vpiName:my_port2[0] |vpiFullName:work@range_itf_port2.my_port2[0] |vpiDefName:work@MyInterface |vpiModport: \_modport: (MyModPort), line:3:12, endln:3:21 |vpiParent: - \_interface: work@MyInterface (work@range_itf_port2.my_port2[0]), file:${SURELOG_DIR}/tests/ModPortRange/dut.sv, line:39:0 + \_interface_inst: work@MyInterface (work@range_itf_port2.my_port2[0]), file:${SURELOG_DIR}/tests/ModPortRange/dut.sv, line:39:0 |vpiName:MyModPort |vpiIODecl: \_io_decl: (my_logic), line:5:19, endln:5:27 @@ -1071,19 +1071,19 @@ design: (work@range_itf_port) \_logic_typespec: , line:2:4, endln:2:9 |vpiName:my_logic |vpiVisibility:1 - |vpiInterface: - \_interface: work@MyInterface (work@range_itf_port2.my_port2[0]), file:${SURELOG_DIR}/tests/ModPortRange/dut.sv, line:39:0 - |vpiInterface: - \_interface: work@MyInterface (work@range_itf_port2.my_port2[1]), file:${SURELOG_DIR}/tests/ModPortRange/dut.sv, line:39:0 + |vpiInterfaceInst: + \_interface_inst: work@MyInterface (work@range_itf_port2.my_port2[0]), file:${SURELOG_DIR}/tests/ModPortRange/dut.sv, line:39:0 + |vpiInterfaceInst: + \_interface_inst: work@MyInterface (work@range_itf_port2.my_port2[1]), file:${SURELOG_DIR}/tests/ModPortRange/dut.sv, line:39:0 |vpiParent: - \_module: work@range_itf_port2 (work@range_itf_port2), file:${SURELOG_DIR}/tests/ModPortRange/dut.sv, line:39:1, endln:46:10 + \_module_inst: work@range_itf_port2 (work@range_itf_port2), file:${SURELOG_DIR}/tests/ModPortRange/dut.sv, line:39:1, endln:46:10 |vpiName:my_port2[1] |vpiFullName:work@range_itf_port2.my_port2[1] |vpiDefName:work@MyInterface |vpiModport: \_modport: (MyModPort), line:3:12, endln:3:21 |vpiParent: - \_interface: work@MyInterface (work@range_itf_port2.my_port2[1]), file:${SURELOG_DIR}/tests/ModPortRange/dut.sv, line:39:0 + \_interface_inst: work@MyInterface (work@range_itf_port2.my_port2[1]), file:${SURELOG_DIR}/tests/ModPortRange/dut.sv, line:39:0 |vpiName:MyModPort |vpiIODecl: \_io_decl: (my_logic), line:5:19, endln:5:27 @@ -1095,19 +1095,19 @@ design: (work@range_itf_port) \_logic_typespec: , line:2:4, endln:2:9 |vpiName:my_logic |vpiVisibility:1 - |vpiInterface: - \_interface: work@MyInterface (work@range_itf_port2.my_port2[1]), file:${SURELOG_DIR}/tests/ModPortRange/dut.sv, line:39:0 - |vpiInterface: - \_interface: work@MyInterface (work@range_itf_port2.my_port3), file:${SURELOG_DIR}/tests/ModPortRange/dut.sv, line:39:0 + |vpiInterfaceInst: + \_interface_inst: work@MyInterface (work@range_itf_port2.my_port2[1]), file:${SURELOG_DIR}/tests/ModPortRange/dut.sv, line:39:0 + |vpiInterfaceInst: + \_interface_inst: work@MyInterface (work@range_itf_port2.my_port3), file:${SURELOG_DIR}/tests/ModPortRange/dut.sv, line:39:0 |vpiParent: - \_module: work@range_itf_port2 (work@range_itf_port2), file:${SURELOG_DIR}/tests/ModPortRange/dut.sv, line:39:1, endln:46:10 + \_module_inst: work@range_itf_port2 (work@range_itf_port2), file:${SURELOG_DIR}/tests/ModPortRange/dut.sv, line:39:1, endln:46:10 |vpiName:my_port3 |vpiFullName:work@range_itf_port2.my_port3 |vpiDefName:work@MyInterface |vpiModport: \_modport: (MyModPort), line:3:12, endln:3:21 |vpiParent: - \_interface: work@MyInterface (work@range_itf_port2.my_port3), file:${SURELOG_DIR}/tests/ModPortRange/dut.sv, line:39:0 + \_interface_inst: work@MyInterface (work@range_itf_port2.my_port3), file:${SURELOG_DIR}/tests/ModPortRange/dut.sv, line:39:0 |vpiName:MyModPort |vpiIODecl: \_io_decl: (my_logic), line:5:19, endln:5:27 @@ -1119,21 +1119,21 @@ design: (work@range_itf_port) \_logic_typespec: , line:2:4, endln:2:9 |vpiName:my_logic |vpiVisibility:1 - |vpiInterface: - \_interface: work@MyInterface (work@range_itf_port2.my_port3), file:${SURELOG_DIR}/tests/ModPortRange/dut.sv, line:39:0 - |vpiInterface: - \_interface: work@MyInterface (work@range_itf_port2.my_port3), file:${SURELOG_DIR}/tests/ModPortRange/dut.sv, line:39:0 - |vpiInterface: - \_interface: work@MyInterface (work@range_itf_port2.my_port4), file:${SURELOG_DIR}/tests/ModPortRange/dut.sv, line:39:0 + |vpiInterfaceInst: + \_interface_inst: work@MyInterface (work@range_itf_port2.my_port3), file:${SURELOG_DIR}/tests/ModPortRange/dut.sv, line:39:0 + |vpiInterfaceInst: + \_interface_inst: work@MyInterface (work@range_itf_port2.my_port3), file:${SURELOG_DIR}/tests/ModPortRange/dut.sv, line:39:0 + |vpiInterfaceInst: + \_interface_inst: work@MyInterface (work@range_itf_port2.my_port4), file:${SURELOG_DIR}/tests/ModPortRange/dut.sv, line:39:0 |vpiParent: - \_module: work@range_itf_port2 (work@range_itf_port2), file:${SURELOG_DIR}/tests/ModPortRange/dut.sv, line:39:1, endln:46:10 + \_module_inst: work@range_itf_port2 (work@range_itf_port2), file:${SURELOG_DIR}/tests/ModPortRange/dut.sv, line:39:1, endln:46:10 |vpiName:my_port4 |vpiFullName:work@range_itf_port2.my_port4 |vpiDefName:work@MyInterface |vpiModport: \_modport: (MyModPort), line:3:12, endln:3:21 |vpiParent: - \_interface: work@MyInterface (work@range_itf_port2.my_port4), file:${SURELOG_DIR}/tests/ModPortRange/dut.sv, line:39:0 + \_interface_inst: work@MyInterface (work@range_itf_port2.my_port4), file:${SURELOG_DIR}/tests/ModPortRange/dut.sv, line:39:0 |vpiName:MyModPort |vpiIODecl: \_io_decl: (my_logic), line:5:19, endln:5:27 @@ -1145,12 +1145,12 @@ design: (work@range_itf_port) \_logic_typespec: , line:2:4, endln:2:9 |vpiName:my_logic |vpiVisibility:1 - |vpiInterface: - \_interface: work@MyInterface (work@range_itf_port2.my_port4), file:${SURELOG_DIR}/tests/ModPortRange/dut.sv, line:39:0 + |vpiInterfaceInst: + \_interface_inst: work@MyInterface (work@range_itf_port2.my_port4), file:${SURELOG_DIR}/tests/ModPortRange/dut.sv, line:39:0 |vpiInterfaceArray: \_interface_array: (work@range_itf_port2.my_port2), line:41:27, endln:41:35 |vpiParent: - \_module: work@range_itf_port2 (work@range_itf_port2), file:${SURELOG_DIR}/tests/ModPortRange/dut.sv, line:39:1, endln:46:10 + \_module_inst: work@range_itf_port2 (work@range_itf_port2), file:${SURELOG_DIR}/tests/ModPortRange/dut.sv, line:39:1, endln:46:10 |vpiName:my_port2 |vpiFullName:work@range_itf_port2.my_port2 |vpiSize:2 @@ -1173,13 +1173,13 @@ design: (work@range_itf_port) |UINT:0 |vpiConstType:9 |vpiInstance: - \_interface: work@MyInterface (work@range_itf_port2.my_port2[0]), file:${SURELOG_DIR}/tests/ModPortRange/dut.sv, line:39:0 + \_interface_inst: work@MyInterface (work@range_itf_port2.my_port2[0]), file:${SURELOG_DIR}/tests/ModPortRange/dut.sv, line:39:0 |vpiInstance: - \_interface: work@MyInterface (work@range_itf_port2.my_port2[1]), file:${SURELOG_DIR}/tests/ModPortRange/dut.sv, line:39:0 + \_interface_inst: work@MyInterface (work@range_itf_port2.my_port2[1]), file:${SURELOG_DIR}/tests/ModPortRange/dut.sv, line:39:0 |vpiInterfaceArray: \_interface_array: (work@range_itf_port2.my_port4) |vpiParent: - \_module: work@range_itf_port2 (work@range_itf_port2), file:${SURELOG_DIR}/tests/ModPortRange/dut.sv, line:39:1, endln:46:10 + \_module_inst: work@range_itf_port2 (work@range_itf_port2), file:${SURELOG_DIR}/tests/ModPortRange/dut.sv, line:39:1, endln:46:10 |vpiName:my_port4 |vpiFullName:work@range_itf_port2.my_port4 |vpiSize:2 @@ -1202,7 +1202,7 @@ design: (work@range_itf_port) |UINT:0 |vpiConstType:9 |vpiInstance: - \_interface: work@MyInterface (work@range_itf_port2.my_port4), file:${SURELOG_DIR}/tests/ModPortRange/dut.sv, line:39:0 + \_interface_inst: work@MyInterface (work@range_itf_port2.my_port4), file:${SURELOG_DIR}/tests/ModPortRange/dut.sv, line:39:0 =================== [ FATAL] : 0 [ SYNTAX] : 0 diff --git a/tests/ModPortTest/ModPortTest.log b/tests/ModPortTest/ModPortTest.log index 2a6591dfcd..15a8198a30 100644 --- a/tests/ModPortTest/ModPortTest.log +++ b/tests/ModPortTest/ModPortTest.log @@ -332,13 +332,13 @@ design 1 enum_const 8 enum_typespec 2 enum_var 2 -interface 4 +interface_inst 4 interface_typespec 9 io_decl 7 logic_net 13 logic_typespec 8 modport 7 -module 7 +module_inst 7 operation 4 packed_array_typespec 1 param_assign 1 @@ -360,20 +360,20 @@ unsupported_typespec 1 design: (work@dff0_test) |vpiName:work@dff0_test |uhdmallInterfaces: -\_interface: work@AXI_BUS (work@AXI_BUS), file:${SURELOG_DIR}/tests/ModPortTest/top.v, line:8:1, endln:26:13 +\_interface_inst: work@AXI_BUS (work@AXI_BUS), file:${SURELOG_DIR}/tests/ModPortTest/top.v, line:8:1, endln:26:13 |vpiParent: \_design: (work@dff0_test) |vpiFullName:work@AXI_BUS |vpiParameter: \_parameter: (work@AXI_BUS.AXI_ID_WIDTH), line:9:12, endln:9:24 |vpiParent: - \_interface: work@AXI_BUS (work@AXI_BUS), file:${SURELOG_DIR}/tests/ModPortTest/top.v, line:8:1, endln:26:13 + \_interface_inst: work@AXI_BUS (work@AXI_BUS), file:${SURELOG_DIR}/tests/ModPortTest/top.v, line:8:1, endln:26:13 |vpiName:AXI_ID_WIDTH |vpiFullName:work@AXI_BUS.AXI_ID_WIDTH |vpiParamAssign: \_param_assign: , line:9:12, endln:9:31 |vpiParent: - \_interface: work@AXI_BUS (work@AXI_BUS), file:${SURELOG_DIR}/tests/ModPortTest/top.v, line:8:1, endln:26:13 + \_interface_inst: work@AXI_BUS (work@AXI_BUS), file:${SURELOG_DIR}/tests/ModPortTest/top.v, line:8:1, endln:26:13 |vpiRhs: \_operation: , line:9:29, endln:9:31 |vpiOpType:1 @@ -388,10 +388,10 @@ design: (work@dff0_test) |vpiTypedef: \_logic_typespec: (id_t), line:12:11, endln:12:16 |vpiParent: - \_interface: work@AXI_BUS (work@AXI_BUS), file:${SURELOG_DIR}/tests/ModPortTest/top.v, line:8:1, endln:26:13 + \_interface_inst: work@AXI_BUS (work@AXI_BUS), file:${SURELOG_DIR}/tests/ModPortTest/top.v, line:8:1, endln:26:13 |vpiName:id_t |vpiInstance: - \_interface: work@AXI_BUS (work@AXI_BUS), file:${SURELOG_DIR}/tests/ModPortTest/top.v, line:8:1, endln:26:13 + \_interface_inst: work@AXI_BUS (work@AXI_BUS), file:${SURELOG_DIR}/tests/ModPortTest/top.v, line:8:1, endln:26:13 |vpiRange: \_range: , line:12:17, endln:12:35 |vpiLeftRange: @@ -414,19 +414,19 @@ design: (work@dff0_test) |vpiNet: \_logic_net: (work@AXI_BUS.aw_id), line:14:15, endln:14:20 |vpiParent: - \_interface: work@AXI_BUS (work@AXI_BUS), file:${SURELOG_DIR}/tests/ModPortTest/top.v, line:8:1, endln:26:13 + \_interface_inst: work@AXI_BUS (work@AXI_BUS), file:${SURELOG_DIR}/tests/ModPortTest/top.v, line:8:1, endln:26:13 |vpiName:aw_id |vpiFullName:work@AXI_BUS.aw_id |vpiNet: \_logic_net: (work@AXI_BUS.rw_id), line:20:14, endln:20:19 |vpiParent: - \_interface: work@AXI_BUS (work@AXI_BUS), file:${SURELOG_DIR}/tests/ModPortTest/top.v, line:8:1, endln:26:13 + \_interface_inst: work@AXI_BUS (work@AXI_BUS), file:${SURELOG_DIR}/tests/ModPortTest/top.v, line:8:1, endln:26:13 |vpiName:rw_id |vpiFullName:work@AXI_BUS.rw_id |vpiModport: \_modport: (Master), line:16:11, endln:16:17 |vpiParent: - \_interface: work@AXI_BUS (work@AXI_BUS), file:${SURELOG_DIR}/tests/ModPortTest/top.v, line:8:1, endln:26:13 + \_interface_inst: work@AXI_BUS (work@AXI_BUS), file:${SURELOG_DIR}/tests/ModPortTest/top.v, line:8:1, endln:26:13 |vpiName:Master |vpiIODecl: \_io_decl: (aw_id), line:17:12, endln:17:17 @@ -435,14 +435,14 @@ design: (work@dff0_test) |vpiModport: \_modport: (Slave), line:22:11, endln:22:16 |vpiParent: - \_interface: work@AXI_BUS (work@AXI_BUS), file:${SURELOG_DIR}/tests/ModPortTest/top.v, line:8:1, endln:26:13 + \_interface_inst: work@AXI_BUS (work@AXI_BUS), file:${SURELOG_DIR}/tests/ModPortTest/top.v, line:8:1, endln:26:13 |vpiName:Slave |vpiIODecl: \_io_decl: (ww_id), line:23:12, endln:23:17 |vpiDirection:2 |vpiName:ww_id |uhdmallInterfaces: -\_interface: work@mem_if (work@mem_if), file:${SURELOG_DIR}/tests/ModPortTest/top.v, line:29:1, endln:34:13 +\_interface_inst: work@mem_if (work@mem_if), file:${SURELOG_DIR}/tests/ModPortTest/top.v, line:29:1, endln:34:13 |vpiParent: \_design: (work@dff0_test) |vpiFullName:work@mem_if @@ -450,14 +450,14 @@ design: (work@dff0_test) |vpiNet: \_logic_net: (work@mem_if.clk), line:29:30, endln:29:33 |vpiParent: - \_interface: work@mem_if (work@mem_if), file:${SURELOG_DIR}/tests/ModPortTest/top.v, line:29:1, endln:34:13 + \_interface_inst: work@mem_if (work@mem_if), file:${SURELOG_DIR}/tests/ModPortTest/top.v, line:29:1, endln:34:13 |vpiName:clk |vpiFullName:work@mem_if.clk |vpiNetType:1 |vpiModport: \_modport: (memory), line:32:12, endln:32:18 |vpiParent: - \_interface: work@mem_if (work@mem_if), file:${SURELOG_DIR}/tests/ModPortTest/top.v, line:29:1, endln:34:13 + \_interface_inst: work@mem_if (work@mem_if), file:${SURELOG_DIR}/tests/ModPortTest/top.v, line:29:1, endln:34:13 |vpiName:memory |vpiIODecl: \_io_decl: (clk), line:32:27, endln:32:30 @@ -466,7 +466,7 @@ design: (work@dff0_test) |vpiModport: \_modport: (system), line:31:12, endln:31:18 |vpiParent: - \_interface: work@mem_if (work@mem_if), file:${SURELOG_DIR}/tests/ModPortTest/top.v, line:29:1, endln:34:13 + \_interface_inst: work@mem_if (work@mem_if), file:${SURELOG_DIR}/tests/ModPortTest/top.v, line:29:1, endln:34:13 |vpiName:system |vpiIODecl: \_io_decl: (clk), line:31:26, endln:31:29 @@ -475,7 +475,7 @@ design: (work@dff0_test) |vpiPort: \_port: (clk), line:29:30, endln:29:33 |vpiParent: - \_interface: work@mem_if (work@mem_if), file:${SURELOG_DIR}/tests/ModPortTest/top.v, line:29:1, endln:34:13 + \_interface_inst: work@mem_if (work@mem_if), file:${SURELOG_DIR}/tests/ModPortTest/top.v, line:29:1, endln:34:13 |vpiName:clk |vpiDirection:1 |vpiLowConn: @@ -483,7 +483,7 @@ design: (work@dff0_test) |vpiActual: \_logic_net: (work@mem_if.clk), line:29:30, endln:29:33 |uhdmallModules: -\_module: work@dff0_test (work@dff0_test), file:${SURELOG_DIR}/tests/ModPortTest/top.v, line:1:1, endln:5:10 +\_module_inst: work@dff0_test (work@dff0_test), file:${SURELOG_DIR}/tests/ModPortTest/top.v, line:1:1, endln:5:10 |vpiParent: \_design: (work@dff0_test) |vpiFullName:work@dff0_test @@ -491,14 +491,14 @@ design: (work@dff0_test) |vpiNet: \_logic_net: (work@dff0_test.n1), line:4:7, endln:4:9 |vpiParent: - \_module: work@dff0_test (work@dff0_test), file:${SURELOG_DIR}/tests/ModPortTest/top.v, line:1:1, endln:5:10 + \_module_inst: work@dff0_test (work@dff0_test), file:${SURELOG_DIR}/tests/ModPortTest/top.v, line:1:1, endln:5:10 |vpiName:n1 |vpiFullName:work@dff0_test.n1 |vpiNetType:48 |vpiPort: \_port: (n1), line:1:18, endln:1:20 |vpiParent: - \_module: work@dff0_test (work@dff0_test), file:${SURELOG_DIR}/tests/ModPortTest/top.v, line:1:1, endln:5:10 + \_module_inst: work@dff0_test (work@dff0_test), file:${SURELOG_DIR}/tests/ModPortTest/top.v, line:1:1, endln:5:10 |vpiName:n1 |vpiDirection:2 |vpiLowConn: @@ -508,17 +508,17 @@ design: (work@dff0_test) |vpiTypedef: \_logic_typespec: , line:3:10, endln:3:10 |uhdmallModules: -\_module: work@memory_ctrl1 (work@memory_ctrl1), file:${SURELOG_DIR}/tests/ModPortTest/top.v, line:36:1, endln:43:10 +\_module_inst: work@memory_ctrl1 (work@memory_ctrl1), file:${SURELOG_DIR}/tests/ModPortTest/top.v, line:36:1, endln:43:10 |vpiParent: \_design: (work@dff0_test) |vpiFullName:work@memory_ctrl1 |vpiTypedef: \_enum_typespec: (fsm_t), line:38:1, endln:38:44 |vpiParent: - \_module: work@memory_ctrl1 (work@memory_ctrl1), file:${SURELOG_DIR}/tests/ModPortTest/top.v, line:36:1, endln:43:10 + \_module_inst: work@memory_ctrl1 (work@memory_ctrl1), file:${SURELOG_DIR}/tests/ModPortTest/top.v, line:36:1, endln:43:10 |vpiName:fsm_t |vpiInstance: - \_module: work@memory_ctrl1 (work@memory_ctrl1), file:${SURELOG_DIR}/tests/ModPortTest/top.v, line:36:1, endln:43:10 + \_module_inst: work@memory_ctrl1 (work@memory_ctrl1), file:${SURELOG_DIR}/tests/ModPortTest/top.v, line:36:1, endln:43:10 |vpiEnumConst: \_enum_const: (IDLE), line:38:16, endln:38:20 |vpiName:IDLE @@ -547,40 +547,40 @@ design: (work@dff0_test) |vpiNet: \_logic_net: (work@memory_ctrl1.state), line:40:7, endln:40:12 |vpiParent: - \_module: work@memory_ctrl1 (work@memory_ctrl1), file:${SURELOG_DIR}/tests/ModPortTest/top.v, line:36:1, endln:43:10 + \_module_inst: work@memory_ctrl1 (work@memory_ctrl1), file:${SURELOG_DIR}/tests/ModPortTest/top.v, line:36:1, endln:43:10 |vpiName:state |vpiFullName:work@memory_ctrl1.state |vpiNet: \_logic_net: (work@memory_ctrl1.sif), line:36:37, endln:36:40 |vpiParent: - \_module: work@memory_ctrl1 (work@memory_ctrl1), file:${SURELOG_DIR}/tests/ModPortTest/top.v, line:36:1, endln:43:10 + \_module_inst: work@memory_ctrl1 (work@memory_ctrl1), file:${SURELOG_DIR}/tests/ModPortTest/top.v, line:36:1, endln:43:10 |vpiName:sif |vpiFullName:work@memory_ctrl1.sif |vpiPort: \_port: (sif), line:36:37, endln:36:40 |vpiParent: - \_module: work@memory_ctrl1 (work@memory_ctrl1), file:${SURELOG_DIR}/tests/ModPortTest/top.v, line:36:1, endln:43:10 + \_module_inst: work@memory_ctrl1 (work@memory_ctrl1), file:${SURELOG_DIR}/tests/ModPortTest/top.v, line:36:1, endln:43:10 |vpiName:sif |vpiDirection:3 |vpiLowConn: \_ref_obj: |vpiActual: - \_interface: work@mem_if (work@mem_if), file:${SURELOG_DIR}/tests/ModPortTest/top.v, line:29:1, endln:34:13 + \_interface_inst: work@mem_if (work@mem_if), file:${SURELOG_DIR}/tests/ModPortTest/top.v, line:29:1, endln:34:13 |vpiTypedef: \_interface_typespec: (mem_if), line:36:22, endln:36:28 |vpiName:mem_if |uhdmallModules: -\_module: work@memory_ctrl2 (work@memory_ctrl2), file:${SURELOG_DIR}/tests/ModPortTest/top.v, line:45:1, endln:53:10 +\_module_inst: work@memory_ctrl2 (work@memory_ctrl2), file:${SURELOG_DIR}/tests/ModPortTest/top.v, line:45:1, endln:53:10 |vpiParent: \_design: (work@dff0_test) |vpiFullName:work@memory_ctrl2 |vpiTypedef: \_enum_typespec: (fsm_t), line:47:1, endln:47:44 |vpiParent: - \_module: work@memory_ctrl2 (work@memory_ctrl2), file:${SURELOG_DIR}/tests/ModPortTest/top.v, line:45:1, endln:53:10 + \_module_inst: work@memory_ctrl2 (work@memory_ctrl2), file:${SURELOG_DIR}/tests/ModPortTest/top.v, line:45:1, endln:53:10 |vpiName:fsm_t |vpiInstance: - \_module: work@memory_ctrl2 (work@memory_ctrl2), file:${SURELOG_DIR}/tests/ModPortTest/top.v, line:45:1, endln:53:10 + \_module_inst: work@memory_ctrl2 (work@memory_ctrl2), file:${SURELOG_DIR}/tests/ModPortTest/top.v, line:45:1, endln:53:10 |vpiEnumConst: \_enum_const: (IDLE), line:47:16, endln:47:20 |vpiName:IDLE @@ -609,25 +609,25 @@ design: (work@dff0_test) |vpiNet: \_logic_net: (work@memory_ctrl2.state), line:49:7, endln:49:12 |vpiParent: - \_module: work@memory_ctrl2 (work@memory_ctrl2), file:${SURELOG_DIR}/tests/ModPortTest/top.v, line:45:1, endln:53:10 + \_module_inst: work@memory_ctrl2 (work@memory_ctrl2), file:${SURELOG_DIR}/tests/ModPortTest/top.v, line:45:1, endln:53:10 |vpiName:state |vpiFullName:work@memory_ctrl2.state |vpiNet: \_logic_net: (work@memory_ctrl2.t), line:51:4, endln:51:5 |vpiParent: - \_module: work@memory_ctrl2 (work@memory_ctrl2), file:${SURELOG_DIR}/tests/ModPortTest/top.v, line:45:1, endln:53:10 + \_module_inst: work@memory_ctrl2 (work@memory_ctrl2), file:${SURELOG_DIR}/tests/ModPortTest/top.v, line:45:1, endln:53:10 |vpiName:t |vpiFullName:work@memory_ctrl2.t |vpiNet: \_logic_net: (work@memory_ctrl2.sif), line:45:36, endln:45:39 |vpiParent: - \_module: work@memory_ctrl2 (work@memory_ctrl2), file:${SURELOG_DIR}/tests/ModPortTest/top.v, line:45:1, endln:53:10 + \_module_inst: work@memory_ctrl2 (work@memory_ctrl2), file:${SURELOG_DIR}/tests/ModPortTest/top.v, line:45:1, endln:53:10 |vpiName:sif |vpiFullName:work@memory_ctrl2.sif |vpiPort: \_port: (sif), line:45:36, endln:45:39 |vpiParent: - \_module: work@memory_ctrl2 (work@memory_ctrl2), file:${SURELOG_DIR}/tests/ModPortTest/top.v, line:45:1, endln:53:10 + \_module_inst: work@memory_ctrl2 (work@memory_ctrl2), file:${SURELOG_DIR}/tests/ModPortTest/top.v, line:45:1, endln:53:10 |vpiName:sif |vpiDirection:3 |vpiLowConn: @@ -641,14 +641,14 @@ design: (work@dff0_test) |vpiName:system |vpiIsModPort:1 |uhdmtopModules: -\_module: work@dff0_test (work@dff0_test), file:${SURELOG_DIR}/tests/ModPortTest/top.v, line:1:1, endln:5:10 +\_module_inst: work@dff0_test (work@dff0_test), file:${SURELOG_DIR}/tests/ModPortTest/top.v, line:1:1, endln:5:10 |vpiName:work@dff0_test |vpiDefName:work@dff0_test |vpiTop:1 |vpiNet: \_logic_net: (work@dff0_test.n1), line:4:7, endln:4:17 |vpiParent: - \_module: work@dff0_test (work@dff0_test), file:${SURELOG_DIR}/tests/ModPortTest/top.v, line:1:1, endln:5:10 + \_module_inst: work@dff0_test (work@dff0_test), file:${SURELOG_DIR}/tests/ModPortTest/top.v, line:1:1, endln:5:10 |vpiTypespec: \_logic_typespec: , line:4:3, endln:4:6 |vpiName:n1 @@ -658,7 +658,7 @@ design: (work@dff0_test) |vpiPort: \_port: (n1), line:1:18, endln:1:20 |vpiParent: - \_module: work@dff0_test (work@dff0_test), file:${SURELOG_DIR}/tests/ModPortTest/top.v, line:1:1, endln:5:10 + \_module_inst: work@dff0_test (work@dff0_test), file:${SURELOG_DIR}/tests/ModPortTest/top.v, line:1:1, endln:5:10 |vpiName:n1 |vpiDirection:2 |vpiLowConn: @@ -670,12 +670,12 @@ design: (work@dff0_test) |vpiTypedef: \_logic_typespec: , line:3:10, endln:3:10 |uhdmtopModules: -\_module: work@memory_ctrl1 (work@memory_ctrl1), file:${SURELOG_DIR}/tests/ModPortTest/top.v, line:36:1, endln:43:10 +\_module_inst: work@memory_ctrl1 (work@memory_ctrl1), file:${SURELOG_DIR}/tests/ModPortTest/top.v, line:36:1, endln:43:10 |vpiName:work@memory_ctrl1 |vpiVariables: \_enum_var: (work@memory_ctrl1.state), line:40:7, endln:40:12 |vpiParent: - \_module: work@memory_ctrl1 (work@memory_ctrl1), file:${SURELOG_DIR}/tests/ModPortTest/top.v, line:36:1, endln:43:10 + \_module_inst: work@memory_ctrl1 (work@memory_ctrl1), file:${SURELOG_DIR}/tests/ModPortTest/top.v, line:36:1, endln:43:10 |vpiTypespec: \_enum_typespec: (fsm_t), line:38:1, endln:38:44 |vpiName:state @@ -689,28 +689,28 @@ design: (work@dff0_test) |vpiPort: \_port: (sif), line:36:37, endln:36:40 |vpiParent: - \_module: work@memory_ctrl1 (work@memory_ctrl1), file:${SURELOG_DIR}/tests/ModPortTest/top.v, line:36:1, endln:43:10 + \_module_inst: work@memory_ctrl1 (work@memory_ctrl1), file:${SURELOG_DIR}/tests/ModPortTest/top.v, line:36:1, endln:43:10 |vpiName:sif |vpiDirection:3 |vpiLowConn: \_ref_obj: (work@memory_ctrl1.sif), line:36:37, endln:36:40 |vpiFullName:work@memory_ctrl1.sif |vpiActual: - \_interface: work@mem_if (work@memory_ctrl1.sif), file:${SURELOG_DIR}/tests/ModPortTest/top.v, line:36:0 + \_interface_inst: work@mem_if (work@memory_ctrl1.sif), file:${SURELOG_DIR}/tests/ModPortTest/top.v, line:36:0 |vpiTypedef: \_interface_typespec: (mem_if), line:36:22, endln:36:28 |vpiName:mem_if - |vpiInterface: - \_interface: work@mem_if (work@memory_ctrl1.sif), file:${SURELOG_DIR}/tests/ModPortTest/top.v, line:36:0 + |vpiInterfaceInst: + \_interface_inst: work@mem_if (work@memory_ctrl1.sif), file:${SURELOG_DIR}/tests/ModPortTest/top.v, line:36:0 |vpiParent: - \_module: work@memory_ctrl1 (work@memory_ctrl1), file:${SURELOG_DIR}/tests/ModPortTest/top.v, line:36:1, endln:43:10 + \_module_inst: work@memory_ctrl1 (work@memory_ctrl1), file:${SURELOG_DIR}/tests/ModPortTest/top.v, line:36:1, endln:43:10 |vpiName:sif |vpiFullName:work@memory_ctrl1.sif |vpiDefName:work@mem_if |vpiModport: \_modport: (memory), line:32:12, endln:32:18 |vpiParent: - \_interface: work@mem_if (work@memory_ctrl1.sif), file:${SURELOG_DIR}/tests/ModPortTest/top.v, line:36:0 + \_interface_inst: work@mem_if (work@memory_ctrl1.sif), file:${SURELOG_DIR}/tests/ModPortTest/top.v, line:36:0 |vpiName:memory |vpiIODecl: \_io_decl: (clk), line:32:27, endln:32:30 @@ -722,12 +722,12 @@ design: (work@dff0_test) \_logic_typespec: , line:29:25, endln:29:29 |vpiName:clk |vpiNetType:1 - |vpiInterface: - \_interface: work@mem_if (work@memory_ctrl1.sif), file:${SURELOG_DIR}/tests/ModPortTest/top.v, line:36:0 + |vpiInterfaceInst: + \_interface_inst: work@mem_if (work@memory_ctrl1.sif), file:${SURELOG_DIR}/tests/ModPortTest/top.v, line:36:0 |vpiModport: \_modport: (system), line:31:12, endln:31:18 |vpiParent: - \_interface: work@mem_if (work@memory_ctrl1.sif), file:${SURELOG_DIR}/tests/ModPortTest/top.v, line:36:0 + \_interface_inst: work@mem_if (work@memory_ctrl1.sif), file:${SURELOG_DIR}/tests/ModPortTest/top.v, line:36:0 |vpiName:system |vpiIODecl: \_io_decl: (clk), line:31:26, endln:31:29 @@ -735,17 +735,17 @@ design: (work@dff0_test) |vpiName:clk |vpiExpr: \_logic_net: (clk), line:29:30, endln:29:33 - |vpiInterface: - \_interface: work@mem_if (work@memory_ctrl1.sif), file:${SURELOG_DIR}/tests/ModPortTest/top.v, line:36:0 - |vpiInterface: - \_interface: work@mem_if (work@memory_ctrl1.sif), file:${SURELOG_DIR}/tests/ModPortTest/top.v, line:36:0 + |vpiInterfaceInst: + \_interface_inst: work@mem_if (work@memory_ctrl1.sif), file:${SURELOG_DIR}/tests/ModPortTest/top.v, line:36:0 + |vpiInterfaceInst: + \_interface_inst: work@mem_if (work@memory_ctrl1.sif), file:${SURELOG_DIR}/tests/ModPortTest/top.v, line:36:0 |uhdmtopModules: -\_module: work@memory_ctrl2 (work@memory_ctrl2), file:${SURELOG_DIR}/tests/ModPortTest/top.v, line:45:1, endln:53:10 +\_module_inst: work@memory_ctrl2 (work@memory_ctrl2), file:${SURELOG_DIR}/tests/ModPortTest/top.v, line:45:1, endln:53:10 |vpiName:work@memory_ctrl2 |vpiVariables: \_enum_var: (work@memory_ctrl2.state), line:49:7, endln:49:12 |vpiParent: - \_module: work@memory_ctrl2 (work@memory_ctrl2), file:${SURELOG_DIR}/tests/ModPortTest/top.v, line:45:1, endln:53:10 + \_module_inst: work@memory_ctrl2 (work@memory_ctrl2), file:${SURELOG_DIR}/tests/ModPortTest/top.v, line:45:1, endln:53:10 |vpiTypespec: \_enum_typespec: (fsm_t), line:47:1, endln:47:44 |vpiName:state @@ -758,7 +758,7 @@ design: (work@dff0_test) |vpiNet: \_logic_net: (work@memory_ctrl2.t), line:51:4, endln:51:5 |vpiParent: - \_module: work@memory_ctrl2 (work@memory_ctrl2), file:${SURELOG_DIR}/tests/ModPortTest/top.v, line:45:1, endln:53:10 + \_module_inst: work@memory_ctrl2 (work@memory_ctrl2), file:${SURELOG_DIR}/tests/ModPortTest/top.v, line:45:1, endln:53:10 |vpiTypespec: \_unsupported_typespec: (DD), line:51:1, endln:51:3 |vpiName:DD @@ -768,7 +768,7 @@ design: (work@dff0_test) |vpiPort: \_port: (sif), line:45:36, endln:45:39 |vpiParent: - \_module: work@memory_ctrl2 (work@memory_ctrl2), file:${SURELOG_DIR}/tests/ModPortTest/top.v, line:45:1, endln:53:10 + \_module_inst: work@memory_ctrl2 (work@memory_ctrl2), file:${SURELOG_DIR}/tests/ModPortTest/top.v, line:45:1, endln:53:10 |vpiName:sif |vpiDirection:3 |vpiLowConn: @@ -782,17 +782,17 @@ design: (work@dff0_test) \_interface_typespec: (mem_if), line:45:22, endln:45:28 |vpiName:system |vpiIsModPort:1 - |vpiInterface: - \_interface: work@mem_if (work@memory_ctrl2.sif), file:${SURELOG_DIR}/tests/ModPortTest/top.v, line:45:0 + |vpiInterfaceInst: + \_interface_inst: work@mem_if (work@memory_ctrl2.sif), file:${SURELOG_DIR}/tests/ModPortTest/top.v, line:45:0 |vpiParent: - \_module: work@memory_ctrl2 (work@memory_ctrl2), file:${SURELOG_DIR}/tests/ModPortTest/top.v, line:45:1, endln:53:10 + \_module_inst: work@memory_ctrl2 (work@memory_ctrl2), file:${SURELOG_DIR}/tests/ModPortTest/top.v, line:45:1, endln:53:10 |vpiName:sif |vpiFullName:work@memory_ctrl2.sif |vpiDefName:work@mem_if |vpiModport: \_modport: (system), line:31:12, endln:31:18 |vpiParent: - \_interface: work@mem_if (work@memory_ctrl2.sif), file:${SURELOG_DIR}/tests/ModPortTest/top.v, line:45:0 + \_interface_inst: work@mem_if (work@memory_ctrl2.sif), file:${SURELOG_DIR}/tests/ModPortTest/top.v, line:45:0 |vpiName:system |vpiIODecl: \_io_decl: (clk), line:31:26, endln:31:29 @@ -804,8 +804,8 @@ design: (work@dff0_test) \_logic_typespec: , line:29:25, endln:29:29 |vpiName:clk |vpiNetType:1 - |vpiInterface: - \_interface: work@mem_if (work@memory_ctrl2.sif), file:${SURELOG_DIR}/tests/ModPortTest/top.v, line:45:0 + |vpiInterfaceInst: + \_interface_inst: work@mem_if (work@memory_ctrl2.sif), file:${SURELOG_DIR}/tests/ModPortTest/top.v, line:45:0 =================== [ FATAL] : 0 [ SYNTAX] : 0 diff --git a/tests/MultContAssign/MultContAssign.log b/tests/MultContAssign/MultContAssign.log index 65f5f8840c..c251c46f1c 100644 --- a/tests/MultContAssign/MultContAssign.log +++ b/tests/MultContAssign/MultContAssign.log @@ -565,7 +565,7 @@ int_typespec 3 int_var 1 logic_net 20 logic_typespec 8 -module 10 +module_inst 10 operation 8 param_assign 2 parameter 2 @@ -586,7 +586,7 @@ int_typespec 3 int_var 1 logic_net 20 logic_typespec 8 -module 10 +module_inst 10 operation 16 param_assign 2 parameter 2 @@ -607,14 +607,14 @@ design: (work@top) |vpiElaborated:1 |vpiName:work@top |uhdmallModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/MultContAssign/dut.sv, line:3:1, endln:45:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/MultContAssign/dut.sv, line:3:1, endln:45:10 |vpiParent: \_design: (work@top) |vpiFullName:work@top |vpiParameter: \_parameter: (work@top.NUM_WAYS), line:29:11, endln:29:19 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/MultContAssign/dut.sv, line:3:1, endln:45:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/MultContAssign/dut.sv, line:3:1, endln:45:10 |UINT:1 |vpiTypespec: \_int_typespec: @@ -623,7 +623,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:29:11, endln:29:23 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/MultContAssign/dut.sv, line:3:1, endln:45:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/MultContAssign/dut.sv, line:3:1, endln:45:10 |vpiRhs: \_constant: , line:29:22, endln:29:23 |vpiDecompile:1 @@ -638,13 +638,13 @@ design: (work@top) |vpiNet: \_logic_net: (work@top.v), line:5:6, endln:5:7 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/MultContAssign/dut.sv, line:3:1, endln:45:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/MultContAssign/dut.sv, line:3:1, endln:45:10 |vpiName:v |vpiFullName:work@top.v |vpiContAssign: \_cont_assign: , line:6:30, endln:6:43 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/MultContAssign/dut.sv, line:3:1, endln:45:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/MultContAssign/dut.sv, line:3:1, endln:45:10 |vpiStrength0:1 |vpiStrength1:8 |vpiRhs: @@ -666,7 +666,7 @@ design: (work@top) |vpiContAssign: \_cont_assign: , line:7:30, endln:7:44 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/MultContAssign/dut.sv, line:3:1, endln:45:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/MultContAssign/dut.sv, line:3:1, endln:45:10 |vpiStrength0:8 |vpiStrength1:1 |vpiRhs: @@ -693,7 +693,7 @@ design: (work@top) |vpiContAssign: \_cont_assign: , line:9:9, endln:9:15 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/MultContAssign/dut.sv, line:3:1, endln:45:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/MultContAssign/dut.sv, line:3:1, endln:45:10 |vpiRhs: \_constant: , line:9:13, endln:9:15 |vpiParent: @@ -713,7 +713,7 @@ design: (work@top) |vpiContAssign: \_cont_assign: , line:10:9, endln:10:15 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/MultContAssign/dut.sv, line:3:1, endln:45:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/MultContAssign/dut.sv, line:3:1, endln:45:10 |vpiRhs: \_constant: , line:10:13, endln:10:15 |vpiParent: @@ -733,7 +733,7 @@ design: (work@top) |vpiContAssign: \_cont_assign: , line:13:29, endln:13:42 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/MultContAssign/dut.sv, line:3:1, endln:45:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/MultContAssign/dut.sv, line:3:1, endln:45:10 |vpiStrength0:8 |vpiStrength1:8 |vpiRhs: @@ -755,7 +755,7 @@ design: (work@top) |vpiContAssign: \_cont_assign: , line:14:30, endln:14:44 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/MultContAssign/dut.sv, line:3:1, endln:45:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/MultContAssign/dut.sv, line:3:1, endln:45:10 |vpiStrength0:8 |vpiStrength1:8 |vpiRhs: @@ -782,7 +782,7 @@ design: (work@top) |vpiContAssign: \_cont_assign: , line:21:17, endln:21:48 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/MultContAssign/dut.sv, line:3:1, endln:45:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/MultContAssign/dut.sv, line:3:1, endln:45:10 |vpiRhs: \_operation: , line:21:23, endln:21:48 |vpiParent: @@ -836,7 +836,7 @@ design: (work@top) |vpiContAssign: \_cont_assign: , line:22:17, endln:22:48 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/MultContAssign/dut.sv, line:3:1, endln:45:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/MultContAssign/dut.sv, line:3:1, endln:45:10 |vpiRhs: \_operation: , line:22:23, endln:22:48 |vpiParent: @@ -890,7 +890,7 @@ design: (work@top) |vpiContAssign: \_cont_assign: , line:24:33, endln:24:49 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/MultContAssign/dut.sv, line:3:1, endln:45:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/MultContAssign/dut.sv, line:3:1, endln:45:10 |vpiStrength0:32 |vpiStrength1:32 |vpiRhs: @@ -912,7 +912,7 @@ design: (work@top) |vpiContAssign: \_cont_assign: , line:26:18, endln:26:61 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/MultContAssign/dut.sv, line:3:1, endln:45:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/MultContAssign/dut.sv, line:3:1, endln:45:10 |vpiRhs: \_operation: , line:26:30, endln:26:61 |vpiParent: @@ -951,7 +951,7 @@ design: (work@top) |vpiActual: \_logic_net: (pull_up_1) |uhdmallModules: -\_module: work@top2 (work@top2), file:${SURELOG_DIR}/tests/MultContAssign/dut.sv, line:57:1, endln:64:10 +\_module_inst: work@top2 (work@top2), file:${SURELOG_DIR}/tests/MultContAssign/dut.sv, line:57:1, endln:64:10 |vpiParent: \_design: (work@top) |vpiFullName:work@top2 @@ -959,14 +959,14 @@ design: (work@top) |vpiNet: \_logic_net: (work@top2.two), line:58:9, endln:58:12 |vpiParent: - \_module: work@top2 (work@top2), file:${SURELOG_DIR}/tests/MultContAssign/dut.sv, line:57:1, endln:64:10 + \_module_inst: work@top2 (work@top2), file:${SURELOG_DIR}/tests/MultContAssign/dut.sv, line:57:1, endln:64:10 |vpiName:two |vpiFullName:work@top2.two |vpiNetType:13 |vpiProcess: \_initial: , line:63:3, endln:63:68 |vpiParent: - \_module: work@top2 (work@top2), file:${SURELOG_DIR}/tests/MultContAssign/dut.sv, line:57:1, endln:64:10 + \_module_inst: work@top2 (work@top2), file:${SURELOG_DIR}/tests/MultContAssign/dut.sv, line:57:1, endln:64:10 |vpiStmt: \_sys_func_call: ($display), line:63:11, endln:63:67 |vpiParent: @@ -983,7 +983,7 @@ design: (work@top) |vpiContAssign: \_cont_assign: , line:60:10, endln:60:20 |vpiParent: - \_module: work@top2 (work@top2), file:${SURELOG_DIR}/tests/MultContAssign/dut.sv, line:57:1, endln:64:10 + \_module_inst: work@top2 (work@top2), file:${SURELOG_DIR}/tests/MultContAssign/dut.sv, line:57:1, endln:64:10 |vpiRhs: \_constant: , line:60:16, endln:60:20 |vpiParent: @@ -1003,7 +1003,7 @@ design: (work@top) |vpiContAssign: \_cont_assign: , line:61:10, endln:61:20 |vpiParent: - \_module: work@top2 (work@top2), file:${SURELOG_DIR}/tests/MultContAssign/dut.sv, line:57:1, endln:64:10 + \_module_inst: work@top2 (work@top2), file:${SURELOG_DIR}/tests/MultContAssign/dut.sv, line:57:1, endln:64:10 |vpiRhs: \_constant: , line:61:16, endln:61:20 |vpiParent: @@ -1021,7 +1021,7 @@ design: (work@top) |vpiActual: \_logic_net: (work@top2.two), line:58:9, endln:58:12 |uhdmallModules: -\_module: work@wandwor_test0 (work@wandwor_test0), file:${SURELOG_DIR}/tests/MultContAssign/dut.sv, line:48:1, endln:54:10 +\_module_inst: work@wandwor_test0 (work@wandwor_test0), file:${SURELOG_DIR}/tests/MultContAssign/dut.sv, line:48:1, endln:54:10 |vpiParent: \_design: (work@top) |vpiFullName:work@wandwor_test0 @@ -1029,26 +1029,26 @@ design: (work@top) |vpiNet: \_logic_net: (work@wandwor_test0.A), line:48:23, endln:48:24 |vpiParent: - \_module: work@wandwor_test0 (work@wandwor_test0), file:${SURELOG_DIR}/tests/MultContAssign/dut.sv, line:48:1, endln:54:10 + \_module_inst: work@wandwor_test0 (work@wandwor_test0), file:${SURELOG_DIR}/tests/MultContAssign/dut.sv, line:48:1, endln:54:10 |vpiName:A |vpiFullName:work@wandwor_test0.A |vpiNet: \_logic_net: (work@wandwor_test0.B), line:48:26, endln:48:27 |vpiParent: - \_module: work@wandwor_test0 (work@wandwor_test0), file:${SURELOG_DIR}/tests/MultContAssign/dut.sv, line:48:1, endln:54:10 + \_module_inst: work@wandwor_test0 (work@wandwor_test0), file:${SURELOG_DIR}/tests/MultContAssign/dut.sv, line:48:1, endln:54:10 |vpiName:B |vpiFullName:work@wandwor_test0.B |vpiNet: \_logic_net: (work@wandwor_test0.X), line:48:29, endln:48:30 |vpiParent: - \_module: work@wandwor_test0 (work@wandwor_test0), file:${SURELOG_DIR}/tests/MultContAssign/dut.sv, line:48:1, endln:54:10 + \_module_inst: work@wandwor_test0 (work@wandwor_test0), file:${SURELOG_DIR}/tests/MultContAssign/dut.sv, line:48:1, endln:54:10 |vpiName:X |vpiFullName:work@wandwor_test0.X |vpiNetType:3 |vpiPort: \_port: (A), line:48:23, endln:48:24 |vpiParent: - \_module: work@wandwor_test0 (work@wandwor_test0), file:${SURELOG_DIR}/tests/MultContAssign/dut.sv, line:48:1, endln:54:10 + \_module_inst: work@wandwor_test0 (work@wandwor_test0), file:${SURELOG_DIR}/tests/MultContAssign/dut.sv, line:48:1, endln:54:10 |vpiName:A |vpiDirection:1 |vpiLowConn: @@ -1060,7 +1060,7 @@ design: (work@top) |vpiPort: \_port: (B), line:48:26, endln:48:27 |vpiParent: - \_module: work@wandwor_test0 (work@wandwor_test0), file:${SURELOG_DIR}/tests/MultContAssign/dut.sv, line:48:1, endln:54:10 + \_module_inst: work@wandwor_test0 (work@wandwor_test0), file:${SURELOG_DIR}/tests/MultContAssign/dut.sv, line:48:1, endln:54:10 |vpiName:B |vpiDirection:1 |vpiLowConn: @@ -1072,7 +1072,7 @@ design: (work@top) |vpiPort: \_port: (X), line:48:29, endln:48:30 |vpiParent: - \_module: work@wandwor_test0 (work@wandwor_test0), file:${SURELOG_DIR}/tests/MultContAssign/dut.sv, line:48:1, endln:54:10 + \_module_inst: work@wandwor_test0 (work@wandwor_test0), file:${SURELOG_DIR}/tests/MultContAssign/dut.sv, line:48:1, endln:54:10 |vpiName:X |vpiDirection:2 |vpiLowConn: @@ -1084,7 +1084,7 @@ design: (work@top) |vpiContAssign: \_cont_assign: , line:52:9, endln:52:21 |vpiParent: - \_module: work@wandwor_test0 (work@wandwor_test0), file:${SURELOG_DIR}/tests/MultContAssign/dut.sv, line:48:1, endln:54:10 + \_module_inst: work@wandwor_test0 (work@wandwor_test0), file:${SURELOG_DIR}/tests/MultContAssign/dut.sv, line:48:1, endln:54:10 |vpiRhs: \_ref_obj: (work@wandwor_test0.A), line:52:13, endln:52:14 |vpiParent: @@ -1104,7 +1104,7 @@ design: (work@top) |vpiContAssign: \_cont_assign: , line:52:9, endln:52:21 |vpiParent: - \_module: work@wandwor_test0 (work@wandwor_test0), file:${SURELOG_DIR}/tests/MultContAssign/dut.sv, line:48:1, endln:54:10 + \_module_inst: work@wandwor_test0 (work@wandwor_test0), file:${SURELOG_DIR}/tests/MultContAssign/dut.sv, line:48:1, endln:54:10 |vpiRhs: \_ref_obj: (work@wandwor_test0.B), line:52:20, endln:52:21 |vpiParent: @@ -1122,12 +1122,12 @@ design: (work@top) |vpiActual: \_logic_net: (work@wandwor_test0.X), line:48:29, endln:48:30 |uhdmtopModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/MultContAssign/dut.sv, line:3:1, endln:45:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/MultContAssign/dut.sv, line:3:1, endln:45:10 |vpiName:work@top |vpiVariables: \_int_var: (work@top.v), line:5:6, endln:5:7 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/MultContAssign/dut.sv, line:3:1, endln:45:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/MultContAssign/dut.sv, line:3:1, endln:45:10 |vpiTypespec: \_int_typespec: , line:5:2, endln:5:5 |vpiSigned:1 @@ -1137,7 +1137,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.NUM_WAYS), line:29:11, endln:29:19 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/MultContAssign/dut.sv, line:3:1, endln:45:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/MultContAssign/dut.sv, line:3:1, endln:45:10 |UINT:1 |vpiTypespec: \_int_typespec: @@ -1148,7 +1148,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:29:11, endln:29:23 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/MultContAssign/dut.sv, line:3:1, endln:45:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/MultContAssign/dut.sv, line:3:1, endln:45:10 |vpiRhs: \_constant: , line:29:22, endln:29:23 |vpiDecompile:1 @@ -1209,7 +1209,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.genblk1), line:17:4, endln:18:50 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/MultContAssign/dut.sv, line:3:1, endln:45:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/MultContAssign/dut.sv, line:3:1, endln:45:10 |vpiName:genblk1 |vpiFullName:work@top.genblk1 |vpiGenScope: @@ -1245,7 +1245,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.genblk2), line:31:4, endln:42:11 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/MultContAssign/dut.sv, line:3:1, endln:45:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/MultContAssign/dut.sv, line:3:1, endln:45:10 |vpiName:genblk2 |vpiFullName:work@top.genblk2 |vpiGenScope: @@ -1274,7 +1274,7 @@ design: (work@top) |vpiContAssign: \_cont_assign: , line:6:30, endln:6:43 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/MultContAssign/dut.sv, line:3:1, endln:45:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/MultContAssign/dut.sv, line:3:1, endln:45:10 |vpiStrength0:1 |vpiStrength1:8 |vpiRhs: @@ -1296,7 +1296,7 @@ design: (work@top) |vpiContAssign: \_cont_assign: , line:7:30, endln:7:44 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/MultContAssign/dut.sv, line:3:1, endln:45:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/MultContAssign/dut.sv, line:3:1, endln:45:10 |vpiStrength0:8 |vpiStrength1:1 |vpiRhs: @@ -1323,7 +1323,7 @@ design: (work@top) |vpiContAssign: \_cont_assign: , line:9:9, endln:9:15 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/MultContAssign/dut.sv, line:3:1, endln:45:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/MultContAssign/dut.sv, line:3:1, endln:45:10 |vpiRhs: \_constant: , line:9:13, endln:9:15 |vpiParent: @@ -1343,7 +1343,7 @@ design: (work@top) |vpiContAssign: \_cont_assign: , line:10:9, endln:10:15 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/MultContAssign/dut.sv, line:3:1, endln:45:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/MultContAssign/dut.sv, line:3:1, endln:45:10 |vpiRhs: \_constant: , line:10:13, endln:10:15 |vpiParent: @@ -1363,7 +1363,7 @@ design: (work@top) |vpiContAssign: \_cont_assign: , line:13:29, endln:13:42 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/MultContAssign/dut.sv, line:3:1, endln:45:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/MultContAssign/dut.sv, line:3:1, endln:45:10 |vpiStrength0:8 |vpiStrength1:8 |vpiRhs: @@ -1385,7 +1385,7 @@ design: (work@top) |vpiContAssign: \_cont_assign: , line:14:30, endln:14:44 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/MultContAssign/dut.sv, line:3:1, endln:45:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/MultContAssign/dut.sv, line:3:1, endln:45:10 |vpiStrength0:8 |vpiStrength1:8 |vpiRhs: @@ -1412,7 +1412,7 @@ design: (work@top) |vpiContAssign: \_cont_assign: , line:21:17, endln:21:48 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/MultContAssign/dut.sv, line:3:1, endln:45:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/MultContAssign/dut.sv, line:3:1, endln:45:10 |vpiRhs: \_operation: , line:21:23, endln:21:48 |vpiParent: @@ -1454,7 +1454,7 @@ design: (work@top) |vpiContAssign: \_cont_assign: , line:22:17, endln:22:48 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/MultContAssign/dut.sv, line:3:1, endln:45:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/MultContAssign/dut.sv, line:3:1, endln:45:10 |vpiRhs: \_operation: , line:22:23, endln:22:48 |vpiParent: @@ -1496,7 +1496,7 @@ design: (work@top) |vpiContAssign: \_cont_assign: , line:24:33, endln:24:49 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/MultContAssign/dut.sv, line:3:1, endln:45:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/MultContAssign/dut.sv, line:3:1, endln:45:10 |vpiStrength0:32 |vpiStrength1:32 |vpiRhs: @@ -1512,7 +1512,7 @@ design: (work@top) |vpiContAssign: \_cont_assign: , line:26:18, endln:26:61 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/MultContAssign/dut.sv, line:3:1, endln:45:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/MultContAssign/dut.sv, line:3:1, endln:45:10 |vpiRhs: \_operation: , line:26:30, endln:26:61 |vpiParent: @@ -1545,14 +1545,14 @@ design: (work@top) |vpiActual: \_logic_net: (pull_up_1) |uhdmtopModules: -\_module: work@wandwor_test0 (work@wandwor_test0), file:${SURELOG_DIR}/tests/MultContAssign/dut.sv, line:48:1, endln:54:10 +\_module_inst: work@wandwor_test0 (work@wandwor_test0), file:${SURELOG_DIR}/tests/MultContAssign/dut.sv, line:48:1, endln:54:10 |vpiName:work@wandwor_test0 |vpiDefName:work@wandwor_test0 |vpiTop:1 |vpiNet: \_logic_net: (work@wandwor_test0.A), line:48:23, endln:48:24 |vpiParent: - \_module: work@wandwor_test0 (work@wandwor_test0), file:${SURELOG_DIR}/tests/MultContAssign/dut.sv, line:48:1, endln:54:10 + \_module_inst: work@wandwor_test0 (work@wandwor_test0), file:${SURELOG_DIR}/tests/MultContAssign/dut.sv, line:48:1, endln:54:10 |vpiTypespec: \_logic_typespec: , line:49:8, endln:49:8 |vpiName:A @@ -1560,7 +1560,7 @@ design: (work@top) |vpiNet: \_logic_net: (work@wandwor_test0.B), line:48:26, endln:48:27 |vpiParent: - \_module: work@wandwor_test0 (work@wandwor_test0), file:${SURELOG_DIR}/tests/MultContAssign/dut.sv, line:48:1, endln:54:10 + \_module_inst: work@wandwor_test0 (work@wandwor_test0), file:${SURELOG_DIR}/tests/MultContAssign/dut.sv, line:48:1, endln:54:10 |vpiTypespec: \_logic_typespec: , line:49:8, endln:49:8 |vpiName:B @@ -1568,7 +1568,7 @@ design: (work@top) |vpiNet: \_logic_net: (work@wandwor_test0.X), line:48:29, endln:48:30 |vpiParent: - \_module: work@wandwor_test0 (work@wandwor_test0), file:${SURELOG_DIR}/tests/MultContAssign/dut.sv, line:48:1, endln:54:10 + \_module_inst: work@wandwor_test0 (work@wandwor_test0), file:${SURELOG_DIR}/tests/MultContAssign/dut.sv, line:48:1, endln:54:10 |vpiTypespec: \_logic_typespec: , line:50:9, endln:50:12 |vpiName:X @@ -1578,7 +1578,7 @@ design: (work@top) |vpiPort: \_port: (A), line:48:23, endln:48:24 |vpiParent: - \_module: work@wandwor_test0 (work@wandwor_test0), file:${SURELOG_DIR}/tests/MultContAssign/dut.sv, line:48:1, endln:54:10 + \_module_inst: work@wandwor_test0 (work@wandwor_test0), file:${SURELOG_DIR}/tests/MultContAssign/dut.sv, line:48:1, endln:54:10 |vpiName:A |vpiDirection:1 |vpiLowConn: @@ -1592,11 +1592,11 @@ design: (work@top) |vpiTypedef: \_logic_typespec: , line:49:8, endln:49:8 |vpiInstance: - \_module: work@wandwor_test0 (work@wandwor_test0), file:${SURELOG_DIR}/tests/MultContAssign/dut.sv, line:48:1, endln:54:10 + \_module_inst: work@wandwor_test0 (work@wandwor_test0), file:${SURELOG_DIR}/tests/MultContAssign/dut.sv, line:48:1, endln:54:10 |vpiPort: \_port: (B), line:48:26, endln:48:27 |vpiParent: - \_module: work@wandwor_test0 (work@wandwor_test0), file:${SURELOG_DIR}/tests/MultContAssign/dut.sv, line:48:1, endln:54:10 + \_module_inst: work@wandwor_test0 (work@wandwor_test0), file:${SURELOG_DIR}/tests/MultContAssign/dut.sv, line:48:1, endln:54:10 |vpiName:B |vpiDirection:1 |vpiLowConn: @@ -1610,11 +1610,11 @@ design: (work@top) |vpiTypedef: \_logic_typespec: , line:49:8, endln:49:8 |vpiInstance: - \_module: work@wandwor_test0 (work@wandwor_test0), file:${SURELOG_DIR}/tests/MultContAssign/dut.sv, line:48:1, endln:54:10 + \_module_inst: work@wandwor_test0 (work@wandwor_test0), file:${SURELOG_DIR}/tests/MultContAssign/dut.sv, line:48:1, endln:54:10 |vpiPort: \_port: (X), line:48:29, endln:48:30 |vpiParent: - \_module: work@wandwor_test0 (work@wandwor_test0), file:${SURELOG_DIR}/tests/MultContAssign/dut.sv, line:48:1, endln:54:10 + \_module_inst: work@wandwor_test0 (work@wandwor_test0), file:${SURELOG_DIR}/tests/MultContAssign/dut.sv, line:48:1, endln:54:10 |vpiName:X |vpiDirection:2 |vpiLowConn: @@ -1628,11 +1628,11 @@ design: (work@top) |vpiTypedef: \_logic_typespec: , line:50:9, endln:50:12 |vpiInstance: - \_module: work@wandwor_test0 (work@wandwor_test0), file:${SURELOG_DIR}/tests/MultContAssign/dut.sv, line:48:1, endln:54:10 + \_module_inst: work@wandwor_test0 (work@wandwor_test0), file:${SURELOG_DIR}/tests/MultContAssign/dut.sv, line:48:1, endln:54:10 |vpiContAssign: \_cont_assign: , line:52:9, endln:52:21 |vpiParent: - \_module: work@wandwor_test0 (work@wandwor_test0), file:${SURELOG_DIR}/tests/MultContAssign/dut.sv, line:48:1, endln:54:10 + \_module_inst: work@wandwor_test0 (work@wandwor_test0), file:${SURELOG_DIR}/tests/MultContAssign/dut.sv, line:48:1, endln:54:10 |vpiRhs: \_ref_obj: (work@wandwor_test0.A), line:52:13, endln:52:14 |vpiParent: @@ -1652,7 +1652,7 @@ design: (work@top) |vpiContAssign: \_cont_assign: , line:52:9, endln:52:21 |vpiParent: - \_module: work@wandwor_test0 (work@wandwor_test0), file:${SURELOG_DIR}/tests/MultContAssign/dut.sv, line:48:1, endln:54:10 + \_module_inst: work@wandwor_test0 (work@wandwor_test0), file:${SURELOG_DIR}/tests/MultContAssign/dut.sv, line:48:1, endln:54:10 |vpiRhs: \_ref_obj: (work@wandwor_test0.B), line:52:20, endln:52:21 |vpiParent: @@ -1670,14 +1670,14 @@ design: (work@top) |vpiActual: \_logic_net: (work@wandwor_test0.X), line:48:29, endln:48:30 |uhdmtopModules: -\_module: work@top2 (work@top2), file:${SURELOG_DIR}/tests/MultContAssign/dut.sv, line:57:1, endln:64:10 +\_module_inst: work@top2 (work@top2), file:${SURELOG_DIR}/tests/MultContAssign/dut.sv, line:57:1, endln:64:10 |vpiName:work@top2 |vpiDefName:work@top2 |vpiTop:1 |vpiNet: \_logic_net: (work@top2.two), line:58:9, endln:58:12 |vpiParent: - \_module: work@top2 (work@top2), file:${SURELOG_DIR}/tests/MultContAssign/dut.sv, line:57:1, endln:64:10 + \_module_inst: work@top2 (work@top2), file:${SURELOG_DIR}/tests/MultContAssign/dut.sv, line:57:1, endln:64:10 |vpiTypespec: \_logic_typespec: , line:58:3, endln:58:8 |vpiName:two @@ -1687,7 +1687,7 @@ design: (work@top) |vpiProcess: \_initial: , line:63:3, endln:63:68 |vpiParent: - \_module: work@top2 (work@top2), file:${SURELOG_DIR}/tests/MultContAssign/dut.sv, line:57:1, endln:64:10 + \_module_inst: work@top2 (work@top2), file:${SURELOG_DIR}/tests/MultContAssign/dut.sv, line:57:1, endln:64:10 |vpiStmt: \_sys_func_call: ($display), line:63:11, endln:63:67 |vpiParent: @@ -1698,7 +1698,7 @@ design: (work@top) |vpiContAssign: \_cont_assign: , line:60:10, endln:60:20 |vpiParent: - \_module: work@top2 (work@top2), file:${SURELOG_DIR}/tests/MultContAssign/dut.sv, line:57:1, endln:64:10 + \_module_inst: work@top2 (work@top2), file:${SURELOG_DIR}/tests/MultContAssign/dut.sv, line:57:1, endln:64:10 |vpiRhs: \_constant: , line:60:16, endln:60:20 |vpiLhs: @@ -1712,7 +1712,7 @@ design: (work@top) |vpiContAssign: \_cont_assign: , line:61:10, endln:61:20 |vpiParent: - \_module: work@top2 (work@top2), file:${SURELOG_DIR}/tests/MultContAssign/dut.sv, line:57:1, endln:64:10 + \_module_inst: work@top2 (work@top2), file:${SURELOG_DIR}/tests/MultContAssign/dut.sv, line:57:1, endln:64:10 |vpiRhs: \_constant: , line:61:16, endln:61:20 |vpiLhs: diff --git a/tests/MultiConcat/MultiConcat.log b/tests/MultiConcat/MultiConcat.log index faec88b774..9f1821a440 100644 --- a/tests/MultiConcat/MultiConcat.log +++ b/tests/MultiConcat/MultiConcat.log @@ -1687,7 +1687,7 @@ enum_const 58 enum_typespec 8 int_typespec 33 logic_typespec 32 -module 2 +module_inst 2 operation 1038 package 3 packed_array_typespec 10 @@ -1705,7 +1705,7 @@ enum_const 58 enum_typespec 8 int_typespec 33 logic_typespec 32 -module 2 +module_inst 2 operation 1038 package 3 packed_array_typespec 10 diff --git a/tests/MultiConcatValueSize/MultiConcatValueSize.log b/tests/MultiConcatValueSize/MultiConcatValueSize.log index 2582a744ea..2321f4eafa 100644 --- a/tests/MultiConcatValueSize/MultiConcatValueSize.log +++ b/tests/MultiConcatValueSize/MultiConcatValueSize.log @@ -802,7 +802,7 @@ io_decl 11 logic_net 4 logic_typespec 25 logic_var 1 -module 18 +module_inst 18 operation 47 package 8 packed_array_typespec 23 @@ -841,7 +841,7 @@ io_decl 22 logic_net 4 logic_typespec 25 logic_var 1 -module 22 +module_inst 22 operation 47 package 8 packed_array_typespec 23 @@ -1003,7 +1003,7 @@ design: (work@top) |vpiElemTypespec: \_enum_typespec: (prim_pad_wrapper_pkg::pad_type_e), line:2:4, endln:5:17 |vpiParent: - \_module: work@sub_top (work@sub_top), file:${SURELOG_DIR}/tests/MultiConcatValueSize/dut.sv, line:41:1, endln:50:10 + \_module_inst: work@sub_top (work@sub_top), file:${SURELOG_DIR}/tests/MultiConcatValueSize/dut.sv, line:41:1, endln:50:10 |vpiName:prim_pad_wrapper_pkg::pad_type_e |vpiInstance: \_package: pinmux_pkg (pinmux_pkg::), file:${SURELOG_DIR}/tests/MultiConcatValueSize/dut.sv, line:8:1, endln:20:24 @@ -1168,7 +1168,7 @@ design: (work@top) |vpiTypespec: \_struct_typespec: (pinmux_pkg::target_cfg_t), line:13:12, endln:13:18 |vpiParent: - \_module: work@sub_top (work@sub_top), file:${SURELOG_DIR}/tests/MultiConcatValueSize/dut.sv, line:41:1, endln:50:10 + \_module_inst: work@sub_top (work@sub_top), file:${SURELOG_DIR}/tests/MultiConcatValueSize/dut.sv, line:41:1, endln:50:10 |vpiName:pinmux_pkg::target_cfg_t |vpiInstance: \_package: pinmux_pkg (pinmux_pkg::), file:${SURELOG_DIR}/tests/MultiConcatValueSize/dut.sv, line:8:1, endln:20:24 @@ -1689,14 +1689,14 @@ design: (work@top) \_int_typespec: |vpiSigned:1 |uhdmallModules: -\_module: work@prim_generic_pad_attr (work@prim_generic_pad_attr), file:${SURELOG_DIR}/tests/MultiConcatValueSize/dut.sv, line:22:1, endln:28:34 +\_module_inst: work@prim_generic_pad_attr (work@prim_generic_pad_attr), file:${SURELOG_DIR}/tests/MultiConcatValueSize/dut.sv, line:22:1, endln:28:34 |vpiParent: \_design: (work@top) |vpiFullName:work@prim_generic_pad_attr |vpiParameter: \_parameter: (work@prim_generic_pad_attr.PadType), line:24:25, endln:24:32 |vpiParent: - \_module: work@prim_generic_pad_attr (work@prim_generic_pad_attr), file:${SURELOG_DIR}/tests/MultiConcatValueSize/dut.sv, line:22:1, endln:28:34 + \_module_inst: work@prim_generic_pad_attr (work@prim_generic_pad_attr), file:${SURELOG_DIR}/tests/MultiConcatValueSize/dut.sv, line:22:1, endln:28:34 |vpiTypespec: \_enum_typespec: (prim_pad_wrapper_pkg::pad_type_e), line:2:4, endln:5:17 |vpiName:PadType @@ -1704,7 +1704,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:24:25, endln:24:36 |vpiParent: - \_module: work@prim_generic_pad_attr (work@prim_generic_pad_attr), file:${SURELOG_DIR}/tests/MultiConcatValueSize/dut.sv, line:22:1, endln:28:34 + \_module_inst: work@prim_generic_pad_attr (work@prim_generic_pad_attr), file:${SURELOG_DIR}/tests/MultiConcatValueSize/dut.sv, line:22:1, endln:28:34 |vpiRhs: \_ref_obj: (A), line:24:35, endln:24:36 |vpiName:A @@ -1720,13 +1720,13 @@ design: (work@top) |vpiNet: \_logic_net: (work@prim_generic_pad_attr.a), line:22:41, endln:22:42 |vpiParent: - \_module: work@prim_generic_pad_attr (work@prim_generic_pad_attr), file:${SURELOG_DIR}/tests/MultiConcatValueSize/dut.sv, line:22:1, endln:28:34 + \_module_inst: work@prim_generic_pad_attr (work@prim_generic_pad_attr), file:${SURELOG_DIR}/tests/MultiConcatValueSize/dut.sv, line:22:1, endln:28:34 |vpiName:a |vpiFullName:work@prim_generic_pad_attr.a |vpiPort: \_port: (a), line:22:41, endln:22:42 |vpiParent: - \_module: work@prim_generic_pad_attr (work@prim_generic_pad_attr), file:${SURELOG_DIR}/tests/MultiConcatValueSize/dut.sv, line:22:1, endln:28:34 + \_module_inst: work@prim_generic_pad_attr (work@prim_generic_pad_attr), file:${SURELOG_DIR}/tests/MultiConcatValueSize/dut.sv, line:22:1, endln:28:34 |vpiName:a |vpiDirection:2 |vpiLowConn: @@ -1737,14 +1737,14 @@ design: (work@top) \_int_typespec: , line:22:37, endln:22:40 |vpiSigned:1 |uhdmallModules: -\_module: work@prim_pad_attr (work@prim_pad_attr), file:${SURELOG_DIR}/tests/MultiConcatValueSize/dut.sv, line:30:1, endln:39:10 +\_module_inst: work@prim_pad_attr (work@prim_pad_attr), file:${SURELOG_DIR}/tests/MultiConcatValueSize/dut.sv, line:30:1, endln:39:10 |vpiParent: \_design: (work@top) |vpiFullName:work@prim_pad_attr |vpiParameter: \_parameter: (work@prim_pad_attr.PadType), line:32:25, endln:32:32 |vpiParent: - \_module: work@prim_pad_attr (work@prim_pad_attr), file:${SURELOG_DIR}/tests/MultiConcatValueSize/dut.sv, line:30:1, endln:39:10 + \_module_inst: work@prim_pad_attr (work@prim_pad_attr), file:${SURELOG_DIR}/tests/MultiConcatValueSize/dut.sv, line:30:1, endln:39:10 |vpiTypespec: \_enum_typespec: (prim_pad_wrapper_pkg::pad_type_e), line:2:4, endln:5:17 |vpiName:PadType @@ -1752,7 +1752,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:32:25, endln:32:36 |vpiParent: - \_module: work@prim_pad_attr (work@prim_pad_attr), file:${SURELOG_DIR}/tests/MultiConcatValueSize/dut.sv, line:30:1, endln:39:10 + \_module_inst: work@prim_pad_attr (work@prim_pad_attr), file:${SURELOG_DIR}/tests/MultiConcatValueSize/dut.sv, line:30:1, endln:39:10 |vpiRhs: \_ref_obj: (A), line:32:35, endln:32:36 |vpiName:A @@ -1768,13 +1768,13 @@ design: (work@top) |vpiNet: \_logic_net: (work@prim_pad_attr.b), line:30:33, endln:30:34 |vpiParent: - \_module: work@prim_pad_attr (work@prim_pad_attr), file:${SURELOG_DIR}/tests/MultiConcatValueSize/dut.sv, line:30:1, endln:39:10 + \_module_inst: work@prim_pad_attr (work@prim_pad_attr), file:${SURELOG_DIR}/tests/MultiConcatValueSize/dut.sv, line:30:1, endln:39:10 |vpiName:b |vpiFullName:work@prim_pad_attr.b |vpiPort: \_port: (b), line:30:33, endln:30:34 |vpiParent: - \_module: work@prim_pad_attr (work@prim_pad_attr), file:${SURELOG_DIR}/tests/MultiConcatValueSize/dut.sv, line:30:1, endln:39:10 + \_module_inst: work@prim_pad_attr (work@prim_pad_attr), file:${SURELOG_DIR}/tests/MultiConcatValueSize/dut.sv, line:30:1, endln:39:10 |vpiName:b |vpiDirection:2 |vpiLowConn: @@ -1785,14 +1785,14 @@ design: (work@top) \_int_typespec: , line:30:29, endln:30:32 |vpiSigned:1 |uhdmallModules: -\_module: work@sub_top (work@sub_top), file:${SURELOG_DIR}/tests/MultiConcatValueSize/dut.sv, line:41:1, endln:50:10 +\_module_inst: work@sub_top (work@sub_top), file:${SURELOG_DIR}/tests/MultiConcatValueSize/dut.sv, line:41:1, endln:50:10 |vpiParent: \_design: (work@top) |vpiFullName:work@sub_top |vpiParameter: \_parameter: (work@sub_top.DefaultTargetCfg), line:17:27, endln:17:43 |vpiParent: - \_module: work@sub_top (work@sub_top), file:${SURELOG_DIR}/tests/MultiConcatValueSize/dut.sv, line:41:1, endln:50:10 + \_module_inst: work@sub_top (work@sub_top), file:${SURELOG_DIR}/tests/MultiConcatValueSize/dut.sv, line:41:1, endln:50:10 |vpiTypespec: \_struct_typespec: (pinmux_pkg::target_cfg_t), line:13:12, endln:13:18 |vpiParent: @@ -1892,7 +1892,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@sub_top.NDioPads), line:11:18, endln:11:26 |vpiParent: - \_module: work@sub_top (work@sub_top), file:${SURELOG_DIR}/tests/MultiConcatValueSize/dut.sv, line:41:1, endln:50:10 + \_module_inst: work@sub_top (work@sub_top), file:${SURELOG_DIR}/tests/MultiConcatValueSize/dut.sv, line:41:1, endln:50:10 |UINT:1 |vpiTypespec: \_int_typespec: , line:11:14, endln:11:17 @@ -1908,7 +1908,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@sub_top.TargetCfg), line:43:27, endln:43:36 |vpiParent: - \_module: work@sub_top (work@sub_top), file:${SURELOG_DIR}/tests/MultiConcatValueSize/dut.sv, line:41:1, endln:50:10 + \_module_inst: work@sub_top (work@sub_top), file:${SURELOG_DIR}/tests/MultiConcatValueSize/dut.sv, line:41:1, endln:50:10 |vpiTypespec: \_struct_typespec: (pinmux_pkg::target_cfg_t), line:13:12, endln:13:18 |vpiName:TargetCfg @@ -1916,7 +1916,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:11:18, endln:11:30 |vpiParent: - \_module: work@sub_top (work@sub_top), file:${SURELOG_DIR}/tests/MultiConcatValueSize/dut.sv, line:41:1, endln:50:10 + \_module_inst: work@sub_top (work@sub_top), file:${SURELOG_DIR}/tests/MultiConcatValueSize/dut.sv, line:41:1, endln:50:10 |vpiRhs: \_constant: , line:11:29, endln:11:30 |vpiParent: @@ -1951,7 +1951,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:17:27, endln:19:5 |vpiParent: - \_module: work@sub_top (work@sub_top), file:${SURELOG_DIR}/tests/MultiConcatValueSize/dut.sv, line:41:1, endln:50:10 + \_module_inst: work@sub_top (work@sub_top), file:${SURELOG_DIR}/tests/MultiConcatValueSize/dut.sv, line:41:1, endln:50:10 |vpiRhs: \_operation: , line:17:46, endln:19:5 |vpiParent: @@ -2082,7 +2082,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:43:27, endln:43:55 |vpiParent: - \_module: work@sub_top (work@sub_top), file:${SURELOG_DIR}/tests/MultiConcatValueSize/dut.sv, line:41:1, endln:50:10 + \_module_inst: work@sub_top (work@sub_top), file:${SURELOG_DIR}/tests/MultiConcatValueSize/dut.sv, line:41:1, endln:50:10 |vpiRhs: \_ref_obj: (DefaultTargetCfg), line:43:39, endln:43:55 |vpiName:DefaultTargetCfg @@ -2098,13 +2098,13 @@ design: (work@top) |vpiNet: \_logic_net: (work@sub_top.c), line:41:27, endln:41:28 |vpiParent: - \_module: work@sub_top (work@sub_top), file:${SURELOG_DIR}/tests/MultiConcatValueSize/dut.sv, line:41:1, endln:50:10 + \_module_inst: work@sub_top (work@sub_top), file:${SURELOG_DIR}/tests/MultiConcatValueSize/dut.sv, line:41:1, endln:50:10 |vpiName:c |vpiFullName:work@sub_top.c |vpiPort: \_port: (c), line:41:27, endln:41:28 |vpiParent: - \_module: work@sub_top (work@sub_top), file:${SURELOG_DIR}/tests/MultiConcatValueSize/dut.sv, line:41:1, endln:50:10 + \_module_inst: work@sub_top (work@sub_top), file:${SURELOG_DIR}/tests/MultiConcatValueSize/dut.sv, line:41:1, endln:50:10 |vpiName:c |vpiDirection:2 |vpiLowConn: @@ -2115,14 +2115,14 @@ design: (work@top) \_int_typespec: , line:41:23, endln:41:26 |vpiSigned:1 |uhdmallModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/MultiConcatValueSize/dut.sv, line:52:1, endln:60:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/MultiConcatValueSize/dut.sv, line:52:1, endln:60:10 |vpiParent: \_design: (work@top) |vpiFullName:work@top |vpiParameter: \_parameter: (work@top.PinmuxTargetCfg), line:53:40, endln:53:55 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/MultiConcatValueSize/dut.sv, line:52:1, endln:60:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/MultiConcatValueSize/dut.sv, line:52:1, endln:60:10 |vpiTypespec: \_struct_typespec: (pinmux_pkg::target_cfg_t), line:13:12, endln:13:18 |vpiLocalParam:1 @@ -2131,7 +2131,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:53:40, endln:55:5 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/MultiConcatValueSize/dut.sv, line:52:1, endln:60:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/MultiConcatValueSize/dut.sv, line:52:1, endln:60:10 |vpiRhs: \_operation: , line:53:58, endln:55:5 |vpiOpType:75 @@ -2170,13 +2170,13 @@ design: (work@top) |vpiNet: \_logic_net: (work@top.o), line:52:23, endln:52:24 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/MultiConcatValueSize/dut.sv, line:52:1, endln:60:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/MultiConcatValueSize/dut.sv, line:52:1, endln:60:10 |vpiName:o |vpiFullName:work@top.o |vpiPort: \_port: (o), line:52:23, endln:52:24 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/MultiConcatValueSize/dut.sv, line:52:1, endln:60:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/MultiConcatValueSize/dut.sv, line:52:1, endln:60:10 |vpiName:o |vpiDirection:2 |vpiLowConn: @@ -2187,12 +2187,12 @@ design: (work@top) \_int_typespec: , line:52:19, endln:52:22 |vpiSigned:1 |uhdmtopModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/MultiConcatValueSize/dut.sv, line:52:1, endln:60:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/MultiConcatValueSize/dut.sv, line:52:1, endln:60:10 |vpiName:work@top |vpiVariables: \_int_var: (work@top.o), line:52:23, endln:52:24 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/MultiConcatValueSize/dut.sv, line:52:1, endln:60:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/MultiConcatValueSize/dut.sv, line:52:1, endln:60:10 |vpiTypespec: \_int_typespec: , line:52:19, endln:52:22 |vpiSigned:1 @@ -2203,7 +2203,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.PinmuxTargetCfg), line:53:40, endln:53:55 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/MultiConcatValueSize/dut.sv, line:52:1, endln:60:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/MultiConcatValueSize/dut.sv, line:52:1, endln:60:10 |vpiTypespec: \_struct_typespec: (pinmux_pkg::target_cfg_t), line:13:12, endln:13:18 |vpiParent: @@ -2303,7 +2303,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:53:40, endln:55:5 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/MultiConcatValueSize/dut.sv, line:52:1, endln:60:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/MultiConcatValueSize/dut.sv, line:52:1, endln:60:10 |vpiRhs: \_operation: , line:53:58, endln:55:5 |vpiParent: @@ -2423,7 +2423,7 @@ design: (work@top) |vpiPort: \_port: (o), line:52:23, endln:52:24 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/MultiConcatValueSize/dut.sv, line:52:1, endln:60:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/MultiConcatValueSize/dut.sv, line:52:1, endln:60:10 |vpiName:o |vpiDirection:2 |vpiLowConn: @@ -2438,17 +2438,17 @@ design: (work@top) \_int_typespec: , line:52:19, endln:52:22 |vpiSigned:1 |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/MultiConcatValueSize/dut.sv, line:52:1, endln:60:10 - |vpiModule: - \_module: work@sub_top (work@top.u_sub), file:${SURELOG_DIR}/tests/MultiConcatValueSize/dut.sv, line:57:4, endln:59:19 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/MultiConcatValueSize/dut.sv, line:52:1, endln:60:10 + |vpiModuleInst: + \_module_inst: work@sub_top (work@top.u_sub), file:${SURELOG_DIR}/tests/MultiConcatValueSize/dut.sv, line:57:4, endln:59:19 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/MultiConcatValueSize/dut.sv, line:52:1, endln:60:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/MultiConcatValueSize/dut.sv, line:52:1, endln:60:10 |vpiName:u_sub |vpiFullName:work@top.u_sub |vpiVariables: \_int_var: (work@top.u_sub.c), line:41:27, endln:41:28 |vpiParent: - \_module: work@sub_top (work@top.u_sub), file:${SURELOG_DIR}/tests/MultiConcatValueSize/dut.sv, line:57:4, endln:59:19 + \_module_inst: work@sub_top (work@top.u_sub), file:${SURELOG_DIR}/tests/MultiConcatValueSize/dut.sv, line:57:4, endln:59:19 |vpiTypespec: \_int_typespec: , line:41:23, endln:41:26 |vpiSigned:1 @@ -2459,7 +2459,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.u_sub.DefaultTargetCfg), line:17:27, endln:17:43 |vpiParent: - \_module: work@sub_top (work@top.u_sub), file:${SURELOG_DIR}/tests/MultiConcatValueSize/dut.sv, line:57:4, endln:59:19 + \_module_inst: work@sub_top (work@top.u_sub), file:${SURELOG_DIR}/tests/MultiConcatValueSize/dut.sv, line:57:4, endln:59:19 |vpiTypespec: \_struct_typespec: (pinmux_pkg::target_cfg_t), line:13:12, endln:13:18 |vpiParent: @@ -2559,7 +2559,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.u_sub.NDioPads), line:11:18, endln:11:26 |vpiParent: - \_module: work@sub_top (work@top.u_sub), file:${SURELOG_DIR}/tests/MultiConcatValueSize/dut.sv, line:57:4, endln:59:19 + \_module_inst: work@sub_top (work@top.u_sub), file:${SURELOG_DIR}/tests/MultiConcatValueSize/dut.sv, line:57:4, endln:59:19 |UINT:1 |vpiTypespec: \_int_typespec: , line:11:14, endln:11:17 @@ -2575,7 +2575,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.u_sub.TargetCfg), line:43:27, endln:43:36 |vpiParent: - \_module: work@sub_top (work@top.u_sub), file:${SURELOG_DIR}/tests/MultiConcatValueSize/dut.sv, line:57:4, endln:59:19 + \_module_inst: work@sub_top (work@top.u_sub), file:${SURELOG_DIR}/tests/MultiConcatValueSize/dut.sv, line:57:4, endln:59:19 |vpiTypespec: \_struct_typespec: (pinmux_pkg::target_cfg_t), line:13:12, endln:13:18 |vpiParent: @@ -2674,7 +2674,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:11:18, endln:11:30 |vpiParent: - \_module: work@sub_top (work@top.u_sub), file:${SURELOG_DIR}/tests/MultiConcatValueSize/dut.sv, line:57:4, endln:59:19 + \_module_inst: work@sub_top (work@top.u_sub), file:${SURELOG_DIR}/tests/MultiConcatValueSize/dut.sv, line:57:4, endln:59:19 |vpiRhs: \_constant: , line:11:29, endln:11:30 |vpiDecompile:1 @@ -2688,7 +2688,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:17:27, endln:19:5 |vpiParent: - \_module: work@sub_top (work@top.u_sub), file:${SURELOG_DIR}/tests/MultiConcatValueSize/dut.sv, line:57:4, endln:59:19 + \_module_inst: work@sub_top (work@top.u_sub), file:${SURELOG_DIR}/tests/MultiConcatValueSize/dut.sv, line:57:4, endln:59:19 |vpiRhs: \_operation: , line:17:46, endln:19:5 |vpiParent: @@ -2805,7 +2805,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:43:27, endln:43:55 |vpiParent: - \_module: work@sub_top (work@top.u_sub), file:${SURELOG_DIR}/tests/MultiConcatValueSize/dut.sv, line:57:4, endln:59:19 + \_module_inst: work@sub_top (work@top.u_sub), file:${SURELOG_DIR}/tests/MultiConcatValueSize/dut.sv, line:57:4, endln:59:19 |vpiOverriden:1 |vpiRhs: \_operation: , line:58:18, endln:58:33 @@ -2930,11 +2930,11 @@ design: (work@top) |vpiDefFile:${SURELOG_DIR}/tests/MultiConcatValueSize/dut.sv |vpiDefLineNo:41 |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/MultiConcatValueSize/dut.sv, line:52:1, endln:60:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/MultiConcatValueSize/dut.sv, line:52:1, endln:60:10 |vpiPort: \_port: (c), line:41:27, endln:41:28 |vpiParent: - \_module: work@sub_top (work@top.u_sub), file:${SURELOG_DIR}/tests/MultiConcatValueSize/dut.sv, line:57:4, endln:59:19 + \_module_inst: work@sub_top (work@top.u_sub), file:${SURELOG_DIR}/tests/MultiConcatValueSize/dut.sv, line:57:4, endln:59:19 |vpiName:c |vpiDirection:2 |vpiHighConn: @@ -2957,11 +2957,11 @@ design: (work@top) \_int_typespec: , line:41:23, endln:41:26 |vpiSigned:1 |vpiInstance: - \_module: work@sub_top (work@top.u_sub), file:${SURELOG_DIR}/tests/MultiConcatValueSize/dut.sv, line:57:4, endln:59:19 + \_module_inst: work@sub_top (work@top.u_sub), file:${SURELOG_DIR}/tests/MultiConcatValueSize/dut.sv, line:57:4, endln:59:19 |vpiGenScopeArray: \_gen_scope_array: (work@top.u_sub.gen_dio_attr[0]), line:45:41, endln:49:6 |vpiParent: - \_module: work@sub_top (work@top.u_sub), file:${SURELOG_DIR}/tests/MultiConcatValueSize/dut.sv, line:57:4, endln:59:19 + \_module_inst: work@sub_top (work@top.u_sub), file:${SURELOG_DIR}/tests/MultiConcatValueSize/dut.sv, line:57:4, endln:59:19 |vpiName:gen_dio_attr[0] |vpiFullName:work@top.u_sub.gen_dio_attr[0] |vpiGenScope: @@ -2979,8 +2979,8 @@ design: (work@top) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@top.u_sub.gen_dio_attr[0].k - |vpiModule: - \_module: work@prim_pad_attr (work@top.u_sub.gen_dio_attr[0].u_prim_pad_attr), file:${SURELOG_DIR}/tests/MultiConcatValueSize/dut.sv, line:46:6, endln:48:31 + |vpiModuleInst: + \_module_inst: work@prim_pad_attr (work@top.u_sub.gen_dio_attr[0].u_prim_pad_attr), file:${SURELOG_DIR}/tests/MultiConcatValueSize/dut.sv, line:46:6, endln:48:31 |vpiParent: \_gen_scope: (work@top.u_sub.gen_dio_attr[0]) |vpiName:u_prim_pad_attr @@ -2988,7 +2988,7 @@ design: (work@top) |vpiVariables: \_int_var: (work@top.u_sub.gen_dio_attr[0].u_prim_pad_attr.b), line:30:33, endln:30:34 |vpiParent: - \_module: work@prim_pad_attr (work@top.u_sub.gen_dio_attr[0].u_prim_pad_attr), file:${SURELOG_DIR}/tests/MultiConcatValueSize/dut.sv, line:46:6, endln:48:31 + \_module_inst: work@prim_pad_attr (work@top.u_sub.gen_dio_attr[0].u_prim_pad_attr), file:${SURELOG_DIR}/tests/MultiConcatValueSize/dut.sv, line:46:6, endln:48:31 |vpiTypespec: \_int_typespec: , line:30:29, endln:30:32 |vpiSigned:1 @@ -2997,7 +2997,7 @@ design: (work@top) |vpiSigned:1 |vpiVisibility:1 |vpiInstance: - \_module: work@prim_pad_attr (work@top.u_sub.gen_dio_attr[0].u_prim_pad_attr), file:${SURELOG_DIR}/tests/MultiConcatValueSize/dut.sv, line:46:6, endln:48:31 + \_module_inst: work@prim_pad_attr (work@top.u_sub.gen_dio_attr[0].u_prim_pad_attr), file:${SURELOG_DIR}/tests/MultiConcatValueSize/dut.sv, line:46:6, endln:48:31 |vpiParameter: \_parameter: (work@top.u_sub.gen_dio_attr[0].u_prim_pad_attr.PadType), line:32:25, endln:32:32 |vpiParent: @@ -3056,7 +3056,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:32:25, endln:32:36 |vpiParent: - \_module: work@prim_pad_attr (work@top.u_sub.gen_dio_attr[0].u_prim_pad_attr), file:${SURELOG_DIR}/tests/MultiConcatValueSize/dut.sv, line:46:6, endln:48:31 + \_module_inst: work@prim_pad_attr (work@top.u_sub.gen_dio_attr[0].u_prim_pad_attr), file:${SURELOG_DIR}/tests/MultiConcatValueSize/dut.sv, line:46:6, endln:48:31 |vpiOverriden:1 |vpiRhs: \_constant: , line:32:35, endln:32:36 @@ -3078,7 +3078,7 @@ design: (work@top) |vpiPort: \_port: (b), line:30:33, endln:30:34 |vpiParent: - \_module: work@prim_pad_attr (work@top.u_sub.gen_dio_attr[0].u_prim_pad_attr), file:${SURELOG_DIR}/tests/MultiConcatValueSize/dut.sv, line:46:6, endln:48:31 + \_module_inst: work@prim_pad_attr (work@top.u_sub.gen_dio_attr[0].u_prim_pad_attr), file:${SURELOG_DIR}/tests/MultiConcatValueSize/dut.sv, line:46:6, endln:48:31 |vpiName:b |vpiDirection:2 |vpiHighConn: @@ -3101,11 +3101,11 @@ design: (work@top) \_int_typespec: , line:30:29, endln:30:32 |vpiSigned:1 |vpiInstance: - \_module: work@prim_pad_attr (work@top.u_sub.gen_dio_attr[0].u_prim_pad_attr), file:${SURELOG_DIR}/tests/MultiConcatValueSize/dut.sv, line:46:6, endln:48:31 + \_module_inst: work@prim_pad_attr (work@top.u_sub.gen_dio_attr[0].u_prim_pad_attr), file:${SURELOG_DIR}/tests/MultiConcatValueSize/dut.sv, line:46:6, endln:48:31 |vpiGenScopeArray: \_gen_scope_array: (work@top.u_sub.gen_dio_attr[0].u_prim_pad_attr.gen_generic), line:34:4, endln:38:7 |vpiParent: - \_module: work@prim_pad_attr (work@top.u_sub.gen_dio_attr[0].u_prim_pad_attr), file:${SURELOG_DIR}/tests/MultiConcatValueSize/dut.sv, line:46:6, endln:48:31 + \_module_inst: work@prim_pad_attr (work@top.u_sub.gen_dio_attr[0].u_prim_pad_attr), file:${SURELOG_DIR}/tests/MultiConcatValueSize/dut.sv, line:46:6, endln:48:31 |vpiName:gen_generic |vpiFullName:work@top.u_sub.gen_dio_attr[0].u_prim_pad_attr.gen_generic |vpiGenScope: @@ -3113,8 +3113,8 @@ design: (work@top) |vpiParent: \_gen_scope_array: (work@top.u_sub.gen_dio_attr[0].u_prim_pad_attr.gen_generic), line:34:4, endln:38:7 |vpiFullName:work@top.u_sub.gen_dio_attr[0].u_prim_pad_attr.gen_generic - |vpiModule: - \_module: work@prim_generic_pad_attr (work@top.u_sub.gen_dio_attr[0].u_prim_pad_attr.gen_generic.u_impl_generic), file:${SURELOG_DIR}/tests/MultiConcatValueSize/dut.sv, line:35:7, endln:37:31 + |vpiModuleInst: + \_module_inst: work@prim_generic_pad_attr (work@top.u_sub.gen_dio_attr[0].u_prim_pad_attr.gen_generic.u_impl_generic), file:${SURELOG_DIR}/tests/MultiConcatValueSize/dut.sv, line:35:7, endln:37:31 |vpiParent: \_gen_scope: (work@top.u_sub.gen_dio_attr[0].u_prim_pad_attr.gen_generic) |vpiName:u_impl_generic @@ -3122,7 +3122,7 @@ design: (work@top) |vpiVariables: \_int_var: (work@top.u_sub.gen_dio_attr[0].u_prim_pad_attr.gen_generic.u_impl_generic.a), line:22:41, endln:22:42 |vpiParent: - \_module: work@prim_generic_pad_attr (work@top.u_sub.gen_dio_attr[0].u_prim_pad_attr.gen_generic.u_impl_generic), file:${SURELOG_DIR}/tests/MultiConcatValueSize/dut.sv, line:35:7, endln:37:31 + \_module_inst: work@prim_generic_pad_attr (work@top.u_sub.gen_dio_attr[0].u_prim_pad_attr.gen_generic.u_impl_generic), file:${SURELOG_DIR}/tests/MultiConcatValueSize/dut.sv, line:35:7, endln:37:31 |vpiTypespec: \_int_typespec: , line:22:37, endln:22:40 |vpiSigned:1 @@ -3131,7 +3131,7 @@ design: (work@top) |vpiSigned:1 |vpiVisibility:1 |vpiInstance: - \_module: work@prim_generic_pad_attr (work@top.u_sub.gen_dio_attr[0].u_prim_pad_attr.gen_generic.u_impl_generic), file:${SURELOG_DIR}/tests/MultiConcatValueSize/dut.sv, line:35:7, endln:37:31 + \_module_inst: work@prim_generic_pad_attr (work@top.u_sub.gen_dio_attr[0].u_prim_pad_attr.gen_generic.u_impl_generic), file:${SURELOG_DIR}/tests/MultiConcatValueSize/dut.sv, line:35:7, endln:37:31 |vpiParameter: \_parameter: (work@top.u_sub.gen_dio_attr[0].u_prim_pad_attr.gen_generic.u_impl_generic.PadType), line:24:25, endln:24:32 |vpiParent: @@ -3190,7 +3190,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:24:25, endln:24:36 |vpiParent: - \_module: work@prim_generic_pad_attr (work@top.u_sub.gen_dio_attr[0].u_prim_pad_attr.gen_generic.u_impl_generic), file:${SURELOG_DIR}/tests/MultiConcatValueSize/dut.sv, line:35:7, endln:37:31 + \_module_inst: work@prim_generic_pad_attr (work@top.u_sub.gen_dio_attr[0].u_prim_pad_attr.gen_generic.u_impl_generic), file:${SURELOG_DIR}/tests/MultiConcatValueSize/dut.sv, line:35:7, endln:37:31 |vpiOverriden:1 |vpiRhs: \_constant: , line:24:35, endln:24:36 @@ -3212,7 +3212,7 @@ design: (work@top) |vpiPort: \_port: (a), line:22:41, endln:22:42 |vpiParent: - \_module: work@prim_generic_pad_attr (work@top.u_sub.gen_dio_attr[0].u_prim_pad_attr.gen_generic.u_impl_generic), file:${SURELOG_DIR}/tests/MultiConcatValueSize/dut.sv, line:35:7, endln:37:31 + \_module_inst: work@prim_generic_pad_attr (work@top.u_sub.gen_dio_attr[0].u_prim_pad_attr.gen_generic.u_impl_generic), file:${SURELOG_DIR}/tests/MultiConcatValueSize/dut.sv, line:35:7, endln:37:31 |vpiName:a |vpiDirection:2 |vpiHighConn: @@ -3235,11 +3235,11 @@ design: (work@top) \_int_typespec: , line:22:37, endln:22:40 |vpiSigned:1 |vpiInstance: - \_module: work@prim_generic_pad_attr (work@top.u_sub.gen_dio_attr[0].u_prim_pad_attr.gen_generic.u_impl_generic), file:${SURELOG_DIR}/tests/MultiConcatValueSize/dut.sv, line:35:7, endln:37:31 + \_module_inst: work@prim_generic_pad_attr (work@top.u_sub.gen_dio_attr[0].u_prim_pad_attr.gen_generic.u_impl_generic), file:${SURELOG_DIR}/tests/MultiConcatValueSize/dut.sv, line:35:7, endln:37:31 |vpiGenScopeArray: \_gen_scope_array: (work@top.u_sub.gen_dio_attr[0].u_prim_pad_attr.gen_generic.u_impl_generic.gen_assign), line:25:4, endln:27:7 |vpiParent: - \_module: work@prim_generic_pad_attr (work@top.u_sub.gen_dio_attr[0].u_prim_pad_attr.gen_generic.u_impl_generic), file:${SURELOG_DIR}/tests/MultiConcatValueSize/dut.sv, line:35:7, endln:37:31 + \_module_inst: work@prim_generic_pad_attr (work@top.u_sub.gen_dio_attr[0].u_prim_pad_attr.gen_generic.u_impl_generic), file:${SURELOG_DIR}/tests/MultiConcatValueSize/dut.sv, line:35:7, endln:37:31 |vpiName:gen_assign |vpiFullName:work@top.u_sub.gen_dio_attr[0].u_prim_pad_attr.gen_generic.u_impl_generic.gen_assign |vpiGenScope: diff --git a/tests/MultiIndexBind/MultiIndexBind.log b/tests/MultiIndexBind/MultiIndexBind.log index e5b8433282..af82095fa5 100644 --- a/tests/MultiIndexBind/MultiIndexBind.log +++ b/tests/MultiIndexBind/MultiIndexBind.log @@ -193,7 +193,7 @@ enum_typespec 1 hier_path 1 logic_net 3 logic_typespec 1 -module 5 +module_inst 5 packed_array_typespec 1 packed_array_var 1 range 5 @@ -215,7 +215,7 @@ enum_typespec 1 hier_path 2 logic_net 3 logic_typespec 1 -module 5 +module_inst 5 packed_array_typespec 1 packed_array_var 1 range 5 @@ -238,17 +238,17 @@ design: (work@PreDecodeStage) |vpiElaborated:1 |vpiName:work@PreDecodeStage |uhdmallModules: -\_module: work@PreDecodeStage (work@PreDecodeStage), file:${SURELOG_DIR}/tests/MultiIndexBind/dut.sv, line:1:1, endln:30:10 +\_module_inst: work@PreDecodeStage (work@PreDecodeStage), file:${SURELOG_DIR}/tests/MultiIndexBind/dut.sv, line:1:1, endln:30:10 |vpiParent: \_design: (work@PreDecodeStage) |vpiFullName:work@PreDecodeStage |vpiTypedef: \_enum_typespec: (IntALU_Code), line:4:1, endln:7:15 |vpiParent: - \_module: work@PreDecodeStage (work@PreDecodeStage), file:${SURELOG_DIR}/tests/MultiIndexBind/dut.sv, line:1:1, endln:30:10 + \_module_inst: work@PreDecodeStage (work@PreDecodeStage), file:${SURELOG_DIR}/tests/MultiIndexBind/dut.sv, line:1:1, endln:30:10 |vpiName:IntALU_Code |vpiInstance: - \_module: work@PreDecodeStage (work@PreDecodeStage), file:${SURELOG_DIR}/tests/MultiIndexBind/dut.sv, line:1:1, endln:30:10 + \_module_inst: work@PreDecodeStage (work@PreDecodeStage), file:${SURELOG_DIR}/tests/MultiIndexBind/dut.sv, line:1:1, endln:30:10 |vpiBaseTypespec: \_logic_typespec: , line:4:14, endln:4:25 |vpiRange: @@ -278,10 +278,10 @@ design: (work@PreDecodeStage) |vpiTypedef: \_struct_typespec: (IntMicroOpOperand), line:9:9, endln:9:15 |vpiParent: - \_module: work@PreDecodeStage (work@PreDecodeStage), file:${SURELOG_DIR}/tests/MultiIndexBind/dut.sv, line:1:1, endln:30:10 + \_module_inst: work@PreDecodeStage (work@PreDecodeStage), file:${SURELOG_DIR}/tests/MultiIndexBind/dut.sv, line:1:1, endln:30:10 |vpiName:IntMicroOpOperand |vpiInstance: - \_module: work@PreDecodeStage (work@PreDecodeStage), file:${SURELOG_DIR}/tests/MultiIndexBind/dut.sv, line:1:1, endln:30:10 + \_module_inst: work@PreDecodeStage (work@PreDecodeStage), file:${SURELOG_DIR}/tests/MultiIndexBind/dut.sv, line:1:1, endln:30:10 |vpiPacked:1 |vpiTypespecMember: \_typespec_member: (aluCode), line:11:17, endln:11:24 @@ -298,10 +298,10 @@ design: (work@PreDecodeStage) |vpiTypedef: \_union_typespec: (MicroOpOperand), line:14:9, endln:14:14 |vpiParent: - \_module: work@PreDecodeStage (work@PreDecodeStage), file:${SURELOG_DIR}/tests/MultiIndexBind/dut.sv, line:1:1, endln:30:10 + \_module_inst: work@PreDecodeStage (work@PreDecodeStage), file:${SURELOG_DIR}/tests/MultiIndexBind/dut.sv, line:1:1, endln:30:10 |vpiName:MicroOpOperand |vpiInstance: - \_module: work@PreDecodeStage (work@PreDecodeStage), file:${SURELOG_DIR}/tests/MultiIndexBind/dut.sv, line:1:1, endln:30:10 + \_module_inst: work@PreDecodeStage (work@PreDecodeStage), file:${SURELOG_DIR}/tests/MultiIndexBind/dut.sv, line:1:1, endln:30:10 |vpiPacked:1 |vpiTypespecMember: \_typespec_member: (intOp), line:16:27, endln:16:32 @@ -318,10 +318,10 @@ design: (work@PreDecodeStage) |vpiTypedef: \_struct_typespec: (OpInfo), line:19:9, endln:19:15 |vpiParent: - \_module: work@PreDecodeStage (work@PreDecodeStage), file:${SURELOG_DIR}/tests/MultiIndexBind/dut.sv, line:1:1, endln:30:10 + \_module_inst: work@PreDecodeStage (work@PreDecodeStage), file:${SURELOG_DIR}/tests/MultiIndexBind/dut.sv, line:1:1, endln:30:10 |vpiName:OpInfo |vpiInstance: - \_module: work@PreDecodeStage (work@PreDecodeStage), file:${SURELOG_DIR}/tests/MultiIndexBind/dut.sv, line:1:1, endln:30:10 + \_module_inst: work@PreDecodeStage (work@PreDecodeStage), file:${SURELOG_DIR}/tests/MultiIndexBind/dut.sv, line:1:1, endln:30:10 |vpiPacked:1 |vpiTypespecMember: \_typespec_member: (operand), line:21:20, endln:21:27 @@ -339,13 +339,13 @@ design: (work@PreDecodeStage) |vpiNet: \_logic_net: (work@PreDecodeStage.microOps), line:26:19, endln:26:27 |vpiParent: - \_module: work@PreDecodeStage (work@PreDecodeStage), file:${SURELOG_DIR}/tests/MultiIndexBind/dut.sv, line:1:1, endln:30:10 + \_module_inst: work@PreDecodeStage (work@PreDecodeStage), file:${SURELOG_DIR}/tests/MultiIndexBind/dut.sv, line:1:1, endln:30:10 |vpiName:microOps |vpiFullName:work@PreDecodeStage.microOps |vpiContAssign: \_cont_assign: , line:28:8, endln:28:48 |vpiParent: - \_module: work@PreDecodeStage (work@PreDecodeStage), file:${SURELOG_DIR}/tests/MultiIndexBind/dut.sv, line:1:1, endln:30:10 + \_module_inst: work@PreDecodeStage (work@PreDecodeStage), file:${SURELOG_DIR}/tests/MultiIndexBind/dut.sv, line:1:1, endln:30:10 |vpiRhs: \_hier_path: (microOps[i][1].operand.intOp.aluCode), line:28:12, endln:28:48 |vpiParent: @@ -376,7 +376,7 @@ design: (work@PreDecodeStage) |vpiActual: \_packed_array_var: (work@PreDecodeStage.microOps), line:26:19, endln:26:27 |vpiParent: - \_module: work@PreDecodeStage (work@PreDecodeStage), file:${SURELOG_DIR}/tests/MultiIndexBind/dut.sv, line:1:1, endln:30:10 + \_module_inst: work@PreDecodeStage (work@PreDecodeStage), file:${SURELOG_DIR}/tests/MultiIndexBind/dut.sv, line:1:1, endln:30:10 |vpiName:microOps |vpiFullName:work@PreDecodeStage.microOps |vpiVisibility:1 @@ -445,7 +445,7 @@ design: (work@PreDecodeStage) |vpiActual: \_logic_net: (o) |uhdmtopModules: -\_module: work@PreDecodeStage (work@PreDecodeStage), file:${SURELOG_DIR}/tests/MultiIndexBind/dut.sv, line:1:1, endln:30:10 +\_module_inst: work@PreDecodeStage (work@PreDecodeStage), file:${SURELOG_DIR}/tests/MultiIndexBind/dut.sv, line:1:1, endln:30:10 |vpiName:work@PreDecodeStage |vpiVariables: \_packed_array_var: (work@PreDecodeStage.microOps), line:26:19, endln:26:27 @@ -471,7 +471,7 @@ design: (work@PreDecodeStage) |vpiContAssign: \_cont_assign: , line:28:8, endln:28:48 |vpiParent: - \_module: work@PreDecodeStage (work@PreDecodeStage), file:${SURELOG_DIR}/tests/MultiIndexBind/dut.sv, line:1:1, endln:30:10 + \_module_inst: work@PreDecodeStage (work@PreDecodeStage), file:${SURELOG_DIR}/tests/MultiIndexBind/dut.sv, line:1:1, endln:30:10 |vpiRhs: \_hier_path: (microOps[i][1].operand.intOp.aluCode), line:28:12, endln:28:48 |vpiParent: diff --git a/tests/MultiPort/MultiPort.log b/tests/MultiPort/MultiPort.log index 459c0b7b2f..883a296b49 100644 --- a/tests/MultiPort/MultiPort.log +++ b/tests/MultiPort/MultiPort.log @@ -97,7 +97,7 @@ import_typespec 1 int_typespec 2 logic_net 2 logic_typespec 2 -module 3 +module_inst 3 package 3 port 4 range 2 @@ -115,7 +115,7 @@ import_typespec 1 int_typespec 2 logic_net 2 logic_typespec 2 -module 3 +module_inst 3 package 3 port 6 range 2 @@ -212,7 +212,7 @@ design: (work@top) |vpiTypedef: \_struct_typespec: (my_pkg::variable_type), line:2:13, endln:2:19 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/MultiPort/dut.sv, line:7:1, endln:11:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/MultiPort/dut.sv, line:7:1, endln:11:10 |vpiName:my_pkg::variable_type |vpiInstance: \_package: my_pkg (my_pkg::), file:${SURELOG_DIR}/tests/MultiPort/dut.sv, line:1:1, endln:6:11 @@ -272,7 +272,7 @@ design: (work@top) |vpiDefName:my_pkg |vpiTop:1 |uhdmallModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/MultiPort/dut.sv, line:7:1, endln:11:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/MultiPort/dut.sv, line:7:1, endln:11:10 |vpiParent: \_design: (work@top) |vpiFullName:work@top @@ -284,19 +284,19 @@ design: (work@top) |vpiNet: \_logic_net: (work@top.a), line:9:25, endln:9:26 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/MultiPort/dut.sv, line:7:1, endln:11:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/MultiPort/dut.sv, line:7:1, endln:11:10 |vpiName:a |vpiFullName:work@top.a |vpiNet: \_logic_net: (work@top.b), line:9:28, endln:9:29 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/MultiPort/dut.sv, line:7:1, endln:11:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/MultiPort/dut.sv, line:7:1, endln:11:10 |vpiName:b |vpiFullName:work@top.b |vpiPort: \_port: (a), line:9:25, endln:9:26 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/MultiPort/dut.sv, line:7:1, endln:11:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/MultiPort/dut.sv, line:7:1, endln:11:10 |vpiName:a |vpiDirection:1 |vpiLowConn: @@ -308,7 +308,7 @@ design: (work@top) |vpiPort: \_port: (b), line:9:28, endln:9:29 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/MultiPort/dut.sv, line:7:1, endln:11:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/MultiPort/dut.sv, line:7:1, endln:11:10 |vpiName:b |vpiDirection:1 |vpiLowConn: @@ -318,12 +318,12 @@ design: (work@top) |vpiTypedef: \_struct_typespec: (my_pkg::variable_type), line:2:13, endln:2:19 |uhdmtopModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/MultiPort/dut.sv, line:7:1, endln:11:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/MultiPort/dut.sv, line:7:1, endln:11:10 |vpiName:work@top |vpiVariables: \_struct_var: (work@top.a), line:9:25, endln:9:26 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/MultiPort/dut.sv, line:7:1, endln:11:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/MultiPort/dut.sv, line:7:1, endln:11:10 |vpiTypespec: \_struct_typespec: (my_pkg::variable_type), line:2:13, endln:2:19 |vpiName:a @@ -332,7 +332,7 @@ design: (work@top) |vpiVariables: \_struct_var: (work@top.b), line:9:28, endln:9:29 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/MultiPort/dut.sv, line:7:1, endln:11:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/MultiPort/dut.sv, line:7:1, endln:11:10 |vpiTypespec: \_struct_typespec: (my_pkg::variable_type), line:2:13, endln:2:19 |vpiName:b @@ -348,7 +348,7 @@ design: (work@top) |vpiPort: \_port: (a), line:9:25, endln:9:26 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/MultiPort/dut.sv, line:7:1, endln:11:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/MultiPort/dut.sv, line:7:1, endln:11:10 |vpiName:a |vpiDirection:1 |vpiLowConn: @@ -362,11 +362,11 @@ design: (work@top) |vpiTypedef: \_struct_typespec: (my_pkg::variable_type), line:2:13, endln:2:19 |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/MultiPort/dut.sv, line:7:1, endln:11:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/MultiPort/dut.sv, line:7:1, endln:11:10 |vpiPort: \_port: (b), line:9:28, endln:9:29 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/MultiPort/dut.sv, line:7:1, endln:11:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/MultiPort/dut.sv, line:7:1, endln:11:10 |vpiName:b |vpiDirection:1 |vpiLowConn: @@ -380,7 +380,7 @@ design: (work@top) |vpiTypedef: \_struct_typespec: (my_pkg::variable_type), line:2:13, endln:2:19 |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/MultiPort/dut.sv, line:7:1, endln:11:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/MultiPort/dut.sv, line:7:1, endln:11:10 =================== [ FATAL] : 0 [ SYNTAX] : 0 diff --git a/tests/MultiSelect/MultiSelect.log b/tests/MultiSelect/MultiSelect.log index 6d2559fa45..496256bd63 100644 --- a/tests/MultiSelect/MultiSelect.log +++ b/tests/MultiSelect/MultiSelect.log @@ -29,7 +29,7 @@ design 1 logic_net 2 logic_typespec 2 logic_var 2 -module 4 +module_inst 4 range 4 ref_obj 2 var_select 8 @@ -45,7 +45,7 @@ design 1 logic_net 2 logic_typespec 2 logic_var 2 -module 4 +module_inst 4 range 4 ref_obj 4 var_select 12 @@ -63,7 +63,7 @@ design: (work@top) |vpiElaborated:1 |vpiName:work@top |uhdmallModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/MultiSelect/dut.sv, line:1:1, endln:11:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/MultiSelect/dut.sv, line:1:1, endln:11:10 |vpiParent: \_design: (work@top) |vpiFullName:work@top @@ -71,21 +71,21 @@ design: (work@top) |vpiNet: \_logic_net: (work@top.a), line:2:8, endln:2:9 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/MultiSelect/dut.sv, line:1:1, endln:11:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/MultiSelect/dut.sv, line:1:1, endln:11:10 |vpiName:a |vpiFullName:work@top.a |vpiNetType:36 |vpiNet: \_logic_net: (work@top.b), line:3:8, endln:3:9 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/MultiSelect/dut.sv, line:1:1, endln:11:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/MultiSelect/dut.sv, line:1:1, endln:11:10 |vpiName:b |vpiFullName:work@top.b |vpiNetType:36 |vpiContAssign: \_cont_assign: , line:5:9, endln:5:23 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/MultiSelect/dut.sv, line:1:1, endln:11:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/MultiSelect/dut.sv, line:1:1, endln:11:10 |vpiRhs: \_constant: , line:5:19, endln:5:23 |vpiParent: @@ -119,7 +119,7 @@ design: (work@top) |vpiContAssign: \_cont_assign: , line:6:9, endln:6:23 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/MultiSelect/dut.sv, line:1:1, endln:11:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/MultiSelect/dut.sv, line:1:1, endln:11:10 |vpiRhs: \_constant: , line:6:19, endln:6:23 |vpiParent: @@ -153,7 +153,7 @@ design: (work@top) |vpiContAssign: \_cont_assign: , line:7:9, endln:7:23 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/MultiSelect/dut.sv, line:1:1, endln:11:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/MultiSelect/dut.sv, line:1:1, endln:11:10 |vpiRhs: \_constant: , line:7:19, endln:7:23 |vpiParent: @@ -187,7 +187,7 @@ design: (work@top) |vpiContAssign: \_cont_assign: , line:8:9, endln:8:23 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/MultiSelect/dut.sv, line:1:1, endln:11:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/MultiSelect/dut.sv, line:1:1, endln:11:10 |vpiRhs: \_constant: , line:8:19, endln:8:23 |vpiParent: @@ -221,7 +221,7 @@ design: (work@top) |vpiContAssign: \_cont_assign: , line:10:9, endln:10:14 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/MultiSelect/dut.sv, line:1:1, endln:11:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/MultiSelect/dut.sv, line:1:1, endln:11:10 |vpiRhs: \_ref_obj: (work@top.a), line:10:13, endln:10:14 |vpiParent: @@ -239,12 +239,12 @@ design: (work@top) |vpiActual: \_array_var: (work@top.b), line:3:8, endln:3:15 |uhdmtopModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/MultiSelect/dut.sv, line:1:1, endln:11:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/MultiSelect/dut.sv, line:1:1, endln:11:10 |vpiName:work@top |vpiVariables: \_array_var: (work@top.a), line:2:8, endln:2:15 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/MultiSelect/dut.sv, line:1:1, endln:11:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/MultiSelect/dut.sv, line:1:1, endln:11:10 |vpiSize:4 |vpiTypespec: \_array_typespec: @@ -299,7 +299,7 @@ design: (work@top) |vpiVariables: \_array_var: (work@top.b), line:3:8, endln:3:15 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/MultiSelect/dut.sv, line:1:1, endln:11:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/MultiSelect/dut.sv, line:1:1, endln:11:10 |vpiSize:4 |vpiTypespec: \_array_typespec: @@ -357,7 +357,7 @@ design: (work@top) |vpiContAssign: \_cont_assign: , line:5:9, endln:5:23 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/MultiSelect/dut.sv, line:1:1, endln:11:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/MultiSelect/dut.sv, line:1:1, endln:11:10 |vpiRhs: \_constant: , line:5:19, endln:5:23 |vpiLhs: @@ -385,7 +385,7 @@ design: (work@top) |vpiContAssign: \_cont_assign: , line:6:9, endln:6:23 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/MultiSelect/dut.sv, line:1:1, endln:11:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/MultiSelect/dut.sv, line:1:1, endln:11:10 |vpiRhs: \_constant: , line:6:19, endln:6:23 |vpiLhs: @@ -413,7 +413,7 @@ design: (work@top) |vpiContAssign: \_cont_assign: , line:7:9, endln:7:23 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/MultiSelect/dut.sv, line:1:1, endln:11:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/MultiSelect/dut.sv, line:1:1, endln:11:10 |vpiRhs: \_constant: , line:7:19, endln:7:23 |vpiLhs: @@ -441,7 +441,7 @@ design: (work@top) |vpiContAssign: \_cont_assign: , line:8:9, endln:8:23 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/MultiSelect/dut.sv, line:1:1, endln:11:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/MultiSelect/dut.sv, line:1:1, endln:11:10 |vpiRhs: \_constant: , line:8:19, endln:8:23 |vpiLhs: @@ -469,7 +469,7 @@ design: (work@top) |vpiContAssign: \_cont_assign: , line:10:9, endln:10:14 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/MultiSelect/dut.sv, line:1:1, endln:11:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/MultiSelect/dut.sv, line:1:1, endln:11:10 |vpiRhs: \_ref_obj: (work@top.a), line:10:13, endln:10:14 |vpiParent: diff --git a/tests/NameCollisionBind/NameCollisionBind.log b/tests/NameCollisionBind/NameCollisionBind.log index 3f24fc0198..8ad4332135 100644 --- a/tests/NameCollisionBind/NameCollisionBind.log +++ b/tests/NameCollisionBind/NameCollisionBind.log @@ -118,12 +118,12 @@ cont_assign 1 design 1 hier_path 1 int_typespec 2 -interface 2 +interface_inst 2 interface_typespec 6 io_decl 2 logic_net 3 modport 2 -module 3 +module_inst 3 port 2 ref_obj 6 struct_typespec 1 @@ -137,12 +137,12 @@ cont_assign 2 design 1 hier_path 2 int_typespec 2 -interface 2 +interface_inst 2 interface_typespec 6 io_decl 2 logic_net 3 modport 2 -module 3 +module_inst 3 port 3 ref_obj 11 struct_typespec 1 @@ -162,7 +162,7 @@ design: (work@CSR_Unit) |vpiElaborated:1 |vpiName:work@CSR_Unit |uhdmallInterfaces: -\_interface: work@PerformanceCounterIF (work@PerformanceCounterIF), file:${SURELOG_DIR}/tests/NameCollisionBind/dut.sv, line:11:1, endln:18:13 +\_interface_inst: work@PerformanceCounterIF (work@PerformanceCounterIF), file:${SURELOG_DIR}/tests/NameCollisionBind/dut.sv, line:11:1, endln:18:13 |vpiParent: \_design: (work@CSR_Unit) |vpiFullName:work@PerformanceCounterIF @@ -170,20 +170,20 @@ design: (work@CSR_Unit) |vpiNet: \_logic_net: (work@PerformanceCounterIF.perfCounter), line:13:21, endln:13:32 |vpiParent: - \_interface: work@PerformanceCounterIF (work@PerformanceCounterIF), file:${SURELOG_DIR}/tests/NameCollisionBind/dut.sv, line:11:1, endln:18:13 + \_interface_inst: work@PerformanceCounterIF (work@PerformanceCounterIF), file:${SURELOG_DIR}/tests/NameCollisionBind/dut.sv, line:11:1, endln:18:13 |vpiName:perfCounter |vpiFullName:work@PerformanceCounterIF.perfCounter |vpiModport: \_modport: (CSR), line:14:13, endln:14:16 |vpiParent: - \_interface: work@PerformanceCounterIF (work@PerformanceCounterIF), file:${SURELOG_DIR}/tests/NameCollisionBind/dut.sv, line:11:1, endln:18:13 + \_interface_inst: work@PerformanceCounterIF (work@PerformanceCounterIF), file:${SURELOG_DIR}/tests/NameCollisionBind/dut.sv, line:11:1, endln:18:13 |vpiName:CSR |vpiIODecl: \_io_decl: (perfCounter), line:16:5, endln:16:16 |vpiDirection:1 |vpiName:perfCounter |uhdmallModules: -\_module: work@CSR_Unit (work@CSR_Unit), file:${SURELOG_DIR}/tests/NameCollisionBind/dut.sv, line:20:1, endln:27:10 +\_module_inst: work@CSR_Unit (work@CSR_Unit), file:${SURELOG_DIR}/tests/NameCollisionBind/dut.sv, line:20:1, endln:27:10 |vpiParent: \_design: (work@CSR_Unit) |vpiFullName:work@CSR_Unit @@ -191,13 +191,13 @@ design: (work@CSR_Unit) |vpiNet: \_logic_net: (work@CSR_Unit.perfCounter), line:21:30, endln:21:41 |vpiParent: - \_module: work@CSR_Unit (work@CSR_Unit), file:${SURELOG_DIR}/tests/NameCollisionBind/dut.sv, line:20:1, endln:27:10 + \_module_inst: work@CSR_Unit (work@CSR_Unit), file:${SURELOG_DIR}/tests/NameCollisionBind/dut.sv, line:20:1, endln:27:10 |vpiName:perfCounter |vpiFullName:work@CSR_Unit.perfCounter |vpiPort: \_port: (perfCounter), line:21:30, endln:21:41 |vpiParent: - \_module: work@CSR_Unit (work@CSR_Unit), file:${SURELOG_DIR}/tests/NameCollisionBind/dut.sv, line:20:1, endln:27:10 + \_module_inst: work@CSR_Unit (work@CSR_Unit), file:${SURELOG_DIR}/tests/NameCollisionBind/dut.sv, line:20:1, endln:27:10 |vpiName:perfCounter |vpiDirection:3 |vpiLowConn: @@ -213,7 +213,7 @@ design: (work@CSR_Unit) |vpiContAssign: \_cont_assign: , line:25:9, endln:25:53 |vpiParent: - \_module: work@CSR_Unit (work@CSR_Unit), file:${SURELOG_DIR}/tests/NameCollisionBind/dut.sv, line:20:1, endln:27:10 + \_module_inst: work@CSR_Unit (work@CSR_Unit), file:${SURELOG_DIR}/tests/NameCollisionBind/dut.sv, line:20:1, endln:27:10 |vpiRhs: \_hier_path: (perfCounter.perfCounter.numLoadMiss), line:25:18, endln:25:53 |vpiParent: @@ -275,7 +275,7 @@ design: (work@CSR_Unit) |vpiRefEndLineNo:6 |vpiRefEndColumnNo:9 |uhdmtopModules: -\_module: work@CSR_Unit (work@CSR_Unit), file:${SURELOG_DIR}/tests/NameCollisionBind/dut.sv, line:20:1, endln:27:10 +\_module_inst: work@CSR_Unit (work@CSR_Unit), file:${SURELOG_DIR}/tests/NameCollisionBind/dut.sv, line:20:1, endln:27:10 |vpiName:work@CSR_Unit |vpiDefName:work@CSR_Unit |vpiTop:1 @@ -287,7 +287,7 @@ design: (work@CSR_Unit) |vpiPort: \_port: (perfCounter), line:21:30, endln:21:41 |vpiParent: - \_module: work@CSR_Unit (work@CSR_Unit), file:${SURELOG_DIR}/tests/NameCollisionBind/dut.sv, line:20:1, endln:27:10 + \_module_inst: work@CSR_Unit (work@CSR_Unit), file:${SURELOG_DIR}/tests/NameCollisionBind/dut.sv, line:20:1, endln:27:10 |vpiName:perfCounter |vpiDirection:3 |vpiLowConn: @@ -304,18 +304,18 @@ design: (work@CSR_Unit) |vpiName:CSR |vpiIsModPort:1 |vpiInstance: - \_module: work@CSR_Unit (work@CSR_Unit), file:${SURELOG_DIR}/tests/NameCollisionBind/dut.sv, line:20:1, endln:27:10 - |vpiInterface: - \_interface: work@PerformanceCounterIF (work@CSR_Unit.perfCounter), file:${SURELOG_DIR}/tests/NameCollisionBind/dut.sv, line:20:0 + \_module_inst: work@CSR_Unit (work@CSR_Unit), file:${SURELOG_DIR}/tests/NameCollisionBind/dut.sv, line:20:1, endln:27:10 + |vpiInterfaceInst: + \_interface_inst: work@PerformanceCounterIF (work@CSR_Unit.perfCounter), file:${SURELOG_DIR}/tests/NameCollisionBind/dut.sv, line:20:0 |vpiParent: - \_module: work@CSR_Unit (work@CSR_Unit), file:${SURELOG_DIR}/tests/NameCollisionBind/dut.sv, line:20:1, endln:27:10 + \_module_inst: work@CSR_Unit (work@CSR_Unit), file:${SURELOG_DIR}/tests/NameCollisionBind/dut.sv, line:20:1, endln:27:10 |vpiName:perfCounter |vpiFullName:work@CSR_Unit.perfCounter |vpiDefName:work@PerformanceCounterIF |vpiModport: \_modport: (CSR), line:14:13, endln:14:16 |vpiParent: - \_interface: work@PerformanceCounterIF (work@CSR_Unit.perfCounter), file:${SURELOG_DIR}/tests/NameCollisionBind/dut.sv, line:20:0 + \_interface_inst: work@PerformanceCounterIF (work@CSR_Unit.perfCounter), file:${SURELOG_DIR}/tests/NameCollisionBind/dut.sv, line:20:0 |vpiName:CSR |vpiIODecl: \_io_decl: (perfCounter), line:16:5, endln:16:16 @@ -327,12 +327,12 @@ design: (work@CSR_Unit) \_struct_typespec: (PerfCounterPath), line:4:9, endln:4:15 |vpiName:perfCounter |vpiVisibility:1 - |vpiInterface: - \_interface: work@PerformanceCounterIF (work@CSR_Unit.perfCounter), file:${SURELOG_DIR}/tests/NameCollisionBind/dut.sv, line:20:0 + |vpiInterfaceInst: + \_interface_inst: work@PerformanceCounterIF (work@CSR_Unit.perfCounter), file:${SURELOG_DIR}/tests/NameCollisionBind/dut.sv, line:20:0 |vpiContAssign: \_cont_assign: , line:25:9, endln:25:53 |vpiParent: - \_module: work@CSR_Unit (work@CSR_Unit), file:${SURELOG_DIR}/tests/NameCollisionBind/dut.sv, line:20:1, endln:27:10 + \_module_inst: work@CSR_Unit (work@CSR_Unit), file:${SURELOG_DIR}/tests/NameCollisionBind/dut.sv, line:20:1, endln:27:10 |vpiRhs: \_hier_path: (perfCounter.perfCounter.numLoadMiss), line:25:18, endln:25:53 |vpiParent: @@ -344,7 +344,7 @@ design: (work@CSR_Unit) \_hier_path: (perfCounter.perfCounter.numLoadMiss), line:25:18, endln:25:53 |vpiName:perfCounter |vpiActual: - \_interface: work@PerformanceCounterIF (work@CSR_Unit.perfCounter), file:${SURELOG_DIR}/tests/NameCollisionBind/dut.sv, line:20:0 + \_interface_inst: work@PerformanceCounterIF (work@CSR_Unit.perfCounter), file:${SURELOG_DIR}/tests/NameCollisionBind/dut.sv, line:20:0 |vpiActual: \_ref_obj: (perfCounter), line:25:30, endln:25:41 |vpiParent: diff --git a/tests/NegInt/NegInt.log b/tests/NegInt/NegInt.log index 3a01514961..b2d0de0c81 100644 --- a/tests/NegInt/NegInt.log +++ b/tests/NegInt/NegInt.log @@ -133,7 +133,7 @@ n<> u<106> t c<1> l<1:1> el<7:1> constant 8 design 1 int_typespec 3 -module 4 +module_inst 4 operation 3 param_assign 2 parameter 2 @@ -144,7 +144,7 @@ parameter 2 constant 8 design 1 int_typespec 3 -module 4 +module_inst 4 operation 3 param_assign 2 parameter 2 @@ -162,14 +162,14 @@ design: (work@find_first_one) |vpiElaborated:1 |vpiName:work@find_first_one |uhdmallModules: -\_module: work@find_first_one (work@find_first_one), file:${SURELOG_DIR}/tests/NegInt/dut.sv, line:1:1, endln:5:10 +\_module_inst: work@find_first_one (work@find_first_one), file:${SURELOG_DIR}/tests/NegInt/dut.sv, line:1:1, endln:5:10 |vpiParent: \_design: (work@find_first_one) |vpiFullName:work@find_first_one |vpiParameter: \_parameter: (work@find_first_one.WIDTH), line:1:40, endln:1:45 |vpiParent: - \_module: work@find_first_one (work@find_first_one), file:${SURELOG_DIR}/tests/NegInt/dut.sv, line:1:1, endln:5:10 + \_module_inst: work@find_first_one (work@find_first_one), file:${SURELOG_DIR}/tests/NegInt/dut.sv, line:1:1, endln:5:10 |vpiTypespec: \_int_typespec: , line:1:36, endln:1:39 |vpiParent: @@ -181,7 +181,7 @@ design: (work@find_first_one) |vpiParamAssign: \_param_assign: , line:1:40, endln:1:50 |vpiParent: - \_module: work@find_first_one (work@find_first_one), file:${SURELOG_DIR}/tests/NegInt/dut.sv, line:1:1, endln:5:10 + \_module_inst: work@find_first_one (work@find_first_one), file:${SURELOG_DIR}/tests/NegInt/dut.sv, line:1:1, endln:5:10 |vpiRhs: \_operation: , line:1:48, endln:1:50 |vpiOpType:1 @@ -195,12 +195,12 @@ design: (work@find_first_one) \_parameter: (work@find_first_one.WIDTH), line:1:40, endln:1:45 |vpiDefName:work@find_first_one |uhdmtopModules: -\_module: work@find_first_one (work@find_first_one), file:${SURELOG_DIR}/tests/NegInt/dut.sv, line:1:1, endln:5:10 +\_module_inst: work@find_first_one (work@find_first_one), file:${SURELOG_DIR}/tests/NegInt/dut.sv, line:1:1, endln:5:10 |vpiName:work@find_first_one |vpiParameter: \_parameter: (work@find_first_one.WIDTH), line:1:40, endln:1:45 |vpiParent: - \_module: work@find_first_one (work@find_first_one), file:${SURELOG_DIR}/tests/NegInt/dut.sv, line:1:1, endln:5:10 + \_module_inst: work@find_first_one (work@find_first_one), file:${SURELOG_DIR}/tests/NegInt/dut.sv, line:1:1, endln:5:10 |vpiTypespec: \_int_typespec: , line:1:36, endln:1:39 |vpiParent: @@ -212,7 +212,7 @@ design: (work@find_first_one) |vpiParamAssign: \_param_assign: , line:1:40, endln:1:50 |vpiParent: - \_module: work@find_first_one (work@find_first_one), file:${SURELOG_DIR}/tests/NegInt/dut.sv, line:1:1, endln:5:10 + \_module_inst: work@find_first_one (work@find_first_one), file:${SURELOG_DIR}/tests/NegInt/dut.sv, line:1:1, endln:5:10 |vpiRhs: \_constant: , line:1:48, endln:1:50 |vpiDecompile:-1 diff --git a/tests/NegParam/NegParam.log b/tests/NegParam/NegParam.log index 0b2d45aba6..50fac41109 100644 --- a/tests/NegParam/NegParam.log +++ b/tests/NegParam/NegParam.log @@ -349,7 +349,7 @@ int_typespec 31 logic_net 3 logic_typespec 2 logic_var 3 -module 9 +module_inst 9 operation 21 param_assign 18 parameter 19 @@ -369,7 +369,7 @@ int_typespec 31 logic_net 3 logic_typespec 2 logic_var 3 -module 9 +module_inst 9 operation 21 param_assign 18 parameter 19 @@ -393,14 +393,14 @@ design: (work@top) |vpiElaborated:1 |vpiName:work@top |uhdmallModules: -\_module: work@prim_packer (work@prim_packer), file:${SURELOG_DIR}/tests/NegParam/dut.sv, line:11:1, endln:31:10 +\_module_inst: work@prim_packer (work@prim_packer), file:${SURELOG_DIR}/tests/NegParam/dut.sv, line:11:1, endln:31:10 |vpiParent: \_design: (work@top) |vpiFullName:work@prim_packer |vpiParameter: \_parameter: (work@prim_packer.InW), line:12:17, endln:12:20 |vpiParent: - \_module: work@prim_packer (work@prim_packer), file:${SURELOG_DIR}/tests/NegParam/dut.sv, line:11:1, endln:31:10 + \_module_inst: work@prim_packer (work@prim_packer), file:${SURELOG_DIR}/tests/NegParam/dut.sv, line:11:1, endln:31:10 |UINT:32 |vpiTypespec: \_int_typespec: , line:12:13, endln:12:16 @@ -413,7 +413,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@prim_packer.OutW), line:13:17, endln:13:21 |vpiParent: - \_module: work@prim_packer (work@prim_packer), file:${SURELOG_DIR}/tests/NegParam/dut.sv, line:11:1, endln:31:10 + \_module_inst: work@prim_packer (work@prim_packer), file:${SURELOG_DIR}/tests/NegParam/dut.sv, line:11:1, endln:31:10 |UINT:32 |vpiTypespec: \_int_typespec: , line:13:13, endln:13:16 @@ -426,7 +426,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@prim_packer.HintByteData), line:14:17, endln:14:29 |vpiParent: - \_module: work@prim_packer (work@prim_packer), file:${SURELOG_DIR}/tests/NegParam/dut.sv, line:11:1, endln:31:10 + \_module_inst: work@prim_packer (work@prim_packer), file:${SURELOG_DIR}/tests/NegParam/dut.sv, line:11:1, endln:31:10 |UINT:0 |vpiTypespec: \_int_typespec: , line:14:13, endln:14:16 @@ -439,7 +439,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@prim_packer.Width), line:18:18, endln:18:23 |vpiParent: - \_module: work@prim_packer (work@prim_packer), file:${SURELOG_DIR}/tests/NegParam/dut.sv, line:11:1, endln:31:10 + \_module_inst: work@prim_packer (work@prim_packer), file:${SURELOG_DIR}/tests/NegParam/dut.sv, line:11:1, endln:31:10 |vpiTypespec: \_int_typespec: , line:18:14, endln:18:17 |vpiParent: @@ -452,7 +452,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@prim_packer.ConcatW), line:19:18, endln:19:25 |vpiParent: - \_module: work@prim_packer (work@prim_packer), file:${SURELOG_DIR}/tests/NegParam/dut.sv, line:11:1, endln:31:10 + \_module_inst: work@prim_packer (work@prim_packer), file:${SURELOG_DIR}/tests/NegParam/dut.sv, line:11:1, endln:31:10 |vpiTypespec: \_int_typespec: , line:19:14, endln:19:17 |vpiParent: @@ -465,7 +465,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@prim_packer.PtrW), line:20:18, endln:20:22 |vpiParent: - \_module: work@prim_packer (work@prim_packer), file:${SURELOG_DIR}/tests/NegParam/dut.sv, line:11:1, endln:31:10 + \_module_inst: work@prim_packer (work@prim_packer), file:${SURELOG_DIR}/tests/NegParam/dut.sv, line:11:1, endln:31:10 |vpiTypespec: \_int_typespec: , line:20:14, endln:20:17 |vpiParent: @@ -478,7 +478,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@prim_packer.IdxW), line:21:18, endln:21:22 |vpiParent: - \_module: work@prim_packer (work@prim_packer), file:${SURELOG_DIR}/tests/NegParam/dut.sv, line:11:1, endln:31:10 + \_module_inst: work@prim_packer (work@prim_packer), file:${SURELOG_DIR}/tests/NegParam/dut.sv, line:11:1, endln:31:10 |vpiTypespec: \_int_typespec: , line:21:14, endln:21:17 |vpiParent: @@ -491,7 +491,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:12:17, endln:12:26 |vpiParent: - \_module: work@prim_packer (work@prim_packer), file:${SURELOG_DIR}/tests/NegParam/dut.sv, line:11:1, endln:31:10 + \_module_inst: work@prim_packer (work@prim_packer), file:${SURELOG_DIR}/tests/NegParam/dut.sv, line:11:1, endln:31:10 |vpiRhs: \_constant: , line:12:24, endln:12:26 |vpiDecompile:32 @@ -505,7 +505,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:13:17, endln:13:26 |vpiParent: - \_module: work@prim_packer (work@prim_packer), file:${SURELOG_DIR}/tests/NegParam/dut.sv, line:11:1, endln:31:10 + \_module_inst: work@prim_packer (work@prim_packer), file:${SURELOG_DIR}/tests/NegParam/dut.sv, line:11:1, endln:31:10 |vpiRhs: \_constant: , line:13:24, endln:13:26 |vpiDecompile:32 @@ -519,7 +519,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:14:17, endln:14:33 |vpiParent: - \_module: work@prim_packer (work@prim_packer), file:${SURELOG_DIR}/tests/NegParam/dut.sv, line:11:1, endln:31:10 + \_module_inst: work@prim_packer (work@prim_packer), file:${SURELOG_DIR}/tests/NegParam/dut.sv, line:11:1, endln:31:10 |vpiRhs: \_constant: , line:14:32, endln:14:33 |vpiDecompile:0 @@ -533,7 +533,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:18:18, endln:18:36 |vpiParent: - \_module: work@prim_packer (work@prim_packer), file:${SURELOG_DIR}/tests/NegParam/dut.sv, line:11:1, endln:31:10 + \_module_inst: work@prim_packer (work@prim_packer), file:${SURELOG_DIR}/tests/NegParam/dut.sv, line:11:1, endln:31:10 |vpiRhs: \_operation: , line:18:26, endln:18:36 |vpiOpType:24 @@ -552,7 +552,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:19:18, endln:19:39 |vpiParent: - \_module: work@prim_packer (work@prim_packer), file:${SURELOG_DIR}/tests/NegParam/dut.sv, line:11:1, endln:31:10 + \_module_inst: work@prim_packer (work@prim_packer), file:${SURELOG_DIR}/tests/NegParam/dut.sv, line:11:1, endln:31:10 |vpiRhs: \_operation: , line:19:28, endln:19:39 |vpiOpType:24 @@ -571,7 +571,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:20:18, endln:20:42 |vpiParent: - \_module: work@prim_packer (work@prim_packer), file:${SURELOG_DIR}/tests/NegParam/dut.sv, line:11:1, endln:31:10 + \_module_inst: work@prim_packer (work@prim_packer), file:${SURELOG_DIR}/tests/NegParam/dut.sv, line:11:1, endln:31:10 |vpiRhs: \_sys_func_call: ($clog2), line:20:25, endln:20:42 |vpiArgument: @@ -598,7 +598,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:21:18, endln:21:52 |vpiParent: - \_module: work@prim_packer (work@prim_packer), file:${SURELOG_DIR}/tests/NegParam/dut.sv, line:11:1, endln:31:10 + \_module_inst: work@prim_packer (work@prim_packer), file:${SURELOG_DIR}/tests/NegParam/dut.sv, line:11:1, endln:31:10 |vpiRhs: \_operation: , line:21:25, endln:21:52 |vpiOpType:24 @@ -631,33 +631,33 @@ design: (work@top) |vpiNet: \_logic_net: (work@prim_packer.pos), line:22:29, endln:22:32 |vpiParent: - \_module: work@prim_packer (work@prim_packer), file:${SURELOG_DIR}/tests/NegParam/dut.sv, line:11:1, endln:31:10 + \_module_inst: work@prim_packer (work@prim_packer), file:${SURELOG_DIR}/tests/NegParam/dut.sv, line:11:1, endln:31:10 |vpiName:pos |vpiFullName:work@prim_packer.pos |vpiNetType:36 |vpiNet: \_logic_net: (work@prim_packer.pos_next), line:22:34, endln:22:42 |vpiParent: - \_module: work@prim_packer (work@prim_packer), file:${SURELOG_DIR}/tests/NegParam/dut.sv, line:11:1, endln:31:10 + \_module_inst: work@prim_packer (work@prim_packer), file:${SURELOG_DIR}/tests/NegParam/dut.sv, line:11:1, endln:31:10 |vpiName:pos_next |vpiFullName:work@prim_packer.pos_next |vpiNetType:36 |vpiNet: \_logic_net: (work@prim_packer.lod_idx), line:23:29, endln:23:36 |vpiParent: - \_module: work@prim_packer (work@prim_packer), file:${SURELOG_DIR}/tests/NegParam/dut.sv, line:11:1, endln:31:10 + \_module_inst: work@prim_packer (work@prim_packer), file:${SURELOG_DIR}/tests/NegParam/dut.sv, line:11:1, endln:31:10 |vpiName:lod_idx |vpiFullName:work@prim_packer.lod_idx |vpiNetType:36 |uhdmallModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/NegParam/dut.sv, line:1:1, endln:9:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/NegParam/dut.sv, line:1:1, endln:9:10 |vpiParent: \_design: (work@top) |vpiFullName:work@top |vpiParameter: \_parameter: (work@top.dram_base_addr_gp), line:2:13, endln:2:30 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/NegParam/dut.sv, line:1:1, endln:9:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/NegParam/dut.sv, line:1:1, endln:9:10 |HEX:0080000000 |vpiTypespec: \_int_typespec: @@ -675,7 +675,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.bp_default_cfg_p), line:4:29, endln:4:45 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/NegParam/dut.sv, line:1:1, endln:9:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/NegParam/dut.sv, line:1:1, endln:9:10 |vpiTypespec: \_unsupported_typespec: (bp_proc_param_s), line:4:13, endln:4:28 |vpiParent: @@ -687,7 +687,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:2:13, endln:2:57 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/NegParam/dut.sv, line:1:1, endln:9:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/NegParam/dut.sv, line:1:1, endln:9:10 |vpiRhs: \_constant: , line:2:41, endln:2:57 |vpiDecompile:40'h00_8000_0000 @@ -701,7 +701,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:4:29, endln:7:6 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/NegParam/dut.sv, line:1:1, endln:9:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/NegParam/dut.sv, line:1:1, endln:9:10 |vpiRhs: \_operation: , line:5:5, endln:7:6 |vpiOpType:75 @@ -738,12 +738,12 @@ design: (work@top) \_parameter: (work@top.bp_default_cfg_p), line:4:29, endln:4:45 |vpiDefName:work@top |uhdmtopModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/NegParam/dut.sv, line:1:1, endln:9:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/NegParam/dut.sv, line:1:1, endln:9:10 |vpiName:work@top |vpiParameter: \_parameter: (work@top.dram_base_addr_gp), line:2:13, endln:2:30 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/NegParam/dut.sv, line:1:1, endln:9:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/NegParam/dut.sv, line:1:1, endln:9:10 |HEX:0080000000 |vpiTypespec: \_int_typespec: @@ -769,7 +769,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.bp_default_cfg_p), line:4:29, endln:4:45 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/NegParam/dut.sv, line:1:1, endln:9:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/NegParam/dut.sv, line:1:1, endln:9:10 |vpiTypespec: \_unsupported_typespec: (bp_proc_param_s), line:4:13, endln:4:28 |vpiParent: @@ -781,7 +781,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:2:13, endln:2:57 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/NegParam/dut.sv, line:1:1, endln:9:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/NegParam/dut.sv, line:1:1, endln:9:10 |vpiRhs: \_constant: , line:2:41, endln:2:57 |vpiDecompile:40'h0080000000 @@ -795,7 +795,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:4:29, endln:7:6 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/NegParam/dut.sv, line:1:1, endln:9:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/NegParam/dut.sv, line:1:1, endln:9:10 |vpiRhs: \_operation: , line:5:5, endln:7:6 |vpiParent: @@ -824,12 +824,12 @@ design: (work@top) |vpiTop:1 |vpiTopModule:1 |uhdmtopModules: -\_module: work@prim_packer (work@prim_packer), file:${SURELOG_DIR}/tests/NegParam/dut.sv, line:11:1, endln:31:10 +\_module_inst: work@prim_packer (work@prim_packer), file:${SURELOG_DIR}/tests/NegParam/dut.sv, line:11:1, endln:31:10 |vpiName:work@prim_packer |vpiVariables: \_logic_var: (work@prim_packer.pos), line:22:29, endln:22:32 |vpiParent: - \_module: work@prim_packer (work@prim_packer), file:${SURELOG_DIR}/tests/NegParam/dut.sv, line:11:1, endln:31:10 + \_module_inst: work@prim_packer (work@prim_packer), file:${SURELOG_DIR}/tests/NegParam/dut.sv, line:11:1, endln:31:10 |vpiTypespec: \_logic_typespec: , line:22:3, endln:22:19 |vpiRange: @@ -874,7 +874,7 @@ design: (work@top) |vpiVariables: \_logic_var: (work@prim_packer.pos_next), line:22:34, endln:22:42 |vpiParent: - \_module: work@prim_packer (work@prim_packer), file:${SURELOG_DIR}/tests/NegParam/dut.sv, line:11:1, endln:31:10 + \_module_inst: work@prim_packer (work@prim_packer), file:${SURELOG_DIR}/tests/NegParam/dut.sv, line:11:1, endln:31:10 |vpiTypespec: \_logic_typespec: , line:22:3, endln:22:19 |vpiName:pos_next @@ -901,7 +901,7 @@ design: (work@top) |vpiVariables: \_logic_var: (work@prim_packer.lod_idx), line:23:29, endln:23:36 |vpiParent: - \_module: work@prim_packer (work@prim_packer), file:${SURELOG_DIR}/tests/NegParam/dut.sv, line:11:1, endln:31:10 + \_module_inst: work@prim_packer (work@prim_packer), file:${SURELOG_DIR}/tests/NegParam/dut.sv, line:11:1, endln:31:10 |vpiTypespec: \_logic_typespec: , line:23:3, endln:23:19 |vpiRange: @@ -946,7 +946,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@prim_packer.InW), line:12:17, endln:12:20 |vpiParent: - \_module: work@prim_packer (work@prim_packer), file:${SURELOG_DIR}/tests/NegParam/dut.sv, line:11:1, endln:31:10 + \_module_inst: work@prim_packer (work@prim_packer), file:${SURELOG_DIR}/tests/NegParam/dut.sv, line:11:1, endln:31:10 |UINT:32 |vpiTypespec: \_int_typespec: , line:12:13, endln:12:16 @@ -959,7 +959,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@prim_packer.OutW), line:13:17, endln:13:21 |vpiParent: - \_module: work@prim_packer (work@prim_packer), file:${SURELOG_DIR}/tests/NegParam/dut.sv, line:11:1, endln:31:10 + \_module_inst: work@prim_packer (work@prim_packer), file:${SURELOG_DIR}/tests/NegParam/dut.sv, line:11:1, endln:31:10 |UINT:32 |vpiTypespec: \_int_typespec: , line:13:13, endln:13:16 @@ -972,7 +972,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@prim_packer.HintByteData), line:14:17, endln:14:29 |vpiParent: - \_module: work@prim_packer (work@prim_packer), file:${SURELOG_DIR}/tests/NegParam/dut.sv, line:11:1, endln:31:10 + \_module_inst: work@prim_packer (work@prim_packer), file:${SURELOG_DIR}/tests/NegParam/dut.sv, line:11:1, endln:31:10 |UINT:0 |vpiTypespec: \_int_typespec: , line:14:13, endln:14:16 @@ -985,7 +985,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@prim_packer.Width), line:18:18, endln:18:23 |vpiParent: - \_module: work@prim_packer (work@prim_packer), file:${SURELOG_DIR}/tests/NegParam/dut.sv, line:11:1, endln:31:10 + \_module_inst: work@prim_packer (work@prim_packer), file:${SURELOG_DIR}/tests/NegParam/dut.sv, line:11:1, endln:31:10 |vpiTypespec: \_int_typespec: , line:18:14, endln:18:17 |vpiParent: @@ -998,7 +998,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@prim_packer.ConcatW), line:19:18, endln:19:25 |vpiParent: - \_module: work@prim_packer (work@prim_packer), file:${SURELOG_DIR}/tests/NegParam/dut.sv, line:11:1, endln:31:10 + \_module_inst: work@prim_packer (work@prim_packer), file:${SURELOG_DIR}/tests/NegParam/dut.sv, line:11:1, endln:31:10 |vpiTypespec: \_int_typespec: , line:19:14, endln:19:17 |vpiParent: @@ -1011,7 +1011,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@prim_packer.PtrW), line:20:18, endln:20:22 |vpiParent: - \_module: work@prim_packer (work@prim_packer), file:${SURELOG_DIR}/tests/NegParam/dut.sv, line:11:1, endln:31:10 + \_module_inst: work@prim_packer (work@prim_packer), file:${SURELOG_DIR}/tests/NegParam/dut.sv, line:11:1, endln:31:10 |vpiTypespec: \_int_typespec: , line:20:14, endln:20:17 |vpiParent: @@ -1024,7 +1024,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@prim_packer.IdxW), line:21:18, endln:21:22 |vpiParent: - \_module: work@prim_packer (work@prim_packer), file:${SURELOG_DIR}/tests/NegParam/dut.sv, line:11:1, endln:31:10 + \_module_inst: work@prim_packer (work@prim_packer), file:${SURELOG_DIR}/tests/NegParam/dut.sv, line:11:1, endln:31:10 |vpiTypespec: \_int_typespec: , line:21:14, endln:21:17 |vpiParent: @@ -1037,7 +1037,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:12:17, endln:12:26 |vpiParent: - \_module: work@prim_packer (work@prim_packer), file:${SURELOG_DIR}/tests/NegParam/dut.sv, line:11:1, endln:31:10 + \_module_inst: work@prim_packer (work@prim_packer), file:${SURELOG_DIR}/tests/NegParam/dut.sv, line:11:1, endln:31:10 |vpiRhs: \_constant: , line:12:24, endln:12:26 |vpiDecompile:32 @@ -1051,7 +1051,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:13:17, endln:13:26 |vpiParent: - \_module: work@prim_packer (work@prim_packer), file:${SURELOG_DIR}/tests/NegParam/dut.sv, line:11:1, endln:31:10 + \_module_inst: work@prim_packer (work@prim_packer), file:${SURELOG_DIR}/tests/NegParam/dut.sv, line:11:1, endln:31:10 |vpiRhs: \_constant: , line:13:24, endln:13:26 |vpiDecompile:32 @@ -1065,7 +1065,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:14:17, endln:14:33 |vpiParent: - \_module: work@prim_packer (work@prim_packer), file:${SURELOG_DIR}/tests/NegParam/dut.sv, line:11:1, endln:31:10 + \_module_inst: work@prim_packer (work@prim_packer), file:${SURELOG_DIR}/tests/NegParam/dut.sv, line:11:1, endln:31:10 |vpiRhs: \_constant: , line:14:32, endln:14:33 |vpiDecompile:0 @@ -1079,7 +1079,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:18:18, endln:18:36 |vpiParent: - \_module: work@prim_packer (work@prim_packer), file:${SURELOG_DIR}/tests/NegParam/dut.sv, line:11:1, endln:31:10 + \_module_inst: work@prim_packer (work@prim_packer), file:${SURELOG_DIR}/tests/NegParam/dut.sv, line:11:1, endln:31:10 |vpiRhs: \_constant: , line:18:26, endln:18:36 |vpiDecompile:64 @@ -1093,7 +1093,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:19:18, endln:19:39 |vpiParent: - \_module: work@prim_packer (work@prim_packer), file:${SURELOG_DIR}/tests/NegParam/dut.sv, line:11:1, endln:31:10 + \_module_inst: work@prim_packer (work@prim_packer), file:${SURELOG_DIR}/tests/NegParam/dut.sv, line:11:1, endln:31:10 |vpiRhs: \_constant: , line:19:28, endln:19:39 |vpiDecompile:96 @@ -1107,7 +1107,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:20:18, endln:20:42 |vpiParent: - \_module: work@prim_packer (work@prim_packer), file:${SURELOG_DIR}/tests/NegParam/dut.sv, line:11:1, endln:31:10 + \_module_inst: work@prim_packer (work@prim_packer), file:${SURELOG_DIR}/tests/NegParam/dut.sv, line:11:1, endln:31:10 |vpiRhs: \_constant: , line:20:25, endln:20:42 |vpiDecompile:7 @@ -1121,7 +1121,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:21:18, endln:21:52 |vpiParent: - \_module: work@prim_packer (work@prim_packer), file:${SURELOG_DIR}/tests/NegParam/dut.sv, line:11:1, endln:31:10 + \_module_inst: work@prim_packer (work@prim_packer), file:${SURELOG_DIR}/tests/NegParam/dut.sv, line:11:1, endln:31:10 |vpiRhs: \_constant: , line:21:25, endln:21:52 |vpiDecompile:5 diff --git a/tests/NetLValue/NetLValue.log b/tests/NetLValue/NetLValue.log index e04ebb03f1..80b1ee246f 100644 --- a/tests/NetLValue/NetLValue.log +++ b/tests/NetLValue/NetLValue.log @@ -154,7 +154,7 @@ hier_path 2 int_typespec 2 int_var 1 logic_net 2 -module 3 +module_inst 3 packed_array_typespec 1 packed_array_var 1 range 2 @@ -176,7 +176,7 @@ hier_path 4 int_typespec 2 int_var 1 logic_net 2 -module 3 +module_inst 3 packed_array_typespec 1 packed_array_var 1 range 2 @@ -198,17 +198,17 @@ design: (work@t) |vpiElaborated:1 |vpiName:work@t |uhdmallModules: -\_module: work@t (work@t), file:${SURELOG_DIR}/tests/NetLValue/dut.sv, line:1:1, endln:10:10 +\_module_inst: work@t (work@t), file:${SURELOG_DIR}/tests/NetLValue/dut.sv, line:1:1, endln:10:10 |vpiParent: \_design: (work@t) |vpiFullName:work@t |vpiTypedef: \_struct_typespec: (S), line:2:12, endln:2:18 |vpiParent: - \_module: work@t (work@t), file:${SURELOG_DIR}/tests/NetLValue/dut.sv, line:1:1, endln:10:10 + \_module_inst: work@t (work@t), file:${SURELOG_DIR}/tests/NetLValue/dut.sv, line:1:1, endln:10:10 |vpiName:S |vpiInstance: - \_module: work@t (work@t), file:${SURELOG_DIR}/tests/NetLValue/dut.sv, line:1:1, endln:10:10 + \_module_inst: work@t (work@t), file:${SURELOG_DIR}/tests/NetLValue/dut.sv, line:1:1, endln:10:10 |vpiTypespecMember: \_typespec_member: (x), line:2:25, endln:2:26 |vpiParent: @@ -228,19 +228,19 @@ design: (work@t) |vpiNet: \_logic_net: (work@t.s), line:3:11, endln:3:12 |vpiParent: - \_module: work@t (work@t), file:${SURELOG_DIR}/tests/NetLValue/dut.sv, line:1:1, endln:10:10 + \_module_inst: work@t (work@t), file:${SURELOG_DIR}/tests/NetLValue/dut.sv, line:1:1, endln:10:10 |vpiName:s |vpiFullName:work@t.s |vpiNet: \_logic_net: (work@t.y), line:4:8, endln:4:9 |vpiParent: - \_module: work@t (work@t), file:${SURELOG_DIR}/tests/NetLValue/dut.sv, line:1:1, endln:10:10 + \_module_inst: work@t (work@t), file:${SURELOG_DIR}/tests/NetLValue/dut.sv, line:1:1, endln:10:10 |vpiName:y |vpiFullName:work@t.y |vpiProcess: \_always: , line:6:4, endln:9:7 |vpiParent: - \_module: work@t (work@t), file:${SURELOG_DIR}/tests/NetLValue/dut.sv, line:1:1, endln:10:10 + \_module_inst: work@t (work@t), file:${SURELOG_DIR}/tests/NetLValue/dut.sv, line:1:1, endln:10:10 |vpiStmt: \_begin: (work@t), line:6:16, endln:9:7 |vpiParent: @@ -324,12 +324,12 @@ design: (work@t) |vpiName:x |vpiAlwaysType:2 |uhdmtopModules: -\_module: work@t (work@t), file:${SURELOG_DIR}/tests/NetLValue/dut.sv, line:1:1, endln:10:10 +\_module_inst: work@t (work@t), file:${SURELOG_DIR}/tests/NetLValue/dut.sv, line:1:1, endln:10:10 |vpiName:work@t |vpiVariables: \_packed_array_var: (work@t.s), line:3:11, endln:3:12 |vpiParent: - \_module: work@t (work@t), file:${SURELOG_DIR}/tests/NetLValue/dut.sv, line:1:1, endln:10:10 + \_module_inst: work@t (work@t), file:${SURELOG_DIR}/tests/NetLValue/dut.sv, line:1:1, endln:10:10 |vpiName:s |vpiFullName:work@t.s |vpiVisibility:1 @@ -361,7 +361,7 @@ design: (work@t) |vpiVariables: \_int_var: (work@t.y), line:4:8, endln:4:9 |vpiParent: - \_module: work@t (work@t), file:${SURELOG_DIR}/tests/NetLValue/dut.sv, line:1:1, endln:10:10 + \_module_inst: work@t (work@t), file:${SURELOG_DIR}/tests/NetLValue/dut.sv, line:1:1, endln:10:10 |vpiTypespec: \_int_typespec: , line:4:4, endln:4:7 |vpiSigned:1 @@ -376,7 +376,7 @@ design: (work@t) |vpiProcess: \_always: , line:6:4, endln:9:7 |vpiParent: - \_module: work@t (work@t), file:${SURELOG_DIR}/tests/NetLValue/dut.sv, line:1:1, endln:10:10 + \_module_inst: work@t (work@t), file:${SURELOG_DIR}/tests/NetLValue/dut.sv, line:1:1, endln:10:10 |vpiStmt: \_begin: (work@t), line:6:16, endln:9:7 |vpiParent: diff --git a/tests/NoParamSubs/NoParamSubs.log b/tests/NoParamSubs/NoParamSubs.log index a3969032f2..c63b202656 100644 --- a/tests/NoParamSubs/NoParamSubs.log +++ b/tests/NoParamSubs/NoParamSubs.log @@ -192,7 +192,7 @@ cont_assign 1 design 1 logic_net 4 logic_typespec 12 -module 9 +module_inst 9 operation 6 param_assign 4 parameter 5 @@ -208,7 +208,7 @@ cont_assign 2 design 1 logic_net 4 logic_typespec 12 -module 9 +module_inst 9 operation 6 param_assign 4 parameter 5 @@ -229,14 +229,14 @@ design: (work@top) |vpiElaborated:1 |vpiName:work@top |uhdmallModules: -\_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/NoParamSubs/dut.sv, line:1:1, endln:4:10 +\_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/NoParamSubs/dut.sv, line:1:1, endln:4:10 |vpiParent: \_design: (work@top) |vpiFullName:work@dut |vpiParameter: \_parameter: (work@dut.P), line:2:26, endln:2:27 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/NoParamSubs/dut.sv, line:1:1, endln:4:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/NoParamSubs/dut.sv, line:1:1, endln:4:10 |UINT:0 |vpiTypespec: \_logic_typespec: , line:2:14, endln:2:25 @@ -265,7 +265,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:2:26, endln:2:31 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/NoParamSubs/dut.sv, line:1:1, endln:4:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/NoParamSubs/dut.sv, line:1:1, endln:4:10 |vpiRhs: \_constant: , line:2:30, endln:2:31 |vpiDecompile:0 @@ -280,14 +280,14 @@ design: (work@top) |vpiNet: \_logic_net: (work@dut.a), line:1:31, endln:1:32 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/NoParamSubs/dut.sv, line:1:1, endln:4:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/NoParamSubs/dut.sv, line:1:1, endln:4:10 |vpiName:a |vpiFullName:work@dut.a |vpiNetType:36 |vpiPort: \_port: (a), line:1:31, endln:1:32 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/NoParamSubs/dut.sv, line:1:1, endln:4:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/NoParamSubs/dut.sv, line:1:1, endln:4:10 |vpiName:a |vpiDirection:2 |vpiLowConn: @@ -317,7 +317,7 @@ design: (work@top) |vpiContAssign: \_cont_assign: , line:3:11, endln:3:16 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/NoParamSubs/dut.sv, line:1:1, endln:4:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/NoParamSubs/dut.sv, line:1:1, endln:4:10 |vpiRhs: \_ref_obj: (work@dut.P), line:3:15, endln:3:16 |vpiParent: @@ -333,14 +333,14 @@ design: (work@top) |vpiActual: \_logic_net: (work@top.u_dut.a), line:1:31, endln:1:32 |uhdmallModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/NoParamSubs/dut.sv, line:6:1, endln:13:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/NoParamSubs/dut.sv, line:6:1, endln:13:10 |vpiParent: \_design: (work@top) |vpiFullName:work@top |vpiParameter: \_parameter: (work@top.X), line:7:26, endln:7:27 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/NoParamSubs/dut.sv, line:6:1, endln:13:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/NoParamSubs/dut.sv, line:6:1, endln:13:10 |vpiTypespec: \_logic_typespec: , line:7:14, endln:7:25 |vpiParent: @@ -368,7 +368,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:7:26, endln:7:37 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/NoParamSubs/dut.sv, line:6:1, endln:13:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/NoParamSubs/dut.sv, line:6:1, endln:13:10 |vpiRhs: \_operation: , line:7:30, endln:7:37 |vpiOpType:75 @@ -390,14 +390,14 @@ design: (work@top) |vpiNet: \_logic_net: (work@top.o), line:6:31, endln:6:32 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/NoParamSubs/dut.sv, line:6:1, endln:13:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/NoParamSubs/dut.sv, line:6:1, endln:13:10 |vpiName:o |vpiFullName:work@top.o |vpiNetType:36 |vpiPort: \_port: (o), line:6:31, endln:6:32 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/NoParamSubs/dut.sv, line:6:1, endln:13:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/NoParamSubs/dut.sv, line:6:1, endln:13:10 |vpiName:o |vpiDirection:2 |vpiLowConn: @@ -425,12 +425,12 @@ design: (work@top) |UINT:0 |vpiConstType:9 |uhdmtopModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/NoParamSubs/dut.sv, line:6:1, endln:13:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/NoParamSubs/dut.sv, line:6:1, endln:13:10 |vpiName:work@top |vpiParameter: \_parameter: (work@top.X), line:7:26, endln:7:27 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/NoParamSubs/dut.sv, line:6:1, endln:13:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/NoParamSubs/dut.sv, line:6:1, endln:13:10 |vpiTypespec: \_logic_typespec: , line:7:14, endln:7:25 |vpiParent: @@ -460,7 +460,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:7:26, endln:7:37 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/NoParamSubs/dut.sv, line:6:1, endln:13:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/NoParamSubs/dut.sv, line:6:1, endln:13:10 |vpiRhs: \_operation: , line:7:30, endln:7:37 |vpiParent: @@ -514,7 +514,7 @@ design: (work@top) |vpiNet: \_logic_net: (work@top.o), line:6:31, endln:6:32 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/NoParamSubs/dut.sv, line:6:1, endln:13:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/NoParamSubs/dut.sv, line:6:1, endln:13:10 |vpiTypespec: \_logic_typespec: , line:6:19, endln:6:30 |vpiRange: @@ -542,7 +542,7 @@ design: (work@top) |vpiPort: \_port: (o), line:6:31, endln:6:32 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/NoParamSubs/dut.sv, line:6:1, endln:13:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/NoParamSubs/dut.sv, line:6:1, endln:13:10 |vpiName:o |vpiDirection:2 |vpiLowConn: @@ -576,17 +576,17 @@ design: (work@top) |UINT:0 |vpiConstType:9 |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/NoParamSubs/dut.sv, line:6:1, endln:13:10 - |vpiModule: - \_module: work@dut (work@top.u_dut), file:${SURELOG_DIR}/tests/NoParamSubs/dut.sv, line:8:4, endln:12:6 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/NoParamSubs/dut.sv, line:6:1, endln:13:10 + |vpiModuleInst: + \_module_inst: work@dut (work@top.u_dut), file:${SURELOG_DIR}/tests/NoParamSubs/dut.sv, line:8:4, endln:12:6 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/NoParamSubs/dut.sv, line:6:1, endln:13:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/NoParamSubs/dut.sv, line:6:1, endln:13:10 |vpiName:u_dut |vpiFullName:work@top.u_dut |vpiParameter: \_parameter: (work@top.u_dut.P), line:2:26, endln:2:27 |vpiParent: - \_module: work@dut (work@top.u_dut), file:${SURELOG_DIR}/tests/NoParamSubs/dut.sv, line:8:4, endln:12:6 + \_module_inst: work@dut (work@top.u_dut), file:${SURELOG_DIR}/tests/NoParamSubs/dut.sv, line:8:4, endln:12:6 |UINT:0 |vpiTypespec: \_logic_typespec: , line:2:14, endln:2:25 @@ -617,7 +617,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:2:26, endln:2:31 |vpiParent: - \_module: work@dut (work@top.u_dut), file:${SURELOG_DIR}/tests/NoParamSubs/dut.sv, line:8:4, endln:12:6 + \_module_inst: work@dut (work@top.u_dut), file:${SURELOG_DIR}/tests/NoParamSubs/dut.sv, line:8:4, endln:12:6 |vpiOverriden:1 |vpiRhs: \_operation: , line:9:10, endln:9:12 @@ -637,7 +637,7 @@ design: (work@top) |vpiNet: \_logic_net: (work@top.u_dut.a), line:1:31, endln:1:32 |vpiParent: - \_module: work@dut (work@top.u_dut), file:${SURELOG_DIR}/tests/NoParamSubs/dut.sv, line:8:4, endln:12:6 + \_module_inst: work@dut (work@top.u_dut), file:${SURELOG_DIR}/tests/NoParamSubs/dut.sv, line:8:4, endln:12:6 |vpiTypespec: \_logic_typespec: , line:1:19, endln:1:30 |vpiRange: @@ -662,11 +662,11 @@ design: (work@top) |vpiFullName:work@top.u_dut.a |vpiNetType:36 |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/NoParamSubs/dut.sv, line:6:1, endln:13:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/NoParamSubs/dut.sv, line:6:1, endln:13:10 |vpiPort: \_port: (a), line:1:31, endln:1:32 |vpiParent: - \_module: work@dut (work@top.u_dut), file:${SURELOG_DIR}/tests/NoParamSubs/dut.sv, line:8:4, endln:12:6 + \_module_inst: work@dut (work@top.u_dut), file:${SURELOG_DIR}/tests/NoParamSubs/dut.sv, line:8:4, endln:12:6 |vpiName:a |vpiDirection:2 |vpiHighConn: @@ -708,11 +708,11 @@ design: (work@top) |UINT:0 |vpiConstType:9 |vpiInstance: - \_module: work@dut (work@top.u_dut), file:${SURELOG_DIR}/tests/NoParamSubs/dut.sv, line:8:4, endln:12:6 + \_module_inst: work@dut (work@top.u_dut), file:${SURELOG_DIR}/tests/NoParamSubs/dut.sv, line:8:4, endln:12:6 |vpiContAssign: \_cont_assign: , line:3:11, endln:3:16 |vpiParent: - \_module: work@dut (work@top.u_dut), file:${SURELOG_DIR}/tests/NoParamSubs/dut.sv, line:8:4, endln:12:6 + \_module_inst: work@dut (work@top.u_dut), file:${SURELOG_DIR}/tests/NoParamSubs/dut.sv, line:8:4, endln:12:6 |vpiRhs: \_ref_obj: (work@top.u_dut.P), line:3:15, endln:3:16 |vpiParent: diff --git a/tests/NonAnsiPort/NonAnsiPort.log b/tests/NonAnsiPort/NonAnsiPort.log index fd0e8610f8..a9247d5207 100644 --- a/tests/NonAnsiPort/NonAnsiPort.log +++ b/tests/NonAnsiPort/NonAnsiPort.log @@ -246,7 +246,7 @@ design 1 hier_path 6 logic_net 3 logic_typespec 5 -module 5 +module_inst 5 package 6 port 6 range 5 @@ -473,17 +473,17 @@ design: (work@dut) |vpiDefName:pkg2 |vpiTop:1 |uhdmallModules: -\_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/NonAnsiPort/dut.sv, line:13:1, endln:25:10 +\_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/NonAnsiPort/dut.sv, line:13:1, endln:25:10 |vpiParent: \_design: (work@dut) |vpiFullName:work@dut |vpiTypedef: \_struct_typespec: (struct2), line:14:13, endln:14:19 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/NonAnsiPort/dut.sv, line:13:1, endln:25:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/NonAnsiPort/dut.sv, line:13:1, endln:25:10 |vpiName:struct2 |vpiInstance: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/NonAnsiPort/dut.sv, line:13:1, endln:25:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/NonAnsiPort/dut.sv, line:13:1, endln:25:10 |vpiPacked:1 |vpiTypespecMember: \_typespec_member: (third), line:15:21, endln:15:26 @@ -523,27 +523,27 @@ design: (work@dut) |vpiNet: \_logic_net: (work@dut.var1), line:13:12, endln:13:16 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/NonAnsiPort/dut.sv, line:13:1, endln:25:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/NonAnsiPort/dut.sv, line:13:1, endln:25:10 |vpiName:var1 |vpiFullName:work@dut.var1 |vpiNetType:1 |vpiNet: \_logic_net: (work@dut.var2), line:13:18, endln:13:22 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/NonAnsiPort/dut.sv, line:13:1, endln:25:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/NonAnsiPort/dut.sv, line:13:1, endln:25:10 |vpiName:var2 |vpiFullName:work@dut.var2 |vpiNetType:1 |vpiNet: \_logic_net: (work@dut.var3), line:13:24, endln:13:28 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/NonAnsiPort/dut.sv, line:13:1, endln:25:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/NonAnsiPort/dut.sv, line:13:1, endln:25:10 |vpiName:var3 |vpiFullName:work@dut.var3 |vpiPort: \_port: (var1), line:13:12, endln:13:16 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/NonAnsiPort/dut.sv, line:13:1, endln:25:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/NonAnsiPort/dut.sv, line:13:1, endln:25:10 |vpiName:var1 |vpiDirection:2 |vpiLowConn: @@ -555,7 +555,7 @@ design: (work@dut) |vpiPort: \_port: (var2), line:13:18, endln:13:22 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/NonAnsiPort/dut.sv, line:13:1, endln:25:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/NonAnsiPort/dut.sv, line:13:1, endln:25:10 |vpiName:var2 |vpiDirection:2 |vpiLowConn: @@ -567,7 +567,7 @@ design: (work@dut) |vpiPort: \_port: (var3), line:13:24, endln:13:28 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/NonAnsiPort/dut.sv, line:13:1, endln:25:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/NonAnsiPort/dut.sv, line:13:1, endln:25:10 |vpiName:var3 |vpiDirection:2 |vpiLowConn: @@ -579,7 +579,7 @@ design: (work@dut) |vpiContAssign: \_cont_assign: , line:22:12, endln:22:28 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/NonAnsiPort/dut.sv, line:13:1, endln:25:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/NonAnsiPort/dut.sv, line:13:1, endln:25:10 |vpiRhs: \_constant: , line:22:25, endln:22:28 |vpiParent: @@ -604,7 +604,7 @@ design: (work@dut) |vpiContAssign: \_cont_assign: , line:23:12, endln:23:29 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/NonAnsiPort/dut.sv, line:13:1, endln:25:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/NonAnsiPort/dut.sv, line:13:1, endln:25:10 |vpiRhs: \_constant: , line:23:26, endln:23:29 |vpiParent: @@ -629,7 +629,7 @@ design: (work@dut) |vpiContAssign: \_cont_assign: , line:24:12, endln:24:27 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/NonAnsiPort/dut.sv, line:13:1, endln:25:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/NonAnsiPort/dut.sv, line:13:1, endln:25:10 |vpiRhs: \_constant: , line:24:25, endln:24:27 |vpiParent: @@ -652,7 +652,7 @@ design: (work@dut) \_ref_obj: (third) |vpiName:third |uhdmtopModules: -\_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/NonAnsiPort/dut.sv, line:13:1, endln:25:10 +\_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/NonAnsiPort/dut.sv, line:13:1, endln:25:10 |vpiName:work@dut |vpiTypedef: \_struct_typespec: (struct2), line:14:13, endln:14:19 @@ -661,7 +661,7 @@ design: (work@dut) |vpiNet: \_struct_net: (work@dut.var1), line:13:12, endln:13:16 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/NonAnsiPort/dut.sv, line:13:1, endln:25:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/NonAnsiPort/dut.sv, line:13:1, endln:25:10 |vpiTypespec: \_struct_typespec: (pkg1::struct1), line:2:13, endln:2:19 |vpiName:var1 @@ -670,7 +670,7 @@ design: (work@dut) |vpiNet: \_struct_net: (work@dut.var2), line:13:18, endln:13:22 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/NonAnsiPort/dut.sv, line:13:1, endln:25:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/NonAnsiPort/dut.sv, line:13:1, endln:25:10 |vpiTypespec: \_struct_typespec: (pkg2::struct1), line:8:13, endln:8:19 |vpiName:var2 @@ -679,7 +679,7 @@ design: (work@dut) |vpiNet: \_struct_net: (work@dut.var3), line:13:24, endln:13:28 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/NonAnsiPort/dut.sv, line:13:1, endln:25:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/NonAnsiPort/dut.sv, line:13:1, endln:25:10 |vpiTypespec: \_struct_typespec: (struct2), line:14:13, endln:14:19 |vpiName:var3 @@ -688,7 +688,7 @@ design: (work@dut) |vpiPort: \_port: (var1), line:13:12, endln:13:16 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/NonAnsiPort/dut.sv, line:13:1, endln:25:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/NonAnsiPort/dut.sv, line:13:1, endln:25:10 |vpiName:var1 |vpiDirection:2 |vpiLowConn: @@ -702,7 +702,7 @@ design: (work@dut) |vpiPort: \_port: (var2), line:13:18, endln:13:22 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/NonAnsiPort/dut.sv, line:13:1, endln:25:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/NonAnsiPort/dut.sv, line:13:1, endln:25:10 |vpiName:var2 |vpiDirection:2 |vpiLowConn: @@ -716,7 +716,7 @@ design: (work@dut) |vpiPort: \_port: (var3), line:13:24, endln:13:28 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/NonAnsiPort/dut.sv, line:13:1, endln:25:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/NonAnsiPort/dut.sv, line:13:1, endln:25:10 |vpiName:var3 |vpiDirection:2 |vpiLowConn: diff --git a/tests/NonSynthError/NonSynthError.log b/tests/NonSynthError/NonSynthError.log index 9719aa1db1..3bec1eccbb 100644 --- a/tests/NonSynthError/NonSynthError.log +++ b/tests/NonSynthError/NonSynthError.log @@ -89,7 +89,7 @@ constant 3 design 1 initial 1 int_typespec 4 -module 5 +module_inst 5 param_assign 2 parameter 2 sys_func_call 1 @@ -105,7 +105,7 @@ constant 3 design 1 initial 2 int_typespec 4 -module 5 +module_inst 5 param_assign 2 parameter 2 sys_func_call 2 @@ -123,14 +123,14 @@ design: (work@dut) |vpiElaborated:1 |vpiName:work@dut |uhdmallModules: -\_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/NonSynthError/dut.sv, line:2:1, endln:13:10 +\_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/NonSynthError/dut.sv, line:2:1, endln:13:10 |vpiParent: \_design: (work@dut) |vpiFullName:work@dut |vpiParameter: \_parameter: (work@dut.S), line:4:11, endln:4:12 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/NonSynthError/dut.sv, line:2:1, endln:13:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/NonSynthError/dut.sv, line:2:1, endln:13:10 |UINT:32 |vpiTypespec: \_int_typespec: @@ -139,7 +139,7 @@ design: (work@dut) |vpiParamAssign: \_param_assign: , line:4:11, endln:4:25 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/NonSynthError/dut.sv, line:2:1, endln:13:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/NonSynthError/dut.sv, line:2:1, endln:13:10 |vpiRhs: \_constant: , line:4:15, endln:4:20 |vpiDecompile:32 @@ -154,13 +154,13 @@ design: (work@dut) |vpiClassDefn: \_class_defn: (work@dut::A), file:${SURELOG_DIR}/tests/NonSynthError/dut.sv, line:10:1, endln:11:9 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/NonSynthError/dut.sv, line:2:1, endln:13:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/NonSynthError/dut.sv, line:2:1, endln:13:10 |vpiName:A |vpiFullName:work@dut::A |vpiProcess: \_initial: , line:6:1, endln:8:4 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/NonSynthError/dut.sv, line:2:1, endln:13:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/NonSynthError/dut.sv, line:2:1, endln:13:10 |vpiStmt: \_begin: (work@dut), line:6:9, endln:8:4 |vpiParent: @@ -172,12 +172,12 @@ design: (work@dut) \_begin: (work@dut), line:6:9, endln:8:4 |vpiName:$display |uhdmtopModules: -\_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/NonSynthError/dut.sv, line:2:1, endln:13:10 +\_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/NonSynthError/dut.sv, line:2:1, endln:13:10 |vpiName:work@dut |vpiParameter: \_parameter: (work@dut.S), line:4:11, endln:4:12 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/NonSynthError/dut.sv, line:2:1, endln:13:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/NonSynthError/dut.sv, line:2:1, endln:13:10 |UINT:32 |vpiTypespec: \_int_typespec: @@ -188,7 +188,7 @@ design: (work@dut) |vpiParamAssign: \_param_assign: , line:4:11, endln:4:25 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/NonSynthError/dut.sv, line:2:1, endln:13:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/NonSynthError/dut.sv, line:2:1, endln:13:10 |vpiRhs: \_constant: , line:4:15, endln:4:25 |vpiDecompile:32 @@ -204,14 +204,14 @@ design: (work@dut) |vpiClassDefn: \_class_defn: (work@dut::A), file:${SURELOG_DIR}/tests/NonSynthError/dut.sv, line:10:1, endln:11:9 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/NonSynthError/dut.sv, line:2:1, endln:13:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/NonSynthError/dut.sv, line:2:1, endln:13:10 |vpiName:A |vpiFullName:work@dut::A |vpiTopModule:1 |vpiProcess: \_initial: , line:6:1, endln:8:4 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/NonSynthError/dut.sv, line:2:1, endln:13:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/NonSynthError/dut.sv, line:2:1, endln:13:10 |vpiStmt: \_begin: (work@dut), line:6:9, endln:8:4 |vpiParent: diff --git a/tests/OldLibrary/OldLibrary.log b/tests/OldLibrary/OldLibrary.log index 3868bc1424..01a433b9e1 100644 --- a/tests/OldLibrary/OldLibrary.log +++ b/tests/OldLibrary/OldLibrary.log @@ -2,27 +2,27 @@ [INF:PP0122] Preprocessing source file "${SURELOG_DIR}/tests/OldLibrary/top.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/tests/OldLibrary/lib/CELL2.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/tests/OldLibrary/lib/CELL3.v". [INF:PP0122] Preprocessing source file "${SURELOG_DIR}/tests/OldLibrary/lib/CELL1.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/tests/OldLibrary/lib/CELL3.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/tests/OldLibrary/lib/CELL2.v". [INF:PA0201] Parsing source file "${SURELOG_DIR}/tests/OldLibrary/top.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/tests/OldLibrary/lib/CELL2.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/tests/OldLibrary/lib/CELL3.v". [INF:PA0201] Parsing source file "${SURELOG_DIR}/tests/OldLibrary/lib/CELL1.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/tests/OldLibrary/lib/CELL3.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/tests/OldLibrary/lib/CELL2.v". [WRN:PA0205] ${SURELOG_DIR}/tests/OldLibrary/top.v:1:1: No timescale set for "top". -[WRN:PA0205] ${SURELOG_DIR}/tests/OldLibrary/lib/CELL2.v:1:1: No timescale set for "CELL2". +[WRN:PA0205] ${SURELOG_DIR}/tests/OldLibrary/lib/CELL3.v:1:1: No timescale set for "CELL3". [WRN:PA0205] ${SURELOG_DIR}/tests/OldLibrary/lib/CELL1.v:1:1: No timescale set for "CELL1". -[WRN:PA0205] ${SURELOG_DIR}/tests/OldLibrary/lib/CELL3.v:1:1: No timescale set for "CELL3". +[WRN:PA0205] ${SURELOG_DIR}/tests/OldLibrary/lib/CELL2.v:1:1: No timescale set for "CELL2". [INF:CP0300] Compilation... @@ -80,7 +80,7 @@ int_var 4 io_decl 17 logic_net 6 logic_var 1 -module 4 +module_inst 4 package 2 table_entry 6 task 9 diff --git a/tests/OneAnd/OneAnd.log b/tests/OneAnd/OneAnd.log index 6444925b0a..d295bf396a 100644 --- a/tests/OneAnd/OneAnd.log +++ b/tests/OneAnd/OneAnd.log @@ -598,7 +598,7 @@ initial 2 logic_net 10 logic_typespec 13 logic_var 2 -module 4 +module_inst 4 operation 10 port 8 ref_obj 40 @@ -618,7 +618,7 @@ initial 4 logic_net 10 logic_typespec 13 logic_var 2 -module 4 +module_inst 4 operation 19 port 12 ref_obj 73 @@ -637,7 +637,7 @@ design: (work@and_tb) |vpiElaborated:1 |vpiName:work@and_tb |uhdmallModules: -\_module: work@and_tb (work@and_tb), file:${SURELOG_DIR}/tests/OneAnd/tb.v, line:1:1, endln:30:10 +\_module_inst: work@and_tb (work@and_tb), file:${SURELOG_DIR}/tests/OneAnd/tb.v, line:1:1, endln:30:10 |vpiParent: \_design: (work@and_tb) |vpiFullName:work@and_tb @@ -645,28 +645,28 @@ design: (work@and_tb) |vpiNet: \_logic_net: (work@and_tb.o), line:1:28, endln:1:29 |vpiParent: - \_module: work@and_tb (work@and_tb), file:${SURELOG_DIR}/tests/OneAnd/tb.v, line:1:1, endln:30:10 + \_module_inst: work@and_tb (work@and_tb), file:${SURELOG_DIR}/tests/OneAnd/tb.v, line:1:1, endln:30:10 |vpiName:o |vpiFullName:work@and_tb.o |vpiNetType:36 |vpiNet: \_logic_net: (work@and_tb.a), line:2:9, endln:2:10 |vpiParent: - \_module: work@and_tb (work@and_tb), file:${SURELOG_DIR}/tests/OneAnd/tb.v, line:1:1, endln:30:10 + \_module_inst: work@and_tb (work@and_tb), file:${SURELOG_DIR}/tests/OneAnd/tb.v, line:1:1, endln:30:10 |vpiName:a |vpiFullName:work@and_tb.a |vpiNetType:36 |vpiNet: \_logic_net: (work@and_tb.b), line:2:12, endln:2:13 |vpiParent: - \_module: work@and_tb (work@and_tb), file:${SURELOG_DIR}/tests/OneAnd/tb.v, line:1:1, endln:30:10 + \_module_inst: work@and_tb (work@and_tb), file:${SURELOG_DIR}/tests/OneAnd/tb.v, line:1:1, endln:30:10 |vpiName:b |vpiFullName:work@and_tb.b |vpiNetType:36 |vpiPort: \_port: (o), line:1:28, endln:1:29 |vpiParent: - \_module: work@and_tb (work@and_tb), file:${SURELOG_DIR}/tests/OneAnd/tb.v, line:1:1, endln:30:10 + \_module_inst: work@and_tb (work@and_tb), file:${SURELOG_DIR}/tests/OneAnd/tb.v, line:1:1, endln:30:10 |vpiName:o |vpiDirection:2 |vpiLowConn: @@ -678,7 +678,7 @@ design: (work@and_tb) |vpiProcess: \_initial: , line:4:3, endln:7:6 |vpiParent: - \_module: work@and_tb (work@and_tb), file:${SURELOG_DIR}/tests/OneAnd/tb.v, line:1:1, endln:30:10 + \_module_inst: work@and_tb (work@and_tb), file:${SURELOG_DIR}/tests/OneAnd/tb.v, line:1:1, endln:30:10 |vpiStmt: \_begin: (work@and_tb), line:4:11, endln:7:6 |vpiParent: @@ -739,7 +739,7 @@ design: (work@and_tb) |vpiProcess: \_initial: , line:9:3, endln:26:6 |vpiParent: - \_module: work@and_tb (work@and_tb), file:${SURELOG_DIR}/tests/OneAnd/tb.v, line:1:1, endln:30:10 + \_module_inst: work@and_tb (work@and_tb), file:${SURELOG_DIR}/tests/OneAnd/tb.v, line:1:1, endln:30:10 |vpiStmt: \_begin: (work@and_tb), line:10:3, endln:26:6 |vpiParent: @@ -1245,7 +1245,7 @@ design: (work@and_tb) |vpiConstType:6 |vpiName:$fatal |uhdmallModules: -\_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/OneAnd/dut.v, line:1:1, endln:5:10 +\_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/OneAnd/dut.v, line:1:1, endln:5:10 |vpiParent: \_design: (work@and_tb) |vpiFullName:work@dut @@ -1253,28 +1253,28 @@ design: (work@and_tb) |vpiNet: \_logic_net: (work@dut.a), line:1:24, endln:1:25 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/OneAnd/dut.v, line:1:1, endln:5:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/OneAnd/dut.v, line:1:1, endln:5:10 |vpiName:a |vpiFullName:work@dut.a |vpiNetType:36 |vpiNet: \_logic_net: (work@dut.b), line:1:39, endln:1:40 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/OneAnd/dut.v, line:1:1, endln:5:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/OneAnd/dut.v, line:1:1, endln:5:10 |vpiName:b |vpiFullName:work@dut.b |vpiNetType:36 |vpiNet: \_logic_net: (work@dut.o), line:1:55, endln:1:56 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/OneAnd/dut.v, line:1:1, endln:5:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/OneAnd/dut.v, line:1:1, endln:5:10 |vpiName:o |vpiFullName:work@dut.o |vpiNetType:36 |vpiPort: \_port: (a), line:1:24, endln:1:25 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/OneAnd/dut.v, line:1:1, endln:5:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/OneAnd/dut.v, line:1:1, endln:5:10 |vpiName:a |vpiDirection:1 |vpiLowConn: @@ -1286,7 +1286,7 @@ design: (work@and_tb) |vpiPort: \_port: (b), line:1:39, endln:1:40 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/OneAnd/dut.v, line:1:1, endln:5:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/OneAnd/dut.v, line:1:1, endln:5:10 |vpiName:b |vpiDirection:1 |vpiLowConn: @@ -1298,7 +1298,7 @@ design: (work@and_tb) |vpiPort: \_port: (o), line:1:55, endln:1:56 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/OneAnd/dut.v, line:1:1, endln:5:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/OneAnd/dut.v, line:1:1, endln:5:10 |vpiName:o |vpiDirection:2 |vpiLowConn: @@ -1310,7 +1310,7 @@ design: (work@and_tb) |vpiContAssign: \_cont_assign: , line:3:10, endln:3:19 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/OneAnd/dut.v, line:1:1, endln:5:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/OneAnd/dut.v, line:1:1, endln:5:10 |vpiRhs: \_operation: , line:3:14, endln:3:19 |vpiParent: @@ -1341,12 +1341,12 @@ design: (work@and_tb) |vpiActual: \_logic_net: (work@and_tb.dut1.o), line:1:55, endln:1:56 |uhdmtopModules: -\_module: work@and_tb (work@and_tb), file:${SURELOG_DIR}/tests/OneAnd/tb.v, line:1:1, endln:30:10 +\_module_inst: work@and_tb (work@and_tb), file:${SURELOG_DIR}/tests/OneAnd/tb.v, line:1:1, endln:30:10 |vpiName:work@and_tb |vpiVariables: \_logic_var: (work@and_tb.a), line:2:9, endln:2:10 |vpiParent: - \_module: work@and_tb (work@and_tb), file:${SURELOG_DIR}/tests/OneAnd/tb.v, line:1:1, endln:30:10 + \_module_inst: work@and_tb (work@and_tb), file:${SURELOG_DIR}/tests/OneAnd/tb.v, line:1:1, endln:30:10 |vpiTypespec: \_logic_typespec: , line:2:3, endln:2:8 |vpiName:a @@ -1355,7 +1355,7 @@ design: (work@and_tb) |vpiVariables: \_logic_var: (work@and_tb.b), line:2:12, endln:2:13 |vpiParent: - \_module: work@and_tb (work@and_tb), file:${SURELOG_DIR}/tests/OneAnd/tb.v, line:1:1, endln:30:10 + \_module_inst: work@and_tb (work@and_tb), file:${SURELOG_DIR}/tests/OneAnd/tb.v, line:1:1, endln:30:10 |vpiTypespec: \_logic_typespec: , line:2:3, endln:2:8 |vpiName:b @@ -1366,7 +1366,7 @@ design: (work@and_tb) |vpiNet: \_logic_net: (work@and_tb.o), line:1:28, endln:1:29 |vpiParent: - \_module: work@and_tb (work@and_tb), file:${SURELOG_DIR}/tests/OneAnd/tb.v, line:1:1, endln:30:10 + \_module_inst: work@and_tb (work@and_tb), file:${SURELOG_DIR}/tests/OneAnd/tb.v, line:1:1, endln:30:10 |vpiTypespec: \_logic_typespec: , line:1:22, endln:1:27 |vpiName:o @@ -1376,7 +1376,7 @@ design: (work@and_tb) |vpiPort: \_port: (o), line:1:28, endln:1:29 |vpiParent: - \_module: work@and_tb (work@and_tb), file:${SURELOG_DIR}/tests/OneAnd/tb.v, line:1:1, endln:30:10 + \_module_inst: work@and_tb (work@and_tb), file:${SURELOG_DIR}/tests/OneAnd/tb.v, line:1:1, endln:30:10 |vpiName:o |vpiDirection:2 |vpiLowConn: @@ -1390,11 +1390,11 @@ design: (work@and_tb) |vpiTypedef: \_logic_typespec: , line:1:22, endln:1:27 |vpiInstance: - \_module: work@and_tb (work@and_tb), file:${SURELOG_DIR}/tests/OneAnd/tb.v, line:1:1, endln:30:10 + \_module_inst: work@and_tb (work@and_tb), file:${SURELOG_DIR}/tests/OneAnd/tb.v, line:1:1, endln:30:10 |vpiProcess: \_initial: , line:4:3, endln:7:6 |vpiParent: - \_module: work@and_tb (work@and_tb), file:${SURELOG_DIR}/tests/OneAnd/tb.v, line:1:1, endln:30:10 + \_module_inst: work@and_tb (work@and_tb), file:${SURELOG_DIR}/tests/OneAnd/tb.v, line:1:1, endln:30:10 |vpiStmt: \_begin: (work@and_tb), line:4:11, endln:7:6 |vpiParent: @@ -1449,7 +1449,7 @@ design: (work@and_tb) |vpiProcess: \_initial: , line:9:3, endln:26:6 |vpiParent: - \_module: work@and_tb (work@and_tb), file:${SURELOG_DIR}/tests/OneAnd/tb.v, line:1:1, endln:30:10 + \_module_inst: work@and_tb (work@and_tb), file:${SURELOG_DIR}/tests/OneAnd/tb.v, line:1:1, endln:30:10 |vpiStmt: \_begin: (work@and_tb), line:10:3, endln:26:6 |vpiParent: @@ -1834,10 +1834,10 @@ design: (work@and_tb) |vpiArgument: \_constant: , line:25:62, endln:25:77 |vpiName:$fatal - |vpiModule: - \_module: work@dut (work@and_tb.dut1), file:${SURELOG_DIR}/tests/OneAnd/tb.v, line:28:3, endln:28:19 + |vpiModuleInst: + \_module_inst: work@dut (work@and_tb.dut1), file:${SURELOG_DIR}/tests/OneAnd/tb.v, line:28:3, endln:28:19 |vpiParent: - \_module: work@and_tb (work@and_tb), file:${SURELOG_DIR}/tests/OneAnd/tb.v, line:1:1, endln:30:10 + \_module_inst: work@and_tb (work@and_tb), file:${SURELOG_DIR}/tests/OneAnd/tb.v, line:1:1, endln:30:10 |vpiName:dut1 |vpiFullName:work@and_tb.dut1 |vpiDefName:work@dut @@ -1846,7 +1846,7 @@ design: (work@and_tb) |vpiNet: \_logic_net: (work@and_tb.dut1.a), line:1:24, endln:1:25 |vpiParent: - \_module: work@dut (work@and_tb.dut1), file:${SURELOG_DIR}/tests/OneAnd/tb.v, line:28:3, endln:28:19 + \_module_inst: work@dut (work@and_tb.dut1), file:${SURELOG_DIR}/tests/OneAnd/tb.v, line:28:3, endln:28:19 |vpiTypespec: \_logic_typespec: , line:1:18, endln:1:23 |vpiName:a @@ -1855,7 +1855,7 @@ design: (work@and_tb) |vpiNet: \_logic_net: (work@and_tb.dut1.b), line:1:39, endln:1:40 |vpiParent: - \_module: work@dut (work@and_tb.dut1), file:${SURELOG_DIR}/tests/OneAnd/tb.v, line:28:3, endln:28:19 + \_module_inst: work@dut (work@and_tb.dut1), file:${SURELOG_DIR}/tests/OneAnd/tb.v, line:28:3, endln:28:19 |vpiTypespec: \_logic_typespec: , line:1:33, endln:1:38 |vpiName:b @@ -1864,18 +1864,18 @@ design: (work@and_tb) |vpiNet: \_logic_net: (work@and_tb.dut1.o), line:1:55, endln:1:56 |vpiParent: - \_module: work@dut (work@and_tb.dut1), file:${SURELOG_DIR}/tests/OneAnd/tb.v, line:28:3, endln:28:19 + \_module_inst: work@dut (work@and_tb.dut1), file:${SURELOG_DIR}/tests/OneAnd/tb.v, line:28:3, endln:28:19 |vpiTypespec: \_logic_typespec: , line:1:49, endln:1:54 |vpiName:o |vpiFullName:work@and_tb.dut1.o |vpiNetType:36 |vpiInstance: - \_module: work@and_tb (work@and_tb), file:${SURELOG_DIR}/tests/OneAnd/tb.v, line:1:1, endln:30:10 + \_module_inst: work@and_tb (work@and_tb), file:${SURELOG_DIR}/tests/OneAnd/tb.v, line:1:1, endln:30:10 |vpiPort: \_port: (a), line:1:24, endln:1:25 |vpiParent: - \_module: work@dut (work@and_tb.dut1), file:${SURELOG_DIR}/tests/OneAnd/tb.v, line:28:3, endln:28:19 + \_module_inst: work@dut (work@and_tb.dut1), file:${SURELOG_DIR}/tests/OneAnd/tb.v, line:28:3, endln:28:19 |vpiName:a |vpiDirection:1 |vpiHighConn: @@ -1897,11 +1897,11 @@ design: (work@and_tb) |vpiTypedef: \_logic_typespec: , line:1:18, endln:1:23 |vpiInstance: - \_module: work@dut (work@and_tb.dut1), file:${SURELOG_DIR}/tests/OneAnd/tb.v, line:28:3, endln:28:19 + \_module_inst: work@dut (work@and_tb.dut1), file:${SURELOG_DIR}/tests/OneAnd/tb.v, line:28:3, endln:28:19 |vpiPort: \_port: (b), line:1:39, endln:1:40 |vpiParent: - \_module: work@dut (work@and_tb.dut1), file:${SURELOG_DIR}/tests/OneAnd/tb.v, line:28:3, endln:28:19 + \_module_inst: work@dut (work@and_tb.dut1), file:${SURELOG_DIR}/tests/OneAnd/tb.v, line:28:3, endln:28:19 |vpiName:b |vpiDirection:1 |vpiHighConn: @@ -1923,11 +1923,11 @@ design: (work@and_tb) |vpiTypedef: \_logic_typespec: , line:1:33, endln:1:38 |vpiInstance: - \_module: work@dut (work@and_tb.dut1), file:${SURELOG_DIR}/tests/OneAnd/tb.v, line:28:3, endln:28:19 + \_module_inst: work@dut (work@and_tb.dut1), file:${SURELOG_DIR}/tests/OneAnd/tb.v, line:28:3, endln:28:19 |vpiPort: \_port: (o), line:1:55, endln:1:56 |vpiParent: - \_module: work@dut (work@and_tb.dut1), file:${SURELOG_DIR}/tests/OneAnd/tb.v, line:28:3, endln:28:19 + \_module_inst: work@dut (work@and_tb.dut1), file:${SURELOG_DIR}/tests/OneAnd/tb.v, line:28:3, endln:28:19 |vpiName:o |vpiDirection:2 |vpiHighConn: @@ -1949,11 +1949,11 @@ design: (work@and_tb) |vpiTypedef: \_logic_typespec: , line:1:49, endln:1:54 |vpiInstance: - \_module: work@dut (work@and_tb.dut1), file:${SURELOG_DIR}/tests/OneAnd/tb.v, line:28:3, endln:28:19 + \_module_inst: work@dut (work@and_tb.dut1), file:${SURELOG_DIR}/tests/OneAnd/tb.v, line:28:3, endln:28:19 |vpiContAssign: \_cont_assign: , line:3:10, endln:3:19 |vpiParent: - \_module: work@dut (work@and_tb.dut1), file:${SURELOG_DIR}/tests/OneAnd/tb.v, line:28:3, endln:28:19 + \_module_inst: work@dut (work@and_tb.dut1), file:${SURELOG_DIR}/tests/OneAnd/tb.v, line:28:3, endln:28:19 |vpiRhs: \_operation: , line:3:14, endln:3:19 |vpiParent: diff --git a/tests/OneClock/OneClock.log b/tests/OneClock/OneClock.log index 56677c3513..cd2d704f31 100644 --- a/tests/OneClock/OneClock.log +++ b/tests/OneClock/OneClock.log @@ -32,7 +32,7 @@ design 1 initial 2 logic_net 2 logic_typespec 1 -module 2 +module_inst 2 operation 1 ref_obj 4 sys_func_call 3 @@ -49,7 +49,7 @@ sys_func_call 3 design: (work@tb) |vpiName:work@tb |uhdmallModules: -\_module: work@tb (work@tb), file:${SURELOG_DIR}/tests/OneClock/tb.v, line:2:1, endln:19:10 +\_module_inst: work@tb (work@tb), file:${SURELOG_DIR}/tests/OneClock/tb.v, line:2:1, endln:19:10 |vpiParent: \_design: (work@tb) |vpiFullName:work@tb @@ -57,14 +57,14 @@ design: (work@tb) |vpiNet: \_logic_net: (work@tb.clk), line:3:7, endln:3:10 |vpiParent: - \_module: work@tb (work@tb), file:${SURELOG_DIR}/tests/OneClock/tb.v, line:2:1, endln:19:10 + \_module_inst: work@tb (work@tb), file:${SURELOG_DIR}/tests/OneClock/tb.v, line:2:1, endln:19:10 |vpiName:clk |vpiFullName:work@tb.clk |vpiNetType:48 |vpiProcess: \_initial: , line:5:3, endln:8:6 |vpiParent: - \_module: work@tb (work@tb), file:${SURELOG_DIR}/tests/OneClock/tb.v, line:2:1, endln:19:10 + \_module_inst: work@tb (work@tb), file:${SURELOG_DIR}/tests/OneClock/tb.v, line:2:1, endln:19:10 |vpiStmt: \_begin: (work@tb), line:5:11, endln:8:6 |vpiParent: @@ -109,7 +109,7 @@ design: (work@tb) |vpiProcess: \_initial: , line:10:3, endln:13:6 |vpiParent: - \_module: work@tb (work@tb), file:${SURELOG_DIR}/tests/OneClock/tb.v, line:2:1, endln:19:10 + \_module_inst: work@tb (work@tb), file:${SURELOG_DIR}/tests/OneClock/tb.v, line:2:1, endln:19:10 |vpiStmt: \_begin: (work@tb), line:11:3, endln:13:6 |vpiParent: @@ -140,7 +140,7 @@ design: (work@tb) |vpiProcess: \_always: , line:15:3, endln:16:19 |vpiParent: - \_module: work@tb (work@tb), file:${SURELOG_DIR}/tests/OneClock/tb.v, line:2:1, endln:19:10 + \_module_inst: work@tb (work@tb), file:${SURELOG_DIR}/tests/OneClock/tb.v, line:2:1, endln:19:10 |vpiStmt: \_delay_control: , line:16:5, endln:16:7 |vpiParent: @@ -175,14 +175,14 @@ design: (work@tb) \_logic_net: (work@tb.clk), line:3:7, endln:3:10 |vpiAlwaysType:1 |uhdmtopModules: -\_module: work@tb (work@tb), file:${SURELOG_DIR}/tests/OneClock/tb.v, line:2:1, endln:19:10 +\_module_inst: work@tb (work@tb), file:${SURELOG_DIR}/tests/OneClock/tb.v, line:2:1, endln:19:10 |vpiName:work@tb |vpiDefName:work@tb |vpiTop:1 |vpiNet: \_logic_net: (work@tb.clk), line:3:7, endln:3:10 |vpiParent: - \_module: work@tb (work@tb), file:${SURELOG_DIR}/tests/OneClock/tb.v, line:2:1, endln:19:10 + \_module_inst: work@tb (work@tb), file:${SURELOG_DIR}/tests/OneClock/tb.v, line:2:1, endln:19:10 |vpiTypespec: \_logic_typespec: , line:3:3, endln:3:6 |vpiName:clk diff --git a/tests/OneDivider/OneDivider.log b/tests/OneDivider/OneDivider.log index 08a26c9ceb..5a01671cec 100644 --- a/tests/OneDivider/OneDivider.log +++ b/tests/OneDivider/OneDivider.log @@ -40,7 +40,7 @@ initial 2 logic_net 10 logic_typespec 12 logic_var 2 -module 4 +module_inst 4 operation 7 port 6 property_spec 1 @@ -59,7 +59,7 @@ sys_func_call 7 design: (work@tb) |vpiName:work@tb |uhdmallModules: -\_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/OneDivider/dut.v, line:1:1, endln:10:10 +\_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/OneDivider/dut.v, line:1:1, endln:10:10 |vpiParent: \_design: (work@tb) |vpiFullName:work@dut @@ -67,28 +67,28 @@ design: (work@tb) |vpiNet: \_logic_net: (work@dut.rstn), line:1:24, endln:1:28 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/OneDivider/dut.v, line:1:1, endln:10:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/OneDivider/dut.v, line:1:1, endln:10:10 |vpiName:rstn |vpiFullName:work@dut.rstn |vpiNetType:36 |vpiNet: \_logic_net: (work@dut.clk), line:2:24, endln:2:27 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/OneDivider/dut.v, line:1:1, endln:10:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/OneDivider/dut.v, line:1:1, endln:10:10 |vpiName:clk |vpiFullName:work@dut.clk |vpiNetType:36 |vpiNet: \_logic_net: (work@dut.div), line:3:23, endln:3:26 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/OneDivider/dut.v, line:1:1, endln:10:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/OneDivider/dut.v, line:1:1, endln:10:10 |vpiName:div |vpiFullName:work@dut.div |vpiNetType:48 |vpiPort: \_port: (rstn), line:1:24, endln:1:28 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/OneDivider/dut.v, line:1:1, endln:10:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/OneDivider/dut.v, line:1:1, endln:10:10 |vpiName:rstn |vpiDirection:1 |vpiLowConn: @@ -100,7 +100,7 @@ design: (work@tb) |vpiPort: \_port: (clk), line:2:24, endln:2:27 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/OneDivider/dut.v, line:1:1, endln:10:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/OneDivider/dut.v, line:1:1, endln:10:10 |vpiName:clk |vpiDirection:1 |vpiLowConn: @@ -112,7 +112,7 @@ design: (work@tb) |vpiPort: \_port: (div), line:3:23, endln:3:26 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/OneDivider/dut.v, line:1:1, endln:10:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/OneDivider/dut.v, line:1:1, endln:10:10 |vpiName:div |vpiDirection:2 |vpiLowConn: @@ -124,7 +124,7 @@ design: (work@tb) |vpiProcess: \_always: , line:5:1, endln:9:23 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/OneDivider/dut.v, line:1:1, endln:10:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/OneDivider/dut.v, line:1:1, endln:10:10 |vpiStmt: \_event_control: , line:5:8, endln:5:39 |vpiParent: @@ -220,7 +220,7 @@ design: (work@tb) \_logic_net: (work@tb.dut1.div), line:3:23, endln:3:26 |vpiAlwaysType:1 |uhdmallModules: -\_module: work@tb (work@tb), file:${SURELOG_DIR}/tests/OneDivider/tb.v, line:1:1, endln:30:10 +\_module_inst: work@tb (work@tb), file:${SURELOG_DIR}/tests/OneDivider/tb.v, line:1:1, endln:30:10 |vpiParent: \_design: (work@tb) |vpiFullName:work@tb @@ -228,28 +228,28 @@ design: (work@tb) |vpiNet: \_logic_net: (work@tb.clk), line:2:7, endln:2:10 |vpiParent: - \_module: work@tb (work@tb), file:${SURELOG_DIR}/tests/OneDivider/tb.v, line:1:1, endln:30:10 + \_module_inst: work@tb (work@tb), file:${SURELOG_DIR}/tests/OneDivider/tb.v, line:1:1, endln:30:10 |vpiName:clk |vpiFullName:work@tb.clk |vpiNetType:48 |vpiNet: \_logic_net: (work@tb.div), line:3:9, endln:3:12 |vpiParent: - \_module: work@tb (work@tb), file:${SURELOG_DIR}/tests/OneDivider/tb.v, line:1:1, endln:30:10 + \_module_inst: work@tb (work@tb), file:${SURELOG_DIR}/tests/OneDivider/tb.v, line:1:1, endln:30:10 |vpiName:div |vpiFullName:work@tb.div |vpiNetType:36 |vpiNet: \_logic_net: (work@tb.rstn), line:4:9, endln:4:13 |vpiParent: - \_module: work@tb (work@tb), file:${SURELOG_DIR}/tests/OneDivider/tb.v, line:1:1, endln:30:10 + \_module_inst: work@tb (work@tb), file:${SURELOG_DIR}/tests/OneDivider/tb.v, line:1:1, endln:30:10 |vpiName:rstn |vpiFullName:work@tb.rstn |vpiNetType:36 |vpiAssertion: \_assert_stmt: (work@tb.ap_div2), line:28:3, endln:28:112 |vpiParent: - \_module: work@tb (work@tb), file:${SURELOG_DIR}/tests/OneDivider/tb.v, line:1:1, endln:30:10 + \_module_inst: work@tb (work@tb), file:${SURELOG_DIR}/tests/OneDivider/tb.v, line:1:1, endln:30:10 |vpiName:ap_div2 |vpiFullName:work@tb.ap_div2 |vpiStmt: @@ -297,7 +297,7 @@ design: (work@tb) |vpiProcess: \_initial: , line:5:3, endln:10:6 |vpiParent: - \_module: work@tb (work@tb), file:${SURELOG_DIR}/tests/OneDivider/tb.v, line:1:1, endln:30:10 + \_module_inst: work@tb (work@tb), file:${SURELOG_DIR}/tests/OneDivider/tb.v, line:1:1, endln:30:10 |vpiStmt: \_begin: (work@tb), line:5:11, endln:10:6 |vpiParent: @@ -368,7 +368,7 @@ design: (work@tb) |vpiProcess: \_initial: , line:12:3, endln:17:6 |vpiParent: - \_module: work@tb (work@tb), file:${SURELOG_DIR}/tests/OneDivider/tb.v, line:1:1, endln:30:10 + \_module_inst: work@tb (work@tb), file:${SURELOG_DIR}/tests/OneDivider/tb.v, line:1:1, endln:30:10 |vpiStmt: \_begin: (work@tb), line:13:3, endln:17:6 |vpiParent: @@ -448,7 +448,7 @@ design: (work@tb) |vpiProcess: \_always: , line:19:3, endln:20:19 |vpiParent: - \_module: work@tb (work@tb), file:${SURELOG_DIR}/tests/OneDivider/tb.v, line:1:1, endln:30:10 + \_module_inst: work@tb (work@tb), file:${SURELOG_DIR}/tests/OneDivider/tb.v, line:1:1, endln:30:10 |vpiStmt: \_delay_control: , line:20:5, endln:20:7 |vpiParent: @@ -483,12 +483,12 @@ design: (work@tb) \_logic_net: (work@tb.clk), line:2:7, endln:2:10 |vpiAlwaysType:1 |uhdmtopModules: -\_module: work@tb (work@tb), file:${SURELOG_DIR}/tests/OneDivider/tb.v, line:1:1, endln:30:10 +\_module_inst: work@tb (work@tb), file:${SURELOG_DIR}/tests/OneDivider/tb.v, line:1:1, endln:30:10 |vpiName:work@tb |vpiVariables: \_logic_var: (work@tb.div), line:3:9, endln:3:12 |vpiParent: - \_module: work@tb (work@tb), file:${SURELOG_DIR}/tests/OneDivider/tb.v, line:1:1, endln:30:10 + \_module_inst: work@tb (work@tb), file:${SURELOG_DIR}/tests/OneDivider/tb.v, line:1:1, endln:30:10 |vpiTypespec: \_logic_typespec: , line:3:3, endln:3:8 |vpiName:div @@ -497,7 +497,7 @@ design: (work@tb) |vpiVariables: \_logic_var: (work@tb.rstn), line:4:9, endln:4:13 |vpiParent: - \_module: work@tb (work@tb), file:${SURELOG_DIR}/tests/OneDivider/tb.v, line:1:1, endln:30:10 + \_module_inst: work@tb (work@tb), file:${SURELOG_DIR}/tests/OneDivider/tb.v, line:1:1, endln:30:10 |vpiTypespec: \_logic_typespec: , line:4:3, endln:4:8 |vpiName:rstn @@ -508,7 +508,7 @@ design: (work@tb) |vpiNet: \_logic_net: (work@tb.clk), line:2:7, endln:2:10 |vpiParent: - \_module: work@tb (work@tb), file:${SURELOG_DIR}/tests/OneDivider/tb.v, line:1:1, endln:30:10 + \_module_inst: work@tb (work@tb), file:${SURELOG_DIR}/tests/OneDivider/tb.v, line:1:1, endln:30:10 |vpiTypespec: \_logic_typespec: , line:2:3, endln:2:6 |vpiName:clk @@ -521,10 +521,10 @@ design: (work@tb) \_initial: , line:12:3, endln:17:6 |vpiProcess: \_always: , line:19:3, endln:20:19 - |vpiModule: - \_module: work@dut (work@tb.dut1), file:${SURELOG_DIR}/tests/OneDivider/tb.v, line:22:3, endln:22:28 + |vpiModuleInst: + \_module_inst: work@dut (work@tb.dut1), file:${SURELOG_DIR}/tests/OneDivider/tb.v, line:22:3, endln:22:28 |vpiParent: - \_module: work@tb (work@tb), file:${SURELOG_DIR}/tests/OneDivider/tb.v, line:1:1, endln:30:10 + \_module_inst: work@tb (work@tb), file:${SURELOG_DIR}/tests/OneDivider/tb.v, line:1:1, endln:30:10 |vpiName:dut1 |vpiFullName:work@tb.dut1 |vpiDefName:work@dut @@ -533,7 +533,7 @@ design: (work@tb) |vpiNet: \_logic_net: (work@tb.dut1.rstn), line:1:24, endln:1:28 |vpiParent: - \_module: work@dut (work@tb.dut1), file:${SURELOG_DIR}/tests/OneDivider/tb.v, line:22:3, endln:22:28 + \_module_inst: work@dut (work@tb.dut1), file:${SURELOG_DIR}/tests/OneDivider/tb.v, line:22:3, endln:22:28 |vpiTypespec: \_logic_typespec: , line:1:18, endln:1:23 |vpiName:rstn @@ -542,7 +542,7 @@ design: (work@tb) |vpiNet: \_logic_net: (work@tb.dut1.clk), line:2:24, endln:2:27 |vpiParent: - \_module: work@dut (work@tb.dut1), file:${SURELOG_DIR}/tests/OneDivider/tb.v, line:22:3, endln:22:28 + \_module_inst: work@dut (work@tb.dut1), file:${SURELOG_DIR}/tests/OneDivider/tb.v, line:22:3, endln:22:28 |vpiTypespec: \_logic_typespec: , line:2:18, endln:2:23 |vpiName:clk @@ -551,18 +551,18 @@ design: (work@tb) |vpiNet: \_logic_net: (work@tb.dut1.div), line:3:23, endln:3:26 |vpiParent: - \_module: work@dut (work@tb.dut1), file:${SURELOG_DIR}/tests/OneDivider/tb.v, line:22:3, endln:22:28 + \_module_inst: work@dut (work@tb.dut1), file:${SURELOG_DIR}/tests/OneDivider/tb.v, line:22:3, endln:22:28 |vpiTypespec: \_logic_typespec: , line:3:19, endln:3:22 |vpiName:div |vpiFullName:work@tb.dut1.div |vpiNetType:48 |vpiInstance: - \_module: work@tb (work@tb), file:${SURELOG_DIR}/tests/OneDivider/tb.v, line:1:1, endln:30:10 + \_module_inst: work@tb (work@tb), file:${SURELOG_DIR}/tests/OneDivider/tb.v, line:1:1, endln:30:10 |vpiPort: \_port: (rstn), line:1:24, endln:1:28 |vpiParent: - \_module: work@dut (work@tb.dut1), file:${SURELOG_DIR}/tests/OneDivider/tb.v, line:22:3, endln:22:28 + \_module_inst: work@dut (work@tb.dut1), file:${SURELOG_DIR}/tests/OneDivider/tb.v, line:22:3, endln:22:28 |vpiName:rstn |vpiDirection:1 |vpiHighConn: @@ -582,7 +582,7 @@ design: (work@tb) |vpiPort: \_port: (clk), line:2:24, endln:2:27 |vpiParent: - \_module: work@dut (work@tb.dut1), file:${SURELOG_DIR}/tests/OneDivider/tb.v, line:22:3, endln:22:28 + \_module_inst: work@dut (work@tb.dut1), file:${SURELOG_DIR}/tests/OneDivider/tb.v, line:22:3, endln:22:28 |vpiName:clk |vpiDirection:1 |vpiHighConn: @@ -602,7 +602,7 @@ design: (work@tb) |vpiPort: \_port: (div), line:3:23, endln:3:26 |vpiParent: - \_module: work@dut (work@tb.dut1), file:${SURELOG_DIR}/tests/OneDivider/tb.v, line:22:3, endln:22:28 + \_module_inst: work@dut (work@tb.dut1), file:${SURELOG_DIR}/tests/OneDivider/tb.v, line:22:3, endln:22:28 |vpiName:div |vpiDirection:2 |vpiHighConn: diff --git a/tests/OneFF/OneFF.log b/tests/OneFF/OneFF.log index 1d8a058ba8..2858f1f90f 100644 --- a/tests/OneFF/OneFF.log +++ b/tests/OneFF/OneFF.log @@ -40,7 +40,7 @@ initial 2 logic_net 14 logic_typespec 16 logic_var 2 -module 4 +module_inst 4 operation 8 port 8 ref_obj 31 @@ -58,7 +58,7 @@ sys_func_call 11 design: (work@tb) |vpiName:work@tb |uhdmallModules: -\_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/OneFF/dut.v, line:2:1, endln:14:10 +\_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/OneFF/dut.v, line:2:1, endln:14:10 |vpiParent: \_design: (work@tb) |vpiFullName:work@dut @@ -66,32 +66,32 @@ design: (work@tb) |vpiNet: \_logic_net: (work@dut.d), line:2:20, endln:2:21 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/OneFF/dut.v, line:2:1, endln:14:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/OneFF/dut.v, line:2:1, endln:14:10 |vpiName:d |vpiFullName:work@dut.d |vpiNet: \_logic_net: (work@dut.rstn), line:3:21, endln:3:25 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/OneFF/dut.v, line:2:1, endln:14:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/OneFF/dut.v, line:2:1, endln:14:10 |vpiName:rstn |vpiFullName:work@dut.rstn |vpiNet: \_logic_net: (work@dut.clk), line:4:21, endln:4:24 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/OneFF/dut.v, line:2:1, endln:14:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/OneFF/dut.v, line:2:1, endln:14:10 |vpiName:clk |vpiFullName:work@dut.clk |vpiNet: \_logic_net: (work@dut.q), line:5:26, endln:5:27 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/OneFF/dut.v, line:2:1, endln:14:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/OneFF/dut.v, line:2:1, endln:14:10 |vpiName:q |vpiFullName:work@dut.q |vpiNetType:48 |vpiPort: \_port: (d), line:2:20, endln:2:21 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/OneFF/dut.v, line:2:1, endln:14:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/OneFF/dut.v, line:2:1, endln:14:10 |vpiName:d |vpiDirection:1 |vpiLowConn: @@ -103,7 +103,7 @@ design: (work@tb) |vpiPort: \_port: (rstn), line:3:21, endln:3:25 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/OneFF/dut.v, line:2:1, endln:14:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/OneFF/dut.v, line:2:1, endln:14:10 |vpiName:rstn |vpiDirection:1 |vpiLowConn: @@ -115,7 +115,7 @@ design: (work@tb) |vpiPort: \_port: (clk), line:4:21, endln:4:24 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/OneFF/dut.v, line:2:1, endln:14:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/OneFF/dut.v, line:2:1, endln:14:10 |vpiName:clk |vpiDirection:1 |vpiLowConn: @@ -127,7 +127,7 @@ design: (work@tb) |vpiPort: \_port: (q), line:5:26, endln:5:27 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/OneFF/dut.v, line:2:1, endln:14:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/OneFF/dut.v, line:2:1, endln:14:10 |vpiName:q |vpiDirection:2 |vpiLowConn: @@ -139,7 +139,7 @@ design: (work@tb) |vpiProcess: \_always: , line:7:3, endln:13:10 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/OneFF/dut.v, line:2:1, endln:14:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/OneFF/dut.v, line:2:1, endln:14:10 |vpiStmt: \_event_control: , line:7:10, endln:7:41 |vpiParent: @@ -235,7 +235,7 @@ design: (work@tb) \_logic_net: (work@tb.dut1.q), line:5:26, endln:5:27 |vpiAlwaysType:1 |uhdmallModules: -\_module: work@tb (work@tb), file:${SURELOG_DIR}/tests/OneFF/tb.v, line:2:1, endln:33:10 +\_module_inst: work@tb (work@tb), file:${SURELOG_DIR}/tests/OneFF/tb.v, line:2:1, endln:33:10 |vpiParent: \_design: (work@tb) |vpiFullName:work@tb @@ -243,35 +243,35 @@ design: (work@tb) |vpiNet: \_logic_net: (work@tb.clk), line:3:7, endln:3:10 |vpiParent: - \_module: work@tb (work@tb), file:${SURELOG_DIR}/tests/OneFF/tb.v, line:2:1, endln:33:10 + \_module_inst: work@tb (work@tb), file:${SURELOG_DIR}/tests/OneFF/tb.v, line:2:1, endln:33:10 |vpiName:clk |vpiFullName:work@tb.clk |vpiNetType:48 |vpiNet: \_logic_net: (work@tb.rstn), line:4:9, endln:4:13 |vpiParent: - \_module: work@tb (work@tb), file:${SURELOG_DIR}/tests/OneFF/tb.v, line:2:1, endln:33:10 + \_module_inst: work@tb (work@tb), file:${SURELOG_DIR}/tests/OneFF/tb.v, line:2:1, endln:33:10 |vpiName:rstn |vpiFullName:work@tb.rstn |vpiNetType:36 |vpiNet: \_logic_net: (work@tb.d), line:5:9, endln:5:10 |vpiParent: - \_module: work@tb (work@tb), file:${SURELOG_DIR}/tests/OneFF/tb.v, line:2:1, endln:33:10 + \_module_inst: work@tb (work@tb), file:${SURELOG_DIR}/tests/OneFF/tb.v, line:2:1, endln:33:10 |vpiName:d |vpiFullName:work@tb.d |vpiNetType:36 |vpiNet: \_logic_net: (work@tb.o), line:6:7, endln:6:8 |vpiParent: - \_module: work@tb (work@tb), file:${SURELOG_DIR}/tests/OneFF/tb.v, line:2:1, endln:33:10 + \_module_inst: work@tb (work@tb), file:${SURELOG_DIR}/tests/OneFF/tb.v, line:2:1, endln:33:10 |vpiName:o |vpiFullName:work@tb.o |vpiNetType:48 |vpiProcess: \_initial: , line:8:3, endln:13:6 |vpiParent: - \_module: work@tb (work@tb), file:${SURELOG_DIR}/tests/OneFF/tb.v, line:2:1, endln:33:10 + \_module_inst: work@tb (work@tb), file:${SURELOG_DIR}/tests/OneFF/tb.v, line:2:1, endln:33:10 |vpiStmt: \_begin: (work@tb), line:8:11, endln:13:6 |vpiParent: @@ -342,7 +342,7 @@ design: (work@tb) |vpiProcess: \_initial: , line:15:3, endln:26:6 |vpiParent: - \_module: work@tb (work@tb), file:${SURELOG_DIR}/tests/OneFF/tb.v, line:2:1, endln:33:10 + \_module_inst: work@tb (work@tb), file:${SURELOG_DIR}/tests/OneFF/tb.v, line:2:1, endln:33:10 |vpiStmt: \_begin: (work@tb), line:16:5, endln:26:6 |vpiParent: @@ -685,7 +685,7 @@ design: (work@tb) |vpiProcess: \_always: , line:28:3, endln:29:19 |vpiParent: - \_module: work@tb (work@tb), file:${SURELOG_DIR}/tests/OneFF/tb.v, line:2:1, endln:33:10 + \_module_inst: work@tb (work@tb), file:${SURELOG_DIR}/tests/OneFF/tb.v, line:2:1, endln:33:10 |vpiStmt: \_delay_control: , line:29:5, endln:29:7 |vpiParent: @@ -720,12 +720,12 @@ design: (work@tb) \_logic_net: (work@tb.clk), line:3:7, endln:3:10 |vpiAlwaysType:1 |uhdmtopModules: -\_module: work@tb (work@tb), file:${SURELOG_DIR}/tests/OneFF/tb.v, line:2:1, endln:33:10 +\_module_inst: work@tb (work@tb), file:${SURELOG_DIR}/tests/OneFF/tb.v, line:2:1, endln:33:10 |vpiName:work@tb |vpiVariables: \_logic_var: (work@tb.rstn), line:4:9, endln:4:13 |vpiParent: - \_module: work@tb (work@tb), file:${SURELOG_DIR}/tests/OneFF/tb.v, line:2:1, endln:33:10 + \_module_inst: work@tb (work@tb), file:${SURELOG_DIR}/tests/OneFF/tb.v, line:2:1, endln:33:10 |vpiTypespec: \_logic_typespec: , line:4:3, endln:4:8 |vpiName:rstn @@ -734,7 +734,7 @@ design: (work@tb) |vpiVariables: \_logic_var: (work@tb.d), line:5:9, endln:5:10 |vpiParent: - \_module: work@tb (work@tb), file:${SURELOG_DIR}/tests/OneFF/tb.v, line:2:1, endln:33:10 + \_module_inst: work@tb (work@tb), file:${SURELOG_DIR}/tests/OneFF/tb.v, line:2:1, endln:33:10 |vpiTypespec: \_logic_typespec: , line:5:3, endln:5:8 |vpiName:d @@ -745,7 +745,7 @@ design: (work@tb) |vpiNet: \_logic_net: (work@tb.clk), line:3:7, endln:3:10 |vpiParent: - \_module: work@tb (work@tb), file:${SURELOG_DIR}/tests/OneFF/tb.v, line:2:1, endln:33:10 + \_module_inst: work@tb (work@tb), file:${SURELOG_DIR}/tests/OneFF/tb.v, line:2:1, endln:33:10 |vpiTypespec: \_logic_typespec: , line:3:3, endln:3:6 |vpiName:clk @@ -754,7 +754,7 @@ design: (work@tb) |vpiNet: \_logic_net: (work@tb.o), line:6:7, endln:6:8 |vpiParent: - \_module: work@tb (work@tb), file:${SURELOG_DIR}/tests/OneFF/tb.v, line:2:1, endln:33:10 + \_module_inst: work@tb (work@tb), file:${SURELOG_DIR}/tests/OneFF/tb.v, line:2:1, endln:33:10 |vpiTypespec: \_logic_typespec: , line:6:3, endln:6:6 |vpiName:o @@ -767,10 +767,10 @@ design: (work@tb) \_initial: , line:15:3, endln:26:6 |vpiProcess: \_always: , line:28:3, endln:29:19 - |vpiModule: - \_module: work@dut (work@tb.dut1), file:${SURELOG_DIR}/tests/OneFF/tb.v, line:31:3, endln:31:29 + |vpiModuleInst: + \_module_inst: work@dut (work@tb.dut1), file:${SURELOG_DIR}/tests/OneFF/tb.v, line:31:3, endln:31:29 |vpiParent: - \_module: work@tb (work@tb), file:${SURELOG_DIR}/tests/OneFF/tb.v, line:2:1, endln:33:10 + \_module_inst: work@tb (work@tb), file:${SURELOG_DIR}/tests/OneFF/tb.v, line:2:1, endln:33:10 |vpiName:dut1 |vpiFullName:work@tb.dut1 |vpiDefName:work@dut @@ -779,7 +779,7 @@ design: (work@tb) |vpiNet: \_logic_net: (work@tb.dut1.d), line:2:20, endln:2:21 |vpiParent: - \_module: work@dut (work@tb.dut1), file:${SURELOG_DIR}/tests/OneFF/tb.v, line:31:3, endln:31:29 + \_module_inst: work@dut (work@tb.dut1), file:${SURELOG_DIR}/tests/OneFF/tb.v, line:31:3, endln:31:29 |vpiTypespec: \_logic_typespec: , line:2:20, endln:2:20 |vpiName:d @@ -787,7 +787,7 @@ design: (work@tb) |vpiNet: \_logic_net: (work@tb.dut1.rstn), line:3:21, endln:3:25 |vpiParent: - \_module: work@dut (work@tb.dut1), file:${SURELOG_DIR}/tests/OneFF/tb.v, line:31:3, endln:31:29 + \_module_inst: work@dut (work@tb.dut1), file:${SURELOG_DIR}/tests/OneFF/tb.v, line:31:3, endln:31:29 |vpiTypespec: \_logic_typespec: , line:3:21, endln:3:21 |vpiName:rstn @@ -795,7 +795,7 @@ design: (work@tb) |vpiNet: \_logic_net: (work@tb.dut1.clk), line:4:21, endln:4:24 |vpiParent: - \_module: work@dut (work@tb.dut1), file:${SURELOG_DIR}/tests/OneFF/tb.v, line:31:3, endln:31:29 + \_module_inst: work@dut (work@tb.dut1), file:${SURELOG_DIR}/tests/OneFF/tb.v, line:31:3, endln:31:29 |vpiTypespec: \_logic_typespec: , line:4:21, endln:4:21 |vpiName:clk @@ -803,18 +803,18 @@ design: (work@tb) |vpiNet: \_logic_net: (work@tb.dut1.q), line:5:26, endln:5:27 |vpiParent: - \_module: work@dut (work@tb.dut1), file:${SURELOG_DIR}/tests/OneFF/tb.v, line:31:3, endln:31:29 + \_module_inst: work@dut (work@tb.dut1), file:${SURELOG_DIR}/tests/OneFF/tb.v, line:31:3, endln:31:29 |vpiTypespec: \_logic_typespec: , line:5:22, endln:5:25 |vpiName:q |vpiFullName:work@tb.dut1.q |vpiNetType:48 |vpiInstance: - \_module: work@tb (work@tb), file:${SURELOG_DIR}/tests/OneFF/tb.v, line:2:1, endln:33:10 + \_module_inst: work@tb (work@tb), file:${SURELOG_DIR}/tests/OneFF/tb.v, line:2:1, endln:33:10 |vpiPort: \_port: (d), line:2:20, endln:2:21 |vpiParent: - \_module: work@dut (work@tb.dut1), file:${SURELOG_DIR}/tests/OneFF/tb.v, line:31:3, endln:31:29 + \_module_inst: work@dut (work@tb.dut1), file:${SURELOG_DIR}/tests/OneFF/tb.v, line:31:3, endln:31:29 |vpiName:d |vpiDirection:1 |vpiHighConn: @@ -834,7 +834,7 @@ design: (work@tb) |vpiPort: \_port: (rstn), line:3:21, endln:3:25 |vpiParent: - \_module: work@dut (work@tb.dut1), file:${SURELOG_DIR}/tests/OneFF/tb.v, line:31:3, endln:31:29 + \_module_inst: work@dut (work@tb.dut1), file:${SURELOG_DIR}/tests/OneFF/tb.v, line:31:3, endln:31:29 |vpiName:rstn |vpiDirection:1 |vpiHighConn: @@ -854,7 +854,7 @@ design: (work@tb) |vpiPort: \_port: (clk), line:4:21, endln:4:24 |vpiParent: - \_module: work@dut (work@tb.dut1), file:${SURELOG_DIR}/tests/OneFF/tb.v, line:31:3, endln:31:29 + \_module_inst: work@dut (work@tb.dut1), file:${SURELOG_DIR}/tests/OneFF/tb.v, line:31:3, endln:31:29 |vpiName:clk |vpiDirection:1 |vpiHighConn: @@ -874,7 +874,7 @@ design: (work@tb) |vpiPort: \_port: (q), line:5:26, endln:5:27 |vpiParent: - \_module: work@dut (work@tb.dut1), file:${SURELOG_DIR}/tests/OneFF/tb.v, line:31:3, endln:31:29 + \_module_inst: work@dut (work@tb.dut1), file:${SURELOG_DIR}/tests/OneFF/tb.v, line:31:3, endln:31:29 |vpiName:q |vpiDirection:2 |vpiHighConn: diff --git a/tests/OneImport/OneImport.log b/tests/OneImport/OneImport.log index aa856128d8..c8aa7c6c31 100644 --- a/tests/OneImport/OneImport.log +++ b/tests/OneImport/OneImport.log @@ -258,7 +258,7 @@ int_typespec 8 integer_typespec 4 logic_net 4 logic_typespec 8 -module 5 +module_inst 5 operation 8 package 3 param_assign 6 @@ -280,7 +280,7 @@ int_typespec 8 integer_typespec 4 logic_net 4 logic_typespec 8 -module 5 +module_inst 5 operation 12 package 3 param_assign 6 @@ -412,7 +412,7 @@ design: (work@dut) |vpiTypedef: \_enum_typespec: (my_pkg::opcode_e), line:2:3, endln:5:14 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/OneImport/dut.sv, line:11:1, endln:20:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/OneImport/dut.sv, line:11:1, endln:20:10 |vpiName:my_pkg::opcode_e |vpiInstance: \_package: my_pkg (my_pkg::), file:${SURELOG_DIR}/tests/OneImport/dut.sv, line:1:1, endln:9:11 @@ -453,14 +453,14 @@ design: (work@dut) |vpiDefName:my_pkg |vpiTop:1 |uhdmallModules: -\_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/OneImport/dut.sv, line:11:1, endln:20:10 +\_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/OneImport/dut.sv, line:11:1, endln:20:10 |vpiParent: \_design: (work@dut) |vpiFullName:work@dut |vpiParameter: \_parameter: (work@dut.PMP_CFG_W), line:7:24, endln:7:33 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/OneImport/dut.sv, line:11:1, endln:20:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/OneImport/dut.sv, line:11:1, endln:20:10 |UINT:2 |vpiTypespec: \_int_typespec: , line:7:11, endln:7:23 @@ -474,7 +474,7 @@ design: (work@dut) |vpiParamAssign: \_param_assign: , line:7:24, endln:7:37 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/OneImport/dut.sv, line:11:1, endln:20:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/OneImport/dut.sv, line:11:1, endln:20:10 |vpiRhs: \_constant: , line:7:36, endln:7:37 |vpiParent: @@ -517,21 +517,21 @@ design: (work@dut) |vpiNet: \_logic_net: (work@dut.a), line:16:14, endln:16:15 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/OneImport/dut.sv, line:11:1, endln:20:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/OneImport/dut.sv, line:11:1, endln:20:10 |vpiName:a |vpiFullName:work@dut.a |vpiNetType:1 |vpiNet: \_logic_net: (work@dut.b), line:17:13, endln:17:14 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/OneImport/dut.sv, line:11:1, endln:20:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/OneImport/dut.sv, line:11:1, endln:20:10 |vpiName:b |vpiFullName:work@dut.b |vpiNetType:48 |vpiPort: \_port: (a), line:11:13, endln:11:14 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/OneImport/dut.sv, line:11:1, endln:20:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/OneImport/dut.sv, line:11:1, endln:20:10 |vpiName:a |vpiDirection:1 |vpiLowConn: @@ -561,7 +561,7 @@ design: (work@dut) |vpiPort: \_port: (b), line:11:16, endln:11:17 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/OneImport/dut.sv, line:11:1, endln:20:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/OneImport/dut.sv, line:11:1, endln:20:10 |vpiName:b |vpiDirection:2 |vpiLowConn: @@ -591,7 +591,7 @@ design: (work@dut) |vpiContAssign: \_cont_assign: , line:18:10, endln:19:35 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/OneImport/dut.sv, line:11:1, endln:20:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/OneImport/dut.sv, line:11:1, endln:20:10 |vpiRhs: \_operation: , line:18:14, endln:19:35 |vpiParent: @@ -651,12 +651,12 @@ design: (work@dut) |vpiActual: \_logic_net: (work@dut.b), line:17:13, endln:17:14 |uhdmtopModules: -\_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/OneImport/dut.sv, line:11:1, endln:20:10 +\_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/OneImport/dut.sv, line:11:1, endln:20:10 |vpiName:work@dut |vpiParameter: \_parameter: (work@dut.PMP_CFG_W), line:7:24, endln:7:33 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/OneImport/dut.sv, line:11:1, endln:20:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/OneImport/dut.sv, line:11:1, endln:20:10 |UINT:2 |vpiTypespec: \_int_typespec: , line:7:11, endln:7:23 @@ -670,7 +670,7 @@ design: (work@dut) |vpiParamAssign: \_param_assign: , line:7:24, endln:7:37 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/OneImport/dut.sv, line:11:1, endln:20:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/OneImport/dut.sv, line:11:1, endln:20:10 |vpiRhs: \_constant: , line:7:36, endln:7:37 |vpiDecompile:2 @@ -696,7 +696,7 @@ design: (work@dut) |vpiNet: \_logic_net: (work@dut.a), line:16:14, endln:16:15 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/OneImport/dut.sv, line:11:1, endln:20:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/OneImport/dut.sv, line:11:1, endln:20:10 |vpiTypespec: \_logic_typespec: , line:16:3, endln:16:13 |vpiRange: @@ -723,7 +723,7 @@ design: (work@dut) |vpiNet: \_logic_net: (work@dut.b), line:17:13, endln:17:14 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/OneImport/dut.sv, line:11:1, endln:20:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/OneImport/dut.sv, line:11:1, endln:20:10 |vpiTypespec: \_logic_typespec: , line:17:3, endln:17:12 |vpiRange: @@ -751,7 +751,7 @@ design: (work@dut) |vpiPort: \_port: (a), line:11:13, endln:11:14 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/OneImport/dut.sv, line:11:1, endln:20:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/OneImport/dut.sv, line:11:1, endln:20:10 |vpiName:a |vpiDirection:1 |vpiLowConn: @@ -785,11 +785,11 @@ design: (work@dut) |UINT:0 |vpiConstType:9 |vpiInstance: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/OneImport/dut.sv, line:11:1, endln:20:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/OneImport/dut.sv, line:11:1, endln:20:10 |vpiPort: \_port: (b), line:11:16, endln:11:17 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/OneImport/dut.sv, line:11:1, endln:20:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/OneImport/dut.sv, line:11:1, endln:20:10 |vpiName:b |vpiDirection:2 |vpiLowConn: @@ -823,11 +823,11 @@ design: (work@dut) |UINT:0 |vpiConstType:9 |vpiInstance: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/OneImport/dut.sv, line:11:1, endln:20:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/OneImport/dut.sv, line:11:1, endln:20:10 |vpiContAssign: \_cont_assign: , line:18:10, endln:19:35 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/OneImport/dut.sv, line:11:1, endln:20:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/OneImport/dut.sv, line:11:1, endln:20:10 |vpiRhs: \_operation: , line:18:14, endln:19:35 |vpiParent: diff --git a/tests/OneNet/OneNet.log b/tests/OneNet/OneNet.log index d16009dffe..a9c0bf978f 100644 --- a/tests/OneNet/OneNet.log +++ b/tests/OneNet/OneNet.log @@ -27,7 +27,7 @@ cont_assign 1 design 1 logic_net 4 logic_typespec 6 -module 3 +module_inst 3 port 4 ref_obj 6 === UHDM Object Stats End === @@ -43,7 +43,7 @@ ref_obj 6 design: (work@dut) |vpiName:work@dut |uhdmallModules: -\_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/OneNet/dut.v, line:1:1, endln:3:10 +\_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/OneNet/dut.v, line:1:1, endln:3:10 |vpiParent: \_design: (work@dut) |vpiFullName:work@dut @@ -51,21 +51,21 @@ design: (work@dut) |vpiNet: \_logic_net: (work@dut.i), line:1:24, endln:1:25 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/OneNet/dut.v, line:1:1, endln:3:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/OneNet/dut.v, line:1:1, endln:3:10 |vpiName:i |vpiFullName:work@dut.i |vpiNetType:1 |vpiNet: \_logic_net: (work@dut.o), line:1:38, endln:1:39 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/OneNet/dut.v, line:1:1, endln:3:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/OneNet/dut.v, line:1:1, endln:3:10 |vpiName:o |vpiFullName:work@dut.o |vpiNetType:48 |vpiPort: \_port: (i), line:1:24, endln:1:25 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/OneNet/dut.v, line:1:1, endln:3:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/OneNet/dut.v, line:1:1, endln:3:10 |vpiName:i |vpiDirection:1 |vpiLowConn: @@ -77,7 +77,7 @@ design: (work@dut) |vpiPort: \_port: (o), line:1:38, endln:1:39 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/OneNet/dut.v, line:1:1, endln:3:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/OneNet/dut.v, line:1:1, endln:3:10 |vpiName:o |vpiDirection:2 |vpiLowConn: @@ -89,7 +89,7 @@ design: (work@dut) |vpiContAssign: \_cont_assign: , line:2:10, endln:2:15 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/OneNet/dut.v, line:1:1, endln:3:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/OneNet/dut.v, line:1:1, endln:3:10 |vpiRhs: \_ref_obj: (work@dut.i), line:2:14, endln:2:15 |vpiParent: @@ -107,14 +107,14 @@ design: (work@dut) |vpiActual: \_logic_net: (work@dut.o), line:1:38, endln:1:39 |uhdmtopModules: -\_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/OneNet/dut.v, line:1:1, endln:3:10 +\_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/OneNet/dut.v, line:1:1, endln:3:10 |vpiName:work@dut |vpiDefName:work@dut |vpiTop:1 |vpiNet: \_logic_net: (work@dut.i), line:1:24, endln:1:25 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/OneNet/dut.v, line:1:1, endln:3:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/OneNet/dut.v, line:1:1, endln:3:10 |vpiTypespec: \_logic_typespec: , line:1:19, endln:1:23 |vpiName:i @@ -123,7 +123,7 @@ design: (work@dut) |vpiNet: \_logic_net: (work@dut.o), line:1:38, endln:1:39 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/OneNet/dut.v, line:1:1, endln:3:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/OneNet/dut.v, line:1:1, endln:3:10 |vpiTypespec: \_logic_typespec: , line:1:34, endln:1:37 |vpiName:o @@ -133,7 +133,7 @@ design: (work@dut) |vpiPort: \_port: (i), line:1:24, endln:1:25 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/OneNet/dut.v, line:1:1, endln:3:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/OneNet/dut.v, line:1:1, endln:3:10 |vpiName:i |vpiDirection:1 |vpiLowConn: @@ -147,7 +147,7 @@ design: (work@dut) |vpiPort: \_port: (o), line:1:38, endln:1:39 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/OneNet/dut.v, line:1:1, endln:3:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/OneNet/dut.v, line:1:1, endln:3:10 |vpiName:o |vpiDirection:2 |vpiLowConn: diff --git a/tests/OneNetInterf/OneNetInterf.log b/tests/OneNetInterf/OneNetInterf.log index a83eeffe19..bbaf71bc94 100644 --- a/tests/OneNetInterf/OneNetInterf.log +++ b/tests/OneNetInterf/OneNetInterf.log @@ -58,11 +58,11 @@ design 1 hier_path 6 immediate_assert 2 initial 1 -interface 7 +interface_inst 7 interface_typespec 5 logic_net 29 logic_typespec 37 -module 18 +module_inst 18 operation 2 port 27 program 2 @@ -81,7 +81,7 @@ sys_func_call 9 design: (work@dut) |vpiName:work@dut |uhdmallInterfaces: -\_interface: work@ConnectTB (work@ConnectTB), file:${SURELOG_DIR}/tests/OneNetInterf/dut.v, line:7:1, endln:8:13 +\_interface_inst: work@ConnectTB (work@ConnectTB), file:${SURELOG_DIR}/tests/OneNetInterf/dut.v, line:7:1, endln:8:13 |vpiParent: \_design: (work@dut) |vpiFullName:work@ConnectTB @@ -89,21 +89,21 @@ design: (work@dut) |vpiNet: \_logic_net: (work@ConnectTB.con_i), line:7:33, endln:7:38 |vpiParent: - \_interface: work@ConnectTB (work@ConnectTB), file:${SURELOG_DIR}/tests/OneNetInterf/dut.v, line:7:1, endln:8:13 + \_interface_inst: work@ConnectTB (work@ConnectTB), file:${SURELOG_DIR}/tests/OneNetInterf/dut.v, line:7:1, endln:8:13 |vpiName:con_i |vpiFullName:work@ConnectTB.con_i |vpiNetType:1 |vpiNet: \_logic_net: (work@ConnectTB.con_o), line:7:51, endln:7:56 |vpiParent: - \_interface: work@ConnectTB (work@ConnectTB), file:${SURELOG_DIR}/tests/OneNetInterf/dut.v, line:7:1, endln:8:13 + \_interface_inst: work@ConnectTB (work@ConnectTB), file:${SURELOG_DIR}/tests/OneNetInterf/dut.v, line:7:1, endln:8:13 |vpiName:con_o |vpiFullName:work@ConnectTB.con_o |vpiNetType:48 |vpiPort: \_port: (con_i), line:7:33, endln:7:38 |vpiParent: - \_interface: work@ConnectTB (work@ConnectTB), file:${SURELOG_DIR}/tests/OneNetInterf/dut.v, line:7:1, endln:8:13 + \_interface_inst: work@ConnectTB (work@ConnectTB), file:${SURELOG_DIR}/tests/OneNetInterf/dut.v, line:7:1, endln:8:13 |vpiName:con_i |vpiDirection:1 |vpiLowConn: @@ -113,7 +113,7 @@ design: (work@dut) |vpiPort: \_port: (con_o), line:7:51, endln:7:56 |vpiParent: - \_interface: work@ConnectTB (work@ConnectTB), file:${SURELOG_DIR}/tests/OneNetInterf/dut.v, line:7:1, endln:8:13 + \_interface_inst: work@ConnectTB (work@ConnectTB), file:${SURELOG_DIR}/tests/OneNetInterf/dut.v, line:7:1, endln:8:13 |vpiName:con_o |vpiDirection:2 |vpiLowConn: @@ -409,7 +409,7 @@ design: (work@dut) |vpiActual: \_logic_net: (work@TESTBENCH.drive), line:1:50, endln:1:55 |uhdmallModules: -\_module: work@SUB (work@SUB), file:${SURELOG_DIR}/tests/OneNetInterf/dut.v, line:14:1, endln:16:10 +\_module_inst: work@SUB (work@SUB), file:${SURELOG_DIR}/tests/OneNetInterf/dut.v, line:14:1, endln:16:10 |vpiParent: \_design: (work@dut) |vpiFullName:work@SUB @@ -417,21 +417,21 @@ design: (work@dut) |vpiNet: \_logic_net: (work@SUB.inp), line:14:24, endln:14:27 |vpiParent: - \_module: work@SUB (work@SUB), file:${SURELOG_DIR}/tests/OneNetInterf/dut.v, line:14:1, endln:16:10 + \_module_inst: work@SUB (work@SUB), file:${SURELOG_DIR}/tests/OneNetInterf/dut.v, line:14:1, endln:16:10 |vpiName:inp |vpiFullName:work@SUB.inp |vpiNetType:1 |vpiNet: \_logic_net: (work@SUB.out), line:14:40, endln:14:43 |vpiParent: - \_module: work@SUB (work@SUB), file:${SURELOG_DIR}/tests/OneNetInterf/dut.v, line:14:1, endln:16:10 + \_module_inst: work@SUB (work@SUB), file:${SURELOG_DIR}/tests/OneNetInterf/dut.v, line:14:1, endln:16:10 |vpiName:out |vpiFullName:work@SUB.out |vpiNetType:48 |vpiPort: \_port: (inp), line:14:24, endln:14:27 |vpiParent: - \_module: work@SUB (work@SUB), file:${SURELOG_DIR}/tests/OneNetInterf/dut.v, line:14:1, endln:16:10 + \_module_inst: work@SUB (work@SUB), file:${SURELOG_DIR}/tests/OneNetInterf/dut.v, line:14:1, endln:16:10 |vpiName:inp |vpiDirection:1 |vpiLowConn: @@ -443,7 +443,7 @@ design: (work@dut) |vpiPort: \_port: (out), line:14:40, endln:14:43 |vpiParent: - \_module: work@SUB (work@SUB), file:${SURELOG_DIR}/tests/OneNetInterf/dut.v, line:14:1, endln:16:10 + \_module_inst: work@SUB (work@SUB), file:${SURELOG_DIR}/tests/OneNetInterf/dut.v, line:14:1, endln:16:10 |vpiName:out |vpiDirection:2 |vpiLowConn: @@ -455,7 +455,7 @@ design: (work@dut) |vpiContAssign: \_cont_assign: , line:15:10, endln:15:19 |vpiParent: - \_module: work@SUB (work@SUB), file:${SURELOG_DIR}/tests/OneNetInterf/dut.v, line:14:1, endln:16:10 + \_module_inst: work@SUB (work@SUB), file:${SURELOG_DIR}/tests/OneNetInterf/dut.v, line:14:1, endln:16:10 |vpiRhs: \_ref_obj: (work@SUB.inp), line:15:16, endln:15:19 |vpiParent: @@ -473,7 +473,7 @@ design: (work@dut) |vpiActual: \_logic_net: (work@dut.middle1.sub1.out), line:14:40, endln:14:43 |uhdmallModules: -\_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/OneNetInterf/dut.v, line:2:1, endln:5:10 +\_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/OneNetInterf/dut.v, line:2:1, endln:5:10 |vpiParent: \_design: (work@dut) |vpiFullName:work@dut @@ -481,21 +481,21 @@ design: (work@dut) |vpiNet: \_logic_net: (work@dut.i), line:2:24, endln:2:25 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/OneNetInterf/dut.v, line:2:1, endln:5:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/OneNetInterf/dut.v, line:2:1, endln:5:10 |vpiName:i |vpiFullName:work@dut.i |vpiNetType:1 |vpiNet: \_logic_net: (work@dut.o), line:2:38, endln:2:39 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/OneNetInterf/dut.v, line:2:1, endln:5:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/OneNetInterf/dut.v, line:2:1, endln:5:10 |vpiName:o |vpiFullName:work@dut.o |vpiNetType:48 |vpiPort: \_port: (i), line:2:24, endln:2:25 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/OneNetInterf/dut.v, line:2:1, endln:5:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/OneNetInterf/dut.v, line:2:1, endln:5:10 |vpiName:i |vpiDirection:1 |vpiLowConn: @@ -507,7 +507,7 @@ design: (work@dut) |vpiPort: \_port: (o), line:2:38, endln:2:39 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/OneNetInterf/dut.v, line:2:1, endln:5:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/OneNetInterf/dut.v, line:2:1, endln:5:10 |vpiName:o |vpiDirection:2 |vpiLowConn: @@ -517,7 +517,7 @@ design: (work@dut) |vpiTypedef: \_logic_typespec: , line:2:34, endln:2:37 |uhdmallModules: -\_module: work@middle (work@middle), file:${SURELOG_DIR}/tests/OneNetInterf/dut.v, line:10:1, endln:12:10 +\_module_inst: work@middle (work@middle), file:${SURELOG_DIR}/tests/OneNetInterf/dut.v, line:10:1, endln:12:10 |vpiParent: \_design: (work@dut) |vpiFullName:work@middle @@ -525,24 +525,24 @@ design: (work@dut) |vpiNet: \_logic_net: (work@middle.conn), line:10:26, endln:10:30 |vpiParent: - \_module: work@middle (work@middle), file:${SURELOG_DIR}/tests/OneNetInterf/dut.v, line:10:1, endln:12:10 + \_module_inst: work@middle (work@middle), file:${SURELOG_DIR}/tests/OneNetInterf/dut.v, line:10:1, endln:12:10 |vpiName:conn |vpiFullName:work@middle.conn |vpiPort: \_port: (conn), line:10:26, endln:10:30 |vpiParent: - \_module: work@middle (work@middle), file:${SURELOG_DIR}/tests/OneNetInterf/dut.v, line:10:1, endln:12:10 + \_module_inst: work@middle (work@middle), file:${SURELOG_DIR}/tests/OneNetInterf/dut.v, line:10:1, endln:12:10 |vpiName:conn |vpiDirection:3 |vpiLowConn: \_ref_obj: |vpiActual: - \_interface: work@ConnectTB (work@ConnectTB), file:${SURELOG_DIR}/tests/OneNetInterf/dut.v, line:7:1, endln:8:13 + \_interface_inst: work@ConnectTB (work@ConnectTB), file:${SURELOG_DIR}/tests/OneNetInterf/dut.v, line:7:1, endln:8:13 |vpiTypedef: \_interface_typespec: (ConnectTB), line:10:16, endln:10:25 |vpiName:ConnectTB |uhdmallModules: -\_module: work@tb (work@tb), file:${SURELOG_DIR}/tests/OneNetInterf/tb.v, line:14:1, endln:19:10 +\_module_inst: work@tb (work@tb), file:${SURELOG_DIR}/tests/OneNetInterf/tb.v, line:14:1, endln:19:10 |vpiParent: \_design: (work@dut) |vpiFullName:work@tb @@ -550,26 +550,26 @@ design: (work@dut) |vpiNet: \_logic_net: (work@tb.i), line:15:8, endln:15:9 |vpiParent: - \_module: work@tb (work@tb), file:${SURELOG_DIR}/tests/OneNetInterf/tb.v, line:14:1, endln:19:10 + \_module_inst: work@tb (work@tb), file:${SURELOG_DIR}/tests/OneNetInterf/tb.v, line:14:1, endln:19:10 |vpiName:i |vpiFullName:work@tb.i |vpiNetType:1 |vpiNet: \_logic_net: (work@tb.o), line:15:10, endln:15:11 |vpiParent: - \_module: work@tb (work@tb), file:${SURELOG_DIR}/tests/OneNetInterf/tb.v, line:14:1, endln:19:10 + \_module_inst: work@tb (work@tb), file:${SURELOG_DIR}/tests/OneNetInterf/tb.v, line:14:1, endln:19:10 |vpiName:o |vpiFullName:work@tb.o |vpiNetType:1 |uhdmtopModules: -\_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/OneNetInterf/dut.v, line:2:1, endln:5:10 +\_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/OneNetInterf/dut.v, line:2:1, endln:5:10 |vpiName:work@dut |vpiDefName:work@dut |vpiTop:1 |vpiNet: \_logic_net: (work@dut.i), line:2:24, endln:2:25 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/OneNetInterf/dut.v, line:2:1, endln:5:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/OneNetInterf/dut.v, line:2:1, endln:5:10 |vpiTypespec: \_logic_typespec: , line:2:19, endln:2:23 |vpiName:i @@ -578,7 +578,7 @@ design: (work@dut) |vpiNet: \_logic_net: (work@dut.o), line:2:38, endln:2:39 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/OneNetInterf/dut.v, line:2:1, endln:5:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/OneNetInterf/dut.v, line:2:1, endln:5:10 |vpiTypespec: \_logic_typespec: , line:2:34, endln:2:37 |vpiName:o @@ -588,7 +588,7 @@ design: (work@dut) |vpiPort: \_port: (i), line:2:24, endln:2:25 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/OneNetInterf/dut.v, line:2:1, endln:5:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/OneNetInterf/dut.v, line:2:1, endln:5:10 |vpiName:i |vpiDirection:1 |vpiLowConn: @@ -602,7 +602,7 @@ design: (work@dut) |vpiPort: \_port: (o), line:2:38, endln:2:39 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/OneNetInterf/dut.v, line:2:1, endln:5:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/OneNetInterf/dut.v, line:2:1, endln:5:10 |vpiName:o |vpiDirection:2 |vpiLowConn: @@ -613,10 +613,10 @@ design: (work@dut) \_logic_net: (work@dut.o), line:2:38, endln:2:39 |vpiTypedef: \_logic_typespec: , line:2:34, endln:2:37 - |vpiInterface: - \_interface: work@ConnectTB (work@dut.conntb), file:${SURELOG_DIR}/tests/OneNetInterf/dut.v, line:3:3, endln:3:41 + |vpiInterfaceInst: + \_interface_inst: work@ConnectTB (work@dut.conntb), file:${SURELOG_DIR}/tests/OneNetInterf/dut.v, line:3:3, endln:3:41 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/OneNetInterf/dut.v, line:2:1, endln:5:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/OneNetInterf/dut.v, line:2:1, endln:5:10 |vpiName:conntb |vpiFullName:work@dut.conntb |vpiDefName:work@ConnectTB @@ -625,7 +625,7 @@ design: (work@dut) |vpiNet: \_logic_net: (work@dut.conntb.con_i), line:7:33, endln:7:38 |vpiParent: - \_interface: work@ConnectTB (work@dut.conntb), file:${SURELOG_DIR}/tests/OneNetInterf/dut.v, line:3:3, endln:3:41 + \_interface_inst: work@ConnectTB (work@dut.conntb), file:${SURELOG_DIR}/tests/OneNetInterf/dut.v, line:3:3, endln:3:41 |vpiTypespec: \_logic_typespec: , line:7:28, endln:7:32 |vpiName:con_i @@ -634,18 +634,18 @@ design: (work@dut) |vpiNet: \_logic_net: (work@dut.conntb.con_o), line:7:51, endln:7:56 |vpiParent: - \_interface: work@ConnectTB (work@dut.conntb), file:${SURELOG_DIR}/tests/OneNetInterf/dut.v, line:3:3, endln:3:41 + \_interface_inst: work@ConnectTB (work@dut.conntb), file:${SURELOG_DIR}/tests/OneNetInterf/dut.v, line:3:3, endln:3:41 |vpiTypespec: \_logic_typespec: , line:7:47, endln:7:50 |vpiName:con_o |vpiFullName:work@dut.conntb.con_o |vpiNetType:48 |vpiInstance: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/OneNetInterf/dut.v, line:2:1, endln:5:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/OneNetInterf/dut.v, line:2:1, endln:5:10 |vpiPort: \_port: (con_i), line:7:33, endln:7:38 |vpiParent: - \_interface: work@ConnectTB (work@dut.conntb), file:${SURELOG_DIR}/tests/OneNetInterf/dut.v, line:3:3, endln:3:41 + \_interface_inst: work@ConnectTB (work@dut.conntb), file:${SURELOG_DIR}/tests/OneNetInterf/dut.v, line:3:3, endln:3:41 |vpiName:con_i |vpiDirection:1 |vpiHighConn: @@ -665,7 +665,7 @@ design: (work@dut) |vpiPort: \_port: (con_o), line:7:51, endln:7:56 |vpiParent: - \_interface: work@ConnectTB (work@dut.conntb), file:${SURELOG_DIR}/tests/OneNetInterf/dut.v, line:3:3, endln:3:41 + \_interface_inst: work@ConnectTB (work@dut.conntb), file:${SURELOG_DIR}/tests/OneNetInterf/dut.v, line:3:3, endln:3:41 |vpiName:con_o |vpiDirection:2 |vpiHighConn: @@ -682,21 +682,21 @@ design: (work@dut) \_logic_net: (work@dut.conntb.con_o), line:7:51, endln:7:56 |vpiTypedef: \_logic_typespec: , line:7:47, endln:7:50 - |vpiModule: - \_module: work@middle (work@dut.middle1), file:${SURELOG_DIR}/tests/OneNetInterf/dut.v, line:4:3, endln:4:26 + |vpiModuleInst: + \_module_inst: work@middle (work@dut.middle1), file:${SURELOG_DIR}/tests/OneNetInterf/dut.v, line:4:3, endln:4:26 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/OneNetInterf/dut.v, line:2:1, endln:5:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/OneNetInterf/dut.v, line:2:1, endln:5:10 |vpiName:middle1 |vpiFullName:work@dut.middle1 |vpiDefName:work@middle |vpiDefFile:${SURELOG_DIR}/tests/OneNetInterf/dut.v |vpiDefLineNo:10 |vpiInstance: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/OneNetInterf/dut.v, line:2:1, endln:5:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/OneNetInterf/dut.v, line:2:1, endln:5:10 |vpiPort: \_port: (conn), line:10:26, endln:10:30 |vpiParent: - \_module: work@middle (work@dut.middle1), file:${SURELOG_DIR}/tests/OneNetInterf/dut.v, line:4:3, endln:4:26 + \_module_inst: work@middle (work@dut.middle1), file:${SURELOG_DIR}/tests/OneNetInterf/dut.v, line:4:3, endln:4:26 |vpiName:conn |vpiDirection:3 |vpiHighConn: @@ -704,28 +704,28 @@ design: (work@dut) |vpiName:conntb |vpiFullName:work@dut.conntb |vpiActual: - \_interface: work@ConnectTB (work@dut.conntb), file:${SURELOG_DIR}/tests/OneNetInterf/dut.v, line:3:0 + \_interface_inst: work@ConnectTB (work@dut.conntb), file:${SURELOG_DIR}/tests/OneNetInterf/dut.v, line:3:0 |vpiLowConn: \_ref_obj: (work@dut.middle1.conn), line:4:18, endln:4:24 |vpiFullName:work@dut.middle1.conn |vpiActual: - \_interface: work@ConnectTB (work@dut.middle1.conn), file:${SURELOG_DIR}/tests/OneNetInterf/dut.v, line:4:0 + \_interface_inst: work@ConnectTB (work@dut.middle1.conn), file:${SURELOG_DIR}/tests/OneNetInterf/dut.v, line:4:0 |vpiTypedef: \_interface_typespec: (ConnectTB), line:10:16, endln:10:25 |vpiName:ConnectTB - |vpiInterface: - \_interface: work@ConnectTB (work@dut.middle1.conn), file:${SURELOG_DIR}/tests/OneNetInterf/dut.v, line:4:0 + |vpiInterfaceInst: + \_interface_inst: work@ConnectTB (work@dut.middle1.conn), file:${SURELOG_DIR}/tests/OneNetInterf/dut.v, line:4:0 |vpiParent: - \_module: work@middle (work@dut.middle1), file:${SURELOG_DIR}/tests/OneNetInterf/dut.v, line:4:3, endln:4:26 + \_module_inst: work@middle (work@dut.middle1), file:${SURELOG_DIR}/tests/OneNetInterf/dut.v, line:4:3, endln:4:26 |vpiName:conn |vpiFullName:work@dut.middle1.conn |vpiDefName:work@ConnectTB - |vpiInterface: - \_interface: work@ConnectTB (work@dut.middle1.conn), file:${SURELOG_DIR}/tests/OneNetInterf/dut.v, line:4:0 - |vpiModule: - \_module: work@SUB (work@dut.middle1.sub1), file:${SURELOG_DIR}/tests/OneNetInterf/dut.v, line:11:3, endln:11:47 + |vpiInterfaceInst: + \_interface_inst: work@ConnectTB (work@dut.middle1.conn), file:${SURELOG_DIR}/tests/OneNetInterf/dut.v, line:4:0 + |vpiModuleInst: + \_module_inst: work@SUB (work@dut.middle1.sub1), file:${SURELOG_DIR}/tests/OneNetInterf/dut.v, line:11:3, endln:11:47 |vpiParent: - \_module: work@middle (work@dut.middle1), file:${SURELOG_DIR}/tests/OneNetInterf/dut.v, line:4:3, endln:4:26 + \_module_inst: work@middle (work@dut.middle1), file:${SURELOG_DIR}/tests/OneNetInterf/dut.v, line:4:3, endln:4:26 |vpiName:sub1 |vpiFullName:work@dut.middle1.sub1 |vpiDefName:work@SUB @@ -734,7 +734,7 @@ design: (work@dut) |vpiNet: \_logic_net: (work@dut.middle1.sub1.inp), line:14:24, endln:14:27 |vpiParent: - \_module: work@SUB (work@dut.middle1.sub1), file:${SURELOG_DIR}/tests/OneNetInterf/dut.v, line:11:3, endln:11:47 + \_module_inst: work@SUB (work@dut.middle1.sub1), file:${SURELOG_DIR}/tests/OneNetInterf/dut.v, line:11:3, endln:11:47 |vpiTypespec: \_logic_typespec: , line:14:19, endln:14:23 |vpiName:inp @@ -743,18 +743,18 @@ design: (work@dut) |vpiNet: \_logic_net: (work@dut.middle1.sub1.out), line:14:40, endln:14:43 |vpiParent: - \_module: work@SUB (work@dut.middle1.sub1), file:${SURELOG_DIR}/tests/OneNetInterf/dut.v, line:11:3, endln:11:47 + \_module_inst: work@SUB (work@dut.middle1.sub1), file:${SURELOG_DIR}/tests/OneNetInterf/dut.v, line:11:3, endln:11:47 |vpiTypespec: \_logic_typespec: , line:14:36, endln:14:39 |vpiName:out |vpiFullName:work@dut.middle1.sub1.out |vpiNetType:48 |vpiInstance: - \_module: work@middle (work@dut.middle1), file:${SURELOG_DIR}/tests/OneNetInterf/dut.v, line:4:3, endln:4:26 + \_module_inst: work@middle (work@dut.middle1), file:${SURELOG_DIR}/tests/OneNetInterf/dut.v, line:4:3, endln:4:26 |vpiPort: \_port: (inp), line:14:24, endln:14:27 |vpiParent: - \_module: work@SUB (work@dut.middle1.sub1), file:${SURELOG_DIR}/tests/OneNetInterf/dut.v, line:11:3, endln:11:47 + \_module_inst: work@SUB (work@dut.middle1.sub1), file:${SURELOG_DIR}/tests/OneNetInterf/dut.v, line:11:3, endln:11:47 |vpiName:inp |vpiDirection:1 |vpiHighConn: @@ -783,7 +783,7 @@ design: (work@dut) |vpiPort: \_port: (out), line:14:40, endln:14:43 |vpiParent: - \_module: work@SUB (work@dut.middle1.sub1), file:${SURELOG_DIR}/tests/OneNetInterf/dut.v, line:11:3, endln:11:47 + \_module_inst: work@SUB (work@dut.middle1.sub1), file:${SURELOG_DIR}/tests/OneNetInterf/dut.v, line:11:3, endln:11:47 |vpiName:out |vpiDirection:2 |vpiHighConn: @@ -812,14 +812,14 @@ design: (work@dut) |vpiContAssign: \_cont_assign: , line:15:10, endln:15:19 |uhdmtopModules: -\_module: work@tb (work@tb), file:${SURELOG_DIR}/tests/OneNetInterf/tb.v, line:14:1, endln:19:10 +\_module_inst: work@tb (work@tb), file:${SURELOG_DIR}/tests/OneNetInterf/tb.v, line:14:1, endln:19:10 |vpiName:work@tb |vpiDefName:work@tb |vpiTop:1 |vpiProgram: \_program: work@TESTBENCH (work@tb.tb), file:${SURELOG_DIR}/tests/OneNetInterf/tb.v, line:18:3, endln:18:61 |vpiParent: - \_module: work@tb (work@tb), file:${SURELOG_DIR}/tests/OneNetInterf/tb.v, line:14:1, endln:19:10 + \_module_inst: work@tb (work@tb), file:${SURELOG_DIR}/tests/OneNetInterf/tb.v, line:14:1, endln:19:10 |vpiName:tb |vpiFullName:work@tb.tb |vpiDefName:work@TESTBENCH @@ -844,7 +844,7 @@ design: (work@dut) |vpiFullName:work@tb.tb.drive |vpiNetType:48 |vpiInstance: - \_module: work@tb (work@tb), file:${SURELOG_DIR}/tests/OneNetInterf/tb.v, line:14:1, endln:19:10 + \_module_inst: work@tb (work@tb), file:${SURELOG_DIR}/tests/OneNetInterf/tb.v, line:14:1, endln:19:10 |vpiProcess: \_initial: , line:2:3, endln:11:6 |vpiPort: @@ -900,7 +900,7 @@ design: (work@dut) |vpiNet: \_logic_net: (work@tb.i), line:15:8, endln:15:9 |vpiParent: - \_module: work@tb (work@tb), file:${SURELOG_DIR}/tests/OneNetInterf/tb.v, line:14:1, endln:19:10 + \_module_inst: work@tb (work@tb), file:${SURELOG_DIR}/tests/OneNetInterf/tb.v, line:14:1, endln:19:10 |vpiTypespec: \_logic_typespec: , line:15:3, endln:15:7 |vpiName:i @@ -909,17 +909,17 @@ design: (work@dut) |vpiNet: \_logic_net: (work@tb.o), line:15:10, endln:15:11 |vpiParent: - \_module: work@tb (work@tb), file:${SURELOG_DIR}/tests/OneNetInterf/tb.v, line:14:1, endln:19:10 + \_module_inst: work@tb (work@tb), file:${SURELOG_DIR}/tests/OneNetInterf/tb.v, line:14:1, endln:19:10 |vpiTypespec: \_logic_typespec: , line:15:3, endln:15:7 |vpiName:o |vpiFullName:work@tb.o |vpiNetType:1 |vpiTopModule:1 - |vpiInterface: - \_interface: work@ConnectTB (work@tb.conntb), file:${SURELOG_DIR}/tests/OneNetInterf/tb.v, line:16:3, endln:16:41 + |vpiInterfaceInst: + \_interface_inst: work@ConnectTB (work@tb.conntb), file:${SURELOG_DIR}/tests/OneNetInterf/tb.v, line:16:3, endln:16:41 |vpiParent: - \_module: work@tb (work@tb), file:${SURELOG_DIR}/tests/OneNetInterf/tb.v, line:14:1, endln:19:10 + \_module_inst: work@tb (work@tb), file:${SURELOG_DIR}/tests/OneNetInterf/tb.v, line:14:1, endln:19:10 |vpiName:conntb |vpiFullName:work@tb.conntb |vpiDefName:work@ConnectTB @@ -928,7 +928,7 @@ design: (work@dut) |vpiNet: \_logic_net: (work@tb.conntb.con_i), line:7:33, endln:7:38 |vpiParent: - \_interface: work@ConnectTB (work@tb.conntb), file:${SURELOG_DIR}/tests/OneNetInterf/tb.v, line:16:3, endln:16:41 + \_interface_inst: work@ConnectTB (work@tb.conntb), file:${SURELOG_DIR}/tests/OneNetInterf/tb.v, line:16:3, endln:16:41 |vpiTypespec: \_logic_typespec: , line:7:28, endln:7:32 |vpiName:con_i @@ -937,18 +937,18 @@ design: (work@dut) |vpiNet: \_logic_net: (work@tb.conntb.con_o), line:7:51, endln:7:56 |vpiParent: - \_interface: work@ConnectTB (work@tb.conntb), file:${SURELOG_DIR}/tests/OneNetInterf/tb.v, line:16:3, endln:16:41 + \_interface_inst: work@ConnectTB (work@tb.conntb), file:${SURELOG_DIR}/tests/OneNetInterf/tb.v, line:16:3, endln:16:41 |vpiTypespec: \_logic_typespec: , line:7:47, endln:7:50 |vpiName:con_o |vpiFullName:work@tb.conntb.con_o |vpiNetType:48 |vpiInstance: - \_module: work@tb (work@tb), file:${SURELOG_DIR}/tests/OneNetInterf/tb.v, line:14:1, endln:19:10 + \_module_inst: work@tb (work@tb), file:${SURELOG_DIR}/tests/OneNetInterf/tb.v, line:14:1, endln:19:10 |vpiPort: \_port: (con_i), line:7:33, endln:7:38 |vpiParent: - \_interface: work@ConnectTB (work@tb.conntb), file:${SURELOG_DIR}/tests/OneNetInterf/tb.v, line:16:3, endln:16:41 + \_interface_inst: work@ConnectTB (work@tb.conntb), file:${SURELOG_DIR}/tests/OneNetInterf/tb.v, line:16:3, endln:16:41 |vpiName:con_i |vpiDirection:1 |vpiHighConn: @@ -968,7 +968,7 @@ design: (work@dut) |vpiPort: \_port: (con_o), line:7:51, endln:7:56 |vpiParent: - \_interface: work@ConnectTB (work@tb.conntb), file:${SURELOG_DIR}/tests/OneNetInterf/tb.v, line:16:3, endln:16:41 + \_interface_inst: work@ConnectTB (work@tb.conntb), file:${SURELOG_DIR}/tests/OneNetInterf/tb.v, line:16:3, endln:16:41 |vpiName:con_o |vpiDirection:2 |vpiHighConn: @@ -985,21 +985,21 @@ design: (work@dut) \_logic_net: (work@tb.conntb.con_o), line:7:51, endln:7:56 |vpiTypedef: \_logic_typespec: , line:7:47, endln:7:50 - |vpiModule: - \_module: work@middle (work@tb.dut1), file:${SURELOG_DIR}/tests/OneNetInterf/tb.v, line:17:3, endln:17:23 + |vpiModuleInst: + \_module_inst: work@middle (work@tb.dut1), file:${SURELOG_DIR}/tests/OneNetInterf/tb.v, line:17:3, endln:17:23 |vpiParent: - \_module: work@tb (work@tb), file:${SURELOG_DIR}/tests/OneNetInterf/tb.v, line:14:1, endln:19:10 + \_module_inst: work@tb (work@tb), file:${SURELOG_DIR}/tests/OneNetInterf/tb.v, line:14:1, endln:19:10 |vpiName:dut1 |vpiFullName:work@tb.dut1 |vpiDefName:work@middle |vpiDefFile:${SURELOG_DIR}/tests/OneNetInterf/dut.v |vpiDefLineNo:10 |vpiInstance: - \_module: work@tb (work@tb), file:${SURELOG_DIR}/tests/OneNetInterf/tb.v, line:14:1, endln:19:10 + \_module_inst: work@tb (work@tb), file:${SURELOG_DIR}/tests/OneNetInterf/tb.v, line:14:1, endln:19:10 |vpiPort: \_port: (conn), line:10:26, endln:10:30 |vpiParent: - \_module: work@middle (work@tb.dut1), file:${SURELOG_DIR}/tests/OneNetInterf/tb.v, line:17:3, endln:17:23 + \_module_inst: work@middle (work@tb.dut1), file:${SURELOG_DIR}/tests/OneNetInterf/tb.v, line:17:3, endln:17:23 |vpiName:conn |vpiDirection:3 |vpiHighConn: @@ -1007,28 +1007,28 @@ design: (work@dut) |vpiName:conntb |vpiFullName:work@tb.conntb |vpiActual: - \_interface: work@ConnectTB (work@tb.conntb), file:${SURELOG_DIR}/tests/OneNetInterf/tb.v, line:16:0 + \_interface_inst: work@ConnectTB (work@tb.conntb), file:${SURELOG_DIR}/tests/OneNetInterf/tb.v, line:16:0 |vpiLowConn: \_ref_obj: (work@tb.dut1.conn), line:17:15, endln:17:21 |vpiFullName:work@tb.dut1.conn |vpiActual: - \_interface: work@ConnectTB (work@tb.dut1.conn), file:${SURELOG_DIR}/tests/OneNetInterf/tb.v, line:17:0 + \_interface_inst: work@ConnectTB (work@tb.dut1.conn), file:${SURELOG_DIR}/tests/OneNetInterf/tb.v, line:17:0 |vpiTypedef: \_interface_typespec: (ConnectTB), line:10:16, endln:10:25 |vpiName:ConnectTB - |vpiInterface: - \_interface: work@ConnectTB (work@tb.dut1.conn), file:${SURELOG_DIR}/tests/OneNetInterf/tb.v, line:17:0 + |vpiInterfaceInst: + \_interface_inst: work@ConnectTB (work@tb.dut1.conn), file:${SURELOG_DIR}/tests/OneNetInterf/tb.v, line:17:0 |vpiParent: - \_module: work@middle (work@tb.dut1), file:${SURELOG_DIR}/tests/OneNetInterf/tb.v, line:17:3, endln:17:23 + \_module_inst: work@middle (work@tb.dut1), file:${SURELOG_DIR}/tests/OneNetInterf/tb.v, line:17:3, endln:17:23 |vpiName:conn |vpiFullName:work@tb.dut1.conn |vpiDefName:work@ConnectTB - |vpiInterface: - \_interface: work@ConnectTB (work@tb.dut1.conn), file:${SURELOG_DIR}/tests/OneNetInterf/tb.v, line:17:0 - |vpiModule: - \_module: work@SUB (work@tb.dut1.sub1), file:${SURELOG_DIR}/tests/OneNetInterf/dut.v, line:11:3, endln:11:47 + |vpiInterfaceInst: + \_interface_inst: work@ConnectTB (work@tb.dut1.conn), file:${SURELOG_DIR}/tests/OneNetInterf/tb.v, line:17:0 + |vpiModuleInst: + \_module_inst: work@SUB (work@tb.dut1.sub1), file:${SURELOG_DIR}/tests/OneNetInterf/dut.v, line:11:3, endln:11:47 |vpiParent: - \_module: work@middle (work@tb.dut1), file:${SURELOG_DIR}/tests/OneNetInterf/tb.v, line:17:3, endln:17:23 + \_module_inst: work@middle (work@tb.dut1), file:${SURELOG_DIR}/tests/OneNetInterf/tb.v, line:17:3, endln:17:23 |vpiName:sub1 |vpiFullName:work@tb.dut1.sub1 |vpiDefName:work@SUB @@ -1037,7 +1037,7 @@ design: (work@dut) |vpiNet: \_logic_net: (work@tb.dut1.sub1.inp), line:14:24, endln:14:27 |vpiParent: - \_module: work@SUB (work@tb.dut1.sub1), file:${SURELOG_DIR}/tests/OneNetInterf/dut.v, line:11:3, endln:11:47 + \_module_inst: work@SUB (work@tb.dut1.sub1), file:${SURELOG_DIR}/tests/OneNetInterf/dut.v, line:11:3, endln:11:47 |vpiTypespec: \_logic_typespec: , line:14:19, endln:14:23 |vpiName:inp @@ -1046,18 +1046,18 @@ design: (work@dut) |vpiNet: \_logic_net: (work@tb.dut1.sub1.out), line:14:40, endln:14:43 |vpiParent: - \_module: work@SUB (work@tb.dut1.sub1), file:${SURELOG_DIR}/tests/OneNetInterf/dut.v, line:11:3, endln:11:47 + \_module_inst: work@SUB (work@tb.dut1.sub1), file:${SURELOG_DIR}/tests/OneNetInterf/dut.v, line:11:3, endln:11:47 |vpiTypespec: \_logic_typespec: , line:14:36, endln:14:39 |vpiName:out |vpiFullName:work@tb.dut1.sub1.out |vpiNetType:48 |vpiInstance: - \_module: work@middle (work@tb.dut1), file:${SURELOG_DIR}/tests/OneNetInterf/tb.v, line:17:3, endln:17:23 + \_module_inst: work@middle (work@tb.dut1), file:${SURELOG_DIR}/tests/OneNetInterf/tb.v, line:17:3, endln:17:23 |vpiPort: \_port: (inp), line:14:24, endln:14:27 |vpiParent: - \_module: work@SUB (work@tb.dut1.sub1), file:${SURELOG_DIR}/tests/OneNetInterf/dut.v, line:11:3, endln:11:47 + \_module_inst: work@SUB (work@tb.dut1.sub1), file:${SURELOG_DIR}/tests/OneNetInterf/dut.v, line:11:3, endln:11:47 |vpiName:inp |vpiDirection:1 |vpiHighConn: @@ -1086,7 +1086,7 @@ design: (work@dut) |vpiPort: \_port: (out), line:14:40, endln:14:43 |vpiParent: - \_module: work@SUB (work@tb.dut1.sub1), file:${SURELOG_DIR}/tests/OneNetInterf/dut.v, line:11:3, endln:11:47 + \_module_inst: work@SUB (work@tb.dut1.sub1), file:${SURELOG_DIR}/tests/OneNetInterf/dut.v, line:11:3, endln:11:47 |vpiName:out |vpiDirection:2 |vpiHighConn: diff --git a/tests/OneNetModPort/OneNetModPort.log b/tests/OneNetModPort/OneNetModPort.log index 696c56621e..0bf1404dac 100644 --- a/tests/OneNetModPort/OneNetModPort.log +++ b/tests/OneNetModPort/OneNetModPort.log @@ -54,14 +54,14 @@ design 1 hier_path 14 immediate_assert 2 initial 1 -interface 7 +interface_inst 7 interface_typespec 8 io_decl 24 logic_net 11 logic_typespec 20 logic_var 8 modport 12 -module 13 +module_inst 13 operation 2 port 12 program 2 @@ -80,7 +80,7 @@ sys_func_call 9 design: (work@TOP) |vpiName:work@TOP |uhdmallInterfaces: -\_interface: work@ConnectTB (work@ConnectTB), file:${SURELOG_DIR}/tests/OneNetModPort/dut.v, line:9:1, endln:20:13 +\_interface_inst: work@ConnectTB (work@ConnectTB), file:${SURELOG_DIR}/tests/OneNetModPort/dut.v, line:9:1, endln:20:13 |vpiParent: \_design: (work@TOP) |vpiFullName:work@ConnectTB @@ -88,21 +88,21 @@ design: (work@TOP) |vpiNet: \_logic_net: (work@ConnectTB.drive), line:10:9, endln:10:14 |vpiParent: - \_interface: work@ConnectTB (work@ConnectTB), file:${SURELOG_DIR}/tests/OneNetModPort/dut.v, line:9:1, endln:20:13 + \_interface_inst: work@ConnectTB (work@ConnectTB), file:${SURELOG_DIR}/tests/OneNetModPort/dut.v, line:9:1, endln:20:13 |vpiName:drive |vpiFullName:work@ConnectTB.drive |vpiNetType:36 |vpiNet: \_logic_net: (work@ConnectTB.observe), line:11:9, endln:11:16 |vpiParent: - \_interface: work@ConnectTB (work@ConnectTB), file:${SURELOG_DIR}/tests/OneNetModPort/dut.v, line:9:1, endln:20:13 + \_interface_inst: work@ConnectTB (work@ConnectTB), file:${SURELOG_DIR}/tests/OneNetModPort/dut.v, line:9:1, endln:20:13 |vpiName:observe |vpiFullName:work@ConnectTB.observe |vpiNetType:36 |vpiModport: \_modport: (dut), line:12:11, endln:12:14 |vpiParent: - \_interface: work@ConnectTB (work@ConnectTB), file:${SURELOG_DIR}/tests/OneNetModPort/dut.v, line:9:1, endln:20:13 + \_interface_inst: work@ConnectTB (work@ConnectTB), file:${SURELOG_DIR}/tests/OneNetModPort/dut.v, line:9:1, endln:20:13 |vpiName:dut |vpiIODecl: \_io_decl: (drive), line:13:11, endln:13:16 @@ -115,7 +115,7 @@ design: (work@TOP) |vpiModport: \_modport: (tb), line:16:11, endln:16:13 |vpiParent: - \_interface: work@ConnectTB (work@ConnectTB), file:${SURELOG_DIR}/tests/OneNetModPort/dut.v, line:9:1, endln:20:13 + \_interface_inst: work@ConnectTB (work@ConnectTB), file:${SURELOG_DIR}/tests/OneNetModPort/dut.v, line:9:1, endln:20:13 |vpiName:tb |vpiIODecl: \_io_decl: (drive), line:17:12, endln:17:17 @@ -428,7 +428,7 @@ design: (work@TOP) |vpiLowConn: \_ref_obj: |uhdmallModules: -\_module: work@SUB (work@SUB), file:${SURELOG_DIR}/tests/OneNetModPort/dut.v, line:26:1, endln:28:10 +\_module_inst: work@SUB (work@SUB), file:${SURELOG_DIR}/tests/OneNetModPort/dut.v, line:26:1, endln:28:10 |vpiParent: \_design: (work@TOP) |vpiFullName:work@SUB @@ -436,21 +436,21 @@ design: (work@TOP) |vpiNet: \_logic_net: (work@SUB.inp), line:26:24, endln:26:27 |vpiParent: - \_module: work@SUB (work@SUB), file:${SURELOG_DIR}/tests/OneNetModPort/dut.v, line:26:1, endln:28:10 + \_module_inst: work@SUB (work@SUB), file:${SURELOG_DIR}/tests/OneNetModPort/dut.v, line:26:1, endln:28:10 |vpiName:inp |vpiFullName:work@SUB.inp |vpiNetType:1 |vpiNet: \_logic_net: (work@SUB.out), line:26:40, endln:26:43 |vpiParent: - \_module: work@SUB (work@SUB), file:${SURELOG_DIR}/tests/OneNetModPort/dut.v, line:26:1, endln:28:10 + \_module_inst: work@SUB (work@SUB), file:${SURELOG_DIR}/tests/OneNetModPort/dut.v, line:26:1, endln:28:10 |vpiName:out |vpiFullName:work@SUB.out |vpiNetType:48 |vpiPort: \_port: (inp), line:26:24, endln:26:27 |vpiParent: - \_module: work@SUB (work@SUB), file:${SURELOG_DIR}/tests/OneNetModPort/dut.v, line:26:1, endln:28:10 + \_module_inst: work@SUB (work@SUB), file:${SURELOG_DIR}/tests/OneNetModPort/dut.v, line:26:1, endln:28:10 |vpiName:inp |vpiDirection:1 |vpiLowConn: @@ -462,7 +462,7 @@ design: (work@TOP) |vpiPort: \_port: (out), line:26:40, endln:26:43 |vpiParent: - \_module: work@SUB (work@SUB), file:${SURELOG_DIR}/tests/OneNetModPort/dut.v, line:26:1, endln:28:10 + \_module_inst: work@SUB (work@SUB), file:${SURELOG_DIR}/tests/OneNetModPort/dut.v, line:26:1, endln:28:10 |vpiName:out |vpiDirection:2 |vpiLowConn: @@ -474,7 +474,7 @@ design: (work@TOP) |vpiContAssign: \_cont_assign: , line:27:10, endln:27:19 |vpiParent: - \_module: work@SUB (work@SUB), file:${SURELOG_DIR}/tests/OneNetModPort/dut.v, line:26:1, endln:28:10 + \_module_inst: work@SUB (work@SUB), file:${SURELOG_DIR}/tests/OneNetModPort/dut.v, line:26:1, endln:28:10 |vpiRhs: \_ref_obj: (work@SUB.inp), line:27:16, endln:27:19 |vpiParent: @@ -492,13 +492,13 @@ design: (work@TOP) |vpiActual: \_logic_net: (work@TOP.dut1.middle1.sub1.out), line:26:40, endln:26:43 |uhdmallModules: -\_module: work@TOP (work@TOP), file:${SURELOG_DIR}/tests/OneNetModPort/tb.v, line:15:1, endln:19:10 +\_module_inst: work@TOP (work@TOP), file:${SURELOG_DIR}/tests/OneNetModPort/tb.v, line:15:1, endln:19:10 |vpiParent: \_design: (work@TOP) |vpiFullName:work@TOP |vpiDefName:work@TOP |uhdmallModules: -\_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/OneNetModPort/dut.v, line:2:1, endln:7:10 +\_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/OneNetModPort/dut.v, line:2:1, endln:7:10 |vpiParent: \_design: (work@TOP) |vpiFullName:work@dut @@ -506,21 +506,21 @@ design: (work@TOP) |vpiNet: \_logic_net: (work@dut.i), line:2:24, endln:2:25 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/OneNetModPort/dut.v, line:2:1, endln:7:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/OneNetModPort/dut.v, line:2:1, endln:7:10 |vpiName:i |vpiFullName:work@dut.i |vpiNetType:1 |vpiNet: \_logic_net: (work@dut.o), line:2:38, endln:2:39 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/OneNetModPort/dut.v, line:2:1, endln:7:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/OneNetModPort/dut.v, line:2:1, endln:7:10 |vpiName:o |vpiFullName:work@dut.o |vpiNetType:48 |vpiPort: \_port: (i), line:2:24, endln:2:25 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/OneNetModPort/dut.v, line:2:1, endln:7:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/OneNetModPort/dut.v, line:2:1, endln:7:10 |vpiName:i |vpiDirection:1 |vpiLowConn: @@ -532,7 +532,7 @@ design: (work@TOP) |vpiPort: \_port: (o), line:2:38, endln:2:39 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/OneNetModPort/dut.v, line:2:1, endln:7:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/OneNetModPort/dut.v, line:2:1, endln:7:10 |vpiName:o |vpiDirection:2 |vpiLowConn: @@ -544,7 +544,7 @@ design: (work@TOP) |vpiContAssign: \_cont_assign: , line:3:10, endln:3:26 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/OneNetModPort/dut.v, line:2:1, endln:7:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/OneNetModPort/dut.v, line:2:1, endln:7:10 |vpiRhs: \_ref_obj: (work@dut.i), line:3:25, endln:3:26 |vpiParent: @@ -569,7 +569,7 @@ design: (work@TOP) |vpiContAssign: \_cont_assign: , line:4:10, endln:4:28 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/OneNetModPort/dut.v, line:2:1, endln:7:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/OneNetModPort/dut.v, line:2:1, endln:7:10 |vpiRhs: \_hier_path: (conntb.observe), line:4:14, endln:4:28 |vpiParent: @@ -592,7 +592,7 @@ design: (work@TOP) |vpiActual: \_logic_net: (work@TOP.dut1.o), line:2:38, endln:2:39 |uhdmallModules: -\_module: work@middle (work@middle), file:${SURELOG_DIR}/tests/OneNetModPort/dut.v, line:22:1, endln:24:10 +\_module_inst: work@middle (work@middle), file:${SURELOG_DIR}/tests/OneNetModPort/dut.v, line:22:1, endln:24:10 |vpiParent: \_design: (work@TOP) |vpiFullName:work@middle @@ -600,13 +600,13 @@ design: (work@TOP) |vpiNet: \_logic_net: (work@middle.intf), line:22:30, endln:22:34 |vpiParent: - \_module: work@middle (work@middle), file:${SURELOG_DIR}/tests/OneNetModPort/dut.v, line:22:1, endln:24:10 + \_module_inst: work@middle (work@middle), file:${SURELOG_DIR}/tests/OneNetModPort/dut.v, line:22:1, endln:24:10 |vpiName:intf |vpiFullName:work@middle.intf |vpiPort: \_port: (intf), line:22:30, endln:22:34 |vpiParent: - \_module: work@middle (work@middle), file:${SURELOG_DIR}/tests/OneNetModPort/dut.v, line:22:1, endln:24:10 + \_module_inst: work@middle (work@middle), file:${SURELOG_DIR}/tests/OneNetModPort/dut.v, line:22:1, endln:24:10 |vpiName:intf |vpiDirection:3 |vpiLowConn: @@ -620,21 +620,21 @@ design: (work@TOP) |vpiName:dut |vpiIsModPort:1 |uhdmtopModules: -\_module: work@TOP (work@TOP), file:${SURELOG_DIR}/tests/OneNetModPort/tb.v, line:15:1, endln:19:10 +\_module_inst: work@TOP (work@TOP), file:${SURELOG_DIR}/tests/OneNetModPort/tb.v, line:15:1, endln:19:10 |vpiName:work@TOP |vpiDefName:work@TOP |vpiTop:1 |vpiProgram: \_program: work@TESTBENCH (work@TOP.tb), file:${SURELOG_DIR}/tests/OneNetModPort/tb.v, line:18:3, endln:18:24 |vpiParent: - \_module: work@TOP (work@TOP), file:${SURELOG_DIR}/tests/OneNetModPort/tb.v, line:15:1, endln:19:10 + \_module_inst: work@TOP (work@TOP), file:${SURELOG_DIR}/tests/OneNetModPort/tb.v, line:15:1, endln:19:10 |vpiName:tb |vpiFullName:work@TOP.tb |vpiDefName:work@TESTBENCH |vpiDefFile:${SURELOG_DIR}/tests/OneNetModPort/tb.v |vpiDefLineNo:1 |vpiInstance: - \_module: work@TOP (work@TOP), file:${SURELOG_DIR}/tests/OneNetModPort/tb.v, line:15:1, endln:19:10 + \_module_inst: work@TOP (work@TOP), file:${SURELOG_DIR}/tests/OneNetModPort/tb.v, line:15:1, endln:19:10 |vpiProcess: \_initial: , line:2:3, endln:11:6 |vpiPort: @@ -648,7 +648,7 @@ design: (work@TOP) |vpiName:conntb |vpiFullName:work@TOP.conntb |vpiActual: - \_interface: work@ConnectTB (work@TOP.conntb), file:${SURELOG_DIR}/tests/OneNetModPort/tb.v, line:16:0 + \_interface_inst: work@ConnectTB (work@TOP.conntb), file:${SURELOG_DIR}/tests/OneNetModPort/tb.v, line:16:0 |vpiLowConn: \_ref_obj: (work@TOP.tb.intf), line:18:16, endln:18:22 |vpiFullName:work@TOP.tb.intf @@ -661,16 +661,16 @@ design: (work@TOP) |vpiName:tb |vpiIsModPort:1 |vpiTopModule:1 - |vpiInterface: - \_interface: work@ConnectTB (work@TOP.conntb), file:${SURELOG_DIR}/tests/OneNetModPort/tb.v, line:16:3, endln:16:22 + |vpiInterfaceInst: + \_interface_inst: work@ConnectTB (work@TOP.conntb), file:${SURELOG_DIR}/tests/OneNetModPort/tb.v, line:16:3, endln:16:22 |vpiParent: - \_module: work@TOP (work@TOP), file:${SURELOG_DIR}/tests/OneNetModPort/tb.v, line:15:1, endln:19:10 + \_module_inst: work@TOP (work@TOP), file:${SURELOG_DIR}/tests/OneNetModPort/tb.v, line:15:1, endln:19:10 |vpiName:conntb |vpiFullName:work@TOP.conntb |vpiVariables: \_logic_var: (work@TOP.conntb.drive), line:10:9, endln:10:14 |vpiParent: - \_interface: work@ConnectTB (work@TOP.conntb), file:${SURELOG_DIR}/tests/OneNetModPort/tb.v, line:16:3, endln:16:22 + \_interface_inst: work@ConnectTB (work@TOP.conntb), file:${SURELOG_DIR}/tests/OneNetModPort/tb.v, line:16:3, endln:16:22 |vpiTypespec: \_logic_typespec: , line:10:3, endln:10:8 |vpiName:drive @@ -679,7 +679,7 @@ design: (work@TOP) |vpiVariables: \_logic_var: (work@TOP.conntb.observe), line:11:9, endln:11:16 |vpiParent: - \_interface: work@ConnectTB (work@TOP.conntb), file:${SURELOG_DIR}/tests/OneNetModPort/tb.v, line:16:3, endln:16:22 + \_interface_inst: work@ConnectTB (work@TOP.conntb), file:${SURELOG_DIR}/tests/OneNetModPort/tb.v, line:16:3, endln:16:22 |vpiTypespec: \_logic_typespec: , line:11:3, endln:11:8 |vpiName:observe @@ -689,11 +689,11 @@ design: (work@TOP) |vpiDefFile:${SURELOG_DIR}/tests/OneNetModPort/dut.v |vpiDefLineNo:9 |vpiInstance: - \_module: work@TOP (work@TOP), file:${SURELOG_DIR}/tests/OneNetModPort/tb.v, line:15:1, endln:19:10 + \_module_inst: work@TOP (work@TOP), file:${SURELOG_DIR}/tests/OneNetModPort/tb.v, line:15:1, endln:19:10 |vpiModport: \_modport: (dut), line:12:11, endln:12:14 |vpiParent: - \_interface: work@ConnectTB (work@TOP.conntb), file:${SURELOG_DIR}/tests/OneNetModPort/tb.v, line:16:3, endln:16:22 + \_interface_inst: work@ConnectTB (work@TOP.conntb), file:${SURELOG_DIR}/tests/OneNetModPort/tb.v, line:16:3, endln:16:22 |vpiName:dut |vpiIODecl: \_io_decl: (drive), line:13:11, endln:13:16 @@ -707,12 +707,12 @@ design: (work@TOP) \_modport: (dut), line:12:11, endln:12:14 |vpiDirection:2 |vpiName:observe - |vpiInterface: - \_interface: work@ConnectTB (work@TOP.conntb), file:${SURELOG_DIR}/tests/OneNetModPort/tb.v, line:16:3, endln:16:22 + |vpiInterfaceInst: + \_interface_inst: work@ConnectTB (work@TOP.conntb), file:${SURELOG_DIR}/tests/OneNetModPort/tb.v, line:16:3, endln:16:22 |vpiModport: \_modport: (tb), line:16:11, endln:16:13 |vpiParent: - \_interface: work@ConnectTB (work@TOP.conntb), file:${SURELOG_DIR}/tests/OneNetModPort/tb.v, line:16:3, endln:16:22 + \_interface_inst: work@ConnectTB (work@TOP.conntb), file:${SURELOG_DIR}/tests/OneNetModPort/tb.v, line:16:3, endln:16:22 |vpiName:tb |vpiIODecl: \_io_decl: (drive), line:17:12, endln:17:17 @@ -726,12 +726,12 @@ design: (work@TOP) \_modport: (tb), line:16:11, endln:16:13 |vpiDirection:1 |vpiName:observe - |vpiInterface: - \_interface: work@ConnectTB (work@TOP.conntb), file:${SURELOG_DIR}/tests/OneNetModPort/tb.v, line:16:3, endln:16:22 - |vpiModule: - \_module: work@dut (work@TOP.dut1), file:${SURELOG_DIR}/tests/OneNetModPort/tb.v, line:17:3, endln:17:42 + |vpiInterfaceInst: + \_interface_inst: work@ConnectTB (work@TOP.conntb), file:${SURELOG_DIR}/tests/OneNetModPort/tb.v, line:16:3, endln:16:22 + |vpiModuleInst: + \_module_inst: work@dut (work@TOP.dut1), file:${SURELOG_DIR}/tests/OneNetModPort/tb.v, line:17:3, endln:17:42 |vpiParent: - \_module: work@TOP (work@TOP), file:${SURELOG_DIR}/tests/OneNetModPort/tb.v, line:15:1, endln:19:10 + \_module_inst: work@TOP (work@TOP), file:${SURELOG_DIR}/tests/OneNetModPort/tb.v, line:15:1, endln:19:10 |vpiName:dut1 |vpiFullName:work@TOP.dut1 |vpiDefName:work@dut @@ -740,7 +740,7 @@ design: (work@TOP) |vpiNet: \_logic_net: (work@TOP.dut1.i), line:2:24, endln:2:25 |vpiParent: - \_module: work@dut (work@TOP.dut1), file:${SURELOG_DIR}/tests/OneNetModPort/tb.v, line:17:3, endln:17:42 + \_module_inst: work@dut (work@TOP.dut1), file:${SURELOG_DIR}/tests/OneNetModPort/tb.v, line:17:3, endln:17:42 |vpiTypespec: \_logic_typespec: , line:2:19, endln:2:23 |vpiName:i @@ -749,18 +749,18 @@ design: (work@TOP) |vpiNet: \_logic_net: (work@TOP.dut1.o), line:2:38, endln:2:39 |vpiParent: - \_module: work@dut (work@TOP.dut1), file:${SURELOG_DIR}/tests/OneNetModPort/tb.v, line:17:3, endln:17:42 + \_module_inst: work@dut (work@TOP.dut1), file:${SURELOG_DIR}/tests/OneNetModPort/tb.v, line:17:3, endln:17:42 |vpiTypespec: \_logic_typespec: , line:2:34, endln:2:37 |vpiName:o |vpiFullName:work@TOP.dut1.o |vpiNetType:48 |vpiInstance: - \_module: work@TOP (work@TOP), file:${SURELOG_DIR}/tests/OneNetModPort/tb.v, line:15:1, endln:19:10 + \_module_inst: work@TOP (work@TOP), file:${SURELOG_DIR}/tests/OneNetModPort/tb.v, line:15:1, endln:19:10 |vpiPort: \_port: (i), line:2:24, endln:2:25 |vpiParent: - \_module: work@dut (work@TOP.dut1), file:${SURELOG_DIR}/tests/OneNetModPort/tb.v, line:17:3, endln:17:42 + \_module_inst: work@dut (work@TOP.dut1), file:${SURELOG_DIR}/tests/OneNetModPort/tb.v, line:17:3, endln:17:42 |vpiName:i |vpiDirection:1 |vpiHighConn: @@ -785,7 +785,7 @@ design: (work@TOP) |vpiPort: \_port: (o), line:2:38, endln:2:39 |vpiParent: - \_module: work@dut (work@TOP.dut1), file:${SURELOG_DIR}/tests/OneNetModPort/tb.v, line:17:3, endln:17:42 + \_module_inst: work@dut (work@TOP.dut1), file:${SURELOG_DIR}/tests/OneNetModPort/tb.v, line:17:3, endln:17:42 |vpiName:o |vpiDirection:2 |vpiHighConn: @@ -807,16 +807,16 @@ design: (work@TOP) \_logic_net: (work@TOP.dut1.o), line:2:38, endln:2:39 |vpiTypedef: \_logic_typespec: , line:2:34, endln:2:37 - |vpiInterface: - \_interface: work@ConnectTB (work@TOP.dut1.conntb), file:${SURELOG_DIR}/tests/OneNetModPort/dut.v, line:5:3, endln:5:22 + |vpiInterfaceInst: + \_interface_inst: work@ConnectTB (work@TOP.dut1.conntb), file:${SURELOG_DIR}/tests/OneNetModPort/dut.v, line:5:3, endln:5:22 |vpiParent: - \_module: work@dut (work@TOP.dut1), file:${SURELOG_DIR}/tests/OneNetModPort/tb.v, line:17:3, endln:17:42 + \_module_inst: work@dut (work@TOP.dut1), file:${SURELOG_DIR}/tests/OneNetModPort/tb.v, line:17:3, endln:17:42 |vpiName:conntb |vpiFullName:work@TOP.dut1.conntb |vpiVariables: \_logic_var: (work@TOP.dut1.conntb.drive), line:10:9, endln:10:14 |vpiParent: - \_interface: work@ConnectTB (work@TOP.dut1.conntb), file:${SURELOG_DIR}/tests/OneNetModPort/dut.v, line:5:3, endln:5:22 + \_interface_inst: work@ConnectTB (work@TOP.dut1.conntb), file:${SURELOG_DIR}/tests/OneNetModPort/dut.v, line:5:3, endln:5:22 |vpiTypespec: \_logic_typespec: , line:10:3, endln:10:8 |vpiName:drive @@ -825,7 +825,7 @@ design: (work@TOP) |vpiVariables: \_logic_var: (work@TOP.dut1.conntb.observe), line:11:9, endln:11:16 |vpiParent: - \_interface: work@ConnectTB (work@TOP.dut1.conntb), file:${SURELOG_DIR}/tests/OneNetModPort/dut.v, line:5:3, endln:5:22 + \_interface_inst: work@ConnectTB (work@TOP.dut1.conntb), file:${SURELOG_DIR}/tests/OneNetModPort/dut.v, line:5:3, endln:5:22 |vpiTypespec: \_logic_typespec: , line:11:3, endln:11:8 |vpiName:observe @@ -835,11 +835,11 @@ design: (work@TOP) |vpiDefFile:${SURELOG_DIR}/tests/OneNetModPort/dut.v |vpiDefLineNo:9 |vpiInstance: - \_module: work@dut (work@TOP.dut1), file:${SURELOG_DIR}/tests/OneNetModPort/tb.v, line:17:3, endln:17:42 + \_module_inst: work@dut (work@TOP.dut1), file:${SURELOG_DIR}/tests/OneNetModPort/tb.v, line:17:3, endln:17:42 |vpiModport: \_modport: (dut), line:12:11, endln:12:14 |vpiParent: - \_interface: work@ConnectTB (work@TOP.dut1.conntb), file:${SURELOG_DIR}/tests/OneNetModPort/dut.v, line:5:3, endln:5:22 + \_interface_inst: work@ConnectTB (work@TOP.dut1.conntb), file:${SURELOG_DIR}/tests/OneNetModPort/dut.v, line:5:3, endln:5:22 |vpiName:dut |vpiIODecl: \_io_decl: (drive), line:13:11, endln:13:16 @@ -853,12 +853,12 @@ design: (work@TOP) \_modport: (dut), line:12:11, endln:12:14 |vpiDirection:2 |vpiName:observe - |vpiInterface: - \_interface: work@ConnectTB (work@TOP.dut1.conntb), file:${SURELOG_DIR}/tests/OneNetModPort/dut.v, line:5:3, endln:5:22 + |vpiInterfaceInst: + \_interface_inst: work@ConnectTB (work@TOP.dut1.conntb), file:${SURELOG_DIR}/tests/OneNetModPort/dut.v, line:5:3, endln:5:22 |vpiModport: \_modport: (tb), line:16:11, endln:16:13 |vpiParent: - \_interface: work@ConnectTB (work@TOP.dut1.conntb), file:${SURELOG_DIR}/tests/OneNetModPort/dut.v, line:5:3, endln:5:22 + \_interface_inst: work@ConnectTB (work@TOP.dut1.conntb), file:${SURELOG_DIR}/tests/OneNetModPort/dut.v, line:5:3, endln:5:22 |vpiName:tb |vpiIODecl: \_io_decl: (drive), line:17:12, endln:17:17 @@ -872,23 +872,23 @@ design: (work@TOP) \_modport: (tb), line:16:11, endln:16:13 |vpiDirection:1 |vpiName:observe - |vpiInterface: - \_interface: work@ConnectTB (work@TOP.dut1.conntb), file:${SURELOG_DIR}/tests/OneNetModPort/dut.v, line:5:3, endln:5:22 - |vpiModule: - \_module: work@middle (work@TOP.dut1.middle1), file:${SURELOG_DIR}/tests/OneNetModPort/dut.v, line:6:3, endln:6:26 + |vpiInterfaceInst: + \_interface_inst: work@ConnectTB (work@TOP.dut1.conntb), file:${SURELOG_DIR}/tests/OneNetModPort/dut.v, line:5:3, endln:5:22 + |vpiModuleInst: + \_module_inst: work@middle (work@TOP.dut1.middle1), file:${SURELOG_DIR}/tests/OneNetModPort/dut.v, line:6:3, endln:6:26 |vpiParent: - \_module: work@dut (work@TOP.dut1), file:${SURELOG_DIR}/tests/OneNetModPort/tb.v, line:17:3, endln:17:42 + \_module_inst: work@dut (work@TOP.dut1), file:${SURELOG_DIR}/tests/OneNetModPort/tb.v, line:17:3, endln:17:42 |vpiName:middle1 |vpiFullName:work@TOP.dut1.middle1 |vpiDefName:work@middle |vpiDefFile:${SURELOG_DIR}/tests/OneNetModPort/dut.v |vpiDefLineNo:22 |vpiInstance: - \_module: work@dut (work@TOP.dut1), file:${SURELOG_DIR}/tests/OneNetModPort/tb.v, line:17:3, endln:17:42 + \_module_inst: work@dut (work@TOP.dut1), file:${SURELOG_DIR}/tests/OneNetModPort/tb.v, line:17:3, endln:17:42 |vpiPort: \_port: (intf), line:22:30, endln:22:34 |vpiParent: - \_module: work@middle (work@TOP.dut1.middle1), file:${SURELOG_DIR}/tests/OneNetModPort/dut.v, line:6:3, endln:6:26 + \_module_inst: work@middle (work@TOP.dut1.middle1), file:${SURELOG_DIR}/tests/OneNetModPort/dut.v, line:6:3, endln:6:26 |vpiName:intf |vpiDirection:3 |vpiHighConn: @@ -896,7 +896,7 @@ design: (work@TOP) |vpiName:conntb |vpiFullName:work@TOP.dut1.conntb |vpiActual: - \_interface: work@ConnectTB (work@TOP.dut1.conntb), file:${SURELOG_DIR}/tests/OneNetModPort/dut.v, line:5:0 + \_interface_inst: work@ConnectTB (work@TOP.dut1.conntb), file:${SURELOG_DIR}/tests/OneNetModPort/dut.v, line:5:0 |vpiLowConn: \_ref_obj: (work@TOP.dut1.middle1.intf), line:6:18, endln:6:24 |vpiFullName:work@TOP.dut1.middle1.intf @@ -908,17 +908,17 @@ design: (work@TOP) \_interface_typespec: (ConnectTB), line:22:16, endln:22:25 |vpiName:dut |vpiIsModPort:1 - |vpiInterface: - \_interface: work@ConnectTB (work@TOP.dut1.middle1.intf), file:${SURELOG_DIR}/tests/OneNetModPort/dut.v, line:6:0 + |vpiInterfaceInst: + \_interface_inst: work@ConnectTB (work@TOP.dut1.middle1.intf), file:${SURELOG_DIR}/tests/OneNetModPort/dut.v, line:6:0 |vpiParent: - \_module: work@middle (work@TOP.dut1.middle1), file:${SURELOG_DIR}/tests/OneNetModPort/dut.v, line:6:3, endln:6:26 + \_module_inst: work@middle (work@TOP.dut1.middle1), file:${SURELOG_DIR}/tests/OneNetModPort/dut.v, line:6:3, endln:6:26 |vpiName:intf |vpiFullName:work@TOP.dut1.middle1.intf |vpiDefName:work@ConnectTB |vpiModport: \_modport: (dut), line:12:11, endln:12:14 |vpiParent: - \_interface: work@ConnectTB (work@TOP.dut1.middle1.intf), file:${SURELOG_DIR}/tests/OneNetModPort/dut.v, line:6:0 + \_interface_inst: work@ConnectTB (work@TOP.dut1.middle1.intf), file:${SURELOG_DIR}/tests/OneNetModPort/dut.v, line:6:0 |vpiName:dut |vpiIODecl: \_io_decl: (drive), line:13:11, endln:13:16 @@ -940,12 +940,12 @@ design: (work@TOP) \_logic_typespec: , line:11:3, endln:11:8 |vpiName:observe |vpiVisibility:1 - |vpiInterface: - \_interface: work@ConnectTB (work@TOP.dut1.middle1.intf), file:${SURELOG_DIR}/tests/OneNetModPort/dut.v, line:6:0 - |vpiModule: - \_module: work@SUB (work@TOP.dut1.middle1.sub1), file:${SURELOG_DIR}/tests/OneNetModPort/dut.v, line:23:3, endln:23:50 + |vpiInterfaceInst: + \_interface_inst: work@ConnectTB (work@TOP.dut1.middle1.intf), file:${SURELOG_DIR}/tests/OneNetModPort/dut.v, line:6:0 + |vpiModuleInst: + \_module_inst: work@SUB (work@TOP.dut1.middle1.sub1), file:${SURELOG_DIR}/tests/OneNetModPort/dut.v, line:23:3, endln:23:50 |vpiParent: - \_module: work@middle (work@TOP.dut1.middle1), file:${SURELOG_DIR}/tests/OneNetModPort/dut.v, line:6:3, endln:6:26 + \_module_inst: work@middle (work@TOP.dut1.middle1), file:${SURELOG_DIR}/tests/OneNetModPort/dut.v, line:6:3, endln:6:26 |vpiName:sub1 |vpiFullName:work@TOP.dut1.middle1.sub1 |vpiDefName:work@SUB @@ -954,7 +954,7 @@ design: (work@TOP) |vpiNet: \_logic_net: (work@TOP.dut1.middle1.sub1.inp), line:26:24, endln:26:27 |vpiParent: - \_module: work@SUB (work@TOP.dut1.middle1.sub1), file:${SURELOG_DIR}/tests/OneNetModPort/dut.v, line:23:3, endln:23:50 + \_module_inst: work@SUB (work@TOP.dut1.middle1.sub1), file:${SURELOG_DIR}/tests/OneNetModPort/dut.v, line:23:3, endln:23:50 |vpiTypespec: \_logic_typespec: , line:26:19, endln:26:23 |vpiName:inp @@ -963,18 +963,18 @@ design: (work@TOP) |vpiNet: \_logic_net: (work@TOP.dut1.middle1.sub1.out), line:26:40, endln:26:43 |vpiParent: - \_module: work@SUB (work@TOP.dut1.middle1.sub1), file:${SURELOG_DIR}/tests/OneNetModPort/dut.v, line:23:3, endln:23:50 + \_module_inst: work@SUB (work@TOP.dut1.middle1.sub1), file:${SURELOG_DIR}/tests/OneNetModPort/dut.v, line:23:3, endln:23:50 |vpiTypespec: \_logic_typespec: , line:26:36, endln:26:39 |vpiName:out |vpiFullName:work@TOP.dut1.middle1.sub1.out |vpiNetType:48 |vpiInstance: - \_module: work@middle (work@TOP.dut1.middle1), file:${SURELOG_DIR}/tests/OneNetModPort/dut.v, line:6:3, endln:6:26 + \_module_inst: work@middle (work@TOP.dut1.middle1), file:${SURELOG_DIR}/tests/OneNetModPort/dut.v, line:6:3, endln:6:26 |vpiPort: \_port: (inp), line:26:24, endln:26:27 |vpiParent: - \_module: work@SUB (work@TOP.dut1.middle1.sub1), file:${SURELOG_DIR}/tests/OneNetModPort/dut.v, line:23:3, endln:23:50 + \_module_inst: work@SUB (work@TOP.dut1.middle1.sub1), file:${SURELOG_DIR}/tests/OneNetModPort/dut.v, line:23:3, endln:23:50 |vpiName:inp |vpiDirection:1 |vpiHighConn: @@ -1003,7 +1003,7 @@ design: (work@TOP) |vpiPort: \_port: (out), line:26:40, endln:26:43 |vpiParent: - \_module: work@SUB (work@TOP.dut1.middle1.sub1), file:${SURELOG_DIR}/tests/OneNetModPort/dut.v, line:23:3, endln:23:50 + \_module_inst: work@SUB (work@TOP.dut1.middle1.sub1), file:${SURELOG_DIR}/tests/OneNetModPort/dut.v, line:23:3, endln:23:50 |vpiName:out |vpiDirection:2 |vpiHighConn: diff --git a/tests/OneNetModPortGeneric/OneNetModPortGeneric.log b/tests/OneNetModPortGeneric/OneNetModPortGeneric.log index 5fd6dbe541..6976aad708 100644 --- a/tests/OneNetModPortGeneric/OneNetModPortGeneric.log +++ b/tests/OneNetModPortGeneric/OneNetModPortGeneric.log @@ -62,13 +62,13 @@ design 1 hier_path 17 immediate_assert 2 initial 1 -interface 8 +interface_inst 8 io_decl 28 logic_net 17 logic_typespec 22 logic_var 10 modport 14 -module 16 +module_inst 16 operation 2 port 14 program 2 @@ -88,7 +88,7 @@ unsupported_typespec 8 design: (work@TOP) |vpiName:work@TOP |uhdmallInterfaces: -\_interface: work@ConnectTB (work@ConnectTB), file:${SURELOG_DIR}/tests/OneNetModPortGeneric/dut.v, line:9:1, endln:20:13 +\_interface_inst: work@ConnectTB (work@ConnectTB), file:${SURELOG_DIR}/tests/OneNetModPortGeneric/dut.v, line:9:1, endln:20:13 |vpiParent: \_design: (work@TOP) |vpiFullName:work@ConnectTB @@ -96,21 +96,21 @@ design: (work@TOP) |vpiNet: \_logic_net: (work@ConnectTB.drive), line:10:9, endln:10:14 |vpiParent: - \_interface: work@ConnectTB (work@ConnectTB), file:${SURELOG_DIR}/tests/OneNetModPortGeneric/dut.v, line:9:1, endln:20:13 + \_interface_inst: work@ConnectTB (work@ConnectTB), file:${SURELOG_DIR}/tests/OneNetModPortGeneric/dut.v, line:9:1, endln:20:13 |vpiName:drive |vpiFullName:work@ConnectTB.drive |vpiNetType:36 |vpiNet: \_logic_net: (work@ConnectTB.observe), line:11:9, endln:11:16 |vpiParent: - \_interface: work@ConnectTB (work@ConnectTB), file:${SURELOG_DIR}/tests/OneNetModPortGeneric/dut.v, line:9:1, endln:20:13 + \_interface_inst: work@ConnectTB (work@ConnectTB), file:${SURELOG_DIR}/tests/OneNetModPortGeneric/dut.v, line:9:1, endln:20:13 |vpiName:observe |vpiFullName:work@ConnectTB.observe |vpiNetType:36 |vpiModport: \_modport: (dut), line:12:11, endln:12:14 |vpiParent: - \_interface: work@ConnectTB (work@ConnectTB), file:${SURELOG_DIR}/tests/OneNetModPortGeneric/dut.v, line:9:1, endln:20:13 + \_interface_inst: work@ConnectTB (work@ConnectTB), file:${SURELOG_DIR}/tests/OneNetModPortGeneric/dut.v, line:9:1, endln:20:13 |vpiName:dut |vpiIODecl: \_io_decl: (drive), line:13:11, endln:13:16 @@ -123,7 +123,7 @@ design: (work@TOP) |vpiModport: \_modport: (tb), line:16:11, endln:16:13 |vpiParent: - \_interface: work@ConnectTB (work@ConnectTB), file:${SURELOG_DIR}/tests/OneNetModPortGeneric/dut.v, line:9:1, endln:20:13 + \_interface_inst: work@ConnectTB (work@ConnectTB), file:${SURELOG_DIR}/tests/OneNetModPortGeneric/dut.v, line:9:1, endln:20:13 |vpiName:tb |vpiIODecl: \_io_decl: (drive), line:17:12, endln:17:17 @@ -444,7 +444,7 @@ design: (work@TOP) |vpiActual: \_logic_net: (work@TESTBENCH.intf), line:1:31, endln:1:35 |uhdmallModules: -\_module: work@OBSERVER (work@OBSERVER), file:${SURELOG_DIR}/tests/OneNetModPortGeneric/dut.v, line:30:1, endln:32:10 +\_module_inst: work@OBSERVER (work@OBSERVER), file:${SURELOG_DIR}/tests/OneNetModPortGeneric/dut.v, line:30:1, endln:32:10 |vpiParent: \_design: (work@TOP) |vpiFullName:work@OBSERVER @@ -452,13 +452,13 @@ design: (work@TOP) |vpiNet: \_logic_net: (work@OBSERVER.intf), line:30:27, endln:30:31 |vpiParent: - \_module: work@OBSERVER (work@OBSERVER), file:${SURELOG_DIR}/tests/OneNetModPortGeneric/dut.v, line:30:1, endln:32:10 + \_module_inst: work@OBSERVER (work@OBSERVER), file:${SURELOG_DIR}/tests/OneNetModPortGeneric/dut.v, line:30:1, endln:32:10 |vpiName:intf |vpiFullName:work@OBSERVER.intf |vpiPort: \_port: (intf), line:30:27, endln:30:31 |vpiParent: - \_module: work@OBSERVER (work@OBSERVER), file:${SURELOG_DIR}/tests/OneNetModPortGeneric/dut.v, line:30:1, endln:32:10 + \_module_inst: work@OBSERVER (work@OBSERVER), file:${SURELOG_DIR}/tests/OneNetModPortGeneric/dut.v, line:30:1, endln:32:10 |vpiName:intf |vpiDirection:3 |vpiLowConn: @@ -471,7 +471,7 @@ design: (work@TOP) |vpiContAssign: \_cont_assign: , line:31:11, endln:31:29 |vpiParent: - \_module: work@OBSERVER (work@OBSERVER), file:${SURELOG_DIR}/tests/OneNetModPortGeneric/dut.v, line:30:1, endln:32:10 + \_module_inst: work@OBSERVER (work@OBSERVER), file:${SURELOG_DIR}/tests/OneNetModPortGeneric/dut.v, line:30:1, endln:32:10 |vpiRhs: \_hier_path: (intf.observe), line:31:17, endln:31:29 |vpiParent: @@ -494,7 +494,7 @@ design: (work@TOP) |vpiActual: \_logic_net: (obs) |uhdmallModules: -\_module: work@SUB (work@SUB), file:${SURELOG_DIR}/tests/OneNetModPortGeneric/dut.v, line:26:1, endln:28:10 +\_module_inst: work@SUB (work@SUB), file:${SURELOG_DIR}/tests/OneNetModPortGeneric/dut.v, line:26:1, endln:28:10 |vpiParent: \_design: (work@TOP) |vpiFullName:work@SUB @@ -502,21 +502,21 @@ design: (work@TOP) |vpiNet: \_logic_net: (work@SUB.inp), line:26:24, endln:26:27 |vpiParent: - \_module: work@SUB (work@SUB), file:${SURELOG_DIR}/tests/OneNetModPortGeneric/dut.v, line:26:1, endln:28:10 + \_module_inst: work@SUB (work@SUB), file:${SURELOG_DIR}/tests/OneNetModPortGeneric/dut.v, line:26:1, endln:28:10 |vpiName:inp |vpiFullName:work@SUB.inp |vpiNetType:1 |vpiNet: \_logic_net: (work@SUB.out), line:26:40, endln:26:43 |vpiParent: - \_module: work@SUB (work@SUB), file:${SURELOG_DIR}/tests/OneNetModPortGeneric/dut.v, line:26:1, endln:28:10 + \_module_inst: work@SUB (work@SUB), file:${SURELOG_DIR}/tests/OneNetModPortGeneric/dut.v, line:26:1, endln:28:10 |vpiName:out |vpiFullName:work@SUB.out |vpiNetType:48 |vpiPort: \_port: (inp), line:26:24, endln:26:27 |vpiParent: - \_module: work@SUB (work@SUB), file:${SURELOG_DIR}/tests/OneNetModPortGeneric/dut.v, line:26:1, endln:28:10 + \_module_inst: work@SUB (work@SUB), file:${SURELOG_DIR}/tests/OneNetModPortGeneric/dut.v, line:26:1, endln:28:10 |vpiName:inp |vpiDirection:1 |vpiLowConn: @@ -528,7 +528,7 @@ design: (work@TOP) |vpiPort: \_port: (out), line:26:40, endln:26:43 |vpiParent: - \_module: work@SUB (work@SUB), file:${SURELOG_DIR}/tests/OneNetModPortGeneric/dut.v, line:26:1, endln:28:10 + \_module_inst: work@SUB (work@SUB), file:${SURELOG_DIR}/tests/OneNetModPortGeneric/dut.v, line:26:1, endln:28:10 |vpiName:out |vpiDirection:2 |vpiLowConn: @@ -540,7 +540,7 @@ design: (work@TOP) |vpiContAssign: \_cont_assign: , line:27:10, endln:27:19 |vpiParent: - \_module: work@SUB (work@SUB), file:${SURELOG_DIR}/tests/OneNetModPortGeneric/dut.v, line:26:1, endln:28:10 + \_module_inst: work@SUB (work@SUB), file:${SURELOG_DIR}/tests/OneNetModPortGeneric/dut.v, line:26:1, endln:28:10 |vpiRhs: \_ref_obj: (work@SUB.inp), line:27:16, endln:27:19 |vpiParent: @@ -558,13 +558,13 @@ design: (work@TOP) |vpiActual: \_logic_net: (work@TOP.dut1.middle1.sub1.out), line:26:40, endln:26:43 |uhdmallModules: -\_module: work@TOP (work@TOP), file:${SURELOG_DIR}/tests/OneNetModPortGeneric/tb.v, line:15:1, endln:20:10 +\_module_inst: work@TOP (work@TOP), file:${SURELOG_DIR}/tests/OneNetModPortGeneric/tb.v, line:15:1, endln:20:10 |vpiParent: \_design: (work@TOP) |vpiFullName:work@TOP |vpiDefName:work@TOP |uhdmallModules: -\_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/OneNetModPortGeneric/dut.v, line:2:1, endln:7:10 +\_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/OneNetModPortGeneric/dut.v, line:2:1, endln:7:10 |vpiParent: \_design: (work@TOP) |vpiFullName:work@dut @@ -572,21 +572,21 @@ design: (work@TOP) |vpiNet: \_logic_net: (work@dut.i), line:2:24, endln:2:25 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/OneNetModPortGeneric/dut.v, line:2:1, endln:7:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/OneNetModPortGeneric/dut.v, line:2:1, endln:7:10 |vpiName:i |vpiFullName:work@dut.i |vpiNetType:1 |vpiNet: \_logic_net: (work@dut.o), line:2:38, endln:2:39 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/OneNetModPortGeneric/dut.v, line:2:1, endln:7:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/OneNetModPortGeneric/dut.v, line:2:1, endln:7:10 |vpiName:o |vpiFullName:work@dut.o |vpiNetType:48 |vpiPort: \_port: (i), line:2:24, endln:2:25 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/OneNetModPortGeneric/dut.v, line:2:1, endln:7:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/OneNetModPortGeneric/dut.v, line:2:1, endln:7:10 |vpiName:i |vpiDirection:1 |vpiLowConn: @@ -598,7 +598,7 @@ design: (work@TOP) |vpiPort: \_port: (o), line:2:38, endln:2:39 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/OneNetModPortGeneric/dut.v, line:2:1, endln:7:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/OneNetModPortGeneric/dut.v, line:2:1, endln:7:10 |vpiName:o |vpiDirection:2 |vpiLowConn: @@ -610,7 +610,7 @@ design: (work@TOP) |vpiContAssign: \_cont_assign: , line:3:10, endln:3:26 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/OneNetModPortGeneric/dut.v, line:2:1, endln:7:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/OneNetModPortGeneric/dut.v, line:2:1, endln:7:10 |vpiRhs: \_ref_obj: (work@dut.i), line:3:25, endln:3:26 |vpiParent: @@ -635,7 +635,7 @@ design: (work@TOP) |vpiContAssign: \_cont_assign: , line:4:10, endln:4:28 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/OneNetModPortGeneric/dut.v, line:2:1, endln:7:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/OneNetModPortGeneric/dut.v, line:2:1, endln:7:10 |vpiRhs: \_hier_path: (conntb.observe), line:4:14, endln:4:28 |vpiParent: @@ -658,7 +658,7 @@ design: (work@TOP) |vpiActual: \_logic_net: (work@TOP.dut1.o), line:2:38, endln:2:39 |uhdmallModules: -\_module: work@middle (work@middle), file:${SURELOG_DIR}/tests/OneNetModPortGeneric/dut.v, line:22:1, endln:24:10 +\_module_inst: work@middle (work@middle), file:${SURELOG_DIR}/tests/OneNetModPortGeneric/dut.v, line:22:1, endln:24:10 |vpiParent: \_design: (work@TOP) |vpiFullName:work@middle @@ -666,13 +666,13 @@ design: (work@TOP) |vpiNet: \_logic_net: (work@middle.intf), line:22:26, endln:22:30 |vpiParent: - \_module: work@middle (work@middle), file:${SURELOG_DIR}/tests/OneNetModPortGeneric/dut.v, line:22:1, endln:24:10 + \_module_inst: work@middle (work@middle), file:${SURELOG_DIR}/tests/OneNetModPortGeneric/dut.v, line:22:1, endln:24:10 |vpiName:intf |vpiFullName:work@middle.intf |vpiPort: \_port: (intf), line:22:26, endln:22:30 |vpiParent: - \_module: work@middle (work@middle), file:${SURELOG_DIR}/tests/OneNetModPortGeneric/dut.v, line:22:1, endln:24:10 + \_module_inst: work@middle (work@middle), file:${SURELOG_DIR}/tests/OneNetModPortGeneric/dut.v, line:22:1, endln:24:10 |vpiName:intf |vpiDirection:3 |vpiLowConn: @@ -683,14 +683,14 @@ design: (work@TOP) \_unsupported_typespec: (intf), line:22:26, endln:22:30 |vpiName:intf |uhdmtopModules: -\_module: work@TOP (work@TOP), file:${SURELOG_DIR}/tests/OneNetModPortGeneric/tb.v, line:15:1, endln:20:10 +\_module_inst: work@TOP (work@TOP), file:${SURELOG_DIR}/tests/OneNetModPortGeneric/tb.v, line:15:1, endln:20:10 |vpiName:work@TOP |vpiDefName:work@TOP |vpiTop:1 |vpiProgram: \_program: work@TESTBENCH (work@TOP.tb), file:${SURELOG_DIR}/tests/OneNetModPortGeneric/tb.v, line:18:3, endln:18:35 |vpiParent: - \_module: work@TOP (work@TOP), file:${SURELOG_DIR}/tests/OneNetModPortGeneric/tb.v, line:15:1, endln:20:10 + \_module_inst: work@TOP (work@TOP), file:${SURELOG_DIR}/tests/OneNetModPortGeneric/tb.v, line:15:1, endln:20:10 |vpiName:tb |vpiFullName:work@TOP.tb |vpiDefName:work@TESTBENCH @@ -706,7 +706,7 @@ design: (work@TOP) |vpiName:intf |vpiFullName:work@TOP.tb.intf |vpiInstance: - \_module: work@TOP (work@TOP), file:${SURELOG_DIR}/tests/OneNetModPortGeneric/tb.v, line:15:1, endln:20:10 + \_module_inst: work@TOP (work@TOP), file:${SURELOG_DIR}/tests/OneNetModPortGeneric/tb.v, line:15:1, endln:20:10 |vpiProcess: \_initial: , line:2:3, endln:11:6 |vpiPort: @@ -734,16 +734,16 @@ design: (work@TOP) \_unsupported_typespec: (intf), line:1:31, endln:1:35 |vpiName:intf |vpiTopModule:1 - |vpiInterface: - \_interface: work@ConnectTB (work@TOP.conntb), file:${SURELOG_DIR}/tests/OneNetModPortGeneric/tb.v, line:16:3, endln:16:22 + |vpiInterfaceInst: + \_interface_inst: work@ConnectTB (work@TOP.conntb), file:${SURELOG_DIR}/tests/OneNetModPortGeneric/tb.v, line:16:3, endln:16:22 |vpiParent: - \_module: work@TOP (work@TOP), file:${SURELOG_DIR}/tests/OneNetModPortGeneric/tb.v, line:15:1, endln:20:10 + \_module_inst: work@TOP (work@TOP), file:${SURELOG_DIR}/tests/OneNetModPortGeneric/tb.v, line:15:1, endln:20:10 |vpiName:conntb |vpiFullName:work@TOP.conntb |vpiVariables: \_logic_var: (work@TOP.conntb.drive), line:10:9, endln:10:14 |vpiParent: - \_interface: work@ConnectTB (work@TOP.conntb), file:${SURELOG_DIR}/tests/OneNetModPortGeneric/tb.v, line:16:3, endln:16:22 + \_interface_inst: work@ConnectTB (work@TOP.conntb), file:${SURELOG_DIR}/tests/OneNetModPortGeneric/tb.v, line:16:3, endln:16:22 |vpiTypespec: \_logic_typespec: , line:10:3, endln:10:8 |vpiName:drive @@ -752,7 +752,7 @@ design: (work@TOP) |vpiVariables: \_logic_var: (work@TOP.conntb.observe), line:11:9, endln:11:16 |vpiParent: - \_interface: work@ConnectTB (work@TOP.conntb), file:${SURELOG_DIR}/tests/OneNetModPortGeneric/tb.v, line:16:3, endln:16:22 + \_interface_inst: work@ConnectTB (work@TOP.conntb), file:${SURELOG_DIR}/tests/OneNetModPortGeneric/tb.v, line:16:3, endln:16:22 |vpiTypespec: \_logic_typespec: , line:11:3, endln:11:8 |vpiName:observe @@ -761,7 +761,7 @@ design: (work@TOP) |vpiVariables: \_logic_var: (work@TOP.conntb.drive), line:10:9, endln:10:14 |vpiParent: - \_interface: work@ConnectTB (work@TOP.conntb), file:${SURELOG_DIR}/tests/OneNetModPortGeneric/tb.v, line:16:3, endln:16:22 + \_interface_inst: work@ConnectTB (work@TOP.conntb), file:${SURELOG_DIR}/tests/OneNetModPortGeneric/tb.v, line:16:3, endln:16:22 |vpiTypespec: \_logic_typespec: , line:10:3, endln:10:8 |vpiName:drive @@ -770,7 +770,7 @@ design: (work@TOP) |vpiVariables: \_logic_var: (work@TOP.conntb.observe), line:11:9, endln:11:16 |vpiParent: - \_interface: work@ConnectTB (work@TOP.conntb), file:${SURELOG_DIR}/tests/OneNetModPortGeneric/tb.v, line:16:3, endln:16:22 + \_interface_inst: work@ConnectTB (work@TOP.conntb), file:${SURELOG_DIR}/tests/OneNetModPortGeneric/tb.v, line:16:3, endln:16:22 |vpiTypespec: \_logic_typespec: , line:11:3, endln:11:8 |vpiName:observe @@ -780,11 +780,11 @@ design: (work@TOP) |vpiDefFile:${SURELOG_DIR}/tests/OneNetModPortGeneric/dut.v |vpiDefLineNo:9 |vpiInstance: - \_module: work@TOP (work@TOP), file:${SURELOG_DIR}/tests/OneNetModPortGeneric/tb.v, line:15:1, endln:20:10 + \_module_inst: work@TOP (work@TOP), file:${SURELOG_DIR}/tests/OneNetModPortGeneric/tb.v, line:15:1, endln:20:10 |vpiModport: \_modport: (dut), line:12:11, endln:12:14 |vpiParent: - \_interface: work@ConnectTB (work@TOP.conntb), file:${SURELOG_DIR}/tests/OneNetModPortGeneric/tb.v, line:16:3, endln:16:22 + \_interface_inst: work@ConnectTB (work@TOP.conntb), file:${SURELOG_DIR}/tests/OneNetModPortGeneric/tb.v, line:16:3, endln:16:22 |vpiName:dut |vpiIODecl: \_io_decl: (drive), line:13:11, endln:13:16 @@ -798,12 +798,12 @@ design: (work@TOP) \_modport: (dut), line:12:11, endln:12:14 |vpiDirection:2 |vpiName:observe - |vpiInterface: - \_interface: work@ConnectTB (work@TOP.conntb), file:${SURELOG_DIR}/tests/OneNetModPortGeneric/tb.v, line:16:3, endln:16:22 + |vpiInterfaceInst: + \_interface_inst: work@ConnectTB (work@TOP.conntb), file:${SURELOG_DIR}/tests/OneNetModPortGeneric/tb.v, line:16:3, endln:16:22 |vpiModport: \_modport: (tb), line:16:11, endln:16:13 |vpiParent: - \_interface: work@ConnectTB (work@TOP.conntb), file:${SURELOG_DIR}/tests/OneNetModPortGeneric/tb.v, line:16:3, endln:16:22 + \_interface_inst: work@ConnectTB (work@TOP.conntb), file:${SURELOG_DIR}/tests/OneNetModPortGeneric/tb.v, line:16:3, endln:16:22 |vpiName:tb |vpiIODecl: \_io_decl: (drive), line:17:12, endln:17:17 @@ -817,12 +817,12 @@ design: (work@TOP) \_modport: (tb), line:16:11, endln:16:13 |vpiDirection:1 |vpiName:observe - |vpiInterface: - \_interface: work@ConnectTB (work@TOP.conntb), file:${SURELOG_DIR}/tests/OneNetModPortGeneric/tb.v, line:16:3, endln:16:22 - |vpiModule: - \_module: work@dut (work@TOP.dut1), file:${SURELOG_DIR}/tests/OneNetModPortGeneric/tb.v, line:17:3, endln:17:52 + |vpiInterfaceInst: + \_interface_inst: work@ConnectTB (work@TOP.conntb), file:${SURELOG_DIR}/tests/OneNetModPortGeneric/tb.v, line:16:3, endln:16:22 + |vpiModuleInst: + \_module_inst: work@dut (work@TOP.dut1), file:${SURELOG_DIR}/tests/OneNetModPortGeneric/tb.v, line:17:3, endln:17:52 |vpiParent: - \_module: work@TOP (work@TOP), file:${SURELOG_DIR}/tests/OneNetModPortGeneric/tb.v, line:15:1, endln:20:10 + \_module_inst: work@TOP (work@TOP), file:${SURELOG_DIR}/tests/OneNetModPortGeneric/tb.v, line:15:1, endln:20:10 |vpiName:dut1 |vpiFullName:work@TOP.dut1 |vpiDefName:work@dut @@ -831,7 +831,7 @@ design: (work@TOP) |vpiNet: \_logic_net: (work@TOP.dut1.i), line:2:24, endln:2:25 |vpiParent: - \_module: work@dut (work@TOP.dut1), file:${SURELOG_DIR}/tests/OneNetModPortGeneric/tb.v, line:17:3, endln:17:52 + \_module_inst: work@dut (work@TOP.dut1), file:${SURELOG_DIR}/tests/OneNetModPortGeneric/tb.v, line:17:3, endln:17:52 |vpiTypespec: \_logic_typespec: , line:2:19, endln:2:23 |vpiName:i @@ -840,18 +840,18 @@ design: (work@TOP) |vpiNet: \_logic_net: (work@TOP.dut1.o), line:2:38, endln:2:39 |vpiParent: - \_module: work@dut (work@TOP.dut1), file:${SURELOG_DIR}/tests/OneNetModPortGeneric/tb.v, line:17:3, endln:17:52 + \_module_inst: work@dut (work@TOP.dut1), file:${SURELOG_DIR}/tests/OneNetModPortGeneric/tb.v, line:17:3, endln:17:52 |vpiTypespec: \_logic_typespec: , line:2:34, endln:2:37 |vpiName:o |vpiFullName:work@TOP.dut1.o |vpiNetType:48 |vpiInstance: - \_module: work@TOP (work@TOP), file:${SURELOG_DIR}/tests/OneNetModPortGeneric/tb.v, line:15:1, endln:20:10 + \_module_inst: work@TOP (work@TOP), file:${SURELOG_DIR}/tests/OneNetModPortGeneric/tb.v, line:15:1, endln:20:10 |vpiPort: \_port: (i), line:2:24, endln:2:25 |vpiParent: - \_module: work@dut (work@TOP.dut1), file:${SURELOG_DIR}/tests/OneNetModPortGeneric/tb.v, line:17:3, endln:17:52 + \_module_inst: work@dut (work@TOP.dut1), file:${SURELOG_DIR}/tests/OneNetModPortGeneric/tb.v, line:17:3, endln:17:52 |vpiName:i |vpiDirection:1 |vpiHighConn: @@ -876,7 +876,7 @@ design: (work@TOP) |vpiPort: \_port: (o), line:2:38, endln:2:39 |vpiParent: - \_module: work@dut (work@TOP.dut1), file:${SURELOG_DIR}/tests/OneNetModPortGeneric/tb.v, line:17:3, endln:17:52 + \_module_inst: work@dut (work@TOP.dut1), file:${SURELOG_DIR}/tests/OneNetModPortGeneric/tb.v, line:17:3, endln:17:52 |vpiName:o |vpiDirection:2 |vpiHighConn: @@ -898,16 +898,16 @@ design: (work@TOP) \_logic_net: (work@TOP.dut1.o), line:2:38, endln:2:39 |vpiTypedef: \_logic_typespec: , line:2:34, endln:2:37 - |vpiInterface: - \_interface: work@ConnectTB (work@TOP.dut1.conntb), file:${SURELOG_DIR}/tests/OneNetModPortGeneric/dut.v, line:5:3, endln:5:22 + |vpiInterfaceInst: + \_interface_inst: work@ConnectTB (work@TOP.dut1.conntb), file:${SURELOG_DIR}/tests/OneNetModPortGeneric/dut.v, line:5:3, endln:5:22 |vpiParent: - \_module: work@dut (work@TOP.dut1), file:${SURELOG_DIR}/tests/OneNetModPortGeneric/tb.v, line:17:3, endln:17:52 + \_module_inst: work@dut (work@TOP.dut1), file:${SURELOG_DIR}/tests/OneNetModPortGeneric/tb.v, line:17:3, endln:17:52 |vpiName:conntb |vpiFullName:work@TOP.dut1.conntb |vpiVariables: \_logic_var: (work@TOP.dut1.conntb.drive), line:10:9, endln:10:14 |vpiParent: - \_interface: work@ConnectTB (work@TOP.dut1.conntb), file:${SURELOG_DIR}/tests/OneNetModPortGeneric/dut.v, line:5:3, endln:5:22 + \_interface_inst: work@ConnectTB (work@TOP.dut1.conntb), file:${SURELOG_DIR}/tests/OneNetModPortGeneric/dut.v, line:5:3, endln:5:22 |vpiTypespec: \_logic_typespec: , line:10:3, endln:10:8 |vpiName:drive @@ -916,7 +916,7 @@ design: (work@TOP) |vpiVariables: \_logic_var: (work@TOP.dut1.conntb.observe), line:11:9, endln:11:16 |vpiParent: - \_interface: work@ConnectTB (work@TOP.dut1.conntb), file:${SURELOG_DIR}/tests/OneNetModPortGeneric/dut.v, line:5:3, endln:5:22 + \_interface_inst: work@ConnectTB (work@TOP.dut1.conntb), file:${SURELOG_DIR}/tests/OneNetModPortGeneric/dut.v, line:5:3, endln:5:22 |vpiTypespec: \_logic_typespec: , line:11:3, endln:11:8 |vpiName:observe @@ -926,11 +926,11 @@ design: (work@TOP) |vpiDefFile:${SURELOG_DIR}/tests/OneNetModPortGeneric/dut.v |vpiDefLineNo:9 |vpiInstance: - \_module: work@dut (work@TOP.dut1), file:${SURELOG_DIR}/tests/OneNetModPortGeneric/tb.v, line:17:3, endln:17:52 + \_module_inst: work@dut (work@TOP.dut1), file:${SURELOG_DIR}/tests/OneNetModPortGeneric/tb.v, line:17:3, endln:17:52 |vpiModport: \_modport: (dut), line:12:11, endln:12:14 |vpiParent: - \_interface: work@ConnectTB (work@TOP.dut1.conntb), file:${SURELOG_DIR}/tests/OneNetModPortGeneric/dut.v, line:5:3, endln:5:22 + \_interface_inst: work@ConnectTB (work@TOP.dut1.conntb), file:${SURELOG_DIR}/tests/OneNetModPortGeneric/dut.v, line:5:3, endln:5:22 |vpiName:dut |vpiIODecl: \_io_decl: (drive), line:13:11, endln:13:16 @@ -944,12 +944,12 @@ design: (work@TOP) \_modport: (dut), line:12:11, endln:12:14 |vpiDirection:2 |vpiName:observe - |vpiInterface: - \_interface: work@ConnectTB (work@TOP.dut1.conntb), file:${SURELOG_DIR}/tests/OneNetModPortGeneric/dut.v, line:5:3, endln:5:22 + |vpiInterfaceInst: + \_interface_inst: work@ConnectTB (work@TOP.dut1.conntb), file:${SURELOG_DIR}/tests/OneNetModPortGeneric/dut.v, line:5:3, endln:5:22 |vpiModport: \_modport: (tb), line:16:11, endln:16:13 |vpiParent: - \_interface: work@ConnectTB (work@TOP.dut1.conntb), file:${SURELOG_DIR}/tests/OneNetModPortGeneric/dut.v, line:5:3, endln:5:22 + \_interface_inst: work@ConnectTB (work@TOP.dut1.conntb), file:${SURELOG_DIR}/tests/OneNetModPortGeneric/dut.v, line:5:3, endln:5:22 |vpiName:tb |vpiIODecl: \_io_decl: (drive), line:17:12, endln:17:17 @@ -963,12 +963,12 @@ design: (work@TOP) \_modport: (tb), line:16:11, endln:16:13 |vpiDirection:1 |vpiName:observe - |vpiInterface: - \_interface: work@ConnectTB (work@TOP.dut1.conntb), file:${SURELOG_DIR}/tests/OneNetModPortGeneric/dut.v, line:5:3, endln:5:22 - |vpiModule: - \_module: work@middle (work@TOP.dut1.middle1), file:${SURELOG_DIR}/tests/OneNetModPortGeneric/dut.v, line:6:3, endln:6:39 + |vpiInterfaceInst: + \_interface_inst: work@ConnectTB (work@TOP.dut1.conntb), file:${SURELOG_DIR}/tests/OneNetModPortGeneric/dut.v, line:5:3, endln:5:22 + |vpiModuleInst: + \_module_inst: work@middle (work@TOP.dut1.middle1), file:${SURELOG_DIR}/tests/OneNetModPortGeneric/dut.v, line:6:3, endln:6:39 |vpiParent: - \_module: work@dut (work@TOP.dut1), file:${SURELOG_DIR}/tests/OneNetModPortGeneric/tb.v, line:17:3, endln:17:52 + \_module_inst: work@dut (work@TOP.dut1), file:${SURELOG_DIR}/tests/OneNetModPortGeneric/tb.v, line:17:3, endln:17:52 |vpiName:middle1 |vpiFullName:work@TOP.dut1.middle1 |vpiDefName:work@middle @@ -977,18 +977,18 @@ design: (work@TOP) |vpiNet: \_logic_net: (work@TOP.dut1.middle1.intf), line:22:26, endln:22:30 |vpiParent: - \_module: work@middle (work@TOP.dut1.middle1), file:${SURELOG_DIR}/tests/OneNetModPortGeneric/dut.v, line:6:3, endln:6:39 + \_module_inst: work@middle (work@TOP.dut1.middle1), file:${SURELOG_DIR}/tests/OneNetModPortGeneric/dut.v, line:6:3, endln:6:39 |vpiTypespec: \_unsupported_typespec: (intf), line:22:26, endln:22:30 |vpiName:intf |vpiName:intf |vpiFullName:work@TOP.dut1.middle1.intf |vpiInstance: - \_module: work@dut (work@TOP.dut1), file:${SURELOG_DIR}/tests/OneNetModPortGeneric/tb.v, line:17:3, endln:17:52 + \_module_inst: work@dut (work@TOP.dut1), file:${SURELOG_DIR}/tests/OneNetModPortGeneric/tb.v, line:17:3, endln:17:52 |vpiPort: \_port: (intf), line:22:26, endln:22:30 |vpiParent: - \_module: work@middle (work@TOP.dut1.middle1), file:${SURELOG_DIR}/tests/OneNetModPortGeneric/dut.v, line:6:3, endln:6:39 + \_module_inst: work@middle (work@TOP.dut1.middle1), file:${SURELOG_DIR}/tests/OneNetModPortGeneric/dut.v, line:6:3, endln:6:39 |vpiName:intf |vpiDirection:3 |vpiHighConn: @@ -1009,17 +1009,17 @@ design: (work@TOP) |vpiTypedef: \_unsupported_typespec: (intf), line:22:26, endln:22:30 |vpiName:intf - |vpiInterface: - \_interface: work@ConnectTB (work@TOP.dut1.middle1.intf), file:${SURELOG_DIR}/tests/OneNetModPortGeneric/dut.v, line:22:0 + |vpiInterfaceInst: + \_interface_inst: work@ConnectTB (work@TOP.dut1.middle1.intf), file:${SURELOG_DIR}/tests/OneNetModPortGeneric/dut.v, line:22:0 |vpiParent: - \_module: work@middle (work@TOP.dut1.middle1), file:${SURELOG_DIR}/tests/OneNetModPortGeneric/dut.v, line:6:3, endln:6:39 + \_module_inst: work@middle (work@TOP.dut1.middle1), file:${SURELOG_DIR}/tests/OneNetModPortGeneric/dut.v, line:6:3, endln:6:39 |vpiName:intf |vpiFullName:work@TOP.dut1.middle1.intf |vpiDefName:work@ConnectTB |vpiModport: \_modport: (dut), line:12:11, endln:12:14 |vpiParent: - \_interface: work@ConnectTB (work@TOP.dut1.middle1.intf), file:${SURELOG_DIR}/tests/OneNetModPortGeneric/dut.v, line:22:0 + \_interface_inst: work@ConnectTB (work@TOP.dut1.middle1.intf), file:${SURELOG_DIR}/tests/OneNetModPortGeneric/dut.v, line:22:0 |vpiName:dut |vpiIODecl: \_io_decl: (drive), line:13:11, endln:13:16 @@ -1041,12 +1041,12 @@ design: (work@TOP) \_logic_typespec: , line:11:3, endln:11:8 |vpiName:observe |vpiVisibility:1 - |vpiInterface: - \_interface: work@ConnectTB (work@TOP.dut1.middle1.intf), file:${SURELOG_DIR}/tests/OneNetModPortGeneric/dut.v, line:22:0 - |vpiModule: - \_module: work@SUB (work@TOP.dut1.middle1.sub1), file:${SURELOG_DIR}/tests/OneNetModPortGeneric/dut.v, line:23:3, endln:23:50 + |vpiInterfaceInst: + \_interface_inst: work@ConnectTB (work@TOP.dut1.middle1.intf), file:${SURELOG_DIR}/tests/OneNetModPortGeneric/dut.v, line:22:0 + |vpiModuleInst: + \_module_inst: work@SUB (work@TOP.dut1.middle1.sub1), file:${SURELOG_DIR}/tests/OneNetModPortGeneric/dut.v, line:23:3, endln:23:50 |vpiParent: - \_module: work@middle (work@TOP.dut1.middle1), file:${SURELOG_DIR}/tests/OneNetModPortGeneric/dut.v, line:6:3, endln:6:39 + \_module_inst: work@middle (work@TOP.dut1.middle1), file:${SURELOG_DIR}/tests/OneNetModPortGeneric/dut.v, line:6:3, endln:6:39 |vpiName:sub1 |vpiFullName:work@TOP.dut1.middle1.sub1 |vpiDefName:work@SUB @@ -1055,7 +1055,7 @@ design: (work@TOP) |vpiNet: \_logic_net: (work@TOP.dut1.middle1.sub1.inp), line:26:24, endln:26:27 |vpiParent: - \_module: work@SUB (work@TOP.dut1.middle1.sub1), file:${SURELOG_DIR}/tests/OneNetModPortGeneric/dut.v, line:23:3, endln:23:50 + \_module_inst: work@SUB (work@TOP.dut1.middle1.sub1), file:${SURELOG_DIR}/tests/OneNetModPortGeneric/dut.v, line:23:3, endln:23:50 |vpiTypespec: \_logic_typespec: , line:26:19, endln:26:23 |vpiName:inp @@ -1064,18 +1064,18 @@ design: (work@TOP) |vpiNet: \_logic_net: (work@TOP.dut1.middle1.sub1.out), line:26:40, endln:26:43 |vpiParent: - \_module: work@SUB (work@TOP.dut1.middle1.sub1), file:${SURELOG_DIR}/tests/OneNetModPortGeneric/dut.v, line:23:3, endln:23:50 + \_module_inst: work@SUB (work@TOP.dut1.middle1.sub1), file:${SURELOG_DIR}/tests/OneNetModPortGeneric/dut.v, line:23:3, endln:23:50 |vpiTypespec: \_logic_typespec: , line:26:36, endln:26:39 |vpiName:out |vpiFullName:work@TOP.dut1.middle1.sub1.out |vpiNetType:48 |vpiInstance: - \_module: work@middle (work@TOP.dut1.middle1), file:${SURELOG_DIR}/tests/OneNetModPortGeneric/dut.v, line:6:3, endln:6:39 + \_module_inst: work@middle (work@TOP.dut1.middle1), file:${SURELOG_DIR}/tests/OneNetModPortGeneric/dut.v, line:6:3, endln:6:39 |vpiPort: \_port: (inp), line:26:24, endln:26:27 |vpiParent: - \_module: work@SUB (work@TOP.dut1.middle1.sub1), file:${SURELOG_DIR}/tests/OneNetModPortGeneric/dut.v, line:23:3, endln:23:50 + \_module_inst: work@SUB (work@TOP.dut1.middle1.sub1), file:${SURELOG_DIR}/tests/OneNetModPortGeneric/dut.v, line:23:3, endln:23:50 |vpiName:inp |vpiDirection:1 |vpiHighConn: @@ -1106,7 +1106,7 @@ design: (work@TOP) |vpiPort: \_port: (out), line:26:40, endln:26:43 |vpiParent: - \_module: work@SUB (work@TOP.dut1.middle1.sub1), file:${SURELOG_DIR}/tests/OneNetModPortGeneric/dut.v, line:23:3, endln:23:50 + \_module_inst: work@SUB (work@TOP.dut1.middle1.sub1), file:${SURELOG_DIR}/tests/OneNetModPortGeneric/dut.v, line:23:3, endln:23:50 |vpiName:out |vpiDirection:2 |vpiHighConn: @@ -1140,10 +1140,10 @@ design: (work@TOP) \_cont_assign: , line:3:10, endln:3:26 |vpiContAssign: \_cont_assign: , line:4:10, endln:4:28 - |vpiModule: - \_module: work@OBSERVER (work@TOP.obs), file:${SURELOG_DIR}/tests/OneNetModPortGeneric/tb.v, line:19:3, endln:19:32 + |vpiModuleInst: + \_module_inst: work@OBSERVER (work@TOP.obs), file:${SURELOG_DIR}/tests/OneNetModPortGeneric/tb.v, line:19:3, endln:19:32 |vpiParent: - \_module: work@TOP (work@TOP), file:${SURELOG_DIR}/tests/OneNetModPortGeneric/tb.v, line:15:1, endln:20:10 + \_module_inst: work@TOP (work@TOP), file:${SURELOG_DIR}/tests/OneNetModPortGeneric/tb.v, line:15:1, endln:20:10 |vpiName:obs |vpiFullName:work@TOP.obs |vpiDefName:work@OBSERVER @@ -1152,7 +1152,7 @@ design: (work@TOP) |vpiNet: \_logic_net: (work@TOP.obs.intf), line:30:27, endln:30:31 |vpiParent: - \_module: work@OBSERVER (work@TOP.obs), file:${SURELOG_DIR}/tests/OneNetModPortGeneric/tb.v, line:19:3, endln:19:32 + \_module_inst: work@OBSERVER (work@TOP.obs), file:${SURELOG_DIR}/tests/OneNetModPortGeneric/tb.v, line:19:3, endln:19:32 |vpiTypespec: \_unsupported_typespec: (intf), line:30:27, endln:30:31 |vpiName:intf @@ -1163,11 +1163,11 @@ design: (work@TOP) |vpiName:obs |vpiNetType:1 |vpiInstance: - \_module: work@TOP (work@TOP), file:${SURELOG_DIR}/tests/OneNetModPortGeneric/tb.v, line:15:1, endln:20:10 + \_module_inst: work@TOP (work@TOP), file:${SURELOG_DIR}/tests/OneNetModPortGeneric/tb.v, line:15:1, endln:20:10 |vpiPort: \_port: (intf), line:30:27, endln:30:31 |vpiParent: - \_module: work@OBSERVER (work@TOP.obs), file:${SURELOG_DIR}/tests/OneNetModPortGeneric/tb.v, line:19:3, endln:19:32 + \_module_inst: work@OBSERVER (work@TOP.obs), file:${SURELOG_DIR}/tests/OneNetModPortGeneric/tb.v, line:19:3, endln:19:32 |vpiName:intf |vpiDirection:3 |vpiHighConn: @@ -1175,25 +1175,25 @@ design: (work@TOP) |vpiName:conntb |vpiFullName:work@TOP.conntb |vpiActual: - \_interface: work@ConnectTB (work@TOP.conntb), file:${SURELOG_DIR}/tests/OneNetModPortGeneric/tb.v, line:16:0 + \_interface_inst: work@ConnectTB (work@TOP.conntb), file:${SURELOG_DIR}/tests/OneNetModPortGeneric/tb.v, line:16:0 |vpiLowConn: \_ref_obj: , line:19:16, endln:19:29 |vpiActual: - \_interface: work@ConnectTB (work@TOP.obs.intf), file:${SURELOG_DIR}/tests/OneNetModPortGeneric/tb.v, line:19:0 + \_interface_inst: work@ConnectTB (work@TOP.obs.intf), file:${SURELOG_DIR}/tests/OneNetModPortGeneric/tb.v, line:19:0 |vpiTypedef: \_unsupported_typespec: (intf), line:30:27, endln:30:31 |vpiName:intf - |vpiInterface: - \_interface: work@ConnectTB (work@TOP.obs.intf), file:${SURELOG_DIR}/tests/OneNetModPortGeneric/tb.v, line:19:0 + |vpiInterfaceInst: + \_interface_inst: work@ConnectTB (work@TOP.obs.intf), file:${SURELOG_DIR}/tests/OneNetModPortGeneric/tb.v, line:19:0 |vpiParent: - \_module: work@OBSERVER (work@TOP.obs), file:${SURELOG_DIR}/tests/OneNetModPortGeneric/tb.v, line:19:3, endln:19:32 + \_module_inst: work@OBSERVER (work@TOP.obs), file:${SURELOG_DIR}/tests/OneNetModPortGeneric/tb.v, line:19:3, endln:19:32 |vpiName:intf |vpiFullName:work@TOP.obs.intf |vpiDefName:work@ConnectTB |vpiModport: \_modport: (dut), line:12:11, endln:12:14 |vpiParent: - \_interface: work@ConnectTB (work@TOP.obs.intf), file:${SURELOG_DIR}/tests/OneNetModPortGeneric/tb.v, line:19:0 + \_interface_inst: work@ConnectTB (work@TOP.obs.intf), file:${SURELOG_DIR}/tests/OneNetModPortGeneric/tb.v, line:19:0 |vpiName:dut |vpiIODecl: \_io_decl: (drive), line:13:11, endln:13:16 @@ -1207,12 +1207,12 @@ design: (work@TOP) |vpiName:observe |vpiExpr: \_logic_var: (work@TOP.conntb.observe), line:11:9, endln:11:16 - |vpiInterface: - \_interface: work@ConnectTB (work@TOP.obs.intf), file:${SURELOG_DIR}/tests/OneNetModPortGeneric/tb.v, line:19:0 + |vpiInterfaceInst: + \_interface_inst: work@ConnectTB (work@TOP.obs.intf), file:${SURELOG_DIR}/tests/OneNetModPortGeneric/tb.v, line:19:0 |vpiModport: \_modport: (tb), line:16:11, endln:16:13 |vpiParent: - \_interface: work@ConnectTB (work@TOP.obs.intf), file:${SURELOG_DIR}/tests/OneNetModPortGeneric/tb.v, line:19:0 + \_interface_inst: work@ConnectTB (work@TOP.obs.intf), file:${SURELOG_DIR}/tests/OneNetModPortGeneric/tb.v, line:19:0 |vpiName:tb |vpiIODecl: \_io_decl: (drive), line:17:12, endln:17:17 @@ -1226,8 +1226,8 @@ design: (work@TOP) |vpiName:observe |vpiExpr: \_logic_var: (work@TOP.conntb.observe), line:11:9, endln:11:16 - |vpiInterface: - \_interface: work@ConnectTB (work@TOP.obs.intf), file:${SURELOG_DIR}/tests/OneNetModPortGeneric/tb.v, line:19:0 + |vpiInterfaceInst: + \_interface_inst: work@ConnectTB (work@TOP.obs.intf), file:${SURELOG_DIR}/tests/OneNetModPortGeneric/tb.v, line:19:0 |vpiContAssign: \_cont_assign: , line:31:11, endln:31:29 =================== diff --git a/tests/OneNetNonAnsi/OneNetNonAnsi.log b/tests/OneNetNonAnsi/OneNetNonAnsi.log index 67851d9eac..35b72d9669 100644 --- a/tests/OneNetNonAnsi/OneNetNonAnsi.log +++ b/tests/OneNetNonAnsi/OneNetNonAnsi.log @@ -37,7 +37,7 @@ immediate_assert 2 initial 2 logic_net 8 logic_typespec 7 -module 5 +module_inst 5 operation 2 port 4 ref_obj 18 @@ -55,7 +55,7 @@ sys_func_call 9 design: (work@tb) |vpiName:work@tb |uhdmallModules: -\_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/OneNetNonAnsi/dut.v, line:1:1, endln:7:10 +\_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/OneNetNonAnsi/dut.v, line:1:1, endln:7:10 |vpiParent: \_design: (work@tb) |vpiFullName:work@dut @@ -63,21 +63,21 @@ design: (work@tb) |vpiNet: \_logic_net: (work@dut.i), line:4:8, endln:4:9 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/OneNetNonAnsi/dut.v, line:1:1, endln:7:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/OneNetNonAnsi/dut.v, line:1:1, endln:7:10 |vpiName:i |vpiFullName:work@dut.i |vpiNetType:1 |vpiNet: \_logic_net: (work@dut.o), line:5:7, endln:5:8 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/OneNetNonAnsi/dut.v, line:1:1, endln:7:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/OneNetNonAnsi/dut.v, line:1:1, endln:7:10 |vpiName:o |vpiFullName:work@dut.o |vpiNetType:48 |vpiPort: \_port: (i), line:1:13, endln:1:14 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/OneNetNonAnsi/dut.v, line:1:1, endln:7:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/OneNetNonAnsi/dut.v, line:1:1, endln:7:10 |vpiName:i |vpiDirection:1 |vpiLowConn: @@ -89,7 +89,7 @@ design: (work@tb) |vpiPort: \_port: (o), line:1:16, endln:1:17 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/OneNetNonAnsi/dut.v, line:1:1, endln:7:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/OneNetNonAnsi/dut.v, line:1:1, endln:7:10 |vpiName:o |vpiDirection:2 |vpiLowConn: @@ -101,7 +101,7 @@ design: (work@tb) |vpiContAssign: \_cont_assign: , line:6:10, endln:6:15 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/OneNetNonAnsi/dut.v, line:1:1, endln:7:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/OneNetNonAnsi/dut.v, line:1:1, endln:7:10 |vpiRhs: \_ref_obj: (work@dut.i), line:6:14, endln:6:15 |vpiParent: @@ -119,7 +119,7 @@ design: (work@tb) |vpiActual: \_logic_net: (work@tb.dut1.o), line:5:7, endln:5:8 |uhdmallModules: -\_module: work@tb (work@tb), file:${SURELOG_DIR}/tests/OneNetNonAnsi/tb.v, line:1:1, endln:21:10 +\_module_inst: work@tb (work@tb), file:${SURELOG_DIR}/tests/OneNetNonAnsi/tb.v, line:1:1, endln:21:10 |vpiParent: \_design: (work@tb) |vpiFullName:work@tb @@ -127,19 +127,19 @@ design: (work@tb) |vpiNet: \_logic_net: (work@tb.i), line:2:9, endln:2:10 |vpiParent: - \_module: work@tb (work@tb), file:${SURELOG_DIR}/tests/OneNetNonAnsi/tb.v, line:1:1, endln:21:10 + \_module_inst: work@tb (work@tb), file:${SURELOG_DIR}/tests/OneNetNonAnsi/tb.v, line:1:1, endln:21:10 |vpiName:i |vpiFullName:work@tb.i |vpiNet: \_logic_net: (work@tb.o), line:2:12, endln:2:13 |vpiParent: - \_module: work@tb (work@tb), file:${SURELOG_DIR}/tests/OneNetNonAnsi/tb.v, line:1:1, endln:21:10 + \_module_inst: work@tb (work@tb), file:${SURELOG_DIR}/tests/OneNetNonAnsi/tb.v, line:1:1, endln:21:10 |vpiName:o |vpiFullName:work@tb.o |vpiProcess: \_initial: , line:4:3, endln:9:6 |vpiParent: - \_module: work@tb (work@tb), file:${SURELOG_DIR}/tests/OneNetNonAnsi/tb.v, line:1:1, endln:21:10 + \_module_inst: work@tb (work@tb), file:${SURELOG_DIR}/tests/OneNetNonAnsi/tb.v, line:1:1, endln:21:10 |vpiStmt: \_begin: (work@tb), line:4:11, endln:9:6 |vpiParent: @@ -210,7 +210,7 @@ design: (work@tb) |vpiProcess: \_initial: , line:11:3, endln:17:6 |vpiParent: - \_module: work@tb (work@tb), file:${SURELOG_DIR}/tests/OneNetNonAnsi/tb.v, line:1:1, endln:21:10 + \_module_inst: work@tb (work@tb), file:${SURELOG_DIR}/tests/OneNetNonAnsi/tb.v, line:1:1, endln:21:10 |vpiStmt: \_begin: (work@tb), line:12:3, endln:17:6 |vpiParent: @@ -394,14 +394,14 @@ design: (work@tb) |vpiConstType:6 |vpiName:$fatal |uhdmtopModules: -\_module: work@tb (work@tb), file:${SURELOG_DIR}/tests/OneNetNonAnsi/tb.v, line:1:1, endln:21:10 +\_module_inst: work@tb (work@tb), file:${SURELOG_DIR}/tests/OneNetNonAnsi/tb.v, line:1:1, endln:21:10 |vpiName:work@tb |vpiDefName:work@tb |vpiTop:1 |vpiNet: \_logic_net: (work@tb.i), line:2:9, endln:2:10 |vpiParent: - \_module: work@tb (work@tb), file:${SURELOG_DIR}/tests/OneNetNonAnsi/tb.v, line:1:1, endln:21:10 + \_module_inst: work@tb (work@tb), file:${SURELOG_DIR}/tests/OneNetNonAnsi/tb.v, line:1:1, endln:21:10 |vpiTypespec: \_logic_typespec: , line:2:3, endln:2:8 |vpiName:i @@ -409,7 +409,7 @@ design: (work@tb) |vpiNet: \_logic_net: (work@tb.o), line:2:12, endln:2:13 |vpiParent: - \_module: work@tb (work@tb), file:${SURELOG_DIR}/tests/OneNetNonAnsi/tb.v, line:1:1, endln:21:10 + \_module_inst: work@tb (work@tb), file:${SURELOG_DIR}/tests/OneNetNonAnsi/tb.v, line:1:1, endln:21:10 |vpiTypespec: \_logic_typespec: , line:2:3, endln:2:8 |vpiName:o @@ -419,10 +419,10 @@ design: (work@tb) \_initial: , line:4:3, endln:9:6 |vpiProcess: \_initial: , line:11:3, endln:17:6 - |vpiModule: - \_module: work@dut (work@tb.dut1), file:${SURELOG_DIR}/tests/OneNetNonAnsi/tb.v, line:19:3, endln:19:17 + |vpiModuleInst: + \_module_inst: work@dut (work@tb.dut1), file:${SURELOG_DIR}/tests/OneNetNonAnsi/tb.v, line:19:3, endln:19:17 |vpiParent: - \_module: work@tb (work@tb), file:${SURELOG_DIR}/tests/OneNetNonAnsi/tb.v, line:1:1, endln:21:10 + \_module_inst: work@tb (work@tb), file:${SURELOG_DIR}/tests/OneNetNonAnsi/tb.v, line:1:1, endln:21:10 |vpiName:dut1 |vpiFullName:work@tb.dut1 |vpiDefName:work@dut @@ -431,7 +431,7 @@ design: (work@tb) |vpiNet: \_logic_net: (work@tb.dut1.i), line:4:8, endln:4:9 |vpiParent: - \_module: work@dut (work@tb.dut1), file:${SURELOG_DIR}/tests/OneNetNonAnsi/tb.v, line:19:3, endln:19:17 + \_module_inst: work@dut (work@tb.dut1), file:${SURELOG_DIR}/tests/OneNetNonAnsi/tb.v, line:19:3, endln:19:17 |vpiTypespec: \_logic_typespec: , line:4:3, endln:4:7 |vpiName:i @@ -440,18 +440,18 @@ design: (work@tb) |vpiNet: \_logic_net: (work@tb.dut1.o), line:5:7, endln:5:8 |vpiParent: - \_module: work@dut (work@tb.dut1), file:${SURELOG_DIR}/tests/OneNetNonAnsi/tb.v, line:19:3, endln:19:17 + \_module_inst: work@dut (work@tb.dut1), file:${SURELOG_DIR}/tests/OneNetNonAnsi/tb.v, line:19:3, endln:19:17 |vpiTypespec: \_logic_typespec: , line:5:3, endln:5:6 |vpiName:o |vpiFullName:work@tb.dut1.o |vpiNetType:48 |vpiInstance: - \_module: work@tb (work@tb), file:${SURELOG_DIR}/tests/OneNetNonAnsi/tb.v, line:1:1, endln:21:10 + \_module_inst: work@tb (work@tb), file:${SURELOG_DIR}/tests/OneNetNonAnsi/tb.v, line:1:1, endln:21:10 |vpiPort: \_port: (i), line:1:13, endln:1:14 |vpiParent: - \_module: work@dut (work@tb.dut1), file:${SURELOG_DIR}/tests/OneNetNonAnsi/tb.v, line:19:3, endln:19:17 + \_module_inst: work@dut (work@tb.dut1), file:${SURELOG_DIR}/tests/OneNetNonAnsi/tb.v, line:19:3, endln:19:17 |vpiName:i |vpiDirection:1 |vpiHighConn: @@ -471,7 +471,7 @@ design: (work@tb) |vpiPort: \_port: (o), line:1:16, endln:1:17 |vpiParent: - \_module: work@dut (work@tb.dut1), file:${SURELOG_DIR}/tests/OneNetNonAnsi/tb.v, line:19:3, endln:19:17 + \_module_inst: work@dut (work@tb.dut1), file:${SURELOG_DIR}/tests/OneNetNonAnsi/tb.v, line:19:3, endln:19:17 |vpiName:o |vpiDirection:2 |vpiHighConn: diff --git a/tests/OneNetRange/OneNetRange.log b/tests/OneNetRange/OneNetRange.log index bb25edc651..fe32239d13 100644 --- a/tests/OneNetRange/OneNetRange.log +++ b/tests/OneNetRange/OneNetRange.log @@ -55,11 +55,11 @@ hier_path 6 immediate_assert 2 initial 1 int_typespec 12 -interface 6 +interface_inst 6 interface_typespec 3 logic_net 25 logic_typespec 30 -module 23 +module_inst 23 operation 46 param_assign 13 parameter 13 @@ -81,14 +81,14 @@ sys_func_call 9 design: (work@TOP) |vpiName:work@TOP |uhdmallInterfaces: -\_interface: work@ConnectTB (work@ConnectTB), file:${SURELOG_DIR}/tests/OneNetRange/dut.v, line:8:1, endln:9:13 +\_interface_inst: work@ConnectTB (work@ConnectTB), file:${SURELOG_DIR}/tests/OneNetRange/dut.v, line:8:1, endln:9:13 |vpiParent: \_design: (work@TOP) |vpiFullName:work@ConnectTB |vpiParameter: \_parameter: (work@ConnectTB.width), line:8:33, endln:8:38 |vpiParent: - \_interface: work@ConnectTB (work@ConnectTB), file:${SURELOG_DIR}/tests/OneNetRange/dut.v, line:8:1, endln:9:13 + \_interface_inst: work@ConnectTB (work@ConnectTB), file:${SURELOG_DIR}/tests/OneNetRange/dut.v, line:8:1, endln:9:13 |UINT:1 |vpiTypespec: \_int_typespec: @@ -97,7 +97,7 @@ design: (work@TOP) |vpiParamAssign: \_param_assign: , line:8:33, endln:8:42 |vpiParent: - \_interface: work@ConnectTB (work@ConnectTB), file:${SURELOG_DIR}/tests/OneNetRange/dut.v, line:8:1, endln:9:13 + \_interface_inst: work@ConnectTB (work@ConnectTB), file:${SURELOG_DIR}/tests/OneNetRange/dut.v, line:8:1, endln:9:13 |vpiRhs: \_constant: , line:8:41, endln:8:42 |vpiDecompile:1 @@ -112,21 +112,21 @@ design: (work@TOP) |vpiNet: \_logic_net: (work@ConnectTB.con_i), line:8:68, endln:8:73 |vpiParent: - \_interface: work@ConnectTB (work@ConnectTB), file:${SURELOG_DIR}/tests/OneNetRange/dut.v, line:8:1, endln:9:13 + \_interface_inst: work@ConnectTB (work@ConnectTB), file:${SURELOG_DIR}/tests/OneNetRange/dut.v, line:8:1, endln:9:13 |vpiName:con_i |vpiFullName:work@ConnectTB.con_i |vpiNetType:1 |vpiNet: \_logic_net: (work@ConnectTB.con_o), line:8:98, endln:8:103 |vpiParent: - \_interface: work@ConnectTB (work@ConnectTB), file:${SURELOG_DIR}/tests/OneNetRange/dut.v, line:8:1, endln:9:13 + \_interface_inst: work@ConnectTB (work@ConnectTB), file:${SURELOG_DIR}/tests/OneNetRange/dut.v, line:8:1, endln:9:13 |vpiName:con_o |vpiFullName:work@ConnectTB.con_o |vpiNetType:48 |vpiPort: \_port: (con_i), line:8:68, endln:8:73 |vpiParent: - \_interface: work@ConnectTB (work@ConnectTB), file:${SURELOG_DIR}/tests/OneNetRange/dut.v, line:8:1, endln:9:13 + \_interface_inst: work@ConnectTB (work@ConnectTB), file:${SURELOG_DIR}/tests/OneNetRange/dut.v, line:8:1, endln:9:13 |vpiName:con_i |vpiDirection:1 |vpiLowConn: @@ -136,7 +136,7 @@ design: (work@TOP) |vpiPort: \_port: (con_o), line:8:98, endln:8:103 |vpiParent: - \_interface: work@ConnectTB (work@ConnectTB), file:${SURELOG_DIR}/tests/OneNetRange/dut.v, line:8:1, endln:9:13 + \_interface_inst: work@ConnectTB (work@ConnectTB), file:${SURELOG_DIR}/tests/OneNetRange/dut.v, line:8:1, endln:9:13 |vpiName:con_o |vpiDirection:2 |vpiLowConn: @@ -455,14 +455,14 @@ design: (work@TOP) |vpiActual: \_logic_net: (work@TESTBENCH.drive), line:1:98, endln:1:103 |uhdmallModules: -\_module: work@SUB (work@SUB), file:${SURELOG_DIR}/tests/OneNetRange/dut.v, line:15:1, endln:17:10 +\_module_inst: work@SUB (work@SUB), file:${SURELOG_DIR}/tests/OneNetRange/dut.v, line:15:1, endln:17:10 |vpiParent: \_design: (work@TOP) |vpiFullName:work@SUB |vpiParameter: \_parameter: (work@SUB.width), line:15:24, endln:15:29 |vpiParent: - \_module: work@SUB (work@SUB), file:${SURELOG_DIR}/tests/OneNetRange/dut.v, line:15:1, endln:17:10 + \_module_inst: work@SUB (work@SUB), file:${SURELOG_DIR}/tests/OneNetRange/dut.v, line:15:1, endln:17:10 |UINT:1 |vpiTypespec: \_int_typespec: @@ -471,7 +471,7 @@ design: (work@TOP) |vpiParamAssign: \_param_assign: , line:15:24, endln:15:33 |vpiParent: - \_module: work@SUB (work@SUB), file:${SURELOG_DIR}/tests/OneNetRange/dut.v, line:15:1, endln:17:10 + \_module_inst: work@SUB (work@SUB), file:${SURELOG_DIR}/tests/OneNetRange/dut.v, line:15:1, endln:17:10 |vpiRhs: \_constant: , line:15:32, endln:15:33 |vpiDecompile:1 @@ -486,21 +486,21 @@ design: (work@TOP) |vpiNet: \_logic_net: (work@SUB.inp), line:15:59, endln:15:62 |vpiParent: - \_module: work@SUB (work@SUB), file:${SURELOG_DIR}/tests/OneNetRange/dut.v, line:15:1, endln:17:10 + \_module_inst: work@SUB (work@SUB), file:${SURELOG_DIR}/tests/OneNetRange/dut.v, line:15:1, endln:17:10 |vpiName:inp |vpiFullName:work@SUB.inp |vpiNetType:1 |vpiNet: \_logic_net: (work@SUB.out), line:15:87, endln:15:90 |vpiParent: - \_module: work@SUB (work@SUB), file:${SURELOG_DIR}/tests/OneNetRange/dut.v, line:15:1, endln:17:10 + \_module_inst: work@SUB (work@SUB), file:${SURELOG_DIR}/tests/OneNetRange/dut.v, line:15:1, endln:17:10 |vpiName:out |vpiFullName:work@SUB.out |vpiNetType:48 |vpiPort: \_port: (inp), line:15:59, endln:15:62 |vpiParent: - \_module: work@SUB (work@SUB), file:${SURELOG_DIR}/tests/OneNetRange/dut.v, line:15:1, endln:17:10 + \_module_inst: work@SUB (work@SUB), file:${SURELOG_DIR}/tests/OneNetRange/dut.v, line:15:1, endln:17:10 |vpiName:inp |vpiDirection:1 |vpiLowConn: @@ -540,7 +540,7 @@ design: (work@TOP) |vpiPort: \_port: (out), line:15:87, endln:15:90 |vpiParent: - \_module: work@SUB (work@SUB), file:${SURELOG_DIR}/tests/OneNetRange/dut.v, line:15:1, endln:17:10 + \_module_inst: work@SUB (work@SUB), file:${SURELOG_DIR}/tests/OneNetRange/dut.v, line:15:1, endln:17:10 |vpiName:out |vpiDirection:2 |vpiLowConn: @@ -580,7 +580,7 @@ design: (work@TOP) |vpiContAssign: \_cont_assign: , line:16:10, endln:16:19 |vpiParent: - \_module: work@SUB (work@SUB), file:${SURELOG_DIR}/tests/OneNetRange/dut.v, line:15:1, endln:17:10 + \_module_inst: work@SUB (work@SUB), file:${SURELOG_DIR}/tests/OneNetRange/dut.v, line:15:1, endln:17:10 |vpiRhs: \_ref_obj: (work@SUB.inp), line:16:16, endln:16:19 |vpiParent: @@ -598,14 +598,14 @@ design: (work@TOP) |vpiActual: \_logic_net: (work@TOP.dut1.middle1.sub1.out), line:15:87, endln:15:90 |uhdmallModules: -\_module: work@TOP (work@TOP), file:${SURELOG_DIR}/tests/OneNetRange/tb.v, line:16:1, endln:23:10 +\_module_inst: work@TOP (work@TOP), file:${SURELOG_DIR}/tests/OneNetRange/tb.v, line:16:1, endln:23:10 |vpiParent: \_design: (work@TOP) |vpiFullName:work@TOP |vpiParameter: \_parameter: (work@TOP.width), line:17:13, endln:17:18 |vpiParent: - \_module: work@TOP (work@TOP), file:${SURELOG_DIR}/tests/OneNetRange/tb.v, line:16:1, endln:23:10 + \_module_inst: work@TOP (work@TOP), file:${SURELOG_DIR}/tests/OneNetRange/tb.v, line:16:1, endln:23:10 |UINT:16 |vpiTypespec: \_int_typespec: @@ -614,7 +614,7 @@ design: (work@TOP) |vpiParamAssign: \_param_assign: , line:17:13, endln:17:23 |vpiParent: - \_module: work@TOP (work@TOP), file:${SURELOG_DIR}/tests/OneNetRange/tb.v, line:16:1, endln:23:10 + \_module_inst: work@TOP (work@TOP), file:${SURELOG_DIR}/tests/OneNetRange/tb.v, line:16:1, endln:23:10 |vpiRhs: \_constant: , line:17:21, endln:17:23 |vpiDecompile:16 @@ -629,26 +629,26 @@ design: (work@TOP) |vpiNet: \_logic_net: (work@TOP.i), line:18:20, endln:18:21 |vpiParent: - \_module: work@TOP (work@TOP), file:${SURELOG_DIR}/tests/OneNetRange/tb.v, line:16:1, endln:23:10 + \_module_inst: work@TOP (work@TOP), file:${SURELOG_DIR}/tests/OneNetRange/tb.v, line:16:1, endln:23:10 |vpiName:i |vpiFullName:work@TOP.i |vpiNetType:1 |vpiNet: \_logic_net: (work@TOP.o), line:19:20, endln:19:21 |vpiParent: - \_module: work@TOP (work@TOP), file:${SURELOG_DIR}/tests/OneNetRange/tb.v, line:16:1, endln:23:10 + \_module_inst: work@TOP (work@TOP), file:${SURELOG_DIR}/tests/OneNetRange/tb.v, line:16:1, endln:23:10 |vpiName:o |vpiFullName:work@TOP.o |vpiNetType:1 |uhdmallModules: -\_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/OneNetRange/dut.v, line:2:1, endln:5:10 +\_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/OneNetRange/dut.v, line:2:1, endln:5:10 |vpiParent: \_design: (work@TOP) |vpiFullName:work@dut |vpiParameter: \_parameter: (work@dut.width), line:2:24, endln:2:29 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/OneNetRange/dut.v, line:2:1, endln:5:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/OneNetRange/dut.v, line:2:1, endln:5:10 |UINT:1 |vpiTypespec: \_int_typespec: @@ -657,7 +657,7 @@ design: (work@TOP) |vpiParamAssign: \_param_assign: , line:2:24, endln:2:33 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/OneNetRange/dut.v, line:2:1, endln:5:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/OneNetRange/dut.v, line:2:1, endln:5:10 |vpiRhs: \_constant: , line:2:32, endln:2:33 |vpiDecompile:1 @@ -672,21 +672,21 @@ design: (work@TOP) |vpiNet: \_logic_net: (work@dut.i), line:2:59, endln:2:60 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/OneNetRange/dut.v, line:2:1, endln:5:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/OneNetRange/dut.v, line:2:1, endln:5:10 |vpiName:i |vpiFullName:work@dut.i |vpiNetType:1 |vpiNet: \_logic_net: (work@dut.o), line:2:85, endln:2:86 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/OneNetRange/dut.v, line:2:1, endln:5:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/OneNetRange/dut.v, line:2:1, endln:5:10 |vpiName:o |vpiFullName:work@dut.o |vpiNetType:48 |vpiPort: \_port: (i), line:2:59, endln:2:60 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/OneNetRange/dut.v, line:2:1, endln:5:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/OneNetRange/dut.v, line:2:1, endln:5:10 |vpiName:i |vpiDirection:1 |vpiLowConn: @@ -726,7 +726,7 @@ design: (work@TOP) |vpiPort: \_port: (o), line:2:85, endln:2:86 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/OneNetRange/dut.v, line:2:1, endln:5:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/OneNetRange/dut.v, line:2:1, endln:5:10 |vpiName:o |vpiDirection:2 |vpiLowConn: @@ -764,14 +764,14 @@ design: (work@TOP) |UINT:0 |vpiConstType:9 |uhdmallModules: -\_module: work@middle (work@middle), file:${SURELOG_DIR}/tests/OneNetRange/dut.v, line:11:1, endln:13:10 +\_module_inst: work@middle (work@middle), file:${SURELOG_DIR}/tests/OneNetRange/dut.v, line:11:1, endln:13:10 |vpiParent: \_design: (work@TOP) |vpiFullName:work@middle |vpiParameter: \_parameter: (work@middle.width), line:11:27, endln:11:32 |vpiParent: - \_module: work@middle (work@middle), file:${SURELOG_DIR}/tests/OneNetRange/dut.v, line:11:1, endln:13:10 + \_module_inst: work@middle (work@middle), file:${SURELOG_DIR}/tests/OneNetRange/dut.v, line:11:1, endln:13:10 |UINT:1 |vpiTypespec: \_int_typespec: @@ -780,7 +780,7 @@ design: (work@TOP) |vpiParamAssign: \_param_assign: , line:11:27, endln:11:36 |vpiParent: - \_module: work@middle (work@middle), file:${SURELOG_DIR}/tests/OneNetRange/dut.v, line:11:1, endln:13:10 + \_module_inst: work@middle (work@middle), file:${SURELOG_DIR}/tests/OneNetRange/dut.v, line:11:1, endln:13:10 |vpiRhs: \_constant: , line:11:35, endln:11:36 |vpiDecompile:1 @@ -795,29 +795,29 @@ design: (work@TOP) |vpiNet: \_logic_net: (work@middle.conn), line:11:49, endln:11:53 |vpiParent: - \_module: work@middle (work@middle), file:${SURELOG_DIR}/tests/OneNetRange/dut.v, line:11:1, endln:13:10 + \_module_inst: work@middle (work@middle), file:${SURELOG_DIR}/tests/OneNetRange/dut.v, line:11:1, endln:13:10 |vpiName:conn |vpiFullName:work@middle.conn |vpiPort: \_port: (conn), line:11:49, endln:11:53 |vpiParent: - \_module: work@middle (work@middle), file:${SURELOG_DIR}/tests/OneNetRange/dut.v, line:11:1, endln:13:10 + \_module_inst: work@middle (work@middle), file:${SURELOG_DIR}/tests/OneNetRange/dut.v, line:11:1, endln:13:10 |vpiName:conn |vpiDirection:3 |vpiLowConn: \_ref_obj: |vpiActual: - \_interface: work@ConnectTB (work@ConnectTB), file:${SURELOG_DIR}/tests/OneNetRange/dut.v, line:8:1, endln:9:13 + \_interface_inst: work@ConnectTB (work@ConnectTB), file:${SURELOG_DIR}/tests/OneNetRange/dut.v, line:8:1, endln:9:13 |vpiTypedef: \_interface_typespec: (ConnectTB), line:11:39, endln:11:48 |vpiName:ConnectTB |uhdmtopModules: -\_module: work@TOP (work@TOP), file:${SURELOG_DIR}/tests/OneNetRange/tb.v, line:16:1, endln:23:10 +\_module_inst: work@TOP (work@TOP), file:${SURELOG_DIR}/tests/OneNetRange/tb.v, line:16:1, endln:23:10 |vpiName:work@TOP |vpiParameter: \_parameter: (work@TOP.width), line:17:13, endln:17:18 |vpiParent: - \_module: work@TOP (work@TOP), file:${SURELOG_DIR}/tests/OneNetRange/tb.v, line:16:1, endln:23:10 + \_module_inst: work@TOP (work@TOP), file:${SURELOG_DIR}/tests/OneNetRange/tb.v, line:16:1, endln:23:10 |UINT:16 |vpiTypespec: \_int_typespec: @@ -828,7 +828,7 @@ design: (work@TOP) |vpiParamAssign: \_param_assign: , line:17:13, endln:17:23 |vpiParent: - \_module: work@TOP (work@TOP), file:${SURELOG_DIR}/tests/OneNetRange/tb.v, line:16:1, endln:23:10 + \_module_inst: work@TOP (work@TOP), file:${SURELOG_DIR}/tests/OneNetRange/tb.v, line:16:1, endln:23:10 |vpiRhs: \_constant: , line:17:21, endln:17:23 |vpiDecompile:16 @@ -844,7 +844,7 @@ design: (work@TOP) |vpiProgram: \_program: work@TESTBENCH (work@TOP.tb), file:${SURELOG_DIR}/tests/OneNetRange/tb.v, line:22:3, endln:22:70 |vpiParent: - \_module: work@TOP (work@TOP), file:${SURELOG_DIR}/tests/OneNetRange/tb.v, line:16:1, endln:23:10 + \_module_inst: work@TOP (work@TOP), file:${SURELOG_DIR}/tests/OneNetRange/tb.v, line:16:1, endln:23:10 |vpiName:tb |vpiFullName:work@TOP.tb |vpiDefName:work@TESTBENCH @@ -905,7 +905,7 @@ design: (work@TOP) |vpiFullName:work@TOP.tb.drive |vpiNetType:48 |vpiInstance: - \_module: work@TOP (work@TOP), file:${SURELOG_DIR}/tests/OneNetRange/tb.v, line:16:1, endln:23:10 + \_module_inst: work@TOP (work@TOP), file:${SURELOG_DIR}/tests/OneNetRange/tb.v, line:16:1, endln:23:10 |vpiProcess: \_initial: , line:2:3, endln:12:6 |vpiPort: @@ -1001,7 +1001,7 @@ design: (work@TOP) |vpiNet: \_logic_net: (work@TOP.i), line:18:20, endln:18:21 |vpiParent: - \_module: work@TOP (work@TOP), file:${SURELOG_DIR}/tests/OneNetRange/tb.v, line:16:1, endln:23:10 + \_module_inst: work@TOP (work@TOP), file:${SURELOG_DIR}/tests/OneNetRange/tb.v, line:16:1, endln:23:10 |vpiTypespec: \_logic_typespec: , line:18:3, endln:18:19 |vpiRange: @@ -1028,7 +1028,7 @@ design: (work@TOP) |vpiNet: \_logic_net: (work@TOP.o), line:19:20, endln:19:21 |vpiParent: - \_module: work@TOP (work@TOP), file:${SURELOG_DIR}/tests/OneNetRange/tb.v, line:16:1, endln:23:10 + \_module_inst: work@TOP (work@TOP), file:${SURELOG_DIR}/tests/OneNetRange/tb.v, line:16:1, endln:23:10 |vpiTypespec: \_logic_typespec: , line:19:3, endln:19:19 |vpiRange: @@ -1053,16 +1053,16 @@ design: (work@TOP) |vpiFullName:work@TOP.o |vpiNetType:1 |vpiTopModule:1 - |vpiInterface: - \_interface: work@ConnectTB (work@TOP.conntb), file:${SURELOG_DIR}/tests/OneNetRange/tb.v, line:20:3, endln:20:50 + |vpiInterfaceInst: + \_interface_inst: work@ConnectTB (work@TOP.conntb), file:${SURELOG_DIR}/tests/OneNetRange/tb.v, line:20:3, endln:20:50 |vpiParent: - \_module: work@TOP (work@TOP), file:${SURELOG_DIR}/tests/OneNetRange/tb.v, line:16:1, endln:23:10 + \_module_inst: work@TOP (work@TOP), file:${SURELOG_DIR}/tests/OneNetRange/tb.v, line:16:1, endln:23:10 |vpiName:conntb |vpiFullName:work@TOP.conntb |vpiParameter: \_parameter: (work@TOP.conntb.width), line:8:33, endln:8:38 |vpiParent: - \_interface: work@ConnectTB (work@TOP.conntb), file:${SURELOG_DIR}/tests/OneNetRange/tb.v, line:20:3, endln:20:50 + \_interface_inst: work@ConnectTB (work@TOP.conntb), file:${SURELOG_DIR}/tests/OneNetRange/tb.v, line:20:3, endln:20:50 |UINT:1 |vpiTypespec: \_int_typespec: @@ -1073,7 +1073,7 @@ design: (work@TOP) |vpiParamAssign: \_param_assign: , line:8:33, endln:8:42 |vpiParent: - \_interface: work@ConnectTB (work@TOP.conntb), file:${SURELOG_DIR}/tests/OneNetRange/tb.v, line:20:3, endln:20:50 + \_interface_inst: work@ConnectTB (work@TOP.conntb), file:${SURELOG_DIR}/tests/OneNetRange/tb.v, line:20:3, endln:20:50 |vpiOverriden:1 |vpiRhs: \_constant: , line:8:41, endln:8:42 @@ -1091,7 +1091,7 @@ design: (work@TOP) |vpiNet: \_logic_net: (work@TOP.conntb.con_i), line:8:68, endln:8:73 |vpiParent: - \_interface: work@ConnectTB (work@TOP.conntb), file:${SURELOG_DIR}/tests/OneNetRange/tb.v, line:20:3, endln:20:50 + \_interface_inst: work@ConnectTB (work@TOP.conntb), file:${SURELOG_DIR}/tests/OneNetRange/tb.v, line:20:3, endln:20:50 |vpiTypespec: \_logic_typespec: , line:8:51, endln:8:67 |vpiRange: @@ -1118,7 +1118,7 @@ design: (work@TOP) |vpiNet: \_logic_net: (work@TOP.conntb.con_o), line:8:98, endln:8:103 |vpiParent: - \_interface: work@ConnectTB (work@TOP.conntb), file:${SURELOG_DIR}/tests/OneNetRange/tb.v, line:20:3, endln:20:50 + \_interface_inst: work@ConnectTB (work@TOP.conntb), file:${SURELOG_DIR}/tests/OneNetRange/tb.v, line:20:3, endln:20:50 |vpiTypespec: \_logic_typespec: , line:8:82, endln:8:97 |vpiRange: @@ -1143,11 +1143,11 @@ design: (work@TOP) |vpiFullName:work@TOP.conntb.con_o |vpiNetType:48 |vpiInstance: - \_module: work@TOP (work@TOP), file:${SURELOG_DIR}/tests/OneNetRange/tb.v, line:16:1, endln:23:10 + \_module_inst: work@TOP (work@TOP), file:${SURELOG_DIR}/tests/OneNetRange/tb.v, line:16:1, endln:23:10 |vpiPort: \_port: (con_i), line:8:68, endln:8:73 |vpiParent: - \_interface: work@ConnectTB (work@TOP.conntb), file:${SURELOG_DIR}/tests/OneNetRange/tb.v, line:20:3, endln:20:50 + \_interface_inst: work@ConnectTB (work@TOP.conntb), file:${SURELOG_DIR}/tests/OneNetRange/tb.v, line:20:3, endln:20:50 |vpiName:con_i |vpiDirection:1 |vpiHighConn: @@ -1187,7 +1187,7 @@ design: (work@TOP) |vpiPort: \_port: (con_o), line:8:98, endln:8:103 |vpiParent: - \_interface: work@ConnectTB (work@TOP.conntb), file:${SURELOG_DIR}/tests/OneNetRange/tb.v, line:20:3, endln:20:50 + \_interface_inst: work@ConnectTB (work@TOP.conntb), file:${SURELOG_DIR}/tests/OneNetRange/tb.v, line:20:3, endln:20:50 |vpiName:con_o |vpiDirection:2 |vpiHighConn: @@ -1224,16 +1224,16 @@ design: (work@TOP) |vpiSize:64 |UINT:0 |vpiConstType:9 - |vpiModule: - \_module: work@dut (work@TOP.dut1), file:${SURELOG_DIR}/tests/OneNetRange/tb.v, line:21:3, endln:21:57 + |vpiModuleInst: + \_module_inst: work@dut (work@TOP.dut1), file:${SURELOG_DIR}/tests/OneNetRange/tb.v, line:21:3, endln:21:57 |vpiParent: - \_module: work@TOP (work@TOP), file:${SURELOG_DIR}/tests/OneNetRange/tb.v, line:16:1, endln:23:10 + \_module_inst: work@TOP (work@TOP), file:${SURELOG_DIR}/tests/OneNetRange/tb.v, line:16:1, endln:23:10 |vpiName:dut1 |vpiFullName:work@TOP.dut1 |vpiParameter: \_parameter: (work@TOP.dut1.width), line:2:24, endln:2:29 |vpiParent: - \_module: work@dut (work@TOP.dut1), file:${SURELOG_DIR}/tests/OneNetRange/tb.v, line:21:3, endln:21:57 + \_module_inst: work@dut (work@TOP.dut1), file:${SURELOG_DIR}/tests/OneNetRange/tb.v, line:21:3, endln:21:57 |UINT:1 |vpiTypespec: \_int_typespec: @@ -1244,7 +1244,7 @@ design: (work@TOP) |vpiParamAssign: \_param_assign: , line:2:24, endln:2:33 |vpiParent: - \_module: work@dut (work@TOP.dut1), file:${SURELOG_DIR}/tests/OneNetRange/tb.v, line:21:3, endln:21:57 + \_module_inst: work@dut (work@TOP.dut1), file:${SURELOG_DIR}/tests/OneNetRange/tb.v, line:21:3, endln:21:57 |vpiOverriden:1 |vpiRhs: \_constant: , line:2:32, endln:2:33 @@ -1262,7 +1262,7 @@ design: (work@TOP) |vpiNet: \_logic_net: (work@TOP.dut1.i), line:2:59, endln:2:60 |vpiParent: - \_module: work@dut (work@TOP.dut1), file:${SURELOG_DIR}/tests/OneNetRange/tb.v, line:21:3, endln:21:57 + \_module_inst: work@dut (work@TOP.dut1), file:${SURELOG_DIR}/tests/OneNetRange/tb.v, line:21:3, endln:21:57 |vpiTypespec: \_logic_typespec: , line:2:42, endln:2:58 |vpiRange: @@ -1289,7 +1289,7 @@ design: (work@TOP) |vpiNet: \_logic_net: (work@TOP.dut1.o), line:2:85, endln:2:86 |vpiParent: - \_module: work@dut (work@TOP.dut1), file:${SURELOG_DIR}/tests/OneNetRange/tb.v, line:21:3, endln:21:57 + \_module_inst: work@dut (work@TOP.dut1), file:${SURELOG_DIR}/tests/OneNetRange/tb.v, line:21:3, endln:21:57 |vpiTypespec: \_logic_typespec: , line:2:69, endln:2:84 |vpiRange: @@ -1314,11 +1314,11 @@ design: (work@TOP) |vpiFullName:work@TOP.dut1.o |vpiNetType:48 |vpiInstance: - \_module: work@TOP (work@TOP), file:${SURELOG_DIR}/tests/OneNetRange/tb.v, line:16:1, endln:23:10 + \_module_inst: work@TOP (work@TOP), file:${SURELOG_DIR}/tests/OneNetRange/tb.v, line:16:1, endln:23:10 |vpiPort: \_port: (i), line:2:59, endln:2:60 |vpiParent: - \_module: work@dut (work@TOP.dut1), file:${SURELOG_DIR}/tests/OneNetRange/tb.v, line:21:3, endln:21:57 + \_module_inst: work@dut (work@TOP.dut1), file:${SURELOG_DIR}/tests/OneNetRange/tb.v, line:21:3, endln:21:57 |vpiName:i |vpiDirection:1 |vpiHighConn: @@ -1363,7 +1363,7 @@ design: (work@TOP) |vpiPort: \_port: (o), line:2:85, endln:2:86 |vpiParent: - \_module: work@dut (work@TOP.dut1), file:${SURELOG_DIR}/tests/OneNetRange/tb.v, line:21:3, endln:21:57 + \_module_inst: work@dut (work@TOP.dut1), file:${SURELOG_DIR}/tests/OneNetRange/tb.v, line:21:3, endln:21:57 |vpiName:o |vpiDirection:2 |vpiHighConn: @@ -1405,16 +1405,16 @@ design: (work@TOP) |vpiSize:64 |UINT:0 |vpiConstType:9 - |vpiInterface: - \_interface: work@ConnectTB (work@TOP.dut1.conntb), file:${SURELOG_DIR}/tests/OneNetRange/dut.v, line:3:3, endln:3:58 + |vpiInterfaceInst: + \_interface_inst: work@ConnectTB (work@TOP.dut1.conntb), file:${SURELOG_DIR}/tests/OneNetRange/dut.v, line:3:3, endln:3:58 |vpiParent: - \_module: work@dut (work@TOP.dut1), file:${SURELOG_DIR}/tests/OneNetRange/tb.v, line:21:3, endln:21:57 + \_module_inst: work@dut (work@TOP.dut1), file:${SURELOG_DIR}/tests/OneNetRange/tb.v, line:21:3, endln:21:57 |vpiName:conntb |vpiFullName:work@TOP.dut1.conntb |vpiParameter: \_parameter: (work@TOP.dut1.conntb.width), line:8:33, endln:8:38 |vpiParent: - \_interface: work@ConnectTB (work@TOP.dut1.conntb), file:${SURELOG_DIR}/tests/OneNetRange/dut.v, line:3:3, endln:3:58 + \_interface_inst: work@ConnectTB (work@TOP.dut1.conntb), file:${SURELOG_DIR}/tests/OneNetRange/dut.v, line:3:3, endln:3:58 |UINT:1 |vpiTypespec: \_int_typespec: @@ -1425,7 +1425,7 @@ design: (work@TOP) |vpiParamAssign: \_param_assign: , line:8:33, endln:8:42 |vpiParent: - \_interface: work@ConnectTB (work@TOP.dut1.conntb), file:${SURELOG_DIR}/tests/OneNetRange/dut.v, line:3:3, endln:3:58 + \_interface_inst: work@ConnectTB (work@TOP.dut1.conntb), file:${SURELOG_DIR}/tests/OneNetRange/dut.v, line:3:3, endln:3:58 |vpiOverriden:1 |vpiRhs: \_constant: , line:8:41, endln:8:42 @@ -1443,7 +1443,7 @@ design: (work@TOP) |vpiNet: \_logic_net: (work@TOP.dut1.conntb.con_i), line:8:68, endln:8:73 |vpiParent: - \_interface: work@ConnectTB (work@TOP.dut1.conntb), file:${SURELOG_DIR}/tests/OneNetRange/dut.v, line:3:3, endln:3:58 + \_interface_inst: work@ConnectTB (work@TOP.dut1.conntb), file:${SURELOG_DIR}/tests/OneNetRange/dut.v, line:3:3, endln:3:58 |vpiTypespec: \_logic_typespec: , line:8:51, endln:8:67 |vpiRange: @@ -1470,7 +1470,7 @@ design: (work@TOP) |vpiNet: \_logic_net: (work@TOP.dut1.conntb.con_o), line:8:98, endln:8:103 |vpiParent: - \_interface: work@ConnectTB (work@TOP.dut1.conntb), file:${SURELOG_DIR}/tests/OneNetRange/dut.v, line:3:3, endln:3:58 + \_interface_inst: work@ConnectTB (work@TOP.dut1.conntb), file:${SURELOG_DIR}/tests/OneNetRange/dut.v, line:3:3, endln:3:58 |vpiTypespec: \_logic_typespec: , line:8:82, endln:8:97 |vpiRange: @@ -1495,11 +1495,11 @@ design: (work@TOP) |vpiFullName:work@TOP.dut1.conntb.con_o |vpiNetType:48 |vpiInstance: - \_module: work@dut (work@TOP.dut1), file:${SURELOG_DIR}/tests/OneNetRange/tb.v, line:21:3, endln:21:57 + \_module_inst: work@dut (work@TOP.dut1), file:${SURELOG_DIR}/tests/OneNetRange/tb.v, line:21:3, endln:21:57 |vpiPort: \_port: (con_i), line:8:68, endln:8:73 |vpiParent: - \_interface: work@ConnectTB (work@TOP.dut1.conntb), file:${SURELOG_DIR}/tests/OneNetRange/dut.v, line:3:3, endln:3:58 + \_interface_inst: work@ConnectTB (work@TOP.dut1.conntb), file:${SURELOG_DIR}/tests/OneNetRange/dut.v, line:3:3, endln:3:58 |vpiName:con_i |vpiDirection:1 |vpiHighConn: @@ -1539,7 +1539,7 @@ design: (work@TOP) |vpiPort: \_port: (con_o), line:8:98, endln:8:103 |vpiParent: - \_interface: work@ConnectTB (work@TOP.dut1.conntb), file:${SURELOG_DIR}/tests/OneNetRange/dut.v, line:3:3, endln:3:58 + \_interface_inst: work@ConnectTB (work@TOP.dut1.conntb), file:${SURELOG_DIR}/tests/OneNetRange/dut.v, line:3:3, endln:3:58 |vpiName:con_o |vpiDirection:2 |vpiHighConn: @@ -1576,16 +1576,16 @@ design: (work@TOP) |vpiSize:64 |UINT:0 |vpiConstType:9 - |vpiModule: - \_module: work@middle (work@TOP.dut1.middle1), file:${SURELOG_DIR}/tests/OneNetRange/dut.v, line:4:3, endln:4:43 + |vpiModuleInst: + \_module_inst: work@middle (work@TOP.dut1.middle1), file:${SURELOG_DIR}/tests/OneNetRange/dut.v, line:4:3, endln:4:43 |vpiParent: - \_module: work@dut (work@TOP.dut1), file:${SURELOG_DIR}/tests/OneNetRange/tb.v, line:21:3, endln:21:57 + \_module_inst: work@dut (work@TOP.dut1), file:${SURELOG_DIR}/tests/OneNetRange/tb.v, line:21:3, endln:21:57 |vpiName:middle1 |vpiFullName:work@TOP.dut1.middle1 |vpiParameter: \_parameter: (work@TOP.dut1.middle1.width), line:11:27, endln:11:32 |vpiParent: - \_module: work@middle (work@TOP.dut1.middle1), file:${SURELOG_DIR}/tests/OneNetRange/dut.v, line:4:3, endln:4:43 + \_module_inst: work@middle (work@TOP.dut1.middle1), file:${SURELOG_DIR}/tests/OneNetRange/dut.v, line:4:3, endln:4:43 |UINT:1 |vpiTypespec: \_int_typespec: @@ -1596,7 +1596,7 @@ design: (work@TOP) |vpiParamAssign: \_param_assign: , line:11:27, endln:11:36 |vpiParent: - \_module: work@middle (work@TOP.dut1.middle1), file:${SURELOG_DIR}/tests/OneNetRange/dut.v, line:4:3, endln:4:43 + \_module_inst: work@middle (work@TOP.dut1.middle1), file:${SURELOG_DIR}/tests/OneNetRange/dut.v, line:4:3, endln:4:43 |vpiOverriden:1 |vpiRhs: \_constant: , line:11:35, endln:11:36 @@ -1612,11 +1612,11 @@ design: (work@TOP) |vpiDefFile:${SURELOG_DIR}/tests/OneNetRange/dut.v |vpiDefLineNo:11 |vpiInstance: - \_module: work@dut (work@TOP.dut1), file:${SURELOG_DIR}/tests/OneNetRange/tb.v, line:21:3, endln:21:57 + \_module_inst: work@dut (work@TOP.dut1), file:${SURELOG_DIR}/tests/OneNetRange/tb.v, line:21:3, endln:21:57 |vpiPort: \_port: (conn), line:11:49, endln:11:53 |vpiParent: - \_module: work@middle (work@TOP.dut1.middle1), file:${SURELOG_DIR}/tests/OneNetRange/dut.v, line:4:3, endln:4:43 + \_module_inst: work@middle (work@TOP.dut1.middle1), file:${SURELOG_DIR}/tests/OneNetRange/dut.v, line:4:3, endln:4:43 |vpiName:conn |vpiDirection:3 |vpiHighConn: @@ -1624,34 +1624,34 @@ design: (work@TOP) |vpiName:conntb |vpiFullName:work@TOP.dut1.conntb |vpiActual: - \_interface: work@ConnectTB (work@TOP.dut1.conntb), file:${SURELOG_DIR}/tests/OneNetRange/dut.v, line:3:0 + \_interface_inst: work@ConnectTB (work@TOP.dut1.conntb), file:${SURELOG_DIR}/tests/OneNetRange/dut.v, line:3:0 |vpiLowConn: \_ref_obj: (work@TOP.dut1.middle1.conn), line:4:35, endln:4:41 |vpiFullName:work@TOP.dut1.middle1.conn |vpiActual: - \_interface: work@ConnectTB (work@TOP.dut1.middle1.conn), file:${SURELOG_DIR}/tests/OneNetRange/dut.v, line:4:0 + \_interface_inst: work@ConnectTB (work@TOP.dut1.middle1.conn), file:${SURELOG_DIR}/tests/OneNetRange/dut.v, line:4:0 |vpiTypedef: \_interface_typespec: (ConnectTB), line:11:39, endln:11:48 |vpiName:ConnectTB - |vpiInterface: - \_interface: work@ConnectTB (work@TOP.dut1.middle1.conn), file:${SURELOG_DIR}/tests/OneNetRange/dut.v, line:4:0 + |vpiInterfaceInst: + \_interface_inst: work@ConnectTB (work@TOP.dut1.middle1.conn), file:${SURELOG_DIR}/tests/OneNetRange/dut.v, line:4:0 |vpiParent: - \_module: work@middle (work@TOP.dut1.middle1), file:${SURELOG_DIR}/tests/OneNetRange/dut.v, line:4:3, endln:4:43 + \_module_inst: work@middle (work@TOP.dut1.middle1), file:${SURELOG_DIR}/tests/OneNetRange/dut.v, line:4:3, endln:4:43 |vpiName:conn |vpiFullName:work@TOP.dut1.middle1.conn |vpiDefName:work@ConnectTB - |vpiInterface: - \_interface: work@ConnectTB (work@TOP.dut1.middle1.conn), file:${SURELOG_DIR}/tests/OneNetRange/dut.v, line:4:0 - |vpiModule: - \_module: work@SUB (work@TOP.dut1.middle1.sub1), file:${SURELOG_DIR}/tests/OneNetRange/dut.v, line:12:3, endln:12:64 + |vpiInterfaceInst: + \_interface_inst: work@ConnectTB (work@TOP.dut1.middle1.conn), file:${SURELOG_DIR}/tests/OneNetRange/dut.v, line:4:0 + |vpiModuleInst: + \_module_inst: work@SUB (work@TOP.dut1.middle1.sub1), file:${SURELOG_DIR}/tests/OneNetRange/dut.v, line:12:3, endln:12:64 |vpiParent: - \_module: work@middle (work@TOP.dut1.middle1), file:${SURELOG_DIR}/tests/OneNetRange/dut.v, line:4:3, endln:4:43 + \_module_inst: work@middle (work@TOP.dut1.middle1), file:${SURELOG_DIR}/tests/OneNetRange/dut.v, line:4:3, endln:4:43 |vpiName:sub1 |vpiFullName:work@TOP.dut1.middle1.sub1 |vpiParameter: \_parameter: (work@TOP.dut1.middle1.sub1.width), line:15:24, endln:15:29 |vpiParent: - \_module: work@SUB (work@TOP.dut1.middle1.sub1), file:${SURELOG_DIR}/tests/OneNetRange/dut.v, line:12:3, endln:12:64 + \_module_inst: work@SUB (work@TOP.dut1.middle1.sub1), file:${SURELOG_DIR}/tests/OneNetRange/dut.v, line:12:3, endln:12:64 |UINT:1 |vpiTypespec: \_int_typespec: @@ -1662,7 +1662,7 @@ design: (work@TOP) |vpiParamAssign: \_param_assign: , line:15:24, endln:15:33 |vpiParent: - \_module: work@SUB (work@TOP.dut1.middle1.sub1), file:${SURELOG_DIR}/tests/OneNetRange/dut.v, line:12:3, endln:12:64 + \_module_inst: work@SUB (work@TOP.dut1.middle1.sub1), file:${SURELOG_DIR}/tests/OneNetRange/dut.v, line:12:3, endln:12:64 |vpiOverriden:1 |vpiRhs: \_constant: , line:15:32, endln:15:33 @@ -1680,7 +1680,7 @@ design: (work@TOP) |vpiNet: \_logic_net: (work@TOP.dut1.middle1.sub1.inp), line:15:59, endln:15:62 |vpiParent: - \_module: work@SUB (work@TOP.dut1.middle1.sub1), file:${SURELOG_DIR}/tests/OneNetRange/dut.v, line:12:3, endln:12:64 + \_module_inst: work@SUB (work@TOP.dut1.middle1.sub1), file:${SURELOG_DIR}/tests/OneNetRange/dut.v, line:12:3, endln:12:64 |vpiTypespec: \_logic_typespec: , line:15:42, endln:15:58 |vpiRange: @@ -1707,7 +1707,7 @@ design: (work@TOP) |vpiNet: \_logic_net: (work@TOP.dut1.middle1.sub1.out), line:15:87, endln:15:90 |vpiParent: - \_module: work@SUB (work@TOP.dut1.middle1.sub1), file:${SURELOG_DIR}/tests/OneNetRange/dut.v, line:12:3, endln:12:64 + \_module_inst: work@SUB (work@TOP.dut1.middle1.sub1), file:${SURELOG_DIR}/tests/OneNetRange/dut.v, line:12:3, endln:12:64 |vpiTypespec: \_logic_typespec: , line:15:71, endln:15:86 |vpiRange: @@ -1732,11 +1732,11 @@ design: (work@TOP) |vpiFullName:work@TOP.dut1.middle1.sub1.out |vpiNetType:48 |vpiInstance: - \_module: work@middle (work@TOP.dut1.middle1), file:${SURELOG_DIR}/tests/OneNetRange/dut.v, line:4:3, endln:4:43 + \_module_inst: work@middle (work@TOP.dut1.middle1), file:${SURELOG_DIR}/tests/OneNetRange/dut.v, line:4:3, endln:4:43 |vpiPort: \_port: (inp), line:15:59, endln:15:62 |vpiParent: - \_module: work@SUB (work@TOP.dut1.middle1.sub1), file:${SURELOG_DIR}/tests/OneNetRange/dut.v, line:12:3, endln:12:64 + \_module_inst: work@SUB (work@TOP.dut1.middle1.sub1), file:${SURELOG_DIR}/tests/OneNetRange/dut.v, line:12:3, endln:12:64 |vpiName:inp |vpiDirection:1 |vpiHighConn: @@ -1785,7 +1785,7 @@ design: (work@TOP) |vpiPort: \_port: (out), line:15:87, endln:15:90 |vpiParent: - \_module: work@SUB (work@TOP.dut1.middle1.sub1), file:${SURELOG_DIR}/tests/OneNetRange/dut.v, line:12:3, endln:12:64 + \_module_inst: work@SUB (work@TOP.dut1.middle1.sub1), file:${SURELOG_DIR}/tests/OneNetRange/dut.v, line:12:3, endln:12:64 |vpiName:out |vpiDirection:2 |vpiHighConn: diff --git a/tests/PAssignType/PAssignType.log b/tests/PAssignType/PAssignType.log index 5fdd93985b..c7f3510149 100644 --- a/tests/PAssignType/PAssignType.log +++ b/tests/PAssignType/PAssignType.log @@ -224,7 +224,7 @@ design 1 import_typespec 1 logic_net 1 logic_typespec 21 -module 14 +module_inst 14 operation 15 package 3 param_assign 10 @@ -244,7 +244,7 @@ design 1 import_typespec 1 logic_net 1 logic_typespec 21 -module 14 +module_inst 14 operation 15 package 3 param_assign 10 @@ -360,7 +360,7 @@ design: (work@aes_core) |vpiTypespec: \_struct_typespec: (aes_pkg::ctrl_reg_t), line:2:9, endln:2:15 |vpiParent: - \_module: work@aes_core (work@aes_core), file:${SURELOG_DIR}/tests/PAssignType/dut.sv, line:22:1, endln:26:10 + \_module_inst: work@aes_core (work@aes_core), file:${SURELOG_DIR}/tests/PAssignType/dut.sv, line:22:1, endln:26:10 |vpiName:aes_pkg::ctrl_reg_t |vpiInstance: \_package: aes_pkg (aes_pkg::), file:${SURELOG_DIR}/tests/PAssignType/dut.sv, line:1:1, endln:9:11 @@ -428,14 +428,14 @@ design: (work@aes_core) |vpiDefName:aes_pkg |vpiTop:1 |uhdmallModules: -\_module: work@aes_core (work@aes_core), file:${SURELOG_DIR}/tests/PAssignType/dut.sv, line:22:1, endln:26:10 +\_module_inst: work@aes_core (work@aes_core), file:${SURELOG_DIR}/tests/PAssignType/dut.sv, line:22:1, endln:26:10 |vpiParent: \_design: (work@aes_core) |vpiFullName:work@aes_core |vpiParameter: \_parameter: (work@aes_core.CTRL_RESET), line:6:22, endln:6:32 |vpiParent: - \_module: work@aes_core (work@aes_core), file:${SURELOG_DIR}/tests/PAssignType/dut.sv, line:22:1, endln:26:10 + \_module_inst: work@aes_core (work@aes_core), file:${SURELOG_DIR}/tests/PAssignType/dut.sv, line:22:1, endln:26:10 |vpiTypespec: \_struct_typespec: (aes_pkg::ctrl_reg_t), line:2:9, endln:2:15 |vpiParent: @@ -486,7 +486,7 @@ design: (work@aes_core) |vpiParamAssign: \_param_assign: , line:6:22, endln:8:2 |vpiParent: - \_module: work@aes_core (work@aes_core), file:${SURELOG_DIR}/tests/PAssignType/dut.sv, line:22:1, endln:26:10 + \_module_inst: work@aes_core (work@aes_core), file:${SURELOG_DIR}/tests/PAssignType/dut.sv, line:22:1, endln:26:10 |vpiRhs: \_operation: , line:6:35, endln:8:2 |vpiParent: @@ -568,18 +568,18 @@ design: (work@aes_core) |vpiNet: \_logic_net: (work@aes_core.ctrl_q), line:24:14, endln:24:20 |vpiParent: - \_module: work@aes_core (work@aes_core), file:${SURELOG_DIR}/tests/PAssignType/dut.sv, line:22:1, endln:26:10 + \_module_inst: work@aes_core (work@aes_core), file:${SURELOG_DIR}/tests/PAssignType/dut.sv, line:22:1, endln:26:10 |vpiName:ctrl_q |vpiFullName:work@aes_core.ctrl_q |uhdmallModules: -\_module: work@shadow (work@shadow), file:${SURELOG_DIR}/tests/PAssignType/dut.sv, line:16:1, endln:20:10 +\_module_inst: work@shadow (work@shadow), file:${SURELOG_DIR}/tests/PAssignType/dut.sv, line:16:1, endln:20:10 |vpiParent: \_design: (work@aes_core) |vpiFullName:work@shadow |vpiParameter: \_parameter: (work@shadow.RESVAL), line:17:26, endln:17:32 |vpiParent: - \_module: work@shadow (work@shadow), file:${SURELOG_DIR}/tests/PAssignType/dut.sv, line:16:1, endln:20:10 + \_module_inst: work@shadow (work@shadow), file:${SURELOG_DIR}/tests/PAssignType/dut.sv, line:16:1, endln:20:10 |BIN:0 |vpiTypespec: \_logic_typespec: , line:17:13, endln:17:25 @@ -608,7 +608,7 @@ design: (work@aes_core) |vpiParamAssign: \_param_assign: , line:17:26, endln:17:37 |vpiParent: - \_module: work@shadow (work@shadow), file:${SURELOG_DIR}/tests/PAssignType/dut.sv, line:16:1, endln:20:10 + \_module_inst: work@shadow (work@shadow), file:${SURELOG_DIR}/tests/PAssignType/dut.sv, line:16:1, endln:20:10 |vpiRhs: \_constant: , line:17:35, endln:17:37 |vpiDecompile:'0 @@ -621,14 +621,14 @@ design: (work@aes_core) \_parameter: (work@shadow.RESVAL), line:17:26, endln:17:32 |vpiDefName:work@shadow |uhdmallModules: -\_module: work@subreg (work@subreg), file:${SURELOG_DIR}/tests/PAssignType/dut.sv, line:11:1, endln:14:10 +\_module_inst: work@subreg (work@subreg), file:${SURELOG_DIR}/tests/PAssignType/dut.sv, line:11:1, endln:14:10 |vpiParent: \_design: (work@aes_core) |vpiFullName:work@subreg |vpiParameter: \_parameter: (work@subreg.RESVAL), line:12:26, endln:12:32 |vpiParent: - \_module: work@subreg (work@subreg), file:${SURELOG_DIR}/tests/PAssignType/dut.sv, line:11:1, endln:14:10 + \_module_inst: work@subreg (work@subreg), file:${SURELOG_DIR}/tests/PAssignType/dut.sv, line:11:1, endln:14:10 |BIN:0 |vpiTypespec: \_logic_typespec: , line:12:13, endln:12:25 @@ -657,7 +657,7 @@ design: (work@aes_core) |vpiParamAssign: \_param_assign: , line:12:26, endln:12:37 |vpiParent: - \_module: work@subreg (work@subreg), file:${SURELOG_DIR}/tests/PAssignType/dut.sv, line:11:1, endln:14:10 + \_module_inst: work@subreg (work@subreg), file:${SURELOG_DIR}/tests/PAssignType/dut.sv, line:11:1, endln:14:10 |vpiRhs: \_constant: , line:12:35, endln:12:37 |vpiDecompile:'0 @@ -670,12 +670,12 @@ design: (work@aes_core) \_parameter: (work@subreg.RESVAL), line:12:26, endln:12:32 |vpiDefName:work@subreg |uhdmtopModules: -\_module: work@aes_core (work@aes_core), file:${SURELOG_DIR}/tests/PAssignType/dut.sv, line:22:1, endln:26:10 +\_module_inst: work@aes_core (work@aes_core), file:${SURELOG_DIR}/tests/PAssignType/dut.sv, line:22:1, endln:26:10 |vpiName:work@aes_core |vpiParameter: \_parameter: (work@aes_core.CTRL_RESET), line:6:22, endln:6:32 |vpiParent: - \_module: work@aes_core (work@aes_core), file:${SURELOG_DIR}/tests/PAssignType/dut.sv, line:22:1, endln:26:10 + \_module_inst: work@aes_core (work@aes_core), file:${SURELOG_DIR}/tests/PAssignType/dut.sv, line:22:1, endln:26:10 |vpiTypespec: \_struct_typespec: (aes_pkg::ctrl_reg_t), line:2:9, endln:2:15 |vpiParent: @@ -726,7 +726,7 @@ design: (work@aes_core) |vpiParamAssign: \_param_assign: , line:6:22, endln:8:2 |vpiParent: - \_module: work@aes_core (work@aes_core), file:${SURELOG_DIR}/tests/PAssignType/dut.sv, line:22:1, endln:26:10 + \_module_inst: work@aes_core (work@aes_core), file:${SURELOG_DIR}/tests/PAssignType/dut.sv, line:22:1, endln:26:10 |vpiRhs: \_operation: , line:6:35, endln:8:2 |vpiParent: @@ -795,22 +795,22 @@ design: (work@aes_core) |vpiNet: \_struct_net: (work@aes_core.ctrl_q), line:24:14, endln:24:20 |vpiParent: - \_module: work@aes_core (work@aes_core), file:${SURELOG_DIR}/tests/PAssignType/dut.sv, line:22:1, endln:26:10 + \_module_inst: work@aes_core (work@aes_core), file:${SURELOG_DIR}/tests/PAssignType/dut.sv, line:22:1, endln:26:10 |vpiTypespec: \_struct_typespec: (aes_pkg::ctrl_reg_t), line:2:9, endln:2:15 |vpiName:ctrl_q |vpiFullName:work@aes_core.ctrl_q |vpiTopModule:1 - |vpiModule: - \_module: work@shadow (work@aes_core.shadow_reg), file:${SURELOG_DIR}/tests/PAssignType/dut.sv, line:25:3, endln:25:46 + |vpiModuleInst: + \_module_inst: work@shadow (work@aes_core.shadow_reg), file:${SURELOG_DIR}/tests/PAssignType/dut.sv, line:25:3, endln:25:46 |vpiParent: - \_module: work@aes_core (work@aes_core), file:${SURELOG_DIR}/tests/PAssignType/dut.sv, line:22:1, endln:26:10 + \_module_inst: work@aes_core (work@aes_core), file:${SURELOG_DIR}/tests/PAssignType/dut.sv, line:22:1, endln:26:10 |vpiName:shadow_reg |vpiFullName:work@aes_core.shadow_reg |vpiParameter: \_parameter: (work@aes_core.shadow_reg.RESVAL), line:17:26, endln:17:32 |vpiParent: - \_module: work@shadow (work@aes_core.shadow_reg), file:${SURELOG_DIR}/tests/PAssignType/dut.sv, line:25:3, endln:25:46 + \_module_inst: work@shadow (work@aes_core.shadow_reg), file:${SURELOG_DIR}/tests/PAssignType/dut.sv, line:25:3, endln:25:46 |BIN:0 |vpiTypespec: \_logic_typespec: , line:17:13, endln:17:25 @@ -841,7 +841,7 @@ design: (work@aes_core) |vpiParamAssign: \_param_assign: , line:17:26, endln:17:37 |vpiParent: - \_module: work@shadow (work@aes_core.shadow_reg), file:${SURELOG_DIR}/tests/PAssignType/dut.sv, line:25:3, endln:25:46 + \_module_inst: work@shadow (work@aes_core.shadow_reg), file:${SURELOG_DIR}/tests/PAssignType/dut.sv, line:25:3, endln:25:46 |vpiOverriden:1 |vpiRhs: \_constant: , line:25:20, endln:25:30 @@ -854,17 +854,17 @@ design: (work@aes_core) |vpiDefFile:${SURELOG_DIR}/tests/PAssignType/dut.sv |vpiDefLineNo:16 |vpiInstance: - \_module: work@aes_core (work@aes_core), file:${SURELOG_DIR}/tests/PAssignType/dut.sv, line:22:1, endln:26:10 - |vpiModule: - \_module: work@subreg (work@aes_core.shadow_reg.commit_reg), file:${SURELOG_DIR}/tests/PAssignType/dut.sv, line:19:3, endln:19:42 + \_module_inst: work@aes_core (work@aes_core), file:${SURELOG_DIR}/tests/PAssignType/dut.sv, line:22:1, endln:26:10 + |vpiModuleInst: + \_module_inst: work@subreg (work@aes_core.shadow_reg.commit_reg), file:${SURELOG_DIR}/tests/PAssignType/dut.sv, line:19:3, endln:19:42 |vpiParent: - \_module: work@shadow (work@aes_core.shadow_reg), file:${SURELOG_DIR}/tests/PAssignType/dut.sv, line:25:3, endln:25:46 + \_module_inst: work@shadow (work@aes_core.shadow_reg), file:${SURELOG_DIR}/tests/PAssignType/dut.sv, line:25:3, endln:25:46 |vpiName:commit_reg |vpiFullName:work@aes_core.shadow_reg.commit_reg |vpiParameter: \_parameter: (work@aes_core.shadow_reg.commit_reg.RESVAL), line:12:26, endln:12:32 |vpiParent: - \_module: work@subreg (work@aes_core.shadow_reg.commit_reg), file:${SURELOG_DIR}/tests/PAssignType/dut.sv, line:19:3, endln:19:42 + \_module_inst: work@subreg (work@aes_core.shadow_reg.commit_reg), file:${SURELOG_DIR}/tests/PAssignType/dut.sv, line:19:3, endln:19:42 |BIN:0 |vpiTypespec: \_logic_typespec: , line:12:13, endln:12:25 @@ -895,7 +895,7 @@ design: (work@aes_core) |vpiParamAssign: \_param_assign: , line:12:26, endln:12:37 |vpiParent: - \_module: work@subreg (work@aes_core.shadow_reg.commit_reg), file:${SURELOG_DIR}/tests/PAssignType/dut.sv, line:19:3, endln:19:42 + \_module_inst: work@subreg (work@aes_core.shadow_reg.commit_reg), file:${SURELOG_DIR}/tests/PAssignType/dut.sv, line:19:3, endln:19:42 |vpiOverriden:1 |vpiRhs: \_constant: , line:12:35, endln:12:37 @@ -911,7 +911,7 @@ design: (work@aes_core) |vpiDefFile:${SURELOG_DIR}/tests/PAssignType/dut.sv |vpiDefLineNo:11 |vpiInstance: - \_module: work@shadow (work@aes_core.shadow_reg), file:${SURELOG_DIR}/tests/PAssignType/dut.sv, line:25:3, endln:25:46 + \_module_inst: work@shadow (work@aes_core.shadow_reg), file:${SURELOG_DIR}/tests/PAssignType/dut.sv, line:25:3, endln:25:46 =================== [ FATAL] : 0 [ SYNTAX] : 0 diff --git a/tests/PPComment/PPComment.log b/tests/PPComment/PPComment.log index 791b471bba..e7846b9622 100644 --- a/tests/PPComment/PPComment.log +++ b/tests/PPComment/PPComment.log @@ -26,7 +26,7 @@ cont_assign 2 design 1 logic_net 4 -module 3 +module_inst 3 ref_obj 4 === UHDM Object Stats End === [INF:UH0707] Elaborating UHDM... @@ -35,7 +35,7 @@ ref_obj 4 cont_assign 4 design 1 logic_net 4 -module 3 +module_inst 3 ref_obj 8 === UHDM Object Stats End === [INF:UH0708] Writing UHDM DB: ${SURELOG_DIR}/build/regression/PPComment/slpp_unit/surelog.uhdm ... @@ -51,7 +51,7 @@ design: (work@top) |vpiElaborated:1 |vpiName:work@top |uhdmallModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/PPComment/dut.sv, line:1:1, endln:12:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/PPComment/dut.sv, line:1:1, endln:12:10 |vpiParent: \_design: (work@top) |vpiFullName:work@top @@ -59,7 +59,7 @@ design: (work@top) |vpiContAssign: \_cont_assign: , line:5:14, endln:5:18 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/PPComment/dut.sv, line:1:1, endln:12:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/PPComment/dut.sv, line:1:1, endln:12:10 |vpiRhs: \_ref_obj: (work@top.b), line:5:17, endln:5:18 |vpiParent: @@ -79,7 +79,7 @@ design: (work@top) |vpiContAssign: \_cont_assign: , line:6:14, endln:6:18 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/PPComment/dut.sv, line:1:1, endln:12:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/PPComment/dut.sv, line:1:1, endln:12:10 |vpiRhs: \_ref_obj: (work@top.d), line:6:17, endln:6:18 |vpiParent: @@ -97,7 +97,7 @@ design: (work@top) |vpiActual: \_logic_net: (c) |uhdmtopModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/PPComment/dut.sv, line:1:1, endln:12:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/PPComment/dut.sv, line:1:1, endln:12:10 |vpiName:work@top |vpiDefName:work@top |vpiTop:1 @@ -121,7 +121,7 @@ design: (work@top) |vpiContAssign: \_cont_assign: , line:5:14, endln:5:18 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/PPComment/dut.sv, line:1:1, endln:12:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/PPComment/dut.sv, line:1:1, endln:12:10 |vpiRhs: \_ref_obj: (work@top.b), line:5:17, endln:5:18 |vpiParent: @@ -141,7 +141,7 @@ design: (work@top) |vpiContAssign: \_cont_assign: , line:6:14, endln:6:18 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/PPComment/dut.sv, line:1:1, endln:12:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/PPComment/dut.sv, line:1:1, endln:12:10 |vpiRhs: \_ref_obj: (work@top.d), line:6:17, endln:6:18 |vpiParent: diff --git a/tests/PPMacro/PPMacro.log b/tests/PPMacro/PPMacro.log index 5fe0ad3cd2..342f45d60b 100644 --- a/tests/PPMacro/PPMacro.log +++ b/tests/PPMacro/PPMacro.log @@ -98,7 +98,7 @@ constant 9 cont_assign 4 design 1 logic_net 2 -module 5 +module_inst 5 operation 2 ref_obj 4 sys_func_call 2 @@ -110,7 +110,7 @@ constant 9 cont_assign 6 design 1 logic_net 2 -module 5 +module_inst 5 operation 2 ref_obj 6 sys_func_call 2 @@ -128,7 +128,7 @@ design: (work@top1) |vpiElaborated:1 |vpiName:work@top1 |uhdmallModules: -\_module: work@top1 (work@top1), file:${SURELOG_DIR}/tests/PPMacro/dut.sv, line:2:1, endln:4:10 +\_module_inst: work@top1 (work@top1), file:${SURELOG_DIR}/tests/PPMacro/dut.sv, line:2:1, endln:4:10 |vpiParent: \_design: (work@top1) |vpiFullName:work@top1 @@ -136,7 +136,7 @@ design: (work@top1) |vpiContAssign: \_cont_assign: , line:3:10, endln:3:25 |vpiParent: - \_module: work@top1 (work@top1), file:${SURELOG_DIR}/tests/PPMacro/dut.sv, line:2:1, endln:4:10 + \_module_inst: work@top1 (work@top1), file:${SURELOG_DIR}/tests/PPMacro/dut.sv, line:2:1, endln:4:10 |vpiRhs: \_sys_func_call: ($clog2), line:3:14, endln:3:25 |vpiParent: @@ -159,7 +159,7 @@ design: (work@top1) |vpiActual: \_logic_net: (a) |uhdmallModules: -\_module: work@top2 (work@top2), file:${SURELOG_DIR}/tests/PPMacro/dut.sv, line:7:1, endln:9:10 +\_module_inst: work@top2 (work@top2), file:${SURELOG_DIR}/tests/PPMacro/dut.sv, line:7:1, endln:9:10 |vpiParent: \_design: (work@top1) |vpiFullName:work@top2 @@ -167,7 +167,7 @@ design: (work@top1) |vpiContAssign: \_cont_assign: , line:8:10, endln:8:24 |vpiParent: - \_module: work@top2 (work@top2), file:${SURELOG_DIR}/tests/PPMacro/dut.sv, line:7:1, endln:9:10 + \_module_inst: work@top2 (work@top2), file:${SURELOG_DIR}/tests/PPMacro/dut.sv, line:7:1, endln:9:10 |vpiRhs: \_operation: , line:8:14, endln:8:24 |vpiParent: @@ -198,7 +198,7 @@ design: (work@top1) |vpiActual: \_logic_net: (a) |uhdmtopModules: -\_module: work@top1 (work@top1), file:${SURELOG_DIR}/tests/PPMacro/dut.sv, line:2:1, endln:4:10 +\_module_inst: work@top1 (work@top1), file:${SURELOG_DIR}/tests/PPMacro/dut.sv, line:2:1, endln:4:10 |vpiName:work@top1 |vpiDefName:work@top1 |vpiTop:1 @@ -210,7 +210,7 @@ design: (work@top1) |vpiContAssign: \_cont_assign: , line:3:10, endln:3:25 |vpiParent: - \_module: work@top1 (work@top1), file:${SURELOG_DIR}/tests/PPMacro/dut.sv, line:2:1, endln:4:10 + \_module_inst: work@top1 (work@top1), file:${SURELOG_DIR}/tests/PPMacro/dut.sv, line:2:1, endln:4:10 |vpiRhs: \_constant: |vpiParent: @@ -228,7 +228,7 @@ design: (work@top1) |vpiActual: \_logic_net: (a) |uhdmtopModules: -\_module: work@top2 (work@top2), file:${SURELOG_DIR}/tests/PPMacro/dut.sv, line:7:1, endln:9:10 +\_module_inst: work@top2 (work@top2), file:${SURELOG_DIR}/tests/PPMacro/dut.sv, line:7:1, endln:9:10 |vpiName:work@top2 |vpiDefName:work@top2 |vpiTop:1 @@ -240,7 +240,7 @@ design: (work@top1) |vpiContAssign: \_cont_assign: , line:8:10, endln:8:24 |vpiParent: - \_module: work@top2 (work@top2), file:${SURELOG_DIR}/tests/PPMacro/dut.sv, line:7:1, endln:9:10 + \_module_inst: work@top2 (work@top2), file:${SURELOG_DIR}/tests/PPMacro/dut.sv, line:7:1, endln:9:10 |vpiRhs: \_constant: |vpiParent: diff --git a/tests/PackDataType/PackDataType.log b/tests/PackDataType/PackDataType.log index 732d3f5e26..509c88fccd 100644 --- a/tests/PackDataType/PackDataType.log +++ b/tests/PackDataType/PackDataType.log @@ -492,7 +492,7 @@ io_decl 11 logic_net 2 logic_typespec 7 logic_var 2 -module 9 +module_inst 9 operation 6 package 5 param_assign 6 @@ -528,7 +528,7 @@ io_decl 22 logic_net 2 logic_typespec 7 logic_var 2 -module 10 +module_inst 10 operation 6 package 5 param_assign 6 @@ -1267,20 +1267,20 @@ design: (work@kmac_keymgr) \_int_typespec: |vpiSigned:1 |uhdmallModules: -\_module: work@OK (work@OK), file:${SURELOG_DIR}/tests/PackDataType/dut.sv, line:13:1, endln:14:10 +\_module_inst: work@OK (work@OK), file:${SURELOG_DIR}/tests/PackDataType/dut.sv, line:13:1, endln:14:10 |vpiParent: \_design: (work@kmac_keymgr) |vpiFullName:work@OK |vpiDefName:work@OK |uhdmallModules: -\_module: work@kmac_keymgr (work@kmac_keymgr), file:${SURELOG_DIR}/tests/PackDataType/dut.sv, line:16:1, endln:24:10 +\_module_inst: work@kmac_keymgr (work@kmac_keymgr), file:${SURELOG_DIR}/tests/PackDataType/dut.sv, line:16:1, endln:24:10 |vpiParent: \_design: (work@kmac_keymgr) |vpiFullName:work@kmac_keymgr |vpiParameter: \_parameter: (work@kmac_keymgr.KeyMgrDigestW), line:18:17, endln:18:30 |vpiParent: - \_module: work@kmac_keymgr (work@kmac_keymgr), file:${SURELOG_DIR}/tests/PackDataType/dut.sv, line:16:1, endln:24:10 + \_module_inst: work@kmac_keymgr (work@kmac_keymgr), file:${SURELOG_DIR}/tests/PackDataType/dut.sv, line:16:1, endln:24:10 |UINT:247 |vpiTypespec: \_int_typespec: , line:18:13, endln:18:16 @@ -1294,7 +1294,7 @@ design: (work@kmac_keymgr) |vpiParamAssign: \_param_assign: , line:18:17, endln:18:67 |vpiParent: - \_module: work@kmac_keymgr (work@kmac_keymgr), file:${SURELOG_DIR}/tests/PackDataType/dut.sv, line:16:1, endln:24:10 + \_module_inst: work@kmac_keymgr (work@kmac_keymgr), file:${SURELOG_DIR}/tests/PackDataType/dut.sv, line:16:1, endln:24:10 |vpiRhs: \_constant: , line:18:33, endln:18:67 |vpiDecompile:247 @@ -1309,21 +1309,21 @@ design: (work@kmac_keymgr) |vpiNet: \_logic_net: (work@kmac_keymgr.keymgr_data_o), line:16:55, endln:16:68 |vpiParent: - \_module: work@kmac_keymgr (work@kmac_keymgr), file:${SURELOG_DIR}/tests/PackDataType/dut.sv, line:16:1, endln:24:10 + \_module_inst: work@kmac_keymgr (work@kmac_keymgr), file:${SURELOG_DIR}/tests/PackDataType/dut.sv, line:16:1, endln:24:10 |vpiName:keymgr_data_o |vpiFullName:work@kmac_keymgr.keymgr_data_o |vpiNetType:1 |vpiNet: \_logic_net: (work@kmac_keymgr.keymgr_digest), line:22:28, endln:22:41 |vpiParent: - \_module: work@kmac_keymgr (work@kmac_keymgr), file:${SURELOG_DIR}/tests/PackDataType/dut.sv, line:16:1, endln:24:10 + \_module_inst: work@kmac_keymgr (work@kmac_keymgr), file:${SURELOG_DIR}/tests/PackDataType/dut.sv, line:16:1, endln:24:10 |vpiName:keymgr_digest |vpiFullName:work@kmac_keymgr.keymgr_digest |vpiNetType:36 |vpiPort: \_port: (keymgr_data_o), line:16:55, endln:16:68 |vpiParent: - \_module: work@kmac_keymgr (work@kmac_keymgr), file:${SURELOG_DIR}/tests/PackDataType/dut.sv, line:16:1, endln:24:10 + \_module_inst: work@kmac_keymgr (work@kmac_keymgr), file:${SURELOG_DIR}/tests/PackDataType/dut.sv, line:16:1, endln:24:10 |vpiName:keymgr_data_o |vpiDirection:2 |vpiLowConn: @@ -1333,12 +1333,12 @@ design: (work@kmac_keymgr) |vpiTypedef: \_struct_typespec: (keymgr_pkg::kmac_data_rsp_t), line:5:10, endln:5:16 |uhdmtopModules: -\_module: work@kmac_keymgr (work@kmac_keymgr), file:${SURELOG_DIR}/tests/PackDataType/dut.sv, line:16:1, endln:24:10 +\_module_inst: work@kmac_keymgr (work@kmac_keymgr), file:${SURELOG_DIR}/tests/PackDataType/dut.sv, line:16:1, endln:24:10 |vpiName:work@kmac_keymgr |vpiVariables: \_array_var: (work@kmac_keymgr.keymgr_digest), line:22:28, endln:22:45 |vpiParent: - \_module: work@kmac_keymgr (work@kmac_keymgr), file:${SURELOG_DIR}/tests/PackDataType/dut.sv, line:16:1, endln:24:10 + \_module_inst: work@kmac_keymgr (work@kmac_keymgr), file:${SURELOG_DIR}/tests/PackDataType/dut.sv, line:16:1, endln:24:10 |vpiSize:2 |vpiTypespec: \_array_typespec: @@ -1419,7 +1419,7 @@ design: (work@kmac_keymgr) |vpiParameter: \_parameter: (work@kmac_keymgr.KeyMgrDigestW), line:18:17, endln:18:30 |vpiParent: - \_module: work@kmac_keymgr (work@kmac_keymgr), file:${SURELOG_DIR}/tests/PackDataType/dut.sv, line:16:1, endln:24:10 + \_module_inst: work@kmac_keymgr (work@kmac_keymgr), file:${SURELOG_DIR}/tests/PackDataType/dut.sv, line:16:1, endln:24:10 |UINT:247 |vpiTypespec: \_int_typespec: , line:18:13, endln:18:16 @@ -1433,7 +1433,7 @@ design: (work@kmac_keymgr) |vpiParamAssign: \_param_assign: , line:18:17, endln:18:67 |vpiParent: - \_module: work@kmac_keymgr (work@kmac_keymgr), file:${SURELOG_DIR}/tests/PackDataType/dut.sv, line:16:1, endln:24:10 + \_module_inst: work@kmac_keymgr (work@kmac_keymgr), file:${SURELOG_DIR}/tests/PackDataType/dut.sv, line:16:1, endln:24:10 |vpiRhs: \_constant: , line:18:33, endln:18:67 |vpiDecompile:247 @@ -1449,7 +1449,7 @@ design: (work@kmac_keymgr) |vpiNet: \_struct_net: (work@kmac_keymgr.keymgr_data_o), line:16:55, endln:16:68 |vpiParent: - \_module: work@kmac_keymgr (work@kmac_keymgr), file:${SURELOG_DIR}/tests/PackDataType/dut.sv, line:16:1, endln:24:10 + \_module_inst: work@kmac_keymgr (work@kmac_keymgr), file:${SURELOG_DIR}/tests/PackDataType/dut.sv, line:16:1, endln:24:10 |vpiTypespec: \_struct_typespec: (keymgr_pkg::kmac_data_rsp_t), line:5:10, endln:5:16 |vpiName:keymgr_data_o @@ -1459,7 +1459,7 @@ design: (work@kmac_keymgr) |vpiPort: \_port: (keymgr_data_o), line:16:55, endln:16:68 |vpiParent: - \_module: work@kmac_keymgr (work@kmac_keymgr), file:${SURELOG_DIR}/tests/PackDataType/dut.sv, line:16:1, endln:24:10 + \_module_inst: work@kmac_keymgr (work@kmac_keymgr), file:${SURELOG_DIR}/tests/PackDataType/dut.sv, line:16:1, endln:24:10 |vpiName:keymgr_data_o |vpiDirection:2 |vpiLowConn: @@ -1473,11 +1473,11 @@ design: (work@kmac_keymgr) |vpiTypedef: \_struct_typespec: (keymgr_pkg::kmac_data_rsp_t), line:5:10, endln:5:16 |vpiInstance: - \_module: work@kmac_keymgr (work@kmac_keymgr), file:${SURELOG_DIR}/tests/PackDataType/dut.sv, line:16:1, endln:24:10 + \_module_inst: work@kmac_keymgr (work@kmac_keymgr), file:${SURELOG_DIR}/tests/PackDataType/dut.sv, line:16:1, endln:24:10 |vpiGenScopeArray: \_gen_scope_array: (work@kmac_keymgr.genblk1), line:19:2, endln:20:12 |vpiParent: - \_module: work@kmac_keymgr (work@kmac_keymgr), file:${SURELOG_DIR}/tests/PackDataType/dut.sv, line:16:1, endln:24:10 + \_module_inst: work@kmac_keymgr (work@kmac_keymgr), file:${SURELOG_DIR}/tests/PackDataType/dut.sv, line:16:1, endln:24:10 |vpiName:genblk1 |vpiFullName:work@kmac_keymgr.genblk1 |vpiGenScope: @@ -1485,8 +1485,8 @@ design: (work@kmac_keymgr) |vpiParent: \_gen_scope_array: (work@kmac_keymgr.genblk1), line:19:2, endln:20:12 |vpiFullName:work@kmac_keymgr.genblk1 - |vpiModule: - \_module: work@OK (work@kmac_keymgr.genblk1.ok), file:${SURELOG_DIR}/tests/PackDataType/dut.sv, line:20:4, endln:20:12 + |vpiModuleInst: + \_module_inst: work@OK (work@kmac_keymgr.genblk1.ok), file:${SURELOG_DIR}/tests/PackDataType/dut.sv, line:20:4, endln:20:12 |vpiParent: \_gen_scope: (work@kmac_keymgr.genblk1) |vpiName:ok diff --git a/tests/PackFunc/PackFunc.log b/tests/PackFunc/PackFunc.log index 7ff0a694aa..8478a83201 100644 --- a/tests/PackFunc/PackFunc.log +++ b/tests/PackFunc/PackFunc.log @@ -161,7 +161,7 @@ function 2 io_decl 2 logic_typespec 8 logic_var 2 -module 1 +module_inst 1 operation 6 package 6 range 10 @@ -183,7 +183,7 @@ function 4 io_decl 4 logic_typespec 8 logic_var 4 -module 1 +module_inst 1 operation 6 package 6 range 10 diff --git a/tests/PackFuncParent/PackFuncParent.log b/tests/PackFuncParent/PackFuncParent.log index be89d9d9d4..6f66f9361c 100644 --- a/tests/PackFuncParent/PackFuncParent.log +++ b/tests/PackFuncParent/PackFuncParent.log @@ -252,7 +252,7 @@ io_decl 4 logic_net 2 logic_typespec 15 logic_var 6 -module 6 +module_inst 6 package 3 param_assign 6 parameter 6 @@ -277,7 +277,7 @@ io_decl 8 logic_net 2 logic_typespec 15 logic_var 10 -module 6 +module_inst 6 package 3 param_assign 6 parameter 6 @@ -830,7 +830,7 @@ design: (work@top) |vpiInstance: \_package: my_pkg (my_pkg::), file:${SURELOG_DIR}/tests/PackFuncParent/dut.sv, line:1:1, endln:11:11 |uhdmallModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/PackFuncParent/dut.sv, line:13:1, endln:15:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/PackFuncParent/dut.sv, line:13:1, endln:15:10 |vpiParent: \_design: (work@top) |vpiFullName:work@top @@ -838,14 +838,14 @@ design: (work@top) |vpiNet: \_logic_net: (work@top.o), line:13:32, endln:13:33 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/PackFuncParent/dut.sv, line:13:1, endln:15:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/PackFuncParent/dut.sv, line:13:1, endln:15:10 |vpiName:o |vpiFullName:work@top.o |vpiNetType:36 |vpiPort: \_port: (o), line:13:32, endln:13:33 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/PackFuncParent/dut.sv, line:13:1, endln:15:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/PackFuncParent/dut.sv, line:13:1, endln:15:10 |vpiName:o |vpiDirection:2 |vpiLowConn: @@ -875,7 +875,7 @@ design: (work@top) |vpiContAssign: \_cont_assign: , line:14:11, endln:14:44 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/PackFuncParent/dut.sv, line:13:1, endln:15:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/PackFuncParent/dut.sv, line:13:1, endln:15:10 |vpiRhs: \_func_call: (my_pkg::sbox4_16bit), line:14:15, endln:14:21 |vpiParent: @@ -902,14 +902,14 @@ design: (work@top) |vpiActual: \_logic_net: (work@top.o), line:13:32, endln:13:33 |uhdmtopModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/PackFuncParent/dut.sv, line:13:1, endln:15:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/PackFuncParent/dut.sv, line:13:1, endln:15:10 |vpiName:work@top |vpiDefName:work@top |vpiTop:1 |vpiNet: \_logic_net: (work@top.o), line:13:32, endln:13:33 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/PackFuncParent/dut.sv, line:13:1, endln:15:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/PackFuncParent/dut.sv, line:13:1, endln:15:10 |vpiTypespec: \_logic_typespec: , line:13:19, endln:13:31 |vpiRange: @@ -937,7 +937,7 @@ design: (work@top) |vpiPort: \_port: (o), line:13:32, endln:13:33 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/PackFuncParent/dut.sv, line:13:1, endln:15:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/PackFuncParent/dut.sv, line:13:1, endln:15:10 |vpiName:o |vpiDirection:2 |vpiLowConn: @@ -971,11 +971,11 @@ design: (work@top) |UINT:0 |vpiConstType:9 |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/PackFuncParent/dut.sv, line:13:1, endln:15:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/PackFuncParent/dut.sv, line:13:1, endln:15:10 |vpiContAssign: \_cont_assign: , line:14:11, endln:14:44 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/PackFuncParent/dut.sv, line:13:1, endln:15:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/PackFuncParent/dut.sv, line:13:1, endln:15:10 |vpiRhs: \_constant: |vpiParent: diff --git a/tests/PackImport/PackImport.log b/tests/PackImport/PackImport.log index 2862f5c174..f61b994875 100644 --- a/tests/PackImport/PackImport.log +++ b/tests/PackImport/PackImport.log @@ -47,7 +47,7 @@ enum_typespec 2 import_typespec 3 logic_net 4 logic_typespec 12 -module 6 +module_inst 6 operation 12 package 6 param_assign 4 @@ -183,7 +183,7 @@ design: (work@top) |vpiTypedef: \_enum_typespec: (ibex_pkg::opcode_e), line:5:1, endln:8:12 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/PackImport/dut.sv, line:18:1, endln:20:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/PackImport/dut.sv, line:18:1, endln:20:10 |vpiName:ibex_pkg::opcode_e |vpiInstance: \_package: ibex_tracer_pkg (ibex_tracer_pkg::), file:${SURELOG_DIR}/tests/PackImport/dut.sv, line:11:1, endln:14:11 @@ -306,7 +306,7 @@ design: (work@top) |vpiDefName:ibex_tracer_pkg |vpiTop:1 |uhdmallModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/PackImport/dut.sv, line:18:1, endln:20:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/PackImport/dut.sv, line:18:1, endln:20:10 |vpiParent: \_design: (work@top) |vpiFullName:work@top @@ -318,20 +318,20 @@ design: (work@top) |vpiNet: \_logic_net: (work@top.clk_i), line:18:18, endln:18:23 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/PackImport/dut.sv, line:18:1, endln:20:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/PackImport/dut.sv, line:18:1, endln:20:10 |vpiName:clk_i |vpiFullName:work@top.clk_i |vpiNet: \_logic_net: (work@top.o1), line:18:45, endln:18:47 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/PackImport/dut.sv, line:18:1, endln:20:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/PackImport/dut.sv, line:18:1, endln:20:10 |vpiName:o1 |vpiFullName:work@top.o1 |vpiNetType:36 |vpiPort: \_port: (clk_i), line:18:18, endln:18:23 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/PackImport/dut.sv, line:18:1, endln:20:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/PackImport/dut.sv, line:18:1, endln:20:10 |vpiName:clk_i |vpiDirection:1 |vpiLowConn: @@ -343,7 +343,7 @@ design: (work@top) |vpiPort: \_port: (o1), line:18:45, endln:18:47 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/PackImport/dut.sv, line:18:1, endln:20:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/PackImport/dut.sv, line:18:1, endln:20:10 |vpiName:o1 |vpiDirection:2 |vpiLowConn: @@ -371,7 +371,7 @@ design: (work@top) |UINT:0 |vpiConstType:9 |uhdmtopModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/PackImport/dut.sv, line:18:1, endln:20:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/PackImport/dut.sv, line:18:1, endln:20:10 |vpiName:work@top |vpiTypedef: \_enum_typespec: (ibex_pkg::opcode_e), line:5:1, endln:8:12 @@ -382,7 +382,7 @@ design: (work@top) |vpiNet: \_logic_net: (work@top.clk_i), line:18:18, endln:18:23 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/PackImport/dut.sv, line:18:1, endln:20:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/PackImport/dut.sv, line:18:1, endln:20:10 |vpiTypespec: \_logic_typespec: , line:18:18, endln:18:18 |vpiName:clk_i @@ -390,7 +390,7 @@ design: (work@top) |vpiNet: \_logic_net: (work@top.o1), line:18:45, endln:18:47 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/PackImport/dut.sv, line:18:1, endln:20:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/PackImport/dut.sv, line:18:1, endln:20:10 |vpiTypespec: \_logic_typespec: , line:18:32, endln:18:44 |vpiRange: @@ -418,7 +418,7 @@ design: (work@top) |vpiPort: \_port: (clk_i), line:18:18, endln:18:23 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/PackImport/dut.sv, line:18:1, endln:20:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/PackImport/dut.sv, line:18:1, endln:20:10 |vpiName:clk_i |vpiDirection:1 |vpiLowConn: @@ -432,7 +432,7 @@ design: (work@top) |vpiPort: \_port: (o1), line:18:45, endln:18:47 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/PackImport/dut.sv, line:18:1, endln:20:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/PackImport/dut.sv, line:18:1, endln:20:10 |vpiName:o1 |vpiDirection:2 |vpiLowConn: diff --git a/tests/PackStructVar/PackStructVar.log b/tests/PackStructVar/PackStructVar.log index 2e15812df6..8409ef7524 100644 --- a/tests/PackStructVar/PackStructVar.log +++ b/tests/PackStructVar/PackStructVar.log @@ -38,7 +38,7 @@ enum_typespec 2 int_typespec 53 logic_net 1 logic_typespec 20 -module 7 +module_inst 7 operation 27 package 6 param_assign 44 @@ -62,7 +62,7 @@ enum_typespec 2 int_typespec 53 logic_net 1 logic_typespec 20 -module 7 +module_inst 7 operation 27 package 6 param_assign 44 @@ -1520,7 +1520,7 @@ design: (work@flash_ctrl) |vpiDefName:tlul_pkg |vpiTop:1 |uhdmallModules: -\_module: work@flash_ctrl (work@flash_ctrl), file:${SURELOG_DIR}/tests/PackStructVar/dut.sv, line:41:1, endln:47:10 +\_module_inst: work@flash_ctrl (work@flash_ctrl), file:${SURELOG_DIR}/tests/PackStructVar/dut.sv, line:41:1, endln:47:10 |vpiParent: \_design: (work@flash_ctrl) |vpiFullName:work@flash_ctrl @@ -1528,16 +1528,16 @@ design: (work@flash_ctrl) |vpiNet: \_logic_net: (work@flash_ctrl.tl_fifo_h2d), line:44:21, endln:44:32 |vpiParent: - \_module: work@flash_ctrl (work@flash_ctrl), file:${SURELOG_DIR}/tests/PackStructVar/dut.sv, line:41:1, endln:47:10 + \_module_inst: work@flash_ctrl (work@flash_ctrl), file:${SURELOG_DIR}/tests/PackStructVar/dut.sv, line:41:1, endln:47:10 |vpiName:tl_fifo_h2d |vpiFullName:work@flash_ctrl.tl_fifo_h2d |uhdmtopModules: -\_module: work@flash_ctrl (work@flash_ctrl), file:${SURELOG_DIR}/tests/PackStructVar/dut.sv, line:41:1, endln:47:10 +\_module_inst: work@flash_ctrl (work@flash_ctrl), file:${SURELOG_DIR}/tests/PackStructVar/dut.sv, line:41:1, endln:47:10 |vpiName:work@flash_ctrl |vpiVariables: \_array_var: (work@flash_ctrl.tl_fifo_h2d), line:44:21, endln:44:36 |vpiParent: - \_module: work@flash_ctrl (work@flash_ctrl), file:${SURELOG_DIR}/tests/PackStructVar/dut.sv, line:41:1, endln:47:10 + \_module_inst: work@flash_ctrl (work@flash_ctrl), file:${SURELOG_DIR}/tests/PackStructVar/dut.sv, line:41:1, endln:47:10 |vpiSize:2 |vpiTypespec: \_array_typespec: diff --git a/tests/PackageBind/PackageBind.log b/tests/PackageBind/PackageBind.log index 97169b9293..52cb9dd26a 100644 --- a/tests/PackageBind/PackageBind.log +++ b/tests/PackageBind/PackageBind.log @@ -182,7 +182,7 @@ integer_typespec 10 integer_var 5 io_decl 2 logic_net 1 -module 4 +module_inst 4 operation 6 package 3 param_assign 9 @@ -208,7 +208,7 @@ integer_typespec 10 integer_var 9 io_decl 4 logic_net 1 -module 4 +module_inst 4 operation 12 package 3 param_assign 9 @@ -596,7 +596,7 @@ design: (work@top) |vpiInstance: \_package: prim_util_pkg (prim_util_pkg::), file:${SURELOG_DIR}/tests/PackageBind/dut.sv, line:1:1, endln:10:11 |uhdmallModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/PackageBind/dut.sv, line:12:1, endln:14:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/PackageBind/dut.sv, line:12:1, endln:14:10 |vpiParent: \_design: (work@top) |vpiFullName:work@top @@ -604,13 +604,13 @@ design: (work@top) |vpiNet: \_logic_net: (work@top.o), line:12:27, endln:12:28 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/PackageBind/dut.sv, line:12:1, endln:14:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/PackageBind/dut.sv, line:12:1, endln:14:10 |vpiName:o |vpiFullName:work@top.o |vpiPort: \_port: (o), line:12:27, endln:12:28 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/PackageBind/dut.sv, line:12:1, endln:14:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/PackageBind/dut.sv, line:12:1, endln:14:10 |vpiName:o |vpiDirection:2 |vpiLowConn: @@ -623,7 +623,7 @@ design: (work@top) |vpiContAssign: \_cont_assign: , line:13:11, endln:13:40 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/PackageBind/dut.sv, line:12:1, endln:14:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/PackageBind/dut.sv, line:12:1, endln:14:10 |vpiRhs: \_func_call: (prim_util_pkg::_clog2), line:13:15, endln:13:28 |vpiParent: @@ -650,12 +650,12 @@ design: (work@top) |vpiActual: \_integer_var: (work@top.o), line:12:27, endln:12:28 |uhdmtopModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/PackageBind/dut.sv, line:12:1, endln:14:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/PackageBind/dut.sv, line:12:1, endln:14:10 |vpiName:work@top |vpiVariables: \_integer_var: (work@top.o), line:12:27, endln:12:28 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/PackageBind/dut.sv, line:12:1, endln:14:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/PackageBind/dut.sv, line:12:1, endln:14:10 |vpiTypespec: \_integer_typespec: , line:12:19, endln:12:26 |vpiSigned:1 @@ -669,7 +669,7 @@ design: (work@top) |vpiPort: \_port: (o), line:12:27, endln:12:28 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/PackageBind/dut.sv, line:12:1, endln:14:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/PackageBind/dut.sv, line:12:1, endln:14:10 |vpiName:o |vpiDirection:2 |vpiLowConn: @@ -684,11 +684,11 @@ design: (work@top) \_integer_typespec: , line:12:19, endln:12:26 |vpiSigned:1 |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/PackageBind/dut.sv, line:12:1, endln:14:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/PackageBind/dut.sv, line:12:1, endln:14:10 |vpiContAssign: \_cont_assign: , line:13:11, endln:13:40 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/PackageBind/dut.sv, line:12:1, endln:14:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/PackageBind/dut.sv, line:12:1, endln:14:10 |vpiRhs: \_constant: |vpiParent: diff --git a/tests/PackageConst/PackageConst.log b/tests/PackageConst/PackageConst.log index 75b517c693..98a92bf058 100644 --- a/tests/PackageConst/PackageConst.log +++ b/tests/PackageConst/PackageConst.log @@ -78,7 +78,7 @@ design 1 enum_const 2 enum_typespec 2 int_typespec 8 -module 4 +module_inst 4 package 6 param_assign 4 parameter 4 @@ -92,7 +92,7 @@ design 1 enum_const 2 enum_typespec 2 int_typespec 8 -module 4 +module_inst 4 package 6 param_assign 4 parameter 4 diff --git a/tests/PackageDpi/PackageDpi.log b/tests/PackageDpi/PackageDpi.log index 5dcf2a7b13..a86ebcae95 100644 --- a/tests/PackageDpi/PackageDpi.log +++ b/tests/PackageDpi/PackageDpi.log @@ -37,7 +37,7 @@ int_typespec 5 int_var 5 io_decl 2 logic_net 4 -module 2 +module_inst 2 package 3 range 2 ref_obj 2 @@ -60,7 +60,7 @@ int_typespec 5 int_var 6 io_decl 4 logic_net 4 -module 2 +module_inst 2 package 3 range 2 ref_obj 2 diff --git a/tests/PackageEval/PackageEval.log b/tests/PackageEval/PackageEval.log index 3bd6fb8211..174b76e921 100644 --- a/tests/PackageEval/PackageEval.log +++ b/tests/PackageEval/PackageEval.log @@ -26,7 +26,7 @@ constant 42 design 1 int_typespec 11 logic_typespec 4 -module 2 +module_inst 2 operation 10 package 3 param_assign 12 @@ -44,7 +44,7 @@ constant 42 design 1 int_typespec 11 logic_typespec 4 -module 2 +module_inst 2 operation 10 package 3 param_assign 12 diff --git a/tests/PackageFuncCall/PackageFuncCall.log b/tests/PackageFuncCall/PackageFuncCall.log index 2bd3fcc89b..c015382cc2 100644 --- a/tests/PackageFuncCall/PackageFuncCall.log +++ b/tests/PackageFuncCall/PackageFuncCall.log @@ -796,7 +796,7 @@ io_decl 15 logic_net 7 logic_typespec 16 logic_var 5 -module 5 +module_inst 5 named_begin 1 operation 26 package 5 @@ -842,7 +842,7 @@ io_decl 30 logic_net 7 logic_typespec 16 logic_var 9 -module 5 +module_inst 5 named_begin 2 operation 40 package 5 @@ -2566,7 +2566,7 @@ design: (work@top) \_int_typespec: |vpiSigned:1 |uhdmallModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/PackageFuncCall/dut.sv, line:26:1, endln:42:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/PackageFuncCall/dut.sv, line:26:1, endln:42:10 |vpiParent: \_design: (work@top) |vpiFullName:work@top @@ -2574,7 +2574,7 @@ design: (work@top) |vpiProcess: \_always: , line:31:2, endln:38:13 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/PackageFuncCall/dut.sv, line:26:1, endln:42:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/PackageFuncCall/dut.sv, line:26:1, endln:42:10 |vpiStmt: \_named_begin: (work@top.p_post_round_xor), line:31:14, endln:38:13 |vpiParent: @@ -2737,7 +2737,7 @@ design: (work@top) |vpiContAssign: \_cont_assign: , line:28:8, endln:29:55 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/PackageFuncCall/dut.sv, line:26:1, endln:42:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/PackageFuncCall/dut.sv, line:26:1, endln:42:10 |vpiRhs: \_func_call: (prim_cipher_pkg::sbox4_64bit), line:28:26, endln:28:41 |vpiParent: @@ -2771,7 +2771,7 @@ design: (work@top) |vpiActual: \_logic_net: (data_state_sbox) |uhdmtopModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/PackageFuncCall/dut.sv, line:26:1, endln:42:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/PackageFuncCall/dut.sv, line:26:1, endln:42:10 |vpiName:work@top |vpiDefName:work@top |vpiTop:1 @@ -2807,7 +2807,7 @@ design: (work@top) |vpiProcess: \_always: , line:31:2, endln:38:13 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/PackageFuncCall/dut.sv, line:26:1, endln:42:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/PackageFuncCall/dut.sv, line:26:1, endln:42:10 |vpiStmt: \_named_begin: (work@top.p_post_round_xor), line:31:14, endln:38:13 |vpiParent: @@ -2945,7 +2945,7 @@ design: (work@top) |vpiContAssign: \_cont_assign: , line:28:8, endln:29:55 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/PackageFuncCall/dut.sv, line:26:1, endln:42:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/PackageFuncCall/dut.sv, line:26:1, endln:42:10 |vpiRhs: \_func_call: (prim_cipher_pkg::sbox4_64bit), line:28:26, endln:28:41 |vpiParent: diff --git a/tests/PackageHierRef/PackageHierRef.log b/tests/PackageHierRef/PackageHierRef.log index 3289681e9f..de554a5785 100644 --- a/tests/PackageHierRef/PackageHierRef.log +++ b/tests/PackageHierRef/PackageHierRef.log @@ -775,7 +775,7 @@ int_var 13 io_decl 11 logic_net 2 logic_var 1 -module 13 +module_inst 13 named_begin 1 package 14 param_assign 18 diff --git a/tests/PackageNet/PackageNet.log b/tests/PackageNet/PackageNet.log index 8cface07b8..60dc4c1e3f 100644 --- a/tests/PackageNet/PackageNet.log +++ b/tests/PackageNet/PackageNet.log @@ -144,7 +144,7 @@ int_typespec 14 logic_net 5 logic_typespec 6 logic_var 1 -module 5 +module_inst 5 operation 1 package 3 packed_array_typespec 2 @@ -166,7 +166,7 @@ int_typespec 14 logic_net 5 logic_typespec 6 logic_var 1 -module 5 +module_inst 5 operation 2 package 3 packed_array_typespec 2 @@ -328,7 +328,7 @@ design: (work@test) |vpiTypedef: \_logic_typespec: (my_package1::word), line:6:9, endln:6:20 |vpiParent: - \_module: work@test (work@test), file:${SURELOG_DIR}/tests/PackageNet/dut.sv, line:13:1, endln:21:10 + \_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/PackageNet/dut.sv, line:13:1, endln:21:10 |vpiName:my_package1::word |vpiInstance: \_package: my_package1 (my_package1::), file:${SURELOG_DIR}/tests/PackageNet/dut.sv, line:1:1, endln:10:11 @@ -360,14 +360,14 @@ design: (work@test) |vpiFullName:my_package1::v |vpiNetType:36 |uhdmallModules: -\_module: work@test (work@test), file:${SURELOG_DIR}/tests/PackageNet/dut.sv, line:13:1, endln:21:10 +\_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/PackageNet/dut.sv, line:13:1, endln:21:10 |vpiParent: \_design: (work@test) |vpiFullName:work@test |vpiParameter: \_parameter: (work@test.p1), line:3:12, endln:3:14 |vpiParent: - \_module: work@test (work@test), file:${SURELOG_DIR}/tests/PackageNet/dut.sv, line:13:1, endln:21:10 + \_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/PackageNet/dut.sv, line:13:1, endln:21:10 |UINT:1 |vpiTypespec: \_int_typespec: @@ -379,7 +379,7 @@ design: (work@test) |vpiParameter: \_parameter: (work@test.p2), line:4:12, endln:4:14 |vpiParent: - \_module: work@test (work@test), file:${SURELOG_DIR}/tests/PackageNet/dut.sv, line:13:1, endln:21:10 + \_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/PackageNet/dut.sv, line:13:1, endln:21:10 |UINT:2 |vpiTypespec: \_int_typespec: @@ -392,7 +392,7 @@ design: (work@test) |vpiParamAssign: \_param_assign: , line:3:12, endln:3:18 |vpiParent: - \_module: work@test (work@test), file:${SURELOG_DIR}/tests/PackageNet/dut.sv, line:13:1, endln:21:10 + \_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/PackageNet/dut.sv, line:13:1, endln:21:10 |vpiRhs: \_constant: , line:3:17, endln:3:18 |vpiParent: @@ -420,7 +420,7 @@ design: (work@test) |vpiParamAssign: \_param_assign: , line:4:12, endln:4:18 |vpiParent: - \_module: work@test (work@test), file:${SURELOG_DIR}/tests/PackageNet/dut.sv, line:13:1, endln:21:10 + \_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/PackageNet/dut.sv, line:13:1, endln:21:10 |vpiRhs: \_constant: , line:4:17, endln:4:18 |vpiParent: @@ -454,14 +454,14 @@ design: (work@test) |vpiNet: \_logic_net: (work@test.v), line:8:6, endln:8:7 |vpiParent: - \_module: work@test (work@test), file:${SURELOG_DIR}/tests/PackageNet/dut.sv, line:13:1, endln:21:10 + \_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/PackageNet/dut.sv, line:13:1, endln:21:10 |vpiName:v |vpiFullName:work@test.v |vpiNetType:36 |vpiProcess: \_initial: , line:17:1, endln:19:4 |vpiParent: - \_module: work@test (work@test), file:${SURELOG_DIR}/tests/PackageNet/dut.sv, line:13:1, endln:21:10 + \_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/PackageNet/dut.sv, line:13:1, endln:21:10 |vpiStmt: \_begin: (work@test), line:17:9, endln:19:4 |vpiParent: @@ -511,12 +511,12 @@ design: (work@test) |vpiActual: \_logic_var: (work@test.v), line:8:6, endln:8:7 |uhdmtopModules: -\_module: work@test (work@test), file:${SURELOG_DIR}/tests/PackageNet/dut.sv, line:13:1, endln:21:10 +\_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/PackageNet/dut.sv, line:13:1, endln:21:10 |vpiName:work@test |vpiVariables: \_logic_var: (work@test.v), line:8:6, endln:8:7 |vpiParent: - \_module: work@test (work@test), file:${SURELOG_DIR}/tests/PackageNet/dut.sv, line:13:1, endln:21:10 + \_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/PackageNet/dut.sv, line:13:1, endln:21:10 |vpiTypespec: \_logic_typespec: (word), line:6:9, endln:6:20 |vpiName:word @@ -548,7 +548,7 @@ design: (work@test) |vpiParameter: \_parameter: (work@test.p1), line:3:12, endln:3:14 |vpiParent: - \_module: work@test (work@test), file:${SURELOG_DIR}/tests/PackageNet/dut.sv, line:13:1, endln:21:10 + \_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/PackageNet/dut.sv, line:13:1, endln:21:10 |UINT:1 |vpiTypespec: \_int_typespec: @@ -560,7 +560,7 @@ design: (work@test) |vpiParameter: \_parameter: (work@test.p2), line:4:12, endln:4:14 |vpiParent: - \_module: work@test (work@test), file:${SURELOG_DIR}/tests/PackageNet/dut.sv, line:13:1, endln:21:10 + \_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/PackageNet/dut.sv, line:13:1, endln:21:10 |UINT:2 |vpiTypespec: \_int_typespec: @@ -573,7 +573,7 @@ design: (work@test) |vpiParamAssign: \_param_assign: , line:3:12, endln:3:18 |vpiParent: - \_module: work@test (work@test), file:${SURELOG_DIR}/tests/PackageNet/dut.sv, line:13:1, endln:21:10 + \_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/PackageNet/dut.sv, line:13:1, endln:21:10 |vpiRhs: \_constant: , line:3:17, endln:3:18 |vpiDecompile:1 @@ -587,7 +587,7 @@ design: (work@test) |vpiParamAssign: \_param_assign: , line:4:12, endln:4:18 |vpiParent: - \_module: work@test (work@test), file:${SURELOG_DIR}/tests/PackageNet/dut.sv, line:13:1, endln:21:10 + \_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/PackageNet/dut.sv, line:13:1, endln:21:10 |vpiRhs: \_constant: , line:4:17, endln:4:18 |vpiDecompile:2 @@ -608,7 +608,7 @@ design: (work@test) |vpiProcess: \_initial: , line:17:1, endln:19:4 |vpiParent: - \_module: work@test (work@test), file:${SURELOG_DIR}/tests/PackageNet/dut.sv, line:13:1, endln:21:10 + \_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/PackageNet/dut.sv, line:13:1, endln:21:10 |vpiStmt: \_begin: (work@test), line:17:9, endln:19:4 |vpiParent: diff --git a/tests/PackageParam/PackageParam.log b/tests/PackageParam/PackageParam.log index d486947f25..b6ba87e07b 100644 --- a/tests/PackageParam/PackageParam.log +++ b/tests/PackageParam/PackageParam.log @@ -522,7 +522,7 @@ int_var 4 io_decl 11 logic_typespec 14 logic_var 1 -module 6 +module_inst 6 operation 22 package 11 param_assign 34 @@ -550,7 +550,7 @@ int_var 4 io_decl 22 logic_typespec 14 logic_var 1 -module 6 +module_inst 6 operation 22 package 11 param_assign 34 diff --git a/tests/PackageType/PackageType.log b/tests/PackageType/PackageType.log index 86d2bd6214..53cf51f9dd 100644 --- a/tests/PackageType/PackageType.log +++ b/tests/PackageType/PackageType.log @@ -413,7 +413,7 @@ int_var 4 integer_typespec 12 io_decl 11 logic_var 1 -module 2 +module_inst 2 operation 15 package 5 packed_array_typespec 4 @@ -445,7 +445,7 @@ int_var 4 integer_typespec 12 io_decl 22 logic_var 1 -module 2 +module_inst 2 operation 15 package 5 packed_array_typespec 4 diff --git a/tests/PackageTypeParam/PackageTypeParam.log b/tests/PackageTypeParam/PackageTypeParam.log index 8562b5a36e..468bcd0d60 100644 --- a/tests/PackageTypeParam/PackageTypeParam.log +++ b/tests/PackageTypeParam/PackageTypeParam.log @@ -191,7 +191,7 @@ design 1 event_control 1 logic_net 4 logic_typespec 13 -module 4 +module_inst 4 operation 1 package 3 port 6 @@ -213,7 +213,7 @@ design 1 event_control 2 logic_net 4 logic_typespec 13 -module 4 +module_inst 4 operation 2 package 3 port 9 @@ -508,14 +508,14 @@ design: (work@module_a) |vpiDefName:new_package |vpiTop:1 |uhdmallModules: -\_module: work@module_a (work@module_a), file:${SURELOG_DIR}/tests/PackageTypeParam/dut.sv, line:12:1, endln:28:21 +\_module_inst: work@module_a (work@module_a), file:${SURELOG_DIR}/tests/PackageTypeParam/dut.sv, line:12:1, endln:28:21 |vpiParent: \_design: (work@module_a) |vpiFullName:work@module_a |vpiParameter: \_type_parameter: (work@module_a.TYPE_PARAMETER), line:14:20, endln:14:34 |vpiParent: - \_module: work@module_a (work@module_a), file:${SURELOG_DIR}/tests/PackageTypeParam/dut.sv, line:12:1, endln:28:21 + \_module_inst: work@module_a (work@module_a), file:${SURELOG_DIR}/tests/PackageTypeParam/dut.sv, line:12:1, endln:28:21 |vpiName:TYPE_PARAMETER |vpiFullName:work@module_a.TYPE_PARAMETER |vpiTypespec: @@ -524,25 +524,25 @@ design: (work@module_a) |vpiNet: \_logic_net: (work@module_a.input_struct), line:17:25, endln:17:37 |vpiParent: - \_module: work@module_a (work@module_a), file:${SURELOG_DIR}/tests/PackageTypeParam/dut.sv, line:12:1, endln:28:21 + \_module_inst: work@module_a (work@module_a), file:${SURELOG_DIR}/tests/PackageTypeParam/dut.sv, line:12:1, endln:28:21 |vpiName:input_struct |vpiFullName:work@module_a.input_struct |vpiNet: \_logic_net: (work@module_a.output_struct), line:18:26, endln:18:39 |vpiParent: - \_module: work@module_a (work@module_a), file:${SURELOG_DIR}/tests/PackageTypeParam/dut.sv, line:12:1, endln:28:21 + \_module_inst: work@module_a (work@module_a), file:${SURELOG_DIR}/tests/PackageTypeParam/dut.sv, line:12:1, endln:28:21 |vpiName:output_struct |vpiFullName:work@module_a.output_struct |vpiNet: \_logic_net: (work@module_a.clk), line:19:10, endln:19:13 |vpiParent: - \_module: work@module_a (work@module_a), file:${SURELOG_DIR}/tests/PackageTypeParam/dut.sv, line:12:1, endln:28:21 + \_module_inst: work@module_a (work@module_a), file:${SURELOG_DIR}/tests/PackageTypeParam/dut.sv, line:12:1, endln:28:21 |vpiName:clk |vpiFullName:work@module_a.clk |vpiPort: \_port: (input_struct), line:17:25, endln:17:37 |vpiParent: - \_module: work@module_a (work@module_a), file:${SURELOG_DIR}/tests/PackageTypeParam/dut.sv, line:12:1, endln:28:21 + \_module_inst: work@module_a (work@module_a), file:${SURELOG_DIR}/tests/PackageTypeParam/dut.sv, line:12:1, endln:28:21 |vpiName:input_struct |vpiDirection:1 |vpiLowConn: @@ -554,7 +554,7 @@ design: (work@module_a) |vpiPort: \_port: (output_struct), line:18:26, endln:18:39 |vpiParent: - \_module: work@module_a (work@module_a), file:${SURELOG_DIR}/tests/PackageTypeParam/dut.sv, line:12:1, endln:28:21 + \_module_inst: work@module_a (work@module_a), file:${SURELOG_DIR}/tests/PackageTypeParam/dut.sv, line:12:1, endln:28:21 |vpiName:output_struct |vpiDirection:2 |vpiLowConn: @@ -566,7 +566,7 @@ design: (work@module_a) |vpiPort: \_port: (clk), line:19:10, endln:19:13 |vpiParent: - \_module: work@module_a (work@module_a), file:${SURELOG_DIR}/tests/PackageTypeParam/dut.sv, line:12:1, endln:28:21 + \_module_inst: work@module_a (work@module_a), file:${SURELOG_DIR}/tests/PackageTypeParam/dut.sv, line:12:1, endln:28:21 |vpiName:clk |vpiDirection:1 |vpiLowConn: @@ -578,7 +578,7 @@ design: (work@module_a) |vpiProcess: \_always: , line:23:3, endln:25:6 |vpiParent: - \_module: work@module_a (work@module_a), file:${SURELOG_DIR}/tests/PackageTypeParam/dut.sv, line:12:1, endln:28:21 + \_module_inst: work@module_a (work@module_a), file:${SURELOG_DIR}/tests/PackageTypeParam/dut.sv, line:12:1, endln:28:21 |vpiStmt: \_event_control: , line:23:13, endln:23:27 |vpiParent: @@ -624,7 +624,7 @@ design: (work@module_a) \_struct_net: (work@module_a.output_struct), line:18:26, endln:18:39 |vpiAlwaysType:3 |uhdmtopModules: -\_module: work@module_a (work@module_a), file:${SURELOG_DIR}/tests/PackageTypeParam/dut.sv, line:12:1, endln:28:21 +\_module_inst: work@module_a (work@module_a), file:${SURELOG_DIR}/tests/PackageTypeParam/dut.sv, line:12:1, endln:28:21 |vpiName:work@module_a |vpiParameter: \_type_parameter: (work@module_a.TYPE_PARAMETER), line:14:20, endln:14:34 @@ -633,7 +633,7 @@ design: (work@module_a) |vpiNet: \_struct_net: (work@module_a.input_struct), line:17:25, endln:17:37 |vpiParent: - \_module: work@module_a (work@module_a), file:${SURELOG_DIR}/tests/PackageTypeParam/dut.sv, line:12:1, endln:28:21 + \_module_inst: work@module_a (work@module_a), file:${SURELOG_DIR}/tests/PackageTypeParam/dut.sv, line:12:1, endln:28:21 |vpiTypespec: \_struct_typespec: (new_package::zzz), line:2:9, endln:2:15 |vpiName:input_struct @@ -641,7 +641,7 @@ design: (work@module_a) |vpiNet: \_struct_net: (work@module_a.output_struct), line:18:26, endln:18:39 |vpiParent: - \_module: work@module_a (work@module_a), file:${SURELOG_DIR}/tests/PackageTypeParam/dut.sv, line:12:1, endln:28:21 + \_module_inst: work@module_a (work@module_a), file:${SURELOG_DIR}/tests/PackageTypeParam/dut.sv, line:12:1, endln:28:21 |vpiTypespec: \_struct_typespec: (new_package::zzz), line:2:9, endln:2:15 |vpiName:output_struct @@ -649,7 +649,7 @@ design: (work@module_a) |vpiNet: \_logic_net: (work@module_a.clk), line:19:10, endln:19:13 |vpiParent: - \_module: work@module_a (work@module_a), file:${SURELOG_DIR}/tests/PackageTypeParam/dut.sv, line:12:1, endln:28:21 + \_module_inst: work@module_a (work@module_a), file:${SURELOG_DIR}/tests/PackageTypeParam/dut.sv, line:12:1, endln:28:21 |vpiTypespec: \_logic_typespec: , line:19:10, endln:19:10 |vpiName:clk @@ -658,7 +658,7 @@ design: (work@module_a) |vpiPort: \_port: (input_struct), line:17:25, endln:17:37 |vpiParent: - \_module: work@module_a (work@module_a), file:${SURELOG_DIR}/tests/PackageTypeParam/dut.sv, line:12:1, endln:28:21 + \_module_inst: work@module_a (work@module_a), file:${SURELOG_DIR}/tests/PackageTypeParam/dut.sv, line:12:1, endln:28:21 |vpiName:input_struct |vpiDirection:1 |vpiLowConn: @@ -672,11 +672,11 @@ design: (work@module_a) |vpiTypedef: \_struct_typespec: (new_package::zzz), line:2:9, endln:2:15 |vpiInstance: - \_module: work@module_a (work@module_a), file:${SURELOG_DIR}/tests/PackageTypeParam/dut.sv, line:12:1, endln:28:21 + \_module_inst: work@module_a (work@module_a), file:${SURELOG_DIR}/tests/PackageTypeParam/dut.sv, line:12:1, endln:28:21 |vpiPort: \_port: (output_struct), line:18:26, endln:18:39 |vpiParent: - \_module: work@module_a (work@module_a), file:${SURELOG_DIR}/tests/PackageTypeParam/dut.sv, line:12:1, endln:28:21 + \_module_inst: work@module_a (work@module_a), file:${SURELOG_DIR}/tests/PackageTypeParam/dut.sv, line:12:1, endln:28:21 |vpiName:output_struct |vpiDirection:2 |vpiLowConn: @@ -690,11 +690,11 @@ design: (work@module_a) |vpiTypedef: \_struct_typespec: (new_package::zzz), line:2:9, endln:2:15 |vpiInstance: - \_module: work@module_a (work@module_a), file:${SURELOG_DIR}/tests/PackageTypeParam/dut.sv, line:12:1, endln:28:21 + \_module_inst: work@module_a (work@module_a), file:${SURELOG_DIR}/tests/PackageTypeParam/dut.sv, line:12:1, endln:28:21 |vpiPort: \_port: (clk), line:19:10, endln:19:13 |vpiParent: - \_module: work@module_a (work@module_a), file:${SURELOG_DIR}/tests/PackageTypeParam/dut.sv, line:12:1, endln:28:21 + \_module_inst: work@module_a (work@module_a), file:${SURELOG_DIR}/tests/PackageTypeParam/dut.sv, line:12:1, endln:28:21 |vpiName:clk |vpiDirection:1 |vpiLowConn: @@ -708,11 +708,11 @@ design: (work@module_a) |vpiTypedef: \_logic_typespec: , line:19:10, endln:19:10 |vpiInstance: - \_module: work@module_a (work@module_a), file:${SURELOG_DIR}/tests/PackageTypeParam/dut.sv, line:12:1, endln:28:21 + \_module_inst: work@module_a (work@module_a), file:${SURELOG_DIR}/tests/PackageTypeParam/dut.sv, line:12:1, endln:28:21 |vpiProcess: \_always: , line:23:3, endln:25:6 |vpiParent: - \_module: work@module_a (work@module_a), file:${SURELOG_DIR}/tests/PackageTypeParam/dut.sv, line:12:1, endln:28:21 + \_module_inst: work@module_a (work@module_a), file:${SURELOG_DIR}/tests/PackageTypeParam/dut.sv, line:12:1, endln:28:21 |vpiStmt: \_event_control: , line:23:13, endln:23:27 |vpiParent: diff --git a/tests/PackageValue/PackageValue.log b/tests/PackageValue/PackageValue.log index 6e140d3803..78970a4c68 100644 --- a/tests/PackageValue/PackageValue.log +++ b/tests/PackageValue/PackageValue.log @@ -911,7 +911,7 @@ integer_typespec 3 io_decl 11 logic_typespec 88 logic_var 1 -module 10 +module_inst 10 named_begin 1 operation 67 package 11 @@ -947,7 +947,7 @@ integer_typespec 3 io_decl 22 logic_typespec 88 logic_var 1 -module 10 +module_inst 10 named_begin 2 operation 67 package 11 @@ -1794,7 +1794,7 @@ design: (work@prim_diff_decode) |vpiTypedef: \_enum_typespec: (prim_pkg::impl_e), line:4:3, endln:7:12 |vpiParent: - \_module: work@prim_diff_decode (work@prim_diff_decode), file:${SURELOG_DIR}/tests/PackageValue/top.sv, line:11:1, endln:33:10 + \_module_inst: work@prim_diff_decode (work@prim_diff_decode), file:${SURELOG_DIR}/tests/PackageValue/top.sv, line:11:1, endln:33:10 |vpiName:prim_pkg::impl_e |vpiInstance: \_package: prim_pkg (prim_pkg::), file:${SURELOG_DIR}/tests/PackageValue/top.sv, line:1:1, endln:9:11 @@ -3314,14 +3314,14 @@ design: (work@prim_diff_decode) \_int_typespec: |vpiSigned:1 |uhdmallModules: -\_module: work@prim_diff_decode (work@prim_diff_decode), file:${SURELOG_DIR}/tests/PackageValue/top.sv, line:11:1, endln:33:10 +\_module_inst: work@prim_diff_decode (work@prim_diff_decode), file:${SURELOG_DIR}/tests/PackageValue/top.sv, line:11:1, endln:33:10 |vpiParent: \_design: (work@prim_diff_decode) |vpiFullName:work@prim_diff_decode |vpiParameter: \_parameter: (work@prim_diff_decode.Impl), line:12:30, endln:12:34 |vpiParent: - \_module: work@prim_diff_decode (work@prim_diff_decode), file:${SURELOG_DIR}/tests/PackageValue/top.sv, line:11:1, endln:33:10 + \_module_inst: work@prim_diff_decode (work@prim_diff_decode), file:${SURELOG_DIR}/tests/PackageValue/top.sv, line:11:1, endln:33:10 |UINT:1 |vpiTypespec: \_enum_typespec: (prim_pkg::impl_e), line:4:3, endln:7:12 @@ -3330,7 +3330,7 @@ design: (work@prim_diff_decode) |vpiParamAssign: \_param_assign: , line:12:30, endln:12:58 |vpiParent: - \_module: work@prim_diff_decode (work@prim_diff_decode), file:${SURELOG_DIR}/tests/PackageValue/top.sv, line:11:1, endln:33:10 + \_module_inst: work@prim_diff_decode (work@prim_diff_decode), file:${SURELOG_DIR}/tests/PackageValue/top.sv, line:11:1, endln:33:10 |vpiRhs: \_constant: , line:12:37, endln:12:47 |vpiDecompile:1 @@ -3347,12 +3347,12 @@ design: (work@prim_diff_decode) \_import_typespec: (prim_pkg), line:15:12, endln:15:23 |vpiDefName:work@prim_diff_decode |uhdmtopModules: -\_module: work@prim_diff_decode (work@prim_diff_decode), file:${SURELOG_DIR}/tests/PackageValue/top.sv, line:11:1, endln:33:10 +\_module_inst: work@prim_diff_decode (work@prim_diff_decode), file:${SURELOG_DIR}/tests/PackageValue/top.sv, line:11:1, endln:33:10 |vpiName:work@prim_diff_decode |vpiParameter: \_parameter: (work@prim_diff_decode.Impl), line:12:30, endln:12:34 |vpiParent: - \_module: work@prim_diff_decode (work@prim_diff_decode), file:${SURELOG_DIR}/tests/PackageValue/top.sv, line:11:1, endln:33:10 + \_module_inst: work@prim_diff_decode (work@prim_diff_decode), file:${SURELOG_DIR}/tests/PackageValue/top.sv, line:11:1, endln:33:10 |UINT:1 |vpiTypespec: \_enum_typespec: (prim_pkg::impl_e), line:4:3, endln:7:12 @@ -3389,7 +3389,7 @@ design: (work@prim_diff_decode) |vpiParamAssign: \_param_assign: , line:12:30, endln:12:58 |vpiParent: - \_module: work@prim_diff_decode (work@prim_diff_decode), file:${SURELOG_DIR}/tests/PackageValue/top.sv, line:11:1, endln:33:10 + \_module_inst: work@prim_diff_decode (work@prim_diff_decode), file:${SURELOG_DIR}/tests/PackageValue/top.sv, line:11:1, endln:33:10 |vpiRhs: \_constant: , line:12:37, endln:12:58 |vpiDecompile:1 @@ -3410,7 +3410,7 @@ design: (work@prim_diff_decode) |vpiGenScopeArray: \_gen_scope_array: (work@prim_diff_decode.gen_pad_generic), line:17:5, endln:31:6 |vpiParent: - \_module: work@prim_diff_decode (work@prim_diff_decode), file:${SURELOG_DIR}/tests/PackageValue/top.sv, line:11:1, endln:33:10 + \_module_inst: work@prim_diff_decode (work@prim_diff_decode), file:${SURELOG_DIR}/tests/PackageValue/top.sv, line:11:1, endln:33:10 |vpiName:gen_pad_generic |vpiFullName:work@prim_diff_decode.gen_pad_generic |vpiGenScope: diff --git a/tests/PackedArrayAssign/PackedArrayAssign.log b/tests/PackedArrayAssign/PackedArrayAssign.log index 78ed71270e..0f42cb7e84 100644 --- a/tests/PackedArrayAssign/PackedArrayAssign.log +++ b/tests/PackedArrayAssign/PackedArrayAssign.log @@ -141,7 +141,7 @@ cont_assign 1 design 1 logic_net 3 logic_typespec 4 -module 4 +module_inst 4 operation 1 packed_array_typespec 1 packed_array_var 1 @@ -161,7 +161,7 @@ cont_assign 2 design 1 logic_net 3 logic_typespec 4 -module 4 +module_inst 4 operation 1 packed_array_typespec 1 packed_array_var 1 @@ -185,17 +185,17 @@ design: (work@top) |vpiElaborated:1 |vpiName:work@top |uhdmallModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/PackedArrayAssign/dut.sv, line:1:1, endln:8:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/PackedArrayAssign/dut.sv, line:1:1, endln:8:10 |vpiParent: \_design: (work@top) |vpiFullName:work@top |vpiTypedef: \_struct_typespec: (filter_ctl_t), line:2:12, endln:2:18 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/PackedArrayAssign/dut.sv, line:1:1, endln:8:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/PackedArrayAssign/dut.sv, line:1:1, endln:8:10 |vpiName:filter_ctl_t |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/PackedArrayAssign/dut.sv, line:1:1, endln:8:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/PackedArrayAssign/dut.sv, line:1:1, endln:8:10 |vpiPacked:1 |vpiTypespecMember: \_typespec_member: (min_v), line:3:19, endln:3:24 @@ -235,20 +235,20 @@ design: (work@top) |vpiNet: \_logic_net: (work@top.o), line:1:31, endln:1:32 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/PackedArrayAssign/dut.sv, line:1:1, endln:8:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/PackedArrayAssign/dut.sv, line:1:1, endln:8:10 |vpiName:o |vpiFullName:work@top.o |vpiNetType:36 |vpiNet: \_logic_net: (work@top.a), line:6:23, endln:6:24 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/PackedArrayAssign/dut.sv, line:1:1, endln:8:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/PackedArrayAssign/dut.sv, line:1:1, endln:8:10 |vpiName:a |vpiFullName:work@top.a |vpiPort: \_port: (o), line:1:31, endln:1:32 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/PackedArrayAssign/dut.sv, line:1:1, endln:8:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/PackedArrayAssign/dut.sv, line:1:1, endln:8:10 |vpiName:o |vpiDirection:2 |vpiLowConn: @@ -278,7 +278,7 @@ design: (work@top) |vpiContAssign: \_cont_assign: , line:7:11, endln:7:19 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/PackedArrayAssign/dut.sv, line:1:1, endln:8:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/PackedArrayAssign/dut.sv, line:1:1, endln:8:10 |vpiRhs: \_bit_select: (work@top.a), line:7:15, endln:7:19 |vpiParent: @@ -306,12 +306,12 @@ design: (work@top) |vpiActual: \_logic_net: (work@top.o), line:1:31, endln:1:32 |uhdmtopModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/PackedArrayAssign/dut.sv, line:1:1, endln:8:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/PackedArrayAssign/dut.sv, line:1:1, endln:8:10 |vpiName:work@top |vpiVariables: \_packed_array_var: (work@top.a), line:6:23, endln:6:43 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/PackedArrayAssign/dut.sv, line:1:1, endln:8:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/PackedArrayAssign/dut.sv, line:1:1, endln:8:10 |vpiName:a |vpiFullName:work@top.a |vpiVisibility:1 @@ -364,7 +364,7 @@ design: (work@top) |vpiNet: \_logic_net: (work@top.o), line:1:31, endln:1:32 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/PackedArrayAssign/dut.sv, line:1:1, endln:8:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/PackedArrayAssign/dut.sv, line:1:1, endln:8:10 |vpiTypespec: \_logic_typespec: , line:1:19, endln:1:30 |vpiRange: @@ -392,7 +392,7 @@ design: (work@top) |vpiPort: \_port: (o), line:1:31, endln:1:32 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/PackedArrayAssign/dut.sv, line:1:1, endln:8:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/PackedArrayAssign/dut.sv, line:1:1, endln:8:10 |vpiName:o |vpiDirection:2 |vpiLowConn: @@ -426,11 +426,11 @@ design: (work@top) |UINT:0 |vpiConstType:9 |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/PackedArrayAssign/dut.sv, line:1:1, endln:8:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/PackedArrayAssign/dut.sv, line:1:1, endln:8:10 |vpiContAssign: \_cont_assign: , line:7:11, endln:7:19 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/PackedArrayAssign/dut.sv, line:1:1, endln:8:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/PackedArrayAssign/dut.sv, line:1:1, endln:8:10 |vpiRhs: \_bit_select: (work@top.a), line:7:15, endln:7:19 |vpiParent: diff --git a/tests/PackedArrayBind/PackedArrayBind.log b/tests/PackedArrayBind/PackedArrayBind.log index 04f7442741..670f3e6616 100644 --- a/tests/PackedArrayBind/PackedArrayBind.log +++ b/tests/PackedArrayBind/PackedArrayBind.log @@ -165,7 +165,7 @@ design 1 hier_path 1 logic_net 2 logic_typespec 2 -module 3 +module_inst 3 packed_array_typespec 2 range 4 ref_obj 5 @@ -183,7 +183,7 @@ design 1 hier_path 2 logic_net 2 logic_typespec 2 -module 3 +module_inst 3 packed_array_typespec 2 range 4 ref_obj 10 @@ -204,17 +204,17 @@ design: (work@PreDecodeStage) |vpiElaborated:1 |vpiName:work@PreDecodeStage |uhdmallModules: -\_module: work@PreDecodeStage (work@PreDecodeStage), file:${SURELOG_DIR}/tests/PackedArrayBind/dut.sv, line:1:1, endln:26:10 +\_module_inst: work@PreDecodeStage (work@PreDecodeStage), file:${SURELOG_DIR}/tests/PackedArrayBind/dut.sv, line:1:1, endln:26:10 |vpiParent: \_design: (work@PreDecodeStage) |vpiFullName:work@PreDecodeStage |vpiTypedef: \_logic_typespec: (MSHR_IndexPath), line:3:9, endln:3:20 |vpiParent: - \_module: work@PreDecodeStage (work@PreDecodeStage), file:${SURELOG_DIR}/tests/PackedArrayBind/dut.sv, line:1:1, endln:26:10 + \_module_inst: work@PreDecodeStage (work@PreDecodeStage), file:${SURELOG_DIR}/tests/PackedArrayBind/dut.sv, line:1:1, endln:26:10 |vpiName:MSHR_IndexPath |vpiInstance: - \_module: work@PreDecodeStage (work@PreDecodeStage), file:${SURELOG_DIR}/tests/PackedArrayBind/dut.sv, line:1:1, endln:26:10 + \_module_inst: work@PreDecodeStage (work@PreDecodeStage), file:${SURELOG_DIR}/tests/PackedArrayBind/dut.sv, line:1:1, endln:26:10 |vpiRange: \_range: , line:3:15, endln:3:20 |vpiLeftRange: @@ -236,10 +236,10 @@ design: (work@PreDecodeStage) |vpiTypedef: \_struct_typespec: (MemIssueQueueEntry), line:10:9, endln:10:15 |vpiParent: - \_module: work@PreDecodeStage (work@PreDecodeStage), file:${SURELOG_DIR}/tests/PackedArrayBind/dut.sv, line:1:1, endln:26:10 + \_module_inst: work@PreDecodeStage (work@PreDecodeStage), file:${SURELOG_DIR}/tests/PackedArrayBind/dut.sv, line:1:1, endln:26:10 |vpiName:MemIssueQueueEntry |vpiInstance: - \_module: work@PreDecodeStage (work@PreDecodeStage), file:${SURELOG_DIR}/tests/PackedArrayBind/dut.sv, line:1:1, endln:26:10 + \_module_inst: work@PreDecodeStage (work@PreDecodeStage), file:${SURELOG_DIR}/tests/PackedArrayBind/dut.sv, line:1:1, endln:26:10 |vpiPacked:1 |vpiTypespecMember: \_typespec_member: (memOpInfo), line:12:15, endln:12:24 @@ -249,10 +249,10 @@ design: (work@PreDecodeStage) |vpiTypespec: \_struct_typespec: (MemOpInfo), line:5:9, endln:5:15 |vpiParent: - \_module: work@PreDecodeStage (work@PreDecodeStage), file:${SURELOG_DIR}/tests/PackedArrayBind/dut.sv, line:1:1, endln:26:10 + \_module_inst: work@PreDecodeStage (work@PreDecodeStage), file:${SURELOG_DIR}/tests/PackedArrayBind/dut.sv, line:1:1, endln:26:10 |vpiName:MemOpInfo |vpiInstance: - \_module: work@PreDecodeStage (work@PreDecodeStage), file:${SURELOG_DIR}/tests/PackedArrayBind/dut.sv, line:1:1, endln:26:10 + \_module_inst: work@PreDecodeStage (work@PreDecodeStage), file:${SURELOG_DIR}/tests/PackedArrayBind/dut.sv, line:1:1, endln:26:10 |vpiPacked:1 |vpiTypespecMember: \_typespec_member: (mshrID), line:7:20, endln:7:26 @@ -301,10 +301,10 @@ design: (work@PreDecodeStage) |vpiTypedef: \_struct_typespec: (ReplayQueueEntry), line:15:9, endln:15:15 |vpiParent: - \_module: work@PreDecodeStage (work@PreDecodeStage), file:${SURELOG_DIR}/tests/PackedArrayBind/dut.sv, line:1:1, endln:26:10 + \_module_inst: work@PreDecodeStage (work@PreDecodeStage), file:${SURELOG_DIR}/tests/PackedArrayBind/dut.sv, line:1:1, endln:26:10 |vpiName:ReplayQueueEntry |vpiInstance: - \_module: work@PreDecodeStage (work@PreDecodeStage), file:${SURELOG_DIR}/tests/PackedArrayBind/dut.sv, line:1:1, endln:26:10 + \_module_inst: work@PreDecodeStage (work@PreDecodeStage), file:${SURELOG_DIR}/tests/PackedArrayBind/dut.sv, line:1:1, endln:26:10 |vpiPacked:1 |vpiTypespecMember: \_typespec_member: (memData), line:17:36, endln:17:43 @@ -346,13 +346,13 @@ design: (work@PreDecodeStage) |vpiNet: \_logic_net: (work@PreDecodeStage.replayEntryOut), line:22:18, endln:22:32 |vpiParent: - \_module: work@PreDecodeStage (work@PreDecodeStage), file:${SURELOG_DIR}/tests/PackedArrayBind/dut.sv, line:1:1, endln:26:10 + \_module_inst: work@PreDecodeStage (work@PreDecodeStage), file:${SURELOG_DIR}/tests/PackedArrayBind/dut.sv, line:1:1, endln:26:10 |vpiName:replayEntryOut |vpiFullName:work@PreDecodeStage.replayEntryOut |vpiContAssign: \_cont_assign: , line:24:9, endln:24:60 |vpiParent: - \_module: work@PreDecodeStage (work@PreDecodeStage), file:${SURELOG_DIR}/tests/PackedArrayBind/dut.sv, line:1:1, endln:26:10 + \_module_inst: work@PreDecodeStage (work@PreDecodeStage), file:${SURELOG_DIR}/tests/PackedArrayBind/dut.sv, line:1:1, endln:26:10 |vpiRhs: \_hier_path: (replayEntryOut.memData[0].memOpInfo.mshrID), line:24:18, endln:24:60 |vpiParent: @@ -395,12 +395,12 @@ design: (work@PreDecodeStage) |vpiActual: \_logic_net: (mshrID) |uhdmtopModules: -\_module: work@PreDecodeStage (work@PreDecodeStage), file:${SURELOG_DIR}/tests/PackedArrayBind/dut.sv, line:1:1, endln:26:10 +\_module_inst: work@PreDecodeStage (work@PreDecodeStage), file:${SURELOG_DIR}/tests/PackedArrayBind/dut.sv, line:1:1, endln:26:10 |vpiName:work@PreDecodeStage |vpiVariables: \_struct_var: (work@PreDecodeStage.replayEntryOut), line:22:18, endln:22:32 |vpiParent: - \_module: work@PreDecodeStage (work@PreDecodeStage), file:${SURELOG_DIR}/tests/PackedArrayBind/dut.sv, line:1:1, endln:26:10 + \_module_inst: work@PreDecodeStage (work@PreDecodeStage), file:${SURELOG_DIR}/tests/PackedArrayBind/dut.sv, line:1:1, endln:26:10 |vpiTypespec: \_struct_typespec: (ReplayQueueEntry), line:15:9, endln:15:15 |vpiName:replayEntryOut @@ -424,7 +424,7 @@ design: (work@PreDecodeStage) |vpiContAssign: \_cont_assign: , line:24:9, endln:24:60 |vpiParent: - \_module: work@PreDecodeStage (work@PreDecodeStage), file:${SURELOG_DIR}/tests/PackedArrayBind/dut.sv, line:1:1, endln:26:10 + \_module_inst: work@PreDecodeStage (work@PreDecodeStage), file:${SURELOG_DIR}/tests/PackedArrayBind/dut.sv, line:1:1, endln:26:10 |vpiRhs: \_hier_path: (replayEntryOut.memData[0].memOpInfo.mshrID), line:24:18, endln:24:60 |vpiParent: diff --git a/tests/PackedArrayHierPath/PackedArrayHierPath.log b/tests/PackedArrayHierPath/PackedArrayHierPath.log index 248c53fd74..37d7232219 100644 --- a/tests/PackedArrayHierPath/PackedArrayHierPath.log +++ b/tests/PackedArrayHierPath/PackedArrayHierPath.log @@ -221,7 +221,7 @@ hier_path 4 int_typespec 13 int_var 2 io_decl 2 -module 2 +module_inst 2 operation 43 package 3 packed_array_typespec 4 @@ -245,7 +245,7 @@ hier_path 8 int_typespec 13 int_var 2 io_decl 4 -module 2 +module_inst 2 operation 47 package 3 packed_array_typespec 4 diff --git a/tests/PackedArrayStruct/PackedArrayStruct.log b/tests/PackedArrayStruct/PackedArrayStruct.log index 36aaa41e5e..c59aef414c 100644 --- a/tests/PackedArrayStruct/PackedArrayStruct.log +++ b/tests/PackedArrayStruct/PackedArrayStruct.log @@ -114,7 +114,7 @@ cont_assign 1 design 1 logic_net 3 logic_typespec 4 -module 4 +module_inst 4 packed_array_typespec 1 port 2 range 5 @@ -131,7 +131,7 @@ cont_assign 2 design 1 logic_net 3 logic_typespec 4 -module 4 +module_inst 4 packed_array_typespec 1 port 3 range 5 @@ -153,17 +153,17 @@ design: (work@top) |vpiElaborated:1 |vpiName:work@top |uhdmallModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/PackedArrayStruct/dut.sv, line:1:1, endln:7:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/PackedArrayStruct/dut.sv, line:1:1, endln:7:10 |vpiParent: \_design: (work@top) |vpiFullName:work@top |vpiTypedef: \_packed_array_typespec: (struct_array_t), line:5:4, endln:5:18 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/PackedArrayStruct/dut.sv, line:1:1, endln:7:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/PackedArrayStruct/dut.sv, line:1:1, endln:7:10 |vpiName:struct_array_t |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/PackedArrayStruct/dut.sv, line:1:1, endln:7:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/PackedArrayStruct/dut.sv, line:1:1, endln:7:10 |vpiRange: \_range: , line:4:6, endln:4:12 |vpiLeftRange: @@ -203,20 +203,20 @@ design: (work@top) |vpiNet: \_logic_net: (work@top.o), line:1:32, endln:1:33 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/PackedArrayStruct/dut.sv, line:1:1, endln:7:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/PackedArrayStruct/dut.sv, line:1:1, endln:7:10 |vpiName:o |vpiFullName:work@top.o |vpiNetType:36 |vpiNet: \_logic_net: (work@top.a), line:5:19, endln:5:20 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/PackedArrayStruct/dut.sv, line:1:1, endln:7:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/PackedArrayStruct/dut.sv, line:1:1, endln:7:10 |vpiName:a |vpiFullName:work@top.a |vpiPort: \_port: (o), line:1:32, endln:1:33 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/PackedArrayStruct/dut.sv, line:1:1, endln:7:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/PackedArrayStruct/dut.sv, line:1:1, endln:7:10 |vpiName:o |vpiDirection:2 |vpiLowConn: @@ -246,7 +246,7 @@ design: (work@top) |vpiContAssign: \_cont_assign: , line:6:11, endln:6:16 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/PackedArrayStruct/dut.sv, line:1:1, endln:7:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/PackedArrayStruct/dut.sv, line:1:1, endln:7:10 |vpiRhs: \_ref_obj: (work@top.a), line:6:15, endln:6:16 |vpiParent: @@ -264,12 +264,12 @@ design: (work@top) |vpiActual: \_logic_net: (work@top.o), line:1:32, endln:1:33 |uhdmtopModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/PackedArrayStruct/dut.sv, line:1:1, endln:7:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/PackedArrayStruct/dut.sv, line:1:1, endln:7:10 |vpiName:work@top |vpiVariables: \_struct_var: (work@top.a), line:5:19, endln:5:20 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/PackedArrayStruct/dut.sv, line:1:1, endln:7:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/PackedArrayStruct/dut.sv, line:1:1, endln:7:10 |vpiTypespec: \_packed_array_typespec: (struct_array_t), line:5:4, endln:5:18 |vpiName:a @@ -288,7 +288,7 @@ design: (work@top) |vpiNet: \_logic_net: (work@top.o), line:1:32, endln:1:33 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/PackedArrayStruct/dut.sv, line:1:1, endln:7:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/PackedArrayStruct/dut.sv, line:1:1, endln:7:10 |vpiTypespec: \_logic_typespec: , line:1:19, endln:1:31 |vpiRange: @@ -316,7 +316,7 @@ design: (work@top) |vpiPort: \_port: (o), line:1:32, endln:1:33 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/PackedArrayStruct/dut.sv, line:1:1, endln:7:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/PackedArrayStruct/dut.sv, line:1:1, endln:7:10 |vpiName:o |vpiDirection:2 |vpiLowConn: @@ -350,11 +350,11 @@ design: (work@top) |UINT:0 |vpiConstType:9 |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/PackedArrayStruct/dut.sv, line:1:1, endln:7:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/PackedArrayStruct/dut.sv, line:1:1, endln:7:10 |vpiContAssign: \_cont_assign: , line:6:11, endln:6:16 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/PackedArrayStruct/dut.sv, line:1:1, endln:7:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/PackedArrayStruct/dut.sv, line:1:1, endln:7:10 |vpiRhs: \_ref_obj: (work@top.a), line:6:15, endln:6:16 |vpiParent: diff --git a/tests/PackedArrayTypespec/PackedArrayTypespec.log b/tests/PackedArrayTypespec/PackedArrayTypespec.log index 572ee3d6b7..8d32e7a9d0 100644 --- a/tests/PackedArrayTypespec/PackedArrayTypespec.log +++ b/tests/PackedArrayTypespec/PackedArrayTypespec.log @@ -109,7 +109,7 @@ design 1 enum_const 3 enum_typespec 1 logic_typespec 1 -module 4 +module_inst 4 packed_array_typespec 4 range 5 === UHDM Object Stats End === @@ -121,7 +121,7 @@ design 1 enum_const 3 enum_typespec 1 logic_typespec 1 -module 4 +module_inst 4 packed_array_typespec 4 range 5 === UHDM Object Stats End === @@ -138,17 +138,17 @@ design: (work@top) |vpiElaborated:1 |vpiName:work@top |uhdmallModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/PackedArrayTypespec/dut.sv, line:1:1, endln:13:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/PackedArrayTypespec/dut.sv, line:1:1, endln:13:10 |vpiParent: \_design: (work@top) |vpiFullName:work@top |vpiTypedef: \_packed_array_typespec: (fmt_unit_types_t), line:9:11, endln:9:22 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/PackedArrayTypespec/dut.sv, line:1:1, endln:13:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/PackedArrayTypespec/dut.sv, line:1:1, endln:13:10 |vpiName:fmt_unit_types_t |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/PackedArrayTypespec/dut.sv, line:1:1, endln:13:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/PackedArrayTypespec/dut.sv, line:1:1, endln:13:10 |vpiRange: \_range: , line:9:23, endln:9:28 |vpiLeftRange: @@ -170,10 +170,10 @@ design: (work@top) |vpiElemTypespec: \_enum_typespec: (unit_type_t), line:3:4, endln:7:17 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/PackedArrayTypespec/dut.sv, line:1:1, endln:13:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/PackedArrayTypespec/dut.sv, line:1:1, endln:13:10 |vpiName:unit_type_t |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/PackedArrayTypespec/dut.sv, line:1:1, endln:13:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/PackedArrayTypespec/dut.sv, line:1:1, endln:13:10 |vpiBaseTypespec: \_logic_typespec: , line:3:17, endln:3:28 |vpiRange: @@ -215,10 +215,10 @@ design: (work@top) |vpiTypedef: \_packed_array_typespec: (opgrp_fmt_unit_types_t), line:11:11, endln:11:27 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/PackedArrayTypespec/dut.sv, line:1:1, endln:13:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/PackedArrayTypespec/dut.sv, line:1:1, endln:13:10 |vpiName:opgrp_fmt_unit_types_t |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/PackedArrayTypespec/dut.sv, line:1:1, endln:13:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/PackedArrayTypespec/dut.sv, line:1:1, endln:13:10 |vpiRange: \_range: , line:11:28, endln:11:33 |vpiLeftRange: @@ -243,7 +243,7 @@ design: (work@top) \_enum_typespec: (unit_type_t), line:3:4, endln:7:17 |vpiDefName:work@top |uhdmtopModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/PackedArrayTypespec/dut.sv, line:1:1, endln:13:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/PackedArrayTypespec/dut.sv, line:1:1, endln:13:10 |vpiName:work@top |vpiTypedef: \_packed_array_typespec: (fmt_unit_types_t), line:9:11, endln:9:22 diff --git a/tests/PackedEnum/PackedEnum.log b/tests/PackedEnum/PackedEnum.log index 2a4e5fbf8b..05814004ac 100644 --- a/tests/PackedEnum/PackedEnum.log +++ b/tests/PackedEnum/PackedEnum.log @@ -109,7 +109,7 @@ enum_const 2 enum_typespec 1 logic_net 1 logic_typespec 2 -module 4 +module_inst 4 packed_array_typespec 1 range 2 struct_typespec 1 @@ -125,7 +125,7 @@ enum_const 2 enum_typespec 1 logic_net 1 logic_typespec 2 -module 4 +module_inst 4 packed_array_typespec 1 range 2 struct_typespec 1 @@ -145,17 +145,17 @@ design: (work@dut) |vpiElaborated:1 |vpiName:work@dut |uhdmallModules: -\_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/PackedEnum/dut.sv, line:1:1, endln:8:10 +\_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/PackedEnum/dut.sv, line:1:1, endln:8:10 |vpiParent: \_design: (work@dut) |vpiFullName:work@dut |vpiTypedef: \_enum_typespec: (cstate_e), line:2:4, endln:2:47 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/PackedEnum/dut.sv, line:1:1, endln:8:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/PackedEnum/dut.sv, line:1:1, endln:8:10 |vpiName:cstate_e |vpiInstance: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/PackedEnum/dut.sv, line:1:1, endln:8:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/PackedEnum/dut.sv, line:1:1, endln:8:10 |vpiBaseTypespec: \_logic_typespec: , line:2:17, endln:2:22 |vpiEnumConst: @@ -174,16 +174,16 @@ design: (work@dut) |vpiNet: \_logic_net: (work@dut.hw2reg_wrap_t), line:7:6, endln:7:19 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/PackedEnum/dut.sv, line:1:1, endln:8:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/PackedEnum/dut.sv, line:1:1, endln:8:10 |vpiName:hw2reg_wrap_t |vpiFullName:work@dut.hw2reg_wrap_t |uhdmtopModules: -\_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/PackedEnum/dut.sv, line:1:1, endln:8:10 +\_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/PackedEnum/dut.sv, line:1:1, endln:8:10 |vpiName:work@dut |vpiVariables: \_struct_var: (work@dut.hw2reg_wrap_t), line:7:6, endln:7:19 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/PackedEnum/dut.sv, line:1:1, endln:8:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/PackedEnum/dut.sv, line:1:1, endln:8:10 |vpiTypespec: \_struct_typespec: , line:4:4, endln:4:10 |vpiPacked:1 diff --git a/tests/PackedEnumPort/PackedEnumPort.log b/tests/PackedEnumPort/PackedEnumPort.log index 4ad9a4e323..2970179412 100644 --- a/tests/PackedEnumPort/PackedEnumPort.log +++ b/tests/PackedEnumPort/PackedEnumPort.log @@ -167,7 +167,7 @@ int_typespec 6 int_var 2 logic_net 5 logic_typespec 6 -module 8 +module_inst 8 package 3 packed_array_var 1 port 6 @@ -187,7 +187,7 @@ int_typespec 6 int_var 2 logic_net 5 logic_typespec 6 -module 8 +module_inst 8 package 3 packed_array_var 1 port 9 @@ -335,7 +335,7 @@ design: (work@top) |vpiDefName:lc_ctrl_pkg |vpiTop:1 |uhdmallModules: -\_module: work@lc_ctrl_fsm (work@lc_ctrl_fsm), file:${SURELOG_DIR}/tests/PackedEnumPort/dut.sv, line:11:1, endln:16:24 +\_module_inst: work@lc_ctrl_fsm (work@lc_ctrl_fsm), file:${SURELOG_DIR}/tests/PackedEnumPort/dut.sv, line:11:1, endln:16:24 |vpiParent: \_design: (work@top) |vpiFullName:work@lc_ctrl_fsm @@ -343,14 +343,14 @@ design: (work@top) |vpiNet: \_logic_net: (work@lc_ctrl_fsm.lc_clk_byp_ack_i), line:13:15, endln:13:31 |vpiParent: - \_module: work@lc_ctrl_fsm (work@lc_ctrl_fsm), file:${SURELOG_DIR}/tests/PackedEnumPort/dut.sv, line:11:1, endln:16:24 + \_module_inst: work@lc_ctrl_fsm (work@lc_ctrl_fsm), file:${SURELOG_DIR}/tests/PackedEnumPort/dut.sv, line:11:1, endln:16:24 |vpiName:lc_clk_byp_ack_i |vpiFullName:work@lc_ctrl_fsm.lc_clk_byp_ack_i |vpiNetType:36 |vpiPort: \_port: (lc_clk_byp_ack_i), line:13:15, endln:13:31 |vpiParent: - \_module: work@lc_ctrl_fsm (work@lc_ctrl_fsm), file:${SURELOG_DIR}/tests/PackedEnumPort/dut.sv, line:11:1, endln:16:24 + \_module_inst: work@lc_ctrl_fsm (work@lc_ctrl_fsm), file:${SURELOG_DIR}/tests/PackedEnumPort/dut.sv, line:11:1, endln:16:24 |vpiName:lc_clk_byp_ack_i |vpiDirection:1 |vpiLowConn: @@ -360,7 +360,7 @@ design: (work@top) |vpiTypedef: \_logic_typespec: , line:13:9, endln:13:14 |uhdmallModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/PackedEnumPort/dut.sv, line:24:1, endln:37:16 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/PackedEnumPort/dut.sv, line:24:1, endln:37:16 |vpiParent: \_design: (work@top) |vpiFullName:work@top @@ -368,25 +368,25 @@ design: (work@top) |vpiNet: \_logic_net: (work@top.o), line:24:23, endln:24:24 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/PackedEnumPort/dut.sv, line:24:1, endln:37:16 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/PackedEnumPort/dut.sv, line:24:1, endln:37:16 |vpiName:o |vpiFullName:work@top.o |vpiNet: \_logic_net: (work@top.p), line:24:37, endln:24:38 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/PackedEnumPort/dut.sv, line:24:1, endln:37:16 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/PackedEnumPort/dut.sv, line:24:1, endln:37:16 |vpiName:p |vpiFullName:work@top.p |vpiNet: \_logic_net: (work@top.lc_clk_byp_ack), line:25:30, endln:25:44 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/PackedEnumPort/dut.sv, line:24:1, endln:37:16 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/PackedEnumPort/dut.sv, line:24:1, endln:37:16 |vpiName:lc_clk_byp_ack |vpiFullName:work@top.lc_clk_byp_ack |vpiPort: \_port: (o), line:24:23, endln:24:24 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/PackedEnumPort/dut.sv, line:24:1, endln:37:16 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/PackedEnumPort/dut.sv, line:24:1, endln:37:16 |vpiName:o |vpiDirection:2 |vpiLowConn: @@ -399,7 +399,7 @@ design: (work@top) |vpiPort: \_port: (p), line:24:37, endln:24:38 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/PackedEnumPort/dut.sv, line:24:1, endln:37:16 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/PackedEnumPort/dut.sv, line:24:1, endln:37:16 |vpiName:p |vpiDirection:2 |vpiLowConn: @@ -410,12 +410,12 @@ design: (work@top) \_int_typespec: , line:24:33, endln:24:36 |vpiSigned:1 |uhdmtopModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/PackedEnumPort/dut.sv, line:24:1, endln:37:16 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/PackedEnumPort/dut.sv, line:24:1, endln:37:16 |vpiName:work@top |vpiVariables: \_int_var: (work@top.o), line:24:23, endln:24:24 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/PackedEnumPort/dut.sv, line:24:1, endln:37:16 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/PackedEnumPort/dut.sv, line:24:1, endln:37:16 |vpiTypespec: \_int_typespec: , line:24:19, endln:24:22 |vpiSigned:1 @@ -426,7 +426,7 @@ design: (work@top) |vpiVariables: \_int_var: (work@top.p), line:24:37, endln:24:38 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/PackedEnumPort/dut.sv, line:24:1, endln:37:16 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/PackedEnumPort/dut.sv, line:24:1, endln:37:16 |vpiTypespec: \_int_typespec: , line:24:33, endln:24:36 |vpiSigned:1 @@ -437,7 +437,7 @@ design: (work@top) |vpiVariables: \_packed_array_var: (work@top.lc_clk_byp_ack), line:25:30, endln:25:44 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/PackedEnumPort/dut.sv, line:24:1, endln:37:16 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/PackedEnumPort/dut.sv, line:24:1, endln:37:16 |vpiName:lc_clk_byp_ack |vpiFullName:work@top.lc_clk_byp_ack |vpiVisibility:1 @@ -473,7 +473,7 @@ design: (work@top) |vpiPort: \_port: (o), line:24:23, endln:24:24 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/PackedEnumPort/dut.sv, line:24:1, endln:37:16 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/PackedEnumPort/dut.sv, line:24:1, endln:37:16 |vpiName:o |vpiDirection:2 |vpiLowConn: @@ -488,11 +488,11 @@ design: (work@top) \_int_typespec: , line:24:19, endln:24:22 |vpiSigned:1 |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/PackedEnumPort/dut.sv, line:24:1, endln:37:16 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/PackedEnumPort/dut.sv, line:24:1, endln:37:16 |vpiPort: \_port: (p), line:24:37, endln:24:38 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/PackedEnumPort/dut.sv, line:24:1, endln:37:16 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/PackedEnumPort/dut.sv, line:24:1, endln:37:16 |vpiName:p |vpiDirection:2 |vpiLowConn: @@ -507,11 +507,11 @@ design: (work@top) \_int_typespec: , line:24:33, endln:24:36 |vpiSigned:1 |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/PackedEnumPort/dut.sv, line:24:1, endln:37:16 - |vpiModule: - \_module: work@lc_ctrl_fsm (work@top.u_lc_ctrl_fsm), file:${SURELOG_DIR}/tests/PackedEnumPort/dut.sv, line:34:4, endln:36:6 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/PackedEnumPort/dut.sv, line:24:1, endln:37:16 + |vpiModuleInst: + \_module_inst: work@lc_ctrl_fsm (work@top.u_lc_ctrl_fsm), file:${SURELOG_DIR}/tests/PackedEnumPort/dut.sv, line:34:4, endln:36:6 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/PackedEnumPort/dut.sv, line:24:1, endln:37:16 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/PackedEnumPort/dut.sv, line:24:1, endln:37:16 |vpiName:u_lc_ctrl_fsm |vpiFullName:work@top.u_lc_ctrl_fsm |vpiDefName:work@lc_ctrl_fsm @@ -520,18 +520,18 @@ design: (work@top) |vpiNet: \_logic_net: (work@top.u_lc_ctrl_fsm.lc_clk_byp_ack_i), line:13:15, endln:13:31 |vpiParent: - \_module: work@lc_ctrl_fsm (work@top.u_lc_ctrl_fsm), file:${SURELOG_DIR}/tests/PackedEnumPort/dut.sv, line:34:4, endln:36:6 + \_module_inst: work@lc_ctrl_fsm (work@top.u_lc_ctrl_fsm), file:${SURELOG_DIR}/tests/PackedEnumPort/dut.sv, line:34:4, endln:36:6 |vpiTypespec: \_logic_typespec: , line:13:9, endln:13:14 |vpiName:lc_clk_byp_ack_i |vpiFullName:work@top.u_lc_ctrl_fsm.lc_clk_byp_ack_i |vpiNetType:36 |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/PackedEnumPort/dut.sv, line:24:1, endln:37:16 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/PackedEnumPort/dut.sv, line:24:1, endln:37:16 |vpiPort: \_port: (lc_clk_byp_ack_i), line:13:15, endln:13:31 |vpiParent: - \_module: work@lc_ctrl_fsm (work@top.u_lc_ctrl_fsm), file:${SURELOG_DIR}/tests/PackedEnumPort/dut.sv, line:34:4, endln:36:6 + \_module_inst: work@lc_ctrl_fsm (work@top.u_lc_ctrl_fsm), file:${SURELOG_DIR}/tests/PackedEnumPort/dut.sv, line:34:4, endln:36:6 |vpiName:lc_clk_byp_ack_i |vpiDirection:1 |vpiHighConn: @@ -567,7 +567,7 @@ design: (work@top) |vpiTypedef: \_logic_typespec: , line:13:9, endln:13:14 |vpiInstance: - \_module: work@lc_ctrl_fsm (work@top.u_lc_ctrl_fsm), file:${SURELOG_DIR}/tests/PackedEnumPort/dut.sv, line:34:4, endln:36:6 + \_module_inst: work@lc_ctrl_fsm (work@top.u_lc_ctrl_fsm), file:${SURELOG_DIR}/tests/PackedEnumPort/dut.sv, line:34:4, endln:36:6 =================== [ FATAL] : 0 [ SYNTAX] : 0 diff --git a/tests/PackedEnumVar/PackedEnumVar.log b/tests/PackedEnumVar/PackedEnumVar.log index 3613a57978..6a5c2bc0a0 100644 --- a/tests/PackedEnumVar/PackedEnumVar.log +++ b/tests/PackedEnumVar/PackedEnumVar.log @@ -186,7 +186,7 @@ int_typespec 3 int_var 1 logic_net 1 logic_typespec 1 -module 3 +module_inst 3 operation 2 packed_array_typespec 2 packed_array_var 2 @@ -213,7 +213,7 @@ int_typespec 3 int_var 1 logic_net 1 logic_typespec 1 -module 3 +module_inst 3 operation 3 packed_array_typespec 2 packed_array_var 4 @@ -234,17 +234,17 @@ design: (work@top) |vpiElaborated:1 |vpiName:work@top |uhdmallModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/PackedEnumVar/dut.sv, line:1:1, endln:18:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/PackedEnumVar/dut.sv, line:1:1, endln:18:10 |vpiParent: \_design: (work@top) |vpiFullName:work@top |vpiTypedef: \_enum_typespec: (sp2v_e), line:2:4, endln:5:13 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/PackedEnumVar/dut.sv, line:1:1, endln:18:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/PackedEnumVar/dut.sv, line:1:1, endln:18:10 |vpiName:sp2v_e |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/PackedEnumVar/dut.sv, line:1:1, endln:18:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/PackedEnumVar/dut.sv, line:1:1, endln:18:10 |vpiBaseTypespec: \_logic_typespec: , line:2:17, endln:2:28 |vpiRange: @@ -281,7 +281,7 @@ design: (work@top) |vpiTaskFunc: \_function: (work@top.get_BA), line:9:4, endln:13:15 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/PackedEnumVar/dut.sv, line:1:1, endln:18:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/PackedEnumVar/dut.sv, line:1:1, endln:18:10 |vpiName:get_BA |vpiFullName:work@top.get_BA |vpiVariables: @@ -387,7 +387,7 @@ design: (work@top) |vpiTypespec: \_enum_typespec: (sp2v_e), line:2:4, endln:5:13 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/PackedEnumVar/dut.sv, line:1:1, endln:18:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/PackedEnumVar/dut.sv, line:1:1, endln:18:10 |vpiStmt: \_begin: (work@top.get_BA) |vpiParent: @@ -440,17 +440,17 @@ design: (work@top) |vpiActual: \_packed_array_var: (work@top.get_BA.out), line:10:20, endln:10:23 |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/PackedEnumVar/dut.sv, line:1:1, endln:18:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/PackedEnumVar/dut.sv, line:1:1, endln:18:10 |vpiNet: \_logic_net: (work@top.o), line:8:17, endln:8:18 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/PackedEnumVar/dut.sv, line:1:1, endln:18:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/PackedEnumVar/dut.sv, line:1:1, endln:18:10 |vpiName:o |vpiFullName:work@top.o |vpiContAssign: \_cont_assign: , line:15:11, endln:15:29 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/PackedEnumVar/dut.sv, line:1:1, endln:18:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/PackedEnumVar/dut.sv, line:1:1, endln:18:10 |vpiRhs: \_operation: , line:15:15, endln:15:29 |vpiParent: @@ -475,12 +475,12 @@ design: (work@top) |vpiActual: \_int_var: (work@top.o), line:8:17, endln:8:18 |uhdmtopModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/PackedEnumVar/dut.sv, line:1:1, endln:18:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/PackedEnumVar/dut.sv, line:1:1, endln:18:10 |vpiName:work@top |vpiVariables: \_int_var: (work@top.o), line:8:17, endln:8:18 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/PackedEnumVar/dut.sv, line:1:1, endln:18:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/PackedEnumVar/dut.sv, line:1:1, endln:18:10 |vpiTypespec: \_int_typespec: , line:8:4, endln:8:7 |vpiSigned:1 @@ -494,7 +494,7 @@ design: (work@top) |vpiTaskFunc: \_function: (work@top.get_BA), line:9:4, endln:13:15 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/PackedEnumVar/dut.sv, line:1:1, endln:18:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/PackedEnumVar/dut.sv, line:1:1, endln:18:10 |vpiName:get_BA |vpiFullName:work@top.get_BA |vpiVariables: @@ -525,7 +525,7 @@ design: (work@top) |vpiReturn: \_packed_array_var: , line:9:23, endln:9:35 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/PackedEnumVar/dut.sv, line:1:1, endln:18:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/PackedEnumVar/dut.sv, line:1:1, endln:18:10 |vpiStmt: \_begin: (work@top.get_BA) |vpiParent: @@ -597,12 +597,12 @@ design: (work@top) |vpiActual: \_packed_array_var: (work@top.get_BA.out), line:10:20, endln:10:23 |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/PackedEnumVar/dut.sv, line:1:1, endln:18:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/PackedEnumVar/dut.sv, line:1:1, endln:18:10 |vpiTopModule:1 |vpiContAssign: \_cont_assign: , line:15:11, endln:15:29 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/PackedEnumVar/dut.sv, line:1:1, endln:18:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/PackedEnumVar/dut.sv, line:1:1, endln:18:10 |vpiRhs: \_operation: , line:15:15, endln:15:29 |vpiParent: diff --git a/tests/PackedUnpackedIo/PackedUnpackedIo.log b/tests/PackedUnpackedIo/PackedUnpackedIo.log index d935116444..06235bba6a 100644 --- a/tests/PackedUnpackedIo/PackedUnpackedIo.log +++ b/tests/PackedUnpackedIo/PackedUnpackedIo.log @@ -185,7 +185,7 @@ function 2 io_decl 12 logic_typespec 22 logic_var 2 -module 1 +module_inst 1 package 3 packed_array_typespec 2 range 32 @@ -199,7 +199,7 @@ function 4 io_decl 24 logic_typespec 22 logic_var 2 -module 1 +module_inst 1 package 3 packed_array_typespec 2 range 40 diff --git a/tests/ParamArray/ParamArray.log b/tests/ParamArray/ParamArray.log index c26a20020a..d7effea7d3 100644 --- a/tests/ParamArray/ParamArray.log +++ b/tests/ParamArray/ParamArray.log @@ -555,7 +555,7 @@ io_decl 11 logic_net 1 logic_typespec 14 logic_var 2 -module 11 +module_inst 11 operation 55 package 8 param_assign 20 @@ -590,7 +590,7 @@ io_decl 22 logic_net 1 logic_typespec 14 logic_var 2 -module 11 +module_inst 11 operation 55 package 8 param_assign 20 @@ -771,7 +771,7 @@ design: (work@top) |vpiElemTypespec: \_struct_typespec: (otp_ctrl_pkg::part_info_t), line:2:11, endln:2:17 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamArray/dut.sv, line:43:1, endln:50:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamArray/dut.sv, line:43:1, endln:50:10 |vpiName:otp_ctrl_pkg::part_info_t |vpiInstance: \_package: otp_ctrl_part_pkg (otp_ctrl_part_pkg::), file:${SURELOG_DIR}/tests/ParamArray/dut.sv, line:9:1, endln:27:11 @@ -1146,7 +1146,7 @@ design: (work@top) |vpiTypedef: \_enum_typespec: (otp_ctrl_part_pkg::part_idx_e), line:22:3, endln:25:16 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamArray/dut.sv, line:43:1, endln:50:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamArray/dut.sv, line:43:1, endln:50:10 |vpiName:otp_ctrl_part_pkg::part_idx_e |vpiInstance: \_package: otp_ctrl_part_pkg (otp_ctrl_part_pkg::), file:${SURELOG_DIR}/tests/ParamArray/dut.sv, line:9:1, endln:27:11 @@ -1599,14 +1599,14 @@ design: (work@top) \_int_typespec: |vpiSigned:1 |uhdmallModules: -\_module: work@otp_ctrl_lci (work@otp_ctrl_lci), file:${SURELOG_DIR}/tests/ParamArray/dut.sv, line:29:1, endln:40:10 +\_module_inst: work@otp_ctrl_lci (work@otp_ctrl_lci), file:${SURELOG_DIR}/tests/ParamArray/dut.sv, line:29:1, endln:40:10 |vpiParent: \_design: (work@top) |vpiFullName:work@otp_ctrl_lci |vpiParameter: \_parameter: (work@otp_ctrl_lci.NumPart), line:5:17, endln:5:24 |vpiParent: - \_module: work@otp_ctrl_lci (work@otp_ctrl_lci), file:${SURELOG_DIR}/tests/ParamArray/dut.sv, line:29:1, endln:40:10 + \_module_inst: work@otp_ctrl_lci (work@otp_ctrl_lci), file:${SURELOG_DIR}/tests/ParamArray/dut.sv, line:29:1, endln:40:10 |UINT:7 |vpiTypespec: \_int_typespec: , line:5:13, endln:5:16 @@ -1622,7 +1622,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@otp_ctrl_lci.Info), line:33:25, endln:33:29 |vpiParent: - \_module: work@otp_ctrl_lci (work@otp_ctrl_lci), file:${SURELOG_DIR}/tests/ParamArray/dut.sv, line:29:1, endln:40:10 + \_module_inst: work@otp_ctrl_lci (work@otp_ctrl_lci), file:${SURELOG_DIR}/tests/ParamArray/dut.sv, line:29:1, endln:40:10 |vpiTypespec: \_struct_typespec: (otp_ctrl_pkg::part_info_t), line:2:11, endln:2:17 |vpiName:Info @@ -1630,7 +1630,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@otp_ctrl_lci.NumLcOtpWords), line:36:17, endln:36:30 |vpiParent: - \_module: work@otp_ctrl_lci (work@otp_ctrl_lci), file:${SURELOG_DIR}/tests/ParamArray/dut.sv, line:29:1, endln:40:10 + \_module_inst: work@otp_ctrl_lci (work@otp_ctrl_lci), file:${SURELOG_DIR}/tests/ParamArray/dut.sv, line:29:1, endln:40:10 |vpiTypespec: \_int_typespec: , line:36:13, endln:36:16 |vpiParent: @@ -1643,7 +1643,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:5:17, endln:5:28 |vpiParent: - \_module: work@otp_ctrl_lci (work@otp_ctrl_lci), file:${SURELOG_DIR}/tests/ParamArray/dut.sv, line:29:1, endln:40:10 + \_module_inst: work@otp_ctrl_lci (work@otp_ctrl_lci), file:${SURELOG_DIR}/tests/ParamArray/dut.sv, line:29:1, endln:40:10 |vpiRhs: \_constant: , line:5:27, endln:5:28 |vpiParent: @@ -1678,7 +1678,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:33:25, endln:33:47 |vpiParent: - \_module: work@otp_ctrl_lci (work@otp_ctrl_lci), file:${SURELOG_DIR}/tests/ParamArray/dut.sv, line:29:1, endln:40:10 + \_module_inst: work@otp_ctrl_lci (work@otp_ctrl_lci), file:${SURELOG_DIR}/tests/ParamArray/dut.sv, line:29:1, endln:40:10 |vpiRhs: \_operation: , line:33:32, endln:33:47 |vpiTypespec: @@ -1697,7 +1697,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:36:17, endln:36:47 |vpiParent: - \_module: work@otp_ctrl_lci (work@otp_ctrl_lci), file:${SURELOG_DIR}/tests/ParamArray/dut.sv, line:29:1, endln:40:10 + \_module_inst: work@otp_ctrl_lci (work@otp_ctrl_lci), file:${SURELOG_DIR}/tests/ParamArray/dut.sv, line:29:1, endln:40:10 |vpiRhs: \_operation: , line:36:33, endln:36:47 |vpiOpType:23 @@ -1732,19 +1732,19 @@ design: (work@top) |vpiNet: \_logic_net: (work@otp_ctrl_lci.cnt_d), line:38:28, endln:38:33 |vpiParent: - \_module: work@otp_ctrl_lci (work@otp_ctrl_lci), file:${SURELOG_DIR}/tests/ParamArray/dut.sv, line:29:1, endln:40:10 + \_module_inst: work@otp_ctrl_lci (work@otp_ctrl_lci), file:${SURELOG_DIR}/tests/ParamArray/dut.sv, line:29:1, endln:40:10 |vpiName:cnt_d |vpiFullName:work@otp_ctrl_lci.cnt_d |vpiNetType:36 |uhdmallModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamArray/dut.sv, line:43:1, endln:50:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamArray/dut.sv, line:43:1, endln:50:10 |vpiParent: \_design: (work@top) |vpiFullName:work@top |vpiParameter: \_parameter: (work@top.NumPart), line:5:17, endln:5:24 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamArray/dut.sv, line:43:1, endln:50:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamArray/dut.sv, line:43:1, endln:50:10 |UINT:7 |vpiTypespec: \_int_typespec: , line:5:13, endln:5:16 @@ -1760,7 +1760,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.PartInfo), line:11:26, endln:11:34 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamArray/dut.sv, line:43:1, endln:50:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamArray/dut.sv, line:43:1, endln:50:10 |vpiSize:1 |vpiTypespec: \_array_typespec: @@ -1895,7 +1895,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:5:17, endln:5:28 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamArray/dut.sv, line:43:1, endln:50:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamArray/dut.sv, line:43:1, endln:50:10 |vpiRhs: \_constant: , line:5:27, endln:5:28 |vpiParent: @@ -1930,7 +1930,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:11:26, endln:20:4 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamArray/dut.sv, line:43:1, endln:50:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamArray/dut.sv, line:43:1, endln:50:10 |vpiRhs: \_operation: , line:11:47, endln:20:4 |vpiParent: @@ -2123,12 +2123,12 @@ design: (work@top) \_import_typespec: (otp_ctrl_part_pkg), line:44:10, endln:44:30 |vpiDefName:work@top |uhdmtopModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamArray/dut.sv, line:43:1, endln:50:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamArray/dut.sv, line:43:1, endln:50:10 |vpiName:work@top |vpiParameter: \_parameter: (work@top.NumPart), line:5:17, endln:5:24 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamArray/dut.sv, line:43:1, endln:50:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamArray/dut.sv, line:43:1, endln:50:10 |UINT:7 |vpiTypespec: \_int_typespec: , line:5:13, endln:5:16 @@ -2144,7 +2144,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.PartInfo), line:11:26, endln:11:34 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamArray/dut.sv, line:43:1, endln:50:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamArray/dut.sv, line:43:1, endln:50:10 |vpiSize:1 |vpiTypespec: \_array_typespec: @@ -2279,7 +2279,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:5:17, endln:5:28 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamArray/dut.sv, line:43:1, endln:50:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamArray/dut.sv, line:43:1, endln:50:10 |vpiRhs: \_constant: , line:5:27, endln:5:28 |vpiDecompile:7 @@ -2293,7 +2293,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:11:26, endln:20:4 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamArray/dut.sv, line:43:1, endln:50:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamArray/dut.sv, line:43:1, endln:50:10 |vpiRhs: \_operation: , line:11:47, endln:20:4 |vpiParent: @@ -2443,16 +2443,16 @@ design: (work@top) |vpiDefName:work@top |vpiTop:1 |vpiTopModule:1 - |vpiModule: - \_module: work@otp_ctrl_lci (work@top.u_otp_ctrl_lci), file:${SURELOG_DIR}/tests/ParamArray/dut.sv, line:46:3, endln:48:23 + |vpiModuleInst: + \_module_inst: work@otp_ctrl_lci (work@top.u_otp_ctrl_lci), file:${SURELOG_DIR}/tests/ParamArray/dut.sv, line:46:3, endln:48:23 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamArray/dut.sv, line:43:1, endln:50:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamArray/dut.sv, line:43:1, endln:50:10 |vpiName:u_otp_ctrl_lci |vpiFullName:work@top.u_otp_ctrl_lci |vpiVariables: \_logic_var: (work@top.u_otp_ctrl_lci.cnt_d), line:38:28, endln:38:33 |vpiParent: - \_module: work@otp_ctrl_lci (work@top.u_otp_ctrl_lci), file:${SURELOG_DIR}/tests/ParamArray/dut.sv, line:46:3, endln:48:23 + \_module_inst: work@otp_ctrl_lci (work@top.u_otp_ctrl_lci), file:${SURELOG_DIR}/tests/ParamArray/dut.sv, line:46:3, endln:48:23 |vpiTypespec: \_logic_typespec: , line:38:2, endln:38:27 |vpiRange: @@ -2497,7 +2497,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.u_otp_ctrl_lci.NumPart), line:5:17, endln:5:24 |vpiParent: - \_module: work@otp_ctrl_lci (work@top.u_otp_ctrl_lci), file:${SURELOG_DIR}/tests/ParamArray/dut.sv, line:46:3, endln:48:23 + \_module_inst: work@otp_ctrl_lci (work@top.u_otp_ctrl_lci), file:${SURELOG_DIR}/tests/ParamArray/dut.sv, line:46:3, endln:48:23 |UINT:7 |vpiTypespec: \_int_typespec: , line:5:13, endln:5:16 @@ -2513,7 +2513,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.u_otp_ctrl_lci.Info), line:33:25, endln:33:29 |vpiParent: - \_module: work@otp_ctrl_lci (work@top.u_otp_ctrl_lci), file:${SURELOG_DIR}/tests/ParamArray/dut.sv, line:46:3, endln:48:23 + \_module_inst: work@otp_ctrl_lci (work@top.u_otp_ctrl_lci), file:${SURELOG_DIR}/tests/ParamArray/dut.sv, line:46:3, endln:48:23 |vpiTypespec: \_struct_typespec: (otp_ctrl_pkg::part_info_t), line:2:11, endln:2:17 |vpiParent: @@ -2563,7 +2563,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.u_otp_ctrl_lci.NumLcOtpWords), line:36:17, endln:36:30 |vpiParent: - \_module: work@otp_ctrl_lci (work@top.u_otp_ctrl_lci), file:${SURELOG_DIR}/tests/ParamArray/dut.sv, line:46:3, endln:48:23 + \_module_inst: work@otp_ctrl_lci (work@top.u_otp_ctrl_lci), file:${SURELOG_DIR}/tests/ParamArray/dut.sv, line:46:3, endln:48:23 |vpiTypespec: \_int_typespec: , line:36:13, endln:36:16 |vpiParent: @@ -2576,7 +2576,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:33:25, endln:33:47 |vpiParent: - \_module: work@otp_ctrl_lci (work@top.u_otp_ctrl_lci), file:${SURELOG_DIR}/tests/ParamArray/dut.sv, line:46:3, endln:48:23 + \_module_inst: work@otp_ctrl_lci (work@top.u_otp_ctrl_lci), file:${SURELOG_DIR}/tests/ParamArray/dut.sv, line:46:3, endln:48:23 |vpiOverriden:1 |vpiRhs: \_operation: , line:17:5, endln:19:6 @@ -2596,7 +2596,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:36:17, endln:36:47 |vpiParent: - \_module: work@otp_ctrl_lci (work@top.u_otp_ctrl_lci), file:${SURELOG_DIR}/tests/ParamArray/dut.sv, line:46:3, endln:48:23 + \_module_inst: work@otp_ctrl_lci (work@top.u_otp_ctrl_lci), file:${SURELOG_DIR}/tests/ParamArray/dut.sv, line:46:3, endln:48:23 |vpiRhs: \_constant: , line:36:33, endln:36:47 |vpiDecompile:28 @@ -2610,7 +2610,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:5:17, endln:5:28 |vpiParent: - \_module: work@otp_ctrl_lci (work@top.u_otp_ctrl_lci), file:${SURELOG_DIR}/tests/ParamArray/dut.sv, line:46:3, endln:48:23 + \_module_inst: work@otp_ctrl_lci (work@top.u_otp_ctrl_lci), file:${SURELOG_DIR}/tests/ParamArray/dut.sv, line:46:3, endln:48:23 |vpiRhs: \_constant: , line:5:27, endln:5:28 |vpiDecompile:7 @@ -2629,7 +2629,7 @@ design: (work@top) |vpiDefFile:${SURELOG_DIR}/tests/ParamArray/dut.sv |vpiDefLineNo:29 |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamArray/dut.sv, line:43:1, endln:50:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamArray/dut.sv, line:43:1, endln:50:10 =================== [ FATAL] : 0 [ SYNTAX] : 0 diff --git a/tests/ParamArraySelect/ParamArraySelect.log b/tests/ParamArraySelect/ParamArraySelect.log index bb9aa54c24..0942fa4bb0 100644 --- a/tests/ParamArraySelect/ParamArraySelect.log +++ b/tests/ParamArraySelect/ParamArraySelect.log @@ -824,7 +824,7 @@ io_decl 11 logic_net 2 logic_typespec 38 logic_var 3 -module 16 +module_inst 16 operation 89 package 8 param_assign 30 @@ -862,7 +862,7 @@ io_decl 22 logic_net 2 logic_typespec 38 logic_var 3 -module 16 +module_inst 16 operation 89 package 8 param_assign 34 @@ -1079,7 +1079,7 @@ design: (work@top) |vpiElemTypespec: \_struct_typespec: (otp_ctrl_pkg::part_info_t), line:2:11, endln:2:17 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamArraySelect/dut.sv, line:51:1, endln:71:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamArraySelect/dut.sv, line:51:1, endln:71:10 |vpiName:otp_ctrl_pkg::part_info_t |vpiInstance: \_package: otp_ctrl_part_pkg (otp_ctrl_part_pkg::), file:${SURELOG_DIR}/tests/ParamArraySelect/dut.sv, line:10:1, endln:30:11 @@ -1534,7 +1534,7 @@ design: (work@top) |vpiTypedef: \_enum_typespec: (otp_ctrl_part_pkg::part_idx_e), line:25:3, endln:28:16 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamArraySelect/dut.sv, line:51:1, endln:71:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamArraySelect/dut.sv, line:51:1, endln:71:10 |vpiName:otp_ctrl_part_pkg::part_idx_e |vpiInstance: \_package: otp_ctrl_part_pkg (otp_ctrl_part_pkg::), file:${SURELOG_DIR}/tests/ParamArraySelect/dut.sv, line:10:1, endln:30:11 @@ -1987,14 +1987,14 @@ design: (work@top) \_int_typespec: |vpiSigned:1 |uhdmallModules: -\_module: work@otp_ctrl_lci (work@otp_ctrl_lci), file:${SURELOG_DIR}/tests/ParamArraySelect/dut.sv, line:33:1, endln:48:10 +\_module_inst: work@otp_ctrl_lci (work@otp_ctrl_lci), file:${SURELOG_DIR}/tests/ParamArraySelect/dut.sv, line:33:1, endln:48:10 |vpiParent: \_design: (work@top) |vpiFullName:work@otp_ctrl_lci |vpiParameter: \_parameter: (work@otp_ctrl_lci.NumPart), line:6:17, endln:6:24 |vpiParent: - \_module: work@otp_ctrl_lci (work@otp_ctrl_lci), file:${SURELOG_DIR}/tests/ParamArraySelect/dut.sv, line:33:1, endln:48:10 + \_module_inst: work@otp_ctrl_lci (work@otp_ctrl_lci), file:${SURELOG_DIR}/tests/ParamArraySelect/dut.sv, line:33:1, endln:48:10 |UINT:2 |vpiTypespec: \_int_typespec: , line:6:13, endln:6:16 @@ -2010,7 +2010,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@otp_ctrl_lci.Info), line:37:25, endln:37:29 |vpiParent: - \_module: work@otp_ctrl_lci (work@otp_ctrl_lci), file:${SURELOG_DIR}/tests/ParamArraySelect/dut.sv, line:33:1, endln:48:10 + \_module_inst: work@otp_ctrl_lci (work@otp_ctrl_lci), file:${SURELOG_DIR}/tests/ParamArraySelect/dut.sv, line:33:1, endln:48:10 |vpiTypespec: \_struct_typespec: (otp_ctrl_pkg::part_info_t), line:2:11, endln:2:17 |vpiName:Info @@ -2018,7 +2018,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@otp_ctrl_lci.NumLcOtpWords), line:40:17, endln:40:30 |vpiParent: - \_module: work@otp_ctrl_lci (work@otp_ctrl_lci), file:${SURELOG_DIR}/tests/ParamArraySelect/dut.sv, line:33:1, endln:48:10 + \_module_inst: work@otp_ctrl_lci (work@otp_ctrl_lci), file:${SURELOG_DIR}/tests/ParamArraySelect/dut.sv, line:33:1, endln:48:10 |vpiTypespec: \_int_typespec: , line:40:13, endln:40:16 |vpiParent: @@ -2031,7 +2031,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:6:17, endln:6:28 |vpiParent: - \_module: work@otp_ctrl_lci (work@otp_ctrl_lci), file:${SURELOG_DIR}/tests/ParamArraySelect/dut.sv, line:33:1, endln:48:10 + \_module_inst: work@otp_ctrl_lci (work@otp_ctrl_lci), file:${SURELOG_DIR}/tests/ParamArraySelect/dut.sv, line:33:1, endln:48:10 |vpiRhs: \_constant: , line:6:27, endln:6:28 |vpiParent: @@ -2066,7 +2066,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:37:25, endln:37:47 |vpiParent: - \_module: work@otp_ctrl_lci (work@otp_ctrl_lci), file:${SURELOG_DIR}/tests/ParamArraySelect/dut.sv, line:33:1, endln:48:10 + \_module_inst: work@otp_ctrl_lci (work@otp_ctrl_lci), file:${SURELOG_DIR}/tests/ParamArraySelect/dut.sv, line:33:1, endln:48:10 |vpiRhs: \_operation: , line:37:32, endln:37:47 |vpiTypespec: @@ -2085,7 +2085,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:40:17, endln:40:47 |vpiParent: - \_module: work@otp_ctrl_lci (work@otp_ctrl_lci), file:${SURELOG_DIR}/tests/ParamArraySelect/dut.sv, line:33:1, endln:48:10 + \_module_inst: work@otp_ctrl_lci (work@otp_ctrl_lci), file:${SURELOG_DIR}/tests/ParamArraySelect/dut.sv, line:33:1, endln:48:10 |vpiRhs: \_operation: , line:40:33, endln:40:47 |vpiOpType:23 @@ -2120,19 +2120,19 @@ design: (work@top) |vpiNet: \_logic_net: (work@otp_ctrl_lci.cnt_d), line:42:28, endln:42:33 |vpiParent: - \_module: work@otp_ctrl_lci (work@otp_ctrl_lci), file:${SURELOG_DIR}/tests/ParamArraySelect/dut.sv, line:33:1, endln:48:10 + \_module_inst: work@otp_ctrl_lci (work@otp_ctrl_lci), file:${SURELOG_DIR}/tests/ParamArraySelect/dut.sv, line:33:1, endln:48:10 |vpiName:cnt_d |vpiFullName:work@otp_ctrl_lci.cnt_d |vpiNetType:36 |uhdmallModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamArraySelect/dut.sv, line:51:1, endln:71:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamArraySelect/dut.sv, line:51:1, endln:71:10 |vpiParent: \_design: (work@top) |vpiFullName:work@top |vpiParameter: \_parameter: (work@top.NumPart), line:6:17, endln:6:24 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamArraySelect/dut.sv, line:51:1, endln:71:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamArraySelect/dut.sv, line:51:1, endln:71:10 |UINT:2 |vpiTypespec: \_int_typespec: , line:6:13, endln:6:16 @@ -2148,7 +2148,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.PartInfo), line:12:26, endln:12:34 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamArraySelect/dut.sv, line:51:1, endln:71:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamArraySelect/dut.sv, line:51:1, endln:71:10 |vpiSize:1 |vpiTypespec: \_array_typespec: @@ -2319,7 +2319,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.OtpByteAddrWidth), line:58:17, endln:58:33 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamArraySelect/dut.sv, line:51:1, endln:71:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamArraySelect/dut.sv, line:51:1, endln:71:10 |UINT:3 |vpiTypespec: \_int_typespec: , line:58:13, endln:58:16 @@ -2332,7 +2332,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:6:17, endln:6:28 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamArraySelect/dut.sv, line:51:1, endln:71:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamArraySelect/dut.sv, line:51:1, endln:71:10 |vpiRhs: \_constant: , line:6:27, endln:6:28 |vpiParent: @@ -2367,7 +2367,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:12:26, endln:23:4 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamArraySelect/dut.sv, line:51:1, endln:71:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamArraySelect/dut.sv, line:51:1, endln:71:10 |vpiRhs: \_operation: , line:12:47, endln:23:4 |vpiParent: @@ -2625,7 +2625,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:58:17, endln:58:37 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamArraySelect/dut.sv, line:51:1, endln:71:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamArraySelect/dut.sv, line:51:1, endln:71:10 |vpiRhs: \_constant: , line:58:36, endln:58:37 |vpiDecompile:3 @@ -2646,17 +2646,17 @@ design: (work@top) |vpiNet: \_logic_net: (work@top.aaa), line:59:41, endln:59:44 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamArraySelect/dut.sv, line:51:1, endln:71:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamArraySelect/dut.sv, line:51:1, endln:71:10 |vpiName:aaa |vpiFullName:work@top.aaa |vpiNetType:36 |uhdmtopModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamArraySelect/dut.sv, line:51:1, endln:71:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamArraySelect/dut.sv, line:51:1, endln:71:10 |vpiName:work@top |vpiVariables: \_logic_var: (work@top.aaa), line:59:41, endln:59:44 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamArraySelect/dut.sv, line:51:1, endln:71:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamArraySelect/dut.sv, line:51:1, endln:71:10 |vpiTypespec: \_logic_typespec: , line:59:3, endln:59:40 |vpiRange: @@ -2695,7 +2695,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.NumPart), line:6:17, endln:6:24 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamArraySelect/dut.sv, line:51:1, endln:71:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamArraySelect/dut.sv, line:51:1, endln:71:10 |UINT:2 |vpiTypespec: \_int_typespec: , line:6:13, endln:6:16 @@ -2711,7 +2711,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.PartInfo), line:12:26, endln:12:34 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamArraySelect/dut.sv, line:51:1, endln:71:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamArraySelect/dut.sv, line:51:1, endln:71:10 |vpiSize:1 |vpiTypespec: \_array_typespec: @@ -2882,7 +2882,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.OtpByteAddrWidth), line:58:17, endln:58:33 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamArraySelect/dut.sv, line:51:1, endln:71:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamArraySelect/dut.sv, line:51:1, endln:71:10 |UINT:3 |vpiTypespec: \_int_typespec: , line:58:13, endln:58:16 @@ -2895,7 +2895,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:6:17, endln:6:28 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamArraySelect/dut.sv, line:51:1, endln:71:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamArraySelect/dut.sv, line:51:1, endln:71:10 |vpiRhs: \_constant: , line:6:27, endln:6:28 |vpiDecompile:2 @@ -2909,7 +2909,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:12:26, endln:23:4 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamArraySelect/dut.sv, line:51:1, endln:71:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamArraySelect/dut.sv, line:51:1, endln:71:10 |vpiRhs: \_operation: , line:12:47, endln:23:4 |vpiParent: @@ -3123,7 +3123,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:58:17, endln:58:37 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamArraySelect/dut.sv, line:51:1, endln:71:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamArraySelect/dut.sv, line:51:1, endln:71:10 |vpiRhs: \_constant: , line:58:36, endln:58:37 |vpiDecompile:3 @@ -3143,16 +3143,16 @@ design: (work@top) |vpiDefName:work@top |vpiTop:1 |vpiTopModule:1 - |vpiModule: - \_module: work@otp_ctrl_lci (work@top.u_otp_ctrl_lci), file:${SURELOG_DIR}/tests/ParamArraySelect/dut.sv, line:54:3, endln:56:23 + |vpiModuleInst: + \_module_inst: work@otp_ctrl_lci (work@top.u_otp_ctrl_lci), file:${SURELOG_DIR}/tests/ParamArraySelect/dut.sv, line:54:3, endln:56:23 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamArraySelect/dut.sv, line:51:1, endln:71:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamArraySelect/dut.sv, line:51:1, endln:71:10 |vpiName:u_otp_ctrl_lci |vpiFullName:work@top.u_otp_ctrl_lci |vpiVariables: \_logic_var: (work@top.u_otp_ctrl_lci.cnt_d), line:42:28, endln:42:33 |vpiParent: - \_module: work@otp_ctrl_lci (work@top.u_otp_ctrl_lci), file:${SURELOG_DIR}/tests/ParamArraySelect/dut.sv, line:54:3, endln:56:23 + \_module_inst: work@otp_ctrl_lci (work@top.u_otp_ctrl_lci), file:${SURELOG_DIR}/tests/ParamArraySelect/dut.sv, line:54:3, endln:56:23 |vpiTypespec: \_logic_typespec: , line:42:2, endln:42:27 |vpiRange: @@ -3197,7 +3197,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.u_otp_ctrl_lci.NumPart), line:6:17, endln:6:24 |vpiParent: - \_module: work@otp_ctrl_lci (work@top.u_otp_ctrl_lci), file:${SURELOG_DIR}/tests/ParamArraySelect/dut.sv, line:54:3, endln:56:23 + \_module_inst: work@otp_ctrl_lci (work@top.u_otp_ctrl_lci), file:${SURELOG_DIR}/tests/ParamArraySelect/dut.sv, line:54:3, endln:56:23 |UINT:2 |vpiTypespec: \_int_typespec: , line:6:13, endln:6:16 @@ -3213,7 +3213,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.u_otp_ctrl_lci.Info), line:37:25, endln:37:29 |vpiParent: - \_module: work@otp_ctrl_lci (work@top.u_otp_ctrl_lci), file:${SURELOG_DIR}/tests/ParamArraySelect/dut.sv, line:54:3, endln:56:23 + \_module_inst: work@otp_ctrl_lci (work@top.u_otp_ctrl_lci), file:${SURELOG_DIR}/tests/ParamArraySelect/dut.sv, line:54:3, endln:56:23 |vpiTypespec: \_struct_typespec: (otp_ctrl_pkg::part_info_t), line:2:11, endln:2:17 |vpiParent: @@ -3299,7 +3299,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.u_otp_ctrl_lci.NumLcOtpWords), line:40:17, endln:40:30 |vpiParent: - \_module: work@otp_ctrl_lci (work@top.u_otp_ctrl_lci), file:${SURELOG_DIR}/tests/ParamArraySelect/dut.sv, line:54:3, endln:56:23 + \_module_inst: work@otp_ctrl_lci (work@top.u_otp_ctrl_lci), file:${SURELOG_DIR}/tests/ParamArraySelect/dut.sv, line:54:3, endln:56:23 |vpiTypespec: \_int_typespec: , line:40:13, endln:40:16 |vpiParent: @@ -3312,7 +3312,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:37:25, endln:37:47 |vpiParent: - \_module: work@otp_ctrl_lci (work@top.u_otp_ctrl_lci), file:${SURELOG_DIR}/tests/ParamArraySelect/dut.sv, line:54:3, endln:56:23 + \_module_inst: work@otp_ctrl_lci (work@top.u_otp_ctrl_lci), file:${SURELOG_DIR}/tests/ParamArraySelect/dut.sv, line:54:3, endln:56:23 |vpiOverriden:1 |vpiRhs: \_operation: , line:19:5, endln:22:6 @@ -3340,7 +3340,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:40:17, endln:40:47 |vpiParent: - \_module: work@otp_ctrl_lci (work@top.u_otp_ctrl_lci), file:${SURELOG_DIR}/tests/ParamArraySelect/dut.sv, line:54:3, endln:56:23 + \_module_inst: work@otp_ctrl_lci (work@top.u_otp_ctrl_lci), file:${SURELOG_DIR}/tests/ParamArraySelect/dut.sv, line:54:3, endln:56:23 |vpiRhs: \_constant: , line:40:33, endln:40:47 |vpiDecompile:28 @@ -3354,7 +3354,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:6:17, endln:6:28 |vpiParent: - \_module: work@otp_ctrl_lci (work@top.u_otp_ctrl_lci), file:${SURELOG_DIR}/tests/ParamArraySelect/dut.sv, line:54:3, endln:56:23 + \_module_inst: work@otp_ctrl_lci (work@top.u_otp_ctrl_lci), file:${SURELOG_DIR}/tests/ParamArraySelect/dut.sv, line:54:3, endln:56:23 |vpiRhs: \_constant: , line:6:27, endln:6:28 |vpiDecompile:2 @@ -3373,11 +3373,11 @@ design: (work@top) |vpiDefFile:${SURELOG_DIR}/tests/ParamArraySelect/dut.sv |vpiDefLineNo:33 |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamArraySelect/dut.sv, line:51:1, endln:71:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamArraySelect/dut.sv, line:51:1, endln:71:10 |vpiGenScopeArray: \_gen_scope_array: (work@top.gen_part_sel[0]), line:61:39, endln:68:6 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamArraySelect/dut.sv, line:51:1, endln:71:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamArraySelect/dut.sv, line:51:1, endln:71:10 |vpiName:gen_part_sel[0] |vpiFullName:work@top.gen_part_sel[0] |vpiGenScope: @@ -3538,7 +3538,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.gen_part_sel[1]), line:61:39, endln:68:6 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamArraySelect/dut.sv, line:51:1, endln:71:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamArraySelect/dut.sv, line:51:1, endln:71:10 |vpiName:gen_part_sel[1] |vpiFullName:work@top.gen_part_sel[1] |vpiGenScope: diff --git a/tests/ParamBitSelect/ParamBitSelect.log b/tests/ParamBitSelect/ParamBitSelect.log index b6662b0184..8fad40fd17 100644 --- a/tests/ParamBitSelect/ParamBitSelect.log +++ b/tests/ParamBitSelect/ParamBitSelect.log @@ -201,7 +201,7 @@ gen_scope 14 gen_scope_array 14 int_typespec 6 logic_typespec 4 -module 10 +module_inst 10 operation 11 param_assign 2 parameter 6 @@ -218,7 +218,7 @@ gen_scope 20 gen_scope_array 20 int_typespec 6 logic_typespec 4 -module 14 +module_inst 14 operation 11 param_assign 2 parameter 6 @@ -238,20 +238,20 @@ design: (work@dut) |vpiElaborated:1 |vpiName:work@dut |uhdmallModules: -\_module: work@GOOD (work@GOOD), file:${SURELOG_DIR}/tests/ParamBitSelect/dut.sv, line:1:1, endln:3:10 +\_module_inst: work@GOOD (work@GOOD), file:${SURELOG_DIR}/tests/ParamBitSelect/dut.sv, line:1:1, endln:3:10 |vpiParent: \_design: (work@dut) |vpiFullName:work@GOOD |vpiDefName:work@GOOD |uhdmallModules: -\_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/ParamBitSelect/dut.sv, line:5:1, endln:21:10 +\_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/ParamBitSelect/dut.sv, line:5:1, endln:21:10 |vpiParent: \_design: (work@dut) |vpiFullName:work@dut |vpiParameter: \_parameter: (work@dut.test), line:7:11, endln:7:15 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/ParamBitSelect/dut.sv, line:5:1, endln:21:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/ParamBitSelect/dut.sv, line:5:1, endln:21:10 |BIN:0011 |vpiTypespec: \_int_typespec: @@ -268,7 +268,7 @@ design: (work@dut) |vpiParamAssign: \_param_assign: , line:7:11, endln:7:25 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/ParamBitSelect/dut.sv, line:5:1, endln:21:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/ParamBitSelect/dut.sv, line:5:1, endln:21:10 |vpiRhs: \_constant: , line:7:18, endln:7:25 |vpiDecompile:4'b0011 @@ -281,12 +281,12 @@ design: (work@dut) \_parameter: (work@dut.test), line:7:11, endln:7:15 |vpiDefName:work@dut |uhdmtopModules: -\_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/ParamBitSelect/dut.sv, line:5:1, endln:21:10 +\_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/ParamBitSelect/dut.sv, line:5:1, endln:21:10 |vpiName:work@dut |vpiParameter: \_parameter: (work@dut.test), line:7:11, endln:7:15 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/ParamBitSelect/dut.sv, line:5:1, endln:21:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/ParamBitSelect/dut.sv, line:5:1, endln:21:10 |BIN:0011 |vpiTypespec: \_int_typespec: @@ -311,7 +311,7 @@ design: (work@dut) |vpiParamAssign: \_param_assign: , line:7:11, endln:7:25 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/ParamBitSelect/dut.sv, line:5:1, endln:21:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/ParamBitSelect/dut.sv, line:5:1, endln:21:10 |vpiRhs: \_constant: , line:7:18, endln:7:25 |vpiDecompile:4'b0011 @@ -336,7 +336,7 @@ design: (work@dut) |vpiGenScopeArray: \_gen_scope_array: (work@dut.genblk1[0]), line:9:32, endln:19:4 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/ParamBitSelect/dut.sv, line:5:1, endln:21:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/ParamBitSelect/dut.sv, line:5:1, endln:21:10 |vpiName:genblk1[0] |vpiFullName:work@dut.genblk1[0] |vpiGenScope: @@ -354,8 +354,8 @@ design: (work@dut) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@dut.genblk1[0].k - |vpiModule: - \_module: work@dut.genblk1[0].genblk1::MOD (work@dut.genblk1[0].genblk1.m), file:${SURELOG_DIR}/tests/ParamBitSelect/dut.sv, line:11:5, endln:11:14 + |vpiModuleInst: + \_module_inst: work@dut.genblk1[0].genblk1::MOD (work@dut.genblk1[0].genblk1.m), file:${SURELOG_DIR}/tests/ParamBitSelect/dut.sv, line:11:5, endln:11:14 |vpiParent: \_gen_scope: (work@dut.genblk1[0]) |vpiName:m @@ -372,8 +372,8 @@ design: (work@dut) |vpiParent: \_gen_scope_array: (work@dut.genblk1[0].genblk1), line:12:5, endln:16:8 |vpiFullName:work@dut.genblk1[0].genblk1 - |vpiModule: - \_module: work@GOOD (work@dut.genblk1[0].genblk1.good), file:${SURELOG_DIR}/tests/ParamBitSelect/dut.sv, line:13:8, endln:13:20 + |vpiModuleInst: + \_module_inst: work@GOOD (work@dut.genblk1[0].genblk1.good), file:${SURELOG_DIR}/tests/ParamBitSelect/dut.sv, line:13:8, endln:13:20 |vpiParent: \_gen_scope: (work@dut.genblk1[0].genblk1) |vpiName:good @@ -384,7 +384,7 @@ design: (work@dut) |vpiGenScopeArray: \_gen_scope_array: (work@dut.genblk1[1]), line:9:32, endln:19:4 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/ParamBitSelect/dut.sv, line:5:1, endln:21:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/ParamBitSelect/dut.sv, line:5:1, endln:21:10 |vpiName:genblk1[1] |vpiFullName:work@dut.genblk1[1] |vpiGenScope: @@ -402,8 +402,8 @@ design: (work@dut) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@dut.genblk1[1].k - |vpiModule: - \_module: work@dut.genblk1[1].genblk1::MOD (work@dut.genblk1[1].genblk1.m), file:${SURELOG_DIR}/tests/ParamBitSelect/dut.sv, line:11:5, endln:11:14 + |vpiModuleInst: + \_module_inst: work@dut.genblk1[1].genblk1::MOD (work@dut.genblk1[1].genblk1.m), file:${SURELOG_DIR}/tests/ParamBitSelect/dut.sv, line:11:5, endln:11:14 |vpiParent: \_gen_scope: (work@dut.genblk1[1]) |vpiName:m @@ -420,8 +420,8 @@ design: (work@dut) |vpiParent: \_gen_scope_array: (work@dut.genblk1[1].genblk1), line:12:5, endln:16:8 |vpiFullName:work@dut.genblk1[1].genblk1 - |vpiModule: - \_module: work@GOOD (work@dut.genblk1[1].genblk1.good), file:${SURELOG_DIR}/tests/ParamBitSelect/dut.sv, line:13:8, endln:13:20 + |vpiModuleInst: + \_module_inst: work@GOOD (work@dut.genblk1[1].genblk1.good), file:${SURELOG_DIR}/tests/ParamBitSelect/dut.sv, line:13:8, endln:13:20 |vpiParent: \_gen_scope: (work@dut.genblk1[1].genblk1) |vpiName:good @@ -432,7 +432,7 @@ design: (work@dut) |vpiGenScopeArray: \_gen_scope_array: (work@dut.genblk1[2]), line:9:32, endln:19:4 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/ParamBitSelect/dut.sv, line:5:1, endln:21:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/ParamBitSelect/dut.sv, line:5:1, endln:21:10 |vpiName:genblk1[2] |vpiFullName:work@dut.genblk1[2] |vpiGenScope: @@ -453,7 +453,7 @@ design: (work@dut) |vpiGenScopeArray: \_gen_scope_array: (work@dut.genblk1[3]), line:9:32, endln:19:4 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/ParamBitSelect/dut.sv, line:5:1, endln:21:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/ParamBitSelect/dut.sv, line:5:1, endln:21:10 |vpiName:genblk1[3] |vpiFullName:work@dut.genblk1[3] |vpiGenScope: diff --git a/tests/ParamByValue/ParamByValue.log b/tests/ParamByValue/ParamByValue.log index f1c1b2d506..bcb276f19e 100644 --- a/tests/ParamByValue/ParamByValue.log +++ b/tests/ParamByValue/ParamByValue.log @@ -259,7 +259,7 @@ enum_typespec 2 import_typespec 1 integer_typespec 1 logic_typespec 26 -module 13 +module_inst 13 operation 5 package 3 param_assign 16 @@ -277,7 +277,7 @@ enum_typespec 2 import_typespec 1 integer_typespec 1 logic_typespec 26 -module 13 +module_inst 13 operation 5 package 3 param_assign 16 @@ -528,7 +528,7 @@ design: (work@top) |vpiTypedef: \_enum_typespec: (lc_ctrl_state_pkg::lc_state_e), line:4:3, endln:6:16 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamByValue/dut.sv, line:20:1, endln:27:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamByValue/dut.sv, line:20:1, endln:27:10 |vpiName:lc_ctrl_state_pkg::lc_state_e |vpiInstance: \_package: lc_ctrl_state_pkg (lc_ctrl_state_pkg::), file:${SURELOG_DIR}/tests/ParamByValue/dut.sv, line:1:1, endln:7:11 @@ -562,14 +562,14 @@ design: (work@top) |vpiDefName:lc_ctrl_state_pkg |vpiTop:1 |uhdmallModules: -\_module: work@generic_flop (work@generic_flop), file:${SURELOG_DIR}/tests/ParamByValue/dut.sv, line:9:1, endln:10:10 +\_module_inst: work@generic_flop (work@generic_flop), file:${SURELOG_DIR}/tests/ParamByValue/dut.sv, line:9:1, endln:10:10 |vpiParent: \_design: (work@top) |vpiFullName:work@generic_flop |vpiParameter: \_parameter: (work@generic_flop.ResetValue), line:9:46, endln:9:56 |vpiParent: - \_module: work@generic_flop (work@generic_flop), file:${SURELOG_DIR}/tests/ParamByValue/dut.sv, line:9:1, endln:10:10 + \_module_inst: work@generic_flop (work@generic_flop), file:${SURELOG_DIR}/tests/ParamByValue/dut.sv, line:9:1, endln:10:10 |UINT:0 |vpiTypespec: \_logic_typespec: , line:9:33, endln:9:45 @@ -598,7 +598,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:9:46, endln:9:60 |vpiParent: - \_module: work@generic_flop (work@generic_flop), file:${SURELOG_DIR}/tests/ParamByValue/dut.sv, line:9:1, endln:10:10 + \_module_inst: work@generic_flop (work@generic_flop), file:${SURELOG_DIR}/tests/ParamByValue/dut.sv, line:9:1, endln:10:10 |vpiRhs: \_constant: , line:9:59, endln:9:60 |vpiDecompile:0 @@ -611,14 +611,14 @@ design: (work@top) \_parameter: (work@generic_flop.ResetValue), line:9:46, endln:9:56 |vpiDefName:work@generic_flop |uhdmallModules: -\_module: work@prim_flop (work@prim_flop), file:${SURELOG_DIR}/tests/ParamByValue/dut.sv, line:12:1, endln:18:10 +\_module_inst: work@prim_flop (work@prim_flop), file:${SURELOG_DIR}/tests/ParamByValue/dut.sv, line:12:1, endln:18:10 |vpiParent: \_design: (work@top) |vpiFullName:work@prim_flop |vpiParameter: \_parameter: (work@prim_flop.ResetValue), line:12:44, endln:12:54 |vpiParent: - \_module: work@prim_flop (work@prim_flop), file:${SURELOG_DIR}/tests/ParamByValue/dut.sv, line:12:1, endln:18:10 + \_module_inst: work@prim_flop (work@prim_flop), file:${SURELOG_DIR}/tests/ParamByValue/dut.sv, line:12:1, endln:18:10 |UINT:0 |vpiTypespec: \_logic_typespec: , line:12:31, endln:12:43 @@ -647,7 +647,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:12:44, endln:12:58 |vpiParent: - \_module: work@prim_flop (work@prim_flop), file:${SURELOG_DIR}/tests/ParamByValue/dut.sv, line:12:1, endln:18:10 + \_module_inst: work@prim_flop (work@prim_flop), file:${SURELOG_DIR}/tests/ParamByValue/dut.sv, line:12:1, endln:18:10 |vpiRhs: \_constant: , line:12:57, endln:12:58 |vpiDecompile:0 @@ -660,14 +660,14 @@ design: (work@top) \_parameter: (work@prim_flop.ResetValue), line:12:44, endln:12:54 |vpiDefName:work@prim_flop |uhdmallModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamByValue/dut.sv, line:20:1, endln:27:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamByValue/dut.sv, line:20:1, endln:27:10 |vpiParent: \_design: (work@top) |vpiFullName:work@top |vpiParameter: \_parameter: (work@top.B0), line:2:26, endln:2:28 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamByValue/dut.sv, line:20:1, endln:27:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamByValue/dut.sv, line:20:1, endln:27:10 |BIN:1110011001111001 |vpiTypespec: \_logic_typespec: , line:2:13, endln:2:25 @@ -701,7 +701,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.B1), line:3:26, endln:3:28 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamByValue/dut.sv, line:20:1, endln:27:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamByValue/dut.sv, line:20:1, endln:27:10 |BIN:1101111101101110 |vpiTypespec: \_logic_typespec: , line:3:13, endln:3:25 @@ -735,7 +735,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:2:26, endln:2:51 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamByValue/dut.sv, line:20:1, endln:27:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamByValue/dut.sv, line:20:1, endln:27:10 |vpiRhs: \_constant: , line:2:31, endln:2:51 |vpiParent: @@ -807,7 +807,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:3:26, endln:3:51 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamByValue/dut.sv, line:20:1, endln:27:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamByValue/dut.sv, line:20:1, endln:27:10 |vpiRhs: \_constant: , line:3:31, endln:3:51 |vpiParent: @@ -882,12 +882,12 @@ design: (work@top) \_import_typespec: (lc_ctrl_state_pkg), line:21:10, endln:21:30 |vpiDefName:work@top |uhdmtopModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamByValue/dut.sv, line:20:1, endln:27:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamByValue/dut.sv, line:20:1, endln:27:10 |vpiName:work@top |vpiParameter: \_parameter: (work@top.B0), line:2:26, endln:2:28 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamByValue/dut.sv, line:20:1, endln:27:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamByValue/dut.sv, line:20:1, endln:27:10 |BIN:1110011001111001 |vpiTypespec: \_logic_typespec: , line:2:13, endln:2:25 @@ -921,7 +921,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.B1), line:3:26, endln:3:28 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamByValue/dut.sv, line:20:1, endln:27:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamByValue/dut.sv, line:20:1, endln:27:10 |BIN:1101111101101110 |vpiTypespec: \_logic_typespec: , line:3:13, endln:3:25 @@ -955,7 +955,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:2:26, endln:2:51 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamByValue/dut.sv, line:20:1, endln:27:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamByValue/dut.sv, line:20:1, endln:27:10 |vpiRhs: \_constant: , line:2:31, endln:2:51 |vpiDecompile:16'b1110011001111001 @@ -967,7 +967,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:3:26, endln:3:51 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamByValue/dut.sv, line:20:1, endln:27:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamByValue/dut.sv, line:20:1, endln:27:10 |vpiRhs: \_constant: , line:3:31, endln:3:51 |vpiDecompile:16'b1101111101101110 @@ -983,16 +983,16 @@ design: (work@top) |vpiDefName:work@top |vpiTop:1 |vpiTopModule:1 - |vpiModule: - \_module: work@prim_flop (work@top.state_regs), file:${SURELOG_DIR}/tests/ParamByValue/dut.sv, line:23:3, endln:25:19 + |vpiModuleInst: + \_module_inst: work@prim_flop (work@top.state_regs), file:${SURELOG_DIR}/tests/ParamByValue/dut.sv, line:23:3, endln:25:19 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamByValue/dut.sv, line:20:1, endln:27:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamByValue/dut.sv, line:20:1, endln:27:10 |vpiName:state_regs |vpiFullName:work@top.state_regs |vpiParameter: \_parameter: (work@top.state_regs.ResetValue), line:12:44, endln:12:54 |vpiParent: - \_module: work@prim_flop (work@top.state_regs), file:${SURELOG_DIR}/tests/ParamByValue/dut.sv, line:23:3, endln:25:19 + \_module_inst: work@prim_flop (work@top.state_regs), file:${SURELOG_DIR}/tests/ParamByValue/dut.sv, line:23:3, endln:25:19 |UINT:0 |vpiTypespec: \_logic_typespec: , line:12:31, endln:12:43 @@ -1023,7 +1023,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:12:44, endln:12:58 |vpiParent: - \_module: work@prim_flop (work@top.state_regs), file:${SURELOG_DIR}/tests/ParamByValue/dut.sv, line:23:3, endln:25:19 + \_module_inst: work@prim_flop (work@top.state_regs), file:${SURELOG_DIR}/tests/ParamByValue/dut.sv, line:23:3, endln:25:19 |vpiOverriden:1 |vpiRhs: \_constant: , line:12:57, endln:12:58 @@ -1039,17 +1039,17 @@ design: (work@top) |vpiDefFile:${SURELOG_DIR}/tests/ParamByValue/dut.sv |vpiDefLineNo:12 |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamByValue/dut.sv, line:20:1, endln:27:10 - |vpiModule: - \_module: work@generic_flop (work@top.state_regs.impl_generic), file:${SURELOG_DIR}/tests/ParamByValue/dut.sv, line:14:5, endln:16:23 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamByValue/dut.sv, line:20:1, endln:27:10 + |vpiModuleInst: + \_module_inst: work@generic_flop (work@top.state_regs.impl_generic), file:${SURELOG_DIR}/tests/ParamByValue/dut.sv, line:14:5, endln:16:23 |vpiParent: - \_module: work@prim_flop (work@top.state_regs), file:${SURELOG_DIR}/tests/ParamByValue/dut.sv, line:23:3, endln:25:19 + \_module_inst: work@prim_flop (work@top.state_regs), file:${SURELOG_DIR}/tests/ParamByValue/dut.sv, line:23:3, endln:25:19 |vpiName:impl_generic |vpiFullName:work@top.state_regs.impl_generic |vpiParameter: \_parameter: (work@top.state_regs.impl_generic.ResetValue), line:9:46, endln:9:56 |vpiParent: - \_module: work@generic_flop (work@top.state_regs.impl_generic), file:${SURELOG_DIR}/tests/ParamByValue/dut.sv, line:14:5, endln:16:23 + \_module_inst: work@generic_flop (work@top.state_regs.impl_generic), file:${SURELOG_DIR}/tests/ParamByValue/dut.sv, line:14:5, endln:16:23 |UINT:0 |vpiTypespec: \_logic_typespec: , line:9:33, endln:9:45 @@ -1080,7 +1080,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:9:46, endln:9:60 |vpiParent: - \_module: work@generic_flop (work@top.state_regs.impl_generic), file:${SURELOG_DIR}/tests/ParamByValue/dut.sv, line:14:5, endln:16:23 + \_module_inst: work@generic_flop (work@top.state_regs.impl_generic), file:${SURELOG_DIR}/tests/ParamByValue/dut.sv, line:14:5, endln:16:23 |vpiOverriden:1 |vpiRhs: \_constant: , line:9:59, endln:9:60 @@ -1096,7 +1096,7 @@ design: (work@top) |vpiDefFile:${SURELOG_DIR}/tests/ParamByValue/dut.sv |vpiDefLineNo:9 |vpiInstance: - \_module: work@prim_flop (work@top.state_regs), file:${SURELOG_DIR}/tests/ParamByValue/dut.sv, line:23:3, endln:25:19 + \_module_inst: work@prim_flop (work@top.state_regs), file:${SURELOG_DIR}/tests/ParamByValue/dut.sv, line:23:3, endln:25:19 =================== [ FATAL] : 0 [ SYNTAX] : 0 diff --git a/tests/ParamCast/ParamCast.log b/tests/ParamCast/ParamCast.log index a331b57e5f..ed28b36c51 100644 --- a/tests/ParamCast/ParamCast.log +++ b/tests/ParamCast/ParamCast.log @@ -392,7 +392,7 @@ io_decl 11 logic_net 1 logic_typespec 1 logic_var 2 -module 4 +module_inst 4 operation 8 package 5 param_assign 6 @@ -420,7 +420,7 @@ io_decl 22 logic_net 1 logic_typespec 1 logic_var 2 -module 4 +module_inst 4 operation 8 package 5 param_assign 6 @@ -596,7 +596,7 @@ design: (work@otp_ctrl) |vpiTypedef: \_enum_typespec: (otp_ctrl_part_pkg::part_idx_e), line:3:1, endln:8:16 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/ParamCast/dut.sv, line:15:1, endln:18:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/ParamCast/dut.sv, line:15:1, endln:18:10 |vpiName:otp_ctrl_part_pkg::part_idx_e |vpiInstance: \_package: otp_ctrl_part_pkg (otp_ctrl_part_pkg::), file:${SURELOG_DIR}/tests/ParamCast/dut.sv, line:1:1, endln:12:11 @@ -1057,14 +1057,14 @@ design: (work@otp_ctrl) \_int_typespec: |vpiSigned:1 |uhdmallModules: -\_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/ParamCast/dut.sv, line:15:1, endln:18:10 +\_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/ParamCast/dut.sv, line:15:1, endln:18:10 |vpiParent: \_design: (work@otp_ctrl) |vpiFullName:work@otp_ctrl |vpiParameter: \_parameter: (work@otp_ctrl.NumAgents), line:10:16, endln:10:25 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/ParamCast/dut.sv, line:15:1, endln:18:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/ParamCast/dut.sv, line:15:1, endln:18:10 |UINT:3 |vpiTypespec: \_int_typespec: , line:10:12, endln:10:15 @@ -1080,7 +1080,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:10:16, endln:10:46 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/ParamCast/dut.sv, line:15:1, endln:18:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/ParamCast/dut.sv, line:15:1, endln:18:10 |vpiRhs: \_constant: , line:10:28, endln:10:46 |vpiParent: @@ -1119,17 +1119,17 @@ design: (work@otp_ctrl) |vpiNet: \_logic_net: (work@otp_ctrl.part_otp_arb_req), line:17:28, endln:17:44 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/ParamCast/dut.sv, line:15:1, endln:18:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/ParamCast/dut.sv, line:15:1, endln:18:10 |vpiName:part_otp_arb_req |vpiFullName:work@otp_ctrl.part_otp_arb_req |vpiNetType:36 |uhdmtopModules: -\_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/ParamCast/dut.sv, line:15:1, endln:18:10 +\_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/ParamCast/dut.sv, line:15:1, endln:18:10 |vpiName:work@otp_ctrl |vpiVariables: \_logic_var: (work@otp_ctrl.part_otp_arb_req), line:17:28, endln:17:44 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/ParamCast/dut.sv, line:15:1, endln:18:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/ParamCast/dut.sv, line:15:1, endln:18:10 |vpiTypespec: \_logic_typespec: , line:17:3, endln:17:24 |vpiRange: @@ -1174,7 +1174,7 @@ design: (work@otp_ctrl) |vpiParameter: \_parameter: (work@otp_ctrl.NumAgents), line:10:16, endln:10:25 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/ParamCast/dut.sv, line:15:1, endln:18:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/ParamCast/dut.sv, line:15:1, endln:18:10 |UINT:3 |vpiTypespec: \_int_typespec: , line:10:12, endln:10:15 @@ -1190,7 +1190,7 @@ design: (work@otp_ctrl) |vpiParamAssign: \_param_assign: , line:10:16, endln:10:46 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/ParamCast/dut.sv, line:15:1, endln:18:10 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/ParamCast/dut.sv, line:15:1, endln:18:10 |vpiRhs: \_constant: , line:10:28, endln:10:46 |vpiDecompile:3 diff --git a/tests/ParamComplex/ParamComplex.log b/tests/ParamComplex/ParamComplex.log index 90d8695b87..803bec56f3 100644 --- a/tests/ParamComplex/ParamComplex.log +++ b/tests/ParamComplex/ParamComplex.log @@ -482,7 +482,7 @@ int_var 4 io_decl 11 logic_typespec 16 logic_var 1 -module 9 +module_inst 9 operation 11 package 5 param_assign 6 @@ -513,7 +513,7 @@ int_var 4 io_decl 22 logic_typespec 16 logic_var 1 -module 9 +module_inst 9 operation 11 package 5 param_assign 6 @@ -1149,14 +1149,14 @@ design: (work@top) \_int_typespec: |vpiSigned:1 |uhdmallModules: -\_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/ParamComplex/dut.sv, line:17:1, endln:22:10 +\_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/ParamComplex/dut.sv, line:17:1, endln:22:10 |vpiParent: \_design: (work@top) |vpiFullName:work@dut |vpiParameter: \_parameter: (work@dut.size), line:18:19, endln:18:23 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/ParamComplex/dut.sv, line:17:1, endln:22:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/ParamComplex/dut.sv, line:17:1, endln:22:10 |UINT:0 |vpiTypespec: \_int_typespec: , line:18:15, endln:18:18 @@ -1169,7 +1169,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@dut.init), line:19:30, endln:19:34 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/ParamComplex/dut.sv, line:17:1, endln:22:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/ParamComplex/dut.sv, line:17:1, endln:22:10 |BIN:0 |vpiTypespec: \_bit_typespec: , line:19:15, endln:19:29 @@ -1209,7 +1209,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:18:19, endln:18:27 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/ParamComplex/dut.sv, line:17:1, endln:22:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/ParamComplex/dut.sv, line:17:1, endln:22:10 |vpiRhs: \_constant: , line:18:26, endln:18:27 |vpiDecompile:0 @@ -1223,7 +1223,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:19:30, endln:19:39 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/ParamComplex/dut.sv, line:17:1, endln:22:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/ParamComplex/dut.sv, line:17:1, endln:22:10 |vpiRhs: \_constant: , line:19:37, endln:19:39 |vpiDecompile:'0 @@ -1236,14 +1236,14 @@ design: (work@top) \_parameter: (work@dut.init), line:19:30, endln:19:34 |vpiDefName:work@dut |uhdmallModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamComplex/dut.sv, line:9:1, endln:15:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamComplex/dut.sv, line:9:1, endln:15:10 |vpiParent: \_design: (work@top) |vpiFullName:work@top |vpiParameter: \_parameter: (work@top.init_val), line:10:30, endln:10:38 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamComplex/dut.sv, line:9:1, endln:15:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamComplex/dut.sv, line:9:1, endln:15:10 |vpiTypespec: \_struct_typespec: (pkg::complex_t), line:2:11, endln:2:17 |vpiLocalParam:1 @@ -1252,7 +1252,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:10:30, endln:10:58 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamComplex/dut.sv, line:9:1, endln:15:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamComplex/dut.sv, line:9:1, endln:15:10 |vpiRhs: \_operation: , line:10:41, endln:10:58 |vpiOpType:75 @@ -1282,12 +1282,12 @@ design: (work@top) \_parameter: (work@top.init_val), line:10:30, endln:10:38 |vpiDefName:work@top |uhdmtopModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamComplex/dut.sv, line:9:1, endln:15:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamComplex/dut.sv, line:9:1, endln:15:10 |vpiName:work@top |vpiParameter: \_parameter: (work@top.init_val), line:10:30, endln:10:38 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamComplex/dut.sv, line:9:1, endln:15:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamComplex/dut.sv, line:9:1, endln:15:10 |vpiTypespec: \_struct_typespec: (pkg::complex_t), line:2:11, endln:2:17 |vpiParent: @@ -1354,7 +1354,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:10:30, endln:10:58 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamComplex/dut.sv, line:9:1, endln:15:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamComplex/dut.sv, line:9:1, endln:15:10 |vpiRhs: \_operation: , line:10:41, endln:10:58 |vpiParent: @@ -1441,16 +1441,16 @@ design: (work@top) |vpiDefName:work@top |vpiTop:1 |vpiTopModule:1 - |vpiModule: - \_module: work@dut (work@top.asgn0), file:${SURELOG_DIR}/tests/ParamComplex/dut.sv, line:11:4, endln:14:16 + |vpiModuleInst: + \_module_inst: work@dut (work@top.asgn0), file:${SURELOG_DIR}/tests/ParamComplex/dut.sv, line:11:4, endln:14:16 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamComplex/dut.sv, line:9:1, endln:15:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamComplex/dut.sv, line:9:1, endln:15:10 |vpiName:asgn0 |vpiFullName:work@top.asgn0 |vpiParameter: \_parameter: (work@top.asgn0.size), line:18:19, endln:18:23 |vpiParent: - \_module: work@dut (work@top.asgn0), file:${SURELOG_DIR}/tests/ParamComplex/dut.sv, line:11:4, endln:14:16 + \_module_inst: work@dut (work@top.asgn0), file:${SURELOG_DIR}/tests/ParamComplex/dut.sv, line:11:4, endln:14:16 |UINT:0 |vpiTypespec: \_int_typespec: , line:18:15, endln:18:18 @@ -1463,7 +1463,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.asgn0.init), line:19:30, endln:19:34 |vpiParent: - \_module: work@dut (work@top.asgn0), file:${SURELOG_DIR}/tests/ParamComplex/dut.sv, line:11:4, endln:14:16 + \_module_inst: work@dut (work@top.asgn0), file:${SURELOG_DIR}/tests/ParamComplex/dut.sv, line:11:4, endln:14:16 |BIN:0 |vpiTypespec: \_bit_typespec: , line:19:15, endln:19:29 @@ -1508,7 +1508,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:18:19, endln:18:27 |vpiParent: - \_module: work@dut (work@top.asgn0), file:${SURELOG_DIR}/tests/ParamComplex/dut.sv, line:11:4, endln:14:16 + \_module_inst: work@dut (work@top.asgn0), file:${SURELOG_DIR}/tests/ParamComplex/dut.sv, line:11:4, endln:14:16 |vpiOverriden:1 |vpiRhs: \_constant: , line:18:26, endln:18:27 @@ -1523,7 +1523,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:19:30, endln:19:39 |vpiParent: - \_module: work@dut (work@top.asgn0), file:${SURELOG_DIR}/tests/ParamComplex/dut.sv, line:11:4, endln:14:16 + \_module_inst: work@dut (work@top.asgn0), file:${SURELOG_DIR}/tests/ParamComplex/dut.sv, line:11:4, endln:14:16 |vpiOverriden:1 |vpiRhs: \_operation: , line:13:15, endln:13:25 @@ -1615,7 +1615,7 @@ design: (work@top) |vpiDefFile:${SURELOG_DIR}/tests/ParamComplex/dut.sv |vpiDefLineNo:17 |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamComplex/dut.sv, line:9:1, endln:15:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamComplex/dut.sv, line:9:1, endln:15:10 =================== [ FATAL] : 0 [ SYNTAX] : 0 diff --git a/tests/ParamComplexVerilator/ParamComplexVerilator.log b/tests/ParamComplexVerilator/ParamComplexVerilator.log index 6efbe5a7d2..65ebd8dc8c 100644 --- a/tests/ParamComplexVerilator/ParamComplexVerilator.log +++ b/tests/ParamComplexVerilator/ParamComplexVerilator.log @@ -482,7 +482,7 @@ int_var 4 io_decl 11 logic_typespec 12 logic_var 1 -module 8 +module_inst 8 operation 9 package 5 param_assign 6 @@ -513,7 +513,7 @@ int_var 4 io_decl 22 logic_typespec 12 logic_var 1 -module 8 +module_inst 8 operation 9 package 5 param_assign 6 @@ -1149,14 +1149,14 @@ design: (work@top) \_int_typespec: |vpiSigned:1 |uhdmallModules: -\_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/ParamComplexVerilator/dut.sv, line:17:1, endln:22:10 +\_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/ParamComplexVerilator/dut.sv, line:17:1, endln:22:10 |vpiParent: \_design: (work@top) |vpiFullName:work@dut |vpiParameter: \_parameter: (work@dut.size), line:18:19, endln:18:23 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/ParamComplexVerilator/dut.sv, line:17:1, endln:22:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/ParamComplexVerilator/dut.sv, line:17:1, endln:22:10 |UINT:0 |vpiTypespec: \_int_typespec: , line:18:15, endln:18:18 @@ -1169,7 +1169,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@dut.init), line:19:30, endln:19:34 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/ParamComplexVerilator/dut.sv, line:17:1, endln:22:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/ParamComplexVerilator/dut.sv, line:17:1, endln:22:10 |BIN:0 |vpiTypespec: \_bit_typespec: , line:19:15, endln:19:29 @@ -1209,7 +1209,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:18:19, endln:18:27 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/ParamComplexVerilator/dut.sv, line:17:1, endln:22:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/ParamComplexVerilator/dut.sv, line:17:1, endln:22:10 |vpiRhs: \_constant: , line:18:26, endln:18:27 |vpiDecompile:0 @@ -1223,7 +1223,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:19:30, endln:19:39 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/ParamComplexVerilator/dut.sv, line:17:1, endln:22:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/ParamComplexVerilator/dut.sv, line:17:1, endln:22:10 |vpiRhs: \_constant: , line:19:37, endln:19:39 |vpiDecompile:'0 @@ -1236,14 +1236,14 @@ design: (work@top) \_parameter: (work@dut.init), line:19:30, endln:19:34 |vpiDefName:work@dut |uhdmallModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamComplexVerilator/dut.sv, line:9:1, endln:15:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamComplexVerilator/dut.sv, line:9:1, endln:15:10 |vpiParent: \_design: (work@top) |vpiFullName:work@top |vpiParameter: \_parameter: (work@top.init_val), line:10:30, endln:10:38 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamComplexVerilator/dut.sv, line:9:1, endln:15:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamComplexVerilator/dut.sv, line:9:1, endln:15:10 |vpiTypespec: \_struct_typespec: (pkg::complex_t), line:2:11, endln:2:17 |vpiLocalParam:1 @@ -1252,7 +1252,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:10:30, endln:10:58 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamComplexVerilator/dut.sv, line:9:1, endln:15:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamComplexVerilator/dut.sv, line:9:1, endln:15:10 |vpiRhs: \_operation: , line:10:41, endln:10:58 |vpiOpType:75 @@ -1282,12 +1282,12 @@ design: (work@top) \_parameter: (work@top.init_val), line:10:30, endln:10:38 |vpiDefName:work@top |uhdmtopModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamComplexVerilator/dut.sv, line:9:1, endln:15:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamComplexVerilator/dut.sv, line:9:1, endln:15:10 |vpiName:work@top |vpiParameter: \_parameter: (work@top.init_val), line:10:30, endln:10:38 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamComplexVerilator/dut.sv, line:9:1, endln:15:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamComplexVerilator/dut.sv, line:9:1, endln:15:10 |vpiTypespec: \_struct_typespec: (pkg::complex_t), line:2:11, endln:2:17 |vpiParent: @@ -1354,7 +1354,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:10:30, endln:10:58 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamComplexVerilator/dut.sv, line:9:1, endln:15:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamComplexVerilator/dut.sv, line:9:1, endln:15:10 |vpiRhs: \_operation: , line:10:41, endln:10:58 |vpiParent: @@ -1441,16 +1441,16 @@ design: (work@top) |vpiDefName:work@top |vpiTop:1 |vpiTopModule:1 - |vpiModule: - \_module: work@dut (work@top.asgn0), file:${SURELOG_DIR}/tests/ParamComplexVerilator/dut.sv, line:11:4, endln:14:16 + |vpiModuleInst: + \_module_inst: work@dut (work@top.asgn0), file:${SURELOG_DIR}/tests/ParamComplexVerilator/dut.sv, line:11:4, endln:14:16 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamComplexVerilator/dut.sv, line:9:1, endln:15:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamComplexVerilator/dut.sv, line:9:1, endln:15:10 |vpiName:asgn0 |vpiFullName:work@top.asgn0 |vpiParameter: \_parameter: (work@top.asgn0.size), line:18:19, endln:18:23 |vpiParent: - \_module: work@dut (work@top.asgn0), file:${SURELOG_DIR}/tests/ParamComplexVerilator/dut.sv, line:11:4, endln:14:16 + \_module_inst: work@dut (work@top.asgn0), file:${SURELOG_DIR}/tests/ParamComplexVerilator/dut.sv, line:11:4, endln:14:16 |UINT:0 |vpiTypespec: \_int_typespec: , line:18:15, endln:18:18 @@ -1463,7 +1463,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.asgn0.init), line:19:30, endln:19:34 |vpiParent: - \_module: work@dut (work@top.asgn0), file:${SURELOG_DIR}/tests/ParamComplexVerilator/dut.sv, line:11:4, endln:14:16 + \_module_inst: work@dut (work@top.asgn0), file:${SURELOG_DIR}/tests/ParamComplexVerilator/dut.sv, line:11:4, endln:14:16 |BIN:0 |vpiTypespec: \_bit_typespec: , line:19:15, endln:19:29 @@ -1508,7 +1508,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:18:19, endln:18:27 |vpiParent: - \_module: work@dut (work@top.asgn0), file:${SURELOG_DIR}/tests/ParamComplexVerilator/dut.sv, line:11:4, endln:14:16 + \_module_inst: work@dut (work@top.asgn0), file:${SURELOG_DIR}/tests/ParamComplexVerilator/dut.sv, line:11:4, endln:14:16 |vpiOverriden:1 |vpiRhs: \_constant: , line:18:26, endln:18:27 @@ -1523,7 +1523,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:19:30, endln:19:39 |vpiParent: - \_module: work@dut (work@top.asgn0), file:${SURELOG_DIR}/tests/ParamComplexVerilator/dut.sv, line:11:4, endln:14:16 + \_module_inst: work@dut (work@top.asgn0), file:${SURELOG_DIR}/tests/ParamComplexVerilator/dut.sv, line:11:4, endln:14:16 |vpiOverriden:1 |vpiRhs: \_operation: , line:13:15, endln:13:25 @@ -1541,7 +1541,7 @@ design: (work@top) |vpiDefFile:${SURELOG_DIR}/tests/ParamComplexVerilator/dut.sv |vpiDefLineNo:17 |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamComplexVerilator/dut.sv, line:9:1, endln:15:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamComplexVerilator/dut.sv, line:9:1, endln:15:10 =================== [ FATAL] : 0 [ SYNTAX] : 0 diff --git a/tests/ParamConcat/ParamConcat.log b/tests/ParamConcat/ParamConcat.log index 5b4249f5e9..4d92445494 100644 --- a/tests/ParamConcat/ParamConcat.log +++ b/tests/ParamConcat/ParamConcat.log @@ -428,7 +428,7 @@ int_var 4 io_decl 11 logic_typespec 14 logic_var 1 -module 8 +module_inst 8 operation 9 package 2 param_assign 4 @@ -458,7 +458,7 @@ int_var 4 io_decl 22 logic_typespec 14 logic_var 1 -module 8 +module_inst 8 operation 9 package 2 param_assign 4 @@ -958,14 +958,14 @@ design: (work@top) \_int_typespec: |vpiSigned:1 |uhdmallModules: -\_module: work@ibex_csr (work@ibex_csr), file:${SURELOG_DIR}/tests/ParamConcat/dut.sv, line:1:1, endln:4:10 +\_module_inst: work@ibex_csr (work@ibex_csr), file:${SURELOG_DIR}/tests/ParamConcat/dut.sv, line:1:1, endln:4:10 |vpiParent: \_design: (work@top) |vpiFullName:work@ibex_csr |vpiParameter: \_parameter: (work@ibex_csr.ResetValue), line:2:25, endln:2:35 |vpiParent: - \_module: work@ibex_csr (work@ibex_csr), file:${SURELOG_DIR}/tests/ParamConcat/dut.sv, line:1:1, endln:4:10 + \_module_inst: work@ibex_csr (work@ibex_csr), file:${SURELOG_DIR}/tests/ParamConcat/dut.sv, line:1:1, endln:4:10 |BIN:0 |vpiTypespec: \_bit_typespec: , line:2:15, endln:2:24 @@ -995,7 +995,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:2:25, endln:2:40 |vpiParent: - \_module: work@ibex_csr (work@ibex_csr), file:${SURELOG_DIR}/tests/ParamConcat/dut.sv, line:1:1, endln:4:10 + \_module_inst: work@ibex_csr (work@ibex_csr), file:${SURELOG_DIR}/tests/ParamConcat/dut.sv, line:1:1, endln:4:10 |vpiRhs: \_constant: , line:2:38, endln:2:40 |vpiDecompile:'0 @@ -1008,21 +1008,21 @@ design: (work@top) \_parameter: (work@ibex_csr.ResetValue), line:2:25, endln:2:35 |vpiDefName:work@ibex_csr |uhdmallModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamConcat/dut.sv, line:6:1, endln:19:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamConcat/dut.sv, line:6:1, endln:19:10 |vpiParent: \_design: (work@top) |vpiFullName:work@top |vpiParameter: \_parameter: (work@top.MSTATUS_RST_VAL), line:14:23, endln:14:38 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamConcat/dut.sv, line:6:1, endln:19:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamConcat/dut.sv, line:6:1, endln:19:10 |vpiTypespec: \_struct_typespec: (status_t), line:9:11, endln:9:17 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamConcat/dut.sv, line:6:1, endln:19:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamConcat/dut.sv, line:6:1, endln:19:10 |vpiName:status_t |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamConcat/dut.sv, line:6:1, endln:19:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamConcat/dut.sv, line:6:1, endln:19:10 |vpiPacked:1 |vpiTypespecMember: \_typespec_member: (mie), line:10:11, endln:10:14 @@ -1058,7 +1058,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:14:23, endln:15:53 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamConcat/dut.sv, line:6:1, endln:19:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamConcat/dut.sv, line:6:1, endln:19:10 |vpiRhs: \_operation: , line:14:41, endln:15:53 |vpiOpType:75 @@ -1090,19 +1090,19 @@ design: (work@top) \_struct_typespec: (status_t), line:9:11, endln:9:17 |vpiDefName:work@top |uhdmtopModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamConcat/dut.sv, line:6:1, endln:19:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamConcat/dut.sv, line:6:1, endln:19:10 |vpiName:work@top |vpiParameter: \_parameter: (work@top.MSTATUS_RST_VAL), line:14:23, endln:14:38 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamConcat/dut.sv, line:6:1, endln:19:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamConcat/dut.sv, line:6:1, endln:19:10 |vpiTypespec: \_struct_typespec: (status_t), line:9:11, endln:9:17 |vpiParent: \_parameter: (work@top.MSTATUS_RST_VAL), line:14:23, endln:14:38 |vpiName:status_t |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamConcat/dut.sv, line:6:1, endln:19:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamConcat/dut.sv, line:6:1, endln:19:10 |vpiPacked:1 |vpiTypespecMember: \_typespec_member: (mie), line:10:11, endln:10:14 @@ -1138,7 +1138,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:14:23, endln:15:53 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamConcat/dut.sv, line:6:1, endln:19:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamConcat/dut.sv, line:6:1, endln:19:10 |vpiRhs: \_operation: , line:14:41, endln:15:53 |vpiParent: @@ -1201,16 +1201,16 @@ design: (work@top) |vpiDefName:work@top |vpiTop:1 |vpiTopModule:1 - |vpiModule: - \_module: work@ibex_csr (work@top.u_mstatus_csr), file:${SURELOG_DIR}/tests/ParamConcat/dut.sv, line:16:3, endln:18:21 + |vpiModuleInst: + \_module_inst: work@ibex_csr (work@top.u_mstatus_csr), file:${SURELOG_DIR}/tests/ParamConcat/dut.sv, line:16:3, endln:18:21 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamConcat/dut.sv, line:6:1, endln:19:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamConcat/dut.sv, line:6:1, endln:19:10 |vpiName:u_mstatus_csr |vpiFullName:work@top.u_mstatus_csr |vpiParameter: \_parameter: (work@top.u_mstatus_csr.ResetValue), line:2:25, endln:2:35 |vpiParent: - \_module: work@ibex_csr (work@top.u_mstatus_csr), file:${SURELOG_DIR}/tests/ParamConcat/dut.sv, line:16:3, endln:18:21 + \_module_inst: work@ibex_csr (work@top.u_mstatus_csr), file:${SURELOG_DIR}/tests/ParamConcat/dut.sv, line:16:3, endln:18:21 |BIN:0 |vpiTypespec: \_bit_typespec: , line:2:15, endln:2:24 @@ -1242,7 +1242,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:2:25, endln:2:40 |vpiParent: - \_module: work@ibex_csr (work@top.u_mstatus_csr), file:${SURELOG_DIR}/tests/ParamConcat/dut.sv, line:16:3, endln:18:21 + \_module_inst: work@ibex_csr (work@top.u_mstatus_csr), file:${SURELOG_DIR}/tests/ParamConcat/dut.sv, line:16:3, endln:18:21 |vpiOverriden:1 |vpiRhs: \_operation: , line:17:18, endln:17:35 @@ -1308,7 +1308,7 @@ design: (work@top) |vpiDefFile:${SURELOG_DIR}/tests/ParamConcat/dut.sv |vpiDefLineNo:1 |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamConcat/dut.sv, line:6:1, endln:19:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamConcat/dut.sv, line:6:1, endln:19:10 =================== [ FATAL] : 0 [ SYNTAX] : 0 diff --git a/tests/ParamConst/ParamConst.log b/tests/ParamConst/ParamConst.log index 748c21f45b..31f4fbfb3b 100644 --- a/tests/ParamConst/ParamConst.log +++ b/tests/ParamConst/ParamConst.log @@ -526,7 +526,7 @@ integer_typespec 1 io_decl 11 logic_typespec 26 logic_var 1 -module 13 +module_inst 13 operation 5 package 5 param_assign 16 @@ -554,7 +554,7 @@ integer_typespec 1 io_decl 22 logic_typespec 26 logic_var 1 -module 13 +module_inst 13 operation 5 package 5 param_assign 16 @@ -851,7 +851,7 @@ design: (work@top) |vpiTypedef: \_enum_typespec: (lc_ctrl_state_pkg::lc_state_e), line:4:3, endln:6:16 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamConst/dut.sv, line:18:1, endln:25:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamConst/dut.sv, line:18:1, endln:25:10 |vpiName:lc_ctrl_state_pkg::lc_state_e |vpiInstance: \_package: lc_ctrl_state_pkg (lc_ctrl_state_pkg::), file:${SURELOG_DIR}/tests/ParamConst/dut.sv, line:1:1, endln:7:11 @@ -1315,14 +1315,14 @@ design: (work@top) \_int_typespec: |vpiSigned:1 |uhdmallModules: -\_module: work@generic_flop (work@generic_flop), file:${SURELOG_DIR}/tests/ParamConst/dut.sv, line:9:1, endln:10:10 +\_module_inst: work@generic_flop (work@generic_flop), file:${SURELOG_DIR}/tests/ParamConst/dut.sv, line:9:1, endln:10:10 |vpiParent: \_design: (work@top) |vpiFullName:work@generic_flop |vpiParameter: \_parameter: (work@generic_flop.ResetValue), line:9:45, endln:9:55 |vpiParent: - \_module: work@generic_flop (work@generic_flop), file:${SURELOG_DIR}/tests/ParamConst/dut.sv, line:9:1, endln:10:10 + \_module_inst: work@generic_flop (work@generic_flop), file:${SURELOG_DIR}/tests/ParamConst/dut.sv, line:9:1, endln:10:10 |UINT:0 |vpiTypespec: \_logic_typespec: , line:9:33, endln:9:44 @@ -1351,7 +1351,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:9:45, endln:9:59 |vpiParent: - \_module: work@generic_flop (work@generic_flop), file:${SURELOG_DIR}/tests/ParamConst/dut.sv, line:9:1, endln:10:10 + \_module_inst: work@generic_flop (work@generic_flop), file:${SURELOG_DIR}/tests/ParamConst/dut.sv, line:9:1, endln:10:10 |vpiRhs: \_constant: , line:9:58, endln:9:59 |vpiDecompile:0 @@ -1364,14 +1364,14 @@ design: (work@top) \_parameter: (work@generic_flop.ResetValue), line:9:45, endln:9:55 |vpiDefName:work@generic_flop |uhdmallModules: -\_module: work@prim_flop (work@prim_flop), file:${SURELOG_DIR}/tests/ParamConst/dut.sv, line:12:1, endln:16:10 +\_module_inst: work@prim_flop (work@prim_flop), file:${SURELOG_DIR}/tests/ParamConst/dut.sv, line:12:1, endln:16:10 |vpiParent: \_design: (work@top) |vpiFullName:work@prim_flop |vpiParameter: \_parameter: (work@prim_flop.ResetValue), line:12:43, endln:12:53 |vpiParent: - \_module: work@prim_flop (work@prim_flop), file:${SURELOG_DIR}/tests/ParamConst/dut.sv, line:12:1, endln:16:10 + \_module_inst: work@prim_flop (work@prim_flop), file:${SURELOG_DIR}/tests/ParamConst/dut.sv, line:12:1, endln:16:10 |UINT:0 |vpiTypespec: \_logic_typespec: , line:12:31, endln:12:42 @@ -1400,7 +1400,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:12:43, endln:12:57 |vpiParent: - \_module: work@prim_flop (work@prim_flop), file:${SURELOG_DIR}/tests/ParamConst/dut.sv, line:12:1, endln:16:10 + \_module_inst: work@prim_flop (work@prim_flop), file:${SURELOG_DIR}/tests/ParamConst/dut.sv, line:12:1, endln:16:10 |vpiRhs: \_constant: , line:12:56, endln:12:57 |vpiDecompile:0 @@ -1413,14 +1413,14 @@ design: (work@top) \_parameter: (work@prim_flop.ResetValue), line:12:43, endln:12:53 |vpiDefName:work@prim_flop |uhdmallModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamConst/dut.sv, line:18:1, endln:25:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamConst/dut.sv, line:18:1, endln:25:10 |vpiParent: \_design: (work@top) |vpiFullName:work@top |vpiParameter: \_parameter: (work@top.B0), line:2:25, endln:2:27 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamConst/dut.sv, line:18:1, endln:25:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamConst/dut.sv, line:18:1, endln:25:10 |BIN:01 |vpiTypespec: \_logic_typespec: , line:2:13, endln:2:24 @@ -1454,7 +1454,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.B1), line:3:25, endln:3:27 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamConst/dut.sv, line:18:1, endln:25:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamConst/dut.sv, line:18:1, endln:25:10 |BIN:10 |vpiTypespec: \_logic_typespec: , line:3:13, endln:3:24 @@ -1488,7 +1488,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:2:25, endln:2:35 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamConst/dut.sv, line:18:1, endln:25:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamConst/dut.sv, line:18:1, endln:25:10 |vpiRhs: \_constant: , line:2:30, endln:2:35 |vpiParent: @@ -1560,7 +1560,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:3:25, endln:3:35 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamConst/dut.sv, line:18:1, endln:25:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamConst/dut.sv, line:18:1, endln:25:10 |vpiRhs: \_constant: , line:3:30, endln:3:35 |vpiParent: @@ -1635,12 +1635,12 @@ design: (work@top) \_import_typespec: (lc_ctrl_state_pkg), line:19:10, endln:19:30 |vpiDefName:work@top |uhdmtopModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamConst/dut.sv, line:18:1, endln:25:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamConst/dut.sv, line:18:1, endln:25:10 |vpiName:work@top |vpiParameter: \_parameter: (work@top.B0), line:2:25, endln:2:27 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamConst/dut.sv, line:18:1, endln:25:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamConst/dut.sv, line:18:1, endln:25:10 |BIN:01 |vpiTypespec: \_logic_typespec: , line:2:13, endln:2:24 @@ -1674,7 +1674,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.B1), line:3:25, endln:3:27 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamConst/dut.sv, line:18:1, endln:25:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamConst/dut.sv, line:18:1, endln:25:10 |BIN:10 |vpiTypespec: \_logic_typespec: , line:3:13, endln:3:24 @@ -1708,7 +1708,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:2:25, endln:2:35 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamConst/dut.sv, line:18:1, endln:25:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamConst/dut.sv, line:18:1, endln:25:10 |vpiRhs: \_constant: , line:2:30, endln:2:35 |vpiDecompile:2'b01 @@ -1720,7 +1720,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:3:25, endln:3:35 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamConst/dut.sv, line:18:1, endln:25:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamConst/dut.sv, line:18:1, endln:25:10 |vpiRhs: \_constant: , line:3:30, endln:3:35 |vpiDecompile:2'b10 @@ -1736,16 +1736,16 @@ design: (work@top) |vpiDefName:work@top |vpiTop:1 |vpiTopModule:1 - |vpiModule: - \_module: work@prim_flop (work@top.state_regs), file:${SURELOG_DIR}/tests/ParamConst/dut.sv, line:21:3, endln:23:19 + |vpiModuleInst: + \_module_inst: work@prim_flop (work@top.state_regs), file:${SURELOG_DIR}/tests/ParamConst/dut.sv, line:21:3, endln:23:19 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamConst/dut.sv, line:18:1, endln:25:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamConst/dut.sv, line:18:1, endln:25:10 |vpiName:state_regs |vpiFullName:work@top.state_regs |vpiParameter: \_parameter: (work@top.state_regs.ResetValue), line:12:43, endln:12:53 |vpiParent: - \_module: work@prim_flop (work@top.state_regs), file:${SURELOG_DIR}/tests/ParamConst/dut.sv, line:21:3, endln:23:19 + \_module_inst: work@prim_flop (work@top.state_regs), file:${SURELOG_DIR}/tests/ParamConst/dut.sv, line:21:3, endln:23:19 |UINT:0 |vpiTypespec: \_logic_typespec: , line:12:31, endln:12:42 @@ -1776,7 +1776,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:12:43, endln:12:57 |vpiParent: - \_module: work@prim_flop (work@top.state_regs), file:${SURELOG_DIR}/tests/ParamConst/dut.sv, line:21:3, endln:23:19 + \_module_inst: work@prim_flop (work@top.state_regs), file:${SURELOG_DIR}/tests/ParamConst/dut.sv, line:21:3, endln:23:19 |vpiOverriden:1 |vpiRhs: \_constant: , line:12:56, endln:12:57 @@ -1792,17 +1792,17 @@ design: (work@top) |vpiDefFile:${SURELOG_DIR}/tests/ParamConst/dut.sv |vpiDefLineNo:12 |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamConst/dut.sv, line:18:1, endln:25:10 - |vpiModule: - \_module: work@generic_flop (work@top.state_regs.impl_generic), file:${SURELOG_DIR}/tests/ParamConst/dut.sv, line:13:5, endln:15:23 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamConst/dut.sv, line:18:1, endln:25:10 + |vpiModuleInst: + \_module_inst: work@generic_flop (work@top.state_regs.impl_generic), file:${SURELOG_DIR}/tests/ParamConst/dut.sv, line:13:5, endln:15:23 |vpiParent: - \_module: work@prim_flop (work@top.state_regs), file:${SURELOG_DIR}/tests/ParamConst/dut.sv, line:21:3, endln:23:19 + \_module_inst: work@prim_flop (work@top.state_regs), file:${SURELOG_DIR}/tests/ParamConst/dut.sv, line:21:3, endln:23:19 |vpiName:impl_generic |vpiFullName:work@top.state_regs.impl_generic |vpiParameter: \_parameter: (work@top.state_regs.impl_generic.ResetValue), line:9:45, endln:9:55 |vpiParent: - \_module: work@generic_flop (work@top.state_regs.impl_generic), file:${SURELOG_DIR}/tests/ParamConst/dut.sv, line:13:5, endln:15:23 + \_module_inst: work@generic_flop (work@top.state_regs.impl_generic), file:${SURELOG_DIR}/tests/ParamConst/dut.sv, line:13:5, endln:15:23 |UINT:0 |vpiTypespec: \_logic_typespec: , line:9:33, endln:9:44 @@ -1833,7 +1833,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:9:45, endln:9:59 |vpiParent: - \_module: work@generic_flop (work@top.state_regs.impl_generic), file:${SURELOG_DIR}/tests/ParamConst/dut.sv, line:13:5, endln:15:23 + \_module_inst: work@generic_flop (work@top.state_regs.impl_generic), file:${SURELOG_DIR}/tests/ParamConst/dut.sv, line:13:5, endln:15:23 |vpiOverriden:1 |vpiRhs: \_constant: , line:9:58, endln:9:59 @@ -1849,7 +1849,7 @@ design: (work@top) |vpiDefFile:${SURELOG_DIR}/tests/ParamConst/dut.sv |vpiDefLineNo:9 |vpiInstance: - \_module: work@prim_flop (work@top.state_regs), file:${SURELOG_DIR}/tests/ParamConst/dut.sv, line:21:3, endln:23:19 + \_module_inst: work@prim_flop (work@top.state_regs), file:${SURELOG_DIR}/tests/ParamConst/dut.sv, line:21:3, endln:23:19 =================== [ FATAL] : 0 [ SYNTAX] : 0 diff --git a/tests/ParamElab/ParamElab.log b/tests/ParamElab/ParamElab.log index 8443be0153..bd03207043 100644 --- a/tests/ParamElab/ParamElab.log +++ b/tests/ParamElab/ParamElab.log @@ -460,7 +460,7 @@ int_typespec 24 int_var 4 io_decl 11 logic_var 1 -module 11 +module_inst 11 operation 7 package 2 param_assign 6 @@ -486,7 +486,7 @@ int_typespec 24 int_var 4 io_decl 22 logic_var 1 -module 15 +module_inst 15 operation 7 package 2 param_assign 6 @@ -982,20 +982,20 @@ design: (work@dut) \_int_typespec: |vpiSigned:1 |uhdmallModules: -\_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/ParamElab/dut.sv, line:1:1, endln:6:10 +\_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/ParamElab/dut.sv, line:1:1, endln:6:10 |vpiParent: \_design: (work@dut) |vpiFullName:work@dut |vpiDefName:work@dut |uhdmallModules: -\_module: work@test (work@test), file:${SURELOG_DIR}/tests/ParamElab/dut.sv, line:8:1, endln:20:10 +\_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/ParamElab/dut.sv, line:8:1, endln:20:10 |vpiParent: \_design: (work@dut) |vpiFullName:work@test |vpiParameter: \_parameter: (work@test.Width), line:9:16, endln:9:21 |vpiParent: - \_module: work@test (work@test), file:${SURELOG_DIR}/tests/ParamElab/dut.sv, line:8:1, endln:20:10 + \_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/ParamElab/dut.sv, line:8:1, endln:20:10 |UINT:32 |vpiTypespec: \_int_typespec: , line:9:12, endln:9:15 @@ -1008,7 +1008,7 @@ design: (work@dut) |vpiParameter: \_parameter: (work@test.DataBitsPerMask), line:10:16, endln:10:31 |vpiParent: - \_module: work@test (work@test), file:${SURELOG_DIR}/tests/ParamElab/dut.sv, line:8:1, endln:20:10 + \_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/ParamElab/dut.sv, line:8:1, endln:20:10 |UINT:2 |vpiTypespec: \_int_typespec: , line:10:12, endln:10:15 @@ -1021,7 +1021,7 @@ design: (work@dut) |vpiParameter: \_parameter: (work@test.MaskWidth), line:12:24, endln:12:33 |vpiParent: - \_module: work@test (work@test), file:${SURELOG_DIR}/tests/ParamElab/dut.sv, line:8:1, endln:20:10 + \_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/ParamElab/dut.sv, line:8:1, endln:20:10 |vpiTypespec: \_int_typespec: , line:12:20, endln:12:23 |vpiParent: @@ -1034,7 +1034,7 @@ design: (work@dut) |vpiParamAssign: \_param_assign: , line:9:16, endln:9:36 |vpiParent: - \_module: work@test (work@test), file:${SURELOG_DIR}/tests/ParamElab/dut.sv, line:8:1, endln:20:10 + \_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/ParamElab/dut.sv, line:8:1, endln:20:10 |vpiRhs: \_constant: , line:9:34, endln:9:36 |vpiDecompile:32 @@ -1048,7 +1048,7 @@ design: (work@dut) |vpiParamAssign: \_param_assign: , line:10:16, endln:10:35 |vpiParent: - \_module: work@test (work@test), file:${SURELOG_DIR}/tests/ParamElab/dut.sv, line:8:1, endln:20:10 + \_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/ParamElab/dut.sv, line:8:1, endln:20:10 |vpiRhs: \_constant: , line:10:34, endln:10:35 |vpiDecompile:2 @@ -1062,7 +1062,7 @@ design: (work@dut) |vpiParamAssign: \_param_assign: , line:12:24, endln:12:59 |vpiParent: - \_module: work@test (work@test), file:${SURELOG_DIR}/tests/ParamElab/dut.sv, line:8:1, endln:20:10 + \_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/ParamElab/dut.sv, line:8:1, endln:20:10 |vpiRhs: \_operation: , line:12:36, endln:12:59 |vpiOpType:12 @@ -1080,21 +1080,21 @@ design: (work@dut) \_parameter: (work@test.MaskWidth), line:12:24, endln:12:33 |vpiDefName:work@test |uhdmtopModules: -\_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/ParamElab/dut.sv, line:1:1, endln:6:10 +\_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/ParamElab/dut.sv, line:1:1, endln:6:10 |vpiName:work@dut |vpiDefName:work@dut |vpiTop:1 |vpiTopModule:1 - |vpiModule: - \_module: work@test (work@dut.t), file:${SURELOG_DIR}/tests/ParamElab/dut.sv, line:2:9, endln:5:16 + |vpiModuleInst: + \_module_inst: work@test (work@dut.t), file:${SURELOG_DIR}/tests/ParamElab/dut.sv, line:2:9, endln:5:16 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/ParamElab/dut.sv, line:1:1, endln:6:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/ParamElab/dut.sv, line:1:1, endln:6:10 |vpiName:t |vpiFullName:work@dut.t |vpiParameter: \_parameter: (work@dut.t.Width), line:9:16, endln:9:21 |vpiParent: - \_module: work@test (work@dut.t), file:${SURELOG_DIR}/tests/ParamElab/dut.sv, line:2:9, endln:5:16 + \_module_inst: work@test (work@dut.t), file:${SURELOG_DIR}/tests/ParamElab/dut.sv, line:2:9, endln:5:16 |UINT:32 |vpiTypespec: \_int_typespec: , line:9:12, endln:9:15 @@ -1107,7 +1107,7 @@ design: (work@dut) |vpiParameter: \_parameter: (work@dut.t.DataBitsPerMask), line:10:16, endln:10:31 |vpiParent: - \_module: work@test (work@dut.t), file:${SURELOG_DIR}/tests/ParamElab/dut.sv, line:2:9, endln:5:16 + \_module_inst: work@test (work@dut.t), file:${SURELOG_DIR}/tests/ParamElab/dut.sv, line:2:9, endln:5:16 |UINT:2 |vpiTypespec: \_int_typespec: , line:10:12, endln:10:15 @@ -1120,7 +1120,7 @@ design: (work@dut) |vpiParameter: \_parameter: (work@dut.t.MaskWidth), line:12:24, endln:12:33 |vpiParent: - \_module: work@test (work@dut.t), file:${SURELOG_DIR}/tests/ParamElab/dut.sv, line:2:9, endln:5:16 + \_module_inst: work@test (work@dut.t), file:${SURELOG_DIR}/tests/ParamElab/dut.sv, line:2:9, endln:5:16 |vpiTypespec: \_int_typespec: , line:12:20, endln:12:23 |vpiParent: @@ -1133,7 +1133,7 @@ design: (work@dut) |vpiParamAssign: \_param_assign: , line:9:16, endln:9:36 |vpiParent: - \_module: work@test (work@dut.t), file:${SURELOG_DIR}/tests/ParamElab/dut.sv, line:2:9, endln:5:16 + \_module_inst: work@test (work@dut.t), file:${SURELOG_DIR}/tests/ParamElab/dut.sv, line:2:9, endln:5:16 |vpiOverriden:1 |vpiRhs: \_constant: , line:9:34, endln:9:36 @@ -1148,7 +1148,7 @@ design: (work@dut) |vpiParamAssign: \_param_assign: , line:10:16, endln:10:35 |vpiParent: - \_module: work@test (work@dut.t), file:${SURELOG_DIR}/tests/ParamElab/dut.sv, line:2:9, endln:5:16 + \_module_inst: work@test (work@dut.t), file:${SURELOG_DIR}/tests/ParamElab/dut.sv, line:2:9, endln:5:16 |vpiOverriden:1 |vpiRhs: \_constant: , line:10:34, endln:10:35 @@ -1163,7 +1163,7 @@ design: (work@dut) |vpiParamAssign: \_param_assign: , line:12:24, endln:12:59 |vpiParent: - \_module: work@test (work@dut.t), file:${SURELOG_DIR}/tests/ParamElab/dut.sv, line:2:9, endln:5:16 + \_module_inst: work@test (work@dut.t), file:${SURELOG_DIR}/tests/ParamElab/dut.sv, line:2:9, endln:5:16 |vpiRhs: \_constant: , line:12:36, endln:12:59 |vpiDecompile:4 @@ -1178,11 +1178,11 @@ design: (work@dut) |vpiDefFile:${SURELOG_DIR}/tests/ParamElab/dut.sv |vpiDefLineNo:8 |vpiInstance: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/ParamElab/dut.sv, line:1:1, endln:6:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/ParamElab/dut.sv, line:1:1, endln:6:10 |vpiGenScopeArray: \_gen_scope_array: (work@dut.t.genblk1[0]), line:15:36, endln:17:7 |vpiParent: - \_module: work@test (work@dut.t), file:${SURELOG_DIR}/tests/ParamElab/dut.sv, line:2:9, endln:5:16 + \_module_inst: work@test (work@dut.t), file:${SURELOG_DIR}/tests/ParamElab/dut.sv, line:2:9, endln:5:16 |vpiName:genblk1[0] |vpiFullName:work@dut.t.genblk1[0] |vpiGenScope: @@ -1200,8 +1200,8 @@ design: (work@dut) |vpiLocalParam:1 |vpiName:i |vpiFullName:work@dut.t.genblk1[0].i - |vpiModule: - \_module: work@dut.t.genblk1[0]::G1 (work@dut.t.genblk1[0].u), file:${SURELOG_DIR}/tests/ParamElab/dut.sv, line:16:7, endln:16:14 + |vpiModuleInst: + \_module_inst: work@dut.t.genblk1[0]::G1 (work@dut.t.genblk1[0].u), file:${SURELOG_DIR}/tests/ParamElab/dut.sv, line:16:7, endln:16:14 |vpiParent: \_gen_scope: (work@dut.t.genblk1[0]) |vpiName:u @@ -1210,7 +1210,7 @@ design: (work@dut) |vpiGenScopeArray: \_gen_scope_array: (work@dut.t.genblk1[1]), line:15:36, endln:17:7 |vpiParent: - \_module: work@test (work@dut.t), file:${SURELOG_DIR}/tests/ParamElab/dut.sv, line:2:9, endln:5:16 + \_module_inst: work@test (work@dut.t), file:${SURELOG_DIR}/tests/ParamElab/dut.sv, line:2:9, endln:5:16 |vpiName:genblk1[1] |vpiFullName:work@dut.t.genblk1[1] |vpiGenScope: @@ -1228,8 +1228,8 @@ design: (work@dut) |vpiLocalParam:1 |vpiName:i |vpiFullName:work@dut.t.genblk1[1].i - |vpiModule: - \_module: work@dut.t.genblk1[1]::G1 (work@dut.t.genblk1[1].u), file:${SURELOG_DIR}/tests/ParamElab/dut.sv, line:16:7, endln:16:14 + |vpiModuleInst: + \_module_inst: work@dut.t.genblk1[1]::G1 (work@dut.t.genblk1[1].u), file:${SURELOG_DIR}/tests/ParamElab/dut.sv, line:16:7, endln:16:14 |vpiParent: \_gen_scope: (work@dut.t.genblk1[1]) |vpiName:u @@ -1238,7 +1238,7 @@ design: (work@dut) |vpiGenScopeArray: \_gen_scope_array: (work@dut.t.genblk1[2]), line:15:36, endln:17:7 |vpiParent: - \_module: work@test (work@dut.t), file:${SURELOG_DIR}/tests/ParamElab/dut.sv, line:2:9, endln:5:16 + \_module_inst: work@test (work@dut.t), file:${SURELOG_DIR}/tests/ParamElab/dut.sv, line:2:9, endln:5:16 |vpiName:genblk1[2] |vpiFullName:work@dut.t.genblk1[2] |vpiGenScope: @@ -1256,8 +1256,8 @@ design: (work@dut) |vpiLocalParam:1 |vpiName:i |vpiFullName:work@dut.t.genblk1[2].i - |vpiModule: - \_module: work@dut.t.genblk1[2]::G1 (work@dut.t.genblk1[2].u), file:${SURELOG_DIR}/tests/ParamElab/dut.sv, line:16:7, endln:16:14 + |vpiModuleInst: + \_module_inst: work@dut.t.genblk1[2]::G1 (work@dut.t.genblk1[2].u), file:${SURELOG_DIR}/tests/ParamElab/dut.sv, line:16:7, endln:16:14 |vpiParent: \_gen_scope: (work@dut.t.genblk1[2]) |vpiName:u @@ -1266,7 +1266,7 @@ design: (work@dut) |vpiGenScopeArray: \_gen_scope_array: (work@dut.t.genblk1[3]), line:15:36, endln:17:7 |vpiParent: - \_module: work@test (work@dut.t), file:${SURELOG_DIR}/tests/ParamElab/dut.sv, line:2:9, endln:5:16 + \_module_inst: work@test (work@dut.t), file:${SURELOG_DIR}/tests/ParamElab/dut.sv, line:2:9, endln:5:16 |vpiName:genblk1[3] |vpiFullName:work@dut.t.genblk1[3] |vpiGenScope: @@ -1284,8 +1284,8 @@ design: (work@dut) |vpiLocalParam:1 |vpiName:i |vpiFullName:work@dut.t.genblk1[3].i - |vpiModule: - \_module: work@dut.t.genblk1[3]::G1 (work@dut.t.genblk1[3].u), file:${SURELOG_DIR}/tests/ParamElab/dut.sv, line:16:7, endln:16:14 + |vpiModuleInst: + \_module_inst: work@dut.t.genblk1[3]::G1 (work@dut.t.genblk1[3].u), file:${SURELOG_DIR}/tests/ParamElab/dut.sv, line:16:7, endln:16:14 |vpiParent: \_gen_scope: (work@dut.t.genblk1[3]) |vpiName:u diff --git a/tests/ParamElabMulti/ParamElabMulti.log b/tests/ParamElabMulti/ParamElabMulti.log index d2904267b0..ef6a220368 100644 --- a/tests/ParamElabMulti/ParamElabMulti.log +++ b/tests/ParamElabMulti/ParamElabMulti.log @@ -497,7 +497,7 @@ hier_path 1 import_typespec 5 int_typespec 37 logic_typespec 25 -module 18 +module_inst 18 operation 47 package 6 packed_array_typespec 23 @@ -525,7 +525,7 @@ hier_path 1 import_typespec 5 int_typespec 37 logic_typespec 25 -module 22 +module_inst 22 operation 47 package 6 packed_array_typespec 23 @@ -678,7 +678,7 @@ design: (work@top) |vpiElemTypespec: \_enum_typespec: (prim_pad_wrapper_pkg::pad_type_e), line:2:4, endln:5:17 |vpiParent: - \_module: work@sub_top (work@sub_top), file:${SURELOG_DIR}/tests/ParamElabMulti/dut.sv, line:41:1, endln:50:10 + \_module_inst: work@sub_top (work@sub_top), file:${SURELOG_DIR}/tests/ParamElabMulti/dut.sv, line:41:1, endln:50:10 |vpiName:prim_pad_wrapper_pkg::pad_type_e |vpiInstance: \_package: pinmux_pkg (pinmux_pkg::), file:${SURELOG_DIR}/tests/ParamElabMulti/dut.sv, line:8:1, endln:20:24 @@ -805,7 +805,7 @@ design: (work@top) |vpiTypespec: \_struct_typespec: (pinmux_pkg::target_cfg_t), line:13:12, endln:13:18 |vpiParent: - \_module: work@sub_top (work@sub_top), file:${SURELOG_DIR}/tests/ParamElabMulti/dut.sv, line:41:1, endln:50:10 + \_module_inst: work@sub_top (work@sub_top), file:${SURELOG_DIR}/tests/ParamElabMulti/dut.sv, line:41:1, endln:50:10 |vpiName:pinmux_pkg::target_cfg_t |vpiInstance: \_package: pinmux_pkg (pinmux_pkg::), file:${SURELOG_DIR}/tests/ParamElabMulti/dut.sv, line:8:1, endln:20:24 @@ -896,14 +896,14 @@ design: (work@top) |vpiDefName:pinmux_pkg |vpiTop:1 |uhdmallModules: -\_module: work@prim_generic_pad_attr (work@prim_generic_pad_attr), file:${SURELOG_DIR}/tests/ParamElabMulti/dut.sv, line:22:1, endln:28:34 +\_module_inst: work@prim_generic_pad_attr (work@prim_generic_pad_attr), file:${SURELOG_DIR}/tests/ParamElabMulti/dut.sv, line:22:1, endln:28:34 |vpiParent: \_design: (work@top) |vpiFullName:work@prim_generic_pad_attr |vpiParameter: \_parameter: (work@prim_generic_pad_attr.PadType), line:24:25, endln:24:32 |vpiParent: - \_module: work@prim_generic_pad_attr (work@prim_generic_pad_attr), file:${SURELOG_DIR}/tests/ParamElabMulti/dut.sv, line:22:1, endln:28:34 + \_module_inst: work@prim_generic_pad_attr (work@prim_generic_pad_attr), file:${SURELOG_DIR}/tests/ParamElabMulti/dut.sv, line:22:1, endln:28:34 |vpiTypespec: \_enum_typespec: (prim_pad_wrapper_pkg::pad_type_e), line:2:4, endln:5:17 |vpiName:PadType @@ -911,7 +911,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:24:25, endln:24:36 |vpiParent: - \_module: work@prim_generic_pad_attr (work@prim_generic_pad_attr), file:${SURELOG_DIR}/tests/ParamElabMulti/dut.sv, line:22:1, endln:28:34 + \_module_inst: work@prim_generic_pad_attr (work@prim_generic_pad_attr), file:${SURELOG_DIR}/tests/ParamElabMulti/dut.sv, line:22:1, endln:28:34 |vpiRhs: \_ref_obj: (A), line:24:35, endln:24:36 |vpiName:A @@ -925,14 +925,14 @@ design: (work@top) \_import_typespec: (prim_pad_wrapper_pkg), line:23:11, endln:23:34 |vpiDefName:work@prim_generic_pad_attr |uhdmallModules: -\_module: work@prim_pad_attr (work@prim_pad_attr), file:${SURELOG_DIR}/tests/ParamElabMulti/dut.sv, line:30:1, endln:39:10 +\_module_inst: work@prim_pad_attr (work@prim_pad_attr), file:${SURELOG_DIR}/tests/ParamElabMulti/dut.sv, line:30:1, endln:39:10 |vpiParent: \_design: (work@top) |vpiFullName:work@prim_pad_attr |vpiParameter: \_parameter: (work@prim_pad_attr.PadType), line:32:25, endln:32:32 |vpiParent: - \_module: work@prim_pad_attr (work@prim_pad_attr), file:${SURELOG_DIR}/tests/ParamElabMulti/dut.sv, line:30:1, endln:39:10 + \_module_inst: work@prim_pad_attr (work@prim_pad_attr), file:${SURELOG_DIR}/tests/ParamElabMulti/dut.sv, line:30:1, endln:39:10 |vpiTypespec: \_enum_typespec: (prim_pad_wrapper_pkg::pad_type_e), line:2:4, endln:5:17 |vpiName:PadType @@ -940,7 +940,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:32:25, endln:32:36 |vpiParent: - \_module: work@prim_pad_attr (work@prim_pad_attr), file:${SURELOG_DIR}/tests/ParamElabMulti/dut.sv, line:30:1, endln:39:10 + \_module_inst: work@prim_pad_attr (work@prim_pad_attr), file:${SURELOG_DIR}/tests/ParamElabMulti/dut.sv, line:30:1, endln:39:10 |vpiRhs: \_ref_obj: (A), line:32:35, endln:32:36 |vpiName:A @@ -954,14 +954,14 @@ design: (work@top) \_import_typespec: (prim_pad_wrapper_pkg), line:31:11, endln:31:34 |vpiDefName:work@prim_pad_attr |uhdmallModules: -\_module: work@sub_top (work@sub_top), file:${SURELOG_DIR}/tests/ParamElabMulti/dut.sv, line:41:1, endln:50:10 +\_module_inst: work@sub_top (work@sub_top), file:${SURELOG_DIR}/tests/ParamElabMulti/dut.sv, line:41:1, endln:50:10 |vpiParent: \_design: (work@top) |vpiFullName:work@sub_top |vpiParameter: \_parameter: (work@sub_top.DefaultTargetCfg), line:17:27, endln:17:43 |vpiParent: - \_module: work@sub_top (work@sub_top), file:${SURELOG_DIR}/tests/ParamElabMulti/dut.sv, line:41:1, endln:50:10 + \_module_inst: work@sub_top (work@sub_top), file:${SURELOG_DIR}/tests/ParamElabMulti/dut.sv, line:41:1, endln:50:10 |vpiTypespec: \_struct_typespec: (pinmux_pkg::target_cfg_t), line:13:12, endln:13:18 |vpiParent: @@ -1061,7 +1061,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@sub_top.NDioPads), line:11:18, endln:11:26 |vpiParent: - \_module: work@sub_top (work@sub_top), file:${SURELOG_DIR}/tests/ParamElabMulti/dut.sv, line:41:1, endln:50:10 + \_module_inst: work@sub_top (work@sub_top), file:${SURELOG_DIR}/tests/ParamElabMulti/dut.sv, line:41:1, endln:50:10 |UINT:1 |vpiTypespec: \_int_typespec: , line:11:14, endln:11:17 @@ -1077,7 +1077,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@sub_top.TargetCfg), line:43:27, endln:43:36 |vpiParent: - \_module: work@sub_top (work@sub_top), file:${SURELOG_DIR}/tests/ParamElabMulti/dut.sv, line:41:1, endln:50:10 + \_module_inst: work@sub_top (work@sub_top), file:${SURELOG_DIR}/tests/ParamElabMulti/dut.sv, line:41:1, endln:50:10 |vpiTypespec: \_struct_typespec: (pinmux_pkg::target_cfg_t), line:13:12, endln:13:18 |vpiName:TargetCfg @@ -1085,7 +1085,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:11:18, endln:11:30 |vpiParent: - \_module: work@sub_top (work@sub_top), file:${SURELOG_DIR}/tests/ParamElabMulti/dut.sv, line:41:1, endln:50:10 + \_module_inst: work@sub_top (work@sub_top), file:${SURELOG_DIR}/tests/ParamElabMulti/dut.sv, line:41:1, endln:50:10 |vpiRhs: \_constant: , line:11:29, endln:11:30 |vpiParent: @@ -1120,7 +1120,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:17:27, endln:19:5 |vpiParent: - \_module: work@sub_top (work@sub_top), file:${SURELOG_DIR}/tests/ParamElabMulti/dut.sv, line:41:1, endln:50:10 + \_module_inst: work@sub_top (work@sub_top), file:${SURELOG_DIR}/tests/ParamElabMulti/dut.sv, line:41:1, endln:50:10 |vpiRhs: \_operation: , line:17:46, endln:19:5 |vpiParent: @@ -1251,7 +1251,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:43:27, endln:43:55 |vpiParent: - \_module: work@sub_top (work@sub_top), file:${SURELOG_DIR}/tests/ParamElabMulti/dut.sv, line:41:1, endln:50:10 + \_module_inst: work@sub_top (work@sub_top), file:${SURELOG_DIR}/tests/ParamElabMulti/dut.sv, line:41:1, endln:50:10 |vpiRhs: \_ref_obj: (DefaultTargetCfg), line:43:39, endln:43:55 |vpiName:DefaultTargetCfg @@ -1265,14 +1265,14 @@ design: (work@top) \_import_typespec: (pinmux_pkg), line:42:11, endln:42:24 |vpiDefName:work@sub_top |uhdmallModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamElabMulti/dut.sv, line:52:1, endln:61:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamElabMulti/dut.sv, line:52:1, endln:61:10 |vpiParent: \_design: (work@top) |vpiFullName:work@top |vpiParameter: \_parameter: (work@top.PinmuxTargetCfg), line:53:40, endln:53:55 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamElabMulti/dut.sv, line:52:1, endln:61:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamElabMulti/dut.sv, line:52:1, endln:61:10 |vpiTypespec: \_struct_typespec: (pinmux_pkg::target_cfg_t), line:13:12, endln:13:18 |vpiLocalParam:1 @@ -1281,7 +1281,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:53:40, endln:55:5 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamElabMulti/dut.sv, line:52:1, endln:61:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamElabMulti/dut.sv, line:52:1, endln:61:10 |vpiRhs: \_operation: , line:53:58, endln:55:5 |vpiOpType:75 @@ -1318,12 +1318,12 @@ design: (work@top) \_parameter: (work@top.PinmuxTargetCfg), line:53:40, endln:53:55 |vpiDefName:work@top |uhdmtopModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamElabMulti/dut.sv, line:52:1, endln:61:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamElabMulti/dut.sv, line:52:1, endln:61:10 |vpiName:work@top |vpiParameter: \_parameter: (work@top.PinmuxTargetCfg), line:53:40, endln:53:55 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamElabMulti/dut.sv, line:52:1, endln:61:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamElabMulti/dut.sv, line:52:1, endln:61:10 |vpiTypespec: \_struct_typespec: (pinmux_pkg::target_cfg_t), line:13:12, endln:13:18 |vpiParent: @@ -1423,7 +1423,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:53:40, endln:55:5 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamElabMulti/dut.sv, line:52:1, endln:61:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamElabMulti/dut.sv, line:52:1, endln:61:10 |vpiRhs: \_operation: , line:53:58, endln:55:5 |vpiParent: @@ -1540,16 +1540,16 @@ design: (work@top) |vpiDefName:work@top |vpiTop:1 |vpiTopModule:1 - |vpiModule: - \_module: work@sub_top (work@top.u_sub), file:${SURELOG_DIR}/tests/ParamElabMulti/dut.sv, line:57:4, endln:59:14 + |vpiModuleInst: + \_module_inst: work@sub_top (work@top.u_sub), file:${SURELOG_DIR}/tests/ParamElabMulti/dut.sv, line:57:4, endln:59:14 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamElabMulti/dut.sv, line:52:1, endln:61:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamElabMulti/dut.sv, line:52:1, endln:61:10 |vpiName:u_sub |vpiFullName:work@top.u_sub |vpiParameter: \_parameter: (work@top.u_sub.DefaultTargetCfg), line:17:27, endln:17:43 |vpiParent: - \_module: work@sub_top (work@top.u_sub), file:${SURELOG_DIR}/tests/ParamElabMulti/dut.sv, line:57:4, endln:59:14 + \_module_inst: work@sub_top (work@top.u_sub), file:${SURELOG_DIR}/tests/ParamElabMulti/dut.sv, line:57:4, endln:59:14 |vpiTypespec: \_struct_typespec: (pinmux_pkg::target_cfg_t), line:13:12, endln:13:18 |vpiParent: @@ -1649,7 +1649,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.u_sub.NDioPads), line:11:18, endln:11:26 |vpiParent: - \_module: work@sub_top (work@top.u_sub), file:${SURELOG_DIR}/tests/ParamElabMulti/dut.sv, line:57:4, endln:59:14 + \_module_inst: work@sub_top (work@top.u_sub), file:${SURELOG_DIR}/tests/ParamElabMulti/dut.sv, line:57:4, endln:59:14 |UINT:1 |vpiTypespec: \_int_typespec: , line:11:14, endln:11:17 @@ -1665,7 +1665,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.u_sub.TargetCfg), line:43:27, endln:43:36 |vpiParent: - \_module: work@sub_top (work@top.u_sub), file:${SURELOG_DIR}/tests/ParamElabMulti/dut.sv, line:57:4, endln:59:14 + \_module_inst: work@sub_top (work@top.u_sub), file:${SURELOG_DIR}/tests/ParamElabMulti/dut.sv, line:57:4, endln:59:14 |vpiTypespec: \_struct_typespec: (pinmux_pkg::target_cfg_t), line:13:12, endln:13:18 |vpiParent: @@ -1764,7 +1764,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:11:18, endln:11:30 |vpiParent: - \_module: work@sub_top (work@top.u_sub), file:${SURELOG_DIR}/tests/ParamElabMulti/dut.sv, line:57:4, endln:59:14 + \_module_inst: work@sub_top (work@top.u_sub), file:${SURELOG_DIR}/tests/ParamElabMulti/dut.sv, line:57:4, endln:59:14 |vpiRhs: \_constant: , line:11:29, endln:11:30 |vpiDecompile:1 @@ -1778,7 +1778,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:17:27, endln:19:5 |vpiParent: - \_module: work@sub_top (work@top.u_sub), file:${SURELOG_DIR}/tests/ParamElabMulti/dut.sv, line:57:4, endln:59:14 + \_module_inst: work@sub_top (work@top.u_sub), file:${SURELOG_DIR}/tests/ParamElabMulti/dut.sv, line:57:4, endln:59:14 |vpiRhs: \_operation: , line:17:46, endln:19:5 |vpiParent: @@ -1895,7 +1895,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:43:27, endln:43:55 |vpiParent: - \_module: work@sub_top (work@top.u_sub), file:${SURELOG_DIR}/tests/ParamElabMulti/dut.sv, line:57:4, endln:59:14 + \_module_inst: work@sub_top (work@top.u_sub), file:${SURELOG_DIR}/tests/ParamElabMulti/dut.sv, line:57:4, endln:59:14 |vpiOverriden:1 |vpiRhs: \_operation: , line:58:18, endln:58:33 @@ -2020,11 +2020,11 @@ design: (work@top) |vpiDefFile:${SURELOG_DIR}/tests/ParamElabMulti/dut.sv |vpiDefLineNo:41 |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamElabMulti/dut.sv, line:52:1, endln:61:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamElabMulti/dut.sv, line:52:1, endln:61:10 |vpiGenScopeArray: \_gen_scope_array: (work@top.u_sub.gen_dio_attr[0]), line:45:41, endln:49:6 |vpiParent: - \_module: work@sub_top (work@top.u_sub), file:${SURELOG_DIR}/tests/ParamElabMulti/dut.sv, line:57:4, endln:59:14 + \_module_inst: work@sub_top (work@top.u_sub), file:${SURELOG_DIR}/tests/ParamElabMulti/dut.sv, line:57:4, endln:59:14 |vpiName:gen_dio_attr[0] |vpiFullName:work@top.u_sub.gen_dio_attr[0] |vpiGenScope: @@ -2042,8 +2042,8 @@ design: (work@top) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@top.u_sub.gen_dio_attr[0].k - |vpiModule: - \_module: work@prim_pad_attr (work@top.u_sub.gen_dio_attr[0].u_prim_pad_attr), file:${SURELOG_DIR}/tests/ParamElabMulti/dut.sv, line:46:6, endln:48:26 + |vpiModuleInst: + \_module_inst: work@prim_pad_attr (work@top.u_sub.gen_dio_attr[0].u_prim_pad_attr), file:${SURELOG_DIR}/tests/ParamElabMulti/dut.sv, line:46:6, endln:48:26 |vpiParent: \_gen_scope: (work@top.u_sub.gen_dio_attr[0]) |vpiName:u_prim_pad_attr @@ -2106,7 +2106,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:32:25, endln:32:36 |vpiParent: - \_module: work@prim_pad_attr (work@top.u_sub.gen_dio_attr[0].u_prim_pad_attr), file:${SURELOG_DIR}/tests/ParamElabMulti/dut.sv, line:46:6, endln:48:26 + \_module_inst: work@prim_pad_attr (work@top.u_sub.gen_dio_attr[0].u_prim_pad_attr), file:${SURELOG_DIR}/tests/ParamElabMulti/dut.sv, line:46:6, endln:48:26 |vpiOverriden:1 |vpiRhs: \_constant: , line:32:35, endln:32:36 @@ -2128,7 +2128,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.u_sub.gen_dio_attr[0].u_prim_pad_attr.gen_generic), line:34:4, endln:38:7 |vpiParent: - \_module: work@prim_pad_attr (work@top.u_sub.gen_dio_attr[0].u_prim_pad_attr), file:${SURELOG_DIR}/tests/ParamElabMulti/dut.sv, line:46:6, endln:48:26 + \_module_inst: work@prim_pad_attr (work@top.u_sub.gen_dio_attr[0].u_prim_pad_attr), file:${SURELOG_DIR}/tests/ParamElabMulti/dut.sv, line:46:6, endln:48:26 |vpiName:gen_generic |vpiFullName:work@top.u_sub.gen_dio_attr[0].u_prim_pad_attr.gen_generic |vpiGenScope: @@ -2136,8 +2136,8 @@ design: (work@top) |vpiParent: \_gen_scope_array: (work@top.u_sub.gen_dio_attr[0].u_prim_pad_attr.gen_generic), line:34:4, endln:38:7 |vpiFullName:work@top.u_sub.gen_dio_attr[0].u_prim_pad_attr.gen_generic - |vpiModule: - \_module: work@prim_generic_pad_attr (work@top.u_sub.gen_dio_attr[0].u_prim_pad_attr.gen_generic.u_impl_generic), file:${SURELOG_DIR}/tests/ParamElabMulti/dut.sv, line:35:7, endln:37:26 + |vpiModuleInst: + \_module_inst: work@prim_generic_pad_attr (work@top.u_sub.gen_dio_attr[0].u_prim_pad_attr.gen_generic.u_impl_generic), file:${SURELOG_DIR}/tests/ParamElabMulti/dut.sv, line:35:7, endln:37:26 |vpiParent: \_gen_scope: (work@top.u_sub.gen_dio_attr[0].u_prim_pad_attr.gen_generic) |vpiName:u_impl_generic @@ -2200,7 +2200,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:24:25, endln:24:36 |vpiParent: - \_module: work@prim_generic_pad_attr (work@top.u_sub.gen_dio_attr[0].u_prim_pad_attr.gen_generic.u_impl_generic), file:${SURELOG_DIR}/tests/ParamElabMulti/dut.sv, line:35:7, endln:37:26 + \_module_inst: work@prim_generic_pad_attr (work@top.u_sub.gen_dio_attr[0].u_prim_pad_attr.gen_generic.u_impl_generic), file:${SURELOG_DIR}/tests/ParamElabMulti/dut.sv, line:35:7, endln:37:26 |vpiOverriden:1 |vpiRhs: \_constant: , line:24:35, endln:24:36 @@ -2222,7 +2222,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.u_sub.gen_dio_attr[0].u_prim_pad_attr.gen_generic.u_impl_generic.gen_assign), line:25:4, endln:27:7 |vpiParent: - \_module: work@prim_generic_pad_attr (work@top.u_sub.gen_dio_attr[0].u_prim_pad_attr.gen_generic.u_impl_generic), file:${SURELOG_DIR}/tests/ParamElabMulti/dut.sv, line:35:7, endln:37:26 + \_module_inst: work@prim_generic_pad_attr (work@top.u_sub.gen_dio_attr[0].u_prim_pad_attr.gen_generic.u_impl_generic), file:${SURELOG_DIR}/tests/ParamElabMulti/dut.sv, line:35:7, endln:37:26 |vpiName:gen_assign |vpiFullName:work@top.u_sub.gen_dio_attr[0].u_prim_pad_attr.gen_generic.u_impl_generic.gen_assign |vpiGenScope: diff --git a/tests/ParamFile/ParamFile.log b/tests/ParamFile/ParamFile.log index 4f0fe8c2b6..0f481baa06 100644 --- a/tests/ParamFile/ParamFile.log +++ b/tests/ParamFile/ParamFile.log @@ -236,7 +236,7 @@ if_stmt 2 initial 1 logic_net 4 logic_typespec 6 -module 9 +module_inst 9 named_begin 2 operation 2 param_assign 4 @@ -258,14 +258,14 @@ sys_func_call 2 design: (work@dut) |vpiName:work@dut |uhdmallModules: -\_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/ParamFile/dut.sv, line:3:1, endln:10:10 +\_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/ParamFile/dut.sv, line:3:1, endln:10:10 |vpiParent: \_design: (work@dut) |vpiFullName:work@dut |vpiParameter: \_parameter: (work@dut.SRAMInitFile), line:4:14, endln:4:26 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/ParamFile/dut.sv, line:3:1, endln:10:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/ParamFile/dut.sv, line:3:1, endln:10:10 |STRING: |vpiTypespec: \_string_typespec: @@ -274,7 +274,7 @@ design: (work@dut) |vpiParamAssign: \_param_assign: , line:4:14, endln:4:31 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/ParamFile/dut.sv, line:3:1, endln:10:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/ParamFile/dut.sv, line:3:1, endln:10:10 |vpiRhs: \_constant: , line:4:29, endln:4:31 |STRING: @@ -287,14 +287,14 @@ design: (work@dut) |vpiNet: \_logic_net: (work@dut.o), line:3:26, endln:3:27 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/ParamFile/dut.sv, line:3:1, endln:10:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/ParamFile/dut.sv, line:3:1, endln:10:10 |vpiName:o |vpiFullName:work@dut.o |vpiNetType:36 |vpiPort: \_port: (o), line:3:26, endln:3:27 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/ParamFile/dut.sv, line:3:1, endln:10:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/ParamFile/dut.sv, line:3:1, endln:10:10 |vpiName:o |vpiDirection:2 |vpiLowConn: @@ -304,14 +304,14 @@ design: (work@dut) |vpiTypedef: \_logic_typespec: , line:3:20, endln:3:25 |uhdmallModules: -\_module: work@ram_1p (work@ram_1p), file:${SURELOG_DIR}/tests/ParamFile/dut.sv, line:12:1, endln:30:10 +\_module_inst: work@ram_1p (work@ram_1p), file:${SURELOG_DIR}/tests/ParamFile/dut.sv, line:12:1, endln:30:10 |vpiParent: \_design: (work@dut) |vpiFullName:work@ram_1p |vpiParameter: \_parameter: (work@ram_1p.MemInitFile), line:13:23, endln:13:34 |vpiParent: - \_module: work@ram_1p (work@ram_1p), file:${SURELOG_DIR}/tests/ParamFile/dut.sv, line:12:1, endln:30:10 + \_module_inst: work@ram_1p (work@ram_1p), file:${SURELOG_DIR}/tests/ParamFile/dut.sv, line:12:1, endln:30:10 |STRING: |vpiTypespec: \_string_typespec: @@ -320,7 +320,7 @@ design: (work@dut) |vpiParamAssign: \_param_assign: , line:13:23, endln:13:39 |vpiParent: - \_module: work@ram_1p (work@ram_1p), file:${SURELOG_DIR}/tests/ParamFile/dut.sv, line:12:1, endln:30:10 + \_module_inst: work@ram_1p (work@ram_1p), file:${SURELOG_DIR}/tests/ParamFile/dut.sv, line:12:1, endln:30:10 |vpiRhs: \_constant: , line:13:37, endln:13:39 |STRING: @@ -333,14 +333,14 @@ design: (work@dut) |vpiNet: \_logic_net: (work@ram_1p.out), line:15:22, endln:15:25 |vpiParent: - \_module: work@ram_1p (work@ram_1p), file:${SURELOG_DIR}/tests/ParamFile/dut.sv, line:12:1, endln:30:10 + \_module_inst: work@ram_1p (work@ram_1p), file:${SURELOG_DIR}/tests/ParamFile/dut.sv, line:12:1, endln:30:10 |vpiName:out |vpiFullName:work@ram_1p.out |vpiNetType:36 |vpiPort: \_port: (out), line:15:22, endln:15:25 |vpiParent: - \_module: work@ram_1p (work@ram_1p), file:${SURELOG_DIR}/tests/ParamFile/dut.sv, line:12:1, endln:30:10 + \_module_inst: work@ram_1p (work@ram_1p), file:${SURELOG_DIR}/tests/ParamFile/dut.sv, line:12:1, endln:30:10 |vpiName:out |vpiDirection:2 |vpiLowConn: @@ -352,7 +352,7 @@ design: (work@dut) |vpiProcess: \_initial: , line:18:1, endln:28:4 |vpiParent: - \_module: work@ram_1p (work@ram_1p), file:${SURELOG_DIR}/tests/ParamFile/dut.sv, line:12:1, endln:30:10 + \_module_inst: work@ram_1p (work@ram_1p), file:${SURELOG_DIR}/tests/ParamFile/dut.sv, line:12:1, endln:30:10 |vpiStmt: \_begin: (work@ram_1p), line:18:9, endln:28:4 |vpiParent: @@ -485,12 +485,12 @@ design: (work@dut) |vpiActual: \_logic_net: (work@dut.u_ram.out), line:15:22, endln:15:25 |uhdmtopModules: -\_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/ParamFile/dut.sv, line:3:1, endln:10:10 +\_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/ParamFile/dut.sv, line:3:1, endln:10:10 |vpiName:work@dut |vpiParameter: \_parameter: (work@dut.SRAMInitFile), line:4:14, endln:4:26 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/ParamFile/dut.sv, line:3:1, endln:10:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/ParamFile/dut.sv, line:3:1, endln:10:10 |STRING: |vpiTypespec: \_string_typespec: @@ -501,7 +501,7 @@ design: (work@dut) |vpiParamAssign: \_param_assign: , line:4:14, endln:4:31 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/ParamFile/dut.sv, line:3:1, endln:10:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/ParamFile/dut.sv, line:3:1, endln:10:10 |vpiRhs: \_constant: , line:4:29, endln:4:31 |STRING: @@ -515,7 +515,7 @@ design: (work@dut) |vpiNet: \_logic_net: (work@dut.o), line:3:26, endln:3:27 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/ParamFile/dut.sv, line:3:1, endln:10:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/ParamFile/dut.sv, line:3:1, endln:10:10 |vpiTypespec: \_logic_typespec: , line:3:20, endln:3:25 |vpiName:o @@ -525,7 +525,7 @@ design: (work@dut) |vpiPort: \_port: (o), line:3:26, endln:3:27 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/ParamFile/dut.sv, line:3:1, endln:10:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/ParamFile/dut.sv, line:3:1, endln:10:10 |vpiName:o |vpiDirection:2 |vpiLowConn: @@ -536,16 +536,16 @@ design: (work@dut) \_logic_net: (work@dut.o), line:3:26, endln:3:27 |vpiTypedef: \_logic_typespec: , line:3:20, endln:3:25 - |vpiModule: - \_module: work@ram_1p (work@dut.u_ram), file:${SURELOG_DIR}/tests/ParamFile/dut.sv, line:5:4, endln:9:6 + |vpiModuleInst: + \_module_inst: work@ram_1p (work@dut.u_ram), file:${SURELOG_DIR}/tests/ParamFile/dut.sv, line:5:4, endln:9:6 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/ParamFile/dut.sv, line:3:1, endln:10:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/ParamFile/dut.sv, line:3:1, endln:10:10 |vpiName:u_ram |vpiFullName:work@dut.u_ram |vpiParameter: \_parameter: (work@dut.u_ram.MemInitFile), line:13:23, endln:13:34 |vpiParent: - \_module: work@ram_1p (work@dut.u_ram), file:${SURELOG_DIR}/tests/ParamFile/dut.sv, line:5:4, endln:9:6 + \_module_inst: work@ram_1p (work@dut.u_ram), file:${SURELOG_DIR}/tests/ParamFile/dut.sv, line:5:4, endln:9:6 |STRING: |vpiTypespec: \_string_typespec: @@ -556,7 +556,7 @@ design: (work@dut) |vpiParamAssign: \_param_assign: , line:13:23, endln:13:39 |vpiParent: - \_module: work@ram_1p (work@dut.u_ram), file:${SURELOG_DIR}/tests/ParamFile/dut.sv, line:5:4, endln:9:6 + \_module_inst: work@ram_1p (work@dut.u_ram), file:${SURELOG_DIR}/tests/ParamFile/dut.sv, line:5:4, endln:9:6 |vpiOverriden:1 |vpiRhs: \_constant: , line:13:37, endln:13:39 @@ -572,18 +572,18 @@ design: (work@dut) |vpiNet: \_logic_net: (work@dut.u_ram.out), line:15:22, endln:15:25 |vpiParent: - \_module: work@ram_1p (work@dut.u_ram), file:${SURELOG_DIR}/tests/ParamFile/dut.sv, line:5:4, endln:9:6 + \_module_inst: work@ram_1p (work@dut.u_ram), file:${SURELOG_DIR}/tests/ParamFile/dut.sv, line:5:4, endln:9:6 |vpiTypespec: \_logic_typespec: , line:15:16, endln:15:21 |vpiName:out |vpiFullName:work@dut.u_ram.out |vpiNetType:36 |vpiInstance: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/ParamFile/dut.sv, line:3:1, endln:10:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/ParamFile/dut.sv, line:3:1, endln:10:10 |vpiPort: \_port: (out), line:15:22, endln:15:25 |vpiParent: - \_module: work@ram_1p (work@dut.u_ram), file:${SURELOG_DIR}/tests/ParamFile/dut.sv, line:5:4, endln:9:6 + \_module_inst: work@ram_1p (work@dut.u_ram), file:${SURELOG_DIR}/tests/ParamFile/dut.sv, line:5:4, endln:9:6 |vpiName:out |vpiDirection:2 |vpiHighConn: diff --git a/tests/ParamFile/ParamFileNoTop.log b/tests/ParamFile/ParamFileNoTop.log index b9e8afc48a..ecd1f4ffa6 100644 --- a/tests/ParamFile/ParamFileNoTop.log +++ b/tests/ParamFile/ParamFileNoTop.log @@ -240,7 +240,7 @@ if_stmt 2 initial 1 logic_net 2 logic_typespec 2 -module 4 +module_inst 4 named_begin 2 operation 2 param_assign 2 @@ -262,14 +262,14 @@ sys_func_call 2 design: (unnamed) |vpiName:unnamed |uhdmallModules: -\_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/ParamFile/dut.sv, line:3:1, endln:10:10 +\_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/ParamFile/dut.sv, line:3:1, endln:10:10 |vpiParent: \_design: (unnamed) |vpiFullName:work@dut |vpiParameter: \_parameter: (work@dut.SRAMInitFile), line:4:14, endln:4:26 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/ParamFile/dut.sv, line:3:1, endln:10:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/ParamFile/dut.sv, line:3:1, endln:10:10 |STRING: |vpiTypespec: \_string_typespec: @@ -278,7 +278,7 @@ design: (unnamed) |vpiParamAssign: \_param_assign: , line:4:14, endln:4:31 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/ParamFile/dut.sv, line:3:1, endln:10:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/ParamFile/dut.sv, line:3:1, endln:10:10 |vpiRhs: \_constant: , line:4:29, endln:4:31 |STRING: @@ -291,14 +291,14 @@ design: (unnamed) |vpiNet: \_logic_net: (work@dut.o), line:3:26, endln:3:27 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/ParamFile/dut.sv, line:3:1, endln:10:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/ParamFile/dut.sv, line:3:1, endln:10:10 |vpiName:o |vpiFullName:work@dut.o |vpiNetType:36 |vpiPort: \_port: (o), line:3:26, endln:3:27 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/ParamFile/dut.sv, line:3:1, endln:10:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/ParamFile/dut.sv, line:3:1, endln:10:10 |vpiName:o |vpiDirection:2 |vpiLowConn: @@ -308,14 +308,14 @@ design: (unnamed) |vpiTypedef: \_logic_typespec: , line:3:20, endln:3:25 |uhdmallModules: -\_module: work@ram_1p (work@ram_1p), file:${SURELOG_DIR}/tests/ParamFile/dut.sv, line:12:1, endln:30:10 +\_module_inst: work@ram_1p (work@ram_1p), file:${SURELOG_DIR}/tests/ParamFile/dut.sv, line:12:1, endln:30:10 |vpiParent: \_design: (unnamed) |vpiFullName:work@ram_1p |vpiParameter: \_parameter: (work@ram_1p.MemInitFile), line:13:23, endln:13:34 |vpiParent: - \_module: work@ram_1p (work@ram_1p), file:${SURELOG_DIR}/tests/ParamFile/dut.sv, line:12:1, endln:30:10 + \_module_inst: work@ram_1p (work@ram_1p), file:${SURELOG_DIR}/tests/ParamFile/dut.sv, line:12:1, endln:30:10 |STRING: |vpiTypespec: \_string_typespec: @@ -324,7 +324,7 @@ design: (unnamed) |vpiParamAssign: \_param_assign: , line:13:23, endln:13:39 |vpiParent: - \_module: work@ram_1p (work@ram_1p), file:${SURELOG_DIR}/tests/ParamFile/dut.sv, line:12:1, endln:30:10 + \_module_inst: work@ram_1p (work@ram_1p), file:${SURELOG_DIR}/tests/ParamFile/dut.sv, line:12:1, endln:30:10 |vpiRhs: \_constant: , line:13:37, endln:13:39 |STRING: @@ -337,14 +337,14 @@ design: (unnamed) |vpiNet: \_logic_net: (work@ram_1p.out), line:15:22, endln:15:25 |vpiParent: - \_module: work@ram_1p (work@ram_1p), file:${SURELOG_DIR}/tests/ParamFile/dut.sv, line:12:1, endln:30:10 + \_module_inst: work@ram_1p (work@ram_1p), file:${SURELOG_DIR}/tests/ParamFile/dut.sv, line:12:1, endln:30:10 |vpiName:out |vpiFullName:work@ram_1p.out |vpiNetType:36 |vpiPort: \_port: (out), line:15:22, endln:15:25 |vpiParent: - \_module: work@ram_1p (work@ram_1p), file:${SURELOG_DIR}/tests/ParamFile/dut.sv, line:12:1, endln:30:10 + \_module_inst: work@ram_1p (work@ram_1p), file:${SURELOG_DIR}/tests/ParamFile/dut.sv, line:12:1, endln:30:10 |vpiName:out |vpiDirection:2 |vpiLowConn: @@ -356,7 +356,7 @@ design: (unnamed) |vpiProcess: \_initial: , line:18:1, endln:28:4 |vpiParent: - \_module: work@ram_1p (work@ram_1p), file:${SURELOG_DIR}/tests/ParamFile/dut.sv, line:12:1, endln:30:10 + \_module_inst: work@ram_1p (work@ram_1p), file:${SURELOG_DIR}/tests/ParamFile/dut.sv, line:12:1, endln:30:10 |vpiStmt: \_begin: (work@ram_1p), line:18:9, endln:28:4 |vpiParent: diff --git a/tests/ParamFile/ParamFileOverr.log b/tests/ParamFile/ParamFileOverr.log index 448dade0ac..759a4a022c 100644 --- a/tests/ParamFile/ParamFileOverr.log +++ b/tests/ParamFile/ParamFileOverr.log @@ -236,7 +236,7 @@ if_stmt 2 initial 1 logic_net 4 logic_typespec 6 -module 8 +module_inst 8 named_begin 2 operation 2 param_assign 4 @@ -258,21 +258,21 @@ sys_func_call 2 design: (work@dut) |vpiName:work@dut |uhdmallModules: -\_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/ParamFile/dut.sv, line:3:1, endln:10:10 +\_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/ParamFile/dut.sv, line:3:1, endln:10:10 |vpiParent: \_design: (work@dut) |vpiFullName:work@dut |vpiParameter: \_parameter: (work@dut.SRAMInitFile), line:4:14, endln:4:26 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/ParamFile/dut.sv, line:3:1, endln:10:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/ParamFile/dut.sv, line:3:1, endln:10:10 |STRING: |vpiName:SRAMInitFile |vpiFullName:work@dut.SRAMInitFile |vpiParamAssign: \_param_assign: , line:4:14, endln:4:31 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/ParamFile/dut.sv, line:3:1, endln:10:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/ParamFile/dut.sv, line:3:1, endln:10:10 |vpiRhs: \_constant: , line:4:29, endln:4:31 |STRING: @@ -285,14 +285,14 @@ design: (work@dut) |vpiNet: \_logic_net: (work@dut.o), line:3:26, endln:3:27 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/ParamFile/dut.sv, line:3:1, endln:10:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/ParamFile/dut.sv, line:3:1, endln:10:10 |vpiName:o |vpiFullName:work@dut.o |vpiNetType:36 |vpiPort: \_port: (o), line:3:26, endln:3:27 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/ParamFile/dut.sv, line:3:1, endln:10:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/ParamFile/dut.sv, line:3:1, endln:10:10 |vpiName:o |vpiDirection:2 |vpiLowConn: @@ -302,14 +302,14 @@ design: (work@dut) |vpiTypedef: \_logic_typespec: , line:3:20, endln:3:25 |uhdmallModules: -\_module: work@ram_1p (work@ram_1p), file:${SURELOG_DIR}/tests/ParamFile/dut.sv, line:12:1, endln:30:10 +\_module_inst: work@ram_1p (work@ram_1p), file:${SURELOG_DIR}/tests/ParamFile/dut.sv, line:12:1, endln:30:10 |vpiParent: \_design: (work@dut) |vpiFullName:work@ram_1p |vpiParameter: \_parameter: (work@ram_1p.MemInitFile), line:13:23, endln:13:34 |vpiParent: - \_module: work@ram_1p (work@ram_1p), file:${SURELOG_DIR}/tests/ParamFile/dut.sv, line:12:1, endln:30:10 + \_module_inst: work@ram_1p (work@ram_1p), file:${SURELOG_DIR}/tests/ParamFile/dut.sv, line:12:1, endln:30:10 |STRING: |vpiTypespec: \_string_typespec: @@ -318,7 +318,7 @@ design: (work@dut) |vpiParamAssign: \_param_assign: , line:13:23, endln:13:39 |vpiParent: - \_module: work@ram_1p (work@ram_1p), file:${SURELOG_DIR}/tests/ParamFile/dut.sv, line:12:1, endln:30:10 + \_module_inst: work@ram_1p (work@ram_1p), file:${SURELOG_DIR}/tests/ParamFile/dut.sv, line:12:1, endln:30:10 |vpiRhs: \_constant: , line:13:37, endln:13:39 |STRING: @@ -331,14 +331,14 @@ design: (work@dut) |vpiNet: \_logic_net: (work@ram_1p.out), line:15:22, endln:15:25 |vpiParent: - \_module: work@ram_1p (work@ram_1p), file:${SURELOG_DIR}/tests/ParamFile/dut.sv, line:12:1, endln:30:10 + \_module_inst: work@ram_1p (work@ram_1p), file:${SURELOG_DIR}/tests/ParamFile/dut.sv, line:12:1, endln:30:10 |vpiName:out |vpiFullName:work@ram_1p.out |vpiNetType:36 |vpiPort: \_port: (out), line:15:22, endln:15:25 |vpiParent: - \_module: work@ram_1p (work@ram_1p), file:${SURELOG_DIR}/tests/ParamFile/dut.sv, line:12:1, endln:30:10 + \_module_inst: work@ram_1p (work@ram_1p), file:${SURELOG_DIR}/tests/ParamFile/dut.sv, line:12:1, endln:30:10 |vpiName:out |vpiDirection:2 |vpiLowConn: @@ -350,7 +350,7 @@ design: (work@dut) |vpiProcess: \_initial: , line:18:1, endln:28:4 |vpiParent: - \_module: work@ram_1p (work@ram_1p), file:${SURELOG_DIR}/tests/ParamFile/dut.sv, line:12:1, endln:30:10 + \_module_inst: work@ram_1p (work@ram_1p), file:${SURELOG_DIR}/tests/ParamFile/dut.sv, line:12:1, endln:30:10 |vpiStmt: \_begin: (work@ram_1p), line:18:9, endln:28:4 |vpiParent: @@ -483,19 +483,19 @@ design: (work@dut) |vpiActual: \_logic_net: (work@dut.u_ram.out), line:15:22, endln:15:25 |uhdmtopModules: -\_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/ParamFile/dut.sv, line:3:1, endln:10:10 +\_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/ParamFile/dut.sv, line:3:1, endln:10:10 |vpiName:work@dut |vpiParameter: \_parameter: (work@dut.SRAMInitFile), line:4:14, endln:4:26 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/ParamFile/dut.sv, line:3:1, endln:10:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/ParamFile/dut.sv, line:3:1, endln:10:10 |STRING: |vpiName:SRAMInitFile |vpiFullName:work@dut.SRAMInitFile |vpiParamAssign: \_param_assign: , line:4:14, endln:4:31 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/ParamFile/dut.sv, line:3:1, endln:10:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/ParamFile/dut.sv, line:3:1, endln:10:10 |vpiRhs: \_constant: , line:4:29, endln:4:31 |vpiDecompile:/blah @@ -509,7 +509,7 @@ design: (work@dut) |vpiNet: \_logic_net: (work@dut.o), line:3:26, endln:3:27 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/ParamFile/dut.sv, line:3:1, endln:10:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/ParamFile/dut.sv, line:3:1, endln:10:10 |vpiTypespec: \_logic_typespec: , line:3:20, endln:3:25 |vpiName:o @@ -519,7 +519,7 @@ design: (work@dut) |vpiPort: \_port: (o), line:3:26, endln:3:27 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/ParamFile/dut.sv, line:3:1, endln:10:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/ParamFile/dut.sv, line:3:1, endln:10:10 |vpiName:o |vpiDirection:2 |vpiLowConn: @@ -530,16 +530,16 @@ design: (work@dut) \_logic_net: (work@dut.o), line:3:26, endln:3:27 |vpiTypedef: \_logic_typespec: , line:3:20, endln:3:25 - |vpiModule: - \_module: work@ram_1p (work@dut.u_ram), file:${SURELOG_DIR}/tests/ParamFile/dut.sv, line:5:4, endln:9:6 + |vpiModuleInst: + \_module_inst: work@ram_1p (work@dut.u_ram), file:${SURELOG_DIR}/tests/ParamFile/dut.sv, line:5:4, endln:9:6 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/ParamFile/dut.sv, line:3:1, endln:10:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/ParamFile/dut.sv, line:3:1, endln:10:10 |vpiName:u_ram |vpiFullName:work@dut.u_ram |vpiParameter: \_parameter: (work@dut.u_ram.MemInitFile), line:13:23, endln:13:34 |vpiParent: - \_module: work@ram_1p (work@dut.u_ram), file:${SURELOG_DIR}/tests/ParamFile/dut.sv, line:5:4, endln:9:6 + \_module_inst: work@ram_1p (work@dut.u_ram), file:${SURELOG_DIR}/tests/ParamFile/dut.sv, line:5:4, endln:9:6 |STRING: |vpiTypespec: \_string_typespec: @@ -550,7 +550,7 @@ design: (work@dut) |vpiParamAssign: \_param_assign: , line:13:23, endln:13:39 |vpiParent: - \_module: work@ram_1p (work@dut.u_ram), file:${SURELOG_DIR}/tests/ParamFile/dut.sv, line:5:4, endln:9:6 + \_module_inst: work@ram_1p (work@dut.u_ram), file:${SURELOG_DIR}/tests/ParamFile/dut.sv, line:5:4, endln:9:6 |vpiOverriden:1 |vpiRhs: \_constant: , line:13:37, endln:13:39 @@ -568,18 +568,18 @@ design: (work@dut) |vpiNet: \_logic_net: (work@dut.u_ram.out), line:15:22, endln:15:25 |vpiParent: - \_module: work@ram_1p (work@dut.u_ram), file:${SURELOG_DIR}/tests/ParamFile/dut.sv, line:5:4, endln:9:6 + \_module_inst: work@ram_1p (work@dut.u_ram), file:${SURELOG_DIR}/tests/ParamFile/dut.sv, line:5:4, endln:9:6 |vpiTypespec: \_logic_typespec: , line:15:16, endln:15:21 |vpiName:out |vpiFullName:work@dut.u_ram.out |vpiNetType:36 |vpiInstance: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/ParamFile/dut.sv, line:3:1, endln:10:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/ParamFile/dut.sv, line:3:1, endln:10:10 |vpiPort: \_port: (out), line:15:22, endln:15:25 |vpiParent: - \_module: work@ram_1p (work@dut.u_ram), file:${SURELOG_DIR}/tests/ParamFile/dut.sv, line:5:4, endln:9:6 + \_module_inst: work@ram_1p (work@dut.u_ram), file:${SURELOG_DIR}/tests/ParamFile/dut.sv, line:5:4, endln:9:6 |vpiName:out |vpiDirection:2 |vpiHighConn: diff --git a/tests/ParamFromPackage/ParamFromPackage.log b/tests/ParamFromPackage/ParamFromPackage.log index 6906ab8b66..3847ecb7e1 100644 --- a/tests/ParamFromPackage/ParamFromPackage.log +++ b/tests/ParamFromPackage/ParamFromPackage.log @@ -160,7 +160,7 @@ constant 67 design 1 import_typespec 1 logic_typespec 15 -module 9 +module_inst 9 package 3 param_assign 10 parameter 11 @@ -173,7 +173,7 @@ constant 67 design 1 import_typespec 1 logic_typespec 15 -module 9 +module_inst 9 package 3 param_assign 10 parameter 11 @@ -333,14 +333,14 @@ design: (work@top) |vpiDefName:aes_pkg |vpiTop:1 |uhdmallModules: -\_module: work@aes_cipher_core (work@aes_cipher_core), file:${SURELOG_DIR}/tests/ParamFromPackage/dut.sv, line:5:1, endln:10:10 +\_module_inst: work@aes_cipher_core (work@aes_cipher_core), file:${SURELOG_DIR}/tests/ParamFromPackage/dut.sv, line:5:1, endln:10:10 |vpiParent: \_design: (work@top) |vpiFullName:work@aes_cipher_core |vpiParameter: \_parameter: (work@aes_cipher_core.X), line:2:31, endln:2:32 |vpiParent: - \_module: work@aes_cipher_core (work@aes_cipher_core), file:${SURELOG_DIR}/tests/ParamFromPackage/dut.sv, line:5:1, endln:10:10 + \_module_inst: work@aes_cipher_core (work@aes_cipher_core), file:${SURELOG_DIR}/tests/ParamFromPackage/dut.sv, line:5:1, endln:10:10 |HEX:abcd |vpiTypespec: \_logic_typespec: , line:2:14, endln:2:30 @@ -394,7 +394,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@aes_cipher_core.P), line:7:34, endln:7:35 |vpiParent: - \_module: work@aes_cipher_core (work@aes_cipher_core), file:${SURELOG_DIR}/tests/ParamFromPackage/dut.sv, line:5:1, endln:10:10 + \_module_inst: work@aes_cipher_core (work@aes_cipher_core), file:${SURELOG_DIR}/tests/ParamFromPackage/dut.sv, line:5:1, endln:10:10 |HEX:abcd |vpiTypespec: \_logic_typespec: , line:7:17, endln:7:33 @@ -441,7 +441,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@aes_cipher_core.Z), line:8:23, endln:8:24 |vpiParent: - \_module: work@aes_cipher_core (work@aes_cipher_core), file:${SURELOG_DIR}/tests/ParamFromPackage/dut.sv, line:5:1, endln:10:10 + \_module_inst: work@aes_cipher_core (work@aes_cipher_core), file:${SURELOG_DIR}/tests/ParamFromPackage/dut.sv, line:5:1, endln:10:10 |UINT:0 |vpiTypespec: \_logic_typespec: , line:8:17, endln:8:22 @@ -452,7 +452,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:2:31, endln:2:43 |vpiParent: - \_module: work@aes_cipher_core (work@aes_cipher_core), file:${SURELOG_DIR}/tests/ParamFromPackage/dut.sv, line:5:1, endln:10:10 + \_module_inst: work@aes_cipher_core (work@aes_cipher_core), file:${SURELOG_DIR}/tests/ParamFromPackage/dut.sv, line:5:1, endln:10:10 |vpiRhs: \_constant: , line:2:35, endln:2:43 |vpiParent: @@ -564,7 +564,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:7:34, endln:7:39 |vpiParent: - \_module: work@aes_cipher_core (work@aes_cipher_core), file:${SURELOG_DIR}/tests/ParamFromPackage/dut.sv, line:5:1, endln:10:10 + \_module_inst: work@aes_cipher_core (work@aes_cipher_core), file:${SURELOG_DIR}/tests/ParamFromPackage/dut.sv, line:5:1, endln:10:10 |vpiRhs: \_constant: , line:7:38, endln:7:39 |vpiDecompile:32'habcd @@ -578,7 +578,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:8:23, endln:8:28 |vpiParent: - \_module: work@aes_cipher_core (work@aes_cipher_core), file:${SURELOG_DIR}/tests/ParamFromPackage/dut.sv, line:5:1, endln:10:10 + \_module_inst: work@aes_cipher_core (work@aes_cipher_core), file:${SURELOG_DIR}/tests/ParamFromPackage/dut.sv, line:5:1, endln:10:10 |vpiRhs: \_constant: , line:8:27, endln:8:28 |vpiDecompile:0 @@ -593,27 +593,27 @@ design: (work@top) \_import_typespec: (aes_pkg), line:5:31, endln:5:41 |vpiDefName:work@aes_cipher_core |uhdmallModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamFromPackage/dut.sv, line:12:1, endln:14:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamFromPackage/dut.sv, line:12:1, endln:14:10 |vpiParent: \_design: (work@top) |vpiFullName:work@top |vpiDefName:work@top |uhdmtopModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamFromPackage/dut.sv, line:12:1, endln:14:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamFromPackage/dut.sv, line:12:1, endln:14:10 |vpiName:work@top |vpiDefName:work@top |vpiTop:1 |vpiTopModule:1 - |vpiModule: - \_module: work@aes_cipher_core (work@top.u_aes_cipher_core), file:${SURELOG_DIR}/tests/ParamFromPackage/dut.sv, line:13:4, endln:13:49 + |vpiModuleInst: + \_module_inst: work@aes_cipher_core (work@top.u_aes_cipher_core), file:${SURELOG_DIR}/tests/ParamFromPackage/dut.sv, line:13:4, endln:13:49 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamFromPackage/dut.sv, line:12:1, endln:14:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamFromPackage/dut.sv, line:12:1, endln:14:10 |vpiName:u_aes_cipher_core |vpiFullName:work@top.u_aes_cipher_core |vpiParameter: \_parameter: (work@top.u_aes_cipher_core.X), line:2:31, endln:2:32 |vpiParent: - \_module: work@aes_cipher_core (work@top.u_aes_cipher_core), file:${SURELOG_DIR}/tests/ParamFromPackage/dut.sv, line:13:4, endln:13:49 + \_module_inst: work@aes_cipher_core (work@top.u_aes_cipher_core), file:${SURELOG_DIR}/tests/ParamFromPackage/dut.sv, line:13:4, endln:13:49 |HEX:abcd |vpiTypespec: \_logic_typespec: , line:2:14, endln:2:30 @@ -667,7 +667,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.u_aes_cipher_core.P), line:7:34, endln:7:35 |vpiParent: - \_module: work@aes_cipher_core (work@top.u_aes_cipher_core), file:${SURELOG_DIR}/tests/ParamFromPackage/dut.sv, line:13:4, endln:13:49 + \_module_inst: work@aes_cipher_core (work@top.u_aes_cipher_core), file:${SURELOG_DIR}/tests/ParamFromPackage/dut.sv, line:13:4, endln:13:49 |HEX:abcd |vpiTypespec: \_logic_typespec: , line:7:17, endln:7:33 @@ -718,7 +718,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.u_aes_cipher_core.Z), line:8:23, endln:8:24 |vpiParent: - \_module: work@aes_cipher_core (work@top.u_aes_cipher_core), file:${SURELOG_DIR}/tests/ParamFromPackage/dut.sv, line:13:4, endln:13:49 + \_module_inst: work@aes_cipher_core (work@top.u_aes_cipher_core), file:${SURELOG_DIR}/tests/ParamFromPackage/dut.sv, line:13:4, endln:13:49 |UINT:0 |vpiTypespec: \_logic_typespec: , line:8:17, endln:8:22 @@ -729,7 +729,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:7:34, endln:7:39 |vpiParent: - \_module: work@aes_cipher_core (work@top.u_aes_cipher_core), file:${SURELOG_DIR}/tests/ParamFromPackage/dut.sv, line:13:4, endln:13:49 + \_module_inst: work@aes_cipher_core (work@top.u_aes_cipher_core), file:${SURELOG_DIR}/tests/ParamFromPackage/dut.sv, line:13:4, endln:13:49 |vpiRhs: \_constant: , line:7:38, endln:7:39 |vpiDecompile:32'habcd @@ -787,7 +787,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:8:23, endln:8:28 |vpiParent: - \_module: work@aes_cipher_core (work@top.u_aes_cipher_core), file:${SURELOG_DIR}/tests/ParamFromPackage/dut.sv, line:13:4, endln:13:49 + \_module_inst: work@aes_cipher_core (work@top.u_aes_cipher_core), file:${SURELOG_DIR}/tests/ParamFromPackage/dut.sv, line:13:4, endln:13:49 |vpiOverriden:1 |vpiRhs: \_constant: , line:8:27, endln:8:28 @@ -802,7 +802,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:2:31, endln:2:43 |vpiParent: - \_module: work@aes_cipher_core (work@top.u_aes_cipher_core), file:${SURELOG_DIR}/tests/ParamFromPackage/dut.sv, line:13:4, endln:13:49 + \_module_inst: work@aes_cipher_core (work@top.u_aes_cipher_core), file:${SURELOG_DIR}/tests/ParamFromPackage/dut.sv, line:13:4, endln:13:49 |vpiRhs: \_constant: , line:2:35, endln:2:43 |vpiDecompile:32'habcd @@ -817,7 +817,7 @@ design: (work@top) |vpiDefFile:${SURELOG_DIR}/tests/ParamFromPackage/dut.sv |vpiDefLineNo:5 |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamFromPackage/dut.sv, line:12:1, endln:14:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamFromPackage/dut.sv, line:12:1, endln:14:10 =================== [ FATAL] : 0 [ SYNTAX] : 0 diff --git a/tests/ParamInFunc/ParamInFunc.log b/tests/ParamInFunc/ParamInFunc.log index 8d1d4a9b08..b69bb2fc5c 100644 --- a/tests/ParamInFunc/ParamInFunc.log +++ b/tests/ParamInFunc/ParamInFunc.log @@ -180,7 +180,7 @@ io_decl 1 logic_net 8 logic_typespec 2 logic_var 1 -module 3 +module_inst 3 operation 1 param_assign 2 parameter 2 @@ -201,7 +201,7 @@ io_decl 2 logic_net 8 logic_typespec 2 logic_var 1 -module 3 +module_inst 3 operation 2 param_assign 4 parameter 6 @@ -223,7 +223,7 @@ design: (work@func_block_top) |vpiElaborated:1 |vpiName:work@func_block_top |uhdmallModules: -\_module: work@func_block_top (work@func_block_top), file:${SURELOG_DIR}/tests/ParamInFunc/dut.sv, line:3:1, endln:10:10 +\_module_inst: work@func_block_top (work@func_block_top), file:${SURELOG_DIR}/tests/ParamInFunc/dut.sv, line:3:1, endln:10:10 |vpiParent: \_design: (work@func_block_top) |vpiFullName:work@func_block_top @@ -231,7 +231,7 @@ design: (work@func_block_top) |vpiTaskFunc: \_function: (work@func_block_top.func3), line:4:9, endln:9:20 |vpiParent: - \_module: work@func_block_top (work@func_block_top), file:${SURELOG_DIR}/tests/ParamInFunc/dut.sv, line:3:1, endln:10:10 + \_module_inst: work@func_block_top (work@func_block_top), file:${SURELOG_DIR}/tests/ParamInFunc/dut.sv, line:3:1, endln:10:10 |vpiName:func3 |vpiFullName:work@func_block_top.func3 |vpiParameter: @@ -304,7 +304,7 @@ design: (work@func_block_top) |UINT:0 |vpiConstType:9 |vpiParent: - \_module: work@func_block_top (work@func_block_top), file:${SURELOG_DIR}/tests/ParamInFunc/dut.sv, line:3:1, endln:10:10 + \_module_inst: work@func_block_top (work@func_block_top), file:${SURELOG_DIR}/tests/ParamInFunc/dut.sv, line:3:1, endln:10:10 |vpiIODecl: \_io_decl: (inp), line:7:30, endln:7:33 |vpiParent: @@ -392,35 +392,35 @@ design: (work@func_block_top) |vpiActual: \_parameter: (B), line:6:27, endln:6:28 |vpiInstance: - \_module: work@func_block_top (work@func_block_top), file:${SURELOG_DIR}/tests/ParamInFunc/dut.sv, line:3:1, endln:10:10 + \_module_inst: work@func_block_top (work@func_block_top), file:${SURELOG_DIR}/tests/ParamInFunc/dut.sv, line:3:1, endln:10:10 |vpiNet: \_logic_net: (work@func_block_top.inp), line:3:23, endln:3:26 |vpiParent: - \_module: work@func_block_top (work@func_block_top), file:${SURELOG_DIR}/tests/ParamInFunc/dut.sv, line:3:1, endln:10:10 + \_module_inst: work@func_block_top (work@func_block_top), file:${SURELOG_DIR}/tests/ParamInFunc/dut.sv, line:3:1, endln:10:10 |vpiName:inp |vpiFullName:work@func_block_top.inp |vpiNet: \_logic_net: (work@func_block_top.out1), line:3:28, endln:3:32 |vpiParent: - \_module: work@func_block_top (work@func_block_top), file:${SURELOG_DIR}/tests/ParamInFunc/dut.sv, line:3:1, endln:10:10 + \_module_inst: work@func_block_top (work@func_block_top), file:${SURELOG_DIR}/tests/ParamInFunc/dut.sv, line:3:1, endln:10:10 |vpiName:out1 |vpiFullName:work@func_block_top.out1 |vpiNet: \_logic_net: (work@func_block_top.out2), line:3:34, endln:3:38 |vpiParent: - \_module: work@func_block_top (work@func_block_top), file:${SURELOG_DIR}/tests/ParamInFunc/dut.sv, line:3:1, endln:10:10 + \_module_inst: work@func_block_top (work@func_block_top), file:${SURELOG_DIR}/tests/ParamInFunc/dut.sv, line:3:1, endln:10:10 |vpiName:out2 |vpiFullName:work@func_block_top.out2 |vpiNet: \_logic_net: (work@func_block_top.out3), line:3:40, endln:3:44 |vpiParent: - \_module: work@func_block_top (work@func_block_top), file:${SURELOG_DIR}/tests/ParamInFunc/dut.sv, line:3:1, endln:10:10 + \_module_inst: work@func_block_top (work@func_block_top), file:${SURELOG_DIR}/tests/ParamInFunc/dut.sv, line:3:1, endln:10:10 |vpiName:out3 |vpiFullName:work@func_block_top.out3 |vpiPort: \_port: (inp), line:3:23, endln:3:26 |vpiParent: - \_module: work@func_block_top (work@func_block_top), file:${SURELOG_DIR}/tests/ParamInFunc/dut.sv, line:3:1, endln:10:10 + \_module_inst: work@func_block_top (work@func_block_top), file:${SURELOG_DIR}/tests/ParamInFunc/dut.sv, line:3:1, endln:10:10 |vpiName:inp |vpiDirection:3 |vpiLowConn: @@ -430,7 +430,7 @@ design: (work@func_block_top) |vpiPort: \_port: (out1), line:3:28, endln:3:32 |vpiParent: - \_module: work@func_block_top (work@func_block_top), file:${SURELOG_DIR}/tests/ParamInFunc/dut.sv, line:3:1, endln:10:10 + \_module_inst: work@func_block_top (work@func_block_top), file:${SURELOG_DIR}/tests/ParamInFunc/dut.sv, line:3:1, endln:10:10 |vpiName:out1 |vpiDirection:3 |vpiLowConn: @@ -440,7 +440,7 @@ design: (work@func_block_top) |vpiPort: \_port: (out2), line:3:34, endln:3:38 |vpiParent: - \_module: work@func_block_top (work@func_block_top), file:${SURELOG_DIR}/tests/ParamInFunc/dut.sv, line:3:1, endln:10:10 + \_module_inst: work@func_block_top (work@func_block_top), file:${SURELOG_DIR}/tests/ParamInFunc/dut.sv, line:3:1, endln:10:10 |vpiName:out2 |vpiDirection:3 |vpiLowConn: @@ -450,7 +450,7 @@ design: (work@func_block_top) |vpiPort: \_port: (out3), line:3:40, endln:3:44 |vpiParent: - \_module: work@func_block_top (work@func_block_top), file:${SURELOG_DIR}/tests/ParamInFunc/dut.sv, line:3:1, endln:10:10 + \_module_inst: work@func_block_top (work@func_block_top), file:${SURELOG_DIR}/tests/ParamInFunc/dut.sv, line:3:1, endln:10:10 |vpiName:out3 |vpiDirection:3 |vpiLowConn: @@ -458,14 +458,14 @@ design: (work@func_block_top) |vpiActual: \_logic_net: (work@func_block_top.out3), line:3:40, endln:3:44 |uhdmtopModules: -\_module: work@func_block_top (work@func_block_top), file:${SURELOG_DIR}/tests/ParamInFunc/dut.sv, line:3:1, endln:10:10 +\_module_inst: work@func_block_top (work@func_block_top), file:${SURELOG_DIR}/tests/ParamInFunc/dut.sv, line:3:1, endln:10:10 |vpiName:work@func_block_top |vpiDefName:work@func_block_top |vpiTop:1 |vpiTaskFunc: \_function: (work@func_block_top.func3), line:4:9, endln:9:20 |vpiParent: - \_module: work@func_block_top (work@func_block_top), file:${SURELOG_DIR}/tests/ParamInFunc/dut.sv, line:3:1, endln:10:10 + \_module_inst: work@func_block_top (work@func_block_top), file:${SURELOG_DIR}/tests/ParamInFunc/dut.sv, line:3:1, endln:10:10 |vpiName:func3 |vpiFullName:work@func_block_top.func3 |vpiParameter: @@ -524,7 +524,7 @@ design: (work@func_block_top) |vpiReturn: \_logic_var: , line:4:28, endln:4:34 |vpiParent: - \_module: work@func_block_top (work@func_block_top), file:${SURELOG_DIR}/tests/ParamInFunc/dut.sv, line:3:1, endln:10:10 + \_module_inst: work@func_block_top (work@func_block_top), file:${SURELOG_DIR}/tests/ParamInFunc/dut.sv, line:3:1, endln:10:10 |vpiIODecl: \_io_decl: (inp), line:7:30, endln:7:33 |vpiParent: @@ -596,36 +596,36 @@ design: (work@func_block_top) |vpiActual: \_parameter: (B), line:6:27, endln:6:28 |vpiInstance: - \_module: work@func_block_top (work@func_block_top), file:${SURELOG_DIR}/tests/ParamInFunc/dut.sv, line:3:1, endln:10:10 + \_module_inst: work@func_block_top (work@func_block_top), file:${SURELOG_DIR}/tests/ParamInFunc/dut.sv, line:3:1, endln:10:10 |vpiNet: \_logic_net: (work@func_block_top.inp), line:3:23, endln:3:26 |vpiParent: - \_module: work@func_block_top (work@func_block_top), file:${SURELOG_DIR}/tests/ParamInFunc/dut.sv, line:3:1, endln:10:10 + \_module_inst: work@func_block_top (work@func_block_top), file:${SURELOG_DIR}/tests/ParamInFunc/dut.sv, line:3:1, endln:10:10 |vpiName:inp |vpiFullName:work@func_block_top.inp |vpiNet: \_logic_net: (work@func_block_top.out1), line:3:28, endln:3:32 |vpiParent: - \_module: work@func_block_top (work@func_block_top), file:${SURELOG_DIR}/tests/ParamInFunc/dut.sv, line:3:1, endln:10:10 + \_module_inst: work@func_block_top (work@func_block_top), file:${SURELOG_DIR}/tests/ParamInFunc/dut.sv, line:3:1, endln:10:10 |vpiName:out1 |vpiFullName:work@func_block_top.out1 |vpiNet: \_logic_net: (work@func_block_top.out2), line:3:34, endln:3:38 |vpiParent: - \_module: work@func_block_top (work@func_block_top), file:${SURELOG_DIR}/tests/ParamInFunc/dut.sv, line:3:1, endln:10:10 + \_module_inst: work@func_block_top (work@func_block_top), file:${SURELOG_DIR}/tests/ParamInFunc/dut.sv, line:3:1, endln:10:10 |vpiName:out2 |vpiFullName:work@func_block_top.out2 |vpiNet: \_logic_net: (work@func_block_top.out3), line:3:40, endln:3:44 |vpiParent: - \_module: work@func_block_top (work@func_block_top), file:${SURELOG_DIR}/tests/ParamInFunc/dut.sv, line:3:1, endln:10:10 + \_module_inst: work@func_block_top (work@func_block_top), file:${SURELOG_DIR}/tests/ParamInFunc/dut.sv, line:3:1, endln:10:10 |vpiName:out3 |vpiFullName:work@func_block_top.out3 |vpiTopModule:1 |vpiPort: \_port: (inp), line:3:23, endln:3:26 |vpiParent: - \_module: work@func_block_top (work@func_block_top), file:${SURELOG_DIR}/tests/ParamInFunc/dut.sv, line:3:1, endln:10:10 + \_module_inst: work@func_block_top (work@func_block_top), file:${SURELOG_DIR}/tests/ParamInFunc/dut.sv, line:3:1, endln:10:10 |vpiName:inp |vpiDirection:3 |vpiLowConn: @@ -637,11 +637,11 @@ design: (work@func_block_top) |vpiActual: \_logic_net: (work@func_block_top.inp), line:3:23, endln:3:26 |vpiInstance: - \_module: work@func_block_top (work@func_block_top), file:${SURELOG_DIR}/tests/ParamInFunc/dut.sv, line:3:1, endln:10:10 + \_module_inst: work@func_block_top (work@func_block_top), file:${SURELOG_DIR}/tests/ParamInFunc/dut.sv, line:3:1, endln:10:10 |vpiPort: \_port: (out1), line:3:28, endln:3:32 |vpiParent: - \_module: work@func_block_top (work@func_block_top), file:${SURELOG_DIR}/tests/ParamInFunc/dut.sv, line:3:1, endln:10:10 + \_module_inst: work@func_block_top (work@func_block_top), file:${SURELOG_DIR}/tests/ParamInFunc/dut.sv, line:3:1, endln:10:10 |vpiName:out1 |vpiDirection:3 |vpiLowConn: @@ -653,11 +653,11 @@ design: (work@func_block_top) |vpiActual: \_logic_net: (work@func_block_top.out1), line:3:28, endln:3:32 |vpiInstance: - \_module: work@func_block_top (work@func_block_top), file:${SURELOG_DIR}/tests/ParamInFunc/dut.sv, line:3:1, endln:10:10 + \_module_inst: work@func_block_top (work@func_block_top), file:${SURELOG_DIR}/tests/ParamInFunc/dut.sv, line:3:1, endln:10:10 |vpiPort: \_port: (out2), line:3:34, endln:3:38 |vpiParent: - \_module: work@func_block_top (work@func_block_top), file:${SURELOG_DIR}/tests/ParamInFunc/dut.sv, line:3:1, endln:10:10 + \_module_inst: work@func_block_top (work@func_block_top), file:${SURELOG_DIR}/tests/ParamInFunc/dut.sv, line:3:1, endln:10:10 |vpiName:out2 |vpiDirection:3 |vpiLowConn: @@ -669,11 +669,11 @@ design: (work@func_block_top) |vpiActual: \_logic_net: (work@func_block_top.out2), line:3:34, endln:3:38 |vpiInstance: - \_module: work@func_block_top (work@func_block_top), file:${SURELOG_DIR}/tests/ParamInFunc/dut.sv, line:3:1, endln:10:10 + \_module_inst: work@func_block_top (work@func_block_top), file:${SURELOG_DIR}/tests/ParamInFunc/dut.sv, line:3:1, endln:10:10 |vpiPort: \_port: (out3), line:3:40, endln:3:44 |vpiParent: - \_module: work@func_block_top (work@func_block_top), file:${SURELOG_DIR}/tests/ParamInFunc/dut.sv, line:3:1, endln:10:10 + \_module_inst: work@func_block_top (work@func_block_top), file:${SURELOG_DIR}/tests/ParamInFunc/dut.sv, line:3:1, endln:10:10 |vpiName:out3 |vpiDirection:3 |vpiLowConn: @@ -685,7 +685,7 @@ design: (work@func_block_top) |vpiActual: \_logic_net: (work@func_block_top.out3), line:3:40, endln:3:44 |vpiInstance: - \_module: work@func_block_top (work@func_block_top), file:${SURELOG_DIR}/tests/ParamInFunc/dut.sv, line:3:1, endln:10:10 + \_module_inst: work@func_block_top (work@func_block_top), file:${SURELOG_DIR}/tests/ParamInFunc/dut.sv, line:3:1, endln:10:10 =================== [ FATAL] : 0 [ SYNTAX] : 0 diff --git a/tests/ParamIndex/ParamIndex.log b/tests/ParamIndex/ParamIndex.log index bdb24c3593..dd40400c3a 100644 --- a/tests/ParamIndex/ParamIndex.log +++ b/tests/ParamIndex/ParamIndex.log @@ -323,7 +323,7 @@ int_var 8 logic_net 6 logic_typespec 6 logic_var 6 -module 15 +module_inst 15 param_assign 10 parameter 10 range 8 @@ -340,7 +340,7 @@ int_var 8 logic_net 6 logic_typespec 6 logic_var 6 -module 15 +module_inst 15 param_assign 10 parameter 10 range 8 @@ -360,14 +360,14 @@ design: (work@top) |vpiElaborated:1 |vpiName:work@top |uhdmallModules: -\_module: work@bottom (work@bottom), file:${SURELOG_DIR}/tests/ParamIndex/dut.sv, line:19:1, endln:23:10 +\_module_inst: work@bottom (work@bottom), file:${SURELOG_DIR}/tests/ParamIndex/dut.sv, line:19:1, endln:23:10 |vpiParent: \_design: (work@top) |vpiFullName:work@bottom |vpiParameter: \_type_parameter: (work@bottom.TP1), line:19:32, endln:19:35 |vpiParent: - \_module: work@bottom (work@bottom), file:${SURELOG_DIR}/tests/ParamIndex/dut.sv, line:19:1, endln:23:10 + \_module_inst: work@bottom (work@bottom), file:${SURELOG_DIR}/tests/ParamIndex/dut.sv, line:19:1, endln:23:10 |vpiName:TP1 |vpiFullName:work@bottom.TP1 |vpiTypespec: @@ -377,7 +377,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@bottom.SIZE), line:19:55, endln:19:59 |vpiParent: - \_module: work@bottom (work@bottom), file:${SURELOG_DIR}/tests/ParamIndex/dut.sv, line:19:1, endln:23:10 + \_module_inst: work@bottom (work@bottom), file:${SURELOG_DIR}/tests/ParamIndex/dut.sv, line:19:1, endln:23:10 |UINT:10 |vpiTypespec: \_int_typespec: @@ -386,7 +386,7 @@ design: (work@top) |vpiParameter: \_type_parameter: (work@bottom.TP2), line:19:79, endln:19:82 |vpiParent: - \_module: work@bottom (work@bottom), file:${SURELOG_DIR}/tests/ParamIndex/dut.sv, line:19:1, endln:23:10 + \_module_inst: work@bottom (work@bottom), file:${SURELOG_DIR}/tests/ParamIndex/dut.sv, line:19:1, endln:23:10 |vpiName:TP2 |vpiFullName:work@bottom.TP2 |vpiTypespec: @@ -397,7 +397,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@bottom.PPP), line:19:104, endln:19:107 |vpiParent: - \_module: work@bottom (work@bottom), file:${SURELOG_DIR}/tests/ParamIndex/dut.sv, line:19:1, endln:23:10 + \_module_inst: work@bottom (work@bottom), file:${SURELOG_DIR}/tests/ParamIndex/dut.sv, line:19:1, endln:23:10 |UINT:1150 |vpiTypespec: \_int_typespec: , line:19:100, endln:19:103 @@ -410,7 +410,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:19:55, endln:19:62 |vpiParent: - \_module: work@bottom (work@bottom), file:${SURELOG_DIR}/tests/ParamIndex/dut.sv, line:19:1, endln:23:10 + \_module_inst: work@bottom (work@bottom), file:${SURELOG_DIR}/tests/ParamIndex/dut.sv, line:19:1, endln:23:10 |vpiRhs: \_constant: , line:19:60, endln:19:62 |vpiDecompile:10 @@ -424,7 +424,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:19:104, endln:19:114 |vpiParent: - \_module: work@bottom (work@bottom), file:${SURELOG_DIR}/tests/ParamIndex/dut.sv, line:19:1, endln:23:10 + \_module_inst: work@bottom (work@bottom), file:${SURELOG_DIR}/tests/ParamIndex/dut.sv, line:19:1, endln:23:10 |vpiRhs: \_constant: , line:19:110, endln:19:114 |vpiDecompile:1150 @@ -439,31 +439,31 @@ design: (work@top) |vpiNet: \_logic_net: (work@bottom.DATA1), line:20:9, endln:20:14 |vpiParent: - \_module: work@bottom (work@bottom), file:${SURELOG_DIR}/tests/ParamIndex/dut.sv, line:19:1, endln:23:10 + \_module_inst: work@bottom (work@bottom), file:${SURELOG_DIR}/tests/ParamIndex/dut.sv, line:19:1, endln:23:10 |vpiName:DATA1 |vpiFullName:work@bottom.DATA1 |vpiNet: \_logic_net: (work@bottom.a), line:21:20, endln:21:21 |vpiParent: - \_module: work@bottom (work@bottom), file:${SURELOG_DIR}/tests/ParamIndex/dut.sv, line:19:1, endln:23:10 + \_module_inst: work@bottom (work@bottom), file:${SURELOG_DIR}/tests/ParamIndex/dut.sv, line:19:1, endln:23:10 |vpiName:a |vpiFullName:work@bottom.a |vpiNetType:36 |vpiNet: \_logic_net: (work@bottom.DATA2), line:22:9, endln:22:14 |vpiParent: - \_module: work@bottom (work@bottom), file:${SURELOG_DIR}/tests/ParamIndex/dut.sv, line:19:1, endln:23:10 + \_module_inst: work@bottom (work@bottom), file:${SURELOG_DIR}/tests/ParamIndex/dut.sv, line:19:1, endln:23:10 |vpiName:DATA2 |vpiFullName:work@bottom.DATA2 |uhdmallModules: -\_module: work@mid (work@mid), file:${SURELOG_DIR}/tests/ParamIndex/dut.sv, line:11:1, endln:17:10 +\_module_inst: work@mid (work@mid), file:${SURELOG_DIR}/tests/ParamIndex/dut.sv, line:11:1, endln:17:10 |vpiParent: \_design: (work@top) |vpiFullName:work@mid |vpiParameter: \_type_parameter: (work@mid.TP0), line:11:29, endln:11:32 |vpiParent: - \_module: work@mid (work@mid), file:${SURELOG_DIR}/tests/ParamIndex/dut.sv, line:11:1, endln:17:10 + \_module_inst: work@mid (work@mid), file:${SURELOG_DIR}/tests/ParamIndex/dut.sv, line:11:1, endln:17:10 |vpiName:TP0 |vpiFullName:work@mid.TP0 |vpiTypespec: @@ -474,18 +474,18 @@ design: (work@top) |vpiNet: \_logic_net: (work@mid.DATA0), line:12:6, endln:12:11 |vpiParent: - \_module: work@mid (work@mid), file:${SURELOG_DIR}/tests/ParamIndex/dut.sv, line:11:1, endln:17:10 + \_module_inst: work@mid (work@mid), file:${SURELOG_DIR}/tests/ParamIndex/dut.sv, line:11:1, endln:17:10 |vpiName:DATA0 |vpiFullName:work@mid.DATA0 |uhdmallModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamIndex/dut.sv, line:2:1, endln:9:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamIndex/dut.sv, line:2:1, endln:9:10 |vpiParent: \_design: (work@top) |vpiFullName:work@top |vpiParameter: \_type_parameter: (work@top.TPTOP), line:3:16, endln:3:21 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamIndex/dut.sv, line:2:1, endln:9:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamIndex/dut.sv, line:2:1, endln:9:10 |vpiName:TPTOP |vpiFullName:work@top.TPTOP |vpiTypespec: @@ -497,16 +497,16 @@ design: (work@top) |vpiNet: \_logic_net: (work@top.DATATOP), line:5:8, endln:5:15 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamIndex/dut.sv, line:2:1, endln:9:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamIndex/dut.sv, line:2:1, endln:9:10 |vpiName:DATATOP |vpiFullName:work@top.DATATOP |uhdmtopModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamIndex/dut.sv, line:2:1, endln:9:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamIndex/dut.sv, line:2:1, endln:9:10 |vpiName:work@top |vpiVariables: \_int_var: (work@top.DATATOP), line:5:8, endln:5:15 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamIndex/dut.sv, line:2:1, endln:9:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamIndex/dut.sv, line:2:1, endln:9:10 |vpiTypespec: \_int_typespec: , line:3:24, endln:3:27 |vpiName:DATATOP @@ -517,16 +517,16 @@ design: (work@top) |vpiDefName:work@top |vpiTop:1 |vpiTopModule:1 - |vpiModule: - \_module: work@mid (work@top.u0), file:${SURELOG_DIR}/tests/ParamIndex/dut.sv, line:7:3, endln:7:27 + |vpiModuleInst: + \_module_inst: work@mid (work@top.u0), file:${SURELOG_DIR}/tests/ParamIndex/dut.sv, line:7:3, endln:7:27 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamIndex/dut.sv, line:2:1, endln:9:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamIndex/dut.sv, line:2:1, endln:9:10 |vpiName:u0 |vpiFullName:work@top.u0 |vpiVariables: \_int_var: (work@top.u0.DATA0), line:12:6, endln:12:11 |vpiParent: - \_module: work@mid (work@top.u0), file:${SURELOG_DIR}/tests/ParamIndex/dut.sv, line:7:3, endln:7:27 + \_module_inst: work@mid (work@top.u0), file:${SURELOG_DIR}/tests/ParamIndex/dut.sv, line:7:3, endln:7:27 |vpiTypespec: \_int_typespec: , line:3:24, endln:3:27 |vpiParent: @@ -538,7 +538,7 @@ design: (work@top) |vpiParameter: \_type_parameter: (work@top.u0.TP0) |vpiParent: - \_module: work@mid (work@top.u0), file:${SURELOG_DIR}/tests/ParamIndex/dut.sv, line:7:3, endln:7:27 + \_module_inst: work@mid (work@top.u0), file:${SURELOG_DIR}/tests/ParamIndex/dut.sv, line:7:3, endln:7:27 |vpiName:TP0 |vpiFullName:work@top.u0.TP0 |vpiTypespec: @@ -551,17 +551,17 @@ design: (work@top) |vpiName:UNDEF |vpiNetType:1 |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamIndex/dut.sv, line:2:1, endln:9:10 - |vpiModule: - \_module: work@bottom (work@top.u0.u1), file:${SURELOG_DIR}/tests/ParamIndex/dut.sv, line:13:2, endln:13:27 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamIndex/dut.sv, line:2:1, endln:9:10 + |vpiModuleInst: + \_module_inst: work@bottom (work@top.u0.u1), file:${SURELOG_DIR}/tests/ParamIndex/dut.sv, line:13:2, endln:13:27 |vpiParent: - \_module: work@mid (work@top.u0), file:${SURELOG_DIR}/tests/ParamIndex/dut.sv, line:7:3, endln:7:27 + \_module_inst: work@mid (work@top.u0), file:${SURELOG_DIR}/tests/ParamIndex/dut.sv, line:7:3, endln:7:27 |vpiName:u1 |vpiFullName:work@top.u0.u1 |vpiVariables: \_int_var: (work@top.u0.u1.DATA1), line:20:9, endln:20:14 |vpiParent: - \_module: work@bottom (work@top.u0.u1), file:${SURELOG_DIR}/tests/ParamIndex/dut.sv, line:13:2, endln:13:27 + \_module_inst: work@bottom (work@top.u0.u1), file:${SURELOG_DIR}/tests/ParamIndex/dut.sv, line:13:2, endln:13:27 |vpiTypespec: \_int_typespec: , line:3:24, endln:3:27 |vpiParent: @@ -573,7 +573,7 @@ design: (work@top) |vpiVariables: \_logic_var: (work@top.u0.u1.a), line:21:20, endln:21:21 |vpiParent: - \_module: work@bottom (work@top.u0.u1), file:${SURELOG_DIR}/tests/ParamIndex/dut.sv, line:13:2, endln:13:27 + \_module_inst: work@bottom (work@top.u0.u1), file:${SURELOG_DIR}/tests/ParamIndex/dut.sv, line:13:2, endln:13:27 |vpiTypespec: \_logic_typespec: , line:21:5, endln:21:19 |vpiRange: @@ -618,7 +618,7 @@ design: (work@top) |vpiVariables: \_int_var: (work@top.u0.u1.DATA2), line:22:9, endln:22:14 |vpiParent: - \_module: work@bottom (work@top.u0.u1), file:${SURELOG_DIR}/tests/ParamIndex/dut.sv, line:13:2, endln:13:27 + \_module_inst: work@bottom (work@top.u0.u1), file:${SURELOG_DIR}/tests/ParamIndex/dut.sv, line:13:2, endln:13:27 |vpiTypespec: \_int_typespec: , line:19:85, endln:19:88 |vpiName:DATA2 @@ -627,7 +627,7 @@ design: (work@top) |vpiParameter: \_type_parameter: (work@top.u0.u1.TP1) |vpiParent: - \_module: work@bottom (work@top.u0.u1), file:${SURELOG_DIR}/tests/ParamIndex/dut.sv, line:13:2, endln:13:27 + \_module_inst: work@bottom (work@top.u0.u1), file:${SURELOG_DIR}/tests/ParamIndex/dut.sv, line:13:2, endln:13:27 |vpiName:TP1 |vpiFullName:work@top.u0.u1.TP1 |vpiTypespec: @@ -635,7 +635,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.u0.u1.SIZE), line:19:55, endln:19:59 |vpiParent: - \_module: work@bottom (work@top.u0.u1), file:${SURELOG_DIR}/tests/ParamIndex/dut.sv, line:13:2, endln:13:27 + \_module_inst: work@bottom (work@top.u0.u1), file:${SURELOG_DIR}/tests/ParamIndex/dut.sv, line:13:2, endln:13:27 |UINT:10 |vpiTypespec: \_int_typespec: @@ -648,7 +648,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.u0.u1.PPP), line:19:104, endln:19:107 |vpiParent: - \_module: work@bottom (work@top.u0.u1), file:${SURELOG_DIR}/tests/ParamIndex/dut.sv, line:13:2, endln:13:27 + \_module_inst: work@bottom (work@top.u0.u1), file:${SURELOG_DIR}/tests/ParamIndex/dut.sv, line:13:2, endln:13:27 |UINT:1150 |vpiTypespec: \_int_typespec: , line:19:100, endln:19:103 @@ -661,7 +661,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:19:55, endln:19:62 |vpiParent: - \_module: work@bottom (work@top.u0.u1), file:${SURELOG_DIR}/tests/ParamIndex/dut.sv, line:13:2, endln:13:27 + \_module_inst: work@bottom (work@top.u0.u1), file:${SURELOG_DIR}/tests/ParamIndex/dut.sv, line:13:2, endln:13:27 |vpiRhs: \_constant: , line:19:60, endln:19:62 |vpiDecompile:10 @@ -675,7 +675,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:19:104, endln:19:114 |vpiParent: - \_module: work@bottom (work@top.u0.u1), file:${SURELOG_DIR}/tests/ParamIndex/dut.sv, line:13:2, endln:13:27 + \_module_inst: work@bottom (work@top.u0.u1), file:${SURELOG_DIR}/tests/ParamIndex/dut.sv, line:13:2, endln:13:27 |vpiRhs: \_constant: , line:19:110, endln:19:114 |vpiDecompile:1150 @@ -690,17 +690,17 @@ design: (work@top) |vpiDefFile:${SURELOG_DIR}/tests/ParamIndex/dut.sv |vpiDefLineNo:19 |vpiInstance: - \_module: work@mid (work@top.u0), file:${SURELOG_DIR}/tests/ParamIndex/dut.sv, line:7:3, endln:7:27 - |vpiModule: - \_module: work@bottom (work@top.u0.u2), file:${SURELOG_DIR}/tests/ParamIndex/dut.sv, line:14:2, endln:14:38 + \_module_inst: work@mid (work@top.u0), file:${SURELOG_DIR}/tests/ParamIndex/dut.sv, line:7:3, endln:7:27 + |vpiModuleInst: + \_module_inst: work@bottom (work@top.u0.u2), file:${SURELOG_DIR}/tests/ParamIndex/dut.sv, line:14:2, endln:14:38 |vpiParent: - \_module: work@mid (work@top.u0), file:${SURELOG_DIR}/tests/ParamIndex/dut.sv, line:7:3, endln:7:27 + \_module_inst: work@mid (work@top.u0), file:${SURELOG_DIR}/tests/ParamIndex/dut.sv, line:7:3, endln:7:27 |vpiName:u2 |vpiFullName:work@top.u0.u2 |vpiVariables: \_int_var: (work@top.u0.u2.DATA1), line:20:9, endln:20:14 |vpiParent: - \_module: work@bottom (work@top.u0.u2), file:${SURELOG_DIR}/tests/ParamIndex/dut.sv, line:14:2, endln:14:38 + \_module_inst: work@bottom (work@top.u0.u2), file:${SURELOG_DIR}/tests/ParamIndex/dut.sv, line:14:2, endln:14:38 |vpiTypespec: \_int_typespec: , line:14:16, endln:14:19 |vpiParent: @@ -712,7 +712,7 @@ design: (work@top) |vpiVariables: \_logic_var: (work@top.u0.u2.a), line:21:20, endln:21:21 |vpiParent: - \_module: work@bottom (work@top.u0.u2), file:${SURELOG_DIR}/tests/ParamIndex/dut.sv, line:14:2, endln:14:38 + \_module_inst: work@bottom (work@top.u0.u2), file:${SURELOG_DIR}/tests/ParamIndex/dut.sv, line:14:2, endln:14:38 |vpiTypespec: \_logic_typespec: , line:21:5, endln:21:19 |vpiRange: @@ -757,7 +757,7 @@ design: (work@top) |vpiVariables: \_int_var: (work@top.u0.u2.DATA2), line:22:9, endln:22:14 |vpiParent: - \_module: work@bottom (work@top.u0.u2), file:${SURELOG_DIR}/tests/ParamIndex/dut.sv, line:14:2, endln:14:38 + \_module_inst: work@bottom (work@top.u0.u2), file:${SURELOG_DIR}/tests/ParamIndex/dut.sv, line:14:2, endln:14:38 |vpiTypespec: \_int_typespec: , line:19:85, endln:19:88 |vpiName:DATA2 @@ -766,7 +766,7 @@ design: (work@top) |vpiParameter: \_type_parameter: (work@top.u0.u2.TP1) |vpiParent: - \_module: work@bottom (work@top.u0.u2), file:${SURELOG_DIR}/tests/ParamIndex/dut.sv, line:14:2, endln:14:38 + \_module_inst: work@bottom (work@top.u0.u2), file:${SURELOG_DIR}/tests/ParamIndex/dut.sv, line:14:2, endln:14:38 |vpiName:TP1 |vpiFullName:work@top.u0.u2.TP1 |vpiTypespec: @@ -774,7 +774,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.u0.u2.SIZE), line:19:55, endln:19:59 |vpiParent: - \_module: work@bottom (work@top.u0.u2), file:${SURELOG_DIR}/tests/ParamIndex/dut.sv, line:14:2, endln:14:38 + \_module_inst: work@bottom (work@top.u0.u2), file:${SURELOG_DIR}/tests/ParamIndex/dut.sv, line:14:2, endln:14:38 |UINT:10 |vpiTypespec: \_int_typespec: @@ -787,7 +787,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.u0.u2.PPP), line:19:104, endln:19:107 |vpiParent: - \_module: work@bottom (work@top.u0.u2), file:${SURELOG_DIR}/tests/ParamIndex/dut.sv, line:14:2, endln:14:38 + \_module_inst: work@bottom (work@top.u0.u2), file:${SURELOG_DIR}/tests/ParamIndex/dut.sv, line:14:2, endln:14:38 |UINT:1150 |vpiTypespec: \_int_typespec: , line:19:100, endln:19:103 @@ -800,7 +800,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:19:55, endln:19:62 |vpiParent: - \_module: work@bottom (work@top.u0.u2), file:${SURELOG_DIR}/tests/ParamIndex/dut.sv, line:14:2, endln:14:38 + \_module_inst: work@bottom (work@top.u0.u2), file:${SURELOG_DIR}/tests/ParamIndex/dut.sv, line:14:2, endln:14:38 |vpiOverriden:1 |vpiRhs: \_constant: , line:19:60, endln:19:62 @@ -815,7 +815,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:19:104, endln:19:114 |vpiParent: - \_module: work@bottom (work@top.u0.u2), file:${SURELOG_DIR}/tests/ParamIndex/dut.sv, line:14:2, endln:14:38 + \_module_inst: work@bottom (work@top.u0.u2), file:${SURELOG_DIR}/tests/ParamIndex/dut.sv, line:14:2, endln:14:38 |vpiRhs: \_constant: , line:19:110, endln:19:114 |vpiDecompile:1150 @@ -830,17 +830,17 @@ design: (work@top) |vpiDefFile:${SURELOG_DIR}/tests/ParamIndex/dut.sv |vpiDefLineNo:19 |vpiInstance: - \_module: work@mid (work@top.u0), file:${SURELOG_DIR}/tests/ParamIndex/dut.sv, line:7:3, endln:7:27 - |vpiModule: - \_module: work@bottom (work@top.u0.u3), file:${SURELOG_DIR}/tests/ParamIndex/dut.sv, line:15:2, endln:15:38 + \_module_inst: work@mid (work@top.u0), file:${SURELOG_DIR}/tests/ParamIndex/dut.sv, line:7:3, endln:7:27 + |vpiModuleInst: + \_module_inst: work@bottom (work@top.u0.u3), file:${SURELOG_DIR}/tests/ParamIndex/dut.sv, line:15:2, endln:15:38 |vpiParent: - \_module: work@mid (work@top.u0), file:${SURELOG_DIR}/tests/ParamIndex/dut.sv, line:7:3, endln:7:27 + \_module_inst: work@mid (work@top.u0), file:${SURELOG_DIR}/tests/ParamIndex/dut.sv, line:7:3, endln:7:27 |vpiName:u3 |vpiFullName:work@top.u0.u3 |vpiVariables: \_logic_var: (work@top.u0.u3.DATA1), line:20:9, endln:20:14 |vpiParent: - \_module: work@bottom (work@top.u0.u3), file:${SURELOG_DIR}/tests/ParamIndex/dut.sv, line:15:2, endln:15:38 + \_module_inst: work@bottom (work@top.u0.u3), file:${SURELOG_DIR}/tests/ParamIndex/dut.sv, line:15:2, endln:15:38 |vpiTypespec: \_logic_typespec: , line:19:38, endln:19:43 |vpiName:DATA1 @@ -849,7 +849,7 @@ design: (work@top) |vpiVariables: \_logic_var: (work@top.u0.u3.a), line:21:20, endln:21:21 |vpiParent: - \_module: work@bottom (work@top.u0.u3), file:${SURELOG_DIR}/tests/ParamIndex/dut.sv, line:15:2, endln:15:38 + \_module_inst: work@bottom (work@top.u0.u3), file:${SURELOG_DIR}/tests/ParamIndex/dut.sv, line:15:2, endln:15:38 |vpiTypespec: \_logic_typespec: , line:21:5, endln:21:19 |vpiRange: @@ -894,7 +894,7 @@ design: (work@top) |vpiVariables: \_int_var: (work@top.u0.u3.DATA2), line:22:9, endln:22:14 |vpiParent: - \_module: work@bottom (work@top.u0.u3), file:${SURELOG_DIR}/tests/ParamIndex/dut.sv, line:15:2, endln:15:38 + \_module_inst: work@bottom (work@top.u0.u3), file:${SURELOG_DIR}/tests/ParamIndex/dut.sv, line:15:2, endln:15:38 |vpiTypespec: \_int_typespec: , line:19:85, endln:19:88 |vpiName:DATA2 @@ -905,7 +905,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.u0.u3.SIZE), line:19:55, endln:19:59 |vpiParent: - \_module: work@bottom (work@top.u0.u3), file:${SURELOG_DIR}/tests/ParamIndex/dut.sv, line:15:2, endln:15:38 + \_module_inst: work@bottom (work@top.u0.u3), file:${SURELOG_DIR}/tests/ParamIndex/dut.sv, line:15:2, endln:15:38 |UINT:10 |vpiTypespec: \_int_typespec: @@ -918,7 +918,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.u0.u3.PPP), line:19:104, endln:19:107 |vpiParent: - \_module: work@bottom (work@top.u0.u3), file:${SURELOG_DIR}/tests/ParamIndex/dut.sv, line:15:2, endln:15:38 + \_module_inst: work@bottom (work@top.u0.u3), file:${SURELOG_DIR}/tests/ParamIndex/dut.sv, line:15:2, endln:15:38 |UINT:1150 |vpiTypespec: \_int_typespec: , line:19:100, endln:19:103 @@ -931,7 +931,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:19:55, endln:19:62 |vpiParent: - \_module: work@bottom (work@top.u0.u3), file:${SURELOG_DIR}/tests/ParamIndex/dut.sv, line:15:2, endln:15:38 + \_module_inst: work@bottom (work@top.u0.u3), file:${SURELOG_DIR}/tests/ParamIndex/dut.sv, line:15:2, endln:15:38 |vpiOverriden:1 |vpiRhs: \_constant: , line:19:60, endln:19:62 @@ -946,7 +946,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:19:104, endln:19:114 |vpiParent: - \_module: work@bottom (work@top.u0.u3), file:${SURELOG_DIR}/tests/ParamIndex/dut.sv, line:15:2, endln:15:38 + \_module_inst: work@bottom (work@top.u0.u3), file:${SURELOG_DIR}/tests/ParamIndex/dut.sv, line:15:2, endln:15:38 |vpiOverriden:1 |vpiRhs: \_constant: , line:19:110, endln:19:114 @@ -962,17 +962,17 @@ design: (work@top) |vpiDefFile:${SURELOG_DIR}/tests/ParamIndex/dut.sv |vpiDefLineNo:19 |vpiInstance: - \_module: work@mid (work@top.u0), file:${SURELOG_DIR}/tests/ParamIndex/dut.sv, line:7:3, endln:7:27 - |vpiModule: - \_module: work@bottom (work@top.u0.u4), file:${SURELOG_DIR}/tests/ParamIndex/dut.sv, line:16:2, endln:16:39 + \_module_inst: work@mid (work@top.u0), file:${SURELOG_DIR}/tests/ParamIndex/dut.sv, line:7:3, endln:7:27 + |vpiModuleInst: + \_module_inst: work@bottom (work@top.u0.u4), file:${SURELOG_DIR}/tests/ParamIndex/dut.sv, line:16:2, endln:16:39 |vpiParent: - \_module: work@mid (work@top.u0), file:${SURELOG_DIR}/tests/ParamIndex/dut.sv, line:7:3, endln:7:27 + \_module_inst: work@mid (work@top.u0), file:${SURELOG_DIR}/tests/ParamIndex/dut.sv, line:7:3, endln:7:27 |vpiName:u4 |vpiFullName:work@top.u0.u4 |vpiVariables: \_logic_var: (work@top.u0.u4.DATA1), line:20:9, endln:20:14 |vpiParent: - \_module: work@bottom (work@top.u0.u4), file:${SURELOG_DIR}/tests/ParamIndex/dut.sv, line:16:2, endln:16:39 + \_module_inst: work@bottom (work@top.u0.u4), file:${SURELOG_DIR}/tests/ParamIndex/dut.sv, line:16:2, endln:16:39 |vpiTypespec: \_logic_typespec: , line:19:38, endln:19:43 |vpiName:DATA1 @@ -981,7 +981,7 @@ design: (work@top) |vpiVariables: \_logic_var: (work@top.u0.u4.a), line:21:20, endln:21:21 |vpiParent: - \_module: work@bottom (work@top.u0.u4), file:${SURELOG_DIR}/tests/ParamIndex/dut.sv, line:16:2, endln:16:39 + \_module_inst: work@bottom (work@top.u0.u4), file:${SURELOG_DIR}/tests/ParamIndex/dut.sv, line:16:2, endln:16:39 |vpiTypespec: \_logic_typespec: , line:21:5, endln:21:19 |vpiRange: @@ -1026,7 +1026,7 @@ design: (work@top) |vpiVariables: \_int_var: (work@top.u0.u4.DATA2), line:22:9, endln:22:14 |vpiParent: - \_module: work@bottom (work@top.u0.u4), file:${SURELOG_DIR}/tests/ParamIndex/dut.sv, line:16:2, endln:16:39 + \_module_inst: work@bottom (work@top.u0.u4), file:${SURELOG_DIR}/tests/ParamIndex/dut.sv, line:16:2, endln:16:39 |vpiTypespec: \_int_typespec: , line:19:85, endln:19:88 |vpiName:DATA2 @@ -1037,7 +1037,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.u0.u4.SIZE), line:19:55, endln:19:59 |vpiParent: - \_module: work@bottom (work@top.u0.u4), file:${SURELOG_DIR}/tests/ParamIndex/dut.sv, line:16:2, endln:16:39 + \_module_inst: work@bottom (work@top.u0.u4), file:${SURELOG_DIR}/tests/ParamIndex/dut.sv, line:16:2, endln:16:39 |UINT:10 |vpiTypespec: \_int_typespec: @@ -1050,7 +1050,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.u0.u4.PPP), line:19:104, endln:19:107 |vpiParent: - \_module: work@bottom (work@top.u0.u4), file:${SURELOG_DIR}/tests/ParamIndex/dut.sv, line:16:2, endln:16:39 + \_module_inst: work@bottom (work@top.u0.u4), file:${SURELOG_DIR}/tests/ParamIndex/dut.sv, line:16:2, endln:16:39 |UINT:1150 |vpiTypespec: \_int_typespec: , line:19:100, endln:19:103 @@ -1063,7 +1063,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:19:55, endln:19:62 |vpiParent: - \_module: work@bottom (work@top.u0.u4), file:${SURELOG_DIR}/tests/ParamIndex/dut.sv, line:16:2, endln:16:39 + \_module_inst: work@bottom (work@top.u0.u4), file:${SURELOG_DIR}/tests/ParamIndex/dut.sv, line:16:2, endln:16:39 |vpiOverriden:1 |vpiRhs: \_constant: , line:19:60, endln:19:62 @@ -1078,7 +1078,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:19:104, endln:19:114 |vpiParent: - \_module: work@bottom (work@top.u0.u4), file:${SURELOG_DIR}/tests/ParamIndex/dut.sv, line:16:2, endln:16:39 + \_module_inst: work@bottom (work@top.u0.u4), file:${SURELOG_DIR}/tests/ParamIndex/dut.sv, line:16:2, endln:16:39 |vpiRhs: \_constant: , line:19:110, endln:19:114 |vpiDecompile:1150 @@ -1093,7 +1093,7 @@ design: (work@top) |vpiDefFile:${SURELOG_DIR}/tests/ParamIndex/dut.sv |vpiDefLineNo:19 |vpiInstance: - \_module: work@mid (work@top.u0), file:${SURELOG_DIR}/tests/ParamIndex/dut.sv, line:7:3, endln:7:27 + \_module_inst: work@mid (work@top.u0), file:${SURELOG_DIR}/tests/ParamIndex/dut.sv, line:7:3, endln:7:27 =================== [ FATAL] : 0 [ SYNTAX] : 0 diff --git a/tests/ParamLine/ParamLine.log b/tests/ParamLine/ParamLine.log index 34528e4327..5ebce002df 100644 --- a/tests/ParamLine/ParamLine.log +++ b/tests/ParamLine/ParamLine.log @@ -44,21 +44,21 @@ design: (work@top) |vpiElaborated:1 |vpiName:work@top |uhdmallModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamLine/dut.sv, line:1:1, endln:33:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamLine/dut.sv, line:1:1, endln:33:10 |vpiParent: \_design: (work@top) |vpiFullName:work@top |vpiParameter: \_parameter: (work@top.p), line:2:15, endln:2:16 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamLine/dut.sv, line:1:1, endln:33:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamLine/dut.sv, line:1:1, endln:33:10 |BIN:0 |vpiName:p |vpiFullName:work@top.p |vpiParamAssign: \_param_assign: , line:2:15, endln:2:23 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamLine/dut.sv, line:1:1, endln:33:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamLine/dut.sv, line:1:1, endln:33:10 |vpiRhs: \_constant: , line:2:19, endln:2:23 |vpiDecompile:1'b0 @@ -79,19 +79,19 @@ design: (work@top) \_parameter: (work@top.p), line:2:15, endln:2:16 |vpiDefName:work@top |uhdmtopModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamLine/dut.sv, line:1:1, endln:33:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamLine/dut.sv, line:1:1, endln:33:10 |vpiName:work@top |vpiParameter: \_parameter: (work@top.p), line:2:15, endln:2:16 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamLine/dut.sv, line:1:1, endln:33:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamLine/dut.sv, line:1:1, endln:33:10 |BIN:0 |vpiName:p |vpiFullName:work@top.p |vpiParamAssign: \_param_assign: , line:2:15, endln:2:23 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamLine/dut.sv, line:1:1, endln:33:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamLine/dut.sv, line:1:1, endln:33:10 |vpiRhs: \_constant: , line:2:19, endln:2:23 |vpiDecompile:BLAH @@ -106,7 +106,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.genblk1), line:3:4, endln:5:7 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamLine/dut.sv, line:1:1, endln:33:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamLine/dut.sv, line:1:1, endln:33:10 |vpiName:genblk1 |vpiFullName:work@top.genblk1 |vpiGenScope: @@ -114,8 +114,8 @@ design: (work@top) |vpiParent: \_gen_scope_array: (work@top.genblk1), line:3:4, endln:5:7 |vpiFullName:work@top.genblk1 - |vpiModule: - \_module: work@top.genblk1::GOOD_BLAH (work@top.genblk1.good), file:${SURELOG_DIR}/tests/ParamLine/dut.sv, line:4:7, endln:4:24 + |vpiModuleInst: + \_module_inst: work@top.genblk1::GOOD_BLAH (work@top.genblk1.good), file:${SURELOG_DIR}/tests/ParamLine/dut.sv, line:4:7, endln:4:24 |vpiParent: \_gen_scope: (work@top.genblk1) |vpiName:good @@ -173,21 +173,21 @@ design: (work@top) |vpiElaborated:1 |vpiName:work@top |uhdmallModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamLine/dut.sv, line:1:1, endln:33:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamLine/dut.sv, line:1:1, endln:33:10 |vpiParent: \_design: (work@top) |vpiFullName:work@top |vpiParameter: \_parameter: (work@top.p), line:2:15, endln:2:16 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamLine/dut.sv, line:1:1, endln:33:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamLine/dut.sv, line:1:1, endln:33:10 |BIN:0 |vpiName:p |vpiFullName:work@top.p |vpiParamAssign: \_param_assign: , line:2:15, endln:2:23 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamLine/dut.sv, line:1:1, endln:33:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamLine/dut.sv, line:1:1, endln:33:10 |vpiRhs: \_constant: , line:2:19, endln:2:23 |vpiDecompile:1'b0 @@ -208,19 +208,19 @@ design: (work@top) \_parameter: (work@top.p), line:2:15, endln:2:16 |vpiDefName:work@top |uhdmtopModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamLine/dut.sv, line:1:1, endln:33:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamLine/dut.sv, line:1:1, endln:33:10 |vpiName:work@top |vpiParameter: \_parameter: (work@top.p), line:2:15, endln:2:16 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamLine/dut.sv, line:1:1, endln:33:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamLine/dut.sv, line:1:1, endln:33:10 |BIN:0 |vpiName:p |vpiFullName:work@top.p |vpiParamAssign: \_param_assign: , line:2:15, endln:2:23 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamLine/dut.sv, line:1:1, endln:33:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamLine/dut.sv, line:1:1, endln:33:10 |vpiRhs: \_constant: , line:2:19, endln:2:23 |vpiDecompile:4'b1001 @@ -235,7 +235,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.genblk2), line:6:4, endln:8:7 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamLine/dut.sv, line:1:1, endln:33:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamLine/dut.sv, line:1:1, endln:33:10 |vpiName:genblk2 |vpiFullName:work@top.genblk2 |vpiGenScope: @@ -243,8 +243,8 @@ design: (work@top) |vpiParent: \_gen_scope_array: (work@top.genblk2), line:6:4, endln:8:7 |vpiFullName:work@top.genblk2 - |vpiModule: - \_module: work@top.genblk2::GOOD_BIN1 (work@top.genblk2.good), file:${SURELOG_DIR}/tests/ParamLine/dut.sv, line:7:7, endln:7:24 + |vpiModuleInst: + \_module_inst: work@top.genblk2::GOOD_BIN1 (work@top.genblk2.good), file:${SURELOG_DIR}/tests/ParamLine/dut.sv, line:7:7, endln:7:24 |vpiParent: \_gen_scope: (work@top.genblk2) |vpiName:good @@ -294,21 +294,21 @@ design: (work@top) |vpiElaborated:1 |vpiName:work@top |uhdmallModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamLine/dut.sv, line:1:1, endln:33:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamLine/dut.sv, line:1:1, endln:33:10 |vpiParent: \_design: (work@top) |vpiFullName:work@top |vpiParameter: \_parameter: (work@top.p), line:2:15, endln:2:16 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamLine/dut.sv, line:1:1, endln:33:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamLine/dut.sv, line:1:1, endln:33:10 |BIN:0 |vpiName:p |vpiFullName:work@top.p |vpiParamAssign: \_param_assign: , line:2:15, endln:2:23 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamLine/dut.sv, line:1:1, endln:33:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamLine/dut.sv, line:1:1, endln:33:10 |vpiRhs: \_constant: , line:2:19, endln:2:23 |vpiDecompile:1'b0 @@ -329,19 +329,19 @@ design: (work@top) \_parameter: (work@top.p), line:2:15, endln:2:16 |vpiDefName:work@top |uhdmtopModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamLine/dut.sv, line:1:1, endln:33:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamLine/dut.sv, line:1:1, endln:33:10 |vpiName:work@top |vpiParameter: \_parameter: (work@top.p), line:2:15, endln:2:16 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamLine/dut.sv, line:1:1, endln:33:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamLine/dut.sv, line:1:1, endln:33:10 |BIN:0 |vpiName:p |vpiFullName:work@top.p |vpiParamAssign: \_param_assign: , line:2:15, endln:2:23 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamLine/dut.sv, line:1:1, endln:33:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamLine/dut.sv, line:1:1, endln:33:10 |vpiRhs: \_constant: , line:2:19, endln:2:23 |vpiDecompile:'b1002 @@ -404,21 +404,21 @@ design: (work@top) |vpiElaborated:1 |vpiName:work@top |uhdmallModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamLine/dut.sv, line:1:1, endln:33:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamLine/dut.sv, line:1:1, endln:33:10 |vpiParent: \_design: (work@top) |vpiFullName:work@top |vpiParameter: \_parameter: (work@top.p), line:2:15, endln:2:16 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamLine/dut.sv, line:1:1, endln:33:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamLine/dut.sv, line:1:1, endln:33:10 |BIN:0 |vpiName:p |vpiFullName:work@top.p |vpiParamAssign: \_param_assign: , line:2:15, endln:2:23 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamLine/dut.sv, line:1:1, endln:33:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamLine/dut.sv, line:1:1, endln:33:10 |vpiRhs: \_constant: , line:2:19, endln:2:23 |vpiDecompile:1'b0 @@ -439,19 +439,19 @@ design: (work@top) \_parameter: (work@top.p), line:2:15, endln:2:16 |vpiDefName:work@top |uhdmtopModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamLine/dut.sv, line:1:1, endln:33:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamLine/dut.sv, line:1:1, endln:33:10 |vpiName:work@top |vpiParameter: \_parameter: (work@top.p), line:2:15, endln:2:16 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamLine/dut.sv, line:1:1, endln:33:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamLine/dut.sv, line:1:1, endln:33:10 |BIN:0 |vpiName:p |vpiFullName:work@top.p |vpiParamAssign: \_param_assign: , line:2:15, endln:2:23 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamLine/dut.sv, line:1:1, endln:33:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamLine/dut.sv, line:1:1, endln:33:10 |vpiRhs: \_constant: , line:2:19, endln:2:23 |vpiDecompile:'hFF @@ -465,7 +465,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.genblk4), line:12:4, endln:14:7 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamLine/dut.sv, line:1:1, endln:33:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamLine/dut.sv, line:1:1, endln:33:10 |vpiName:genblk4 |vpiFullName:work@top.genblk4 |vpiGenScope: @@ -473,8 +473,8 @@ design: (work@top) |vpiParent: \_gen_scope_array: (work@top.genblk4), line:12:4, endln:14:7 |vpiFullName:work@top.genblk4 - |vpiModule: - \_module: work@top.genblk4::GOOD_HEXA (work@top.genblk4.good), file:${SURELOG_DIR}/tests/ParamLine/dut.sv, line:13:7, endln:13:24 + |vpiModuleInst: + \_module_inst: work@top.genblk4::GOOD_HEXA (work@top.genblk4.good), file:${SURELOG_DIR}/tests/ParamLine/dut.sv, line:13:7, endln:13:24 |vpiParent: \_gen_scope: (work@top.genblk4) |vpiName:good @@ -532,21 +532,21 @@ design: (work@top) |vpiElaborated:1 |vpiName:work@top |uhdmallModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamLine/dut.sv, line:1:1, endln:33:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamLine/dut.sv, line:1:1, endln:33:10 |vpiParent: \_design: (work@top) |vpiFullName:work@top |vpiParameter: \_parameter: (work@top.p), line:2:15, endln:2:16 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamLine/dut.sv, line:1:1, endln:33:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamLine/dut.sv, line:1:1, endln:33:10 |BIN:0 |vpiName:p |vpiFullName:work@top.p |vpiParamAssign: \_param_assign: , line:2:15, endln:2:23 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamLine/dut.sv, line:1:1, endln:33:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamLine/dut.sv, line:1:1, endln:33:10 |vpiRhs: \_constant: , line:2:19, endln:2:23 |vpiDecompile:1'b0 @@ -567,19 +567,19 @@ design: (work@top) \_parameter: (work@top.p), line:2:15, endln:2:16 |vpiDefName:work@top |uhdmtopModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamLine/dut.sv, line:1:1, endln:33:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamLine/dut.sv, line:1:1, endln:33:10 |vpiName:work@top |vpiParameter: \_parameter: (work@top.p), line:2:15, endln:2:16 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamLine/dut.sv, line:1:1, endln:33:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamLine/dut.sv, line:1:1, endln:33:10 |BIN:0 |vpiName:p |vpiFullName:work@top.p |vpiParamAssign: \_param_assign: , line:2:15, endln:2:23 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamLine/dut.sv, line:1:1, endln:33:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamLine/dut.sv, line:1:1, endln:33:10 |vpiRhs: \_constant: , line:2:19, endln:2:23 |vpiDecompile:-12 @@ -594,7 +594,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.genblk5), line:15:4, endln:17:7 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamLine/dut.sv, line:1:1, endln:33:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamLine/dut.sv, line:1:1, endln:33:10 |vpiName:genblk5 |vpiFullName:work@top.genblk5 |vpiGenScope: @@ -602,8 +602,8 @@ design: (work@top) |vpiParent: \_gen_scope_array: (work@top.genblk5), line:15:4, endln:17:7 |vpiFullName:work@top.genblk5 - |vpiModule: - \_module: work@top.genblk5::GOOD_MINUS12 (work@top.genblk5.good), file:${SURELOG_DIR}/tests/ParamLine/dut.sv, line:16:7, endln:16:27 + |vpiModuleInst: + \_module_inst: work@top.genblk5::GOOD_MINUS12 (work@top.genblk5.good), file:${SURELOG_DIR}/tests/ParamLine/dut.sv, line:16:7, endln:16:27 |vpiParent: \_gen_scope: (work@top.genblk5) |vpiName:good @@ -661,21 +661,21 @@ design: (work@top) |vpiElaborated:1 |vpiName:work@top |uhdmallModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamLine/dut.sv, line:1:1, endln:33:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamLine/dut.sv, line:1:1, endln:33:10 |vpiParent: \_design: (work@top) |vpiFullName:work@top |vpiParameter: \_parameter: (work@top.p), line:2:15, endln:2:16 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamLine/dut.sv, line:1:1, endln:33:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamLine/dut.sv, line:1:1, endln:33:10 |BIN:0 |vpiName:p |vpiFullName:work@top.p |vpiParamAssign: \_param_assign: , line:2:15, endln:2:23 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamLine/dut.sv, line:1:1, endln:33:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamLine/dut.sv, line:1:1, endln:33:10 |vpiRhs: \_constant: , line:2:19, endln:2:23 |vpiDecompile:1'b0 @@ -696,19 +696,19 @@ design: (work@top) \_parameter: (work@top.p), line:2:15, endln:2:16 |vpiDefName:work@top |uhdmtopModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamLine/dut.sv, line:1:1, endln:33:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamLine/dut.sv, line:1:1, endln:33:10 |vpiName:work@top |vpiParameter: \_parameter: (work@top.p), line:2:15, endln:2:16 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamLine/dut.sv, line:1:1, endln:33:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamLine/dut.sv, line:1:1, endln:33:10 |BIN:0 |vpiName:p |vpiFullName:work@top.p |vpiParamAssign: \_param_assign: , line:2:15, endln:2:23 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamLine/dut.sv, line:1:1, endln:33:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamLine/dut.sv, line:1:1, endln:33:10 |vpiRhs: \_constant: , line:2:19, endln:2:23 |vpiDecompile:12 @@ -723,7 +723,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.genblk6), line:18:4, endln:20:7 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamLine/dut.sv, line:1:1, endln:33:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamLine/dut.sv, line:1:1, endln:33:10 |vpiName:genblk6 |vpiFullName:work@top.genblk6 |vpiGenScope: @@ -731,8 +731,8 @@ design: (work@top) |vpiParent: \_gen_scope_array: (work@top.genblk6), line:18:4, endln:20:7 |vpiFullName:work@top.genblk6 - |vpiModule: - \_module: work@top.genblk6::GOOD_12 (work@top.genblk6.good), file:${SURELOG_DIR}/tests/ParamLine/dut.sv, line:19:7, endln:19:22 + |vpiModuleInst: + \_module_inst: work@top.genblk6::GOOD_12 (work@top.genblk6.good), file:${SURELOG_DIR}/tests/ParamLine/dut.sv, line:19:7, endln:19:22 |vpiParent: \_gen_scope: (work@top.genblk6) |vpiName:good @@ -790,21 +790,21 @@ design: (work@top) |vpiElaborated:1 |vpiName:work@top |uhdmallModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamLine/dut.sv, line:1:1, endln:33:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamLine/dut.sv, line:1:1, endln:33:10 |vpiParent: \_design: (work@top) |vpiFullName:work@top |vpiParameter: \_parameter: (work@top.p), line:2:15, endln:2:16 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamLine/dut.sv, line:1:1, endln:33:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamLine/dut.sv, line:1:1, endln:33:10 |BIN:0 |vpiName:p |vpiFullName:work@top.p |vpiParamAssign: \_param_assign: , line:2:15, endln:2:23 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamLine/dut.sv, line:1:1, endln:33:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamLine/dut.sv, line:1:1, endln:33:10 |vpiRhs: \_constant: , line:2:19, endln:2:23 |vpiDecompile:1'b0 @@ -825,19 +825,19 @@ design: (work@top) \_parameter: (work@top.p), line:2:15, endln:2:16 |vpiDefName:work@top |uhdmtopModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamLine/dut.sv, line:1:1, endln:33:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamLine/dut.sv, line:1:1, endln:33:10 |vpiName:work@top |vpiParameter: \_parameter: (work@top.p), line:2:15, endln:2:16 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamLine/dut.sv, line:1:1, endln:33:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamLine/dut.sv, line:1:1, endln:33:10 |BIN:0 |vpiName:p |vpiFullName:work@top.p |vpiParamAssign: \_param_assign: , line:2:15, endln:2:23 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamLine/dut.sv, line:1:1, endln:33:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamLine/dut.sv, line:1:1, endln:33:10 |vpiRhs: \_constant: , line:2:19, endln:2:23 |vpiDecompile:12.120000 @@ -852,7 +852,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.genblk7), line:21:4, endln:23:7 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamLine/dut.sv, line:1:1, endln:33:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamLine/dut.sv, line:1:1, endln:33:10 |vpiName:genblk7 |vpiFullName:work@top.genblk7 |vpiGenScope: @@ -860,8 +860,8 @@ design: (work@top) |vpiParent: \_gen_scope_array: (work@top.genblk7), line:21:4, endln:23:7 |vpiFullName:work@top.genblk7 - |vpiModule: - \_module: work@top.genblk7::GOOD_REAL12 (work@top.genblk7.good), file:${SURELOG_DIR}/tests/ParamLine/dut.sv, line:22:7, endln:22:26 + |vpiModuleInst: + \_module_inst: work@top.genblk7::GOOD_REAL12 (work@top.genblk7.good), file:${SURELOG_DIR}/tests/ParamLine/dut.sv, line:22:7, endln:22:26 |vpiParent: \_gen_scope: (work@top.genblk7) |vpiName:good @@ -919,21 +919,21 @@ design: (work@top) |vpiElaborated:1 |vpiName:work@top |uhdmallModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamLine/dut.sv, line:1:1, endln:33:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamLine/dut.sv, line:1:1, endln:33:10 |vpiParent: \_design: (work@top) |vpiFullName:work@top |vpiParameter: \_parameter: (work@top.p), line:2:15, endln:2:16 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamLine/dut.sv, line:1:1, endln:33:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamLine/dut.sv, line:1:1, endln:33:10 |BIN:0 |vpiName:p |vpiFullName:work@top.p |vpiParamAssign: \_param_assign: , line:2:15, endln:2:23 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamLine/dut.sv, line:1:1, endln:33:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamLine/dut.sv, line:1:1, endln:33:10 |vpiRhs: \_constant: , line:2:19, endln:2:23 |vpiDecompile:1'b0 @@ -954,19 +954,19 @@ design: (work@top) \_parameter: (work@top.p), line:2:15, endln:2:16 |vpiDefName:work@top |uhdmtopModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamLine/dut.sv, line:1:1, endln:33:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamLine/dut.sv, line:1:1, endln:33:10 |vpiName:work@top |vpiParameter: \_parameter: (work@top.p), line:2:15, endln:2:16 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamLine/dut.sv, line:1:1, endln:33:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamLine/dut.sv, line:1:1, endln:33:10 |BIN:0 |vpiName:p |vpiFullName:work@top.p |vpiParamAssign: \_param_assign: , line:2:15, endln:2:23 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamLine/dut.sv, line:1:1, endln:33:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamLine/dut.sv, line:1:1, endln:33:10 |vpiRhs: \_constant: , line:2:19, endln:2:23 |vpiDecompile:0 @@ -981,7 +981,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.genblk8), line:24:4, endln:26:7 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamLine/dut.sv, line:1:1, endln:33:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamLine/dut.sv, line:1:1, endln:33:10 |vpiName:genblk8 |vpiFullName:work@top.genblk8 |vpiGenScope: @@ -989,8 +989,8 @@ design: (work@top) |vpiParent: \_gen_scope_array: (work@top.genblk8), line:24:4, endln:26:7 |vpiFullName:work@top.genblk8 - |vpiModule: - \_module: work@top.genblk8::GOOD_0 (work@top.genblk8.good), file:${SURELOG_DIR}/tests/ParamLine/dut.sv, line:25:7, endln:25:21 + |vpiModuleInst: + \_module_inst: work@top.genblk8::GOOD_0 (work@top.genblk8.good), file:${SURELOG_DIR}/tests/ParamLine/dut.sv, line:25:7, endln:25:21 |vpiParent: \_gen_scope: (work@top.genblk8) |vpiName:good @@ -1048,21 +1048,21 @@ design: (work@top) |vpiElaborated:1 |vpiName:work@top |uhdmallModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamLine/dut.sv, line:1:1, endln:33:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamLine/dut.sv, line:1:1, endln:33:10 |vpiParent: \_design: (work@top) |vpiFullName:work@top |vpiParameter: \_parameter: (work@top.p), line:2:15, endln:2:16 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamLine/dut.sv, line:1:1, endln:33:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamLine/dut.sv, line:1:1, endln:33:10 |BIN:0 |vpiName:p |vpiFullName:work@top.p |vpiParamAssign: \_param_assign: , line:2:15, endln:2:23 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamLine/dut.sv, line:1:1, endln:33:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamLine/dut.sv, line:1:1, endln:33:10 |vpiRhs: \_constant: , line:2:19, endln:2:23 |vpiDecompile:1'b0 @@ -1083,19 +1083,19 @@ design: (work@top) \_parameter: (work@top.p), line:2:15, endln:2:16 |vpiDefName:work@top |uhdmtopModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamLine/dut.sv, line:1:1, endln:33:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamLine/dut.sv, line:1:1, endln:33:10 |vpiName:work@top |vpiParameter: \_parameter: (work@top.p), line:2:15, endln:2:16 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamLine/dut.sv, line:1:1, endln:33:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamLine/dut.sv, line:1:1, endln:33:10 |BIN:0 |vpiName:p |vpiFullName:work@top.p |vpiParamAssign: \_param_assign: , line:2:15, endln:2:23 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamLine/dut.sv, line:1:1, endln:33:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamLine/dut.sv, line:1:1, endln:33:10 |vpiRhs: \_constant: , line:2:19, endln:2:23 |vpiDecompile:STR.WITH.DOT @@ -1110,7 +1110,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.genblk9), line:27:4, endln:29:7 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamLine/dut.sv, line:1:1, endln:33:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamLine/dut.sv, line:1:1, endln:33:10 |vpiName:genblk9 |vpiFullName:work@top.genblk9 |vpiGenScope: @@ -1118,8 +1118,8 @@ design: (work@top) |vpiParent: \_gen_scope_array: (work@top.genblk9), line:27:4, endln:29:7 |vpiFullName:work@top.genblk9 - |vpiModule: - \_module: work@top.genblk9::GOOD_STR_WITH_DOT (work@top.genblk9.good), file:${SURELOG_DIR}/tests/ParamLine/dut.sv, line:28:7, endln:28:32 + |vpiModuleInst: + \_module_inst: work@top.genblk9::GOOD_STR_WITH_DOT (work@top.genblk9.good), file:${SURELOG_DIR}/tests/ParamLine/dut.sv, line:28:7, endln:28:32 |vpiParent: \_gen_scope: (work@top.genblk9) |vpiName:good @@ -1177,21 +1177,21 @@ design: (work@top) |vpiElaborated:1 |vpiName:work@top |uhdmallModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamLine/dut.sv, line:1:1, endln:33:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamLine/dut.sv, line:1:1, endln:33:10 |vpiParent: \_design: (work@top) |vpiFullName:work@top |vpiParameter: \_parameter: (work@top.p), line:2:15, endln:2:16 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamLine/dut.sv, line:1:1, endln:33:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamLine/dut.sv, line:1:1, endln:33:10 |BIN:0 |vpiName:p |vpiFullName:work@top.p |vpiParamAssign: \_param_assign: , line:2:15, endln:2:23 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamLine/dut.sv, line:1:1, endln:33:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamLine/dut.sv, line:1:1, endln:33:10 |vpiRhs: \_constant: , line:2:19, endln:2:23 |vpiDecompile:1'b0 @@ -1212,19 +1212,19 @@ design: (work@top) \_parameter: (work@top.p), line:2:15, endln:2:16 |vpiDefName:work@top |uhdmtopModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamLine/dut.sv, line:1:1, endln:33:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamLine/dut.sv, line:1:1, endln:33:10 |vpiName:work@top |vpiParameter: \_parameter: (work@top.p), line:2:15, endln:2:16 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamLine/dut.sv, line:1:1, endln:33:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamLine/dut.sv, line:1:1, endln:33:10 |BIN:0 |vpiName:p |vpiFullName:work@top.p |vpiParamAssign: \_param_assign: , line:2:15, endln:2:23 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamLine/dut.sv, line:1:1, endln:33:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamLine/dut.sv, line:1:1, endln:33:10 |vpiRhs: \_constant: , line:2:19, endln:2:23 |vpiDecompile:-STR @@ -1239,7 +1239,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.genblk10), line:30:4, endln:32:7 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamLine/dut.sv, line:1:1, endln:33:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamLine/dut.sv, line:1:1, endln:33:10 |vpiName:genblk10 |vpiFullName:work@top.genblk10 |vpiGenScope: @@ -1247,8 +1247,8 @@ design: (work@top) |vpiParent: \_gen_scope_array: (work@top.genblk10), line:30:4, endln:32:7 |vpiFullName:work@top.genblk10 - |vpiModule: - \_module: work@top.genblk10::GOOD_MINUS_STR (work@top.genblk10.good), file:${SURELOG_DIR}/tests/ParamLine/dut.sv, line:31:7, endln:31:29 + |vpiModuleInst: + \_module_inst: work@top.genblk10::GOOD_MINUS_STR (work@top.genblk10.good), file:${SURELOG_DIR}/tests/ParamLine/dut.sv, line:31:7, endln:31:29 |vpiParent: \_gen_scope: (work@top.genblk10) |vpiName:good diff --git a/tests/ParamList/ParamList.log b/tests/ParamList/ParamList.log index 7b46181488..b08ca6e558 100644 --- a/tests/ParamList/ParamList.log +++ b/tests/ParamList/ParamList.log @@ -64,7 +64,7 @@ n<> u<37> t c<1> l<2:1> el<11:1> constant 6 design 1 int_typespec 4 -module 5 +module_inst 5 param_assign 4 parameter 4 === UHDM Object Stats End === @@ -74,7 +74,7 @@ parameter 4 constant 6 design 1 int_typespec 4 -module 5 +module_inst 5 param_assign 4 parameter 4 === UHDM Object Stats End === @@ -91,14 +91,14 @@ design: (work@r5p_soc_top) |vpiElaborated:1 |vpiName:work@r5p_soc_top |uhdmallModules: -\_module: work@r5p_soc_top (work@r5p_soc_top), file:${SURELOG_DIR}/tests/ParamList/dut.sv, line:2:1, endln:10:10 +\_module_inst: work@r5p_soc_top (work@r5p_soc_top), file:${SURELOG_DIR}/tests/ParamList/dut.sv, line:2:1, endln:10:10 |vpiParent: \_design: (work@r5p_soc_top) |vpiFullName:work@r5p_soc_top |vpiParameter: \_parameter: (work@r5p_soc_top.GW), line:4:16, endln:4:18 |vpiParent: - \_module: work@r5p_soc_top (work@r5p_soc_top), file:${SURELOG_DIR}/tests/ParamList/dut.sv, line:2:1, endln:10:10 + \_module_inst: work@r5p_soc_top (work@r5p_soc_top), file:${SURELOG_DIR}/tests/ParamList/dut.sv, line:2:1, endln:10:10 |UINT:32 |vpiTypespec: \_int_typespec: , line:4:3, endln:4:15 @@ -109,7 +109,7 @@ design: (work@r5p_soc_top) |vpiParameter: \_parameter: (work@r5p_soc_top.XLEN), line:6:16, endln:6:20 |vpiParent: - \_module: work@r5p_soc_top (work@r5p_soc_top), file:${SURELOG_DIR}/tests/ParamList/dut.sv, line:2:1, endln:10:10 + \_module_inst: work@r5p_soc_top (work@r5p_soc_top), file:${SURELOG_DIR}/tests/ParamList/dut.sv, line:2:1, endln:10:10 |UINT:32 |vpiTypespec: \_int_typespec: , line:6:3, endln:6:15 @@ -120,7 +120,7 @@ design: (work@r5p_soc_top) |vpiParamAssign: \_param_assign: , line:4:16, endln:4:23 |vpiParent: - \_module: work@r5p_soc_top (work@r5p_soc_top), file:${SURELOG_DIR}/tests/ParamList/dut.sv, line:2:1, endln:10:10 + \_module_inst: work@r5p_soc_top (work@r5p_soc_top), file:${SURELOG_DIR}/tests/ParamList/dut.sv, line:2:1, endln:10:10 |vpiRhs: \_constant: , line:4:21, endln:4:23 |vpiDecompile:32 @@ -134,7 +134,7 @@ design: (work@r5p_soc_top) |vpiParamAssign: \_param_assign: , line:6:16, endln:6:25 |vpiParent: - \_module: work@r5p_soc_top (work@r5p_soc_top), file:${SURELOG_DIR}/tests/ParamList/dut.sv, line:2:1, endln:10:10 + \_module_inst: work@r5p_soc_top (work@r5p_soc_top), file:${SURELOG_DIR}/tests/ParamList/dut.sv, line:2:1, endln:10:10 |vpiRhs: \_constant: , line:6:23, endln:6:25 |vpiDecompile:32 @@ -147,12 +147,12 @@ design: (work@r5p_soc_top) \_parameter: (work@r5p_soc_top.XLEN), line:6:16, endln:6:20 |vpiDefName:work@r5p_soc_top |uhdmtopModules: -\_module: work@r5p_soc_top (work@r5p_soc_top), file:${SURELOG_DIR}/tests/ParamList/dut.sv, line:2:1, endln:10:10 +\_module_inst: work@r5p_soc_top (work@r5p_soc_top), file:${SURELOG_DIR}/tests/ParamList/dut.sv, line:2:1, endln:10:10 |vpiName:work@r5p_soc_top |vpiParameter: \_parameter: (work@r5p_soc_top.GW), line:4:16, endln:4:18 |vpiParent: - \_module: work@r5p_soc_top (work@r5p_soc_top), file:${SURELOG_DIR}/tests/ParamList/dut.sv, line:2:1, endln:10:10 + \_module_inst: work@r5p_soc_top (work@r5p_soc_top), file:${SURELOG_DIR}/tests/ParamList/dut.sv, line:2:1, endln:10:10 |UINT:32 |vpiTypespec: \_int_typespec: , line:4:3, endln:4:15 @@ -163,7 +163,7 @@ design: (work@r5p_soc_top) |vpiParameter: \_parameter: (work@r5p_soc_top.XLEN), line:6:16, endln:6:20 |vpiParent: - \_module: work@r5p_soc_top (work@r5p_soc_top), file:${SURELOG_DIR}/tests/ParamList/dut.sv, line:2:1, endln:10:10 + \_module_inst: work@r5p_soc_top (work@r5p_soc_top), file:${SURELOG_DIR}/tests/ParamList/dut.sv, line:2:1, endln:10:10 |UINT:32 |vpiTypespec: \_int_typespec: , line:6:3, endln:6:15 @@ -174,7 +174,7 @@ design: (work@r5p_soc_top) |vpiParamAssign: \_param_assign: , line:4:16, endln:4:23 |vpiParent: - \_module: work@r5p_soc_top (work@r5p_soc_top), file:${SURELOG_DIR}/tests/ParamList/dut.sv, line:2:1, endln:10:10 + \_module_inst: work@r5p_soc_top (work@r5p_soc_top), file:${SURELOG_DIR}/tests/ParamList/dut.sv, line:2:1, endln:10:10 |vpiRhs: \_constant: , line:4:21, endln:4:23 |vpiDecompile:32 @@ -188,7 +188,7 @@ design: (work@r5p_soc_top) |vpiParamAssign: \_param_assign: , line:6:16, endln:6:25 |vpiParent: - \_module: work@r5p_soc_top (work@r5p_soc_top), file:${SURELOG_DIR}/tests/ParamList/dut.sv, line:2:1, endln:10:10 + \_module_inst: work@r5p_soc_top (work@r5p_soc_top), file:${SURELOG_DIR}/tests/ParamList/dut.sv, line:2:1, endln:10:10 |vpiRhs: \_constant: , line:6:23, endln:6:25 |vpiDecompile:32 diff --git a/tests/ParamMultiConcat/ParamMultiConcat.log b/tests/ParamMultiConcat/ParamMultiConcat.log index 600012de1e..c925fd2e9b 100644 --- a/tests/ParamMultiConcat/ParamMultiConcat.log +++ b/tests/ParamMultiConcat/ParamMultiConcat.log @@ -192,7 +192,7 @@ design 1 int_typespec 16 logic_net 2 logic_typespec 3 -module 8 +module_inst 8 operation 14 param_assign 8 parameter 8 @@ -208,7 +208,7 @@ design 1 int_typespec 16 logic_net 2 logic_typespec 3 -module 8 +module_inst 8 operation 14 param_assign 8 parameter 8 @@ -229,14 +229,14 @@ design: (work@top) |vpiElaborated:1 |vpiName:work@top |uhdmallModules: -\_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/ParamMultiConcat/dut.sv, line:1:1, endln:7:10 +\_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/ParamMultiConcat/dut.sv, line:1:1, endln:7:10 |vpiParent: \_design: (work@top) |vpiFullName:work@dut |vpiParameter: \_parameter: (work@dut.Width), line:3:18, endln:3:23 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/ParamMultiConcat/dut.sv, line:1:1, endln:7:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/ParamMultiConcat/dut.sv, line:1:1, endln:7:10 |vpiTypespec: \_int_typespec: , line:3:14, endln:3:17 |vpiParent: @@ -248,20 +248,20 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:3:18, endln:3:23 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/ParamMultiConcat/dut.sv, line:1:1, endln:7:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/ParamMultiConcat/dut.sv, line:1:1, endln:7:10 |vpiLhs: \_parameter: (work@dut.Width), line:3:18, endln:3:23 |vpiDefName:work@dut |vpiNet: \_logic_net: (work@dut.wmask_i), line:5:22, endln:5:29 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/ParamMultiConcat/dut.sv, line:1:1, endln:7:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/ParamMultiConcat/dut.sv, line:1:1, endln:7:10 |vpiName:wmask_i |vpiFullName:work@dut.wmask_i |vpiPort: \_port: (wmask_i), line:5:22, endln:5:29 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/ParamMultiConcat/dut.sv, line:1:1, endln:7:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/ParamMultiConcat/dut.sv, line:1:1, endln:7:10 |vpiName:wmask_i |vpiDirection:1 |vpiLowConn: @@ -299,14 +299,14 @@ design: (work@top) |UINT:0 |vpiConstType:9 |uhdmallModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamMultiConcat/dut.sv, line:9:1, endln:18:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamMultiConcat/dut.sv, line:9:1, endln:18:10 |vpiParent: \_design: (work@top) |vpiFullName:work@top |vpiParameter: \_parameter: (work@top.Width), line:10:18, endln:10:23 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamMultiConcat/dut.sv, line:9:1, endln:18:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamMultiConcat/dut.sv, line:9:1, endln:18:10 |UINT:16 |vpiTypespec: \_int_typespec: , line:10:14, endln:10:17 @@ -319,7 +319,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.EccWidth), line:11:18, endln:11:26 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamMultiConcat/dut.sv, line:9:1, endln:18:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamMultiConcat/dut.sv, line:9:1, endln:18:10 |UINT:3 |vpiTypespec: \_int_typespec: , line:11:14, endln:11:17 @@ -332,7 +332,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.BBB), line:12:15, endln:12:18 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamMultiConcat/dut.sv, line:9:1, endln:18:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamMultiConcat/dut.sv, line:9:1, endln:18:10 |vpiTypespec: \_int_typespec: , line:12:11, endln:12:14 |vpiParent: @@ -344,7 +344,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:10:18, endln:10:28 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamMultiConcat/dut.sv, line:9:1, endln:18:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamMultiConcat/dut.sv, line:9:1, endln:18:10 |vpiRhs: \_constant: , line:10:26, endln:10:28 |vpiDecompile:16 @@ -358,7 +358,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:11:18, endln:11:30 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamMultiConcat/dut.sv, line:9:1, endln:18:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamMultiConcat/dut.sv, line:9:1, endln:18:10 |vpiRhs: \_constant: , line:11:29, endln:11:30 |vpiDecompile:3 @@ -372,7 +372,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:12:15, endln:12:43 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamMultiConcat/dut.sv, line:9:1, endln:18:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamMultiConcat/dut.sv, line:9:1, endln:18:10 |vpiRhs: \_operation: , line:12:21, endln:12:43 |vpiOpType:34 @@ -406,12 +406,12 @@ design: (work@top) \_parameter: (work@top.BBB), line:12:15, endln:12:18 |vpiDefName:work@top |uhdmtopModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamMultiConcat/dut.sv, line:9:1, endln:18:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamMultiConcat/dut.sv, line:9:1, endln:18:10 |vpiName:work@top |vpiParameter: \_parameter: (work@top.Width), line:10:18, endln:10:23 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamMultiConcat/dut.sv, line:9:1, endln:18:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamMultiConcat/dut.sv, line:9:1, endln:18:10 |UINT:16 |vpiTypespec: \_int_typespec: , line:10:14, endln:10:17 @@ -424,7 +424,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.EccWidth), line:11:18, endln:11:26 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamMultiConcat/dut.sv, line:9:1, endln:18:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamMultiConcat/dut.sv, line:9:1, endln:18:10 |UINT:3 |vpiTypespec: \_int_typespec: , line:11:14, endln:11:17 @@ -437,7 +437,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.BBB), line:12:15, endln:12:18 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamMultiConcat/dut.sv, line:9:1, endln:18:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamMultiConcat/dut.sv, line:9:1, endln:18:10 |vpiTypespec: \_int_typespec: , line:12:11, endln:12:14 |vpiParent: @@ -449,7 +449,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:10:18, endln:10:28 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamMultiConcat/dut.sv, line:9:1, endln:18:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamMultiConcat/dut.sv, line:9:1, endln:18:10 |vpiRhs: \_constant: , line:10:26, endln:10:28 |vpiDecompile:16 @@ -463,7 +463,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:11:18, endln:11:30 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamMultiConcat/dut.sv, line:9:1, endln:18:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamMultiConcat/dut.sv, line:9:1, endln:18:10 |vpiRhs: \_constant: , line:11:29, endln:11:30 |vpiDecompile:3 @@ -477,7 +477,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:12:15, endln:12:43 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamMultiConcat/dut.sv, line:9:1, endln:18:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamMultiConcat/dut.sv, line:9:1, endln:18:10 |vpiRhs: \_constant: , line:12:21, endln:12:43 |vpiDecompile:32'b1111111111111111111 @@ -491,16 +491,16 @@ design: (work@top) |vpiDefName:work@top |vpiTop:1 |vpiTopModule:1 - |vpiModule: - \_module: work@dut (work@top.u_dut), file:${SURELOG_DIR}/tests/ParamMultiConcat/dut.sv, line:13:4, endln:17:6 + |vpiModuleInst: + \_module_inst: work@dut (work@top.u_dut), file:${SURELOG_DIR}/tests/ParamMultiConcat/dut.sv, line:13:4, endln:17:6 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamMultiConcat/dut.sv, line:9:1, endln:18:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamMultiConcat/dut.sv, line:9:1, endln:18:10 |vpiName:u_dut |vpiFullName:work@top.u_dut |vpiParameter: \_parameter: (work@top.u_dut.Width), line:3:18, endln:3:23 |vpiParent: - \_module: work@dut (work@top.u_dut), file:${SURELOG_DIR}/tests/ParamMultiConcat/dut.sv, line:13:4, endln:17:6 + \_module_inst: work@dut (work@top.u_dut), file:${SURELOG_DIR}/tests/ParamMultiConcat/dut.sv, line:13:4, endln:17:6 |vpiTypespec: \_int_typespec: , line:3:14, endln:3:17 |vpiParent: @@ -512,7 +512,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:3:18, endln:3:23 |vpiParent: - \_module: work@dut (work@top.u_dut), file:${SURELOG_DIR}/tests/ParamMultiConcat/dut.sv, line:13:4, endln:17:6 + \_module_inst: work@dut (work@top.u_dut), file:${SURELOG_DIR}/tests/ParamMultiConcat/dut.sv, line:13:4, endln:17:6 |vpiOverriden:1 |vpiRhs: \_constant: @@ -530,7 +530,7 @@ design: (work@top) |vpiNet: \_logic_net: (work@top.u_dut.wmask_i), line:5:22, endln:5:29 |vpiParent: - \_module: work@dut (work@top.u_dut), file:${SURELOG_DIR}/tests/ParamMultiConcat/dut.sv, line:13:4, endln:17:6 + \_module_inst: work@dut (work@top.u_dut), file:${SURELOG_DIR}/tests/ParamMultiConcat/dut.sv, line:13:4, endln:17:6 |vpiTypespec: \_logic_typespec: , line:5:10, endln:5:21 |vpiRange: @@ -554,11 +554,11 @@ design: (work@top) |vpiName:wmask_i |vpiFullName:work@top.u_dut.wmask_i |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamMultiConcat/dut.sv, line:9:1, endln:18:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamMultiConcat/dut.sv, line:9:1, endln:18:10 |vpiPort: \_port: (wmask_i), line:5:22, endln:5:29 |vpiParent: - \_module: work@dut (work@top.u_dut), file:${SURELOG_DIR}/tests/ParamMultiConcat/dut.sv, line:13:4, endln:17:6 + \_module_inst: work@dut (work@top.u_dut), file:${SURELOG_DIR}/tests/ParamMultiConcat/dut.sv, line:13:4, endln:17:6 |vpiName:wmask_i |vpiDirection:1 |vpiHighConn: @@ -601,7 +601,7 @@ design: (work@top) |UINT:0 |vpiConstType:9 |vpiInstance: - \_module: work@dut (work@top.u_dut), file:${SURELOG_DIR}/tests/ParamMultiConcat/dut.sv, line:13:4, endln:17:6 + \_module_inst: work@dut (work@top.u_dut), file:${SURELOG_DIR}/tests/ParamMultiConcat/dut.sv, line:13:4, endln:17:6 =================== [ FATAL] : 0 [ SYNTAX] : 0 diff --git a/tests/ParamNoDefault/ParamNoDefault.log b/tests/ParamNoDefault/ParamNoDefault.log index edb67ff784..e3b9331c51 100644 --- a/tests/ParamNoDefault/ParamNoDefault.log +++ b/tests/ParamNoDefault/ParamNoDefault.log @@ -157,7 +157,7 @@ n<> u<122> t c<1> l<1:1> el<19:1> constant 31 design 1 logic_typespec 9 -module 7 +module_inst 7 operation 6 param_assign 4 parameter 6 @@ -173,7 +173,7 @@ typespec_member 6 constant 31 design 1 logic_typespec 9 -module 7 +module_inst 7 operation 6 param_assign 4 parameter 6 @@ -196,14 +196,14 @@ design: (work@top) |vpiElaborated:1 |vpiName:work@top |uhdmallModules: -\_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/ParamNoDefault/dut.sv, line:1:1, endln:4:10 +\_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/ParamNoDefault/dut.sv, line:1:1, endln:4:10 |vpiParent: \_design: (work@top) |vpiFullName:work@dut |vpiParameter: \_parameter: (work@dut.A), line:2:26, endln:2:27 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/ParamNoDefault/dut.sv, line:1:1, endln:4:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/ParamNoDefault/dut.sv, line:1:1, endln:4:10 |vpiTypespec: \_logic_typespec: , line:2:14, endln:2:25 |vpiParent: @@ -231,26 +231,26 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:2:26, endln:2:27 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/ParamNoDefault/dut.sv, line:1:1, endln:4:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/ParamNoDefault/dut.sv, line:1:1, endln:4:10 |vpiLhs: \_parameter: (work@dut.A), line:2:26, endln:2:27 |vpiDefName:work@dut |uhdmallModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamNoDefault/dut.sv, line:6:1, endln:18:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamNoDefault/dut.sv, line:6:1, endln:18:10 |vpiParent: \_design: (work@top) |vpiFullName:work@top |vpiParameter: \_parameter: (work@top.X), line:14:23, endln:14:24 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamNoDefault/dut.sv, line:6:1, endln:18:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamNoDefault/dut.sv, line:6:1, endln:18:10 |vpiTypespec: \_struct_typespec: (struct_1), line:7:12, endln:7:18 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamNoDefault/dut.sv, line:6:1, endln:18:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamNoDefault/dut.sv, line:6:1, endln:18:10 |vpiName:struct_1 |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamNoDefault/dut.sv, line:6:1, endln:18:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamNoDefault/dut.sv, line:6:1, endln:18:10 |vpiPacked:1 |vpiTypespecMember: \_typespec_member: (a), line:8:19, endln:8:20 @@ -291,7 +291,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:14:23, endln:14:42 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamNoDefault/dut.sv, line:6:1, endln:18:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamNoDefault/dut.sv, line:6:1, endln:18:10 |vpiRhs: \_operation: , line:14:27, endln:14:42 |vpiOpType:75 @@ -323,19 +323,19 @@ design: (work@top) \_struct_typespec: (struct_1), line:7:12, endln:7:18 |vpiDefName:work@top |uhdmtopModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamNoDefault/dut.sv, line:6:1, endln:18:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamNoDefault/dut.sv, line:6:1, endln:18:10 |vpiName:work@top |vpiParameter: \_parameter: (work@top.X), line:14:23, endln:14:24 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamNoDefault/dut.sv, line:6:1, endln:18:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamNoDefault/dut.sv, line:6:1, endln:18:10 |vpiTypespec: \_struct_typespec: (struct_1), line:7:12, endln:7:18 |vpiParent: \_parameter: (work@top.X), line:14:23, endln:14:24 |vpiName:struct_1 |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamNoDefault/dut.sv, line:6:1, endln:18:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamNoDefault/dut.sv, line:6:1, endln:18:10 |vpiPacked:1 |vpiTypespecMember: \_typespec_member: (a), line:8:19, endln:8:20 @@ -376,7 +376,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:14:23, endln:14:42 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamNoDefault/dut.sv, line:6:1, endln:18:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamNoDefault/dut.sv, line:6:1, endln:18:10 |vpiRhs: \_operation: , line:14:27, endln:14:42 |vpiParent: @@ -463,16 +463,16 @@ design: (work@top) |vpiDefName:work@top |vpiTop:1 |vpiTopModule:1 - |vpiModule: - \_module: work@dut (work@top.u_dut), file:${SURELOG_DIR}/tests/ParamNoDefault/dut.sv, line:17:4, endln:17:25 + |vpiModuleInst: + \_module_inst: work@dut (work@top.u_dut), file:${SURELOG_DIR}/tests/ParamNoDefault/dut.sv, line:17:4, endln:17:25 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamNoDefault/dut.sv, line:6:1, endln:18:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamNoDefault/dut.sv, line:6:1, endln:18:10 |vpiName:u_dut |vpiFullName:work@top.u_dut |vpiParameter: \_parameter: (work@top.u_dut.A), line:2:26, endln:2:27 |vpiParent: - \_module: work@dut (work@top.u_dut), file:${SURELOG_DIR}/tests/ParamNoDefault/dut.sv, line:17:4, endln:17:25 + \_module_inst: work@dut (work@top.u_dut), file:${SURELOG_DIR}/tests/ParamNoDefault/dut.sv, line:17:4, endln:17:25 |vpiTypespec: \_logic_typespec: , line:2:14, endln:2:25 |vpiParent: @@ -502,7 +502,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:2:26, endln:2:27 |vpiParent: - \_module: work@dut (work@top.u_dut), file:${SURELOG_DIR}/tests/ParamNoDefault/dut.sv, line:17:4, endln:17:25 + \_module_inst: work@dut (work@top.u_dut), file:${SURELOG_DIR}/tests/ParamNoDefault/dut.sv, line:17:4, endln:17:25 |vpiOverriden:1 |vpiRhs: \_constant: , line:17:13, endln:17:14 @@ -515,7 +515,7 @@ design: (work@top) |vpiDefFile:${SURELOG_DIR}/tests/ParamNoDefault/dut.sv |vpiDefLineNo:1 |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamNoDefault/dut.sv, line:6:1, endln:18:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamNoDefault/dut.sv, line:6:1, endln:18:10 =================== [ FATAL] : 0 [ SYNTAX] : 0 diff --git a/tests/ParamNoImport/ParamNoImport.log b/tests/ParamNoImport/ParamNoImport.log index c9552a6394..0c83a8a322 100644 --- a/tests/ParamNoImport/ParamNoImport.log +++ b/tests/ParamNoImport/ParamNoImport.log @@ -144,7 +144,7 @@ constant 25 design 1 int_typespec 1 logic_typespec 7 -module 7 +module_inst 7 operation 9 package 3 param_assign 6 @@ -163,7 +163,7 @@ constant 25 design 1 int_typespec 1 logic_typespec 7 -module 7 +module_inst 7 operation 9 package 3 param_assign 6 @@ -347,27 +347,27 @@ design: (work@dut) |vpiDefName:pkg |vpiTop:1 |uhdmallModules: -\_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/ParamNoImport/dut.sv, line:14:1, endln:18:10 +\_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/ParamNoImport/dut.sv, line:14:1, endln:18:10 |vpiParent: \_design: (work@dut) |vpiFullName:work@dut |vpiDefName:work@dut |uhdmallModules: -\_module: work@test (work@test), file:${SURELOG_DIR}/tests/ParamNoImport/dut.sv, line:1:1, endln:3:10 +\_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/ParamNoImport/dut.sv, line:1:1, endln:3:10 |vpiParent: \_design: (work@dut) |vpiFullName:work@test |vpiParameter: \_parameter: (work@test.PWR_AST_RSP), line:1:26, endln:1:37 |vpiParent: - \_module: work@test (work@test), file:${SURELOG_DIR}/tests/ParamNoImport/dut.sv, line:1:1, endln:3:10 + \_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/ParamNoImport/dut.sv, line:1:1, endln:3:10 |BIN:0 |vpiName:PWR_AST_RSP |vpiFullName:work@test.PWR_AST_RSP |vpiParamAssign: \_param_assign: , line:1:26, endln:1:42 |vpiParent: - \_module: work@test (work@test), file:${SURELOG_DIR}/tests/ParamNoImport/dut.sv, line:1:1, endln:3:10 + \_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/ParamNoImport/dut.sv, line:1:1, endln:3:10 |vpiRhs: \_constant: , line:1:40, endln:1:42 |vpiDecompile:'0 @@ -378,28 +378,28 @@ design: (work@dut) \_parameter: (work@test.PWR_AST_RSP), line:1:26, endln:1:37 |vpiDefName:work@test |uhdmtopModules: -\_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/ParamNoImport/dut.sv, line:14:1, endln:18:10 +\_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/ParamNoImport/dut.sv, line:14:1, endln:18:10 |vpiName:work@dut |vpiDefName:work@dut |vpiTop:1 |vpiTopModule:1 - |vpiModule: - \_module: work@test (work@dut.t), file:${SURELOG_DIR}/tests/ParamNoImport/dut.sv, line:16:1, endln:16:52 + |vpiModuleInst: + \_module_inst: work@test (work@dut.t), file:${SURELOG_DIR}/tests/ParamNoImport/dut.sv, line:16:1, endln:16:52 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/ParamNoImport/dut.sv, line:14:1, endln:18:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/ParamNoImport/dut.sv, line:14:1, endln:18:10 |vpiName:t |vpiFullName:work@dut.t |vpiParameter: \_parameter: (work@dut.t.PWR_AST_RSP), line:1:26, endln:1:37 |vpiParent: - \_module: work@test (work@dut.t), file:${SURELOG_DIR}/tests/ParamNoImport/dut.sv, line:16:1, endln:16:52 + \_module_inst: work@test (work@dut.t), file:${SURELOG_DIR}/tests/ParamNoImport/dut.sv, line:16:1, endln:16:52 |BIN:0 |vpiName:PWR_AST_RSP |vpiFullName:work@dut.t.PWR_AST_RSP |vpiParamAssign: \_param_assign: , line:1:26, endln:1:42 |vpiParent: - \_module: work@test (work@dut.t), file:${SURELOG_DIR}/tests/ParamNoImport/dut.sv, line:16:1, endln:16:52 + \_module_inst: work@test (work@dut.t), file:${SURELOG_DIR}/tests/ParamNoImport/dut.sv, line:16:1, endln:16:52 |vpiOverriden:1 |vpiRhs: \_operation: , line:9:47, endln:11:2 @@ -464,7 +464,7 @@ design: (work@dut) |vpiDefFile:${SURELOG_DIR}/tests/ParamNoImport/dut.sv |vpiDefLineNo:1 |vpiInstance: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/ParamNoImport/dut.sv, line:14:1, endln:18:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/ParamNoImport/dut.sv, line:14:1, endln:18:10 =================== [ FATAL] : 0 [ SYNTAX] : 0 diff --git a/tests/ParamNoSubst/ParamNoSubst.log b/tests/ParamNoSubst/ParamNoSubst.log index 06e6fe1953..a5712c62a5 100644 --- a/tests/ParamNoSubst/ParamNoSubst.log +++ b/tests/ParamNoSubst/ParamNoSubst.log @@ -224,7 +224,7 @@ design 1 import_typespec 1 logic_net 1 logic_typespec 15 -module 13 +module_inst 13 operation 11 package 3 param_assign 10 @@ -245,7 +245,7 @@ design 1 import_typespec 1 logic_net 1 logic_typespec 15 -module 13 +module_inst 13 operation 11 package 3 param_assign 10 @@ -362,7 +362,7 @@ design: (work@aes_core), id:148 |vpiTypespec: \_struct_typespec: (aes_pkg::ctrl_reg_t), id:1, line:2:9, endln:2:15 |vpiParent: - \_module: work@aes_core (work@aes_core), id:150, file:${SURELOG_DIR}/tests/ParamNoSubst/dut.sv, line:22:1, endln:26:10 + \_module_inst: work@aes_core (work@aes_core), id:150, file:${SURELOG_DIR}/tests/ParamNoSubst/dut.sv, line:22:1, endln:26:10 |vpiName:aes_pkg::ctrl_reg_t |vpiInstance: \_package: aes_pkg (aes_pkg::), id:0, file:${SURELOG_DIR}/tests/ParamNoSubst/dut.sv, line:1:1, endln:9:11 @@ -430,14 +430,14 @@ design: (work@aes_core), id:148 |vpiDefName:aes_pkg |vpiTop:1 |uhdmallModules: -\_module: work@aes_core (work@aes_core), id:150, file:${SURELOG_DIR}/tests/ParamNoSubst/dut.sv, line:22:1, endln:26:10 +\_module_inst: work@aes_core (work@aes_core), id:150, file:${SURELOG_DIR}/tests/ParamNoSubst/dut.sv, line:22:1, endln:26:10 |vpiParent: \_design: (work@aes_core), id:148 |vpiFullName:work@aes_core |vpiParameter: \_parameter: (work@aes_core.CTRL_RESET), id:60, line:6:22, endln:6:32 |vpiParent: - \_module: work@aes_core (work@aes_core), id:150, file:${SURELOG_DIR}/tests/ParamNoSubst/dut.sv, line:22:1, endln:26:10 + \_module_inst: work@aes_core (work@aes_core), id:150, file:${SURELOG_DIR}/tests/ParamNoSubst/dut.sv, line:22:1, endln:26:10 |vpiTypespec: \_struct_typespec: (aes_pkg::ctrl_reg_t), id:61, line:2:9, endln:2:15 |vpiParent: @@ -488,7 +488,7 @@ design: (work@aes_core), id:148 |vpiParamAssign: \_param_assign: , id:67, line:6:22, endln:8:2 |vpiParent: - \_module: work@aes_core (work@aes_core), id:150, file:${SURELOG_DIR}/tests/ParamNoSubst/dut.sv, line:22:1, endln:26:10 + \_module_inst: work@aes_core (work@aes_core), id:150, file:${SURELOG_DIR}/tests/ParamNoSubst/dut.sv, line:22:1, endln:26:10 |vpiRhs: \_operation: , id:68, line:6:35, endln:8:2 |vpiParent: @@ -570,18 +570,18 @@ design: (work@aes_core), id:148 |vpiNet: \_logic_net: (work@aes_core.ctrl_q), id:151, line:24:14, endln:24:20 |vpiParent: - \_module: work@aes_core (work@aes_core), id:150, file:${SURELOG_DIR}/tests/ParamNoSubst/dut.sv, line:22:1, endln:26:10 + \_module_inst: work@aes_core (work@aes_core), id:150, file:${SURELOG_DIR}/tests/ParamNoSubst/dut.sv, line:22:1, endln:26:10 |vpiName:ctrl_q |vpiFullName:work@aes_core.ctrl_q |uhdmallModules: -\_module: work@prim_subreg (work@prim_subreg), id:152, file:${SURELOG_DIR}/tests/ParamNoSubst/dut.sv, line:11:1, endln:14:10 +\_module_inst: work@prim_subreg (work@prim_subreg), id:152, file:${SURELOG_DIR}/tests/ParamNoSubst/dut.sv, line:11:1, endln:14:10 |vpiParent: \_design: (work@aes_core), id:148 |vpiFullName:work@prim_subreg |vpiParameter: \_parameter: (work@prim_subreg.RESVAL), id:85, line:12:26, endln:12:32 |vpiParent: - \_module: work@prim_subreg (work@prim_subreg), id:152, file:${SURELOG_DIR}/tests/ParamNoSubst/dut.sv, line:11:1, endln:14:10 + \_module_inst: work@prim_subreg (work@prim_subreg), id:152, file:${SURELOG_DIR}/tests/ParamNoSubst/dut.sv, line:11:1, endln:14:10 |BIN:0 |vpiTypespec: \_logic_typespec: , id:84, line:12:13, endln:12:25 @@ -610,7 +610,7 @@ design: (work@aes_core), id:148 |vpiParamAssign: \_param_assign: , id:86, line:12:26, endln:12:37 |vpiParent: - \_module: work@prim_subreg (work@prim_subreg), id:152, file:${SURELOG_DIR}/tests/ParamNoSubst/dut.sv, line:11:1, endln:14:10 + \_module_inst: work@prim_subreg (work@prim_subreg), id:152, file:${SURELOG_DIR}/tests/ParamNoSubst/dut.sv, line:11:1, endln:14:10 |vpiRhs: \_constant: , id:87, line:12:35, endln:12:37 |vpiDecompile:'0 @@ -623,14 +623,14 @@ design: (work@aes_core), id:148 \_parameter: (work@prim_subreg.RESVAL), id:85, line:12:26, endln:12:32 |vpiDefName:work@prim_subreg |uhdmallModules: -\_module: work@prim_subreg_shadow (work@prim_subreg_shadow), id:153, file:${SURELOG_DIR}/tests/ParamNoSubst/dut.sv, line:16:1, endln:20:10 +\_module_inst: work@prim_subreg_shadow (work@prim_subreg_shadow), id:153, file:${SURELOG_DIR}/tests/ParamNoSubst/dut.sv, line:16:1, endln:20:10 |vpiParent: \_design: (work@aes_core), id:148 |vpiFullName:work@prim_subreg_shadow |vpiParameter: \_parameter: (work@prim_subreg_shadow.RESVAL), id:93, line:17:26, endln:17:32 |vpiParent: - \_module: work@prim_subreg_shadow (work@prim_subreg_shadow), id:153, file:${SURELOG_DIR}/tests/ParamNoSubst/dut.sv, line:16:1, endln:20:10 + \_module_inst: work@prim_subreg_shadow (work@prim_subreg_shadow), id:153, file:${SURELOG_DIR}/tests/ParamNoSubst/dut.sv, line:16:1, endln:20:10 |BIN:0 |vpiTypespec: \_logic_typespec: , id:92, line:17:13, endln:17:25 @@ -659,7 +659,7 @@ design: (work@aes_core), id:148 |vpiParamAssign: \_param_assign: , id:94, line:17:26, endln:17:37 |vpiParent: - \_module: work@prim_subreg_shadow (work@prim_subreg_shadow), id:153, file:${SURELOG_DIR}/tests/ParamNoSubst/dut.sv, line:16:1, endln:20:10 + \_module_inst: work@prim_subreg_shadow (work@prim_subreg_shadow), id:153, file:${SURELOG_DIR}/tests/ParamNoSubst/dut.sv, line:16:1, endln:20:10 |vpiRhs: \_constant: , id:95, line:17:35, endln:17:37 |vpiDecompile:'0 @@ -672,12 +672,12 @@ design: (work@aes_core), id:148 \_parameter: (work@prim_subreg_shadow.RESVAL), id:93, line:17:26, endln:17:32 |vpiDefName:work@prim_subreg_shadow |uhdmtopModules: -\_module: work@aes_core (work@aes_core), id:154, file:${SURELOG_DIR}/tests/ParamNoSubst/dut.sv, line:22:1, endln:26:10 +\_module_inst: work@aes_core (work@aes_core), id:154, file:${SURELOG_DIR}/tests/ParamNoSubst/dut.sv, line:22:1, endln:26:10 |vpiName:work@aes_core |vpiParameter: \_parameter: (work@aes_core.CTRL_RESET), id:155, line:6:22, endln:6:32 |vpiParent: - \_module: work@aes_core (work@aes_core), id:154, file:${SURELOG_DIR}/tests/ParamNoSubst/dut.sv, line:22:1, endln:26:10 + \_module_inst: work@aes_core (work@aes_core), id:154, file:${SURELOG_DIR}/tests/ParamNoSubst/dut.sv, line:22:1, endln:26:10 |vpiTypespec: \_struct_typespec: (aes_pkg::ctrl_reg_t), id:156, line:2:9, endln:2:15 |vpiParent: @@ -728,7 +728,7 @@ design: (work@aes_core), id:148 |vpiParamAssign: \_param_assign: , id:107, line:6:22, endln:8:2 |vpiParent: - \_module: work@aes_core (work@aes_core), id:154, file:${SURELOG_DIR}/tests/ParamNoSubst/dut.sv, line:22:1, endln:26:10 + \_module_inst: work@aes_core (work@aes_core), id:154, file:${SURELOG_DIR}/tests/ParamNoSubst/dut.sv, line:22:1, endln:26:10 |vpiRhs: \_operation: , id:119, line:6:35, endln:8:2 |vpiParent: @@ -797,22 +797,22 @@ design: (work@aes_core), id:148 |vpiNet: \_struct_net: (work@aes_core.ctrl_q), id:139, line:24:14, endln:24:20 |vpiParent: - \_module: work@aes_core (work@aes_core), id:154, file:${SURELOG_DIR}/tests/ParamNoSubst/dut.sv, line:22:1, endln:26:10 + \_module_inst: work@aes_core (work@aes_core), id:154, file:${SURELOG_DIR}/tests/ParamNoSubst/dut.sv, line:22:1, endln:26:10 |vpiTypespec: \_struct_typespec: (aes_pkg::ctrl_reg_t), id:1, line:2:9, endln:2:15 |vpiName:ctrl_q |vpiFullName:work@aes_core.ctrl_q |vpiTopModule:1 - |vpiModule: - \_module: work@prim_subreg_shadow (work@aes_core.ctrl_shadowed_reg), id:162, file:${SURELOG_DIR}/tests/ParamNoSubst/dut.sv, line:25:3, endln:25:65 + |vpiModuleInst: + \_module_inst: work@prim_subreg_shadow (work@aes_core.ctrl_shadowed_reg), id:162, file:${SURELOG_DIR}/tests/ParamNoSubst/dut.sv, line:25:3, endln:25:65 |vpiParent: - \_module: work@aes_core (work@aes_core), id:154, file:${SURELOG_DIR}/tests/ParamNoSubst/dut.sv, line:22:1, endln:26:10 + \_module_inst: work@aes_core (work@aes_core), id:154, file:${SURELOG_DIR}/tests/ParamNoSubst/dut.sv, line:22:1, endln:26:10 |vpiName:ctrl_shadowed_reg |vpiFullName:work@aes_core.ctrl_shadowed_reg |vpiParameter: \_parameter: (work@aes_core.ctrl_shadowed_reg.RESVAL), id:163, line:17:26, endln:17:32 |vpiParent: - \_module: work@prim_subreg_shadow (work@aes_core.ctrl_shadowed_reg), id:162, file:${SURELOG_DIR}/tests/ParamNoSubst/dut.sv, line:25:3, endln:25:65 + \_module_inst: work@prim_subreg_shadow (work@aes_core.ctrl_shadowed_reg), id:162, file:${SURELOG_DIR}/tests/ParamNoSubst/dut.sv, line:25:3, endln:25:65 |BIN:0 |vpiTypespec: \_logic_typespec: , id:164, line:17:13, endln:17:25 @@ -843,7 +843,7 @@ design: (work@aes_core), id:148 |vpiParamAssign: \_param_assign: , id:143, line:17:26, endln:17:37 |vpiParent: - \_module: work@prim_subreg_shadow (work@aes_core.ctrl_shadowed_reg), id:162, file:${SURELOG_DIR}/tests/ParamNoSubst/dut.sv, line:25:3, endln:25:65 + \_module_inst: work@prim_subreg_shadow (work@aes_core.ctrl_shadowed_reg), id:162, file:${SURELOG_DIR}/tests/ParamNoSubst/dut.sv, line:25:3, endln:25:65 |vpiOverriden:1 |vpiRhs: \_ref_obj: (CTRL_RESET), id:142, line:25:32, endln:25:42 @@ -856,17 +856,17 @@ design: (work@aes_core), id:148 |vpiDefFile:${SURELOG_DIR}/tests/ParamNoSubst/dut.sv |vpiDefLineNo:16 |vpiInstance: - \_module: work@aes_core (work@aes_core), id:154, file:${SURELOG_DIR}/tests/ParamNoSubst/dut.sv, line:22:1, endln:26:10 - |vpiModule: - \_module: work@prim_subreg (work@aes_core.ctrl_shadowed_reg.committed_reg), id:168, file:${SURELOG_DIR}/tests/ParamNoSubst/dut.sv, line:19:3, endln:19:50 + \_module_inst: work@aes_core (work@aes_core), id:154, file:${SURELOG_DIR}/tests/ParamNoSubst/dut.sv, line:22:1, endln:26:10 + |vpiModuleInst: + \_module_inst: work@prim_subreg (work@aes_core.ctrl_shadowed_reg.committed_reg), id:168, file:${SURELOG_DIR}/tests/ParamNoSubst/dut.sv, line:19:3, endln:19:50 |vpiParent: - \_module: work@prim_subreg_shadow (work@aes_core.ctrl_shadowed_reg), id:162, file:${SURELOG_DIR}/tests/ParamNoSubst/dut.sv, line:25:3, endln:25:65 + \_module_inst: work@prim_subreg_shadow (work@aes_core.ctrl_shadowed_reg), id:162, file:${SURELOG_DIR}/tests/ParamNoSubst/dut.sv, line:25:3, endln:25:65 |vpiName:committed_reg |vpiFullName:work@aes_core.ctrl_shadowed_reg.committed_reg |vpiParameter: \_parameter: (work@aes_core.ctrl_shadowed_reg.committed_reg.RESVAL), id:169, line:12:26, endln:12:32 |vpiParent: - \_module: work@prim_subreg (work@aes_core.ctrl_shadowed_reg.committed_reg), id:168, file:${SURELOG_DIR}/tests/ParamNoSubst/dut.sv, line:19:3, endln:19:50 + \_module_inst: work@prim_subreg (work@aes_core.ctrl_shadowed_reg.committed_reg), id:168, file:${SURELOG_DIR}/tests/ParamNoSubst/dut.sv, line:19:3, endln:19:50 |BIN:0 |vpiTypespec: \_logic_typespec: , id:170, line:12:13, endln:12:25 @@ -897,7 +897,7 @@ design: (work@aes_core), id:148 |vpiParamAssign: \_param_assign: , id:146, line:12:26, endln:12:37 |vpiParent: - \_module: work@prim_subreg (work@aes_core.ctrl_shadowed_reg.committed_reg), id:168, file:${SURELOG_DIR}/tests/ParamNoSubst/dut.sv, line:19:3, endln:19:50 + \_module_inst: work@prim_subreg (work@aes_core.ctrl_shadowed_reg.committed_reg), id:168, file:${SURELOG_DIR}/tests/ParamNoSubst/dut.sv, line:19:3, endln:19:50 |vpiOverriden:1 |vpiRhs: \_ref_obj: (CTRL_RESET), id:145, line:19:25, endln:19:31 @@ -912,7 +912,7 @@ design: (work@aes_core), id:148 |vpiDefFile:${SURELOG_DIR}/tests/ParamNoSubst/dut.sv |vpiDefLineNo:11 |vpiInstance: - \_module: work@prim_subreg_shadow (work@aes_core.ctrl_shadowed_reg), id:162, file:${SURELOG_DIR}/tests/ParamNoSubst/dut.sv, line:25:3, endln:25:65 + \_module_inst: work@prim_subreg_shadow (work@aes_core.ctrl_shadowed_reg), id:162, file:${SURELOG_DIR}/tests/ParamNoSubst/dut.sv, line:25:3, endln:25:65 =================== [ FATAL] : 0 [ SYNTAX] : 0 diff --git a/tests/ParamOverload1/ParamOverload1.log b/tests/ParamOverload1/ParamOverload1.log index a01ca17a0b..c9ed407b95 100644 --- a/tests/ParamOverload1/ParamOverload1.log +++ b/tests/ParamOverload1/ParamOverload1.log @@ -208,7 +208,7 @@ design 1 int_typespec 17 int_var 4 logic_net 2 -module 11 +module_inst 11 operation 19 param_assign 4 parameter 6 @@ -227,7 +227,7 @@ design 1 int_typespec 17 int_var 4 logic_net 2 -module 11 +module_inst 11 operation 19 param_assign 4 parameter 6 @@ -248,14 +248,14 @@ design: (work@top) |vpiElaborated:1 |vpiName:work@top |uhdmallModules: -\_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/ParamOverload1/dut.sv, line:1:1, endln:4:10 +\_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/ParamOverload1/dut.sv, line:1:1, endln:4:10 |vpiParent: \_design: (work@top) |vpiFullName:work@dut |vpiParameter: \_parameter: (work@dut.P), line:2:18, endln:2:19 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/ParamOverload1/dut.sv, line:1:1, endln:4:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/ParamOverload1/dut.sv, line:1:1, endln:4:10 |vpiSize:1 |vpiTypespec: \_array_typespec: @@ -300,7 +300,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:2:18, endln:2:42 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/ParamOverload1/dut.sv, line:1:1, endln:4:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/ParamOverload1/dut.sv, line:1:1, endln:4:10 |vpiRhs: \_operation: , line:2:26, endln:2:42 |vpiOpType:75 @@ -340,13 +340,13 @@ design: (work@top) |vpiNet: \_logic_net: (work@dut.x), line:1:23, endln:1:24 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/ParamOverload1/dut.sv, line:1:1, endln:4:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/ParamOverload1/dut.sv, line:1:1, endln:4:10 |vpiName:x |vpiFullName:work@dut.x |vpiPort: \_port: (x), line:1:23, endln:1:24 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/ParamOverload1/dut.sv, line:1:1, endln:4:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/ParamOverload1/dut.sv, line:1:1, endln:4:10 |vpiName:x |vpiDirection:2 |vpiLowConn: @@ -359,7 +359,7 @@ design: (work@top) |vpiContAssign: \_cont_assign: , line:3:11, endln:3:19 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/ParamOverload1/dut.sv, line:1:1, endln:4:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/ParamOverload1/dut.sv, line:1:1, endln:4:10 |vpiRhs: \_bit_select: (work@dut.P), line:3:15, endln:3:19 |vpiParent: @@ -387,7 +387,7 @@ design: (work@top) |vpiActual: \_int_var: (work@top.u_dut1.x), line:1:23, endln:1:24 |uhdmallModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamOverload1/dut.sv, line:6:1, endln:10:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamOverload1/dut.sv, line:6:1, endln:10:10 |vpiParent: \_design: (work@top) |vpiFullName:work@top @@ -395,13 +395,13 @@ design: (work@top) |vpiNet: \_logic_net: (work@top.o), line:6:23, endln:6:24 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamOverload1/dut.sv, line:6:1, endln:10:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamOverload1/dut.sv, line:6:1, endln:10:10 |vpiName:o |vpiFullName:work@top.o |vpiPort: \_port: (o), line:6:23, endln:6:24 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamOverload1/dut.sv, line:6:1, endln:10:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamOverload1/dut.sv, line:6:1, endln:10:10 |vpiName:o |vpiDirection:2 |vpiLowConn: @@ -412,12 +412,12 @@ design: (work@top) \_int_typespec: , line:6:19, endln:6:22 |vpiSigned:1 |uhdmtopModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamOverload1/dut.sv, line:6:1, endln:10:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamOverload1/dut.sv, line:6:1, endln:10:10 |vpiName:work@top |vpiVariables: \_int_var: (work@top.o), line:6:23, endln:6:24 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamOverload1/dut.sv, line:6:1, endln:10:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamOverload1/dut.sv, line:6:1, endln:10:10 |vpiTypespec: \_int_typespec: , line:6:19, endln:6:22 |vpiSigned:1 @@ -431,7 +431,7 @@ design: (work@top) |vpiPort: \_port: (o), line:6:23, endln:6:24 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamOverload1/dut.sv, line:6:1, endln:10:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamOverload1/dut.sv, line:6:1, endln:10:10 |vpiName:o |vpiDirection:2 |vpiLowConn: @@ -446,17 +446,17 @@ design: (work@top) \_int_typespec: , line:6:19, endln:6:22 |vpiSigned:1 |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamOverload1/dut.sv, line:6:1, endln:10:10 - |vpiModule: - \_module: work@dut (work@top.u_dut1), file:${SURELOG_DIR}/tests/ParamOverload1/dut.sv, line:7:4, endln:7:43 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamOverload1/dut.sv, line:6:1, endln:10:10 + |vpiModuleInst: + \_module_inst: work@dut (work@top.u_dut1), file:${SURELOG_DIR}/tests/ParamOverload1/dut.sv, line:7:4, endln:7:43 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamOverload1/dut.sv, line:6:1, endln:10:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamOverload1/dut.sv, line:6:1, endln:10:10 |vpiName:u_dut1 |vpiFullName:work@top.u_dut1 |vpiVariables: \_int_var: (work@top.u_dut1.x), line:1:23, endln:1:24 |vpiParent: - \_module: work@dut (work@top.u_dut1), file:${SURELOG_DIR}/tests/ParamOverload1/dut.sv, line:7:4, endln:7:43 + \_module_inst: work@dut (work@top.u_dut1), file:${SURELOG_DIR}/tests/ParamOverload1/dut.sv, line:7:4, endln:7:43 |vpiTypespec: \_int_typespec: , line:1:19, endln:1:22 |vpiSigned:1 @@ -467,7 +467,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.u_dut1.P), line:2:18, endln:2:19 |vpiParent: - \_module: work@dut (work@top.u_dut1), file:${SURELOG_DIR}/tests/ParamOverload1/dut.sv, line:7:4, endln:7:43 + \_module_inst: work@dut (work@top.u_dut1), file:${SURELOG_DIR}/tests/ParamOverload1/dut.sv, line:7:4, endln:7:43 |vpiSize:1 |vpiTypespec: \_array_typespec: @@ -548,7 +548,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:2:18, endln:2:42 |vpiParent: - \_module: work@dut (work@top.u_dut1), file:${SURELOG_DIR}/tests/ParamOverload1/dut.sv, line:7:4, endln:7:43 + \_module_inst: work@dut (work@top.u_dut1), file:${SURELOG_DIR}/tests/ParamOverload1/dut.sv, line:7:4, endln:7:43 |vpiOverriden:1 |vpiRhs: \_operation: , line:7:13, endln:7:26 @@ -577,11 +577,11 @@ design: (work@top) |vpiDefFile:${SURELOG_DIR}/tests/ParamOverload1/dut.sv |vpiDefLineNo:1 |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamOverload1/dut.sv, line:6:1, endln:10:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamOverload1/dut.sv, line:6:1, endln:10:10 |vpiPort: \_port: (x), line:1:23, endln:1:24 |vpiParent: - \_module: work@dut (work@top.u_dut1), file:${SURELOG_DIR}/tests/ParamOverload1/dut.sv, line:7:4, endln:7:43 + \_module_inst: work@dut (work@top.u_dut1), file:${SURELOG_DIR}/tests/ParamOverload1/dut.sv, line:7:4, endln:7:43 |vpiName:x |vpiDirection:2 |vpiHighConn: @@ -604,11 +604,11 @@ design: (work@top) \_int_typespec: , line:1:19, endln:1:22 |vpiSigned:1 |vpiInstance: - \_module: work@dut (work@top.u_dut1), file:${SURELOG_DIR}/tests/ParamOverload1/dut.sv, line:7:4, endln:7:43 + \_module_inst: work@dut (work@top.u_dut1), file:${SURELOG_DIR}/tests/ParamOverload1/dut.sv, line:7:4, endln:7:43 |vpiContAssign: \_cont_assign: , line:3:11, endln:3:19 |vpiParent: - \_module: work@dut (work@top.u_dut1), file:${SURELOG_DIR}/tests/ParamOverload1/dut.sv, line:7:4, endln:7:43 + \_module_inst: work@dut (work@top.u_dut1), file:${SURELOG_DIR}/tests/ParamOverload1/dut.sv, line:7:4, endln:7:43 |vpiRhs: \_bit_select: (work@top.u_dut1.P), line:3:15, endln:3:19 |vpiParent: @@ -633,16 +633,16 @@ design: (work@top) |vpiFullName:work@top.u_dut1.x |vpiActual: \_int_var: (work@top.u_dut1.x), line:1:23, endln:1:24 - |vpiModule: - \_module: work@dut (work@top.u_dut2), file:${SURELOG_DIR}/tests/ParamOverload1/dut.sv, line:8:4, endln:8:22 + |vpiModuleInst: + \_module_inst: work@dut (work@top.u_dut2), file:${SURELOG_DIR}/tests/ParamOverload1/dut.sv, line:8:4, endln:8:22 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamOverload1/dut.sv, line:6:1, endln:10:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamOverload1/dut.sv, line:6:1, endln:10:10 |vpiName:u_dut2 |vpiFullName:work@top.u_dut2 |vpiVariables: \_int_var: (work@top.u_dut2.x), line:1:23, endln:1:24 |vpiParent: - \_module: work@dut (work@top.u_dut2), file:${SURELOG_DIR}/tests/ParamOverload1/dut.sv, line:8:4, endln:8:22 + \_module_inst: work@dut (work@top.u_dut2), file:${SURELOG_DIR}/tests/ParamOverload1/dut.sv, line:8:4, endln:8:22 |vpiTypespec: \_int_typespec: , line:1:19, endln:1:22 |vpiSigned:1 @@ -653,7 +653,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.u_dut2.P), line:2:18, endln:2:19 |vpiParent: - \_module: work@dut (work@top.u_dut2), file:${SURELOG_DIR}/tests/ParamOverload1/dut.sv, line:8:4, endln:8:22 + \_module_inst: work@dut (work@top.u_dut2), file:${SURELOG_DIR}/tests/ParamOverload1/dut.sv, line:8:4, endln:8:22 |vpiSize:1 |vpiTypespec: \_array_typespec: @@ -734,7 +734,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:2:18, endln:2:42 |vpiParent: - \_module: work@dut (work@top.u_dut2), file:${SURELOG_DIR}/tests/ParamOverload1/dut.sv, line:8:4, endln:8:22 + \_module_inst: work@dut (work@top.u_dut2), file:${SURELOG_DIR}/tests/ParamOverload1/dut.sv, line:8:4, endln:8:22 |vpiRhs: \_operation: , line:2:26, endln:2:42 |vpiParent: @@ -827,11 +827,11 @@ design: (work@top) |vpiDefFile:${SURELOG_DIR}/tests/ParamOverload1/dut.sv |vpiDefLineNo:1 |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamOverload1/dut.sv, line:6:1, endln:10:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamOverload1/dut.sv, line:6:1, endln:10:10 |vpiPort: \_port: (x), line:1:23, endln:1:24 |vpiParent: - \_module: work@dut (work@top.u_dut2), file:${SURELOG_DIR}/tests/ParamOverload1/dut.sv, line:8:4, endln:8:22 + \_module_inst: work@dut (work@top.u_dut2), file:${SURELOG_DIR}/tests/ParamOverload1/dut.sv, line:8:4, endln:8:22 |vpiName:x |vpiDirection:2 |vpiHighConn: @@ -854,11 +854,11 @@ design: (work@top) \_int_typespec: , line:1:19, endln:1:22 |vpiSigned:1 |vpiInstance: - \_module: work@dut (work@top.u_dut2), file:${SURELOG_DIR}/tests/ParamOverload1/dut.sv, line:8:4, endln:8:22 + \_module_inst: work@dut (work@top.u_dut2), file:${SURELOG_DIR}/tests/ParamOverload1/dut.sv, line:8:4, endln:8:22 |vpiContAssign: \_cont_assign: , line:3:11, endln:3:19 |vpiParent: - \_module: work@dut (work@top.u_dut2), file:${SURELOG_DIR}/tests/ParamOverload1/dut.sv, line:8:4, endln:8:22 + \_module_inst: work@dut (work@top.u_dut2), file:${SURELOG_DIR}/tests/ParamOverload1/dut.sv, line:8:4, endln:8:22 |vpiRhs: \_constant: , line:2:34, endln:2:35 |vpiParent: @@ -875,16 +875,16 @@ design: (work@top) |vpiFullName:work@top.u_dut2.x |vpiActual: \_int_var: (work@top.u_dut2.x), line:1:23, endln:1:24 - |vpiModule: - \_module: work@dut (work@top.u_dut3), file:${SURELOG_DIR}/tests/ParamOverload1/dut.sv, line:9:4, endln:9:34 + |vpiModuleInst: + \_module_inst: work@dut (work@top.u_dut3), file:${SURELOG_DIR}/tests/ParamOverload1/dut.sv, line:9:4, endln:9:34 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamOverload1/dut.sv, line:6:1, endln:10:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamOverload1/dut.sv, line:6:1, endln:10:10 |vpiName:u_dut3 |vpiFullName:work@top.u_dut3 |vpiVariables: \_int_var: (work@top.u_dut3.x), line:1:23, endln:1:24 |vpiParent: - \_module: work@dut (work@top.u_dut3), file:${SURELOG_DIR}/tests/ParamOverload1/dut.sv, line:9:4, endln:9:34 + \_module_inst: work@dut (work@top.u_dut3), file:${SURELOG_DIR}/tests/ParamOverload1/dut.sv, line:9:4, endln:9:34 |vpiTypespec: \_int_typespec: , line:1:19, endln:1:22 |vpiSigned:1 @@ -895,7 +895,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.u_dut3.P), line:2:18, endln:2:19 |vpiParent: - \_module: work@dut (work@top.u_dut3), file:${SURELOG_DIR}/tests/ParamOverload1/dut.sv, line:9:4, endln:9:34 + \_module_inst: work@dut (work@top.u_dut3), file:${SURELOG_DIR}/tests/ParamOverload1/dut.sv, line:9:4, endln:9:34 |vpiSize:1 |vpiTypespec: \_array_typespec: @@ -976,7 +976,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:2:18, endln:2:42 |vpiParent: - \_module: work@dut (work@top.u_dut3), file:${SURELOG_DIR}/tests/ParamOverload1/dut.sv, line:9:4, endln:9:34 + \_module_inst: work@dut (work@top.u_dut3), file:${SURELOG_DIR}/tests/ParamOverload1/dut.sv, line:9:4, endln:9:34 |vpiOverriden:1 |vpiRhs: \_constant: , line:2:26, endln:2:42 @@ -992,11 +992,11 @@ design: (work@top) |vpiDefFile:${SURELOG_DIR}/tests/ParamOverload1/dut.sv |vpiDefLineNo:1 |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamOverload1/dut.sv, line:6:1, endln:10:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamOverload1/dut.sv, line:6:1, endln:10:10 |vpiPort: \_port: (x), line:1:23, endln:1:24 |vpiParent: - \_module: work@dut (work@top.u_dut3), file:${SURELOG_DIR}/tests/ParamOverload1/dut.sv, line:9:4, endln:9:34 + \_module_inst: work@dut (work@top.u_dut3), file:${SURELOG_DIR}/tests/ParamOverload1/dut.sv, line:9:4, endln:9:34 |vpiName:x |vpiDirection:2 |vpiHighConn: @@ -1019,11 +1019,11 @@ design: (work@top) \_int_typespec: , line:1:19, endln:1:22 |vpiSigned:1 |vpiInstance: - \_module: work@dut (work@top.u_dut3), file:${SURELOG_DIR}/tests/ParamOverload1/dut.sv, line:9:4, endln:9:34 + \_module_inst: work@dut (work@top.u_dut3), file:${SURELOG_DIR}/tests/ParamOverload1/dut.sv, line:9:4, endln:9:34 |vpiContAssign: \_cont_assign: , line:3:11, endln:3:19 |vpiParent: - \_module: work@dut (work@top.u_dut3), file:${SURELOG_DIR}/tests/ParamOverload1/dut.sv, line:9:4, endln:9:34 + \_module_inst: work@dut (work@top.u_dut3), file:${SURELOG_DIR}/tests/ParamOverload1/dut.sv, line:9:4, endln:9:34 |vpiRhs: \_constant: , line:2:26, endln:2:27 |vpiParent: diff --git a/tests/ParamOverload2/ParamOverload2.log b/tests/ParamOverload2/ParamOverload2.log index 1bbbc9f542..bde4ef09d4 100644 --- a/tests/ParamOverload2/ParamOverload2.log +++ b/tests/ParamOverload2/ParamOverload2.log @@ -149,7 +149,7 @@ constant 103 design 1 import_typespec 1 logic_typespec 19 -module 6 +module_inst 6 operation 8 package 3 packed_array_typespec 2 @@ -165,7 +165,7 @@ constant 103 design 1 import_typespec 1 logic_typespec 19 -module 6 +module_inst 6 operation 8 package 3 packed_array_typespec 2 @@ -334,7 +334,7 @@ design: (work@top) |vpiTypedefAlias: \_logic_typespec: (keymgr_pkg::lfsr_perm_t), line:2:12, endln:2:29 |vpiParent: - \_module: work@keymgr (work@keymgr), file:${SURELOG_DIR}/tests/ParamOverload2/dut.sv, line:9:1, endln:12:10 + \_module_inst: work@keymgr (work@keymgr), file:${SURELOG_DIR}/tests/ParamOverload2/dut.sv, line:9:1, endln:12:10 |vpiName:keymgr_pkg::lfsr_perm_t |vpiInstance: \_package: keymgr_pkg (keymgr_pkg::), file:${SURELOG_DIR}/tests/ParamOverload2/dut.sv, line:1:1, endln:7:11 @@ -448,14 +448,14 @@ design: (work@top) |vpiDefName:keymgr_pkg |vpiTop:1 |uhdmallModules: -\_module: work@keymgr (work@keymgr), file:${SURELOG_DIR}/tests/ParamOverload2/dut.sv, line:9:1, endln:12:10 +\_module_inst: work@keymgr (work@keymgr), file:${SURELOG_DIR}/tests/ParamOverload2/dut.sv, line:9:1, endln:12:10 |vpiParent: \_design: (work@top) |vpiFullName:work@keymgr |vpiParameter: \_parameter: (work@keymgr.RndCnstLfsrPermDefault), line:3:26, endln:3:48 |vpiParent: - \_module: work@keymgr (work@keymgr), file:${SURELOG_DIR}/tests/ParamOverload2/dut.sv, line:9:1, endln:12:10 + \_module_inst: work@keymgr (work@keymgr), file:${SURELOG_DIR}/tests/ParamOverload2/dut.sv, line:9:1, endln:12:10 |vpiTypespec: \_logic_typespec: (lfsr_perm_t), line:2:12, endln:2:29 |vpiParent: @@ -556,7 +556,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@keymgr.RndCnstLfsrPerm), line:11:26, endln:11:41 |vpiParent: - \_module: work@keymgr (work@keymgr), file:${SURELOG_DIR}/tests/ParamOverload2/dut.sv, line:9:1, endln:12:10 + \_module_inst: work@keymgr (work@keymgr), file:${SURELOG_DIR}/tests/ParamOverload2/dut.sv, line:9:1, endln:12:10 |vpiTypespec: \_logic_typespec: (lfsr_perm_t), line:2:12, endln:2:29 |vpiParent: @@ -611,7 +611,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:3:26, endln:6:5 |vpiParent: - \_module: work@keymgr (work@keymgr), file:${SURELOG_DIR}/tests/ParamOverload2/dut.sv, line:9:1, endln:12:10 + \_module_inst: work@keymgr (work@keymgr), file:${SURELOG_DIR}/tests/ParamOverload2/dut.sv, line:9:1, endln:12:10 |vpiRhs: \_operation: , line:3:51, endln:6:5 |vpiParent: @@ -737,7 +737,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:11:26, endln:11:66 |vpiParent: - \_module: work@keymgr (work@keymgr), file:${SURELOG_DIR}/tests/ParamOverload2/dut.sv, line:9:1, endln:12:10 + \_module_inst: work@keymgr (work@keymgr), file:${SURELOG_DIR}/tests/ParamOverload2/dut.sv, line:9:1, endln:12:10 |vpiRhs: \_ref_obj: (RndCnstLfsrPermDefault), line:11:44, endln:11:66 |vpiName:RndCnstLfsrPermDefault @@ -749,27 +749,27 @@ design: (work@top) \_import_typespec: (keymgr_pkg), line:10:11, endln:10:24 |vpiDefName:work@keymgr |uhdmallModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamOverload2/dut.sv, line:14:1, endln:18:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamOverload2/dut.sv, line:14:1, endln:18:10 |vpiParent: \_design: (work@top) |vpiFullName:work@top |vpiDefName:work@top |uhdmtopModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamOverload2/dut.sv, line:14:1, endln:18:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamOverload2/dut.sv, line:14:1, endln:18:10 |vpiName:work@top |vpiDefName:work@top |vpiTop:1 |vpiTopModule:1 - |vpiModule: - \_module: work@keymgr (work@top.u_keymgr), file:${SURELOG_DIR}/tests/ParamOverload2/dut.sv, line:15:4, endln:17:18 + |vpiModuleInst: + \_module_inst: work@keymgr (work@top.u_keymgr), file:${SURELOG_DIR}/tests/ParamOverload2/dut.sv, line:15:4, endln:17:18 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamOverload2/dut.sv, line:14:1, endln:18:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamOverload2/dut.sv, line:14:1, endln:18:10 |vpiName:u_keymgr |vpiFullName:work@top.u_keymgr |vpiParameter: \_parameter: (work@top.u_keymgr.RndCnstLfsrPermDefault), line:3:26, endln:3:48 |vpiParent: - \_module: work@keymgr (work@top.u_keymgr), file:${SURELOG_DIR}/tests/ParamOverload2/dut.sv, line:15:4, endln:17:18 + \_module_inst: work@keymgr (work@top.u_keymgr), file:${SURELOG_DIR}/tests/ParamOverload2/dut.sv, line:15:4, endln:17:18 |vpiTypespec: \_logic_typespec: (lfsr_perm_t), line:2:12, endln:2:29 |vpiParent: @@ -870,7 +870,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.u_keymgr.RndCnstLfsrPerm), line:11:26, endln:11:41 |vpiParent: - \_module: work@keymgr (work@top.u_keymgr), file:${SURELOG_DIR}/tests/ParamOverload2/dut.sv, line:15:4, endln:17:18 + \_module_inst: work@keymgr (work@top.u_keymgr), file:${SURELOG_DIR}/tests/ParamOverload2/dut.sv, line:15:4, endln:17:18 |vpiTypespec: \_logic_typespec: (lfsr_perm_t), line:2:12, endln:2:29 |vpiParent: @@ -970,7 +970,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:3:26, endln:6:5 |vpiParent: - \_module: work@keymgr (work@top.u_keymgr), file:${SURELOG_DIR}/tests/ParamOverload2/dut.sv, line:15:4, endln:17:18 + \_module_inst: work@keymgr (work@top.u_keymgr), file:${SURELOG_DIR}/tests/ParamOverload2/dut.sv, line:15:4, endln:17:18 |vpiRhs: \_operation: , line:3:51, endln:6:5 |vpiTypespec: @@ -1089,7 +1089,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:11:26, endln:11:66 |vpiParent: - \_module: work@keymgr (work@top.u_keymgr), file:${SURELOG_DIR}/tests/ParamOverload2/dut.sv, line:15:4, endln:17:18 + \_module_inst: work@keymgr (work@top.u_keymgr), file:${SURELOG_DIR}/tests/ParamOverload2/dut.sv, line:15:4, endln:17:18 |vpiOverriden:1 |vpiRhs: \_constant: , line:11:44, endln:11:66 @@ -1109,7 +1109,7 @@ design: (work@top) |vpiDefFile:${SURELOG_DIR}/tests/ParamOverload2/dut.sv |vpiDefLineNo:9 |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamOverload2/dut.sv, line:14:1, endln:18:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamOverload2/dut.sv, line:14:1, endln:18:10 =================== [ FATAL] : 0 [ SYNTAX] : 0 diff --git a/tests/ParamOverload3/ParamOverload3.log b/tests/ParamOverload3/ParamOverload3.log index 0c0ff7db0c..9be76ad551 100644 --- a/tests/ParamOverload3/ParamOverload3.log +++ b/tests/ParamOverload3/ParamOverload3.log @@ -677,7 +677,7 @@ int_typespec 51 int_var 2 io_decl 2 logic_typespec 2 -module 28 +module_inst 28 operation 95 package 3 packed_array_typespec 4 @@ -711,7 +711,7 @@ int_typespec 51 int_var 2 io_decl 4 logic_typespec 2 -module 28 +module_inst 28 operation 99 package 3 packed_array_typespec 4 @@ -1720,14 +1720,14 @@ design: (work@top) |vpiInstance: \_package: fpnew_pkg (fpnew_pkg::), file:${SURELOG_DIR}/tests/ParamOverload3/dut.sv, line:1:1, endln:41:11 |uhdmallModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamOverload3/dut.sv, line:43:1, endln:64:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamOverload3/dut.sv, line:43:1, endln:64:10 |vpiParent: \_design: (work@top) |vpiFullName:work@top |vpiParameter: \_parameter: (work@top.NUM_FORMATS), line:44:28, endln:44:39 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamOverload3/dut.sv, line:43:1, endln:64:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamOverload3/dut.sv, line:43:1, endln:64:10 |UINT:5 |vpiTypespec: \_int_typespec: , line:44:15, endln:44:27 @@ -1739,7 +1739,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.Features), line:45:46, endln:45:54 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamOverload3/dut.sv, line:43:1, endln:64:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamOverload3/dut.sv, line:43:1, endln:64:10 |vpiTypespec: \_unsupported_typespec: (fpnew_pkg::fpu_features_t), line:45:14, endln:45:25 |vpiParent: @@ -1750,13 +1750,13 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.WIDTH), line:46:14, endln:46:19 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamOverload3/dut.sv, line:43:1, endln:64:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamOverload3/dut.sv, line:43:1, endln:64:10 |vpiName:WIDTH |vpiFullName:work@top.WIDTH |vpiParamAssign: \_param_assign: , line:44:28, endln:44:68 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamOverload3/dut.sv, line:43:1, endln:64:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamOverload3/dut.sv, line:43:1, endln:64:10 |vpiRhs: \_constant: , line:44:43, endln:44:54 |vpiDecompile:5 @@ -1770,7 +1770,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:45:46, endln:45:85 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamOverload3/dut.sv, line:43:1, endln:64:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamOverload3/dut.sv, line:43:1, endln:64:10 |vpiRhs: \_operation: , line:45:63, endln:45:74 |vpiOpType:75 @@ -1864,7 +1864,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:46:14, endln:46:36 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamOverload3/dut.sv, line:43:1, endln:64:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamOverload3/dut.sv, line:43:1, endln:64:10 |vpiRhs: \_hier_path: (Features.Width), line:46:22, endln:46:36 |vpiName:Features.Width @@ -1880,12 +1880,12 @@ design: (work@top) \_parameter: (work@top.WIDTH), line:46:14, endln:46:19 |vpiDefName:work@top |uhdmtopModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamOverload3/dut.sv, line:43:1, endln:64:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamOverload3/dut.sv, line:43:1, endln:64:10 |vpiName:work@top |vpiParameter: \_parameter: (work@top.NUM_FORMATS), line:44:28, endln:44:39 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamOverload3/dut.sv, line:43:1, endln:64:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamOverload3/dut.sv, line:43:1, endln:64:10 |UINT:5 |vpiTypespec: \_int_typespec: , line:44:15, endln:44:27 @@ -1897,7 +1897,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.Features), line:45:46, endln:45:54 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamOverload3/dut.sv, line:43:1, endln:64:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamOverload3/dut.sv, line:43:1, endln:64:10 |vpiTypespec: \_unsupported_typespec: (fpnew_pkg::fpu_features_t), line:45:14, endln:45:25 |vpiParent: @@ -1908,13 +1908,13 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.WIDTH), line:46:14, endln:46:19 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamOverload3/dut.sv, line:43:1, endln:64:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamOverload3/dut.sv, line:43:1, endln:64:10 |vpiName:WIDTH |vpiFullName:work@top.WIDTH |vpiParamAssign: \_param_assign: , line:44:28, endln:44:68 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamOverload3/dut.sv, line:43:1, endln:64:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamOverload3/dut.sv, line:43:1, endln:64:10 |vpiRhs: \_constant: , line:44:43, endln:44:68 |vpiDecompile:5 @@ -1928,7 +1928,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:45:46, endln:45:85 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamOverload3/dut.sv, line:43:1, endln:64:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamOverload3/dut.sv, line:43:1, endln:64:10 |vpiRhs: \_operation: , line:45:63, endln:45:74 |vpiParent: @@ -2024,7 +2024,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:46:14, endln:46:36 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamOverload3/dut.sv, line:43:1, endln:64:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamOverload3/dut.sv, line:43:1, endln:64:10 |vpiRhs: \_constant: , line:46:22, endln:46:36 |vpiDecompile:64 @@ -2039,7 +2039,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.gen_nanbox_check[0]), line:49:56, endln:62:6 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamOverload3/dut.sv, line:43:1, endln:64:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamOverload3/dut.sv, line:43:1, endln:64:10 |vpiName:gen_nanbox_check[0] |vpiFullName:work@top.gen_nanbox_check[0] |vpiGenScope: @@ -2099,7 +2099,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.gen_nanbox_check[1]), line:49:56, endln:62:6 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamOverload3/dut.sv, line:43:1, endln:64:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamOverload3/dut.sv, line:43:1, endln:64:10 |vpiName:gen_nanbox_check[1] |vpiFullName:work@top.gen_nanbox_check[1] |vpiGenScope: @@ -2189,7 +2189,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.gen_nanbox_check[2]), line:49:56, endln:62:6 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamOverload3/dut.sv, line:43:1, endln:64:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamOverload3/dut.sv, line:43:1, endln:64:10 |vpiName:gen_nanbox_check[2] |vpiFullName:work@top.gen_nanbox_check[2] |vpiGenScope: @@ -2249,7 +2249,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.gen_nanbox_check[3]), line:49:56, endln:62:6 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamOverload3/dut.sv, line:43:1, endln:64:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamOverload3/dut.sv, line:43:1, endln:64:10 |vpiName:gen_nanbox_check[3] |vpiFullName:work@top.gen_nanbox_check[3] |vpiGenScope: @@ -2309,7 +2309,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.gen_nanbox_check[4]), line:49:56, endln:62:6 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamOverload3/dut.sv, line:43:1, endln:64:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamOverload3/dut.sv, line:43:1, endln:64:10 |vpiName:gen_nanbox_check[4] |vpiFullName:work@top.gen_nanbox_check[4] |vpiGenScope: diff --git a/tests/ParamOverload4/ParamOverload4.log b/tests/ParamOverload4/ParamOverload4.log index 8597da4d07..2c52334a1f 100644 --- a/tests/ParamOverload4/ParamOverload4.log +++ b/tests/ParamOverload4/ParamOverload4.log @@ -695,7 +695,7 @@ design 1 gen_scope 520 gen_scope_array 520 int_typespec 138 -module 5 +module_inst 5 operation 397 param_assign 6 parameter 138 @@ -708,7 +708,7 @@ design 1 gen_scope 780 gen_scope_array 780 int_typespec 138 -module 5 +module_inst 5 operation 397 param_assign 6 parameter 138 @@ -726,14 +726,14 @@ design: (work@ibex_pmp) |vpiElaborated:1 |vpiName:work@ibex_pmp |uhdmallModules: -\_module: work@ibex_pmp (work@ibex_pmp), file:${SURELOG_DIR}/tests/ParamOverload4/dut.sv, line:2:1, endln:34:10 +\_module_inst: work@ibex_pmp (work@ibex_pmp), file:${SURELOG_DIR}/tests/ParamOverload4/dut.sv, line:2:1, endln:34:10 |vpiParent: \_design: (work@ibex_pmp) |vpiFullName:work@ibex_pmp |vpiParameter: \_parameter: (work@ibex_pmp.PMPGranularity), line:5:28, endln:5:42 |vpiParent: - \_module: work@ibex_pmp (work@ibex_pmp), file:${SURELOG_DIR}/tests/ParamOverload4/dut.sv, line:2:1, endln:34:10 + \_module_inst: work@ibex_pmp (work@ibex_pmp), file:${SURELOG_DIR}/tests/ParamOverload4/dut.sv, line:2:1, endln:34:10 |UINT:0 |vpiTypespec: \_int_typespec: , line:5:15, endln:5:27 @@ -744,7 +744,7 @@ design: (work@ibex_pmp) |vpiParameter: \_parameter: (work@ibex_pmp.PMPNumChan), line:7:28, endln:7:38 |vpiParent: - \_module: work@ibex_pmp (work@ibex_pmp), file:${SURELOG_DIR}/tests/ParamOverload4/dut.sv, line:2:1, endln:34:10 + \_module_inst: work@ibex_pmp (work@ibex_pmp), file:${SURELOG_DIR}/tests/ParamOverload4/dut.sv, line:2:1, endln:34:10 |UINT:2 |vpiTypespec: \_int_typespec: , line:7:15, endln:7:27 @@ -755,7 +755,7 @@ design: (work@ibex_pmp) |vpiParameter: \_parameter: (work@ibex_pmp.PMPNumRegions), line:9:28, endln:9:41 |vpiParent: - \_module: work@ibex_pmp (work@ibex_pmp), file:${SURELOG_DIR}/tests/ParamOverload4/dut.sv, line:2:1, endln:34:10 + \_module_inst: work@ibex_pmp (work@ibex_pmp), file:${SURELOG_DIR}/tests/ParamOverload4/dut.sv, line:2:1, endln:34:10 |UINT:4 |vpiTypespec: \_int_typespec: , line:9:15, endln:9:27 @@ -766,7 +766,7 @@ design: (work@ibex_pmp) |vpiParamAssign: \_param_assign: , line:5:28, endln:5:46 |vpiParent: - \_module: work@ibex_pmp (work@ibex_pmp), file:${SURELOG_DIR}/tests/ParamOverload4/dut.sv, line:2:1, endln:34:10 + \_module_inst: work@ibex_pmp (work@ibex_pmp), file:${SURELOG_DIR}/tests/ParamOverload4/dut.sv, line:2:1, endln:34:10 |vpiRhs: \_constant: , line:5:45, endln:5:46 |vpiDecompile:0 @@ -780,7 +780,7 @@ design: (work@ibex_pmp) |vpiParamAssign: \_param_assign: , line:7:28, endln:7:46 |vpiParent: - \_module: work@ibex_pmp (work@ibex_pmp), file:${SURELOG_DIR}/tests/ParamOverload4/dut.sv, line:2:1, endln:34:10 + \_module_inst: work@ibex_pmp (work@ibex_pmp), file:${SURELOG_DIR}/tests/ParamOverload4/dut.sv, line:2:1, endln:34:10 |vpiRhs: \_constant: , line:7:45, endln:7:46 |vpiDecompile:2 @@ -794,7 +794,7 @@ design: (work@ibex_pmp) |vpiParamAssign: \_param_assign: , line:9:28, endln:9:46 |vpiParent: - \_module: work@ibex_pmp (work@ibex_pmp), file:${SURELOG_DIR}/tests/ParamOverload4/dut.sv, line:2:1, endln:34:10 + \_module_inst: work@ibex_pmp (work@ibex_pmp), file:${SURELOG_DIR}/tests/ParamOverload4/dut.sv, line:2:1, endln:34:10 |vpiRhs: \_constant: , line:9:45, endln:9:46 |vpiDecompile:4 @@ -807,12 +807,12 @@ design: (work@ibex_pmp) \_parameter: (work@ibex_pmp.PMPNumRegions), line:9:28, endln:9:41 |vpiDefName:work@ibex_pmp |uhdmtopModules: -\_module: work@ibex_pmp (work@ibex_pmp), file:${SURELOG_DIR}/tests/ParamOverload4/dut.sv, line:2:1, endln:34:10 +\_module_inst: work@ibex_pmp (work@ibex_pmp), file:${SURELOG_DIR}/tests/ParamOverload4/dut.sv, line:2:1, endln:34:10 |vpiName:work@ibex_pmp |vpiParameter: \_parameter: (work@ibex_pmp.PMPGranularity), line:5:28, endln:5:42 |vpiParent: - \_module: work@ibex_pmp (work@ibex_pmp), file:${SURELOG_DIR}/tests/ParamOverload4/dut.sv, line:2:1, endln:34:10 + \_module_inst: work@ibex_pmp (work@ibex_pmp), file:${SURELOG_DIR}/tests/ParamOverload4/dut.sv, line:2:1, endln:34:10 |UINT:0 |vpiTypespec: \_int_typespec: , line:5:15, endln:5:27 @@ -823,7 +823,7 @@ design: (work@ibex_pmp) |vpiParameter: \_parameter: (work@ibex_pmp.PMPNumChan), line:7:28, endln:7:38 |vpiParent: - \_module: work@ibex_pmp (work@ibex_pmp), file:${SURELOG_DIR}/tests/ParamOverload4/dut.sv, line:2:1, endln:34:10 + \_module_inst: work@ibex_pmp (work@ibex_pmp), file:${SURELOG_DIR}/tests/ParamOverload4/dut.sv, line:2:1, endln:34:10 |UINT:2 |vpiTypespec: \_int_typespec: , line:7:15, endln:7:27 @@ -834,7 +834,7 @@ design: (work@ibex_pmp) |vpiParameter: \_parameter: (work@ibex_pmp.PMPNumRegions), line:9:28, endln:9:41 |vpiParent: - \_module: work@ibex_pmp (work@ibex_pmp), file:${SURELOG_DIR}/tests/ParamOverload4/dut.sv, line:2:1, endln:34:10 + \_module_inst: work@ibex_pmp (work@ibex_pmp), file:${SURELOG_DIR}/tests/ParamOverload4/dut.sv, line:2:1, endln:34:10 |UINT:4 |vpiTypespec: \_int_typespec: , line:9:15, endln:9:27 @@ -845,7 +845,7 @@ design: (work@ibex_pmp) |vpiParamAssign: \_param_assign: , line:5:28, endln:5:46 |vpiParent: - \_module: work@ibex_pmp (work@ibex_pmp), file:${SURELOG_DIR}/tests/ParamOverload4/dut.sv, line:2:1, endln:34:10 + \_module_inst: work@ibex_pmp (work@ibex_pmp), file:${SURELOG_DIR}/tests/ParamOverload4/dut.sv, line:2:1, endln:34:10 |vpiRhs: \_constant: , line:5:45, endln:5:46 |vpiDecompile:0 @@ -859,7 +859,7 @@ design: (work@ibex_pmp) |vpiParamAssign: \_param_assign: , line:7:28, endln:7:46 |vpiParent: - \_module: work@ibex_pmp (work@ibex_pmp), file:${SURELOG_DIR}/tests/ParamOverload4/dut.sv, line:2:1, endln:34:10 + \_module_inst: work@ibex_pmp (work@ibex_pmp), file:${SURELOG_DIR}/tests/ParamOverload4/dut.sv, line:2:1, endln:34:10 |vpiRhs: \_constant: , line:7:45, endln:7:46 |vpiDecompile:2 @@ -873,7 +873,7 @@ design: (work@ibex_pmp) |vpiParamAssign: \_param_assign: , line:9:28, endln:9:46 |vpiParent: - \_module: work@ibex_pmp (work@ibex_pmp), file:${SURELOG_DIR}/tests/ParamOverload4/dut.sv, line:2:1, endln:34:10 + \_module_inst: work@ibex_pmp (work@ibex_pmp), file:${SURELOG_DIR}/tests/ParamOverload4/dut.sv, line:2:1, endln:34:10 |vpiRhs: \_constant: , line:9:45, endln:9:46 |vpiDecompile:4 @@ -890,7 +890,7 @@ design: (work@ibex_pmp) |vpiGenScopeArray: \_gen_scope_array: (work@ibex_pmp.g_addr_exp[0]), line:20:46, endln:30:6 |vpiParent: - \_module: work@ibex_pmp (work@ibex_pmp), file:${SURELOG_DIR}/tests/ParamOverload4/dut.sv, line:2:1, endln:34:10 + \_module_inst: work@ibex_pmp (work@ibex_pmp), file:${SURELOG_DIR}/tests/ParamOverload4/dut.sv, line:2:1, endln:34:10 |vpiName:g_addr_exp[0] |vpiFullName:work@ibex_pmp.g_addr_exp[0] |vpiGenScope: @@ -1935,7 +1935,7 @@ design: (work@ibex_pmp) |vpiGenScopeArray: \_gen_scope_array: (work@ibex_pmp.g_addr_exp[1]), line:20:46, endln:30:6 |vpiParent: - \_module: work@ibex_pmp (work@ibex_pmp), file:${SURELOG_DIR}/tests/ParamOverload4/dut.sv, line:2:1, endln:34:10 + \_module_inst: work@ibex_pmp (work@ibex_pmp), file:${SURELOG_DIR}/tests/ParamOverload4/dut.sv, line:2:1, endln:34:10 |vpiName:g_addr_exp[1] |vpiFullName:work@ibex_pmp.g_addr_exp[1] |vpiGenScope: @@ -2980,7 +2980,7 @@ design: (work@ibex_pmp) |vpiGenScopeArray: \_gen_scope_array: (work@ibex_pmp.g_addr_exp[2]), line:20:46, endln:30:6 |vpiParent: - \_module: work@ibex_pmp (work@ibex_pmp), file:${SURELOG_DIR}/tests/ParamOverload4/dut.sv, line:2:1, endln:34:10 + \_module_inst: work@ibex_pmp (work@ibex_pmp), file:${SURELOG_DIR}/tests/ParamOverload4/dut.sv, line:2:1, endln:34:10 |vpiName:g_addr_exp[2] |vpiFullName:work@ibex_pmp.g_addr_exp[2] |vpiGenScope: @@ -4025,7 +4025,7 @@ design: (work@ibex_pmp) |vpiGenScopeArray: \_gen_scope_array: (work@ibex_pmp.g_addr_exp[3]), line:20:46, endln:30:6 |vpiParent: - \_module: work@ibex_pmp (work@ibex_pmp), file:${SURELOG_DIR}/tests/ParamOverload4/dut.sv, line:2:1, endln:34:10 + \_module_inst: work@ibex_pmp (work@ibex_pmp), file:${SURELOG_DIR}/tests/ParamOverload4/dut.sv, line:2:1, endln:34:10 |vpiName:g_addr_exp[3] |vpiFullName:work@ibex_pmp.g_addr_exp[3] |vpiGenScope: diff --git a/tests/ParamOverloadProp/ParamOverloadProp.log b/tests/ParamOverloadProp/ParamOverloadProp.log index c0d6f433ac..a200c2bb09 100644 --- a/tests/ParamOverloadProp/ParamOverloadProp.log +++ b/tests/ParamOverloadProp/ParamOverloadProp.log @@ -116,7 +116,7 @@ constant 16 design 1 int_typespec 2 logic_typespec 2 -module 7 +module_inst 7 operation 2 param_assign 4 parameter 4 @@ -130,7 +130,7 @@ constant 16 design 1 int_typespec 2 logic_typespec 2 -module 7 +module_inst 7 operation 2 param_assign 4 parameter 4 @@ -150,14 +150,14 @@ design: (work@top) |vpiElaborated:1 |vpiName:work@top |uhdmallModules: -\_module: work@prim_flop (work@prim_flop), file:${SURELOG_DIR}/tests/ParamOverloadProp/dut.sv, line:7:1, endln:10:10 +\_module_inst: work@prim_flop (work@prim_flop), file:${SURELOG_DIR}/tests/ParamOverloadProp/dut.sv, line:7:1, endln:10:10 |vpiParent: \_design: (work@top) |vpiFullName:work@prim_flop |vpiParameter: \_parameter: (work@prim_flop.Width), line:8:18, endln:8:23 |vpiParent: - \_module: work@prim_flop (work@prim_flop), file:${SURELOG_DIR}/tests/ParamOverloadProp/dut.sv, line:7:1, endln:10:10 + \_module_inst: work@prim_flop (work@prim_flop), file:${SURELOG_DIR}/tests/ParamOverloadProp/dut.sv, line:7:1, endln:10:10 |UINT:1 |vpiTypespec: \_int_typespec: , line:8:14, endln:8:17 @@ -170,7 +170,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@prim_flop.ResetValue), line:9:32, endln:9:42 |vpiParent: - \_module: work@prim_flop (work@prim_flop), file:${SURELOG_DIR}/tests/ParamOverloadProp/dut.sv, line:7:1, endln:10:10 + \_module_inst: work@prim_flop (work@prim_flop), file:${SURELOG_DIR}/tests/ParamOverloadProp/dut.sv, line:7:1, endln:10:10 |vpiTypespec: \_logic_typespec: , line:9:14, endln:9:31 |vpiParent: @@ -210,7 +210,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:8:18, endln:8:27 |vpiParent: - \_module: work@prim_flop (work@prim_flop), file:${SURELOG_DIR}/tests/ParamOverloadProp/dut.sv, line:7:1, endln:10:10 + \_module_inst: work@prim_flop (work@prim_flop), file:${SURELOG_DIR}/tests/ParamOverloadProp/dut.sv, line:7:1, endln:10:10 |vpiRhs: \_constant: , line:8:26, endln:8:27 |vpiDecompile:1 @@ -224,7 +224,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:9:32, endln:9:50 |vpiParent: - \_module: work@prim_flop (work@prim_flop), file:${SURELOG_DIR}/tests/ParamOverloadProp/dut.sv, line:7:1, endln:10:10 + \_module_inst: work@prim_flop (work@prim_flop), file:${SURELOG_DIR}/tests/ParamOverloadProp/dut.sv, line:7:1, endln:10:10 |vpiRhs: \_ref_obj: (Width), line:9:45, endln:9:50 |vpiName:Width @@ -232,27 +232,27 @@ design: (work@top) \_parameter: (work@prim_flop.ResetValue), line:9:32, endln:9:42 |vpiDefName:work@prim_flop |uhdmallModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamOverloadProp/dut.sv, line:1:1, endln:5:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamOverloadProp/dut.sv, line:1:1, endln:5:10 |vpiParent: \_design: (work@top) |vpiFullName:work@top |vpiDefName:work@top |uhdmtopModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamOverloadProp/dut.sv, line:1:1, endln:5:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamOverloadProp/dut.sv, line:1:1, endln:5:10 |vpiName:work@top |vpiDefName:work@top |vpiTop:1 |vpiTopModule:1 - |vpiModule: - \_module: work@prim_flop (work@top.u_prim_flop), file:${SURELOG_DIR}/tests/ParamOverloadProp/dut.sv, line:2:4, endln:4:20 + |vpiModuleInst: + \_module_inst: work@prim_flop (work@top.u_prim_flop), file:${SURELOG_DIR}/tests/ParamOverloadProp/dut.sv, line:2:4, endln:4:20 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamOverloadProp/dut.sv, line:1:1, endln:5:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamOverloadProp/dut.sv, line:1:1, endln:5:10 |vpiName:u_prim_flop |vpiFullName:work@top.u_prim_flop |vpiParameter: \_parameter: (work@top.u_prim_flop.Width), line:8:18, endln:8:23 |vpiParent: - \_module: work@prim_flop (work@top.u_prim_flop), file:${SURELOG_DIR}/tests/ParamOverloadProp/dut.sv, line:2:4, endln:4:20 + \_module_inst: work@prim_flop (work@top.u_prim_flop), file:${SURELOG_DIR}/tests/ParamOverloadProp/dut.sv, line:2:4, endln:4:20 |UINT:1 |vpiTypespec: \_int_typespec: , line:8:14, endln:8:17 @@ -265,7 +265,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.u_prim_flop.ResetValue), line:9:32, endln:9:42 |vpiParent: - \_module: work@prim_flop (work@top.u_prim_flop), file:${SURELOG_DIR}/tests/ParamOverloadProp/dut.sv, line:2:4, endln:4:20 + \_module_inst: work@prim_flop (work@top.u_prim_flop), file:${SURELOG_DIR}/tests/ParamOverloadProp/dut.sv, line:2:4, endln:4:20 |vpiTypespec: \_logic_typespec: , line:9:14, endln:9:31 |vpiParent: @@ -308,7 +308,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:8:18, endln:8:27 |vpiParent: - \_module: work@prim_flop (work@top.u_prim_flop), file:${SURELOG_DIR}/tests/ParamOverloadProp/dut.sv, line:2:4, endln:4:20 + \_module_inst: work@prim_flop (work@top.u_prim_flop), file:${SURELOG_DIR}/tests/ParamOverloadProp/dut.sv, line:2:4, endln:4:20 |vpiOverriden:1 |vpiRhs: \_constant: , line:8:26, endln:8:27 @@ -323,7 +323,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:9:32, endln:9:50 |vpiParent: - \_module: work@prim_flop (work@top.u_prim_flop), file:${SURELOG_DIR}/tests/ParamOverloadProp/dut.sv, line:2:4, endln:4:20 + \_module_inst: work@prim_flop (work@top.u_prim_flop), file:${SURELOG_DIR}/tests/ParamOverloadProp/dut.sv, line:2:4, endln:4:20 |vpiOverriden:1 |vpiRhs: \_constant: , line:9:45, endln:9:50 @@ -339,7 +339,7 @@ design: (work@top) |vpiDefFile:${SURELOG_DIR}/tests/ParamOverloadProp/dut.sv |vpiDefLineNo:7 |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamOverloadProp/dut.sv, line:1:1, endln:5:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamOverloadProp/dut.sv, line:1:1, endln:5:10 =================== [ FATAL] : 0 [ SYNTAX] : 0 diff --git a/tests/ParamOverloading/ParamOverloading.log b/tests/ParamOverloading/ParamOverloading.log index 500e268f42..684d561047 100644 --- a/tests/ParamOverloading/ParamOverloading.log +++ b/tests/ParamOverloading/ParamOverloading.log @@ -327,7 +327,7 @@ int_typespec 6 int_var 1 logic_net 1 logic_typespec 36 -module 12 +module_inst 12 operation 17 param_assign 10 parameter 13 @@ -347,7 +347,7 @@ int_typespec 6 int_var 1 logic_net 1 logic_typespec 36 -module 12 +module_inst 12 operation 17 param_assign 10 parameter 13 @@ -371,14 +371,14 @@ design: (work@top) |vpiElaborated:1 |vpiName:work@top |uhdmallModules: -\_module: work@prim_subreg (work@prim_subreg), file:${SURELOG_DIR}/tests/ParamOverloading/dut.sv, line:2:1, endln:5:10 +\_module_inst: work@prim_subreg (work@prim_subreg), file:${SURELOG_DIR}/tests/ParamOverloading/dut.sv, line:2:1, endln:5:10 |vpiParent: \_design: (work@top) |vpiFullName:work@prim_subreg |vpiParameter: \_parameter: (work@prim_subreg.RESVAL), line:3:26, endln:3:32 |vpiParent: - \_module: work@prim_subreg (work@prim_subreg), file:${SURELOG_DIR}/tests/ParamOverloading/dut.sv, line:2:1, endln:5:10 + \_module_inst: work@prim_subreg (work@prim_subreg), file:${SURELOG_DIR}/tests/ParamOverloading/dut.sv, line:2:1, endln:5:10 |BIN:0 |vpiTypespec: \_logic_typespec: , line:3:14, endln:3:25 @@ -407,7 +407,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:3:26, endln:3:37 |vpiParent: - \_module: work@prim_subreg (work@prim_subreg), file:${SURELOG_DIR}/tests/ParamOverloading/dut.sv, line:2:1, endln:5:10 + \_module_inst: work@prim_subreg (work@prim_subreg), file:${SURELOG_DIR}/tests/ParamOverloading/dut.sv, line:2:1, endln:5:10 |vpiRhs: \_constant: , line:3:35, endln:3:37 |vpiDecompile:'0 @@ -422,25 +422,25 @@ design: (work@top) |vpiNet: \_logic_net: (work@prim_subreg.a), line:4:8, endln:4:9 |vpiParent: - \_module: work@prim_subreg (work@prim_subreg), file:${SURELOG_DIR}/tests/ParamOverloading/dut.sv, line:2:1, endln:5:10 + \_module_inst: work@prim_subreg (work@prim_subreg), file:${SURELOG_DIR}/tests/ParamOverloading/dut.sv, line:2:1, endln:5:10 |vpiName:a |vpiFullName:work@prim_subreg.a |uhdmallModules: -\_module: work@prim_subreg_shadow (work@prim_subreg_shadow), file:${SURELOG_DIR}/tests/ParamOverloading/dut.sv, line:7:1, endln:22:10 +\_module_inst: work@prim_subreg_shadow (work@prim_subreg_shadow), file:${SURELOG_DIR}/tests/ParamOverloading/dut.sv, line:7:1, endln:22:10 |vpiParent: \_design: (work@top) |vpiFullName:work@prim_subreg_shadow |vpiParameter: \_parameter: (work@prim_subreg_shadow.RESVAL), line:13:24, endln:13:30 |vpiParent: - \_module: work@prim_subreg_shadow (work@prim_subreg_shadow), file:${SURELOG_DIR}/tests/ParamOverloading/dut.sv, line:7:1, endln:22:10 + \_module_inst: work@prim_subreg_shadow (work@prim_subreg_shadow), file:${SURELOG_DIR}/tests/ParamOverloading/dut.sv, line:7:1, endln:22:10 |vpiTypespec: \_struct_typespec: (struct_ab), line:8:12, endln:8:18 |vpiParent: - \_module: work@prim_subreg_shadow (work@prim_subreg_shadow), file:${SURELOG_DIR}/tests/ParamOverloading/dut.sv, line:7:1, endln:22:10 + \_module_inst: work@prim_subreg_shadow (work@prim_subreg_shadow), file:${SURELOG_DIR}/tests/ParamOverloading/dut.sv, line:7:1, endln:22:10 |vpiName:struct_ab |vpiInstance: - \_module: work@prim_subreg_shadow (work@prim_subreg_shadow), file:${SURELOG_DIR}/tests/ParamOverloading/dut.sv, line:7:1, endln:22:10 + \_module_inst: work@prim_subreg_shadow (work@prim_subreg_shadow), file:${SURELOG_DIR}/tests/ParamOverloading/dut.sv, line:7:1, endln:22:10 |vpiPacked:1 |vpiTypespecMember: \_typespec_member: (a), line:9:19, endln:9:20 @@ -515,7 +515,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:13:24, endln:16:5 |vpiParent: - \_module: work@prim_subreg_shadow (work@prim_subreg_shadow), file:${SURELOG_DIR}/tests/ParamOverloading/dut.sv, line:7:1, endln:22:10 + \_module_inst: work@prim_subreg_shadow (work@prim_subreg_shadow), file:${SURELOG_DIR}/tests/ParamOverloading/dut.sv, line:7:1, endln:22:10 |vpiRhs: \_operation: , line:13:33, endln:16:5 |vpiOpType:75 @@ -547,14 +547,14 @@ design: (work@top) \_struct_typespec: (struct_ab), line:8:12, endln:8:18 |vpiDefName:work@prim_subreg_shadow |uhdmallModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamOverloading/dut.sv, line:24:1, endln:41:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamOverloading/dut.sv, line:24:1, endln:41:10 |vpiParent: \_design: (work@top) |vpiFullName:work@top |vpiParameter: \_parameter: (work@top.v1), line:29:14, endln:29:16 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamOverloading/dut.sv, line:24:1, endln:41:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamOverloading/dut.sv, line:24:1, endln:41:10 |UINT:1 |vpiTypespec: \_int_typespec: @@ -563,7 +563,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.v2), line:30:14, endln:30:16 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamOverloading/dut.sv, line:24:1, endln:41:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamOverloading/dut.sv, line:24:1, endln:41:10 |UINT:0 |vpiTypespec: \_int_typespec: @@ -572,14 +572,14 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.CTRL_RESET), line:32:24, endln:32:34 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamOverloading/dut.sv, line:24:1, endln:41:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamOverloading/dut.sv, line:24:1, endln:41:10 |vpiTypespec: \_struct_typespec: (struct_ab), line:25:12, endln:25:18 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamOverloading/dut.sv, line:24:1, endln:41:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamOverloading/dut.sv, line:24:1, endln:41:10 |vpiName:struct_ab |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamOverloading/dut.sv, line:24:1, endln:41:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamOverloading/dut.sv, line:24:1, endln:41:10 |vpiPacked:1 |vpiTypespecMember: \_typespec_member: (a), line:26:19, endln:26:20 @@ -654,7 +654,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:29:14, endln:29:20 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamOverloading/dut.sv, line:24:1, endln:41:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamOverloading/dut.sv, line:24:1, endln:41:10 |vpiRhs: \_constant: , line:29:19, endln:29:20 |vpiDecompile:1 @@ -668,7 +668,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:30:14, endln:30:20 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamOverloading/dut.sv, line:24:1, endln:41:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamOverloading/dut.sv, line:24:1, endln:41:10 |vpiRhs: \_constant: , line:30:19, endln:30:20 |vpiDecompile:0 @@ -682,7 +682,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:32:24, endln:36:5 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamOverloading/dut.sv, line:24:1, endln:41:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamOverloading/dut.sv, line:24:1, endln:41:10 |vpiRhs: \_operation: , line:32:37, endln:36:5 |vpiOpType:75 @@ -702,12 +702,12 @@ design: (work@top) \_struct_typespec: (struct_ab), line:25:12, endln:25:18 |vpiDefName:work@top |uhdmtopModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamOverloading/dut.sv, line:24:1, endln:41:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamOverloading/dut.sv, line:24:1, endln:41:10 |vpiName:work@top |vpiParameter: \_parameter: (work@top.v1), line:29:14, endln:29:16 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamOverloading/dut.sv, line:24:1, endln:41:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamOverloading/dut.sv, line:24:1, endln:41:10 |UINT:1 |vpiTypespec: \_int_typespec: @@ -718,7 +718,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.v2), line:30:14, endln:30:16 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamOverloading/dut.sv, line:24:1, endln:41:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamOverloading/dut.sv, line:24:1, endln:41:10 |UINT:0 |vpiTypespec: \_int_typespec: @@ -729,14 +729,14 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.CTRL_RESET), line:32:24, endln:32:34 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamOverloading/dut.sv, line:24:1, endln:41:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamOverloading/dut.sv, line:24:1, endln:41:10 |vpiTypespec: \_struct_typespec: (struct_ab), line:25:12, endln:25:18 |vpiParent: \_parameter: (work@top.CTRL_RESET), line:32:24, endln:32:34 |vpiName:struct_ab |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamOverloading/dut.sv, line:24:1, endln:41:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamOverloading/dut.sv, line:24:1, endln:41:10 |vpiPacked:1 |vpiTypespecMember: \_typespec_member: (a), line:26:19, endln:26:20 @@ -811,7 +811,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:29:14, endln:29:20 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamOverloading/dut.sv, line:24:1, endln:41:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamOverloading/dut.sv, line:24:1, endln:41:10 |vpiRhs: \_constant: , line:29:19, endln:29:20 |vpiDecompile:1 @@ -825,7 +825,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:30:14, endln:30:20 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamOverloading/dut.sv, line:24:1, endln:41:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamOverloading/dut.sv, line:24:1, endln:41:10 |vpiRhs: \_constant: , line:30:19, endln:30:20 |vpiDecompile:0 @@ -839,7 +839,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:32:24, endln:36:5 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamOverloading/dut.sv, line:24:1, endln:41:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamOverloading/dut.sv, line:24:1, endln:41:10 |vpiRhs: \_operation: , line:32:37, endln:36:5 |vpiParent: @@ -942,23 +942,23 @@ design: (work@top) |vpiDefName:work@top |vpiTop:1 |vpiTopModule:1 - |vpiModule: - \_module: work@prim_subreg_shadow (work@top.u_ctrl_reg_shadowed), file:${SURELOG_DIR}/tests/ParamOverloading/dut.sv, line:38:4, endln:40:28 + |vpiModuleInst: + \_module_inst: work@prim_subreg_shadow (work@top.u_ctrl_reg_shadowed), file:${SURELOG_DIR}/tests/ParamOverloading/dut.sv, line:38:4, endln:40:28 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamOverloading/dut.sv, line:24:1, endln:41:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamOverloading/dut.sv, line:24:1, endln:41:10 |vpiName:u_ctrl_reg_shadowed |vpiFullName:work@top.u_ctrl_reg_shadowed |vpiParameter: \_parameter: (work@top.u_ctrl_reg_shadowed.RESVAL), line:13:24, endln:13:30 |vpiParent: - \_module: work@prim_subreg_shadow (work@top.u_ctrl_reg_shadowed), file:${SURELOG_DIR}/tests/ParamOverloading/dut.sv, line:38:4, endln:40:28 + \_module_inst: work@prim_subreg_shadow (work@top.u_ctrl_reg_shadowed), file:${SURELOG_DIR}/tests/ParamOverloading/dut.sv, line:38:4, endln:40:28 |vpiTypespec: \_struct_typespec: (struct_ab), line:8:12, endln:8:18 |vpiParent: \_parameter: (work@top.u_ctrl_reg_shadowed.RESVAL), line:13:24, endln:13:30 |vpiName:struct_ab |vpiInstance: - \_module: work@prim_subreg_shadow (work@prim_subreg_shadow), file:${SURELOG_DIR}/tests/ParamOverloading/dut.sv, line:7:1, endln:22:10 + \_module_inst: work@prim_subreg_shadow (work@prim_subreg_shadow), file:${SURELOG_DIR}/tests/ParamOverloading/dut.sv, line:7:1, endln:22:10 |vpiPacked:1 |vpiTypespecMember: \_typespec_member: (a), line:9:19, endln:9:20 @@ -1033,7 +1033,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:13:24, endln:16:5 |vpiParent: - \_module: work@prim_subreg_shadow (work@top.u_ctrl_reg_shadowed), file:${SURELOG_DIR}/tests/ParamOverloading/dut.sv, line:38:4, endln:40:28 + \_module_inst: work@prim_subreg_shadow (work@top.u_ctrl_reg_shadowed), file:${SURELOG_DIR}/tests/ParamOverloading/dut.sv, line:38:4, endln:40:28 |vpiOverriden:1 |vpiRhs: \_operation: , line:39:15, endln:39:25 @@ -1138,17 +1138,17 @@ design: (work@top) |vpiDefFile:${SURELOG_DIR}/tests/ParamOverloading/dut.sv |vpiDefLineNo:7 |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamOverloading/dut.sv, line:24:1, endln:41:10 - |vpiModule: - \_module: work@prim_subreg (work@top.u_ctrl_reg_shadowed.staged_reg), file:${SURELOG_DIR}/tests/ParamOverloading/dut.sv, line:18:4, endln:20:19 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamOverloading/dut.sv, line:24:1, endln:41:10 + |vpiModuleInst: + \_module_inst: work@prim_subreg (work@top.u_ctrl_reg_shadowed.staged_reg), file:${SURELOG_DIR}/tests/ParamOverloading/dut.sv, line:18:4, endln:20:19 |vpiParent: - \_module: work@prim_subreg_shadow (work@top.u_ctrl_reg_shadowed), file:${SURELOG_DIR}/tests/ParamOverloading/dut.sv, line:38:4, endln:40:28 + \_module_inst: work@prim_subreg_shadow (work@top.u_ctrl_reg_shadowed), file:${SURELOG_DIR}/tests/ParamOverloading/dut.sv, line:38:4, endln:40:28 |vpiName:staged_reg |vpiFullName:work@top.u_ctrl_reg_shadowed.staged_reg |vpiVariables: \_int_var: (work@top.u_ctrl_reg_shadowed.staged_reg.a), line:4:8, endln:4:24 |vpiParent: - \_module: work@prim_subreg (work@top.u_ctrl_reg_shadowed.staged_reg), file:${SURELOG_DIR}/tests/ParamOverloading/dut.sv, line:18:4, endln:20:19 + \_module_inst: work@prim_subreg (work@top.u_ctrl_reg_shadowed.staged_reg), file:${SURELOG_DIR}/tests/ParamOverloading/dut.sv, line:18:4, endln:20:19 |vpiTypespec: \_int_typespec: , line:4:4, endln:4:7 |vpiSigned:1 @@ -1195,7 +1195,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.u_ctrl_reg_shadowed.staged_reg.RESVAL), line:3:26, endln:3:32 |vpiParent: - \_module: work@prim_subreg (work@top.u_ctrl_reg_shadowed.staged_reg), file:${SURELOG_DIR}/tests/ParamOverloading/dut.sv, line:18:4, endln:20:19 + \_module_inst: work@prim_subreg (work@top.u_ctrl_reg_shadowed.staged_reg), file:${SURELOG_DIR}/tests/ParamOverloading/dut.sv, line:18:4, endln:20:19 |BIN:0 |vpiTypespec: \_logic_typespec: , line:3:14, endln:3:25 @@ -1226,7 +1226,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:3:26, endln:3:37 |vpiParent: - \_module: work@prim_subreg (work@top.u_ctrl_reg_shadowed.staged_reg), file:${SURELOG_DIR}/tests/ParamOverloading/dut.sv, line:18:4, endln:20:19 + \_module_inst: work@prim_subreg (work@top.u_ctrl_reg_shadowed.staged_reg), file:${SURELOG_DIR}/tests/ParamOverloading/dut.sv, line:18:4, endln:20:19 |vpiOverriden:1 |vpiRhs: \_constant: , line:19:15, endln:19:21 @@ -1239,7 +1239,7 @@ design: (work@top) |vpiDefFile:${SURELOG_DIR}/tests/ParamOverloading/dut.sv |vpiDefLineNo:2 |vpiInstance: - \_module: work@prim_subreg_shadow (work@top.u_ctrl_reg_shadowed), file:${SURELOG_DIR}/tests/ParamOverloading/dut.sv, line:38:4, endln:40:28 + \_module_inst: work@prim_subreg_shadow (work@top.u_ctrl_reg_shadowed), file:${SURELOG_DIR}/tests/ParamOverloading/dut.sv, line:38:4, endln:40:28 =================== [ FATAL] : 0 [ SYNTAX] : 0 diff --git a/tests/ParamRef/ParamRef.log b/tests/ParamRef/ParamRef.log index b5b8aa5564..eba468a9a8 100644 --- a/tests/ParamRef/ParamRef.log +++ b/tests/ParamRef/ParamRef.log @@ -231,7 +231,7 @@ design 1 import_typespec 1 int_typespec 16 logic_typespec 5 -module 16 +module_inst 16 operation 9 package 6 param_assign 18 @@ -247,7 +247,7 @@ design 1 import_typespec 1 int_typespec 16 logic_typespec 5 -module 16 +module_inst 16 operation 9 package 6 param_assign 18 @@ -528,14 +528,14 @@ design: (work@top_earlgrey) |vpiDefName:dm |vpiTop:1 |uhdmallModules: -\_module: work@ibex_core (work@ibex_core), file:${SURELOG_DIR}/tests/ParamRef/dut.sv, line:25:1, endln:27:10 +\_module_inst: work@ibex_core (work@ibex_core), file:${SURELOG_DIR}/tests/ParamRef/dut.sv, line:25:1, endln:27:10 |vpiParent: \_design: (work@top_earlgrey) |vpiFullName:work@ibex_core |vpiParameter: \_parameter: (work@ibex_core.DmExceptionAddr), line:26:27, endln:26:42 |vpiParent: - \_module: work@ibex_core (work@ibex_core), file:${SURELOG_DIR}/tests/ParamRef/dut.sv, line:25:1, endln:27:10 + \_module_inst: work@ibex_core (work@ibex_core), file:${SURELOG_DIR}/tests/ParamRef/dut.sv, line:25:1, endln:27:10 |UINT:4 |vpiTypespec: \_int_typespec: , line:26:14, endln:26:26 @@ -546,7 +546,7 @@ design: (work@top_earlgrey) |vpiParamAssign: \_param_assign: , line:26:27, endln:26:46 |vpiParent: - \_module: work@ibex_core (work@ibex_core), file:${SURELOG_DIR}/tests/ParamRef/dut.sv, line:25:1, endln:27:10 + \_module_inst: work@ibex_core (work@ibex_core), file:${SURELOG_DIR}/tests/ParamRef/dut.sv, line:25:1, endln:27:10 |vpiRhs: \_constant: , line:26:45, endln:26:46 |vpiDecompile:4 @@ -559,14 +559,14 @@ design: (work@top_earlgrey) \_parameter: (work@ibex_core.DmExceptionAddr), line:26:27, endln:26:42 |vpiDefName:work@ibex_core |uhdmallModules: -\_module: work@rv_core_ibex (work@rv_core_ibex), file:${SURELOG_DIR}/tests/ParamRef/dut.sv, line:18:1, endln:23:10 +\_module_inst: work@rv_core_ibex (work@rv_core_ibex), file:${SURELOG_DIR}/tests/ParamRef/dut.sv, line:18:1, endln:23:10 |vpiParent: \_design: (work@top_earlgrey) |vpiFullName:work@rv_core_ibex |vpiParameter: \_parameter: (work@rv_core_ibex.DmExceptionAddr), line:19:27, endln:19:42 |vpiParent: - \_module: work@rv_core_ibex (work@rv_core_ibex), file:${SURELOG_DIR}/tests/ParamRef/dut.sv, line:18:1, endln:23:10 + \_module_inst: work@rv_core_ibex (work@rv_core_ibex), file:${SURELOG_DIR}/tests/ParamRef/dut.sv, line:18:1, endln:23:10 |UINT:3 |vpiTypespec: \_int_typespec: , line:19:14, endln:19:26 @@ -577,7 +577,7 @@ design: (work@top_earlgrey) |vpiParamAssign: \_param_assign: , line:19:27, endln:19:46 |vpiParent: - \_module: work@rv_core_ibex (work@rv_core_ibex), file:${SURELOG_DIR}/tests/ParamRef/dut.sv, line:18:1, endln:23:10 + \_module_inst: work@rv_core_ibex (work@rv_core_ibex), file:${SURELOG_DIR}/tests/ParamRef/dut.sv, line:18:1, endln:23:10 |vpiRhs: \_constant: , line:19:45, endln:19:46 |vpiDecompile:3 @@ -590,14 +590,14 @@ design: (work@top_earlgrey) \_parameter: (work@rv_core_ibex.DmExceptionAddr), line:19:27, endln:19:42 |vpiDefName:work@rv_core_ibex |uhdmallModules: -\_module: work@top_earlgrey (work@top_earlgrey), file:${SURELOG_DIR}/tests/ParamRef/dut.sv, line:10:1, endln:16:10 +\_module_inst: work@top_earlgrey (work@top_earlgrey), file:${SURELOG_DIR}/tests/ParamRef/dut.sv, line:10:1, endln:16:10 |vpiParent: \_design: (work@top_earlgrey) |vpiFullName:work@top_earlgrey |vpiParameter: \_parameter: (work@top_earlgrey.ADDR_SPACE_DEBUG_MEM), line:2:19, endln:2:39 |vpiParent: - \_module: work@top_earlgrey (work@top_earlgrey), file:${SURELOG_DIR}/tests/ParamRef/dut.sv, line:10:1, endln:16:10 + \_module_inst: work@top_earlgrey (work@top_earlgrey), file:${SURELOG_DIR}/tests/ParamRef/dut.sv, line:10:1, endln:16:10 |UINT:1 |vpiTypespec: \_int_typespec: , line:2:15, endln:2:18 @@ -614,7 +614,7 @@ design: (work@top_earlgrey) |vpiParamAssign: \_param_assign: , line:2:19, endln:2:43 |vpiParent: - \_module: work@top_earlgrey (work@top_earlgrey), file:${SURELOG_DIR}/tests/ParamRef/dut.sv, line:10:1, endln:16:10 + \_module_inst: work@top_earlgrey (work@top_earlgrey), file:${SURELOG_DIR}/tests/ParamRef/dut.sv, line:10:1, endln:16:10 |vpiRhs: \_constant: , line:2:42, endln:2:43 |vpiParent: @@ -651,12 +651,12 @@ design: (work@top_earlgrey) \_import_typespec: (tl_main_pkg), line:11:10, endln:11:24 |vpiDefName:work@top_earlgrey |uhdmtopModules: -\_module: work@top_earlgrey (work@top_earlgrey), file:${SURELOG_DIR}/tests/ParamRef/dut.sv, line:10:1, endln:16:10 +\_module_inst: work@top_earlgrey (work@top_earlgrey), file:${SURELOG_DIR}/tests/ParamRef/dut.sv, line:10:1, endln:16:10 |vpiName:work@top_earlgrey |vpiParameter: \_parameter: (work@top_earlgrey.ADDR_SPACE_DEBUG_MEM), line:2:19, endln:2:39 |vpiParent: - \_module: work@top_earlgrey (work@top_earlgrey), file:${SURELOG_DIR}/tests/ParamRef/dut.sv, line:10:1, endln:16:10 + \_module_inst: work@top_earlgrey (work@top_earlgrey), file:${SURELOG_DIR}/tests/ParamRef/dut.sv, line:10:1, endln:16:10 |UINT:1 |vpiTypespec: \_int_typespec: , line:2:15, endln:2:18 @@ -673,7 +673,7 @@ design: (work@top_earlgrey) |vpiParamAssign: \_param_assign: , line:2:19, endln:2:43 |vpiParent: - \_module: work@top_earlgrey (work@top_earlgrey), file:${SURELOG_DIR}/tests/ParamRef/dut.sv, line:10:1, endln:16:10 + \_module_inst: work@top_earlgrey (work@top_earlgrey), file:${SURELOG_DIR}/tests/ParamRef/dut.sv, line:10:1, endln:16:10 |vpiRhs: \_constant: , line:2:42, endln:2:43 |vpiDecompile:1 @@ -689,16 +689,16 @@ design: (work@top_earlgrey) |vpiDefName:work@top_earlgrey |vpiTop:1 |vpiTopModule:1 - |vpiModule: - \_module: work@rv_core_ibex (work@top_earlgrey.u_rv_core_ibex), file:${SURELOG_DIR}/tests/ParamRef/dut.sv, line:13:3, endln:15:22 + |vpiModuleInst: + \_module_inst: work@rv_core_ibex (work@top_earlgrey.u_rv_core_ibex), file:${SURELOG_DIR}/tests/ParamRef/dut.sv, line:13:3, endln:15:22 |vpiParent: - \_module: work@top_earlgrey (work@top_earlgrey), file:${SURELOG_DIR}/tests/ParamRef/dut.sv, line:10:1, endln:16:10 + \_module_inst: work@top_earlgrey (work@top_earlgrey), file:${SURELOG_DIR}/tests/ParamRef/dut.sv, line:10:1, endln:16:10 |vpiName:u_rv_core_ibex |vpiFullName:work@top_earlgrey.u_rv_core_ibex |vpiParameter: \_parameter: (work@top_earlgrey.u_rv_core_ibex.DmExceptionAddr), line:19:27, endln:19:42 |vpiParent: - \_module: work@rv_core_ibex (work@top_earlgrey.u_rv_core_ibex), file:${SURELOG_DIR}/tests/ParamRef/dut.sv, line:13:3, endln:15:22 + \_module_inst: work@rv_core_ibex (work@top_earlgrey.u_rv_core_ibex), file:${SURELOG_DIR}/tests/ParamRef/dut.sv, line:13:3, endln:15:22 |UINT:3 |vpiTypespec: \_int_typespec: , line:19:14, endln:19:26 @@ -709,7 +709,7 @@ design: (work@top_earlgrey) |vpiParamAssign: \_param_assign: , line:19:27, endln:19:46 |vpiParent: - \_module: work@rv_core_ibex (work@top_earlgrey.u_rv_core_ibex), file:${SURELOG_DIR}/tests/ParamRef/dut.sv, line:13:3, endln:15:22 + \_module_inst: work@rv_core_ibex (work@top_earlgrey.u_rv_core_ibex), file:${SURELOG_DIR}/tests/ParamRef/dut.sv, line:13:3, endln:15:22 |vpiOverriden:1 |vpiRhs: \_operation: , line:14:23, endln:14:66 @@ -748,17 +748,17 @@ design: (work@top_earlgrey) |vpiDefFile:${SURELOG_DIR}/tests/ParamRef/dut.sv |vpiDefLineNo:18 |vpiInstance: - \_module: work@top_earlgrey (work@top_earlgrey), file:${SURELOG_DIR}/tests/ParamRef/dut.sv, line:10:1, endln:16:10 - |vpiModule: - \_module: work@ibex_core (work@top_earlgrey.u_rv_core_ibex.u_core), file:${SURELOG_DIR}/tests/ParamRef/dut.sv, line:20:4, endln:22:14 + \_module_inst: work@top_earlgrey (work@top_earlgrey), file:${SURELOG_DIR}/tests/ParamRef/dut.sv, line:10:1, endln:16:10 + |vpiModuleInst: + \_module_inst: work@ibex_core (work@top_earlgrey.u_rv_core_ibex.u_core), file:${SURELOG_DIR}/tests/ParamRef/dut.sv, line:20:4, endln:22:14 |vpiParent: - \_module: work@rv_core_ibex (work@top_earlgrey.u_rv_core_ibex), file:${SURELOG_DIR}/tests/ParamRef/dut.sv, line:13:3, endln:15:22 + \_module_inst: work@rv_core_ibex (work@top_earlgrey.u_rv_core_ibex), file:${SURELOG_DIR}/tests/ParamRef/dut.sv, line:13:3, endln:15:22 |vpiName:u_core |vpiFullName:work@top_earlgrey.u_rv_core_ibex.u_core |vpiParameter: \_parameter: (work@top_earlgrey.u_rv_core_ibex.u_core.DmExceptionAddr), line:26:27, endln:26:42 |vpiParent: - \_module: work@ibex_core (work@top_earlgrey.u_rv_core_ibex.u_core), file:${SURELOG_DIR}/tests/ParamRef/dut.sv, line:20:4, endln:22:14 + \_module_inst: work@ibex_core (work@top_earlgrey.u_rv_core_ibex.u_core), file:${SURELOG_DIR}/tests/ParamRef/dut.sv, line:20:4, endln:22:14 |UINT:4 |vpiTypespec: \_int_typespec: , line:26:14, endln:26:26 @@ -769,7 +769,7 @@ design: (work@top_earlgrey) |vpiParamAssign: \_param_assign: , line:26:27, endln:26:46 |vpiParent: - \_module: work@ibex_core (work@top_earlgrey.u_rv_core_ibex.u_core), file:${SURELOG_DIR}/tests/ParamRef/dut.sv, line:20:4, endln:22:14 + \_module_inst: work@ibex_core (work@top_earlgrey.u_rv_core_ibex.u_core), file:${SURELOG_DIR}/tests/ParamRef/dut.sv, line:20:4, endln:22:14 |vpiOverriden:1 |vpiRhs: \_operation: , line:21:24, endln:21:39 @@ -834,7 +834,7 @@ design: (work@top_earlgrey) |vpiDefFile:${SURELOG_DIR}/tests/ParamRef/dut.sv |vpiDefLineNo:25 |vpiInstance: - \_module: work@rv_core_ibex (work@top_earlgrey.u_rv_core_ibex), file:${SURELOG_DIR}/tests/ParamRef/dut.sv, line:13:3, endln:15:22 + \_module_inst: work@rv_core_ibex (work@top_earlgrey.u_rv_core_ibex), file:${SURELOG_DIR}/tests/ParamRef/dut.sv, line:13:3, endln:15:22 =================== [ FATAL] : 0 [ SYNTAX] : 0 diff --git a/tests/ParamScope/ParamScope.log b/tests/ParamScope/ParamScope.log index 6ef0852c51..ec6be645b6 100644 --- a/tests/ParamScope/ParamScope.log +++ b/tests/ParamScope/ParamScope.log @@ -234,7 +234,7 @@ constant 21 design 1 import_typespec 1 int_typespec 18 -module 18 +module_inst 18 operation 13 package 3 param_assign 14 @@ -250,7 +250,7 @@ constant 21 design 1 import_typespec 1 int_typespec 18 -module 18 +module_inst 18 operation 13 package 3 param_assign 14 @@ -355,14 +355,14 @@ design: (work@top) |vpiDefName:foo_pkg |vpiTop:1 |uhdmallModules: -\_module: work@bottom (work@bottom), file:${SURELOG_DIR}/tests/ParamScope/dut.sv, line:5:1, endln:7:10 +\_module_inst: work@bottom (work@bottom), file:${SURELOG_DIR}/tests/ParamScope/dut.sv, line:5:1, endln:7:10 |vpiParent: \_design: (work@top) |vpiFullName:work@bottom |vpiParameter: \_parameter: (work@bottom.VALUE), line:6:17, endln:6:22 |vpiParent: - \_module: work@bottom (work@bottom), file:${SURELOG_DIR}/tests/ParamScope/dut.sv, line:5:1, endln:7:10 + \_module_inst: work@bottom (work@bottom), file:${SURELOG_DIR}/tests/ParamScope/dut.sv, line:5:1, endln:7:10 |UINT:8 |vpiTypespec: \_int_typespec: , line:6:13, endln:6:16 @@ -375,7 +375,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:6:17, endln:6:26 |vpiParent: - \_module: work@bottom (work@bottom), file:${SURELOG_DIR}/tests/ParamScope/dut.sv, line:5:1, endln:7:10 + \_module_inst: work@bottom (work@bottom), file:${SURELOG_DIR}/tests/ParamScope/dut.sv, line:5:1, endln:7:10 |vpiRhs: \_constant: , line:6:25, endln:6:26 |vpiDecompile:8 @@ -388,14 +388,14 @@ design: (work@top) \_parameter: (work@bottom.VALUE), line:6:17, endln:6:22 |vpiDefName:work@bottom |uhdmallModules: -\_module: work@lower (work@lower), file:${SURELOG_DIR}/tests/ParamScope/dut.sv, line:9:1, endln:15:10 +\_module_inst: work@lower (work@lower), file:${SURELOG_DIR}/tests/ParamScope/dut.sv, line:9:1, endln:15:10 |vpiParent: \_design: (work@top) |vpiFullName:work@lower |vpiParameter: \_parameter: (work@lower.VALUE_TEMP), line:2:17, endln:2:27 |vpiParent: - \_module: work@lower (work@lower), file:${SURELOG_DIR}/tests/ParamScope/dut.sv, line:9:1, endln:15:10 + \_module_inst: work@lower (work@lower), file:${SURELOG_DIR}/tests/ParamScope/dut.sv, line:9:1, endln:15:10 |vpiTypespec: \_int_typespec: , line:2:13, endln:2:16 |vpiParent: @@ -410,7 +410,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@lower.VALUE), line:11:17, endln:11:22 |vpiParent: - \_module: work@lower (work@lower), file:${SURELOG_DIR}/tests/ParamScope/dut.sv, line:9:1, endln:15:10 + \_module_inst: work@lower (work@lower), file:${SURELOG_DIR}/tests/ParamScope/dut.sv, line:9:1, endln:15:10 |vpiTypespec: \_int_typespec: , line:11:13, endln:11:16 |vpiParent: @@ -422,7 +422,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:2:17, endln:2:43 |vpiParent: - \_module: work@lower (work@lower), file:${SURELOG_DIR}/tests/ParamScope/dut.sv, line:9:1, endln:15:10 + \_module_inst: work@lower (work@lower), file:${SURELOG_DIR}/tests/ParamScope/dut.sv, line:9:1, endln:15:10 |vpiRhs: \_operation: , line:2:30, endln:2:43 |vpiParent: @@ -463,7 +463,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:11:17, endln:11:39 |vpiParent: - \_module: work@lower (work@lower), file:${SURELOG_DIR}/tests/ParamScope/dut.sv, line:9:1, endln:15:10 + \_module_inst: work@lower (work@lower), file:${SURELOG_DIR}/tests/ParamScope/dut.sv, line:9:1, endln:15:10 |vpiRhs: \_operation: , line:11:25, endln:11:39 |vpiOpType:24 @@ -486,14 +486,14 @@ design: (work@top) \_import_typespec: (foo_pkg), line:10:10, endln:10:20 |vpiDefName:work@lower |uhdmallModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamScope/dut.sv, line:22:1, endln:25:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamScope/dut.sv, line:22:1, endln:25:10 |vpiParent: \_design: (work@top) |vpiFullName:work@top |vpiParameter: \_parameter: (work@top.VALUE), line:23:17, endln:23:22 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamScope/dut.sv, line:22:1, endln:25:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamScope/dut.sv, line:22:1, endln:25:10 |UINT:5 |vpiTypespec: \_int_typespec: , line:23:13, endln:23:16 @@ -506,7 +506,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:23:17, endln:23:26 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamScope/dut.sv, line:22:1, endln:25:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamScope/dut.sv, line:22:1, endln:25:10 |vpiRhs: \_constant: , line:23:25, endln:23:26 |vpiDecompile:5 @@ -519,14 +519,14 @@ design: (work@top) \_parameter: (work@top.VALUE), line:23:17, endln:23:22 |vpiDefName:work@top |uhdmallModules: -\_module: work@upper (work@upper), file:${SURELOG_DIR}/tests/ParamScope/dut.sv, line:17:1, endln:20:10 +\_module_inst: work@upper (work@upper), file:${SURELOG_DIR}/tests/ParamScope/dut.sv, line:17:1, endln:20:10 |vpiParent: \_design: (work@top) |vpiFullName:work@upper |vpiParameter: \_parameter: (work@upper.VALUE), line:18:17, endln:18:22 |vpiParent: - \_module: work@upper (work@upper), file:${SURELOG_DIR}/tests/ParamScope/dut.sv, line:17:1, endln:20:10 + \_module_inst: work@upper (work@upper), file:${SURELOG_DIR}/tests/ParamScope/dut.sv, line:17:1, endln:20:10 |UINT:7 |vpiTypespec: \_int_typespec: , line:18:13, endln:18:16 @@ -539,7 +539,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:18:17, endln:18:26 |vpiParent: - \_module: work@upper (work@upper), file:${SURELOG_DIR}/tests/ParamScope/dut.sv, line:17:1, endln:20:10 + \_module_inst: work@upper (work@upper), file:${SURELOG_DIR}/tests/ParamScope/dut.sv, line:17:1, endln:20:10 |vpiRhs: \_constant: , line:18:25, endln:18:26 |vpiDecompile:7 @@ -552,12 +552,12 @@ design: (work@top) \_parameter: (work@upper.VALUE), line:18:17, endln:18:22 |vpiDefName:work@upper |uhdmtopModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamScope/dut.sv, line:22:1, endln:25:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamScope/dut.sv, line:22:1, endln:25:10 |vpiName:work@top |vpiParameter: \_parameter: (work@top.VALUE), line:23:17, endln:23:22 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamScope/dut.sv, line:22:1, endln:25:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamScope/dut.sv, line:22:1, endln:25:10 |UINT:5 |vpiTypespec: \_int_typespec: , line:23:13, endln:23:16 @@ -570,7 +570,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:23:17, endln:23:26 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamScope/dut.sv, line:22:1, endln:25:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamScope/dut.sv, line:22:1, endln:25:10 |vpiRhs: \_constant: , line:23:25, endln:23:26 |vpiDecompile:5 @@ -584,16 +584,16 @@ design: (work@top) |vpiDefName:work@top |vpiTop:1 |vpiTopModule:1 - |vpiModule: - \_module: work@upper (work@top.upper_u), file:${SURELOG_DIR}/tests/ParamScope/dut.sv, line:24:3, endln:24:20 + |vpiModuleInst: + \_module_inst: work@upper (work@top.upper_u), file:${SURELOG_DIR}/tests/ParamScope/dut.sv, line:24:3, endln:24:20 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamScope/dut.sv, line:22:1, endln:25:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamScope/dut.sv, line:22:1, endln:25:10 |vpiName:upper_u |vpiFullName:work@top.upper_u |vpiParameter: \_parameter: (work@top.upper_u.VALUE), line:18:17, endln:18:22 |vpiParent: - \_module: work@upper (work@top.upper_u), file:${SURELOG_DIR}/tests/ParamScope/dut.sv, line:24:3, endln:24:20 + \_module_inst: work@upper (work@top.upper_u), file:${SURELOG_DIR}/tests/ParamScope/dut.sv, line:24:3, endln:24:20 |UINT:7 |vpiTypespec: \_int_typespec: , line:18:13, endln:18:16 @@ -606,7 +606,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:18:17, endln:18:26 |vpiParent: - \_module: work@upper (work@top.upper_u), file:${SURELOG_DIR}/tests/ParamScope/dut.sv, line:24:3, endln:24:20 + \_module_inst: work@upper (work@top.upper_u), file:${SURELOG_DIR}/tests/ParamScope/dut.sv, line:24:3, endln:24:20 |vpiRhs: \_constant: , line:18:25, endln:18:26 |vpiDecompile:7 @@ -621,17 +621,17 @@ design: (work@top) |vpiDefFile:${SURELOG_DIR}/tests/ParamScope/dut.sv |vpiDefLineNo:17 |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamScope/dut.sv, line:22:1, endln:25:10 - |vpiModule: - \_module: work@lower (work@top.upper_u.lower_u), file:${SURELOG_DIR}/tests/ParamScope/dut.sv, line:19:3, endln:19:20 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamScope/dut.sv, line:22:1, endln:25:10 + |vpiModuleInst: + \_module_inst: work@lower (work@top.upper_u.lower_u), file:${SURELOG_DIR}/tests/ParamScope/dut.sv, line:19:3, endln:19:20 |vpiParent: - \_module: work@upper (work@top.upper_u), file:${SURELOG_DIR}/tests/ParamScope/dut.sv, line:24:3, endln:24:20 + \_module_inst: work@upper (work@top.upper_u), file:${SURELOG_DIR}/tests/ParamScope/dut.sv, line:24:3, endln:24:20 |vpiName:lower_u |vpiFullName:work@top.upper_u.lower_u |vpiParameter: \_parameter: (work@top.upper_u.lower_u.VALUE_TEMP), line:2:17, endln:2:27 |vpiParent: - \_module: work@lower (work@top.upper_u.lower_u), file:${SURELOG_DIR}/tests/ParamScope/dut.sv, line:19:3, endln:19:20 + \_module_inst: work@lower (work@top.upper_u.lower_u), file:${SURELOG_DIR}/tests/ParamScope/dut.sv, line:19:3, endln:19:20 |vpiTypespec: \_int_typespec: , line:2:13, endln:2:16 |vpiParent: @@ -646,7 +646,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.upper_u.lower_u.VALUE), line:11:17, endln:11:22 |vpiParent: - \_module: work@lower (work@top.upper_u.lower_u), file:${SURELOG_DIR}/tests/ParamScope/dut.sv, line:19:3, endln:19:20 + \_module_inst: work@lower (work@top.upper_u.lower_u), file:${SURELOG_DIR}/tests/ParamScope/dut.sv, line:19:3, endln:19:20 |vpiTypespec: \_int_typespec: , line:11:13, endln:11:16 |vpiParent: @@ -658,7 +658,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:2:17, endln:2:43 |vpiParent: - \_module: work@lower (work@top.upper_u.lower_u), file:${SURELOG_DIR}/tests/ParamScope/dut.sv, line:19:3, endln:19:20 + \_module_inst: work@lower (work@top.upper_u.lower_u), file:${SURELOG_DIR}/tests/ParamScope/dut.sv, line:19:3, endln:19:20 |vpiRhs: \_operation: , line:2:30, endln:2:43 |vpiParent: @@ -686,7 +686,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:11:17, endln:11:39 |vpiParent: - \_module: work@lower (work@top.upper_u.lower_u), file:${SURELOG_DIR}/tests/ParamScope/dut.sv, line:19:3, endln:19:20 + \_module_inst: work@lower (work@top.upper_u.lower_u), file:${SURELOG_DIR}/tests/ParamScope/dut.sv, line:19:3, endln:19:20 |vpiRhs: \_operation: , line:11:25, endln:11:39 |vpiTypespec: @@ -732,17 +732,17 @@ design: (work@top) |vpiDefFile:${SURELOG_DIR}/tests/ParamScope/dut.sv |vpiDefLineNo:9 |vpiInstance: - \_module: work@upper (work@top.upper_u), file:${SURELOG_DIR}/tests/ParamScope/dut.sv, line:24:3, endln:24:20 - |vpiModule: - \_module: work@bottom (work@top.upper_u.lower_u.bottom_u), file:${SURELOG_DIR}/tests/ParamScope/dut.sv, line:12:3, endln:14:16 + \_module_inst: work@upper (work@top.upper_u), file:${SURELOG_DIR}/tests/ParamScope/dut.sv, line:24:3, endln:24:20 + |vpiModuleInst: + \_module_inst: work@bottom (work@top.upper_u.lower_u.bottom_u), file:${SURELOG_DIR}/tests/ParamScope/dut.sv, line:12:3, endln:14:16 |vpiParent: - \_module: work@lower (work@top.upper_u.lower_u), file:${SURELOG_DIR}/tests/ParamScope/dut.sv, line:19:3, endln:19:20 + \_module_inst: work@lower (work@top.upper_u.lower_u), file:${SURELOG_DIR}/tests/ParamScope/dut.sv, line:19:3, endln:19:20 |vpiName:bottom_u |vpiFullName:work@top.upper_u.lower_u.bottom_u |vpiParameter: \_parameter: (work@top.upper_u.lower_u.bottom_u.VALUE), line:6:17, endln:6:22 |vpiParent: - \_module: work@bottom (work@top.upper_u.lower_u.bottom_u), file:${SURELOG_DIR}/tests/ParamScope/dut.sv, line:12:3, endln:14:16 + \_module_inst: work@bottom (work@top.upper_u.lower_u.bottom_u), file:${SURELOG_DIR}/tests/ParamScope/dut.sv, line:12:3, endln:14:16 |UINT:8 |vpiTypespec: \_int_typespec: , line:6:13, endln:6:16 @@ -755,7 +755,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:6:17, endln:6:26 |vpiParent: - \_module: work@bottom (work@top.upper_u.lower_u.bottom_u), file:${SURELOG_DIR}/tests/ParamScope/dut.sv, line:12:3, endln:14:16 + \_module_inst: work@bottom (work@top.upper_u.lower_u.bottom_u), file:${SURELOG_DIR}/tests/ParamScope/dut.sv, line:12:3, endln:14:16 |vpiOverriden:1 |vpiRhs: \_operation: , line:13:12, endln:13:17 @@ -808,7 +808,7 @@ design: (work@top) |vpiDefFile:${SURELOG_DIR}/tests/ParamScope/dut.sv |vpiDefLineNo:5 |vpiInstance: - \_module: work@lower (work@top.upper_u.lower_u), file:${SURELOG_DIR}/tests/ParamScope/dut.sv, line:19:3, endln:19:20 + \_module_inst: work@lower (work@top.upper_u.lower_u), file:${SURELOG_DIR}/tests/ParamScope/dut.sv, line:19:3, endln:19:20 =================== [ FATAL] : 0 [ SYNTAX] : 0 diff --git a/tests/ParamSubstituteComplex/ParamSubstituteComplex.log b/tests/ParamSubstituteComplex/ParamSubstituteComplex.log index 2d24de6615..ee85b7a47a 100644 --- a/tests/ParamSubstituteComplex/ParamSubstituteComplex.log +++ b/tests/ParamSubstituteComplex/ParamSubstituteComplex.log @@ -567,7 +567,7 @@ gen_scope_array 4 hier_path 2 int_typespec 29 logic_typespec 81 -module 8 +module_inst 8 operation 39 packed_array_typespec 1 param_assign 26 @@ -591,7 +591,7 @@ gen_scope_array 6 hier_path 2 int_typespec 29 logic_typespec 81 -module 10 +module_inst 10 operation 39 packed_array_typespec 1 param_assign 26 @@ -616,27 +616,27 @@ design: (work@top) |vpiElaborated:1 |vpiName:work@top |uhdmallModules: -\_module: work@GOOD (work@GOOD), file:${SURELOG_DIR}/tests/ParamSubstituteComplex/dut.sv, line:1:1, endln:2:10 +\_module_inst: work@GOOD (work@GOOD), file:${SURELOG_DIR}/tests/ParamSubstituteComplex/dut.sv, line:1:1, endln:2:10 |vpiParent: \_design: (work@top) |vpiFullName:work@GOOD |vpiDefName:work@GOOD |uhdmallModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamSubstituteComplex/dut.sv, line:4:1, endln:53:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamSubstituteComplex/dut.sv, line:4:1, endln:53:10 |vpiParent: \_design: (work@top) |vpiFullName:work@top |vpiParameter: \_parameter: (work@top.RV64D_Xsflt), line:16:27, endln:16:38 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamSubstituteComplex/dut.sv, line:4:1, endln:53:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamSubstituteComplex/dut.sv, line:4:1, endln:53:10 |vpiTypespec: \_struct_typespec: (fpu_features_t), line:8:9, endln:8:15 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamSubstituteComplex/dut.sv, line:4:1, endln:53:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamSubstituteComplex/dut.sv, line:4:1, endln:53:10 |vpiName:fpu_features_t |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamSubstituteComplex/dut.sv, line:4:1, endln:53:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamSubstituteComplex/dut.sv, line:4:1, endln:53:10 |vpiPacked:1 |vpiTypespecMember: \_typespec_member: (Width), line:9:18, endln:9:23 @@ -693,10 +693,10 @@ design: (work@top) |vpiTypedefAlias: \_logic_typespec: (fmt_logic_t), line:6:9, endln:6:20 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamSubstituteComplex/dut.sv, line:4:1, endln:53:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamSubstituteComplex/dut.sv, line:4:1, endln:53:10 |vpiName:fmt_logic_t |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamSubstituteComplex/dut.sv, line:4:1, endln:53:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamSubstituteComplex/dut.sv, line:4:1, endln:53:10 |vpiRange: \_range: , line:6:15, endln:6:20 |vpiLeftRange: @@ -783,7 +783,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.XLEN), line:23:13, endln:23:17 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamSubstituteComplex/dut.sv, line:4:1, endln:53:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamSubstituteComplex/dut.sv, line:4:1, endln:53:10 |UINT:64 |vpiTypespec: \_int_typespec: @@ -793,14 +793,14 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.IS_XLEN64), line:25:12, endln:25:21 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamSubstituteComplex/dut.sv, line:4:1, endln:53:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamSubstituteComplex/dut.sv, line:4:1, endln:53:10 |vpiLocalParam:1 |vpiName:IS_XLEN64 |vpiFullName:work@top.IS_XLEN64 |vpiParameter: \_parameter: (work@top.RVF), line:26:16, endln:26:19 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamSubstituteComplex/dut.sv, line:4:1, endln:53:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamSubstituteComplex/dut.sv, line:4:1, endln:53:10 |vpiTypespec: \_bit_typespec: , line:26:12, endln:26:15 |vpiParent: @@ -812,7 +812,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.RVD), line:27:16, endln:27:19 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamSubstituteComplex/dut.sv, line:4:1, endln:53:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamSubstituteComplex/dut.sv, line:4:1, endln:53:10 |vpiTypespec: \_bit_typespec: , line:27:12, endln:27:15 |vpiParent: @@ -824,7 +824,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.XF16), line:28:16, endln:28:20 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamSubstituteComplex/dut.sv, line:4:1, endln:53:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamSubstituteComplex/dut.sv, line:4:1, endln:53:10 |BIN:0 |vpiTypespec: \_bit_typespec: , line:28:12, endln:28:15 @@ -837,7 +837,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.XF16ALT), line:29:16, endln:29:23 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamSubstituteComplex/dut.sv, line:4:1, endln:53:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamSubstituteComplex/dut.sv, line:4:1, endln:53:10 |BIN:0 |vpiTypespec: \_bit_typespec: , line:29:12, endln:29:15 @@ -850,7 +850,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.XF8), line:30:16, endln:30:19 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamSubstituteComplex/dut.sv, line:4:1, endln:53:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamSubstituteComplex/dut.sv, line:4:1, endln:53:10 |BIN:0 |vpiTypespec: \_bit_typespec: , line:30:12, endln:30:15 @@ -863,7 +863,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.XFVEC), line:31:16, endln:31:21 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamSubstituteComplex/dut.sv, line:4:1, endln:53:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamSubstituteComplex/dut.sv, line:4:1, endln:53:10 |BIN:0 |vpiTypespec: \_bit_typespec: , line:31:12, endln:31:15 @@ -876,7 +876,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.FPU_FEATURES), line:33:27, endln:33:39 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamSubstituteComplex/dut.sv, line:4:1, endln:53:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamSubstituteComplex/dut.sv, line:4:1, endln:53:10 |vpiTypespec: \_struct_typespec: (fpu_features_t), line:8:9, endln:8:15 |vpiLocalParam:1 @@ -885,7 +885,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.Features), line:40:29, endln:40:37 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamSubstituteComplex/dut.sv, line:4:1, endln:53:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamSubstituteComplex/dut.sv, line:4:1, endln:53:10 |vpiTypespec: \_struct_typespec: (fpu_features_t), line:8:9, endln:8:15 |vpiName:Features @@ -893,7 +893,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.FpFmtMask), line:41:29, endln:41:38 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamSubstituteComplex/dut.sv, line:4:1, endln:53:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamSubstituteComplex/dut.sv, line:4:1, endln:53:10 |vpiTypespec: \_logic_typespec: (fmt_logic_t), line:6:9, endln:6:20 |vpiParent: @@ -926,14 +926,14 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.DEBUGME), line:43:12, endln:43:19 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamSubstituteComplex/dut.sv, line:4:1, endln:53:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamSubstituteComplex/dut.sv, line:4:1, endln:53:10 |vpiLocalParam:1 |vpiName:DEBUGME |vpiFullName:work@top.DEBUGME |vpiParamAssign: \_param_assign: , line:16:27, endln:22:4 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamSubstituteComplex/dut.sv, line:4:1, endln:53:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamSubstituteComplex/dut.sv, line:4:1, endln:53:10 |vpiRhs: \_operation: , line:16:41, endln:22:4 |vpiOpType:75 @@ -997,7 +997,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:23:13, endln:23:22 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamSubstituteComplex/dut.sv, line:4:1, endln:53:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamSubstituteComplex/dut.sv, line:4:1, endln:53:10 |vpiRhs: \_constant: , line:23:20, endln:23:22 |vpiDecompile:64 @@ -1011,7 +1011,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:25:12, endln:25:51 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamSubstituteComplex/dut.sv, line:4:1, endln:53:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamSubstituteComplex/dut.sv, line:4:1, endln:53:10 |vpiRhs: \_operation: , line:25:25, endln:25:51 |vpiOpType:32 @@ -1054,7 +1054,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:26:16, endln:26:31 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamSubstituteComplex/dut.sv, line:4:1, endln:53:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamSubstituteComplex/dut.sv, line:4:1, endln:53:10 |vpiRhs: \_ref_obj: (IS_XLEN64), line:26:22, endln:26:31 |vpiName:IS_XLEN64 @@ -1063,7 +1063,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:27:16, endln:27:31 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamSubstituteComplex/dut.sv, line:4:1, endln:53:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamSubstituteComplex/dut.sv, line:4:1, endln:53:10 |vpiRhs: \_ref_obj: (IS_XLEN64), line:27:22, endln:27:31 |vpiName:IS_XLEN64 @@ -1072,7 +1072,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:28:16, endln:28:30 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamSubstituteComplex/dut.sv, line:4:1, endln:53:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamSubstituteComplex/dut.sv, line:4:1, endln:53:10 |vpiRhs: \_constant: , line:28:26, endln:28:30 |vpiDecompile:1'b0 @@ -1086,7 +1086,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:29:16, endln:29:30 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamSubstituteComplex/dut.sv, line:4:1, endln:53:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamSubstituteComplex/dut.sv, line:4:1, endln:53:10 |vpiRhs: \_constant: , line:29:26, endln:29:30 |vpiDecompile:1'b0 @@ -1100,7 +1100,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:30:16, endln:30:30 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamSubstituteComplex/dut.sv, line:4:1, endln:53:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamSubstituteComplex/dut.sv, line:4:1, endln:53:10 |vpiRhs: \_constant: , line:30:26, endln:30:30 |vpiDecompile:1'b0 @@ -1114,7 +1114,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:31:16, endln:31:30 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamSubstituteComplex/dut.sv, line:4:1, endln:53:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamSubstituteComplex/dut.sv, line:4:1, endln:53:10 |vpiRhs: \_constant: , line:31:26, endln:31:30 |vpiDecompile:1'b0 @@ -1128,7 +1128,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:33:27, endln:39:6 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamSubstituteComplex/dut.sv, line:4:1, endln:53:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamSubstituteComplex/dut.sv, line:4:1, endln:53:10 |vpiRhs: \_operation: , line:33:42, endln:39:6 |vpiOpType:75 @@ -1276,7 +1276,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:40:29, endln:40:58 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamSubstituteComplex/dut.sv, line:4:1, endln:53:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamSubstituteComplex/dut.sv, line:4:1, endln:53:10 |vpiRhs: \_ref_obj: (FPU_FEATURES), line:40:46, endln:40:58 |vpiName:FPU_FEATURES @@ -1285,7 +1285,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:41:29, endln:41:63 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamSubstituteComplex/dut.sv, line:4:1, endln:53:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamSubstituteComplex/dut.sv, line:4:1, endln:53:10 |vpiRhs: \_hier_path: (Features.FpFmtMask), line:41:45, endln:41:63 |vpiName:Features.FpFmtMask @@ -1302,7 +1302,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:43:12, endln:43:34 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamSubstituteComplex/dut.sv, line:4:1, endln:53:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamSubstituteComplex/dut.sv, line:4:1, endln:53:10 |vpiRhs: \_bit_select: (FpFmtMask), line:43:22, endln:43:34 |vpiParent: @@ -1325,19 +1325,19 @@ design: (work@top) \_struct_typespec: (fpu_features_t), line:8:9, endln:8:15 |vpiDefName:work@top |uhdmtopModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamSubstituteComplex/dut.sv, line:4:1, endln:53:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamSubstituteComplex/dut.sv, line:4:1, endln:53:10 |vpiName:work@top |vpiParameter: \_parameter: (work@top.RV64D_Xsflt), line:16:27, endln:16:38 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamSubstituteComplex/dut.sv, line:4:1, endln:53:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamSubstituteComplex/dut.sv, line:4:1, endln:53:10 |vpiTypespec: \_struct_typespec: (fpu_features_t), line:8:9, endln:8:15 |vpiParent: \_parameter: (work@top.RV64D_Xsflt), line:16:27, endln:16:38 |vpiName:fpu_features_t |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamSubstituteComplex/dut.sv, line:4:1, endln:53:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamSubstituteComplex/dut.sv, line:4:1, endln:53:10 |vpiPacked:1 |vpiTypespecMember: \_typespec_member: (Width), line:9:18, endln:9:23 @@ -1397,7 +1397,7 @@ design: (work@top) \_logic_typespec: (fmt_logic_t), line:6:9, endln:6:20 |vpiName:fmt_logic_t |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamSubstituteComplex/dut.sv, line:4:1, endln:53:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamSubstituteComplex/dut.sv, line:4:1, endln:53:10 |vpiRange: \_range: , line:6:15, endln:6:20 |vpiParent: @@ -1459,7 +1459,7 @@ design: (work@top) \_logic_typespec: (fmt_logic_t), line:6:9, endln:6:20 |vpiName:fmt_logic_t |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamSubstituteComplex/dut.sv, line:4:1, endln:53:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamSubstituteComplex/dut.sv, line:4:1, endln:53:10 |vpiRange: \_range: , line:6:15, endln:6:20 |vpiParent: @@ -1511,7 +1511,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.XLEN), line:23:13, endln:23:17 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamSubstituteComplex/dut.sv, line:4:1, endln:53:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamSubstituteComplex/dut.sv, line:4:1, endln:53:10 |UINT:64 |vpiTypespec: \_int_typespec: @@ -1523,14 +1523,14 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.IS_XLEN64), line:25:12, endln:25:21 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamSubstituteComplex/dut.sv, line:4:1, endln:53:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamSubstituteComplex/dut.sv, line:4:1, endln:53:10 |vpiLocalParam:1 |vpiName:IS_XLEN64 |vpiFullName:work@top.IS_XLEN64 |vpiParameter: \_parameter: (work@top.RVF), line:26:16, endln:26:19 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamSubstituteComplex/dut.sv, line:4:1, endln:53:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamSubstituteComplex/dut.sv, line:4:1, endln:53:10 |vpiTypespec: \_bit_typespec: , line:26:12, endln:26:15 |vpiParent: @@ -1542,7 +1542,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.RVD), line:27:16, endln:27:19 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamSubstituteComplex/dut.sv, line:4:1, endln:53:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamSubstituteComplex/dut.sv, line:4:1, endln:53:10 |vpiTypespec: \_bit_typespec: , line:27:12, endln:27:15 |vpiParent: @@ -1554,7 +1554,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.XF16), line:28:16, endln:28:20 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamSubstituteComplex/dut.sv, line:4:1, endln:53:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamSubstituteComplex/dut.sv, line:4:1, endln:53:10 |BIN:0 |vpiTypespec: \_bit_typespec: , line:28:12, endln:28:15 @@ -1567,7 +1567,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.XF16ALT), line:29:16, endln:29:23 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamSubstituteComplex/dut.sv, line:4:1, endln:53:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamSubstituteComplex/dut.sv, line:4:1, endln:53:10 |BIN:0 |vpiTypespec: \_bit_typespec: , line:29:12, endln:29:15 @@ -1580,7 +1580,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.XF8), line:30:16, endln:30:19 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamSubstituteComplex/dut.sv, line:4:1, endln:53:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamSubstituteComplex/dut.sv, line:4:1, endln:53:10 |BIN:0 |vpiTypespec: \_bit_typespec: , line:30:12, endln:30:15 @@ -1593,7 +1593,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.XFVEC), line:31:16, endln:31:21 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamSubstituteComplex/dut.sv, line:4:1, endln:53:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamSubstituteComplex/dut.sv, line:4:1, endln:53:10 |BIN:0 |vpiTypespec: \_bit_typespec: , line:31:12, endln:31:15 @@ -1606,14 +1606,14 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.FPU_FEATURES), line:33:27, endln:33:39 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamSubstituteComplex/dut.sv, line:4:1, endln:53:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamSubstituteComplex/dut.sv, line:4:1, endln:53:10 |vpiTypespec: \_struct_typespec: (fpu_features_t), line:8:9, endln:8:15 |vpiParent: \_parameter: (work@top.FPU_FEATURES), line:33:27, endln:33:39 |vpiName:fpu_features_t |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamSubstituteComplex/dut.sv, line:4:1, endln:53:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamSubstituteComplex/dut.sv, line:4:1, endln:53:10 |vpiPacked:1 |vpiTypespecMember: \_typespec_member: (Width), line:9:18, endln:9:23 @@ -1673,7 +1673,7 @@ design: (work@top) \_logic_typespec: (fmt_logic_t), line:6:9, endln:6:20 |vpiName:fmt_logic_t |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamSubstituteComplex/dut.sv, line:4:1, endln:53:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamSubstituteComplex/dut.sv, line:4:1, endln:53:10 |vpiRange: \_range: , line:6:15, endln:6:20 |vpiParent: @@ -1735,7 +1735,7 @@ design: (work@top) \_logic_typespec: (fmt_logic_t), line:6:9, endln:6:20 |vpiName:fmt_logic_t |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamSubstituteComplex/dut.sv, line:4:1, endln:53:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamSubstituteComplex/dut.sv, line:4:1, endln:53:10 |vpiRange: \_range: , line:6:15, endln:6:20 |vpiParent: @@ -1787,14 +1787,14 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.Features), line:40:29, endln:40:37 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamSubstituteComplex/dut.sv, line:4:1, endln:53:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamSubstituteComplex/dut.sv, line:4:1, endln:53:10 |vpiTypespec: \_struct_typespec: (fpu_features_t), line:8:9, endln:8:15 |vpiParent: \_parameter: (work@top.Features), line:40:29, endln:40:37 |vpiName:fpu_features_t |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamSubstituteComplex/dut.sv, line:4:1, endln:53:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamSubstituteComplex/dut.sv, line:4:1, endln:53:10 |vpiPacked:1 |vpiTypespecMember: \_typespec_member: (Width), line:9:18, endln:9:23 @@ -1854,7 +1854,7 @@ design: (work@top) \_logic_typespec: (fmt_logic_t), line:6:9, endln:6:20 |vpiName:fmt_logic_t |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamSubstituteComplex/dut.sv, line:4:1, endln:53:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamSubstituteComplex/dut.sv, line:4:1, endln:53:10 |vpiRange: \_range: , line:6:15, endln:6:20 |vpiParent: @@ -1916,7 +1916,7 @@ design: (work@top) \_logic_typespec: (fmt_logic_t), line:6:9, endln:6:20 |vpiName:fmt_logic_t |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamSubstituteComplex/dut.sv, line:4:1, endln:53:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamSubstituteComplex/dut.sv, line:4:1, endln:53:10 |vpiRange: \_range: , line:6:15, endln:6:20 |vpiParent: @@ -1967,7 +1967,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.FpFmtMask), line:41:29, endln:41:38 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamSubstituteComplex/dut.sv, line:4:1, endln:53:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamSubstituteComplex/dut.sv, line:4:1, endln:53:10 |vpiTypespec: \_logic_typespec: (fmt_logic_t), line:6:9, endln:6:20 |vpiParent: @@ -1979,7 +1979,7 @@ design: (work@top) \_logic_typespec: (fmt_logic_t), line:6:9, endln:6:20 |vpiName:fmt_logic_t |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamSubstituteComplex/dut.sv, line:4:1, endln:53:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamSubstituteComplex/dut.sv, line:4:1, endln:53:10 |vpiRange: \_range: , line:6:15, endln:6:20 |vpiParent: @@ -2025,14 +2025,14 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.DEBUGME), line:43:12, endln:43:19 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamSubstituteComplex/dut.sv, line:4:1, endln:53:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamSubstituteComplex/dut.sv, line:4:1, endln:53:10 |vpiLocalParam:1 |vpiName:DEBUGME |vpiFullName:work@top.DEBUGME |vpiParamAssign: \_param_assign: , line:16:27, endln:22:4 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamSubstituteComplex/dut.sv, line:4:1, endln:53:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamSubstituteComplex/dut.sv, line:4:1, endln:53:10 |vpiRhs: \_operation: , line:16:41, endln:22:4 |vpiParent: @@ -2251,7 +2251,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:23:13, endln:23:22 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamSubstituteComplex/dut.sv, line:4:1, endln:53:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamSubstituteComplex/dut.sv, line:4:1, endln:53:10 |vpiRhs: \_constant: , line:23:20, endln:23:22 |vpiDecompile:64 @@ -2265,7 +2265,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:25:12, endln:25:51 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamSubstituteComplex/dut.sv, line:4:1, endln:53:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamSubstituteComplex/dut.sv, line:4:1, endln:53:10 |vpiRhs: \_constant: , line:25:25, endln:25:51 |vpiDecompile:1 @@ -2277,7 +2277,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:26:16, endln:26:31 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamSubstituteComplex/dut.sv, line:4:1, endln:53:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamSubstituteComplex/dut.sv, line:4:1, endln:53:10 |vpiRhs: \_constant: , line:26:22, endln:26:31 |vpiDecompile:1 @@ -2291,7 +2291,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:27:16, endln:27:31 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamSubstituteComplex/dut.sv, line:4:1, endln:53:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamSubstituteComplex/dut.sv, line:4:1, endln:53:10 |vpiRhs: \_constant: , line:27:22, endln:27:31 |vpiDecompile:1 @@ -2305,7 +2305,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:28:16, endln:28:30 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamSubstituteComplex/dut.sv, line:4:1, endln:53:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamSubstituteComplex/dut.sv, line:4:1, endln:53:10 |vpiRhs: \_constant: , line:28:26, endln:28:30 |vpiDecompile:1'b0 @@ -2319,7 +2319,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:29:16, endln:29:30 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamSubstituteComplex/dut.sv, line:4:1, endln:53:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamSubstituteComplex/dut.sv, line:4:1, endln:53:10 |vpiRhs: \_constant: , line:29:26, endln:29:30 |vpiDecompile:1'b0 @@ -2333,7 +2333,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:30:16, endln:30:30 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamSubstituteComplex/dut.sv, line:4:1, endln:53:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamSubstituteComplex/dut.sv, line:4:1, endln:53:10 |vpiRhs: \_constant: , line:30:26, endln:30:30 |vpiDecompile:1'b0 @@ -2347,7 +2347,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:31:16, endln:31:30 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamSubstituteComplex/dut.sv, line:4:1, endln:53:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamSubstituteComplex/dut.sv, line:4:1, endln:53:10 |vpiRhs: \_constant: , line:31:26, endln:31:30 |vpiDecompile:1'b0 @@ -2361,7 +2361,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:33:27, endln:39:6 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamSubstituteComplex/dut.sv, line:4:1, endln:53:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamSubstituteComplex/dut.sv, line:4:1, endln:53:10 |vpiRhs: \_operation: , line:33:42, endln:39:6 |vpiParent: @@ -2664,7 +2664,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:40:29, endln:40:58 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamSubstituteComplex/dut.sv, line:4:1, endln:53:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamSubstituteComplex/dut.sv, line:4:1, endln:53:10 |vpiRhs: \_ref_obj: (FPU_FEATURES), line:40:46, endln:40:58 |vpiName:FPU_FEATURES @@ -2675,7 +2675,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:41:29, endln:41:63 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamSubstituteComplex/dut.sv, line:4:1, endln:53:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamSubstituteComplex/dut.sv, line:4:1, endln:53:10 |vpiRhs: \_constant: , line:41:45, endln:41:63 |vpiDecompile:5'b11000 @@ -2689,7 +2689,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:43:12, endln:43:34 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamSubstituteComplex/dut.sv, line:4:1, endln:53:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamSubstituteComplex/dut.sv, line:4:1, endln:53:10 |vpiRhs: \_constant: , line:43:22, endln:43:34 |vpiDecompile:1'b1 @@ -2708,7 +2708,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.genblk1), line:45:1, endln:47:4 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamSubstituteComplex/dut.sv, line:4:1, endln:53:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamSubstituteComplex/dut.sv, line:4:1, endln:53:10 |vpiName:genblk1 |vpiFullName:work@top.genblk1 |vpiGenScope: @@ -2716,8 +2716,8 @@ design: (work@top) |vpiParent: \_gen_scope_array: (work@top.genblk1), line:45:1, endln:47:4 |vpiFullName:work@top.genblk1 - |vpiModule: - \_module: work@GOOD (work@top.genblk1.good1), file:${SURELOG_DIR}/tests/ParamSubstituteComplex/dut.sv, line:46:3, endln:46:16 + |vpiModuleInst: + \_module_inst: work@GOOD (work@top.genblk1.good1), file:${SURELOG_DIR}/tests/ParamSubstituteComplex/dut.sv, line:46:3, endln:46:16 |vpiParent: \_gen_scope: (work@top.genblk1) |vpiName:good1 @@ -2728,7 +2728,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.genblk2), line:49:1, endln:51:4 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamSubstituteComplex/dut.sv, line:4:1, endln:53:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamSubstituteComplex/dut.sv, line:4:1, endln:53:10 |vpiName:genblk2 |vpiFullName:work@top.genblk2 |vpiGenScope: @@ -2736,8 +2736,8 @@ design: (work@top) |vpiParent: \_gen_scope_array: (work@top.genblk2), line:49:1, endln:51:4 |vpiFullName:work@top.genblk2 - |vpiModule: - \_module: work@GOOD (work@top.genblk2.good2), file:${SURELOG_DIR}/tests/ParamSubstituteComplex/dut.sv, line:50:3, endln:50:16 + |vpiModuleInst: + \_module_inst: work@GOOD (work@top.genblk2.good2), file:${SURELOG_DIR}/tests/ParamSubstituteComplex/dut.sv, line:50:3, endln:50:16 |vpiParent: \_gen_scope: (work@top.genblk2) |vpiName:good2 diff --git a/tests/ParamTypespec/ParamTypespec.log b/tests/ParamTypespec/ParamTypespec.log index f4701214e8..4dac1291da 100644 --- a/tests/ParamTypespec/ParamTypespec.log +++ b/tests/ParamTypespec/ParamTypespec.log @@ -195,7 +195,7 @@ integer_typespec 16 logic_net 2 logic_typespec 8 logic_var 1 -module 5 +module_inst 5 operation 38 package 3 param_assign 8 @@ -217,7 +217,7 @@ integer_typespec 16 logic_net 2 logic_typespec 8 logic_var 1 -module 5 +module_inst 5 operation 39 package 3 param_assign 8 @@ -398,14 +398,14 @@ design: (work@top) |vpiDefName:otp_ctrl_part_pkg |vpiTop:1 |uhdmallModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamTypespec/dut.sv, line:9:1, endln:16:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamTypespec/dut.sv, line:9:1, endln:16:10 |vpiParent: \_design: (work@top) |vpiFullName:work@top |vpiParameter: \_parameter: (work@top.PartInvDefault), line:2:26, endln:2:40 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamTypespec/dut.sv, line:9:1, endln:16:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamTypespec/dut.sv, line:9:1, endln:16:10 |vpiTypespec: \_logic_typespec: , line:2:14, endln:2:25 |vpiParent: @@ -438,13 +438,13 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.P), line:12:14, endln:12:15 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamTypespec/dut.sv, line:9:1, endln:16:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamTypespec/dut.sv, line:9:1, endln:16:10 |vpiName:P |vpiFullName:work@top.P |vpiParamAssign: \_param_assign: , line:2:26, endln:6:49 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamTypespec/dut.sv, line:9:1, endln:16:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamTypespec/dut.sv, line:9:1, endln:16:10 |vpiRhs: \_operation: , line:2:43, endln:6:49 |vpiParent: @@ -523,7 +523,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:12:14, endln:12:32 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamTypespec/dut.sv, line:9:1, endln:16:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamTypespec/dut.sv, line:9:1, endln:16:10 |vpiRhs: \_ref_obj: (PartInvDefault), line:12:18, endln:12:32 |vpiName:PartInvDefault @@ -535,20 +535,20 @@ design: (work@top) |vpiNet: \_logic_net: (work@top.o), line:9:23, endln:9:24 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamTypespec/dut.sv, line:9:1, endln:16:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamTypespec/dut.sv, line:9:1, endln:16:10 |vpiName:o |vpiFullName:work@top.o |vpiNet: \_logic_net: (work@top.part_buf_data), line:14:40, endln:14:53 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamTypespec/dut.sv, line:9:1, endln:16:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamTypespec/dut.sv, line:9:1, endln:16:10 |vpiName:part_buf_data |vpiFullName:work@top.part_buf_data |vpiNetType:36 |vpiPort: \_port: (o), line:9:23, endln:9:24 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamTypespec/dut.sv, line:9:1, endln:16:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamTypespec/dut.sv, line:9:1, endln:16:10 |vpiName:o |vpiDirection:2 |vpiLowConn: @@ -561,7 +561,7 @@ design: (work@top) |vpiContAssign: \_cont_assign: , line:15:11, endln:15:34 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamTypespec/dut.sv, line:9:1, endln:16:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamTypespec/dut.sv, line:9:1, endln:16:10 |vpiRhs: \_operation: , line:15:15, endln:15:34 |vpiParent: @@ -587,12 +587,12 @@ design: (work@top) |vpiActual: \_int_var: (work@top.o), line:9:23, endln:9:24 |uhdmtopModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamTypespec/dut.sv, line:9:1, endln:16:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamTypespec/dut.sv, line:9:1, endln:16:10 |vpiName:work@top |vpiVariables: \_int_var: (work@top.o), line:9:23, endln:9:24 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamTypespec/dut.sv, line:9:1, endln:16:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamTypespec/dut.sv, line:9:1, endln:16:10 |vpiTypespec: \_int_typespec: , line:9:19, endln:9:22 |vpiSigned:1 @@ -603,7 +603,7 @@ design: (work@top) |vpiVariables: \_logic_var: (work@top.part_buf_data), line:14:40, endln:14:58 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamTypespec/dut.sv, line:9:1, endln:16:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamTypespec/dut.sv, line:9:1, endln:16:10 |vpiTypespec: \_logic_typespec: , line:14:4, endln:14:39 |vpiRange: @@ -654,7 +654,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.PartInvDefault), line:2:26, endln:2:40 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamTypespec/dut.sv, line:9:1, endln:16:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamTypespec/dut.sv, line:9:1, endln:16:10 |vpiTypespec: \_logic_typespec: , line:2:14, endln:2:25 |vpiParent: @@ -687,13 +687,13 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.P), line:12:14, endln:12:15 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamTypespec/dut.sv, line:9:1, endln:16:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamTypespec/dut.sv, line:9:1, endln:16:10 |vpiName:P |vpiFullName:work@top.P |vpiParamAssign: \_param_assign: , line:2:26, endln:6:49 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamTypespec/dut.sv, line:9:1, endln:16:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamTypespec/dut.sv, line:9:1, endln:16:10 |vpiRhs: \_constant: |vpiSize:3 @@ -704,7 +704,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:12:14, endln:12:32 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamTypespec/dut.sv, line:9:1, endln:16:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamTypespec/dut.sv, line:9:1, endln:16:10 |vpiRhs: \_constant: , line:12:18, endln:12:32 |vpiDecompile:1 @@ -721,7 +721,7 @@ design: (work@top) |vpiPort: \_port: (o), line:9:23, endln:9:24 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamTypespec/dut.sv, line:9:1, endln:16:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamTypespec/dut.sv, line:9:1, endln:16:10 |vpiName:o |vpiDirection:2 |vpiLowConn: @@ -736,11 +736,11 @@ design: (work@top) \_int_typespec: , line:9:19, endln:9:22 |vpiSigned:1 |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamTypespec/dut.sv, line:9:1, endln:16:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamTypespec/dut.sv, line:9:1, endln:16:10 |vpiContAssign: \_cont_assign: , line:15:11, endln:15:34 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamTypespec/dut.sv, line:9:1, endln:16:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamTypespec/dut.sv, line:9:1, endln:16:10 |vpiRhs: \_operation: , line:15:15, endln:15:34 |vpiParent: diff --git a/tests/ParamTypespec2/ParamTypespec2.log b/tests/ParamTypespec2/ParamTypespec2.log index be7cbbb34f..b21f9e9d32 100644 --- a/tests/ParamTypespec2/ParamTypespec2.log +++ b/tests/ParamTypespec2/ParamTypespec2.log @@ -208,7 +208,7 @@ int_typespec 8 int_var 2 logic_net 3 logic_typespec 26 -module 7 +module_inst 7 operation 17 package 3 packed_array_typespec 3 @@ -235,7 +235,7 @@ int_typespec 8 int_var 2 logic_net 3 logic_typespec 26 -module 7 +module_inst 7 operation 21 package 3 packed_array_typespec 3 @@ -362,7 +362,7 @@ design: (work@top) |vpiTypespec: \_struct_typespec: (prim_esc_pkg::esc_tx_t), line:2:11, endln:2:17 |vpiParent: - \_module: work@nmi_gen (work@nmi_gen), file:${SURELOG_DIR}/tests/ParamTypespec2/dut.sv, line:12:1, endln:19:10 + \_module_inst: work@nmi_gen (work@nmi_gen), file:${SURELOG_DIR}/tests/ParamTypespec2/dut.sv, line:12:1, endln:19:10 |vpiName:prim_esc_pkg::esc_tx_t |vpiInstance: \_package: prim_esc_pkg (prim_esc_pkg::), file:${SURELOG_DIR}/tests/ParamTypespec2/dut.sv, line:1:1, endln:10:26 @@ -437,14 +437,14 @@ design: (work@top) |vpiDefName:prim_esc_pkg |vpiTop:1 |uhdmallModules: -\_module: work@nmi_gen (work@nmi_gen), file:${SURELOG_DIR}/tests/ParamTypespec2/dut.sv, line:12:1, endln:19:10 +\_module_inst: work@nmi_gen (work@nmi_gen), file:${SURELOG_DIR}/tests/ParamTypespec2/dut.sv, line:12:1, endln:19:10 |vpiParent: \_design: (work@top) |vpiFullName:work@nmi_gen |vpiParameter: \_parameter: (work@nmi_gen.ESC_TX_DEFAULT), line:7:22, endln:7:36 |vpiParent: - \_module: work@nmi_gen (work@nmi_gen), file:${SURELOG_DIR}/tests/ParamTypespec2/dut.sv, line:12:1, endln:19:10 + \_module_inst: work@nmi_gen (work@nmi_gen), file:${SURELOG_DIR}/tests/ParamTypespec2/dut.sv, line:12:1, endln:19:10 |vpiTypespec: \_struct_typespec: (prim_esc_pkg::esc_tx_t), line:2:11, endln:2:17 |vpiParent: @@ -491,7 +491,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:7:22, endln:8:54 |vpiParent: - \_module: work@nmi_gen (work@nmi_gen), file:${SURELOG_DIR}/tests/ParamTypespec2/dut.sv, line:12:1, endln:19:10 + \_module_inst: work@nmi_gen (work@nmi_gen), file:${SURELOG_DIR}/tests/ParamTypespec2/dut.sv, line:12:1, endln:19:10 |vpiRhs: \_operation: , line:7:39, endln:8:54 |vpiParent: @@ -586,19 +586,19 @@ design: (work@top) |vpiNet: \_logic_net: (work@nmi_gen.a), line:15:25, endln:15:26 |vpiParent: - \_module: work@nmi_gen (work@nmi_gen), file:${SURELOG_DIR}/tests/ParamTypespec2/dut.sv, line:12:1, endln:19:10 + \_module_inst: work@nmi_gen (work@nmi_gen), file:${SURELOG_DIR}/tests/ParamTypespec2/dut.sv, line:12:1, endln:19:10 |vpiName:a |vpiFullName:work@nmi_gen.a |vpiNet: \_logic_net: (work@nmi_gen.x), line:16:15, endln:16:16 |vpiParent: - \_module: work@nmi_gen (work@nmi_gen), file:${SURELOG_DIR}/tests/ParamTypespec2/dut.sv, line:12:1, endln:19:10 + \_module_inst: work@nmi_gen (work@nmi_gen), file:${SURELOG_DIR}/tests/ParamTypespec2/dut.sv, line:12:1, endln:19:10 |vpiName:x |vpiFullName:work@nmi_gen.x |vpiPort: \_port: (a), line:15:25, endln:15:26 |vpiParent: - \_module: work@nmi_gen (work@nmi_gen), file:${SURELOG_DIR}/tests/ParamTypespec2/dut.sv, line:12:1, endln:19:10 + \_module_inst: work@nmi_gen (work@nmi_gen), file:${SURELOG_DIR}/tests/ParamTypespec2/dut.sv, line:12:1, endln:19:10 |vpiName:a |vpiDirection:1 |vpiLowConn: @@ -630,7 +630,7 @@ design: (work@top) |vpiPort: \_port: (x), line:16:15, endln:16:16 |vpiParent: - \_module: work@nmi_gen (work@nmi_gen), file:${SURELOG_DIR}/tests/ParamTypespec2/dut.sv, line:12:1, endln:19:10 + \_module_inst: work@nmi_gen (work@nmi_gen), file:${SURELOG_DIR}/tests/ParamTypespec2/dut.sv, line:12:1, endln:19:10 |vpiName:x |vpiDirection:2 |vpiLowConn: @@ -643,7 +643,7 @@ design: (work@top) |vpiContAssign: \_cont_assign: , line:18:11, endln:18:22 |vpiParent: - \_module: work@nmi_gen (work@nmi_gen), file:${SURELOG_DIR}/tests/ParamTypespec2/dut.sv, line:12:1, endln:19:10 + \_module_inst: work@nmi_gen (work@nmi_gen), file:${SURELOG_DIR}/tests/ParamTypespec2/dut.sv, line:12:1, endln:19:10 |vpiRhs: \_operation: , line:18:15, endln:18:22 |vpiParent: @@ -669,7 +669,7 @@ design: (work@top) |vpiActual: \_int_var: (work@top.u_nmi_gen.x), line:16:15, endln:16:16 |uhdmallModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamTypespec2/dut.sv, line:21:1, endln:26:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamTypespec2/dut.sv, line:21:1, endln:26:10 |vpiParent: \_design: (work@top) |vpiFullName:work@top @@ -677,13 +677,13 @@ design: (work@top) |vpiNet: \_logic_net: (work@top.o), line:21:23, endln:21:24 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamTypespec2/dut.sv, line:21:1, endln:26:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamTypespec2/dut.sv, line:21:1, endln:26:10 |vpiName:o |vpiFullName:work@top.o |vpiPort: \_port: (o), line:21:23, endln:21:24 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamTypespec2/dut.sv, line:21:1, endln:26:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamTypespec2/dut.sv, line:21:1, endln:26:10 |vpiName:o |vpiDirection:2 |vpiLowConn: @@ -694,12 +694,12 @@ design: (work@top) \_int_typespec: , line:21:19, endln:21:22 |vpiSigned:1 |uhdmtopModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamTypespec2/dut.sv, line:21:1, endln:26:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamTypespec2/dut.sv, line:21:1, endln:26:10 |vpiName:work@top |vpiVariables: \_int_var: (work@top.o), line:21:23, endln:21:24 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamTypespec2/dut.sv, line:21:1, endln:26:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamTypespec2/dut.sv, line:21:1, endln:26:10 |vpiTypespec: \_int_typespec: , line:21:19, endln:21:22 |vpiSigned:1 @@ -713,7 +713,7 @@ design: (work@top) |vpiPort: \_port: (o), line:21:23, endln:21:24 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamTypespec2/dut.sv, line:21:1, endln:26:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamTypespec2/dut.sv, line:21:1, endln:26:10 |vpiName:o |vpiDirection:2 |vpiLowConn: @@ -728,17 +728,17 @@ design: (work@top) \_int_typespec: , line:21:19, endln:21:22 |vpiSigned:1 |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamTypespec2/dut.sv, line:21:1, endln:26:10 - |vpiModule: - \_module: work@nmi_gen (work@top.u_nmi_gen), file:${SURELOG_DIR}/tests/ParamTypespec2/dut.sv, line:22:4, endln:25:6 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamTypespec2/dut.sv, line:21:1, endln:26:10 + |vpiModuleInst: + \_module_inst: work@nmi_gen (work@top.u_nmi_gen), file:${SURELOG_DIR}/tests/ParamTypespec2/dut.sv, line:22:4, endln:25:6 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamTypespec2/dut.sv, line:21:1, endln:26:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamTypespec2/dut.sv, line:21:1, endln:26:10 |vpiName:u_nmi_gen |vpiFullName:work@top.u_nmi_gen |vpiVariables: \_packed_array_var: (work@top.u_nmi_gen.a), line:15:25, endln:15:26 |vpiParent: - \_module: work@nmi_gen (work@top.u_nmi_gen), file:${SURELOG_DIR}/tests/ParamTypespec2/dut.sv, line:22:4, endln:25:6 + \_module_inst: work@nmi_gen (work@top.u_nmi_gen), file:${SURELOG_DIR}/tests/ParamTypespec2/dut.sv, line:22:4, endln:25:6 |vpiName:a |vpiFullName:work@top.u_nmi_gen.a |vpiVisibility:1 @@ -770,7 +770,7 @@ design: (work@top) |vpiVariables: \_int_var: (work@top.u_nmi_gen.x), line:16:15, endln:16:16 |vpiParent: - \_module: work@nmi_gen (work@top.u_nmi_gen), file:${SURELOG_DIR}/tests/ParamTypespec2/dut.sv, line:22:4, endln:25:6 + \_module_inst: work@nmi_gen (work@top.u_nmi_gen), file:${SURELOG_DIR}/tests/ParamTypespec2/dut.sv, line:22:4, endln:25:6 |vpiTypespec: \_int_typespec: , line:16:11, endln:16:14 |vpiSigned:1 @@ -781,7 +781,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.u_nmi_gen.ESC_TX_DEFAULT), line:7:22, endln:7:36 |vpiParent: - \_module: work@nmi_gen (work@top.u_nmi_gen), file:${SURELOG_DIR}/tests/ParamTypespec2/dut.sv, line:22:4, endln:25:6 + \_module_inst: work@nmi_gen (work@top.u_nmi_gen), file:${SURELOG_DIR}/tests/ParamTypespec2/dut.sv, line:22:4, endln:25:6 |vpiTypespec: \_struct_typespec: (prim_esc_pkg::esc_tx_t), line:2:11, endln:2:17 |vpiParent: @@ -828,7 +828,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:7:22, endln:8:54 |vpiParent: - \_module: work@nmi_gen (work@top.u_nmi_gen), file:${SURELOG_DIR}/tests/ParamTypespec2/dut.sv, line:22:4, endln:25:6 + \_module_inst: work@nmi_gen (work@top.u_nmi_gen), file:${SURELOG_DIR}/tests/ParamTypespec2/dut.sv, line:22:4, endln:25:6 |vpiRhs: \_operation: , line:7:39, endln:8:54 |vpiParent: @@ -900,11 +900,11 @@ design: (work@top) |vpiDefFile:${SURELOG_DIR}/tests/ParamTypespec2/dut.sv |vpiDefLineNo:12 |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ParamTypespec2/dut.sv, line:21:1, endln:26:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamTypespec2/dut.sv, line:21:1, endln:26:10 |vpiPort: \_port: (a), line:15:25, endln:15:26 |vpiParent: - \_module: work@nmi_gen (work@top.u_nmi_gen), file:${SURELOG_DIR}/tests/ParamTypespec2/dut.sv, line:22:4, endln:25:6 + \_module_inst: work@nmi_gen (work@top.u_nmi_gen), file:${SURELOG_DIR}/tests/ParamTypespec2/dut.sv, line:22:4, endln:25:6 |vpiName:a |vpiDirection:1 |vpiHighConn: @@ -977,11 +977,11 @@ design: (work@top) |vpiElemTypespec: \_struct_typespec: (prim_esc_pkg::esc_tx_t), line:2:11, endln:2:17 |vpiInstance: - \_module: work@nmi_gen (work@top.u_nmi_gen), file:${SURELOG_DIR}/tests/ParamTypespec2/dut.sv, line:22:4, endln:25:6 + \_module_inst: work@nmi_gen (work@top.u_nmi_gen), file:${SURELOG_DIR}/tests/ParamTypespec2/dut.sv, line:22:4, endln:25:6 |vpiPort: \_port: (x), line:16:15, endln:16:16 |vpiParent: - \_module: work@nmi_gen (work@top.u_nmi_gen), file:${SURELOG_DIR}/tests/ParamTypespec2/dut.sv, line:22:4, endln:25:6 + \_module_inst: work@nmi_gen (work@top.u_nmi_gen), file:${SURELOG_DIR}/tests/ParamTypespec2/dut.sv, line:22:4, endln:25:6 |vpiName:x |vpiDirection:2 |vpiHighConn: @@ -1004,11 +1004,11 @@ design: (work@top) \_int_typespec: , line:16:11, endln:16:14 |vpiSigned:1 |vpiInstance: - \_module: work@nmi_gen (work@top.u_nmi_gen), file:${SURELOG_DIR}/tests/ParamTypespec2/dut.sv, line:22:4, endln:25:6 + \_module_inst: work@nmi_gen (work@top.u_nmi_gen), file:${SURELOG_DIR}/tests/ParamTypespec2/dut.sv, line:22:4, endln:25:6 |vpiContAssign: \_cont_assign: , line:18:11, endln:18:22 |vpiParent: - \_module: work@nmi_gen (work@top.u_nmi_gen), file:${SURELOG_DIR}/tests/ParamTypespec2/dut.sv, line:22:4, endln:25:6 + \_module_inst: work@nmi_gen (work@top.u_nmi_gen), file:${SURELOG_DIR}/tests/ParamTypespec2/dut.sv, line:22:4, endln:25:6 |vpiRhs: \_operation: , line:18:15, endln:18:22 |vpiParent: diff --git a/tests/PartSelect3/PartSelect3.log b/tests/PartSelect3/PartSelect3.log index 6ac1c6028b..aef6a5a934 100644 --- a/tests/PartSelect3/PartSelect3.log +++ b/tests/PartSelect3/PartSelect3.log @@ -117,7 +117,7 @@ design 1 logic_net 1 logic_typespec 1 logic_var 1 -module 4 +module_inst 4 part_select 2 range 6 ref_obj 2 @@ -132,7 +132,7 @@ design 1 logic_net 1 logic_typespec 1 logic_var 1 -module 4 +module_inst 4 part_select 3 range 6 ref_obj 3 @@ -151,7 +151,7 @@ design: (work@t) |vpiElaborated:1 |vpiName:work@t |uhdmallModules: -\_module: work@t (work@t), file:${SURELOG_DIR}/tests/PartSelect3/dut.sv, line:1:1, endln:4:10 +\_module_inst: work@t (work@t), file:${SURELOG_DIR}/tests/PartSelect3/dut.sv, line:1:1, endln:4:10 |vpiParent: \_design: (work@t) |vpiFullName:work@t @@ -159,14 +159,14 @@ design: (work@t) |vpiNet: \_logic_net: (work@t.state_d), line:2:23, endln:2:30 |vpiParent: - \_module: work@t (work@t), file:${SURELOG_DIR}/tests/PartSelect3/dut.sv, line:1:1, endln:4:10 + \_module_inst: work@t (work@t), file:${SURELOG_DIR}/tests/PartSelect3/dut.sv, line:1:1, endln:4:10 |vpiName:state_d |vpiFullName:work@t.state_d |vpiNetType:36 |vpiContAssign: \_cont_assign: , line:3:8, endln:3:40 |vpiParent: - \_module: work@t (work@t), file:${SURELOG_DIR}/tests/PartSelect3/dut.sv, line:1:1, endln:4:10 + \_module_inst: work@t (work@t), file:${SURELOG_DIR}/tests/PartSelect3/dut.sv, line:1:1, endln:4:10 |vpiRhs: \_constant: , line:3:29, endln:3:40 |vpiParent: @@ -215,12 +215,12 @@ design: (work@t) |UINT:0 |vpiConstType:9 |uhdmtopModules: -\_module: work@t (work@t), file:${SURELOG_DIR}/tests/PartSelect3/dut.sv, line:1:1, endln:4:10 +\_module_inst: work@t (work@t), file:${SURELOG_DIR}/tests/PartSelect3/dut.sv, line:1:1, endln:4:10 |vpiName:work@t |vpiVariables: \_logic_var: (work@t.state_d), line:2:23, endln:2:30 |vpiParent: - \_module: work@t (work@t), file:${SURELOG_DIR}/tests/PartSelect3/dut.sv, line:1:1, endln:4:10 + \_module_inst: work@t (work@t), file:${SURELOG_DIR}/tests/PartSelect3/dut.sv, line:1:1, endln:4:10 |vpiTypespec: \_logic_typespec: , line:2:1, endln:2:22 |vpiRange: @@ -340,7 +340,7 @@ design: (work@t) |vpiContAssign: \_cont_assign: , line:3:8, endln:3:40 |vpiParent: - \_module: work@t (work@t), file:${SURELOG_DIR}/tests/PartSelect3/dut.sv, line:1:1, endln:4:10 + \_module_inst: work@t (work@t), file:${SURELOG_DIR}/tests/PartSelect3/dut.sv, line:1:1, endln:4:10 |vpiRhs: \_constant: , line:3:29, endln:3:40 |vpiLhs: diff --git a/tests/PartSelect4/PartSelect4.log b/tests/PartSelect4/PartSelect4.log index f3911d1d73..20a6fb5b45 100644 --- a/tests/PartSelect4/PartSelect4.log +++ b/tests/PartSelect4/PartSelect4.log @@ -288,7 +288,7 @@ gen_scope_array 16 indexed_part_select 1 int_typespec 21 logic_typespec 1 -module 27 +module_inst 27 operation 23 param_assign 17 parameter 25 @@ -306,7 +306,7 @@ gen_scope_array 24 indexed_part_select 1 int_typespec 21 logic_typespec 1 -module 35 +module_inst 35 operation 23 param_assign 25 parameter 25 @@ -326,14 +326,14 @@ design: (work@xbar_main) |vpiElaborated:1 |vpiName:work@xbar_main |uhdmallModules: -\_module: work@tlul_fifo_sync (work@tlul_fifo_sync), file:${SURELOG_DIR}/tests/PartSelect4/dut.sv, line:2:1, endln:3:10 +\_module_inst: work@tlul_fifo_sync (work@tlul_fifo_sync), file:${SURELOG_DIR}/tests/PartSelect4/dut.sv, line:2:1, endln:3:10 |vpiParent: \_design: (work@xbar_main) |vpiFullName:work@tlul_fifo_sync |vpiParameter: \_parameter: (work@tlul_fifo_sync.ReqDepth), line:2:48, endln:2:56 |vpiParent: - \_module: work@tlul_fifo_sync (work@tlul_fifo_sync), file:${SURELOG_DIR}/tests/PartSelect4/dut.sv, line:2:1, endln:3:10 + \_module_inst: work@tlul_fifo_sync (work@tlul_fifo_sync), file:${SURELOG_DIR}/tests/PartSelect4/dut.sv, line:2:1, endln:3:10 |vpiTypespec: \_int_typespec: , line:2:35, endln:2:47 |vpiParent: @@ -343,19 +343,19 @@ design: (work@xbar_main) |vpiParamAssign: \_param_assign: , line:2:48, endln:2:56 |vpiParent: - \_module: work@tlul_fifo_sync (work@tlul_fifo_sync), file:${SURELOG_DIR}/tests/PartSelect4/dut.sv, line:2:1, endln:3:10 + \_module_inst: work@tlul_fifo_sync (work@tlul_fifo_sync), file:${SURELOG_DIR}/tests/PartSelect4/dut.sv, line:2:1, endln:3:10 |vpiLhs: \_parameter: (work@tlul_fifo_sync.ReqDepth), line:2:48, endln:2:56 |vpiDefName:work@tlul_fifo_sync |uhdmallModules: -\_module: work@tlul_socket_1n (work@tlul_socket_1n), file:${SURELOG_DIR}/tests/PartSelect4/dut.sv, line:5:1, endln:9:10 +\_module_inst: work@tlul_socket_1n (work@tlul_socket_1n), file:${SURELOG_DIR}/tests/PartSelect4/dut.sv, line:5:1, endln:9:10 |vpiParent: \_design: (work@xbar_main) |vpiFullName:work@tlul_socket_1n |vpiParameter: \_parameter: (work@tlul_socket_1n.N), line:5:48, endln:5:49 |vpiParent: - \_module: work@tlul_socket_1n (work@tlul_socket_1n), file:${SURELOG_DIR}/tests/PartSelect4/dut.sv, line:5:1, endln:9:10 + \_module_inst: work@tlul_socket_1n (work@tlul_socket_1n), file:${SURELOG_DIR}/tests/PartSelect4/dut.sv, line:5:1, endln:9:10 |vpiTypespec: \_int_typespec: , line:5:35, endln:5:47 |vpiParent: @@ -365,7 +365,7 @@ design: (work@xbar_main) |vpiParameter: \_parameter: (work@tlul_socket_1n.DReqDepth), line:5:75, endln:5:84 |vpiParent: - \_module: work@tlul_socket_1n (work@tlul_socket_1n), file:${SURELOG_DIR}/tests/PartSelect4/dut.sv, line:5:1, endln:9:10 + \_module_inst: work@tlul_socket_1n (work@tlul_socket_1n), file:${SURELOG_DIR}/tests/PartSelect4/dut.sv, line:5:1, endln:9:10 |vpiTypespec: \_bit_typespec: , line:5:61, endln:5:74 |vpiParent: @@ -419,25 +419,25 @@ design: (work@xbar_main) |vpiParamAssign: \_param_assign: , line:5:48, endln:5:49 |vpiParent: - \_module: work@tlul_socket_1n (work@tlul_socket_1n), file:${SURELOG_DIR}/tests/PartSelect4/dut.sv, line:5:1, endln:9:10 + \_module_inst: work@tlul_socket_1n (work@tlul_socket_1n), file:${SURELOG_DIR}/tests/PartSelect4/dut.sv, line:5:1, endln:9:10 |vpiLhs: \_parameter: (work@tlul_socket_1n.N), line:5:48, endln:5:49 |vpiParamAssign: \_param_assign: , line:5:75, endln:5:84 |vpiParent: - \_module: work@tlul_socket_1n (work@tlul_socket_1n), file:${SURELOG_DIR}/tests/PartSelect4/dut.sv, line:5:1, endln:9:10 + \_module_inst: work@tlul_socket_1n (work@tlul_socket_1n), file:${SURELOG_DIR}/tests/PartSelect4/dut.sv, line:5:1, endln:9:10 |vpiLhs: \_parameter: (work@tlul_socket_1n.DReqDepth), line:5:75, endln:5:84 |vpiDefName:work@tlul_socket_1n |uhdmallModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/PartSelect4/dut.sv, line:16:1, endln:21:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/PartSelect4/dut.sv, line:16:1, endln:21:10 |vpiParent: \_design: (work@xbar_main) |vpiFullName:work@top |vpiParameter: \_parameter: (work@top.A), line:18:12, endln:18:13 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/PartSelect4/dut.sv, line:16:1, endln:21:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/PartSelect4/dut.sv, line:16:1, endln:21:10 |HEX:200000000000000 |vpiTypespec: \_int_typespec: @@ -454,13 +454,13 @@ design: (work@xbar_main) |vpiParameter: \_parameter: (work@top.B), line:19:12, endln:19:13 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/PartSelect4/dut.sv, line:16:1, endln:21:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/PartSelect4/dut.sv, line:16:1, endln:21:10 |vpiName:B |vpiFullName:work@top.B |vpiParamAssign: \_param_assign: , line:18:12, endln:18:35 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/PartSelect4/dut.sv, line:16:1, endln:21:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/PartSelect4/dut.sv, line:16:1, endln:21:10 |vpiRhs: \_constant: , line:18:16, endln:18:35 |vpiDecompile:68'h200000000000000 @@ -474,7 +474,7 @@ design: (work@xbar_main) |vpiParamAssign: \_param_assign: , line:19:12, endln:19:25 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/PartSelect4/dut.sv, line:16:1, endln:21:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/PartSelect4/dut.sv, line:16:1, endln:21:10 |vpiRhs: \_indexed_part_select: , line:19:16, endln:19:25 |vpiParent: @@ -512,27 +512,27 @@ design: (work@xbar_main) \_parameter: (work@top.B), line:19:12, endln:19:13 |vpiDefName:work@top |uhdmallModules: -\_module: work@xbar_main (work@xbar_main), file:${SURELOG_DIR}/tests/PartSelect4/dut.sv, line:11:1, endln:13:10 +\_module_inst: work@xbar_main (work@xbar_main), file:${SURELOG_DIR}/tests/PartSelect4/dut.sv, line:11:1, endln:13:10 |vpiParent: \_design: (work@xbar_main) |vpiFullName:work@xbar_main |vpiDefName:work@xbar_main |uhdmtopModules: -\_module: work@xbar_main (work@xbar_main), file:${SURELOG_DIR}/tests/PartSelect4/dut.sv, line:11:1, endln:13:10 +\_module_inst: work@xbar_main (work@xbar_main), file:${SURELOG_DIR}/tests/PartSelect4/dut.sv, line:11:1, endln:13:10 |vpiName:work@xbar_main |vpiDefName:work@xbar_main |vpiTop:1 |vpiTopModule:1 - |vpiModule: - \_module: work@tlul_socket_1n (work@xbar_main.u_s1n_25), file:${SURELOG_DIR}/tests/PartSelect4/dut.sv, line:12:3, endln:12:72 + |vpiModuleInst: + \_module_inst: work@tlul_socket_1n (work@xbar_main.u_s1n_25), file:${SURELOG_DIR}/tests/PartSelect4/dut.sv, line:12:3, endln:12:72 |vpiParent: - \_module: work@xbar_main (work@xbar_main), file:${SURELOG_DIR}/tests/PartSelect4/dut.sv, line:11:1, endln:13:10 + \_module_inst: work@xbar_main (work@xbar_main), file:${SURELOG_DIR}/tests/PartSelect4/dut.sv, line:11:1, endln:13:10 |vpiName:u_s1n_25 |vpiFullName:work@xbar_main.u_s1n_25 |vpiParameter: \_parameter: (work@xbar_main.u_s1n_25.N), line:5:48, endln:5:49 |vpiParent: - \_module: work@tlul_socket_1n (work@xbar_main.u_s1n_25), file:${SURELOG_DIR}/tests/PartSelect4/dut.sv, line:12:3, endln:12:72 + \_module_inst: work@tlul_socket_1n (work@xbar_main.u_s1n_25), file:${SURELOG_DIR}/tests/PartSelect4/dut.sv, line:12:3, endln:12:72 |vpiTypespec: \_int_typespec: , line:5:35, endln:5:47 |vpiParent: @@ -542,7 +542,7 @@ design: (work@xbar_main) |vpiParameter: \_parameter: (work@xbar_main.u_s1n_25.DReqDepth), line:5:75, endln:5:84 |vpiParent: - \_module: work@tlul_socket_1n (work@xbar_main.u_s1n_25), file:${SURELOG_DIR}/tests/PartSelect4/dut.sv, line:12:3, endln:12:72 + \_module_inst: work@tlul_socket_1n (work@xbar_main.u_s1n_25), file:${SURELOG_DIR}/tests/PartSelect4/dut.sv, line:12:3, endln:12:72 |vpiTypespec: \_bit_typespec: , line:5:61, endln:5:74 |vpiParent: @@ -599,7 +599,7 @@ design: (work@xbar_main) |vpiParamAssign: \_param_assign: , line:5:48, endln:5:49 |vpiParent: - \_module: work@tlul_socket_1n (work@xbar_main.u_s1n_25), file:${SURELOG_DIR}/tests/PartSelect4/dut.sv, line:12:3, endln:12:72 + \_module_inst: work@tlul_socket_1n (work@xbar_main.u_s1n_25), file:${SURELOG_DIR}/tests/PartSelect4/dut.sv, line:12:3, endln:12:72 |vpiOverriden:1 |vpiRhs: \_constant: @@ -614,7 +614,7 @@ design: (work@xbar_main) |vpiParamAssign: \_param_assign: , line:5:75, endln:5:84 |vpiParent: - \_module: work@tlul_socket_1n (work@xbar_main.u_s1n_25), file:${SURELOG_DIR}/tests/PartSelect4/dut.sv, line:12:3, endln:12:72 + \_module_inst: work@tlul_socket_1n (work@xbar_main.u_s1n_25), file:${SURELOG_DIR}/tests/PartSelect4/dut.sv, line:12:3, endln:12:72 |vpiOverriden:1 |vpiRhs: \_constant: @@ -630,11 +630,11 @@ design: (work@xbar_main) |vpiDefFile:${SURELOG_DIR}/tests/PartSelect4/dut.sv |vpiDefLineNo:5 |vpiInstance: - \_module: work@xbar_main (work@xbar_main), file:${SURELOG_DIR}/tests/PartSelect4/dut.sv, line:11:1, endln:13:10 + \_module_inst: work@xbar_main (work@xbar_main), file:${SURELOG_DIR}/tests/PartSelect4/dut.sv, line:11:1, endln:13:10 |vpiGenScopeArray: \_gen_scope_array: (work@xbar_main.u_s1n_25.gen_dfifo[0]), line:6:36, endln:8:6 |vpiParent: - \_module: work@tlul_socket_1n (work@xbar_main.u_s1n_25), file:${SURELOG_DIR}/tests/PartSelect4/dut.sv, line:12:3, endln:12:72 + \_module_inst: work@tlul_socket_1n (work@xbar_main.u_s1n_25), file:${SURELOG_DIR}/tests/PartSelect4/dut.sv, line:12:3, endln:12:72 |vpiName:gen_dfifo[0] |vpiFullName:work@xbar_main.u_s1n_25.gen_dfifo[0] |vpiGenScope: @@ -652,8 +652,8 @@ design: (work@xbar_main) |vpiLocalParam:1 |vpiName:i |vpiFullName:work@xbar_main.u_s1n_25.gen_dfifo[0].i - |vpiModule: - \_module: work@tlul_fifo_sync (work@xbar_main.u_s1n_25.gen_dfifo[0].fifo_d), file:${SURELOG_DIR}/tests/PartSelect4/dut.sv, line:7:5, endln:7:61 + |vpiModuleInst: + \_module_inst: work@tlul_fifo_sync (work@xbar_main.u_s1n_25.gen_dfifo[0].fifo_d), file:${SURELOG_DIR}/tests/PartSelect4/dut.sv, line:7:5, endln:7:61 |vpiParent: \_gen_scope: (work@xbar_main.u_s1n_25.gen_dfifo[0]) |vpiName:fifo_d @@ -671,7 +671,7 @@ design: (work@xbar_main) |vpiParamAssign: \_param_assign: , line:2:48, endln:2:56 |vpiParent: - \_module: work@tlul_fifo_sync (work@xbar_main.u_s1n_25.gen_dfifo[0].fifo_d), file:${SURELOG_DIR}/tests/PartSelect4/dut.sv, line:7:5, endln:7:61 + \_module_inst: work@tlul_fifo_sync (work@xbar_main.u_s1n_25.gen_dfifo[0].fifo_d), file:${SURELOG_DIR}/tests/PartSelect4/dut.sv, line:7:5, endln:7:61 |vpiOverriden:1 |vpiRhs: \_constant: @@ -689,7 +689,7 @@ design: (work@xbar_main) |vpiGenScopeArray: \_gen_scope_array: (work@xbar_main.u_s1n_25.gen_dfifo[1]), line:6:36, endln:8:6 |vpiParent: - \_module: work@tlul_socket_1n (work@xbar_main.u_s1n_25), file:${SURELOG_DIR}/tests/PartSelect4/dut.sv, line:12:3, endln:12:72 + \_module_inst: work@tlul_socket_1n (work@xbar_main.u_s1n_25), file:${SURELOG_DIR}/tests/PartSelect4/dut.sv, line:12:3, endln:12:72 |vpiName:gen_dfifo[1] |vpiFullName:work@xbar_main.u_s1n_25.gen_dfifo[1] |vpiGenScope: @@ -707,8 +707,8 @@ design: (work@xbar_main) |vpiLocalParam:1 |vpiName:i |vpiFullName:work@xbar_main.u_s1n_25.gen_dfifo[1].i - |vpiModule: - \_module: work@tlul_fifo_sync (work@xbar_main.u_s1n_25.gen_dfifo[1].fifo_d), file:${SURELOG_DIR}/tests/PartSelect4/dut.sv, line:7:5, endln:7:61 + |vpiModuleInst: + \_module_inst: work@tlul_fifo_sync (work@xbar_main.u_s1n_25.gen_dfifo[1].fifo_d), file:${SURELOG_DIR}/tests/PartSelect4/dut.sv, line:7:5, endln:7:61 |vpiParent: \_gen_scope: (work@xbar_main.u_s1n_25.gen_dfifo[1]) |vpiName:fifo_d @@ -726,7 +726,7 @@ design: (work@xbar_main) |vpiParamAssign: \_param_assign: , line:2:48, endln:2:56 |vpiParent: - \_module: work@tlul_fifo_sync (work@xbar_main.u_s1n_25.gen_dfifo[1].fifo_d), file:${SURELOG_DIR}/tests/PartSelect4/dut.sv, line:7:5, endln:7:61 + \_module_inst: work@tlul_fifo_sync (work@xbar_main.u_s1n_25.gen_dfifo[1].fifo_d), file:${SURELOG_DIR}/tests/PartSelect4/dut.sv, line:7:5, endln:7:61 |vpiOverriden:1 |vpiRhs: \_constant: @@ -744,7 +744,7 @@ design: (work@xbar_main) |vpiGenScopeArray: \_gen_scope_array: (work@xbar_main.u_s1n_25.gen_dfifo[2]), line:6:36, endln:8:6 |vpiParent: - \_module: work@tlul_socket_1n (work@xbar_main.u_s1n_25), file:${SURELOG_DIR}/tests/PartSelect4/dut.sv, line:12:3, endln:12:72 + \_module_inst: work@tlul_socket_1n (work@xbar_main.u_s1n_25), file:${SURELOG_DIR}/tests/PartSelect4/dut.sv, line:12:3, endln:12:72 |vpiName:gen_dfifo[2] |vpiFullName:work@xbar_main.u_s1n_25.gen_dfifo[2] |vpiGenScope: @@ -762,8 +762,8 @@ design: (work@xbar_main) |vpiLocalParam:1 |vpiName:i |vpiFullName:work@xbar_main.u_s1n_25.gen_dfifo[2].i - |vpiModule: - \_module: work@tlul_fifo_sync (work@xbar_main.u_s1n_25.gen_dfifo[2].fifo_d), file:${SURELOG_DIR}/tests/PartSelect4/dut.sv, line:7:5, endln:7:61 + |vpiModuleInst: + \_module_inst: work@tlul_fifo_sync (work@xbar_main.u_s1n_25.gen_dfifo[2].fifo_d), file:${SURELOG_DIR}/tests/PartSelect4/dut.sv, line:7:5, endln:7:61 |vpiParent: \_gen_scope: (work@xbar_main.u_s1n_25.gen_dfifo[2]) |vpiName:fifo_d @@ -781,7 +781,7 @@ design: (work@xbar_main) |vpiParamAssign: \_param_assign: , line:2:48, endln:2:56 |vpiParent: - \_module: work@tlul_fifo_sync (work@xbar_main.u_s1n_25.gen_dfifo[2].fifo_d), file:${SURELOG_DIR}/tests/PartSelect4/dut.sv, line:7:5, endln:7:61 + \_module_inst: work@tlul_fifo_sync (work@xbar_main.u_s1n_25.gen_dfifo[2].fifo_d), file:${SURELOG_DIR}/tests/PartSelect4/dut.sv, line:7:5, endln:7:61 |vpiOverriden:1 |vpiRhs: \_constant: @@ -799,7 +799,7 @@ design: (work@xbar_main) |vpiGenScopeArray: \_gen_scope_array: (work@xbar_main.u_s1n_25.gen_dfifo[3]), line:6:36, endln:8:6 |vpiParent: - \_module: work@tlul_socket_1n (work@xbar_main.u_s1n_25), file:${SURELOG_DIR}/tests/PartSelect4/dut.sv, line:12:3, endln:12:72 + \_module_inst: work@tlul_socket_1n (work@xbar_main.u_s1n_25), file:${SURELOG_DIR}/tests/PartSelect4/dut.sv, line:12:3, endln:12:72 |vpiName:gen_dfifo[3] |vpiFullName:work@xbar_main.u_s1n_25.gen_dfifo[3] |vpiGenScope: @@ -817,8 +817,8 @@ design: (work@xbar_main) |vpiLocalParam:1 |vpiName:i |vpiFullName:work@xbar_main.u_s1n_25.gen_dfifo[3].i - |vpiModule: - \_module: work@tlul_fifo_sync (work@xbar_main.u_s1n_25.gen_dfifo[3].fifo_d), file:${SURELOG_DIR}/tests/PartSelect4/dut.sv, line:7:5, endln:7:61 + |vpiModuleInst: + \_module_inst: work@tlul_fifo_sync (work@xbar_main.u_s1n_25.gen_dfifo[3].fifo_d), file:${SURELOG_DIR}/tests/PartSelect4/dut.sv, line:7:5, endln:7:61 |vpiParent: \_gen_scope: (work@xbar_main.u_s1n_25.gen_dfifo[3]) |vpiName:fifo_d @@ -836,7 +836,7 @@ design: (work@xbar_main) |vpiParamAssign: \_param_assign: , line:2:48, endln:2:56 |vpiParent: - \_module: work@tlul_fifo_sync (work@xbar_main.u_s1n_25.gen_dfifo[3].fifo_d), file:${SURELOG_DIR}/tests/PartSelect4/dut.sv, line:7:5, endln:7:61 + \_module_inst: work@tlul_fifo_sync (work@xbar_main.u_s1n_25.gen_dfifo[3].fifo_d), file:${SURELOG_DIR}/tests/PartSelect4/dut.sv, line:7:5, endln:7:61 |vpiOverriden:1 |vpiRhs: \_constant: @@ -854,7 +854,7 @@ design: (work@xbar_main) |vpiGenScopeArray: \_gen_scope_array: (work@xbar_main.u_s1n_25.gen_dfifo[4]), line:6:36, endln:8:6 |vpiParent: - \_module: work@tlul_socket_1n (work@xbar_main.u_s1n_25), file:${SURELOG_DIR}/tests/PartSelect4/dut.sv, line:12:3, endln:12:72 + \_module_inst: work@tlul_socket_1n (work@xbar_main.u_s1n_25), file:${SURELOG_DIR}/tests/PartSelect4/dut.sv, line:12:3, endln:12:72 |vpiName:gen_dfifo[4] |vpiFullName:work@xbar_main.u_s1n_25.gen_dfifo[4] |vpiGenScope: @@ -872,8 +872,8 @@ design: (work@xbar_main) |vpiLocalParam:1 |vpiName:i |vpiFullName:work@xbar_main.u_s1n_25.gen_dfifo[4].i - |vpiModule: - \_module: work@tlul_fifo_sync (work@xbar_main.u_s1n_25.gen_dfifo[4].fifo_d), file:${SURELOG_DIR}/tests/PartSelect4/dut.sv, line:7:5, endln:7:61 + |vpiModuleInst: + \_module_inst: work@tlul_fifo_sync (work@xbar_main.u_s1n_25.gen_dfifo[4].fifo_d), file:${SURELOG_DIR}/tests/PartSelect4/dut.sv, line:7:5, endln:7:61 |vpiParent: \_gen_scope: (work@xbar_main.u_s1n_25.gen_dfifo[4]) |vpiName:fifo_d @@ -891,7 +891,7 @@ design: (work@xbar_main) |vpiParamAssign: \_param_assign: , line:2:48, endln:2:56 |vpiParent: - \_module: work@tlul_fifo_sync (work@xbar_main.u_s1n_25.gen_dfifo[4].fifo_d), file:${SURELOG_DIR}/tests/PartSelect4/dut.sv, line:7:5, endln:7:61 + \_module_inst: work@tlul_fifo_sync (work@xbar_main.u_s1n_25.gen_dfifo[4].fifo_d), file:${SURELOG_DIR}/tests/PartSelect4/dut.sv, line:7:5, endln:7:61 |vpiOverriden:1 |vpiRhs: \_constant: @@ -909,7 +909,7 @@ design: (work@xbar_main) |vpiGenScopeArray: \_gen_scope_array: (work@xbar_main.u_s1n_25.gen_dfifo[5]), line:6:36, endln:8:6 |vpiParent: - \_module: work@tlul_socket_1n (work@xbar_main.u_s1n_25), file:${SURELOG_DIR}/tests/PartSelect4/dut.sv, line:12:3, endln:12:72 + \_module_inst: work@tlul_socket_1n (work@xbar_main.u_s1n_25), file:${SURELOG_DIR}/tests/PartSelect4/dut.sv, line:12:3, endln:12:72 |vpiName:gen_dfifo[5] |vpiFullName:work@xbar_main.u_s1n_25.gen_dfifo[5] |vpiGenScope: @@ -927,8 +927,8 @@ design: (work@xbar_main) |vpiLocalParam:1 |vpiName:i |vpiFullName:work@xbar_main.u_s1n_25.gen_dfifo[5].i - |vpiModule: - \_module: work@tlul_fifo_sync (work@xbar_main.u_s1n_25.gen_dfifo[5].fifo_d), file:${SURELOG_DIR}/tests/PartSelect4/dut.sv, line:7:5, endln:7:61 + |vpiModuleInst: + \_module_inst: work@tlul_fifo_sync (work@xbar_main.u_s1n_25.gen_dfifo[5].fifo_d), file:${SURELOG_DIR}/tests/PartSelect4/dut.sv, line:7:5, endln:7:61 |vpiParent: \_gen_scope: (work@xbar_main.u_s1n_25.gen_dfifo[5]) |vpiName:fifo_d @@ -946,7 +946,7 @@ design: (work@xbar_main) |vpiParamAssign: \_param_assign: , line:2:48, endln:2:56 |vpiParent: - \_module: work@tlul_fifo_sync (work@xbar_main.u_s1n_25.gen_dfifo[5].fifo_d), file:${SURELOG_DIR}/tests/PartSelect4/dut.sv, line:7:5, endln:7:61 + \_module_inst: work@tlul_fifo_sync (work@xbar_main.u_s1n_25.gen_dfifo[5].fifo_d), file:${SURELOG_DIR}/tests/PartSelect4/dut.sv, line:7:5, endln:7:61 |vpiOverriden:1 |vpiRhs: \_constant: @@ -964,7 +964,7 @@ design: (work@xbar_main) |vpiGenScopeArray: \_gen_scope_array: (work@xbar_main.u_s1n_25.gen_dfifo[6]), line:6:36, endln:8:6 |vpiParent: - \_module: work@tlul_socket_1n (work@xbar_main.u_s1n_25), file:${SURELOG_DIR}/tests/PartSelect4/dut.sv, line:12:3, endln:12:72 + \_module_inst: work@tlul_socket_1n (work@xbar_main.u_s1n_25), file:${SURELOG_DIR}/tests/PartSelect4/dut.sv, line:12:3, endln:12:72 |vpiName:gen_dfifo[6] |vpiFullName:work@xbar_main.u_s1n_25.gen_dfifo[6] |vpiGenScope: @@ -982,8 +982,8 @@ design: (work@xbar_main) |vpiLocalParam:1 |vpiName:i |vpiFullName:work@xbar_main.u_s1n_25.gen_dfifo[6].i - |vpiModule: - \_module: work@tlul_fifo_sync (work@xbar_main.u_s1n_25.gen_dfifo[6].fifo_d), file:${SURELOG_DIR}/tests/PartSelect4/dut.sv, line:7:5, endln:7:61 + |vpiModuleInst: + \_module_inst: work@tlul_fifo_sync (work@xbar_main.u_s1n_25.gen_dfifo[6].fifo_d), file:${SURELOG_DIR}/tests/PartSelect4/dut.sv, line:7:5, endln:7:61 |vpiParent: \_gen_scope: (work@xbar_main.u_s1n_25.gen_dfifo[6]) |vpiName:fifo_d @@ -1001,7 +1001,7 @@ design: (work@xbar_main) |vpiParamAssign: \_param_assign: , line:2:48, endln:2:56 |vpiParent: - \_module: work@tlul_fifo_sync (work@xbar_main.u_s1n_25.gen_dfifo[6].fifo_d), file:${SURELOG_DIR}/tests/PartSelect4/dut.sv, line:7:5, endln:7:61 + \_module_inst: work@tlul_fifo_sync (work@xbar_main.u_s1n_25.gen_dfifo[6].fifo_d), file:${SURELOG_DIR}/tests/PartSelect4/dut.sv, line:7:5, endln:7:61 |vpiOverriden:1 |vpiRhs: \_constant: @@ -1019,7 +1019,7 @@ design: (work@xbar_main) |vpiGenScopeArray: \_gen_scope_array: (work@xbar_main.u_s1n_25.gen_dfifo[7]), line:6:36, endln:8:6 |vpiParent: - \_module: work@tlul_socket_1n (work@xbar_main.u_s1n_25), file:${SURELOG_DIR}/tests/PartSelect4/dut.sv, line:12:3, endln:12:72 + \_module_inst: work@tlul_socket_1n (work@xbar_main.u_s1n_25), file:${SURELOG_DIR}/tests/PartSelect4/dut.sv, line:12:3, endln:12:72 |vpiName:gen_dfifo[7] |vpiFullName:work@xbar_main.u_s1n_25.gen_dfifo[7] |vpiGenScope: @@ -1037,8 +1037,8 @@ design: (work@xbar_main) |vpiLocalParam:1 |vpiName:i |vpiFullName:work@xbar_main.u_s1n_25.gen_dfifo[7].i - |vpiModule: - \_module: work@tlul_fifo_sync (work@xbar_main.u_s1n_25.gen_dfifo[7].fifo_d), file:${SURELOG_DIR}/tests/PartSelect4/dut.sv, line:7:5, endln:7:61 + |vpiModuleInst: + \_module_inst: work@tlul_fifo_sync (work@xbar_main.u_s1n_25.gen_dfifo[7].fifo_d), file:${SURELOG_DIR}/tests/PartSelect4/dut.sv, line:7:5, endln:7:61 |vpiParent: \_gen_scope: (work@xbar_main.u_s1n_25.gen_dfifo[7]) |vpiName:fifo_d @@ -1056,7 +1056,7 @@ design: (work@xbar_main) |vpiParamAssign: \_param_assign: , line:2:48, endln:2:56 |vpiParent: - \_module: work@tlul_fifo_sync (work@xbar_main.u_s1n_25.gen_dfifo[7].fifo_d), file:${SURELOG_DIR}/tests/PartSelect4/dut.sv, line:7:5, endln:7:61 + \_module_inst: work@tlul_fifo_sync (work@xbar_main.u_s1n_25.gen_dfifo[7].fifo_d), file:${SURELOG_DIR}/tests/PartSelect4/dut.sv, line:7:5, endln:7:61 |vpiOverriden:1 |vpiRhs: \_constant: @@ -1072,12 +1072,12 @@ design: (work@xbar_main) |vpiDefFile:${SURELOG_DIR}/tests/PartSelect4/dut.sv |vpiDefLineNo:2 |uhdmtopModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/PartSelect4/dut.sv, line:16:1, endln:21:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/PartSelect4/dut.sv, line:16:1, endln:21:10 |vpiName:work@top |vpiParameter: \_parameter: (work@top.A), line:18:12, endln:18:13 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/PartSelect4/dut.sv, line:16:1, endln:21:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/PartSelect4/dut.sv, line:16:1, endln:21:10 |HEX:200000000000000 |vpiTypespec: \_int_typespec: @@ -1102,13 +1102,13 @@ design: (work@xbar_main) |vpiParameter: \_parameter: (work@top.B), line:19:12, endln:19:13 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/PartSelect4/dut.sv, line:16:1, endln:21:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/PartSelect4/dut.sv, line:16:1, endln:21:10 |vpiName:B |vpiFullName:work@top.B |vpiParamAssign: \_param_assign: , line:18:12, endln:18:35 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/PartSelect4/dut.sv, line:16:1, endln:21:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/PartSelect4/dut.sv, line:16:1, endln:21:10 |vpiRhs: \_constant: , line:18:16, endln:18:35 |vpiDecompile:68'h200000000000000 @@ -1122,7 +1122,7 @@ design: (work@xbar_main) |vpiParamAssign: \_param_assign: , line:19:12, endln:19:25 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/PartSelect4/dut.sv, line:16:1, endln:21:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/PartSelect4/dut.sv, line:16:1, endln:21:10 |vpiRhs: \_constant: , line:19:16, endln:19:25 |vpiDecompile:0 diff --git a/tests/PartSelectElab/PartSelectElab.log b/tests/PartSelectElab/PartSelectElab.log index c681e0fd63..792a1649fb 100644 --- a/tests/PartSelectElab/PartSelectElab.log +++ b/tests/PartSelectElab/PartSelectElab.log @@ -31,7 +31,7 @@ design 1 event_control 1 logic_net 6 logic_typespec 7 -module 3 +module_inst 3 operation 2 part_select 2 port 4 @@ -49,7 +49,7 @@ design 1 event_control 2 logic_net 6 logic_typespec 7 -module 3 +module_inst 3 operation 4 part_select 4 port 6 @@ -69,7 +69,7 @@ design: (work@test) |vpiElaborated:1 |vpiName:work@test |uhdmallModules: -\_module: work@test (work@test), file:${SURELOG_DIR}/tests/PartSelectElab/dut.sv, line:1:1, endln:8:10 +\_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/PartSelectElab/dut.sv, line:1:1, endln:8:10 |vpiParent: \_design: (work@test) |vpiFullName:work@test @@ -77,27 +77,27 @@ design: (work@test) |vpiNet: \_logic_net: (work@test.state), line:1:24, endln:1:29 |vpiParent: - \_module: work@test (work@test), file:${SURELOG_DIR}/tests/PartSelectElab/dut.sv, line:1:1, endln:8:10 + \_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/PartSelectElab/dut.sv, line:1:1, endln:8:10 |vpiName:state |vpiFullName:work@test.state |vpiNetType:48 |vpiNet: \_logic_net: (work@test.clk), line:1:37, endln:1:40 |vpiParent: - \_module: work@test (work@test), file:${SURELOG_DIR}/tests/PartSelectElab/dut.sv, line:1:1, endln:8:10 + \_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/PartSelectElab/dut.sv, line:1:1, endln:8:10 |vpiName:clk |vpiFullName:work@test.clk |vpiNet: \_logic_net: (work@test.data), line:2:12, endln:2:16 |vpiParent: - \_module: work@test (work@test), file:${SURELOG_DIR}/tests/PartSelectElab/dut.sv, line:1:1, endln:8:10 + \_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/PartSelectElab/dut.sv, line:1:1, endln:8:10 |vpiName:data |vpiFullName:work@test.data |vpiNetType:48 |vpiPort: \_port: (state), line:1:24, endln:1:29 |vpiParent: - \_module: work@test (work@test), file:${SURELOG_DIR}/tests/PartSelectElab/dut.sv, line:1:1, endln:8:10 + \_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/PartSelectElab/dut.sv, line:1:1, endln:8:10 |vpiName:state |vpiDirection:2 |vpiLowConn: @@ -109,7 +109,7 @@ design: (work@test) |vpiPort: \_port: (clk), line:1:37, endln:1:40 |vpiParent: - \_module: work@test (work@test), file:${SURELOG_DIR}/tests/PartSelectElab/dut.sv, line:1:1, endln:8:10 + \_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/PartSelectElab/dut.sv, line:1:1, endln:8:10 |vpiName:clk |vpiDirection:1 |vpiLowConn: @@ -121,7 +121,7 @@ design: (work@test) |vpiProcess: \_always: , line:4:1, endln:6:4 |vpiParent: - \_module: work@test (work@test), file:${SURELOG_DIR}/tests/PartSelectElab/dut.sv, line:1:1, endln:8:10 + \_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/PartSelectElab/dut.sv, line:1:1, endln:8:10 |vpiStmt: \_event_control: , line:4:8, endln:4:22 |vpiParent: @@ -208,14 +208,14 @@ design: (work@test) |vpiConstType:9 |vpiAlwaysType:1 |uhdmtopModules: -\_module: work@test (work@test), file:${SURELOG_DIR}/tests/PartSelectElab/dut.sv, line:1:1, endln:8:10 +\_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/PartSelectElab/dut.sv, line:1:1, endln:8:10 |vpiName:work@test |vpiDefName:work@test |vpiTop:1 |vpiNet: \_logic_net: (work@test.state), line:1:24, endln:1:29 |vpiParent: - \_module: work@test (work@test), file:${SURELOG_DIR}/tests/PartSelectElab/dut.sv, line:1:1, endln:8:10 + \_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/PartSelectElab/dut.sv, line:1:1, endln:8:10 |vpiTypespec: \_logic_typespec: , line:1:20, endln:1:23 |vpiName:state @@ -224,7 +224,7 @@ design: (work@test) |vpiNet: \_logic_net: (work@test.clk), line:1:37, endln:1:40 |vpiParent: - \_module: work@test (work@test), file:${SURELOG_DIR}/tests/PartSelectElab/dut.sv, line:1:1, endln:8:10 + \_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/PartSelectElab/dut.sv, line:1:1, endln:8:10 |vpiTypespec: \_logic_typespec: , line:1:37, endln:1:37 |vpiName:clk @@ -232,7 +232,7 @@ design: (work@test) |vpiNet: \_logic_net: (work@test.data), line:2:12, endln:2:16 |vpiParent: - \_module: work@test (work@test), file:${SURELOG_DIR}/tests/PartSelectElab/dut.sv, line:1:1, endln:8:10 + \_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/PartSelectElab/dut.sv, line:1:1, endln:8:10 |vpiTypespec: \_logic_typespec: , line:2:1, endln:2:11 |vpiRange: @@ -260,7 +260,7 @@ design: (work@test) |vpiPort: \_port: (state), line:1:24, endln:1:29 |vpiParent: - \_module: work@test (work@test), file:${SURELOG_DIR}/tests/PartSelectElab/dut.sv, line:1:1, endln:8:10 + \_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/PartSelectElab/dut.sv, line:1:1, endln:8:10 |vpiName:state |vpiDirection:2 |vpiLowConn: @@ -274,11 +274,11 @@ design: (work@test) |vpiTypedef: \_logic_typespec: , line:1:20, endln:1:23 |vpiInstance: - \_module: work@test (work@test), file:${SURELOG_DIR}/tests/PartSelectElab/dut.sv, line:1:1, endln:8:10 + \_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/PartSelectElab/dut.sv, line:1:1, endln:8:10 |vpiPort: \_port: (clk), line:1:37, endln:1:40 |vpiParent: - \_module: work@test (work@test), file:${SURELOG_DIR}/tests/PartSelectElab/dut.sv, line:1:1, endln:8:10 + \_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/PartSelectElab/dut.sv, line:1:1, endln:8:10 |vpiName:clk |vpiDirection:1 |vpiLowConn: @@ -292,11 +292,11 @@ design: (work@test) |vpiTypedef: \_logic_typespec: , line:1:37, endln:1:37 |vpiInstance: - \_module: work@test (work@test), file:${SURELOG_DIR}/tests/PartSelectElab/dut.sv, line:1:1, endln:8:10 + \_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/PartSelectElab/dut.sv, line:1:1, endln:8:10 |vpiProcess: \_always: , line:4:1, endln:6:4 |vpiParent: - \_module: work@test (work@test), file:${SURELOG_DIR}/tests/PartSelectElab/dut.sv, line:1:1, endln:8:10 + \_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/PartSelectElab/dut.sv, line:1:1, endln:8:10 |vpiStmt: \_event_control: , line:4:8, endln:4:22 |vpiParent: diff --git a/tests/PartSelectHier/PartSelectHier.log b/tests/PartSelectHier/PartSelectHier.log index 707c2eeac7..42f2be5c19 100644 --- a/tests/PartSelectHier/PartSelectHier.log +++ b/tests/PartSelectHier/PartSelectHier.log @@ -144,7 +144,7 @@ hier_path 1 logic_net 2 logic_typespec 3 logic_var 1 -module 5 +module_inst 5 package 3 part_select 1 range 4 @@ -163,7 +163,7 @@ hier_path 2 logic_net 2 logic_typespec 3 logic_var 1 -module 5 +module_inst 5 package 3 part_select 2 range 4 @@ -288,7 +288,7 @@ design: (work@dut) |vpiDefName:tlul_pkg |vpiTop:1 |uhdmallModules: -\_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/PartSelectHier/dut.sv, line:6:1, endln:10:10 +\_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/PartSelectHier/dut.sv, line:6:1, endln:10:10 |vpiParent: \_design: (work@dut) |vpiFullName:work@dut @@ -296,21 +296,21 @@ design: (work@dut) |vpiNet: \_logic_net: (work@dut.drsp_fifo_o), line:7:22, endln:7:33 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/PartSelectHier/dut.sv, line:6:1, endln:10:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/PartSelectHier/dut.sv, line:6:1, endln:10:10 |vpiName:drsp_fifo_o |vpiFullName:work@dut.drsp_fifo_o |vpiNetType:1 |vpiNet: \_logic_net: (work@dut.hfifo_rspid), line:8:15, endln:8:26 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/PartSelectHier/dut.sv, line:6:1, endln:10:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/PartSelectHier/dut.sv, line:6:1, endln:10:10 |vpiName:hfifo_rspid |vpiFullName:work@dut.hfifo_rspid |vpiNetType:36 |vpiContAssign: \_cont_assign: , line:9:10, endln:9:49 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/PartSelectHier/dut.sv, line:6:1, endln:10:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/PartSelectHier/dut.sv, line:6:1, endln:10:10 |vpiRhs: \_hier_path: (drsp_fifo_o.d_source[8:3]), line:9:24, endln:9:49 |vpiParent: @@ -348,12 +348,12 @@ design: (work@dut) |vpiActual: \_logic_var: (work@dut.hfifo_rspid), line:8:15, endln:8:26 |uhdmtopModules: -\_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/PartSelectHier/dut.sv, line:6:1, endln:10:10 +\_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/PartSelectHier/dut.sv, line:6:1, endln:10:10 |vpiName:work@dut |vpiVariables: \_logic_var: (work@dut.hfifo_rspid), line:8:15, endln:8:26 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/PartSelectHier/dut.sv, line:6:1, endln:10:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/PartSelectHier/dut.sv, line:6:1, endln:10:10 |vpiTypespec: \_logic_typespec: , line:8:3, endln:8:14 |vpiRange: @@ -400,7 +400,7 @@ design: (work@dut) |vpiNet: \_struct_net: (work@dut.drsp_fifo_o), line:7:22, endln:7:33 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/PartSelectHier/dut.sv, line:6:1, endln:10:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/PartSelectHier/dut.sv, line:6:1, endln:10:10 |vpiTypespec: \_struct_typespec: (tlul_pkg::tl_d2h_t), line:2:11, endln:2:17 |vpiName:drsp_fifo_o @@ -410,7 +410,7 @@ design: (work@dut) |vpiContAssign: \_cont_assign: , line:9:10, endln:9:49 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/PartSelectHier/dut.sv, line:6:1, endln:10:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/PartSelectHier/dut.sv, line:6:1, endln:10:10 |vpiRhs: \_hier_path: (drsp_fifo_o.d_source[8:3]), line:9:24, endln:9:49 |vpiParent: diff --git a/tests/PartSelectHierPath/PartSelectHierPath.log b/tests/PartSelectHierPath/PartSelectHierPath.log index ff27c0637a..fb4d7b4a9b 100644 --- a/tests/PartSelectHierPath/PartSelectHierPath.log +++ b/tests/PartSelectHierPath/PartSelectHierPath.log @@ -150,7 +150,7 @@ hier_path 1 import_typespec 1 logic_net 1 logic_typespec 4 -module 4 +module_inst 4 package 3 part_select 2 range 4 @@ -169,7 +169,7 @@ hier_path 2 import_typespec 1 logic_net 1 logic_typespec 4 -module 4 +module_inst 4 package 3 part_select 4 range 4 @@ -286,7 +286,7 @@ design: (work@top) |vpiTypedef: \_struct_typespec: (swerv_types::trace_pkt_t), line:3:9, endln:3:15 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/PartSelectHierPath/dut.sv, line:10:1, endln:14:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/PartSelectHierPath/dut.sv, line:10:1, endln:14:10 |vpiName:swerv_types::trace_pkt_t |vpiInstance: \_package: swerv_types (swerv_types::), file:${SURELOG_DIR}/tests/PartSelectHierPath/dut.sv, line:1:1, endln:8:11 @@ -366,7 +366,7 @@ design: (work@top) |vpiDefName:swerv_types |vpiTop:1 |uhdmallModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/PartSelectHierPath/dut.sv, line:10:1, endln:14:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/PartSelectHierPath/dut.sv, line:10:1, endln:14:10 |vpiParent: \_design: (work@top) |vpiFullName:work@top @@ -378,13 +378,13 @@ design: (work@top) |vpiNet: \_logic_net: (work@top.trace_rv_trace_pkt), line:12:16, endln:12:34 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/PartSelectHierPath/dut.sv, line:10:1, endln:14:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/PartSelectHierPath/dut.sv, line:10:1, endln:14:10 |vpiName:trace_rv_trace_pkt |vpiFullName:work@top.trace_rv_trace_pkt |vpiContAssign: \_cont_assign: , line:13:10, endln:13:84 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/PartSelectHierPath/dut.sv, line:10:1, endln:14:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/PartSelectHierPath/dut.sv, line:10:1, endln:14:10 |vpiRhs: \_hier_path: (trace_rv_trace_pkt.trace_rv_i_insn_ip[63:0]), line:13:41, endln:13:84 |vpiParent: @@ -436,7 +436,7 @@ design: (work@top) |UINT:0 |vpiConstType:9 |uhdmtopModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/PartSelectHierPath/dut.sv, line:10:1, endln:14:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/PartSelectHierPath/dut.sv, line:10:1, endln:14:10 |vpiName:work@top |vpiTypedef: \_struct_typespec: (swerv_types::trace_pkt_t), line:3:9, endln:3:15 @@ -447,7 +447,7 @@ design: (work@top) |vpiNet: \_struct_net: (work@top.trace_rv_trace_pkt), line:12:16, endln:12:34 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/PartSelectHierPath/dut.sv, line:10:1, endln:14:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/PartSelectHierPath/dut.sv, line:10:1, endln:14:10 |vpiTypespec: \_struct_typespec: (swerv_types::trace_pkt_t), line:3:9, endln:3:15 |vpiName:trace_rv_trace_pkt @@ -456,7 +456,7 @@ design: (work@top) |vpiContAssign: \_cont_assign: , line:13:10, endln:13:84 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/PartSelectHierPath/dut.sv, line:10:1, endln:14:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/PartSelectHierPath/dut.sv, line:10:1, endln:14:10 |vpiRhs: \_hier_path: (trace_rv_trace_pkt.trace_rv_i_insn_ip[63:0]), line:13:41, endln:13:84 |vpiParent: diff --git a/tests/PartSelectNoParent/PartSelectNoParent.log b/tests/PartSelectNoParent/PartSelectNoParent.log index fbe5e6c307..74ad10f722 100644 --- a/tests/PartSelectNoParent/PartSelectNoParent.log +++ b/tests/PartSelectNoParent/PartSelectNoParent.log @@ -261,7 +261,7 @@ int_typespec 31 int_var 2 logic_net 2 logic_typespec 3 -module 6 +module_inst 6 named_begin 1 operation 6 package 3 @@ -293,7 +293,7 @@ int_typespec 31 int_var 3 logic_net 2 logic_typespec 3 -module 6 +module_inst 6 named_begin 2 operation 8 package 3 @@ -599,7 +599,7 @@ design: (work@top) |vpiTypedef: \_struct_typespec: (my_pkg::hw_key_req_t), line:6:12, endln:6:18 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/PartSelectNoParent/dut.sv, line:11:1, endln:19:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/PartSelectNoParent/dut.sv, line:11:1, endln:19:10 |vpiName:my_pkg::hw_key_req_t |vpiInstance: \_package: my_pkg (my_pkg::), file:${SURELOG_DIR}/tests/PartSelectNoParent/dut.sv, line:1:1, endln:9:11 @@ -663,14 +663,14 @@ design: (work@top) |vpiDefName:my_pkg |vpiTop:1 |uhdmallModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/PartSelectNoParent/dut.sv, line:11:1, endln:19:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/PartSelectNoParent/dut.sv, line:11:1, endln:19:10 |vpiParent: \_design: (work@top) |vpiFullName:work@top |vpiParameter: \_parameter: (work@top.KeyWidth), line:3:18, endln:3:26 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/PartSelectNoParent/dut.sv, line:11:1, endln:19:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/PartSelectNoParent/dut.sv, line:11:1, endln:19:10 |UINT:256 |vpiTypespec: \_int_typespec: , line:3:14, endln:3:17 @@ -686,7 +686,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.NumRegsKey), line:4:18, endln:4:28 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/PartSelectNoParent/dut.sv, line:11:1, endln:19:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/PartSelectNoParent/dut.sv, line:11:1, endln:19:10 |UINT:8 |vpiTypespec: \_int_typespec: , line:4:14, endln:4:17 @@ -702,7 +702,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.Shares), line:2:18, endln:2:24 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/PartSelectNoParent/dut.sv, line:11:1, endln:19:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/PartSelectNoParent/dut.sv, line:11:1, endln:19:10 |UINT:2 |vpiTypespec: \_int_typespec: , line:2:14, endln:2:17 @@ -718,7 +718,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:2:18, endln:2:28 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/PartSelectNoParent/dut.sv, line:11:1, endln:19:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/PartSelectNoParent/dut.sv, line:11:1, endln:19:10 |vpiRhs: \_constant: , line:2:27, endln:2:28 |vpiParent: @@ -753,7 +753,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:3:18, endln:3:32 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/PartSelectNoParent/dut.sv, line:11:1, endln:19:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/PartSelectNoParent/dut.sv, line:11:1, endln:19:10 |vpiRhs: \_constant: , line:3:29, endln:3:32 |vpiParent: @@ -788,7 +788,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:4:18, endln:4:32 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/PartSelectNoParent/dut.sv, line:11:1, endln:19:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/PartSelectNoParent/dut.sv, line:11:1, endln:19:10 |vpiRhs: \_constant: , line:4:31, endln:4:32 |vpiParent: @@ -828,19 +828,19 @@ design: (work@top) |vpiNet: \_logic_net: (work@top.o), line:11:23, endln:11:24 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/PartSelectNoParent/dut.sv, line:11:1, endln:19:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/PartSelectNoParent/dut.sv, line:11:1, endln:19:10 |vpiName:o |vpiFullName:work@top.o |vpiNet: \_logic_net: (work@top.keymgr_key_i), line:13:17, endln:13:29 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/PartSelectNoParent/dut.sv, line:11:1, endln:19:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/PartSelectNoParent/dut.sv, line:11:1, endln:19:10 |vpiName:keymgr_key_i |vpiFullName:work@top.keymgr_key_i |vpiPort: \_port: (o), line:11:23, endln:11:24 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/PartSelectNoParent/dut.sv, line:11:1, endln:19:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/PartSelectNoParent/dut.sv, line:11:1, endln:19:10 |vpiName:o |vpiDirection:2 |vpiLowConn: @@ -853,7 +853,7 @@ design: (work@top) |vpiProcess: \_always: , line:14:4, endln:18:7 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/PartSelectNoParent/dut.sv, line:11:1, endln:19:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/PartSelectNoParent/dut.sv, line:11:1, endln:19:10 |vpiStmt: \_named_begin: (work@top.key_sideload_get), line:14:16, endln:18:7 |vpiParent: @@ -989,12 +989,12 @@ design: (work@top) \_int_var: (work@top.o), line:11:23, endln:11:24 |vpiAlwaysType:2 |uhdmtopModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/PartSelectNoParent/dut.sv, line:11:1, endln:19:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/PartSelectNoParent/dut.sv, line:11:1, endln:19:10 |vpiName:work@top |vpiVariables: \_int_var: (work@top.o), line:11:23, endln:11:24 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/PartSelectNoParent/dut.sv, line:11:1, endln:19:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/PartSelectNoParent/dut.sv, line:11:1, endln:19:10 |vpiTypespec: \_int_typespec: , line:11:19, endln:11:22 |vpiSigned:1 @@ -1005,7 +1005,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.KeyWidth), line:3:18, endln:3:26 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/PartSelectNoParent/dut.sv, line:11:1, endln:19:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/PartSelectNoParent/dut.sv, line:11:1, endln:19:10 |UINT:256 |vpiTypespec: \_int_typespec: , line:3:14, endln:3:17 @@ -1021,7 +1021,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.NumRegsKey), line:4:18, endln:4:28 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/PartSelectNoParent/dut.sv, line:11:1, endln:19:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/PartSelectNoParent/dut.sv, line:11:1, endln:19:10 |UINT:8 |vpiTypespec: \_int_typespec: , line:4:14, endln:4:17 @@ -1037,7 +1037,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.Shares), line:2:18, endln:2:24 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/PartSelectNoParent/dut.sv, line:11:1, endln:19:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/PartSelectNoParent/dut.sv, line:11:1, endln:19:10 |UINT:2 |vpiTypespec: \_int_typespec: , line:2:14, endln:2:17 @@ -1053,7 +1053,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:2:18, endln:2:28 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/PartSelectNoParent/dut.sv, line:11:1, endln:19:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/PartSelectNoParent/dut.sv, line:11:1, endln:19:10 |vpiRhs: \_constant: , line:2:27, endln:2:28 |vpiDecompile:2 @@ -1067,7 +1067,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:3:18, endln:3:32 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/PartSelectNoParent/dut.sv, line:11:1, endln:19:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/PartSelectNoParent/dut.sv, line:11:1, endln:19:10 |vpiRhs: \_constant: , line:3:29, endln:3:32 |vpiDecompile:256 @@ -1081,7 +1081,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:4:18, endln:4:32 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/PartSelectNoParent/dut.sv, line:11:1, endln:19:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/PartSelectNoParent/dut.sv, line:11:1, endln:19:10 |vpiRhs: \_constant: , line:4:31, endln:4:32 |vpiDecompile:8 @@ -1101,7 +1101,7 @@ design: (work@top) |vpiNet: \_struct_net: (work@top.keymgr_key_i), line:13:17, endln:13:29 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/PartSelectNoParent/dut.sv, line:11:1, endln:19:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/PartSelectNoParent/dut.sv, line:11:1, endln:19:10 |vpiTypespec: \_struct_typespec: (my_pkg::hw_key_req_t), line:6:12, endln:6:18 |vpiName:keymgr_key_i @@ -1110,7 +1110,7 @@ design: (work@top) |vpiPort: \_port: (o), line:11:23, endln:11:24 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/PartSelectNoParent/dut.sv, line:11:1, endln:19:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/PartSelectNoParent/dut.sv, line:11:1, endln:19:10 |vpiName:o |vpiDirection:2 |vpiLowConn: @@ -1125,11 +1125,11 @@ design: (work@top) \_int_typespec: , line:11:19, endln:11:22 |vpiSigned:1 |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/PartSelectNoParent/dut.sv, line:11:1, endln:19:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/PartSelectNoParent/dut.sv, line:11:1, endln:19:10 |vpiProcess: \_always: , line:14:4, endln:18:7 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/PartSelectNoParent/dut.sv, line:11:1, endln:19:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/PartSelectNoParent/dut.sv, line:11:1, endln:19:10 |vpiStmt: \_named_begin: (work@top.key_sideload_get), line:14:16, endln:18:7 |vpiParent: @@ -1241,7 +1241,7 @@ design: (work@top) |vpiContAssign: \_cont_assign: , line:13:17, endln:13:29 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/PartSelectNoParent/dut.sv, line:11:1, endln:19:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/PartSelectNoParent/dut.sv, line:11:1, endln:19:10 |vpiNetDeclAssign:1 |vpiRhs: \_constant: , line:13:32, endln:13:34 diff --git a/tests/PartSelectParent/PartSelectParent.log b/tests/PartSelectParent/PartSelectParent.log index baa676cb93..e8082c0856 100644 --- a/tests/PartSelectParent/PartSelectParent.log +++ b/tests/PartSelectParent/PartSelectParent.log @@ -126,7 +126,7 @@ initial 1 int_typespec 3 int_var 1 logic_net 1 -module 3 +module_inst 3 operation 3 part_select 3 port 2 @@ -144,7 +144,7 @@ initial 2 int_typespec 3 int_var 1 logic_net 1 -module 3 +module_inst 3 operation 5 part_select 5 port 3 @@ -163,7 +163,7 @@ design: (work@top) |vpiElaborated:1 |vpiName:work@top |uhdmallModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/PartSelectParent/dut.sv, line:1:1, endln:8:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/PartSelectParent/dut.sv, line:1:1, endln:8:10 |vpiParent: \_design: (work@top) |vpiFullName:work@top @@ -171,13 +171,13 @@ design: (work@top) |vpiNet: \_logic_net: (work@top.o), line:1:23, endln:1:24 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/PartSelectParent/dut.sv, line:1:1, endln:8:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/PartSelectParent/dut.sv, line:1:1, endln:8:10 |vpiName:o |vpiFullName:work@top.o |vpiPort: \_port: (o), line:1:23, endln:1:24 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/PartSelectParent/dut.sv, line:1:1, endln:8:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/PartSelectParent/dut.sv, line:1:1, endln:8:10 |vpiName:o |vpiDirection:2 |vpiLowConn: @@ -190,7 +190,7 @@ design: (work@top) |vpiProcess: \_initial: , line:2:4, endln:5:7 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/PartSelectParent/dut.sv, line:1:1, endln:8:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/PartSelectParent/dut.sv, line:1:1, endln:8:10 |vpiStmt: \_begin: (work@top), line:2:12, endln:5:7 |vpiParent: @@ -259,7 +259,7 @@ design: (work@top) |vpiContAssign: \_cont_assign: , line:7:13, endln:7:29 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/PartSelectParent/dut.sv, line:1:1, endln:8:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/PartSelectParent/dut.sv, line:1:1, endln:8:10 |vpiRhs: \_constant: , line:7:24, endln:7:29 |vpiParent: @@ -296,12 +296,12 @@ design: (work@top) |UINT:0 |vpiConstType:9 |uhdmtopModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/PartSelectParent/dut.sv, line:1:1, endln:8:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/PartSelectParent/dut.sv, line:1:1, endln:8:10 |vpiName:work@top |vpiVariables: \_int_var: (work@top.o), line:1:23, endln:1:24 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/PartSelectParent/dut.sv, line:1:1, endln:8:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/PartSelectParent/dut.sv, line:1:1, endln:8:10 |vpiTypespec: \_int_typespec: , line:1:19, endln:1:22 |vpiSigned:1 @@ -315,7 +315,7 @@ design: (work@top) |vpiPort: \_port: (o), line:1:23, endln:1:24 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/PartSelectParent/dut.sv, line:1:1, endln:8:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/PartSelectParent/dut.sv, line:1:1, endln:8:10 |vpiName:o |vpiDirection:2 |vpiLowConn: @@ -330,11 +330,11 @@ design: (work@top) \_int_typespec: , line:1:19, endln:1:22 |vpiSigned:1 |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/PartSelectParent/dut.sv, line:1:1, endln:8:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/PartSelectParent/dut.sv, line:1:1, endln:8:10 |vpiProcess: \_initial: , line:2:4, endln:5:7 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/PartSelectParent/dut.sv, line:1:1, endln:8:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/PartSelectParent/dut.sv, line:1:1, endln:8:10 |vpiStmt: \_begin: (work@top), line:2:12, endln:5:7 |vpiParent: @@ -388,7 +388,7 @@ design: (work@top) |vpiContAssign: \_cont_assign: , line:7:13, endln:7:29 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/PartSelectParent/dut.sv, line:1:1, endln:8:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/PartSelectParent/dut.sv, line:1:1, endln:8:10 |vpiRhs: \_constant: , line:7:24, endln:7:29 |vpiLhs: diff --git a/tests/PartSelectRange/PartSelectRange.log b/tests/PartSelectRange/PartSelectRange.log index 1396ddf4f8..e7580f274f 100644 --- a/tests/PartSelectRange/PartSelectRange.log +++ b/tests/PartSelectRange/PartSelectRange.log @@ -264,7 +264,7 @@ gen_scope 8 gen_scope_array 8 int_typespec 6 logic_typespec 3 -module 7 +module_inst 7 operation 15 param_assign 4 parameter 6 @@ -281,7 +281,7 @@ gen_scope 12 gen_scope_array 12 int_typespec 6 logic_typespec 3 -module 9 +module_inst 9 operation 15 param_assign 4 parameter 6 @@ -302,14 +302,14 @@ design: (work@test) |vpiElaborated:1 |vpiName:work@test |uhdmallModules: -\_module: work@test (work@test), file:${SURELOG_DIR}/tests/PartSelectRange/dut.sv, line:1:1, endln:19:10 +\_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/PartSelectRange/dut.sv, line:1:1, endln:19:10 |vpiParent: \_design: (work@test) |vpiFullName:work@test |vpiParameter: \_parameter: (work@test.MAP), line:3:19, endln:3:22 |vpiParent: - \_module: work@test (work@test), file:${SURELOG_DIR}/tests/PartSelectRange/dut.sv, line:1:1, endln:19:10 + \_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/PartSelectRange/dut.sv, line:1:1, endln:19:10 |BIN:0100 |vpiTypespec: \_int_typespec: , line:3:13, endln:3:18 @@ -338,7 +338,7 @@ design: (work@test) |vpiParameter: \_parameter: (work@test.N), line:4:13, endln:4:14 |vpiParent: - \_module: work@test (work@test), file:${SURELOG_DIR}/tests/PartSelectRange/dut.sv, line:1:1, endln:19:10 + \_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/PartSelectRange/dut.sv, line:1:1, endln:19:10 |UINT:2 |vpiTypespec: \_int_typespec: @@ -347,7 +347,7 @@ design: (work@test) |vpiParamAssign: \_param_assign: , line:3:19, endln:3:33 |vpiParent: - \_module: work@test (work@test), file:${SURELOG_DIR}/tests/PartSelectRange/dut.sv, line:1:1, endln:19:10 + \_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/PartSelectRange/dut.sv, line:1:1, endln:19:10 |vpiRhs: \_constant: , line:3:25, endln:3:33 |vpiDecompile:4'b01_00 @@ -361,7 +361,7 @@ design: (work@test) |vpiParamAssign: \_param_assign: , line:4:13, endln:4:18 |vpiParent: - \_module: work@test (work@test), file:${SURELOG_DIR}/tests/PartSelectRange/dut.sv, line:1:1, endln:19:10 + \_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/PartSelectRange/dut.sv, line:1:1, endln:19:10 |vpiRhs: \_constant: , line:4:17, endln:4:18 |vpiDecompile:2 @@ -374,12 +374,12 @@ design: (work@test) \_parameter: (work@test.N), line:4:13, endln:4:14 |vpiDefName:work@test |uhdmtopModules: -\_module: work@test (work@test), file:${SURELOG_DIR}/tests/PartSelectRange/dut.sv, line:1:1, endln:19:10 +\_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/PartSelectRange/dut.sv, line:1:1, endln:19:10 |vpiName:work@test |vpiParameter: \_parameter: (work@test.MAP), line:3:19, endln:3:22 |vpiParent: - \_module: work@test (work@test), file:${SURELOG_DIR}/tests/PartSelectRange/dut.sv, line:1:1, endln:19:10 + \_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/PartSelectRange/dut.sv, line:1:1, endln:19:10 |BIN:0100 |vpiTypespec: \_int_typespec: , line:3:13, endln:3:18 @@ -410,7 +410,7 @@ design: (work@test) |vpiParameter: \_parameter: (work@test.N), line:4:13, endln:4:14 |vpiParent: - \_module: work@test (work@test), file:${SURELOG_DIR}/tests/PartSelectRange/dut.sv, line:1:1, endln:19:10 + \_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/PartSelectRange/dut.sv, line:1:1, endln:19:10 |UINT:2 |vpiTypespec: \_int_typespec: @@ -421,7 +421,7 @@ design: (work@test) |vpiParamAssign: \_param_assign: , line:3:19, endln:3:33 |vpiParent: - \_module: work@test (work@test), file:${SURELOG_DIR}/tests/PartSelectRange/dut.sv, line:1:1, endln:19:10 + \_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/PartSelectRange/dut.sv, line:1:1, endln:19:10 |vpiRhs: \_constant: , line:3:25, endln:3:33 |vpiDecompile:4'b0100 @@ -443,7 +443,7 @@ design: (work@test) |vpiParamAssign: \_param_assign: , line:4:13, endln:4:18 |vpiParent: - \_module: work@test (work@test), file:${SURELOG_DIR}/tests/PartSelectRange/dut.sv, line:1:1, endln:19:10 + \_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/PartSelectRange/dut.sv, line:1:1, endln:19:10 |vpiRhs: \_constant: , line:4:17, endln:4:18 |vpiDecompile:2 @@ -460,7 +460,7 @@ design: (work@test) |vpiGenScopeArray: \_gen_scope_array: (work@test.loop[0]), line:8:6, endln:17:9 |vpiParent: - \_module: work@test (work@test), file:${SURELOG_DIR}/tests/PartSelectRange/dut.sv, line:1:1, endln:19:10 + \_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/PartSelectRange/dut.sv, line:1:1, endln:19:10 |vpiName:loop[0] |vpiFullName:work@test.loop[0] |vpiGenScope: @@ -489,8 +489,8 @@ design: (work@test) |vpiParent: \_gen_scope_array: (work@test.loop[0].foo), line:9:2, endln:16:7 |vpiFullName:work@test.loop[0].foo - |vpiModule: - \_module: work@test.loop[0].foo::foo (work@test.loop[0].foo.i0), file:${SURELOG_DIR}/tests/PartSelectRange/dut.sv, line:11:7, endln:11:17 + |vpiModuleInst: + \_module_inst: work@test.loop[0].foo::foo (work@test.loop[0].foo.i0), file:${SURELOG_DIR}/tests/PartSelectRange/dut.sv, line:11:7, endln:11:17 |vpiParent: \_gen_scope: (work@test.loop[0].foo) |vpiName:i0 @@ -499,7 +499,7 @@ design: (work@test) |vpiGenScopeArray: \_gen_scope_array: (work@test.loop[1]), line:8:6, endln:17:9 |vpiParent: - \_module: work@test (work@test), file:${SURELOG_DIR}/tests/PartSelectRange/dut.sv, line:1:1, endln:19:10 + \_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/PartSelectRange/dut.sv, line:1:1, endln:19:10 |vpiName:loop[1] |vpiFullName:work@test.loop[1] |vpiGenScope: @@ -528,8 +528,8 @@ design: (work@test) |vpiParent: \_gen_scope_array: (work@test.loop[1].bar), line:15:7, endln:15:17 |vpiFullName:work@test.loop[1].bar - |vpiModule: - \_module: work@test.loop[1].bar::bar (work@test.loop[1].bar.i0), file:${SURELOG_DIR}/tests/PartSelectRange/dut.sv, line:15:7, endln:15:17 + |vpiModuleInst: + \_module_inst: work@test.loop[1].bar::bar (work@test.loop[1].bar.i0), file:${SURELOG_DIR}/tests/PartSelectRange/dut.sv, line:15:7, endln:15:17 |vpiParent: \_gen_scope: (work@test.loop[1].bar) |vpiName:i0 diff --git a/tests/PatAssignOp/PatAssignOp.log b/tests/PatAssignOp/PatAssignOp.log index 27c3a30044..b6ce2a1561 100644 --- a/tests/PatAssignOp/PatAssignOp.log +++ b/tests/PatAssignOp/PatAssignOp.log @@ -541,7 +541,7 @@ int_typespec 20 int_var 4 io_decl 11 logic_var 1 -module 6 +module_inst 6 operation 18 package 2 param_assign 12 @@ -570,7 +570,7 @@ int_typespec 20 int_var 4 io_decl 22 logic_var 1 -module 7 +module_inst 7 operation 18 package 2 param_assign 12 @@ -1067,14 +1067,14 @@ design: (work@top) \_int_typespec: |vpiSigned:1 |uhdmallModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/PatAssignOp/dut.sv, line:2:1, endln:16:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/PatAssignOp/dut.sv, line:2:1, endln:16:10 |vpiParent: \_design: (work@top) |vpiFullName:work@top |vpiParameter: \_parameter: (work@top.coh_noc_dims_p), line:3:14, endln:3:28 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/PatAssignOp/dut.sv, line:2:1, endln:16:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/PatAssignOp/dut.sv, line:2:1, endln:16:10 |UINT:2 |vpiTypespec: \_int_typespec: @@ -1084,7 +1084,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.coh_noc_trans_p), line:4:14, endln:4:29 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/PatAssignOp/dut.sv, line:2:1, endln:16:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/PatAssignOp/dut.sv, line:2:1, endln:16:10 |UINT:0 |vpiTypespec: \_int_typespec: @@ -1094,7 +1094,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.coh_noc_x_cord_width_p), line:5:15, endln:5:37 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/PatAssignOp/dut.sv, line:2:1, endln:16:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/PatAssignOp/dut.sv, line:2:1, endln:16:10 |UINT:10 |vpiTypespec: \_int_typespec: @@ -1104,7 +1104,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.coh_noc_y_cord_width_p), line:6:15, endln:6:37 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/PatAssignOp/dut.sv, line:2:1, endln:16:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/PatAssignOp/dut.sv, line:2:1, endln:16:10 |UINT:20 |vpiTypespec: \_int_typespec: @@ -1114,7 +1114,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.coh_noc_cord_markers_pos_p), line:7:18, endln:7:44 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/PatAssignOp/dut.sv, line:2:1, endln:16:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/PatAssignOp/dut.sv, line:2:1, endln:16:10 |vpiSize:1 |vpiTypespec: \_array_typespec: @@ -1150,14 +1150,14 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.coh_noc_cord_width_p), line:9:14, endln:9:34 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/PatAssignOp/dut.sv, line:2:1, endln:16:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/PatAssignOp/dut.sv, line:2:1, endln:16:10 |vpiLocalParam:1 |vpiName:coh_noc_cord_width_p |vpiFullName:work@top.coh_noc_cord_width_p |vpiParamAssign: \_param_assign: , line:3:14, endln:3:40 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/PatAssignOp/dut.sv, line:2:1, endln:16:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/PatAssignOp/dut.sv, line:2:1, endln:16:10 |vpiRhs: \_constant: , line:3:39, endln:3:40 |vpiDecompile:2 @@ -1171,7 +1171,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:4:14, endln:4:40 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/PatAssignOp/dut.sv, line:2:1, endln:16:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/PatAssignOp/dut.sv, line:2:1, endln:16:10 |vpiRhs: \_constant: , line:4:39, endln:4:40 |vpiDecompile:0 @@ -1185,7 +1185,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:5:15, endln:5:42 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/PatAssignOp/dut.sv, line:2:1, endln:16:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/PatAssignOp/dut.sv, line:2:1, endln:16:10 |vpiRhs: \_constant: , line:5:40, endln:5:42 |vpiDecompile:10 @@ -1199,7 +1199,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:6:15, endln:6:42 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/PatAssignOp/dut.sv, line:2:1, endln:16:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/PatAssignOp/dut.sv, line:2:1, endln:16:10 |vpiRhs: \_constant: , line:6:40, endln:6:42 |vpiDecompile:20 @@ -1213,7 +1213,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:7:18, endln:8:84 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/PatAssignOp/dut.sv, line:2:1, endln:16:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/PatAssignOp/dut.sv, line:2:1, endln:16:10 |vpiRhs: \_operation: , line:7:65, endln:8:84 |vpiOpType:32 @@ -1289,7 +1289,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:9:14, endln:9:81 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/PatAssignOp/dut.sv, line:2:1, endln:16:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/PatAssignOp/dut.sv, line:2:1, endln:16:10 |vpiRhs: \_bit_select: (coh_noc_cord_markers_pos_p), line:9:39, endln:9:81 |vpiParent: @@ -1306,12 +1306,12 @@ design: (work@top) \_parameter: (work@top.coh_noc_cord_width_p), line:9:14, endln:9:34 |vpiDefName:work@top |uhdmtopModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/PatAssignOp/dut.sv, line:2:1, endln:16:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/PatAssignOp/dut.sv, line:2:1, endln:16:10 |vpiName:work@top |vpiParameter: \_parameter: (work@top.coh_noc_dims_p), line:3:14, endln:3:28 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/PatAssignOp/dut.sv, line:2:1, endln:16:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/PatAssignOp/dut.sv, line:2:1, endln:16:10 |UINT:2 |vpiTypespec: \_int_typespec: @@ -1323,7 +1323,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.coh_noc_trans_p), line:4:14, endln:4:29 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/PatAssignOp/dut.sv, line:2:1, endln:16:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/PatAssignOp/dut.sv, line:2:1, endln:16:10 |UINT:0 |vpiTypespec: \_int_typespec: @@ -1335,7 +1335,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.coh_noc_x_cord_width_p), line:5:15, endln:5:37 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/PatAssignOp/dut.sv, line:2:1, endln:16:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/PatAssignOp/dut.sv, line:2:1, endln:16:10 |UINT:10 |vpiTypespec: \_int_typespec: @@ -1347,7 +1347,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.coh_noc_y_cord_width_p), line:6:15, endln:6:37 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/PatAssignOp/dut.sv, line:2:1, endln:16:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/PatAssignOp/dut.sv, line:2:1, endln:16:10 |UINT:20 |vpiTypespec: \_int_typespec: @@ -1359,7 +1359,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.coh_noc_cord_markers_pos_p), line:7:18, endln:7:44 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/PatAssignOp/dut.sv, line:2:1, endln:16:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/PatAssignOp/dut.sv, line:2:1, endln:16:10 |vpiSize:1 |vpiTypespec: \_array_typespec: @@ -1417,14 +1417,14 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.coh_noc_cord_width_p), line:9:14, endln:9:34 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/PatAssignOp/dut.sv, line:2:1, endln:16:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/PatAssignOp/dut.sv, line:2:1, endln:16:10 |vpiLocalParam:1 |vpiName:coh_noc_cord_width_p |vpiFullName:work@top.coh_noc_cord_width_p |vpiParamAssign: \_param_assign: , line:3:14, endln:3:40 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/PatAssignOp/dut.sv, line:2:1, endln:16:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/PatAssignOp/dut.sv, line:2:1, endln:16:10 |vpiRhs: \_constant: , line:3:39, endln:3:40 |vpiDecompile:2 @@ -1438,7 +1438,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:4:14, endln:4:40 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/PatAssignOp/dut.sv, line:2:1, endln:16:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/PatAssignOp/dut.sv, line:2:1, endln:16:10 |vpiRhs: \_constant: , line:4:39, endln:4:40 |vpiDecompile:0 @@ -1452,7 +1452,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:5:15, endln:5:42 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/PatAssignOp/dut.sv, line:2:1, endln:16:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/PatAssignOp/dut.sv, line:2:1, endln:16:10 |vpiRhs: \_constant: , line:5:40, endln:5:42 |vpiDecompile:10 @@ -1466,7 +1466,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:6:15, endln:6:42 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/PatAssignOp/dut.sv, line:2:1, endln:16:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/PatAssignOp/dut.sv, line:2:1, endln:16:10 |vpiRhs: \_constant: , line:6:40, endln:6:42 |vpiDecompile:20 @@ -1480,7 +1480,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:7:18, endln:8:84 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/PatAssignOp/dut.sv, line:2:1, endln:16:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/PatAssignOp/dut.sv, line:2:1, endln:16:10 |vpiRhs: \_operation: , line:8:9, endln:8:84 |vpiParent: @@ -1516,7 +1516,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:9:14, endln:9:81 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/PatAssignOp/dut.sv, line:2:1, endln:16:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/PatAssignOp/dut.sv, line:2:1, endln:16:10 |vpiRhs: \_constant: , line:9:39, endln:9:81 |vpiDecompile:30 @@ -1531,7 +1531,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.genblk2), line:13:2, endln:15:6 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/PatAssignOp/dut.sv, line:2:1, endln:16:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/PatAssignOp/dut.sv, line:2:1, endln:16:10 |vpiName:genblk2 |vpiFullName:work@top.genblk2 |vpiGenScope: @@ -1539,8 +1539,8 @@ design: (work@top) |vpiParent: \_gen_scope_array: (work@top.genblk2), line:13:2, endln:15:6 |vpiFullName:work@top.genblk2 - |vpiModule: - \_module: work@top.genblk2::GOOD (work@top.genblk2.good), file:${SURELOG_DIR}/tests/PatAssignOp/dut.sv, line:14:6, endln:14:18 + |vpiModuleInst: + \_module_inst: work@top.genblk2::GOOD (work@top.genblk2.good), file:${SURELOG_DIR}/tests/PatAssignOp/dut.sv, line:14:6, endln:14:18 |vpiParent: \_gen_scope: (work@top.genblk2) |vpiName:good diff --git a/tests/PatternAssignLogic/PatternAssignLogic.log b/tests/PatternAssignLogic/PatternAssignLogic.log index 47469db146..1e521f4c57 100644 --- a/tests/PatternAssignLogic/PatternAssignLogic.log +++ b/tests/PatternAssignLogic/PatternAssignLogic.log @@ -73,7 +73,7 @@ n<> u<46> t c<1> l<1:1> el<5:1> constant 7 design 1 logic_typespec 2 -module 4 +module_inst 4 operation 2 param_assign 2 parameter 2 @@ -87,7 +87,7 @@ tagged_pattern 2 constant 7 design 1 logic_typespec 2 -module 4 +module_inst 4 operation 2 param_assign 2 parameter 2 @@ -108,14 +108,14 @@ design: (work@top) |vpiElaborated:1 |vpiName:work@top |uhdmallModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/PatternAssignLogic/dut.sv, line:1:1, endln:4:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/PatternAssignLogic/dut.sv, line:1:1, endln:4:10 |vpiParent: \_design: (work@top) |vpiFullName:work@top |vpiParameter: \_parameter: (work@top.P), line:3:25, endln:3:26 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/PatternAssignLogic/dut.sv, line:1:1, endln:4:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/PatternAssignLogic/dut.sv, line:1:1, endln:4:10 |vpiTypespec: \_logic_typespec: , line:3:14, endln:3:24 |vpiParent: @@ -143,7 +143,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:3:25, endln:3:42 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/PatternAssignLogic/dut.sv, line:1:1, endln:4:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/PatternAssignLogic/dut.sv, line:1:1, endln:4:10 |vpiRhs: \_operation: , line:3:29, endln:3:42 |vpiOpType:75 @@ -162,12 +162,12 @@ design: (work@top) \_parameter: (work@top.P), line:3:25, endln:3:26 |vpiDefName:work@top |uhdmtopModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/PatternAssignLogic/dut.sv, line:1:1, endln:4:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/PatternAssignLogic/dut.sv, line:1:1, endln:4:10 |vpiName:work@top |vpiParameter: \_parameter: (work@top.P), line:3:25, endln:3:26 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/PatternAssignLogic/dut.sv, line:1:1, endln:4:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/PatternAssignLogic/dut.sv, line:1:1, endln:4:10 |vpiTypespec: \_logic_typespec: , line:3:14, endln:3:24 |vpiParent: @@ -197,7 +197,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:3:25, endln:3:42 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/PatternAssignLogic/dut.sv, line:1:1, endln:4:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/PatternAssignLogic/dut.sv, line:1:1, endln:4:10 |vpiRhs: \_constant: , line:3:29, endln:3:42 |vpiDecompile:8'd255 diff --git a/tests/PatternAssignment/PatternAssignment.log b/tests/PatternAssignment/PatternAssignment.log index 0f7001fb95..87167b5014 100644 --- a/tests/PatternAssignment/PatternAssignment.log +++ b/tests/PatternAssignment/PatternAssignment.log @@ -146,7 +146,7 @@ design 1 logic_net 2 logic_typespec 3 logic_var 1 -module 3 +module_inst 3 operation 12 ref_obj 5 string_typespec 6 @@ -164,7 +164,7 @@ design 1 logic_net 2 logic_typespec 3 logic_var 1 -module 3 +module_inst 3 operation 16 ref_obj 7 string_typespec 6 @@ -186,17 +186,17 @@ design: (work@dut) |vpiElaborated:1 |vpiName:work@dut |uhdmallModules: -\_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/PatternAssignment/dut.sv, line:1:1, endln:15:10 +\_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/PatternAssignment/dut.sv, line:1:1, endln:15:10 |vpiParent: \_design: (work@dut) |vpiFullName:work@dut |vpiTypedef: \_struct_typespec: (typedef_struct), line:3:9, endln:3:15 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/PatternAssignment/dut.sv, line:1:1, endln:15:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/PatternAssignment/dut.sv, line:1:1, endln:15:10 |vpiName:typedef_struct |vpiInstance: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/PatternAssignment/dut.sv, line:1:1, endln:15:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/PatternAssignment/dut.sv, line:1:1, endln:15:10 |vpiPacked:1 |vpiTypespecMember: \_typespec_member: (a), line:4:9, endln:4:10 @@ -230,20 +230,20 @@ design: (work@dut) |vpiNet: \_logic_net: (work@dut.c), line:8:16, endln:8:17 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/PatternAssignment/dut.sv, line:1:1, endln:15:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/PatternAssignment/dut.sv, line:1:1, endln:15:10 |vpiName:c |vpiFullName:work@dut.c |vpiNet: \_logic_net: (work@dut.test), line:9:7, endln:9:11 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/PatternAssignment/dut.sv, line:1:1, endln:15:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/PatternAssignment/dut.sv, line:1:1, endln:15:10 |vpiName:test |vpiFullName:work@dut.test |vpiNetType:36 |vpiContAssign: \_cont_assign: , line:10:8, endln:13:2 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/PatternAssignment/dut.sv, line:1:1, endln:15:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/PatternAssignment/dut.sv, line:1:1, endln:15:10 |vpiRhs: \_operation: , line:10:12, endln:13:2 |vpiParent: @@ -339,12 +339,12 @@ design: (work@dut) |vpiActual: \_struct_net: (work@dut.c), line:8:16, endln:8:17 |uhdmtopModules: -\_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/PatternAssignment/dut.sv, line:1:1, endln:15:10 +\_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/PatternAssignment/dut.sv, line:1:1, endln:15:10 |vpiName:work@dut |vpiVariables: \_logic_var: (work@dut.test), line:9:7, endln:9:18 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/PatternAssignment/dut.sv, line:1:1, endln:15:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/PatternAssignment/dut.sv, line:1:1, endln:15:10 |vpiTypespec: \_logic_typespec: , line:9:1, endln:9:6 |vpiName:test @@ -363,7 +363,7 @@ design: (work@dut) |vpiNet: \_struct_net: (work@dut.c), line:8:16, endln:8:17 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/PatternAssignment/dut.sv, line:1:1, endln:15:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/PatternAssignment/dut.sv, line:1:1, endln:15:10 |vpiTypespec: \_struct_typespec: (typedef_struct), line:3:9, endln:3:15 |vpiName:c @@ -372,7 +372,7 @@ design: (work@dut) |vpiContAssign: \_cont_assign: , line:10:8, endln:13:2 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/PatternAssignment/dut.sv, line:1:1, endln:15:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/PatternAssignment/dut.sv, line:1:1, endln:15:10 |vpiRhs: \_operation: , line:10:12, endln:13:2 |vpiParent: diff --git a/tests/PatternOrder/PatternOrder.log b/tests/PatternOrder/PatternOrder.log index 4b41ea9efd..0a3876ab87 100644 --- a/tests/PatternOrder/PatternOrder.log +++ b/tests/PatternOrder/PatternOrder.log @@ -124,7 +124,7 @@ design 1 int_typespec 3 logic_net 1 logic_typespec 2 -module 3 +module_inst 3 operation 7 real_typespec 2 string_typespec 6 @@ -141,7 +141,7 @@ design 1 int_typespec 3 logic_net 1 logic_typespec 2 -module 3 +module_inst 3 operation 7 real_typespec 2 string_typespec 6 @@ -163,7 +163,7 @@ design: (work@top) |vpiElaborated:1 |vpiName:work@top |uhdmallModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/PatternOrder/dut.sv, line:1:1, endln:10:16 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/PatternOrder/dut.sv, line:1:1, endln:10:16 |vpiParent: \_design: (work@top) |vpiFullName:work@top @@ -171,16 +171,16 @@ design: (work@top) |vpiNet: \_logic_net: (work@top.ABC), line:8:3, endln:8:6 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/PatternOrder/dut.sv, line:1:1, endln:10:16 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/PatternOrder/dut.sv, line:1:1, endln:10:16 |vpiName:ABC |vpiFullName:work@top.ABC |uhdmtopModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/PatternOrder/dut.sv, line:1:1, endln:10:16 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/PatternOrder/dut.sv, line:1:1, endln:10:16 |vpiName:work@top |vpiVariables: \_struct_var: (work@top.ABC), line:8:3, endln:8:57 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/PatternOrder/dut.sv, line:1:1, endln:10:16 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/PatternOrder/dut.sv, line:1:1, endln:10:16 |vpiTypespec: \_struct_typespec: , line:2:4, endln:2:10 |vpiTypespecMember: diff --git a/tests/PkgImportFunc/PkgImportFunc.log b/tests/PkgImportFunc/PkgImportFunc.log index 2009395f46..3110441817 100644 --- a/tests/PkgImportFunc/PkgImportFunc.log +++ b/tests/PkgImportFunc/PkgImportFunc.log @@ -131,7 +131,7 @@ import_typespec 2 int_typespec 13 int_var 11 logic_net 1 -module 4 +module_inst 4 package 6 param_assign 2 parameter 2 @@ -153,7 +153,7 @@ import_typespec 2 int_typespec 13 int_var 23 logic_net 1 -module 4 +module_inst 4 package 6 param_assign 2 parameter 2 @@ -536,7 +536,7 @@ design: (work@top) |vpiInstance: \_package: lc_ctrl_state_pkg (lc_ctrl_state_pkg::), file:${SURELOG_DIR}/tests/PkgImportFunc/dut.sv, line:8:1, endln:10:11 |uhdmallModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/PkgImportFunc/dut.sv, line:12:1, endln:14:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/PkgImportFunc/dut.sv, line:12:1, endln:14:10 |vpiParent: \_design: (work@top) |vpiFullName:work@top @@ -544,13 +544,13 @@ design: (work@top) |vpiNet: \_logic_net: (work@top.o), line:12:23, endln:12:24 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/PkgImportFunc/dut.sv, line:12:1, endln:14:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/PkgImportFunc/dut.sv, line:12:1, endln:14:10 |vpiName:o |vpiFullName:work@top.o |vpiPort: \_port: (o), line:12:23, endln:12:24 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/PkgImportFunc/dut.sv, line:12:1, endln:14:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/PkgImportFunc/dut.sv, line:12:1, endln:14:10 |vpiName:o |vpiDirection:2 |vpiLowConn: @@ -563,7 +563,7 @@ design: (work@top) |vpiContAssign: \_cont_assign: , line:13:11, endln:13:41 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/PkgImportFunc/dut.sv, line:12:1, endln:14:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/PkgImportFunc/dut.sv, line:12:1, endln:14:10 |vpiRhs: \_func_call: (lc_ctrl_state_pkg::get_5), line:13:15, endln:13:32 |vpiParent: @@ -580,12 +580,12 @@ design: (work@top) |vpiActual: \_int_var: (work@top.o), line:12:23, endln:12:24 |uhdmtopModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/PkgImportFunc/dut.sv, line:12:1, endln:14:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/PkgImportFunc/dut.sv, line:12:1, endln:14:10 |vpiName:work@top |vpiVariables: \_int_var: (work@top.o), line:12:23, endln:12:24 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/PkgImportFunc/dut.sv, line:12:1, endln:14:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/PkgImportFunc/dut.sv, line:12:1, endln:14:10 |vpiTypespec: \_int_typespec: , line:12:19, endln:12:22 |vpiSigned:1 @@ -599,7 +599,7 @@ design: (work@top) |vpiPort: \_port: (o), line:12:23, endln:12:24 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/PkgImportFunc/dut.sv, line:12:1, endln:14:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/PkgImportFunc/dut.sv, line:12:1, endln:14:10 |vpiName:o |vpiDirection:2 |vpiLowConn: @@ -614,11 +614,11 @@ design: (work@top) \_int_typespec: , line:12:19, endln:12:22 |vpiSigned:1 |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/PkgImportFunc/dut.sv, line:12:1, endln:14:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/PkgImportFunc/dut.sv, line:12:1, endln:14:10 |vpiContAssign: \_cont_assign: , line:13:11, endln:13:41 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/PkgImportFunc/dut.sv, line:12:1, endln:14:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/PkgImportFunc/dut.sv, line:12:1, endln:14:10 |vpiRhs: \_constant: , line:3:20, endln:3:21 |vpiParent: diff --git a/tests/PkgImportPkg/PkgImportPkg.log b/tests/PkgImportPkg/PkgImportPkg.log index dab94d4c47..5005387cf5 100644 --- a/tests/PkgImportPkg/PkgImportPkg.log +++ b/tests/PkgImportPkg/PkgImportPkg.log @@ -111,7 +111,7 @@ import_typespec 3 logic_net 2 logic_typespec 2 logic_var 1 -module 3 +module_inst 3 package 6 port 4 range 2 @@ -130,7 +130,7 @@ import_typespec 3 logic_net 2 logic_typespec 2 logic_var 1 -module 3 +module_inst 3 package 6 port 6 range 2 @@ -212,7 +212,7 @@ design: (work@otp_ctrl) |vpiTypedef: \_struct_typespec: (otp_ctrl_pkg::otp_ast_req_t), line:2:11, endln:2:17 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/PkgImportPkg/dut.sv, line:11:1, endln:17:21 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/PkgImportPkg/dut.sv, line:11:1, endln:17:21 |vpiName:otp_ctrl_pkg::otp_ast_req_t |vpiInstance: \_package: otp_ctrl_part_pkg (otp_ctrl_part_pkg::), file:${SURELOG_DIR}/tests/PkgImportPkg/dut.sv, line:7:1, endln:9:31 @@ -279,7 +279,7 @@ design: (work@otp_ctrl) |vpiDefName:otp_ctrl_part_pkg |vpiTop:1 |uhdmallModules: -\_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/PkgImportPkg/dut.sv, line:11:1, endln:17:21 +\_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/PkgImportPkg/dut.sv, line:11:1, endln:17:21 |vpiParent: \_design: (work@otp_ctrl) |vpiFullName:work@otp_ctrl @@ -291,19 +291,19 @@ design: (work@otp_ctrl) |vpiNet: \_logic_net: (work@otp_ctrl.otp_ast_pwr_seq_o), line:14:24, endln:14:41 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/PkgImportPkg/dut.sv, line:11:1, endln:17:21 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/PkgImportPkg/dut.sv, line:11:1, endln:17:21 |vpiName:otp_ast_pwr_seq_o |vpiFullName:work@otp_ctrl.otp_ast_pwr_seq_o |vpiNet: \_logic_net: (work@otp_ctrl.otp_ast_pwr_seq_h_i), line:15:24, endln:15:43 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/PkgImportPkg/dut.sv, line:11:1, endln:17:21 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/PkgImportPkg/dut.sv, line:11:1, endln:17:21 |vpiName:otp_ast_pwr_seq_h_i |vpiFullName:work@otp_ctrl.otp_ast_pwr_seq_h_i |vpiPort: \_port: (otp_ast_pwr_seq_o), line:14:24, endln:14:41 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/PkgImportPkg/dut.sv, line:11:1, endln:17:21 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/PkgImportPkg/dut.sv, line:11:1, endln:17:21 |vpiName:otp_ast_pwr_seq_o |vpiDirection:2 |vpiLowConn: @@ -315,7 +315,7 @@ design: (work@otp_ctrl) |vpiPort: \_port: (otp_ast_pwr_seq_h_i), line:15:24, endln:15:43 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/PkgImportPkg/dut.sv, line:11:1, endln:17:21 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/PkgImportPkg/dut.sv, line:11:1, endln:17:21 |vpiName:otp_ast_pwr_seq_h_i |vpiDirection:1 |vpiLowConn: @@ -326,12 +326,12 @@ design: (work@otp_ctrl) \_unsupported_typespec: (otp_ast_rsp_t), line:15:10, endln:15:23 |vpiName:otp_ast_rsp_t |uhdmtopModules: -\_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/PkgImportPkg/dut.sv, line:11:1, endln:17:21 +\_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/PkgImportPkg/dut.sv, line:11:1, endln:17:21 |vpiName:work@otp_ctrl |vpiVariables: \_logic_var: (work@otp_ctrl.otp_ast_pwr_seq_h_i), line:15:24, endln:15:43 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/PkgImportPkg/dut.sv, line:11:1, endln:17:21 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/PkgImportPkg/dut.sv, line:11:1, endln:17:21 |vpiName:otp_ast_pwr_seq_h_i |vpiFullName:work@otp_ctrl.otp_ast_pwr_seq_h_i |vpiVisibility:1 @@ -344,7 +344,7 @@ design: (work@otp_ctrl) |vpiNet: \_struct_net: (work@otp_ctrl.otp_ast_pwr_seq_o), line:14:24, endln:14:41 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/PkgImportPkg/dut.sv, line:11:1, endln:17:21 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/PkgImportPkg/dut.sv, line:11:1, endln:17:21 |vpiTypespec: \_struct_typespec: (otp_ctrl_pkg::otp_ast_req_t), line:2:11, endln:2:17 |vpiName:otp_ast_pwr_seq_o @@ -353,7 +353,7 @@ design: (work@otp_ctrl) |vpiPort: \_port: (otp_ast_pwr_seq_o), line:14:24, endln:14:41 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/PkgImportPkg/dut.sv, line:11:1, endln:17:21 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/PkgImportPkg/dut.sv, line:11:1, endln:17:21 |vpiName:otp_ast_pwr_seq_o |vpiDirection:2 |vpiLowConn: @@ -367,11 +367,11 @@ design: (work@otp_ctrl) |vpiTypedef: \_struct_typespec: (otp_ctrl_pkg::otp_ast_req_t), line:2:11, endln:2:17 |vpiInstance: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/PkgImportPkg/dut.sv, line:11:1, endln:17:21 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/PkgImportPkg/dut.sv, line:11:1, endln:17:21 |vpiPort: \_port: (otp_ast_pwr_seq_h_i), line:15:24, endln:15:43 |vpiParent: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/PkgImportPkg/dut.sv, line:11:1, endln:17:21 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/PkgImportPkg/dut.sv, line:11:1, endln:17:21 |vpiName:otp_ast_pwr_seq_h_i |vpiDirection:1 |vpiLowConn: @@ -386,7 +386,7 @@ design: (work@otp_ctrl) \_unsupported_typespec: (otp_ast_rsp_t), line:15:10, endln:15:23 |vpiName:otp_ast_rsp_t |vpiInstance: - \_module: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/PkgImportPkg/dut.sv, line:11:1, endln:17:21 + \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/PkgImportPkg/dut.sv, line:11:1, endln:17:21 =================== [ FATAL] : 0 [ SYNTAX] : 0 diff --git a/tests/PortByName/PortByName.log b/tests/PortByName/PortByName.log index 614e3cdd81..b161d5bf8a 100644 --- a/tests/PortByName/PortByName.log +++ b/tests/PortByName/PortByName.log @@ -36,7 +36,7 @@ design 1 logic_net 10 logic_typespec 13 logic_var 4 -module 7 +module_inst 7 operation 9 port 6 range 29 @@ -54,7 +54,7 @@ design 1 logic_net 10 logic_typespec 13 logic_var 4 -module 7 +module_inst 7 operation 9 port 9 range 29 @@ -73,7 +73,7 @@ design: (work@top) |vpiElaborated:1 |vpiName:work@top |uhdmallModules: -\_module: work@ibex_id_stage (work@ibex_id_stage), file:${SURELOG_DIR}/tests/PortByName/dut.sv, line:12:1, endln:20:10 +\_module_inst: work@ibex_id_stage (work@ibex_id_stage), file:${SURELOG_DIR}/tests/PortByName/dut.sv, line:12:1, endln:20:10 |vpiParent: \_design: (work@top) |vpiFullName:work@ibex_id_stage @@ -81,35 +81,35 @@ design: (work@top) |vpiNet: \_logic_net: (work@ibex_id_stage.first), line:13:39, endln:13:44 |vpiParent: - \_module: work@ibex_id_stage (work@ibex_id_stage), file:${SURELOG_DIR}/tests/PortByName/dut.sv, line:12:1, endln:20:10 + \_module_inst: work@ibex_id_stage (work@ibex_id_stage), file:${SURELOG_DIR}/tests/PortByName/dut.sv, line:12:1, endln:20:10 |vpiName:first |vpiFullName:work@ibex_id_stage.first |vpiNetType:36 |vpiNet: \_logic_net: (work@ibex_id_stage.second), line:14:39, endln:14:45 |vpiParent: - \_module: work@ibex_id_stage (work@ibex_id_stage), file:${SURELOG_DIR}/tests/PortByName/dut.sv, line:12:1, endln:20:10 + \_module_inst: work@ibex_id_stage (work@ibex_id_stage), file:${SURELOG_DIR}/tests/PortByName/dut.sv, line:12:1, endln:20:10 |vpiName:second |vpiFullName:work@ibex_id_stage.second |vpiNetType:36 |vpiNet: \_logic_net: (work@ibex_id_stage.third), line:15:39, endln:15:44 |vpiParent: - \_module: work@ibex_id_stage (work@ibex_id_stage), file:${SURELOG_DIR}/tests/PortByName/dut.sv, line:12:1, endln:20:10 + \_module_inst: work@ibex_id_stage (work@ibex_id_stage), file:${SURELOG_DIR}/tests/PortByName/dut.sv, line:12:1, endln:20:10 |vpiName:third |vpiFullName:work@ibex_id_stage.third |vpiNetType:36 |vpiNet: \_logic_net: (work@ibex_id_stage.fourth), line:17:16, endln:17:22 |vpiParent: - \_module: work@ibex_id_stage (work@ibex_id_stage), file:${SURELOG_DIR}/tests/PortByName/dut.sv, line:12:1, endln:20:10 + \_module_inst: work@ibex_id_stage (work@ibex_id_stage), file:${SURELOG_DIR}/tests/PortByName/dut.sv, line:12:1, endln:20:10 |vpiName:fourth |vpiFullName:work@ibex_id_stage.fourth |vpiNetType:36 |vpiPort: \_port: (first), line:13:39, endln:13:44 |vpiParent: - \_module: work@ibex_id_stage (work@ibex_id_stage), file:${SURELOG_DIR}/tests/PortByName/dut.sv, line:12:1, endln:20:10 + \_module_inst: work@ibex_id_stage (work@ibex_id_stage), file:${SURELOG_DIR}/tests/PortByName/dut.sv, line:12:1, endln:20:10 |vpiName:first |vpiDirection:1 |vpiLowConn: @@ -139,7 +139,7 @@ design: (work@top) |vpiPort: \_port: (second), line:14:39, endln:14:45 |vpiParent: - \_module: work@ibex_id_stage (work@ibex_id_stage), file:${SURELOG_DIR}/tests/PortByName/dut.sv, line:12:1, endln:20:10 + \_module_inst: work@ibex_id_stage (work@ibex_id_stage), file:${SURELOG_DIR}/tests/PortByName/dut.sv, line:12:1, endln:20:10 |vpiName:second |vpiDirection:1 |vpiLowConn: @@ -200,7 +200,7 @@ design: (work@top) |vpiPort: \_port: (third), line:15:39, endln:15:44 |vpiParent: - \_module: work@ibex_id_stage (work@ibex_id_stage), file:${SURELOG_DIR}/tests/PortByName/dut.sv, line:12:1, endln:20:10 + \_module_inst: work@ibex_id_stage (work@ibex_id_stage), file:${SURELOG_DIR}/tests/PortByName/dut.sv, line:12:1, endln:20:10 |vpiName:third |vpiDirection:2 |vpiLowConn: @@ -261,7 +261,7 @@ design: (work@top) |vpiContAssign: \_cont_assign: , line:18:10, endln:18:24 |vpiParent: - \_module: work@ibex_id_stage (work@ibex_id_stage), file:${SURELOG_DIR}/tests/PortByName/dut.sv, line:12:1, endln:20:10 + \_module_inst: work@ibex_id_stage (work@ibex_id_stage), file:${SURELOG_DIR}/tests/PortByName/dut.sv, line:12:1, endln:20:10 |vpiRhs: \_ref_obj: (work@ibex_id_stage.fourth), line:18:18, endln:18:24 |vpiParent: @@ -279,7 +279,7 @@ design: (work@top) |vpiActual: \_array_net: (work@top.id_stage_i.third), line:15:39, endln:15:44 |uhdmallModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/PortByName/dut.sv, line:1:1, endln:11:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/PortByName/dut.sv, line:1:1, endln:11:10 |vpiParent: \_design: (work@top) |vpiFullName:work@top @@ -287,31 +287,31 @@ design: (work@top) |vpiNet: \_logic_net: (work@top.top_second), line:2:16, endln:2:26 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/PortByName/dut.sv, line:1:1, endln:11:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/PortByName/dut.sv, line:1:1, endln:11:10 |vpiName:top_second |vpiFullName:work@top.top_second |vpiNetType:36 |vpiNet: \_logic_net: (work@top.top_third), line:3:16, endln:3:25 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/PortByName/dut.sv, line:1:1, endln:11:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/PortByName/dut.sv, line:1:1, endln:11:10 |vpiName:top_third |vpiFullName:work@top.top_third |vpiNetType:36 |vpiNet: \_logic_net: (work@top.top_first), line:4:16, endln:4:25 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/PortByName/dut.sv, line:1:1, endln:11:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/PortByName/dut.sv, line:1:1, endln:11:10 |vpiName:top_first |vpiFullName:work@top.top_first |vpiNetType:36 |uhdmtopModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/PortByName/dut.sv, line:1:1, endln:11:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/PortByName/dut.sv, line:1:1, endln:11:10 |vpiName:work@top |vpiVariables: \_array_var: (work@top.top_second), line:2:16, endln:2:29 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/PortByName/dut.sv, line:1:1, endln:11:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/PortByName/dut.sv, line:1:1, endln:11:10 |vpiSize:2 |vpiTypespec: \_array_typespec: @@ -392,7 +392,7 @@ design: (work@top) |vpiVariables: \_array_var: (work@top.top_third), line:3:16, endln:3:28 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/PortByName/dut.sv, line:1:1, endln:11:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/PortByName/dut.sv, line:1:1, endln:11:10 |vpiSize:2 |vpiTypespec: \_array_typespec: @@ -473,7 +473,7 @@ design: (work@top) |vpiVariables: \_logic_var: (work@top.top_first), line:4:16, endln:4:25 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/PortByName/dut.sv, line:1:1, endln:11:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/PortByName/dut.sv, line:1:1, endln:11:10 |vpiTypespec: \_logic_typespec: , line:4:3, endln:4:14 |vpiRange: @@ -518,16 +518,16 @@ design: (work@top) |vpiDefName:work@top |vpiTop:1 |vpiTopModule:1 - |vpiModule: - \_module: work@ibex_id_stage (work@top.id_stage_i), file:${SURELOG_DIR}/tests/PortByName/dut.sv, line:5:3, endln:9:5 + |vpiModuleInst: + \_module_inst: work@ibex_id_stage (work@top.id_stage_i), file:${SURELOG_DIR}/tests/PortByName/dut.sv, line:5:3, endln:9:5 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/PortByName/dut.sv, line:1:1, endln:11:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/PortByName/dut.sv, line:1:1, endln:11:10 |vpiName:id_stage_i |vpiFullName:work@top.id_stage_i |vpiVariables: \_array_var: (work@top.id_stage_i.fourth), line:17:16, endln:17:25 |vpiParent: - \_module: work@ibex_id_stage (work@top.id_stage_i), file:${SURELOG_DIR}/tests/PortByName/dut.sv, line:5:3, endln:9:5 + \_module_inst: work@ibex_id_stage (work@top.id_stage_i), file:${SURELOG_DIR}/tests/PortByName/dut.sv, line:5:3, endln:9:5 |vpiSize:2 |vpiTypespec: \_array_typespec: @@ -611,7 +611,7 @@ design: (work@top) |vpiNet: \_logic_net: (work@top.id_stage_i.first), line:13:39, endln:13:44 |vpiParent: - \_module: work@ibex_id_stage (work@top.id_stage_i), file:${SURELOG_DIR}/tests/PortByName/dut.sv, line:5:3, endln:9:5 + \_module_inst: work@ibex_id_stage (work@top.id_stage_i), file:${SURELOG_DIR}/tests/PortByName/dut.sv, line:5:3, endln:9:5 |vpiTypespec: \_logic_typespec: , line:13:12, endln:13:23 |vpiRange: @@ -638,7 +638,7 @@ design: (work@top) |vpiArrayNet: \_array_net: (work@top.id_stage_i.second), line:14:39, endln:14:45 |vpiParent: - \_module: work@ibex_id_stage (work@top.id_stage_i), file:${SURELOG_DIR}/tests/PortByName/dut.sv, line:5:3, endln:9:5 + \_module_inst: work@ibex_id_stage (work@top.id_stage_i), file:${SURELOG_DIR}/tests/PortByName/dut.sv, line:5:3, endln:9:5 |vpiSize:2 |vpiName:second |vpiFullName:work@top.id_stage_i.second @@ -697,7 +697,7 @@ design: (work@top) |vpiArrayNet: \_array_net: (work@top.id_stage_i.third), line:15:39, endln:15:44 |vpiParent: - \_module: work@ibex_id_stage (work@top.id_stage_i), file:${SURELOG_DIR}/tests/PortByName/dut.sv, line:5:3, endln:9:5 + \_module_inst: work@ibex_id_stage (work@top.id_stage_i), file:${SURELOG_DIR}/tests/PortByName/dut.sv, line:5:3, endln:9:5 |vpiSize:2 |vpiName:third |vpiFullName:work@top.id_stage_i.third @@ -754,11 +754,11 @@ design: (work@top) |vpiFullName:work@top.id_stage_i.third |vpiNetType:36 |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/PortByName/dut.sv, line:1:1, endln:11:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/PortByName/dut.sv, line:1:1, endln:11:10 |vpiPort: \_port: (first), line:13:39, endln:13:44 |vpiParent: - \_module: work@ibex_id_stage (work@top.id_stage_i), file:${SURELOG_DIR}/tests/PortByName/dut.sv, line:5:3, endln:9:5 + \_module_inst: work@ibex_id_stage (work@top.id_stage_i), file:${SURELOG_DIR}/tests/PortByName/dut.sv, line:5:3, endln:9:5 |vpiName:first |vpiDirection:1 |vpiHighConn: @@ -800,11 +800,11 @@ design: (work@top) |UINT:0 |vpiConstType:9 |vpiInstance: - \_module: work@ibex_id_stage (work@top.id_stage_i), file:${SURELOG_DIR}/tests/PortByName/dut.sv, line:5:3, endln:9:5 + \_module_inst: work@ibex_id_stage (work@top.id_stage_i), file:${SURELOG_DIR}/tests/PortByName/dut.sv, line:5:3, endln:9:5 |vpiPort: \_port: (second), line:14:39, endln:14:45 |vpiParent: - \_module: work@ibex_id_stage (work@top.id_stage_i), file:${SURELOG_DIR}/tests/PortByName/dut.sv, line:5:3, endln:9:5 + \_module_inst: work@ibex_id_stage (work@top.id_stage_i), file:${SURELOG_DIR}/tests/PortByName/dut.sv, line:5:3, endln:9:5 |vpiName:second |vpiDirection:1 |vpiHighConn: @@ -846,11 +846,11 @@ design: (work@top) |UINT:0 |vpiConstType:9 |vpiInstance: - \_module: work@ibex_id_stage (work@top.id_stage_i), file:${SURELOG_DIR}/tests/PortByName/dut.sv, line:5:3, endln:9:5 + \_module_inst: work@ibex_id_stage (work@top.id_stage_i), file:${SURELOG_DIR}/tests/PortByName/dut.sv, line:5:3, endln:9:5 |vpiPort: \_port: (third), line:15:39, endln:15:44 |vpiParent: - \_module: work@ibex_id_stage (work@top.id_stage_i), file:${SURELOG_DIR}/tests/PortByName/dut.sv, line:5:3, endln:9:5 + \_module_inst: work@ibex_id_stage (work@top.id_stage_i), file:${SURELOG_DIR}/tests/PortByName/dut.sv, line:5:3, endln:9:5 |vpiName:third |vpiDirection:2 |vpiHighConn: @@ -892,11 +892,11 @@ design: (work@top) |UINT:0 |vpiConstType:9 |vpiInstance: - \_module: work@ibex_id_stage (work@top.id_stage_i), file:${SURELOG_DIR}/tests/PortByName/dut.sv, line:5:3, endln:9:5 + \_module_inst: work@ibex_id_stage (work@top.id_stage_i), file:${SURELOG_DIR}/tests/PortByName/dut.sv, line:5:3, endln:9:5 |vpiContAssign: \_cont_assign: , line:18:10, endln:18:24 |vpiParent: - \_module: work@ibex_id_stage (work@top.id_stage_i), file:${SURELOG_DIR}/tests/PortByName/dut.sv, line:5:3, endln:9:5 + \_module_inst: work@ibex_id_stage (work@top.id_stage_i), file:${SURELOG_DIR}/tests/PortByName/dut.sv, line:5:3, endln:9:5 |vpiRhs: \_ref_obj: (work@top.id_stage_i.fourth), line:18:18, endln:18:24 |vpiParent: diff --git a/tests/PortComplex/PortComplex.log b/tests/PortComplex/PortComplex.log index 9e83d37753..5fe21af51e 100644 --- a/tests/PortComplex/PortComplex.log +++ b/tests/PortComplex/PortComplex.log @@ -269,7 +269,7 @@ design 1 int_typespec 2 logic_net 3 logic_typespec 16 -module 9 +module_inst 9 operation 1 package 6 packed_array_net 2 @@ -290,7 +290,7 @@ design 1 int_typespec 2 logic_net 3 logic_typespec 16 -module 9 +module_inst 9 operation 1 package 6 packed_array_net 2 @@ -834,7 +834,7 @@ design: (work@dut) |vpiDefName:dm |vpiTop:1 |uhdmallModules: -\_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/PortComplex/dut.sv, line:9:1, endln:13:10 +\_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/PortComplex/dut.sv, line:9:1, endln:13:10 |vpiParent: \_design: (work@dut) |vpiFullName:work@dut @@ -842,14 +842,14 @@ design: (work@dut) |vpiNet: \_logic_net: (work@dut.alert_tx_o), line:10:33, endln:10:43 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/PortComplex/dut.sv, line:9:1, endln:13:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/PortComplex/dut.sv, line:9:1, endln:13:10 |vpiName:alert_tx_o |vpiFullName:work@dut.alert_tx_o |vpiNetType:1 |vpiPort: \_port: (alert_tx_o), line:10:33, endln:10:43 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/PortComplex/dut.sv, line:9:1, endln:13:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/PortComplex/dut.sv, line:9:1, endln:13:10 |vpiName:alert_tx_o |vpiDirection:2 |vpiLowConn: @@ -859,14 +859,14 @@ design: (work@dut) |vpiTypedef: \_struct_typespec: (pr_pkg::alert_tx_t), line:2:11, endln:2:17 |uhdmallModules: -\_module: work@dut2 (work@dut2), file:${SURELOG_DIR}/tests/PortComplex/dut.sv, line:26:1, endln:33:10 +\_module_inst: work@dut2 (work@dut2), file:${SURELOG_DIR}/tests/PortComplex/dut.sv, line:26:1, endln:33:10 |vpiParent: \_design: (work@dut) |vpiFullName:work@dut2 |vpiParameter: \_parameter: (work@dut2.NrHarts), line:27:31, endln:27:38 |vpiParent: - \_module: work@dut2 (work@dut2), file:${SURELOG_DIR}/tests/PortComplex/dut.sv, line:26:1, endln:33:10 + \_module_inst: work@dut2 (work@dut2), file:${SURELOG_DIR}/tests/PortComplex/dut.sv, line:26:1, endln:33:10 |UINT:1 |vpiTypespec: \_int_typespec: , line:27:11, endln:27:23 @@ -877,7 +877,7 @@ design: (work@dut) |vpiParamAssign: \_param_assign: , line:27:31, endln:27:51 |vpiParent: - \_module: work@dut2 (work@dut2), file:${SURELOG_DIR}/tests/PortComplex/dut.sv, line:26:1, endln:33:10 + \_module_inst: work@dut2 (work@dut2), file:${SURELOG_DIR}/tests/PortComplex/dut.sv, line:26:1, endln:33:10 |vpiRhs: \_constant: , line:27:50, endln:27:51 |vpiDecompile:1 @@ -892,21 +892,21 @@ design: (work@dut) |vpiNet: \_logic_net: (work@dut2.hartinfo_i), line:30:44, endln:30:54 |vpiParent: - \_module: work@dut2 (work@dut2), file:${SURELOG_DIR}/tests/PortComplex/dut.sv, line:26:1, endln:33:10 + \_module_inst: work@dut2 (work@dut2), file:${SURELOG_DIR}/tests/PortComplex/dut.sv, line:26:1, endln:33:10 |vpiName:hartinfo_i |vpiFullName:work@dut2.hartinfo_i |vpiNetType:1 |vpiNet: \_logic_net: (work@dut2.hart_info_i_without_range), line:31:44, endln:31:69 |vpiParent: - \_module: work@dut2 (work@dut2), file:${SURELOG_DIR}/tests/PortComplex/dut.sv, line:26:1, endln:33:10 + \_module_inst: work@dut2 (work@dut2), file:${SURELOG_DIR}/tests/PortComplex/dut.sv, line:26:1, endln:33:10 |vpiName:hart_info_i_without_range |vpiFullName:work@dut2.hart_info_i_without_range |vpiNetType:1 |vpiPort: \_port: (hartinfo_i), line:30:44, endln:30:54 |vpiParent: - \_module: work@dut2 (work@dut2), file:${SURELOG_DIR}/tests/PortComplex/dut.sv, line:26:1, endln:33:10 + \_module_inst: work@dut2 (work@dut2), file:${SURELOG_DIR}/tests/PortComplex/dut.sv, line:26:1, endln:33:10 |vpiName:hartinfo_i |vpiDirection:1 |vpiLowConn: @@ -918,7 +918,7 @@ design: (work@dut) |vpiPort: \_port: (hart_info_i_without_range), line:31:44, endln:31:69 |vpiParent: - \_module: work@dut2 (work@dut2), file:${SURELOG_DIR}/tests/PortComplex/dut.sv, line:26:1, endln:33:10 + \_module_inst: work@dut2 (work@dut2), file:${SURELOG_DIR}/tests/PortComplex/dut.sv, line:26:1, endln:33:10 |vpiName:hart_info_i_without_range |vpiDirection:1 |vpiLowConn: @@ -928,14 +928,14 @@ design: (work@dut) |vpiTypedef: \_struct_typespec: (dm::hartinfo_t), line:16:9, endln:16:15 |uhdmtopModules: -\_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/PortComplex/dut.sv, line:9:1, endln:13:10 +\_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/PortComplex/dut.sv, line:9:1, endln:13:10 |vpiName:work@dut |vpiDefName:work@dut |vpiTop:1 |vpiNet: \_packed_array_net: (work@dut.alert_tx_o), line:10:33, endln:10:43 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/PortComplex/dut.sv, line:9:1, endln:13:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/PortComplex/dut.sv, line:9:1, endln:13:10 |vpiName:alert_tx_o |vpiFullName:work@dut.alert_tx_o |vpiNetType:1 @@ -966,7 +966,7 @@ design: (work@dut) |vpiPort: \_port: (alert_tx_o), line:10:33, endln:10:43 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/PortComplex/dut.sv, line:9:1, endln:13:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/PortComplex/dut.sv, line:9:1, endln:13:10 |vpiName:alert_tx_o |vpiDirection:2 |vpiLowConn: @@ -980,14 +980,14 @@ design: (work@dut) |vpiTypedef: \_struct_typespec: (pr_pkg::alert_tx_t), line:2:11, endln:2:17 |vpiInstance: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/PortComplex/dut.sv, line:9:1, endln:13:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/PortComplex/dut.sv, line:9:1, endln:13:10 |uhdmtopModules: -\_module: work@dut2 (work@dut2), file:${SURELOG_DIR}/tests/PortComplex/dut.sv, line:26:1, endln:33:10 +\_module_inst: work@dut2 (work@dut2), file:${SURELOG_DIR}/tests/PortComplex/dut.sv, line:26:1, endln:33:10 |vpiName:work@dut2 |vpiParameter: \_parameter: (work@dut2.NrHarts), line:27:31, endln:27:38 |vpiParent: - \_module: work@dut2 (work@dut2), file:${SURELOG_DIR}/tests/PortComplex/dut.sv, line:26:1, endln:33:10 + \_module_inst: work@dut2 (work@dut2), file:${SURELOG_DIR}/tests/PortComplex/dut.sv, line:26:1, endln:33:10 |UINT:1 |vpiTypespec: \_int_typespec: , line:27:11, endln:27:23 @@ -998,7 +998,7 @@ design: (work@dut) |vpiParamAssign: \_param_assign: , line:27:31, endln:27:51 |vpiParent: - \_module: work@dut2 (work@dut2), file:${SURELOG_DIR}/tests/PortComplex/dut.sv, line:26:1, endln:33:10 + \_module_inst: work@dut2 (work@dut2), file:${SURELOG_DIR}/tests/PortComplex/dut.sv, line:26:1, endln:33:10 |vpiRhs: \_constant: , line:27:50, endln:27:51 |vpiDecompile:1 @@ -1014,7 +1014,7 @@ design: (work@dut) |vpiNet: \_packed_array_net: (work@dut2.hartinfo_i), line:30:44, endln:30:54 |vpiParent: - \_module: work@dut2 (work@dut2), file:${SURELOG_DIR}/tests/PortComplex/dut.sv, line:26:1, endln:33:10 + \_module_inst: work@dut2 (work@dut2), file:${SURELOG_DIR}/tests/PortComplex/dut.sv, line:26:1, endln:33:10 |vpiName:hartinfo_i |vpiFullName:work@dut2.hartinfo_i |vpiNetType:1 @@ -1044,7 +1044,7 @@ design: (work@dut) |vpiNet: \_struct_net: (work@dut2.hart_info_i_without_range), line:31:44, endln:31:69 |vpiParent: - \_module: work@dut2 (work@dut2), file:${SURELOG_DIR}/tests/PortComplex/dut.sv, line:26:1, endln:33:10 + \_module_inst: work@dut2 (work@dut2), file:${SURELOG_DIR}/tests/PortComplex/dut.sv, line:26:1, endln:33:10 |vpiTypespec: \_struct_typespec: (dm::hartinfo_t), line:16:9, endln:16:15 |vpiName:hart_info_i_without_range @@ -1054,7 +1054,7 @@ design: (work@dut) |vpiPort: \_port: (hartinfo_i), line:30:44, endln:30:54 |vpiParent: - \_module: work@dut2 (work@dut2), file:${SURELOG_DIR}/tests/PortComplex/dut.sv, line:26:1, endln:33:10 + \_module_inst: work@dut2 (work@dut2), file:${SURELOG_DIR}/tests/PortComplex/dut.sv, line:26:1, endln:33:10 |vpiName:hartinfo_i |vpiDirection:1 |vpiLowConn: @@ -1068,11 +1068,11 @@ design: (work@dut) |vpiTypedef: \_struct_typespec: (dm::hartinfo_t), line:16:9, endln:16:15 |vpiInstance: - \_module: work@dut2 (work@dut2), file:${SURELOG_DIR}/tests/PortComplex/dut.sv, line:26:1, endln:33:10 + \_module_inst: work@dut2 (work@dut2), file:${SURELOG_DIR}/tests/PortComplex/dut.sv, line:26:1, endln:33:10 |vpiPort: \_port: (hart_info_i_without_range), line:31:44, endln:31:69 |vpiParent: - \_module: work@dut2 (work@dut2), file:${SURELOG_DIR}/tests/PortComplex/dut.sv, line:26:1, endln:33:10 + \_module_inst: work@dut2 (work@dut2), file:${SURELOG_DIR}/tests/PortComplex/dut.sv, line:26:1, endln:33:10 |vpiName:hart_info_i_without_range |vpiDirection:1 |vpiLowConn: @@ -1086,7 +1086,7 @@ design: (work@dut) |vpiTypedef: \_struct_typespec: (dm::hartinfo_t), line:16:9, endln:16:15 |vpiInstance: - \_module: work@dut2 (work@dut2), file:${SURELOG_DIR}/tests/PortComplex/dut.sv, line:26:1, endln:33:10 + \_module_inst: work@dut2 (work@dut2), file:${SURELOG_DIR}/tests/PortComplex/dut.sv, line:26:1, endln:33:10 =================== [ FATAL] : 0 [ SYNTAX] : 0 diff --git a/tests/PortExpr/PortExpr.log b/tests/PortExpr/PortExpr.log index c1e2205c68..e7f959856e 100644 --- a/tests/PortExpr/PortExpr.log +++ b/tests/PortExpr/PortExpr.log @@ -66,7 +66,7 @@ constant 2 design 1 logic_net 5 logic_typespec 6 -module 3 +module_inst 3 operation 1 port 6 range 1 @@ -85,7 +85,7 @@ unsupported_typespec 2 design: (work@top) |vpiName:work@top |uhdmallModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/PortExpr/dut.sv, line:1:1, endln:6:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/PortExpr/dut.sv, line:1:1, endln:6:10 |vpiParent: \_design: (work@top) |vpiFullName:work@top @@ -93,24 +93,24 @@ design: (work@top) |vpiNet: \_logic_net: (work@top.op[79]), line:4:11, endln:4:23 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/PortExpr/dut.sv, line:1:1, endln:6:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/PortExpr/dut.sv, line:1:1, endln:6:10 |vpiName:op[79] |vpiFullName:work@top.op[79] |vpiNet: \_logic_net: (work@top.op[78]), line:5:11, endln:5:23 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/PortExpr/dut.sv, line:1:1, endln:6:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/PortExpr/dut.sv, line:1:1, endln:6:10 |vpiName:op[78] |vpiFullName:work@top.op[78] |vpiPort: \_port: , line:2:4, endln:2:36 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/PortExpr/dut.sv, line:1:1, endln:6:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/PortExpr/dut.sv, line:1:1, endln:6:10 |vpiDirection:3 |vpiPort: \_port: (op[79]), line:4:11, endln:4:23 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/PortExpr/dut.sv, line:1:1, endln:6:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/PortExpr/dut.sv, line:1:1, endln:6:10 |vpiName:op[79] |vpiDirection:2 |vpiLowConn: @@ -122,7 +122,7 @@ design: (work@top) |vpiPort: \_port: (op[78]), line:5:11, endln:5:23 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/PortExpr/dut.sv, line:1:1, endln:6:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/PortExpr/dut.sv, line:1:1, endln:6:10 |vpiName:op[78] |vpiDirection:2 |vpiLowConn: @@ -132,14 +132,14 @@ design: (work@top) |vpiTypedef: \_logic_typespec: , line:5:11, endln:5:11 |uhdmtopModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/PortExpr/dut.sv, line:1:1, endln:6:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/PortExpr/dut.sv, line:1:1, endln:6:10 |vpiName:work@top |vpiDefName:work@top |vpiTop:1 |vpiNet: \_logic_net: (work@top.op[79]), line:4:11, endln:4:23 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/PortExpr/dut.sv, line:1:1, endln:6:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/PortExpr/dut.sv, line:1:1, endln:6:10 |vpiTypespec: \_logic_typespec: , line:4:11, endln:4:11 |vpiName:op[79] @@ -147,7 +147,7 @@ design: (work@top) |vpiNet: \_logic_net: (work@top.op[78]), line:5:11, endln:5:23 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/PortExpr/dut.sv, line:1:1, endln:6:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/PortExpr/dut.sv, line:1:1, endln:6:10 |vpiTypespec: \_logic_typespec: , line:5:11, endln:5:11 |vpiName:op[78] @@ -156,7 +156,7 @@ design: (work@top) |vpiPort: \_port: (op), line:2:4, endln:2:36 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/PortExpr/dut.sv, line:1:1, endln:6:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/PortExpr/dut.sv, line:1:1, endln:6:10 |vpiName:op |vpiDirection:3 |vpiLowConn: @@ -191,7 +191,7 @@ design: (work@top) |vpiPort: \_port: (op[79]), line:4:11, endln:4:23 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/PortExpr/dut.sv, line:1:1, endln:6:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/PortExpr/dut.sv, line:1:1, endln:6:10 |vpiName:op[79] |vpiDirection:2 |vpiLowConn: @@ -205,7 +205,7 @@ design: (work@top) |vpiPort: \_port: (op[78]), line:5:11, endln:5:23 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/PortExpr/dut.sv, line:1:1, endln:6:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/PortExpr/dut.sv, line:1:1, endln:6:10 |vpiName:op[78] |vpiDirection:2 |vpiLowConn: diff --git a/tests/PortInitVal/PortInitVal.log b/tests/PortInitVal/PortInitVal.log index 3da4850f9c..f7bea4aaa8 100644 --- a/tests/PortInitVal/PortInitVal.log +++ b/tests/PortInitVal/PortInitVal.log @@ -135,7 +135,7 @@ event_control 1 if_stmt 1 logic_net 6 logic_typespec 5 -module 4 +module_inst 4 port 2 ref_obj 6 === UHDM Object Stats End === @@ -152,7 +152,7 @@ event_control 2 if_stmt 2 logic_net 6 logic_typespec 5 -module 4 +module_inst 4 port 3 ref_obj 11 === UHDM Object Stats End === @@ -169,7 +169,7 @@ design: (work@dut) |vpiElaborated:1 |vpiName:work@dut |uhdmallModules: -\_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/PortInitVal/dut.sv, line:1:1, endln:9:10 +\_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/PortInitVal/dut.sv, line:1:1, endln:9:10 |vpiParent: \_design: (work@dut) |vpiFullName:work@dut @@ -177,21 +177,21 @@ design: (work@dut) |vpiNet: \_logic_net: (work@dut.a), line:2:14, endln:2:15 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/PortInitVal/dut.sv, line:1:1, endln:9:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/PortInitVal/dut.sv, line:1:1, endln:9:10 |vpiName:a |vpiFullName:work@dut.a |vpiNetType:1 |vpiNet: \_logic_net: (work@dut.b), line:1:13, endln:1:14 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/PortInitVal/dut.sv, line:1:1, endln:9:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/PortInitVal/dut.sv, line:1:1, endln:9:10 |vpiName:b |vpiFullName:work@dut.b |vpiNetType:48 |vpiPort: \_port: (b), line:1:13, endln:1:14 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/PortInitVal/dut.sv, line:1:1, endln:9:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/PortInitVal/dut.sv, line:1:1, endln:9:10 |vpiName:b |vpiDirection:2 |vpiLowConn: @@ -203,7 +203,7 @@ design: (work@dut) |vpiProcess: \_always: , line:4:9, endln:6:12 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/PortInitVal/dut.sv, line:1:1, endln:9:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/PortInitVal/dut.sv, line:1:1, endln:9:10 |vpiStmt: \_event_control: , line:4:16, endln:4:18 |vpiParent: @@ -251,7 +251,7 @@ design: (work@dut) |vpiContAssign: \_cont_assign: , line:7:11, endln:7:16 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/PortInitVal/dut.sv, line:1:1, endln:9:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/PortInitVal/dut.sv, line:1:1, endln:9:10 |vpiRhs: \_ref_obj: (work@dut.a), line:7:15, endln:7:16 |vpiParent: @@ -269,14 +269,14 @@ design: (work@dut) |vpiActual: \_logic_net: (c) |uhdmtopModules: -\_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/PortInitVal/dut.sv, line:1:1, endln:9:10 +\_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/PortInitVal/dut.sv, line:1:1, endln:9:10 |vpiName:work@dut |vpiDefName:work@dut |vpiTop:1 |vpiNet: \_logic_net: (work@dut.a), line:2:14, endln:2:15 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/PortInitVal/dut.sv, line:1:1, endln:9:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/PortInitVal/dut.sv, line:1:1, endln:9:10 |vpiTypespec: \_logic_typespec: , line:2:9, endln:2:13 |vpiName:a @@ -285,7 +285,7 @@ design: (work@dut) |vpiNet: \_logic_net: (work@dut.b), line:1:13, endln:1:14 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/PortInitVal/dut.sv, line:1:1, endln:9:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/PortInitVal/dut.sv, line:1:1, endln:9:10 |vpiTypespec: \_logic_typespec: , line:3:16, endln:3:19 |vpiName:b @@ -299,7 +299,7 @@ design: (work@dut) |vpiPort: \_port: (b), line:1:13, endln:1:14 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/PortInitVal/dut.sv, line:1:1, endln:9:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/PortInitVal/dut.sv, line:1:1, endln:9:10 |vpiName:b |vpiDirection:2 |vpiLowConn: @@ -313,11 +313,11 @@ design: (work@dut) |vpiTypedef: \_logic_typespec: , line:3:16, endln:3:19 |vpiInstance: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/PortInitVal/dut.sv, line:1:1, endln:9:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/PortInitVal/dut.sv, line:1:1, endln:9:10 |vpiProcess: \_always: , line:4:9, endln:6:12 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/PortInitVal/dut.sv, line:1:1, endln:9:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/PortInitVal/dut.sv, line:1:1, endln:9:10 |vpiStmt: \_event_control: , line:4:16, endln:4:18 |vpiParent: @@ -359,7 +359,7 @@ design: (work@dut) |vpiContAssign: \_cont_assign: , line:2:14, endln:2:15 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/PortInitVal/dut.sv, line:1:1, endln:9:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/PortInitVal/dut.sv, line:1:1, endln:9:10 |vpiNetDeclAssign:1 |vpiRhs: \_constant: , line:2:18, endln:2:19 @@ -374,7 +374,7 @@ design: (work@dut) |vpiContAssign: \_cont_assign: , line:7:11, endln:7:16 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/PortInitVal/dut.sv, line:1:1, endln:9:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/PortInitVal/dut.sv, line:1:1, endln:9:10 |vpiRhs: \_ref_obj: (work@dut.a), line:7:15, endln:7:16 |vpiParent: diff --git a/tests/PortMultiDim/PortMultiDim.log b/tests/PortMultiDim/PortMultiDim.log index f57d1acb64..1652e89a23 100644 --- a/tests/PortMultiDim/PortMultiDim.log +++ b/tests/PortMultiDim/PortMultiDim.log @@ -31,7 +31,7 @@ design 1 logic_net 3 logic_typespec 4 logic_var 1 -module 4 +module_inst 4 operation 3 part_select 1 port 2 @@ -50,7 +50,7 @@ design 1 logic_net 3 logic_typespec 4 logic_var 1 -module 4 +module_inst 4 operation 3 part_select 2 port 3 @@ -71,7 +71,7 @@ design: (work@ibex_multdiv_fast) |vpiElaborated:1 |vpiName:work@ibex_multdiv_fast |uhdmallModules: -\_module: work@ibex_multdiv_fast (work@ibex_multdiv_fast), file:${SURELOG_DIR}/tests/PortMultiDim/dut.sv, line:1:1, endln:8:10 +\_module_inst: work@ibex_multdiv_fast (work@ibex_multdiv_fast), file:${SURELOG_DIR}/tests/PortMultiDim/dut.sv, line:1:1, endln:8:10 |vpiParent: \_design: (work@ibex_multdiv_fast) |vpiFullName:work@ibex_multdiv_fast @@ -79,21 +79,21 @@ design: (work@ibex_multdiv_fast) |vpiNet: \_logic_net: (work@ibex_multdiv_fast.imd_val_q_i), line:2:24, endln:2:35 |vpiParent: - \_module: work@ibex_multdiv_fast (work@ibex_multdiv_fast), file:${SURELOG_DIR}/tests/PortMultiDim/dut.sv, line:1:1, endln:8:10 + \_module_inst: work@ibex_multdiv_fast (work@ibex_multdiv_fast), file:${SURELOG_DIR}/tests/PortMultiDim/dut.sv, line:1:1, endln:8:10 |vpiName:imd_val_q_i |vpiFullName:work@ibex_multdiv_fast.imd_val_q_i |vpiNetType:36 |vpiNet: \_logic_net: (work@ibex_multdiv_fast.op_denominator_q), line:5:16, endln:5:32 |vpiParent: - \_module: work@ibex_multdiv_fast (work@ibex_multdiv_fast), file:${SURELOG_DIR}/tests/PortMultiDim/dut.sv, line:1:1, endln:8:10 + \_module_inst: work@ibex_multdiv_fast (work@ibex_multdiv_fast), file:${SURELOG_DIR}/tests/PortMultiDim/dut.sv, line:1:1, endln:8:10 |vpiName:op_denominator_q |vpiFullName:work@ibex_multdiv_fast.op_denominator_q |vpiNetType:36 |vpiPort: \_port: (imd_val_q_i), line:2:24, endln:2:35 |vpiParent: - \_module: work@ibex_multdiv_fast (work@ibex_multdiv_fast), file:${SURELOG_DIR}/tests/PortMultiDim/dut.sv, line:1:1, endln:8:10 + \_module_inst: work@ibex_multdiv_fast (work@ibex_multdiv_fast), file:${SURELOG_DIR}/tests/PortMultiDim/dut.sv, line:1:1, endln:8:10 |vpiName:imd_val_q_i |vpiDirection:1 |vpiLowConn: @@ -154,7 +154,7 @@ design: (work@ibex_multdiv_fast) |vpiContAssign: \_cont_assign: , line:6:10, endln:6:49 |vpiParent: - \_module: work@ibex_multdiv_fast (work@ibex_multdiv_fast), file:${SURELOG_DIR}/tests/PortMultiDim/dut.sv, line:1:1, endln:8:10 + \_module_inst: work@ibex_multdiv_fast (work@ibex_multdiv_fast), file:${SURELOG_DIR}/tests/PortMultiDim/dut.sv, line:1:1, endln:8:10 |vpiRhs: \_var_select: (work@ibex_multdiv_fast.imd_val_q_i), line:6:29, endln:6:49 |vpiParent: @@ -195,12 +195,12 @@ design: (work@ibex_multdiv_fast) |vpiActual: \_logic_var: (work@ibex_multdiv_fast.op_denominator_q), line:5:16, endln:5:32 |uhdmtopModules: -\_module: work@ibex_multdiv_fast (work@ibex_multdiv_fast), file:${SURELOG_DIR}/tests/PortMultiDim/dut.sv, line:1:1, endln:8:10 +\_module_inst: work@ibex_multdiv_fast (work@ibex_multdiv_fast), file:${SURELOG_DIR}/tests/PortMultiDim/dut.sv, line:1:1, endln:8:10 |vpiName:work@ibex_multdiv_fast |vpiVariables: \_logic_var: (work@ibex_multdiv_fast.op_denominator_q), line:5:16, endln:5:32 |vpiParent: - \_module: work@ibex_multdiv_fast (work@ibex_multdiv_fast), file:${SURELOG_DIR}/tests/PortMultiDim/dut.sv, line:1:1, endln:8:10 + \_module_inst: work@ibex_multdiv_fast (work@ibex_multdiv_fast), file:${SURELOG_DIR}/tests/PortMultiDim/dut.sv, line:1:1, endln:8:10 |vpiTypespec: \_logic_typespec: , line:5:3, endln:5:15 |vpiRange: @@ -247,7 +247,7 @@ design: (work@ibex_multdiv_fast) |vpiArrayNet: \_array_net: (work@ibex_multdiv_fast.imd_val_q_i), line:2:24, endln:2:35 |vpiParent: - \_module: work@ibex_multdiv_fast (work@ibex_multdiv_fast), file:${SURELOG_DIR}/tests/PortMultiDim/dut.sv, line:1:1, endln:8:10 + \_module_inst: work@ibex_multdiv_fast (work@ibex_multdiv_fast), file:${SURELOG_DIR}/tests/PortMultiDim/dut.sv, line:1:1, endln:8:10 |vpiSize:2 |vpiName:imd_val_q_i |vpiFullName:work@ibex_multdiv_fast.imd_val_q_i @@ -307,7 +307,7 @@ design: (work@ibex_multdiv_fast) |vpiPort: \_port: (imd_val_q_i), line:2:24, endln:2:35 |vpiParent: - \_module: work@ibex_multdiv_fast (work@ibex_multdiv_fast), file:${SURELOG_DIR}/tests/PortMultiDim/dut.sv, line:1:1, endln:8:10 + \_module_inst: work@ibex_multdiv_fast (work@ibex_multdiv_fast), file:${SURELOG_DIR}/tests/PortMultiDim/dut.sv, line:1:1, endln:8:10 |vpiName:imd_val_q_i |vpiDirection:1 |vpiLowConn: @@ -341,11 +341,11 @@ design: (work@ibex_multdiv_fast) |UINT:0 |vpiConstType:9 |vpiInstance: - \_module: work@ibex_multdiv_fast (work@ibex_multdiv_fast), file:${SURELOG_DIR}/tests/PortMultiDim/dut.sv, line:1:1, endln:8:10 + \_module_inst: work@ibex_multdiv_fast (work@ibex_multdiv_fast), file:${SURELOG_DIR}/tests/PortMultiDim/dut.sv, line:1:1, endln:8:10 |vpiContAssign: \_cont_assign: , line:6:10, endln:6:49 |vpiParent: - \_module: work@ibex_multdiv_fast (work@ibex_multdiv_fast), file:${SURELOG_DIR}/tests/PortMultiDim/dut.sv, line:1:1, endln:8:10 + \_module_inst: work@ibex_multdiv_fast (work@ibex_multdiv_fast), file:${SURELOG_DIR}/tests/PortMultiDim/dut.sv, line:1:1, endln:8:10 |vpiRhs: \_var_select: (work@ibex_multdiv_fast.imd_val_q_i), line:6:29, endln:6:49 |vpiParent: diff --git a/tests/PortPackage/PortPackage.log b/tests/PortPackage/PortPackage.log index eea350de13..d024a89f14 100644 --- a/tests/PortPackage/PortPackage.log +++ b/tests/PortPackage/PortPackage.log @@ -32,7 +32,7 @@ design 1 int_typespec 2 logic_net 1 logic_typespec 4 -module 6 +module_inst 6 package 3 param_assign 2 parameter 2 @@ -51,7 +51,7 @@ design 1 int_typespec 2 logic_net 1 logic_typespec 4 -module 6 +module_inst 6 package 3 param_assign 2 parameter 2 @@ -210,14 +210,14 @@ design: (work@dm_top) |vpiDefName:dm |vpiTop:1 |uhdmallModules: -\_module: work@dm_top (work@dm_top), file:${SURELOG_DIR}/tests/PortPackage/dut.sv, line:10:1, endln:17:10 +\_module_inst: work@dm_top (work@dm_top), file:${SURELOG_DIR}/tests/PortPackage/dut.sv, line:10:1, endln:17:10 |vpiParent: \_design: (work@dm_top) |vpiFullName:work@dm_top |vpiParameter: \_parameter: (work@dm_top.NrHarts), line:11:35, endln:11:42 |vpiParent: - \_module: work@dm_top (work@dm_top), file:${SURELOG_DIR}/tests/PortPackage/dut.sv, line:10:1, endln:17:10 + \_module_inst: work@dm_top (work@dm_top), file:${SURELOG_DIR}/tests/PortPackage/dut.sv, line:10:1, endln:17:10 |UINT:1 |vpiTypespec: \_int_typespec: , line:11:15, endln:11:18 @@ -230,7 +230,7 @@ design: (work@dm_top) |vpiParamAssign: \_param_assign: , line:11:35, endln:11:55 |vpiParent: - \_module: work@dm_top (work@dm_top), file:${SURELOG_DIR}/tests/PortPackage/dut.sv, line:10:1, endln:17:10 + \_module_inst: work@dm_top (work@dm_top), file:${SURELOG_DIR}/tests/PortPackage/dut.sv, line:10:1, endln:17:10 |vpiRhs: \_constant: , line:11:54, endln:11:55 |vpiDecompile:1 @@ -245,14 +245,14 @@ design: (work@dm_top) |vpiNet: \_logic_net: (work@dm_top.hartinfo_i), line:13:35, endln:13:45 |vpiParent: - \_module: work@dm_top (work@dm_top), file:${SURELOG_DIR}/tests/PortPackage/dut.sv, line:10:1, endln:17:10 + \_module_inst: work@dm_top (work@dm_top), file:${SURELOG_DIR}/tests/PortPackage/dut.sv, line:10:1, endln:17:10 |vpiName:hartinfo_i |vpiFullName:work@dm_top.hartinfo_i |vpiNetType:1 |vpiPort: \_port: (hartinfo_i), line:13:35, endln:13:45 |vpiParent: - \_module: work@dm_top (work@dm_top), file:${SURELOG_DIR}/tests/PortPackage/dut.sv, line:10:1, endln:17:10 + \_module_inst: work@dm_top (work@dm_top), file:${SURELOG_DIR}/tests/PortPackage/dut.sv, line:10:1, endln:17:10 |vpiName:hartinfo_i |vpiDirection:3 |vpiLowConn: @@ -262,12 +262,12 @@ design: (work@dm_top) |vpiTypedef: \_struct_typespec: (dm::hartinfo_t), line:3:10, endln:3:16 |uhdmtopModules: -\_module: work@dm_top (work@dm_top), file:${SURELOG_DIR}/tests/PortPackage/dut.sv, line:10:1, endln:17:10 +\_module_inst: work@dm_top (work@dm_top), file:${SURELOG_DIR}/tests/PortPackage/dut.sv, line:10:1, endln:17:10 |vpiName:work@dm_top |vpiParameter: \_parameter: (work@dm_top.NrHarts), line:11:35, endln:11:42 |vpiParent: - \_module: work@dm_top (work@dm_top), file:${SURELOG_DIR}/tests/PortPackage/dut.sv, line:10:1, endln:17:10 + \_module_inst: work@dm_top (work@dm_top), file:${SURELOG_DIR}/tests/PortPackage/dut.sv, line:10:1, endln:17:10 |UINT:1 |vpiTypespec: \_int_typespec: , line:11:15, endln:11:18 @@ -280,7 +280,7 @@ design: (work@dm_top) |vpiParamAssign: \_param_assign: , line:11:35, endln:11:55 |vpiParent: - \_module: work@dm_top (work@dm_top), file:${SURELOG_DIR}/tests/PortPackage/dut.sv, line:10:1, endln:17:10 + \_module_inst: work@dm_top (work@dm_top), file:${SURELOG_DIR}/tests/PortPackage/dut.sv, line:10:1, endln:17:10 |vpiRhs: \_constant: , line:11:54, endln:11:55 |vpiDecompile:1 @@ -296,7 +296,7 @@ design: (work@dm_top) |vpiNet: \_struct_net: (work@dm_top.hartinfo_i), line:13:35, endln:13:45 |vpiParent: - \_module: work@dm_top (work@dm_top), file:${SURELOG_DIR}/tests/PortPackage/dut.sv, line:10:1, endln:17:10 + \_module_inst: work@dm_top (work@dm_top), file:${SURELOG_DIR}/tests/PortPackage/dut.sv, line:10:1, endln:17:10 |vpiTypespec: \_struct_typespec: (dm::hartinfo_t), line:3:10, endln:3:16 |vpiName:hartinfo_i @@ -306,7 +306,7 @@ design: (work@dm_top) |vpiPort: \_port: (hartinfo_i), line:13:35, endln:13:45 |vpiParent: - \_module: work@dm_top (work@dm_top), file:${SURELOG_DIR}/tests/PortPackage/dut.sv, line:10:1, endln:17:10 + \_module_inst: work@dm_top (work@dm_top), file:${SURELOG_DIR}/tests/PortPackage/dut.sv, line:10:1, endln:17:10 |vpiName:hartinfo_i |vpiDirection:3 |vpiLowConn: @@ -320,7 +320,7 @@ design: (work@dm_top) |vpiTypedef: \_struct_typespec: (dm::hartinfo_t), line:3:10, endln:3:16 |vpiInstance: - \_module: work@dm_top (work@dm_top), file:${SURELOG_DIR}/tests/PortPackage/dut.sv, line:10:1, endln:17:10 + \_module_inst: work@dm_top (work@dm_top), file:${SURELOG_DIR}/tests/PortPackage/dut.sv, line:10:1, endln:17:10 =================== [ FATAL] : 0 [ SYNTAX] : 0 diff --git a/tests/PortRanges/PortRanges.log b/tests/PortRanges/PortRanges.log index c181b65116..73a683c64f 100644 --- a/tests/PortRanges/PortRanges.log +++ b/tests/PortRanges/PortRanges.log @@ -486,7 +486,7 @@ io_decl 11 logic_net 16 logic_typespec 24 logic_var 1 -module 6 +module_inst 6 package 2 port 16 range 32 @@ -511,7 +511,7 @@ io_decl 22 logic_net 16 logic_typespec 24 logic_var 1 -module 6 +module_inst 6 package 2 port 24 range 32 @@ -1006,7 +1006,7 @@ design: (work@DFlipflop8Bit) \_int_typespec: |vpiSigned:1 |uhdmallModules: -\_module: work@DFlipflop8Bit (work@DFlipflop8Bit), file:${SURELOG_DIR}/tests/PortRanges/dut.sv, line:1:1, endln:9:10 +\_module_inst: work@DFlipflop8Bit (work@DFlipflop8Bit), file:${SURELOG_DIR}/tests/PortRanges/dut.sv, line:1:1, endln:9:10 |vpiParent: \_design: (work@DFlipflop8Bit) |vpiFullName:work@DFlipflop8Bit @@ -1014,33 +1014,33 @@ design: (work@DFlipflop8Bit) |vpiNet: \_logic_net: (work@DFlipflop8Bit.A1), line:1:22, endln:1:24 |vpiParent: - \_module: work@DFlipflop8Bit (work@DFlipflop8Bit), file:${SURELOG_DIR}/tests/PortRanges/dut.sv, line:1:1, endln:9:10 + \_module_inst: work@DFlipflop8Bit (work@DFlipflop8Bit), file:${SURELOG_DIR}/tests/PortRanges/dut.sv, line:1:1, endln:9:10 |vpiName:A1 |vpiFullName:work@DFlipflop8Bit.A1 |vpiNetType:1 |vpiNet: \_logic_net: (work@DFlipflop8Bit.Q1), line:1:26, endln:1:28 |vpiParent: - \_module: work@DFlipflop8Bit (work@DFlipflop8Bit), file:${SURELOG_DIR}/tests/PortRanges/dut.sv, line:1:1, endln:9:10 + \_module_inst: work@DFlipflop8Bit (work@DFlipflop8Bit), file:${SURELOG_DIR}/tests/PortRanges/dut.sv, line:1:1, endln:9:10 |vpiName:Q1 |vpiFullName:work@DFlipflop8Bit.Q1 |vpiNetType:48 |vpiNet: \_logic_net: (work@DFlipflop8Bit.A2), line:1:30, endln:1:32 |vpiParent: - \_module: work@DFlipflop8Bit (work@DFlipflop8Bit), file:${SURELOG_DIR}/tests/PortRanges/dut.sv, line:1:1, endln:9:10 + \_module_inst: work@DFlipflop8Bit (work@DFlipflop8Bit), file:${SURELOG_DIR}/tests/PortRanges/dut.sv, line:1:1, endln:9:10 |vpiName:A2 |vpiFullName:work@DFlipflop8Bit.A2 |vpiNet: \_logic_net: (work@DFlipflop8Bit.Q2), line:1:34, endln:1:36 |vpiParent: - \_module: work@DFlipflop8Bit (work@DFlipflop8Bit), file:${SURELOG_DIR}/tests/PortRanges/dut.sv, line:1:1, endln:9:10 + \_module_inst: work@DFlipflop8Bit (work@DFlipflop8Bit), file:${SURELOG_DIR}/tests/PortRanges/dut.sv, line:1:1, endln:9:10 |vpiName:Q2 |vpiFullName:work@DFlipflop8Bit.Q2 |vpiPort: \_port: (A1), line:1:22, endln:1:24 |vpiParent: - \_module: work@DFlipflop8Bit (work@DFlipflop8Bit), file:${SURELOG_DIR}/tests/PortRanges/dut.sv, line:1:1, endln:9:10 + \_module_inst: work@DFlipflop8Bit (work@DFlipflop8Bit), file:${SURELOG_DIR}/tests/PortRanges/dut.sv, line:1:1, endln:9:10 |vpiName:A1 |vpiDirection:1 |vpiLowConn: @@ -1070,7 +1070,7 @@ design: (work@DFlipflop8Bit) |vpiPort: \_port: (Q1), line:1:26, endln:1:28 |vpiParent: - \_module: work@DFlipflop8Bit (work@DFlipflop8Bit), file:${SURELOG_DIR}/tests/PortRanges/dut.sv, line:1:1, endln:9:10 + \_module_inst: work@DFlipflop8Bit (work@DFlipflop8Bit), file:${SURELOG_DIR}/tests/PortRanges/dut.sv, line:1:1, endln:9:10 |vpiName:Q1 |vpiDirection:2 |vpiLowConn: @@ -1100,7 +1100,7 @@ design: (work@DFlipflop8Bit) |vpiPort: \_port: (A2), line:1:30, endln:1:32 |vpiParent: - \_module: work@DFlipflop8Bit (work@DFlipflop8Bit), file:${SURELOG_DIR}/tests/PortRanges/dut.sv, line:1:1, endln:9:10 + \_module_inst: work@DFlipflop8Bit (work@DFlipflop8Bit), file:${SURELOG_DIR}/tests/PortRanges/dut.sv, line:1:1, endln:9:10 |vpiName:A2 |vpiDirection:1 |vpiLowConn: @@ -1130,7 +1130,7 @@ design: (work@DFlipflop8Bit) |vpiPort: \_port: (Q2), line:1:34, endln:1:36 |vpiParent: - \_module: work@DFlipflop8Bit (work@DFlipflop8Bit), file:${SURELOG_DIR}/tests/PortRanges/dut.sv, line:1:1, endln:9:10 + \_module_inst: work@DFlipflop8Bit (work@DFlipflop8Bit), file:${SURELOG_DIR}/tests/PortRanges/dut.sv, line:1:1, endln:9:10 |vpiName:Q2 |vpiDirection:2 |vpiLowConn: @@ -1158,7 +1158,7 @@ design: (work@DFlipflop8Bit) |UINT:0 |vpiConstType:9 |uhdmallModules: -\_module: work@DFlipflop8Bit2 (work@DFlipflop8Bit2), file:${SURELOG_DIR}/tests/PortRanges/dut.sv, line:12:1, endln:17:10 +\_module_inst: work@DFlipflop8Bit2 (work@DFlipflop8Bit2), file:${SURELOG_DIR}/tests/PortRanges/dut.sv, line:12:1, endln:17:10 |vpiParent: \_design: (work@DFlipflop8Bit) |vpiFullName:work@DFlipflop8Bit2 @@ -1166,33 +1166,33 @@ design: (work@DFlipflop8Bit) |vpiNet: \_logic_net: (work@DFlipflop8Bit2.A3), line:12:35, endln:12:37 |vpiParent: - \_module: work@DFlipflop8Bit2 (work@DFlipflop8Bit2), file:${SURELOG_DIR}/tests/PortRanges/dut.sv, line:12:1, endln:17:10 + \_module_inst: work@DFlipflop8Bit2 (work@DFlipflop8Bit2), file:${SURELOG_DIR}/tests/PortRanges/dut.sv, line:12:1, endln:17:10 |vpiName:A3 |vpiFullName:work@DFlipflop8Bit2.A3 |vpiNet: \_logic_net: (work@DFlipflop8Bit2.A4), line:13:40, endln:13:42 |vpiParent: - \_module: work@DFlipflop8Bit2 (work@DFlipflop8Bit2), file:${SURELOG_DIR}/tests/PortRanges/dut.sv, line:12:1, endln:17:10 + \_module_inst: work@DFlipflop8Bit2 (work@DFlipflop8Bit2), file:${SURELOG_DIR}/tests/PortRanges/dut.sv, line:12:1, endln:17:10 |vpiName:A4 |vpiFullName:work@DFlipflop8Bit2.A4 |vpiNetType:1 |vpiNet: \_logic_net: (work@DFlipflop8Bit2.Q3), line:14:36, endln:14:38 |vpiParent: - \_module: work@DFlipflop8Bit2 (work@DFlipflop8Bit2), file:${SURELOG_DIR}/tests/PortRanges/dut.sv, line:12:1, endln:17:10 + \_module_inst: work@DFlipflop8Bit2 (work@DFlipflop8Bit2), file:${SURELOG_DIR}/tests/PortRanges/dut.sv, line:12:1, endln:17:10 |vpiName:Q3 |vpiFullName:work@DFlipflop8Bit2.Q3 |vpiNet: \_logic_net: (work@DFlipflop8Bit2.Q4), line:15:40, endln:15:42 |vpiParent: - \_module: work@DFlipflop8Bit2 (work@DFlipflop8Bit2), file:${SURELOG_DIR}/tests/PortRanges/dut.sv, line:12:1, endln:17:10 + \_module_inst: work@DFlipflop8Bit2 (work@DFlipflop8Bit2), file:${SURELOG_DIR}/tests/PortRanges/dut.sv, line:12:1, endln:17:10 |vpiName:Q4 |vpiFullName:work@DFlipflop8Bit2.Q4 |vpiNetType:48 |vpiPort: \_port: (A3), line:12:35, endln:12:37 |vpiParent: - \_module: work@DFlipflop8Bit2 (work@DFlipflop8Bit2), file:${SURELOG_DIR}/tests/PortRanges/dut.sv, line:12:1, endln:17:10 + \_module_inst: work@DFlipflop8Bit2 (work@DFlipflop8Bit2), file:${SURELOG_DIR}/tests/PortRanges/dut.sv, line:12:1, endln:17:10 |vpiName:A3 |vpiDirection:1 |vpiLowConn: @@ -1222,7 +1222,7 @@ design: (work@DFlipflop8Bit) |vpiPort: \_port: (A4), line:13:40, endln:13:42 |vpiParent: - \_module: work@DFlipflop8Bit2 (work@DFlipflop8Bit2), file:${SURELOG_DIR}/tests/PortRanges/dut.sv, line:12:1, endln:17:10 + \_module_inst: work@DFlipflop8Bit2 (work@DFlipflop8Bit2), file:${SURELOG_DIR}/tests/PortRanges/dut.sv, line:12:1, endln:17:10 |vpiName:A4 |vpiDirection:1 |vpiLowConn: @@ -1252,7 +1252,7 @@ design: (work@DFlipflop8Bit) |vpiPort: \_port: (Q3), line:14:36, endln:14:38 |vpiParent: - \_module: work@DFlipflop8Bit2 (work@DFlipflop8Bit2), file:${SURELOG_DIR}/tests/PortRanges/dut.sv, line:12:1, endln:17:10 + \_module_inst: work@DFlipflop8Bit2 (work@DFlipflop8Bit2), file:${SURELOG_DIR}/tests/PortRanges/dut.sv, line:12:1, endln:17:10 |vpiName:Q3 |vpiDirection:2 |vpiLowConn: @@ -1282,7 +1282,7 @@ design: (work@DFlipflop8Bit) |vpiPort: \_port: (Q4), line:15:40, endln:15:42 |vpiParent: - \_module: work@DFlipflop8Bit2 (work@DFlipflop8Bit2), file:${SURELOG_DIR}/tests/PortRanges/dut.sv, line:12:1, endln:17:10 + \_module_inst: work@DFlipflop8Bit2 (work@DFlipflop8Bit2), file:${SURELOG_DIR}/tests/PortRanges/dut.sv, line:12:1, endln:17:10 |vpiName:Q4 |vpiDirection:2 |vpiLowConn: @@ -1310,14 +1310,14 @@ design: (work@DFlipflop8Bit) |UINT:0 |vpiConstType:9 |uhdmtopModules: -\_module: work@DFlipflop8Bit (work@DFlipflop8Bit), file:${SURELOG_DIR}/tests/PortRanges/dut.sv, line:1:1, endln:9:10 +\_module_inst: work@DFlipflop8Bit (work@DFlipflop8Bit), file:${SURELOG_DIR}/tests/PortRanges/dut.sv, line:1:1, endln:9:10 |vpiName:work@DFlipflop8Bit |vpiDefName:work@DFlipflop8Bit |vpiTop:1 |vpiNet: \_logic_net: (work@DFlipflop8Bit.A1), line:1:22, endln:1:24 |vpiParent: - \_module: work@DFlipflop8Bit (work@DFlipflop8Bit), file:${SURELOG_DIR}/tests/PortRanges/dut.sv, line:1:1, endln:9:10 + \_module_inst: work@DFlipflop8Bit (work@DFlipflop8Bit), file:${SURELOG_DIR}/tests/PortRanges/dut.sv, line:1:1, endln:9:10 |vpiTypespec: \_logic_typespec: , line:4:7, endln:4:17 |vpiRange: @@ -1344,7 +1344,7 @@ design: (work@DFlipflop8Bit) |vpiNet: \_logic_net: (work@DFlipflop8Bit.Q1), line:1:26, endln:1:28 |vpiParent: - \_module: work@DFlipflop8Bit (work@DFlipflop8Bit), file:${SURELOG_DIR}/tests/PortRanges/dut.sv, line:1:1, endln:9:10 + \_module_inst: work@DFlipflop8Bit (work@DFlipflop8Bit), file:${SURELOG_DIR}/tests/PortRanges/dut.sv, line:1:1, endln:9:10 |vpiTypespec: \_logic_typespec: , line:3:8, endln:3:17 |vpiRange: @@ -1371,7 +1371,7 @@ design: (work@DFlipflop8Bit) |vpiNet: \_logic_net: (work@DFlipflop8Bit.A2), line:1:30, endln:1:32 |vpiParent: - \_module: work@DFlipflop8Bit (work@DFlipflop8Bit), file:${SURELOG_DIR}/tests/PortRanges/dut.sv, line:1:1, endln:9:10 + \_module_inst: work@DFlipflop8Bit (work@DFlipflop8Bit), file:${SURELOG_DIR}/tests/PortRanges/dut.sv, line:1:1, endln:9:10 |vpiTypespec: \_logic_typespec: , line:7:8, endln:7:13 |vpiRange: @@ -1397,7 +1397,7 @@ design: (work@DFlipflop8Bit) |vpiNet: \_logic_net: (work@DFlipflop8Bit.Q2), line:1:34, endln:1:36 |vpiParent: - \_module: work@DFlipflop8Bit (work@DFlipflop8Bit), file:${SURELOG_DIR}/tests/PortRanges/dut.sv, line:1:1, endln:9:10 + \_module_inst: work@DFlipflop8Bit (work@DFlipflop8Bit), file:${SURELOG_DIR}/tests/PortRanges/dut.sv, line:1:1, endln:9:10 |vpiTypespec: \_logic_typespec: , line:6:9, endln:6:14 |vpiRange: @@ -1424,7 +1424,7 @@ design: (work@DFlipflop8Bit) |vpiPort: \_port: (A1), line:1:22, endln:1:24 |vpiParent: - \_module: work@DFlipflop8Bit (work@DFlipflop8Bit), file:${SURELOG_DIR}/tests/PortRanges/dut.sv, line:1:1, endln:9:10 + \_module_inst: work@DFlipflop8Bit (work@DFlipflop8Bit), file:${SURELOG_DIR}/tests/PortRanges/dut.sv, line:1:1, endln:9:10 |vpiName:A1 |vpiDirection:1 |vpiLowConn: @@ -1458,11 +1458,11 @@ design: (work@DFlipflop8Bit) |UINT:0 |vpiConstType:9 |vpiInstance: - \_module: work@DFlipflop8Bit (work@DFlipflop8Bit), file:${SURELOG_DIR}/tests/PortRanges/dut.sv, line:1:1, endln:9:10 + \_module_inst: work@DFlipflop8Bit (work@DFlipflop8Bit), file:${SURELOG_DIR}/tests/PortRanges/dut.sv, line:1:1, endln:9:10 |vpiPort: \_port: (Q1), line:1:26, endln:1:28 |vpiParent: - \_module: work@DFlipflop8Bit (work@DFlipflop8Bit), file:${SURELOG_DIR}/tests/PortRanges/dut.sv, line:1:1, endln:9:10 + \_module_inst: work@DFlipflop8Bit (work@DFlipflop8Bit), file:${SURELOG_DIR}/tests/PortRanges/dut.sv, line:1:1, endln:9:10 |vpiName:Q1 |vpiDirection:2 |vpiLowConn: @@ -1496,11 +1496,11 @@ design: (work@DFlipflop8Bit) |UINT:0 |vpiConstType:9 |vpiInstance: - \_module: work@DFlipflop8Bit (work@DFlipflop8Bit), file:${SURELOG_DIR}/tests/PortRanges/dut.sv, line:1:1, endln:9:10 + \_module_inst: work@DFlipflop8Bit (work@DFlipflop8Bit), file:${SURELOG_DIR}/tests/PortRanges/dut.sv, line:1:1, endln:9:10 |vpiPort: \_port: (A2), line:1:30, endln:1:32 |vpiParent: - \_module: work@DFlipflop8Bit (work@DFlipflop8Bit), file:${SURELOG_DIR}/tests/PortRanges/dut.sv, line:1:1, endln:9:10 + \_module_inst: work@DFlipflop8Bit (work@DFlipflop8Bit), file:${SURELOG_DIR}/tests/PortRanges/dut.sv, line:1:1, endln:9:10 |vpiName:A2 |vpiDirection:1 |vpiLowConn: @@ -1534,11 +1534,11 @@ design: (work@DFlipflop8Bit) |UINT:0 |vpiConstType:9 |vpiInstance: - \_module: work@DFlipflop8Bit (work@DFlipflop8Bit), file:${SURELOG_DIR}/tests/PortRanges/dut.sv, line:1:1, endln:9:10 + \_module_inst: work@DFlipflop8Bit (work@DFlipflop8Bit), file:${SURELOG_DIR}/tests/PortRanges/dut.sv, line:1:1, endln:9:10 |vpiPort: \_port: (Q2), line:1:34, endln:1:36 |vpiParent: - \_module: work@DFlipflop8Bit (work@DFlipflop8Bit), file:${SURELOG_DIR}/tests/PortRanges/dut.sv, line:1:1, endln:9:10 + \_module_inst: work@DFlipflop8Bit (work@DFlipflop8Bit), file:${SURELOG_DIR}/tests/PortRanges/dut.sv, line:1:1, endln:9:10 |vpiName:Q2 |vpiDirection:2 |vpiLowConn: @@ -1572,16 +1572,16 @@ design: (work@DFlipflop8Bit) |UINT:0 |vpiConstType:9 |vpiInstance: - \_module: work@DFlipflop8Bit (work@DFlipflop8Bit), file:${SURELOG_DIR}/tests/PortRanges/dut.sv, line:1:1, endln:9:10 + \_module_inst: work@DFlipflop8Bit (work@DFlipflop8Bit), file:${SURELOG_DIR}/tests/PortRanges/dut.sv, line:1:1, endln:9:10 |uhdmtopModules: -\_module: work@DFlipflop8Bit2 (work@DFlipflop8Bit2), file:${SURELOG_DIR}/tests/PortRanges/dut.sv, line:12:1, endln:17:10 +\_module_inst: work@DFlipflop8Bit2 (work@DFlipflop8Bit2), file:${SURELOG_DIR}/tests/PortRanges/dut.sv, line:12:1, endln:17:10 |vpiName:work@DFlipflop8Bit2 |vpiDefName:work@DFlipflop8Bit2 |vpiTop:1 |vpiNet: \_logic_net: (work@DFlipflop8Bit2.A3), line:12:35, endln:12:37 |vpiParent: - \_module: work@DFlipflop8Bit2 (work@DFlipflop8Bit2), file:${SURELOG_DIR}/tests/PortRanges/dut.sv, line:12:1, endln:17:10 + \_module_inst: work@DFlipflop8Bit2 (work@DFlipflop8Bit2), file:${SURELOG_DIR}/tests/PortRanges/dut.sv, line:12:1, endln:17:10 |vpiTypespec: \_logic_typespec: , line:12:29, endln:12:34 |vpiRange: @@ -1607,7 +1607,7 @@ design: (work@DFlipflop8Bit) |vpiNet: \_logic_net: (work@DFlipflop8Bit2.A4), line:13:40, endln:13:42 |vpiParent: - \_module: work@DFlipflop8Bit2 (work@DFlipflop8Bit2), file:${SURELOG_DIR}/tests/PortRanges/dut.sv, line:12:1, endln:17:10 + \_module_inst: work@DFlipflop8Bit2 (work@DFlipflop8Bit2), file:${SURELOG_DIR}/tests/PortRanges/dut.sv, line:12:1, endln:17:10 |vpiTypespec: \_logic_typespec: , line:13:29, endln:13:39 |vpiRange: @@ -1634,7 +1634,7 @@ design: (work@DFlipflop8Bit) |vpiNet: \_logic_net: (work@DFlipflop8Bit2.Q3), line:14:36, endln:14:38 |vpiParent: - \_module: work@DFlipflop8Bit2 (work@DFlipflop8Bit2), file:${SURELOG_DIR}/tests/PortRanges/dut.sv, line:12:1, endln:17:10 + \_module_inst: work@DFlipflop8Bit2 (work@DFlipflop8Bit2), file:${SURELOG_DIR}/tests/PortRanges/dut.sv, line:12:1, endln:17:10 |vpiTypespec: \_logic_typespec: , line:14:30, endln:14:35 |vpiRange: @@ -1660,7 +1660,7 @@ design: (work@DFlipflop8Bit) |vpiNet: \_logic_net: (work@DFlipflop8Bit2.Q4), line:15:40, endln:15:42 |vpiParent: - \_module: work@DFlipflop8Bit2 (work@DFlipflop8Bit2), file:${SURELOG_DIR}/tests/PortRanges/dut.sv, line:12:1, endln:17:10 + \_module_inst: work@DFlipflop8Bit2 (work@DFlipflop8Bit2), file:${SURELOG_DIR}/tests/PortRanges/dut.sv, line:12:1, endln:17:10 |vpiTypespec: \_logic_typespec: , line:15:30, endln:15:39 |vpiRange: @@ -1688,7 +1688,7 @@ design: (work@DFlipflop8Bit) |vpiPort: \_port: (A3), line:12:35, endln:12:37 |vpiParent: - \_module: work@DFlipflop8Bit2 (work@DFlipflop8Bit2), file:${SURELOG_DIR}/tests/PortRanges/dut.sv, line:12:1, endln:17:10 + \_module_inst: work@DFlipflop8Bit2 (work@DFlipflop8Bit2), file:${SURELOG_DIR}/tests/PortRanges/dut.sv, line:12:1, endln:17:10 |vpiName:A3 |vpiDirection:1 |vpiLowConn: @@ -1722,11 +1722,11 @@ design: (work@DFlipflop8Bit) |UINT:0 |vpiConstType:9 |vpiInstance: - \_module: work@DFlipflop8Bit2 (work@DFlipflop8Bit2), file:${SURELOG_DIR}/tests/PortRanges/dut.sv, line:12:1, endln:17:10 + \_module_inst: work@DFlipflop8Bit2 (work@DFlipflop8Bit2), file:${SURELOG_DIR}/tests/PortRanges/dut.sv, line:12:1, endln:17:10 |vpiPort: \_port: (A4), line:13:40, endln:13:42 |vpiParent: - \_module: work@DFlipflop8Bit2 (work@DFlipflop8Bit2), file:${SURELOG_DIR}/tests/PortRanges/dut.sv, line:12:1, endln:17:10 + \_module_inst: work@DFlipflop8Bit2 (work@DFlipflop8Bit2), file:${SURELOG_DIR}/tests/PortRanges/dut.sv, line:12:1, endln:17:10 |vpiName:A4 |vpiDirection:1 |vpiLowConn: @@ -1760,11 +1760,11 @@ design: (work@DFlipflop8Bit) |UINT:0 |vpiConstType:9 |vpiInstance: - \_module: work@DFlipflop8Bit2 (work@DFlipflop8Bit2), file:${SURELOG_DIR}/tests/PortRanges/dut.sv, line:12:1, endln:17:10 + \_module_inst: work@DFlipflop8Bit2 (work@DFlipflop8Bit2), file:${SURELOG_DIR}/tests/PortRanges/dut.sv, line:12:1, endln:17:10 |vpiPort: \_port: (Q3), line:14:36, endln:14:38 |vpiParent: - \_module: work@DFlipflop8Bit2 (work@DFlipflop8Bit2), file:${SURELOG_DIR}/tests/PortRanges/dut.sv, line:12:1, endln:17:10 + \_module_inst: work@DFlipflop8Bit2 (work@DFlipflop8Bit2), file:${SURELOG_DIR}/tests/PortRanges/dut.sv, line:12:1, endln:17:10 |vpiName:Q3 |vpiDirection:2 |vpiLowConn: @@ -1798,11 +1798,11 @@ design: (work@DFlipflop8Bit) |UINT:0 |vpiConstType:9 |vpiInstance: - \_module: work@DFlipflop8Bit2 (work@DFlipflop8Bit2), file:${SURELOG_DIR}/tests/PortRanges/dut.sv, line:12:1, endln:17:10 + \_module_inst: work@DFlipflop8Bit2 (work@DFlipflop8Bit2), file:${SURELOG_DIR}/tests/PortRanges/dut.sv, line:12:1, endln:17:10 |vpiPort: \_port: (Q4), line:15:40, endln:15:42 |vpiParent: - \_module: work@DFlipflop8Bit2 (work@DFlipflop8Bit2), file:${SURELOG_DIR}/tests/PortRanges/dut.sv, line:12:1, endln:17:10 + \_module_inst: work@DFlipflop8Bit2 (work@DFlipflop8Bit2), file:${SURELOG_DIR}/tests/PortRanges/dut.sv, line:12:1, endln:17:10 |vpiName:Q4 |vpiDirection:2 |vpiLowConn: @@ -1836,7 +1836,7 @@ design: (work@DFlipflop8Bit) |UINT:0 |vpiConstType:9 |vpiInstance: - \_module: work@DFlipflop8Bit2 (work@DFlipflop8Bit2), file:${SURELOG_DIR}/tests/PortRanges/dut.sv, line:12:1, endln:17:10 + \_module_inst: work@DFlipflop8Bit2 (work@DFlipflop8Bit2), file:${SURELOG_DIR}/tests/PortRanges/dut.sv, line:12:1, endln:17:10 =================== [ FATAL] : 0 [ SYNTAX] : 0 diff --git a/tests/PortWildcard/PortWildcard.log b/tests/PortWildcard/PortWildcard.log index 671c07733b..df021baf79 100644 --- a/tests/PortWildcard/PortWildcard.log +++ b/tests/PortWildcard/PortWildcard.log @@ -461,7 +461,7 @@ io_decl 11 logic_net 15 logic_typespec 15 logic_var 1 -module 7 +module_inst 7 operation 10 package 2 param_assign 2 @@ -489,7 +489,7 @@ io_decl 22 logic_net 15 logic_typespec 15 logic_var 1 -module 7 +module_inst 7 operation 12 package 2 param_assign 2 @@ -987,7 +987,7 @@ design: (work@dut) \_int_typespec: |vpiSigned:1 |uhdmallModules: -\_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/PortWildcard/dut.sv, line:15:1, endln:21:10 +\_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/PortWildcard/dut.sv, line:15:1, endln:21:10 |vpiParent: \_design: (work@dut) |vpiFullName:work@dut @@ -995,14 +995,14 @@ design: (work@dut) |vpiNet: \_logic_net: (work@dut.rst_l), line:16:31, endln:16:36 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/PortWildcard/dut.sv, line:15:1, endln:21:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/PortWildcard/dut.sv, line:15:1, endln:21:10 |vpiName:rst_l |vpiFullName:work@dut.rst_l |vpiNetType:36 |vpiPort: \_port: (rst_l), line:16:31, endln:16:36 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/PortWildcard/dut.sv, line:15:1, endln:21:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/PortWildcard/dut.sv, line:15:1, endln:21:10 |vpiName:rst_l |vpiDirection:1 |vpiLowConn: @@ -1012,14 +1012,14 @@ design: (work@dut) |vpiTypedef: \_logic_typespec: , line:16:7, endln:16:12 |uhdmallModules: -\_module: work@rvdff (work@rvdff), file:${SURELOG_DIR}/tests/PortWildcard/dut.sv, line:3:1, endln:13:10 +\_module_inst: work@rvdff (work@rvdff), file:${SURELOG_DIR}/tests/PortWildcard/dut.sv, line:3:1, endln:13:10 |vpiParent: \_design: (work@dut) |vpiFullName:work@rvdff |vpiParameter: \_parameter: (work@rvdff.WIDTH), line:3:27, endln:3:32 |vpiParent: - \_module: work@rvdff (work@rvdff), file:${SURELOG_DIR}/tests/PortWildcard/dut.sv, line:3:1, endln:13:10 + \_module_inst: work@rvdff (work@rvdff), file:${SURELOG_DIR}/tests/PortWildcard/dut.sv, line:3:1, endln:13:10 |UINT:1 |vpiTypespec: \_int_typespec: @@ -1028,7 +1028,7 @@ design: (work@dut) |vpiParamAssign: \_param_assign: , line:3:27, endln:3:34 |vpiParent: - \_module: work@rvdff (work@rvdff), file:${SURELOG_DIR}/tests/PortWildcard/dut.sv, line:3:1, endln:13:10 + \_module_inst: work@rvdff (work@rvdff), file:${SURELOG_DIR}/tests/PortWildcard/dut.sv, line:3:1, endln:13:10 |vpiRhs: \_constant: , line:3:33, endln:3:34 |vpiDecompile:1 @@ -1043,35 +1043,35 @@ design: (work@dut) |vpiNet: \_logic_net: (work@rvdff.din), line:5:30, endln:5:33 |vpiParent: - \_module: work@rvdff (work@rvdff), file:${SURELOG_DIR}/tests/PortWildcard/dut.sv, line:3:1, endln:13:10 + \_module_inst: work@rvdff (work@rvdff), file:${SURELOG_DIR}/tests/PortWildcard/dut.sv, line:3:1, endln:13:10 |vpiName:din |vpiFullName:work@rvdff.din |vpiNetType:36 |vpiNet: \_logic_net: (work@rvdff.clk), line:6:28, endln:6:31 |vpiParent: - \_module: work@rvdff (work@rvdff), file:${SURELOG_DIR}/tests/PortWildcard/dut.sv, line:3:1, endln:13:10 + \_module_inst: work@rvdff (work@rvdff), file:${SURELOG_DIR}/tests/PortWildcard/dut.sv, line:3:1, endln:13:10 |vpiName:clk |vpiFullName:work@rvdff.clk |vpiNetType:36 |vpiNet: \_logic_net: (work@rvdff.rst_l), line:7:36, endln:7:41 |vpiParent: - \_module: work@rvdff (work@rvdff), file:${SURELOG_DIR}/tests/PortWildcard/dut.sv, line:3:1, endln:13:10 + \_module_inst: work@rvdff (work@rvdff), file:${SURELOG_DIR}/tests/PortWildcard/dut.sv, line:3:1, endln:13:10 |vpiName:rst_l |vpiFullName:work@rvdff.rst_l |vpiNetType:36 |vpiNet: \_logic_net: (work@rvdff.dout), line:9:31, endln:9:35 |vpiParent: - \_module: work@rvdff (work@rvdff), file:${SURELOG_DIR}/tests/PortWildcard/dut.sv, line:3:1, endln:13:10 + \_module_inst: work@rvdff (work@rvdff), file:${SURELOG_DIR}/tests/PortWildcard/dut.sv, line:3:1, endln:13:10 |vpiName:dout |vpiFullName:work@rvdff.dout |vpiNetType:36 |vpiPort: \_port: (din), line:5:30, endln:5:33 |vpiParent: - \_module: work@rvdff (work@rvdff), file:${SURELOG_DIR}/tests/PortWildcard/dut.sv, line:3:1, endln:13:10 + \_module_inst: work@rvdff (work@rvdff), file:${SURELOG_DIR}/tests/PortWildcard/dut.sv, line:3:1, endln:13:10 |vpiName:din |vpiDirection:1 |vpiLowConn: @@ -1111,7 +1111,7 @@ design: (work@dut) |vpiPort: \_port: (clk), line:6:28, endln:6:31 |vpiParent: - \_module: work@rvdff (work@rvdff), file:${SURELOG_DIR}/tests/PortWildcard/dut.sv, line:3:1, endln:13:10 + \_module_inst: work@rvdff (work@rvdff), file:${SURELOG_DIR}/tests/PortWildcard/dut.sv, line:3:1, endln:13:10 |vpiName:clk |vpiDirection:1 |vpiLowConn: @@ -1123,7 +1123,7 @@ design: (work@dut) |vpiPort: \_port: (rst_l), line:7:36, endln:7:41 |vpiParent: - \_module: work@rvdff (work@rvdff), file:${SURELOG_DIR}/tests/PortWildcard/dut.sv, line:3:1, endln:13:10 + \_module_inst: work@rvdff (work@rvdff), file:${SURELOG_DIR}/tests/PortWildcard/dut.sv, line:3:1, endln:13:10 |vpiName:rst_l |vpiDirection:1 |vpiLowConn: @@ -1135,7 +1135,7 @@ design: (work@dut) |vpiPort: \_port: (dout), line:9:31, endln:9:35 |vpiParent: - \_module: work@rvdff (work@rvdff), file:${SURELOG_DIR}/tests/PortWildcard/dut.sv, line:3:1, endln:13:10 + \_module_inst: work@rvdff (work@rvdff), file:${SURELOG_DIR}/tests/PortWildcard/dut.sv, line:3:1, endln:13:10 |vpiName:dout |vpiDirection:2 |vpiLowConn: @@ -1173,14 +1173,14 @@ design: (work@dut) |UINT:0 |vpiConstType:9 |uhdmtopModules: -\_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/PortWildcard/dut.sv, line:15:1, endln:21:10 +\_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/PortWildcard/dut.sv, line:15:1, endln:21:10 |vpiName:work@dut |vpiDefName:work@dut |vpiTop:1 |vpiNet: \_logic_net: (work@dut.rst_l), line:16:31, endln:16:36 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/PortWildcard/dut.sv, line:15:1, endln:21:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/PortWildcard/dut.sv, line:15:1, endln:21:10 |vpiTypespec: \_logic_typespec: , line:16:7, endln:16:12 |vpiName:rst_l @@ -1189,7 +1189,7 @@ design: (work@dut) |vpiNet: \_logic_net: (work@dut.free_clk), line:17:40, endln:17:48 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/PortWildcard/dut.sv, line:15:1, endln:21:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/PortWildcard/dut.sv, line:15:1, endln:21:10 |vpiName:free_clk |vpiFullName:work@dut.free_clk |vpiNetType:1 @@ -1213,7 +1213,7 @@ design: (work@dut) |vpiPort: \_port: (rst_l), line:16:31, endln:16:36 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/PortWildcard/dut.sv, line:15:1, endln:21:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/PortWildcard/dut.sv, line:15:1, endln:21:10 |vpiName:rst_l |vpiDirection:1 |vpiLowConn: @@ -1227,17 +1227,17 @@ design: (work@dut) |vpiTypedef: \_logic_typespec: , line:16:7, endln:16:12 |vpiInstance: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/PortWildcard/dut.sv, line:15:1, endln:21:10 - |vpiModule: - \_module: work@rvdff (work@dut.freezerfpc_ff), file:${SURELOG_DIR}/tests/PortWildcard/dut.sv, line:17:3, endln:19:77 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/PortWildcard/dut.sv, line:15:1, endln:21:10 + |vpiModuleInst: + \_module_inst: work@rvdff (work@dut.freezerfpc_ff), file:${SURELOG_DIR}/tests/PortWildcard/dut.sv, line:17:3, endln:19:77 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/PortWildcard/dut.sv, line:15:1, endln:21:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/PortWildcard/dut.sv, line:15:1, endln:21:10 |vpiName:freezerfpc_ff |vpiFullName:work@dut.freezerfpc_ff |vpiParameter: \_parameter: (work@dut.freezerfpc_ff.WIDTH), line:3:27, endln:3:32 |vpiParent: - \_module: work@rvdff (work@dut.freezerfpc_ff), file:${SURELOG_DIR}/tests/PortWildcard/dut.sv, line:17:3, endln:19:77 + \_module_inst: work@rvdff (work@dut.freezerfpc_ff), file:${SURELOG_DIR}/tests/PortWildcard/dut.sv, line:17:3, endln:19:77 |UINT:1 |vpiTypespec: \_int_typespec: @@ -1248,7 +1248,7 @@ design: (work@dut) |vpiParamAssign: \_param_assign: , line:3:27, endln:3:34 |vpiParent: - \_module: work@rvdff (work@dut.freezerfpc_ff), file:${SURELOG_DIR}/tests/PortWildcard/dut.sv, line:17:3, endln:19:77 + \_module_inst: work@rvdff (work@dut.freezerfpc_ff), file:${SURELOG_DIR}/tests/PortWildcard/dut.sv, line:17:3, endln:19:77 |vpiOverriden:1 |vpiRhs: \_constant: , line:3:33, endln:3:34 @@ -1266,7 +1266,7 @@ design: (work@dut) |vpiNet: \_logic_net: (work@dut.freezerfpc_ff.din), line:5:30, endln:5:33 |vpiParent: - \_module: work@rvdff (work@dut.freezerfpc_ff), file:${SURELOG_DIR}/tests/PortWildcard/dut.sv, line:17:3, endln:19:77 + \_module_inst: work@rvdff (work@dut.freezerfpc_ff), file:${SURELOG_DIR}/tests/PortWildcard/dut.sv, line:17:3, endln:19:77 |vpiTypespec: \_logic_typespec: , line:5:12, endln:5:29 |vpiRange: @@ -1293,7 +1293,7 @@ design: (work@dut) |vpiNet: \_logic_net: (work@dut.freezerfpc_ff.clk), line:6:28, endln:6:31 |vpiParent: - \_module: work@rvdff (work@dut.freezerfpc_ff), file:${SURELOG_DIR}/tests/PortWildcard/dut.sv, line:17:3, endln:19:77 + \_module_inst: work@rvdff (work@dut.freezerfpc_ff), file:${SURELOG_DIR}/tests/PortWildcard/dut.sv, line:17:3, endln:19:77 |vpiTypespec: \_logic_typespec: , line:6:12, endln:6:17 |vpiName:clk @@ -1302,7 +1302,7 @@ design: (work@dut) |vpiNet: \_logic_net: (work@dut.freezerfpc_ff.rst_l), line:7:36, endln:7:41 |vpiParent: - \_module: work@rvdff (work@dut.freezerfpc_ff), file:${SURELOG_DIR}/tests/PortWildcard/dut.sv, line:17:3, endln:19:77 + \_module_inst: work@rvdff (work@dut.freezerfpc_ff), file:${SURELOG_DIR}/tests/PortWildcard/dut.sv, line:17:3, endln:19:77 |vpiTypespec: \_logic_typespec: , line:7:12, endln:7:17 |vpiName:rst_l @@ -1311,7 +1311,7 @@ design: (work@dut) |vpiNet: \_logic_net: (work@dut.freezerfpc_ff.dout), line:9:31, endln:9:35 |vpiParent: - \_module: work@rvdff (work@dut.freezerfpc_ff), file:${SURELOG_DIR}/tests/PortWildcard/dut.sv, line:17:3, endln:19:77 + \_module_inst: work@rvdff (work@dut.freezerfpc_ff), file:${SURELOG_DIR}/tests/PortWildcard/dut.sv, line:17:3, endln:19:77 |vpiTypespec: \_logic_typespec: , line:9:13, endln:9:30 |vpiRange: @@ -1336,11 +1336,11 @@ design: (work@dut) |vpiFullName:work@dut.freezerfpc_ff.dout |vpiNetType:36 |vpiInstance: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/PortWildcard/dut.sv, line:15:1, endln:21:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/PortWildcard/dut.sv, line:15:1, endln:21:10 |vpiPort: \_port: (din), line:5:30, endln:5:33 |vpiParent: - \_module: work@rvdff (work@dut.freezerfpc_ff), file:${SURELOG_DIR}/tests/PortWildcard/dut.sv, line:17:3, endln:19:77 + \_module_inst: work@rvdff (work@dut.freezerfpc_ff), file:${SURELOG_DIR}/tests/PortWildcard/dut.sv, line:17:3, endln:19:77 |vpiName:din |vpiDirection:1 |vpiHighConn: @@ -1395,11 +1395,11 @@ design: (work@dut) |UINT:0 |vpiConstType:9 |vpiInstance: - \_module: work@rvdff (work@dut.freezerfpc_ff), file:${SURELOG_DIR}/tests/PortWildcard/dut.sv, line:17:3, endln:19:77 + \_module_inst: work@rvdff (work@dut.freezerfpc_ff), file:${SURELOG_DIR}/tests/PortWildcard/dut.sv, line:17:3, endln:19:77 |vpiPort: \_port: (clk), line:6:28, endln:6:31 |vpiParent: - \_module: work@rvdff (work@dut.freezerfpc_ff), file:${SURELOG_DIR}/tests/PortWildcard/dut.sv, line:17:3, endln:19:77 + \_module_inst: work@rvdff (work@dut.freezerfpc_ff), file:${SURELOG_DIR}/tests/PortWildcard/dut.sv, line:17:3, endln:19:77 |vpiName:clk |vpiDirection:1 |vpiHighConn: @@ -1421,11 +1421,11 @@ design: (work@dut) |vpiTypedef: \_logic_typespec: , line:6:12, endln:6:17 |vpiInstance: - \_module: work@rvdff (work@dut.freezerfpc_ff), file:${SURELOG_DIR}/tests/PortWildcard/dut.sv, line:17:3, endln:19:77 + \_module_inst: work@rvdff (work@dut.freezerfpc_ff), file:${SURELOG_DIR}/tests/PortWildcard/dut.sv, line:17:3, endln:19:77 |vpiPort: \_port: (rst_l), line:7:36, endln:7:41 |vpiParent: - \_module: work@rvdff (work@dut.freezerfpc_ff), file:${SURELOG_DIR}/tests/PortWildcard/dut.sv, line:17:3, endln:19:77 + \_module_inst: work@rvdff (work@dut.freezerfpc_ff), file:${SURELOG_DIR}/tests/PortWildcard/dut.sv, line:17:3, endln:19:77 |vpiName:rst_l |vpiDirection:1 |vpiHighConn: @@ -1447,11 +1447,11 @@ design: (work@dut) |vpiTypedef: \_logic_typespec: , line:7:12, endln:7:17 |vpiInstance: - \_module: work@rvdff (work@dut.freezerfpc_ff), file:${SURELOG_DIR}/tests/PortWildcard/dut.sv, line:17:3, endln:19:77 + \_module_inst: work@rvdff (work@dut.freezerfpc_ff), file:${SURELOG_DIR}/tests/PortWildcard/dut.sv, line:17:3, endln:19:77 |vpiPort: \_port: (dout), line:9:31, endln:9:35 |vpiParent: - \_module: work@rvdff (work@dut.freezerfpc_ff), file:${SURELOG_DIR}/tests/PortWildcard/dut.sv, line:17:3, endln:19:77 + \_module_inst: work@rvdff (work@dut.freezerfpc_ff), file:${SURELOG_DIR}/tests/PortWildcard/dut.sv, line:17:3, endln:19:77 |vpiName:dout |vpiDirection:2 |vpiHighConn: @@ -1506,7 +1506,7 @@ design: (work@dut) |UINT:0 |vpiConstType:9 |vpiInstance: - \_module: work@rvdff (work@dut.freezerfpc_ff), file:${SURELOG_DIR}/tests/PortWildcard/dut.sv, line:17:3, endln:19:77 + \_module_inst: work@rvdff (work@dut.freezerfpc_ff), file:${SURELOG_DIR}/tests/PortWildcard/dut.sv, line:17:3, endln:19:77 =================== [ FATAL] : 0 [ SYNTAX] : 0 diff --git a/tests/PoundDelay/PoundDelay.log b/tests/PoundDelay/PoundDelay.log index 30d2a6cf3c..ab34701bcd 100644 --- a/tests/PoundDelay/PoundDelay.log +++ b/tests/PoundDelay/PoundDelay.log @@ -24,13 +24,13 @@ === UHDM Object Stats Begin (Non-Elaborated Model) === design 1 -module 2 +module_inst 2 === UHDM Object Stats End === [INF:UH0707] Elaborating UHDM... === UHDM Object Stats Begin (Elaborated Model) === design 1 -module 2 +module_inst 2 === UHDM Object Stats End === [INF:UH0708] Writing UHDM DB: ${SURELOG_DIR}/build/regression/PoundDelay/slpp_unit/surelog.uhdm ... @@ -45,13 +45,13 @@ design: (work@top) |vpiElaborated:1 |vpiName:work@top |uhdmallModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/PoundDelay/dut.sv, line:1:1, endln:5:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/PoundDelay/dut.sv, line:1:1, endln:5:10 |vpiParent: \_design: (work@top) |vpiFullName:work@top |vpiDefName:work@top |uhdmtopModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/PoundDelay/dut.sv, line:1:1, endln:5:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/PoundDelay/dut.sv, line:1:1, endln:5:10 |vpiName:work@top |vpiDefName:work@top |vpiTop:1 diff --git a/tests/PoundDelayTask/PoundDelayTask.log b/tests/PoundDelayTask/PoundDelayTask.log index fa71d7533b..073fb4928a 100644 --- a/tests/PoundDelayTask/PoundDelayTask.log +++ b/tests/PoundDelayTask/PoundDelayTask.log @@ -76,7 +76,7 @@ constant 1 delay_control 1 design 1 initial 1 -module 2 +module_inst 2 sys_func_call 1 task 1 task_call 1 @@ -89,7 +89,7 @@ constant 1 delay_control 2 design 1 initial 2 -module 2 +module_inst 2 sys_func_call 2 task 2 task_call 2 @@ -107,7 +107,7 @@ design: (work@m) |vpiElaborated:1 |vpiName:work@m |uhdmallModules: -\_module: work@m (work@m), file:${SURELOG_DIR}/tests/PoundDelayTask/dut.sv, line:1:1, endln:9:10 +\_module_inst: work@m (work@m), file:${SURELOG_DIR}/tests/PoundDelayTask/dut.sv, line:1:1, endln:9:10 |vpiParent: \_design: (work@m) |vpiFullName:work@m @@ -115,12 +115,12 @@ design: (work@m) |vpiTaskFunc: \_task: (work@m.t), line:2:5, endln:4:12 |vpiParent: - \_module: work@m (work@m), file:${SURELOG_DIR}/tests/PoundDelayTask/dut.sv, line:1:1, endln:9:10 + \_module_inst: work@m (work@m), file:${SURELOG_DIR}/tests/PoundDelayTask/dut.sv, line:1:1, endln:9:10 |vpiName:t |vpiFullName:work@m.t |vpiVisibility:1 |vpiParent: - \_module: work@m (work@m), file:${SURELOG_DIR}/tests/PoundDelayTask/dut.sv, line:1:1, endln:9:10 + \_module_inst: work@m (work@m), file:${SURELOG_DIR}/tests/PoundDelayTask/dut.sv, line:1:1, endln:9:10 |vpiStmt: \_sys_func_call: ($display), line:3:9, endln:3:32 |vpiParent: @@ -135,11 +135,11 @@ design: (work@m) |vpiConstType:6 |vpiName:$display |vpiInstance: - \_module: work@m (work@m), file:${SURELOG_DIR}/tests/PoundDelayTask/dut.sv, line:1:1, endln:9:10 + \_module_inst: work@m (work@m), file:${SURELOG_DIR}/tests/PoundDelayTask/dut.sv, line:1:1, endln:9:10 |vpiProcess: \_initial: , line:6:5, endln:8:8 |vpiParent: - \_module: work@m (work@m), file:${SURELOG_DIR}/tests/PoundDelayTask/dut.sv, line:1:1, endln:9:10 + \_module_inst: work@m (work@m), file:${SURELOG_DIR}/tests/PoundDelayTask/dut.sv, line:1:1, endln:9:10 |vpiStmt: \_begin: (work@m), line:6:13, endln:8:8 |vpiParent: @@ -157,19 +157,19 @@ design: (work@m) |vpiTask: \_task: (work@m.t), line:2:5, endln:4:12 |uhdmtopModules: -\_module: work@m (work@m), file:${SURELOG_DIR}/tests/PoundDelayTask/dut.sv, line:1:1, endln:9:10 +\_module_inst: work@m (work@m), file:${SURELOG_DIR}/tests/PoundDelayTask/dut.sv, line:1:1, endln:9:10 |vpiName:work@m |vpiDefName:work@m |vpiTop:1 |vpiTaskFunc: \_task: (work@m.t), line:2:5, endln:4:12 |vpiParent: - \_module: work@m (work@m), file:${SURELOG_DIR}/tests/PoundDelayTask/dut.sv, line:1:1, endln:9:10 + \_module_inst: work@m (work@m), file:${SURELOG_DIR}/tests/PoundDelayTask/dut.sv, line:1:1, endln:9:10 |vpiName:t |vpiFullName:work@m.t |vpiVisibility:1 |vpiParent: - \_module: work@m (work@m), file:${SURELOG_DIR}/tests/PoundDelayTask/dut.sv, line:1:1, endln:9:10 + \_module_inst: work@m (work@m), file:${SURELOG_DIR}/tests/PoundDelayTask/dut.sv, line:1:1, endln:9:10 |vpiStmt: \_sys_func_call: ($display), line:3:9, endln:3:32 |vpiParent: @@ -178,12 +178,12 @@ design: (work@m) \_constant: , line:3:18, endln:3:31 |vpiName:$display |vpiInstance: - \_module: work@m (work@m), file:${SURELOG_DIR}/tests/PoundDelayTask/dut.sv, line:1:1, endln:9:10 + \_module_inst: work@m (work@m), file:${SURELOG_DIR}/tests/PoundDelayTask/dut.sv, line:1:1, endln:9:10 |vpiTopModule:1 |vpiProcess: \_initial: , line:6:5, endln:8:8 |vpiParent: - \_module: work@m (work@m), file:${SURELOG_DIR}/tests/PoundDelayTask/dut.sv, line:1:1, endln:9:10 + \_module_inst: work@m (work@m), file:${SURELOG_DIR}/tests/PoundDelayTask/dut.sv, line:1:1, endln:9:10 |vpiStmt: \_begin: (work@m), line:6:13, endln:8:8 |vpiParent: diff --git a/tests/PpLppdr/PpLppdr.log b/tests/PpLppdr/PpLppdr.log index ad1461e2f7..7604a0c2c0 100644 --- a/tests/PpLppdr/PpLppdr.log +++ b/tests/PpLppdr/PpLppdr.log @@ -118,7 +118,7 @@ constant 3 design 1 func_call 2 logic_net 3 -module 2 +module_inst 2 ref_obj 6 task 1 === UHDM Object Stats End === @@ -132,7 +132,7 @@ constant 3 design 1 func_call 4 logic_net 3 -module 2 +module_inst 2 ref_obj 12 task 2 === UHDM Object Stats End === @@ -149,7 +149,7 @@ design: (work@top) |vpiElaborated:1 |vpiName:work@top |uhdmallModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/PpLppdr/dut.sv, line:16:1, endln:25:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/PpLppdr/dut.sv, line:16:1, endln:25:10 |vpiParent: \_design: (work@top) |vpiFullName:work@top @@ -157,13 +157,13 @@ design: (work@top) |vpiTaskFunc: \_task: (work@top.set_refgen_en), line:18:3, endln:22:8 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/PpLppdr/dut.sv, line:16:1, endln:25:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/PpLppdr/dut.sv, line:16:1, endln:25:10 |vpiName:set_refgen_en |vpiFullName:work@top.set_refgen_en |vpiVisibility:1 |vpiAutomatic:1 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/PpLppdr/dut.sv, line:16:1, endln:25:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/PpLppdr/dut.sv, line:16:1, endln:25:10 |vpiStmt: \_begin: (work@top.set_refgen_en), line:19:5, endln:21:8 |vpiParent: @@ -260,22 +260,22 @@ design: (work@top) \_logic_net: (wdata) |vpiName:csr_write |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/PpLppdr/dut.sv, line:16:1, endln:25:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/PpLppdr/dut.sv, line:16:1, endln:25:10 |uhdmtopModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/PpLppdr/dut.sv, line:16:1, endln:25:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/PpLppdr/dut.sv, line:16:1, endln:25:10 |vpiName:work@top |vpiDefName:work@top |vpiTop:1 |vpiTaskFunc: \_task: (work@top.set_refgen_en), line:18:3, endln:22:8 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/PpLppdr/dut.sv, line:16:1, endln:25:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/PpLppdr/dut.sv, line:16:1, endln:25:10 |vpiName:set_refgen_en |vpiFullName:work@top.set_refgen_en |vpiVisibility:1 |vpiAutomatic:1 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/PpLppdr/dut.sv, line:16:1, endln:25:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/PpLppdr/dut.sv, line:16:1, endln:25:10 |vpiStmt: \_begin: (work@top.set_refgen_en), line:19:5, endln:21:8 |vpiParent: @@ -359,7 +359,7 @@ design: (work@top) \_logic_net: (wdata) |vpiName:csr_write |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/PpLppdr/dut.sv, line:16:1, endln:25:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/PpLppdr/dut.sv, line:16:1, endln:25:10 |vpiNet: \_logic_net: (DDR_CMN_OFFSET) |vpiName:DDR_CMN_OFFSET diff --git a/tests/PragmaProtect/PragmaProtect.log b/tests/PragmaProtect/PragmaProtect.log index 1bfd666616..3777651289 100644 --- a/tests/PragmaProtect/PragmaProtect.log +++ b/tests/PragmaProtect/PragmaProtect.log @@ -60,7 +60,7 @@ io_decl 11 logic_net 13 logic_typespec 14 logic_var 1 -module 3 +module_inst 3 operation 10 package 2 port 8 diff --git a/tests/PreprocFunc/PreprocFunc.log b/tests/PreprocFunc/PreprocFunc.log index f41ebd415f..4ba00a794d 100644 --- a/tests/PreprocFunc/PreprocFunc.log +++ b/tests/PreprocFunc/PreprocFunc.log @@ -674,7 +674,7 @@ integer_var 4 io_decl 12 logic_typespec 2 logic_var 2 -module 6 +module_inst 6 operation 19 package 2 param_assign 14 @@ -710,7 +710,7 @@ integer_var 5 io_decl 24 logic_typespec 2 logic_var 3 -module 6 +module_inst 6 operation 24 package 2 param_assign 14 @@ -1211,14 +1211,14 @@ design: (work@asym_ram) \_int_typespec: |vpiSigned:1 |uhdmallModules: -\_module: work@asym_ram (work@asym_ram), file:${SURELOG_DIR}/tests/PreprocFunc/dut.sv, line:5:1, endln:45:10 +\_module_inst: work@asym_ram (work@asym_ram), file:${SURELOG_DIR}/tests/PreprocFunc/dut.sv, line:5:1, endln:45:10 |vpiParent: \_design: (work@asym_ram) |vpiFullName:work@asym_ram |vpiParameter: \_parameter: (work@asym_ram.WIDTHB), line:6:11, endln:6:17 |vpiParent: - \_module: work@asym_ram (work@asym_ram), file:${SURELOG_DIR}/tests/PreprocFunc/dut.sv, line:5:1, endln:45:10 + \_module_inst: work@asym_ram (work@asym_ram), file:${SURELOG_DIR}/tests/PreprocFunc/dut.sv, line:5:1, endln:45:10 |UINT:4 |vpiTypespec: \_int_typespec: @@ -1227,7 +1227,7 @@ design: (work@asym_ram) |vpiParameter: \_parameter: (work@asym_ram.WIDTHA), line:7:11, endln:7:17 |vpiParent: - \_module: work@asym_ram (work@asym_ram), file:${SURELOG_DIR}/tests/PreprocFunc/dut.sv, line:5:1, endln:45:10 + \_module_inst: work@asym_ram (work@asym_ram), file:${SURELOG_DIR}/tests/PreprocFunc/dut.sv, line:5:1, endln:45:10 |UINT:4 |vpiTypespec: \_int_typespec: @@ -1236,35 +1236,35 @@ design: (work@asym_ram) |vpiParameter: \_parameter: (work@asym_ram.maxWIDTH), line:30:12, endln:30:20 |vpiParent: - \_module: work@asym_ram (work@asym_ram), file:${SURELOG_DIR}/tests/PreprocFunc/dut.sv, line:5:1, endln:45:10 + \_module_inst: work@asym_ram (work@asym_ram), file:${SURELOG_DIR}/tests/PreprocFunc/dut.sv, line:5:1, endln:45:10 |vpiLocalParam:1 |vpiName:maxWIDTH |vpiFullName:work@asym_ram.maxWIDTH |vpiParameter: \_parameter: (work@asym_ram.minWIDTH), line:35:12, endln:35:20 |vpiParent: - \_module: work@asym_ram (work@asym_ram), file:${SURELOG_DIR}/tests/PreprocFunc/dut.sv, line:5:1, endln:45:10 + \_module_inst: work@asym_ram (work@asym_ram), file:${SURELOG_DIR}/tests/PreprocFunc/dut.sv, line:5:1, endln:45:10 |vpiLocalParam:1 |vpiName:minWIDTH |vpiFullName:work@asym_ram.minWIDTH |vpiParameter: \_parameter: (work@asym_ram.RATIO), line:39:12, endln:39:17 |vpiParent: - \_module: work@asym_ram (work@asym_ram), file:${SURELOG_DIR}/tests/PreprocFunc/dut.sv, line:5:1, endln:45:10 + \_module_inst: work@asym_ram (work@asym_ram), file:${SURELOG_DIR}/tests/PreprocFunc/dut.sv, line:5:1, endln:45:10 |vpiLocalParam:1 |vpiName:RATIO |vpiFullName:work@asym_ram.RATIO |vpiParameter: \_parameter: (work@asym_ram.log2RATIO), line:42:12, endln:42:21 |vpiParent: - \_module: work@asym_ram (work@asym_ram), file:${SURELOG_DIR}/tests/PreprocFunc/dut.sv, line:5:1, endln:45:10 + \_module_inst: work@asym_ram (work@asym_ram), file:${SURELOG_DIR}/tests/PreprocFunc/dut.sv, line:5:1, endln:45:10 |vpiLocalParam:1 |vpiName:log2RATIO |vpiFullName:work@asym_ram.log2RATIO |vpiParamAssign: \_param_assign: , line:6:11, endln:6:21 |vpiParent: - \_module: work@asym_ram (work@asym_ram), file:${SURELOG_DIR}/tests/PreprocFunc/dut.sv, line:5:1, endln:45:10 + \_module_inst: work@asym_ram (work@asym_ram), file:${SURELOG_DIR}/tests/PreprocFunc/dut.sv, line:5:1, endln:45:10 |vpiRhs: \_constant: , line:6:20, endln:6:21 |vpiDecompile:4 @@ -1278,7 +1278,7 @@ design: (work@asym_ram) |vpiParamAssign: \_param_assign: , line:7:11, endln:7:21 |vpiParent: - \_module: work@asym_ram (work@asym_ram), file:${SURELOG_DIR}/tests/PreprocFunc/dut.sv, line:5:1, endln:45:10 + \_module_inst: work@asym_ram (work@asym_ram), file:${SURELOG_DIR}/tests/PreprocFunc/dut.sv, line:5:1, endln:45:10 |vpiRhs: \_constant: , line:7:20, endln:7:21 |vpiDecompile:4 @@ -1292,7 +1292,7 @@ design: (work@asym_ram) |vpiParamAssign: \_param_assign: , line:30:12, endln:30:66 |vpiParent: - \_module: work@asym_ram (work@asym_ram), file:${SURELOG_DIR}/tests/PreprocFunc/dut.sv, line:5:1, endln:45:10 + \_module_inst: work@asym_ram (work@asym_ram), file:${SURELOG_DIR}/tests/PreprocFunc/dut.sv, line:5:1, endln:45:10 |vpiRhs: \_operation: , line:30:23, endln:30:66 |vpiOpType:33 @@ -1331,7 +1331,7 @@ design: (work@asym_ram) |vpiParamAssign: \_param_assign: , line:35:12, endln:35:66 |vpiParent: - \_module: work@asym_ram (work@asym_ram), file:${SURELOG_DIR}/tests/PreprocFunc/dut.sv, line:5:1, endln:45:10 + \_module_inst: work@asym_ram (work@asym_ram), file:${SURELOG_DIR}/tests/PreprocFunc/dut.sv, line:5:1, endln:45:10 |vpiRhs: \_operation: , line:35:23, endln:35:66 |vpiOpType:33 @@ -1370,7 +1370,7 @@ design: (work@asym_ram) |vpiParamAssign: \_param_assign: , line:39:12, endln:39:39 |vpiParent: - \_module: work@asym_ram (work@asym_ram), file:${SURELOG_DIR}/tests/PreprocFunc/dut.sv, line:5:1, endln:45:10 + \_module_inst: work@asym_ram (work@asym_ram), file:${SURELOG_DIR}/tests/PreprocFunc/dut.sv, line:5:1, endln:45:10 |vpiRhs: \_operation: , line:39:20, endln:39:39 |vpiOpType:12 @@ -1389,7 +1389,7 @@ design: (work@asym_ram) |vpiParamAssign: \_param_assign: , line:42:12, endln:42:35 |vpiParent: - \_module: work@asym_ram (work@asym_ram), file:${SURELOG_DIR}/tests/PreprocFunc/dut.sv, line:5:1, endln:45:10 + \_module_inst: work@asym_ram (work@asym_ram), file:${SURELOG_DIR}/tests/PreprocFunc/dut.sv, line:5:1, endln:45:10 |vpiRhs: \_func_call: (log2), line:42:24, endln:42:28 |vpiArgument: @@ -1406,7 +1406,7 @@ design: (work@asym_ram) |vpiTaskFunc: \_function: (work@asym_ram.log2), line:13:1, endln:28:12 |vpiParent: - \_module: work@asym_ram (work@asym_ram), file:${SURELOG_DIR}/tests/PreprocFunc/dut.sv, line:5:1, endln:45:10 + \_module_inst: work@asym_ram (work@asym_ram), file:${SURELOG_DIR}/tests/PreprocFunc/dut.sv, line:5:1, endln:45:10 |vpiName:log2 |vpiFullName:work@asym_ram.log2 |vpiVariables: @@ -1451,7 +1451,7 @@ design: (work@asym_ram) |vpiSigned:1 |vpiSigned:1 |vpiParent: - \_module: work@asym_ram (work@asym_ram), file:${SURELOG_DIR}/tests/PreprocFunc/dut.sv, line:5:1, endln:45:10 + \_module_inst: work@asym_ram (work@asym_ram), file:${SURELOG_DIR}/tests/PreprocFunc/dut.sv, line:5:1, endln:45:10 |vpiIODecl: \_io_decl: (value), line:14:15, endln:14:20 |vpiParent: @@ -1690,14 +1690,14 @@ design: (work@asym_ram) |vpiActual: \_integer_var: (log2), line:13:10, endln:13:17 |vpiInstance: - \_module: work@asym_ram (work@asym_ram), file:${SURELOG_DIR}/tests/PreprocFunc/dut.sv, line:5:1, endln:45:10 + \_module_inst: work@asym_ram (work@asym_ram), file:${SURELOG_DIR}/tests/PreprocFunc/dut.sv, line:5:1, endln:45:10 |uhdmtopModules: -\_module: work@asym_ram (work@asym_ram), file:${SURELOG_DIR}/tests/PreprocFunc/dut.sv, line:5:1, endln:45:10 +\_module_inst: work@asym_ram (work@asym_ram), file:${SURELOG_DIR}/tests/PreprocFunc/dut.sv, line:5:1, endln:45:10 |vpiName:work@asym_ram |vpiParameter: \_parameter: (work@asym_ram.WIDTHB), line:6:11, endln:6:17 |vpiParent: - \_module: work@asym_ram (work@asym_ram), file:${SURELOG_DIR}/tests/PreprocFunc/dut.sv, line:5:1, endln:45:10 + \_module_inst: work@asym_ram (work@asym_ram), file:${SURELOG_DIR}/tests/PreprocFunc/dut.sv, line:5:1, endln:45:10 |UINT:4 |vpiTypespec: \_int_typespec: @@ -1708,7 +1708,7 @@ design: (work@asym_ram) |vpiParameter: \_parameter: (work@asym_ram.WIDTHA), line:7:11, endln:7:17 |vpiParent: - \_module: work@asym_ram (work@asym_ram), file:${SURELOG_DIR}/tests/PreprocFunc/dut.sv, line:5:1, endln:45:10 + \_module_inst: work@asym_ram (work@asym_ram), file:${SURELOG_DIR}/tests/PreprocFunc/dut.sv, line:5:1, endln:45:10 |UINT:4 |vpiTypespec: \_int_typespec: @@ -1719,35 +1719,35 @@ design: (work@asym_ram) |vpiParameter: \_parameter: (work@asym_ram.maxWIDTH), line:30:12, endln:30:20 |vpiParent: - \_module: work@asym_ram (work@asym_ram), file:${SURELOG_DIR}/tests/PreprocFunc/dut.sv, line:5:1, endln:45:10 + \_module_inst: work@asym_ram (work@asym_ram), file:${SURELOG_DIR}/tests/PreprocFunc/dut.sv, line:5:1, endln:45:10 |vpiLocalParam:1 |vpiName:maxWIDTH |vpiFullName:work@asym_ram.maxWIDTH |vpiParameter: \_parameter: (work@asym_ram.minWIDTH), line:35:12, endln:35:20 |vpiParent: - \_module: work@asym_ram (work@asym_ram), file:${SURELOG_DIR}/tests/PreprocFunc/dut.sv, line:5:1, endln:45:10 + \_module_inst: work@asym_ram (work@asym_ram), file:${SURELOG_DIR}/tests/PreprocFunc/dut.sv, line:5:1, endln:45:10 |vpiLocalParam:1 |vpiName:minWIDTH |vpiFullName:work@asym_ram.minWIDTH |vpiParameter: \_parameter: (work@asym_ram.RATIO), line:39:12, endln:39:17 |vpiParent: - \_module: work@asym_ram (work@asym_ram), file:${SURELOG_DIR}/tests/PreprocFunc/dut.sv, line:5:1, endln:45:10 + \_module_inst: work@asym_ram (work@asym_ram), file:${SURELOG_DIR}/tests/PreprocFunc/dut.sv, line:5:1, endln:45:10 |vpiLocalParam:1 |vpiName:RATIO |vpiFullName:work@asym_ram.RATIO |vpiParameter: \_parameter: (work@asym_ram.log2RATIO), line:42:12, endln:42:21 |vpiParent: - \_module: work@asym_ram (work@asym_ram), file:${SURELOG_DIR}/tests/PreprocFunc/dut.sv, line:5:1, endln:45:10 + \_module_inst: work@asym_ram (work@asym_ram), file:${SURELOG_DIR}/tests/PreprocFunc/dut.sv, line:5:1, endln:45:10 |vpiLocalParam:1 |vpiName:log2RATIO |vpiFullName:work@asym_ram.log2RATIO |vpiParamAssign: \_param_assign: , line:6:11, endln:6:21 |vpiParent: - \_module: work@asym_ram (work@asym_ram), file:${SURELOG_DIR}/tests/PreprocFunc/dut.sv, line:5:1, endln:45:10 + \_module_inst: work@asym_ram (work@asym_ram), file:${SURELOG_DIR}/tests/PreprocFunc/dut.sv, line:5:1, endln:45:10 |vpiRhs: \_constant: , line:6:20, endln:6:21 |vpiDecompile:4 @@ -1761,7 +1761,7 @@ design: (work@asym_ram) |vpiParamAssign: \_param_assign: , line:7:11, endln:7:21 |vpiParent: - \_module: work@asym_ram (work@asym_ram), file:${SURELOG_DIR}/tests/PreprocFunc/dut.sv, line:5:1, endln:45:10 + \_module_inst: work@asym_ram (work@asym_ram), file:${SURELOG_DIR}/tests/PreprocFunc/dut.sv, line:5:1, endln:45:10 |vpiRhs: \_constant: , line:7:20, endln:7:21 |vpiDecompile:4 @@ -1775,7 +1775,7 @@ design: (work@asym_ram) |vpiParamAssign: \_param_assign: , line:30:12, endln:30:66 |vpiParent: - \_module: work@asym_ram (work@asym_ram), file:${SURELOG_DIR}/tests/PreprocFunc/dut.sv, line:5:1, endln:45:10 + \_module_inst: work@asym_ram (work@asym_ram), file:${SURELOG_DIR}/tests/PreprocFunc/dut.sv, line:5:1, endln:45:10 |vpiRhs: \_constant: , line:30:23, endln:30:66 |vpiDecompile:64'b0000000000000000000000000000000000000000000000000000000000000100 @@ -1787,7 +1787,7 @@ design: (work@asym_ram) |vpiParamAssign: \_param_assign: , line:35:12, endln:35:66 |vpiParent: - \_module: work@asym_ram (work@asym_ram), file:${SURELOG_DIR}/tests/PreprocFunc/dut.sv, line:5:1, endln:45:10 + \_module_inst: work@asym_ram (work@asym_ram), file:${SURELOG_DIR}/tests/PreprocFunc/dut.sv, line:5:1, endln:45:10 |vpiRhs: \_constant: , line:35:23, endln:35:66 |vpiDecompile:64'b0000000000000000000000000000000000000000000000000000000000000100 @@ -1799,7 +1799,7 @@ design: (work@asym_ram) |vpiParamAssign: \_param_assign: , line:39:12, endln:39:39 |vpiParent: - \_module: work@asym_ram (work@asym_ram), file:${SURELOG_DIR}/tests/PreprocFunc/dut.sv, line:5:1, endln:45:10 + \_module_inst: work@asym_ram (work@asym_ram), file:${SURELOG_DIR}/tests/PreprocFunc/dut.sv, line:5:1, endln:45:10 |vpiRhs: \_constant: , line:39:20, endln:39:39 |vpiDecompile:1 @@ -1811,7 +1811,7 @@ design: (work@asym_ram) |vpiParamAssign: \_param_assign: , line:42:12, endln:42:35 |vpiParent: - \_module: work@asym_ram (work@asym_ram), file:${SURELOG_DIR}/tests/PreprocFunc/dut.sv, line:5:1, endln:45:10 + \_module_inst: work@asym_ram (work@asym_ram), file:${SURELOG_DIR}/tests/PreprocFunc/dut.sv, line:5:1, endln:45:10 |vpiRhs: \_constant: , line:42:24, endln:42:35 |vpiDecompile:1 @@ -1825,7 +1825,7 @@ design: (work@asym_ram) |vpiTaskFunc: \_function: (work@asym_ram.log2), line:13:1, endln:28:12 |vpiParent: - \_module: work@asym_ram (work@asym_ram), file:${SURELOG_DIR}/tests/PreprocFunc/dut.sv, line:5:1, endln:45:10 + \_module_inst: work@asym_ram (work@asym_ram), file:${SURELOG_DIR}/tests/PreprocFunc/dut.sv, line:5:1, endln:45:10 |vpiName:log2 |vpiFullName:work@asym_ram.log2 |vpiVariables: @@ -1851,7 +1851,7 @@ design: (work@asym_ram) |vpiReturn: \_integer_var: , line:13:10, endln:13:17 |vpiParent: - \_module: work@asym_ram (work@asym_ram), file:${SURELOG_DIR}/tests/PreprocFunc/dut.sv, line:5:1, endln:45:10 + \_module_inst: work@asym_ram (work@asym_ram), file:${SURELOG_DIR}/tests/PreprocFunc/dut.sv, line:5:1, endln:45:10 |vpiIODecl: \_io_decl: (value), line:14:15, endln:14:20 |vpiParent: @@ -2055,7 +2055,7 @@ design: (work@asym_ram) |vpiActual: \_integer_var: , line:13:10, endln:13:17 |vpiInstance: - \_module: work@asym_ram (work@asym_ram), file:${SURELOG_DIR}/tests/PreprocFunc/dut.sv, line:5:1, endln:45:10 + \_module_inst: work@asym_ram (work@asym_ram), file:${SURELOG_DIR}/tests/PreprocFunc/dut.sv, line:5:1, endln:45:10 |vpiTopModule:1 =================== [ FATAL] : 0 diff --git a/tests/PreprocLine/PreprocLine.log b/tests/PreprocLine/PreprocLine.log index 183eda04c1..300a22c9f3 100644 --- a/tests/PreprocLine/PreprocLine.log +++ b/tests/PreprocLine/PreprocLine.log @@ -15,38 +15,38 @@ n u<3> t p<4> l<1:8> el<1:11> n<> u<4> t p<65> c<2> s<64> l<1:1> el<1:12> n<> u<5> t p<17> s<6> l<3:9> el<3:10> n u<6> t p<17> s<16> l<3:10> el<3:17> -n<"${SURELOG_DIR}/tests/PreprocLine/dut.sv"> u<7> t p<8> l<3:18> el<3:64> -n<> u<8> t p<9> c<7> l<3:18> el<3:64> -n<> u<9> t p<10> c<8> l<3:18> el<3:64> -n<> u<10> t p<16> c<9> s<15> l<3:18> el<3:64> -n<3> u<11> t p<12> l<3:66> el<3:67> -n<> u<12> t p<13> c<11> l<3:66> el<3:67> -n<> u<13> t p<14> c<12> l<3:66> el<3:67> -n<> u<14> t p<15> c<13> l<3:66> el<3:67> -n<> u<15> t p<16> c<14> l<3:66> el<3:67> -n<> u<16> t p<17> c<10> l<3:18> el<3:67> -n<> u<17> t p<18> c<5> l<3:9> el<3:68> -n<> u<18> t p<19> c<17> l<3:9> el<3:69> -n<> u<19> t p<20> c<18> l<3:9> el<3:69> -n<> u<20> t p<21> c<19> l<3:9> el<3:69> -n<> u<21> t p<57> c<20> s<38> l<3:9> el<3:69> +n<"${SURELOG_DIR}/tests/PreprocLine/dut.sv"> u<7> t p<8> l<3:18> el<3:78> +n<> u<8> t p<9> c<7> l<3:18> el<3:78> +n<> u<9> t p<10> c<8> l<3:18> el<3:78> +n<> u<10> t p<16> c<9> s<15> l<3:18> el<3:78> +n<3> u<11> t p<12> l<3:80> el<3:81> +n<> u<12> t p<13> c<11> l<3:80> el<3:81> +n<> u<13> t p<14> c<12> l<3:80> el<3:81> +n<> u<14> t p<15> c<13> l<3:80> el<3:81> +n<> u<15> t p<16> c<14> l<3:80> el<3:81> +n<> u<16> t p<17> c<10> l<3:18> el<3:81> +n<> u<17> t p<18> c<5> l<3:9> el<3:82> +n<> u<18> t p<19> c<17> l<3:9> el<3:83> +n<> u<19> t p<20> c<18> l<3:9> el<3:83> +n<> u<20> t p<21> c<19> l<3:9> el<3:83> +n<> u<21> t p<57> c<20> s<38> l<3:9> el<3:83> n<> u<22> t p<34> s<23> l<5:9> el<5:10> n u<23> t p<34> s<33> l<5:10> el<5:17> -n<"${SURELOG_DIR}/tests/PreprocLine/fake.v"> u<24> t p<25> l<5:18> el<5:64> -n<> u<25> t p<26> c<24> l<5:18> el<5:64> -n<> u<26> t p<27> c<25> l<5:18> el<5:64> -n<> u<27> t p<33> c<26> s<32> l<5:18> el<5:64> -n<102> u<28> t p<29> l<5:66> el<5:69> -n<> u<29> t p<30> c<28> l<5:66> el<5:69> -n<> u<30> t p<31> c<29> l<5:66> el<5:69> -n<> u<31> t p<32> c<30> l<5:66> el<5:69> -n<> u<32> t p<33> c<31> l<5:66> el<5:69> -n<> u<33> t p<34> c<27> l<5:18> el<5:69> -n<> u<34> t p<35> c<22> l<5:9> el<5:70> -n<> u<35> t p<36> c<34> l<5:9> el<5:71> -n<> u<36> t p<37> c<35> l<5:9> el<5:71> -n<> u<37> t p<38> c<36> l<5:9> el<5:71> -n<> u<38> t p<57> c<37> s<55> l<5:9> el<5:71> +n<"${SURELOG_DIR}/tests/PreprocLine/fake.v"> u<24> t p<25> l<5:18> el<5:78> +n<> u<25> t p<26> c<24> l<5:18> el<5:78> +n<> u<26> t p<27> c<25> l<5:18> el<5:78> +n<> u<27> t p<33> c<26> s<32> l<5:18> el<5:78> +n<102> u<28> t p<29> l<5:80> el<5:83> +n<> u<29> t p<30> c<28> l<5:80> el<5:83> +n<> u<30> t p<31> c<29> l<5:80> el<5:83> +n<> u<31> t p<32> c<30> l<5:80> el<5:83> +n<> u<32> t p<33> c<31> l<5:80> el<5:83> +n<> u<33> t p<34> c<27> l<5:18> el<5:83> +n<> u<34> t p<35> c<22> l<5:9> el<5:84> +n<> u<35> t p<36> c<34> l<5:9> el<5:85> +n<> u<36> t p<37> c<35> l<5:9> el<5:85> +n<> u<37> t p<38> c<36> l<5:9> el<5:85> +n<> u<38> t p<57> c<37> s<55> l<5:9> el<5:85> n<> u<39> t p<51> s<40> f<0> l<10:9> el<10:10> n u<40> t p<51> s<50> f<0> l<10:10> el<10:17> n<""> u<41> t p<42> f<0> l<10:18> el<10:20> diff --git a/tests/PreprocString/PreprocString.log b/tests/PreprocString/PreprocString.log index 220bd4919b..0bb1f59b83 100644 --- a/tests/PreprocString/PreprocString.log +++ b/tests/PreprocString/PreprocString.log @@ -62,7 +62,7 @@ begin 1 constant 1 design 1 initial 1 -module 2 +module_inst 2 sys_func_call 1 === UHDM Object Stats End === [INF:UH0707] Elaborating UHDM... @@ -72,7 +72,7 @@ begin 2 constant 1 design 1 initial 2 -module 2 +module_inst 2 sys_func_call 2 === UHDM Object Stats End === [INF:UH0708] Writing UHDM DB: ${SURELOG_DIR}/build/regression/PreprocString/slpp_all/surelog.uhdm ... @@ -88,7 +88,7 @@ design: (work@test) |vpiElaborated:1 |vpiName:work@test |uhdmallModules: -\_module: work@test (work@test), file:${SURELOG_DIR}/tests/PreprocString/dut.sv, line:1:1, endln:9:10 +\_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/PreprocString/dut.sv, line:1:1, endln:9:10 |vpiParent: \_design: (work@test) |vpiFullName:work@test @@ -96,7 +96,7 @@ design: (work@test) |vpiProcess: \_initial: , line:6:1, endln:8:8 |vpiParent: - \_module: work@test (work@test), file:${SURELOG_DIR}/tests/PreprocString/dut.sv, line:1:1, endln:9:10 + \_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/PreprocString/dut.sv, line:1:1, endln:9:10 |vpiStmt: \_begin: (work@test), line:6:9, endln:8:8 |vpiParent: @@ -116,7 +116,7 @@ design: (work@test) |vpiConstType:6 |vpiName:$display |uhdmtopModules: -\_module: work@test (work@test), file:${SURELOG_DIR}/tests/PreprocString/dut.sv, line:1:1, endln:9:10 +\_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/PreprocString/dut.sv, line:1:1, endln:9:10 |vpiName:work@test |vpiDefName:work@test |vpiTop:1 @@ -124,7 +124,7 @@ design: (work@test) |vpiProcess: \_initial: , line:6:1, endln:8:8 |vpiParent: - \_module: work@test (work@test), file:${SURELOG_DIR}/tests/PreprocString/dut.sv, line:1:1, endln:9:10 + \_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/PreprocString/dut.sv, line:1:1, endln:9:10 |vpiStmt: \_begin: (work@test), line:6:9, endln:8:8 |vpiParent: diff --git a/tests/PreprocTest/PreprocTest.log b/tests/PreprocTest/PreprocTest.log index e66843e609..4e06e7dd5e 100644 --- a/tests/PreprocTest/PreprocTest.log +++ b/tests/PreprocTest/PreprocTest.log @@ -44,7 +44,7 @@ int_typespec 9 int_var 4 io_decl 11 logic_var 1 -module 2 +module_inst 2 package 8 range 2 task 9 diff --git a/tests/PreprocUhdmCov/PreprocUhdmCov.log b/tests/PreprocUhdmCov/PreprocUhdmCov.log index c7e897235f..edcca72f2b 100644 --- a/tests/PreprocUhdmCov/PreprocUhdmCov.log +++ b/tests/PreprocUhdmCov/PreprocUhdmCov.log @@ -526,7 +526,7 @@ io_decl 13 logic_net 5 logic_typespec 10 logic_var 2 -module 6 +module_inst 6 package 2 param_assign 1 parameter 1 @@ -558,7 +558,7 @@ io_decl 26 logic_net 5 logic_typespec 10 logic_var 2 -module 6 +module_inst 6 package 2 param_assign 1 parameter 1 @@ -1060,17 +1060,17 @@ design: (work@top) \_int_typespec: |vpiSigned:1 |uhdmallModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/PreprocUhdmCov/dut.sv, line:4:1, endln:50:17 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/PreprocUhdmCov/dut.sv, line:4:1, endln:50:17 |vpiParent: \_design: (work@top) |vpiFullName:work@top |vpiTypedef: \_struct_typespec: (spi_device_reg2hw_intr_enable_reg_t), line:38:9, endln:38:15 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/PreprocUhdmCov/dut.sv, line:4:1, endln:50:17 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/PreprocUhdmCov/dut.sv, line:4:1, endln:50:17 |vpiName:spi_device_reg2hw_intr_enable_reg_t |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/PreprocUhdmCov/dut.sv, line:4:1, endln:50:17 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/PreprocUhdmCov/dut.sv, line:4:1, endln:50:17 |vpiPacked:1 |vpiTypespecMember: \_typespec_member: (txunderflow), line:42:10, endln:42:21 @@ -1105,7 +1105,7 @@ design: (work@top) |vpiTaskFunc: \_function: (work@top.prince_shiftrows_32bit), line:45:4, endln:48:40 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/PreprocUhdmCov/dut.sv, line:4:1, endln:50:17 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/PreprocUhdmCov/dut.sv, line:4:1, endln:50:17 |vpiName:prince_shiftrows_32bit |vpiFullName:work@top.prince_shiftrows_32bit |vpiVisibility:1 @@ -1133,7 +1133,7 @@ design: (work@top) |UINT:0 |vpiConstType:9 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/PreprocUhdmCov/dut.sv, line:4:1, endln:50:17 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/PreprocUhdmCov/dut.sv, line:4:1, endln:50:17 |vpiIODecl: \_io_decl: (state_in), line:45:77, endln:45:85 |vpiDirection:1 @@ -1206,25 +1206,25 @@ design: (work@top) \_function: (work@top.prince_shiftrows_32bit), line:45:4, endln:48:40 |vpiFullName:work@top.prince_shiftrows_32bit |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/PreprocUhdmCov/dut.sv, line:4:1, endln:50:17 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/PreprocUhdmCov/dut.sv, line:4:1, endln:50:17 |vpiNet: \_logic_net: (work@top.b), line:4:25, endln:4:26 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/PreprocUhdmCov/dut.sv, line:4:1, endln:50:17 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/PreprocUhdmCov/dut.sv, line:4:1, endln:50:17 |vpiName:b |vpiFullName:work@top.b |vpiNetType:36 |vpiNet: \_logic_net: (work@top.a), line:4:41, endln:4:42 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/PreprocUhdmCov/dut.sv, line:4:1, endln:50:17 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/PreprocUhdmCov/dut.sv, line:4:1, endln:50:17 |vpiName:a |vpiFullName:work@top.a |vpiNetType:36 |vpiPort: \_port: (b), line:4:25, endln:4:26 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/PreprocUhdmCov/dut.sv, line:4:1, endln:50:17 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/PreprocUhdmCov/dut.sv, line:4:1, endln:50:17 |vpiName:b |vpiDirection:1 |vpiLowConn: @@ -1236,7 +1236,7 @@ design: (work@top) |vpiPort: \_port: (a), line:4:41, endln:4:42 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/PreprocUhdmCov/dut.sv, line:4:1, endln:50:17 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/PreprocUhdmCov/dut.sv, line:4:1, endln:50:17 |vpiName:a |vpiDirection:2 |vpiLowConn: @@ -1248,7 +1248,7 @@ design: (work@top) |vpiContAssign: \_cont_assign: , line:9:11, endln:9:16 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/PreprocUhdmCov/dut.sv, line:4:1, endln:50:17 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/PreprocUhdmCov/dut.sv, line:4:1, endln:50:17 |vpiRhs: \_ref_obj: (work@top.b), line:9:15, endln:9:16 |vpiParent: @@ -1268,7 +1268,7 @@ design: (work@top) |vpiContAssign: \_cont_assign: , line:15:11, endln:15:16 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/PreprocUhdmCov/dut.sv, line:4:1, endln:50:17 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/PreprocUhdmCov/dut.sv, line:4:1, endln:50:17 |vpiRhs: \_ref_obj: (work@top.b), line:15:15, endln:15:16 |vpiParent: @@ -1288,7 +1288,7 @@ design: (work@top) |vpiContAssign: \_cont_assign: , line:20:11, endln:20:16 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/PreprocUhdmCov/dut.sv, line:4:1, endln:50:17 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/PreprocUhdmCov/dut.sv, line:4:1, endln:50:17 |vpiRhs: \_ref_obj: (work@top.b), line:20:15, endln:20:16 |vpiParent: @@ -1308,7 +1308,7 @@ design: (work@top) |vpiContAssign: \_cont_assign: , line:26:9, endln:26:14 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/PreprocUhdmCov/dut.sv, line:4:1, endln:50:17 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/PreprocUhdmCov/dut.sv, line:4:1, endln:50:17 |vpiRhs: \_ref_obj: (work@top.b), line:26:13, endln:26:14 |vpiParent: @@ -1326,7 +1326,7 @@ design: (work@top) |vpiActual: \_logic_net: (work@top.a), line:4:41, endln:4:42 |uhdmtopModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/PreprocUhdmCov/dut.sv, line:4:1, endln:50:17 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/PreprocUhdmCov/dut.sv, line:4:1, endln:50:17 |vpiName:work@top |vpiTypedef: \_struct_typespec: (spi_device_reg2hw_intr_enable_reg_t), line:38:9, endln:38:15 @@ -1335,7 +1335,7 @@ design: (work@top) |vpiTaskFunc: \_function: (work@top.prince_shiftrows_32bit), line:45:4, endln:48:40 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/PreprocUhdmCov/dut.sv, line:4:1, endln:50:17 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/PreprocUhdmCov/dut.sv, line:4:1, endln:50:17 |vpiName:prince_shiftrows_32bit |vpiFullName:work@top.prince_shiftrows_32bit |vpiVisibility:1 @@ -1343,7 +1343,7 @@ design: (work@top) |vpiReturn: \_logic_var: , line:45:23, endln:45:35 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/PreprocUhdmCov/dut.sv, line:4:1, endln:50:17 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/PreprocUhdmCov/dut.sv, line:4:1, endln:50:17 |vpiIODecl: \_io_decl: (state_in), line:45:77, endln:45:85 |vpiParent: @@ -1366,11 +1366,11 @@ design: (work@top) \_function: (work@top.prince_shiftrows_32bit), line:45:4, endln:48:40 |vpiFullName:work@top.prince_shiftrows_32bit |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/PreprocUhdmCov/dut.sv, line:4:1, endln:50:17 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/PreprocUhdmCov/dut.sv, line:4:1, endln:50:17 |vpiNet: \_logic_net: (work@top.b), line:4:25, endln:4:26 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/PreprocUhdmCov/dut.sv, line:4:1, endln:50:17 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/PreprocUhdmCov/dut.sv, line:4:1, endln:50:17 |vpiTypespec: \_logic_typespec: , line:4:19, endln:4:24 |vpiName:b @@ -1379,7 +1379,7 @@ design: (work@top) |vpiNet: \_logic_net: (work@top.a), line:4:41, endln:4:42 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/PreprocUhdmCov/dut.sv, line:4:1, endln:50:17 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/PreprocUhdmCov/dut.sv, line:4:1, endln:50:17 |vpiTypespec: \_logic_typespec: , line:4:35, endln:4:40 |vpiName:a @@ -1388,7 +1388,7 @@ design: (work@top) |vpiNet: \_logic_net: (work@top.clk_i), line:33:14, endln:33:19 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/PreprocUhdmCov/dut.sv, line:4:1, endln:50:17 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/PreprocUhdmCov/dut.sv, line:4:1, endln:50:17 |vpiName:clk_i |vpiFullName:work@top.clk_i |vpiNetType:1 @@ -1396,7 +1396,7 @@ design: (work@top) |vpiPort: \_port: (b), line:4:25, endln:4:26 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/PreprocUhdmCov/dut.sv, line:4:1, endln:50:17 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/PreprocUhdmCov/dut.sv, line:4:1, endln:50:17 |vpiName:b |vpiDirection:1 |vpiLowConn: @@ -1410,11 +1410,11 @@ design: (work@top) |vpiTypedef: \_logic_typespec: , line:4:19, endln:4:24 |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/PreprocUhdmCov/dut.sv, line:4:1, endln:50:17 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/PreprocUhdmCov/dut.sv, line:4:1, endln:50:17 |vpiPort: \_port: (a), line:4:41, endln:4:42 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/PreprocUhdmCov/dut.sv, line:4:1, endln:50:17 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/PreprocUhdmCov/dut.sv, line:4:1, endln:50:17 |vpiName:a |vpiDirection:2 |vpiLowConn: @@ -1428,17 +1428,17 @@ design: (work@top) |vpiTypedef: \_logic_typespec: , line:4:35, endln:4:40 |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/PreprocUhdmCov/dut.sv, line:4:1, endln:50:17 - |vpiModule: - \_module: work@top::prim_subreg (work@top.u_ip0_p7), file:${SURELOG_DIR}/tests/PreprocUhdmCov/dut.sv, line:30:2, endln:34:6 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/PreprocUhdmCov/dut.sv, line:4:1, endln:50:17 + |vpiModuleInst: + \_module_inst: work@top::prim_subreg (work@top.u_ip0_p7), file:${SURELOG_DIR}/tests/PreprocUhdmCov/dut.sv, line:30:2, endln:34:6 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/PreprocUhdmCov/dut.sv, line:4:1, endln:50:17 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/PreprocUhdmCov/dut.sv, line:4:1, endln:50:17 |vpiName:u_ip0_p7 |vpiFullName:work@top.u_ip0_p7 |vpiParamAssign: \_param_assign: |vpiParent: - \_module: work@top::prim_subreg (work@top.u_ip0_p7), file:${SURELOG_DIR}/tests/PreprocUhdmCov/dut.sv, line:30:2, endln:34:6 + \_module_inst: work@top::prim_subreg (work@top.u_ip0_p7), file:${SURELOG_DIR}/tests/PreprocUhdmCov/dut.sv, line:30:2, endln:34:6 |vpiOverriden:1 |vpiRhs: \_constant: , line:31:0, endln:31:0 @@ -1451,11 +1451,11 @@ design: (work@top) |vpiName:DW |vpiDefName:work@top::prim_subreg |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/PreprocUhdmCov/dut.sv, line:4:1, endln:50:17 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/PreprocUhdmCov/dut.sv, line:4:1, endln:50:17 |vpiPort: \_port: (clk_i), line:33:5, endln:33:10 |vpiParent: - \_module: work@top::prim_subreg (work@top.u_ip0_p7), file:${SURELOG_DIR}/tests/PreprocUhdmCov/dut.sv, line:30:2, endln:34:6 + \_module_inst: work@top::prim_subreg (work@top.u_ip0_p7), file:${SURELOG_DIR}/tests/PreprocUhdmCov/dut.sv, line:30:2, endln:34:6 |vpiName:clk_i |vpiHighConn: \_ref_obj: (work@top.clk_i), line:33:14, endln:33:19 @@ -1466,7 +1466,7 @@ design: (work@top) |vpiContAssign: \_cont_assign: , line:9:11, endln:9:16 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/PreprocUhdmCov/dut.sv, line:4:1, endln:50:17 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/PreprocUhdmCov/dut.sv, line:4:1, endln:50:17 |vpiRhs: \_ref_obj: (work@top.b), line:9:15, endln:9:16 |vpiParent: @@ -1486,7 +1486,7 @@ design: (work@top) |vpiContAssign: \_cont_assign: , line:15:11, endln:15:16 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/PreprocUhdmCov/dut.sv, line:4:1, endln:50:17 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/PreprocUhdmCov/dut.sv, line:4:1, endln:50:17 |vpiRhs: \_ref_obj: (work@top.b), line:15:15, endln:15:16 |vpiParent: @@ -1506,7 +1506,7 @@ design: (work@top) |vpiContAssign: \_cont_assign: , line:20:11, endln:20:16 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/PreprocUhdmCov/dut.sv, line:4:1, endln:50:17 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/PreprocUhdmCov/dut.sv, line:4:1, endln:50:17 |vpiRhs: \_ref_obj: (work@top.b), line:20:15, endln:20:16 |vpiParent: @@ -1526,7 +1526,7 @@ design: (work@top) |vpiContAssign: \_cont_assign: , line:26:9, endln:26:14 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/PreprocUhdmCov/dut.sv, line:4:1, endln:50:17 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/PreprocUhdmCov/dut.sv, line:4:1, endln:50:17 |vpiRhs: \_ref_obj: (work@top.b), line:26:13, endln:26:14 |vpiParent: diff --git a/tests/PrimTermExpr/PrimTermExpr.log b/tests/PrimTermExpr/PrimTermExpr.log index b5268a1cea..d71cbe21ab 100644 --- a/tests/PrimTermExpr/PrimTermExpr.log +++ b/tests/PrimTermExpr/PrimTermExpr.log @@ -148,7 +148,7 @@ design 1 gate 2 logic_net 10 logic_typespec 9 -module 5 +module_inst 5 port 16 prim_term 6 range 4 @@ -163,7 +163,7 @@ design 1 gate 2 logic_net 10 logic_typespec 9 -module 5 +module_inst 5 port 21 prim_term 6 range 4 @@ -182,7 +182,7 @@ design: (work@encoder_4to2_gates) |vpiElaborated:1 |vpiName:work@encoder_4to2_gates |uhdmallModules: -\_module: work@encoder_4to2_gates (work@encoder_4to2_gates), file:${SURELOG_DIR}/tests/PrimTermExpr/dut.sv, line:1:1, endln:8:10 +\_module_inst: work@encoder_4to2_gates (work@encoder_4to2_gates), file:${SURELOG_DIR}/tests/PrimTermExpr/dut.sv, line:1:1, endln:8:10 |vpiParent: \_design: (work@encoder_4to2_gates) |vpiFullName:work@encoder_4to2_gates @@ -190,37 +190,37 @@ design: (work@encoder_4to2_gates) |vpiNet: \_logic_net: (work@encoder_4to2_gates.i0), line:1:28, endln:1:30 |vpiParent: - \_module: work@encoder_4to2_gates (work@encoder_4to2_gates), file:${SURELOG_DIR}/tests/PrimTermExpr/dut.sv, line:1:1, endln:8:10 + \_module_inst: work@encoder_4to2_gates (work@encoder_4to2_gates), file:${SURELOG_DIR}/tests/PrimTermExpr/dut.sv, line:1:1, endln:8:10 |vpiName:i0 |vpiFullName:work@encoder_4to2_gates.i0 |vpiNet: \_logic_net: (work@encoder_4to2_gates.i1), line:1:31, endln:1:33 |vpiParent: - \_module: work@encoder_4to2_gates (work@encoder_4to2_gates), file:${SURELOG_DIR}/tests/PrimTermExpr/dut.sv, line:1:1, endln:8:10 + \_module_inst: work@encoder_4to2_gates (work@encoder_4to2_gates), file:${SURELOG_DIR}/tests/PrimTermExpr/dut.sv, line:1:1, endln:8:10 |vpiName:i1 |vpiFullName:work@encoder_4to2_gates.i1 |vpiNet: \_logic_net: (work@encoder_4to2_gates.i2), line:1:34, endln:1:36 |vpiParent: - \_module: work@encoder_4to2_gates (work@encoder_4to2_gates), file:${SURELOG_DIR}/tests/PrimTermExpr/dut.sv, line:1:1, endln:8:10 + \_module_inst: work@encoder_4to2_gates (work@encoder_4to2_gates), file:${SURELOG_DIR}/tests/PrimTermExpr/dut.sv, line:1:1, endln:8:10 |vpiName:i2 |vpiFullName:work@encoder_4to2_gates.i2 |vpiNet: \_logic_net: (work@encoder_4to2_gates.i3), line:1:37, endln:1:39 |vpiParent: - \_module: work@encoder_4to2_gates (work@encoder_4to2_gates), file:${SURELOG_DIR}/tests/PrimTermExpr/dut.sv, line:1:1, endln:8:10 + \_module_inst: work@encoder_4to2_gates (work@encoder_4to2_gates), file:${SURELOG_DIR}/tests/PrimTermExpr/dut.sv, line:1:1, endln:8:10 |vpiName:i3 |vpiFullName:work@encoder_4to2_gates.i3 |vpiNet: \_logic_net: (work@encoder_4to2_gates.y), line:1:40, endln:1:41 |vpiParent: - \_module: work@encoder_4to2_gates (work@encoder_4to2_gates), file:${SURELOG_DIR}/tests/PrimTermExpr/dut.sv, line:1:1, endln:8:10 + \_module_inst: work@encoder_4to2_gates (work@encoder_4to2_gates), file:${SURELOG_DIR}/tests/PrimTermExpr/dut.sv, line:1:1, endln:8:10 |vpiName:y |vpiFullName:work@encoder_4to2_gates.y |vpiPort: \_port: (i0), line:1:28, endln:1:30 |vpiParent: - \_module: work@encoder_4to2_gates (work@encoder_4to2_gates), file:${SURELOG_DIR}/tests/PrimTermExpr/dut.sv, line:1:1, endln:8:10 + \_module_inst: work@encoder_4to2_gates (work@encoder_4to2_gates), file:${SURELOG_DIR}/tests/PrimTermExpr/dut.sv, line:1:1, endln:8:10 |vpiName:i0 |vpiDirection:1 |vpiLowConn: @@ -232,7 +232,7 @@ design: (work@encoder_4to2_gates) |vpiPort: \_port: (i1), line:1:31, endln:1:33 |vpiParent: - \_module: work@encoder_4to2_gates (work@encoder_4to2_gates), file:${SURELOG_DIR}/tests/PrimTermExpr/dut.sv, line:1:1, endln:8:10 + \_module_inst: work@encoder_4to2_gates (work@encoder_4to2_gates), file:${SURELOG_DIR}/tests/PrimTermExpr/dut.sv, line:1:1, endln:8:10 |vpiName:i1 |vpiDirection:1 |vpiLowConn: @@ -244,7 +244,7 @@ design: (work@encoder_4to2_gates) |vpiPort: \_port: (i2), line:1:34, endln:1:36 |vpiParent: - \_module: work@encoder_4to2_gates (work@encoder_4to2_gates), file:${SURELOG_DIR}/tests/PrimTermExpr/dut.sv, line:1:1, endln:8:10 + \_module_inst: work@encoder_4to2_gates (work@encoder_4to2_gates), file:${SURELOG_DIR}/tests/PrimTermExpr/dut.sv, line:1:1, endln:8:10 |vpiName:i2 |vpiDirection:1 |vpiLowConn: @@ -256,7 +256,7 @@ design: (work@encoder_4to2_gates) |vpiPort: \_port: (i3), line:1:37, endln:1:39 |vpiParent: - \_module: work@encoder_4to2_gates (work@encoder_4to2_gates), file:${SURELOG_DIR}/tests/PrimTermExpr/dut.sv, line:1:1, endln:8:10 + \_module_inst: work@encoder_4to2_gates (work@encoder_4to2_gates), file:${SURELOG_DIR}/tests/PrimTermExpr/dut.sv, line:1:1, endln:8:10 |vpiName:i3 |vpiDirection:1 |vpiLowConn: @@ -268,7 +268,7 @@ design: (work@encoder_4to2_gates) |vpiPort: \_port: (y), line:1:40, endln:1:41 |vpiParent: - \_module: work@encoder_4to2_gates (work@encoder_4to2_gates), file:${SURELOG_DIR}/tests/PrimTermExpr/dut.sv, line:1:1, endln:8:10 + \_module_inst: work@encoder_4to2_gates (work@encoder_4to2_gates), file:${SURELOG_DIR}/tests/PrimTermExpr/dut.sv, line:1:1, endln:8:10 |vpiName:y |vpiDirection:2 |vpiLowConn: @@ -296,14 +296,14 @@ design: (work@encoder_4to2_gates) |UINT:0 |vpiConstType:9 |uhdmtopModules: -\_module: work@encoder_4to2_gates (work@encoder_4to2_gates), file:${SURELOG_DIR}/tests/PrimTermExpr/dut.sv, line:1:1, endln:8:10 +\_module_inst: work@encoder_4to2_gates (work@encoder_4to2_gates), file:${SURELOG_DIR}/tests/PrimTermExpr/dut.sv, line:1:1, endln:8:10 |vpiName:work@encoder_4to2_gates |vpiDefName:work@encoder_4to2_gates |vpiTop:1 |vpiNet: \_logic_net: (work@encoder_4to2_gates.i0), line:1:28, endln:1:30 |vpiParent: - \_module: work@encoder_4to2_gates (work@encoder_4to2_gates), file:${SURELOG_DIR}/tests/PrimTermExpr/dut.sv, line:1:1, endln:8:10 + \_module_inst: work@encoder_4to2_gates (work@encoder_4to2_gates), file:${SURELOG_DIR}/tests/PrimTermExpr/dut.sv, line:1:1, endln:8:10 |vpiTypespec: \_logic_typespec: , line:2:7, endln:2:7 |vpiName:i0 @@ -311,7 +311,7 @@ design: (work@encoder_4to2_gates) |vpiNet: \_logic_net: (work@encoder_4to2_gates.i1), line:1:31, endln:1:33 |vpiParent: - \_module: work@encoder_4to2_gates (work@encoder_4to2_gates), file:${SURELOG_DIR}/tests/PrimTermExpr/dut.sv, line:1:1, endln:8:10 + \_module_inst: work@encoder_4to2_gates (work@encoder_4to2_gates), file:${SURELOG_DIR}/tests/PrimTermExpr/dut.sv, line:1:1, endln:8:10 |vpiTypespec: \_logic_typespec: , line:2:7, endln:2:7 |vpiName:i1 @@ -319,7 +319,7 @@ design: (work@encoder_4to2_gates) |vpiNet: \_logic_net: (work@encoder_4to2_gates.i2), line:1:34, endln:1:36 |vpiParent: - \_module: work@encoder_4to2_gates (work@encoder_4to2_gates), file:${SURELOG_DIR}/tests/PrimTermExpr/dut.sv, line:1:1, endln:8:10 + \_module_inst: work@encoder_4to2_gates (work@encoder_4to2_gates), file:${SURELOG_DIR}/tests/PrimTermExpr/dut.sv, line:1:1, endln:8:10 |vpiTypespec: \_logic_typespec: , line:2:7, endln:2:7 |vpiName:i2 @@ -327,7 +327,7 @@ design: (work@encoder_4to2_gates) |vpiNet: \_logic_net: (work@encoder_4to2_gates.i3), line:1:37, endln:1:39 |vpiParent: - \_module: work@encoder_4to2_gates (work@encoder_4to2_gates), file:${SURELOG_DIR}/tests/PrimTermExpr/dut.sv, line:1:1, endln:8:10 + \_module_inst: work@encoder_4to2_gates (work@encoder_4to2_gates), file:${SURELOG_DIR}/tests/PrimTermExpr/dut.sv, line:1:1, endln:8:10 |vpiTypespec: \_logic_typespec: , line:2:7, endln:2:7 |vpiName:i3 @@ -335,7 +335,7 @@ design: (work@encoder_4to2_gates) |vpiNet: \_logic_net: (work@encoder_4to2_gates.y), line:1:40, endln:1:41 |vpiParent: - \_module: work@encoder_4to2_gates (work@encoder_4to2_gates), file:${SURELOG_DIR}/tests/PrimTermExpr/dut.sv, line:1:1, endln:8:10 + \_module_inst: work@encoder_4to2_gates (work@encoder_4to2_gates), file:${SURELOG_DIR}/tests/PrimTermExpr/dut.sv, line:1:1, endln:8:10 |vpiTypespec: \_logic_typespec: , line:3:8, endln:3:13 |vpiRange: @@ -362,7 +362,7 @@ design: (work@encoder_4to2_gates) |vpiPort: \_port: (i0), line:1:28, endln:1:30 |vpiParent: - \_module: work@encoder_4to2_gates (work@encoder_4to2_gates), file:${SURELOG_DIR}/tests/PrimTermExpr/dut.sv, line:1:1, endln:8:10 + \_module_inst: work@encoder_4to2_gates (work@encoder_4to2_gates), file:${SURELOG_DIR}/tests/PrimTermExpr/dut.sv, line:1:1, endln:8:10 |vpiName:i0 |vpiDirection:1 |vpiLowConn: @@ -376,11 +376,11 @@ design: (work@encoder_4to2_gates) |vpiTypedef: \_logic_typespec: , line:2:7, endln:2:7 |vpiInstance: - \_module: work@encoder_4to2_gates (work@encoder_4to2_gates), file:${SURELOG_DIR}/tests/PrimTermExpr/dut.sv, line:1:1, endln:8:10 + \_module_inst: work@encoder_4to2_gates (work@encoder_4to2_gates), file:${SURELOG_DIR}/tests/PrimTermExpr/dut.sv, line:1:1, endln:8:10 |vpiPort: \_port: (i1), line:1:31, endln:1:33 |vpiParent: - \_module: work@encoder_4to2_gates (work@encoder_4to2_gates), file:${SURELOG_DIR}/tests/PrimTermExpr/dut.sv, line:1:1, endln:8:10 + \_module_inst: work@encoder_4to2_gates (work@encoder_4to2_gates), file:${SURELOG_DIR}/tests/PrimTermExpr/dut.sv, line:1:1, endln:8:10 |vpiName:i1 |vpiDirection:1 |vpiLowConn: @@ -394,11 +394,11 @@ design: (work@encoder_4to2_gates) |vpiTypedef: \_logic_typespec: , line:2:7, endln:2:7 |vpiInstance: - \_module: work@encoder_4to2_gates (work@encoder_4to2_gates), file:${SURELOG_DIR}/tests/PrimTermExpr/dut.sv, line:1:1, endln:8:10 + \_module_inst: work@encoder_4to2_gates (work@encoder_4to2_gates), file:${SURELOG_DIR}/tests/PrimTermExpr/dut.sv, line:1:1, endln:8:10 |vpiPort: \_port: (i2), line:1:34, endln:1:36 |vpiParent: - \_module: work@encoder_4to2_gates (work@encoder_4to2_gates), file:${SURELOG_DIR}/tests/PrimTermExpr/dut.sv, line:1:1, endln:8:10 + \_module_inst: work@encoder_4to2_gates (work@encoder_4to2_gates), file:${SURELOG_DIR}/tests/PrimTermExpr/dut.sv, line:1:1, endln:8:10 |vpiName:i2 |vpiDirection:1 |vpiLowConn: @@ -412,11 +412,11 @@ design: (work@encoder_4to2_gates) |vpiTypedef: \_logic_typespec: , line:2:7, endln:2:7 |vpiInstance: - \_module: work@encoder_4to2_gates (work@encoder_4to2_gates), file:${SURELOG_DIR}/tests/PrimTermExpr/dut.sv, line:1:1, endln:8:10 + \_module_inst: work@encoder_4to2_gates (work@encoder_4to2_gates), file:${SURELOG_DIR}/tests/PrimTermExpr/dut.sv, line:1:1, endln:8:10 |vpiPort: \_port: (i3), line:1:37, endln:1:39 |vpiParent: - \_module: work@encoder_4to2_gates (work@encoder_4to2_gates), file:${SURELOG_DIR}/tests/PrimTermExpr/dut.sv, line:1:1, endln:8:10 + \_module_inst: work@encoder_4to2_gates (work@encoder_4to2_gates), file:${SURELOG_DIR}/tests/PrimTermExpr/dut.sv, line:1:1, endln:8:10 |vpiName:i3 |vpiDirection:1 |vpiLowConn: @@ -430,11 +430,11 @@ design: (work@encoder_4to2_gates) |vpiTypedef: \_logic_typespec: , line:2:7, endln:2:7 |vpiInstance: - \_module: work@encoder_4to2_gates (work@encoder_4to2_gates), file:${SURELOG_DIR}/tests/PrimTermExpr/dut.sv, line:1:1, endln:8:10 + \_module_inst: work@encoder_4to2_gates (work@encoder_4to2_gates), file:${SURELOG_DIR}/tests/PrimTermExpr/dut.sv, line:1:1, endln:8:10 |vpiPort: \_port: (y), line:1:40, endln:1:41 |vpiParent: - \_module: work@encoder_4to2_gates (work@encoder_4to2_gates), file:${SURELOG_DIR}/tests/PrimTermExpr/dut.sv, line:1:1, endln:8:10 + \_module_inst: work@encoder_4to2_gates (work@encoder_4to2_gates), file:${SURELOG_DIR}/tests/PrimTermExpr/dut.sv, line:1:1, endln:8:10 |vpiName:y |vpiDirection:2 |vpiLowConn: @@ -468,11 +468,11 @@ design: (work@encoder_4to2_gates) |UINT:0 |vpiConstType:9 |vpiInstance: - \_module: work@encoder_4to2_gates (work@encoder_4to2_gates), file:${SURELOG_DIR}/tests/PrimTermExpr/dut.sv, line:1:1, endln:8:10 + \_module_inst: work@encoder_4to2_gates (work@encoder_4to2_gates), file:${SURELOG_DIR}/tests/PrimTermExpr/dut.sv, line:1:1, endln:8:10 |vpiPrimitive: \_gate: work@or (work@encoder_4to2_gates.o1), line:5:4, endln:5:19 |vpiParent: - \_module: work@encoder_4to2_gates (work@encoder_4to2_gates), file:${SURELOG_DIR}/tests/PrimTermExpr/dut.sv, line:1:1, endln:8:10 + \_module_inst: work@encoder_4to2_gates (work@encoder_4to2_gates), file:${SURELOG_DIR}/tests/PrimTermExpr/dut.sv, line:1:1, endln:8:10 |vpiDefName:work@or |vpiName:o1 |vpiFullName:work@encoder_4to2_gates.o1 @@ -527,7 +527,7 @@ design: (work@encoder_4to2_gates) |vpiPrimitive: \_gate: work@or (work@encoder_4to2_gates.o2), line:6:4, endln:6:19 |vpiParent: - \_module: work@encoder_4to2_gates (work@encoder_4to2_gates), file:${SURELOG_DIR}/tests/PrimTermExpr/dut.sv, line:1:1, endln:8:10 + \_module_inst: work@encoder_4to2_gates (work@encoder_4to2_gates), file:${SURELOG_DIR}/tests/PrimTermExpr/dut.sv, line:1:1, endln:8:10 |vpiDefName:work@or |vpiName:o2 |vpiFullName:work@encoder_4to2_gates.o2 diff --git a/tests/ProcForLoop/ProcForLoop.log b/tests/ProcForLoop/ProcForLoop.log index b74497547e..8495dce184 100644 --- a/tests/ProcForLoop/ProcForLoop.log +++ b/tests/ProcForLoop/ProcForLoop.log @@ -439,7 +439,7 @@ int_typespec 11 int_var 6 io_decl 11 logic_var 2 -module 2 +module_inst 2 operation 4 package 2 ref_obj 7 @@ -466,7 +466,7 @@ int_typespec 11 int_var 8 io_decl 22 logic_var 2 -module 2 +module_inst 2 operation 8 package 2 ref_obj 14 @@ -960,7 +960,7 @@ design: (work@top) \_int_typespec: |vpiSigned:1 |uhdmallModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/ProcForLoop/dut.sv, line:1:1, endln:11:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ProcForLoop/dut.sv, line:1:1, endln:11:10 |vpiParent: \_design: (work@top) |vpiFullName:work@top @@ -968,14 +968,14 @@ design: (work@top) |vpiTaskFunc: \_function: (work@top.foo), line:2:5, endln:9:16 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ProcForLoop/dut.sv, line:1:1, endln:11:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ProcForLoop/dut.sv, line:1:1, endln:11:10 |vpiName:foo |vpiFullName:work@top.foo |vpiVisibility:1 |vpiReturn: \_logic_var: |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ProcForLoop/dut.sv, line:1:1, endln:11:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ProcForLoop/dut.sv, line:1:1, endln:11:10 |vpiStmt: \_begin: (work@top.foo) |vpiParent: @@ -1178,23 +1178,23 @@ design: (work@top) |vpiConstType:9 |vpiName:f2 |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ProcForLoop/dut.sv, line:1:1, endln:11:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ProcForLoop/dut.sv, line:1:1, endln:11:10 |uhdmtopModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/ProcForLoop/dut.sv, line:1:1, endln:11:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ProcForLoop/dut.sv, line:1:1, endln:11:10 |vpiName:work@top |vpiDefName:work@top |vpiTop:1 |vpiTaskFunc: \_function: (work@top.foo), line:2:5, endln:9:16 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ProcForLoop/dut.sv, line:1:1, endln:11:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ProcForLoop/dut.sv, line:1:1, endln:11:10 |vpiName:foo |vpiFullName:work@top.foo |vpiVisibility:1 |vpiReturn: \_logic_var: |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ProcForLoop/dut.sv, line:1:1, endln:11:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ProcForLoop/dut.sv, line:1:1, endln:11:10 |vpiStmt: \_begin: (work@top.foo) |vpiParent: @@ -1353,7 +1353,7 @@ design: (work@top) \_constant: , line:7:15, endln:7:16 |vpiName:f2 |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ProcForLoop/dut.sv, line:1:1, endln:11:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ProcForLoop/dut.sv, line:1:1, endln:11:10 |vpiTopModule:1 =================== [ FATAL] : 0 diff --git a/tests/RangeInf/RangeInf.log b/tests/RangeInf/RangeInf.log index 71fca2090a..ce620ba91a 100644 --- a/tests/RangeInf/RangeInf.log +++ b/tests/RangeInf/RangeInf.log @@ -489,7 +489,7 @@ io_decl 11 logic_net 12 logic_typespec 14 logic_var 1 -module 4 +module_inst 4 operation 4 package 2 part_select 1 @@ -518,7 +518,7 @@ io_decl 22 logic_net 12 logic_typespec 14 logic_var 1 -module 4 +module_inst 4 operation 6 package 2 part_select 2 @@ -1015,7 +1015,7 @@ design: (work@FullAdder) \_int_typespec: |vpiSigned:1 |uhdmallModules: -\_module: work@FullAdder (work@FullAdder), file:${SURELOG_DIR}/tests/RangeInf/dut.sv, line:1:1, endln:10:10 +\_module_inst: work@FullAdder (work@FullAdder), file:${SURELOG_DIR}/tests/RangeInf/dut.sv, line:1:1, endln:10:10 |vpiParent: \_design: (work@FullAdder) |vpiFullName:work@FullAdder @@ -1023,46 +1023,46 @@ design: (work@FullAdder) |vpiNet: \_logic_net: (work@FullAdder.temp), line:6:14, endln:6:18 |vpiParent: - \_module: work@FullAdder (work@FullAdder), file:${SURELOG_DIR}/tests/RangeInf/dut.sv, line:1:1, endln:10:10 + \_module_inst: work@FullAdder (work@FullAdder), file:${SURELOG_DIR}/tests/RangeInf/dut.sv, line:1:1, endln:10:10 |vpiName:temp |vpiFullName:work@FullAdder.temp |vpiNetType:1 |vpiNet: \_logic_net: (work@FullAdder.A), line:1:18, endln:1:19 |vpiParent: - \_module: work@FullAdder (work@FullAdder), file:${SURELOG_DIR}/tests/RangeInf/dut.sv, line:1:1, endln:10:10 + \_module_inst: work@FullAdder (work@FullAdder), file:${SURELOG_DIR}/tests/RangeInf/dut.sv, line:1:1, endln:10:10 |vpiName:A |vpiFullName:work@FullAdder.A |vpiNet: \_logic_net: (work@FullAdder.B), line:1:20, endln:1:21 |vpiParent: - \_module: work@FullAdder (work@FullAdder), file:${SURELOG_DIR}/tests/RangeInf/dut.sv, line:1:1, endln:10:10 + \_module_inst: work@FullAdder (work@FullAdder), file:${SURELOG_DIR}/tests/RangeInf/dut.sv, line:1:1, endln:10:10 |vpiName:B |vpiFullName:work@FullAdder.B |vpiNet: \_logic_net: (work@FullAdder.Cin), line:1:22, endln:1:25 |vpiParent: - \_module: work@FullAdder (work@FullAdder), file:${SURELOG_DIR}/tests/RangeInf/dut.sv, line:1:1, endln:10:10 + \_module_inst: work@FullAdder (work@FullAdder), file:${SURELOG_DIR}/tests/RangeInf/dut.sv, line:1:1, endln:10:10 |vpiName:Cin |vpiFullName:work@FullAdder.Cin |vpiNet: \_logic_net: (work@FullAdder.Sum), line:1:26, endln:1:29 |vpiParent: - \_module: work@FullAdder (work@FullAdder), file:${SURELOG_DIR}/tests/RangeInf/dut.sv, line:1:1, endln:10:10 + \_module_inst: work@FullAdder (work@FullAdder), file:${SURELOG_DIR}/tests/RangeInf/dut.sv, line:1:1, endln:10:10 |vpiName:Sum |vpiFullName:work@FullAdder.Sum |vpiNetType:1 |vpiNet: \_logic_net: (work@FullAdder.Cout), line:1:30, endln:1:34 |vpiParent: - \_module: work@FullAdder (work@FullAdder), file:${SURELOG_DIR}/tests/RangeInf/dut.sv, line:1:1, endln:10:10 + \_module_inst: work@FullAdder (work@FullAdder), file:${SURELOG_DIR}/tests/RangeInf/dut.sv, line:1:1, endln:10:10 |vpiName:Cout |vpiFullName:work@FullAdder.Cout |vpiNetType:1 |vpiPort: \_port: (A), line:1:18, endln:1:19 |vpiParent: - \_module: work@FullAdder (work@FullAdder), file:${SURELOG_DIR}/tests/RangeInf/dut.sv, line:1:1, endln:10:10 + \_module_inst: work@FullAdder (work@FullAdder), file:${SURELOG_DIR}/tests/RangeInf/dut.sv, line:1:1, endln:10:10 |vpiName:A |vpiDirection:1 |vpiLowConn: @@ -1092,7 +1092,7 @@ design: (work@FullAdder) |vpiPort: \_port: (B), line:1:20, endln:1:21 |vpiParent: - \_module: work@FullAdder (work@FullAdder), file:${SURELOG_DIR}/tests/RangeInf/dut.sv, line:1:1, endln:10:10 + \_module_inst: work@FullAdder (work@FullAdder), file:${SURELOG_DIR}/tests/RangeInf/dut.sv, line:1:1, endln:10:10 |vpiName:B |vpiDirection:1 |vpiLowConn: @@ -1122,7 +1122,7 @@ design: (work@FullAdder) |vpiPort: \_port: (Cin), line:1:22, endln:1:25 |vpiParent: - \_module: work@FullAdder (work@FullAdder), file:${SURELOG_DIR}/tests/RangeInf/dut.sv, line:1:1, endln:10:10 + \_module_inst: work@FullAdder (work@FullAdder), file:${SURELOG_DIR}/tests/RangeInf/dut.sv, line:1:1, endln:10:10 |vpiName:Cin |vpiDirection:1 |vpiLowConn: @@ -1134,7 +1134,7 @@ design: (work@FullAdder) |vpiPort: \_port: (Sum), line:1:26, endln:1:29 |vpiParent: - \_module: work@FullAdder (work@FullAdder), file:${SURELOG_DIR}/tests/RangeInf/dut.sv, line:1:1, endln:10:10 + \_module_inst: work@FullAdder (work@FullAdder), file:${SURELOG_DIR}/tests/RangeInf/dut.sv, line:1:1, endln:10:10 |vpiName:Sum |vpiDirection:2 |vpiLowConn: @@ -1164,7 +1164,7 @@ design: (work@FullAdder) |vpiPort: \_port: (Cout), line:1:30, endln:1:34 |vpiParent: - \_module: work@FullAdder (work@FullAdder), file:${SURELOG_DIR}/tests/RangeInf/dut.sv, line:1:1, endln:10:10 + \_module_inst: work@FullAdder (work@FullAdder), file:${SURELOG_DIR}/tests/RangeInf/dut.sv, line:1:1, endln:10:10 |vpiName:Cout |vpiDirection:2 |vpiLowConn: @@ -1176,7 +1176,7 @@ design: (work@FullAdder) |vpiContAssign: \_cont_assign: , line:7:11, endln:7:23 |vpiParent: - \_module: work@FullAdder (work@FullAdder), file:${SURELOG_DIR}/tests/RangeInf/dut.sv, line:1:1, endln:10:10 + \_module_inst: work@FullAdder (work@FullAdder), file:${SURELOG_DIR}/tests/RangeInf/dut.sv, line:1:1, endln:10:10 |vpiRhs: \_operation: , line:7:16, endln:7:23 |vpiParent: @@ -1222,7 +1222,7 @@ design: (work@FullAdder) |vpiContAssign: \_cont_assign: , line:8:11, endln:8:24 |vpiParent: - \_module: work@FullAdder (work@FullAdder), file:${SURELOG_DIR}/tests/RangeInf/dut.sv, line:1:1, endln:10:10 + \_module_inst: work@FullAdder (work@FullAdder), file:${SURELOG_DIR}/tests/RangeInf/dut.sv, line:1:1, endln:10:10 |vpiRhs: \_part_select: , line:8:15, endln:8:24 |vpiParent: @@ -1256,7 +1256,7 @@ design: (work@FullAdder) |vpiContAssign: \_cont_assign: , line:9:11, endln:9:23 |vpiParent: - \_module: work@FullAdder (work@FullAdder), file:${SURELOG_DIR}/tests/RangeInf/dut.sv, line:1:1, endln:10:10 + \_module_inst: work@FullAdder (work@FullAdder), file:${SURELOG_DIR}/tests/RangeInf/dut.sv, line:1:1, endln:10:10 |vpiRhs: \_bit_select: (work@FullAdder.temp), line:9:16, endln:9:23 |vpiParent: @@ -1284,14 +1284,14 @@ design: (work@FullAdder) |vpiActual: \_logic_net: (work@FullAdder.Cout), line:1:30, endln:1:34 |uhdmtopModules: -\_module: work@FullAdder (work@FullAdder), file:${SURELOG_DIR}/tests/RangeInf/dut.sv, line:1:1, endln:10:10 +\_module_inst: work@FullAdder (work@FullAdder), file:${SURELOG_DIR}/tests/RangeInf/dut.sv, line:1:1, endln:10:10 |vpiName:work@FullAdder |vpiDefName:work@FullAdder |vpiTop:1 |vpiNet: \_logic_net: (work@FullAdder.temp), line:6:14, endln:6:18 |vpiParent: - \_module: work@FullAdder (work@FullAdder), file:${SURELOG_DIR}/tests/RangeInf/dut.sv, line:1:1, endln:10:10 + \_module_inst: work@FullAdder (work@FullAdder), file:${SURELOG_DIR}/tests/RangeInf/dut.sv, line:1:1, endln:10:10 |vpiTypespec: \_logic_typespec: , line:6:4, endln:6:14 |vpiRange: @@ -1318,7 +1318,7 @@ design: (work@FullAdder) |vpiNet: \_logic_net: (work@FullAdder.A), line:1:18, endln:1:19 |vpiParent: - \_module: work@FullAdder (work@FullAdder), file:${SURELOG_DIR}/tests/RangeInf/dut.sv, line:1:1, endln:10:10 + \_module_inst: work@FullAdder (work@FullAdder), file:${SURELOG_DIR}/tests/RangeInf/dut.sv, line:1:1, endln:10:10 |vpiTypespec: \_logic_typespec: , line:2:10, endln:2:15 |vpiRange: @@ -1344,7 +1344,7 @@ design: (work@FullAdder) |vpiNet: \_logic_net: (work@FullAdder.B), line:1:20, endln:1:21 |vpiParent: - \_module: work@FullAdder (work@FullAdder), file:${SURELOG_DIR}/tests/RangeInf/dut.sv, line:1:1, endln:10:10 + \_module_inst: work@FullAdder (work@FullAdder), file:${SURELOG_DIR}/tests/RangeInf/dut.sv, line:1:1, endln:10:10 |vpiTypespec: \_logic_typespec: , line:2:10, endln:2:15 |vpiName:B @@ -1352,7 +1352,7 @@ design: (work@FullAdder) |vpiNet: \_logic_net: (work@FullAdder.Cin), line:1:22, endln:1:25 |vpiParent: - \_module: work@FullAdder (work@FullAdder), file:${SURELOG_DIR}/tests/RangeInf/dut.sv, line:1:1, endln:10:10 + \_module_inst: work@FullAdder (work@FullAdder), file:${SURELOG_DIR}/tests/RangeInf/dut.sv, line:1:1, endln:10:10 |vpiTypespec: \_logic_typespec: , line:3:10, endln:3:10 |vpiName:Cin @@ -1360,7 +1360,7 @@ design: (work@FullAdder) |vpiNet: \_logic_net: (work@FullAdder.Sum), line:1:26, endln:1:29 |vpiParent: - \_module: work@FullAdder (work@FullAdder), file:${SURELOG_DIR}/tests/RangeInf/dut.sv, line:1:1, endln:10:10 + \_module_inst: work@FullAdder (work@FullAdder), file:${SURELOG_DIR}/tests/RangeInf/dut.sv, line:1:1, endln:10:10 |vpiTypespec: \_logic_typespec: , line:4:11, endln:4:21 |vpiRange: @@ -1387,7 +1387,7 @@ design: (work@FullAdder) |vpiNet: \_logic_net: (work@FullAdder.Cout), line:1:30, endln:1:34 |vpiParent: - \_module: work@FullAdder (work@FullAdder), file:${SURELOG_DIR}/tests/RangeInf/dut.sv, line:1:1, endln:10:10 + \_module_inst: work@FullAdder (work@FullAdder), file:${SURELOG_DIR}/tests/RangeInf/dut.sv, line:1:1, endln:10:10 |vpiTypespec: \_logic_typespec: , line:5:11, endln:5:15 |vpiName:Cout @@ -1397,7 +1397,7 @@ design: (work@FullAdder) |vpiPort: \_port: (A), line:1:18, endln:1:19 |vpiParent: - \_module: work@FullAdder (work@FullAdder), file:${SURELOG_DIR}/tests/RangeInf/dut.sv, line:1:1, endln:10:10 + \_module_inst: work@FullAdder (work@FullAdder), file:${SURELOG_DIR}/tests/RangeInf/dut.sv, line:1:1, endln:10:10 |vpiName:A |vpiDirection:1 |vpiLowConn: @@ -1431,11 +1431,11 @@ design: (work@FullAdder) |UINT:0 |vpiConstType:9 |vpiInstance: - \_module: work@FullAdder (work@FullAdder), file:${SURELOG_DIR}/tests/RangeInf/dut.sv, line:1:1, endln:10:10 + \_module_inst: work@FullAdder (work@FullAdder), file:${SURELOG_DIR}/tests/RangeInf/dut.sv, line:1:1, endln:10:10 |vpiPort: \_port: (B), line:1:20, endln:1:21 |vpiParent: - \_module: work@FullAdder (work@FullAdder), file:${SURELOG_DIR}/tests/RangeInf/dut.sv, line:1:1, endln:10:10 + \_module_inst: work@FullAdder (work@FullAdder), file:${SURELOG_DIR}/tests/RangeInf/dut.sv, line:1:1, endln:10:10 |vpiName:B |vpiDirection:1 |vpiLowConn: @@ -1449,11 +1449,11 @@ design: (work@FullAdder) |vpiTypedef: \_logic_typespec: , line:2:10, endln:2:15 |vpiInstance: - \_module: work@FullAdder (work@FullAdder), file:${SURELOG_DIR}/tests/RangeInf/dut.sv, line:1:1, endln:10:10 + \_module_inst: work@FullAdder (work@FullAdder), file:${SURELOG_DIR}/tests/RangeInf/dut.sv, line:1:1, endln:10:10 |vpiPort: \_port: (Cin), line:1:22, endln:1:25 |vpiParent: - \_module: work@FullAdder (work@FullAdder), file:${SURELOG_DIR}/tests/RangeInf/dut.sv, line:1:1, endln:10:10 + \_module_inst: work@FullAdder (work@FullAdder), file:${SURELOG_DIR}/tests/RangeInf/dut.sv, line:1:1, endln:10:10 |vpiName:Cin |vpiDirection:1 |vpiLowConn: @@ -1467,11 +1467,11 @@ design: (work@FullAdder) |vpiTypedef: \_logic_typespec: , line:3:10, endln:3:10 |vpiInstance: - \_module: work@FullAdder (work@FullAdder), file:${SURELOG_DIR}/tests/RangeInf/dut.sv, line:1:1, endln:10:10 + \_module_inst: work@FullAdder (work@FullAdder), file:${SURELOG_DIR}/tests/RangeInf/dut.sv, line:1:1, endln:10:10 |vpiPort: \_port: (Sum), line:1:26, endln:1:29 |vpiParent: - \_module: work@FullAdder (work@FullAdder), file:${SURELOG_DIR}/tests/RangeInf/dut.sv, line:1:1, endln:10:10 + \_module_inst: work@FullAdder (work@FullAdder), file:${SURELOG_DIR}/tests/RangeInf/dut.sv, line:1:1, endln:10:10 |vpiName:Sum |vpiDirection:2 |vpiLowConn: @@ -1505,11 +1505,11 @@ design: (work@FullAdder) |UINT:0 |vpiConstType:9 |vpiInstance: - \_module: work@FullAdder (work@FullAdder), file:${SURELOG_DIR}/tests/RangeInf/dut.sv, line:1:1, endln:10:10 + \_module_inst: work@FullAdder (work@FullAdder), file:${SURELOG_DIR}/tests/RangeInf/dut.sv, line:1:1, endln:10:10 |vpiPort: \_port: (Cout), line:1:30, endln:1:34 |vpiParent: - \_module: work@FullAdder (work@FullAdder), file:${SURELOG_DIR}/tests/RangeInf/dut.sv, line:1:1, endln:10:10 + \_module_inst: work@FullAdder (work@FullAdder), file:${SURELOG_DIR}/tests/RangeInf/dut.sv, line:1:1, endln:10:10 |vpiName:Cout |vpiDirection:2 |vpiLowConn: @@ -1523,11 +1523,11 @@ design: (work@FullAdder) |vpiTypedef: \_logic_typespec: , line:5:11, endln:5:15 |vpiInstance: - \_module: work@FullAdder (work@FullAdder), file:${SURELOG_DIR}/tests/RangeInf/dut.sv, line:1:1, endln:10:10 + \_module_inst: work@FullAdder (work@FullAdder), file:${SURELOG_DIR}/tests/RangeInf/dut.sv, line:1:1, endln:10:10 |vpiContAssign: \_cont_assign: , line:7:11, endln:7:23 |vpiParent: - \_module: work@FullAdder (work@FullAdder), file:${SURELOG_DIR}/tests/RangeInf/dut.sv, line:1:1, endln:10:10 + \_module_inst: work@FullAdder (work@FullAdder), file:${SURELOG_DIR}/tests/RangeInf/dut.sv, line:1:1, endln:10:10 |vpiRhs: \_operation: , line:7:16, endln:7:23 |vpiParent: @@ -1573,7 +1573,7 @@ design: (work@FullAdder) |vpiContAssign: \_cont_assign: , line:8:11, endln:8:24 |vpiParent: - \_module: work@FullAdder (work@FullAdder), file:${SURELOG_DIR}/tests/RangeInf/dut.sv, line:1:1, endln:10:10 + \_module_inst: work@FullAdder (work@FullAdder), file:${SURELOG_DIR}/tests/RangeInf/dut.sv, line:1:1, endln:10:10 |vpiRhs: \_part_select: , line:8:15, endln:8:24 |vpiParent: @@ -1601,7 +1601,7 @@ design: (work@FullAdder) |vpiContAssign: \_cont_assign: , line:9:11, endln:9:23 |vpiParent: - \_module: work@FullAdder (work@FullAdder), file:${SURELOG_DIR}/tests/RangeInf/dut.sv, line:1:1, endln:10:10 + \_module_inst: work@FullAdder (work@FullAdder), file:${SURELOG_DIR}/tests/RangeInf/dut.sv, line:1:1, endln:10:10 |vpiRhs: \_bit_select: (work@FullAdder.temp), line:9:16, endln:9:23 |vpiParent: diff --git a/tests/RangeSelect/RangeSelect.log b/tests/RangeSelect/RangeSelect.log index 40735f0dad..30e2c82414 100644 --- a/tests/RangeSelect/RangeSelect.log +++ b/tests/RangeSelect/RangeSelect.log @@ -36,7 +36,7 @@ indexed_part_select 2 logic_net 4 logic_typespec 3 logic_var 2 -module 3 +module_inst 3 operation 1 range 4 ref_obj 4 @@ -56,7 +56,7 @@ indexed_part_select 2 logic_net 4 logic_typespec 3 logic_var 2 -module 3 +module_inst 3 operation 1 range 4 ref_obj 4 @@ -77,17 +77,17 @@ design: (work@top) |vpiElaborated:1 |vpiName:work@top |uhdmallModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/RangeSelect/dut.sv, line:1:1, endln:11:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/RangeSelect/dut.sv, line:1:1, endln:11:10 |vpiParent: \_design: (work@top) |vpiFullName:work@top |vpiTypedef: \_struct_typespec: (tl_h2d_t), line:2:12, endln:2:18 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/RangeSelect/dut.sv, line:1:1, endln:11:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/RangeSelect/dut.sv, line:1:1, endln:11:10 |vpiName:tl_h2d_t |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/RangeSelect/dut.sv, line:1:1, endln:11:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/RangeSelect/dut.sv, line:1:1, endln:11:10 |vpiPacked:1 |vpiTypespecMember: \_typespec_member: (source), line:3:19, endln:3:25 @@ -127,36 +127,36 @@ design: (work@top) |vpiNet: \_logic_net: (work@top.a), line:6:13, endln:6:14 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/RangeSelect/dut.sv, line:1:1, endln:11:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/RangeSelect/dut.sv, line:1:1, endln:11:10 |vpiName:a |vpiFullName:work@top.a |vpiNet: \_logic_net: (work@top.b), line:7:13, endln:7:14 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/RangeSelect/dut.sv, line:1:1, endln:11:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/RangeSelect/dut.sv, line:1:1, endln:11:10 |vpiName:b |vpiFullName:work@top.b |vpiNet: \_logic_net: (work@top.c), line:8:10, endln:8:11 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/RangeSelect/dut.sv, line:1:1, endln:11:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/RangeSelect/dut.sv, line:1:1, endln:11:10 |vpiName:c |vpiFullName:work@top.c |vpiNetType:36 |vpiNet: \_logic_net: (work@top.d), line:9:16, endln:9:17 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/RangeSelect/dut.sv, line:1:1, endln:11:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/RangeSelect/dut.sv, line:1:1, endln:11:10 |vpiName:d |vpiFullName:work@top.d |vpiNetType:36 |uhdmtopModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/RangeSelect/dut.sv, line:1:1, endln:11:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/RangeSelect/dut.sv, line:1:1, endln:11:10 |vpiName:work@top |vpiVariables: \_logic_var: (work@top.c), line:8:10, endln:8:33 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/RangeSelect/dut.sv, line:1:1, endln:11:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/RangeSelect/dut.sv, line:1:1, endln:11:10 |vpiTypespec: \_logic_typespec: , line:8:4, endln:8:9 |vpiName:c @@ -201,7 +201,7 @@ design: (work@top) |vpiVariables: \_logic_var: (work@top.d), line:9:16, endln:9:36 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/RangeSelect/dut.sv, line:1:1, endln:11:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/RangeSelect/dut.sv, line:1:1, endln:11:10 |vpiTypespec: \_logic_typespec: , line:9:4, endln:9:15 |vpiRange: @@ -279,7 +279,7 @@ design: (work@top) |vpiNet: \_struct_net: (work@top.b), line:7:13, endln:7:14 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/RangeSelect/dut.sv, line:1:1, endln:11:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/RangeSelect/dut.sv, line:1:1, endln:11:10 |vpiTypespec: \_struct_typespec: (tl_h2d_t), line:2:12, endln:2:18 |vpiName:b @@ -287,7 +287,7 @@ design: (work@top) |vpiArrayNet: \_array_net: (work@top.a), line:6:13, endln:6:14 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/RangeSelect/dut.sv, line:1:1, endln:11:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/RangeSelect/dut.sv, line:1:1, endln:11:10 |vpiSize:4 |vpiName:a |vpiFullName:work@top.a diff --git a/tests/ReorderPatt/ReorderPatt.log b/tests/ReorderPatt/ReorderPatt.log index 8965311a40..3e161106f8 100644 --- a/tests/ReorderPatt/ReorderPatt.log +++ b/tests/ReorderPatt/ReorderPatt.log @@ -123,7 +123,7 @@ cont_assign 2 design 1 int_typespec 4 logic_net 1 -module 5 +module_inst 5 operation 4 param_assign 4 parameter 5 @@ -140,7 +140,7 @@ cont_assign 3 design 1 int_typespec 4 logic_net 1 -module 5 +module_inst 5 operation 4 param_assign 4 parameter 5 @@ -160,14 +160,14 @@ design: (work@top) |vpiElaborated:1 |vpiName:work@top |uhdmallModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/ReorderPatt/dut.sv, line:1:1, endln:5:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ReorderPatt/dut.sv, line:1:1, endln:5:10 |vpiParent: \_design: (work@top) |vpiFullName:work@top |vpiParameter: \_parameter: (work@top.x), line:2:18, endln:2:19 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ReorderPatt/dut.sv, line:1:1, endln:5:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ReorderPatt/dut.sv, line:1:1, endln:5:10 |vpiSize:1 |vpiTypespec: \_array_typespec: @@ -204,13 +204,13 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.a), line:3:14, endln:3:15 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ReorderPatt/dut.sv, line:1:1, endln:5:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ReorderPatt/dut.sv, line:1:1, endln:5:10 |vpiName:a |vpiFullName:work@top.a |vpiParamAssign: \_param_assign: , line:2:18, endln:2:37 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ReorderPatt/dut.sv, line:1:1, endln:5:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ReorderPatt/dut.sv, line:1:1, endln:5:10 |vpiRhs: \_operation: , line:2:28, endln:2:37 |vpiOpType:75 @@ -231,7 +231,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:3:14, endln:3:22 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ReorderPatt/dut.sv, line:1:1, endln:5:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ReorderPatt/dut.sv, line:1:1, endln:5:10 |vpiRhs: \_bit_select: (x), line:3:18, endln:3:22 |vpiParent: @@ -252,7 +252,7 @@ design: (work@top) |vpiContAssign: \_cont_assign: , line:4:11, endln:4:19 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ReorderPatt/dut.sv, line:1:1, endln:5:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ReorderPatt/dut.sv, line:1:1, endln:5:10 |vpiRhs: \_bit_select: (work@top.x), line:4:15, endln:4:19 |vpiParent: @@ -280,12 +280,12 @@ design: (work@top) |vpiActual: \_logic_net: (b) |uhdmtopModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/ReorderPatt/dut.sv, line:1:1, endln:5:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ReorderPatt/dut.sv, line:1:1, endln:5:10 |vpiName:work@top |vpiParameter: \_parameter: (work@top.x), line:2:18, endln:2:19 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ReorderPatt/dut.sv, line:1:1, endln:5:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ReorderPatt/dut.sv, line:1:1, endln:5:10 |vpiSize:1 |vpiTypespec: \_array_typespec: @@ -342,13 +342,13 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.a), line:3:14, endln:3:15 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ReorderPatt/dut.sv, line:1:1, endln:5:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ReorderPatt/dut.sv, line:1:1, endln:5:10 |vpiName:a |vpiFullName:work@top.a |vpiParamAssign: \_param_assign: , line:2:18, endln:2:37 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ReorderPatt/dut.sv, line:1:1, endln:5:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ReorderPatt/dut.sv, line:1:1, endln:5:10 |vpiRhs: \_operation: , line:2:28, endln:2:37 |vpiParent: @@ -405,7 +405,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:3:14, endln:3:22 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ReorderPatt/dut.sv, line:1:1, endln:5:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ReorderPatt/dut.sv, line:1:1, endln:5:10 |vpiRhs: \_constant: , line:3:18, endln:3:22 |vpiDecompile:11 @@ -424,7 +424,7 @@ design: (work@top) |vpiContAssign: \_cont_assign: , line:4:11, endln:4:19 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/ReorderPatt/dut.sv, line:1:1, endln:5:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ReorderPatt/dut.sv, line:1:1, endln:5:10 |vpiRhs: \_constant: , line:2:34, endln:2:36 |vpiParent: diff --git a/tests/RepeatStmt/RepeatStmt.log b/tests/RepeatStmt/RepeatStmt.log index 843b82725e..f79801540b 100644 --- a/tests/RepeatStmt/RepeatStmt.log +++ b/tests/RepeatStmt/RepeatStmt.log @@ -201,7 +201,7 @@ gen_scope_array 2 io_decl 1 logic_typespec 5 logic_var 4 -module 6 +module_inst 6 named_begin 1 operation 2 param_assign 8 @@ -224,7 +224,7 @@ gen_scope_array 3 io_decl 2 logic_typespec 5 logic_var 4 -module 7 +module_inst 7 named_begin 2 operation 3 param_assign 8 @@ -246,27 +246,27 @@ design: (work@constfunc11) |vpiElaborated:1 |vpiName:work@constfunc11 |uhdmallModules: -\_module: work@GOOD (work@GOOD), file:${SURELOG_DIR}/tests/RepeatStmt/dut.sv, line:1:1, endln:2:10 +\_module_inst: work@GOOD (work@GOOD), file:${SURELOG_DIR}/tests/RepeatStmt/dut.sv, line:1:1, endln:2:10 |vpiParent: \_design: (work@constfunc11) |vpiFullName:work@GOOD |vpiDefName:work@GOOD |uhdmallModules: -\_module: work@constfunc11 (work@constfunc11), file:${SURELOG_DIR}/tests/RepeatStmt/dut.sv, line:4:1, endln:23:10 +\_module_inst: work@constfunc11 (work@constfunc11), file:${SURELOG_DIR}/tests/RepeatStmt/dut.sv, line:4:1, endln:23:10 |vpiParent: \_design: (work@constfunc11) |vpiFullName:work@constfunc11 |vpiParameter: \_parameter: (work@constfunc11.val0), line:17:12, endln:17:16 |vpiParent: - \_module: work@constfunc11 (work@constfunc11), file:${SURELOG_DIR}/tests/RepeatStmt/dut.sv, line:4:1, endln:23:10 + \_module_inst: work@constfunc11 (work@constfunc11), file:${SURELOG_DIR}/tests/RepeatStmt/dut.sv, line:4:1, endln:23:10 |vpiLocalParam:1 |vpiName:val0 |vpiFullName:work@constfunc11.val0 |vpiParamAssign: \_param_assign: , line:17:12, endln:17:26 |vpiParent: - \_module: work@constfunc11 (work@constfunc11), file:${SURELOG_DIR}/tests/RepeatStmt/dut.sv, line:4:1, endln:23:10 + \_module_inst: work@constfunc11 (work@constfunc11), file:${SURELOG_DIR}/tests/RepeatStmt/dut.sv, line:4:1, endln:23:10 |vpiRhs: \_func_call: (pow2), line:17:19, endln:17:23 |vpiArgument: @@ -286,7 +286,7 @@ design: (work@constfunc11) |vpiTaskFunc: \_function: (work@constfunc11.pow2), line:6:1, endln:15:12 |vpiParent: - \_module: work@constfunc11 (work@constfunc11), file:${SURELOG_DIR}/tests/RepeatStmt/dut.sv, line:4:1, endln:23:10 + \_module_inst: work@constfunc11 (work@constfunc11), file:${SURELOG_DIR}/tests/RepeatStmt/dut.sv, line:4:1, endln:23:10 |vpiName:pow2 |vpiFullName:work@constfunc11.pow2 |vpiVisibility:1 @@ -313,7 +313,7 @@ design: (work@constfunc11) |UINT:0 |vpiConstType:9 |vpiParent: - \_module: work@constfunc11 (work@constfunc11), file:${SURELOG_DIR}/tests/RepeatStmt/dut.sv, line:4:1, endln:23:10 + \_module_inst: work@constfunc11 (work@constfunc11), file:${SURELOG_DIR}/tests/RepeatStmt/dut.sv, line:4:1, endln:23:10 |vpiIODecl: \_io_decl: (x), line:6:34, endln:6:35 |vpiDirection:1 @@ -419,21 +419,21 @@ design: (work@constfunc11) |vpiActual: \_logic_var: (pow2), line:6:10, endln:6:16 |vpiInstance: - \_module: work@constfunc11 (work@constfunc11), file:${SURELOG_DIR}/tests/RepeatStmt/dut.sv, line:4:1, endln:23:10 + \_module_inst: work@constfunc11 (work@constfunc11), file:${SURELOG_DIR}/tests/RepeatStmt/dut.sv, line:4:1, endln:23:10 |uhdmtopModules: -\_module: work@constfunc11 (work@constfunc11), file:${SURELOG_DIR}/tests/RepeatStmt/dut.sv, line:4:1, endln:23:10 +\_module_inst: work@constfunc11 (work@constfunc11), file:${SURELOG_DIR}/tests/RepeatStmt/dut.sv, line:4:1, endln:23:10 |vpiName:work@constfunc11 |vpiParameter: \_parameter: (work@constfunc11.val0), line:17:12, endln:17:16 |vpiParent: - \_module: work@constfunc11 (work@constfunc11), file:${SURELOG_DIR}/tests/RepeatStmt/dut.sv, line:4:1, endln:23:10 + \_module_inst: work@constfunc11 (work@constfunc11), file:${SURELOG_DIR}/tests/RepeatStmt/dut.sv, line:4:1, endln:23:10 |vpiLocalParam:1 |vpiName:val0 |vpiFullName:work@constfunc11.val0 |vpiParamAssign: \_param_assign: , line:17:12, endln:17:26 |vpiParent: - \_module: work@constfunc11 (work@constfunc11), file:${SURELOG_DIR}/tests/RepeatStmt/dut.sv, line:4:1, endln:23:10 + \_module_inst: work@constfunc11 (work@constfunc11), file:${SURELOG_DIR}/tests/RepeatStmt/dut.sv, line:4:1, endln:23:10 |vpiRhs: \_constant: , line:17:19, endln:17:26 |vpiDecompile:16 @@ -447,14 +447,14 @@ design: (work@constfunc11) |vpiTaskFunc: \_function: (work@constfunc11.pow2), line:6:1, endln:15:12 |vpiParent: - \_module: work@constfunc11 (work@constfunc11), file:${SURELOG_DIR}/tests/RepeatStmt/dut.sv, line:4:1, endln:23:10 + \_module_inst: work@constfunc11 (work@constfunc11), file:${SURELOG_DIR}/tests/RepeatStmt/dut.sv, line:4:1, endln:23:10 |vpiName:pow2 |vpiFullName:work@constfunc11.pow2 |vpiVisibility:1 |vpiReturn: \_logic_var: , line:6:10, endln:6:16 |vpiParent: - \_module: work@constfunc11 (work@constfunc11), file:${SURELOG_DIR}/tests/RepeatStmt/dut.sv, line:4:1, endln:23:10 + \_module_inst: work@constfunc11 (work@constfunc11), file:${SURELOG_DIR}/tests/RepeatStmt/dut.sv, line:4:1, endln:23:10 |vpiIODecl: \_io_decl: (x), line:6:34, endln:6:35 |vpiParent: @@ -532,12 +532,12 @@ design: (work@constfunc11) |vpiActual: \_logic_var: , line:6:10, endln:6:16 |vpiInstance: - \_module: work@constfunc11 (work@constfunc11), file:${SURELOG_DIR}/tests/RepeatStmt/dut.sv, line:4:1, endln:23:10 + \_module_inst: work@constfunc11 (work@constfunc11), file:${SURELOG_DIR}/tests/RepeatStmt/dut.sv, line:4:1, endln:23:10 |vpiTopModule:1 |vpiGenScopeArray: \_gen_scope_array: (work@constfunc11.genblk1), line:19:1, endln:21:4 |vpiParent: - \_module: work@constfunc11 (work@constfunc11), file:${SURELOG_DIR}/tests/RepeatStmt/dut.sv, line:4:1, endln:23:10 + \_module_inst: work@constfunc11 (work@constfunc11), file:${SURELOG_DIR}/tests/RepeatStmt/dut.sv, line:4:1, endln:23:10 |vpiName:genblk1 |vpiFullName:work@constfunc11.genblk1 |vpiGenScope: @@ -545,8 +545,8 @@ design: (work@constfunc11) |vpiParent: \_gen_scope_array: (work@constfunc11.genblk1), line:19:1, endln:21:4 |vpiFullName:work@constfunc11.genblk1 - |vpiModule: - \_module: work@GOOD (work@constfunc11.genblk1.good), file:${SURELOG_DIR}/tests/RepeatStmt/dut.sv, line:20:4, endln:20:16 + |vpiModuleInst: + \_module_inst: work@GOOD (work@constfunc11.genblk1.good), file:${SURELOG_DIR}/tests/RepeatStmt/dut.sv, line:20:4, endln:20:16 |vpiParent: \_gen_scope: (work@constfunc11.genblk1) |vpiName:good diff --git a/tests/Rom/Rom.log b/tests/Rom/Rom.log index 13af071bb6..46ccfcab4d 100644 --- a/tests/Rom/Rom.log +++ b/tests/Rom/Rom.log @@ -456,7 +456,7 @@ io_decl 11 logic_net 3 logic_typespec 2 logic_var 3 -module 4 +module_inst 4 operation 29 package 2 param_assign 2 @@ -485,7 +485,7 @@ io_decl 22 logic_net 3 logic_typespec 2 logic_var 3 -module 4 +module_inst 4 operation 29 package 2 param_assign 2 @@ -982,14 +982,14 @@ design: (work@top) \_int_typespec: |vpiSigned:1 |uhdmallModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/Rom/dut.sv, line:1:1, endln:20:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/Rom/dut.sv, line:1:1, endln:20:10 |vpiParent: \_design: (work@top) |vpiFullName:work@top |vpiParameter: \_parameter: (work@top.RhoOffset), line:13:18, endln:13:27 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/Rom/dut.sv, line:1:1, endln:20:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/Rom/dut.sv, line:1:1, endln:20:10 |vpiSize:1 |vpiTypespec: \_array_typespec: @@ -1065,7 +1065,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:13:18, endln:17:7 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/Rom/dut.sv, line:1:1, endln:20:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/Rom/dut.sv, line:1:1, endln:20:10 |vpiRhs: \_operation: , line:13:38, endln:17:7 |vpiOpType:75 @@ -1109,24 +1109,24 @@ design: (work@top) |vpiNet: \_logic_net: (work@top.mem), line:3:33, endln:3:36 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/Rom/dut.sv, line:1:1, endln:20:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/Rom/dut.sv, line:1:1, endln:20:10 |vpiName:mem |vpiFullName:work@top.mem |vpiNetType:36 |vpiNet: \_logic_net: (work@top.sbox_enc), line:8:20, endln:8:28 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/Rom/dut.sv, line:1:1, endln:20:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/Rom/dut.sv, line:1:1, endln:20:10 |vpiName:sbox_enc |vpiFullName:work@top.sbox_enc |vpiNetType:36 |uhdmtopModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/Rom/dut.sv, line:1:1, endln:20:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/Rom/dut.sv, line:1:1, endln:20:10 |vpiName:work@top |vpiVariables: \_logic_var: (work@top.mem), line:3:33, endln:6:7 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/Rom/dut.sv, line:1:1, endln:20:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/Rom/dut.sv, line:1:1, endln:20:10 |vpiTypespec: \_logic_typespec: , line:3:7, endln:3:32 |vpiRange: @@ -1251,7 +1251,7 @@ design: (work@top) |vpiVariables: \_array_var: (work@top.sbox_enc), line:8:20, endln:8:34 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/Rom/dut.sv, line:1:1, endln:20:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/Rom/dut.sv, line:1:1, endln:20:10 |vpiSize:256 |vpiTypespec: \_array_typespec: @@ -1350,7 +1350,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.RhoOffset), line:13:18, endln:13:27 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/Rom/dut.sv, line:1:1, endln:20:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/Rom/dut.sv, line:1:1, endln:20:10 |vpiSize:1 |vpiTypespec: \_array_typespec: @@ -1496,7 +1496,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:13:18, endln:17:7 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/Rom/dut.sv, line:1:1, endln:20:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/Rom/dut.sv, line:1:1, endln:20:10 |vpiRhs: \_operation: , line:13:38, endln:17:7 |vpiParent: diff --git a/tests/ScalarParam/ScalarParam.log b/tests/ScalarParam/ScalarParam.log index f2ec947a74..a6c4bdfafb 100644 --- a/tests/ScalarParam/ScalarParam.log +++ b/tests/ScalarParam/ScalarParam.log @@ -140,7 +140,7 @@ constant 10 design 1 gen_scope 2 gen_scope_array 2 -module 9 +module_inst 9 operation 1 param_assign 2 parameter 2 @@ -154,7 +154,7 @@ constant 10 design 1 gen_scope 3 gen_scope_array 3 -module 10 +module_inst 10 operation 1 param_assign 2 parameter 2 @@ -173,26 +173,26 @@ design: (work@dut) |vpiElaborated:1 |vpiName:work@dut |uhdmallModules: -\_module: work@GOOD (work@GOOD), file:${SURELOG_DIR}/tests/ScalarParam/dut.sv, line:1:1, endln:2:10 +\_module_inst: work@GOOD (work@GOOD), file:${SURELOG_DIR}/tests/ScalarParam/dut.sv, line:1:1, endln:2:10 |vpiParent: \_design: (work@dut) |vpiFullName:work@GOOD |vpiDefName:work@GOOD |uhdmallModules: -\_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/ScalarParam/dut.sv, line:12:1, endln:18:10 +\_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/ScalarParam/dut.sv, line:12:1, endln:18:10 |vpiParent: \_design: (work@dut) |vpiFullName:work@dut |vpiDefName:work@dut |uhdmallModules: -\_module: work@param_test (work@param_test), file:${SURELOG_DIR}/tests/ScalarParam/dut.sv, line:4:1, endln:10:10 +\_module_inst: work@param_test (work@param_test), file:${SURELOG_DIR}/tests/ScalarParam/dut.sv, line:4:1, endln:10:10 |vpiParent: \_design: (work@dut) |vpiFullName:work@param_test |vpiParameter: \_parameter: (work@param_test.DRspDepth), line:5:25, endln:5:34 |vpiParent: - \_module: work@param_test (work@param_test), file:${SURELOG_DIR}/tests/ScalarParam/dut.sv, line:4:1, endln:10:10 + \_module_inst: work@param_test (work@param_test), file:${SURELOG_DIR}/tests/ScalarParam/dut.sv, line:4:1, endln:10:10 |HEX:2 |vpiTypespec: \_bit_typespec: , line:5:11, endln:5:20 @@ -222,7 +222,7 @@ design: (work@dut) |vpiParamAssign: \_param_assign: , line:5:25, endln:5:41 |vpiParent: - \_module: work@param_test (work@param_test), file:${SURELOG_DIR}/tests/ScalarParam/dut.sv, line:4:1, endln:10:10 + \_module_inst: work@param_test (work@param_test), file:${SURELOG_DIR}/tests/ScalarParam/dut.sv, line:4:1, endln:10:10 |vpiRhs: \_constant: , line:5:37, endln:5:41 |vpiDecompile:4'h2 @@ -235,21 +235,21 @@ design: (work@dut) \_parameter: (work@param_test.DRspDepth), line:5:25, endln:5:34 |vpiDefName:work@param_test |uhdmtopModules: -\_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/ScalarParam/dut.sv, line:12:1, endln:18:10 +\_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/ScalarParam/dut.sv, line:12:1, endln:18:10 |vpiName:work@dut |vpiDefName:work@dut |vpiTop:1 |vpiTopModule:1 - |vpiModule: - \_module: work@param_test (work@dut.t1), file:${SURELOG_DIR}/tests/ScalarParam/dut.sv, line:14:3, endln:16:11 + |vpiModuleInst: + \_module_inst: work@param_test (work@dut.t1), file:${SURELOG_DIR}/tests/ScalarParam/dut.sv, line:14:3, endln:16:11 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/ScalarParam/dut.sv, line:12:1, endln:18:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/ScalarParam/dut.sv, line:12:1, endln:18:10 |vpiName:t1 |vpiFullName:work@dut.t1 |vpiParameter: \_parameter: (work@dut.t1.DRspDepth), line:5:25, endln:5:34 |vpiParent: - \_module: work@param_test (work@dut.t1), file:${SURELOG_DIR}/tests/ScalarParam/dut.sv, line:14:3, endln:16:11 + \_module_inst: work@param_test (work@dut.t1), file:${SURELOG_DIR}/tests/ScalarParam/dut.sv, line:14:3, endln:16:11 |HEX:2 |vpiTypespec: \_bit_typespec: , line:5:11, endln:5:20 @@ -281,7 +281,7 @@ design: (work@dut) |vpiParamAssign: \_param_assign: , line:5:25, endln:5:41 |vpiParent: - \_module: work@param_test (work@dut.t1), file:${SURELOG_DIR}/tests/ScalarParam/dut.sv, line:14:3, endln:16:11 + \_module_inst: work@param_test (work@dut.t1), file:${SURELOG_DIR}/tests/ScalarParam/dut.sv, line:14:3, endln:16:11 |vpiOverriden:1 |vpiRhs: \_constant: , line:5:37, endln:5:41 @@ -297,11 +297,11 @@ design: (work@dut) |vpiDefFile:${SURELOG_DIR}/tests/ScalarParam/dut.sv |vpiDefLineNo:4 |vpiInstance: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/ScalarParam/dut.sv, line:12:1, endln:18:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/ScalarParam/dut.sv, line:12:1, endln:18:10 |vpiGenScopeArray: \_gen_scope_array: (work@dut.t1.genblk1), line:7:4, endln:9:7 |vpiParent: - \_module: work@param_test (work@dut.t1), file:${SURELOG_DIR}/tests/ScalarParam/dut.sv, line:14:3, endln:16:11 + \_module_inst: work@param_test (work@dut.t1), file:${SURELOG_DIR}/tests/ScalarParam/dut.sv, line:14:3, endln:16:11 |vpiName:genblk1 |vpiFullName:work@dut.t1.genblk1 |vpiGenScope: @@ -309,8 +309,8 @@ design: (work@dut) |vpiParent: \_gen_scope_array: (work@dut.t1.genblk1), line:7:4, endln:9:7 |vpiFullName:work@dut.t1.genblk1 - |vpiModule: - \_module: work@GOOD (work@dut.t1.genblk1.good), file:${SURELOG_DIR}/tests/ScalarParam/dut.sv, line:8:6, endln:8:18 + |vpiModuleInst: + \_module_inst: work@GOOD (work@dut.t1.genblk1.good), file:${SURELOG_DIR}/tests/ScalarParam/dut.sv, line:8:6, endln:8:18 |vpiParent: \_gen_scope: (work@dut.t1.genblk1) |vpiName:good diff --git a/tests/SelectHierPath/SelectHierPath.log b/tests/SelectHierPath/SelectHierPath.log index e987e3704f..95873aff92 100644 --- a/tests/SelectHierPath/SelectHierPath.log +++ b/tests/SelectHierPath/SelectHierPath.log @@ -113,7 +113,7 @@ design 1 hier_path 1 int_typespec 1 logic_net 2 -module 4 +module_inst 4 operation 1 range 1 ref_obj 4 @@ -132,7 +132,7 @@ design 1 hier_path 2 int_typespec 1 logic_net 2 -module 4 +module_inst 4 operation 1 range 1 ref_obj 8 @@ -153,7 +153,7 @@ design: (work@IntegerRegisterWriteStage) |vpiElaborated:1 |vpiName:work@IntegerRegisterWriteStage |uhdmallModules: -\_module: work@IntegerRegisterWriteStage (work@IntegerRegisterWriteStage), file:${SURELOG_DIR}/tests/SelectHierPath/dut.sv, line:10:1, endln:16:10 +\_module_inst: work@IntegerRegisterWriteStage (work@IntegerRegisterWriteStage), file:${SURELOG_DIR}/tests/SelectHierPath/dut.sv, line:10:1, endln:16:10 |vpiParent: \_design: (work@IntegerRegisterWriteStage) |vpiFullName:work@IntegerRegisterWriteStage @@ -161,13 +161,13 @@ design: (work@IntegerRegisterWriteStage) |vpiNet: \_logic_net: (work@IntegerRegisterWriteStage.pipeReg), line:12:34, endln:12:41 |vpiParent: - \_module: work@IntegerRegisterWriteStage (work@IntegerRegisterWriteStage), file:${SURELOG_DIR}/tests/SelectHierPath/dut.sv, line:10:1, endln:16:10 + \_module_inst: work@IntegerRegisterWriteStage (work@IntegerRegisterWriteStage), file:${SURELOG_DIR}/tests/SelectHierPath/dut.sv, line:10:1, endln:16:10 |vpiName:pipeReg |vpiFullName:work@IntegerRegisterWriteStage.pipeReg |vpiContAssign: \_cont_assign: , line:14:8, endln:14:40 |vpiParent: - \_module: work@IntegerRegisterWriteStage (work@IntegerRegisterWriteStage), file:${SURELOG_DIR}/tests/SelectHierPath/dut.sv, line:10:1, endln:16:10 + \_module_inst: work@IntegerRegisterWriteStage (work@IntegerRegisterWriteStage), file:${SURELOG_DIR}/tests/SelectHierPath/dut.sv, line:10:1, endln:16:10 |vpiRhs: \_hier_path: (pipeReg[1].brResult.nextAddr), line:14:12, endln:14:40 |vpiParent: @@ -248,7 +248,7 @@ design: (work@IntegerRegisterWriteStage) |vpiRefEndLineNo:6 |vpiRefEndColumnNo:17 |uhdmtopModules: -\_module: work@IntegerRegisterWriteStage (work@IntegerRegisterWriteStage), file:${SURELOG_DIR}/tests/SelectHierPath/dut.sv, line:10:1, endln:16:10 +\_module_inst: work@IntegerRegisterWriteStage (work@IntegerRegisterWriteStage), file:${SURELOG_DIR}/tests/SelectHierPath/dut.sv, line:10:1, endln:16:10 |vpiName:work@IntegerRegisterWriteStage |vpiDefName:work@IntegerRegisterWriteStage |vpiTop:1 @@ -259,7 +259,7 @@ design: (work@IntegerRegisterWriteStage) |vpiArrayNet: \_array_net: (work@IntegerRegisterWriteStage.pipeReg), line:12:34, endln:12:41 |vpiParent: - \_module: work@IntegerRegisterWriteStage (work@IntegerRegisterWriteStage), file:${SURELOG_DIR}/tests/SelectHierPath/dut.sv, line:10:1, endln:16:10 + \_module_inst: work@IntegerRegisterWriteStage (work@IntegerRegisterWriteStage), file:${SURELOG_DIR}/tests/SelectHierPath/dut.sv, line:10:1, endln:16:10 |vpiSize:2 |vpiName:pipeReg |vpiFullName:work@IntegerRegisterWriteStage.pipeReg @@ -301,7 +301,7 @@ design: (work@IntegerRegisterWriteStage) |vpiContAssign: \_cont_assign: , line:14:8, endln:14:40 |vpiParent: - \_module: work@IntegerRegisterWriteStage (work@IntegerRegisterWriteStage), file:${SURELOG_DIR}/tests/SelectHierPath/dut.sv, line:10:1, endln:16:10 + \_module_inst: work@IntegerRegisterWriteStage (work@IntegerRegisterWriteStage), file:${SURELOG_DIR}/tests/SelectHierPath/dut.sv, line:10:1, endln:16:10 |vpiRhs: \_hier_path: (pipeReg[1].brResult.nextAddr), line:14:12, endln:14:40 |vpiParent: diff --git a/tests/SelectSelect/SelectSelect.log b/tests/SelectSelect/SelectSelect.log index 24d315de54..1699306668 100644 --- a/tests/SelectSelect/SelectSelect.log +++ b/tests/SelectSelect/SelectSelect.log @@ -405,7 +405,7 @@ io_decl 11 logic_net 2 logic_typespec 2 logic_var 2 -module 3 +module_inst 3 package 2 packed_array_typespec 1 packed_array_var 1 @@ -436,7 +436,7 @@ io_decl 22 logic_net 2 logic_typespec 2 logic_var 2 -module 3 +module_inst 3 package 2 packed_array_typespec 1 packed_array_var 1 @@ -935,17 +935,17 @@ design: (work@adc_ctrl_core) \_int_typespec: |vpiSigned:1 |uhdmallModules: -\_module: work@adc_ctrl_core (work@adc_ctrl_core), file:${SURELOG_DIR}/tests/SelectSelect/dut.sv, line:1:1, endln:8:10 +\_module_inst: work@adc_ctrl_core (work@adc_ctrl_core), file:${SURELOG_DIR}/tests/SelectSelect/dut.sv, line:1:1, endln:8:10 |vpiParent: \_design: (work@adc_ctrl_core) |vpiFullName:work@adc_ctrl_core |vpiTypedef: \_struct_typespec: (filter_ctl_t), line:2:12, endln:2:18 |vpiParent: - \_module: work@adc_ctrl_core (work@adc_ctrl_core), file:${SURELOG_DIR}/tests/SelectSelect/dut.sv, line:1:1, endln:8:10 + \_module_inst: work@adc_ctrl_core (work@adc_ctrl_core), file:${SURELOG_DIR}/tests/SelectSelect/dut.sv, line:1:1, endln:8:10 |vpiName:filter_ctl_t |vpiInstance: - \_module: work@adc_ctrl_core (work@adc_ctrl_core), file:${SURELOG_DIR}/tests/SelectSelect/dut.sv, line:1:1, endln:8:10 + \_module_inst: work@adc_ctrl_core (work@adc_ctrl_core), file:${SURELOG_DIR}/tests/SelectSelect/dut.sv, line:1:1, endln:8:10 |vpiPacked:1 |vpiTypespecMember: \_typespec_member: (min_v), line:3:19, endln:3:24 @@ -985,23 +985,23 @@ design: (work@adc_ctrl_core) |vpiNet: \_logic_net: (work@adc_ctrl_core.a), line:6:28, endln:6:29 |vpiParent: - \_module: work@adc_ctrl_core (work@adc_ctrl_core), file:${SURELOG_DIR}/tests/SelectSelect/dut.sv, line:1:1, endln:8:10 + \_module_inst: work@adc_ctrl_core (work@adc_ctrl_core), file:${SURELOG_DIR}/tests/SelectSelect/dut.sv, line:1:1, endln:8:10 |vpiName:a |vpiFullName:work@adc_ctrl_core.a |vpiNet: \_logic_net: (work@adc_ctrl_core.x), line:7:16, endln:7:17 |vpiParent: - \_module: work@adc_ctrl_core (work@adc_ctrl_core), file:${SURELOG_DIR}/tests/SelectSelect/dut.sv, line:1:1, endln:8:10 + \_module_inst: work@adc_ctrl_core (work@adc_ctrl_core), file:${SURELOG_DIR}/tests/SelectSelect/dut.sv, line:1:1, endln:8:10 |vpiName:x |vpiFullName:work@adc_ctrl_core.x |vpiNetType:36 |uhdmtopModules: -\_module: work@adc_ctrl_core (work@adc_ctrl_core), file:${SURELOG_DIR}/tests/SelectSelect/dut.sv, line:1:1, endln:8:10 +\_module_inst: work@adc_ctrl_core (work@adc_ctrl_core), file:${SURELOG_DIR}/tests/SelectSelect/dut.sv, line:1:1, endln:8:10 |vpiName:work@adc_ctrl_core |vpiVariables: \_packed_array_var: (work@adc_ctrl_core.a), line:6:28, endln:6:29 |vpiParent: - \_module: work@adc_ctrl_core (work@adc_ctrl_core), file:${SURELOG_DIR}/tests/SelectSelect/dut.sv, line:1:1, endln:8:10 + \_module_inst: work@adc_ctrl_core (work@adc_ctrl_core), file:${SURELOG_DIR}/tests/SelectSelect/dut.sv, line:1:1, endln:8:10 |vpiName:a |vpiFullName:work@adc_ctrl_core.a |vpiVisibility:1 @@ -1051,7 +1051,7 @@ design: (work@adc_ctrl_core) |vpiVariables: \_logic_var: (work@adc_ctrl_core.x), line:7:16, endln:7:33 |vpiParent: - \_module: work@adc_ctrl_core (work@adc_ctrl_core), file:${SURELOG_DIR}/tests/SelectSelect/dut.sv, line:1:1, endln:8:10 + \_module_inst: work@adc_ctrl_core (work@adc_ctrl_core), file:${SURELOG_DIR}/tests/SelectSelect/dut.sv, line:1:1, endln:8:10 |vpiTypespec: \_logic_typespec: , line:7:4, endln:7:15 |vpiRange: diff --git a/tests/Selects/Selects.log b/tests/Selects/Selects.log index 514b90dba1..00a176f758 100644 --- a/tests/Selects/Selects.log +++ b/tests/Selects/Selects.log @@ -169,7 +169,7 @@ hier_path 2 logic_net 4 logic_typespec 3 logic_var 2 -module 3 +module_inst 3 packed_array_typespec 2 packed_array_var 1 range 3 @@ -188,7 +188,7 @@ hier_path 2 logic_net 4 logic_typespec 3 logic_var 2 -module 3 +module_inst 3 packed_array_typespec 2 packed_array_var 1 range 3 @@ -210,17 +210,17 @@ design: (work@t) |vpiElaborated:1 |vpiName:work@t |uhdmallModules: -\_module: work@t (work@t), file:${SURELOG_DIR}/tests/Selects/dut.sv, line:1:1, endln:16:10 +\_module_inst: work@t (work@t), file:${SURELOG_DIR}/tests/Selects/dut.sv, line:1:1, endln:16:10 |vpiParent: \_design: (work@t) |vpiFullName:work@t |vpiTypedef: \_struct_typespec: (rstmgr_reg2hw_sw_rst_ctrl_n_mreg_t), line:3:11, endln:3:17 |vpiParent: - \_module: work@t (work@t), file:${SURELOG_DIR}/tests/Selects/dut.sv, line:1:1, endln:16:10 + \_module_inst: work@t (work@t), file:${SURELOG_DIR}/tests/Selects/dut.sv, line:1:1, endln:16:10 |vpiName:rstmgr_reg2hw_sw_rst_ctrl_n_mreg_t |vpiInstance: - \_module: work@t (work@t), file:${SURELOG_DIR}/tests/Selects/dut.sv, line:1:1, endln:16:10 + \_module_inst: work@t (work@t), file:${SURELOG_DIR}/tests/Selects/dut.sv, line:1:1, endln:16:10 |vpiPacked:1 |vpiTypespecMember: \_typespec_member: (q), line:4:18, endln:4:19 @@ -239,10 +239,10 @@ design: (work@t) |vpiTypedef: \_struct_typespec: (rstmgr_reg2hw_t), line:7:11, endln:7:17 |vpiParent: - \_module: work@t (work@t), file:${SURELOG_DIR}/tests/Selects/dut.sv, line:1:1, endln:16:10 + \_module_inst: work@t (work@t), file:${SURELOG_DIR}/tests/Selects/dut.sv, line:1:1, endln:16:10 |vpiName:rstmgr_reg2hw_t |vpiInstance: - \_module: work@t (work@t), file:${SURELOG_DIR}/tests/Selects/dut.sv, line:1:1, endln:16:10 + \_module_inst: work@t (work@t), file:${SURELOG_DIR}/tests/Selects/dut.sv, line:1:1, endln:16:10 |vpiPacked:1 |vpiTypespecMember: \_typespec_member: (sw_rst_ctrl_n), line:8:46, endln:8:59 @@ -284,36 +284,36 @@ design: (work@t) |vpiNet: \_logic_net: (work@t.reg2hw), line:11:19, endln:11:25 |vpiParent: - \_module: work@t (work@t), file:${SURELOG_DIR}/tests/Selects/dut.sv, line:1:1, endln:16:10 + \_module_inst: work@t (work@t), file:${SURELOG_DIR}/tests/Selects/dut.sv, line:1:1, endln:16:10 |vpiName:reg2hw |vpiFullName:work@t.reg2hw |vpiNet: \_logic_net: (work@t.sw_rst_ctrl_n), line:12:44, endln:12:57 |vpiParent: - \_module: work@t (work@t), file:${SURELOG_DIR}/tests/Selects/dut.sv, line:1:1, endln:16:10 + \_module_inst: work@t (work@t), file:${SURELOG_DIR}/tests/Selects/dut.sv, line:1:1, endln:16:10 |vpiName:sw_rst_ctrl_n |vpiFullName:work@t.sw_rst_ctrl_n |vpiNet: \_logic_net: (work@t.X), line:14:9, endln:14:10 |vpiParent: - \_module: work@t (work@t), file:${SURELOG_DIR}/tests/Selects/dut.sv, line:1:1, endln:16:10 + \_module_inst: work@t (work@t), file:${SURELOG_DIR}/tests/Selects/dut.sv, line:1:1, endln:16:10 |vpiName:X |vpiFullName:work@t.X |vpiNetType:36 |vpiNet: \_logic_net: (work@t.Y), line:15:9, endln:15:10 |vpiParent: - \_module: work@t (work@t), file:${SURELOG_DIR}/tests/Selects/dut.sv, line:1:1, endln:16:10 + \_module_inst: work@t (work@t), file:${SURELOG_DIR}/tests/Selects/dut.sv, line:1:1, endln:16:10 |vpiName:Y |vpiFullName:work@t.Y |vpiNetType:36 |uhdmtopModules: -\_module: work@t (work@t), file:${SURELOG_DIR}/tests/Selects/dut.sv, line:1:1, endln:16:10 +\_module_inst: work@t (work@t), file:${SURELOG_DIR}/tests/Selects/dut.sv, line:1:1, endln:16:10 |vpiName:work@t |vpiVariables: \_struct_var: (work@t.reg2hw), line:11:19, endln:11:25 |vpiParent: - \_module: work@t (work@t), file:${SURELOG_DIR}/tests/Selects/dut.sv, line:1:1, endln:16:10 + \_module_inst: work@t (work@t), file:${SURELOG_DIR}/tests/Selects/dut.sv, line:1:1, endln:16:10 |vpiTypespec: \_struct_typespec: (rstmgr_reg2hw_t), line:7:11, endln:7:17 |vpiName:reg2hw @@ -322,7 +322,7 @@ design: (work@t) |vpiVariables: \_packed_array_var: (work@t.sw_rst_ctrl_n), line:12:44, endln:12:57 |vpiParent: - \_module: work@t (work@t), file:${SURELOG_DIR}/tests/Selects/dut.sv, line:1:1, endln:16:10 + \_module_inst: work@t (work@t), file:${SURELOG_DIR}/tests/Selects/dut.sv, line:1:1, endln:16:10 |vpiName:sw_rst_ctrl_n |vpiFullName:work@t.sw_rst_ctrl_n |vpiVisibility:1 @@ -354,7 +354,7 @@ design: (work@t) |vpiVariables: \_logic_var: (work@t.X), line:14:9, endln:14:38 |vpiParent: - \_module: work@t (work@t), file:${SURELOG_DIR}/tests/Selects/dut.sv, line:1:1, endln:16:10 + \_module_inst: work@t (work@t), file:${SURELOG_DIR}/tests/Selects/dut.sv, line:1:1, endln:16:10 |vpiTypespec: \_logic_typespec: , line:14:3, endln:14:8 |vpiName:X @@ -390,7 +390,7 @@ design: (work@t) |vpiVariables: \_logic_var: (work@t.Y), line:15:9, endln:15:31 |vpiParent: - \_module: work@t (work@t), file:${SURELOG_DIR}/tests/Selects/dut.sv, line:1:1, endln:16:10 + \_module_inst: work@t (work@t), file:${SURELOG_DIR}/tests/Selects/dut.sv, line:1:1, endln:16:10 |vpiTypespec: \_logic_typespec: , line:15:3, endln:15:8 |vpiName:Y diff --git a/tests/SequenceInst/SequenceInst.log b/tests/SequenceInst/SequenceInst.log index 7636e45216..4132b06674 100644 --- a/tests/SequenceInst/SequenceInst.log +++ b/tests/SequenceInst/SequenceInst.log @@ -548,7 +548,7 @@ if_else 1 logic_net 8 logic_typespec 8 logic_var 8 -module 2 +module_inst 2 operation 15 port 14 property_inst 2 @@ -572,7 +572,7 @@ if_else 2 logic_net 8 logic_typespec 8 logic_var 8 -module 2 +module_inst 2 operation 30 port 21 property_inst 4 @@ -593,7 +593,7 @@ design: (work@m) |vpiElaborated:1 |vpiName:work@m |uhdmallModules: -\_module: work@m (work@m), file:${SURELOG_DIR}/tests/SequenceInst/dut.sv, line:1:1, endln:30:10 +\_module_inst: work@m (work@m), file:${SURELOG_DIR}/tests/SequenceInst/dut.sv, line:1:1, endln:30:10 |vpiParent: \_design: (work@m) |vpiFullName:work@m @@ -601,63 +601,63 @@ design: (work@m) |vpiNet: \_logic_net: (work@m.b), line:1:19, endln:1:20 |vpiParent: - \_module: work@m (work@m), file:${SURELOG_DIR}/tests/SequenceInst/dut.sv, line:1:1, endln:30:10 + \_module_inst: work@m (work@m), file:${SURELOG_DIR}/tests/SequenceInst/dut.sv, line:1:1, endln:30:10 |vpiName:b |vpiFullName:work@m.b |vpiNetType:36 |vpiNet: \_logic_net: (work@m.c), line:1:22, endln:1:23 |vpiParent: - \_module: work@m (work@m), file:${SURELOG_DIR}/tests/SequenceInst/dut.sv, line:1:1, endln:30:10 + \_module_inst: work@m (work@m), file:${SURELOG_DIR}/tests/SequenceInst/dut.sv, line:1:1, endln:30:10 |vpiName:c |vpiFullName:work@m.c |vpiNetType:36 |vpiNet: \_logic_net: (work@m.d), line:1:25, endln:1:26 |vpiParent: - \_module: work@m (work@m), file:${SURELOG_DIR}/tests/SequenceInst/dut.sv, line:1:1, endln:30:10 + \_module_inst: work@m (work@m), file:${SURELOG_DIR}/tests/SequenceInst/dut.sv, line:1:1, endln:30:10 |vpiName:d |vpiFullName:work@m.d |vpiNetType:36 |vpiNet: \_logic_net: (work@m.rst1), line:1:28, endln:1:32 |vpiParent: - \_module: work@m (work@m), file:${SURELOG_DIR}/tests/SequenceInst/dut.sv, line:1:1, endln:30:10 + \_module_inst: work@m (work@m), file:${SURELOG_DIR}/tests/SequenceInst/dut.sv, line:1:1, endln:30:10 |vpiName:rst1 |vpiFullName:work@m.rst1 |vpiNetType:36 |vpiNet: \_logic_net: (work@m.clk1), line:1:34, endln:1:38 |vpiParent: - \_module: work@m (work@m), file:${SURELOG_DIR}/tests/SequenceInst/dut.sv, line:1:1, endln:30:10 + \_module_inst: work@m (work@m), file:${SURELOG_DIR}/tests/SequenceInst/dut.sv, line:1:1, endln:30:10 |vpiName:clk1 |vpiFullName:work@m.clk1 |vpiNetType:36 |vpiNet: \_logic_net: (work@m.clk2), line:1:40, endln:1:44 |vpiParent: - \_module: work@m (work@m), file:${SURELOG_DIR}/tests/SequenceInst/dut.sv, line:1:1, endln:30:10 + \_module_inst: work@m (work@m), file:${SURELOG_DIR}/tests/SequenceInst/dut.sv, line:1:1, endln:30:10 |vpiName:clk2 |vpiFullName:work@m.clk2 |vpiNetType:36 |vpiNet: \_logic_net: (work@m.rst), line:3:9, endln:3:12 |vpiParent: - \_module: work@m (work@m), file:${SURELOG_DIR}/tests/SequenceInst/dut.sv, line:1:1, endln:30:10 + \_module_inst: work@m (work@m), file:${SURELOG_DIR}/tests/SequenceInst/dut.sv, line:1:1, endln:30:10 |vpiName:rst |vpiFullName:work@m.rst |vpiNetType:36 |vpiNet: \_logic_net: (work@m.a), line:1:16, endln:1:17 |vpiParent: - \_module: work@m (work@m), file:${SURELOG_DIR}/tests/SequenceInst/dut.sv, line:1:1, endln:30:10 + \_module_inst: work@m (work@m), file:${SURELOG_DIR}/tests/SequenceInst/dut.sv, line:1:1, endln:30:10 |vpiName:a |vpiFullName:work@m.a |vpiNetType:36 |vpiAssertion: \_assert_stmt: (work@m.a1), line:16:3, endln:16:45 |vpiParent: - \_module: work@m (work@m), file:${SURELOG_DIR}/tests/SequenceInst/dut.sv, line:1:1, endln:30:10 + \_module_inst: work@m (work@m), file:${SURELOG_DIR}/tests/SequenceInst/dut.sv, line:1:1, endln:30:10 |vpiName:a1 |vpiFullName:work@m.a1 |vpiProperty: @@ -689,7 +689,7 @@ design: (work@m) |vpiAssertion: \_assert_stmt: (work@m.a2), line:18:3, endln:18:66 |vpiParent: - \_module: work@m (work@m), file:${SURELOG_DIR}/tests/SequenceInst/dut.sv, line:1:1, endln:30:10 + \_module_inst: work@m (work@m), file:${SURELOG_DIR}/tests/SequenceInst/dut.sv, line:1:1, endln:30:10 |vpiName:a2 |vpiFullName:work@m.a2 |vpiProperty: @@ -755,7 +755,7 @@ design: (work@m) |vpiAssertion: \_assert_stmt: (work@m.a4), line:28:3, endln:28:79 |vpiParent: - \_module: work@m (work@m), file:${SURELOG_DIR}/tests/SequenceInst/dut.sv, line:1:1, endln:30:10 + \_module_inst: work@m (work@m), file:${SURELOG_DIR}/tests/SequenceInst/dut.sv, line:1:1, endln:30:10 |vpiName:a4 |vpiFullName:work@m.a4 |vpiProperty: @@ -859,7 +859,7 @@ design: (work@m) |vpiPort: \_port: (a), line:1:16, endln:1:17 |vpiParent: - \_module: work@m (work@m), file:${SURELOG_DIR}/tests/SequenceInst/dut.sv, line:1:1, endln:30:10 + \_module_inst: work@m (work@m), file:${SURELOG_DIR}/tests/SequenceInst/dut.sv, line:1:1, endln:30:10 |vpiName:a |vpiDirection:3 |vpiLowConn: @@ -869,7 +869,7 @@ design: (work@m) |vpiPort: \_port: (b), line:1:19, endln:1:20 |vpiParent: - \_module: work@m (work@m), file:${SURELOG_DIR}/tests/SequenceInst/dut.sv, line:1:1, endln:30:10 + \_module_inst: work@m (work@m), file:${SURELOG_DIR}/tests/SequenceInst/dut.sv, line:1:1, endln:30:10 |vpiName:b |vpiDirection:3 |vpiLowConn: @@ -879,7 +879,7 @@ design: (work@m) |vpiPort: \_port: (c), line:1:22, endln:1:23 |vpiParent: - \_module: work@m (work@m), file:${SURELOG_DIR}/tests/SequenceInst/dut.sv, line:1:1, endln:30:10 + \_module_inst: work@m (work@m), file:${SURELOG_DIR}/tests/SequenceInst/dut.sv, line:1:1, endln:30:10 |vpiName:c |vpiDirection:3 |vpiLowConn: @@ -889,7 +889,7 @@ design: (work@m) |vpiPort: \_port: (d), line:1:25, endln:1:26 |vpiParent: - \_module: work@m (work@m), file:${SURELOG_DIR}/tests/SequenceInst/dut.sv, line:1:1, endln:30:10 + \_module_inst: work@m (work@m), file:${SURELOG_DIR}/tests/SequenceInst/dut.sv, line:1:1, endln:30:10 |vpiName:d |vpiDirection:3 |vpiLowConn: @@ -899,7 +899,7 @@ design: (work@m) |vpiPort: \_port: (rst1), line:1:28, endln:1:32 |vpiParent: - \_module: work@m (work@m), file:${SURELOG_DIR}/tests/SequenceInst/dut.sv, line:1:1, endln:30:10 + \_module_inst: work@m (work@m), file:${SURELOG_DIR}/tests/SequenceInst/dut.sv, line:1:1, endln:30:10 |vpiName:rst1 |vpiDirection:3 |vpiLowConn: @@ -909,7 +909,7 @@ design: (work@m) |vpiPort: \_port: (clk1), line:1:34, endln:1:38 |vpiParent: - \_module: work@m (work@m), file:${SURELOG_DIR}/tests/SequenceInst/dut.sv, line:1:1, endln:30:10 + \_module_inst: work@m (work@m), file:${SURELOG_DIR}/tests/SequenceInst/dut.sv, line:1:1, endln:30:10 |vpiName:clk1 |vpiDirection:3 |vpiLowConn: @@ -919,7 +919,7 @@ design: (work@m) |vpiPort: \_port: (clk2), line:1:40, endln:1:44 |vpiParent: - \_module: work@m (work@m), file:${SURELOG_DIR}/tests/SequenceInst/dut.sv, line:1:1, endln:30:10 + \_module_inst: work@m (work@m), file:${SURELOG_DIR}/tests/SequenceInst/dut.sv, line:1:1, endln:30:10 |vpiName:clk2 |vpiDirection:3 |vpiLowConn: @@ -929,7 +929,7 @@ design: (work@m) |vpiProcess: \_always: , line:20:3, endln:26:6 |vpiParent: - \_module: work@m (work@m), file:${SURELOG_DIR}/tests/SequenceInst/dut.sv, line:1:1, endln:30:10 + \_module_inst: work@m (work@m), file:${SURELOG_DIR}/tests/SequenceInst/dut.sv, line:1:1, endln:30:10 |vpiStmt: \_event_control: , line:20:10, endln:20:40 |vpiParent: @@ -1020,12 +1020,12 @@ design: (work@m) |vpiName:p_triggers |vpiAlwaysType:1 |uhdmtopModules: -\_module: work@m (work@m), file:${SURELOG_DIR}/tests/SequenceInst/dut.sv, line:1:1, endln:30:10 +\_module_inst: work@m (work@m), file:${SURELOG_DIR}/tests/SequenceInst/dut.sv, line:1:1, endln:30:10 |vpiName:work@m |vpiVariables: \_logic_var: (work@m.b), line:1:19, endln:1:20 |vpiParent: - \_module: work@m (work@m), file:${SURELOG_DIR}/tests/SequenceInst/dut.sv, line:1:1, endln:30:10 + \_module_inst: work@m (work@m), file:${SURELOG_DIR}/tests/SequenceInst/dut.sv, line:1:1, endln:30:10 |vpiTypespec: \_logic_typespec: , line:1:19, endln:1:20 |vpiName:b @@ -1034,7 +1034,7 @@ design: (work@m) |vpiVariables: \_logic_var: (work@m.c), line:1:22, endln:1:23 |vpiParent: - \_module: work@m (work@m), file:${SURELOG_DIR}/tests/SequenceInst/dut.sv, line:1:1, endln:30:10 + \_module_inst: work@m (work@m), file:${SURELOG_DIR}/tests/SequenceInst/dut.sv, line:1:1, endln:30:10 |vpiTypespec: \_logic_typespec: , line:1:22, endln:1:23 |vpiName:c @@ -1043,7 +1043,7 @@ design: (work@m) |vpiVariables: \_logic_var: (work@m.d), line:1:25, endln:1:26 |vpiParent: - \_module: work@m (work@m), file:${SURELOG_DIR}/tests/SequenceInst/dut.sv, line:1:1, endln:30:10 + \_module_inst: work@m (work@m), file:${SURELOG_DIR}/tests/SequenceInst/dut.sv, line:1:1, endln:30:10 |vpiTypespec: \_logic_typespec: , line:1:25, endln:1:26 |vpiName:d @@ -1052,7 +1052,7 @@ design: (work@m) |vpiVariables: \_logic_var: (work@m.rst1), line:1:28, endln:1:32 |vpiParent: - \_module: work@m (work@m), file:${SURELOG_DIR}/tests/SequenceInst/dut.sv, line:1:1, endln:30:10 + \_module_inst: work@m (work@m), file:${SURELOG_DIR}/tests/SequenceInst/dut.sv, line:1:1, endln:30:10 |vpiTypespec: \_logic_typespec: , line:1:28, endln:1:32 |vpiName:rst1 @@ -1061,7 +1061,7 @@ design: (work@m) |vpiVariables: \_logic_var: (work@m.clk1), line:1:34, endln:1:38 |vpiParent: - \_module: work@m (work@m), file:${SURELOG_DIR}/tests/SequenceInst/dut.sv, line:1:1, endln:30:10 + \_module_inst: work@m (work@m), file:${SURELOG_DIR}/tests/SequenceInst/dut.sv, line:1:1, endln:30:10 |vpiTypespec: \_logic_typespec: , line:1:34, endln:1:38 |vpiName:clk1 @@ -1070,7 +1070,7 @@ design: (work@m) |vpiVariables: \_logic_var: (work@m.clk2), line:1:40, endln:1:44 |vpiParent: - \_module: work@m (work@m), file:${SURELOG_DIR}/tests/SequenceInst/dut.sv, line:1:1, endln:30:10 + \_module_inst: work@m (work@m), file:${SURELOG_DIR}/tests/SequenceInst/dut.sv, line:1:1, endln:30:10 |vpiTypespec: \_logic_typespec: , line:1:40, endln:1:44 |vpiName:clk2 @@ -1079,7 +1079,7 @@ design: (work@m) |vpiVariables: \_logic_var: (work@m.rst), line:3:9, endln:3:12 |vpiParent: - \_module: work@m (work@m), file:${SURELOG_DIR}/tests/SequenceInst/dut.sv, line:1:1, endln:30:10 + \_module_inst: work@m (work@m), file:${SURELOG_DIR}/tests/SequenceInst/dut.sv, line:1:1, endln:30:10 |vpiTypespec: \_logic_typespec: , line:3:3, endln:3:8 |vpiName:rst @@ -1088,7 +1088,7 @@ design: (work@m) |vpiVariables: \_logic_var: (work@m.a), line:1:16, endln:1:17 |vpiParent: - \_module: work@m (work@m), file:${SURELOG_DIR}/tests/SequenceInst/dut.sv, line:1:1, endln:30:10 + \_module_inst: work@m (work@m), file:${SURELOG_DIR}/tests/SequenceInst/dut.sv, line:1:1, endln:30:10 |vpiTypespec: \_logic_typespec: , line:1:16, endln:1:17 |vpiName:a @@ -1099,7 +1099,7 @@ design: (work@m) |vpiAssertion: \_assert_stmt: (work@m.a1), line:16:3, endln:16:45 |vpiParent: - \_module: work@m (work@m), file:${SURELOG_DIR}/tests/SequenceInst/dut.sv, line:1:1, endln:30:10 + \_module_inst: work@m (work@m), file:${SURELOG_DIR}/tests/SequenceInst/dut.sv, line:1:1, endln:30:10 |vpiName:a1 |vpiFullName:work@m.a1 |vpiProperty: @@ -1138,7 +1138,7 @@ design: (work@m) |vpiAssertion: \_assert_stmt: (work@m.a2), line:18:3, endln:18:66 |vpiParent: - \_module: work@m (work@m), file:${SURELOG_DIR}/tests/SequenceInst/dut.sv, line:1:1, endln:30:10 + \_module_inst: work@m (work@m), file:${SURELOG_DIR}/tests/SequenceInst/dut.sv, line:1:1, endln:30:10 |vpiName:a2 |vpiFullName:work@m.a2 |vpiProperty: @@ -1212,7 +1212,7 @@ design: (work@m) |vpiAssertion: \_assert_stmt: (work@m.a4), line:28:3, endln:28:79 |vpiParent: - \_module: work@m (work@m), file:${SURELOG_DIR}/tests/SequenceInst/dut.sv, line:1:1, endln:30:10 + \_module_inst: work@m (work@m), file:${SURELOG_DIR}/tests/SequenceInst/dut.sv, line:1:1, endln:30:10 |vpiName:a4 |vpiFullName:work@m.a4 |vpiProperty: @@ -1308,7 +1308,7 @@ design: (work@m) |vpiDefaultClocking: \_clocking_block: (work@m.unnamed_clocking_block), line:4:3, endln:4:48 |vpiParent: - \_module: work@m (work@m), file:${SURELOG_DIR}/tests/SequenceInst/dut.sv, line:1:1, endln:30:10 + \_module_inst: work@m (work@m), file:${SURELOG_DIR}/tests/SequenceInst/dut.sv, line:1:1, endln:30:10 |vpiName:unnamed_clocking_block |vpiFullName:work@m.unnamed_clocking_block |vpiClockingEvent: @@ -1329,11 +1329,11 @@ design: (work@m) |vpiActual: \_logic_var: (work@m.clk1), line:1:34, endln:1:38 |vpiInstance: - \_module: work@m (work@m), file:${SURELOG_DIR}/tests/SequenceInst/dut.sv, line:1:1, endln:30:10 + \_module_inst: work@m (work@m), file:${SURELOG_DIR}/tests/SequenceInst/dut.sv, line:1:1, endln:30:10 |vpiPort: \_port: (a), line:1:16, endln:1:17 |vpiParent: - \_module: work@m (work@m), file:${SURELOG_DIR}/tests/SequenceInst/dut.sv, line:1:1, endln:30:10 + \_module_inst: work@m (work@m), file:${SURELOG_DIR}/tests/SequenceInst/dut.sv, line:1:1, endln:30:10 |vpiName:a |vpiDirection:3 |vpiLowConn: @@ -1345,11 +1345,11 @@ design: (work@m) |vpiActual: \_logic_var: (work@m.a), line:1:16, endln:1:17 |vpiInstance: - \_module: work@m (work@m), file:${SURELOG_DIR}/tests/SequenceInst/dut.sv, line:1:1, endln:30:10 + \_module_inst: work@m (work@m), file:${SURELOG_DIR}/tests/SequenceInst/dut.sv, line:1:1, endln:30:10 |vpiPort: \_port: (b), line:1:19, endln:1:20 |vpiParent: - \_module: work@m (work@m), file:${SURELOG_DIR}/tests/SequenceInst/dut.sv, line:1:1, endln:30:10 + \_module_inst: work@m (work@m), file:${SURELOG_DIR}/tests/SequenceInst/dut.sv, line:1:1, endln:30:10 |vpiName:b |vpiDirection:3 |vpiLowConn: @@ -1361,11 +1361,11 @@ design: (work@m) |vpiActual: \_logic_var: (work@m.b), line:1:19, endln:1:20 |vpiInstance: - \_module: work@m (work@m), file:${SURELOG_DIR}/tests/SequenceInst/dut.sv, line:1:1, endln:30:10 + \_module_inst: work@m (work@m), file:${SURELOG_DIR}/tests/SequenceInst/dut.sv, line:1:1, endln:30:10 |vpiPort: \_port: (c), line:1:22, endln:1:23 |vpiParent: - \_module: work@m (work@m), file:${SURELOG_DIR}/tests/SequenceInst/dut.sv, line:1:1, endln:30:10 + \_module_inst: work@m (work@m), file:${SURELOG_DIR}/tests/SequenceInst/dut.sv, line:1:1, endln:30:10 |vpiName:c |vpiDirection:3 |vpiLowConn: @@ -1377,11 +1377,11 @@ design: (work@m) |vpiActual: \_logic_var: (work@m.c), line:1:22, endln:1:23 |vpiInstance: - \_module: work@m (work@m), file:${SURELOG_DIR}/tests/SequenceInst/dut.sv, line:1:1, endln:30:10 + \_module_inst: work@m (work@m), file:${SURELOG_DIR}/tests/SequenceInst/dut.sv, line:1:1, endln:30:10 |vpiPort: \_port: (d), line:1:25, endln:1:26 |vpiParent: - \_module: work@m (work@m), file:${SURELOG_DIR}/tests/SequenceInst/dut.sv, line:1:1, endln:30:10 + \_module_inst: work@m (work@m), file:${SURELOG_DIR}/tests/SequenceInst/dut.sv, line:1:1, endln:30:10 |vpiName:d |vpiDirection:3 |vpiLowConn: @@ -1393,11 +1393,11 @@ design: (work@m) |vpiActual: \_logic_var: (work@m.d), line:1:25, endln:1:26 |vpiInstance: - \_module: work@m (work@m), file:${SURELOG_DIR}/tests/SequenceInst/dut.sv, line:1:1, endln:30:10 + \_module_inst: work@m (work@m), file:${SURELOG_DIR}/tests/SequenceInst/dut.sv, line:1:1, endln:30:10 |vpiPort: \_port: (rst1), line:1:28, endln:1:32 |vpiParent: - \_module: work@m (work@m), file:${SURELOG_DIR}/tests/SequenceInst/dut.sv, line:1:1, endln:30:10 + \_module_inst: work@m (work@m), file:${SURELOG_DIR}/tests/SequenceInst/dut.sv, line:1:1, endln:30:10 |vpiName:rst1 |vpiDirection:3 |vpiLowConn: @@ -1409,11 +1409,11 @@ design: (work@m) |vpiActual: \_logic_var: (work@m.rst1), line:1:28, endln:1:32 |vpiInstance: - \_module: work@m (work@m), file:${SURELOG_DIR}/tests/SequenceInst/dut.sv, line:1:1, endln:30:10 + \_module_inst: work@m (work@m), file:${SURELOG_DIR}/tests/SequenceInst/dut.sv, line:1:1, endln:30:10 |vpiPort: \_port: (clk1), line:1:34, endln:1:38 |vpiParent: - \_module: work@m (work@m), file:${SURELOG_DIR}/tests/SequenceInst/dut.sv, line:1:1, endln:30:10 + \_module_inst: work@m (work@m), file:${SURELOG_DIR}/tests/SequenceInst/dut.sv, line:1:1, endln:30:10 |vpiName:clk1 |vpiDirection:3 |vpiLowConn: @@ -1425,11 +1425,11 @@ design: (work@m) |vpiActual: \_logic_var: (work@m.clk1), line:1:34, endln:1:38 |vpiInstance: - \_module: work@m (work@m), file:${SURELOG_DIR}/tests/SequenceInst/dut.sv, line:1:1, endln:30:10 + \_module_inst: work@m (work@m), file:${SURELOG_DIR}/tests/SequenceInst/dut.sv, line:1:1, endln:30:10 |vpiPort: \_port: (clk2), line:1:40, endln:1:44 |vpiParent: - \_module: work@m (work@m), file:${SURELOG_DIR}/tests/SequenceInst/dut.sv, line:1:1, endln:30:10 + \_module_inst: work@m (work@m), file:${SURELOG_DIR}/tests/SequenceInst/dut.sv, line:1:1, endln:30:10 |vpiName:clk2 |vpiDirection:3 |vpiLowConn: @@ -1441,11 +1441,11 @@ design: (work@m) |vpiActual: \_logic_var: (work@m.clk2), line:1:40, endln:1:44 |vpiInstance: - \_module: work@m (work@m), file:${SURELOG_DIR}/tests/SequenceInst/dut.sv, line:1:1, endln:30:10 + \_module_inst: work@m (work@m), file:${SURELOG_DIR}/tests/SequenceInst/dut.sv, line:1:1, endln:30:10 |vpiProcess: \_always: , line:20:3, endln:26:6 |vpiParent: - \_module: work@m (work@m), file:${SURELOG_DIR}/tests/SequenceInst/dut.sv, line:1:1, endln:30:10 + \_module_inst: work@m (work@m), file:${SURELOG_DIR}/tests/SequenceInst/dut.sv, line:1:1, endln:30:10 |vpiStmt: \_event_control: , line:20:10, endln:20:40 |vpiParent: diff --git a/tests/SignedBin/SignedBin.log b/tests/SignedBin/SignedBin.log index 5e743ceaa1..98496f3849 100644 --- a/tests/SignedBin/SignedBin.log +++ b/tests/SignedBin/SignedBin.log @@ -82,7 +82,7 @@ design 1 int_typespec 2 logic_net 2 logic_typespec 3 -module 5 +module_inst 5 operation 2 port 2 ref_obj 2 @@ -95,7 +95,7 @@ design 1 int_typespec 2 logic_net 2 logic_typespec 3 -module 5 +module_inst 5 operation 2 port 3 ref_obj 3 @@ -113,13 +113,13 @@ design: (work@dut) |vpiElaborated:1 |vpiName:work@dut |uhdmallModules: -\_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/SignedBin/dut.sv, line:7:1, endln:10:10 +\_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/SignedBin/dut.sv, line:7:1, endln:10:10 |vpiParent: \_design: (work@dut) |vpiFullName:work@dut |vpiDefName:work@dut |uhdmallModules: -\_module: work@prim_subreg (work@prim_subreg), file:${SURELOG_DIR}/tests/SignedBin/dut.sv, line:1:1, endln:5:10 +\_module_inst: work@prim_subreg (work@prim_subreg), file:${SURELOG_DIR}/tests/SignedBin/dut.sv, line:1:1, endln:5:10 |vpiParent: \_design: (work@dut) |vpiFullName:work@prim_subreg @@ -127,14 +127,14 @@ design: (work@dut) |vpiNet: \_logic_net: (work@prim_subreg.test), line:2:13, endln:2:17 |vpiParent: - \_module: work@prim_subreg (work@prim_subreg), file:${SURELOG_DIR}/tests/SignedBin/dut.sv, line:1:1, endln:5:10 + \_module_inst: work@prim_subreg (work@prim_subreg), file:${SURELOG_DIR}/tests/SignedBin/dut.sv, line:1:1, endln:5:10 |vpiName:test |vpiFullName:work@prim_subreg.test |vpiNetType:36 |vpiPort: \_port: (test), line:2:13, endln:2:17 |vpiParent: - \_module: work@prim_subreg (work@prim_subreg), file:${SURELOG_DIR}/tests/SignedBin/dut.sv, line:1:1, endln:5:10 + \_module_inst: work@prim_subreg (work@prim_subreg), file:${SURELOG_DIR}/tests/SignedBin/dut.sv, line:1:1, endln:5:10 |vpiName:test |vpiDirection:1 |vpiLowConn: @@ -144,15 +144,15 @@ design: (work@dut) |vpiTypedef: \_logic_typespec: , line:2:7, endln:2:12 |uhdmtopModules: -\_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/SignedBin/dut.sv, line:7:1, endln:10:10 +\_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/SignedBin/dut.sv, line:7:1, endln:10:10 |vpiName:work@dut |vpiDefName:work@dut |vpiTop:1 |vpiTopModule:1 - |vpiModule: - \_module: work@prim_subreg (work@dut.s), file:${SURELOG_DIR}/tests/SignedBin/dut.sv, line:9:1, endln:9:36 + |vpiModuleInst: + \_module_inst: work@prim_subreg (work@dut.s), file:${SURELOG_DIR}/tests/SignedBin/dut.sv, line:9:1, endln:9:36 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/SignedBin/dut.sv, line:7:1, endln:10:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/SignedBin/dut.sv, line:7:1, endln:10:10 |vpiName:s |vpiFullName:work@dut.s |vpiDefName:work@prim_subreg @@ -161,18 +161,18 @@ design: (work@dut) |vpiNet: \_logic_net: (work@dut.s.test), line:2:13, endln:2:17 |vpiParent: - \_module: work@prim_subreg (work@dut.s), file:${SURELOG_DIR}/tests/SignedBin/dut.sv, line:9:1, endln:9:36 + \_module_inst: work@prim_subreg (work@dut.s), file:${SURELOG_DIR}/tests/SignedBin/dut.sv, line:9:1, endln:9:36 |vpiTypespec: \_logic_typespec: , line:2:7, endln:2:12 |vpiName:test |vpiFullName:work@dut.s.test |vpiNetType:36 |vpiInstance: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/SignedBin/dut.sv, line:7:1, endln:10:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/SignedBin/dut.sv, line:7:1, endln:10:10 |vpiPort: \_port: (test), line:2:13, endln:2:17 |vpiParent: - \_module: work@prim_subreg (work@dut.s), file:${SURELOG_DIR}/tests/SignedBin/dut.sv, line:9:1, endln:9:36 + \_module_inst: work@prim_subreg (work@dut.s), file:${SURELOG_DIR}/tests/SignedBin/dut.sv, line:9:1, endln:9:36 |vpiName:test |vpiDirection:1 |vpiHighConn: @@ -195,7 +195,7 @@ design: (work@dut) |vpiTypedef: \_logic_typespec: , line:2:7, endln:2:12 |vpiInstance: - \_module: work@prim_subreg (work@dut.s), file:${SURELOG_DIR}/tests/SignedBin/dut.sv, line:9:1, endln:9:36 + \_module_inst: work@prim_subreg (work@dut.s), file:${SURELOG_DIR}/tests/SignedBin/dut.sv, line:9:1, endln:9:36 =================== [ FATAL] : 0 [ SYNTAX] : 0 diff --git a/tests/SignedBinConst/SignedBinConst.log b/tests/SignedBinConst/SignedBinConst.log index 98307c5ab1..2bdbc98fef 100644 --- a/tests/SignedBinConst/SignedBinConst.log +++ b/tests/SignedBinConst/SignedBinConst.log @@ -200,7 +200,7 @@ int_typespec 19 int_var 1 logic_net 7 logic_typespec 4 -module 9 +module_inst 9 param_assign 6 parameter 6 range 10 @@ -215,7 +215,7 @@ int_typespec 19 int_var 1 logic_net 7 logic_typespec 4 -module 9 +module_inst 9 param_assign 6 parameter 6 range 10 @@ -233,14 +233,14 @@ design: (work@top1) |vpiElaborated:1 |vpiName:work@top1 |uhdmallModules: -\_module: work@top1 (work@top1), file:${SURELOG_DIR}/tests/SignedBinConst/dut.sv, line:1:1, endln:5:10 +\_module_inst: work@top1 (work@top1), file:${SURELOG_DIR}/tests/SignedBinConst/dut.sv, line:1:1, endln:5:10 |vpiParent: \_design: (work@top1) |vpiFullName:work@top1 |vpiParameter: \_parameter: (work@top1.p1), line:2:19, endln:2:21 |vpiParent: - \_module: work@top1 (work@top1), file:${SURELOG_DIR}/tests/SignedBinConst/dut.sv, line:1:1, endln:5:10 + \_module_inst: work@top1 (work@top1), file:${SURELOG_DIR}/tests/SignedBinConst/dut.sv, line:1:1, endln:5:10 |BIN:1 |vpiTypespec: \_int_typespec: , line:2:13, endln:2:18 @@ -269,7 +269,7 @@ design: (work@top1) |vpiParameter: \_parameter: (work@top1.p2), line:3:19, endln:3:21 |vpiParent: - \_module: work@top1 (work@top1), file:${SURELOG_DIR}/tests/SignedBinConst/dut.sv, line:1:1, endln:5:10 + \_module_inst: work@top1 (work@top1), file:${SURELOG_DIR}/tests/SignedBinConst/dut.sv, line:1:1, endln:5:10 |BIN:10 |vpiTypespec: \_int_typespec: , line:3:13, endln:3:18 @@ -298,7 +298,7 @@ design: (work@top1) |vpiParameter: \_parameter: (work@top1.p3), line:4:17, endln:4:19 |vpiParent: - \_module: work@top1 (work@top1), file:${SURELOG_DIR}/tests/SignedBinConst/dut.sv, line:1:1, endln:5:10 + \_module_inst: work@top1 (work@top1), file:${SURELOG_DIR}/tests/SignedBinConst/dut.sv, line:1:1, endln:5:10 |BIN:10 |vpiTypespec: \_int_typespec: , line:4:13, endln:4:16 @@ -311,7 +311,7 @@ design: (work@top1) |vpiParamAssign: \_param_assign: , line:2:19, endln:2:30 |vpiParent: - \_module: work@top1 (work@top1), file:${SURELOG_DIR}/tests/SignedBinConst/dut.sv, line:1:1, endln:5:10 + \_module_inst: work@top1 (work@top1), file:${SURELOG_DIR}/tests/SignedBinConst/dut.sv, line:1:1, endln:5:10 |vpiRhs: \_constant: , line:2:25, endln:2:30 |vpiDecompile:1'sb1 @@ -325,7 +325,7 @@ design: (work@top1) |vpiParamAssign: \_param_assign: , line:3:19, endln:3:31 |vpiParent: - \_module: work@top1 (work@top1), file:${SURELOG_DIR}/tests/SignedBinConst/dut.sv, line:1:1, endln:5:10 + \_module_inst: work@top1 (work@top1), file:${SURELOG_DIR}/tests/SignedBinConst/dut.sv, line:1:1, endln:5:10 |vpiRhs: \_constant: , line:3:25, endln:3:31 |vpiDecompile:2'sb10 @@ -339,7 +339,7 @@ design: (work@top1) |vpiParamAssign: \_param_assign: , line:4:17, endln:4:29 |vpiParent: - \_module: work@top1 (work@top1), file:${SURELOG_DIR}/tests/SignedBinConst/dut.sv, line:1:1, endln:5:10 + \_module_inst: work@top1 (work@top1), file:${SURELOG_DIR}/tests/SignedBinConst/dut.sv, line:1:1, endln:5:10 |vpiRhs: \_constant: , line:4:23, endln:4:29 |vpiDecompile:2'sb10 @@ -352,7 +352,7 @@ design: (work@top1) \_parameter: (work@top1.p3), line:4:17, endln:4:19 |vpiDefName:work@top1 |uhdmallModules: -\_module: work@top2 (work@top2), file:${SURELOG_DIR}/tests/SignedBinConst/dut.sv, line:8:1, endln:12:10 +\_module_inst: work@top2 (work@top2), file:${SURELOG_DIR}/tests/SignedBinConst/dut.sv, line:8:1, endln:12:10 |vpiParent: \_design: (work@top1) |vpiFullName:work@top2 @@ -360,30 +360,30 @@ design: (work@top1) |vpiNet: \_logic_net: (work@top2.p1), line:9:13, endln:9:15 |vpiParent: - \_module: work@top2 (work@top2), file:${SURELOG_DIR}/tests/SignedBinConst/dut.sv, line:8:1, endln:12:10 + \_module_inst: work@top2 (work@top2), file:${SURELOG_DIR}/tests/SignedBinConst/dut.sv, line:8:1, endln:12:10 |vpiName:p1 |vpiFullName:work@top2.p1 |vpiNetType:48 |vpiNet: \_logic_net: (work@top2.p2), line:10:13, endln:10:15 |vpiParent: - \_module: work@top2 (work@top2), file:${SURELOG_DIR}/tests/SignedBinConst/dut.sv, line:8:1, endln:12:10 + \_module_inst: work@top2 (work@top2), file:${SURELOG_DIR}/tests/SignedBinConst/dut.sv, line:8:1, endln:12:10 |vpiName:p2 |vpiFullName:work@top2.p2 |vpiNetType:48 |vpiNet: \_logic_net: (work@top2.p3), line:11:7, endln:11:9 |vpiParent: - \_module: work@top2 (work@top2), file:${SURELOG_DIR}/tests/SignedBinConst/dut.sv, line:8:1, endln:12:10 + \_module_inst: work@top2 (work@top2), file:${SURELOG_DIR}/tests/SignedBinConst/dut.sv, line:8:1, endln:12:10 |vpiName:p3 |vpiFullName:work@top2.p3 |uhdmtopModules: -\_module: work@top1 (work@top1), file:${SURELOG_DIR}/tests/SignedBinConst/dut.sv, line:1:1, endln:5:10 +\_module_inst: work@top1 (work@top1), file:${SURELOG_DIR}/tests/SignedBinConst/dut.sv, line:1:1, endln:5:10 |vpiName:work@top1 |vpiParameter: \_parameter: (work@top1.p1), line:2:19, endln:2:21 |vpiParent: - \_module: work@top1 (work@top1), file:${SURELOG_DIR}/tests/SignedBinConst/dut.sv, line:1:1, endln:5:10 + \_module_inst: work@top1 (work@top1), file:${SURELOG_DIR}/tests/SignedBinConst/dut.sv, line:1:1, endln:5:10 |BIN:1 |vpiTypespec: \_int_typespec: , line:2:13, endln:2:18 @@ -414,7 +414,7 @@ design: (work@top1) |vpiParameter: \_parameter: (work@top1.p2), line:3:19, endln:3:21 |vpiParent: - \_module: work@top1 (work@top1), file:${SURELOG_DIR}/tests/SignedBinConst/dut.sv, line:1:1, endln:5:10 + \_module_inst: work@top1 (work@top1), file:${SURELOG_DIR}/tests/SignedBinConst/dut.sv, line:1:1, endln:5:10 |BIN:10 |vpiTypespec: \_int_typespec: , line:3:13, endln:3:18 @@ -445,7 +445,7 @@ design: (work@top1) |vpiParameter: \_parameter: (work@top1.p3), line:4:17, endln:4:19 |vpiParent: - \_module: work@top1 (work@top1), file:${SURELOG_DIR}/tests/SignedBinConst/dut.sv, line:1:1, endln:5:10 + \_module_inst: work@top1 (work@top1), file:${SURELOG_DIR}/tests/SignedBinConst/dut.sv, line:1:1, endln:5:10 |BIN:10 |vpiTypespec: \_int_typespec: , line:4:13, endln:4:16 @@ -458,7 +458,7 @@ design: (work@top1) |vpiParamAssign: \_param_assign: , line:2:19, endln:2:30 |vpiParent: - \_module: work@top1 (work@top1), file:${SURELOG_DIR}/tests/SignedBinConst/dut.sv, line:1:1, endln:5:10 + \_module_inst: work@top1 (work@top1), file:${SURELOG_DIR}/tests/SignedBinConst/dut.sv, line:1:1, endln:5:10 |vpiRhs: \_constant: , line:2:25, endln:2:30 |vpiDecompile:3 @@ -472,7 +472,7 @@ design: (work@top1) |vpiParamAssign: \_param_assign: , line:3:19, endln:3:31 |vpiParent: - \_module: work@top1 (work@top1), file:${SURELOG_DIR}/tests/SignedBinConst/dut.sv, line:1:1, endln:5:10 + \_module_inst: work@top1 (work@top1), file:${SURELOG_DIR}/tests/SignedBinConst/dut.sv, line:1:1, endln:5:10 |vpiRhs: \_constant: , line:3:25, endln:3:31 |vpiDecompile:2'b10 @@ -486,7 +486,7 @@ design: (work@top1) |vpiParamAssign: \_param_assign: , line:4:17, endln:4:29 |vpiParent: - \_module: work@top1 (work@top1), file:${SURELOG_DIR}/tests/SignedBinConst/dut.sv, line:1:1, endln:5:10 + \_module_inst: work@top1 (work@top1), file:${SURELOG_DIR}/tests/SignedBinConst/dut.sv, line:1:1, endln:5:10 |vpiRhs: \_constant: , line:4:23, endln:4:29 |vpiDecompile:-2 @@ -501,12 +501,12 @@ design: (work@top1) |vpiTop:1 |vpiTopModule:1 |uhdmtopModules: -\_module: work@top2 (work@top2), file:${SURELOG_DIR}/tests/SignedBinConst/dut.sv, line:8:1, endln:12:10 +\_module_inst: work@top2 (work@top2), file:${SURELOG_DIR}/tests/SignedBinConst/dut.sv, line:8:1, endln:12:10 |vpiName:work@top2 |vpiVariables: \_int_var: (work@top2.p3), line:11:7, endln:11:19 |vpiParent: - \_module: work@top2 (work@top2), file:${SURELOG_DIR}/tests/SignedBinConst/dut.sv, line:8:1, endln:12:10 + \_module_inst: work@top2 (work@top2), file:${SURELOG_DIR}/tests/SignedBinConst/dut.sv, line:8:1, endln:12:10 |vpiTypespec: \_int_typespec: , line:11:3, endln:11:6 |vpiSigned:1 @@ -527,7 +527,7 @@ design: (work@top1) |vpiNet: \_logic_net: (work@top2.p1), line:9:13, endln:9:24 |vpiParent: - \_module: work@top2 (work@top2), file:${SURELOG_DIR}/tests/SignedBinConst/dut.sv, line:8:1, endln:12:10 + \_module_inst: work@top2 (work@top2), file:${SURELOG_DIR}/tests/SignedBinConst/dut.sv, line:8:1, endln:12:10 |vpiTypespec: \_logic_typespec: , line:9:3, endln:9:12 |vpiRange: @@ -554,7 +554,7 @@ design: (work@top1) |vpiNet: \_logic_net: (work@top2.p2), line:10:13, endln:10:25 |vpiParent: - \_module: work@top2 (work@top2), file:${SURELOG_DIR}/tests/SignedBinConst/dut.sv, line:8:1, endln:12:10 + \_module_inst: work@top2 (work@top2), file:${SURELOG_DIR}/tests/SignedBinConst/dut.sv, line:8:1, endln:12:10 |vpiTypespec: \_logic_typespec: , line:10:3, endln:10:12 |vpiRange: @@ -582,7 +582,7 @@ design: (work@top1) |vpiContAssign: \_cont_assign: , line:9:13, endln:9:15 |vpiParent: - \_module: work@top2 (work@top2), file:${SURELOG_DIR}/tests/SignedBinConst/dut.sv, line:8:1, endln:12:10 + \_module_inst: work@top2 (work@top2), file:${SURELOG_DIR}/tests/SignedBinConst/dut.sv, line:8:1, endln:12:10 |vpiNetDeclAssign:1 |vpiRhs: \_constant: , line:9:19, endln:9:24 @@ -602,7 +602,7 @@ design: (work@top1) |vpiContAssign: \_cont_assign: , line:10:13, endln:10:15 |vpiParent: - \_module: work@top2 (work@top2), file:${SURELOG_DIR}/tests/SignedBinConst/dut.sv, line:8:1, endln:12:10 + \_module_inst: work@top2 (work@top2), file:${SURELOG_DIR}/tests/SignedBinConst/dut.sv, line:8:1, endln:12:10 |vpiNetDeclAssign:1 |vpiRhs: \_constant: , line:10:19, endln:10:25 diff --git a/tests/SignedParam/SignedParam.log b/tests/SignedParam/SignedParam.log index 313cb9a6be..4783ce9d6a 100644 --- a/tests/SignedParam/SignedParam.log +++ b/tests/SignedParam/SignedParam.log @@ -321,7 +321,7 @@ int_typespec 11 int_var 4 io_decl 11 logic_var 1 -module 5 +module_inst 5 package 2 param_assign 2 parameter 2 @@ -343,7 +343,7 @@ int_typespec 11 int_var 4 io_decl 22 logic_var 1 -module 5 +module_inst 5 package 2 param_assign 2 parameter 2 @@ -837,14 +837,14 @@ design: (work@prim_pad_wrapper) \_int_typespec: |vpiSigned:1 |uhdmallModules: -\_module: work@prim_pad_wrapper (work@prim_pad_wrapper), file:${SURELOG_DIR}/tests/SignedParam/dut.sv, line:2:1, endln:10:10 +\_module_inst: work@prim_pad_wrapper (work@prim_pad_wrapper), file:${SURELOG_DIR}/tests/SignedParam/dut.sv, line:2:1, endln:10:10 |vpiParent: \_design: (work@prim_pad_wrapper) |vpiFullName:work@prim_pad_wrapper |vpiParameter: \_parameter: (work@prim_pad_wrapper.AttrDw), line:6:26, endln:6:32 |vpiParent: - \_module: work@prim_pad_wrapper (work@prim_pad_wrapper), file:${SURELOG_DIR}/tests/SignedParam/dut.sv, line:2:1, endln:10:10 + \_module_inst: work@prim_pad_wrapper (work@prim_pad_wrapper), file:${SURELOG_DIR}/tests/SignedParam/dut.sv, line:2:1, endln:10:10 |UINT:6 |vpiTypespec: \_int_typespec: , line:6:15, endln:6:18 @@ -857,7 +857,7 @@ design: (work@prim_pad_wrapper) |vpiParamAssign: \_param_assign: , line:6:26, endln:6:36 |vpiParent: - \_module: work@prim_pad_wrapper (work@prim_pad_wrapper), file:${SURELOG_DIR}/tests/SignedParam/dut.sv, line:2:1, endln:10:10 + \_module_inst: work@prim_pad_wrapper (work@prim_pad_wrapper), file:${SURELOG_DIR}/tests/SignedParam/dut.sv, line:2:1, endln:10:10 |vpiRhs: \_constant: , line:6:35, endln:6:36 |vpiDecompile:6 @@ -870,12 +870,12 @@ design: (work@prim_pad_wrapper) \_parameter: (work@prim_pad_wrapper.AttrDw), line:6:26, endln:6:32 |vpiDefName:work@prim_pad_wrapper |uhdmtopModules: -\_module: work@prim_pad_wrapper (work@prim_pad_wrapper), file:${SURELOG_DIR}/tests/SignedParam/dut.sv, line:2:1, endln:10:10 +\_module_inst: work@prim_pad_wrapper (work@prim_pad_wrapper), file:${SURELOG_DIR}/tests/SignedParam/dut.sv, line:2:1, endln:10:10 |vpiName:work@prim_pad_wrapper |vpiParameter: \_parameter: (work@prim_pad_wrapper.AttrDw), line:6:26, endln:6:32 |vpiParent: - \_module: work@prim_pad_wrapper (work@prim_pad_wrapper), file:${SURELOG_DIR}/tests/SignedParam/dut.sv, line:2:1, endln:10:10 + \_module_inst: work@prim_pad_wrapper (work@prim_pad_wrapper), file:${SURELOG_DIR}/tests/SignedParam/dut.sv, line:2:1, endln:10:10 |UINT:6 |vpiTypespec: \_int_typespec: , line:6:15, endln:6:18 @@ -888,7 +888,7 @@ design: (work@prim_pad_wrapper) |vpiParamAssign: \_param_assign: , line:6:26, endln:6:36 |vpiParent: - \_module: work@prim_pad_wrapper (work@prim_pad_wrapper), file:${SURELOG_DIR}/tests/SignedParam/dut.sv, line:2:1, endln:10:10 + \_module_inst: work@prim_pad_wrapper (work@prim_pad_wrapper), file:${SURELOG_DIR}/tests/SignedParam/dut.sv, line:2:1, endln:10:10 |vpiRhs: \_constant: , line:6:35, endln:6:36 |vpiDecompile:6 diff --git a/tests/SignedPort/SignedPort.log b/tests/SignedPort/SignedPort.log index 03732c75aa..6b5c400759 100644 --- a/tests/SignedPort/SignedPort.log +++ b/tests/SignedPort/SignedPort.log @@ -389,7 +389,7 @@ io_decl 11 logic_net 5 logic_typespec 7 logic_var 2 -module 4 +module_inst 4 package 2 port 4 range 10 @@ -416,7 +416,7 @@ io_decl 22 logic_net 5 logic_typespec 7 logic_var 2 -module 4 +module_inst 4 package 2 port 6 range 10 @@ -912,7 +912,7 @@ design: (work@dut) \_int_typespec: |vpiSigned:1 |uhdmallModules: -\_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/SignedPort/dut.sv, line:2:1, endln:5:10 +\_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/SignedPort/dut.sv, line:2:1, endln:5:10 |vpiParent: \_design: (work@dut) |vpiFullName:work@dut @@ -920,28 +920,28 @@ design: (work@dut) |vpiNet: \_logic_net: (work@dut.a), line:2:38, endln:2:39 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/SignedPort/dut.sv, line:2:1, endln:5:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/SignedPort/dut.sv, line:2:1, endln:5:10 |vpiName:a |vpiFullName:work@dut.a |vpiNetType:36 |vpiNet: \_logic_net: (work@dut.b), line:2:69, endln:2:70 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/SignedPort/dut.sv, line:2:1, endln:5:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/SignedPort/dut.sv, line:2:1, endln:5:10 |vpiName:b |vpiFullName:work@dut.b |vpiNetType:36 |vpiNet: \_logic_net: (work@dut.c), line:3:22, endln:3:23 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/SignedPort/dut.sv, line:2:1, endln:5:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/SignedPort/dut.sv, line:2:1, endln:5:10 |vpiName:c |vpiFullName:work@dut.c |vpiNetType:36 |vpiPort: \_port: (a), line:2:38, endln:2:39 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/SignedPort/dut.sv, line:2:1, endln:5:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/SignedPort/dut.sv, line:2:1, endln:5:10 |vpiName:a |vpiDirection:1 |vpiLowConn: @@ -972,7 +972,7 @@ design: (work@dut) |vpiPort: \_port: (b), line:2:69, endln:2:70 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/SignedPort/dut.sv, line:2:1, endln:5:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/SignedPort/dut.sv, line:2:1, endln:5:10 |vpiName:b |vpiDirection:2 |vpiLowConn: @@ -1002,7 +1002,7 @@ design: (work@dut) |vpiContAssign: \_cont_assign: , line:4:11, endln:4:27 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/SignedPort/dut.sv, line:2:1, endln:5:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/SignedPort/dut.sv, line:2:1, endln:5:10 |vpiRhs: \_sys_func_call: ($unsigned), line:4:15, endln:4:24 |vpiParent: @@ -1025,12 +1025,12 @@ design: (work@dut) |vpiActual: \_logic_net: (work@dut.b), line:2:69, endln:2:70 |uhdmtopModules: -\_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/SignedPort/dut.sv, line:2:1, endln:5:10 +\_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/SignedPort/dut.sv, line:2:1, endln:5:10 |vpiName:work@dut |vpiVariables: \_logic_var: (work@dut.c), line:3:22, endln:3:23 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/SignedPort/dut.sv, line:2:1, endln:5:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/SignedPort/dut.sv, line:2:1, endln:5:10 |vpiTypespec: \_logic_typespec: , line:3:3, endln:3:21 |vpiRange: @@ -1079,7 +1079,7 @@ design: (work@dut) |vpiNet: \_logic_net: (work@dut.a), line:2:38, endln:2:39 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/SignedPort/dut.sv, line:2:1, endln:5:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/SignedPort/dut.sv, line:2:1, endln:5:10 |vpiTypespec: \_logic_typespec: , line:2:19, endln:2:37 |vpiRange: @@ -1108,7 +1108,7 @@ design: (work@dut) |vpiNet: \_logic_net: (work@dut.b), line:2:69, endln:2:70 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/SignedPort/dut.sv, line:2:1, endln:5:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/SignedPort/dut.sv, line:2:1, endln:5:10 |vpiTypespec: \_logic_typespec: , line:2:48, endln:2:68 |vpiRange: @@ -1136,7 +1136,7 @@ design: (work@dut) |vpiPort: \_port: (a), line:2:38, endln:2:39 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/SignedPort/dut.sv, line:2:1, endln:5:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/SignedPort/dut.sv, line:2:1, endln:5:10 |vpiName:a |vpiDirection:1 |vpiLowConn: @@ -1171,11 +1171,11 @@ design: (work@dut) |vpiConstType:9 |vpiSigned:1 |vpiInstance: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/SignedPort/dut.sv, line:2:1, endln:5:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/SignedPort/dut.sv, line:2:1, endln:5:10 |vpiPort: \_port: (b), line:2:69, endln:2:70 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/SignedPort/dut.sv, line:2:1, endln:5:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/SignedPort/dut.sv, line:2:1, endln:5:10 |vpiName:b |vpiDirection:2 |vpiLowConn: @@ -1209,11 +1209,11 @@ design: (work@dut) |UINT:0 |vpiConstType:9 |vpiInstance: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/SignedPort/dut.sv, line:2:1, endln:5:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/SignedPort/dut.sv, line:2:1, endln:5:10 |vpiContAssign: \_cont_assign: , line:4:11, endln:4:27 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/SignedPort/dut.sv, line:2:1, endln:5:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/SignedPort/dut.sv, line:2:1, endln:5:10 |vpiRhs: \_sys_func_call: ($unsigned), line:4:15, endln:4:24 |vpiParent: diff --git a/tests/SignedPort2/SignedPort2.log b/tests/SignedPort2/SignedPort2.log index 271cbbb405..43401252b3 100644 --- a/tests/SignedPort2/SignedPort2.log +++ b/tests/SignedPort2/SignedPort2.log @@ -94,7 +94,7 @@ cont_assign 1 design 1 logic_net 4 logic_typespec 6 -module 4 +module_inst 4 port 4 range 4 ref_obj 6 @@ -107,7 +107,7 @@ cont_assign 2 design 1 logic_net 4 logic_typespec 6 -module 4 +module_inst 4 port 6 range 4 ref_obj 10 @@ -125,7 +125,7 @@ design: (work@wire_top) |vpiElaborated:1 |vpiName:work@wire_top |uhdmallModules: -\_module: work@wire_top (work@wire_top), file:${SURELOG_DIR}/tests/SignedPort2/dut.sv, line:1:1, endln:6:10 +\_module_inst: work@wire_top (work@wire_top), file:${SURELOG_DIR}/tests/SignedPort2/dut.sv, line:1:1, endln:6:10 |vpiParent: \_design: (work@wire_top) |vpiFullName:work@wire_top @@ -133,21 +133,21 @@ design: (work@wire_top) |vpiNet: \_logic_net: (work@wire_top.inp), line:1:17, endln:1:20 |vpiParent: - \_module: work@wire_top (work@wire_top), file:${SURELOG_DIR}/tests/SignedPort2/dut.sv, line:1:1, endln:6:10 + \_module_inst: work@wire_top (work@wire_top), file:${SURELOG_DIR}/tests/SignedPort2/dut.sv, line:1:1, endln:6:10 |vpiName:inp |vpiFullName:work@wire_top.inp |vpiNetType:1 |vpiNet: \_logic_net: (work@wire_top.xn), line:1:22, endln:1:24 |vpiParent: - \_module: work@wire_top (work@wire_top), file:${SURELOG_DIR}/tests/SignedPort2/dut.sv, line:1:1, endln:6:10 + \_module_inst: work@wire_top (work@wire_top), file:${SURELOG_DIR}/tests/SignedPort2/dut.sv, line:1:1, endln:6:10 |vpiName:xn |vpiFullName:work@wire_top.xn |vpiNetType:48 |vpiPort: \_port: (inp), line:1:17, endln:1:20 |vpiParent: - \_module: work@wire_top (work@wire_top), file:${SURELOG_DIR}/tests/SignedPort2/dut.sv, line:1:1, endln:6:10 + \_module_inst: work@wire_top (work@wire_top), file:${SURELOG_DIR}/tests/SignedPort2/dut.sv, line:1:1, endln:6:10 |vpiName:inp |vpiDirection:1 |vpiLowConn: @@ -159,7 +159,7 @@ design: (work@wire_top) |vpiPort: \_port: (xn), line:1:22, endln:1:24 |vpiParent: - \_module: work@wire_top (work@wire_top), file:${SURELOG_DIR}/tests/SignedPort2/dut.sv, line:1:1, endln:6:10 + \_module_inst: work@wire_top (work@wire_top), file:${SURELOG_DIR}/tests/SignedPort2/dut.sv, line:1:1, endln:6:10 |vpiName:xn |vpiDirection:2 |vpiLowConn: @@ -189,7 +189,7 @@ design: (work@wire_top) |vpiContAssign: \_cont_assign: , line:5:12, endln:5:20 |vpiParent: - \_module: work@wire_top (work@wire_top), file:${SURELOG_DIR}/tests/SignedPort2/dut.sv, line:1:1, endln:6:10 + \_module_inst: work@wire_top (work@wire_top), file:${SURELOG_DIR}/tests/SignedPort2/dut.sv, line:1:1, endln:6:10 |vpiRhs: \_ref_obj: (work@wire_top.inp), line:5:17, endln:5:20 |vpiParent: @@ -207,14 +207,14 @@ design: (work@wire_top) |vpiActual: \_logic_net: (work@wire_top.xn), line:1:22, endln:1:24 |uhdmtopModules: -\_module: work@wire_top (work@wire_top), file:${SURELOG_DIR}/tests/SignedPort2/dut.sv, line:1:1, endln:6:10 +\_module_inst: work@wire_top (work@wire_top), file:${SURELOG_DIR}/tests/SignedPort2/dut.sv, line:1:1, endln:6:10 |vpiName:work@wire_top |vpiDefName:work@wire_top |vpiTop:1 |vpiNet: \_logic_net: (work@wire_top.inp), line:1:17, endln:1:20 |vpiParent: - \_module: work@wire_top (work@wire_top), file:${SURELOG_DIR}/tests/SignedPort2/dut.sv, line:1:1, endln:6:10 + \_module_inst: work@wire_top (work@wire_top), file:${SURELOG_DIR}/tests/SignedPort2/dut.sv, line:1:1, endln:6:10 |vpiTypespec: \_logic_typespec: , line:2:11, endln:2:15 |vpiName:inp @@ -224,7 +224,7 @@ design: (work@wire_top) |vpiNet: \_logic_net: (work@wire_top.xn), line:1:22, endln:1:24 |vpiParent: - \_module: work@wire_top (work@wire_top), file:${SURELOG_DIR}/tests/SignedPort2/dut.sv, line:1:1, endln:6:10 + \_module_inst: work@wire_top (work@wire_top), file:${SURELOG_DIR}/tests/SignedPort2/dut.sv, line:1:1, endln:6:10 |vpiTypespec: \_logic_typespec: , line:3:12, endln:3:21 |vpiRange: @@ -252,7 +252,7 @@ design: (work@wire_top) |vpiPort: \_port: (inp), line:1:17, endln:1:20 |vpiParent: - \_module: work@wire_top (work@wire_top), file:${SURELOG_DIR}/tests/SignedPort2/dut.sv, line:1:1, endln:6:10 + \_module_inst: work@wire_top (work@wire_top), file:${SURELOG_DIR}/tests/SignedPort2/dut.sv, line:1:1, endln:6:10 |vpiName:inp |vpiDirection:1 |vpiLowConn: @@ -266,11 +266,11 @@ design: (work@wire_top) |vpiTypedef: \_logic_typespec: , line:2:11, endln:2:15 |vpiInstance: - \_module: work@wire_top (work@wire_top), file:${SURELOG_DIR}/tests/SignedPort2/dut.sv, line:1:1, endln:6:10 + \_module_inst: work@wire_top (work@wire_top), file:${SURELOG_DIR}/tests/SignedPort2/dut.sv, line:1:1, endln:6:10 |vpiPort: \_port: (xn), line:1:22, endln:1:24 |vpiParent: - \_module: work@wire_top (work@wire_top), file:${SURELOG_DIR}/tests/SignedPort2/dut.sv, line:1:1, endln:6:10 + \_module_inst: work@wire_top (work@wire_top), file:${SURELOG_DIR}/tests/SignedPort2/dut.sv, line:1:1, endln:6:10 |vpiName:xn |vpiDirection:2 |vpiLowConn: @@ -304,11 +304,11 @@ design: (work@wire_top) |UINT:0 |vpiConstType:9 |vpiInstance: - \_module: work@wire_top (work@wire_top), file:${SURELOG_DIR}/tests/SignedPort2/dut.sv, line:1:1, endln:6:10 + \_module_inst: work@wire_top (work@wire_top), file:${SURELOG_DIR}/tests/SignedPort2/dut.sv, line:1:1, endln:6:10 |vpiContAssign: \_cont_assign: , line:5:12, endln:5:20 |vpiParent: - \_module: work@wire_top (work@wire_top), file:${SURELOG_DIR}/tests/SignedPort2/dut.sv, line:1:1, endln:6:10 + \_module_inst: work@wire_top (work@wire_top), file:${SURELOG_DIR}/tests/SignedPort2/dut.sv, line:1:1, endln:6:10 |vpiRhs: \_ref_obj: (work@wire_top.inp), line:5:17, endln:5:20 |vpiParent: diff --git a/tests/SimpleClass1/SimpleClass1.log b/tests/SimpleClass1/SimpleClass1.log index c27b11a4de..fb406f5c37 100644 --- a/tests/SimpleClass1/SimpleClass1.log +++ b/tests/SimpleClass1/SimpleClass1.log @@ -841,7 +841,7 @@ logic_var 71 long_int_typespec 179 long_int_var 15 method_func_call 17747 -module 27 +module_inst 27 named_begin 18 named_event 8 named_fork 7 diff --git a/tests/SimpleConstraint/SimpleConstraint.log b/tests/SimpleConstraint/SimpleConstraint.log index 84d49443de..c480926323 100644 --- a/tests/SimpleConstraint/SimpleConstraint.log +++ b/tests/SimpleConstraint/SimpleConstraint.log @@ -1052,7 +1052,7 @@ io_decl 12 logic_net 2 logic_var 1 method_func_call 10 -module 2 +module_inst 2 operation 6 package 2 program 1 diff --git a/tests/SimpleInterface/SimpleInterface.log b/tests/SimpleInterface/SimpleInterface.log index 707e905f32..bb5f51334e 100644 --- a/tests/SimpleInterface/SimpleInterface.log +++ b/tests/SimpleInterface/SimpleInterface.log @@ -2215,7 +2215,7 @@ indexed_part_select 41 initial 1 int_typespec 2681 int_var 1171 -interface 5 +interface_inst 5 interface_typespec 3 io_decl 6913 logic_net 474 @@ -2225,7 +2225,7 @@ long_int_typespec 99 long_int_var 7 method_func_call 7996 modport 6 -module 36 +module_inst 36 named_begin 6 named_event 8 named_fork 3 diff --git a/tests/SimpleTask/SimpleTask.log b/tests/SimpleTask/SimpleTask.log index 142be91d9e..fc516b3f0d 100644 --- a/tests/SimpleTask/SimpleTask.log +++ b/tests/SimpleTask/SimpleTask.log @@ -99,7 +99,7 @@ io_decl 15 logic_net 18 logic_typespec 8 logic_var 1 -module 3 +module_inst 3 operation 10 package 2 range 13 diff --git a/tests/SplitFile/SplitFile.log b/tests/SplitFile/SplitFile.log index 0184d1c26e..2f11ab1933 100644 --- a/tests/SplitFile/SplitFile.log +++ b/tests/SplitFile/SplitFile.log @@ -228,12 +228,12 @@ function 9 gate 1 int_typespec 9 int_var 4 -interface 3 +interface_inst 3 io_decl 11 logic_net 27 logic_typespec 19 logic_var 1 -module 27 +module_inst 27 operation 2 package 14 port 20 diff --git a/tests/StandardBlock/StandardBlock.log b/tests/StandardBlock/StandardBlock.log index b772f55982..7453fab800 100644 --- a/tests/StandardBlock/StandardBlock.log +++ b/tests/StandardBlock/StandardBlock.log @@ -290,7 +290,7 @@ gen_scope_array 14 int_typespec 4 logic_typespec 5 logic_var 5 -module 5 +module_inst 5 operation 4 param_assign 2 parameter 4 @@ -305,7 +305,7 @@ gen_scope_array 21 int_typespec 4 logic_typespec 5 logic_var 10 -module 5 +module_inst 5 operation 4 param_assign 2 parameter 4 @@ -323,14 +323,14 @@ design: (work@top) |vpiElaborated:1 |vpiName:work@top |uhdmallModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/StandardBlock/dut.sv, line:1:1, endln:28:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/StandardBlock/dut.sv, line:1:1, endln:28:10 |vpiParent: \_design: (work@top) |vpiFullName:work@top |vpiParameter: \_parameter: (work@top.genblk2), line:2:11, endln:2:18 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/StandardBlock/dut.sv, line:1:1, endln:28:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/StandardBlock/dut.sv, line:1:1, endln:28:10 |UINT:0 |vpiTypespec: \_int_typespec: @@ -339,7 +339,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:2:11, endln:2:22 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/StandardBlock/dut.sv, line:1:1, endln:28:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/StandardBlock/dut.sv, line:1:1, endln:28:10 |vpiRhs: \_constant: , line:2:21, endln:2:22 |vpiDecompile:0 @@ -352,12 +352,12 @@ design: (work@top) \_parameter: (work@top.genblk2), line:2:11, endln:2:18 |vpiDefName:work@top |uhdmtopModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/StandardBlock/dut.sv, line:1:1, endln:28:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/StandardBlock/dut.sv, line:1:1, endln:28:10 |vpiName:work@top |vpiParameter: \_parameter: (work@top.genblk2), line:2:11, endln:2:18 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/StandardBlock/dut.sv, line:1:1, endln:28:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/StandardBlock/dut.sv, line:1:1, endln:28:10 |UINT:0 |vpiTypespec: \_int_typespec: @@ -368,7 +368,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:2:11, endln:2:22 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/StandardBlock/dut.sv, line:1:1, endln:28:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/StandardBlock/dut.sv, line:1:1, endln:28:10 |vpiRhs: \_constant: , line:2:21, endln:2:22 |vpiDecompile:0 @@ -385,7 +385,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.genblk1), line:5:1, endln:6:14 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/StandardBlock/dut.sv, line:1:1, endln:28:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/StandardBlock/dut.sv, line:1:1, endln:28:10 |vpiName:genblk1 |vpiFullName:work@top.genblk1 |vpiGenScope: @@ -405,7 +405,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.genblk02), line:9:1, endln:10:14 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/StandardBlock/dut.sv, line:1:1, endln:28:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/StandardBlock/dut.sv, line:1:1, endln:28:10 |vpiName:genblk02 |vpiFullName:work@top.genblk02 |vpiGenScope: @@ -425,7 +425,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.g1[0]), line:13:31, endln:17:4 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/StandardBlock/dut.sv, line:1:1, endln:28:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/StandardBlock/dut.sv, line:1:1, endln:28:10 |vpiName:g1[0] |vpiFullName:work@top.g1[0] |vpiGenScope: @@ -466,7 +466,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.genblk4[0]), line:25:1, endln:25:16 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/StandardBlock/dut.sv, line:1:1, endln:28:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/StandardBlock/dut.sv, line:1:1, endln:28:10 |vpiName:genblk4[0] |vpiFullName:work@top.genblk4[0] |vpiGenScope: @@ -507,7 +507,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.genblk5), line:27:1, endln:27:16 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/StandardBlock/dut.sv, line:1:1, endln:28:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/StandardBlock/dut.sv, line:1:1, endln:28:10 |vpiName:genblk5 |vpiFullName:work@top.genblk5 |vpiGenScope: diff --git a/tests/StandardNetVar/StandardNetVar.log b/tests/StandardNetVar/StandardNetVar.log index c35d413e7d..7b382b2fd5 100644 --- a/tests/StandardNetVar/StandardNetVar.log +++ b/tests/StandardNetVar/StandardNetVar.log @@ -127,7 +127,7 @@ design 1 logic_net 14 logic_typespec 18 logic_var 4 -module 2 +module_inst 2 port 10 ref_obj 10 === UHDM Object Stats End === @@ -138,7 +138,7 @@ design 1 logic_net 14 logic_typespec 18 logic_var 4 -module 2 +module_inst 2 port 15 ref_obj 15 === UHDM Object Stats End === @@ -155,7 +155,7 @@ design: (work@net_vars) |vpiElaborated:1 |vpiName:work@net_vars |uhdmallModules: -\_module: work@net_vars (work@net_vars), file:${SURELOG_DIR}/tests/StandardNetVar/dut.sv, line:1:1, endln:8:10 +\_module_inst: work@net_vars (work@net_vars), file:${SURELOG_DIR}/tests/StandardNetVar/dut.sv, line:1:1, endln:8:10 |vpiParent: \_design: (work@net_vars) |vpiFullName:work@net_vars @@ -163,67 +163,67 @@ design: (work@net_vars) |vpiNet: \_logic_net: (work@net_vars.i1), line:1:34, endln:1:36 |vpiParent: - \_module: work@net_vars (work@net_vars), file:${SURELOG_DIR}/tests/StandardNetVar/dut.sv, line:1:1, endln:8:10 + \_module_inst: work@net_vars (work@net_vars), file:${SURELOG_DIR}/tests/StandardNetVar/dut.sv, line:1:1, endln:8:10 |vpiName:i1 |vpiFullName:work@net_vars.i1 |vpiNetType:36 |vpiNet: \_logic_net: (work@net_vars.i2), line:1:54, endln:1:56 |vpiParent: - \_module: work@net_vars (work@net_vars), file:${SURELOG_DIR}/tests/StandardNetVar/dut.sv, line:1:1, endln:8:10 + \_module_inst: work@net_vars (work@net_vars), file:${SURELOG_DIR}/tests/StandardNetVar/dut.sv, line:1:1, endln:8:10 |vpiName:i2 |vpiFullName:work@net_vars.i2 |vpiNet: \_logic_net: (work@net_vars.i3), line:1:80, endln:1:82 |vpiParent: - \_module: work@net_vars (work@net_vars), file:${SURELOG_DIR}/tests/StandardNetVar/dut.sv, line:1:1, endln:8:10 + \_module_inst: work@net_vars (work@net_vars), file:${SURELOG_DIR}/tests/StandardNetVar/dut.sv, line:1:1, endln:8:10 |vpiName:i3 |vpiFullName:work@net_vars.i3 |vpiNetType:36 |vpiNet: \_logic_net: (work@net_vars.o1), line:1:111, endln:1:113 |vpiParent: - \_module: work@net_vars (work@net_vars), file:${SURELOG_DIR}/tests/StandardNetVar/dut.sv, line:1:1, endln:8:10 + \_module_inst: work@net_vars (work@net_vars), file:${SURELOG_DIR}/tests/StandardNetVar/dut.sv, line:1:1, endln:8:10 |vpiName:o1 |vpiFullName:work@net_vars.o1 |vpiNetType:36 |vpiNet: \_logic_net: (work@net_vars.o2), line:1:133, endln:1:135 |vpiParent: - \_module: work@net_vars (work@net_vars), file:${SURELOG_DIR}/tests/StandardNetVar/dut.sv, line:1:1, endln:8:10 + \_module_inst: work@net_vars (work@net_vars), file:${SURELOG_DIR}/tests/StandardNetVar/dut.sv, line:1:1, endln:8:10 |vpiName:o2 |vpiFullName:work@net_vars.o2 |vpiNet: \_logic_net: (work@net_vars.a), line:3:6, endln:3:7 |vpiParent: - \_module: work@net_vars (work@net_vars), file:${SURELOG_DIR}/tests/StandardNetVar/dut.sv, line:1:1, endln:8:10 + \_module_inst: work@net_vars (work@net_vars), file:${SURELOG_DIR}/tests/StandardNetVar/dut.sv, line:1:1, endln:8:10 |vpiName:a |vpiFullName:work@net_vars.a |vpiNetType:1 |vpiNet: \_logic_net: (work@net_vars.b), line:4:12, endln:4:13 |vpiParent: - \_module: work@net_vars (work@net_vars), file:${SURELOG_DIR}/tests/StandardNetVar/dut.sv, line:1:1, endln:8:10 + \_module_inst: work@net_vars (work@net_vars), file:${SURELOG_DIR}/tests/StandardNetVar/dut.sv, line:1:1, endln:8:10 |vpiName:b |vpiFullName:work@net_vars.b |vpiNetType:1 |vpiNet: \_logic_net: (work@net_vars.c), line:5:7, endln:5:8 |vpiParent: - \_module: work@net_vars (work@net_vars), file:${SURELOG_DIR}/tests/StandardNetVar/dut.sv, line:1:1, endln:8:10 + \_module_inst: work@net_vars (work@net_vars), file:${SURELOG_DIR}/tests/StandardNetVar/dut.sv, line:1:1, endln:8:10 |vpiName:c |vpiFullName:work@net_vars.c |vpiNetType:36 |vpiNet: \_logic_net: (work@net_vars.d), line:6:5, endln:6:6 |vpiParent: - \_module: work@net_vars (work@net_vars), file:${SURELOG_DIR}/tests/StandardNetVar/dut.sv, line:1:1, endln:8:10 + \_module_inst: work@net_vars (work@net_vars), file:${SURELOG_DIR}/tests/StandardNetVar/dut.sv, line:1:1, endln:8:10 |vpiName:d |vpiFullName:work@net_vars.d |vpiPort: \_port: (i1), line:1:34, endln:1:36 |vpiParent: - \_module: work@net_vars (work@net_vars), file:${SURELOG_DIR}/tests/StandardNetVar/dut.sv, line:1:1, endln:8:10 + \_module_inst: work@net_vars (work@net_vars), file:${SURELOG_DIR}/tests/StandardNetVar/dut.sv, line:1:1, endln:8:10 |vpiName:i1 |vpiDirection:1 |vpiLowConn: @@ -235,7 +235,7 @@ design: (work@net_vars) |vpiPort: \_port: (i2), line:1:54, endln:1:56 |vpiParent: - \_module: work@net_vars (work@net_vars), file:${SURELOG_DIR}/tests/StandardNetVar/dut.sv, line:1:1, endln:8:10 + \_module_inst: work@net_vars (work@net_vars), file:${SURELOG_DIR}/tests/StandardNetVar/dut.sv, line:1:1, endln:8:10 |vpiName:i2 |vpiDirection:1 |vpiLowConn: @@ -247,7 +247,7 @@ design: (work@net_vars) |vpiPort: \_port: (i3), line:1:80, endln:1:82 |vpiParent: - \_module: work@net_vars (work@net_vars), file:${SURELOG_DIR}/tests/StandardNetVar/dut.sv, line:1:1, endln:8:10 + \_module_inst: work@net_vars (work@net_vars), file:${SURELOG_DIR}/tests/StandardNetVar/dut.sv, line:1:1, endln:8:10 |vpiName:i3 |vpiDirection:1 |vpiLowConn: @@ -259,7 +259,7 @@ design: (work@net_vars) |vpiPort: \_port: (o1), line:1:111, endln:1:113 |vpiParent: - \_module: work@net_vars (work@net_vars), file:${SURELOG_DIR}/tests/StandardNetVar/dut.sv, line:1:1, endln:8:10 + \_module_inst: work@net_vars (work@net_vars), file:${SURELOG_DIR}/tests/StandardNetVar/dut.sv, line:1:1, endln:8:10 |vpiName:o1 |vpiDirection:2 |vpiLowConn: @@ -271,7 +271,7 @@ design: (work@net_vars) |vpiPort: \_port: (o2), line:1:133, endln:1:135 |vpiParent: - \_module: work@net_vars (work@net_vars), file:${SURELOG_DIR}/tests/StandardNetVar/dut.sv, line:1:1, endln:8:10 + \_module_inst: work@net_vars (work@net_vars), file:${SURELOG_DIR}/tests/StandardNetVar/dut.sv, line:1:1, endln:8:10 |vpiName:o2 |vpiDirection:2 |vpiLowConn: @@ -281,12 +281,12 @@ design: (work@net_vars) |vpiTypedef: \_logic_typespec: , line:1:133, endln:1:133 |uhdmtopModules: -\_module: work@net_vars (work@net_vars), file:${SURELOG_DIR}/tests/StandardNetVar/dut.sv, line:1:1, endln:8:10 +\_module_inst: work@net_vars (work@net_vars), file:${SURELOG_DIR}/tests/StandardNetVar/dut.sv, line:1:1, endln:8:10 |vpiName:work@net_vars |vpiVariables: \_logic_var: (work@net_vars.i1), line:1:34, endln:1:36 |vpiParent: - \_module: work@net_vars (work@net_vars), file:${SURELOG_DIR}/tests/StandardNetVar/dut.sv, line:1:1, endln:8:10 + \_module_inst: work@net_vars (work@net_vars), file:${SURELOG_DIR}/tests/StandardNetVar/dut.sv, line:1:1, endln:8:10 |vpiTypespec: \_logic_typespec: , line:1:28, endln:1:33 |vpiName:i1 @@ -295,7 +295,7 @@ design: (work@net_vars) |vpiVariables: \_logic_var: (work@net_vars.o1), line:1:111, endln:1:113 |vpiParent: - \_module: work@net_vars (work@net_vars), file:${SURELOG_DIR}/tests/StandardNetVar/dut.sv, line:1:1, endln:8:10 + \_module_inst: work@net_vars (work@net_vars), file:${SURELOG_DIR}/tests/StandardNetVar/dut.sv, line:1:1, endln:8:10 |vpiTypespec: \_logic_typespec: , line:1:105, endln:1:110 |vpiName:o1 @@ -304,7 +304,7 @@ design: (work@net_vars) |vpiVariables: \_logic_var: (work@net_vars.c), line:5:7, endln:5:8 |vpiParent: - \_module: work@net_vars (work@net_vars), file:${SURELOG_DIR}/tests/StandardNetVar/dut.sv, line:1:1, endln:8:10 + \_module_inst: work@net_vars (work@net_vars), file:${SURELOG_DIR}/tests/StandardNetVar/dut.sv, line:1:1, endln:8:10 |vpiTypespec: \_logic_typespec: , line:5:1, endln:5:6 |vpiName:c @@ -313,7 +313,7 @@ design: (work@net_vars) |vpiVariables: \_logic_var: (work@net_vars.d), line:6:5, endln:6:6 |vpiParent: - \_module: work@net_vars (work@net_vars), file:${SURELOG_DIR}/tests/StandardNetVar/dut.sv, line:1:1, endln:8:10 + \_module_inst: work@net_vars (work@net_vars), file:${SURELOG_DIR}/tests/StandardNetVar/dut.sv, line:1:1, endln:8:10 |vpiName:d |vpiFullName:work@net_vars.d |vpiVisibility:1 @@ -322,7 +322,7 @@ design: (work@net_vars) |vpiNet: \_logic_net: (work@net_vars.i2), line:1:54, endln:1:56 |vpiParent: - \_module: work@net_vars (work@net_vars), file:${SURELOG_DIR}/tests/StandardNetVar/dut.sv, line:1:1, endln:8:10 + \_module_inst: work@net_vars (work@net_vars), file:${SURELOG_DIR}/tests/StandardNetVar/dut.sv, line:1:1, endln:8:10 |vpiTypespec: \_logic_typespec: , line:1:54, endln:1:54 |vpiName:i2 @@ -330,7 +330,7 @@ design: (work@net_vars) |vpiNet: \_logic_net: (work@net_vars.i3), line:1:80, endln:1:82 |vpiParent: - \_module: work@net_vars (work@net_vars), file:${SURELOG_DIR}/tests/StandardNetVar/dut.sv, line:1:1, endln:8:10 + \_module_inst: work@net_vars (work@net_vars), file:${SURELOG_DIR}/tests/StandardNetVar/dut.sv, line:1:1, endln:8:10 |vpiTypespec: \_logic_typespec: , line:1:74, endln:1:79 |vpiName:i3 @@ -339,7 +339,7 @@ design: (work@net_vars) |vpiNet: \_logic_net: (work@net_vars.o2), line:1:133, endln:1:135 |vpiParent: - \_module: work@net_vars (work@net_vars), file:${SURELOG_DIR}/tests/StandardNetVar/dut.sv, line:1:1, endln:8:10 + \_module_inst: work@net_vars (work@net_vars), file:${SURELOG_DIR}/tests/StandardNetVar/dut.sv, line:1:1, endln:8:10 |vpiTypespec: \_logic_typespec: , line:1:133, endln:1:133 |vpiName:o2 @@ -347,7 +347,7 @@ design: (work@net_vars) |vpiNet: \_logic_net: (work@net_vars.a), line:3:6, endln:3:7 |vpiParent: - \_module: work@net_vars (work@net_vars), file:${SURELOG_DIR}/tests/StandardNetVar/dut.sv, line:1:1, endln:8:10 + \_module_inst: work@net_vars (work@net_vars), file:${SURELOG_DIR}/tests/StandardNetVar/dut.sv, line:1:1, endln:8:10 |vpiTypespec: \_logic_typespec: , line:3:1, endln:3:5 |vpiName:a @@ -356,7 +356,7 @@ design: (work@net_vars) |vpiNet: \_logic_net: (work@net_vars.b), line:4:12, endln:4:13 |vpiParent: - \_module: work@net_vars (work@net_vars), file:${SURELOG_DIR}/tests/StandardNetVar/dut.sv, line:1:1, endln:8:10 + \_module_inst: work@net_vars (work@net_vars), file:${SURELOG_DIR}/tests/StandardNetVar/dut.sv, line:1:1, endln:8:10 |vpiTypespec: \_logic_typespec: , line:4:6, endln:4:11 |vpiName:b @@ -366,7 +366,7 @@ design: (work@net_vars) |vpiPort: \_port: (i1), line:1:34, endln:1:36 |vpiParent: - \_module: work@net_vars (work@net_vars), file:${SURELOG_DIR}/tests/StandardNetVar/dut.sv, line:1:1, endln:8:10 + \_module_inst: work@net_vars (work@net_vars), file:${SURELOG_DIR}/tests/StandardNetVar/dut.sv, line:1:1, endln:8:10 |vpiName:i1 |vpiDirection:1 |vpiLowConn: @@ -380,11 +380,11 @@ design: (work@net_vars) |vpiTypedef: \_logic_typespec: , line:1:28, endln:1:33 |vpiInstance: - \_module: work@net_vars (work@net_vars), file:${SURELOG_DIR}/tests/StandardNetVar/dut.sv, line:1:1, endln:8:10 + \_module_inst: work@net_vars (work@net_vars), file:${SURELOG_DIR}/tests/StandardNetVar/dut.sv, line:1:1, endln:8:10 |vpiPort: \_port: (i2), line:1:54, endln:1:56 |vpiParent: - \_module: work@net_vars (work@net_vars), file:${SURELOG_DIR}/tests/StandardNetVar/dut.sv, line:1:1, endln:8:10 + \_module_inst: work@net_vars (work@net_vars), file:${SURELOG_DIR}/tests/StandardNetVar/dut.sv, line:1:1, endln:8:10 |vpiName:i2 |vpiDirection:1 |vpiLowConn: @@ -398,11 +398,11 @@ design: (work@net_vars) |vpiTypedef: \_logic_typespec: , line:1:54, endln:1:54 |vpiInstance: - \_module: work@net_vars (work@net_vars), file:${SURELOG_DIR}/tests/StandardNetVar/dut.sv, line:1:1, endln:8:10 + \_module_inst: work@net_vars (work@net_vars), file:${SURELOG_DIR}/tests/StandardNetVar/dut.sv, line:1:1, endln:8:10 |vpiPort: \_port: (i3), line:1:80, endln:1:82 |vpiParent: - \_module: work@net_vars (work@net_vars), file:${SURELOG_DIR}/tests/StandardNetVar/dut.sv, line:1:1, endln:8:10 + \_module_inst: work@net_vars (work@net_vars), file:${SURELOG_DIR}/tests/StandardNetVar/dut.sv, line:1:1, endln:8:10 |vpiName:i3 |vpiDirection:1 |vpiLowConn: @@ -416,11 +416,11 @@ design: (work@net_vars) |vpiTypedef: \_logic_typespec: , line:1:74, endln:1:79 |vpiInstance: - \_module: work@net_vars (work@net_vars), file:${SURELOG_DIR}/tests/StandardNetVar/dut.sv, line:1:1, endln:8:10 + \_module_inst: work@net_vars (work@net_vars), file:${SURELOG_DIR}/tests/StandardNetVar/dut.sv, line:1:1, endln:8:10 |vpiPort: \_port: (o1), line:1:111, endln:1:113 |vpiParent: - \_module: work@net_vars (work@net_vars), file:${SURELOG_DIR}/tests/StandardNetVar/dut.sv, line:1:1, endln:8:10 + \_module_inst: work@net_vars (work@net_vars), file:${SURELOG_DIR}/tests/StandardNetVar/dut.sv, line:1:1, endln:8:10 |vpiName:o1 |vpiDirection:2 |vpiLowConn: @@ -434,11 +434,11 @@ design: (work@net_vars) |vpiTypedef: \_logic_typespec: , line:1:105, endln:1:110 |vpiInstance: - \_module: work@net_vars (work@net_vars), file:${SURELOG_DIR}/tests/StandardNetVar/dut.sv, line:1:1, endln:8:10 + \_module_inst: work@net_vars (work@net_vars), file:${SURELOG_DIR}/tests/StandardNetVar/dut.sv, line:1:1, endln:8:10 |vpiPort: \_port: (o2), line:1:133, endln:1:135 |vpiParent: - \_module: work@net_vars (work@net_vars), file:${SURELOG_DIR}/tests/StandardNetVar/dut.sv, line:1:1, endln:8:10 + \_module_inst: work@net_vars (work@net_vars), file:${SURELOG_DIR}/tests/StandardNetVar/dut.sv, line:1:1, endln:8:10 |vpiName:o2 |vpiDirection:2 |vpiLowConn: @@ -452,7 +452,7 @@ design: (work@net_vars) |vpiTypedef: \_logic_typespec: , line:1:133, endln:1:133 |vpiInstance: - \_module: work@net_vars (work@net_vars), file:${SURELOG_DIR}/tests/StandardNetVar/dut.sv, line:1:1, endln:8:10 + \_module_inst: work@net_vars (work@net_vars), file:${SURELOG_DIR}/tests/StandardNetVar/dut.sv, line:1:1, endln:8:10 =================== [ FATAL] : 0 [ SYNTAX] : 0 diff --git a/tests/StaticTask/StaticTask.log b/tests/StaticTask/StaticTask.log index 5c114fcf9c..c24b770345 100644 --- a/tests/StaticTask/StaticTask.log +++ b/tests/StaticTask/StaticTask.log @@ -110,7 +110,7 @@ design 1 initial 1 integer_typespec 1 integer_var 1 -module 2 +module_inst 2 operation 1 ref_obj 3 sys_func_call 1 @@ -128,7 +128,7 @@ design 1 initial 2 integer_typespec 1 integer_var 4 -module 2 +module_inst 2 operation 2 ref_obj 6 sys_func_call 2 @@ -148,7 +148,7 @@ design: (work@tb) |vpiElaborated:1 |vpiName:work@tb |uhdmallModules: -\_module: work@tb (work@tb), file:${SURELOG_DIR}/tests/StaticTask/dut.sv, line:1:1, endln:10:10 +\_module_inst: work@tb (work@tb), file:${SURELOG_DIR}/tests/StaticTask/dut.sv, line:1:1, endln:10:10 |vpiParent: \_design: (work@tb) |vpiFullName:work@tb @@ -156,7 +156,7 @@ design: (work@tb) |vpiTaskFunc: \_task: (work@tb.display), line:5:2, endln:9:9 |vpiParent: - \_module: work@tb (work@tb), file:${SURELOG_DIR}/tests/StaticTask/dut.sv, line:1:1, endln:10:10 + \_module_inst: work@tb (work@tb), file:${SURELOG_DIR}/tests/StaticTask/dut.sv, line:1:1, endln:10:10 |vpiName:display |vpiFullName:work@tb.display |vpiVariables: @@ -171,7 +171,7 @@ design: (work@tb) |vpiSigned:1 |vpiVisibility:1 |vpiParent: - \_module: work@tb (work@tb), file:${SURELOG_DIR}/tests/StaticTask/dut.sv, line:1:1, endln:10:10 + \_module_inst: work@tb (work@tb), file:${SURELOG_DIR}/tests/StaticTask/dut.sv, line:1:1, endln:10:10 |vpiStmt: \_begin: (work@tb.display) |vpiParent: @@ -250,11 +250,11 @@ design: (work@tb) \_integer_var: (work@tb.display.i), line:6:10, endln:6:11 |vpiName:$display |vpiInstance: - \_module: work@tb (work@tb), file:${SURELOG_DIR}/tests/StaticTask/dut.sv, line:1:1, endln:10:10 + \_module_inst: work@tb (work@tb), file:${SURELOG_DIR}/tests/StaticTask/dut.sv, line:1:1, endln:10:10 |vpiProcess: \_initial: , line:3:2, endln:3:20 |vpiParent: - \_module: work@tb (work@tb), file:${SURELOG_DIR}/tests/StaticTask/dut.sv, line:1:1, endln:10:10 + \_module_inst: work@tb (work@tb), file:${SURELOG_DIR}/tests/StaticTask/dut.sv, line:1:1, endln:10:10 |vpiStmt: \_task_call: (display), line:3:10, endln:3:19 |vpiParent: @@ -263,14 +263,14 @@ design: (work@tb) |vpiTask: \_task: (work@tb.display), line:5:2, endln:9:9 |uhdmtopModules: -\_module: work@tb (work@tb), file:${SURELOG_DIR}/tests/StaticTask/dut.sv, line:1:1, endln:10:10 +\_module_inst: work@tb (work@tb), file:${SURELOG_DIR}/tests/StaticTask/dut.sv, line:1:1, endln:10:10 |vpiName:work@tb |vpiDefName:work@tb |vpiTop:1 |vpiTaskFunc: \_task: (work@tb.display), line:5:2, endln:9:9 |vpiParent: - \_module: work@tb (work@tb), file:${SURELOG_DIR}/tests/StaticTask/dut.sv, line:1:1, endln:10:10 + \_module_inst: work@tb (work@tb), file:${SURELOG_DIR}/tests/StaticTask/dut.sv, line:1:1, endln:10:10 |vpiName:display |vpiFullName:work@tb.display |vpiVariables: @@ -284,7 +284,7 @@ design: (work@tb) |vpiSigned:1 |vpiVisibility:1 |vpiParent: - \_module: work@tb (work@tb), file:${SURELOG_DIR}/tests/StaticTask/dut.sv, line:1:1, endln:10:10 + \_module_inst: work@tb (work@tb), file:${SURELOG_DIR}/tests/StaticTask/dut.sv, line:1:1, endln:10:10 |vpiStmt: \_begin: (work@tb.display) |vpiParent: @@ -359,12 +359,12 @@ design: (work@tb) \_integer_var: (work@tb.display.i), line:6:10, endln:6:11 |vpiName:$display |vpiInstance: - \_module: work@tb (work@tb), file:${SURELOG_DIR}/tests/StaticTask/dut.sv, line:1:1, endln:10:10 + \_module_inst: work@tb (work@tb), file:${SURELOG_DIR}/tests/StaticTask/dut.sv, line:1:1, endln:10:10 |vpiTopModule:1 |vpiProcess: \_initial: , line:3:2, endln:3:20 |vpiParent: - \_module: work@tb (work@tb), file:${SURELOG_DIR}/tests/StaticTask/dut.sv, line:1:1, endln:10:10 + \_module_inst: work@tb (work@tb), file:${SURELOG_DIR}/tests/StaticTask/dut.sv, line:1:1, endln:10:10 |vpiStmt: \_task_call: (display), line:3:10, endln:3:19 |vpiParent: diff --git a/tests/StreamingOp/StreamingOp.log b/tests/StreamingOp/StreamingOp.log index da11aacc0e..5eae005cd3 100644 --- a/tests/StreamingOp/StreamingOp.log +++ b/tests/StreamingOp/StreamingOp.log @@ -122,7 +122,7 @@ constant 3 cont_assign 3 design 1 logic_net 5 -module 3 +module_inst 3 operation 6 ref_obj 7 === UHDM Object Stats End === @@ -133,7 +133,7 @@ constant 3 cont_assign 6 design 1 logic_net 5 -module 3 +module_inst 3 operation 12 ref_obj 14 === UHDM Object Stats End === @@ -150,7 +150,7 @@ design: (work@dut) |vpiElaborated:1 |vpiName:work@dut |uhdmallModules: -\_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/StreamingOp/dut.sv, line:1:1, endln:5:10 +\_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/StreamingOp/dut.sv, line:1:1, endln:5:10 |vpiParent: \_design: (work@dut) |vpiFullName:work@dut @@ -158,7 +158,7 @@ design: (work@dut) |vpiContAssign: \_cont_assign: , line:2:10, endln:2:29 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/StreamingOp/dut.sv, line:1:1, endln:5:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/StreamingOp/dut.sv, line:1:1, endln:5:10 |vpiRhs: \_operation: , line:2:21, endln:2:27 |vpiParent: @@ -196,7 +196,7 @@ design: (work@dut) |vpiContAssign: \_cont_assign: , line:3:10, endln:3:36 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/StreamingOp/dut.sv, line:1:1, endln:5:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/StreamingOp/dut.sv, line:1:1, endln:5:10 |vpiRhs: \_operation: , line:3:19, endln:3:34 |vpiParent: @@ -229,7 +229,7 @@ design: (work@dut) |vpiContAssign: \_cont_assign: , line:4:10, endln:4:33 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/StreamingOp/dut.sv, line:1:1, endln:5:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/StreamingOp/dut.sv, line:1:1, endln:5:10 |vpiRhs: \_operation: , line:4:29, endln:4:32 |vpiParent: @@ -260,7 +260,7 @@ design: (work@dut) |vpiActual: \_logic_net: (conv_data) |uhdmtopModules: -\_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/StreamingOp/dut.sv, line:1:1, endln:5:10 +\_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/StreamingOp/dut.sv, line:1:1, endln:5:10 |vpiName:work@dut |vpiDefName:work@dut |vpiTop:1 @@ -288,7 +288,7 @@ design: (work@dut) |vpiContAssign: \_cont_assign: , line:2:10, endln:2:29 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/StreamingOp/dut.sv, line:1:1, endln:5:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/StreamingOp/dut.sv, line:1:1, endln:5:10 |vpiRhs: \_operation: , line:2:21, endln:2:27 |vpiParent: @@ -328,7 +328,7 @@ design: (work@dut) |vpiContAssign: \_cont_assign: , line:3:10, endln:3:36 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/StreamingOp/dut.sv, line:1:1, endln:5:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/StreamingOp/dut.sv, line:1:1, endln:5:10 |vpiRhs: \_operation: , line:3:19, endln:3:34 |vpiParent: @@ -360,7 +360,7 @@ design: (work@dut) |vpiContAssign: \_cont_assign: , line:4:10, endln:4:33 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/StreamingOp/dut.sv, line:1:1, endln:5:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/StreamingOp/dut.sv, line:1:1, endln:5:10 |vpiRhs: \_operation: , line:4:29, endln:4:32 |vpiParent: diff --git a/tests/StringConcat/StringConcat.log b/tests/StringConcat/StringConcat.log index 2009f32f77..0ffc8078fe 100644 --- a/tests/StringConcat/StringConcat.log +++ b/tests/StringConcat/StringConcat.log @@ -29,7 +29,7 @@ === UHDM Object Stats Begin (Non-Elaborated Model) === constant 6 design 1 -module 4 +module_inst 4 operation 2 param_assign 2 parameter 2 @@ -40,7 +40,7 @@ string_typespec 2 === UHDM Object Stats Begin (Elaborated Model) === constant 6 design 1 -module 4 +module_inst 4 operation 2 param_assign 2 parameter 2 @@ -59,14 +59,14 @@ design: (work@top) |vpiElaborated:1 |vpiName:work@top |uhdmallModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/StringConcat/dut.sv, line:1:1, endln:3:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/StringConcat/dut.sv, line:1:1, endln:3:10 |vpiParent: \_design: (work@top) |vpiFullName:work@top |vpiParameter: \_parameter: (work@top.X), line:2:22, endln:2:23 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/StringConcat/dut.sv, line:1:1, endln:3:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/StringConcat/dut.sv, line:1:1, endln:3:10 |vpiTypespec: \_string_typespec: , line:2:15, endln:2:21 |vpiParent: @@ -77,7 +77,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:2:22, endln:2:42 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/StringConcat/dut.sv, line:1:1, endln:3:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/StringConcat/dut.sv, line:1:1, endln:3:10 |vpiRhs: \_operation: , line:2:26, endln:2:42 |vpiOpType:33 @@ -101,12 +101,12 @@ design: (work@top) \_parameter: (work@top.X), line:2:22, endln:2:23 |vpiDefName:work@top |uhdmtopModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/StringConcat/dut.sv, line:1:1, endln:3:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/StringConcat/dut.sv, line:1:1, endln:3:10 |vpiName:work@top |vpiParameter: \_parameter: (work@top.X), line:2:22, endln:2:23 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/StringConcat/dut.sv, line:1:1, endln:3:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/StringConcat/dut.sv, line:1:1, endln:3:10 |vpiTypespec: \_string_typespec: , line:2:15, endln:2:21 |vpiParent: @@ -117,7 +117,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:2:22, endln:2:42 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/StringConcat/dut.sv, line:1:1, endln:3:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/StringConcat/dut.sv, line:1:1, endln:3:10 |vpiRhs: \_constant: , line:2:26, endln:2:42 |vpiDecompile:abcdefgh diff --git a/tests/StringMethod/StringMethod.log b/tests/StringMethod/StringMethod.log index 20ba351528..db300f21b1 100644 --- a/tests/StringMethod/StringMethod.log +++ b/tests/StringMethod/StringMethod.log @@ -446,7 +446,7 @@ io_decl 11 logic_net 5 logic_var 1 method_func_call 5 -module 3 +module_inst 3 package 2 ref_obj 7 string_typespec 2 @@ -476,7 +476,7 @@ io_decl 22 logic_net 5 logic_var 1 method_func_call 6 -module 3 +module_inst 3 package 2 ref_obj 9 string_typespec 2 @@ -971,7 +971,7 @@ design: (work@top) \_int_typespec: |vpiSigned:1 |uhdmallModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/StringMethod/dut.sv, line:1:1, endln:10:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/StringMethod/dut.sv, line:1:1, endln:10:10 |vpiParent: \_design: (work@top) |vpiFullName:work@top @@ -979,37 +979,37 @@ design: (work@top) |vpiNet: \_logic_net: (work@top.s), line:2:11, endln:2:12 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/StringMethod/dut.sv, line:1:1, endln:10:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/StringMethod/dut.sv, line:1:1, endln:10:10 |vpiName:s |vpiFullName:work@top.s |vpiNet: \_logic_net: (work@top.t), line:3:11, endln:3:12 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/StringMethod/dut.sv, line:1:1, endln:10:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/StringMethod/dut.sv, line:1:1, endln:10:10 |vpiName:t |vpiFullName:work@top.t |vpiNet: \_logic_net: (work@top.a), line:7:9, endln:7:10 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/StringMethod/dut.sv, line:1:1, endln:10:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/StringMethod/dut.sv, line:1:1, endln:10:10 |vpiName:a |vpiFullName:work@top.a |vpiNet: \_logic_net: (work@top.b), line:8:9, endln:8:10 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/StringMethod/dut.sv, line:1:1, endln:10:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/StringMethod/dut.sv, line:1:1, endln:10:10 |vpiName:b |vpiFullName:work@top.b |vpiNet: \_logic_net: (work@top.c), line:9:9, endln:9:10 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/StringMethod/dut.sv, line:1:1, endln:10:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/StringMethod/dut.sv, line:1:1, endln:10:10 |vpiName:c |vpiFullName:work@top.c |vpiProcess: \_initial: , line:4:4, endln:6:7 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/StringMethod/dut.sv, line:1:1, endln:10:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/StringMethod/dut.sv, line:1:1, endln:10:10 |vpiStmt: \_begin: (work@top), line:4:12, endln:6:7 |vpiParent: @@ -1040,12 +1040,12 @@ design: (work@top) \_ref_obj: (s), line:5:7, endln:5:8 |vpiName:s |uhdmtopModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/StringMethod/dut.sv, line:1:1, endln:10:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/StringMethod/dut.sv, line:1:1, endln:10:10 |vpiName:work@top |vpiVariables: \_string_var: (work@top.s), line:2:11, endln:2:21 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/StringMethod/dut.sv, line:1:1, endln:10:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/StringMethod/dut.sv, line:1:1, endln:10:10 |vpiTypespec: \_string_typespec: , line:2:4, endln:2:10 |vpiName:s @@ -1060,7 +1060,7 @@ design: (work@top) |vpiVariables: \_string_var: (work@top.t), line:3:11, endln:3:29 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/StringMethod/dut.sv, line:1:1, endln:10:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/StringMethod/dut.sv, line:1:1, endln:10:10 |vpiTypespec: \_string_typespec: , line:3:4, endln:3:10 |vpiName:t @@ -1098,7 +1098,7 @@ design: (work@top) |vpiVariables: \_byte_var: (work@top.a), line:7:9, endln:7:22 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/StringMethod/dut.sv, line:1:1, endln:10:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/StringMethod/dut.sv, line:1:1, endln:10:10 |vpiTypespec: \_byte_typespec: , line:7:4, endln:7:8 |vpiSigned:1 @@ -1129,7 +1129,7 @@ design: (work@top) |vpiVariables: \_int_var: (work@top.b), line:8:9, endln:8:25 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/StringMethod/dut.sv, line:1:1, endln:10:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/StringMethod/dut.sv, line:1:1, endln:10:10 |vpiTypespec: \_int_typespec: , line:8:4, endln:8:7 |vpiSigned:1 @@ -1159,7 +1159,7 @@ design: (work@top) |vpiVariables: \_int_var: (work@top.c), line:9:9, endln:9:26 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/StringMethod/dut.sv, line:1:1, endln:10:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/StringMethod/dut.sv, line:1:1, endln:10:10 |vpiTypespec: \_int_typespec: , line:9:4, endln:9:7 |vpiSigned:1 @@ -1192,7 +1192,7 @@ design: (work@top) |vpiProcess: \_initial: , line:4:4, endln:6:7 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/StringMethod/dut.sv, line:1:1, endln:10:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/StringMethod/dut.sv, line:1:1, endln:10:10 |vpiStmt: \_begin: (work@top), line:4:12, endln:6:7 |vpiParent: diff --git a/tests/StringParameter/StringParameter.log b/tests/StringParameter/StringParameter.log index 077de7d3e1..f3fead3b87 100644 --- a/tests/StringParameter/StringParameter.log +++ b/tests/StringParameter/StringParameter.log @@ -29,7 +29,7 @@ === UHDM Object Stats Begin (Non-Elaborated Model) === constant 6 design 1 -module 7 +module_inst 7 param_assign 4 parameter 4 string_typespec 4 @@ -39,7 +39,7 @@ string_typespec 4 === UHDM Object Stats Begin (Elaborated Model) === constant 6 design 1 -module 7 +module_inst 7 param_assign 4 parameter 4 string_typespec 4 @@ -57,14 +57,14 @@ design: (work@top) |vpiElaborated:1 |vpiName:work@top |uhdmallModules: -\_module: work@parameter_module (work@parameter_module), file:${SURELOG_DIR}/tests/StringParameter/dut.sv, line:8:1, endln:11:10 +\_module_inst: work@parameter_module (work@parameter_module), file:${SURELOG_DIR}/tests/StringParameter/dut.sv, line:8:1, endln:11:10 |vpiParent: \_design: (work@top) |vpiFullName:work@parameter_module |vpiParameter: \_parameter: (work@parameter_module.FIRSTPARAMETER), line:9:11, endln:9:25 |vpiParent: - \_module: work@parameter_module (work@parameter_module), file:${SURELOG_DIR}/tests/StringParameter/dut.sv, line:8:1, endln:11:10 + \_module_inst: work@parameter_module (work@parameter_module), file:${SURELOG_DIR}/tests/StringParameter/dut.sv, line:8:1, endln:11:10 |STRING:FIRSTVALUE |vpiTypespec: \_string_typespec: @@ -73,7 +73,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@parameter_module.SECONDPARAMETER), line:10:11, endln:10:26 |vpiParent: - \_module: work@parameter_module (work@parameter_module), file:${SURELOG_DIR}/tests/StringParameter/dut.sv, line:8:1, endln:11:10 + \_module_inst: work@parameter_module (work@parameter_module), file:${SURELOG_DIR}/tests/StringParameter/dut.sv, line:8:1, endln:11:10 |STRING:SECONDVALUE |vpiTypespec: \_string_typespec: @@ -82,7 +82,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:9:11, endln:9:40 |vpiParent: - \_module: work@parameter_module (work@parameter_module), file:${SURELOG_DIR}/tests/StringParameter/dut.sv, line:8:1, endln:11:10 + \_module_inst: work@parameter_module (work@parameter_module), file:${SURELOG_DIR}/tests/StringParameter/dut.sv, line:8:1, endln:11:10 |vpiRhs: \_constant: , line:9:28, endln:9:40 |vpiDecompile:FIRSTVALUE @@ -96,7 +96,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:10:11, endln:10:42 |vpiParent: - \_module: work@parameter_module (work@parameter_module), file:${SURELOG_DIR}/tests/StringParameter/dut.sv, line:8:1, endln:11:10 + \_module_inst: work@parameter_module (work@parameter_module), file:${SURELOG_DIR}/tests/StringParameter/dut.sv, line:8:1, endln:11:10 |vpiRhs: \_constant: , line:10:29, endln:10:42 |vpiDecompile:SECONDVALUE @@ -109,27 +109,27 @@ design: (work@top) \_parameter: (work@parameter_module.SECONDPARAMETER), line:10:11, endln:10:26 |vpiDefName:work@parameter_module |uhdmallModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/StringParameter/dut.sv, line:1:1, endln:6:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/StringParameter/dut.sv, line:1:1, endln:6:10 |vpiParent: \_design: (work@top) |vpiFullName:work@top |vpiDefName:work@top |uhdmtopModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/StringParameter/dut.sv, line:1:1, endln:6:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/StringParameter/dut.sv, line:1:1, endln:6:10 |vpiName:work@top |vpiDefName:work@top |vpiTop:1 |vpiTopModule:1 - |vpiModule: - \_module: work@parameter_module (work@top.test_module), file:${SURELOG_DIR}/tests/StringParameter/dut.sv, line:2:9, endln:5:26 + |vpiModuleInst: + \_module_inst: work@parameter_module (work@top.test_module), file:${SURELOG_DIR}/tests/StringParameter/dut.sv, line:2:9, endln:5:26 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/StringParameter/dut.sv, line:1:1, endln:6:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/StringParameter/dut.sv, line:1:1, endln:6:10 |vpiName:test_module |vpiFullName:work@top.test_module |vpiParameter: \_parameter: (work@top.test_module.FIRSTPARAMETER), line:9:11, endln:9:25 |vpiParent: - \_module: work@parameter_module (work@top.test_module), file:${SURELOG_DIR}/tests/StringParameter/dut.sv, line:2:9, endln:5:26 + \_module_inst: work@parameter_module (work@top.test_module), file:${SURELOG_DIR}/tests/StringParameter/dut.sv, line:2:9, endln:5:26 |STRING:FIRSTVALUE |vpiTypespec: \_string_typespec: @@ -140,7 +140,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.test_module.SECONDPARAMETER), line:10:11, endln:10:26 |vpiParent: - \_module: work@parameter_module (work@top.test_module), file:${SURELOG_DIR}/tests/StringParameter/dut.sv, line:2:9, endln:5:26 + \_module_inst: work@parameter_module (work@top.test_module), file:${SURELOG_DIR}/tests/StringParameter/dut.sv, line:2:9, endln:5:26 |STRING:SECONDVALUE |vpiTypespec: \_string_typespec: @@ -151,7 +151,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:9:11, endln:9:40 |vpiParent: - \_module: work@parameter_module (work@top.test_module), file:${SURELOG_DIR}/tests/StringParameter/dut.sv, line:2:9, endln:5:26 + \_module_inst: work@parameter_module (work@top.test_module), file:${SURELOG_DIR}/tests/StringParameter/dut.sv, line:2:9, endln:5:26 |vpiOverriden:1 |vpiRhs: \_constant: , line:9:28, endln:9:40 @@ -166,7 +166,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:10:11, endln:10:42 |vpiParent: - \_module: work@parameter_module (work@top.test_module), file:${SURELOG_DIR}/tests/StringParameter/dut.sv, line:2:9, endln:5:26 + \_module_inst: work@parameter_module (work@top.test_module), file:${SURELOG_DIR}/tests/StringParameter/dut.sv, line:2:9, endln:5:26 |vpiOverriden:1 |vpiRhs: \_constant: , line:10:29, endln:10:42 @@ -182,7 +182,7 @@ design: (work@top) |vpiDefFile:${SURELOG_DIR}/tests/StringParameter/dut.sv |vpiDefLineNo:8 |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/StringParameter/dut.sv, line:1:1, endln:6:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/StringParameter/dut.sv, line:1:1, endln:6:10 =================== [ FATAL] : 0 [ SYNTAX] : 0 diff --git a/tests/StringPort/StringPort.log b/tests/StringPort/StringPort.log index 4b61ff21a6..f509a61249 100644 --- a/tests/StringPort/StringPort.log +++ b/tests/StringPort/StringPort.log @@ -340,7 +340,7 @@ int_var 4 io_decl 11 logic_net 1 logic_var 1 -module 2 +module_inst 2 package 2 port 2 ref_obj 3 @@ -368,7 +368,7 @@ int_var 4 io_decl 22 logic_net 1 logic_var 1 -module 2 +module_inst 2 package 2 port 3 ref_obj 5 @@ -864,7 +864,7 @@ design: (work@top) \_int_typespec: |vpiSigned:1 |uhdmallModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/StringPort/dut.sv, line:1:1, endln:6:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/StringPort/dut.sv, line:1:1, endln:6:10 |vpiParent: \_design: (work@top) |vpiFullName:work@top @@ -872,13 +872,13 @@ design: (work@top) |vpiNet: \_logic_net: (work@top.o), line:1:26, endln:1:27 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/StringPort/dut.sv, line:1:1, endln:6:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/StringPort/dut.sv, line:1:1, endln:6:10 |vpiName:o |vpiFullName:work@top.o |vpiPort: \_port: (o), line:1:26, endln:1:27 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/StringPort/dut.sv, line:1:1, endln:6:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/StringPort/dut.sv, line:1:1, endln:6:10 |vpiName:o |vpiDirection:2 |vpiLowConn: @@ -890,7 +890,7 @@ design: (work@top) |vpiProcess: \_initial: , line:3:4, endln:5:7 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/StringPort/dut.sv, line:1:1, endln:6:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/StringPort/dut.sv, line:1:1, endln:6:10 |vpiStmt: \_begin: (work@top), line:3:12, endln:5:7 |vpiParent: @@ -919,12 +919,12 @@ design: (work@top) |vpiActual: \_string_var: (work@top.o), line:1:26, endln:1:27 |uhdmtopModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/StringPort/dut.sv, line:1:1, endln:6:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/StringPort/dut.sv, line:1:1, endln:6:10 |vpiName:work@top |vpiVariables: \_string_var: (work@top.o), line:1:26, endln:1:27 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/StringPort/dut.sv, line:1:1, endln:6:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/StringPort/dut.sv, line:1:1, endln:6:10 |vpiTypespec: \_string_typespec: , line:1:19, endln:1:25 |vpiName:o @@ -936,7 +936,7 @@ design: (work@top) |vpiPort: \_port: (o), line:1:26, endln:1:27 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/StringPort/dut.sv, line:1:1, endln:6:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/StringPort/dut.sv, line:1:1, endln:6:10 |vpiName:o |vpiDirection:2 |vpiLowConn: @@ -950,11 +950,11 @@ design: (work@top) |vpiTypedef: \_string_typespec: , line:1:19, endln:1:25 |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/StringPort/dut.sv, line:1:1, endln:6:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/StringPort/dut.sv, line:1:1, endln:6:10 |vpiProcess: \_initial: , line:3:4, endln:5:7 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/StringPort/dut.sv, line:1:1, endln:6:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/StringPort/dut.sv, line:1:1, endln:6:10 |vpiStmt: \_begin: (work@top), line:3:12, endln:5:7 |vpiParent: diff --git a/tests/StringRange/StringRange.log b/tests/StringRange/StringRange.log index 4a6ce928d7..0a7ef1729d 100644 --- a/tests/StringRange/StringRange.log +++ b/tests/StringRange/StringRange.log @@ -2098,7 +2098,7 @@ io_decl 2 logic_net 56 logic_typespec 38 logic_var 2 -module 1223 +module_inst 1223 operation 917 param_assign 2419 parameter 2707 @@ -2135,7 +2135,7 @@ io_decl 7 logic_net 56 logic_typespec 38 logic_var 2 -module 1223 +module_inst 1223 operation 958 param_assign 2419 parameter 2707 @@ -2160,14 +2160,14 @@ design: (work@top) |vpiElaborated:1 |vpiName:work@top |uhdmallModules: -\_module: work@Example (work@Example), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:1:1, endln:37:10 +\_module_inst: work@Example (work@Example), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:1:1, endln:37:10 |vpiParent: \_design: (work@top) |vpiFullName:work@Example |vpiParameter: \_parameter: (work@Example.OUTPUT), line:2:15, endln:2:21 |vpiParent: - \_module: work@Example (work@Example), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:1:1, endln:37:10 + \_module_inst: work@Example (work@Example), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:1:1, endln:37:10 |STRING:FOO |vpiTypespec: \_string_typespec: @@ -2176,7 +2176,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:2:15, endln:2:29 |vpiParent: - \_module: work@Example (work@Example), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:1:1, endln:37:10 + \_module_inst: work@Example (work@Example), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:1:1, endln:37:10 |vpiRhs: \_constant: , line:2:24, endln:2:29 |vpiDecompile:FOO @@ -2191,7 +2191,7 @@ design: (work@top) |vpiTaskFunc: \_function: (work@Example.flip), line:6:5, endln:9:16 |vpiParent: - \_module: work@Example (work@Example), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:1:1, endln:37:10 + \_module_inst: work@Example (work@Example), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:1:1, endln:37:10 |vpiName:flip |vpiFullName:work@Example.flip |vpiVisibility:1 @@ -2219,7 +2219,7 @@ design: (work@top) |UINT:0 |vpiConstType:9 |vpiParent: - \_module: work@Example (work@Example), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:1:1, endln:37:10 + \_module_inst: work@Example (work@Example), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:1:1, endln:37:10 |vpiIODecl: \_io_decl: (inp), line:7:22, endln:7:25 |vpiParent: @@ -2276,45 +2276,45 @@ design: (work@top) |vpiActual: \_logic_var: (flip), line:6:24, endln:6:30 |vpiInstance: - \_module: work@Example (work@Example), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:1:1, endln:37:10 + \_module_inst: work@Example (work@Example), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:1:1, endln:37:10 |vpiNet: \_logic_net: (work@Example.j), line:30:13, endln:30:14 |vpiParent: - \_module: work@Example (work@Example), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:1:1, endln:37:10 + \_module_inst: work@Example (work@Example), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:1:1, endln:37:10 |vpiName:j |vpiFullName:work@Example.j |vpiNet: \_logic_net: (work@Example.outA), line:1:16, endln:1:20 |vpiParent: - \_module: work@Example (work@Example), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:1:1, endln:37:10 + \_module_inst: work@Example (work@Example), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:1:1, endln:37:10 |vpiName:outA |vpiFullName:work@Example.outA |vpiNetType:1 |vpiNet: \_logic_net: (work@Example.outB), line:1:22, endln:1:26 |vpiParent: - \_module: work@Example (work@Example), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:1:1, endln:37:10 + \_module_inst: work@Example (work@Example), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:1:1, endln:37:10 |vpiName:outB |vpiFullName:work@Example.outB |vpiNetType:1 |vpiNet: \_logic_net: (work@Example.outC), line:1:28, endln:1:32 |vpiParent: - \_module: work@Example (work@Example), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:1:1, endln:37:10 + \_module_inst: work@Example (work@Example), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:1:1, endln:37:10 |vpiName:outC |vpiFullName:work@Example.outC |vpiNetType:48 |vpiNet: \_logic_net: (work@Example.outD), line:1:34, endln:1:38 |vpiParent: - \_module: work@Example (work@Example), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:1:1, endln:37:10 + \_module_inst: work@Example (work@Example), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:1:1, endln:37:10 |vpiName:outD |vpiFullName:work@Example.outD |vpiNetType:48 |vpiPort: \_port: (outA), line:1:16, endln:1:20 |vpiParent: - \_module: work@Example (work@Example), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:1:1, endln:37:10 + \_module_inst: work@Example (work@Example), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:1:1, endln:37:10 |vpiName:outA |vpiDirection:2 |vpiLowConn: @@ -2344,7 +2344,7 @@ design: (work@top) |vpiPort: \_port: (outB), line:1:22, endln:1:26 |vpiParent: - \_module: work@Example (work@Example), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:1:1, endln:37:10 + \_module_inst: work@Example (work@Example), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:1:1, endln:37:10 |vpiName:outB |vpiDirection:2 |vpiLowConn: @@ -2374,7 +2374,7 @@ design: (work@top) |vpiPort: \_port: (outC), line:1:28, endln:1:32 |vpiParent: - \_module: work@Example (work@Example), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:1:1, endln:37:10 + \_module_inst: work@Example (work@Example), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:1:1, endln:37:10 |vpiName:outC |vpiDirection:2 |vpiLowConn: @@ -2386,7 +2386,7 @@ design: (work@top) |vpiPort: \_port: (outD), line:1:34, endln:1:38 |vpiParent: - \_module: work@Example (work@Example), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:1:1, endln:37:10 + \_module_inst: work@Example (work@Example), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:1:1, endln:37:10 |vpiName:outD |vpiDirection:2 |vpiLowConn: @@ -2398,7 +2398,7 @@ design: (work@top) |vpiProcess: \_initial: , line:31:5, endln:36:8 |vpiParent: - \_module: work@Example (work@Example), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:1:1, endln:37:10 + \_module_inst: work@Example (work@Example), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:1:1, endln:37:10 |vpiStmt: \_begin: (work@Example), line:31:13, endln:36:8 |vpiParent: @@ -2607,7 +2607,7 @@ design: (work@top) |vpiProcess: \_initial: , line:24:9, endln:24:26 |vpiParent: - \_module: work@Example (work@Example), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:1:1, endln:37:10 + \_module_inst: work@Example (work@Example), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:1:1, endln:37:10 |vpiStmt: \_assignment: , line:24:17, endln:24:25 |vpiParent: @@ -2633,7 +2633,7 @@ design: (work@top) |vpiProcess: \_initial: , line:24:9, endln:24:26 |vpiParent: - \_module: work@Example (work@Example), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:1:1, endln:37:10 + \_module_inst: work@Example (work@Example), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:1:1, endln:37:10 |vpiStmt: \_assignment: , line:24:17, endln:24:25 |vpiParent: @@ -2659,7 +2659,7 @@ design: (work@top) |vpiProcess: \_initial: , line:24:9, endln:24:26 |vpiParent: - \_module: work@Example (work@Example), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:1:1, endln:37:10 + \_module_inst: work@Example (work@Example), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:1:1, endln:37:10 |vpiStmt: \_assignment: , line:24:17, endln:24:25 |vpiParent: @@ -2685,7 +2685,7 @@ design: (work@top) |vpiProcess: \_initial: , line:24:9, endln:24:26 |vpiParent: - \_module: work@Example (work@Example), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:1:1, endln:37:10 + \_module_inst: work@Example (work@Example), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:1:1, endln:37:10 |vpiStmt: \_assignment: , line:24:17, endln:24:25 |vpiParent: @@ -2709,14 +2709,14 @@ design: (work@top) |vpiActual: \_logic_net: (work@top.e1.outC), line:1:28, endln:1:32 |uhdmallModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:39:1, endln:86:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:39:1, endln:86:10 |vpiParent: \_design: (work@top) |vpiFullName:work@top |vpiParameter: \_parameter: (work@top.W), line:60:15, endln:60:16 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:39:1, endln:86:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:39:1, endln:86:10 |UINT:10 |vpiTypespec: \_int_typespec: @@ -2725,7 +2725,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.X), line:61:15, endln:61:16 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:39:1, endln:86:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:39:1, endln:86:10 |UINT:3 |vpiTypespec: \_int_typespec: @@ -2734,7 +2734,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.Y), line:62:23, endln:62:24 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:39:1, endln:86:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:39:1, endln:86:10 |vpiTypespec: \_int_typespec: , line:62:16, endln:62:22 |vpiParent: @@ -2746,7 +2746,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.Z), line:63:23, endln:63:24 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:39:1, endln:86:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:39:1, endln:86:10 |vpiTypespec: \_int_typespec: , line:63:16, endln:63:22 |vpiParent: @@ -2758,7 +2758,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:60:15, endln:60:21 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:39:1, endln:86:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:39:1, endln:86:10 |vpiRhs: \_constant: , line:60:19, endln:60:21 |vpiDecompile:10 @@ -2772,7 +2772,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:61:15, endln:61:20 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:39:1, endln:86:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:39:1, endln:86:10 |vpiRhs: \_constant: , line:61:19, endln:61:20 |vpiDecompile:3 @@ -2786,7 +2786,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:62:23, endln:62:40 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:39:1, endln:86:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:39:1, endln:86:10 |vpiRhs: \_sys_func_call: ($floor), line:62:27, endln:62:40 |vpiArgument: @@ -2810,7 +2810,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:63:23, endln:63:48 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:39:1, endln:86:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:39:1, endln:86:10 |vpiRhs: \_func_call: (negate), line:63:27, endln:63:33 |vpiArgument: @@ -2842,12 +2842,12 @@ design: (work@top) |vpiTaskFunc: \_function: (work@top.negate), line:56:5, endln:59:16 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:39:1, endln:86:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:39:1, endln:86:10 |vpiName:negate |vpiFullName:work@top.negate |vpiVisibility:1 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:39:1, endln:86:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:39:1, endln:86:10 |vpiIODecl: \_io_decl: (inp), line:57:23, endln:57:26 |vpiParent: @@ -2885,130 +2885,130 @@ design: (work@top) |vpiActual: \_logic_net: (negate) |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:39:1, endln:86:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:39:1, endln:86:10 |vpiNet: \_logic_net: (work@top.a1), line:40:17, endln:40:19 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:39:1, endln:86:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:39:1, endln:86:10 |vpiName:a1 |vpiFullName:work@top.a1 |vpiNetType:1 |vpiNet: \_logic_net: (work@top.a2), line:40:21, endln:40:23 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:39:1, endln:86:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:39:1, endln:86:10 |vpiName:a2 |vpiFullName:work@top.a2 |vpiNetType:1 |vpiNet: \_logic_net: (work@top.a3), line:40:25, endln:40:27 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:39:1, endln:86:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:39:1, endln:86:10 |vpiName:a3 |vpiFullName:work@top.a3 |vpiNetType:1 |vpiNet: \_logic_net: (work@top.a4), line:40:29, endln:40:31 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:39:1, endln:86:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:39:1, endln:86:10 |vpiName:a4 |vpiFullName:work@top.a4 |vpiNetType:1 |vpiNet: \_logic_net: (work@top.b1), line:41:17, endln:41:19 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:39:1, endln:86:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:39:1, endln:86:10 |vpiName:b1 |vpiFullName:work@top.b1 |vpiNetType:1 |vpiNet: \_logic_net: (work@top.b2), line:41:21, endln:41:23 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:39:1, endln:86:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:39:1, endln:86:10 |vpiName:b2 |vpiFullName:work@top.b2 |vpiNetType:1 |vpiNet: \_logic_net: (work@top.b3), line:41:25, endln:41:27 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:39:1, endln:86:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:39:1, endln:86:10 |vpiName:b3 |vpiFullName:work@top.b3 |vpiNetType:1 |vpiNet: \_logic_net: (work@top.b4), line:41:29, endln:41:31 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:39:1, endln:86:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:39:1, endln:86:10 |vpiName:b4 |vpiFullName:work@top.b4 |vpiNetType:1 |vpiNet: \_logic_net: (work@top.c1), line:42:17, endln:42:19 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:39:1, endln:86:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:39:1, endln:86:10 |vpiName:c1 |vpiFullName:work@top.c1 |vpiNetType:1 |vpiNet: \_logic_net: (work@top.c2), line:42:21, endln:42:23 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:39:1, endln:86:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:39:1, endln:86:10 |vpiName:c2 |vpiFullName:work@top.c2 |vpiNetType:1 |vpiNet: \_logic_net: (work@top.c3), line:42:25, endln:42:27 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:39:1, endln:86:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:39:1, endln:86:10 |vpiName:c3 |vpiFullName:work@top.c3 |vpiNetType:1 |vpiNet: \_logic_net: (work@top.c4), line:42:29, endln:42:31 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:39:1, endln:86:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:39:1, endln:86:10 |vpiName:c4 |vpiFullName:work@top.c4 |vpiNetType:1 |vpiNet: \_logic_net: (work@top.d1), line:43:17, endln:43:19 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:39:1, endln:86:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:39:1, endln:86:10 |vpiName:d1 |vpiFullName:work@top.d1 |vpiNetType:1 |vpiNet: \_logic_net: (work@top.d2), line:43:21, endln:43:23 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:39:1, endln:86:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:39:1, endln:86:10 |vpiName:d2 |vpiFullName:work@top.d2 |vpiNetType:1 |vpiNet: \_logic_net: (work@top.d3), line:43:25, endln:43:27 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:39:1, endln:86:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:39:1, endln:86:10 |vpiName:d3 |vpiFullName:work@top.d3 |vpiNetType:1 |vpiNet: \_logic_net: (work@top.d4), line:43:29, endln:43:31 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:39:1, endln:86:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:39:1, endln:86:10 |vpiName:d4 |vpiFullName:work@top.d4 |vpiNetType:1 |vpiNet: \_logic_net: (work@top.out), line:39:12, endln:39:15 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:39:1, endln:86:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:39:1, endln:86:10 |vpiName:out |vpiFullName:work@top.out |vpiNetType:1 |vpiPort: \_port: (out), line:39:12, endln:39:15 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:39:1, endln:86:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:39:1, endln:86:10 |vpiName:out |vpiDirection:2 |vpiLowConn: @@ -3077,7 +3077,7 @@ design: (work@top) |vpiProcess: \_always: , line:65:5, endln:85:8 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:39:1, endln:86:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:39:1, endln:86:10 |vpiStmt: \_begin: (work@top), line:65:17, endln:85:8 |vpiParent: @@ -3536,7 +3536,7 @@ design: (work@top) |vpiContAssign: \_cont_assign: , line:50:12, endln:54:24 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:39:1, endln:86:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:39:1, endln:86:10 |vpiRhs: \_operation: , line:50:18, endln:54:24 |vpiParent: @@ -3679,12 +3679,12 @@ design: (work@top) |vpiActual: \_logic_net: (work@top.out), line:39:12, endln:39:15 |uhdmtopModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:39:1, endln:86:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:39:1, endln:86:10 |vpiName:work@top |vpiParameter: \_parameter: (work@top.W), line:60:15, endln:60:16 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:39:1, endln:86:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:39:1, endln:86:10 |UINT:10 |vpiTypespec: \_int_typespec: @@ -3695,7 +3695,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.X), line:61:15, endln:61:16 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:39:1, endln:86:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:39:1, endln:86:10 |UINT:3 |vpiTypespec: \_int_typespec: @@ -3706,7 +3706,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.Y), line:62:23, endln:62:24 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:39:1, endln:86:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:39:1, endln:86:10 |vpiTypespec: \_int_typespec: , line:62:16, endln:62:22 |vpiParent: @@ -3718,7 +3718,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.Z), line:63:23, endln:63:24 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:39:1, endln:86:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:39:1, endln:86:10 |vpiTypespec: \_int_typespec: , line:63:16, endln:63:22 |vpiParent: @@ -3730,7 +3730,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:60:15, endln:60:21 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:39:1, endln:86:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:39:1, endln:86:10 |vpiRhs: \_constant: , line:60:19, endln:60:21 |vpiDecompile:10 @@ -3744,7 +3744,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:61:15, endln:61:20 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:39:1, endln:86:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:39:1, endln:86:10 |vpiRhs: \_constant: , line:61:19, endln:61:20 |vpiDecompile:3 @@ -3758,7 +3758,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:62:23, endln:62:40 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:39:1, endln:86:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:39:1, endln:86:10 |vpiRhs: \_sys_func_call: ($floor), line:62:27, endln:62:40 |vpiArgument: @@ -3775,7 +3775,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:63:23, endln:63:48 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:39:1, endln:86:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:39:1, endln:86:10 |vpiRhs: \_func_call: (negate), line:63:27, endln:63:33 |vpiArgument: @@ -3803,12 +3803,12 @@ design: (work@top) |vpiTaskFunc: \_function: (work@top.negate), line:56:5, endln:59:16 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:39:1, endln:86:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:39:1, endln:86:10 |vpiName:negate |vpiFullName:work@top.negate |vpiVisibility:1 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:39:1, endln:86:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:39:1, endln:86:10 |vpiIODecl: \_io_decl: (inp), line:57:23, endln:57:26 |vpiParent: @@ -3845,11 +3845,11 @@ design: (work@top) |vpiActual: \_logic_net: (negate) |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:39:1, endln:86:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:39:1, endln:86:10 |vpiNet: \_logic_net: (work@top.a1), line:40:17, endln:40:19 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:39:1, endln:86:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:39:1, endln:86:10 |vpiTypespec: \_logic_typespec: , line:40:5, endln:40:16 |vpiRange: @@ -3876,7 +3876,7 @@ design: (work@top) |vpiNet: \_logic_net: (work@top.a2), line:40:21, endln:40:23 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:39:1, endln:86:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:39:1, endln:86:10 |vpiTypespec: \_logic_typespec: , line:40:5, endln:40:16 |vpiName:a2 @@ -3885,7 +3885,7 @@ design: (work@top) |vpiNet: \_logic_net: (work@top.a3), line:40:25, endln:40:27 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:39:1, endln:86:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:39:1, endln:86:10 |vpiTypespec: \_logic_typespec: , line:40:5, endln:40:16 |vpiName:a3 @@ -3894,7 +3894,7 @@ design: (work@top) |vpiNet: \_logic_net: (work@top.a4), line:40:29, endln:40:31 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:39:1, endln:86:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:39:1, endln:86:10 |vpiTypespec: \_logic_typespec: , line:40:5, endln:40:16 |vpiName:a4 @@ -3903,7 +3903,7 @@ design: (work@top) |vpiNet: \_logic_net: (work@top.b1), line:41:17, endln:41:19 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:39:1, endln:86:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:39:1, endln:86:10 |vpiTypespec: \_logic_typespec: , line:41:5, endln:41:16 |vpiRange: @@ -3930,7 +3930,7 @@ design: (work@top) |vpiNet: \_logic_net: (work@top.b2), line:41:21, endln:41:23 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:39:1, endln:86:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:39:1, endln:86:10 |vpiTypespec: \_logic_typespec: , line:41:5, endln:41:16 |vpiName:b2 @@ -3939,7 +3939,7 @@ design: (work@top) |vpiNet: \_logic_net: (work@top.b3), line:41:25, endln:41:27 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:39:1, endln:86:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:39:1, endln:86:10 |vpiTypespec: \_logic_typespec: , line:41:5, endln:41:16 |vpiName:b3 @@ -3948,7 +3948,7 @@ design: (work@top) |vpiNet: \_logic_net: (work@top.b4), line:41:29, endln:41:31 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:39:1, endln:86:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:39:1, endln:86:10 |vpiTypespec: \_logic_typespec: , line:41:5, endln:41:16 |vpiName:b4 @@ -3957,7 +3957,7 @@ design: (work@top) |vpiNet: \_logic_net: (work@top.c1), line:42:17, endln:42:19 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:39:1, endln:86:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:39:1, endln:86:10 |vpiTypespec: \_logic_typespec: , line:42:5, endln:42:9 |vpiName:c1 @@ -3966,7 +3966,7 @@ design: (work@top) |vpiNet: \_logic_net: (work@top.c2), line:42:21, endln:42:23 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:39:1, endln:86:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:39:1, endln:86:10 |vpiTypespec: \_logic_typespec: , line:42:5, endln:42:9 |vpiName:c2 @@ -3975,7 +3975,7 @@ design: (work@top) |vpiNet: \_logic_net: (work@top.c3), line:42:25, endln:42:27 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:39:1, endln:86:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:39:1, endln:86:10 |vpiTypespec: \_logic_typespec: , line:42:5, endln:42:9 |vpiName:c3 @@ -3984,7 +3984,7 @@ design: (work@top) |vpiNet: \_logic_net: (work@top.c4), line:42:29, endln:42:31 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:39:1, endln:86:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:39:1, endln:86:10 |vpiTypespec: \_logic_typespec: , line:42:5, endln:42:9 |vpiName:c4 @@ -3993,7 +3993,7 @@ design: (work@top) |vpiNet: \_logic_net: (work@top.d1), line:43:17, endln:43:19 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:39:1, endln:86:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:39:1, endln:86:10 |vpiTypespec: \_logic_typespec: , line:43:5, endln:43:9 |vpiName:d1 @@ -4002,7 +4002,7 @@ design: (work@top) |vpiNet: \_logic_net: (work@top.d2), line:43:21, endln:43:23 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:39:1, endln:86:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:39:1, endln:86:10 |vpiTypespec: \_logic_typespec: , line:43:5, endln:43:9 |vpiName:d2 @@ -4011,7 +4011,7 @@ design: (work@top) |vpiNet: \_logic_net: (work@top.d3), line:43:25, endln:43:27 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:39:1, endln:86:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:39:1, endln:86:10 |vpiTypespec: \_logic_typespec: , line:43:5, endln:43:9 |vpiName:d3 @@ -4020,7 +4020,7 @@ design: (work@top) |vpiNet: \_logic_net: (work@top.d4), line:43:29, endln:43:31 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:39:1, endln:86:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:39:1, endln:86:10 |vpiTypespec: \_logic_typespec: , line:43:5, endln:43:9 |vpiName:d4 @@ -4029,7 +4029,7 @@ design: (work@top) |vpiNet: \_logic_net: (work@top.out), line:39:12, endln:39:15 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:39:1, endln:86:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:39:1, endln:86:10 |vpiTypespec: \_logic_typespec: , line:49:12, endln:49:36 |vpiRange: @@ -4061,7 +4061,7 @@ design: (work@top) |vpiPort: \_port: (out), line:39:12, endln:39:15 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:39:1, endln:86:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:39:1, endln:86:10 |vpiName:out |vpiDirection:2 |vpiLowConn: @@ -4095,11 +4095,11 @@ design: (work@top) |UINT:0 |vpiConstType:9 |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:39:1, endln:86:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:39:1, endln:86:10 |vpiProcess: \_always: , line:65:5, endln:85:8 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:39:1, endln:86:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:39:1, endln:86:10 |vpiStmt: \_begin: (work@top), line:65:17, endln:85:8 |vpiParent: @@ -4453,16 +4453,16 @@ design: (work@top) |vpiOperand: \_constant: , line:84:22, endln:84:23 |vpiAlwaysType:2 - |vpiModule: - \_module: work@Example (work@top.e1), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:44:5, endln:44:41 + |vpiModuleInst: + \_module_inst: work@Example (work@top.e1), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:44:5, endln:44:41 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:39:1, endln:86:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:39:1, endln:86:10 |vpiName:e1 |vpiFullName:work@top.e1 |vpiVariables: \_integer_var: (work@top.e1.j), line:30:13, endln:30:14 |vpiParent: - \_module: work@Example (work@top.e1), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:44:5, endln:44:41 + \_module_inst: work@Example (work@top.e1), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:44:5, endln:44:41 |vpiTypespec: \_integer_typespec: , line:30:5, endln:30:12 |vpiSigned:1 @@ -4472,7 +4472,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.e1.OUTPUT), line:2:15, endln:2:21 |vpiParent: - \_module: work@Example (work@top.e1), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:44:5, endln:44:41 + \_module_inst: work@Example (work@top.e1), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:44:5, endln:44:41 |STRING:FOO |vpiTypespec: \_string_typespec: @@ -4483,7 +4483,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:2:15, endln:2:29 |vpiParent: - \_module: work@Example (work@top.e1), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:44:5, endln:44:41 + \_module_inst: work@Example (work@top.e1), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:44:5, endln:44:41 |vpiRhs: \_constant: , line:2:24, endln:2:29 |vpiDecompile:FOO @@ -4500,7 +4500,7 @@ design: (work@top) |vpiTaskFunc: \_function: (work@top.e1.flip), line:6:5, endln:9:16 |vpiParent: - \_module: work@Example (work@top.e1), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:44:5, endln:44:41 + \_module_inst: work@Example (work@top.e1), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:44:5, endln:44:41 |vpiName:flip |vpiFullName:work@top.e1.flip |vpiVisibility:1 @@ -4508,7 +4508,7 @@ design: (work@top) |vpiReturn: \_logic_var: , line:6:24, endln:6:30 |vpiParent: - \_module: work@Example (work@top.e1), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:44:5, endln:44:41 + \_module_inst: work@Example (work@top.e1), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:44:5, endln:44:41 |vpiIODecl: \_io_decl: (inp), line:7:22, endln:7:25 |vpiParent: @@ -4545,11 +4545,11 @@ design: (work@top) |vpiActual: \_logic_var: , line:6:24, endln:6:30 |vpiInstance: - \_module: work@Example (work@top.e1), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:44:5, endln:44:41 + \_module_inst: work@Example (work@top.e1), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:44:5, endln:44:41 |vpiNet: \_logic_net: (work@top.e1.outA), line:1:16, endln:1:20 |vpiParent: - \_module: work@Example (work@top.e1), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:44:5, endln:44:41 + \_module_inst: work@Example (work@top.e1), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:44:5, endln:44:41 |vpiTypespec: \_logic_typespec: , line:3:12, endln:3:23 |vpiRange: @@ -4576,7 +4576,7 @@ design: (work@top) |vpiNet: \_logic_net: (work@top.e1.outB), line:1:22, endln:1:26 |vpiParent: - \_module: work@Example (work@top.e1), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:44:5, endln:44:41 + \_module_inst: work@Example (work@top.e1), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:44:5, endln:44:41 |vpiTypespec: \_logic_typespec: , line:4:12, endln:4:23 |vpiRange: @@ -4603,7 +4603,7 @@ design: (work@top) |vpiNet: \_logic_net: (work@top.e1.outC), line:1:28, endln:1:32 |vpiParent: - \_module: work@Example (work@top.e1), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:44:5, endln:44:41 + \_module_inst: work@Example (work@top.e1), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:44:5, endln:44:41 |vpiTypespec: \_logic_typespec: , line:5:12, endln:5:15 |vpiName:outC @@ -4612,18 +4612,18 @@ design: (work@top) |vpiNet: \_logic_net: (work@top.e1.outD), line:1:34, endln:1:38 |vpiParent: - \_module: work@Example (work@top.e1), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:44:5, endln:44:41 + \_module_inst: work@Example (work@top.e1), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:44:5, endln:44:41 |vpiTypespec: \_logic_typespec: , line:5:12, endln:5:15 |vpiName:outD |vpiFullName:work@top.e1.outD |vpiNetType:48 |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:39:1, endln:86:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:39:1, endln:86:10 |vpiPort: \_port: (outA), line:1:16, endln:1:20 |vpiParent: - \_module: work@Example (work@top.e1), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:44:5, endln:44:41 + \_module_inst: work@Example (work@top.e1), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:44:5, endln:44:41 |vpiName:outA |vpiDirection:2 |vpiHighConn: @@ -4665,11 +4665,11 @@ design: (work@top) |UINT:0 |vpiConstType:9 |vpiInstance: - \_module: work@Example (work@top.e1), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:44:5, endln:44:41 + \_module_inst: work@Example (work@top.e1), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:44:5, endln:44:41 |vpiPort: \_port: (outB), line:1:22, endln:1:26 |vpiParent: - \_module: work@Example (work@top.e1), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:44:5, endln:44:41 + \_module_inst: work@Example (work@top.e1), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:44:5, endln:44:41 |vpiName:outB |vpiDirection:2 |vpiHighConn: @@ -4711,11 +4711,11 @@ design: (work@top) |UINT:0 |vpiConstType:9 |vpiInstance: - \_module: work@Example (work@top.e1), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:44:5, endln:44:41 + \_module_inst: work@Example (work@top.e1), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:44:5, endln:44:41 |vpiPort: \_port: (outC), line:1:28, endln:1:32 |vpiParent: - \_module: work@Example (work@top.e1), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:44:5, endln:44:41 + \_module_inst: work@Example (work@top.e1), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:44:5, endln:44:41 |vpiName:outC |vpiDirection:2 |vpiHighConn: @@ -4737,11 +4737,11 @@ design: (work@top) |vpiTypedef: \_logic_typespec: , line:5:12, endln:5:15 |vpiInstance: - \_module: work@Example (work@top.e1), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:44:5, endln:44:41 + \_module_inst: work@Example (work@top.e1), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:44:5, endln:44:41 |vpiPort: \_port: (outD), line:1:34, endln:1:38 |vpiParent: - \_module: work@Example (work@top.e1), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:44:5, endln:44:41 + \_module_inst: work@Example (work@top.e1), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:44:5, endln:44:41 |vpiName:outD |vpiDirection:2 |vpiHighConn: @@ -4763,11 +4763,11 @@ design: (work@top) |vpiTypedef: \_logic_typespec: , line:5:12, endln:5:15 |vpiInstance: - \_module: work@Example (work@top.e1), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:44:5, endln:44:41 + \_module_inst: work@Example (work@top.e1), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:44:5, endln:44:41 |vpiProcess: \_initial: , line:31:5, endln:36:8 |vpiParent: - \_module: work@Example (work@top.e1), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:44:5, endln:44:41 + \_module_inst: work@Example (work@top.e1), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:44:5, endln:44:41 |vpiStmt: \_begin: (work@top.e1), line:31:13, endln:36:8 |vpiParent: @@ -4939,7 +4939,7 @@ design: (work@top) |vpiProcess: \_initial: , line:24:9, endln:24:26 |vpiParent: - \_module: work@Example (work@top.e1), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:44:5, endln:44:41 + \_module_inst: work@Example (work@top.e1), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:44:5, endln:44:41 |vpiStmt: \_assignment: , line:24:17, endln:24:25 |vpiParent: @@ -4959,7 +4959,7 @@ design: (work@top) |vpiProcess: \_initial: , line:24:9, endln:24:26 |vpiParent: - \_module: work@Example (work@top.e1), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:44:5, endln:44:41 + \_module_inst: work@Example (work@top.e1), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:44:5, endln:44:41 |vpiStmt: \_assignment: , line:24:17, endln:24:25 |vpiParent: @@ -4979,7 +4979,7 @@ design: (work@top) |vpiProcess: \_initial: , line:24:9, endln:24:26 |vpiParent: - \_module: work@Example (work@top.e1), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:44:5, endln:44:41 + \_module_inst: work@Example (work@top.e1), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:44:5, endln:44:41 |vpiStmt: \_assignment: , line:24:17, endln:24:25 |vpiParent: @@ -4999,7 +4999,7 @@ design: (work@top) |vpiProcess: \_initial: , line:24:9, endln:24:26 |vpiParent: - \_module: work@Example (work@top.e1), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:44:5, endln:44:41 + \_module_inst: work@Example (work@top.e1), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:44:5, endln:44:41 |vpiStmt: \_assignment: , line:24:17, endln:24:25 |vpiParent: @@ -5019,7 +5019,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e1.genblk1), line:12:9, endln:15:29 |vpiParent: - \_module: work@Example (work@top.e1), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:44:5, endln:44:41 + \_module_inst: work@Example (work@top.e1), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:44:5, endln:44:41 |vpiName:genblk1 |vpiFullName:work@top.e1.genblk1 |vpiGenScope: @@ -5050,7 +5050,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e1.genblk2), line:17:9, endln:21:16 |vpiParent: - \_module: work@Example (work@top.e1), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:44:5, endln:44:41 + \_module_inst: work@Example (work@top.e1), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:44:5, endln:44:41 |vpiName:genblk2 |vpiFullName:work@top.e1.genblk2 |vpiGenScope: @@ -5085,7 +5085,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e1.genblk3[0]), line:26:13, endln:27:34 |vpiParent: - \_module: work@Example (work@top.e1), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:44:5, endln:44:41 + \_module_inst: work@Example (work@top.e1), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:44:5, endln:44:41 |vpiName:genblk3[0] |vpiFullName:work@top.e1.genblk3[0] |vpiGenScope: @@ -5106,7 +5106,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e1.genblk3[1]), line:26:13, endln:27:34 |vpiParent: - \_module: work@Example (work@top.e1), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:44:5, endln:44:41 + \_module_inst: work@Example (work@top.e1), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:44:5, endln:44:41 |vpiName:genblk3[1] |vpiFullName:work@top.e1.genblk3[1] |vpiGenScope: @@ -5127,7 +5127,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e1.genblk3[2]), line:26:13, endln:27:34 |vpiParent: - \_module: work@Example (work@top.e1), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:44:5, endln:44:41 + \_module_inst: work@Example (work@top.e1), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:44:5, endln:44:41 |vpiName:genblk3[2] |vpiFullName:work@top.e1.genblk3[2] |vpiGenScope: @@ -5148,7 +5148,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e1.genblk3[3]), line:26:13, endln:27:34 |vpiParent: - \_module: work@Example (work@top.e1), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:44:5, endln:44:41 + \_module_inst: work@Example (work@top.e1), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:44:5, endln:44:41 |vpiName:genblk3[3] |vpiFullName:work@top.e1.genblk3[3] |vpiGenScope: @@ -5169,7 +5169,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e1.genblk3[4]), line:26:13, endln:27:34 |vpiParent: - \_module: work@Example (work@top.e1), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:44:5, endln:44:41 + \_module_inst: work@Example (work@top.e1), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:44:5, endln:44:41 |vpiName:genblk3[4] |vpiFullName:work@top.e1.genblk3[4] |vpiGenScope: @@ -5190,7 +5190,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e1.genblk3[5]), line:26:13, endln:27:34 |vpiParent: - \_module: work@Example (work@top.e1), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:44:5, endln:44:41 + \_module_inst: work@Example (work@top.e1), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:44:5, endln:44:41 |vpiName:genblk3[5] |vpiFullName:work@top.e1.genblk3[5] |vpiGenScope: @@ -5211,7 +5211,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e1.genblk3[6]), line:26:13, endln:27:34 |vpiParent: - \_module: work@Example (work@top.e1), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:44:5, endln:44:41 + \_module_inst: work@Example (work@top.e1), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:44:5, endln:44:41 |vpiName:genblk3[6] |vpiFullName:work@top.e1.genblk3[6] |vpiGenScope: @@ -5232,7 +5232,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e1.genblk3[7]), line:26:13, endln:27:34 |vpiParent: - \_module: work@Example (work@top.e1), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:44:5, endln:44:41 + \_module_inst: work@Example (work@top.e1), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:44:5, endln:44:41 |vpiName:genblk3[7] |vpiFullName:work@top.e1.genblk3[7] |vpiGenScope: @@ -5253,7 +5253,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e1.genblk3[8]), line:26:13, endln:27:34 |vpiParent: - \_module: work@Example (work@top.e1), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:44:5, endln:44:41 + \_module_inst: work@Example (work@top.e1), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:44:5, endln:44:41 |vpiName:genblk3[8] |vpiFullName:work@top.e1.genblk3[8] |vpiGenScope: @@ -5274,7 +5274,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e1.genblk3[9]), line:26:13, endln:27:34 |vpiParent: - \_module: work@Example (work@top.e1), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:44:5, endln:44:41 + \_module_inst: work@Example (work@top.e1), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:44:5, endln:44:41 |vpiName:genblk3[9] |vpiFullName:work@top.e1.genblk3[9] |vpiGenScope: @@ -5295,7 +5295,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e1.genblk3[10]), line:26:13, endln:27:34 |vpiParent: - \_module: work@Example (work@top.e1), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:44:5, endln:44:41 + \_module_inst: work@Example (work@top.e1), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:44:5, endln:44:41 |vpiName:genblk3[10] |vpiFullName:work@top.e1.genblk3[10] |vpiGenScope: @@ -5316,7 +5316,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e1.genblk3[11]), line:26:13, endln:27:34 |vpiParent: - \_module: work@Example (work@top.e1), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:44:5, endln:44:41 + \_module_inst: work@Example (work@top.e1), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:44:5, endln:44:41 |vpiName:genblk3[11] |vpiFullName:work@top.e1.genblk3[11] |vpiGenScope: @@ -5337,7 +5337,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e1.genblk3[12]), line:26:13, endln:27:34 |vpiParent: - \_module: work@Example (work@top.e1), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:44:5, endln:44:41 + \_module_inst: work@Example (work@top.e1), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:44:5, endln:44:41 |vpiName:genblk3[12] |vpiFullName:work@top.e1.genblk3[12] |vpiGenScope: @@ -5358,7 +5358,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e1.genblk3[13]), line:26:13, endln:27:34 |vpiParent: - \_module: work@Example (work@top.e1), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:44:5, endln:44:41 + \_module_inst: work@Example (work@top.e1), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:44:5, endln:44:41 |vpiName:genblk3[13] |vpiFullName:work@top.e1.genblk3[13] |vpiGenScope: @@ -5379,7 +5379,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e1.genblk3[14]), line:26:13, endln:27:34 |vpiParent: - \_module: work@Example (work@top.e1), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:44:5, endln:44:41 + \_module_inst: work@Example (work@top.e1), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:44:5, endln:44:41 |vpiName:genblk3[14] |vpiFullName:work@top.e1.genblk3[14] |vpiGenScope: @@ -5400,7 +5400,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e1.genblk3[15]), line:26:13, endln:27:34 |vpiParent: - \_module: work@Example (work@top.e1), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:44:5, endln:44:41 + \_module_inst: work@Example (work@top.e1), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:44:5, endln:44:41 |vpiName:genblk3[15] |vpiFullName:work@top.e1.genblk3[15] |vpiGenScope: @@ -5421,7 +5421,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e1.genblk3[16]), line:26:13, endln:27:34 |vpiParent: - \_module: work@Example (work@top.e1), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:44:5, endln:44:41 + \_module_inst: work@Example (work@top.e1), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:44:5, endln:44:41 |vpiName:genblk3[16] |vpiFullName:work@top.e1.genblk3[16] |vpiGenScope: @@ -5442,7 +5442,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e1.genblk3[17]), line:26:13, endln:27:34 |vpiParent: - \_module: work@Example (work@top.e1), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:44:5, endln:44:41 + \_module_inst: work@Example (work@top.e1), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:44:5, endln:44:41 |vpiName:genblk3[17] |vpiFullName:work@top.e1.genblk3[17] |vpiGenScope: @@ -5463,7 +5463,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e1.genblk3[18]), line:26:13, endln:27:34 |vpiParent: - \_module: work@Example (work@top.e1), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:44:5, endln:44:41 + \_module_inst: work@Example (work@top.e1), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:44:5, endln:44:41 |vpiName:genblk3[18] |vpiFullName:work@top.e1.genblk3[18] |vpiGenScope: @@ -5484,7 +5484,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e1.genblk3[19]), line:26:13, endln:27:34 |vpiParent: - \_module: work@Example (work@top.e1), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:44:5, endln:44:41 + \_module_inst: work@Example (work@top.e1), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:44:5, endln:44:41 |vpiName:genblk3[19] |vpiFullName:work@top.e1.genblk3[19] |vpiGenScope: @@ -5505,7 +5505,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e1.genblk3[20]), line:26:13, endln:27:34 |vpiParent: - \_module: work@Example (work@top.e1), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:44:5, endln:44:41 + \_module_inst: work@Example (work@top.e1), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:44:5, endln:44:41 |vpiName:genblk3[20] |vpiFullName:work@top.e1.genblk3[20] |vpiGenScope: @@ -5526,7 +5526,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e1.genblk3[21]), line:26:13, endln:27:34 |vpiParent: - \_module: work@Example (work@top.e1), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:44:5, endln:44:41 + \_module_inst: work@Example (work@top.e1), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:44:5, endln:44:41 |vpiName:genblk3[21] |vpiFullName:work@top.e1.genblk3[21] |vpiGenScope: @@ -5547,7 +5547,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e1.genblk3[22]), line:26:13, endln:27:34 |vpiParent: - \_module: work@Example (work@top.e1), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:44:5, endln:44:41 + \_module_inst: work@Example (work@top.e1), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:44:5, endln:44:41 |vpiName:genblk3[22] |vpiFullName:work@top.e1.genblk3[22] |vpiGenScope: @@ -5568,7 +5568,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e1.genblk3[23]), line:26:13, endln:27:34 |vpiParent: - \_module: work@Example (work@top.e1), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:44:5, endln:44:41 + \_module_inst: work@Example (work@top.e1), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:44:5, endln:44:41 |vpiName:genblk3[23] |vpiFullName:work@top.e1.genblk3[23] |vpiGenScope: @@ -5589,7 +5589,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e1.genblk3[24]), line:26:13, endln:27:34 |vpiParent: - \_module: work@Example (work@top.e1), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:44:5, endln:44:41 + \_module_inst: work@Example (work@top.e1), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:44:5, endln:44:41 |vpiName:genblk3[24] |vpiFullName:work@top.e1.genblk3[24] |vpiGenScope: @@ -5610,7 +5610,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e1.genblk3[25]), line:26:13, endln:27:34 |vpiParent: - \_module: work@Example (work@top.e1), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:44:5, endln:44:41 + \_module_inst: work@Example (work@top.e1), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:44:5, endln:44:41 |vpiName:genblk3[25] |vpiFullName:work@top.e1.genblk3[25] |vpiGenScope: @@ -5631,7 +5631,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e1.genblk3[26]), line:26:13, endln:27:34 |vpiParent: - \_module: work@Example (work@top.e1), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:44:5, endln:44:41 + \_module_inst: work@Example (work@top.e1), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:44:5, endln:44:41 |vpiName:genblk3[26] |vpiFullName:work@top.e1.genblk3[26] |vpiGenScope: @@ -5652,7 +5652,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e1.genblk3[27]), line:26:13, endln:27:34 |vpiParent: - \_module: work@Example (work@top.e1), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:44:5, endln:44:41 + \_module_inst: work@Example (work@top.e1), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:44:5, endln:44:41 |vpiName:genblk3[27] |vpiFullName:work@top.e1.genblk3[27] |vpiGenScope: @@ -5673,7 +5673,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e1.genblk3[28]), line:26:13, endln:27:34 |vpiParent: - \_module: work@Example (work@top.e1), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:44:5, endln:44:41 + \_module_inst: work@Example (work@top.e1), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:44:5, endln:44:41 |vpiName:genblk3[28] |vpiFullName:work@top.e1.genblk3[28] |vpiGenScope: @@ -5694,7 +5694,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e1.genblk3[29]), line:26:13, endln:27:34 |vpiParent: - \_module: work@Example (work@top.e1), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:44:5, endln:44:41 + \_module_inst: work@Example (work@top.e1), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:44:5, endln:44:41 |vpiName:genblk3[29] |vpiFullName:work@top.e1.genblk3[29] |vpiGenScope: @@ -5715,7 +5715,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e1.genblk3[30]), line:26:13, endln:27:34 |vpiParent: - \_module: work@Example (work@top.e1), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:44:5, endln:44:41 + \_module_inst: work@Example (work@top.e1), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:44:5, endln:44:41 |vpiName:genblk3[30] |vpiFullName:work@top.e1.genblk3[30] |vpiGenScope: @@ -5736,7 +5736,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e1.genblk3[31]), line:26:13, endln:27:34 |vpiParent: - \_module: work@Example (work@top.e1), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:44:5, endln:44:41 + \_module_inst: work@Example (work@top.e1), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:44:5, endln:44:41 |vpiName:genblk3[31] |vpiFullName:work@top.e1.genblk3[31] |vpiGenScope: @@ -5757,7 +5757,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e1.genblk3[32]), line:26:13, endln:27:34 |vpiParent: - \_module: work@Example (work@top.e1), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:44:5, endln:44:41 + \_module_inst: work@Example (work@top.e1), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:44:5, endln:44:41 |vpiName:genblk3[32] |vpiFullName:work@top.e1.genblk3[32] |vpiGenScope: @@ -5778,7 +5778,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e1.genblk3[33]), line:26:13, endln:27:34 |vpiParent: - \_module: work@Example (work@top.e1), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:44:5, endln:44:41 + \_module_inst: work@Example (work@top.e1), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:44:5, endln:44:41 |vpiName:genblk3[33] |vpiFullName:work@top.e1.genblk3[33] |vpiGenScope: @@ -5799,7 +5799,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e1.genblk3[34]), line:26:13, endln:27:34 |vpiParent: - \_module: work@Example (work@top.e1), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:44:5, endln:44:41 + \_module_inst: work@Example (work@top.e1), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:44:5, endln:44:41 |vpiName:genblk3[34] |vpiFullName:work@top.e1.genblk3[34] |vpiGenScope: @@ -5820,7 +5820,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e1.genblk3[35]), line:26:13, endln:27:34 |vpiParent: - \_module: work@Example (work@top.e1), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:44:5, endln:44:41 + \_module_inst: work@Example (work@top.e1), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:44:5, endln:44:41 |vpiName:genblk3[35] |vpiFullName:work@top.e1.genblk3[35] |vpiGenScope: @@ -5841,7 +5841,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e1.genblk3[36]), line:26:13, endln:27:34 |vpiParent: - \_module: work@Example (work@top.e1), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:44:5, endln:44:41 + \_module_inst: work@Example (work@top.e1), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:44:5, endln:44:41 |vpiName:genblk3[36] |vpiFullName:work@top.e1.genblk3[36] |vpiGenScope: @@ -5862,7 +5862,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e1.genblk3[37]), line:26:13, endln:27:34 |vpiParent: - \_module: work@Example (work@top.e1), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:44:5, endln:44:41 + \_module_inst: work@Example (work@top.e1), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:44:5, endln:44:41 |vpiName:genblk3[37] |vpiFullName:work@top.e1.genblk3[37] |vpiGenScope: @@ -5883,7 +5883,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e1.genblk3[38]), line:26:13, endln:27:34 |vpiParent: - \_module: work@Example (work@top.e1), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:44:5, endln:44:41 + \_module_inst: work@Example (work@top.e1), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:44:5, endln:44:41 |vpiName:genblk3[38] |vpiFullName:work@top.e1.genblk3[38] |vpiGenScope: @@ -5904,7 +5904,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e1.genblk3[39]), line:26:13, endln:27:34 |vpiParent: - \_module: work@Example (work@top.e1), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:44:5, endln:44:41 + \_module_inst: work@Example (work@top.e1), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:44:5, endln:44:41 |vpiName:genblk3[39] |vpiFullName:work@top.e1.genblk3[39] |vpiGenScope: @@ -5925,7 +5925,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e1.genblk3[40]), line:26:13, endln:27:34 |vpiParent: - \_module: work@Example (work@top.e1), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:44:5, endln:44:41 + \_module_inst: work@Example (work@top.e1), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:44:5, endln:44:41 |vpiName:genblk3[40] |vpiFullName:work@top.e1.genblk3[40] |vpiGenScope: @@ -5946,7 +5946,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e1.genblk3[41]), line:26:13, endln:27:34 |vpiParent: - \_module: work@Example (work@top.e1), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:44:5, endln:44:41 + \_module_inst: work@Example (work@top.e1), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:44:5, endln:44:41 |vpiName:genblk3[41] |vpiFullName:work@top.e1.genblk3[41] |vpiGenScope: @@ -5967,7 +5967,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e1.genblk3[42]), line:26:13, endln:27:34 |vpiParent: - \_module: work@Example (work@top.e1), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:44:5, endln:44:41 + \_module_inst: work@Example (work@top.e1), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:44:5, endln:44:41 |vpiName:genblk3[42] |vpiFullName:work@top.e1.genblk3[42] |vpiGenScope: @@ -5988,7 +5988,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e1.genblk3[43]), line:26:13, endln:27:34 |vpiParent: - \_module: work@Example (work@top.e1), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:44:5, endln:44:41 + \_module_inst: work@Example (work@top.e1), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:44:5, endln:44:41 |vpiName:genblk3[43] |vpiFullName:work@top.e1.genblk3[43] |vpiGenScope: @@ -6009,7 +6009,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e1.genblk3[44]), line:26:13, endln:27:34 |vpiParent: - \_module: work@Example (work@top.e1), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:44:5, endln:44:41 + \_module_inst: work@Example (work@top.e1), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:44:5, endln:44:41 |vpiName:genblk3[44] |vpiFullName:work@top.e1.genblk3[44] |vpiGenScope: @@ -6030,7 +6030,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e1.genblk3[45]), line:26:13, endln:27:34 |vpiParent: - \_module: work@Example (work@top.e1), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:44:5, endln:44:41 + \_module_inst: work@Example (work@top.e1), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:44:5, endln:44:41 |vpiName:genblk3[45] |vpiFullName:work@top.e1.genblk3[45] |vpiGenScope: @@ -6051,7 +6051,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e1.genblk3[46]), line:26:13, endln:27:34 |vpiParent: - \_module: work@Example (work@top.e1), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:44:5, endln:44:41 + \_module_inst: work@Example (work@top.e1), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:44:5, endln:44:41 |vpiName:genblk3[46] |vpiFullName:work@top.e1.genblk3[46] |vpiGenScope: @@ -6072,7 +6072,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e1.genblk3[47]), line:26:13, endln:27:34 |vpiParent: - \_module: work@Example (work@top.e1), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:44:5, endln:44:41 + \_module_inst: work@Example (work@top.e1), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:44:5, endln:44:41 |vpiName:genblk3[47] |vpiFullName:work@top.e1.genblk3[47] |vpiGenScope: @@ -6093,7 +6093,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e1.genblk3[48]), line:26:13, endln:27:34 |vpiParent: - \_module: work@Example (work@top.e1), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:44:5, endln:44:41 + \_module_inst: work@Example (work@top.e1), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:44:5, endln:44:41 |vpiName:genblk3[48] |vpiFullName:work@top.e1.genblk3[48] |vpiGenScope: @@ -6114,7 +6114,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e1.genblk3[49]), line:26:13, endln:27:34 |vpiParent: - \_module: work@Example (work@top.e1), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:44:5, endln:44:41 + \_module_inst: work@Example (work@top.e1), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:44:5, endln:44:41 |vpiName:genblk3[49] |vpiFullName:work@top.e1.genblk3[49] |vpiGenScope: @@ -6135,7 +6135,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e1.genblk3[50]), line:26:13, endln:27:34 |vpiParent: - \_module: work@Example (work@top.e1), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:44:5, endln:44:41 + \_module_inst: work@Example (work@top.e1), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:44:5, endln:44:41 |vpiName:genblk3[50] |vpiFullName:work@top.e1.genblk3[50] |vpiGenScope: @@ -6156,7 +6156,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e1.genblk3[51]), line:26:13, endln:27:34 |vpiParent: - \_module: work@Example (work@top.e1), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:44:5, endln:44:41 + \_module_inst: work@Example (work@top.e1), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:44:5, endln:44:41 |vpiName:genblk3[51] |vpiFullName:work@top.e1.genblk3[51] |vpiGenScope: @@ -6177,7 +6177,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e1.genblk3[52]), line:26:13, endln:27:34 |vpiParent: - \_module: work@Example (work@top.e1), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:44:5, endln:44:41 + \_module_inst: work@Example (work@top.e1), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:44:5, endln:44:41 |vpiName:genblk3[52] |vpiFullName:work@top.e1.genblk3[52] |vpiGenScope: @@ -6198,7 +6198,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e1.genblk3[53]), line:26:13, endln:27:34 |vpiParent: - \_module: work@Example (work@top.e1), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:44:5, endln:44:41 + \_module_inst: work@Example (work@top.e1), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:44:5, endln:44:41 |vpiName:genblk3[53] |vpiFullName:work@top.e1.genblk3[53] |vpiGenScope: @@ -6219,7 +6219,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e1.genblk3[54]), line:26:13, endln:27:34 |vpiParent: - \_module: work@Example (work@top.e1), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:44:5, endln:44:41 + \_module_inst: work@Example (work@top.e1), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:44:5, endln:44:41 |vpiName:genblk3[54] |vpiFullName:work@top.e1.genblk3[54] |vpiGenScope: @@ -6240,7 +6240,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e1.genblk3[55]), line:26:13, endln:27:34 |vpiParent: - \_module: work@Example (work@top.e1), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:44:5, endln:44:41 + \_module_inst: work@Example (work@top.e1), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:44:5, endln:44:41 |vpiName:genblk3[55] |vpiFullName:work@top.e1.genblk3[55] |vpiGenScope: @@ -6261,7 +6261,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e1.genblk3[56]), line:26:13, endln:27:34 |vpiParent: - \_module: work@Example (work@top.e1), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:44:5, endln:44:41 + \_module_inst: work@Example (work@top.e1), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:44:5, endln:44:41 |vpiName:genblk3[56] |vpiFullName:work@top.e1.genblk3[56] |vpiGenScope: @@ -6282,7 +6282,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e1.genblk3[57]), line:26:13, endln:27:34 |vpiParent: - \_module: work@Example (work@top.e1), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:44:5, endln:44:41 + \_module_inst: work@Example (work@top.e1), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:44:5, endln:44:41 |vpiName:genblk3[57] |vpiFullName:work@top.e1.genblk3[57] |vpiGenScope: @@ -6303,7 +6303,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e1.genblk3[58]), line:26:13, endln:27:34 |vpiParent: - \_module: work@Example (work@top.e1), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:44:5, endln:44:41 + \_module_inst: work@Example (work@top.e1), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:44:5, endln:44:41 |vpiName:genblk3[58] |vpiFullName:work@top.e1.genblk3[58] |vpiGenScope: @@ -6324,7 +6324,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e1.genblk3[59]), line:26:13, endln:27:34 |vpiParent: - \_module: work@Example (work@top.e1), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:44:5, endln:44:41 + \_module_inst: work@Example (work@top.e1), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:44:5, endln:44:41 |vpiName:genblk3[59] |vpiFullName:work@top.e1.genblk3[59] |vpiGenScope: @@ -6345,7 +6345,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e1.genblk3[60]), line:26:13, endln:27:34 |vpiParent: - \_module: work@Example (work@top.e1), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:44:5, endln:44:41 + \_module_inst: work@Example (work@top.e1), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:44:5, endln:44:41 |vpiName:genblk3[60] |vpiFullName:work@top.e1.genblk3[60] |vpiGenScope: @@ -6366,7 +6366,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e1.genblk3[61]), line:26:13, endln:27:34 |vpiParent: - \_module: work@Example (work@top.e1), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:44:5, endln:44:41 + \_module_inst: work@Example (work@top.e1), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:44:5, endln:44:41 |vpiName:genblk3[61] |vpiFullName:work@top.e1.genblk3[61] |vpiGenScope: @@ -6387,7 +6387,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e1.genblk3[62]), line:26:13, endln:27:34 |vpiParent: - \_module: work@Example (work@top.e1), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:44:5, endln:44:41 + \_module_inst: work@Example (work@top.e1), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:44:5, endln:44:41 |vpiName:genblk3[62] |vpiFullName:work@top.e1.genblk3[62] |vpiGenScope: @@ -6408,7 +6408,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e1.genblk3[63]), line:26:13, endln:27:34 |vpiParent: - \_module: work@Example (work@top.e1), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:44:5, endln:44:41 + \_module_inst: work@Example (work@top.e1), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:44:5, endln:44:41 |vpiName:genblk3[63] |vpiFullName:work@top.e1.genblk3[63] |vpiGenScope: @@ -6429,7 +6429,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e1.genblk3[64]), line:26:13, endln:27:34 |vpiParent: - \_module: work@Example (work@top.e1), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:44:5, endln:44:41 + \_module_inst: work@Example (work@top.e1), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:44:5, endln:44:41 |vpiName:genblk3[64] |vpiFullName:work@top.e1.genblk3[64] |vpiGenScope: @@ -6450,7 +6450,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e1.genblk3[65]), line:26:13, endln:27:34 |vpiParent: - \_module: work@Example (work@top.e1), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:44:5, endln:44:41 + \_module_inst: work@Example (work@top.e1), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:44:5, endln:44:41 |vpiName:genblk3[65] |vpiFullName:work@top.e1.genblk3[65] |vpiGenScope: @@ -6471,7 +6471,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e1.genblk3[66]), line:26:13, endln:27:34 |vpiParent: - \_module: work@Example (work@top.e1), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:44:5, endln:44:41 + \_module_inst: work@Example (work@top.e1), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:44:5, endln:44:41 |vpiName:genblk3[66] |vpiFullName:work@top.e1.genblk3[66] |vpiGenScope: @@ -6492,7 +6492,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e1.genblk3[67]), line:26:13, endln:27:34 |vpiParent: - \_module: work@Example (work@top.e1), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:44:5, endln:44:41 + \_module_inst: work@Example (work@top.e1), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:44:5, endln:44:41 |vpiName:genblk3[67] |vpiFullName:work@top.e1.genblk3[67] |vpiGenScope: @@ -6513,7 +6513,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e1.genblk3[68]), line:26:13, endln:27:34 |vpiParent: - \_module: work@Example (work@top.e1), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:44:5, endln:44:41 + \_module_inst: work@Example (work@top.e1), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:44:5, endln:44:41 |vpiName:genblk3[68] |vpiFullName:work@top.e1.genblk3[68] |vpiGenScope: @@ -6534,7 +6534,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e1.genblk3[69]), line:26:13, endln:27:34 |vpiParent: - \_module: work@Example (work@top.e1), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:44:5, endln:44:41 + \_module_inst: work@Example (work@top.e1), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:44:5, endln:44:41 |vpiName:genblk3[69] |vpiFullName:work@top.e1.genblk3[69] |vpiGenScope: @@ -6555,7 +6555,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e1.genblk3[70]), line:26:13, endln:27:34 |vpiParent: - \_module: work@Example (work@top.e1), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:44:5, endln:44:41 + \_module_inst: work@Example (work@top.e1), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:44:5, endln:44:41 |vpiName:genblk3[70] |vpiFullName:work@top.e1.genblk3[70] |vpiGenScope: @@ -6576,7 +6576,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e1.genblk3[71]), line:26:13, endln:27:34 |vpiParent: - \_module: work@Example (work@top.e1), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:44:5, endln:44:41 + \_module_inst: work@Example (work@top.e1), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:44:5, endln:44:41 |vpiName:genblk3[71] |vpiFullName:work@top.e1.genblk3[71] |vpiGenScope: @@ -6597,7 +6597,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e1.genblk3[72]), line:26:13, endln:27:34 |vpiParent: - \_module: work@Example (work@top.e1), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:44:5, endln:44:41 + \_module_inst: work@Example (work@top.e1), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:44:5, endln:44:41 |vpiName:genblk3[72] |vpiFullName:work@top.e1.genblk3[72] |vpiGenScope: @@ -6618,7 +6618,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e1.genblk3[73]), line:26:13, endln:27:34 |vpiParent: - \_module: work@Example (work@top.e1), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:44:5, endln:44:41 + \_module_inst: work@Example (work@top.e1), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:44:5, endln:44:41 |vpiName:genblk3[73] |vpiFullName:work@top.e1.genblk3[73] |vpiGenScope: @@ -6639,7 +6639,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e1.genblk3[74]), line:26:13, endln:27:34 |vpiParent: - \_module: work@Example (work@top.e1), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:44:5, endln:44:41 + \_module_inst: work@Example (work@top.e1), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:44:5, endln:44:41 |vpiName:genblk3[74] |vpiFullName:work@top.e1.genblk3[74] |vpiGenScope: @@ -6660,7 +6660,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e1.genblk3[75]), line:26:13, endln:27:34 |vpiParent: - \_module: work@Example (work@top.e1), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:44:5, endln:44:41 + \_module_inst: work@Example (work@top.e1), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:44:5, endln:44:41 |vpiName:genblk3[75] |vpiFullName:work@top.e1.genblk3[75] |vpiGenScope: @@ -6681,7 +6681,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e1.genblk3[76]), line:26:13, endln:27:34 |vpiParent: - \_module: work@Example (work@top.e1), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:44:5, endln:44:41 + \_module_inst: work@Example (work@top.e1), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:44:5, endln:44:41 |vpiName:genblk3[76] |vpiFullName:work@top.e1.genblk3[76] |vpiGenScope: @@ -6702,7 +6702,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e1.genblk3[77]), line:26:13, endln:27:34 |vpiParent: - \_module: work@Example (work@top.e1), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:44:5, endln:44:41 + \_module_inst: work@Example (work@top.e1), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:44:5, endln:44:41 |vpiName:genblk3[77] |vpiFullName:work@top.e1.genblk3[77] |vpiGenScope: @@ -6723,7 +6723,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e1.genblk3[78]), line:26:13, endln:27:34 |vpiParent: - \_module: work@Example (work@top.e1), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:44:5, endln:44:41 + \_module_inst: work@Example (work@top.e1), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:44:5, endln:44:41 |vpiName:genblk3[78] |vpiFullName:work@top.e1.genblk3[78] |vpiGenScope: @@ -6778,16 +6778,16 @@ design: (work@top) |vpiFullName:work@top.e1.genblk3[78].genblk1.outC |vpiActual: \_logic_net: (work@top.e1.outC), line:1:28, endln:1:32 - |vpiModule: - \_module: work@Example (work@top.e2), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:45:5, endln:45:41 + |vpiModuleInst: + \_module_inst: work@Example (work@top.e2), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:45:5, endln:45:41 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:39:1, endln:86:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:39:1, endln:86:10 |vpiName:e2 |vpiFullName:work@top.e2 |vpiVariables: \_integer_var: (work@top.e2.j), line:30:13, endln:30:14 |vpiParent: - \_module: work@Example (work@top.e2), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:45:5, endln:45:41 + \_module_inst: work@Example (work@top.e2), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:45:5, endln:45:41 |vpiTypespec: \_integer_typespec: , line:30:5, endln:30:12 |vpiSigned:1 @@ -6797,7 +6797,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.e2.OUTPUT), line:2:15, endln:2:21 |vpiParent: - \_module: work@Example (work@top.e2), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:45:5, endln:45:41 + \_module_inst: work@Example (work@top.e2), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:45:5, endln:45:41 |STRING:FOO |vpiTypespec: \_string_typespec: @@ -6808,7 +6808,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:2:15, endln:2:29 |vpiParent: - \_module: work@Example (work@top.e2), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:45:5, endln:45:41 + \_module_inst: work@Example (work@top.e2), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:45:5, endln:45:41 |vpiOverriden:1 |vpiRhs: \_constant: , line:2:24, endln:2:29 @@ -6826,7 +6826,7 @@ design: (work@top) |vpiTaskFunc: \_function: (work@top.e2.flip), line:6:5, endln:9:16 |vpiParent: - \_module: work@Example (work@top.e2), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:45:5, endln:45:41 + \_module_inst: work@Example (work@top.e2), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:45:5, endln:45:41 |vpiName:flip |vpiFullName:work@top.e2.flip |vpiVisibility:1 @@ -6834,7 +6834,7 @@ design: (work@top) |vpiReturn: \_logic_var: , line:6:24, endln:6:30 |vpiParent: - \_module: work@Example (work@top.e2), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:45:5, endln:45:41 + \_module_inst: work@Example (work@top.e2), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:45:5, endln:45:41 |vpiIODecl: \_io_decl: (inp), line:7:22, endln:7:25 |vpiParent: @@ -6871,11 +6871,11 @@ design: (work@top) |vpiActual: \_logic_var: , line:6:24, endln:6:30 |vpiInstance: - \_module: work@Example (work@top.e2), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:45:5, endln:45:41 + \_module_inst: work@Example (work@top.e2), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:45:5, endln:45:41 |vpiNet: \_logic_net: (work@top.e2.outA), line:1:16, endln:1:20 |vpiParent: - \_module: work@Example (work@top.e2), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:45:5, endln:45:41 + \_module_inst: work@Example (work@top.e2), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:45:5, endln:45:41 |vpiTypespec: \_logic_typespec: , line:3:12, endln:3:23 |vpiRange: @@ -6902,7 +6902,7 @@ design: (work@top) |vpiNet: \_logic_net: (work@top.e2.outB), line:1:22, endln:1:26 |vpiParent: - \_module: work@Example (work@top.e2), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:45:5, endln:45:41 + \_module_inst: work@Example (work@top.e2), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:45:5, endln:45:41 |vpiTypespec: \_logic_typespec: , line:4:12, endln:4:23 |vpiRange: @@ -6929,7 +6929,7 @@ design: (work@top) |vpiNet: \_logic_net: (work@top.e2.outC), line:1:28, endln:1:32 |vpiParent: - \_module: work@Example (work@top.e2), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:45:5, endln:45:41 + \_module_inst: work@Example (work@top.e2), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:45:5, endln:45:41 |vpiTypespec: \_logic_typespec: , line:5:12, endln:5:15 |vpiName:outC @@ -6938,18 +6938,18 @@ design: (work@top) |vpiNet: \_logic_net: (work@top.e2.outD), line:1:34, endln:1:38 |vpiParent: - \_module: work@Example (work@top.e2), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:45:5, endln:45:41 + \_module_inst: work@Example (work@top.e2), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:45:5, endln:45:41 |vpiTypespec: \_logic_typespec: , line:5:12, endln:5:15 |vpiName:outD |vpiFullName:work@top.e2.outD |vpiNetType:48 |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:39:1, endln:86:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:39:1, endln:86:10 |vpiPort: \_port: (outA), line:1:16, endln:1:20 |vpiParent: - \_module: work@Example (work@top.e2), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:45:5, endln:45:41 + \_module_inst: work@Example (work@top.e2), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:45:5, endln:45:41 |vpiName:outA |vpiDirection:2 |vpiHighConn: @@ -6991,11 +6991,11 @@ design: (work@top) |UINT:0 |vpiConstType:9 |vpiInstance: - \_module: work@Example (work@top.e2), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:45:5, endln:45:41 + \_module_inst: work@Example (work@top.e2), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:45:5, endln:45:41 |vpiPort: \_port: (outB), line:1:22, endln:1:26 |vpiParent: - \_module: work@Example (work@top.e2), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:45:5, endln:45:41 + \_module_inst: work@Example (work@top.e2), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:45:5, endln:45:41 |vpiName:outB |vpiDirection:2 |vpiHighConn: @@ -7037,11 +7037,11 @@ design: (work@top) |UINT:0 |vpiConstType:9 |vpiInstance: - \_module: work@Example (work@top.e2), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:45:5, endln:45:41 + \_module_inst: work@Example (work@top.e2), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:45:5, endln:45:41 |vpiPort: \_port: (outC), line:1:28, endln:1:32 |vpiParent: - \_module: work@Example (work@top.e2), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:45:5, endln:45:41 + \_module_inst: work@Example (work@top.e2), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:45:5, endln:45:41 |vpiName:outC |vpiDirection:2 |vpiHighConn: @@ -7063,11 +7063,11 @@ design: (work@top) |vpiTypedef: \_logic_typespec: , line:5:12, endln:5:15 |vpiInstance: - \_module: work@Example (work@top.e2), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:45:5, endln:45:41 + \_module_inst: work@Example (work@top.e2), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:45:5, endln:45:41 |vpiPort: \_port: (outD), line:1:34, endln:1:38 |vpiParent: - \_module: work@Example (work@top.e2), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:45:5, endln:45:41 + \_module_inst: work@Example (work@top.e2), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:45:5, endln:45:41 |vpiName:outD |vpiDirection:2 |vpiHighConn: @@ -7089,11 +7089,11 @@ design: (work@top) |vpiTypedef: \_logic_typespec: , line:5:12, endln:5:15 |vpiInstance: - \_module: work@Example (work@top.e2), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:45:5, endln:45:41 + \_module_inst: work@Example (work@top.e2), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:45:5, endln:45:41 |vpiProcess: \_initial: , line:31:5, endln:36:8 |vpiParent: - \_module: work@Example (work@top.e2), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:45:5, endln:45:41 + \_module_inst: work@Example (work@top.e2), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:45:5, endln:45:41 |vpiStmt: \_begin: (work@top.e2), line:31:13, endln:36:8 |vpiParent: @@ -7265,7 +7265,7 @@ design: (work@top) |vpiProcess: \_initial: , line:24:9, endln:24:26 |vpiParent: - \_module: work@Example (work@top.e2), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:45:5, endln:45:41 + \_module_inst: work@Example (work@top.e2), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:45:5, endln:45:41 |vpiStmt: \_assignment: , line:24:17, endln:24:25 |vpiParent: @@ -7285,7 +7285,7 @@ design: (work@top) |vpiProcess: \_initial: , line:24:9, endln:24:26 |vpiParent: - \_module: work@Example (work@top.e2), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:45:5, endln:45:41 + \_module_inst: work@Example (work@top.e2), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:45:5, endln:45:41 |vpiStmt: \_assignment: , line:24:17, endln:24:25 |vpiParent: @@ -7305,7 +7305,7 @@ design: (work@top) |vpiProcess: \_initial: , line:24:9, endln:24:26 |vpiParent: - \_module: work@Example (work@top.e2), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:45:5, endln:45:41 + \_module_inst: work@Example (work@top.e2), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:45:5, endln:45:41 |vpiStmt: \_assignment: , line:24:17, endln:24:25 |vpiParent: @@ -7325,7 +7325,7 @@ design: (work@top) |vpiProcess: \_initial: , line:24:9, endln:24:26 |vpiParent: - \_module: work@Example (work@top.e2), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:45:5, endln:45:41 + \_module_inst: work@Example (work@top.e2), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:45:5, endln:45:41 |vpiStmt: \_assignment: , line:24:17, endln:24:25 |vpiParent: @@ -7345,7 +7345,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e2.genblk1), line:12:9, endln:15:29 |vpiParent: - \_module: work@Example (work@top.e2), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:45:5, endln:45:41 + \_module_inst: work@Example (work@top.e2), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:45:5, endln:45:41 |vpiName:genblk1 |vpiFullName:work@top.e2.genblk1 |vpiGenScope: @@ -7376,7 +7376,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e2.genblk2), line:17:9, endln:21:16 |vpiParent: - \_module: work@Example (work@top.e2), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:45:5, endln:45:41 + \_module_inst: work@Example (work@top.e2), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:45:5, endln:45:41 |vpiName:genblk2 |vpiFullName:work@top.e2.genblk2 |vpiGenScope: @@ -7411,7 +7411,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e2.genblk3[0]), line:26:13, endln:27:34 |vpiParent: - \_module: work@Example (work@top.e2), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:45:5, endln:45:41 + \_module_inst: work@Example (work@top.e2), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:45:5, endln:45:41 |vpiName:genblk3[0] |vpiFullName:work@top.e2.genblk3[0] |vpiGenScope: @@ -7432,7 +7432,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e2.genblk3[1]), line:26:13, endln:27:34 |vpiParent: - \_module: work@Example (work@top.e2), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:45:5, endln:45:41 + \_module_inst: work@Example (work@top.e2), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:45:5, endln:45:41 |vpiName:genblk3[1] |vpiFullName:work@top.e2.genblk3[1] |vpiGenScope: @@ -7453,7 +7453,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e2.genblk3[2]), line:26:13, endln:27:34 |vpiParent: - \_module: work@Example (work@top.e2), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:45:5, endln:45:41 + \_module_inst: work@Example (work@top.e2), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:45:5, endln:45:41 |vpiName:genblk3[2] |vpiFullName:work@top.e2.genblk3[2] |vpiGenScope: @@ -7474,7 +7474,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e2.genblk3[3]), line:26:13, endln:27:34 |vpiParent: - \_module: work@Example (work@top.e2), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:45:5, endln:45:41 + \_module_inst: work@Example (work@top.e2), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:45:5, endln:45:41 |vpiName:genblk3[3] |vpiFullName:work@top.e2.genblk3[3] |vpiGenScope: @@ -7495,7 +7495,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e2.genblk3[4]), line:26:13, endln:27:34 |vpiParent: - \_module: work@Example (work@top.e2), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:45:5, endln:45:41 + \_module_inst: work@Example (work@top.e2), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:45:5, endln:45:41 |vpiName:genblk3[4] |vpiFullName:work@top.e2.genblk3[4] |vpiGenScope: @@ -7516,7 +7516,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e2.genblk3[5]), line:26:13, endln:27:34 |vpiParent: - \_module: work@Example (work@top.e2), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:45:5, endln:45:41 + \_module_inst: work@Example (work@top.e2), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:45:5, endln:45:41 |vpiName:genblk3[5] |vpiFullName:work@top.e2.genblk3[5] |vpiGenScope: @@ -7537,7 +7537,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e2.genblk3[6]), line:26:13, endln:27:34 |vpiParent: - \_module: work@Example (work@top.e2), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:45:5, endln:45:41 + \_module_inst: work@Example (work@top.e2), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:45:5, endln:45:41 |vpiName:genblk3[6] |vpiFullName:work@top.e2.genblk3[6] |vpiGenScope: @@ -7558,7 +7558,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e2.genblk3[7]), line:26:13, endln:27:34 |vpiParent: - \_module: work@Example (work@top.e2), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:45:5, endln:45:41 + \_module_inst: work@Example (work@top.e2), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:45:5, endln:45:41 |vpiName:genblk3[7] |vpiFullName:work@top.e2.genblk3[7] |vpiGenScope: @@ -7579,7 +7579,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e2.genblk3[8]), line:26:13, endln:27:34 |vpiParent: - \_module: work@Example (work@top.e2), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:45:5, endln:45:41 + \_module_inst: work@Example (work@top.e2), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:45:5, endln:45:41 |vpiName:genblk3[8] |vpiFullName:work@top.e2.genblk3[8] |vpiGenScope: @@ -7600,7 +7600,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e2.genblk3[9]), line:26:13, endln:27:34 |vpiParent: - \_module: work@Example (work@top.e2), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:45:5, endln:45:41 + \_module_inst: work@Example (work@top.e2), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:45:5, endln:45:41 |vpiName:genblk3[9] |vpiFullName:work@top.e2.genblk3[9] |vpiGenScope: @@ -7621,7 +7621,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e2.genblk3[10]), line:26:13, endln:27:34 |vpiParent: - \_module: work@Example (work@top.e2), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:45:5, endln:45:41 + \_module_inst: work@Example (work@top.e2), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:45:5, endln:45:41 |vpiName:genblk3[10] |vpiFullName:work@top.e2.genblk3[10] |vpiGenScope: @@ -7642,7 +7642,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e2.genblk3[11]), line:26:13, endln:27:34 |vpiParent: - \_module: work@Example (work@top.e2), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:45:5, endln:45:41 + \_module_inst: work@Example (work@top.e2), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:45:5, endln:45:41 |vpiName:genblk3[11] |vpiFullName:work@top.e2.genblk3[11] |vpiGenScope: @@ -7663,7 +7663,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e2.genblk3[12]), line:26:13, endln:27:34 |vpiParent: - \_module: work@Example (work@top.e2), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:45:5, endln:45:41 + \_module_inst: work@Example (work@top.e2), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:45:5, endln:45:41 |vpiName:genblk3[12] |vpiFullName:work@top.e2.genblk3[12] |vpiGenScope: @@ -7684,7 +7684,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e2.genblk3[13]), line:26:13, endln:27:34 |vpiParent: - \_module: work@Example (work@top.e2), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:45:5, endln:45:41 + \_module_inst: work@Example (work@top.e2), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:45:5, endln:45:41 |vpiName:genblk3[13] |vpiFullName:work@top.e2.genblk3[13] |vpiGenScope: @@ -7705,7 +7705,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e2.genblk3[14]), line:26:13, endln:27:34 |vpiParent: - \_module: work@Example (work@top.e2), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:45:5, endln:45:41 + \_module_inst: work@Example (work@top.e2), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:45:5, endln:45:41 |vpiName:genblk3[14] |vpiFullName:work@top.e2.genblk3[14] |vpiGenScope: @@ -7726,7 +7726,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e2.genblk3[15]), line:26:13, endln:27:34 |vpiParent: - \_module: work@Example (work@top.e2), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:45:5, endln:45:41 + \_module_inst: work@Example (work@top.e2), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:45:5, endln:45:41 |vpiName:genblk3[15] |vpiFullName:work@top.e2.genblk3[15] |vpiGenScope: @@ -7747,7 +7747,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e2.genblk3[16]), line:26:13, endln:27:34 |vpiParent: - \_module: work@Example (work@top.e2), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:45:5, endln:45:41 + \_module_inst: work@Example (work@top.e2), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:45:5, endln:45:41 |vpiName:genblk3[16] |vpiFullName:work@top.e2.genblk3[16] |vpiGenScope: @@ -7768,7 +7768,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e2.genblk3[17]), line:26:13, endln:27:34 |vpiParent: - \_module: work@Example (work@top.e2), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:45:5, endln:45:41 + \_module_inst: work@Example (work@top.e2), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:45:5, endln:45:41 |vpiName:genblk3[17] |vpiFullName:work@top.e2.genblk3[17] |vpiGenScope: @@ -7789,7 +7789,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e2.genblk3[18]), line:26:13, endln:27:34 |vpiParent: - \_module: work@Example (work@top.e2), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:45:5, endln:45:41 + \_module_inst: work@Example (work@top.e2), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:45:5, endln:45:41 |vpiName:genblk3[18] |vpiFullName:work@top.e2.genblk3[18] |vpiGenScope: @@ -7810,7 +7810,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e2.genblk3[19]), line:26:13, endln:27:34 |vpiParent: - \_module: work@Example (work@top.e2), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:45:5, endln:45:41 + \_module_inst: work@Example (work@top.e2), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:45:5, endln:45:41 |vpiName:genblk3[19] |vpiFullName:work@top.e2.genblk3[19] |vpiGenScope: @@ -7831,7 +7831,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e2.genblk3[20]), line:26:13, endln:27:34 |vpiParent: - \_module: work@Example (work@top.e2), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:45:5, endln:45:41 + \_module_inst: work@Example (work@top.e2), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:45:5, endln:45:41 |vpiName:genblk3[20] |vpiFullName:work@top.e2.genblk3[20] |vpiGenScope: @@ -7852,7 +7852,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e2.genblk3[21]), line:26:13, endln:27:34 |vpiParent: - \_module: work@Example (work@top.e2), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:45:5, endln:45:41 + \_module_inst: work@Example (work@top.e2), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:45:5, endln:45:41 |vpiName:genblk3[21] |vpiFullName:work@top.e2.genblk3[21] |vpiGenScope: @@ -7873,7 +7873,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e2.genblk3[22]), line:26:13, endln:27:34 |vpiParent: - \_module: work@Example (work@top.e2), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:45:5, endln:45:41 + \_module_inst: work@Example (work@top.e2), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:45:5, endln:45:41 |vpiName:genblk3[22] |vpiFullName:work@top.e2.genblk3[22] |vpiGenScope: @@ -7894,7 +7894,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e2.genblk3[23]), line:26:13, endln:27:34 |vpiParent: - \_module: work@Example (work@top.e2), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:45:5, endln:45:41 + \_module_inst: work@Example (work@top.e2), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:45:5, endln:45:41 |vpiName:genblk3[23] |vpiFullName:work@top.e2.genblk3[23] |vpiGenScope: @@ -7915,7 +7915,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e2.genblk3[24]), line:26:13, endln:27:34 |vpiParent: - \_module: work@Example (work@top.e2), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:45:5, endln:45:41 + \_module_inst: work@Example (work@top.e2), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:45:5, endln:45:41 |vpiName:genblk3[24] |vpiFullName:work@top.e2.genblk3[24] |vpiGenScope: @@ -7936,7 +7936,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e2.genblk3[25]), line:26:13, endln:27:34 |vpiParent: - \_module: work@Example (work@top.e2), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:45:5, endln:45:41 + \_module_inst: work@Example (work@top.e2), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:45:5, endln:45:41 |vpiName:genblk3[25] |vpiFullName:work@top.e2.genblk3[25] |vpiGenScope: @@ -7957,7 +7957,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e2.genblk3[26]), line:26:13, endln:27:34 |vpiParent: - \_module: work@Example (work@top.e2), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:45:5, endln:45:41 + \_module_inst: work@Example (work@top.e2), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:45:5, endln:45:41 |vpiName:genblk3[26] |vpiFullName:work@top.e2.genblk3[26] |vpiGenScope: @@ -7978,7 +7978,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e2.genblk3[27]), line:26:13, endln:27:34 |vpiParent: - \_module: work@Example (work@top.e2), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:45:5, endln:45:41 + \_module_inst: work@Example (work@top.e2), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:45:5, endln:45:41 |vpiName:genblk3[27] |vpiFullName:work@top.e2.genblk3[27] |vpiGenScope: @@ -7999,7 +7999,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e2.genblk3[28]), line:26:13, endln:27:34 |vpiParent: - \_module: work@Example (work@top.e2), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:45:5, endln:45:41 + \_module_inst: work@Example (work@top.e2), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:45:5, endln:45:41 |vpiName:genblk3[28] |vpiFullName:work@top.e2.genblk3[28] |vpiGenScope: @@ -8020,7 +8020,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e2.genblk3[29]), line:26:13, endln:27:34 |vpiParent: - \_module: work@Example (work@top.e2), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:45:5, endln:45:41 + \_module_inst: work@Example (work@top.e2), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:45:5, endln:45:41 |vpiName:genblk3[29] |vpiFullName:work@top.e2.genblk3[29] |vpiGenScope: @@ -8041,7 +8041,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e2.genblk3[30]), line:26:13, endln:27:34 |vpiParent: - \_module: work@Example (work@top.e2), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:45:5, endln:45:41 + \_module_inst: work@Example (work@top.e2), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:45:5, endln:45:41 |vpiName:genblk3[30] |vpiFullName:work@top.e2.genblk3[30] |vpiGenScope: @@ -8062,7 +8062,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e2.genblk3[31]), line:26:13, endln:27:34 |vpiParent: - \_module: work@Example (work@top.e2), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:45:5, endln:45:41 + \_module_inst: work@Example (work@top.e2), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:45:5, endln:45:41 |vpiName:genblk3[31] |vpiFullName:work@top.e2.genblk3[31] |vpiGenScope: @@ -8083,7 +8083,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e2.genblk3[32]), line:26:13, endln:27:34 |vpiParent: - \_module: work@Example (work@top.e2), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:45:5, endln:45:41 + \_module_inst: work@Example (work@top.e2), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:45:5, endln:45:41 |vpiName:genblk3[32] |vpiFullName:work@top.e2.genblk3[32] |vpiGenScope: @@ -8104,7 +8104,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e2.genblk3[33]), line:26:13, endln:27:34 |vpiParent: - \_module: work@Example (work@top.e2), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:45:5, endln:45:41 + \_module_inst: work@Example (work@top.e2), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:45:5, endln:45:41 |vpiName:genblk3[33] |vpiFullName:work@top.e2.genblk3[33] |vpiGenScope: @@ -8125,7 +8125,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e2.genblk3[34]), line:26:13, endln:27:34 |vpiParent: - \_module: work@Example (work@top.e2), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:45:5, endln:45:41 + \_module_inst: work@Example (work@top.e2), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:45:5, endln:45:41 |vpiName:genblk3[34] |vpiFullName:work@top.e2.genblk3[34] |vpiGenScope: @@ -8146,7 +8146,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e2.genblk3[35]), line:26:13, endln:27:34 |vpiParent: - \_module: work@Example (work@top.e2), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:45:5, endln:45:41 + \_module_inst: work@Example (work@top.e2), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:45:5, endln:45:41 |vpiName:genblk3[35] |vpiFullName:work@top.e2.genblk3[35] |vpiGenScope: @@ -8167,7 +8167,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e2.genblk3[36]), line:26:13, endln:27:34 |vpiParent: - \_module: work@Example (work@top.e2), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:45:5, endln:45:41 + \_module_inst: work@Example (work@top.e2), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:45:5, endln:45:41 |vpiName:genblk3[36] |vpiFullName:work@top.e2.genblk3[36] |vpiGenScope: @@ -8188,7 +8188,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e2.genblk3[37]), line:26:13, endln:27:34 |vpiParent: - \_module: work@Example (work@top.e2), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:45:5, endln:45:41 + \_module_inst: work@Example (work@top.e2), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:45:5, endln:45:41 |vpiName:genblk3[37] |vpiFullName:work@top.e2.genblk3[37] |vpiGenScope: @@ -8209,7 +8209,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e2.genblk3[38]), line:26:13, endln:27:34 |vpiParent: - \_module: work@Example (work@top.e2), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:45:5, endln:45:41 + \_module_inst: work@Example (work@top.e2), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:45:5, endln:45:41 |vpiName:genblk3[38] |vpiFullName:work@top.e2.genblk3[38] |vpiGenScope: @@ -8230,7 +8230,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e2.genblk3[39]), line:26:13, endln:27:34 |vpiParent: - \_module: work@Example (work@top.e2), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:45:5, endln:45:41 + \_module_inst: work@Example (work@top.e2), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:45:5, endln:45:41 |vpiName:genblk3[39] |vpiFullName:work@top.e2.genblk3[39] |vpiGenScope: @@ -8251,7 +8251,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e2.genblk3[40]), line:26:13, endln:27:34 |vpiParent: - \_module: work@Example (work@top.e2), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:45:5, endln:45:41 + \_module_inst: work@Example (work@top.e2), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:45:5, endln:45:41 |vpiName:genblk3[40] |vpiFullName:work@top.e2.genblk3[40] |vpiGenScope: @@ -8272,7 +8272,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e2.genblk3[41]), line:26:13, endln:27:34 |vpiParent: - \_module: work@Example (work@top.e2), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:45:5, endln:45:41 + \_module_inst: work@Example (work@top.e2), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:45:5, endln:45:41 |vpiName:genblk3[41] |vpiFullName:work@top.e2.genblk3[41] |vpiGenScope: @@ -8293,7 +8293,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e2.genblk3[42]), line:26:13, endln:27:34 |vpiParent: - \_module: work@Example (work@top.e2), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:45:5, endln:45:41 + \_module_inst: work@Example (work@top.e2), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:45:5, endln:45:41 |vpiName:genblk3[42] |vpiFullName:work@top.e2.genblk3[42] |vpiGenScope: @@ -8314,7 +8314,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e2.genblk3[43]), line:26:13, endln:27:34 |vpiParent: - \_module: work@Example (work@top.e2), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:45:5, endln:45:41 + \_module_inst: work@Example (work@top.e2), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:45:5, endln:45:41 |vpiName:genblk3[43] |vpiFullName:work@top.e2.genblk3[43] |vpiGenScope: @@ -8335,7 +8335,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e2.genblk3[44]), line:26:13, endln:27:34 |vpiParent: - \_module: work@Example (work@top.e2), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:45:5, endln:45:41 + \_module_inst: work@Example (work@top.e2), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:45:5, endln:45:41 |vpiName:genblk3[44] |vpiFullName:work@top.e2.genblk3[44] |vpiGenScope: @@ -8356,7 +8356,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e2.genblk3[45]), line:26:13, endln:27:34 |vpiParent: - \_module: work@Example (work@top.e2), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:45:5, endln:45:41 + \_module_inst: work@Example (work@top.e2), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:45:5, endln:45:41 |vpiName:genblk3[45] |vpiFullName:work@top.e2.genblk3[45] |vpiGenScope: @@ -8377,7 +8377,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e2.genblk3[46]), line:26:13, endln:27:34 |vpiParent: - \_module: work@Example (work@top.e2), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:45:5, endln:45:41 + \_module_inst: work@Example (work@top.e2), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:45:5, endln:45:41 |vpiName:genblk3[46] |vpiFullName:work@top.e2.genblk3[46] |vpiGenScope: @@ -8398,7 +8398,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e2.genblk3[47]), line:26:13, endln:27:34 |vpiParent: - \_module: work@Example (work@top.e2), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:45:5, endln:45:41 + \_module_inst: work@Example (work@top.e2), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:45:5, endln:45:41 |vpiName:genblk3[47] |vpiFullName:work@top.e2.genblk3[47] |vpiGenScope: @@ -8419,7 +8419,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e2.genblk3[48]), line:26:13, endln:27:34 |vpiParent: - \_module: work@Example (work@top.e2), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:45:5, endln:45:41 + \_module_inst: work@Example (work@top.e2), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:45:5, endln:45:41 |vpiName:genblk3[48] |vpiFullName:work@top.e2.genblk3[48] |vpiGenScope: @@ -8440,7 +8440,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e2.genblk3[49]), line:26:13, endln:27:34 |vpiParent: - \_module: work@Example (work@top.e2), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:45:5, endln:45:41 + \_module_inst: work@Example (work@top.e2), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:45:5, endln:45:41 |vpiName:genblk3[49] |vpiFullName:work@top.e2.genblk3[49] |vpiGenScope: @@ -8461,7 +8461,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e2.genblk3[50]), line:26:13, endln:27:34 |vpiParent: - \_module: work@Example (work@top.e2), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:45:5, endln:45:41 + \_module_inst: work@Example (work@top.e2), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:45:5, endln:45:41 |vpiName:genblk3[50] |vpiFullName:work@top.e2.genblk3[50] |vpiGenScope: @@ -8482,7 +8482,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e2.genblk3[51]), line:26:13, endln:27:34 |vpiParent: - \_module: work@Example (work@top.e2), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:45:5, endln:45:41 + \_module_inst: work@Example (work@top.e2), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:45:5, endln:45:41 |vpiName:genblk3[51] |vpiFullName:work@top.e2.genblk3[51] |vpiGenScope: @@ -8503,7 +8503,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e2.genblk3[52]), line:26:13, endln:27:34 |vpiParent: - \_module: work@Example (work@top.e2), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:45:5, endln:45:41 + \_module_inst: work@Example (work@top.e2), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:45:5, endln:45:41 |vpiName:genblk3[52] |vpiFullName:work@top.e2.genblk3[52] |vpiGenScope: @@ -8524,7 +8524,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e2.genblk3[53]), line:26:13, endln:27:34 |vpiParent: - \_module: work@Example (work@top.e2), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:45:5, endln:45:41 + \_module_inst: work@Example (work@top.e2), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:45:5, endln:45:41 |vpiName:genblk3[53] |vpiFullName:work@top.e2.genblk3[53] |vpiGenScope: @@ -8545,7 +8545,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e2.genblk3[54]), line:26:13, endln:27:34 |vpiParent: - \_module: work@Example (work@top.e2), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:45:5, endln:45:41 + \_module_inst: work@Example (work@top.e2), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:45:5, endln:45:41 |vpiName:genblk3[54] |vpiFullName:work@top.e2.genblk3[54] |vpiGenScope: @@ -8566,7 +8566,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e2.genblk3[55]), line:26:13, endln:27:34 |vpiParent: - \_module: work@Example (work@top.e2), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:45:5, endln:45:41 + \_module_inst: work@Example (work@top.e2), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:45:5, endln:45:41 |vpiName:genblk3[55] |vpiFullName:work@top.e2.genblk3[55] |vpiGenScope: @@ -8587,7 +8587,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e2.genblk3[56]), line:26:13, endln:27:34 |vpiParent: - \_module: work@Example (work@top.e2), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:45:5, endln:45:41 + \_module_inst: work@Example (work@top.e2), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:45:5, endln:45:41 |vpiName:genblk3[56] |vpiFullName:work@top.e2.genblk3[56] |vpiGenScope: @@ -8608,7 +8608,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e2.genblk3[57]), line:26:13, endln:27:34 |vpiParent: - \_module: work@Example (work@top.e2), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:45:5, endln:45:41 + \_module_inst: work@Example (work@top.e2), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:45:5, endln:45:41 |vpiName:genblk3[57] |vpiFullName:work@top.e2.genblk3[57] |vpiGenScope: @@ -8629,7 +8629,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e2.genblk3[58]), line:26:13, endln:27:34 |vpiParent: - \_module: work@Example (work@top.e2), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:45:5, endln:45:41 + \_module_inst: work@Example (work@top.e2), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:45:5, endln:45:41 |vpiName:genblk3[58] |vpiFullName:work@top.e2.genblk3[58] |vpiGenScope: @@ -8650,7 +8650,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e2.genblk3[59]), line:26:13, endln:27:34 |vpiParent: - \_module: work@Example (work@top.e2), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:45:5, endln:45:41 + \_module_inst: work@Example (work@top.e2), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:45:5, endln:45:41 |vpiName:genblk3[59] |vpiFullName:work@top.e2.genblk3[59] |vpiGenScope: @@ -8671,7 +8671,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e2.genblk3[60]), line:26:13, endln:27:34 |vpiParent: - \_module: work@Example (work@top.e2), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:45:5, endln:45:41 + \_module_inst: work@Example (work@top.e2), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:45:5, endln:45:41 |vpiName:genblk3[60] |vpiFullName:work@top.e2.genblk3[60] |vpiGenScope: @@ -8692,7 +8692,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e2.genblk3[61]), line:26:13, endln:27:34 |vpiParent: - \_module: work@Example (work@top.e2), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:45:5, endln:45:41 + \_module_inst: work@Example (work@top.e2), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:45:5, endln:45:41 |vpiName:genblk3[61] |vpiFullName:work@top.e2.genblk3[61] |vpiGenScope: @@ -8713,7 +8713,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e2.genblk3[62]), line:26:13, endln:27:34 |vpiParent: - \_module: work@Example (work@top.e2), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:45:5, endln:45:41 + \_module_inst: work@Example (work@top.e2), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:45:5, endln:45:41 |vpiName:genblk3[62] |vpiFullName:work@top.e2.genblk3[62] |vpiGenScope: @@ -8734,7 +8734,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e2.genblk3[63]), line:26:13, endln:27:34 |vpiParent: - \_module: work@Example (work@top.e2), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:45:5, endln:45:41 + \_module_inst: work@Example (work@top.e2), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:45:5, endln:45:41 |vpiName:genblk3[63] |vpiFullName:work@top.e2.genblk3[63] |vpiGenScope: @@ -8755,7 +8755,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e2.genblk3[64]), line:26:13, endln:27:34 |vpiParent: - \_module: work@Example (work@top.e2), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:45:5, endln:45:41 + \_module_inst: work@Example (work@top.e2), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:45:5, endln:45:41 |vpiName:genblk3[64] |vpiFullName:work@top.e2.genblk3[64] |vpiGenScope: @@ -8776,7 +8776,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e2.genblk3[65]), line:26:13, endln:27:34 |vpiParent: - \_module: work@Example (work@top.e2), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:45:5, endln:45:41 + \_module_inst: work@Example (work@top.e2), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:45:5, endln:45:41 |vpiName:genblk3[65] |vpiFullName:work@top.e2.genblk3[65] |vpiGenScope: @@ -8797,7 +8797,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e2.genblk3[66]), line:26:13, endln:27:34 |vpiParent: - \_module: work@Example (work@top.e2), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:45:5, endln:45:41 + \_module_inst: work@Example (work@top.e2), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:45:5, endln:45:41 |vpiName:genblk3[66] |vpiFullName:work@top.e2.genblk3[66] |vpiGenScope: @@ -8818,7 +8818,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e2.genblk3[67]), line:26:13, endln:27:34 |vpiParent: - \_module: work@Example (work@top.e2), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:45:5, endln:45:41 + \_module_inst: work@Example (work@top.e2), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:45:5, endln:45:41 |vpiName:genblk3[67] |vpiFullName:work@top.e2.genblk3[67] |vpiGenScope: @@ -8839,7 +8839,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e2.genblk3[68]), line:26:13, endln:27:34 |vpiParent: - \_module: work@Example (work@top.e2), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:45:5, endln:45:41 + \_module_inst: work@Example (work@top.e2), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:45:5, endln:45:41 |vpiName:genblk3[68] |vpiFullName:work@top.e2.genblk3[68] |vpiGenScope: @@ -8860,7 +8860,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e2.genblk3[69]), line:26:13, endln:27:34 |vpiParent: - \_module: work@Example (work@top.e2), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:45:5, endln:45:41 + \_module_inst: work@Example (work@top.e2), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:45:5, endln:45:41 |vpiName:genblk3[69] |vpiFullName:work@top.e2.genblk3[69] |vpiGenScope: @@ -8881,7 +8881,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e2.genblk3[70]), line:26:13, endln:27:34 |vpiParent: - \_module: work@Example (work@top.e2), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:45:5, endln:45:41 + \_module_inst: work@Example (work@top.e2), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:45:5, endln:45:41 |vpiName:genblk3[70] |vpiFullName:work@top.e2.genblk3[70] |vpiGenScope: @@ -8902,7 +8902,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e2.genblk3[71]), line:26:13, endln:27:34 |vpiParent: - \_module: work@Example (work@top.e2), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:45:5, endln:45:41 + \_module_inst: work@Example (work@top.e2), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:45:5, endln:45:41 |vpiName:genblk3[71] |vpiFullName:work@top.e2.genblk3[71] |vpiGenScope: @@ -8923,7 +8923,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e2.genblk3[72]), line:26:13, endln:27:34 |vpiParent: - \_module: work@Example (work@top.e2), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:45:5, endln:45:41 + \_module_inst: work@Example (work@top.e2), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:45:5, endln:45:41 |vpiName:genblk3[72] |vpiFullName:work@top.e2.genblk3[72] |vpiGenScope: @@ -8944,7 +8944,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e2.genblk3[73]), line:26:13, endln:27:34 |vpiParent: - \_module: work@Example (work@top.e2), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:45:5, endln:45:41 + \_module_inst: work@Example (work@top.e2), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:45:5, endln:45:41 |vpiName:genblk3[73] |vpiFullName:work@top.e2.genblk3[73] |vpiGenScope: @@ -8965,7 +8965,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e2.genblk3[74]), line:26:13, endln:27:34 |vpiParent: - \_module: work@Example (work@top.e2), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:45:5, endln:45:41 + \_module_inst: work@Example (work@top.e2), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:45:5, endln:45:41 |vpiName:genblk3[74] |vpiFullName:work@top.e2.genblk3[74] |vpiGenScope: @@ -8986,7 +8986,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e2.genblk3[75]), line:26:13, endln:27:34 |vpiParent: - \_module: work@Example (work@top.e2), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:45:5, endln:45:41 + \_module_inst: work@Example (work@top.e2), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:45:5, endln:45:41 |vpiName:genblk3[75] |vpiFullName:work@top.e2.genblk3[75] |vpiGenScope: @@ -9007,7 +9007,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e2.genblk3[76]), line:26:13, endln:27:34 |vpiParent: - \_module: work@Example (work@top.e2), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:45:5, endln:45:41 + \_module_inst: work@Example (work@top.e2), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:45:5, endln:45:41 |vpiName:genblk3[76] |vpiFullName:work@top.e2.genblk3[76] |vpiGenScope: @@ -9028,7 +9028,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e2.genblk3[77]), line:26:13, endln:27:34 |vpiParent: - \_module: work@Example (work@top.e2), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:45:5, endln:45:41 + \_module_inst: work@Example (work@top.e2), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:45:5, endln:45:41 |vpiName:genblk3[77] |vpiFullName:work@top.e2.genblk3[77] |vpiGenScope: @@ -9049,7 +9049,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e2.genblk3[78]), line:26:13, endln:27:34 |vpiParent: - \_module: work@Example (work@top.e2), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:45:5, endln:45:41 + \_module_inst: work@Example (work@top.e2), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:45:5, endln:45:41 |vpiName:genblk3[78] |vpiFullName:work@top.e2.genblk3[78] |vpiGenScope: @@ -9104,16 +9104,16 @@ design: (work@top) |vpiFullName:work@top.e2.genblk3[78].genblk1.outC |vpiActual: \_logic_net: (work@top.e2.outC), line:1:28, endln:1:32 - |vpiModule: - \_module: work@Example (work@top.e3), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:46:5, endln:46:41 + |vpiModuleInst: + \_module_inst: work@Example (work@top.e3), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:46:5, endln:46:41 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:39:1, endln:86:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:39:1, endln:86:10 |vpiName:e3 |vpiFullName:work@top.e3 |vpiVariables: \_integer_var: (work@top.e3.j), line:30:13, endln:30:14 |vpiParent: - \_module: work@Example (work@top.e3), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:46:5, endln:46:41 + \_module_inst: work@Example (work@top.e3), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:46:5, endln:46:41 |vpiTypespec: \_integer_typespec: , line:30:5, endln:30:12 |vpiSigned:1 @@ -9123,7 +9123,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.e3.OUTPUT), line:2:15, endln:2:21 |vpiParent: - \_module: work@Example (work@top.e3), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:46:5, endln:46:41 + \_module_inst: work@Example (work@top.e3), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:46:5, endln:46:41 |STRING:FOO |vpiTypespec: \_string_typespec: @@ -9134,7 +9134,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:2:15, endln:2:29 |vpiParent: - \_module: work@Example (work@top.e3), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:46:5, endln:46:41 + \_module_inst: work@Example (work@top.e3), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:46:5, endln:46:41 |vpiOverriden:1 |vpiRhs: \_constant: , line:2:24, endln:2:29 @@ -9152,7 +9152,7 @@ design: (work@top) |vpiTaskFunc: \_function: (work@top.e3.flip), line:6:5, endln:9:16 |vpiParent: - \_module: work@Example (work@top.e3), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:46:5, endln:46:41 + \_module_inst: work@Example (work@top.e3), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:46:5, endln:46:41 |vpiName:flip |vpiFullName:work@top.e3.flip |vpiVisibility:1 @@ -9160,7 +9160,7 @@ design: (work@top) |vpiReturn: \_logic_var: , line:6:24, endln:6:30 |vpiParent: - \_module: work@Example (work@top.e3), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:46:5, endln:46:41 + \_module_inst: work@Example (work@top.e3), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:46:5, endln:46:41 |vpiIODecl: \_io_decl: (inp), line:7:22, endln:7:25 |vpiParent: @@ -9197,11 +9197,11 @@ design: (work@top) |vpiActual: \_logic_var: , line:6:24, endln:6:30 |vpiInstance: - \_module: work@Example (work@top.e3), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:46:5, endln:46:41 + \_module_inst: work@Example (work@top.e3), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:46:5, endln:46:41 |vpiNet: \_logic_net: (work@top.e3.outA), line:1:16, endln:1:20 |vpiParent: - \_module: work@Example (work@top.e3), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:46:5, endln:46:41 + \_module_inst: work@Example (work@top.e3), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:46:5, endln:46:41 |vpiTypespec: \_logic_typespec: , line:3:12, endln:3:23 |vpiRange: @@ -9228,7 +9228,7 @@ design: (work@top) |vpiNet: \_logic_net: (work@top.e3.outB), line:1:22, endln:1:26 |vpiParent: - \_module: work@Example (work@top.e3), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:46:5, endln:46:41 + \_module_inst: work@Example (work@top.e3), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:46:5, endln:46:41 |vpiTypespec: \_logic_typespec: , line:4:12, endln:4:23 |vpiRange: @@ -9255,7 +9255,7 @@ design: (work@top) |vpiNet: \_logic_net: (work@top.e3.outC), line:1:28, endln:1:32 |vpiParent: - \_module: work@Example (work@top.e3), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:46:5, endln:46:41 + \_module_inst: work@Example (work@top.e3), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:46:5, endln:46:41 |vpiTypespec: \_logic_typespec: , line:5:12, endln:5:15 |vpiName:outC @@ -9264,18 +9264,18 @@ design: (work@top) |vpiNet: \_logic_net: (work@top.e3.outD), line:1:34, endln:1:38 |vpiParent: - \_module: work@Example (work@top.e3), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:46:5, endln:46:41 + \_module_inst: work@Example (work@top.e3), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:46:5, endln:46:41 |vpiTypespec: \_logic_typespec: , line:5:12, endln:5:15 |vpiName:outD |vpiFullName:work@top.e3.outD |vpiNetType:48 |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:39:1, endln:86:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:39:1, endln:86:10 |vpiPort: \_port: (outA), line:1:16, endln:1:20 |vpiParent: - \_module: work@Example (work@top.e3), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:46:5, endln:46:41 + \_module_inst: work@Example (work@top.e3), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:46:5, endln:46:41 |vpiName:outA |vpiDirection:2 |vpiHighConn: @@ -9317,11 +9317,11 @@ design: (work@top) |UINT:0 |vpiConstType:9 |vpiInstance: - \_module: work@Example (work@top.e3), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:46:5, endln:46:41 + \_module_inst: work@Example (work@top.e3), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:46:5, endln:46:41 |vpiPort: \_port: (outB), line:1:22, endln:1:26 |vpiParent: - \_module: work@Example (work@top.e3), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:46:5, endln:46:41 + \_module_inst: work@Example (work@top.e3), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:46:5, endln:46:41 |vpiName:outB |vpiDirection:2 |vpiHighConn: @@ -9363,11 +9363,11 @@ design: (work@top) |UINT:0 |vpiConstType:9 |vpiInstance: - \_module: work@Example (work@top.e3), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:46:5, endln:46:41 + \_module_inst: work@Example (work@top.e3), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:46:5, endln:46:41 |vpiPort: \_port: (outC), line:1:28, endln:1:32 |vpiParent: - \_module: work@Example (work@top.e3), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:46:5, endln:46:41 + \_module_inst: work@Example (work@top.e3), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:46:5, endln:46:41 |vpiName:outC |vpiDirection:2 |vpiHighConn: @@ -9389,11 +9389,11 @@ design: (work@top) |vpiTypedef: \_logic_typespec: , line:5:12, endln:5:15 |vpiInstance: - \_module: work@Example (work@top.e3), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:46:5, endln:46:41 + \_module_inst: work@Example (work@top.e3), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:46:5, endln:46:41 |vpiPort: \_port: (outD), line:1:34, endln:1:38 |vpiParent: - \_module: work@Example (work@top.e3), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:46:5, endln:46:41 + \_module_inst: work@Example (work@top.e3), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:46:5, endln:46:41 |vpiName:outD |vpiDirection:2 |vpiHighConn: @@ -9415,11 +9415,11 @@ design: (work@top) |vpiTypedef: \_logic_typespec: , line:5:12, endln:5:15 |vpiInstance: - \_module: work@Example (work@top.e3), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:46:5, endln:46:41 + \_module_inst: work@Example (work@top.e3), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:46:5, endln:46:41 |vpiProcess: \_initial: , line:31:5, endln:36:8 |vpiParent: - \_module: work@Example (work@top.e3), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:46:5, endln:46:41 + \_module_inst: work@Example (work@top.e3), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:46:5, endln:46:41 |vpiStmt: \_begin: (work@top.e3), line:31:13, endln:36:8 |vpiParent: @@ -9591,7 +9591,7 @@ design: (work@top) |vpiProcess: \_initial: , line:24:9, endln:24:26 |vpiParent: - \_module: work@Example (work@top.e3), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:46:5, endln:46:41 + \_module_inst: work@Example (work@top.e3), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:46:5, endln:46:41 |vpiStmt: \_assignment: , line:24:17, endln:24:25 |vpiParent: @@ -9611,7 +9611,7 @@ design: (work@top) |vpiProcess: \_initial: , line:24:9, endln:24:26 |vpiParent: - \_module: work@Example (work@top.e3), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:46:5, endln:46:41 + \_module_inst: work@Example (work@top.e3), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:46:5, endln:46:41 |vpiStmt: \_assignment: , line:24:17, endln:24:25 |vpiParent: @@ -9631,7 +9631,7 @@ design: (work@top) |vpiProcess: \_initial: , line:24:9, endln:24:26 |vpiParent: - \_module: work@Example (work@top.e3), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:46:5, endln:46:41 + \_module_inst: work@Example (work@top.e3), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:46:5, endln:46:41 |vpiStmt: \_assignment: , line:24:17, endln:24:25 |vpiParent: @@ -9651,7 +9651,7 @@ design: (work@top) |vpiProcess: \_initial: , line:24:9, endln:24:26 |vpiParent: - \_module: work@Example (work@top.e3), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:46:5, endln:46:41 + \_module_inst: work@Example (work@top.e3), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:46:5, endln:46:41 |vpiStmt: \_assignment: , line:24:17, endln:24:25 |vpiParent: @@ -9671,7 +9671,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e3.genblk1), line:12:9, endln:15:29 |vpiParent: - \_module: work@Example (work@top.e3), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:46:5, endln:46:41 + \_module_inst: work@Example (work@top.e3), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:46:5, endln:46:41 |vpiName:genblk1 |vpiFullName:work@top.e3.genblk1 |vpiGenScope: @@ -9706,7 +9706,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e3.genblk2), line:17:9, endln:21:16 |vpiParent: - \_module: work@Example (work@top.e3), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:46:5, endln:46:41 + \_module_inst: work@Example (work@top.e3), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:46:5, endln:46:41 |vpiName:genblk2 |vpiFullName:work@top.e3.genblk2 |vpiGenScope: @@ -9737,7 +9737,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e3.genblk3[0]), line:26:13, endln:27:34 |vpiParent: - \_module: work@Example (work@top.e3), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:46:5, endln:46:41 + \_module_inst: work@Example (work@top.e3), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:46:5, endln:46:41 |vpiName:genblk3[0] |vpiFullName:work@top.e3.genblk3[0] |vpiGenScope: @@ -9758,7 +9758,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e3.genblk3[1]), line:26:13, endln:27:34 |vpiParent: - \_module: work@Example (work@top.e3), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:46:5, endln:46:41 + \_module_inst: work@Example (work@top.e3), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:46:5, endln:46:41 |vpiName:genblk3[1] |vpiFullName:work@top.e3.genblk3[1] |vpiGenScope: @@ -9779,7 +9779,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e3.genblk3[2]), line:26:13, endln:27:34 |vpiParent: - \_module: work@Example (work@top.e3), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:46:5, endln:46:41 + \_module_inst: work@Example (work@top.e3), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:46:5, endln:46:41 |vpiName:genblk3[2] |vpiFullName:work@top.e3.genblk3[2] |vpiGenScope: @@ -9800,7 +9800,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e3.genblk3[3]), line:26:13, endln:27:34 |vpiParent: - \_module: work@Example (work@top.e3), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:46:5, endln:46:41 + \_module_inst: work@Example (work@top.e3), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:46:5, endln:46:41 |vpiName:genblk3[3] |vpiFullName:work@top.e3.genblk3[3] |vpiGenScope: @@ -9821,7 +9821,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e3.genblk3[4]), line:26:13, endln:27:34 |vpiParent: - \_module: work@Example (work@top.e3), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:46:5, endln:46:41 + \_module_inst: work@Example (work@top.e3), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:46:5, endln:46:41 |vpiName:genblk3[4] |vpiFullName:work@top.e3.genblk3[4] |vpiGenScope: @@ -9842,7 +9842,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e3.genblk3[5]), line:26:13, endln:27:34 |vpiParent: - \_module: work@Example (work@top.e3), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:46:5, endln:46:41 + \_module_inst: work@Example (work@top.e3), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:46:5, endln:46:41 |vpiName:genblk3[5] |vpiFullName:work@top.e3.genblk3[5] |vpiGenScope: @@ -9863,7 +9863,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e3.genblk3[6]), line:26:13, endln:27:34 |vpiParent: - \_module: work@Example (work@top.e3), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:46:5, endln:46:41 + \_module_inst: work@Example (work@top.e3), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:46:5, endln:46:41 |vpiName:genblk3[6] |vpiFullName:work@top.e3.genblk3[6] |vpiGenScope: @@ -9884,7 +9884,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e3.genblk3[7]), line:26:13, endln:27:34 |vpiParent: - \_module: work@Example (work@top.e3), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:46:5, endln:46:41 + \_module_inst: work@Example (work@top.e3), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:46:5, endln:46:41 |vpiName:genblk3[7] |vpiFullName:work@top.e3.genblk3[7] |vpiGenScope: @@ -9905,7 +9905,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e3.genblk3[8]), line:26:13, endln:27:34 |vpiParent: - \_module: work@Example (work@top.e3), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:46:5, endln:46:41 + \_module_inst: work@Example (work@top.e3), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:46:5, endln:46:41 |vpiName:genblk3[8] |vpiFullName:work@top.e3.genblk3[8] |vpiGenScope: @@ -9926,7 +9926,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e3.genblk3[9]), line:26:13, endln:27:34 |vpiParent: - \_module: work@Example (work@top.e3), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:46:5, endln:46:41 + \_module_inst: work@Example (work@top.e3), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:46:5, endln:46:41 |vpiName:genblk3[9] |vpiFullName:work@top.e3.genblk3[9] |vpiGenScope: @@ -9947,7 +9947,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e3.genblk3[10]), line:26:13, endln:27:34 |vpiParent: - \_module: work@Example (work@top.e3), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:46:5, endln:46:41 + \_module_inst: work@Example (work@top.e3), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:46:5, endln:46:41 |vpiName:genblk3[10] |vpiFullName:work@top.e3.genblk3[10] |vpiGenScope: @@ -9968,7 +9968,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e3.genblk3[11]), line:26:13, endln:27:34 |vpiParent: - \_module: work@Example (work@top.e3), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:46:5, endln:46:41 + \_module_inst: work@Example (work@top.e3), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:46:5, endln:46:41 |vpiName:genblk3[11] |vpiFullName:work@top.e3.genblk3[11] |vpiGenScope: @@ -9989,7 +9989,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e3.genblk3[12]), line:26:13, endln:27:34 |vpiParent: - \_module: work@Example (work@top.e3), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:46:5, endln:46:41 + \_module_inst: work@Example (work@top.e3), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:46:5, endln:46:41 |vpiName:genblk3[12] |vpiFullName:work@top.e3.genblk3[12] |vpiGenScope: @@ -10010,7 +10010,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e3.genblk3[13]), line:26:13, endln:27:34 |vpiParent: - \_module: work@Example (work@top.e3), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:46:5, endln:46:41 + \_module_inst: work@Example (work@top.e3), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:46:5, endln:46:41 |vpiName:genblk3[13] |vpiFullName:work@top.e3.genblk3[13] |vpiGenScope: @@ -10031,7 +10031,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e3.genblk3[14]), line:26:13, endln:27:34 |vpiParent: - \_module: work@Example (work@top.e3), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:46:5, endln:46:41 + \_module_inst: work@Example (work@top.e3), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:46:5, endln:46:41 |vpiName:genblk3[14] |vpiFullName:work@top.e3.genblk3[14] |vpiGenScope: @@ -10052,7 +10052,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e3.genblk3[15]), line:26:13, endln:27:34 |vpiParent: - \_module: work@Example (work@top.e3), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:46:5, endln:46:41 + \_module_inst: work@Example (work@top.e3), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:46:5, endln:46:41 |vpiName:genblk3[15] |vpiFullName:work@top.e3.genblk3[15] |vpiGenScope: @@ -10073,7 +10073,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e3.genblk3[16]), line:26:13, endln:27:34 |vpiParent: - \_module: work@Example (work@top.e3), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:46:5, endln:46:41 + \_module_inst: work@Example (work@top.e3), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:46:5, endln:46:41 |vpiName:genblk3[16] |vpiFullName:work@top.e3.genblk3[16] |vpiGenScope: @@ -10094,7 +10094,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e3.genblk3[17]), line:26:13, endln:27:34 |vpiParent: - \_module: work@Example (work@top.e3), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:46:5, endln:46:41 + \_module_inst: work@Example (work@top.e3), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:46:5, endln:46:41 |vpiName:genblk3[17] |vpiFullName:work@top.e3.genblk3[17] |vpiGenScope: @@ -10115,7 +10115,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e3.genblk3[18]), line:26:13, endln:27:34 |vpiParent: - \_module: work@Example (work@top.e3), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:46:5, endln:46:41 + \_module_inst: work@Example (work@top.e3), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:46:5, endln:46:41 |vpiName:genblk3[18] |vpiFullName:work@top.e3.genblk3[18] |vpiGenScope: @@ -10136,7 +10136,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e3.genblk3[19]), line:26:13, endln:27:34 |vpiParent: - \_module: work@Example (work@top.e3), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:46:5, endln:46:41 + \_module_inst: work@Example (work@top.e3), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:46:5, endln:46:41 |vpiName:genblk3[19] |vpiFullName:work@top.e3.genblk3[19] |vpiGenScope: @@ -10157,7 +10157,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e3.genblk3[20]), line:26:13, endln:27:34 |vpiParent: - \_module: work@Example (work@top.e3), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:46:5, endln:46:41 + \_module_inst: work@Example (work@top.e3), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:46:5, endln:46:41 |vpiName:genblk3[20] |vpiFullName:work@top.e3.genblk3[20] |vpiGenScope: @@ -10178,7 +10178,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e3.genblk3[21]), line:26:13, endln:27:34 |vpiParent: - \_module: work@Example (work@top.e3), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:46:5, endln:46:41 + \_module_inst: work@Example (work@top.e3), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:46:5, endln:46:41 |vpiName:genblk3[21] |vpiFullName:work@top.e3.genblk3[21] |vpiGenScope: @@ -10199,7 +10199,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e3.genblk3[22]), line:26:13, endln:27:34 |vpiParent: - \_module: work@Example (work@top.e3), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:46:5, endln:46:41 + \_module_inst: work@Example (work@top.e3), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:46:5, endln:46:41 |vpiName:genblk3[22] |vpiFullName:work@top.e3.genblk3[22] |vpiGenScope: @@ -10220,7 +10220,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e3.genblk3[23]), line:26:13, endln:27:34 |vpiParent: - \_module: work@Example (work@top.e3), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:46:5, endln:46:41 + \_module_inst: work@Example (work@top.e3), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:46:5, endln:46:41 |vpiName:genblk3[23] |vpiFullName:work@top.e3.genblk3[23] |vpiGenScope: @@ -10241,7 +10241,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e3.genblk3[24]), line:26:13, endln:27:34 |vpiParent: - \_module: work@Example (work@top.e3), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:46:5, endln:46:41 + \_module_inst: work@Example (work@top.e3), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:46:5, endln:46:41 |vpiName:genblk3[24] |vpiFullName:work@top.e3.genblk3[24] |vpiGenScope: @@ -10262,7 +10262,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e3.genblk3[25]), line:26:13, endln:27:34 |vpiParent: - \_module: work@Example (work@top.e3), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:46:5, endln:46:41 + \_module_inst: work@Example (work@top.e3), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:46:5, endln:46:41 |vpiName:genblk3[25] |vpiFullName:work@top.e3.genblk3[25] |vpiGenScope: @@ -10283,7 +10283,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e3.genblk3[26]), line:26:13, endln:27:34 |vpiParent: - \_module: work@Example (work@top.e3), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:46:5, endln:46:41 + \_module_inst: work@Example (work@top.e3), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:46:5, endln:46:41 |vpiName:genblk3[26] |vpiFullName:work@top.e3.genblk3[26] |vpiGenScope: @@ -10304,7 +10304,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e3.genblk3[27]), line:26:13, endln:27:34 |vpiParent: - \_module: work@Example (work@top.e3), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:46:5, endln:46:41 + \_module_inst: work@Example (work@top.e3), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:46:5, endln:46:41 |vpiName:genblk3[27] |vpiFullName:work@top.e3.genblk3[27] |vpiGenScope: @@ -10325,7 +10325,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e3.genblk3[28]), line:26:13, endln:27:34 |vpiParent: - \_module: work@Example (work@top.e3), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:46:5, endln:46:41 + \_module_inst: work@Example (work@top.e3), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:46:5, endln:46:41 |vpiName:genblk3[28] |vpiFullName:work@top.e3.genblk3[28] |vpiGenScope: @@ -10346,7 +10346,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e3.genblk3[29]), line:26:13, endln:27:34 |vpiParent: - \_module: work@Example (work@top.e3), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:46:5, endln:46:41 + \_module_inst: work@Example (work@top.e3), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:46:5, endln:46:41 |vpiName:genblk3[29] |vpiFullName:work@top.e3.genblk3[29] |vpiGenScope: @@ -10367,7 +10367,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e3.genblk3[30]), line:26:13, endln:27:34 |vpiParent: - \_module: work@Example (work@top.e3), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:46:5, endln:46:41 + \_module_inst: work@Example (work@top.e3), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:46:5, endln:46:41 |vpiName:genblk3[30] |vpiFullName:work@top.e3.genblk3[30] |vpiGenScope: @@ -10388,7 +10388,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e3.genblk3[31]), line:26:13, endln:27:34 |vpiParent: - \_module: work@Example (work@top.e3), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:46:5, endln:46:41 + \_module_inst: work@Example (work@top.e3), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:46:5, endln:46:41 |vpiName:genblk3[31] |vpiFullName:work@top.e3.genblk3[31] |vpiGenScope: @@ -10409,7 +10409,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e3.genblk3[32]), line:26:13, endln:27:34 |vpiParent: - \_module: work@Example (work@top.e3), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:46:5, endln:46:41 + \_module_inst: work@Example (work@top.e3), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:46:5, endln:46:41 |vpiName:genblk3[32] |vpiFullName:work@top.e3.genblk3[32] |vpiGenScope: @@ -10430,7 +10430,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e3.genblk3[33]), line:26:13, endln:27:34 |vpiParent: - \_module: work@Example (work@top.e3), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:46:5, endln:46:41 + \_module_inst: work@Example (work@top.e3), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:46:5, endln:46:41 |vpiName:genblk3[33] |vpiFullName:work@top.e3.genblk3[33] |vpiGenScope: @@ -10451,7 +10451,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e3.genblk3[34]), line:26:13, endln:27:34 |vpiParent: - \_module: work@Example (work@top.e3), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:46:5, endln:46:41 + \_module_inst: work@Example (work@top.e3), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:46:5, endln:46:41 |vpiName:genblk3[34] |vpiFullName:work@top.e3.genblk3[34] |vpiGenScope: @@ -10472,7 +10472,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e3.genblk3[35]), line:26:13, endln:27:34 |vpiParent: - \_module: work@Example (work@top.e3), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:46:5, endln:46:41 + \_module_inst: work@Example (work@top.e3), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:46:5, endln:46:41 |vpiName:genblk3[35] |vpiFullName:work@top.e3.genblk3[35] |vpiGenScope: @@ -10493,7 +10493,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e3.genblk3[36]), line:26:13, endln:27:34 |vpiParent: - \_module: work@Example (work@top.e3), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:46:5, endln:46:41 + \_module_inst: work@Example (work@top.e3), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:46:5, endln:46:41 |vpiName:genblk3[36] |vpiFullName:work@top.e3.genblk3[36] |vpiGenScope: @@ -10514,7 +10514,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e3.genblk3[37]), line:26:13, endln:27:34 |vpiParent: - \_module: work@Example (work@top.e3), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:46:5, endln:46:41 + \_module_inst: work@Example (work@top.e3), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:46:5, endln:46:41 |vpiName:genblk3[37] |vpiFullName:work@top.e3.genblk3[37] |vpiGenScope: @@ -10535,7 +10535,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e3.genblk3[38]), line:26:13, endln:27:34 |vpiParent: - \_module: work@Example (work@top.e3), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:46:5, endln:46:41 + \_module_inst: work@Example (work@top.e3), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:46:5, endln:46:41 |vpiName:genblk3[38] |vpiFullName:work@top.e3.genblk3[38] |vpiGenScope: @@ -10556,7 +10556,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e3.genblk3[39]), line:26:13, endln:27:34 |vpiParent: - \_module: work@Example (work@top.e3), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:46:5, endln:46:41 + \_module_inst: work@Example (work@top.e3), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:46:5, endln:46:41 |vpiName:genblk3[39] |vpiFullName:work@top.e3.genblk3[39] |vpiGenScope: @@ -10577,7 +10577,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e3.genblk3[40]), line:26:13, endln:27:34 |vpiParent: - \_module: work@Example (work@top.e3), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:46:5, endln:46:41 + \_module_inst: work@Example (work@top.e3), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:46:5, endln:46:41 |vpiName:genblk3[40] |vpiFullName:work@top.e3.genblk3[40] |vpiGenScope: @@ -10598,7 +10598,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e3.genblk3[41]), line:26:13, endln:27:34 |vpiParent: - \_module: work@Example (work@top.e3), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:46:5, endln:46:41 + \_module_inst: work@Example (work@top.e3), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:46:5, endln:46:41 |vpiName:genblk3[41] |vpiFullName:work@top.e3.genblk3[41] |vpiGenScope: @@ -10619,7 +10619,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e3.genblk3[42]), line:26:13, endln:27:34 |vpiParent: - \_module: work@Example (work@top.e3), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:46:5, endln:46:41 + \_module_inst: work@Example (work@top.e3), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:46:5, endln:46:41 |vpiName:genblk3[42] |vpiFullName:work@top.e3.genblk3[42] |vpiGenScope: @@ -10640,7 +10640,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e3.genblk3[43]), line:26:13, endln:27:34 |vpiParent: - \_module: work@Example (work@top.e3), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:46:5, endln:46:41 + \_module_inst: work@Example (work@top.e3), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:46:5, endln:46:41 |vpiName:genblk3[43] |vpiFullName:work@top.e3.genblk3[43] |vpiGenScope: @@ -10661,7 +10661,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e3.genblk3[44]), line:26:13, endln:27:34 |vpiParent: - \_module: work@Example (work@top.e3), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:46:5, endln:46:41 + \_module_inst: work@Example (work@top.e3), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:46:5, endln:46:41 |vpiName:genblk3[44] |vpiFullName:work@top.e3.genblk3[44] |vpiGenScope: @@ -10682,7 +10682,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e3.genblk3[45]), line:26:13, endln:27:34 |vpiParent: - \_module: work@Example (work@top.e3), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:46:5, endln:46:41 + \_module_inst: work@Example (work@top.e3), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:46:5, endln:46:41 |vpiName:genblk3[45] |vpiFullName:work@top.e3.genblk3[45] |vpiGenScope: @@ -10703,7 +10703,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e3.genblk3[46]), line:26:13, endln:27:34 |vpiParent: - \_module: work@Example (work@top.e3), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:46:5, endln:46:41 + \_module_inst: work@Example (work@top.e3), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:46:5, endln:46:41 |vpiName:genblk3[46] |vpiFullName:work@top.e3.genblk3[46] |vpiGenScope: @@ -10724,7 +10724,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e3.genblk3[47]), line:26:13, endln:27:34 |vpiParent: - \_module: work@Example (work@top.e3), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:46:5, endln:46:41 + \_module_inst: work@Example (work@top.e3), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:46:5, endln:46:41 |vpiName:genblk3[47] |vpiFullName:work@top.e3.genblk3[47] |vpiGenScope: @@ -10745,7 +10745,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e3.genblk3[48]), line:26:13, endln:27:34 |vpiParent: - \_module: work@Example (work@top.e3), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:46:5, endln:46:41 + \_module_inst: work@Example (work@top.e3), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:46:5, endln:46:41 |vpiName:genblk3[48] |vpiFullName:work@top.e3.genblk3[48] |vpiGenScope: @@ -10766,7 +10766,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e3.genblk3[49]), line:26:13, endln:27:34 |vpiParent: - \_module: work@Example (work@top.e3), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:46:5, endln:46:41 + \_module_inst: work@Example (work@top.e3), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:46:5, endln:46:41 |vpiName:genblk3[49] |vpiFullName:work@top.e3.genblk3[49] |vpiGenScope: @@ -10787,7 +10787,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e3.genblk3[50]), line:26:13, endln:27:34 |vpiParent: - \_module: work@Example (work@top.e3), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:46:5, endln:46:41 + \_module_inst: work@Example (work@top.e3), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:46:5, endln:46:41 |vpiName:genblk3[50] |vpiFullName:work@top.e3.genblk3[50] |vpiGenScope: @@ -10808,7 +10808,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e3.genblk3[51]), line:26:13, endln:27:34 |vpiParent: - \_module: work@Example (work@top.e3), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:46:5, endln:46:41 + \_module_inst: work@Example (work@top.e3), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:46:5, endln:46:41 |vpiName:genblk3[51] |vpiFullName:work@top.e3.genblk3[51] |vpiGenScope: @@ -10829,7 +10829,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e3.genblk3[52]), line:26:13, endln:27:34 |vpiParent: - \_module: work@Example (work@top.e3), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:46:5, endln:46:41 + \_module_inst: work@Example (work@top.e3), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:46:5, endln:46:41 |vpiName:genblk3[52] |vpiFullName:work@top.e3.genblk3[52] |vpiGenScope: @@ -10850,7 +10850,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e3.genblk3[53]), line:26:13, endln:27:34 |vpiParent: - \_module: work@Example (work@top.e3), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:46:5, endln:46:41 + \_module_inst: work@Example (work@top.e3), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:46:5, endln:46:41 |vpiName:genblk3[53] |vpiFullName:work@top.e3.genblk3[53] |vpiGenScope: @@ -10871,7 +10871,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e3.genblk3[54]), line:26:13, endln:27:34 |vpiParent: - \_module: work@Example (work@top.e3), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:46:5, endln:46:41 + \_module_inst: work@Example (work@top.e3), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:46:5, endln:46:41 |vpiName:genblk3[54] |vpiFullName:work@top.e3.genblk3[54] |vpiGenScope: @@ -10892,7 +10892,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e3.genblk3[55]), line:26:13, endln:27:34 |vpiParent: - \_module: work@Example (work@top.e3), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:46:5, endln:46:41 + \_module_inst: work@Example (work@top.e3), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:46:5, endln:46:41 |vpiName:genblk3[55] |vpiFullName:work@top.e3.genblk3[55] |vpiGenScope: @@ -10913,7 +10913,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e3.genblk3[56]), line:26:13, endln:27:34 |vpiParent: - \_module: work@Example (work@top.e3), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:46:5, endln:46:41 + \_module_inst: work@Example (work@top.e3), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:46:5, endln:46:41 |vpiName:genblk3[56] |vpiFullName:work@top.e3.genblk3[56] |vpiGenScope: @@ -10934,7 +10934,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e3.genblk3[57]), line:26:13, endln:27:34 |vpiParent: - \_module: work@Example (work@top.e3), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:46:5, endln:46:41 + \_module_inst: work@Example (work@top.e3), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:46:5, endln:46:41 |vpiName:genblk3[57] |vpiFullName:work@top.e3.genblk3[57] |vpiGenScope: @@ -10955,7 +10955,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e3.genblk3[58]), line:26:13, endln:27:34 |vpiParent: - \_module: work@Example (work@top.e3), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:46:5, endln:46:41 + \_module_inst: work@Example (work@top.e3), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:46:5, endln:46:41 |vpiName:genblk3[58] |vpiFullName:work@top.e3.genblk3[58] |vpiGenScope: @@ -10976,7 +10976,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e3.genblk3[59]), line:26:13, endln:27:34 |vpiParent: - \_module: work@Example (work@top.e3), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:46:5, endln:46:41 + \_module_inst: work@Example (work@top.e3), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:46:5, endln:46:41 |vpiName:genblk3[59] |vpiFullName:work@top.e3.genblk3[59] |vpiGenScope: @@ -10997,7 +10997,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e3.genblk3[60]), line:26:13, endln:27:34 |vpiParent: - \_module: work@Example (work@top.e3), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:46:5, endln:46:41 + \_module_inst: work@Example (work@top.e3), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:46:5, endln:46:41 |vpiName:genblk3[60] |vpiFullName:work@top.e3.genblk3[60] |vpiGenScope: @@ -11018,7 +11018,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e3.genblk3[61]), line:26:13, endln:27:34 |vpiParent: - \_module: work@Example (work@top.e3), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:46:5, endln:46:41 + \_module_inst: work@Example (work@top.e3), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:46:5, endln:46:41 |vpiName:genblk3[61] |vpiFullName:work@top.e3.genblk3[61] |vpiGenScope: @@ -11039,7 +11039,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e3.genblk3[62]), line:26:13, endln:27:34 |vpiParent: - \_module: work@Example (work@top.e3), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:46:5, endln:46:41 + \_module_inst: work@Example (work@top.e3), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:46:5, endln:46:41 |vpiName:genblk3[62] |vpiFullName:work@top.e3.genblk3[62] |vpiGenScope: @@ -11060,7 +11060,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e3.genblk3[63]), line:26:13, endln:27:34 |vpiParent: - \_module: work@Example (work@top.e3), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:46:5, endln:46:41 + \_module_inst: work@Example (work@top.e3), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:46:5, endln:46:41 |vpiName:genblk3[63] |vpiFullName:work@top.e3.genblk3[63] |vpiGenScope: @@ -11081,7 +11081,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e3.genblk3[64]), line:26:13, endln:27:34 |vpiParent: - \_module: work@Example (work@top.e3), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:46:5, endln:46:41 + \_module_inst: work@Example (work@top.e3), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:46:5, endln:46:41 |vpiName:genblk3[64] |vpiFullName:work@top.e3.genblk3[64] |vpiGenScope: @@ -11099,16 +11099,16 @@ design: (work@top) |vpiLocalParam:1 |vpiName:i |vpiFullName:work@top.e3.genblk3[64].i - |vpiModule: - \_module: work@Example (work@top.e4), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:47:5, endln:47:41 + |vpiModuleInst: + \_module_inst: work@Example (work@top.e4), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:47:5, endln:47:41 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:39:1, endln:86:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:39:1, endln:86:10 |vpiName:e4 |vpiFullName:work@top.e4 |vpiVariables: \_integer_var: (work@top.e4.j), line:30:13, endln:30:14 |vpiParent: - \_module: work@Example (work@top.e4), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:47:5, endln:47:41 + \_module_inst: work@Example (work@top.e4), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:47:5, endln:47:41 |vpiTypespec: \_integer_typespec: , line:30:5, endln:30:12 |vpiSigned:1 @@ -11118,7 +11118,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.e4.OUTPUT), line:2:15, endln:2:21 |vpiParent: - \_module: work@Example (work@top.e4), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:47:5, endln:47:41 + \_module_inst: work@Example (work@top.e4), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:47:5, endln:47:41 |STRING:FOO |vpiTypespec: \_string_typespec: @@ -11129,7 +11129,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:2:15, endln:2:29 |vpiParent: - \_module: work@Example (work@top.e4), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:47:5, endln:47:41 + \_module_inst: work@Example (work@top.e4), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:47:5, endln:47:41 |vpiOverriden:1 |vpiRhs: \_constant: , line:2:24, endln:2:29 @@ -11147,7 +11147,7 @@ design: (work@top) |vpiTaskFunc: \_function: (work@top.e4.flip), line:6:5, endln:9:16 |vpiParent: - \_module: work@Example (work@top.e4), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:47:5, endln:47:41 + \_module_inst: work@Example (work@top.e4), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:47:5, endln:47:41 |vpiName:flip |vpiFullName:work@top.e4.flip |vpiVisibility:1 @@ -11155,7 +11155,7 @@ design: (work@top) |vpiReturn: \_logic_var: , line:6:24, endln:6:30 |vpiParent: - \_module: work@Example (work@top.e4), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:47:5, endln:47:41 + \_module_inst: work@Example (work@top.e4), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:47:5, endln:47:41 |vpiIODecl: \_io_decl: (inp), line:7:22, endln:7:25 |vpiParent: @@ -11192,11 +11192,11 @@ design: (work@top) |vpiActual: \_logic_var: , line:6:24, endln:6:30 |vpiInstance: - \_module: work@Example (work@top.e4), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:47:5, endln:47:41 + \_module_inst: work@Example (work@top.e4), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:47:5, endln:47:41 |vpiNet: \_logic_net: (work@top.e4.outA), line:1:16, endln:1:20 |vpiParent: - \_module: work@Example (work@top.e4), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:47:5, endln:47:41 + \_module_inst: work@Example (work@top.e4), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:47:5, endln:47:41 |vpiTypespec: \_logic_typespec: , line:3:12, endln:3:23 |vpiRange: @@ -11223,7 +11223,7 @@ design: (work@top) |vpiNet: \_logic_net: (work@top.e4.outB), line:1:22, endln:1:26 |vpiParent: - \_module: work@Example (work@top.e4), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:47:5, endln:47:41 + \_module_inst: work@Example (work@top.e4), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:47:5, endln:47:41 |vpiTypespec: \_logic_typespec: , line:4:12, endln:4:23 |vpiRange: @@ -11250,7 +11250,7 @@ design: (work@top) |vpiNet: \_logic_net: (work@top.e4.outC), line:1:28, endln:1:32 |vpiParent: - \_module: work@Example (work@top.e4), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:47:5, endln:47:41 + \_module_inst: work@Example (work@top.e4), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:47:5, endln:47:41 |vpiTypespec: \_logic_typespec: , line:5:12, endln:5:15 |vpiName:outC @@ -11259,18 +11259,18 @@ design: (work@top) |vpiNet: \_logic_net: (work@top.e4.outD), line:1:34, endln:1:38 |vpiParent: - \_module: work@Example (work@top.e4), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:47:5, endln:47:41 + \_module_inst: work@Example (work@top.e4), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:47:5, endln:47:41 |vpiTypespec: \_logic_typespec: , line:5:12, endln:5:15 |vpiName:outD |vpiFullName:work@top.e4.outD |vpiNetType:48 |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:39:1, endln:86:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:39:1, endln:86:10 |vpiPort: \_port: (outA), line:1:16, endln:1:20 |vpiParent: - \_module: work@Example (work@top.e4), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:47:5, endln:47:41 + \_module_inst: work@Example (work@top.e4), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:47:5, endln:47:41 |vpiName:outA |vpiDirection:2 |vpiHighConn: @@ -11312,11 +11312,11 @@ design: (work@top) |UINT:0 |vpiConstType:9 |vpiInstance: - \_module: work@Example (work@top.e4), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:47:5, endln:47:41 + \_module_inst: work@Example (work@top.e4), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:47:5, endln:47:41 |vpiPort: \_port: (outB), line:1:22, endln:1:26 |vpiParent: - \_module: work@Example (work@top.e4), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:47:5, endln:47:41 + \_module_inst: work@Example (work@top.e4), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:47:5, endln:47:41 |vpiName:outB |vpiDirection:2 |vpiHighConn: @@ -11358,11 +11358,11 @@ design: (work@top) |UINT:0 |vpiConstType:9 |vpiInstance: - \_module: work@Example (work@top.e4), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:47:5, endln:47:41 + \_module_inst: work@Example (work@top.e4), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:47:5, endln:47:41 |vpiPort: \_port: (outC), line:1:28, endln:1:32 |vpiParent: - \_module: work@Example (work@top.e4), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:47:5, endln:47:41 + \_module_inst: work@Example (work@top.e4), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:47:5, endln:47:41 |vpiName:outC |vpiDirection:2 |vpiHighConn: @@ -11384,11 +11384,11 @@ design: (work@top) |vpiTypedef: \_logic_typespec: , line:5:12, endln:5:15 |vpiInstance: - \_module: work@Example (work@top.e4), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:47:5, endln:47:41 + \_module_inst: work@Example (work@top.e4), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:47:5, endln:47:41 |vpiPort: \_port: (outD), line:1:34, endln:1:38 |vpiParent: - \_module: work@Example (work@top.e4), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:47:5, endln:47:41 + \_module_inst: work@Example (work@top.e4), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:47:5, endln:47:41 |vpiName:outD |vpiDirection:2 |vpiHighConn: @@ -11410,11 +11410,11 @@ design: (work@top) |vpiTypedef: \_logic_typespec: , line:5:12, endln:5:15 |vpiInstance: - \_module: work@Example (work@top.e4), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:47:5, endln:47:41 + \_module_inst: work@Example (work@top.e4), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:47:5, endln:47:41 |vpiProcess: \_initial: , line:31:5, endln:36:8 |vpiParent: - \_module: work@Example (work@top.e4), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:47:5, endln:47:41 + \_module_inst: work@Example (work@top.e4), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:47:5, endln:47:41 |vpiStmt: \_begin: (work@top.e4), line:31:13, endln:36:8 |vpiParent: @@ -11586,7 +11586,7 @@ design: (work@top) |vpiProcess: \_initial: , line:24:9, endln:24:26 |vpiParent: - \_module: work@Example (work@top.e4), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:47:5, endln:47:41 + \_module_inst: work@Example (work@top.e4), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:47:5, endln:47:41 |vpiStmt: \_assignment: , line:24:17, endln:24:25 |vpiParent: @@ -11606,7 +11606,7 @@ design: (work@top) |vpiProcess: \_initial: , line:24:9, endln:24:26 |vpiParent: - \_module: work@Example (work@top.e4), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:47:5, endln:47:41 + \_module_inst: work@Example (work@top.e4), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:47:5, endln:47:41 |vpiStmt: \_assignment: , line:24:17, endln:24:25 |vpiParent: @@ -11626,7 +11626,7 @@ design: (work@top) |vpiProcess: \_initial: , line:24:9, endln:24:26 |vpiParent: - \_module: work@Example (work@top.e4), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:47:5, endln:47:41 + \_module_inst: work@Example (work@top.e4), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:47:5, endln:47:41 |vpiStmt: \_assignment: , line:24:17, endln:24:25 |vpiParent: @@ -11646,7 +11646,7 @@ design: (work@top) |vpiProcess: \_initial: , line:24:9, endln:24:26 |vpiParent: - \_module: work@Example (work@top.e4), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:47:5, endln:47:41 + \_module_inst: work@Example (work@top.e4), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:47:5, endln:47:41 |vpiStmt: \_assignment: , line:24:17, endln:24:25 |vpiParent: @@ -11666,7 +11666,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e4.genblk1), line:12:9, endln:15:29 |vpiParent: - \_module: work@Example (work@top.e4), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:47:5, endln:47:41 + \_module_inst: work@Example (work@top.e4), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:47:5, endln:47:41 |vpiName:genblk1 |vpiFullName:work@top.e4.genblk1 |vpiGenScope: @@ -11697,7 +11697,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e4.genblk2), line:17:9, endln:21:16 |vpiParent: - \_module: work@Example (work@top.e4), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:47:5, endln:47:41 + \_module_inst: work@Example (work@top.e4), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:47:5, endln:47:41 |vpiName:genblk2 |vpiFullName:work@top.e4.genblk2 |vpiGenScope: @@ -11728,7 +11728,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e4.genblk3[0]), line:26:13, endln:27:34 |vpiParent: - \_module: work@Example (work@top.e4), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:47:5, endln:47:41 + \_module_inst: work@Example (work@top.e4), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:47:5, endln:47:41 |vpiName:genblk3[0] |vpiFullName:work@top.e4.genblk3[0] |vpiGenScope: @@ -11749,7 +11749,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e4.genblk3[1]), line:26:13, endln:27:34 |vpiParent: - \_module: work@Example (work@top.e4), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:47:5, endln:47:41 + \_module_inst: work@Example (work@top.e4), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:47:5, endln:47:41 |vpiName:genblk3[1] |vpiFullName:work@top.e4.genblk3[1] |vpiGenScope: @@ -11770,7 +11770,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e4.genblk3[2]), line:26:13, endln:27:34 |vpiParent: - \_module: work@Example (work@top.e4), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:47:5, endln:47:41 + \_module_inst: work@Example (work@top.e4), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:47:5, endln:47:41 |vpiName:genblk3[2] |vpiFullName:work@top.e4.genblk3[2] |vpiGenScope: @@ -11791,7 +11791,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e4.genblk3[3]), line:26:13, endln:27:34 |vpiParent: - \_module: work@Example (work@top.e4), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:47:5, endln:47:41 + \_module_inst: work@Example (work@top.e4), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:47:5, endln:47:41 |vpiName:genblk3[3] |vpiFullName:work@top.e4.genblk3[3] |vpiGenScope: @@ -11812,7 +11812,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e4.genblk3[4]), line:26:13, endln:27:34 |vpiParent: - \_module: work@Example (work@top.e4), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:47:5, endln:47:41 + \_module_inst: work@Example (work@top.e4), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:47:5, endln:47:41 |vpiName:genblk3[4] |vpiFullName:work@top.e4.genblk3[4] |vpiGenScope: @@ -11833,7 +11833,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e4.genblk3[5]), line:26:13, endln:27:34 |vpiParent: - \_module: work@Example (work@top.e4), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:47:5, endln:47:41 + \_module_inst: work@Example (work@top.e4), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:47:5, endln:47:41 |vpiName:genblk3[5] |vpiFullName:work@top.e4.genblk3[5] |vpiGenScope: @@ -11854,7 +11854,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e4.genblk3[6]), line:26:13, endln:27:34 |vpiParent: - \_module: work@Example (work@top.e4), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:47:5, endln:47:41 + \_module_inst: work@Example (work@top.e4), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:47:5, endln:47:41 |vpiName:genblk3[6] |vpiFullName:work@top.e4.genblk3[6] |vpiGenScope: @@ -11875,7 +11875,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e4.genblk3[7]), line:26:13, endln:27:34 |vpiParent: - \_module: work@Example (work@top.e4), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:47:5, endln:47:41 + \_module_inst: work@Example (work@top.e4), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:47:5, endln:47:41 |vpiName:genblk3[7] |vpiFullName:work@top.e4.genblk3[7] |vpiGenScope: @@ -11896,7 +11896,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e4.genblk3[8]), line:26:13, endln:27:34 |vpiParent: - \_module: work@Example (work@top.e4), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:47:5, endln:47:41 + \_module_inst: work@Example (work@top.e4), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:47:5, endln:47:41 |vpiName:genblk3[8] |vpiFullName:work@top.e4.genblk3[8] |vpiGenScope: @@ -11917,7 +11917,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e4.genblk3[9]), line:26:13, endln:27:34 |vpiParent: - \_module: work@Example (work@top.e4), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:47:5, endln:47:41 + \_module_inst: work@Example (work@top.e4), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:47:5, endln:47:41 |vpiName:genblk3[9] |vpiFullName:work@top.e4.genblk3[9] |vpiGenScope: @@ -11938,7 +11938,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e4.genblk3[10]), line:26:13, endln:27:34 |vpiParent: - \_module: work@Example (work@top.e4), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:47:5, endln:47:41 + \_module_inst: work@Example (work@top.e4), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:47:5, endln:47:41 |vpiName:genblk3[10] |vpiFullName:work@top.e4.genblk3[10] |vpiGenScope: @@ -11959,7 +11959,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e4.genblk3[11]), line:26:13, endln:27:34 |vpiParent: - \_module: work@Example (work@top.e4), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:47:5, endln:47:41 + \_module_inst: work@Example (work@top.e4), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:47:5, endln:47:41 |vpiName:genblk3[11] |vpiFullName:work@top.e4.genblk3[11] |vpiGenScope: @@ -11980,7 +11980,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e4.genblk3[12]), line:26:13, endln:27:34 |vpiParent: - \_module: work@Example (work@top.e4), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:47:5, endln:47:41 + \_module_inst: work@Example (work@top.e4), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:47:5, endln:47:41 |vpiName:genblk3[12] |vpiFullName:work@top.e4.genblk3[12] |vpiGenScope: @@ -12001,7 +12001,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e4.genblk3[13]), line:26:13, endln:27:34 |vpiParent: - \_module: work@Example (work@top.e4), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:47:5, endln:47:41 + \_module_inst: work@Example (work@top.e4), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:47:5, endln:47:41 |vpiName:genblk3[13] |vpiFullName:work@top.e4.genblk3[13] |vpiGenScope: @@ -12022,7 +12022,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e4.genblk3[14]), line:26:13, endln:27:34 |vpiParent: - \_module: work@Example (work@top.e4), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:47:5, endln:47:41 + \_module_inst: work@Example (work@top.e4), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:47:5, endln:47:41 |vpiName:genblk3[14] |vpiFullName:work@top.e4.genblk3[14] |vpiGenScope: @@ -12043,7 +12043,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e4.genblk3[15]), line:26:13, endln:27:34 |vpiParent: - \_module: work@Example (work@top.e4), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:47:5, endln:47:41 + \_module_inst: work@Example (work@top.e4), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:47:5, endln:47:41 |vpiName:genblk3[15] |vpiFullName:work@top.e4.genblk3[15] |vpiGenScope: @@ -12064,7 +12064,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e4.genblk3[16]), line:26:13, endln:27:34 |vpiParent: - \_module: work@Example (work@top.e4), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:47:5, endln:47:41 + \_module_inst: work@Example (work@top.e4), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:47:5, endln:47:41 |vpiName:genblk3[16] |vpiFullName:work@top.e4.genblk3[16] |vpiGenScope: @@ -12085,7 +12085,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e4.genblk3[17]), line:26:13, endln:27:34 |vpiParent: - \_module: work@Example (work@top.e4), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:47:5, endln:47:41 + \_module_inst: work@Example (work@top.e4), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:47:5, endln:47:41 |vpiName:genblk3[17] |vpiFullName:work@top.e4.genblk3[17] |vpiGenScope: @@ -12106,7 +12106,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e4.genblk3[18]), line:26:13, endln:27:34 |vpiParent: - \_module: work@Example (work@top.e4), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:47:5, endln:47:41 + \_module_inst: work@Example (work@top.e4), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:47:5, endln:47:41 |vpiName:genblk3[18] |vpiFullName:work@top.e4.genblk3[18] |vpiGenScope: @@ -12127,7 +12127,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e4.genblk3[19]), line:26:13, endln:27:34 |vpiParent: - \_module: work@Example (work@top.e4), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:47:5, endln:47:41 + \_module_inst: work@Example (work@top.e4), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:47:5, endln:47:41 |vpiName:genblk3[19] |vpiFullName:work@top.e4.genblk3[19] |vpiGenScope: @@ -12148,7 +12148,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e4.genblk3[20]), line:26:13, endln:27:34 |vpiParent: - \_module: work@Example (work@top.e4), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:47:5, endln:47:41 + \_module_inst: work@Example (work@top.e4), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:47:5, endln:47:41 |vpiName:genblk3[20] |vpiFullName:work@top.e4.genblk3[20] |vpiGenScope: @@ -12169,7 +12169,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e4.genblk3[21]), line:26:13, endln:27:34 |vpiParent: - \_module: work@Example (work@top.e4), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:47:5, endln:47:41 + \_module_inst: work@Example (work@top.e4), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:47:5, endln:47:41 |vpiName:genblk3[21] |vpiFullName:work@top.e4.genblk3[21] |vpiGenScope: @@ -12190,7 +12190,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e4.genblk3[22]), line:26:13, endln:27:34 |vpiParent: - \_module: work@Example (work@top.e4), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:47:5, endln:47:41 + \_module_inst: work@Example (work@top.e4), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:47:5, endln:47:41 |vpiName:genblk3[22] |vpiFullName:work@top.e4.genblk3[22] |vpiGenScope: @@ -12211,7 +12211,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e4.genblk3[23]), line:26:13, endln:27:34 |vpiParent: - \_module: work@Example (work@top.e4), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:47:5, endln:47:41 + \_module_inst: work@Example (work@top.e4), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:47:5, endln:47:41 |vpiName:genblk3[23] |vpiFullName:work@top.e4.genblk3[23] |vpiGenScope: @@ -12232,7 +12232,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e4.genblk3[24]), line:26:13, endln:27:34 |vpiParent: - \_module: work@Example (work@top.e4), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:47:5, endln:47:41 + \_module_inst: work@Example (work@top.e4), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:47:5, endln:47:41 |vpiName:genblk3[24] |vpiFullName:work@top.e4.genblk3[24] |vpiGenScope: @@ -12253,7 +12253,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e4.genblk3[25]), line:26:13, endln:27:34 |vpiParent: - \_module: work@Example (work@top.e4), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:47:5, endln:47:41 + \_module_inst: work@Example (work@top.e4), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:47:5, endln:47:41 |vpiName:genblk3[25] |vpiFullName:work@top.e4.genblk3[25] |vpiGenScope: @@ -12274,7 +12274,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e4.genblk3[26]), line:26:13, endln:27:34 |vpiParent: - \_module: work@Example (work@top.e4), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:47:5, endln:47:41 + \_module_inst: work@Example (work@top.e4), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:47:5, endln:47:41 |vpiName:genblk3[26] |vpiFullName:work@top.e4.genblk3[26] |vpiGenScope: @@ -12295,7 +12295,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e4.genblk3[27]), line:26:13, endln:27:34 |vpiParent: - \_module: work@Example (work@top.e4), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:47:5, endln:47:41 + \_module_inst: work@Example (work@top.e4), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:47:5, endln:47:41 |vpiName:genblk3[27] |vpiFullName:work@top.e4.genblk3[27] |vpiGenScope: @@ -12316,7 +12316,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e4.genblk3[28]), line:26:13, endln:27:34 |vpiParent: - \_module: work@Example (work@top.e4), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:47:5, endln:47:41 + \_module_inst: work@Example (work@top.e4), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:47:5, endln:47:41 |vpiName:genblk3[28] |vpiFullName:work@top.e4.genblk3[28] |vpiGenScope: @@ -12337,7 +12337,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e4.genblk3[29]), line:26:13, endln:27:34 |vpiParent: - \_module: work@Example (work@top.e4), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:47:5, endln:47:41 + \_module_inst: work@Example (work@top.e4), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:47:5, endln:47:41 |vpiName:genblk3[29] |vpiFullName:work@top.e4.genblk3[29] |vpiGenScope: @@ -12358,7 +12358,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e4.genblk3[30]), line:26:13, endln:27:34 |vpiParent: - \_module: work@Example (work@top.e4), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:47:5, endln:47:41 + \_module_inst: work@Example (work@top.e4), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:47:5, endln:47:41 |vpiName:genblk3[30] |vpiFullName:work@top.e4.genblk3[30] |vpiGenScope: @@ -12379,7 +12379,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e4.genblk3[31]), line:26:13, endln:27:34 |vpiParent: - \_module: work@Example (work@top.e4), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:47:5, endln:47:41 + \_module_inst: work@Example (work@top.e4), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:47:5, endln:47:41 |vpiName:genblk3[31] |vpiFullName:work@top.e4.genblk3[31] |vpiGenScope: @@ -12400,7 +12400,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e4.genblk3[32]), line:26:13, endln:27:34 |vpiParent: - \_module: work@Example (work@top.e4), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:47:5, endln:47:41 + \_module_inst: work@Example (work@top.e4), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:47:5, endln:47:41 |vpiName:genblk3[32] |vpiFullName:work@top.e4.genblk3[32] |vpiGenScope: @@ -12421,7 +12421,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e4.genblk3[33]), line:26:13, endln:27:34 |vpiParent: - \_module: work@Example (work@top.e4), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:47:5, endln:47:41 + \_module_inst: work@Example (work@top.e4), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:47:5, endln:47:41 |vpiName:genblk3[33] |vpiFullName:work@top.e4.genblk3[33] |vpiGenScope: @@ -12442,7 +12442,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e4.genblk3[34]), line:26:13, endln:27:34 |vpiParent: - \_module: work@Example (work@top.e4), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:47:5, endln:47:41 + \_module_inst: work@Example (work@top.e4), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:47:5, endln:47:41 |vpiName:genblk3[34] |vpiFullName:work@top.e4.genblk3[34] |vpiGenScope: @@ -12463,7 +12463,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e4.genblk3[35]), line:26:13, endln:27:34 |vpiParent: - \_module: work@Example (work@top.e4), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:47:5, endln:47:41 + \_module_inst: work@Example (work@top.e4), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:47:5, endln:47:41 |vpiName:genblk3[35] |vpiFullName:work@top.e4.genblk3[35] |vpiGenScope: @@ -12484,7 +12484,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e4.genblk3[36]), line:26:13, endln:27:34 |vpiParent: - \_module: work@Example (work@top.e4), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:47:5, endln:47:41 + \_module_inst: work@Example (work@top.e4), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:47:5, endln:47:41 |vpiName:genblk3[36] |vpiFullName:work@top.e4.genblk3[36] |vpiGenScope: @@ -12505,7 +12505,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e4.genblk3[37]), line:26:13, endln:27:34 |vpiParent: - \_module: work@Example (work@top.e4), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:47:5, endln:47:41 + \_module_inst: work@Example (work@top.e4), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:47:5, endln:47:41 |vpiName:genblk3[37] |vpiFullName:work@top.e4.genblk3[37] |vpiGenScope: @@ -12526,7 +12526,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e4.genblk3[38]), line:26:13, endln:27:34 |vpiParent: - \_module: work@Example (work@top.e4), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:47:5, endln:47:41 + \_module_inst: work@Example (work@top.e4), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:47:5, endln:47:41 |vpiName:genblk3[38] |vpiFullName:work@top.e4.genblk3[38] |vpiGenScope: @@ -12547,7 +12547,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e4.genblk3[39]), line:26:13, endln:27:34 |vpiParent: - \_module: work@Example (work@top.e4), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:47:5, endln:47:41 + \_module_inst: work@Example (work@top.e4), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:47:5, endln:47:41 |vpiName:genblk3[39] |vpiFullName:work@top.e4.genblk3[39] |vpiGenScope: @@ -12568,7 +12568,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e4.genblk3[40]), line:26:13, endln:27:34 |vpiParent: - \_module: work@Example (work@top.e4), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:47:5, endln:47:41 + \_module_inst: work@Example (work@top.e4), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:47:5, endln:47:41 |vpiName:genblk3[40] |vpiFullName:work@top.e4.genblk3[40] |vpiGenScope: @@ -12589,7 +12589,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e4.genblk3[41]), line:26:13, endln:27:34 |vpiParent: - \_module: work@Example (work@top.e4), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:47:5, endln:47:41 + \_module_inst: work@Example (work@top.e4), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:47:5, endln:47:41 |vpiName:genblk3[41] |vpiFullName:work@top.e4.genblk3[41] |vpiGenScope: @@ -12610,7 +12610,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e4.genblk3[42]), line:26:13, endln:27:34 |vpiParent: - \_module: work@Example (work@top.e4), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:47:5, endln:47:41 + \_module_inst: work@Example (work@top.e4), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:47:5, endln:47:41 |vpiName:genblk3[42] |vpiFullName:work@top.e4.genblk3[42] |vpiGenScope: @@ -12631,7 +12631,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e4.genblk3[43]), line:26:13, endln:27:34 |vpiParent: - \_module: work@Example (work@top.e4), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:47:5, endln:47:41 + \_module_inst: work@Example (work@top.e4), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:47:5, endln:47:41 |vpiName:genblk3[43] |vpiFullName:work@top.e4.genblk3[43] |vpiGenScope: @@ -12652,7 +12652,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e4.genblk3[44]), line:26:13, endln:27:34 |vpiParent: - \_module: work@Example (work@top.e4), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:47:5, endln:47:41 + \_module_inst: work@Example (work@top.e4), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:47:5, endln:47:41 |vpiName:genblk3[44] |vpiFullName:work@top.e4.genblk3[44] |vpiGenScope: @@ -12673,7 +12673,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e4.genblk3[45]), line:26:13, endln:27:34 |vpiParent: - \_module: work@Example (work@top.e4), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:47:5, endln:47:41 + \_module_inst: work@Example (work@top.e4), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:47:5, endln:47:41 |vpiName:genblk3[45] |vpiFullName:work@top.e4.genblk3[45] |vpiGenScope: @@ -12694,7 +12694,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e4.genblk3[46]), line:26:13, endln:27:34 |vpiParent: - \_module: work@Example (work@top.e4), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:47:5, endln:47:41 + \_module_inst: work@Example (work@top.e4), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:47:5, endln:47:41 |vpiName:genblk3[46] |vpiFullName:work@top.e4.genblk3[46] |vpiGenScope: @@ -12715,7 +12715,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e4.genblk3[47]), line:26:13, endln:27:34 |vpiParent: - \_module: work@Example (work@top.e4), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:47:5, endln:47:41 + \_module_inst: work@Example (work@top.e4), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:47:5, endln:47:41 |vpiName:genblk3[47] |vpiFullName:work@top.e4.genblk3[47] |vpiGenScope: @@ -12736,7 +12736,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e4.genblk3[48]), line:26:13, endln:27:34 |vpiParent: - \_module: work@Example (work@top.e4), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:47:5, endln:47:41 + \_module_inst: work@Example (work@top.e4), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:47:5, endln:47:41 |vpiName:genblk3[48] |vpiFullName:work@top.e4.genblk3[48] |vpiGenScope: @@ -12757,7 +12757,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e4.genblk3[49]), line:26:13, endln:27:34 |vpiParent: - \_module: work@Example (work@top.e4), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:47:5, endln:47:41 + \_module_inst: work@Example (work@top.e4), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:47:5, endln:47:41 |vpiName:genblk3[49] |vpiFullName:work@top.e4.genblk3[49] |vpiGenScope: @@ -12778,7 +12778,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e4.genblk3[50]), line:26:13, endln:27:34 |vpiParent: - \_module: work@Example (work@top.e4), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:47:5, endln:47:41 + \_module_inst: work@Example (work@top.e4), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:47:5, endln:47:41 |vpiName:genblk3[50] |vpiFullName:work@top.e4.genblk3[50] |vpiGenScope: @@ -12799,7 +12799,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e4.genblk3[51]), line:26:13, endln:27:34 |vpiParent: - \_module: work@Example (work@top.e4), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:47:5, endln:47:41 + \_module_inst: work@Example (work@top.e4), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:47:5, endln:47:41 |vpiName:genblk3[51] |vpiFullName:work@top.e4.genblk3[51] |vpiGenScope: @@ -12820,7 +12820,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e4.genblk3[52]), line:26:13, endln:27:34 |vpiParent: - \_module: work@Example (work@top.e4), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:47:5, endln:47:41 + \_module_inst: work@Example (work@top.e4), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:47:5, endln:47:41 |vpiName:genblk3[52] |vpiFullName:work@top.e4.genblk3[52] |vpiGenScope: @@ -12841,7 +12841,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e4.genblk3[53]), line:26:13, endln:27:34 |vpiParent: - \_module: work@Example (work@top.e4), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:47:5, endln:47:41 + \_module_inst: work@Example (work@top.e4), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:47:5, endln:47:41 |vpiName:genblk3[53] |vpiFullName:work@top.e4.genblk3[53] |vpiGenScope: @@ -12862,7 +12862,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e4.genblk3[54]), line:26:13, endln:27:34 |vpiParent: - \_module: work@Example (work@top.e4), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:47:5, endln:47:41 + \_module_inst: work@Example (work@top.e4), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:47:5, endln:47:41 |vpiName:genblk3[54] |vpiFullName:work@top.e4.genblk3[54] |vpiGenScope: @@ -12883,7 +12883,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e4.genblk3[55]), line:26:13, endln:27:34 |vpiParent: - \_module: work@Example (work@top.e4), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:47:5, endln:47:41 + \_module_inst: work@Example (work@top.e4), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:47:5, endln:47:41 |vpiName:genblk3[55] |vpiFullName:work@top.e4.genblk3[55] |vpiGenScope: @@ -12904,7 +12904,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e4.genblk3[56]), line:26:13, endln:27:34 |vpiParent: - \_module: work@Example (work@top.e4), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:47:5, endln:47:41 + \_module_inst: work@Example (work@top.e4), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:47:5, endln:47:41 |vpiName:genblk3[56] |vpiFullName:work@top.e4.genblk3[56] |vpiGenScope: @@ -12925,7 +12925,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e4.genblk3[57]), line:26:13, endln:27:34 |vpiParent: - \_module: work@Example (work@top.e4), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:47:5, endln:47:41 + \_module_inst: work@Example (work@top.e4), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:47:5, endln:47:41 |vpiName:genblk3[57] |vpiFullName:work@top.e4.genblk3[57] |vpiGenScope: @@ -12946,7 +12946,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e4.genblk3[58]), line:26:13, endln:27:34 |vpiParent: - \_module: work@Example (work@top.e4), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:47:5, endln:47:41 + \_module_inst: work@Example (work@top.e4), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:47:5, endln:47:41 |vpiName:genblk3[58] |vpiFullName:work@top.e4.genblk3[58] |vpiGenScope: @@ -12967,7 +12967,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e4.genblk3[59]), line:26:13, endln:27:34 |vpiParent: - \_module: work@Example (work@top.e4), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:47:5, endln:47:41 + \_module_inst: work@Example (work@top.e4), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:47:5, endln:47:41 |vpiName:genblk3[59] |vpiFullName:work@top.e4.genblk3[59] |vpiGenScope: @@ -12988,7 +12988,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e4.genblk3[60]), line:26:13, endln:27:34 |vpiParent: - \_module: work@Example (work@top.e4), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:47:5, endln:47:41 + \_module_inst: work@Example (work@top.e4), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:47:5, endln:47:41 |vpiName:genblk3[60] |vpiFullName:work@top.e4.genblk3[60] |vpiGenScope: @@ -13009,7 +13009,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e4.genblk3[61]), line:26:13, endln:27:34 |vpiParent: - \_module: work@Example (work@top.e4), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:47:5, endln:47:41 + \_module_inst: work@Example (work@top.e4), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:47:5, endln:47:41 |vpiName:genblk3[61] |vpiFullName:work@top.e4.genblk3[61] |vpiGenScope: @@ -13030,7 +13030,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e4.genblk3[62]), line:26:13, endln:27:34 |vpiParent: - \_module: work@Example (work@top.e4), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:47:5, endln:47:41 + \_module_inst: work@Example (work@top.e4), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:47:5, endln:47:41 |vpiName:genblk3[62] |vpiFullName:work@top.e4.genblk3[62] |vpiGenScope: @@ -13051,7 +13051,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e4.genblk3[63]), line:26:13, endln:27:34 |vpiParent: - \_module: work@Example (work@top.e4), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:47:5, endln:47:41 + \_module_inst: work@Example (work@top.e4), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:47:5, endln:47:41 |vpiName:genblk3[63] |vpiFullName:work@top.e4.genblk3[63] |vpiGenScope: @@ -13072,7 +13072,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.e4.genblk3[64]), line:26:13, endln:27:34 |vpiParent: - \_module: work@Example (work@top.e4), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:47:5, endln:47:41 + \_module_inst: work@Example (work@top.e4), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:47:5, endln:47:41 |vpiName:genblk3[64] |vpiFullName:work@top.e4.genblk3[64] |vpiGenScope: @@ -13093,7 +13093,7 @@ design: (work@top) |vpiContAssign: \_cont_assign: , line:50:12, endln:54:24 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:39:1, endln:86:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/StringRange/dut.sv, line:39:1, endln:86:10 |vpiRhs: \_operation: , line:50:18, endln:54:24 |vpiParent: diff --git a/tests/StructAccess/StructAccess.log b/tests/StructAccess/StructAccess.log index 153680f25f..f8c0b64244 100644 --- a/tests/StructAccess/StructAccess.log +++ b/tests/StructAccess/StructAccess.log @@ -539,7 +539,7 @@ io_decl 11 logic_net 7 logic_typespec 5 logic_var 4 -module 5 +module_inst 5 operation 1 package 2 range 2 @@ -572,7 +572,7 @@ io_decl 22 logic_net 7 logic_typespec 5 logic_var 4 -module 5 +module_inst 5 operation 1 package 2 range 2 @@ -1070,17 +1070,17 @@ design: (work@top) \_int_typespec: |vpiSigned:1 |uhdmallModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/StructAccess/dut.sv, line:1:1, endln:30:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/StructAccess/dut.sv, line:1:1, endln:30:10 |vpiParent: \_design: (work@top) |vpiFullName:work@top |vpiTypedef: \_enum_typespec: (pmp_cfg_enum), line:3:2, endln:5:17 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/StructAccess/dut.sv, line:1:1, endln:30:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/StructAccess/dut.sv, line:1:1, endln:30:10 |vpiName:pmp_cfg_enum |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/StructAccess/dut.sv, line:1:1, endln:30:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/StructAccess/dut.sv, line:1:1, endln:30:10 |vpiBaseTypespec: \_logic_typespec: , line:3:15, endln:3:26 |vpiRange: @@ -1110,10 +1110,10 @@ design: (work@top) |vpiTypedef: \_struct_typespec: (pmp_cfg_struct), line:7:10, endln:7:16 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/StructAccess/dut.sv, line:1:1, endln:30:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/StructAccess/dut.sv, line:1:1, endln:30:10 |vpiName:pmp_cfg_struct |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/StructAccess/dut.sv, line:1:1, endln:30:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/StructAccess/dut.sv, line:1:1, endln:30:10 |vpiPacked:1 |vpiTypespecMember: \_typespec_member: (a), line:8:10, endln:8:11 @@ -1132,10 +1132,10 @@ design: (work@top) |vpiTypedef: \_struct_typespec: (pmp_cfg_t), line:11:10, endln:11:16 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/StructAccess/dut.sv, line:1:1, endln:30:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/StructAccess/dut.sv, line:1:1, endln:30:10 |vpiName:pmp_cfg_t |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/StructAccess/dut.sv, line:1:1, endln:30:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/StructAccess/dut.sv, line:1:1, endln:30:10 |vpiPacked:1 |vpiTypespecMember: \_typespec_member: (mode), line:12:17, endln:12:21 @@ -1165,52 +1165,52 @@ design: (work@top) |vpiNet: \_logic_net: (work@top.csr_pmp_cfg_i), line:16:17, endln:16:30 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/StructAccess/dut.sv, line:1:1, endln:30:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/StructAccess/dut.sv, line:1:1, endln:30:10 |vpiName:csr_pmp_cfg_i |vpiFullName:work@top.csr_pmp_cfg_i |vpiNet: \_logic_net: (work@top.csr_pmp_cfg_ie), line:17:17, endln:17:31 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/StructAccess/dut.sv, line:1:1, endln:30:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/StructAccess/dut.sv, line:1:1, endln:30:10 |vpiName:csr_pmp_cfg_ie |vpiFullName:work@top.csr_pmp_cfg_ie |vpiNet: \_logic_net: (work@top.enum_test), line:18:15, endln:18:24 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/StructAccess/dut.sv, line:1:1, endln:30:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/StructAccess/dut.sv, line:1:1, endln:30:10 |vpiName:enum_test |vpiFullName:work@top.enum_test |vpiNet: \_logic_net: (work@top.t), line:22:8, endln:22:9 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/StructAccess/dut.sv, line:1:1, endln:30:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/StructAccess/dut.sv, line:1:1, endln:30:10 |vpiName:t |vpiFullName:work@top.t |vpiNetType:36 |vpiNet: \_logic_net: (work@top.first), line:24:15, endln:24:20 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/StructAccess/dut.sv, line:1:1, endln:30:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/StructAccess/dut.sv, line:1:1, endln:30:10 |vpiName:first |vpiFullName:work@top.first |vpiNet: \_logic_net: (work@top.second), line:25:8, endln:25:14 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/StructAccess/dut.sv, line:1:1, endln:30:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/StructAccess/dut.sv, line:1:1, endln:30:10 |vpiName:second |vpiFullName:work@top.second |vpiNetType:36 |vpiNet: \_logic_net: (work@top.third), line:26:8, endln:26:13 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/StructAccess/dut.sv, line:1:1, endln:30:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/StructAccess/dut.sv, line:1:1, endln:30:10 |vpiName:third |vpiFullName:work@top.third |vpiNetType:36 |vpiContAssign: \_cont_assign: , line:20:9, endln:20:33 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/StructAccess/dut.sv, line:1:1, endln:30:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/StructAccess/dut.sv, line:1:1, endln:30:10 |vpiRhs: \_ref_obj: (work@top.PMP_MODE_OFF), line:20:21, endln:20:33 |vpiParent: @@ -1230,7 +1230,7 @@ design: (work@top) |vpiContAssign: \_cont_assign: , line:28:9, endln:28:43 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/StructAccess/dut.sv, line:1:1, endln:30:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/StructAccess/dut.sv, line:1:1, endln:30:10 |vpiRhs: \_ref_obj: (work@top.PMP_MODE_OFF), line:28:31, endln:28:43 |vpiParent: @@ -1253,12 +1253,12 @@ design: (work@top) \_ref_obj: (mode) |vpiName:mode |uhdmtopModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/StructAccess/dut.sv, line:1:1, endln:30:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/StructAccess/dut.sv, line:1:1, endln:30:10 |vpiName:work@top |vpiVariables: \_array_var: (work@top.csr_pmp_cfg_i), line:16:17, endln:16:35 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/StructAccess/dut.sv, line:1:1, endln:30:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/StructAccess/dut.sv, line:1:1, endln:30:10 |vpiSize:4 |vpiTypespec: \_array_typespec: @@ -1303,7 +1303,7 @@ design: (work@top) |vpiVariables: \_struct_var: (work@top.csr_pmp_cfg_ie), line:17:17, endln:17:31 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/StructAccess/dut.sv, line:1:1, endln:30:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/StructAccess/dut.sv, line:1:1, endln:30:10 |vpiTypespec: \_struct_typespec: (pmp_cfg_t), line:11:10, endln:11:16 |vpiName:csr_pmp_cfg_ie @@ -1312,7 +1312,7 @@ design: (work@top) |vpiVariables: \_enum_var: (work@top.enum_test), line:18:15, endln:18:24 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/StructAccess/dut.sv, line:1:1, endln:30:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/StructAccess/dut.sv, line:1:1, endln:30:10 |vpiTypespec: \_enum_typespec: (pmp_cfg_enum), line:3:2, endln:5:17 |vpiName:enum_test @@ -1321,7 +1321,7 @@ design: (work@top) |vpiVariables: \_logic_var: (work@top.t), line:22:8, endln:22:24 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/StructAccess/dut.sv, line:1:1, endln:30:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/StructAccess/dut.sv, line:1:1, endln:30:10 |vpiTypespec: \_logic_typespec: , line:22:2, endln:22:7 |vpiName:t @@ -1344,7 +1344,7 @@ design: (work@top) |vpiVariables: \_enum_var: (work@top.first), line:24:15, endln:24:20 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/StructAccess/dut.sv, line:1:1, endln:30:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/StructAccess/dut.sv, line:1:1, endln:30:10 |vpiTypespec: \_enum_typespec: (pmp_cfg_enum), line:3:2, endln:5:17 |vpiName:first @@ -1373,7 +1373,7 @@ design: (work@top) |vpiVariables: \_logic_var: (work@top.second), line:25:8, endln:25:39 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/StructAccess/dut.sv, line:1:1, endln:30:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/StructAccess/dut.sv, line:1:1, endln:30:10 |vpiTypespec: \_logic_typespec: , line:25:2, endln:25:7 |vpiName:second @@ -1406,7 +1406,7 @@ design: (work@top) |vpiVariables: \_logic_var: (work@top.third), line:26:8, endln:26:43 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/StructAccess/dut.sv, line:1:1, endln:30:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/StructAccess/dut.sv, line:1:1, endln:30:10 |vpiTypespec: \_logic_typespec: , line:26:2, endln:26:7 |vpiName:third @@ -1442,7 +1442,7 @@ design: (work@top) |vpiContAssign: \_cont_assign: , line:20:9, endln:20:33 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/StructAccess/dut.sv, line:1:1, endln:30:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/StructAccess/dut.sv, line:1:1, endln:30:10 |vpiRhs: \_constant: |vpiParent: @@ -1462,7 +1462,7 @@ design: (work@top) |vpiContAssign: \_cont_assign: , line:28:9, endln:28:43 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/StructAccess/dut.sv, line:1:1, endln:30:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/StructAccess/dut.sv, line:1:1, endln:30:10 |vpiRhs: \_constant: |vpiParent: diff --git a/tests/StructArrayNet/StructArrayNet.log b/tests/StructArrayNet/StructArrayNet.log index ab4f5c042a..1518ea2f26 100644 --- a/tests/StructArrayNet/StructArrayNet.log +++ b/tests/StructArrayNet/StructArrayNet.log @@ -168,7 +168,7 @@ int_typespec 8 int_var 1 logic_net 3 logic_typespec 2 -module 8 +module_inst 8 operation 1 package 3 packed_array_net 1 @@ -191,7 +191,7 @@ int_typespec 8 int_var 1 logic_net 3 logic_typespec 2 -module 8 +module_inst 8 operation 1 package 3 packed_array_net 1 @@ -338,7 +338,7 @@ design: (work@dut) |vpiDefName:pkg |vpiTop:1 |uhdmallModules: -\_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/StructArrayNet/dut.sv, line:9:1, endln:13:10 +\_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/StructArrayNet/dut.sv, line:9:1, endln:13:10 |vpiParent: \_design: (work@dut) |vpiFullName:work@dut @@ -346,20 +346,20 @@ design: (work@dut) |vpiNet: \_logic_net: (work@dut.sel), line:9:22, endln:9:25 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/StructArrayNet/dut.sv, line:9:1, endln:13:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/StructArrayNet/dut.sv, line:9:1, endln:13:10 |vpiName:sel |vpiFullName:work@dut.sel |vpiNet: \_logic_net: (work@dut.struct_array), line:10:32, endln:10:44 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/StructArrayNet/dut.sv, line:9:1, endln:13:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/StructArrayNet/dut.sv, line:9:1, endln:13:10 |vpiName:struct_array |vpiFullName:work@dut.struct_array |vpiNetType:1 |vpiPort: \_port: (sel), line:9:22, endln:9:25 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/StructArrayNet/dut.sv, line:9:1, endln:13:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/StructArrayNet/dut.sv, line:9:1, endln:13:10 |vpiName:sel |vpiDirection:1 |vpiLowConn: @@ -370,7 +370,7 @@ design: (work@dut) \_int_typespec: , line:9:18, endln:9:21 |vpiSigned:1 |uhdmallModules: -\_module: work@mod (work@mod), file:${SURELOG_DIR}/tests/StructArrayNet/dut.sv, line:6:1, endln:7:10 +\_module_inst: work@mod (work@mod), file:${SURELOG_DIR}/tests/StructArrayNet/dut.sv, line:6:1, endln:7:10 |vpiParent: \_design: (work@dut) |vpiFullName:work@mod @@ -378,14 +378,14 @@ design: (work@dut) |vpiNet: \_logic_net: (work@mod.struct_i), line:6:30, endln:6:38 |vpiParent: - \_module: work@mod (work@mod), file:${SURELOG_DIR}/tests/StructArrayNet/dut.sv, line:6:1, endln:7:10 + \_module_inst: work@mod (work@mod), file:${SURELOG_DIR}/tests/StructArrayNet/dut.sv, line:6:1, endln:7:10 |vpiName:struct_i |vpiFullName:work@mod.struct_i |vpiNetType:1 |vpiPort: \_port: (struct_i), line:6:30, endln:6:38 |vpiParent: - \_module: work@mod (work@mod), file:${SURELOG_DIR}/tests/StructArrayNet/dut.sv, line:6:1, endln:7:10 + \_module_inst: work@mod (work@mod), file:${SURELOG_DIR}/tests/StructArrayNet/dut.sv, line:6:1, endln:7:10 |vpiName:struct_i |vpiDirection:1 |vpiLowConn: @@ -395,12 +395,12 @@ design: (work@dut) |vpiTypedef: \_struct_typespec: (pkg::Struct), line:3:12, endln:3:18 |uhdmtopModules: -\_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/StructArrayNet/dut.sv, line:9:1, endln:13:10 +\_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/StructArrayNet/dut.sv, line:9:1, endln:13:10 |vpiName:work@dut |vpiVariables: \_int_var: (work@dut.sel), line:9:22, endln:9:25 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/StructArrayNet/dut.sv, line:9:1, endln:13:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/StructArrayNet/dut.sv, line:9:1, endln:13:10 |vpiTypespec: \_int_typespec: , line:9:18, endln:9:21 |vpiSigned:1 @@ -413,7 +413,7 @@ design: (work@dut) |vpiNet: \_packed_array_net: (work@dut.struct_array), line:10:32, endln:10:44 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/StructArrayNet/dut.sv, line:9:1, endln:13:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/StructArrayNet/dut.sv, line:9:1, endln:13:10 |vpiName:struct_array |vpiFullName:work@dut.struct_array |vpiNetType:1 @@ -444,7 +444,7 @@ design: (work@dut) |vpiPort: \_port: (sel), line:9:22, endln:9:25 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/StructArrayNet/dut.sv, line:9:1, endln:13:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/StructArrayNet/dut.sv, line:9:1, endln:13:10 |vpiName:sel |vpiDirection:1 |vpiLowConn: @@ -459,11 +459,11 @@ design: (work@dut) \_int_typespec: , line:9:18, endln:9:21 |vpiSigned:1 |vpiInstance: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/StructArrayNet/dut.sv, line:9:1, endln:13:10 - |vpiModule: - \_module: work@mod (work@dut.m), file:${SURELOG_DIR}/tests/StructArrayNet/dut.sv, line:12:4, endln:12:40 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/StructArrayNet/dut.sv, line:9:1, endln:13:10 + |vpiModuleInst: + \_module_inst: work@mod (work@dut.m), file:${SURELOG_DIR}/tests/StructArrayNet/dut.sv, line:12:4, endln:12:40 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/StructArrayNet/dut.sv, line:9:1, endln:13:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/StructArrayNet/dut.sv, line:9:1, endln:13:10 |vpiName:m |vpiFullName:work@dut.m |vpiDefName:work@mod @@ -472,18 +472,18 @@ design: (work@dut) |vpiNet: \_struct_net: (work@dut.m.struct_i), line:6:30, endln:6:38 |vpiParent: - \_module: work@mod (work@dut.m), file:${SURELOG_DIR}/tests/StructArrayNet/dut.sv, line:12:4, endln:12:40 + \_module_inst: work@mod (work@dut.m), file:${SURELOG_DIR}/tests/StructArrayNet/dut.sv, line:12:4, endln:12:40 |vpiTypespec: \_struct_typespec: (pkg::Struct), line:3:12, endln:3:18 |vpiName:struct_i |vpiFullName:work@dut.m.struct_i |vpiNetType:1 |vpiInstance: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/StructArrayNet/dut.sv, line:9:1, endln:13:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/StructArrayNet/dut.sv, line:9:1, endln:13:10 |vpiPort: \_port: (struct_i), line:6:30, endln:6:38 |vpiParent: - \_module: work@mod (work@dut.m), file:${SURELOG_DIR}/tests/StructArrayNet/dut.sv, line:12:4, endln:12:40 + \_module_inst: work@mod (work@dut.m), file:${SURELOG_DIR}/tests/StructArrayNet/dut.sv, line:12:4, endln:12:40 |vpiName:struct_i |vpiDirection:1 |vpiHighConn: @@ -519,7 +519,7 @@ design: (work@dut) |vpiTypedef: \_struct_typespec: (pkg::Struct), line:3:12, endln:3:18 |vpiInstance: - \_module: work@mod (work@dut.m), file:${SURELOG_DIR}/tests/StructArrayNet/dut.sv, line:12:4, endln:12:40 + \_module_inst: work@mod (work@dut.m), file:${SURELOG_DIR}/tests/StructArrayNet/dut.sv, line:12:4, endln:12:40 =================== [ FATAL] : 0 [ SYNTAX] : 0 diff --git a/tests/StructStructHierPath/StructStructHierPath.log b/tests/StructStructHierPath/StructStructHierPath.log index 52462d9b16..30de38efce 100644 --- a/tests/StructStructHierPath/StructStructHierPath.log +++ b/tests/StructStructHierPath/StructStructHierPath.log @@ -265,7 +265,7 @@ if_stmt 1 import_typespec 1 logic_net 5 logic_typespec 13 -module 3 +module_inst 3 operation 7 package 3 port 2 @@ -289,7 +289,7 @@ if_stmt 2 import_typespec 1 logic_net 5 logic_typespec 13 -module 3 +module_inst 3 operation 8 package 3 port 3 @@ -584,7 +584,7 @@ design: (work@r5p_wbu) |vpiTypedef: \_struct_typespec: (riscv_isa_pkg::ctl_t), line:19:9, endln:19:15 |vpiParent: - \_module: work@r5p_wbu (work@r5p_wbu), file:${SURELOG_DIR}/tests/StructStructHierPath/dut.sv, line:28:1, endln:37:10 + \_module_inst: work@r5p_wbu (work@r5p_wbu), file:${SURELOG_DIR}/tests/StructStructHierPath/dut.sv, line:28:1, endln:37:10 |vpiName:riscv_isa_pkg::ctl_t |vpiInstance: \_package: riscv_isa_pkg (riscv_isa_pkg::), file:${SURELOG_DIR}/tests/StructStructHierPath/dut.sv, line:2:1, endln:26:26 @@ -597,7 +597,7 @@ design: (work@r5p_wbu) |vpiTypespec: \_struct_typespec: (riscv_isa_pkg::gpr_t), line:4:9, endln:4:15 |vpiParent: - \_module: work@r5p_wbu (work@r5p_wbu), file:${SURELOG_DIR}/tests/StructStructHierPath/dut.sv, line:28:1, endln:37:10 + \_module_inst: work@r5p_wbu (work@r5p_wbu), file:${SURELOG_DIR}/tests/StructStructHierPath/dut.sv, line:28:1, endln:37:10 |vpiName:riscv_isa_pkg::gpr_t |vpiInstance: \_package: riscv_isa_pkg (riscv_isa_pkg::), file:${SURELOG_DIR}/tests/StructStructHierPath/dut.sv, line:2:1, endln:26:26 @@ -802,7 +802,7 @@ design: (work@r5p_wbu) |vpiDefName:riscv_isa_pkg |vpiTop:1 |uhdmallModules: -\_module: work@r5p_wbu (work@r5p_wbu), file:${SURELOG_DIR}/tests/StructStructHierPath/dut.sv, line:28:1, endln:37:10 +\_module_inst: work@r5p_wbu (work@r5p_wbu), file:${SURELOG_DIR}/tests/StructStructHierPath/dut.sv, line:28:1, endln:37:10 |vpiParent: \_design: (work@r5p_wbu) |vpiFullName:work@r5p_wbu @@ -816,20 +816,20 @@ design: (work@r5p_wbu) |vpiNet: \_logic_net: (work@r5p_wbu.ctl), line:28:31, endln:28:34 |vpiParent: - \_module: work@r5p_wbu (work@r5p_wbu), file:${SURELOG_DIR}/tests/StructStructHierPath/dut.sv, line:28:1, endln:37:10 + \_module_inst: work@r5p_wbu (work@r5p_wbu), file:${SURELOG_DIR}/tests/StructStructHierPath/dut.sv, line:28:1, endln:37:10 |vpiName:ctl |vpiFullName:work@r5p_wbu.ctl |vpiNet: \_logic_net: (work@r5p_wbu.wen), line:30:7, endln:30:10 |vpiParent: - \_module: work@r5p_wbu (work@r5p_wbu), file:${SURELOG_DIR}/tests/StructStructHierPath/dut.sv, line:28:1, endln:37:10 + \_module_inst: work@r5p_wbu (work@r5p_wbu), file:${SURELOG_DIR}/tests/StructStructHierPath/dut.sv, line:28:1, endln:37:10 |vpiName:wen |vpiFullName:work@r5p_wbu.wen |vpiNetType:48 |vpiPort: \_port: (ctl), line:28:31, endln:28:34 |vpiParent: - \_module: work@r5p_wbu (work@r5p_wbu), file:${SURELOG_DIR}/tests/StructStructHierPath/dut.sv, line:28:1, endln:37:10 + \_module_inst: work@r5p_wbu (work@r5p_wbu), file:${SURELOG_DIR}/tests/StructStructHierPath/dut.sv, line:28:1, endln:37:10 |vpiName:ctl |vpiDirection:1 |vpiLowConn: @@ -841,7 +841,7 @@ design: (work@r5p_wbu) |vpiProcess: \_always: , line:31:3, endln:34:6 |vpiParent: - \_module: work@r5p_wbu (work@r5p_wbu), file:${SURELOG_DIR}/tests/StructStructHierPath/dut.sv, line:28:1, endln:37:10 + \_module_inst: work@r5p_wbu (work@r5p_wbu), file:${SURELOG_DIR}/tests/StructStructHierPath/dut.sv, line:28:1, endln:37:10 |vpiStmt: \_event_control: , line:31:13, endln:31:27 |vpiParent: @@ -914,7 +914,7 @@ design: (work@r5p_wbu) \_logic_net: (work@r5p_wbu.wen), line:30:7, endln:30:10 |vpiAlwaysType:3 |uhdmtopModules: -\_module: work@r5p_wbu (work@r5p_wbu), file:${SURELOG_DIR}/tests/StructStructHierPath/dut.sv, line:28:1, endln:37:10 +\_module_inst: work@r5p_wbu (work@r5p_wbu), file:${SURELOG_DIR}/tests/StructStructHierPath/dut.sv, line:28:1, endln:37:10 |vpiName:work@r5p_wbu |vpiTypedef: \_struct_typespec: (riscv_isa_pkg::ctl_t), line:19:9, endln:19:15 @@ -927,7 +927,7 @@ design: (work@r5p_wbu) |vpiNet: \_struct_net: (work@r5p_wbu.ctl), line:28:31, endln:28:34 |vpiParent: - \_module: work@r5p_wbu (work@r5p_wbu), file:${SURELOG_DIR}/tests/StructStructHierPath/dut.sv, line:28:1, endln:37:10 + \_module_inst: work@r5p_wbu (work@r5p_wbu), file:${SURELOG_DIR}/tests/StructStructHierPath/dut.sv, line:28:1, endln:37:10 |vpiTypespec: \_struct_typespec: (riscv_isa_pkg::ctl_t), line:19:9, endln:19:15 |vpiName:ctl @@ -935,7 +935,7 @@ design: (work@r5p_wbu) |vpiNet: \_logic_net: (work@r5p_wbu.wen), line:30:7, endln:30:10 |vpiParent: - \_module: work@r5p_wbu (work@r5p_wbu), file:${SURELOG_DIR}/tests/StructStructHierPath/dut.sv, line:28:1, endln:37:10 + \_module_inst: work@r5p_wbu (work@r5p_wbu), file:${SURELOG_DIR}/tests/StructStructHierPath/dut.sv, line:28:1, endln:37:10 |vpiTypespec: \_logic_typespec: , line:30:3, endln:30:6 |vpiName:wen @@ -953,7 +953,7 @@ design: (work@r5p_wbu) |vpiPort: \_port: (ctl), line:28:31, endln:28:34 |vpiParent: - \_module: work@r5p_wbu (work@r5p_wbu), file:${SURELOG_DIR}/tests/StructStructHierPath/dut.sv, line:28:1, endln:37:10 + \_module_inst: work@r5p_wbu (work@r5p_wbu), file:${SURELOG_DIR}/tests/StructStructHierPath/dut.sv, line:28:1, endln:37:10 |vpiName:ctl |vpiDirection:1 |vpiLowConn: @@ -967,11 +967,11 @@ design: (work@r5p_wbu) |vpiTypedef: \_struct_typespec: (riscv_isa_pkg::ctl_t), line:19:9, endln:19:15 |vpiInstance: - \_module: work@r5p_wbu (work@r5p_wbu), file:${SURELOG_DIR}/tests/StructStructHierPath/dut.sv, line:28:1, endln:37:10 + \_module_inst: work@r5p_wbu (work@r5p_wbu), file:${SURELOG_DIR}/tests/StructStructHierPath/dut.sv, line:28:1, endln:37:10 |vpiProcess: \_always: , line:31:3, endln:34:6 |vpiParent: - \_module: work@r5p_wbu (work@r5p_wbu), file:${SURELOG_DIR}/tests/StructStructHierPath/dut.sv, line:28:1, endln:37:10 + \_module_inst: work@r5p_wbu (work@r5p_wbu), file:${SURELOG_DIR}/tests/StructStructHierPath/dut.sv, line:28:1, endln:37:10 |vpiStmt: \_event_control: , line:31:13, endln:31:27 |vpiParent: diff --git a/tests/StructTypedef/StructTypedef.log b/tests/StructTypedef/StructTypedef.log index b1d3624b15..63e18c1f8d 100644 --- a/tests/StructTypedef/StructTypedef.log +++ b/tests/StructTypedef/StructTypedef.log @@ -395,7 +395,7 @@ io_decl 11 logic_net 1 logic_typespec 6 logic_var 1 -module 2 +module_inst 2 package 8 struct_net 1 struct_typespec 9 @@ -421,7 +421,7 @@ io_decl 22 logic_net 1 logic_typespec 6 logic_var 1 -module 2 +module_inst 2 package 8 struct_net 1 struct_typespec 9 @@ -664,7 +664,7 @@ design: (work@top) |vpiTypedef: \_struct_typespec: (flash_ctrl_pkg::mp_region_cfg_t), line:3:9, endln:3:15 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/StructTypedef/dut.sv, line:21:1, endln:27:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/StructTypedef/dut.sv, line:21:1, endln:27:10 |vpiName:flash_ctrl_pkg::mp_region_cfg_t |vpiTypedefAlias: \_struct_typespec: (flash_ctrl_reg_pkg::flash_ctrl_reg2hw_mp_region_cfg_mreg_t), line:3:9, endln:3:15 @@ -1170,7 +1170,7 @@ design: (work@top) \_int_typespec: |vpiSigned:1 |uhdmallModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/StructTypedef/dut.sv, line:21:1, endln:27:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/StructTypedef/dut.sv, line:21:1, endln:27:10 |vpiParent: \_design: (work@top) |vpiFullName:work@top @@ -1182,11 +1182,11 @@ design: (work@top) |vpiNet: \_logic_net: (work@top.region_cfg), line:24:20, endln:24:30 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/StructTypedef/dut.sv, line:21:1, endln:27:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/StructTypedef/dut.sv, line:21:1, endln:27:10 |vpiName:region_cfg |vpiFullName:work@top.region_cfg |uhdmtopModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/StructTypedef/dut.sv, line:21:1, endln:27:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/StructTypedef/dut.sv, line:21:1, endln:27:10 |vpiName:work@top |vpiTypedef: \_struct_typespec: (flash_ctrl_pkg::mp_region_cfg_t), line:3:9, endln:3:15 @@ -1197,7 +1197,7 @@ design: (work@top) |vpiNet: \_struct_net: (work@top.region_cfg), line:24:20, endln:24:30 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/StructTypedef/dut.sv, line:21:1, endln:27:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/StructTypedef/dut.sv, line:21:1, endln:27:10 |vpiTypespec: \_struct_typespec: (flash_ctrl_pkg::mp_region_cfg_t), line:3:9, endln:3:15 |vpiName:region_cfg diff --git a/tests/StructVar/StructVar.log b/tests/StructVar/StructVar.log index 173809e0a8..d78949e26a 100644 --- a/tests/StructVar/StructVar.log +++ b/tests/StructVar/StructVar.log @@ -57,7 +57,7 @@ int_typespec 2 logic_net 13 logic_typespec 8 logic_var 3 -module 14 +module_inst 14 operation 23 parameter 2 range 21 @@ -89,7 +89,7 @@ int_typespec 2 logic_net 13 logic_typespec 8 logic_var 3 -module 14 +module_inst 14 operation 31 parameter 2 range 21 @@ -113,17 +113,17 @@ design: (work@test) |vpiElaborated:1 |vpiName:work@test |uhdmallModules: -\_module: work@dut1 (work@dut1), file:${SURELOG_DIR}/tests/StructVar/dut.sv, line:1:1, endln:31:10 +\_module_inst: work@dut1 (work@dut1), file:${SURELOG_DIR}/tests/StructVar/dut.sv, line:1:1, endln:31:10 |vpiParent: \_design: (work@test) |vpiFullName:work@dut1 |vpiTypedef: \_struct_typespec: (intf), line:13:11, endln:13:17 |vpiParent: - \_module: work@dut1 (work@dut1), file:${SURELOG_DIR}/tests/StructVar/dut.sv, line:1:1, endln:31:10 + \_module_inst: work@dut1 (work@dut1), file:${SURELOG_DIR}/tests/StructVar/dut.sv, line:1:1, endln:31:10 |vpiName:intf |vpiInstance: - \_module: work@dut1 (work@dut1), file:${SURELOG_DIR}/tests/StructVar/dut.sv, line:1:1, endln:31:10 + \_module_inst: work@dut1 (work@dut1), file:${SURELOG_DIR}/tests/StructVar/dut.sv, line:1:1, endln:31:10 |vpiTypespecMember: \_typespec_member: (addr), line:14:22, endln:14:26 |vpiParent: @@ -209,10 +209,10 @@ design: (work@test) |vpiTypedef: \_struct_typespec: (mem_s), line:3:11, endln:3:17 |vpiParent: - \_module: work@dut1 (work@dut1), file:${SURELOG_DIR}/tests/StructVar/dut.sv, line:1:1, endln:31:10 + \_module_inst: work@dut1 (work@dut1), file:${SURELOG_DIR}/tests/StructVar/dut.sv, line:1:1, endln:31:10 |vpiName:mem_s |vpiInstance: - \_module: work@dut1 (work@dut1), file:${SURELOG_DIR}/tests/StructVar/dut.sv, line:1:1, endln:31:10 + \_module_inst: work@dut1 (work@dut1), file:${SURELOG_DIR}/tests/StructVar/dut.sv, line:1:1, endln:31:10 |vpiPacked:1 |vpiTypespecMember: \_typespec_member: (addr), line:4:20, endln:4:24 @@ -303,69 +303,69 @@ design: (work@test) |vpiNet: \_logic_net: (work@dut1.mem1), line:9:9, endln:9:13 |vpiParent: - \_module: work@dut1 (work@dut1), file:${SURELOG_DIR}/tests/StructVar/dut.sv, line:1:1, endln:31:10 + \_module_inst: work@dut1 (work@dut1), file:${SURELOG_DIR}/tests/StructVar/dut.sv, line:1:1, endln:31:10 |vpiName:mem1 |vpiFullName:work@dut1.mem1 |vpiNet: \_logic_net: (work@dut1.mem2), line:11:9, endln:11:13 |vpiParent: - \_module: work@dut1 (work@dut1), file:${SURELOG_DIR}/tests/StructVar/dut.sv, line:1:1, endln:31:10 + \_module_inst: work@dut1 (work@dut1), file:${SURELOG_DIR}/tests/StructVar/dut.sv, line:1:1, endln:31:10 |vpiName:mem2 |vpiFullName:work@dut1.mem2 |vpiNet: \_logic_net: (work@dut1.intf1), line:19:13, endln:19:18 |vpiParent: - \_module: work@dut1 (work@dut1), file:${SURELOG_DIR}/tests/StructVar/dut.sv, line:1:1, endln:31:10 + \_module_inst: work@dut1 (work@dut1), file:${SURELOG_DIR}/tests/StructVar/dut.sv, line:1:1, endln:31:10 |vpiName:intf1 |vpiFullName:work@dut1.intf1 |vpiNetType:1 |vpiNet: \_logic_net: (work@dut1.intf2), line:21:13, endln:21:18 |vpiParent: - \_module: work@dut1 (work@dut1), file:${SURELOG_DIR}/tests/StructVar/dut.sv, line:1:1, endln:31:10 + \_module_inst: work@dut1 (work@dut1), file:${SURELOG_DIR}/tests/StructVar/dut.sv, line:1:1, endln:31:10 |vpiName:intf2 |vpiFullName:work@dut1.intf2 |vpiNetType:1 |vpiNet: \_logic_net: (work@dut1.intf3), line:22:13, endln:22:18 |vpiParent: - \_module: work@dut1 (work@dut1), file:${SURELOG_DIR}/tests/StructVar/dut.sv, line:1:1, endln:31:10 + \_module_inst: work@dut1 (work@dut1), file:${SURELOG_DIR}/tests/StructVar/dut.sv, line:1:1, endln:31:10 |vpiName:intf3 |vpiFullName:work@dut1.intf3 |vpiNetType:1 |vpiNet: \_logic_net: (work@dut1.csr_pmp_addr), line:26:16, endln:26:28 |vpiParent: - \_module: work@dut1 (work@dut1), file:${SURELOG_DIR}/tests/StructVar/dut.sv, line:1:1, endln:31:10 + \_module_inst: work@dut1 (work@dut1), file:${SURELOG_DIR}/tests/StructVar/dut.sv, line:1:1, endln:31:10 |vpiName:csr_pmp_addr |vpiFullName:work@dut1.csr_pmp_addr |vpiNetType:36 |vpiNet: \_logic_net: (work@dut1.pmp_req_err), line:27:16, endln:27:27 |vpiParent: - \_module: work@dut1 (work@dut1), file:${SURELOG_DIR}/tests/StructVar/dut.sv, line:1:1, endln:31:10 + \_module_inst: work@dut1 (work@dut1), file:${SURELOG_DIR}/tests/StructVar/dut.sv, line:1:1, endln:31:10 |vpiName:pmp_req_err |vpiFullName:work@dut1.pmp_req_err |vpiNetType:36 |vpiNet: \_logic_net: (work@dut1.pmp_req_err1), line:28:16, endln:28:28 |vpiParent: - \_module: work@dut1 (work@dut1), file:${SURELOG_DIR}/tests/StructVar/dut.sv, line:1:1, endln:31:10 + \_module_inst: work@dut1 (work@dut1), file:${SURELOG_DIR}/tests/StructVar/dut.sv, line:1:1, endln:31:10 |vpiName:pmp_req_err1 |vpiFullName:work@dut1.pmp_req_err1 |vpiNetType:36 |uhdmallModules: -\_module: work@dut2 (work@dut2), file:${SURELOG_DIR}/tests/StructVar/dut.sv, line:34:1, endln:44:10 +\_module_inst: work@dut2 (work@dut2), file:${SURELOG_DIR}/tests/StructVar/dut.sv, line:34:1, endln:44:10 |vpiParent: \_design: (work@test) |vpiFullName:work@dut2 |vpiTypedef: \_struct_typespec: (mem_s), line:36:11, endln:36:17 |vpiParent: - \_module: work@dut2 (work@dut2), file:${SURELOG_DIR}/tests/StructVar/dut.sv, line:34:1, endln:44:10 + \_module_inst: work@dut2 (work@dut2), file:${SURELOG_DIR}/tests/StructVar/dut.sv, line:34:1, endln:44:10 |vpiName:mem_s |vpiInstance: - \_module: work@dut2 (work@dut2), file:${SURELOG_DIR}/tests/StructVar/dut.sv, line:34:1, endln:44:10 + \_module_inst: work@dut2 (work@dut2), file:${SURELOG_DIR}/tests/StructVar/dut.sv, line:34:1, endln:44:10 |vpiPacked:1 |vpiTypespecMember: \_typespec_member: (addr), line:37:20, endln:37:24 @@ -441,33 +441,33 @@ design: (work@test) |vpiNet: \_logic_net: (work@dut2.mem), line:41:9, endln:41:12 |vpiParent: - \_module: work@dut2 (work@dut2), file:${SURELOG_DIR}/tests/StructVar/dut.sv, line:34:1, endln:44:10 + \_module_inst: work@dut2 (work@dut2), file:${SURELOG_DIR}/tests/StructVar/dut.sv, line:34:1, endln:44:10 |vpiName:mem |vpiFullName:work@dut2.mem |vpiNet: \_logic_net: (work@dut2.memArr), line:42:9, endln:42:15 |vpiParent: - \_module: work@dut2 (work@dut2), file:${SURELOG_DIR}/tests/StructVar/dut.sv, line:34:1, endln:44:10 + \_module_inst: work@dut2 (work@dut2), file:${SURELOG_DIR}/tests/StructVar/dut.sv, line:34:1, endln:44:10 |vpiName:memArr |vpiFullName:work@dut2.memArr |vpiNet: \_logic_net: (work@dut2.memMulti), line:43:9, endln:43:17 |vpiParent: - \_module: work@dut2 (work@dut2), file:${SURELOG_DIR}/tests/StructVar/dut.sv, line:34:1, endln:44:10 + \_module_inst: work@dut2 (work@dut2), file:${SURELOG_DIR}/tests/StructVar/dut.sv, line:34:1, endln:44:10 |vpiName:memMulti |vpiFullName:work@dut2.memMulti |uhdmallModules: -\_module: work@prim_generic_ram_1 (work@prim_generic_ram_1), file:${SURELOG_DIR}/tests/StructVar/dut.sv, line:47:1, endln:66:10 +\_module_inst: work@prim_generic_ram_1 (work@prim_generic_ram_1), file:${SURELOG_DIR}/tests/StructVar/dut.sv, line:47:1, endln:66:10 |vpiParent: \_design: (work@test) |vpiFullName:work@prim_generic_ram_1 |vpiTypedef: \_enum_typespec: (pmp_cfg_mode_e), line:49:3, endln:51:20 |vpiParent: - \_module: work@prim_generic_ram_1 (work@prim_generic_ram_1), file:${SURELOG_DIR}/tests/StructVar/dut.sv, line:47:1, endln:66:10 + \_module_inst: work@prim_generic_ram_1 (work@prim_generic_ram_1), file:${SURELOG_DIR}/tests/StructVar/dut.sv, line:47:1, endln:66:10 |vpiName:pmp_cfg_mode_e |vpiInstance: - \_module: work@prim_generic_ram_1 (work@prim_generic_ram_1), file:${SURELOG_DIR}/tests/StructVar/dut.sv, line:47:1, endln:66:10 + \_module_inst: work@prim_generic_ram_1 (work@prim_generic_ram_1), file:${SURELOG_DIR}/tests/StructVar/dut.sv, line:47:1, endln:66:10 |vpiBaseTypespec: \_logic_typespec: , line:49:16, endln:49:27 |vpiRange: @@ -497,10 +497,10 @@ design: (work@test) |vpiTypedef: \_struct_typespec: (pmp_cfg_t), line:52:11, endln:52:17 |vpiParent: - \_module: work@prim_generic_ram_1 (work@prim_generic_ram_1), file:${SURELOG_DIR}/tests/StructVar/dut.sv, line:47:1, endln:66:10 + \_module_inst: work@prim_generic_ram_1 (work@prim_generic_ram_1), file:${SURELOG_DIR}/tests/StructVar/dut.sv, line:47:1, endln:66:10 |vpiName:pmp_cfg_t |vpiInstance: - \_module: work@prim_generic_ram_1 (work@prim_generic_ram_1), file:${SURELOG_DIR}/tests/StructVar/dut.sv, line:47:1, endln:66:10 + \_module_inst: work@prim_generic_ram_1 (work@prim_generic_ram_1), file:${SURELOG_DIR}/tests/StructVar/dut.sv, line:47:1, endln:66:10 |vpiPacked:1 |vpiTypespecMember: \_typespec_member: (lock), line:53:20, endln:53:24 @@ -532,11 +532,11 @@ design: (work@test) |vpiNet: \_logic_net: (work@prim_generic_ram_1.pmp_cfg), line:57:17, endln:57:24 |vpiParent: - \_module: work@prim_generic_ram_1 (work@prim_generic_ram_1), file:${SURELOG_DIR}/tests/StructVar/dut.sv, line:47:1, endln:66:10 + \_module_inst: work@prim_generic_ram_1 (work@prim_generic_ram_1), file:${SURELOG_DIR}/tests/StructVar/dut.sv, line:47:1, endln:66:10 |vpiName:pmp_cfg |vpiFullName:work@prim_generic_ram_1.pmp_cfg |uhdmallModules: -\_module: work@test (work@test), file:${SURELOG_DIR}/tests/StructVar/dut.sv, line:69:1, endln:76:10 +\_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/StructVar/dut.sv, line:69:1, endln:76:10 |vpiParent: \_design: (work@test) |vpiFullName:work@test @@ -544,7 +544,7 @@ design: (work@test) |vpiProcess: \_initial: , line:74:1, endln:75:25 |vpiParent: - \_module: work@test (work@test), file:${SURELOG_DIR}/tests/StructVar/dut.sv, line:69:1, endln:76:10 + \_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/StructVar/dut.sv, line:69:1, endln:76:10 |vpiStmt: \_sys_func_call: ($vpi_decompiler), line:75:3, endln:75:24 |vpiParent: @@ -559,7 +559,7 @@ design: (work@test) \_logic_net: (test) |vpiName:$vpi_decompiler |uhdmtopModules: -\_module: work@test (work@test), file:${SURELOG_DIR}/tests/StructVar/dut.sv, line:69:1, endln:76:10 +\_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/StructVar/dut.sv, line:69:1, endln:76:10 |vpiName:work@test |vpiDefName:work@test |vpiTop:1 @@ -571,7 +571,7 @@ design: (work@test) |vpiProcess: \_initial: , line:74:1, endln:75:25 |vpiParent: - \_module: work@test (work@test), file:${SURELOG_DIR}/tests/StructVar/dut.sv, line:69:1, endln:76:10 + \_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/StructVar/dut.sv, line:69:1, endln:76:10 |vpiStmt: \_sys_func_call: ($vpi_decompiler), line:75:3, endln:75:24 |vpiParent: @@ -585,16 +585,16 @@ design: (work@test) |vpiActual: \_logic_net: (test) |vpiName:$vpi_decompiler - |vpiModule: - \_module: work@dut1 (work@test.u1), file:${SURELOG_DIR}/tests/StructVar/dut.sv, line:70:3, endln:70:13 + |vpiModuleInst: + \_module_inst: work@dut1 (work@test.u1), file:${SURELOG_DIR}/tests/StructVar/dut.sv, line:70:3, endln:70:13 |vpiParent: - \_module: work@test (work@test), file:${SURELOG_DIR}/tests/StructVar/dut.sv, line:69:1, endln:76:10 + \_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/StructVar/dut.sv, line:69:1, endln:76:10 |vpiName:u1 |vpiFullName:work@test.u1 |vpiVariables: \_struct_var: (work@test.u1.mem1), line:9:9, endln:9:13 |vpiParent: - \_module: work@dut1 (work@test.u1), file:${SURELOG_DIR}/tests/StructVar/dut.sv, line:70:3, endln:70:13 + \_module_inst: work@dut1 (work@test.u1), file:${SURELOG_DIR}/tests/StructVar/dut.sv, line:70:3, endln:70:13 |vpiTypespec: \_struct_typespec: (mem_s), line:3:11, endln:3:17 |vpiName:mem1 @@ -603,7 +603,7 @@ design: (work@test) |vpiVariables: \_array_var: (work@test.u1.mem2), line:11:9, endln:11:17 |vpiParent: - \_module: work@dut1 (work@test.u1), file:${SURELOG_DIR}/tests/StructVar/dut.sv, line:70:3, endln:70:13 + \_module_inst: work@dut1 (work@test.u1), file:${SURELOG_DIR}/tests/StructVar/dut.sv, line:70:3, endln:70:13 |vpiSize:2 |vpiTypespec: \_array_typespec: @@ -648,7 +648,7 @@ design: (work@test) |vpiVariables: \_array_var: (work@test.u1.csr_pmp_addr), line:26:16, endln:26:32 |vpiParent: - \_module: work@dut1 (work@test.u1), file:${SURELOG_DIR}/tests/StructVar/dut.sv, line:70:3, endln:70:13 + \_module_inst: work@dut1 (work@test.u1), file:${SURELOG_DIR}/tests/StructVar/dut.sv, line:70:3, endln:70:13 |vpiSize:2 |vpiTypespec: \_array_typespec: @@ -729,7 +729,7 @@ design: (work@test) |vpiVariables: \_array_var: (work@test.u1.pmp_req_err), line:27:16, endln:27:32 |vpiParent: - \_module: work@dut1 (work@test.u1), file:${SURELOG_DIR}/tests/StructVar/dut.sv, line:70:3, endln:70:13 + \_module_inst: work@dut1 (work@test.u1), file:${SURELOG_DIR}/tests/StructVar/dut.sv, line:70:3, endln:70:13 |vpiSize:2 |vpiTypespec: \_array_typespec: @@ -774,7 +774,7 @@ design: (work@test) |vpiVariables: \_array_var: (work@test.u1.pmp_req_err1), line:28:16, endln:28:33 |vpiParent: - \_module: work@dut1 (work@test.u1), file:${SURELOG_DIR}/tests/StructVar/dut.sv, line:70:3, endln:70:13 + \_module_inst: work@dut1 (work@test.u1), file:${SURELOG_DIR}/tests/StructVar/dut.sv, line:70:3, endln:70:13 |vpiSize:6 |vpiTypespec: \_array_typespec: @@ -852,7 +852,7 @@ design: (work@test) |vpiNet: \_struct_net: (work@test.u1.intf1), line:19:13, endln:19:18 |vpiParent: - \_module: work@dut1 (work@test.u1), file:${SURELOG_DIR}/tests/StructVar/dut.sv, line:70:3, endln:70:13 + \_module_inst: work@dut1 (work@test.u1), file:${SURELOG_DIR}/tests/StructVar/dut.sv, line:70:3, endln:70:13 |vpiTypespec: \_struct_typespec: (intf), line:13:11, endln:13:17 |vpiName:intf1 @@ -861,7 +861,7 @@ design: (work@test) |vpiArrayNet: \_array_net: (work@test.u1.intf2), line:21:13, endln:21:18 |vpiParent: - \_module: work@dut1 (work@test.u1), file:${SURELOG_DIR}/tests/StructVar/dut.sv, line:70:3, endln:70:13 + \_module_inst: work@dut1 (work@test.u1), file:${SURELOG_DIR}/tests/StructVar/dut.sv, line:70:3, endln:70:13 |vpiSize:2 |vpiName:intf2 |vpiFullName:work@test.u1.intf2 @@ -903,7 +903,7 @@ design: (work@test) |vpiArrayNet: \_array_net: (work@test.u1.intf3), line:22:13, endln:22:18 |vpiParent: - \_module: work@dut1 (work@test.u1), file:${SURELOG_DIR}/tests/StructVar/dut.sv, line:70:3, endln:70:13 + \_module_inst: work@dut1 (work@test.u1), file:${SURELOG_DIR}/tests/StructVar/dut.sv, line:70:3, endln:70:13 |vpiSize:6 |vpiName:intf3 |vpiFullName:work@test.u1.intf3 @@ -969,17 +969,17 @@ design: (work@test) |vpiFullName:work@test.u1.intf3.intf3 |vpiNetType:1 |vpiInstance: - \_module: work@test (work@test), file:${SURELOG_DIR}/tests/StructVar/dut.sv, line:69:1, endln:76:10 - |vpiModule: - \_module: work@dut2 (work@test.u2), file:${SURELOG_DIR}/tests/StructVar/dut.sv, line:71:3, endln:71:13 + \_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/StructVar/dut.sv, line:69:1, endln:76:10 + |vpiModuleInst: + \_module_inst: work@dut2 (work@test.u2), file:${SURELOG_DIR}/tests/StructVar/dut.sv, line:71:3, endln:71:13 |vpiParent: - \_module: work@test (work@test), file:${SURELOG_DIR}/tests/StructVar/dut.sv, line:69:1, endln:76:10 + \_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/StructVar/dut.sv, line:69:1, endln:76:10 |vpiName:u2 |vpiFullName:work@test.u2 |vpiVariables: \_struct_var: (work@test.u2.mem), line:41:9, endln:41:12 |vpiParent: - \_module: work@dut2 (work@test.u2), file:${SURELOG_DIR}/tests/StructVar/dut.sv, line:71:3, endln:71:13 + \_module_inst: work@dut2 (work@test.u2), file:${SURELOG_DIR}/tests/StructVar/dut.sv, line:71:3, endln:71:13 |vpiTypespec: \_struct_typespec: (mem_s), line:36:11, endln:36:17 |vpiName:mem @@ -988,7 +988,7 @@ design: (work@test) |vpiVariables: \_array_var: (work@test.u2.memArr), line:42:9, endln:42:20 |vpiParent: - \_module: work@dut2 (work@test.u2), file:${SURELOG_DIR}/tests/StructVar/dut.sv, line:71:3, endln:71:13 + \_module_inst: work@dut2 (work@test.u2), file:${SURELOG_DIR}/tests/StructVar/dut.sv, line:71:3, endln:71:13 |vpiSize:20 |vpiTypespec: \_array_typespec: @@ -1033,7 +1033,7 @@ design: (work@test) |vpiVariables: \_array_var: (work@test.u2.memMulti), line:43:9, endln:43:22 |vpiParent: - \_module: work@dut2 (work@test.u2), file:${SURELOG_DIR}/tests/StructVar/dut.sv, line:71:3, endln:71:13 + \_module_inst: work@dut2 (work@test.u2), file:${SURELOG_DIR}/tests/StructVar/dut.sv, line:71:3, endln:71:13 |vpiSize:600 |vpiTypespec: \_array_typespec: @@ -1107,17 +1107,17 @@ design: (work@test) |vpiDefFile:${SURELOG_DIR}/tests/StructVar/dut.sv |vpiDefLineNo:34 |vpiInstance: - \_module: work@test (work@test), file:${SURELOG_DIR}/tests/StructVar/dut.sv, line:69:1, endln:76:10 - |vpiModule: - \_module: work@prim_generic_ram_1 (work@test.u3), file:${SURELOG_DIR}/tests/StructVar/dut.sv, line:72:3, endln:72:27 + \_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/StructVar/dut.sv, line:69:1, endln:76:10 + |vpiModuleInst: + \_module_inst: work@prim_generic_ram_1 (work@test.u3), file:${SURELOG_DIR}/tests/StructVar/dut.sv, line:72:3, endln:72:27 |vpiParent: - \_module: work@test (work@test), file:${SURELOG_DIR}/tests/StructVar/dut.sv, line:69:1, endln:76:10 + \_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/StructVar/dut.sv, line:69:1, endln:76:10 |vpiName:u3 |vpiFullName:work@test.u3 |vpiVariables: \_array_var: (work@test.u3.pmp_cfg), line:57:17, endln:57:29 |vpiParent: - \_module: work@prim_generic_ram_1 (work@test.u3), file:${SURELOG_DIR}/tests/StructVar/dut.sv, line:72:3, endln:72:27 + \_module_inst: work@prim_generic_ram_1 (work@test.u3), file:${SURELOG_DIR}/tests/StructVar/dut.sv, line:72:3, endln:72:27 |vpiSize:2 |vpiTypespec: \_array_typespec: @@ -1167,11 +1167,11 @@ design: (work@test) |vpiDefFile:${SURELOG_DIR}/tests/StructVar/dut.sv |vpiDefLineNo:47 |vpiInstance: - \_module: work@test (work@test), file:${SURELOG_DIR}/tests/StructVar/dut.sv, line:69:1, endln:76:10 + \_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/StructVar/dut.sv, line:69:1, endln:76:10 |vpiGenScopeArray: \_gen_scope_array: (work@test.u3.g_pmp_csrs[0]), line:59:33, endln:64:5 |vpiParent: - \_module: work@prim_generic_ram_1 (work@test.u3), file:${SURELOG_DIR}/tests/StructVar/dut.sv, line:72:3, endln:72:27 + \_module_inst: work@prim_generic_ram_1 (work@test.u3), file:${SURELOG_DIR}/tests/StructVar/dut.sv, line:72:3, endln:72:27 |vpiName:g_pmp_csrs[0] |vpiFullName:work@test.u3.g_pmp_csrs[0] |vpiGenScope: @@ -1300,7 +1300,7 @@ design: (work@test) |vpiGenScopeArray: \_gen_scope_array: (work@test.u3.g_pmp_csrs[1]), line:59:33, endln:64:5 |vpiParent: - \_module: work@prim_generic_ram_1 (work@test.u3), file:${SURELOG_DIR}/tests/StructVar/dut.sv, line:72:3, endln:72:27 + \_module_inst: work@prim_generic_ram_1 (work@test.u3), file:${SURELOG_DIR}/tests/StructVar/dut.sv, line:72:3, endln:72:27 |vpiName:g_pmp_csrs[1] |vpiFullName:work@test.u3.g_pmp_csrs[1] |vpiGenScope: diff --git a/tests/StructVarImp/StructVarImp.log b/tests/StructVarImp/StructVarImp.log index 28e9a61b16..d4947e3bec 100644 --- a/tests/StructVarImp/StructVarImp.log +++ b/tests/StructVarImp/StructVarImp.log @@ -505,7 +505,7 @@ io_decl 11 logic_net 2 logic_typespec 12 logic_var 1 -module 5 +module_inst 5 package 5 packed_array_typespec 1 packed_array_var 1 @@ -537,7 +537,7 @@ io_decl 22 logic_net 2 logic_typespec 12 logic_var 1 -module 5 +module_inst 5 package 5 packed_array_typespec 1 packed_array_var 1 @@ -985,7 +985,7 @@ design: (work@top) |vpiTypedef: \_struct_typespec: (flash_ctrl_reg_pkg::flash_ctrl_reg2hw_mp_region_cfg_mreg_t), line:7:11, endln:7:17 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/StructVarImp/dut.sv, line:33:1, endln:38:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/StructVarImp/dut.sv, line:33:1, endln:38:10 |vpiName:flash_ctrl_reg_pkg::flash_ctrl_reg2hw_mp_region_cfg_mreg_t |vpiInstance: \_package: flash_ctrl_reg_pkg (flash_ctrl_reg_pkg::), file:${SURELOG_DIR}/tests/StructVarImp/dut.sv, line:1:1, endln:29:11 @@ -1661,14 +1661,14 @@ design: (work@top) \_int_typespec: |vpiSigned:1 |uhdmallModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/StructVarImp/dut.sv, line:33:1, endln:38:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/StructVarImp/dut.sv, line:33:1, endln:38:10 |vpiParent: \_design: (work@top) |vpiFullName:work@top |vpiParameter: \_parameter: (work@top.NBanks), line:4:17, endln:4:23 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/StructVarImp/dut.sv, line:33:1, endln:38:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/StructVarImp/dut.sv, line:33:1, endln:38:10 |UINT:2 |vpiTypespec: \_int_typespec: , line:4:13, endln:4:16 @@ -1684,7 +1684,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.NumRegions), line:5:17, endln:5:27 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/StructVarImp/dut.sv, line:33:1, endln:38:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/StructVarImp/dut.sv, line:33:1, endln:38:10 |UINT:8 |vpiTypespec: \_int_typespec: , line:5:13, endln:5:16 @@ -1700,7 +1700,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:4:17, endln:4:27 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/StructVarImp/dut.sv, line:33:1, endln:38:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/StructVarImp/dut.sv, line:33:1, endln:38:10 |vpiRhs: \_constant: , line:4:26, endln:4:27 |vpiParent: @@ -1735,7 +1735,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:5:17, endln:5:31 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/StructVarImp/dut.sv, line:33:1, endln:38:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/StructVarImp/dut.sv, line:33:1, endln:38:10 |vpiRhs: \_constant: , line:5:30, endln:5:31 |vpiParent: @@ -1775,16 +1775,16 @@ design: (work@top) |vpiNet: \_logic_net: (work@top.region_cfgs), line:36:56, endln:36:67 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/StructVarImp/dut.sv, line:33:1, endln:38:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/StructVarImp/dut.sv, line:33:1, endln:38:10 |vpiName:region_cfgs |vpiFullName:work@top.region_cfgs |uhdmtopModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/StructVarImp/dut.sv, line:33:1, endln:38:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/StructVarImp/dut.sv, line:33:1, endln:38:10 |vpiName:work@top |vpiVariables: \_packed_array_var: (work@top.region_cfgs), line:36:56, endln:36:67 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/StructVarImp/dut.sv, line:33:1, endln:38:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/StructVarImp/dut.sv, line:33:1, endln:38:10 |vpiName:region_cfgs |vpiFullName:work@top.region_cfgs |vpiVisibility:1 @@ -1815,7 +1815,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.NBanks), line:4:17, endln:4:23 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/StructVarImp/dut.sv, line:33:1, endln:38:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/StructVarImp/dut.sv, line:33:1, endln:38:10 |UINT:2 |vpiTypespec: \_int_typespec: , line:4:13, endln:4:16 @@ -1831,7 +1831,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.NumRegions), line:5:17, endln:5:27 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/StructVarImp/dut.sv, line:33:1, endln:38:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/StructVarImp/dut.sv, line:33:1, endln:38:10 |UINT:8 |vpiTypespec: \_int_typespec: , line:5:13, endln:5:16 @@ -1847,7 +1847,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:4:17, endln:4:27 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/StructVarImp/dut.sv, line:33:1, endln:38:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/StructVarImp/dut.sv, line:33:1, endln:38:10 |vpiRhs: \_constant: , line:4:26, endln:4:27 |vpiDecompile:2 @@ -1861,7 +1861,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:5:17, endln:5:31 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/StructVarImp/dut.sv, line:33:1, endln:38:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/StructVarImp/dut.sv, line:33:1, endln:38:10 |vpiRhs: \_constant: , line:5:30, endln:5:31 |vpiDecompile:8 diff --git a/tests/SynthForeach/SynthForeach.log b/tests/SynthForeach/SynthForeach.log index bfe35ba3d3..e1c7d519a5 100644 --- a/tests/SynthForeach/SynthForeach.log +++ b/tests/SynthForeach/SynthForeach.log @@ -314,7 +314,7 @@ hier_path 5 logic_net 7 logic_typespec 11 logic_var 2 -module 7 +module_inst 7 operation 13 port 8 range 32 @@ -342,7 +342,7 @@ hier_path 5 logic_net 7 logic_typespec 11 logic_var 4 -module 7 +module_inst 7 operation 17 port 12 range 32 @@ -364,7 +364,7 @@ design: (work@dut) |vpiElaborated:1 |vpiName:work@dut |uhdmallModules: -\_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/SynthForeach/dut.sv, line:1:1, endln:7:10 +\_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/SynthForeach/dut.sv, line:1:1, endln:7:10 |vpiParent: \_design: (work@dut) |vpiFullName:work@dut @@ -372,20 +372,20 @@ design: (work@dut) |vpiNet: \_logic_net: (work@dut.clk), line:1:18, endln:1:21 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/SynthForeach/dut.sv, line:1:1, endln:7:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/SynthForeach/dut.sv, line:1:1, endln:7:10 |vpiName:clk |vpiFullName:work@dut.clk |vpiNet: \_logic_net: (work@dut.data), line:1:43, endln:1:47 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/SynthForeach/dut.sv, line:1:1, endln:7:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/SynthForeach/dut.sv, line:1:1, endln:7:10 |vpiName:data |vpiFullName:work@dut.data |vpiNetType:36 |vpiPort: \_port: (clk), line:1:18, endln:1:21 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/SynthForeach/dut.sv, line:1:1, endln:7:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/SynthForeach/dut.sv, line:1:1, endln:7:10 |vpiName:clk |vpiDirection:1 |vpiLowConn: @@ -397,7 +397,7 @@ design: (work@dut) |vpiPort: \_port: (data), line:1:43, endln:1:47 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/SynthForeach/dut.sv, line:1:1, endln:7:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/SynthForeach/dut.sv, line:1:1, endln:7:10 |vpiName:data |vpiDirection:2 |vpiLowConn: @@ -484,7 +484,7 @@ design: (work@dut) |vpiProcess: \_always: , line:2:5, endln:6:8 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/SynthForeach/dut.sv, line:1:1, endln:7:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/SynthForeach/dut.sv, line:1:1, endln:7:10 |vpiStmt: \_event_control: , line:2:12, endln:2:26 |vpiParent: @@ -638,7 +638,7 @@ design: (work@dut) \_logic_var: (j), line:4:29, endln:4:30 |vpiAlwaysType:1 |uhdmallModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/SynthForeach/dut.sv, line:9:1, endln:16:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/SynthForeach/dut.sv, line:9:1, endln:16:10 |vpiParent: \_design: (work@dut) |vpiFullName:work@top @@ -646,19 +646,19 @@ design: (work@dut) |vpiNet: \_logic_net: (work@top.clk), line:9:18, endln:9:21 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/SynthForeach/dut.sv, line:9:1, endln:16:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/SynthForeach/dut.sv, line:9:1, endln:16:10 |vpiName:clk |vpiFullName:work@top.clk |vpiNet: \_logic_net: (work@top.B), line:9:45, endln:9:46 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/SynthForeach/dut.sv, line:9:1, endln:16:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/SynthForeach/dut.sv, line:9:1, endln:16:10 |vpiName:B |vpiFullName:work@top.B |vpiPort: \_port: (clk), line:9:18, endln:9:21 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/SynthForeach/dut.sv, line:9:1, endln:16:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/SynthForeach/dut.sv, line:9:1, endln:16:10 |vpiName:clk |vpiDirection:1 |vpiLowConn: @@ -670,7 +670,7 @@ design: (work@dut) |vpiPort: \_port: (B), line:9:45, endln:9:46 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/SynthForeach/dut.sv, line:9:1, endln:16:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/SynthForeach/dut.sv, line:9:1, endln:16:10 |vpiName:B |vpiDirection:2 |vpiLowConn: @@ -768,7 +768,7 @@ design: (work@dut) |vpiProcess: \_always: , line:10:5, endln:15:8 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/SynthForeach/dut.sv, line:9:1, endln:16:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/SynthForeach/dut.sv, line:9:1, endln:16:10 |vpiStmt: \_event_control: , line:10:12, endln:10:26 |vpiParent: @@ -1044,14 +1044,14 @@ design: (work@dut) \_bit_var: (s), line:11:27, endln:11:28 |vpiAlwaysType:1 |uhdmtopModules: -\_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/SynthForeach/dut.sv, line:1:1, endln:7:10 +\_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/SynthForeach/dut.sv, line:1:1, endln:7:10 |vpiName:work@dut |vpiDefName:work@dut |vpiTop:1 |vpiNet: \_logic_net: (work@dut.clk), line:1:18, endln:1:21 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/SynthForeach/dut.sv, line:1:1, endln:7:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/SynthForeach/dut.sv, line:1:1, endln:7:10 |vpiTypespec: \_logic_typespec: , line:1:18, endln:1:18 |vpiName:clk @@ -1059,7 +1059,7 @@ design: (work@dut) |vpiArrayNet: \_array_net: (work@dut.data), line:1:43, endln:1:47 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/SynthForeach/dut.sv, line:1:1, endln:7:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/SynthForeach/dut.sv, line:1:1, endln:7:10 |vpiSize:16 |vpiName:data |vpiFullName:work@dut.data @@ -1145,7 +1145,7 @@ design: (work@dut) |vpiPort: \_port: (clk), line:1:18, endln:1:21 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/SynthForeach/dut.sv, line:1:1, endln:7:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/SynthForeach/dut.sv, line:1:1, endln:7:10 |vpiName:clk |vpiDirection:1 |vpiLowConn: @@ -1159,11 +1159,11 @@ design: (work@dut) |vpiTypedef: \_logic_typespec: , line:1:18, endln:1:18 |vpiInstance: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/SynthForeach/dut.sv, line:1:1, endln:7:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/SynthForeach/dut.sv, line:1:1, endln:7:10 |vpiPort: \_port: (data), line:1:43, endln:1:47 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/SynthForeach/dut.sv, line:1:1, endln:7:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/SynthForeach/dut.sv, line:1:1, endln:7:10 |vpiName:data |vpiDirection:2 |vpiLowConn: @@ -1197,11 +1197,11 @@ design: (work@dut) |UINT:0 |vpiConstType:9 |vpiInstance: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/SynthForeach/dut.sv, line:1:1, endln:7:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/SynthForeach/dut.sv, line:1:1, endln:7:10 |vpiProcess: \_always: , line:2:5, endln:6:8 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/SynthForeach/dut.sv, line:1:1, endln:7:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/SynthForeach/dut.sv, line:1:1, endln:7:10 |vpiStmt: \_event_control: , line:2:12, endln:2:26 |vpiParent: @@ -1331,12 +1331,12 @@ design: (work@dut) \_logic_var: (j), line:4:29, endln:4:30 |vpiAlwaysType:1 |uhdmtopModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/SynthForeach/dut.sv, line:9:1, endln:16:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/SynthForeach/dut.sv, line:9:1, endln:16:10 |vpiName:work@top |vpiVariables: \_array_var: (work@top.B), line:9:45, endln:9:52 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/SynthForeach/dut.sv, line:9:1, endln:16:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/SynthForeach/dut.sv, line:9:1, endln:16:10 |vpiSize:8 |vpiTypespec: \_array_typespec: @@ -1442,7 +1442,7 @@ design: (work@dut) |vpiNet: \_logic_net: (work@top.clk), line:9:18, endln:9:21 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/SynthForeach/dut.sv, line:9:1, endln:16:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/SynthForeach/dut.sv, line:9:1, endln:16:10 |vpiTypespec: \_logic_typespec: , line:9:18, endln:9:18 |vpiName:clk @@ -1451,7 +1451,7 @@ design: (work@dut) |vpiPort: \_port: (clk), line:9:18, endln:9:21 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/SynthForeach/dut.sv, line:9:1, endln:16:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/SynthForeach/dut.sv, line:9:1, endln:16:10 |vpiName:clk |vpiDirection:1 |vpiLowConn: @@ -1465,11 +1465,11 @@ design: (work@dut) |vpiTypedef: \_logic_typespec: , line:9:18, endln:9:18 |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/SynthForeach/dut.sv, line:9:1, endln:16:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/SynthForeach/dut.sv, line:9:1, endln:16:10 |vpiPort: \_port: (B), line:9:45, endln:9:46 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/SynthForeach/dut.sv, line:9:1, endln:16:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/SynthForeach/dut.sv, line:9:1, endln:16:10 |vpiName:B |vpiDirection:2 |vpiLowConn: @@ -1524,11 +1524,11 @@ design: (work@dut) |vpiConstType:9 |vpiSigned:1 |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/SynthForeach/dut.sv, line:9:1, endln:16:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/SynthForeach/dut.sv, line:9:1, endln:16:10 |vpiProcess: \_always: , line:10:5, endln:15:8 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/SynthForeach/dut.sv, line:9:1, endln:16:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/SynthForeach/dut.sv, line:9:1, endln:16:10 |vpiStmt: \_event_control: , line:10:12, endln:10:26 |vpiParent: diff --git a/tests/SystemCall/SystemCall.log b/tests/SystemCall/SystemCall.log index 16fb335532..e23eb995eb 100644 --- a/tests/SystemCall/SystemCall.log +++ b/tests/SystemCall/SystemCall.log @@ -102,7 +102,7 @@ design 1 io_decl 1 let_decl 1 logic_net 3 -module 3 +module_inst 3 operation 1 ref_obj 5 seq_formal_decl 1 @@ -117,7 +117,7 @@ design 1 io_decl 1 let_decl 2 logic_net 3 -module 3 +module_inst 3 operation 2 ref_obj 10 seq_formal_decl 1 @@ -136,7 +136,7 @@ design: (work@m2) |vpiElaborated:1 |vpiName:work@m2 |uhdmallModules: -\_module: work@m2 (work@m2), file:${SURELOG_DIR}/tests/SystemCall/dut.sv, line:1:1, endln:6:10 +\_module_inst: work@m2 (work@m2), file:${SURELOG_DIR}/tests/SystemCall/dut.sv, line:1:1, endln:6:10 |vpiParent: \_design: (work@m2) |vpiFullName:work@m2 @@ -176,7 +176,7 @@ design: (work@m2) |vpiContAssign: \_cont_assign: , line:4:8, endln:4:39 |vpiParent: - \_module: work@m2 (work@m2), file:${SURELOG_DIR}/tests/SystemCall/dut.sv, line:1:1, endln:6:10 + \_module_inst: work@m2 (work@m2), file:${SURELOG_DIR}/tests/SystemCall/dut.sv, line:1:1, endln:6:10 |vpiRhs: \_sys_func_call: ($past), line:4:12, endln:4:17 |vpiParent: @@ -224,12 +224,12 @@ design: (work@m2) |vpiActual: \_logic_net: (a) |uhdmtopModules: -\_module: work@m2 (work@m2), file:${SURELOG_DIR}/tests/SystemCall/dut.sv, line:1:1, endln:6:10 +\_module_inst: work@m2 (work@m2), file:${SURELOG_DIR}/tests/SystemCall/dut.sv, line:1:1, endln:6:10 |vpiName:work@m2 |vpiLetDecl: \_let_decl: (p2), line:3:1, endln:3:30 |vpiParent: - \_module: work@m2 (work@m2), file:${SURELOG_DIR}/tests/SystemCall/dut.sv, line:1:1, endln:6:10 + \_module_inst: work@m2 (work@m2), file:${SURELOG_DIR}/tests/SystemCall/dut.sv, line:1:1, endln:6:10 |vpiExpr: \_sys_func_call: ($past), line:3:13, endln:3:29 |vpiParent: @@ -274,7 +274,7 @@ design: (work@m2) |vpiContAssign: \_cont_assign: , line:4:8, endln:4:39 |vpiParent: - \_module: work@m2 (work@m2), file:${SURELOG_DIR}/tests/SystemCall/dut.sv, line:1:1, endln:6:10 + \_module_inst: work@m2 (work@m2), file:${SURELOG_DIR}/tests/SystemCall/dut.sv, line:1:1, endln:6:10 |vpiRhs: \_sys_func_call: ($past), line:4:12, endln:4:17 |vpiParent: diff --git a/tests/TNocBadType/TNocBadType.log b/tests/TNocBadType/TNocBadType.log index 550c78a71b..04fd00febe 100644 --- a/tests/TNocBadType/TNocBadType.log +++ b/tests/TNocBadType/TNocBadType.log @@ -90,11 +90,11 @@ n<> u<56> t c<1> l<1:1> el<14:1> === UHDM Object Stats Begin (Non-Elaborated Model) === design 1 int_typespec 1 -interface 1 +interface_inst 1 interface_typespec 1 logic_net 2 logic_var 1 -module 2 +module_inst 2 unsupported_typespec 1 === UHDM Object Stats End === [INF:UH0707] Elaborating UHDM... @@ -102,11 +102,11 @@ unsupported_typespec 1 === UHDM Object Stats Begin (Elaborated Model) === design 1 int_typespec 1 -interface 1 +interface_inst 1 interface_typespec 1 logic_net 2 logic_var 1 -module 2 +module_inst 2 unsupported_typespec 1 === UHDM Object Stats End === [INF:UH0708] Writing UHDM DB: ${SURELOG_DIR}/build/regression/TNocBadType/slpp_all/surelog.uhdm ... @@ -122,51 +122,51 @@ design: (work@top) |vpiElaborated:1 |vpiName:work@top |uhdmallInterfaces: -\_interface: work@tnoc_types (work@tnoc_types), file:${SURELOG_DIR}/tests/TNocBadType/dut.sv, line:1:1, endln:4:13 +\_interface_inst: work@tnoc_types (work@tnoc_types), file:${SURELOG_DIR}/tests/TNocBadType/dut.sv, line:1:1, endln:4:13 |vpiParent: \_design: (work@top) |vpiFullName:work@tnoc_types |vpiTypedef: \_int_typespec: (tnoc_common_header), line:2:10, endln:2:13 |vpiParent: - \_interface: work@tnoc_types (work@tnoc_types), file:${SURELOG_DIR}/tests/TNocBadType/dut.sv, line:1:1, endln:4:13 + \_interface_inst: work@tnoc_types (work@tnoc_types), file:${SURELOG_DIR}/tests/TNocBadType/dut.sv, line:1:1, endln:4:13 |vpiName:tnoc_common_header |vpiInstance: - \_interface: work@tnoc_types (work@tnoc_types), file:${SURELOG_DIR}/tests/TNocBadType/dut.sv, line:1:1, endln:4:13 + \_interface_inst: work@tnoc_types (work@tnoc_types), file:${SURELOG_DIR}/tests/TNocBadType/dut.sv, line:1:1, endln:4:13 |vpiSigned:1 |vpiDefName:work@tnoc_types |uhdmallModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/TNocBadType/dut.sv, line:7:1, endln:13:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/TNocBadType/dut.sv, line:7:1, endln:13:10 |vpiParent: \_design: (work@top) |vpiFullName:work@top |vpiTypedef: \_unsupported_typespec: (tnoc_common_header), line:10:11, endln:10:16 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/TNocBadType/dut.sv, line:7:1, endln:13:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/TNocBadType/dut.sv, line:7:1, endln:13:10 |vpiName:tnoc_common_header |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/TNocBadType/dut.sv, line:7:1, endln:13:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/TNocBadType/dut.sv, line:7:1, endln:13:10 |vpiDefName:work@top |vpiNet: \_logic_net: (work@top.types), line:8:16, endln:8:21 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/TNocBadType/dut.sv, line:7:1, endln:13:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/TNocBadType/dut.sv, line:7:1, endln:13:10 |vpiName:types |vpiFullName:work@top.types |vpiNet: \_logic_net: (work@top.common_header), line:12:23, endln:12:36 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/TNocBadType/dut.sv, line:7:1, endln:13:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/TNocBadType/dut.sv, line:7:1, endln:13:10 |vpiName:common_header |vpiFullName:work@top.common_header |uhdmtopModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/TNocBadType/dut.sv, line:7:1, endln:13:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/TNocBadType/dut.sv, line:7:1, endln:13:10 |vpiName:work@top |vpiVariables: \_logic_var: (work@top.common_header), line:12:23, endln:12:36 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/TNocBadType/dut.sv, line:7:1, endln:13:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/TNocBadType/dut.sv, line:7:1, endln:13:10 |vpiTypespec: \_unsupported_typespec: (tnoc_common_header), line:10:11, endln:10:16 |vpiName:common_header diff --git a/tests/TaggedParam/TaggedParam.log b/tests/TaggedParam/TaggedParam.log index 3be4781772..e2b8491e82 100644 --- a/tests/TaggedParam/TaggedParam.log +++ b/tests/TaggedParam/TaggedParam.log @@ -158,7 +158,7 @@ constant 22 design 1 int_typespec 13 logic_typespec 13 -module 7 +module_inst 7 operation 11 package 3 param_assign 4 @@ -176,7 +176,7 @@ constant 22 design 1 int_typespec 13 logic_typespec 13 -module 7 +module_inst 7 operation 11 package 3 param_assign 4 @@ -295,14 +295,14 @@ design: (work@fpu_wrap) |vpiDefName:fpnew_pkg |vpiTop:1 |uhdmallModules: -\_module: work@fpnew_top (work@fpnew_top), file:${SURELOG_DIR}/tests/TaggedParam/dut.sv, line:10:2, endln:14:11 +\_module_inst: work@fpnew_top (work@fpnew_top), file:${SURELOG_DIR}/tests/TaggedParam/dut.sv, line:10:2, endln:14:11 |vpiParent: \_design: (work@fpu_wrap) |vpiFullName:work@fpnew_top |vpiParameter: \_parameter: (work@fpnew_top.Features), line:12:45, endln:12:53 |vpiParent: - \_module: work@fpnew_top (work@fpnew_top), file:${SURELOG_DIR}/tests/TaggedParam/dut.sv, line:10:2, endln:14:11 + \_module_inst: work@fpnew_top (work@fpnew_top), file:${SURELOG_DIR}/tests/TaggedParam/dut.sv, line:10:2, endln:14:11 |vpiTypespec: \_struct_typespec: (fpnew_pkg::fpu_features_t), line:3:9, endln:3:15 |vpiName:Features @@ -310,7 +310,7 @@ design: (work@fpu_wrap) |vpiParamAssign: \_param_assign: , line:12:45, endln:12:84 |vpiParent: - \_module: work@fpnew_top (work@fpnew_top), file:${SURELOG_DIR}/tests/TaggedParam/dut.sv, line:10:2, endln:14:11 + \_module_inst: work@fpnew_top (work@fpnew_top), file:${SURELOG_DIR}/tests/TaggedParam/dut.sv, line:10:2, endln:14:11 |vpiRhs: \_ref_obj: (fpnew_pkg::RV64D_Xsflt), line:12:62, endln:12:73 |vpiName:fpnew_pkg::RV64D_Xsflt @@ -318,14 +318,14 @@ design: (work@fpu_wrap) \_parameter: (work@fpnew_top.Features), line:12:45, endln:12:53 |vpiDefName:work@fpnew_top |uhdmallModules: -\_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/TaggedParam/dut.sv, line:16:1, endln:27:10 +\_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/TaggedParam/dut.sv, line:16:1, endln:27:10 |vpiParent: \_design: (work@fpu_wrap) |vpiFullName:work@fpu_wrap |vpiParameter: \_parameter: (work@fpu_wrap.FPU_FEATURES), line:18:38, endln:18:50 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/TaggedParam/dut.sv, line:16:1, endln:27:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/TaggedParam/dut.sv, line:16:1, endln:27:10 |vpiTypespec: \_struct_typespec: (fpnew_pkg::fpu_features_t), line:3:9, endln:3:15 |vpiLocalParam:1 @@ -334,7 +334,7 @@ design: (work@fpu_wrap) |vpiParamAssign: \_param_assign: , line:18:38, endln:21:6 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/TaggedParam/dut.sv, line:16:1, endln:27:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/TaggedParam/dut.sv, line:16:1, endln:27:10 |vpiRhs: \_operation: , line:18:53, endln:21:6 |vpiOpType:75 @@ -364,12 +364,12 @@ design: (work@fpu_wrap) \_parameter: (work@fpu_wrap.FPU_FEATURES), line:18:38, endln:18:50 |vpiDefName:work@fpu_wrap |uhdmtopModules: -\_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/TaggedParam/dut.sv, line:16:1, endln:27:10 +\_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/TaggedParam/dut.sv, line:16:1, endln:27:10 |vpiName:work@fpu_wrap |vpiParameter: \_parameter: (work@fpu_wrap.FPU_FEATURES), line:18:38, endln:18:50 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/TaggedParam/dut.sv, line:16:1, endln:27:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/TaggedParam/dut.sv, line:16:1, endln:27:10 |vpiTypespec: \_struct_typespec: (fpnew_pkg::fpu_features_t), line:3:9, endln:3:15 |vpiParent: @@ -416,7 +416,7 @@ design: (work@fpu_wrap) |vpiParamAssign: \_param_assign: , line:18:38, endln:21:6 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/TaggedParam/dut.sv, line:16:1, endln:27:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/TaggedParam/dut.sv, line:16:1, endln:27:10 |vpiRhs: \_operation: , line:18:53, endln:21:6 |vpiParent: @@ -483,16 +483,16 @@ design: (work@fpu_wrap) |vpiDefName:work@fpu_wrap |vpiTop:1 |vpiTopModule:1 - |vpiModule: - \_module: work@fpnew_top (work@fpu_wrap.i_fpnew_bulk), file:${SURELOG_DIR}/tests/TaggedParam/dut.sv, line:23:8, endln:25:24 + |vpiModuleInst: + \_module_inst: work@fpnew_top (work@fpu_wrap.i_fpnew_bulk), file:${SURELOG_DIR}/tests/TaggedParam/dut.sv, line:23:8, endln:25:24 |vpiParent: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/TaggedParam/dut.sv, line:16:1, endln:27:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/TaggedParam/dut.sv, line:16:1, endln:27:10 |vpiName:i_fpnew_bulk |vpiFullName:work@fpu_wrap.i_fpnew_bulk |vpiParameter: \_parameter: (work@fpu_wrap.i_fpnew_bulk.Features), line:12:45, endln:12:53 |vpiParent: - \_module: work@fpnew_top (work@fpu_wrap.i_fpnew_bulk), file:${SURELOG_DIR}/tests/TaggedParam/dut.sv, line:23:8, endln:25:24 + \_module_inst: work@fpnew_top (work@fpu_wrap.i_fpnew_bulk), file:${SURELOG_DIR}/tests/TaggedParam/dut.sv, line:23:8, endln:25:24 |vpiTypespec: \_struct_typespec: (fpnew_pkg::fpu_features_t), line:3:9, endln:3:15 |vpiParent: @@ -538,7 +538,7 @@ design: (work@fpu_wrap) |vpiParamAssign: \_param_assign: , line:12:45, endln:12:84 |vpiParent: - \_module: work@fpnew_top (work@fpu_wrap.i_fpnew_bulk), file:${SURELOG_DIR}/tests/TaggedParam/dut.sv, line:23:8, endln:25:24 + \_module_inst: work@fpnew_top (work@fpu_wrap.i_fpnew_bulk), file:${SURELOG_DIR}/tests/TaggedParam/dut.sv, line:23:8, endln:25:24 |vpiOverriden:1 |vpiRhs: \_operation: , line:24:25, endln:24:37 @@ -607,7 +607,7 @@ design: (work@fpu_wrap) |vpiDefFile:${SURELOG_DIR}/tests/TaggedParam/dut.sv |vpiDefLineNo:10 |vpiInstance: - \_module: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/TaggedParam/dut.sv, line:16:1, endln:27:10 + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/TaggedParam/dut.sv, line:16:1, endln:27:10 =================== [ FATAL] : 0 [ SYNTAX] : 0 diff --git a/tests/TaggedPattern/TaggedPattern.log b/tests/TaggedPattern/TaggedPattern.log index b373d4992e..3975381159 100644 --- a/tests/TaggedPattern/TaggedPattern.log +++ b/tests/TaggedPattern/TaggedPattern.log @@ -425,7 +425,7 @@ int_var 4 io_decl 11 logic_net 1 logic_var 1 -module 3 +module_inst 3 package 2 range 2 ref_obj 3 @@ -457,7 +457,7 @@ int_var 4 io_decl 22 logic_net 1 logic_var 1 -module 3 +module_inst 3 package 2 range 2 ref_obj 6 @@ -956,7 +956,7 @@ design: (work@top) \_int_typespec: |vpiSigned:1 |uhdmallModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/TaggedPattern/dut.sv, line:1:1, endln:14:11 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/TaggedPattern/dut.sv, line:1:1, endln:14:11 |vpiParent: \_design: (work@top) |vpiFullName:work@top @@ -964,13 +964,13 @@ design: (work@top) |vpiNet: \_logic_net: (work@top.un), line:6:4, endln:6:6 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/TaggedPattern/dut.sv, line:1:1, endln:14:11 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/TaggedPattern/dut.sv, line:1:1, endln:14:11 |vpiName:un |vpiFullName:work@top.un |vpiProcess: \_initial: , line:8:2, endln:12:5 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/TaggedPattern/dut.sv, line:1:1, endln:14:11 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/TaggedPattern/dut.sv, line:1:1, endln:14:11 |vpiStmt: \_begin: (work@top), line:8:10, endln:12:5 |vpiParent: @@ -1048,14 +1048,14 @@ design: (work@top) \_struct_net: (work@top.un), line:6:4, endln:6:6 |vpiName:$display |uhdmtopModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/TaggedPattern/dut.sv, line:1:1, endln:14:11 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/TaggedPattern/dut.sv, line:1:1, endln:14:11 |vpiName:work@top |vpiDefName:work@top |vpiTop:1 |vpiNet: \_struct_net: (work@top.un), line:6:4, endln:6:6 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/TaggedPattern/dut.sv, line:1:1, endln:14:11 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/TaggedPattern/dut.sv, line:1:1, endln:14:11 |vpiTypespec: \_union_typespec: , line:3:2, endln:3:14 |vpiPacked:1 @@ -1135,7 +1135,7 @@ design: (work@top) |vpiProcess: \_initial: , line:8:2, endln:12:5 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/TaggedPattern/dut.sv, line:1:1, endln:14:11 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/TaggedPattern/dut.sv, line:1:1, endln:14:11 |vpiStmt: \_begin: (work@top), line:8:10, endln:12:5 |vpiParent: diff --git a/tests/TaggedPatternLogic/TaggedPatternLogic.log b/tests/TaggedPatternLogic/TaggedPatternLogic.log index 341e555024..bb7492ba93 100644 --- a/tests/TaggedPatternLogic/TaggedPatternLogic.log +++ b/tests/TaggedPatternLogic/TaggedPatternLogic.log @@ -125,7 +125,7 @@ n<> u<98> t c<1> l<1:1> el<16:1> constant 37 design 1 logic_typespec 18 -module 4 +module_inst 4 operation 17 param_assign 2 parameter 3 @@ -141,7 +141,7 @@ typespec_member 18 constant 37 design 1 logic_typespec 18 -module 4 +module_inst 4 operation 17 param_assign 2 parameter 3 @@ -164,21 +164,21 @@ design: (work@top) |vpiElaborated:1 |vpiName:work@top |uhdmallModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/TaggedPatternLogic/dut.sv, line:1:1, endln:15:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/TaggedPatternLogic/dut.sv, line:1:1, endln:15:10 |vpiParent: \_design: (work@top) |vpiFullName:work@top |vpiParameter: \_parameter: (work@top.RSP_DEFAULT), line:8:23, endln:8:34 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/TaggedPatternLogic/dut.sv, line:1:1, endln:15:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/TaggedPatternLogic/dut.sv, line:1:1, endln:15:10 |vpiTypespec: \_struct_typespec: (complex_t), line:2:11, endln:2:17 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/TaggedPatternLogic/dut.sv, line:1:1, endln:15:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/TaggedPatternLogic/dut.sv, line:1:1, endln:15:10 |vpiName:complex_t |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/TaggedPatternLogic/dut.sv, line:1:1, endln:15:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/TaggedPatternLogic/dut.sv, line:1:1, endln:15:10 |vpiPacked:1 |vpiTypespecMember: \_typespec_member: (addr), line:3:17, endln:3:21 @@ -247,7 +247,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:8:23, endln:12:4 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/TaggedPatternLogic/dut.sv, line:1:1, endln:15:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/TaggedPatternLogic/dut.sv, line:1:1, endln:15:10 |vpiRhs: \_operation: , line:8:37, endln:12:4 |vpiOpType:75 @@ -300,19 +300,19 @@ design: (work@top) \_struct_typespec: (complex_t), line:2:11, endln:2:17 |vpiDefName:work@top |uhdmtopModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/TaggedPatternLogic/dut.sv, line:1:1, endln:15:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/TaggedPatternLogic/dut.sv, line:1:1, endln:15:10 |vpiName:work@top |vpiParameter: \_parameter: (work@top.RSP_DEFAULT), line:8:23, endln:8:34 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/TaggedPatternLogic/dut.sv, line:1:1, endln:15:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/TaggedPatternLogic/dut.sv, line:1:1, endln:15:10 |vpiTypespec: \_struct_typespec: (complex_t), line:2:11, endln:2:17 |vpiParent: \_parameter: (work@top.RSP_DEFAULT), line:8:23, endln:8:34 |vpiName:complex_t |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/TaggedPatternLogic/dut.sv, line:1:1, endln:15:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/TaggedPatternLogic/dut.sv, line:1:1, endln:15:10 |vpiPacked:1 |vpiTypespecMember: \_typespec_member: (addr), line:3:17, endln:3:21 @@ -381,7 +381,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:8:23, endln:12:4 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/TaggedPatternLogic/dut.sv, line:1:1, endln:15:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/TaggedPatternLogic/dut.sv, line:1:1, endln:15:10 |vpiRhs: \_operation: , line:8:37, endln:12:4 |vpiParent: diff --git a/tests/TaskBind/TaskBind.log b/tests/TaskBind/TaskBind.log index cf34b861d6..2c2e0c3d31 100644 --- a/tests/TaskBind/TaskBind.log +++ b/tests/TaskBind/TaskBind.log @@ -111,7 +111,7 @@ design 1 initial 1 integer_typespec 1 integer_var 1 -module 2 +module_inst 2 operation 1 ref_obj 3 sys_func_call 1 @@ -129,7 +129,7 @@ design 1 initial 2 integer_typespec 1 integer_var 4 -module 2 +module_inst 2 operation 2 ref_obj 6 sys_func_call 2 @@ -149,7 +149,7 @@ design: (work@tb) |vpiElaborated:1 |vpiName:work@tb |uhdmallModules: -\_module: work@tb (work@tb), file:${SURELOG_DIR}/tests/TaskBind/dut.sv, line:1:1, endln:9:10 +\_module_inst: work@tb (work@tb), file:${SURELOG_DIR}/tests/TaskBind/dut.sv, line:1:1, endln:9:10 |vpiParent: \_design: (work@tb) |vpiFullName:work@tb @@ -157,7 +157,7 @@ design: (work@tb) |vpiTaskFunc: \_task: (work@tb.display), line:4:2, endln:8:9 |vpiParent: - \_module: work@tb (work@tb), file:${SURELOG_DIR}/tests/TaskBind/dut.sv, line:1:1, endln:9:10 + \_module_inst: work@tb (work@tb), file:${SURELOG_DIR}/tests/TaskBind/dut.sv, line:1:1, endln:9:10 |vpiName:display |vpiFullName:work@tb.display |vpiVariables: @@ -173,7 +173,7 @@ design: (work@tb) |vpiVisibility:1 |vpiAutomatic:1 |vpiParent: - \_module: work@tb (work@tb), file:${SURELOG_DIR}/tests/TaskBind/dut.sv, line:1:1, endln:9:10 + \_module_inst: work@tb (work@tb), file:${SURELOG_DIR}/tests/TaskBind/dut.sv, line:1:1, endln:9:10 |vpiStmt: \_begin: (work@tb.display) |vpiParent: @@ -252,11 +252,11 @@ design: (work@tb) \_integer_var: (work@tb.display.i), line:5:10, endln:5:11 |vpiName:$display |vpiInstance: - \_module: work@tb (work@tb), file:${SURELOG_DIR}/tests/TaskBind/dut.sv, line:1:1, endln:9:10 + \_module_inst: work@tb (work@tb), file:${SURELOG_DIR}/tests/TaskBind/dut.sv, line:1:1, endln:9:10 |vpiProcess: \_initial: , line:2:2, endln:2:20 |vpiParent: - \_module: work@tb (work@tb), file:${SURELOG_DIR}/tests/TaskBind/dut.sv, line:1:1, endln:9:10 + \_module_inst: work@tb (work@tb), file:${SURELOG_DIR}/tests/TaskBind/dut.sv, line:1:1, endln:9:10 |vpiStmt: \_task_call: (display), line:2:10, endln:2:19 |vpiParent: @@ -265,14 +265,14 @@ design: (work@tb) |vpiTask: \_task: (work@tb.display), line:4:2, endln:8:9 |uhdmtopModules: -\_module: work@tb (work@tb), file:${SURELOG_DIR}/tests/TaskBind/dut.sv, line:1:1, endln:9:10 +\_module_inst: work@tb (work@tb), file:${SURELOG_DIR}/tests/TaskBind/dut.sv, line:1:1, endln:9:10 |vpiName:work@tb |vpiDefName:work@tb |vpiTop:1 |vpiTaskFunc: \_task: (work@tb.display), line:4:2, endln:8:9 |vpiParent: - \_module: work@tb (work@tb), file:${SURELOG_DIR}/tests/TaskBind/dut.sv, line:1:1, endln:9:10 + \_module_inst: work@tb (work@tb), file:${SURELOG_DIR}/tests/TaskBind/dut.sv, line:1:1, endln:9:10 |vpiName:display |vpiFullName:work@tb.display |vpiVariables: @@ -287,7 +287,7 @@ design: (work@tb) |vpiVisibility:1 |vpiAutomatic:1 |vpiParent: - \_module: work@tb (work@tb), file:${SURELOG_DIR}/tests/TaskBind/dut.sv, line:1:1, endln:9:10 + \_module_inst: work@tb (work@tb), file:${SURELOG_DIR}/tests/TaskBind/dut.sv, line:1:1, endln:9:10 |vpiStmt: \_begin: (work@tb.display) |vpiParent: @@ -362,12 +362,12 @@ design: (work@tb) \_integer_var: (work@tb.display.i), line:5:10, endln:5:11 |vpiName:$display |vpiInstance: - \_module: work@tb (work@tb), file:${SURELOG_DIR}/tests/TaskBind/dut.sv, line:1:1, endln:9:10 + \_module_inst: work@tb (work@tb), file:${SURELOG_DIR}/tests/TaskBind/dut.sv, line:1:1, endln:9:10 |vpiTopModule:1 |vpiProcess: \_initial: , line:2:2, endln:2:20 |vpiParent: - \_module: work@tb (work@tb), file:${SURELOG_DIR}/tests/TaskBind/dut.sv, line:1:1, endln:9:10 + \_module_inst: work@tb (work@tb), file:${SURELOG_DIR}/tests/TaskBind/dut.sv, line:1:1, endln:9:10 |vpiStmt: \_task_call: (display), line:2:10, endln:2:19 |vpiParent: diff --git a/tests/TaskDeclNoOrder/TaskDeclNoOrder.log b/tests/TaskDeclNoOrder/TaskDeclNoOrder.log index 147d9eb7bc..dc09aef87c 100644 --- a/tests/TaskDeclNoOrder/TaskDeclNoOrder.log +++ b/tests/TaskDeclNoOrder/TaskDeclNoOrder.log @@ -246,7 +246,7 @@ integer_var 1 io_decl 4 logic_typespec 7 logic_var 6 -module 2 +module_inst 2 range 11 task 1 === UHDM Object Stats End === @@ -263,7 +263,7 @@ integer_var 2 io_decl 8 logic_typespec 7 logic_var 21 -module 2 +module_inst 2 range 11 task 2 === UHDM Object Stats End === @@ -280,7 +280,7 @@ design: (work@dut) |vpiElaborated:1 |vpiName:work@dut |uhdmallModules: -\_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/TaskDeclNoOrder/dut.sv, line:1:1, endln:24:10 +\_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/TaskDeclNoOrder/dut.sv, line:1:1, endln:24:10 |vpiParent: \_design: (work@dut) |vpiFullName:work@dut @@ -288,7 +288,7 @@ design: (work@dut) |vpiTaskFunc: \_task: (work@dut.set_pll_fast_run), line:3:1, endln:21:8 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/TaskDeclNoOrder/dut.sv, line:1:1, endln:24:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/TaskDeclNoOrder/dut.sv, line:1:1, endln:24:10 |vpiName:set_pll_fast_run |vpiFullName:work@dut.set_pll_fast_run |vpiVariables: @@ -448,7 +448,7 @@ design: (work@dut) |vpiVisibility:1 |vpiAutomatic:1 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/TaskDeclNoOrder/dut.sv, line:1:1, endln:24:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/TaskDeclNoOrder/dut.sv, line:1:1, endln:24:10 |vpiIODecl: \_io_decl: (pll_vco1_freq_MHz), line:9:20, endln:9:37 |vpiParent: @@ -557,16 +557,16 @@ design: (work@dut) |vpiLhs: \_logic_var: (work@dut.set_pll_fast_run.fine_vco2_val), line:7:24, endln:7:37 |vpiInstance: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/TaskDeclNoOrder/dut.sv, line:1:1, endln:24:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/TaskDeclNoOrder/dut.sv, line:1:1, endln:24:10 |uhdmtopModules: -\_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/TaskDeclNoOrder/dut.sv, line:1:1, endln:24:10 +\_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/TaskDeclNoOrder/dut.sv, line:1:1, endln:24:10 |vpiName:work@dut |vpiDefName:work@dut |vpiTop:1 |vpiTaskFunc: \_task: (work@dut.set_pll_fast_run), line:3:1, endln:21:8 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/TaskDeclNoOrder/dut.sv, line:1:1, endln:24:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/TaskDeclNoOrder/dut.sv, line:1:1, endln:24:10 |vpiName:set_pll_fast_run |vpiFullName:work@dut.set_pll_fast_run |vpiVariables: @@ -631,7 +631,7 @@ design: (work@dut) |vpiVisibility:1 |vpiAutomatic:1 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/TaskDeclNoOrder/dut.sv, line:1:1, endln:24:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/TaskDeclNoOrder/dut.sv, line:1:1, endln:24:10 |vpiIODecl: \_io_decl: (pll_vco1_freq_MHz), line:9:20, endln:9:37 |vpiParent: @@ -790,7 +790,7 @@ design: (work@dut) |vpiName:fine_vco2_val |vpiFullName:work@dut.set_pll_fast_run.fine_vco2_val |vpiInstance: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/TaskDeclNoOrder/dut.sv, line:1:1, endln:24:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/TaskDeclNoOrder/dut.sv, line:1:1, endln:24:10 |vpiTopModule:1 =================== [ FATAL] : 0 diff --git a/tests/TaskDeclTypes/TaskDeclTypes.log b/tests/TaskDeclTypes/TaskDeclTypes.log index 3c3131c6ac..186ba1ded3 100644 --- a/tests/TaskDeclTypes/TaskDeclTypes.log +++ b/tests/TaskDeclTypes/TaskDeclTypes.log @@ -89,7 +89,7 @@ design 1 int_typespec 1 io_decl 3 logic_typespec 1 -module 2 +module_inst 2 range 2 string_typespec 1 task 1 @@ -102,7 +102,7 @@ design 1 int_typespec 1 io_decl 6 logic_typespec 1 -module 2 +module_inst 2 range 3 string_typespec 1 task 2 @@ -120,7 +120,7 @@ design: (work@top) |vpiElaborated:1 |vpiName:work@top |uhdmallModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/TaskDeclTypes/dut.sv, line:1:1, endln:7:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/TaskDeclTypes/dut.sv, line:1:1, endln:7:10 |vpiParent: \_design: (work@top) |vpiFullName:work@top @@ -128,12 +128,12 @@ design: (work@top) |vpiTaskFunc: \_task: (work@top.simutil_memload), line:2:3, endln:6:10 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/TaskDeclTypes/dut.sv, line:1:1, endln:7:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/TaskDeclTypes/dut.sv, line:1:1, endln:7:10 |vpiName:simutil_memload |vpiFullName:work@top.simutil_memload |vpiVisibility:1 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/TaskDeclTypes/dut.sv, line:1:1, endln:7:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/TaskDeclTypes/dut.sv, line:1:1, endln:7:10 |vpiIODecl: \_io_decl: (file), line:3:18, endln:3:22 |vpiParent: @@ -200,21 +200,21 @@ design: (work@top) |UINT:0 |vpiConstType:9 |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/TaskDeclTypes/dut.sv, line:1:1, endln:7:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/TaskDeclTypes/dut.sv, line:1:1, endln:7:10 |uhdmtopModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/TaskDeclTypes/dut.sv, line:1:1, endln:7:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/TaskDeclTypes/dut.sv, line:1:1, endln:7:10 |vpiName:work@top |vpiDefName:work@top |vpiTop:1 |vpiTaskFunc: \_task: (work@top.simutil_memload), line:2:3, endln:6:10 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/TaskDeclTypes/dut.sv, line:1:1, endln:7:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/TaskDeclTypes/dut.sv, line:1:1, endln:7:10 |vpiName:simutil_memload |vpiFullName:work@top.simutil_memload |vpiVisibility:1 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/TaskDeclTypes/dut.sv, line:1:1, endln:7:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/TaskDeclTypes/dut.sv, line:1:1, endln:7:10 |vpiIODecl: \_io_decl: (file), line:3:18, endln:3:22 |vpiParent: @@ -248,7 +248,7 @@ design: (work@top) |vpiTypedef: \_logic_typespec: , line:5:11, endln:5:16 |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/TaskDeclTypes/dut.sv, line:1:1, endln:7:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/TaskDeclTypes/dut.sv, line:1:1, endln:7:10 |vpiTopModule:1 =================== [ FATAL] : 0 diff --git a/tests/TaskDecls/TaskDecls.log b/tests/TaskDecls/TaskDecls.log index 226d499888..9207bc304b 100644 --- a/tests/TaskDecls/TaskDecls.log +++ b/tests/TaskDecls/TaskDecls.log @@ -532,7 +532,7 @@ integer_var 1 io_decl 15 logic_typespec 3 logic_var 1 -module 5 +module_inst 5 operation 3 package 5 param_assign 3 @@ -564,7 +564,7 @@ integer_var 2 io_decl 30 logic_typespec 3 logic_var 1 -module 5 +module_inst 5 operation 5 package 5 param_assign 4 @@ -1284,14 +1284,14 @@ design: (work@gen_errors) \_int_typespec: |vpiSigned:1 |uhdmallModules: -\_module: work@gen_errors (work@gen_errors), file:${SURELOG_DIR}/tests/TaskDecls/dut.sv, line:18:1, endln:38:10 +\_module_inst: work@gen_errors (work@gen_errors), file:${SURELOG_DIR}/tests/TaskDecls/dut.sv, line:18:1, endln:38:10 |vpiParent: \_design: (work@gen_errors) |vpiFullName:work@gen_errors |vpiParameter: \_parameter: (work@gen_errors.width_a), line:19:12, endln:19:19 |vpiParent: - \_module: work@gen_errors (work@gen_errors), file:${SURELOG_DIR}/tests/TaskDecls/dut.sv, line:18:1, endln:38:10 + \_module_inst: work@gen_errors (work@gen_errors), file:${SURELOG_DIR}/tests/TaskDecls/dut.sv, line:18:1, endln:38:10 |UINT:8 |vpiTypespec: \_int_typespec: @@ -1300,7 +1300,7 @@ design: (work@gen_errors) |vpiParamAssign: \_param_assign: , line:19:12, endln:19:23 |vpiParent: - \_module: work@gen_errors (work@gen_errors), file:${SURELOG_DIR}/tests/TaskDecls/dut.sv, line:18:1, endln:38:10 + \_module_inst: work@gen_errors (work@gen_errors), file:${SURELOG_DIR}/tests/TaskDecls/dut.sv, line:18:1, endln:38:10 |vpiRhs: \_constant: , line:19:22, endln:19:23 |vpiDecompile:8 @@ -1315,7 +1315,7 @@ design: (work@gen_errors) |vpiTaskFunc: \_task: (work@gen_errors.A), line:20:4, endln:35:11 |vpiParent: - \_module: work@gen_errors (work@gen_errors), file:${SURELOG_DIR}/tests/TaskDecls/dut.sv, line:18:1, endln:38:10 + \_module_inst: work@gen_errors (work@gen_errors), file:${SURELOG_DIR}/tests/TaskDecls/dut.sv, line:18:1, endln:38:10 |vpiName:A |vpiFullName:work@gen_errors.A |vpiVariables: @@ -1346,7 +1346,7 @@ design: (work@gen_errors) |vpiName:llen |vpiVisibility:1 |vpiParent: - \_module: work@gen_errors (work@gen_errors), file:${SURELOG_DIR}/tests/TaskDecls/dut.sv, line:18:1, endln:38:10 + \_module_inst: work@gen_errors (work@gen_errors), file:${SURELOG_DIR}/tests/TaskDecls/dut.sv, line:18:1, endln:38:10 |vpiIODecl: \_io_decl: (l), line:21:26, endln:21:27 |vpiParent: @@ -1467,14 +1467,14 @@ design: (work@gen_errors) |vpiActual: \_io_decl: (C), line:25:14, endln:25:15 |vpiInstance: - \_module: work@gen_errors (work@gen_errors), file:${SURELOG_DIR}/tests/TaskDecls/dut.sv, line:18:1, endln:38:10 + \_module_inst: work@gen_errors (work@gen_errors), file:${SURELOG_DIR}/tests/TaskDecls/dut.sv, line:18:1, endln:38:10 |uhdmtopModules: -\_module: work@gen_errors (work@gen_errors), file:${SURELOG_DIR}/tests/TaskDecls/dut.sv, line:18:1, endln:38:10 +\_module_inst: work@gen_errors (work@gen_errors), file:${SURELOG_DIR}/tests/TaskDecls/dut.sv, line:18:1, endln:38:10 |vpiName:work@gen_errors |vpiParameter: \_parameter: (work@gen_errors.width_a), line:19:12, endln:19:19 |vpiParent: - \_module: work@gen_errors (work@gen_errors), file:${SURELOG_DIR}/tests/TaskDecls/dut.sv, line:18:1, endln:38:10 + \_module_inst: work@gen_errors (work@gen_errors), file:${SURELOG_DIR}/tests/TaskDecls/dut.sv, line:18:1, endln:38:10 |UINT:8 |vpiTypespec: \_int_typespec: @@ -1485,7 +1485,7 @@ design: (work@gen_errors) |vpiParamAssign: \_param_assign: , line:19:12, endln:19:23 |vpiParent: - \_module: work@gen_errors (work@gen_errors), file:${SURELOG_DIR}/tests/TaskDecls/dut.sv, line:18:1, endln:38:10 + \_module_inst: work@gen_errors (work@gen_errors), file:${SURELOG_DIR}/tests/TaskDecls/dut.sv, line:18:1, endln:38:10 |vpiRhs: \_constant: , line:19:22, endln:19:23 |vpiDecompile:8 @@ -1501,7 +1501,7 @@ design: (work@gen_errors) |vpiTaskFunc: \_task: (work@gen_errors.A), line:20:4, endln:35:11 |vpiParent: - \_module: work@gen_errors (work@gen_errors), file:${SURELOG_DIR}/tests/TaskDecls/dut.sv, line:18:1, endln:38:10 + \_module_inst: work@gen_errors (work@gen_errors), file:${SURELOG_DIR}/tests/TaskDecls/dut.sv, line:18:1, endln:38:10 |vpiName:A |vpiFullName:work@gen_errors.A |vpiVariables: @@ -1529,7 +1529,7 @@ design: (work@gen_errors) |vpiFullName:work@gen_errors.A.llen |vpiVisibility:1 |vpiParent: - \_module: work@gen_errors (work@gen_errors), file:${SURELOG_DIR}/tests/TaskDecls/dut.sv, line:18:1, endln:38:10 + \_module_inst: work@gen_errors (work@gen_errors), file:${SURELOG_DIR}/tests/TaskDecls/dut.sv, line:18:1, endln:38:10 |vpiIODecl: \_io_decl: (l), line:21:26, endln:21:27 |vpiParent: @@ -1595,7 +1595,7 @@ design: (work@gen_errors) |vpiActual: \_io_decl: (C), line:25:14, endln:25:15 |vpiInstance: - \_module: work@gen_errors (work@gen_errors), file:${SURELOG_DIR}/tests/TaskDecls/dut.sv, line:18:1, endln:38:10 + \_module_inst: work@gen_errors (work@gen_errors), file:${SURELOG_DIR}/tests/TaskDecls/dut.sv, line:18:1, endln:38:10 |vpiTopModule:1 =================== [ FATAL] : 0 diff --git a/tests/TaskProto/TaskProto.log b/tests/TaskProto/TaskProto.log index 95021f990f..816dc35bc5 100644 --- a/tests/TaskProto/TaskProto.log +++ b/tests/TaskProto/TaskProto.log @@ -85,7 +85,7 @@ int_typespec 4 int_var 1 io_decl 1 logic_net 1 -module 2 +module_inst 2 port 2 ref_obj 3 task 1 @@ -101,7 +101,7 @@ int_typespec 4 int_var 1 io_decl 2 logic_net 1 -module 2 +module_inst 2 port 3 ref_obj 5 task 2 @@ -120,7 +120,7 @@ design: (work@top) |vpiElaborated:1 |vpiName:work@top |uhdmallModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/TaskProto/dut.sv, line:1:1, endln:7:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/TaskProto/dut.sv, line:1:1, endln:7:10 |vpiParent: \_design: (work@top) |vpiFullName:work@top @@ -128,14 +128,14 @@ design: (work@top) |vpiTaskFunc: \_task: (work@top.test_output_argument), line:2:4, endln:2:59 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/TaskProto/dut.sv, line:1:1, endln:7:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/TaskProto/dut.sv, line:1:1, endln:7:10 |vpiName:test_output_argument |vpiFullName:work@top.test_output_argument |vpiAccessType:4 |vpiVisibility:1 |vpiDPICStr:2 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/TaskProto/dut.sv, line:1:1, endln:7:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/TaskProto/dut.sv, line:1:1, endln:7:10 |vpiIODecl: \_io_decl: (o), line:2:56, endln:2:57 |vpiDirection:2 @@ -144,17 +144,17 @@ design: (work@top) \_int_typespec: , line:2:52, endln:2:55 |vpiSigned:1 |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/TaskProto/dut.sv, line:1:1, endln:7:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/TaskProto/dut.sv, line:1:1, endln:7:10 |vpiNet: \_logic_net: (work@top.a), line:1:23, endln:1:24 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/TaskProto/dut.sv, line:1:1, endln:7:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/TaskProto/dut.sv, line:1:1, endln:7:10 |vpiName:a |vpiFullName:work@top.a |vpiPort: \_port: (a), line:1:23, endln:1:24 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/TaskProto/dut.sv, line:1:1, endln:7:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/TaskProto/dut.sv, line:1:1, endln:7:10 |vpiName:a |vpiDirection:2 |vpiLowConn: @@ -167,7 +167,7 @@ design: (work@top) |vpiProcess: \_initial: , line:4:4, endln:6:7 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/TaskProto/dut.sv, line:1:1, endln:7:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/TaskProto/dut.sv, line:1:1, endln:7:10 |vpiStmt: \_begin: (work@top), line:4:12, endln:6:7 |vpiParent: @@ -189,12 +189,12 @@ design: (work@top) |vpiTask: \_task: (work@top.test_output_argument), line:2:4, endln:2:59 |uhdmtopModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/TaskProto/dut.sv, line:1:1, endln:7:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/TaskProto/dut.sv, line:1:1, endln:7:10 |vpiName:work@top |vpiVariables: \_int_var: (work@top.a), line:1:23, endln:1:24 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/TaskProto/dut.sv, line:1:1, endln:7:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/TaskProto/dut.sv, line:1:1, endln:7:10 |vpiTypespec: \_int_typespec: , line:1:19, endln:1:22 |vpiSigned:1 @@ -207,14 +207,14 @@ design: (work@top) |vpiTaskFunc: \_task: (work@top.test_output_argument), line:2:4, endln:2:59 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/TaskProto/dut.sv, line:1:1, endln:7:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/TaskProto/dut.sv, line:1:1, endln:7:10 |vpiName:test_output_argument |vpiFullName:work@top.test_output_argument |vpiAccessType:4 |vpiVisibility:1 |vpiDPICStr:2 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/TaskProto/dut.sv, line:1:1, endln:7:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/TaskProto/dut.sv, line:1:1, endln:7:10 |vpiIODecl: \_io_decl: (o), line:2:56, endln:2:57 |vpiParent: @@ -224,12 +224,12 @@ design: (work@top) |vpiTypedef: \_int_typespec: , line:2:52, endln:2:55 |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/TaskProto/dut.sv, line:1:1, endln:7:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/TaskProto/dut.sv, line:1:1, endln:7:10 |vpiTopModule:1 |vpiPort: \_port: (a), line:1:23, endln:1:24 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/TaskProto/dut.sv, line:1:1, endln:7:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/TaskProto/dut.sv, line:1:1, endln:7:10 |vpiName:a |vpiDirection:2 |vpiLowConn: @@ -244,11 +244,11 @@ design: (work@top) \_int_typespec: , line:1:19, endln:1:22 |vpiSigned:1 |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/TaskProto/dut.sv, line:1:1, endln:7:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/TaskProto/dut.sv, line:1:1, endln:7:10 |vpiProcess: \_initial: , line:4:4, endln:6:7 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/TaskProto/dut.sv, line:1:1, endln:7:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/TaskProto/dut.sv, line:1:1, endln:7:10 |vpiStmt: \_begin: (work@top), line:4:12, endln:6:7 |vpiParent: diff --git a/tests/TaskProtoDef/TaskProtoDef.log b/tests/TaskProtoDef/TaskProtoDef.log index 484a86fbe4..2283af9200 100644 --- a/tests/TaskProtoDef/TaskProtoDef.log +++ b/tests/TaskProtoDef/TaskProtoDef.log @@ -62,7 +62,7 @@ n<> u<35> t c<1> l<1:1> el<7:1> design 1 function 1 io_decl 1 -module 2 +module_inst 2 string_typespec 1 === UHDM Object Stats End === [INF:UH0707] Elaborating UHDM... @@ -71,7 +71,7 @@ string_typespec 1 design 1 function 2 io_decl 2 -module 2 +module_inst 2 string_typespec 1 === UHDM Object Stats End === [INF:UH0708] Writing UHDM DB: ${SURELOG_DIR}/build/regression/TaskProtoDef/slpp_all/surelog.uhdm ... @@ -87,7 +87,7 @@ design: (work@top) |vpiElaborated:1 |vpiName:work@top |uhdmallModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/TaskProtoDef/dut.sv, line:1:1, endln:6:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/TaskProtoDef/dut.sv, line:1:1, endln:6:10 |vpiParent: \_design: (work@top) |vpiFullName:work@top @@ -95,14 +95,14 @@ design: (work@top) |vpiTaskFunc: \_function: (work@top.simutil_memload), line:3:4, endln:5:11 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/TaskProtoDef/dut.sv, line:1:1, endln:6:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/TaskProtoDef/dut.sv, line:1:1, endln:6:10 |vpiName:simutil_memload |vpiFullName:work@top.simutil_memload |vpiAccessType:3 |vpiVisibility:1 |vpiDPICStr:2 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/TaskProtoDef/dut.sv, line:1:1, endln:6:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/TaskProtoDef/dut.sv, line:1:1, endln:6:10 |vpiIODecl: \_io_decl: (file), line:4:20, endln:4:24 |vpiParent: @@ -112,23 +112,23 @@ design: (work@top) |vpiTypedef: \_string_typespec: , line:4:13, endln:4:19 |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/TaskProtoDef/dut.sv, line:1:1, endln:6:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/TaskProtoDef/dut.sv, line:1:1, endln:6:10 |uhdmtopModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/TaskProtoDef/dut.sv, line:1:1, endln:6:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/TaskProtoDef/dut.sv, line:1:1, endln:6:10 |vpiName:work@top |vpiDefName:work@top |vpiTop:1 |vpiTaskFunc: \_function: (work@top.simutil_memload), line:3:4, endln:5:11 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/TaskProtoDef/dut.sv, line:1:1, endln:6:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/TaskProtoDef/dut.sv, line:1:1, endln:6:10 |vpiName:simutil_memload |vpiFullName:work@top.simutil_memload |vpiAccessType:3 |vpiVisibility:1 |vpiDPICStr:2 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/TaskProtoDef/dut.sv, line:1:1, endln:6:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/TaskProtoDef/dut.sv, line:1:1, endln:6:10 |vpiIODecl: \_io_decl: (file), line:4:20, endln:4:24 |vpiParent: @@ -138,7 +138,7 @@ design: (work@top) |vpiTypedef: \_string_typespec: , line:4:13, endln:4:19 |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/TaskProtoDef/dut.sv, line:1:1, endln:6:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/TaskProtoDef/dut.sv, line:1:1, endln:6:10 |vpiTopModule:1 =================== [ FATAL] : 0 diff --git a/tests/Ternary/Ternary.log b/tests/Ternary/Ternary.log index 03f151503e..ede1d7816d 100644 --- a/tests/Ternary/Ternary.log +++ b/tests/Ternary/Ternary.log @@ -1177,7 +1177,7 @@ io_decl 11 logic_net 22 logic_typespec 13 logic_var 1 -module 5 +module_inst 5 operation 15 package 2 param_assign 26 @@ -1215,7 +1215,7 @@ io_decl 22 logic_net 22 logic_typespec 13 logic_var 1 -module 5 +module_inst 5 operation 30 package 2 param_assign 26 @@ -1714,14 +1714,14 @@ design: (work@test) \_int_typespec: |vpiSigned:1 |uhdmallModules: -\_module: work@test (work@test), file:${SURELOG_DIR}/tests/Ternary/top.sv, line:3:1, endln:85:10 +\_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/Ternary/top.sv, line:3:1, endln:85:10 |vpiParent: \_design: (work@test) |vpiFullName:work@test |vpiParameter: \_parameter: (work@test.FRAME_LENGTH), line:9:16, endln:9:28 |vpiParent: - \_module: work@test (work@test), file:${SURELOG_DIR}/tests/Ternary/top.sv, line:3:1, endln:85:10 + \_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/Ternary/top.sv, line:3:1, endln:85:10 |UINT:15 |vpiTypespec: \_int_typespec: @@ -1731,7 +1731,7 @@ design: (work@test) |vpiParameter: \_parameter: (work@test.ESTABLISHED), line:10:16, endln:10:27 |vpiParent: - \_module: work@test (work@test), file:${SURELOG_DIR}/tests/Ternary/top.sv, line:3:1, endln:85:10 + \_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/Ternary/top.sv, line:3:1, endln:85:10 |HEX:0003 |vpiTypespec: \_int_typespec: @@ -1749,7 +1749,7 @@ design: (work@test) |vpiParameter: \_parameter: (work@test.USER_DELAY_INIT), line:24:16, endln:24:31 |vpiParent: - \_module: work@test (work@test), file:${SURELOG_DIR}/tests/Ternary/top.sv, line:3:1, endln:85:10 + \_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/Ternary/top.sv, line:3:1, endln:85:10 |HEX:001 |vpiTypespec: \_int_typespec: @@ -1767,7 +1767,7 @@ design: (work@test) |vpiParameter: \_parameter: (work@test.USER_CLEAN), line:25:16, endln:25:26 |vpiParent: - \_module: work@test (work@test), file:${SURELOG_DIR}/tests/Ternary/top.sv, line:3:1, endln:85:10 + \_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/Ternary/top.sv, line:3:1, endln:85:10 |HEX:002 |vpiTypespec: \_int_typespec: @@ -1785,7 +1785,7 @@ design: (work@test) |vpiParameter: \_parameter: (work@test.USER_CLEAN_CHECK), line:26:16, endln:26:32 |vpiParent: - \_module: work@test (work@test), file:${SURELOG_DIR}/tests/Ternary/top.sv, line:3:1, endln:85:10 + \_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/Ternary/top.sv, line:3:1, endln:85:10 |HEX:004 |vpiTypespec: \_int_typespec: @@ -1803,7 +1803,7 @@ design: (work@test) |vpiParameter: \_parameter: (work@test.USER_CLEAR_INTS), line:27:16, endln:27:31 |vpiParent: - \_module: work@test (work@test), file:${SURELOG_DIR}/tests/Ternary/top.sv, line:3:1, endln:85:10 + \_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/Ternary/top.sv, line:3:1, endln:85:10 |HEX:008 |vpiTypespec: \_int_typespec: @@ -1821,7 +1821,7 @@ design: (work@test) |vpiParameter: \_parameter: (work@test.USER_INIT), line:28:16, endln:28:25 |vpiParent: - \_module: work@test (work@test), file:${SURELOG_DIR}/tests/Ternary/top.sv, line:3:1, endln:85:10 + \_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/Ternary/top.sv, line:3:1, endln:85:10 |HEX:010 |vpiTypespec: \_int_typespec: @@ -1839,7 +1839,7 @@ design: (work@test) |vpiParameter: \_parameter: (work@test.USER_IDLE), line:29:16, endln:29:25 |vpiParent: - \_module: work@test (work@test), file:${SURELOG_DIR}/tests/Ternary/top.sv, line:3:1, endln:85:10 + \_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/Ternary/top.sv, line:3:1, endln:85:10 |HEX:020 |vpiTypespec: \_int_typespec: @@ -1857,7 +1857,7 @@ design: (work@test) |vpiParameter: \_parameter: (work@test.USER_CHECK_STATE), line:30:16, endln:30:32 |vpiParent: - \_module: work@test (work@test), file:${SURELOG_DIR}/tests/Ternary/top.sv, line:3:1, endln:85:10 + \_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/Ternary/top.sv, line:3:1, endln:85:10 |HEX:040 |vpiTypespec: \_int_typespec: @@ -1875,7 +1875,7 @@ design: (work@test) |vpiParameter: \_parameter: (work@test.USER_CHECK_SPACE), line:31:16, endln:31:32 |vpiParent: - \_module: work@test (work@test), file:${SURELOG_DIR}/tests/Ternary/top.sv, line:3:1, endln:85:10 + \_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/Ternary/top.sv, line:3:1, endln:85:10 |HEX:080 |vpiTypespec: \_int_typespec: @@ -1893,7 +1893,7 @@ design: (work@test) |vpiParameter: \_parameter: (work@test.USER_WRITE_DATA), line:32:16, endln:32:31 |vpiParent: - \_module: work@test (work@test), file:${SURELOG_DIR}/tests/Ternary/top.sv, line:3:1, endln:85:10 + \_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/Ternary/top.sv, line:3:1, endln:85:10 |HEX:100 |vpiTypespec: \_int_typespec: @@ -1911,7 +1911,7 @@ design: (work@test) |vpiParameter: \_parameter: (work@test.USER_READ_LENGTH), line:33:16, endln:33:32 |vpiParent: - \_module: work@test (work@test), file:${SURELOG_DIR}/tests/Ternary/top.sv, line:3:1, endln:85:10 + \_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/Ternary/top.sv, line:3:1, endln:85:10 |HEX:200 |vpiTypespec: \_int_typespec: @@ -1929,7 +1929,7 @@ design: (work@test) |vpiParameter: \_parameter: (work@test.USER_READ_DATA), line:34:16, endln:34:30 |vpiParent: - \_module: work@test (work@test), file:${SURELOG_DIR}/tests/Ternary/top.sv, line:3:1, endln:85:10 + \_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/Ternary/top.sv, line:3:1, endln:85:10 |HEX:400 |vpiTypespec: \_int_typespec: @@ -1947,7 +1947,7 @@ design: (work@test) |vpiParamAssign: \_param_assign: , line:9:16, endln:9:33 |vpiParent: - \_module: work@test (work@test), file:${SURELOG_DIR}/tests/Ternary/top.sv, line:3:1, endln:85:10 + \_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/Ternary/top.sv, line:3:1, endln:85:10 |vpiRhs: \_constant: , line:9:31, endln:9:33 |vpiDecompile:15 @@ -1961,7 +1961,7 @@ design: (work@test) |vpiParamAssign: \_param_assign: , line:10:16, endln:10:39 |vpiParent: - \_module: work@test (work@test), file:${SURELOG_DIR}/tests/Ternary/top.sv, line:3:1, endln:85:10 + \_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/Ternary/top.sv, line:3:1, endln:85:10 |vpiRhs: \_constant: , line:10:31, endln:10:39 |vpiDecompile:16'h0003 @@ -1975,7 +1975,7 @@ design: (work@test) |vpiParamAssign: \_param_assign: , line:24:16, endln:24:42 |vpiParent: - \_module: work@test (work@test), file:${SURELOG_DIR}/tests/Ternary/top.sv, line:3:1, endln:85:10 + \_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/Ternary/top.sv, line:3:1, endln:85:10 |vpiRhs: \_constant: , line:24:35, endln:24:42 |vpiDecompile:11'h001 @@ -1989,7 +1989,7 @@ design: (work@test) |vpiParamAssign: \_param_assign: , line:25:16, endln:25:42 |vpiParent: - \_module: work@test (work@test), file:${SURELOG_DIR}/tests/Ternary/top.sv, line:3:1, endln:85:10 + \_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/Ternary/top.sv, line:3:1, endln:85:10 |vpiRhs: \_constant: , line:25:35, endln:25:42 |vpiDecompile:11'h002 @@ -2003,7 +2003,7 @@ design: (work@test) |vpiParamAssign: \_param_assign: , line:26:16, endln:26:42 |vpiParent: - \_module: work@test (work@test), file:${SURELOG_DIR}/tests/Ternary/top.sv, line:3:1, endln:85:10 + \_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/Ternary/top.sv, line:3:1, endln:85:10 |vpiRhs: \_constant: , line:26:35, endln:26:42 |vpiDecompile:11'h004 @@ -2017,7 +2017,7 @@ design: (work@test) |vpiParamAssign: \_param_assign: , line:27:16, endln:27:42 |vpiParent: - \_module: work@test (work@test), file:${SURELOG_DIR}/tests/Ternary/top.sv, line:3:1, endln:85:10 + \_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/Ternary/top.sv, line:3:1, endln:85:10 |vpiRhs: \_constant: , line:27:35, endln:27:42 |vpiDecompile:11'h008 @@ -2031,7 +2031,7 @@ design: (work@test) |vpiParamAssign: \_param_assign: , line:28:16, endln:28:42 |vpiParent: - \_module: work@test (work@test), file:${SURELOG_DIR}/tests/Ternary/top.sv, line:3:1, endln:85:10 + \_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/Ternary/top.sv, line:3:1, endln:85:10 |vpiRhs: \_constant: , line:28:35, endln:28:42 |vpiDecompile:11'h010 @@ -2045,7 +2045,7 @@ design: (work@test) |vpiParamAssign: \_param_assign: , line:29:16, endln:29:42 |vpiParent: - \_module: work@test (work@test), file:${SURELOG_DIR}/tests/Ternary/top.sv, line:3:1, endln:85:10 + \_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/Ternary/top.sv, line:3:1, endln:85:10 |vpiRhs: \_constant: , line:29:35, endln:29:42 |vpiDecompile:11'h020 @@ -2059,7 +2059,7 @@ design: (work@test) |vpiParamAssign: \_param_assign: , line:30:16, endln:30:42 |vpiParent: - \_module: work@test (work@test), file:${SURELOG_DIR}/tests/Ternary/top.sv, line:3:1, endln:85:10 + \_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/Ternary/top.sv, line:3:1, endln:85:10 |vpiRhs: \_constant: , line:30:35, endln:30:42 |vpiDecompile:11'h040 @@ -2073,7 +2073,7 @@ design: (work@test) |vpiParamAssign: \_param_assign: , line:31:16, endln:31:42 |vpiParent: - \_module: work@test (work@test), file:${SURELOG_DIR}/tests/Ternary/top.sv, line:3:1, endln:85:10 + \_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/Ternary/top.sv, line:3:1, endln:85:10 |vpiRhs: \_constant: , line:31:35, endln:31:42 |vpiDecompile:11'h080 @@ -2087,7 +2087,7 @@ design: (work@test) |vpiParamAssign: \_param_assign: , line:32:16, endln:32:42 |vpiParent: - \_module: work@test (work@test), file:${SURELOG_DIR}/tests/Ternary/top.sv, line:3:1, endln:85:10 + \_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/Ternary/top.sv, line:3:1, endln:85:10 |vpiRhs: \_constant: , line:32:35, endln:32:42 |vpiDecompile:11'h100 @@ -2101,7 +2101,7 @@ design: (work@test) |vpiParamAssign: \_param_assign: , line:33:16, endln:33:42 |vpiParent: - \_module: work@test (work@test), file:${SURELOG_DIR}/tests/Ternary/top.sv, line:3:1, endln:85:10 + \_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/Ternary/top.sv, line:3:1, endln:85:10 |vpiRhs: \_constant: , line:33:35, endln:33:42 |vpiDecompile:11'h200 @@ -2115,7 +2115,7 @@ design: (work@test) |vpiParamAssign: \_param_assign: , line:34:16, endln:34:42 |vpiParent: - \_module: work@test (work@test), file:${SURELOG_DIR}/tests/Ternary/top.sv, line:3:1, endln:85:10 + \_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/Ternary/top.sv, line:3:1, endln:85:10 |vpiRhs: \_constant: , line:34:35, endln:34:42 |vpiDecompile:11'h400 @@ -2130,83 +2130,83 @@ design: (work@test) |vpiNet: \_logic_net: (work@test.CLK), line:6:11, endln:6:14 |vpiParent: - \_module: work@test (work@test), file:${SURELOG_DIR}/tests/Ternary/top.sv, line:3:1, endln:85:10 + \_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/Ternary/top.sv, line:3:1, endln:85:10 |vpiName:CLK |vpiFullName:work@test.CLK |vpiNet: \_logic_net: (work@test.RAMRST), line:12:10, endln:12:16 |vpiParent: - \_module: work@test (work@test), file:${SURELOG_DIR}/tests/Ternary/top.sv, line:3:1, endln:85:10 + \_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/Ternary/top.sv, line:3:1, endln:85:10 |vpiName:RAMRST |vpiFullName:work@test.RAMRST |vpiNetType:1 |vpiNet: \_logic_net: (work@test.UserReadData), line:13:17, endln:13:29 |vpiParent: - \_module: work@test (work@test), file:${SURELOG_DIR}/tests/Ternary/top.sv, line:3:1, endln:85:10 + \_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/Ternary/top.sv, line:3:1, endln:85:10 |vpiName:UserReadData |vpiFullName:work@test.UserReadData |vpiNetType:1 |vpiNet: \_logic_net: (work@test.UserReadDataValid), line:14:10, endln:14:27 |vpiParent: - \_module: work@test (work@test), file:${SURELOG_DIR}/tests/Ternary/top.sv, line:3:1, endln:85:10 + \_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/Ternary/top.sv, line:3:1, endln:85:10 |vpiName:UserReadDataValid |vpiFullName:work@test.UserReadDataValid |vpiNetType:1 |vpiNet: \_logic_net: (work@test.Delay), line:16:16, endln:16:21 |vpiParent: - \_module: work@test (work@test), file:${SURELOG_DIR}/tests/Ternary/top.sv, line:3:1, endln:85:10 + \_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/Ternary/top.sv, line:3:1, endln:85:10 |vpiName:Delay |vpiFullName:work@test.Delay |vpiNetType:48 |vpiNet: \_logic_net: (work@test.UserState), line:17:16, endln:17:25 |vpiParent: - \_module: work@test (work@test), file:${SURELOG_DIR}/tests/Ternary/top.sv, line:3:1, endln:85:10 + \_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/Ternary/top.sv, line:3:1, endln:85:10 |vpiName:UserState |vpiFullName:work@test.UserState |vpiNetType:48 |vpiNet: \_logic_net: (work@test.UserValidCount), line:18:16, endln:18:30 |vpiParent: - \_module: work@test (work@test), file:${SURELOG_DIR}/tests/Ternary/top.sv, line:3:1, endln:85:10 + \_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/Ternary/top.sv, line:3:1, endln:85:10 |vpiName:UserValidCount |vpiFullName:work@test.UserValidCount |vpiNetType:48 |vpiNet: \_logic_net: (work@test.ConnectionState), line:19:15, endln:19:30 |vpiParent: - \_module: work@test (work@test), file:${SURELOG_DIR}/tests/Ternary/top.sv, line:3:1, endln:85:10 + \_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/Ternary/top.sv, line:3:1, endln:85:10 |vpiName:ConnectionState |vpiFullName:work@test.ConnectionState |vpiNetType:48 |vpiNet: \_logic_net: (work@test.InterruptStatus), line:20:16, endln:20:31 |vpiParent: - \_module: work@test (work@test), file:${SURELOG_DIR}/tests/Ternary/top.sv, line:3:1, endln:85:10 + \_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/Ternary/top.sv, line:3:1, endln:85:10 |vpiName:InterruptStatus |vpiFullName:work@test.InterruptStatus |vpiNetType:48 |vpiNet: \_logic_net: (work@test.FrameLength), line:21:16, endln:21:27 |vpiParent: - \_module: work@test (work@test), file:${SURELOG_DIR}/tests/Ternary/top.sv, line:3:1, endln:85:10 + \_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/Ternary/top.sv, line:3:1, endln:85:10 |vpiName:FrameLength |vpiFullName:work@test.FrameLength |vpiNetType:48 |vpiNet: \_logic_net: (work@test.LatencyDelay), line:22:15, endln:22:27 |vpiParent: - \_module: work@test (work@test), file:${SURELOG_DIR}/tests/Ternary/top.sv, line:3:1, endln:85:10 + \_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/Ternary/top.sv, line:3:1, endln:85:10 |vpiName:LatencyDelay |vpiFullName:work@test.LatencyDelay |vpiNetType:48 |vpiPort: \_port: (CLK), line:6:11, endln:6:14 |vpiParent: - \_module: work@test (work@test), file:${SURELOG_DIR}/tests/Ternary/top.sv, line:3:1, endln:85:10 + \_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/Ternary/top.sv, line:3:1, endln:85:10 |vpiName:CLK |vpiDirection:1 |vpiLowConn: @@ -2218,7 +2218,7 @@ design: (work@test) |vpiProcess: \_always: , line:37:5, endln:83:8 |vpiParent: - \_module: work@test (work@test), file:${SURELOG_DIR}/tests/Ternary/top.sv, line:3:1, endln:85:10 + \_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/Ternary/top.sv, line:3:1, endln:85:10 |vpiStmt: \_event_control: , line:37:12, endln:37:45 |vpiParent: @@ -2893,12 +2893,12 @@ design: (work@test) \_logic_net: (work@test.UserState), line:17:16, endln:17:25 |vpiAlwaysType:1 |uhdmtopModules: -\_module: work@test (work@test), file:${SURELOG_DIR}/tests/Ternary/top.sv, line:3:1, endln:85:10 +\_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/Ternary/top.sv, line:3:1, endln:85:10 |vpiName:work@test |vpiParameter: \_parameter: (work@test.FRAME_LENGTH), line:9:16, endln:9:28 |vpiParent: - \_module: work@test (work@test), file:${SURELOG_DIR}/tests/Ternary/top.sv, line:3:1, endln:85:10 + \_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/Ternary/top.sv, line:3:1, endln:85:10 |UINT:15 |vpiTypespec: \_int_typespec: @@ -2910,7 +2910,7 @@ design: (work@test) |vpiParameter: \_parameter: (work@test.ESTABLISHED), line:10:16, endln:10:27 |vpiParent: - \_module: work@test (work@test), file:${SURELOG_DIR}/tests/Ternary/top.sv, line:3:1, endln:85:10 + \_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/Ternary/top.sv, line:3:1, endln:85:10 |HEX:0003 |vpiTypespec: \_int_typespec: @@ -2936,7 +2936,7 @@ design: (work@test) |vpiParameter: \_parameter: (work@test.USER_DELAY_INIT), line:24:16, endln:24:31 |vpiParent: - \_module: work@test (work@test), file:${SURELOG_DIR}/tests/Ternary/top.sv, line:3:1, endln:85:10 + \_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/Ternary/top.sv, line:3:1, endln:85:10 |HEX:001 |vpiTypespec: \_int_typespec: @@ -2962,7 +2962,7 @@ design: (work@test) |vpiParameter: \_parameter: (work@test.USER_CLEAN), line:25:16, endln:25:26 |vpiParent: - \_module: work@test (work@test), file:${SURELOG_DIR}/tests/Ternary/top.sv, line:3:1, endln:85:10 + \_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/Ternary/top.sv, line:3:1, endln:85:10 |HEX:002 |vpiTypespec: \_int_typespec: @@ -2988,7 +2988,7 @@ design: (work@test) |vpiParameter: \_parameter: (work@test.USER_CLEAN_CHECK), line:26:16, endln:26:32 |vpiParent: - \_module: work@test (work@test), file:${SURELOG_DIR}/tests/Ternary/top.sv, line:3:1, endln:85:10 + \_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/Ternary/top.sv, line:3:1, endln:85:10 |HEX:004 |vpiTypespec: \_int_typespec: @@ -3014,7 +3014,7 @@ design: (work@test) |vpiParameter: \_parameter: (work@test.USER_CLEAR_INTS), line:27:16, endln:27:31 |vpiParent: - \_module: work@test (work@test), file:${SURELOG_DIR}/tests/Ternary/top.sv, line:3:1, endln:85:10 + \_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/Ternary/top.sv, line:3:1, endln:85:10 |HEX:008 |vpiTypespec: \_int_typespec: @@ -3040,7 +3040,7 @@ design: (work@test) |vpiParameter: \_parameter: (work@test.USER_INIT), line:28:16, endln:28:25 |vpiParent: - \_module: work@test (work@test), file:${SURELOG_DIR}/tests/Ternary/top.sv, line:3:1, endln:85:10 + \_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/Ternary/top.sv, line:3:1, endln:85:10 |HEX:010 |vpiTypespec: \_int_typespec: @@ -3066,7 +3066,7 @@ design: (work@test) |vpiParameter: \_parameter: (work@test.USER_IDLE), line:29:16, endln:29:25 |vpiParent: - \_module: work@test (work@test), file:${SURELOG_DIR}/tests/Ternary/top.sv, line:3:1, endln:85:10 + \_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/Ternary/top.sv, line:3:1, endln:85:10 |HEX:020 |vpiTypespec: \_int_typespec: @@ -3092,7 +3092,7 @@ design: (work@test) |vpiParameter: \_parameter: (work@test.USER_CHECK_STATE), line:30:16, endln:30:32 |vpiParent: - \_module: work@test (work@test), file:${SURELOG_DIR}/tests/Ternary/top.sv, line:3:1, endln:85:10 + \_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/Ternary/top.sv, line:3:1, endln:85:10 |HEX:040 |vpiTypespec: \_int_typespec: @@ -3118,7 +3118,7 @@ design: (work@test) |vpiParameter: \_parameter: (work@test.USER_CHECK_SPACE), line:31:16, endln:31:32 |vpiParent: - \_module: work@test (work@test), file:${SURELOG_DIR}/tests/Ternary/top.sv, line:3:1, endln:85:10 + \_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/Ternary/top.sv, line:3:1, endln:85:10 |HEX:080 |vpiTypespec: \_int_typespec: @@ -3144,7 +3144,7 @@ design: (work@test) |vpiParameter: \_parameter: (work@test.USER_WRITE_DATA), line:32:16, endln:32:31 |vpiParent: - \_module: work@test (work@test), file:${SURELOG_DIR}/tests/Ternary/top.sv, line:3:1, endln:85:10 + \_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/Ternary/top.sv, line:3:1, endln:85:10 |HEX:100 |vpiTypespec: \_int_typespec: @@ -3170,7 +3170,7 @@ design: (work@test) |vpiParameter: \_parameter: (work@test.USER_READ_LENGTH), line:33:16, endln:33:32 |vpiParent: - \_module: work@test (work@test), file:${SURELOG_DIR}/tests/Ternary/top.sv, line:3:1, endln:85:10 + \_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/Ternary/top.sv, line:3:1, endln:85:10 |HEX:200 |vpiTypespec: \_int_typespec: @@ -3196,7 +3196,7 @@ design: (work@test) |vpiParameter: \_parameter: (work@test.USER_READ_DATA), line:34:16, endln:34:30 |vpiParent: - \_module: work@test (work@test), file:${SURELOG_DIR}/tests/Ternary/top.sv, line:3:1, endln:85:10 + \_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/Ternary/top.sv, line:3:1, endln:85:10 |HEX:400 |vpiTypespec: \_int_typespec: @@ -3222,7 +3222,7 @@ design: (work@test) |vpiParamAssign: \_param_assign: , line:9:16, endln:9:33 |vpiParent: - \_module: work@test (work@test), file:${SURELOG_DIR}/tests/Ternary/top.sv, line:3:1, endln:85:10 + \_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/Ternary/top.sv, line:3:1, endln:85:10 |vpiRhs: \_constant: , line:9:31, endln:9:33 |vpiDecompile:15 @@ -3236,7 +3236,7 @@ design: (work@test) |vpiParamAssign: \_param_assign: , line:10:16, endln:10:39 |vpiParent: - \_module: work@test (work@test), file:${SURELOG_DIR}/tests/Ternary/top.sv, line:3:1, endln:85:10 + \_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/Ternary/top.sv, line:3:1, endln:85:10 |vpiRhs: \_constant: , line:10:31, endln:10:39 |vpiDecompile:16'h0003 @@ -3250,7 +3250,7 @@ design: (work@test) |vpiParamAssign: \_param_assign: , line:24:16, endln:24:42 |vpiParent: - \_module: work@test (work@test), file:${SURELOG_DIR}/tests/Ternary/top.sv, line:3:1, endln:85:10 + \_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/Ternary/top.sv, line:3:1, endln:85:10 |vpiRhs: \_constant: , line:24:35, endln:24:42 |vpiDecompile:11'h001 @@ -3264,7 +3264,7 @@ design: (work@test) |vpiParamAssign: \_param_assign: , line:25:16, endln:25:42 |vpiParent: - \_module: work@test (work@test), file:${SURELOG_DIR}/tests/Ternary/top.sv, line:3:1, endln:85:10 + \_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/Ternary/top.sv, line:3:1, endln:85:10 |vpiRhs: \_constant: , line:25:35, endln:25:42 |vpiDecompile:11'h002 @@ -3278,7 +3278,7 @@ design: (work@test) |vpiParamAssign: \_param_assign: , line:26:16, endln:26:42 |vpiParent: - \_module: work@test (work@test), file:${SURELOG_DIR}/tests/Ternary/top.sv, line:3:1, endln:85:10 + \_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/Ternary/top.sv, line:3:1, endln:85:10 |vpiRhs: \_constant: , line:26:35, endln:26:42 |vpiDecompile:11'h004 @@ -3292,7 +3292,7 @@ design: (work@test) |vpiParamAssign: \_param_assign: , line:27:16, endln:27:42 |vpiParent: - \_module: work@test (work@test), file:${SURELOG_DIR}/tests/Ternary/top.sv, line:3:1, endln:85:10 + \_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/Ternary/top.sv, line:3:1, endln:85:10 |vpiRhs: \_constant: , line:27:35, endln:27:42 |vpiDecompile:11'h008 @@ -3306,7 +3306,7 @@ design: (work@test) |vpiParamAssign: \_param_assign: , line:28:16, endln:28:42 |vpiParent: - \_module: work@test (work@test), file:${SURELOG_DIR}/tests/Ternary/top.sv, line:3:1, endln:85:10 + \_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/Ternary/top.sv, line:3:1, endln:85:10 |vpiRhs: \_constant: , line:28:35, endln:28:42 |vpiDecompile:11'h010 @@ -3320,7 +3320,7 @@ design: (work@test) |vpiParamAssign: \_param_assign: , line:29:16, endln:29:42 |vpiParent: - \_module: work@test (work@test), file:${SURELOG_DIR}/tests/Ternary/top.sv, line:3:1, endln:85:10 + \_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/Ternary/top.sv, line:3:1, endln:85:10 |vpiRhs: \_constant: , line:29:35, endln:29:42 |vpiDecompile:11'h020 @@ -3334,7 +3334,7 @@ design: (work@test) |vpiParamAssign: \_param_assign: , line:30:16, endln:30:42 |vpiParent: - \_module: work@test (work@test), file:${SURELOG_DIR}/tests/Ternary/top.sv, line:3:1, endln:85:10 + \_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/Ternary/top.sv, line:3:1, endln:85:10 |vpiRhs: \_constant: , line:30:35, endln:30:42 |vpiDecompile:11'h040 @@ -3348,7 +3348,7 @@ design: (work@test) |vpiParamAssign: \_param_assign: , line:31:16, endln:31:42 |vpiParent: - \_module: work@test (work@test), file:${SURELOG_DIR}/tests/Ternary/top.sv, line:3:1, endln:85:10 + \_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/Ternary/top.sv, line:3:1, endln:85:10 |vpiRhs: \_constant: , line:31:35, endln:31:42 |vpiDecompile:11'h080 @@ -3362,7 +3362,7 @@ design: (work@test) |vpiParamAssign: \_param_assign: , line:32:16, endln:32:42 |vpiParent: - \_module: work@test (work@test), file:${SURELOG_DIR}/tests/Ternary/top.sv, line:3:1, endln:85:10 + \_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/Ternary/top.sv, line:3:1, endln:85:10 |vpiRhs: \_constant: , line:32:35, endln:32:42 |vpiDecompile:11'h100 @@ -3376,7 +3376,7 @@ design: (work@test) |vpiParamAssign: \_param_assign: , line:33:16, endln:33:42 |vpiParent: - \_module: work@test (work@test), file:${SURELOG_DIR}/tests/Ternary/top.sv, line:3:1, endln:85:10 + \_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/Ternary/top.sv, line:3:1, endln:85:10 |vpiRhs: \_constant: , line:33:35, endln:33:42 |vpiDecompile:11'h200 @@ -3390,7 +3390,7 @@ design: (work@test) |vpiParamAssign: \_param_assign: , line:34:16, endln:34:42 |vpiParent: - \_module: work@test (work@test), file:${SURELOG_DIR}/tests/Ternary/top.sv, line:3:1, endln:85:10 + \_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/Ternary/top.sv, line:3:1, endln:85:10 |vpiRhs: \_constant: , line:34:35, endln:34:42 |vpiDecompile:11'h400 @@ -3406,7 +3406,7 @@ design: (work@test) |vpiNet: \_logic_net: (work@test.CLK), line:6:11, endln:6:14 |vpiParent: - \_module: work@test (work@test), file:${SURELOG_DIR}/tests/Ternary/top.sv, line:3:1, endln:85:10 + \_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/Ternary/top.sv, line:3:1, endln:85:10 |vpiTypespec: \_logic_typespec: , line:6:11, endln:6:11 |vpiName:CLK @@ -3414,7 +3414,7 @@ design: (work@test) |vpiNet: \_logic_net: (work@test.RAMRST), line:12:10, endln:12:16 |vpiParent: - \_module: work@test (work@test), file:${SURELOG_DIR}/tests/Ternary/top.sv, line:3:1, endln:85:10 + \_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/Ternary/top.sv, line:3:1, endln:85:10 |vpiTypespec: \_logic_typespec: , line:12:5, endln:12:9 |vpiName:RAMRST @@ -3423,7 +3423,7 @@ design: (work@test) |vpiNet: \_logic_net: (work@test.UserReadData), line:13:17, endln:13:29 |vpiParent: - \_module: work@test (work@test), file:${SURELOG_DIR}/tests/Ternary/top.sv, line:3:1, endln:85:10 + \_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/Ternary/top.sv, line:3:1, endln:85:10 |vpiTypespec: \_logic_typespec: , line:13:5, endln:13:16 |vpiRange: @@ -3450,7 +3450,7 @@ design: (work@test) |vpiNet: \_logic_net: (work@test.UserReadDataValid), line:14:10, endln:14:27 |vpiParent: - \_module: work@test (work@test), file:${SURELOG_DIR}/tests/Ternary/top.sv, line:3:1, endln:85:10 + \_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/Ternary/top.sv, line:3:1, endln:85:10 |vpiTypespec: \_logic_typespec: , line:14:5, endln:14:9 |vpiName:UserReadDataValid @@ -3459,7 +3459,7 @@ design: (work@test) |vpiNet: \_logic_net: (work@test.Delay), line:16:16, endln:16:21 |vpiParent: - \_module: work@test (work@test), file:${SURELOG_DIR}/tests/Ternary/top.sv, line:3:1, endln:85:10 + \_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/Ternary/top.sv, line:3:1, endln:85:10 |vpiTypespec: \_logic_typespec: , line:16:5, endln:16:15 |vpiRange: @@ -3486,7 +3486,7 @@ design: (work@test) |vpiNet: \_logic_net: (work@test.UserState), line:17:16, endln:17:25 |vpiParent: - \_module: work@test (work@test), file:${SURELOG_DIR}/tests/Ternary/top.sv, line:3:1, endln:85:10 + \_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/Ternary/top.sv, line:3:1, endln:85:10 |vpiTypespec: \_logic_typespec: , line:17:5, endln:17:15 |vpiRange: @@ -3513,7 +3513,7 @@ design: (work@test) |vpiNet: \_logic_net: (work@test.UserValidCount), line:18:16, endln:18:30 |vpiParent: - \_module: work@test (work@test), file:${SURELOG_DIR}/tests/Ternary/top.sv, line:3:1, endln:85:10 + \_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/Ternary/top.sv, line:3:1, endln:85:10 |vpiTypespec: \_logic_typespec: , line:18:5, endln:18:15 |vpiRange: @@ -3540,7 +3540,7 @@ design: (work@test) |vpiNet: \_logic_net: (work@test.ConnectionState), line:19:15, endln:19:30 |vpiParent: - \_module: work@test (work@test), file:${SURELOG_DIR}/tests/Ternary/top.sv, line:3:1, endln:85:10 + \_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/Ternary/top.sv, line:3:1, endln:85:10 |vpiTypespec: \_logic_typespec: , line:19:5, endln:19:14 |vpiRange: @@ -3567,7 +3567,7 @@ design: (work@test) |vpiNet: \_logic_net: (work@test.InterruptStatus), line:20:16, endln:20:31 |vpiParent: - \_module: work@test (work@test), file:${SURELOG_DIR}/tests/Ternary/top.sv, line:3:1, endln:85:10 + \_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/Ternary/top.sv, line:3:1, endln:85:10 |vpiTypespec: \_logic_typespec: , line:20:5, endln:20:15 |vpiRange: @@ -3594,7 +3594,7 @@ design: (work@test) |vpiNet: \_logic_net: (work@test.FrameLength), line:21:16, endln:21:27 |vpiParent: - \_module: work@test (work@test), file:${SURELOG_DIR}/tests/Ternary/top.sv, line:3:1, endln:85:10 + \_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/Ternary/top.sv, line:3:1, endln:85:10 |vpiTypespec: \_logic_typespec: , line:21:5, endln:21:15 |vpiRange: @@ -3621,7 +3621,7 @@ design: (work@test) |vpiNet: \_logic_net: (work@test.LatencyDelay), line:22:15, endln:22:27 |vpiParent: - \_module: work@test (work@test), file:${SURELOG_DIR}/tests/Ternary/top.sv, line:3:1, endln:85:10 + \_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/Ternary/top.sv, line:3:1, endln:85:10 |vpiTypespec: \_logic_typespec: , line:22:5, endln:22:14 |vpiRange: @@ -3649,7 +3649,7 @@ design: (work@test) |vpiPort: \_port: (CLK), line:6:11, endln:6:14 |vpiParent: - \_module: work@test (work@test), file:${SURELOG_DIR}/tests/Ternary/top.sv, line:3:1, endln:85:10 + \_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/Ternary/top.sv, line:3:1, endln:85:10 |vpiName:CLK |vpiDirection:1 |vpiLowConn: @@ -3663,11 +3663,11 @@ design: (work@test) |vpiTypedef: \_logic_typespec: , line:6:11, endln:6:11 |vpiInstance: - \_module: work@test (work@test), file:${SURELOG_DIR}/tests/Ternary/top.sv, line:3:1, endln:85:10 + \_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/Ternary/top.sv, line:3:1, endln:85:10 |vpiProcess: \_always: , line:37:5, endln:83:8 |vpiParent: - \_module: work@test (work@test), file:${SURELOG_DIR}/tests/Ternary/top.sv, line:3:1, endln:85:10 + \_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/Ternary/top.sv, line:3:1, endln:85:10 |vpiStmt: \_event_control: , line:37:12, endln:37:45 |vpiParent: diff --git a/tests/TernaryAssoc/TernaryAssoc.log b/tests/TernaryAssoc/TernaryAssoc.log index 8f5203d6de..5f082dcd16 100644 --- a/tests/TernaryAssoc/TernaryAssoc.log +++ b/tests/TernaryAssoc/TernaryAssoc.log @@ -29,7 +29,7 @@ design 1 logic_net 6 logic_typespec 2 logic_var 6 -module 3 +module_inst 3 operation 4 range 5 ref_obj 12 @@ -43,7 +43,7 @@ design 1 logic_net 6 logic_typespec 2 logic_var 6 -module 3 +module_inst 3 operation 6 range 5 ref_obj 18 @@ -61,7 +61,7 @@ design: (work@top) |vpiElaborated:1 |vpiName:work@top |uhdmallModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/TernaryAssoc/dut.sv, line:1:1, endln:7:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/TernaryAssoc/dut.sv, line:1:1, endln:7:10 |vpiParent: \_design: (work@top) |vpiFullName:work@top @@ -69,49 +69,49 @@ design: (work@top) |vpiNet: \_logic_net: (work@top.first_condition), line:2:14, endln:2:29 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/TernaryAssoc/dut.sv, line:1:1, endln:7:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/TernaryAssoc/dut.sv, line:1:1, endln:7:10 |vpiName:first_condition |vpiFullName:work@top.first_condition |vpiNetType:36 |vpiNet: \_logic_net: (work@top.first_condition_false), line:2:31, endln:2:52 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/TernaryAssoc/dut.sv, line:1:1, endln:7:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/TernaryAssoc/dut.sv, line:1:1, endln:7:10 |vpiName:first_condition_false |vpiFullName:work@top.first_condition_false |vpiNetType:36 |vpiNet: \_logic_net: (work@top.first_condition_true), line:3:14, endln:3:34 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/TernaryAssoc/dut.sv, line:1:1, endln:7:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/TernaryAssoc/dut.sv, line:1:1, endln:7:10 |vpiName:first_condition_true |vpiFullName:work@top.first_condition_true |vpiNetType:36 |vpiNet: \_logic_net: (work@top.second_condition_true), line:3:35, endln:3:56 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/TernaryAssoc/dut.sv, line:1:1, endln:7:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/TernaryAssoc/dut.sv, line:1:1, endln:7:10 |vpiName:second_condition_true |vpiFullName:work@top.second_condition_true |vpiNetType:36 |vpiNet: \_logic_net: (work@top.second_condition_false), line:3:58, endln:3:80 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/TernaryAssoc/dut.sv, line:1:1, endln:7:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/TernaryAssoc/dut.sv, line:1:1, endln:7:10 |vpiName:second_condition_false |vpiFullName:work@top.second_condition_false |vpiNetType:36 |vpiNet: \_logic_net: (work@top.result), line:3:82, endln:3:88 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/TernaryAssoc/dut.sv, line:1:1, endln:7:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/TernaryAssoc/dut.sv, line:1:1, endln:7:10 |vpiName:result |vpiFullName:work@top.result |vpiNetType:36 |vpiContAssign: \_cont_assign: , line:4:8, endln:6:63 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/TernaryAssoc/dut.sv, line:1:1, endln:7:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/TernaryAssoc/dut.sv, line:1:1, endln:7:10 |vpiRhs: \_operation: , line:4:17, endln:6:63 |vpiParent: @@ -171,12 +171,12 @@ design: (work@top) |vpiActual: \_logic_var: (work@top.result), line:3:82, endln:3:88 |uhdmtopModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/TernaryAssoc/dut.sv, line:1:1, endln:7:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/TernaryAssoc/dut.sv, line:1:1, endln:7:10 |vpiName:work@top |vpiVariables: \_logic_var: (work@top.first_condition), line:2:14, endln:2:29 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/TernaryAssoc/dut.sv, line:1:1, endln:7:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/TernaryAssoc/dut.sv, line:1:1, endln:7:10 |vpiTypespec: \_logic_typespec: , line:2:1, endln:2:6 |vpiName:first_condition @@ -185,7 +185,7 @@ design: (work@top) |vpiVariables: \_logic_var: (work@top.first_condition_false), line:2:31, endln:2:52 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/TernaryAssoc/dut.sv, line:1:1, endln:7:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/TernaryAssoc/dut.sv, line:1:1, endln:7:10 |vpiTypespec: \_logic_typespec: , line:2:1, endln:2:6 |vpiName:first_condition_false @@ -194,7 +194,7 @@ design: (work@top) |vpiVariables: \_logic_var: (work@top.first_condition_true), line:3:14, endln:3:34 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/TernaryAssoc/dut.sv, line:1:1, endln:7:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/TernaryAssoc/dut.sv, line:1:1, endln:7:10 |vpiTypespec: \_logic_typespec: , line:3:1, endln:3:13 |vpiRange: @@ -239,7 +239,7 @@ design: (work@top) |vpiVariables: \_logic_var: (work@top.second_condition_true), line:3:35, endln:3:56 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/TernaryAssoc/dut.sv, line:1:1, endln:7:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/TernaryAssoc/dut.sv, line:1:1, endln:7:10 |vpiTypespec: \_logic_typespec: , line:3:1, endln:3:13 |vpiName:second_condition_true @@ -266,7 +266,7 @@ design: (work@top) |vpiVariables: \_logic_var: (work@top.second_condition_false), line:3:58, endln:3:80 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/TernaryAssoc/dut.sv, line:1:1, endln:7:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/TernaryAssoc/dut.sv, line:1:1, endln:7:10 |vpiTypespec: \_logic_typespec: , line:3:1, endln:3:13 |vpiName:second_condition_false @@ -293,7 +293,7 @@ design: (work@top) |vpiVariables: \_logic_var: (work@top.result), line:3:82, endln:3:88 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/TernaryAssoc/dut.sv, line:1:1, endln:7:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/TernaryAssoc/dut.sv, line:1:1, endln:7:10 |vpiTypespec: \_logic_typespec: , line:3:1, endln:3:13 |vpiName:result @@ -323,7 +323,7 @@ design: (work@top) |vpiContAssign: \_cont_assign: , line:4:8, endln:6:63 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/TernaryAssoc/dut.sv, line:1:1, endln:7:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/TernaryAssoc/dut.sv, line:1:1, endln:7:10 |vpiRhs: \_operation: , line:4:17, endln:6:63 |vpiParent: diff --git a/tests/TestFileSplit/TestFileSplit.log b/tests/TestFileSplit/TestFileSplit.log index ed264d0a96..74430cfe41 100644 --- a/tests/TestFileSplit/TestFileSplit.log +++ b/tests/TestFileSplit/TestFileSplit.log @@ -456,7 +456,7 @@ int_typespec 9 int_var 4 io_decl 11 logic_var 1 -module 7 +module_inst 7 package 5 task 9 === UHDM Object Stats End === diff --git a/tests/TestSepComp/TestSepComp.log b/tests/TestSepComp/TestSepComp.log index 74d10b1b22..759fa350c0 100644 --- a/tests/TestSepComp/TestSepComp.log +++ b/tests/TestSepComp/TestSepComp.log @@ -27,15 +27,15 @@ [ NOTE] : 0 [INF:CM0023] Creating log file ${SURELOG_DIR}/tests/TestSepComp/slpp_all/surelog.log. +PARSER CACHE USED FOR: ${SURELOG_DIR}/tests/TestSepComp/top.sv PARSER CACHE USED FOR: ${SURELOG_DIR}/tests/TestSepComp/pkg1.sv PARSER CACHE USED FOR: ${SURELOG_DIR}/tests/TestSepComp/pkg2.sv -PARSER CACHE USED FOR: ${SURELOG_DIR}/tests/TestSepComp/top.sv +[WRN:PA0205] ${SURELOG_DIR}/tests/TestSepComp/top.sv:1:1: No timescale set for "top". + [WRN:PA0205] ${SURELOG_DIR}/tests/TestSepComp/pkg1.sv:1:1: No timescale set for "pkg1". [WRN:PA0205] ${SURELOG_DIR}/tests/TestSepComp/pkg2.sv:1:1: No timescale set for "pkg2". -[WRN:PA0205] ${SURELOG_DIR}/tests/TestSepComp/top.sv:1:1: No timescale set for "top". - [INF:CP0300] Compilation... [INF:CP0301] ${SURELOG_DIR}/tests/TestSepComp/pkg1.sv:1:1: Compile package "pkg1". @@ -102,7 +102,7 @@ design: (work@top) |vpiTypespec: \_enum_typespec: (pkg2::enum2), line:3:3, endln:5:11 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/TestSepComp/top.sv, line:1:1, endln:4:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/TestSepComp/top.sv, line:1:1, endln:4:10 |vpiName:pkg2::enum2 |vpiTypedefAlias: \_enum_typespec: (pkg1::enum1), line:3:3, endln:5:11 @@ -182,14 +182,14 @@ design: (work@top) |vpiDefName:pkg2 |vpiTop:1 |uhdmallModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/TestSepComp/top.sv, line:1:1, endln:4:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/TestSepComp/top.sv, line:1:1, endln:4:10 |vpiParent: \_design: (work@top) |vpiFullName:work@top |vpiParameter: \_parameter: (work@top.P1), line:4:18, endln:4:20 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/TestSepComp/top.sv, line:1:1, endln:4:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/TestSepComp/top.sv, line:1:1, endln:4:10 |INT:0 |vpiTypespec: \_enum_typespec: (enum2), line:3:3, endln:5:11 @@ -227,7 +227,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:4:18, endln:4:33 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/TestSepComp/top.sv, line:1:1, endln:4:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/TestSepComp/top.sv, line:1:1, endln:4:10 |vpiRhs: \_constant: , line:4:23, endln:4:29 |vpiParent: @@ -309,12 +309,12 @@ design: (work@top) \_import_typespec: (pkg2), line:2:11, endln:2:18 |vpiDefName:work@top |uhdmtopModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/TestSepComp/top.sv, line:1:1, endln:4:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/TestSepComp/top.sv, line:1:1, endln:4:10 |vpiName:work@top |vpiParameter: \_parameter: (work@top.P1), line:4:18, endln:4:20 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/TestSepComp/top.sv, line:1:1, endln:4:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/TestSepComp/top.sv, line:1:1, endln:4:10 |INT:0 |vpiTypespec: \_enum_typespec: (enum2), line:3:3, endln:5:11 @@ -352,7 +352,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:4:18, endln:4:33 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/TestSepComp/top.sv, line:1:1, endln:4:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/TestSepComp/top.sv, line:1:1, endln:4:10 |vpiRhs: \_constant: , line:4:23, endln:4:33 |vpiDecompile:0 diff --git a/tests/TestSepCompNoHash/TestSepCompNoHash.log b/tests/TestSepCompNoHash/TestSepCompNoHash.log index e009119d3d..a5790f032e 100644 --- a/tests/TestSepCompNoHash/TestSepCompNoHash.log +++ b/tests/TestSepCompNoHash/TestSepCompNoHash.log @@ -105,7 +105,7 @@ design: (work@top) |vpiTypespec: \_enum_typespec: (pkg2::enum2), line:3:3, endln:5:11 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/TestSepCompNoHash/top.sv, line:1:1, endln:4:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/TestSepCompNoHash/top.sv, line:1:1, endln:4:10 |vpiName:pkg2::enum2 |vpiTypedefAlias: \_enum_typespec: (pkg1::enum1), line:3:3, endln:5:11 @@ -185,14 +185,14 @@ design: (work@top) |vpiDefName:pkg2 |vpiTop:1 |uhdmallModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/TestSepCompNoHash/top.sv, line:1:1, endln:4:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/TestSepCompNoHash/top.sv, line:1:1, endln:4:10 |vpiParent: \_design: (work@top) |vpiFullName:work@top |vpiParameter: \_parameter: (work@top.P1), line:4:18, endln:4:20 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/TestSepCompNoHash/top.sv, line:1:1, endln:4:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/TestSepCompNoHash/top.sv, line:1:1, endln:4:10 |INT:0 |vpiTypespec: \_enum_typespec: (enum2), line:3:3, endln:5:11 @@ -230,7 +230,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:4:18, endln:4:33 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/TestSepCompNoHash/top.sv, line:1:1, endln:4:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/TestSepCompNoHash/top.sv, line:1:1, endln:4:10 |vpiRhs: \_constant: , line:4:23, endln:4:29 |vpiParent: @@ -312,12 +312,12 @@ design: (work@top) \_import_typespec: (pkg2), line:2:11, endln:2:18 |vpiDefName:work@top |uhdmtopModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/TestSepCompNoHash/top.sv, line:1:1, endln:4:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/TestSepCompNoHash/top.sv, line:1:1, endln:4:10 |vpiName:work@top |vpiParameter: \_parameter: (work@top.P1), line:4:18, endln:4:20 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/TestSepCompNoHash/top.sv, line:1:1, endln:4:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/TestSepCompNoHash/top.sv, line:1:1, endln:4:10 |INT:0 |vpiTypespec: \_enum_typespec: (enum2), line:3:3, endln:5:11 @@ -355,7 +355,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:4:18, endln:4:33 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/TestSepCompNoHash/top.sv, line:1:1, endln:4:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/TestSepCompNoHash/top.sv, line:1:1, endln:4:10 |vpiRhs: \_constant: , line:4:23, endln:4:33 |vpiDecompile:0 diff --git a/tests/TfCalls/TfCalls.log b/tests/TfCalls/TfCalls.log index c6620ba9c6..1613ffe7ef 100644 --- a/tests/TfCalls/TfCalls.log +++ b/tests/TfCalls/TfCalls.log @@ -31,7 +31,7 @@ design 1 initial 1 logic_net 4 logic_typespec 6 -module 2 +module_inst 2 port 4 ref_obj 5 sys_func_call 1 @@ -48,7 +48,7 @@ sys_func_call 1 design: (work@m1) |vpiName:work@m1 |uhdmallModules: -\_module: work@m1 (work@m1), file:${SURELOG_DIR}/tests/TfCalls/top.v, line:1:1, endln:5:10 +\_module_inst: work@m1 (work@m1), file:${SURELOG_DIR}/tests/TfCalls/top.v, line:1:1, endln:5:10 |vpiParent: \_design: (work@m1) |vpiFullName:work@m1 @@ -56,19 +56,19 @@ design: (work@m1) |vpiNet: \_logic_net: (work@m1.clk), line:1:17, endln:1:20 |vpiParent: - \_module: work@m1 (work@m1), file:${SURELOG_DIR}/tests/TfCalls/top.v, line:1:1, endln:5:10 + \_module_inst: work@m1 (work@m1), file:${SURELOG_DIR}/tests/TfCalls/top.v, line:1:1, endln:5:10 |vpiName:clk |vpiFullName:work@m1.clk |vpiNet: \_logic_net: (work@m1.out), line:1:29, endln:1:32 |vpiParent: - \_module: work@m1 (work@m1), file:${SURELOG_DIR}/tests/TfCalls/top.v, line:1:1, endln:5:10 + \_module_inst: work@m1 (work@m1), file:${SURELOG_DIR}/tests/TfCalls/top.v, line:1:1, endln:5:10 |vpiName:out |vpiFullName:work@m1.out |vpiPort: \_port: (clk), line:1:17, endln:1:20 |vpiParent: - \_module: work@m1 (work@m1), file:${SURELOG_DIR}/tests/TfCalls/top.v, line:1:1, endln:5:10 + \_module_inst: work@m1 (work@m1), file:${SURELOG_DIR}/tests/TfCalls/top.v, line:1:1, endln:5:10 |vpiName:clk |vpiDirection:1 |vpiLowConn: @@ -80,7 +80,7 @@ design: (work@m1) |vpiPort: \_port: (out), line:1:29, endln:1:32 |vpiParent: - \_module: work@m1 (work@m1), file:${SURELOG_DIR}/tests/TfCalls/top.v, line:1:1, endln:5:10 + \_module_inst: work@m1 (work@m1), file:${SURELOG_DIR}/tests/TfCalls/top.v, line:1:1, endln:5:10 |vpiName:out |vpiDirection:2 |vpiLowConn: @@ -92,7 +92,7 @@ design: (work@m1) |vpiProcess: \_initial: , line:2:3, endln:4:6 |vpiParent: - \_module: work@m1 (work@m1), file:${SURELOG_DIR}/tests/TfCalls/top.v, line:1:1, endln:5:10 + \_module_inst: work@m1 (work@m1), file:${SURELOG_DIR}/tests/TfCalls/top.v, line:1:1, endln:5:10 |vpiStmt: \_begin: (work@m1), line:2:11, endln:4:6 |vpiParent: @@ -120,14 +120,14 @@ design: (work@m1) \_logic_net: (work@m1.clk), line:1:17, endln:1:20 |vpiName:$display |uhdmtopModules: -\_module: work@m1 (work@m1), file:${SURELOG_DIR}/tests/TfCalls/top.v, line:1:1, endln:5:10 +\_module_inst: work@m1 (work@m1), file:${SURELOG_DIR}/tests/TfCalls/top.v, line:1:1, endln:5:10 |vpiName:work@m1 |vpiDefName:work@m1 |vpiTop:1 |vpiNet: \_logic_net: (work@m1.clk), line:1:17, endln:1:20 |vpiParent: - \_module: work@m1 (work@m1), file:${SURELOG_DIR}/tests/TfCalls/top.v, line:1:1, endln:5:10 + \_module_inst: work@m1 (work@m1), file:${SURELOG_DIR}/tests/TfCalls/top.v, line:1:1, endln:5:10 |vpiTypespec: \_logic_typespec: , line:1:17, endln:1:17 |vpiName:clk @@ -135,7 +135,7 @@ design: (work@m1) |vpiNet: \_logic_net: (work@m1.out), line:1:29, endln:1:32 |vpiParent: - \_module: work@m1 (work@m1), file:${SURELOG_DIR}/tests/TfCalls/top.v, line:1:1, endln:5:10 + \_module_inst: work@m1 (work@m1), file:${SURELOG_DIR}/tests/TfCalls/top.v, line:1:1, endln:5:10 |vpiTypespec: \_logic_typespec: , line:1:29, endln:1:29 |vpiName:out @@ -144,7 +144,7 @@ design: (work@m1) |vpiPort: \_port: (clk), line:1:17, endln:1:20 |vpiParent: - \_module: work@m1 (work@m1), file:${SURELOG_DIR}/tests/TfCalls/top.v, line:1:1, endln:5:10 + \_module_inst: work@m1 (work@m1), file:${SURELOG_DIR}/tests/TfCalls/top.v, line:1:1, endln:5:10 |vpiName:clk |vpiDirection:1 |vpiLowConn: @@ -158,7 +158,7 @@ design: (work@m1) |vpiPort: \_port: (out), line:1:29, endln:1:32 |vpiParent: - \_module: work@m1 (work@m1), file:${SURELOG_DIR}/tests/TfCalls/top.v, line:1:1, endln:5:10 + \_module_inst: work@m1 (work@m1), file:${SURELOG_DIR}/tests/TfCalls/top.v, line:1:1, endln:5:10 |vpiName:out |vpiDirection:2 |vpiLowConn: diff --git a/tests/ThisHier/ThisHier.log b/tests/ThisHier/ThisHier.log index 6ac0e5e70d..348ef11022 100644 --- a/tests/ThisHier/ThisHier.log +++ b/tests/ThisHier/ThisHier.log @@ -185,7 +185,7 @@ function 4 hier_path 5 int_typespec 1 int_var 1 -module 1 +module_inst 1 package 3 range 4 ref_obj 20 @@ -210,7 +210,7 @@ function 14 hier_path 16 int_typespec 1 int_var 4 -module 1 +module_inst 1 package 3 range 4 ref_obj 49 diff --git a/tests/TimeUnit/TimeUnit.log b/tests/TimeUnit/TimeUnit.log index 0e2c53a009..cb0547c7ac 100644 --- a/tests/TimeUnit/TimeUnit.log +++ b/tests/TimeUnit/TimeUnit.log @@ -115,12 +115,12 @@ function 9 gate 1 int_typespec 9 int_var 4 -interface 3 +interface_inst 3 io_decl 11 logic_net 25 logic_typespec 19 logic_var 1 -module 18 +module_inst 18 operation 2 package 2 port 18 diff --git a/tests/TopFunc/TopFunc.log b/tests/TopFunc/TopFunc.log index b9ce78343d..1e52c2d52c 100644 --- a/tests/TopFunc/TopFunc.log +++ b/tests/TopFunc/TopFunc.log @@ -86,7 +86,7 @@ function 1 int_typespec 4 int_var 2 logic_net 1 -module 4 +module_inst 4 param_assign 1 parameter 1 port 2 @@ -104,7 +104,7 @@ function 1 int_typespec 4 int_var 2 logic_net 1 -module 4 +module_inst 4 param_assign 1 parameter 1 port 3 @@ -124,7 +124,7 @@ design: (work@top) |vpiElaborated:1 |vpiName:work@top |uhdmallModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/TopFunc/dut.sv, line:5:1, endln:7:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/TopFunc/dut.sv, line:5:1, endln:7:10 |vpiParent: \_design: (work@top) |vpiFullName:work@top @@ -132,13 +132,13 @@ design: (work@top) |vpiNet: \_logic_net: (work@top.o), line:5:23, endln:5:24 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/TopFunc/dut.sv, line:5:1, endln:7:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/TopFunc/dut.sv, line:5:1, endln:7:10 |vpiName:o |vpiFullName:work@top.o |vpiPort: \_port: (o), line:5:23, endln:5:24 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/TopFunc/dut.sv, line:5:1, endln:7:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/TopFunc/dut.sv, line:5:1, endln:7:10 |vpiName:o |vpiDirection:2 |vpiLowConn: @@ -151,7 +151,7 @@ design: (work@top) |vpiContAssign: \_cont_assign: , line:6:11, endln:6:22 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/TopFunc/dut.sv, line:5:1, endln:7:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/TopFunc/dut.sv, line:5:1, endln:7:10 |vpiRhs: \_func_call: (get_1), line:6:15, endln:6:22 |vpiParent: @@ -196,12 +196,12 @@ design: (work@top) |UINT:1 |vpiConstType:9 |uhdmtopModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/TopFunc/dut.sv, line:5:1, endln:7:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/TopFunc/dut.sv, line:5:1, endln:7:10 |vpiName:work@top |vpiVariables: \_int_var: (work@top.o), line:5:23, endln:5:24 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/TopFunc/dut.sv, line:5:1, endln:7:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/TopFunc/dut.sv, line:5:1, endln:7:10 |vpiTypespec: \_int_typespec: , line:5:19, endln:5:22 |vpiSigned:1 @@ -215,7 +215,7 @@ design: (work@top) |vpiPort: \_port: (o), line:5:23, endln:5:24 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/TopFunc/dut.sv, line:5:1, endln:7:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/TopFunc/dut.sv, line:5:1, endln:7:10 |vpiName:o |vpiDirection:2 |vpiLowConn: @@ -230,11 +230,11 @@ design: (work@top) \_int_typespec: , line:5:19, endln:5:22 |vpiSigned:1 |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/TopFunc/dut.sv, line:5:1, endln:7:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/TopFunc/dut.sv, line:5:1, endln:7:10 |vpiContAssign: \_cont_assign: , line:6:11, endln:6:22 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/TopFunc/dut.sv, line:5:1, endln:7:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/TopFunc/dut.sv, line:5:1, endln:7:10 |vpiRhs: \_constant: , line:2:11, endln:2:12 |vpiParent: diff --git a/tests/TranslateOff/TranslateOff.log b/tests/TranslateOff/TranslateOff.log index 93d969775f..181e42de81 100644 --- a/tests/TranslateOff/TranslateOff.log +++ b/tests/TranslateOff/TranslateOff.log @@ -69,7 +69,7 @@ n<> u<42> t c<1> l<10:1> el<24:1> cont_assign 2 design 1 logic_net 4 -module 3 +module_inst 3 ref_obj 4 === UHDM Object Stats End === [INF:UH0707] Elaborating UHDM... @@ -78,7 +78,7 @@ ref_obj 4 cont_assign 4 design 1 logic_net 4 -module 3 +module_inst 3 ref_obj 8 === UHDM Object Stats End === [INF:UH0708] Writing UHDM DB: ${SURELOG_DIR}/build/regression/TranslateOff/slpp_all/surelog.uhdm ... @@ -94,7 +94,7 @@ design: (work@top) |vpiElaborated:1 |vpiName:work@top |uhdmallModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/TranslateOff/dut.sv, line:10:1, endln:23:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/TranslateOff/dut.sv, line:10:1, endln:23:10 |vpiParent: \_design: (work@top) |vpiFullName:work@top @@ -102,7 +102,7 @@ design: (work@top) |vpiContAssign: \_cont_assign: , line:12:8, endln:12:13 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/TranslateOff/dut.sv, line:10:1, endln:23:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/TranslateOff/dut.sv, line:10:1, endln:23:10 |vpiRhs: \_ref_obj: (work@top.b), line:12:12, endln:12:13 |vpiParent: @@ -122,7 +122,7 @@ design: (work@top) |vpiContAssign: \_cont_assign: , line:20:8, endln:20:13 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/TranslateOff/dut.sv, line:10:1, endln:23:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/TranslateOff/dut.sv, line:10:1, endln:23:10 |vpiRhs: \_ref_obj: (work@top.d), line:20:12, endln:20:13 |vpiParent: @@ -140,7 +140,7 @@ design: (work@top) |vpiActual: \_logic_net: (c) |uhdmtopModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/TranslateOff/dut.sv, line:10:1, endln:23:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/TranslateOff/dut.sv, line:10:1, endln:23:10 |vpiName:work@top |vpiDefName:work@top |vpiTop:1 @@ -164,7 +164,7 @@ design: (work@top) |vpiContAssign: \_cont_assign: , line:12:8, endln:12:13 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/TranslateOff/dut.sv, line:10:1, endln:23:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/TranslateOff/dut.sv, line:10:1, endln:23:10 |vpiRhs: \_ref_obj: (work@top.b), line:12:12, endln:12:13 |vpiParent: @@ -184,7 +184,7 @@ design: (work@top) |vpiContAssign: \_cont_assign: , line:20:8, endln:20:13 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/TranslateOff/dut.sv, line:10:1, endln:23:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/TranslateOff/dut.sv, line:10:1, endln:23:10 |vpiRhs: \_ref_obj: (work@top.d), line:20:12, endln:20:13 |vpiParent: diff --git a/tests/TypeDefScope/TypeDefScope.log b/tests/TypeDefScope/TypeDefScope.log index b7db80021a..16f05446ee 100644 --- a/tests/TypeDefScope/TypeDefScope.log +++ b/tests/TypeDefScope/TypeDefScope.log @@ -398,7 +398,7 @@ io_decl 16 logic_net 4 logic_typespec 1 logic_var 1 -module 2 +module_inst 2 package 2 port 4 ref_obj 4 @@ -427,7 +427,7 @@ io_decl 32 logic_net 4 logic_typespec 1 logic_var 1 -module 2 +module_inst 2 package 2 port 6 ref_obj 6 @@ -924,7 +924,7 @@ design: (work@dut) \_int_typespec: |vpiSigned:1 |uhdmallModules: -\_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/TypeDefScope/dut.sv, line:1:1, endln:18:11 +\_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/TypeDefScope/dut.sv, line:1:1, endln:18:11 |vpiParent: \_design: (work@dut) |vpiFullName:work@dut @@ -932,7 +932,7 @@ design: (work@dut) |vpiTaskFunc: \_function: (work@dut.UVMC_set_config_object), line:3:4, endln:15:15 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/TypeDefScope/dut.sv, line:1:1, endln:18:11 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/TypeDefScope/dut.sv, line:1:1, endln:18:11 |vpiName:UVMC_set_config_object |vpiFullName:work@dut.UVMC_set_config_object |vpiVariables: @@ -955,7 +955,7 @@ design: (work@dut) |vpiFullName:work@dut.UVMC_set_config_object.comp |vpiVisibility:1 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/TypeDefScope/dut.sv, line:1:1, endln:18:11 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/TypeDefScope/dut.sv, line:1:1, endln:18:11 |vpiIODecl: \_io_decl: (type_name), line:3:49, endln:3:58 |vpiDirection:1 @@ -1000,23 +1000,23 @@ design: (work@dut) \_logic_typespec: (converter2), line:9:9, endln:9:14 |vpiName:converter2 |vpiInstance: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/TypeDefScope/dut.sv, line:1:1, endln:18:11 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/TypeDefScope/dut.sv, line:1:1, endln:18:11 |vpiNet: \_logic_net: (work@dut.a), line:1:13, endln:1:14 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/TypeDefScope/dut.sv, line:1:1, endln:18:11 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/TypeDefScope/dut.sv, line:1:1, endln:18:11 |vpiName:a |vpiFullName:work@dut.a |vpiNet: \_logic_net: (work@dut.b), line:1:16, endln:1:17 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/TypeDefScope/dut.sv, line:1:1, endln:18:11 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/TypeDefScope/dut.sv, line:1:1, endln:18:11 |vpiName:b |vpiFullName:work@dut.b |vpiPort: \_port: (a), line:1:13, endln:1:14 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/TypeDefScope/dut.sv, line:1:1, endln:18:11 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/TypeDefScope/dut.sv, line:1:1, endln:18:11 |vpiName:a |vpiDirection:3 |vpiLowConn: @@ -1026,7 +1026,7 @@ design: (work@dut) |vpiPort: \_port: (b), line:1:16, endln:1:17 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/TypeDefScope/dut.sv, line:1:1, endln:18:11 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/TypeDefScope/dut.sv, line:1:1, endln:18:11 |vpiName:b |vpiDirection:3 |vpiLowConn: @@ -1034,14 +1034,14 @@ design: (work@dut) |vpiActual: \_logic_net: (work@dut.b), line:1:16, endln:1:17 |uhdmtopModules: -\_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/TypeDefScope/dut.sv, line:1:1, endln:18:11 +\_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/TypeDefScope/dut.sv, line:1:1, endln:18:11 |vpiName:work@dut |vpiDefName:work@dut |vpiTop:1 |vpiTaskFunc: \_function: (work@dut.UVMC_set_config_object), line:3:4, endln:15:15 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/TypeDefScope/dut.sv, line:1:1, endln:18:11 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/TypeDefScope/dut.sv, line:1:1, endln:18:11 |vpiName:UVMC_set_config_object |vpiFullName:work@dut.UVMC_set_config_object |vpiVariables: @@ -1066,7 +1066,7 @@ design: (work@dut) \_ref_var: (work@dut.UVMC_set_config_object.comp), line:12:15, endln:12:19 |vpiVisibility:1 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/TypeDefScope/dut.sv, line:1:1, endln:18:11 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/TypeDefScope/dut.sv, line:1:1, endln:18:11 |vpiIODecl: \_io_decl: (type_name), line:3:49, endln:3:58 |vpiParent: @@ -1135,24 +1135,24 @@ design: (work@dut) |vpiTypedef: \_logic_typespec: (converter2), line:9:9, endln:9:14 |vpiInstance: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/TypeDefScope/dut.sv, line:1:1, endln:18:11 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/TypeDefScope/dut.sv, line:1:1, endln:18:11 |vpiNet: \_logic_net: (work@dut.a), line:1:13, endln:1:14 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/TypeDefScope/dut.sv, line:1:1, endln:18:11 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/TypeDefScope/dut.sv, line:1:1, endln:18:11 |vpiName:a |vpiFullName:work@dut.a |vpiNet: \_logic_net: (work@dut.b), line:1:16, endln:1:17 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/TypeDefScope/dut.sv, line:1:1, endln:18:11 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/TypeDefScope/dut.sv, line:1:1, endln:18:11 |vpiName:b |vpiFullName:work@dut.b |vpiTopModule:1 |vpiPort: \_port: (a), line:1:13, endln:1:14 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/TypeDefScope/dut.sv, line:1:1, endln:18:11 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/TypeDefScope/dut.sv, line:1:1, endln:18:11 |vpiName:a |vpiDirection:3 |vpiLowConn: @@ -1164,11 +1164,11 @@ design: (work@dut) |vpiActual: \_logic_net: (work@dut.a), line:1:13, endln:1:14 |vpiInstance: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/TypeDefScope/dut.sv, line:1:1, endln:18:11 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/TypeDefScope/dut.sv, line:1:1, endln:18:11 |vpiPort: \_port: (b), line:1:16, endln:1:17 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/TypeDefScope/dut.sv, line:1:1, endln:18:11 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/TypeDefScope/dut.sv, line:1:1, endln:18:11 |vpiName:b |vpiDirection:3 |vpiLowConn: @@ -1180,7 +1180,7 @@ design: (work@dut) |vpiActual: \_logic_net: (work@dut.b), line:1:16, endln:1:17 |vpiInstance: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/TypeDefScope/dut.sv, line:1:1, endln:18:11 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/TypeDefScope/dut.sv, line:1:1, endln:18:11 =================== [ FATAL] : 0 [ SYNTAX] : 0 diff --git a/tests/TypeParam/TypeParam.log b/tests/TypeParam/TypeParam.log index 0d073ed2a4..3c75c7384f 100644 --- a/tests/TypeParam/TypeParam.log +++ b/tests/TypeParam/TypeParam.log @@ -38,7 +38,7 @@ int_var 6 logic_net 5 logic_typespec 4 logic_var 2 -module 11 +module_inst 11 param_assign 3 parameter 3 range 4 @@ -55,7 +55,7 @@ int_var 6 logic_net 5 logic_typespec 4 logic_var 2 -module 11 +module_inst 11 param_assign 3 parameter 3 range 4 @@ -75,14 +75,14 @@ design: (work@top) |vpiElaborated:1 |vpiName:work@top |uhdmallModules: -\_module: work@bottom (work@bottom), file:${SURELOG_DIR}/tests/TypeParam/dut.sv, line:17:1, endln:21:10 +\_module_inst: work@bottom (work@bottom), file:${SURELOG_DIR}/tests/TypeParam/dut.sv, line:17:1, endln:21:10 |vpiParent: \_design: (work@top) |vpiFullName:work@bottom |vpiParameter: \_type_parameter: (work@bottom.TP1), line:17:32, endln:17:35 |vpiParent: - \_module: work@bottom (work@bottom), file:${SURELOG_DIR}/tests/TypeParam/dut.sv, line:17:1, endln:21:10 + \_module_inst: work@bottom (work@bottom), file:${SURELOG_DIR}/tests/TypeParam/dut.sv, line:17:1, endln:21:10 |vpiName:TP1 |vpiFullName:work@bottom.TP1 |vpiTypespec: @@ -92,7 +92,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@bottom.SIZE), line:17:55, endln:17:59 |vpiParent: - \_module: work@bottom (work@bottom), file:${SURELOG_DIR}/tests/TypeParam/dut.sv, line:17:1, endln:21:10 + \_module_inst: work@bottom (work@bottom), file:${SURELOG_DIR}/tests/TypeParam/dut.sv, line:17:1, endln:21:10 |UINT:10 |vpiTypespec: \_int_typespec: @@ -101,7 +101,7 @@ design: (work@top) |vpiParameter: \_type_parameter: (work@bottom.TP2), line:17:79, endln:17:82 |vpiParent: - \_module: work@bottom (work@bottom), file:${SURELOG_DIR}/tests/TypeParam/dut.sv, line:17:1, endln:21:10 + \_module_inst: work@bottom (work@bottom), file:${SURELOG_DIR}/tests/TypeParam/dut.sv, line:17:1, endln:21:10 |vpiName:TP2 |vpiFullName:work@bottom.TP2 |vpiTypespec: @@ -112,7 +112,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:17:55, endln:17:62 |vpiParent: - \_module: work@bottom (work@bottom), file:${SURELOG_DIR}/tests/TypeParam/dut.sv, line:17:1, endln:21:10 + \_module_inst: work@bottom (work@bottom), file:${SURELOG_DIR}/tests/TypeParam/dut.sv, line:17:1, endln:21:10 |vpiRhs: \_constant: , line:17:60, endln:17:62 |vpiDecompile:10 @@ -127,31 +127,31 @@ design: (work@top) |vpiNet: \_logic_net: (work@bottom.DATA1), line:18:9, endln:18:14 |vpiParent: - \_module: work@bottom (work@bottom), file:${SURELOG_DIR}/tests/TypeParam/dut.sv, line:17:1, endln:21:10 + \_module_inst: work@bottom (work@bottom), file:${SURELOG_DIR}/tests/TypeParam/dut.sv, line:17:1, endln:21:10 |vpiName:DATA1 |vpiFullName:work@bottom.DATA1 |vpiNet: \_logic_net: (work@bottom.a), line:19:20, endln:19:21 |vpiParent: - \_module: work@bottom (work@bottom), file:${SURELOG_DIR}/tests/TypeParam/dut.sv, line:17:1, endln:21:10 + \_module_inst: work@bottom (work@bottom), file:${SURELOG_DIR}/tests/TypeParam/dut.sv, line:17:1, endln:21:10 |vpiName:a |vpiFullName:work@bottom.a |vpiNetType:36 |vpiNet: \_logic_net: (work@bottom.DATA2), line:20:9, endln:20:14 |vpiParent: - \_module: work@bottom (work@bottom), file:${SURELOG_DIR}/tests/TypeParam/dut.sv, line:17:1, endln:21:10 + \_module_inst: work@bottom (work@bottom), file:${SURELOG_DIR}/tests/TypeParam/dut.sv, line:17:1, endln:21:10 |vpiName:DATA2 |vpiFullName:work@bottom.DATA2 |uhdmallModules: -\_module: work@mid (work@mid), file:${SURELOG_DIR}/tests/TypeParam/dut.sv, line:10:1, endln:15:10 +\_module_inst: work@mid (work@mid), file:${SURELOG_DIR}/tests/TypeParam/dut.sv, line:10:1, endln:15:10 |vpiParent: \_design: (work@top) |vpiFullName:work@mid |vpiParameter: \_type_parameter: (work@mid.TP0), line:10:29, endln:10:32 |vpiParent: - \_module: work@mid (work@mid), file:${SURELOG_DIR}/tests/TypeParam/dut.sv, line:10:1, endln:15:10 + \_module_inst: work@mid (work@mid), file:${SURELOG_DIR}/tests/TypeParam/dut.sv, line:10:1, endln:15:10 |vpiName:TP0 |vpiFullName:work@mid.TP0 |vpiTypespec: @@ -162,18 +162,18 @@ design: (work@top) |vpiNet: \_logic_net: (work@mid.DATA0), line:11:6, endln:11:11 |vpiParent: - \_module: work@mid (work@mid), file:${SURELOG_DIR}/tests/TypeParam/dut.sv, line:10:1, endln:15:10 + \_module_inst: work@mid (work@mid), file:${SURELOG_DIR}/tests/TypeParam/dut.sv, line:10:1, endln:15:10 |vpiName:DATA0 |vpiFullName:work@mid.DATA0 |uhdmallModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/TypeParam/dut.sv, line:1:1, endln:8:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/TypeParam/dut.sv, line:1:1, endln:8:10 |vpiParent: \_design: (work@top) |vpiFullName:work@top |vpiParameter: \_type_parameter: (work@top.TPTOP), line:2:16, endln:2:21 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/TypeParam/dut.sv, line:1:1, endln:8:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/TypeParam/dut.sv, line:1:1, endln:8:10 |vpiName:TPTOP |vpiFullName:work@top.TPTOP |vpiTypespec: @@ -185,16 +185,16 @@ design: (work@top) |vpiNet: \_logic_net: (work@top.DATATOP), line:4:8, endln:4:15 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/TypeParam/dut.sv, line:1:1, endln:8:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/TypeParam/dut.sv, line:1:1, endln:8:10 |vpiName:DATATOP |vpiFullName:work@top.DATATOP |uhdmtopModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/TypeParam/dut.sv, line:1:1, endln:8:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/TypeParam/dut.sv, line:1:1, endln:8:10 |vpiName:work@top |vpiVariables: \_int_var: (work@top.DATATOP), line:4:8, endln:4:15 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/TypeParam/dut.sv, line:1:1, endln:8:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/TypeParam/dut.sv, line:1:1, endln:8:10 |vpiTypespec: \_int_typespec: , line:2:24, endln:2:27 |vpiName:DATATOP @@ -205,16 +205,16 @@ design: (work@top) |vpiDefName:work@top |vpiTop:1 |vpiTopModule:1 - |vpiModule: - \_module: work@mid (work@top.u0), file:${SURELOG_DIR}/tests/TypeParam/dut.sv, line:6:3, endln:6:27 + |vpiModuleInst: + \_module_inst: work@mid (work@top.u0), file:${SURELOG_DIR}/tests/TypeParam/dut.sv, line:6:3, endln:6:27 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/TypeParam/dut.sv, line:1:1, endln:8:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/TypeParam/dut.sv, line:1:1, endln:8:10 |vpiName:u0 |vpiFullName:work@top.u0 |vpiVariables: \_int_var: (work@top.u0.DATA0), line:11:6, endln:11:11 |vpiParent: - \_module: work@mid (work@top.u0), file:${SURELOG_DIR}/tests/TypeParam/dut.sv, line:6:3, endln:6:27 + \_module_inst: work@mid (work@top.u0), file:${SURELOG_DIR}/tests/TypeParam/dut.sv, line:6:3, endln:6:27 |vpiTypespec: \_int_typespec: , line:2:24, endln:2:27 |vpiParent: @@ -226,7 +226,7 @@ design: (work@top) |vpiParameter: \_type_parameter: (work@top.u0.TP0) |vpiParent: - \_module: work@mid (work@top.u0), file:${SURELOG_DIR}/tests/TypeParam/dut.sv, line:6:3, endln:6:27 + \_module_inst: work@mid (work@top.u0), file:${SURELOG_DIR}/tests/TypeParam/dut.sv, line:6:3, endln:6:27 |vpiName:TP0 |vpiFullName:work@top.u0.TP0 |vpiTypespec: @@ -235,17 +235,17 @@ design: (work@top) |vpiDefFile:${SURELOG_DIR}/tests/TypeParam/dut.sv |vpiDefLineNo:10 |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/TypeParam/dut.sv, line:1:1, endln:8:10 - |vpiModule: - \_module: work@bottom (work@top.u0.u1), file:${SURELOG_DIR}/tests/TypeParam/dut.sv, line:12:2, endln:12:27 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/TypeParam/dut.sv, line:1:1, endln:8:10 + |vpiModuleInst: + \_module_inst: work@bottom (work@top.u0.u1), file:${SURELOG_DIR}/tests/TypeParam/dut.sv, line:12:2, endln:12:27 |vpiParent: - \_module: work@mid (work@top.u0), file:${SURELOG_DIR}/tests/TypeParam/dut.sv, line:6:3, endln:6:27 + \_module_inst: work@mid (work@top.u0), file:${SURELOG_DIR}/tests/TypeParam/dut.sv, line:6:3, endln:6:27 |vpiName:u1 |vpiFullName:work@top.u0.u1 |vpiVariables: \_int_var: (work@top.u0.u1.DATA1), line:18:9, endln:18:14 |vpiParent: - \_module: work@bottom (work@top.u0.u1), file:${SURELOG_DIR}/tests/TypeParam/dut.sv, line:12:2, endln:12:27 + \_module_inst: work@bottom (work@top.u0.u1), file:${SURELOG_DIR}/tests/TypeParam/dut.sv, line:12:2, endln:12:27 |vpiTypespec: \_int_typespec: , line:2:24, endln:2:27 |vpiParent: @@ -257,7 +257,7 @@ design: (work@top) |vpiVariables: \_logic_var: (work@top.u0.u1.a), line:19:20, endln:19:21 |vpiParent: - \_module: work@bottom (work@top.u0.u1), file:${SURELOG_DIR}/tests/TypeParam/dut.sv, line:12:2, endln:12:27 + \_module_inst: work@bottom (work@top.u0.u1), file:${SURELOG_DIR}/tests/TypeParam/dut.sv, line:12:2, endln:12:27 |vpiTypespec: \_logic_typespec: , line:19:5, endln:19:19 |vpiRange: @@ -302,7 +302,7 @@ design: (work@top) |vpiVariables: \_int_var: (work@top.u0.u1.DATA2), line:20:9, endln:20:14 |vpiParent: - \_module: work@bottom (work@top.u0.u1), file:${SURELOG_DIR}/tests/TypeParam/dut.sv, line:12:2, endln:12:27 + \_module_inst: work@bottom (work@top.u0.u1), file:${SURELOG_DIR}/tests/TypeParam/dut.sv, line:12:2, endln:12:27 |vpiTypespec: \_int_typespec: , line:17:85, endln:17:88 |vpiName:DATA2 @@ -311,7 +311,7 @@ design: (work@top) |vpiParameter: \_type_parameter: (work@top.u0.u1.TP1) |vpiParent: - \_module: work@bottom (work@top.u0.u1), file:${SURELOG_DIR}/tests/TypeParam/dut.sv, line:12:2, endln:12:27 + \_module_inst: work@bottom (work@top.u0.u1), file:${SURELOG_DIR}/tests/TypeParam/dut.sv, line:12:2, endln:12:27 |vpiName:TP1 |vpiFullName:work@top.u0.u1.TP1 |vpiTypespec: @@ -319,7 +319,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.u0.u1.SIZE), line:17:55, endln:17:59 |vpiParent: - \_module: work@bottom (work@top.u0.u1), file:${SURELOG_DIR}/tests/TypeParam/dut.sv, line:12:2, endln:12:27 + \_module_inst: work@bottom (work@top.u0.u1), file:${SURELOG_DIR}/tests/TypeParam/dut.sv, line:12:2, endln:12:27 |UINT:10 |vpiTypespec: \_int_typespec: @@ -332,7 +332,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:17:55, endln:17:62 |vpiParent: - \_module: work@bottom (work@top.u0.u1), file:${SURELOG_DIR}/tests/TypeParam/dut.sv, line:12:2, endln:12:27 + \_module_inst: work@bottom (work@top.u0.u1), file:${SURELOG_DIR}/tests/TypeParam/dut.sv, line:12:2, endln:12:27 |vpiRhs: \_constant: , line:17:60, endln:17:62 |vpiDecompile:10 @@ -347,17 +347,17 @@ design: (work@top) |vpiDefFile:${SURELOG_DIR}/tests/TypeParam/dut.sv |vpiDefLineNo:17 |vpiInstance: - \_module: work@mid (work@top.u0), file:${SURELOG_DIR}/tests/TypeParam/dut.sv, line:6:3, endln:6:27 - |vpiModule: - \_module: work@bottom (work@top.u0.u2), file:${SURELOG_DIR}/tests/TypeParam/dut.sv, line:13:2, endln:13:38 + \_module_inst: work@mid (work@top.u0), file:${SURELOG_DIR}/tests/TypeParam/dut.sv, line:6:3, endln:6:27 + |vpiModuleInst: + \_module_inst: work@bottom (work@top.u0.u2), file:${SURELOG_DIR}/tests/TypeParam/dut.sv, line:13:2, endln:13:38 |vpiParent: - \_module: work@mid (work@top.u0), file:${SURELOG_DIR}/tests/TypeParam/dut.sv, line:6:3, endln:6:27 + \_module_inst: work@mid (work@top.u0), file:${SURELOG_DIR}/tests/TypeParam/dut.sv, line:6:3, endln:6:27 |vpiName:u2 |vpiFullName:work@top.u0.u2 |vpiVariables: \_int_var: (work@top.u0.u2.DATA1), line:18:9, endln:18:14 |vpiParent: - \_module: work@bottom (work@top.u0.u2), file:${SURELOG_DIR}/tests/TypeParam/dut.sv, line:13:2, endln:13:38 + \_module_inst: work@bottom (work@top.u0.u2), file:${SURELOG_DIR}/tests/TypeParam/dut.sv, line:13:2, endln:13:38 |vpiTypespec: \_int_typespec: , line:13:16, endln:13:19 |vpiParent: @@ -369,7 +369,7 @@ design: (work@top) |vpiVariables: \_logic_var: (work@top.u0.u2.a), line:19:20, endln:19:21 |vpiParent: - \_module: work@bottom (work@top.u0.u2), file:${SURELOG_DIR}/tests/TypeParam/dut.sv, line:13:2, endln:13:38 + \_module_inst: work@bottom (work@top.u0.u2), file:${SURELOG_DIR}/tests/TypeParam/dut.sv, line:13:2, endln:13:38 |vpiTypespec: \_logic_typespec: , line:19:5, endln:19:19 |vpiRange: @@ -414,7 +414,7 @@ design: (work@top) |vpiVariables: \_int_var: (work@top.u0.u2.DATA2), line:20:9, endln:20:14 |vpiParent: - \_module: work@bottom (work@top.u0.u2), file:${SURELOG_DIR}/tests/TypeParam/dut.sv, line:13:2, endln:13:38 + \_module_inst: work@bottom (work@top.u0.u2), file:${SURELOG_DIR}/tests/TypeParam/dut.sv, line:13:2, endln:13:38 |vpiTypespec: \_int_typespec: , line:17:85, endln:17:88 |vpiName:DATA2 @@ -423,7 +423,7 @@ design: (work@top) |vpiParameter: \_type_parameter: (work@top.u0.u2.TP1) |vpiParent: - \_module: work@bottom (work@top.u0.u2), file:${SURELOG_DIR}/tests/TypeParam/dut.sv, line:13:2, endln:13:38 + \_module_inst: work@bottom (work@top.u0.u2), file:${SURELOG_DIR}/tests/TypeParam/dut.sv, line:13:2, endln:13:38 |vpiName:TP1 |vpiFullName:work@top.u0.u2.TP1 |vpiTypespec: @@ -431,7 +431,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.u0.u2.SIZE), line:17:55, endln:17:59 |vpiParent: - \_module: work@bottom (work@top.u0.u2), file:${SURELOG_DIR}/tests/TypeParam/dut.sv, line:13:2, endln:13:38 + \_module_inst: work@bottom (work@top.u0.u2), file:${SURELOG_DIR}/tests/TypeParam/dut.sv, line:13:2, endln:13:38 |UINT:10 |vpiTypespec: \_int_typespec: @@ -444,7 +444,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:17:55, endln:17:62 |vpiParent: - \_module: work@bottom (work@top.u0.u2), file:${SURELOG_DIR}/tests/TypeParam/dut.sv, line:13:2, endln:13:38 + \_module_inst: work@bottom (work@top.u0.u2), file:${SURELOG_DIR}/tests/TypeParam/dut.sv, line:13:2, endln:13:38 |vpiOverriden:1 |vpiRhs: \_constant: , line:17:60, endln:17:62 @@ -460,7 +460,7 @@ design: (work@top) |vpiDefFile:${SURELOG_DIR}/tests/TypeParam/dut.sv |vpiDefLineNo:17 |vpiInstance: - \_module: work@mid (work@top.u0), file:${SURELOG_DIR}/tests/TypeParam/dut.sv, line:6:3, endln:6:27 + \_module_inst: work@mid (work@top.u0), file:${SURELOG_DIR}/tests/TypeParam/dut.sv, line:6:3, endln:6:27 =================== [ FATAL] : 0 [ SYNTAX] : 0 diff --git a/tests/TypeParam2/TypeParam2.log b/tests/TypeParam2/TypeParam2.log index a0f8c2cbea..2a6fa62176 100644 --- a/tests/TypeParam2/TypeParam2.log +++ b/tests/TypeParam2/TypeParam2.log @@ -43,7 +43,7 @@ constant 6 design 1 logic_net 2 logic_typespec 7 -module 5 +module_inst 5 operation 1 range 3 ref_obj 2 @@ -64,14 +64,14 @@ typespec_member 6 design: (work@top) |vpiName:work@top |uhdmallModules: -\_module: work@rr_arb_tree (work@rr_arb_tree), file:${SURELOG_DIR}/tests/TypeParam2/dut.sv, line:1:1, endln:5:10 +\_module_inst: work@rr_arb_tree (work@rr_arb_tree), file:${SURELOG_DIR}/tests/TypeParam2/dut.sv, line:1:1, endln:5:10 |vpiParent: \_design: (work@top) |vpiFullName:work@rr_arb_tree |vpiParameter: \_type_parameter: (work@rr_arb_tree.DataType), line:2:26, endln:2:34 |vpiParent: - \_module: work@rr_arb_tree (work@rr_arb_tree), file:${SURELOG_DIR}/tests/TypeParam2/dut.sv, line:1:1, endln:5:10 + \_module_inst: work@rr_arb_tree (work@rr_arb_tree), file:${SURELOG_DIR}/tests/TypeParam2/dut.sv, line:1:1, endln:5:10 |vpiName:DataType |vpiFullName:work@rr_arb_tree.DataType |vpiTypespec: @@ -115,21 +115,21 @@ design: (work@top) |vpiNet: \_logic_net: (work@rr_arb_tree.data), line:3:12, endln:3:16 |vpiParent: - \_module: work@rr_arb_tree (work@rr_arb_tree), file:${SURELOG_DIR}/tests/TypeParam2/dut.sv, line:1:1, endln:5:10 + \_module_inst: work@rr_arb_tree (work@rr_arb_tree), file:${SURELOG_DIR}/tests/TypeParam2/dut.sv, line:1:1, endln:5:10 |vpiName:data |vpiFullName:work@rr_arb_tree.data |uhdmallModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/TypeParam2/dut.sv, line:8:1, endln:20:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/TypeParam2/dut.sv, line:8:1, endln:20:10 |vpiParent: \_design: (work@top) |vpiFullName:work@top |vpiTypedef: \_struct_typespec: (output_t), line:9:10, endln:9:16 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/TypeParam2/dut.sv, line:8:1, endln:20:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/TypeParam2/dut.sv, line:8:1, endln:20:10 |vpiName:output_t |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/TypeParam2/dut.sv, line:8:1, endln:20:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/TypeParam2/dut.sv, line:8:1, endln:20:10 |vpiPacked:1 |vpiTypespecMember: \_typespec_member: (result), line:10:19, endln:10:25 @@ -195,23 +195,23 @@ design: (work@top) |vpiRefEndColumnNo:10 |vpiDefName:work@top |uhdmtopModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/TypeParam2/dut.sv, line:8:1, endln:20:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/TypeParam2/dut.sv, line:8:1, endln:20:10 |vpiName:work@top |vpiTypedef: \_struct_typespec: (output_t), line:9:10, endln:9:16 |vpiDefName:work@top |vpiTop:1 |vpiTopModule:1 - |vpiModule: - \_module: work@rr_arb_tree (work@top.i_arbiter), file:${SURELOG_DIR}/tests/TypeParam2/dut.sv, line:15:2, endln:17:18 + |vpiModuleInst: + \_module_inst: work@rr_arb_tree (work@top.i_arbiter), file:${SURELOG_DIR}/tests/TypeParam2/dut.sv, line:15:2, endln:17:18 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/TypeParam2/dut.sv, line:8:1, endln:20:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/TypeParam2/dut.sv, line:8:1, endln:20:10 |vpiName:i_arbiter |vpiFullName:work@top.i_arbiter |vpiVariables: \_struct_var: (work@top.i_arbiter.data), line:3:12, endln:3:16 |vpiParent: - \_module: work@rr_arb_tree (work@top.i_arbiter), file:${SURELOG_DIR}/tests/TypeParam2/dut.sv, line:15:2, endln:17:18 + \_module_inst: work@rr_arb_tree (work@top.i_arbiter), file:${SURELOG_DIR}/tests/TypeParam2/dut.sv, line:15:2, endln:17:18 |vpiTypespec: \_struct_typespec: (output_t), line:9:10, endln:9:16 |vpiParent: @@ -286,7 +286,7 @@ design: (work@top) |vpiParameter: \_type_parameter: (work@top.i_arbiter.DataType) |vpiParent: - \_module: work@rr_arb_tree (work@top.i_arbiter), file:${SURELOG_DIR}/tests/TypeParam2/dut.sv, line:15:2, endln:17:18 + \_module_inst: work@rr_arb_tree (work@top.i_arbiter), file:${SURELOG_DIR}/tests/TypeParam2/dut.sv, line:15:2, endln:17:18 |vpiName:DataType |vpiFullName:work@top.i_arbiter.DataType |vpiTypespec: @@ -299,7 +299,7 @@ design: (work@top) |vpiName:DataWidth |vpiNetType:1 |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/TypeParam2/dut.sv, line:8:1, endln:20:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/TypeParam2/dut.sv, line:8:1, endln:20:10 =================== [ FATAL] : 0 [ SYNTAX] : 0 diff --git a/tests/TypeParamElab/TypeParamElab.log b/tests/TypeParamElab/TypeParamElab.log index 86d8057124..3880aec682 100644 --- a/tests/TypeParamElab/TypeParamElab.log +++ b/tests/TypeParamElab/TypeParamElab.log @@ -312,7 +312,7 @@ int_typespec 6 integer_typespec 4 logic_net 1 logic_typespec 8 -module 13 +module_inst 13 operation 8 param_assign 14 parameter 14 @@ -334,7 +334,7 @@ int_typespec 6 integer_typespec 4 logic_net 1 logic_typespec 8 -module 13 +module_inst 13 operation 8 param_assign 14 parameter 14 @@ -360,14 +360,14 @@ design: (work@axi_node_arbiter) |vpiElaborated:1 |vpiName:work@axi_node_arbiter |uhdmallModules: -\_module: work@axi_node_arbiter (work@axi_node_arbiter), file:${SURELOG_DIR}/tests/TypeParamElab/dut.sv, line:22:1, endln:37:10 +\_module_inst: work@axi_node_arbiter (work@axi_node_arbiter), file:${SURELOG_DIR}/tests/TypeParamElab/dut.sv, line:22:1, endln:37:10 |vpiParent: \_design: (work@axi_node_arbiter) |vpiFullName:work@axi_node_arbiter |vpiParameter: \_parameter: (work@axi_node_arbiter.AUX_WIDTH), line:23:26, endln:23:35 |vpiParent: - \_module: work@axi_node_arbiter (work@axi_node_arbiter), file:${SURELOG_DIR}/tests/TypeParamElab/dut.sv, line:22:1, endln:37:10 + \_module_inst: work@axi_node_arbiter (work@axi_node_arbiter), file:${SURELOG_DIR}/tests/TypeParamElab/dut.sv, line:22:1, endln:37:10 |UINT:5 |vpiTypespec: \_int_typespec: , line:23:13, endln:23:25 @@ -378,7 +378,7 @@ design: (work@axi_node_arbiter) |vpiParameter: \_parameter: (work@axi_node_arbiter.ID_WIDTH), line:24:26, endln:24:34 |vpiParent: - \_module: work@axi_node_arbiter (work@axi_node_arbiter), file:${SURELOG_DIR}/tests/TypeParamElab/dut.sv, line:22:1, endln:37:10 + \_module_inst: work@axi_node_arbiter (work@axi_node_arbiter), file:${SURELOG_DIR}/tests/TypeParamElab/dut.sv, line:22:1, endln:37:10 |UINT:5 |vpiTypespec: \_int_typespec: , line:24:13, endln:24:25 @@ -389,7 +389,7 @@ design: (work@axi_node_arbiter) |vpiParameter: \_parameter: (work@axi_node_arbiter.N_MASTER), line:25:26, endln:25:34 |vpiParent: - \_module: work@axi_node_arbiter (work@axi_node_arbiter), file:${SURELOG_DIR}/tests/TypeParamElab/dut.sv, line:22:1, endln:37:10 + \_module_inst: work@axi_node_arbiter (work@axi_node_arbiter), file:${SURELOG_DIR}/tests/TypeParamElab/dut.sv, line:22:1, endln:37:10 |UINT:10 |vpiTypespec: \_int_typespec: , line:25:13, endln:25:25 @@ -400,7 +400,7 @@ design: (work@axi_node_arbiter) |vpiParamAssign: \_param_assign: , line:23:26, endln:23:39 |vpiParent: - \_module: work@axi_node_arbiter (work@axi_node_arbiter), file:${SURELOG_DIR}/tests/TypeParamElab/dut.sv, line:22:1, endln:37:10 + \_module_inst: work@axi_node_arbiter (work@axi_node_arbiter), file:${SURELOG_DIR}/tests/TypeParamElab/dut.sv, line:22:1, endln:37:10 |vpiRhs: \_constant: , line:23:38, endln:23:39 |vpiDecompile:5 @@ -414,7 +414,7 @@ design: (work@axi_node_arbiter) |vpiParamAssign: \_param_assign: , line:24:26, endln:24:38 |vpiParent: - \_module: work@axi_node_arbiter (work@axi_node_arbiter), file:${SURELOG_DIR}/tests/TypeParamElab/dut.sv, line:22:1, endln:37:10 + \_module_inst: work@axi_node_arbiter (work@axi_node_arbiter), file:${SURELOG_DIR}/tests/TypeParamElab/dut.sv, line:22:1, endln:37:10 |vpiRhs: \_constant: , line:24:37, endln:24:38 |vpiDecompile:5 @@ -428,7 +428,7 @@ design: (work@axi_node_arbiter) |vpiParamAssign: \_param_assign: , line:25:26, endln:25:39 |vpiParent: - \_module: work@axi_node_arbiter (work@axi_node_arbiter), file:${SURELOG_DIR}/tests/TypeParamElab/dut.sv, line:22:1, endln:37:10 + \_module_inst: work@axi_node_arbiter (work@axi_node_arbiter), file:${SURELOG_DIR}/tests/TypeParamElab/dut.sv, line:22:1, endln:37:10 |vpiRhs: \_constant: , line:25:37, endln:25:39 |vpiDecompile:10 @@ -442,10 +442,10 @@ design: (work@axi_node_arbiter) |vpiTypedef: \_struct_typespec: (axi_meta_t), line:27:11, endln:27:17 |vpiParent: - \_module: work@axi_node_arbiter (work@axi_node_arbiter), file:${SURELOG_DIR}/tests/TypeParamElab/dut.sv, line:22:1, endln:37:10 + \_module_inst: work@axi_node_arbiter (work@axi_node_arbiter), file:${SURELOG_DIR}/tests/TypeParamElab/dut.sv, line:22:1, endln:37:10 |vpiName:axi_meta_t |vpiInstance: - \_module: work@axi_node_arbiter (work@axi_node_arbiter), file:${SURELOG_DIR}/tests/TypeParamElab/dut.sv, line:22:1, endln:37:10 + \_module_inst: work@axi_node_arbiter (work@axi_node_arbiter), file:${SURELOG_DIR}/tests/TypeParamElab/dut.sv, line:22:1, endln:37:10 |vpiPacked:1 |vpiTypespecMember: \_typespec_member: (aux), line:28:27, endln:28:30 @@ -543,14 +543,14 @@ design: (work@axi_node_arbiter) |vpiRefEndColumnNo:25 |vpiDefName:work@axi_node_arbiter |uhdmallModules: -\_module: work@stream_arbiter (work@stream_arbiter), file:${SURELOG_DIR}/tests/TypeParamElab/dut.sv, line:9:1, endln:20:10 +\_module_inst: work@stream_arbiter (work@stream_arbiter), file:${SURELOG_DIR}/tests/TypeParamElab/dut.sv, line:9:1, endln:20:10 |vpiParent: \_design: (work@axi_node_arbiter) |vpiFullName:work@stream_arbiter |vpiParameter: \_type_parameter: (work@stream_arbiter.DATA_T), line:10:25, endln:10:31 |vpiParent: - \_module: work@stream_arbiter (work@stream_arbiter), file:${SURELOG_DIR}/tests/TypeParamElab/dut.sv, line:9:1, endln:20:10 + \_module_inst: work@stream_arbiter (work@stream_arbiter), file:${SURELOG_DIR}/tests/TypeParamElab/dut.sv, line:9:1, endln:20:10 |vpiName:DATA_T |vpiFullName:work@stream_arbiter.DATA_T |vpiTypespec: @@ -560,7 +560,7 @@ design: (work@axi_node_arbiter) |vpiParameter: \_parameter: (work@stream_arbiter.N_INP), line:11:25, endln:11:30 |vpiParent: - \_module: work@stream_arbiter (work@stream_arbiter), file:${SURELOG_DIR}/tests/TypeParamElab/dut.sv, line:9:1, endln:20:10 + \_module_inst: work@stream_arbiter (work@stream_arbiter), file:${SURELOG_DIR}/tests/TypeParamElab/dut.sv, line:9:1, endln:20:10 |vpiTypespec: \_integer_typespec: , line:11:15, endln:11:22 |vpiParent: @@ -572,7 +572,7 @@ design: (work@axi_node_arbiter) |vpiParameter: \_parameter: (work@stream_arbiter.ARBITER), line:12:25, endln:12:32 |vpiParent: - \_module: work@stream_arbiter (work@stream_arbiter), file:${SURELOG_DIR}/tests/TypeParamElab/dut.sv, line:9:1, endln:20:10 + \_module_inst: work@stream_arbiter (work@stream_arbiter), file:${SURELOG_DIR}/tests/TypeParamElab/dut.sv, line:9:1, endln:20:10 |STRING:rr |vpiTypespec: \_string_typespec: @@ -581,7 +581,7 @@ design: (work@axi_node_arbiter) |vpiParamAssign: \_param_assign: , line:11:25, endln:11:35 |vpiParent: - \_module: work@stream_arbiter (work@stream_arbiter), file:${SURELOG_DIR}/tests/TypeParamElab/dut.sv, line:9:1, endln:20:10 + \_module_inst: work@stream_arbiter (work@stream_arbiter), file:${SURELOG_DIR}/tests/TypeParamElab/dut.sv, line:9:1, endln:20:10 |vpiRhs: \_operation: , line:11:33, endln:11:35 |vpiOpType:1 @@ -596,7 +596,7 @@ design: (work@axi_node_arbiter) |vpiParamAssign: \_param_assign: , line:12:25, endln:12:39 |vpiParent: - \_module: work@stream_arbiter (work@stream_arbiter), file:${SURELOG_DIR}/tests/TypeParamElab/dut.sv, line:9:1, endln:20:10 + \_module_inst: work@stream_arbiter (work@stream_arbiter), file:${SURELOG_DIR}/tests/TypeParamElab/dut.sv, line:9:1, endln:20:10 |vpiRhs: \_constant: , line:12:35, endln:12:39 |vpiDecompile:rr @@ -609,14 +609,14 @@ design: (work@axi_node_arbiter) \_parameter: (work@stream_arbiter.ARBITER), line:12:25, endln:12:32 |vpiDefName:work@stream_arbiter |uhdmallModules: -\_module: work@stream_arbiter_flushable (work@stream_arbiter_flushable), file:${SURELOG_DIR}/tests/TypeParamElab/dut.sv, line:1:1, endln:7:10 +\_module_inst: work@stream_arbiter_flushable (work@stream_arbiter_flushable), file:${SURELOG_DIR}/tests/TypeParamElab/dut.sv, line:1:1, endln:7:10 |vpiParent: \_design: (work@axi_node_arbiter) |vpiFullName:work@stream_arbiter_flushable |vpiParameter: \_type_parameter: (work@stream_arbiter_flushable.DATA_T), line:2:25, endln:2:31 |vpiParent: - \_module: work@stream_arbiter_flushable (work@stream_arbiter_flushable), file:${SURELOG_DIR}/tests/TypeParamElab/dut.sv, line:1:1, endln:7:10 + \_module_inst: work@stream_arbiter_flushable (work@stream_arbiter_flushable), file:${SURELOG_DIR}/tests/TypeParamElab/dut.sv, line:1:1, endln:7:10 |vpiName:DATA_T |vpiFullName:work@stream_arbiter_flushable.DATA_T |vpiTypespec: @@ -626,7 +626,7 @@ design: (work@axi_node_arbiter) |vpiParameter: \_parameter: (work@stream_arbiter_flushable.N_INP), line:3:25, endln:3:30 |vpiParent: - \_module: work@stream_arbiter_flushable (work@stream_arbiter_flushable), file:${SURELOG_DIR}/tests/TypeParamElab/dut.sv, line:1:1, endln:7:10 + \_module_inst: work@stream_arbiter_flushable (work@stream_arbiter_flushable), file:${SURELOG_DIR}/tests/TypeParamElab/dut.sv, line:1:1, endln:7:10 |vpiTypespec: \_integer_typespec: , line:3:15, endln:3:22 |vpiParent: @@ -638,7 +638,7 @@ design: (work@axi_node_arbiter) |vpiParameter: \_parameter: (work@stream_arbiter_flushable.ARBITER), line:4:25, endln:4:32 |vpiParent: - \_module: work@stream_arbiter_flushable (work@stream_arbiter_flushable), file:${SURELOG_DIR}/tests/TypeParamElab/dut.sv, line:1:1, endln:7:10 + \_module_inst: work@stream_arbiter_flushable (work@stream_arbiter_flushable), file:${SURELOG_DIR}/tests/TypeParamElab/dut.sv, line:1:1, endln:7:10 |STRING:rr |vpiTypespec: \_string_typespec: @@ -647,7 +647,7 @@ design: (work@axi_node_arbiter) |vpiParamAssign: \_param_assign: , line:3:25, endln:3:35 |vpiParent: - \_module: work@stream_arbiter_flushable (work@stream_arbiter_flushable), file:${SURELOG_DIR}/tests/TypeParamElab/dut.sv, line:1:1, endln:7:10 + \_module_inst: work@stream_arbiter_flushable (work@stream_arbiter_flushable), file:${SURELOG_DIR}/tests/TypeParamElab/dut.sv, line:1:1, endln:7:10 |vpiRhs: \_operation: , line:3:33, endln:3:35 |vpiOpType:1 @@ -662,7 +662,7 @@ design: (work@axi_node_arbiter) |vpiParamAssign: \_param_assign: , line:4:25, endln:4:39 |vpiParent: - \_module: work@stream_arbiter_flushable (work@stream_arbiter_flushable), file:${SURELOG_DIR}/tests/TypeParamElab/dut.sv, line:1:1, endln:7:10 + \_module_inst: work@stream_arbiter_flushable (work@stream_arbiter_flushable), file:${SURELOG_DIR}/tests/TypeParamElab/dut.sv, line:1:1, endln:7:10 |vpiRhs: \_constant: , line:4:35, endln:4:39 |vpiDecompile:rr @@ -677,13 +677,13 @@ design: (work@axi_node_arbiter) |vpiNet: \_logic_net: (work@stream_arbiter_flushable.oup_data_o), line:5:30, endln:5:40 |vpiParent: - \_module: work@stream_arbiter_flushable (work@stream_arbiter_flushable), file:${SURELOG_DIR}/tests/TypeParamElab/dut.sv, line:1:1, endln:7:10 + \_module_inst: work@stream_arbiter_flushable (work@stream_arbiter_flushable), file:${SURELOG_DIR}/tests/TypeParamElab/dut.sv, line:1:1, endln:7:10 |vpiName:oup_data_o |vpiFullName:work@stream_arbiter_flushable.oup_data_o |vpiPort: \_port: (oup_data_o), line:5:30, endln:5:40 |vpiParent: - \_module: work@stream_arbiter_flushable (work@stream_arbiter_flushable), file:${SURELOG_DIR}/tests/TypeParamElab/dut.sv, line:1:1, endln:7:10 + \_module_inst: work@stream_arbiter_flushable (work@stream_arbiter_flushable), file:${SURELOG_DIR}/tests/TypeParamElab/dut.sv, line:1:1, endln:7:10 |vpiName:oup_data_o |vpiDirection:2 |vpiLowConn: @@ -693,12 +693,12 @@ design: (work@axi_node_arbiter) |vpiTypedef: \_logic_typespec: , line:2:34, endln:2:39 |uhdmtopModules: -\_module: work@axi_node_arbiter (work@axi_node_arbiter), file:${SURELOG_DIR}/tests/TypeParamElab/dut.sv, line:22:1, endln:37:10 +\_module_inst: work@axi_node_arbiter (work@axi_node_arbiter), file:${SURELOG_DIR}/tests/TypeParamElab/dut.sv, line:22:1, endln:37:10 |vpiName:work@axi_node_arbiter |vpiParameter: \_parameter: (work@axi_node_arbiter.AUX_WIDTH), line:23:26, endln:23:35 |vpiParent: - \_module: work@axi_node_arbiter (work@axi_node_arbiter), file:${SURELOG_DIR}/tests/TypeParamElab/dut.sv, line:22:1, endln:37:10 + \_module_inst: work@axi_node_arbiter (work@axi_node_arbiter), file:${SURELOG_DIR}/tests/TypeParamElab/dut.sv, line:22:1, endln:37:10 |UINT:5 |vpiTypespec: \_int_typespec: , line:23:13, endln:23:25 @@ -709,7 +709,7 @@ design: (work@axi_node_arbiter) |vpiParameter: \_parameter: (work@axi_node_arbiter.ID_WIDTH), line:24:26, endln:24:34 |vpiParent: - \_module: work@axi_node_arbiter (work@axi_node_arbiter), file:${SURELOG_DIR}/tests/TypeParamElab/dut.sv, line:22:1, endln:37:10 + \_module_inst: work@axi_node_arbiter (work@axi_node_arbiter), file:${SURELOG_DIR}/tests/TypeParamElab/dut.sv, line:22:1, endln:37:10 |UINT:5 |vpiTypespec: \_int_typespec: , line:24:13, endln:24:25 @@ -720,7 +720,7 @@ design: (work@axi_node_arbiter) |vpiParameter: \_parameter: (work@axi_node_arbiter.N_MASTER), line:25:26, endln:25:34 |vpiParent: - \_module: work@axi_node_arbiter (work@axi_node_arbiter), file:${SURELOG_DIR}/tests/TypeParamElab/dut.sv, line:22:1, endln:37:10 + \_module_inst: work@axi_node_arbiter (work@axi_node_arbiter), file:${SURELOG_DIR}/tests/TypeParamElab/dut.sv, line:22:1, endln:37:10 |UINT:10 |vpiTypespec: \_int_typespec: , line:25:13, endln:25:25 @@ -731,7 +731,7 @@ design: (work@axi_node_arbiter) |vpiParamAssign: \_param_assign: , line:23:26, endln:23:39 |vpiParent: - \_module: work@axi_node_arbiter (work@axi_node_arbiter), file:${SURELOG_DIR}/tests/TypeParamElab/dut.sv, line:22:1, endln:37:10 + \_module_inst: work@axi_node_arbiter (work@axi_node_arbiter), file:${SURELOG_DIR}/tests/TypeParamElab/dut.sv, line:22:1, endln:37:10 |vpiRhs: \_constant: , line:23:38, endln:23:39 |vpiDecompile:5 @@ -745,7 +745,7 @@ design: (work@axi_node_arbiter) |vpiParamAssign: \_param_assign: , line:24:26, endln:24:38 |vpiParent: - \_module: work@axi_node_arbiter (work@axi_node_arbiter), file:${SURELOG_DIR}/tests/TypeParamElab/dut.sv, line:22:1, endln:37:10 + \_module_inst: work@axi_node_arbiter (work@axi_node_arbiter), file:${SURELOG_DIR}/tests/TypeParamElab/dut.sv, line:22:1, endln:37:10 |vpiRhs: \_constant: , line:24:37, endln:24:38 |vpiDecompile:5 @@ -759,7 +759,7 @@ design: (work@axi_node_arbiter) |vpiParamAssign: \_param_assign: , line:25:26, endln:25:39 |vpiParent: - \_module: work@axi_node_arbiter (work@axi_node_arbiter), file:${SURELOG_DIR}/tests/TypeParamElab/dut.sv, line:22:1, endln:37:10 + \_module_inst: work@axi_node_arbiter (work@axi_node_arbiter), file:${SURELOG_DIR}/tests/TypeParamElab/dut.sv, line:22:1, endln:37:10 |vpiRhs: \_constant: , line:25:37, endln:25:39 |vpiDecompile:10 @@ -775,16 +775,16 @@ design: (work@axi_node_arbiter) |vpiDefName:work@axi_node_arbiter |vpiTop:1 |vpiTopModule:1 - |vpiModule: - \_module: work@stream_arbiter (work@axi_node_arbiter.i_arb_inp), file:${SURELOG_DIR}/tests/TypeParamElab/dut.sv, line:32:2, endln:35:19 + |vpiModuleInst: + \_module_inst: work@stream_arbiter (work@axi_node_arbiter.i_arb_inp), file:${SURELOG_DIR}/tests/TypeParamElab/dut.sv, line:32:2, endln:35:19 |vpiParent: - \_module: work@axi_node_arbiter (work@axi_node_arbiter), file:${SURELOG_DIR}/tests/TypeParamElab/dut.sv, line:22:1, endln:37:10 + \_module_inst: work@axi_node_arbiter (work@axi_node_arbiter), file:${SURELOG_DIR}/tests/TypeParamElab/dut.sv, line:22:1, endln:37:10 |vpiName:i_arb_inp |vpiFullName:work@axi_node_arbiter.i_arb_inp |vpiParameter: \_type_parameter: (work@axi_node_arbiter.i_arb_inp.DATA_T) |vpiParent: - \_module: work@stream_arbiter (work@axi_node_arbiter.i_arb_inp), file:${SURELOG_DIR}/tests/TypeParamElab/dut.sv, line:32:2, endln:35:19 + \_module_inst: work@stream_arbiter (work@axi_node_arbiter.i_arb_inp), file:${SURELOG_DIR}/tests/TypeParamElab/dut.sv, line:32:2, endln:35:19 |vpiName:DATA_T |vpiFullName:work@axi_node_arbiter.i_arb_inp.DATA_T |vpiTypespec: @@ -890,7 +890,7 @@ design: (work@axi_node_arbiter) |vpiParameter: \_parameter: (work@axi_node_arbiter.i_arb_inp.N_INP), line:11:25, endln:11:30 |vpiParent: - \_module: work@stream_arbiter (work@axi_node_arbiter.i_arb_inp), file:${SURELOG_DIR}/tests/TypeParamElab/dut.sv, line:32:2, endln:35:19 + \_module_inst: work@stream_arbiter (work@axi_node_arbiter.i_arb_inp), file:${SURELOG_DIR}/tests/TypeParamElab/dut.sv, line:32:2, endln:35:19 |vpiTypespec: \_integer_typespec: , line:11:15, endln:11:22 |vpiParent: @@ -902,7 +902,7 @@ design: (work@axi_node_arbiter) |vpiParameter: \_parameter: (work@axi_node_arbiter.i_arb_inp.ARBITER), line:12:25, endln:12:32 |vpiParent: - \_module: work@stream_arbiter (work@axi_node_arbiter.i_arb_inp), file:${SURELOG_DIR}/tests/TypeParamElab/dut.sv, line:32:2, endln:35:19 + \_module_inst: work@stream_arbiter (work@axi_node_arbiter.i_arb_inp), file:${SURELOG_DIR}/tests/TypeParamElab/dut.sv, line:32:2, endln:35:19 |STRING:rr |vpiTypespec: \_string_typespec: @@ -913,7 +913,7 @@ design: (work@axi_node_arbiter) |vpiParamAssign: \_param_assign: , line:11:25, endln:11:35 |vpiParent: - \_module: work@stream_arbiter (work@axi_node_arbiter.i_arb_inp), file:${SURELOG_DIR}/tests/TypeParamElab/dut.sv, line:32:2, endln:35:19 + \_module_inst: work@stream_arbiter (work@axi_node_arbiter.i_arb_inp), file:${SURELOG_DIR}/tests/TypeParamElab/dut.sv, line:32:2, endln:35:19 |vpiOverriden:1 |vpiRhs: \_constant: , line:11:33, endln:11:35 @@ -928,7 +928,7 @@ design: (work@axi_node_arbiter) |vpiParamAssign: \_param_assign: , line:12:25, endln:12:39 |vpiParent: - \_module: work@stream_arbiter (work@axi_node_arbiter.i_arb_inp), file:${SURELOG_DIR}/tests/TypeParamElab/dut.sv, line:32:2, endln:35:19 + \_module_inst: work@stream_arbiter (work@axi_node_arbiter.i_arb_inp), file:${SURELOG_DIR}/tests/TypeParamElab/dut.sv, line:32:2, endln:35:19 |vpiRhs: \_constant: , line:12:35, endln:12:39 |vpiDecompile:rr @@ -943,17 +943,17 @@ design: (work@axi_node_arbiter) |vpiDefFile:${SURELOG_DIR}/tests/TypeParamElab/dut.sv |vpiDefLineNo:9 |vpiInstance: - \_module: work@axi_node_arbiter (work@axi_node_arbiter), file:${SURELOG_DIR}/tests/TypeParamElab/dut.sv, line:22:1, endln:37:10 - |vpiModule: - \_module: work@stream_arbiter_flushable (work@axi_node_arbiter.i_arb_inp.i_arb), file:${SURELOG_DIR}/tests/TypeParamElab/dut.sv, line:14:3, endln:18:14 + \_module_inst: work@axi_node_arbiter (work@axi_node_arbiter), file:${SURELOG_DIR}/tests/TypeParamElab/dut.sv, line:22:1, endln:37:10 + |vpiModuleInst: + \_module_inst: work@stream_arbiter_flushable (work@axi_node_arbiter.i_arb_inp.i_arb), file:${SURELOG_DIR}/tests/TypeParamElab/dut.sv, line:14:3, endln:18:14 |vpiParent: - \_module: work@stream_arbiter (work@axi_node_arbiter.i_arb_inp), file:${SURELOG_DIR}/tests/TypeParamElab/dut.sv, line:32:2, endln:35:19 + \_module_inst: work@stream_arbiter (work@axi_node_arbiter.i_arb_inp), file:${SURELOG_DIR}/tests/TypeParamElab/dut.sv, line:32:2, endln:35:19 |vpiName:i_arb |vpiFullName:work@axi_node_arbiter.i_arb_inp.i_arb |vpiVariables: \_struct_var: (work@axi_node_arbiter.i_arb_inp.i_arb.oup_data_o), line:5:30, endln:5:40 |vpiParent: - \_module: work@stream_arbiter_flushable (work@axi_node_arbiter.i_arb_inp.i_arb), file:${SURELOG_DIR}/tests/TypeParamElab/dut.sv, line:14:3, endln:18:14 + \_module_inst: work@stream_arbiter_flushable (work@axi_node_arbiter.i_arb_inp.i_arb), file:${SURELOG_DIR}/tests/TypeParamElab/dut.sv, line:14:3, endln:18:14 |vpiTypespec: \_struct_typespec: (axi_meta_t), line:27:11, endln:27:17 |vpiParent: @@ -1060,7 +1060,7 @@ design: (work@axi_node_arbiter) |vpiParameter: \_type_parameter: (work@axi_node_arbiter.i_arb_inp.i_arb.DATA_T) |vpiParent: - \_module: work@stream_arbiter_flushable (work@axi_node_arbiter.i_arb_inp.i_arb), file:${SURELOG_DIR}/tests/TypeParamElab/dut.sv, line:14:3, endln:18:14 + \_module_inst: work@stream_arbiter_flushable (work@axi_node_arbiter.i_arb_inp.i_arb), file:${SURELOG_DIR}/tests/TypeParamElab/dut.sv, line:14:3, endln:18:14 |vpiName:DATA_T |vpiFullName:work@axi_node_arbiter.i_arb_inp.i_arb.DATA_T |vpiTypespec: @@ -1068,7 +1068,7 @@ design: (work@axi_node_arbiter) |vpiParameter: \_parameter: (work@axi_node_arbiter.i_arb_inp.i_arb.N_INP), line:3:25, endln:3:30 |vpiParent: - \_module: work@stream_arbiter_flushable (work@axi_node_arbiter.i_arb_inp.i_arb), file:${SURELOG_DIR}/tests/TypeParamElab/dut.sv, line:14:3, endln:18:14 + \_module_inst: work@stream_arbiter_flushable (work@axi_node_arbiter.i_arb_inp.i_arb), file:${SURELOG_DIR}/tests/TypeParamElab/dut.sv, line:14:3, endln:18:14 |vpiTypespec: \_integer_typespec: , line:3:15, endln:3:22 |vpiParent: @@ -1080,7 +1080,7 @@ design: (work@axi_node_arbiter) |vpiParameter: \_parameter: (work@axi_node_arbiter.i_arb_inp.i_arb.ARBITER), line:4:25, endln:4:32 |vpiParent: - \_module: work@stream_arbiter_flushable (work@axi_node_arbiter.i_arb_inp.i_arb), file:${SURELOG_DIR}/tests/TypeParamElab/dut.sv, line:14:3, endln:18:14 + \_module_inst: work@stream_arbiter_flushable (work@axi_node_arbiter.i_arb_inp.i_arb), file:${SURELOG_DIR}/tests/TypeParamElab/dut.sv, line:14:3, endln:18:14 |STRING:rr |vpiTypespec: \_string_typespec: @@ -1091,7 +1091,7 @@ design: (work@axi_node_arbiter) |vpiParamAssign: \_param_assign: , line:3:25, endln:3:35 |vpiParent: - \_module: work@stream_arbiter_flushable (work@axi_node_arbiter.i_arb_inp.i_arb), file:${SURELOG_DIR}/tests/TypeParamElab/dut.sv, line:14:3, endln:18:14 + \_module_inst: work@stream_arbiter_flushable (work@axi_node_arbiter.i_arb_inp.i_arb), file:${SURELOG_DIR}/tests/TypeParamElab/dut.sv, line:14:3, endln:18:14 |vpiOverriden:1 |vpiRhs: \_constant: , line:3:33, endln:3:35 @@ -1106,7 +1106,7 @@ design: (work@axi_node_arbiter) |vpiParamAssign: \_param_assign: , line:4:25, endln:4:39 |vpiParent: - \_module: work@stream_arbiter_flushable (work@axi_node_arbiter.i_arb_inp.i_arb), file:${SURELOG_DIR}/tests/TypeParamElab/dut.sv, line:14:3, endln:18:14 + \_module_inst: work@stream_arbiter_flushable (work@axi_node_arbiter.i_arb_inp.i_arb), file:${SURELOG_DIR}/tests/TypeParamElab/dut.sv, line:14:3, endln:18:14 |vpiOverriden:1 |vpiRhs: \_constant: , line:4:35, endln:4:39 @@ -1122,11 +1122,11 @@ design: (work@axi_node_arbiter) |vpiDefFile:${SURELOG_DIR}/tests/TypeParamElab/dut.sv |vpiDefLineNo:1 |vpiInstance: - \_module: work@stream_arbiter (work@axi_node_arbiter.i_arb_inp), file:${SURELOG_DIR}/tests/TypeParamElab/dut.sv, line:32:2, endln:35:19 + \_module_inst: work@stream_arbiter (work@axi_node_arbiter.i_arb_inp), file:${SURELOG_DIR}/tests/TypeParamElab/dut.sv, line:32:2, endln:35:19 |vpiPort: \_port: (oup_data_o), line:5:30, endln:5:40 |vpiParent: - \_module: work@stream_arbiter_flushable (work@axi_node_arbiter.i_arb_inp.i_arb), file:${SURELOG_DIR}/tests/TypeParamElab/dut.sv, line:14:3, endln:18:14 + \_module_inst: work@stream_arbiter_flushable (work@axi_node_arbiter.i_arb_inp.i_arb), file:${SURELOG_DIR}/tests/TypeParamElab/dut.sv, line:14:3, endln:18:14 |vpiName:oup_data_o |vpiDirection:2 |vpiLowConn: @@ -1140,7 +1140,7 @@ design: (work@axi_node_arbiter) |vpiTypedef: \_logic_typespec: , line:2:34, endln:2:39 |vpiInstance: - \_module: work@stream_arbiter_flushable (work@axi_node_arbiter.i_arb_inp.i_arb), file:${SURELOG_DIR}/tests/TypeParamElab/dut.sv, line:14:3, endln:18:14 + \_module_inst: work@stream_arbiter_flushable (work@axi_node_arbiter.i_arb_inp.i_arb), file:${SURELOG_DIR}/tests/TypeParamElab/dut.sv, line:14:3, endln:18:14 =================== [ FATAL] : 0 [ SYNTAX] : 0 diff --git a/tests/TypeParamOverride/TypeParamOverride.log b/tests/TypeParamOverride/TypeParamOverride.log index 1d1c92acbf..1d68615383 100644 --- a/tests/TypeParamOverride/TypeParamOverride.log +++ b/tests/TypeParamOverride/TypeParamOverride.log @@ -153,7 +153,7 @@ design 1 hier_path 1 logic_net 1 logic_typespec 5 -module 5 +module_inst 5 named_begin 1 package 3 ref_obj 3 @@ -172,7 +172,7 @@ design 1 hier_path 2 logic_net 1 logic_typespec 5 -module 5 +module_inst 5 named_begin 2 package 3 ref_obj 5 @@ -289,20 +289,20 @@ design: (work@ariane_testharness) |vpiDefName:ariane_axi_soc |vpiTop:1 |uhdmallModules: -\_module: work@ariane_testharness (work@ariane_testharness), file:${SURELOG_DIR}/tests/TypeParamOverride/dut.sv, line:23:1, endln:31:10 +\_module_inst: work@ariane_testharness (work@ariane_testharness), file:${SURELOG_DIR}/tests/TypeParamOverride/dut.sv, line:23:1, endln:31:10 |vpiParent: \_design: (work@ariane_testharness) |vpiFullName:work@ariane_testharness |vpiDefName:work@ariane_testharness |uhdmallModules: -\_module: work@axi_err_slv (work@axi_err_slv), file:${SURELOG_DIR}/tests/TypeParamOverride/dut.sv, line:10:1, endln:20:10 +\_module_inst: work@axi_err_slv (work@axi_err_slv), file:${SURELOG_DIR}/tests/TypeParamOverride/dut.sv, line:10:1, endln:20:10 |vpiParent: \_design: (work@ariane_testharness) |vpiFullName:work@axi_err_slv |vpiParameter: \_type_parameter: (work@axi_err_slv.resp_t), line:11:19, endln:11:25 |vpiParent: - \_module: work@axi_err_slv (work@axi_err_slv), file:${SURELOG_DIR}/tests/TypeParamOverride/dut.sv, line:10:1, endln:20:10 + \_module_inst: work@axi_err_slv (work@axi_err_slv), file:${SURELOG_DIR}/tests/TypeParamOverride/dut.sv, line:10:1, endln:20:10 |vpiName:resp_t |vpiFullName:work@axi_err_slv.resp_t |vpiTypespec: @@ -313,13 +313,13 @@ design: (work@ariane_testharness) |vpiNet: \_logic_net: (work@axi_err_slv.err_resp), line:14:11, endln:14:19 |vpiParent: - \_module: work@axi_err_slv (work@axi_err_slv), file:${SURELOG_DIR}/tests/TypeParamOverride/dut.sv, line:10:1, endln:20:10 + \_module_inst: work@axi_err_slv (work@axi_err_slv), file:${SURELOG_DIR}/tests/TypeParamOverride/dut.sv, line:10:1, endln:20:10 |vpiName:err_resp |vpiFullName:work@axi_err_slv.err_resp |vpiProcess: \_always: , line:16:3, endln:19:6 |vpiParent: - \_module: work@axi_err_slv (work@axi_err_slv), file:${SURELOG_DIR}/tests/TypeParamOverride/dut.sv, line:10:1, endln:20:10 + \_module_inst: work@axi_err_slv (work@axi_err_slv), file:${SURELOG_DIR}/tests/TypeParamOverride/dut.sv, line:10:1, endln:20:10 |vpiStmt: \_named_begin: (work@axi_err_slv.proc_w_channel), line:16:15, endln:19:6 |vpiParent: @@ -355,21 +355,21 @@ design: (work@ariane_testharness) |vpiName:w_ready |vpiAlwaysType:2 |uhdmtopModules: -\_module: work@ariane_testharness (work@ariane_testharness), file:${SURELOG_DIR}/tests/TypeParamOverride/dut.sv, line:23:1, endln:31:10 +\_module_inst: work@ariane_testharness (work@ariane_testharness), file:${SURELOG_DIR}/tests/TypeParamOverride/dut.sv, line:23:1, endln:31:10 |vpiName:work@ariane_testharness |vpiDefName:work@ariane_testharness |vpiTop:1 |vpiTopModule:1 - |vpiModule: - \_module: work@axi_err_slv (work@ariane_testharness.i_gpio_err_slv), file:${SURELOG_DIR}/tests/TypeParamOverride/dut.sv, line:25:1, endln:28:3 + |vpiModuleInst: + \_module_inst: work@axi_err_slv (work@ariane_testharness.i_gpio_err_slv), file:${SURELOG_DIR}/tests/TypeParamOverride/dut.sv, line:25:1, endln:28:3 |vpiParent: - \_module: work@ariane_testharness (work@ariane_testharness), file:${SURELOG_DIR}/tests/TypeParamOverride/dut.sv, line:23:1, endln:31:10 + \_module_inst: work@ariane_testharness (work@ariane_testharness), file:${SURELOG_DIR}/tests/TypeParamOverride/dut.sv, line:23:1, endln:31:10 |vpiName:i_gpio_err_slv |vpiFullName:work@ariane_testharness.i_gpio_err_slv |vpiVariables: \_struct_var: (work@ariane_testharness.i_gpio_err_slv.err_resp), line:14:11, endln:14:19 |vpiParent: - \_module: work@axi_err_slv (work@ariane_testharness.i_gpio_err_slv), file:${SURELOG_DIR}/tests/TypeParamOverride/dut.sv, line:25:1, endln:28:3 + \_module_inst: work@axi_err_slv (work@ariane_testharness.i_gpio_err_slv), file:${SURELOG_DIR}/tests/TypeParamOverride/dut.sv, line:25:1, endln:28:3 |vpiTypespec: \_struct_typespec: (ariane_axi_soc::resp_slv_t), line:3:9, endln:3:15 |vpiName:err_resp @@ -378,7 +378,7 @@ design: (work@ariane_testharness) |vpiParameter: \_type_parameter: (work@ariane_testharness.i_gpio_err_slv.resp_t) |vpiParent: - \_module: work@axi_err_slv (work@ariane_testharness.i_gpio_err_slv), file:${SURELOG_DIR}/tests/TypeParamOverride/dut.sv, line:25:1, endln:28:3 + \_module_inst: work@axi_err_slv (work@ariane_testharness.i_gpio_err_slv), file:${SURELOG_DIR}/tests/TypeParamOverride/dut.sv, line:25:1, endln:28:3 |vpiName:resp_t |vpiFullName:work@ariane_testharness.i_gpio_err_slv.resp_t |vpiTypespec: @@ -387,11 +387,11 @@ design: (work@ariane_testharness) |vpiDefFile:${SURELOG_DIR}/tests/TypeParamOverride/dut.sv |vpiDefLineNo:10 |vpiInstance: - \_module: work@ariane_testharness (work@ariane_testharness), file:${SURELOG_DIR}/tests/TypeParamOverride/dut.sv, line:23:1, endln:31:10 + \_module_inst: work@ariane_testharness (work@ariane_testharness), file:${SURELOG_DIR}/tests/TypeParamOverride/dut.sv, line:23:1, endln:31:10 |vpiProcess: \_always: , line:16:3, endln:19:6 |vpiParent: - \_module: work@axi_err_slv (work@ariane_testharness.i_gpio_err_slv), file:${SURELOG_DIR}/tests/TypeParamOverride/dut.sv, line:25:1, endln:28:3 + \_module_inst: work@axi_err_slv (work@ariane_testharness.i_gpio_err_slv), file:${SURELOG_DIR}/tests/TypeParamOverride/dut.sv, line:25:1, endln:28:3 |vpiStmt: \_named_begin: (work@ariane_testharness.i_gpio_err_slv.proc_w_channel), line:16:15, endln:19:6 |vpiParent: diff --git a/tests/TypedefAlias/TypedefAlias.log b/tests/TypedefAlias/TypedefAlias.log index a9cd4c65a1..a2addcd3b5 100644 --- a/tests/TypedefAlias/TypedefAlias.log +++ b/tests/TypedefAlias/TypedefAlias.log @@ -36,7 +36,7 @@ design 1 logic_net 2 logic_typespec 9 logic_var 2 -module 3 +module_inst 3 package 6 packed_array_typespec 1 range 6 @@ -51,7 +51,7 @@ design 1 logic_net 2 logic_typespec 9 logic_var 2 -module 3 +module_inst 3 package 6 packed_array_typespec 1 range 6 @@ -201,17 +201,17 @@ design: (work@test) |vpiDefName:package2 |vpiTop:1 |uhdmallModules: -\_module: work@test (work@test), file:${SURELOG_DIR}/tests/TypedefAlias/dut.sv, line:15:1, endln:20:10 +\_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/TypedefAlias/dut.sv, line:15:1, endln:20:10 |vpiParent: \_design: (work@test) |vpiFullName:work@test |vpiTypedef: \_logic_typespec: (t_two_bits), line:16:13, endln:16:24 |vpiParent: - \_module: work@test (work@test), file:${SURELOG_DIR}/tests/TypedefAlias/dut.sv, line:15:1, endln:20:10 + \_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/TypedefAlias/dut.sv, line:15:1, endln:20:10 |vpiName:t_two_bits |vpiInstance: - \_module: work@test (work@test), file:${SURELOG_DIR}/tests/TypedefAlias/dut.sv, line:15:1, endln:20:10 + \_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/TypedefAlias/dut.sv, line:15:1, endln:20:10 |vpiRange: \_range: , line:16:19, endln:16:24 |vpiLeftRange: @@ -233,12 +233,12 @@ design: (work@test) |vpiTypedef: \_logic_typespec: (t_two_bits_copy), line:16:13, endln:16:24 |vpiParent: - \_module: work@test (work@test), file:${SURELOG_DIR}/tests/TypedefAlias/dut.sv, line:15:1, endln:20:10 + \_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/TypedefAlias/dut.sv, line:15:1, endln:20:10 |vpiName:t_two_bits_copy |vpiTypedefAlias: \_logic_typespec: (t_two_bits), line:16:13, endln:16:24 |vpiInstance: - \_module: work@test (work@test), file:${SURELOG_DIR}/tests/TypedefAlias/dut.sv, line:15:1, endln:20:10 + \_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/TypedefAlias/dut.sv, line:15:1, endln:20:10 |vpiRange: \_range: , line:16:19, endln:16:24 |vpiParent: @@ -263,24 +263,24 @@ design: (work@test) |vpiNet: \_logic_net: (work@test.kkkk), line:18:16, endln:18:20 |vpiParent: - \_module: work@test (work@test), file:${SURELOG_DIR}/tests/TypedefAlias/dut.sv, line:15:1, endln:20:10 + \_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/TypedefAlias/dut.sv, line:15:1, endln:20:10 |vpiName:kkkk |vpiFullName:work@test.kkkk |vpiNetType:36 |vpiNet: \_logic_net: (work@test.zzzz), line:19:21, endln:19:25 |vpiParent: - \_module: work@test (work@test), file:${SURELOG_DIR}/tests/TypedefAlias/dut.sv, line:15:1, endln:20:10 + \_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/TypedefAlias/dut.sv, line:15:1, endln:20:10 |vpiName:zzzz |vpiFullName:work@test.zzzz |vpiNetType:36 |uhdmtopModules: -\_module: work@test (work@test), file:${SURELOG_DIR}/tests/TypedefAlias/dut.sv, line:15:1, endln:20:10 +\_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/TypedefAlias/dut.sv, line:15:1, endln:20:10 |vpiName:work@test |vpiVariables: \_logic_var: (work@test.kkkk), line:18:16, endln:18:20 |vpiParent: - \_module: work@test (work@test), file:${SURELOG_DIR}/tests/TypedefAlias/dut.sv, line:15:1, endln:20:10 + \_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/TypedefAlias/dut.sv, line:15:1, endln:20:10 |vpiTypespec: \_logic_typespec: (t_two_bits), line:16:13, endln:16:24 |vpiName:t_two_bits @@ -310,7 +310,7 @@ design: (work@test) |vpiVariables: \_logic_var: (work@test.zzzz), line:19:21, endln:19:25 |vpiParent: - \_module: work@test (work@test), file:${SURELOG_DIR}/tests/TypedefAlias/dut.sv, line:15:1, endln:20:10 + \_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/TypedefAlias/dut.sv, line:15:1, endln:20:10 |vpiTypespec: \_logic_typespec: (t_two_bits), line:16:13, endln:16:24 |vpiName:t_two_bits diff --git a/tests/TypedefPack/TypedefPack.log b/tests/TypedefPack/TypedefPack.log index 8e4d6bb565..a3518785e8 100644 --- a/tests/TypedefPack/TypedefPack.log +++ b/tests/TypedefPack/TypedefPack.log @@ -140,7 +140,7 @@ enum_typespec 5 enum_var 1 logic_net 3 logic_typespec 8 -module 5 +module_inst 5 operation 2 package 3 port 4 @@ -158,7 +158,7 @@ enum_typespec 5 enum_var 1 logic_net 3 logic_typespec 8 -module 5 +module_inst 5 operation 3 package 3 port 6 @@ -326,7 +326,7 @@ design: (work@prim_lc_sender) |vpiDefName:lc_ctrl_pkg |vpiTop:1 |uhdmallModules: -\_module: work@prim_lc_sender (work@prim_lc_sender), file:${SURELOG_DIR}/tests/TypedefPack/dut.sv, line:10:1, endln:15:27 +\_module_inst: work@prim_lc_sender (work@prim_lc_sender), file:${SURELOG_DIR}/tests/TypedefPack/dut.sv, line:10:1, endln:15:27 |vpiParent: \_design: (work@prim_lc_sender) |vpiFullName:work@prim_lc_sender @@ -334,19 +334,19 @@ design: (work@prim_lc_sender) |vpiNet: \_logic_net: (work@prim_lc_sender.lc_en_i), line:11:16, endln:11:23 |vpiParent: - \_module: work@prim_lc_sender (work@prim_lc_sender), file:${SURELOG_DIR}/tests/TypedefPack/dut.sv, line:10:1, endln:15:27 + \_module_inst: work@prim_lc_sender (work@prim_lc_sender), file:${SURELOG_DIR}/tests/TypedefPack/dut.sv, line:10:1, endln:15:27 |vpiName:lc_en_i |vpiFullName:work@prim_lc_sender.lc_en_i |vpiNet: \_logic_net: (work@prim_lc_sender.lc_en_o), line:12:31, endln:12:38 |vpiParent: - \_module: work@prim_lc_sender (work@prim_lc_sender), file:${SURELOG_DIR}/tests/TypedefPack/dut.sv, line:10:1, endln:15:27 + \_module_inst: work@prim_lc_sender (work@prim_lc_sender), file:${SURELOG_DIR}/tests/TypedefPack/dut.sv, line:10:1, endln:15:27 |vpiName:lc_en_o |vpiFullName:work@prim_lc_sender.lc_en_o |vpiPort: \_port: (lc_en_i), line:11:16, endln:11:23 |vpiParent: - \_module: work@prim_lc_sender (work@prim_lc_sender), file:${SURELOG_DIR}/tests/TypedefPack/dut.sv, line:10:1, endln:15:27 + \_module_inst: work@prim_lc_sender (work@prim_lc_sender), file:${SURELOG_DIR}/tests/TypedefPack/dut.sv, line:10:1, endln:15:27 |vpiName:lc_en_i |vpiDirection:1 |vpiLowConn: @@ -376,7 +376,7 @@ design: (work@prim_lc_sender) |vpiPort: \_port: (lc_en_o), line:12:31, endln:12:38 |vpiParent: - \_module: work@prim_lc_sender (work@prim_lc_sender), file:${SURELOG_DIR}/tests/TypedefPack/dut.sv, line:10:1, endln:15:27 + \_module_inst: work@prim_lc_sender (work@prim_lc_sender), file:${SURELOG_DIR}/tests/TypedefPack/dut.sv, line:10:1, endln:15:27 |vpiName:lc_en_o |vpiDirection:2 |vpiLowConn: @@ -388,7 +388,7 @@ design: (work@prim_lc_sender) |vpiContAssign: \_cont_assign: , line:14:10, endln:14:50 |vpiParent: - \_module: work@prim_lc_sender (work@prim_lc_sender), file:${SURELOG_DIR}/tests/TypedefPack/dut.sv, line:10:1, endln:15:27 + \_module_inst: work@prim_lc_sender (work@prim_lc_sender), file:${SURELOG_DIR}/tests/TypedefPack/dut.sv, line:10:1, endln:15:27 |vpiRhs: \_operation: , line:14:20, endln:14:50 |vpiParent: @@ -413,12 +413,12 @@ design: (work@prim_lc_sender) |vpiActual: \_enum_var: (work@prim_lc_sender.lc_en_o), line:12:31, endln:12:38 |uhdmtopModules: -\_module: work@prim_lc_sender (work@prim_lc_sender), file:${SURELOG_DIR}/tests/TypedefPack/dut.sv, line:10:1, endln:15:27 +\_module_inst: work@prim_lc_sender (work@prim_lc_sender), file:${SURELOG_DIR}/tests/TypedefPack/dut.sv, line:10:1, endln:15:27 |vpiName:work@prim_lc_sender |vpiVariables: \_enum_var: (work@prim_lc_sender.lc_en_o), line:12:31, endln:12:38 |vpiParent: - \_module: work@prim_lc_sender (work@prim_lc_sender), file:${SURELOG_DIR}/tests/TypedefPack/dut.sv, line:10:1, endln:15:27 + \_module_inst: work@prim_lc_sender (work@prim_lc_sender), file:${SURELOG_DIR}/tests/TypedefPack/dut.sv, line:10:1, endln:15:27 |vpiTypespec: \_enum_typespec: (lc_ctrl_pkg::lc_tx_t), line:2:3, endln:5:13 |vpiName:lc_en_o @@ -429,7 +429,7 @@ design: (work@prim_lc_sender) |vpiNet: \_logic_net: (work@prim_lc_sender.lc_en_i), line:11:16, endln:11:23 |vpiParent: - \_module: work@prim_lc_sender (work@prim_lc_sender), file:${SURELOG_DIR}/tests/TypedefPack/dut.sv, line:10:1, endln:15:27 + \_module_inst: work@prim_lc_sender (work@prim_lc_sender), file:${SURELOG_DIR}/tests/TypedefPack/dut.sv, line:10:1, endln:15:27 |vpiTypespec: \_logic_typespec: , line:11:10, endln:11:15 |vpiRange: @@ -456,7 +456,7 @@ design: (work@prim_lc_sender) |vpiPort: \_port: (lc_en_i), line:11:16, endln:11:23 |vpiParent: - \_module: work@prim_lc_sender (work@prim_lc_sender), file:${SURELOG_DIR}/tests/TypedefPack/dut.sv, line:10:1, endln:15:27 + \_module_inst: work@prim_lc_sender (work@prim_lc_sender), file:${SURELOG_DIR}/tests/TypedefPack/dut.sv, line:10:1, endln:15:27 |vpiName:lc_en_i |vpiDirection:1 |vpiLowConn: @@ -490,11 +490,11 @@ design: (work@prim_lc_sender) |UINT:0 |vpiConstType:9 |vpiInstance: - \_module: work@prim_lc_sender (work@prim_lc_sender), file:${SURELOG_DIR}/tests/TypedefPack/dut.sv, line:10:1, endln:15:27 + \_module_inst: work@prim_lc_sender (work@prim_lc_sender), file:${SURELOG_DIR}/tests/TypedefPack/dut.sv, line:10:1, endln:15:27 |vpiPort: \_port: (lc_en_o), line:12:31, endln:12:38 |vpiParent: - \_module: work@prim_lc_sender (work@prim_lc_sender), file:${SURELOG_DIR}/tests/TypedefPack/dut.sv, line:10:1, endln:15:27 + \_module_inst: work@prim_lc_sender (work@prim_lc_sender), file:${SURELOG_DIR}/tests/TypedefPack/dut.sv, line:10:1, endln:15:27 |vpiName:lc_en_o |vpiDirection:2 |vpiLowConn: @@ -508,11 +508,11 @@ design: (work@prim_lc_sender) |vpiTypedef: \_enum_typespec: (lc_ctrl_pkg::lc_tx_t), line:2:3, endln:5:13 |vpiInstance: - \_module: work@prim_lc_sender (work@prim_lc_sender), file:${SURELOG_DIR}/tests/TypedefPack/dut.sv, line:10:1, endln:15:27 + \_module_inst: work@prim_lc_sender (work@prim_lc_sender), file:${SURELOG_DIR}/tests/TypedefPack/dut.sv, line:10:1, endln:15:27 |vpiContAssign: \_cont_assign: , line:14:10, endln:14:50 |vpiParent: - \_module: work@prim_lc_sender (work@prim_lc_sender), file:${SURELOG_DIR}/tests/TypedefPack/dut.sv, line:10:1, endln:15:27 + \_module_inst: work@prim_lc_sender (work@prim_lc_sender), file:${SURELOG_DIR}/tests/TypedefPack/dut.sv, line:10:1, endln:15:27 |vpiRhs: \_operation: , line:14:20, endln:14:50 |vpiParent: diff --git a/tests/TypedefRange/TypedefRange.log b/tests/TypedefRange/TypedefRange.log index 1fb8e994de..c9c0368722 100644 --- a/tests/TypedefRange/TypedefRange.log +++ b/tests/TypedefRange/TypedefRange.log @@ -30,7 +30,7 @@ Instance tree: constant 8 design 1 logic_typespec 3 -module 1 +module_inst 1 package 3 packed_array_typespec 4 range 4 diff --git a/tests/TypedefUnpacked/TypedefUnpacked.log b/tests/TypedefUnpacked/TypedefUnpacked.log index c2a0d99bbf..20b8cc5502 100644 --- a/tests/TypedefUnpacked/TypedefUnpacked.log +++ b/tests/TypedefUnpacked/TypedefUnpacked.log @@ -47,7 +47,7 @@ design 1 hier_path 3 logic_net 3 logic_typespec 6 -module 4 +module_inst 4 package 3 port 2 range 2 @@ -179,7 +179,7 @@ design: (work@dut) |vpiDefName:pkg |vpiTop:1 |uhdmallModules: -\_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/TypedefUnpacked/dut.sv, line:8:1, endln:12:10 +\_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/TypedefUnpacked/dut.sv, line:8:1, endln:12:10 |vpiParent: \_design: (work@dut) |vpiFullName:work@dut @@ -187,19 +187,19 @@ design: (work@dut) |vpiNet: \_logic_net: (work@dut.o), line:8:19, endln:8:20 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/TypedefUnpacked/dut.sv, line:8:1, endln:12:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/TypedefUnpacked/dut.sv, line:8:1, endln:12:10 |vpiName:o |vpiFullName:work@dut.o |vpiNet: \_logic_net: (work@dut.c), line:9:11, endln:9:12 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/TypedefUnpacked/dut.sv, line:8:1, endln:12:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/TypedefUnpacked/dut.sv, line:8:1, endln:12:10 |vpiName:c |vpiFullName:work@dut.c |vpiPort: \_port: (o), line:8:19, endln:8:20 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/TypedefUnpacked/dut.sv, line:8:1, endln:12:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/TypedefUnpacked/dut.sv, line:8:1, endln:12:10 |vpiName:o |vpiDirection:2 |vpiLowConn: @@ -211,7 +211,7 @@ design: (work@dut) |vpiContAssign: \_cont_assign: , line:10:11, endln:10:21 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/TypedefUnpacked/dut.sv, line:8:1, endln:12:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/TypedefUnpacked/dut.sv, line:8:1, endln:12:10 |vpiRhs: \_constant: , line:10:20, endln:10:21 |vpiParent: @@ -248,7 +248,7 @@ design: (work@dut) |vpiContAssign: \_cont_assign: , line:11:11, endln:11:21 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/TypedefUnpacked/dut.sv, line:8:1, endln:12:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/TypedefUnpacked/dut.sv, line:8:1, endln:12:10 |vpiRhs: \_hier_path: (c[1].x), line:11:15, endln:11:21 |vpiParent: @@ -281,12 +281,12 @@ design: (work@dut) |vpiActual: \_logic_net: (work@dut.o), line:8:19, endln:8:20 |uhdmtopModules: -\_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/TypedefUnpacked/dut.sv, line:8:1, endln:12:10 +\_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/TypedefUnpacked/dut.sv, line:8:1, endln:12:10 |vpiName:work@dut |vpiVariables: \_array_var: (work@dut.c), line:9:11, endln:9:12 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/TypedefUnpacked/dut.sv, line:8:1, endln:12:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/TypedefUnpacked/dut.sv, line:8:1, endln:12:10 |vpiTypespec: \_array_typespec: (pkg::b) |vpiName:c @@ -299,7 +299,7 @@ design: (work@dut) |vpiNet: \_logic_net: (work@dut.o), line:8:19, endln:8:20 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/TypedefUnpacked/dut.sv, line:8:1, endln:12:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/TypedefUnpacked/dut.sv, line:8:1, endln:12:10 |vpiTypespec: \_logic_typespec: , line:8:19, endln:8:19 |vpiName:o @@ -308,7 +308,7 @@ design: (work@dut) |vpiPort: \_port: (o), line:8:19, endln:8:20 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/TypedefUnpacked/dut.sv, line:8:1, endln:12:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/TypedefUnpacked/dut.sv, line:8:1, endln:12:10 |vpiName:o |vpiDirection:2 |vpiLowConn: diff --git a/tests/Typename/Typename.log b/tests/Typename/Typename.log index cbdb12a594..f3891f674e 100644 --- a/tests/Typename/Typename.log +++ b/tests/Typename/Typename.log @@ -381,7 +381,7 @@ int_var 4 io_decl 11 logic_net 1 logic_var 1 -module 2 +module_inst 2 package 2 ref_obj 1 sys_func_call 4 @@ -406,7 +406,7 @@ int_var 4 io_decl 22 logic_net 1 logic_var 1 -module 2 +module_inst 2 package 2 ref_obj 2 sys_func_call 8 @@ -900,7 +900,7 @@ design: (work@top) \_int_typespec: |vpiSigned:1 |uhdmallModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/Typename/dut.sv, line:1:1, endln:9:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/Typename/dut.sv, line:1:1, endln:9:10 |vpiParent: \_design: (work@top) |vpiFullName:work@top @@ -908,7 +908,7 @@ design: (work@top) |vpiProcess: \_initial: , line:3:1, endln:7:4 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/Typename/dut.sv, line:1:1, endln:9:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/Typename/dut.sv, line:1:1, endln:9:10 |vpiStmt: \_begin: (work@top), line:3:9, endln:7:4 |vpiParent: @@ -981,7 +981,7 @@ design: (work@top) |vpiName:$typename |vpiName:$display |uhdmtopModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/Typename/dut.sv, line:1:1, endln:9:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/Typename/dut.sv, line:1:1, endln:9:10 |vpiName:work@top |vpiDefName:work@top |vpiTop:1 @@ -993,7 +993,7 @@ design: (work@top) |vpiProcess: \_initial: , line:3:1, endln:7:4 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/Typename/dut.sv, line:1:1, endln:9:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/Typename/dut.sv, line:1:1, endln:9:10 |vpiStmt: \_begin: (work@top), line:3:9, endln:7:4 |vpiParent: diff --git a/tests/TypespecExpr/TypespecExpr.log b/tests/TypespecExpr/TypespecExpr.log index 6969dcf305..fac034a8d6 100644 --- a/tests/TypespecExpr/TypespecExpr.log +++ b/tests/TypespecExpr/TypespecExpr.log @@ -208,7 +208,7 @@ design 1 logic_net 3 logic_typespec 17 logic_var 1 -module 9 +module_inst 9 operation 10 param_assign 4 parameter 6 @@ -229,7 +229,7 @@ design 1 logic_net 3 logic_typespec 17 logic_var 1 -module 9 +module_inst 9 operation 10 param_assign 4 parameter 6 @@ -254,14 +254,14 @@ design: (work@Mod2) |vpiElaborated:1 |vpiName:work@Mod2 |uhdmallModules: -\_module: work@Mod1 (work@Mod1), file:${SURELOG_DIR}/tests/TypespecExpr/dut.sv, line:1:1, endln:3:10 +\_module_inst: work@Mod1 (work@Mod1), file:${SURELOG_DIR}/tests/TypespecExpr/dut.sv, line:1:1, endln:3:10 |vpiParent: \_design: (work@Mod2) |vpiFullName:work@Mod1 |vpiParameter: \_parameter: (work@Mod1.PARAM), line:1:38, endln:1:43 |vpiParent: - \_module: work@Mod1 (work@Mod1), file:${SURELOG_DIR}/tests/TypespecExpr/dut.sv, line:1:1, endln:3:10 + \_module_inst: work@Mod1 (work@Mod1), file:${SURELOG_DIR}/tests/TypespecExpr/dut.sv, line:1:1, endln:3:10 |BIN:0 |vpiTypespec: \_logic_typespec: , line:1:25, endln:1:37 @@ -290,7 +290,7 @@ design: (work@Mod2) |vpiParamAssign: \_param_assign: , line:1:38, endln:1:48 |vpiParent: - \_module: work@Mod1 (work@Mod1), file:${SURELOG_DIR}/tests/TypespecExpr/dut.sv, line:1:1, endln:3:10 + \_module_inst: work@Mod1 (work@Mod1), file:${SURELOG_DIR}/tests/TypespecExpr/dut.sv, line:1:1, endln:3:10 |vpiRhs: \_constant: , line:1:46, endln:1:48 |vpiDecompile:'0 @@ -305,14 +305,14 @@ design: (work@Mod2) |vpiNet: \_logic_net: (work@Mod1.x), line:1:71, endln:1:72 |vpiParent: - \_module: work@Mod1 (work@Mod1), file:${SURELOG_DIR}/tests/TypespecExpr/dut.sv, line:1:1, endln:3:10 + \_module_inst: work@Mod1 (work@Mod1), file:${SURELOG_DIR}/tests/TypespecExpr/dut.sv, line:1:1, endln:3:10 |vpiName:x |vpiFullName:work@Mod1.x |vpiNetType:36 |vpiPort: \_port: (x), line:1:71, endln:1:72 |vpiParent: - \_module: work@Mod1 (work@Mod1), file:${SURELOG_DIR}/tests/TypespecExpr/dut.sv, line:1:1, endln:3:10 + \_module_inst: work@Mod1 (work@Mod1), file:${SURELOG_DIR}/tests/TypespecExpr/dut.sv, line:1:1, endln:3:10 |vpiName:x |vpiDirection:2 |vpiLowConn: @@ -342,7 +342,7 @@ design: (work@Mod2) |vpiContAssign: \_cont_assign: , line:2:11, endln:2:20 |vpiParent: - \_module: work@Mod1 (work@Mod1), file:${SURELOG_DIR}/tests/TypespecExpr/dut.sv, line:1:1, endln:3:10 + \_module_inst: work@Mod1 (work@Mod1), file:${SURELOG_DIR}/tests/TypespecExpr/dut.sv, line:1:1, endln:3:10 |vpiRhs: \_ref_obj: (work@Mod1.PARAM), line:2:15, endln:2:20 |vpiParent: @@ -358,21 +358,21 @@ design: (work@Mod2) |vpiActual: \_logic_net: (work@Mod2.mod1.x), line:1:71, endln:1:72 |uhdmallModules: -\_module: work@Mod2 (work@Mod2), file:${SURELOG_DIR}/tests/TypespecExpr/dut.sv, line:5:1, endln:10:10 +\_module_inst: work@Mod2 (work@Mod2), file:${SURELOG_DIR}/tests/TypespecExpr/dut.sv, line:5:1, endln:10:10 |vpiParent: \_design: (work@Mod2) |vpiFullName:work@Mod2 |vpiParameter: \_parameter: (work@Mod2.STRUCT), line:7:21, endln:7:27 |vpiParent: - \_module: work@Mod2 (work@Mod2), file:${SURELOG_DIR}/tests/TypespecExpr/dut.sv, line:5:1, endln:10:10 + \_module_inst: work@Mod2 (work@Mod2), file:${SURELOG_DIR}/tests/TypespecExpr/dut.sv, line:5:1, endln:10:10 |vpiTypespec: \_struct_typespec: (Struct), line:6:12, endln:6:18 |vpiParent: - \_module: work@Mod2 (work@Mod2), file:${SURELOG_DIR}/tests/TypespecExpr/dut.sv, line:5:1, endln:10:10 + \_module_inst: work@Mod2 (work@Mod2), file:${SURELOG_DIR}/tests/TypespecExpr/dut.sv, line:5:1, endln:10:10 |vpiName:Struct |vpiInstance: - \_module: work@Mod2 (work@Mod2), file:${SURELOG_DIR}/tests/TypespecExpr/dut.sv, line:5:1, endln:10:10 + \_module_inst: work@Mod2 (work@Mod2), file:${SURELOG_DIR}/tests/TypespecExpr/dut.sv, line:5:1, endln:10:10 |vpiPacked:1 |vpiTypespecMember: \_typespec_member: (x), line:6:40, endln:6:41 @@ -413,7 +413,7 @@ design: (work@Mod2) |vpiParamAssign: \_param_assign: , line:7:21, endln:7:40 |vpiParent: - \_module: work@Mod2 (work@Mod2), file:${SURELOG_DIR}/tests/TypespecExpr/dut.sv, line:5:1, endln:10:10 + \_module_inst: work@Mod2 (work@Mod2), file:${SURELOG_DIR}/tests/TypespecExpr/dut.sv, line:5:1, endln:10:10 |vpiRhs: \_operation: , line:7:30, endln:7:40 |vpiOpType:75 @@ -436,17 +436,17 @@ design: (work@Mod2) |vpiNet: \_logic_net: (work@Mod2.x), line:8:16, endln:8:17 |vpiParent: - \_module: work@Mod2 (work@Mod2), file:${SURELOG_DIR}/tests/TypespecExpr/dut.sv, line:5:1, endln:10:10 + \_module_inst: work@Mod2 (work@Mod2), file:${SURELOG_DIR}/tests/TypespecExpr/dut.sv, line:5:1, endln:10:10 |vpiName:x |vpiFullName:work@Mod2.x |vpiNetType:36 |uhdmtopModules: -\_module: work@Mod2 (work@Mod2), file:${SURELOG_DIR}/tests/TypespecExpr/dut.sv, line:5:1, endln:10:10 +\_module_inst: work@Mod2 (work@Mod2), file:${SURELOG_DIR}/tests/TypespecExpr/dut.sv, line:5:1, endln:10:10 |vpiName:work@Mod2 |vpiVariables: \_logic_var: (work@Mod2.x), line:8:16, endln:8:17 |vpiParent: - \_module: work@Mod2 (work@Mod2), file:${SURELOG_DIR}/tests/TypespecExpr/dut.sv, line:5:1, endln:10:10 + \_module_inst: work@Mod2 (work@Mod2), file:${SURELOG_DIR}/tests/TypespecExpr/dut.sv, line:5:1, endln:10:10 |vpiTypespec: \_logic_typespec: , line:8:4, endln:8:15 |vpiRange: @@ -491,14 +491,14 @@ design: (work@Mod2) |vpiParameter: \_parameter: (work@Mod2.STRUCT), line:7:21, endln:7:27 |vpiParent: - \_module: work@Mod2 (work@Mod2), file:${SURELOG_DIR}/tests/TypespecExpr/dut.sv, line:5:1, endln:10:10 + \_module_inst: work@Mod2 (work@Mod2), file:${SURELOG_DIR}/tests/TypespecExpr/dut.sv, line:5:1, endln:10:10 |vpiTypespec: \_struct_typespec: (Struct), line:6:12, endln:6:18 |vpiParent: \_parameter: (work@Mod2.STRUCT), line:7:21, endln:7:27 |vpiName:Struct |vpiInstance: - \_module: work@Mod2 (work@Mod2), file:${SURELOG_DIR}/tests/TypespecExpr/dut.sv, line:5:1, endln:10:10 + \_module_inst: work@Mod2 (work@Mod2), file:${SURELOG_DIR}/tests/TypespecExpr/dut.sv, line:5:1, endln:10:10 |vpiPacked:1 |vpiTypespecMember: \_typespec_member: (x), line:6:40, endln:6:41 @@ -539,7 +539,7 @@ design: (work@Mod2) |vpiParamAssign: \_param_assign: , line:7:21, endln:7:40 |vpiParent: - \_module: work@Mod2 (work@Mod2), file:${SURELOG_DIR}/tests/TypespecExpr/dut.sv, line:5:1, endln:10:10 + \_module_inst: work@Mod2 (work@Mod2), file:${SURELOG_DIR}/tests/TypespecExpr/dut.sv, line:5:1, endln:10:10 |vpiRhs: \_operation: , line:7:30, endln:7:40 |vpiParent: @@ -600,16 +600,16 @@ design: (work@Mod2) |vpiDefName:work@Mod2 |vpiTop:1 |vpiTopModule:1 - |vpiModule: - \_module: work@Mod1 (work@Mod2.mod1), file:${SURELOG_DIR}/tests/TypespecExpr/dut.sv, line:9:4, endln:9:39 + |vpiModuleInst: + \_module_inst: work@Mod1 (work@Mod2.mod1), file:${SURELOG_DIR}/tests/TypespecExpr/dut.sv, line:9:4, endln:9:39 |vpiParent: - \_module: work@Mod2 (work@Mod2), file:${SURELOG_DIR}/tests/TypespecExpr/dut.sv, line:5:1, endln:10:10 + \_module_inst: work@Mod2 (work@Mod2), file:${SURELOG_DIR}/tests/TypespecExpr/dut.sv, line:5:1, endln:10:10 |vpiName:mod1 |vpiFullName:work@Mod2.mod1 |vpiParameter: \_parameter: (work@Mod2.mod1.PARAM), line:1:38, endln:1:43 |vpiParent: - \_module: work@Mod1 (work@Mod2.mod1), file:${SURELOG_DIR}/tests/TypespecExpr/dut.sv, line:9:4, endln:9:39 + \_module_inst: work@Mod1 (work@Mod2.mod1), file:${SURELOG_DIR}/tests/TypespecExpr/dut.sv, line:9:4, endln:9:39 |BIN:0 |vpiTypespec: \_logic_typespec: , line:1:25, endln:1:37 @@ -640,7 +640,7 @@ design: (work@Mod2) |vpiParamAssign: \_param_assign: , line:1:38, endln:1:48 |vpiParent: - \_module: work@Mod1 (work@Mod2.mod1), file:${SURELOG_DIR}/tests/TypespecExpr/dut.sv, line:9:4, endln:9:39 + \_module_inst: work@Mod1 (work@Mod2.mod1), file:${SURELOG_DIR}/tests/TypespecExpr/dut.sv, line:9:4, endln:9:39 |vpiOverriden:1 |vpiRhs: \_constant: , line:9:18, endln:9:24 @@ -655,7 +655,7 @@ design: (work@Mod2) |vpiNet: \_logic_net: (work@Mod2.mod1.x), line:1:71, endln:1:72 |vpiParent: - \_module: work@Mod1 (work@Mod2.mod1), file:${SURELOG_DIR}/tests/TypespecExpr/dut.sv, line:9:4, endln:9:39 + \_module_inst: work@Mod1 (work@Mod2.mod1), file:${SURELOG_DIR}/tests/TypespecExpr/dut.sv, line:9:4, endln:9:39 |vpiTypespec: \_logic_typespec: , line:1:58, endln:1:70 |vpiRange: @@ -680,11 +680,11 @@ design: (work@Mod2) |vpiFullName:work@Mod2.mod1.x |vpiNetType:36 |vpiInstance: - \_module: work@Mod2 (work@Mod2), file:${SURELOG_DIR}/tests/TypespecExpr/dut.sv, line:5:1, endln:10:10 + \_module_inst: work@Mod2 (work@Mod2), file:${SURELOG_DIR}/tests/TypespecExpr/dut.sv, line:5:1, endln:10:10 |vpiPort: \_port: (x), line:1:71, endln:1:72 |vpiParent: - \_module: work@Mod1 (work@Mod2.mod1), file:${SURELOG_DIR}/tests/TypespecExpr/dut.sv, line:9:4, endln:9:39 + \_module_inst: work@Mod1 (work@Mod2.mod1), file:${SURELOG_DIR}/tests/TypespecExpr/dut.sv, line:9:4, endln:9:39 |vpiName:x |vpiDirection:2 |vpiHighConn: @@ -726,11 +726,11 @@ design: (work@Mod2) |UINT:0 |vpiConstType:9 |vpiInstance: - \_module: work@Mod1 (work@Mod2.mod1), file:${SURELOG_DIR}/tests/TypespecExpr/dut.sv, line:9:4, endln:9:39 + \_module_inst: work@Mod1 (work@Mod2.mod1), file:${SURELOG_DIR}/tests/TypespecExpr/dut.sv, line:9:4, endln:9:39 |vpiContAssign: \_cont_assign: , line:2:11, endln:2:20 |vpiParent: - \_module: work@Mod1 (work@Mod2.mod1), file:${SURELOG_DIR}/tests/TypespecExpr/dut.sv, line:9:4, endln:9:39 + \_module_inst: work@Mod1 (work@Mod2.mod1), file:${SURELOG_DIR}/tests/TypespecExpr/dut.sv, line:9:4, endln:9:39 |vpiRhs: \_ref_obj: (work@Mod2.mod1.PARAM), line:2:15, endln:2:20 |vpiParent: diff --git a/tests/TypespecMask/TypespecMask.log b/tests/TypespecMask/TypespecMask.log index a7998e343a..78a8895943 100644 --- a/tests/TypespecMask/TypespecMask.log +++ b/tests/TypespecMask/TypespecMask.log @@ -119,7 +119,7 @@ constant 28 design 1 int_typespec 4 logic_typespec 4 -module 5 +module_inst 5 operation 4 param_assign 6 parameter 6 @@ -133,7 +133,7 @@ constant 28 design 1 int_typespec 4 logic_typespec 4 -module 5 +module_inst 5 operation 4 param_assign 6 parameter 6 @@ -153,14 +153,14 @@ design: (work@flash_ctrl_erase) |vpiElaborated:1 |vpiName:work@flash_ctrl_erase |uhdmallModules: -\_module: work@flash_ctrl_erase (work@flash_ctrl_erase), file:${SURELOG_DIR}/tests/TypespecMask/dut.sv, line:1:1, endln:8:10 +\_module_inst: work@flash_ctrl_erase (work@flash_ctrl_erase), file:${SURELOG_DIR}/tests/TypespecMask/dut.sv, line:1:1, endln:8:10 |vpiParent: \_design: (work@flash_ctrl_erase) |vpiFullName:work@flash_ctrl_erase |vpiParameter: \_parameter: (work@flash_ctrl_erase.BankAddrMask), line:3:26, endln:3:38 |vpiParent: - \_module: work@flash_ctrl_erase (work@flash_ctrl_erase), file:${SURELOG_DIR}/tests/TypespecMask/dut.sv, line:1:1, endln:8:10 + \_module_inst: work@flash_ctrl_erase (work@flash_ctrl_erase), file:${SURELOG_DIR}/tests/TypespecMask/dut.sv, line:1:1, endln:8:10 |vpiTypespec: \_logic_typespec: , line:3:14, endln:3:25 |vpiParent: @@ -189,7 +189,7 @@ design: (work@flash_ctrl_erase) |vpiParameter: \_parameter: (work@flash_ctrl_erase.NMioPads), line:5:17, endln:5:25 |vpiParent: - \_module: work@flash_ctrl_erase (work@flash_ctrl_erase), file:${SURELOG_DIR}/tests/TypespecMask/dut.sv, line:1:1, endln:8:10 + \_module_inst: work@flash_ctrl_erase (work@flash_ctrl_erase), file:${SURELOG_DIR}/tests/TypespecMask/dut.sv, line:1:1, endln:8:10 |UINT:8 |vpiTypespec: \_int_typespec: , line:5:13, endln:5:16 @@ -202,7 +202,7 @@ design: (work@flash_ctrl_erase) |vpiParameter: \_parameter: (work@flash_ctrl_erase.ConnectDioIn), line:6:36, endln:6:48 |vpiParent: - \_module: work@flash_ctrl_erase (work@flash_ctrl_erase), file:${SURELOG_DIR}/tests/TypespecMask/dut.sv, line:1:1, endln:8:10 + \_module_inst: work@flash_ctrl_erase (work@flash_ctrl_erase), file:${SURELOG_DIR}/tests/TypespecMask/dut.sv, line:1:1, endln:8:10 |BIN:11110000 |vpiTypespec: \_logic_typespec: , line:6:13, endln:6:35 @@ -243,7 +243,7 @@ design: (work@flash_ctrl_erase) |vpiParamAssign: \_param_assign: , line:3:26, endln:3:46 |vpiParent: - \_module: work@flash_ctrl_erase (work@flash_ctrl_erase), file:${SURELOG_DIR}/tests/TypespecMask/dut.sv, line:1:1, endln:8:10 + \_module_inst: work@flash_ctrl_erase (work@flash_ctrl_erase), file:${SURELOG_DIR}/tests/TypespecMask/dut.sv, line:1:1, endln:8:10 |vpiRhs: \_operation: , line:3:41, endln:3:46 |vpiOpType:4 @@ -258,7 +258,7 @@ design: (work@flash_ctrl_erase) |vpiParamAssign: \_param_assign: , line:5:17, endln:5:29 |vpiParent: - \_module: work@flash_ctrl_erase (work@flash_ctrl_erase), file:${SURELOG_DIR}/tests/TypespecMask/dut.sv, line:1:1, endln:8:10 + \_module_inst: work@flash_ctrl_erase (work@flash_ctrl_erase), file:${SURELOG_DIR}/tests/TypespecMask/dut.sv, line:1:1, endln:8:10 |vpiRhs: \_constant: , line:5:28, endln:5:29 |vpiDecompile:8 @@ -272,7 +272,7 @@ design: (work@flash_ctrl_erase) |vpiParamAssign: \_param_assign: , line:6:36, endln:6:62 |vpiParent: - \_module: work@flash_ctrl_erase (work@flash_ctrl_erase), file:${SURELOG_DIR}/tests/TypespecMask/dut.sv, line:1:1, endln:8:10 + \_module_inst: work@flash_ctrl_erase (work@flash_ctrl_erase), file:${SURELOG_DIR}/tests/TypespecMask/dut.sv, line:1:1, endln:8:10 |vpiRhs: \_constant: , line:6:51, endln:6:62 |vpiDecompile:8'b11110000 @@ -285,12 +285,12 @@ design: (work@flash_ctrl_erase) \_parameter: (work@flash_ctrl_erase.ConnectDioIn), line:6:36, endln:6:48 |vpiDefName:work@flash_ctrl_erase |uhdmtopModules: -\_module: work@flash_ctrl_erase (work@flash_ctrl_erase), file:${SURELOG_DIR}/tests/TypespecMask/dut.sv, line:1:1, endln:8:10 +\_module_inst: work@flash_ctrl_erase (work@flash_ctrl_erase), file:${SURELOG_DIR}/tests/TypespecMask/dut.sv, line:1:1, endln:8:10 |vpiName:work@flash_ctrl_erase |vpiParameter: \_parameter: (work@flash_ctrl_erase.BankAddrMask), line:3:26, endln:3:38 |vpiParent: - \_module: work@flash_ctrl_erase (work@flash_ctrl_erase), file:${SURELOG_DIR}/tests/TypespecMask/dut.sv, line:1:1, endln:8:10 + \_module_inst: work@flash_ctrl_erase (work@flash_ctrl_erase), file:${SURELOG_DIR}/tests/TypespecMask/dut.sv, line:1:1, endln:8:10 |vpiTypespec: \_logic_typespec: , line:3:14, endln:3:25 |vpiParent: @@ -321,7 +321,7 @@ design: (work@flash_ctrl_erase) |vpiParameter: \_parameter: (work@flash_ctrl_erase.NMioPads), line:5:17, endln:5:25 |vpiParent: - \_module: work@flash_ctrl_erase (work@flash_ctrl_erase), file:${SURELOG_DIR}/tests/TypespecMask/dut.sv, line:1:1, endln:8:10 + \_module_inst: work@flash_ctrl_erase (work@flash_ctrl_erase), file:${SURELOG_DIR}/tests/TypespecMask/dut.sv, line:1:1, endln:8:10 |UINT:8 |vpiTypespec: \_int_typespec: , line:5:13, endln:5:16 @@ -334,7 +334,7 @@ design: (work@flash_ctrl_erase) |vpiParameter: \_parameter: (work@flash_ctrl_erase.ConnectDioIn), line:6:36, endln:6:48 |vpiParent: - \_module: work@flash_ctrl_erase (work@flash_ctrl_erase), file:${SURELOG_DIR}/tests/TypespecMask/dut.sv, line:1:1, endln:8:10 + \_module_inst: work@flash_ctrl_erase (work@flash_ctrl_erase), file:${SURELOG_DIR}/tests/TypespecMask/dut.sv, line:1:1, endln:8:10 |BIN:11110000 |vpiTypespec: \_logic_typespec: , line:6:13, endln:6:35 @@ -378,7 +378,7 @@ design: (work@flash_ctrl_erase) |vpiParamAssign: \_param_assign: , line:3:26, endln:3:46 |vpiParent: - \_module: work@flash_ctrl_erase (work@flash_ctrl_erase), file:${SURELOG_DIR}/tests/TypespecMask/dut.sv, line:1:1, endln:8:10 + \_module_inst: work@flash_ctrl_erase (work@flash_ctrl_erase), file:${SURELOG_DIR}/tests/TypespecMask/dut.sv, line:1:1, endln:8:10 |vpiRhs: \_constant: , line:3:41, endln:3:46 |vpiDecompile:262128 @@ -392,7 +392,7 @@ design: (work@flash_ctrl_erase) |vpiParamAssign: \_param_assign: , line:5:17, endln:5:29 |vpiParent: - \_module: work@flash_ctrl_erase (work@flash_ctrl_erase), file:${SURELOG_DIR}/tests/TypespecMask/dut.sv, line:1:1, endln:8:10 + \_module_inst: work@flash_ctrl_erase (work@flash_ctrl_erase), file:${SURELOG_DIR}/tests/TypespecMask/dut.sv, line:1:1, endln:8:10 |vpiRhs: \_constant: , line:5:28, endln:5:29 |vpiDecompile:8 @@ -406,7 +406,7 @@ design: (work@flash_ctrl_erase) |vpiParamAssign: \_param_assign: , line:6:36, endln:6:62 |vpiParent: - \_module: work@flash_ctrl_erase (work@flash_ctrl_erase), file:${SURELOG_DIR}/tests/TypespecMask/dut.sv, line:1:1, endln:8:10 + \_module_inst: work@flash_ctrl_erase (work@flash_ctrl_erase), file:${SURELOG_DIR}/tests/TypespecMask/dut.sv, line:1:1, endln:8:10 |vpiRhs: \_constant: , line:6:51, endln:6:62 |vpiDecompile:8'b11110000 diff --git a/tests/Udp/Udp.log b/tests/Udp/Udp.log index a9531b45ee..2b859ddb87 100644 --- a/tests/Udp/Udp.log +++ b/tests/Udp/Udp.log @@ -968,7 +968,7 @@ io_decl 23 logic_net 21 logic_typespec 2 logic_var 1 -module 2 +module_inst 2 package 2 ref_obj 14 sys_func_call 2 @@ -1001,7 +1001,7 @@ io_decl 34 logic_net 21 logic_typespec 2 logic_var 1 -module 2 +module_inst 2 package 2 ref_obj 27 sys_func_call 4 @@ -1805,7 +1805,7 @@ design: (work@udp_body_tb) |vpiName:q |vpiFullName:work@udp_sequential_initial.q |uhdmallModules: -\_module: work@udp_body_tb (work@udp_body_tb), file:${SURELOG_DIR}/tests/Udp/dut.sv, line:84:1, endln:106:10 +\_module_inst: work@udp_body_tb (work@udp_body_tb), file:${SURELOG_DIR}/tests/Udp/dut.sv, line:84:1, endln:106:10 |vpiParent: \_design: (work@udp_body_tb) |vpiFullName:work@udp_body_tb @@ -1813,28 +1813,28 @@ design: (work@udp_body_tb) |vpiNet: \_logic_net: (work@udp_body_tb.b), line:86:5, endln:86:6 |vpiParent: - \_module: work@udp_body_tb (work@udp_body_tb), file:${SURELOG_DIR}/tests/Udp/dut.sv, line:84:1, endln:106:10 + \_module_inst: work@udp_body_tb (work@udp_body_tb), file:${SURELOG_DIR}/tests/Udp/dut.sv, line:84:1, endln:106:10 |vpiName:b |vpiFullName:work@udp_body_tb.b |vpiNetType:48 |vpiNet: \_logic_net: (work@udp_body_tb.c), line:86:7, endln:86:8 |vpiParent: - \_module: work@udp_body_tb (work@udp_body_tb), file:${SURELOG_DIR}/tests/Udp/dut.sv, line:84:1, endln:106:10 + \_module_inst: work@udp_body_tb (work@udp_body_tb), file:${SURELOG_DIR}/tests/Udp/dut.sv, line:84:1, endln:106:10 |vpiName:c |vpiFullName:work@udp_body_tb.c |vpiNetType:48 |vpiNet: \_logic_net: (work@udp_body_tb.a), line:87:6, endln:87:7 |vpiParent: - \_module: work@udp_body_tb (work@udp_body_tb), file:${SURELOG_DIR}/tests/Udp/dut.sv, line:84:1, endln:106:10 + \_module_inst: work@udp_body_tb (work@udp_body_tb), file:${SURELOG_DIR}/tests/Udp/dut.sv, line:84:1, endln:106:10 |vpiName:a |vpiFullName:work@udp_body_tb.a |vpiNetType:1 |vpiProcess: \_initial: , line:91:1, endln:104:4 |vpiParent: - \_module: work@udp_body_tb (work@udp_body_tb), file:${SURELOG_DIR}/tests/Udp/dut.sv, line:84:1, endln:106:10 + \_module_inst: work@udp_body_tb (work@udp_body_tb), file:${SURELOG_DIR}/tests/Udp/dut.sv, line:84:1, endln:106:10 |vpiStmt: \_begin: (work@udp_body_tb), line:91:9, endln:104:4 |vpiParent: @@ -2148,14 +2148,14 @@ design: (work@udp_body_tb) \_delay_control: , line:103:3, endln:103:5 |vpiName:$finish |uhdmtopModules: -\_module: work@udp_body_tb (work@udp_body_tb), file:${SURELOG_DIR}/tests/Udp/dut.sv, line:84:1, endln:106:10 +\_module_inst: work@udp_body_tb (work@udp_body_tb), file:${SURELOG_DIR}/tests/Udp/dut.sv, line:84:1, endln:106:10 |vpiName:work@udp_body_tb |vpiDefName:work@udp_body_tb |vpiTop:1 |vpiNet: \_logic_net: (work@udp_body_tb.b), line:86:5, endln:86:6 |vpiParent: - \_module: work@udp_body_tb (work@udp_body_tb), file:${SURELOG_DIR}/tests/Udp/dut.sv, line:84:1, endln:106:10 + \_module_inst: work@udp_body_tb (work@udp_body_tb), file:${SURELOG_DIR}/tests/Udp/dut.sv, line:84:1, endln:106:10 |vpiTypespec: \_logic_typespec: , line:86:1, endln:86:4 |vpiName:b @@ -2164,7 +2164,7 @@ design: (work@udp_body_tb) |vpiNet: \_logic_net: (work@udp_body_tb.c), line:86:7, endln:86:8 |vpiParent: - \_module: work@udp_body_tb (work@udp_body_tb), file:${SURELOG_DIR}/tests/Udp/dut.sv, line:84:1, endln:106:10 + \_module_inst: work@udp_body_tb (work@udp_body_tb), file:${SURELOG_DIR}/tests/Udp/dut.sv, line:84:1, endln:106:10 |vpiTypespec: \_logic_typespec: , line:86:1, endln:86:4 |vpiName:c @@ -2173,7 +2173,7 @@ design: (work@udp_body_tb) |vpiNet: \_logic_net: (work@udp_body_tb.a), line:87:6, endln:87:7 |vpiParent: - \_module: work@udp_body_tb (work@udp_body_tb), file:${SURELOG_DIR}/tests/Udp/dut.sv, line:84:1, endln:106:10 + \_module_inst: work@udp_body_tb (work@udp_body_tb), file:${SURELOG_DIR}/tests/Udp/dut.sv, line:84:1, endln:106:10 |vpiTypespec: \_logic_typespec: , line:87:1, endln:87:5 |vpiName:a @@ -2183,7 +2183,7 @@ design: (work@udp_body_tb) |vpiProcess: \_initial: , line:91:1, endln:104:4 |vpiParent: - \_module: work@udp_body_tb (work@udp_body_tb), file:${SURELOG_DIR}/tests/Udp/dut.sv, line:84:1, endln:106:10 + \_module_inst: work@udp_body_tb (work@udp_body_tb), file:${SURELOG_DIR}/tests/Udp/dut.sv, line:84:1, endln:106:10 |vpiStmt: \_begin: (work@udp_body_tb), line:91:9, endln:104:4 |vpiParent: @@ -2433,7 +2433,7 @@ design: (work@udp_body_tb) |vpiPrimitive: \_udp: work@udp_body (work@udp_body_tb.udp), file:${SURELOG_DIR}/tests/Udp/dut.sv, line:89:1, endln:89:22 |vpiParent: - \_module: work@udp_body_tb (work@udp_body_tb), file:${SURELOG_DIR}/tests/Udp/dut.sv, line:84:1, endln:106:10 + \_module_inst: work@udp_body_tb (work@udp_body_tb), file:${SURELOG_DIR}/tests/Udp/dut.sv, line:84:1, endln:106:10 |vpiDefName:work@udp_body |vpiName:udp |vpiFullName:work@udp_body_tb.udp diff --git a/tests/UnaryPlus/UnaryPlus.log b/tests/UnaryPlus/UnaryPlus.log index 59234bd5e2..80e1e1c69c 100644 --- a/tests/UnaryPlus/UnaryPlus.log +++ b/tests/UnaryPlus/UnaryPlus.log @@ -79,7 +79,7 @@ design 1 gen_scope 16 gen_scope_array 16 int_typespec 8 -module 3 +module_inst 3 operation 9 parameter 8 === UHDM Object Stats End === @@ -91,7 +91,7 @@ design 1 gen_scope 24 gen_scope_array 24 int_typespec 8 -module 3 +module_inst 3 operation 9 parameter 8 === UHDM Object Stats End === @@ -108,13 +108,13 @@ design: (work@alert_handler_reg_wrap) |vpiElaborated:1 |vpiName:work@alert_handler_reg_wrap |uhdmallModules: -\_module: work@alert_handler_reg_wrap (work@alert_handler_reg_wrap), file:${SURELOG_DIR}/tests/UnaryPlus/dut.sv, line:1:1, endln:4:10 +\_module_inst: work@alert_handler_reg_wrap (work@alert_handler_reg_wrap), file:${SURELOG_DIR}/tests/UnaryPlus/dut.sv, line:1:1, endln:4:10 |vpiParent: \_design: (work@alert_handler_reg_wrap) |vpiFullName:work@alert_handler_reg_wrap |vpiDefName:work@alert_handler_reg_wrap |uhdmtopModules: -\_module: work@alert_handler_reg_wrap (work@alert_handler_reg_wrap), file:${SURELOG_DIR}/tests/UnaryPlus/dut.sv, line:1:1, endln:4:10 +\_module_inst: work@alert_handler_reg_wrap (work@alert_handler_reg_wrap), file:${SURELOG_DIR}/tests/UnaryPlus/dut.sv, line:1:1, endln:4:10 |vpiName:work@alert_handler_reg_wrap |vpiDefName:work@alert_handler_reg_wrap |vpiTop:1 @@ -122,7 +122,7 @@ design: (work@alert_handler_reg_wrap) |vpiGenScopeArray: \_gen_scope_array: (work@alert_handler_reg_wrap.g_dmem_intg_check[0]), line:2:48, endln:3:6 |vpiParent: - \_module: work@alert_handler_reg_wrap (work@alert_handler_reg_wrap), file:${SURELOG_DIR}/tests/UnaryPlus/dut.sv, line:1:1, endln:4:10 + \_module_inst: work@alert_handler_reg_wrap (work@alert_handler_reg_wrap), file:${SURELOG_DIR}/tests/UnaryPlus/dut.sv, line:1:1, endln:4:10 |vpiName:g_dmem_intg_check[0] |vpiFullName:work@alert_handler_reg_wrap.g_dmem_intg_check[0] |vpiGenScope: @@ -143,7 +143,7 @@ design: (work@alert_handler_reg_wrap) |vpiGenScopeArray: \_gen_scope_array: (work@alert_handler_reg_wrap.g_dmem_intg_check[1]), line:2:48, endln:3:6 |vpiParent: - \_module: work@alert_handler_reg_wrap (work@alert_handler_reg_wrap), file:${SURELOG_DIR}/tests/UnaryPlus/dut.sv, line:1:1, endln:4:10 + \_module_inst: work@alert_handler_reg_wrap (work@alert_handler_reg_wrap), file:${SURELOG_DIR}/tests/UnaryPlus/dut.sv, line:1:1, endln:4:10 |vpiName:g_dmem_intg_check[1] |vpiFullName:work@alert_handler_reg_wrap.g_dmem_intg_check[1] |vpiGenScope: @@ -164,7 +164,7 @@ design: (work@alert_handler_reg_wrap) |vpiGenScopeArray: \_gen_scope_array: (work@alert_handler_reg_wrap.g_dmem_intg_check[2]), line:2:48, endln:3:6 |vpiParent: - \_module: work@alert_handler_reg_wrap (work@alert_handler_reg_wrap), file:${SURELOG_DIR}/tests/UnaryPlus/dut.sv, line:1:1, endln:4:10 + \_module_inst: work@alert_handler_reg_wrap (work@alert_handler_reg_wrap), file:${SURELOG_DIR}/tests/UnaryPlus/dut.sv, line:1:1, endln:4:10 |vpiName:g_dmem_intg_check[2] |vpiFullName:work@alert_handler_reg_wrap.g_dmem_intg_check[2] |vpiGenScope: @@ -185,7 +185,7 @@ design: (work@alert_handler_reg_wrap) |vpiGenScopeArray: \_gen_scope_array: (work@alert_handler_reg_wrap.g_dmem_intg_check[3]), line:2:48, endln:3:6 |vpiParent: - \_module: work@alert_handler_reg_wrap (work@alert_handler_reg_wrap), file:${SURELOG_DIR}/tests/UnaryPlus/dut.sv, line:1:1, endln:4:10 + \_module_inst: work@alert_handler_reg_wrap (work@alert_handler_reg_wrap), file:${SURELOG_DIR}/tests/UnaryPlus/dut.sv, line:1:1, endln:4:10 |vpiName:g_dmem_intg_check[3] |vpiFullName:work@alert_handler_reg_wrap.g_dmem_intg_check[3] |vpiGenScope: @@ -206,7 +206,7 @@ design: (work@alert_handler_reg_wrap) |vpiGenScopeArray: \_gen_scope_array: (work@alert_handler_reg_wrap.g_dmem_intg_check[4]), line:2:48, endln:3:6 |vpiParent: - \_module: work@alert_handler_reg_wrap (work@alert_handler_reg_wrap), file:${SURELOG_DIR}/tests/UnaryPlus/dut.sv, line:1:1, endln:4:10 + \_module_inst: work@alert_handler_reg_wrap (work@alert_handler_reg_wrap), file:${SURELOG_DIR}/tests/UnaryPlus/dut.sv, line:1:1, endln:4:10 |vpiName:g_dmem_intg_check[4] |vpiFullName:work@alert_handler_reg_wrap.g_dmem_intg_check[4] |vpiGenScope: @@ -227,7 +227,7 @@ design: (work@alert_handler_reg_wrap) |vpiGenScopeArray: \_gen_scope_array: (work@alert_handler_reg_wrap.g_dmem_intg_check[5]), line:2:48, endln:3:6 |vpiParent: - \_module: work@alert_handler_reg_wrap (work@alert_handler_reg_wrap), file:${SURELOG_DIR}/tests/UnaryPlus/dut.sv, line:1:1, endln:4:10 + \_module_inst: work@alert_handler_reg_wrap (work@alert_handler_reg_wrap), file:${SURELOG_DIR}/tests/UnaryPlus/dut.sv, line:1:1, endln:4:10 |vpiName:g_dmem_intg_check[5] |vpiFullName:work@alert_handler_reg_wrap.g_dmem_intg_check[5] |vpiGenScope: @@ -248,7 +248,7 @@ design: (work@alert_handler_reg_wrap) |vpiGenScopeArray: \_gen_scope_array: (work@alert_handler_reg_wrap.g_dmem_intg_check[6]), line:2:48, endln:3:6 |vpiParent: - \_module: work@alert_handler_reg_wrap (work@alert_handler_reg_wrap), file:${SURELOG_DIR}/tests/UnaryPlus/dut.sv, line:1:1, endln:4:10 + \_module_inst: work@alert_handler_reg_wrap (work@alert_handler_reg_wrap), file:${SURELOG_DIR}/tests/UnaryPlus/dut.sv, line:1:1, endln:4:10 |vpiName:g_dmem_intg_check[6] |vpiFullName:work@alert_handler_reg_wrap.g_dmem_intg_check[6] |vpiGenScope: @@ -269,7 +269,7 @@ design: (work@alert_handler_reg_wrap) |vpiGenScopeArray: \_gen_scope_array: (work@alert_handler_reg_wrap.g_dmem_intg_check[7]), line:2:48, endln:3:6 |vpiParent: - \_module: work@alert_handler_reg_wrap (work@alert_handler_reg_wrap), file:${SURELOG_DIR}/tests/UnaryPlus/dut.sv, line:1:1, endln:4:10 + \_module_inst: work@alert_handler_reg_wrap (work@alert_handler_reg_wrap), file:${SURELOG_DIR}/tests/UnaryPlus/dut.sv, line:1:1, endln:4:10 |vpiName:g_dmem_intg_check[7] |vpiFullName:work@alert_handler_reg_wrap.g_dmem_intg_check[7] |vpiGenScope: diff --git a/tests/UndersVal/UndersVal.log b/tests/UndersVal/UndersVal.log index 08ef5c009f..6a9cbc84aa 100644 --- a/tests/UndersVal/UndersVal.log +++ b/tests/UndersVal/UndersVal.log @@ -364,7 +364,7 @@ int_var 4 io_decl 11 logic_typespec 1 logic_var 1 -module 3 +module_inst 3 package 2 range 1 task 9 @@ -386,7 +386,7 @@ int_var 4 io_decl 22 logic_typespec 1 logic_var 1 -module 3 +module_inst 3 package 2 range 1 task 18 @@ -879,17 +879,17 @@ design: (work@dut) \_int_typespec: |vpiSigned:1 |uhdmallModules: -\_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/UndersVal/dut.sv, line:1:1, endln:12:10 +\_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/UndersVal/dut.sv, line:1:1, endln:12:10 |vpiParent: \_design: (work@dut) |vpiFullName:work@dut |vpiTypedef: \_enum_typespec: (err_code_e), line:3:3, endln:10:16 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/UndersVal/dut.sv, line:1:1, endln:12:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/UndersVal/dut.sv, line:1:1, endln:12:10 |vpiName:err_code_e |vpiInstance: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/UndersVal/dut.sv, line:1:1, endln:12:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/UndersVal/dut.sv, line:1:1, endln:12:10 |vpiBaseTypespec: \_logic_typespec: , line:3:16, endln:3:28 |vpiRange: @@ -948,7 +948,7 @@ design: (work@dut) |vpiSize:32 |vpiDefName:work@dut |uhdmtopModules: -\_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/UndersVal/dut.sv, line:1:1, endln:12:10 +\_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/UndersVal/dut.sv, line:1:1, endln:12:10 |vpiName:work@dut |vpiTypedef: \_enum_typespec: (err_code_e), line:3:3, endln:10:16 diff --git a/tests/UnelabPack/UnelabPack.log b/tests/UnelabPack/UnelabPack.log index 6e90e4dedb..14063ff949 100644 --- a/tests/UnelabPack/UnelabPack.log +++ b/tests/UnelabPack/UnelabPack.log @@ -71,7 +71,7 @@ n<> u<42> t c<1> l<1:1> el<8:1> constant 9 design 1 int_typespec 6 -module 3 +module_inst 3 package 6 param_assign 8 parameter 8 @@ -83,7 +83,7 @@ ref_obj 3 constant 9 design 1 int_typespec 6 -module 3 +module_inst 3 package 6 param_assign 8 parameter 8 diff --git a/tests/UnionCast/UnionCast.log b/tests/UnionCast/UnionCast.log index cac2691ded..391d115207 100644 --- a/tests/UnionCast/UnionCast.log +++ b/tests/UnionCast/UnionCast.log @@ -1621,7 +1621,7 @@ int_var 6 io_decl 2 logic_net 11 logic_typespec 152 -module 6 +module_inst 6 operation 41 package 3 packed_array_typespec 2 @@ -1652,7 +1652,7 @@ int_var 6 io_decl 5 logic_net 11 logic_typespec 152 -module 6 +module_inst 6 operation 42 package 3 packed_array_typespec 2 @@ -4006,7 +4006,7 @@ design: (work@r5p_lsu) |vpiTypedef: \_enum_typespec: (riscv_isa_pkg::fn3_alu_et), line:57:1, endln:66:14 |vpiParent: - \_module: work@r5p_lsu (work@r5p_lsu), file:${SURELOG_DIR}/tests/UnionCast/dut.sv, line:145:1, endln:166:19 + \_module_inst: work@r5p_lsu (work@r5p_lsu), file:${SURELOG_DIR}/tests/UnionCast/dut.sv, line:145:1, endln:166:19 |vpiName:riscv_isa_pkg::fn3_alu_et |vpiInstance: \_package: riscv_isa_pkg (riscv_isa_pkg::), file:${SURELOG_DIR}/tests/UnionCast/dut.sv, line:19:1, endln:125:26 @@ -4083,7 +4083,7 @@ design: (work@r5p_lsu) |vpiTypedef: \_enum_typespec: (riscv_isa_pkg::fn3_bru_et), line:94:1, endln:103:14 |vpiParent: - \_module: work@r5p_lsu (work@r5p_lsu), file:${SURELOG_DIR}/tests/UnionCast/dut.sv, line:145:1, endln:166:19 + \_module_inst: work@r5p_lsu (work@r5p_lsu), file:${SURELOG_DIR}/tests/UnionCast/dut.sv, line:145:1, endln:166:19 |vpiName:riscv_isa_pkg::fn3_bru_et |vpiInstance: \_package: riscv_isa_pkg (riscv_isa_pkg::), file:${SURELOG_DIR}/tests/UnionCast/dut.sv, line:19:1, endln:125:26 @@ -4148,7 +4148,7 @@ design: (work@r5p_lsu) |vpiTypedef: \_enum_typespec: (riscv_isa_pkg::fn3_ldu_et), line:69:1, endln:78:14 |vpiParent: - \_module: work@r5p_lsu (work@r5p_lsu), file:${SURELOG_DIR}/tests/UnionCast/dut.sv, line:145:1, endln:166:19 + \_module_inst: work@r5p_lsu (work@r5p_lsu), file:${SURELOG_DIR}/tests/UnionCast/dut.sv, line:145:1, endln:166:19 |vpiName:riscv_isa_pkg::fn3_ldu_et |vpiInstance: \_package: riscv_isa_pkg (riscv_isa_pkg::), file:${SURELOG_DIR}/tests/UnionCast/dut.sv, line:19:1, endln:125:26 @@ -4225,7 +4225,7 @@ design: (work@r5p_lsu) |vpiTypedef: \_enum_typespec: (riscv_isa_pkg::fn3_stu_et), line:82:1, endln:91:14 |vpiParent: - \_module: work@r5p_lsu (work@r5p_lsu), file:${SURELOG_DIR}/tests/UnionCast/dut.sv, line:145:1, endln:166:19 + \_module_inst: work@r5p_lsu (work@r5p_lsu), file:${SURELOG_DIR}/tests/UnionCast/dut.sv, line:145:1, endln:166:19 |vpiName:riscv_isa_pkg::fn3_stu_et |vpiInstance: \_package: riscv_isa_pkg (riscv_isa_pkg::), file:${SURELOG_DIR}/tests/UnionCast/dut.sv, line:19:1, endln:125:26 @@ -4284,7 +4284,7 @@ design: (work@r5p_lsu) |vpiTypedef: \_logic_typespec: (riscv_isa_pkg::fn3_t), line:48:9, endln:48:22 |vpiParent: - \_module: work@r5p_lsu (work@r5p_lsu), file:${SURELOG_DIR}/tests/UnionCast/dut.sv, line:145:1, endln:166:19 + \_module_inst: work@r5p_lsu (work@r5p_lsu), file:${SURELOG_DIR}/tests/UnionCast/dut.sv, line:145:1, endln:166:19 |vpiName:riscv_isa_pkg::fn3_t |vpiInstance: \_package: riscv_isa_pkg (riscv_isa_pkg::), file:${SURELOG_DIR}/tests/UnionCast/dut.sv, line:19:1, endln:125:26 @@ -4309,7 +4309,7 @@ design: (work@r5p_lsu) |vpiTypedef: \_struct_typespec: (riscv_isa_pkg::op32_b_t), line:110:9, endln:110:15 |vpiParent: - \_module: work@r5p_lsu (work@r5p_lsu), file:${SURELOG_DIR}/tests/UnionCast/dut.sv, line:145:1, endln:166:19 + \_module_inst: work@r5p_lsu (work@r5p_lsu), file:${SURELOG_DIR}/tests/UnionCast/dut.sv, line:145:1, endln:166:19 |vpiName:riscv_isa_pkg::op32_b_t |vpiInstance: \_package: riscv_isa_pkg (riscv_isa_pkg::), file:${SURELOG_DIR}/tests/UnionCast/dut.sv, line:19:1, endln:125:26 @@ -4577,7 +4577,7 @@ design: (work@r5p_lsu) |vpiTypespec: \_struct_typespec: (riscv_isa_pkg::op32_opcode_t), line:51:9, endln:51:15 |vpiParent: - \_module: work@r5p_lsu (work@r5p_lsu), file:${SURELOG_DIR}/tests/UnionCast/dut.sv, line:145:1, endln:166:19 + \_module_inst: work@r5p_lsu (work@r5p_lsu), file:${SURELOG_DIR}/tests/UnionCast/dut.sv, line:145:1, endln:166:19 |vpiName:riscv_isa_pkg::op32_opcode_t |vpiInstance: \_package: riscv_isa_pkg (riscv_isa_pkg::), file:${SURELOG_DIR}/tests/UnionCast/dut.sv, line:19:1, endln:125:26 @@ -4590,7 +4590,7 @@ design: (work@r5p_lsu) |vpiTypespec: \_enum_typespec: (riscv_isa_pkg::op32_op62_et), line:41:1, endln:46:16 |vpiParent: - \_module: work@r5p_lsu (work@r5p_lsu), file:${SURELOG_DIR}/tests/UnionCast/dut.sv, line:145:1, endln:166:19 + \_module_inst: work@r5p_lsu (work@r5p_lsu), file:${SURELOG_DIR}/tests/UnionCast/dut.sv, line:145:1, endln:166:19 |vpiName:riscv_isa_pkg::op32_op62_et |vpiInstance: \_package: riscv_isa_pkg (riscv_isa_pkg::), file:${SURELOG_DIR}/tests/UnionCast/dut.sv, line:19:1, endln:125:26 @@ -4857,7 +4857,7 @@ design: (work@r5p_lsu) |vpiTypedef: \_struct_typespec: (riscv_isa_pkg::op32_i_t), line:108:9, endln:108:15 |vpiParent: - \_module: work@r5p_lsu (work@r5p_lsu), file:${SURELOG_DIR}/tests/UnionCast/dut.sv, line:145:1, endln:166:19 + \_module_inst: work@r5p_lsu (work@r5p_lsu), file:${SURELOG_DIR}/tests/UnionCast/dut.sv, line:145:1, endln:166:19 |vpiName:riscv_isa_pkg::op32_i_t |vpiInstance: \_package: riscv_isa_pkg (riscv_isa_pkg::), file:${SURELOG_DIR}/tests/UnionCast/dut.sv, line:19:1, endln:125:26 @@ -5024,7 +5024,7 @@ design: (work@r5p_lsu) |vpiTypedef: \_struct_typespec: (riscv_isa_pkg::op32_j_t), line:112:9, endln:112:15 |vpiParent: - \_module: work@r5p_lsu (work@r5p_lsu), file:${SURELOG_DIR}/tests/UnionCast/dut.sv, line:145:1, endln:166:19 + \_module_inst: work@r5p_lsu (work@r5p_lsu), file:${SURELOG_DIR}/tests/UnionCast/dut.sv, line:145:1, endln:166:19 |vpiName:riscv_isa_pkg::op32_j_t |vpiInstance: \_package: riscv_isa_pkg (riscv_isa_pkg::), file:${SURELOG_DIR}/tests/UnionCast/dut.sv, line:19:1, endln:125:26 @@ -5228,7 +5228,7 @@ design: (work@r5p_lsu) |vpiTypedef: \_struct_typespec: (riscv_isa_pkg::op32_r4_t), line:106:9, endln:106:15 |vpiParent: - \_module: work@r5p_lsu (work@r5p_lsu), file:${SURELOG_DIR}/tests/UnionCast/dut.sv, line:145:1, endln:166:19 + \_module_inst: work@r5p_lsu (work@r5p_lsu), file:${SURELOG_DIR}/tests/UnionCast/dut.sv, line:145:1, endln:166:19 |vpiName:riscv_isa_pkg::op32_r4_t |vpiInstance: \_package: riscv_isa_pkg (riscv_isa_pkg::), file:${SURELOG_DIR}/tests/UnionCast/dut.sv, line:19:1, endln:125:26 @@ -5467,7 +5467,7 @@ design: (work@r5p_lsu) |vpiTypedef: \_struct_typespec: (riscv_isa_pkg::op32_r_t), line:107:9, endln:107:15 |vpiParent: - \_module: work@r5p_lsu (work@r5p_lsu), file:${SURELOG_DIR}/tests/UnionCast/dut.sv, line:145:1, endln:166:19 + \_module_inst: work@r5p_lsu (work@r5p_lsu), file:${SURELOG_DIR}/tests/UnionCast/dut.sv, line:145:1, endln:166:19 |vpiName:riscv_isa_pkg::op32_r_t |vpiInstance: \_package: riscv_isa_pkg (riscv_isa_pkg::), file:${SURELOG_DIR}/tests/UnionCast/dut.sv, line:19:1, endln:125:26 @@ -5670,7 +5670,7 @@ design: (work@r5p_lsu) |vpiTypedef: \_struct_typespec: (riscv_isa_pkg::op32_s_t), line:109:9, endln:109:15 |vpiParent: - \_module: work@r5p_lsu (work@r5p_lsu), file:${SURELOG_DIR}/tests/UnionCast/dut.sv, line:145:1, endln:166:19 + \_module_inst: work@r5p_lsu (work@r5p_lsu), file:${SURELOG_DIR}/tests/UnionCast/dut.sv, line:145:1, endln:166:19 |vpiName:riscv_isa_pkg::op32_s_t |vpiInstance: \_package: riscv_isa_pkg (riscv_isa_pkg::), file:${SURELOG_DIR}/tests/UnionCast/dut.sv, line:19:1, endln:125:26 @@ -5873,7 +5873,7 @@ design: (work@r5p_lsu) |vpiTypedef: \_union_typespec: (riscv_isa_pkg::op32_t), line:115:9, endln:115:14 |vpiParent: - \_module: work@r5p_lsu (work@r5p_lsu), file:${SURELOG_DIR}/tests/UnionCast/dut.sv, line:145:1, endln:166:19 + \_module_inst: work@r5p_lsu (work@r5p_lsu), file:${SURELOG_DIR}/tests/UnionCast/dut.sv, line:145:1, endln:166:19 |vpiName:riscv_isa_pkg::op32_t |vpiInstance: \_package: riscv_isa_pkg (riscv_isa_pkg::), file:${SURELOG_DIR}/tests/UnionCast/dut.sv, line:19:1, endln:125:26 @@ -5946,7 +5946,7 @@ design: (work@r5p_lsu) |vpiTypespec: \_struct_typespec: (riscv_isa_pkg::op32_u_t), line:111:9, endln:111:15 |vpiParent: - \_module: work@r5p_lsu (work@r5p_lsu), file:${SURELOG_DIR}/tests/UnionCast/dut.sv, line:145:1, endln:166:19 + \_module_inst: work@r5p_lsu (work@r5p_lsu), file:${SURELOG_DIR}/tests/UnionCast/dut.sv, line:145:1, endln:166:19 |vpiName:riscv_isa_pkg::op32_u_t |vpiInstance: \_package: riscv_isa_pkg (riscv_isa_pkg::), file:${SURELOG_DIR}/tests/UnionCast/dut.sv, line:19:1, endln:125:26 @@ -6190,7 +6190,7 @@ design: (work@r5p_lsu) |vpiInstance: \_package: riscv_isa_pkg (riscv_isa_pkg::), file:${SURELOG_DIR}/tests/UnionCast/dut.sv, line:19:1, endln:125:26 |uhdmallModules: -\_module: work@r5p_lsu (work@r5p_lsu), file:${SURELOG_DIR}/tests/UnionCast/dut.sv, line:145:1, endln:166:19 +\_module_inst: work@r5p_lsu (work@r5p_lsu), file:${SURELOG_DIR}/tests/UnionCast/dut.sv, line:145:1, endln:166:19 |vpiParent: \_design: (work@r5p_lsu) |vpiFullName:work@r5p_lsu @@ -6306,48 +6306,48 @@ design: (work@r5p_lsu) |vpiNet: \_logic_net: (work@r5p_lsu.ins), line:149:25, endln:149:28 |vpiParent: - \_module: work@r5p_lsu (work@r5p_lsu), file:${SURELOG_DIR}/tests/UnionCast/dut.sv, line:145:1, endln:166:19 + \_module_inst: work@r5p_lsu (work@r5p_lsu), file:${SURELOG_DIR}/tests/UnionCast/dut.sv, line:145:1, endln:166:19 |vpiName:ins |vpiFullName:work@r5p_lsu.ins |vpiNetType:36 |vpiNet: \_logic_net: (work@r5p_lsu.rd), line:151:25, endln:151:27 |vpiParent: - \_module: work@r5p_lsu (work@r5p_lsu), file:${SURELOG_DIR}/tests/UnionCast/dut.sv, line:145:1, endln:166:19 + \_module_inst: work@r5p_lsu (work@r5p_lsu), file:${SURELOG_DIR}/tests/UnionCast/dut.sv, line:145:1, endln:166:19 |vpiName:rd |vpiFullName:work@r5p_lsu.rd |vpiNetType:36 |vpiNet: \_logic_net: (work@r5p_lsu.rs1), line:152:25, endln:152:28 |vpiParent: - \_module: work@r5p_lsu (work@r5p_lsu), file:${SURELOG_DIR}/tests/UnionCast/dut.sv, line:145:1, endln:166:19 + \_module_inst: work@r5p_lsu (work@r5p_lsu), file:${SURELOG_DIR}/tests/UnionCast/dut.sv, line:145:1, endln:166:19 |vpiName:rs1 |vpiFullName:work@r5p_lsu.rs1 |vpiNetType:36 |vpiNet: \_logic_net: (work@r5p_lsu.rs2), line:153:25, endln:153:28 |vpiParent: - \_module: work@r5p_lsu (work@r5p_lsu), file:${SURELOG_DIR}/tests/UnionCast/dut.sv, line:145:1, endln:166:19 + \_module_inst: work@r5p_lsu (work@r5p_lsu), file:${SURELOG_DIR}/tests/UnionCast/dut.sv, line:145:1, endln:166:19 |vpiName:rs2 |vpiFullName:work@r5p_lsu.rs2 |vpiNetType:36 |vpiNet: \_logic_net: (work@r5p_lsu.imm), line:154:25, endln:154:28 |vpiParent: - \_module: work@r5p_lsu (work@r5p_lsu), file:${SURELOG_DIR}/tests/UnionCast/dut.sv, line:145:1, endln:166:19 + \_module_inst: work@r5p_lsu (work@r5p_lsu), file:${SURELOG_DIR}/tests/UnionCast/dut.sv, line:145:1, endln:166:19 |vpiName:imm |vpiFullName:work@r5p_lsu.imm |vpiNetType:36 |vpiNet: \_logic_net: (work@r5p_lsu.dec), line:157:8, endln:157:11 |vpiParent: - \_module: work@r5p_lsu (work@r5p_lsu), file:${SURELOG_DIR}/tests/UnionCast/dut.sv, line:145:1, endln:166:19 + \_module_inst: work@r5p_lsu (work@r5p_lsu), file:${SURELOG_DIR}/tests/UnionCast/dut.sv, line:145:1, endln:166:19 |vpiName:dec |vpiFullName:work@r5p_lsu.dec |vpiPort: \_port: (ins), line:149:25, endln:149:28 |vpiParent: - \_module: work@r5p_lsu (work@r5p_lsu), file:${SURELOG_DIR}/tests/UnionCast/dut.sv, line:145:1, endln:166:19 + \_module_inst: work@r5p_lsu (work@r5p_lsu), file:${SURELOG_DIR}/tests/UnionCast/dut.sv, line:145:1, endln:166:19 |vpiName:ins |vpiDirection:1 |vpiLowConn: @@ -6390,7 +6390,7 @@ design: (work@r5p_lsu) |vpiPort: \_port: (rd), line:151:25, endln:151:27 |vpiParent: - \_module: work@r5p_lsu (work@r5p_lsu), file:${SURELOG_DIR}/tests/UnionCast/dut.sv, line:145:1, endln:166:19 + \_module_inst: work@r5p_lsu (work@r5p_lsu), file:${SURELOG_DIR}/tests/UnionCast/dut.sv, line:145:1, endln:166:19 |vpiName:rd |vpiDirection:2 |vpiLowConn: @@ -6433,7 +6433,7 @@ design: (work@r5p_lsu) |vpiPort: \_port: (rs1), line:152:25, endln:152:28 |vpiParent: - \_module: work@r5p_lsu (work@r5p_lsu), file:${SURELOG_DIR}/tests/UnionCast/dut.sv, line:145:1, endln:166:19 + \_module_inst: work@r5p_lsu (work@r5p_lsu), file:${SURELOG_DIR}/tests/UnionCast/dut.sv, line:145:1, endln:166:19 |vpiName:rs1 |vpiDirection:2 |vpiLowConn: @@ -6476,7 +6476,7 @@ design: (work@r5p_lsu) |vpiPort: \_port: (rs2), line:153:25, endln:153:28 |vpiParent: - \_module: work@r5p_lsu (work@r5p_lsu), file:${SURELOG_DIR}/tests/UnionCast/dut.sv, line:145:1, endln:166:19 + \_module_inst: work@r5p_lsu (work@r5p_lsu), file:${SURELOG_DIR}/tests/UnionCast/dut.sv, line:145:1, endln:166:19 |vpiName:rs2 |vpiDirection:2 |vpiLowConn: @@ -6519,7 +6519,7 @@ design: (work@r5p_lsu) |vpiPort: \_port: (imm), line:154:25, endln:154:28 |vpiParent: - \_module: work@r5p_lsu (work@r5p_lsu), file:${SURELOG_DIR}/tests/UnionCast/dut.sv, line:145:1, endln:166:19 + \_module_inst: work@r5p_lsu (work@r5p_lsu), file:${SURELOG_DIR}/tests/UnionCast/dut.sv, line:145:1, endln:166:19 |vpiName:imm |vpiDirection:2 |vpiLowConn: @@ -6562,7 +6562,7 @@ design: (work@r5p_lsu) |vpiContAssign: \_cont_assign: , line:159:8, endln:159:26 |vpiParent: - \_module: work@r5p_lsu (work@r5p_lsu), file:${SURELOG_DIR}/tests/UnionCast/dut.sv, line:145:1, endln:166:19 + \_module_inst: work@r5p_lsu (work@r5p_lsu), file:${SURELOG_DIR}/tests/UnionCast/dut.sv, line:145:1, endln:166:19 |vpiRhs: \_operation: , line:159:14, endln:159:26 |vpiParent: @@ -6589,7 +6589,7 @@ design: (work@r5p_lsu) |vpiContAssign: \_cont_assign: , line:161:8, endln:161:22 |vpiParent: - \_module: work@r5p_lsu (work@r5p_lsu), file:${SURELOG_DIR}/tests/UnionCast/dut.sv, line:145:1, endln:166:19 + \_module_inst: work@r5p_lsu (work@r5p_lsu), file:${SURELOG_DIR}/tests/UnionCast/dut.sv, line:145:1, endln:166:19 |vpiRhs: \_hier_path: (dec.r.rd), line:161:14, endln:161:22 |vpiParent: @@ -6619,7 +6619,7 @@ design: (work@r5p_lsu) |vpiContAssign: \_cont_assign: , line:162:8, endln:162:23 |vpiParent: - \_module: work@r5p_lsu (work@r5p_lsu), file:${SURELOG_DIR}/tests/UnionCast/dut.sv, line:145:1, endln:166:19 + \_module_inst: work@r5p_lsu (work@r5p_lsu), file:${SURELOG_DIR}/tests/UnionCast/dut.sv, line:145:1, endln:166:19 |vpiRhs: \_hier_path: (dec.r.rs1), line:162:14, endln:162:23 |vpiParent: @@ -6649,7 +6649,7 @@ design: (work@r5p_lsu) |vpiContAssign: \_cont_assign: , line:163:8, endln:163:23 |vpiParent: - \_module: work@r5p_lsu (work@r5p_lsu), file:${SURELOG_DIR}/tests/UnionCast/dut.sv, line:145:1, endln:166:19 + \_module_inst: work@r5p_lsu (work@r5p_lsu), file:${SURELOG_DIR}/tests/UnionCast/dut.sv, line:145:1, endln:166:19 |vpiRhs: \_hier_path: (dec.r.rs2), line:163:14, endln:163:23 |vpiParent: @@ -6679,7 +6679,7 @@ design: (work@r5p_lsu) |vpiContAssign: \_cont_assign: , line:164:8, endln:164:28 |vpiParent: - \_module: work@r5p_lsu (work@r5p_lsu), file:${SURELOG_DIR}/tests/UnionCast/dut.sv, line:145:1, endln:166:19 + \_module_inst: work@r5p_lsu (work@r5p_lsu), file:${SURELOG_DIR}/tests/UnionCast/dut.sv, line:145:1, endln:166:19 |vpiRhs: \_hier_path: (dec.i.imm_11_0), line:164:14, endln:164:28 |vpiParent: @@ -6707,12 +6707,12 @@ design: (work@r5p_lsu) |vpiActual: \_logic_net: (work@r5p_lsu.imm), line:154:25, endln:154:28 |uhdmtopModules: -\_module: work@r5p_lsu (work@r5p_lsu), file:${SURELOG_DIR}/tests/UnionCast/dut.sv, line:145:1, endln:166:19 +\_module_inst: work@r5p_lsu (work@r5p_lsu), file:${SURELOG_DIR}/tests/UnionCast/dut.sv, line:145:1, endln:166:19 |vpiName:work@r5p_lsu |vpiVariables: \_union_var: (work@r5p_lsu.dec), line:157:8, endln:157:11 |vpiParent: - \_module: work@r5p_lsu (work@r5p_lsu), file:${SURELOG_DIR}/tests/UnionCast/dut.sv, line:145:1, endln:166:19 + \_module_inst: work@r5p_lsu (work@r5p_lsu), file:${SURELOG_DIR}/tests/UnionCast/dut.sv, line:145:1, endln:166:19 |vpiTypespec: \_union_typespec: (riscv_isa_pkg::op32_t), line:115:9, endln:115:14 |vpiName:dec @@ -6755,7 +6755,7 @@ design: (work@r5p_lsu) |vpiTaskFunc: \_function: (riscv_isa_pkg::opsiz), line:25:1, endln:34:19 |vpiParent: - \_module: work@r5p_lsu (work@r5p_lsu), file:${SURELOG_DIR}/tests/UnionCast/dut.sv, line:145:1, endln:166:19 + \_module_inst: work@r5p_lsu (work@r5p_lsu), file:${SURELOG_DIR}/tests/UnionCast/dut.sv, line:145:1, endln:166:19 |vpiName:opsiz |vpiFullName:riscv_isa_pkg::opsiz |vpiVisibility:1 @@ -6763,7 +6763,7 @@ design: (work@r5p_lsu) |vpiReturn: \_int_var: , line:25:20, endln:25:32 |vpiParent: - \_module: work@r5p_lsu (work@r5p_lsu), file:${SURELOG_DIR}/tests/UnionCast/dut.sv, line:145:1, endln:166:19 + \_module_inst: work@r5p_lsu (work@r5p_lsu), file:${SURELOG_DIR}/tests/UnionCast/dut.sv, line:145:1, endln:166:19 |vpiIODecl: \_io_decl: (op), line:25:55, endln:25:57 |vpiParent: @@ -6829,11 +6829,11 @@ design: (work@r5p_lsu) |vpiActual: \_int_var: , line:25:20, endln:25:32 |vpiInstance: - \_module: work@r5p_lsu (work@r5p_lsu), file:${SURELOG_DIR}/tests/UnionCast/dut.sv, line:145:1, endln:166:19 + \_module_inst: work@r5p_lsu (work@r5p_lsu), file:${SURELOG_DIR}/tests/UnionCast/dut.sv, line:145:1, endln:166:19 |vpiNet: \_logic_net: (work@r5p_lsu.ins), line:149:25, endln:149:28 |vpiParent: - \_module: work@r5p_lsu (work@r5p_lsu), file:${SURELOG_DIR}/tests/UnionCast/dut.sv, line:145:1, endln:166:19 + \_module_inst: work@r5p_lsu (work@r5p_lsu), file:${SURELOG_DIR}/tests/UnionCast/dut.sv, line:145:1, endln:166:19 |vpiTypespec: \_logic_typespec: , line:149:10, endln:149:24 |vpiRange: @@ -6860,7 +6860,7 @@ design: (work@r5p_lsu) |vpiNet: \_logic_net: (work@r5p_lsu.rd), line:151:25, endln:151:27 |vpiParent: - \_module: work@r5p_lsu (work@r5p_lsu), file:${SURELOG_DIR}/tests/UnionCast/dut.sv, line:145:1, endln:166:19 + \_module_inst: work@r5p_lsu (work@r5p_lsu), file:${SURELOG_DIR}/tests/UnionCast/dut.sv, line:145:1, endln:166:19 |vpiTypespec: \_logic_typespec: , line:151:10, endln:151:24 |vpiRange: @@ -6887,7 +6887,7 @@ design: (work@r5p_lsu) |vpiNet: \_logic_net: (work@r5p_lsu.rs1), line:152:25, endln:152:28 |vpiParent: - \_module: work@r5p_lsu (work@r5p_lsu), file:${SURELOG_DIR}/tests/UnionCast/dut.sv, line:145:1, endln:166:19 + \_module_inst: work@r5p_lsu (work@r5p_lsu), file:${SURELOG_DIR}/tests/UnionCast/dut.sv, line:145:1, endln:166:19 |vpiTypespec: \_logic_typespec: , line:152:10, endln:152:24 |vpiRange: @@ -6914,7 +6914,7 @@ design: (work@r5p_lsu) |vpiNet: \_logic_net: (work@r5p_lsu.rs2), line:153:25, endln:153:28 |vpiParent: - \_module: work@r5p_lsu (work@r5p_lsu), file:${SURELOG_DIR}/tests/UnionCast/dut.sv, line:145:1, endln:166:19 + \_module_inst: work@r5p_lsu (work@r5p_lsu), file:${SURELOG_DIR}/tests/UnionCast/dut.sv, line:145:1, endln:166:19 |vpiTypespec: \_logic_typespec: , line:153:10, endln:153:24 |vpiRange: @@ -6941,7 +6941,7 @@ design: (work@r5p_lsu) |vpiNet: \_logic_net: (work@r5p_lsu.imm), line:154:25, endln:154:28 |vpiParent: - \_module: work@r5p_lsu (work@r5p_lsu), file:${SURELOG_DIR}/tests/UnionCast/dut.sv, line:145:1, endln:166:19 + \_module_inst: work@r5p_lsu (work@r5p_lsu), file:${SURELOG_DIR}/tests/UnionCast/dut.sv, line:145:1, endln:166:19 |vpiTypespec: \_logic_typespec: , line:154:10, endln:154:24 |vpiRange: @@ -6969,7 +6969,7 @@ design: (work@r5p_lsu) |vpiPort: \_port: (ins), line:149:25, endln:149:28 |vpiParent: - \_module: work@r5p_lsu (work@r5p_lsu), file:${SURELOG_DIR}/tests/UnionCast/dut.sv, line:145:1, endln:166:19 + \_module_inst: work@r5p_lsu (work@r5p_lsu), file:${SURELOG_DIR}/tests/UnionCast/dut.sv, line:145:1, endln:166:19 |vpiName:ins |vpiDirection:1 |vpiLowConn: @@ -7003,11 +7003,11 @@ design: (work@r5p_lsu) |UINT:0 |vpiConstType:9 |vpiInstance: - \_module: work@r5p_lsu (work@r5p_lsu), file:${SURELOG_DIR}/tests/UnionCast/dut.sv, line:145:1, endln:166:19 + \_module_inst: work@r5p_lsu (work@r5p_lsu), file:${SURELOG_DIR}/tests/UnionCast/dut.sv, line:145:1, endln:166:19 |vpiPort: \_port: (rd), line:151:25, endln:151:27 |vpiParent: - \_module: work@r5p_lsu (work@r5p_lsu), file:${SURELOG_DIR}/tests/UnionCast/dut.sv, line:145:1, endln:166:19 + \_module_inst: work@r5p_lsu (work@r5p_lsu), file:${SURELOG_DIR}/tests/UnionCast/dut.sv, line:145:1, endln:166:19 |vpiName:rd |vpiDirection:2 |vpiLowConn: @@ -7041,11 +7041,11 @@ design: (work@r5p_lsu) |UINT:0 |vpiConstType:9 |vpiInstance: - \_module: work@r5p_lsu (work@r5p_lsu), file:${SURELOG_DIR}/tests/UnionCast/dut.sv, line:145:1, endln:166:19 + \_module_inst: work@r5p_lsu (work@r5p_lsu), file:${SURELOG_DIR}/tests/UnionCast/dut.sv, line:145:1, endln:166:19 |vpiPort: \_port: (rs1), line:152:25, endln:152:28 |vpiParent: - \_module: work@r5p_lsu (work@r5p_lsu), file:${SURELOG_DIR}/tests/UnionCast/dut.sv, line:145:1, endln:166:19 + \_module_inst: work@r5p_lsu (work@r5p_lsu), file:${SURELOG_DIR}/tests/UnionCast/dut.sv, line:145:1, endln:166:19 |vpiName:rs1 |vpiDirection:2 |vpiLowConn: @@ -7079,11 +7079,11 @@ design: (work@r5p_lsu) |UINT:0 |vpiConstType:9 |vpiInstance: - \_module: work@r5p_lsu (work@r5p_lsu), file:${SURELOG_DIR}/tests/UnionCast/dut.sv, line:145:1, endln:166:19 + \_module_inst: work@r5p_lsu (work@r5p_lsu), file:${SURELOG_DIR}/tests/UnionCast/dut.sv, line:145:1, endln:166:19 |vpiPort: \_port: (rs2), line:153:25, endln:153:28 |vpiParent: - \_module: work@r5p_lsu (work@r5p_lsu), file:${SURELOG_DIR}/tests/UnionCast/dut.sv, line:145:1, endln:166:19 + \_module_inst: work@r5p_lsu (work@r5p_lsu), file:${SURELOG_DIR}/tests/UnionCast/dut.sv, line:145:1, endln:166:19 |vpiName:rs2 |vpiDirection:2 |vpiLowConn: @@ -7117,11 +7117,11 @@ design: (work@r5p_lsu) |UINT:0 |vpiConstType:9 |vpiInstance: - \_module: work@r5p_lsu (work@r5p_lsu), file:${SURELOG_DIR}/tests/UnionCast/dut.sv, line:145:1, endln:166:19 + \_module_inst: work@r5p_lsu (work@r5p_lsu), file:${SURELOG_DIR}/tests/UnionCast/dut.sv, line:145:1, endln:166:19 |vpiPort: \_port: (imm), line:154:25, endln:154:28 |vpiParent: - \_module: work@r5p_lsu (work@r5p_lsu), file:${SURELOG_DIR}/tests/UnionCast/dut.sv, line:145:1, endln:166:19 + \_module_inst: work@r5p_lsu (work@r5p_lsu), file:${SURELOG_DIR}/tests/UnionCast/dut.sv, line:145:1, endln:166:19 |vpiName:imm |vpiDirection:2 |vpiLowConn: @@ -7155,11 +7155,11 @@ design: (work@r5p_lsu) |UINT:0 |vpiConstType:9 |vpiInstance: - \_module: work@r5p_lsu (work@r5p_lsu), file:${SURELOG_DIR}/tests/UnionCast/dut.sv, line:145:1, endln:166:19 + \_module_inst: work@r5p_lsu (work@r5p_lsu), file:${SURELOG_DIR}/tests/UnionCast/dut.sv, line:145:1, endln:166:19 |vpiContAssign: \_cont_assign: , line:159:8, endln:159:26 |vpiParent: - \_module: work@r5p_lsu (work@r5p_lsu), file:${SURELOG_DIR}/tests/UnionCast/dut.sv, line:145:1, endln:166:19 + \_module_inst: work@r5p_lsu (work@r5p_lsu), file:${SURELOG_DIR}/tests/UnionCast/dut.sv, line:145:1, endln:166:19 |vpiRhs: \_operation: , line:159:14, endln:159:26 |vpiParent: @@ -11153,7 +11153,7 @@ design: (work@r5p_lsu) |vpiContAssign: \_cont_assign: , line:161:8, endln:161:22 |vpiParent: - \_module: work@r5p_lsu (work@r5p_lsu), file:${SURELOG_DIR}/tests/UnionCast/dut.sv, line:145:1, endln:166:19 + \_module_inst: work@r5p_lsu (work@r5p_lsu), file:${SURELOG_DIR}/tests/UnionCast/dut.sv, line:145:1, endln:166:19 |vpiRhs: \_hier_path: (dec.r.rd), line:161:14, endln:161:22 |vpiParent: @@ -11191,7 +11191,7 @@ design: (work@r5p_lsu) |vpiContAssign: \_cont_assign: , line:162:8, endln:162:23 |vpiParent: - \_module: work@r5p_lsu (work@r5p_lsu), file:${SURELOG_DIR}/tests/UnionCast/dut.sv, line:145:1, endln:166:19 + \_module_inst: work@r5p_lsu (work@r5p_lsu), file:${SURELOG_DIR}/tests/UnionCast/dut.sv, line:145:1, endln:166:19 |vpiRhs: \_hier_path: (dec.r.rs1), line:162:14, endln:162:23 |vpiParent: @@ -11229,7 +11229,7 @@ design: (work@r5p_lsu) |vpiContAssign: \_cont_assign: , line:163:8, endln:163:23 |vpiParent: - \_module: work@r5p_lsu (work@r5p_lsu), file:${SURELOG_DIR}/tests/UnionCast/dut.sv, line:145:1, endln:166:19 + \_module_inst: work@r5p_lsu (work@r5p_lsu), file:${SURELOG_DIR}/tests/UnionCast/dut.sv, line:145:1, endln:166:19 |vpiRhs: \_hier_path: (dec.r.rs2), line:163:14, endln:163:23 |vpiParent: @@ -11267,7 +11267,7 @@ design: (work@r5p_lsu) |vpiContAssign: \_cont_assign: , line:164:8, endln:164:28 |vpiParent: - \_module: work@r5p_lsu (work@r5p_lsu), file:${SURELOG_DIR}/tests/UnionCast/dut.sv, line:145:1, endln:166:19 + \_module_inst: work@r5p_lsu (work@r5p_lsu), file:${SURELOG_DIR}/tests/UnionCast/dut.sv, line:145:1, endln:166:19 |vpiRhs: \_hier_path: (dec.i.imm_11_0), line:164:14, endln:164:28 |vpiParent: diff --git a/tests/UnitClass/UnitClass.log b/tests/UnitClass/UnitClass.log index ab38077e8f..d63dc20185 100644 --- a/tests/UnitClass/UnitClass.log +++ b/tests/UnitClass/UnitClass.log @@ -672,7 +672,7 @@ int_var 4 io_decl 11 logic_typespec 1 logic_var 2 -module 4 +module_inst 4 package 2 packed_array_typespec 1 param_assign 8 diff --git a/tests/UnitConcat/UnitConcat.log b/tests/UnitConcat/UnitConcat.log index f549ee63a4..e672e3c6b6 100644 --- a/tests/UnitConcat/UnitConcat.log +++ b/tests/UnitConcat/UnitConcat.log @@ -26,7 +26,7 @@ cont_assign 1 design 1 logic_net 5 -module 3 +module_inst 3 operation 1 ref_obj 5 === UHDM Object Stats End === @@ -42,7 +42,7 @@ ref_obj 5 design: (work@dut) |vpiName:work@dut |uhdmallModules: -\_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/UnitConcat/top.sv, line:1:1, endln:8:10 +\_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/UnitConcat/top.sv, line:1:1, endln:8:10 |vpiParent: \_design: (work@dut) |vpiFullName:work@dut @@ -50,7 +50,7 @@ design: (work@dut) |vpiContAssign: \_cont_assign: , line:3:10, endln:6:23 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/UnitConcat/top.sv, line:1:1, endln:8:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/UnitConcat/top.sv, line:1:1, endln:8:10 |vpiRhs: \_ref_obj: (work@dut.irq), line:6:20, endln:6:23 |vpiParent: @@ -97,7 +97,7 @@ design: (work@dut) |vpiActual: \_logic_net: (intr_classa_o) |uhdmtopModules: -\_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/UnitConcat/top.sv, line:1:1, endln:8:10 +\_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/UnitConcat/top.sv, line:1:1, endln:8:10 |vpiName:work@dut |vpiDefName:work@dut |vpiTop:1 diff --git a/tests/UnitDefParam/UnitDefParam.log b/tests/UnitDefParam/UnitDefParam.log index ea62443333..a4fc2f3bc4 100644 --- a/tests/UnitDefParam/UnitDefParam.log +++ b/tests/UnitDefParam/UnitDefParam.log @@ -1213,7 +1213,7 @@ int_typespec 73 int_var 4 io_decl 11 logic_var 1 -module 77 +module_inst 77 operation 73 package 2 param_assign 13 @@ -1643,14 +1643,14 @@ design: (work@top_def) \_int_typespec: |vpiSigned:1 |uhdmallModules: -\_module: work@def (work@def), file:${SURELOG_DIR}/tests/UnitDefParam/def.v, line:2:1, endln:8:10 +\_module_inst: work@def (work@def), file:${SURELOG_DIR}/tests/UnitDefParam/def.v, line:2:1, endln:8:10 |vpiParent: \_design: (work@top_def) |vpiFullName:work@def |vpiParameter: \_parameter: (work@def.SIZE1), line:3:11, endln:3:16 |vpiParent: - \_module: work@def (work@def), file:${SURELOG_DIR}/tests/UnitDefParam/def.v, line:2:1, endln:8:10 + \_module_inst: work@def (work@def), file:${SURELOG_DIR}/tests/UnitDefParam/def.v, line:2:1, endln:8:10 |UINT:2 |vpiTypespec: \_int_typespec: @@ -1659,7 +1659,7 @@ design: (work@top_def) |vpiParamAssign: \_param_assign: , line:3:11, endln:3:20 |vpiParent: - \_module: work@def (work@def), file:${SURELOG_DIR}/tests/UnitDefParam/def.v, line:2:1, endln:8:10 + \_module_inst: work@def (work@def), file:${SURELOG_DIR}/tests/UnitDefParam/def.v, line:2:1, endln:8:10 |vpiRhs: \_constant: , line:3:19, endln:3:20 |vpiDecompile:2 @@ -1672,20 +1672,20 @@ design: (work@top_def) \_parameter: (work@def.SIZE1), line:3:11, endln:3:16 |vpiDefName:work@def |uhdmallModules: -\_module: work@defparam_example (work@defparam_example), file:${SURELOG_DIR}/tests/UnitDefParam/small.v, line:14:1, endln:27:10 +\_module_inst: work@defparam_example (work@defparam_example), file:${SURELOG_DIR}/tests/UnitDefParam/small.v, line:14:1, endln:27:10 |vpiParent: \_design: (work@top_def) |vpiFullName:work@defparam_example |vpiDefName:work@defparam_example |uhdmallModules: -\_module: work@secret_number (work@secret_number), file:${SURELOG_DIR}/tests/UnitDefParam/small.v, line:2:1, endln:12:10 +\_module_inst: work@secret_number (work@secret_number), file:${SURELOG_DIR}/tests/UnitDefParam/small.v, line:2:1, endln:12:10 |vpiParent: \_design: (work@top_def) |vpiFullName:work@secret_number |vpiParameter: \_parameter: (work@secret_number.SIZE), line:3:12, endln:3:16 |vpiParent: - \_module: work@secret_number (work@secret_number), file:${SURELOG_DIR}/tests/UnitDefParam/small.v, line:2:1, endln:12:10 + \_module_inst: work@secret_number (work@secret_number), file:${SURELOG_DIR}/tests/UnitDefParam/small.v, line:2:1, endln:12:10 |UINT:0 |vpiTypespec: \_int_typespec: @@ -1694,7 +1694,7 @@ design: (work@top_def) |vpiParamAssign: \_param_assign: , line:3:12, endln:3:20 |vpiParent: - \_module: work@secret_number (work@secret_number), file:${SURELOG_DIR}/tests/UnitDefParam/small.v, line:2:1, endln:12:10 + \_module_inst: work@secret_number (work@secret_number), file:${SURELOG_DIR}/tests/UnitDefParam/small.v, line:2:1, endln:12:10 |vpiRhs: \_constant: , line:3:19, endln:3:20 |vpiDecompile:0 @@ -1707,14 +1707,14 @@ design: (work@top_def) \_parameter: (work@secret_number.SIZE), line:3:12, endln:3:16 |vpiDefName:work@secret_number |uhdmallModules: -\_module: work@small_test (work@small_test), file:${SURELOG_DIR}/tests/UnitDefParam/top.v, line:11:1, endln:60:10 +\_module_inst: work@small_test (work@small_test), file:${SURELOG_DIR}/tests/UnitDefParam/top.v, line:11:1, endln:60:10 |vpiParent: \_design: (work@top_def) |vpiFullName:work@small_test |vpiParameter: \_parameter: (work@small_test.SIZE), line:14:27, endln:14:31 |vpiParent: - \_module: work@small_test (work@small_test), file:${SURELOG_DIR}/tests/UnitDefParam/top.v, line:11:1, endln:60:10 + \_module_inst: work@small_test (work@small_test), file:${SURELOG_DIR}/tests/UnitDefParam/top.v, line:11:1, endln:60:10 |REAL:10.000000 |vpiTypespec: \_int_typespec: , line:14:14, endln:14:20 @@ -1744,7 +1744,7 @@ design: (work@top_def) |vpiParameter: \_parameter: (work@small_test.dummy), line:15:14, endln:15:19 |vpiParent: - \_module: work@small_test (work@small_test), file:${SURELOG_DIR}/tests/UnitDefParam/top.v, line:11:1, endln:60:10 + \_module_inst: work@small_test (work@small_test), file:${SURELOG_DIR}/tests/UnitDefParam/top.v, line:11:1, endln:60:10 |UINT:5 |vpiTypespec: \_int_typespec: @@ -1753,7 +1753,7 @@ design: (work@top_def) |vpiParameter: \_parameter: (work@small_test.p1), line:16:11, endln:16:13 |vpiParent: - \_module: work@small_test (work@small_test), file:${SURELOG_DIR}/tests/UnitDefParam/top.v, line:11:1, endln:60:10 + \_module_inst: work@small_test (work@small_test), file:${SURELOG_DIR}/tests/UnitDefParam/top.v, line:11:1, endln:60:10 |BIN:100 |vpiTypespec: \_int_typespec: @@ -1770,7 +1770,7 @@ design: (work@top_def) |vpiParamAssign: \_param_assign: , line:14:27, endln:14:37 |vpiParent: - \_module: work@small_test (work@small_test), file:${SURELOG_DIR}/tests/UnitDefParam/top.v, line:11:1, endln:60:10 + \_module_inst: work@small_test (work@small_test), file:${SURELOG_DIR}/tests/UnitDefParam/top.v, line:11:1, endln:60:10 |vpiRhs: \_constant: , line:14:34, endln:14:37 |vpiDecompile:1e1 @@ -1784,7 +1784,7 @@ design: (work@top_def) |vpiParamAssign: \_param_assign: , line:15:14, endln:15:23 |vpiParent: - \_module: work@small_test (work@small_test), file:${SURELOG_DIR}/tests/UnitDefParam/top.v, line:11:1, endln:60:10 + \_module_inst: work@small_test (work@small_test), file:${SURELOG_DIR}/tests/UnitDefParam/top.v, line:11:1, endln:60:10 |vpiRhs: \_constant: , line:15:22, endln:15:23 |vpiDecompile:5 @@ -1798,7 +1798,7 @@ design: (work@top_def) |vpiParamAssign: \_param_assign: , line:16:11, endln:16:23 |vpiParent: - \_module: work@small_test (work@small_test), file:${SURELOG_DIR}/tests/UnitDefParam/top.v, line:11:1, endln:60:10 + \_module_inst: work@small_test (work@small_test), file:${SURELOG_DIR}/tests/UnitDefParam/top.v, line:11:1, endln:60:10 |vpiRhs: \_constant: , line:16:16, endln:16:23 |vpiDecompile:13'b100 @@ -1811,33 +1811,33 @@ design: (work@top_def) \_parameter: (work@small_test.p1), line:16:11, endln:16:13 |vpiDefName:work@small_test |uhdmallModules: -\_module: work@small_top (work@small_top), file:${SURELOG_DIR}/tests/UnitDefParam/top.v, line:7:1, endln:9:10 +\_module_inst: work@small_top (work@small_top), file:${SURELOG_DIR}/tests/UnitDefParam/top.v, line:7:1, endln:9:10 |vpiParent: \_design: (work@top_def) |vpiFullName:work@small_top |vpiDefName:work@small_top |uhdmallModules: -\_module: work@top_def (work@top_def), file:${SURELOG_DIR}/tests/UnitDefParam/top.v, line:1:1, endln:5:10 +\_module_inst: work@top_def (work@top_def), file:${SURELOG_DIR}/tests/UnitDefParam/top.v, line:1:1, endln:5:10 |vpiParent: \_design: (work@top_def) |vpiFullName:work@top_def |vpiDefName:work@top_def |uhdmtopModules: -\_module: work@top_def (work@top_def), file:${SURELOG_DIR}/tests/UnitDefParam/top.v, line:1:1, endln:5:10 +\_module_inst: work@top_def (work@top_def), file:${SURELOG_DIR}/tests/UnitDefParam/top.v, line:1:1, endln:5:10 |vpiName:work@top_def |vpiDefName:work@top_def |vpiTop:1 |vpiTopModule:1 - |vpiModule: - \_module: work@def (work@top_def.u1), file:${SURELOG_DIR}/tests/UnitDefParam/top.v, line:3:5, endln:3:19 + |vpiModuleInst: + \_module_inst: work@def (work@top_def.u1), file:${SURELOG_DIR}/tests/UnitDefParam/top.v, line:3:5, endln:3:19 |vpiParent: - \_module: work@top_def (work@top_def), file:${SURELOG_DIR}/tests/UnitDefParam/top.v, line:1:1, endln:5:10 + \_module_inst: work@top_def (work@top_def), file:${SURELOG_DIR}/tests/UnitDefParam/top.v, line:1:1, endln:5:10 |vpiName:u1 |vpiFullName:work@top_def.u1 |vpiParameter: \_parameter: (work@top_def.u1.SIZE1), line:3:11, endln:3:16 |vpiParent: - \_module: work@def (work@top_def.u1), file:${SURELOG_DIR}/tests/UnitDefParam/top.v, line:3:5, endln:3:19 + \_module_inst: work@def (work@top_def.u1), file:${SURELOG_DIR}/tests/UnitDefParam/top.v, line:3:5, endln:3:19 |UINT:2 |vpiTypespec: \_int_typespec: @@ -1848,7 +1848,7 @@ design: (work@top_def) |vpiParamAssign: \_param_assign: , line:3:11, endln:3:20 |vpiParent: - \_module: work@def (work@top_def.u1), file:${SURELOG_DIR}/tests/UnitDefParam/top.v, line:3:5, endln:3:19 + \_module_inst: work@def (work@top_def.u1), file:${SURELOG_DIR}/tests/UnitDefParam/top.v, line:3:5, endln:3:19 |vpiOverriden:1 |vpiRhs: \_constant: , line:3:19, endln:3:20 @@ -1864,23 +1864,23 @@ design: (work@top_def) |vpiDefFile:${SURELOG_DIR}/tests/UnitDefParam/def.v |vpiDefLineNo:2 |vpiInstance: - \_module: work@top_def (work@top_def), file:${SURELOG_DIR}/tests/UnitDefParam/top.v, line:1:1, endln:5:10 + \_module_inst: work@top_def (work@top_def), file:${SURELOG_DIR}/tests/UnitDefParam/top.v, line:1:1, endln:5:10 |uhdmtopModules: -\_module: work@small_top (work@small_top), file:${SURELOG_DIR}/tests/UnitDefParam/top.v, line:7:1, endln:9:10 +\_module_inst: work@small_top (work@small_top), file:${SURELOG_DIR}/tests/UnitDefParam/top.v, line:7:1, endln:9:10 |vpiName:work@small_top |vpiDefName:work@small_top |vpiTop:1 |vpiTopModule:1 - |vpiModule: - \_module: work@small_test (work@small_top.u1), file:${SURELOG_DIR}/tests/UnitDefParam/top.v, line:8:4, endln:8:29 + |vpiModuleInst: + \_module_inst: work@small_test (work@small_top.u1), file:${SURELOG_DIR}/tests/UnitDefParam/top.v, line:8:4, endln:8:29 |vpiParent: - \_module: work@small_top (work@small_top), file:${SURELOG_DIR}/tests/UnitDefParam/top.v, line:7:1, endln:9:10 + \_module_inst: work@small_top (work@small_top), file:${SURELOG_DIR}/tests/UnitDefParam/top.v, line:7:1, endln:9:10 |vpiName:u1 |vpiFullName:work@small_top.u1 |vpiParameter: \_parameter: (work@small_top.u1.SIZE), line:14:27, endln:14:31 |vpiParent: - \_module: work@small_test (work@small_top.u1), file:${SURELOG_DIR}/tests/UnitDefParam/top.v, line:8:4, endln:8:29 + \_module_inst: work@small_test (work@small_top.u1), file:${SURELOG_DIR}/tests/UnitDefParam/top.v, line:8:4, endln:8:29 |REAL:10.000000 |vpiTypespec: \_int_typespec: , line:14:14, endln:14:20 @@ -1912,7 +1912,7 @@ design: (work@top_def) |vpiParameter: \_parameter: (work@small_top.u1.dummy), line:15:14, endln:15:19 |vpiParent: - \_module: work@small_test (work@small_top.u1), file:${SURELOG_DIR}/tests/UnitDefParam/top.v, line:8:4, endln:8:29 + \_module_inst: work@small_test (work@small_top.u1), file:${SURELOG_DIR}/tests/UnitDefParam/top.v, line:8:4, endln:8:29 |UINT:5 |vpiTypespec: \_int_typespec: @@ -1923,7 +1923,7 @@ design: (work@top_def) |vpiParameter: \_parameter: (work@small_top.u1.p1), line:16:11, endln:16:13 |vpiParent: - \_module: work@small_test (work@small_top.u1), file:${SURELOG_DIR}/tests/UnitDefParam/top.v, line:8:4, endln:8:29 + \_module_inst: work@small_test (work@small_top.u1), file:${SURELOG_DIR}/tests/UnitDefParam/top.v, line:8:4, endln:8:29 |BIN:100 |vpiTypespec: \_int_typespec: @@ -1948,7 +1948,7 @@ design: (work@top_def) |vpiParamAssign: \_param_assign: , line:14:27, endln:14:37 |vpiParent: - \_module: work@small_test (work@small_top.u1), file:${SURELOG_DIR}/tests/UnitDefParam/top.v, line:8:4, endln:8:29 + \_module_inst: work@small_test (work@small_top.u1), file:${SURELOG_DIR}/tests/UnitDefParam/top.v, line:8:4, endln:8:29 |vpiOverriden:1 |vpiRhs: \_constant: , line:14:34, endln:14:37 @@ -1963,7 +1963,7 @@ design: (work@top_def) |vpiParamAssign: \_param_assign: , line:15:14, endln:15:23 |vpiParent: - \_module: work@small_test (work@small_top.u1), file:${SURELOG_DIR}/tests/UnitDefParam/top.v, line:8:4, endln:8:29 + \_module_inst: work@small_test (work@small_top.u1), file:${SURELOG_DIR}/tests/UnitDefParam/top.v, line:8:4, endln:8:29 |vpiOverriden:1 |vpiRhs: \_constant: , line:15:22, endln:15:23 @@ -1978,7 +1978,7 @@ design: (work@top_def) |vpiParamAssign: \_param_assign: , line:16:11, endln:16:23 |vpiParent: - \_module: work@small_test (work@small_top.u1), file:${SURELOG_DIR}/tests/UnitDefParam/top.v, line:8:4, endln:8:29 + \_module_inst: work@small_test (work@small_top.u1), file:${SURELOG_DIR}/tests/UnitDefParam/top.v, line:8:4, endln:8:29 |vpiRhs: \_constant: , line:16:16, endln:16:23 |vpiDecompile:13'b100 @@ -1993,11 +1993,11 @@ design: (work@top_def) |vpiDefFile:${SURELOG_DIR}/tests/UnitDefParam/top.v |vpiDefLineNo:11 |vpiInstance: - \_module: work@small_top (work@small_top), file:${SURELOG_DIR}/tests/UnitDefParam/top.v, line:7:1, endln:9:10 + \_module_inst: work@small_top (work@small_top), file:${SURELOG_DIR}/tests/UnitDefParam/top.v, line:7:1, endln:9:10 |vpiGenScopeArray: \_gen_scope_array: (work@small_top.u1.B1[0]), line:23:1, endln:57:4 |vpiParent: - \_module: work@small_test (work@small_top.u1), file:${SURELOG_DIR}/tests/UnitDefParam/top.v, line:8:4, endln:8:29 + \_module_inst: work@small_test (work@small_top.u1), file:${SURELOG_DIR}/tests/UnitDefParam/top.v, line:8:4, endln:8:29 |vpiName:B1[0] |vpiFullName:work@small_top.u1.B1[0] |vpiGenScope: @@ -2015,8 +2015,8 @@ design: (work@top_def) |vpiLocalParam:1 |vpiName:i |vpiFullName:work@small_top.u1.B1[0].i - |vpiModule: - \_module: work@small_top.u1.B1[0]::M1 (work@small_top.u1.B1[0].N1), file:${SURELOG_DIR}/tests/UnitDefParam/top.v, line:26:1, endln:26:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[0]::M1 (work@small_top.u1.B1[0].N1), file:${SURELOG_DIR}/tests/UnitDefParam/top.v, line:26:1, endln:26:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[0]) |vpiName:N1 @@ -2043,8 +2043,8 @@ design: (work@top_def) |vpiLocalParam:1 |vpiName:j |vpiFullName:work@small_top.u1.B1[0].B2[0].j - |vpiModule: - \_module: work@small_top.u1.B1[0].B2[0]::M2 (work@small_top.u1.B1[0].B2[0].N2), file:${SURELOG_DIR}/tests/UnitDefParam/top.v, line:32:1, endln:32:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[0].B2[0]::M2 (work@small_top.u1.B1[0].B2[0].N2), file:${SURELOG_DIR}/tests/UnitDefParam/top.v, line:32:1, endln:32:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[0].B2[0]) |vpiName:N2 @@ -2071,8 +2071,8 @@ design: (work@top_def) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[0].B2[0].B3[0].k - |vpiModule: - \_module: work@small_top.u1.B1[0].B2[0].B3[0]::M3 (work@small_top.u1.B1[0].B2[0].B3[0].N3), file:${SURELOG_DIR}/tests/UnitDefParam/top.v, line:39:1, endln:39:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[0].B2[0].B3[0]::M3 (work@small_top.u1.B1[0].B2[0].B3[0].N3), file:${SURELOG_DIR}/tests/UnitDefParam/top.v, line:39:1, endln:39:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[0].B2[0].B3[0]) |vpiName:N3 @@ -2099,8 +2099,8 @@ design: (work@top_def) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[0].B2[0].B3[1].k - |vpiModule: - \_module: work@small_top.u1.B1[0].B2[0].B3[1]::M3 (work@small_top.u1.B1[0].B2[0].B3[1].N3), file:${SURELOG_DIR}/tests/UnitDefParam/top.v, line:39:1, endln:39:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[0].B2[0].B3[1]::M3 (work@small_top.u1.B1[0].B2[0].B3[1].N3), file:${SURELOG_DIR}/tests/UnitDefParam/top.v, line:39:1, endln:39:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[0].B2[0].B3[1]) |vpiName:N3 @@ -2127,8 +2127,8 @@ design: (work@top_def) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[0].B2[0].B3[2].k - |vpiModule: - \_module: work@small_top.u1.B1[0].B2[0].B3[2]::M3 (work@small_top.u1.B1[0].B2[0].B3[2].N3), file:${SURELOG_DIR}/tests/UnitDefParam/top.v, line:39:1, endln:39:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[0].B2[0].B3[2]::M3 (work@small_top.u1.B1[0].B2[0].B3[2].N3), file:${SURELOG_DIR}/tests/UnitDefParam/top.v, line:39:1, endln:39:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[0].B2[0].B3[2]) |vpiName:N3 @@ -2155,8 +2155,8 @@ design: (work@top_def) |vpiLocalParam:1 |vpiName:j |vpiFullName:work@small_top.u1.B1[0].B2[1].j - |vpiModule: - \_module: work@small_top.u1.B1[0].B2[1]::M2 (work@small_top.u1.B1[0].B2[1].N2), file:${SURELOG_DIR}/tests/UnitDefParam/top.v, line:32:1, endln:32:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[0].B2[1]::M2 (work@small_top.u1.B1[0].B2[1].N2), file:${SURELOG_DIR}/tests/UnitDefParam/top.v, line:32:1, endln:32:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[0].B2[1]) |vpiName:N2 @@ -2183,8 +2183,8 @@ design: (work@top_def) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[0].B2[1].B3[0].k - |vpiModule: - \_module: work@small_top.u1.B1[0].B2[1].B3[0]::M3 (work@small_top.u1.B1[0].B2[1].B3[0].N3), file:${SURELOG_DIR}/tests/UnitDefParam/top.v, line:39:1, endln:39:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[0].B2[1].B3[0]::M3 (work@small_top.u1.B1[0].B2[1].B3[0].N3), file:${SURELOG_DIR}/tests/UnitDefParam/top.v, line:39:1, endln:39:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[0].B2[1].B3[0]) |vpiName:N3 @@ -2211,8 +2211,8 @@ design: (work@top_def) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[0].B2[1].B3[1].k - |vpiModule: - \_module: work@small_top.u1.B1[0].B2[1].B3[1]::M3 (work@small_top.u1.B1[0].B2[1].B3[1].N3), file:${SURELOG_DIR}/tests/UnitDefParam/top.v, line:39:1, endln:39:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[0].B2[1].B3[1]::M3 (work@small_top.u1.B1[0].B2[1].B3[1].N3), file:${SURELOG_DIR}/tests/UnitDefParam/top.v, line:39:1, endln:39:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[0].B2[1].B3[1]) |vpiName:N3 @@ -2239,8 +2239,8 @@ design: (work@top_def) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[0].B2[1].B3[2].k - |vpiModule: - \_module: work@small_top.u1.B1[0].B2[1].B3[2]::M3 (work@small_top.u1.B1[0].B2[1].B3[2].N3), file:${SURELOG_DIR}/tests/UnitDefParam/top.v, line:39:1, endln:39:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[0].B2[1].B3[2]::M3 (work@small_top.u1.B1[0].B2[1].B3[2].N3), file:${SURELOG_DIR}/tests/UnitDefParam/top.v, line:39:1, endln:39:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[0].B2[1].B3[2]) |vpiName:N3 @@ -2267,8 +2267,8 @@ design: (work@top_def) |vpiLocalParam:1 |vpiName:j |vpiFullName:work@small_top.u1.B1[0].B2[2].j - |vpiModule: - \_module: work@small_top.u1.B1[0].B2[2]::M2 (work@small_top.u1.B1[0].B2[2].N2), file:${SURELOG_DIR}/tests/UnitDefParam/top.v, line:32:1, endln:32:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[0].B2[2]::M2 (work@small_top.u1.B1[0].B2[2].N2), file:${SURELOG_DIR}/tests/UnitDefParam/top.v, line:32:1, endln:32:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[0].B2[2]) |vpiName:N2 @@ -2295,8 +2295,8 @@ design: (work@top_def) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[0].B2[2].B3[0].k - |vpiModule: - \_module: work@small_top.u1.B1[0].B2[2].B3[0]::M3 (work@small_top.u1.B1[0].B2[2].B3[0].N3), file:${SURELOG_DIR}/tests/UnitDefParam/top.v, line:39:1, endln:39:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[0].B2[2].B3[0]::M3 (work@small_top.u1.B1[0].B2[2].B3[0].N3), file:${SURELOG_DIR}/tests/UnitDefParam/top.v, line:39:1, endln:39:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[0].B2[2].B3[0]) |vpiName:N3 @@ -2323,8 +2323,8 @@ design: (work@top_def) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[0].B2[2].B3[1].k - |vpiModule: - \_module: work@small_top.u1.B1[0].B2[2].B3[1]::M3 (work@small_top.u1.B1[0].B2[2].B3[1].N3), file:${SURELOG_DIR}/tests/UnitDefParam/top.v, line:39:1, endln:39:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[0].B2[2].B3[1]::M3 (work@small_top.u1.B1[0].B2[2].B3[1].N3), file:${SURELOG_DIR}/tests/UnitDefParam/top.v, line:39:1, endln:39:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[0].B2[2].B3[1]) |vpiName:N3 @@ -2351,8 +2351,8 @@ design: (work@top_def) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[0].B2[2].B3[2].k - |vpiModule: - \_module: work@small_top.u1.B1[0].B2[2].B3[2]::M3 (work@small_top.u1.B1[0].B2[2].B3[2].N3), file:${SURELOG_DIR}/tests/UnitDefParam/top.v, line:39:1, endln:39:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[0].B2[2].B3[2]::M3 (work@small_top.u1.B1[0].B2[2].B3[2].N3), file:${SURELOG_DIR}/tests/UnitDefParam/top.v, line:39:1, endln:39:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[0].B2[2].B3[2]) |vpiName:N3 @@ -2361,7 +2361,7 @@ design: (work@top_def) |vpiGenScopeArray: \_gen_scope_array: (work@small_top.u1.B1[1]), line:23:1, endln:57:4 |vpiParent: - \_module: work@small_test (work@small_top.u1), file:${SURELOG_DIR}/tests/UnitDefParam/top.v, line:8:4, endln:8:29 + \_module_inst: work@small_test (work@small_top.u1), file:${SURELOG_DIR}/tests/UnitDefParam/top.v, line:8:4, endln:8:29 |vpiName:B1[1] |vpiFullName:work@small_top.u1.B1[1] |vpiGenScope: @@ -2379,8 +2379,8 @@ design: (work@top_def) |vpiLocalParam:1 |vpiName:i |vpiFullName:work@small_top.u1.B1[1].i - |vpiModule: - \_module: work@small_top.u1.B1[1]::M1 (work@small_top.u1.B1[1].N1), file:${SURELOG_DIR}/tests/UnitDefParam/top.v, line:26:1, endln:26:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[1]::M1 (work@small_top.u1.B1[1].N1), file:${SURELOG_DIR}/tests/UnitDefParam/top.v, line:26:1, endln:26:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[1]) |vpiName:N1 @@ -2407,8 +2407,8 @@ design: (work@top_def) |vpiLocalParam:1 |vpiName:j |vpiFullName:work@small_top.u1.B1[1].B2[0].j - |vpiModule: - \_module: work@small_top.u1.B1[1].B2[0]::M2 (work@small_top.u1.B1[1].B2[0].N2), file:${SURELOG_DIR}/tests/UnitDefParam/top.v, line:32:1, endln:32:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[1].B2[0]::M2 (work@small_top.u1.B1[1].B2[0].N2), file:${SURELOG_DIR}/tests/UnitDefParam/top.v, line:32:1, endln:32:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[1].B2[0]) |vpiName:N2 @@ -2435,8 +2435,8 @@ design: (work@top_def) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[1].B2[0].B3[0].k - |vpiModule: - \_module: work@small_top.u1.B1[1].B2[0].B3[0]::M3 (work@small_top.u1.B1[1].B2[0].B3[0].N3), file:${SURELOG_DIR}/tests/UnitDefParam/top.v, line:39:1, endln:39:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[1].B2[0].B3[0]::M3 (work@small_top.u1.B1[1].B2[0].B3[0].N3), file:${SURELOG_DIR}/tests/UnitDefParam/top.v, line:39:1, endln:39:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[1].B2[0].B3[0]) |vpiName:N3 @@ -2463,8 +2463,8 @@ design: (work@top_def) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[1].B2[0].B3[1].k - |vpiModule: - \_module: work@small_top.u1.B1[1].B2[0].B3[1]::M3 (work@small_top.u1.B1[1].B2[0].B3[1].N3), file:${SURELOG_DIR}/tests/UnitDefParam/top.v, line:39:1, endln:39:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[1].B2[0].B3[1]::M3 (work@small_top.u1.B1[1].B2[0].B3[1].N3), file:${SURELOG_DIR}/tests/UnitDefParam/top.v, line:39:1, endln:39:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[1].B2[0].B3[1]) |vpiName:N3 @@ -2491,8 +2491,8 @@ design: (work@top_def) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[1].B2[0].B3[2].k - |vpiModule: - \_module: work@small_top.u1.B1[1].B2[0].B3[2]::M3 (work@small_top.u1.B1[1].B2[0].B3[2].N3), file:${SURELOG_DIR}/tests/UnitDefParam/top.v, line:39:1, endln:39:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[1].B2[0].B3[2]::M3 (work@small_top.u1.B1[1].B2[0].B3[2].N3), file:${SURELOG_DIR}/tests/UnitDefParam/top.v, line:39:1, endln:39:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[1].B2[0].B3[2]) |vpiName:N3 @@ -2519,8 +2519,8 @@ design: (work@top_def) |vpiLocalParam:1 |vpiName:j |vpiFullName:work@small_top.u1.B1[1].B2[1].j - |vpiModule: - \_module: work@small_top.u1.B1[1].B2[1]::M2 (work@small_top.u1.B1[1].B2[1].N2), file:${SURELOG_DIR}/tests/UnitDefParam/top.v, line:32:1, endln:32:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[1].B2[1]::M2 (work@small_top.u1.B1[1].B2[1].N2), file:${SURELOG_DIR}/tests/UnitDefParam/top.v, line:32:1, endln:32:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[1].B2[1]) |vpiName:N2 @@ -2547,8 +2547,8 @@ design: (work@top_def) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[1].B2[1].B3[0].k - |vpiModule: - \_module: work@small_top.u1.B1[1].B2[1].B3[0]::M3 (work@small_top.u1.B1[1].B2[1].B3[0].N3), file:${SURELOG_DIR}/tests/UnitDefParam/top.v, line:39:1, endln:39:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[1].B2[1].B3[0]::M3 (work@small_top.u1.B1[1].B2[1].B3[0].N3), file:${SURELOG_DIR}/tests/UnitDefParam/top.v, line:39:1, endln:39:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[1].B2[1].B3[0]) |vpiName:N3 @@ -2575,8 +2575,8 @@ design: (work@top_def) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[1].B2[1].B3[1].k - |vpiModule: - \_module: work@small_top.u1.B1[1].B2[1].B3[1]::M3 (work@small_top.u1.B1[1].B2[1].B3[1].N3), file:${SURELOG_DIR}/tests/UnitDefParam/top.v, line:39:1, endln:39:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[1].B2[1].B3[1]::M3 (work@small_top.u1.B1[1].B2[1].B3[1].N3), file:${SURELOG_DIR}/tests/UnitDefParam/top.v, line:39:1, endln:39:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[1].B2[1].B3[1]) |vpiName:N3 @@ -2603,8 +2603,8 @@ design: (work@top_def) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[1].B2[1].B3[2].k - |vpiModule: - \_module: work@small_top.u1.B1[1].B2[1].B3[2]::M3 (work@small_top.u1.B1[1].B2[1].B3[2].N3), file:${SURELOG_DIR}/tests/UnitDefParam/top.v, line:39:1, endln:39:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[1].B2[1].B3[2]::M3 (work@small_top.u1.B1[1].B2[1].B3[2].N3), file:${SURELOG_DIR}/tests/UnitDefParam/top.v, line:39:1, endln:39:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[1].B2[1].B3[2]) |vpiName:N3 @@ -2631,8 +2631,8 @@ design: (work@top_def) |vpiLocalParam:1 |vpiName:j |vpiFullName:work@small_top.u1.B1[1].B2[2].j - |vpiModule: - \_module: work@small_top.u1.B1[1].B2[2]::M2 (work@small_top.u1.B1[1].B2[2].N2), file:${SURELOG_DIR}/tests/UnitDefParam/top.v, line:32:1, endln:32:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[1].B2[2]::M2 (work@small_top.u1.B1[1].B2[2].N2), file:${SURELOG_DIR}/tests/UnitDefParam/top.v, line:32:1, endln:32:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[1].B2[2]) |vpiName:N2 @@ -2659,8 +2659,8 @@ design: (work@top_def) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[1].B2[2].B3[0].k - |vpiModule: - \_module: work@small_top.u1.B1[1].B2[2].B3[0]::M3 (work@small_top.u1.B1[1].B2[2].B3[0].N3), file:${SURELOG_DIR}/tests/UnitDefParam/top.v, line:39:1, endln:39:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[1].B2[2].B3[0]::M3 (work@small_top.u1.B1[1].B2[2].B3[0].N3), file:${SURELOG_DIR}/tests/UnitDefParam/top.v, line:39:1, endln:39:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[1].B2[2].B3[0]) |vpiName:N3 @@ -2687,8 +2687,8 @@ design: (work@top_def) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[1].B2[2].B3[1].k - |vpiModule: - \_module: work@small_top.u1.B1[1].B2[2].B3[1]::M3 (work@small_top.u1.B1[1].B2[2].B3[1].N3), file:${SURELOG_DIR}/tests/UnitDefParam/top.v, line:39:1, endln:39:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[1].B2[2].B3[1]::M3 (work@small_top.u1.B1[1].B2[2].B3[1].N3), file:${SURELOG_DIR}/tests/UnitDefParam/top.v, line:39:1, endln:39:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[1].B2[2].B3[1]) |vpiName:N3 @@ -2715,8 +2715,8 @@ design: (work@top_def) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[1].B2[2].B3[2].k - |vpiModule: - \_module: work@small_top.u1.B1[1].B2[2].B3[2]::M3 (work@small_top.u1.B1[1].B2[2].B3[2].N3), file:${SURELOG_DIR}/tests/UnitDefParam/top.v, line:39:1, endln:39:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[1].B2[2].B3[2]::M3 (work@small_top.u1.B1[1].B2[2].B3[2].N3), file:${SURELOG_DIR}/tests/UnitDefParam/top.v, line:39:1, endln:39:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[1].B2[2].B3[2]) |vpiName:N3 @@ -2754,8 +2754,8 @@ design: (work@top_def) |vpiLocalParam:1 |vpiName:m |vpiFullName:work@small_top.u1.B1[1].B4.B5[0].m - |vpiModule: - \_module: work@small_top.u1.B1[1].B4.B5[0]::M4 (work@small_top.u1.B1[1].B4.B5[0].N4), file:${SURELOG_DIR}/tests/UnitDefParam/top.v, line:52:1, endln:52:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[1].B4.B5[0]::M4 (work@small_top.u1.B1[1].B4.B5[0].N4), file:${SURELOG_DIR}/tests/UnitDefParam/top.v, line:52:1, endln:52:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[1].B4.B5[0]) |vpiName:N4 @@ -2782,8 +2782,8 @@ design: (work@top_def) |vpiLocalParam:1 |vpiName:m |vpiFullName:work@small_top.u1.B1[1].B4.B5[1].m - |vpiModule: - \_module: work@small_top.u1.B1[1].B4.B5[1]::M4 (work@small_top.u1.B1[1].B4.B5[1].N4), file:${SURELOG_DIR}/tests/UnitDefParam/top.v, line:52:1, endln:52:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[1].B4.B5[1]::M4 (work@small_top.u1.B1[1].B4.B5[1].N4), file:${SURELOG_DIR}/tests/UnitDefParam/top.v, line:52:1, endln:52:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[1].B4.B5[1]) |vpiName:N4 @@ -2810,8 +2810,8 @@ design: (work@top_def) |vpiLocalParam:1 |vpiName:m |vpiFullName:work@small_top.u1.B1[1].B4.B5[2].m - |vpiModule: - \_module: work@small_top.u1.B1[1].B4.B5[2]::M4 (work@small_top.u1.B1[1].B4.B5[2].N4), file:${SURELOG_DIR}/tests/UnitDefParam/top.v, line:52:1, endln:52:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[1].B4.B5[2]::M4 (work@small_top.u1.B1[1].B4.B5[2].N4), file:${SURELOG_DIR}/tests/UnitDefParam/top.v, line:52:1, endln:52:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[1].B4.B5[2]) |vpiName:N4 @@ -2820,7 +2820,7 @@ design: (work@top_def) |vpiGenScopeArray: \_gen_scope_array: (work@small_top.u1.B1[2]), line:23:1, endln:57:4 |vpiParent: - \_module: work@small_test (work@small_top.u1), file:${SURELOG_DIR}/tests/UnitDefParam/top.v, line:8:4, endln:8:29 + \_module_inst: work@small_test (work@small_top.u1), file:${SURELOG_DIR}/tests/UnitDefParam/top.v, line:8:4, endln:8:29 |vpiName:B1[2] |vpiFullName:work@small_top.u1.B1[2] |vpiGenScope: @@ -2838,8 +2838,8 @@ design: (work@top_def) |vpiLocalParam:1 |vpiName:i |vpiFullName:work@small_top.u1.B1[2].i - |vpiModule: - \_module: work@small_top.u1.B1[2]::M1 (work@small_top.u1.B1[2].N1), file:${SURELOG_DIR}/tests/UnitDefParam/top.v, line:26:1, endln:26:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[2]::M1 (work@small_top.u1.B1[2].N1), file:${SURELOG_DIR}/tests/UnitDefParam/top.v, line:26:1, endln:26:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[2]) |vpiName:N1 @@ -2866,8 +2866,8 @@ design: (work@top_def) |vpiLocalParam:1 |vpiName:j |vpiFullName:work@small_top.u1.B1[2].B2[0].j - |vpiModule: - \_module: work@small_top.u1.B1[2].B2[0]::M2 (work@small_top.u1.B1[2].B2[0].N2), file:${SURELOG_DIR}/tests/UnitDefParam/top.v, line:32:1, endln:32:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[2].B2[0]::M2 (work@small_top.u1.B1[2].B2[0].N2), file:${SURELOG_DIR}/tests/UnitDefParam/top.v, line:32:1, endln:32:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[2].B2[0]) |vpiName:N2 @@ -2894,8 +2894,8 @@ design: (work@top_def) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[2].B2[0].B3[0].k - |vpiModule: - \_module: work@small_top.u1.B1[2].B2[0].B3[0]::M3 (work@small_top.u1.B1[2].B2[0].B3[0].N3), file:${SURELOG_DIR}/tests/UnitDefParam/top.v, line:39:1, endln:39:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[2].B2[0].B3[0]::M3 (work@small_top.u1.B1[2].B2[0].B3[0].N3), file:${SURELOG_DIR}/tests/UnitDefParam/top.v, line:39:1, endln:39:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[2].B2[0].B3[0]) |vpiName:N3 @@ -2922,8 +2922,8 @@ design: (work@top_def) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[2].B2[0].B3[1].k - |vpiModule: - \_module: work@small_top.u1.B1[2].B2[0].B3[1]::M3 (work@small_top.u1.B1[2].B2[0].B3[1].N3), file:${SURELOG_DIR}/tests/UnitDefParam/top.v, line:39:1, endln:39:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[2].B2[0].B3[1]::M3 (work@small_top.u1.B1[2].B2[0].B3[1].N3), file:${SURELOG_DIR}/tests/UnitDefParam/top.v, line:39:1, endln:39:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[2].B2[0].B3[1]) |vpiName:N3 @@ -2950,8 +2950,8 @@ design: (work@top_def) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[2].B2[0].B3[2].k - |vpiModule: - \_module: work@small_top.u1.B1[2].B2[0].B3[2]::M3 (work@small_top.u1.B1[2].B2[0].B3[2].N3), file:${SURELOG_DIR}/tests/UnitDefParam/top.v, line:39:1, endln:39:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[2].B2[0].B3[2]::M3 (work@small_top.u1.B1[2].B2[0].B3[2].N3), file:${SURELOG_DIR}/tests/UnitDefParam/top.v, line:39:1, endln:39:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[2].B2[0].B3[2]) |vpiName:N3 @@ -2978,8 +2978,8 @@ design: (work@top_def) |vpiLocalParam:1 |vpiName:j |vpiFullName:work@small_top.u1.B1[2].B2[1].j - |vpiModule: - \_module: work@small_top.u1.B1[2].B2[1]::M2 (work@small_top.u1.B1[2].B2[1].N2), file:${SURELOG_DIR}/tests/UnitDefParam/top.v, line:32:1, endln:32:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[2].B2[1]::M2 (work@small_top.u1.B1[2].B2[1].N2), file:${SURELOG_DIR}/tests/UnitDefParam/top.v, line:32:1, endln:32:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[2].B2[1]) |vpiName:N2 @@ -3006,8 +3006,8 @@ design: (work@top_def) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[2].B2[1].B3[0].k - |vpiModule: - \_module: work@small_top.u1.B1[2].B2[1].B3[0]::M3 (work@small_top.u1.B1[2].B2[1].B3[0].N3), file:${SURELOG_DIR}/tests/UnitDefParam/top.v, line:39:1, endln:39:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[2].B2[1].B3[0]::M3 (work@small_top.u1.B1[2].B2[1].B3[0].N3), file:${SURELOG_DIR}/tests/UnitDefParam/top.v, line:39:1, endln:39:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[2].B2[1].B3[0]) |vpiName:N3 @@ -3034,8 +3034,8 @@ design: (work@top_def) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[2].B2[1].B3[1].k - |vpiModule: - \_module: work@small_top.u1.B1[2].B2[1].B3[1]::M3 (work@small_top.u1.B1[2].B2[1].B3[1].N3), file:${SURELOG_DIR}/tests/UnitDefParam/top.v, line:39:1, endln:39:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[2].B2[1].B3[1]::M3 (work@small_top.u1.B1[2].B2[1].B3[1].N3), file:${SURELOG_DIR}/tests/UnitDefParam/top.v, line:39:1, endln:39:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[2].B2[1].B3[1]) |vpiName:N3 @@ -3062,8 +3062,8 @@ design: (work@top_def) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[2].B2[1].B3[2].k - |vpiModule: - \_module: work@small_top.u1.B1[2].B2[1].B3[2]::M3 (work@small_top.u1.B1[2].B2[1].B3[2].N3), file:${SURELOG_DIR}/tests/UnitDefParam/top.v, line:39:1, endln:39:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[2].B2[1].B3[2]::M3 (work@small_top.u1.B1[2].B2[1].B3[2].N3), file:${SURELOG_DIR}/tests/UnitDefParam/top.v, line:39:1, endln:39:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[2].B2[1].B3[2]) |vpiName:N3 @@ -3090,8 +3090,8 @@ design: (work@top_def) |vpiLocalParam:1 |vpiName:j |vpiFullName:work@small_top.u1.B1[2].B2[2].j - |vpiModule: - \_module: work@small_top.u1.B1[2].B2[2]::M2 (work@small_top.u1.B1[2].B2[2].N2), file:${SURELOG_DIR}/tests/UnitDefParam/top.v, line:32:1, endln:32:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[2].B2[2]::M2 (work@small_top.u1.B1[2].B2[2].N2), file:${SURELOG_DIR}/tests/UnitDefParam/top.v, line:32:1, endln:32:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[2].B2[2]) |vpiName:N2 @@ -3118,8 +3118,8 @@ design: (work@top_def) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[2].B2[2].B3[0].k - |vpiModule: - \_module: work@small_top.u1.B1[2].B2[2].B3[0]::M3 (work@small_top.u1.B1[2].B2[2].B3[0].N3), file:${SURELOG_DIR}/tests/UnitDefParam/top.v, line:39:1, endln:39:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[2].B2[2].B3[0]::M3 (work@small_top.u1.B1[2].B2[2].B3[0].N3), file:${SURELOG_DIR}/tests/UnitDefParam/top.v, line:39:1, endln:39:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[2].B2[2].B3[0]) |vpiName:N3 @@ -3146,8 +3146,8 @@ design: (work@top_def) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[2].B2[2].B3[1].k - |vpiModule: - \_module: work@small_top.u1.B1[2].B2[2].B3[1]::M3 (work@small_top.u1.B1[2].B2[2].B3[1].N3), file:${SURELOG_DIR}/tests/UnitDefParam/top.v, line:39:1, endln:39:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[2].B2[2].B3[1]::M3 (work@small_top.u1.B1[2].B2[2].B3[1].N3), file:${SURELOG_DIR}/tests/UnitDefParam/top.v, line:39:1, endln:39:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[2].B2[2].B3[1]) |vpiName:N3 @@ -3174,8 +3174,8 @@ design: (work@top_def) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[2].B2[2].B3[2].k - |vpiModule: - \_module: work@small_top.u1.B1[2].B2[2].B3[2]::M3 (work@small_top.u1.B1[2].B2[2].B3[2].N3), file:${SURELOG_DIR}/tests/UnitDefParam/top.v, line:39:1, endln:39:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[2].B2[2].B3[2]::M3 (work@small_top.u1.B1[2].B2[2].B3[2].N3), file:${SURELOG_DIR}/tests/UnitDefParam/top.v, line:39:1, endln:39:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[2].B2[2].B3[2]) |vpiName:N3 @@ -3213,8 +3213,8 @@ design: (work@top_def) |vpiLocalParam:1 |vpiName:m |vpiFullName:work@small_top.u1.B1[2].B4.B5[0].m - |vpiModule: - \_module: work@small_top.u1.B1[2].B4.B5[0]::M4 (work@small_top.u1.B1[2].B4.B5[0].N4), file:${SURELOG_DIR}/tests/UnitDefParam/top.v, line:52:1, endln:52:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[2].B4.B5[0]::M4 (work@small_top.u1.B1[2].B4.B5[0].N4), file:${SURELOG_DIR}/tests/UnitDefParam/top.v, line:52:1, endln:52:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[2].B4.B5[0]) |vpiName:N4 @@ -3241,8 +3241,8 @@ design: (work@top_def) |vpiLocalParam:1 |vpiName:m |vpiFullName:work@small_top.u1.B1[2].B4.B5[1].m - |vpiModule: - \_module: work@small_top.u1.B1[2].B4.B5[1]::M4 (work@small_top.u1.B1[2].B4.B5[1].N4), file:${SURELOG_DIR}/tests/UnitDefParam/top.v, line:52:1, endln:52:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[2].B4.B5[1]::M4 (work@small_top.u1.B1[2].B4.B5[1].N4), file:${SURELOG_DIR}/tests/UnitDefParam/top.v, line:52:1, endln:52:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[2].B4.B5[1]) |vpiName:N4 @@ -3269,29 +3269,29 @@ design: (work@top_def) |vpiLocalParam:1 |vpiName:m |vpiFullName:work@small_top.u1.B1[2].B4.B5[2].m - |vpiModule: - \_module: work@small_top.u1.B1[2].B4.B5[2]::M4 (work@small_top.u1.B1[2].B4.B5[2].N4), file:${SURELOG_DIR}/tests/UnitDefParam/top.v, line:52:1, endln:52:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[2].B4.B5[2]::M4 (work@small_top.u1.B1[2].B4.B5[2].N4), file:${SURELOG_DIR}/tests/UnitDefParam/top.v, line:52:1, endln:52:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[2].B4.B5[2]) |vpiName:N4 |vpiFullName:work@small_top.u1.B1[2].B4.B5[2].N4 |vpiDefName:work@small_top.u1.B1[2].B4.B5[2]::M4 |uhdmtopModules: -\_module: work@defparam_example (work@defparam_example), file:${SURELOG_DIR}/tests/UnitDefParam/small.v, line:14:1, endln:27:10 +\_module_inst: work@defparam_example (work@defparam_example), file:${SURELOG_DIR}/tests/UnitDefParam/small.v, line:14:1, endln:27:10 |vpiName:work@defparam_example |vpiDefName:work@defparam_example |vpiTop:1 |vpiTopModule:1 - |vpiModule: - \_module: work@secret_number (work@defparam_example.U0), file:${SURELOG_DIR}/tests/UnitDefParam/small.v, line:19:3, endln:19:22 + |vpiModuleInst: + \_module_inst: work@secret_number (work@defparam_example.U0), file:${SURELOG_DIR}/tests/UnitDefParam/small.v, line:19:3, endln:19:22 |vpiParent: - \_module: work@defparam_example (work@defparam_example), file:${SURELOG_DIR}/tests/UnitDefParam/small.v, line:14:1, endln:27:10 + \_module_inst: work@defparam_example (work@defparam_example), file:${SURELOG_DIR}/tests/UnitDefParam/small.v, line:14:1, endln:27:10 |vpiName:U0 |vpiFullName:work@defparam_example.U0 |vpiParameter: \_parameter: (work@defparam_example.U0.SIZE), line:3:12, endln:3:16 |vpiParent: - \_module: work@secret_number (work@defparam_example.U0), file:${SURELOG_DIR}/tests/UnitDefParam/small.v, line:19:3, endln:19:22 + \_module_inst: work@secret_number (work@defparam_example.U0), file:${SURELOG_DIR}/tests/UnitDefParam/small.v, line:19:3, endln:19:22 |UINT:0 |vpiTypespec: \_int_typespec: @@ -3302,7 +3302,7 @@ design: (work@top_def) |vpiParamAssign: \_param_assign: , line:3:12, endln:3:20 |vpiParent: - \_module: work@secret_number (work@defparam_example.U0), file:${SURELOG_DIR}/tests/UnitDefParam/small.v, line:19:3, endln:19:22 + \_module_inst: work@secret_number (work@defparam_example.U0), file:${SURELOG_DIR}/tests/UnitDefParam/small.v, line:19:3, endln:19:22 |vpiRhs: \_constant: , line:3:19, endln:3:20 |vpiDecompile:0 @@ -3317,17 +3317,17 @@ design: (work@top_def) |vpiDefFile:${SURELOG_DIR}/tests/UnitDefParam/small.v |vpiDefLineNo:2 |vpiInstance: - \_module: work@defparam_example (work@defparam_example), file:${SURELOG_DIR}/tests/UnitDefParam/small.v, line:14:1, endln:27:10 - |vpiModule: - \_module: work@secret_number (work@defparam_example.U1), file:${SURELOG_DIR}/tests/UnitDefParam/small.v, line:20:3, endln:20:22 + \_module_inst: work@defparam_example (work@defparam_example), file:${SURELOG_DIR}/tests/UnitDefParam/small.v, line:14:1, endln:27:10 + |vpiModuleInst: + \_module_inst: work@secret_number (work@defparam_example.U1), file:${SURELOG_DIR}/tests/UnitDefParam/small.v, line:20:3, endln:20:22 |vpiParent: - \_module: work@defparam_example (work@defparam_example), file:${SURELOG_DIR}/tests/UnitDefParam/small.v, line:14:1, endln:27:10 + \_module_inst: work@defparam_example (work@defparam_example), file:${SURELOG_DIR}/tests/UnitDefParam/small.v, line:14:1, endln:27:10 |vpiName:U1 |vpiFullName:work@defparam_example.U1 |vpiParameter: \_parameter: (work@defparam_example.U1.SIZE), line:3:12, endln:3:16 |vpiParent: - \_module: work@secret_number (work@defparam_example.U1), file:${SURELOG_DIR}/tests/UnitDefParam/small.v, line:20:3, endln:20:22 + \_module_inst: work@secret_number (work@defparam_example.U1), file:${SURELOG_DIR}/tests/UnitDefParam/small.v, line:20:3, endln:20:22 |UINT:0 |vpiTypespec: \_int_typespec: @@ -3338,7 +3338,7 @@ design: (work@top_def) |vpiParamAssign: \_param_assign: , line:3:12, endln:3:20 |vpiParent: - \_module: work@secret_number (work@defparam_example.U1), file:${SURELOG_DIR}/tests/UnitDefParam/small.v, line:20:3, endln:20:22 + \_module_inst: work@secret_number (work@defparam_example.U1), file:${SURELOG_DIR}/tests/UnitDefParam/small.v, line:20:3, endln:20:22 |vpiRhs: \_constant: , line:3:19, endln:3:20 |vpiDecompile:1 @@ -3353,11 +3353,11 @@ design: (work@top_def) |vpiDefFile:${SURELOG_DIR}/tests/UnitDefParam/small.v |vpiDefLineNo:2 |vpiInstance: - \_module: work@defparam_example (work@defparam_example), file:${SURELOG_DIR}/tests/UnitDefParam/small.v, line:14:1, endln:27:10 + \_module_inst: work@defparam_example (work@defparam_example), file:${SURELOG_DIR}/tests/UnitDefParam/small.v, line:14:1, endln:27:10 |vpiGenScopeArray: \_gen_scope_array: (work@defparam_example.U1.B1[0]), line:6:36, endln:8:5 |vpiParent: - \_module: work@secret_number (work@defparam_example.U1), file:${SURELOG_DIR}/tests/UnitDefParam/small.v, line:20:3, endln:20:22 + \_module_inst: work@secret_number (work@defparam_example.U1), file:${SURELOG_DIR}/tests/UnitDefParam/small.v, line:20:3, endln:20:22 |vpiName:B1[0] |vpiFullName:work@defparam_example.U1.B1[0] |vpiGenScope: @@ -3375,23 +3375,23 @@ design: (work@top_def) |vpiLocalParam:1 |vpiName:i |vpiFullName:work@defparam_example.U1.B1[0].i - |vpiModule: - \_module: work@defparam_example.U1.B1[0]::M1 (work@defparam_example.U1.B1[0].N1), file:${SURELOG_DIR}/tests/UnitDefParam/small.v, line:7:3, endln:7:11 + |vpiModuleInst: + \_module_inst: work@defparam_example.U1.B1[0]::M1 (work@defparam_example.U1.B1[0].N1), file:${SURELOG_DIR}/tests/UnitDefParam/small.v, line:7:3, endln:7:11 |vpiParent: \_gen_scope: (work@defparam_example.U1.B1[0]) |vpiName:N1 |vpiFullName:work@defparam_example.U1.B1[0].N1 |vpiDefName:work@defparam_example.U1.B1[0]::M1 - |vpiModule: - \_module: work@secret_number (work@defparam_example.U2), file:${SURELOG_DIR}/tests/UnitDefParam/small.v, line:21:3, endln:21:22 + |vpiModuleInst: + \_module_inst: work@secret_number (work@defparam_example.U2), file:${SURELOG_DIR}/tests/UnitDefParam/small.v, line:21:3, endln:21:22 |vpiParent: - \_module: work@defparam_example (work@defparam_example), file:${SURELOG_DIR}/tests/UnitDefParam/small.v, line:14:1, endln:27:10 + \_module_inst: work@defparam_example (work@defparam_example), file:${SURELOG_DIR}/tests/UnitDefParam/small.v, line:14:1, endln:27:10 |vpiName:U2 |vpiFullName:work@defparam_example.U2 |vpiParameter: \_parameter: (work@defparam_example.U2.SIZE), line:3:12, endln:3:16 |vpiParent: - \_module: work@secret_number (work@defparam_example.U2), file:${SURELOG_DIR}/tests/UnitDefParam/small.v, line:21:3, endln:21:22 + \_module_inst: work@secret_number (work@defparam_example.U2), file:${SURELOG_DIR}/tests/UnitDefParam/small.v, line:21:3, endln:21:22 |UINT:0 |vpiTypespec: \_int_typespec: @@ -3402,7 +3402,7 @@ design: (work@top_def) |vpiParamAssign: \_param_assign: , line:3:12, endln:3:20 |vpiParent: - \_module: work@secret_number (work@defparam_example.U2), file:${SURELOG_DIR}/tests/UnitDefParam/small.v, line:21:3, endln:21:22 + \_module_inst: work@secret_number (work@defparam_example.U2), file:${SURELOG_DIR}/tests/UnitDefParam/small.v, line:21:3, endln:21:22 |vpiRhs: \_constant: , line:3:19, endln:3:20 |vpiDecompile:2 @@ -3417,11 +3417,11 @@ design: (work@top_def) |vpiDefFile:${SURELOG_DIR}/tests/UnitDefParam/small.v |vpiDefLineNo:2 |vpiInstance: - \_module: work@defparam_example (work@defparam_example), file:${SURELOG_DIR}/tests/UnitDefParam/small.v, line:14:1, endln:27:10 + \_module_inst: work@defparam_example (work@defparam_example), file:${SURELOG_DIR}/tests/UnitDefParam/small.v, line:14:1, endln:27:10 |vpiGenScopeArray: \_gen_scope_array: (work@defparam_example.U2.B1[0]), line:6:36, endln:8:5 |vpiParent: - \_module: work@secret_number (work@defparam_example.U2), file:${SURELOG_DIR}/tests/UnitDefParam/small.v, line:21:3, endln:21:22 + \_module_inst: work@secret_number (work@defparam_example.U2), file:${SURELOG_DIR}/tests/UnitDefParam/small.v, line:21:3, endln:21:22 |vpiName:B1[0] |vpiFullName:work@defparam_example.U2.B1[0] |vpiGenScope: @@ -3439,8 +3439,8 @@ design: (work@top_def) |vpiLocalParam:1 |vpiName:i |vpiFullName:work@defparam_example.U2.B1[0].i - |vpiModule: - \_module: work@defparam_example.U2.B1[0]::M1 (work@defparam_example.U2.B1[0].N1), file:${SURELOG_DIR}/tests/UnitDefParam/small.v, line:7:3, endln:7:11 + |vpiModuleInst: + \_module_inst: work@defparam_example.U2.B1[0]::M1 (work@defparam_example.U2.B1[0].N1), file:${SURELOG_DIR}/tests/UnitDefParam/small.v, line:7:3, endln:7:11 |vpiParent: \_gen_scope: (work@defparam_example.U2.B1[0]) |vpiName:N1 @@ -3449,7 +3449,7 @@ design: (work@top_def) |vpiGenScopeArray: \_gen_scope_array: (work@defparam_example.U2.B1[1]), line:6:36, endln:8:5 |vpiParent: - \_module: work@secret_number (work@defparam_example.U2), file:${SURELOG_DIR}/tests/UnitDefParam/small.v, line:21:3, endln:21:22 + \_module_inst: work@secret_number (work@defparam_example.U2), file:${SURELOG_DIR}/tests/UnitDefParam/small.v, line:21:3, endln:21:22 |vpiName:B1[1] |vpiFullName:work@defparam_example.U2.B1[1] |vpiGenScope: @@ -3467,23 +3467,23 @@ design: (work@top_def) |vpiLocalParam:1 |vpiName:i |vpiFullName:work@defparam_example.U2.B1[1].i - |vpiModule: - \_module: work@defparam_example.U2.B1[1]::M1 (work@defparam_example.U2.B1[1].N1), file:${SURELOG_DIR}/tests/UnitDefParam/small.v, line:7:3, endln:7:11 + |vpiModuleInst: + \_module_inst: work@defparam_example.U2.B1[1]::M1 (work@defparam_example.U2.B1[1].N1), file:${SURELOG_DIR}/tests/UnitDefParam/small.v, line:7:3, endln:7:11 |vpiParent: \_gen_scope: (work@defparam_example.U2.B1[1]) |vpiName:N1 |vpiFullName:work@defparam_example.U2.B1[1].N1 |vpiDefName:work@defparam_example.U2.B1[1]::M1 - |vpiModule: - \_module: work@secret_number (work@defparam_example.U3), file:${SURELOG_DIR}/tests/UnitDefParam/small.v, line:22:3, endln:22:22 + |vpiModuleInst: + \_module_inst: work@secret_number (work@defparam_example.U3), file:${SURELOG_DIR}/tests/UnitDefParam/small.v, line:22:3, endln:22:22 |vpiParent: - \_module: work@defparam_example (work@defparam_example), file:${SURELOG_DIR}/tests/UnitDefParam/small.v, line:14:1, endln:27:10 + \_module_inst: work@defparam_example (work@defparam_example), file:${SURELOG_DIR}/tests/UnitDefParam/small.v, line:14:1, endln:27:10 |vpiName:U3 |vpiFullName:work@defparam_example.U3 |vpiParameter: \_parameter: (work@defparam_example.U3.SIZE), line:3:12, endln:3:16 |vpiParent: - \_module: work@secret_number (work@defparam_example.U3), file:${SURELOG_DIR}/tests/UnitDefParam/small.v, line:22:3, endln:22:22 + \_module_inst: work@secret_number (work@defparam_example.U3), file:${SURELOG_DIR}/tests/UnitDefParam/small.v, line:22:3, endln:22:22 |UINT:0 |vpiTypespec: \_int_typespec: @@ -3494,7 +3494,7 @@ design: (work@top_def) |vpiParamAssign: \_param_assign: , line:3:12, endln:3:20 |vpiParent: - \_module: work@secret_number (work@defparam_example.U3), file:${SURELOG_DIR}/tests/UnitDefParam/small.v, line:22:3, endln:22:22 + \_module_inst: work@secret_number (work@defparam_example.U3), file:${SURELOG_DIR}/tests/UnitDefParam/small.v, line:22:3, endln:22:22 |vpiRhs: \_constant: , line:3:19, endln:3:20 |vpiDecompile:3 @@ -3509,11 +3509,11 @@ design: (work@top_def) |vpiDefFile:${SURELOG_DIR}/tests/UnitDefParam/small.v |vpiDefLineNo:2 |vpiInstance: - \_module: work@defparam_example (work@defparam_example), file:${SURELOG_DIR}/tests/UnitDefParam/small.v, line:14:1, endln:27:10 + \_module_inst: work@defparam_example (work@defparam_example), file:${SURELOG_DIR}/tests/UnitDefParam/small.v, line:14:1, endln:27:10 |vpiGenScopeArray: \_gen_scope_array: (work@defparam_example.U3.B1[0]), line:6:36, endln:8:5 |vpiParent: - \_module: work@secret_number (work@defparam_example.U3), file:${SURELOG_DIR}/tests/UnitDefParam/small.v, line:22:3, endln:22:22 + \_module_inst: work@secret_number (work@defparam_example.U3), file:${SURELOG_DIR}/tests/UnitDefParam/small.v, line:22:3, endln:22:22 |vpiName:B1[0] |vpiFullName:work@defparam_example.U3.B1[0] |vpiGenScope: @@ -3531,8 +3531,8 @@ design: (work@top_def) |vpiLocalParam:1 |vpiName:i |vpiFullName:work@defparam_example.U3.B1[0].i - |vpiModule: - \_module: work@defparam_example.U3.B1[0]::M1 (work@defparam_example.U3.B1[0].N1), file:${SURELOG_DIR}/tests/UnitDefParam/small.v, line:7:3, endln:7:11 + |vpiModuleInst: + \_module_inst: work@defparam_example.U3.B1[0]::M1 (work@defparam_example.U3.B1[0].N1), file:${SURELOG_DIR}/tests/UnitDefParam/small.v, line:7:3, endln:7:11 |vpiParent: \_gen_scope: (work@defparam_example.U3.B1[0]) |vpiName:N1 @@ -3541,7 +3541,7 @@ design: (work@top_def) |vpiGenScopeArray: \_gen_scope_array: (work@defparam_example.U3.B1[1]), line:6:36, endln:8:5 |vpiParent: - \_module: work@secret_number (work@defparam_example.U3), file:${SURELOG_DIR}/tests/UnitDefParam/small.v, line:22:3, endln:22:22 + \_module_inst: work@secret_number (work@defparam_example.U3), file:${SURELOG_DIR}/tests/UnitDefParam/small.v, line:22:3, endln:22:22 |vpiName:B1[1] |vpiFullName:work@defparam_example.U3.B1[1] |vpiGenScope: @@ -3559,8 +3559,8 @@ design: (work@top_def) |vpiLocalParam:1 |vpiName:i |vpiFullName:work@defparam_example.U3.B1[1].i - |vpiModule: - \_module: work@defparam_example.U3.B1[1]::M1 (work@defparam_example.U3.B1[1].N1), file:${SURELOG_DIR}/tests/UnitDefParam/small.v, line:7:3, endln:7:11 + |vpiModuleInst: + \_module_inst: work@defparam_example.U3.B1[1]::M1 (work@defparam_example.U3.B1[1].N1), file:${SURELOG_DIR}/tests/UnitDefParam/small.v, line:7:3, endln:7:11 |vpiParent: \_gen_scope: (work@defparam_example.U3.B1[1]) |vpiName:N1 @@ -3569,7 +3569,7 @@ design: (work@top_def) |vpiGenScopeArray: \_gen_scope_array: (work@defparam_example.U3.B1[2]), line:6:36, endln:8:5 |vpiParent: - \_module: work@secret_number (work@defparam_example.U3), file:${SURELOG_DIR}/tests/UnitDefParam/small.v, line:22:3, endln:22:22 + \_module_inst: work@secret_number (work@defparam_example.U3), file:${SURELOG_DIR}/tests/UnitDefParam/small.v, line:22:3, endln:22:22 |vpiName:B1[2] |vpiFullName:work@defparam_example.U3.B1[2] |vpiGenScope: @@ -3587,22 +3587,22 @@ design: (work@top_def) |vpiLocalParam:1 |vpiName:i |vpiFullName:work@defparam_example.U3.B1[2].i - |vpiModule: - \_module: work@defparam_example.U3.B1[2]::M1 (work@defparam_example.U3.B1[2].N1), file:${SURELOG_DIR}/tests/UnitDefParam/small.v, line:7:3, endln:7:11 + |vpiModuleInst: + \_module_inst: work@defparam_example.U3.B1[2]::M1 (work@defparam_example.U3.B1[2].N1), file:${SURELOG_DIR}/tests/UnitDefParam/small.v, line:7:3, endln:7:11 |vpiParent: \_gen_scope: (work@defparam_example.U3.B1[2]) |vpiName:N1 |vpiFullName:work@defparam_example.U3.B1[2].N1 |vpiDefName:work@defparam_example.U3.B1[2]::M1 - |vpiModule: - \_module: work@defparam_example::NO_DEF (work@defparam_example.U5), file:${SURELOG_DIR}/tests/UnitDefParam/small.v, line:23:3, endln:23:15 + |vpiModuleInst: + \_module_inst: work@defparam_example::NO_DEF (work@defparam_example.U5), file:${SURELOG_DIR}/tests/UnitDefParam/small.v, line:23:3, endln:23:15 |vpiParent: - \_module: work@defparam_example (work@defparam_example), file:${SURELOG_DIR}/tests/UnitDefParam/small.v, line:14:1, endln:27:10 + \_module_inst: work@defparam_example (work@defparam_example), file:${SURELOG_DIR}/tests/UnitDefParam/small.v, line:14:1, endln:27:10 |vpiName:U5 |vpiFullName:work@defparam_example.U5 |vpiDefName:work@defparam_example::NO_DEF |vpiInstance: - \_module: work@defparam_example (work@defparam_example), file:${SURELOG_DIR}/tests/UnitDefParam/small.v, line:14:1, endln:27:10 + \_module_inst: work@defparam_example (work@defparam_example), file:${SURELOG_DIR}/tests/UnitDefParam/small.v, line:14:1, endln:27:10 =================== [ FATAL] : 0 [ SYNTAX] : 0 diff --git a/tests/UnitElab/UnitElab.log b/tests/UnitElab/UnitElab.log index b7c75b65b8..a7480b597f 100644 --- a/tests/UnitElab/UnitElab.log +++ b/tests/UnitElab/UnitElab.log @@ -13585,8 +13585,8 @@ io_decl 11 logic_net 105 logic_typespec 134 logic_var 1 -module 1274 module_array 1 +module_inst 1274 module_typespec 1 operation 1360 package 2 @@ -14020,7 +14020,7 @@ design: (work@bottom1) \_int_typespec: |vpiSigned:1 |uhdmallModules: -\_module: work@bottom1 (work@bottom1), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:1:1, endln:4:10 +\_module_inst: work@bottom1 (work@bottom1), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:1:1, endln:4:10 |vpiParent: \_design: (work@bottom1) |vpiFullName:work@bottom1 @@ -14028,19 +14028,19 @@ design: (work@bottom1) |vpiNet: \_logic_net: (work@bottom1.a), line:1:23, endln:1:24 |vpiParent: - \_module: work@bottom1 (work@bottom1), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:1:1, endln:4:10 + \_module_inst: work@bottom1 (work@bottom1), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:1:1, endln:4:10 |vpiName:a |vpiFullName:work@bottom1.a |vpiNet: \_logic_net: (work@bottom1.b), line:1:32, endln:1:33 |vpiParent: - \_module: work@bottom1 (work@bottom1), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:1:1, endln:4:10 + \_module_inst: work@bottom1 (work@bottom1), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:1:1, endln:4:10 |vpiName:b |vpiFullName:work@bottom1.b |vpiPort: \_port: (a), line:1:23, endln:1:24 |vpiParent: - \_module: work@bottom1 (work@bottom1), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:1:1, endln:4:10 + \_module_inst: work@bottom1 (work@bottom1), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:1:1, endln:4:10 |vpiName:a |vpiDirection:1 |vpiLowConn: @@ -14052,7 +14052,7 @@ design: (work@bottom1) |vpiPort: \_port: (b), line:1:32, endln:1:33 |vpiParent: - \_module: work@bottom1 (work@bottom1), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:1:1, endln:4:10 + \_module_inst: work@bottom1 (work@bottom1), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:1:1, endln:4:10 |vpiName:b |vpiDirection:1 |vpiLowConn: @@ -14062,7 +14062,7 @@ design: (work@bottom1) |vpiTypedef: \_logic_typespec: , line:1:32, endln:1:32 |uhdmallModules: -\_module: work@bottom2 (work@bottom2), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:6:1, endln:8:10 +\_module_inst: work@bottom2 (work@bottom2), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:6:1, endln:8:10 |vpiParent: \_design: (work@bottom1) |vpiFullName:work@bottom2 @@ -14070,19 +14070,19 @@ design: (work@bottom1) |vpiNet: \_logic_net: (work@bottom2.a), line:6:23, endln:6:24 |vpiParent: - \_module: work@bottom2 (work@bottom2), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:6:1, endln:8:10 + \_module_inst: work@bottom2 (work@bottom2), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:6:1, endln:8:10 |vpiName:a |vpiFullName:work@bottom2.a |vpiNet: \_logic_net: (work@bottom2.b), line:6:32, endln:6:33 |vpiParent: - \_module: work@bottom2 (work@bottom2), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:6:1, endln:8:10 + \_module_inst: work@bottom2 (work@bottom2), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:6:1, endln:8:10 |vpiName:b |vpiFullName:work@bottom2.b |vpiPort: \_port: (a), line:6:23, endln:6:24 |vpiParent: - \_module: work@bottom2 (work@bottom2), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:6:1, endln:8:10 + \_module_inst: work@bottom2 (work@bottom2), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:6:1, endln:8:10 |vpiName:a |vpiDirection:1 |vpiLowConn: @@ -14094,7 +14094,7 @@ design: (work@bottom1) |vpiPort: \_port: (b), line:6:32, endln:6:33 |vpiParent: - \_module: work@bottom2 (work@bottom2), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:6:1, endln:8:10 + \_module_inst: work@bottom2 (work@bottom2), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:6:1, endln:8:10 |vpiName:b |vpiDirection:1 |vpiLowConn: @@ -14104,7 +14104,7 @@ design: (work@bottom1) |vpiTypedef: \_logic_typespec: , line:6:32, endln:6:32 |uhdmallModules: -\_module: work@bottom4 (work@bottom4), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:11:1, endln:13:10 +\_module_inst: work@bottom4 (work@bottom4), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:11:1, endln:13:10 |vpiParent: \_design: (work@bottom1) |vpiFullName:work@bottom4 @@ -14112,19 +14112,19 @@ design: (work@bottom1) |vpiNet: \_logic_net: (work@bottom4.a), line:11:23, endln:11:24 |vpiParent: - \_module: work@bottom4 (work@bottom4), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:11:1, endln:13:10 + \_module_inst: work@bottom4 (work@bottom4), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:11:1, endln:13:10 |vpiName:a |vpiFullName:work@bottom4.a |vpiNet: \_logic_net: (work@bottom4.b), line:11:32, endln:11:33 |vpiParent: - \_module: work@bottom4 (work@bottom4), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:11:1, endln:13:10 + \_module_inst: work@bottom4 (work@bottom4), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:11:1, endln:13:10 |vpiName:b |vpiFullName:work@bottom4.b |vpiPort: \_port: (a), line:11:23, endln:11:24 |vpiParent: - \_module: work@bottom4 (work@bottom4), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:11:1, endln:13:10 + \_module_inst: work@bottom4 (work@bottom4), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:11:1, endln:13:10 |vpiName:a |vpiDirection:1 |vpiLowConn: @@ -14136,7 +14136,7 @@ design: (work@bottom1) |vpiPort: \_port: (b), line:11:32, endln:11:33 |vpiParent: - \_module: work@bottom4 (work@bottom4), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:11:1, endln:13:10 + \_module_inst: work@bottom4 (work@bottom4), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:11:1, endln:13:10 |vpiName:b |vpiDirection:1 |vpiLowConn: @@ -14146,7 +14146,7 @@ design: (work@bottom1) |vpiTypedef: \_logic_typespec: , line:11:32, endln:11:32 |uhdmallModules: -\_module: work@bottom5 (work@bottom5), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:16:1, endln:17:10 +\_module_inst: work@bottom5 (work@bottom5), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:16:1, endln:17:10 |vpiParent: \_design: (work@bottom1) |vpiFullName:work@bottom5 @@ -14154,19 +14154,19 @@ design: (work@bottom1) |vpiNet: \_logic_net: (work@bottom5.a), line:16:23, endln:16:24 |vpiParent: - \_module: work@bottom5 (work@bottom5), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:16:1, endln:17:10 + \_module_inst: work@bottom5 (work@bottom5), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:16:1, endln:17:10 |vpiName:a |vpiFullName:work@bottom5.a |vpiNet: \_logic_net: (work@bottom5.b), line:16:32, endln:16:33 |vpiParent: - \_module: work@bottom5 (work@bottom5), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:16:1, endln:17:10 + \_module_inst: work@bottom5 (work@bottom5), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:16:1, endln:17:10 |vpiName:b |vpiFullName:work@bottom5.b |vpiPort: \_port: (a), line:16:23, endln:16:24 |vpiParent: - \_module: work@bottom5 (work@bottom5), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:16:1, endln:17:10 + \_module_inst: work@bottom5 (work@bottom5), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:16:1, endln:17:10 |vpiName:a |vpiDirection:1 |vpiLowConn: @@ -14178,7 +14178,7 @@ design: (work@bottom1) |vpiPort: \_port: (b), line:16:32, endln:16:33 |vpiParent: - \_module: work@bottom5 (work@bottom5), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:16:1, endln:17:10 + \_module_inst: work@bottom5 (work@bottom5), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:16:1, endln:17:10 |vpiName:b |vpiDirection:1 |vpiLowConn: @@ -14188,7 +14188,7 @@ design: (work@bottom1) |vpiTypedef: \_logic_typespec: , line:16:32, endln:16:32 |uhdmallModules: -\_module: work@my_module (work@my_module), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:20:1, endln:24:10 +\_module_inst: work@my_module (work@my_module), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:20:1, endln:24:10 |vpiParent: \_design: (work@bottom1) |vpiFullName:work@my_module @@ -14196,25 +14196,25 @@ design: (work@bottom1) |vpiNet: \_logic_net: (work@my_module.a), line:20:19, endln:20:20 |vpiParent: - \_module: work@my_module (work@my_module), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:20:1, endln:24:10 + \_module_inst: work@my_module (work@my_module), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:20:1, endln:24:10 |vpiName:a |vpiFullName:work@my_module.a |vpiNet: \_logic_net: (work@my_module.b), line:20:22, endln:20:23 |vpiParent: - \_module: work@my_module (work@my_module), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:20:1, endln:24:10 + \_module_inst: work@my_module (work@my_module), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:20:1, endln:24:10 |vpiName:b |vpiFullName:work@my_module.b |vpiNet: \_logic_net: (work@my_module.c), line:20:25, endln:20:26 |vpiParent: - \_module: work@my_module (work@my_module), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:20:1, endln:24:10 + \_module_inst: work@my_module (work@my_module), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:20:1, endln:24:10 |vpiName:c |vpiFullName:work@my_module.c |vpiPort: \_port: (a), line:20:19, endln:20:20 |vpiParent: - \_module: work@my_module (work@my_module), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:20:1, endln:24:10 + \_module_inst: work@my_module (work@my_module), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:20:1, endln:24:10 |vpiName:a |vpiDirection:1 |vpiLowConn: @@ -14226,7 +14226,7 @@ design: (work@bottom1) |vpiPort: \_port: (b), line:20:22, endln:20:23 |vpiParent: - \_module: work@my_module (work@my_module), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:20:1, endln:24:10 + \_module_inst: work@my_module (work@my_module), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:20:1, endln:24:10 |vpiName:b |vpiDirection:1 |vpiLowConn: @@ -14238,7 +14238,7 @@ design: (work@bottom1) |vpiPort: \_port: (c), line:20:25, endln:20:26 |vpiParent: - \_module: work@my_module (work@my_module), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:20:1, endln:24:10 + \_module_inst: work@my_module (work@my_module), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:20:1, endln:24:10 |vpiName:c |vpiDirection:2 |vpiLowConn: @@ -14250,7 +14250,7 @@ design: (work@bottom1) |vpiContAssign: \_cont_assign: , line:23:10, endln:23:19 |vpiParent: - \_module: work@my_module (work@my_module), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:20:1, endln:24:10 + \_module_inst: work@my_module (work@my_module), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:20:1, endln:24:10 |vpiRhs: \_operation: , line:23:14, endln:23:19 |vpiParent: @@ -14281,14 +14281,14 @@ design: (work@bottom1) |vpiActual: \_logic_net: (work@top.inst[0][0][0].c), line:20:25, endln:20:26 |uhdmallModules: -\_module: work@small_test (work@small_test), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:5:1, endln:54:10 +\_module_inst: work@small_test (work@small_test), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:5:1, endln:54:10 |vpiParent: \_design: (work@bottom1) |vpiFullName:work@small_test |vpiParameter: \_parameter: (work@small_test.SIZE), line:8:27, endln:8:31 |vpiParent: - \_module: work@small_test (work@small_test), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:5:1, endln:54:10 + \_module_inst: work@small_test (work@small_test), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:5:1, endln:54:10 |REAL:10.000000 |vpiTypespec: \_int_typespec: , line:8:14, endln:8:20 @@ -14318,7 +14318,7 @@ design: (work@bottom1) |vpiParameter: \_parameter: (work@small_test.dummy), line:9:14, endln:9:19 |vpiParent: - \_module: work@small_test (work@small_test), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:5:1, endln:54:10 + \_module_inst: work@small_test (work@small_test), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:5:1, endln:54:10 |UINT:5 |vpiTypespec: \_int_typespec: @@ -14327,7 +14327,7 @@ design: (work@bottom1) |vpiParameter: \_parameter: (work@small_test.p1), line:10:11, endln:10:13 |vpiParent: - \_module: work@small_test (work@small_test), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:5:1, endln:54:10 + \_module_inst: work@small_test (work@small_test), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:5:1, endln:54:10 |BIN:100 |vpiTypespec: \_int_typespec: @@ -14344,7 +14344,7 @@ design: (work@bottom1) |vpiParamAssign: \_param_assign: , line:8:27, endln:8:37 |vpiParent: - \_module: work@small_test (work@small_test), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:5:1, endln:54:10 + \_module_inst: work@small_test (work@small_test), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:5:1, endln:54:10 |vpiRhs: \_constant: , line:8:34, endln:8:37 |vpiDecompile:1e1 @@ -14358,7 +14358,7 @@ design: (work@bottom1) |vpiParamAssign: \_param_assign: , line:9:14, endln:9:23 |vpiParent: - \_module: work@small_test (work@small_test), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:5:1, endln:54:10 + \_module_inst: work@small_test (work@small_test), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:5:1, endln:54:10 |vpiRhs: \_constant: , line:9:22, endln:9:23 |vpiDecompile:5 @@ -14372,7 +14372,7 @@ design: (work@bottom1) |vpiParamAssign: \_param_assign: , line:10:11, endln:10:23 |vpiParent: - \_module: work@small_test (work@small_test), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:5:1, endln:54:10 + \_module_inst: work@small_test (work@small_test), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:5:1, endln:54:10 |vpiRhs: \_constant: , line:10:16, endln:10:23 |vpiDecompile:13'b100 @@ -14385,20 +14385,20 @@ design: (work@bottom1) \_parameter: (work@small_test.p1), line:10:11, endln:10:13 |vpiDefName:work@small_test |uhdmallModules: -\_module: work@small_top (work@small_top), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:1:1, endln:3:10 +\_module_inst: work@small_top (work@small_top), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:1:1, endln:3:10 |vpiParent: \_design: (work@bottom1) |vpiFullName:work@small_top |vpiDefName:work@small_top |uhdmallModules: -\_module: work@test (work@test), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:35:1, endln:76:10 +\_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:35:1, endln:76:10 |vpiParent: \_design: (work@bottom1) |vpiFullName:work@test |vpiParameter: \_parameter: (work@test.POWER1), line:37:13, endln:37:19 |vpiParent: - \_module: work@test (work@test), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:35:1, endln:76:10 + \_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:35:1, endln:76:10 |UINT:1 |vpiTypespec: \_int_typespec: @@ -14407,7 +14407,7 @@ design: (work@bottom1) |vpiParameter: \_parameter: (work@test.POWER2), line:38:13, endln:38:19 |vpiParent: - \_module: work@test (work@test), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:35:1, endln:76:10 + \_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:35:1, endln:76:10 |UINT:1 |vpiTypespec: \_int_typespec: @@ -14416,7 +14416,7 @@ design: (work@bottom1) |vpiParamAssign: \_param_assign: , line:37:13, endln:37:23 |vpiParent: - \_module: work@test (work@test), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:35:1, endln:76:10 + \_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:35:1, endln:76:10 |vpiRhs: \_constant: , line:37:22, endln:37:23 |vpiDecompile:1 @@ -14430,7 +14430,7 @@ design: (work@bottom1) |vpiParamAssign: \_param_assign: , line:38:13, endln:38:23 |vpiParent: - \_module: work@test (work@test), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:35:1, endln:76:10 + \_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:35:1, endln:76:10 |vpiRhs: \_constant: , line:38:22, endln:38:23 |vpiDecompile:1 @@ -14445,19 +14445,19 @@ design: (work@bottom1) |vpiNet: \_logic_net: (work@test.a), line:35:13, endln:35:14 |vpiParent: - \_module: work@test (work@test), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:35:1, endln:76:10 + \_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:35:1, endln:76:10 |vpiName:a |vpiFullName:work@test.a |vpiNet: \_logic_net: (work@test.b), line:35:16, endln:35:17 |vpiParent: - \_module: work@test (work@test), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:35:1, endln:76:10 + \_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:35:1, endln:76:10 |vpiName:b |vpiFullName:work@test.b |vpiPort: \_port: (a), line:35:13, endln:35:14 |vpiParent: - \_module: work@test (work@test), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:35:1, endln:76:10 + \_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:35:1, endln:76:10 |vpiName:a |vpiDirection:3 |vpiLowConn: @@ -14467,7 +14467,7 @@ design: (work@bottom1) |vpiPort: \_port: (b), line:35:16, endln:35:17 |vpiParent: - \_module: work@test (work@test), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:35:1, endln:76:10 + \_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:35:1, endln:76:10 |vpiName:b |vpiDirection:3 |vpiLowConn: @@ -14475,7 +14475,7 @@ design: (work@bottom1) |vpiActual: \_logic_net: (work@test.b), line:35:16, endln:35:17 |uhdmallModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:26:1, endln:31:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:26:1, endln:31:10 |vpiParent: \_design: (work@bottom1) |vpiFullName:work@top @@ -14483,25 +14483,25 @@ design: (work@bottom1) |vpiNet: \_logic_net: (work@top.a), line:26:13, endln:26:14 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:26:1, endln:31:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:26:1, endln:31:10 |vpiName:a |vpiFullName:work@top.a |vpiNet: \_logic_net: (work@top.b), line:26:16, endln:26:17 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:26:1, endln:31:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:26:1, endln:31:10 |vpiName:b |vpiFullName:work@top.b |vpiNet: \_logic_net: (work@top.c), line:26:19, endln:26:20 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:26:1, endln:31:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:26:1, endln:31:10 |vpiName:c |vpiFullName:work@top.c |vpiPort: \_port: (a), line:26:13, endln:26:14 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:26:1, endln:31:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:26:1, endln:31:10 |vpiName:a |vpiDirection:1 |vpiLowConn: @@ -14531,7 +14531,7 @@ design: (work@bottom1) |vpiPort: \_port: (b), line:26:16, endln:26:17 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:26:1, endln:31:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:26:1, endln:31:10 |vpiName:b |vpiDirection:1 |vpiLowConn: @@ -14561,7 +14561,7 @@ design: (work@bottom1) |vpiPort: \_port: (c), line:26:19, endln:26:20 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:26:1, endln:31:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:26:1, endln:31:10 |vpiName:c |vpiDirection:2 |vpiLowConn: @@ -14589,14 +14589,14 @@ design: (work@bottom1) |UINT:0 |vpiConstType:9 |uhdmtopModules: -\_module: work@bottom1 (work@bottom1), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:1:1, endln:4:10 +\_module_inst: work@bottom1 (work@bottom1), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:1:1, endln:4:10 |vpiName:work@bottom1 |vpiDefName:work@bottom1 |vpiTop:1 |vpiNet: \_logic_net: (work@bottom1.a), line:1:23, endln:1:24 |vpiParent: - \_module: work@bottom1 (work@bottom1), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:1:1, endln:4:10 + \_module_inst: work@bottom1 (work@bottom1), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:1:1, endln:4:10 |vpiTypespec: \_logic_typespec: , line:1:23, endln:1:23 |vpiName:a @@ -14604,7 +14604,7 @@ design: (work@bottom1) |vpiNet: \_logic_net: (work@bottom1.b), line:1:32, endln:1:33 |vpiParent: - \_module: work@bottom1 (work@bottom1), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:1:1, endln:4:10 + \_module_inst: work@bottom1 (work@bottom1), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:1:1, endln:4:10 |vpiTypespec: \_logic_typespec: , line:1:32, endln:1:32 |vpiName:b @@ -14613,7 +14613,7 @@ design: (work@bottom1) |vpiPort: \_port: (a), line:1:23, endln:1:24 |vpiParent: - \_module: work@bottom1 (work@bottom1), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:1:1, endln:4:10 + \_module_inst: work@bottom1 (work@bottom1), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:1:1, endln:4:10 |vpiName:a |vpiDirection:1 |vpiLowConn: @@ -14627,7 +14627,7 @@ design: (work@bottom1) |vpiPort: \_port: (b), line:1:32, endln:1:33 |vpiParent: - \_module: work@bottom1 (work@bottom1), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:1:1, endln:4:10 + \_module_inst: work@bottom1 (work@bottom1), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:1:1, endln:4:10 |vpiName:b |vpiDirection:1 |vpiLowConn: @@ -14638,10 +14638,10 @@ design: (work@bottom1) \_logic_net: (work@bottom1.b), line:1:32, endln:1:33 |vpiTypedef: \_logic_typespec: , line:1:32, endln:1:32 - |vpiModule: - \_module: work@bottom2 (work@bottom1.u1), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:2:2, endln:2:20 + |vpiModuleInst: + \_module_inst: work@bottom2 (work@bottom1.u1), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:2:2, endln:2:20 |vpiParent: - \_module: work@bottom1 (work@bottom1), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:1:1, endln:4:10 + \_module_inst: work@bottom1 (work@bottom1), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:1:1, endln:4:10 |vpiName:u1 |vpiFullName:work@bottom1.u1 |vpiDefName:work@bottom2 @@ -14650,7 +14650,7 @@ design: (work@bottom1) |vpiNet: \_logic_net: (work@bottom1.u1.a), line:6:23, endln:6:24 |vpiParent: - \_module: work@bottom2 (work@bottom1.u1), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:2:2, endln:2:20 + \_module_inst: work@bottom2 (work@bottom1.u1), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:2:2, endln:2:20 |vpiTypespec: \_logic_typespec: , line:6:23, endln:6:23 |vpiName:a @@ -14658,17 +14658,17 @@ design: (work@bottom1) |vpiNet: \_logic_net: (work@bottom1.u1.b), line:6:32, endln:6:33 |vpiParent: - \_module: work@bottom2 (work@bottom1.u1), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:2:2, endln:2:20 + \_module_inst: work@bottom2 (work@bottom1.u1), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:2:2, endln:2:20 |vpiTypespec: \_logic_typespec: , line:6:32, endln:6:32 |vpiName:b |vpiFullName:work@bottom1.u1.b |vpiInstance: - \_module: work@bottom1 (work@bottom1), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:1:1, endln:4:10 + \_module_inst: work@bottom1 (work@bottom1), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:1:1, endln:4:10 |vpiPort: \_port: (a), line:6:23, endln:6:24 |vpiParent: - \_module: work@bottom2 (work@bottom1.u1), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:2:2, endln:2:20 + \_module_inst: work@bottom2 (work@bottom1.u1), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:2:2, endln:2:20 |vpiName:a |vpiDirection:1 |vpiHighConn: @@ -14688,7 +14688,7 @@ design: (work@bottom1) |vpiPort: \_port: (b), line:6:32, endln:6:33 |vpiParent: - \_module: work@bottom2 (work@bottom1.u1), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:2:2, endln:2:20 + \_module_inst: work@bottom2 (work@bottom1.u1), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:2:2, endln:2:20 |vpiName:b |vpiDirection:1 |vpiHighConn: @@ -14705,10 +14705,10 @@ design: (work@bottom1) \_logic_net: (work@bottom1.u1.b), line:6:32, endln:6:33 |vpiTypedef: \_logic_typespec: , line:6:32, endln:6:32 - |vpiModule: - \_module: work@bottom4 (work@bottom1.u1.u2), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:7:2, endln:7:20 + |vpiModuleInst: + \_module_inst: work@bottom4 (work@bottom1.u1.u2), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:7:2, endln:7:20 |vpiParent: - \_module: work@bottom2 (work@bottom1.u1), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:2:2, endln:2:20 + \_module_inst: work@bottom2 (work@bottom1.u1), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:2:2, endln:2:20 |vpiName:u2 |vpiFullName:work@bottom1.u1.u2 |vpiDefName:work@bottom4 @@ -14717,7 +14717,7 @@ design: (work@bottom1) |vpiNet: \_logic_net: (work@bottom1.u1.u2.a), line:11:23, endln:11:24 |vpiParent: - \_module: work@bottom4 (work@bottom1.u1.u2), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:7:2, endln:7:20 + \_module_inst: work@bottom4 (work@bottom1.u1.u2), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:7:2, endln:7:20 |vpiTypespec: \_logic_typespec: , line:11:23, endln:11:23 |vpiName:a @@ -14725,17 +14725,17 @@ design: (work@bottom1) |vpiNet: \_logic_net: (work@bottom1.u1.u2.b), line:11:32, endln:11:33 |vpiParent: - \_module: work@bottom4 (work@bottom1.u1.u2), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:7:2, endln:7:20 + \_module_inst: work@bottom4 (work@bottom1.u1.u2), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:7:2, endln:7:20 |vpiTypespec: \_logic_typespec: , line:11:32, endln:11:32 |vpiName:b |vpiFullName:work@bottom1.u1.u2.b |vpiInstance: - \_module: work@bottom2 (work@bottom1.u1), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:2:2, endln:2:20 + \_module_inst: work@bottom2 (work@bottom1.u1), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:2:2, endln:2:20 |vpiPort: \_port: (a), line:11:23, endln:11:24 |vpiParent: - \_module: work@bottom4 (work@bottom1.u1.u2), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:7:2, endln:7:20 + \_module_inst: work@bottom4 (work@bottom1.u1.u2), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:7:2, endln:7:20 |vpiName:a |vpiDirection:1 |vpiHighConn: @@ -14755,7 +14755,7 @@ design: (work@bottom1) |vpiPort: \_port: (b), line:11:32, endln:11:33 |vpiParent: - \_module: work@bottom4 (work@bottom1.u1.u2), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:7:2, endln:7:20 + \_module_inst: work@bottom4 (work@bottom1.u1.u2), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:7:2, endln:7:20 |vpiName:b |vpiDirection:1 |vpiHighConn: @@ -14772,35 +14772,35 @@ design: (work@bottom1) \_logic_net: (work@bottom1.u1.u2.b), line:11:32, endln:11:33 |vpiTypedef: \_logic_typespec: , line:11:32, endln:11:32 - |vpiModule: - \_module: work@bottom2 (work@bottom1.u1.u2.u2), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:12:1, endln:12:19 + |vpiModuleInst: + \_module_inst: work@bottom2 (work@bottom1.u1.u2.u2), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:12:1, endln:12:19 |vpiParent: - \_module: work@bottom4 (work@bottom1.u1.u2), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:7:2, endln:7:20 + \_module_inst: work@bottom4 (work@bottom1.u1.u2), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:7:2, endln:7:20 |vpiName:u2 |vpiFullName:work@bottom1.u1.u2.u2 |vpiDefName:work@bottom2 |vpiDefFile:${SURELOG_DIR}/tests/UnitElab/top.v |vpiDefLineNo:6 |vpiInstance: - \_module: work@bottom4 (work@bottom1.u1.u2), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:7:2, endln:7:20 - |vpiModule: - \_module: work@bottom1::bottom3 (work@bottom1.u2), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:3:2, endln:3:20 + \_module_inst: work@bottom4 (work@bottom1.u1.u2), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:7:2, endln:7:20 + |vpiModuleInst: + \_module_inst: work@bottom1::bottom3 (work@bottom1.u2), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:3:2, endln:3:20 |vpiParent: - \_module: work@bottom1 (work@bottom1), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:1:1, endln:4:10 + \_module_inst: work@bottom1 (work@bottom1), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:1:1, endln:4:10 |vpiName:u2 |vpiFullName:work@bottom1.u2 |vpiDefName:work@bottom1::bottom3 |vpiInstance: - \_module: work@bottom1 (work@bottom1), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:1:1, endln:4:10 + \_module_inst: work@bottom1 (work@bottom1), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:1:1, endln:4:10 |uhdmtopModules: -\_module: work@bottom5 (work@bottom5), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:16:1, endln:17:10 +\_module_inst: work@bottom5 (work@bottom5), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:16:1, endln:17:10 |vpiName:work@bottom5 |vpiDefName:work@bottom5 |vpiTop:1 |vpiNet: \_logic_net: (work@bottom5.a), line:16:23, endln:16:24 |vpiParent: - \_module: work@bottom5 (work@bottom5), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:16:1, endln:17:10 + \_module_inst: work@bottom5 (work@bottom5), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:16:1, endln:17:10 |vpiTypespec: \_logic_typespec: , line:16:23, endln:16:23 |vpiName:a @@ -14808,7 +14808,7 @@ design: (work@bottom1) |vpiNet: \_logic_net: (work@bottom5.b), line:16:32, endln:16:33 |vpiParent: - \_module: work@bottom5 (work@bottom5), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:16:1, endln:17:10 + \_module_inst: work@bottom5 (work@bottom5), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:16:1, endln:17:10 |vpiTypespec: \_logic_typespec: , line:16:32, endln:16:32 |vpiName:b @@ -14817,7 +14817,7 @@ design: (work@bottom1) |vpiPort: \_port: (a), line:16:23, endln:16:24 |vpiParent: - \_module: work@bottom5 (work@bottom5), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:16:1, endln:17:10 + \_module_inst: work@bottom5 (work@bottom5), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:16:1, endln:17:10 |vpiName:a |vpiDirection:1 |vpiLowConn: @@ -14831,7 +14831,7 @@ design: (work@bottom1) |vpiPort: \_port: (b), line:16:32, endln:16:33 |vpiParent: - \_module: work@bottom5 (work@bottom5), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:16:1, endln:17:10 + \_module_inst: work@bottom5 (work@bottom5), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:16:1, endln:17:10 |vpiName:b |vpiDirection:1 |vpiLowConn: @@ -14843,14 +14843,14 @@ design: (work@bottom1) |vpiTypedef: \_logic_typespec: , line:16:32, endln:16:32 |uhdmtopModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:26:1, endln:31:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:26:1, endln:31:10 |vpiName:work@top |vpiDefName:work@top |vpiTop:1 |vpiNet: \_logic_net: (work@top.a), line:26:13, endln:26:14 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:26:1, endln:31:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:26:1, endln:31:10 |vpiTypespec: \_logic_typespec: , line:27:7, endln:27:12 |vpiRange: @@ -14876,7 +14876,7 @@ design: (work@bottom1) |vpiNet: \_logic_net: (work@top.b), line:26:16, endln:26:17 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:26:1, endln:31:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:26:1, endln:31:10 |vpiTypespec: \_logic_typespec: , line:27:7, endln:27:12 |vpiName:b @@ -14884,7 +14884,7 @@ design: (work@bottom1) |vpiNet: \_logic_net: (work@top.c), line:26:19, endln:26:20 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:26:1, endln:31:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:26:1, endln:31:10 |vpiTypespec: \_logic_typespec: , line:28:8, endln:28:13 |vpiRange: @@ -14911,7 +14911,7 @@ design: (work@bottom1) |vpiPort: \_port: (a), line:26:13, endln:26:14 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:26:1, endln:31:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:26:1, endln:31:10 |vpiName:a |vpiDirection:1 |vpiLowConn: @@ -14945,7 +14945,7 @@ design: (work@bottom1) |vpiPort: \_port: (b), line:26:16, endln:26:17 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:26:1, endln:31:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:26:1, endln:31:10 |vpiName:b |vpiDirection:1 |vpiLowConn: @@ -14959,7 +14959,7 @@ design: (work@bottom1) |vpiPort: \_port: (c), line:26:19, endln:26:20 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:26:1, endln:31:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:26:1, endln:31:10 |vpiName:c |vpiDirection:2 |vpiLowConn: @@ -14990,10 +14990,10 @@ design: (work@bottom1) |vpiSize:64 |UINT:0 |vpiConstType:9 - |vpiModule: - \_module: work@my_module (work@top.inst[0][0][0]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 + |vpiModuleInst: + \_module_inst: work@my_module (work@top.inst[0][0][0]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:26:1, endln:31:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:26:1, endln:31:10 |vpiName:inst[0][0][0] |vpiFullName:work@top.inst[0][0][0] |vpiDefName:work@my_module @@ -15002,7 +15002,7 @@ design: (work@bottom1) |vpiNet: \_logic_net: (work@top.inst[0][0][0].a), line:20:19, endln:20:20 |vpiParent: - \_module: work@my_module (work@top.inst[0][0][0]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 + \_module_inst: work@my_module (work@top.inst[0][0][0]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 |vpiTypespec: \_logic_typespec: , line:21:7, endln:21:7 |vpiName:a @@ -15010,7 +15010,7 @@ design: (work@bottom1) |vpiNet: \_logic_net: (work@top.inst[0][0][0].b), line:20:22, endln:20:23 |vpiParent: - \_module: work@my_module (work@top.inst[0][0][0]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 + \_module_inst: work@my_module (work@top.inst[0][0][0]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 |vpiTypespec: \_logic_typespec: , line:21:7, endln:21:7 |vpiName:b @@ -15018,17 +15018,17 @@ design: (work@bottom1) |vpiNet: \_logic_net: (work@top.inst[0][0][0].c), line:20:25, endln:20:26 |vpiParent: - \_module: work@my_module (work@top.inst[0][0][0]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 + \_module_inst: work@my_module (work@top.inst[0][0][0]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 |vpiTypespec: \_logic_typespec: , line:22:8, endln:22:8 |vpiName:c |vpiFullName:work@top.inst[0][0][0].c |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:26:1, endln:31:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:26:1, endln:31:10 |vpiPort: \_port: (a), line:20:19, endln:20:20 |vpiParent: - \_module: work@my_module (work@top.inst[0][0][0]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 + \_module_inst: work@my_module (work@top.inst[0][0][0]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 |vpiName:a |vpiDirection:1 |vpiHighConn: @@ -15052,7 +15052,7 @@ design: (work@bottom1) |vpiPort: \_port: (b), line:20:22, endln:20:23 |vpiParent: - \_module: work@my_module (work@top.inst[0][0][0]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 + \_module_inst: work@my_module (work@top.inst[0][0][0]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 |vpiName:b |vpiDirection:1 |vpiHighConn: @@ -15076,7 +15076,7 @@ design: (work@bottom1) |vpiPort: \_port: (c), line:20:25, endln:20:26 |vpiParent: - \_module: work@my_module (work@top.inst[0][0][0]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 + \_module_inst: work@my_module (work@top.inst[0][0][0]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 |vpiName:c |vpiDirection:2 |vpiHighConn: @@ -15121,10 +15121,10 @@ design: (work@bottom1) |vpiName:c |vpiActual: \_logic_net: (work@top.inst[0][0][0].c), line:20:25, endln:20:26 - |vpiModule: - \_module: work@my_module (work@top.inst[0][0][1]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 + |vpiModuleInst: + \_module_inst: work@my_module (work@top.inst[0][0][1]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:26:1, endln:31:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:26:1, endln:31:10 |vpiName:inst[0][0][1] |vpiFullName:work@top.inst[0][0][1] |vpiDefName:work@my_module @@ -15133,7 +15133,7 @@ design: (work@bottom1) |vpiNet: \_logic_net: (work@top.inst[0][0][1].a), line:20:19, endln:20:20 |vpiParent: - \_module: work@my_module (work@top.inst[0][0][1]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 + \_module_inst: work@my_module (work@top.inst[0][0][1]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 |vpiTypespec: \_logic_typespec: , line:21:7, endln:21:7 |vpiName:a @@ -15141,7 +15141,7 @@ design: (work@bottom1) |vpiNet: \_logic_net: (work@top.inst[0][0][1].b), line:20:22, endln:20:23 |vpiParent: - \_module: work@my_module (work@top.inst[0][0][1]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 + \_module_inst: work@my_module (work@top.inst[0][0][1]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 |vpiTypespec: \_logic_typespec: , line:21:7, endln:21:7 |vpiName:b @@ -15149,17 +15149,17 @@ design: (work@bottom1) |vpiNet: \_logic_net: (work@top.inst[0][0][1].c), line:20:25, endln:20:26 |vpiParent: - \_module: work@my_module (work@top.inst[0][0][1]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 + \_module_inst: work@my_module (work@top.inst[0][0][1]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 |vpiTypespec: \_logic_typespec: , line:22:8, endln:22:8 |vpiName:c |vpiFullName:work@top.inst[0][0][1].c |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:26:1, endln:31:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:26:1, endln:31:10 |vpiPort: \_port: (a), line:20:19, endln:20:20 |vpiParent: - \_module: work@my_module (work@top.inst[0][0][1]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 + \_module_inst: work@my_module (work@top.inst[0][0][1]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 |vpiName:a |vpiDirection:1 |vpiHighConn: @@ -15183,7 +15183,7 @@ design: (work@bottom1) |vpiPort: \_port: (b), line:20:22, endln:20:23 |vpiParent: - \_module: work@my_module (work@top.inst[0][0][1]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 + \_module_inst: work@my_module (work@top.inst[0][0][1]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 |vpiName:b |vpiDirection:1 |vpiHighConn: @@ -15207,7 +15207,7 @@ design: (work@bottom1) |vpiPort: \_port: (c), line:20:25, endln:20:26 |vpiParent: - \_module: work@my_module (work@top.inst[0][0][1]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 + \_module_inst: work@my_module (work@top.inst[0][0][1]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 |vpiName:c |vpiDirection:2 |vpiHighConn: @@ -15256,10 +15256,10 @@ design: (work@bottom1) |vpiName:c |vpiActual: \_logic_net: (work@top.inst[0][0][1].c), line:20:25, endln:20:26 - |vpiModule: - \_module: work@my_module (work@top.inst[0][1][0]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 + |vpiModuleInst: + \_module_inst: work@my_module (work@top.inst[0][1][0]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:26:1, endln:31:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:26:1, endln:31:10 |vpiName:inst[0][1][0] |vpiFullName:work@top.inst[0][1][0] |vpiDefName:work@my_module @@ -15268,7 +15268,7 @@ design: (work@bottom1) |vpiNet: \_logic_net: (work@top.inst[0][1][0].a), line:20:19, endln:20:20 |vpiParent: - \_module: work@my_module (work@top.inst[0][1][0]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 + \_module_inst: work@my_module (work@top.inst[0][1][0]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 |vpiTypespec: \_logic_typespec: , line:21:7, endln:21:7 |vpiName:a @@ -15276,7 +15276,7 @@ design: (work@bottom1) |vpiNet: \_logic_net: (work@top.inst[0][1][0].b), line:20:22, endln:20:23 |vpiParent: - \_module: work@my_module (work@top.inst[0][1][0]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 + \_module_inst: work@my_module (work@top.inst[0][1][0]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 |vpiTypespec: \_logic_typespec: , line:21:7, endln:21:7 |vpiName:b @@ -15284,17 +15284,17 @@ design: (work@bottom1) |vpiNet: \_logic_net: (work@top.inst[0][1][0].c), line:20:25, endln:20:26 |vpiParent: - \_module: work@my_module (work@top.inst[0][1][0]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 + \_module_inst: work@my_module (work@top.inst[0][1][0]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 |vpiTypespec: \_logic_typespec: , line:22:8, endln:22:8 |vpiName:c |vpiFullName:work@top.inst[0][1][0].c |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:26:1, endln:31:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:26:1, endln:31:10 |vpiPort: \_port: (a), line:20:19, endln:20:20 |vpiParent: - \_module: work@my_module (work@top.inst[0][1][0]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 + \_module_inst: work@my_module (work@top.inst[0][1][0]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 |vpiName:a |vpiDirection:1 |vpiHighConn: @@ -15318,7 +15318,7 @@ design: (work@bottom1) |vpiPort: \_port: (b), line:20:22, endln:20:23 |vpiParent: - \_module: work@my_module (work@top.inst[0][1][0]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 + \_module_inst: work@my_module (work@top.inst[0][1][0]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 |vpiName:b |vpiDirection:1 |vpiHighConn: @@ -15342,7 +15342,7 @@ design: (work@bottom1) |vpiPort: \_port: (c), line:20:25, endln:20:26 |vpiParent: - \_module: work@my_module (work@top.inst[0][1][0]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 + \_module_inst: work@my_module (work@top.inst[0][1][0]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 |vpiName:c |vpiDirection:2 |vpiHighConn: @@ -15391,10 +15391,10 @@ design: (work@bottom1) |vpiName:c |vpiActual: \_logic_net: (work@top.inst[0][1][0].c), line:20:25, endln:20:26 - |vpiModule: - \_module: work@my_module (work@top.inst[0][1][1]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 + |vpiModuleInst: + \_module_inst: work@my_module (work@top.inst[0][1][1]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:26:1, endln:31:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:26:1, endln:31:10 |vpiName:inst[0][1][1] |vpiFullName:work@top.inst[0][1][1] |vpiDefName:work@my_module @@ -15403,7 +15403,7 @@ design: (work@bottom1) |vpiNet: \_logic_net: (work@top.inst[0][1][1].a), line:20:19, endln:20:20 |vpiParent: - \_module: work@my_module (work@top.inst[0][1][1]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 + \_module_inst: work@my_module (work@top.inst[0][1][1]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 |vpiTypespec: \_logic_typespec: , line:21:7, endln:21:7 |vpiName:a @@ -15411,7 +15411,7 @@ design: (work@bottom1) |vpiNet: \_logic_net: (work@top.inst[0][1][1].b), line:20:22, endln:20:23 |vpiParent: - \_module: work@my_module (work@top.inst[0][1][1]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 + \_module_inst: work@my_module (work@top.inst[0][1][1]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 |vpiTypespec: \_logic_typespec: , line:21:7, endln:21:7 |vpiName:b @@ -15419,17 +15419,17 @@ design: (work@bottom1) |vpiNet: \_logic_net: (work@top.inst[0][1][1].c), line:20:25, endln:20:26 |vpiParent: - \_module: work@my_module (work@top.inst[0][1][1]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 + \_module_inst: work@my_module (work@top.inst[0][1][1]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 |vpiTypespec: \_logic_typespec: , line:22:8, endln:22:8 |vpiName:c |vpiFullName:work@top.inst[0][1][1].c |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:26:1, endln:31:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:26:1, endln:31:10 |vpiPort: \_port: (a), line:20:19, endln:20:20 |vpiParent: - \_module: work@my_module (work@top.inst[0][1][1]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 + \_module_inst: work@my_module (work@top.inst[0][1][1]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 |vpiName:a |vpiDirection:1 |vpiHighConn: @@ -15453,7 +15453,7 @@ design: (work@bottom1) |vpiPort: \_port: (b), line:20:22, endln:20:23 |vpiParent: - \_module: work@my_module (work@top.inst[0][1][1]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 + \_module_inst: work@my_module (work@top.inst[0][1][1]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 |vpiName:b |vpiDirection:1 |vpiHighConn: @@ -15477,7 +15477,7 @@ design: (work@bottom1) |vpiPort: \_port: (c), line:20:25, endln:20:26 |vpiParent: - \_module: work@my_module (work@top.inst[0][1][1]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 + \_module_inst: work@my_module (work@top.inst[0][1][1]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 |vpiName:c |vpiDirection:2 |vpiHighConn: @@ -15526,10 +15526,10 @@ design: (work@bottom1) |vpiName:c |vpiActual: \_logic_net: (work@top.inst[0][1][1].c), line:20:25, endln:20:26 - |vpiModule: - \_module: work@my_module (work@top.inst[0][2][0]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 + |vpiModuleInst: + \_module_inst: work@my_module (work@top.inst[0][2][0]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:26:1, endln:31:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:26:1, endln:31:10 |vpiName:inst[0][2][0] |vpiFullName:work@top.inst[0][2][0] |vpiDefName:work@my_module @@ -15538,7 +15538,7 @@ design: (work@bottom1) |vpiNet: \_logic_net: (work@top.inst[0][2][0].a), line:20:19, endln:20:20 |vpiParent: - \_module: work@my_module (work@top.inst[0][2][0]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 + \_module_inst: work@my_module (work@top.inst[0][2][0]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 |vpiTypespec: \_logic_typespec: , line:21:7, endln:21:7 |vpiName:a @@ -15546,7 +15546,7 @@ design: (work@bottom1) |vpiNet: \_logic_net: (work@top.inst[0][2][0].b), line:20:22, endln:20:23 |vpiParent: - \_module: work@my_module (work@top.inst[0][2][0]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 + \_module_inst: work@my_module (work@top.inst[0][2][0]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 |vpiTypespec: \_logic_typespec: , line:21:7, endln:21:7 |vpiName:b @@ -15554,17 +15554,17 @@ design: (work@bottom1) |vpiNet: \_logic_net: (work@top.inst[0][2][0].c), line:20:25, endln:20:26 |vpiParent: - \_module: work@my_module (work@top.inst[0][2][0]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 + \_module_inst: work@my_module (work@top.inst[0][2][0]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 |vpiTypespec: \_logic_typespec: , line:22:8, endln:22:8 |vpiName:c |vpiFullName:work@top.inst[0][2][0].c |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:26:1, endln:31:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:26:1, endln:31:10 |vpiPort: \_port: (a), line:20:19, endln:20:20 |vpiParent: - \_module: work@my_module (work@top.inst[0][2][0]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 + \_module_inst: work@my_module (work@top.inst[0][2][0]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 |vpiName:a |vpiDirection:1 |vpiHighConn: @@ -15588,7 +15588,7 @@ design: (work@bottom1) |vpiPort: \_port: (b), line:20:22, endln:20:23 |vpiParent: - \_module: work@my_module (work@top.inst[0][2][0]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 + \_module_inst: work@my_module (work@top.inst[0][2][0]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 |vpiName:b |vpiDirection:1 |vpiHighConn: @@ -15612,7 +15612,7 @@ design: (work@bottom1) |vpiPort: \_port: (c), line:20:25, endln:20:26 |vpiParent: - \_module: work@my_module (work@top.inst[0][2][0]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 + \_module_inst: work@my_module (work@top.inst[0][2][0]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 |vpiName:c |vpiDirection:2 |vpiHighConn: @@ -15661,10 +15661,10 @@ design: (work@bottom1) |vpiName:c |vpiActual: \_logic_net: (work@top.inst[0][2][0].c), line:20:25, endln:20:26 - |vpiModule: - \_module: work@my_module (work@top.inst[0][2][1]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 + |vpiModuleInst: + \_module_inst: work@my_module (work@top.inst[0][2][1]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:26:1, endln:31:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:26:1, endln:31:10 |vpiName:inst[0][2][1] |vpiFullName:work@top.inst[0][2][1] |vpiDefName:work@my_module @@ -15673,7 +15673,7 @@ design: (work@bottom1) |vpiNet: \_logic_net: (work@top.inst[0][2][1].a), line:20:19, endln:20:20 |vpiParent: - \_module: work@my_module (work@top.inst[0][2][1]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 + \_module_inst: work@my_module (work@top.inst[0][2][1]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 |vpiTypespec: \_logic_typespec: , line:21:7, endln:21:7 |vpiName:a @@ -15681,7 +15681,7 @@ design: (work@bottom1) |vpiNet: \_logic_net: (work@top.inst[0][2][1].b), line:20:22, endln:20:23 |vpiParent: - \_module: work@my_module (work@top.inst[0][2][1]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 + \_module_inst: work@my_module (work@top.inst[0][2][1]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 |vpiTypespec: \_logic_typespec: , line:21:7, endln:21:7 |vpiName:b @@ -15689,17 +15689,17 @@ design: (work@bottom1) |vpiNet: \_logic_net: (work@top.inst[0][2][1].c), line:20:25, endln:20:26 |vpiParent: - \_module: work@my_module (work@top.inst[0][2][1]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 + \_module_inst: work@my_module (work@top.inst[0][2][1]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 |vpiTypespec: \_logic_typespec: , line:22:8, endln:22:8 |vpiName:c |vpiFullName:work@top.inst[0][2][1].c |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:26:1, endln:31:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:26:1, endln:31:10 |vpiPort: \_port: (a), line:20:19, endln:20:20 |vpiParent: - \_module: work@my_module (work@top.inst[0][2][1]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 + \_module_inst: work@my_module (work@top.inst[0][2][1]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 |vpiName:a |vpiDirection:1 |vpiHighConn: @@ -15723,7 +15723,7 @@ design: (work@bottom1) |vpiPort: \_port: (b), line:20:22, endln:20:23 |vpiParent: - \_module: work@my_module (work@top.inst[0][2][1]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 + \_module_inst: work@my_module (work@top.inst[0][2][1]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 |vpiName:b |vpiDirection:1 |vpiHighConn: @@ -15747,7 +15747,7 @@ design: (work@bottom1) |vpiPort: \_port: (c), line:20:25, endln:20:26 |vpiParent: - \_module: work@my_module (work@top.inst[0][2][1]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 + \_module_inst: work@my_module (work@top.inst[0][2][1]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 |vpiName:c |vpiDirection:2 |vpiHighConn: @@ -15796,10 +15796,10 @@ design: (work@bottom1) |vpiName:c |vpiActual: \_logic_net: (work@top.inst[0][2][1].c), line:20:25, endln:20:26 - |vpiModule: - \_module: work@my_module (work@top.inst[1][0][0]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 + |vpiModuleInst: + \_module_inst: work@my_module (work@top.inst[1][0][0]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:26:1, endln:31:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:26:1, endln:31:10 |vpiName:inst[1][0][0] |vpiFullName:work@top.inst[1][0][0] |vpiDefName:work@my_module @@ -15808,7 +15808,7 @@ design: (work@bottom1) |vpiNet: \_logic_net: (work@top.inst[1][0][0].a), line:20:19, endln:20:20 |vpiParent: - \_module: work@my_module (work@top.inst[1][0][0]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 + \_module_inst: work@my_module (work@top.inst[1][0][0]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 |vpiTypespec: \_logic_typespec: , line:21:7, endln:21:7 |vpiName:a @@ -15816,7 +15816,7 @@ design: (work@bottom1) |vpiNet: \_logic_net: (work@top.inst[1][0][0].b), line:20:22, endln:20:23 |vpiParent: - \_module: work@my_module (work@top.inst[1][0][0]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 + \_module_inst: work@my_module (work@top.inst[1][0][0]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 |vpiTypespec: \_logic_typespec: , line:21:7, endln:21:7 |vpiName:b @@ -15824,17 +15824,17 @@ design: (work@bottom1) |vpiNet: \_logic_net: (work@top.inst[1][0][0].c), line:20:25, endln:20:26 |vpiParent: - \_module: work@my_module (work@top.inst[1][0][0]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 + \_module_inst: work@my_module (work@top.inst[1][0][0]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 |vpiTypespec: \_logic_typespec: , line:22:8, endln:22:8 |vpiName:c |vpiFullName:work@top.inst[1][0][0].c |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:26:1, endln:31:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:26:1, endln:31:10 |vpiPort: \_port: (a), line:20:19, endln:20:20 |vpiParent: - \_module: work@my_module (work@top.inst[1][0][0]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 + \_module_inst: work@my_module (work@top.inst[1][0][0]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 |vpiName:a |vpiDirection:1 |vpiHighConn: @@ -15858,7 +15858,7 @@ design: (work@bottom1) |vpiPort: \_port: (b), line:20:22, endln:20:23 |vpiParent: - \_module: work@my_module (work@top.inst[1][0][0]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 + \_module_inst: work@my_module (work@top.inst[1][0][0]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 |vpiName:b |vpiDirection:1 |vpiHighConn: @@ -15882,7 +15882,7 @@ design: (work@bottom1) |vpiPort: \_port: (c), line:20:25, endln:20:26 |vpiParent: - \_module: work@my_module (work@top.inst[1][0][0]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 + \_module_inst: work@my_module (work@top.inst[1][0][0]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 |vpiName:c |vpiDirection:2 |vpiHighConn: @@ -15931,10 +15931,10 @@ design: (work@bottom1) |vpiName:c |vpiActual: \_logic_net: (work@top.inst[1][0][0].c), line:20:25, endln:20:26 - |vpiModule: - \_module: work@my_module (work@top.inst[1][0][1]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 + |vpiModuleInst: + \_module_inst: work@my_module (work@top.inst[1][0][1]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:26:1, endln:31:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:26:1, endln:31:10 |vpiName:inst[1][0][1] |vpiFullName:work@top.inst[1][0][1] |vpiDefName:work@my_module @@ -15943,7 +15943,7 @@ design: (work@bottom1) |vpiNet: \_logic_net: (work@top.inst[1][0][1].a), line:20:19, endln:20:20 |vpiParent: - \_module: work@my_module (work@top.inst[1][0][1]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 + \_module_inst: work@my_module (work@top.inst[1][0][1]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 |vpiTypespec: \_logic_typespec: , line:21:7, endln:21:7 |vpiName:a @@ -15951,7 +15951,7 @@ design: (work@bottom1) |vpiNet: \_logic_net: (work@top.inst[1][0][1].b), line:20:22, endln:20:23 |vpiParent: - \_module: work@my_module (work@top.inst[1][0][1]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 + \_module_inst: work@my_module (work@top.inst[1][0][1]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 |vpiTypespec: \_logic_typespec: , line:21:7, endln:21:7 |vpiName:b @@ -15959,17 +15959,17 @@ design: (work@bottom1) |vpiNet: \_logic_net: (work@top.inst[1][0][1].c), line:20:25, endln:20:26 |vpiParent: - \_module: work@my_module (work@top.inst[1][0][1]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 + \_module_inst: work@my_module (work@top.inst[1][0][1]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 |vpiTypespec: \_logic_typespec: , line:22:8, endln:22:8 |vpiName:c |vpiFullName:work@top.inst[1][0][1].c |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:26:1, endln:31:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:26:1, endln:31:10 |vpiPort: \_port: (a), line:20:19, endln:20:20 |vpiParent: - \_module: work@my_module (work@top.inst[1][0][1]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 + \_module_inst: work@my_module (work@top.inst[1][0][1]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 |vpiName:a |vpiDirection:1 |vpiHighConn: @@ -15993,7 +15993,7 @@ design: (work@bottom1) |vpiPort: \_port: (b), line:20:22, endln:20:23 |vpiParent: - \_module: work@my_module (work@top.inst[1][0][1]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 + \_module_inst: work@my_module (work@top.inst[1][0][1]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 |vpiName:b |vpiDirection:1 |vpiHighConn: @@ -16017,7 +16017,7 @@ design: (work@bottom1) |vpiPort: \_port: (c), line:20:25, endln:20:26 |vpiParent: - \_module: work@my_module (work@top.inst[1][0][1]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 + \_module_inst: work@my_module (work@top.inst[1][0][1]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 |vpiName:c |vpiDirection:2 |vpiHighConn: @@ -16066,10 +16066,10 @@ design: (work@bottom1) |vpiName:c |vpiActual: \_logic_net: (work@top.inst[1][0][1].c), line:20:25, endln:20:26 - |vpiModule: - \_module: work@my_module (work@top.inst[1][1][0]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 + |vpiModuleInst: + \_module_inst: work@my_module (work@top.inst[1][1][0]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:26:1, endln:31:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:26:1, endln:31:10 |vpiName:inst[1][1][0] |vpiFullName:work@top.inst[1][1][0] |vpiDefName:work@my_module @@ -16078,7 +16078,7 @@ design: (work@bottom1) |vpiNet: \_logic_net: (work@top.inst[1][1][0].a), line:20:19, endln:20:20 |vpiParent: - \_module: work@my_module (work@top.inst[1][1][0]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 + \_module_inst: work@my_module (work@top.inst[1][1][0]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 |vpiTypespec: \_logic_typespec: , line:21:7, endln:21:7 |vpiName:a @@ -16086,7 +16086,7 @@ design: (work@bottom1) |vpiNet: \_logic_net: (work@top.inst[1][1][0].b), line:20:22, endln:20:23 |vpiParent: - \_module: work@my_module (work@top.inst[1][1][0]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 + \_module_inst: work@my_module (work@top.inst[1][1][0]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 |vpiTypespec: \_logic_typespec: , line:21:7, endln:21:7 |vpiName:b @@ -16094,17 +16094,17 @@ design: (work@bottom1) |vpiNet: \_logic_net: (work@top.inst[1][1][0].c), line:20:25, endln:20:26 |vpiParent: - \_module: work@my_module (work@top.inst[1][1][0]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 + \_module_inst: work@my_module (work@top.inst[1][1][0]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 |vpiTypespec: \_logic_typespec: , line:22:8, endln:22:8 |vpiName:c |vpiFullName:work@top.inst[1][1][0].c |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:26:1, endln:31:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:26:1, endln:31:10 |vpiPort: \_port: (a), line:20:19, endln:20:20 |vpiParent: - \_module: work@my_module (work@top.inst[1][1][0]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 + \_module_inst: work@my_module (work@top.inst[1][1][0]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 |vpiName:a |vpiDirection:1 |vpiHighConn: @@ -16128,7 +16128,7 @@ design: (work@bottom1) |vpiPort: \_port: (b), line:20:22, endln:20:23 |vpiParent: - \_module: work@my_module (work@top.inst[1][1][0]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 + \_module_inst: work@my_module (work@top.inst[1][1][0]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 |vpiName:b |vpiDirection:1 |vpiHighConn: @@ -16152,7 +16152,7 @@ design: (work@bottom1) |vpiPort: \_port: (c), line:20:25, endln:20:26 |vpiParent: - \_module: work@my_module (work@top.inst[1][1][0]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 + \_module_inst: work@my_module (work@top.inst[1][1][0]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 |vpiName:c |vpiDirection:2 |vpiHighConn: @@ -16201,10 +16201,10 @@ design: (work@bottom1) |vpiName:c |vpiActual: \_logic_net: (work@top.inst[1][1][0].c), line:20:25, endln:20:26 - |vpiModule: - \_module: work@my_module (work@top.inst[1][1][1]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 + |vpiModuleInst: + \_module_inst: work@my_module (work@top.inst[1][1][1]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:26:1, endln:31:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:26:1, endln:31:10 |vpiName:inst[1][1][1] |vpiFullName:work@top.inst[1][1][1] |vpiDefName:work@my_module @@ -16213,7 +16213,7 @@ design: (work@bottom1) |vpiNet: \_logic_net: (work@top.inst[1][1][1].a), line:20:19, endln:20:20 |vpiParent: - \_module: work@my_module (work@top.inst[1][1][1]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 + \_module_inst: work@my_module (work@top.inst[1][1][1]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 |vpiTypespec: \_logic_typespec: , line:21:7, endln:21:7 |vpiName:a @@ -16221,7 +16221,7 @@ design: (work@bottom1) |vpiNet: \_logic_net: (work@top.inst[1][1][1].b), line:20:22, endln:20:23 |vpiParent: - \_module: work@my_module (work@top.inst[1][1][1]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 + \_module_inst: work@my_module (work@top.inst[1][1][1]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 |vpiTypespec: \_logic_typespec: , line:21:7, endln:21:7 |vpiName:b @@ -16229,17 +16229,17 @@ design: (work@bottom1) |vpiNet: \_logic_net: (work@top.inst[1][1][1].c), line:20:25, endln:20:26 |vpiParent: - \_module: work@my_module (work@top.inst[1][1][1]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 + \_module_inst: work@my_module (work@top.inst[1][1][1]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 |vpiTypespec: \_logic_typespec: , line:22:8, endln:22:8 |vpiName:c |vpiFullName:work@top.inst[1][1][1].c |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:26:1, endln:31:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:26:1, endln:31:10 |vpiPort: \_port: (a), line:20:19, endln:20:20 |vpiParent: - \_module: work@my_module (work@top.inst[1][1][1]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 + \_module_inst: work@my_module (work@top.inst[1][1][1]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 |vpiName:a |vpiDirection:1 |vpiHighConn: @@ -16263,7 +16263,7 @@ design: (work@bottom1) |vpiPort: \_port: (b), line:20:22, endln:20:23 |vpiParent: - \_module: work@my_module (work@top.inst[1][1][1]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 + \_module_inst: work@my_module (work@top.inst[1][1][1]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 |vpiName:b |vpiDirection:1 |vpiHighConn: @@ -16287,7 +16287,7 @@ design: (work@bottom1) |vpiPort: \_port: (c), line:20:25, endln:20:26 |vpiParent: - \_module: work@my_module (work@top.inst[1][1][1]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 + \_module_inst: work@my_module (work@top.inst[1][1][1]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 |vpiName:c |vpiDirection:2 |vpiHighConn: @@ -16336,10 +16336,10 @@ design: (work@bottom1) |vpiName:c |vpiActual: \_logic_net: (work@top.inst[1][1][1].c), line:20:25, endln:20:26 - |vpiModule: - \_module: work@my_module (work@top.inst[1][2][0]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 + |vpiModuleInst: + \_module_inst: work@my_module (work@top.inst[1][2][0]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:26:1, endln:31:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:26:1, endln:31:10 |vpiName:inst[1][2][0] |vpiFullName:work@top.inst[1][2][0] |vpiDefName:work@my_module @@ -16348,7 +16348,7 @@ design: (work@bottom1) |vpiNet: \_logic_net: (work@top.inst[1][2][0].a), line:20:19, endln:20:20 |vpiParent: - \_module: work@my_module (work@top.inst[1][2][0]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 + \_module_inst: work@my_module (work@top.inst[1][2][0]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 |vpiTypespec: \_logic_typespec: , line:21:7, endln:21:7 |vpiName:a @@ -16356,7 +16356,7 @@ design: (work@bottom1) |vpiNet: \_logic_net: (work@top.inst[1][2][0].b), line:20:22, endln:20:23 |vpiParent: - \_module: work@my_module (work@top.inst[1][2][0]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 + \_module_inst: work@my_module (work@top.inst[1][2][0]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 |vpiTypespec: \_logic_typespec: , line:21:7, endln:21:7 |vpiName:b @@ -16364,17 +16364,17 @@ design: (work@bottom1) |vpiNet: \_logic_net: (work@top.inst[1][2][0].c), line:20:25, endln:20:26 |vpiParent: - \_module: work@my_module (work@top.inst[1][2][0]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 + \_module_inst: work@my_module (work@top.inst[1][2][0]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 |vpiTypespec: \_logic_typespec: , line:22:8, endln:22:8 |vpiName:c |vpiFullName:work@top.inst[1][2][0].c |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:26:1, endln:31:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:26:1, endln:31:10 |vpiPort: \_port: (a), line:20:19, endln:20:20 |vpiParent: - \_module: work@my_module (work@top.inst[1][2][0]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 + \_module_inst: work@my_module (work@top.inst[1][2][0]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 |vpiName:a |vpiDirection:1 |vpiHighConn: @@ -16398,7 +16398,7 @@ design: (work@bottom1) |vpiPort: \_port: (b), line:20:22, endln:20:23 |vpiParent: - \_module: work@my_module (work@top.inst[1][2][0]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 + \_module_inst: work@my_module (work@top.inst[1][2][0]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 |vpiName:b |vpiDirection:1 |vpiHighConn: @@ -16422,7 +16422,7 @@ design: (work@bottom1) |vpiPort: \_port: (c), line:20:25, endln:20:26 |vpiParent: - \_module: work@my_module (work@top.inst[1][2][0]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 + \_module_inst: work@my_module (work@top.inst[1][2][0]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 |vpiName:c |vpiDirection:2 |vpiHighConn: @@ -16471,10 +16471,10 @@ design: (work@bottom1) |vpiName:c |vpiActual: \_logic_net: (work@top.inst[1][2][0].c), line:20:25, endln:20:26 - |vpiModule: - \_module: work@my_module (work@top.inst[1][2][1]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 + |vpiModuleInst: + \_module_inst: work@my_module (work@top.inst[1][2][1]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:26:1, endln:31:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:26:1, endln:31:10 |vpiName:inst[1][2][1] |vpiFullName:work@top.inst[1][2][1] |vpiDefName:work@my_module @@ -16483,7 +16483,7 @@ design: (work@bottom1) |vpiNet: \_logic_net: (work@top.inst[1][2][1].a), line:20:19, endln:20:20 |vpiParent: - \_module: work@my_module (work@top.inst[1][2][1]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 + \_module_inst: work@my_module (work@top.inst[1][2][1]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 |vpiTypespec: \_logic_typespec: , line:21:7, endln:21:7 |vpiName:a @@ -16491,7 +16491,7 @@ design: (work@bottom1) |vpiNet: \_logic_net: (work@top.inst[1][2][1].b), line:20:22, endln:20:23 |vpiParent: - \_module: work@my_module (work@top.inst[1][2][1]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 + \_module_inst: work@my_module (work@top.inst[1][2][1]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 |vpiTypespec: \_logic_typespec: , line:21:7, endln:21:7 |vpiName:b @@ -16499,17 +16499,17 @@ design: (work@bottom1) |vpiNet: \_logic_net: (work@top.inst[1][2][1].c), line:20:25, endln:20:26 |vpiParent: - \_module: work@my_module (work@top.inst[1][2][1]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 + \_module_inst: work@my_module (work@top.inst[1][2][1]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 |vpiTypespec: \_logic_typespec: , line:22:8, endln:22:8 |vpiName:c |vpiFullName:work@top.inst[1][2][1].c |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:26:1, endln:31:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:26:1, endln:31:10 |vpiPort: \_port: (a), line:20:19, endln:20:20 |vpiParent: - \_module: work@my_module (work@top.inst[1][2][1]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 + \_module_inst: work@my_module (work@top.inst[1][2][1]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 |vpiName:a |vpiDirection:1 |vpiHighConn: @@ -16533,7 +16533,7 @@ design: (work@bottom1) |vpiPort: \_port: (b), line:20:22, endln:20:23 |vpiParent: - \_module: work@my_module (work@top.inst[1][2][1]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 + \_module_inst: work@my_module (work@top.inst[1][2][1]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 |vpiName:b |vpiDirection:1 |vpiHighConn: @@ -16557,7 +16557,7 @@ design: (work@bottom1) |vpiPort: \_port: (c), line:20:25, endln:20:26 |vpiParent: - \_module: work@my_module (work@top.inst[1][2][1]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 + \_module_inst: work@my_module (work@top.inst[1][2][1]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 |vpiName:c |vpiDirection:2 |vpiHighConn: @@ -16606,10 +16606,10 @@ design: (work@bottom1) |vpiName:c |vpiActual: \_logic_net: (work@top.inst[1][2][1].c), line:20:25, endln:20:26 - |vpiModule: - \_module: work@my_module (work@top.inst[2][0][0]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 + |vpiModuleInst: + \_module_inst: work@my_module (work@top.inst[2][0][0]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:26:1, endln:31:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:26:1, endln:31:10 |vpiName:inst[2][0][0] |vpiFullName:work@top.inst[2][0][0] |vpiDefName:work@my_module @@ -16618,7 +16618,7 @@ design: (work@bottom1) |vpiNet: \_logic_net: (work@top.inst[2][0][0].a), line:20:19, endln:20:20 |vpiParent: - \_module: work@my_module (work@top.inst[2][0][0]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 + \_module_inst: work@my_module (work@top.inst[2][0][0]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 |vpiTypespec: \_logic_typespec: , line:21:7, endln:21:7 |vpiName:a @@ -16626,7 +16626,7 @@ design: (work@bottom1) |vpiNet: \_logic_net: (work@top.inst[2][0][0].b), line:20:22, endln:20:23 |vpiParent: - \_module: work@my_module (work@top.inst[2][0][0]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 + \_module_inst: work@my_module (work@top.inst[2][0][0]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 |vpiTypespec: \_logic_typespec: , line:21:7, endln:21:7 |vpiName:b @@ -16634,17 +16634,17 @@ design: (work@bottom1) |vpiNet: \_logic_net: (work@top.inst[2][0][0].c), line:20:25, endln:20:26 |vpiParent: - \_module: work@my_module (work@top.inst[2][0][0]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 + \_module_inst: work@my_module (work@top.inst[2][0][0]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 |vpiTypespec: \_logic_typespec: , line:22:8, endln:22:8 |vpiName:c |vpiFullName:work@top.inst[2][0][0].c |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:26:1, endln:31:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:26:1, endln:31:10 |vpiPort: \_port: (a), line:20:19, endln:20:20 |vpiParent: - \_module: work@my_module (work@top.inst[2][0][0]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 + \_module_inst: work@my_module (work@top.inst[2][0][0]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 |vpiName:a |vpiDirection:1 |vpiHighConn: @@ -16668,7 +16668,7 @@ design: (work@bottom1) |vpiPort: \_port: (b), line:20:22, endln:20:23 |vpiParent: - \_module: work@my_module (work@top.inst[2][0][0]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 + \_module_inst: work@my_module (work@top.inst[2][0][0]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 |vpiName:b |vpiDirection:1 |vpiHighConn: @@ -16692,7 +16692,7 @@ design: (work@bottom1) |vpiPort: \_port: (c), line:20:25, endln:20:26 |vpiParent: - \_module: work@my_module (work@top.inst[2][0][0]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 + \_module_inst: work@my_module (work@top.inst[2][0][0]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 |vpiName:c |vpiDirection:2 |vpiHighConn: @@ -16741,10 +16741,10 @@ design: (work@bottom1) |vpiName:c |vpiActual: \_logic_net: (work@top.inst[2][0][0].c), line:20:25, endln:20:26 - |vpiModule: - \_module: work@my_module (work@top.inst[2][0][1]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 + |vpiModuleInst: + \_module_inst: work@my_module (work@top.inst[2][0][1]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:26:1, endln:31:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:26:1, endln:31:10 |vpiName:inst[2][0][1] |vpiFullName:work@top.inst[2][0][1] |vpiDefName:work@my_module @@ -16753,7 +16753,7 @@ design: (work@bottom1) |vpiNet: \_logic_net: (work@top.inst[2][0][1].a), line:20:19, endln:20:20 |vpiParent: - \_module: work@my_module (work@top.inst[2][0][1]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 + \_module_inst: work@my_module (work@top.inst[2][0][1]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 |vpiTypespec: \_logic_typespec: , line:21:7, endln:21:7 |vpiName:a @@ -16761,7 +16761,7 @@ design: (work@bottom1) |vpiNet: \_logic_net: (work@top.inst[2][0][1].b), line:20:22, endln:20:23 |vpiParent: - \_module: work@my_module (work@top.inst[2][0][1]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 + \_module_inst: work@my_module (work@top.inst[2][0][1]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 |vpiTypespec: \_logic_typespec: , line:21:7, endln:21:7 |vpiName:b @@ -16769,17 +16769,17 @@ design: (work@bottom1) |vpiNet: \_logic_net: (work@top.inst[2][0][1].c), line:20:25, endln:20:26 |vpiParent: - \_module: work@my_module (work@top.inst[2][0][1]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 + \_module_inst: work@my_module (work@top.inst[2][0][1]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 |vpiTypespec: \_logic_typespec: , line:22:8, endln:22:8 |vpiName:c |vpiFullName:work@top.inst[2][0][1].c |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:26:1, endln:31:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:26:1, endln:31:10 |vpiPort: \_port: (a), line:20:19, endln:20:20 |vpiParent: - \_module: work@my_module (work@top.inst[2][0][1]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 + \_module_inst: work@my_module (work@top.inst[2][0][1]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 |vpiName:a |vpiDirection:1 |vpiHighConn: @@ -16803,7 +16803,7 @@ design: (work@bottom1) |vpiPort: \_port: (b), line:20:22, endln:20:23 |vpiParent: - \_module: work@my_module (work@top.inst[2][0][1]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 + \_module_inst: work@my_module (work@top.inst[2][0][1]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 |vpiName:b |vpiDirection:1 |vpiHighConn: @@ -16827,7 +16827,7 @@ design: (work@bottom1) |vpiPort: \_port: (c), line:20:25, endln:20:26 |vpiParent: - \_module: work@my_module (work@top.inst[2][0][1]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 + \_module_inst: work@my_module (work@top.inst[2][0][1]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 |vpiName:c |vpiDirection:2 |vpiHighConn: @@ -16876,10 +16876,10 @@ design: (work@bottom1) |vpiName:c |vpiActual: \_logic_net: (work@top.inst[2][0][1].c), line:20:25, endln:20:26 - |vpiModule: - \_module: work@my_module (work@top.inst[2][1][0]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 + |vpiModuleInst: + \_module_inst: work@my_module (work@top.inst[2][1][0]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:26:1, endln:31:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:26:1, endln:31:10 |vpiName:inst[2][1][0] |vpiFullName:work@top.inst[2][1][0] |vpiDefName:work@my_module @@ -16888,7 +16888,7 @@ design: (work@bottom1) |vpiNet: \_logic_net: (work@top.inst[2][1][0].a), line:20:19, endln:20:20 |vpiParent: - \_module: work@my_module (work@top.inst[2][1][0]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 + \_module_inst: work@my_module (work@top.inst[2][1][0]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 |vpiTypespec: \_logic_typespec: , line:21:7, endln:21:7 |vpiName:a @@ -16896,7 +16896,7 @@ design: (work@bottom1) |vpiNet: \_logic_net: (work@top.inst[2][1][0].b), line:20:22, endln:20:23 |vpiParent: - \_module: work@my_module (work@top.inst[2][1][0]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 + \_module_inst: work@my_module (work@top.inst[2][1][0]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 |vpiTypespec: \_logic_typespec: , line:21:7, endln:21:7 |vpiName:b @@ -16904,17 +16904,17 @@ design: (work@bottom1) |vpiNet: \_logic_net: (work@top.inst[2][1][0].c), line:20:25, endln:20:26 |vpiParent: - \_module: work@my_module (work@top.inst[2][1][0]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 + \_module_inst: work@my_module (work@top.inst[2][1][0]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 |vpiTypespec: \_logic_typespec: , line:22:8, endln:22:8 |vpiName:c |vpiFullName:work@top.inst[2][1][0].c |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:26:1, endln:31:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:26:1, endln:31:10 |vpiPort: \_port: (a), line:20:19, endln:20:20 |vpiParent: - \_module: work@my_module (work@top.inst[2][1][0]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 + \_module_inst: work@my_module (work@top.inst[2][1][0]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 |vpiName:a |vpiDirection:1 |vpiHighConn: @@ -16938,7 +16938,7 @@ design: (work@bottom1) |vpiPort: \_port: (b), line:20:22, endln:20:23 |vpiParent: - \_module: work@my_module (work@top.inst[2][1][0]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 + \_module_inst: work@my_module (work@top.inst[2][1][0]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 |vpiName:b |vpiDirection:1 |vpiHighConn: @@ -16962,7 +16962,7 @@ design: (work@bottom1) |vpiPort: \_port: (c), line:20:25, endln:20:26 |vpiParent: - \_module: work@my_module (work@top.inst[2][1][0]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 + \_module_inst: work@my_module (work@top.inst[2][1][0]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 |vpiName:c |vpiDirection:2 |vpiHighConn: @@ -17011,10 +17011,10 @@ design: (work@bottom1) |vpiName:c |vpiActual: \_logic_net: (work@top.inst[2][1][0].c), line:20:25, endln:20:26 - |vpiModule: - \_module: work@my_module (work@top.inst[2][1][1]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 + |vpiModuleInst: + \_module_inst: work@my_module (work@top.inst[2][1][1]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:26:1, endln:31:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:26:1, endln:31:10 |vpiName:inst[2][1][1] |vpiFullName:work@top.inst[2][1][1] |vpiDefName:work@my_module @@ -17023,7 +17023,7 @@ design: (work@bottom1) |vpiNet: \_logic_net: (work@top.inst[2][1][1].a), line:20:19, endln:20:20 |vpiParent: - \_module: work@my_module (work@top.inst[2][1][1]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 + \_module_inst: work@my_module (work@top.inst[2][1][1]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 |vpiTypespec: \_logic_typespec: , line:21:7, endln:21:7 |vpiName:a @@ -17031,7 +17031,7 @@ design: (work@bottom1) |vpiNet: \_logic_net: (work@top.inst[2][1][1].b), line:20:22, endln:20:23 |vpiParent: - \_module: work@my_module (work@top.inst[2][1][1]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 + \_module_inst: work@my_module (work@top.inst[2][1][1]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 |vpiTypespec: \_logic_typespec: , line:21:7, endln:21:7 |vpiName:b @@ -17039,17 +17039,17 @@ design: (work@bottom1) |vpiNet: \_logic_net: (work@top.inst[2][1][1].c), line:20:25, endln:20:26 |vpiParent: - \_module: work@my_module (work@top.inst[2][1][1]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 + \_module_inst: work@my_module (work@top.inst[2][1][1]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 |vpiTypespec: \_logic_typespec: , line:22:8, endln:22:8 |vpiName:c |vpiFullName:work@top.inst[2][1][1].c |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:26:1, endln:31:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:26:1, endln:31:10 |vpiPort: \_port: (a), line:20:19, endln:20:20 |vpiParent: - \_module: work@my_module (work@top.inst[2][1][1]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 + \_module_inst: work@my_module (work@top.inst[2][1][1]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 |vpiName:a |vpiDirection:1 |vpiHighConn: @@ -17073,7 +17073,7 @@ design: (work@bottom1) |vpiPort: \_port: (b), line:20:22, endln:20:23 |vpiParent: - \_module: work@my_module (work@top.inst[2][1][1]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 + \_module_inst: work@my_module (work@top.inst[2][1][1]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 |vpiName:b |vpiDirection:1 |vpiHighConn: @@ -17097,7 +17097,7 @@ design: (work@bottom1) |vpiPort: \_port: (c), line:20:25, endln:20:26 |vpiParent: - \_module: work@my_module (work@top.inst[2][1][1]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 + \_module_inst: work@my_module (work@top.inst[2][1][1]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 |vpiName:c |vpiDirection:2 |vpiHighConn: @@ -17146,10 +17146,10 @@ design: (work@bottom1) |vpiName:c |vpiActual: \_logic_net: (work@top.inst[2][1][1].c), line:20:25, endln:20:26 - |vpiModule: - \_module: work@my_module (work@top.inst[2][2][0]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 + |vpiModuleInst: + \_module_inst: work@my_module (work@top.inst[2][2][0]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:26:1, endln:31:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:26:1, endln:31:10 |vpiName:inst[2][2][0] |vpiFullName:work@top.inst[2][2][0] |vpiDefName:work@my_module @@ -17158,7 +17158,7 @@ design: (work@bottom1) |vpiNet: \_logic_net: (work@top.inst[2][2][0].a), line:20:19, endln:20:20 |vpiParent: - \_module: work@my_module (work@top.inst[2][2][0]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 + \_module_inst: work@my_module (work@top.inst[2][2][0]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 |vpiTypespec: \_logic_typespec: , line:21:7, endln:21:7 |vpiName:a @@ -17166,7 +17166,7 @@ design: (work@bottom1) |vpiNet: \_logic_net: (work@top.inst[2][2][0].b), line:20:22, endln:20:23 |vpiParent: - \_module: work@my_module (work@top.inst[2][2][0]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 + \_module_inst: work@my_module (work@top.inst[2][2][0]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 |vpiTypespec: \_logic_typespec: , line:21:7, endln:21:7 |vpiName:b @@ -17174,17 +17174,17 @@ design: (work@bottom1) |vpiNet: \_logic_net: (work@top.inst[2][2][0].c), line:20:25, endln:20:26 |vpiParent: - \_module: work@my_module (work@top.inst[2][2][0]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 + \_module_inst: work@my_module (work@top.inst[2][2][0]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 |vpiTypespec: \_logic_typespec: , line:22:8, endln:22:8 |vpiName:c |vpiFullName:work@top.inst[2][2][0].c |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:26:1, endln:31:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:26:1, endln:31:10 |vpiPort: \_port: (a), line:20:19, endln:20:20 |vpiParent: - \_module: work@my_module (work@top.inst[2][2][0]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 + \_module_inst: work@my_module (work@top.inst[2][2][0]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 |vpiName:a |vpiDirection:1 |vpiHighConn: @@ -17208,7 +17208,7 @@ design: (work@bottom1) |vpiPort: \_port: (b), line:20:22, endln:20:23 |vpiParent: - \_module: work@my_module (work@top.inst[2][2][0]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 + \_module_inst: work@my_module (work@top.inst[2][2][0]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 |vpiName:b |vpiDirection:1 |vpiHighConn: @@ -17232,7 +17232,7 @@ design: (work@bottom1) |vpiPort: \_port: (c), line:20:25, endln:20:26 |vpiParent: - \_module: work@my_module (work@top.inst[2][2][0]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 + \_module_inst: work@my_module (work@top.inst[2][2][0]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 |vpiName:c |vpiDirection:2 |vpiHighConn: @@ -17281,10 +17281,10 @@ design: (work@bottom1) |vpiName:c |vpiActual: \_logic_net: (work@top.inst[2][2][0].c), line:20:25, endln:20:26 - |vpiModule: - \_module: work@my_module (work@top.inst[2][2][1]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 + |vpiModuleInst: + \_module_inst: work@my_module (work@top.inst[2][2][1]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:26:1, endln:31:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:26:1, endln:31:10 |vpiName:inst[2][2][1] |vpiFullName:work@top.inst[2][2][1] |vpiDefName:work@my_module @@ -17293,7 +17293,7 @@ design: (work@bottom1) |vpiNet: \_logic_net: (work@top.inst[2][2][1].a), line:20:19, endln:20:20 |vpiParent: - \_module: work@my_module (work@top.inst[2][2][1]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 + \_module_inst: work@my_module (work@top.inst[2][2][1]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 |vpiTypespec: \_logic_typespec: , line:21:7, endln:21:7 |vpiName:a @@ -17301,7 +17301,7 @@ design: (work@bottom1) |vpiNet: \_logic_net: (work@top.inst[2][2][1].b), line:20:22, endln:20:23 |vpiParent: - \_module: work@my_module (work@top.inst[2][2][1]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 + \_module_inst: work@my_module (work@top.inst[2][2][1]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 |vpiTypespec: \_logic_typespec: , line:21:7, endln:21:7 |vpiName:b @@ -17309,17 +17309,17 @@ design: (work@bottom1) |vpiNet: \_logic_net: (work@top.inst[2][2][1].c), line:20:25, endln:20:26 |vpiParent: - \_module: work@my_module (work@top.inst[2][2][1]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 + \_module_inst: work@my_module (work@top.inst[2][2][1]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 |vpiTypespec: \_logic_typespec: , line:22:8, endln:22:8 |vpiName:c |vpiFullName:work@top.inst[2][2][1].c |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:26:1, endln:31:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:26:1, endln:31:10 |vpiPort: \_port: (a), line:20:19, endln:20:20 |vpiParent: - \_module: work@my_module (work@top.inst[2][2][1]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 + \_module_inst: work@my_module (work@top.inst[2][2][1]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 |vpiName:a |vpiDirection:1 |vpiHighConn: @@ -17343,7 +17343,7 @@ design: (work@bottom1) |vpiPort: \_port: (b), line:20:22, endln:20:23 |vpiParent: - \_module: work@my_module (work@top.inst[2][2][1]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 + \_module_inst: work@my_module (work@top.inst[2][2][1]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 |vpiName:b |vpiDirection:1 |vpiHighConn: @@ -17367,7 +17367,7 @@ design: (work@bottom1) |vpiPort: \_port: (c), line:20:25, endln:20:26 |vpiParent: - \_module: work@my_module (work@top.inst[2][2][1]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 + \_module_inst: work@my_module (work@top.inst[2][2][1]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 |vpiName:c |vpiDirection:2 |vpiHighConn: @@ -17416,10 +17416,10 @@ design: (work@bottom1) |vpiName:c |vpiActual: \_logic_net: (work@top.inst[2][2][1].c), line:20:25, endln:20:26 - |vpiModule: - \_module: work@my_module (work@top.inst[3][0][0]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 + |vpiModuleInst: + \_module_inst: work@my_module (work@top.inst[3][0][0]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:26:1, endln:31:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:26:1, endln:31:10 |vpiName:inst[3][0][0] |vpiFullName:work@top.inst[3][0][0] |vpiDefName:work@my_module @@ -17428,7 +17428,7 @@ design: (work@bottom1) |vpiNet: \_logic_net: (work@top.inst[3][0][0].a), line:20:19, endln:20:20 |vpiParent: - \_module: work@my_module (work@top.inst[3][0][0]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 + \_module_inst: work@my_module (work@top.inst[3][0][0]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 |vpiTypespec: \_logic_typespec: , line:21:7, endln:21:7 |vpiName:a @@ -17436,7 +17436,7 @@ design: (work@bottom1) |vpiNet: \_logic_net: (work@top.inst[3][0][0].b), line:20:22, endln:20:23 |vpiParent: - \_module: work@my_module (work@top.inst[3][0][0]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 + \_module_inst: work@my_module (work@top.inst[3][0][0]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 |vpiTypespec: \_logic_typespec: , line:21:7, endln:21:7 |vpiName:b @@ -17444,17 +17444,17 @@ design: (work@bottom1) |vpiNet: \_logic_net: (work@top.inst[3][0][0].c), line:20:25, endln:20:26 |vpiParent: - \_module: work@my_module (work@top.inst[3][0][0]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 + \_module_inst: work@my_module (work@top.inst[3][0][0]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 |vpiTypespec: \_logic_typespec: , line:22:8, endln:22:8 |vpiName:c |vpiFullName:work@top.inst[3][0][0].c |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:26:1, endln:31:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:26:1, endln:31:10 |vpiPort: \_port: (a), line:20:19, endln:20:20 |vpiParent: - \_module: work@my_module (work@top.inst[3][0][0]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 + \_module_inst: work@my_module (work@top.inst[3][0][0]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 |vpiName:a |vpiDirection:1 |vpiHighConn: @@ -17478,7 +17478,7 @@ design: (work@bottom1) |vpiPort: \_port: (b), line:20:22, endln:20:23 |vpiParent: - \_module: work@my_module (work@top.inst[3][0][0]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 + \_module_inst: work@my_module (work@top.inst[3][0][0]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 |vpiName:b |vpiDirection:1 |vpiHighConn: @@ -17502,7 +17502,7 @@ design: (work@bottom1) |vpiPort: \_port: (c), line:20:25, endln:20:26 |vpiParent: - \_module: work@my_module (work@top.inst[3][0][0]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 + \_module_inst: work@my_module (work@top.inst[3][0][0]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 |vpiName:c |vpiDirection:2 |vpiHighConn: @@ -17551,10 +17551,10 @@ design: (work@bottom1) |vpiName:c |vpiActual: \_logic_net: (work@top.inst[3][0][0].c), line:20:25, endln:20:26 - |vpiModule: - \_module: work@my_module (work@top.inst[3][0][1]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 + |vpiModuleInst: + \_module_inst: work@my_module (work@top.inst[3][0][1]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:26:1, endln:31:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:26:1, endln:31:10 |vpiName:inst[3][0][1] |vpiFullName:work@top.inst[3][0][1] |vpiDefName:work@my_module @@ -17563,7 +17563,7 @@ design: (work@bottom1) |vpiNet: \_logic_net: (work@top.inst[3][0][1].a), line:20:19, endln:20:20 |vpiParent: - \_module: work@my_module (work@top.inst[3][0][1]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 + \_module_inst: work@my_module (work@top.inst[3][0][1]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 |vpiTypespec: \_logic_typespec: , line:21:7, endln:21:7 |vpiName:a @@ -17571,7 +17571,7 @@ design: (work@bottom1) |vpiNet: \_logic_net: (work@top.inst[3][0][1].b), line:20:22, endln:20:23 |vpiParent: - \_module: work@my_module (work@top.inst[3][0][1]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 + \_module_inst: work@my_module (work@top.inst[3][0][1]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 |vpiTypespec: \_logic_typespec: , line:21:7, endln:21:7 |vpiName:b @@ -17579,17 +17579,17 @@ design: (work@bottom1) |vpiNet: \_logic_net: (work@top.inst[3][0][1].c), line:20:25, endln:20:26 |vpiParent: - \_module: work@my_module (work@top.inst[3][0][1]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 + \_module_inst: work@my_module (work@top.inst[3][0][1]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 |vpiTypespec: \_logic_typespec: , line:22:8, endln:22:8 |vpiName:c |vpiFullName:work@top.inst[3][0][1].c |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:26:1, endln:31:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:26:1, endln:31:10 |vpiPort: \_port: (a), line:20:19, endln:20:20 |vpiParent: - \_module: work@my_module (work@top.inst[3][0][1]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 + \_module_inst: work@my_module (work@top.inst[3][0][1]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 |vpiName:a |vpiDirection:1 |vpiHighConn: @@ -17613,7 +17613,7 @@ design: (work@bottom1) |vpiPort: \_port: (b), line:20:22, endln:20:23 |vpiParent: - \_module: work@my_module (work@top.inst[3][0][1]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 + \_module_inst: work@my_module (work@top.inst[3][0][1]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 |vpiName:b |vpiDirection:1 |vpiHighConn: @@ -17637,7 +17637,7 @@ design: (work@bottom1) |vpiPort: \_port: (c), line:20:25, endln:20:26 |vpiParent: - \_module: work@my_module (work@top.inst[3][0][1]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 + \_module_inst: work@my_module (work@top.inst[3][0][1]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 |vpiName:c |vpiDirection:2 |vpiHighConn: @@ -17686,10 +17686,10 @@ design: (work@bottom1) |vpiName:c |vpiActual: \_logic_net: (work@top.inst[3][0][1].c), line:20:25, endln:20:26 - |vpiModule: - \_module: work@my_module (work@top.inst[3][1][0]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 + |vpiModuleInst: + \_module_inst: work@my_module (work@top.inst[3][1][0]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:26:1, endln:31:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:26:1, endln:31:10 |vpiName:inst[3][1][0] |vpiFullName:work@top.inst[3][1][0] |vpiDefName:work@my_module @@ -17698,7 +17698,7 @@ design: (work@bottom1) |vpiNet: \_logic_net: (work@top.inst[3][1][0].a), line:20:19, endln:20:20 |vpiParent: - \_module: work@my_module (work@top.inst[3][1][0]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 + \_module_inst: work@my_module (work@top.inst[3][1][0]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 |vpiTypespec: \_logic_typespec: , line:21:7, endln:21:7 |vpiName:a @@ -17706,7 +17706,7 @@ design: (work@bottom1) |vpiNet: \_logic_net: (work@top.inst[3][1][0].b), line:20:22, endln:20:23 |vpiParent: - \_module: work@my_module (work@top.inst[3][1][0]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 + \_module_inst: work@my_module (work@top.inst[3][1][0]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 |vpiTypespec: \_logic_typespec: , line:21:7, endln:21:7 |vpiName:b @@ -17714,17 +17714,17 @@ design: (work@bottom1) |vpiNet: \_logic_net: (work@top.inst[3][1][0].c), line:20:25, endln:20:26 |vpiParent: - \_module: work@my_module (work@top.inst[3][1][0]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 + \_module_inst: work@my_module (work@top.inst[3][1][0]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 |vpiTypespec: \_logic_typespec: , line:22:8, endln:22:8 |vpiName:c |vpiFullName:work@top.inst[3][1][0].c |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:26:1, endln:31:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:26:1, endln:31:10 |vpiPort: \_port: (a), line:20:19, endln:20:20 |vpiParent: - \_module: work@my_module (work@top.inst[3][1][0]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 + \_module_inst: work@my_module (work@top.inst[3][1][0]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 |vpiName:a |vpiDirection:1 |vpiHighConn: @@ -17748,7 +17748,7 @@ design: (work@bottom1) |vpiPort: \_port: (b), line:20:22, endln:20:23 |vpiParent: - \_module: work@my_module (work@top.inst[3][1][0]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 + \_module_inst: work@my_module (work@top.inst[3][1][0]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 |vpiName:b |vpiDirection:1 |vpiHighConn: @@ -17772,7 +17772,7 @@ design: (work@bottom1) |vpiPort: \_port: (c), line:20:25, endln:20:26 |vpiParent: - \_module: work@my_module (work@top.inst[3][1][0]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 + \_module_inst: work@my_module (work@top.inst[3][1][0]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 |vpiName:c |vpiDirection:2 |vpiHighConn: @@ -17821,10 +17821,10 @@ design: (work@bottom1) |vpiName:c |vpiActual: \_logic_net: (work@top.inst[3][1][0].c), line:20:25, endln:20:26 - |vpiModule: - \_module: work@my_module (work@top.inst[3][1][1]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 + |vpiModuleInst: + \_module_inst: work@my_module (work@top.inst[3][1][1]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:26:1, endln:31:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:26:1, endln:31:10 |vpiName:inst[3][1][1] |vpiFullName:work@top.inst[3][1][1] |vpiDefName:work@my_module @@ -17833,7 +17833,7 @@ design: (work@bottom1) |vpiNet: \_logic_net: (work@top.inst[3][1][1].a), line:20:19, endln:20:20 |vpiParent: - \_module: work@my_module (work@top.inst[3][1][1]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 + \_module_inst: work@my_module (work@top.inst[3][1][1]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 |vpiTypespec: \_logic_typespec: , line:21:7, endln:21:7 |vpiName:a @@ -17841,7 +17841,7 @@ design: (work@bottom1) |vpiNet: \_logic_net: (work@top.inst[3][1][1].b), line:20:22, endln:20:23 |vpiParent: - \_module: work@my_module (work@top.inst[3][1][1]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 + \_module_inst: work@my_module (work@top.inst[3][1][1]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 |vpiTypespec: \_logic_typespec: , line:21:7, endln:21:7 |vpiName:b @@ -17849,17 +17849,17 @@ design: (work@bottom1) |vpiNet: \_logic_net: (work@top.inst[3][1][1].c), line:20:25, endln:20:26 |vpiParent: - \_module: work@my_module (work@top.inst[3][1][1]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 + \_module_inst: work@my_module (work@top.inst[3][1][1]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 |vpiTypespec: \_logic_typespec: , line:22:8, endln:22:8 |vpiName:c |vpiFullName:work@top.inst[3][1][1].c |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:26:1, endln:31:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:26:1, endln:31:10 |vpiPort: \_port: (a), line:20:19, endln:20:20 |vpiParent: - \_module: work@my_module (work@top.inst[3][1][1]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 + \_module_inst: work@my_module (work@top.inst[3][1][1]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 |vpiName:a |vpiDirection:1 |vpiHighConn: @@ -17883,7 +17883,7 @@ design: (work@bottom1) |vpiPort: \_port: (b), line:20:22, endln:20:23 |vpiParent: - \_module: work@my_module (work@top.inst[3][1][1]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 + \_module_inst: work@my_module (work@top.inst[3][1][1]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 |vpiName:b |vpiDirection:1 |vpiHighConn: @@ -17907,7 +17907,7 @@ design: (work@bottom1) |vpiPort: \_port: (c), line:20:25, endln:20:26 |vpiParent: - \_module: work@my_module (work@top.inst[3][1][1]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 + \_module_inst: work@my_module (work@top.inst[3][1][1]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 |vpiName:c |vpiDirection:2 |vpiHighConn: @@ -17956,10 +17956,10 @@ design: (work@bottom1) |vpiName:c |vpiActual: \_logic_net: (work@top.inst[3][1][1].c), line:20:25, endln:20:26 - |vpiModule: - \_module: work@my_module (work@top.inst[3][2][0]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 + |vpiModuleInst: + \_module_inst: work@my_module (work@top.inst[3][2][0]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:26:1, endln:31:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:26:1, endln:31:10 |vpiName:inst[3][2][0] |vpiFullName:work@top.inst[3][2][0] |vpiDefName:work@my_module @@ -17968,7 +17968,7 @@ design: (work@bottom1) |vpiNet: \_logic_net: (work@top.inst[3][2][0].a), line:20:19, endln:20:20 |vpiParent: - \_module: work@my_module (work@top.inst[3][2][0]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 + \_module_inst: work@my_module (work@top.inst[3][2][0]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 |vpiTypespec: \_logic_typespec: , line:21:7, endln:21:7 |vpiName:a @@ -17976,7 +17976,7 @@ design: (work@bottom1) |vpiNet: \_logic_net: (work@top.inst[3][2][0].b), line:20:22, endln:20:23 |vpiParent: - \_module: work@my_module (work@top.inst[3][2][0]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 + \_module_inst: work@my_module (work@top.inst[3][2][0]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 |vpiTypespec: \_logic_typespec: , line:21:7, endln:21:7 |vpiName:b @@ -17984,17 +17984,17 @@ design: (work@bottom1) |vpiNet: \_logic_net: (work@top.inst[3][2][0].c), line:20:25, endln:20:26 |vpiParent: - \_module: work@my_module (work@top.inst[3][2][0]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 + \_module_inst: work@my_module (work@top.inst[3][2][0]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 |vpiTypespec: \_logic_typespec: , line:22:8, endln:22:8 |vpiName:c |vpiFullName:work@top.inst[3][2][0].c |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:26:1, endln:31:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:26:1, endln:31:10 |vpiPort: \_port: (a), line:20:19, endln:20:20 |vpiParent: - \_module: work@my_module (work@top.inst[3][2][0]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 + \_module_inst: work@my_module (work@top.inst[3][2][0]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 |vpiName:a |vpiDirection:1 |vpiHighConn: @@ -18018,7 +18018,7 @@ design: (work@bottom1) |vpiPort: \_port: (b), line:20:22, endln:20:23 |vpiParent: - \_module: work@my_module (work@top.inst[3][2][0]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 + \_module_inst: work@my_module (work@top.inst[3][2][0]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 |vpiName:b |vpiDirection:1 |vpiHighConn: @@ -18042,7 +18042,7 @@ design: (work@bottom1) |vpiPort: \_port: (c), line:20:25, endln:20:26 |vpiParent: - \_module: work@my_module (work@top.inst[3][2][0]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 + \_module_inst: work@my_module (work@top.inst[3][2][0]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 |vpiName:c |vpiDirection:2 |vpiHighConn: @@ -18091,10 +18091,10 @@ design: (work@bottom1) |vpiName:c |vpiActual: \_logic_net: (work@top.inst[3][2][0].c), line:20:25, endln:20:26 - |vpiModule: - \_module: work@my_module (work@top.inst[3][2][1]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 + |vpiModuleInst: + \_module_inst: work@my_module (work@top.inst[3][2][1]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:26:1, endln:31:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:26:1, endln:31:10 |vpiName:inst[3][2][1] |vpiFullName:work@top.inst[3][2][1] |vpiDefName:work@my_module @@ -18103,7 +18103,7 @@ design: (work@bottom1) |vpiNet: \_logic_net: (work@top.inst[3][2][1].a), line:20:19, endln:20:20 |vpiParent: - \_module: work@my_module (work@top.inst[3][2][1]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 + \_module_inst: work@my_module (work@top.inst[3][2][1]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 |vpiTypespec: \_logic_typespec: , line:21:7, endln:21:7 |vpiName:a @@ -18111,7 +18111,7 @@ design: (work@bottom1) |vpiNet: \_logic_net: (work@top.inst[3][2][1].b), line:20:22, endln:20:23 |vpiParent: - \_module: work@my_module (work@top.inst[3][2][1]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 + \_module_inst: work@my_module (work@top.inst[3][2][1]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 |vpiTypespec: \_logic_typespec: , line:21:7, endln:21:7 |vpiName:b @@ -18119,17 +18119,17 @@ design: (work@bottom1) |vpiNet: \_logic_net: (work@top.inst[3][2][1].c), line:20:25, endln:20:26 |vpiParent: - \_module: work@my_module (work@top.inst[3][2][1]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 + \_module_inst: work@my_module (work@top.inst[3][2][1]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 |vpiTypespec: \_logic_typespec: , line:22:8, endln:22:8 |vpiName:c |vpiFullName:work@top.inst[3][2][1].c |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:26:1, endln:31:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:26:1, endln:31:10 |vpiPort: \_port: (a), line:20:19, endln:20:20 |vpiParent: - \_module: work@my_module (work@top.inst[3][2][1]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 + \_module_inst: work@my_module (work@top.inst[3][2][1]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 |vpiName:a |vpiDirection:1 |vpiHighConn: @@ -18153,7 +18153,7 @@ design: (work@bottom1) |vpiPort: \_port: (b), line:20:22, endln:20:23 |vpiParent: - \_module: work@my_module (work@top.inst[3][2][1]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 + \_module_inst: work@my_module (work@top.inst[3][2][1]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 |vpiName:b |vpiDirection:1 |vpiHighConn: @@ -18177,7 +18177,7 @@ design: (work@bottom1) |vpiPort: \_port: (c), line:20:25, endln:20:26 |vpiParent: - \_module: work@my_module (work@top.inst[3][2][1]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 + \_module_inst: work@my_module (work@top.inst[3][2][1]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 |vpiName:c |vpiDirection:2 |vpiHighConn: @@ -18226,10 +18226,10 @@ design: (work@bottom1) |vpiName:c |vpiActual: \_logic_net: (work@top.inst[3][2][1].c), line:20:25, endln:20:26 - |vpiModule: - \_module: work@my_module (work@top.inst1), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:30:3, endln:30:30 + |vpiModuleInst: + \_module_inst: work@my_module (work@top.inst1), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:30:3, endln:30:30 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:26:1, endln:31:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:26:1, endln:31:10 |vpiName:inst1 |vpiFullName:work@top.inst1 |vpiDefName:work@my_module @@ -18238,7 +18238,7 @@ design: (work@bottom1) |vpiNet: \_logic_net: (work@top.inst1.a), line:20:19, endln:20:20 |vpiParent: - \_module: work@my_module (work@top.inst1), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:30:3, endln:30:30 + \_module_inst: work@my_module (work@top.inst1), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:30:3, endln:30:30 |vpiTypespec: \_logic_typespec: , line:21:7, endln:21:7 |vpiName:a @@ -18246,7 +18246,7 @@ design: (work@bottom1) |vpiNet: \_logic_net: (work@top.inst1.b), line:20:22, endln:20:23 |vpiParent: - \_module: work@my_module (work@top.inst1), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:30:3, endln:30:30 + \_module_inst: work@my_module (work@top.inst1), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:30:3, endln:30:30 |vpiTypespec: \_logic_typespec: , line:21:7, endln:21:7 |vpiName:b @@ -18254,17 +18254,17 @@ design: (work@bottom1) |vpiNet: \_logic_net: (work@top.inst1.c), line:20:25, endln:20:26 |vpiParent: - \_module: work@my_module (work@top.inst1), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:30:3, endln:30:30 + \_module_inst: work@my_module (work@top.inst1), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:30:3, endln:30:30 |vpiTypespec: \_logic_typespec: , line:22:8, endln:22:8 |vpiName:c |vpiFullName:work@top.inst1.c |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:26:1, endln:31:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:26:1, endln:31:10 |vpiPort: \_port: (a), line:20:19, endln:20:20 |vpiParent: - \_module: work@my_module (work@top.inst1), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:30:3, endln:30:30 + \_module_inst: work@my_module (work@top.inst1), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:30:3, endln:30:30 |vpiName:a |vpiDirection:1 |vpiHighConn: @@ -18284,7 +18284,7 @@ design: (work@bottom1) |vpiPort: \_port: (b), line:20:22, endln:20:23 |vpiParent: - \_module: work@my_module (work@top.inst1), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:30:3, endln:30:30 + \_module_inst: work@my_module (work@top.inst1), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:30:3, endln:30:30 |vpiName:b |vpiDirection:1 |vpiHighConn: @@ -18304,7 +18304,7 @@ design: (work@bottom1) |vpiPort: \_port: (c), line:20:25, endln:20:26 |vpiParent: - \_module: work@my_module (work@top.inst1), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:30:3, endln:30:30 + \_module_inst: work@my_module (work@top.inst1), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:30:3, endln:30:30 |vpiName:c |vpiDirection:2 |vpiHighConn: @@ -18352,7 +18352,7 @@ design: (work@bottom1) |vpiModuleArray: \_module_array: (work@my_module), line:29:13, endln:29:17 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:26:1, endln:31:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:26:1, endln:31:10 |vpiName:inst |vpiFullName:work@my_module |vpiRange: @@ -18409,64 +18409,64 @@ design: (work@bottom1) |vpiSize:64 |UINT:0 |vpiConstType:9 - |vpiModule: - \_module: work@my_module (work@top.inst[0][0][0]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 - |vpiModule: - \_module: work@my_module (work@top.inst[0][0][1]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 - |vpiModule: - \_module: work@my_module (work@top.inst[0][1][0]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 - |vpiModule: - \_module: work@my_module (work@top.inst[0][1][1]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 - |vpiModule: - \_module: work@my_module (work@top.inst[0][2][0]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 - |vpiModule: - \_module: work@my_module (work@top.inst[0][2][1]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 - |vpiModule: - \_module: work@my_module (work@top.inst[1][0][0]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 - |vpiModule: - \_module: work@my_module (work@top.inst[1][0][1]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 - |vpiModule: - \_module: work@my_module (work@top.inst[1][1][0]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 - |vpiModule: - \_module: work@my_module (work@top.inst[1][1][1]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 - |vpiModule: - \_module: work@my_module (work@top.inst[1][2][0]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 - |vpiModule: - \_module: work@my_module (work@top.inst[1][2][1]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 - |vpiModule: - \_module: work@my_module (work@top.inst[2][0][0]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 - |vpiModule: - \_module: work@my_module (work@top.inst[2][0][1]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 - |vpiModule: - \_module: work@my_module (work@top.inst[2][1][0]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 - |vpiModule: - \_module: work@my_module (work@top.inst[2][1][1]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 - |vpiModule: - \_module: work@my_module (work@top.inst[2][2][0]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 - |vpiModule: - \_module: work@my_module (work@top.inst[2][2][1]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 - |vpiModule: - \_module: work@my_module (work@top.inst[3][0][0]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 - |vpiModule: - \_module: work@my_module (work@top.inst[3][0][1]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 - |vpiModule: - \_module: work@my_module (work@top.inst[3][1][0]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 - |vpiModule: - \_module: work@my_module (work@top.inst[3][1][1]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 - |vpiModule: - \_module: work@my_module (work@top.inst[3][2][0]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 - |vpiModule: - \_module: work@my_module (work@top.inst[3][2][1]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 + |vpiModuleInst: + \_module_inst: work@my_module (work@top.inst[0][0][0]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 + |vpiModuleInst: + \_module_inst: work@my_module (work@top.inst[0][0][1]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 + |vpiModuleInst: + \_module_inst: work@my_module (work@top.inst[0][1][0]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 + |vpiModuleInst: + \_module_inst: work@my_module (work@top.inst[0][1][1]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 + |vpiModuleInst: + \_module_inst: work@my_module (work@top.inst[0][2][0]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 + |vpiModuleInst: + \_module_inst: work@my_module (work@top.inst[0][2][1]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 + |vpiModuleInst: + \_module_inst: work@my_module (work@top.inst[1][0][0]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 + |vpiModuleInst: + \_module_inst: work@my_module (work@top.inst[1][0][1]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 + |vpiModuleInst: + \_module_inst: work@my_module (work@top.inst[1][1][0]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 + |vpiModuleInst: + \_module_inst: work@my_module (work@top.inst[1][1][1]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 + |vpiModuleInst: + \_module_inst: work@my_module (work@top.inst[1][2][0]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 + |vpiModuleInst: + \_module_inst: work@my_module (work@top.inst[1][2][1]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 + |vpiModuleInst: + \_module_inst: work@my_module (work@top.inst[2][0][0]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 + |vpiModuleInst: + \_module_inst: work@my_module (work@top.inst[2][0][1]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 + |vpiModuleInst: + \_module_inst: work@my_module (work@top.inst[2][1][0]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 + |vpiModuleInst: + \_module_inst: work@my_module (work@top.inst[2][1][1]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 + |vpiModuleInst: + \_module_inst: work@my_module (work@top.inst[2][2][0]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 + |vpiModuleInst: + \_module_inst: work@my_module (work@top.inst[2][2][1]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 + |vpiModuleInst: + \_module_inst: work@my_module (work@top.inst[3][0][0]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 + |vpiModuleInst: + \_module_inst: work@my_module (work@top.inst[3][0][1]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 + |vpiModuleInst: + \_module_inst: work@my_module (work@top.inst[3][1][0]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 + |vpiModuleInst: + \_module_inst: work@my_module (work@top.inst[3][1][1]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 + |vpiModuleInst: + \_module_inst: work@my_module (work@top.inst[3][2][0]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 + |vpiModuleInst: + \_module_inst: work@my_module (work@top.inst[3][2][1]), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:29:3, endln:29:44 |vpiElemTypespec: \_module_typespec: (my_module), line:29:3, endln:29:12 |vpiName:my_module |uhdmtopModules: -\_module: work@test (work@test), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:35:1, endln:76:10 +\_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:35:1, endln:76:10 |vpiName:work@test |vpiParameter: \_parameter: (work@test.POWER1), line:37:13, endln:37:19 |vpiParent: - \_module: work@test (work@test), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:35:1, endln:76:10 + \_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:35:1, endln:76:10 |UINT:1 |vpiTypespec: \_int_typespec: @@ -18477,7 +18477,7 @@ design: (work@bottom1) |vpiParameter: \_parameter: (work@test.POWER2), line:38:13, endln:38:19 |vpiParent: - \_module: work@test (work@test), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:35:1, endln:76:10 + \_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:35:1, endln:76:10 |UINT:1 |vpiTypespec: \_int_typespec: @@ -18488,7 +18488,7 @@ design: (work@bottom1) |vpiParamAssign: \_param_assign: , line:37:13, endln:37:23 |vpiParent: - \_module: work@test (work@test), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:35:1, endln:76:10 + \_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:35:1, endln:76:10 |vpiRhs: \_constant: , line:37:22, endln:37:23 |vpiDecompile:1 @@ -18502,7 +18502,7 @@ design: (work@bottom1) |vpiParamAssign: \_param_assign: , line:38:13, endln:38:23 |vpiParent: - \_module: work@test (work@test), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:35:1, endln:76:10 + \_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:35:1, endln:76:10 |vpiRhs: \_constant: , line:38:22, endln:38:23 |vpiDecompile:1 @@ -18518,20 +18518,20 @@ design: (work@bottom1) |vpiNet: \_logic_net: (work@test.a), line:35:13, endln:35:14 |vpiParent: - \_module: work@test (work@test), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:35:1, endln:76:10 + \_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:35:1, endln:76:10 |vpiName:a |vpiFullName:work@test.a |vpiNet: \_logic_net: (work@test.b), line:35:16, endln:35:17 |vpiParent: - \_module: work@test (work@test), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:35:1, endln:76:10 + \_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:35:1, endln:76:10 |vpiName:b |vpiFullName:work@test.b |vpiTopModule:1 |vpiPort: \_port: (a), line:35:13, endln:35:14 |vpiParent: - \_module: work@test (work@test), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:35:1, endln:76:10 + \_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:35:1, endln:76:10 |vpiName:a |vpiDirection:3 |vpiLowConn: @@ -18543,7 +18543,7 @@ design: (work@bottom1) |vpiPort: \_port: (b), line:35:16, endln:35:17 |vpiParent: - \_module: work@test (work@test), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:35:1, endln:76:10 + \_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:35:1, endln:76:10 |vpiName:b |vpiDirection:3 |vpiLowConn: @@ -18555,7 +18555,7 @@ design: (work@bottom1) |vpiGenScopeArray: \_gen_scope_array: (work@test.g1), line:44:7, endln:44:19 |vpiParent: - \_module: work@test (work@test), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:35:1, endln:76:10 + \_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:35:1, endln:76:10 |vpiName:g1 |vpiFullName:work@test.g1 |vpiGenScope: @@ -18601,7 +18601,7 @@ design: (work@bottom1) |vpiGenScopeArray: \_gen_scope_array: (work@test.g1), line:51:5, endln:55:8 |vpiParent: - \_module: work@test (work@test), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:35:1, endln:76:10 + \_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:35:1, endln:76:10 |vpiName:g1 |vpiFullName:work@test.g1 |vpiGenScope: @@ -18658,7 +18658,7 @@ design: (work@bottom1) |vpiGenScopeArray: \_gen_scope_array: (work@test.u1), line:62:6, endln:72:14 |vpiParent: - \_module: work@test (work@test), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:35:1, endln:76:10 + \_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:35:1, endln:76:10 |vpiName:u1 |vpiFullName:work@test.u1 |vpiGenScope: @@ -18725,7 +18725,7 @@ design: (work@bottom1) |vpiPrimitive: \_gate: work@and (work@test.u0), line:39:7, endln:39:14 |vpiParent: - \_module: work@test (work@test), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:35:1, endln:76:10 + \_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:35:1, endln:76:10 |vpiDefName:work@and |vpiName:u0 |vpiFullName:work@test.u0 @@ -18760,7 +18760,7 @@ design: (work@bottom1) |vpiPrimitive: \_gate: work@and (work@test.u4), line:58:6, endln:58:13 |vpiParent: - \_module: work@test (work@test), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:35:1, endln:76:10 + \_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:35:1, endln:76:10 |vpiDefName:work@and |vpiName:u4 |vpiFullName:work@test.u4 @@ -18793,21 +18793,21 @@ design: (work@bottom1) |vpiActual: \_logic_net: (work@test.b), line:35:16, endln:35:17 |uhdmtopModules: -\_module: work@small_top (work@small_top), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:1:1, endln:3:10 +\_module_inst: work@small_top (work@small_top), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:1:1, endln:3:10 |vpiName:work@small_top |vpiDefName:work@small_top |vpiTop:1 |vpiTopModule:1 - |vpiModule: - \_module: work@small_test (work@small_top.u1), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:2:4, endln:2:29 + |vpiModuleInst: + \_module_inst: work@small_test (work@small_top.u1), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:2:4, endln:2:29 |vpiParent: - \_module: work@small_top (work@small_top), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:1:1, endln:3:10 + \_module_inst: work@small_top (work@small_top), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:1:1, endln:3:10 |vpiName:u1 |vpiFullName:work@small_top.u1 |vpiParameter: \_parameter: (work@small_top.u1.SIZE), line:8:27, endln:8:31 |vpiParent: - \_module: work@small_test (work@small_top.u1), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:2:4, endln:2:29 + \_module_inst: work@small_test (work@small_top.u1), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:2:4, endln:2:29 |REAL:10.000000 |vpiTypespec: \_int_typespec: , line:8:14, endln:8:20 @@ -18839,7 +18839,7 @@ design: (work@bottom1) |vpiParameter: \_parameter: (work@small_top.u1.dummy), line:9:14, endln:9:19 |vpiParent: - \_module: work@small_test (work@small_top.u1), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:2:4, endln:2:29 + \_module_inst: work@small_test (work@small_top.u1), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:2:4, endln:2:29 |UINT:5 |vpiTypespec: \_int_typespec: @@ -18850,7 +18850,7 @@ design: (work@bottom1) |vpiParameter: \_parameter: (work@small_top.u1.p1), line:10:11, endln:10:13 |vpiParent: - \_module: work@small_test (work@small_top.u1), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:2:4, endln:2:29 + \_module_inst: work@small_test (work@small_top.u1), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:2:4, endln:2:29 |BIN:100 |vpiTypespec: \_int_typespec: @@ -18875,7 +18875,7 @@ design: (work@bottom1) |vpiParamAssign: \_param_assign: , line:8:27, endln:8:37 |vpiParent: - \_module: work@small_test (work@small_top.u1), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:2:4, endln:2:29 + \_module_inst: work@small_test (work@small_top.u1), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:2:4, endln:2:29 |vpiOverriden:1 |vpiRhs: \_constant: , line:8:34, endln:8:37 @@ -18890,7 +18890,7 @@ design: (work@bottom1) |vpiParamAssign: \_param_assign: , line:9:14, endln:9:23 |vpiParent: - \_module: work@small_test (work@small_top.u1), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:2:4, endln:2:29 + \_module_inst: work@small_test (work@small_top.u1), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:2:4, endln:2:29 |vpiOverriden:1 |vpiRhs: \_constant: , line:9:22, endln:9:23 @@ -18905,7 +18905,7 @@ design: (work@bottom1) |vpiParamAssign: \_param_assign: , line:10:11, endln:10:23 |vpiParent: - \_module: work@small_test (work@small_top.u1), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:2:4, endln:2:29 + \_module_inst: work@small_test (work@small_top.u1), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:2:4, endln:2:29 |vpiRhs: \_constant: , line:10:16, endln:10:23 |vpiDecompile:13'b100 @@ -18920,11 +18920,11 @@ design: (work@bottom1) |vpiDefFile:${SURELOG_DIR}/tests/UnitElab/small.v |vpiDefLineNo:5 |vpiInstance: - \_module: work@small_top (work@small_top), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:1:1, endln:3:10 + \_module_inst: work@small_top (work@small_top), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:1:1, endln:3:10 |vpiGenScopeArray: \_gen_scope_array: (work@small_top.u1.B1[0]), line:17:1, endln:51:4 |vpiParent: - \_module: work@small_test (work@small_top.u1), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:2:4, endln:2:29 + \_module_inst: work@small_test (work@small_top.u1), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:2:4, endln:2:29 |vpiName:B1[0] |vpiFullName:work@small_top.u1.B1[0] |vpiGenScope: @@ -18942,8 +18942,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:i |vpiFullName:work@small_top.u1.B1[0].i - |vpiModule: - \_module: work@small_top.u1.B1[0]::M1 (work@small_top.u1.B1[0].N1), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:20:1, endln:20:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[0]::M1 (work@small_top.u1.B1[0].N1), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:20:1, endln:20:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[0]) |vpiName:N1 @@ -18970,8 +18970,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:j |vpiFullName:work@small_top.u1.B1[0].B2[0].j - |vpiModule: - \_module: work@small_top.u1.B1[0].B2[0]::M2 (work@small_top.u1.B1[0].B2[0].N2), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:26:1, endln:26:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[0].B2[0]::M2 (work@small_top.u1.B1[0].B2[0].N2), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:26:1, endln:26:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[0].B2[0]) |vpiName:N2 @@ -18998,8 +18998,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[0].B2[0].B3[0].k - |vpiModule: - \_module: work@small_top.u1.B1[0].B2[0].B3[0]::M3 (work@small_top.u1.B1[0].B2[0].B3[0].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[0].B2[0].B3[0]::M3 (work@small_top.u1.B1[0].B2[0].B3[0].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[0].B2[0].B3[0]) |vpiName:N3 @@ -19026,8 +19026,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[0].B2[0].B3[1].k - |vpiModule: - \_module: work@small_top.u1.B1[0].B2[0].B3[1]::M3 (work@small_top.u1.B1[0].B2[0].B3[1].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[0].B2[0].B3[1]::M3 (work@small_top.u1.B1[0].B2[0].B3[1].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[0].B2[0].B3[1]) |vpiName:N3 @@ -19054,8 +19054,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[0].B2[0].B3[2].k - |vpiModule: - \_module: work@small_top.u1.B1[0].B2[0].B3[2]::M3 (work@small_top.u1.B1[0].B2[0].B3[2].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[0].B2[0].B3[2]::M3 (work@small_top.u1.B1[0].B2[0].B3[2].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[0].B2[0].B3[2]) |vpiName:N3 @@ -19082,8 +19082,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[0].B2[0].B3[3].k - |vpiModule: - \_module: work@small_top.u1.B1[0].B2[0].B3[3]::M3 (work@small_top.u1.B1[0].B2[0].B3[3].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[0].B2[0].B3[3]::M3 (work@small_top.u1.B1[0].B2[0].B3[3].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[0].B2[0].B3[3]) |vpiName:N3 @@ -19110,8 +19110,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[0].B2[0].B3[4].k - |vpiModule: - \_module: work@small_top.u1.B1[0].B2[0].B3[4]::M3 (work@small_top.u1.B1[0].B2[0].B3[4].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[0].B2[0].B3[4]::M3 (work@small_top.u1.B1[0].B2[0].B3[4].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[0].B2[0].B3[4]) |vpiName:N3 @@ -19138,8 +19138,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[0].B2[0].B3[5].k - |vpiModule: - \_module: work@small_top.u1.B1[0].B2[0].B3[5]::M3 (work@small_top.u1.B1[0].B2[0].B3[5].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[0].B2[0].B3[5]::M3 (work@small_top.u1.B1[0].B2[0].B3[5].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[0].B2[0].B3[5]) |vpiName:N3 @@ -19166,8 +19166,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[0].B2[0].B3[6].k - |vpiModule: - \_module: work@small_top.u1.B1[0].B2[0].B3[6]::M3 (work@small_top.u1.B1[0].B2[0].B3[6].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[0].B2[0].B3[6]::M3 (work@small_top.u1.B1[0].B2[0].B3[6].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[0].B2[0].B3[6]) |vpiName:N3 @@ -19194,8 +19194,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[0].B2[0].B3[7].k - |vpiModule: - \_module: work@small_top.u1.B1[0].B2[0].B3[7]::M3 (work@small_top.u1.B1[0].B2[0].B3[7].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[0].B2[0].B3[7]::M3 (work@small_top.u1.B1[0].B2[0].B3[7].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[0].B2[0].B3[7]) |vpiName:N3 @@ -19222,8 +19222,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[0].B2[0].B3[8].k - |vpiModule: - \_module: work@small_top.u1.B1[0].B2[0].B3[8]::M3 (work@small_top.u1.B1[0].B2[0].B3[8].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[0].B2[0].B3[8]::M3 (work@small_top.u1.B1[0].B2[0].B3[8].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[0].B2[0].B3[8]) |vpiName:N3 @@ -19250,8 +19250,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[0].B2[0].B3[9].k - |vpiModule: - \_module: work@small_top.u1.B1[0].B2[0].B3[9]::M3 (work@small_top.u1.B1[0].B2[0].B3[9].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[0].B2[0].B3[9]::M3 (work@small_top.u1.B1[0].B2[0].B3[9].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[0].B2[0].B3[9]) |vpiName:N3 @@ -19278,8 +19278,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:j |vpiFullName:work@small_top.u1.B1[0].B2[1].j - |vpiModule: - \_module: work@small_top.u1.B1[0].B2[1]::M2 (work@small_top.u1.B1[0].B2[1].N2), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:26:1, endln:26:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[0].B2[1]::M2 (work@small_top.u1.B1[0].B2[1].N2), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:26:1, endln:26:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[0].B2[1]) |vpiName:N2 @@ -19306,8 +19306,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[0].B2[1].B3[0].k - |vpiModule: - \_module: work@small_top.u1.B1[0].B2[1].B3[0]::M3 (work@small_top.u1.B1[0].B2[1].B3[0].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[0].B2[1].B3[0]::M3 (work@small_top.u1.B1[0].B2[1].B3[0].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[0].B2[1].B3[0]) |vpiName:N3 @@ -19334,8 +19334,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[0].B2[1].B3[1].k - |vpiModule: - \_module: work@small_top.u1.B1[0].B2[1].B3[1]::M3 (work@small_top.u1.B1[0].B2[1].B3[1].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[0].B2[1].B3[1]::M3 (work@small_top.u1.B1[0].B2[1].B3[1].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[0].B2[1].B3[1]) |vpiName:N3 @@ -19362,8 +19362,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[0].B2[1].B3[2].k - |vpiModule: - \_module: work@small_top.u1.B1[0].B2[1].B3[2]::M3 (work@small_top.u1.B1[0].B2[1].B3[2].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[0].B2[1].B3[2]::M3 (work@small_top.u1.B1[0].B2[1].B3[2].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[0].B2[1].B3[2]) |vpiName:N3 @@ -19390,8 +19390,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[0].B2[1].B3[3].k - |vpiModule: - \_module: work@small_top.u1.B1[0].B2[1].B3[3]::M3 (work@small_top.u1.B1[0].B2[1].B3[3].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[0].B2[1].B3[3]::M3 (work@small_top.u1.B1[0].B2[1].B3[3].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[0].B2[1].B3[3]) |vpiName:N3 @@ -19418,8 +19418,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[0].B2[1].B3[4].k - |vpiModule: - \_module: work@small_top.u1.B1[0].B2[1].B3[4]::M3 (work@small_top.u1.B1[0].B2[1].B3[4].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[0].B2[1].B3[4]::M3 (work@small_top.u1.B1[0].B2[1].B3[4].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[0].B2[1].B3[4]) |vpiName:N3 @@ -19446,8 +19446,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[0].B2[1].B3[5].k - |vpiModule: - \_module: work@small_top.u1.B1[0].B2[1].B3[5]::M3 (work@small_top.u1.B1[0].B2[1].B3[5].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[0].B2[1].B3[5]::M3 (work@small_top.u1.B1[0].B2[1].B3[5].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[0].B2[1].B3[5]) |vpiName:N3 @@ -19474,8 +19474,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[0].B2[1].B3[6].k - |vpiModule: - \_module: work@small_top.u1.B1[0].B2[1].B3[6]::M3 (work@small_top.u1.B1[0].B2[1].B3[6].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[0].B2[1].B3[6]::M3 (work@small_top.u1.B1[0].B2[1].B3[6].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[0].B2[1].B3[6]) |vpiName:N3 @@ -19502,8 +19502,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[0].B2[1].B3[7].k - |vpiModule: - \_module: work@small_top.u1.B1[0].B2[1].B3[7]::M3 (work@small_top.u1.B1[0].B2[1].B3[7].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[0].B2[1].B3[7]::M3 (work@small_top.u1.B1[0].B2[1].B3[7].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[0].B2[1].B3[7]) |vpiName:N3 @@ -19530,8 +19530,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[0].B2[1].B3[8].k - |vpiModule: - \_module: work@small_top.u1.B1[0].B2[1].B3[8]::M3 (work@small_top.u1.B1[0].B2[1].B3[8].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[0].B2[1].B3[8]::M3 (work@small_top.u1.B1[0].B2[1].B3[8].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[0].B2[1].B3[8]) |vpiName:N3 @@ -19558,8 +19558,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[0].B2[1].B3[9].k - |vpiModule: - \_module: work@small_top.u1.B1[0].B2[1].B3[9]::M3 (work@small_top.u1.B1[0].B2[1].B3[9].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[0].B2[1].B3[9]::M3 (work@small_top.u1.B1[0].B2[1].B3[9].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[0].B2[1].B3[9]) |vpiName:N3 @@ -19586,8 +19586,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:j |vpiFullName:work@small_top.u1.B1[0].B2[2].j - |vpiModule: - \_module: work@small_top.u1.B1[0].B2[2]::M2 (work@small_top.u1.B1[0].B2[2].N2), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:26:1, endln:26:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[0].B2[2]::M2 (work@small_top.u1.B1[0].B2[2].N2), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:26:1, endln:26:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[0].B2[2]) |vpiName:N2 @@ -19614,8 +19614,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[0].B2[2].B3[0].k - |vpiModule: - \_module: work@small_top.u1.B1[0].B2[2].B3[0]::M3 (work@small_top.u1.B1[0].B2[2].B3[0].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[0].B2[2].B3[0]::M3 (work@small_top.u1.B1[0].B2[2].B3[0].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[0].B2[2].B3[0]) |vpiName:N3 @@ -19642,8 +19642,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[0].B2[2].B3[1].k - |vpiModule: - \_module: work@small_top.u1.B1[0].B2[2].B3[1]::M3 (work@small_top.u1.B1[0].B2[2].B3[1].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[0].B2[2].B3[1]::M3 (work@small_top.u1.B1[0].B2[2].B3[1].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[0].B2[2].B3[1]) |vpiName:N3 @@ -19670,8 +19670,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[0].B2[2].B3[2].k - |vpiModule: - \_module: work@small_top.u1.B1[0].B2[2].B3[2]::M3 (work@small_top.u1.B1[0].B2[2].B3[2].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[0].B2[2].B3[2]::M3 (work@small_top.u1.B1[0].B2[2].B3[2].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[0].B2[2].B3[2]) |vpiName:N3 @@ -19698,8 +19698,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[0].B2[2].B3[3].k - |vpiModule: - \_module: work@small_top.u1.B1[0].B2[2].B3[3]::M3 (work@small_top.u1.B1[0].B2[2].B3[3].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[0].B2[2].B3[3]::M3 (work@small_top.u1.B1[0].B2[2].B3[3].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[0].B2[2].B3[3]) |vpiName:N3 @@ -19726,8 +19726,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[0].B2[2].B3[4].k - |vpiModule: - \_module: work@small_top.u1.B1[0].B2[2].B3[4]::M3 (work@small_top.u1.B1[0].B2[2].B3[4].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[0].B2[2].B3[4]::M3 (work@small_top.u1.B1[0].B2[2].B3[4].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[0].B2[2].B3[4]) |vpiName:N3 @@ -19754,8 +19754,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[0].B2[2].B3[5].k - |vpiModule: - \_module: work@small_top.u1.B1[0].B2[2].B3[5]::M3 (work@small_top.u1.B1[0].B2[2].B3[5].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[0].B2[2].B3[5]::M3 (work@small_top.u1.B1[0].B2[2].B3[5].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[0].B2[2].B3[5]) |vpiName:N3 @@ -19782,8 +19782,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[0].B2[2].B3[6].k - |vpiModule: - \_module: work@small_top.u1.B1[0].B2[2].B3[6]::M3 (work@small_top.u1.B1[0].B2[2].B3[6].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[0].B2[2].B3[6]::M3 (work@small_top.u1.B1[0].B2[2].B3[6].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[0].B2[2].B3[6]) |vpiName:N3 @@ -19810,8 +19810,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[0].B2[2].B3[7].k - |vpiModule: - \_module: work@small_top.u1.B1[0].B2[2].B3[7]::M3 (work@small_top.u1.B1[0].B2[2].B3[7].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[0].B2[2].B3[7]::M3 (work@small_top.u1.B1[0].B2[2].B3[7].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[0].B2[2].B3[7]) |vpiName:N3 @@ -19838,8 +19838,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[0].B2[2].B3[8].k - |vpiModule: - \_module: work@small_top.u1.B1[0].B2[2].B3[8]::M3 (work@small_top.u1.B1[0].B2[2].B3[8].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[0].B2[2].B3[8]::M3 (work@small_top.u1.B1[0].B2[2].B3[8].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[0].B2[2].B3[8]) |vpiName:N3 @@ -19866,8 +19866,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[0].B2[2].B3[9].k - |vpiModule: - \_module: work@small_top.u1.B1[0].B2[2].B3[9]::M3 (work@small_top.u1.B1[0].B2[2].B3[9].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[0].B2[2].B3[9]::M3 (work@small_top.u1.B1[0].B2[2].B3[9].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[0].B2[2].B3[9]) |vpiName:N3 @@ -19894,8 +19894,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:j |vpiFullName:work@small_top.u1.B1[0].B2[3].j - |vpiModule: - \_module: work@small_top.u1.B1[0].B2[3]::M2 (work@small_top.u1.B1[0].B2[3].N2), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:26:1, endln:26:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[0].B2[3]::M2 (work@small_top.u1.B1[0].B2[3].N2), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:26:1, endln:26:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[0].B2[3]) |vpiName:N2 @@ -19922,8 +19922,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[0].B2[3].B3[0].k - |vpiModule: - \_module: work@small_top.u1.B1[0].B2[3].B3[0]::M3 (work@small_top.u1.B1[0].B2[3].B3[0].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[0].B2[3].B3[0]::M3 (work@small_top.u1.B1[0].B2[3].B3[0].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[0].B2[3].B3[0]) |vpiName:N3 @@ -19950,8 +19950,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[0].B2[3].B3[1].k - |vpiModule: - \_module: work@small_top.u1.B1[0].B2[3].B3[1]::M3 (work@small_top.u1.B1[0].B2[3].B3[1].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[0].B2[3].B3[1]::M3 (work@small_top.u1.B1[0].B2[3].B3[1].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[0].B2[3].B3[1]) |vpiName:N3 @@ -19978,8 +19978,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[0].B2[3].B3[2].k - |vpiModule: - \_module: work@small_top.u1.B1[0].B2[3].B3[2]::M3 (work@small_top.u1.B1[0].B2[3].B3[2].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[0].B2[3].B3[2]::M3 (work@small_top.u1.B1[0].B2[3].B3[2].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[0].B2[3].B3[2]) |vpiName:N3 @@ -20006,8 +20006,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[0].B2[3].B3[3].k - |vpiModule: - \_module: work@small_top.u1.B1[0].B2[3].B3[3]::M3 (work@small_top.u1.B1[0].B2[3].B3[3].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[0].B2[3].B3[3]::M3 (work@small_top.u1.B1[0].B2[3].B3[3].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[0].B2[3].B3[3]) |vpiName:N3 @@ -20034,8 +20034,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[0].B2[3].B3[4].k - |vpiModule: - \_module: work@small_top.u1.B1[0].B2[3].B3[4]::M3 (work@small_top.u1.B1[0].B2[3].B3[4].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[0].B2[3].B3[4]::M3 (work@small_top.u1.B1[0].B2[3].B3[4].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[0].B2[3].B3[4]) |vpiName:N3 @@ -20062,8 +20062,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[0].B2[3].B3[5].k - |vpiModule: - \_module: work@small_top.u1.B1[0].B2[3].B3[5]::M3 (work@small_top.u1.B1[0].B2[3].B3[5].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[0].B2[3].B3[5]::M3 (work@small_top.u1.B1[0].B2[3].B3[5].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[0].B2[3].B3[5]) |vpiName:N3 @@ -20090,8 +20090,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[0].B2[3].B3[6].k - |vpiModule: - \_module: work@small_top.u1.B1[0].B2[3].B3[6]::M3 (work@small_top.u1.B1[0].B2[3].B3[6].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[0].B2[3].B3[6]::M3 (work@small_top.u1.B1[0].B2[3].B3[6].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[0].B2[3].B3[6]) |vpiName:N3 @@ -20118,8 +20118,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[0].B2[3].B3[7].k - |vpiModule: - \_module: work@small_top.u1.B1[0].B2[3].B3[7]::M3 (work@small_top.u1.B1[0].B2[3].B3[7].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[0].B2[3].B3[7]::M3 (work@small_top.u1.B1[0].B2[3].B3[7].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[0].B2[3].B3[7]) |vpiName:N3 @@ -20146,8 +20146,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[0].B2[3].B3[8].k - |vpiModule: - \_module: work@small_top.u1.B1[0].B2[3].B3[8]::M3 (work@small_top.u1.B1[0].B2[3].B3[8].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[0].B2[3].B3[8]::M3 (work@small_top.u1.B1[0].B2[3].B3[8].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[0].B2[3].B3[8]) |vpiName:N3 @@ -20174,8 +20174,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[0].B2[3].B3[9].k - |vpiModule: - \_module: work@small_top.u1.B1[0].B2[3].B3[9]::M3 (work@small_top.u1.B1[0].B2[3].B3[9].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[0].B2[3].B3[9]::M3 (work@small_top.u1.B1[0].B2[3].B3[9].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[0].B2[3].B3[9]) |vpiName:N3 @@ -20202,8 +20202,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:j |vpiFullName:work@small_top.u1.B1[0].B2[4].j - |vpiModule: - \_module: work@small_top.u1.B1[0].B2[4]::M2 (work@small_top.u1.B1[0].B2[4].N2), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:26:1, endln:26:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[0].B2[4]::M2 (work@small_top.u1.B1[0].B2[4].N2), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:26:1, endln:26:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[0].B2[4]) |vpiName:N2 @@ -20230,8 +20230,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[0].B2[4].B3[0].k - |vpiModule: - \_module: work@small_top.u1.B1[0].B2[4].B3[0]::M3 (work@small_top.u1.B1[0].B2[4].B3[0].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[0].B2[4].B3[0]::M3 (work@small_top.u1.B1[0].B2[4].B3[0].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[0].B2[4].B3[0]) |vpiName:N3 @@ -20258,8 +20258,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[0].B2[4].B3[1].k - |vpiModule: - \_module: work@small_top.u1.B1[0].B2[4].B3[1]::M3 (work@small_top.u1.B1[0].B2[4].B3[1].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[0].B2[4].B3[1]::M3 (work@small_top.u1.B1[0].B2[4].B3[1].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[0].B2[4].B3[1]) |vpiName:N3 @@ -20286,8 +20286,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[0].B2[4].B3[2].k - |vpiModule: - \_module: work@small_top.u1.B1[0].B2[4].B3[2]::M3 (work@small_top.u1.B1[0].B2[4].B3[2].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[0].B2[4].B3[2]::M3 (work@small_top.u1.B1[0].B2[4].B3[2].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[0].B2[4].B3[2]) |vpiName:N3 @@ -20314,8 +20314,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[0].B2[4].B3[3].k - |vpiModule: - \_module: work@small_top.u1.B1[0].B2[4].B3[3]::M3 (work@small_top.u1.B1[0].B2[4].B3[3].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[0].B2[4].B3[3]::M3 (work@small_top.u1.B1[0].B2[4].B3[3].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[0].B2[4].B3[3]) |vpiName:N3 @@ -20342,8 +20342,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[0].B2[4].B3[4].k - |vpiModule: - \_module: work@small_top.u1.B1[0].B2[4].B3[4]::M3 (work@small_top.u1.B1[0].B2[4].B3[4].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[0].B2[4].B3[4]::M3 (work@small_top.u1.B1[0].B2[4].B3[4].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[0].B2[4].B3[4]) |vpiName:N3 @@ -20370,8 +20370,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[0].B2[4].B3[5].k - |vpiModule: - \_module: work@small_top.u1.B1[0].B2[4].B3[5]::M3 (work@small_top.u1.B1[0].B2[4].B3[5].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[0].B2[4].B3[5]::M3 (work@small_top.u1.B1[0].B2[4].B3[5].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[0].B2[4].B3[5]) |vpiName:N3 @@ -20398,8 +20398,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[0].B2[4].B3[6].k - |vpiModule: - \_module: work@small_top.u1.B1[0].B2[4].B3[6]::M3 (work@small_top.u1.B1[0].B2[4].B3[6].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[0].B2[4].B3[6]::M3 (work@small_top.u1.B1[0].B2[4].B3[6].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[0].B2[4].B3[6]) |vpiName:N3 @@ -20426,8 +20426,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[0].B2[4].B3[7].k - |vpiModule: - \_module: work@small_top.u1.B1[0].B2[4].B3[7]::M3 (work@small_top.u1.B1[0].B2[4].B3[7].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[0].B2[4].B3[7]::M3 (work@small_top.u1.B1[0].B2[4].B3[7].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[0].B2[4].B3[7]) |vpiName:N3 @@ -20454,8 +20454,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[0].B2[4].B3[8].k - |vpiModule: - \_module: work@small_top.u1.B1[0].B2[4].B3[8]::M3 (work@small_top.u1.B1[0].B2[4].B3[8].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[0].B2[4].B3[8]::M3 (work@small_top.u1.B1[0].B2[4].B3[8].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[0].B2[4].B3[8]) |vpiName:N3 @@ -20482,8 +20482,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[0].B2[4].B3[9].k - |vpiModule: - \_module: work@small_top.u1.B1[0].B2[4].B3[9]::M3 (work@small_top.u1.B1[0].B2[4].B3[9].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[0].B2[4].B3[9]::M3 (work@small_top.u1.B1[0].B2[4].B3[9].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[0].B2[4].B3[9]) |vpiName:N3 @@ -20510,8 +20510,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:j |vpiFullName:work@small_top.u1.B1[0].B2[5].j - |vpiModule: - \_module: work@small_top.u1.B1[0].B2[5]::M2 (work@small_top.u1.B1[0].B2[5].N2), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:26:1, endln:26:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[0].B2[5]::M2 (work@small_top.u1.B1[0].B2[5].N2), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:26:1, endln:26:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[0].B2[5]) |vpiName:N2 @@ -20538,8 +20538,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[0].B2[5].B3[0].k - |vpiModule: - \_module: work@small_top.u1.B1[0].B2[5].B3[0]::M3 (work@small_top.u1.B1[0].B2[5].B3[0].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[0].B2[5].B3[0]::M3 (work@small_top.u1.B1[0].B2[5].B3[0].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[0].B2[5].B3[0]) |vpiName:N3 @@ -20566,8 +20566,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[0].B2[5].B3[1].k - |vpiModule: - \_module: work@small_top.u1.B1[0].B2[5].B3[1]::M3 (work@small_top.u1.B1[0].B2[5].B3[1].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[0].B2[5].B3[1]::M3 (work@small_top.u1.B1[0].B2[5].B3[1].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[0].B2[5].B3[1]) |vpiName:N3 @@ -20594,8 +20594,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[0].B2[5].B3[2].k - |vpiModule: - \_module: work@small_top.u1.B1[0].B2[5].B3[2]::M3 (work@small_top.u1.B1[0].B2[5].B3[2].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[0].B2[5].B3[2]::M3 (work@small_top.u1.B1[0].B2[5].B3[2].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[0].B2[5].B3[2]) |vpiName:N3 @@ -20622,8 +20622,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[0].B2[5].B3[3].k - |vpiModule: - \_module: work@small_top.u1.B1[0].B2[5].B3[3]::M3 (work@small_top.u1.B1[0].B2[5].B3[3].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[0].B2[5].B3[3]::M3 (work@small_top.u1.B1[0].B2[5].B3[3].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[0].B2[5].B3[3]) |vpiName:N3 @@ -20650,8 +20650,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[0].B2[5].B3[4].k - |vpiModule: - \_module: work@small_top.u1.B1[0].B2[5].B3[4]::M3 (work@small_top.u1.B1[0].B2[5].B3[4].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[0].B2[5].B3[4]::M3 (work@small_top.u1.B1[0].B2[5].B3[4].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[0].B2[5].B3[4]) |vpiName:N3 @@ -20678,8 +20678,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[0].B2[5].B3[5].k - |vpiModule: - \_module: work@small_top.u1.B1[0].B2[5].B3[5]::M3 (work@small_top.u1.B1[0].B2[5].B3[5].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[0].B2[5].B3[5]::M3 (work@small_top.u1.B1[0].B2[5].B3[5].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[0].B2[5].B3[5]) |vpiName:N3 @@ -20706,8 +20706,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[0].B2[5].B3[6].k - |vpiModule: - \_module: work@small_top.u1.B1[0].B2[5].B3[6]::M3 (work@small_top.u1.B1[0].B2[5].B3[6].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[0].B2[5].B3[6]::M3 (work@small_top.u1.B1[0].B2[5].B3[6].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[0].B2[5].B3[6]) |vpiName:N3 @@ -20734,8 +20734,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[0].B2[5].B3[7].k - |vpiModule: - \_module: work@small_top.u1.B1[0].B2[5].B3[7]::M3 (work@small_top.u1.B1[0].B2[5].B3[7].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[0].B2[5].B3[7]::M3 (work@small_top.u1.B1[0].B2[5].B3[7].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[0].B2[5].B3[7]) |vpiName:N3 @@ -20762,8 +20762,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[0].B2[5].B3[8].k - |vpiModule: - \_module: work@small_top.u1.B1[0].B2[5].B3[8]::M3 (work@small_top.u1.B1[0].B2[5].B3[8].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[0].B2[5].B3[8]::M3 (work@small_top.u1.B1[0].B2[5].B3[8].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[0].B2[5].B3[8]) |vpiName:N3 @@ -20790,8 +20790,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[0].B2[5].B3[9].k - |vpiModule: - \_module: work@small_top.u1.B1[0].B2[5].B3[9]::M3 (work@small_top.u1.B1[0].B2[5].B3[9].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[0].B2[5].B3[9]::M3 (work@small_top.u1.B1[0].B2[5].B3[9].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[0].B2[5].B3[9]) |vpiName:N3 @@ -20818,8 +20818,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:j |vpiFullName:work@small_top.u1.B1[0].B2[6].j - |vpiModule: - \_module: work@small_top.u1.B1[0].B2[6]::M2 (work@small_top.u1.B1[0].B2[6].N2), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:26:1, endln:26:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[0].B2[6]::M2 (work@small_top.u1.B1[0].B2[6].N2), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:26:1, endln:26:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[0].B2[6]) |vpiName:N2 @@ -20846,8 +20846,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[0].B2[6].B3[0].k - |vpiModule: - \_module: work@small_top.u1.B1[0].B2[6].B3[0]::M3 (work@small_top.u1.B1[0].B2[6].B3[0].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[0].B2[6].B3[0]::M3 (work@small_top.u1.B1[0].B2[6].B3[0].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[0].B2[6].B3[0]) |vpiName:N3 @@ -20874,8 +20874,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[0].B2[6].B3[1].k - |vpiModule: - \_module: work@small_top.u1.B1[0].B2[6].B3[1]::M3 (work@small_top.u1.B1[0].B2[6].B3[1].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[0].B2[6].B3[1]::M3 (work@small_top.u1.B1[0].B2[6].B3[1].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[0].B2[6].B3[1]) |vpiName:N3 @@ -20902,8 +20902,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[0].B2[6].B3[2].k - |vpiModule: - \_module: work@small_top.u1.B1[0].B2[6].B3[2]::M3 (work@small_top.u1.B1[0].B2[6].B3[2].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[0].B2[6].B3[2]::M3 (work@small_top.u1.B1[0].B2[6].B3[2].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[0].B2[6].B3[2]) |vpiName:N3 @@ -20930,8 +20930,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[0].B2[6].B3[3].k - |vpiModule: - \_module: work@small_top.u1.B1[0].B2[6].B3[3]::M3 (work@small_top.u1.B1[0].B2[6].B3[3].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[0].B2[6].B3[3]::M3 (work@small_top.u1.B1[0].B2[6].B3[3].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[0].B2[6].B3[3]) |vpiName:N3 @@ -20958,8 +20958,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[0].B2[6].B3[4].k - |vpiModule: - \_module: work@small_top.u1.B1[0].B2[6].B3[4]::M3 (work@small_top.u1.B1[0].B2[6].B3[4].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[0].B2[6].B3[4]::M3 (work@small_top.u1.B1[0].B2[6].B3[4].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[0].B2[6].B3[4]) |vpiName:N3 @@ -20986,8 +20986,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[0].B2[6].B3[5].k - |vpiModule: - \_module: work@small_top.u1.B1[0].B2[6].B3[5]::M3 (work@small_top.u1.B1[0].B2[6].B3[5].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[0].B2[6].B3[5]::M3 (work@small_top.u1.B1[0].B2[6].B3[5].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[0].B2[6].B3[5]) |vpiName:N3 @@ -21014,8 +21014,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[0].B2[6].B3[6].k - |vpiModule: - \_module: work@small_top.u1.B1[0].B2[6].B3[6]::M3 (work@small_top.u1.B1[0].B2[6].B3[6].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[0].B2[6].B3[6]::M3 (work@small_top.u1.B1[0].B2[6].B3[6].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[0].B2[6].B3[6]) |vpiName:N3 @@ -21042,8 +21042,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[0].B2[6].B3[7].k - |vpiModule: - \_module: work@small_top.u1.B1[0].B2[6].B3[7]::M3 (work@small_top.u1.B1[0].B2[6].B3[7].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[0].B2[6].B3[7]::M3 (work@small_top.u1.B1[0].B2[6].B3[7].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[0].B2[6].B3[7]) |vpiName:N3 @@ -21070,8 +21070,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[0].B2[6].B3[8].k - |vpiModule: - \_module: work@small_top.u1.B1[0].B2[6].B3[8]::M3 (work@small_top.u1.B1[0].B2[6].B3[8].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[0].B2[6].B3[8]::M3 (work@small_top.u1.B1[0].B2[6].B3[8].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[0].B2[6].B3[8]) |vpiName:N3 @@ -21098,8 +21098,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[0].B2[6].B3[9].k - |vpiModule: - \_module: work@small_top.u1.B1[0].B2[6].B3[9]::M3 (work@small_top.u1.B1[0].B2[6].B3[9].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[0].B2[6].B3[9]::M3 (work@small_top.u1.B1[0].B2[6].B3[9].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[0].B2[6].B3[9]) |vpiName:N3 @@ -21126,8 +21126,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:j |vpiFullName:work@small_top.u1.B1[0].B2[7].j - |vpiModule: - \_module: work@small_top.u1.B1[0].B2[7]::M2 (work@small_top.u1.B1[0].B2[7].N2), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:26:1, endln:26:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[0].B2[7]::M2 (work@small_top.u1.B1[0].B2[7].N2), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:26:1, endln:26:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[0].B2[7]) |vpiName:N2 @@ -21154,8 +21154,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[0].B2[7].B3[0].k - |vpiModule: - \_module: work@small_top.u1.B1[0].B2[7].B3[0]::M3 (work@small_top.u1.B1[0].B2[7].B3[0].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[0].B2[7].B3[0]::M3 (work@small_top.u1.B1[0].B2[7].B3[0].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[0].B2[7].B3[0]) |vpiName:N3 @@ -21182,8 +21182,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[0].B2[7].B3[1].k - |vpiModule: - \_module: work@small_top.u1.B1[0].B2[7].B3[1]::M3 (work@small_top.u1.B1[0].B2[7].B3[1].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[0].B2[7].B3[1]::M3 (work@small_top.u1.B1[0].B2[7].B3[1].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[0].B2[7].B3[1]) |vpiName:N3 @@ -21210,8 +21210,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[0].B2[7].B3[2].k - |vpiModule: - \_module: work@small_top.u1.B1[0].B2[7].B3[2]::M3 (work@small_top.u1.B1[0].B2[7].B3[2].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[0].B2[7].B3[2]::M3 (work@small_top.u1.B1[0].B2[7].B3[2].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[0].B2[7].B3[2]) |vpiName:N3 @@ -21238,8 +21238,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[0].B2[7].B3[3].k - |vpiModule: - \_module: work@small_top.u1.B1[0].B2[7].B3[3]::M3 (work@small_top.u1.B1[0].B2[7].B3[3].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[0].B2[7].B3[3]::M3 (work@small_top.u1.B1[0].B2[7].B3[3].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[0].B2[7].B3[3]) |vpiName:N3 @@ -21266,8 +21266,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[0].B2[7].B3[4].k - |vpiModule: - \_module: work@small_top.u1.B1[0].B2[7].B3[4]::M3 (work@small_top.u1.B1[0].B2[7].B3[4].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[0].B2[7].B3[4]::M3 (work@small_top.u1.B1[0].B2[7].B3[4].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[0].B2[7].B3[4]) |vpiName:N3 @@ -21294,8 +21294,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[0].B2[7].B3[5].k - |vpiModule: - \_module: work@small_top.u1.B1[0].B2[7].B3[5]::M3 (work@small_top.u1.B1[0].B2[7].B3[5].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[0].B2[7].B3[5]::M3 (work@small_top.u1.B1[0].B2[7].B3[5].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[0].B2[7].B3[5]) |vpiName:N3 @@ -21322,8 +21322,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[0].B2[7].B3[6].k - |vpiModule: - \_module: work@small_top.u1.B1[0].B2[7].B3[6]::M3 (work@small_top.u1.B1[0].B2[7].B3[6].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[0].B2[7].B3[6]::M3 (work@small_top.u1.B1[0].B2[7].B3[6].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[0].B2[7].B3[6]) |vpiName:N3 @@ -21350,8 +21350,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[0].B2[7].B3[7].k - |vpiModule: - \_module: work@small_top.u1.B1[0].B2[7].B3[7]::M3 (work@small_top.u1.B1[0].B2[7].B3[7].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[0].B2[7].B3[7]::M3 (work@small_top.u1.B1[0].B2[7].B3[7].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[0].B2[7].B3[7]) |vpiName:N3 @@ -21378,8 +21378,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[0].B2[7].B3[8].k - |vpiModule: - \_module: work@small_top.u1.B1[0].B2[7].B3[8]::M3 (work@small_top.u1.B1[0].B2[7].B3[8].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[0].B2[7].B3[8]::M3 (work@small_top.u1.B1[0].B2[7].B3[8].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[0].B2[7].B3[8]) |vpiName:N3 @@ -21406,8 +21406,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[0].B2[7].B3[9].k - |vpiModule: - \_module: work@small_top.u1.B1[0].B2[7].B3[9]::M3 (work@small_top.u1.B1[0].B2[7].B3[9].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[0].B2[7].B3[9]::M3 (work@small_top.u1.B1[0].B2[7].B3[9].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[0].B2[7].B3[9]) |vpiName:N3 @@ -21434,8 +21434,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:j |vpiFullName:work@small_top.u1.B1[0].B2[8].j - |vpiModule: - \_module: work@small_top.u1.B1[0].B2[8]::M2 (work@small_top.u1.B1[0].B2[8].N2), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:26:1, endln:26:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[0].B2[8]::M2 (work@small_top.u1.B1[0].B2[8].N2), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:26:1, endln:26:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[0].B2[8]) |vpiName:N2 @@ -21462,8 +21462,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[0].B2[8].B3[0].k - |vpiModule: - \_module: work@small_top.u1.B1[0].B2[8].B3[0]::M3 (work@small_top.u1.B1[0].B2[8].B3[0].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[0].B2[8].B3[0]::M3 (work@small_top.u1.B1[0].B2[8].B3[0].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[0].B2[8].B3[0]) |vpiName:N3 @@ -21490,8 +21490,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[0].B2[8].B3[1].k - |vpiModule: - \_module: work@small_top.u1.B1[0].B2[8].B3[1]::M3 (work@small_top.u1.B1[0].B2[8].B3[1].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[0].B2[8].B3[1]::M3 (work@small_top.u1.B1[0].B2[8].B3[1].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[0].B2[8].B3[1]) |vpiName:N3 @@ -21518,8 +21518,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[0].B2[8].B3[2].k - |vpiModule: - \_module: work@small_top.u1.B1[0].B2[8].B3[2]::M3 (work@small_top.u1.B1[0].B2[8].B3[2].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[0].B2[8].B3[2]::M3 (work@small_top.u1.B1[0].B2[8].B3[2].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[0].B2[8].B3[2]) |vpiName:N3 @@ -21546,8 +21546,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[0].B2[8].B3[3].k - |vpiModule: - \_module: work@small_top.u1.B1[0].B2[8].B3[3]::M3 (work@small_top.u1.B1[0].B2[8].B3[3].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[0].B2[8].B3[3]::M3 (work@small_top.u1.B1[0].B2[8].B3[3].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[0].B2[8].B3[3]) |vpiName:N3 @@ -21574,8 +21574,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[0].B2[8].B3[4].k - |vpiModule: - \_module: work@small_top.u1.B1[0].B2[8].B3[4]::M3 (work@small_top.u1.B1[0].B2[8].B3[4].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[0].B2[8].B3[4]::M3 (work@small_top.u1.B1[0].B2[8].B3[4].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[0].B2[8].B3[4]) |vpiName:N3 @@ -21602,8 +21602,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[0].B2[8].B3[5].k - |vpiModule: - \_module: work@small_top.u1.B1[0].B2[8].B3[5]::M3 (work@small_top.u1.B1[0].B2[8].B3[5].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[0].B2[8].B3[5]::M3 (work@small_top.u1.B1[0].B2[8].B3[5].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[0].B2[8].B3[5]) |vpiName:N3 @@ -21630,8 +21630,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[0].B2[8].B3[6].k - |vpiModule: - \_module: work@small_top.u1.B1[0].B2[8].B3[6]::M3 (work@small_top.u1.B1[0].B2[8].B3[6].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[0].B2[8].B3[6]::M3 (work@small_top.u1.B1[0].B2[8].B3[6].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[0].B2[8].B3[6]) |vpiName:N3 @@ -21658,8 +21658,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[0].B2[8].B3[7].k - |vpiModule: - \_module: work@small_top.u1.B1[0].B2[8].B3[7]::M3 (work@small_top.u1.B1[0].B2[8].B3[7].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[0].B2[8].B3[7]::M3 (work@small_top.u1.B1[0].B2[8].B3[7].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[0].B2[8].B3[7]) |vpiName:N3 @@ -21686,8 +21686,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[0].B2[8].B3[8].k - |vpiModule: - \_module: work@small_top.u1.B1[0].B2[8].B3[8]::M3 (work@small_top.u1.B1[0].B2[8].B3[8].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[0].B2[8].B3[8]::M3 (work@small_top.u1.B1[0].B2[8].B3[8].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[0].B2[8].B3[8]) |vpiName:N3 @@ -21714,8 +21714,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[0].B2[8].B3[9].k - |vpiModule: - \_module: work@small_top.u1.B1[0].B2[8].B3[9]::M3 (work@small_top.u1.B1[0].B2[8].B3[9].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[0].B2[8].B3[9]::M3 (work@small_top.u1.B1[0].B2[8].B3[9].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[0].B2[8].B3[9]) |vpiName:N3 @@ -21742,8 +21742,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:j |vpiFullName:work@small_top.u1.B1[0].B2[9].j - |vpiModule: - \_module: work@small_top.u1.B1[0].B2[9]::M2 (work@small_top.u1.B1[0].B2[9].N2), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:26:1, endln:26:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[0].B2[9]::M2 (work@small_top.u1.B1[0].B2[9].N2), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:26:1, endln:26:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[0].B2[9]) |vpiName:N2 @@ -21770,8 +21770,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[0].B2[9].B3[0].k - |vpiModule: - \_module: work@small_top.u1.B1[0].B2[9].B3[0]::M3 (work@small_top.u1.B1[0].B2[9].B3[0].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[0].B2[9].B3[0]::M3 (work@small_top.u1.B1[0].B2[9].B3[0].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[0].B2[9].B3[0]) |vpiName:N3 @@ -21798,8 +21798,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[0].B2[9].B3[1].k - |vpiModule: - \_module: work@small_top.u1.B1[0].B2[9].B3[1]::M3 (work@small_top.u1.B1[0].B2[9].B3[1].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[0].B2[9].B3[1]::M3 (work@small_top.u1.B1[0].B2[9].B3[1].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[0].B2[9].B3[1]) |vpiName:N3 @@ -21826,8 +21826,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[0].B2[9].B3[2].k - |vpiModule: - \_module: work@small_top.u1.B1[0].B2[9].B3[2]::M3 (work@small_top.u1.B1[0].B2[9].B3[2].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[0].B2[9].B3[2]::M3 (work@small_top.u1.B1[0].B2[9].B3[2].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[0].B2[9].B3[2]) |vpiName:N3 @@ -21854,8 +21854,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[0].B2[9].B3[3].k - |vpiModule: - \_module: work@small_top.u1.B1[0].B2[9].B3[3]::M3 (work@small_top.u1.B1[0].B2[9].B3[3].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[0].B2[9].B3[3]::M3 (work@small_top.u1.B1[0].B2[9].B3[3].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[0].B2[9].B3[3]) |vpiName:N3 @@ -21882,8 +21882,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[0].B2[9].B3[4].k - |vpiModule: - \_module: work@small_top.u1.B1[0].B2[9].B3[4]::M3 (work@small_top.u1.B1[0].B2[9].B3[4].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[0].B2[9].B3[4]::M3 (work@small_top.u1.B1[0].B2[9].B3[4].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[0].B2[9].B3[4]) |vpiName:N3 @@ -21910,8 +21910,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[0].B2[9].B3[5].k - |vpiModule: - \_module: work@small_top.u1.B1[0].B2[9].B3[5]::M3 (work@small_top.u1.B1[0].B2[9].B3[5].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[0].B2[9].B3[5]::M3 (work@small_top.u1.B1[0].B2[9].B3[5].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[0].B2[9].B3[5]) |vpiName:N3 @@ -21938,8 +21938,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[0].B2[9].B3[6].k - |vpiModule: - \_module: work@small_top.u1.B1[0].B2[9].B3[6]::M3 (work@small_top.u1.B1[0].B2[9].B3[6].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[0].B2[9].B3[6]::M3 (work@small_top.u1.B1[0].B2[9].B3[6].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[0].B2[9].B3[6]) |vpiName:N3 @@ -21966,8 +21966,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[0].B2[9].B3[7].k - |vpiModule: - \_module: work@small_top.u1.B1[0].B2[9].B3[7]::M3 (work@small_top.u1.B1[0].B2[9].B3[7].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[0].B2[9].B3[7]::M3 (work@small_top.u1.B1[0].B2[9].B3[7].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[0].B2[9].B3[7]) |vpiName:N3 @@ -21994,8 +21994,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[0].B2[9].B3[8].k - |vpiModule: - \_module: work@small_top.u1.B1[0].B2[9].B3[8]::M3 (work@small_top.u1.B1[0].B2[9].B3[8].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[0].B2[9].B3[8]::M3 (work@small_top.u1.B1[0].B2[9].B3[8].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[0].B2[9].B3[8]) |vpiName:N3 @@ -22022,8 +22022,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[0].B2[9].B3[9].k - |vpiModule: - \_module: work@small_top.u1.B1[0].B2[9].B3[9]::M3 (work@small_top.u1.B1[0].B2[9].B3[9].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[0].B2[9].B3[9]::M3 (work@small_top.u1.B1[0].B2[9].B3[9].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[0].B2[9].B3[9]) |vpiName:N3 @@ -22032,7 +22032,7 @@ design: (work@bottom1) |vpiGenScopeArray: \_gen_scope_array: (work@small_top.u1.B1[1]), line:17:1, endln:51:4 |vpiParent: - \_module: work@small_test (work@small_top.u1), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:2:4, endln:2:29 + \_module_inst: work@small_test (work@small_top.u1), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:2:4, endln:2:29 |vpiName:B1[1] |vpiFullName:work@small_top.u1.B1[1] |vpiGenScope: @@ -22050,8 +22050,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:i |vpiFullName:work@small_top.u1.B1[1].i - |vpiModule: - \_module: work@small_top.u1.B1[1]::M1 (work@small_top.u1.B1[1].N1), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:20:1, endln:20:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[1]::M1 (work@small_top.u1.B1[1].N1), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:20:1, endln:20:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[1]) |vpiName:N1 @@ -22078,8 +22078,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:j |vpiFullName:work@small_top.u1.B1[1].B2[0].j - |vpiModule: - \_module: work@small_top.u1.B1[1].B2[0]::M2 (work@small_top.u1.B1[1].B2[0].N2), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:26:1, endln:26:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[1].B2[0]::M2 (work@small_top.u1.B1[1].B2[0].N2), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:26:1, endln:26:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[1].B2[0]) |vpiName:N2 @@ -22106,8 +22106,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[1].B2[0].B3[0].k - |vpiModule: - \_module: work@small_top.u1.B1[1].B2[0].B3[0]::M3 (work@small_top.u1.B1[1].B2[0].B3[0].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[1].B2[0].B3[0]::M3 (work@small_top.u1.B1[1].B2[0].B3[0].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[1].B2[0].B3[0]) |vpiName:N3 @@ -22134,8 +22134,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[1].B2[0].B3[1].k - |vpiModule: - \_module: work@small_top.u1.B1[1].B2[0].B3[1]::M3 (work@small_top.u1.B1[1].B2[0].B3[1].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[1].B2[0].B3[1]::M3 (work@small_top.u1.B1[1].B2[0].B3[1].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[1].B2[0].B3[1]) |vpiName:N3 @@ -22162,8 +22162,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[1].B2[0].B3[2].k - |vpiModule: - \_module: work@small_top.u1.B1[1].B2[0].B3[2]::M3 (work@small_top.u1.B1[1].B2[0].B3[2].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[1].B2[0].B3[2]::M3 (work@small_top.u1.B1[1].B2[0].B3[2].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[1].B2[0].B3[2]) |vpiName:N3 @@ -22190,8 +22190,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[1].B2[0].B3[3].k - |vpiModule: - \_module: work@small_top.u1.B1[1].B2[0].B3[3]::M3 (work@small_top.u1.B1[1].B2[0].B3[3].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[1].B2[0].B3[3]::M3 (work@small_top.u1.B1[1].B2[0].B3[3].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[1].B2[0].B3[3]) |vpiName:N3 @@ -22218,8 +22218,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[1].B2[0].B3[4].k - |vpiModule: - \_module: work@small_top.u1.B1[1].B2[0].B3[4]::M3 (work@small_top.u1.B1[1].B2[0].B3[4].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[1].B2[0].B3[4]::M3 (work@small_top.u1.B1[1].B2[0].B3[4].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[1].B2[0].B3[4]) |vpiName:N3 @@ -22246,8 +22246,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[1].B2[0].B3[5].k - |vpiModule: - \_module: work@small_top.u1.B1[1].B2[0].B3[5]::M3 (work@small_top.u1.B1[1].B2[0].B3[5].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[1].B2[0].B3[5]::M3 (work@small_top.u1.B1[1].B2[0].B3[5].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[1].B2[0].B3[5]) |vpiName:N3 @@ -22274,8 +22274,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[1].B2[0].B3[6].k - |vpiModule: - \_module: work@small_top.u1.B1[1].B2[0].B3[6]::M3 (work@small_top.u1.B1[1].B2[0].B3[6].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[1].B2[0].B3[6]::M3 (work@small_top.u1.B1[1].B2[0].B3[6].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[1].B2[0].B3[6]) |vpiName:N3 @@ -22302,8 +22302,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[1].B2[0].B3[7].k - |vpiModule: - \_module: work@small_top.u1.B1[1].B2[0].B3[7]::M3 (work@small_top.u1.B1[1].B2[0].B3[7].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[1].B2[0].B3[7]::M3 (work@small_top.u1.B1[1].B2[0].B3[7].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[1].B2[0].B3[7]) |vpiName:N3 @@ -22330,8 +22330,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[1].B2[0].B3[8].k - |vpiModule: - \_module: work@small_top.u1.B1[1].B2[0].B3[8]::M3 (work@small_top.u1.B1[1].B2[0].B3[8].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[1].B2[0].B3[8]::M3 (work@small_top.u1.B1[1].B2[0].B3[8].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[1].B2[0].B3[8]) |vpiName:N3 @@ -22358,8 +22358,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[1].B2[0].B3[9].k - |vpiModule: - \_module: work@small_top.u1.B1[1].B2[0].B3[9]::M3 (work@small_top.u1.B1[1].B2[0].B3[9].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[1].B2[0].B3[9]::M3 (work@small_top.u1.B1[1].B2[0].B3[9].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[1].B2[0].B3[9]) |vpiName:N3 @@ -22386,8 +22386,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:j |vpiFullName:work@small_top.u1.B1[1].B2[1].j - |vpiModule: - \_module: work@small_top.u1.B1[1].B2[1]::M2 (work@small_top.u1.B1[1].B2[1].N2), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:26:1, endln:26:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[1].B2[1]::M2 (work@small_top.u1.B1[1].B2[1].N2), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:26:1, endln:26:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[1].B2[1]) |vpiName:N2 @@ -22414,8 +22414,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[1].B2[1].B3[0].k - |vpiModule: - \_module: work@small_top.u1.B1[1].B2[1].B3[0]::M3 (work@small_top.u1.B1[1].B2[1].B3[0].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[1].B2[1].B3[0]::M3 (work@small_top.u1.B1[1].B2[1].B3[0].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[1].B2[1].B3[0]) |vpiName:N3 @@ -22442,8 +22442,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[1].B2[1].B3[1].k - |vpiModule: - \_module: work@small_top.u1.B1[1].B2[1].B3[1]::M3 (work@small_top.u1.B1[1].B2[1].B3[1].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[1].B2[1].B3[1]::M3 (work@small_top.u1.B1[1].B2[1].B3[1].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[1].B2[1].B3[1]) |vpiName:N3 @@ -22470,8 +22470,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[1].B2[1].B3[2].k - |vpiModule: - \_module: work@small_top.u1.B1[1].B2[1].B3[2]::M3 (work@small_top.u1.B1[1].B2[1].B3[2].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[1].B2[1].B3[2]::M3 (work@small_top.u1.B1[1].B2[1].B3[2].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[1].B2[1].B3[2]) |vpiName:N3 @@ -22498,8 +22498,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[1].B2[1].B3[3].k - |vpiModule: - \_module: work@small_top.u1.B1[1].B2[1].B3[3]::M3 (work@small_top.u1.B1[1].B2[1].B3[3].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[1].B2[1].B3[3]::M3 (work@small_top.u1.B1[1].B2[1].B3[3].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[1].B2[1].B3[3]) |vpiName:N3 @@ -22526,8 +22526,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[1].B2[1].B3[4].k - |vpiModule: - \_module: work@small_top.u1.B1[1].B2[1].B3[4]::M3 (work@small_top.u1.B1[1].B2[1].B3[4].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[1].B2[1].B3[4]::M3 (work@small_top.u1.B1[1].B2[1].B3[4].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[1].B2[1].B3[4]) |vpiName:N3 @@ -22554,8 +22554,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[1].B2[1].B3[5].k - |vpiModule: - \_module: work@small_top.u1.B1[1].B2[1].B3[5]::M3 (work@small_top.u1.B1[1].B2[1].B3[5].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[1].B2[1].B3[5]::M3 (work@small_top.u1.B1[1].B2[1].B3[5].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[1].B2[1].B3[5]) |vpiName:N3 @@ -22582,8 +22582,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[1].B2[1].B3[6].k - |vpiModule: - \_module: work@small_top.u1.B1[1].B2[1].B3[6]::M3 (work@small_top.u1.B1[1].B2[1].B3[6].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[1].B2[1].B3[6]::M3 (work@small_top.u1.B1[1].B2[1].B3[6].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[1].B2[1].B3[6]) |vpiName:N3 @@ -22610,8 +22610,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[1].B2[1].B3[7].k - |vpiModule: - \_module: work@small_top.u1.B1[1].B2[1].B3[7]::M3 (work@small_top.u1.B1[1].B2[1].B3[7].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[1].B2[1].B3[7]::M3 (work@small_top.u1.B1[1].B2[1].B3[7].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[1].B2[1].B3[7]) |vpiName:N3 @@ -22638,8 +22638,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[1].B2[1].B3[8].k - |vpiModule: - \_module: work@small_top.u1.B1[1].B2[1].B3[8]::M3 (work@small_top.u1.B1[1].B2[1].B3[8].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[1].B2[1].B3[8]::M3 (work@small_top.u1.B1[1].B2[1].B3[8].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[1].B2[1].B3[8]) |vpiName:N3 @@ -22666,8 +22666,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[1].B2[1].B3[9].k - |vpiModule: - \_module: work@small_top.u1.B1[1].B2[1].B3[9]::M3 (work@small_top.u1.B1[1].B2[1].B3[9].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[1].B2[1].B3[9]::M3 (work@small_top.u1.B1[1].B2[1].B3[9].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[1].B2[1].B3[9]) |vpiName:N3 @@ -22694,8 +22694,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:j |vpiFullName:work@small_top.u1.B1[1].B2[2].j - |vpiModule: - \_module: work@small_top.u1.B1[1].B2[2]::M2 (work@small_top.u1.B1[1].B2[2].N2), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:26:1, endln:26:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[1].B2[2]::M2 (work@small_top.u1.B1[1].B2[2].N2), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:26:1, endln:26:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[1].B2[2]) |vpiName:N2 @@ -22722,8 +22722,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[1].B2[2].B3[0].k - |vpiModule: - \_module: work@small_top.u1.B1[1].B2[2].B3[0]::M3 (work@small_top.u1.B1[1].B2[2].B3[0].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[1].B2[2].B3[0]::M3 (work@small_top.u1.B1[1].B2[2].B3[0].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[1].B2[2].B3[0]) |vpiName:N3 @@ -22750,8 +22750,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[1].B2[2].B3[1].k - |vpiModule: - \_module: work@small_top.u1.B1[1].B2[2].B3[1]::M3 (work@small_top.u1.B1[1].B2[2].B3[1].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[1].B2[2].B3[1]::M3 (work@small_top.u1.B1[1].B2[2].B3[1].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[1].B2[2].B3[1]) |vpiName:N3 @@ -22778,8 +22778,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[1].B2[2].B3[2].k - |vpiModule: - \_module: work@small_top.u1.B1[1].B2[2].B3[2]::M3 (work@small_top.u1.B1[1].B2[2].B3[2].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[1].B2[2].B3[2]::M3 (work@small_top.u1.B1[1].B2[2].B3[2].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[1].B2[2].B3[2]) |vpiName:N3 @@ -22806,8 +22806,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[1].B2[2].B3[3].k - |vpiModule: - \_module: work@small_top.u1.B1[1].B2[2].B3[3]::M3 (work@small_top.u1.B1[1].B2[2].B3[3].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[1].B2[2].B3[3]::M3 (work@small_top.u1.B1[1].B2[2].B3[3].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[1].B2[2].B3[3]) |vpiName:N3 @@ -22834,8 +22834,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[1].B2[2].B3[4].k - |vpiModule: - \_module: work@small_top.u1.B1[1].B2[2].B3[4]::M3 (work@small_top.u1.B1[1].B2[2].B3[4].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[1].B2[2].B3[4]::M3 (work@small_top.u1.B1[1].B2[2].B3[4].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[1].B2[2].B3[4]) |vpiName:N3 @@ -22862,8 +22862,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[1].B2[2].B3[5].k - |vpiModule: - \_module: work@small_top.u1.B1[1].B2[2].B3[5]::M3 (work@small_top.u1.B1[1].B2[2].B3[5].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[1].B2[2].B3[5]::M3 (work@small_top.u1.B1[1].B2[2].B3[5].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[1].B2[2].B3[5]) |vpiName:N3 @@ -22890,8 +22890,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[1].B2[2].B3[6].k - |vpiModule: - \_module: work@small_top.u1.B1[1].B2[2].B3[6]::M3 (work@small_top.u1.B1[1].B2[2].B3[6].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[1].B2[2].B3[6]::M3 (work@small_top.u1.B1[1].B2[2].B3[6].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[1].B2[2].B3[6]) |vpiName:N3 @@ -22918,8 +22918,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[1].B2[2].B3[7].k - |vpiModule: - \_module: work@small_top.u1.B1[1].B2[2].B3[7]::M3 (work@small_top.u1.B1[1].B2[2].B3[7].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[1].B2[2].B3[7]::M3 (work@small_top.u1.B1[1].B2[2].B3[7].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[1].B2[2].B3[7]) |vpiName:N3 @@ -22946,8 +22946,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[1].B2[2].B3[8].k - |vpiModule: - \_module: work@small_top.u1.B1[1].B2[2].B3[8]::M3 (work@small_top.u1.B1[1].B2[2].B3[8].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[1].B2[2].B3[8]::M3 (work@small_top.u1.B1[1].B2[2].B3[8].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[1].B2[2].B3[8]) |vpiName:N3 @@ -22974,8 +22974,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[1].B2[2].B3[9].k - |vpiModule: - \_module: work@small_top.u1.B1[1].B2[2].B3[9]::M3 (work@small_top.u1.B1[1].B2[2].B3[9].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[1].B2[2].B3[9]::M3 (work@small_top.u1.B1[1].B2[2].B3[9].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[1].B2[2].B3[9]) |vpiName:N3 @@ -23002,8 +23002,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:j |vpiFullName:work@small_top.u1.B1[1].B2[3].j - |vpiModule: - \_module: work@small_top.u1.B1[1].B2[3]::M2 (work@small_top.u1.B1[1].B2[3].N2), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:26:1, endln:26:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[1].B2[3]::M2 (work@small_top.u1.B1[1].B2[3].N2), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:26:1, endln:26:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[1].B2[3]) |vpiName:N2 @@ -23030,8 +23030,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[1].B2[3].B3[0].k - |vpiModule: - \_module: work@small_top.u1.B1[1].B2[3].B3[0]::M3 (work@small_top.u1.B1[1].B2[3].B3[0].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[1].B2[3].B3[0]::M3 (work@small_top.u1.B1[1].B2[3].B3[0].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[1].B2[3].B3[0]) |vpiName:N3 @@ -23058,8 +23058,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[1].B2[3].B3[1].k - |vpiModule: - \_module: work@small_top.u1.B1[1].B2[3].B3[1]::M3 (work@small_top.u1.B1[1].B2[3].B3[1].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[1].B2[3].B3[1]::M3 (work@small_top.u1.B1[1].B2[3].B3[1].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[1].B2[3].B3[1]) |vpiName:N3 @@ -23086,8 +23086,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[1].B2[3].B3[2].k - |vpiModule: - \_module: work@small_top.u1.B1[1].B2[3].B3[2]::M3 (work@small_top.u1.B1[1].B2[3].B3[2].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[1].B2[3].B3[2]::M3 (work@small_top.u1.B1[1].B2[3].B3[2].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[1].B2[3].B3[2]) |vpiName:N3 @@ -23114,8 +23114,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[1].B2[3].B3[3].k - |vpiModule: - \_module: work@small_top.u1.B1[1].B2[3].B3[3]::M3 (work@small_top.u1.B1[1].B2[3].B3[3].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[1].B2[3].B3[3]::M3 (work@small_top.u1.B1[1].B2[3].B3[3].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[1].B2[3].B3[3]) |vpiName:N3 @@ -23142,8 +23142,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[1].B2[3].B3[4].k - |vpiModule: - \_module: work@small_top.u1.B1[1].B2[3].B3[4]::M3 (work@small_top.u1.B1[1].B2[3].B3[4].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[1].B2[3].B3[4]::M3 (work@small_top.u1.B1[1].B2[3].B3[4].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[1].B2[3].B3[4]) |vpiName:N3 @@ -23170,8 +23170,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[1].B2[3].B3[5].k - |vpiModule: - \_module: work@small_top.u1.B1[1].B2[3].B3[5]::M3 (work@small_top.u1.B1[1].B2[3].B3[5].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[1].B2[3].B3[5]::M3 (work@small_top.u1.B1[1].B2[3].B3[5].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[1].B2[3].B3[5]) |vpiName:N3 @@ -23198,8 +23198,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[1].B2[3].B3[6].k - |vpiModule: - \_module: work@small_top.u1.B1[1].B2[3].B3[6]::M3 (work@small_top.u1.B1[1].B2[3].B3[6].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[1].B2[3].B3[6]::M3 (work@small_top.u1.B1[1].B2[3].B3[6].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[1].B2[3].B3[6]) |vpiName:N3 @@ -23226,8 +23226,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[1].B2[3].B3[7].k - |vpiModule: - \_module: work@small_top.u1.B1[1].B2[3].B3[7]::M3 (work@small_top.u1.B1[1].B2[3].B3[7].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[1].B2[3].B3[7]::M3 (work@small_top.u1.B1[1].B2[3].B3[7].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[1].B2[3].B3[7]) |vpiName:N3 @@ -23254,8 +23254,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[1].B2[3].B3[8].k - |vpiModule: - \_module: work@small_top.u1.B1[1].B2[3].B3[8]::M3 (work@small_top.u1.B1[1].B2[3].B3[8].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[1].B2[3].B3[8]::M3 (work@small_top.u1.B1[1].B2[3].B3[8].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[1].B2[3].B3[8]) |vpiName:N3 @@ -23282,8 +23282,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[1].B2[3].B3[9].k - |vpiModule: - \_module: work@small_top.u1.B1[1].B2[3].B3[9]::M3 (work@small_top.u1.B1[1].B2[3].B3[9].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[1].B2[3].B3[9]::M3 (work@small_top.u1.B1[1].B2[3].B3[9].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[1].B2[3].B3[9]) |vpiName:N3 @@ -23310,8 +23310,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:j |vpiFullName:work@small_top.u1.B1[1].B2[4].j - |vpiModule: - \_module: work@small_top.u1.B1[1].B2[4]::M2 (work@small_top.u1.B1[1].B2[4].N2), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:26:1, endln:26:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[1].B2[4]::M2 (work@small_top.u1.B1[1].B2[4].N2), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:26:1, endln:26:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[1].B2[4]) |vpiName:N2 @@ -23338,8 +23338,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[1].B2[4].B3[0].k - |vpiModule: - \_module: work@small_top.u1.B1[1].B2[4].B3[0]::M3 (work@small_top.u1.B1[1].B2[4].B3[0].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[1].B2[4].B3[0]::M3 (work@small_top.u1.B1[1].B2[4].B3[0].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[1].B2[4].B3[0]) |vpiName:N3 @@ -23366,8 +23366,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[1].B2[4].B3[1].k - |vpiModule: - \_module: work@small_top.u1.B1[1].B2[4].B3[1]::M3 (work@small_top.u1.B1[1].B2[4].B3[1].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[1].B2[4].B3[1]::M3 (work@small_top.u1.B1[1].B2[4].B3[1].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[1].B2[4].B3[1]) |vpiName:N3 @@ -23394,8 +23394,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[1].B2[4].B3[2].k - |vpiModule: - \_module: work@small_top.u1.B1[1].B2[4].B3[2]::M3 (work@small_top.u1.B1[1].B2[4].B3[2].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[1].B2[4].B3[2]::M3 (work@small_top.u1.B1[1].B2[4].B3[2].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[1].B2[4].B3[2]) |vpiName:N3 @@ -23422,8 +23422,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[1].B2[4].B3[3].k - |vpiModule: - \_module: work@small_top.u1.B1[1].B2[4].B3[3]::M3 (work@small_top.u1.B1[1].B2[4].B3[3].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[1].B2[4].B3[3]::M3 (work@small_top.u1.B1[1].B2[4].B3[3].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[1].B2[4].B3[3]) |vpiName:N3 @@ -23450,8 +23450,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[1].B2[4].B3[4].k - |vpiModule: - \_module: work@small_top.u1.B1[1].B2[4].B3[4]::M3 (work@small_top.u1.B1[1].B2[4].B3[4].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[1].B2[4].B3[4]::M3 (work@small_top.u1.B1[1].B2[4].B3[4].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[1].B2[4].B3[4]) |vpiName:N3 @@ -23478,8 +23478,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[1].B2[4].B3[5].k - |vpiModule: - \_module: work@small_top.u1.B1[1].B2[4].B3[5]::M3 (work@small_top.u1.B1[1].B2[4].B3[5].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[1].B2[4].B3[5]::M3 (work@small_top.u1.B1[1].B2[4].B3[5].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[1].B2[4].B3[5]) |vpiName:N3 @@ -23506,8 +23506,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[1].B2[4].B3[6].k - |vpiModule: - \_module: work@small_top.u1.B1[1].B2[4].B3[6]::M3 (work@small_top.u1.B1[1].B2[4].B3[6].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[1].B2[4].B3[6]::M3 (work@small_top.u1.B1[1].B2[4].B3[6].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[1].B2[4].B3[6]) |vpiName:N3 @@ -23534,8 +23534,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[1].B2[4].B3[7].k - |vpiModule: - \_module: work@small_top.u1.B1[1].B2[4].B3[7]::M3 (work@small_top.u1.B1[1].B2[4].B3[7].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[1].B2[4].B3[7]::M3 (work@small_top.u1.B1[1].B2[4].B3[7].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[1].B2[4].B3[7]) |vpiName:N3 @@ -23562,8 +23562,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[1].B2[4].B3[8].k - |vpiModule: - \_module: work@small_top.u1.B1[1].B2[4].B3[8]::M3 (work@small_top.u1.B1[1].B2[4].B3[8].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[1].B2[4].B3[8]::M3 (work@small_top.u1.B1[1].B2[4].B3[8].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[1].B2[4].B3[8]) |vpiName:N3 @@ -23590,8 +23590,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[1].B2[4].B3[9].k - |vpiModule: - \_module: work@small_top.u1.B1[1].B2[4].B3[9]::M3 (work@small_top.u1.B1[1].B2[4].B3[9].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[1].B2[4].B3[9]::M3 (work@small_top.u1.B1[1].B2[4].B3[9].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[1].B2[4].B3[9]) |vpiName:N3 @@ -23618,8 +23618,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:j |vpiFullName:work@small_top.u1.B1[1].B2[5].j - |vpiModule: - \_module: work@small_top.u1.B1[1].B2[5]::M2 (work@small_top.u1.B1[1].B2[5].N2), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:26:1, endln:26:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[1].B2[5]::M2 (work@small_top.u1.B1[1].B2[5].N2), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:26:1, endln:26:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[1].B2[5]) |vpiName:N2 @@ -23646,8 +23646,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[1].B2[5].B3[0].k - |vpiModule: - \_module: work@small_top.u1.B1[1].B2[5].B3[0]::M3 (work@small_top.u1.B1[1].B2[5].B3[0].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[1].B2[5].B3[0]::M3 (work@small_top.u1.B1[1].B2[5].B3[0].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[1].B2[5].B3[0]) |vpiName:N3 @@ -23674,8 +23674,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[1].B2[5].B3[1].k - |vpiModule: - \_module: work@small_top.u1.B1[1].B2[5].B3[1]::M3 (work@small_top.u1.B1[1].B2[5].B3[1].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[1].B2[5].B3[1]::M3 (work@small_top.u1.B1[1].B2[5].B3[1].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[1].B2[5].B3[1]) |vpiName:N3 @@ -23702,8 +23702,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[1].B2[5].B3[2].k - |vpiModule: - \_module: work@small_top.u1.B1[1].B2[5].B3[2]::M3 (work@small_top.u1.B1[1].B2[5].B3[2].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[1].B2[5].B3[2]::M3 (work@small_top.u1.B1[1].B2[5].B3[2].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[1].B2[5].B3[2]) |vpiName:N3 @@ -23730,8 +23730,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[1].B2[5].B3[3].k - |vpiModule: - \_module: work@small_top.u1.B1[1].B2[5].B3[3]::M3 (work@small_top.u1.B1[1].B2[5].B3[3].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[1].B2[5].B3[3]::M3 (work@small_top.u1.B1[1].B2[5].B3[3].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[1].B2[5].B3[3]) |vpiName:N3 @@ -23758,8 +23758,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[1].B2[5].B3[4].k - |vpiModule: - \_module: work@small_top.u1.B1[1].B2[5].B3[4]::M3 (work@small_top.u1.B1[1].B2[5].B3[4].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[1].B2[5].B3[4]::M3 (work@small_top.u1.B1[1].B2[5].B3[4].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[1].B2[5].B3[4]) |vpiName:N3 @@ -23786,8 +23786,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[1].B2[5].B3[5].k - |vpiModule: - \_module: work@small_top.u1.B1[1].B2[5].B3[5]::M3 (work@small_top.u1.B1[1].B2[5].B3[5].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[1].B2[5].B3[5]::M3 (work@small_top.u1.B1[1].B2[5].B3[5].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[1].B2[5].B3[5]) |vpiName:N3 @@ -23814,8 +23814,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[1].B2[5].B3[6].k - |vpiModule: - \_module: work@small_top.u1.B1[1].B2[5].B3[6]::M3 (work@small_top.u1.B1[1].B2[5].B3[6].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[1].B2[5].B3[6]::M3 (work@small_top.u1.B1[1].B2[5].B3[6].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[1].B2[5].B3[6]) |vpiName:N3 @@ -23842,8 +23842,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[1].B2[5].B3[7].k - |vpiModule: - \_module: work@small_top.u1.B1[1].B2[5].B3[7]::M3 (work@small_top.u1.B1[1].B2[5].B3[7].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[1].B2[5].B3[7]::M3 (work@small_top.u1.B1[1].B2[5].B3[7].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[1].B2[5].B3[7]) |vpiName:N3 @@ -23870,8 +23870,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[1].B2[5].B3[8].k - |vpiModule: - \_module: work@small_top.u1.B1[1].B2[5].B3[8]::M3 (work@small_top.u1.B1[1].B2[5].B3[8].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[1].B2[5].B3[8]::M3 (work@small_top.u1.B1[1].B2[5].B3[8].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[1].B2[5].B3[8]) |vpiName:N3 @@ -23898,8 +23898,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[1].B2[5].B3[9].k - |vpiModule: - \_module: work@small_top.u1.B1[1].B2[5].B3[9]::M3 (work@small_top.u1.B1[1].B2[5].B3[9].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[1].B2[5].B3[9]::M3 (work@small_top.u1.B1[1].B2[5].B3[9].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[1].B2[5].B3[9]) |vpiName:N3 @@ -23926,8 +23926,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:j |vpiFullName:work@small_top.u1.B1[1].B2[6].j - |vpiModule: - \_module: work@small_top.u1.B1[1].B2[6]::M2 (work@small_top.u1.B1[1].B2[6].N2), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:26:1, endln:26:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[1].B2[6]::M2 (work@small_top.u1.B1[1].B2[6].N2), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:26:1, endln:26:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[1].B2[6]) |vpiName:N2 @@ -23954,8 +23954,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[1].B2[6].B3[0].k - |vpiModule: - \_module: work@small_top.u1.B1[1].B2[6].B3[0]::M3 (work@small_top.u1.B1[1].B2[6].B3[0].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[1].B2[6].B3[0]::M3 (work@small_top.u1.B1[1].B2[6].B3[0].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[1].B2[6].B3[0]) |vpiName:N3 @@ -23982,8 +23982,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[1].B2[6].B3[1].k - |vpiModule: - \_module: work@small_top.u1.B1[1].B2[6].B3[1]::M3 (work@small_top.u1.B1[1].B2[6].B3[1].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[1].B2[6].B3[1]::M3 (work@small_top.u1.B1[1].B2[6].B3[1].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[1].B2[6].B3[1]) |vpiName:N3 @@ -24010,8 +24010,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[1].B2[6].B3[2].k - |vpiModule: - \_module: work@small_top.u1.B1[1].B2[6].B3[2]::M3 (work@small_top.u1.B1[1].B2[6].B3[2].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[1].B2[6].B3[2]::M3 (work@small_top.u1.B1[1].B2[6].B3[2].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[1].B2[6].B3[2]) |vpiName:N3 @@ -24038,8 +24038,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[1].B2[6].B3[3].k - |vpiModule: - \_module: work@small_top.u1.B1[1].B2[6].B3[3]::M3 (work@small_top.u1.B1[1].B2[6].B3[3].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[1].B2[6].B3[3]::M3 (work@small_top.u1.B1[1].B2[6].B3[3].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[1].B2[6].B3[3]) |vpiName:N3 @@ -24066,8 +24066,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[1].B2[6].B3[4].k - |vpiModule: - \_module: work@small_top.u1.B1[1].B2[6].B3[4]::M3 (work@small_top.u1.B1[1].B2[6].B3[4].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[1].B2[6].B3[4]::M3 (work@small_top.u1.B1[1].B2[6].B3[4].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[1].B2[6].B3[4]) |vpiName:N3 @@ -24094,8 +24094,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[1].B2[6].B3[5].k - |vpiModule: - \_module: work@small_top.u1.B1[1].B2[6].B3[5]::M3 (work@small_top.u1.B1[1].B2[6].B3[5].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[1].B2[6].B3[5]::M3 (work@small_top.u1.B1[1].B2[6].B3[5].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[1].B2[6].B3[5]) |vpiName:N3 @@ -24122,8 +24122,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[1].B2[6].B3[6].k - |vpiModule: - \_module: work@small_top.u1.B1[1].B2[6].B3[6]::M3 (work@small_top.u1.B1[1].B2[6].B3[6].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[1].B2[6].B3[6]::M3 (work@small_top.u1.B1[1].B2[6].B3[6].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[1].B2[6].B3[6]) |vpiName:N3 @@ -24150,8 +24150,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[1].B2[6].B3[7].k - |vpiModule: - \_module: work@small_top.u1.B1[1].B2[6].B3[7]::M3 (work@small_top.u1.B1[1].B2[6].B3[7].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[1].B2[6].B3[7]::M3 (work@small_top.u1.B1[1].B2[6].B3[7].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[1].B2[6].B3[7]) |vpiName:N3 @@ -24178,8 +24178,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[1].B2[6].B3[8].k - |vpiModule: - \_module: work@small_top.u1.B1[1].B2[6].B3[8]::M3 (work@small_top.u1.B1[1].B2[6].B3[8].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[1].B2[6].B3[8]::M3 (work@small_top.u1.B1[1].B2[6].B3[8].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[1].B2[6].B3[8]) |vpiName:N3 @@ -24206,8 +24206,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[1].B2[6].B3[9].k - |vpiModule: - \_module: work@small_top.u1.B1[1].B2[6].B3[9]::M3 (work@small_top.u1.B1[1].B2[6].B3[9].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[1].B2[6].B3[9]::M3 (work@small_top.u1.B1[1].B2[6].B3[9].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[1].B2[6].B3[9]) |vpiName:N3 @@ -24234,8 +24234,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:j |vpiFullName:work@small_top.u1.B1[1].B2[7].j - |vpiModule: - \_module: work@small_top.u1.B1[1].B2[7]::M2 (work@small_top.u1.B1[1].B2[7].N2), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:26:1, endln:26:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[1].B2[7]::M2 (work@small_top.u1.B1[1].B2[7].N2), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:26:1, endln:26:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[1].B2[7]) |vpiName:N2 @@ -24262,8 +24262,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[1].B2[7].B3[0].k - |vpiModule: - \_module: work@small_top.u1.B1[1].B2[7].B3[0]::M3 (work@small_top.u1.B1[1].B2[7].B3[0].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[1].B2[7].B3[0]::M3 (work@small_top.u1.B1[1].B2[7].B3[0].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[1].B2[7].B3[0]) |vpiName:N3 @@ -24290,8 +24290,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[1].B2[7].B3[1].k - |vpiModule: - \_module: work@small_top.u1.B1[1].B2[7].B3[1]::M3 (work@small_top.u1.B1[1].B2[7].B3[1].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[1].B2[7].B3[1]::M3 (work@small_top.u1.B1[1].B2[7].B3[1].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[1].B2[7].B3[1]) |vpiName:N3 @@ -24318,8 +24318,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[1].B2[7].B3[2].k - |vpiModule: - \_module: work@small_top.u1.B1[1].B2[7].B3[2]::M3 (work@small_top.u1.B1[1].B2[7].B3[2].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[1].B2[7].B3[2]::M3 (work@small_top.u1.B1[1].B2[7].B3[2].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[1].B2[7].B3[2]) |vpiName:N3 @@ -24346,8 +24346,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[1].B2[7].B3[3].k - |vpiModule: - \_module: work@small_top.u1.B1[1].B2[7].B3[3]::M3 (work@small_top.u1.B1[1].B2[7].B3[3].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[1].B2[7].B3[3]::M3 (work@small_top.u1.B1[1].B2[7].B3[3].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[1].B2[7].B3[3]) |vpiName:N3 @@ -24374,8 +24374,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[1].B2[7].B3[4].k - |vpiModule: - \_module: work@small_top.u1.B1[1].B2[7].B3[4]::M3 (work@small_top.u1.B1[1].B2[7].B3[4].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[1].B2[7].B3[4]::M3 (work@small_top.u1.B1[1].B2[7].B3[4].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[1].B2[7].B3[4]) |vpiName:N3 @@ -24402,8 +24402,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[1].B2[7].B3[5].k - |vpiModule: - \_module: work@small_top.u1.B1[1].B2[7].B3[5]::M3 (work@small_top.u1.B1[1].B2[7].B3[5].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[1].B2[7].B3[5]::M3 (work@small_top.u1.B1[1].B2[7].B3[5].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[1].B2[7].B3[5]) |vpiName:N3 @@ -24430,8 +24430,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[1].B2[7].B3[6].k - |vpiModule: - \_module: work@small_top.u1.B1[1].B2[7].B3[6]::M3 (work@small_top.u1.B1[1].B2[7].B3[6].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[1].B2[7].B3[6]::M3 (work@small_top.u1.B1[1].B2[7].B3[6].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[1].B2[7].B3[6]) |vpiName:N3 @@ -24458,8 +24458,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[1].B2[7].B3[7].k - |vpiModule: - \_module: work@small_top.u1.B1[1].B2[7].B3[7]::M3 (work@small_top.u1.B1[1].B2[7].B3[7].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[1].B2[7].B3[7]::M3 (work@small_top.u1.B1[1].B2[7].B3[7].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[1].B2[7].B3[7]) |vpiName:N3 @@ -24486,8 +24486,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[1].B2[7].B3[8].k - |vpiModule: - \_module: work@small_top.u1.B1[1].B2[7].B3[8]::M3 (work@small_top.u1.B1[1].B2[7].B3[8].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[1].B2[7].B3[8]::M3 (work@small_top.u1.B1[1].B2[7].B3[8].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[1].B2[7].B3[8]) |vpiName:N3 @@ -24514,8 +24514,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[1].B2[7].B3[9].k - |vpiModule: - \_module: work@small_top.u1.B1[1].B2[7].B3[9]::M3 (work@small_top.u1.B1[1].B2[7].B3[9].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[1].B2[7].B3[9]::M3 (work@small_top.u1.B1[1].B2[7].B3[9].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[1].B2[7].B3[9]) |vpiName:N3 @@ -24542,8 +24542,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:j |vpiFullName:work@small_top.u1.B1[1].B2[8].j - |vpiModule: - \_module: work@small_top.u1.B1[1].B2[8]::M2 (work@small_top.u1.B1[1].B2[8].N2), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:26:1, endln:26:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[1].B2[8]::M2 (work@small_top.u1.B1[1].B2[8].N2), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:26:1, endln:26:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[1].B2[8]) |vpiName:N2 @@ -24570,8 +24570,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[1].B2[8].B3[0].k - |vpiModule: - \_module: work@small_top.u1.B1[1].B2[8].B3[0]::M3 (work@small_top.u1.B1[1].B2[8].B3[0].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[1].B2[8].B3[0]::M3 (work@small_top.u1.B1[1].B2[8].B3[0].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[1].B2[8].B3[0]) |vpiName:N3 @@ -24598,8 +24598,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[1].B2[8].B3[1].k - |vpiModule: - \_module: work@small_top.u1.B1[1].B2[8].B3[1]::M3 (work@small_top.u1.B1[1].B2[8].B3[1].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[1].B2[8].B3[1]::M3 (work@small_top.u1.B1[1].B2[8].B3[1].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[1].B2[8].B3[1]) |vpiName:N3 @@ -24626,8 +24626,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[1].B2[8].B3[2].k - |vpiModule: - \_module: work@small_top.u1.B1[1].B2[8].B3[2]::M3 (work@small_top.u1.B1[1].B2[8].B3[2].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[1].B2[8].B3[2]::M3 (work@small_top.u1.B1[1].B2[8].B3[2].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[1].B2[8].B3[2]) |vpiName:N3 @@ -24654,8 +24654,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[1].B2[8].B3[3].k - |vpiModule: - \_module: work@small_top.u1.B1[1].B2[8].B3[3]::M3 (work@small_top.u1.B1[1].B2[8].B3[3].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[1].B2[8].B3[3]::M3 (work@small_top.u1.B1[1].B2[8].B3[3].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[1].B2[8].B3[3]) |vpiName:N3 @@ -24682,8 +24682,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[1].B2[8].B3[4].k - |vpiModule: - \_module: work@small_top.u1.B1[1].B2[8].B3[4]::M3 (work@small_top.u1.B1[1].B2[8].B3[4].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[1].B2[8].B3[4]::M3 (work@small_top.u1.B1[1].B2[8].B3[4].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[1].B2[8].B3[4]) |vpiName:N3 @@ -24710,8 +24710,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[1].B2[8].B3[5].k - |vpiModule: - \_module: work@small_top.u1.B1[1].B2[8].B3[5]::M3 (work@small_top.u1.B1[1].B2[8].B3[5].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[1].B2[8].B3[5]::M3 (work@small_top.u1.B1[1].B2[8].B3[5].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[1].B2[8].B3[5]) |vpiName:N3 @@ -24738,8 +24738,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[1].B2[8].B3[6].k - |vpiModule: - \_module: work@small_top.u1.B1[1].B2[8].B3[6]::M3 (work@small_top.u1.B1[1].B2[8].B3[6].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[1].B2[8].B3[6]::M3 (work@small_top.u1.B1[1].B2[8].B3[6].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[1].B2[8].B3[6]) |vpiName:N3 @@ -24766,8 +24766,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[1].B2[8].B3[7].k - |vpiModule: - \_module: work@small_top.u1.B1[1].B2[8].B3[7]::M3 (work@small_top.u1.B1[1].B2[8].B3[7].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[1].B2[8].B3[7]::M3 (work@small_top.u1.B1[1].B2[8].B3[7].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[1].B2[8].B3[7]) |vpiName:N3 @@ -24794,8 +24794,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[1].B2[8].B3[8].k - |vpiModule: - \_module: work@small_top.u1.B1[1].B2[8].B3[8]::M3 (work@small_top.u1.B1[1].B2[8].B3[8].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[1].B2[8].B3[8]::M3 (work@small_top.u1.B1[1].B2[8].B3[8].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[1].B2[8].B3[8]) |vpiName:N3 @@ -24822,8 +24822,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[1].B2[8].B3[9].k - |vpiModule: - \_module: work@small_top.u1.B1[1].B2[8].B3[9]::M3 (work@small_top.u1.B1[1].B2[8].B3[9].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[1].B2[8].B3[9]::M3 (work@small_top.u1.B1[1].B2[8].B3[9].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[1].B2[8].B3[9]) |vpiName:N3 @@ -24850,8 +24850,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:j |vpiFullName:work@small_top.u1.B1[1].B2[9].j - |vpiModule: - \_module: work@small_top.u1.B1[1].B2[9]::M2 (work@small_top.u1.B1[1].B2[9].N2), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:26:1, endln:26:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[1].B2[9]::M2 (work@small_top.u1.B1[1].B2[9].N2), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:26:1, endln:26:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[1].B2[9]) |vpiName:N2 @@ -24878,8 +24878,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[1].B2[9].B3[0].k - |vpiModule: - \_module: work@small_top.u1.B1[1].B2[9].B3[0]::M3 (work@small_top.u1.B1[1].B2[9].B3[0].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[1].B2[9].B3[0]::M3 (work@small_top.u1.B1[1].B2[9].B3[0].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[1].B2[9].B3[0]) |vpiName:N3 @@ -24906,8 +24906,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[1].B2[9].B3[1].k - |vpiModule: - \_module: work@small_top.u1.B1[1].B2[9].B3[1]::M3 (work@small_top.u1.B1[1].B2[9].B3[1].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[1].B2[9].B3[1]::M3 (work@small_top.u1.B1[1].B2[9].B3[1].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[1].B2[9].B3[1]) |vpiName:N3 @@ -24934,8 +24934,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[1].B2[9].B3[2].k - |vpiModule: - \_module: work@small_top.u1.B1[1].B2[9].B3[2]::M3 (work@small_top.u1.B1[1].B2[9].B3[2].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[1].B2[9].B3[2]::M3 (work@small_top.u1.B1[1].B2[9].B3[2].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[1].B2[9].B3[2]) |vpiName:N3 @@ -24962,8 +24962,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[1].B2[9].B3[3].k - |vpiModule: - \_module: work@small_top.u1.B1[1].B2[9].B3[3]::M3 (work@small_top.u1.B1[1].B2[9].B3[3].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[1].B2[9].B3[3]::M3 (work@small_top.u1.B1[1].B2[9].B3[3].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[1].B2[9].B3[3]) |vpiName:N3 @@ -24990,8 +24990,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[1].B2[9].B3[4].k - |vpiModule: - \_module: work@small_top.u1.B1[1].B2[9].B3[4]::M3 (work@small_top.u1.B1[1].B2[9].B3[4].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[1].B2[9].B3[4]::M3 (work@small_top.u1.B1[1].B2[9].B3[4].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[1].B2[9].B3[4]) |vpiName:N3 @@ -25018,8 +25018,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[1].B2[9].B3[5].k - |vpiModule: - \_module: work@small_top.u1.B1[1].B2[9].B3[5]::M3 (work@small_top.u1.B1[1].B2[9].B3[5].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[1].B2[9].B3[5]::M3 (work@small_top.u1.B1[1].B2[9].B3[5].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[1].B2[9].B3[5]) |vpiName:N3 @@ -25046,8 +25046,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[1].B2[9].B3[6].k - |vpiModule: - \_module: work@small_top.u1.B1[1].B2[9].B3[6]::M3 (work@small_top.u1.B1[1].B2[9].B3[6].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[1].B2[9].B3[6]::M3 (work@small_top.u1.B1[1].B2[9].B3[6].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[1].B2[9].B3[6]) |vpiName:N3 @@ -25074,8 +25074,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[1].B2[9].B3[7].k - |vpiModule: - \_module: work@small_top.u1.B1[1].B2[9].B3[7]::M3 (work@small_top.u1.B1[1].B2[9].B3[7].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[1].B2[9].B3[7]::M3 (work@small_top.u1.B1[1].B2[9].B3[7].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[1].B2[9].B3[7]) |vpiName:N3 @@ -25102,8 +25102,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[1].B2[9].B3[8].k - |vpiModule: - \_module: work@small_top.u1.B1[1].B2[9].B3[8]::M3 (work@small_top.u1.B1[1].B2[9].B3[8].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[1].B2[9].B3[8]::M3 (work@small_top.u1.B1[1].B2[9].B3[8].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[1].B2[9].B3[8]) |vpiName:N3 @@ -25130,8 +25130,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[1].B2[9].B3[9].k - |vpiModule: - \_module: work@small_top.u1.B1[1].B2[9].B3[9]::M3 (work@small_top.u1.B1[1].B2[9].B3[9].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[1].B2[9].B3[9]::M3 (work@small_top.u1.B1[1].B2[9].B3[9].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[1].B2[9].B3[9]) |vpiName:N3 @@ -25169,8 +25169,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:m |vpiFullName:work@small_top.u1.B1[1].B4.B5[0].m - |vpiModule: - \_module: work@small_top.u1.B1[1].B4.B5[0]::M4 (work@small_top.u1.B1[1].B4.B5[0].N4), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:46:1, endln:46:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[1].B4.B5[0]::M4 (work@small_top.u1.B1[1].B4.B5[0].N4), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:46:1, endln:46:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[1].B4.B5[0]) |vpiName:N4 @@ -25197,8 +25197,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:m |vpiFullName:work@small_top.u1.B1[1].B4.B5[1].m - |vpiModule: - \_module: work@small_top.u1.B1[1].B4.B5[1]::M4 (work@small_top.u1.B1[1].B4.B5[1].N4), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:46:1, endln:46:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[1].B4.B5[1]::M4 (work@small_top.u1.B1[1].B4.B5[1].N4), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:46:1, endln:46:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[1].B4.B5[1]) |vpiName:N4 @@ -25225,8 +25225,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:m |vpiFullName:work@small_top.u1.B1[1].B4.B5[2].m - |vpiModule: - \_module: work@small_top.u1.B1[1].B4.B5[2]::M4 (work@small_top.u1.B1[1].B4.B5[2].N4), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:46:1, endln:46:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[1].B4.B5[2]::M4 (work@small_top.u1.B1[1].B4.B5[2].N4), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:46:1, endln:46:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[1].B4.B5[2]) |vpiName:N4 @@ -25253,8 +25253,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:m |vpiFullName:work@small_top.u1.B1[1].B4.B5[3].m - |vpiModule: - \_module: work@small_top.u1.B1[1].B4.B5[3]::M4 (work@small_top.u1.B1[1].B4.B5[3].N4), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:46:1, endln:46:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[1].B4.B5[3]::M4 (work@small_top.u1.B1[1].B4.B5[3].N4), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:46:1, endln:46:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[1].B4.B5[3]) |vpiName:N4 @@ -25281,8 +25281,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:m |vpiFullName:work@small_top.u1.B1[1].B4.B5[4].m - |vpiModule: - \_module: work@small_top.u1.B1[1].B4.B5[4]::M4 (work@small_top.u1.B1[1].B4.B5[4].N4), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:46:1, endln:46:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[1].B4.B5[4]::M4 (work@small_top.u1.B1[1].B4.B5[4].N4), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:46:1, endln:46:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[1].B4.B5[4]) |vpiName:N4 @@ -25309,8 +25309,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:m |vpiFullName:work@small_top.u1.B1[1].B4.B5[5].m - |vpiModule: - \_module: work@small_top.u1.B1[1].B4.B5[5]::M4 (work@small_top.u1.B1[1].B4.B5[5].N4), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:46:1, endln:46:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[1].B4.B5[5]::M4 (work@small_top.u1.B1[1].B4.B5[5].N4), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:46:1, endln:46:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[1].B4.B5[5]) |vpiName:N4 @@ -25337,8 +25337,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:m |vpiFullName:work@small_top.u1.B1[1].B4.B5[6].m - |vpiModule: - \_module: work@small_top.u1.B1[1].B4.B5[6]::M4 (work@small_top.u1.B1[1].B4.B5[6].N4), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:46:1, endln:46:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[1].B4.B5[6]::M4 (work@small_top.u1.B1[1].B4.B5[6].N4), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:46:1, endln:46:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[1].B4.B5[6]) |vpiName:N4 @@ -25365,8 +25365,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:m |vpiFullName:work@small_top.u1.B1[1].B4.B5[7].m - |vpiModule: - \_module: work@small_top.u1.B1[1].B4.B5[7]::M4 (work@small_top.u1.B1[1].B4.B5[7].N4), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:46:1, endln:46:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[1].B4.B5[7]::M4 (work@small_top.u1.B1[1].B4.B5[7].N4), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:46:1, endln:46:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[1].B4.B5[7]) |vpiName:N4 @@ -25393,8 +25393,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:m |vpiFullName:work@small_top.u1.B1[1].B4.B5[8].m - |vpiModule: - \_module: work@small_top.u1.B1[1].B4.B5[8]::M4 (work@small_top.u1.B1[1].B4.B5[8].N4), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:46:1, endln:46:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[1].B4.B5[8]::M4 (work@small_top.u1.B1[1].B4.B5[8].N4), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:46:1, endln:46:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[1].B4.B5[8]) |vpiName:N4 @@ -25421,8 +25421,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:m |vpiFullName:work@small_top.u1.B1[1].B4.B5[9].m - |vpiModule: - \_module: work@small_top.u1.B1[1].B4.B5[9]::M4 (work@small_top.u1.B1[1].B4.B5[9].N4), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:46:1, endln:46:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[1].B4.B5[9]::M4 (work@small_top.u1.B1[1].B4.B5[9].N4), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:46:1, endln:46:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[1].B4.B5[9]) |vpiName:N4 @@ -25431,7 +25431,7 @@ design: (work@bottom1) |vpiGenScopeArray: \_gen_scope_array: (work@small_top.u1.B1[2]), line:17:1, endln:51:4 |vpiParent: - \_module: work@small_test (work@small_top.u1), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:2:4, endln:2:29 + \_module_inst: work@small_test (work@small_top.u1), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:2:4, endln:2:29 |vpiName:B1[2] |vpiFullName:work@small_top.u1.B1[2] |vpiGenScope: @@ -25449,8 +25449,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:i |vpiFullName:work@small_top.u1.B1[2].i - |vpiModule: - \_module: work@small_top.u1.B1[2]::M1 (work@small_top.u1.B1[2].N1), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:20:1, endln:20:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[2]::M1 (work@small_top.u1.B1[2].N1), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:20:1, endln:20:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[2]) |vpiName:N1 @@ -25477,8 +25477,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:j |vpiFullName:work@small_top.u1.B1[2].B2[0].j - |vpiModule: - \_module: work@small_top.u1.B1[2].B2[0]::M2 (work@small_top.u1.B1[2].B2[0].N2), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:26:1, endln:26:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[2].B2[0]::M2 (work@small_top.u1.B1[2].B2[0].N2), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:26:1, endln:26:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[2].B2[0]) |vpiName:N2 @@ -25505,8 +25505,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[2].B2[0].B3[0].k - |vpiModule: - \_module: work@small_top.u1.B1[2].B2[0].B3[0]::M3 (work@small_top.u1.B1[2].B2[0].B3[0].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[2].B2[0].B3[0]::M3 (work@small_top.u1.B1[2].B2[0].B3[0].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[2].B2[0].B3[0]) |vpiName:N3 @@ -25533,8 +25533,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[2].B2[0].B3[1].k - |vpiModule: - \_module: work@small_top.u1.B1[2].B2[0].B3[1]::M3 (work@small_top.u1.B1[2].B2[0].B3[1].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[2].B2[0].B3[1]::M3 (work@small_top.u1.B1[2].B2[0].B3[1].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[2].B2[0].B3[1]) |vpiName:N3 @@ -25561,8 +25561,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[2].B2[0].B3[2].k - |vpiModule: - \_module: work@small_top.u1.B1[2].B2[0].B3[2]::M3 (work@small_top.u1.B1[2].B2[0].B3[2].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[2].B2[0].B3[2]::M3 (work@small_top.u1.B1[2].B2[0].B3[2].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[2].B2[0].B3[2]) |vpiName:N3 @@ -25589,8 +25589,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[2].B2[0].B3[3].k - |vpiModule: - \_module: work@small_top.u1.B1[2].B2[0].B3[3]::M3 (work@small_top.u1.B1[2].B2[0].B3[3].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[2].B2[0].B3[3]::M3 (work@small_top.u1.B1[2].B2[0].B3[3].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[2].B2[0].B3[3]) |vpiName:N3 @@ -25617,8 +25617,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[2].B2[0].B3[4].k - |vpiModule: - \_module: work@small_top.u1.B1[2].B2[0].B3[4]::M3 (work@small_top.u1.B1[2].B2[0].B3[4].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[2].B2[0].B3[4]::M3 (work@small_top.u1.B1[2].B2[0].B3[4].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[2].B2[0].B3[4]) |vpiName:N3 @@ -25645,8 +25645,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[2].B2[0].B3[5].k - |vpiModule: - \_module: work@small_top.u1.B1[2].B2[0].B3[5]::M3 (work@small_top.u1.B1[2].B2[0].B3[5].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[2].B2[0].B3[5]::M3 (work@small_top.u1.B1[2].B2[0].B3[5].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[2].B2[0].B3[5]) |vpiName:N3 @@ -25673,8 +25673,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[2].B2[0].B3[6].k - |vpiModule: - \_module: work@small_top.u1.B1[2].B2[0].B3[6]::M3 (work@small_top.u1.B1[2].B2[0].B3[6].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[2].B2[0].B3[6]::M3 (work@small_top.u1.B1[2].B2[0].B3[6].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[2].B2[0].B3[6]) |vpiName:N3 @@ -25701,8 +25701,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[2].B2[0].B3[7].k - |vpiModule: - \_module: work@small_top.u1.B1[2].B2[0].B3[7]::M3 (work@small_top.u1.B1[2].B2[0].B3[7].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[2].B2[0].B3[7]::M3 (work@small_top.u1.B1[2].B2[0].B3[7].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[2].B2[0].B3[7]) |vpiName:N3 @@ -25729,8 +25729,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[2].B2[0].B3[8].k - |vpiModule: - \_module: work@small_top.u1.B1[2].B2[0].B3[8]::M3 (work@small_top.u1.B1[2].B2[0].B3[8].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[2].B2[0].B3[8]::M3 (work@small_top.u1.B1[2].B2[0].B3[8].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[2].B2[0].B3[8]) |vpiName:N3 @@ -25757,8 +25757,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[2].B2[0].B3[9].k - |vpiModule: - \_module: work@small_top.u1.B1[2].B2[0].B3[9]::M3 (work@small_top.u1.B1[2].B2[0].B3[9].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[2].B2[0].B3[9]::M3 (work@small_top.u1.B1[2].B2[0].B3[9].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[2].B2[0].B3[9]) |vpiName:N3 @@ -25785,8 +25785,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:j |vpiFullName:work@small_top.u1.B1[2].B2[1].j - |vpiModule: - \_module: work@small_top.u1.B1[2].B2[1]::M2 (work@small_top.u1.B1[2].B2[1].N2), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:26:1, endln:26:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[2].B2[1]::M2 (work@small_top.u1.B1[2].B2[1].N2), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:26:1, endln:26:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[2].B2[1]) |vpiName:N2 @@ -25813,8 +25813,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[2].B2[1].B3[0].k - |vpiModule: - \_module: work@small_top.u1.B1[2].B2[1].B3[0]::M3 (work@small_top.u1.B1[2].B2[1].B3[0].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[2].B2[1].B3[0]::M3 (work@small_top.u1.B1[2].B2[1].B3[0].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[2].B2[1].B3[0]) |vpiName:N3 @@ -25841,8 +25841,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[2].B2[1].B3[1].k - |vpiModule: - \_module: work@small_top.u1.B1[2].B2[1].B3[1]::M3 (work@small_top.u1.B1[2].B2[1].B3[1].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[2].B2[1].B3[1]::M3 (work@small_top.u1.B1[2].B2[1].B3[1].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[2].B2[1].B3[1]) |vpiName:N3 @@ -25869,8 +25869,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[2].B2[1].B3[2].k - |vpiModule: - \_module: work@small_top.u1.B1[2].B2[1].B3[2]::M3 (work@small_top.u1.B1[2].B2[1].B3[2].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[2].B2[1].B3[2]::M3 (work@small_top.u1.B1[2].B2[1].B3[2].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[2].B2[1].B3[2]) |vpiName:N3 @@ -25897,8 +25897,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[2].B2[1].B3[3].k - |vpiModule: - \_module: work@small_top.u1.B1[2].B2[1].B3[3]::M3 (work@small_top.u1.B1[2].B2[1].B3[3].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[2].B2[1].B3[3]::M3 (work@small_top.u1.B1[2].B2[1].B3[3].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[2].B2[1].B3[3]) |vpiName:N3 @@ -25925,8 +25925,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[2].B2[1].B3[4].k - |vpiModule: - \_module: work@small_top.u1.B1[2].B2[1].B3[4]::M3 (work@small_top.u1.B1[2].B2[1].B3[4].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[2].B2[1].B3[4]::M3 (work@small_top.u1.B1[2].B2[1].B3[4].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[2].B2[1].B3[4]) |vpiName:N3 @@ -25953,8 +25953,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[2].B2[1].B3[5].k - |vpiModule: - \_module: work@small_top.u1.B1[2].B2[1].B3[5]::M3 (work@small_top.u1.B1[2].B2[1].B3[5].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[2].B2[1].B3[5]::M3 (work@small_top.u1.B1[2].B2[1].B3[5].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[2].B2[1].B3[5]) |vpiName:N3 @@ -25981,8 +25981,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[2].B2[1].B3[6].k - |vpiModule: - \_module: work@small_top.u1.B1[2].B2[1].B3[6]::M3 (work@small_top.u1.B1[2].B2[1].B3[6].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[2].B2[1].B3[6]::M3 (work@small_top.u1.B1[2].B2[1].B3[6].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[2].B2[1].B3[6]) |vpiName:N3 @@ -26009,8 +26009,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[2].B2[1].B3[7].k - |vpiModule: - \_module: work@small_top.u1.B1[2].B2[1].B3[7]::M3 (work@small_top.u1.B1[2].B2[1].B3[7].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[2].B2[1].B3[7]::M3 (work@small_top.u1.B1[2].B2[1].B3[7].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[2].B2[1].B3[7]) |vpiName:N3 @@ -26037,8 +26037,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[2].B2[1].B3[8].k - |vpiModule: - \_module: work@small_top.u1.B1[2].B2[1].B3[8]::M3 (work@small_top.u1.B1[2].B2[1].B3[8].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[2].B2[1].B3[8]::M3 (work@small_top.u1.B1[2].B2[1].B3[8].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[2].B2[1].B3[8]) |vpiName:N3 @@ -26065,8 +26065,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[2].B2[1].B3[9].k - |vpiModule: - \_module: work@small_top.u1.B1[2].B2[1].B3[9]::M3 (work@small_top.u1.B1[2].B2[1].B3[9].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[2].B2[1].B3[9]::M3 (work@small_top.u1.B1[2].B2[1].B3[9].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[2].B2[1].B3[9]) |vpiName:N3 @@ -26093,8 +26093,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:j |vpiFullName:work@small_top.u1.B1[2].B2[2].j - |vpiModule: - \_module: work@small_top.u1.B1[2].B2[2]::M2 (work@small_top.u1.B1[2].B2[2].N2), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:26:1, endln:26:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[2].B2[2]::M2 (work@small_top.u1.B1[2].B2[2].N2), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:26:1, endln:26:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[2].B2[2]) |vpiName:N2 @@ -26121,8 +26121,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[2].B2[2].B3[0].k - |vpiModule: - \_module: work@small_top.u1.B1[2].B2[2].B3[0]::M3 (work@small_top.u1.B1[2].B2[2].B3[0].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[2].B2[2].B3[0]::M3 (work@small_top.u1.B1[2].B2[2].B3[0].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[2].B2[2].B3[0]) |vpiName:N3 @@ -26149,8 +26149,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[2].B2[2].B3[1].k - |vpiModule: - \_module: work@small_top.u1.B1[2].B2[2].B3[1]::M3 (work@small_top.u1.B1[2].B2[2].B3[1].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[2].B2[2].B3[1]::M3 (work@small_top.u1.B1[2].B2[2].B3[1].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[2].B2[2].B3[1]) |vpiName:N3 @@ -26177,8 +26177,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[2].B2[2].B3[2].k - |vpiModule: - \_module: work@small_top.u1.B1[2].B2[2].B3[2]::M3 (work@small_top.u1.B1[2].B2[2].B3[2].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[2].B2[2].B3[2]::M3 (work@small_top.u1.B1[2].B2[2].B3[2].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[2].B2[2].B3[2]) |vpiName:N3 @@ -26205,8 +26205,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[2].B2[2].B3[3].k - |vpiModule: - \_module: work@small_top.u1.B1[2].B2[2].B3[3]::M3 (work@small_top.u1.B1[2].B2[2].B3[3].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[2].B2[2].B3[3]::M3 (work@small_top.u1.B1[2].B2[2].B3[3].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[2].B2[2].B3[3]) |vpiName:N3 @@ -26233,8 +26233,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[2].B2[2].B3[4].k - |vpiModule: - \_module: work@small_top.u1.B1[2].B2[2].B3[4]::M3 (work@small_top.u1.B1[2].B2[2].B3[4].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[2].B2[2].B3[4]::M3 (work@small_top.u1.B1[2].B2[2].B3[4].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[2].B2[2].B3[4]) |vpiName:N3 @@ -26261,8 +26261,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[2].B2[2].B3[5].k - |vpiModule: - \_module: work@small_top.u1.B1[2].B2[2].B3[5]::M3 (work@small_top.u1.B1[2].B2[2].B3[5].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[2].B2[2].B3[5]::M3 (work@small_top.u1.B1[2].B2[2].B3[5].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[2].B2[2].B3[5]) |vpiName:N3 @@ -26289,8 +26289,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[2].B2[2].B3[6].k - |vpiModule: - \_module: work@small_top.u1.B1[2].B2[2].B3[6]::M3 (work@small_top.u1.B1[2].B2[2].B3[6].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[2].B2[2].B3[6]::M3 (work@small_top.u1.B1[2].B2[2].B3[6].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[2].B2[2].B3[6]) |vpiName:N3 @@ -26317,8 +26317,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[2].B2[2].B3[7].k - |vpiModule: - \_module: work@small_top.u1.B1[2].B2[2].B3[7]::M3 (work@small_top.u1.B1[2].B2[2].B3[7].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[2].B2[2].B3[7]::M3 (work@small_top.u1.B1[2].B2[2].B3[7].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[2].B2[2].B3[7]) |vpiName:N3 @@ -26345,8 +26345,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[2].B2[2].B3[8].k - |vpiModule: - \_module: work@small_top.u1.B1[2].B2[2].B3[8]::M3 (work@small_top.u1.B1[2].B2[2].B3[8].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[2].B2[2].B3[8]::M3 (work@small_top.u1.B1[2].B2[2].B3[8].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[2].B2[2].B3[8]) |vpiName:N3 @@ -26373,8 +26373,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[2].B2[2].B3[9].k - |vpiModule: - \_module: work@small_top.u1.B1[2].B2[2].B3[9]::M3 (work@small_top.u1.B1[2].B2[2].B3[9].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[2].B2[2].B3[9]::M3 (work@small_top.u1.B1[2].B2[2].B3[9].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[2].B2[2].B3[9]) |vpiName:N3 @@ -26401,8 +26401,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:j |vpiFullName:work@small_top.u1.B1[2].B2[3].j - |vpiModule: - \_module: work@small_top.u1.B1[2].B2[3]::M2 (work@small_top.u1.B1[2].B2[3].N2), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:26:1, endln:26:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[2].B2[3]::M2 (work@small_top.u1.B1[2].B2[3].N2), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:26:1, endln:26:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[2].B2[3]) |vpiName:N2 @@ -26429,8 +26429,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[2].B2[3].B3[0].k - |vpiModule: - \_module: work@small_top.u1.B1[2].B2[3].B3[0]::M3 (work@small_top.u1.B1[2].B2[3].B3[0].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[2].B2[3].B3[0]::M3 (work@small_top.u1.B1[2].B2[3].B3[0].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[2].B2[3].B3[0]) |vpiName:N3 @@ -26457,8 +26457,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[2].B2[3].B3[1].k - |vpiModule: - \_module: work@small_top.u1.B1[2].B2[3].B3[1]::M3 (work@small_top.u1.B1[2].B2[3].B3[1].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[2].B2[3].B3[1]::M3 (work@small_top.u1.B1[2].B2[3].B3[1].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[2].B2[3].B3[1]) |vpiName:N3 @@ -26485,8 +26485,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[2].B2[3].B3[2].k - |vpiModule: - \_module: work@small_top.u1.B1[2].B2[3].B3[2]::M3 (work@small_top.u1.B1[2].B2[3].B3[2].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[2].B2[3].B3[2]::M3 (work@small_top.u1.B1[2].B2[3].B3[2].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[2].B2[3].B3[2]) |vpiName:N3 @@ -26513,8 +26513,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[2].B2[3].B3[3].k - |vpiModule: - \_module: work@small_top.u1.B1[2].B2[3].B3[3]::M3 (work@small_top.u1.B1[2].B2[3].B3[3].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[2].B2[3].B3[3]::M3 (work@small_top.u1.B1[2].B2[3].B3[3].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[2].B2[3].B3[3]) |vpiName:N3 @@ -26541,8 +26541,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[2].B2[3].B3[4].k - |vpiModule: - \_module: work@small_top.u1.B1[2].B2[3].B3[4]::M3 (work@small_top.u1.B1[2].B2[3].B3[4].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[2].B2[3].B3[4]::M3 (work@small_top.u1.B1[2].B2[3].B3[4].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[2].B2[3].B3[4]) |vpiName:N3 @@ -26569,8 +26569,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[2].B2[3].B3[5].k - |vpiModule: - \_module: work@small_top.u1.B1[2].B2[3].B3[5]::M3 (work@small_top.u1.B1[2].B2[3].B3[5].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[2].B2[3].B3[5]::M3 (work@small_top.u1.B1[2].B2[3].B3[5].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[2].B2[3].B3[5]) |vpiName:N3 @@ -26597,8 +26597,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[2].B2[3].B3[6].k - |vpiModule: - \_module: work@small_top.u1.B1[2].B2[3].B3[6]::M3 (work@small_top.u1.B1[2].B2[3].B3[6].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[2].B2[3].B3[6]::M3 (work@small_top.u1.B1[2].B2[3].B3[6].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[2].B2[3].B3[6]) |vpiName:N3 @@ -26625,8 +26625,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[2].B2[3].B3[7].k - |vpiModule: - \_module: work@small_top.u1.B1[2].B2[3].B3[7]::M3 (work@small_top.u1.B1[2].B2[3].B3[7].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[2].B2[3].B3[7]::M3 (work@small_top.u1.B1[2].B2[3].B3[7].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[2].B2[3].B3[7]) |vpiName:N3 @@ -26653,8 +26653,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[2].B2[3].B3[8].k - |vpiModule: - \_module: work@small_top.u1.B1[2].B2[3].B3[8]::M3 (work@small_top.u1.B1[2].B2[3].B3[8].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[2].B2[3].B3[8]::M3 (work@small_top.u1.B1[2].B2[3].B3[8].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[2].B2[3].B3[8]) |vpiName:N3 @@ -26681,8 +26681,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[2].B2[3].B3[9].k - |vpiModule: - \_module: work@small_top.u1.B1[2].B2[3].B3[9]::M3 (work@small_top.u1.B1[2].B2[3].B3[9].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[2].B2[3].B3[9]::M3 (work@small_top.u1.B1[2].B2[3].B3[9].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[2].B2[3].B3[9]) |vpiName:N3 @@ -26709,8 +26709,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:j |vpiFullName:work@small_top.u1.B1[2].B2[4].j - |vpiModule: - \_module: work@small_top.u1.B1[2].B2[4]::M2 (work@small_top.u1.B1[2].B2[4].N2), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:26:1, endln:26:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[2].B2[4]::M2 (work@small_top.u1.B1[2].B2[4].N2), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:26:1, endln:26:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[2].B2[4]) |vpiName:N2 @@ -26737,8 +26737,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[2].B2[4].B3[0].k - |vpiModule: - \_module: work@small_top.u1.B1[2].B2[4].B3[0]::M3 (work@small_top.u1.B1[2].B2[4].B3[0].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[2].B2[4].B3[0]::M3 (work@small_top.u1.B1[2].B2[4].B3[0].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[2].B2[4].B3[0]) |vpiName:N3 @@ -26765,8 +26765,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[2].B2[4].B3[1].k - |vpiModule: - \_module: work@small_top.u1.B1[2].B2[4].B3[1]::M3 (work@small_top.u1.B1[2].B2[4].B3[1].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[2].B2[4].B3[1]::M3 (work@small_top.u1.B1[2].B2[4].B3[1].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[2].B2[4].B3[1]) |vpiName:N3 @@ -26793,8 +26793,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[2].B2[4].B3[2].k - |vpiModule: - \_module: work@small_top.u1.B1[2].B2[4].B3[2]::M3 (work@small_top.u1.B1[2].B2[4].B3[2].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[2].B2[4].B3[2]::M3 (work@small_top.u1.B1[2].B2[4].B3[2].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[2].B2[4].B3[2]) |vpiName:N3 @@ -26821,8 +26821,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[2].B2[4].B3[3].k - |vpiModule: - \_module: work@small_top.u1.B1[2].B2[4].B3[3]::M3 (work@small_top.u1.B1[2].B2[4].B3[3].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[2].B2[4].B3[3]::M3 (work@small_top.u1.B1[2].B2[4].B3[3].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[2].B2[4].B3[3]) |vpiName:N3 @@ -26849,8 +26849,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[2].B2[4].B3[4].k - |vpiModule: - \_module: work@small_top.u1.B1[2].B2[4].B3[4]::M3 (work@small_top.u1.B1[2].B2[4].B3[4].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[2].B2[4].B3[4]::M3 (work@small_top.u1.B1[2].B2[4].B3[4].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[2].B2[4].B3[4]) |vpiName:N3 @@ -26877,8 +26877,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[2].B2[4].B3[5].k - |vpiModule: - \_module: work@small_top.u1.B1[2].B2[4].B3[5]::M3 (work@small_top.u1.B1[2].B2[4].B3[5].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[2].B2[4].B3[5]::M3 (work@small_top.u1.B1[2].B2[4].B3[5].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[2].B2[4].B3[5]) |vpiName:N3 @@ -26905,8 +26905,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[2].B2[4].B3[6].k - |vpiModule: - \_module: work@small_top.u1.B1[2].B2[4].B3[6]::M3 (work@small_top.u1.B1[2].B2[4].B3[6].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[2].B2[4].B3[6]::M3 (work@small_top.u1.B1[2].B2[4].B3[6].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[2].B2[4].B3[6]) |vpiName:N3 @@ -26933,8 +26933,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[2].B2[4].B3[7].k - |vpiModule: - \_module: work@small_top.u1.B1[2].B2[4].B3[7]::M3 (work@small_top.u1.B1[2].B2[4].B3[7].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[2].B2[4].B3[7]::M3 (work@small_top.u1.B1[2].B2[4].B3[7].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[2].B2[4].B3[7]) |vpiName:N3 @@ -26961,8 +26961,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[2].B2[4].B3[8].k - |vpiModule: - \_module: work@small_top.u1.B1[2].B2[4].B3[8]::M3 (work@small_top.u1.B1[2].B2[4].B3[8].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[2].B2[4].B3[8]::M3 (work@small_top.u1.B1[2].B2[4].B3[8].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[2].B2[4].B3[8]) |vpiName:N3 @@ -26989,8 +26989,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[2].B2[4].B3[9].k - |vpiModule: - \_module: work@small_top.u1.B1[2].B2[4].B3[9]::M3 (work@small_top.u1.B1[2].B2[4].B3[9].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[2].B2[4].B3[9]::M3 (work@small_top.u1.B1[2].B2[4].B3[9].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[2].B2[4].B3[9]) |vpiName:N3 @@ -27017,8 +27017,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:j |vpiFullName:work@small_top.u1.B1[2].B2[5].j - |vpiModule: - \_module: work@small_top.u1.B1[2].B2[5]::M2 (work@small_top.u1.B1[2].B2[5].N2), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:26:1, endln:26:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[2].B2[5]::M2 (work@small_top.u1.B1[2].B2[5].N2), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:26:1, endln:26:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[2].B2[5]) |vpiName:N2 @@ -27045,8 +27045,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[2].B2[5].B3[0].k - |vpiModule: - \_module: work@small_top.u1.B1[2].B2[5].B3[0]::M3 (work@small_top.u1.B1[2].B2[5].B3[0].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[2].B2[5].B3[0]::M3 (work@small_top.u1.B1[2].B2[5].B3[0].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[2].B2[5].B3[0]) |vpiName:N3 @@ -27073,8 +27073,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[2].B2[5].B3[1].k - |vpiModule: - \_module: work@small_top.u1.B1[2].B2[5].B3[1]::M3 (work@small_top.u1.B1[2].B2[5].B3[1].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[2].B2[5].B3[1]::M3 (work@small_top.u1.B1[2].B2[5].B3[1].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[2].B2[5].B3[1]) |vpiName:N3 @@ -27101,8 +27101,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[2].B2[5].B3[2].k - |vpiModule: - \_module: work@small_top.u1.B1[2].B2[5].B3[2]::M3 (work@small_top.u1.B1[2].B2[5].B3[2].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[2].B2[5].B3[2]::M3 (work@small_top.u1.B1[2].B2[5].B3[2].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[2].B2[5].B3[2]) |vpiName:N3 @@ -27129,8 +27129,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[2].B2[5].B3[3].k - |vpiModule: - \_module: work@small_top.u1.B1[2].B2[5].B3[3]::M3 (work@small_top.u1.B1[2].B2[5].B3[3].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[2].B2[5].B3[3]::M3 (work@small_top.u1.B1[2].B2[5].B3[3].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[2].B2[5].B3[3]) |vpiName:N3 @@ -27157,8 +27157,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[2].B2[5].B3[4].k - |vpiModule: - \_module: work@small_top.u1.B1[2].B2[5].B3[4]::M3 (work@small_top.u1.B1[2].B2[5].B3[4].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[2].B2[5].B3[4]::M3 (work@small_top.u1.B1[2].B2[5].B3[4].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[2].B2[5].B3[4]) |vpiName:N3 @@ -27185,8 +27185,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[2].B2[5].B3[5].k - |vpiModule: - \_module: work@small_top.u1.B1[2].B2[5].B3[5]::M3 (work@small_top.u1.B1[2].B2[5].B3[5].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[2].B2[5].B3[5]::M3 (work@small_top.u1.B1[2].B2[5].B3[5].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[2].B2[5].B3[5]) |vpiName:N3 @@ -27213,8 +27213,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[2].B2[5].B3[6].k - |vpiModule: - \_module: work@small_top.u1.B1[2].B2[5].B3[6]::M3 (work@small_top.u1.B1[2].B2[5].B3[6].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[2].B2[5].B3[6]::M3 (work@small_top.u1.B1[2].B2[5].B3[6].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[2].B2[5].B3[6]) |vpiName:N3 @@ -27241,8 +27241,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[2].B2[5].B3[7].k - |vpiModule: - \_module: work@small_top.u1.B1[2].B2[5].B3[7]::M3 (work@small_top.u1.B1[2].B2[5].B3[7].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[2].B2[5].B3[7]::M3 (work@small_top.u1.B1[2].B2[5].B3[7].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[2].B2[5].B3[7]) |vpiName:N3 @@ -27269,8 +27269,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[2].B2[5].B3[8].k - |vpiModule: - \_module: work@small_top.u1.B1[2].B2[5].B3[8]::M3 (work@small_top.u1.B1[2].B2[5].B3[8].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[2].B2[5].B3[8]::M3 (work@small_top.u1.B1[2].B2[5].B3[8].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[2].B2[5].B3[8]) |vpiName:N3 @@ -27297,8 +27297,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[2].B2[5].B3[9].k - |vpiModule: - \_module: work@small_top.u1.B1[2].B2[5].B3[9]::M3 (work@small_top.u1.B1[2].B2[5].B3[9].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[2].B2[5].B3[9]::M3 (work@small_top.u1.B1[2].B2[5].B3[9].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[2].B2[5].B3[9]) |vpiName:N3 @@ -27325,8 +27325,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:j |vpiFullName:work@small_top.u1.B1[2].B2[6].j - |vpiModule: - \_module: work@small_top.u1.B1[2].B2[6]::M2 (work@small_top.u1.B1[2].B2[6].N2), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:26:1, endln:26:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[2].B2[6]::M2 (work@small_top.u1.B1[2].B2[6].N2), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:26:1, endln:26:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[2].B2[6]) |vpiName:N2 @@ -27353,8 +27353,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[2].B2[6].B3[0].k - |vpiModule: - \_module: work@small_top.u1.B1[2].B2[6].B3[0]::M3 (work@small_top.u1.B1[2].B2[6].B3[0].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[2].B2[6].B3[0]::M3 (work@small_top.u1.B1[2].B2[6].B3[0].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[2].B2[6].B3[0]) |vpiName:N3 @@ -27381,8 +27381,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[2].B2[6].B3[1].k - |vpiModule: - \_module: work@small_top.u1.B1[2].B2[6].B3[1]::M3 (work@small_top.u1.B1[2].B2[6].B3[1].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[2].B2[6].B3[1]::M3 (work@small_top.u1.B1[2].B2[6].B3[1].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[2].B2[6].B3[1]) |vpiName:N3 @@ -27409,8 +27409,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[2].B2[6].B3[2].k - |vpiModule: - \_module: work@small_top.u1.B1[2].B2[6].B3[2]::M3 (work@small_top.u1.B1[2].B2[6].B3[2].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[2].B2[6].B3[2]::M3 (work@small_top.u1.B1[2].B2[6].B3[2].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[2].B2[6].B3[2]) |vpiName:N3 @@ -27437,8 +27437,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[2].B2[6].B3[3].k - |vpiModule: - \_module: work@small_top.u1.B1[2].B2[6].B3[3]::M3 (work@small_top.u1.B1[2].B2[6].B3[3].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[2].B2[6].B3[3]::M3 (work@small_top.u1.B1[2].B2[6].B3[3].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[2].B2[6].B3[3]) |vpiName:N3 @@ -27465,8 +27465,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[2].B2[6].B3[4].k - |vpiModule: - \_module: work@small_top.u1.B1[2].B2[6].B3[4]::M3 (work@small_top.u1.B1[2].B2[6].B3[4].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[2].B2[6].B3[4]::M3 (work@small_top.u1.B1[2].B2[6].B3[4].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[2].B2[6].B3[4]) |vpiName:N3 @@ -27493,8 +27493,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[2].B2[6].B3[5].k - |vpiModule: - \_module: work@small_top.u1.B1[2].B2[6].B3[5]::M3 (work@small_top.u1.B1[2].B2[6].B3[5].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[2].B2[6].B3[5]::M3 (work@small_top.u1.B1[2].B2[6].B3[5].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[2].B2[6].B3[5]) |vpiName:N3 @@ -27521,8 +27521,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[2].B2[6].B3[6].k - |vpiModule: - \_module: work@small_top.u1.B1[2].B2[6].B3[6]::M3 (work@small_top.u1.B1[2].B2[6].B3[6].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[2].B2[6].B3[6]::M3 (work@small_top.u1.B1[2].B2[6].B3[6].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[2].B2[6].B3[6]) |vpiName:N3 @@ -27549,8 +27549,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[2].B2[6].B3[7].k - |vpiModule: - \_module: work@small_top.u1.B1[2].B2[6].B3[7]::M3 (work@small_top.u1.B1[2].B2[6].B3[7].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[2].B2[6].B3[7]::M3 (work@small_top.u1.B1[2].B2[6].B3[7].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[2].B2[6].B3[7]) |vpiName:N3 @@ -27577,8 +27577,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[2].B2[6].B3[8].k - |vpiModule: - \_module: work@small_top.u1.B1[2].B2[6].B3[8]::M3 (work@small_top.u1.B1[2].B2[6].B3[8].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[2].B2[6].B3[8]::M3 (work@small_top.u1.B1[2].B2[6].B3[8].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[2].B2[6].B3[8]) |vpiName:N3 @@ -27605,8 +27605,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[2].B2[6].B3[9].k - |vpiModule: - \_module: work@small_top.u1.B1[2].B2[6].B3[9]::M3 (work@small_top.u1.B1[2].B2[6].B3[9].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[2].B2[6].B3[9]::M3 (work@small_top.u1.B1[2].B2[6].B3[9].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[2].B2[6].B3[9]) |vpiName:N3 @@ -27633,8 +27633,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:j |vpiFullName:work@small_top.u1.B1[2].B2[7].j - |vpiModule: - \_module: work@small_top.u1.B1[2].B2[7]::M2 (work@small_top.u1.B1[2].B2[7].N2), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:26:1, endln:26:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[2].B2[7]::M2 (work@small_top.u1.B1[2].B2[7].N2), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:26:1, endln:26:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[2].B2[7]) |vpiName:N2 @@ -27661,8 +27661,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[2].B2[7].B3[0].k - |vpiModule: - \_module: work@small_top.u1.B1[2].B2[7].B3[0]::M3 (work@small_top.u1.B1[2].B2[7].B3[0].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[2].B2[7].B3[0]::M3 (work@small_top.u1.B1[2].B2[7].B3[0].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[2].B2[7].B3[0]) |vpiName:N3 @@ -27689,8 +27689,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[2].B2[7].B3[1].k - |vpiModule: - \_module: work@small_top.u1.B1[2].B2[7].B3[1]::M3 (work@small_top.u1.B1[2].B2[7].B3[1].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[2].B2[7].B3[1]::M3 (work@small_top.u1.B1[2].B2[7].B3[1].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[2].B2[7].B3[1]) |vpiName:N3 @@ -27717,8 +27717,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[2].B2[7].B3[2].k - |vpiModule: - \_module: work@small_top.u1.B1[2].B2[7].B3[2]::M3 (work@small_top.u1.B1[2].B2[7].B3[2].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[2].B2[7].B3[2]::M3 (work@small_top.u1.B1[2].B2[7].B3[2].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[2].B2[7].B3[2]) |vpiName:N3 @@ -27745,8 +27745,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[2].B2[7].B3[3].k - |vpiModule: - \_module: work@small_top.u1.B1[2].B2[7].B3[3]::M3 (work@small_top.u1.B1[2].B2[7].B3[3].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[2].B2[7].B3[3]::M3 (work@small_top.u1.B1[2].B2[7].B3[3].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[2].B2[7].B3[3]) |vpiName:N3 @@ -27773,8 +27773,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[2].B2[7].B3[4].k - |vpiModule: - \_module: work@small_top.u1.B1[2].B2[7].B3[4]::M3 (work@small_top.u1.B1[2].B2[7].B3[4].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[2].B2[7].B3[4]::M3 (work@small_top.u1.B1[2].B2[7].B3[4].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[2].B2[7].B3[4]) |vpiName:N3 @@ -27801,8 +27801,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[2].B2[7].B3[5].k - |vpiModule: - \_module: work@small_top.u1.B1[2].B2[7].B3[5]::M3 (work@small_top.u1.B1[2].B2[7].B3[5].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[2].B2[7].B3[5]::M3 (work@small_top.u1.B1[2].B2[7].B3[5].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[2].B2[7].B3[5]) |vpiName:N3 @@ -27829,8 +27829,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[2].B2[7].B3[6].k - |vpiModule: - \_module: work@small_top.u1.B1[2].B2[7].B3[6]::M3 (work@small_top.u1.B1[2].B2[7].B3[6].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[2].B2[7].B3[6]::M3 (work@small_top.u1.B1[2].B2[7].B3[6].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[2].B2[7].B3[6]) |vpiName:N3 @@ -27857,8 +27857,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[2].B2[7].B3[7].k - |vpiModule: - \_module: work@small_top.u1.B1[2].B2[7].B3[7]::M3 (work@small_top.u1.B1[2].B2[7].B3[7].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[2].B2[7].B3[7]::M3 (work@small_top.u1.B1[2].B2[7].B3[7].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[2].B2[7].B3[7]) |vpiName:N3 @@ -27885,8 +27885,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[2].B2[7].B3[8].k - |vpiModule: - \_module: work@small_top.u1.B1[2].B2[7].B3[8]::M3 (work@small_top.u1.B1[2].B2[7].B3[8].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[2].B2[7].B3[8]::M3 (work@small_top.u1.B1[2].B2[7].B3[8].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[2].B2[7].B3[8]) |vpiName:N3 @@ -27913,8 +27913,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[2].B2[7].B3[9].k - |vpiModule: - \_module: work@small_top.u1.B1[2].B2[7].B3[9]::M3 (work@small_top.u1.B1[2].B2[7].B3[9].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[2].B2[7].B3[9]::M3 (work@small_top.u1.B1[2].B2[7].B3[9].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[2].B2[7].B3[9]) |vpiName:N3 @@ -27941,8 +27941,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:j |vpiFullName:work@small_top.u1.B1[2].B2[8].j - |vpiModule: - \_module: work@small_top.u1.B1[2].B2[8]::M2 (work@small_top.u1.B1[2].B2[8].N2), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:26:1, endln:26:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[2].B2[8]::M2 (work@small_top.u1.B1[2].B2[8].N2), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:26:1, endln:26:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[2].B2[8]) |vpiName:N2 @@ -27969,8 +27969,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[2].B2[8].B3[0].k - |vpiModule: - \_module: work@small_top.u1.B1[2].B2[8].B3[0]::M3 (work@small_top.u1.B1[2].B2[8].B3[0].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[2].B2[8].B3[0]::M3 (work@small_top.u1.B1[2].B2[8].B3[0].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[2].B2[8].B3[0]) |vpiName:N3 @@ -27997,8 +27997,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[2].B2[8].B3[1].k - |vpiModule: - \_module: work@small_top.u1.B1[2].B2[8].B3[1]::M3 (work@small_top.u1.B1[2].B2[8].B3[1].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[2].B2[8].B3[1]::M3 (work@small_top.u1.B1[2].B2[8].B3[1].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[2].B2[8].B3[1]) |vpiName:N3 @@ -28025,8 +28025,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[2].B2[8].B3[2].k - |vpiModule: - \_module: work@small_top.u1.B1[2].B2[8].B3[2]::M3 (work@small_top.u1.B1[2].B2[8].B3[2].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[2].B2[8].B3[2]::M3 (work@small_top.u1.B1[2].B2[8].B3[2].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[2].B2[8].B3[2]) |vpiName:N3 @@ -28053,8 +28053,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[2].B2[8].B3[3].k - |vpiModule: - \_module: work@small_top.u1.B1[2].B2[8].B3[3]::M3 (work@small_top.u1.B1[2].B2[8].B3[3].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[2].B2[8].B3[3]::M3 (work@small_top.u1.B1[2].B2[8].B3[3].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[2].B2[8].B3[3]) |vpiName:N3 @@ -28081,8 +28081,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[2].B2[8].B3[4].k - |vpiModule: - \_module: work@small_top.u1.B1[2].B2[8].B3[4]::M3 (work@small_top.u1.B1[2].B2[8].B3[4].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[2].B2[8].B3[4]::M3 (work@small_top.u1.B1[2].B2[8].B3[4].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[2].B2[8].B3[4]) |vpiName:N3 @@ -28109,8 +28109,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[2].B2[8].B3[5].k - |vpiModule: - \_module: work@small_top.u1.B1[2].B2[8].B3[5]::M3 (work@small_top.u1.B1[2].B2[8].B3[5].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[2].B2[8].B3[5]::M3 (work@small_top.u1.B1[2].B2[8].B3[5].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[2].B2[8].B3[5]) |vpiName:N3 @@ -28137,8 +28137,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[2].B2[8].B3[6].k - |vpiModule: - \_module: work@small_top.u1.B1[2].B2[8].B3[6]::M3 (work@small_top.u1.B1[2].B2[8].B3[6].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[2].B2[8].B3[6]::M3 (work@small_top.u1.B1[2].B2[8].B3[6].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[2].B2[8].B3[6]) |vpiName:N3 @@ -28165,8 +28165,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[2].B2[8].B3[7].k - |vpiModule: - \_module: work@small_top.u1.B1[2].B2[8].B3[7]::M3 (work@small_top.u1.B1[2].B2[8].B3[7].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[2].B2[8].B3[7]::M3 (work@small_top.u1.B1[2].B2[8].B3[7].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[2].B2[8].B3[7]) |vpiName:N3 @@ -28193,8 +28193,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[2].B2[8].B3[8].k - |vpiModule: - \_module: work@small_top.u1.B1[2].B2[8].B3[8]::M3 (work@small_top.u1.B1[2].B2[8].B3[8].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[2].B2[8].B3[8]::M3 (work@small_top.u1.B1[2].B2[8].B3[8].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[2].B2[8].B3[8]) |vpiName:N3 @@ -28221,8 +28221,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[2].B2[8].B3[9].k - |vpiModule: - \_module: work@small_top.u1.B1[2].B2[8].B3[9]::M3 (work@small_top.u1.B1[2].B2[8].B3[9].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[2].B2[8].B3[9]::M3 (work@small_top.u1.B1[2].B2[8].B3[9].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[2].B2[8].B3[9]) |vpiName:N3 @@ -28249,8 +28249,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:j |vpiFullName:work@small_top.u1.B1[2].B2[9].j - |vpiModule: - \_module: work@small_top.u1.B1[2].B2[9]::M2 (work@small_top.u1.B1[2].B2[9].N2), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:26:1, endln:26:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[2].B2[9]::M2 (work@small_top.u1.B1[2].B2[9].N2), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:26:1, endln:26:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[2].B2[9]) |vpiName:N2 @@ -28277,8 +28277,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[2].B2[9].B3[0].k - |vpiModule: - \_module: work@small_top.u1.B1[2].B2[9].B3[0]::M3 (work@small_top.u1.B1[2].B2[9].B3[0].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[2].B2[9].B3[0]::M3 (work@small_top.u1.B1[2].B2[9].B3[0].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[2].B2[9].B3[0]) |vpiName:N3 @@ -28305,8 +28305,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[2].B2[9].B3[1].k - |vpiModule: - \_module: work@small_top.u1.B1[2].B2[9].B3[1]::M3 (work@small_top.u1.B1[2].B2[9].B3[1].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[2].B2[9].B3[1]::M3 (work@small_top.u1.B1[2].B2[9].B3[1].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[2].B2[9].B3[1]) |vpiName:N3 @@ -28333,8 +28333,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[2].B2[9].B3[2].k - |vpiModule: - \_module: work@small_top.u1.B1[2].B2[9].B3[2]::M3 (work@small_top.u1.B1[2].B2[9].B3[2].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[2].B2[9].B3[2]::M3 (work@small_top.u1.B1[2].B2[9].B3[2].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[2].B2[9].B3[2]) |vpiName:N3 @@ -28361,8 +28361,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[2].B2[9].B3[3].k - |vpiModule: - \_module: work@small_top.u1.B1[2].B2[9].B3[3]::M3 (work@small_top.u1.B1[2].B2[9].B3[3].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[2].B2[9].B3[3]::M3 (work@small_top.u1.B1[2].B2[9].B3[3].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[2].B2[9].B3[3]) |vpiName:N3 @@ -28389,8 +28389,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[2].B2[9].B3[4].k - |vpiModule: - \_module: work@small_top.u1.B1[2].B2[9].B3[4]::M3 (work@small_top.u1.B1[2].B2[9].B3[4].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[2].B2[9].B3[4]::M3 (work@small_top.u1.B1[2].B2[9].B3[4].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[2].B2[9].B3[4]) |vpiName:N3 @@ -28417,8 +28417,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[2].B2[9].B3[5].k - |vpiModule: - \_module: work@small_top.u1.B1[2].B2[9].B3[5]::M3 (work@small_top.u1.B1[2].B2[9].B3[5].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[2].B2[9].B3[5]::M3 (work@small_top.u1.B1[2].B2[9].B3[5].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[2].B2[9].B3[5]) |vpiName:N3 @@ -28445,8 +28445,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[2].B2[9].B3[6].k - |vpiModule: - \_module: work@small_top.u1.B1[2].B2[9].B3[6]::M3 (work@small_top.u1.B1[2].B2[9].B3[6].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[2].B2[9].B3[6]::M3 (work@small_top.u1.B1[2].B2[9].B3[6].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[2].B2[9].B3[6]) |vpiName:N3 @@ -28473,8 +28473,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[2].B2[9].B3[7].k - |vpiModule: - \_module: work@small_top.u1.B1[2].B2[9].B3[7]::M3 (work@small_top.u1.B1[2].B2[9].B3[7].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[2].B2[9].B3[7]::M3 (work@small_top.u1.B1[2].B2[9].B3[7].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[2].B2[9].B3[7]) |vpiName:N3 @@ -28501,8 +28501,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[2].B2[9].B3[8].k - |vpiModule: - \_module: work@small_top.u1.B1[2].B2[9].B3[8]::M3 (work@small_top.u1.B1[2].B2[9].B3[8].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[2].B2[9].B3[8]::M3 (work@small_top.u1.B1[2].B2[9].B3[8].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[2].B2[9].B3[8]) |vpiName:N3 @@ -28529,8 +28529,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[2].B2[9].B3[9].k - |vpiModule: - \_module: work@small_top.u1.B1[2].B2[9].B3[9]::M3 (work@small_top.u1.B1[2].B2[9].B3[9].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[2].B2[9].B3[9]::M3 (work@small_top.u1.B1[2].B2[9].B3[9].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[2].B2[9].B3[9]) |vpiName:N3 @@ -28568,8 +28568,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:m |vpiFullName:work@small_top.u1.B1[2].B4.B5[0].m - |vpiModule: - \_module: work@small_top.u1.B1[2].B4.B5[0]::M4 (work@small_top.u1.B1[2].B4.B5[0].N4), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:46:1, endln:46:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[2].B4.B5[0]::M4 (work@small_top.u1.B1[2].B4.B5[0].N4), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:46:1, endln:46:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[2].B4.B5[0]) |vpiName:N4 @@ -28596,8 +28596,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:m |vpiFullName:work@small_top.u1.B1[2].B4.B5[1].m - |vpiModule: - \_module: work@small_top.u1.B1[2].B4.B5[1]::M4 (work@small_top.u1.B1[2].B4.B5[1].N4), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:46:1, endln:46:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[2].B4.B5[1]::M4 (work@small_top.u1.B1[2].B4.B5[1].N4), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:46:1, endln:46:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[2].B4.B5[1]) |vpiName:N4 @@ -28624,8 +28624,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:m |vpiFullName:work@small_top.u1.B1[2].B4.B5[2].m - |vpiModule: - \_module: work@small_top.u1.B1[2].B4.B5[2]::M4 (work@small_top.u1.B1[2].B4.B5[2].N4), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:46:1, endln:46:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[2].B4.B5[2]::M4 (work@small_top.u1.B1[2].B4.B5[2].N4), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:46:1, endln:46:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[2].B4.B5[2]) |vpiName:N4 @@ -28652,8 +28652,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:m |vpiFullName:work@small_top.u1.B1[2].B4.B5[3].m - |vpiModule: - \_module: work@small_top.u1.B1[2].B4.B5[3]::M4 (work@small_top.u1.B1[2].B4.B5[3].N4), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:46:1, endln:46:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[2].B4.B5[3]::M4 (work@small_top.u1.B1[2].B4.B5[3].N4), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:46:1, endln:46:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[2].B4.B5[3]) |vpiName:N4 @@ -28680,8 +28680,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:m |vpiFullName:work@small_top.u1.B1[2].B4.B5[4].m - |vpiModule: - \_module: work@small_top.u1.B1[2].B4.B5[4]::M4 (work@small_top.u1.B1[2].B4.B5[4].N4), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:46:1, endln:46:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[2].B4.B5[4]::M4 (work@small_top.u1.B1[2].B4.B5[4].N4), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:46:1, endln:46:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[2].B4.B5[4]) |vpiName:N4 @@ -28708,8 +28708,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:m |vpiFullName:work@small_top.u1.B1[2].B4.B5[5].m - |vpiModule: - \_module: work@small_top.u1.B1[2].B4.B5[5]::M4 (work@small_top.u1.B1[2].B4.B5[5].N4), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:46:1, endln:46:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[2].B4.B5[5]::M4 (work@small_top.u1.B1[2].B4.B5[5].N4), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:46:1, endln:46:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[2].B4.B5[5]) |vpiName:N4 @@ -28736,8 +28736,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:m |vpiFullName:work@small_top.u1.B1[2].B4.B5[6].m - |vpiModule: - \_module: work@small_top.u1.B1[2].B4.B5[6]::M4 (work@small_top.u1.B1[2].B4.B5[6].N4), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:46:1, endln:46:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[2].B4.B5[6]::M4 (work@small_top.u1.B1[2].B4.B5[6].N4), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:46:1, endln:46:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[2].B4.B5[6]) |vpiName:N4 @@ -28764,8 +28764,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:m |vpiFullName:work@small_top.u1.B1[2].B4.B5[7].m - |vpiModule: - \_module: work@small_top.u1.B1[2].B4.B5[7]::M4 (work@small_top.u1.B1[2].B4.B5[7].N4), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:46:1, endln:46:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[2].B4.B5[7]::M4 (work@small_top.u1.B1[2].B4.B5[7].N4), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:46:1, endln:46:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[2].B4.B5[7]) |vpiName:N4 @@ -28792,8 +28792,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:m |vpiFullName:work@small_top.u1.B1[2].B4.B5[8].m - |vpiModule: - \_module: work@small_top.u1.B1[2].B4.B5[8]::M4 (work@small_top.u1.B1[2].B4.B5[8].N4), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:46:1, endln:46:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[2].B4.B5[8]::M4 (work@small_top.u1.B1[2].B4.B5[8].N4), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:46:1, endln:46:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[2].B4.B5[8]) |vpiName:N4 @@ -28820,8 +28820,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:m |vpiFullName:work@small_top.u1.B1[2].B4.B5[9].m - |vpiModule: - \_module: work@small_top.u1.B1[2].B4.B5[9]::M4 (work@small_top.u1.B1[2].B4.B5[9].N4), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:46:1, endln:46:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[2].B4.B5[9]::M4 (work@small_top.u1.B1[2].B4.B5[9].N4), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:46:1, endln:46:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[2].B4.B5[9]) |vpiName:N4 @@ -28830,7 +28830,7 @@ design: (work@bottom1) |vpiGenScopeArray: \_gen_scope_array: (work@small_top.u1.B1[3]), line:17:1, endln:51:4 |vpiParent: - \_module: work@small_test (work@small_top.u1), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:2:4, endln:2:29 + \_module_inst: work@small_test (work@small_top.u1), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:2:4, endln:2:29 |vpiName:B1[3] |vpiFullName:work@small_top.u1.B1[3] |vpiGenScope: @@ -28848,8 +28848,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:i |vpiFullName:work@small_top.u1.B1[3].i - |vpiModule: - \_module: work@small_top.u1.B1[3]::M1 (work@small_top.u1.B1[3].N1), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:20:1, endln:20:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[3]::M1 (work@small_top.u1.B1[3].N1), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:20:1, endln:20:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[3]) |vpiName:N1 @@ -28876,8 +28876,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:j |vpiFullName:work@small_top.u1.B1[3].B2[0].j - |vpiModule: - \_module: work@small_top.u1.B1[3].B2[0]::M2 (work@small_top.u1.B1[3].B2[0].N2), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:26:1, endln:26:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[3].B2[0]::M2 (work@small_top.u1.B1[3].B2[0].N2), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:26:1, endln:26:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[3].B2[0]) |vpiName:N2 @@ -28904,8 +28904,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[3].B2[0].B3[0].k - |vpiModule: - \_module: work@small_top.u1.B1[3].B2[0].B3[0]::M3 (work@small_top.u1.B1[3].B2[0].B3[0].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[3].B2[0].B3[0]::M3 (work@small_top.u1.B1[3].B2[0].B3[0].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[3].B2[0].B3[0]) |vpiName:N3 @@ -28932,8 +28932,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[3].B2[0].B3[1].k - |vpiModule: - \_module: work@small_top.u1.B1[3].B2[0].B3[1]::M3 (work@small_top.u1.B1[3].B2[0].B3[1].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[3].B2[0].B3[1]::M3 (work@small_top.u1.B1[3].B2[0].B3[1].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[3].B2[0].B3[1]) |vpiName:N3 @@ -28960,8 +28960,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[3].B2[0].B3[2].k - |vpiModule: - \_module: work@small_top.u1.B1[3].B2[0].B3[2]::M3 (work@small_top.u1.B1[3].B2[0].B3[2].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[3].B2[0].B3[2]::M3 (work@small_top.u1.B1[3].B2[0].B3[2].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[3].B2[0].B3[2]) |vpiName:N3 @@ -28988,8 +28988,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[3].B2[0].B3[3].k - |vpiModule: - \_module: work@small_top.u1.B1[3].B2[0].B3[3]::M3 (work@small_top.u1.B1[3].B2[0].B3[3].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[3].B2[0].B3[3]::M3 (work@small_top.u1.B1[3].B2[0].B3[3].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[3].B2[0].B3[3]) |vpiName:N3 @@ -29016,8 +29016,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[3].B2[0].B3[4].k - |vpiModule: - \_module: work@small_top.u1.B1[3].B2[0].B3[4]::M3 (work@small_top.u1.B1[3].B2[0].B3[4].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[3].B2[0].B3[4]::M3 (work@small_top.u1.B1[3].B2[0].B3[4].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[3].B2[0].B3[4]) |vpiName:N3 @@ -29044,8 +29044,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[3].B2[0].B3[5].k - |vpiModule: - \_module: work@small_top.u1.B1[3].B2[0].B3[5]::M3 (work@small_top.u1.B1[3].B2[0].B3[5].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[3].B2[0].B3[5]::M3 (work@small_top.u1.B1[3].B2[0].B3[5].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[3].B2[0].B3[5]) |vpiName:N3 @@ -29072,8 +29072,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[3].B2[0].B3[6].k - |vpiModule: - \_module: work@small_top.u1.B1[3].B2[0].B3[6]::M3 (work@small_top.u1.B1[3].B2[0].B3[6].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[3].B2[0].B3[6]::M3 (work@small_top.u1.B1[3].B2[0].B3[6].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[3].B2[0].B3[6]) |vpiName:N3 @@ -29100,8 +29100,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[3].B2[0].B3[7].k - |vpiModule: - \_module: work@small_top.u1.B1[3].B2[0].B3[7]::M3 (work@small_top.u1.B1[3].B2[0].B3[7].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[3].B2[0].B3[7]::M3 (work@small_top.u1.B1[3].B2[0].B3[7].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[3].B2[0].B3[7]) |vpiName:N3 @@ -29128,8 +29128,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[3].B2[0].B3[8].k - |vpiModule: - \_module: work@small_top.u1.B1[3].B2[0].B3[8]::M3 (work@small_top.u1.B1[3].B2[0].B3[8].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[3].B2[0].B3[8]::M3 (work@small_top.u1.B1[3].B2[0].B3[8].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[3].B2[0].B3[8]) |vpiName:N3 @@ -29156,8 +29156,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[3].B2[0].B3[9].k - |vpiModule: - \_module: work@small_top.u1.B1[3].B2[0].B3[9]::M3 (work@small_top.u1.B1[3].B2[0].B3[9].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[3].B2[0].B3[9]::M3 (work@small_top.u1.B1[3].B2[0].B3[9].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[3].B2[0].B3[9]) |vpiName:N3 @@ -29184,8 +29184,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:j |vpiFullName:work@small_top.u1.B1[3].B2[1].j - |vpiModule: - \_module: work@small_top.u1.B1[3].B2[1]::M2 (work@small_top.u1.B1[3].B2[1].N2), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:26:1, endln:26:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[3].B2[1]::M2 (work@small_top.u1.B1[3].B2[1].N2), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:26:1, endln:26:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[3].B2[1]) |vpiName:N2 @@ -29212,8 +29212,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[3].B2[1].B3[0].k - |vpiModule: - \_module: work@small_top.u1.B1[3].B2[1].B3[0]::M3 (work@small_top.u1.B1[3].B2[1].B3[0].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[3].B2[1].B3[0]::M3 (work@small_top.u1.B1[3].B2[1].B3[0].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[3].B2[1].B3[0]) |vpiName:N3 @@ -29240,8 +29240,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[3].B2[1].B3[1].k - |vpiModule: - \_module: work@small_top.u1.B1[3].B2[1].B3[1]::M3 (work@small_top.u1.B1[3].B2[1].B3[1].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[3].B2[1].B3[1]::M3 (work@small_top.u1.B1[3].B2[1].B3[1].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[3].B2[1].B3[1]) |vpiName:N3 @@ -29268,8 +29268,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[3].B2[1].B3[2].k - |vpiModule: - \_module: work@small_top.u1.B1[3].B2[1].B3[2]::M3 (work@small_top.u1.B1[3].B2[1].B3[2].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[3].B2[1].B3[2]::M3 (work@small_top.u1.B1[3].B2[1].B3[2].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[3].B2[1].B3[2]) |vpiName:N3 @@ -29296,8 +29296,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[3].B2[1].B3[3].k - |vpiModule: - \_module: work@small_top.u1.B1[3].B2[1].B3[3]::M3 (work@small_top.u1.B1[3].B2[1].B3[3].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[3].B2[1].B3[3]::M3 (work@small_top.u1.B1[3].B2[1].B3[3].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[3].B2[1].B3[3]) |vpiName:N3 @@ -29324,8 +29324,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[3].B2[1].B3[4].k - |vpiModule: - \_module: work@small_top.u1.B1[3].B2[1].B3[4]::M3 (work@small_top.u1.B1[3].B2[1].B3[4].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[3].B2[1].B3[4]::M3 (work@small_top.u1.B1[3].B2[1].B3[4].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[3].B2[1].B3[4]) |vpiName:N3 @@ -29352,8 +29352,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[3].B2[1].B3[5].k - |vpiModule: - \_module: work@small_top.u1.B1[3].B2[1].B3[5]::M3 (work@small_top.u1.B1[3].B2[1].B3[5].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[3].B2[1].B3[5]::M3 (work@small_top.u1.B1[3].B2[1].B3[5].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[3].B2[1].B3[5]) |vpiName:N3 @@ -29380,8 +29380,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[3].B2[1].B3[6].k - |vpiModule: - \_module: work@small_top.u1.B1[3].B2[1].B3[6]::M3 (work@small_top.u1.B1[3].B2[1].B3[6].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[3].B2[1].B3[6]::M3 (work@small_top.u1.B1[3].B2[1].B3[6].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[3].B2[1].B3[6]) |vpiName:N3 @@ -29408,8 +29408,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[3].B2[1].B3[7].k - |vpiModule: - \_module: work@small_top.u1.B1[3].B2[1].B3[7]::M3 (work@small_top.u1.B1[3].B2[1].B3[7].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[3].B2[1].B3[7]::M3 (work@small_top.u1.B1[3].B2[1].B3[7].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[3].B2[1].B3[7]) |vpiName:N3 @@ -29436,8 +29436,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[3].B2[1].B3[8].k - |vpiModule: - \_module: work@small_top.u1.B1[3].B2[1].B3[8]::M3 (work@small_top.u1.B1[3].B2[1].B3[8].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[3].B2[1].B3[8]::M3 (work@small_top.u1.B1[3].B2[1].B3[8].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[3].B2[1].B3[8]) |vpiName:N3 @@ -29464,8 +29464,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[3].B2[1].B3[9].k - |vpiModule: - \_module: work@small_top.u1.B1[3].B2[1].B3[9]::M3 (work@small_top.u1.B1[3].B2[1].B3[9].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[3].B2[1].B3[9]::M3 (work@small_top.u1.B1[3].B2[1].B3[9].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[3].B2[1].B3[9]) |vpiName:N3 @@ -29492,8 +29492,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:j |vpiFullName:work@small_top.u1.B1[3].B2[2].j - |vpiModule: - \_module: work@small_top.u1.B1[3].B2[2]::M2 (work@small_top.u1.B1[3].B2[2].N2), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:26:1, endln:26:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[3].B2[2]::M2 (work@small_top.u1.B1[3].B2[2].N2), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:26:1, endln:26:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[3].B2[2]) |vpiName:N2 @@ -29520,8 +29520,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[3].B2[2].B3[0].k - |vpiModule: - \_module: work@small_top.u1.B1[3].B2[2].B3[0]::M3 (work@small_top.u1.B1[3].B2[2].B3[0].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[3].B2[2].B3[0]::M3 (work@small_top.u1.B1[3].B2[2].B3[0].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[3].B2[2].B3[0]) |vpiName:N3 @@ -29548,8 +29548,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[3].B2[2].B3[1].k - |vpiModule: - \_module: work@small_top.u1.B1[3].B2[2].B3[1]::M3 (work@small_top.u1.B1[3].B2[2].B3[1].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[3].B2[2].B3[1]::M3 (work@small_top.u1.B1[3].B2[2].B3[1].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[3].B2[2].B3[1]) |vpiName:N3 @@ -29576,8 +29576,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[3].B2[2].B3[2].k - |vpiModule: - \_module: work@small_top.u1.B1[3].B2[2].B3[2]::M3 (work@small_top.u1.B1[3].B2[2].B3[2].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[3].B2[2].B3[2]::M3 (work@small_top.u1.B1[3].B2[2].B3[2].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[3].B2[2].B3[2]) |vpiName:N3 @@ -29604,8 +29604,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[3].B2[2].B3[3].k - |vpiModule: - \_module: work@small_top.u1.B1[3].B2[2].B3[3]::M3 (work@small_top.u1.B1[3].B2[2].B3[3].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[3].B2[2].B3[3]::M3 (work@small_top.u1.B1[3].B2[2].B3[3].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[3].B2[2].B3[3]) |vpiName:N3 @@ -29632,8 +29632,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[3].B2[2].B3[4].k - |vpiModule: - \_module: work@small_top.u1.B1[3].B2[2].B3[4]::M3 (work@small_top.u1.B1[3].B2[2].B3[4].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[3].B2[2].B3[4]::M3 (work@small_top.u1.B1[3].B2[2].B3[4].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[3].B2[2].B3[4]) |vpiName:N3 @@ -29660,8 +29660,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[3].B2[2].B3[5].k - |vpiModule: - \_module: work@small_top.u1.B1[3].B2[2].B3[5]::M3 (work@small_top.u1.B1[3].B2[2].B3[5].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[3].B2[2].B3[5]::M3 (work@small_top.u1.B1[3].B2[2].B3[5].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[3].B2[2].B3[5]) |vpiName:N3 @@ -29688,8 +29688,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[3].B2[2].B3[6].k - |vpiModule: - \_module: work@small_top.u1.B1[3].B2[2].B3[6]::M3 (work@small_top.u1.B1[3].B2[2].B3[6].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[3].B2[2].B3[6]::M3 (work@small_top.u1.B1[3].B2[2].B3[6].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[3].B2[2].B3[6]) |vpiName:N3 @@ -29716,8 +29716,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[3].B2[2].B3[7].k - |vpiModule: - \_module: work@small_top.u1.B1[3].B2[2].B3[7]::M3 (work@small_top.u1.B1[3].B2[2].B3[7].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[3].B2[2].B3[7]::M3 (work@small_top.u1.B1[3].B2[2].B3[7].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[3].B2[2].B3[7]) |vpiName:N3 @@ -29744,8 +29744,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[3].B2[2].B3[8].k - |vpiModule: - \_module: work@small_top.u1.B1[3].B2[2].B3[8]::M3 (work@small_top.u1.B1[3].B2[2].B3[8].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[3].B2[2].B3[8]::M3 (work@small_top.u1.B1[3].B2[2].B3[8].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[3].B2[2].B3[8]) |vpiName:N3 @@ -29772,8 +29772,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[3].B2[2].B3[9].k - |vpiModule: - \_module: work@small_top.u1.B1[3].B2[2].B3[9]::M3 (work@small_top.u1.B1[3].B2[2].B3[9].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[3].B2[2].B3[9]::M3 (work@small_top.u1.B1[3].B2[2].B3[9].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[3].B2[2].B3[9]) |vpiName:N3 @@ -29800,8 +29800,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:j |vpiFullName:work@small_top.u1.B1[3].B2[3].j - |vpiModule: - \_module: work@small_top.u1.B1[3].B2[3]::M2 (work@small_top.u1.B1[3].B2[3].N2), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:26:1, endln:26:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[3].B2[3]::M2 (work@small_top.u1.B1[3].B2[3].N2), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:26:1, endln:26:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[3].B2[3]) |vpiName:N2 @@ -29828,8 +29828,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[3].B2[3].B3[0].k - |vpiModule: - \_module: work@small_top.u1.B1[3].B2[3].B3[0]::M3 (work@small_top.u1.B1[3].B2[3].B3[0].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[3].B2[3].B3[0]::M3 (work@small_top.u1.B1[3].B2[3].B3[0].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[3].B2[3].B3[0]) |vpiName:N3 @@ -29856,8 +29856,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[3].B2[3].B3[1].k - |vpiModule: - \_module: work@small_top.u1.B1[3].B2[3].B3[1]::M3 (work@small_top.u1.B1[3].B2[3].B3[1].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[3].B2[3].B3[1]::M3 (work@small_top.u1.B1[3].B2[3].B3[1].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[3].B2[3].B3[1]) |vpiName:N3 @@ -29884,8 +29884,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[3].B2[3].B3[2].k - |vpiModule: - \_module: work@small_top.u1.B1[3].B2[3].B3[2]::M3 (work@small_top.u1.B1[3].B2[3].B3[2].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[3].B2[3].B3[2]::M3 (work@small_top.u1.B1[3].B2[3].B3[2].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[3].B2[3].B3[2]) |vpiName:N3 @@ -29912,8 +29912,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[3].B2[3].B3[3].k - |vpiModule: - \_module: work@small_top.u1.B1[3].B2[3].B3[3]::M3 (work@small_top.u1.B1[3].B2[3].B3[3].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[3].B2[3].B3[3]::M3 (work@small_top.u1.B1[3].B2[3].B3[3].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[3].B2[3].B3[3]) |vpiName:N3 @@ -29940,8 +29940,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[3].B2[3].B3[4].k - |vpiModule: - \_module: work@small_top.u1.B1[3].B2[3].B3[4]::M3 (work@small_top.u1.B1[3].B2[3].B3[4].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[3].B2[3].B3[4]::M3 (work@small_top.u1.B1[3].B2[3].B3[4].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[3].B2[3].B3[4]) |vpiName:N3 @@ -29968,8 +29968,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[3].B2[3].B3[5].k - |vpiModule: - \_module: work@small_top.u1.B1[3].B2[3].B3[5]::M3 (work@small_top.u1.B1[3].B2[3].B3[5].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[3].B2[3].B3[5]::M3 (work@small_top.u1.B1[3].B2[3].B3[5].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[3].B2[3].B3[5]) |vpiName:N3 @@ -29996,8 +29996,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[3].B2[3].B3[6].k - |vpiModule: - \_module: work@small_top.u1.B1[3].B2[3].B3[6]::M3 (work@small_top.u1.B1[3].B2[3].B3[6].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[3].B2[3].B3[6]::M3 (work@small_top.u1.B1[3].B2[3].B3[6].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[3].B2[3].B3[6]) |vpiName:N3 @@ -30024,8 +30024,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[3].B2[3].B3[7].k - |vpiModule: - \_module: work@small_top.u1.B1[3].B2[3].B3[7]::M3 (work@small_top.u1.B1[3].B2[3].B3[7].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[3].B2[3].B3[7]::M3 (work@small_top.u1.B1[3].B2[3].B3[7].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[3].B2[3].B3[7]) |vpiName:N3 @@ -30052,8 +30052,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[3].B2[3].B3[8].k - |vpiModule: - \_module: work@small_top.u1.B1[3].B2[3].B3[8]::M3 (work@small_top.u1.B1[3].B2[3].B3[8].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[3].B2[3].B3[8]::M3 (work@small_top.u1.B1[3].B2[3].B3[8].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[3].B2[3].B3[8]) |vpiName:N3 @@ -30080,8 +30080,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[3].B2[3].B3[9].k - |vpiModule: - \_module: work@small_top.u1.B1[3].B2[3].B3[9]::M3 (work@small_top.u1.B1[3].B2[3].B3[9].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[3].B2[3].B3[9]::M3 (work@small_top.u1.B1[3].B2[3].B3[9].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[3].B2[3].B3[9]) |vpiName:N3 @@ -30108,8 +30108,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:j |vpiFullName:work@small_top.u1.B1[3].B2[4].j - |vpiModule: - \_module: work@small_top.u1.B1[3].B2[4]::M2 (work@small_top.u1.B1[3].B2[4].N2), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:26:1, endln:26:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[3].B2[4]::M2 (work@small_top.u1.B1[3].B2[4].N2), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:26:1, endln:26:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[3].B2[4]) |vpiName:N2 @@ -30136,8 +30136,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[3].B2[4].B3[0].k - |vpiModule: - \_module: work@small_top.u1.B1[3].B2[4].B3[0]::M3 (work@small_top.u1.B1[3].B2[4].B3[0].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[3].B2[4].B3[0]::M3 (work@small_top.u1.B1[3].B2[4].B3[0].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[3].B2[4].B3[0]) |vpiName:N3 @@ -30164,8 +30164,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[3].B2[4].B3[1].k - |vpiModule: - \_module: work@small_top.u1.B1[3].B2[4].B3[1]::M3 (work@small_top.u1.B1[3].B2[4].B3[1].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[3].B2[4].B3[1]::M3 (work@small_top.u1.B1[3].B2[4].B3[1].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[3].B2[4].B3[1]) |vpiName:N3 @@ -30192,8 +30192,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[3].B2[4].B3[2].k - |vpiModule: - \_module: work@small_top.u1.B1[3].B2[4].B3[2]::M3 (work@small_top.u1.B1[3].B2[4].B3[2].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[3].B2[4].B3[2]::M3 (work@small_top.u1.B1[3].B2[4].B3[2].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[3].B2[4].B3[2]) |vpiName:N3 @@ -30220,8 +30220,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[3].B2[4].B3[3].k - |vpiModule: - \_module: work@small_top.u1.B1[3].B2[4].B3[3]::M3 (work@small_top.u1.B1[3].B2[4].B3[3].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[3].B2[4].B3[3]::M3 (work@small_top.u1.B1[3].B2[4].B3[3].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[3].B2[4].B3[3]) |vpiName:N3 @@ -30248,8 +30248,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[3].B2[4].B3[4].k - |vpiModule: - \_module: work@small_top.u1.B1[3].B2[4].B3[4]::M3 (work@small_top.u1.B1[3].B2[4].B3[4].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[3].B2[4].B3[4]::M3 (work@small_top.u1.B1[3].B2[4].B3[4].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[3].B2[4].B3[4]) |vpiName:N3 @@ -30276,8 +30276,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[3].B2[4].B3[5].k - |vpiModule: - \_module: work@small_top.u1.B1[3].B2[4].B3[5]::M3 (work@small_top.u1.B1[3].B2[4].B3[5].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[3].B2[4].B3[5]::M3 (work@small_top.u1.B1[3].B2[4].B3[5].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[3].B2[4].B3[5]) |vpiName:N3 @@ -30304,8 +30304,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[3].B2[4].B3[6].k - |vpiModule: - \_module: work@small_top.u1.B1[3].B2[4].B3[6]::M3 (work@small_top.u1.B1[3].B2[4].B3[6].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[3].B2[4].B3[6]::M3 (work@small_top.u1.B1[3].B2[4].B3[6].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[3].B2[4].B3[6]) |vpiName:N3 @@ -30332,8 +30332,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[3].B2[4].B3[7].k - |vpiModule: - \_module: work@small_top.u1.B1[3].B2[4].B3[7]::M3 (work@small_top.u1.B1[3].B2[4].B3[7].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[3].B2[4].B3[7]::M3 (work@small_top.u1.B1[3].B2[4].B3[7].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[3].B2[4].B3[7]) |vpiName:N3 @@ -30360,8 +30360,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[3].B2[4].B3[8].k - |vpiModule: - \_module: work@small_top.u1.B1[3].B2[4].B3[8]::M3 (work@small_top.u1.B1[3].B2[4].B3[8].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[3].B2[4].B3[8]::M3 (work@small_top.u1.B1[3].B2[4].B3[8].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[3].B2[4].B3[8]) |vpiName:N3 @@ -30388,8 +30388,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[3].B2[4].B3[9].k - |vpiModule: - \_module: work@small_top.u1.B1[3].B2[4].B3[9]::M3 (work@small_top.u1.B1[3].B2[4].B3[9].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[3].B2[4].B3[9]::M3 (work@small_top.u1.B1[3].B2[4].B3[9].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[3].B2[4].B3[9]) |vpiName:N3 @@ -30416,8 +30416,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:j |vpiFullName:work@small_top.u1.B1[3].B2[5].j - |vpiModule: - \_module: work@small_top.u1.B1[3].B2[5]::M2 (work@small_top.u1.B1[3].B2[5].N2), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:26:1, endln:26:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[3].B2[5]::M2 (work@small_top.u1.B1[3].B2[5].N2), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:26:1, endln:26:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[3].B2[5]) |vpiName:N2 @@ -30444,8 +30444,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[3].B2[5].B3[0].k - |vpiModule: - \_module: work@small_top.u1.B1[3].B2[5].B3[0]::M3 (work@small_top.u1.B1[3].B2[5].B3[0].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[3].B2[5].B3[0]::M3 (work@small_top.u1.B1[3].B2[5].B3[0].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[3].B2[5].B3[0]) |vpiName:N3 @@ -30472,8 +30472,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[3].B2[5].B3[1].k - |vpiModule: - \_module: work@small_top.u1.B1[3].B2[5].B3[1]::M3 (work@small_top.u1.B1[3].B2[5].B3[1].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[3].B2[5].B3[1]::M3 (work@small_top.u1.B1[3].B2[5].B3[1].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[3].B2[5].B3[1]) |vpiName:N3 @@ -30500,8 +30500,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[3].B2[5].B3[2].k - |vpiModule: - \_module: work@small_top.u1.B1[3].B2[5].B3[2]::M3 (work@small_top.u1.B1[3].B2[5].B3[2].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[3].B2[5].B3[2]::M3 (work@small_top.u1.B1[3].B2[5].B3[2].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[3].B2[5].B3[2]) |vpiName:N3 @@ -30528,8 +30528,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[3].B2[5].B3[3].k - |vpiModule: - \_module: work@small_top.u1.B1[3].B2[5].B3[3]::M3 (work@small_top.u1.B1[3].B2[5].B3[3].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[3].B2[5].B3[3]::M3 (work@small_top.u1.B1[3].B2[5].B3[3].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[3].B2[5].B3[3]) |vpiName:N3 @@ -30556,8 +30556,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[3].B2[5].B3[4].k - |vpiModule: - \_module: work@small_top.u1.B1[3].B2[5].B3[4]::M3 (work@small_top.u1.B1[3].B2[5].B3[4].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[3].B2[5].B3[4]::M3 (work@small_top.u1.B1[3].B2[5].B3[4].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[3].B2[5].B3[4]) |vpiName:N3 @@ -30584,8 +30584,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[3].B2[5].B3[5].k - |vpiModule: - \_module: work@small_top.u1.B1[3].B2[5].B3[5]::M3 (work@small_top.u1.B1[3].B2[5].B3[5].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[3].B2[5].B3[5]::M3 (work@small_top.u1.B1[3].B2[5].B3[5].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[3].B2[5].B3[5]) |vpiName:N3 @@ -30612,8 +30612,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[3].B2[5].B3[6].k - |vpiModule: - \_module: work@small_top.u1.B1[3].B2[5].B3[6]::M3 (work@small_top.u1.B1[3].B2[5].B3[6].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[3].B2[5].B3[6]::M3 (work@small_top.u1.B1[3].B2[5].B3[6].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[3].B2[5].B3[6]) |vpiName:N3 @@ -30640,8 +30640,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[3].B2[5].B3[7].k - |vpiModule: - \_module: work@small_top.u1.B1[3].B2[5].B3[7]::M3 (work@small_top.u1.B1[3].B2[5].B3[7].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[3].B2[5].B3[7]::M3 (work@small_top.u1.B1[3].B2[5].B3[7].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[3].B2[5].B3[7]) |vpiName:N3 @@ -30668,8 +30668,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[3].B2[5].B3[8].k - |vpiModule: - \_module: work@small_top.u1.B1[3].B2[5].B3[8]::M3 (work@small_top.u1.B1[3].B2[5].B3[8].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[3].B2[5].B3[8]::M3 (work@small_top.u1.B1[3].B2[5].B3[8].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[3].B2[5].B3[8]) |vpiName:N3 @@ -30696,8 +30696,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[3].B2[5].B3[9].k - |vpiModule: - \_module: work@small_top.u1.B1[3].B2[5].B3[9]::M3 (work@small_top.u1.B1[3].B2[5].B3[9].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[3].B2[5].B3[9]::M3 (work@small_top.u1.B1[3].B2[5].B3[9].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[3].B2[5].B3[9]) |vpiName:N3 @@ -30724,8 +30724,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:j |vpiFullName:work@small_top.u1.B1[3].B2[6].j - |vpiModule: - \_module: work@small_top.u1.B1[3].B2[6]::M2 (work@small_top.u1.B1[3].B2[6].N2), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:26:1, endln:26:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[3].B2[6]::M2 (work@small_top.u1.B1[3].B2[6].N2), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:26:1, endln:26:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[3].B2[6]) |vpiName:N2 @@ -30752,8 +30752,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[3].B2[6].B3[0].k - |vpiModule: - \_module: work@small_top.u1.B1[3].B2[6].B3[0]::M3 (work@small_top.u1.B1[3].B2[6].B3[0].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[3].B2[6].B3[0]::M3 (work@small_top.u1.B1[3].B2[6].B3[0].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[3].B2[6].B3[0]) |vpiName:N3 @@ -30780,8 +30780,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[3].B2[6].B3[1].k - |vpiModule: - \_module: work@small_top.u1.B1[3].B2[6].B3[1]::M3 (work@small_top.u1.B1[3].B2[6].B3[1].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[3].B2[6].B3[1]::M3 (work@small_top.u1.B1[3].B2[6].B3[1].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[3].B2[6].B3[1]) |vpiName:N3 @@ -30808,8 +30808,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[3].B2[6].B3[2].k - |vpiModule: - \_module: work@small_top.u1.B1[3].B2[6].B3[2]::M3 (work@small_top.u1.B1[3].B2[6].B3[2].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[3].B2[6].B3[2]::M3 (work@small_top.u1.B1[3].B2[6].B3[2].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[3].B2[6].B3[2]) |vpiName:N3 @@ -30836,8 +30836,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[3].B2[6].B3[3].k - |vpiModule: - \_module: work@small_top.u1.B1[3].B2[6].B3[3]::M3 (work@small_top.u1.B1[3].B2[6].B3[3].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[3].B2[6].B3[3]::M3 (work@small_top.u1.B1[3].B2[6].B3[3].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[3].B2[6].B3[3]) |vpiName:N3 @@ -30864,8 +30864,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[3].B2[6].B3[4].k - |vpiModule: - \_module: work@small_top.u1.B1[3].B2[6].B3[4]::M3 (work@small_top.u1.B1[3].B2[6].B3[4].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[3].B2[6].B3[4]::M3 (work@small_top.u1.B1[3].B2[6].B3[4].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[3].B2[6].B3[4]) |vpiName:N3 @@ -30892,8 +30892,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[3].B2[6].B3[5].k - |vpiModule: - \_module: work@small_top.u1.B1[3].B2[6].B3[5]::M3 (work@small_top.u1.B1[3].B2[6].B3[5].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[3].B2[6].B3[5]::M3 (work@small_top.u1.B1[3].B2[6].B3[5].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[3].B2[6].B3[5]) |vpiName:N3 @@ -30920,8 +30920,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[3].B2[6].B3[6].k - |vpiModule: - \_module: work@small_top.u1.B1[3].B2[6].B3[6]::M3 (work@small_top.u1.B1[3].B2[6].B3[6].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[3].B2[6].B3[6]::M3 (work@small_top.u1.B1[3].B2[6].B3[6].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[3].B2[6].B3[6]) |vpiName:N3 @@ -30948,8 +30948,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[3].B2[6].B3[7].k - |vpiModule: - \_module: work@small_top.u1.B1[3].B2[6].B3[7]::M3 (work@small_top.u1.B1[3].B2[6].B3[7].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[3].B2[6].B3[7]::M3 (work@small_top.u1.B1[3].B2[6].B3[7].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[3].B2[6].B3[7]) |vpiName:N3 @@ -30976,8 +30976,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[3].B2[6].B3[8].k - |vpiModule: - \_module: work@small_top.u1.B1[3].B2[6].B3[8]::M3 (work@small_top.u1.B1[3].B2[6].B3[8].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[3].B2[6].B3[8]::M3 (work@small_top.u1.B1[3].B2[6].B3[8].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[3].B2[6].B3[8]) |vpiName:N3 @@ -31004,8 +31004,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[3].B2[6].B3[9].k - |vpiModule: - \_module: work@small_top.u1.B1[3].B2[6].B3[9]::M3 (work@small_top.u1.B1[3].B2[6].B3[9].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[3].B2[6].B3[9]::M3 (work@small_top.u1.B1[3].B2[6].B3[9].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[3].B2[6].B3[9]) |vpiName:N3 @@ -31032,8 +31032,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:j |vpiFullName:work@small_top.u1.B1[3].B2[7].j - |vpiModule: - \_module: work@small_top.u1.B1[3].B2[7]::M2 (work@small_top.u1.B1[3].B2[7].N2), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:26:1, endln:26:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[3].B2[7]::M2 (work@small_top.u1.B1[3].B2[7].N2), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:26:1, endln:26:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[3].B2[7]) |vpiName:N2 @@ -31060,8 +31060,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[3].B2[7].B3[0].k - |vpiModule: - \_module: work@small_top.u1.B1[3].B2[7].B3[0]::M3 (work@small_top.u1.B1[3].B2[7].B3[0].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[3].B2[7].B3[0]::M3 (work@small_top.u1.B1[3].B2[7].B3[0].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[3].B2[7].B3[0]) |vpiName:N3 @@ -31088,8 +31088,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[3].B2[7].B3[1].k - |vpiModule: - \_module: work@small_top.u1.B1[3].B2[7].B3[1]::M3 (work@small_top.u1.B1[3].B2[7].B3[1].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[3].B2[7].B3[1]::M3 (work@small_top.u1.B1[3].B2[7].B3[1].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[3].B2[7].B3[1]) |vpiName:N3 @@ -31116,8 +31116,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[3].B2[7].B3[2].k - |vpiModule: - \_module: work@small_top.u1.B1[3].B2[7].B3[2]::M3 (work@small_top.u1.B1[3].B2[7].B3[2].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[3].B2[7].B3[2]::M3 (work@small_top.u1.B1[3].B2[7].B3[2].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[3].B2[7].B3[2]) |vpiName:N3 @@ -31144,8 +31144,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[3].B2[7].B3[3].k - |vpiModule: - \_module: work@small_top.u1.B1[3].B2[7].B3[3]::M3 (work@small_top.u1.B1[3].B2[7].B3[3].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[3].B2[7].B3[3]::M3 (work@small_top.u1.B1[3].B2[7].B3[3].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[3].B2[7].B3[3]) |vpiName:N3 @@ -31172,8 +31172,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[3].B2[7].B3[4].k - |vpiModule: - \_module: work@small_top.u1.B1[3].B2[7].B3[4]::M3 (work@small_top.u1.B1[3].B2[7].B3[4].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[3].B2[7].B3[4]::M3 (work@small_top.u1.B1[3].B2[7].B3[4].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[3].B2[7].B3[4]) |vpiName:N3 @@ -31200,8 +31200,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[3].B2[7].B3[5].k - |vpiModule: - \_module: work@small_top.u1.B1[3].B2[7].B3[5]::M3 (work@small_top.u1.B1[3].B2[7].B3[5].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[3].B2[7].B3[5]::M3 (work@small_top.u1.B1[3].B2[7].B3[5].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[3].B2[7].B3[5]) |vpiName:N3 @@ -31228,8 +31228,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[3].B2[7].B3[6].k - |vpiModule: - \_module: work@small_top.u1.B1[3].B2[7].B3[6]::M3 (work@small_top.u1.B1[3].B2[7].B3[6].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[3].B2[7].B3[6]::M3 (work@small_top.u1.B1[3].B2[7].B3[6].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[3].B2[7].B3[6]) |vpiName:N3 @@ -31256,8 +31256,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[3].B2[7].B3[7].k - |vpiModule: - \_module: work@small_top.u1.B1[3].B2[7].B3[7]::M3 (work@small_top.u1.B1[3].B2[7].B3[7].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[3].B2[7].B3[7]::M3 (work@small_top.u1.B1[3].B2[7].B3[7].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[3].B2[7].B3[7]) |vpiName:N3 @@ -31284,8 +31284,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[3].B2[7].B3[8].k - |vpiModule: - \_module: work@small_top.u1.B1[3].B2[7].B3[8]::M3 (work@small_top.u1.B1[3].B2[7].B3[8].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[3].B2[7].B3[8]::M3 (work@small_top.u1.B1[3].B2[7].B3[8].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[3].B2[7].B3[8]) |vpiName:N3 @@ -31312,8 +31312,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[3].B2[7].B3[9].k - |vpiModule: - \_module: work@small_top.u1.B1[3].B2[7].B3[9]::M3 (work@small_top.u1.B1[3].B2[7].B3[9].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[3].B2[7].B3[9]::M3 (work@small_top.u1.B1[3].B2[7].B3[9].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[3].B2[7].B3[9]) |vpiName:N3 @@ -31340,8 +31340,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:j |vpiFullName:work@small_top.u1.B1[3].B2[8].j - |vpiModule: - \_module: work@small_top.u1.B1[3].B2[8]::M2 (work@small_top.u1.B1[3].B2[8].N2), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:26:1, endln:26:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[3].B2[8]::M2 (work@small_top.u1.B1[3].B2[8].N2), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:26:1, endln:26:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[3].B2[8]) |vpiName:N2 @@ -31368,8 +31368,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[3].B2[8].B3[0].k - |vpiModule: - \_module: work@small_top.u1.B1[3].B2[8].B3[0]::M3 (work@small_top.u1.B1[3].B2[8].B3[0].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[3].B2[8].B3[0]::M3 (work@small_top.u1.B1[3].B2[8].B3[0].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[3].B2[8].B3[0]) |vpiName:N3 @@ -31396,8 +31396,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[3].B2[8].B3[1].k - |vpiModule: - \_module: work@small_top.u1.B1[3].B2[8].B3[1]::M3 (work@small_top.u1.B1[3].B2[8].B3[1].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[3].B2[8].B3[1]::M3 (work@small_top.u1.B1[3].B2[8].B3[1].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[3].B2[8].B3[1]) |vpiName:N3 @@ -31424,8 +31424,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[3].B2[8].B3[2].k - |vpiModule: - \_module: work@small_top.u1.B1[3].B2[8].B3[2]::M3 (work@small_top.u1.B1[3].B2[8].B3[2].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[3].B2[8].B3[2]::M3 (work@small_top.u1.B1[3].B2[8].B3[2].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[3].B2[8].B3[2]) |vpiName:N3 @@ -31452,8 +31452,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[3].B2[8].B3[3].k - |vpiModule: - \_module: work@small_top.u1.B1[3].B2[8].B3[3]::M3 (work@small_top.u1.B1[3].B2[8].B3[3].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[3].B2[8].B3[3]::M3 (work@small_top.u1.B1[3].B2[8].B3[3].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[3].B2[8].B3[3]) |vpiName:N3 @@ -31480,8 +31480,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[3].B2[8].B3[4].k - |vpiModule: - \_module: work@small_top.u1.B1[3].B2[8].B3[4]::M3 (work@small_top.u1.B1[3].B2[8].B3[4].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[3].B2[8].B3[4]::M3 (work@small_top.u1.B1[3].B2[8].B3[4].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[3].B2[8].B3[4]) |vpiName:N3 @@ -31508,8 +31508,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[3].B2[8].B3[5].k - |vpiModule: - \_module: work@small_top.u1.B1[3].B2[8].B3[5]::M3 (work@small_top.u1.B1[3].B2[8].B3[5].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[3].B2[8].B3[5]::M3 (work@small_top.u1.B1[3].B2[8].B3[5].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[3].B2[8].B3[5]) |vpiName:N3 @@ -31536,8 +31536,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[3].B2[8].B3[6].k - |vpiModule: - \_module: work@small_top.u1.B1[3].B2[8].B3[6]::M3 (work@small_top.u1.B1[3].B2[8].B3[6].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[3].B2[8].B3[6]::M3 (work@small_top.u1.B1[3].B2[8].B3[6].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[3].B2[8].B3[6]) |vpiName:N3 @@ -31564,8 +31564,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[3].B2[8].B3[7].k - |vpiModule: - \_module: work@small_top.u1.B1[3].B2[8].B3[7]::M3 (work@small_top.u1.B1[3].B2[8].B3[7].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[3].B2[8].B3[7]::M3 (work@small_top.u1.B1[3].B2[8].B3[7].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[3].B2[8].B3[7]) |vpiName:N3 @@ -31592,8 +31592,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[3].B2[8].B3[8].k - |vpiModule: - \_module: work@small_top.u1.B1[3].B2[8].B3[8]::M3 (work@small_top.u1.B1[3].B2[8].B3[8].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[3].B2[8].B3[8]::M3 (work@small_top.u1.B1[3].B2[8].B3[8].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[3].B2[8].B3[8]) |vpiName:N3 @@ -31620,8 +31620,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[3].B2[8].B3[9].k - |vpiModule: - \_module: work@small_top.u1.B1[3].B2[8].B3[9]::M3 (work@small_top.u1.B1[3].B2[8].B3[9].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[3].B2[8].B3[9]::M3 (work@small_top.u1.B1[3].B2[8].B3[9].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[3].B2[8].B3[9]) |vpiName:N3 @@ -31648,8 +31648,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:j |vpiFullName:work@small_top.u1.B1[3].B2[9].j - |vpiModule: - \_module: work@small_top.u1.B1[3].B2[9]::M2 (work@small_top.u1.B1[3].B2[9].N2), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:26:1, endln:26:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[3].B2[9]::M2 (work@small_top.u1.B1[3].B2[9].N2), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:26:1, endln:26:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[3].B2[9]) |vpiName:N2 @@ -31676,8 +31676,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[3].B2[9].B3[0].k - |vpiModule: - \_module: work@small_top.u1.B1[3].B2[9].B3[0]::M3 (work@small_top.u1.B1[3].B2[9].B3[0].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[3].B2[9].B3[0]::M3 (work@small_top.u1.B1[3].B2[9].B3[0].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[3].B2[9].B3[0]) |vpiName:N3 @@ -31704,8 +31704,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[3].B2[9].B3[1].k - |vpiModule: - \_module: work@small_top.u1.B1[3].B2[9].B3[1]::M3 (work@small_top.u1.B1[3].B2[9].B3[1].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[3].B2[9].B3[1]::M3 (work@small_top.u1.B1[3].B2[9].B3[1].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[3].B2[9].B3[1]) |vpiName:N3 @@ -31732,8 +31732,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[3].B2[9].B3[2].k - |vpiModule: - \_module: work@small_top.u1.B1[3].B2[9].B3[2]::M3 (work@small_top.u1.B1[3].B2[9].B3[2].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[3].B2[9].B3[2]::M3 (work@small_top.u1.B1[3].B2[9].B3[2].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[3].B2[9].B3[2]) |vpiName:N3 @@ -31760,8 +31760,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[3].B2[9].B3[3].k - |vpiModule: - \_module: work@small_top.u1.B1[3].B2[9].B3[3]::M3 (work@small_top.u1.B1[3].B2[9].B3[3].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[3].B2[9].B3[3]::M3 (work@small_top.u1.B1[3].B2[9].B3[3].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[3].B2[9].B3[3]) |vpiName:N3 @@ -31788,8 +31788,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[3].B2[9].B3[4].k - |vpiModule: - \_module: work@small_top.u1.B1[3].B2[9].B3[4]::M3 (work@small_top.u1.B1[3].B2[9].B3[4].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[3].B2[9].B3[4]::M3 (work@small_top.u1.B1[3].B2[9].B3[4].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[3].B2[9].B3[4]) |vpiName:N3 @@ -31816,8 +31816,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[3].B2[9].B3[5].k - |vpiModule: - \_module: work@small_top.u1.B1[3].B2[9].B3[5]::M3 (work@small_top.u1.B1[3].B2[9].B3[5].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[3].B2[9].B3[5]::M3 (work@small_top.u1.B1[3].B2[9].B3[5].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[3].B2[9].B3[5]) |vpiName:N3 @@ -31844,8 +31844,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[3].B2[9].B3[6].k - |vpiModule: - \_module: work@small_top.u1.B1[3].B2[9].B3[6]::M3 (work@small_top.u1.B1[3].B2[9].B3[6].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[3].B2[9].B3[6]::M3 (work@small_top.u1.B1[3].B2[9].B3[6].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[3].B2[9].B3[6]) |vpiName:N3 @@ -31872,8 +31872,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[3].B2[9].B3[7].k - |vpiModule: - \_module: work@small_top.u1.B1[3].B2[9].B3[7]::M3 (work@small_top.u1.B1[3].B2[9].B3[7].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[3].B2[9].B3[7]::M3 (work@small_top.u1.B1[3].B2[9].B3[7].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[3].B2[9].B3[7]) |vpiName:N3 @@ -31900,8 +31900,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[3].B2[9].B3[8].k - |vpiModule: - \_module: work@small_top.u1.B1[3].B2[9].B3[8]::M3 (work@small_top.u1.B1[3].B2[9].B3[8].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[3].B2[9].B3[8]::M3 (work@small_top.u1.B1[3].B2[9].B3[8].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[3].B2[9].B3[8]) |vpiName:N3 @@ -31928,8 +31928,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[3].B2[9].B3[9].k - |vpiModule: - \_module: work@small_top.u1.B1[3].B2[9].B3[9]::M3 (work@small_top.u1.B1[3].B2[9].B3[9].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[3].B2[9].B3[9]::M3 (work@small_top.u1.B1[3].B2[9].B3[9].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[3].B2[9].B3[9]) |vpiName:N3 @@ -31967,8 +31967,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:m |vpiFullName:work@small_top.u1.B1[3].B4.B5[0].m - |vpiModule: - \_module: work@small_top.u1.B1[3].B4.B5[0]::M4 (work@small_top.u1.B1[3].B4.B5[0].N4), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:46:1, endln:46:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[3].B4.B5[0]::M4 (work@small_top.u1.B1[3].B4.B5[0].N4), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:46:1, endln:46:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[3].B4.B5[0]) |vpiName:N4 @@ -31995,8 +31995,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:m |vpiFullName:work@small_top.u1.B1[3].B4.B5[1].m - |vpiModule: - \_module: work@small_top.u1.B1[3].B4.B5[1]::M4 (work@small_top.u1.B1[3].B4.B5[1].N4), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:46:1, endln:46:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[3].B4.B5[1]::M4 (work@small_top.u1.B1[3].B4.B5[1].N4), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:46:1, endln:46:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[3].B4.B5[1]) |vpiName:N4 @@ -32023,8 +32023,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:m |vpiFullName:work@small_top.u1.B1[3].B4.B5[2].m - |vpiModule: - \_module: work@small_top.u1.B1[3].B4.B5[2]::M4 (work@small_top.u1.B1[3].B4.B5[2].N4), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:46:1, endln:46:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[3].B4.B5[2]::M4 (work@small_top.u1.B1[3].B4.B5[2].N4), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:46:1, endln:46:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[3].B4.B5[2]) |vpiName:N4 @@ -32051,8 +32051,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:m |vpiFullName:work@small_top.u1.B1[3].B4.B5[3].m - |vpiModule: - \_module: work@small_top.u1.B1[3].B4.B5[3]::M4 (work@small_top.u1.B1[3].B4.B5[3].N4), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:46:1, endln:46:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[3].B4.B5[3]::M4 (work@small_top.u1.B1[3].B4.B5[3].N4), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:46:1, endln:46:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[3].B4.B5[3]) |vpiName:N4 @@ -32079,8 +32079,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:m |vpiFullName:work@small_top.u1.B1[3].B4.B5[4].m - |vpiModule: - \_module: work@small_top.u1.B1[3].B4.B5[4]::M4 (work@small_top.u1.B1[3].B4.B5[4].N4), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:46:1, endln:46:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[3].B4.B5[4]::M4 (work@small_top.u1.B1[3].B4.B5[4].N4), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:46:1, endln:46:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[3].B4.B5[4]) |vpiName:N4 @@ -32107,8 +32107,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:m |vpiFullName:work@small_top.u1.B1[3].B4.B5[5].m - |vpiModule: - \_module: work@small_top.u1.B1[3].B4.B5[5]::M4 (work@small_top.u1.B1[3].B4.B5[5].N4), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:46:1, endln:46:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[3].B4.B5[5]::M4 (work@small_top.u1.B1[3].B4.B5[5].N4), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:46:1, endln:46:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[3].B4.B5[5]) |vpiName:N4 @@ -32135,8 +32135,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:m |vpiFullName:work@small_top.u1.B1[3].B4.B5[6].m - |vpiModule: - \_module: work@small_top.u1.B1[3].B4.B5[6]::M4 (work@small_top.u1.B1[3].B4.B5[6].N4), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:46:1, endln:46:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[3].B4.B5[6]::M4 (work@small_top.u1.B1[3].B4.B5[6].N4), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:46:1, endln:46:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[3].B4.B5[6]) |vpiName:N4 @@ -32163,8 +32163,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:m |vpiFullName:work@small_top.u1.B1[3].B4.B5[7].m - |vpiModule: - \_module: work@small_top.u1.B1[3].B4.B5[7]::M4 (work@small_top.u1.B1[3].B4.B5[7].N4), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:46:1, endln:46:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[3].B4.B5[7]::M4 (work@small_top.u1.B1[3].B4.B5[7].N4), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:46:1, endln:46:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[3].B4.B5[7]) |vpiName:N4 @@ -32191,8 +32191,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:m |vpiFullName:work@small_top.u1.B1[3].B4.B5[8].m - |vpiModule: - \_module: work@small_top.u1.B1[3].B4.B5[8]::M4 (work@small_top.u1.B1[3].B4.B5[8].N4), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:46:1, endln:46:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[3].B4.B5[8]::M4 (work@small_top.u1.B1[3].B4.B5[8].N4), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:46:1, endln:46:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[3].B4.B5[8]) |vpiName:N4 @@ -32219,8 +32219,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:m |vpiFullName:work@small_top.u1.B1[3].B4.B5[9].m - |vpiModule: - \_module: work@small_top.u1.B1[3].B4.B5[9]::M4 (work@small_top.u1.B1[3].B4.B5[9].N4), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:46:1, endln:46:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[3].B4.B5[9]::M4 (work@small_top.u1.B1[3].B4.B5[9].N4), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:46:1, endln:46:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[3].B4.B5[9]) |vpiName:N4 @@ -32229,7 +32229,7 @@ design: (work@bottom1) |vpiGenScopeArray: \_gen_scope_array: (work@small_top.u1.B1[4]), line:17:1, endln:51:4 |vpiParent: - \_module: work@small_test (work@small_top.u1), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:2:4, endln:2:29 + \_module_inst: work@small_test (work@small_top.u1), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:2:4, endln:2:29 |vpiName:B1[4] |vpiFullName:work@small_top.u1.B1[4] |vpiGenScope: @@ -32247,8 +32247,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:i |vpiFullName:work@small_top.u1.B1[4].i - |vpiModule: - \_module: work@small_top.u1.B1[4]::M1 (work@small_top.u1.B1[4].N1), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:20:1, endln:20:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[4]::M1 (work@small_top.u1.B1[4].N1), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:20:1, endln:20:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[4]) |vpiName:N1 @@ -32275,8 +32275,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:j |vpiFullName:work@small_top.u1.B1[4].B2[0].j - |vpiModule: - \_module: work@small_top.u1.B1[4].B2[0]::M2 (work@small_top.u1.B1[4].B2[0].N2), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:26:1, endln:26:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[4].B2[0]::M2 (work@small_top.u1.B1[4].B2[0].N2), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:26:1, endln:26:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[4].B2[0]) |vpiName:N2 @@ -32303,8 +32303,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[4].B2[0].B3[0].k - |vpiModule: - \_module: work@small_top.u1.B1[4].B2[0].B3[0]::M3 (work@small_top.u1.B1[4].B2[0].B3[0].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[4].B2[0].B3[0]::M3 (work@small_top.u1.B1[4].B2[0].B3[0].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[4].B2[0].B3[0]) |vpiName:N3 @@ -32331,8 +32331,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[4].B2[0].B3[1].k - |vpiModule: - \_module: work@small_top.u1.B1[4].B2[0].B3[1]::M3 (work@small_top.u1.B1[4].B2[0].B3[1].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[4].B2[0].B3[1]::M3 (work@small_top.u1.B1[4].B2[0].B3[1].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[4].B2[0].B3[1]) |vpiName:N3 @@ -32359,8 +32359,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[4].B2[0].B3[2].k - |vpiModule: - \_module: work@small_top.u1.B1[4].B2[0].B3[2]::M3 (work@small_top.u1.B1[4].B2[0].B3[2].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[4].B2[0].B3[2]::M3 (work@small_top.u1.B1[4].B2[0].B3[2].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[4].B2[0].B3[2]) |vpiName:N3 @@ -32387,8 +32387,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[4].B2[0].B3[3].k - |vpiModule: - \_module: work@small_top.u1.B1[4].B2[0].B3[3]::M3 (work@small_top.u1.B1[4].B2[0].B3[3].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[4].B2[0].B3[3]::M3 (work@small_top.u1.B1[4].B2[0].B3[3].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[4].B2[0].B3[3]) |vpiName:N3 @@ -32415,8 +32415,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[4].B2[0].B3[4].k - |vpiModule: - \_module: work@small_top.u1.B1[4].B2[0].B3[4]::M3 (work@small_top.u1.B1[4].B2[0].B3[4].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[4].B2[0].B3[4]::M3 (work@small_top.u1.B1[4].B2[0].B3[4].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[4].B2[0].B3[4]) |vpiName:N3 @@ -32443,8 +32443,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[4].B2[0].B3[5].k - |vpiModule: - \_module: work@small_top.u1.B1[4].B2[0].B3[5]::M3 (work@small_top.u1.B1[4].B2[0].B3[5].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[4].B2[0].B3[5]::M3 (work@small_top.u1.B1[4].B2[0].B3[5].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[4].B2[0].B3[5]) |vpiName:N3 @@ -32471,8 +32471,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[4].B2[0].B3[6].k - |vpiModule: - \_module: work@small_top.u1.B1[4].B2[0].B3[6]::M3 (work@small_top.u1.B1[4].B2[0].B3[6].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[4].B2[0].B3[6]::M3 (work@small_top.u1.B1[4].B2[0].B3[6].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[4].B2[0].B3[6]) |vpiName:N3 @@ -32499,8 +32499,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[4].B2[0].B3[7].k - |vpiModule: - \_module: work@small_top.u1.B1[4].B2[0].B3[7]::M3 (work@small_top.u1.B1[4].B2[0].B3[7].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[4].B2[0].B3[7]::M3 (work@small_top.u1.B1[4].B2[0].B3[7].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[4].B2[0].B3[7]) |vpiName:N3 @@ -32527,8 +32527,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[4].B2[0].B3[8].k - |vpiModule: - \_module: work@small_top.u1.B1[4].B2[0].B3[8]::M3 (work@small_top.u1.B1[4].B2[0].B3[8].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[4].B2[0].B3[8]::M3 (work@small_top.u1.B1[4].B2[0].B3[8].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[4].B2[0].B3[8]) |vpiName:N3 @@ -32555,8 +32555,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[4].B2[0].B3[9].k - |vpiModule: - \_module: work@small_top.u1.B1[4].B2[0].B3[9]::M3 (work@small_top.u1.B1[4].B2[0].B3[9].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[4].B2[0].B3[9]::M3 (work@small_top.u1.B1[4].B2[0].B3[9].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[4].B2[0].B3[9]) |vpiName:N3 @@ -32583,8 +32583,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:j |vpiFullName:work@small_top.u1.B1[4].B2[1].j - |vpiModule: - \_module: work@small_top.u1.B1[4].B2[1]::M2 (work@small_top.u1.B1[4].B2[1].N2), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:26:1, endln:26:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[4].B2[1]::M2 (work@small_top.u1.B1[4].B2[1].N2), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:26:1, endln:26:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[4].B2[1]) |vpiName:N2 @@ -32611,8 +32611,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[4].B2[1].B3[0].k - |vpiModule: - \_module: work@small_top.u1.B1[4].B2[1].B3[0]::M3 (work@small_top.u1.B1[4].B2[1].B3[0].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[4].B2[1].B3[0]::M3 (work@small_top.u1.B1[4].B2[1].B3[0].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[4].B2[1].B3[0]) |vpiName:N3 @@ -32639,8 +32639,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[4].B2[1].B3[1].k - |vpiModule: - \_module: work@small_top.u1.B1[4].B2[1].B3[1]::M3 (work@small_top.u1.B1[4].B2[1].B3[1].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[4].B2[1].B3[1]::M3 (work@small_top.u1.B1[4].B2[1].B3[1].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[4].B2[1].B3[1]) |vpiName:N3 @@ -32667,8 +32667,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[4].B2[1].B3[2].k - |vpiModule: - \_module: work@small_top.u1.B1[4].B2[1].B3[2]::M3 (work@small_top.u1.B1[4].B2[1].B3[2].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[4].B2[1].B3[2]::M3 (work@small_top.u1.B1[4].B2[1].B3[2].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[4].B2[1].B3[2]) |vpiName:N3 @@ -32695,8 +32695,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[4].B2[1].B3[3].k - |vpiModule: - \_module: work@small_top.u1.B1[4].B2[1].B3[3]::M3 (work@small_top.u1.B1[4].B2[1].B3[3].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[4].B2[1].B3[3]::M3 (work@small_top.u1.B1[4].B2[1].B3[3].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[4].B2[1].B3[3]) |vpiName:N3 @@ -32723,8 +32723,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[4].B2[1].B3[4].k - |vpiModule: - \_module: work@small_top.u1.B1[4].B2[1].B3[4]::M3 (work@small_top.u1.B1[4].B2[1].B3[4].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[4].B2[1].B3[4]::M3 (work@small_top.u1.B1[4].B2[1].B3[4].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[4].B2[1].B3[4]) |vpiName:N3 @@ -32751,8 +32751,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[4].B2[1].B3[5].k - |vpiModule: - \_module: work@small_top.u1.B1[4].B2[1].B3[5]::M3 (work@small_top.u1.B1[4].B2[1].B3[5].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[4].B2[1].B3[5]::M3 (work@small_top.u1.B1[4].B2[1].B3[5].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[4].B2[1].B3[5]) |vpiName:N3 @@ -32779,8 +32779,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[4].B2[1].B3[6].k - |vpiModule: - \_module: work@small_top.u1.B1[4].B2[1].B3[6]::M3 (work@small_top.u1.B1[4].B2[1].B3[6].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[4].B2[1].B3[6]::M3 (work@small_top.u1.B1[4].B2[1].B3[6].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[4].B2[1].B3[6]) |vpiName:N3 @@ -32807,8 +32807,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[4].B2[1].B3[7].k - |vpiModule: - \_module: work@small_top.u1.B1[4].B2[1].B3[7]::M3 (work@small_top.u1.B1[4].B2[1].B3[7].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[4].B2[1].B3[7]::M3 (work@small_top.u1.B1[4].B2[1].B3[7].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[4].B2[1].B3[7]) |vpiName:N3 @@ -32835,8 +32835,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[4].B2[1].B3[8].k - |vpiModule: - \_module: work@small_top.u1.B1[4].B2[1].B3[8]::M3 (work@small_top.u1.B1[4].B2[1].B3[8].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[4].B2[1].B3[8]::M3 (work@small_top.u1.B1[4].B2[1].B3[8].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[4].B2[1].B3[8]) |vpiName:N3 @@ -32863,8 +32863,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[4].B2[1].B3[9].k - |vpiModule: - \_module: work@small_top.u1.B1[4].B2[1].B3[9]::M3 (work@small_top.u1.B1[4].B2[1].B3[9].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[4].B2[1].B3[9]::M3 (work@small_top.u1.B1[4].B2[1].B3[9].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[4].B2[1].B3[9]) |vpiName:N3 @@ -32891,8 +32891,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:j |vpiFullName:work@small_top.u1.B1[4].B2[2].j - |vpiModule: - \_module: work@small_top.u1.B1[4].B2[2]::M2 (work@small_top.u1.B1[4].B2[2].N2), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:26:1, endln:26:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[4].B2[2]::M2 (work@small_top.u1.B1[4].B2[2].N2), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:26:1, endln:26:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[4].B2[2]) |vpiName:N2 @@ -32919,8 +32919,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[4].B2[2].B3[0].k - |vpiModule: - \_module: work@small_top.u1.B1[4].B2[2].B3[0]::M3 (work@small_top.u1.B1[4].B2[2].B3[0].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[4].B2[2].B3[0]::M3 (work@small_top.u1.B1[4].B2[2].B3[0].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[4].B2[2].B3[0]) |vpiName:N3 @@ -32947,8 +32947,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[4].B2[2].B3[1].k - |vpiModule: - \_module: work@small_top.u1.B1[4].B2[2].B3[1]::M3 (work@small_top.u1.B1[4].B2[2].B3[1].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[4].B2[2].B3[1]::M3 (work@small_top.u1.B1[4].B2[2].B3[1].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[4].B2[2].B3[1]) |vpiName:N3 @@ -32975,8 +32975,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[4].B2[2].B3[2].k - |vpiModule: - \_module: work@small_top.u1.B1[4].B2[2].B3[2]::M3 (work@small_top.u1.B1[4].B2[2].B3[2].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[4].B2[2].B3[2]::M3 (work@small_top.u1.B1[4].B2[2].B3[2].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[4].B2[2].B3[2]) |vpiName:N3 @@ -33003,8 +33003,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[4].B2[2].B3[3].k - |vpiModule: - \_module: work@small_top.u1.B1[4].B2[2].B3[3]::M3 (work@small_top.u1.B1[4].B2[2].B3[3].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[4].B2[2].B3[3]::M3 (work@small_top.u1.B1[4].B2[2].B3[3].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[4].B2[2].B3[3]) |vpiName:N3 @@ -33031,8 +33031,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[4].B2[2].B3[4].k - |vpiModule: - \_module: work@small_top.u1.B1[4].B2[2].B3[4]::M3 (work@small_top.u1.B1[4].B2[2].B3[4].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[4].B2[2].B3[4]::M3 (work@small_top.u1.B1[4].B2[2].B3[4].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[4].B2[2].B3[4]) |vpiName:N3 @@ -33059,8 +33059,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[4].B2[2].B3[5].k - |vpiModule: - \_module: work@small_top.u1.B1[4].B2[2].B3[5]::M3 (work@small_top.u1.B1[4].B2[2].B3[5].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[4].B2[2].B3[5]::M3 (work@small_top.u1.B1[4].B2[2].B3[5].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[4].B2[2].B3[5]) |vpiName:N3 @@ -33087,8 +33087,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[4].B2[2].B3[6].k - |vpiModule: - \_module: work@small_top.u1.B1[4].B2[2].B3[6]::M3 (work@small_top.u1.B1[4].B2[2].B3[6].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[4].B2[2].B3[6]::M3 (work@small_top.u1.B1[4].B2[2].B3[6].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[4].B2[2].B3[6]) |vpiName:N3 @@ -33115,8 +33115,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[4].B2[2].B3[7].k - |vpiModule: - \_module: work@small_top.u1.B1[4].B2[2].B3[7]::M3 (work@small_top.u1.B1[4].B2[2].B3[7].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[4].B2[2].B3[7]::M3 (work@small_top.u1.B1[4].B2[2].B3[7].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[4].B2[2].B3[7]) |vpiName:N3 @@ -33143,8 +33143,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[4].B2[2].B3[8].k - |vpiModule: - \_module: work@small_top.u1.B1[4].B2[2].B3[8]::M3 (work@small_top.u1.B1[4].B2[2].B3[8].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[4].B2[2].B3[8]::M3 (work@small_top.u1.B1[4].B2[2].B3[8].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[4].B2[2].B3[8]) |vpiName:N3 @@ -33171,8 +33171,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[4].B2[2].B3[9].k - |vpiModule: - \_module: work@small_top.u1.B1[4].B2[2].B3[9]::M3 (work@small_top.u1.B1[4].B2[2].B3[9].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[4].B2[2].B3[9]::M3 (work@small_top.u1.B1[4].B2[2].B3[9].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[4].B2[2].B3[9]) |vpiName:N3 @@ -33199,8 +33199,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:j |vpiFullName:work@small_top.u1.B1[4].B2[3].j - |vpiModule: - \_module: work@small_top.u1.B1[4].B2[3]::M2 (work@small_top.u1.B1[4].B2[3].N2), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:26:1, endln:26:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[4].B2[3]::M2 (work@small_top.u1.B1[4].B2[3].N2), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:26:1, endln:26:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[4].B2[3]) |vpiName:N2 @@ -33227,8 +33227,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[4].B2[3].B3[0].k - |vpiModule: - \_module: work@small_top.u1.B1[4].B2[3].B3[0]::M3 (work@small_top.u1.B1[4].B2[3].B3[0].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[4].B2[3].B3[0]::M3 (work@small_top.u1.B1[4].B2[3].B3[0].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[4].B2[3].B3[0]) |vpiName:N3 @@ -33255,8 +33255,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[4].B2[3].B3[1].k - |vpiModule: - \_module: work@small_top.u1.B1[4].B2[3].B3[1]::M3 (work@small_top.u1.B1[4].B2[3].B3[1].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[4].B2[3].B3[1]::M3 (work@small_top.u1.B1[4].B2[3].B3[1].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[4].B2[3].B3[1]) |vpiName:N3 @@ -33283,8 +33283,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[4].B2[3].B3[2].k - |vpiModule: - \_module: work@small_top.u1.B1[4].B2[3].B3[2]::M3 (work@small_top.u1.B1[4].B2[3].B3[2].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[4].B2[3].B3[2]::M3 (work@small_top.u1.B1[4].B2[3].B3[2].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[4].B2[3].B3[2]) |vpiName:N3 @@ -33311,8 +33311,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[4].B2[3].B3[3].k - |vpiModule: - \_module: work@small_top.u1.B1[4].B2[3].B3[3]::M3 (work@small_top.u1.B1[4].B2[3].B3[3].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[4].B2[3].B3[3]::M3 (work@small_top.u1.B1[4].B2[3].B3[3].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[4].B2[3].B3[3]) |vpiName:N3 @@ -33339,8 +33339,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[4].B2[3].B3[4].k - |vpiModule: - \_module: work@small_top.u1.B1[4].B2[3].B3[4]::M3 (work@small_top.u1.B1[4].B2[3].B3[4].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[4].B2[3].B3[4]::M3 (work@small_top.u1.B1[4].B2[3].B3[4].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[4].B2[3].B3[4]) |vpiName:N3 @@ -33367,8 +33367,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[4].B2[3].B3[5].k - |vpiModule: - \_module: work@small_top.u1.B1[4].B2[3].B3[5]::M3 (work@small_top.u1.B1[4].B2[3].B3[5].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[4].B2[3].B3[5]::M3 (work@small_top.u1.B1[4].B2[3].B3[5].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[4].B2[3].B3[5]) |vpiName:N3 @@ -33395,8 +33395,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[4].B2[3].B3[6].k - |vpiModule: - \_module: work@small_top.u1.B1[4].B2[3].B3[6]::M3 (work@small_top.u1.B1[4].B2[3].B3[6].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[4].B2[3].B3[6]::M3 (work@small_top.u1.B1[4].B2[3].B3[6].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[4].B2[3].B3[6]) |vpiName:N3 @@ -33423,8 +33423,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[4].B2[3].B3[7].k - |vpiModule: - \_module: work@small_top.u1.B1[4].B2[3].B3[7]::M3 (work@small_top.u1.B1[4].B2[3].B3[7].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[4].B2[3].B3[7]::M3 (work@small_top.u1.B1[4].B2[3].B3[7].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[4].B2[3].B3[7]) |vpiName:N3 @@ -33451,8 +33451,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[4].B2[3].B3[8].k - |vpiModule: - \_module: work@small_top.u1.B1[4].B2[3].B3[8]::M3 (work@small_top.u1.B1[4].B2[3].B3[8].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[4].B2[3].B3[8]::M3 (work@small_top.u1.B1[4].B2[3].B3[8].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[4].B2[3].B3[8]) |vpiName:N3 @@ -33479,8 +33479,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[4].B2[3].B3[9].k - |vpiModule: - \_module: work@small_top.u1.B1[4].B2[3].B3[9]::M3 (work@small_top.u1.B1[4].B2[3].B3[9].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[4].B2[3].B3[9]::M3 (work@small_top.u1.B1[4].B2[3].B3[9].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[4].B2[3].B3[9]) |vpiName:N3 @@ -33507,8 +33507,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:j |vpiFullName:work@small_top.u1.B1[4].B2[4].j - |vpiModule: - \_module: work@small_top.u1.B1[4].B2[4]::M2 (work@small_top.u1.B1[4].B2[4].N2), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:26:1, endln:26:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[4].B2[4]::M2 (work@small_top.u1.B1[4].B2[4].N2), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:26:1, endln:26:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[4].B2[4]) |vpiName:N2 @@ -33535,8 +33535,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[4].B2[4].B3[0].k - |vpiModule: - \_module: work@small_top.u1.B1[4].B2[4].B3[0]::M3 (work@small_top.u1.B1[4].B2[4].B3[0].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[4].B2[4].B3[0]::M3 (work@small_top.u1.B1[4].B2[4].B3[0].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[4].B2[4].B3[0]) |vpiName:N3 @@ -33563,8 +33563,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[4].B2[4].B3[1].k - |vpiModule: - \_module: work@small_top.u1.B1[4].B2[4].B3[1]::M3 (work@small_top.u1.B1[4].B2[4].B3[1].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[4].B2[4].B3[1]::M3 (work@small_top.u1.B1[4].B2[4].B3[1].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[4].B2[4].B3[1]) |vpiName:N3 @@ -33591,8 +33591,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[4].B2[4].B3[2].k - |vpiModule: - \_module: work@small_top.u1.B1[4].B2[4].B3[2]::M3 (work@small_top.u1.B1[4].B2[4].B3[2].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[4].B2[4].B3[2]::M3 (work@small_top.u1.B1[4].B2[4].B3[2].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[4].B2[4].B3[2]) |vpiName:N3 @@ -33619,8 +33619,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[4].B2[4].B3[3].k - |vpiModule: - \_module: work@small_top.u1.B1[4].B2[4].B3[3]::M3 (work@small_top.u1.B1[4].B2[4].B3[3].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[4].B2[4].B3[3]::M3 (work@small_top.u1.B1[4].B2[4].B3[3].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[4].B2[4].B3[3]) |vpiName:N3 @@ -33647,8 +33647,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[4].B2[4].B3[4].k - |vpiModule: - \_module: work@small_top.u1.B1[4].B2[4].B3[4]::M3 (work@small_top.u1.B1[4].B2[4].B3[4].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[4].B2[4].B3[4]::M3 (work@small_top.u1.B1[4].B2[4].B3[4].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[4].B2[4].B3[4]) |vpiName:N3 @@ -33675,8 +33675,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[4].B2[4].B3[5].k - |vpiModule: - \_module: work@small_top.u1.B1[4].B2[4].B3[5]::M3 (work@small_top.u1.B1[4].B2[4].B3[5].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[4].B2[4].B3[5]::M3 (work@small_top.u1.B1[4].B2[4].B3[5].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[4].B2[4].B3[5]) |vpiName:N3 @@ -33703,8 +33703,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[4].B2[4].B3[6].k - |vpiModule: - \_module: work@small_top.u1.B1[4].B2[4].B3[6]::M3 (work@small_top.u1.B1[4].B2[4].B3[6].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[4].B2[4].B3[6]::M3 (work@small_top.u1.B1[4].B2[4].B3[6].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[4].B2[4].B3[6]) |vpiName:N3 @@ -33731,8 +33731,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[4].B2[4].B3[7].k - |vpiModule: - \_module: work@small_top.u1.B1[4].B2[4].B3[7]::M3 (work@small_top.u1.B1[4].B2[4].B3[7].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[4].B2[4].B3[7]::M3 (work@small_top.u1.B1[4].B2[4].B3[7].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[4].B2[4].B3[7]) |vpiName:N3 @@ -33759,8 +33759,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[4].B2[4].B3[8].k - |vpiModule: - \_module: work@small_top.u1.B1[4].B2[4].B3[8]::M3 (work@small_top.u1.B1[4].B2[4].B3[8].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[4].B2[4].B3[8]::M3 (work@small_top.u1.B1[4].B2[4].B3[8].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[4].B2[4].B3[8]) |vpiName:N3 @@ -33787,8 +33787,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[4].B2[4].B3[9].k - |vpiModule: - \_module: work@small_top.u1.B1[4].B2[4].B3[9]::M3 (work@small_top.u1.B1[4].B2[4].B3[9].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[4].B2[4].B3[9]::M3 (work@small_top.u1.B1[4].B2[4].B3[9].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[4].B2[4].B3[9]) |vpiName:N3 @@ -33815,8 +33815,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:j |vpiFullName:work@small_top.u1.B1[4].B2[5].j - |vpiModule: - \_module: work@small_top.u1.B1[4].B2[5]::M2 (work@small_top.u1.B1[4].B2[5].N2), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:26:1, endln:26:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[4].B2[5]::M2 (work@small_top.u1.B1[4].B2[5].N2), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:26:1, endln:26:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[4].B2[5]) |vpiName:N2 @@ -33843,8 +33843,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[4].B2[5].B3[0].k - |vpiModule: - \_module: work@small_top.u1.B1[4].B2[5].B3[0]::M3 (work@small_top.u1.B1[4].B2[5].B3[0].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[4].B2[5].B3[0]::M3 (work@small_top.u1.B1[4].B2[5].B3[0].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[4].B2[5].B3[0]) |vpiName:N3 @@ -33871,8 +33871,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[4].B2[5].B3[1].k - |vpiModule: - \_module: work@small_top.u1.B1[4].B2[5].B3[1]::M3 (work@small_top.u1.B1[4].B2[5].B3[1].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[4].B2[5].B3[1]::M3 (work@small_top.u1.B1[4].B2[5].B3[1].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[4].B2[5].B3[1]) |vpiName:N3 @@ -33899,8 +33899,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[4].B2[5].B3[2].k - |vpiModule: - \_module: work@small_top.u1.B1[4].B2[5].B3[2]::M3 (work@small_top.u1.B1[4].B2[5].B3[2].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[4].B2[5].B3[2]::M3 (work@small_top.u1.B1[4].B2[5].B3[2].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[4].B2[5].B3[2]) |vpiName:N3 @@ -33927,8 +33927,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[4].B2[5].B3[3].k - |vpiModule: - \_module: work@small_top.u1.B1[4].B2[5].B3[3]::M3 (work@small_top.u1.B1[4].B2[5].B3[3].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[4].B2[5].B3[3]::M3 (work@small_top.u1.B1[4].B2[5].B3[3].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[4].B2[5].B3[3]) |vpiName:N3 @@ -33955,8 +33955,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[4].B2[5].B3[4].k - |vpiModule: - \_module: work@small_top.u1.B1[4].B2[5].B3[4]::M3 (work@small_top.u1.B1[4].B2[5].B3[4].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[4].B2[5].B3[4]::M3 (work@small_top.u1.B1[4].B2[5].B3[4].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[4].B2[5].B3[4]) |vpiName:N3 @@ -33983,8 +33983,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[4].B2[5].B3[5].k - |vpiModule: - \_module: work@small_top.u1.B1[4].B2[5].B3[5]::M3 (work@small_top.u1.B1[4].B2[5].B3[5].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[4].B2[5].B3[5]::M3 (work@small_top.u1.B1[4].B2[5].B3[5].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[4].B2[5].B3[5]) |vpiName:N3 @@ -34011,8 +34011,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[4].B2[5].B3[6].k - |vpiModule: - \_module: work@small_top.u1.B1[4].B2[5].B3[6]::M3 (work@small_top.u1.B1[4].B2[5].B3[6].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[4].B2[5].B3[6]::M3 (work@small_top.u1.B1[4].B2[5].B3[6].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[4].B2[5].B3[6]) |vpiName:N3 @@ -34039,8 +34039,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[4].B2[5].B3[7].k - |vpiModule: - \_module: work@small_top.u1.B1[4].B2[5].B3[7]::M3 (work@small_top.u1.B1[4].B2[5].B3[7].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[4].B2[5].B3[7]::M3 (work@small_top.u1.B1[4].B2[5].B3[7].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[4].B2[5].B3[7]) |vpiName:N3 @@ -34067,8 +34067,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[4].B2[5].B3[8].k - |vpiModule: - \_module: work@small_top.u1.B1[4].B2[5].B3[8]::M3 (work@small_top.u1.B1[4].B2[5].B3[8].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[4].B2[5].B3[8]::M3 (work@small_top.u1.B1[4].B2[5].B3[8].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[4].B2[5].B3[8]) |vpiName:N3 @@ -34095,8 +34095,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[4].B2[5].B3[9].k - |vpiModule: - \_module: work@small_top.u1.B1[4].B2[5].B3[9]::M3 (work@small_top.u1.B1[4].B2[5].B3[9].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[4].B2[5].B3[9]::M3 (work@small_top.u1.B1[4].B2[5].B3[9].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[4].B2[5].B3[9]) |vpiName:N3 @@ -34123,8 +34123,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:j |vpiFullName:work@small_top.u1.B1[4].B2[6].j - |vpiModule: - \_module: work@small_top.u1.B1[4].B2[6]::M2 (work@small_top.u1.B1[4].B2[6].N2), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:26:1, endln:26:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[4].B2[6]::M2 (work@small_top.u1.B1[4].B2[6].N2), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:26:1, endln:26:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[4].B2[6]) |vpiName:N2 @@ -34151,8 +34151,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[4].B2[6].B3[0].k - |vpiModule: - \_module: work@small_top.u1.B1[4].B2[6].B3[0]::M3 (work@small_top.u1.B1[4].B2[6].B3[0].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[4].B2[6].B3[0]::M3 (work@small_top.u1.B1[4].B2[6].B3[0].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[4].B2[6].B3[0]) |vpiName:N3 @@ -34179,8 +34179,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[4].B2[6].B3[1].k - |vpiModule: - \_module: work@small_top.u1.B1[4].B2[6].B3[1]::M3 (work@small_top.u1.B1[4].B2[6].B3[1].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[4].B2[6].B3[1]::M3 (work@small_top.u1.B1[4].B2[6].B3[1].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[4].B2[6].B3[1]) |vpiName:N3 @@ -34207,8 +34207,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[4].B2[6].B3[2].k - |vpiModule: - \_module: work@small_top.u1.B1[4].B2[6].B3[2]::M3 (work@small_top.u1.B1[4].B2[6].B3[2].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[4].B2[6].B3[2]::M3 (work@small_top.u1.B1[4].B2[6].B3[2].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[4].B2[6].B3[2]) |vpiName:N3 @@ -34235,8 +34235,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[4].B2[6].B3[3].k - |vpiModule: - \_module: work@small_top.u1.B1[4].B2[6].B3[3]::M3 (work@small_top.u1.B1[4].B2[6].B3[3].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[4].B2[6].B3[3]::M3 (work@small_top.u1.B1[4].B2[6].B3[3].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[4].B2[6].B3[3]) |vpiName:N3 @@ -34263,8 +34263,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[4].B2[6].B3[4].k - |vpiModule: - \_module: work@small_top.u1.B1[4].B2[6].B3[4]::M3 (work@small_top.u1.B1[4].B2[6].B3[4].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[4].B2[6].B3[4]::M3 (work@small_top.u1.B1[4].B2[6].B3[4].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[4].B2[6].B3[4]) |vpiName:N3 @@ -34291,8 +34291,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[4].B2[6].B3[5].k - |vpiModule: - \_module: work@small_top.u1.B1[4].B2[6].B3[5]::M3 (work@small_top.u1.B1[4].B2[6].B3[5].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[4].B2[6].B3[5]::M3 (work@small_top.u1.B1[4].B2[6].B3[5].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[4].B2[6].B3[5]) |vpiName:N3 @@ -34319,8 +34319,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[4].B2[6].B3[6].k - |vpiModule: - \_module: work@small_top.u1.B1[4].B2[6].B3[6]::M3 (work@small_top.u1.B1[4].B2[6].B3[6].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[4].B2[6].B3[6]::M3 (work@small_top.u1.B1[4].B2[6].B3[6].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[4].B2[6].B3[6]) |vpiName:N3 @@ -34347,8 +34347,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[4].B2[6].B3[7].k - |vpiModule: - \_module: work@small_top.u1.B1[4].B2[6].B3[7]::M3 (work@small_top.u1.B1[4].B2[6].B3[7].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[4].B2[6].B3[7]::M3 (work@small_top.u1.B1[4].B2[6].B3[7].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[4].B2[6].B3[7]) |vpiName:N3 @@ -34375,8 +34375,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[4].B2[6].B3[8].k - |vpiModule: - \_module: work@small_top.u1.B1[4].B2[6].B3[8]::M3 (work@small_top.u1.B1[4].B2[6].B3[8].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[4].B2[6].B3[8]::M3 (work@small_top.u1.B1[4].B2[6].B3[8].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[4].B2[6].B3[8]) |vpiName:N3 @@ -34403,8 +34403,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[4].B2[6].B3[9].k - |vpiModule: - \_module: work@small_top.u1.B1[4].B2[6].B3[9]::M3 (work@small_top.u1.B1[4].B2[6].B3[9].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[4].B2[6].B3[9]::M3 (work@small_top.u1.B1[4].B2[6].B3[9].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[4].B2[6].B3[9]) |vpiName:N3 @@ -34431,8 +34431,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:j |vpiFullName:work@small_top.u1.B1[4].B2[7].j - |vpiModule: - \_module: work@small_top.u1.B1[4].B2[7]::M2 (work@small_top.u1.B1[4].B2[7].N2), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:26:1, endln:26:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[4].B2[7]::M2 (work@small_top.u1.B1[4].B2[7].N2), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:26:1, endln:26:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[4].B2[7]) |vpiName:N2 @@ -34459,8 +34459,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[4].B2[7].B3[0].k - |vpiModule: - \_module: work@small_top.u1.B1[4].B2[7].B3[0]::M3 (work@small_top.u1.B1[4].B2[7].B3[0].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[4].B2[7].B3[0]::M3 (work@small_top.u1.B1[4].B2[7].B3[0].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[4].B2[7].B3[0]) |vpiName:N3 @@ -34487,8 +34487,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[4].B2[7].B3[1].k - |vpiModule: - \_module: work@small_top.u1.B1[4].B2[7].B3[1]::M3 (work@small_top.u1.B1[4].B2[7].B3[1].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[4].B2[7].B3[1]::M3 (work@small_top.u1.B1[4].B2[7].B3[1].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[4].B2[7].B3[1]) |vpiName:N3 @@ -34515,8 +34515,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[4].B2[7].B3[2].k - |vpiModule: - \_module: work@small_top.u1.B1[4].B2[7].B3[2]::M3 (work@small_top.u1.B1[4].B2[7].B3[2].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[4].B2[7].B3[2]::M3 (work@small_top.u1.B1[4].B2[7].B3[2].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[4].B2[7].B3[2]) |vpiName:N3 @@ -34543,8 +34543,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[4].B2[7].B3[3].k - |vpiModule: - \_module: work@small_top.u1.B1[4].B2[7].B3[3]::M3 (work@small_top.u1.B1[4].B2[7].B3[3].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[4].B2[7].B3[3]::M3 (work@small_top.u1.B1[4].B2[7].B3[3].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[4].B2[7].B3[3]) |vpiName:N3 @@ -34571,8 +34571,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[4].B2[7].B3[4].k - |vpiModule: - \_module: work@small_top.u1.B1[4].B2[7].B3[4]::M3 (work@small_top.u1.B1[4].B2[7].B3[4].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[4].B2[7].B3[4]::M3 (work@small_top.u1.B1[4].B2[7].B3[4].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[4].B2[7].B3[4]) |vpiName:N3 @@ -34599,8 +34599,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[4].B2[7].B3[5].k - |vpiModule: - \_module: work@small_top.u1.B1[4].B2[7].B3[5]::M3 (work@small_top.u1.B1[4].B2[7].B3[5].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[4].B2[7].B3[5]::M3 (work@small_top.u1.B1[4].B2[7].B3[5].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[4].B2[7].B3[5]) |vpiName:N3 @@ -34627,8 +34627,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[4].B2[7].B3[6].k - |vpiModule: - \_module: work@small_top.u1.B1[4].B2[7].B3[6]::M3 (work@small_top.u1.B1[4].B2[7].B3[6].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[4].B2[7].B3[6]::M3 (work@small_top.u1.B1[4].B2[7].B3[6].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[4].B2[7].B3[6]) |vpiName:N3 @@ -34655,8 +34655,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[4].B2[7].B3[7].k - |vpiModule: - \_module: work@small_top.u1.B1[4].B2[7].B3[7]::M3 (work@small_top.u1.B1[4].B2[7].B3[7].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[4].B2[7].B3[7]::M3 (work@small_top.u1.B1[4].B2[7].B3[7].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[4].B2[7].B3[7]) |vpiName:N3 @@ -34683,8 +34683,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[4].B2[7].B3[8].k - |vpiModule: - \_module: work@small_top.u1.B1[4].B2[7].B3[8]::M3 (work@small_top.u1.B1[4].B2[7].B3[8].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[4].B2[7].B3[8]::M3 (work@small_top.u1.B1[4].B2[7].B3[8].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[4].B2[7].B3[8]) |vpiName:N3 @@ -34711,8 +34711,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[4].B2[7].B3[9].k - |vpiModule: - \_module: work@small_top.u1.B1[4].B2[7].B3[9]::M3 (work@small_top.u1.B1[4].B2[7].B3[9].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[4].B2[7].B3[9]::M3 (work@small_top.u1.B1[4].B2[7].B3[9].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[4].B2[7].B3[9]) |vpiName:N3 @@ -34739,8 +34739,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:j |vpiFullName:work@small_top.u1.B1[4].B2[8].j - |vpiModule: - \_module: work@small_top.u1.B1[4].B2[8]::M2 (work@small_top.u1.B1[4].B2[8].N2), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:26:1, endln:26:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[4].B2[8]::M2 (work@small_top.u1.B1[4].B2[8].N2), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:26:1, endln:26:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[4].B2[8]) |vpiName:N2 @@ -34767,8 +34767,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[4].B2[8].B3[0].k - |vpiModule: - \_module: work@small_top.u1.B1[4].B2[8].B3[0]::M3 (work@small_top.u1.B1[4].B2[8].B3[0].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[4].B2[8].B3[0]::M3 (work@small_top.u1.B1[4].B2[8].B3[0].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[4].B2[8].B3[0]) |vpiName:N3 @@ -34795,8 +34795,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[4].B2[8].B3[1].k - |vpiModule: - \_module: work@small_top.u1.B1[4].B2[8].B3[1]::M3 (work@small_top.u1.B1[4].B2[8].B3[1].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[4].B2[8].B3[1]::M3 (work@small_top.u1.B1[4].B2[8].B3[1].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[4].B2[8].B3[1]) |vpiName:N3 @@ -34823,8 +34823,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[4].B2[8].B3[2].k - |vpiModule: - \_module: work@small_top.u1.B1[4].B2[8].B3[2]::M3 (work@small_top.u1.B1[4].B2[8].B3[2].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[4].B2[8].B3[2]::M3 (work@small_top.u1.B1[4].B2[8].B3[2].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[4].B2[8].B3[2]) |vpiName:N3 @@ -34851,8 +34851,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[4].B2[8].B3[3].k - |vpiModule: - \_module: work@small_top.u1.B1[4].B2[8].B3[3]::M3 (work@small_top.u1.B1[4].B2[8].B3[3].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[4].B2[8].B3[3]::M3 (work@small_top.u1.B1[4].B2[8].B3[3].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[4].B2[8].B3[3]) |vpiName:N3 @@ -34879,8 +34879,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[4].B2[8].B3[4].k - |vpiModule: - \_module: work@small_top.u1.B1[4].B2[8].B3[4]::M3 (work@small_top.u1.B1[4].B2[8].B3[4].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[4].B2[8].B3[4]::M3 (work@small_top.u1.B1[4].B2[8].B3[4].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[4].B2[8].B3[4]) |vpiName:N3 @@ -34907,8 +34907,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[4].B2[8].B3[5].k - |vpiModule: - \_module: work@small_top.u1.B1[4].B2[8].B3[5]::M3 (work@small_top.u1.B1[4].B2[8].B3[5].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[4].B2[8].B3[5]::M3 (work@small_top.u1.B1[4].B2[8].B3[5].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[4].B2[8].B3[5]) |vpiName:N3 @@ -34935,8 +34935,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[4].B2[8].B3[6].k - |vpiModule: - \_module: work@small_top.u1.B1[4].B2[8].B3[6]::M3 (work@small_top.u1.B1[4].B2[8].B3[6].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[4].B2[8].B3[6]::M3 (work@small_top.u1.B1[4].B2[8].B3[6].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[4].B2[8].B3[6]) |vpiName:N3 @@ -34963,8 +34963,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[4].B2[8].B3[7].k - |vpiModule: - \_module: work@small_top.u1.B1[4].B2[8].B3[7]::M3 (work@small_top.u1.B1[4].B2[8].B3[7].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[4].B2[8].B3[7]::M3 (work@small_top.u1.B1[4].B2[8].B3[7].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[4].B2[8].B3[7]) |vpiName:N3 @@ -34991,8 +34991,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[4].B2[8].B3[8].k - |vpiModule: - \_module: work@small_top.u1.B1[4].B2[8].B3[8]::M3 (work@small_top.u1.B1[4].B2[8].B3[8].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[4].B2[8].B3[8]::M3 (work@small_top.u1.B1[4].B2[8].B3[8].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[4].B2[8].B3[8]) |vpiName:N3 @@ -35019,8 +35019,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[4].B2[8].B3[9].k - |vpiModule: - \_module: work@small_top.u1.B1[4].B2[8].B3[9]::M3 (work@small_top.u1.B1[4].B2[8].B3[9].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[4].B2[8].B3[9]::M3 (work@small_top.u1.B1[4].B2[8].B3[9].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[4].B2[8].B3[9]) |vpiName:N3 @@ -35047,8 +35047,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:j |vpiFullName:work@small_top.u1.B1[4].B2[9].j - |vpiModule: - \_module: work@small_top.u1.B1[4].B2[9]::M2 (work@small_top.u1.B1[4].B2[9].N2), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:26:1, endln:26:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[4].B2[9]::M2 (work@small_top.u1.B1[4].B2[9].N2), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:26:1, endln:26:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[4].B2[9]) |vpiName:N2 @@ -35075,8 +35075,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[4].B2[9].B3[0].k - |vpiModule: - \_module: work@small_top.u1.B1[4].B2[9].B3[0]::M3 (work@small_top.u1.B1[4].B2[9].B3[0].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[4].B2[9].B3[0]::M3 (work@small_top.u1.B1[4].B2[9].B3[0].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[4].B2[9].B3[0]) |vpiName:N3 @@ -35103,8 +35103,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[4].B2[9].B3[1].k - |vpiModule: - \_module: work@small_top.u1.B1[4].B2[9].B3[1]::M3 (work@small_top.u1.B1[4].B2[9].B3[1].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[4].B2[9].B3[1]::M3 (work@small_top.u1.B1[4].B2[9].B3[1].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[4].B2[9].B3[1]) |vpiName:N3 @@ -35131,8 +35131,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[4].B2[9].B3[2].k - |vpiModule: - \_module: work@small_top.u1.B1[4].B2[9].B3[2]::M3 (work@small_top.u1.B1[4].B2[9].B3[2].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[4].B2[9].B3[2]::M3 (work@small_top.u1.B1[4].B2[9].B3[2].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[4].B2[9].B3[2]) |vpiName:N3 @@ -35159,8 +35159,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[4].B2[9].B3[3].k - |vpiModule: - \_module: work@small_top.u1.B1[4].B2[9].B3[3]::M3 (work@small_top.u1.B1[4].B2[9].B3[3].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[4].B2[9].B3[3]::M3 (work@small_top.u1.B1[4].B2[9].B3[3].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[4].B2[9].B3[3]) |vpiName:N3 @@ -35187,8 +35187,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[4].B2[9].B3[4].k - |vpiModule: - \_module: work@small_top.u1.B1[4].B2[9].B3[4]::M3 (work@small_top.u1.B1[4].B2[9].B3[4].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[4].B2[9].B3[4]::M3 (work@small_top.u1.B1[4].B2[9].B3[4].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[4].B2[9].B3[4]) |vpiName:N3 @@ -35215,8 +35215,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[4].B2[9].B3[5].k - |vpiModule: - \_module: work@small_top.u1.B1[4].B2[9].B3[5]::M3 (work@small_top.u1.B1[4].B2[9].B3[5].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[4].B2[9].B3[5]::M3 (work@small_top.u1.B1[4].B2[9].B3[5].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[4].B2[9].B3[5]) |vpiName:N3 @@ -35243,8 +35243,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[4].B2[9].B3[6].k - |vpiModule: - \_module: work@small_top.u1.B1[4].B2[9].B3[6]::M3 (work@small_top.u1.B1[4].B2[9].B3[6].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[4].B2[9].B3[6]::M3 (work@small_top.u1.B1[4].B2[9].B3[6].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[4].B2[9].B3[6]) |vpiName:N3 @@ -35271,8 +35271,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[4].B2[9].B3[7].k - |vpiModule: - \_module: work@small_top.u1.B1[4].B2[9].B3[7]::M3 (work@small_top.u1.B1[4].B2[9].B3[7].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[4].B2[9].B3[7]::M3 (work@small_top.u1.B1[4].B2[9].B3[7].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[4].B2[9].B3[7]) |vpiName:N3 @@ -35299,8 +35299,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[4].B2[9].B3[8].k - |vpiModule: - \_module: work@small_top.u1.B1[4].B2[9].B3[8]::M3 (work@small_top.u1.B1[4].B2[9].B3[8].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[4].B2[9].B3[8]::M3 (work@small_top.u1.B1[4].B2[9].B3[8].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[4].B2[9].B3[8]) |vpiName:N3 @@ -35327,8 +35327,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[4].B2[9].B3[9].k - |vpiModule: - \_module: work@small_top.u1.B1[4].B2[9].B3[9]::M3 (work@small_top.u1.B1[4].B2[9].B3[9].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[4].B2[9].B3[9]::M3 (work@small_top.u1.B1[4].B2[9].B3[9].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[4].B2[9].B3[9]) |vpiName:N3 @@ -35366,8 +35366,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:m |vpiFullName:work@small_top.u1.B1[4].B4.B5[0].m - |vpiModule: - \_module: work@small_top.u1.B1[4].B4.B5[0]::M4 (work@small_top.u1.B1[4].B4.B5[0].N4), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:46:1, endln:46:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[4].B4.B5[0]::M4 (work@small_top.u1.B1[4].B4.B5[0].N4), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:46:1, endln:46:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[4].B4.B5[0]) |vpiName:N4 @@ -35394,8 +35394,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:m |vpiFullName:work@small_top.u1.B1[4].B4.B5[1].m - |vpiModule: - \_module: work@small_top.u1.B1[4].B4.B5[1]::M4 (work@small_top.u1.B1[4].B4.B5[1].N4), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:46:1, endln:46:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[4].B4.B5[1]::M4 (work@small_top.u1.B1[4].B4.B5[1].N4), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:46:1, endln:46:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[4].B4.B5[1]) |vpiName:N4 @@ -35422,8 +35422,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:m |vpiFullName:work@small_top.u1.B1[4].B4.B5[2].m - |vpiModule: - \_module: work@small_top.u1.B1[4].B4.B5[2]::M4 (work@small_top.u1.B1[4].B4.B5[2].N4), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:46:1, endln:46:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[4].B4.B5[2]::M4 (work@small_top.u1.B1[4].B4.B5[2].N4), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:46:1, endln:46:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[4].B4.B5[2]) |vpiName:N4 @@ -35450,8 +35450,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:m |vpiFullName:work@small_top.u1.B1[4].B4.B5[3].m - |vpiModule: - \_module: work@small_top.u1.B1[4].B4.B5[3]::M4 (work@small_top.u1.B1[4].B4.B5[3].N4), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:46:1, endln:46:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[4].B4.B5[3]::M4 (work@small_top.u1.B1[4].B4.B5[3].N4), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:46:1, endln:46:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[4].B4.B5[3]) |vpiName:N4 @@ -35478,8 +35478,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:m |vpiFullName:work@small_top.u1.B1[4].B4.B5[4].m - |vpiModule: - \_module: work@small_top.u1.B1[4].B4.B5[4]::M4 (work@small_top.u1.B1[4].B4.B5[4].N4), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:46:1, endln:46:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[4].B4.B5[4]::M4 (work@small_top.u1.B1[4].B4.B5[4].N4), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:46:1, endln:46:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[4].B4.B5[4]) |vpiName:N4 @@ -35506,8 +35506,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:m |vpiFullName:work@small_top.u1.B1[4].B4.B5[5].m - |vpiModule: - \_module: work@small_top.u1.B1[4].B4.B5[5]::M4 (work@small_top.u1.B1[4].B4.B5[5].N4), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:46:1, endln:46:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[4].B4.B5[5]::M4 (work@small_top.u1.B1[4].B4.B5[5].N4), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:46:1, endln:46:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[4].B4.B5[5]) |vpiName:N4 @@ -35534,8 +35534,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:m |vpiFullName:work@small_top.u1.B1[4].B4.B5[6].m - |vpiModule: - \_module: work@small_top.u1.B1[4].B4.B5[6]::M4 (work@small_top.u1.B1[4].B4.B5[6].N4), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:46:1, endln:46:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[4].B4.B5[6]::M4 (work@small_top.u1.B1[4].B4.B5[6].N4), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:46:1, endln:46:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[4].B4.B5[6]) |vpiName:N4 @@ -35562,8 +35562,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:m |vpiFullName:work@small_top.u1.B1[4].B4.B5[7].m - |vpiModule: - \_module: work@small_top.u1.B1[4].B4.B5[7]::M4 (work@small_top.u1.B1[4].B4.B5[7].N4), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:46:1, endln:46:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[4].B4.B5[7]::M4 (work@small_top.u1.B1[4].B4.B5[7].N4), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:46:1, endln:46:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[4].B4.B5[7]) |vpiName:N4 @@ -35590,8 +35590,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:m |vpiFullName:work@small_top.u1.B1[4].B4.B5[8].m - |vpiModule: - \_module: work@small_top.u1.B1[4].B4.B5[8]::M4 (work@small_top.u1.B1[4].B4.B5[8].N4), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:46:1, endln:46:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[4].B4.B5[8]::M4 (work@small_top.u1.B1[4].B4.B5[8].N4), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:46:1, endln:46:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[4].B4.B5[8]) |vpiName:N4 @@ -35618,8 +35618,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:m |vpiFullName:work@small_top.u1.B1[4].B4.B5[9].m - |vpiModule: - \_module: work@small_top.u1.B1[4].B4.B5[9]::M4 (work@small_top.u1.B1[4].B4.B5[9].N4), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:46:1, endln:46:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[4].B4.B5[9]::M4 (work@small_top.u1.B1[4].B4.B5[9].N4), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:46:1, endln:46:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[4].B4.B5[9]) |vpiName:N4 @@ -35628,7 +35628,7 @@ design: (work@bottom1) |vpiGenScopeArray: \_gen_scope_array: (work@small_top.u1.B1[5]), line:17:1, endln:51:4 |vpiParent: - \_module: work@small_test (work@small_top.u1), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:2:4, endln:2:29 + \_module_inst: work@small_test (work@small_top.u1), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:2:4, endln:2:29 |vpiName:B1[5] |vpiFullName:work@small_top.u1.B1[5] |vpiGenScope: @@ -35646,8 +35646,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:i |vpiFullName:work@small_top.u1.B1[5].i - |vpiModule: - \_module: work@small_top.u1.B1[5]::M1 (work@small_top.u1.B1[5].N1), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:20:1, endln:20:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[5]::M1 (work@small_top.u1.B1[5].N1), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:20:1, endln:20:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[5]) |vpiName:N1 @@ -35674,8 +35674,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:j |vpiFullName:work@small_top.u1.B1[5].B2[0].j - |vpiModule: - \_module: work@small_top.u1.B1[5].B2[0]::M2 (work@small_top.u1.B1[5].B2[0].N2), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:26:1, endln:26:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[5].B2[0]::M2 (work@small_top.u1.B1[5].B2[0].N2), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:26:1, endln:26:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[5].B2[0]) |vpiName:N2 @@ -35702,8 +35702,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[5].B2[0].B3[0].k - |vpiModule: - \_module: work@small_top.u1.B1[5].B2[0].B3[0]::M3 (work@small_top.u1.B1[5].B2[0].B3[0].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[5].B2[0].B3[0]::M3 (work@small_top.u1.B1[5].B2[0].B3[0].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[5].B2[0].B3[0]) |vpiName:N3 @@ -35730,8 +35730,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[5].B2[0].B3[1].k - |vpiModule: - \_module: work@small_top.u1.B1[5].B2[0].B3[1]::M3 (work@small_top.u1.B1[5].B2[0].B3[1].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[5].B2[0].B3[1]::M3 (work@small_top.u1.B1[5].B2[0].B3[1].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[5].B2[0].B3[1]) |vpiName:N3 @@ -35758,8 +35758,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[5].B2[0].B3[2].k - |vpiModule: - \_module: work@small_top.u1.B1[5].B2[0].B3[2]::M3 (work@small_top.u1.B1[5].B2[0].B3[2].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[5].B2[0].B3[2]::M3 (work@small_top.u1.B1[5].B2[0].B3[2].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[5].B2[0].B3[2]) |vpiName:N3 @@ -35786,8 +35786,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[5].B2[0].B3[3].k - |vpiModule: - \_module: work@small_top.u1.B1[5].B2[0].B3[3]::M3 (work@small_top.u1.B1[5].B2[0].B3[3].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[5].B2[0].B3[3]::M3 (work@small_top.u1.B1[5].B2[0].B3[3].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[5].B2[0].B3[3]) |vpiName:N3 @@ -35814,8 +35814,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[5].B2[0].B3[4].k - |vpiModule: - \_module: work@small_top.u1.B1[5].B2[0].B3[4]::M3 (work@small_top.u1.B1[5].B2[0].B3[4].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[5].B2[0].B3[4]::M3 (work@small_top.u1.B1[5].B2[0].B3[4].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[5].B2[0].B3[4]) |vpiName:N3 @@ -35842,8 +35842,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[5].B2[0].B3[5].k - |vpiModule: - \_module: work@small_top.u1.B1[5].B2[0].B3[5]::M3 (work@small_top.u1.B1[5].B2[0].B3[5].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[5].B2[0].B3[5]::M3 (work@small_top.u1.B1[5].B2[0].B3[5].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[5].B2[0].B3[5]) |vpiName:N3 @@ -35870,8 +35870,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[5].B2[0].B3[6].k - |vpiModule: - \_module: work@small_top.u1.B1[5].B2[0].B3[6]::M3 (work@small_top.u1.B1[5].B2[0].B3[6].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[5].B2[0].B3[6]::M3 (work@small_top.u1.B1[5].B2[0].B3[6].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[5].B2[0].B3[6]) |vpiName:N3 @@ -35898,8 +35898,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[5].B2[0].B3[7].k - |vpiModule: - \_module: work@small_top.u1.B1[5].B2[0].B3[7]::M3 (work@small_top.u1.B1[5].B2[0].B3[7].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[5].B2[0].B3[7]::M3 (work@small_top.u1.B1[5].B2[0].B3[7].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[5].B2[0].B3[7]) |vpiName:N3 @@ -35926,8 +35926,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[5].B2[0].B3[8].k - |vpiModule: - \_module: work@small_top.u1.B1[5].B2[0].B3[8]::M3 (work@small_top.u1.B1[5].B2[0].B3[8].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[5].B2[0].B3[8]::M3 (work@small_top.u1.B1[5].B2[0].B3[8].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[5].B2[0].B3[8]) |vpiName:N3 @@ -35954,8 +35954,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[5].B2[0].B3[9].k - |vpiModule: - \_module: work@small_top.u1.B1[5].B2[0].B3[9]::M3 (work@small_top.u1.B1[5].B2[0].B3[9].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[5].B2[0].B3[9]::M3 (work@small_top.u1.B1[5].B2[0].B3[9].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[5].B2[0].B3[9]) |vpiName:N3 @@ -35982,8 +35982,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:j |vpiFullName:work@small_top.u1.B1[5].B2[1].j - |vpiModule: - \_module: work@small_top.u1.B1[5].B2[1]::M2 (work@small_top.u1.B1[5].B2[1].N2), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:26:1, endln:26:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[5].B2[1]::M2 (work@small_top.u1.B1[5].B2[1].N2), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:26:1, endln:26:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[5].B2[1]) |vpiName:N2 @@ -36010,8 +36010,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[5].B2[1].B3[0].k - |vpiModule: - \_module: work@small_top.u1.B1[5].B2[1].B3[0]::M3 (work@small_top.u1.B1[5].B2[1].B3[0].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[5].B2[1].B3[0]::M3 (work@small_top.u1.B1[5].B2[1].B3[0].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[5].B2[1].B3[0]) |vpiName:N3 @@ -36038,8 +36038,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[5].B2[1].B3[1].k - |vpiModule: - \_module: work@small_top.u1.B1[5].B2[1].B3[1]::M3 (work@small_top.u1.B1[5].B2[1].B3[1].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[5].B2[1].B3[1]::M3 (work@small_top.u1.B1[5].B2[1].B3[1].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[5].B2[1].B3[1]) |vpiName:N3 @@ -36066,8 +36066,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[5].B2[1].B3[2].k - |vpiModule: - \_module: work@small_top.u1.B1[5].B2[1].B3[2]::M3 (work@small_top.u1.B1[5].B2[1].B3[2].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[5].B2[1].B3[2]::M3 (work@small_top.u1.B1[5].B2[1].B3[2].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[5].B2[1].B3[2]) |vpiName:N3 @@ -36094,8 +36094,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[5].B2[1].B3[3].k - |vpiModule: - \_module: work@small_top.u1.B1[5].B2[1].B3[3]::M3 (work@small_top.u1.B1[5].B2[1].B3[3].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[5].B2[1].B3[3]::M3 (work@small_top.u1.B1[5].B2[1].B3[3].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[5].B2[1].B3[3]) |vpiName:N3 @@ -36122,8 +36122,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[5].B2[1].B3[4].k - |vpiModule: - \_module: work@small_top.u1.B1[5].B2[1].B3[4]::M3 (work@small_top.u1.B1[5].B2[1].B3[4].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[5].B2[1].B3[4]::M3 (work@small_top.u1.B1[5].B2[1].B3[4].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[5].B2[1].B3[4]) |vpiName:N3 @@ -36150,8 +36150,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[5].B2[1].B3[5].k - |vpiModule: - \_module: work@small_top.u1.B1[5].B2[1].B3[5]::M3 (work@small_top.u1.B1[5].B2[1].B3[5].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[5].B2[1].B3[5]::M3 (work@small_top.u1.B1[5].B2[1].B3[5].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[5].B2[1].B3[5]) |vpiName:N3 @@ -36178,8 +36178,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[5].B2[1].B3[6].k - |vpiModule: - \_module: work@small_top.u1.B1[5].B2[1].B3[6]::M3 (work@small_top.u1.B1[5].B2[1].B3[6].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[5].B2[1].B3[6]::M3 (work@small_top.u1.B1[5].B2[1].B3[6].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[5].B2[1].B3[6]) |vpiName:N3 @@ -36206,8 +36206,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[5].B2[1].B3[7].k - |vpiModule: - \_module: work@small_top.u1.B1[5].B2[1].B3[7]::M3 (work@small_top.u1.B1[5].B2[1].B3[7].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[5].B2[1].B3[7]::M3 (work@small_top.u1.B1[5].B2[1].B3[7].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[5].B2[1].B3[7]) |vpiName:N3 @@ -36234,8 +36234,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[5].B2[1].B3[8].k - |vpiModule: - \_module: work@small_top.u1.B1[5].B2[1].B3[8]::M3 (work@small_top.u1.B1[5].B2[1].B3[8].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[5].B2[1].B3[8]::M3 (work@small_top.u1.B1[5].B2[1].B3[8].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[5].B2[1].B3[8]) |vpiName:N3 @@ -36262,8 +36262,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[5].B2[1].B3[9].k - |vpiModule: - \_module: work@small_top.u1.B1[5].B2[1].B3[9]::M3 (work@small_top.u1.B1[5].B2[1].B3[9].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[5].B2[1].B3[9]::M3 (work@small_top.u1.B1[5].B2[1].B3[9].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[5].B2[1].B3[9]) |vpiName:N3 @@ -36290,8 +36290,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:j |vpiFullName:work@small_top.u1.B1[5].B2[2].j - |vpiModule: - \_module: work@small_top.u1.B1[5].B2[2]::M2 (work@small_top.u1.B1[5].B2[2].N2), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:26:1, endln:26:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[5].B2[2]::M2 (work@small_top.u1.B1[5].B2[2].N2), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:26:1, endln:26:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[5].B2[2]) |vpiName:N2 @@ -36318,8 +36318,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[5].B2[2].B3[0].k - |vpiModule: - \_module: work@small_top.u1.B1[5].B2[2].B3[0]::M3 (work@small_top.u1.B1[5].B2[2].B3[0].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[5].B2[2].B3[0]::M3 (work@small_top.u1.B1[5].B2[2].B3[0].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[5].B2[2].B3[0]) |vpiName:N3 @@ -36346,8 +36346,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[5].B2[2].B3[1].k - |vpiModule: - \_module: work@small_top.u1.B1[5].B2[2].B3[1]::M3 (work@small_top.u1.B1[5].B2[2].B3[1].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[5].B2[2].B3[1]::M3 (work@small_top.u1.B1[5].B2[2].B3[1].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[5].B2[2].B3[1]) |vpiName:N3 @@ -36374,8 +36374,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[5].B2[2].B3[2].k - |vpiModule: - \_module: work@small_top.u1.B1[5].B2[2].B3[2]::M3 (work@small_top.u1.B1[5].B2[2].B3[2].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[5].B2[2].B3[2]::M3 (work@small_top.u1.B1[5].B2[2].B3[2].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[5].B2[2].B3[2]) |vpiName:N3 @@ -36402,8 +36402,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[5].B2[2].B3[3].k - |vpiModule: - \_module: work@small_top.u1.B1[5].B2[2].B3[3]::M3 (work@small_top.u1.B1[5].B2[2].B3[3].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[5].B2[2].B3[3]::M3 (work@small_top.u1.B1[5].B2[2].B3[3].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[5].B2[2].B3[3]) |vpiName:N3 @@ -36430,8 +36430,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[5].B2[2].B3[4].k - |vpiModule: - \_module: work@small_top.u1.B1[5].B2[2].B3[4]::M3 (work@small_top.u1.B1[5].B2[2].B3[4].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[5].B2[2].B3[4]::M3 (work@small_top.u1.B1[5].B2[2].B3[4].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[5].B2[2].B3[4]) |vpiName:N3 @@ -36458,8 +36458,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[5].B2[2].B3[5].k - |vpiModule: - \_module: work@small_top.u1.B1[5].B2[2].B3[5]::M3 (work@small_top.u1.B1[5].B2[2].B3[5].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[5].B2[2].B3[5]::M3 (work@small_top.u1.B1[5].B2[2].B3[5].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[5].B2[2].B3[5]) |vpiName:N3 @@ -36486,8 +36486,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[5].B2[2].B3[6].k - |vpiModule: - \_module: work@small_top.u1.B1[5].B2[2].B3[6]::M3 (work@small_top.u1.B1[5].B2[2].B3[6].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[5].B2[2].B3[6]::M3 (work@small_top.u1.B1[5].B2[2].B3[6].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[5].B2[2].B3[6]) |vpiName:N3 @@ -36514,8 +36514,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[5].B2[2].B3[7].k - |vpiModule: - \_module: work@small_top.u1.B1[5].B2[2].B3[7]::M3 (work@small_top.u1.B1[5].B2[2].B3[7].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[5].B2[2].B3[7]::M3 (work@small_top.u1.B1[5].B2[2].B3[7].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[5].B2[2].B3[7]) |vpiName:N3 @@ -36542,8 +36542,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[5].B2[2].B3[8].k - |vpiModule: - \_module: work@small_top.u1.B1[5].B2[2].B3[8]::M3 (work@small_top.u1.B1[5].B2[2].B3[8].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[5].B2[2].B3[8]::M3 (work@small_top.u1.B1[5].B2[2].B3[8].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[5].B2[2].B3[8]) |vpiName:N3 @@ -36570,8 +36570,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[5].B2[2].B3[9].k - |vpiModule: - \_module: work@small_top.u1.B1[5].B2[2].B3[9]::M3 (work@small_top.u1.B1[5].B2[2].B3[9].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[5].B2[2].B3[9]::M3 (work@small_top.u1.B1[5].B2[2].B3[9].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[5].B2[2].B3[9]) |vpiName:N3 @@ -36598,8 +36598,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:j |vpiFullName:work@small_top.u1.B1[5].B2[3].j - |vpiModule: - \_module: work@small_top.u1.B1[5].B2[3]::M2 (work@small_top.u1.B1[5].B2[3].N2), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:26:1, endln:26:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[5].B2[3]::M2 (work@small_top.u1.B1[5].B2[3].N2), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:26:1, endln:26:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[5].B2[3]) |vpiName:N2 @@ -36626,8 +36626,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[5].B2[3].B3[0].k - |vpiModule: - \_module: work@small_top.u1.B1[5].B2[3].B3[0]::M3 (work@small_top.u1.B1[5].B2[3].B3[0].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[5].B2[3].B3[0]::M3 (work@small_top.u1.B1[5].B2[3].B3[0].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[5].B2[3].B3[0]) |vpiName:N3 @@ -36654,8 +36654,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[5].B2[3].B3[1].k - |vpiModule: - \_module: work@small_top.u1.B1[5].B2[3].B3[1]::M3 (work@small_top.u1.B1[5].B2[3].B3[1].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[5].B2[3].B3[1]::M3 (work@small_top.u1.B1[5].B2[3].B3[1].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[5].B2[3].B3[1]) |vpiName:N3 @@ -36682,8 +36682,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[5].B2[3].B3[2].k - |vpiModule: - \_module: work@small_top.u1.B1[5].B2[3].B3[2]::M3 (work@small_top.u1.B1[5].B2[3].B3[2].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[5].B2[3].B3[2]::M3 (work@small_top.u1.B1[5].B2[3].B3[2].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[5].B2[3].B3[2]) |vpiName:N3 @@ -36710,8 +36710,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[5].B2[3].B3[3].k - |vpiModule: - \_module: work@small_top.u1.B1[5].B2[3].B3[3]::M3 (work@small_top.u1.B1[5].B2[3].B3[3].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[5].B2[3].B3[3]::M3 (work@small_top.u1.B1[5].B2[3].B3[3].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[5].B2[3].B3[3]) |vpiName:N3 @@ -36738,8 +36738,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[5].B2[3].B3[4].k - |vpiModule: - \_module: work@small_top.u1.B1[5].B2[3].B3[4]::M3 (work@small_top.u1.B1[5].B2[3].B3[4].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[5].B2[3].B3[4]::M3 (work@small_top.u1.B1[5].B2[3].B3[4].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[5].B2[3].B3[4]) |vpiName:N3 @@ -36766,8 +36766,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[5].B2[3].B3[5].k - |vpiModule: - \_module: work@small_top.u1.B1[5].B2[3].B3[5]::M3 (work@small_top.u1.B1[5].B2[3].B3[5].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[5].B2[3].B3[5]::M3 (work@small_top.u1.B1[5].B2[3].B3[5].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[5].B2[3].B3[5]) |vpiName:N3 @@ -36794,8 +36794,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[5].B2[3].B3[6].k - |vpiModule: - \_module: work@small_top.u1.B1[5].B2[3].B3[6]::M3 (work@small_top.u1.B1[5].B2[3].B3[6].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[5].B2[3].B3[6]::M3 (work@small_top.u1.B1[5].B2[3].B3[6].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[5].B2[3].B3[6]) |vpiName:N3 @@ -36822,8 +36822,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[5].B2[3].B3[7].k - |vpiModule: - \_module: work@small_top.u1.B1[5].B2[3].B3[7]::M3 (work@small_top.u1.B1[5].B2[3].B3[7].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[5].B2[3].B3[7]::M3 (work@small_top.u1.B1[5].B2[3].B3[7].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[5].B2[3].B3[7]) |vpiName:N3 @@ -36850,8 +36850,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[5].B2[3].B3[8].k - |vpiModule: - \_module: work@small_top.u1.B1[5].B2[3].B3[8]::M3 (work@small_top.u1.B1[5].B2[3].B3[8].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[5].B2[3].B3[8]::M3 (work@small_top.u1.B1[5].B2[3].B3[8].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[5].B2[3].B3[8]) |vpiName:N3 @@ -36878,8 +36878,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[5].B2[3].B3[9].k - |vpiModule: - \_module: work@small_top.u1.B1[5].B2[3].B3[9]::M3 (work@small_top.u1.B1[5].B2[3].B3[9].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[5].B2[3].B3[9]::M3 (work@small_top.u1.B1[5].B2[3].B3[9].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[5].B2[3].B3[9]) |vpiName:N3 @@ -36906,8 +36906,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:j |vpiFullName:work@small_top.u1.B1[5].B2[4].j - |vpiModule: - \_module: work@small_top.u1.B1[5].B2[4]::M2 (work@small_top.u1.B1[5].B2[4].N2), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:26:1, endln:26:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[5].B2[4]::M2 (work@small_top.u1.B1[5].B2[4].N2), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:26:1, endln:26:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[5].B2[4]) |vpiName:N2 @@ -36934,8 +36934,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[5].B2[4].B3[0].k - |vpiModule: - \_module: work@small_top.u1.B1[5].B2[4].B3[0]::M3 (work@small_top.u1.B1[5].B2[4].B3[0].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[5].B2[4].B3[0]::M3 (work@small_top.u1.B1[5].B2[4].B3[0].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[5].B2[4].B3[0]) |vpiName:N3 @@ -36962,8 +36962,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[5].B2[4].B3[1].k - |vpiModule: - \_module: work@small_top.u1.B1[5].B2[4].B3[1]::M3 (work@small_top.u1.B1[5].B2[4].B3[1].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[5].B2[4].B3[1]::M3 (work@small_top.u1.B1[5].B2[4].B3[1].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[5].B2[4].B3[1]) |vpiName:N3 @@ -36990,8 +36990,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[5].B2[4].B3[2].k - |vpiModule: - \_module: work@small_top.u1.B1[5].B2[4].B3[2]::M3 (work@small_top.u1.B1[5].B2[4].B3[2].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[5].B2[4].B3[2]::M3 (work@small_top.u1.B1[5].B2[4].B3[2].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[5].B2[4].B3[2]) |vpiName:N3 @@ -37018,8 +37018,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[5].B2[4].B3[3].k - |vpiModule: - \_module: work@small_top.u1.B1[5].B2[4].B3[3]::M3 (work@small_top.u1.B1[5].B2[4].B3[3].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[5].B2[4].B3[3]::M3 (work@small_top.u1.B1[5].B2[4].B3[3].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[5].B2[4].B3[3]) |vpiName:N3 @@ -37046,8 +37046,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[5].B2[4].B3[4].k - |vpiModule: - \_module: work@small_top.u1.B1[5].B2[4].B3[4]::M3 (work@small_top.u1.B1[5].B2[4].B3[4].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[5].B2[4].B3[4]::M3 (work@small_top.u1.B1[5].B2[4].B3[4].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[5].B2[4].B3[4]) |vpiName:N3 @@ -37074,8 +37074,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[5].B2[4].B3[5].k - |vpiModule: - \_module: work@small_top.u1.B1[5].B2[4].B3[5]::M3 (work@small_top.u1.B1[5].B2[4].B3[5].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[5].B2[4].B3[5]::M3 (work@small_top.u1.B1[5].B2[4].B3[5].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[5].B2[4].B3[5]) |vpiName:N3 @@ -37102,8 +37102,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[5].B2[4].B3[6].k - |vpiModule: - \_module: work@small_top.u1.B1[5].B2[4].B3[6]::M3 (work@small_top.u1.B1[5].B2[4].B3[6].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[5].B2[4].B3[6]::M3 (work@small_top.u1.B1[5].B2[4].B3[6].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[5].B2[4].B3[6]) |vpiName:N3 @@ -37130,8 +37130,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[5].B2[4].B3[7].k - |vpiModule: - \_module: work@small_top.u1.B1[5].B2[4].B3[7]::M3 (work@small_top.u1.B1[5].B2[4].B3[7].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[5].B2[4].B3[7]::M3 (work@small_top.u1.B1[5].B2[4].B3[7].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[5].B2[4].B3[7]) |vpiName:N3 @@ -37158,8 +37158,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[5].B2[4].B3[8].k - |vpiModule: - \_module: work@small_top.u1.B1[5].B2[4].B3[8]::M3 (work@small_top.u1.B1[5].B2[4].B3[8].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[5].B2[4].B3[8]::M3 (work@small_top.u1.B1[5].B2[4].B3[8].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[5].B2[4].B3[8]) |vpiName:N3 @@ -37186,8 +37186,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[5].B2[4].B3[9].k - |vpiModule: - \_module: work@small_top.u1.B1[5].B2[4].B3[9]::M3 (work@small_top.u1.B1[5].B2[4].B3[9].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[5].B2[4].B3[9]::M3 (work@small_top.u1.B1[5].B2[4].B3[9].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[5].B2[4].B3[9]) |vpiName:N3 @@ -37214,8 +37214,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:j |vpiFullName:work@small_top.u1.B1[5].B2[5].j - |vpiModule: - \_module: work@small_top.u1.B1[5].B2[5]::M2 (work@small_top.u1.B1[5].B2[5].N2), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:26:1, endln:26:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[5].B2[5]::M2 (work@small_top.u1.B1[5].B2[5].N2), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:26:1, endln:26:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[5].B2[5]) |vpiName:N2 @@ -37242,8 +37242,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[5].B2[5].B3[0].k - |vpiModule: - \_module: work@small_top.u1.B1[5].B2[5].B3[0]::M3 (work@small_top.u1.B1[5].B2[5].B3[0].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[5].B2[5].B3[0]::M3 (work@small_top.u1.B1[5].B2[5].B3[0].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[5].B2[5].B3[0]) |vpiName:N3 @@ -37270,8 +37270,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[5].B2[5].B3[1].k - |vpiModule: - \_module: work@small_top.u1.B1[5].B2[5].B3[1]::M3 (work@small_top.u1.B1[5].B2[5].B3[1].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[5].B2[5].B3[1]::M3 (work@small_top.u1.B1[5].B2[5].B3[1].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[5].B2[5].B3[1]) |vpiName:N3 @@ -37298,8 +37298,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[5].B2[5].B3[2].k - |vpiModule: - \_module: work@small_top.u1.B1[5].B2[5].B3[2]::M3 (work@small_top.u1.B1[5].B2[5].B3[2].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[5].B2[5].B3[2]::M3 (work@small_top.u1.B1[5].B2[5].B3[2].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[5].B2[5].B3[2]) |vpiName:N3 @@ -37326,8 +37326,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[5].B2[5].B3[3].k - |vpiModule: - \_module: work@small_top.u1.B1[5].B2[5].B3[3]::M3 (work@small_top.u1.B1[5].B2[5].B3[3].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[5].B2[5].B3[3]::M3 (work@small_top.u1.B1[5].B2[5].B3[3].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[5].B2[5].B3[3]) |vpiName:N3 @@ -37354,8 +37354,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[5].B2[5].B3[4].k - |vpiModule: - \_module: work@small_top.u1.B1[5].B2[5].B3[4]::M3 (work@small_top.u1.B1[5].B2[5].B3[4].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[5].B2[5].B3[4]::M3 (work@small_top.u1.B1[5].B2[5].B3[4].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[5].B2[5].B3[4]) |vpiName:N3 @@ -37382,8 +37382,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[5].B2[5].B3[5].k - |vpiModule: - \_module: work@small_top.u1.B1[5].B2[5].B3[5]::M3 (work@small_top.u1.B1[5].B2[5].B3[5].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[5].B2[5].B3[5]::M3 (work@small_top.u1.B1[5].B2[5].B3[5].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[5].B2[5].B3[5]) |vpiName:N3 @@ -37410,8 +37410,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[5].B2[5].B3[6].k - |vpiModule: - \_module: work@small_top.u1.B1[5].B2[5].B3[6]::M3 (work@small_top.u1.B1[5].B2[5].B3[6].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[5].B2[5].B3[6]::M3 (work@small_top.u1.B1[5].B2[5].B3[6].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[5].B2[5].B3[6]) |vpiName:N3 @@ -37438,8 +37438,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[5].B2[5].B3[7].k - |vpiModule: - \_module: work@small_top.u1.B1[5].B2[5].B3[7]::M3 (work@small_top.u1.B1[5].B2[5].B3[7].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[5].B2[5].B3[7]::M3 (work@small_top.u1.B1[5].B2[5].B3[7].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[5].B2[5].B3[7]) |vpiName:N3 @@ -37466,8 +37466,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[5].B2[5].B3[8].k - |vpiModule: - \_module: work@small_top.u1.B1[5].B2[5].B3[8]::M3 (work@small_top.u1.B1[5].B2[5].B3[8].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[5].B2[5].B3[8]::M3 (work@small_top.u1.B1[5].B2[5].B3[8].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[5].B2[5].B3[8]) |vpiName:N3 @@ -37494,8 +37494,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[5].B2[5].B3[9].k - |vpiModule: - \_module: work@small_top.u1.B1[5].B2[5].B3[9]::M3 (work@small_top.u1.B1[5].B2[5].B3[9].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[5].B2[5].B3[9]::M3 (work@small_top.u1.B1[5].B2[5].B3[9].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[5].B2[5].B3[9]) |vpiName:N3 @@ -37522,8 +37522,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:j |vpiFullName:work@small_top.u1.B1[5].B2[6].j - |vpiModule: - \_module: work@small_top.u1.B1[5].B2[6]::M2 (work@small_top.u1.B1[5].B2[6].N2), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:26:1, endln:26:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[5].B2[6]::M2 (work@small_top.u1.B1[5].B2[6].N2), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:26:1, endln:26:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[5].B2[6]) |vpiName:N2 @@ -37550,8 +37550,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[5].B2[6].B3[0].k - |vpiModule: - \_module: work@small_top.u1.B1[5].B2[6].B3[0]::M3 (work@small_top.u1.B1[5].B2[6].B3[0].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[5].B2[6].B3[0]::M3 (work@small_top.u1.B1[5].B2[6].B3[0].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[5].B2[6].B3[0]) |vpiName:N3 @@ -37578,8 +37578,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[5].B2[6].B3[1].k - |vpiModule: - \_module: work@small_top.u1.B1[5].B2[6].B3[1]::M3 (work@small_top.u1.B1[5].B2[6].B3[1].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[5].B2[6].B3[1]::M3 (work@small_top.u1.B1[5].B2[6].B3[1].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[5].B2[6].B3[1]) |vpiName:N3 @@ -37606,8 +37606,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[5].B2[6].B3[2].k - |vpiModule: - \_module: work@small_top.u1.B1[5].B2[6].B3[2]::M3 (work@small_top.u1.B1[5].B2[6].B3[2].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[5].B2[6].B3[2]::M3 (work@small_top.u1.B1[5].B2[6].B3[2].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[5].B2[6].B3[2]) |vpiName:N3 @@ -37634,8 +37634,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[5].B2[6].B3[3].k - |vpiModule: - \_module: work@small_top.u1.B1[5].B2[6].B3[3]::M3 (work@small_top.u1.B1[5].B2[6].B3[3].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[5].B2[6].B3[3]::M3 (work@small_top.u1.B1[5].B2[6].B3[3].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[5].B2[6].B3[3]) |vpiName:N3 @@ -37662,8 +37662,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[5].B2[6].B3[4].k - |vpiModule: - \_module: work@small_top.u1.B1[5].B2[6].B3[4]::M3 (work@small_top.u1.B1[5].B2[6].B3[4].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[5].B2[6].B3[4]::M3 (work@small_top.u1.B1[5].B2[6].B3[4].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[5].B2[6].B3[4]) |vpiName:N3 @@ -37690,8 +37690,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[5].B2[6].B3[5].k - |vpiModule: - \_module: work@small_top.u1.B1[5].B2[6].B3[5]::M3 (work@small_top.u1.B1[5].B2[6].B3[5].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[5].B2[6].B3[5]::M3 (work@small_top.u1.B1[5].B2[6].B3[5].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[5].B2[6].B3[5]) |vpiName:N3 @@ -37718,8 +37718,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[5].B2[6].B3[6].k - |vpiModule: - \_module: work@small_top.u1.B1[5].B2[6].B3[6]::M3 (work@small_top.u1.B1[5].B2[6].B3[6].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[5].B2[6].B3[6]::M3 (work@small_top.u1.B1[5].B2[6].B3[6].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[5].B2[6].B3[6]) |vpiName:N3 @@ -37746,8 +37746,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[5].B2[6].B3[7].k - |vpiModule: - \_module: work@small_top.u1.B1[5].B2[6].B3[7]::M3 (work@small_top.u1.B1[5].B2[6].B3[7].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[5].B2[6].B3[7]::M3 (work@small_top.u1.B1[5].B2[6].B3[7].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[5].B2[6].B3[7]) |vpiName:N3 @@ -37774,8 +37774,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[5].B2[6].B3[8].k - |vpiModule: - \_module: work@small_top.u1.B1[5].B2[6].B3[8]::M3 (work@small_top.u1.B1[5].B2[6].B3[8].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[5].B2[6].B3[8]::M3 (work@small_top.u1.B1[5].B2[6].B3[8].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[5].B2[6].B3[8]) |vpiName:N3 @@ -37802,8 +37802,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[5].B2[6].B3[9].k - |vpiModule: - \_module: work@small_top.u1.B1[5].B2[6].B3[9]::M3 (work@small_top.u1.B1[5].B2[6].B3[9].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[5].B2[6].B3[9]::M3 (work@small_top.u1.B1[5].B2[6].B3[9].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[5].B2[6].B3[9]) |vpiName:N3 @@ -37830,8 +37830,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:j |vpiFullName:work@small_top.u1.B1[5].B2[7].j - |vpiModule: - \_module: work@small_top.u1.B1[5].B2[7]::M2 (work@small_top.u1.B1[5].B2[7].N2), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:26:1, endln:26:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[5].B2[7]::M2 (work@small_top.u1.B1[5].B2[7].N2), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:26:1, endln:26:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[5].B2[7]) |vpiName:N2 @@ -37858,8 +37858,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[5].B2[7].B3[0].k - |vpiModule: - \_module: work@small_top.u1.B1[5].B2[7].B3[0]::M3 (work@small_top.u1.B1[5].B2[7].B3[0].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[5].B2[7].B3[0]::M3 (work@small_top.u1.B1[5].B2[7].B3[0].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[5].B2[7].B3[0]) |vpiName:N3 @@ -37886,8 +37886,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[5].B2[7].B3[1].k - |vpiModule: - \_module: work@small_top.u1.B1[5].B2[7].B3[1]::M3 (work@small_top.u1.B1[5].B2[7].B3[1].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[5].B2[7].B3[1]::M3 (work@small_top.u1.B1[5].B2[7].B3[1].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[5].B2[7].B3[1]) |vpiName:N3 @@ -37914,8 +37914,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[5].B2[7].B3[2].k - |vpiModule: - \_module: work@small_top.u1.B1[5].B2[7].B3[2]::M3 (work@small_top.u1.B1[5].B2[7].B3[2].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[5].B2[7].B3[2]::M3 (work@small_top.u1.B1[5].B2[7].B3[2].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[5].B2[7].B3[2]) |vpiName:N3 @@ -37942,8 +37942,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[5].B2[7].B3[3].k - |vpiModule: - \_module: work@small_top.u1.B1[5].B2[7].B3[3]::M3 (work@small_top.u1.B1[5].B2[7].B3[3].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[5].B2[7].B3[3]::M3 (work@small_top.u1.B1[5].B2[7].B3[3].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[5].B2[7].B3[3]) |vpiName:N3 @@ -37970,8 +37970,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[5].B2[7].B3[4].k - |vpiModule: - \_module: work@small_top.u1.B1[5].B2[7].B3[4]::M3 (work@small_top.u1.B1[5].B2[7].B3[4].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[5].B2[7].B3[4]::M3 (work@small_top.u1.B1[5].B2[7].B3[4].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[5].B2[7].B3[4]) |vpiName:N3 @@ -37998,8 +37998,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[5].B2[7].B3[5].k - |vpiModule: - \_module: work@small_top.u1.B1[5].B2[7].B3[5]::M3 (work@small_top.u1.B1[5].B2[7].B3[5].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[5].B2[7].B3[5]::M3 (work@small_top.u1.B1[5].B2[7].B3[5].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[5].B2[7].B3[5]) |vpiName:N3 @@ -38026,8 +38026,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[5].B2[7].B3[6].k - |vpiModule: - \_module: work@small_top.u1.B1[5].B2[7].B3[6]::M3 (work@small_top.u1.B1[5].B2[7].B3[6].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[5].B2[7].B3[6]::M3 (work@small_top.u1.B1[5].B2[7].B3[6].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[5].B2[7].B3[6]) |vpiName:N3 @@ -38054,8 +38054,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[5].B2[7].B3[7].k - |vpiModule: - \_module: work@small_top.u1.B1[5].B2[7].B3[7]::M3 (work@small_top.u1.B1[5].B2[7].B3[7].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[5].B2[7].B3[7]::M3 (work@small_top.u1.B1[5].B2[7].B3[7].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[5].B2[7].B3[7]) |vpiName:N3 @@ -38082,8 +38082,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[5].B2[7].B3[8].k - |vpiModule: - \_module: work@small_top.u1.B1[5].B2[7].B3[8]::M3 (work@small_top.u1.B1[5].B2[7].B3[8].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[5].B2[7].B3[8]::M3 (work@small_top.u1.B1[5].B2[7].B3[8].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[5].B2[7].B3[8]) |vpiName:N3 @@ -38110,8 +38110,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[5].B2[7].B3[9].k - |vpiModule: - \_module: work@small_top.u1.B1[5].B2[7].B3[9]::M3 (work@small_top.u1.B1[5].B2[7].B3[9].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[5].B2[7].B3[9]::M3 (work@small_top.u1.B1[5].B2[7].B3[9].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[5].B2[7].B3[9]) |vpiName:N3 @@ -38138,8 +38138,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:j |vpiFullName:work@small_top.u1.B1[5].B2[8].j - |vpiModule: - \_module: work@small_top.u1.B1[5].B2[8]::M2 (work@small_top.u1.B1[5].B2[8].N2), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:26:1, endln:26:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[5].B2[8]::M2 (work@small_top.u1.B1[5].B2[8].N2), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:26:1, endln:26:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[5].B2[8]) |vpiName:N2 @@ -38166,8 +38166,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[5].B2[8].B3[0].k - |vpiModule: - \_module: work@small_top.u1.B1[5].B2[8].B3[0]::M3 (work@small_top.u1.B1[5].B2[8].B3[0].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[5].B2[8].B3[0]::M3 (work@small_top.u1.B1[5].B2[8].B3[0].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[5].B2[8].B3[0]) |vpiName:N3 @@ -38194,8 +38194,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[5].B2[8].B3[1].k - |vpiModule: - \_module: work@small_top.u1.B1[5].B2[8].B3[1]::M3 (work@small_top.u1.B1[5].B2[8].B3[1].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[5].B2[8].B3[1]::M3 (work@small_top.u1.B1[5].B2[8].B3[1].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[5].B2[8].B3[1]) |vpiName:N3 @@ -38222,8 +38222,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[5].B2[8].B3[2].k - |vpiModule: - \_module: work@small_top.u1.B1[5].B2[8].B3[2]::M3 (work@small_top.u1.B1[5].B2[8].B3[2].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[5].B2[8].B3[2]::M3 (work@small_top.u1.B1[5].B2[8].B3[2].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[5].B2[8].B3[2]) |vpiName:N3 @@ -38250,8 +38250,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[5].B2[8].B3[3].k - |vpiModule: - \_module: work@small_top.u1.B1[5].B2[8].B3[3]::M3 (work@small_top.u1.B1[5].B2[8].B3[3].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[5].B2[8].B3[3]::M3 (work@small_top.u1.B1[5].B2[8].B3[3].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[5].B2[8].B3[3]) |vpiName:N3 @@ -38278,8 +38278,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[5].B2[8].B3[4].k - |vpiModule: - \_module: work@small_top.u1.B1[5].B2[8].B3[4]::M3 (work@small_top.u1.B1[5].B2[8].B3[4].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[5].B2[8].B3[4]::M3 (work@small_top.u1.B1[5].B2[8].B3[4].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[5].B2[8].B3[4]) |vpiName:N3 @@ -38306,8 +38306,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[5].B2[8].B3[5].k - |vpiModule: - \_module: work@small_top.u1.B1[5].B2[8].B3[5]::M3 (work@small_top.u1.B1[5].B2[8].B3[5].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[5].B2[8].B3[5]::M3 (work@small_top.u1.B1[5].B2[8].B3[5].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[5].B2[8].B3[5]) |vpiName:N3 @@ -38334,8 +38334,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[5].B2[8].B3[6].k - |vpiModule: - \_module: work@small_top.u1.B1[5].B2[8].B3[6]::M3 (work@small_top.u1.B1[5].B2[8].B3[6].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[5].B2[8].B3[6]::M3 (work@small_top.u1.B1[5].B2[8].B3[6].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[5].B2[8].B3[6]) |vpiName:N3 @@ -38362,8 +38362,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[5].B2[8].B3[7].k - |vpiModule: - \_module: work@small_top.u1.B1[5].B2[8].B3[7]::M3 (work@small_top.u1.B1[5].B2[8].B3[7].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[5].B2[8].B3[7]::M3 (work@small_top.u1.B1[5].B2[8].B3[7].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[5].B2[8].B3[7]) |vpiName:N3 @@ -38390,8 +38390,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[5].B2[8].B3[8].k - |vpiModule: - \_module: work@small_top.u1.B1[5].B2[8].B3[8]::M3 (work@small_top.u1.B1[5].B2[8].B3[8].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[5].B2[8].B3[8]::M3 (work@small_top.u1.B1[5].B2[8].B3[8].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[5].B2[8].B3[8]) |vpiName:N3 @@ -38418,8 +38418,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[5].B2[8].B3[9].k - |vpiModule: - \_module: work@small_top.u1.B1[5].B2[8].B3[9]::M3 (work@small_top.u1.B1[5].B2[8].B3[9].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[5].B2[8].B3[9]::M3 (work@small_top.u1.B1[5].B2[8].B3[9].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[5].B2[8].B3[9]) |vpiName:N3 @@ -38446,8 +38446,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:j |vpiFullName:work@small_top.u1.B1[5].B2[9].j - |vpiModule: - \_module: work@small_top.u1.B1[5].B2[9]::M2 (work@small_top.u1.B1[5].B2[9].N2), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:26:1, endln:26:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[5].B2[9]::M2 (work@small_top.u1.B1[5].B2[9].N2), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:26:1, endln:26:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[5].B2[9]) |vpiName:N2 @@ -38474,8 +38474,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[5].B2[9].B3[0].k - |vpiModule: - \_module: work@small_top.u1.B1[5].B2[9].B3[0]::M3 (work@small_top.u1.B1[5].B2[9].B3[0].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[5].B2[9].B3[0]::M3 (work@small_top.u1.B1[5].B2[9].B3[0].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[5].B2[9].B3[0]) |vpiName:N3 @@ -38502,8 +38502,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[5].B2[9].B3[1].k - |vpiModule: - \_module: work@small_top.u1.B1[5].B2[9].B3[1]::M3 (work@small_top.u1.B1[5].B2[9].B3[1].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[5].B2[9].B3[1]::M3 (work@small_top.u1.B1[5].B2[9].B3[1].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[5].B2[9].B3[1]) |vpiName:N3 @@ -38530,8 +38530,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[5].B2[9].B3[2].k - |vpiModule: - \_module: work@small_top.u1.B1[5].B2[9].B3[2]::M3 (work@small_top.u1.B1[5].B2[9].B3[2].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[5].B2[9].B3[2]::M3 (work@small_top.u1.B1[5].B2[9].B3[2].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[5].B2[9].B3[2]) |vpiName:N3 @@ -38558,8 +38558,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[5].B2[9].B3[3].k - |vpiModule: - \_module: work@small_top.u1.B1[5].B2[9].B3[3]::M3 (work@small_top.u1.B1[5].B2[9].B3[3].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[5].B2[9].B3[3]::M3 (work@small_top.u1.B1[5].B2[9].B3[3].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[5].B2[9].B3[3]) |vpiName:N3 @@ -38586,8 +38586,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[5].B2[9].B3[4].k - |vpiModule: - \_module: work@small_top.u1.B1[5].B2[9].B3[4]::M3 (work@small_top.u1.B1[5].B2[9].B3[4].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[5].B2[9].B3[4]::M3 (work@small_top.u1.B1[5].B2[9].B3[4].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[5].B2[9].B3[4]) |vpiName:N3 @@ -38614,8 +38614,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[5].B2[9].B3[5].k - |vpiModule: - \_module: work@small_top.u1.B1[5].B2[9].B3[5]::M3 (work@small_top.u1.B1[5].B2[9].B3[5].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[5].B2[9].B3[5]::M3 (work@small_top.u1.B1[5].B2[9].B3[5].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[5].B2[9].B3[5]) |vpiName:N3 @@ -38642,8 +38642,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[5].B2[9].B3[6].k - |vpiModule: - \_module: work@small_top.u1.B1[5].B2[9].B3[6]::M3 (work@small_top.u1.B1[5].B2[9].B3[6].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[5].B2[9].B3[6]::M3 (work@small_top.u1.B1[5].B2[9].B3[6].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[5].B2[9].B3[6]) |vpiName:N3 @@ -38670,8 +38670,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[5].B2[9].B3[7].k - |vpiModule: - \_module: work@small_top.u1.B1[5].B2[9].B3[7]::M3 (work@small_top.u1.B1[5].B2[9].B3[7].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[5].B2[9].B3[7]::M3 (work@small_top.u1.B1[5].B2[9].B3[7].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[5].B2[9].B3[7]) |vpiName:N3 @@ -38698,8 +38698,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[5].B2[9].B3[8].k - |vpiModule: - \_module: work@small_top.u1.B1[5].B2[9].B3[8]::M3 (work@small_top.u1.B1[5].B2[9].B3[8].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[5].B2[9].B3[8]::M3 (work@small_top.u1.B1[5].B2[9].B3[8].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[5].B2[9].B3[8]) |vpiName:N3 @@ -38726,8 +38726,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[5].B2[9].B3[9].k - |vpiModule: - \_module: work@small_top.u1.B1[5].B2[9].B3[9]::M3 (work@small_top.u1.B1[5].B2[9].B3[9].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[5].B2[9].B3[9]::M3 (work@small_top.u1.B1[5].B2[9].B3[9].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[5].B2[9].B3[9]) |vpiName:N3 @@ -38765,8 +38765,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:m |vpiFullName:work@small_top.u1.B1[5].B4.B5[0].m - |vpiModule: - \_module: work@small_top.u1.B1[5].B4.B5[0]::M4 (work@small_top.u1.B1[5].B4.B5[0].N4), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:46:1, endln:46:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[5].B4.B5[0]::M4 (work@small_top.u1.B1[5].B4.B5[0].N4), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:46:1, endln:46:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[5].B4.B5[0]) |vpiName:N4 @@ -38793,8 +38793,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:m |vpiFullName:work@small_top.u1.B1[5].B4.B5[1].m - |vpiModule: - \_module: work@small_top.u1.B1[5].B4.B5[1]::M4 (work@small_top.u1.B1[5].B4.B5[1].N4), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:46:1, endln:46:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[5].B4.B5[1]::M4 (work@small_top.u1.B1[5].B4.B5[1].N4), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:46:1, endln:46:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[5].B4.B5[1]) |vpiName:N4 @@ -38821,8 +38821,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:m |vpiFullName:work@small_top.u1.B1[5].B4.B5[2].m - |vpiModule: - \_module: work@small_top.u1.B1[5].B4.B5[2]::M4 (work@small_top.u1.B1[5].B4.B5[2].N4), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:46:1, endln:46:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[5].B4.B5[2]::M4 (work@small_top.u1.B1[5].B4.B5[2].N4), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:46:1, endln:46:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[5].B4.B5[2]) |vpiName:N4 @@ -38849,8 +38849,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:m |vpiFullName:work@small_top.u1.B1[5].B4.B5[3].m - |vpiModule: - \_module: work@small_top.u1.B1[5].B4.B5[3]::M4 (work@small_top.u1.B1[5].B4.B5[3].N4), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:46:1, endln:46:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[5].B4.B5[3]::M4 (work@small_top.u1.B1[5].B4.B5[3].N4), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:46:1, endln:46:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[5].B4.B5[3]) |vpiName:N4 @@ -38877,8 +38877,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:m |vpiFullName:work@small_top.u1.B1[5].B4.B5[4].m - |vpiModule: - \_module: work@small_top.u1.B1[5].B4.B5[4]::M4 (work@small_top.u1.B1[5].B4.B5[4].N4), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:46:1, endln:46:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[5].B4.B5[4]::M4 (work@small_top.u1.B1[5].B4.B5[4].N4), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:46:1, endln:46:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[5].B4.B5[4]) |vpiName:N4 @@ -38905,8 +38905,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:m |vpiFullName:work@small_top.u1.B1[5].B4.B5[5].m - |vpiModule: - \_module: work@small_top.u1.B1[5].B4.B5[5]::M4 (work@small_top.u1.B1[5].B4.B5[5].N4), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:46:1, endln:46:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[5].B4.B5[5]::M4 (work@small_top.u1.B1[5].B4.B5[5].N4), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:46:1, endln:46:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[5].B4.B5[5]) |vpiName:N4 @@ -38933,8 +38933,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:m |vpiFullName:work@small_top.u1.B1[5].B4.B5[6].m - |vpiModule: - \_module: work@small_top.u1.B1[5].B4.B5[6]::M4 (work@small_top.u1.B1[5].B4.B5[6].N4), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:46:1, endln:46:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[5].B4.B5[6]::M4 (work@small_top.u1.B1[5].B4.B5[6].N4), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:46:1, endln:46:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[5].B4.B5[6]) |vpiName:N4 @@ -38961,8 +38961,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:m |vpiFullName:work@small_top.u1.B1[5].B4.B5[7].m - |vpiModule: - \_module: work@small_top.u1.B1[5].B4.B5[7]::M4 (work@small_top.u1.B1[5].B4.B5[7].N4), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:46:1, endln:46:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[5].B4.B5[7]::M4 (work@small_top.u1.B1[5].B4.B5[7].N4), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:46:1, endln:46:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[5].B4.B5[7]) |vpiName:N4 @@ -38989,8 +38989,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:m |vpiFullName:work@small_top.u1.B1[5].B4.B5[8].m - |vpiModule: - \_module: work@small_top.u1.B1[5].B4.B5[8]::M4 (work@small_top.u1.B1[5].B4.B5[8].N4), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:46:1, endln:46:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[5].B4.B5[8]::M4 (work@small_top.u1.B1[5].B4.B5[8].N4), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:46:1, endln:46:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[5].B4.B5[8]) |vpiName:N4 @@ -39017,8 +39017,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:m |vpiFullName:work@small_top.u1.B1[5].B4.B5[9].m - |vpiModule: - \_module: work@small_top.u1.B1[5].B4.B5[9]::M4 (work@small_top.u1.B1[5].B4.B5[9].N4), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:46:1, endln:46:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[5].B4.B5[9]::M4 (work@small_top.u1.B1[5].B4.B5[9].N4), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:46:1, endln:46:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[5].B4.B5[9]) |vpiName:N4 @@ -39027,7 +39027,7 @@ design: (work@bottom1) |vpiGenScopeArray: \_gen_scope_array: (work@small_top.u1.B1[6]), line:17:1, endln:51:4 |vpiParent: - \_module: work@small_test (work@small_top.u1), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:2:4, endln:2:29 + \_module_inst: work@small_test (work@small_top.u1), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:2:4, endln:2:29 |vpiName:B1[6] |vpiFullName:work@small_top.u1.B1[6] |vpiGenScope: @@ -39045,8 +39045,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:i |vpiFullName:work@small_top.u1.B1[6].i - |vpiModule: - \_module: work@small_top.u1.B1[6]::M1 (work@small_top.u1.B1[6].N1), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:20:1, endln:20:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[6]::M1 (work@small_top.u1.B1[6].N1), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:20:1, endln:20:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[6]) |vpiName:N1 @@ -39073,8 +39073,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:j |vpiFullName:work@small_top.u1.B1[6].B2[0].j - |vpiModule: - \_module: work@small_top.u1.B1[6].B2[0]::M2 (work@small_top.u1.B1[6].B2[0].N2), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:26:1, endln:26:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[6].B2[0]::M2 (work@small_top.u1.B1[6].B2[0].N2), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:26:1, endln:26:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[6].B2[0]) |vpiName:N2 @@ -39101,8 +39101,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[6].B2[0].B3[0].k - |vpiModule: - \_module: work@small_top.u1.B1[6].B2[0].B3[0]::M3 (work@small_top.u1.B1[6].B2[0].B3[0].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[6].B2[0].B3[0]::M3 (work@small_top.u1.B1[6].B2[0].B3[0].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[6].B2[0].B3[0]) |vpiName:N3 @@ -39129,8 +39129,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[6].B2[0].B3[1].k - |vpiModule: - \_module: work@small_top.u1.B1[6].B2[0].B3[1]::M3 (work@small_top.u1.B1[6].B2[0].B3[1].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[6].B2[0].B3[1]::M3 (work@small_top.u1.B1[6].B2[0].B3[1].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[6].B2[0].B3[1]) |vpiName:N3 @@ -39157,8 +39157,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[6].B2[0].B3[2].k - |vpiModule: - \_module: work@small_top.u1.B1[6].B2[0].B3[2]::M3 (work@small_top.u1.B1[6].B2[0].B3[2].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[6].B2[0].B3[2]::M3 (work@small_top.u1.B1[6].B2[0].B3[2].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[6].B2[0].B3[2]) |vpiName:N3 @@ -39185,8 +39185,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[6].B2[0].B3[3].k - |vpiModule: - \_module: work@small_top.u1.B1[6].B2[0].B3[3]::M3 (work@small_top.u1.B1[6].B2[0].B3[3].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[6].B2[0].B3[3]::M3 (work@small_top.u1.B1[6].B2[0].B3[3].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[6].B2[0].B3[3]) |vpiName:N3 @@ -39213,8 +39213,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[6].B2[0].B3[4].k - |vpiModule: - \_module: work@small_top.u1.B1[6].B2[0].B3[4]::M3 (work@small_top.u1.B1[6].B2[0].B3[4].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[6].B2[0].B3[4]::M3 (work@small_top.u1.B1[6].B2[0].B3[4].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[6].B2[0].B3[4]) |vpiName:N3 @@ -39241,8 +39241,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[6].B2[0].B3[5].k - |vpiModule: - \_module: work@small_top.u1.B1[6].B2[0].B3[5]::M3 (work@small_top.u1.B1[6].B2[0].B3[5].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[6].B2[0].B3[5]::M3 (work@small_top.u1.B1[6].B2[0].B3[5].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[6].B2[0].B3[5]) |vpiName:N3 @@ -39269,8 +39269,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[6].B2[0].B3[6].k - |vpiModule: - \_module: work@small_top.u1.B1[6].B2[0].B3[6]::M3 (work@small_top.u1.B1[6].B2[0].B3[6].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[6].B2[0].B3[6]::M3 (work@small_top.u1.B1[6].B2[0].B3[6].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[6].B2[0].B3[6]) |vpiName:N3 @@ -39297,8 +39297,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[6].B2[0].B3[7].k - |vpiModule: - \_module: work@small_top.u1.B1[6].B2[0].B3[7]::M3 (work@small_top.u1.B1[6].B2[0].B3[7].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[6].B2[0].B3[7]::M3 (work@small_top.u1.B1[6].B2[0].B3[7].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[6].B2[0].B3[7]) |vpiName:N3 @@ -39325,8 +39325,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[6].B2[0].B3[8].k - |vpiModule: - \_module: work@small_top.u1.B1[6].B2[0].B3[8]::M3 (work@small_top.u1.B1[6].B2[0].B3[8].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[6].B2[0].B3[8]::M3 (work@small_top.u1.B1[6].B2[0].B3[8].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[6].B2[0].B3[8]) |vpiName:N3 @@ -39353,8 +39353,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[6].B2[0].B3[9].k - |vpiModule: - \_module: work@small_top.u1.B1[6].B2[0].B3[9]::M3 (work@small_top.u1.B1[6].B2[0].B3[9].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[6].B2[0].B3[9]::M3 (work@small_top.u1.B1[6].B2[0].B3[9].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[6].B2[0].B3[9]) |vpiName:N3 @@ -39381,8 +39381,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:j |vpiFullName:work@small_top.u1.B1[6].B2[1].j - |vpiModule: - \_module: work@small_top.u1.B1[6].B2[1]::M2 (work@small_top.u1.B1[6].B2[1].N2), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:26:1, endln:26:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[6].B2[1]::M2 (work@small_top.u1.B1[6].B2[1].N2), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:26:1, endln:26:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[6].B2[1]) |vpiName:N2 @@ -39409,8 +39409,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[6].B2[1].B3[0].k - |vpiModule: - \_module: work@small_top.u1.B1[6].B2[1].B3[0]::M3 (work@small_top.u1.B1[6].B2[1].B3[0].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[6].B2[1].B3[0]::M3 (work@small_top.u1.B1[6].B2[1].B3[0].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[6].B2[1].B3[0]) |vpiName:N3 @@ -39437,8 +39437,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[6].B2[1].B3[1].k - |vpiModule: - \_module: work@small_top.u1.B1[6].B2[1].B3[1]::M3 (work@small_top.u1.B1[6].B2[1].B3[1].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[6].B2[1].B3[1]::M3 (work@small_top.u1.B1[6].B2[1].B3[1].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[6].B2[1].B3[1]) |vpiName:N3 @@ -39465,8 +39465,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[6].B2[1].B3[2].k - |vpiModule: - \_module: work@small_top.u1.B1[6].B2[1].B3[2]::M3 (work@small_top.u1.B1[6].B2[1].B3[2].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[6].B2[1].B3[2]::M3 (work@small_top.u1.B1[6].B2[1].B3[2].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[6].B2[1].B3[2]) |vpiName:N3 @@ -39493,8 +39493,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[6].B2[1].B3[3].k - |vpiModule: - \_module: work@small_top.u1.B1[6].B2[1].B3[3]::M3 (work@small_top.u1.B1[6].B2[1].B3[3].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[6].B2[1].B3[3]::M3 (work@small_top.u1.B1[6].B2[1].B3[3].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[6].B2[1].B3[3]) |vpiName:N3 @@ -39521,8 +39521,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[6].B2[1].B3[4].k - |vpiModule: - \_module: work@small_top.u1.B1[6].B2[1].B3[4]::M3 (work@small_top.u1.B1[6].B2[1].B3[4].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[6].B2[1].B3[4]::M3 (work@small_top.u1.B1[6].B2[1].B3[4].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[6].B2[1].B3[4]) |vpiName:N3 @@ -39549,8 +39549,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[6].B2[1].B3[5].k - |vpiModule: - \_module: work@small_top.u1.B1[6].B2[1].B3[5]::M3 (work@small_top.u1.B1[6].B2[1].B3[5].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[6].B2[1].B3[5]::M3 (work@small_top.u1.B1[6].B2[1].B3[5].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[6].B2[1].B3[5]) |vpiName:N3 @@ -39577,8 +39577,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[6].B2[1].B3[6].k - |vpiModule: - \_module: work@small_top.u1.B1[6].B2[1].B3[6]::M3 (work@small_top.u1.B1[6].B2[1].B3[6].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[6].B2[1].B3[6]::M3 (work@small_top.u1.B1[6].B2[1].B3[6].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[6].B2[1].B3[6]) |vpiName:N3 @@ -39605,8 +39605,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[6].B2[1].B3[7].k - |vpiModule: - \_module: work@small_top.u1.B1[6].B2[1].B3[7]::M3 (work@small_top.u1.B1[6].B2[1].B3[7].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[6].B2[1].B3[7]::M3 (work@small_top.u1.B1[6].B2[1].B3[7].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[6].B2[1].B3[7]) |vpiName:N3 @@ -39633,8 +39633,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[6].B2[1].B3[8].k - |vpiModule: - \_module: work@small_top.u1.B1[6].B2[1].B3[8]::M3 (work@small_top.u1.B1[6].B2[1].B3[8].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[6].B2[1].B3[8]::M3 (work@small_top.u1.B1[6].B2[1].B3[8].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[6].B2[1].B3[8]) |vpiName:N3 @@ -39661,8 +39661,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[6].B2[1].B3[9].k - |vpiModule: - \_module: work@small_top.u1.B1[6].B2[1].B3[9]::M3 (work@small_top.u1.B1[6].B2[1].B3[9].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[6].B2[1].B3[9]::M3 (work@small_top.u1.B1[6].B2[1].B3[9].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[6].B2[1].B3[9]) |vpiName:N3 @@ -39689,8 +39689,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:j |vpiFullName:work@small_top.u1.B1[6].B2[2].j - |vpiModule: - \_module: work@small_top.u1.B1[6].B2[2]::M2 (work@small_top.u1.B1[6].B2[2].N2), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:26:1, endln:26:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[6].B2[2]::M2 (work@small_top.u1.B1[6].B2[2].N2), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:26:1, endln:26:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[6].B2[2]) |vpiName:N2 @@ -39717,8 +39717,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[6].B2[2].B3[0].k - |vpiModule: - \_module: work@small_top.u1.B1[6].B2[2].B3[0]::M3 (work@small_top.u1.B1[6].B2[2].B3[0].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[6].B2[2].B3[0]::M3 (work@small_top.u1.B1[6].B2[2].B3[0].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[6].B2[2].B3[0]) |vpiName:N3 @@ -39745,8 +39745,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[6].B2[2].B3[1].k - |vpiModule: - \_module: work@small_top.u1.B1[6].B2[2].B3[1]::M3 (work@small_top.u1.B1[6].B2[2].B3[1].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[6].B2[2].B3[1]::M3 (work@small_top.u1.B1[6].B2[2].B3[1].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[6].B2[2].B3[1]) |vpiName:N3 @@ -39773,8 +39773,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[6].B2[2].B3[2].k - |vpiModule: - \_module: work@small_top.u1.B1[6].B2[2].B3[2]::M3 (work@small_top.u1.B1[6].B2[2].B3[2].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[6].B2[2].B3[2]::M3 (work@small_top.u1.B1[6].B2[2].B3[2].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[6].B2[2].B3[2]) |vpiName:N3 @@ -39801,8 +39801,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[6].B2[2].B3[3].k - |vpiModule: - \_module: work@small_top.u1.B1[6].B2[2].B3[3]::M3 (work@small_top.u1.B1[6].B2[2].B3[3].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[6].B2[2].B3[3]::M3 (work@small_top.u1.B1[6].B2[2].B3[3].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[6].B2[2].B3[3]) |vpiName:N3 @@ -39829,8 +39829,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[6].B2[2].B3[4].k - |vpiModule: - \_module: work@small_top.u1.B1[6].B2[2].B3[4]::M3 (work@small_top.u1.B1[6].B2[2].B3[4].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[6].B2[2].B3[4]::M3 (work@small_top.u1.B1[6].B2[2].B3[4].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[6].B2[2].B3[4]) |vpiName:N3 @@ -39857,8 +39857,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[6].B2[2].B3[5].k - |vpiModule: - \_module: work@small_top.u1.B1[6].B2[2].B3[5]::M3 (work@small_top.u1.B1[6].B2[2].B3[5].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[6].B2[2].B3[5]::M3 (work@small_top.u1.B1[6].B2[2].B3[5].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[6].B2[2].B3[5]) |vpiName:N3 @@ -39885,8 +39885,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[6].B2[2].B3[6].k - |vpiModule: - \_module: work@small_top.u1.B1[6].B2[2].B3[6]::M3 (work@small_top.u1.B1[6].B2[2].B3[6].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[6].B2[2].B3[6]::M3 (work@small_top.u1.B1[6].B2[2].B3[6].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[6].B2[2].B3[6]) |vpiName:N3 @@ -39913,8 +39913,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[6].B2[2].B3[7].k - |vpiModule: - \_module: work@small_top.u1.B1[6].B2[2].B3[7]::M3 (work@small_top.u1.B1[6].B2[2].B3[7].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[6].B2[2].B3[7]::M3 (work@small_top.u1.B1[6].B2[2].B3[7].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[6].B2[2].B3[7]) |vpiName:N3 @@ -39941,8 +39941,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[6].B2[2].B3[8].k - |vpiModule: - \_module: work@small_top.u1.B1[6].B2[2].B3[8]::M3 (work@small_top.u1.B1[6].B2[2].B3[8].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[6].B2[2].B3[8]::M3 (work@small_top.u1.B1[6].B2[2].B3[8].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[6].B2[2].B3[8]) |vpiName:N3 @@ -39969,8 +39969,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[6].B2[2].B3[9].k - |vpiModule: - \_module: work@small_top.u1.B1[6].B2[2].B3[9]::M3 (work@small_top.u1.B1[6].B2[2].B3[9].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[6].B2[2].B3[9]::M3 (work@small_top.u1.B1[6].B2[2].B3[9].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[6].B2[2].B3[9]) |vpiName:N3 @@ -39997,8 +39997,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:j |vpiFullName:work@small_top.u1.B1[6].B2[3].j - |vpiModule: - \_module: work@small_top.u1.B1[6].B2[3]::M2 (work@small_top.u1.B1[6].B2[3].N2), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:26:1, endln:26:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[6].B2[3]::M2 (work@small_top.u1.B1[6].B2[3].N2), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:26:1, endln:26:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[6].B2[3]) |vpiName:N2 @@ -40025,8 +40025,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[6].B2[3].B3[0].k - |vpiModule: - \_module: work@small_top.u1.B1[6].B2[3].B3[0]::M3 (work@small_top.u1.B1[6].B2[3].B3[0].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[6].B2[3].B3[0]::M3 (work@small_top.u1.B1[6].B2[3].B3[0].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[6].B2[3].B3[0]) |vpiName:N3 @@ -40053,8 +40053,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[6].B2[3].B3[1].k - |vpiModule: - \_module: work@small_top.u1.B1[6].B2[3].B3[1]::M3 (work@small_top.u1.B1[6].B2[3].B3[1].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[6].B2[3].B3[1]::M3 (work@small_top.u1.B1[6].B2[3].B3[1].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[6].B2[3].B3[1]) |vpiName:N3 @@ -40081,8 +40081,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[6].B2[3].B3[2].k - |vpiModule: - \_module: work@small_top.u1.B1[6].B2[3].B3[2]::M3 (work@small_top.u1.B1[6].B2[3].B3[2].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[6].B2[3].B3[2]::M3 (work@small_top.u1.B1[6].B2[3].B3[2].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[6].B2[3].B3[2]) |vpiName:N3 @@ -40109,8 +40109,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[6].B2[3].B3[3].k - |vpiModule: - \_module: work@small_top.u1.B1[6].B2[3].B3[3]::M3 (work@small_top.u1.B1[6].B2[3].B3[3].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[6].B2[3].B3[3]::M3 (work@small_top.u1.B1[6].B2[3].B3[3].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[6].B2[3].B3[3]) |vpiName:N3 @@ -40137,8 +40137,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[6].B2[3].B3[4].k - |vpiModule: - \_module: work@small_top.u1.B1[6].B2[3].B3[4]::M3 (work@small_top.u1.B1[6].B2[3].B3[4].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[6].B2[3].B3[4]::M3 (work@small_top.u1.B1[6].B2[3].B3[4].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[6].B2[3].B3[4]) |vpiName:N3 @@ -40165,8 +40165,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[6].B2[3].B3[5].k - |vpiModule: - \_module: work@small_top.u1.B1[6].B2[3].B3[5]::M3 (work@small_top.u1.B1[6].B2[3].B3[5].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[6].B2[3].B3[5]::M3 (work@small_top.u1.B1[6].B2[3].B3[5].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[6].B2[3].B3[5]) |vpiName:N3 @@ -40193,8 +40193,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[6].B2[3].B3[6].k - |vpiModule: - \_module: work@small_top.u1.B1[6].B2[3].B3[6]::M3 (work@small_top.u1.B1[6].B2[3].B3[6].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[6].B2[3].B3[6]::M3 (work@small_top.u1.B1[6].B2[3].B3[6].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[6].B2[3].B3[6]) |vpiName:N3 @@ -40221,8 +40221,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[6].B2[3].B3[7].k - |vpiModule: - \_module: work@small_top.u1.B1[6].B2[3].B3[7]::M3 (work@small_top.u1.B1[6].B2[3].B3[7].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[6].B2[3].B3[7]::M3 (work@small_top.u1.B1[6].B2[3].B3[7].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[6].B2[3].B3[7]) |vpiName:N3 @@ -40249,8 +40249,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[6].B2[3].B3[8].k - |vpiModule: - \_module: work@small_top.u1.B1[6].B2[3].B3[8]::M3 (work@small_top.u1.B1[6].B2[3].B3[8].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[6].B2[3].B3[8]::M3 (work@small_top.u1.B1[6].B2[3].B3[8].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[6].B2[3].B3[8]) |vpiName:N3 @@ -40277,8 +40277,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[6].B2[3].B3[9].k - |vpiModule: - \_module: work@small_top.u1.B1[6].B2[3].B3[9]::M3 (work@small_top.u1.B1[6].B2[3].B3[9].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[6].B2[3].B3[9]::M3 (work@small_top.u1.B1[6].B2[3].B3[9].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[6].B2[3].B3[9]) |vpiName:N3 @@ -40305,8 +40305,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:j |vpiFullName:work@small_top.u1.B1[6].B2[4].j - |vpiModule: - \_module: work@small_top.u1.B1[6].B2[4]::M2 (work@small_top.u1.B1[6].B2[4].N2), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:26:1, endln:26:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[6].B2[4]::M2 (work@small_top.u1.B1[6].B2[4].N2), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:26:1, endln:26:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[6].B2[4]) |vpiName:N2 @@ -40333,8 +40333,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[6].B2[4].B3[0].k - |vpiModule: - \_module: work@small_top.u1.B1[6].B2[4].B3[0]::M3 (work@small_top.u1.B1[6].B2[4].B3[0].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[6].B2[4].B3[0]::M3 (work@small_top.u1.B1[6].B2[4].B3[0].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[6].B2[4].B3[0]) |vpiName:N3 @@ -40361,8 +40361,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[6].B2[4].B3[1].k - |vpiModule: - \_module: work@small_top.u1.B1[6].B2[4].B3[1]::M3 (work@small_top.u1.B1[6].B2[4].B3[1].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[6].B2[4].B3[1]::M3 (work@small_top.u1.B1[6].B2[4].B3[1].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[6].B2[4].B3[1]) |vpiName:N3 @@ -40389,8 +40389,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[6].B2[4].B3[2].k - |vpiModule: - \_module: work@small_top.u1.B1[6].B2[4].B3[2]::M3 (work@small_top.u1.B1[6].B2[4].B3[2].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[6].B2[4].B3[2]::M3 (work@small_top.u1.B1[6].B2[4].B3[2].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[6].B2[4].B3[2]) |vpiName:N3 @@ -40417,8 +40417,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[6].B2[4].B3[3].k - |vpiModule: - \_module: work@small_top.u1.B1[6].B2[4].B3[3]::M3 (work@small_top.u1.B1[6].B2[4].B3[3].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[6].B2[4].B3[3]::M3 (work@small_top.u1.B1[6].B2[4].B3[3].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[6].B2[4].B3[3]) |vpiName:N3 @@ -40445,8 +40445,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[6].B2[4].B3[4].k - |vpiModule: - \_module: work@small_top.u1.B1[6].B2[4].B3[4]::M3 (work@small_top.u1.B1[6].B2[4].B3[4].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[6].B2[4].B3[4]::M3 (work@small_top.u1.B1[6].B2[4].B3[4].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[6].B2[4].B3[4]) |vpiName:N3 @@ -40473,8 +40473,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[6].B2[4].B3[5].k - |vpiModule: - \_module: work@small_top.u1.B1[6].B2[4].B3[5]::M3 (work@small_top.u1.B1[6].B2[4].B3[5].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[6].B2[4].B3[5]::M3 (work@small_top.u1.B1[6].B2[4].B3[5].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[6].B2[4].B3[5]) |vpiName:N3 @@ -40501,8 +40501,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[6].B2[4].B3[6].k - |vpiModule: - \_module: work@small_top.u1.B1[6].B2[4].B3[6]::M3 (work@small_top.u1.B1[6].B2[4].B3[6].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[6].B2[4].B3[6]::M3 (work@small_top.u1.B1[6].B2[4].B3[6].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[6].B2[4].B3[6]) |vpiName:N3 @@ -40529,8 +40529,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[6].B2[4].B3[7].k - |vpiModule: - \_module: work@small_top.u1.B1[6].B2[4].B3[7]::M3 (work@small_top.u1.B1[6].B2[4].B3[7].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[6].B2[4].B3[7]::M3 (work@small_top.u1.B1[6].B2[4].B3[7].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[6].B2[4].B3[7]) |vpiName:N3 @@ -40557,8 +40557,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[6].B2[4].B3[8].k - |vpiModule: - \_module: work@small_top.u1.B1[6].B2[4].B3[8]::M3 (work@small_top.u1.B1[6].B2[4].B3[8].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[6].B2[4].B3[8]::M3 (work@small_top.u1.B1[6].B2[4].B3[8].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[6].B2[4].B3[8]) |vpiName:N3 @@ -40585,8 +40585,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[6].B2[4].B3[9].k - |vpiModule: - \_module: work@small_top.u1.B1[6].B2[4].B3[9]::M3 (work@small_top.u1.B1[6].B2[4].B3[9].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[6].B2[4].B3[9]::M3 (work@small_top.u1.B1[6].B2[4].B3[9].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[6].B2[4].B3[9]) |vpiName:N3 @@ -40613,8 +40613,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:j |vpiFullName:work@small_top.u1.B1[6].B2[5].j - |vpiModule: - \_module: work@small_top.u1.B1[6].B2[5]::M2 (work@small_top.u1.B1[6].B2[5].N2), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:26:1, endln:26:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[6].B2[5]::M2 (work@small_top.u1.B1[6].B2[5].N2), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:26:1, endln:26:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[6].B2[5]) |vpiName:N2 @@ -40641,8 +40641,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[6].B2[5].B3[0].k - |vpiModule: - \_module: work@small_top.u1.B1[6].B2[5].B3[0]::M3 (work@small_top.u1.B1[6].B2[5].B3[0].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[6].B2[5].B3[0]::M3 (work@small_top.u1.B1[6].B2[5].B3[0].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[6].B2[5].B3[0]) |vpiName:N3 @@ -40669,8 +40669,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[6].B2[5].B3[1].k - |vpiModule: - \_module: work@small_top.u1.B1[6].B2[5].B3[1]::M3 (work@small_top.u1.B1[6].B2[5].B3[1].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[6].B2[5].B3[1]::M3 (work@small_top.u1.B1[6].B2[5].B3[1].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[6].B2[5].B3[1]) |vpiName:N3 @@ -40697,8 +40697,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[6].B2[5].B3[2].k - |vpiModule: - \_module: work@small_top.u1.B1[6].B2[5].B3[2]::M3 (work@small_top.u1.B1[6].B2[5].B3[2].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[6].B2[5].B3[2]::M3 (work@small_top.u1.B1[6].B2[5].B3[2].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[6].B2[5].B3[2]) |vpiName:N3 @@ -40725,8 +40725,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[6].B2[5].B3[3].k - |vpiModule: - \_module: work@small_top.u1.B1[6].B2[5].B3[3]::M3 (work@small_top.u1.B1[6].B2[5].B3[3].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[6].B2[5].B3[3]::M3 (work@small_top.u1.B1[6].B2[5].B3[3].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[6].B2[5].B3[3]) |vpiName:N3 @@ -40753,8 +40753,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[6].B2[5].B3[4].k - |vpiModule: - \_module: work@small_top.u1.B1[6].B2[5].B3[4]::M3 (work@small_top.u1.B1[6].B2[5].B3[4].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[6].B2[5].B3[4]::M3 (work@small_top.u1.B1[6].B2[5].B3[4].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[6].B2[5].B3[4]) |vpiName:N3 @@ -40781,8 +40781,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[6].B2[5].B3[5].k - |vpiModule: - \_module: work@small_top.u1.B1[6].B2[5].B3[5]::M3 (work@small_top.u1.B1[6].B2[5].B3[5].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[6].B2[5].B3[5]::M3 (work@small_top.u1.B1[6].B2[5].B3[5].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[6].B2[5].B3[5]) |vpiName:N3 @@ -40809,8 +40809,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[6].B2[5].B3[6].k - |vpiModule: - \_module: work@small_top.u1.B1[6].B2[5].B3[6]::M3 (work@small_top.u1.B1[6].B2[5].B3[6].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[6].B2[5].B3[6]::M3 (work@small_top.u1.B1[6].B2[5].B3[6].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[6].B2[5].B3[6]) |vpiName:N3 @@ -40837,8 +40837,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[6].B2[5].B3[7].k - |vpiModule: - \_module: work@small_top.u1.B1[6].B2[5].B3[7]::M3 (work@small_top.u1.B1[6].B2[5].B3[7].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[6].B2[5].B3[7]::M3 (work@small_top.u1.B1[6].B2[5].B3[7].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[6].B2[5].B3[7]) |vpiName:N3 @@ -40865,8 +40865,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[6].B2[5].B3[8].k - |vpiModule: - \_module: work@small_top.u1.B1[6].B2[5].B3[8]::M3 (work@small_top.u1.B1[6].B2[5].B3[8].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[6].B2[5].B3[8]::M3 (work@small_top.u1.B1[6].B2[5].B3[8].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[6].B2[5].B3[8]) |vpiName:N3 @@ -40893,8 +40893,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[6].B2[5].B3[9].k - |vpiModule: - \_module: work@small_top.u1.B1[6].B2[5].B3[9]::M3 (work@small_top.u1.B1[6].B2[5].B3[9].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[6].B2[5].B3[9]::M3 (work@small_top.u1.B1[6].B2[5].B3[9].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[6].B2[5].B3[9]) |vpiName:N3 @@ -40921,8 +40921,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:j |vpiFullName:work@small_top.u1.B1[6].B2[6].j - |vpiModule: - \_module: work@small_top.u1.B1[6].B2[6]::M2 (work@small_top.u1.B1[6].B2[6].N2), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:26:1, endln:26:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[6].B2[6]::M2 (work@small_top.u1.B1[6].B2[6].N2), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:26:1, endln:26:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[6].B2[6]) |vpiName:N2 @@ -40949,8 +40949,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[6].B2[6].B3[0].k - |vpiModule: - \_module: work@small_top.u1.B1[6].B2[6].B3[0]::M3 (work@small_top.u1.B1[6].B2[6].B3[0].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[6].B2[6].B3[0]::M3 (work@small_top.u1.B1[6].B2[6].B3[0].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[6].B2[6].B3[0]) |vpiName:N3 @@ -40977,8 +40977,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[6].B2[6].B3[1].k - |vpiModule: - \_module: work@small_top.u1.B1[6].B2[6].B3[1]::M3 (work@small_top.u1.B1[6].B2[6].B3[1].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[6].B2[6].B3[1]::M3 (work@small_top.u1.B1[6].B2[6].B3[1].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[6].B2[6].B3[1]) |vpiName:N3 @@ -41005,8 +41005,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[6].B2[6].B3[2].k - |vpiModule: - \_module: work@small_top.u1.B1[6].B2[6].B3[2]::M3 (work@small_top.u1.B1[6].B2[6].B3[2].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[6].B2[6].B3[2]::M3 (work@small_top.u1.B1[6].B2[6].B3[2].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[6].B2[6].B3[2]) |vpiName:N3 @@ -41033,8 +41033,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[6].B2[6].B3[3].k - |vpiModule: - \_module: work@small_top.u1.B1[6].B2[6].B3[3]::M3 (work@small_top.u1.B1[6].B2[6].B3[3].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[6].B2[6].B3[3]::M3 (work@small_top.u1.B1[6].B2[6].B3[3].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[6].B2[6].B3[3]) |vpiName:N3 @@ -41061,8 +41061,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[6].B2[6].B3[4].k - |vpiModule: - \_module: work@small_top.u1.B1[6].B2[6].B3[4]::M3 (work@small_top.u1.B1[6].B2[6].B3[4].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[6].B2[6].B3[4]::M3 (work@small_top.u1.B1[6].B2[6].B3[4].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[6].B2[6].B3[4]) |vpiName:N3 @@ -41089,8 +41089,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[6].B2[6].B3[5].k - |vpiModule: - \_module: work@small_top.u1.B1[6].B2[6].B3[5]::M3 (work@small_top.u1.B1[6].B2[6].B3[5].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[6].B2[6].B3[5]::M3 (work@small_top.u1.B1[6].B2[6].B3[5].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[6].B2[6].B3[5]) |vpiName:N3 @@ -41117,8 +41117,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[6].B2[6].B3[6].k - |vpiModule: - \_module: work@small_top.u1.B1[6].B2[6].B3[6]::M3 (work@small_top.u1.B1[6].B2[6].B3[6].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[6].B2[6].B3[6]::M3 (work@small_top.u1.B1[6].B2[6].B3[6].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[6].B2[6].B3[6]) |vpiName:N3 @@ -41145,8 +41145,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[6].B2[6].B3[7].k - |vpiModule: - \_module: work@small_top.u1.B1[6].B2[6].B3[7]::M3 (work@small_top.u1.B1[6].B2[6].B3[7].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[6].B2[6].B3[7]::M3 (work@small_top.u1.B1[6].B2[6].B3[7].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[6].B2[6].B3[7]) |vpiName:N3 @@ -41173,8 +41173,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[6].B2[6].B3[8].k - |vpiModule: - \_module: work@small_top.u1.B1[6].B2[6].B3[8]::M3 (work@small_top.u1.B1[6].B2[6].B3[8].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[6].B2[6].B3[8]::M3 (work@small_top.u1.B1[6].B2[6].B3[8].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[6].B2[6].B3[8]) |vpiName:N3 @@ -41201,8 +41201,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[6].B2[6].B3[9].k - |vpiModule: - \_module: work@small_top.u1.B1[6].B2[6].B3[9]::M3 (work@small_top.u1.B1[6].B2[6].B3[9].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[6].B2[6].B3[9]::M3 (work@small_top.u1.B1[6].B2[6].B3[9].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[6].B2[6].B3[9]) |vpiName:N3 @@ -41229,8 +41229,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:j |vpiFullName:work@small_top.u1.B1[6].B2[7].j - |vpiModule: - \_module: work@small_top.u1.B1[6].B2[7]::M2 (work@small_top.u1.B1[6].B2[7].N2), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:26:1, endln:26:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[6].B2[7]::M2 (work@small_top.u1.B1[6].B2[7].N2), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:26:1, endln:26:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[6].B2[7]) |vpiName:N2 @@ -41257,8 +41257,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[6].B2[7].B3[0].k - |vpiModule: - \_module: work@small_top.u1.B1[6].B2[7].B3[0]::M3 (work@small_top.u1.B1[6].B2[7].B3[0].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[6].B2[7].B3[0]::M3 (work@small_top.u1.B1[6].B2[7].B3[0].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[6].B2[7].B3[0]) |vpiName:N3 @@ -41285,8 +41285,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[6].B2[7].B3[1].k - |vpiModule: - \_module: work@small_top.u1.B1[6].B2[7].B3[1]::M3 (work@small_top.u1.B1[6].B2[7].B3[1].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[6].B2[7].B3[1]::M3 (work@small_top.u1.B1[6].B2[7].B3[1].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[6].B2[7].B3[1]) |vpiName:N3 @@ -41313,8 +41313,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[6].B2[7].B3[2].k - |vpiModule: - \_module: work@small_top.u1.B1[6].B2[7].B3[2]::M3 (work@small_top.u1.B1[6].B2[7].B3[2].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[6].B2[7].B3[2]::M3 (work@small_top.u1.B1[6].B2[7].B3[2].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[6].B2[7].B3[2]) |vpiName:N3 @@ -41341,8 +41341,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[6].B2[7].B3[3].k - |vpiModule: - \_module: work@small_top.u1.B1[6].B2[7].B3[3]::M3 (work@small_top.u1.B1[6].B2[7].B3[3].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[6].B2[7].B3[3]::M3 (work@small_top.u1.B1[6].B2[7].B3[3].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[6].B2[7].B3[3]) |vpiName:N3 @@ -41369,8 +41369,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[6].B2[7].B3[4].k - |vpiModule: - \_module: work@small_top.u1.B1[6].B2[7].B3[4]::M3 (work@small_top.u1.B1[6].B2[7].B3[4].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[6].B2[7].B3[4]::M3 (work@small_top.u1.B1[6].B2[7].B3[4].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[6].B2[7].B3[4]) |vpiName:N3 @@ -41397,8 +41397,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[6].B2[7].B3[5].k - |vpiModule: - \_module: work@small_top.u1.B1[6].B2[7].B3[5]::M3 (work@small_top.u1.B1[6].B2[7].B3[5].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[6].B2[7].B3[5]::M3 (work@small_top.u1.B1[6].B2[7].B3[5].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[6].B2[7].B3[5]) |vpiName:N3 @@ -41425,8 +41425,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[6].B2[7].B3[6].k - |vpiModule: - \_module: work@small_top.u1.B1[6].B2[7].B3[6]::M3 (work@small_top.u1.B1[6].B2[7].B3[6].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[6].B2[7].B3[6]::M3 (work@small_top.u1.B1[6].B2[7].B3[6].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[6].B2[7].B3[6]) |vpiName:N3 @@ -41453,8 +41453,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[6].B2[7].B3[7].k - |vpiModule: - \_module: work@small_top.u1.B1[6].B2[7].B3[7]::M3 (work@small_top.u1.B1[6].B2[7].B3[7].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[6].B2[7].B3[7]::M3 (work@small_top.u1.B1[6].B2[7].B3[7].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[6].B2[7].B3[7]) |vpiName:N3 @@ -41481,8 +41481,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[6].B2[7].B3[8].k - |vpiModule: - \_module: work@small_top.u1.B1[6].B2[7].B3[8]::M3 (work@small_top.u1.B1[6].B2[7].B3[8].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[6].B2[7].B3[8]::M3 (work@small_top.u1.B1[6].B2[7].B3[8].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[6].B2[7].B3[8]) |vpiName:N3 @@ -41509,8 +41509,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[6].B2[7].B3[9].k - |vpiModule: - \_module: work@small_top.u1.B1[6].B2[7].B3[9]::M3 (work@small_top.u1.B1[6].B2[7].B3[9].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[6].B2[7].B3[9]::M3 (work@small_top.u1.B1[6].B2[7].B3[9].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[6].B2[7].B3[9]) |vpiName:N3 @@ -41537,8 +41537,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:j |vpiFullName:work@small_top.u1.B1[6].B2[8].j - |vpiModule: - \_module: work@small_top.u1.B1[6].B2[8]::M2 (work@small_top.u1.B1[6].B2[8].N2), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:26:1, endln:26:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[6].B2[8]::M2 (work@small_top.u1.B1[6].B2[8].N2), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:26:1, endln:26:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[6].B2[8]) |vpiName:N2 @@ -41565,8 +41565,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[6].B2[8].B3[0].k - |vpiModule: - \_module: work@small_top.u1.B1[6].B2[8].B3[0]::M3 (work@small_top.u1.B1[6].B2[8].B3[0].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[6].B2[8].B3[0]::M3 (work@small_top.u1.B1[6].B2[8].B3[0].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[6].B2[8].B3[0]) |vpiName:N3 @@ -41593,8 +41593,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[6].B2[8].B3[1].k - |vpiModule: - \_module: work@small_top.u1.B1[6].B2[8].B3[1]::M3 (work@small_top.u1.B1[6].B2[8].B3[1].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[6].B2[8].B3[1]::M3 (work@small_top.u1.B1[6].B2[8].B3[1].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[6].B2[8].B3[1]) |vpiName:N3 @@ -41621,8 +41621,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[6].B2[8].B3[2].k - |vpiModule: - \_module: work@small_top.u1.B1[6].B2[8].B3[2]::M3 (work@small_top.u1.B1[6].B2[8].B3[2].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[6].B2[8].B3[2]::M3 (work@small_top.u1.B1[6].B2[8].B3[2].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[6].B2[8].B3[2]) |vpiName:N3 @@ -41649,8 +41649,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[6].B2[8].B3[3].k - |vpiModule: - \_module: work@small_top.u1.B1[6].B2[8].B3[3]::M3 (work@small_top.u1.B1[6].B2[8].B3[3].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[6].B2[8].B3[3]::M3 (work@small_top.u1.B1[6].B2[8].B3[3].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[6].B2[8].B3[3]) |vpiName:N3 @@ -41677,8 +41677,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[6].B2[8].B3[4].k - |vpiModule: - \_module: work@small_top.u1.B1[6].B2[8].B3[4]::M3 (work@small_top.u1.B1[6].B2[8].B3[4].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[6].B2[8].B3[4]::M3 (work@small_top.u1.B1[6].B2[8].B3[4].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[6].B2[8].B3[4]) |vpiName:N3 @@ -41705,8 +41705,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[6].B2[8].B3[5].k - |vpiModule: - \_module: work@small_top.u1.B1[6].B2[8].B3[5]::M3 (work@small_top.u1.B1[6].B2[8].B3[5].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[6].B2[8].B3[5]::M3 (work@small_top.u1.B1[6].B2[8].B3[5].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[6].B2[8].B3[5]) |vpiName:N3 @@ -41733,8 +41733,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[6].B2[8].B3[6].k - |vpiModule: - \_module: work@small_top.u1.B1[6].B2[8].B3[6]::M3 (work@small_top.u1.B1[6].B2[8].B3[6].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[6].B2[8].B3[6]::M3 (work@small_top.u1.B1[6].B2[8].B3[6].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[6].B2[8].B3[6]) |vpiName:N3 @@ -41761,8 +41761,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[6].B2[8].B3[7].k - |vpiModule: - \_module: work@small_top.u1.B1[6].B2[8].B3[7]::M3 (work@small_top.u1.B1[6].B2[8].B3[7].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[6].B2[8].B3[7]::M3 (work@small_top.u1.B1[6].B2[8].B3[7].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[6].B2[8].B3[7]) |vpiName:N3 @@ -41789,8 +41789,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[6].B2[8].B3[8].k - |vpiModule: - \_module: work@small_top.u1.B1[6].B2[8].B3[8]::M3 (work@small_top.u1.B1[6].B2[8].B3[8].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[6].B2[8].B3[8]::M3 (work@small_top.u1.B1[6].B2[8].B3[8].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[6].B2[8].B3[8]) |vpiName:N3 @@ -41817,8 +41817,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[6].B2[8].B3[9].k - |vpiModule: - \_module: work@small_top.u1.B1[6].B2[8].B3[9]::M3 (work@small_top.u1.B1[6].B2[8].B3[9].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[6].B2[8].B3[9]::M3 (work@small_top.u1.B1[6].B2[8].B3[9].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[6].B2[8].B3[9]) |vpiName:N3 @@ -41845,8 +41845,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:j |vpiFullName:work@small_top.u1.B1[6].B2[9].j - |vpiModule: - \_module: work@small_top.u1.B1[6].B2[9]::M2 (work@small_top.u1.B1[6].B2[9].N2), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:26:1, endln:26:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[6].B2[9]::M2 (work@small_top.u1.B1[6].B2[9].N2), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:26:1, endln:26:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[6].B2[9]) |vpiName:N2 @@ -41873,8 +41873,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[6].B2[9].B3[0].k - |vpiModule: - \_module: work@small_top.u1.B1[6].B2[9].B3[0]::M3 (work@small_top.u1.B1[6].B2[9].B3[0].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[6].B2[9].B3[0]::M3 (work@small_top.u1.B1[6].B2[9].B3[0].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[6].B2[9].B3[0]) |vpiName:N3 @@ -41901,8 +41901,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[6].B2[9].B3[1].k - |vpiModule: - \_module: work@small_top.u1.B1[6].B2[9].B3[1]::M3 (work@small_top.u1.B1[6].B2[9].B3[1].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[6].B2[9].B3[1]::M3 (work@small_top.u1.B1[6].B2[9].B3[1].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[6].B2[9].B3[1]) |vpiName:N3 @@ -41929,8 +41929,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[6].B2[9].B3[2].k - |vpiModule: - \_module: work@small_top.u1.B1[6].B2[9].B3[2]::M3 (work@small_top.u1.B1[6].B2[9].B3[2].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[6].B2[9].B3[2]::M3 (work@small_top.u1.B1[6].B2[9].B3[2].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[6].B2[9].B3[2]) |vpiName:N3 @@ -41957,8 +41957,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[6].B2[9].B3[3].k - |vpiModule: - \_module: work@small_top.u1.B1[6].B2[9].B3[3]::M3 (work@small_top.u1.B1[6].B2[9].B3[3].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[6].B2[9].B3[3]::M3 (work@small_top.u1.B1[6].B2[9].B3[3].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[6].B2[9].B3[3]) |vpiName:N3 @@ -41985,8 +41985,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[6].B2[9].B3[4].k - |vpiModule: - \_module: work@small_top.u1.B1[6].B2[9].B3[4]::M3 (work@small_top.u1.B1[6].B2[9].B3[4].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[6].B2[9].B3[4]::M3 (work@small_top.u1.B1[6].B2[9].B3[4].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[6].B2[9].B3[4]) |vpiName:N3 @@ -42013,8 +42013,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[6].B2[9].B3[5].k - |vpiModule: - \_module: work@small_top.u1.B1[6].B2[9].B3[5]::M3 (work@small_top.u1.B1[6].B2[9].B3[5].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[6].B2[9].B3[5]::M3 (work@small_top.u1.B1[6].B2[9].B3[5].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[6].B2[9].B3[5]) |vpiName:N3 @@ -42041,8 +42041,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[6].B2[9].B3[6].k - |vpiModule: - \_module: work@small_top.u1.B1[6].B2[9].B3[6]::M3 (work@small_top.u1.B1[6].B2[9].B3[6].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[6].B2[9].B3[6]::M3 (work@small_top.u1.B1[6].B2[9].B3[6].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[6].B2[9].B3[6]) |vpiName:N3 @@ -42069,8 +42069,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[6].B2[9].B3[7].k - |vpiModule: - \_module: work@small_top.u1.B1[6].B2[9].B3[7]::M3 (work@small_top.u1.B1[6].B2[9].B3[7].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[6].B2[9].B3[7]::M3 (work@small_top.u1.B1[6].B2[9].B3[7].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[6].B2[9].B3[7]) |vpiName:N3 @@ -42097,8 +42097,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[6].B2[9].B3[8].k - |vpiModule: - \_module: work@small_top.u1.B1[6].B2[9].B3[8]::M3 (work@small_top.u1.B1[6].B2[9].B3[8].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[6].B2[9].B3[8]::M3 (work@small_top.u1.B1[6].B2[9].B3[8].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[6].B2[9].B3[8]) |vpiName:N3 @@ -42125,8 +42125,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[6].B2[9].B3[9].k - |vpiModule: - \_module: work@small_top.u1.B1[6].B2[9].B3[9]::M3 (work@small_top.u1.B1[6].B2[9].B3[9].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[6].B2[9].B3[9]::M3 (work@small_top.u1.B1[6].B2[9].B3[9].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[6].B2[9].B3[9]) |vpiName:N3 @@ -42164,8 +42164,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:m |vpiFullName:work@small_top.u1.B1[6].B4.B5[0].m - |vpiModule: - \_module: work@small_top.u1.B1[6].B4.B5[0]::M4 (work@small_top.u1.B1[6].B4.B5[0].N4), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:46:1, endln:46:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[6].B4.B5[0]::M4 (work@small_top.u1.B1[6].B4.B5[0].N4), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:46:1, endln:46:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[6].B4.B5[0]) |vpiName:N4 @@ -42192,8 +42192,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:m |vpiFullName:work@small_top.u1.B1[6].B4.B5[1].m - |vpiModule: - \_module: work@small_top.u1.B1[6].B4.B5[1]::M4 (work@small_top.u1.B1[6].B4.B5[1].N4), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:46:1, endln:46:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[6].B4.B5[1]::M4 (work@small_top.u1.B1[6].B4.B5[1].N4), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:46:1, endln:46:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[6].B4.B5[1]) |vpiName:N4 @@ -42220,8 +42220,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:m |vpiFullName:work@small_top.u1.B1[6].B4.B5[2].m - |vpiModule: - \_module: work@small_top.u1.B1[6].B4.B5[2]::M4 (work@small_top.u1.B1[6].B4.B5[2].N4), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:46:1, endln:46:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[6].B4.B5[2]::M4 (work@small_top.u1.B1[6].B4.B5[2].N4), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:46:1, endln:46:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[6].B4.B5[2]) |vpiName:N4 @@ -42248,8 +42248,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:m |vpiFullName:work@small_top.u1.B1[6].B4.B5[3].m - |vpiModule: - \_module: work@small_top.u1.B1[6].B4.B5[3]::M4 (work@small_top.u1.B1[6].B4.B5[3].N4), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:46:1, endln:46:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[6].B4.B5[3]::M4 (work@small_top.u1.B1[6].B4.B5[3].N4), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:46:1, endln:46:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[6].B4.B5[3]) |vpiName:N4 @@ -42276,8 +42276,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:m |vpiFullName:work@small_top.u1.B1[6].B4.B5[4].m - |vpiModule: - \_module: work@small_top.u1.B1[6].B4.B5[4]::M4 (work@small_top.u1.B1[6].B4.B5[4].N4), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:46:1, endln:46:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[6].B4.B5[4]::M4 (work@small_top.u1.B1[6].B4.B5[4].N4), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:46:1, endln:46:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[6].B4.B5[4]) |vpiName:N4 @@ -42304,8 +42304,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:m |vpiFullName:work@small_top.u1.B1[6].B4.B5[5].m - |vpiModule: - \_module: work@small_top.u1.B1[6].B4.B5[5]::M4 (work@small_top.u1.B1[6].B4.B5[5].N4), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:46:1, endln:46:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[6].B4.B5[5]::M4 (work@small_top.u1.B1[6].B4.B5[5].N4), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:46:1, endln:46:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[6].B4.B5[5]) |vpiName:N4 @@ -42332,8 +42332,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:m |vpiFullName:work@small_top.u1.B1[6].B4.B5[6].m - |vpiModule: - \_module: work@small_top.u1.B1[6].B4.B5[6]::M4 (work@small_top.u1.B1[6].B4.B5[6].N4), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:46:1, endln:46:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[6].B4.B5[6]::M4 (work@small_top.u1.B1[6].B4.B5[6].N4), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:46:1, endln:46:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[6].B4.B5[6]) |vpiName:N4 @@ -42360,8 +42360,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:m |vpiFullName:work@small_top.u1.B1[6].B4.B5[7].m - |vpiModule: - \_module: work@small_top.u1.B1[6].B4.B5[7]::M4 (work@small_top.u1.B1[6].B4.B5[7].N4), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:46:1, endln:46:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[6].B4.B5[7]::M4 (work@small_top.u1.B1[6].B4.B5[7].N4), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:46:1, endln:46:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[6].B4.B5[7]) |vpiName:N4 @@ -42388,8 +42388,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:m |vpiFullName:work@small_top.u1.B1[6].B4.B5[8].m - |vpiModule: - \_module: work@small_top.u1.B1[6].B4.B5[8]::M4 (work@small_top.u1.B1[6].B4.B5[8].N4), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:46:1, endln:46:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[6].B4.B5[8]::M4 (work@small_top.u1.B1[6].B4.B5[8].N4), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:46:1, endln:46:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[6].B4.B5[8]) |vpiName:N4 @@ -42416,8 +42416,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:m |vpiFullName:work@small_top.u1.B1[6].B4.B5[9].m - |vpiModule: - \_module: work@small_top.u1.B1[6].B4.B5[9]::M4 (work@small_top.u1.B1[6].B4.B5[9].N4), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:46:1, endln:46:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[6].B4.B5[9]::M4 (work@small_top.u1.B1[6].B4.B5[9].N4), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:46:1, endln:46:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[6].B4.B5[9]) |vpiName:N4 @@ -42426,7 +42426,7 @@ design: (work@bottom1) |vpiGenScopeArray: \_gen_scope_array: (work@small_top.u1.B1[7]), line:17:1, endln:51:4 |vpiParent: - \_module: work@small_test (work@small_top.u1), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:2:4, endln:2:29 + \_module_inst: work@small_test (work@small_top.u1), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:2:4, endln:2:29 |vpiName:B1[7] |vpiFullName:work@small_top.u1.B1[7] |vpiGenScope: @@ -42444,8 +42444,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:i |vpiFullName:work@small_top.u1.B1[7].i - |vpiModule: - \_module: work@small_top.u1.B1[7]::M1 (work@small_top.u1.B1[7].N1), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:20:1, endln:20:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[7]::M1 (work@small_top.u1.B1[7].N1), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:20:1, endln:20:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[7]) |vpiName:N1 @@ -42472,8 +42472,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:j |vpiFullName:work@small_top.u1.B1[7].B2[0].j - |vpiModule: - \_module: work@small_top.u1.B1[7].B2[0]::M2 (work@small_top.u1.B1[7].B2[0].N2), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:26:1, endln:26:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[7].B2[0]::M2 (work@small_top.u1.B1[7].B2[0].N2), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:26:1, endln:26:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[7].B2[0]) |vpiName:N2 @@ -42500,8 +42500,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[7].B2[0].B3[0].k - |vpiModule: - \_module: work@small_top.u1.B1[7].B2[0].B3[0]::M3 (work@small_top.u1.B1[7].B2[0].B3[0].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[7].B2[0].B3[0]::M3 (work@small_top.u1.B1[7].B2[0].B3[0].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[7].B2[0].B3[0]) |vpiName:N3 @@ -42528,8 +42528,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[7].B2[0].B3[1].k - |vpiModule: - \_module: work@small_top.u1.B1[7].B2[0].B3[1]::M3 (work@small_top.u1.B1[7].B2[0].B3[1].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[7].B2[0].B3[1]::M3 (work@small_top.u1.B1[7].B2[0].B3[1].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[7].B2[0].B3[1]) |vpiName:N3 @@ -42556,8 +42556,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[7].B2[0].B3[2].k - |vpiModule: - \_module: work@small_top.u1.B1[7].B2[0].B3[2]::M3 (work@small_top.u1.B1[7].B2[0].B3[2].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[7].B2[0].B3[2]::M3 (work@small_top.u1.B1[7].B2[0].B3[2].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[7].B2[0].B3[2]) |vpiName:N3 @@ -42584,8 +42584,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[7].B2[0].B3[3].k - |vpiModule: - \_module: work@small_top.u1.B1[7].B2[0].B3[3]::M3 (work@small_top.u1.B1[7].B2[0].B3[3].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[7].B2[0].B3[3]::M3 (work@small_top.u1.B1[7].B2[0].B3[3].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[7].B2[0].B3[3]) |vpiName:N3 @@ -42612,8 +42612,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[7].B2[0].B3[4].k - |vpiModule: - \_module: work@small_top.u1.B1[7].B2[0].B3[4]::M3 (work@small_top.u1.B1[7].B2[0].B3[4].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[7].B2[0].B3[4]::M3 (work@small_top.u1.B1[7].B2[0].B3[4].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[7].B2[0].B3[4]) |vpiName:N3 @@ -42640,8 +42640,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[7].B2[0].B3[5].k - |vpiModule: - \_module: work@small_top.u1.B1[7].B2[0].B3[5]::M3 (work@small_top.u1.B1[7].B2[0].B3[5].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[7].B2[0].B3[5]::M3 (work@small_top.u1.B1[7].B2[0].B3[5].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[7].B2[0].B3[5]) |vpiName:N3 @@ -42668,8 +42668,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[7].B2[0].B3[6].k - |vpiModule: - \_module: work@small_top.u1.B1[7].B2[0].B3[6]::M3 (work@small_top.u1.B1[7].B2[0].B3[6].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[7].B2[0].B3[6]::M3 (work@small_top.u1.B1[7].B2[0].B3[6].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[7].B2[0].B3[6]) |vpiName:N3 @@ -42696,8 +42696,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[7].B2[0].B3[7].k - |vpiModule: - \_module: work@small_top.u1.B1[7].B2[0].B3[7]::M3 (work@small_top.u1.B1[7].B2[0].B3[7].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[7].B2[0].B3[7]::M3 (work@small_top.u1.B1[7].B2[0].B3[7].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[7].B2[0].B3[7]) |vpiName:N3 @@ -42724,8 +42724,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[7].B2[0].B3[8].k - |vpiModule: - \_module: work@small_top.u1.B1[7].B2[0].B3[8]::M3 (work@small_top.u1.B1[7].B2[0].B3[8].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[7].B2[0].B3[8]::M3 (work@small_top.u1.B1[7].B2[0].B3[8].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[7].B2[0].B3[8]) |vpiName:N3 @@ -42752,8 +42752,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[7].B2[0].B3[9].k - |vpiModule: - \_module: work@small_top.u1.B1[7].B2[0].B3[9]::M3 (work@small_top.u1.B1[7].B2[0].B3[9].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[7].B2[0].B3[9]::M3 (work@small_top.u1.B1[7].B2[0].B3[9].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[7].B2[0].B3[9]) |vpiName:N3 @@ -42780,8 +42780,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:j |vpiFullName:work@small_top.u1.B1[7].B2[1].j - |vpiModule: - \_module: work@small_top.u1.B1[7].B2[1]::M2 (work@small_top.u1.B1[7].B2[1].N2), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:26:1, endln:26:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[7].B2[1]::M2 (work@small_top.u1.B1[7].B2[1].N2), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:26:1, endln:26:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[7].B2[1]) |vpiName:N2 @@ -42808,8 +42808,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[7].B2[1].B3[0].k - |vpiModule: - \_module: work@small_top.u1.B1[7].B2[1].B3[0]::M3 (work@small_top.u1.B1[7].B2[1].B3[0].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[7].B2[1].B3[0]::M3 (work@small_top.u1.B1[7].B2[1].B3[0].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[7].B2[1].B3[0]) |vpiName:N3 @@ -42836,8 +42836,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[7].B2[1].B3[1].k - |vpiModule: - \_module: work@small_top.u1.B1[7].B2[1].B3[1]::M3 (work@small_top.u1.B1[7].B2[1].B3[1].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[7].B2[1].B3[1]::M3 (work@small_top.u1.B1[7].B2[1].B3[1].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[7].B2[1].B3[1]) |vpiName:N3 @@ -42864,8 +42864,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[7].B2[1].B3[2].k - |vpiModule: - \_module: work@small_top.u1.B1[7].B2[1].B3[2]::M3 (work@small_top.u1.B1[7].B2[1].B3[2].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[7].B2[1].B3[2]::M3 (work@small_top.u1.B1[7].B2[1].B3[2].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[7].B2[1].B3[2]) |vpiName:N3 @@ -42892,8 +42892,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[7].B2[1].B3[3].k - |vpiModule: - \_module: work@small_top.u1.B1[7].B2[1].B3[3]::M3 (work@small_top.u1.B1[7].B2[1].B3[3].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[7].B2[1].B3[3]::M3 (work@small_top.u1.B1[7].B2[1].B3[3].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[7].B2[1].B3[3]) |vpiName:N3 @@ -42920,8 +42920,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[7].B2[1].B3[4].k - |vpiModule: - \_module: work@small_top.u1.B1[7].B2[1].B3[4]::M3 (work@small_top.u1.B1[7].B2[1].B3[4].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[7].B2[1].B3[4]::M3 (work@small_top.u1.B1[7].B2[1].B3[4].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[7].B2[1].B3[4]) |vpiName:N3 @@ -42948,8 +42948,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[7].B2[1].B3[5].k - |vpiModule: - \_module: work@small_top.u1.B1[7].B2[1].B3[5]::M3 (work@small_top.u1.B1[7].B2[1].B3[5].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[7].B2[1].B3[5]::M3 (work@small_top.u1.B1[7].B2[1].B3[5].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[7].B2[1].B3[5]) |vpiName:N3 @@ -42976,8 +42976,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[7].B2[1].B3[6].k - |vpiModule: - \_module: work@small_top.u1.B1[7].B2[1].B3[6]::M3 (work@small_top.u1.B1[7].B2[1].B3[6].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[7].B2[1].B3[6]::M3 (work@small_top.u1.B1[7].B2[1].B3[6].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[7].B2[1].B3[6]) |vpiName:N3 @@ -43004,8 +43004,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[7].B2[1].B3[7].k - |vpiModule: - \_module: work@small_top.u1.B1[7].B2[1].B3[7]::M3 (work@small_top.u1.B1[7].B2[1].B3[7].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[7].B2[1].B3[7]::M3 (work@small_top.u1.B1[7].B2[1].B3[7].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[7].B2[1].B3[7]) |vpiName:N3 @@ -43032,8 +43032,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[7].B2[1].B3[8].k - |vpiModule: - \_module: work@small_top.u1.B1[7].B2[1].B3[8]::M3 (work@small_top.u1.B1[7].B2[1].B3[8].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[7].B2[1].B3[8]::M3 (work@small_top.u1.B1[7].B2[1].B3[8].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[7].B2[1].B3[8]) |vpiName:N3 @@ -43060,8 +43060,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[7].B2[1].B3[9].k - |vpiModule: - \_module: work@small_top.u1.B1[7].B2[1].B3[9]::M3 (work@small_top.u1.B1[7].B2[1].B3[9].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[7].B2[1].B3[9]::M3 (work@small_top.u1.B1[7].B2[1].B3[9].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[7].B2[1].B3[9]) |vpiName:N3 @@ -43088,8 +43088,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:j |vpiFullName:work@small_top.u1.B1[7].B2[2].j - |vpiModule: - \_module: work@small_top.u1.B1[7].B2[2]::M2 (work@small_top.u1.B1[7].B2[2].N2), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:26:1, endln:26:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[7].B2[2]::M2 (work@small_top.u1.B1[7].B2[2].N2), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:26:1, endln:26:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[7].B2[2]) |vpiName:N2 @@ -43116,8 +43116,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[7].B2[2].B3[0].k - |vpiModule: - \_module: work@small_top.u1.B1[7].B2[2].B3[0]::M3 (work@small_top.u1.B1[7].B2[2].B3[0].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[7].B2[2].B3[0]::M3 (work@small_top.u1.B1[7].B2[2].B3[0].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[7].B2[2].B3[0]) |vpiName:N3 @@ -43144,8 +43144,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[7].B2[2].B3[1].k - |vpiModule: - \_module: work@small_top.u1.B1[7].B2[2].B3[1]::M3 (work@small_top.u1.B1[7].B2[2].B3[1].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[7].B2[2].B3[1]::M3 (work@small_top.u1.B1[7].B2[2].B3[1].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[7].B2[2].B3[1]) |vpiName:N3 @@ -43172,8 +43172,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[7].B2[2].B3[2].k - |vpiModule: - \_module: work@small_top.u1.B1[7].B2[2].B3[2]::M3 (work@small_top.u1.B1[7].B2[2].B3[2].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[7].B2[2].B3[2]::M3 (work@small_top.u1.B1[7].B2[2].B3[2].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[7].B2[2].B3[2]) |vpiName:N3 @@ -43200,8 +43200,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[7].B2[2].B3[3].k - |vpiModule: - \_module: work@small_top.u1.B1[7].B2[2].B3[3]::M3 (work@small_top.u1.B1[7].B2[2].B3[3].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[7].B2[2].B3[3]::M3 (work@small_top.u1.B1[7].B2[2].B3[3].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[7].B2[2].B3[3]) |vpiName:N3 @@ -43228,8 +43228,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[7].B2[2].B3[4].k - |vpiModule: - \_module: work@small_top.u1.B1[7].B2[2].B3[4]::M3 (work@small_top.u1.B1[7].B2[2].B3[4].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[7].B2[2].B3[4]::M3 (work@small_top.u1.B1[7].B2[2].B3[4].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[7].B2[2].B3[4]) |vpiName:N3 @@ -43256,8 +43256,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[7].B2[2].B3[5].k - |vpiModule: - \_module: work@small_top.u1.B1[7].B2[2].B3[5]::M3 (work@small_top.u1.B1[7].B2[2].B3[5].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[7].B2[2].B3[5]::M3 (work@small_top.u1.B1[7].B2[2].B3[5].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[7].B2[2].B3[5]) |vpiName:N3 @@ -43284,8 +43284,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[7].B2[2].B3[6].k - |vpiModule: - \_module: work@small_top.u1.B1[7].B2[2].B3[6]::M3 (work@small_top.u1.B1[7].B2[2].B3[6].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[7].B2[2].B3[6]::M3 (work@small_top.u1.B1[7].B2[2].B3[6].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[7].B2[2].B3[6]) |vpiName:N3 @@ -43312,8 +43312,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[7].B2[2].B3[7].k - |vpiModule: - \_module: work@small_top.u1.B1[7].B2[2].B3[7]::M3 (work@small_top.u1.B1[7].B2[2].B3[7].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[7].B2[2].B3[7]::M3 (work@small_top.u1.B1[7].B2[2].B3[7].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[7].B2[2].B3[7]) |vpiName:N3 @@ -43340,8 +43340,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[7].B2[2].B3[8].k - |vpiModule: - \_module: work@small_top.u1.B1[7].B2[2].B3[8]::M3 (work@small_top.u1.B1[7].B2[2].B3[8].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[7].B2[2].B3[8]::M3 (work@small_top.u1.B1[7].B2[2].B3[8].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[7].B2[2].B3[8]) |vpiName:N3 @@ -43368,8 +43368,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[7].B2[2].B3[9].k - |vpiModule: - \_module: work@small_top.u1.B1[7].B2[2].B3[9]::M3 (work@small_top.u1.B1[7].B2[2].B3[9].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[7].B2[2].B3[9]::M3 (work@small_top.u1.B1[7].B2[2].B3[9].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[7].B2[2].B3[9]) |vpiName:N3 @@ -43396,8 +43396,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:j |vpiFullName:work@small_top.u1.B1[7].B2[3].j - |vpiModule: - \_module: work@small_top.u1.B1[7].B2[3]::M2 (work@small_top.u1.B1[7].B2[3].N2), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:26:1, endln:26:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[7].B2[3]::M2 (work@small_top.u1.B1[7].B2[3].N2), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:26:1, endln:26:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[7].B2[3]) |vpiName:N2 @@ -43424,8 +43424,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[7].B2[3].B3[0].k - |vpiModule: - \_module: work@small_top.u1.B1[7].B2[3].B3[0]::M3 (work@small_top.u1.B1[7].B2[3].B3[0].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[7].B2[3].B3[0]::M3 (work@small_top.u1.B1[7].B2[3].B3[0].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[7].B2[3].B3[0]) |vpiName:N3 @@ -43452,8 +43452,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[7].B2[3].B3[1].k - |vpiModule: - \_module: work@small_top.u1.B1[7].B2[3].B3[1]::M3 (work@small_top.u1.B1[7].B2[3].B3[1].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[7].B2[3].B3[1]::M3 (work@small_top.u1.B1[7].B2[3].B3[1].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[7].B2[3].B3[1]) |vpiName:N3 @@ -43480,8 +43480,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[7].B2[3].B3[2].k - |vpiModule: - \_module: work@small_top.u1.B1[7].B2[3].B3[2]::M3 (work@small_top.u1.B1[7].B2[3].B3[2].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[7].B2[3].B3[2]::M3 (work@small_top.u1.B1[7].B2[3].B3[2].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[7].B2[3].B3[2]) |vpiName:N3 @@ -43508,8 +43508,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[7].B2[3].B3[3].k - |vpiModule: - \_module: work@small_top.u1.B1[7].B2[3].B3[3]::M3 (work@small_top.u1.B1[7].B2[3].B3[3].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[7].B2[3].B3[3]::M3 (work@small_top.u1.B1[7].B2[3].B3[3].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[7].B2[3].B3[3]) |vpiName:N3 @@ -43536,8 +43536,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[7].B2[3].B3[4].k - |vpiModule: - \_module: work@small_top.u1.B1[7].B2[3].B3[4]::M3 (work@small_top.u1.B1[7].B2[3].B3[4].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[7].B2[3].B3[4]::M3 (work@small_top.u1.B1[7].B2[3].B3[4].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[7].B2[3].B3[4]) |vpiName:N3 @@ -43564,8 +43564,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[7].B2[3].B3[5].k - |vpiModule: - \_module: work@small_top.u1.B1[7].B2[3].B3[5]::M3 (work@small_top.u1.B1[7].B2[3].B3[5].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[7].B2[3].B3[5]::M3 (work@small_top.u1.B1[7].B2[3].B3[5].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[7].B2[3].B3[5]) |vpiName:N3 @@ -43592,8 +43592,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[7].B2[3].B3[6].k - |vpiModule: - \_module: work@small_top.u1.B1[7].B2[3].B3[6]::M3 (work@small_top.u1.B1[7].B2[3].B3[6].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[7].B2[3].B3[6]::M3 (work@small_top.u1.B1[7].B2[3].B3[6].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[7].B2[3].B3[6]) |vpiName:N3 @@ -43620,8 +43620,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[7].B2[3].B3[7].k - |vpiModule: - \_module: work@small_top.u1.B1[7].B2[3].B3[7]::M3 (work@small_top.u1.B1[7].B2[3].B3[7].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[7].B2[3].B3[7]::M3 (work@small_top.u1.B1[7].B2[3].B3[7].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[7].B2[3].B3[7]) |vpiName:N3 @@ -43648,8 +43648,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[7].B2[3].B3[8].k - |vpiModule: - \_module: work@small_top.u1.B1[7].B2[3].B3[8]::M3 (work@small_top.u1.B1[7].B2[3].B3[8].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[7].B2[3].B3[8]::M3 (work@small_top.u1.B1[7].B2[3].B3[8].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[7].B2[3].B3[8]) |vpiName:N3 @@ -43676,8 +43676,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[7].B2[3].B3[9].k - |vpiModule: - \_module: work@small_top.u1.B1[7].B2[3].B3[9]::M3 (work@small_top.u1.B1[7].B2[3].B3[9].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[7].B2[3].B3[9]::M3 (work@small_top.u1.B1[7].B2[3].B3[9].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[7].B2[3].B3[9]) |vpiName:N3 @@ -43704,8 +43704,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:j |vpiFullName:work@small_top.u1.B1[7].B2[4].j - |vpiModule: - \_module: work@small_top.u1.B1[7].B2[4]::M2 (work@small_top.u1.B1[7].B2[4].N2), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:26:1, endln:26:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[7].B2[4]::M2 (work@small_top.u1.B1[7].B2[4].N2), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:26:1, endln:26:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[7].B2[4]) |vpiName:N2 @@ -43732,8 +43732,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[7].B2[4].B3[0].k - |vpiModule: - \_module: work@small_top.u1.B1[7].B2[4].B3[0]::M3 (work@small_top.u1.B1[7].B2[4].B3[0].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[7].B2[4].B3[0]::M3 (work@small_top.u1.B1[7].B2[4].B3[0].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[7].B2[4].B3[0]) |vpiName:N3 @@ -43760,8 +43760,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[7].B2[4].B3[1].k - |vpiModule: - \_module: work@small_top.u1.B1[7].B2[4].B3[1]::M3 (work@small_top.u1.B1[7].B2[4].B3[1].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[7].B2[4].B3[1]::M3 (work@small_top.u1.B1[7].B2[4].B3[1].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[7].B2[4].B3[1]) |vpiName:N3 @@ -43788,8 +43788,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[7].B2[4].B3[2].k - |vpiModule: - \_module: work@small_top.u1.B1[7].B2[4].B3[2]::M3 (work@small_top.u1.B1[7].B2[4].B3[2].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[7].B2[4].B3[2]::M3 (work@small_top.u1.B1[7].B2[4].B3[2].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[7].B2[4].B3[2]) |vpiName:N3 @@ -43816,8 +43816,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[7].B2[4].B3[3].k - |vpiModule: - \_module: work@small_top.u1.B1[7].B2[4].B3[3]::M3 (work@small_top.u1.B1[7].B2[4].B3[3].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[7].B2[4].B3[3]::M3 (work@small_top.u1.B1[7].B2[4].B3[3].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[7].B2[4].B3[3]) |vpiName:N3 @@ -43844,8 +43844,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[7].B2[4].B3[4].k - |vpiModule: - \_module: work@small_top.u1.B1[7].B2[4].B3[4]::M3 (work@small_top.u1.B1[7].B2[4].B3[4].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[7].B2[4].B3[4]::M3 (work@small_top.u1.B1[7].B2[4].B3[4].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[7].B2[4].B3[4]) |vpiName:N3 @@ -43872,8 +43872,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[7].B2[4].B3[5].k - |vpiModule: - \_module: work@small_top.u1.B1[7].B2[4].B3[5]::M3 (work@small_top.u1.B1[7].B2[4].B3[5].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[7].B2[4].B3[5]::M3 (work@small_top.u1.B1[7].B2[4].B3[5].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[7].B2[4].B3[5]) |vpiName:N3 @@ -43900,8 +43900,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[7].B2[4].B3[6].k - |vpiModule: - \_module: work@small_top.u1.B1[7].B2[4].B3[6]::M3 (work@small_top.u1.B1[7].B2[4].B3[6].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[7].B2[4].B3[6]::M3 (work@small_top.u1.B1[7].B2[4].B3[6].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[7].B2[4].B3[6]) |vpiName:N3 @@ -43928,8 +43928,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[7].B2[4].B3[7].k - |vpiModule: - \_module: work@small_top.u1.B1[7].B2[4].B3[7]::M3 (work@small_top.u1.B1[7].B2[4].B3[7].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[7].B2[4].B3[7]::M3 (work@small_top.u1.B1[7].B2[4].B3[7].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[7].B2[4].B3[7]) |vpiName:N3 @@ -43956,8 +43956,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[7].B2[4].B3[8].k - |vpiModule: - \_module: work@small_top.u1.B1[7].B2[4].B3[8]::M3 (work@small_top.u1.B1[7].B2[4].B3[8].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[7].B2[4].B3[8]::M3 (work@small_top.u1.B1[7].B2[4].B3[8].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[7].B2[4].B3[8]) |vpiName:N3 @@ -43984,8 +43984,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[7].B2[4].B3[9].k - |vpiModule: - \_module: work@small_top.u1.B1[7].B2[4].B3[9]::M3 (work@small_top.u1.B1[7].B2[4].B3[9].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[7].B2[4].B3[9]::M3 (work@small_top.u1.B1[7].B2[4].B3[9].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[7].B2[4].B3[9]) |vpiName:N3 @@ -44012,8 +44012,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:j |vpiFullName:work@small_top.u1.B1[7].B2[5].j - |vpiModule: - \_module: work@small_top.u1.B1[7].B2[5]::M2 (work@small_top.u1.B1[7].B2[5].N2), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:26:1, endln:26:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[7].B2[5]::M2 (work@small_top.u1.B1[7].B2[5].N2), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:26:1, endln:26:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[7].B2[5]) |vpiName:N2 @@ -44040,8 +44040,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[7].B2[5].B3[0].k - |vpiModule: - \_module: work@small_top.u1.B1[7].B2[5].B3[0]::M3 (work@small_top.u1.B1[7].B2[5].B3[0].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[7].B2[5].B3[0]::M3 (work@small_top.u1.B1[7].B2[5].B3[0].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[7].B2[5].B3[0]) |vpiName:N3 @@ -44068,8 +44068,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[7].B2[5].B3[1].k - |vpiModule: - \_module: work@small_top.u1.B1[7].B2[5].B3[1]::M3 (work@small_top.u1.B1[7].B2[5].B3[1].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[7].B2[5].B3[1]::M3 (work@small_top.u1.B1[7].B2[5].B3[1].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[7].B2[5].B3[1]) |vpiName:N3 @@ -44096,8 +44096,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[7].B2[5].B3[2].k - |vpiModule: - \_module: work@small_top.u1.B1[7].B2[5].B3[2]::M3 (work@small_top.u1.B1[7].B2[5].B3[2].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[7].B2[5].B3[2]::M3 (work@small_top.u1.B1[7].B2[5].B3[2].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[7].B2[5].B3[2]) |vpiName:N3 @@ -44124,8 +44124,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[7].B2[5].B3[3].k - |vpiModule: - \_module: work@small_top.u1.B1[7].B2[5].B3[3]::M3 (work@small_top.u1.B1[7].B2[5].B3[3].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[7].B2[5].B3[3]::M3 (work@small_top.u1.B1[7].B2[5].B3[3].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[7].B2[5].B3[3]) |vpiName:N3 @@ -44152,8 +44152,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[7].B2[5].B3[4].k - |vpiModule: - \_module: work@small_top.u1.B1[7].B2[5].B3[4]::M3 (work@small_top.u1.B1[7].B2[5].B3[4].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[7].B2[5].B3[4]::M3 (work@small_top.u1.B1[7].B2[5].B3[4].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[7].B2[5].B3[4]) |vpiName:N3 @@ -44180,8 +44180,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[7].B2[5].B3[5].k - |vpiModule: - \_module: work@small_top.u1.B1[7].B2[5].B3[5]::M3 (work@small_top.u1.B1[7].B2[5].B3[5].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[7].B2[5].B3[5]::M3 (work@small_top.u1.B1[7].B2[5].B3[5].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[7].B2[5].B3[5]) |vpiName:N3 @@ -44208,8 +44208,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[7].B2[5].B3[6].k - |vpiModule: - \_module: work@small_top.u1.B1[7].B2[5].B3[6]::M3 (work@small_top.u1.B1[7].B2[5].B3[6].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[7].B2[5].B3[6]::M3 (work@small_top.u1.B1[7].B2[5].B3[6].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[7].B2[5].B3[6]) |vpiName:N3 @@ -44236,8 +44236,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[7].B2[5].B3[7].k - |vpiModule: - \_module: work@small_top.u1.B1[7].B2[5].B3[7]::M3 (work@small_top.u1.B1[7].B2[5].B3[7].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[7].B2[5].B3[7]::M3 (work@small_top.u1.B1[7].B2[5].B3[7].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[7].B2[5].B3[7]) |vpiName:N3 @@ -44264,8 +44264,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[7].B2[5].B3[8].k - |vpiModule: - \_module: work@small_top.u1.B1[7].B2[5].B3[8]::M3 (work@small_top.u1.B1[7].B2[5].B3[8].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[7].B2[5].B3[8]::M3 (work@small_top.u1.B1[7].B2[5].B3[8].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[7].B2[5].B3[8]) |vpiName:N3 @@ -44292,8 +44292,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[7].B2[5].B3[9].k - |vpiModule: - \_module: work@small_top.u1.B1[7].B2[5].B3[9]::M3 (work@small_top.u1.B1[7].B2[5].B3[9].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[7].B2[5].B3[9]::M3 (work@small_top.u1.B1[7].B2[5].B3[9].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[7].B2[5].B3[9]) |vpiName:N3 @@ -44320,8 +44320,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:j |vpiFullName:work@small_top.u1.B1[7].B2[6].j - |vpiModule: - \_module: work@small_top.u1.B1[7].B2[6]::M2 (work@small_top.u1.B1[7].B2[6].N2), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:26:1, endln:26:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[7].B2[6]::M2 (work@small_top.u1.B1[7].B2[6].N2), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:26:1, endln:26:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[7].B2[6]) |vpiName:N2 @@ -44348,8 +44348,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[7].B2[6].B3[0].k - |vpiModule: - \_module: work@small_top.u1.B1[7].B2[6].B3[0]::M3 (work@small_top.u1.B1[7].B2[6].B3[0].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[7].B2[6].B3[0]::M3 (work@small_top.u1.B1[7].B2[6].B3[0].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[7].B2[6].B3[0]) |vpiName:N3 @@ -44376,8 +44376,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[7].B2[6].B3[1].k - |vpiModule: - \_module: work@small_top.u1.B1[7].B2[6].B3[1]::M3 (work@small_top.u1.B1[7].B2[6].B3[1].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[7].B2[6].B3[1]::M3 (work@small_top.u1.B1[7].B2[6].B3[1].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[7].B2[6].B3[1]) |vpiName:N3 @@ -44404,8 +44404,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[7].B2[6].B3[2].k - |vpiModule: - \_module: work@small_top.u1.B1[7].B2[6].B3[2]::M3 (work@small_top.u1.B1[7].B2[6].B3[2].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[7].B2[6].B3[2]::M3 (work@small_top.u1.B1[7].B2[6].B3[2].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[7].B2[6].B3[2]) |vpiName:N3 @@ -44432,8 +44432,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[7].B2[6].B3[3].k - |vpiModule: - \_module: work@small_top.u1.B1[7].B2[6].B3[3]::M3 (work@small_top.u1.B1[7].B2[6].B3[3].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[7].B2[6].B3[3]::M3 (work@small_top.u1.B1[7].B2[6].B3[3].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[7].B2[6].B3[3]) |vpiName:N3 @@ -44460,8 +44460,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[7].B2[6].B3[4].k - |vpiModule: - \_module: work@small_top.u1.B1[7].B2[6].B3[4]::M3 (work@small_top.u1.B1[7].B2[6].B3[4].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[7].B2[6].B3[4]::M3 (work@small_top.u1.B1[7].B2[6].B3[4].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[7].B2[6].B3[4]) |vpiName:N3 @@ -44488,8 +44488,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[7].B2[6].B3[5].k - |vpiModule: - \_module: work@small_top.u1.B1[7].B2[6].B3[5]::M3 (work@small_top.u1.B1[7].B2[6].B3[5].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[7].B2[6].B3[5]::M3 (work@small_top.u1.B1[7].B2[6].B3[5].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[7].B2[6].B3[5]) |vpiName:N3 @@ -44516,8 +44516,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[7].B2[6].B3[6].k - |vpiModule: - \_module: work@small_top.u1.B1[7].B2[6].B3[6]::M3 (work@small_top.u1.B1[7].B2[6].B3[6].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[7].B2[6].B3[6]::M3 (work@small_top.u1.B1[7].B2[6].B3[6].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[7].B2[6].B3[6]) |vpiName:N3 @@ -44544,8 +44544,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[7].B2[6].B3[7].k - |vpiModule: - \_module: work@small_top.u1.B1[7].B2[6].B3[7]::M3 (work@small_top.u1.B1[7].B2[6].B3[7].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[7].B2[6].B3[7]::M3 (work@small_top.u1.B1[7].B2[6].B3[7].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[7].B2[6].B3[7]) |vpiName:N3 @@ -44572,8 +44572,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[7].B2[6].B3[8].k - |vpiModule: - \_module: work@small_top.u1.B1[7].B2[6].B3[8]::M3 (work@small_top.u1.B1[7].B2[6].B3[8].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[7].B2[6].B3[8]::M3 (work@small_top.u1.B1[7].B2[6].B3[8].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[7].B2[6].B3[8]) |vpiName:N3 @@ -44600,8 +44600,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[7].B2[6].B3[9].k - |vpiModule: - \_module: work@small_top.u1.B1[7].B2[6].B3[9]::M3 (work@small_top.u1.B1[7].B2[6].B3[9].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[7].B2[6].B3[9]::M3 (work@small_top.u1.B1[7].B2[6].B3[9].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[7].B2[6].B3[9]) |vpiName:N3 @@ -44628,8 +44628,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:j |vpiFullName:work@small_top.u1.B1[7].B2[7].j - |vpiModule: - \_module: work@small_top.u1.B1[7].B2[7]::M2 (work@small_top.u1.B1[7].B2[7].N2), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:26:1, endln:26:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[7].B2[7]::M2 (work@small_top.u1.B1[7].B2[7].N2), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:26:1, endln:26:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[7].B2[7]) |vpiName:N2 @@ -44656,8 +44656,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[7].B2[7].B3[0].k - |vpiModule: - \_module: work@small_top.u1.B1[7].B2[7].B3[0]::M3 (work@small_top.u1.B1[7].B2[7].B3[0].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[7].B2[7].B3[0]::M3 (work@small_top.u1.B1[7].B2[7].B3[0].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[7].B2[7].B3[0]) |vpiName:N3 @@ -44684,8 +44684,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[7].B2[7].B3[1].k - |vpiModule: - \_module: work@small_top.u1.B1[7].B2[7].B3[1]::M3 (work@small_top.u1.B1[7].B2[7].B3[1].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[7].B2[7].B3[1]::M3 (work@small_top.u1.B1[7].B2[7].B3[1].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[7].B2[7].B3[1]) |vpiName:N3 @@ -44712,8 +44712,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[7].B2[7].B3[2].k - |vpiModule: - \_module: work@small_top.u1.B1[7].B2[7].B3[2]::M3 (work@small_top.u1.B1[7].B2[7].B3[2].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[7].B2[7].B3[2]::M3 (work@small_top.u1.B1[7].B2[7].B3[2].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[7].B2[7].B3[2]) |vpiName:N3 @@ -44740,8 +44740,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[7].B2[7].B3[3].k - |vpiModule: - \_module: work@small_top.u1.B1[7].B2[7].B3[3]::M3 (work@small_top.u1.B1[7].B2[7].B3[3].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[7].B2[7].B3[3]::M3 (work@small_top.u1.B1[7].B2[7].B3[3].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[7].B2[7].B3[3]) |vpiName:N3 @@ -44768,8 +44768,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[7].B2[7].B3[4].k - |vpiModule: - \_module: work@small_top.u1.B1[7].B2[7].B3[4]::M3 (work@small_top.u1.B1[7].B2[7].B3[4].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[7].B2[7].B3[4]::M3 (work@small_top.u1.B1[7].B2[7].B3[4].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[7].B2[7].B3[4]) |vpiName:N3 @@ -44796,8 +44796,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[7].B2[7].B3[5].k - |vpiModule: - \_module: work@small_top.u1.B1[7].B2[7].B3[5]::M3 (work@small_top.u1.B1[7].B2[7].B3[5].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[7].B2[7].B3[5]::M3 (work@small_top.u1.B1[7].B2[7].B3[5].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[7].B2[7].B3[5]) |vpiName:N3 @@ -44824,8 +44824,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[7].B2[7].B3[6].k - |vpiModule: - \_module: work@small_top.u1.B1[7].B2[7].B3[6]::M3 (work@small_top.u1.B1[7].B2[7].B3[6].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[7].B2[7].B3[6]::M3 (work@small_top.u1.B1[7].B2[7].B3[6].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[7].B2[7].B3[6]) |vpiName:N3 @@ -44852,8 +44852,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[7].B2[7].B3[7].k - |vpiModule: - \_module: work@small_top.u1.B1[7].B2[7].B3[7]::M3 (work@small_top.u1.B1[7].B2[7].B3[7].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[7].B2[7].B3[7]::M3 (work@small_top.u1.B1[7].B2[7].B3[7].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[7].B2[7].B3[7]) |vpiName:N3 @@ -44880,8 +44880,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[7].B2[7].B3[8].k - |vpiModule: - \_module: work@small_top.u1.B1[7].B2[7].B3[8]::M3 (work@small_top.u1.B1[7].B2[7].B3[8].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[7].B2[7].B3[8]::M3 (work@small_top.u1.B1[7].B2[7].B3[8].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[7].B2[7].B3[8]) |vpiName:N3 @@ -44908,8 +44908,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[7].B2[7].B3[9].k - |vpiModule: - \_module: work@small_top.u1.B1[7].B2[7].B3[9]::M3 (work@small_top.u1.B1[7].B2[7].B3[9].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[7].B2[7].B3[9]::M3 (work@small_top.u1.B1[7].B2[7].B3[9].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[7].B2[7].B3[9]) |vpiName:N3 @@ -44936,8 +44936,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:j |vpiFullName:work@small_top.u1.B1[7].B2[8].j - |vpiModule: - \_module: work@small_top.u1.B1[7].B2[8]::M2 (work@small_top.u1.B1[7].B2[8].N2), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:26:1, endln:26:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[7].B2[8]::M2 (work@small_top.u1.B1[7].B2[8].N2), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:26:1, endln:26:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[7].B2[8]) |vpiName:N2 @@ -44964,8 +44964,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[7].B2[8].B3[0].k - |vpiModule: - \_module: work@small_top.u1.B1[7].B2[8].B3[0]::M3 (work@small_top.u1.B1[7].B2[8].B3[0].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[7].B2[8].B3[0]::M3 (work@small_top.u1.B1[7].B2[8].B3[0].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[7].B2[8].B3[0]) |vpiName:N3 @@ -44992,8 +44992,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[7].B2[8].B3[1].k - |vpiModule: - \_module: work@small_top.u1.B1[7].B2[8].B3[1]::M3 (work@small_top.u1.B1[7].B2[8].B3[1].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[7].B2[8].B3[1]::M3 (work@small_top.u1.B1[7].B2[8].B3[1].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[7].B2[8].B3[1]) |vpiName:N3 @@ -45020,8 +45020,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[7].B2[8].B3[2].k - |vpiModule: - \_module: work@small_top.u1.B1[7].B2[8].B3[2]::M3 (work@small_top.u1.B1[7].B2[8].B3[2].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[7].B2[8].B3[2]::M3 (work@small_top.u1.B1[7].B2[8].B3[2].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[7].B2[8].B3[2]) |vpiName:N3 @@ -45048,8 +45048,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[7].B2[8].B3[3].k - |vpiModule: - \_module: work@small_top.u1.B1[7].B2[8].B3[3]::M3 (work@small_top.u1.B1[7].B2[8].B3[3].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[7].B2[8].B3[3]::M3 (work@small_top.u1.B1[7].B2[8].B3[3].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[7].B2[8].B3[3]) |vpiName:N3 @@ -45076,8 +45076,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[7].B2[8].B3[4].k - |vpiModule: - \_module: work@small_top.u1.B1[7].B2[8].B3[4]::M3 (work@small_top.u1.B1[7].B2[8].B3[4].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[7].B2[8].B3[4]::M3 (work@small_top.u1.B1[7].B2[8].B3[4].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[7].B2[8].B3[4]) |vpiName:N3 @@ -45104,8 +45104,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[7].B2[8].B3[5].k - |vpiModule: - \_module: work@small_top.u1.B1[7].B2[8].B3[5]::M3 (work@small_top.u1.B1[7].B2[8].B3[5].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[7].B2[8].B3[5]::M3 (work@small_top.u1.B1[7].B2[8].B3[5].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[7].B2[8].B3[5]) |vpiName:N3 @@ -45132,8 +45132,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[7].B2[8].B3[6].k - |vpiModule: - \_module: work@small_top.u1.B1[7].B2[8].B3[6]::M3 (work@small_top.u1.B1[7].B2[8].B3[6].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[7].B2[8].B3[6]::M3 (work@small_top.u1.B1[7].B2[8].B3[6].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[7].B2[8].B3[6]) |vpiName:N3 @@ -45160,8 +45160,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[7].B2[8].B3[7].k - |vpiModule: - \_module: work@small_top.u1.B1[7].B2[8].B3[7]::M3 (work@small_top.u1.B1[7].B2[8].B3[7].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[7].B2[8].B3[7]::M3 (work@small_top.u1.B1[7].B2[8].B3[7].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[7].B2[8].B3[7]) |vpiName:N3 @@ -45188,8 +45188,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[7].B2[8].B3[8].k - |vpiModule: - \_module: work@small_top.u1.B1[7].B2[8].B3[8]::M3 (work@small_top.u1.B1[7].B2[8].B3[8].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[7].B2[8].B3[8]::M3 (work@small_top.u1.B1[7].B2[8].B3[8].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[7].B2[8].B3[8]) |vpiName:N3 @@ -45216,8 +45216,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[7].B2[8].B3[9].k - |vpiModule: - \_module: work@small_top.u1.B1[7].B2[8].B3[9]::M3 (work@small_top.u1.B1[7].B2[8].B3[9].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[7].B2[8].B3[9]::M3 (work@small_top.u1.B1[7].B2[8].B3[9].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[7].B2[8].B3[9]) |vpiName:N3 @@ -45244,8 +45244,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:j |vpiFullName:work@small_top.u1.B1[7].B2[9].j - |vpiModule: - \_module: work@small_top.u1.B1[7].B2[9]::M2 (work@small_top.u1.B1[7].B2[9].N2), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:26:1, endln:26:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[7].B2[9]::M2 (work@small_top.u1.B1[7].B2[9].N2), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:26:1, endln:26:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[7].B2[9]) |vpiName:N2 @@ -45272,8 +45272,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[7].B2[9].B3[0].k - |vpiModule: - \_module: work@small_top.u1.B1[7].B2[9].B3[0]::M3 (work@small_top.u1.B1[7].B2[9].B3[0].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[7].B2[9].B3[0]::M3 (work@small_top.u1.B1[7].B2[9].B3[0].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[7].B2[9].B3[0]) |vpiName:N3 @@ -45300,8 +45300,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[7].B2[9].B3[1].k - |vpiModule: - \_module: work@small_top.u1.B1[7].B2[9].B3[1]::M3 (work@small_top.u1.B1[7].B2[9].B3[1].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[7].B2[9].B3[1]::M3 (work@small_top.u1.B1[7].B2[9].B3[1].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[7].B2[9].B3[1]) |vpiName:N3 @@ -45328,8 +45328,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[7].B2[9].B3[2].k - |vpiModule: - \_module: work@small_top.u1.B1[7].B2[9].B3[2]::M3 (work@small_top.u1.B1[7].B2[9].B3[2].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[7].B2[9].B3[2]::M3 (work@small_top.u1.B1[7].B2[9].B3[2].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[7].B2[9].B3[2]) |vpiName:N3 @@ -45356,8 +45356,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[7].B2[9].B3[3].k - |vpiModule: - \_module: work@small_top.u1.B1[7].B2[9].B3[3]::M3 (work@small_top.u1.B1[7].B2[9].B3[3].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[7].B2[9].B3[3]::M3 (work@small_top.u1.B1[7].B2[9].B3[3].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[7].B2[9].B3[3]) |vpiName:N3 @@ -45384,8 +45384,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[7].B2[9].B3[4].k - |vpiModule: - \_module: work@small_top.u1.B1[7].B2[9].B3[4]::M3 (work@small_top.u1.B1[7].B2[9].B3[4].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[7].B2[9].B3[4]::M3 (work@small_top.u1.B1[7].B2[9].B3[4].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[7].B2[9].B3[4]) |vpiName:N3 @@ -45412,8 +45412,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[7].B2[9].B3[5].k - |vpiModule: - \_module: work@small_top.u1.B1[7].B2[9].B3[5]::M3 (work@small_top.u1.B1[7].B2[9].B3[5].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[7].B2[9].B3[5]::M3 (work@small_top.u1.B1[7].B2[9].B3[5].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[7].B2[9].B3[5]) |vpiName:N3 @@ -45440,8 +45440,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[7].B2[9].B3[6].k - |vpiModule: - \_module: work@small_top.u1.B1[7].B2[9].B3[6]::M3 (work@small_top.u1.B1[7].B2[9].B3[6].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[7].B2[9].B3[6]::M3 (work@small_top.u1.B1[7].B2[9].B3[6].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[7].B2[9].B3[6]) |vpiName:N3 @@ -45468,8 +45468,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[7].B2[9].B3[7].k - |vpiModule: - \_module: work@small_top.u1.B1[7].B2[9].B3[7]::M3 (work@small_top.u1.B1[7].B2[9].B3[7].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[7].B2[9].B3[7]::M3 (work@small_top.u1.B1[7].B2[9].B3[7].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[7].B2[9].B3[7]) |vpiName:N3 @@ -45496,8 +45496,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[7].B2[9].B3[8].k - |vpiModule: - \_module: work@small_top.u1.B1[7].B2[9].B3[8]::M3 (work@small_top.u1.B1[7].B2[9].B3[8].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[7].B2[9].B3[8]::M3 (work@small_top.u1.B1[7].B2[9].B3[8].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[7].B2[9].B3[8]) |vpiName:N3 @@ -45524,8 +45524,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[7].B2[9].B3[9].k - |vpiModule: - \_module: work@small_top.u1.B1[7].B2[9].B3[9]::M3 (work@small_top.u1.B1[7].B2[9].B3[9].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[7].B2[9].B3[9]::M3 (work@small_top.u1.B1[7].B2[9].B3[9].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[7].B2[9].B3[9]) |vpiName:N3 @@ -45563,8 +45563,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:m |vpiFullName:work@small_top.u1.B1[7].B4.B5[0].m - |vpiModule: - \_module: work@small_top.u1.B1[7].B4.B5[0]::M4 (work@small_top.u1.B1[7].B4.B5[0].N4), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:46:1, endln:46:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[7].B4.B5[0]::M4 (work@small_top.u1.B1[7].B4.B5[0].N4), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:46:1, endln:46:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[7].B4.B5[0]) |vpiName:N4 @@ -45591,8 +45591,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:m |vpiFullName:work@small_top.u1.B1[7].B4.B5[1].m - |vpiModule: - \_module: work@small_top.u1.B1[7].B4.B5[1]::M4 (work@small_top.u1.B1[7].B4.B5[1].N4), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:46:1, endln:46:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[7].B4.B5[1]::M4 (work@small_top.u1.B1[7].B4.B5[1].N4), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:46:1, endln:46:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[7].B4.B5[1]) |vpiName:N4 @@ -45619,8 +45619,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:m |vpiFullName:work@small_top.u1.B1[7].B4.B5[2].m - |vpiModule: - \_module: work@small_top.u1.B1[7].B4.B5[2]::M4 (work@small_top.u1.B1[7].B4.B5[2].N4), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:46:1, endln:46:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[7].B4.B5[2]::M4 (work@small_top.u1.B1[7].B4.B5[2].N4), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:46:1, endln:46:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[7].B4.B5[2]) |vpiName:N4 @@ -45647,8 +45647,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:m |vpiFullName:work@small_top.u1.B1[7].B4.B5[3].m - |vpiModule: - \_module: work@small_top.u1.B1[7].B4.B5[3]::M4 (work@small_top.u1.B1[7].B4.B5[3].N4), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:46:1, endln:46:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[7].B4.B5[3]::M4 (work@small_top.u1.B1[7].B4.B5[3].N4), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:46:1, endln:46:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[7].B4.B5[3]) |vpiName:N4 @@ -45675,8 +45675,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:m |vpiFullName:work@small_top.u1.B1[7].B4.B5[4].m - |vpiModule: - \_module: work@small_top.u1.B1[7].B4.B5[4]::M4 (work@small_top.u1.B1[7].B4.B5[4].N4), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:46:1, endln:46:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[7].B4.B5[4]::M4 (work@small_top.u1.B1[7].B4.B5[4].N4), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:46:1, endln:46:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[7].B4.B5[4]) |vpiName:N4 @@ -45703,8 +45703,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:m |vpiFullName:work@small_top.u1.B1[7].B4.B5[5].m - |vpiModule: - \_module: work@small_top.u1.B1[7].B4.B5[5]::M4 (work@small_top.u1.B1[7].B4.B5[5].N4), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:46:1, endln:46:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[7].B4.B5[5]::M4 (work@small_top.u1.B1[7].B4.B5[5].N4), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:46:1, endln:46:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[7].B4.B5[5]) |vpiName:N4 @@ -45731,8 +45731,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:m |vpiFullName:work@small_top.u1.B1[7].B4.B5[6].m - |vpiModule: - \_module: work@small_top.u1.B1[7].B4.B5[6]::M4 (work@small_top.u1.B1[7].B4.B5[6].N4), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:46:1, endln:46:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[7].B4.B5[6]::M4 (work@small_top.u1.B1[7].B4.B5[6].N4), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:46:1, endln:46:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[7].B4.B5[6]) |vpiName:N4 @@ -45759,8 +45759,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:m |vpiFullName:work@small_top.u1.B1[7].B4.B5[7].m - |vpiModule: - \_module: work@small_top.u1.B1[7].B4.B5[7]::M4 (work@small_top.u1.B1[7].B4.B5[7].N4), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:46:1, endln:46:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[7].B4.B5[7]::M4 (work@small_top.u1.B1[7].B4.B5[7].N4), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:46:1, endln:46:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[7].B4.B5[7]) |vpiName:N4 @@ -45787,8 +45787,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:m |vpiFullName:work@small_top.u1.B1[7].B4.B5[8].m - |vpiModule: - \_module: work@small_top.u1.B1[7].B4.B5[8]::M4 (work@small_top.u1.B1[7].B4.B5[8].N4), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:46:1, endln:46:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[7].B4.B5[8]::M4 (work@small_top.u1.B1[7].B4.B5[8].N4), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:46:1, endln:46:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[7].B4.B5[8]) |vpiName:N4 @@ -45815,8 +45815,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:m |vpiFullName:work@small_top.u1.B1[7].B4.B5[9].m - |vpiModule: - \_module: work@small_top.u1.B1[7].B4.B5[9]::M4 (work@small_top.u1.B1[7].B4.B5[9].N4), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:46:1, endln:46:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[7].B4.B5[9]::M4 (work@small_top.u1.B1[7].B4.B5[9].N4), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:46:1, endln:46:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[7].B4.B5[9]) |vpiName:N4 @@ -45825,7 +45825,7 @@ design: (work@bottom1) |vpiGenScopeArray: \_gen_scope_array: (work@small_top.u1.B1[8]), line:17:1, endln:51:4 |vpiParent: - \_module: work@small_test (work@small_top.u1), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:2:4, endln:2:29 + \_module_inst: work@small_test (work@small_top.u1), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:2:4, endln:2:29 |vpiName:B1[8] |vpiFullName:work@small_top.u1.B1[8] |vpiGenScope: @@ -45843,8 +45843,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:i |vpiFullName:work@small_top.u1.B1[8].i - |vpiModule: - \_module: work@small_top.u1.B1[8]::M1 (work@small_top.u1.B1[8].N1), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:20:1, endln:20:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[8]::M1 (work@small_top.u1.B1[8].N1), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:20:1, endln:20:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[8]) |vpiName:N1 @@ -45871,8 +45871,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:j |vpiFullName:work@small_top.u1.B1[8].B2[0].j - |vpiModule: - \_module: work@small_top.u1.B1[8].B2[0]::M2 (work@small_top.u1.B1[8].B2[0].N2), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:26:1, endln:26:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[8].B2[0]::M2 (work@small_top.u1.B1[8].B2[0].N2), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:26:1, endln:26:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[8].B2[0]) |vpiName:N2 @@ -45899,8 +45899,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[8].B2[0].B3[0].k - |vpiModule: - \_module: work@small_top.u1.B1[8].B2[0].B3[0]::M3 (work@small_top.u1.B1[8].B2[0].B3[0].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[8].B2[0].B3[0]::M3 (work@small_top.u1.B1[8].B2[0].B3[0].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[8].B2[0].B3[0]) |vpiName:N3 @@ -45927,8 +45927,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[8].B2[0].B3[1].k - |vpiModule: - \_module: work@small_top.u1.B1[8].B2[0].B3[1]::M3 (work@small_top.u1.B1[8].B2[0].B3[1].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[8].B2[0].B3[1]::M3 (work@small_top.u1.B1[8].B2[0].B3[1].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[8].B2[0].B3[1]) |vpiName:N3 @@ -45955,8 +45955,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[8].B2[0].B3[2].k - |vpiModule: - \_module: work@small_top.u1.B1[8].B2[0].B3[2]::M3 (work@small_top.u1.B1[8].B2[0].B3[2].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[8].B2[0].B3[2]::M3 (work@small_top.u1.B1[8].B2[0].B3[2].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[8].B2[0].B3[2]) |vpiName:N3 @@ -45983,8 +45983,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[8].B2[0].B3[3].k - |vpiModule: - \_module: work@small_top.u1.B1[8].B2[0].B3[3]::M3 (work@small_top.u1.B1[8].B2[0].B3[3].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[8].B2[0].B3[3]::M3 (work@small_top.u1.B1[8].B2[0].B3[3].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[8].B2[0].B3[3]) |vpiName:N3 @@ -46011,8 +46011,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[8].B2[0].B3[4].k - |vpiModule: - \_module: work@small_top.u1.B1[8].B2[0].B3[4]::M3 (work@small_top.u1.B1[8].B2[0].B3[4].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[8].B2[0].B3[4]::M3 (work@small_top.u1.B1[8].B2[0].B3[4].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[8].B2[0].B3[4]) |vpiName:N3 @@ -46039,8 +46039,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[8].B2[0].B3[5].k - |vpiModule: - \_module: work@small_top.u1.B1[8].B2[0].B3[5]::M3 (work@small_top.u1.B1[8].B2[0].B3[5].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[8].B2[0].B3[5]::M3 (work@small_top.u1.B1[8].B2[0].B3[5].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[8].B2[0].B3[5]) |vpiName:N3 @@ -46067,8 +46067,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[8].B2[0].B3[6].k - |vpiModule: - \_module: work@small_top.u1.B1[8].B2[0].B3[6]::M3 (work@small_top.u1.B1[8].B2[0].B3[6].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[8].B2[0].B3[6]::M3 (work@small_top.u1.B1[8].B2[0].B3[6].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[8].B2[0].B3[6]) |vpiName:N3 @@ -46095,8 +46095,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[8].B2[0].B3[7].k - |vpiModule: - \_module: work@small_top.u1.B1[8].B2[0].B3[7]::M3 (work@small_top.u1.B1[8].B2[0].B3[7].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[8].B2[0].B3[7]::M3 (work@small_top.u1.B1[8].B2[0].B3[7].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[8].B2[0].B3[7]) |vpiName:N3 @@ -46123,8 +46123,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[8].B2[0].B3[8].k - |vpiModule: - \_module: work@small_top.u1.B1[8].B2[0].B3[8]::M3 (work@small_top.u1.B1[8].B2[0].B3[8].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[8].B2[0].B3[8]::M3 (work@small_top.u1.B1[8].B2[0].B3[8].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[8].B2[0].B3[8]) |vpiName:N3 @@ -46151,8 +46151,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[8].B2[0].B3[9].k - |vpiModule: - \_module: work@small_top.u1.B1[8].B2[0].B3[9]::M3 (work@small_top.u1.B1[8].B2[0].B3[9].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[8].B2[0].B3[9]::M3 (work@small_top.u1.B1[8].B2[0].B3[9].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[8].B2[0].B3[9]) |vpiName:N3 @@ -46179,8 +46179,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:j |vpiFullName:work@small_top.u1.B1[8].B2[1].j - |vpiModule: - \_module: work@small_top.u1.B1[8].B2[1]::M2 (work@small_top.u1.B1[8].B2[1].N2), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:26:1, endln:26:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[8].B2[1]::M2 (work@small_top.u1.B1[8].B2[1].N2), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:26:1, endln:26:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[8].B2[1]) |vpiName:N2 @@ -46207,8 +46207,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[8].B2[1].B3[0].k - |vpiModule: - \_module: work@small_top.u1.B1[8].B2[1].B3[0]::M3 (work@small_top.u1.B1[8].B2[1].B3[0].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[8].B2[1].B3[0]::M3 (work@small_top.u1.B1[8].B2[1].B3[0].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[8].B2[1].B3[0]) |vpiName:N3 @@ -46235,8 +46235,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[8].B2[1].B3[1].k - |vpiModule: - \_module: work@small_top.u1.B1[8].B2[1].B3[1]::M3 (work@small_top.u1.B1[8].B2[1].B3[1].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[8].B2[1].B3[1]::M3 (work@small_top.u1.B1[8].B2[1].B3[1].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[8].B2[1].B3[1]) |vpiName:N3 @@ -46263,8 +46263,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[8].B2[1].B3[2].k - |vpiModule: - \_module: work@small_top.u1.B1[8].B2[1].B3[2]::M3 (work@small_top.u1.B1[8].B2[1].B3[2].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[8].B2[1].B3[2]::M3 (work@small_top.u1.B1[8].B2[1].B3[2].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[8].B2[1].B3[2]) |vpiName:N3 @@ -46291,8 +46291,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[8].B2[1].B3[3].k - |vpiModule: - \_module: work@small_top.u1.B1[8].B2[1].B3[3]::M3 (work@small_top.u1.B1[8].B2[1].B3[3].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[8].B2[1].B3[3]::M3 (work@small_top.u1.B1[8].B2[1].B3[3].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[8].B2[1].B3[3]) |vpiName:N3 @@ -46319,8 +46319,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[8].B2[1].B3[4].k - |vpiModule: - \_module: work@small_top.u1.B1[8].B2[1].B3[4]::M3 (work@small_top.u1.B1[8].B2[1].B3[4].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[8].B2[1].B3[4]::M3 (work@small_top.u1.B1[8].B2[1].B3[4].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[8].B2[1].B3[4]) |vpiName:N3 @@ -46347,8 +46347,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[8].B2[1].B3[5].k - |vpiModule: - \_module: work@small_top.u1.B1[8].B2[1].B3[5]::M3 (work@small_top.u1.B1[8].B2[1].B3[5].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[8].B2[1].B3[5]::M3 (work@small_top.u1.B1[8].B2[1].B3[5].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[8].B2[1].B3[5]) |vpiName:N3 @@ -46375,8 +46375,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[8].B2[1].B3[6].k - |vpiModule: - \_module: work@small_top.u1.B1[8].B2[1].B3[6]::M3 (work@small_top.u1.B1[8].B2[1].B3[6].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[8].B2[1].B3[6]::M3 (work@small_top.u1.B1[8].B2[1].B3[6].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[8].B2[1].B3[6]) |vpiName:N3 @@ -46403,8 +46403,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[8].B2[1].B3[7].k - |vpiModule: - \_module: work@small_top.u1.B1[8].B2[1].B3[7]::M3 (work@small_top.u1.B1[8].B2[1].B3[7].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[8].B2[1].B3[7]::M3 (work@small_top.u1.B1[8].B2[1].B3[7].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[8].B2[1].B3[7]) |vpiName:N3 @@ -46431,8 +46431,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[8].B2[1].B3[8].k - |vpiModule: - \_module: work@small_top.u1.B1[8].B2[1].B3[8]::M3 (work@small_top.u1.B1[8].B2[1].B3[8].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[8].B2[1].B3[8]::M3 (work@small_top.u1.B1[8].B2[1].B3[8].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[8].B2[1].B3[8]) |vpiName:N3 @@ -46459,8 +46459,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[8].B2[1].B3[9].k - |vpiModule: - \_module: work@small_top.u1.B1[8].B2[1].B3[9]::M3 (work@small_top.u1.B1[8].B2[1].B3[9].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[8].B2[1].B3[9]::M3 (work@small_top.u1.B1[8].B2[1].B3[9].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[8].B2[1].B3[9]) |vpiName:N3 @@ -46487,8 +46487,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:j |vpiFullName:work@small_top.u1.B1[8].B2[2].j - |vpiModule: - \_module: work@small_top.u1.B1[8].B2[2]::M2 (work@small_top.u1.B1[8].B2[2].N2), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:26:1, endln:26:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[8].B2[2]::M2 (work@small_top.u1.B1[8].B2[2].N2), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:26:1, endln:26:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[8].B2[2]) |vpiName:N2 @@ -46515,8 +46515,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[8].B2[2].B3[0].k - |vpiModule: - \_module: work@small_top.u1.B1[8].B2[2].B3[0]::M3 (work@small_top.u1.B1[8].B2[2].B3[0].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[8].B2[2].B3[0]::M3 (work@small_top.u1.B1[8].B2[2].B3[0].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[8].B2[2].B3[0]) |vpiName:N3 @@ -46543,8 +46543,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[8].B2[2].B3[1].k - |vpiModule: - \_module: work@small_top.u1.B1[8].B2[2].B3[1]::M3 (work@small_top.u1.B1[8].B2[2].B3[1].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[8].B2[2].B3[1]::M3 (work@small_top.u1.B1[8].B2[2].B3[1].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[8].B2[2].B3[1]) |vpiName:N3 @@ -46571,8 +46571,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[8].B2[2].B3[2].k - |vpiModule: - \_module: work@small_top.u1.B1[8].B2[2].B3[2]::M3 (work@small_top.u1.B1[8].B2[2].B3[2].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[8].B2[2].B3[2]::M3 (work@small_top.u1.B1[8].B2[2].B3[2].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[8].B2[2].B3[2]) |vpiName:N3 @@ -46599,8 +46599,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[8].B2[2].B3[3].k - |vpiModule: - \_module: work@small_top.u1.B1[8].B2[2].B3[3]::M3 (work@small_top.u1.B1[8].B2[2].B3[3].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[8].B2[2].B3[3]::M3 (work@small_top.u1.B1[8].B2[2].B3[3].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[8].B2[2].B3[3]) |vpiName:N3 @@ -46627,8 +46627,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[8].B2[2].B3[4].k - |vpiModule: - \_module: work@small_top.u1.B1[8].B2[2].B3[4]::M3 (work@small_top.u1.B1[8].B2[2].B3[4].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[8].B2[2].B3[4]::M3 (work@small_top.u1.B1[8].B2[2].B3[4].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[8].B2[2].B3[4]) |vpiName:N3 @@ -46655,8 +46655,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[8].B2[2].B3[5].k - |vpiModule: - \_module: work@small_top.u1.B1[8].B2[2].B3[5]::M3 (work@small_top.u1.B1[8].B2[2].B3[5].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[8].B2[2].B3[5]::M3 (work@small_top.u1.B1[8].B2[2].B3[5].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[8].B2[2].B3[5]) |vpiName:N3 @@ -46683,8 +46683,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[8].B2[2].B3[6].k - |vpiModule: - \_module: work@small_top.u1.B1[8].B2[2].B3[6]::M3 (work@small_top.u1.B1[8].B2[2].B3[6].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[8].B2[2].B3[6]::M3 (work@small_top.u1.B1[8].B2[2].B3[6].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[8].B2[2].B3[6]) |vpiName:N3 @@ -46711,8 +46711,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[8].B2[2].B3[7].k - |vpiModule: - \_module: work@small_top.u1.B1[8].B2[2].B3[7]::M3 (work@small_top.u1.B1[8].B2[2].B3[7].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[8].B2[2].B3[7]::M3 (work@small_top.u1.B1[8].B2[2].B3[7].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[8].B2[2].B3[7]) |vpiName:N3 @@ -46739,8 +46739,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[8].B2[2].B3[8].k - |vpiModule: - \_module: work@small_top.u1.B1[8].B2[2].B3[8]::M3 (work@small_top.u1.B1[8].B2[2].B3[8].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[8].B2[2].B3[8]::M3 (work@small_top.u1.B1[8].B2[2].B3[8].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[8].B2[2].B3[8]) |vpiName:N3 @@ -46767,8 +46767,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[8].B2[2].B3[9].k - |vpiModule: - \_module: work@small_top.u1.B1[8].B2[2].B3[9]::M3 (work@small_top.u1.B1[8].B2[2].B3[9].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[8].B2[2].B3[9]::M3 (work@small_top.u1.B1[8].B2[2].B3[9].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[8].B2[2].B3[9]) |vpiName:N3 @@ -46795,8 +46795,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:j |vpiFullName:work@small_top.u1.B1[8].B2[3].j - |vpiModule: - \_module: work@small_top.u1.B1[8].B2[3]::M2 (work@small_top.u1.B1[8].B2[3].N2), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:26:1, endln:26:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[8].B2[3]::M2 (work@small_top.u1.B1[8].B2[3].N2), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:26:1, endln:26:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[8].B2[3]) |vpiName:N2 @@ -46823,8 +46823,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[8].B2[3].B3[0].k - |vpiModule: - \_module: work@small_top.u1.B1[8].B2[3].B3[0]::M3 (work@small_top.u1.B1[8].B2[3].B3[0].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[8].B2[3].B3[0]::M3 (work@small_top.u1.B1[8].B2[3].B3[0].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[8].B2[3].B3[0]) |vpiName:N3 @@ -46851,8 +46851,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[8].B2[3].B3[1].k - |vpiModule: - \_module: work@small_top.u1.B1[8].B2[3].B3[1]::M3 (work@small_top.u1.B1[8].B2[3].B3[1].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[8].B2[3].B3[1]::M3 (work@small_top.u1.B1[8].B2[3].B3[1].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[8].B2[3].B3[1]) |vpiName:N3 @@ -46879,8 +46879,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[8].B2[3].B3[2].k - |vpiModule: - \_module: work@small_top.u1.B1[8].B2[3].B3[2]::M3 (work@small_top.u1.B1[8].B2[3].B3[2].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[8].B2[3].B3[2]::M3 (work@small_top.u1.B1[8].B2[3].B3[2].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[8].B2[3].B3[2]) |vpiName:N3 @@ -46907,8 +46907,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[8].B2[3].B3[3].k - |vpiModule: - \_module: work@small_top.u1.B1[8].B2[3].B3[3]::M3 (work@small_top.u1.B1[8].B2[3].B3[3].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[8].B2[3].B3[3]::M3 (work@small_top.u1.B1[8].B2[3].B3[3].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[8].B2[3].B3[3]) |vpiName:N3 @@ -46935,8 +46935,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[8].B2[3].B3[4].k - |vpiModule: - \_module: work@small_top.u1.B1[8].B2[3].B3[4]::M3 (work@small_top.u1.B1[8].B2[3].B3[4].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[8].B2[3].B3[4]::M3 (work@small_top.u1.B1[8].B2[3].B3[4].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[8].B2[3].B3[4]) |vpiName:N3 @@ -46963,8 +46963,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[8].B2[3].B3[5].k - |vpiModule: - \_module: work@small_top.u1.B1[8].B2[3].B3[5]::M3 (work@small_top.u1.B1[8].B2[3].B3[5].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[8].B2[3].B3[5]::M3 (work@small_top.u1.B1[8].B2[3].B3[5].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[8].B2[3].B3[5]) |vpiName:N3 @@ -46991,8 +46991,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[8].B2[3].B3[6].k - |vpiModule: - \_module: work@small_top.u1.B1[8].B2[3].B3[6]::M3 (work@small_top.u1.B1[8].B2[3].B3[6].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[8].B2[3].B3[6]::M3 (work@small_top.u1.B1[8].B2[3].B3[6].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[8].B2[3].B3[6]) |vpiName:N3 @@ -47019,8 +47019,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[8].B2[3].B3[7].k - |vpiModule: - \_module: work@small_top.u1.B1[8].B2[3].B3[7]::M3 (work@small_top.u1.B1[8].B2[3].B3[7].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[8].B2[3].B3[7]::M3 (work@small_top.u1.B1[8].B2[3].B3[7].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[8].B2[3].B3[7]) |vpiName:N3 @@ -47047,8 +47047,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[8].B2[3].B3[8].k - |vpiModule: - \_module: work@small_top.u1.B1[8].B2[3].B3[8]::M3 (work@small_top.u1.B1[8].B2[3].B3[8].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[8].B2[3].B3[8]::M3 (work@small_top.u1.B1[8].B2[3].B3[8].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[8].B2[3].B3[8]) |vpiName:N3 @@ -47075,8 +47075,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[8].B2[3].B3[9].k - |vpiModule: - \_module: work@small_top.u1.B1[8].B2[3].B3[9]::M3 (work@small_top.u1.B1[8].B2[3].B3[9].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[8].B2[3].B3[9]::M3 (work@small_top.u1.B1[8].B2[3].B3[9].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[8].B2[3].B3[9]) |vpiName:N3 @@ -47103,8 +47103,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:j |vpiFullName:work@small_top.u1.B1[8].B2[4].j - |vpiModule: - \_module: work@small_top.u1.B1[8].B2[4]::M2 (work@small_top.u1.B1[8].B2[4].N2), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:26:1, endln:26:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[8].B2[4]::M2 (work@small_top.u1.B1[8].B2[4].N2), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:26:1, endln:26:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[8].B2[4]) |vpiName:N2 @@ -47131,8 +47131,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[8].B2[4].B3[0].k - |vpiModule: - \_module: work@small_top.u1.B1[8].B2[4].B3[0]::M3 (work@small_top.u1.B1[8].B2[4].B3[0].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[8].B2[4].B3[0]::M3 (work@small_top.u1.B1[8].B2[4].B3[0].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[8].B2[4].B3[0]) |vpiName:N3 @@ -47159,8 +47159,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[8].B2[4].B3[1].k - |vpiModule: - \_module: work@small_top.u1.B1[8].B2[4].B3[1]::M3 (work@small_top.u1.B1[8].B2[4].B3[1].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[8].B2[4].B3[1]::M3 (work@small_top.u1.B1[8].B2[4].B3[1].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[8].B2[4].B3[1]) |vpiName:N3 @@ -47187,8 +47187,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[8].B2[4].B3[2].k - |vpiModule: - \_module: work@small_top.u1.B1[8].B2[4].B3[2]::M3 (work@small_top.u1.B1[8].B2[4].B3[2].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[8].B2[4].B3[2]::M3 (work@small_top.u1.B1[8].B2[4].B3[2].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[8].B2[4].B3[2]) |vpiName:N3 @@ -47215,8 +47215,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[8].B2[4].B3[3].k - |vpiModule: - \_module: work@small_top.u1.B1[8].B2[4].B3[3]::M3 (work@small_top.u1.B1[8].B2[4].B3[3].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[8].B2[4].B3[3]::M3 (work@small_top.u1.B1[8].B2[4].B3[3].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[8].B2[4].B3[3]) |vpiName:N3 @@ -47243,8 +47243,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[8].B2[4].B3[4].k - |vpiModule: - \_module: work@small_top.u1.B1[8].B2[4].B3[4]::M3 (work@small_top.u1.B1[8].B2[4].B3[4].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[8].B2[4].B3[4]::M3 (work@small_top.u1.B1[8].B2[4].B3[4].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[8].B2[4].B3[4]) |vpiName:N3 @@ -47271,8 +47271,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[8].B2[4].B3[5].k - |vpiModule: - \_module: work@small_top.u1.B1[8].B2[4].B3[5]::M3 (work@small_top.u1.B1[8].B2[4].B3[5].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[8].B2[4].B3[5]::M3 (work@small_top.u1.B1[8].B2[4].B3[5].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[8].B2[4].B3[5]) |vpiName:N3 @@ -47299,8 +47299,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[8].B2[4].B3[6].k - |vpiModule: - \_module: work@small_top.u1.B1[8].B2[4].B3[6]::M3 (work@small_top.u1.B1[8].B2[4].B3[6].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[8].B2[4].B3[6]::M3 (work@small_top.u1.B1[8].B2[4].B3[6].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[8].B2[4].B3[6]) |vpiName:N3 @@ -47327,8 +47327,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[8].B2[4].B3[7].k - |vpiModule: - \_module: work@small_top.u1.B1[8].B2[4].B3[7]::M3 (work@small_top.u1.B1[8].B2[4].B3[7].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[8].B2[4].B3[7]::M3 (work@small_top.u1.B1[8].B2[4].B3[7].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[8].B2[4].B3[7]) |vpiName:N3 @@ -47355,8 +47355,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[8].B2[4].B3[8].k - |vpiModule: - \_module: work@small_top.u1.B1[8].B2[4].B3[8]::M3 (work@small_top.u1.B1[8].B2[4].B3[8].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[8].B2[4].B3[8]::M3 (work@small_top.u1.B1[8].B2[4].B3[8].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[8].B2[4].B3[8]) |vpiName:N3 @@ -47383,8 +47383,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[8].B2[4].B3[9].k - |vpiModule: - \_module: work@small_top.u1.B1[8].B2[4].B3[9]::M3 (work@small_top.u1.B1[8].B2[4].B3[9].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[8].B2[4].B3[9]::M3 (work@small_top.u1.B1[8].B2[4].B3[9].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[8].B2[4].B3[9]) |vpiName:N3 @@ -47411,8 +47411,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:j |vpiFullName:work@small_top.u1.B1[8].B2[5].j - |vpiModule: - \_module: work@small_top.u1.B1[8].B2[5]::M2 (work@small_top.u1.B1[8].B2[5].N2), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:26:1, endln:26:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[8].B2[5]::M2 (work@small_top.u1.B1[8].B2[5].N2), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:26:1, endln:26:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[8].B2[5]) |vpiName:N2 @@ -47439,8 +47439,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[8].B2[5].B3[0].k - |vpiModule: - \_module: work@small_top.u1.B1[8].B2[5].B3[0]::M3 (work@small_top.u1.B1[8].B2[5].B3[0].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[8].B2[5].B3[0]::M3 (work@small_top.u1.B1[8].B2[5].B3[0].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[8].B2[5].B3[0]) |vpiName:N3 @@ -47467,8 +47467,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[8].B2[5].B3[1].k - |vpiModule: - \_module: work@small_top.u1.B1[8].B2[5].B3[1]::M3 (work@small_top.u1.B1[8].B2[5].B3[1].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[8].B2[5].B3[1]::M3 (work@small_top.u1.B1[8].B2[5].B3[1].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[8].B2[5].B3[1]) |vpiName:N3 @@ -47495,8 +47495,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[8].B2[5].B3[2].k - |vpiModule: - \_module: work@small_top.u1.B1[8].B2[5].B3[2]::M3 (work@small_top.u1.B1[8].B2[5].B3[2].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[8].B2[5].B3[2]::M3 (work@small_top.u1.B1[8].B2[5].B3[2].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[8].B2[5].B3[2]) |vpiName:N3 @@ -47523,8 +47523,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[8].B2[5].B3[3].k - |vpiModule: - \_module: work@small_top.u1.B1[8].B2[5].B3[3]::M3 (work@small_top.u1.B1[8].B2[5].B3[3].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[8].B2[5].B3[3]::M3 (work@small_top.u1.B1[8].B2[5].B3[3].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[8].B2[5].B3[3]) |vpiName:N3 @@ -47551,8 +47551,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[8].B2[5].B3[4].k - |vpiModule: - \_module: work@small_top.u1.B1[8].B2[5].B3[4]::M3 (work@small_top.u1.B1[8].B2[5].B3[4].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[8].B2[5].B3[4]::M3 (work@small_top.u1.B1[8].B2[5].B3[4].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[8].B2[5].B3[4]) |vpiName:N3 @@ -47579,8 +47579,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[8].B2[5].B3[5].k - |vpiModule: - \_module: work@small_top.u1.B1[8].B2[5].B3[5]::M3 (work@small_top.u1.B1[8].B2[5].B3[5].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[8].B2[5].B3[5]::M3 (work@small_top.u1.B1[8].B2[5].B3[5].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[8].B2[5].B3[5]) |vpiName:N3 @@ -47607,8 +47607,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[8].B2[5].B3[6].k - |vpiModule: - \_module: work@small_top.u1.B1[8].B2[5].B3[6]::M3 (work@small_top.u1.B1[8].B2[5].B3[6].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[8].B2[5].B3[6]::M3 (work@small_top.u1.B1[8].B2[5].B3[6].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[8].B2[5].B3[6]) |vpiName:N3 @@ -47635,8 +47635,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[8].B2[5].B3[7].k - |vpiModule: - \_module: work@small_top.u1.B1[8].B2[5].B3[7]::M3 (work@small_top.u1.B1[8].B2[5].B3[7].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[8].B2[5].B3[7]::M3 (work@small_top.u1.B1[8].B2[5].B3[7].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[8].B2[5].B3[7]) |vpiName:N3 @@ -47663,8 +47663,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[8].B2[5].B3[8].k - |vpiModule: - \_module: work@small_top.u1.B1[8].B2[5].B3[8]::M3 (work@small_top.u1.B1[8].B2[5].B3[8].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[8].B2[5].B3[8]::M3 (work@small_top.u1.B1[8].B2[5].B3[8].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[8].B2[5].B3[8]) |vpiName:N3 @@ -47691,8 +47691,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[8].B2[5].B3[9].k - |vpiModule: - \_module: work@small_top.u1.B1[8].B2[5].B3[9]::M3 (work@small_top.u1.B1[8].B2[5].B3[9].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[8].B2[5].B3[9]::M3 (work@small_top.u1.B1[8].B2[5].B3[9].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[8].B2[5].B3[9]) |vpiName:N3 @@ -47719,8 +47719,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:j |vpiFullName:work@small_top.u1.B1[8].B2[6].j - |vpiModule: - \_module: work@small_top.u1.B1[8].B2[6]::M2 (work@small_top.u1.B1[8].B2[6].N2), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:26:1, endln:26:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[8].B2[6]::M2 (work@small_top.u1.B1[8].B2[6].N2), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:26:1, endln:26:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[8].B2[6]) |vpiName:N2 @@ -47747,8 +47747,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[8].B2[6].B3[0].k - |vpiModule: - \_module: work@small_top.u1.B1[8].B2[6].B3[0]::M3 (work@small_top.u1.B1[8].B2[6].B3[0].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[8].B2[6].B3[0]::M3 (work@small_top.u1.B1[8].B2[6].B3[0].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[8].B2[6].B3[0]) |vpiName:N3 @@ -47775,8 +47775,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[8].B2[6].B3[1].k - |vpiModule: - \_module: work@small_top.u1.B1[8].B2[6].B3[1]::M3 (work@small_top.u1.B1[8].B2[6].B3[1].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[8].B2[6].B3[1]::M3 (work@small_top.u1.B1[8].B2[6].B3[1].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[8].B2[6].B3[1]) |vpiName:N3 @@ -47803,8 +47803,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[8].B2[6].B3[2].k - |vpiModule: - \_module: work@small_top.u1.B1[8].B2[6].B3[2]::M3 (work@small_top.u1.B1[8].B2[6].B3[2].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[8].B2[6].B3[2]::M3 (work@small_top.u1.B1[8].B2[6].B3[2].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[8].B2[6].B3[2]) |vpiName:N3 @@ -47831,8 +47831,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[8].B2[6].B3[3].k - |vpiModule: - \_module: work@small_top.u1.B1[8].B2[6].B3[3]::M3 (work@small_top.u1.B1[8].B2[6].B3[3].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[8].B2[6].B3[3]::M3 (work@small_top.u1.B1[8].B2[6].B3[3].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[8].B2[6].B3[3]) |vpiName:N3 @@ -47859,8 +47859,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[8].B2[6].B3[4].k - |vpiModule: - \_module: work@small_top.u1.B1[8].B2[6].B3[4]::M3 (work@small_top.u1.B1[8].B2[6].B3[4].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[8].B2[6].B3[4]::M3 (work@small_top.u1.B1[8].B2[6].B3[4].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[8].B2[6].B3[4]) |vpiName:N3 @@ -47887,8 +47887,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[8].B2[6].B3[5].k - |vpiModule: - \_module: work@small_top.u1.B1[8].B2[6].B3[5]::M3 (work@small_top.u1.B1[8].B2[6].B3[5].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[8].B2[6].B3[5]::M3 (work@small_top.u1.B1[8].B2[6].B3[5].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[8].B2[6].B3[5]) |vpiName:N3 @@ -47915,8 +47915,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[8].B2[6].B3[6].k - |vpiModule: - \_module: work@small_top.u1.B1[8].B2[6].B3[6]::M3 (work@small_top.u1.B1[8].B2[6].B3[6].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[8].B2[6].B3[6]::M3 (work@small_top.u1.B1[8].B2[6].B3[6].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[8].B2[6].B3[6]) |vpiName:N3 @@ -47943,8 +47943,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[8].B2[6].B3[7].k - |vpiModule: - \_module: work@small_top.u1.B1[8].B2[6].B3[7]::M3 (work@small_top.u1.B1[8].B2[6].B3[7].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[8].B2[6].B3[7]::M3 (work@small_top.u1.B1[8].B2[6].B3[7].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[8].B2[6].B3[7]) |vpiName:N3 @@ -47971,8 +47971,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[8].B2[6].B3[8].k - |vpiModule: - \_module: work@small_top.u1.B1[8].B2[6].B3[8]::M3 (work@small_top.u1.B1[8].B2[6].B3[8].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[8].B2[6].B3[8]::M3 (work@small_top.u1.B1[8].B2[6].B3[8].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[8].B2[6].B3[8]) |vpiName:N3 @@ -47999,8 +47999,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[8].B2[6].B3[9].k - |vpiModule: - \_module: work@small_top.u1.B1[8].B2[6].B3[9]::M3 (work@small_top.u1.B1[8].B2[6].B3[9].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[8].B2[6].B3[9]::M3 (work@small_top.u1.B1[8].B2[6].B3[9].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[8].B2[6].B3[9]) |vpiName:N3 @@ -48027,8 +48027,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:j |vpiFullName:work@small_top.u1.B1[8].B2[7].j - |vpiModule: - \_module: work@small_top.u1.B1[8].B2[7]::M2 (work@small_top.u1.B1[8].B2[7].N2), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:26:1, endln:26:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[8].B2[7]::M2 (work@small_top.u1.B1[8].B2[7].N2), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:26:1, endln:26:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[8].B2[7]) |vpiName:N2 @@ -48055,8 +48055,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[8].B2[7].B3[0].k - |vpiModule: - \_module: work@small_top.u1.B1[8].B2[7].B3[0]::M3 (work@small_top.u1.B1[8].B2[7].B3[0].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[8].B2[7].B3[0]::M3 (work@small_top.u1.B1[8].B2[7].B3[0].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[8].B2[7].B3[0]) |vpiName:N3 @@ -48083,8 +48083,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[8].B2[7].B3[1].k - |vpiModule: - \_module: work@small_top.u1.B1[8].B2[7].B3[1]::M3 (work@small_top.u1.B1[8].B2[7].B3[1].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[8].B2[7].B3[1]::M3 (work@small_top.u1.B1[8].B2[7].B3[1].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[8].B2[7].B3[1]) |vpiName:N3 @@ -48111,8 +48111,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[8].B2[7].B3[2].k - |vpiModule: - \_module: work@small_top.u1.B1[8].B2[7].B3[2]::M3 (work@small_top.u1.B1[8].B2[7].B3[2].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[8].B2[7].B3[2]::M3 (work@small_top.u1.B1[8].B2[7].B3[2].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[8].B2[7].B3[2]) |vpiName:N3 @@ -48139,8 +48139,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[8].B2[7].B3[3].k - |vpiModule: - \_module: work@small_top.u1.B1[8].B2[7].B3[3]::M3 (work@small_top.u1.B1[8].B2[7].B3[3].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[8].B2[7].B3[3]::M3 (work@small_top.u1.B1[8].B2[7].B3[3].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[8].B2[7].B3[3]) |vpiName:N3 @@ -48167,8 +48167,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[8].B2[7].B3[4].k - |vpiModule: - \_module: work@small_top.u1.B1[8].B2[7].B3[4]::M3 (work@small_top.u1.B1[8].B2[7].B3[4].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[8].B2[7].B3[4]::M3 (work@small_top.u1.B1[8].B2[7].B3[4].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[8].B2[7].B3[4]) |vpiName:N3 @@ -48195,8 +48195,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[8].B2[7].B3[5].k - |vpiModule: - \_module: work@small_top.u1.B1[8].B2[7].B3[5]::M3 (work@small_top.u1.B1[8].B2[7].B3[5].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[8].B2[7].B3[5]::M3 (work@small_top.u1.B1[8].B2[7].B3[5].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[8].B2[7].B3[5]) |vpiName:N3 @@ -48223,8 +48223,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[8].B2[7].B3[6].k - |vpiModule: - \_module: work@small_top.u1.B1[8].B2[7].B3[6]::M3 (work@small_top.u1.B1[8].B2[7].B3[6].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[8].B2[7].B3[6]::M3 (work@small_top.u1.B1[8].B2[7].B3[6].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[8].B2[7].B3[6]) |vpiName:N3 @@ -48251,8 +48251,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[8].B2[7].B3[7].k - |vpiModule: - \_module: work@small_top.u1.B1[8].B2[7].B3[7]::M3 (work@small_top.u1.B1[8].B2[7].B3[7].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[8].B2[7].B3[7]::M3 (work@small_top.u1.B1[8].B2[7].B3[7].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[8].B2[7].B3[7]) |vpiName:N3 @@ -48279,8 +48279,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[8].B2[7].B3[8].k - |vpiModule: - \_module: work@small_top.u1.B1[8].B2[7].B3[8]::M3 (work@small_top.u1.B1[8].B2[7].B3[8].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[8].B2[7].B3[8]::M3 (work@small_top.u1.B1[8].B2[7].B3[8].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[8].B2[7].B3[8]) |vpiName:N3 @@ -48307,8 +48307,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[8].B2[7].B3[9].k - |vpiModule: - \_module: work@small_top.u1.B1[8].B2[7].B3[9]::M3 (work@small_top.u1.B1[8].B2[7].B3[9].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[8].B2[7].B3[9]::M3 (work@small_top.u1.B1[8].B2[7].B3[9].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[8].B2[7].B3[9]) |vpiName:N3 @@ -48335,8 +48335,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:j |vpiFullName:work@small_top.u1.B1[8].B2[8].j - |vpiModule: - \_module: work@small_top.u1.B1[8].B2[8]::M2 (work@small_top.u1.B1[8].B2[8].N2), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:26:1, endln:26:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[8].B2[8]::M2 (work@small_top.u1.B1[8].B2[8].N2), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:26:1, endln:26:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[8].B2[8]) |vpiName:N2 @@ -48363,8 +48363,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[8].B2[8].B3[0].k - |vpiModule: - \_module: work@small_top.u1.B1[8].B2[8].B3[0]::M3 (work@small_top.u1.B1[8].B2[8].B3[0].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[8].B2[8].B3[0]::M3 (work@small_top.u1.B1[8].B2[8].B3[0].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[8].B2[8].B3[0]) |vpiName:N3 @@ -48391,8 +48391,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[8].B2[8].B3[1].k - |vpiModule: - \_module: work@small_top.u1.B1[8].B2[8].B3[1]::M3 (work@small_top.u1.B1[8].B2[8].B3[1].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[8].B2[8].B3[1]::M3 (work@small_top.u1.B1[8].B2[8].B3[1].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[8].B2[8].B3[1]) |vpiName:N3 @@ -48419,8 +48419,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[8].B2[8].B3[2].k - |vpiModule: - \_module: work@small_top.u1.B1[8].B2[8].B3[2]::M3 (work@small_top.u1.B1[8].B2[8].B3[2].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[8].B2[8].B3[2]::M3 (work@small_top.u1.B1[8].B2[8].B3[2].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[8].B2[8].B3[2]) |vpiName:N3 @@ -48447,8 +48447,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[8].B2[8].B3[3].k - |vpiModule: - \_module: work@small_top.u1.B1[8].B2[8].B3[3]::M3 (work@small_top.u1.B1[8].B2[8].B3[3].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[8].B2[8].B3[3]::M3 (work@small_top.u1.B1[8].B2[8].B3[3].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[8].B2[8].B3[3]) |vpiName:N3 @@ -48475,8 +48475,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[8].B2[8].B3[4].k - |vpiModule: - \_module: work@small_top.u1.B1[8].B2[8].B3[4]::M3 (work@small_top.u1.B1[8].B2[8].B3[4].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[8].B2[8].B3[4]::M3 (work@small_top.u1.B1[8].B2[8].B3[4].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[8].B2[8].B3[4]) |vpiName:N3 @@ -48503,8 +48503,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[8].B2[8].B3[5].k - |vpiModule: - \_module: work@small_top.u1.B1[8].B2[8].B3[5]::M3 (work@small_top.u1.B1[8].B2[8].B3[5].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[8].B2[8].B3[5]::M3 (work@small_top.u1.B1[8].B2[8].B3[5].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[8].B2[8].B3[5]) |vpiName:N3 @@ -48531,8 +48531,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[8].B2[8].B3[6].k - |vpiModule: - \_module: work@small_top.u1.B1[8].B2[8].B3[6]::M3 (work@small_top.u1.B1[8].B2[8].B3[6].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[8].B2[8].B3[6]::M3 (work@small_top.u1.B1[8].B2[8].B3[6].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[8].B2[8].B3[6]) |vpiName:N3 @@ -48559,8 +48559,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[8].B2[8].B3[7].k - |vpiModule: - \_module: work@small_top.u1.B1[8].B2[8].B3[7]::M3 (work@small_top.u1.B1[8].B2[8].B3[7].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[8].B2[8].B3[7]::M3 (work@small_top.u1.B1[8].B2[8].B3[7].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[8].B2[8].B3[7]) |vpiName:N3 @@ -48587,8 +48587,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[8].B2[8].B3[8].k - |vpiModule: - \_module: work@small_top.u1.B1[8].B2[8].B3[8]::M3 (work@small_top.u1.B1[8].B2[8].B3[8].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[8].B2[8].B3[8]::M3 (work@small_top.u1.B1[8].B2[8].B3[8].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[8].B2[8].B3[8]) |vpiName:N3 @@ -48615,8 +48615,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[8].B2[8].B3[9].k - |vpiModule: - \_module: work@small_top.u1.B1[8].B2[8].B3[9]::M3 (work@small_top.u1.B1[8].B2[8].B3[9].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[8].B2[8].B3[9]::M3 (work@small_top.u1.B1[8].B2[8].B3[9].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[8].B2[8].B3[9]) |vpiName:N3 @@ -48643,8 +48643,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:j |vpiFullName:work@small_top.u1.B1[8].B2[9].j - |vpiModule: - \_module: work@small_top.u1.B1[8].B2[9]::M2 (work@small_top.u1.B1[8].B2[9].N2), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:26:1, endln:26:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[8].B2[9]::M2 (work@small_top.u1.B1[8].B2[9].N2), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:26:1, endln:26:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[8].B2[9]) |vpiName:N2 @@ -48671,8 +48671,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[8].B2[9].B3[0].k - |vpiModule: - \_module: work@small_top.u1.B1[8].B2[9].B3[0]::M3 (work@small_top.u1.B1[8].B2[9].B3[0].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[8].B2[9].B3[0]::M3 (work@small_top.u1.B1[8].B2[9].B3[0].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[8].B2[9].B3[0]) |vpiName:N3 @@ -48699,8 +48699,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[8].B2[9].B3[1].k - |vpiModule: - \_module: work@small_top.u1.B1[8].B2[9].B3[1]::M3 (work@small_top.u1.B1[8].B2[9].B3[1].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[8].B2[9].B3[1]::M3 (work@small_top.u1.B1[8].B2[9].B3[1].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[8].B2[9].B3[1]) |vpiName:N3 @@ -48727,8 +48727,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[8].B2[9].B3[2].k - |vpiModule: - \_module: work@small_top.u1.B1[8].B2[9].B3[2]::M3 (work@small_top.u1.B1[8].B2[9].B3[2].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[8].B2[9].B3[2]::M3 (work@small_top.u1.B1[8].B2[9].B3[2].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[8].B2[9].B3[2]) |vpiName:N3 @@ -48755,8 +48755,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[8].B2[9].B3[3].k - |vpiModule: - \_module: work@small_top.u1.B1[8].B2[9].B3[3]::M3 (work@small_top.u1.B1[8].B2[9].B3[3].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[8].B2[9].B3[3]::M3 (work@small_top.u1.B1[8].B2[9].B3[3].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[8].B2[9].B3[3]) |vpiName:N3 @@ -48783,8 +48783,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[8].B2[9].B3[4].k - |vpiModule: - \_module: work@small_top.u1.B1[8].B2[9].B3[4]::M3 (work@small_top.u1.B1[8].B2[9].B3[4].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[8].B2[9].B3[4]::M3 (work@small_top.u1.B1[8].B2[9].B3[4].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[8].B2[9].B3[4]) |vpiName:N3 @@ -48811,8 +48811,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[8].B2[9].B3[5].k - |vpiModule: - \_module: work@small_top.u1.B1[8].B2[9].B3[5]::M3 (work@small_top.u1.B1[8].B2[9].B3[5].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[8].B2[9].B3[5]::M3 (work@small_top.u1.B1[8].B2[9].B3[5].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[8].B2[9].B3[5]) |vpiName:N3 @@ -48839,8 +48839,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[8].B2[9].B3[6].k - |vpiModule: - \_module: work@small_top.u1.B1[8].B2[9].B3[6]::M3 (work@small_top.u1.B1[8].B2[9].B3[6].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[8].B2[9].B3[6]::M3 (work@small_top.u1.B1[8].B2[9].B3[6].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[8].B2[9].B3[6]) |vpiName:N3 @@ -48867,8 +48867,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[8].B2[9].B3[7].k - |vpiModule: - \_module: work@small_top.u1.B1[8].B2[9].B3[7]::M3 (work@small_top.u1.B1[8].B2[9].B3[7].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[8].B2[9].B3[7]::M3 (work@small_top.u1.B1[8].B2[9].B3[7].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[8].B2[9].B3[7]) |vpiName:N3 @@ -48895,8 +48895,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[8].B2[9].B3[8].k - |vpiModule: - \_module: work@small_top.u1.B1[8].B2[9].B3[8]::M3 (work@small_top.u1.B1[8].B2[9].B3[8].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[8].B2[9].B3[8]::M3 (work@small_top.u1.B1[8].B2[9].B3[8].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[8].B2[9].B3[8]) |vpiName:N3 @@ -48923,8 +48923,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[8].B2[9].B3[9].k - |vpiModule: - \_module: work@small_top.u1.B1[8].B2[9].B3[9]::M3 (work@small_top.u1.B1[8].B2[9].B3[9].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[8].B2[9].B3[9]::M3 (work@small_top.u1.B1[8].B2[9].B3[9].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[8].B2[9].B3[9]) |vpiName:N3 @@ -48962,8 +48962,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:m |vpiFullName:work@small_top.u1.B1[8].B4.B5[0].m - |vpiModule: - \_module: work@small_top.u1.B1[8].B4.B5[0]::M4 (work@small_top.u1.B1[8].B4.B5[0].N4), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:46:1, endln:46:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[8].B4.B5[0]::M4 (work@small_top.u1.B1[8].B4.B5[0].N4), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:46:1, endln:46:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[8].B4.B5[0]) |vpiName:N4 @@ -48990,8 +48990,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:m |vpiFullName:work@small_top.u1.B1[8].B4.B5[1].m - |vpiModule: - \_module: work@small_top.u1.B1[8].B4.B5[1]::M4 (work@small_top.u1.B1[8].B4.B5[1].N4), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:46:1, endln:46:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[8].B4.B5[1]::M4 (work@small_top.u1.B1[8].B4.B5[1].N4), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:46:1, endln:46:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[8].B4.B5[1]) |vpiName:N4 @@ -49018,8 +49018,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:m |vpiFullName:work@small_top.u1.B1[8].B4.B5[2].m - |vpiModule: - \_module: work@small_top.u1.B1[8].B4.B5[2]::M4 (work@small_top.u1.B1[8].B4.B5[2].N4), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:46:1, endln:46:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[8].B4.B5[2]::M4 (work@small_top.u1.B1[8].B4.B5[2].N4), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:46:1, endln:46:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[8].B4.B5[2]) |vpiName:N4 @@ -49046,8 +49046,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:m |vpiFullName:work@small_top.u1.B1[8].B4.B5[3].m - |vpiModule: - \_module: work@small_top.u1.B1[8].B4.B5[3]::M4 (work@small_top.u1.B1[8].B4.B5[3].N4), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:46:1, endln:46:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[8].B4.B5[3]::M4 (work@small_top.u1.B1[8].B4.B5[3].N4), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:46:1, endln:46:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[8].B4.B5[3]) |vpiName:N4 @@ -49074,8 +49074,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:m |vpiFullName:work@small_top.u1.B1[8].B4.B5[4].m - |vpiModule: - \_module: work@small_top.u1.B1[8].B4.B5[4]::M4 (work@small_top.u1.B1[8].B4.B5[4].N4), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:46:1, endln:46:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[8].B4.B5[4]::M4 (work@small_top.u1.B1[8].B4.B5[4].N4), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:46:1, endln:46:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[8].B4.B5[4]) |vpiName:N4 @@ -49102,8 +49102,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:m |vpiFullName:work@small_top.u1.B1[8].B4.B5[5].m - |vpiModule: - \_module: work@small_top.u1.B1[8].B4.B5[5]::M4 (work@small_top.u1.B1[8].B4.B5[5].N4), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:46:1, endln:46:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[8].B4.B5[5]::M4 (work@small_top.u1.B1[8].B4.B5[5].N4), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:46:1, endln:46:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[8].B4.B5[5]) |vpiName:N4 @@ -49130,8 +49130,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:m |vpiFullName:work@small_top.u1.B1[8].B4.B5[6].m - |vpiModule: - \_module: work@small_top.u1.B1[8].B4.B5[6]::M4 (work@small_top.u1.B1[8].B4.B5[6].N4), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:46:1, endln:46:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[8].B4.B5[6]::M4 (work@small_top.u1.B1[8].B4.B5[6].N4), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:46:1, endln:46:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[8].B4.B5[6]) |vpiName:N4 @@ -49158,8 +49158,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:m |vpiFullName:work@small_top.u1.B1[8].B4.B5[7].m - |vpiModule: - \_module: work@small_top.u1.B1[8].B4.B5[7]::M4 (work@small_top.u1.B1[8].B4.B5[7].N4), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:46:1, endln:46:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[8].B4.B5[7]::M4 (work@small_top.u1.B1[8].B4.B5[7].N4), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:46:1, endln:46:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[8].B4.B5[7]) |vpiName:N4 @@ -49186,8 +49186,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:m |vpiFullName:work@small_top.u1.B1[8].B4.B5[8].m - |vpiModule: - \_module: work@small_top.u1.B1[8].B4.B5[8]::M4 (work@small_top.u1.B1[8].B4.B5[8].N4), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:46:1, endln:46:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[8].B4.B5[8]::M4 (work@small_top.u1.B1[8].B4.B5[8].N4), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:46:1, endln:46:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[8].B4.B5[8]) |vpiName:N4 @@ -49214,8 +49214,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:m |vpiFullName:work@small_top.u1.B1[8].B4.B5[9].m - |vpiModule: - \_module: work@small_top.u1.B1[8].B4.B5[9]::M4 (work@small_top.u1.B1[8].B4.B5[9].N4), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:46:1, endln:46:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[8].B4.B5[9]::M4 (work@small_top.u1.B1[8].B4.B5[9].N4), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:46:1, endln:46:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[8].B4.B5[9]) |vpiName:N4 @@ -49224,7 +49224,7 @@ design: (work@bottom1) |vpiGenScopeArray: \_gen_scope_array: (work@small_top.u1.B1[9]), line:17:1, endln:51:4 |vpiParent: - \_module: work@small_test (work@small_top.u1), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:2:4, endln:2:29 + \_module_inst: work@small_test (work@small_top.u1), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:2:4, endln:2:29 |vpiName:B1[9] |vpiFullName:work@small_top.u1.B1[9] |vpiGenScope: @@ -49242,8 +49242,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:i |vpiFullName:work@small_top.u1.B1[9].i - |vpiModule: - \_module: work@small_top.u1.B1[9]::M1 (work@small_top.u1.B1[9].N1), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:20:1, endln:20:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[9]::M1 (work@small_top.u1.B1[9].N1), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:20:1, endln:20:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[9]) |vpiName:N1 @@ -49270,8 +49270,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:j |vpiFullName:work@small_top.u1.B1[9].B2[0].j - |vpiModule: - \_module: work@small_top.u1.B1[9].B2[0]::M2 (work@small_top.u1.B1[9].B2[0].N2), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:26:1, endln:26:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[9].B2[0]::M2 (work@small_top.u1.B1[9].B2[0].N2), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:26:1, endln:26:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[9].B2[0]) |vpiName:N2 @@ -49298,8 +49298,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[9].B2[0].B3[0].k - |vpiModule: - \_module: work@small_top.u1.B1[9].B2[0].B3[0]::M3 (work@small_top.u1.B1[9].B2[0].B3[0].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[9].B2[0].B3[0]::M3 (work@small_top.u1.B1[9].B2[0].B3[0].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[9].B2[0].B3[0]) |vpiName:N3 @@ -49326,8 +49326,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[9].B2[0].B3[1].k - |vpiModule: - \_module: work@small_top.u1.B1[9].B2[0].B3[1]::M3 (work@small_top.u1.B1[9].B2[0].B3[1].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[9].B2[0].B3[1]::M3 (work@small_top.u1.B1[9].B2[0].B3[1].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[9].B2[0].B3[1]) |vpiName:N3 @@ -49354,8 +49354,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[9].B2[0].B3[2].k - |vpiModule: - \_module: work@small_top.u1.B1[9].B2[0].B3[2]::M3 (work@small_top.u1.B1[9].B2[0].B3[2].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[9].B2[0].B3[2]::M3 (work@small_top.u1.B1[9].B2[0].B3[2].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[9].B2[0].B3[2]) |vpiName:N3 @@ -49382,8 +49382,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[9].B2[0].B3[3].k - |vpiModule: - \_module: work@small_top.u1.B1[9].B2[0].B3[3]::M3 (work@small_top.u1.B1[9].B2[0].B3[3].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[9].B2[0].B3[3]::M3 (work@small_top.u1.B1[9].B2[0].B3[3].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[9].B2[0].B3[3]) |vpiName:N3 @@ -49410,8 +49410,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[9].B2[0].B3[4].k - |vpiModule: - \_module: work@small_top.u1.B1[9].B2[0].B3[4]::M3 (work@small_top.u1.B1[9].B2[0].B3[4].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[9].B2[0].B3[4]::M3 (work@small_top.u1.B1[9].B2[0].B3[4].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[9].B2[0].B3[4]) |vpiName:N3 @@ -49438,8 +49438,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[9].B2[0].B3[5].k - |vpiModule: - \_module: work@small_top.u1.B1[9].B2[0].B3[5]::M3 (work@small_top.u1.B1[9].B2[0].B3[5].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[9].B2[0].B3[5]::M3 (work@small_top.u1.B1[9].B2[0].B3[5].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[9].B2[0].B3[5]) |vpiName:N3 @@ -49466,8 +49466,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[9].B2[0].B3[6].k - |vpiModule: - \_module: work@small_top.u1.B1[9].B2[0].B3[6]::M3 (work@small_top.u1.B1[9].B2[0].B3[6].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[9].B2[0].B3[6]::M3 (work@small_top.u1.B1[9].B2[0].B3[6].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[9].B2[0].B3[6]) |vpiName:N3 @@ -49494,8 +49494,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[9].B2[0].B3[7].k - |vpiModule: - \_module: work@small_top.u1.B1[9].B2[0].B3[7]::M3 (work@small_top.u1.B1[9].B2[0].B3[7].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[9].B2[0].B3[7]::M3 (work@small_top.u1.B1[9].B2[0].B3[7].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[9].B2[0].B3[7]) |vpiName:N3 @@ -49522,8 +49522,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[9].B2[0].B3[8].k - |vpiModule: - \_module: work@small_top.u1.B1[9].B2[0].B3[8]::M3 (work@small_top.u1.B1[9].B2[0].B3[8].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[9].B2[0].B3[8]::M3 (work@small_top.u1.B1[9].B2[0].B3[8].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[9].B2[0].B3[8]) |vpiName:N3 @@ -49550,8 +49550,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[9].B2[0].B3[9].k - |vpiModule: - \_module: work@small_top.u1.B1[9].B2[0].B3[9]::M3 (work@small_top.u1.B1[9].B2[0].B3[9].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[9].B2[0].B3[9]::M3 (work@small_top.u1.B1[9].B2[0].B3[9].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[9].B2[0].B3[9]) |vpiName:N3 @@ -49578,8 +49578,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:j |vpiFullName:work@small_top.u1.B1[9].B2[1].j - |vpiModule: - \_module: work@small_top.u1.B1[9].B2[1]::M2 (work@small_top.u1.B1[9].B2[1].N2), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:26:1, endln:26:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[9].B2[1]::M2 (work@small_top.u1.B1[9].B2[1].N2), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:26:1, endln:26:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[9].B2[1]) |vpiName:N2 @@ -49606,8 +49606,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[9].B2[1].B3[0].k - |vpiModule: - \_module: work@small_top.u1.B1[9].B2[1].B3[0]::M3 (work@small_top.u1.B1[9].B2[1].B3[0].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[9].B2[1].B3[0]::M3 (work@small_top.u1.B1[9].B2[1].B3[0].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[9].B2[1].B3[0]) |vpiName:N3 @@ -49634,8 +49634,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[9].B2[1].B3[1].k - |vpiModule: - \_module: work@small_top.u1.B1[9].B2[1].B3[1]::M3 (work@small_top.u1.B1[9].B2[1].B3[1].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[9].B2[1].B3[1]::M3 (work@small_top.u1.B1[9].B2[1].B3[1].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[9].B2[1].B3[1]) |vpiName:N3 @@ -49662,8 +49662,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[9].B2[1].B3[2].k - |vpiModule: - \_module: work@small_top.u1.B1[9].B2[1].B3[2]::M3 (work@small_top.u1.B1[9].B2[1].B3[2].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[9].B2[1].B3[2]::M3 (work@small_top.u1.B1[9].B2[1].B3[2].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[9].B2[1].B3[2]) |vpiName:N3 @@ -49690,8 +49690,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[9].B2[1].B3[3].k - |vpiModule: - \_module: work@small_top.u1.B1[9].B2[1].B3[3]::M3 (work@small_top.u1.B1[9].B2[1].B3[3].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[9].B2[1].B3[3]::M3 (work@small_top.u1.B1[9].B2[1].B3[3].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[9].B2[1].B3[3]) |vpiName:N3 @@ -49718,8 +49718,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[9].B2[1].B3[4].k - |vpiModule: - \_module: work@small_top.u1.B1[9].B2[1].B3[4]::M3 (work@small_top.u1.B1[9].B2[1].B3[4].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[9].B2[1].B3[4]::M3 (work@small_top.u1.B1[9].B2[1].B3[4].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[9].B2[1].B3[4]) |vpiName:N3 @@ -49746,8 +49746,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[9].B2[1].B3[5].k - |vpiModule: - \_module: work@small_top.u1.B1[9].B2[1].B3[5]::M3 (work@small_top.u1.B1[9].B2[1].B3[5].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[9].B2[1].B3[5]::M3 (work@small_top.u1.B1[9].B2[1].B3[5].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[9].B2[1].B3[5]) |vpiName:N3 @@ -49774,8 +49774,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[9].B2[1].B3[6].k - |vpiModule: - \_module: work@small_top.u1.B1[9].B2[1].B3[6]::M3 (work@small_top.u1.B1[9].B2[1].B3[6].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[9].B2[1].B3[6]::M3 (work@small_top.u1.B1[9].B2[1].B3[6].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[9].B2[1].B3[6]) |vpiName:N3 @@ -49802,8 +49802,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[9].B2[1].B3[7].k - |vpiModule: - \_module: work@small_top.u1.B1[9].B2[1].B3[7]::M3 (work@small_top.u1.B1[9].B2[1].B3[7].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[9].B2[1].B3[7]::M3 (work@small_top.u1.B1[9].B2[1].B3[7].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[9].B2[1].B3[7]) |vpiName:N3 @@ -49830,8 +49830,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[9].B2[1].B3[8].k - |vpiModule: - \_module: work@small_top.u1.B1[9].B2[1].B3[8]::M3 (work@small_top.u1.B1[9].B2[1].B3[8].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[9].B2[1].B3[8]::M3 (work@small_top.u1.B1[9].B2[1].B3[8].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[9].B2[1].B3[8]) |vpiName:N3 @@ -49858,8 +49858,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[9].B2[1].B3[9].k - |vpiModule: - \_module: work@small_top.u1.B1[9].B2[1].B3[9]::M3 (work@small_top.u1.B1[9].B2[1].B3[9].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[9].B2[1].B3[9]::M3 (work@small_top.u1.B1[9].B2[1].B3[9].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[9].B2[1].B3[9]) |vpiName:N3 @@ -49886,8 +49886,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:j |vpiFullName:work@small_top.u1.B1[9].B2[2].j - |vpiModule: - \_module: work@small_top.u1.B1[9].B2[2]::M2 (work@small_top.u1.B1[9].B2[2].N2), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:26:1, endln:26:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[9].B2[2]::M2 (work@small_top.u1.B1[9].B2[2].N2), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:26:1, endln:26:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[9].B2[2]) |vpiName:N2 @@ -49914,8 +49914,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[9].B2[2].B3[0].k - |vpiModule: - \_module: work@small_top.u1.B1[9].B2[2].B3[0]::M3 (work@small_top.u1.B1[9].B2[2].B3[0].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[9].B2[2].B3[0]::M3 (work@small_top.u1.B1[9].B2[2].B3[0].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[9].B2[2].B3[0]) |vpiName:N3 @@ -49942,8 +49942,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[9].B2[2].B3[1].k - |vpiModule: - \_module: work@small_top.u1.B1[9].B2[2].B3[1]::M3 (work@small_top.u1.B1[9].B2[2].B3[1].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[9].B2[2].B3[1]::M3 (work@small_top.u1.B1[9].B2[2].B3[1].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[9].B2[2].B3[1]) |vpiName:N3 @@ -49970,8 +49970,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[9].B2[2].B3[2].k - |vpiModule: - \_module: work@small_top.u1.B1[9].B2[2].B3[2]::M3 (work@small_top.u1.B1[9].B2[2].B3[2].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[9].B2[2].B3[2]::M3 (work@small_top.u1.B1[9].B2[2].B3[2].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[9].B2[2].B3[2]) |vpiName:N3 @@ -49998,8 +49998,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[9].B2[2].B3[3].k - |vpiModule: - \_module: work@small_top.u1.B1[9].B2[2].B3[3]::M3 (work@small_top.u1.B1[9].B2[2].B3[3].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[9].B2[2].B3[3]::M3 (work@small_top.u1.B1[9].B2[2].B3[3].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[9].B2[2].B3[3]) |vpiName:N3 @@ -50026,8 +50026,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[9].B2[2].B3[4].k - |vpiModule: - \_module: work@small_top.u1.B1[9].B2[2].B3[4]::M3 (work@small_top.u1.B1[9].B2[2].B3[4].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[9].B2[2].B3[4]::M3 (work@small_top.u1.B1[9].B2[2].B3[4].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[9].B2[2].B3[4]) |vpiName:N3 @@ -50054,8 +50054,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[9].B2[2].B3[5].k - |vpiModule: - \_module: work@small_top.u1.B1[9].B2[2].B3[5]::M3 (work@small_top.u1.B1[9].B2[2].B3[5].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[9].B2[2].B3[5]::M3 (work@small_top.u1.B1[9].B2[2].B3[5].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[9].B2[2].B3[5]) |vpiName:N3 @@ -50082,8 +50082,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[9].B2[2].B3[6].k - |vpiModule: - \_module: work@small_top.u1.B1[9].B2[2].B3[6]::M3 (work@small_top.u1.B1[9].B2[2].B3[6].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[9].B2[2].B3[6]::M3 (work@small_top.u1.B1[9].B2[2].B3[6].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[9].B2[2].B3[6]) |vpiName:N3 @@ -50110,8 +50110,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[9].B2[2].B3[7].k - |vpiModule: - \_module: work@small_top.u1.B1[9].B2[2].B3[7]::M3 (work@small_top.u1.B1[9].B2[2].B3[7].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[9].B2[2].B3[7]::M3 (work@small_top.u1.B1[9].B2[2].B3[7].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[9].B2[2].B3[7]) |vpiName:N3 @@ -50138,8 +50138,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[9].B2[2].B3[8].k - |vpiModule: - \_module: work@small_top.u1.B1[9].B2[2].B3[8]::M3 (work@small_top.u1.B1[9].B2[2].B3[8].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[9].B2[2].B3[8]::M3 (work@small_top.u1.B1[9].B2[2].B3[8].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[9].B2[2].B3[8]) |vpiName:N3 @@ -50166,8 +50166,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[9].B2[2].B3[9].k - |vpiModule: - \_module: work@small_top.u1.B1[9].B2[2].B3[9]::M3 (work@small_top.u1.B1[9].B2[2].B3[9].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[9].B2[2].B3[9]::M3 (work@small_top.u1.B1[9].B2[2].B3[9].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[9].B2[2].B3[9]) |vpiName:N3 @@ -50194,8 +50194,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:j |vpiFullName:work@small_top.u1.B1[9].B2[3].j - |vpiModule: - \_module: work@small_top.u1.B1[9].B2[3]::M2 (work@small_top.u1.B1[9].B2[3].N2), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:26:1, endln:26:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[9].B2[3]::M2 (work@small_top.u1.B1[9].B2[3].N2), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:26:1, endln:26:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[9].B2[3]) |vpiName:N2 @@ -50222,8 +50222,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[9].B2[3].B3[0].k - |vpiModule: - \_module: work@small_top.u1.B1[9].B2[3].B3[0]::M3 (work@small_top.u1.B1[9].B2[3].B3[0].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[9].B2[3].B3[0]::M3 (work@small_top.u1.B1[9].B2[3].B3[0].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[9].B2[3].B3[0]) |vpiName:N3 @@ -50250,8 +50250,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[9].B2[3].B3[1].k - |vpiModule: - \_module: work@small_top.u1.B1[9].B2[3].B3[1]::M3 (work@small_top.u1.B1[9].B2[3].B3[1].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[9].B2[3].B3[1]::M3 (work@small_top.u1.B1[9].B2[3].B3[1].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[9].B2[3].B3[1]) |vpiName:N3 @@ -50278,8 +50278,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[9].B2[3].B3[2].k - |vpiModule: - \_module: work@small_top.u1.B1[9].B2[3].B3[2]::M3 (work@small_top.u1.B1[9].B2[3].B3[2].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[9].B2[3].B3[2]::M3 (work@small_top.u1.B1[9].B2[3].B3[2].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[9].B2[3].B3[2]) |vpiName:N3 @@ -50306,8 +50306,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[9].B2[3].B3[3].k - |vpiModule: - \_module: work@small_top.u1.B1[9].B2[3].B3[3]::M3 (work@small_top.u1.B1[9].B2[3].B3[3].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[9].B2[3].B3[3]::M3 (work@small_top.u1.B1[9].B2[3].B3[3].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[9].B2[3].B3[3]) |vpiName:N3 @@ -50334,8 +50334,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[9].B2[3].B3[4].k - |vpiModule: - \_module: work@small_top.u1.B1[9].B2[3].B3[4]::M3 (work@small_top.u1.B1[9].B2[3].B3[4].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[9].B2[3].B3[4]::M3 (work@small_top.u1.B1[9].B2[3].B3[4].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[9].B2[3].B3[4]) |vpiName:N3 @@ -50362,8 +50362,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[9].B2[3].B3[5].k - |vpiModule: - \_module: work@small_top.u1.B1[9].B2[3].B3[5]::M3 (work@small_top.u1.B1[9].B2[3].B3[5].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[9].B2[3].B3[5]::M3 (work@small_top.u1.B1[9].B2[3].B3[5].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[9].B2[3].B3[5]) |vpiName:N3 @@ -50390,8 +50390,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[9].B2[3].B3[6].k - |vpiModule: - \_module: work@small_top.u1.B1[9].B2[3].B3[6]::M3 (work@small_top.u1.B1[9].B2[3].B3[6].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[9].B2[3].B3[6]::M3 (work@small_top.u1.B1[9].B2[3].B3[6].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[9].B2[3].B3[6]) |vpiName:N3 @@ -50418,8 +50418,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[9].B2[3].B3[7].k - |vpiModule: - \_module: work@small_top.u1.B1[9].B2[3].B3[7]::M3 (work@small_top.u1.B1[9].B2[3].B3[7].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[9].B2[3].B3[7]::M3 (work@small_top.u1.B1[9].B2[3].B3[7].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[9].B2[3].B3[7]) |vpiName:N3 @@ -50446,8 +50446,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[9].B2[3].B3[8].k - |vpiModule: - \_module: work@small_top.u1.B1[9].B2[3].B3[8]::M3 (work@small_top.u1.B1[9].B2[3].B3[8].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[9].B2[3].B3[8]::M3 (work@small_top.u1.B1[9].B2[3].B3[8].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[9].B2[3].B3[8]) |vpiName:N3 @@ -50474,8 +50474,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[9].B2[3].B3[9].k - |vpiModule: - \_module: work@small_top.u1.B1[9].B2[3].B3[9]::M3 (work@small_top.u1.B1[9].B2[3].B3[9].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[9].B2[3].B3[9]::M3 (work@small_top.u1.B1[9].B2[3].B3[9].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[9].B2[3].B3[9]) |vpiName:N3 @@ -50502,8 +50502,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:j |vpiFullName:work@small_top.u1.B1[9].B2[4].j - |vpiModule: - \_module: work@small_top.u1.B1[9].B2[4]::M2 (work@small_top.u1.B1[9].B2[4].N2), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:26:1, endln:26:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[9].B2[4]::M2 (work@small_top.u1.B1[9].B2[4].N2), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:26:1, endln:26:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[9].B2[4]) |vpiName:N2 @@ -50530,8 +50530,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[9].B2[4].B3[0].k - |vpiModule: - \_module: work@small_top.u1.B1[9].B2[4].B3[0]::M3 (work@small_top.u1.B1[9].B2[4].B3[0].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[9].B2[4].B3[0]::M3 (work@small_top.u1.B1[9].B2[4].B3[0].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[9].B2[4].B3[0]) |vpiName:N3 @@ -50558,8 +50558,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[9].B2[4].B3[1].k - |vpiModule: - \_module: work@small_top.u1.B1[9].B2[4].B3[1]::M3 (work@small_top.u1.B1[9].B2[4].B3[1].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[9].B2[4].B3[1]::M3 (work@small_top.u1.B1[9].B2[4].B3[1].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[9].B2[4].B3[1]) |vpiName:N3 @@ -50586,8 +50586,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[9].B2[4].B3[2].k - |vpiModule: - \_module: work@small_top.u1.B1[9].B2[4].B3[2]::M3 (work@small_top.u1.B1[9].B2[4].B3[2].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[9].B2[4].B3[2]::M3 (work@small_top.u1.B1[9].B2[4].B3[2].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[9].B2[4].B3[2]) |vpiName:N3 @@ -50614,8 +50614,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[9].B2[4].B3[3].k - |vpiModule: - \_module: work@small_top.u1.B1[9].B2[4].B3[3]::M3 (work@small_top.u1.B1[9].B2[4].B3[3].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[9].B2[4].B3[3]::M3 (work@small_top.u1.B1[9].B2[4].B3[3].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[9].B2[4].B3[3]) |vpiName:N3 @@ -50642,8 +50642,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[9].B2[4].B3[4].k - |vpiModule: - \_module: work@small_top.u1.B1[9].B2[4].B3[4]::M3 (work@small_top.u1.B1[9].B2[4].B3[4].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[9].B2[4].B3[4]::M3 (work@small_top.u1.B1[9].B2[4].B3[4].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[9].B2[4].B3[4]) |vpiName:N3 @@ -50670,8 +50670,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[9].B2[4].B3[5].k - |vpiModule: - \_module: work@small_top.u1.B1[9].B2[4].B3[5]::M3 (work@small_top.u1.B1[9].B2[4].B3[5].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[9].B2[4].B3[5]::M3 (work@small_top.u1.B1[9].B2[4].B3[5].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[9].B2[4].B3[5]) |vpiName:N3 @@ -50698,8 +50698,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[9].B2[4].B3[6].k - |vpiModule: - \_module: work@small_top.u1.B1[9].B2[4].B3[6]::M3 (work@small_top.u1.B1[9].B2[4].B3[6].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[9].B2[4].B3[6]::M3 (work@small_top.u1.B1[9].B2[4].B3[6].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[9].B2[4].B3[6]) |vpiName:N3 @@ -50726,8 +50726,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[9].B2[4].B3[7].k - |vpiModule: - \_module: work@small_top.u1.B1[9].B2[4].B3[7]::M3 (work@small_top.u1.B1[9].B2[4].B3[7].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[9].B2[4].B3[7]::M3 (work@small_top.u1.B1[9].B2[4].B3[7].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[9].B2[4].B3[7]) |vpiName:N3 @@ -50754,8 +50754,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[9].B2[4].B3[8].k - |vpiModule: - \_module: work@small_top.u1.B1[9].B2[4].B3[8]::M3 (work@small_top.u1.B1[9].B2[4].B3[8].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[9].B2[4].B3[8]::M3 (work@small_top.u1.B1[9].B2[4].B3[8].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[9].B2[4].B3[8]) |vpiName:N3 @@ -50782,8 +50782,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[9].B2[4].B3[9].k - |vpiModule: - \_module: work@small_top.u1.B1[9].B2[4].B3[9]::M3 (work@small_top.u1.B1[9].B2[4].B3[9].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[9].B2[4].B3[9]::M3 (work@small_top.u1.B1[9].B2[4].B3[9].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[9].B2[4].B3[9]) |vpiName:N3 @@ -50810,8 +50810,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:j |vpiFullName:work@small_top.u1.B1[9].B2[5].j - |vpiModule: - \_module: work@small_top.u1.B1[9].B2[5]::M2 (work@small_top.u1.B1[9].B2[5].N2), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:26:1, endln:26:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[9].B2[5]::M2 (work@small_top.u1.B1[9].B2[5].N2), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:26:1, endln:26:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[9].B2[5]) |vpiName:N2 @@ -50838,8 +50838,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[9].B2[5].B3[0].k - |vpiModule: - \_module: work@small_top.u1.B1[9].B2[5].B3[0]::M3 (work@small_top.u1.B1[9].B2[5].B3[0].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[9].B2[5].B3[0]::M3 (work@small_top.u1.B1[9].B2[5].B3[0].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[9].B2[5].B3[0]) |vpiName:N3 @@ -50866,8 +50866,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[9].B2[5].B3[1].k - |vpiModule: - \_module: work@small_top.u1.B1[9].B2[5].B3[1]::M3 (work@small_top.u1.B1[9].B2[5].B3[1].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[9].B2[5].B3[1]::M3 (work@small_top.u1.B1[9].B2[5].B3[1].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[9].B2[5].B3[1]) |vpiName:N3 @@ -50894,8 +50894,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[9].B2[5].B3[2].k - |vpiModule: - \_module: work@small_top.u1.B1[9].B2[5].B3[2]::M3 (work@small_top.u1.B1[9].B2[5].B3[2].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[9].B2[5].B3[2]::M3 (work@small_top.u1.B1[9].B2[5].B3[2].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[9].B2[5].B3[2]) |vpiName:N3 @@ -50922,8 +50922,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[9].B2[5].B3[3].k - |vpiModule: - \_module: work@small_top.u1.B1[9].B2[5].B3[3]::M3 (work@small_top.u1.B1[9].B2[5].B3[3].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[9].B2[5].B3[3]::M3 (work@small_top.u1.B1[9].B2[5].B3[3].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[9].B2[5].B3[3]) |vpiName:N3 @@ -50950,8 +50950,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[9].B2[5].B3[4].k - |vpiModule: - \_module: work@small_top.u1.B1[9].B2[5].B3[4]::M3 (work@small_top.u1.B1[9].B2[5].B3[4].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[9].B2[5].B3[4]::M3 (work@small_top.u1.B1[9].B2[5].B3[4].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[9].B2[5].B3[4]) |vpiName:N3 @@ -50978,8 +50978,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[9].B2[5].B3[5].k - |vpiModule: - \_module: work@small_top.u1.B1[9].B2[5].B3[5]::M3 (work@small_top.u1.B1[9].B2[5].B3[5].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[9].B2[5].B3[5]::M3 (work@small_top.u1.B1[9].B2[5].B3[5].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[9].B2[5].B3[5]) |vpiName:N3 @@ -51006,8 +51006,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[9].B2[5].B3[6].k - |vpiModule: - \_module: work@small_top.u1.B1[9].B2[5].B3[6]::M3 (work@small_top.u1.B1[9].B2[5].B3[6].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[9].B2[5].B3[6]::M3 (work@small_top.u1.B1[9].B2[5].B3[6].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[9].B2[5].B3[6]) |vpiName:N3 @@ -51034,8 +51034,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[9].B2[5].B3[7].k - |vpiModule: - \_module: work@small_top.u1.B1[9].B2[5].B3[7]::M3 (work@small_top.u1.B1[9].B2[5].B3[7].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[9].B2[5].B3[7]::M3 (work@small_top.u1.B1[9].B2[5].B3[7].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[9].B2[5].B3[7]) |vpiName:N3 @@ -51062,8 +51062,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[9].B2[5].B3[8].k - |vpiModule: - \_module: work@small_top.u1.B1[9].B2[5].B3[8]::M3 (work@small_top.u1.B1[9].B2[5].B3[8].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[9].B2[5].B3[8]::M3 (work@small_top.u1.B1[9].B2[5].B3[8].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[9].B2[5].B3[8]) |vpiName:N3 @@ -51090,8 +51090,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[9].B2[5].B3[9].k - |vpiModule: - \_module: work@small_top.u1.B1[9].B2[5].B3[9]::M3 (work@small_top.u1.B1[9].B2[5].B3[9].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[9].B2[5].B3[9]::M3 (work@small_top.u1.B1[9].B2[5].B3[9].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[9].B2[5].B3[9]) |vpiName:N3 @@ -51118,8 +51118,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:j |vpiFullName:work@small_top.u1.B1[9].B2[6].j - |vpiModule: - \_module: work@small_top.u1.B1[9].B2[6]::M2 (work@small_top.u1.B1[9].B2[6].N2), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:26:1, endln:26:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[9].B2[6]::M2 (work@small_top.u1.B1[9].B2[6].N2), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:26:1, endln:26:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[9].B2[6]) |vpiName:N2 @@ -51146,8 +51146,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[9].B2[6].B3[0].k - |vpiModule: - \_module: work@small_top.u1.B1[9].B2[6].B3[0]::M3 (work@small_top.u1.B1[9].B2[6].B3[0].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[9].B2[6].B3[0]::M3 (work@small_top.u1.B1[9].B2[6].B3[0].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[9].B2[6].B3[0]) |vpiName:N3 @@ -51174,8 +51174,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[9].B2[6].B3[1].k - |vpiModule: - \_module: work@small_top.u1.B1[9].B2[6].B3[1]::M3 (work@small_top.u1.B1[9].B2[6].B3[1].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[9].B2[6].B3[1]::M3 (work@small_top.u1.B1[9].B2[6].B3[1].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[9].B2[6].B3[1]) |vpiName:N3 @@ -51202,8 +51202,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[9].B2[6].B3[2].k - |vpiModule: - \_module: work@small_top.u1.B1[9].B2[6].B3[2]::M3 (work@small_top.u1.B1[9].B2[6].B3[2].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[9].B2[6].B3[2]::M3 (work@small_top.u1.B1[9].B2[6].B3[2].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[9].B2[6].B3[2]) |vpiName:N3 @@ -51230,8 +51230,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[9].B2[6].B3[3].k - |vpiModule: - \_module: work@small_top.u1.B1[9].B2[6].B3[3]::M3 (work@small_top.u1.B1[9].B2[6].B3[3].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[9].B2[6].B3[3]::M3 (work@small_top.u1.B1[9].B2[6].B3[3].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[9].B2[6].B3[3]) |vpiName:N3 @@ -51258,8 +51258,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[9].B2[6].B3[4].k - |vpiModule: - \_module: work@small_top.u1.B1[9].B2[6].B3[4]::M3 (work@small_top.u1.B1[9].B2[6].B3[4].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[9].B2[6].B3[4]::M3 (work@small_top.u1.B1[9].B2[6].B3[4].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[9].B2[6].B3[4]) |vpiName:N3 @@ -51286,8 +51286,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[9].B2[6].B3[5].k - |vpiModule: - \_module: work@small_top.u1.B1[9].B2[6].B3[5]::M3 (work@small_top.u1.B1[9].B2[6].B3[5].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[9].B2[6].B3[5]::M3 (work@small_top.u1.B1[9].B2[6].B3[5].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[9].B2[6].B3[5]) |vpiName:N3 @@ -51314,8 +51314,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[9].B2[6].B3[6].k - |vpiModule: - \_module: work@small_top.u1.B1[9].B2[6].B3[6]::M3 (work@small_top.u1.B1[9].B2[6].B3[6].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[9].B2[6].B3[6]::M3 (work@small_top.u1.B1[9].B2[6].B3[6].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[9].B2[6].B3[6]) |vpiName:N3 @@ -51342,8 +51342,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[9].B2[6].B3[7].k - |vpiModule: - \_module: work@small_top.u1.B1[9].B2[6].B3[7]::M3 (work@small_top.u1.B1[9].B2[6].B3[7].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[9].B2[6].B3[7]::M3 (work@small_top.u1.B1[9].B2[6].B3[7].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[9].B2[6].B3[7]) |vpiName:N3 @@ -51370,8 +51370,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[9].B2[6].B3[8].k - |vpiModule: - \_module: work@small_top.u1.B1[9].B2[6].B3[8]::M3 (work@small_top.u1.B1[9].B2[6].B3[8].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[9].B2[6].B3[8]::M3 (work@small_top.u1.B1[9].B2[6].B3[8].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[9].B2[6].B3[8]) |vpiName:N3 @@ -51398,8 +51398,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[9].B2[6].B3[9].k - |vpiModule: - \_module: work@small_top.u1.B1[9].B2[6].B3[9]::M3 (work@small_top.u1.B1[9].B2[6].B3[9].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[9].B2[6].B3[9]::M3 (work@small_top.u1.B1[9].B2[6].B3[9].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[9].B2[6].B3[9]) |vpiName:N3 @@ -51426,8 +51426,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:j |vpiFullName:work@small_top.u1.B1[9].B2[7].j - |vpiModule: - \_module: work@small_top.u1.B1[9].B2[7]::M2 (work@small_top.u1.B1[9].B2[7].N2), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:26:1, endln:26:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[9].B2[7]::M2 (work@small_top.u1.B1[9].B2[7].N2), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:26:1, endln:26:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[9].B2[7]) |vpiName:N2 @@ -51454,8 +51454,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[9].B2[7].B3[0].k - |vpiModule: - \_module: work@small_top.u1.B1[9].B2[7].B3[0]::M3 (work@small_top.u1.B1[9].B2[7].B3[0].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[9].B2[7].B3[0]::M3 (work@small_top.u1.B1[9].B2[7].B3[0].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[9].B2[7].B3[0]) |vpiName:N3 @@ -51482,8 +51482,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[9].B2[7].B3[1].k - |vpiModule: - \_module: work@small_top.u1.B1[9].B2[7].B3[1]::M3 (work@small_top.u1.B1[9].B2[7].B3[1].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[9].B2[7].B3[1]::M3 (work@small_top.u1.B1[9].B2[7].B3[1].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[9].B2[7].B3[1]) |vpiName:N3 @@ -51510,8 +51510,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[9].B2[7].B3[2].k - |vpiModule: - \_module: work@small_top.u1.B1[9].B2[7].B3[2]::M3 (work@small_top.u1.B1[9].B2[7].B3[2].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[9].B2[7].B3[2]::M3 (work@small_top.u1.B1[9].B2[7].B3[2].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[9].B2[7].B3[2]) |vpiName:N3 @@ -51538,8 +51538,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[9].B2[7].B3[3].k - |vpiModule: - \_module: work@small_top.u1.B1[9].B2[7].B3[3]::M3 (work@small_top.u1.B1[9].B2[7].B3[3].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[9].B2[7].B3[3]::M3 (work@small_top.u1.B1[9].B2[7].B3[3].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[9].B2[7].B3[3]) |vpiName:N3 @@ -51566,8 +51566,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[9].B2[7].B3[4].k - |vpiModule: - \_module: work@small_top.u1.B1[9].B2[7].B3[4]::M3 (work@small_top.u1.B1[9].B2[7].B3[4].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[9].B2[7].B3[4]::M3 (work@small_top.u1.B1[9].B2[7].B3[4].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[9].B2[7].B3[4]) |vpiName:N3 @@ -51594,8 +51594,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[9].B2[7].B3[5].k - |vpiModule: - \_module: work@small_top.u1.B1[9].B2[7].B3[5]::M3 (work@small_top.u1.B1[9].B2[7].B3[5].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[9].B2[7].B3[5]::M3 (work@small_top.u1.B1[9].B2[7].B3[5].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[9].B2[7].B3[5]) |vpiName:N3 @@ -51622,8 +51622,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[9].B2[7].B3[6].k - |vpiModule: - \_module: work@small_top.u1.B1[9].B2[7].B3[6]::M3 (work@small_top.u1.B1[9].B2[7].B3[6].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[9].B2[7].B3[6]::M3 (work@small_top.u1.B1[9].B2[7].B3[6].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[9].B2[7].B3[6]) |vpiName:N3 @@ -51650,8 +51650,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[9].B2[7].B3[7].k - |vpiModule: - \_module: work@small_top.u1.B1[9].B2[7].B3[7]::M3 (work@small_top.u1.B1[9].B2[7].B3[7].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[9].B2[7].B3[7]::M3 (work@small_top.u1.B1[9].B2[7].B3[7].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[9].B2[7].B3[7]) |vpiName:N3 @@ -51678,8 +51678,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[9].B2[7].B3[8].k - |vpiModule: - \_module: work@small_top.u1.B1[9].B2[7].B3[8]::M3 (work@small_top.u1.B1[9].B2[7].B3[8].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[9].B2[7].B3[8]::M3 (work@small_top.u1.B1[9].B2[7].B3[8].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[9].B2[7].B3[8]) |vpiName:N3 @@ -51706,8 +51706,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[9].B2[7].B3[9].k - |vpiModule: - \_module: work@small_top.u1.B1[9].B2[7].B3[9]::M3 (work@small_top.u1.B1[9].B2[7].B3[9].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[9].B2[7].B3[9]::M3 (work@small_top.u1.B1[9].B2[7].B3[9].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[9].B2[7].B3[9]) |vpiName:N3 @@ -51734,8 +51734,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:j |vpiFullName:work@small_top.u1.B1[9].B2[8].j - |vpiModule: - \_module: work@small_top.u1.B1[9].B2[8]::M2 (work@small_top.u1.B1[9].B2[8].N2), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:26:1, endln:26:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[9].B2[8]::M2 (work@small_top.u1.B1[9].B2[8].N2), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:26:1, endln:26:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[9].B2[8]) |vpiName:N2 @@ -51762,8 +51762,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[9].B2[8].B3[0].k - |vpiModule: - \_module: work@small_top.u1.B1[9].B2[8].B3[0]::M3 (work@small_top.u1.B1[9].B2[8].B3[0].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[9].B2[8].B3[0]::M3 (work@small_top.u1.B1[9].B2[8].B3[0].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[9].B2[8].B3[0]) |vpiName:N3 @@ -51790,8 +51790,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[9].B2[8].B3[1].k - |vpiModule: - \_module: work@small_top.u1.B1[9].B2[8].B3[1]::M3 (work@small_top.u1.B1[9].B2[8].B3[1].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[9].B2[8].B3[1]::M3 (work@small_top.u1.B1[9].B2[8].B3[1].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[9].B2[8].B3[1]) |vpiName:N3 @@ -51818,8 +51818,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[9].B2[8].B3[2].k - |vpiModule: - \_module: work@small_top.u1.B1[9].B2[8].B3[2]::M3 (work@small_top.u1.B1[9].B2[8].B3[2].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[9].B2[8].B3[2]::M3 (work@small_top.u1.B1[9].B2[8].B3[2].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[9].B2[8].B3[2]) |vpiName:N3 @@ -51846,8 +51846,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[9].B2[8].B3[3].k - |vpiModule: - \_module: work@small_top.u1.B1[9].B2[8].B3[3]::M3 (work@small_top.u1.B1[9].B2[8].B3[3].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[9].B2[8].B3[3]::M3 (work@small_top.u1.B1[9].B2[8].B3[3].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[9].B2[8].B3[3]) |vpiName:N3 @@ -51874,8 +51874,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[9].B2[8].B3[4].k - |vpiModule: - \_module: work@small_top.u1.B1[9].B2[8].B3[4]::M3 (work@small_top.u1.B1[9].B2[8].B3[4].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[9].B2[8].B3[4]::M3 (work@small_top.u1.B1[9].B2[8].B3[4].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[9].B2[8].B3[4]) |vpiName:N3 @@ -51902,8 +51902,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[9].B2[8].B3[5].k - |vpiModule: - \_module: work@small_top.u1.B1[9].B2[8].B3[5]::M3 (work@small_top.u1.B1[9].B2[8].B3[5].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[9].B2[8].B3[5]::M3 (work@small_top.u1.B1[9].B2[8].B3[5].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[9].B2[8].B3[5]) |vpiName:N3 @@ -51930,8 +51930,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[9].B2[8].B3[6].k - |vpiModule: - \_module: work@small_top.u1.B1[9].B2[8].B3[6]::M3 (work@small_top.u1.B1[9].B2[8].B3[6].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[9].B2[8].B3[6]::M3 (work@small_top.u1.B1[9].B2[8].B3[6].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[9].B2[8].B3[6]) |vpiName:N3 @@ -51958,8 +51958,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[9].B2[8].B3[7].k - |vpiModule: - \_module: work@small_top.u1.B1[9].B2[8].B3[7]::M3 (work@small_top.u1.B1[9].B2[8].B3[7].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[9].B2[8].B3[7]::M3 (work@small_top.u1.B1[9].B2[8].B3[7].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[9].B2[8].B3[7]) |vpiName:N3 @@ -51986,8 +51986,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[9].B2[8].B3[8].k - |vpiModule: - \_module: work@small_top.u1.B1[9].B2[8].B3[8]::M3 (work@small_top.u1.B1[9].B2[8].B3[8].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[9].B2[8].B3[8]::M3 (work@small_top.u1.B1[9].B2[8].B3[8].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[9].B2[8].B3[8]) |vpiName:N3 @@ -52014,8 +52014,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[9].B2[8].B3[9].k - |vpiModule: - \_module: work@small_top.u1.B1[9].B2[8].B3[9]::M3 (work@small_top.u1.B1[9].B2[8].B3[9].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[9].B2[8].B3[9]::M3 (work@small_top.u1.B1[9].B2[8].B3[9].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[9].B2[8].B3[9]) |vpiName:N3 @@ -52042,8 +52042,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:j |vpiFullName:work@small_top.u1.B1[9].B2[9].j - |vpiModule: - \_module: work@small_top.u1.B1[9].B2[9]::M2 (work@small_top.u1.B1[9].B2[9].N2), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:26:1, endln:26:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[9].B2[9]::M2 (work@small_top.u1.B1[9].B2[9].N2), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:26:1, endln:26:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[9].B2[9]) |vpiName:N2 @@ -52070,8 +52070,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[9].B2[9].B3[0].k - |vpiModule: - \_module: work@small_top.u1.B1[9].B2[9].B3[0]::M3 (work@small_top.u1.B1[9].B2[9].B3[0].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[9].B2[9].B3[0]::M3 (work@small_top.u1.B1[9].B2[9].B3[0].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[9].B2[9].B3[0]) |vpiName:N3 @@ -52098,8 +52098,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[9].B2[9].B3[1].k - |vpiModule: - \_module: work@small_top.u1.B1[9].B2[9].B3[1]::M3 (work@small_top.u1.B1[9].B2[9].B3[1].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[9].B2[9].B3[1]::M3 (work@small_top.u1.B1[9].B2[9].B3[1].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[9].B2[9].B3[1]) |vpiName:N3 @@ -52126,8 +52126,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[9].B2[9].B3[2].k - |vpiModule: - \_module: work@small_top.u1.B1[9].B2[9].B3[2]::M3 (work@small_top.u1.B1[9].B2[9].B3[2].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[9].B2[9].B3[2]::M3 (work@small_top.u1.B1[9].B2[9].B3[2].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[9].B2[9].B3[2]) |vpiName:N3 @@ -52154,8 +52154,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[9].B2[9].B3[3].k - |vpiModule: - \_module: work@small_top.u1.B1[9].B2[9].B3[3]::M3 (work@small_top.u1.B1[9].B2[9].B3[3].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[9].B2[9].B3[3]::M3 (work@small_top.u1.B1[9].B2[9].B3[3].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[9].B2[9].B3[3]) |vpiName:N3 @@ -52182,8 +52182,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[9].B2[9].B3[4].k - |vpiModule: - \_module: work@small_top.u1.B1[9].B2[9].B3[4]::M3 (work@small_top.u1.B1[9].B2[9].B3[4].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[9].B2[9].B3[4]::M3 (work@small_top.u1.B1[9].B2[9].B3[4].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[9].B2[9].B3[4]) |vpiName:N3 @@ -52210,8 +52210,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[9].B2[9].B3[5].k - |vpiModule: - \_module: work@small_top.u1.B1[9].B2[9].B3[5]::M3 (work@small_top.u1.B1[9].B2[9].B3[5].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[9].B2[9].B3[5]::M3 (work@small_top.u1.B1[9].B2[9].B3[5].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[9].B2[9].B3[5]) |vpiName:N3 @@ -52238,8 +52238,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[9].B2[9].B3[6].k - |vpiModule: - \_module: work@small_top.u1.B1[9].B2[9].B3[6]::M3 (work@small_top.u1.B1[9].B2[9].B3[6].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[9].B2[9].B3[6]::M3 (work@small_top.u1.B1[9].B2[9].B3[6].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[9].B2[9].B3[6]) |vpiName:N3 @@ -52266,8 +52266,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[9].B2[9].B3[7].k - |vpiModule: - \_module: work@small_top.u1.B1[9].B2[9].B3[7]::M3 (work@small_top.u1.B1[9].B2[9].B3[7].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[9].B2[9].B3[7]::M3 (work@small_top.u1.B1[9].B2[9].B3[7].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[9].B2[9].B3[7]) |vpiName:N3 @@ -52294,8 +52294,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[9].B2[9].B3[8].k - |vpiModule: - \_module: work@small_top.u1.B1[9].B2[9].B3[8]::M3 (work@small_top.u1.B1[9].B2[9].B3[8].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[9].B2[9].B3[8]::M3 (work@small_top.u1.B1[9].B2[9].B3[8].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[9].B2[9].B3[8]) |vpiName:N3 @@ -52322,8 +52322,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:k |vpiFullName:work@small_top.u1.B1[9].B2[9].B3[9].k - |vpiModule: - \_module: work@small_top.u1.B1[9].B2[9].B3[9]::M3 (work@small_top.u1.B1[9].B2[9].B3[9].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[9].B2[9].B3[9]::M3 (work@small_top.u1.B1[9].B2[9].B3[9].N3), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:33:1, endln:33:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[9].B2[9].B3[9]) |vpiName:N3 @@ -52361,8 +52361,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:m |vpiFullName:work@small_top.u1.B1[9].B4.B5[0].m - |vpiModule: - \_module: work@small_top.u1.B1[9].B4.B5[0]::M4 (work@small_top.u1.B1[9].B4.B5[0].N4), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:46:1, endln:46:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[9].B4.B5[0]::M4 (work@small_top.u1.B1[9].B4.B5[0].N4), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:46:1, endln:46:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[9].B4.B5[0]) |vpiName:N4 @@ -52389,8 +52389,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:m |vpiFullName:work@small_top.u1.B1[9].B4.B5[1].m - |vpiModule: - \_module: work@small_top.u1.B1[9].B4.B5[1]::M4 (work@small_top.u1.B1[9].B4.B5[1].N4), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:46:1, endln:46:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[9].B4.B5[1]::M4 (work@small_top.u1.B1[9].B4.B5[1].N4), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:46:1, endln:46:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[9].B4.B5[1]) |vpiName:N4 @@ -52417,8 +52417,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:m |vpiFullName:work@small_top.u1.B1[9].B4.B5[2].m - |vpiModule: - \_module: work@small_top.u1.B1[9].B4.B5[2]::M4 (work@small_top.u1.B1[9].B4.B5[2].N4), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:46:1, endln:46:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[9].B4.B5[2]::M4 (work@small_top.u1.B1[9].B4.B5[2].N4), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:46:1, endln:46:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[9].B4.B5[2]) |vpiName:N4 @@ -52445,8 +52445,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:m |vpiFullName:work@small_top.u1.B1[9].B4.B5[3].m - |vpiModule: - \_module: work@small_top.u1.B1[9].B4.B5[3]::M4 (work@small_top.u1.B1[9].B4.B5[3].N4), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:46:1, endln:46:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[9].B4.B5[3]::M4 (work@small_top.u1.B1[9].B4.B5[3].N4), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:46:1, endln:46:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[9].B4.B5[3]) |vpiName:N4 @@ -52473,8 +52473,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:m |vpiFullName:work@small_top.u1.B1[9].B4.B5[4].m - |vpiModule: - \_module: work@small_top.u1.B1[9].B4.B5[4]::M4 (work@small_top.u1.B1[9].B4.B5[4].N4), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:46:1, endln:46:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[9].B4.B5[4]::M4 (work@small_top.u1.B1[9].B4.B5[4].N4), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:46:1, endln:46:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[9].B4.B5[4]) |vpiName:N4 @@ -52501,8 +52501,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:m |vpiFullName:work@small_top.u1.B1[9].B4.B5[5].m - |vpiModule: - \_module: work@small_top.u1.B1[9].B4.B5[5]::M4 (work@small_top.u1.B1[9].B4.B5[5].N4), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:46:1, endln:46:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[9].B4.B5[5]::M4 (work@small_top.u1.B1[9].B4.B5[5].N4), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:46:1, endln:46:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[9].B4.B5[5]) |vpiName:N4 @@ -52529,8 +52529,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:m |vpiFullName:work@small_top.u1.B1[9].B4.B5[6].m - |vpiModule: - \_module: work@small_top.u1.B1[9].B4.B5[6]::M4 (work@small_top.u1.B1[9].B4.B5[6].N4), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:46:1, endln:46:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[9].B4.B5[6]::M4 (work@small_top.u1.B1[9].B4.B5[6].N4), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:46:1, endln:46:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[9].B4.B5[6]) |vpiName:N4 @@ -52557,8 +52557,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:m |vpiFullName:work@small_top.u1.B1[9].B4.B5[7].m - |vpiModule: - \_module: work@small_top.u1.B1[9].B4.B5[7]::M4 (work@small_top.u1.B1[9].B4.B5[7].N4), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:46:1, endln:46:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[9].B4.B5[7]::M4 (work@small_top.u1.B1[9].B4.B5[7].N4), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:46:1, endln:46:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[9].B4.B5[7]) |vpiName:N4 @@ -52585,8 +52585,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:m |vpiFullName:work@small_top.u1.B1[9].B4.B5[8].m - |vpiModule: - \_module: work@small_top.u1.B1[9].B4.B5[8]::M4 (work@small_top.u1.B1[9].B4.B5[8].N4), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:46:1, endln:46:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[9].B4.B5[8]::M4 (work@small_top.u1.B1[9].B4.B5[8].N4), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:46:1, endln:46:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[9].B4.B5[8]) |vpiName:N4 @@ -52613,8 +52613,8 @@ design: (work@bottom1) |vpiLocalParam:1 |vpiName:m |vpiFullName:work@small_top.u1.B1[9].B4.B5[9].m - |vpiModule: - \_module: work@small_top.u1.B1[9].B4.B5[9]::M4 (work@small_top.u1.B1[9].B4.B5[9].N4), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:46:1, endln:46:9 + |vpiModuleInst: + \_module_inst: work@small_top.u1.B1[9].B4.B5[9]::M4 (work@small_top.u1.B1[9].B4.B5[9].N4), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:46:1, endln:46:9 |vpiParent: \_gen_scope: (work@small_top.u1.B1[9].B4.B5[9]) |vpiName:N4 diff --git a/tests/UnitElabBlock/UnitElabBlock.log b/tests/UnitElabBlock/UnitElabBlock.log index 0e511786ca..fc52e5fe31 100644 --- a/tests/UnitElabBlock/UnitElabBlock.log +++ b/tests/UnitElabBlock/UnitElabBlock.log @@ -555,7 +555,7 @@ io_decl 11 logic_net 10 logic_typespec 12 logic_var 4 -module 9 +module_inst 9 named_begin 2 named_fork 1 operation 1 diff --git a/tests/UnitElabExternNested/UnitElabExternNested.log b/tests/UnitElabExternNested/UnitElabExternNested.log index 218803fa9e..1d85c09135 100644 --- a/tests/UnitElabExternNested/UnitElabExternNested.log +++ b/tests/UnitElabExternNested/UnitElabExternNested.log @@ -87,7 +87,7 @@ io_decl 11 logic_net 55 logic_typespec 18 logic_var 3 -module 18 +module_inst 18 package 2 param_assign 4 parameter 4 diff --git a/tests/UnitEnum/UnitEnum.log b/tests/UnitEnum/UnitEnum.log index a2b13128cd..ff57ab22c9 100644 --- a/tests/UnitEnum/UnitEnum.log +++ b/tests/UnitEnum/UnitEnum.log @@ -423,7 +423,7 @@ int_var 4 io_decl 11 logic_net 6 logic_var 1 -module 2 +module_inst 2 package 5 task 9 unsupported_typespec 1 @@ -531,7 +531,7 @@ design: (work@top) |vpiTypedef: \_enum_typespec: (pkg::fsm_t_pkg), line:6:1, endln:6:48 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/UnitEnum/top.v, line:14:1, endln:24:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/UnitEnum/top.v, line:14:1, endln:24:10 |vpiName:pkg::fsm_t_pkg |vpiInstance: \_package: pkg (pkg::), file:${SURELOG_DIR}/tests/UnitEnum/top.v, line:2:1, endln:8:11 @@ -938,17 +938,17 @@ design: (work@top) \_int_typespec: |vpiSigned:1 |uhdmallModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/UnitEnum/top.v, line:14:1, endln:24:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/UnitEnum/top.v, line:14:1, endln:24:10 |vpiParent: \_design: (work@top) |vpiFullName:work@top |vpiTypedef: \_enum_typespec: (fsm_t), line:16:1, endln:16:44 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/UnitEnum/top.v, line:14:1, endln:24:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/UnitEnum/top.v, line:14:1, endln:24:10 |vpiName:fsm_t |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/UnitEnum/top.v, line:14:1, endln:24:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/UnitEnum/top.v, line:14:1, endln:24:10 |vpiEnumConst: \_enum_const: (IDLE), line:16:16, endln:16:20 |vpiName:IDLE @@ -981,40 +981,40 @@ design: (work@top) |vpiNet: \_logic_net: (work@top.state), line:18:7, endln:18:12 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/UnitEnum/top.v, line:14:1, endln:24:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/UnitEnum/top.v, line:14:1, endln:24:10 |vpiName:state |vpiFullName:work@top.state |vpiNet: \_logic_net: (work@top.state2), line:19:11, endln:19:17 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/UnitEnum/top.v, line:14:1, endln:24:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/UnitEnum/top.v, line:14:1, endln:24:10 |vpiName:state2 |vpiFullName:work@top.state2 |vpiNet: \_logic_net: (work@top.env), line:21:13, endln:21:16 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/UnitEnum/top.v, line:14:1, endln:24:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/UnitEnum/top.v, line:14:1, endln:24:10 |vpiName:env |vpiFullName:work@top.env |vpiNet: \_logic_net: (work@top.cfg), line:22:16, endln:22:19 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/UnitEnum/top.v, line:14:1, endln:24:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/UnitEnum/top.v, line:14:1, endln:24:10 |vpiName:cfg |vpiFullName:work@top.cfg |vpiNet: \_logic_net: (work@top.cfg), line:23:16, endln:23:19 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/UnitEnum/top.v, line:14:1, endln:24:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/UnitEnum/top.v, line:14:1, endln:24:10 |vpiName:cfg |vpiFullName:work@top.cfg |uhdmtopModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/UnitEnum/top.v, line:14:1, endln:24:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/UnitEnum/top.v, line:14:1, endln:24:10 |vpiName:work@top |vpiVariables: \_enum_var: (work@top.state), line:18:7, endln:18:12 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/UnitEnum/top.v, line:14:1, endln:24:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/UnitEnum/top.v, line:14:1, endln:24:10 |vpiTypespec: \_enum_typespec: (fsm_t), line:16:1, endln:16:44 |vpiName:state @@ -1023,7 +1023,7 @@ design: (work@top) |vpiVariables: \_enum_var: (work@top.state2), line:19:11, endln:19:17 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/UnitEnum/top.v, line:14:1, endln:24:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/UnitEnum/top.v, line:14:1, endln:24:10 |vpiTypespec: \_enum_typespec: (pkg::fsm_t_pkg), line:6:1, endln:6:48 |vpiName:state2 @@ -1032,7 +1032,7 @@ design: (work@top) |vpiVariables: \_class_var: (work@top.cfg), line:22:16, endln:22:19 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/UnitEnum/top.v, line:14:1, endln:24:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/UnitEnum/top.v, line:14:1, endln:24:10 |vpiTypespec: \_class_typespec: (Configuration1), line:22:1, endln:22:15 |vpiName:Configuration1 @@ -1044,7 +1044,7 @@ design: (work@top) |vpiVariables: \_class_var: (work@top.cfg), line:23:16, endln:23:19 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/UnitEnum/top.v, line:14:1, endln:24:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/UnitEnum/top.v, line:14:1, endln:24:10 |vpiTypespec: \_class_typespec: (Configuration2), line:23:1, endln:23:15 |vpiName:Configuration2 @@ -1064,7 +1064,7 @@ design: (work@top) |vpiNet: \_logic_net: (work@top.env), line:21:13, endln:21:16 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/UnitEnum/top.v, line:14:1, endln:24:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/UnitEnum/top.v, line:14:1, endln:24:10 |vpiTypespec: \_unsupported_typespec: (Environment), line:21:1, endln:21:12 |vpiName:Environment diff --git a/tests/UnitForeach/UnitForeach.log b/tests/UnitForeach/UnitForeach.log index afcfd2fff0..e9ef202c9c 100644 --- a/tests/UnitForeach/UnitForeach.log +++ b/tests/UnitForeach/UnitForeach.log @@ -758,7 +758,7 @@ int_var 5 io_decl 13 logic_var 2 method_func_call 23 -module 2 +module_inst 2 operation 1 package 5 range 5 diff --git a/tests/UnitLibrary/UnitLibrary.log b/tests/UnitLibrary/UnitLibrary.log index 236dde6986..22533d86a0 100644 --- a/tests/UnitLibrary/UnitLibrary.log +++ b/tests/UnitLibrary/UnitLibrary.log @@ -286,7 +286,7 @@ int_typespec 9 int_var 4 io_decl 11 logic_var 1 -module 33 +module_inst 33 package 2 task 9 === UHDM Object Stats End === diff --git a/tests/UnitPackage/UnitPackage.log b/tests/UnitPackage/UnitPackage.log index bfdf52c0ca..8bb09d7f58 100644 --- a/tests/UnitPackage/UnitPackage.log +++ b/tests/UnitPackage/UnitPackage.log @@ -1047,7 +1047,7 @@ integer_var 14 io_decl 23 logic_net 5 logic_var 1 -module 8 +module_inst 8 operation 6 package 8 param_assign 5 @@ -1091,7 +1091,7 @@ integer_var 14 io_decl 58 logic_net 5 logic_var 1 -module 9 +module_inst 9 operation 15 package 8 param_assign 6 @@ -2934,7 +2934,7 @@ design: (work@simple_package) \_int_typespec: |vpiSigned:1 |uhdmallModules: -\_module: work@simple_package (work@simple_package), file:${SURELOG_DIR}/tests/UnitPackage/simple_pkg.sv, line:11:1, endln:30:10 +\_module_inst: work@simple_package (work@simple_package), file:${SURELOG_DIR}/tests/UnitPackage/simple_pkg.sv, line:11:1, endln:30:10 |vpiParent: \_design: (work@simple_package) |vpiFullName:work@simple_package @@ -3329,37 +3329,37 @@ design: (work@simple_package) |vpiNet: \_logic_net: (work@simple_package.errCnt), line:5:12, endln:5:18 |vpiParent: - \_module: work@simple_package (work@simple_package), file:${SURELOG_DIR}/tests/UnitPackage/simple_pkg.sv, line:11:1, endln:30:10 + \_module_inst: work@simple_package (work@simple_package), file:${SURELOG_DIR}/tests/UnitPackage/simple_pkg.sv, line:11:1, endln:30:10 |vpiName:errCnt |vpiFullName:work@simple_package.errCnt |vpiNet: \_logic_net: (work@simple_package.warnCnt), line:6:12, endln:6:19 |vpiParent: - \_module: work@simple_package (work@simple_package), file:${SURELOG_DIR}/tests/UnitPackage/simple_pkg.sv, line:11:1, endln:30:10 + \_module_inst: work@simple_package (work@simple_package), file:${SURELOG_DIR}/tests/UnitPackage/simple_pkg.sv, line:11:1, endln:30:10 |vpiName:warnCnt |vpiFullName:work@simple_package.warnCnt |vpiNet: \_logic_net: (work@simple_package.terminate_on_error), line:7:12, endln:7:30 |vpiParent: - \_module: work@simple_package (work@simple_package), file:${SURELOG_DIR}/tests/UnitPackage/simple_pkg.sv, line:11:1, endln:30:10 + \_module_inst: work@simple_package (work@simple_package), file:${SURELOG_DIR}/tests/UnitPackage/simple_pkg.sv, line:11:1, endln:30:10 |vpiName:terminate_on_error |vpiFullName:work@simple_package.terminate_on_error |vpiNet: \_logic_net: (work@simple_package.msgName), line:8:12, endln:8:19 |vpiParent: - \_module: work@simple_package (work@simple_package), file:${SURELOG_DIR}/tests/UnitPackage/simple_pkg.sv, line:11:1, endln:30:10 + \_module_inst: work@simple_package (work@simple_package), file:${SURELOG_DIR}/tests/UnitPackage/simple_pkg.sv, line:11:1, endln:30:10 |vpiName:msgName |vpiFullName:work@simple_package.msgName |vpiNet: \_logic_net: (work@simple_package.value), line:13:8, endln:13:13 |vpiParent: - \_module: work@simple_package (work@simple_package), file:${SURELOG_DIR}/tests/UnitPackage/simple_pkg.sv, line:11:1, endln:30:10 + \_module_inst: work@simple_package (work@simple_package), file:${SURELOG_DIR}/tests/UnitPackage/simple_pkg.sv, line:11:1, endln:30:10 |vpiName:value |vpiFullName:work@simple_package.value |vpiProcess: \_initial: , line:19:1, endln:28:4 |vpiParent: - \_module: work@simple_package (work@simple_package), file:${SURELOG_DIR}/tests/UnitPackage/simple_pkg.sv, line:11:1, endln:30:10 + \_module_inst: work@simple_package (work@simple_package), file:${SURELOG_DIR}/tests/UnitPackage/simple_pkg.sv, line:11:1, endln:30:10 |vpiStmt: \_begin: (work@simple_package), line:19:9, endln:28:4 |vpiParent: @@ -3523,12 +3523,12 @@ design: (work@simple_package) |vpiTask: \_task: (msgPkg::msg_fatal), line:40:3, endln:43:10 |uhdmtopModules: -\_module: work@simple_package (work@simple_package), file:${SURELOG_DIR}/tests/UnitPackage/simple_pkg.sv, line:11:1, endln:30:10 +\_module_inst: work@simple_package (work@simple_package), file:${SURELOG_DIR}/tests/UnitPackage/simple_pkg.sv, line:11:1, endln:30:10 |vpiName:work@simple_package |vpiVariables: \_integer_var: (work@simple_package.errCnt), line:5:12, endln:5:23 |vpiParent: - \_module: work@simple_package (work@simple_package), file:${SURELOG_DIR}/tests/UnitPackage/simple_pkg.sv, line:11:1, endln:30:10 + \_module_inst: work@simple_package (work@simple_package), file:${SURELOG_DIR}/tests/UnitPackage/simple_pkg.sv, line:11:1, endln:30:10 |vpiTypespec: \_integer_typespec: , line:5:3, endln:5:10 |vpiSigned:1 @@ -3545,7 +3545,7 @@ design: (work@simple_package) |vpiVariables: \_integer_var: (work@simple_package.warnCnt), line:6:12, endln:6:23 |vpiParent: - \_module: work@simple_package (work@simple_package), file:${SURELOG_DIR}/tests/UnitPackage/simple_pkg.sv, line:11:1, endln:30:10 + \_module_inst: work@simple_package (work@simple_package), file:${SURELOG_DIR}/tests/UnitPackage/simple_pkg.sv, line:11:1, endln:30:10 |vpiTypespec: \_integer_typespec: , line:6:3, endln:6:10 |vpiSigned:1 @@ -3562,7 +3562,7 @@ design: (work@simple_package) |vpiVariables: \_bit_var: (work@simple_package.terminate_on_error), line:7:12, endln:7:30 |vpiParent: - \_module: work@simple_package (work@simple_package), file:${SURELOG_DIR}/tests/UnitPackage/simple_pkg.sv, line:11:1, endln:30:10 + \_module_inst: work@simple_package (work@simple_package), file:${SURELOG_DIR}/tests/UnitPackage/simple_pkg.sv, line:11:1, endln:30:10 |vpiTypespec: \_bit_typespec: , line:7:3, endln:7:6 |vpiName:terminate_on_error @@ -3577,7 +3577,7 @@ design: (work@simple_package) |vpiVariables: \_string_var: (work@simple_package.msgName), line:8:12, endln:8:28 |vpiParent: - \_module: work@simple_package (work@simple_package), file:${SURELOG_DIR}/tests/UnitPackage/simple_pkg.sv, line:11:1, endln:30:10 + \_module_inst: work@simple_package (work@simple_package), file:${SURELOG_DIR}/tests/UnitPackage/simple_pkg.sv, line:11:1, endln:30:10 |vpiTypespec: \_string_typespec: , line:8:3, endln:8:9 |vpiName:msgName @@ -3593,7 +3593,7 @@ design: (work@simple_package) |vpiVariables: \_enum_var: (work@simple_package.value), line:13:8, endln:13:13 |vpiParent: - \_module: work@simple_package (work@simple_package), file:${SURELOG_DIR}/tests/UnitPackage/simple_pkg.sv, line:11:1, endln:30:10 + \_module_inst: work@simple_package (work@simple_package), file:${SURELOG_DIR}/tests/UnitPackage/simple_pkg.sv, line:11:1, endln:30:10 |vpiTypespec: \_enum_typespec: (definesPkg::bool), line:10:3, endln:10:36 |vpiName:value @@ -3611,12 +3611,12 @@ design: (work@simple_package) |vpiTaskFunc: \_task: (msgPkg::initMsgPkg), line:12:3, endln:15:10 |vpiParent: - \_module: work@simple_package (work@simple_package), file:${SURELOG_DIR}/tests/UnitPackage/simple_pkg.sv, line:11:1, endln:30:10 + \_module_inst: work@simple_package (work@simple_package), file:${SURELOG_DIR}/tests/UnitPackage/simple_pkg.sv, line:11:1, endln:30:10 |vpiName:initMsgPkg |vpiFullName:msgPkg::initMsgPkg |vpiVisibility:1 |vpiParent: - \_module: work@simple_package (work@simple_package), file:${SURELOG_DIR}/tests/UnitPackage/simple_pkg.sv, line:11:1, endln:30:10 + \_module_inst: work@simple_package (work@simple_package), file:${SURELOG_DIR}/tests/UnitPackage/simple_pkg.sv, line:11:1, endln:30:10 |vpiIODecl: \_io_decl: (mName), line:12:27, endln:12:32 |vpiParent: @@ -3683,16 +3683,16 @@ design: (work@simple_package) |vpiActual: \_string_var: (work@simple_package.msgName), line:8:12, endln:8:28 |vpiInstance: - \_module: work@simple_package (work@simple_package), file:${SURELOG_DIR}/tests/UnitPackage/simple_pkg.sv, line:11:1, endln:30:10 + \_module_inst: work@simple_package (work@simple_package), file:${SURELOG_DIR}/tests/UnitPackage/simple_pkg.sv, line:11:1, endln:30:10 |vpiTaskFunc: \_task: (msgPkg::msg_info), line:19:3, endln:21:10 |vpiParent: - \_module: work@simple_package (work@simple_package), file:${SURELOG_DIR}/tests/UnitPackage/simple_pkg.sv, line:11:1, endln:30:10 + \_module_inst: work@simple_package (work@simple_package), file:${SURELOG_DIR}/tests/UnitPackage/simple_pkg.sv, line:11:1, endln:30:10 |vpiName:msg_info |vpiFullName:msgPkg::msg_info |vpiVisibility:1 |vpiParent: - \_module: work@simple_package (work@simple_package), file:${SURELOG_DIR}/tests/UnitPackage/simple_pkg.sv, line:11:1, endln:30:10 + \_module_inst: work@simple_package (work@simple_package), file:${SURELOG_DIR}/tests/UnitPackage/simple_pkg.sv, line:11:1, endln:30:10 |vpiIODecl: \_io_decl: (msg), line:19:26, endln:19:29 |vpiParent: @@ -3730,16 +3730,16 @@ design: (work@simple_package) \_io_decl: (msg), line:19:26, endln:19:29 |vpiName:$display |vpiInstance: - \_module: work@simple_package (work@simple_package), file:${SURELOG_DIR}/tests/UnitPackage/simple_pkg.sv, line:11:1, endln:30:10 + \_module_inst: work@simple_package (work@simple_package), file:${SURELOG_DIR}/tests/UnitPackage/simple_pkg.sv, line:11:1, endln:30:10 |vpiTaskFunc: \_task: (msgPkg::msg_warn), line:25:3, endln:28:10 |vpiParent: - \_module: work@simple_package (work@simple_package), file:${SURELOG_DIR}/tests/UnitPackage/simple_pkg.sv, line:11:1, endln:30:10 + \_module_inst: work@simple_package (work@simple_package), file:${SURELOG_DIR}/tests/UnitPackage/simple_pkg.sv, line:11:1, endln:30:10 |vpiName:msg_warn |vpiFullName:msgPkg::msg_warn |vpiVisibility:1 |vpiParent: - \_module: work@simple_package (work@simple_package), file:${SURELOG_DIR}/tests/UnitPackage/simple_pkg.sv, line:11:1, endln:30:10 + \_module_inst: work@simple_package (work@simple_package), file:${SURELOG_DIR}/tests/UnitPackage/simple_pkg.sv, line:11:1, endln:30:10 |vpiIODecl: \_io_decl: (msg), line:25:26, endln:25:29 |vpiParent: @@ -3795,16 +3795,16 @@ design: (work@simple_package) |vpiActual: \_integer_var: (work@simple_package.warnCnt), line:6:12, endln:6:23 |vpiInstance: - \_module: work@simple_package (work@simple_package), file:${SURELOG_DIR}/tests/UnitPackage/simple_pkg.sv, line:11:1, endln:30:10 + \_module_inst: work@simple_package (work@simple_package), file:${SURELOG_DIR}/tests/UnitPackage/simple_pkg.sv, line:11:1, endln:30:10 |vpiTaskFunc: \_task: (msgPkg::msg_error), line:32:3, endln:36:10 |vpiParent: - \_module: work@simple_package (work@simple_package), file:${SURELOG_DIR}/tests/UnitPackage/simple_pkg.sv, line:11:1, endln:30:10 + \_module_inst: work@simple_package (work@simple_package), file:${SURELOG_DIR}/tests/UnitPackage/simple_pkg.sv, line:11:1, endln:30:10 |vpiName:msg_error |vpiFullName:msgPkg::msg_error |vpiVisibility:1 |vpiParent: - \_module: work@simple_package (work@simple_package), file:${SURELOG_DIR}/tests/UnitPackage/simple_pkg.sv, line:11:1, endln:30:10 + \_module_inst: work@simple_package (work@simple_package), file:${SURELOG_DIR}/tests/UnitPackage/simple_pkg.sv, line:11:1, endln:30:10 |vpiIODecl: \_io_decl: (msg), line:32:27, endln:32:30 |vpiParent: @@ -3877,16 +3877,16 @@ design: (work@simple_package) \_if_stmt: , line:35:5, endln:35:37 |vpiName:$finish |vpiInstance: - \_module: work@simple_package (work@simple_package), file:${SURELOG_DIR}/tests/UnitPackage/simple_pkg.sv, line:11:1, endln:30:10 + \_module_inst: work@simple_package (work@simple_package), file:${SURELOG_DIR}/tests/UnitPackage/simple_pkg.sv, line:11:1, endln:30:10 |vpiTaskFunc: \_task: (msgPkg::msg_fatal), line:40:3, endln:43:10 |vpiParent: - \_module: work@simple_package (work@simple_package), file:${SURELOG_DIR}/tests/UnitPackage/simple_pkg.sv, line:11:1, endln:30:10 + \_module_inst: work@simple_package (work@simple_package), file:${SURELOG_DIR}/tests/UnitPackage/simple_pkg.sv, line:11:1, endln:30:10 |vpiName:msg_fatal |vpiFullName:msgPkg::msg_fatal |vpiVisibility:1 |vpiParent: - \_module: work@simple_package (work@simple_package), file:${SURELOG_DIR}/tests/UnitPackage/simple_pkg.sv, line:11:1, endln:30:10 + \_module_inst: work@simple_package (work@simple_package), file:${SURELOG_DIR}/tests/UnitPackage/simple_pkg.sv, line:11:1, endln:30:10 |vpiIODecl: \_io_decl: (msg), line:40:27, endln:40:30 |vpiParent: @@ -3934,18 +3934,18 @@ design: (work@simple_package) \_begin: (work@simple_package.msg_fatal) |vpiName:$finish |vpiInstance: - \_module: work@simple_package (work@simple_package), file:${SURELOG_DIR}/tests/UnitPackage/simple_pkg.sv, line:11:1, endln:30:10 + \_module_inst: work@simple_package (work@simple_package), file:${SURELOG_DIR}/tests/UnitPackage/simple_pkg.sv, line:11:1, endln:30:10 |vpiTaskFunc: \_function: (msgPkg::getErrCnt), line:47:3, endln:49:14 |vpiParent: - \_module: work@simple_package (work@simple_package), file:${SURELOG_DIR}/tests/UnitPackage/simple_pkg.sv, line:11:1, endln:30:10 + \_module_inst: work@simple_package (work@simple_package), file:${SURELOG_DIR}/tests/UnitPackage/simple_pkg.sv, line:11:1, endln:30:10 |vpiName:getErrCnt |vpiFullName:msgPkg::getErrCnt |vpiVisibility:1 |vpiReturn: \_integer_var: , line:47:12, endln:47:19 |vpiParent: - \_module: work@simple_package (work@simple_package), file:${SURELOG_DIR}/tests/UnitPackage/simple_pkg.sv, line:11:1, endln:30:10 + \_module_inst: work@simple_package (work@simple_package), file:${SURELOG_DIR}/tests/UnitPackage/simple_pkg.sv, line:11:1, endln:30:10 |vpiStmt: \_assignment: , line:48:5, endln:48:23 |vpiParent: @@ -3969,18 +3969,18 @@ design: (work@simple_package) |vpiActual: \_integer_var: , line:47:12, endln:47:19 |vpiInstance: - \_module: work@simple_package (work@simple_package), file:${SURELOG_DIR}/tests/UnitPackage/simple_pkg.sv, line:11:1, endln:30:10 + \_module_inst: work@simple_package (work@simple_package), file:${SURELOG_DIR}/tests/UnitPackage/simple_pkg.sv, line:11:1, endln:30:10 |vpiTaskFunc: \_function: (msgPkg::getWarnCnt), line:53:3, endln:55:14 |vpiParent: - \_module: work@simple_package (work@simple_package), file:${SURELOG_DIR}/tests/UnitPackage/simple_pkg.sv, line:11:1, endln:30:10 + \_module_inst: work@simple_package (work@simple_package), file:${SURELOG_DIR}/tests/UnitPackage/simple_pkg.sv, line:11:1, endln:30:10 |vpiName:getWarnCnt |vpiFullName:msgPkg::getWarnCnt |vpiVisibility:1 |vpiReturn: \_integer_var: , line:53:12, endln:53:19 |vpiParent: - \_module: work@simple_package (work@simple_package), file:${SURELOG_DIR}/tests/UnitPackage/simple_pkg.sv, line:11:1, endln:30:10 + \_module_inst: work@simple_package (work@simple_package), file:${SURELOG_DIR}/tests/UnitPackage/simple_pkg.sv, line:11:1, endln:30:10 |vpiStmt: \_assignment: , line:54:5, endln:54:25 |vpiParent: @@ -4004,12 +4004,12 @@ design: (work@simple_package) |vpiActual: \_integer_var: , line:53:12, endln:53:19 |vpiInstance: - \_module: work@simple_package (work@simple_package), file:${SURELOG_DIR}/tests/UnitPackage/simple_pkg.sv, line:11:1, endln:30:10 + \_module_inst: work@simple_package (work@simple_package), file:${SURELOG_DIR}/tests/UnitPackage/simple_pkg.sv, line:11:1, endln:30:10 |vpiTopModule:1 |vpiProcess: \_initial: , line:19:1, endln:28:4 |vpiParent: - \_module: work@simple_package (work@simple_package), file:${SURELOG_DIR}/tests/UnitPackage/simple_pkg.sv, line:11:1, endln:30:10 + \_module_inst: work@simple_package (work@simple_package), file:${SURELOG_DIR}/tests/UnitPackage/simple_pkg.sv, line:11:1, endln:30:10 |vpiStmt: \_begin: (work@simple_package), line:19:9, endln:28:4 |vpiParent: @@ -4127,7 +4127,7 @@ design: (work@simple_package) |vpiGenScopeArray: \_gen_scope_array: (work@simple_package.inst), line:15:1, endln:17:6 |vpiParent: - \_module: work@simple_package (work@simple_package), file:${SURELOG_DIR}/tests/UnitPackage/simple_pkg.sv, line:11:1, endln:30:10 + \_module_inst: work@simple_package (work@simple_package), file:${SURELOG_DIR}/tests/UnitPackage/simple_pkg.sv, line:11:1, endln:30:10 |vpiName:inst |vpiFullName:work@simple_package.inst |vpiGenScope: @@ -4143,8 +4143,8 @@ design: (work@simple_package) |vpiFullName:work@simple_package.inst.u1.SIZE |vpiTypedef: \_enum_typespec: (definesPkg::bool), line:10:3, endln:10:36 - |vpiModule: - \_module: work@simple_package.inst::M1 (work@simple_package.inst.u1), file:${SURELOG_DIR}/tests/UnitPackage/simple_pkg.sv, line:16:4, endln:16:12 + |vpiModuleInst: + \_module_inst: work@simple_package.inst::M1 (work@simple_package.inst.u1), file:${SURELOG_DIR}/tests/UnitPackage/simple_pkg.sv, line:16:4, endln:16:12 |vpiParent: \_gen_scope: (work@simple_package.inst) |vpiName:u1 @@ -4152,7 +4152,7 @@ design: (work@simple_package) |vpiParamAssign: \_param_assign: |vpiParent: - \_module: work@simple_package.inst::M1 (work@simple_package.inst.u1), file:${SURELOG_DIR}/tests/UnitPackage/simple_pkg.sv, line:16:4, endln:16:12 + \_module_inst: work@simple_package.inst::M1 (work@simple_package.inst.u1), file:${SURELOG_DIR}/tests/UnitPackage/simple_pkg.sv, line:16:4, endln:16:12 |vpiRhs: \_constant: , line:8:0, endln:8:0 |vpiDecompile:2 diff --git a/tests/UnitPartSelect/UnitPartSelect.log b/tests/UnitPartSelect/UnitPartSelect.log index 7f6672d3e4..0e68d7e6c4 100644 --- a/tests/UnitPartSelect/UnitPartSelect.log +++ b/tests/UnitPartSelect/UnitPartSelect.log @@ -847,7 +847,7 @@ io_decl 11 logic_net 22 logic_typespec 21 logic_var 1 -module 15 +module_inst 15 operation 3 package 2 param_assign 2 @@ -883,7 +883,7 @@ io_decl 22 logic_net 22 logic_typespec 21 logic_var 1 -module 15 +module_inst 15 operation 6 package 2 param_assign 2 @@ -1382,7 +1382,7 @@ design: (work@toto) \_int_typespec: |vpiSigned:1 |uhdmallModules: -\_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/UnitPartSelect/top.sv, line:21:1, endln:27:10 +\_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/UnitPartSelect/top.sv, line:21:1, endln:27:10 |vpiParent: \_design: (work@toto) |vpiFullName:work@dut @@ -1390,21 +1390,21 @@ design: (work@toto) |vpiNet: \_logic_net: (work@dut.a), line:24:16, endln:24:17 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/UnitPartSelect/top.sv, line:21:1, endln:27:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/UnitPartSelect/top.sv, line:21:1, endln:27:10 |vpiName:a |vpiFullName:work@dut.a |vpiNetType:1 |vpiNet: \_logic_net: (work@dut.o), line:25:15, endln:25:16 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/UnitPartSelect/top.sv, line:21:1, endln:27:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/UnitPartSelect/top.sv, line:21:1, endln:27:10 |vpiName:o |vpiFullName:work@dut.o |vpiNetType:48 |vpiPort: \_port: (a), line:21:13, endln:21:14 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/UnitPartSelect/top.sv, line:21:1, endln:27:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/UnitPartSelect/top.sv, line:21:1, endln:27:10 |vpiName:a |vpiDirection:1 |vpiLowConn: @@ -1434,7 +1434,7 @@ design: (work@toto) |vpiPort: \_port: (o), line:21:16, endln:21:17 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/UnitPartSelect/top.sv, line:21:1, endln:27:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/UnitPartSelect/top.sv, line:21:1, endln:27:10 |vpiName:o |vpiDirection:2 |vpiLowConn: @@ -1464,7 +1464,7 @@ design: (work@toto) |vpiContAssign: \_cont_assign: , line:26:10, endln:26:20 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/UnitPartSelect/top.sv, line:21:1, endln:27:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/UnitPartSelect/top.sv, line:21:1, endln:27:10 |vpiRhs: \_part_select: , line:26:14, endln:26:20 |vpiParent: @@ -1496,7 +1496,7 @@ design: (work@toto) |vpiActual: \_logic_net: (work@dut.o), line:25:15, endln:25:16 |uhdmallModules: -\_module: work@dut_no_decl (work@dut_no_decl), file:${SURELOG_DIR}/tests/UnitPartSelect/top.sv, line:38:1, endln:41:10 +\_module_inst: work@dut_no_decl (work@dut_no_decl), file:${SURELOG_DIR}/tests/UnitPartSelect/top.sv, line:38:1, endln:41:10 |vpiParent: \_design: (work@toto) |vpiFullName:work@dut_no_decl @@ -1504,19 +1504,19 @@ design: (work@toto) |vpiNet: \_logic_net: (work@dut_no_decl.a), line:38:32, endln:38:33 |vpiParent: - \_module: work@dut_no_decl (work@dut_no_decl), file:${SURELOG_DIR}/tests/UnitPartSelect/top.sv, line:38:1, endln:41:10 + \_module_inst: work@dut_no_decl (work@dut_no_decl), file:${SURELOG_DIR}/tests/UnitPartSelect/top.sv, line:38:1, endln:41:10 |vpiName:a |vpiFullName:work@dut_no_decl.a |vpiNet: \_logic_net: (work@dut_no_decl.b), line:38:48, endln:38:49 |vpiParent: - \_module: work@dut_no_decl (work@dut_no_decl), file:${SURELOG_DIR}/tests/UnitPartSelect/top.sv, line:38:1, endln:41:10 + \_module_inst: work@dut_no_decl (work@dut_no_decl), file:${SURELOG_DIR}/tests/UnitPartSelect/top.sv, line:38:1, endln:41:10 |vpiName:b |vpiFullName:work@dut_no_decl.b |vpiPort: \_port: (a), line:38:32, endln:38:33 |vpiParent: - \_module: work@dut_no_decl (work@dut_no_decl), file:${SURELOG_DIR}/tests/UnitPartSelect/top.sv, line:38:1, endln:41:10 + \_module_inst: work@dut_no_decl (work@dut_no_decl), file:${SURELOG_DIR}/tests/UnitPartSelect/top.sv, line:38:1, endln:41:10 |vpiName:a |vpiDirection:1 |vpiLowConn: @@ -1546,7 +1546,7 @@ design: (work@toto) |vpiPort: \_port: (b), line:38:48, endln:38:49 |vpiParent: - \_module: work@dut_no_decl (work@dut_no_decl), file:${SURELOG_DIR}/tests/UnitPartSelect/top.sv, line:38:1, endln:41:10 + \_module_inst: work@dut_no_decl (work@dut_no_decl), file:${SURELOG_DIR}/tests/UnitPartSelect/top.sv, line:38:1, endln:41:10 |vpiName:b |vpiDirection:2 |vpiLowConn: @@ -1576,7 +1576,7 @@ design: (work@toto) |vpiContAssign: \_cont_assign: , line:39:10, endln:39:21 |vpiParent: - \_module: work@dut_no_decl (work@dut_no_decl), file:${SURELOG_DIR}/tests/UnitPartSelect/top.sv, line:38:1, endln:41:10 + \_module_inst: work@dut_no_decl (work@dut_no_decl), file:${SURELOG_DIR}/tests/UnitPartSelect/top.sv, line:38:1, endln:41:10 |vpiRhs: \_bit_select: (work@dut_no_decl.a), line:39:17, endln:39:21 |vpiParent: @@ -1616,7 +1616,7 @@ design: (work@toto) |vpiContAssign: \_cont_assign: , line:40:10, endln:40:25 |vpiParent: - \_module: work@dut_no_decl (work@dut_no_decl), file:${SURELOG_DIR}/tests/UnitPartSelect/top.sv, line:38:1, endln:41:10 + \_module_inst: work@dut_no_decl (work@dut_no_decl), file:${SURELOG_DIR}/tests/UnitPartSelect/top.sv, line:38:1, endln:41:10 |vpiRhs: \_part_select: , line:40:19, endln:40:25 |vpiParent: @@ -1662,7 +1662,7 @@ design: (work@toto) |UINT:0 |vpiConstType:9 |uhdmallModules: -\_module: work@dut_part_select (work@dut_part_select), file:${SURELOG_DIR}/tests/UnitPartSelect/top.sv, line:30:1, endln:35:10 +\_module_inst: work@dut_part_select (work@dut_part_select), file:${SURELOG_DIR}/tests/UnitPartSelect/top.sv, line:30:1, endln:35:10 |vpiParent: \_design: (work@toto) |vpiFullName:work@dut_part_select @@ -1670,33 +1670,33 @@ design: (work@toto) |vpiNet: \_logic_net: (work@dut_part_select.a), line:30:36, endln:30:37 |vpiParent: - \_module: work@dut_part_select (work@dut_part_select), file:${SURELOG_DIR}/tests/UnitPartSelect/top.sv, line:30:1, endln:35:10 + \_module_inst: work@dut_part_select (work@dut_part_select), file:${SURELOG_DIR}/tests/UnitPartSelect/top.sv, line:30:1, endln:35:10 |vpiName:a |vpiFullName:work@dut_part_select.a |vpiNet: \_logic_net: (work@dut_part_select.b), line:30:52, endln:30:53 |vpiParent: - \_module: work@dut_part_select (work@dut_part_select), file:${SURELOG_DIR}/tests/UnitPartSelect/top.sv, line:30:1, endln:35:10 + \_module_inst: work@dut_part_select (work@dut_part_select), file:${SURELOG_DIR}/tests/UnitPartSelect/top.sv, line:30:1, endln:35:10 |vpiName:b |vpiFullName:work@dut_part_select.b |vpiNet: \_logic_net: (work@dut_part_select.a), line:31:14, endln:31:15 |vpiParent: - \_module: work@dut_part_select (work@dut_part_select), file:${SURELOG_DIR}/tests/UnitPartSelect/top.sv, line:30:1, endln:35:10 + \_module_inst: work@dut_part_select (work@dut_part_select), file:${SURELOG_DIR}/tests/UnitPartSelect/top.sv, line:30:1, endln:35:10 |vpiName:a |vpiFullName:work@dut_part_select.a |vpiNetType:1 |vpiNet: \_logic_net: (work@dut_part_select.b), line:32:13, endln:32:14 |vpiParent: - \_module: work@dut_part_select (work@dut_part_select), file:${SURELOG_DIR}/tests/UnitPartSelect/top.sv, line:30:1, endln:35:10 + \_module_inst: work@dut_part_select (work@dut_part_select), file:${SURELOG_DIR}/tests/UnitPartSelect/top.sv, line:30:1, endln:35:10 |vpiName:b |vpiFullName:work@dut_part_select.b |vpiNetType:48 |vpiPort: \_port: (a), line:30:36, endln:30:37 |vpiParent: - \_module: work@dut_part_select (work@dut_part_select), file:${SURELOG_DIR}/tests/UnitPartSelect/top.sv, line:30:1, endln:35:10 + \_module_inst: work@dut_part_select (work@dut_part_select), file:${SURELOG_DIR}/tests/UnitPartSelect/top.sv, line:30:1, endln:35:10 |vpiName:a |vpiDirection:1 |vpiLowConn: @@ -1726,7 +1726,7 @@ design: (work@toto) |vpiPort: \_port: (b), line:30:52, endln:30:53 |vpiParent: - \_module: work@dut_part_select (work@dut_part_select), file:${SURELOG_DIR}/tests/UnitPartSelect/top.sv, line:30:1, endln:35:10 + \_module_inst: work@dut_part_select (work@dut_part_select), file:${SURELOG_DIR}/tests/UnitPartSelect/top.sv, line:30:1, endln:35:10 |vpiName:b |vpiDirection:2 |vpiLowConn: @@ -1756,7 +1756,7 @@ design: (work@toto) |vpiContAssign: \_cont_assign: , line:33:10, endln:33:21 |vpiParent: - \_module: work@dut_part_select (work@dut_part_select), file:${SURELOG_DIR}/tests/UnitPartSelect/top.sv, line:30:1, endln:35:10 + \_module_inst: work@dut_part_select (work@dut_part_select), file:${SURELOG_DIR}/tests/UnitPartSelect/top.sv, line:30:1, endln:35:10 |vpiRhs: \_bit_select: (work@dut_part_select.a), line:33:17, endln:33:21 |vpiParent: @@ -1796,7 +1796,7 @@ design: (work@toto) |vpiContAssign: \_cont_assign: , line:34:10, endln:34:25 |vpiParent: - \_module: work@dut_part_select (work@dut_part_select), file:${SURELOG_DIR}/tests/UnitPartSelect/top.sv, line:30:1, endln:35:10 + \_module_inst: work@dut_part_select (work@dut_part_select), file:${SURELOG_DIR}/tests/UnitPartSelect/top.sv, line:30:1, endln:35:10 |vpiRhs: \_part_select: , line:34:19, endln:34:25 |vpiParent: @@ -1842,14 +1842,14 @@ design: (work@toto) |UINT:0 |vpiConstType:9 |uhdmallModules: -\_module: work@toto (work@toto), file:${SURELOG_DIR}/tests/UnitPartSelect/top.sv, line:1:1, endln:19:10 +\_module_inst: work@toto (work@toto), file:${SURELOG_DIR}/tests/UnitPartSelect/top.sv, line:1:1, endln:19:10 |vpiParent: \_design: (work@toto) |vpiFullName:work@toto |vpiParameter: \_parameter: (work@toto.IDLE), line:3:13, endln:3:17 |vpiParent: - \_module: work@toto (work@toto), file:${SURELOG_DIR}/tests/UnitPartSelect/top.sv, line:1:1, endln:19:10 + \_module_inst: work@toto (work@toto), file:${SURELOG_DIR}/tests/UnitPartSelect/top.sv, line:1:1, endln:19:10 |UINT:0 |vpiTypespec: \_int_typespec: @@ -1858,7 +1858,7 @@ design: (work@toto) |vpiParamAssign: \_param_assign: , line:3:13, endln:3:21 |vpiParent: - \_module: work@toto (work@toto), file:${SURELOG_DIR}/tests/UnitPartSelect/top.sv, line:1:1, endln:19:10 + \_module_inst: work@toto (work@toto), file:${SURELOG_DIR}/tests/UnitPartSelect/top.sv, line:1:1, endln:19:10 |vpiRhs: \_constant: , line:3:20, endln:3:21 |vpiDecompile:0 @@ -1873,21 +1873,21 @@ design: (work@toto) |vpiNet: \_logic_net: (work@toto.state), line:5:13, endln:5:18 |vpiParent: - \_module: work@toto (work@toto), file:${SURELOG_DIR}/tests/UnitPartSelect/top.sv, line:1:1, endln:19:10 + \_module_inst: work@toto (work@toto), file:${SURELOG_DIR}/tests/UnitPartSelect/top.sv, line:1:1, endln:19:10 |vpiName:state |vpiFullName:work@toto.state |vpiNetType:48 |vpiNet: \_logic_net: (work@toto.next), line:5:20, endln:5:24 |vpiParent: - \_module: work@toto (work@toto), file:${SURELOG_DIR}/tests/UnitPartSelect/top.sv, line:1:1, endln:19:10 + \_module_inst: work@toto (work@toto), file:${SURELOG_DIR}/tests/UnitPartSelect/top.sv, line:1:1, endln:19:10 |vpiName:next |vpiFullName:work@toto.next |vpiNetType:48 |vpiProcess: \_always: , line:7:3, endln:17:6 |vpiParent: - \_module: work@toto (work@toto), file:${SURELOG_DIR}/tests/UnitPartSelect/top.sv, line:1:1, endln:19:10 + \_module_inst: work@toto (work@toto), file:${SURELOG_DIR}/tests/UnitPartSelect/top.sv, line:1:1, endln:19:10 |vpiStmt: \_event_control: , line:7:10, endln:7:25 |vpiParent: @@ -2025,12 +2025,12 @@ design: (work@toto) |vpiFullName:work@toto |vpiAlwaysType:1 |uhdmtopModules: -\_module: work@toto (work@toto), file:${SURELOG_DIR}/tests/UnitPartSelect/top.sv, line:1:1, endln:19:10 +\_module_inst: work@toto (work@toto), file:${SURELOG_DIR}/tests/UnitPartSelect/top.sv, line:1:1, endln:19:10 |vpiName:work@toto |vpiParameter: \_parameter: (work@toto.IDLE), line:3:13, endln:3:17 |vpiParent: - \_module: work@toto (work@toto), file:${SURELOG_DIR}/tests/UnitPartSelect/top.sv, line:1:1, endln:19:10 + \_module_inst: work@toto (work@toto), file:${SURELOG_DIR}/tests/UnitPartSelect/top.sv, line:1:1, endln:19:10 |UINT:0 |vpiTypespec: \_int_typespec: @@ -2041,7 +2041,7 @@ design: (work@toto) |vpiParamAssign: \_param_assign: , line:3:13, endln:3:21 |vpiParent: - \_module: work@toto (work@toto), file:${SURELOG_DIR}/tests/UnitPartSelect/top.sv, line:1:1, endln:19:10 + \_module_inst: work@toto (work@toto), file:${SURELOG_DIR}/tests/UnitPartSelect/top.sv, line:1:1, endln:19:10 |vpiRhs: \_constant: , line:3:20, endln:3:21 |vpiDecompile:0 @@ -2057,7 +2057,7 @@ design: (work@toto) |vpiNet: \_logic_net: (work@toto.state), line:5:13, endln:5:18 |vpiParent: - \_module: work@toto (work@toto), file:${SURELOG_DIR}/tests/UnitPartSelect/top.sv, line:1:1, endln:19:10 + \_module_inst: work@toto (work@toto), file:${SURELOG_DIR}/tests/UnitPartSelect/top.sv, line:1:1, endln:19:10 |vpiTypespec: \_logic_typespec: , line:5:3, endln:5:12 |vpiRange: @@ -2084,7 +2084,7 @@ design: (work@toto) |vpiNet: \_logic_net: (work@toto.next), line:5:20, endln:5:24 |vpiParent: - \_module: work@toto (work@toto), file:${SURELOG_DIR}/tests/UnitPartSelect/top.sv, line:1:1, endln:19:10 + \_module_inst: work@toto (work@toto), file:${SURELOG_DIR}/tests/UnitPartSelect/top.sv, line:1:1, endln:19:10 |vpiTypespec: \_logic_typespec: , line:5:3, endln:5:12 |vpiName:next @@ -2102,7 +2102,7 @@ design: (work@toto) |vpiProcess: \_always: , line:7:3, endln:17:6 |vpiParent: - \_module: work@toto (work@toto), file:${SURELOG_DIR}/tests/UnitPartSelect/top.sv, line:1:1, endln:19:10 + \_module_inst: work@toto (work@toto), file:${SURELOG_DIR}/tests/UnitPartSelect/top.sv, line:1:1, endln:19:10 |vpiStmt: \_event_control: , line:7:10, endln:7:25 |vpiParent: @@ -2220,14 +2220,14 @@ design: (work@toto) |vpiFullName:work@toto |vpiAlwaysType:1 |uhdmtopModules: -\_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/UnitPartSelect/top.sv, line:21:1, endln:27:10 +\_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/UnitPartSelect/top.sv, line:21:1, endln:27:10 |vpiName:work@dut |vpiDefName:work@dut |vpiTop:1 |vpiNet: \_logic_net: (work@dut.a), line:24:16, endln:24:17 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/UnitPartSelect/top.sv, line:21:1, endln:27:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/UnitPartSelect/top.sv, line:21:1, endln:27:10 |vpiTypespec: \_logic_typespec: , line:24:5, endln:24:15 |vpiRange: @@ -2254,7 +2254,7 @@ design: (work@toto) |vpiNet: \_logic_net: (work@dut.o), line:25:15, endln:25:16 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/UnitPartSelect/top.sv, line:21:1, endln:27:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/UnitPartSelect/top.sv, line:21:1, endln:27:10 |vpiTypespec: \_logic_typespec: , line:25:5, endln:25:14 |vpiRange: @@ -2282,7 +2282,7 @@ design: (work@toto) |vpiPort: \_port: (a), line:21:13, endln:21:14 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/UnitPartSelect/top.sv, line:21:1, endln:27:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/UnitPartSelect/top.sv, line:21:1, endln:27:10 |vpiName:a |vpiDirection:1 |vpiLowConn: @@ -2316,11 +2316,11 @@ design: (work@toto) |UINT:0 |vpiConstType:9 |vpiInstance: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/UnitPartSelect/top.sv, line:21:1, endln:27:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/UnitPartSelect/top.sv, line:21:1, endln:27:10 |vpiPort: \_port: (o), line:21:16, endln:21:17 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/UnitPartSelect/top.sv, line:21:1, endln:27:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/UnitPartSelect/top.sv, line:21:1, endln:27:10 |vpiName:o |vpiDirection:2 |vpiLowConn: @@ -2354,11 +2354,11 @@ design: (work@toto) |UINT:0 |vpiConstType:9 |vpiInstance: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/UnitPartSelect/top.sv, line:21:1, endln:27:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/UnitPartSelect/top.sv, line:21:1, endln:27:10 |vpiContAssign: \_cont_assign: , line:26:10, endln:26:20 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/UnitPartSelect/top.sv, line:21:1, endln:27:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/UnitPartSelect/top.sv, line:21:1, endln:27:10 |vpiRhs: \_part_select: , line:26:14, endln:26:20 |vpiParent: @@ -2384,14 +2384,14 @@ design: (work@toto) |vpiActual: \_logic_net: (work@dut.o), line:25:15, endln:25:16 |uhdmtopModules: -\_module: work@dut_part_select (work@dut_part_select), file:${SURELOG_DIR}/tests/UnitPartSelect/top.sv, line:30:1, endln:35:10 +\_module_inst: work@dut_part_select (work@dut_part_select), file:${SURELOG_DIR}/tests/UnitPartSelect/top.sv, line:30:1, endln:35:10 |vpiName:work@dut_part_select |vpiDefName:work@dut_part_select |vpiTop:1 |vpiNet: \_logic_net: (work@dut_part_select.a), line:30:36, endln:30:37 |vpiParent: - \_module: work@dut_part_select (work@dut_part_select), file:${SURELOG_DIR}/tests/UnitPartSelect/top.sv, line:30:1, endln:35:10 + \_module_inst: work@dut_part_select (work@dut_part_select), file:${SURELOG_DIR}/tests/UnitPartSelect/top.sv, line:30:1, endln:35:10 |vpiTypespec: \_logic_typespec: , line:30:30, endln:30:35 |vpiRange: @@ -2417,7 +2417,7 @@ design: (work@toto) |vpiNet: \_logic_net: (work@dut_part_select.b), line:30:52, endln:30:53 |vpiParent: - \_module: work@dut_part_select (work@dut_part_select), file:${SURELOG_DIR}/tests/UnitPartSelect/top.sv, line:30:1, endln:35:10 + \_module_inst: work@dut_part_select (work@dut_part_select), file:${SURELOG_DIR}/tests/UnitPartSelect/top.sv, line:30:1, endln:35:10 |vpiTypespec: \_logic_typespec: , line:30:46, endln:30:51 |vpiRange: @@ -2443,7 +2443,7 @@ design: (work@toto) |vpiNet: \_logic_net: (work@dut_part_select.a), line:31:14, endln:31:15 |vpiParent: - \_module: work@dut_part_select (work@dut_part_select), file:${SURELOG_DIR}/tests/UnitPartSelect/top.sv, line:30:1, endln:35:10 + \_module_inst: work@dut_part_select (work@dut_part_select), file:${SURELOG_DIR}/tests/UnitPartSelect/top.sv, line:30:1, endln:35:10 |vpiTypespec: \_logic_typespec: , line:31:3, endln:31:13 |vpiRange: @@ -2470,7 +2470,7 @@ design: (work@toto) |vpiNet: \_logic_net: (work@dut_part_select.b), line:32:13, endln:32:14 |vpiParent: - \_module: work@dut_part_select (work@dut_part_select), file:${SURELOG_DIR}/tests/UnitPartSelect/top.sv, line:30:1, endln:35:10 + \_module_inst: work@dut_part_select (work@dut_part_select), file:${SURELOG_DIR}/tests/UnitPartSelect/top.sv, line:30:1, endln:35:10 |vpiTypespec: \_logic_typespec: , line:32:3, endln:32:12 |vpiRange: @@ -2498,7 +2498,7 @@ design: (work@toto) |vpiPort: \_port: (a), line:30:36, endln:30:37 |vpiParent: - \_module: work@dut_part_select (work@dut_part_select), file:${SURELOG_DIR}/tests/UnitPartSelect/top.sv, line:30:1, endln:35:10 + \_module_inst: work@dut_part_select (work@dut_part_select), file:${SURELOG_DIR}/tests/UnitPartSelect/top.sv, line:30:1, endln:35:10 |vpiName:a |vpiDirection:1 |vpiLowConn: @@ -2532,11 +2532,11 @@ design: (work@toto) |UINT:0 |vpiConstType:9 |vpiInstance: - \_module: work@dut_part_select (work@dut_part_select), file:${SURELOG_DIR}/tests/UnitPartSelect/top.sv, line:30:1, endln:35:10 + \_module_inst: work@dut_part_select (work@dut_part_select), file:${SURELOG_DIR}/tests/UnitPartSelect/top.sv, line:30:1, endln:35:10 |vpiPort: \_port: (b), line:30:52, endln:30:53 |vpiParent: - \_module: work@dut_part_select (work@dut_part_select), file:${SURELOG_DIR}/tests/UnitPartSelect/top.sv, line:30:1, endln:35:10 + \_module_inst: work@dut_part_select (work@dut_part_select), file:${SURELOG_DIR}/tests/UnitPartSelect/top.sv, line:30:1, endln:35:10 |vpiName:b |vpiDirection:2 |vpiLowConn: @@ -2570,11 +2570,11 @@ design: (work@toto) |UINT:0 |vpiConstType:9 |vpiInstance: - \_module: work@dut_part_select (work@dut_part_select), file:${SURELOG_DIR}/tests/UnitPartSelect/top.sv, line:30:1, endln:35:10 + \_module_inst: work@dut_part_select (work@dut_part_select), file:${SURELOG_DIR}/tests/UnitPartSelect/top.sv, line:30:1, endln:35:10 |vpiContAssign: \_cont_assign: , line:33:10, endln:33:21 |vpiParent: - \_module: work@dut_part_select (work@dut_part_select), file:${SURELOG_DIR}/tests/UnitPartSelect/top.sv, line:30:1, endln:35:10 + \_module_inst: work@dut_part_select (work@dut_part_select), file:${SURELOG_DIR}/tests/UnitPartSelect/top.sv, line:30:1, endln:35:10 |vpiRhs: \_bit_select: (work@dut_part_select.a), line:33:17, endln:33:21 |vpiParent: @@ -2610,7 +2610,7 @@ design: (work@toto) |vpiContAssign: \_cont_assign: , line:34:10, endln:34:25 |vpiParent: - \_module: work@dut_part_select (work@dut_part_select), file:${SURELOG_DIR}/tests/UnitPartSelect/top.sv, line:30:1, endln:35:10 + \_module_inst: work@dut_part_select (work@dut_part_select), file:${SURELOG_DIR}/tests/UnitPartSelect/top.sv, line:30:1, endln:35:10 |vpiRhs: \_part_select: , line:34:19, endln:34:25 |vpiParent: @@ -2644,14 +2644,14 @@ design: (work@toto) |vpiRightRange: \_constant: , line:34:14, endln:34:15 |uhdmtopModules: -\_module: work@dut_no_decl (work@dut_no_decl), file:${SURELOG_DIR}/tests/UnitPartSelect/top.sv, line:38:1, endln:41:10 +\_module_inst: work@dut_no_decl (work@dut_no_decl), file:${SURELOG_DIR}/tests/UnitPartSelect/top.sv, line:38:1, endln:41:10 |vpiName:work@dut_no_decl |vpiDefName:work@dut_no_decl |vpiTop:1 |vpiNet: \_logic_net: (work@dut_no_decl.a), line:38:32, endln:38:33 |vpiParent: - \_module: work@dut_no_decl (work@dut_no_decl), file:${SURELOG_DIR}/tests/UnitPartSelect/top.sv, line:38:1, endln:41:10 + \_module_inst: work@dut_no_decl (work@dut_no_decl), file:${SURELOG_DIR}/tests/UnitPartSelect/top.sv, line:38:1, endln:41:10 |vpiTypespec: \_logic_typespec: , line:38:26, endln:38:31 |vpiRange: @@ -2677,7 +2677,7 @@ design: (work@toto) |vpiNet: \_logic_net: (work@dut_no_decl.b), line:38:48, endln:38:49 |vpiParent: - \_module: work@dut_no_decl (work@dut_no_decl), file:${SURELOG_DIR}/tests/UnitPartSelect/top.sv, line:38:1, endln:41:10 + \_module_inst: work@dut_no_decl (work@dut_no_decl), file:${SURELOG_DIR}/tests/UnitPartSelect/top.sv, line:38:1, endln:41:10 |vpiTypespec: \_logic_typespec: , line:38:42, endln:38:47 |vpiRange: @@ -2704,7 +2704,7 @@ design: (work@toto) |vpiPort: \_port: (a), line:38:32, endln:38:33 |vpiParent: - \_module: work@dut_no_decl (work@dut_no_decl), file:${SURELOG_DIR}/tests/UnitPartSelect/top.sv, line:38:1, endln:41:10 + \_module_inst: work@dut_no_decl (work@dut_no_decl), file:${SURELOG_DIR}/tests/UnitPartSelect/top.sv, line:38:1, endln:41:10 |vpiName:a |vpiDirection:1 |vpiLowConn: @@ -2738,11 +2738,11 @@ design: (work@toto) |UINT:0 |vpiConstType:9 |vpiInstance: - \_module: work@dut_no_decl (work@dut_no_decl), file:${SURELOG_DIR}/tests/UnitPartSelect/top.sv, line:38:1, endln:41:10 + \_module_inst: work@dut_no_decl (work@dut_no_decl), file:${SURELOG_DIR}/tests/UnitPartSelect/top.sv, line:38:1, endln:41:10 |vpiPort: \_port: (b), line:38:48, endln:38:49 |vpiParent: - \_module: work@dut_no_decl (work@dut_no_decl), file:${SURELOG_DIR}/tests/UnitPartSelect/top.sv, line:38:1, endln:41:10 + \_module_inst: work@dut_no_decl (work@dut_no_decl), file:${SURELOG_DIR}/tests/UnitPartSelect/top.sv, line:38:1, endln:41:10 |vpiName:b |vpiDirection:2 |vpiLowConn: @@ -2776,11 +2776,11 @@ design: (work@toto) |UINT:0 |vpiConstType:9 |vpiInstance: - \_module: work@dut_no_decl (work@dut_no_decl), file:${SURELOG_DIR}/tests/UnitPartSelect/top.sv, line:38:1, endln:41:10 + \_module_inst: work@dut_no_decl (work@dut_no_decl), file:${SURELOG_DIR}/tests/UnitPartSelect/top.sv, line:38:1, endln:41:10 |vpiContAssign: \_cont_assign: , line:39:10, endln:39:21 |vpiParent: - \_module: work@dut_no_decl (work@dut_no_decl), file:${SURELOG_DIR}/tests/UnitPartSelect/top.sv, line:38:1, endln:41:10 + \_module_inst: work@dut_no_decl (work@dut_no_decl), file:${SURELOG_DIR}/tests/UnitPartSelect/top.sv, line:38:1, endln:41:10 |vpiRhs: \_bit_select: (work@dut_no_decl.a), line:39:17, endln:39:21 |vpiParent: @@ -2816,7 +2816,7 @@ design: (work@toto) |vpiContAssign: \_cont_assign: , line:40:10, endln:40:25 |vpiParent: - \_module: work@dut_no_decl (work@dut_no_decl), file:${SURELOG_DIR}/tests/UnitPartSelect/top.sv, line:38:1, endln:41:10 + \_module_inst: work@dut_no_decl (work@dut_no_decl), file:${SURELOG_DIR}/tests/UnitPartSelect/top.sv, line:38:1, endln:41:10 |vpiRhs: \_part_select: , line:40:19, endln:40:25 |vpiParent: diff --git a/tests/UnitPython/UnitPython.log b/tests/UnitPython/UnitPython.log index b8fea5a1dd..11ac1b9afc 100644 --- a/tests/UnitPython/UnitPython.log +++ b/tests/UnitPython/UnitPython.log @@ -446,7 +446,7 @@ int_var 4 io_decl 11 logic_net 6 logic_var 1 -module 4 +module_inst 4 package 5 task 9 unsupported_typespec 1 diff --git a/tests/UnitSVA/UnitSVA.log b/tests/UnitSVA/UnitSVA.log index 6dd97c07dd..da1890dbe3 100644 --- a/tests/UnitSVA/UnitSVA.log +++ b/tests/UnitSVA/UnitSVA.log @@ -471,7 +471,7 @@ assume 2 constant 18 design 1 logic_net 12 -module 2 +module_inst 2 operation 29 property_spec 8 range 1 @@ -486,7 +486,7 @@ assume 4 constant 18 design 1 logic_net 12 -module 2 +module_inst 2 operation 58 property_spec 16 range 2 @@ -506,7 +506,7 @@ design: (work@top) |vpiElaborated:1 |vpiName:work@top |uhdmallModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/UnitSVA/dut.sv, line:1:1, endln:26:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/UnitSVA/dut.sv, line:1:1, endln:26:10 |vpiParent: \_design: (work@top) |vpiFullName:work@top @@ -514,7 +514,7 @@ design: (work@top) |vpiAssertion: \_assert_stmt: (work@top), line:3:1, endln:3:63 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/UnitSVA/dut.sv, line:1:1, endln:26:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/UnitSVA/dut.sv, line:1:1, endln:26:10 |vpiFullName:work@top |vpiProperty: \_property_spec: , line:3:18, endln:3:61 @@ -580,7 +580,7 @@ design: (work@top) |vpiAssertion: \_assert_stmt: (work@top), line:5:1, endln:5:61 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/UnitSVA/dut.sv, line:1:1, endln:26:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/UnitSVA/dut.sv, line:1:1, endln:26:10 |vpiFullName:work@top |vpiProperty: \_property_spec: , line:5:18, endln:5:59 @@ -652,7 +652,7 @@ design: (work@top) |vpiAssertion: \_assert_stmt: (work@top), line:7:1, endln:7:65 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/UnitSVA/dut.sv, line:1:1, endln:26:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/UnitSVA/dut.sv, line:1:1, endln:26:10 |vpiFullName:work@top |vpiProperty: \_property_spec: , line:7:18, endln:7:63 @@ -732,7 +732,7 @@ design: (work@top) |vpiAssertion: \_assert_stmt: (work@top), line:9:1, endln:9:59 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/UnitSVA/dut.sv, line:1:1, endln:26:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/UnitSVA/dut.sv, line:1:1, endln:26:10 |vpiFullName:work@top |vpiProperty: \_property_spec: , line:9:18, endln:9:57 @@ -799,7 +799,7 @@ design: (work@top) |vpiAssertion: \_assert_stmt: (work@top), line:11:1, endln:11:59 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/UnitSVA/dut.sv, line:1:1, endln:26:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/UnitSVA/dut.sv, line:1:1, endln:26:10 |vpiFullName:work@top |vpiProperty: \_property_spec: , line:11:18, endln:11:57 @@ -865,7 +865,7 @@ design: (work@top) |vpiAssertion: \_assert_stmt: (work@top), line:13:1, endln:15:3 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/UnitSVA/dut.sv, line:1:1, endln:26:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/UnitSVA/dut.sv, line:1:1, endln:26:10 |vpiFullName:work@top |vpiProperty: \_property_spec: , line:14:3, endln:14:31 @@ -907,7 +907,7 @@ design: (work@top) |vpiAssertion: \_assume: (work@top.lock_req), line:17:1, endln:19:112 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/UnitSVA/dut.sv, line:1:1, endln:26:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/UnitSVA/dut.sv, line:1:1, endln:26:10 |vpiName:lock_req |vpiFullName:work@top.lock_req |vpiStmt: @@ -977,7 +977,7 @@ design: (work@top) |vpiAssertion: \_assume: (work@top), line:21:1, endln:23:3 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/UnitSVA/dut.sv, line:1:1, endln:26:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/UnitSVA/dut.sv, line:1:1, endln:26:10 |vpiFullName:work@top |vpiProperty: \_property_spec: , line:22:7, endln:22:18 @@ -1004,7 +1004,7 @@ design: (work@top) |vpiActual: \_logic_net: (d) |uhdmtopModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/UnitSVA/dut.sv, line:1:1, endln:26:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/UnitSVA/dut.sv, line:1:1, endln:26:10 |vpiName:work@top |vpiDefName:work@top |vpiTop:1 @@ -1059,7 +1059,7 @@ design: (work@top) |vpiAssertion: \_assert_stmt: (work@top), line:3:1, endln:3:63 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/UnitSVA/dut.sv, line:1:1, endln:26:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/UnitSVA/dut.sv, line:1:1, endln:26:10 |vpiFullName:work@top |vpiProperty: \_property_spec: , line:3:18, endln:3:61 @@ -1129,7 +1129,7 @@ design: (work@top) |vpiAssertion: \_assert_stmt: (work@top), line:5:1, endln:5:61 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/UnitSVA/dut.sv, line:1:1, endln:26:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/UnitSVA/dut.sv, line:1:1, endln:26:10 |vpiFullName:work@top |vpiProperty: \_property_spec: , line:5:18, endln:5:59 @@ -1201,7 +1201,7 @@ design: (work@top) |vpiAssertion: \_assert_stmt: (work@top), line:7:1, endln:7:65 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/UnitSVA/dut.sv, line:1:1, endln:26:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/UnitSVA/dut.sv, line:1:1, endln:26:10 |vpiFullName:work@top |vpiProperty: \_property_spec: , line:7:18, endln:7:63 @@ -1279,7 +1279,7 @@ design: (work@top) |vpiAssertion: \_assert_stmt: (work@top), line:9:1, endln:9:59 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/UnitSVA/dut.sv, line:1:1, endln:26:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/UnitSVA/dut.sv, line:1:1, endln:26:10 |vpiFullName:work@top |vpiProperty: \_property_spec: , line:9:18, endln:9:57 @@ -1343,7 +1343,7 @@ design: (work@top) |vpiAssertion: \_assert_stmt: (work@top), line:11:1, endln:11:59 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/UnitSVA/dut.sv, line:1:1, endln:26:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/UnitSVA/dut.sv, line:1:1, endln:26:10 |vpiFullName:work@top |vpiProperty: \_property_spec: , line:11:18, endln:11:57 @@ -1413,7 +1413,7 @@ design: (work@top) |vpiAssertion: \_assert_stmt: (work@top), line:13:1, endln:15:3 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/UnitSVA/dut.sv, line:1:1, endln:26:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/UnitSVA/dut.sv, line:1:1, endln:26:10 |vpiFullName:work@top |vpiProperty: \_property_spec: , line:14:3, endln:14:31 @@ -1471,7 +1471,7 @@ design: (work@top) |vpiAssertion: \_assume: (work@top.lock_req), line:17:1, endln:19:112 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/UnitSVA/dut.sv, line:1:1, endln:26:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/UnitSVA/dut.sv, line:1:1, endln:26:10 |vpiName:lock_req |vpiFullName:work@top.lock_req |vpiStmt: @@ -1550,7 +1550,7 @@ design: (work@top) |vpiAssertion: \_assume: (work@top), line:21:1, endln:23:3 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/UnitSVA/dut.sv, line:1:1, endln:26:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/UnitSVA/dut.sv, line:1:1, endln:26:10 |vpiFullName:work@top |vpiProperty: \_property_spec: , line:22:7, endln:22:18 diff --git a/tests/UnitTest/UnitTest.log b/tests/UnitTest/UnitTest.log index 73393973fd..900b5c7378 100644 --- a/tests/UnitTest/UnitTest.log +++ b/tests/UnitTest/UnitTest.log @@ -664,13 +664,13 @@ design 1 if_else 3 if_stmt 1 initial 1 -interface 3 +interface_inst 3 interface_typespec 9 io_decl 5 logic_net 24 logic_typespec 16 modport 5 -module 8 +module_inst 8 operation 16 port 11 range 4 @@ -717,7 +717,7 @@ design: (work@tb_operators) \_design: (work@tb_operators) |vpiName:work@DD2 |uhdmallInterfaces: -\_interface: work@mem_if (work@mem_if), file:${SURELOG_DIR}/tests/UnitTest/top.v, line:47:1, endln:52:13 +\_interface_inst: work@mem_if (work@mem_if), file:${SURELOG_DIR}/tests/UnitTest/top.v, line:47:1, endln:52:13 |vpiParent: \_design: (work@tb_operators) |vpiFullName:work@mem_if @@ -725,14 +725,14 @@ design: (work@tb_operators) |vpiNet: \_logic_net: (work@mem_if.clk), line:47:30, endln:47:33 |vpiParent: - \_interface: work@mem_if (work@mem_if), file:${SURELOG_DIR}/tests/UnitTest/top.v, line:47:1, endln:52:13 + \_interface_inst: work@mem_if (work@mem_if), file:${SURELOG_DIR}/tests/UnitTest/top.v, line:47:1, endln:52:13 |vpiName:clk |vpiFullName:work@mem_if.clk |vpiNetType:1 |vpiModport: \_modport: (memory), line:50:12, endln:50:18 |vpiParent: - \_interface: work@mem_if (work@mem_if), file:${SURELOG_DIR}/tests/UnitTest/top.v, line:47:1, endln:52:13 + \_interface_inst: work@mem_if (work@mem_if), file:${SURELOG_DIR}/tests/UnitTest/top.v, line:47:1, endln:52:13 |vpiName:memory |vpiIODecl: \_io_decl: (clk), line:50:27, endln:50:30 @@ -741,7 +741,7 @@ design: (work@tb_operators) |vpiModport: \_modport: (system), line:49:12, endln:49:18 |vpiParent: - \_interface: work@mem_if (work@mem_if), file:${SURELOG_DIR}/tests/UnitTest/top.v, line:47:1, endln:52:13 + \_interface_inst: work@mem_if (work@mem_if), file:${SURELOG_DIR}/tests/UnitTest/top.v, line:47:1, endln:52:13 |vpiName:system |vpiIODecl: \_io_decl: (clk), line:49:26, endln:49:29 @@ -750,7 +750,7 @@ design: (work@tb_operators) |vpiPort: \_port: (clk), line:47:30, endln:47:33 |vpiParent: - \_interface: work@mem_if (work@mem_if), file:${SURELOG_DIR}/tests/UnitTest/top.v, line:47:1, endln:52:13 + \_interface_inst: work@mem_if (work@mem_if), file:${SURELOG_DIR}/tests/UnitTest/top.v, line:47:1, endln:52:13 |vpiName:clk |vpiDirection:1 |vpiLowConn: @@ -758,7 +758,7 @@ design: (work@tb_operators) |vpiActual: \_logic_net: (work@mem_if.clk), line:47:30, endln:47:33 |uhdmallModules: -\_module: work@memory_ctrl1 (work@memory_ctrl1), file:${SURELOG_DIR}/tests/UnitTest/top.v, line:57:1, endln:67:10 +\_module_inst: work@memory_ctrl1 (work@memory_ctrl1), file:${SURELOG_DIR}/tests/UnitTest/top.v, line:57:1, endln:67:10 |vpiParent: \_design: (work@tb_operators) |vpiFullName:work@memory_ctrl1 @@ -766,58 +766,58 @@ design: (work@tb_operators) |vpiNet: \_logic_net: (work@memory_ctrl1.toto1), line:59:5, endln:59:10 |vpiParent: - \_module: work@memory_ctrl1 (work@memory_ctrl1), file:${SURELOG_DIR}/tests/UnitTest/top.v, line:57:1, endln:67:10 + \_module_inst: work@memory_ctrl1 (work@memory_ctrl1), file:${SURELOG_DIR}/tests/UnitTest/top.v, line:57:1, endln:67:10 |vpiName:toto1 |vpiFullName:work@memory_ctrl1.toto1 |vpiNet: \_logic_net: (work@memory_ctrl1.toto2), line:61:5, endln:61:10 |vpiParent: - \_module: work@memory_ctrl1 (work@memory_ctrl1), file:${SURELOG_DIR}/tests/UnitTest/top.v, line:57:1, endln:67:10 + \_module_inst: work@memory_ctrl1 (work@memory_ctrl1), file:${SURELOG_DIR}/tests/UnitTest/top.v, line:57:1, endln:67:10 |vpiName:toto2 |vpiFullName:work@memory_ctrl1.toto2 |vpiNet: \_logic_net: (work@memory_ctrl1.i1), line:63:6, endln:63:8 |vpiParent: - \_module: work@memory_ctrl1 (work@memory_ctrl1), file:${SURELOG_DIR}/tests/UnitTest/top.v, line:57:1, endln:67:10 + \_module_inst: work@memory_ctrl1 (work@memory_ctrl1), file:${SURELOG_DIR}/tests/UnitTest/top.v, line:57:1, endln:67:10 |vpiName:i1 |vpiFullName:work@memory_ctrl1.i1 |vpiNetType:1 |vpiNet: \_logic_net: (work@memory_ctrl1.o1), line:65:5, endln:65:7 |vpiParent: - \_module: work@memory_ctrl1 (work@memory_ctrl1), file:${SURELOG_DIR}/tests/UnitTest/top.v, line:57:1, endln:67:10 + \_module_inst: work@memory_ctrl1 (work@memory_ctrl1), file:${SURELOG_DIR}/tests/UnitTest/top.v, line:57:1, endln:67:10 |vpiName:o1 |vpiFullName:work@memory_ctrl1.o1 |vpiNetType:48 |vpiNet: \_logic_net: (work@memory_ctrl1.sif1), line:57:29, endln:57:33 |vpiParent: - \_module: work@memory_ctrl1 (work@memory_ctrl1), file:${SURELOG_DIR}/tests/UnitTest/top.v, line:57:1, endln:67:10 + \_module_inst: work@memory_ctrl1 (work@memory_ctrl1), file:${SURELOG_DIR}/tests/UnitTest/top.v, line:57:1, endln:67:10 |vpiName:sif1 |vpiFullName:work@memory_ctrl1.sif1 |vpiNet: \_logic_net: (work@memory_ctrl1.sif2), line:57:49, endln:57:53 |vpiParent: - \_module: work@memory_ctrl1 (work@memory_ctrl1), file:${SURELOG_DIR}/tests/UnitTest/top.v, line:57:1, endln:67:10 + \_module_inst: work@memory_ctrl1 (work@memory_ctrl1), file:${SURELOG_DIR}/tests/UnitTest/top.v, line:57:1, endln:67:10 |vpiName:sif2 |vpiFullName:work@memory_ctrl1.sif2 |vpiPort: \_port: (sif1), line:57:29, endln:57:33 |vpiParent: - \_module: work@memory_ctrl1 (work@memory_ctrl1), file:${SURELOG_DIR}/tests/UnitTest/top.v, line:57:1, endln:67:10 + \_module_inst: work@memory_ctrl1 (work@memory_ctrl1), file:${SURELOG_DIR}/tests/UnitTest/top.v, line:57:1, endln:67:10 |vpiName:sif1 |vpiDirection:3 |vpiLowConn: \_ref_obj: |vpiActual: - \_interface: work@mem_if (work@mem_if), file:${SURELOG_DIR}/tests/UnitTest/top.v, line:47:1, endln:52:13 + \_interface_inst: work@mem_if (work@mem_if), file:${SURELOG_DIR}/tests/UnitTest/top.v, line:47:1, endln:52:13 |vpiTypedef: \_interface_typespec: (mem_if), line:57:22, endln:57:28 |vpiName:mem_if |vpiPort: \_port: (sif2), line:57:49, endln:57:53 |vpiParent: - \_module: work@memory_ctrl1 (work@memory_ctrl1), file:${SURELOG_DIR}/tests/UnitTest/top.v, line:57:1, endln:67:10 + \_module_inst: work@memory_ctrl1 (work@memory_ctrl1), file:${SURELOG_DIR}/tests/UnitTest/top.v, line:57:1, endln:67:10 |vpiName:sif2 |vpiDirection:3 |vpiLowConn: @@ -831,7 +831,7 @@ design: (work@tb_operators) |vpiName:system |vpiIsModPort:1 |uhdmallModules: -\_module: work@tb_operators (work@tb_operators), file:${SURELOG_DIR}/tests/UnitTest/top.v, line:3:1, endln:38:10 +\_module_inst: work@tb_operators (work@tb_operators), file:${SURELOG_DIR}/tests/UnitTest/top.v, line:3:1, endln:38:10 |vpiParent: \_design: (work@tb_operators) |vpiFullName:work@tb_operators @@ -839,21 +839,21 @@ design: (work@tb_operators) |vpiNet: \_logic_net: (work@tb_operators.shifter), line:5:13, endln:5:20 |vpiParent: - \_module: work@tb_operators (work@tb_operators), file:${SURELOG_DIR}/tests/UnitTest/top.v, line:3:1, endln:38:10 + \_module_inst: work@tb_operators (work@tb_operators), file:${SURELOG_DIR}/tests/UnitTest/top.v, line:3:1, endln:38:10 |vpiName:shifter |vpiFullName:work@tb_operators.shifter |vpiNetType:1 |vpiNet: \_logic_net: (work@tb_operators.result), line:6:13, endln:6:19 |vpiParent: - \_module: work@tb_operators (work@tb_operators), file:${SURELOG_DIR}/tests/UnitTest/top.v, line:3:1, endln:38:10 + \_module_inst: work@tb_operators (work@tb_operators), file:${SURELOG_DIR}/tests/UnitTest/top.v, line:3:1, endln:38:10 |vpiName:result |vpiFullName:work@tb_operators.result |vpiNetType:1 |vpiProcess: \_initial: , line:8:1, endln:36:4 |vpiParent: - \_module: work@tb_operators (work@tb_operators), file:${SURELOG_DIR}/tests/UnitTest/top.v, line:3:1, endln:38:10 + \_module_inst: work@tb_operators (work@tb_operators), file:${SURELOG_DIR}/tests/UnitTest/top.v, line:3:1, endln:38:10 |vpiStmt: \_begin: (work@tb_operators), line:8:9, endln:36:4 |vpiParent: @@ -1451,7 +1451,7 @@ design: (work@tb_operators) |vpiActual: \_logic_net: (work@tb_operators.shifter), line:5:13, endln:5:20 |uhdmallModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/UnitTest/top.v, line:40:1, endln:44:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/UnitTest/top.v, line:40:1, endln:44:10 |vpiParent: \_design: (work@tb_operators) |vpiFullName:work@top @@ -1459,33 +1459,33 @@ design: (work@tb_operators) |vpiNet: \_logic_net: (work@top.i), line:40:19, endln:40:20 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/UnitTest/top.v, line:40:1, endln:44:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/UnitTest/top.v, line:40:1, endln:44:10 |vpiName:i |vpiFullName:work@top.i |vpiNet: \_logic_net: (work@top.o), line:40:29, endln:40:30 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/UnitTest/top.v, line:40:1, endln:44:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/UnitTest/top.v, line:40:1, endln:44:10 |vpiName:o |vpiFullName:work@top.o |vpiNet: \_logic_net: (work@top.i), line:41:6, endln:41:7 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/UnitTest/top.v, line:40:1, endln:44:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/UnitTest/top.v, line:40:1, endln:44:10 |vpiName:i |vpiFullName:work@top.i |vpiNetType:1 |vpiNet: \_logic_net: (work@top.o), line:42:5, endln:42:6 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/UnitTest/top.v, line:40:1, endln:44:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/UnitTest/top.v, line:40:1, endln:44:10 |vpiName:o |vpiFullName:work@top.o |vpiNetType:48 |vpiPort: \_port: (i), line:40:19, endln:40:20 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/UnitTest/top.v, line:40:1, endln:44:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/UnitTest/top.v, line:40:1, endln:44:10 |vpiName:i |vpiDirection:1 |vpiLowConn: @@ -1497,7 +1497,7 @@ design: (work@tb_operators) |vpiPort: \_port: (o), line:40:29, endln:40:30 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/UnitTest/top.v, line:40:1, endln:44:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/UnitTest/top.v, line:40:1, endln:44:10 |vpiName:o |vpiDirection:2 |vpiLowConn: @@ -1509,7 +1509,7 @@ design: (work@tb_operators) |vpiContAssign: \_cont_assign: , line:43:8, endln:43:13 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/UnitTest/top.v, line:40:1, endln:44:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/UnitTest/top.v, line:40:1, endln:44:10 |vpiRhs: \_ref_obj: (work@top.i), line:43:12, endln:43:13 |vpiParent: @@ -1527,14 +1527,14 @@ design: (work@tb_operators) |vpiActual: \_logic_net: (work@top.o), line:40:29, endln:40:30 |uhdmtopModules: -\_module: work@tb_operators (work@tb_operators), file:${SURELOG_DIR}/tests/UnitTest/top.v, line:3:1, endln:38:10 +\_module_inst: work@tb_operators (work@tb_operators), file:${SURELOG_DIR}/tests/UnitTest/top.v, line:3:1, endln:38:10 |vpiName:work@tb_operators |vpiDefName:work@tb_operators |vpiTop:1 |vpiNet: \_logic_net: (work@tb_operators.shifter), line:5:13, endln:5:20 |vpiParent: - \_module: work@tb_operators (work@tb_operators), file:${SURELOG_DIR}/tests/UnitTest/top.v, line:3:1, endln:38:10 + \_module_inst: work@tb_operators (work@tb_operators), file:${SURELOG_DIR}/tests/UnitTest/top.v, line:3:1, endln:38:10 |vpiTypespec: \_logic_typespec: , line:5:1, endln:5:12 |vpiRange: @@ -1561,7 +1561,7 @@ design: (work@tb_operators) |vpiNet: \_logic_net: (work@tb_operators.result), line:6:13, endln:6:19 |vpiParent: - \_module: work@tb_operators (work@tb_operators), file:${SURELOG_DIR}/tests/UnitTest/top.v, line:3:1, endln:38:10 + \_module_inst: work@tb_operators (work@tb_operators), file:${SURELOG_DIR}/tests/UnitTest/top.v, line:3:1, endln:38:10 |vpiTypespec: \_logic_typespec: , line:6:1, endln:6:12 |vpiRange: @@ -1589,14 +1589,14 @@ design: (work@tb_operators) |vpiProcess: \_initial: , line:8:1, endln:36:4 |uhdmtopModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/UnitTest/top.v, line:40:1, endln:44:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/UnitTest/top.v, line:40:1, endln:44:10 |vpiName:work@top |vpiDefName:work@top |vpiTop:1 |vpiNet: \_logic_net: (work@top.i), line:40:19, endln:40:20 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/UnitTest/top.v, line:40:1, endln:44:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/UnitTest/top.v, line:40:1, endln:44:10 |vpiTypespec: \_logic_typespec: , line:40:19, endln:40:19 |vpiName:i @@ -1604,7 +1604,7 @@ design: (work@tb_operators) |vpiNet: \_logic_net: (work@top.o), line:40:29, endln:40:30 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/UnitTest/top.v, line:40:1, endln:44:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/UnitTest/top.v, line:40:1, endln:44:10 |vpiTypespec: \_logic_typespec: , line:40:29, endln:40:29 |vpiName:o @@ -1612,7 +1612,7 @@ design: (work@tb_operators) |vpiNet: \_logic_net: (work@top.i), line:41:6, endln:41:7 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/UnitTest/top.v, line:40:1, endln:44:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/UnitTest/top.v, line:40:1, endln:44:10 |vpiTypespec: \_logic_typespec: , line:41:1, endln:41:5 |vpiName:i @@ -1621,7 +1621,7 @@ design: (work@tb_operators) |vpiNet: \_logic_net: (work@top.o), line:42:5, endln:42:6 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/UnitTest/top.v, line:40:1, endln:44:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/UnitTest/top.v, line:40:1, endln:44:10 |vpiTypespec: \_logic_typespec: , line:42:1, endln:42:4 |vpiName:o @@ -1631,7 +1631,7 @@ design: (work@tb_operators) |vpiPort: \_port: (i), line:40:19, endln:40:20 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/UnitTest/top.v, line:40:1, endln:44:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/UnitTest/top.v, line:40:1, endln:44:10 |vpiName:i |vpiDirection:1 |vpiLowConn: @@ -1645,7 +1645,7 @@ design: (work@tb_operators) |vpiPort: \_port: (o), line:40:29, endln:40:30 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/UnitTest/top.v, line:40:1, endln:44:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/UnitTest/top.v, line:40:1, endln:44:10 |vpiName:o |vpiDirection:2 |vpiLowConn: @@ -1659,12 +1659,12 @@ design: (work@tb_operators) |vpiContAssign: \_cont_assign: , line:43:8, endln:43:13 |uhdmtopModules: -\_module: work@memory_ctrl1 (work@memory_ctrl1), file:${SURELOG_DIR}/tests/UnitTest/top.v, line:57:1, endln:67:10 +\_module_inst: work@memory_ctrl1 (work@memory_ctrl1), file:${SURELOG_DIR}/tests/UnitTest/top.v, line:57:1, endln:67:10 |vpiName:work@memory_ctrl1 |vpiVariables: \_class_var: (work@memory_ctrl1.toto2), line:61:5, endln:61:10 |vpiParent: - \_module: work@memory_ctrl1 (work@memory_ctrl1), file:${SURELOG_DIR}/tests/UnitTest/top.v, line:57:1, endln:67:10 + \_module_inst: work@memory_ctrl1 (work@memory_ctrl1), file:${SURELOG_DIR}/tests/UnitTest/top.v, line:57:1, endln:67:10 |vpiTypespec: \_class_typespec: (DD2), line:61:1, endln:61:4 |vpiName:DD2 @@ -1678,7 +1678,7 @@ design: (work@tb_operators) |vpiNet: \_logic_net: (work@memory_ctrl1.toto1), line:59:5, endln:59:10 |vpiParent: - \_module: work@memory_ctrl1 (work@memory_ctrl1), file:${SURELOG_DIR}/tests/UnitTest/top.v, line:57:1, endln:67:10 + \_module_inst: work@memory_ctrl1 (work@memory_ctrl1), file:${SURELOG_DIR}/tests/UnitTest/top.v, line:57:1, endln:67:10 |vpiTypespec: \_unsupported_typespec: (DD1), line:59:1, endln:59:4 |vpiName:DD1 @@ -1687,7 +1687,7 @@ design: (work@tb_operators) |vpiNet: \_logic_net: (work@memory_ctrl1.i1), line:63:6, endln:63:8 |vpiParent: - \_module: work@memory_ctrl1 (work@memory_ctrl1), file:${SURELOG_DIR}/tests/UnitTest/top.v, line:57:1, endln:67:10 + \_module_inst: work@memory_ctrl1 (work@memory_ctrl1), file:${SURELOG_DIR}/tests/UnitTest/top.v, line:57:1, endln:67:10 |vpiTypespec: \_logic_typespec: , line:63:1, endln:63:5 |vpiName:i1 @@ -1696,7 +1696,7 @@ design: (work@tb_operators) |vpiNet: \_logic_net: (work@memory_ctrl1.o1), line:65:5, endln:65:7 |vpiParent: - \_module: work@memory_ctrl1 (work@memory_ctrl1), file:${SURELOG_DIR}/tests/UnitTest/top.v, line:57:1, endln:67:10 + \_module_inst: work@memory_ctrl1 (work@memory_ctrl1), file:${SURELOG_DIR}/tests/UnitTest/top.v, line:57:1, endln:67:10 |vpiTypespec: \_logic_typespec: , line:65:1, endln:65:4 |vpiName:o1 @@ -1706,21 +1706,21 @@ design: (work@tb_operators) |vpiPort: \_port: (sif1), line:57:29, endln:57:33 |vpiParent: - \_module: work@memory_ctrl1 (work@memory_ctrl1), file:${SURELOG_DIR}/tests/UnitTest/top.v, line:57:1, endln:67:10 + \_module_inst: work@memory_ctrl1 (work@memory_ctrl1), file:${SURELOG_DIR}/tests/UnitTest/top.v, line:57:1, endln:67:10 |vpiName:sif1 |vpiDirection:3 |vpiLowConn: \_ref_obj: (work@memory_ctrl1.sif1), line:57:29, endln:57:33 |vpiFullName:work@memory_ctrl1.sif1 |vpiActual: - \_interface: work@mem_if (work@memory_ctrl1.sif1), file:${SURELOG_DIR}/tests/UnitTest/top.v, line:57:0 + \_interface_inst: work@mem_if (work@memory_ctrl1.sif1), file:${SURELOG_DIR}/tests/UnitTest/top.v, line:57:0 |vpiTypedef: \_interface_typespec: (mem_if), line:57:22, endln:57:28 |vpiName:mem_if |vpiPort: \_port: (sif2), line:57:49, endln:57:53 |vpiParent: - \_module: work@memory_ctrl1 (work@memory_ctrl1), file:${SURELOG_DIR}/tests/UnitTest/top.v, line:57:1, endln:67:10 + \_module_inst: work@memory_ctrl1 (work@memory_ctrl1), file:${SURELOG_DIR}/tests/UnitTest/top.v, line:57:1, endln:67:10 |vpiName:sif2 |vpiDirection:3 |vpiLowConn: @@ -1734,17 +1734,17 @@ design: (work@tb_operators) \_interface_typespec: (mem_if), line:57:35, endln:57:41 |vpiName:system |vpiIsModPort:1 - |vpiInterface: - \_interface: work@mem_if (work@memory_ctrl1.sif1), file:${SURELOG_DIR}/tests/UnitTest/top.v, line:57:0 + |vpiInterfaceInst: + \_interface_inst: work@mem_if (work@memory_ctrl1.sif1), file:${SURELOG_DIR}/tests/UnitTest/top.v, line:57:0 |vpiParent: - \_module: work@memory_ctrl1 (work@memory_ctrl1), file:${SURELOG_DIR}/tests/UnitTest/top.v, line:57:1, endln:67:10 + \_module_inst: work@memory_ctrl1 (work@memory_ctrl1), file:${SURELOG_DIR}/tests/UnitTest/top.v, line:57:1, endln:67:10 |vpiName:sif1 |vpiFullName:work@memory_ctrl1.sif1 |vpiDefName:work@mem_if |vpiModport: \_modport: (memory), line:50:12, endln:50:18 |vpiParent: - \_interface: work@mem_if (work@memory_ctrl1.sif1), file:${SURELOG_DIR}/tests/UnitTest/top.v, line:57:0 + \_interface_inst: work@mem_if (work@memory_ctrl1.sif1), file:${SURELOG_DIR}/tests/UnitTest/top.v, line:57:0 |vpiName:memory |vpiIODecl: \_io_decl: (clk), line:50:27, endln:50:30 @@ -1756,12 +1756,12 @@ design: (work@tb_operators) \_logic_typespec: , line:47:25, endln:47:29 |vpiName:clk |vpiNetType:1 - |vpiInterface: - \_interface: work@mem_if (work@memory_ctrl1.sif1), file:${SURELOG_DIR}/tests/UnitTest/top.v, line:57:0 + |vpiInterfaceInst: + \_interface_inst: work@mem_if (work@memory_ctrl1.sif1), file:${SURELOG_DIR}/tests/UnitTest/top.v, line:57:0 |vpiModport: \_modport: (system), line:49:12, endln:49:18 |vpiParent: - \_interface: work@mem_if (work@memory_ctrl1.sif1), file:${SURELOG_DIR}/tests/UnitTest/top.v, line:57:0 + \_interface_inst: work@mem_if (work@memory_ctrl1.sif1), file:${SURELOG_DIR}/tests/UnitTest/top.v, line:57:0 |vpiName:system |vpiIODecl: \_io_decl: (clk), line:49:26, endln:49:29 @@ -1769,21 +1769,21 @@ design: (work@tb_operators) |vpiName:clk |vpiExpr: \_logic_net: (clk), line:47:30, endln:47:33 - |vpiInterface: - \_interface: work@mem_if (work@memory_ctrl1.sif1), file:${SURELOG_DIR}/tests/UnitTest/top.v, line:57:0 - |vpiInterface: - \_interface: work@mem_if (work@memory_ctrl1.sif1), file:${SURELOG_DIR}/tests/UnitTest/top.v, line:57:0 - |vpiInterface: - \_interface: work@mem_if (work@memory_ctrl1.sif2), file:${SURELOG_DIR}/tests/UnitTest/top.v, line:57:0 + |vpiInterfaceInst: + \_interface_inst: work@mem_if (work@memory_ctrl1.sif1), file:${SURELOG_DIR}/tests/UnitTest/top.v, line:57:0 + |vpiInterfaceInst: + \_interface_inst: work@mem_if (work@memory_ctrl1.sif1), file:${SURELOG_DIR}/tests/UnitTest/top.v, line:57:0 + |vpiInterfaceInst: + \_interface_inst: work@mem_if (work@memory_ctrl1.sif2), file:${SURELOG_DIR}/tests/UnitTest/top.v, line:57:0 |vpiParent: - \_module: work@memory_ctrl1 (work@memory_ctrl1), file:${SURELOG_DIR}/tests/UnitTest/top.v, line:57:1, endln:67:10 + \_module_inst: work@memory_ctrl1 (work@memory_ctrl1), file:${SURELOG_DIR}/tests/UnitTest/top.v, line:57:1, endln:67:10 |vpiName:sif2 |vpiFullName:work@memory_ctrl1.sif2 |vpiDefName:work@mem_if |vpiModport: \_modport: (system), line:49:12, endln:49:18 |vpiParent: - \_interface: work@mem_if (work@memory_ctrl1.sif2), file:${SURELOG_DIR}/tests/UnitTest/top.v, line:57:0 + \_interface_inst: work@mem_if (work@memory_ctrl1.sif2), file:${SURELOG_DIR}/tests/UnitTest/top.v, line:57:0 |vpiName:system |vpiIODecl: \_io_decl: (clk), line:49:26, endln:49:29 @@ -1795,8 +1795,8 @@ design: (work@tb_operators) \_logic_typespec: , line:47:25, endln:47:29 |vpiName:clk |vpiNetType:1 - |vpiInterface: - \_interface: work@mem_if (work@memory_ctrl1.sif2), file:${SURELOG_DIR}/tests/UnitTest/top.v, line:57:0 + |vpiInterfaceInst: + \_interface_inst: work@mem_if (work@memory_ctrl1.sif2), file:${SURELOG_DIR}/tests/UnitTest/top.v, line:57:0 =================== [ FATAL] : 0 [ SYNTAX] : 0 diff --git a/tests/UnitThisNew/UnitThisNew.log b/tests/UnitThisNew/UnitThisNew.log index 208b0e0f98..a54083dd5f 100644 --- a/tests/UnitThisNew/UnitThisNew.log +++ b/tests/UnitThisNew/UnitThisNew.log @@ -596,7 +596,7 @@ int_var 4 io_decl 19 logic_var 1 method_func_call 10 -module 2 +module_inst 2 operation 4 package 5 range 2 @@ -635,7 +635,7 @@ int_var 4 io_decl 38 logic_var 1 method_func_call 20 -module 2 +module_inst 2 operation 8 package 5 range 2 diff --git a/tests/UnpackPort/UnpackPort.log b/tests/UnpackPort/UnpackPort.log index 1cdf9ecadc..74d41c05a6 100644 --- a/tests/UnpackPort/UnpackPort.log +++ b/tests/UnpackPort/UnpackPort.log @@ -433,7 +433,7 @@ io_decl 11 logic_net 1 logic_typespec 8 logic_var 1 -module 4 +module_inst 4 operation 25 package 2 parameter 7 @@ -469,7 +469,7 @@ io_decl 22 logic_net 1 logic_typespec 8 logic_var 1 -module 4 +module_inst 4 operation 32 package 2 parameter 7 @@ -969,17 +969,17 @@ design: (work@dut) \_int_typespec: |vpiSigned:1 |uhdmallModules: -\_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/UnpackPort/dut.sv, line:1:1, endln:11:10 +\_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/UnpackPort/dut.sv, line:1:1, endln:11:10 |vpiParent: \_design: (work@dut) |vpiFullName:work@dut |vpiTypedef: \_struct_typespec: (struct2), line:2:11, endln:2:17 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/UnpackPort/dut.sv, line:1:1, endln:11:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/UnpackPort/dut.sv, line:1:1, endln:11:10 |vpiName:struct2 |vpiInstance: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/UnpackPort/dut.sv, line:1:1, endln:11:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/UnpackPort/dut.sv, line:1:1, endln:11:10 |vpiPacked:1 |vpiTypespecMember: \_typespec_member: (third), line:3:19, endln:3:24 @@ -1019,13 +1019,13 @@ design: (work@dut) |vpiNet: \_logic_net: (work@dut.var3), line:1:12, endln:1:16 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/UnpackPort/dut.sv, line:1:1, endln:11:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/UnpackPort/dut.sv, line:1:1, endln:11:10 |vpiName:var3 |vpiFullName:work@dut.var3 |vpiPort: \_port: (var3), line:1:12, endln:1:16 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/UnpackPort/dut.sv, line:1:1, endln:11:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/UnpackPort/dut.sv, line:1:1, endln:11:10 |vpiName:var3 |vpiDirection:2 |vpiLowConn: @@ -1066,7 +1066,7 @@ design: (work@dut) |vpiElemTypespec: \_struct_typespec: (struct2), line:2:11, endln:2:17 |uhdmtopModules: -\_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/UnpackPort/dut.sv, line:1:1, endln:11:10 +\_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/UnpackPort/dut.sv, line:1:1, endln:11:10 |vpiName:work@dut |vpiTypedef: \_struct_typespec: (struct2), line:2:11, endln:2:17 @@ -1075,7 +1075,7 @@ design: (work@dut) |vpiArrayNet: \_array_net: (work@dut.var3), line:1:12, endln:1:16 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/UnpackPort/dut.sv, line:1:1, endln:11:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/UnpackPort/dut.sv, line:1:1, endln:11:10 |vpiSize:7 |vpiName:var3 |vpiFullName:work@dut.var3 @@ -1117,7 +1117,7 @@ design: (work@dut) |vpiPort: \_port: (var3), line:1:12, endln:1:16 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/UnpackPort/dut.sv, line:1:1, endln:11:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/UnpackPort/dut.sv, line:1:1, endln:11:10 |vpiName:var3 |vpiDirection:2 |vpiLowConn: @@ -1131,11 +1131,11 @@ design: (work@dut) |vpiTypedef: \_struct_typespec: (struct2), line:2:11, endln:2:17 |vpiInstance: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/UnpackPort/dut.sv, line:1:1, endln:11:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/UnpackPort/dut.sv, line:1:1, endln:11:10 |vpiGenScopeArray: \_gen_scope_array: (work@dut.g_fill[0]), line:8:30, endln:10:6 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/UnpackPort/dut.sv, line:1:1, endln:11:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/UnpackPort/dut.sv, line:1:1, endln:11:10 |vpiName:g_fill[0] |vpiFullName:work@dut.g_fill[0] |vpiGenScope: @@ -1167,7 +1167,7 @@ design: (work@dut) \_operation: , line:9:24, endln:9:37 |vpiName:struct2 |vpiInstance: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/UnpackPort/dut.sv, line:1:1, endln:11:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/UnpackPort/dut.sv, line:1:1, endln:11:10 |vpiPacked:1 |vpiTypespecMember: \_typespec_member: (third), line:3:19, endln:3:24 @@ -1237,7 +1237,7 @@ design: (work@dut) |vpiGenScopeArray: \_gen_scope_array: (work@dut.g_fill[1]), line:8:30, endln:10:6 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/UnpackPort/dut.sv, line:1:1, endln:11:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/UnpackPort/dut.sv, line:1:1, endln:11:10 |vpiName:g_fill[1] |vpiFullName:work@dut.g_fill[1] |vpiGenScope: @@ -1269,7 +1269,7 @@ design: (work@dut) \_operation: , line:9:24, endln:9:37 |vpiName:struct2 |vpiInstance: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/UnpackPort/dut.sv, line:1:1, endln:11:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/UnpackPort/dut.sv, line:1:1, endln:11:10 |vpiPacked:1 |vpiTypespecMember: \_typespec_member: (third), line:3:19, endln:3:24 @@ -1339,7 +1339,7 @@ design: (work@dut) |vpiGenScopeArray: \_gen_scope_array: (work@dut.g_fill[2]), line:8:30, endln:10:6 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/UnpackPort/dut.sv, line:1:1, endln:11:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/UnpackPort/dut.sv, line:1:1, endln:11:10 |vpiName:g_fill[2] |vpiFullName:work@dut.g_fill[2] |vpiGenScope: @@ -1371,7 +1371,7 @@ design: (work@dut) \_operation: , line:9:24, endln:9:37 |vpiName:struct2 |vpiInstance: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/UnpackPort/dut.sv, line:1:1, endln:11:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/UnpackPort/dut.sv, line:1:1, endln:11:10 |vpiPacked:1 |vpiTypespecMember: \_typespec_member: (third), line:3:19, endln:3:24 @@ -1441,7 +1441,7 @@ design: (work@dut) |vpiGenScopeArray: \_gen_scope_array: (work@dut.g_fill[3]), line:8:30, endln:10:6 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/UnpackPort/dut.sv, line:1:1, endln:11:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/UnpackPort/dut.sv, line:1:1, endln:11:10 |vpiName:g_fill[3] |vpiFullName:work@dut.g_fill[3] |vpiGenScope: @@ -1473,7 +1473,7 @@ design: (work@dut) \_operation: , line:9:24, endln:9:37 |vpiName:struct2 |vpiInstance: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/UnpackPort/dut.sv, line:1:1, endln:11:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/UnpackPort/dut.sv, line:1:1, endln:11:10 |vpiPacked:1 |vpiTypespecMember: \_typespec_member: (third), line:3:19, endln:3:24 @@ -1543,7 +1543,7 @@ design: (work@dut) |vpiGenScopeArray: \_gen_scope_array: (work@dut.g_fill[4]), line:8:30, endln:10:6 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/UnpackPort/dut.sv, line:1:1, endln:11:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/UnpackPort/dut.sv, line:1:1, endln:11:10 |vpiName:g_fill[4] |vpiFullName:work@dut.g_fill[4] |vpiGenScope: @@ -1575,7 +1575,7 @@ design: (work@dut) \_operation: , line:9:24, endln:9:37 |vpiName:struct2 |vpiInstance: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/UnpackPort/dut.sv, line:1:1, endln:11:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/UnpackPort/dut.sv, line:1:1, endln:11:10 |vpiPacked:1 |vpiTypespecMember: \_typespec_member: (third), line:3:19, endln:3:24 @@ -1645,7 +1645,7 @@ design: (work@dut) |vpiGenScopeArray: \_gen_scope_array: (work@dut.g_fill[5]), line:8:30, endln:10:6 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/UnpackPort/dut.sv, line:1:1, endln:11:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/UnpackPort/dut.sv, line:1:1, endln:11:10 |vpiName:g_fill[5] |vpiFullName:work@dut.g_fill[5] |vpiGenScope: @@ -1677,7 +1677,7 @@ design: (work@dut) \_operation: , line:9:24, endln:9:37 |vpiName:struct2 |vpiInstance: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/UnpackPort/dut.sv, line:1:1, endln:11:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/UnpackPort/dut.sv, line:1:1, endln:11:10 |vpiPacked:1 |vpiTypespecMember: \_typespec_member: (third), line:3:19, endln:3:24 @@ -1747,7 +1747,7 @@ design: (work@dut) |vpiGenScopeArray: \_gen_scope_array: (work@dut.g_fill[6]), line:8:30, endln:10:6 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/UnpackPort/dut.sv, line:1:1, endln:11:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/UnpackPort/dut.sv, line:1:1, endln:11:10 |vpiName:g_fill[6] |vpiFullName:work@dut.g_fill[6] |vpiGenScope: @@ -1779,7 +1779,7 @@ design: (work@dut) \_operation: , line:9:24, endln:9:37 |vpiName:struct2 |vpiInstance: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/UnpackPort/dut.sv, line:1:1, endln:11:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/UnpackPort/dut.sv, line:1:1, endln:11:10 |vpiPacked:1 |vpiTypespecMember: \_typespec_member: (third), line:3:19, endln:3:24 diff --git a/tests/UnpackedTypespec/UnpackedTypespec.log b/tests/UnpackedTypespec/UnpackedTypespec.log index b2400b02c6..52636561fc 100644 --- a/tests/UnpackedTypespec/UnpackedTypespec.log +++ b/tests/UnpackedTypespec/UnpackedTypespec.log @@ -230,7 +230,7 @@ int_typespec 3 integer_typespec 1 logic_net 1 logic_typespec 2 -module 5 +module_inst 5 operation 1 packed_array_typespec 7 range 15 @@ -250,7 +250,7 @@ int_typespec 3 integer_typespec 1 logic_net 1 logic_typespec 2 -module 5 +module_inst 5 operation 1 packed_array_typespec 7 range 15 @@ -270,17 +270,17 @@ design: (work@top) |vpiElaborated:1 |vpiName:work@top |uhdmallModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/UnpackedTypespec/dut.sv, line:1:1, endln:23:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/UnpackedTypespec/dut.sv, line:1:1, endln:23:10 |vpiParent: \_design: (work@top) |vpiFullName:work@top |vpiTypedef: \_packed_array_typespec: (fmt_unit_types_t), line:16:11, endln:16:22 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/UnpackedTypespec/dut.sv, line:1:1, endln:23:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/UnpackedTypespec/dut.sv, line:1:1, endln:23:10 |vpiName:fmt_unit_types_t |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/UnpackedTypespec/dut.sv, line:1:1, endln:23:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/UnpackedTypespec/dut.sv, line:1:1, endln:23:10 |vpiRange: \_range: , line:16:23, endln:16:28 |vpiLeftRange: @@ -302,10 +302,10 @@ design: (work@top) |vpiElemTypespec: \_enum_typespec: (unit_type_t), line:10:4, endln:14:17 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/UnpackedTypespec/dut.sv, line:1:1, endln:23:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/UnpackedTypespec/dut.sv, line:1:1, endln:23:10 |vpiName:unit_type_t |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/UnpackedTypespec/dut.sv, line:1:1, endln:23:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/UnpackedTypespec/dut.sv, line:1:1, endln:23:10 |vpiBaseTypespec: \_logic_typespec: , line:10:17, endln:10:28 |vpiRange: @@ -347,10 +347,10 @@ design: (work@top) |vpiTypedef: \_array_typespec: (fmt_unit_types_t_u) |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/UnpackedTypespec/dut.sv, line:1:1, endln:23:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/UnpackedTypespec/dut.sv, line:1:1, endln:23:10 |vpiName:fmt_unit_types_t_u |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/UnpackedTypespec/dut.sv, line:1:1, endln:23:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/UnpackedTypespec/dut.sv, line:1:1, endln:23:10 |vpiRange: \_range: , line:18:49, endln:18:54 |vpiParent: @@ -396,10 +396,10 @@ design: (work@top) |vpiTypedef: \_array_typespec: (logic_7_0_t) |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/UnpackedTypespec/dut.sv, line:1:1, endln:23:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/UnpackedTypespec/dut.sv, line:1:1, endln:23:10 |vpiName:logic_7_0_t |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/UnpackedTypespec/dut.sv, line:1:1, endln:23:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/UnpackedTypespec/dut.sv, line:1:1, endln:23:10 |vpiRange: \_range: , line:7:35, endln:7:40 |vpiLeftRange: @@ -441,10 +441,10 @@ design: (work@top) |vpiTypedef: \_packed_array_typespec: (opgrp_fmt_unit_types_t), line:21:11, endln:21:27 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/UnpackedTypespec/dut.sv, line:1:1, endln:23:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/UnpackedTypespec/dut.sv, line:1:1, endln:23:10 |vpiName:opgrp_fmt_unit_types_t |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/UnpackedTypespec/dut.sv, line:1:1, endln:23:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/UnpackedTypespec/dut.sv, line:1:1, endln:23:10 |vpiRange: \_range: , line:21:28, endln:21:33 |vpiLeftRange: @@ -468,10 +468,10 @@ design: (work@top) |vpiTypedef: \_array_typespec: (triple) |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/UnpackedTypespec/dut.sv, line:1:1, endln:23:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/UnpackedTypespec/dut.sv, line:1:1, endln:23:10 |vpiName:triple |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/UnpackedTypespec/dut.sv, line:1:1, endln:23:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/UnpackedTypespec/dut.sv, line:1:1, endln:23:10 |vpiRange: \_range: , line:4:22, endln:4:27 |vpiLeftRange: @@ -499,16 +499,16 @@ design: (work@top) |vpiNet: \_logic_net: (work@top.b), line:5:10, endln:5:11 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/UnpackedTypespec/dut.sv, line:1:1, endln:23:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/UnpackedTypespec/dut.sv, line:1:1, endln:23:10 |vpiName:b |vpiFullName:work@top.b |uhdmtopModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/UnpackedTypespec/dut.sv, line:1:1, endln:23:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/UnpackedTypespec/dut.sv, line:1:1, endln:23:10 |vpiName:work@top |vpiVariables: \_array_var: (work@top.b), line:5:10, endln:5:11 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/UnpackedTypespec/dut.sv, line:1:1, endln:23:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/UnpackedTypespec/dut.sv, line:1:1, endln:23:10 |vpiTypespec: \_array_typespec: (triple) |vpiName:triple diff --git a/tests/UnsignedParam/UnsignedParam.log b/tests/UnsignedParam/UnsignedParam.log index 53b731cb98..cd926b8c16 100644 --- a/tests/UnsignedParam/UnsignedParam.log +++ b/tests/UnsignedParam/UnsignedParam.log @@ -205,7 +205,7 @@ design 1 gen_scope 2 gen_scope_array 2 int_typespec 11 -module 7 +module_inst 7 operation 5 param_assign 8 parameter 8 @@ -220,7 +220,7 @@ design 1 gen_scope 3 gen_scope_array 3 int_typespec 11 -module 8 +module_inst 8 operation 5 param_assign 8 parameter 8 @@ -240,20 +240,20 @@ design: (work@top) |vpiElaborated:1 |vpiName:work@top |uhdmallModules: -\_module: work@GOOD (work@GOOD), file:${SURELOG_DIR}/tests/UnsignedParam/dut.sv, line:1:1, endln:2:10 +\_module_inst: work@GOOD (work@GOOD), file:${SURELOG_DIR}/tests/UnsignedParam/dut.sv, line:1:1, endln:2:10 |vpiParent: \_design: (work@top) |vpiFullName:work@GOOD |vpiDefName:work@GOOD |uhdmallModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/UnsignedParam/dut.sv, line:4:1, endln:13:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/UnsignedParam/dut.sv, line:4:1, endln:13:10 |vpiParent: \_design: (work@top) |vpiFullName:work@top |vpiParameter: \_parameter: (work@top.n), line:5:28, endln:5:29 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/UnsignedParam/dut.sv, line:4:1, endln:13:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/UnsignedParam/dut.sv, line:4:1, endln:13:10 |HEX:80000000 |vpiTypespec: \_int_typespec: , line:5:14, endln:5:20 @@ -284,7 +284,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.n2), line:6:28, endln:6:30 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/UnsignedParam/dut.sv, line:4:1, endln:13:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/UnsignedParam/dut.sv, line:4:1, endln:13:10 |vpiTypespec: \_int_typespec: , line:6:14, endln:6:20 |vpiParent: @@ -314,7 +314,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.n3), line:7:28, endln:7:30 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/UnsignedParam/dut.sv, line:4:1, endln:13:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/UnsignedParam/dut.sv, line:4:1, endln:13:10 |HEX:8FFFFFFFFFFF0000 |vpiTypespec: \_int_typespec: , line:7:14, endln:7:20 @@ -345,7 +345,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.n4), line:8:28, endln:8:30 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/UnsignedParam/dut.sv, line:4:1, endln:13:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/UnsignedParam/dut.sv, line:4:1, endln:13:10 |vpiTypespec: \_int_typespec: , line:8:14, endln:8:20 |vpiParent: @@ -375,7 +375,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:5:28, endln:5:45 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/UnsignedParam/dut.sv, line:4:1, endln:13:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/UnsignedParam/dut.sv, line:4:1, endln:13:10 |vpiRhs: \_constant: , line:5:32, endln:5:45 |vpiDecompile:32'h8000_0000 @@ -389,7 +389,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:6:28, endln:6:41 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/UnsignedParam/dut.sv, line:4:1, endln:13:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/UnsignedParam/dut.sv, line:4:1, endln:13:10 |vpiRhs: \_operation: , line:6:33, endln:6:41 |vpiOpType:24 @@ -411,7 +411,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:7:28, endln:7:56 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/UnsignedParam/dut.sv, line:4:1, endln:13:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/UnsignedParam/dut.sv, line:4:1, endln:13:10 |vpiRhs: \_constant: , line:7:33, endln:7:56 |vpiDecompile:64'h8FFF_FFFF_FFFF_0000 @@ -425,7 +425,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:8:28, endln:8:61 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/UnsignedParam/dut.sv, line:4:1, endln:13:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/UnsignedParam/dut.sv, line:4:1, endln:13:10 |vpiRhs: \_operation: , line:8:33, endln:8:61 |vpiOpType:24 @@ -446,12 +446,12 @@ design: (work@top) \_parameter: (work@top.n4), line:8:28, endln:8:30 |vpiDefName:work@top |uhdmtopModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/UnsignedParam/dut.sv, line:4:1, endln:13:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/UnsignedParam/dut.sv, line:4:1, endln:13:10 |vpiName:work@top |vpiParameter: \_parameter: (work@top.n), line:5:28, endln:5:29 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/UnsignedParam/dut.sv, line:4:1, endln:13:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/UnsignedParam/dut.sv, line:4:1, endln:13:10 |HEX:80000000 |vpiTypespec: \_int_typespec: , line:5:14, endln:5:20 @@ -484,7 +484,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.n2), line:6:28, endln:6:30 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/UnsignedParam/dut.sv, line:4:1, endln:13:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/UnsignedParam/dut.sv, line:4:1, endln:13:10 |vpiTypespec: \_int_typespec: , line:6:14, endln:6:20 |vpiParent: @@ -516,7 +516,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.n3), line:7:28, endln:7:30 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/UnsignedParam/dut.sv, line:4:1, endln:13:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/UnsignedParam/dut.sv, line:4:1, endln:13:10 |HEX:8FFFFFFFFFFF0000 |vpiTypespec: \_int_typespec: , line:7:14, endln:7:20 @@ -549,7 +549,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.n4), line:8:28, endln:8:30 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/UnsignedParam/dut.sv, line:4:1, endln:13:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/UnsignedParam/dut.sv, line:4:1, endln:13:10 |vpiTypespec: \_int_typespec: , line:8:14, endln:8:20 |vpiParent: @@ -581,7 +581,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:5:28, endln:5:45 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/UnsignedParam/dut.sv, line:4:1, endln:13:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/UnsignedParam/dut.sv, line:4:1, endln:13:10 |vpiRhs: \_constant: , line:5:32, endln:5:45 |vpiDecompile:64'h80000000 @@ -595,7 +595,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:6:28, endln:6:41 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/UnsignedParam/dut.sv, line:4:1, endln:13:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/UnsignedParam/dut.sv, line:4:1, endln:13:10 |vpiRhs: \_constant: , line:6:33, endln:6:41 |vpiDecompile:2147483649 @@ -609,7 +609,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:7:28, endln:7:56 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/UnsignedParam/dut.sv, line:4:1, endln:13:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/UnsignedParam/dut.sv, line:4:1, endln:13:10 |vpiRhs: \_constant: , line:7:33, endln:7:56 |vpiDecompile:64'h8FFFFFFFFFFF0000 @@ -623,7 +623,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:8:28, endln:8:61 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/UnsignedParam/dut.sv, line:4:1, endln:13:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/UnsignedParam/dut.sv, line:4:1, endln:13:10 |vpiRhs: \_constant: , line:8:33, endln:8:61 |vpiDecompile:10376293541461622783 @@ -640,7 +640,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.genblk1), line:10:3, endln:12:6 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/UnsignedParam/dut.sv, line:4:1, endln:13:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/UnsignedParam/dut.sv, line:4:1, endln:13:10 |vpiName:genblk1 |vpiFullName:work@top.genblk1 |vpiGenScope: @@ -648,8 +648,8 @@ design: (work@top) |vpiParent: \_gen_scope_array: (work@top.genblk1), line:10:3, endln:12:6 |vpiFullName:work@top.genblk1 - |vpiModule: - \_module: work@GOOD (work@top.genblk1.good), file:${SURELOG_DIR}/tests/UnsignedParam/dut.sv, line:11:4, endln:11:16 + |vpiModuleInst: + \_module_inst: work@GOOD (work@top.genblk1.good), file:${SURELOG_DIR}/tests/UnsignedParam/dut.sv, line:11:4, endln:11:16 |vpiParent: \_gen_scope: (work@top.genblk1) |vpiName:good diff --git a/tests/UnsizeConstExpr/UnsizeConstExpr.log b/tests/UnsizeConstExpr/UnsizeConstExpr.log index 9c83619928..b2104525fd 100644 --- a/tests/UnsizeConstExpr/UnsizeConstExpr.log +++ b/tests/UnsizeConstExpr/UnsizeConstExpr.log @@ -97,7 +97,7 @@ design 1 logic_net 2 logic_typespec 1 logic_var 1 -module 4 +module_inst 4 operation 2 part_select 2 range 2 @@ -112,7 +112,7 @@ design 1 logic_net 2 logic_typespec 1 logic_var 1 -module 4 +module_inst 4 operation 3 part_select 3 range 2 @@ -131,7 +131,7 @@ design: (work@top) |vpiElaborated:1 |vpiName:work@top |uhdmallModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/UnsizeConstExpr/dut.sv, line:1:1, endln:7:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/UnsizeConstExpr/dut.sv, line:1:1, endln:7:10 |vpiParent: \_design: (work@top) |vpiFullName:work@top @@ -139,14 +139,14 @@ design: (work@top) |vpiNet: \_logic_net: (work@top.product_exponent), line:3:14, endln:3:30 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/UnsizeConstExpr/dut.sv, line:1:1, endln:7:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/UnsizeConstExpr/dut.sv, line:1:1, endln:7:10 |vpiName:product_exponent |vpiFullName:work@top.product_exponent |vpiNetType:36 |vpiContAssign: \_cont_assign: , line:5:8, endln:5:39 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/UnsizeConstExpr/dut.sv, line:1:1, endln:7:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/UnsizeConstExpr/dut.sv, line:1:1, endln:7:10 |vpiRhs: \_operation: , line:5:12, endln:5:39 |vpiParent: @@ -191,12 +191,12 @@ design: (work@top) |vpiActual: \_logic_net: (p) |uhdmtopModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/UnsizeConstExpr/dut.sv, line:1:1, endln:7:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/UnsizeConstExpr/dut.sv, line:1:1, endln:7:10 |vpiName:work@top |vpiVariables: \_logic_var: (work@top.product_exponent), line:3:14, endln:3:30 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/UnsizeConstExpr/dut.sv, line:1:1, endln:7:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/UnsizeConstExpr/dut.sv, line:1:1, endln:7:10 |vpiTypespec: \_logic_typespec: , line:3:1, endln:3:13 |vpiRange: @@ -248,7 +248,7 @@ design: (work@top) |vpiContAssign: \_cont_assign: , line:5:8, endln:5:39 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/UnsizeConstExpr/dut.sv, line:1:1, endln:7:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/UnsizeConstExpr/dut.sv, line:1:1, endln:7:10 |vpiRhs: \_operation: , line:5:12, endln:5:39 |vpiParent: diff --git a/tests/Unsized/Unsized.log b/tests/Unsized/Unsized.log index 2793295372..81c622b118 100644 --- a/tests/Unsized/Unsized.log +++ b/tests/Unsized/Unsized.log @@ -26,7 +26,7 @@ design 1 logic_net 4 logic_typespec 4 logic_var 4 -module 3 +module_inst 3 range 8 === UHDM Object Stats End === [INF:UH0707] Elaborating UHDM... @@ -37,7 +37,7 @@ design 1 logic_net 4 logic_typespec 4 logic_var 4 -module 3 +module_inst 3 range 8 === UHDM Object Stats End === [INF:UH0708] Writing UHDM DB: ${SURELOG_DIR}/build/regression/Unsized/slpp_all/surelog.uhdm ... @@ -53,7 +53,7 @@ design: (work@top) |vpiElaborated:1 |vpiName:work@top |uhdmallModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/Unsized/dut.sv, line:1:2, endln:6:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/Unsized/dut.sv, line:1:2, endln:6:10 |vpiParent: \_design: (work@top) |vpiFullName:work@top @@ -61,38 +61,38 @@ design: (work@top) |vpiNet: \_logic_net: (work@top.a), line:2:17, endln:2:18 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/Unsized/dut.sv, line:1:2, endln:6:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/Unsized/dut.sv, line:1:2, endln:6:10 |vpiName:a |vpiFullName:work@top.a |vpiNetType:36 |vpiNet: \_logic_net: (work@top.b), line:3:17, endln:3:18 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/Unsized/dut.sv, line:1:2, endln:6:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/Unsized/dut.sv, line:1:2, endln:6:10 |vpiName:b |vpiFullName:work@top.b |vpiNetType:36 |vpiNet: \_logic_net: (work@top.c), line:4:17, endln:4:18 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/Unsized/dut.sv, line:1:2, endln:6:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/Unsized/dut.sv, line:1:2, endln:6:10 |vpiName:c |vpiFullName:work@top.c |vpiNetType:36 |vpiNet: \_logic_net: (work@top.d), line:5:17, endln:5:18 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/Unsized/dut.sv, line:1:2, endln:6:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/Unsized/dut.sv, line:1:2, endln:6:10 |vpiName:d |vpiFullName:work@top.d |vpiNetType:36 |uhdmtopModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/Unsized/dut.sv, line:1:2, endln:6:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/Unsized/dut.sv, line:1:2, endln:6:10 |vpiName:work@top |vpiVariables: \_logic_var: (work@top.a), line:2:17, endln:2:23 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/Unsized/dut.sv, line:1:2, endln:6:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/Unsized/dut.sv, line:1:2, endln:6:10 |vpiTypespec: \_logic_typespec: , line:2:4, endln:2:16 |vpiRange: @@ -143,7 +143,7 @@ design: (work@top) |vpiVariables: \_logic_var: (work@top.b), line:3:17, endln:3:23 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/Unsized/dut.sv, line:1:2, endln:6:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/Unsized/dut.sv, line:1:2, endln:6:10 |vpiTypespec: \_logic_typespec: , line:3:4, endln:3:16 |vpiRange: @@ -194,7 +194,7 @@ design: (work@top) |vpiVariables: \_logic_var: (work@top.c), line:4:17, endln:4:23 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/Unsized/dut.sv, line:1:2, endln:6:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/Unsized/dut.sv, line:1:2, endln:6:10 |vpiTypespec: \_logic_typespec: , line:4:4, endln:4:16 |vpiRange: @@ -245,7 +245,7 @@ design: (work@top) |vpiVariables: \_logic_var: (work@top.d), line:5:17, endln:5:23 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/Unsized/dut.sv, line:1:2, endln:6:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/Unsized/dut.sv, line:1:2, endln:6:10 |vpiTypespec: \_logic_typespec: , line:5:4, endln:5:16 |vpiRange: diff --git a/tests/UnsizedArray/UnsizedArray.log b/tests/UnsizedArray/UnsizedArray.log index 68826c3e1a..1ce0582520 100644 --- a/tests/UnsizedArray/UnsizedArray.log +++ b/tests/UnsizedArray/UnsizedArray.log @@ -68,7 +68,7 @@ byte_var 1 constant 5 design 1 logic_net 1 -module 3 +module_inst 3 operation 1 range 1 === UHDM Object Stats End === @@ -82,7 +82,7 @@ byte_var 1 constant 5 design 1 logic_net 1 -module 3 +module_inst 3 operation 1 range 1 === UHDM Object Stats End === @@ -99,7 +99,7 @@ design: (work@top) |vpiElaborated:1 |vpiName:work@top |uhdmallModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/UnsizedArray/dut.sv, line:1:1, endln:4:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/UnsizedArray/dut.sv, line:1:1, endln:4:10 |vpiParent: \_design: (work@top) |vpiFullName:work@top @@ -107,16 +107,16 @@ design: (work@top) |vpiNet: \_logic_net: (work@top.b), line:2:9, endln:2:10 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/UnsizedArray/dut.sv, line:1:1, endln:4:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/UnsizedArray/dut.sv, line:1:1, endln:4:10 |vpiName:b |vpiFullName:work@top.b |uhdmtopModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/UnsizedArray/dut.sv, line:1:1, endln:4:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/UnsizedArray/dut.sv, line:1:1, endln:4:10 |vpiName:work@top |vpiVariables: \_array_var: (work@top.b), line:2:9, endln:2:12 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/UnsizedArray/dut.sv, line:1:1, endln:4:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/UnsizedArray/dut.sv, line:1:1, endln:4:10 |vpiSize:1 |vpiTypespec: \_array_typespec: diff --git a/tests/UnsizedConstInst/UnsizedConstInst.log b/tests/UnsizedConstInst/UnsizedConstInst.log index c7cc3b7ee4..6468066330 100644 --- a/tests/UnsizedConstInst/UnsizedConstInst.log +++ b/tests/UnsizedConstInst/UnsizedConstInst.log @@ -169,7 +169,7 @@ int_typespec 3 logic_net 2 logic_typespec 2 logic_var 2 -module 10 +module_inst 10 operation 3 param_assign 3 parameter 3 @@ -189,7 +189,7 @@ int_typespec 3 logic_net 2 logic_typespec 2 logic_var 2 -module 10 +module_inst 10 operation 5 param_assign 3 parameter 3 @@ -210,14 +210,14 @@ design: (work@top) |vpiElaborated:1 |vpiName:work@top |uhdmallModules: -\_module: work@bottom (work@bottom), file:${SURELOG_DIR}/tests/UnsizedConstInst/dut.sv, line:1:1, endln:7:10 +\_module_inst: work@bottom (work@bottom), file:${SURELOG_DIR}/tests/UnsizedConstInst/dut.sv, line:1:1, endln:7:10 |vpiParent: \_design: (work@top) |vpiFullName:work@bottom |vpiParameter: \_parameter: (work@bottom.P), line:2:13, endln:2:14 |vpiParent: - \_module: work@bottom (work@bottom), file:${SURELOG_DIR}/tests/UnsizedConstInst/dut.sv, line:1:1, endln:7:10 + \_module_inst: work@bottom (work@bottom), file:${SURELOG_DIR}/tests/UnsizedConstInst/dut.sv, line:1:1, endln:7:10 |UINT:0 |vpiTypespec: \_int_typespec: @@ -226,7 +226,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:2:13, endln:2:18 |vpiParent: - \_module: work@bottom (work@bottom), file:${SURELOG_DIR}/tests/UnsizedConstInst/dut.sv, line:1:1, endln:7:10 + \_module_inst: work@bottom (work@bottom), file:${SURELOG_DIR}/tests/UnsizedConstInst/dut.sv, line:1:1, endln:7:10 |vpiRhs: \_constant: , line:2:17, endln:2:18 |vpiDecompile:0 @@ -241,14 +241,14 @@ design: (work@top) |vpiNet: \_logic_net: (work@bottom.product_exponent), line:3:9, endln:3:25 |vpiParent: - \_module: work@bottom (work@bottom), file:${SURELOG_DIR}/tests/UnsizedConstInst/dut.sv, line:1:1, endln:7:10 + \_module_inst: work@bottom (work@bottom), file:${SURELOG_DIR}/tests/UnsizedConstInst/dut.sv, line:1:1, endln:7:10 |vpiName:product_exponent |vpiFullName:work@bottom.product_exponent |vpiNetType:36 |vpiContAssign: \_cont_assign: , line:5:10, endln:5:41 |vpiParent: - \_module: work@bottom (work@bottom), file:${SURELOG_DIR}/tests/UnsizedConstInst/dut.sv, line:1:1, endln:7:10 + \_module_inst: work@bottom (work@bottom), file:${SURELOG_DIR}/tests/UnsizedConstInst/dut.sv, line:1:1, endln:7:10 |vpiRhs: \_operation: , line:5:14, endln:5:41 |vpiParent: @@ -290,27 +290,27 @@ design: (work@top) |vpiActual: \_logic_net: (p) |uhdmallModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/UnsizedConstInst/dut.sv, line:9:1, endln:12:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/UnsizedConstInst/dut.sv, line:9:1, endln:12:10 |vpiParent: \_design: (work@top) |vpiFullName:work@top |vpiDefName:work@top |uhdmtopModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/UnsizedConstInst/dut.sv, line:9:1, endln:12:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/UnsizedConstInst/dut.sv, line:9:1, endln:12:10 |vpiName:work@top |vpiDefName:work@top |vpiTop:1 |vpiTopModule:1 - |vpiModule: - \_module: work@bottom (work@top.u1), file:${SURELOG_DIR}/tests/UnsizedConstInst/dut.sv, line:10:3, endln:10:24 + |vpiModuleInst: + \_module_inst: work@bottom (work@top.u1), file:${SURELOG_DIR}/tests/UnsizedConstInst/dut.sv, line:10:3, endln:10:24 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/UnsizedConstInst/dut.sv, line:9:1, endln:12:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/UnsizedConstInst/dut.sv, line:9:1, endln:12:10 |vpiName:u1 |vpiFullName:work@top.u1 |vpiVariables: \_array_var: (work@top.u1.product_exponent), line:3:9, endln:3:31 |vpiParent: - \_module: work@bottom (work@top.u1), file:${SURELOG_DIR}/tests/UnsizedConstInst/dut.sv, line:10:3, endln:10:24 + \_module_inst: work@bottom (work@top.u1), file:${SURELOG_DIR}/tests/UnsizedConstInst/dut.sv, line:10:3, endln:10:24 |vpiSize:11 |vpiTypespec: \_array_typespec: @@ -347,7 +347,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.u1.P), line:2:13, endln:2:14 |vpiParent: - \_module: work@bottom (work@top.u1), file:${SURELOG_DIR}/tests/UnsizedConstInst/dut.sv, line:10:3, endln:10:24 + \_module_inst: work@bottom (work@top.u1), file:${SURELOG_DIR}/tests/UnsizedConstInst/dut.sv, line:10:3, endln:10:24 |UINT:0 |vpiTypespec: \_int_typespec: @@ -358,7 +358,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:2:13, endln:2:18 |vpiParent: - \_module: work@bottom (work@top.u1), file:${SURELOG_DIR}/tests/UnsizedConstInst/dut.sv, line:10:3, endln:10:24 + \_module_inst: work@bottom (work@top.u1), file:${SURELOG_DIR}/tests/UnsizedConstInst/dut.sv, line:10:3, endln:10:24 |vpiOverriden:1 |vpiRhs: \_constant: , line:2:17, endln:2:18 @@ -378,11 +378,11 @@ design: (work@top) |vpiName:p |vpiNetType:1 |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/UnsizedConstInst/dut.sv, line:9:1, endln:12:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/UnsizedConstInst/dut.sv, line:9:1, endln:12:10 |vpiContAssign: \_cont_assign: , line:5:10, endln:5:41 |vpiParent: - \_module: work@bottom (work@top.u1), file:${SURELOG_DIR}/tests/UnsizedConstInst/dut.sv, line:10:3, endln:10:24 + \_module_inst: work@bottom (work@top.u1), file:${SURELOG_DIR}/tests/UnsizedConstInst/dut.sv, line:10:3, endln:10:24 |vpiRhs: \_operation: , line:5:14, endln:5:41 |vpiParent: @@ -430,16 +430,16 @@ design: (work@top) |vpiFullName:work@top.u1.p |vpiActual: \_logic_net: (p) - |vpiModule: - \_module: work@bottom (work@top.u2), file:${SURELOG_DIR}/tests/UnsizedConstInst/dut.sv, line:11:3, endln:11:24 + |vpiModuleInst: + \_module_inst: work@bottom (work@top.u2), file:${SURELOG_DIR}/tests/UnsizedConstInst/dut.sv, line:11:3, endln:11:24 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/UnsizedConstInst/dut.sv, line:9:1, endln:12:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/UnsizedConstInst/dut.sv, line:9:1, endln:12:10 |vpiName:u2 |vpiFullName:work@top.u2 |vpiVariables: \_array_var: (work@top.u2.product_exponent), line:3:9, endln:3:31 |vpiParent: - \_module: work@bottom (work@top.u2), file:${SURELOG_DIR}/tests/UnsizedConstInst/dut.sv, line:11:3, endln:11:24 + \_module_inst: work@bottom (work@top.u2), file:${SURELOG_DIR}/tests/UnsizedConstInst/dut.sv, line:11:3, endln:11:24 |vpiSize:11 |vpiTypespec: \_array_typespec: @@ -476,7 +476,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.u2.P), line:2:13, endln:2:14 |vpiParent: - \_module: work@bottom (work@top.u2), file:${SURELOG_DIR}/tests/UnsizedConstInst/dut.sv, line:11:3, endln:11:24 + \_module_inst: work@bottom (work@top.u2), file:${SURELOG_DIR}/tests/UnsizedConstInst/dut.sv, line:11:3, endln:11:24 |UINT:0 |vpiTypespec: \_int_typespec: @@ -487,7 +487,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:2:13, endln:2:18 |vpiParent: - \_module: work@bottom (work@top.u2), file:${SURELOG_DIR}/tests/UnsizedConstInst/dut.sv, line:11:3, endln:11:24 + \_module_inst: work@bottom (work@top.u2), file:${SURELOG_DIR}/tests/UnsizedConstInst/dut.sv, line:11:3, endln:11:24 |vpiOverriden:1 |vpiRhs: \_constant: , line:2:17, endln:2:18 @@ -503,11 +503,11 @@ design: (work@top) |vpiDefFile:${SURELOG_DIR}/tests/UnsizedConstInst/dut.sv |vpiDefLineNo:1 |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/UnsizedConstInst/dut.sv, line:9:1, endln:12:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/UnsizedConstInst/dut.sv, line:9:1, endln:12:10 |vpiContAssign: \_cont_assign: , line:5:10, endln:5:41 |vpiParent: - \_module: work@bottom (work@top.u2), file:${SURELOG_DIR}/tests/UnsizedConstInst/dut.sv, line:11:3, endln:11:24 + \_module_inst: work@bottom (work@top.u2), file:${SURELOG_DIR}/tests/UnsizedConstInst/dut.sv, line:11:3, endln:11:24 |vpiRhs: \_operation: , line:5:14, endln:5:41 |vpiParent: diff --git a/tests/UnsizedElabComp/UnsizedElabComp.log b/tests/UnsizedElabComp/UnsizedElabComp.log index 6c357105e2..1ee08739ff 100644 --- a/tests/UnsizedElabComp/UnsizedElabComp.log +++ b/tests/UnsizedElabComp/UnsizedElabComp.log @@ -228,7 +228,7 @@ design 1 gen_scope 4 gen_scope_array 4 logic_typespec 4 -module 8 +module_inst 8 operation 4 param_assign 4 parameter 4 @@ -242,7 +242,7 @@ design 1 gen_scope 6 gen_scope_array 6 logic_typespec 4 -module 10 +module_inst 10 operation 4 param_assign 4 parameter 4 @@ -261,20 +261,20 @@ design: (work@top) |vpiElaborated:1 |vpiName:work@top |uhdmallModules: -\_module: work@GOOD (work@GOOD), file:${SURELOG_DIR}/tests/UnsizedElabComp/dut.sv, line:1:1, endln:2:10 +\_module_inst: work@GOOD (work@GOOD), file:${SURELOG_DIR}/tests/UnsizedElabComp/dut.sv, line:1:1, endln:2:10 |vpiParent: \_design: (work@top) |vpiFullName:work@GOOD |vpiDefName:work@GOOD |uhdmallModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/UnsizedElabComp/dut.sv, line:4:1, endln:23:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/UnsizedElabComp/dut.sv, line:4:1, endln:23:10 |vpiParent: \_design: (work@top) |vpiFullName:work@top |vpiParameter: \_parameter: (work@top.P1), line:5:25, endln:5:27 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/UnsizedElabComp/dut.sv, line:4:1, endln:23:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/UnsizedElabComp/dut.sv, line:4:1, endln:23:10 |BIN:111 |vpiTypespec: \_logic_typespec: , line:5:13, endln:5:24 @@ -303,7 +303,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.P2), line:6:25, endln:6:27 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/UnsizedElabComp/dut.sv, line:4:1, endln:23:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/UnsizedElabComp/dut.sv, line:4:1, endln:23:10 |BIN:110 |vpiTypespec: \_logic_typespec: , line:6:13, endln:6:24 @@ -332,7 +332,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:5:25, endln:5:36 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/UnsizedElabComp/dut.sv, line:4:1, endln:23:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/UnsizedElabComp/dut.sv, line:4:1, endln:23:10 |vpiRhs: \_constant: , line:5:30, endln:5:36 |vpiDecompile:3'b111 @@ -346,7 +346,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:6:25, endln:6:36 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/UnsizedElabComp/dut.sv, line:4:1, endln:23:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/UnsizedElabComp/dut.sv, line:4:1, endln:23:10 |vpiRhs: \_constant: , line:6:30, endln:6:36 |vpiDecompile:3'b110 @@ -359,12 +359,12 @@ design: (work@top) \_parameter: (work@top.P2), line:6:25, endln:6:27 |vpiDefName:work@top |uhdmtopModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/UnsizedElabComp/dut.sv, line:4:1, endln:23:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/UnsizedElabComp/dut.sv, line:4:1, endln:23:10 |vpiName:work@top |vpiParameter: \_parameter: (work@top.P1), line:5:25, endln:5:27 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/UnsizedElabComp/dut.sv, line:4:1, endln:23:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/UnsizedElabComp/dut.sv, line:4:1, endln:23:10 |BIN:111 |vpiTypespec: \_logic_typespec: , line:5:13, endln:5:24 @@ -395,7 +395,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.P2), line:6:25, endln:6:27 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/UnsizedElabComp/dut.sv, line:4:1, endln:23:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/UnsizedElabComp/dut.sv, line:4:1, endln:23:10 |BIN:110 |vpiTypespec: \_logic_typespec: , line:6:13, endln:6:24 @@ -426,7 +426,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:5:25, endln:5:36 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/UnsizedElabComp/dut.sv, line:4:1, endln:23:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/UnsizedElabComp/dut.sv, line:4:1, endln:23:10 |vpiRhs: \_constant: , line:5:30, endln:5:36 |vpiDecompile:3'b111 @@ -440,7 +440,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:6:25, endln:6:36 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/UnsizedElabComp/dut.sv, line:4:1, endln:23:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/UnsizedElabComp/dut.sv, line:4:1, endln:23:10 |vpiRhs: \_constant: , line:6:30, endln:6:36 |vpiDecompile:3'b110 @@ -457,7 +457,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.genblk1), line:7:3, endln:9:6 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/UnsizedElabComp/dut.sv, line:4:1, endln:23:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/UnsizedElabComp/dut.sv, line:4:1, endln:23:10 |vpiName:genblk1 |vpiFullName:work@top.genblk1 |vpiGenScope: @@ -465,8 +465,8 @@ design: (work@top) |vpiParent: \_gen_scope_array: (work@top.genblk1), line:7:3, endln:9:6 |vpiFullName:work@top.genblk1 - |vpiModule: - \_module: work@GOOD (work@top.genblk1.good1), file:${SURELOG_DIR}/tests/UnsizedElabComp/dut.sv, line:8:5, endln:8:18 + |vpiModuleInst: + \_module_inst: work@GOOD (work@top.genblk1.good1), file:${SURELOG_DIR}/tests/UnsizedElabComp/dut.sv, line:8:5, endln:8:18 |vpiParent: \_gen_scope: (work@top.genblk1) |vpiName:good1 @@ -477,7 +477,7 @@ design: (work@top) |vpiGenScopeArray: \_gen_scope_array: (work@top.genblk2), line:11:3, endln:13:6 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/UnsizedElabComp/dut.sv, line:4:1, endln:23:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/UnsizedElabComp/dut.sv, line:4:1, endln:23:10 |vpiName:genblk2 |vpiFullName:work@top.genblk2 |vpiGenScope: @@ -485,8 +485,8 @@ design: (work@top) |vpiParent: \_gen_scope_array: (work@top.genblk2), line:11:3, endln:13:6 |vpiFullName:work@top.genblk2 - |vpiModule: - \_module: work@GOOD (work@top.genblk2.good2), file:${SURELOG_DIR}/tests/UnsizedElabComp/dut.sv, line:12:5, endln:12:18 + |vpiModuleInst: + \_module_inst: work@GOOD (work@top.genblk2.good2), file:${SURELOG_DIR}/tests/UnsizedElabComp/dut.sv, line:12:5, endln:12:18 |vpiParent: \_gen_scope: (work@top.genblk2) |vpiName:good2 diff --git a/tests/UnsizedPacked/UnsizedPacked.log b/tests/UnsizedPacked/UnsizedPacked.log index 4f3ca56f48..52d3fa7aa5 100644 --- a/tests/UnsizedPacked/UnsizedPacked.log +++ b/tests/UnsizedPacked/UnsizedPacked.log @@ -68,7 +68,7 @@ constant 6 design 1 logic_net 4 logic_typespec 2 -module 2 +module_inst 2 range 3 === UHDM Object Stats End === [ERR:UH0719] ${SURELOG_DIR}/tests/UnsizedPacked/dut.sv:5:5: Illegal dynamic packed dimension "illegal". @@ -81,7 +81,7 @@ constant 6 design 1 logic_net 4 logic_typespec 2 -module 2 +module_inst 2 range 3 === UHDM Object Stats End === [INF:UH0708] Writing UHDM DB: ${SURELOG_DIR}/build/regression/UnsizedPacked/slpp_all/surelog.uhdm ... @@ -97,7 +97,7 @@ design: (work@test) |vpiElaborated:1 |vpiName:work@test |uhdmallModules: -\_module: work@test (work@test), file:${SURELOG_DIR}/tests/UnsizedPacked/dut.sv, line:1:1, endln:7:10 +\_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/UnsizedPacked/dut.sv, line:1:1, endln:7:10 |vpiParent: \_design: (work@test) |vpiFullName:work@test @@ -105,26 +105,26 @@ design: (work@test) |vpiNet: \_logic_net: (work@test.legal), line:3:5, endln:3:10 |vpiParent: - \_module: work@test (work@test), file:${SURELOG_DIR}/tests/UnsizedPacked/dut.sv, line:1:1, endln:7:10 + \_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/UnsizedPacked/dut.sv, line:1:1, endln:7:10 |vpiName:legal |vpiFullName:work@test.legal |vpiNetType:48 |vpiNet: \_logic_net: (work@test.illegal), line:5:8, endln:5:15 |vpiParent: - \_module: work@test (work@test), file:${SURELOG_DIR}/tests/UnsizedPacked/dut.sv, line:1:1, endln:7:10 + \_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/UnsizedPacked/dut.sv, line:1:1, endln:7:10 |vpiName:illegal |vpiFullName:work@test.illegal |vpiNetType:48 |uhdmtopModules: -\_module: work@test (work@test), file:${SURELOG_DIR}/tests/UnsizedPacked/dut.sv, line:1:1, endln:7:10 +\_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/UnsizedPacked/dut.sv, line:1:1, endln:7:10 |vpiName:work@test |vpiDefName:work@test |vpiTop:1 |vpiNet: \_logic_net: (work@test.illegal), line:5:8, endln:5:15 |vpiParent: - \_module: work@test (work@test), file:${SURELOG_DIR}/tests/UnsizedPacked/dut.sv, line:1:1, endln:7:10 + \_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/UnsizedPacked/dut.sv, line:1:1, endln:7:10 |vpiTypespec: \_logic_typespec: , line:5:1, endln:5:7 |vpiRange: @@ -150,7 +150,7 @@ design: (work@test) |vpiArrayNet: \_array_net: (work@test.legal), line:3:5, endln:3:10 |vpiParent: - \_module: work@test (work@test), file:${SURELOG_DIR}/tests/UnsizedPacked/dut.sv, line:1:1, endln:7:10 + \_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/UnsizedPacked/dut.sv, line:1:1, endln:7:10 |vpiSize:1 |vpiName:legal |vpiFullName:work@test.legal diff --git a/tests/UnsizedParam/UnsizedParam.log b/tests/UnsizedParam/UnsizedParam.log index f664e606a4..bdd5086565 100644 --- a/tests/UnsizedParam/UnsizedParam.log +++ b/tests/UnsizedParam/UnsizedParam.log @@ -169,7 +169,7 @@ design 1 int_typespec 8 logic_net 1 logic_typespec 6 -module 9 +module_inst 9 operation 10 packed_array_typespec 1 param_assign 6 @@ -186,7 +186,7 @@ design 1 int_typespec 8 logic_net 1 logic_typespec 6 -module 9 +module_inst 9 operation 12 packed_array_typespec 1 param_assign 6 @@ -207,14 +207,14 @@ design: (work@top) |vpiElaborated:1 |vpiName:work@top |uhdmallModules: -\_module: work@submodule (work@submodule), file:${SURELOG_DIR}/tests/UnsizedParam/dut.sv, line:1:1, endln:6:10 +\_module_inst: work@submodule (work@submodule), file:${SURELOG_DIR}/tests/UnsizedParam/dut.sv, line:1:1, endln:6:10 |vpiParent: \_design: (work@top) |vpiFullName:work@submodule |vpiParameter: \_parameter: (work@submodule.X), line:2:18, endln:2:19 |vpiParent: - \_module: work@submodule (work@submodule), file:${SURELOG_DIR}/tests/UnsizedParam/dut.sv, line:1:1, endln:6:10 + \_module_inst: work@submodule (work@submodule), file:${SURELOG_DIR}/tests/UnsizedParam/dut.sv, line:1:1, endln:6:10 |UINT:20 |vpiTypespec: \_int_typespec: , line:2:14, endln:2:17 @@ -227,7 +227,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@submodule.Y), line:4:24, endln:4:25 |vpiParent: - \_module: work@submodule (work@submodule), file:${SURELOG_DIR}/tests/UnsizedParam/dut.sv, line:1:1, endln:6:10 + \_module_inst: work@submodule (work@submodule), file:${SURELOG_DIR}/tests/UnsizedParam/dut.sv, line:1:1, endln:6:10 |BIN:1 |vpiTypespec: \_logic_typespec: (my_type_t), line:3:12, endln:3:25 @@ -237,10 +237,10 @@ design: (work@top) |vpiTypedefAlias: \_logic_typespec: (my_type_t), line:3:12, endln:3:25 |vpiParent: - \_module: work@submodule (work@submodule), file:${SURELOG_DIR}/tests/UnsizedParam/dut.sv, line:1:1, endln:6:10 + \_module_inst: work@submodule (work@submodule), file:${SURELOG_DIR}/tests/UnsizedParam/dut.sv, line:1:1, endln:6:10 |vpiName:my_type_t |vpiInstance: - \_module: work@submodule (work@submodule), file:${SURELOG_DIR}/tests/UnsizedParam/dut.sv, line:1:1, endln:6:10 + \_module_inst: work@submodule (work@submodule), file:${SURELOG_DIR}/tests/UnsizedParam/dut.sv, line:1:1, endln:6:10 |vpiRange: \_range: , line:3:18, endln:3:25 |vpiLeftRange: @@ -309,7 +309,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:2:18, endln:2:24 |vpiParent: - \_module: work@submodule (work@submodule), file:${SURELOG_DIR}/tests/UnsizedParam/dut.sv, line:1:1, endln:6:10 + \_module_inst: work@submodule (work@submodule), file:${SURELOG_DIR}/tests/UnsizedParam/dut.sv, line:1:1, endln:6:10 |vpiRhs: \_constant: , line:2:22, endln:2:24 |vpiDecompile:20 @@ -323,7 +323,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:4:24, endln:4:30 |vpiParent: - \_module: work@submodule (work@submodule), file:${SURELOG_DIR}/tests/UnsizedParam/dut.sv, line:1:1, endln:6:10 + \_module_inst: work@submodule (work@submodule), file:${SURELOG_DIR}/tests/UnsizedParam/dut.sv, line:1:1, endln:6:10 |vpiRhs: \_constant: , line:4:28, endln:4:30 |vpiDecompile:'1 @@ -340,7 +340,7 @@ design: (work@top) |vpiContAssign: \_cont_assign: , line:5:11, endln:5:22 |vpiParent: - \_module: work@submodule (work@submodule), file:${SURELOG_DIR}/tests/UnsizedParam/dut.sv, line:1:1, endln:6:10 + \_module_inst: work@submodule (work@submodule), file:${SURELOG_DIR}/tests/UnsizedParam/dut.sv, line:1:1, endln:6:10 |vpiRhs: \_operation: , line:5:15, endln:5:22 |vpiParent: @@ -364,27 +364,27 @@ design: (work@top) |vpiActual: \_logic_net: (a) |uhdmallModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/UnsizedParam/dut.sv, line:8:1, endln:11:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/UnsizedParam/dut.sv, line:8:1, endln:11:10 |vpiParent: \_design: (work@top) |vpiFullName:work@top |vpiDefName:work@top |uhdmtopModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/UnsizedParam/dut.sv, line:8:1, endln:11:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/UnsizedParam/dut.sv, line:8:1, endln:11:10 |vpiName:work@top |vpiDefName:work@top |vpiTop:1 |vpiTopModule:1 - |vpiModule: - \_module: work@submodule (work@top.u_sub_default), file:${SURELOG_DIR}/tests/UnsizedParam/dut.sv, line:9:4, endln:9:30 + |vpiModuleInst: + \_module_inst: work@submodule (work@top.u_sub_default), file:${SURELOG_DIR}/tests/UnsizedParam/dut.sv, line:9:4, endln:9:30 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/UnsizedParam/dut.sv, line:8:1, endln:11:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/UnsizedParam/dut.sv, line:8:1, endln:11:10 |vpiName:u_sub_default |vpiFullName:work@top.u_sub_default |vpiParameter: \_parameter: (work@top.u_sub_default.X), line:2:18, endln:2:19 |vpiParent: - \_module: work@submodule (work@top.u_sub_default), file:${SURELOG_DIR}/tests/UnsizedParam/dut.sv, line:9:4, endln:9:30 + \_module_inst: work@submodule (work@top.u_sub_default), file:${SURELOG_DIR}/tests/UnsizedParam/dut.sv, line:9:4, endln:9:30 |UINT:20 |vpiTypespec: \_int_typespec: , line:2:14, endln:2:17 @@ -397,7 +397,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.u_sub_default.Y), line:4:24, endln:4:25 |vpiParent: - \_module: work@submodule (work@top.u_sub_default), file:${SURELOG_DIR}/tests/UnsizedParam/dut.sv, line:9:4, endln:9:30 + \_module_inst: work@submodule (work@top.u_sub_default), file:${SURELOG_DIR}/tests/UnsizedParam/dut.sv, line:9:4, endln:9:30 |BIN:1 |vpiTypespec: \_logic_typespec: (my_type_t), line:3:12, endln:3:25 @@ -410,7 +410,7 @@ design: (work@top) \_logic_typespec: (my_type_t), line:3:12, endln:3:25 |vpiName:my_type_t |vpiInstance: - \_module: work@submodule (work@submodule), file:${SURELOG_DIR}/tests/UnsizedParam/dut.sv, line:1:1, endln:6:10 + \_module_inst: work@submodule (work@submodule), file:${SURELOG_DIR}/tests/UnsizedParam/dut.sv, line:1:1, endln:6:10 |vpiRange: \_range: , line:3:18, endln:3:25 |vpiParent: @@ -482,7 +482,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:2:18, endln:2:24 |vpiParent: - \_module: work@submodule (work@top.u_sub_default), file:${SURELOG_DIR}/tests/UnsizedParam/dut.sv, line:9:4, endln:9:30 + \_module_inst: work@submodule (work@top.u_sub_default), file:${SURELOG_DIR}/tests/UnsizedParam/dut.sv, line:9:4, endln:9:30 |vpiRhs: \_constant: , line:2:22, endln:2:24 |vpiDecompile:20 @@ -496,7 +496,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:4:24, endln:4:30 |vpiParent: - \_module: work@submodule (work@top.u_sub_default), file:${SURELOG_DIR}/tests/UnsizedParam/dut.sv, line:9:4, endln:9:30 + \_module_inst: work@submodule (work@top.u_sub_default), file:${SURELOG_DIR}/tests/UnsizedParam/dut.sv, line:9:4, endln:9:30 |vpiRhs: \_constant: , line:4:28, endln:4:30 |vpiDecompile:1048575 @@ -517,11 +517,11 @@ design: (work@top) |vpiName:a |vpiNetType:1 |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/UnsizedParam/dut.sv, line:8:1, endln:11:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/UnsizedParam/dut.sv, line:8:1, endln:11:10 |vpiContAssign: \_cont_assign: , line:5:11, endln:5:22 |vpiParent: - \_module: work@submodule (work@top.u_sub_default), file:${SURELOG_DIR}/tests/UnsizedParam/dut.sv, line:9:4, endln:9:30 + \_module_inst: work@submodule (work@top.u_sub_default), file:${SURELOG_DIR}/tests/UnsizedParam/dut.sv, line:9:4, endln:9:30 |vpiRhs: \_operation: , line:5:15, endln:5:22 |vpiParent: @@ -548,16 +548,16 @@ design: (work@top) |vpiFullName:work@top.u_sub_default.a |vpiActual: \_logic_net: (a) - |vpiModule: - \_module: work@submodule (work@top.u_sub_5), file:${SURELOG_DIR}/tests/UnsizedParam/dut.sv, line:10:4, endln:10:33 + |vpiModuleInst: + \_module_inst: work@submodule (work@top.u_sub_5), file:${SURELOG_DIR}/tests/UnsizedParam/dut.sv, line:10:4, endln:10:33 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/UnsizedParam/dut.sv, line:8:1, endln:11:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/UnsizedParam/dut.sv, line:8:1, endln:11:10 |vpiName:u_sub_5 |vpiFullName:work@top.u_sub_5 |vpiParameter: \_parameter: (work@top.u_sub_5.X), line:2:18, endln:2:19 |vpiParent: - \_module: work@submodule (work@top.u_sub_5), file:${SURELOG_DIR}/tests/UnsizedParam/dut.sv, line:10:4, endln:10:33 + \_module_inst: work@submodule (work@top.u_sub_5), file:${SURELOG_DIR}/tests/UnsizedParam/dut.sv, line:10:4, endln:10:33 |UINT:20 |vpiTypespec: \_int_typespec: , line:2:14, endln:2:17 @@ -570,7 +570,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.u_sub_5.Y), line:4:24, endln:4:25 |vpiParent: - \_module: work@submodule (work@top.u_sub_5), file:${SURELOG_DIR}/tests/UnsizedParam/dut.sv, line:10:4, endln:10:33 + \_module_inst: work@submodule (work@top.u_sub_5), file:${SURELOG_DIR}/tests/UnsizedParam/dut.sv, line:10:4, endln:10:33 |BIN:1 |vpiTypespec: \_logic_typespec: (my_type_t), line:3:12, endln:3:25 @@ -583,7 +583,7 @@ design: (work@top) \_logic_typespec: (my_type_t), line:3:12, endln:3:25 |vpiName:my_type_t |vpiInstance: - \_module: work@submodule (work@submodule), file:${SURELOG_DIR}/tests/UnsizedParam/dut.sv, line:1:1, endln:6:10 + \_module_inst: work@submodule (work@submodule), file:${SURELOG_DIR}/tests/UnsizedParam/dut.sv, line:1:1, endln:6:10 |vpiRange: \_range: , line:3:18, endln:3:25 |vpiParent: @@ -655,7 +655,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:2:18, endln:2:24 |vpiParent: - \_module: work@submodule (work@top.u_sub_5), file:${SURELOG_DIR}/tests/UnsizedParam/dut.sv, line:10:4, endln:10:33 + \_module_inst: work@submodule (work@top.u_sub_5), file:${SURELOG_DIR}/tests/UnsizedParam/dut.sv, line:10:4, endln:10:33 |vpiOverriden:1 |vpiRhs: \_constant: , line:2:22, endln:2:24 @@ -670,7 +670,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:4:24, endln:4:30 |vpiParent: - \_module: work@submodule (work@top.u_sub_5), file:${SURELOG_DIR}/tests/UnsizedParam/dut.sv, line:10:4, endln:10:33 + \_module_inst: work@submodule (work@top.u_sub_5), file:${SURELOG_DIR}/tests/UnsizedParam/dut.sv, line:10:4, endln:10:33 |vpiOverriden:1 |vpiRhs: \_constant: , line:4:28, endln:4:30 @@ -688,11 +688,11 @@ design: (work@top) |vpiDefFile:${SURELOG_DIR}/tests/UnsizedParam/dut.sv |vpiDefLineNo:1 |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/UnsizedParam/dut.sv, line:8:1, endln:11:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/UnsizedParam/dut.sv, line:8:1, endln:11:10 |vpiContAssign: \_cont_assign: , line:5:11, endln:5:22 |vpiParent: - \_module: work@submodule (work@top.u_sub_5), file:${SURELOG_DIR}/tests/UnsizedParam/dut.sv, line:10:4, endln:10:33 + \_module_inst: work@submodule (work@top.u_sub_5), file:${SURELOG_DIR}/tests/UnsizedParam/dut.sv, line:10:4, endln:10:33 |vpiRhs: \_operation: , line:5:15, endln:5:22 |vpiParent: diff --git a/tests/Value4States/Value4States.log b/tests/Value4States/Value4States.log index c5286fb9ec..e817ae4537 100644 --- a/tests/Value4States/Value4States.log +++ b/tests/Value4States/Value4States.log @@ -95,7 +95,7 @@ n<> u<68> t c<1> l<1:1> el<6:1> constant 14 design 1 logic_typespec 4 -module 5 +module_inst 5 param_assign 4 parameter 4 range 4 @@ -106,7 +106,7 @@ range 4 constant 14 design 1 logic_typespec 4 -module 5 +module_inst 5 param_assign 4 parameter 4 range 4 @@ -124,14 +124,14 @@ design: (work@top) |vpiElaborated:1 |vpiName:work@top |uhdmallModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/Value4States/dut.sv, line:1:1, endln:4:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/Value4States/dut.sv, line:1:1, endln:4:10 |vpiParent: \_design: (work@top) |vpiFullName:work@top |vpiParameter: \_parameter: (work@top.P1), line:2:27, endln:2:29 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/Value4States/dut.sv, line:1:1, endln:4:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/Value4States/dut.sv, line:1:1, endln:4:10 |BIN:X |vpiTypespec: \_logic_typespec: , line:2:14, endln:2:26 @@ -160,7 +160,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.P2), line:3:27, endln:3:29 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/Value4States/dut.sv, line:1:1, endln:4:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/Value4States/dut.sv, line:1:1, endln:4:10 |BIN:Z |vpiTypespec: \_logic_typespec: , line:3:14, endln:3:26 @@ -189,7 +189,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:2:27, endln:2:34 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/Value4States/dut.sv, line:1:1, endln:4:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/Value4States/dut.sv, line:1:1, endln:4:10 |vpiRhs: \_constant: , line:2:32, endln:2:34 |vpiDecompile:'X @@ -203,7 +203,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:3:27, endln:3:34 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/Value4States/dut.sv, line:1:1, endln:4:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/Value4States/dut.sv, line:1:1, endln:4:10 |vpiRhs: \_constant: , line:3:32, endln:3:34 |vpiDecompile:'Z @@ -216,12 +216,12 @@ design: (work@top) \_parameter: (work@top.P2), line:3:27, endln:3:29 |vpiDefName:work@top |uhdmtopModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/Value4States/dut.sv, line:1:1, endln:4:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/Value4States/dut.sv, line:1:1, endln:4:10 |vpiName:work@top |vpiParameter: \_parameter: (work@top.P1), line:2:27, endln:2:29 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/Value4States/dut.sv, line:1:1, endln:4:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/Value4States/dut.sv, line:1:1, endln:4:10 |BIN:X |vpiTypespec: \_logic_typespec: , line:2:14, endln:2:26 @@ -252,7 +252,7 @@ design: (work@top) |vpiParameter: \_parameter: (work@top.P2), line:3:27, endln:3:29 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/Value4States/dut.sv, line:1:1, endln:4:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/Value4States/dut.sv, line:1:1, endln:4:10 |BIN:Z |vpiTypespec: \_logic_typespec: , line:3:14, endln:3:26 @@ -283,7 +283,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:2:27, endln:2:34 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/Value4States/dut.sv, line:1:1, endln:4:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/Value4States/dut.sv, line:1:1, endln:4:10 |vpiRhs: \_constant: , line:2:32, endln:2:34 |vpiDecompile:32'bX @@ -297,7 +297,7 @@ design: (work@top) |vpiParamAssign: \_param_assign: , line:3:27, endln:3:34 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/Value4States/dut.sv, line:1:1, endln:4:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/Value4States/dut.sv, line:1:1, endln:4:10 |vpiRhs: \_constant: , line:3:32, endln:3:34 |vpiDecompile:32'bZ diff --git a/tests/ValueSize/ValueSize.log b/tests/ValueSize/ValueSize.log index 16a7d9708c..5f609b6ccb 100644 --- a/tests/ValueSize/ValueSize.log +++ b/tests/ValueSize/ValueSize.log @@ -29,7 +29,7 @@ bit_typespec 10 constant 52 design 1 logic_typespec 4 -module 2 +module_inst 2 operation 12 package 3 param_assign 8 @@ -47,7 +47,7 @@ bit_typespec 10 constant 52 design 1 logic_typespec 4 -module 2 +module_inst 2 operation 12 package 3 param_assign 8 diff --git a/tests/Values/Values.log b/tests/Values/Values.log index c01f64468d..b1bfd2c5f2 100644 --- a/tests/Values/Values.log +++ b/tests/Values/Values.log @@ -442,7 +442,7 @@ io_decl 11 logic_net 5 logic_typespec 5 logic_var 6 -module 3 +module_inst 3 package 2 range 10 task 9 @@ -465,7 +465,7 @@ io_decl 22 logic_net 5 logic_typespec 5 logic_var 6 -module 3 +module_inst 3 package 2 range 10 task 18 @@ -958,7 +958,7 @@ design: (work@top) \_int_typespec: |vpiSigned:1 |uhdmallModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/Values/dut.sv, line:1:1, endln:7:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/Values/dut.sv, line:1:1, endln:7:10 |vpiParent: \_design: (work@top) |vpiFullName:work@top @@ -966,45 +966,45 @@ design: (work@top) |vpiNet: \_logic_net: (work@top.first), line:2:15, endln:2:20 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/Values/dut.sv, line:1:1, endln:7:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/Values/dut.sv, line:1:1, endln:7:10 |vpiName:first |vpiFullName:work@top.first |vpiNetType:36 |vpiNet: \_logic_net: (work@top.second), line:3:15, endln:3:21 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/Values/dut.sv, line:1:1, endln:7:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/Values/dut.sv, line:1:1, endln:7:10 |vpiName:second |vpiFullName:work@top.second |vpiNetType:36 |vpiNet: \_logic_net: (work@top.third), line:4:15, endln:4:20 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/Values/dut.sv, line:1:1, endln:7:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/Values/dut.sv, line:1:1, endln:7:10 |vpiName:third |vpiFullName:work@top.third |vpiNetType:36 |vpiNet: \_logic_net: (work@top.forth), line:5:15, endln:5:20 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/Values/dut.sv, line:1:1, endln:7:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/Values/dut.sv, line:1:1, endln:7:10 |vpiName:forth |vpiFullName:work@top.forth |vpiNetType:36 |vpiNet: \_logic_net: (work@top.fifth), line:6:15, endln:6:20 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/Values/dut.sv, line:1:1, endln:7:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/Values/dut.sv, line:1:1, endln:7:10 |vpiName:fifth |vpiFullName:work@top.fifth |vpiNetType:36 |uhdmtopModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/Values/dut.sv, line:1:1, endln:7:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/Values/dut.sv, line:1:1, endln:7:10 |vpiName:work@top |vpiVariables: \_logic_var: (work@top.first), line:2:15, endln:2:29 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/Values/dut.sv, line:1:1, endln:7:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/Values/dut.sv, line:1:1, endln:7:10 |vpiTypespec: \_logic_typespec: , line:2:2, endln:2:14 |vpiRange: @@ -1055,7 +1055,7 @@ design: (work@top) |vpiVariables: \_logic_var: (work@top.second), line:3:15, endln:3:30 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/Values/dut.sv, line:1:1, endln:7:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/Values/dut.sv, line:1:1, endln:7:10 |vpiTypespec: \_logic_typespec: , line:3:2, endln:3:14 |vpiRange: @@ -1106,7 +1106,7 @@ design: (work@top) |vpiVariables: \_logic_var: (work@top.third), line:4:15, endln:4:29 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/Values/dut.sv, line:1:1, endln:7:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/Values/dut.sv, line:1:1, endln:7:10 |vpiTypespec: \_logic_typespec: , line:4:2, endln:4:14 |vpiRange: @@ -1157,7 +1157,7 @@ design: (work@top) |vpiVariables: \_logic_var: (work@top.forth), line:5:15, endln:5:29 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/Values/dut.sv, line:1:1, endln:7:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/Values/dut.sv, line:1:1, endln:7:10 |vpiTypespec: \_logic_typespec: , line:5:2, endln:5:14 |vpiRange: @@ -1208,7 +1208,7 @@ design: (work@top) |vpiVariables: \_logic_var: (work@top.fifth), line:6:15, endln:6:25 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/Values/dut.sv, line:1:1, endln:7:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/Values/dut.sv, line:1:1, endln:7:10 |vpiTypespec: \_logic_typespec: , line:6:2, endln:6:14 |vpiRange: diff --git a/tests/VarDecl/VarDecl.log b/tests/VarDecl/VarDecl.log index 642670c9dd..73062548e3 100644 --- a/tests/VarDecl/VarDecl.log +++ b/tests/VarDecl/VarDecl.log @@ -114,7 +114,7 @@ int_var 2 logic_net 2 logic_typespec 4 logic_var 1 -module 2 +module_inst 2 operation 2 port 2 ref_obj 4 @@ -133,7 +133,7 @@ int_var 4 logic_net 2 logic_typespec 4 logic_var 1 -module 2 +module_inst 2 operation 4 port 3 ref_obj 7 @@ -151,7 +151,7 @@ design: (work@top) |vpiElaborated:1 |vpiName:work@top |uhdmallModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/VarDecl/dut.sv, line:1:1, endln:7:16 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/VarDecl/dut.sv, line:1:1, endln:7:16 |vpiParent: \_design: (work@top) |vpiFullName:work@top @@ -159,7 +159,7 @@ design: (work@top) |vpiTaskFunc: \_function: (work@top.theta), line:2:4, endln:6:23 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/VarDecl/dut.sv, line:1:1, endln:7:16 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/VarDecl/dut.sv, line:1:1, endln:7:16 |vpiName:theta |vpiFullName:work@top.theta |vpiVisibility:1 @@ -169,7 +169,7 @@ design: (work@top) |vpiTypespec: \_logic_typespec: , line:2:23, endln:2:28 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/VarDecl/dut.sv, line:1:1, endln:7:16 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/VarDecl/dut.sv, line:1:1, endln:7:16 |vpiStmt: \_for_stmt: (work@top.theta), line:3:7, endln:3:10 |vpiParent: @@ -247,18 +247,18 @@ design: (work@top) |vpiFullName:work@top.theta.a |vpiSigned:1 |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/VarDecl/dut.sv, line:1:1, endln:7:16 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/VarDecl/dut.sv, line:1:1, endln:7:16 |vpiNet: \_logic_net: (work@top.o), line:1:25, endln:1:26 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/VarDecl/dut.sv, line:1:1, endln:7:16 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/VarDecl/dut.sv, line:1:1, endln:7:16 |vpiName:o |vpiFullName:work@top.o |vpiNetType:36 |vpiPort: \_port: (o), line:1:25, endln:1:26 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/VarDecl/dut.sv, line:1:1, endln:7:16 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/VarDecl/dut.sv, line:1:1, endln:7:16 |vpiName:o |vpiDirection:2 |vpiLowConn: @@ -268,14 +268,14 @@ design: (work@top) |vpiTypedef: \_logic_typespec: , line:1:19, endln:1:24 |uhdmtopModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/VarDecl/dut.sv, line:1:1, endln:7:16 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/VarDecl/dut.sv, line:1:1, endln:7:16 |vpiName:work@top |vpiDefName:work@top |vpiTop:1 |vpiTaskFunc: \_function: (work@top.theta), line:2:4, endln:6:23 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/VarDecl/dut.sv, line:1:1, endln:7:16 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/VarDecl/dut.sv, line:1:1, endln:7:16 |vpiName:theta |vpiFullName:work@top.theta |vpiVisibility:1 @@ -283,7 +283,7 @@ design: (work@top) |vpiReturn: \_logic_var: , line:2:23, endln:2:28 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/VarDecl/dut.sv, line:1:1, endln:7:16 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/VarDecl/dut.sv, line:1:1, endln:7:16 |vpiStmt: \_for_stmt: (work@top.theta), line:3:7, endln:3:10 |vpiParent: @@ -347,11 +347,11 @@ design: (work@top) |vpiFullName:work@top.theta.a |vpiSigned:1 |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/VarDecl/dut.sv, line:1:1, endln:7:16 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/VarDecl/dut.sv, line:1:1, endln:7:16 |vpiNet: \_logic_net: (work@top.o), line:1:25, endln:1:26 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/VarDecl/dut.sv, line:1:1, endln:7:16 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/VarDecl/dut.sv, line:1:1, endln:7:16 |vpiTypespec: \_logic_typespec: , line:1:19, endln:1:24 |vpiName:o @@ -361,7 +361,7 @@ design: (work@top) |vpiPort: \_port: (o), line:1:25, endln:1:26 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/VarDecl/dut.sv, line:1:1, endln:7:16 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/VarDecl/dut.sv, line:1:1, endln:7:16 |vpiName:o |vpiDirection:2 |vpiLowConn: @@ -375,7 +375,7 @@ design: (work@top) |vpiTypedef: \_logic_typespec: , line:1:19, endln:1:24 |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/VarDecl/dut.sv, line:1:1, endln:7:16 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/VarDecl/dut.sv, line:1:1, endln:7:16 =================== [ FATAL] : 0 [ SYNTAX] : 0 diff --git a/tests/VarDecl2/VarDecl2.log b/tests/VarDecl2/VarDecl2.log index dda511eb45..8225a59baf 100644 --- a/tests/VarDecl2/VarDecl2.log +++ b/tests/VarDecl2/VarDecl2.log @@ -132,7 +132,7 @@ function 1 int_typespec 7 int_var 5 logic_net 1 -module 2 +module_inst 2 operation 2 port 2 ref_obj 4 @@ -150,7 +150,7 @@ function 2 int_typespec 7 int_var 8 logic_net 1 -module 2 +module_inst 2 operation 4 port 3 ref_obj 7 @@ -169,7 +169,7 @@ design: (work@top) |vpiElaborated:1 |vpiName:work@top |uhdmallModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/VarDecl2/dut.sv, line:1:1, endln:11:16 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/VarDecl2/dut.sv, line:1:1, endln:11:16 |vpiParent: \_design: (work@top) |vpiFullName:work@top @@ -177,7 +177,7 @@ design: (work@top) |vpiTaskFunc: \_function: (work@top.theta), line:2:4, endln:9:23 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/VarDecl2/dut.sv, line:1:1, endln:11:16 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/VarDecl2/dut.sv, line:1:1, endln:11:16 |vpiName:theta |vpiFullName:work@top.theta |vpiVisibility:1 @@ -189,7 +189,7 @@ design: (work@top) |vpiSigned:1 |vpiSigned:1 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/VarDecl2/dut.sv, line:1:1, endln:11:16 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/VarDecl2/dut.sv, line:1:1, endln:11:16 |vpiStmt: \_begin: (work@top.theta) |vpiParent: @@ -306,17 +306,17 @@ design: (work@top) |UINT:0 |vpiConstType:9 |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/VarDecl2/dut.sv, line:1:1, endln:11:16 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/VarDecl2/dut.sv, line:1:1, endln:11:16 |vpiNet: \_logic_net: (work@top.o), line:1:23, endln:1:24 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/VarDecl2/dut.sv, line:1:1, endln:11:16 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/VarDecl2/dut.sv, line:1:1, endln:11:16 |vpiName:o |vpiFullName:work@top.o |vpiPort: \_port: (o), line:1:23, endln:1:24 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/VarDecl2/dut.sv, line:1:1, endln:11:16 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/VarDecl2/dut.sv, line:1:1, endln:11:16 |vpiName:o |vpiDirection:2 |vpiLowConn: @@ -327,12 +327,12 @@ design: (work@top) \_int_typespec: , line:1:19, endln:1:22 |vpiSigned:1 |uhdmtopModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/VarDecl2/dut.sv, line:1:1, endln:11:16 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/VarDecl2/dut.sv, line:1:1, endln:11:16 |vpiName:work@top |vpiVariables: \_int_var: (work@top.o), line:1:23, endln:1:24 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/VarDecl2/dut.sv, line:1:1, endln:11:16 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/VarDecl2/dut.sv, line:1:1, endln:11:16 |vpiTypespec: \_int_typespec: , line:1:19, endln:1:22 |vpiSigned:1 @@ -345,7 +345,7 @@ design: (work@top) |vpiTaskFunc: \_function: (work@top.theta), line:2:4, endln:9:23 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/VarDecl2/dut.sv, line:1:1, endln:11:16 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/VarDecl2/dut.sv, line:1:1, endln:11:16 |vpiName:theta |vpiFullName:work@top.theta |vpiVisibility:1 @@ -353,7 +353,7 @@ design: (work@top) |vpiReturn: \_int_var: , line:2:23, endln:2:26 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/VarDecl2/dut.sv, line:1:1, endln:11:16 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/VarDecl2/dut.sv, line:1:1, endln:11:16 |vpiStmt: \_begin: (work@top.theta) |vpiParent: @@ -443,12 +443,12 @@ design: (work@top) |vpiCondition: \_constant: , line:8:14, endln:8:15 |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/VarDecl2/dut.sv, line:1:1, endln:11:16 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/VarDecl2/dut.sv, line:1:1, endln:11:16 |vpiTopModule:1 |vpiPort: \_port: (o), line:1:23, endln:1:24 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/VarDecl2/dut.sv, line:1:1, endln:11:16 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/VarDecl2/dut.sv, line:1:1, endln:11:16 |vpiName:o |vpiDirection:2 |vpiLowConn: @@ -463,7 +463,7 @@ design: (work@top) \_int_typespec: , line:1:19, endln:1:22 |vpiSigned:1 |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/VarDecl2/dut.sv, line:1:1, endln:11:16 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/VarDecl2/dut.sv, line:1:1, endln:11:16 =================== [ FATAL] : 0 [ SYNTAX] : 0 diff --git a/tests/VarInFunc/VarInFunc.log b/tests/VarInFunc/VarInFunc.log index 82bb44c064..d688faa72d 100644 --- a/tests/VarInFunc/VarInFunc.log +++ b/tests/VarInFunc/VarInFunc.log @@ -417,7 +417,7 @@ io_decl 11 logic_net 4 logic_typespec 8 logic_var 3 -module 5 +module_inst 5 package 2 param_assign 2 parameter 2 @@ -449,7 +449,7 @@ io_decl 22 logic_net 4 logic_typespec 8 logic_var 5 -module 5 +module_inst 5 package 2 param_assign 2 parameter 2 @@ -947,7 +947,7 @@ design: (work@top) \_int_typespec: |vpiSigned:1 |uhdmallModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/VarInFunc/dut.sv, line:1:1, endln:9:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/VarInFunc/dut.sv, line:1:1, endln:9:10 |vpiParent: \_design: (work@top) |vpiFullName:work@top @@ -955,7 +955,7 @@ design: (work@top) |vpiTaskFunc: \_function: (work@top.compute_next_state), line:2:3, endln:6:35 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/VarInFunc/dut.sv, line:1:1, endln:9:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/VarInFunc/dut.sv, line:1:1, endln:9:10 |vpiName:compute_next_state |vpiFullName:work@top.compute_next_state |vpiVariables: @@ -1011,7 +1011,7 @@ design: (work@top) |UINT:0 |vpiConstType:9 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/VarInFunc/dut.sv, line:1:1, endln:9:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/VarInFunc/dut.sv, line:1:1, endln:9:10 |vpiStmt: \_begin: (work@top.compute_next_state) |vpiParent: @@ -1052,23 +1052,23 @@ design: (work@top) |vpiActual: \_logic_var: (work@top.compute_next_state.function_variable), line:3:17, endln:3:34 |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/VarInFunc/dut.sv, line:1:1, endln:9:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/VarInFunc/dut.sv, line:1:1, endln:9:10 |vpiNet: \_logic_net: (work@top.a), line:1:18, endln:1:19 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/VarInFunc/dut.sv, line:1:1, endln:9:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/VarInFunc/dut.sv, line:1:1, endln:9:10 |vpiName:a |vpiFullName:work@top.a |vpiNet: \_logic_net: (work@top.b), line:1:34, endln:1:35 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/VarInFunc/dut.sv, line:1:1, endln:9:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/VarInFunc/dut.sv, line:1:1, endln:9:10 |vpiName:b |vpiFullName:work@top.b |vpiPort: \_port: (a), line:1:18, endln:1:19 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/VarInFunc/dut.sv, line:1:1, endln:9:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/VarInFunc/dut.sv, line:1:1, endln:9:10 |vpiName:a |vpiDirection:1 |vpiLowConn: @@ -1080,7 +1080,7 @@ design: (work@top) |vpiPort: \_port: (b), line:1:34, endln:1:35 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/VarInFunc/dut.sv, line:1:1, endln:9:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/VarInFunc/dut.sv, line:1:1, endln:9:10 |vpiName:b |vpiDirection:2 |vpiLowConn: @@ -1110,7 +1110,7 @@ design: (work@top) |vpiContAssign: \_cont_assign: , line:7:10, endln:7:34 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/VarInFunc/dut.sv, line:1:1, endln:9:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/VarInFunc/dut.sv, line:1:1, endln:9:10 |vpiRhs: \_func_call: (compute_next_state), line:7:14, endln:7:34 |vpiParent: @@ -1127,14 +1127,14 @@ design: (work@top) |vpiActual: \_logic_net: (work@top.b), line:1:34, endln:1:35 |uhdmtopModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/VarInFunc/dut.sv, line:1:1, endln:9:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/VarInFunc/dut.sv, line:1:1, endln:9:10 |vpiName:work@top |vpiDefName:work@top |vpiTop:1 |vpiTaskFunc: \_function: (work@top.compute_next_state), line:2:3, endln:6:35 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/VarInFunc/dut.sv, line:1:1, endln:9:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/VarInFunc/dut.sv, line:1:1, endln:9:10 |vpiName:compute_next_state |vpiFullName:work@top.compute_next_state |vpiVariables: @@ -1150,7 +1150,7 @@ design: (work@top) |vpiReturn: \_logic_var: , line:2:22, endln:2:33 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/VarInFunc/dut.sv, line:1:1, endln:9:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/VarInFunc/dut.sv, line:1:1, endln:9:10 |vpiStmt: \_begin: (work@top.compute_next_state) |vpiParent: @@ -1191,11 +1191,11 @@ design: (work@top) |vpiActual: \_logic_var: (work@top.compute_next_state.function_variable), line:3:17, endln:3:34 |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/VarInFunc/dut.sv, line:1:1, endln:9:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/VarInFunc/dut.sv, line:1:1, endln:9:10 |vpiNet: \_logic_net: (work@top.a), line:1:18, endln:1:19 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/VarInFunc/dut.sv, line:1:1, endln:9:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/VarInFunc/dut.sv, line:1:1, endln:9:10 |vpiTypespec: \_logic_typespec: , line:1:18, endln:1:18 |vpiName:a @@ -1203,7 +1203,7 @@ design: (work@top) |vpiNet: \_logic_net: (work@top.b), line:1:34, endln:1:35 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/VarInFunc/dut.sv, line:1:1, endln:9:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/VarInFunc/dut.sv, line:1:1, endln:9:10 |vpiTypespec: \_logic_typespec: , line:1:28, endln:1:33 |vpiRange: @@ -1230,7 +1230,7 @@ design: (work@top) |vpiPort: \_port: (a), line:1:18, endln:1:19 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/VarInFunc/dut.sv, line:1:1, endln:9:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/VarInFunc/dut.sv, line:1:1, endln:9:10 |vpiName:a |vpiDirection:1 |vpiLowConn: @@ -1244,11 +1244,11 @@ design: (work@top) |vpiTypedef: \_logic_typespec: , line:1:18, endln:1:18 |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/VarInFunc/dut.sv, line:1:1, endln:9:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/VarInFunc/dut.sv, line:1:1, endln:9:10 |vpiPort: \_port: (b), line:1:34, endln:1:35 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/VarInFunc/dut.sv, line:1:1, endln:9:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/VarInFunc/dut.sv, line:1:1, endln:9:10 |vpiName:b |vpiDirection:2 |vpiLowConn: @@ -1282,11 +1282,11 @@ design: (work@top) |UINT:0 |vpiConstType:9 |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/VarInFunc/dut.sv, line:1:1, endln:9:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/VarInFunc/dut.sv, line:1:1, endln:9:10 |vpiContAssign: \_cont_assign: , line:7:10, endln:7:34 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/VarInFunc/dut.sv, line:1:1, endln:9:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/VarInFunc/dut.sv, line:1:1, endln:9:10 |vpiRhs: \_constant: , line:4:32, endln:4:36 |vpiLhs: diff --git a/tests/VarRangeTypedef/VarRangeTypedef.log b/tests/VarRangeTypedef/VarRangeTypedef.log index 4a40ef17f7..447f4e412f 100644 --- a/tests/VarRangeTypedef/VarRangeTypedef.log +++ b/tests/VarRangeTypedef/VarRangeTypedef.log @@ -68,7 +68,7 @@ array_typespec 2 constant 4 design 1 logic_typespec 3 -module 1 +module_inst 1 package 3 range 2 struct_typespec 3 @@ -81,7 +81,7 @@ array_typespec 2 constant 4 design 1 logic_typespec 3 -module 1 +module_inst 1 package 3 range 2 struct_typespec 3 diff --git a/tests/VarSelect/VarSelect.log b/tests/VarSelect/VarSelect.log index 56d94a2170..1b957e6b5a 100644 --- a/tests/VarSelect/VarSelect.log +++ b/tests/VarSelect/VarSelect.log @@ -467,7 +467,7 @@ io_decl 11 logic_net 1 logic_typespec 1 logic_var 2 -module 4 +module_inst 4 operation 2 package 2 range 4 @@ -500,7 +500,7 @@ io_decl 22 logic_net 1 logic_typespec 1 logic_var 2 -module 4 +module_inst 4 operation 4 package 2 range 4 @@ -996,7 +996,7 @@ design: (work@top) \_int_typespec: |vpiSigned:1 |uhdmallModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/VarSelect/dut.sv, line:3:1, endln:14:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/VarSelect/dut.sv, line:3:1, endln:14:10 |vpiParent: \_design: (work@top) |vpiFullName:work@top @@ -1004,14 +1004,14 @@ design: (work@top) |vpiNet: \_logic_net: (work@top.test_net), line:6:22, endln:6:30 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/VarSelect/dut.sv, line:3:1, endln:14:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/VarSelect/dut.sv, line:3:1, endln:14:10 |vpiName:test_net |vpiFullName:work@top.test_net |vpiNetType:36 |vpiProcess: \_initial: , line:7:2, endln:12:5 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/VarSelect/dut.sv, line:3:1, endln:14:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/VarSelect/dut.sv, line:3:1, endln:14:10 |vpiStmt: \_begin: (work@top), line:7:10, endln:12:5 |vpiParent: @@ -1154,7 +1154,7 @@ design: (work@top) |vpiContAssign: \_cont_assign: , line:4:9, endln:4:23 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/VarSelect/dut.sv, line:3:1, endln:14:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/VarSelect/dut.sv, line:3:1, endln:14:10 |vpiRhs: \_constant: , line:4:19, endln:4:23 |vpiParent: @@ -1186,12 +1186,12 @@ design: (work@top) |UINT:0 |vpiConstType:9 |uhdmtopModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/VarSelect/dut.sv, line:3:1, endln:14:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/VarSelect/dut.sv, line:3:1, endln:14:10 |vpiName:work@top |vpiVariables: \_logic_var: (work@top.test_net), line:6:22, endln:6:30 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/VarSelect/dut.sv, line:3:1, endln:14:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/VarSelect/dut.sv, line:3:1, endln:14:10 |vpiTypespec: \_logic_typespec: , line:6:2, endln:6:21 |vpiRange: @@ -1275,7 +1275,7 @@ design: (work@top) |vpiProcess: \_initial: , line:7:2, endln:12:5 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/VarSelect/dut.sv, line:3:1, endln:14:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/VarSelect/dut.sv, line:3:1, endln:14:10 |vpiStmt: \_begin: (work@top), line:7:10, endln:12:5 |vpiParent: @@ -1403,7 +1403,7 @@ design: (work@top) |vpiContAssign: \_cont_assign: , line:4:9, endln:4:23 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/VarSelect/dut.sv, line:3:1, endln:14:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/VarSelect/dut.sv, line:3:1, endln:14:10 |vpiRhs: \_constant: , line:4:19, endln:4:23 |vpiLhs: diff --git a/tests/VarSelectGenStmt/VarSelectGenStmt.log b/tests/VarSelectGenStmt/VarSelectGenStmt.log index ff4a3e7811..558c41c7bd 100644 --- a/tests/VarSelectGenStmt/VarSelectGenStmt.log +++ b/tests/VarSelectGenStmt/VarSelectGenStmt.log @@ -220,7 +220,7 @@ gen_scope_array 12 int_typespec 6 logic_net 7 logic_typespec 12 -module 13 +module_inst 13 operation 9 parameter 6 port 7 @@ -238,7 +238,7 @@ gen_scope_array 18 int_typespec 6 logic_net 7 logic_typespec 12 -module 17 +module_inst 17 operation 9 parameter 6 port 20 @@ -259,7 +259,7 @@ design: (work@aes_sub_bytes) |vpiElaborated:1 |vpiName:work@aes_sub_bytes |uhdmallModules: -\_module: work@aes_sbox (work@aes_sbox), file:${SURELOG_DIR}/tests/VarSelectGenStmt/dut.sv, line:1:1, endln:6:10 +\_module_inst: work@aes_sbox (work@aes_sbox), file:${SURELOG_DIR}/tests/VarSelectGenStmt/dut.sv, line:1:1, endln:6:10 |vpiParent: \_design: (work@aes_sub_bytes) |vpiFullName:work@aes_sbox @@ -267,14 +267,14 @@ design: (work@aes_sub_bytes) |vpiNet: \_logic_net: (work@aes_sbox.data_i), line:3:32, endln:3:38 |vpiParent: - \_module: work@aes_sbox (work@aes_sbox), file:${SURELOG_DIR}/tests/VarSelectGenStmt/dut.sv, line:1:1, endln:6:10 + \_module_inst: work@aes_sbox (work@aes_sbox), file:${SURELOG_DIR}/tests/VarSelectGenStmt/dut.sv, line:1:1, endln:6:10 |vpiName:data_i |vpiFullName:work@aes_sbox.data_i |vpiNetType:36 |vpiPort: \_port: (data_i), line:3:32, endln:3:38 |vpiParent: - \_module: work@aes_sbox (work@aes_sbox), file:${SURELOG_DIR}/tests/VarSelectGenStmt/dut.sv, line:1:1, endln:6:10 + \_module_inst: work@aes_sbox (work@aes_sbox), file:${SURELOG_DIR}/tests/VarSelectGenStmt/dut.sv, line:1:1, endln:6:10 |vpiName:data_i |vpiDirection:1 |vpiLowConn: @@ -338,7 +338,7 @@ design: (work@aes_sub_bytes) |UINT:0 |vpiConstType:9 |uhdmallModules: -\_module: work@aes_sub_bytes (work@aes_sub_bytes), file:${SURELOG_DIR}/tests/VarSelectGenStmt/dut.sv, line:8:1, endln:23:10 +\_module_inst: work@aes_sub_bytes (work@aes_sub_bytes), file:${SURELOG_DIR}/tests/VarSelectGenStmt/dut.sv, line:8:1, endln:23:10 |vpiParent: \_design: (work@aes_sub_bytes) |vpiFullName:work@aes_sub_bytes @@ -346,14 +346,14 @@ design: (work@aes_sub_bytes) |vpiNet: \_logic_net: (work@aes_sub_bytes.data_i), line:10:32, endln:10:38 |vpiParent: - \_module: work@aes_sub_bytes (work@aes_sub_bytes), file:${SURELOG_DIR}/tests/VarSelectGenStmt/dut.sv, line:8:1, endln:23:10 + \_module_inst: work@aes_sub_bytes (work@aes_sub_bytes), file:${SURELOG_DIR}/tests/VarSelectGenStmt/dut.sv, line:8:1, endln:23:10 |vpiName:data_i |vpiFullName:work@aes_sub_bytes.data_i |vpiNetType:36 |vpiPort: \_port: (data_i), line:10:32, endln:10:38 |vpiParent: - \_module: work@aes_sub_bytes (work@aes_sub_bytes), file:${SURELOG_DIR}/tests/VarSelectGenStmt/dut.sv, line:8:1, endln:23:10 + \_module_inst: work@aes_sub_bytes (work@aes_sub_bytes), file:${SURELOG_DIR}/tests/VarSelectGenStmt/dut.sv, line:8:1, endln:23:10 |vpiName:data_i |vpiDirection:1 |vpiLowConn: @@ -417,14 +417,14 @@ design: (work@aes_sub_bytes) |UINT:0 |vpiConstType:9 |uhdmtopModules: -\_module: work@aes_sub_bytes (work@aes_sub_bytes), file:${SURELOG_DIR}/tests/VarSelectGenStmt/dut.sv, line:8:1, endln:23:10 +\_module_inst: work@aes_sub_bytes (work@aes_sub_bytes), file:${SURELOG_DIR}/tests/VarSelectGenStmt/dut.sv, line:8:1, endln:23:10 |vpiName:work@aes_sub_bytes |vpiDefName:work@aes_sub_bytes |vpiTop:1 |vpiNet: \_logic_net: (work@aes_sub_bytes.data_i), line:10:32, endln:10:38 |vpiParent: - \_module: work@aes_sub_bytes (work@aes_sub_bytes), file:${SURELOG_DIR}/tests/VarSelectGenStmt/dut.sv, line:8:1, endln:23:10 + \_module_inst: work@aes_sub_bytes (work@aes_sub_bytes), file:${SURELOG_DIR}/tests/VarSelectGenStmt/dut.sv, line:8:1, endln:23:10 |vpiTypespec: \_logic_typespec: , line:10:10, endln:10:31 |vpiRange: @@ -488,7 +488,7 @@ design: (work@aes_sub_bytes) |vpiPort: \_port: (data_i), line:10:32, endln:10:38 |vpiParent: - \_module: work@aes_sub_bytes (work@aes_sub_bytes), file:${SURELOG_DIR}/tests/VarSelectGenStmt/dut.sv, line:8:1, endln:23:10 + \_module_inst: work@aes_sub_bytes (work@aes_sub_bytes), file:${SURELOG_DIR}/tests/VarSelectGenStmt/dut.sv, line:8:1, endln:23:10 |vpiName:data_i |vpiDirection:1 |vpiLowConn: @@ -562,11 +562,11 @@ design: (work@aes_sub_bytes) |UINT:0 |vpiConstType:9 |vpiInstance: - \_module: work@aes_sub_bytes (work@aes_sub_bytes), file:${SURELOG_DIR}/tests/VarSelectGenStmt/dut.sv, line:8:1, endln:23:10 + \_module_inst: work@aes_sub_bytes (work@aes_sub_bytes), file:${SURELOG_DIR}/tests/VarSelectGenStmt/dut.sv, line:8:1, endln:23:10 |vpiGenScopeArray: \_gen_scope_array: (work@aes_sub_bytes.gen_sbox_j[0]), line:14:34, endln:21:6 |vpiParent: - \_module: work@aes_sub_bytes (work@aes_sub_bytes), file:${SURELOG_DIR}/tests/VarSelectGenStmt/dut.sv, line:8:1, endln:23:10 + \_module_inst: work@aes_sub_bytes (work@aes_sub_bytes), file:${SURELOG_DIR}/tests/VarSelectGenStmt/dut.sv, line:8:1, endln:23:10 |vpiName:gen_sbox_j[0] |vpiFullName:work@aes_sub_bytes.gen_sbox_j[0] |vpiGenScope: @@ -605,8 +605,8 @@ design: (work@aes_sub_bytes) |vpiLocalParam:1 |vpiName:i |vpiFullName:work@aes_sub_bytes.gen_sbox_j[0].gen_sbox_i[0].i - |vpiModule: - \_module: work@aes_sbox (work@aes_sub_bytes.gen_sbox_j[0].gen_sbox_i[0].aes_sbox_ij), file:${SURELOG_DIR}/tests/VarSelectGenStmt/dut.sv, line:16:7, endln:19:9 + |vpiModuleInst: + \_module_inst: work@aes_sbox (work@aes_sub_bytes.gen_sbox_j[0].gen_sbox_i[0].aes_sbox_ij), file:${SURELOG_DIR}/tests/VarSelectGenStmt/dut.sv, line:16:7, endln:19:9 |vpiParent: \_gen_scope: (work@aes_sub_bytes.gen_sbox_j[0].gen_sbox_i[0]) |vpiName:aes_sbox_ij @@ -617,7 +617,7 @@ design: (work@aes_sub_bytes) |vpiNet: \_logic_net: (work@aes_sub_bytes.gen_sbox_j[0].gen_sbox_i[0].aes_sbox_ij.data_i), line:3:32, endln:3:38 |vpiParent: - \_module: work@aes_sbox (work@aes_sub_bytes.gen_sbox_j[0].gen_sbox_i[0].aes_sbox_ij), file:${SURELOG_DIR}/tests/VarSelectGenStmt/dut.sv, line:16:7, endln:19:9 + \_module_inst: work@aes_sbox (work@aes_sub_bytes.gen_sbox_j[0].gen_sbox_i[0].aes_sbox_ij), file:${SURELOG_DIR}/tests/VarSelectGenStmt/dut.sv, line:16:7, endln:19:9 |vpiTypespec: \_logic_typespec: , line:3:10, endln:3:31 |vpiRange: @@ -680,7 +680,7 @@ design: (work@aes_sub_bytes) |vpiPort: \_port: (data_i), line:3:32, endln:3:38 |vpiParent: - \_module: work@aes_sbox (work@aes_sub_bytes.gen_sbox_j[0].gen_sbox_i[0].aes_sbox_ij), file:${SURELOG_DIR}/tests/VarSelectGenStmt/dut.sv, line:16:7, endln:19:9 + \_module_inst: work@aes_sbox (work@aes_sub_bytes.gen_sbox_j[0].gen_sbox_i[0].aes_sbox_ij), file:${SURELOG_DIR}/tests/VarSelectGenStmt/dut.sv, line:16:7, endln:19:9 |vpiName:data_i |vpiDirection:1 |vpiHighConn: @@ -776,7 +776,7 @@ design: (work@aes_sub_bytes) |UINT:0 |vpiConstType:9 |vpiInstance: - \_module: work@aes_sbox (work@aes_sub_bytes.gen_sbox_j[0].gen_sbox_i[0].aes_sbox_ij), file:${SURELOG_DIR}/tests/VarSelectGenStmt/dut.sv, line:16:7, endln:19:9 + \_module_inst: work@aes_sbox (work@aes_sub_bytes.gen_sbox_j[0].gen_sbox_i[0].aes_sbox_ij), file:${SURELOG_DIR}/tests/VarSelectGenStmt/dut.sv, line:16:7, endln:19:9 |vpiGenScopeArray: \_gen_scope_array: (work@aes_sub_bytes.gen_sbox_j[0].gen_sbox_i[1]), line:15:36, endln:20:8 |vpiParent: @@ -798,8 +798,8 @@ design: (work@aes_sub_bytes) |vpiLocalParam:1 |vpiName:i |vpiFullName:work@aes_sub_bytes.gen_sbox_j[0].gen_sbox_i[1].i - |vpiModule: - \_module: work@aes_sbox (work@aes_sub_bytes.gen_sbox_j[0].gen_sbox_i[1].aes_sbox_ij), file:${SURELOG_DIR}/tests/VarSelectGenStmt/dut.sv, line:16:7, endln:19:9 + |vpiModuleInst: + \_module_inst: work@aes_sbox (work@aes_sub_bytes.gen_sbox_j[0].gen_sbox_i[1].aes_sbox_ij), file:${SURELOG_DIR}/tests/VarSelectGenStmt/dut.sv, line:16:7, endln:19:9 |vpiParent: \_gen_scope: (work@aes_sub_bytes.gen_sbox_j[0].gen_sbox_i[1]) |vpiName:aes_sbox_ij @@ -810,7 +810,7 @@ design: (work@aes_sub_bytes) |vpiNet: \_logic_net: (work@aes_sub_bytes.gen_sbox_j[0].gen_sbox_i[1].aes_sbox_ij.data_i), line:3:32, endln:3:38 |vpiParent: - \_module: work@aes_sbox (work@aes_sub_bytes.gen_sbox_j[0].gen_sbox_i[1].aes_sbox_ij), file:${SURELOG_DIR}/tests/VarSelectGenStmt/dut.sv, line:16:7, endln:19:9 + \_module_inst: work@aes_sbox (work@aes_sub_bytes.gen_sbox_j[0].gen_sbox_i[1].aes_sbox_ij), file:${SURELOG_DIR}/tests/VarSelectGenStmt/dut.sv, line:16:7, endln:19:9 |vpiTypespec: \_logic_typespec: , line:3:10, endln:3:31 |vpiRange: @@ -873,7 +873,7 @@ design: (work@aes_sub_bytes) |vpiPort: \_port: (data_i), line:3:32, endln:3:38 |vpiParent: - \_module: work@aes_sbox (work@aes_sub_bytes.gen_sbox_j[0].gen_sbox_i[1].aes_sbox_ij), file:${SURELOG_DIR}/tests/VarSelectGenStmt/dut.sv, line:16:7, endln:19:9 + \_module_inst: work@aes_sbox (work@aes_sub_bytes.gen_sbox_j[0].gen_sbox_i[1].aes_sbox_ij), file:${SURELOG_DIR}/tests/VarSelectGenStmt/dut.sv, line:16:7, endln:19:9 |vpiName:data_i |vpiDirection:1 |vpiHighConn: @@ -969,11 +969,11 @@ design: (work@aes_sub_bytes) |UINT:0 |vpiConstType:9 |vpiInstance: - \_module: work@aes_sbox (work@aes_sub_bytes.gen_sbox_j[0].gen_sbox_i[1].aes_sbox_ij), file:${SURELOG_DIR}/tests/VarSelectGenStmt/dut.sv, line:16:7, endln:19:9 + \_module_inst: work@aes_sbox (work@aes_sub_bytes.gen_sbox_j[0].gen_sbox_i[1].aes_sbox_ij), file:${SURELOG_DIR}/tests/VarSelectGenStmt/dut.sv, line:16:7, endln:19:9 |vpiGenScopeArray: \_gen_scope_array: (work@aes_sub_bytes.gen_sbox_j[1]), line:14:34, endln:21:6 |vpiParent: - \_module: work@aes_sub_bytes (work@aes_sub_bytes), file:${SURELOG_DIR}/tests/VarSelectGenStmt/dut.sv, line:8:1, endln:23:10 + \_module_inst: work@aes_sub_bytes (work@aes_sub_bytes), file:${SURELOG_DIR}/tests/VarSelectGenStmt/dut.sv, line:8:1, endln:23:10 |vpiName:gen_sbox_j[1] |vpiFullName:work@aes_sub_bytes.gen_sbox_j[1] |vpiGenScope: @@ -1012,8 +1012,8 @@ design: (work@aes_sub_bytes) |vpiLocalParam:1 |vpiName:i |vpiFullName:work@aes_sub_bytes.gen_sbox_j[1].gen_sbox_i[0].i - |vpiModule: - \_module: work@aes_sbox (work@aes_sub_bytes.gen_sbox_j[1].gen_sbox_i[0].aes_sbox_ij), file:${SURELOG_DIR}/tests/VarSelectGenStmt/dut.sv, line:16:7, endln:19:9 + |vpiModuleInst: + \_module_inst: work@aes_sbox (work@aes_sub_bytes.gen_sbox_j[1].gen_sbox_i[0].aes_sbox_ij), file:${SURELOG_DIR}/tests/VarSelectGenStmt/dut.sv, line:16:7, endln:19:9 |vpiParent: \_gen_scope: (work@aes_sub_bytes.gen_sbox_j[1].gen_sbox_i[0]) |vpiName:aes_sbox_ij @@ -1024,7 +1024,7 @@ design: (work@aes_sub_bytes) |vpiNet: \_logic_net: (work@aes_sub_bytes.gen_sbox_j[1].gen_sbox_i[0].aes_sbox_ij.data_i), line:3:32, endln:3:38 |vpiParent: - \_module: work@aes_sbox (work@aes_sub_bytes.gen_sbox_j[1].gen_sbox_i[0].aes_sbox_ij), file:${SURELOG_DIR}/tests/VarSelectGenStmt/dut.sv, line:16:7, endln:19:9 + \_module_inst: work@aes_sbox (work@aes_sub_bytes.gen_sbox_j[1].gen_sbox_i[0].aes_sbox_ij), file:${SURELOG_DIR}/tests/VarSelectGenStmt/dut.sv, line:16:7, endln:19:9 |vpiTypespec: \_logic_typespec: , line:3:10, endln:3:31 |vpiRange: @@ -1087,7 +1087,7 @@ design: (work@aes_sub_bytes) |vpiPort: \_port: (data_i), line:3:32, endln:3:38 |vpiParent: - \_module: work@aes_sbox (work@aes_sub_bytes.gen_sbox_j[1].gen_sbox_i[0].aes_sbox_ij), file:${SURELOG_DIR}/tests/VarSelectGenStmt/dut.sv, line:16:7, endln:19:9 + \_module_inst: work@aes_sbox (work@aes_sub_bytes.gen_sbox_j[1].gen_sbox_i[0].aes_sbox_ij), file:${SURELOG_DIR}/tests/VarSelectGenStmt/dut.sv, line:16:7, endln:19:9 |vpiName:data_i |vpiDirection:1 |vpiHighConn: @@ -1183,7 +1183,7 @@ design: (work@aes_sub_bytes) |UINT:0 |vpiConstType:9 |vpiInstance: - \_module: work@aes_sbox (work@aes_sub_bytes.gen_sbox_j[1].gen_sbox_i[0].aes_sbox_ij), file:${SURELOG_DIR}/tests/VarSelectGenStmt/dut.sv, line:16:7, endln:19:9 + \_module_inst: work@aes_sbox (work@aes_sub_bytes.gen_sbox_j[1].gen_sbox_i[0].aes_sbox_ij), file:${SURELOG_DIR}/tests/VarSelectGenStmt/dut.sv, line:16:7, endln:19:9 |vpiGenScopeArray: \_gen_scope_array: (work@aes_sub_bytes.gen_sbox_j[1].gen_sbox_i[1]), line:15:36, endln:20:8 |vpiParent: @@ -1205,8 +1205,8 @@ design: (work@aes_sub_bytes) |vpiLocalParam:1 |vpiName:i |vpiFullName:work@aes_sub_bytes.gen_sbox_j[1].gen_sbox_i[1].i - |vpiModule: - \_module: work@aes_sbox (work@aes_sub_bytes.gen_sbox_j[1].gen_sbox_i[1].aes_sbox_ij), file:${SURELOG_DIR}/tests/VarSelectGenStmt/dut.sv, line:16:7, endln:19:9 + |vpiModuleInst: + \_module_inst: work@aes_sbox (work@aes_sub_bytes.gen_sbox_j[1].gen_sbox_i[1].aes_sbox_ij), file:${SURELOG_DIR}/tests/VarSelectGenStmt/dut.sv, line:16:7, endln:19:9 |vpiParent: \_gen_scope: (work@aes_sub_bytes.gen_sbox_j[1].gen_sbox_i[1]) |vpiName:aes_sbox_ij @@ -1217,7 +1217,7 @@ design: (work@aes_sub_bytes) |vpiNet: \_logic_net: (work@aes_sub_bytes.gen_sbox_j[1].gen_sbox_i[1].aes_sbox_ij.data_i), line:3:32, endln:3:38 |vpiParent: - \_module: work@aes_sbox (work@aes_sub_bytes.gen_sbox_j[1].gen_sbox_i[1].aes_sbox_ij), file:${SURELOG_DIR}/tests/VarSelectGenStmt/dut.sv, line:16:7, endln:19:9 + \_module_inst: work@aes_sbox (work@aes_sub_bytes.gen_sbox_j[1].gen_sbox_i[1].aes_sbox_ij), file:${SURELOG_DIR}/tests/VarSelectGenStmt/dut.sv, line:16:7, endln:19:9 |vpiTypespec: \_logic_typespec: , line:3:10, endln:3:31 |vpiRange: @@ -1280,7 +1280,7 @@ design: (work@aes_sub_bytes) |vpiPort: \_port: (data_i), line:3:32, endln:3:38 |vpiParent: - \_module: work@aes_sbox (work@aes_sub_bytes.gen_sbox_j[1].gen_sbox_i[1].aes_sbox_ij), file:${SURELOG_DIR}/tests/VarSelectGenStmt/dut.sv, line:16:7, endln:19:9 + \_module_inst: work@aes_sbox (work@aes_sub_bytes.gen_sbox_j[1].gen_sbox_i[1].aes_sbox_ij), file:${SURELOG_DIR}/tests/VarSelectGenStmt/dut.sv, line:16:7, endln:19:9 |vpiName:data_i |vpiDirection:1 |vpiHighConn: @@ -1376,7 +1376,7 @@ design: (work@aes_sub_bytes) |UINT:0 |vpiConstType:9 |vpiInstance: - \_module: work@aes_sbox (work@aes_sub_bytes.gen_sbox_j[1].gen_sbox_i[1].aes_sbox_ij), file:${SURELOG_DIR}/tests/VarSelectGenStmt/dut.sv, line:16:7, endln:19:9 + \_module_inst: work@aes_sbox (work@aes_sub_bytes.gen_sbox_j[1].gen_sbox_i[1].aes_sbox_ij), file:${SURELOG_DIR}/tests/VarSelectGenStmt/dut.sv, line:16:7, endln:19:9 =================== [ FATAL] : 0 [ SYNTAX] : 0 diff --git a/tests/VarType/VarType.log b/tests/VarType/VarType.log index b184872806..ab1d8a7b54 100644 --- a/tests/VarType/VarType.log +++ b/tests/VarType/VarType.log @@ -96,7 +96,7 @@ n<> u<69> t c<1> l<1:1> el<6:1> constant 3 design 1 logic_net 3 -module 3 +module_inst 3 operation 1 real_typespec 3 real_var 3 @@ -108,7 +108,7 @@ ref_obj 2 constant 3 design 1 logic_net 3 -module 3 +module_inst 3 operation 1 real_typespec 3 real_var 3 @@ -127,7 +127,7 @@ design: (work@top) |vpiElaborated:1 |vpiName:work@top |uhdmallModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/VarType/dut.sv, line:1:1, endln:5:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/VarType/dut.sv, line:1:1, endln:5:10 |vpiParent: \_design: (work@top) |vpiFullName:work@top @@ -135,28 +135,28 @@ design: (work@top) |vpiNet: \_logic_net: (work@top.a), line:2:6, endln:2:7 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/VarType/dut.sv, line:1:1, endln:5:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/VarType/dut.sv, line:1:1, endln:5:10 |vpiName:a |vpiFullName:work@top.a |vpiNet: \_logic_net: (work@top.b), line:3:6, endln:3:7 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/VarType/dut.sv, line:1:1, endln:5:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/VarType/dut.sv, line:1:1, endln:5:10 |vpiName:b |vpiFullName:work@top.b |vpiNet: \_logic_net: (work@top.c), line:4:15, endln:4:16 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/VarType/dut.sv, line:1:1, endln:5:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/VarType/dut.sv, line:1:1, endln:5:10 |vpiName:c |vpiFullName:work@top.c |uhdmtopModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/VarType/dut.sv, line:1:1, endln:5:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/VarType/dut.sv, line:1:1, endln:5:10 |vpiName:work@top |vpiVariables: \_real_var: (work@top.a), line:2:6, endln:2:14 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/VarType/dut.sv, line:1:1, endln:5:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/VarType/dut.sv, line:1:1, endln:5:10 |vpiTypespec: \_real_typespec: , line:2:1, endln:2:5 |vpiName:a @@ -173,7 +173,7 @@ design: (work@top) |vpiVariables: \_real_var: (work@top.b), line:3:6, endln:3:14 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/VarType/dut.sv, line:1:1, endln:5:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/VarType/dut.sv, line:1:1, endln:5:10 |vpiTypespec: \_real_typespec: , line:3:1, endln:3:5 |vpiName:b @@ -190,7 +190,7 @@ design: (work@top) |vpiVariables: \_real_var: (work@top.c), line:4:15, endln:4:16 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/VarType/dut.sv, line:1:1, endln:5:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/VarType/dut.sv, line:1:1, endln:5:10 |vpiTypespec: \_real_typespec: , line:4:5, endln:4:14 |vpiName:c diff --git a/tests/VirtualClass/VirtualClass.log b/tests/VirtualClass/VirtualClass.log index f51a3f23e6..2054441842 100644 --- a/tests/VirtualClass/VirtualClass.log +++ b/tests/VirtualClass/VirtualClass.log @@ -280,7 +280,7 @@ int_typespec 1 logic_net 3 logic_typespec 4 logic_var 3 -module 3 +module_inst 3 operation 5 packed_array_typespec 2 param_assign 1 @@ -303,7 +303,7 @@ int_typespec 1 logic_net 3 logic_typespec 5 logic_var 3 -module 3 +module_inst 3 operation 7 packed_array_typespec 2 param_assign 2 @@ -555,17 +555,17 @@ design: (work@top) \_constant: , line:2:27, endln:2:28 |vpiVirtual:1 |uhdmallModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/VirtualClass/dut.sv, line:11:1, endln:15:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/VirtualClass/dut.sv, line:11:1, endln:15:10 |vpiParent: \_design: (work@top) |vpiFullName:work@top |vpiTypedef: \_logic_typespec: (t_t0), line:12:13, endln:12:24 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/VirtualClass/dut.sv, line:11:1, endln:15:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/VirtualClass/dut.sv, line:11:1, endln:15:10 |vpiName:t_t0 |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/VirtualClass/dut.sv, line:11:1, endln:15:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/VirtualClass/dut.sv, line:11:1, endln:15:10 |vpiRange: \_range: , line:12:19, endln:12:24 |vpiLeftRange: @@ -588,42 +588,42 @@ design: (work@top) |vpiNet: \_logic_net: (work@top.v0), line:13:26, endln:13:28 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/VirtualClass/dut.sv, line:11:1, endln:15:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/VirtualClass/dut.sv, line:11:1, endln:15:10 |vpiName:v0 |vpiFullName:work@top.v0 |vpiNet: \_logic_net: (work@top.a0), line:13:50, endln:13:52 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/VirtualClass/dut.sv, line:11:1, endln:15:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/VirtualClass/dut.sv, line:11:1, endln:15:10 |vpiName:a0 |vpiFullName:work@top.a0 |vpiNet: \_logic_net: (work@top.s0), line:14:25, endln:14:27 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/VirtualClass/dut.sv, line:11:1, endln:15:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/VirtualClass/dut.sv, line:11:1, endln:15:10 |vpiName:s0 |vpiFullName:work@top.s0 |uhdmtopModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/VirtualClass/dut.sv, line:11:1, endln:15:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/VirtualClass/dut.sv, line:11:1, endln:15:10 |vpiName:work@top |vpiVariables: \_logic_var: (work@top.v0), line:13:26, endln:13:28 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/VirtualClass/dut.sv, line:11:1, endln:15:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/VirtualClass/dut.sv, line:11:1, endln:15:10 |vpiName:v0 |vpiFullName:work@top.v0 |vpiVisibility:1 |vpiVariables: \_logic_var: (work@top.a0), line:13:50, endln:13:52 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/VirtualClass/dut.sv, line:11:1, endln:15:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/VirtualClass/dut.sv, line:11:1, endln:15:10 |vpiName:a0 |vpiFullName:work@top.a0 |vpiVisibility:1 |vpiVariables: \_logic_var: (work@top.s0), line:14:25, endln:14:27 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/VirtualClass/dut.sv, line:11:1, endln:15:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/VirtualClass/dut.sv, line:11:1, endln:15:10 |vpiName:s0 |vpiFullName:work@top.s0 |vpiVisibility:1 diff --git a/tests/VoidFuncReturn/VoidFuncReturn.log b/tests/VoidFuncReturn/VoidFuncReturn.log index 144d4f21cb..87ea440914 100644 --- a/tests/VoidFuncReturn/VoidFuncReturn.log +++ b/tests/VoidFuncReturn/VoidFuncReturn.log @@ -134,7 +134,7 @@ function 1 initial 1 int_typespec 2 io_decl 2 -module 2 +module_inst 2 operation 1 ref_obj 4 return_stmt 1 @@ -153,7 +153,7 @@ function 2 initial 2 int_typespec 2 io_decl 4 -module 2 +module_inst 2 operation 2 ref_obj 8 return_stmt 2 @@ -172,7 +172,7 @@ design: (work@top) |vpiElaborated:1 |vpiName:work@top |uhdmallModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/VoidFuncReturn/dut.sv, line:1:1, endln:11:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/VoidFuncReturn/dut.sv, line:1:1, endln:11:10 |vpiParent: \_design: (work@top) |vpiFullName:work@top @@ -180,12 +180,12 @@ design: (work@top) |vpiTaskFunc: \_function: (work@top.add), line:3:1, endln:6:12 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/VoidFuncReturn/dut.sv, line:1:1, endln:11:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/VoidFuncReturn/dut.sv, line:1:1, endln:11:10 |vpiName:add |vpiFullName:work@top.add |vpiVisibility:1 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/VoidFuncReturn/dut.sv, line:1:1, endln:11:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/VoidFuncReturn/dut.sv, line:1:1, endln:11:10 |vpiIODecl: \_io_decl: (a), line:3:23, endln:3:24 |vpiDirection:1 @@ -260,11 +260,11 @@ design: (work@top) |vpiActual: \_io_decl: (b), line:3:30, endln:3:31 |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/VoidFuncReturn/dut.sv, line:1:1, endln:11:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/VoidFuncReturn/dut.sv, line:1:1, endln:11:10 |vpiProcess: \_initial: , line:8:1, endln:9:29 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/VoidFuncReturn/dut.sv, line:1:1, endln:11:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/VoidFuncReturn/dut.sv, line:1:1, endln:11:10 |vpiStmt: \_sys_func_call: ($display), line:9:1, endln:9:28 |vpiParent: @@ -302,19 +302,19 @@ design: (work@top) \_function: (work@top.add), line:3:1, endln:6:12 |vpiName:$display |uhdmtopModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/VoidFuncReturn/dut.sv, line:1:1, endln:11:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/VoidFuncReturn/dut.sv, line:1:1, endln:11:10 |vpiName:work@top |vpiDefName:work@top |vpiTop:1 |vpiTaskFunc: \_function: (work@top.add), line:3:1, endln:6:12 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/VoidFuncReturn/dut.sv, line:1:1, endln:11:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/VoidFuncReturn/dut.sv, line:1:1, endln:11:10 |vpiName:add |vpiFullName:work@top.add |vpiVisibility:1 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/VoidFuncReturn/dut.sv, line:1:1, endln:11:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/VoidFuncReturn/dut.sv, line:1:1, endln:11:10 |vpiIODecl: \_io_decl: (a), line:3:23, endln:3:24 |vpiParent: @@ -385,12 +385,12 @@ design: (work@top) |vpiActual: \_io_decl: (b), line:3:30, endln:3:31 |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/VoidFuncReturn/dut.sv, line:1:1, endln:11:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/VoidFuncReturn/dut.sv, line:1:1, endln:11:10 |vpiTopModule:1 |vpiProcess: \_initial: , line:8:1, endln:9:29 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/VoidFuncReturn/dut.sv, line:1:1, endln:11:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/VoidFuncReturn/dut.sv, line:1:1, endln:11:10 |vpiStmt: \_sys_func_call: ($display), line:9:1, endln:9:28 |vpiParent: diff --git a/tests/Wand/Wand.log b/tests/Wand/Wand.log index 985e278b2d..d5a7869da1 100644 --- a/tests/Wand/Wand.log +++ b/tests/Wand/Wand.log @@ -25,7 +25,7 @@ cont_assign 2 design 1 logic_net 8 logic_typespec 3 -module 3 +module_inst 3 ref_obj 4 === UHDM Object Stats End === [INF:UH0707] Elaborating UHDM... @@ -35,7 +35,7 @@ cont_assign 4 design 1 logic_net 8 logic_typespec 3 -module 3 +module_inst 3 ref_obj 8 === UHDM Object Stats End === [INF:UH0708] Writing UHDM DB: ${SURELOG_DIR}/build/regression/Wand/slpp_all/surelog.uhdm ... @@ -51,7 +51,7 @@ design: (work@test_wand_wor) |vpiElaborated:1 |vpiName:work@test_wand_wor |uhdmallModules: -\_module: work@test_wand_wor (work@test_wand_wor), file:${SURELOG_DIR}/tests/Wand/dut.sv, line:1:2, endln:10:11 +\_module_inst: work@test_wand_wor (work@test_wand_wor), file:${SURELOG_DIR}/tests/Wand/dut.sv, line:1:2, endln:10:11 |vpiParent: \_design: (work@test_wand_wor) |vpiFullName:work@test_wand_wor @@ -59,35 +59,35 @@ design: (work@test_wand_wor) |vpiNet: \_logic_net: (work@test_wand_wor.a), line:3:9, endln:3:10 |vpiParent: - \_module: work@test_wand_wor (work@test_wand_wor), file:${SURELOG_DIR}/tests/Wand/dut.sv, line:1:2, endln:10:11 + \_module_inst: work@test_wand_wor (work@test_wand_wor), file:${SURELOG_DIR}/tests/Wand/dut.sv, line:1:2, endln:10:11 |vpiName:a |vpiFullName:work@test_wand_wor.a |vpiNetType:2 |vpiNet: \_logic_net: (work@test_wand_wor.b), line:4:9, endln:4:10 |vpiParent: - \_module: work@test_wand_wor (work@test_wand_wor), file:${SURELOG_DIR}/tests/Wand/dut.sv, line:1:2, endln:10:11 + \_module_inst: work@test_wand_wor (work@test_wand_wor), file:${SURELOG_DIR}/tests/Wand/dut.sv, line:1:2, endln:10:11 |vpiName:b |vpiFullName:work@test_wand_wor.b |vpiNetType:3 |vpiNet: \_logic_net: (work@test_wand_wor.c), line:5:8, endln:5:9 |vpiParent: - \_module: work@test_wand_wor (work@test_wand_wor), file:${SURELOG_DIR}/tests/Wand/dut.sv, line:1:2, endln:10:11 + \_module_inst: work@test_wand_wor (work@test_wand_wor), file:${SURELOG_DIR}/tests/Wand/dut.sv, line:1:2, endln:10:11 |vpiName:c |vpiFullName:work@test_wand_wor.c |vpiNetType:48 |vpiNet: \_logic_net: (work@test_wand_wor.d), line:5:11, endln:5:12 |vpiParent: - \_module: work@test_wand_wor (work@test_wand_wor), file:${SURELOG_DIR}/tests/Wand/dut.sv, line:1:2, endln:10:11 + \_module_inst: work@test_wand_wor (work@test_wand_wor), file:${SURELOG_DIR}/tests/Wand/dut.sv, line:1:2, endln:10:11 |vpiName:d |vpiFullName:work@test_wand_wor.d |vpiNetType:48 |vpiContAssign: \_cont_assign: , line:7:11, endln:7:16 |vpiParent: - \_module: work@test_wand_wor (work@test_wand_wor), file:${SURELOG_DIR}/tests/Wand/dut.sv, line:1:2, endln:10:11 + \_module_inst: work@test_wand_wor (work@test_wand_wor), file:${SURELOG_DIR}/tests/Wand/dut.sv, line:1:2, endln:10:11 |vpiRhs: \_ref_obj: (work@test_wand_wor.c), line:7:15, endln:7:16 |vpiParent: @@ -107,7 +107,7 @@ design: (work@test_wand_wor) |vpiContAssign: \_cont_assign: , line:8:11, endln:8:16 |vpiParent: - \_module: work@test_wand_wor (work@test_wand_wor), file:${SURELOG_DIR}/tests/Wand/dut.sv, line:1:2, endln:10:11 + \_module_inst: work@test_wand_wor (work@test_wand_wor), file:${SURELOG_DIR}/tests/Wand/dut.sv, line:1:2, endln:10:11 |vpiRhs: \_ref_obj: (work@test_wand_wor.d), line:8:15, endln:8:16 |vpiParent: @@ -125,14 +125,14 @@ design: (work@test_wand_wor) |vpiActual: \_logic_net: (work@test_wand_wor.b), line:4:9, endln:4:10 |uhdmtopModules: -\_module: work@test_wand_wor (work@test_wand_wor), file:${SURELOG_DIR}/tests/Wand/dut.sv, line:1:2, endln:10:11 +\_module_inst: work@test_wand_wor (work@test_wand_wor), file:${SURELOG_DIR}/tests/Wand/dut.sv, line:1:2, endln:10:11 |vpiName:work@test_wand_wor |vpiDefName:work@test_wand_wor |vpiTop:1 |vpiNet: \_logic_net: (work@test_wand_wor.a), line:3:9, endln:3:10 |vpiParent: - \_module: work@test_wand_wor (work@test_wand_wor), file:${SURELOG_DIR}/tests/Wand/dut.sv, line:1:2, endln:10:11 + \_module_inst: work@test_wand_wor (work@test_wand_wor), file:${SURELOG_DIR}/tests/Wand/dut.sv, line:1:2, endln:10:11 |vpiTypespec: \_logic_typespec: , line:3:4, endln:3:8 |vpiName:a @@ -141,7 +141,7 @@ design: (work@test_wand_wor) |vpiNet: \_logic_net: (work@test_wand_wor.b), line:4:9, endln:4:10 |vpiParent: - \_module: work@test_wand_wor (work@test_wand_wor), file:${SURELOG_DIR}/tests/Wand/dut.sv, line:1:2, endln:10:11 + \_module_inst: work@test_wand_wor (work@test_wand_wor), file:${SURELOG_DIR}/tests/Wand/dut.sv, line:1:2, endln:10:11 |vpiTypespec: \_logic_typespec: , line:4:4, endln:4:7 |vpiName:b @@ -150,7 +150,7 @@ design: (work@test_wand_wor) |vpiNet: \_logic_net: (work@test_wand_wor.c), line:5:8, endln:5:9 |vpiParent: - \_module: work@test_wand_wor (work@test_wand_wor), file:${SURELOG_DIR}/tests/Wand/dut.sv, line:1:2, endln:10:11 + \_module_inst: work@test_wand_wor (work@test_wand_wor), file:${SURELOG_DIR}/tests/Wand/dut.sv, line:1:2, endln:10:11 |vpiTypespec: \_logic_typespec: , line:5:4, endln:5:7 |vpiName:c @@ -159,7 +159,7 @@ design: (work@test_wand_wor) |vpiNet: \_logic_net: (work@test_wand_wor.d), line:5:11, endln:5:12 |vpiParent: - \_module: work@test_wand_wor (work@test_wand_wor), file:${SURELOG_DIR}/tests/Wand/dut.sv, line:1:2, endln:10:11 + \_module_inst: work@test_wand_wor (work@test_wand_wor), file:${SURELOG_DIR}/tests/Wand/dut.sv, line:1:2, endln:10:11 |vpiTypespec: \_logic_typespec: , line:5:4, endln:5:7 |vpiName:d @@ -169,7 +169,7 @@ design: (work@test_wand_wor) |vpiContAssign: \_cont_assign: , line:7:11, endln:7:16 |vpiParent: - \_module: work@test_wand_wor (work@test_wand_wor), file:${SURELOG_DIR}/tests/Wand/dut.sv, line:1:2, endln:10:11 + \_module_inst: work@test_wand_wor (work@test_wand_wor), file:${SURELOG_DIR}/tests/Wand/dut.sv, line:1:2, endln:10:11 |vpiRhs: \_ref_obj: (work@test_wand_wor.c), line:7:15, endln:7:16 |vpiParent: @@ -189,7 +189,7 @@ design: (work@test_wand_wor) |vpiContAssign: \_cont_assign: , line:8:11, endln:8:16 |vpiParent: - \_module: work@test_wand_wor (work@test_wand_wor), file:${SURELOG_DIR}/tests/Wand/dut.sv, line:1:2, endln:10:11 + \_module_inst: work@test_wand_wor (work@test_wand_wor), file:${SURELOG_DIR}/tests/Wand/dut.sv, line:1:2, endln:10:11 |vpiRhs: \_ref_obj: (work@test_wand_wor.d), line:8:15, endln:8:16 |vpiParent: diff --git a/tests/WildConn/WildConn.log b/tests/WildConn/WildConn.log index 6d7a2b2452..8ce949cdb7 100644 --- a/tests/WildConn/WildConn.log +++ b/tests/WildConn/WildConn.log @@ -352,7 +352,7 @@ io_decl 11 logic_net 8 logic_typespec 8 logic_var 1 -module 4 +module_inst 4 package 2 port 8 ref_obj 10 @@ -376,7 +376,7 @@ io_decl 22 logic_net 8 logic_typespec 8 logic_var 1 -module 4 +module_inst 4 package 2 port 12 ref_obj 16 @@ -870,7 +870,7 @@ design: (work@top) \_int_typespec: |vpiSigned:1 |uhdmallModules: -\_module: work@MOD (work@MOD), file:${SURELOG_DIR}/tests/WildConn/dut.sv, line:1:1, endln:5:10 +\_module_inst: work@MOD (work@MOD), file:${SURELOG_DIR}/tests/WildConn/dut.sv, line:1:1, endln:5:10 |vpiParent: \_design: (work@top) |vpiFullName:work@MOD @@ -878,21 +878,21 @@ design: (work@top) |vpiNet: \_logic_net: (work@MOD.a), line:2:3, endln:2:4 |vpiParent: - \_module: work@MOD (work@MOD), file:${SURELOG_DIR}/tests/WildConn/dut.sv, line:1:1, endln:5:10 + \_module_inst: work@MOD (work@MOD), file:${SURELOG_DIR}/tests/WildConn/dut.sv, line:1:1, endln:5:10 |vpiName:a |vpiFullName:work@MOD.a |vpiNetType:36 |vpiNet: \_logic_net: (work@MOD.b), line:3:3, endln:3:4 |vpiParent: - \_module: work@MOD (work@MOD), file:${SURELOG_DIR}/tests/WildConn/dut.sv, line:1:1, endln:5:10 + \_module_inst: work@MOD (work@MOD), file:${SURELOG_DIR}/tests/WildConn/dut.sv, line:1:1, endln:5:10 |vpiName:b |vpiFullName:work@MOD.b |vpiNetType:36 |vpiPort: \_port: (a), line:2:3, endln:2:4 |vpiParent: - \_module: work@MOD (work@MOD), file:${SURELOG_DIR}/tests/WildConn/dut.sv, line:1:1, endln:5:10 + \_module_inst: work@MOD (work@MOD), file:${SURELOG_DIR}/tests/WildConn/dut.sv, line:1:1, endln:5:10 |vpiName:a |vpiDirection:1 |vpiLowConn: @@ -904,7 +904,7 @@ design: (work@top) |vpiPort: \_port: (b), line:3:3, endln:3:4 |vpiParent: - \_module: work@MOD (work@MOD), file:${SURELOG_DIR}/tests/WildConn/dut.sv, line:1:1, endln:5:10 + \_module_inst: work@MOD (work@MOD), file:${SURELOG_DIR}/tests/WildConn/dut.sv, line:1:1, endln:5:10 |vpiName:b |vpiDirection:1 |vpiLowConn: @@ -914,7 +914,7 @@ design: (work@top) |vpiTypedef: \_logic_typespec: , line:1:19, endln:1:24 |uhdmallModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/WildConn/dut.sv, line:7:1, endln:17:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/WildConn/dut.sv, line:7:1, endln:17:10 |vpiParent: \_design: (work@top) |vpiFullName:work@top @@ -922,21 +922,21 @@ design: (work@top) |vpiNet: \_logic_net: (work@top.a), line:8:3, endln:8:4 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/WildConn/dut.sv, line:7:1, endln:17:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/WildConn/dut.sv, line:7:1, endln:17:10 |vpiName:a |vpiFullName:work@top.a |vpiNetType:36 |vpiNet: \_logic_net: (work@top.b), line:9:3, endln:9:4 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/WildConn/dut.sv, line:7:1, endln:17:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/WildConn/dut.sv, line:7:1, endln:17:10 |vpiName:b |vpiFullName:work@top.b |vpiNetType:36 |vpiPort: \_port: (a), line:8:3, endln:8:4 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/WildConn/dut.sv, line:7:1, endln:17:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/WildConn/dut.sv, line:7:1, endln:17:10 |vpiName:a |vpiDirection:1 |vpiLowConn: @@ -948,7 +948,7 @@ design: (work@top) |vpiPort: \_port: (b), line:9:3, endln:9:4 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/WildConn/dut.sv, line:7:1, endln:17:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/WildConn/dut.sv, line:7:1, endln:17:10 |vpiName:b |vpiDirection:1 |vpiLowConn: @@ -958,14 +958,14 @@ design: (work@top) |vpiTypedef: \_logic_typespec: , line:7:18, endln:7:23 |uhdmtopModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/WildConn/dut.sv, line:7:1, endln:17:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/WildConn/dut.sv, line:7:1, endln:17:10 |vpiName:work@top |vpiDefName:work@top |vpiTop:1 |vpiNet: \_logic_net: (work@top.a), line:8:3, endln:8:4 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/WildConn/dut.sv, line:7:1, endln:17:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/WildConn/dut.sv, line:7:1, endln:17:10 |vpiTypespec: \_logic_typespec: , line:7:18, endln:7:23 |vpiName:a @@ -974,7 +974,7 @@ design: (work@top) |vpiNet: \_logic_net: (work@top.b), line:9:3, endln:9:4 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/WildConn/dut.sv, line:7:1, endln:17:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/WildConn/dut.sv, line:7:1, endln:17:10 |vpiTypespec: \_logic_typespec: , line:7:18, endln:7:23 |vpiName:b @@ -984,7 +984,7 @@ design: (work@top) |vpiPort: \_port: (a), line:8:3, endln:8:4 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/WildConn/dut.sv, line:7:1, endln:17:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/WildConn/dut.sv, line:7:1, endln:17:10 |vpiName:a |vpiDirection:1 |vpiLowConn: @@ -998,11 +998,11 @@ design: (work@top) |vpiTypedef: \_logic_typespec: , line:7:18, endln:7:23 |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/WildConn/dut.sv, line:7:1, endln:17:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/WildConn/dut.sv, line:7:1, endln:17:10 |vpiPort: \_port: (b), line:9:3, endln:9:4 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/WildConn/dut.sv, line:7:1, endln:17:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/WildConn/dut.sv, line:7:1, endln:17:10 |vpiName:b |vpiDirection:1 |vpiLowConn: @@ -1016,11 +1016,11 @@ design: (work@top) |vpiTypedef: \_logic_typespec: , line:7:18, endln:7:23 |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/WildConn/dut.sv, line:7:1, endln:17:10 - |vpiModule: - \_module: work@MOD (work@top.u1), file:${SURELOG_DIR}/tests/WildConn/dut.sv, line:12:3, endln:15:5 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/WildConn/dut.sv, line:7:1, endln:17:10 + |vpiModuleInst: + \_module_inst: work@MOD (work@top.u1), file:${SURELOG_DIR}/tests/WildConn/dut.sv, line:12:3, endln:15:5 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/WildConn/dut.sv, line:7:1, endln:17:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/WildConn/dut.sv, line:7:1, endln:17:10 |vpiName:u1 |vpiFullName:work@top.u1 |vpiDefName:work@MOD @@ -1029,7 +1029,7 @@ design: (work@top) |vpiNet: \_logic_net: (work@top.u1.a), line:2:3, endln:2:4 |vpiParent: - \_module: work@MOD (work@top.u1), file:${SURELOG_DIR}/tests/WildConn/dut.sv, line:12:3, endln:15:5 + \_module_inst: work@MOD (work@top.u1), file:${SURELOG_DIR}/tests/WildConn/dut.sv, line:12:3, endln:15:5 |vpiTypespec: \_logic_typespec: , line:1:19, endln:1:24 |vpiName:a @@ -1038,18 +1038,18 @@ design: (work@top) |vpiNet: \_logic_net: (work@top.u1.b), line:3:3, endln:3:4 |vpiParent: - \_module: work@MOD (work@top.u1), file:${SURELOG_DIR}/tests/WildConn/dut.sv, line:12:3, endln:15:5 + \_module_inst: work@MOD (work@top.u1), file:${SURELOG_DIR}/tests/WildConn/dut.sv, line:12:3, endln:15:5 |vpiTypespec: \_logic_typespec: , line:1:19, endln:1:24 |vpiName:b |vpiFullName:work@top.u1.b |vpiNetType:36 |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/WildConn/dut.sv, line:7:1, endln:17:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/WildConn/dut.sv, line:7:1, endln:17:10 |vpiPort: \_port: (a), line:2:3, endln:2:4 |vpiParent: - \_module: work@MOD (work@top.u1), file:${SURELOG_DIR}/tests/WildConn/dut.sv, line:12:3, endln:15:5 + \_module_inst: work@MOD (work@top.u1), file:${SURELOG_DIR}/tests/WildConn/dut.sv, line:12:3, endln:15:5 |vpiName:a |vpiDirection:1 |vpiHighConn: @@ -1071,11 +1071,11 @@ design: (work@top) |vpiTypedef: \_logic_typespec: , line:1:19, endln:1:24 |vpiInstance: - \_module: work@MOD (work@top.u1), file:${SURELOG_DIR}/tests/WildConn/dut.sv, line:12:3, endln:15:5 + \_module_inst: work@MOD (work@top.u1), file:${SURELOG_DIR}/tests/WildConn/dut.sv, line:12:3, endln:15:5 |vpiPort: \_port: (b), line:3:3, endln:3:4 |vpiParent: - \_module: work@MOD (work@top.u1), file:${SURELOG_DIR}/tests/WildConn/dut.sv, line:12:3, endln:15:5 + \_module_inst: work@MOD (work@top.u1), file:${SURELOG_DIR}/tests/WildConn/dut.sv, line:12:3, endln:15:5 |vpiName:b |vpiDirection:1 |vpiHighConn: @@ -1097,7 +1097,7 @@ design: (work@top) |vpiTypedef: \_logic_typespec: , line:1:19, endln:1:24 |vpiInstance: - \_module: work@MOD (work@top.u1), file:${SURELOG_DIR}/tests/WildConn/dut.sv, line:12:3, endln:15:5 + \_module_inst: work@MOD (work@top.u1), file:${SURELOG_DIR}/tests/WildConn/dut.sv, line:12:3, endln:15:5 =================== [ FATAL] : 0 [ SYNTAX] : 0 diff --git a/tests/WireLogicSize/WireLogicSize.log b/tests/WireLogicSize/WireLogicSize.log index 7c6fe56754..c4336c5720 100644 --- a/tests/WireLogicSize/WireLogicSize.log +++ b/tests/WireLogicSize/WireLogicSize.log @@ -84,7 +84,7 @@ constant 12 design 1 logic_net 12 logic_typespec 10 -module 3 +module_inst 3 port 12 range 6 ref_obj 12 @@ -96,7 +96,7 @@ constant 12 design 1 logic_net 12 logic_typespec 10 -module 3 +module_inst 3 port 18 range 6 ref_obj 18 @@ -114,7 +114,7 @@ design: (work@TestFunction) |vpiElaborated:1 |vpiName:work@TestFunction |uhdmallModules: -\_module: work@TestFunction (work@TestFunction), file:${SURELOG_DIR}/tests/WireLogicSize/dut.sv, line:1:1, endln:23:10 +\_module_inst: work@TestFunction (work@TestFunction), file:${SURELOG_DIR}/tests/WireLogicSize/dut.sv, line:1:1, endln:23:10 |vpiParent: \_design: (work@TestFunction) |vpiFullName:work@TestFunction @@ -122,49 +122,49 @@ design: (work@TestFunction) |vpiNet: \_logic_net: (work@TestFunction.O1), line:2:17, endln:2:19 |vpiParent: - \_module: work@TestFunction (work@TestFunction), file:${SURELOG_DIR}/tests/WireLogicSize/dut.sv, line:1:1, endln:23:10 + \_module_inst: work@TestFunction (work@TestFunction), file:${SURELOG_DIR}/tests/WireLogicSize/dut.sv, line:1:1, endln:23:10 |vpiName:O1 |vpiFullName:work@TestFunction.O1 |vpiNetType:36 |vpiNet: \_logic_net: (work@TestFunction.O2), line:2:21, endln:2:23 |vpiParent: - \_module: work@TestFunction (work@TestFunction), file:${SURELOG_DIR}/tests/WireLogicSize/dut.sv, line:1:1, endln:23:10 + \_module_inst: work@TestFunction (work@TestFunction), file:${SURELOG_DIR}/tests/WireLogicSize/dut.sv, line:1:1, endln:23:10 |vpiName:O2 |vpiFullName:work@TestFunction.O2 |vpiNetType:36 |vpiNet: \_logic_net: (work@TestFunction.O3), line:2:25, endln:2:27 |vpiParent: - \_module: work@TestFunction (work@TestFunction), file:${SURELOG_DIR}/tests/WireLogicSize/dut.sv, line:1:1, endln:23:10 + \_module_inst: work@TestFunction (work@TestFunction), file:${SURELOG_DIR}/tests/WireLogicSize/dut.sv, line:1:1, endln:23:10 |vpiName:O3 |vpiFullName:work@TestFunction.O3 |vpiNetType:36 |vpiNet: \_logic_net: (work@TestFunction.O4), line:2:29, endln:2:31 |vpiParent: - \_module: work@TestFunction (work@TestFunction), file:${SURELOG_DIR}/tests/WireLogicSize/dut.sv, line:1:1, endln:23:10 + \_module_inst: work@TestFunction (work@TestFunction), file:${SURELOG_DIR}/tests/WireLogicSize/dut.sv, line:1:1, endln:23:10 |vpiName:O4 |vpiFullName:work@TestFunction.O4 |vpiNetType:36 |vpiNet: \_logic_net: (work@TestFunction.sw), line:3:27, endln:3:29 |vpiParent: - \_module: work@TestFunction (work@TestFunction), file:${SURELOG_DIR}/tests/WireLogicSize/dut.sv, line:1:1, endln:23:10 + \_module_inst: work@TestFunction (work@TestFunction), file:${SURELOG_DIR}/tests/WireLogicSize/dut.sv, line:1:1, endln:23:10 |vpiName:sw |vpiFullName:work@TestFunction.sw |vpiNetType:36 |vpiNet: \_logic_net: (work@TestFunction.sw2), line:3:32, endln:3:35 |vpiParent: - \_module: work@TestFunction (work@TestFunction), file:${SURELOG_DIR}/tests/WireLogicSize/dut.sv, line:1:1, endln:23:10 + \_module_inst: work@TestFunction (work@TestFunction), file:${SURELOG_DIR}/tests/WireLogicSize/dut.sv, line:1:1, endln:23:10 |vpiName:sw2 |vpiFullName:work@TestFunction.sw2 |vpiNetType:36 |vpiPort: \_port: (O1), line:2:17, endln:2:19 |vpiParent: - \_module: work@TestFunction (work@TestFunction), file:${SURELOG_DIR}/tests/WireLogicSize/dut.sv, line:1:1, endln:23:10 + \_module_inst: work@TestFunction (work@TestFunction), file:${SURELOG_DIR}/tests/WireLogicSize/dut.sv, line:1:1, endln:23:10 |vpiName:O1 |vpiDirection:2 |vpiLowConn: @@ -176,7 +176,7 @@ design: (work@TestFunction) |vpiPort: \_port: (O2), line:2:21, endln:2:23 |vpiParent: - \_module: work@TestFunction (work@TestFunction), file:${SURELOG_DIR}/tests/WireLogicSize/dut.sv, line:1:1, endln:23:10 + \_module_inst: work@TestFunction (work@TestFunction), file:${SURELOG_DIR}/tests/WireLogicSize/dut.sv, line:1:1, endln:23:10 |vpiName:O2 |vpiDirection:2 |vpiLowConn: @@ -188,7 +188,7 @@ design: (work@TestFunction) |vpiPort: \_port: (O3), line:2:25, endln:2:27 |vpiParent: - \_module: work@TestFunction (work@TestFunction), file:${SURELOG_DIR}/tests/WireLogicSize/dut.sv, line:1:1, endln:23:10 + \_module_inst: work@TestFunction (work@TestFunction), file:${SURELOG_DIR}/tests/WireLogicSize/dut.sv, line:1:1, endln:23:10 |vpiName:O3 |vpiDirection:2 |vpiLowConn: @@ -200,7 +200,7 @@ design: (work@TestFunction) |vpiPort: \_port: (O4), line:2:29, endln:2:31 |vpiParent: - \_module: work@TestFunction (work@TestFunction), file:${SURELOG_DIR}/tests/WireLogicSize/dut.sv, line:1:1, endln:23:10 + \_module_inst: work@TestFunction (work@TestFunction), file:${SURELOG_DIR}/tests/WireLogicSize/dut.sv, line:1:1, endln:23:10 |vpiName:O4 |vpiDirection:2 |vpiLowConn: @@ -212,7 +212,7 @@ design: (work@TestFunction) |vpiPort: \_port: (sw), line:3:27, endln:3:29 |vpiParent: - \_module: work@TestFunction (work@TestFunction), file:${SURELOG_DIR}/tests/WireLogicSize/dut.sv, line:1:1, endln:23:10 + \_module_inst: work@TestFunction (work@TestFunction), file:${SURELOG_DIR}/tests/WireLogicSize/dut.sv, line:1:1, endln:23:10 |vpiName:sw |vpiDirection:1 |vpiLowConn: @@ -242,7 +242,7 @@ design: (work@TestFunction) |vpiPort: \_port: (sw2), line:3:32, endln:3:35 |vpiParent: - \_module: work@TestFunction (work@TestFunction), file:${SURELOG_DIR}/tests/WireLogicSize/dut.sv, line:1:1, endln:23:10 + \_module_inst: work@TestFunction (work@TestFunction), file:${SURELOG_DIR}/tests/WireLogicSize/dut.sv, line:1:1, endln:23:10 |vpiName:sw2 |vpiDirection:1 |vpiLowConn: @@ -270,14 +270,14 @@ design: (work@TestFunction) |UINT:0 |vpiConstType:9 |uhdmtopModules: -\_module: work@TestFunction (work@TestFunction), file:${SURELOG_DIR}/tests/WireLogicSize/dut.sv, line:1:1, endln:23:10 +\_module_inst: work@TestFunction (work@TestFunction), file:${SURELOG_DIR}/tests/WireLogicSize/dut.sv, line:1:1, endln:23:10 |vpiName:work@TestFunction |vpiDefName:work@TestFunction |vpiTop:1 |vpiNet: \_logic_net: (work@TestFunction.O1), line:2:17, endln:2:19 |vpiParent: - \_module: work@TestFunction (work@TestFunction), file:${SURELOG_DIR}/tests/WireLogicSize/dut.sv, line:1:1, endln:23:10 + \_module_inst: work@TestFunction (work@TestFunction), file:${SURELOG_DIR}/tests/WireLogicSize/dut.sv, line:1:1, endln:23:10 |vpiTypespec: \_logic_typespec: , line:2:11, endln:2:16 |vpiName:O1 @@ -286,7 +286,7 @@ design: (work@TestFunction) |vpiNet: \_logic_net: (work@TestFunction.O2), line:2:21, endln:2:23 |vpiParent: - \_module: work@TestFunction (work@TestFunction), file:${SURELOG_DIR}/tests/WireLogicSize/dut.sv, line:1:1, endln:23:10 + \_module_inst: work@TestFunction (work@TestFunction), file:${SURELOG_DIR}/tests/WireLogicSize/dut.sv, line:1:1, endln:23:10 |vpiTypespec: \_logic_typespec: , line:2:11, endln:2:16 |vpiName:O2 @@ -295,7 +295,7 @@ design: (work@TestFunction) |vpiNet: \_logic_net: (work@TestFunction.O3), line:2:25, endln:2:27 |vpiParent: - \_module: work@TestFunction (work@TestFunction), file:${SURELOG_DIR}/tests/WireLogicSize/dut.sv, line:1:1, endln:23:10 + \_module_inst: work@TestFunction (work@TestFunction), file:${SURELOG_DIR}/tests/WireLogicSize/dut.sv, line:1:1, endln:23:10 |vpiTypespec: \_logic_typespec: , line:2:11, endln:2:16 |vpiName:O3 @@ -304,7 +304,7 @@ design: (work@TestFunction) |vpiNet: \_logic_net: (work@TestFunction.O4), line:2:29, endln:2:31 |vpiParent: - \_module: work@TestFunction (work@TestFunction), file:${SURELOG_DIR}/tests/WireLogicSize/dut.sv, line:1:1, endln:23:10 + \_module_inst: work@TestFunction (work@TestFunction), file:${SURELOG_DIR}/tests/WireLogicSize/dut.sv, line:1:1, endln:23:10 |vpiTypespec: \_logic_typespec: , line:2:11, endln:2:16 |vpiName:O4 @@ -313,7 +313,7 @@ design: (work@TestFunction) |vpiNet: \_logic_net: (work@TestFunction.sw), line:3:27, endln:3:29 |vpiParent: - \_module: work@TestFunction (work@TestFunction), file:${SURELOG_DIR}/tests/WireLogicSize/dut.sv, line:1:1, endln:23:10 + \_module_inst: work@TestFunction (work@TestFunction), file:${SURELOG_DIR}/tests/WireLogicSize/dut.sv, line:1:1, endln:23:10 |vpiTypespec: \_logic_typespec: , line:3:16, endln:3:26 |vpiRange: @@ -340,7 +340,7 @@ design: (work@TestFunction) |vpiNet: \_logic_net: (work@TestFunction.sw2), line:3:32, endln:3:35 |vpiParent: - \_module: work@TestFunction (work@TestFunction), file:${SURELOG_DIR}/tests/WireLogicSize/dut.sv, line:1:1, endln:23:10 + \_module_inst: work@TestFunction (work@TestFunction), file:${SURELOG_DIR}/tests/WireLogicSize/dut.sv, line:1:1, endln:23:10 |vpiTypespec: \_logic_typespec: , line:3:16, endln:3:26 |vpiName:sw2 @@ -350,7 +350,7 @@ design: (work@TestFunction) |vpiPort: \_port: (O1), line:2:17, endln:2:19 |vpiParent: - \_module: work@TestFunction (work@TestFunction), file:${SURELOG_DIR}/tests/WireLogicSize/dut.sv, line:1:1, endln:23:10 + \_module_inst: work@TestFunction (work@TestFunction), file:${SURELOG_DIR}/tests/WireLogicSize/dut.sv, line:1:1, endln:23:10 |vpiName:O1 |vpiDirection:2 |vpiLowConn: @@ -364,11 +364,11 @@ design: (work@TestFunction) |vpiTypedef: \_logic_typespec: , line:2:11, endln:2:16 |vpiInstance: - \_module: work@TestFunction (work@TestFunction), file:${SURELOG_DIR}/tests/WireLogicSize/dut.sv, line:1:1, endln:23:10 + \_module_inst: work@TestFunction (work@TestFunction), file:${SURELOG_DIR}/tests/WireLogicSize/dut.sv, line:1:1, endln:23:10 |vpiPort: \_port: (O2), line:2:21, endln:2:23 |vpiParent: - \_module: work@TestFunction (work@TestFunction), file:${SURELOG_DIR}/tests/WireLogicSize/dut.sv, line:1:1, endln:23:10 + \_module_inst: work@TestFunction (work@TestFunction), file:${SURELOG_DIR}/tests/WireLogicSize/dut.sv, line:1:1, endln:23:10 |vpiName:O2 |vpiDirection:2 |vpiLowConn: @@ -382,11 +382,11 @@ design: (work@TestFunction) |vpiTypedef: \_logic_typespec: , line:2:11, endln:2:16 |vpiInstance: - \_module: work@TestFunction (work@TestFunction), file:${SURELOG_DIR}/tests/WireLogicSize/dut.sv, line:1:1, endln:23:10 + \_module_inst: work@TestFunction (work@TestFunction), file:${SURELOG_DIR}/tests/WireLogicSize/dut.sv, line:1:1, endln:23:10 |vpiPort: \_port: (O3), line:2:25, endln:2:27 |vpiParent: - \_module: work@TestFunction (work@TestFunction), file:${SURELOG_DIR}/tests/WireLogicSize/dut.sv, line:1:1, endln:23:10 + \_module_inst: work@TestFunction (work@TestFunction), file:${SURELOG_DIR}/tests/WireLogicSize/dut.sv, line:1:1, endln:23:10 |vpiName:O3 |vpiDirection:2 |vpiLowConn: @@ -400,11 +400,11 @@ design: (work@TestFunction) |vpiTypedef: \_logic_typespec: , line:2:11, endln:2:16 |vpiInstance: - \_module: work@TestFunction (work@TestFunction), file:${SURELOG_DIR}/tests/WireLogicSize/dut.sv, line:1:1, endln:23:10 + \_module_inst: work@TestFunction (work@TestFunction), file:${SURELOG_DIR}/tests/WireLogicSize/dut.sv, line:1:1, endln:23:10 |vpiPort: \_port: (O4), line:2:29, endln:2:31 |vpiParent: - \_module: work@TestFunction (work@TestFunction), file:${SURELOG_DIR}/tests/WireLogicSize/dut.sv, line:1:1, endln:23:10 + \_module_inst: work@TestFunction (work@TestFunction), file:${SURELOG_DIR}/tests/WireLogicSize/dut.sv, line:1:1, endln:23:10 |vpiName:O4 |vpiDirection:2 |vpiLowConn: @@ -418,11 +418,11 @@ design: (work@TestFunction) |vpiTypedef: \_logic_typespec: , line:2:11, endln:2:16 |vpiInstance: - \_module: work@TestFunction (work@TestFunction), file:${SURELOG_DIR}/tests/WireLogicSize/dut.sv, line:1:1, endln:23:10 + \_module_inst: work@TestFunction (work@TestFunction), file:${SURELOG_DIR}/tests/WireLogicSize/dut.sv, line:1:1, endln:23:10 |vpiPort: \_port: (sw), line:3:27, endln:3:29 |vpiParent: - \_module: work@TestFunction (work@TestFunction), file:${SURELOG_DIR}/tests/WireLogicSize/dut.sv, line:1:1, endln:23:10 + \_module_inst: work@TestFunction (work@TestFunction), file:${SURELOG_DIR}/tests/WireLogicSize/dut.sv, line:1:1, endln:23:10 |vpiName:sw |vpiDirection:1 |vpiLowConn: @@ -456,11 +456,11 @@ design: (work@TestFunction) |UINT:0 |vpiConstType:9 |vpiInstance: - \_module: work@TestFunction (work@TestFunction), file:${SURELOG_DIR}/tests/WireLogicSize/dut.sv, line:1:1, endln:23:10 + \_module_inst: work@TestFunction (work@TestFunction), file:${SURELOG_DIR}/tests/WireLogicSize/dut.sv, line:1:1, endln:23:10 |vpiPort: \_port: (sw2), line:3:32, endln:3:35 |vpiParent: - \_module: work@TestFunction (work@TestFunction), file:${SURELOG_DIR}/tests/WireLogicSize/dut.sv, line:1:1, endln:23:10 + \_module_inst: work@TestFunction (work@TestFunction), file:${SURELOG_DIR}/tests/WireLogicSize/dut.sv, line:1:1, endln:23:10 |vpiName:sw2 |vpiDirection:1 |vpiLowConn: @@ -474,7 +474,7 @@ design: (work@TestFunction) |vpiTypedef: \_logic_typespec: , line:3:16, endln:3:26 |vpiInstance: - \_module: work@TestFunction (work@TestFunction), file:${SURELOG_DIR}/tests/WireLogicSize/dut.sv, line:1:1, endln:23:10 + \_module_inst: work@TestFunction (work@TestFunction), file:${SURELOG_DIR}/tests/WireLogicSize/dut.sv, line:1:1, endln:23:10 =================== [ FATAL] : 0 [ SYNTAX] : 0 diff --git a/tests/WireUnpacked/WireUnpacked.log b/tests/WireUnpacked/WireUnpacked.log index 00733fafa7..ce5f73ab16 100644 --- a/tests/WireUnpacked/WireUnpacked.log +++ b/tests/WireUnpacked/WireUnpacked.log @@ -105,7 +105,7 @@ design 1 indexed_part_select 2 logic_net 2 logic_typespec 1 -module 4 +module_inst 4 range 3 ref_obj 2 var_select 2 @@ -120,7 +120,7 @@ design 1 indexed_part_select 3 logic_net 2 logic_typespec 1 -module 4 +module_inst 4 range 3 ref_obj 3 var_select 3 @@ -138,7 +138,7 @@ design: (work@dut) |vpiElaborated:1 |vpiName:work@dut |uhdmallModules: -\_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/WireUnpacked/dut.sv, line:1:1, endln:4:10 +\_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/WireUnpacked/dut.sv, line:1:1, endln:4:10 |vpiParent: \_design: (work@dut) |vpiFullName:work@dut @@ -146,14 +146,14 @@ design: (work@dut) |vpiNet: \_logic_net: (work@dut.read_buf), line:2:12, endln:2:20 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/WireUnpacked/dut.sv, line:1:1, endln:4:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/WireUnpacked/dut.sv, line:1:1, endln:4:10 |vpiName:read_buf |vpiFullName:work@dut.read_buf |vpiNetType:1 |vpiContAssign: \_cont_assign: , line:3:8, endln:3:32 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/WireUnpacked/dut.sv, line:1:1, endln:4:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/WireUnpacked/dut.sv, line:1:1, endln:4:10 |vpiRhs: \_constant: , line:3:28, endln:3:32 |vpiParent: @@ -195,14 +195,14 @@ design: (work@dut) |UINT:2 |vpiConstType:9 |uhdmtopModules: -\_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/WireUnpacked/dut.sv, line:1:1, endln:4:10 +\_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/WireUnpacked/dut.sv, line:1:1, endln:4:10 |vpiName:work@dut |vpiDefName:work@dut |vpiTop:1 |vpiArrayNet: \_array_net: (work@dut.read_buf), line:2:12, endln:2:20 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/WireUnpacked/dut.sv, line:1:1, endln:4:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/WireUnpacked/dut.sv, line:1:1, endln:4:10 |vpiSize:101 |vpiName:read_buf |vpiFullName:work@dut.read_buf @@ -254,7 +254,7 @@ design: (work@dut) |vpiContAssign: \_cont_assign: , line:3:8, endln:3:32 |vpiParent: - \_module: work@dut (work@dut), file:${SURELOG_DIR}/tests/WireUnpacked/dut.sv, line:1:1, endln:4:10 + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/WireUnpacked/dut.sv, line:1:1, endln:4:10 |vpiRhs: \_constant: , line:3:28, endln:3:32 |vpiLhs: diff --git a/tests/XValue/XValue.log b/tests/XValue/XValue.log index 24fa155743..81e175a826 100644 --- a/tests/XValue/XValue.log +++ b/tests/XValue/XValue.log @@ -114,7 +114,7 @@ enum_const 2 enum_typespec 1 logic_net 4 logic_typespec 7 -module 5 +module_inst 5 port 4 range 5 ref_obj 8 @@ -129,7 +129,7 @@ enum_const 2 enum_typespec 1 logic_net 4 logic_typespec 7 -module 5 +module_inst 5 port 6 range 5 ref_obj 11 @@ -147,17 +147,17 @@ design: (work@top) |vpiElaborated:1 |vpiName:work@top |uhdmallModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/XValue/dut.sv, line:1:1, endln:8:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/XValue/dut.sv, line:1:1, endln:8:10 |vpiParent: \_design: (work@top) |vpiFullName:work@top |vpiTypedef: \_enum_typespec: (dfi_cmd_e), line:2:4, endln:5:16 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/XValue/dut.sv, line:1:1, endln:8:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/XValue/dut.sv, line:1:1, endln:8:10 |vpiName:dfi_cmd_e |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/XValue/dut.sv, line:1:1, endln:8:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/XValue/dut.sv, line:1:1, endln:8:10 |vpiBaseTypespec: \_logic_typespec: , line:2:17, endln:2:28 |vpiRange: @@ -194,21 +194,21 @@ design: (work@top) |vpiNet: \_logic_net: (work@top.clk), line:1:24, endln:1:27 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/XValue/dut.sv, line:1:1, endln:8:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/XValue/dut.sv, line:1:1, endln:8:10 |vpiName:clk |vpiFullName:work@top.clk |vpiNetType:36 |vpiNet: \_logic_net: (work@top.o), line:1:47, endln:1:48 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/XValue/dut.sv, line:1:1, endln:8:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/XValue/dut.sv, line:1:1, endln:8:10 |vpiName:o |vpiFullName:work@top.o |vpiNetType:36 |vpiPort: \_port: (clk), line:1:24, endln:1:27 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/XValue/dut.sv, line:1:1, endln:8:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/XValue/dut.sv, line:1:1, endln:8:10 |vpiName:clk |vpiDirection:1 |vpiLowConn: @@ -220,7 +220,7 @@ design: (work@top) |vpiPort: \_port: (o), line:1:47, endln:1:48 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/XValue/dut.sv, line:1:1, endln:8:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/XValue/dut.sv, line:1:1, endln:8:10 |vpiName:o |vpiDirection:2 |vpiLowConn: @@ -250,7 +250,7 @@ design: (work@top) |vpiContAssign: \_cont_assign: , line:7:11, endln:7:23 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/XValue/dut.sv, line:1:1, endln:8:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/XValue/dut.sv, line:1:1, endln:8:10 |vpiRhs: \_ref_obj: (work@top.DESELECT), line:7:15, endln:7:23 |vpiParent: @@ -268,7 +268,7 @@ design: (work@top) |vpiActual: \_logic_net: (work@top.o), line:1:47, endln:1:48 |uhdmtopModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/tests/XValue/dut.sv, line:1:1, endln:8:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/XValue/dut.sv, line:1:1, endln:8:10 |vpiName:work@top |vpiTypedef: \_enum_typespec: (dfi_cmd_e), line:2:4, endln:5:16 @@ -277,7 +277,7 @@ design: (work@top) |vpiNet: \_logic_net: (work@top.clk), line:1:24, endln:1:27 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/XValue/dut.sv, line:1:1, endln:8:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/XValue/dut.sv, line:1:1, endln:8:10 |vpiTypespec: \_logic_typespec: , line:1:18, endln:1:23 |vpiName:clk @@ -286,7 +286,7 @@ design: (work@top) |vpiNet: \_logic_net: (work@top.o), line:1:47, endln:1:48 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/XValue/dut.sv, line:1:1, endln:8:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/XValue/dut.sv, line:1:1, endln:8:10 |vpiTypespec: \_logic_typespec: , line:1:36, endln:1:46 |vpiRange: @@ -314,7 +314,7 @@ design: (work@top) |vpiPort: \_port: (clk), line:1:24, endln:1:27 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/XValue/dut.sv, line:1:1, endln:8:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/XValue/dut.sv, line:1:1, endln:8:10 |vpiName:clk |vpiDirection:1 |vpiLowConn: @@ -328,11 +328,11 @@ design: (work@top) |vpiTypedef: \_logic_typespec: , line:1:18, endln:1:23 |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/XValue/dut.sv, line:1:1, endln:8:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/XValue/dut.sv, line:1:1, endln:8:10 |vpiPort: \_port: (o), line:1:47, endln:1:48 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/XValue/dut.sv, line:1:1, endln:8:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/XValue/dut.sv, line:1:1, endln:8:10 |vpiName:o |vpiDirection:2 |vpiLowConn: @@ -366,11 +366,11 @@ design: (work@top) |UINT:0 |vpiConstType:9 |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/XValue/dut.sv, line:1:1, endln:8:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/XValue/dut.sv, line:1:1, endln:8:10 |vpiContAssign: \_cont_assign: , line:7:11, endln:7:23 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/tests/XValue/dut.sv, line:1:1, endln:8:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/XValue/dut.sv, line:1:1, endln:8:10 |vpiRhs: \_constant: |vpiParent: diff --git a/third_party/tests/AVLMM/AVLMM.log b/third_party/tests/AVLMM/AVLMM.log index 4e044136ad..25f751e3f1 100644 --- a/third_party/tests/AVLMM/AVLMM.log +++ b/third_party/tests/AVLMM/AVLMM.log @@ -92,7 +92,7 @@ logic_net 20 logic_typespec 23 logic_var 9 method_func_call 13 -module 12 +module_inst 12 named_event 1 operation 116 package 2 diff --git a/third_party/tests/AmiqEth/AmiqEth.log b/third_party/tests/AmiqEth/AmiqEth.log index b7b169b84e..64967250c0 100644 --- a/third_party/tests/AmiqEth/AmiqEth.log +++ b/third_party/tests/AmiqEth/AmiqEth.log @@ -1666,7 +1666,7 @@ logic_var 136 long_int_typespec 256 long_int_var 26 method_func_call 29282 -module 68 +module_inst 68 named_begin 24 named_event 17 named_fork 17 diff --git a/third_party/tests/AmiqSimpleTestSuite/AmiqSimpleTestSuite.log b/third_party/tests/AmiqSimpleTestSuite/AmiqSimpleTestSuite.log index 2ff213b679..26bd4288a7 100644 --- a/third_party/tests/AmiqSimpleTestSuite/AmiqSimpleTestSuite.log +++ b/third_party/tests/AmiqSimpleTestSuite/AmiqSimpleTestSuite.log @@ -918,7 +918,7 @@ indexed_part_select 121 initial 8 int_typespec 7110 int_var 2733 -interface 14 +interface_inst 14 interface_typespec 3 io_decl 13135 logic_net 702 @@ -927,7 +927,7 @@ logic_var 92 long_int_typespec 179 long_int_var 15 method_func_call 18141 -module 40 +module_inst 40 named_begin 18 named_event 8 named_fork 7 diff --git a/third_party/tests/ApbSlave/ApbSlave.log b/third_party/tests/ApbSlave/ApbSlave.log index 0f496af25e..395f8559aa 100644 --- a/third_party/tests/ApbSlave/ApbSlave.log +++ b/third_party/tests/ApbSlave/ApbSlave.log @@ -111,7 +111,7 @@ logic_net 49 logic_typespec 47 logic_var 11 method_func_call 67 -module 12 +module_inst 12 named_begin 4 operation 71 package 5 diff --git a/third_party/tests/AzadiRTL/AzadiRTL.log b/third_party/tests/AzadiRTL/AzadiRTL.log index d1dab80c41..90cf25b8d3 100644 --- a/third_party/tests/AzadiRTL/AzadiRTL.log +++ b/third_party/tests/AzadiRTL/AzadiRTL.log @@ -21774,7 +21774,7 @@ logic_typespec 98026 logic_var 3485 long_int_typespec 6 long_int_var 2 -module 3271 +module_inst 3271 named_begin 99 operation 78205 package 41 diff --git a/third_party/tests/BuildOVMPkg/BuildOVMPkg.log b/third_party/tests/BuildOVMPkg/BuildOVMPkg.log index 104d3cf861..4091d98937 100644 --- a/third_party/tests/BuildOVMPkg/BuildOVMPkg.log +++ b/third_party/tests/BuildOVMPkg/BuildOVMPkg.log @@ -866,7 +866,7 @@ io_decl 3530 logic_typespec 83 logic_var 33 method_func_call 3182 -module 16 +module_inst 16 named_event 6 named_fork 4 operation 4767 diff --git a/third_party/tests/BuildUVMPkg/BuildUVMPkg.log b/third_party/tests/BuildUVMPkg/BuildUVMPkg.log index 92e2022b94..1f799c0076 100644 --- a/third_party/tests/BuildUVMPkg/BuildUVMPkg.log +++ b/third_party/tests/BuildUVMPkg/BuildUVMPkg.log @@ -735,7 +735,7 @@ logic_var 38 long_int_typespec 99 long_int_var 7 method_func_call 7996 -module 23 +module_inst 23 named_begin 6 named_event 8 named_fork 3 diff --git a/third_party/tests/Compl1001/Compl1001.log b/third_party/tests/Compl1001/Compl1001.log index bd741faf02..9a8f25b289 100644 --- a/third_party/tests/Compl1001/Compl1001.log +++ b/third_party/tests/Compl1001/Compl1001.log @@ -46,7 +46,7 @@ io_decl 11 logic_net 512 logic_typespec 256 logic_var 1 -module 3 +module_inst 3 operation 4233 package 2 range 512 diff --git a/third_party/tests/CoresSweRV/CoresSweRV.log b/third_party/tests/CoresSweRV/CoresSweRV.log index 1220f8aa05..3d99adaf7c 100644 --- a/third_party/tests/CoresSweRV/CoresSweRV.log +++ b/third_party/tests/CoresSweRV/CoresSweRV.log @@ -4863,7 +4863,7 @@ logic_var 4305 long_int_typespec 99 long_int_var 7 method_func_call 7996 -module 7763 +module_inst 7763 named_begin 34 named_event 8 named_fork 3 @@ -4966,7 +4966,7 @@ long_int_typespec 99 long_int_var 139 method_func_call 45468 method_task_call 3554 -module 7763 +module_inst 7763 named_begin 43 named_event 50 named_fork 10 diff --git a/third_party/tests/CoresSweRVMP/CoresSweRVMP.log b/third_party/tests/CoresSweRVMP/CoresSweRVMP.log index 1991d97921..fa285b2df1 100644 --- a/third_party/tests/CoresSweRVMP/CoresSweRVMP.log +++ b/third_party/tests/CoresSweRVMP/CoresSweRVMP.log @@ -2,11 +2,10 @@ [WRN:CM0010] Command line argument "-Wno-UNOPTFLAT" ignored. -Running: cd ${SURELOG_DIR}/build/regression/CoresSweRVMP/slpp_all/mp_parser; cmake -G "Unix Makefiles" .; make -j 16 +Running: cd ${SURELOG_DIR}/build/regression/CoresSweRVMP/slpp_all/mp_parser; cmake -G "Unix Makefiles" .; make -j 2 -- Configuring done -- Generating done -- Build files have been written to: ${SURELOG_DIR}/build/regression/CoresSweRVMP/slpp_all/mp_parser -Scanning dependencies of target Parse [100%] Generating preprocessing [100%] Built target Parse Surelog preproc status: 0 @@ -114,27 +113,12 @@ Surelog preproc status: 0 [INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/CoresSweRVMP/design/lib/axi4_to_ahb.sv". -Running: cd ${SURELOG_DIR}/build/regression/CoresSweRVMP/slpp_all/mp_preprocess; cmake -G "Unix Makefiles" .; make -j 16 +Running: cd ${SURELOG_DIR}/build/regression/CoresSweRVMP/slpp_all/mp_preprocess; cmake -G "Unix Makefiles" .; make -j 2 -- Configuring done -- Generating done -- Build files have been written to: ${SURELOG_DIR}/build/regression/CoresSweRVMP/slpp_all/mp_preprocess -Scanning dependencies of target Parse -[ 31%] Generating 5_lsu_bus_buffer.sv -[ 31%] Generating 4_dec_tlu_ctl.sv -[ 31%] Generating 1_lsu_stbuf.sv -[ 37%] Generating 8_ifu_aln_ctl.sv -[ 37%] Generating 3_rvjtag_tap.sv -[ 31%] Generating 6_dbg.sv -[ 43%] Generating 9_tb_top.sv -[ 50%] Generating 7_axi4_to_ahb.sv -[ 56%] Generating 10_lsu_bus_intf.sv -[ 62%] Generating 11_ifu_bp_ctl.sv -[ 68%] Generating 12_beh_lib.sv -[ 75%] Generating 14_mem_lib.sv -[ 81%] Generating 13_ifu_mem_ctl.sv -[ 87%] Generating 15_exu.sv -[ 93%] Generating 2_ahb_to_axi4.sv -[100%] Generating 16_dec_decode_ctl.sv +[ 50%] Generating 1_axi4_to_ahb.sv +[100%] Generating 2_mem_lib.sv [100%] Built target Parse Surelog parsing status: 0 [INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/UVM/1800.2-2017-1.0/src/uvm_pkg.sv". @@ -4894,7 +4878,7 @@ logic_var 4305 long_int_typespec 99 long_int_var 7 method_func_call 7996 -module 7763 +module_inst 7763 named_begin 34 named_event 8 named_fork 3 @@ -4997,7 +4981,7 @@ long_int_typespec 99 long_int_var 139 method_func_call 45468 method_task_call 3554 -module 7763 +module_inst 7763 named_begin 43 named_event 50 named_fork 10 diff --git a/third_party/tests/Driver/Driver.log b/third_party/tests/Driver/Driver.log index ab84a8a9e4..180b7b0537 100644 --- a/third_party/tests/Driver/Driver.log +++ b/third_party/tests/Driver/Driver.log @@ -842,7 +842,7 @@ int_typespec 2652 int_var 1181 integer_typespec 5 integer_var 5 -interface 3 +interface_inst 3 interface_typespec 1 io_decl 6955 logic_net 342 @@ -851,7 +851,7 @@ logic_var 42 long_int_typespec 99 long_int_var 7 method_func_call 8073 -module 28 +module_inst 28 named_begin 8 named_event 8 named_fork 5 diff --git a/third_party/tests/Earlgrey_0_1/sim-icarus/Earlgrey_0_1.log b/third_party/tests/Earlgrey_0_1/sim-icarus/Earlgrey_0_1.log index c71b44ae49..e42df3f02f 100644 --- a/third_party/tests/Earlgrey_0_1/sim-icarus/Earlgrey_0_1.log +++ b/third_party/tests/Earlgrey_0_1/sim-icarus/Earlgrey_0_1.log @@ -12470,7 +12470,7 @@ io_decl 253 logic_net 27105 logic_typespec 61905 logic_var 12549 -module 6217 +module_inst 6217 named_begin 200 operation 99245 package 119 diff --git a/third_party/tests/Earlgrey_Verilator_01_05_21/sim-icarus/Earlgrey_Verilator_01_05_21.log b/third_party/tests/Earlgrey_Verilator_01_05_21/sim-icarus/Earlgrey_Verilator_01_05_21.log index 631bcf5ed7..d21cc539f6 100644 --- a/third_party/tests/Earlgrey_Verilator_01_05_21/sim-icarus/Earlgrey_Verilator_01_05_21.log +++ b/third_party/tests/Earlgrey_Verilator_01_05_21/sim-icarus/Earlgrey_Verilator_01_05_21.log @@ -27907,14 +27907,14 @@ int_typespec 67468 int_var 427 integer_typespec 1739 integer_var 8 -interface 10 +interface_inst 10 interface_typespec 1 io_decl 420 logic_net 68633 logic_typespec 214402 logic_var 26597 method_func_call 1 -module 22098 +module_inst 22098 named_begin 522 operation 222418 package 212 diff --git a/third_party/tests/Earlgrey_Verilator_0_1/sim-verilator/Earlgrey_Verilator_0_1.log b/third_party/tests/Earlgrey_Verilator_0_1/sim-verilator/Earlgrey_Verilator_0_1.log index 8d87e2a57d..2a2fae90dc 100644 --- a/third_party/tests/Earlgrey_Verilator_0_1/sim-verilator/Earlgrey_Verilator_0_1.log +++ b/third_party/tests/Earlgrey_Verilator_0_1/sim-verilator/Earlgrey_Verilator_0_1.log @@ -11649,12 +11649,12 @@ int_typespec 21312 int_var 211 integer_typespec 416 integer_var 1 -interface 1 +interface_inst 1 io_decl 344 logic_net 26804 logic_typespec 62156 logic_var 12189 -module 5801 +module_inst 5801 named_begin 192 operation 99931 package 122 diff --git a/third_party/tests/Ibex/Ibex.log b/third_party/tests/Ibex/Ibex.log index 139bcc231a..7b80f72957 100644 --- a/third_party/tests/Ibex/Ibex.log +++ b/third_party/tests/Ibex/Ibex.log @@ -1615,7 +1615,7 @@ initial 9 int_typespec 26295 int_var 6019 integer_typespec 41 -interface 24 +interface_inst 24 interface_typespec 15 io_decl 25063 logic_net 3457 @@ -1624,7 +1624,7 @@ logic_var 902 long_int_typespec 339 long_int_var 31 method_func_call 37796 -module 176 +module_inst 176 named_begin 76 named_event 8 named_fork 20 diff --git a/third_party/tests/IbexGoogle/IbexGoogle.log b/third_party/tests/IbexGoogle/IbexGoogle.log index 057e0e06df..82c8ab4f2c 100644 --- a/third_party/tests/IbexGoogle/IbexGoogle.log +++ b/third_party/tests/IbexGoogle/IbexGoogle.log @@ -987,7 +987,7 @@ logic_var 71 long_int_typespec 179 long_int_var 15 method_func_call 18998 -module 37 +module_inst 37 named_begin 18 named_event 8 named_fork 7 diff --git a/third_party/tests/IncompTitan/IncompTitan.log b/third_party/tests/IncompTitan/IncompTitan.log index 20cc9adfe1..b40c64867c 100644 --- a/third_party/tests/IncompTitan/IncompTitan.log +++ b/third_party/tests/IncompTitan/IncompTitan.log @@ -10687,7 +10687,7 @@ io_decl 273 logic_net 35463 logic_typespec 92983 logic_var 12074 -module 10373 +module_inst 10373 named_begin 108 operation 100397 package 140 diff --git a/third_party/tests/MiniAmiq/MiniAmiq.log b/third_party/tests/MiniAmiq/MiniAmiq.log index 9ea62c36e0..00a9a6e571 100644 --- a/third_party/tests/MiniAmiq/MiniAmiq.log +++ b/third_party/tests/MiniAmiq/MiniAmiq.log @@ -847,7 +847,7 @@ indexed_part_select 81 initial 1 int_typespec 4407 int_var 1985 -interface 1 +interface_inst 1 interface_typespec 1 io_decl 10137 logic_net 57 @@ -856,7 +856,7 @@ logic_var 55 long_int_typespec 139 long_int_var 11 method_func_call 13243 -module 26 +module_inst 26 named_begin 12 named_event 8 named_fork 5 diff --git a/third_party/tests/Monitor/Monitor.log b/third_party/tests/Monitor/Monitor.log index 2367db26fd..1b6aa98e4f 100644 --- a/third_party/tests/Monitor/Monitor.log +++ b/third_party/tests/Monitor/Monitor.log @@ -912,7 +912,7 @@ int_typespec 4742 int_var 2008 integer_typespec 5 integer_var 5 -interface 4 +interface_inst 4 interface_typespec 2 io_decl 10158 logic_net 424 @@ -921,7 +921,7 @@ logic_var 61 long_int_typespec 139 long_int_var 11 method_func_call 13291 -module 31 +module_inst 31 named_begin 14 named_event 8 named_fork 7 diff --git a/third_party/tests/NyuziProcessor/NyuziProcessor.log b/third_party/tests/NyuziProcessor/NyuziProcessor.log index 429b06cd04..246bd84b8c 100644 --- a/third_party/tests/NyuziProcessor/NyuziProcessor.log +++ b/third_party/tests/NyuziProcessor/NyuziProcessor.log @@ -22,125 +22,125 @@ [INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/testbench/sim_sdram.sv". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/scoreboard.sv". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/sram_1r1w.sv". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/l2_axi_bus_interface.sv". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/oh_to_idx.sv". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/l1_store_queue.sv". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/l2_cache_tag_stage.sv". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/nyuzi.sv". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/writeback_stage.sv". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/control_registers.sv". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/cache_lru.sv". [INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/fp_execute_stage5.sv". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/jtag_tap_controller.sv". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/rr_arbiter.sv". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/l2_cache_pending_miss_cam.sv". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/sram_2r1w.sv". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/oh_to_idx.sv". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/fp_execute_stage4.sv". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/l1_l2_interface.sv". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/operand_fetch_stage.sv". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/ifetch_tag_stage.sv". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/sync_fifo.sv". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/reciprocal_rom.sv". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/control_registers.sv". [INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/tlb.sv". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/fp_execute_stage2.sv". - -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/core.sv". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/l2_axi_bus_interface.sv". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/thread_select_stage.sv". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/jtag_tap_controller.sv". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/dcache_data_stage.sv". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/int_execute_stage.sv". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/cam.sv". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/fp_execute_stage2.sv". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/l2_cache_read_stage.sv". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/l2_cache_arb_stage.sv". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/rr_arbiter.sv". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/thread_select_stage.sv". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/synchronizer.sv". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/on_chip_debugger.sv". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/fp_execute_stage1.sv". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/dcache_tag_stage.sv". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/fp_execute_stage4.sv". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/l1_l2_interface.sv". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/l2_cache.sv". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/core.sv". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/dcache_tag_stage.sv". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/l2_cache_update_stage.sv". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/fp_execute_stage3.sv". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/cam.sv". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/sram_2r1w.sv". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/l2_cache.sv". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/l2_cache_arb_stage.sv". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/l1_load_miss_queue.sv". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/operand_fetch_stage.sv". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/reciprocal_rom.sv". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/l1_load_miss_queue.sv". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/ifetch_data_stage.sv". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/sram_1r1w.sv". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/fp_execute_stage3.sv". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/l2_cache_tag_stage.sv". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/l2_cache_pending_miss_cam.sv". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/instruction_decode_stage.sv". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/l2_cache_read_stage.sv". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/ifetch_data_stage.sv". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/synchronizer.sv". [INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/io_request_queue.sv". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/performance_counters.sv". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/dcache_data_stage.sv". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/on_chip_debugger.sv". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/l1_store_queue.sv". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/writeback_stage.sv". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/idx_to_oh.sv". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/l2_cache_update_stage.sv". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/fp_execute_stage1.sv". + +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/nyuzi.sv". [INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/io_interconnect.sv". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/sync_fifo.sv". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/scoreboard.sv". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/idx_to_oh.sv". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/performance_counters.sv". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/cache_lru.sv". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/instruction_decode_stage.sv". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/int_execute_stage.sv". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/ifetch_tag_stage.sv". [INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/fpga/common/async_fifo.sv". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/fpga/common/gpio_controller.sv". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/fpga/common/logic_analyzer.sv". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/fpga/common/axi_sram.sv". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/fpga/common/uart_receive.sv". [INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/fpga/common/spi_controller.sv". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/fpga/common/logic_analyzer.sv". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/fpga/common/axi_sram.sv". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/fpga/common/axi_async_bridge.sv". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/fpga/common/gpio_controller.sv". [INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/fpga/common/vga_sequencer.sv". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/fpga/common/vga_controller.sv". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/fpga/common/sdram_controller.sv". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/fpga/common/uart_receive.sv". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/fpga/common/timer.sv". + +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/fpga/common/axi_async_bridge.sv". [INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/fpga/common/axi_interconnect.sv". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/fpga/common/axi_rom.sv". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/fpga/common/vga_controller.sv". [INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/fpga/common/uart.sv". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/fpga/common/timer.sv". - -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/fpga/common/ps2_controller.sv". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/fpga/common/axi_rom.sv". [INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/fpga/common/uart_transmit.sv". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/fpga/common/sdram_controller.sv". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/fpga/common/ps2_controller.sv". [INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/testbench/soc_tb.sv". @@ -158,125 +158,125 @@ [INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/testbench/sim_sdram.sv". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/scoreboard.sv". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/sram_1r1w.sv". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/l2_axi_bus_interface.sv". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/oh_to_idx.sv". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/l1_store_queue.sv". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/l2_cache_tag_stage.sv". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/nyuzi.sv". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/writeback_stage.sv". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/control_registers.sv". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/cache_lru.sv". [INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/fp_execute_stage5.sv". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/jtag_tap_controller.sv". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/rr_arbiter.sv". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/l2_cache_pending_miss_cam.sv". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/sram_2r1w.sv". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/oh_to_idx.sv". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/fp_execute_stage4.sv". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/l1_l2_interface.sv". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/operand_fetch_stage.sv". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/ifetch_tag_stage.sv". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/sync_fifo.sv". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/reciprocal_rom.sv". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/control_registers.sv". [INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/tlb.sv". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/fp_execute_stage2.sv". - -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/core.sv". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/l2_axi_bus_interface.sv". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/thread_select_stage.sv". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/jtag_tap_controller.sv". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/dcache_data_stage.sv". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/int_execute_stage.sv". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/cam.sv". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/fp_execute_stage2.sv". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/l2_cache_read_stage.sv". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/l2_cache_arb_stage.sv". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/rr_arbiter.sv". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/thread_select_stage.sv". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/synchronizer.sv". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/on_chip_debugger.sv". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/fp_execute_stage1.sv". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/dcache_tag_stage.sv". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/fp_execute_stage4.sv". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/l1_l2_interface.sv". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/l2_cache.sv". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/core.sv". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/dcache_tag_stage.sv". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/l2_cache_update_stage.sv". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/fp_execute_stage3.sv". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/cam.sv". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/sram_2r1w.sv". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/l2_cache.sv". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/l2_cache_arb_stage.sv". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/l1_load_miss_queue.sv". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/operand_fetch_stage.sv". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/reciprocal_rom.sv". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/l1_load_miss_queue.sv". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/ifetch_data_stage.sv". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/sram_1r1w.sv". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/fp_execute_stage3.sv". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/l2_cache_tag_stage.sv". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/l2_cache_pending_miss_cam.sv". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/instruction_decode_stage.sv". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/l2_cache_read_stage.sv". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/ifetch_data_stage.sv". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/synchronizer.sv". [INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/io_request_queue.sv". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/performance_counters.sv". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/dcache_data_stage.sv". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/on_chip_debugger.sv". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/l1_store_queue.sv". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/writeback_stage.sv". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/idx_to_oh.sv". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/l2_cache_update_stage.sv". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/fp_execute_stage1.sv". + +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/nyuzi.sv". [INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/io_interconnect.sv". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/sync_fifo.sv". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/scoreboard.sv". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/idx_to_oh.sv". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/performance_counters.sv". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/cache_lru.sv". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/instruction_decode_stage.sv". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/int_execute_stage.sv". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/ifetch_tag_stage.sv". [INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/fpga/common/async_fifo.sv". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/fpga/common/gpio_controller.sv". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/fpga/common/logic_analyzer.sv". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/fpga/common/axi_sram.sv". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/fpga/common/uart_receive.sv". [INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/fpga/common/spi_controller.sv". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/fpga/common/logic_analyzer.sv". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/fpga/common/axi_sram.sv". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/fpga/common/axi_async_bridge.sv". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/fpga/common/gpio_controller.sv". [INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/fpga/common/vga_sequencer.sv". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/fpga/common/vga_controller.sv". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/fpga/common/sdram_controller.sv". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/fpga/common/uart_receive.sv". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/fpga/common/timer.sv". + +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/fpga/common/axi_async_bridge.sv". [INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/fpga/common/axi_interconnect.sv". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/fpga/common/axi_rom.sv". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/fpga/common/vga_controller.sv". [INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/fpga/common/uart.sv". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/fpga/common/timer.sv". - -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/fpga/common/ps2_controller.sv". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/fpga/common/axi_rom.sv". [INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/fpga/common/uart_transmit.sv". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/fpga/common/sdram_controller.sv". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/fpga/common/ps2_controller.sv". [INF:CM0029] Using global timescale: "10ps/10ps". @@ -535,142 +535,142 @@ ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/testbench/trace_logger.sv:22:1: previous definition. [ERR:CP0329] ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/testbench/soc_tb.sv:22:1: Multiply defined package: "defines", - ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/scoreboard.sv:22:1: previous definition. - -[ERR:CP0329] ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/testbench/soc_tb.sv:22:1: Multiply defined package: "defines", - ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/l2_axi_bus_interface.sv:22:1: previous definition. + ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/sram_1r1w.sv:22:1: previous definition. [ERR:CP0329] ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/testbench/soc_tb.sv:22:1: Multiply defined package: "defines", - ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/l1_store_queue.sv:22:1: previous definition. + ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/l2_cache_tag_stage.sv:22:1: previous definition. [ERR:CP0329] ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/testbench/soc_tb.sv:22:1: Multiply defined package: "defines", - ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/nyuzi.sv:22:1: previous definition. + ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/writeback_stage.sv:22:1: previous definition. [ERR:CP0329] ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/testbench/soc_tb.sv:22:1: Multiply defined package: "defines", - ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/control_registers.sv:22:1: previous definition. + ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/cache_lru.sv:22:1: previous definition. [ERR:CP0329] ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/testbench/soc_tb.sv:22:1: Multiply defined package: "defines", ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/fp_execute_stage5.sv:22:1: previous definition. [ERR:CP0329] ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/testbench/soc_tb.sv:22:1: Multiply defined package: "defines", - ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/jtag_tap_controller.sv:22:1: previous definition. + ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/fp_execute_stage4.sv:22:1: previous definition. [ERR:CP0329] ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/testbench/soc_tb.sv:22:1: Multiply defined package: "defines", - ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/l2_cache_pending_miss_cam.sv:22:1: previous definition. + ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/operand_fetch_stage.sv:22:1: previous definition. [ERR:CP0329] ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/testbench/soc_tb.sv:22:1: Multiply defined package: "defines", - ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/l1_l2_interface.sv:22:1: previous definition. + ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/sync_fifo.sv:22:1: previous definition. [ERR:CP0329] ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/testbench/soc_tb.sv:22:1: Multiply defined package: "defines", - ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/ifetch_tag_stage.sv:22:1: previous definition. + ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/control_registers.sv:22:1: previous definition. [ERR:CP0329] ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/testbench/soc_tb.sv:22:1: Multiply defined package: "defines", ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/tlb.sv:22:1: previous definition. [ERR:CP0329] ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/testbench/soc_tb.sv:22:1: Multiply defined package: "defines", - ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/fp_execute_stage2.sv:22:1: previous definition. + ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/l2_axi_bus_interface.sv:22:1: previous definition. [ERR:CP0329] ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/testbench/soc_tb.sv:22:1: Multiply defined package: "defines", - ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/core.sv:22:1: previous definition. + ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/jtag_tap_controller.sv:22:1: previous definition. [ERR:CP0329] ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/testbench/soc_tb.sv:22:1: Multiply defined package: "defines", - ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/thread_select_stage.sv:22:1: previous definition. + ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/int_execute_stage.sv:22:1: previous definition. [ERR:CP0329] ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/testbench/soc_tb.sv:22:1: Multiply defined package: "defines", - ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/dcache_data_stage.sv:22:1: previous definition. + ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/fp_execute_stage2.sv:22:1: previous definition. [ERR:CP0329] ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/testbench/soc_tb.sv:22:1: Multiply defined package: "defines", - ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/cam.sv:22:1: previous definition. + ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/l2_cache_arb_stage.sv:22:1: previous definition. [ERR:CP0329] ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/testbench/soc_tb.sv:22:1: Multiply defined package: "defines", - ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/l2_cache_read_stage.sv:22:1: previous definition. + ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/thread_select_stage.sv:22:1: previous definition. [ERR:CP0329] ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/testbench/soc_tb.sv:22:1: Multiply defined package: "defines", - ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/fp_execute_stage1.sv:22:1: previous definition. + ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/on_chip_debugger.sv:22:1: previous definition. [ERR:CP0329] ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/testbench/soc_tb.sv:22:1: Multiply defined package: "defines", - ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/fp_execute_stage4.sv:22:1: previous definition. + ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/dcache_tag_stage.sv:22:1: previous definition. [ERR:CP0329] ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/testbench/soc_tb.sv:22:1: Multiply defined package: "defines", - ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/l2_cache.sv:22:1: previous definition. + ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/l1_l2_interface.sv:22:1: previous definition. [ERR:CP0329] ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/testbench/soc_tb.sv:22:1: Multiply defined package: "defines", - ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/dcache_tag_stage.sv:22:1: previous definition. + ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/core.sv:22:1: previous definition. [ERR:CP0329] ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/testbench/soc_tb.sv:22:1: Multiply defined package: "defines", - ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/fp_execute_stage3.sv:22:1: previous definition. + ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/l2_cache_update_stage.sv:22:1: previous definition. [ERR:CP0329] ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/testbench/soc_tb.sv:22:1: Multiply defined package: "defines", - ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/l2_cache_arb_stage.sv:22:1: previous definition. + ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/cam.sv:22:1: previous definition. [ERR:CP0329] ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/testbench/soc_tb.sv:22:1: Multiply defined package: "defines", - ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/operand_fetch_stage.sv:22:1: previous definition. + ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/l2_cache.sv:22:1: previous definition. [ERR:CP0329] ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/testbench/soc_tb.sv:22:1: Multiply defined package: "defines", ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/l1_load_miss_queue.sv:22:1: previous definition. [ERR:CP0329] ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/testbench/soc_tb.sv:22:1: Multiply defined package: "defines", - ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/sram_1r1w.sv:22:1: previous definition. + ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/ifetch_data_stage.sv:22:1: previous definition. [ERR:CP0329] ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/testbench/soc_tb.sv:22:1: Multiply defined package: "defines", - ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/l2_cache_tag_stage.sv:22:1: previous definition. + ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/fp_execute_stage3.sv:22:1: previous definition. [ERR:CP0329] ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/testbench/soc_tb.sv:22:1: Multiply defined package: "defines", - ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/instruction_decode_stage.sv:22:1: previous definition. + ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/l2_cache_pending_miss_cam.sv:22:1: previous definition. [ERR:CP0329] ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/testbench/soc_tb.sv:22:1: Multiply defined package: "defines", - ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/ifetch_data_stage.sv:22:1: previous definition. + ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/l2_cache_read_stage.sv:22:1: previous definition. [ERR:CP0329] ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/testbench/soc_tb.sv:22:1: Multiply defined package: "defines", ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/io_request_queue.sv:22:1: previous definition. [ERR:CP0329] ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/testbench/soc_tb.sv:22:1: Multiply defined package: "defines", - ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/on_chip_debugger.sv:22:1: previous definition. + ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/dcache_data_stage.sv:22:1: previous definition. [ERR:CP0329] ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/testbench/soc_tb.sv:22:1: Multiply defined package: "defines", - ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/writeback_stage.sv:22:1: previous definition. + ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/l1_store_queue.sv:22:1: previous definition. [ERR:CP0329] ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/testbench/soc_tb.sv:22:1: Multiply defined package: "defines", - ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/l2_cache_update_stage.sv:22:1: previous definition. + ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/fp_execute_stage1.sv:22:1: previous definition. + +[ERR:CP0329] ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/testbench/soc_tb.sv:22:1: Multiply defined package: "defines", + ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/nyuzi.sv:22:1: previous definition. [ERR:CP0329] ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/testbench/soc_tb.sv:22:1: Multiply defined package: "defines", ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/io_interconnect.sv:22:1: previous definition. [ERR:CP0329] ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/testbench/soc_tb.sv:22:1: Multiply defined package: "defines", - ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/sync_fifo.sv:22:1: previous definition. + ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/scoreboard.sv:22:1: previous definition. [ERR:CP0329] ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/testbench/soc_tb.sv:22:1: Multiply defined package: "defines", - ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/cache_lru.sv:22:1: previous definition. + ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/instruction_decode_stage.sv:22:1: previous definition. [ERR:CP0329] ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/testbench/soc_tb.sv:22:1: Multiply defined package: "defines", - ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/int_execute_stage.sv:22:1: previous definition. + ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/ifetch_tag_stage.sv:22:1: previous definition. [ERR:CP0329] ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/testbench/soc_tb.sv:22:1: Multiply defined package: "defines", ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/fpga/common/async_fifo.sv:22:1: previous definition. [ERR:CP0329] ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/testbench/soc_tb.sv:22:1: Multiply defined package: "defines", - ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/fpga/common/gpio_controller.sv:22:1: previous definition. + ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/fpga/common/spi_controller.sv:22:1: previous definition. [ERR:CP0329] ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/testbench/soc_tb.sv:22:1: Multiply defined package: "defines", ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/fpga/common/axi_sram.sv:22:1: previous definition. [ERR:CP0329] ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/testbench/soc_tb.sv:22:1: Multiply defined package: "defines", - ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/fpga/common/spi_controller.sv:22:1: previous definition. + ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/fpga/common/gpio_controller.sv:22:1: previous definition. [ERR:CP0329] ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/testbench/soc_tb.sv:22:1: Multiply defined package: "defines", - ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/fpga/common/vga_controller.sv:22:1: previous definition. + ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/fpga/common/sdram_controller.sv:22:1: previous definition. [ERR:CP0329] ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/testbench/soc_tb.sv:22:1: Multiply defined package: "defines", ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/fpga/common/axi_interconnect.sv:22:1: previous definition. [ERR:CP0329] ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/testbench/soc_tb.sv:22:1: Multiply defined package: "defines", - ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/fpga/common/axi_rom.sv:22:1: previous definition. + ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/fpga/common/vga_controller.sv:22:1: previous definition. [ERR:CP0329] ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/testbench/soc_tb.sv:22:1: Multiply defined package: "defines", - ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/fpga/common/ps2_controller.sv:22:1: previous definition. + ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/fpga/common/axi_rom.sv:22:1: previous definition. [ERR:CP0329] ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/testbench/soc_tb.sv:22:1: Multiply defined package: "defines", - ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/fpga/common/sdram_controller.sv:22:1: previous definition. + ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/fpga/common/ps2_controller.sv:22:1: previous definition. [NTE:CP0309] ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/fpga/common/async_fifo.sv:37:29: Implicit port type (wire) for "read_data". @@ -1755,15 +1755,15 @@ int_typespec 54333 int_var 92 integer_typespec 120 integer_var 1 -interface 48 interface_array 4 +interface_inst 48 interface_typespec 118 io_decl 831 logic_net 3873 logic_typespec 19346 logic_var 2684 modport 77 -module 1075 +module_inst 1075 named_begin 8 operation 22755 package 152 @@ -1827,15 +1827,15 @@ int_typespec 54333 int_var 253 integer_typespec 120 integer_var 1 -interface 48 interface_array 4 +interface_inst 48 interface_typespec 118 io_decl 845 logic_net 3873 logic_typespec 19346 logic_var 6026 modport 77 -module 1243 +module_inst 1243 named_begin 50 operation 43624 package 152 diff --git a/third_party/tests/OVMSwitch/OVMSwitch.log b/third_party/tests/OVMSwitch/OVMSwitch.log index b2c51d9d76..d2f75e871a 100644 --- a/third_party/tests/OVMSwitch/OVMSwitch.log +++ b/third_party/tests/OVMSwitch/OVMSwitch.log @@ -768,7 +768,7 @@ int_typespec 4531 int_var 721 integer_typespec 121 integer_var 75 -interface 17 +interface_inst 17 interface_typespec 6 io_decl 3594 logic_net 483 @@ -776,7 +776,7 @@ logic_typespec 255 logic_var 39 method_func_call 3512 modport 17 -module 35 +module_inst 35 named_begin 1 named_event 6 named_fork 4 diff --git a/third_party/tests/Opentitan/Earlgrey.log b/third_party/tests/Opentitan/Earlgrey.log index 9e724c42a6..ef96d7ef44 100644 --- a/third_party/tests/Opentitan/Earlgrey.log +++ b/third_party/tests/Opentitan/Earlgrey.log @@ -39314,7 +39314,7 @@ io_decl 149 logic_net 20805 logic_typespec 44289 logic_var 9249 -module 4604 +module_inst 4604 named_begin 182 operation 69686 package 77 diff --git a/third_party/tests/Opentitan/Opentitan.log b/third_party/tests/Opentitan/Opentitan.log index 8cfc645ae6..54d12c69b0 100644 --- a/third_party/tests/Opentitan/Opentitan.log +++ b/third_party/tests/Opentitan/Opentitan.log @@ -8367,7 +8367,7 @@ int_typespec 18296 int_var 1240 integer_typespec 317 integer_var 2 -interface 5 +interface_inst 5 io_decl 7045 logic_net 20830 logic_typespec 44393 @@ -8375,7 +8375,7 @@ logic_var 9305 long_int_typespec 99 long_int_var 7 method_func_call 7996 -module 4630 +module_inst 4630 named_begin 190 named_event 8 named_fork 3 diff --git a/third_party/tests/RiscV/RiscV.log b/third_party/tests/RiscV/RiscV.log index 27d1650217..af5d04484f 100644 --- a/third_party/tests/RiscV/RiscV.log +++ b/third_party/tests/RiscV/RiscV.log @@ -142,7 +142,7 @@ io_decl 19 logic_net 1049 logic_typespec 1053 logic_var 16 -module 57 +module_inst 57 operation 1490 package 2 param_assign 32 diff --git a/third_party/tests/Rp32/rp32.log b/third_party/tests/Rp32/rp32.log index 0f92df943b..6909e99dc5 100644 --- a/third_party/tests/Rp32/rp32.log +++ b/third_party/tests/Rp32/rp32.log @@ -427,16 +427,16 @@ if_stmt 28 int_typespec 172 int_var 17 integer_typespec 23 -interface 13 interface_array 2 +interface_inst 13 interface_typespec 21 io_decl 235 logic_net 417 logic_typespec 1102 logic_var 203 modport 22 -module 93 module_array 1 +module_inst 93 module_typespec 1 named_begin 1 operation 2069 @@ -494,16 +494,16 @@ if_stmt 187 int_typespec 172 int_var 18 integer_typespec 23 -interface 13 interface_array 2 +interface_inst 13 interface_typespec 21 io_decl 428 logic_net 417 logic_typespec 1102 logic_var 207 modport 22 -module 97 module_array 1 +module_inst 97 module_typespec 1 named_begin 2 operation 5740 diff --git a/third_party/tests/SVSwitch/SVSwitch.log b/third_party/tests/SVSwitch/SVSwitch.log index 4acd6aa2dc..1a2fcab04c 100644 --- a/third_party/tests/SVSwitch/SVSwitch.log +++ b/third_party/tests/SVSwitch/SVSwitch.log @@ -380,8 +380,8 @@ int_typespec 21 int_var 6 integer_typespec 10 integer_var 9 -interface 23 interface_array 1 +interface_inst 23 interface_typespec 16 io_decl 51 logic_net 248 @@ -389,7 +389,7 @@ logic_typespec 195 logic_var 49 method_func_call 43 modport 23 -module 17 +module_inst 17 named_begin 1 operation 216 package 2 diff --git a/third_party/tests/Scoreboard/Scoreboard.log b/third_party/tests/Scoreboard/Scoreboard.log index 969f1582fe..edf24ee285 100644 --- a/third_party/tests/Scoreboard/Scoreboard.log +++ b/third_party/tests/Scoreboard/Scoreboard.log @@ -833,7 +833,7 @@ logic_var 42 long_int_typespec 99 long_int_var 7 method_func_call 8065 -module 27 +module_inst 27 named_begin 9 named_event 8 named_fork 3 diff --git a/third_party/tests/Scr1/Scr1.log b/third_party/tests/Scr1/Scr1.log index db4dacd9fe..c0e8b3ec71 100644 --- a/third_party/tests/Scr1/Scr1.log +++ b/third_party/tests/Scr1/Scr1.log @@ -482,7 +482,7 @@ logic_net 2849 logic_typespec 3424 logic_var 821 method_func_call 5 -module 148 +module_inst 148 named_begin 4 operation 4698 package 2 diff --git a/third_party/tests/Scr1SvTests/Scr1SvTests.log b/third_party/tests/Scr1SvTests/Scr1SvTests.log index 847ece10d6..07d16dc8ac 100644 --- a/third_party/tests/Scr1SvTests/Scr1SvTests.log +++ b/third_party/tests/Scr1SvTests/Scr1SvTests.log @@ -346,7 +346,7 @@ logic_net 3126 logic_typespec 3685 logic_var 1051 method_func_call 4 -module 162 +module_inst 162 named_begin 3 operation 5441 package 2 diff --git a/third_party/tests/SeqDriver/SeqDriver.log b/third_party/tests/SeqDriver/SeqDriver.log index 3de4186ef7..81739a311d 100644 --- a/third_party/tests/SeqDriver/SeqDriver.log +++ b/third_party/tests/SeqDriver/SeqDriver.log @@ -812,7 +812,7 @@ indexed_part_select 81 initial 3 int_typespec 3974 int_var 1874 -interface 3 +interface_inst 3 interface_typespec 1 io_decl 9911 logic_net 324 @@ -821,7 +821,7 @@ logic_var 60 long_int_typespec 139 long_int_var 11 method_func_call 12891 -module 28 +module_inst 28 named_begin 12 named_event 8 named_fork 5 diff --git a/third_party/tests/SimpleOVM/SimpleOVM.log b/third_party/tests/SimpleOVM/SimpleOVM.log index 60f5f8bed3..92dd772d98 100644 --- a/third_party/tests/SimpleOVM/SimpleOVM.log +++ b/third_party/tests/SimpleOVM/SimpleOVM.log @@ -693,7 +693,7 @@ io_decl 3530 logic_typespec 83 logic_var 33 method_func_call 3182 -module 16 +module_inst 16 named_event 6 named_fork 4 operation 4767 diff --git a/third_party/tests/SimpleParserTest/SimpleParserTest.log b/third_party/tests/SimpleParserTest/SimpleParserTest.log index 11b942532f..c5923c2755 100644 --- a/third_party/tests/SimpleParserTest/SimpleParserTest.log +++ b/third_party/tests/SimpleParserTest/SimpleParserTest.log @@ -142,7 +142,7 @@ io_decl 21 logic_net 232 logic_typespec 209 logic_var 2 -module 39 +module_inst 39 named_begin 4 operation 266 package 2 @@ -782,14 +782,14 @@ design: (work@dff_async_reset) |vpiSize:2 |STRING:x x : x |uhdmallModules: -\_module: work@LFSR_TASK (work@LFSR_TASK), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/lfsr_task.v, line:2:1, endln:37:10 +\_module_inst: work@LFSR_TASK (work@LFSR_TASK), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/lfsr_task.v, line:2:1, endln:37:10 |vpiParent: \_design: (work@dff_async_reset) |vpiFullName:work@LFSR_TASK |vpiParameter: \_parameter: (work@LFSR_TASK.Chain1), line:7:17, endln:7:23 |vpiParent: - \_module: work@LFSR_TASK (work@LFSR_TASK), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/lfsr_task.v, line:2:1, endln:37:10 + \_module_inst: work@LFSR_TASK (work@LFSR_TASK), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/lfsr_task.v, line:2:1, endln:37:10 |BIN:10001110 |vpiTypespec: \_int_typespec: , line:7:11, endln:7:16 @@ -818,7 +818,7 @@ design: (work@dff_async_reset) |vpiParameter: \_parameter: (work@LFSR_TASK.Chain2), line:8:17, endln:8:23 |vpiParent: - \_module: work@LFSR_TASK (work@LFSR_TASK), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/lfsr_task.v, line:2:1, endln:37:10 + \_module_inst: work@LFSR_TASK (work@LFSR_TASK), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/lfsr_task.v, line:2:1, endln:37:10 |BIN:10101110 |vpiTypespec: \_int_typespec: , line:8:11, endln:8:16 @@ -847,7 +847,7 @@ design: (work@dff_async_reset) |vpiParamAssign: \_param_assign: , line:7:17, endln:7:37 |vpiParent: - \_module: work@LFSR_TASK (work@LFSR_TASK), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/lfsr_task.v, line:2:1, endln:37:10 + \_module_inst: work@LFSR_TASK (work@LFSR_TASK), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/lfsr_task.v, line:2:1, endln:37:10 |vpiRhs: \_constant: , line:7:26, endln:7:37 |vpiDecompile:8'b10001110 @@ -861,7 +861,7 @@ design: (work@dff_async_reset) |vpiParamAssign: \_param_assign: , line:8:17, endln:8:37 |vpiParent: - \_module: work@LFSR_TASK (work@LFSR_TASK), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/lfsr_task.v, line:2:1, endln:37:10 + \_module_inst: work@LFSR_TASK (work@LFSR_TASK), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/lfsr_task.v, line:2:1, endln:37:10 |vpiRhs: \_constant: , line:8:26, endln:8:37 |vpiDecompile:8'b10101110 @@ -876,7 +876,7 @@ design: (work@dff_async_reset) |vpiTaskFunc: \_task: (work@LFSR_TASK.LFSR_TAPS8_TASK), line:9:2, endln:25:9 |vpiParent: - \_module: work@LFSR_TASK (work@LFSR_TASK), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/lfsr_task.v, line:2:1, endln:37:10 + \_module_inst: work@LFSR_TASK (work@LFSR_TASK), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/lfsr_task.v, line:2:1, endln:37:10 |vpiName:LFSR_TAPS8_TASK |vpiFullName:work@LFSR_TASK.LFSR_TAPS8_TASK |vpiVariables: @@ -895,7 +895,7 @@ design: (work@dff_async_reset) |vpiAutomatic:1 |vpiVisibility:1 |vpiParent: - \_module: work@LFSR_TASK (work@LFSR_TASK), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/lfsr_task.v, line:2:1, endln:37:10 + \_module_inst: work@LFSR_TASK (work@LFSR_TASK), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/lfsr_task.v, line:2:1, endln:37:10 |vpiIODecl: \_io_decl: (A), line:10:14, endln:10:15 |vpiParent: @@ -1329,49 +1329,49 @@ design: (work@dff_async_reset) |UINT:0 |vpiConstType:9 |vpiInstance: - \_module: work@LFSR_TASK (work@LFSR_TASK), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/lfsr_task.v, line:2:1, endln:37:10 + \_module_inst: work@LFSR_TASK (work@LFSR_TASK), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/lfsr_task.v, line:2:1, endln:37:10 |vpiNet: \_logic_net: (work@LFSR_TASK.random1), line:6:11, endln:6:18 |vpiParent: - \_module: work@LFSR_TASK (work@LFSR_TASK), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/lfsr_task.v, line:2:1, endln:37:10 + \_module_inst: work@LFSR_TASK (work@LFSR_TASK), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/lfsr_task.v, line:2:1, endln:37:10 |vpiName:random1 |vpiFullName:work@LFSR_TASK.random1 |vpiNetType:48 |vpiNet: \_logic_net: (work@LFSR_TASK.random2), line:6:20, endln:6:27 |vpiParent: - \_module: work@LFSR_TASK (work@LFSR_TASK), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/lfsr_task.v, line:2:1, endln:37:10 + \_module_inst: work@LFSR_TASK (work@LFSR_TASK), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/lfsr_task.v, line:2:1, endln:37:10 |vpiName:random2 |vpiFullName:work@LFSR_TASK.random2 |vpiNetType:48 |vpiNet: \_logic_net: (work@LFSR_TASK.clock), line:2:19, endln:2:24 |vpiParent: - \_module: work@LFSR_TASK (work@LFSR_TASK), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/lfsr_task.v, line:2:1, endln:37:10 + \_module_inst: work@LFSR_TASK (work@LFSR_TASK), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/lfsr_task.v, line:2:1, endln:37:10 |vpiName:clock |vpiFullName:work@LFSR_TASK.clock |vpiNet: \_logic_net: (work@LFSR_TASK.Reset), line:2:26, endln:2:31 |vpiParent: - \_module: work@LFSR_TASK (work@LFSR_TASK), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/lfsr_task.v, line:2:1, endln:37:10 + \_module_inst: work@LFSR_TASK (work@LFSR_TASK), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/lfsr_task.v, line:2:1, endln:37:10 |vpiName:Reset |vpiFullName:work@LFSR_TASK.Reset |vpiNet: \_logic_net: (work@LFSR_TASK.seed1), line:2:33, endln:2:38 |vpiParent: - \_module: work@LFSR_TASK (work@LFSR_TASK), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/lfsr_task.v, line:2:1, endln:37:10 + \_module_inst: work@LFSR_TASK (work@LFSR_TASK), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/lfsr_task.v, line:2:1, endln:37:10 |vpiName:seed1 |vpiFullName:work@LFSR_TASK.seed1 |vpiNet: \_logic_net: (work@LFSR_TASK.seed2), line:2:40, endln:2:45 |vpiParent: - \_module: work@LFSR_TASK (work@LFSR_TASK), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/lfsr_task.v, line:2:1, endln:37:10 + \_module_inst: work@LFSR_TASK (work@LFSR_TASK), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/lfsr_task.v, line:2:1, endln:37:10 |vpiName:seed2 |vpiFullName:work@LFSR_TASK.seed2 |vpiPort: \_port: (clock), line:2:19, endln:2:24 |vpiParent: - \_module: work@LFSR_TASK (work@LFSR_TASK), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/lfsr_task.v, line:2:1, endln:37:10 + \_module_inst: work@LFSR_TASK (work@LFSR_TASK), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/lfsr_task.v, line:2:1, endln:37:10 |vpiName:clock |vpiDirection:1 |vpiLowConn: @@ -1383,7 +1383,7 @@ design: (work@dff_async_reset) |vpiPort: \_port: (Reset), line:2:26, endln:2:31 |vpiParent: - \_module: work@LFSR_TASK (work@LFSR_TASK), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/lfsr_task.v, line:2:1, endln:37:10 + \_module_inst: work@LFSR_TASK (work@LFSR_TASK), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/lfsr_task.v, line:2:1, endln:37:10 |vpiName:Reset |vpiDirection:1 |vpiLowConn: @@ -1393,7 +1393,7 @@ design: (work@dff_async_reset) |vpiPort: \_port: (seed1), line:2:33, endln:2:38 |vpiParent: - \_module: work@LFSR_TASK (work@LFSR_TASK), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/lfsr_task.v, line:2:1, endln:37:10 + \_module_inst: work@LFSR_TASK (work@LFSR_TASK), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/lfsr_task.v, line:2:1, endln:37:10 |vpiName:seed1 |vpiDirection:1 |vpiLowConn: @@ -1423,7 +1423,7 @@ design: (work@dff_async_reset) |vpiPort: \_port: (seed2), line:2:40, endln:2:45 |vpiParent: - \_module: work@LFSR_TASK (work@LFSR_TASK), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/lfsr_task.v, line:2:1, endln:37:10 + \_module_inst: work@LFSR_TASK (work@LFSR_TASK), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/lfsr_task.v, line:2:1, endln:37:10 |vpiName:seed2 |vpiDirection:1 |vpiLowConn: @@ -1433,7 +1433,7 @@ design: (work@dff_async_reset) |vpiPort: \_port: (random1), line:2:47, endln:2:54 |vpiParent: - \_module: work@LFSR_TASK (work@LFSR_TASK), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/lfsr_task.v, line:2:1, endln:37:10 + \_module_inst: work@LFSR_TASK (work@LFSR_TASK), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/lfsr_task.v, line:2:1, endln:37:10 |vpiName:random1 |vpiDirection:2 |vpiLowConn: @@ -1463,7 +1463,7 @@ design: (work@dff_async_reset) |vpiPort: \_port: (random2), line:2:56, endln:2:63 |vpiParent: - \_module: work@LFSR_TASK (work@LFSR_TASK), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/lfsr_task.v, line:2:1, endln:37:10 + \_module_inst: work@LFSR_TASK (work@LFSR_TASK), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/lfsr_task.v, line:2:1, endln:37:10 |vpiName:random2 |vpiDirection:2 |vpiLowConn: @@ -1493,7 +1493,7 @@ design: (work@dff_async_reset) |vpiProcess: \_always: , line:27:1, endln:31:39 |vpiParent: - \_module: work@LFSR_TASK (work@LFSR_TASK), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/lfsr_task.v, line:2:1, endln:37:10 + \_module_inst: work@LFSR_TASK (work@LFSR_TASK), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/lfsr_task.v, line:2:1, endln:37:10 |vpiStmt: \_event_control: , line:27:7, endln:27:40 |vpiParent: @@ -1593,7 +1593,7 @@ design: (work@dff_async_reset) |vpiProcess: \_always: , line:32:1, endln:36:39 |vpiParent: - \_module: work@LFSR_TASK (work@LFSR_TASK), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/lfsr_task.v, line:2:1, endln:37:10 + \_module_inst: work@LFSR_TASK (work@LFSR_TASK), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/lfsr_task.v, line:2:1, endln:37:10 |vpiStmt: \_event_control: , line:32:7, endln:32:40 |vpiParent: @@ -1691,14 +1691,14 @@ design: (work@dff_async_reset) |vpiName:LFSR_TASK |vpiAlwaysType:1 |uhdmallModules: -\_module: work@arbiter (work@arbiter), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/another_arbiter.v, line:2:1, endln:121:10 +\_module_inst: work@arbiter (work@arbiter), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/another_arbiter.v, line:2:1, endln:121:10 |vpiParent: \_design: (work@dff_async_reset) |vpiFullName:work@arbiter |vpiParameter: \_parameter: (work@arbiter.NUMUNITS), line:7:12, endln:7:20 |vpiParent: - \_module: work@arbiter (work@arbiter), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/another_arbiter.v, line:2:1, endln:121:10 + \_module_inst: work@arbiter (work@arbiter), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/another_arbiter.v, line:2:1, endln:121:10 |UINT:8 |vpiTypespec: \_int_typespec: @@ -1707,7 +1707,7 @@ design: (work@dff_async_reset) |vpiParameter: \_parameter: (work@arbiter.ADDRESSWIDTH), line:8:12, endln:8:24 |vpiParent: - \_module: work@arbiter (work@arbiter), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/another_arbiter.v, line:2:1, endln:121:10 + \_module_inst: work@arbiter (work@arbiter), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/another_arbiter.v, line:2:1, endln:121:10 |UINT:3 |vpiTypespec: \_int_typespec: @@ -1716,7 +1716,7 @@ design: (work@dff_async_reset) |vpiParamAssign: \_param_assign: , line:7:12, endln:7:24 |vpiParent: - \_module: work@arbiter (work@arbiter), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/another_arbiter.v, line:2:1, endln:121:10 + \_module_inst: work@arbiter (work@arbiter), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/another_arbiter.v, line:2:1, endln:121:10 |vpiRhs: \_constant: , line:7:23, endln:7:24 |vpiDecompile:8 @@ -1730,7 +1730,7 @@ design: (work@dff_async_reset) |vpiParamAssign: \_param_assign: , line:8:12, endln:8:28 |vpiParent: - \_module: work@arbiter (work@arbiter), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/another_arbiter.v, line:2:1, endln:121:10 + \_module_inst: work@arbiter (work@arbiter), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/another_arbiter.v, line:2:1, endln:121:10 |vpiRhs: \_constant: , line:8:27, endln:8:28 |vpiDecompile:3 @@ -1745,188 +1745,188 @@ design: (work@dff_async_reset) |vpiNet: \_logic_net: (work@arbiter.i), line:3:10, endln:3:11 |vpiParent: - \_module: work@arbiter (work@arbiter), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/another_arbiter.v, line:2:1, endln:121:10 + \_module_inst: work@arbiter (work@arbiter), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/another_arbiter.v, line:2:1, endln:121:10 |vpiName:i |vpiFullName:work@arbiter.i |vpiNet: \_logic_net: (work@arbiter.j), line:3:12, endln:3:13 |vpiParent: - \_module: work@arbiter (work@arbiter), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/another_arbiter.v, line:2:1, endln:121:10 + \_module_inst: work@arbiter (work@arbiter), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/another_arbiter.v, line:2:1, endln:121:10 |vpiName:j |vpiFullName:work@arbiter.j |vpiNet: \_logic_net: (work@arbiter.k), line:3:14, endln:3:15 |vpiParent: - \_module: work@arbiter (work@arbiter), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/another_arbiter.v, line:2:1, endln:121:10 + \_module_inst: work@arbiter (work@arbiter), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/another_arbiter.v, line:2:1, endln:121:10 |vpiName:k |vpiFullName:work@arbiter.k |vpiNet: \_logic_net: (work@arbiter.p), line:3:16, endln:3:17 |vpiParent: - \_module: work@arbiter (work@arbiter), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/another_arbiter.v, line:2:1, endln:121:10 + \_module_inst: work@arbiter (work@arbiter), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/another_arbiter.v, line:2:1, endln:121:10 |vpiName:p |vpiFullName:work@arbiter.p |vpiNet: \_logic_net: (work@arbiter.q), line:3:18, endln:3:19 |vpiParent: - \_module: work@arbiter (work@arbiter), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/another_arbiter.v, line:2:1, endln:121:10 + \_module_inst: work@arbiter (work@arbiter), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/another_arbiter.v, line:2:1, endln:121:10 |vpiName:q |vpiFullName:work@arbiter.q |vpiNet: \_logic_net: (work@arbiter.r), line:3:20, endln:3:21 |vpiParent: - \_module: work@arbiter (work@arbiter), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/another_arbiter.v, line:2:1, endln:121:10 + \_module_inst: work@arbiter (work@arbiter), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/another_arbiter.v, line:2:1, endln:121:10 |vpiName:r |vpiFullName:work@arbiter.r |vpiNet: \_logic_net: (work@arbiter.s), line:3:22, endln:3:23 |vpiParent: - \_module: work@arbiter (work@arbiter), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/another_arbiter.v, line:2:1, endln:121:10 + \_module_inst: work@arbiter (work@arbiter), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/another_arbiter.v, line:2:1, endln:121:10 |vpiName:s |vpiFullName:work@arbiter.s |vpiNet: \_logic_net: (work@arbiter.t), line:3:24, endln:3:25 |vpiParent: - \_module: work@arbiter (work@arbiter), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/another_arbiter.v, line:2:1, endln:121:10 + \_module_inst: work@arbiter (work@arbiter), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/another_arbiter.v, line:2:1, endln:121:10 |vpiName:t |vpiFullName:work@arbiter.t |vpiNet: \_logic_net: (work@arbiter.u), line:3:26, endln:3:27 |vpiParent: - \_module: work@arbiter (work@arbiter), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/another_arbiter.v, line:2:1, endln:121:10 + \_module_inst: work@arbiter (work@arbiter), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/another_arbiter.v, line:2:1, endln:121:10 |vpiName:u |vpiFullName:work@arbiter.u |vpiNet: \_logic_net: (work@arbiter.v), line:3:28, endln:3:29 |vpiParent: - \_module: work@arbiter (work@arbiter), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/another_arbiter.v, line:2:1, endln:121:10 + \_module_inst: work@arbiter (work@arbiter), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/another_arbiter.v, line:2:1, endln:121:10 |vpiName:v |vpiFullName:work@arbiter.v |vpiNet: \_logic_net: (work@arbiter.prio), line:19:27, endln:19:31 |vpiParent: - \_module: work@arbiter (work@arbiter), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/another_arbiter.v, line:2:1, endln:121:10 + \_module_inst: work@arbiter (work@arbiter), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/another_arbiter.v, line:2:1, endln:121:10 |vpiName:prio |vpiFullName:work@arbiter.prio |vpiNetType:48 |vpiNet: \_logic_net: (work@arbiter.tmp_prio), line:20:27, endln:20:35 |vpiParent: - \_module: work@arbiter (work@arbiter), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/another_arbiter.v, line:2:1, endln:121:10 + \_module_inst: work@arbiter (work@arbiter), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/another_arbiter.v, line:2:1, endln:121:10 |vpiName:tmp_prio |vpiFullName:work@arbiter.tmp_prio |vpiNetType:48 |vpiNet: \_logic_net: (work@arbiter.grant), line:30:23, endln:30:28 |vpiParent: - \_module: work@arbiter (work@arbiter), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/another_arbiter.v, line:2:1, endln:121:10 + \_module_inst: work@arbiter (work@arbiter), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/another_arbiter.v, line:2:1, endln:121:10 |vpiName:grant |vpiFullName:work@arbiter.grant |vpiNetType:48 |vpiNet: \_logic_net: (work@arbiter.grantD), line:31:23, endln:31:29 |vpiParent: - \_module: work@arbiter (work@arbiter), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/another_arbiter.v, line:2:1, endln:121:10 + \_module_inst: work@arbiter (work@arbiter), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/another_arbiter.v, line:2:1, endln:121:10 |vpiName:grantD |vpiFullName:work@arbiter.grantD |vpiNetType:48 |vpiNet: \_logic_net: (work@arbiter.next), line:32:27, endln:32:31 |vpiParent: - \_module: work@arbiter (work@arbiter), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/another_arbiter.v, line:2:1, endln:121:10 + \_module_inst: work@arbiter (work@arbiter), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/another_arbiter.v, line:2:1, endln:121:10 |vpiName:next |vpiFullName:work@arbiter.next |vpiNetType:48 |vpiNet: \_logic_net: (work@arbiter.nextNext), line:33:27, endln:33:35 |vpiParent: - \_module: work@arbiter (work@arbiter), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/another_arbiter.v, line:2:1, endln:121:10 + \_module_inst: work@arbiter (work@arbiter), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/another_arbiter.v, line:2:1, endln:121:10 |vpiName:nextNext |vpiFullName:work@arbiter.nextNext |vpiNetType:48 |vpiNet: \_logic_net: (work@arbiter.scan), line:34:27, endln:34:31 |vpiParent: - \_module: work@arbiter (work@arbiter), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/another_arbiter.v, line:2:1, endln:121:10 + \_module_inst: work@arbiter (work@arbiter), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/another_arbiter.v, line:2:1, endln:121:10 |vpiName:scan |vpiFullName:work@arbiter.scan |vpiNetType:48 |vpiNet: \_logic_net: (work@arbiter.found), line:36:23, endln:36:28 |vpiParent: - \_module: work@arbiter (work@arbiter), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/another_arbiter.v, line:2:1, endln:121:10 + \_module_inst: work@arbiter (work@arbiter), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/another_arbiter.v, line:2:1, endln:121:10 |vpiName:found |vpiFullName:work@arbiter.found |vpiNetType:48 |vpiNet: \_logic_net: (work@arbiter.selectPrio), line:38:27, endln:38:37 |vpiParent: - \_module: work@arbiter (work@arbiter), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/another_arbiter.v, line:2:1, endln:121:10 + \_module_inst: work@arbiter (work@arbiter), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/another_arbiter.v, line:2:1, endln:121:10 |vpiName:selectPrio |vpiFullName:work@arbiter.selectPrio |vpiNetType:48 |vpiNet: \_logic_net: (work@arbiter.min), line:40:27, endln:40:30 |vpiParent: - \_module: work@arbiter (work@arbiter), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/another_arbiter.v, line:2:1, endln:121:10 + \_module_inst: work@arbiter (work@arbiter), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/another_arbiter.v, line:2:1, endln:121:10 |vpiName:min |vpiFullName:work@arbiter.min |vpiNetType:48 |vpiNet: \_logic_net: (work@arbiter.minPrio), line:42:23, endln:42:30 |vpiParent: - \_module: work@arbiter (work@arbiter), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/another_arbiter.v, line:2:1, endln:121:10 + \_module_inst: work@arbiter (work@arbiter), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/another_arbiter.v, line:2:1, endln:121:10 |vpiName:minPrio |vpiFullName:work@arbiter.minPrio |vpiNetType:48 |vpiNet: \_logic_net: (work@arbiter.prioRequest), line:44:24, endln:44:35 |vpiParent: - \_module: work@arbiter (work@arbiter), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/another_arbiter.v, line:2:1, endln:121:10 + \_module_inst: work@arbiter (work@arbiter), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/another_arbiter.v, line:2:1, endln:121:10 |vpiName:prioRequest |vpiFullName:work@arbiter.prioRequest |vpiNetType:1 |vpiNet: \_logic_net: (work@arbiter.finalRequest), line:46:23, endln:46:35 |vpiParent: - \_module: work@arbiter (work@arbiter), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/another_arbiter.v, line:2:1, endln:121:10 + \_module_inst: work@arbiter (work@arbiter), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/another_arbiter.v, line:2:1, endln:121:10 |vpiName:finalRequest |vpiFullName:work@arbiter.finalRequest |vpiNetType:48 |vpiNet: \_logic_net: (work@arbiter.clock), line:2:16, endln:2:21 |vpiParent: - \_module: work@arbiter (work@arbiter), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/another_arbiter.v, line:2:1, endln:121:10 + \_module_inst: work@arbiter (work@arbiter), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/another_arbiter.v, line:2:1, endln:121:10 |vpiName:clock |vpiFullName:work@arbiter.clock |vpiNet: \_logic_net: (work@arbiter.reset), line:2:23, endln:2:28 |vpiParent: - \_module: work@arbiter (work@arbiter), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/another_arbiter.v, line:2:1, endln:121:10 + \_module_inst: work@arbiter (work@arbiter), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/another_arbiter.v, line:2:1, endln:121:10 |vpiName:reset |vpiFullName:work@arbiter.reset |vpiNet: \_logic_net: (work@arbiter.roundORpriority), line:2:30, endln:2:45 |vpiParent: - \_module: work@arbiter (work@arbiter), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/another_arbiter.v, line:2:1, endln:121:10 + \_module_inst: work@arbiter (work@arbiter), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/another_arbiter.v, line:2:1, endln:121:10 |vpiName:roundORpriority |vpiFullName:work@arbiter.roundORpriority |vpiNet: \_logic_net: (work@arbiter.request), line:2:47, endln:2:54 |vpiParent: - \_module: work@arbiter (work@arbiter), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/another_arbiter.v, line:2:1, endln:121:10 + \_module_inst: work@arbiter (work@arbiter), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/another_arbiter.v, line:2:1, endln:121:10 |vpiName:request |vpiFullName:work@arbiter.request |vpiNet: \_logic_net: (work@arbiter.tpriority), line:2:56, endln:2:65 |vpiParent: - \_module: work@arbiter (work@arbiter), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/another_arbiter.v, line:2:1, endln:121:10 + \_module_inst: work@arbiter (work@arbiter), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/another_arbiter.v, line:2:1, endln:121:10 |vpiName:tpriority |vpiFullName:work@arbiter.tpriority |vpiPort: \_port: (clock), line:2:16, endln:2:21 |vpiParent: - \_module: work@arbiter (work@arbiter), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/another_arbiter.v, line:2:1, endln:121:10 + \_module_inst: work@arbiter (work@arbiter), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/another_arbiter.v, line:2:1, endln:121:10 |vpiName:clock |vpiDirection:1 |vpiLowConn: @@ -1938,7 +1938,7 @@ design: (work@dff_async_reset) |vpiPort: \_port: (reset), line:2:23, endln:2:28 |vpiParent: - \_module: work@arbiter (work@arbiter), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/another_arbiter.v, line:2:1, endln:121:10 + \_module_inst: work@arbiter (work@arbiter), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/another_arbiter.v, line:2:1, endln:121:10 |vpiName:reset |vpiDirection:1 |vpiLowConn: @@ -1950,7 +1950,7 @@ design: (work@dff_async_reset) |vpiPort: \_port: (roundORpriority), line:2:30, endln:2:45 |vpiParent: - \_module: work@arbiter (work@arbiter), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/another_arbiter.v, line:2:1, endln:121:10 + \_module_inst: work@arbiter (work@arbiter), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/another_arbiter.v, line:2:1, endln:121:10 |vpiName:roundORpriority |vpiDirection:1 |vpiLowConn: @@ -1962,7 +1962,7 @@ design: (work@dff_async_reset) |vpiPort: \_port: (request), line:2:47, endln:2:54 |vpiParent: - \_module: work@arbiter (work@arbiter), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/another_arbiter.v, line:2:1, endln:121:10 + \_module_inst: work@arbiter (work@arbiter), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/another_arbiter.v, line:2:1, endln:121:10 |vpiName:request |vpiDirection:1 |vpiLowConn: @@ -2002,7 +2002,7 @@ design: (work@dff_async_reset) |vpiPort: \_port: (tpriority), line:2:56, endln:2:65 |vpiParent: - \_module: work@arbiter (work@arbiter), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/another_arbiter.v, line:2:1, endln:121:10 + \_module_inst: work@arbiter (work@arbiter), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/another_arbiter.v, line:2:1, endln:121:10 |vpiName:tpriority |vpiDirection:1 |vpiLowConn: @@ -2052,7 +2052,7 @@ design: (work@dff_async_reset) |vpiPort: \_port: (grant), line:2:67, endln:2:72 |vpiParent: - \_module: work@arbiter (work@arbiter), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/another_arbiter.v, line:2:1, endln:121:10 + \_module_inst: work@arbiter (work@arbiter), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/another_arbiter.v, line:2:1, endln:121:10 |vpiName:grant |vpiDirection:2 |vpiLowConn: @@ -2092,7 +2092,7 @@ design: (work@dff_async_reset) |vpiProcess: \_always: , line:21:2, endln:29:5 |vpiParent: - \_module: work@arbiter (work@arbiter), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/another_arbiter.v, line:2:1, endln:121:10 + \_module_inst: work@arbiter (work@arbiter), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/another_arbiter.v, line:2:1, endln:121:10 |vpiStmt: \_event_control: , line:21:8, endln:21:20 |vpiParent: @@ -2371,7 +2371,7 @@ design: (work@dff_async_reset) |vpiProcess: \_always: , line:49:2, endln:53:5 |vpiParent: - \_module: work@arbiter (work@arbiter), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/another_arbiter.v, line:2:1, endln:121:10 + \_module_inst: work@arbiter (work@arbiter), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/another_arbiter.v, line:2:1, endln:121:10 |vpiStmt: \_event_control: , line:49:8, endln:49:24 |vpiParent: @@ -2457,7 +2457,7 @@ design: (work@dff_async_reset) |vpiProcess: \_always: , line:55:2, endln:59:5 |vpiParent: - \_module: work@arbiter (work@arbiter), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/another_arbiter.v, line:2:1, endln:121:10 + \_module_inst: work@arbiter (work@arbiter), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/another_arbiter.v, line:2:1, endln:121:10 |vpiStmt: \_event_control: , line:55:8, endln:55:24 |vpiParent: @@ -2543,7 +2543,7 @@ design: (work@dff_async_reset) |vpiProcess: \_always: , line:61:2, endln:66:5 |vpiParent: - \_module: work@arbiter (work@arbiter), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/another_arbiter.v, line:2:1, endln:121:10 + \_module_inst: work@arbiter (work@arbiter), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/another_arbiter.v, line:2:1, endln:121:10 |vpiStmt: \_event_control: , line:61:8, endln:62:43 |vpiParent: @@ -2861,7 +2861,7 @@ design: (work@dff_async_reset) |vpiProcess: \_always: , line:68:2, endln:73:5 |vpiParent: - \_module: work@arbiter (work@arbiter), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/another_arbiter.v, line:2:1, endln:121:10 + \_module_inst: work@arbiter (work@arbiter), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/another_arbiter.v, line:2:1, endln:121:10 |vpiStmt: \_event_control: , line:68:8, endln:68:52 |vpiParent: @@ -3048,7 +3048,7 @@ design: (work@dff_async_reset) |vpiProcess: \_always: , line:76:2, endln:83:5 |vpiParent: - \_module: work@arbiter (work@arbiter), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/another_arbiter.v, line:2:1, endln:121:10 + \_module_inst: work@arbiter (work@arbiter), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/another_arbiter.v, line:2:1, endln:121:10 |vpiStmt: \_event_control: , line:76:8, endln:78:33 |vpiParent: @@ -3373,7 +3373,7 @@ design: (work@dff_async_reset) |vpiProcess: \_always: , line:85:2, endln:90:5 |vpiParent: - \_module: work@arbiter (work@arbiter), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/another_arbiter.v, line:2:1, endln:121:10 + \_module_inst: work@arbiter (work@arbiter), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/another_arbiter.v, line:2:1, endln:121:10 |vpiStmt: \_event_control: , line:85:8, endln:86:46 |vpiParent: @@ -3691,7 +3691,7 @@ design: (work@dff_async_reset) |vpiProcess: \_always: , line:94:2, endln:98:5 |vpiParent: - \_module: work@arbiter (work@arbiter), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/another_arbiter.v, line:2:1, endln:121:10 + \_module_inst: work@arbiter (work@arbiter), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/another_arbiter.v, line:2:1, endln:121:10 |vpiStmt: \_event_control: , line:94:8, endln:94:15 |vpiParent: @@ -3904,7 +3904,7 @@ design: (work@dff_async_reset) |vpiProcess: \_always: , line:100:2, endln:106:5 |vpiParent: - \_module: work@arbiter (work@arbiter), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/another_arbiter.v, line:2:1, endln:121:10 + \_module_inst: work@arbiter (work@arbiter), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/another_arbiter.v, line:2:1, endln:121:10 |vpiStmt: \_event_control: , line:100:8, endln:101:43 |vpiParent: @@ -4291,7 +4291,7 @@ design: (work@dff_async_reset) |vpiProcess: \_always: , line:108:2, endln:114:5 |vpiParent: - \_module: work@arbiter (work@arbiter), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/another_arbiter.v, line:2:1, endln:121:10 + \_module_inst: work@arbiter (work@arbiter), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/another_arbiter.v, line:2:1, endln:121:10 |vpiStmt: \_event_control: , line:108:8, endln:109:54 |vpiParent: @@ -4698,7 +4698,7 @@ design: (work@dff_async_reset) |vpiProcess: \_always: , line:115:2, endln:120:5 |vpiParent: - \_module: work@arbiter (work@arbiter), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/another_arbiter.v, line:2:1, endln:121:10 + \_module_inst: work@arbiter (work@arbiter), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/another_arbiter.v, line:2:1, endln:121:10 |vpiStmt: \_event_control: , line:115:8, endln:115:17 |vpiParent: @@ -4885,7 +4885,7 @@ design: (work@dff_async_reset) |vpiContAssign: \_cont_assign: , line:92:9, endln:92:40 |vpiParent: - \_module: work@arbiter (work@arbiter), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/another_arbiter.v, line:2:1, endln:121:10 + \_module_inst: work@arbiter (work@arbiter), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/another_arbiter.v, line:2:1, endln:121:10 |vpiRhs: \_operation: , line:92:23, endln:92:40 |vpiParent: @@ -4916,7 +4916,7 @@ design: (work@dff_async_reset) |vpiActual: \_logic_net: (work@top.U.prioRequest), line:44:24, endln:44:35 |uhdmallModules: -\_module: work@case1 (work@case1), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/m_input_mult.v, line:2:1, endln:18:10 +\_module_inst: work@case1 (work@case1), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/m_input_mult.v, line:2:1, endln:18:10 |vpiParent: \_design: (work@dff_async_reset) |vpiFullName:work@case1 @@ -4924,25 +4924,25 @@ design: (work@dff_async_reset) |vpiNet: \_logic_net: (work@case1.in1), line:2:15, endln:2:18 |vpiParent: - \_module: work@case1 (work@case1), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/m_input_mult.v, line:2:1, endln:18:10 + \_module_inst: work@case1 (work@case1), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/m_input_mult.v, line:2:1, endln:18:10 |vpiName:in1 |vpiFullName:work@case1.in1 |vpiNet: \_logic_net: (work@case1.in2), line:2:20, endln:2:23 |vpiParent: - \_module: work@case1 (work@case1), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/m_input_mult.v, line:2:1, endln:18:10 + \_module_inst: work@case1 (work@case1), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/m_input_mult.v, line:2:1, endln:18:10 |vpiName:in2 |vpiFullName:work@case1.in2 |vpiNet: \_logic_net: (work@case1.out2), line:2:25, endln:2:29 |vpiParent: - \_module: work@case1 (work@case1), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/m_input_mult.v, line:2:1, endln:18:10 + \_module_inst: work@case1 (work@case1), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/m_input_mult.v, line:2:1, endln:18:10 |vpiName:out2 |vpiFullName:work@case1.out2 |vpiPort: \_port: (in1), line:2:15, endln:2:18 |vpiParent: - \_module: work@case1 (work@case1), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/m_input_mult.v, line:2:1, endln:18:10 + \_module_inst: work@case1 (work@case1), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/m_input_mult.v, line:2:1, endln:18:10 |vpiName:in1 |vpiDirection:1 |vpiLowConn: @@ -4972,7 +4972,7 @@ design: (work@dff_async_reset) |vpiPort: \_port: (in2), line:2:20, endln:2:23 |vpiParent: - \_module: work@case1 (work@case1), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/m_input_mult.v, line:2:1, endln:18:10 + \_module_inst: work@case1 (work@case1), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/m_input_mult.v, line:2:1, endln:18:10 |vpiName:in2 |vpiDirection:1 |vpiLowConn: @@ -5002,7 +5002,7 @@ design: (work@dff_async_reset) |vpiPort: \_port: (out2), line:2:25, endln:2:29 |vpiParent: - \_module: work@case1 (work@case1), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/m_input_mult.v, line:2:1, endln:18:10 + \_module_inst: work@case1 (work@case1), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/m_input_mult.v, line:2:1, endln:18:10 |vpiName:out2 |vpiDirection:2 |vpiLowConn: @@ -5014,7 +5014,7 @@ design: (work@dff_async_reset) |vpiProcess: \_always: , line:6:1, endln:16:9 |vpiParent: - \_module: work@case1 (work@case1), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/m_input_mult.v, line:2:1, endln:18:10 + \_module_inst: work@case1 (work@case1), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/m_input_mult.v, line:2:1, endln:18:10 |vpiStmt: \_event_control: , line:6:7, endln:6:20 |vpiParent: @@ -5401,7 +5401,7 @@ design: (work@dff_async_reset) \_logic_net: (work@case1.out2), line:2:25, endln:2:29 |vpiAlwaysType:1 |uhdmallModules: -\_module: work@case2 (work@case2), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/m_input_mult.v, line:21:1, endln:46:10 +\_module_inst: work@case2 (work@case2), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/m_input_mult.v, line:21:1, endln:46:10 |vpiParent: \_design: (work@dff_async_reset) |vpiFullName:work@case2 @@ -5409,32 +5409,32 @@ design: (work@dff_async_reset) |vpiNet: \_logic_net: (work@case2.select), line:25:11, endln:25:17 |vpiParent: - \_module: work@case2 (work@case2), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/m_input_mult.v, line:21:1, endln:46:10 + \_module_inst: work@case2 (work@case2), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/m_input_mult.v, line:21:1, endln:46:10 |vpiName:select |vpiFullName:work@case2.select |vpiNetType:48 |vpiNet: \_logic_net: (work@case2.in1), line:21:15, endln:21:18 |vpiParent: - \_module: work@case2 (work@case2), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/m_input_mult.v, line:21:1, endln:46:10 + \_module_inst: work@case2 (work@case2), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/m_input_mult.v, line:21:1, endln:46:10 |vpiName:in1 |vpiFullName:work@case2.in1 |vpiNet: \_logic_net: (work@case2.sel), line:21:20, endln:21:23 |vpiParent: - \_module: work@case2 (work@case2), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/m_input_mult.v, line:21:1, endln:46:10 + \_module_inst: work@case2 (work@case2), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/m_input_mult.v, line:21:1, endln:46:10 |vpiName:sel |vpiFullName:work@case2.sel |vpiNet: \_logic_net: (work@case2.out2), line:21:25, endln:21:29 |vpiParent: - \_module: work@case2 (work@case2), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/m_input_mult.v, line:21:1, endln:46:10 + \_module_inst: work@case2 (work@case2), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/m_input_mult.v, line:21:1, endln:46:10 |vpiName:out2 |vpiFullName:work@case2.out2 |vpiPort: \_port: (in1), line:21:15, endln:21:18 |vpiParent: - \_module: work@case2 (work@case2), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/m_input_mult.v, line:21:1, endln:46:10 + \_module_inst: work@case2 (work@case2), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/m_input_mult.v, line:21:1, endln:46:10 |vpiName:in1 |vpiDirection:1 |vpiLowConn: @@ -5464,7 +5464,7 @@ design: (work@dff_async_reset) |vpiPort: \_port: (sel), line:21:20, endln:21:23 |vpiParent: - \_module: work@case2 (work@case2), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/m_input_mult.v, line:21:1, endln:46:10 + \_module_inst: work@case2 (work@case2), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/m_input_mult.v, line:21:1, endln:46:10 |vpiName:sel |vpiDirection:1 |vpiLowConn: @@ -5494,7 +5494,7 @@ design: (work@dff_async_reset) |vpiPort: \_port: (out2), line:21:25, endln:21:29 |vpiParent: - \_module: work@case2 (work@case2), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/m_input_mult.v, line:21:1, endln:46:10 + \_module_inst: work@case2 (work@case2), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/m_input_mult.v, line:21:1, endln:46:10 |vpiName:out2 |vpiDirection:2 |vpiLowConn: @@ -5524,7 +5524,7 @@ design: (work@dff_async_reset) |vpiProcess: \_always: , line:27:1, endln:37:9 |vpiParent: - \_module: work@case2 (work@case2), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/m_input_mult.v, line:21:1, endln:46:10 + \_module_inst: work@case2 (work@case2), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/m_input_mult.v, line:21:1, endln:46:10 |vpiStmt: \_event_control: , line:27:7, endln:27:13 |vpiParent: @@ -5826,7 +5826,7 @@ design: (work@dff_async_reset) |vpiContAssign: \_cont_assign: , line:38:9, endln:38:36 |vpiParent: - \_module: work@case2 (work@case2), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/m_input_mult.v, line:21:1, endln:46:10 + \_module_inst: work@case2 (work@case2), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/m_input_mult.v, line:21:1, endln:46:10 |vpiRhs: \_operation: , line:38:21, endln:38:36 |vpiParent: @@ -5883,7 +5883,7 @@ design: (work@dff_async_reset) |vpiContAssign: \_cont_assign: , line:39:9, endln:39:36 |vpiParent: - \_module: work@case2 (work@case2), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/m_input_mult.v, line:21:1, endln:46:10 + \_module_inst: work@case2 (work@case2), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/m_input_mult.v, line:21:1, endln:46:10 |vpiRhs: \_operation: , line:39:21, endln:39:36 |vpiParent: @@ -5940,7 +5940,7 @@ design: (work@dff_async_reset) |vpiContAssign: \_cont_assign: , line:40:9, endln:40:36 |vpiParent: - \_module: work@case2 (work@case2), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/m_input_mult.v, line:21:1, endln:46:10 + \_module_inst: work@case2 (work@case2), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/m_input_mult.v, line:21:1, endln:46:10 |vpiRhs: \_operation: , line:40:21, endln:40:36 |vpiParent: @@ -5997,7 +5997,7 @@ design: (work@dff_async_reset) |vpiContAssign: \_cont_assign: , line:41:9, endln:41:36 |vpiParent: - \_module: work@case2 (work@case2), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/m_input_mult.v, line:21:1, endln:46:10 + \_module_inst: work@case2 (work@case2), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/m_input_mult.v, line:21:1, endln:46:10 |vpiRhs: \_operation: , line:41:21, endln:41:36 |vpiParent: @@ -6054,7 +6054,7 @@ design: (work@dff_async_reset) |vpiContAssign: \_cont_assign: , line:42:9, endln:42:36 |vpiParent: - \_module: work@case2 (work@case2), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/m_input_mult.v, line:21:1, endln:46:10 + \_module_inst: work@case2 (work@case2), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/m_input_mult.v, line:21:1, endln:46:10 |vpiRhs: \_operation: , line:42:21, endln:42:36 |vpiParent: @@ -6111,7 +6111,7 @@ design: (work@dff_async_reset) |vpiContAssign: \_cont_assign: , line:43:9, endln:43:38 |vpiParent: - \_module: work@case2 (work@case2), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/m_input_mult.v, line:21:1, endln:46:10 + \_module_inst: work@case2 (work@case2), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/m_input_mult.v, line:21:1, endln:46:10 |vpiRhs: \_operation: , line:43:23, endln:43:38 |vpiParent: @@ -6168,7 +6168,7 @@ design: (work@dff_async_reset) |vpiContAssign: \_cont_assign: , line:44:9, endln:44:38 |vpiParent: - \_module: work@case2 (work@case2), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/m_input_mult.v, line:21:1, endln:46:10 + \_module_inst: work@case2 (work@case2), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/m_input_mult.v, line:21:1, endln:46:10 |vpiRhs: \_operation: , line:44:23, endln:44:38 |vpiParent: @@ -6225,7 +6225,7 @@ design: (work@dff_async_reset) |vpiContAssign: \_cont_assign: , line:45:9, endln:45:38 |vpiParent: - \_module: work@case2 (work@case2), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/m_input_mult.v, line:21:1, endln:46:10 + \_module_inst: work@case2 (work@case2), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/m_input_mult.v, line:21:1, endln:46:10 |vpiRhs: \_operation: , line:45:23, endln:45:38 |vpiParent: @@ -6280,7 +6280,7 @@ design: (work@dff_async_reset) |UINT:14 |vpiConstType:9 |uhdmallModules: -\_module: work@dff_async_reset (work@dff_async_reset), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/dff.v, line:8:1, endln:31:10 +\_module_inst: work@dff_async_reset (work@dff_async_reset), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/dff.v, line:8:1, endln:31:10 |vpiParent: \_design: (work@dff_async_reset) |vpiFullName:work@dff_async_reset @@ -6288,32 +6288,32 @@ design: (work@dff_async_reset) |vpiNet: \_logic_net: (work@dff_async_reset.q), line:21:5, endln:21:6 |vpiParent: - \_module: work@dff_async_reset (work@dff_async_reset), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/dff.v, line:8:1, endln:31:10 + \_module_inst: work@dff_async_reset (work@dff_async_reset), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/dff.v, line:8:1, endln:31:10 |vpiName:q |vpiFullName:work@dff_async_reset.q |vpiNetType:48 |vpiNet: \_logic_net: (work@dff_async_reset.data), line:9:1, endln:9:5 |vpiParent: - \_module: work@dff_async_reset (work@dff_async_reset), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/dff.v, line:8:1, endln:31:10 + \_module_inst: work@dff_async_reset (work@dff_async_reset), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/dff.v, line:8:1, endln:31:10 |vpiName:data |vpiFullName:work@dff_async_reset.data |vpiNet: \_logic_net: (work@dff_async_reset.clk), line:10:1, endln:10:4 |vpiParent: - \_module: work@dff_async_reset (work@dff_async_reset), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/dff.v, line:8:1, endln:31:10 + \_module_inst: work@dff_async_reset (work@dff_async_reset), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/dff.v, line:8:1, endln:31:10 |vpiName:clk |vpiFullName:work@dff_async_reset.clk |vpiNet: \_logic_net: (work@dff_async_reset.reset), line:11:1, endln:11:6 |vpiParent: - \_module: work@dff_async_reset (work@dff_async_reset), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/dff.v, line:8:1, endln:31:10 + \_module_inst: work@dff_async_reset (work@dff_async_reset), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/dff.v, line:8:1, endln:31:10 |vpiName:reset |vpiFullName:work@dff_async_reset.reset |vpiPort: \_port: (data), line:9:1, endln:9:5 |vpiParent: - \_module: work@dff_async_reset (work@dff_async_reset), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/dff.v, line:8:1, endln:31:10 + \_module_inst: work@dff_async_reset (work@dff_async_reset), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/dff.v, line:8:1, endln:31:10 |vpiName:data |vpiDirection:1 |vpiLowConn: @@ -6325,7 +6325,7 @@ design: (work@dff_async_reset) |vpiPort: \_port: (clk), line:10:1, endln:10:4 |vpiParent: - \_module: work@dff_async_reset (work@dff_async_reset), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/dff.v, line:8:1, endln:31:10 + \_module_inst: work@dff_async_reset (work@dff_async_reset), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/dff.v, line:8:1, endln:31:10 |vpiName:clk |vpiDirection:1 |vpiLowConn: @@ -6337,7 +6337,7 @@ design: (work@dff_async_reset) |vpiPort: \_port: (reset), line:11:1, endln:11:6 |vpiParent: - \_module: work@dff_async_reset (work@dff_async_reset), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/dff.v, line:8:1, endln:31:10 + \_module_inst: work@dff_async_reset (work@dff_async_reset), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/dff.v, line:8:1, endln:31:10 |vpiName:reset |vpiDirection:1 |vpiLowConn: @@ -6349,7 +6349,7 @@ design: (work@dff_async_reset) |vpiPort: \_port: (q), line:12:1, endln:12:2 |vpiParent: - \_module: work@dff_async_reset (work@dff_async_reset), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/dff.v, line:8:1, endln:31:10 + \_module_inst: work@dff_async_reset (work@dff_async_reset), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/dff.v, line:8:1, endln:31:10 |vpiName:q |vpiDirection:2 |vpiLowConn: @@ -6361,7 +6361,7 @@ design: (work@dff_async_reset) |vpiProcess: \_always: , line:24:1, endln:29:4 |vpiParent: - \_module: work@dff_async_reset (work@dff_async_reset), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/dff.v, line:8:1, endln:31:10 + \_module_inst: work@dff_async_reset (work@dff_async_reset), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/dff.v, line:8:1, endln:31:10 |vpiStmt: \_event_control: , line:24:8, endln:24:41 |vpiParent: @@ -6462,7 +6462,7 @@ design: (work@dff_async_reset) \_logic_net: (work@dff_async_reset.q), line:21:5, endln:21:6 |vpiAlwaysType:1 |uhdmallModules: -\_module: work@encoder_using_case (work@encoder_using_case), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/encoder.v, line:7:1, endln:43:10 +\_module_inst: work@encoder_using_case (work@encoder_using_case), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/encoder.v, line:7:1, endln:43:10 |vpiParent: \_design: (work@dff_async_reset) |vpiFullName:work@encoder_using_case @@ -6470,26 +6470,26 @@ design: (work@dff_async_reset) |vpiNet: \_logic_net: (work@encoder_using_case.binary_out), line:17:11, endln:17:21 |vpiParent: - \_module: work@encoder_using_case (work@encoder_using_case), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/encoder.v, line:7:1, endln:43:10 + \_module_inst: work@encoder_using_case (work@encoder_using_case), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/encoder.v, line:7:1, endln:43:10 |vpiName:binary_out |vpiFullName:work@encoder_using_case.binary_out |vpiNetType:48 |vpiNet: \_logic_net: (work@encoder_using_case.encoder_in), line:9:1, endln:9:11 |vpiParent: - \_module: work@encoder_using_case (work@encoder_using_case), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/encoder.v, line:7:1, endln:43:10 + \_module_inst: work@encoder_using_case (work@encoder_using_case), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/encoder.v, line:7:1, endln:43:10 |vpiName:encoder_in |vpiFullName:work@encoder_using_case.encoder_in |vpiNet: \_logic_net: (work@encoder_using_case.enable), line:10:1, endln:10:7 |vpiParent: - \_module: work@encoder_using_case (work@encoder_using_case), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/encoder.v, line:7:1, endln:43:10 + \_module_inst: work@encoder_using_case (work@encoder_using_case), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/encoder.v, line:7:1, endln:43:10 |vpiName:enable |vpiFullName:work@encoder_using_case.enable |vpiPort: \_port: (binary_out), line:8:1, endln:8:11 |vpiParent: - \_module: work@encoder_using_case (work@encoder_using_case), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/encoder.v, line:7:1, endln:43:10 + \_module_inst: work@encoder_using_case (work@encoder_using_case), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/encoder.v, line:7:1, endln:43:10 |vpiName:binary_out |vpiDirection:2 |vpiLowConn: @@ -6519,7 +6519,7 @@ design: (work@dff_async_reset) |vpiPort: \_port: (encoder_in), line:9:1, endln:9:11 |vpiParent: - \_module: work@encoder_using_case (work@encoder_using_case), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/encoder.v, line:7:1, endln:43:10 + \_module_inst: work@encoder_using_case (work@encoder_using_case), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/encoder.v, line:7:1, endln:43:10 |vpiName:encoder_in |vpiDirection:1 |vpiLowConn: @@ -6549,7 +6549,7 @@ design: (work@dff_async_reset) |vpiPort: \_port: (enable), line:10:1, endln:10:7 |vpiParent: - \_module: work@encoder_using_case (work@encoder_using_case), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/encoder.v, line:7:1, endln:43:10 + \_module_inst: work@encoder_using_case (work@encoder_using_case), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/encoder.v, line:7:1, endln:43:10 |vpiName:enable |vpiDirection:1 |vpiLowConn: @@ -6561,7 +6561,7 @@ design: (work@dff_async_reset) |vpiProcess: \_always: , line:19:1, endln:41:4 |vpiParent: - \_module: work@encoder_using_case (work@encoder_using_case), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/encoder.v, line:7:1, endln:43:10 + \_module_inst: work@encoder_using_case (work@encoder_using_case), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/encoder.v, line:7:1, endln:43:10 |vpiStmt: \_event_control: , line:19:8, endln:19:32 |vpiParent: @@ -7150,7 +7150,7 @@ design: (work@dff_async_reset) \_logic_net: (work@encoder_using_case.binary_out), line:17:11, endln:17:21 |vpiAlwaysType:1 |uhdmallModules: -\_module: work@full_adder_gates (work@full_adder_gates), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/full_adder.v, line:7:1, endln:18:10 +\_module_inst: work@full_adder_gates (work@full_adder_gates), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/full_adder.v, line:7:1, endln:18:10 |vpiParent: \_design: (work@dff_async_reset) |vpiFullName:work@full_adder_gates @@ -7158,65 +7158,65 @@ design: (work@dff_async_reset) |vpiNet: \_logic_net: (work@full_adder_gates.and1), line:10:6, endln:10:10 |vpiParent: - \_module: work@full_adder_gates (work@full_adder_gates), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/full_adder.v, line:7:1, endln:18:10 + \_module_inst: work@full_adder_gates (work@full_adder_gates), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/full_adder.v, line:7:1, endln:18:10 |vpiName:and1 |vpiFullName:work@full_adder_gates.and1 |vpiNetType:1 |vpiNet: \_logic_net: (work@full_adder_gates.and2), line:10:11, endln:10:15 |vpiParent: - \_module: work@full_adder_gates (work@full_adder_gates), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/full_adder.v, line:7:1, endln:18:10 + \_module_inst: work@full_adder_gates (work@full_adder_gates), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/full_adder.v, line:7:1, endln:18:10 |vpiName:and2 |vpiFullName:work@full_adder_gates.and2 |vpiNetType:1 |vpiNet: \_logic_net: (work@full_adder_gates.and3), line:10:16, endln:10:20 |vpiParent: - \_module: work@full_adder_gates (work@full_adder_gates), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/full_adder.v, line:7:1, endln:18:10 + \_module_inst: work@full_adder_gates (work@full_adder_gates), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/full_adder.v, line:7:1, endln:18:10 |vpiName:and3 |vpiFullName:work@full_adder_gates.and3 |vpiNetType:1 |vpiNet: \_logic_net: (work@full_adder_gates.sum1), line:10:21, endln:10:25 |vpiParent: - \_module: work@full_adder_gates (work@full_adder_gates), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/full_adder.v, line:7:1, endln:18:10 + \_module_inst: work@full_adder_gates (work@full_adder_gates), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/full_adder.v, line:7:1, endln:18:10 |vpiName:sum1 |vpiFullName:work@full_adder_gates.sum1 |vpiNetType:1 |vpiNet: \_logic_net: (work@full_adder_gates.x), line:7:25, endln:7:26 |vpiParent: - \_module: work@full_adder_gates (work@full_adder_gates), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/full_adder.v, line:7:1, endln:18:10 + \_module_inst: work@full_adder_gates (work@full_adder_gates), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/full_adder.v, line:7:1, endln:18:10 |vpiName:x |vpiFullName:work@full_adder_gates.x |vpiNet: \_logic_net: (work@full_adder_gates.y), line:7:27, endln:7:28 |vpiParent: - \_module: work@full_adder_gates (work@full_adder_gates), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/full_adder.v, line:7:1, endln:18:10 + \_module_inst: work@full_adder_gates (work@full_adder_gates), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/full_adder.v, line:7:1, endln:18:10 |vpiName:y |vpiFullName:work@full_adder_gates.y |vpiNet: \_logic_net: (work@full_adder_gates.z), line:7:29, endln:7:30 |vpiParent: - \_module: work@full_adder_gates (work@full_adder_gates), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/full_adder.v, line:7:1, endln:18:10 + \_module_inst: work@full_adder_gates (work@full_adder_gates), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/full_adder.v, line:7:1, endln:18:10 |vpiName:z |vpiFullName:work@full_adder_gates.z |vpiNet: \_logic_net: (work@full_adder_gates.sum), line:7:31, endln:7:34 |vpiParent: - \_module: work@full_adder_gates (work@full_adder_gates), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/full_adder.v, line:7:1, endln:18:10 + \_module_inst: work@full_adder_gates (work@full_adder_gates), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/full_adder.v, line:7:1, endln:18:10 |vpiName:sum |vpiFullName:work@full_adder_gates.sum |vpiNet: \_logic_net: (work@full_adder_gates.carry), line:7:35, endln:7:40 |vpiParent: - \_module: work@full_adder_gates (work@full_adder_gates), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/full_adder.v, line:7:1, endln:18:10 + \_module_inst: work@full_adder_gates (work@full_adder_gates), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/full_adder.v, line:7:1, endln:18:10 |vpiName:carry |vpiFullName:work@full_adder_gates.carry |vpiPort: \_port: (x), line:7:25, endln:7:26 |vpiParent: - \_module: work@full_adder_gates (work@full_adder_gates), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/full_adder.v, line:7:1, endln:18:10 + \_module_inst: work@full_adder_gates (work@full_adder_gates), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/full_adder.v, line:7:1, endln:18:10 |vpiName:x |vpiDirection:1 |vpiLowConn: @@ -7228,7 +7228,7 @@ design: (work@dff_async_reset) |vpiPort: \_port: (y), line:7:27, endln:7:28 |vpiParent: - \_module: work@full_adder_gates (work@full_adder_gates), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/full_adder.v, line:7:1, endln:18:10 + \_module_inst: work@full_adder_gates (work@full_adder_gates), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/full_adder.v, line:7:1, endln:18:10 |vpiName:y |vpiDirection:1 |vpiLowConn: @@ -7240,7 +7240,7 @@ design: (work@dff_async_reset) |vpiPort: \_port: (z), line:7:29, endln:7:30 |vpiParent: - \_module: work@full_adder_gates (work@full_adder_gates), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/full_adder.v, line:7:1, endln:18:10 + \_module_inst: work@full_adder_gates (work@full_adder_gates), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/full_adder.v, line:7:1, endln:18:10 |vpiName:z |vpiDirection:1 |vpiLowConn: @@ -7252,7 +7252,7 @@ design: (work@dff_async_reset) |vpiPort: \_port: (sum), line:7:31, endln:7:34 |vpiParent: - \_module: work@full_adder_gates (work@full_adder_gates), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/full_adder.v, line:7:1, endln:18:10 + \_module_inst: work@full_adder_gates (work@full_adder_gates), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/full_adder.v, line:7:1, endln:18:10 |vpiName:sum |vpiDirection:2 |vpiLowConn: @@ -7264,7 +7264,7 @@ design: (work@dff_async_reset) |vpiPort: \_port: (carry), line:7:35, endln:7:40 |vpiParent: - \_module: work@full_adder_gates (work@full_adder_gates), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/full_adder.v, line:7:1, endln:18:10 + \_module_inst: work@full_adder_gates (work@full_adder_gates), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/full_adder.v, line:7:1, endln:18:10 |vpiName:carry |vpiDirection:2 |vpiLowConn: @@ -7274,7 +7274,7 @@ design: (work@dff_async_reset) |vpiTypedef: \_logic_typespec: , line:9:8, endln:9:8 |uhdmallModules: -\_module: work@mux21_switch (work@mux21_switch), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/mux21.v, line:7:1, endln:22:10 +\_module_inst: work@mux21_switch (work@mux21_switch), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/mux21.v, line:7:1, endln:22:10 |vpiParent: \_design: (work@dff_async_reset) |vpiFullName:work@mux21_switch @@ -7282,52 +7282,52 @@ design: (work@dff_async_reset) |vpiNet: \_logic_net: (work@mux21_switch.e), line:11:18, endln:11:19 |vpiParent: - \_module: work@mux21_switch (work@mux21_switch), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/mux21.v, line:7:1, endln:22:10 + \_module_inst: work@mux21_switch (work@mux21_switch), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/mux21.v, line:7:1, endln:22:10 |vpiName:e |vpiFullName:work@mux21_switch.e |vpiNetType:1 |vpiNet: \_logic_net: (work@mux21_switch.power), line:13:12, endln:13:17 |vpiParent: - \_module: work@mux21_switch (work@mux21_switch), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/mux21.v, line:7:1, endln:22:10 + \_module_inst: work@mux21_switch (work@mux21_switch), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/mux21.v, line:7:1, endln:22:10 |vpiName:power |vpiFullName:work@mux21_switch.power |vpiNetType:10 |vpiNet: \_logic_net: (work@mux21_switch.ground), line:14:12, endln:14:18 |vpiParent: - \_module: work@mux21_switch (work@mux21_switch), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/mux21.v, line:7:1, endln:22:10 + \_module_inst: work@mux21_switch (work@mux21_switch), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/mux21.v, line:7:1, endln:22:10 |vpiName:ground |vpiFullName:work@mux21_switch.ground |vpiNetType:11 |vpiNet: \_logic_net: (work@mux21_switch.out), line:7:22, endln:7:25 |vpiParent: - \_module: work@mux21_switch (work@mux21_switch), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/mux21.v, line:7:1, endln:22:10 + \_module_inst: work@mux21_switch (work@mux21_switch), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/mux21.v, line:7:1, endln:22:10 |vpiName:out |vpiFullName:work@mux21_switch.out |vpiNet: \_logic_net: (work@mux21_switch.ctrl), line:7:27, endln:7:31 |vpiParent: - \_module: work@mux21_switch (work@mux21_switch), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/mux21.v, line:7:1, endln:22:10 + \_module_inst: work@mux21_switch (work@mux21_switch), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/mux21.v, line:7:1, endln:22:10 |vpiName:ctrl |vpiFullName:work@mux21_switch.ctrl |vpiNet: \_logic_net: (work@mux21_switch.in1), line:7:33, endln:7:36 |vpiParent: - \_module: work@mux21_switch (work@mux21_switch), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/mux21.v, line:7:1, endln:22:10 + \_module_inst: work@mux21_switch (work@mux21_switch), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/mux21.v, line:7:1, endln:22:10 |vpiName:in1 |vpiFullName:work@mux21_switch.in1 |vpiNet: \_logic_net: (work@mux21_switch.in2), line:7:38, endln:7:41 |vpiParent: - \_module: work@mux21_switch (work@mux21_switch), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/mux21.v, line:7:1, endln:22:10 + \_module_inst: work@mux21_switch (work@mux21_switch), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/mux21.v, line:7:1, endln:22:10 |vpiName:in2 |vpiFullName:work@mux21_switch.in2 |vpiPort: \_port: (out), line:7:22, endln:7:25 |vpiParent: - \_module: work@mux21_switch (work@mux21_switch), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/mux21.v, line:7:1, endln:22:10 + \_module_inst: work@mux21_switch (work@mux21_switch), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/mux21.v, line:7:1, endln:22:10 |vpiName:out |vpiDirection:2 |vpiLowConn: @@ -7339,7 +7339,7 @@ design: (work@dff_async_reset) |vpiPort: \_port: (ctrl), line:7:27, endln:7:31 |vpiParent: - \_module: work@mux21_switch (work@mux21_switch), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/mux21.v, line:7:1, endln:22:10 + \_module_inst: work@mux21_switch (work@mux21_switch), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/mux21.v, line:7:1, endln:22:10 |vpiName:ctrl |vpiDirection:1 |vpiLowConn: @@ -7351,7 +7351,7 @@ design: (work@dff_async_reset) |vpiPort: \_port: (in1), line:7:33, endln:7:36 |vpiParent: - \_module: work@mux21_switch (work@mux21_switch), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/mux21.v, line:7:1, endln:22:10 + \_module_inst: work@mux21_switch (work@mux21_switch), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/mux21.v, line:7:1, endln:22:10 |vpiName:in1 |vpiDirection:1 |vpiLowConn: @@ -7363,7 +7363,7 @@ design: (work@dff_async_reset) |vpiPort: \_port: (in2), line:7:38, endln:7:41 |vpiParent: - \_module: work@mux21_switch (work@mux21_switch), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/mux21.v, line:7:1, endln:22:10 + \_module_inst: work@mux21_switch (work@mux21_switch), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/mux21.v, line:7:1, endln:22:10 |vpiName:in2 |vpiDirection:1 |vpiLowConn: @@ -7373,7 +7373,7 @@ design: (work@dff_async_reset) |vpiTypedef: \_logic_typespec: , line:10:11, endln:10:11 |uhdmallModules: -\_module: work@pri_encooder (work@pri_encooder), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/m_input_mult.v, line:49:1, endln:73:10 +\_module_inst: work@pri_encooder (work@pri_encooder), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/m_input_mult.v, line:49:1, endln:73:10 |vpiParent: \_design: (work@dff_async_reset) |vpiFullName:work@pri_encooder @@ -7381,31 +7381,31 @@ design: (work@dff_async_reset) |vpiNet: \_logic_net: (work@pri_encooder.Op), line:49:22, endln:49:24 |vpiParent: - \_module: work@pri_encooder (work@pri_encooder), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/m_input_mult.v, line:49:1, endln:73:10 + \_module_inst: work@pri_encooder (work@pri_encooder), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/m_input_mult.v, line:49:1, endln:73:10 |vpiName:Op |vpiFullName:work@pri_encooder.Op |vpiNet: \_logic_net: (work@pri_encooder.Funct), line:49:26, endln:49:31 |vpiParent: - \_module: work@pri_encooder (work@pri_encooder), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/m_input_mult.v, line:49:1, endln:73:10 + \_module_inst: work@pri_encooder (work@pri_encooder), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/m_input_mult.v, line:49:1, endln:73:10 |vpiName:Funct |vpiFullName:work@pri_encooder.Funct |vpiNet: \_logic_net: (work@pri_encooder.Sel), line:49:33, endln:49:36 |vpiParent: - \_module: work@pri_encooder (work@pri_encooder), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/m_input_mult.v, line:49:1, endln:73:10 + \_module_inst: work@pri_encooder (work@pri_encooder), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/m_input_mult.v, line:49:1, endln:73:10 |vpiName:Sel |vpiFullName:work@pri_encooder.Sel |vpiNet: \_logic_net: (work@pri_encooder.B), line:49:38, endln:49:39 |vpiParent: - \_module: work@pri_encooder (work@pri_encooder), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/m_input_mult.v, line:49:1, endln:73:10 + \_module_inst: work@pri_encooder (work@pri_encooder), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/m_input_mult.v, line:49:1, endln:73:10 |vpiName:B |vpiFullName:work@pri_encooder.B |vpiPort: \_port: (Op), line:49:22, endln:49:24 |vpiParent: - \_module: work@pri_encooder (work@pri_encooder), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/m_input_mult.v, line:49:1, endln:73:10 + \_module_inst: work@pri_encooder (work@pri_encooder), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/m_input_mult.v, line:49:1, endln:73:10 |vpiName:Op |vpiDirection:1 |vpiLowConn: @@ -7435,7 +7435,7 @@ design: (work@dff_async_reset) |vpiPort: \_port: (Funct), line:49:26, endln:49:31 |vpiParent: - \_module: work@pri_encooder (work@pri_encooder), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/m_input_mult.v, line:49:1, endln:73:10 + \_module_inst: work@pri_encooder (work@pri_encooder), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/m_input_mult.v, line:49:1, endln:73:10 |vpiName:Funct |vpiDirection:1 |vpiLowConn: @@ -7465,7 +7465,7 @@ design: (work@dff_async_reset) |vpiPort: \_port: (Sel), line:49:33, endln:49:36 |vpiParent: - \_module: work@pri_encooder (work@pri_encooder), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/m_input_mult.v, line:49:1, endln:73:10 + \_module_inst: work@pri_encooder (work@pri_encooder), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/m_input_mult.v, line:49:1, endln:73:10 |vpiName:Sel |vpiDirection:2 |vpiLowConn: @@ -7495,7 +7495,7 @@ design: (work@dff_async_reset) |vpiPort: \_port: (B), line:49:38, endln:49:39 |vpiParent: - \_module: work@pri_encooder (work@pri_encooder), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/m_input_mult.v, line:49:1, endln:73:10 + \_module_inst: work@pri_encooder (work@pri_encooder), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/m_input_mult.v, line:49:1, endln:73:10 |vpiName:B |vpiDirection:2 |vpiLowConn: @@ -7507,7 +7507,7 @@ design: (work@dff_async_reset) |vpiProcess: \_always: , line:54:1, endln:72:9 |vpiParent: - \_module: work@pri_encooder (work@pri_encooder), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/m_input_mult.v, line:49:1, endln:73:10 + \_module_inst: work@pri_encooder (work@pri_encooder), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/m_input_mult.v, line:49:1, endln:73:10 |vpiStmt: \_event_control: , line:54:7, endln:54:21 |vpiParent: @@ -7830,14 +7830,14 @@ design: (work@dff_async_reset) \_logic_net: (work@pri_encooder.B), line:49:38, endln:49:39 |vpiAlwaysType:1 |uhdmallModules: -\_module: work@syn_fifo (work@syn_fifo), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/synfifo.v, line:8:1, endln:104:10 +\_module_inst: work@syn_fifo (work@syn_fifo), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/synfifo.v, line:8:1, endln:104:10 |vpiParent: \_design: (work@dff_async_reset) |vpiFullName:work@syn_fifo |vpiParameter: \_parameter: (work@syn_fifo.DATA_WIDTH), line:22:11, endln:22:21 |vpiParent: - \_module: work@syn_fifo (work@syn_fifo), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/synfifo.v, line:8:1, endln:104:10 + \_module_inst: work@syn_fifo (work@syn_fifo), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/synfifo.v, line:8:1, endln:104:10 |UINT:8 |vpiTypespec: \_int_typespec: @@ -7846,7 +7846,7 @@ design: (work@dff_async_reset) |vpiParameter: \_parameter: (work@syn_fifo.ADDR_WIDTH), line:23:11, endln:23:21 |vpiParent: - \_module: work@syn_fifo (work@syn_fifo), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/synfifo.v, line:8:1, endln:104:10 + \_module_inst: work@syn_fifo (work@syn_fifo), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/synfifo.v, line:8:1, endln:104:10 |UINT:8 |vpiTypespec: \_int_typespec: @@ -7855,13 +7855,13 @@ design: (work@dff_async_reset) |vpiParameter: \_parameter: (work@syn_fifo.RAM_DEPTH), line:24:11, endln:24:20 |vpiParent: - \_module: work@syn_fifo (work@syn_fifo), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/synfifo.v, line:8:1, endln:104:10 + \_module_inst: work@syn_fifo (work@syn_fifo), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/synfifo.v, line:8:1, endln:104:10 |vpiName:RAM_DEPTH |vpiFullName:work@syn_fifo.RAM_DEPTH |vpiParamAssign: \_param_assign: , line:22:11, endln:22:25 |vpiParent: - \_module: work@syn_fifo (work@syn_fifo), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/synfifo.v, line:8:1, endln:104:10 + \_module_inst: work@syn_fifo (work@syn_fifo), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/synfifo.v, line:8:1, endln:104:10 |vpiRhs: \_constant: , line:22:24, endln:22:25 |vpiDecompile:8 @@ -7875,7 +7875,7 @@ design: (work@dff_async_reset) |vpiParamAssign: \_param_assign: , line:23:11, endln:23:25 |vpiParent: - \_module: work@syn_fifo (work@syn_fifo), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/synfifo.v, line:8:1, endln:104:10 + \_module_inst: work@syn_fifo (work@syn_fifo), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/synfifo.v, line:8:1, endln:104:10 |vpiRhs: \_constant: , line:23:24, endln:23:25 |vpiDecompile:8 @@ -7889,7 +7889,7 @@ design: (work@dff_async_reset) |vpiParamAssign: \_param_assign: , line:24:11, endln:24:40 |vpiParent: - \_module: work@syn_fifo (work@syn_fifo), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/synfifo.v, line:8:1, endln:104:10 + \_module_inst: work@syn_fifo (work@syn_fifo), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/synfifo.v, line:8:1, endln:104:10 |vpiRhs: \_operation: , line:24:24, endln:24:39 |vpiOpType:22 @@ -7912,96 +7912,96 @@ design: (work@dff_async_reset) |vpiNet: \_logic_net: (work@syn_fifo.wr_pointer), line:38:22, endln:38:32 |vpiParent: - \_module: work@syn_fifo (work@syn_fifo), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/synfifo.v, line:8:1, endln:104:10 + \_module_inst: work@syn_fifo (work@syn_fifo), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/synfifo.v, line:8:1, endln:104:10 |vpiName:wr_pointer |vpiFullName:work@syn_fifo.wr_pointer |vpiNetType:48 |vpiNet: \_logic_net: (work@syn_fifo.rd_pointer), line:39:22, endln:39:32 |vpiParent: - \_module: work@syn_fifo (work@syn_fifo), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/synfifo.v, line:8:1, endln:104:10 + \_module_inst: work@syn_fifo (work@syn_fifo), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/synfifo.v, line:8:1, endln:104:10 |vpiName:rd_pointer |vpiFullName:work@syn_fifo.rd_pointer |vpiNetType:48 |vpiNet: \_logic_net: (work@syn_fifo.status_cnt), line:40:21, endln:40:31 |vpiParent: - \_module: work@syn_fifo (work@syn_fifo), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/synfifo.v, line:8:1, endln:104:10 + \_module_inst: work@syn_fifo (work@syn_fifo), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/synfifo.v, line:8:1, endln:104:10 |vpiName:status_cnt |vpiFullName:work@syn_fifo.status_cnt |vpiNetType:48 |vpiNet: \_logic_net: (work@syn_fifo.data_out), line:41:22, endln:41:30 |vpiParent: - \_module: work@syn_fifo (work@syn_fifo), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/synfifo.v, line:8:1, endln:104:10 + \_module_inst: work@syn_fifo (work@syn_fifo), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/synfifo.v, line:8:1, endln:104:10 |vpiName:data_out |vpiFullName:work@syn_fifo.data_out |vpiNetType:48 |vpiNet: \_logic_net: (work@syn_fifo.data_ram), line:42:23, endln:42:31 |vpiParent: - \_module: work@syn_fifo (work@syn_fifo), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/synfifo.v, line:8:1, endln:104:10 + \_module_inst: work@syn_fifo (work@syn_fifo), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/synfifo.v, line:8:1, endln:104:10 |vpiName:data_ram |vpiFullName:work@syn_fifo.data_ram |vpiNetType:1 |vpiNet: \_logic_net: (work@syn_fifo.clk), line:9:1, endln:9:4 |vpiParent: - \_module: work@syn_fifo (work@syn_fifo), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/synfifo.v, line:8:1, endln:104:10 + \_module_inst: work@syn_fifo (work@syn_fifo), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/synfifo.v, line:8:1, endln:104:10 |vpiName:clk |vpiFullName:work@syn_fifo.clk |vpiNet: \_logic_net: (work@syn_fifo.rst), line:10:1, endln:10:4 |vpiParent: - \_module: work@syn_fifo (work@syn_fifo), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/synfifo.v, line:8:1, endln:104:10 + \_module_inst: work@syn_fifo (work@syn_fifo), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/synfifo.v, line:8:1, endln:104:10 |vpiName:rst |vpiFullName:work@syn_fifo.rst |vpiNet: \_logic_net: (work@syn_fifo.wr_cs), line:11:1, endln:11:6 |vpiParent: - \_module: work@syn_fifo (work@syn_fifo), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/synfifo.v, line:8:1, endln:104:10 + \_module_inst: work@syn_fifo (work@syn_fifo), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/synfifo.v, line:8:1, endln:104:10 |vpiName:wr_cs |vpiFullName:work@syn_fifo.wr_cs |vpiNet: \_logic_net: (work@syn_fifo.rd_cs), line:12:1, endln:12:6 |vpiParent: - \_module: work@syn_fifo (work@syn_fifo), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/synfifo.v, line:8:1, endln:104:10 + \_module_inst: work@syn_fifo (work@syn_fifo), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/synfifo.v, line:8:1, endln:104:10 |vpiName:rd_cs |vpiFullName:work@syn_fifo.rd_cs |vpiNet: \_logic_net: (work@syn_fifo.data_in), line:13:1, endln:13:8 |vpiParent: - \_module: work@syn_fifo (work@syn_fifo), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/synfifo.v, line:8:1, endln:104:10 + \_module_inst: work@syn_fifo (work@syn_fifo), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/synfifo.v, line:8:1, endln:104:10 |vpiName:data_in |vpiFullName:work@syn_fifo.data_in |vpiNet: \_logic_net: (work@syn_fifo.rd_en), line:14:1, endln:14:6 |vpiParent: - \_module: work@syn_fifo (work@syn_fifo), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/synfifo.v, line:8:1, endln:104:10 + \_module_inst: work@syn_fifo (work@syn_fifo), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/synfifo.v, line:8:1, endln:104:10 |vpiName:rd_en |vpiFullName:work@syn_fifo.rd_en |vpiNet: \_logic_net: (work@syn_fifo.wr_en), line:15:1, endln:15:6 |vpiParent: - \_module: work@syn_fifo (work@syn_fifo), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/synfifo.v, line:8:1, endln:104:10 + \_module_inst: work@syn_fifo (work@syn_fifo), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/synfifo.v, line:8:1, endln:104:10 |vpiName:wr_en |vpiFullName:work@syn_fifo.wr_en |vpiNet: \_logic_net: (work@syn_fifo.empty), line:17:1, endln:17:6 |vpiParent: - \_module: work@syn_fifo (work@syn_fifo), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/synfifo.v, line:8:1, endln:104:10 + \_module_inst: work@syn_fifo (work@syn_fifo), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/synfifo.v, line:8:1, endln:104:10 |vpiName:empty |vpiFullName:work@syn_fifo.empty |vpiNet: \_logic_net: (work@syn_fifo.full), line:18:1, endln:18:5 |vpiParent: - \_module: work@syn_fifo (work@syn_fifo), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/synfifo.v, line:8:1, endln:104:10 + \_module_inst: work@syn_fifo (work@syn_fifo), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/synfifo.v, line:8:1, endln:104:10 |vpiName:full |vpiFullName:work@syn_fifo.full |vpiPort: \_port: (clk), line:9:1, endln:9:4 |vpiParent: - \_module: work@syn_fifo (work@syn_fifo), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/synfifo.v, line:8:1, endln:104:10 + \_module_inst: work@syn_fifo (work@syn_fifo), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/synfifo.v, line:8:1, endln:104:10 |vpiName:clk |vpiDirection:1 |vpiLowConn: @@ -8013,7 +8013,7 @@ design: (work@dff_async_reset) |vpiPort: \_port: (rst), line:10:1, endln:10:4 |vpiParent: - \_module: work@syn_fifo (work@syn_fifo), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/synfifo.v, line:8:1, endln:104:10 + \_module_inst: work@syn_fifo (work@syn_fifo), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/synfifo.v, line:8:1, endln:104:10 |vpiName:rst |vpiDirection:1 |vpiLowConn: @@ -8025,7 +8025,7 @@ design: (work@dff_async_reset) |vpiPort: \_port: (wr_cs), line:11:1, endln:11:6 |vpiParent: - \_module: work@syn_fifo (work@syn_fifo), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/synfifo.v, line:8:1, endln:104:10 + \_module_inst: work@syn_fifo (work@syn_fifo), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/synfifo.v, line:8:1, endln:104:10 |vpiName:wr_cs |vpiDirection:1 |vpiLowConn: @@ -8037,7 +8037,7 @@ design: (work@dff_async_reset) |vpiPort: \_port: (rd_cs), line:12:1, endln:12:6 |vpiParent: - \_module: work@syn_fifo (work@syn_fifo), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/synfifo.v, line:8:1, endln:104:10 + \_module_inst: work@syn_fifo (work@syn_fifo), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/synfifo.v, line:8:1, endln:104:10 |vpiName:rd_cs |vpiDirection:1 |vpiLowConn: @@ -8049,7 +8049,7 @@ design: (work@dff_async_reset) |vpiPort: \_port: (data_in), line:13:1, endln:13:8 |vpiParent: - \_module: work@syn_fifo (work@syn_fifo), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/synfifo.v, line:8:1, endln:104:10 + \_module_inst: work@syn_fifo (work@syn_fifo), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/synfifo.v, line:8:1, endln:104:10 |vpiName:data_in |vpiDirection:1 |vpiLowConn: @@ -8089,7 +8089,7 @@ design: (work@dff_async_reset) |vpiPort: \_port: (rd_en), line:14:1, endln:14:6 |vpiParent: - \_module: work@syn_fifo (work@syn_fifo), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/synfifo.v, line:8:1, endln:104:10 + \_module_inst: work@syn_fifo (work@syn_fifo), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/synfifo.v, line:8:1, endln:104:10 |vpiName:rd_en |vpiDirection:1 |vpiLowConn: @@ -8101,7 +8101,7 @@ design: (work@dff_async_reset) |vpiPort: \_port: (wr_en), line:15:1, endln:15:6 |vpiParent: - \_module: work@syn_fifo (work@syn_fifo), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/synfifo.v, line:8:1, endln:104:10 + \_module_inst: work@syn_fifo (work@syn_fifo), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/synfifo.v, line:8:1, endln:104:10 |vpiName:wr_en |vpiDirection:1 |vpiLowConn: @@ -8113,7 +8113,7 @@ design: (work@dff_async_reset) |vpiPort: \_port: (data_out), line:16:1, endln:16:9 |vpiParent: - \_module: work@syn_fifo (work@syn_fifo), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/synfifo.v, line:8:1, endln:104:10 + \_module_inst: work@syn_fifo (work@syn_fifo), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/synfifo.v, line:8:1, endln:104:10 |vpiName:data_out |vpiDirection:2 |vpiLowConn: @@ -8153,7 +8153,7 @@ design: (work@dff_async_reset) |vpiPort: \_port: (empty), line:17:1, endln:17:6 |vpiParent: - \_module: work@syn_fifo (work@syn_fifo), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/synfifo.v, line:8:1, endln:104:10 + \_module_inst: work@syn_fifo (work@syn_fifo), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/synfifo.v, line:8:1, endln:104:10 |vpiName:empty |vpiDirection:2 |vpiLowConn: @@ -8165,7 +8165,7 @@ design: (work@dff_async_reset) |vpiPort: \_port: (full), line:18:1, endln:18:5 |vpiParent: - \_module: work@syn_fifo (work@syn_fifo), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/synfifo.v, line:8:1, endln:104:10 + \_module_inst: work@syn_fifo (work@syn_fifo), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/synfifo.v, line:8:1, endln:104:10 |vpiName:full |vpiDirection:2 |vpiLowConn: @@ -8177,7 +8177,7 @@ design: (work@dff_async_reset) |vpiProcess: \_always: , line:49:1, endln:56:4 |vpiParent: - \_module: work@syn_fifo (work@syn_fifo), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/synfifo.v, line:8:1, endln:104:10 + \_module_inst: work@syn_fifo (work@syn_fifo), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/synfifo.v, line:8:1, endln:104:10 |vpiStmt: \_event_control: , line:49:8, endln:49:38 |vpiParent: @@ -8319,7 +8319,7 @@ design: (work@dff_async_reset) |vpiProcess: \_always: , line:58:1, endln:65:4 |vpiParent: - \_module: work@syn_fifo (work@syn_fifo), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/synfifo.v, line:8:1, endln:104:10 + \_module_inst: work@syn_fifo (work@syn_fifo), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/synfifo.v, line:8:1, endln:104:10 |vpiStmt: \_event_control: , line:58:8, endln:58:38 |vpiParent: @@ -8461,7 +8461,7 @@ design: (work@dff_async_reset) |vpiProcess: \_always: , line:67:1, endln:74:4 |vpiParent: - \_module: work@syn_fifo (work@syn_fifo), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/synfifo.v, line:8:1, endln:104:10 + \_module_inst: work@syn_fifo (work@syn_fifo), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/synfifo.v, line:8:1, endln:104:10 |vpiStmt: \_event_control: , line:67:9, endln:67:39 |vpiParent: @@ -8590,7 +8590,7 @@ design: (work@dff_async_reset) |vpiProcess: \_always: , line:76:1, endln:89:4 |vpiParent: - \_module: work@syn_fifo (work@syn_fifo), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/synfifo.v, line:8:1, endln:104:10 + \_module_inst: work@syn_fifo (work@syn_fifo), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/synfifo.v, line:8:1, endln:104:10 |vpiStmt: \_event_control: , line:76:8, endln:76:38 |vpiParent: @@ -8908,7 +8908,7 @@ design: (work@dff_async_reset) |vpiContAssign: \_cont_assign: , line:45:8, endln:45:44 |vpiParent: - \_module: work@syn_fifo (work@syn_fifo), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/synfifo.v, line:8:1, endln:104:10 + \_module_inst: work@syn_fifo (work@syn_fifo), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/synfifo.v, line:8:1, endln:104:10 |vpiRhs: \_operation: , line:45:16, endln:45:43 |vpiParent: @@ -8952,7 +8952,7 @@ design: (work@dff_async_reset) |vpiContAssign: \_cont_assign: , line:46:8, endln:46:33 |vpiParent: - \_module: work@syn_fifo (work@syn_fifo), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/synfifo.v, line:8:1, endln:104:10 + \_module_inst: work@syn_fifo (work@syn_fifo), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/synfifo.v, line:8:1, endln:104:10 |vpiRhs: \_operation: , line:46:17, endln:46:32 |vpiParent: @@ -8983,7 +8983,7 @@ design: (work@dff_async_reset) |vpiActual: \_logic_net: (work@syn_fifo.empty), line:17:1, endln:17:6 |uhdmallModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/arbiter_tb.v, line:3:1, endln:64:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/arbiter_tb.v, line:3:1, endln:64:10 |vpiParent: \_design: (work@dff_async_reset) |vpiFullName:work@top @@ -8991,77 +8991,77 @@ design: (work@dff_async_reset) |vpiNet: \_logic_net: (work@top.clk), line:5:17, endln:5:20 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/arbiter_tb.v, line:3:1, endln:64:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/arbiter_tb.v, line:3:1, endln:64:10 |vpiName:clk |vpiFullName:work@top.clk |vpiNetType:48 |vpiNet: \_logic_net: (work@top.rst), line:6:17, endln:6:20 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/arbiter_tb.v, line:3:1, endln:64:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/arbiter_tb.v, line:3:1, endln:64:10 |vpiName:rst |vpiFullName:work@top.rst |vpiNetType:48 |vpiNet: \_logic_net: (work@top.req3), line:7:17, endln:7:21 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/arbiter_tb.v, line:3:1, endln:64:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/arbiter_tb.v, line:3:1, endln:64:10 |vpiName:req3 |vpiFullName:work@top.req3 |vpiNetType:48 |vpiNet: \_logic_net: (work@top.req2), line:8:17, endln:8:21 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/arbiter_tb.v, line:3:1, endln:64:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/arbiter_tb.v, line:3:1, endln:64:10 |vpiName:req2 |vpiFullName:work@top.req2 |vpiNetType:48 |vpiNet: \_logic_net: (work@top.req1), line:9:17, endln:9:21 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/arbiter_tb.v, line:3:1, endln:64:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/arbiter_tb.v, line:3:1, endln:64:10 |vpiName:req1 |vpiFullName:work@top.req1 |vpiNetType:48 |vpiNet: \_logic_net: (work@top.req0), line:10:17, endln:10:21 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/arbiter_tb.v, line:3:1, endln:64:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/arbiter_tb.v, line:3:1, endln:64:10 |vpiName:req0 |vpiFullName:work@top.req0 |vpiNetType:48 |vpiNet: \_logic_net: (work@top.gnt3), line:11:17, endln:11:21 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/arbiter_tb.v, line:3:1, endln:64:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/arbiter_tb.v, line:3:1, endln:64:10 |vpiName:gnt3 |vpiFullName:work@top.gnt3 |vpiNetType:1 |vpiNet: \_logic_net: (work@top.gnt2), line:12:17, endln:12:21 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/arbiter_tb.v, line:3:1, endln:64:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/arbiter_tb.v, line:3:1, endln:64:10 |vpiName:gnt2 |vpiFullName:work@top.gnt2 |vpiNetType:1 |vpiNet: \_logic_net: (work@top.gnt1), line:13:17, endln:13:21 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/arbiter_tb.v, line:3:1, endln:64:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/arbiter_tb.v, line:3:1, endln:64:10 |vpiName:gnt1 |vpiFullName:work@top.gnt1 |vpiNetType:1 |vpiNet: \_logic_net: (work@top.gnt0), line:14:17, endln:14:21 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/arbiter_tb.v, line:3:1, endln:64:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/arbiter_tb.v, line:3:1, endln:64:10 |vpiName:gnt0 |vpiFullName:work@top.gnt0 |vpiNetType:1 |vpiProcess: \_always: , line:17:1, endln:17:22 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/arbiter_tb.v, line:3:1, endln:64:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/arbiter_tb.v, line:3:1, endln:64:10 |vpiStmt: \_delay_control: , line:17:8, endln:17:10 |vpiParent: @@ -9098,7 +9098,7 @@ design: (work@dff_async_reset) |vpiProcess: \_initial: , line:19:1, endln:48:4 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/arbiter_tb.v, line:3:1, endln:64:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/arbiter_tb.v, line:3:1, endln:64:10 |vpiStmt: \_begin: (work@top), line:19:9, endln:48:4 |vpiParent: @@ -9734,7 +9734,7 @@ design: (work@dff_async_reset) \_delay_control: , line:47:3, endln:47:6 |vpiName:$finish |uhdmallModules: -\_module: work@uart (work@uart), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/uart.v, line:8:1, endln:155:10 +\_module_inst: work@uart (work@uart), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/uart.v, line:8:1, endln:155:10 |vpiParent: \_design: (work@dff_async_reset) |vpiFullName:work@uart @@ -9742,166 +9742,166 @@ design: (work@dff_async_reset) |vpiNet: \_logic_net: (work@uart.tx_reg), line:39:14, endln:39:20 |vpiParent: - \_module: work@uart (work@uart), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/uart.v, line:8:1, endln:155:10 + \_module_inst: work@uart (work@uart), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/uart.v, line:8:1, endln:155:10 |vpiName:tx_reg |vpiFullName:work@uart.tx_reg |vpiNetType:48 |vpiNet: \_logic_net: (work@uart.tx_empty), line:40:14, endln:40:22 |vpiParent: - \_module: work@uart (work@uart), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/uart.v, line:8:1, endln:155:10 + \_module_inst: work@uart (work@uart), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/uart.v, line:8:1, endln:155:10 |vpiName:tx_empty |vpiFullName:work@uart.tx_empty |vpiNetType:48 |vpiNet: \_logic_net: (work@uart.tx_over_run), line:41:14, endln:41:25 |vpiParent: - \_module: work@uart (work@uart), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/uart.v, line:8:1, endln:155:10 + \_module_inst: work@uart (work@uart), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/uart.v, line:8:1, endln:155:10 |vpiName:tx_over_run |vpiFullName:work@uart.tx_over_run |vpiNetType:48 |vpiNet: \_logic_net: (work@uart.tx_cnt), line:42:14, endln:42:20 |vpiParent: - \_module: work@uart (work@uart), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/uart.v, line:8:1, endln:155:10 + \_module_inst: work@uart (work@uart), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/uart.v, line:8:1, endln:155:10 |vpiName:tx_cnt |vpiFullName:work@uart.tx_cnt |vpiNetType:48 |vpiNet: \_logic_net: (work@uart.tx_out), line:43:14, endln:43:20 |vpiParent: - \_module: work@uart (work@uart), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/uart.v, line:8:1, endln:155:10 + \_module_inst: work@uart (work@uart), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/uart.v, line:8:1, endln:155:10 |vpiName:tx_out |vpiFullName:work@uart.tx_out |vpiNetType:48 |vpiNet: \_logic_net: (work@uart.rx_reg), line:44:14, endln:44:20 |vpiParent: - \_module: work@uart (work@uart), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/uart.v, line:8:1, endln:155:10 + \_module_inst: work@uart (work@uart), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/uart.v, line:8:1, endln:155:10 |vpiName:rx_reg |vpiFullName:work@uart.rx_reg |vpiNetType:48 |vpiNet: \_logic_net: (work@uart.rx_data), line:45:14, endln:45:21 |vpiParent: - \_module: work@uart (work@uart), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/uart.v, line:8:1, endln:155:10 + \_module_inst: work@uart (work@uart), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/uart.v, line:8:1, endln:155:10 |vpiName:rx_data |vpiFullName:work@uart.rx_data |vpiNetType:48 |vpiNet: \_logic_net: (work@uart.rx_sample_cnt), line:46:14, endln:46:27 |vpiParent: - \_module: work@uart (work@uart), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/uart.v, line:8:1, endln:155:10 + \_module_inst: work@uart (work@uart), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/uart.v, line:8:1, endln:155:10 |vpiName:rx_sample_cnt |vpiFullName:work@uart.rx_sample_cnt |vpiNetType:48 |vpiNet: \_logic_net: (work@uart.rx_cnt), line:47:14, endln:47:20 |vpiParent: - \_module: work@uart (work@uart), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/uart.v, line:8:1, endln:155:10 + \_module_inst: work@uart (work@uart), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/uart.v, line:8:1, endln:155:10 |vpiName:rx_cnt |vpiFullName:work@uart.rx_cnt |vpiNetType:48 |vpiNet: \_logic_net: (work@uart.rx_frame_err), line:48:14, endln:48:26 |vpiParent: - \_module: work@uart (work@uart), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/uart.v, line:8:1, endln:155:10 + \_module_inst: work@uart (work@uart), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/uart.v, line:8:1, endln:155:10 |vpiName:rx_frame_err |vpiFullName:work@uart.rx_frame_err |vpiNetType:48 |vpiNet: \_logic_net: (work@uart.rx_over_run), line:49:14, endln:49:25 |vpiParent: - \_module: work@uart (work@uart), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/uart.v, line:8:1, endln:155:10 + \_module_inst: work@uart (work@uart), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/uart.v, line:8:1, endln:155:10 |vpiName:rx_over_run |vpiFullName:work@uart.rx_over_run |vpiNetType:48 |vpiNet: \_logic_net: (work@uart.rx_empty), line:50:14, endln:50:22 |vpiParent: - \_module: work@uart (work@uart), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/uart.v, line:8:1, endln:155:10 + \_module_inst: work@uart (work@uart), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/uart.v, line:8:1, endln:155:10 |vpiName:rx_empty |vpiFullName:work@uart.rx_empty |vpiNetType:48 |vpiNet: \_logic_net: (work@uart.rx_d1), line:51:14, endln:51:19 |vpiParent: - \_module: work@uart (work@uart), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/uart.v, line:8:1, endln:155:10 + \_module_inst: work@uart (work@uart), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/uart.v, line:8:1, endln:155:10 |vpiName:rx_d1 |vpiFullName:work@uart.rx_d1 |vpiNetType:48 |vpiNet: \_logic_net: (work@uart.rx_d2), line:52:14, endln:52:19 |vpiParent: - \_module: work@uart (work@uart), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/uart.v, line:8:1, endln:155:10 + \_module_inst: work@uart (work@uart), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/uart.v, line:8:1, endln:155:10 |vpiName:rx_d2 |vpiFullName:work@uart.rx_d2 |vpiNetType:48 |vpiNet: \_logic_net: (work@uart.rx_busy), line:53:14, endln:53:21 |vpiParent: - \_module: work@uart (work@uart), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/uart.v, line:8:1, endln:155:10 + \_module_inst: work@uart (work@uart), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/uart.v, line:8:1, endln:155:10 |vpiName:rx_busy |vpiFullName:work@uart.rx_busy |vpiNetType:48 |vpiNet: \_logic_net: (work@uart.reset), line:9:1, endln:9:6 |vpiParent: - \_module: work@uart (work@uart), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/uart.v, line:8:1, endln:155:10 + \_module_inst: work@uart (work@uart), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/uart.v, line:8:1, endln:155:10 |vpiName:reset |vpiFullName:work@uart.reset |vpiNet: \_logic_net: (work@uart.txclk), line:10:1, endln:10:6 |vpiParent: - \_module: work@uart (work@uart), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/uart.v, line:8:1, endln:155:10 + \_module_inst: work@uart (work@uart), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/uart.v, line:8:1, endln:155:10 |vpiName:txclk |vpiFullName:work@uart.txclk |vpiNet: \_logic_net: (work@uart.ld_tx_data), line:11:1, endln:11:11 |vpiParent: - \_module: work@uart (work@uart), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/uart.v, line:8:1, endln:155:10 + \_module_inst: work@uart (work@uart), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/uart.v, line:8:1, endln:155:10 |vpiName:ld_tx_data |vpiFullName:work@uart.ld_tx_data |vpiNet: \_logic_net: (work@uart.tx_data), line:12:1, endln:12:8 |vpiParent: - \_module: work@uart (work@uart), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/uart.v, line:8:1, endln:155:10 + \_module_inst: work@uart (work@uart), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/uart.v, line:8:1, endln:155:10 |vpiName:tx_data |vpiFullName:work@uart.tx_data |vpiNet: \_logic_net: (work@uart.tx_enable), line:13:1, endln:13:10 |vpiParent: - \_module: work@uart (work@uart), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/uart.v, line:8:1, endln:155:10 + \_module_inst: work@uart (work@uart), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/uart.v, line:8:1, endln:155:10 |vpiName:tx_enable |vpiFullName:work@uart.tx_enable |vpiNet: \_logic_net: (work@uart.rxclk), line:16:1, endln:16:6 |vpiParent: - \_module: work@uart (work@uart), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/uart.v, line:8:1, endln:155:10 + \_module_inst: work@uart (work@uart), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/uart.v, line:8:1, endln:155:10 |vpiName:rxclk |vpiFullName:work@uart.rxclk |vpiNet: \_logic_net: (work@uart.uld_rx_data), line:17:1, endln:17:12 |vpiParent: - \_module: work@uart (work@uart), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/uart.v, line:8:1, endln:155:10 + \_module_inst: work@uart (work@uart), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/uart.v, line:8:1, endln:155:10 |vpiName:uld_rx_data |vpiFullName:work@uart.uld_rx_data |vpiNet: \_logic_net: (work@uart.rx_enable), line:19:1, endln:19:10 |vpiParent: - \_module: work@uart (work@uart), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/uart.v, line:8:1, endln:155:10 + \_module_inst: work@uart (work@uart), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/uart.v, line:8:1, endln:155:10 |vpiName:rx_enable |vpiFullName:work@uart.rx_enable |vpiNet: \_logic_net: (work@uart.rx_in), line:20:1, endln:20:6 |vpiParent: - \_module: work@uart (work@uart), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/uart.v, line:8:1, endln:155:10 + \_module_inst: work@uart (work@uart), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/uart.v, line:8:1, endln:155:10 |vpiName:rx_in |vpiFullName:work@uart.rx_in |vpiPort: \_port: (reset), line:9:1, endln:9:6 |vpiParent: - \_module: work@uart (work@uart), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/uart.v, line:8:1, endln:155:10 + \_module_inst: work@uart (work@uart), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/uart.v, line:8:1, endln:155:10 |vpiName:reset |vpiDirection:1 |vpiLowConn: @@ -9913,7 +9913,7 @@ design: (work@dff_async_reset) |vpiPort: \_port: (txclk), line:10:1, endln:10:6 |vpiParent: - \_module: work@uart (work@uart), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/uart.v, line:8:1, endln:155:10 + \_module_inst: work@uart (work@uart), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/uart.v, line:8:1, endln:155:10 |vpiName:txclk |vpiDirection:1 |vpiLowConn: @@ -9925,7 +9925,7 @@ design: (work@dff_async_reset) |vpiPort: \_port: (ld_tx_data), line:11:1, endln:11:11 |vpiParent: - \_module: work@uart (work@uart), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/uart.v, line:8:1, endln:155:10 + \_module_inst: work@uart (work@uart), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/uart.v, line:8:1, endln:155:10 |vpiName:ld_tx_data |vpiDirection:1 |vpiLowConn: @@ -9937,7 +9937,7 @@ design: (work@dff_async_reset) |vpiPort: \_port: (tx_data), line:12:1, endln:12:8 |vpiParent: - \_module: work@uart (work@uart), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/uart.v, line:8:1, endln:155:10 + \_module_inst: work@uart (work@uart), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/uart.v, line:8:1, endln:155:10 |vpiName:tx_data |vpiDirection:1 |vpiLowConn: @@ -9967,7 +9967,7 @@ design: (work@dff_async_reset) |vpiPort: \_port: (tx_enable), line:13:1, endln:13:10 |vpiParent: - \_module: work@uart (work@uart), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/uart.v, line:8:1, endln:155:10 + \_module_inst: work@uart (work@uart), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/uart.v, line:8:1, endln:155:10 |vpiName:tx_enable |vpiDirection:1 |vpiLowConn: @@ -9979,7 +9979,7 @@ design: (work@dff_async_reset) |vpiPort: \_port: (tx_out), line:14:1, endln:14:7 |vpiParent: - \_module: work@uart (work@uart), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/uart.v, line:8:1, endln:155:10 + \_module_inst: work@uart (work@uart), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/uart.v, line:8:1, endln:155:10 |vpiName:tx_out |vpiDirection:2 |vpiLowConn: @@ -9991,7 +9991,7 @@ design: (work@dff_async_reset) |vpiPort: \_port: (tx_empty), line:15:1, endln:15:9 |vpiParent: - \_module: work@uart (work@uart), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/uart.v, line:8:1, endln:155:10 + \_module_inst: work@uart (work@uart), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/uart.v, line:8:1, endln:155:10 |vpiName:tx_empty |vpiDirection:2 |vpiLowConn: @@ -10003,7 +10003,7 @@ design: (work@dff_async_reset) |vpiPort: \_port: (rxclk), line:16:1, endln:16:6 |vpiParent: - \_module: work@uart (work@uart), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/uart.v, line:8:1, endln:155:10 + \_module_inst: work@uart (work@uart), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/uart.v, line:8:1, endln:155:10 |vpiName:rxclk |vpiDirection:1 |vpiLowConn: @@ -10015,7 +10015,7 @@ design: (work@dff_async_reset) |vpiPort: \_port: (uld_rx_data), line:17:1, endln:17:12 |vpiParent: - \_module: work@uart (work@uart), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/uart.v, line:8:1, endln:155:10 + \_module_inst: work@uart (work@uart), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/uart.v, line:8:1, endln:155:10 |vpiName:uld_rx_data |vpiDirection:1 |vpiLowConn: @@ -10027,7 +10027,7 @@ design: (work@dff_async_reset) |vpiPort: \_port: (rx_data), line:18:1, endln:18:8 |vpiParent: - \_module: work@uart (work@uart), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/uart.v, line:8:1, endln:155:10 + \_module_inst: work@uart (work@uart), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/uart.v, line:8:1, endln:155:10 |vpiName:rx_data |vpiDirection:2 |vpiLowConn: @@ -10057,7 +10057,7 @@ design: (work@dff_async_reset) |vpiPort: \_port: (rx_enable), line:19:1, endln:19:10 |vpiParent: - \_module: work@uart (work@uart), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/uart.v, line:8:1, endln:155:10 + \_module_inst: work@uart (work@uart), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/uart.v, line:8:1, endln:155:10 |vpiName:rx_enable |vpiDirection:1 |vpiLowConn: @@ -10069,7 +10069,7 @@ design: (work@dff_async_reset) |vpiPort: \_port: (rx_in), line:20:1, endln:20:6 |vpiParent: - \_module: work@uart (work@uart), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/uart.v, line:8:1, endln:155:10 + \_module_inst: work@uart (work@uart), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/uart.v, line:8:1, endln:155:10 |vpiName:rx_in |vpiDirection:1 |vpiLowConn: @@ -10081,7 +10081,7 @@ design: (work@dff_async_reset) |vpiPort: \_port: (rx_empty), line:21:1, endln:21:9 |vpiParent: - \_module: work@uart (work@uart), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/uart.v, line:8:1, endln:155:10 + \_module_inst: work@uart (work@uart), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/uart.v, line:8:1, endln:155:10 |vpiName:rx_empty |vpiDirection:2 |vpiLowConn: @@ -10093,7 +10093,7 @@ design: (work@dff_async_reset) |vpiProcess: \_always: , line:56:1, endln:117:4 |vpiParent: - \_module: work@uart (work@uart), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/uart.v, line:8:1, endln:155:10 + \_module_inst: work@uart (work@uart), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/uart.v, line:8:1, endln:155:10 |vpiStmt: \_event_control: , line:56:8, endln:56:42 |vpiParent: @@ -11111,7 +11111,7 @@ design: (work@dff_async_reset) |vpiProcess: \_always: , line:120:1, endln:153:4 |vpiParent: - \_module: work@uart (work@uart), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/uart.v, line:8:1, endln:155:10 + \_module_inst: work@uart (work@uart), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/uart.v, line:8:1, endln:155:10 |vpiStmt: \_event_control: , line:120:8, endln:120:42 |vpiParent: @@ -11733,14 +11733,14 @@ design: (work@dff_async_reset) \_logic_net: (work@uart.tx_cnt), line:42:14, endln:42:20 |vpiAlwaysType:1 |uhdmtopModules: -\_module: work@dff_async_reset (work@dff_async_reset), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/dff.v, line:8:1, endln:31:10 +\_module_inst: work@dff_async_reset (work@dff_async_reset), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/dff.v, line:8:1, endln:31:10 |vpiName:work@dff_async_reset |vpiDefName:work@dff_async_reset |vpiTop:1 |vpiNet: \_logic_net: (work@dff_async_reset.q), line:21:5, endln:21:6 |vpiParent: - \_module: work@dff_async_reset (work@dff_async_reset), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/dff.v, line:8:1, endln:31:10 + \_module_inst: work@dff_async_reset (work@dff_async_reset), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/dff.v, line:8:1, endln:31:10 |vpiTypespec: \_logic_typespec: , line:21:1, endln:21:4 |vpiName:q @@ -11749,7 +11749,7 @@ design: (work@dff_async_reset) |vpiNet: \_logic_net: (work@dff_async_reset.data), line:9:1, endln:9:5 |vpiParent: - \_module: work@dff_async_reset (work@dff_async_reset), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/dff.v, line:8:1, endln:31:10 + \_module_inst: work@dff_async_reset (work@dff_async_reset), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/dff.v, line:8:1, endln:31:10 |vpiTypespec: \_logic_typespec: , line:15:7, endln:15:7 |vpiName:data @@ -11757,7 +11757,7 @@ design: (work@dff_async_reset) |vpiNet: \_logic_net: (work@dff_async_reset.clk), line:10:1, endln:10:4 |vpiParent: - \_module: work@dff_async_reset (work@dff_async_reset), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/dff.v, line:8:1, endln:31:10 + \_module_inst: work@dff_async_reset (work@dff_async_reset), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/dff.v, line:8:1, endln:31:10 |vpiTypespec: \_logic_typespec: , line:15:7, endln:15:7 |vpiName:clk @@ -11765,7 +11765,7 @@ design: (work@dff_async_reset) |vpiNet: \_logic_net: (work@dff_async_reset.reset), line:11:1, endln:11:6 |vpiParent: - \_module: work@dff_async_reset (work@dff_async_reset), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/dff.v, line:8:1, endln:31:10 + \_module_inst: work@dff_async_reset (work@dff_async_reset), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/dff.v, line:8:1, endln:31:10 |vpiTypespec: \_logic_typespec: , line:15:7, endln:15:7 |vpiName:reset @@ -11774,7 +11774,7 @@ design: (work@dff_async_reset) |vpiPort: \_port: (data), line:9:1, endln:9:5 |vpiParent: - \_module: work@dff_async_reset (work@dff_async_reset), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/dff.v, line:8:1, endln:31:10 + \_module_inst: work@dff_async_reset (work@dff_async_reset), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/dff.v, line:8:1, endln:31:10 |vpiName:data |vpiDirection:1 |vpiLowConn: @@ -11788,7 +11788,7 @@ design: (work@dff_async_reset) |vpiPort: \_port: (clk), line:10:1, endln:10:4 |vpiParent: - \_module: work@dff_async_reset (work@dff_async_reset), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/dff.v, line:8:1, endln:31:10 + \_module_inst: work@dff_async_reset (work@dff_async_reset), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/dff.v, line:8:1, endln:31:10 |vpiName:clk |vpiDirection:1 |vpiLowConn: @@ -11802,7 +11802,7 @@ design: (work@dff_async_reset) |vpiPort: \_port: (reset), line:11:1, endln:11:6 |vpiParent: - \_module: work@dff_async_reset (work@dff_async_reset), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/dff.v, line:8:1, endln:31:10 + \_module_inst: work@dff_async_reset (work@dff_async_reset), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/dff.v, line:8:1, endln:31:10 |vpiName:reset |vpiDirection:1 |vpiLowConn: @@ -11816,7 +11816,7 @@ design: (work@dff_async_reset) |vpiPort: \_port: (q), line:12:1, endln:12:2 |vpiParent: - \_module: work@dff_async_reset (work@dff_async_reset), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/dff.v, line:8:1, endln:31:10 + \_module_inst: work@dff_async_reset (work@dff_async_reset), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/dff.v, line:8:1, endln:31:10 |vpiName:q |vpiDirection:2 |vpiLowConn: @@ -11830,14 +11830,14 @@ design: (work@dff_async_reset) |vpiProcess: \_always: , line:24:1, endln:29:4 |uhdmtopModules: -\_module: work@encoder_using_case (work@encoder_using_case), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/encoder.v, line:7:1, endln:43:10 +\_module_inst: work@encoder_using_case (work@encoder_using_case), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/encoder.v, line:7:1, endln:43:10 |vpiName:work@encoder_using_case |vpiDefName:work@encoder_using_case |vpiTop:1 |vpiNet: \_logic_net: (work@encoder_using_case.binary_out), line:17:11, endln:17:21 |vpiParent: - \_module: work@encoder_using_case (work@encoder_using_case), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/encoder.v, line:7:1, endln:43:10 + \_module_inst: work@encoder_using_case (work@encoder_using_case), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/encoder.v, line:7:1, endln:43:10 |vpiTypespec: \_logic_typespec: , line:17:1, endln:17:10 |vpiRange: @@ -11864,7 +11864,7 @@ design: (work@dff_async_reset) |vpiNet: \_logic_net: (work@encoder_using_case.encoder_in), line:9:1, endln:9:11 |vpiParent: - \_module: work@encoder_using_case (work@encoder_using_case), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/encoder.v, line:7:1, endln:43:10 + \_module_inst: work@encoder_using_case (work@encoder_using_case), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/encoder.v, line:7:1, endln:43:10 |vpiTypespec: \_logic_typespec: , line:14:7, endln:14:13 |vpiRange: @@ -11890,7 +11890,7 @@ design: (work@dff_async_reset) |vpiNet: \_logic_net: (work@encoder_using_case.enable), line:10:1, endln:10:7 |vpiParent: - \_module: work@encoder_using_case (work@encoder_using_case), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/encoder.v, line:7:1, endln:43:10 + \_module_inst: work@encoder_using_case (work@encoder_using_case), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/encoder.v, line:7:1, endln:43:10 |vpiTypespec: \_logic_typespec: , line:13:8, endln:13:8 |vpiName:enable @@ -11899,7 +11899,7 @@ design: (work@dff_async_reset) |vpiPort: \_port: (binary_out), line:8:1, endln:8:11 |vpiParent: - \_module: work@encoder_using_case (work@encoder_using_case), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/encoder.v, line:7:1, endln:43:10 + \_module_inst: work@encoder_using_case (work@encoder_using_case), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/encoder.v, line:7:1, endln:43:10 |vpiName:binary_out |vpiDirection:2 |vpiLowConn: @@ -11933,7 +11933,7 @@ design: (work@dff_async_reset) |vpiPort: \_port: (encoder_in), line:9:1, endln:9:11 |vpiParent: - \_module: work@encoder_using_case (work@encoder_using_case), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/encoder.v, line:7:1, endln:43:10 + \_module_inst: work@encoder_using_case (work@encoder_using_case), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/encoder.v, line:7:1, endln:43:10 |vpiName:encoder_in |vpiDirection:1 |vpiLowConn: @@ -11967,7 +11967,7 @@ design: (work@dff_async_reset) |vpiPort: \_port: (enable), line:10:1, endln:10:7 |vpiParent: - \_module: work@encoder_using_case (work@encoder_using_case), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/encoder.v, line:7:1, endln:43:10 + \_module_inst: work@encoder_using_case (work@encoder_using_case), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/encoder.v, line:7:1, endln:43:10 |vpiName:enable |vpiDirection:1 |vpiLowConn: @@ -11981,14 +11981,14 @@ design: (work@dff_async_reset) |vpiProcess: \_always: , line:19:1, endln:41:4 |uhdmtopModules: -\_module: work@case1 (work@case1), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/m_input_mult.v, line:2:1, endln:18:10 +\_module_inst: work@case1 (work@case1), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/m_input_mult.v, line:2:1, endln:18:10 |vpiName:work@case1 |vpiDefName:work@case1 |vpiTop:1 |vpiNet: \_logic_net: (work@case1.in1), line:2:15, endln:2:18 |vpiParent: - \_module: work@case1 (work@case1), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/m_input_mult.v, line:2:1, endln:18:10 + \_module_inst: work@case1 (work@case1), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/m_input_mult.v, line:2:1, endln:18:10 |vpiTypespec: \_logic_typespec: , line:3:7, endln:3:12 |vpiRange: @@ -12014,7 +12014,7 @@ design: (work@dff_async_reset) |vpiNet: \_logic_net: (work@case1.in2), line:2:20, endln:2:23 |vpiParent: - \_module: work@case1 (work@case1), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/m_input_mult.v, line:2:1, endln:18:10 + \_module_inst: work@case1 (work@case1), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/m_input_mult.v, line:2:1, endln:18:10 |vpiTypespec: \_logic_typespec: , line:4:7, endln:4:12 |vpiRange: @@ -12040,7 +12040,7 @@ design: (work@dff_async_reset) |vpiNet: \_logic_net: (work@case1.out2), line:2:25, endln:2:29 |vpiParent: - \_module: work@case1 (work@case1), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/m_input_mult.v, line:2:1, endln:18:10 + \_module_inst: work@case1 (work@case1), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/m_input_mult.v, line:2:1, endln:18:10 |vpiTypespec: \_logic_typespec: , line:5:8, endln:5:8 |vpiName:out2 @@ -12049,7 +12049,7 @@ design: (work@dff_async_reset) |vpiPort: \_port: (in1), line:2:15, endln:2:18 |vpiParent: - \_module: work@case1 (work@case1), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/m_input_mult.v, line:2:1, endln:18:10 + \_module_inst: work@case1 (work@case1), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/m_input_mult.v, line:2:1, endln:18:10 |vpiName:in1 |vpiDirection:1 |vpiLowConn: @@ -12083,7 +12083,7 @@ design: (work@dff_async_reset) |vpiPort: \_port: (in2), line:2:20, endln:2:23 |vpiParent: - \_module: work@case1 (work@case1), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/m_input_mult.v, line:2:1, endln:18:10 + \_module_inst: work@case1 (work@case1), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/m_input_mult.v, line:2:1, endln:18:10 |vpiName:in2 |vpiDirection:1 |vpiLowConn: @@ -12117,7 +12117,7 @@ design: (work@dff_async_reset) |vpiPort: \_port: (out2), line:2:25, endln:2:29 |vpiParent: - \_module: work@case1 (work@case1), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/m_input_mult.v, line:2:1, endln:18:10 + \_module_inst: work@case1 (work@case1), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/m_input_mult.v, line:2:1, endln:18:10 |vpiName:out2 |vpiDirection:2 |vpiLowConn: @@ -12131,14 +12131,14 @@ design: (work@dff_async_reset) |vpiProcess: \_always: , line:6:1, endln:16:9 |uhdmtopModules: -\_module: work@case2 (work@case2), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/m_input_mult.v, line:21:1, endln:46:10 +\_module_inst: work@case2 (work@case2), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/m_input_mult.v, line:21:1, endln:46:10 |vpiName:work@case2 |vpiDefName:work@case2 |vpiTop:1 |vpiNet: \_logic_net: (work@case2.select), line:25:11, endln:25:17 |vpiParent: - \_module: work@case2 (work@case2), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/m_input_mult.v, line:21:1, endln:46:10 + \_module_inst: work@case2 (work@case2), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/m_input_mult.v, line:21:1, endln:46:10 |vpiTypespec: \_logic_typespec: , line:25:1, endln:25:10 |vpiRange: @@ -12165,7 +12165,7 @@ design: (work@dff_async_reset) |vpiNet: \_logic_net: (work@case2.in1), line:21:15, endln:21:18 |vpiParent: - \_module: work@case2 (work@case2), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/m_input_mult.v, line:21:1, endln:46:10 + \_module_inst: work@case2 (work@case2), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/m_input_mult.v, line:21:1, endln:46:10 |vpiTypespec: \_logic_typespec: , line:22:7, endln:22:12 |vpiRange: @@ -12191,7 +12191,7 @@ design: (work@dff_async_reset) |vpiNet: \_logic_net: (work@case2.sel), line:21:20, endln:21:23 |vpiParent: - \_module: work@case2 (work@case2), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/m_input_mult.v, line:21:1, endln:46:10 + \_module_inst: work@case2 (work@case2), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/m_input_mult.v, line:21:1, endln:46:10 |vpiTypespec: \_logic_typespec: , line:23:7, endln:23:12 |vpiRange: @@ -12217,7 +12217,7 @@ design: (work@dff_async_reset) |vpiNet: \_logic_net: (work@case2.out2), line:21:25, endln:21:29 |vpiParent: - \_module: work@case2 (work@case2), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/m_input_mult.v, line:21:1, endln:46:10 + \_module_inst: work@case2 (work@case2), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/m_input_mult.v, line:21:1, endln:46:10 |vpiTypespec: \_logic_typespec: , line:24:8, endln:24:14 |vpiRange: @@ -12244,7 +12244,7 @@ design: (work@dff_async_reset) |vpiPort: \_port: (in1), line:21:15, endln:21:18 |vpiParent: - \_module: work@case2 (work@case2), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/m_input_mult.v, line:21:1, endln:46:10 + \_module_inst: work@case2 (work@case2), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/m_input_mult.v, line:21:1, endln:46:10 |vpiName:in1 |vpiDirection:1 |vpiLowConn: @@ -12278,7 +12278,7 @@ design: (work@dff_async_reset) |vpiPort: \_port: (sel), line:21:20, endln:21:23 |vpiParent: - \_module: work@case2 (work@case2), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/m_input_mult.v, line:21:1, endln:46:10 + \_module_inst: work@case2 (work@case2), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/m_input_mult.v, line:21:1, endln:46:10 |vpiName:sel |vpiDirection:1 |vpiLowConn: @@ -12312,7 +12312,7 @@ design: (work@dff_async_reset) |vpiPort: \_port: (out2), line:21:25, endln:21:29 |vpiParent: - \_module: work@case2 (work@case2), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/m_input_mult.v, line:21:1, endln:46:10 + \_module_inst: work@case2 (work@case2), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/m_input_mult.v, line:21:1, endln:46:10 |vpiName:out2 |vpiDirection:2 |vpiLowConn: @@ -12362,14 +12362,14 @@ design: (work@dff_async_reset) |vpiContAssign: \_cont_assign: , line:45:9, endln:45:38 |uhdmtopModules: -\_module: work@pri_encooder (work@pri_encooder), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/m_input_mult.v, line:49:1, endln:73:10 +\_module_inst: work@pri_encooder (work@pri_encooder), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/m_input_mult.v, line:49:1, endln:73:10 |vpiName:work@pri_encooder |vpiDefName:work@pri_encooder |vpiTop:1 |vpiNet: \_logic_net: (work@pri_encooder.Op), line:49:22, endln:49:24 |vpiParent: - \_module: work@pri_encooder (work@pri_encooder), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/m_input_mult.v, line:49:1, endln:73:10 + \_module_inst: work@pri_encooder (work@pri_encooder), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/m_input_mult.v, line:49:1, endln:73:10 |vpiTypespec: \_logic_typespec: , line:50:7, endln:50:12 |vpiRange: @@ -12395,7 +12395,7 @@ design: (work@dff_async_reset) |vpiNet: \_logic_net: (work@pri_encooder.Funct), line:49:26, endln:49:31 |vpiParent: - \_module: work@pri_encooder (work@pri_encooder), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/m_input_mult.v, line:49:1, endln:73:10 + \_module_inst: work@pri_encooder (work@pri_encooder), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/m_input_mult.v, line:49:1, endln:73:10 |vpiTypespec: \_logic_typespec: , line:51:7, endln:51:12 |vpiRange: @@ -12421,7 +12421,7 @@ design: (work@dff_async_reset) |vpiNet: \_logic_net: (work@pri_encooder.Sel), line:49:33, endln:49:36 |vpiParent: - \_module: work@pri_encooder (work@pri_encooder), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/m_input_mult.v, line:49:1, endln:73:10 + \_module_inst: work@pri_encooder (work@pri_encooder), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/m_input_mult.v, line:49:1, endln:73:10 |vpiTypespec: \_logic_typespec: , line:52:8, endln:52:13 |vpiRange: @@ -12447,7 +12447,7 @@ design: (work@dff_async_reset) |vpiNet: \_logic_net: (work@pri_encooder.B), line:49:38, endln:49:39 |vpiParent: - \_module: work@pri_encooder (work@pri_encooder), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/m_input_mult.v, line:49:1, endln:73:10 + \_module_inst: work@pri_encooder (work@pri_encooder), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/m_input_mult.v, line:49:1, endln:73:10 |vpiTypespec: \_logic_typespec: , line:53:8, endln:53:8 |vpiName:B @@ -12456,7 +12456,7 @@ design: (work@dff_async_reset) |vpiPort: \_port: (Op), line:49:22, endln:49:24 |vpiParent: - \_module: work@pri_encooder (work@pri_encooder), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/m_input_mult.v, line:49:1, endln:73:10 + \_module_inst: work@pri_encooder (work@pri_encooder), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/m_input_mult.v, line:49:1, endln:73:10 |vpiName:Op |vpiDirection:1 |vpiLowConn: @@ -12490,7 +12490,7 @@ design: (work@dff_async_reset) |vpiPort: \_port: (Funct), line:49:26, endln:49:31 |vpiParent: - \_module: work@pri_encooder (work@pri_encooder), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/m_input_mult.v, line:49:1, endln:73:10 + \_module_inst: work@pri_encooder (work@pri_encooder), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/m_input_mult.v, line:49:1, endln:73:10 |vpiName:Funct |vpiDirection:1 |vpiLowConn: @@ -12524,7 +12524,7 @@ design: (work@dff_async_reset) |vpiPort: \_port: (Sel), line:49:33, endln:49:36 |vpiParent: - \_module: work@pri_encooder (work@pri_encooder), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/m_input_mult.v, line:49:1, endln:73:10 + \_module_inst: work@pri_encooder (work@pri_encooder), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/m_input_mult.v, line:49:1, endln:73:10 |vpiName:Sel |vpiDirection:2 |vpiLowConn: @@ -12558,7 +12558,7 @@ design: (work@dff_async_reset) |vpiPort: \_port: (B), line:49:38, endln:49:39 |vpiParent: - \_module: work@pri_encooder (work@pri_encooder), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/m_input_mult.v, line:49:1, endln:73:10 + \_module_inst: work@pri_encooder (work@pri_encooder), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/m_input_mult.v, line:49:1, endln:73:10 |vpiName:B |vpiDirection:2 |vpiLowConn: @@ -12572,12 +12572,12 @@ design: (work@dff_async_reset) |vpiProcess: \_always: , line:54:1, endln:72:9 |uhdmtopModules: -\_module: work@syn_fifo (work@syn_fifo), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/synfifo.v, line:8:1, endln:104:10 +\_module_inst: work@syn_fifo (work@syn_fifo), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/synfifo.v, line:8:1, endln:104:10 |vpiName:work@syn_fifo |vpiParameter: \_parameter: (work@syn_fifo.DATA_WIDTH), line:22:11, endln:22:21 |vpiParent: - \_module: work@syn_fifo (work@syn_fifo), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/synfifo.v, line:8:1, endln:104:10 + \_module_inst: work@syn_fifo (work@syn_fifo), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/synfifo.v, line:8:1, endln:104:10 |UINT:8 |vpiTypespec: \_int_typespec: @@ -12588,7 +12588,7 @@ design: (work@dff_async_reset) |vpiParameter: \_parameter: (work@syn_fifo.ADDR_WIDTH), line:23:11, endln:23:21 |vpiParent: - \_module: work@syn_fifo (work@syn_fifo), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/synfifo.v, line:8:1, endln:104:10 + \_module_inst: work@syn_fifo (work@syn_fifo), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/synfifo.v, line:8:1, endln:104:10 |UINT:8 |vpiTypespec: \_int_typespec: @@ -12599,13 +12599,13 @@ design: (work@dff_async_reset) |vpiParameter: \_parameter: (work@syn_fifo.RAM_DEPTH), line:24:11, endln:24:20 |vpiParent: - \_module: work@syn_fifo (work@syn_fifo), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/synfifo.v, line:8:1, endln:104:10 + \_module_inst: work@syn_fifo (work@syn_fifo), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/synfifo.v, line:8:1, endln:104:10 |vpiName:RAM_DEPTH |vpiFullName:work@syn_fifo.RAM_DEPTH |vpiParamAssign: \_param_assign: , line:22:11, endln:22:25 |vpiParent: - \_module: work@syn_fifo (work@syn_fifo), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/synfifo.v, line:8:1, endln:104:10 + \_module_inst: work@syn_fifo (work@syn_fifo), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/synfifo.v, line:8:1, endln:104:10 |vpiRhs: \_constant: , line:22:24, endln:22:25 |vpiDecompile:8 @@ -12619,7 +12619,7 @@ design: (work@dff_async_reset) |vpiParamAssign: \_param_assign: , line:23:11, endln:23:25 |vpiParent: - \_module: work@syn_fifo (work@syn_fifo), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/synfifo.v, line:8:1, endln:104:10 + \_module_inst: work@syn_fifo (work@syn_fifo), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/synfifo.v, line:8:1, endln:104:10 |vpiRhs: \_constant: , line:23:24, endln:23:25 |vpiDecompile:8 @@ -12633,7 +12633,7 @@ design: (work@dff_async_reset) |vpiParamAssign: \_param_assign: , line:24:11, endln:24:40 |vpiParent: - \_module: work@syn_fifo (work@syn_fifo), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/synfifo.v, line:8:1, endln:104:10 + \_module_inst: work@syn_fifo (work@syn_fifo), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/synfifo.v, line:8:1, endln:104:10 |vpiRhs: \_constant: , line:24:23, endln:24:40 |vpiDecompile:256 @@ -12647,7 +12647,7 @@ design: (work@dff_async_reset) |vpiNet: \_logic_net: (work@syn_fifo.wr_pointer), line:38:22, endln:38:32 |vpiParent: - \_module: work@syn_fifo (work@syn_fifo), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/synfifo.v, line:8:1, endln:104:10 + \_module_inst: work@syn_fifo (work@syn_fifo), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/synfifo.v, line:8:1, endln:104:10 |vpiTypespec: \_logic_typespec: , line:38:1, endln:38:21 |vpiRange: @@ -12674,7 +12674,7 @@ design: (work@dff_async_reset) |vpiNet: \_logic_net: (work@syn_fifo.rd_pointer), line:39:22, endln:39:32 |vpiParent: - \_module: work@syn_fifo (work@syn_fifo), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/synfifo.v, line:8:1, endln:104:10 + \_module_inst: work@syn_fifo (work@syn_fifo), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/synfifo.v, line:8:1, endln:104:10 |vpiTypespec: \_logic_typespec: , line:39:1, endln:39:21 |vpiRange: @@ -12701,7 +12701,7 @@ design: (work@dff_async_reset) |vpiNet: \_logic_net: (work@syn_fifo.status_cnt), line:40:21, endln:40:31 |vpiParent: - \_module: work@syn_fifo (work@syn_fifo), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/synfifo.v, line:8:1, endln:104:10 + \_module_inst: work@syn_fifo (work@syn_fifo), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/synfifo.v, line:8:1, endln:104:10 |vpiTypespec: \_logic_typespec: , line:40:1, endln:40:20 |vpiRange: @@ -12728,7 +12728,7 @@ design: (work@dff_async_reset) |vpiNet: \_logic_net: (work@syn_fifo.data_out), line:41:22, endln:41:30 |vpiParent: - \_module: work@syn_fifo (work@syn_fifo), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/synfifo.v, line:8:1, endln:104:10 + \_module_inst: work@syn_fifo (work@syn_fifo), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/synfifo.v, line:8:1, endln:104:10 |vpiTypespec: \_logic_typespec: , line:41:1, endln:41:21 |vpiRange: @@ -12755,7 +12755,7 @@ design: (work@dff_async_reset) |vpiNet: \_logic_net: (work@syn_fifo.data_ram), line:42:23, endln:42:31 |vpiParent: - \_module: work@syn_fifo (work@syn_fifo), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/synfifo.v, line:8:1, endln:104:10 + \_module_inst: work@syn_fifo (work@syn_fifo), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/synfifo.v, line:8:1, endln:104:10 |vpiTypespec: \_logic_typespec: , line:42:1, endln:42:22 |vpiRange: @@ -12782,7 +12782,7 @@ design: (work@dff_async_reset) |vpiNet: \_logic_net: (work@syn_fifo.clk), line:9:1, endln:9:4 |vpiParent: - \_module: work@syn_fifo (work@syn_fifo), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/synfifo.v, line:8:1, endln:104:10 + \_module_inst: work@syn_fifo (work@syn_fifo), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/synfifo.v, line:8:1, endln:104:10 |vpiTypespec: \_logic_typespec: , line:26:7, endln:26:7 |vpiName:clk @@ -12790,7 +12790,7 @@ design: (work@dff_async_reset) |vpiNet: \_logic_net: (work@syn_fifo.rst), line:10:1, endln:10:4 |vpiParent: - \_module: work@syn_fifo (work@syn_fifo), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/synfifo.v, line:8:1, endln:104:10 + \_module_inst: work@syn_fifo (work@syn_fifo), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/synfifo.v, line:8:1, endln:104:10 |vpiTypespec: \_logic_typespec: , line:27:7, endln:27:7 |vpiName:rst @@ -12798,7 +12798,7 @@ design: (work@dff_async_reset) |vpiNet: \_logic_net: (work@syn_fifo.wr_cs), line:11:1, endln:11:6 |vpiParent: - \_module: work@syn_fifo (work@syn_fifo), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/synfifo.v, line:8:1, endln:104:10 + \_module_inst: work@syn_fifo (work@syn_fifo), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/synfifo.v, line:8:1, endln:104:10 |vpiTypespec: \_logic_typespec: , line:28:7, endln:28:7 |vpiName:wr_cs @@ -12806,7 +12806,7 @@ design: (work@dff_async_reset) |vpiNet: \_logic_net: (work@syn_fifo.rd_cs), line:12:1, endln:12:6 |vpiParent: - \_module: work@syn_fifo (work@syn_fifo), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/synfifo.v, line:8:1, endln:104:10 + \_module_inst: work@syn_fifo (work@syn_fifo), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/synfifo.v, line:8:1, endln:104:10 |vpiTypespec: \_logic_typespec: , line:29:7, endln:29:7 |vpiName:rd_cs @@ -12814,7 +12814,7 @@ design: (work@dff_async_reset) |vpiNet: \_logic_net: (work@syn_fifo.data_in), line:13:1, endln:13:8 |vpiParent: - \_module: work@syn_fifo (work@syn_fifo), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/synfifo.v, line:8:1, endln:104:10 + \_module_inst: work@syn_fifo (work@syn_fifo), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/synfifo.v, line:8:1, endln:104:10 |vpiTypespec: \_logic_typespec: , line:32:7, endln:32:23 |vpiRange: @@ -12840,7 +12840,7 @@ design: (work@dff_async_reset) |vpiNet: \_logic_net: (work@syn_fifo.rd_en), line:14:1, endln:14:6 |vpiParent: - \_module: work@syn_fifo (work@syn_fifo), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/synfifo.v, line:8:1, endln:104:10 + \_module_inst: work@syn_fifo (work@syn_fifo), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/synfifo.v, line:8:1, endln:104:10 |vpiTypespec: \_logic_typespec: , line:30:7, endln:30:7 |vpiName:rd_en @@ -12848,7 +12848,7 @@ design: (work@dff_async_reset) |vpiNet: \_logic_net: (work@syn_fifo.wr_en), line:15:1, endln:15:6 |vpiParent: - \_module: work@syn_fifo (work@syn_fifo), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/synfifo.v, line:8:1, endln:104:10 + \_module_inst: work@syn_fifo (work@syn_fifo), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/synfifo.v, line:8:1, endln:104:10 |vpiTypespec: \_logic_typespec: , line:31:7, endln:31:7 |vpiName:wr_en @@ -12856,7 +12856,7 @@ design: (work@dff_async_reset) |vpiNet: \_logic_net: (work@syn_fifo.empty), line:17:1, endln:17:6 |vpiParent: - \_module: work@syn_fifo (work@syn_fifo), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/synfifo.v, line:8:1, endln:104:10 + \_module_inst: work@syn_fifo (work@syn_fifo), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/synfifo.v, line:8:1, endln:104:10 |vpiTypespec: \_logic_typespec: , line:34:8, endln:34:8 |vpiName:empty @@ -12864,7 +12864,7 @@ design: (work@dff_async_reset) |vpiNet: \_logic_net: (work@syn_fifo.full), line:18:1, endln:18:5 |vpiParent: - \_module: work@syn_fifo (work@syn_fifo), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/synfifo.v, line:8:1, endln:104:10 + \_module_inst: work@syn_fifo (work@syn_fifo), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/synfifo.v, line:8:1, endln:104:10 |vpiTypespec: \_logic_typespec: , line:33:8, endln:33:8 |vpiName:full @@ -12873,7 +12873,7 @@ design: (work@dff_async_reset) |vpiPort: \_port: (clk), line:9:1, endln:9:4 |vpiParent: - \_module: work@syn_fifo (work@syn_fifo), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/synfifo.v, line:8:1, endln:104:10 + \_module_inst: work@syn_fifo (work@syn_fifo), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/synfifo.v, line:8:1, endln:104:10 |vpiName:clk |vpiDirection:1 |vpiLowConn: @@ -12887,7 +12887,7 @@ design: (work@dff_async_reset) |vpiPort: \_port: (rst), line:10:1, endln:10:4 |vpiParent: - \_module: work@syn_fifo (work@syn_fifo), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/synfifo.v, line:8:1, endln:104:10 + \_module_inst: work@syn_fifo (work@syn_fifo), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/synfifo.v, line:8:1, endln:104:10 |vpiName:rst |vpiDirection:1 |vpiLowConn: @@ -12901,7 +12901,7 @@ design: (work@dff_async_reset) |vpiPort: \_port: (wr_cs), line:11:1, endln:11:6 |vpiParent: - \_module: work@syn_fifo (work@syn_fifo), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/synfifo.v, line:8:1, endln:104:10 + \_module_inst: work@syn_fifo (work@syn_fifo), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/synfifo.v, line:8:1, endln:104:10 |vpiName:wr_cs |vpiDirection:1 |vpiLowConn: @@ -12915,7 +12915,7 @@ design: (work@dff_async_reset) |vpiPort: \_port: (rd_cs), line:12:1, endln:12:6 |vpiParent: - \_module: work@syn_fifo (work@syn_fifo), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/synfifo.v, line:8:1, endln:104:10 + \_module_inst: work@syn_fifo (work@syn_fifo), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/synfifo.v, line:8:1, endln:104:10 |vpiName:rd_cs |vpiDirection:1 |vpiLowConn: @@ -12929,7 +12929,7 @@ design: (work@dff_async_reset) |vpiPort: \_port: (data_in), line:13:1, endln:13:8 |vpiParent: - \_module: work@syn_fifo (work@syn_fifo), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/synfifo.v, line:8:1, endln:104:10 + \_module_inst: work@syn_fifo (work@syn_fifo), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/synfifo.v, line:8:1, endln:104:10 |vpiName:data_in |vpiDirection:1 |vpiLowConn: @@ -12963,7 +12963,7 @@ design: (work@dff_async_reset) |vpiPort: \_port: (rd_en), line:14:1, endln:14:6 |vpiParent: - \_module: work@syn_fifo (work@syn_fifo), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/synfifo.v, line:8:1, endln:104:10 + \_module_inst: work@syn_fifo (work@syn_fifo), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/synfifo.v, line:8:1, endln:104:10 |vpiName:rd_en |vpiDirection:1 |vpiLowConn: @@ -12977,7 +12977,7 @@ design: (work@dff_async_reset) |vpiPort: \_port: (wr_en), line:15:1, endln:15:6 |vpiParent: - \_module: work@syn_fifo (work@syn_fifo), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/synfifo.v, line:8:1, endln:104:10 + \_module_inst: work@syn_fifo (work@syn_fifo), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/synfifo.v, line:8:1, endln:104:10 |vpiName:wr_en |vpiDirection:1 |vpiLowConn: @@ -12991,7 +12991,7 @@ design: (work@dff_async_reset) |vpiPort: \_port: (data_out), line:16:1, endln:16:9 |vpiParent: - \_module: work@syn_fifo (work@syn_fifo), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/synfifo.v, line:8:1, endln:104:10 + \_module_inst: work@syn_fifo (work@syn_fifo), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/synfifo.v, line:8:1, endln:104:10 |vpiName:data_out |vpiDirection:2 |vpiLowConn: @@ -13025,7 +13025,7 @@ design: (work@dff_async_reset) |vpiPort: \_port: (empty), line:17:1, endln:17:6 |vpiParent: - \_module: work@syn_fifo (work@syn_fifo), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/synfifo.v, line:8:1, endln:104:10 + \_module_inst: work@syn_fifo (work@syn_fifo), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/synfifo.v, line:8:1, endln:104:10 |vpiName:empty |vpiDirection:2 |vpiLowConn: @@ -13039,7 +13039,7 @@ design: (work@dff_async_reset) |vpiPort: \_port: (full), line:18:1, endln:18:5 |vpiParent: - \_module: work@syn_fifo (work@syn_fifo), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/synfifo.v, line:8:1, endln:104:10 + \_module_inst: work@syn_fifo (work@syn_fifo), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/synfifo.v, line:8:1, endln:104:10 |vpiName:full |vpiDirection:2 |vpiLowConn: @@ -13058,19 +13058,19 @@ design: (work@dff_async_reset) \_always: , line:67:1, endln:74:4 |vpiProcess: \_always: , line:76:1, endln:89:4 - |vpiModule: - \_module: work@syn_fifo::ram_dp_ar_aw (work@syn_fifo.DP_RAM), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/synfifo.v, line:91:1, endln:102:3 + |vpiModuleInst: + \_module_inst: work@syn_fifo::ram_dp_ar_aw (work@syn_fifo.DP_RAM), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/synfifo.v, line:91:1, endln:102:3 |vpiParent: - \_module: work@syn_fifo (work@syn_fifo), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/synfifo.v, line:8:1, endln:104:10 + \_module_inst: work@syn_fifo (work@syn_fifo), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/synfifo.v, line:8:1, endln:104:10 |vpiName:DP_RAM |vpiFullName:work@syn_fifo.DP_RAM |vpiDefName:work@syn_fifo::ram_dp_ar_aw |vpiInstance: - \_module: work@syn_fifo (work@syn_fifo), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/synfifo.v, line:8:1, endln:104:10 + \_module_inst: work@syn_fifo (work@syn_fifo), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/synfifo.v, line:8:1, endln:104:10 |vpiPort: \_port: (address_0), line:92:2, endln:92:11 |vpiParent: - \_module: work@syn_fifo::ram_dp_ar_aw (work@syn_fifo.DP_RAM), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/synfifo.v, line:91:1, endln:102:3 + \_module_inst: work@syn_fifo::ram_dp_ar_aw (work@syn_fifo.DP_RAM), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/synfifo.v, line:91:1, endln:102:3 |vpiName:address_0 |vpiHighConn: \_ref_obj: (work@syn_fifo.wr_pointer), line:92:13, endln:92:23 @@ -13081,7 +13081,7 @@ design: (work@dff_async_reset) |vpiPort: \_port: (data_0), line:93:2, endln:93:8 |vpiParent: - \_module: work@syn_fifo::ram_dp_ar_aw (work@syn_fifo.DP_RAM), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/synfifo.v, line:91:1, endln:102:3 + \_module_inst: work@syn_fifo::ram_dp_ar_aw (work@syn_fifo.DP_RAM), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/synfifo.v, line:91:1, endln:102:3 |vpiName:data_0 |vpiHighConn: \_ref_obj: (work@syn_fifo.data_in), line:93:13, endln:93:20 @@ -13092,7 +13092,7 @@ design: (work@dff_async_reset) |vpiPort: \_port: (cs_0), line:94:2, endln:94:6 |vpiParent: - \_module: work@syn_fifo::ram_dp_ar_aw (work@syn_fifo.DP_RAM), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/synfifo.v, line:91:1, endln:102:3 + \_module_inst: work@syn_fifo::ram_dp_ar_aw (work@syn_fifo.DP_RAM), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/synfifo.v, line:91:1, endln:102:3 |vpiName:cs_0 |vpiHighConn: \_ref_obj: (work@syn_fifo.wr_cs), line:94:13, endln:94:18 @@ -13103,7 +13103,7 @@ design: (work@dff_async_reset) |vpiPort: \_port: (we_0), line:95:2, endln:95:6 |vpiParent: - \_module: work@syn_fifo::ram_dp_ar_aw (work@syn_fifo.DP_RAM), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/synfifo.v, line:91:1, endln:102:3 + \_module_inst: work@syn_fifo::ram_dp_ar_aw (work@syn_fifo.DP_RAM), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/synfifo.v, line:91:1, endln:102:3 |vpiName:we_0 |vpiHighConn: \_ref_obj: (work@syn_fifo.wr_en), line:95:13, endln:95:18 @@ -13114,7 +13114,7 @@ design: (work@dff_async_reset) |vpiPort: \_port: (oe_0), line:96:2, endln:96:6 |vpiParent: - \_module: work@syn_fifo::ram_dp_ar_aw (work@syn_fifo.DP_RAM), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/synfifo.v, line:91:1, endln:102:3 + \_module_inst: work@syn_fifo::ram_dp_ar_aw (work@syn_fifo.DP_RAM), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/synfifo.v, line:91:1, endln:102:3 |vpiName:oe_0 |vpiHighConn: \_constant: , line:96:13, endln:96:17 @@ -13125,7 +13125,7 @@ design: (work@dff_async_reset) |vpiPort: \_port: (address_1), line:97:2, endln:97:11 |vpiParent: - \_module: work@syn_fifo::ram_dp_ar_aw (work@syn_fifo.DP_RAM), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/synfifo.v, line:91:1, endln:102:3 + \_module_inst: work@syn_fifo::ram_dp_ar_aw (work@syn_fifo.DP_RAM), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/synfifo.v, line:91:1, endln:102:3 |vpiName:address_1 |vpiHighConn: \_ref_obj: (work@syn_fifo.rd_pointer), line:97:13, endln:97:23 @@ -13136,7 +13136,7 @@ design: (work@dff_async_reset) |vpiPort: \_port: (data_1), line:98:2, endln:98:8 |vpiParent: - \_module: work@syn_fifo::ram_dp_ar_aw (work@syn_fifo.DP_RAM), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/synfifo.v, line:91:1, endln:102:3 + \_module_inst: work@syn_fifo::ram_dp_ar_aw (work@syn_fifo.DP_RAM), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/synfifo.v, line:91:1, endln:102:3 |vpiName:data_1 |vpiHighConn: \_ref_obj: (work@syn_fifo.data_ram), line:98:13, endln:98:21 @@ -13147,7 +13147,7 @@ design: (work@dff_async_reset) |vpiPort: \_port: (cs_1), line:99:2, endln:99:6 |vpiParent: - \_module: work@syn_fifo::ram_dp_ar_aw (work@syn_fifo.DP_RAM), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/synfifo.v, line:91:1, endln:102:3 + \_module_inst: work@syn_fifo::ram_dp_ar_aw (work@syn_fifo.DP_RAM), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/synfifo.v, line:91:1, endln:102:3 |vpiName:cs_1 |vpiHighConn: \_ref_obj: (work@syn_fifo.rd_cs), line:99:13, endln:99:18 @@ -13158,7 +13158,7 @@ design: (work@dff_async_reset) |vpiPort: \_port: (we_1), line:100:2, endln:100:6 |vpiParent: - \_module: work@syn_fifo::ram_dp_ar_aw (work@syn_fifo.DP_RAM), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/synfifo.v, line:91:1, endln:102:3 + \_module_inst: work@syn_fifo::ram_dp_ar_aw (work@syn_fifo.DP_RAM), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/synfifo.v, line:91:1, endln:102:3 |vpiName:we_1 |vpiHighConn: \_constant: , line:100:13, endln:100:17 @@ -13169,7 +13169,7 @@ design: (work@dff_async_reset) |vpiPort: \_port: (oe_1), line:101:2, endln:101:6 |vpiParent: - \_module: work@syn_fifo::ram_dp_ar_aw (work@syn_fifo.DP_RAM), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/synfifo.v, line:91:1, endln:102:3 + \_module_inst: work@syn_fifo::ram_dp_ar_aw (work@syn_fifo.DP_RAM), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/synfifo.v, line:91:1, endln:102:3 |vpiName:oe_1 |vpiHighConn: \_ref_obj: (work@syn_fifo.rd_en), line:101:13, endln:101:18 @@ -13242,14 +13242,14 @@ design: (work@dff_async_reset) |vpiActual: \_logic_net: (work@syn_fifo.empty), line:17:1, endln:17:6 |uhdmtopModules: -\_module: work@uart (work@uart), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/uart.v, line:8:1, endln:155:10 +\_module_inst: work@uart (work@uart), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/uart.v, line:8:1, endln:155:10 |vpiName:work@uart |vpiDefName:work@uart |vpiTop:1 |vpiNet: \_logic_net: (work@uart.tx_reg), line:39:14, endln:39:20 |vpiParent: - \_module: work@uart (work@uart), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/uart.v, line:8:1, endln:155:10 + \_module_inst: work@uart (work@uart), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/uart.v, line:8:1, endln:155:10 |vpiTypespec: \_logic_typespec: , line:39:1, endln:39:10 |vpiRange: @@ -13276,7 +13276,7 @@ design: (work@dff_async_reset) |vpiNet: \_logic_net: (work@uart.tx_empty), line:40:14, endln:40:22 |vpiParent: - \_module: work@uart (work@uart), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/uart.v, line:8:1, endln:155:10 + \_module_inst: work@uart (work@uart), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/uart.v, line:8:1, endln:155:10 |vpiTypespec: \_logic_typespec: , line:40:1, endln:40:4 |vpiName:tx_empty @@ -13285,7 +13285,7 @@ design: (work@dff_async_reset) |vpiNet: \_logic_net: (work@uart.tx_over_run), line:41:14, endln:41:25 |vpiParent: - \_module: work@uart (work@uart), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/uart.v, line:8:1, endln:155:10 + \_module_inst: work@uart (work@uart), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/uart.v, line:8:1, endln:155:10 |vpiTypespec: \_logic_typespec: , line:41:1, endln:41:4 |vpiName:tx_over_run @@ -13294,7 +13294,7 @@ design: (work@dff_async_reset) |vpiNet: \_logic_net: (work@uart.tx_cnt), line:42:14, endln:42:20 |vpiParent: - \_module: work@uart (work@uart), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/uart.v, line:8:1, endln:155:10 + \_module_inst: work@uart (work@uart), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/uart.v, line:8:1, endln:155:10 |vpiTypespec: \_logic_typespec: , line:42:1, endln:42:10 |vpiRange: @@ -13321,7 +13321,7 @@ design: (work@dff_async_reset) |vpiNet: \_logic_net: (work@uart.tx_out), line:43:14, endln:43:20 |vpiParent: - \_module: work@uart (work@uart), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/uart.v, line:8:1, endln:155:10 + \_module_inst: work@uart (work@uart), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/uart.v, line:8:1, endln:155:10 |vpiTypespec: \_logic_typespec: , line:43:1, endln:43:4 |vpiName:tx_out @@ -13330,7 +13330,7 @@ design: (work@dff_async_reset) |vpiNet: \_logic_net: (work@uart.rx_reg), line:44:14, endln:44:20 |vpiParent: - \_module: work@uart (work@uart), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/uart.v, line:8:1, endln:155:10 + \_module_inst: work@uart (work@uart), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/uart.v, line:8:1, endln:155:10 |vpiTypespec: \_logic_typespec: , line:44:1, endln:44:10 |vpiRange: @@ -13357,7 +13357,7 @@ design: (work@dff_async_reset) |vpiNet: \_logic_net: (work@uart.rx_data), line:45:14, endln:45:21 |vpiParent: - \_module: work@uart (work@uart), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/uart.v, line:8:1, endln:155:10 + \_module_inst: work@uart (work@uart), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/uart.v, line:8:1, endln:155:10 |vpiTypespec: \_logic_typespec: , line:45:1, endln:45:10 |vpiRange: @@ -13384,7 +13384,7 @@ design: (work@dff_async_reset) |vpiNet: \_logic_net: (work@uart.rx_sample_cnt), line:46:14, endln:46:27 |vpiParent: - \_module: work@uart (work@uart), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/uart.v, line:8:1, endln:155:10 + \_module_inst: work@uart (work@uart), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/uart.v, line:8:1, endln:155:10 |vpiTypespec: \_logic_typespec: , line:46:1, endln:46:10 |vpiRange: @@ -13411,7 +13411,7 @@ design: (work@dff_async_reset) |vpiNet: \_logic_net: (work@uart.rx_cnt), line:47:14, endln:47:20 |vpiParent: - \_module: work@uart (work@uart), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/uart.v, line:8:1, endln:155:10 + \_module_inst: work@uart (work@uart), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/uart.v, line:8:1, endln:155:10 |vpiTypespec: \_logic_typespec: , line:47:1, endln:47:10 |vpiRange: @@ -13438,7 +13438,7 @@ design: (work@dff_async_reset) |vpiNet: \_logic_net: (work@uart.rx_frame_err), line:48:14, endln:48:26 |vpiParent: - \_module: work@uart (work@uart), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/uart.v, line:8:1, endln:155:10 + \_module_inst: work@uart (work@uart), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/uart.v, line:8:1, endln:155:10 |vpiTypespec: \_logic_typespec: , line:48:1, endln:48:4 |vpiName:rx_frame_err @@ -13447,7 +13447,7 @@ design: (work@dff_async_reset) |vpiNet: \_logic_net: (work@uart.rx_over_run), line:49:14, endln:49:25 |vpiParent: - \_module: work@uart (work@uart), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/uart.v, line:8:1, endln:155:10 + \_module_inst: work@uart (work@uart), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/uart.v, line:8:1, endln:155:10 |vpiTypespec: \_logic_typespec: , line:49:1, endln:49:4 |vpiName:rx_over_run @@ -13456,7 +13456,7 @@ design: (work@dff_async_reset) |vpiNet: \_logic_net: (work@uart.rx_empty), line:50:14, endln:50:22 |vpiParent: - \_module: work@uart (work@uart), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/uart.v, line:8:1, endln:155:10 + \_module_inst: work@uart (work@uart), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/uart.v, line:8:1, endln:155:10 |vpiTypespec: \_logic_typespec: , line:50:1, endln:50:4 |vpiName:rx_empty @@ -13465,7 +13465,7 @@ design: (work@dff_async_reset) |vpiNet: \_logic_net: (work@uart.rx_d1), line:51:14, endln:51:19 |vpiParent: - \_module: work@uart (work@uart), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/uart.v, line:8:1, endln:155:10 + \_module_inst: work@uart (work@uart), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/uart.v, line:8:1, endln:155:10 |vpiTypespec: \_logic_typespec: , line:51:1, endln:51:4 |vpiName:rx_d1 @@ -13474,7 +13474,7 @@ design: (work@dff_async_reset) |vpiNet: \_logic_net: (work@uart.rx_d2), line:52:14, endln:52:19 |vpiParent: - \_module: work@uart (work@uart), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/uart.v, line:8:1, endln:155:10 + \_module_inst: work@uart (work@uart), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/uart.v, line:8:1, endln:155:10 |vpiTypespec: \_logic_typespec: , line:52:1, endln:52:4 |vpiName:rx_d2 @@ -13483,7 +13483,7 @@ design: (work@dff_async_reset) |vpiNet: \_logic_net: (work@uart.rx_busy), line:53:14, endln:53:21 |vpiParent: - \_module: work@uart (work@uart), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/uart.v, line:8:1, endln:155:10 + \_module_inst: work@uart (work@uart), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/uart.v, line:8:1, endln:155:10 |vpiTypespec: \_logic_typespec: , line:53:1, endln:53:4 |vpiName:rx_busy @@ -13492,7 +13492,7 @@ design: (work@dff_async_reset) |vpiNet: \_logic_net: (work@uart.reset), line:9:1, endln:9:6 |vpiParent: - \_module: work@uart (work@uart), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/uart.v, line:8:1, endln:155:10 + \_module_inst: work@uart (work@uart), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/uart.v, line:8:1, endln:155:10 |vpiTypespec: \_logic_typespec: , line:24:14, endln:24:14 |vpiName:reset @@ -13500,7 +13500,7 @@ design: (work@dff_async_reset) |vpiNet: \_logic_net: (work@uart.txclk), line:10:1, endln:10:6 |vpiParent: - \_module: work@uart (work@uart), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/uart.v, line:8:1, endln:155:10 + \_module_inst: work@uart (work@uart), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/uart.v, line:8:1, endln:155:10 |vpiTypespec: \_logic_typespec: , line:25:14, endln:25:14 |vpiName:txclk @@ -13508,7 +13508,7 @@ design: (work@dff_async_reset) |vpiNet: \_logic_net: (work@uart.ld_tx_data), line:11:1, endln:11:11 |vpiParent: - \_module: work@uart (work@uart), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/uart.v, line:8:1, endln:155:10 + \_module_inst: work@uart (work@uart), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/uart.v, line:8:1, endln:155:10 |vpiTypespec: \_logic_typespec: , line:26:14, endln:26:14 |vpiName:ld_tx_data @@ -13516,7 +13516,7 @@ design: (work@dff_async_reset) |vpiNet: \_logic_net: (work@uart.tx_data), line:12:1, endln:12:8 |vpiParent: - \_module: work@uart (work@uart), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/uart.v, line:8:1, endln:155:10 + \_module_inst: work@uart (work@uart), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/uart.v, line:8:1, endln:155:10 |vpiTypespec: \_logic_typespec: , line:27:8, endln:27:13 |vpiRange: @@ -13542,7 +13542,7 @@ design: (work@dff_async_reset) |vpiNet: \_logic_net: (work@uart.tx_enable), line:13:1, endln:13:10 |vpiParent: - \_module: work@uart (work@uart), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/uart.v, line:8:1, endln:155:10 + \_module_inst: work@uart (work@uart), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/uart.v, line:8:1, endln:155:10 |vpiTypespec: \_logic_typespec: , line:28:14, endln:28:14 |vpiName:tx_enable @@ -13550,7 +13550,7 @@ design: (work@dff_async_reset) |vpiNet: \_logic_net: (work@uart.rxclk), line:16:1, endln:16:6 |vpiParent: - \_module: work@uart (work@uart), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/uart.v, line:8:1, endln:155:10 + \_module_inst: work@uart (work@uart), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/uart.v, line:8:1, endln:155:10 |vpiTypespec: \_logic_typespec: , line:31:14, endln:31:14 |vpiName:rxclk @@ -13558,7 +13558,7 @@ design: (work@dff_async_reset) |vpiNet: \_logic_net: (work@uart.uld_rx_data), line:17:1, endln:17:12 |vpiParent: - \_module: work@uart (work@uart), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/uart.v, line:8:1, endln:155:10 + \_module_inst: work@uart (work@uart), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/uart.v, line:8:1, endln:155:10 |vpiTypespec: \_logic_typespec: , line:32:14, endln:32:14 |vpiName:uld_rx_data @@ -13566,7 +13566,7 @@ design: (work@dff_async_reset) |vpiNet: \_logic_net: (work@uart.rx_enable), line:19:1, endln:19:10 |vpiParent: - \_module: work@uart (work@uart), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/uart.v, line:8:1, endln:155:10 + \_module_inst: work@uart (work@uart), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/uart.v, line:8:1, endln:155:10 |vpiTypespec: \_logic_typespec: , line:34:14, endln:34:14 |vpiName:rx_enable @@ -13574,7 +13574,7 @@ design: (work@dff_async_reset) |vpiNet: \_logic_net: (work@uart.rx_in), line:20:1, endln:20:6 |vpiParent: - \_module: work@uart (work@uart), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/uart.v, line:8:1, endln:155:10 + \_module_inst: work@uart (work@uart), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/uart.v, line:8:1, endln:155:10 |vpiTypespec: \_logic_typespec: , line:35:14, endln:35:14 |vpiName:rx_in @@ -13583,7 +13583,7 @@ design: (work@dff_async_reset) |vpiPort: \_port: (reset), line:9:1, endln:9:6 |vpiParent: - \_module: work@uart (work@uart), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/uart.v, line:8:1, endln:155:10 + \_module_inst: work@uart (work@uart), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/uart.v, line:8:1, endln:155:10 |vpiName:reset |vpiDirection:1 |vpiLowConn: @@ -13597,7 +13597,7 @@ design: (work@dff_async_reset) |vpiPort: \_port: (txclk), line:10:1, endln:10:6 |vpiParent: - \_module: work@uart (work@uart), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/uart.v, line:8:1, endln:155:10 + \_module_inst: work@uart (work@uart), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/uart.v, line:8:1, endln:155:10 |vpiName:txclk |vpiDirection:1 |vpiLowConn: @@ -13611,7 +13611,7 @@ design: (work@dff_async_reset) |vpiPort: \_port: (ld_tx_data), line:11:1, endln:11:11 |vpiParent: - \_module: work@uart (work@uart), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/uart.v, line:8:1, endln:155:10 + \_module_inst: work@uart (work@uart), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/uart.v, line:8:1, endln:155:10 |vpiName:ld_tx_data |vpiDirection:1 |vpiLowConn: @@ -13625,7 +13625,7 @@ design: (work@dff_async_reset) |vpiPort: \_port: (tx_data), line:12:1, endln:12:8 |vpiParent: - \_module: work@uart (work@uart), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/uart.v, line:8:1, endln:155:10 + \_module_inst: work@uart (work@uart), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/uart.v, line:8:1, endln:155:10 |vpiName:tx_data |vpiDirection:1 |vpiLowConn: @@ -13659,7 +13659,7 @@ design: (work@dff_async_reset) |vpiPort: \_port: (tx_enable), line:13:1, endln:13:10 |vpiParent: - \_module: work@uart (work@uart), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/uart.v, line:8:1, endln:155:10 + \_module_inst: work@uart (work@uart), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/uart.v, line:8:1, endln:155:10 |vpiName:tx_enable |vpiDirection:1 |vpiLowConn: @@ -13673,7 +13673,7 @@ design: (work@dff_async_reset) |vpiPort: \_port: (tx_out), line:14:1, endln:14:7 |vpiParent: - \_module: work@uart (work@uart), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/uart.v, line:8:1, endln:155:10 + \_module_inst: work@uart (work@uart), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/uart.v, line:8:1, endln:155:10 |vpiName:tx_out |vpiDirection:2 |vpiLowConn: @@ -13687,7 +13687,7 @@ design: (work@dff_async_reset) |vpiPort: \_port: (tx_empty), line:15:1, endln:15:9 |vpiParent: - \_module: work@uart (work@uart), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/uart.v, line:8:1, endln:155:10 + \_module_inst: work@uart (work@uart), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/uart.v, line:8:1, endln:155:10 |vpiName:tx_empty |vpiDirection:2 |vpiLowConn: @@ -13701,7 +13701,7 @@ design: (work@dff_async_reset) |vpiPort: \_port: (rxclk), line:16:1, endln:16:6 |vpiParent: - \_module: work@uart (work@uart), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/uart.v, line:8:1, endln:155:10 + \_module_inst: work@uart (work@uart), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/uart.v, line:8:1, endln:155:10 |vpiName:rxclk |vpiDirection:1 |vpiLowConn: @@ -13715,7 +13715,7 @@ design: (work@dff_async_reset) |vpiPort: \_port: (uld_rx_data), line:17:1, endln:17:12 |vpiParent: - \_module: work@uart (work@uart), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/uart.v, line:8:1, endln:155:10 + \_module_inst: work@uart (work@uart), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/uart.v, line:8:1, endln:155:10 |vpiName:uld_rx_data |vpiDirection:1 |vpiLowConn: @@ -13729,7 +13729,7 @@ design: (work@dff_async_reset) |vpiPort: \_port: (rx_data), line:18:1, endln:18:8 |vpiParent: - \_module: work@uart (work@uart), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/uart.v, line:8:1, endln:155:10 + \_module_inst: work@uart (work@uart), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/uart.v, line:8:1, endln:155:10 |vpiName:rx_data |vpiDirection:2 |vpiLowConn: @@ -13763,7 +13763,7 @@ design: (work@dff_async_reset) |vpiPort: \_port: (rx_enable), line:19:1, endln:19:10 |vpiParent: - \_module: work@uart (work@uart), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/uart.v, line:8:1, endln:155:10 + \_module_inst: work@uart (work@uart), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/uart.v, line:8:1, endln:155:10 |vpiName:rx_enable |vpiDirection:1 |vpiLowConn: @@ -13777,7 +13777,7 @@ design: (work@dff_async_reset) |vpiPort: \_port: (rx_in), line:20:1, endln:20:6 |vpiParent: - \_module: work@uart (work@uart), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/uart.v, line:8:1, endln:155:10 + \_module_inst: work@uart (work@uart), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/uart.v, line:8:1, endln:155:10 |vpiName:rx_in |vpiDirection:1 |vpiLowConn: @@ -13791,7 +13791,7 @@ design: (work@dff_async_reset) |vpiPort: \_port: (rx_empty), line:21:1, endln:21:9 |vpiParent: - \_module: work@uart (work@uart), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/uart.v, line:8:1, endln:155:10 + \_module_inst: work@uart (work@uart), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/uart.v, line:8:1, endln:155:10 |vpiName:rx_empty |vpiDirection:2 |vpiLowConn: @@ -13807,14 +13807,14 @@ design: (work@dff_async_reset) |vpiProcess: \_always: , line:120:1, endln:153:4 |uhdmtopModules: -\_module: work@top (work@top), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/arbiter_tb.v, line:3:1, endln:64:10 +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/arbiter_tb.v, line:3:1, endln:64:10 |vpiName:work@top |vpiDefName:work@top |vpiTop:1 |vpiNet: \_logic_net: (work@top.clk), line:5:17, endln:5:20 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/arbiter_tb.v, line:3:1, endln:64:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/arbiter_tb.v, line:3:1, endln:64:10 |vpiTypespec: \_logic_typespec: , line:5:1, endln:5:4 |vpiName:clk @@ -13823,7 +13823,7 @@ design: (work@dff_async_reset) |vpiNet: \_logic_net: (work@top.rst), line:6:17, endln:6:20 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/arbiter_tb.v, line:3:1, endln:64:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/arbiter_tb.v, line:3:1, endln:64:10 |vpiTypespec: \_logic_typespec: , line:6:1, endln:6:4 |vpiName:rst @@ -13832,7 +13832,7 @@ design: (work@dff_async_reset) |vpiNet: \_logic_net: (work@top.req3), line:7:17, endln:7:21 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/arbiter_tb.v, line:3:1, endln:64:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/arbiter_tb.v, line:3:1, endln:64:10 |vpiTypespec: \_logic_typespec: , line:7:1, endln:7:4 |vpiName:req3 @@ -13841,7 +13841,7 @@ design: (work@dff_async_reset) |vpiNet: \_logic_net: (work@top.req2), line:8:17, endln:8:21 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/arbiter_tb.v, line:3:1, endln:64:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/arbiter_tb.v, line:3:1, endln:64:10 |vpiTypespec: \_logic_typespec: , line:8:1, endln:8:4 |vpiName:req2 @@ -13850,7 +13850,7 @@ design: (work@dff_async_reset) |vpiNet: \_logic_net: (work@top.req1), line:9:17, endln:9:21 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/arbiter_tb.v, line:3:1, endln:64:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/arbiter_tb.v, line:3:1, endln:64:10 |vpiTypespec: \_logic_typespec: , line:9:1, endln:9:4 |vpiName:req1 @@ -13859,7 +13859,7 @@ design: (work@dff_async_reset) |vpiNet: \_logic_net: (work@top.req0), line:10:17, endln:10:21 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/arbiter_tb.v, line:3:1, endln:64:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/arbiter_tb.v, line:3:1, endln:64:10 |vpiTypespec: \_logic_typespec: , line:10:1, endln:10:4 |vpiName:req0 @@ -13868,7 +13868,7 @@ design: (work@dff_async_reset) |vpiNet: \_logic_net: (work@top.gnt3), line:11:17, endln:11:21 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/arbiter_tb.v, line:3:1, endln:64:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/arbiter_tb.v, line:3:1, endln:64:10 |vpiTypespec: \_logic_typespec: , line:11:1, endln:11:5 |vpiName:gnt3 @@ -13877,7 +13877,7 @@ design: (work@dff_async_reset) |vpiNet: \_logic_net: (work@top.gnt2), line:12:17, endln:12:21 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/arbiter_tb.v, line:3:1, endln:64:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/arbiter_tb.v, line:3:1, endln:64:10 |vpiTypespec: \_logic_typespec: , line:12:1, endln:12:5 |vpiName:gnt2 @@ -13886,7 +13886,7 @@ design: (work@dff_async_reset) |vpiNet: \_logic_net: (work@top.gnt1), line:13:17, endln:13:21 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/arbiter_tb.v, line:3:1, endln:64:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/arbiter_tb.v, line:3:1, endln:64:10 |vpiTypespec: \_logic_typespec: , line:13:1, endln:13:5 |vpiName:gnt1 @@ -13895,7 +13895,7 @@ design: (work@dff_async_reset) |vpiNet: \_logic_net: (work@top.gnt0), line:14:17, endln:14:21 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/arbiter_tb.v, line:3:1, endln:64:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/arbiter_tb.v, line:3:1, endln:64:10 |vpiTypespec: \_logic_typespec: , line:14:1, endln:14:5 |vpiName:gnt0 @@ -13906,16 +13906,16 @@ design: (work@dff_async_reset) \_always: , line:17:1, endln:17:22 |vpiProcess: \_initial: , line:19:1, endln:48:4 - |vpiModule: - \_module: work@arbiter (work@top.U), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/arbiter_tb.v, line:51:1, endln:62:3 + |vpiModuleInst: + \_module_inst: work@arbiter (work@top.U), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/arbiter_tb.v, line:51:1, endln:62:3 |vpiParent: - \_module: work@top (work@top), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/arbiter_tb.v, line:3:1, endln:64:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/arbiter_tb.v, line:3:1, endln:64:10 |vpiName:U |vpiFullName:work@top.U |vpiVariables: \_integer_var: (work@top.U.i), line:3:10, endln:3:11 |vpiParent: - \_module: work@arbiter (work@top.U), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/arbiter_tb.v, line:51:1, endln:62:3 + \_module_inst: work@arbiter (work@top.U), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/arbiter_tb.v, line:51:1, endln:62:3 |vpiTypespec: \_integer_typespec: , line:3:2, endln:3:9 |vpiSigned:1 @@ -13925,7 +13925,7 @@ design: (work@dff_async_reset) |vpiVariables: \_integer_var: (work@top.U.j), line:3:12, endln:3:13 |vpiParent: - \_module: work@arbiter (work@top.U), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/arbiter_tb.v, line:51:1, endln:62:3 + \_module_inst: work@arbiter (work@top.U), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/arbiter_tb.v, line:51:1, endln:62:3 |vpiTypespec: \_integer_typespec: , line:3:2, endln:3:9 |vpiName:j @@ -13934,7 +13934,7 @@ design: (work@dff_async_reset) |vpiVariables: \_integer_var: (work@top.U.k), line:3:14, endln:3:15 |vpiParent: - \_module: work@arbiter (work@top.U), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/arbiter_tb.v, line:51:1, endln:62:3 + \_module_inst: work@arbiter (work@top.U), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/arbiter_tb.v, line:51:1, endln:62:3 |vpiTypespec: \_integer_typespec: , line:3:2, endln:3:9 |vpiName:k @@ -13943,7 +13943,7 @@ design: (work@dff_async_reset) |vpiVariables: \_integer_var: (work@top.U.p), line:3:16, endln:3:17 |vpiParent: - \_module: work@arbiter (work@top.U), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/arbiter_tb.v, line:51:1, endln:62:3 + \_module_inst: work@arbiter (work@top.U), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/arbiter_tb.v, line:51:1, endln:62:3 |vpiTypespec: \_integer_typespec: , line:3:2, endln:3:9 |vpiName:p @@ -13952,7 +13952,7 @@ design: (work@dff_async_reset) |vpiVariables: \_integer_var: (work@top.U.q), line:3:18, endln:3:19 |vpiParent: - \_module: work@arbiter (work@top.U), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/arbiter_tb.v, line:51:1, endln:62:3 + \_module_inst: work@arbiter (work@top.U), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/arbiter_tb.v, line:51:1, endln:62:3 |vpiTypespec: \_integer_typespec: , line:3:2, endln:3:9 |vpiName:q @@ -13961,7 +13961,7 @@ design: (work@dff_async_reset) |vpiVariables: \_integer_var: (work@top.U.r), line:3:20, endln:3:21 |vpiParent: - \_module: work@arbiter (work@top.U), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/arbiter_tb.v, line:51:1, endln:62:3 + \_module_inst: work@arbiter (work@top.U), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/arbiter_tb.v, line:51:1, endln:62:3 |vpiTypespec: \_integer_typespec: , line:3:2, endln:3:9 |vpiName:r @@ -13970,7 +13970,7 @@ design: (work@dff_async_reset) |vpiVariables: \_integer_var: (work@top.U.s), line:3:22, endln:3:23 |vpiParent: - \_module: work@arbiter (work@top.U), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/arbiter_tb.v, line:51:1, endln:62:3 + \_module_inst: work@arbiter (work@top.U), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/arbiter_tb.v, line:51:1, endln:62:3 |vpiTypespec: \_integer_typespec: , line:3:2, endln:3:9 |vpiName:s @@ -13979,7 +13979,7 @@ design: (work@dff_async_reset) |vpiVariables: \_integer_var: (work@top.U.t), line:3:24, endln:3:25 |vpiParent: - \_module: work@arbiter (work@top.U), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/arbiter_tb.v, line:51:1, endln:62:3 + \_module_inst: work@arbiter (work@top.U), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/arbiter_tb.v, line:51:1, endln:62:3 |vpiTypespec: \_integer_typespec: , line:3:2, endln:3:9 |vpiName:t @@ -13988,7 +13988,7 @@ design: (work@dff_async_reset) |vpiVariables: \_integer_var: (work@top.U.u), line:3:26, endln:3:27 |vpiParent: - \_module: work@arbiter (work@top.U), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/arbiter_tb.v, line:51:1, endln:62:3 + \_module_inst: work@arbiter (work@top.U), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/arbiter_tb.v, line:51:1, endln:62:3 |vpiTypespec: \_integer_typespec: , line:3:2, endln:3:9 |vpiName:u @@ -13997,7 +13997,7 @@ design: (work@dff_async_reset) |vpiVariables: \_integer_var: (work@top.U.v), line:3:28, endln:3:29 |vpiParent: - \_module: work@arbiter (work@top.U), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/arbiter_tb.v, line:51:1, endln:62:3 + \_module_inst: work@arbiter (work@top.U), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/arbiter_tb.v, line:51:1, endln:62:3 |vpiTypespec: \_integer_typespec: , line:3:2, endln:3:9 |vpiName:v @@ -14006,7 +14006,7 @@ design: (work@dff_async_reset) |vpiParameter: \_parameter: (work@top.U.NUMUNITS), line:7:12, endln:7:20 |vpiParent: - \_module: work@arbiter (work@top.U), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/arbiter_tb.v, line:51:1, endln:62:3 + \_module_inst: work@arbiter (work@top.U), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/arbiter_tb.v, line:51:1, endln:62:3 |UINT:8 |vpiTypespec: \_int_typespec: @@ -14017,7 +14017,7 @@ design: (work@dff_async_reset) |vpiParameter: \_parameter: (work@top.U.ADDRESSWIDTH), line:8:12, endln:8:24 |vpiParent: - \_module: work@arbiter (work@top.U), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/arbiter_tb.v, line:51:1, endln:62:3 + \_module_inst: work@arbiter (work@top.U), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/arbiter_tb.v, line:51:1, endln:62:3 |UINT:3 |vpiTypespec: \_int_typespec: @@ -14028,7 +14028,7 @@ design: (work@dff_async_reset) |vpiParamAssign: \_param_assign: , line:7:12, endln:7:24 |vpiParent: - \_module: work@arbiter (work@top.U), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/arbiter_tb.v, line:51:1, endln:62:3 + \_module_inst: work@arbiter (work@top.U), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/arbiter_tb.v, line:51:1, endln:62:3 |vpiRhs: \_constant: , line:7:23, endln:7:24 |vpiDecompile:8 @@ -14042,7 +14042,7 @@ design: (work@dff_async_reset) |vpiParamAssign: \_param_assign: , line:8:12, endln:8:28 |vpiParent: - \_module: work@arbiter (work@top.U), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/arbiter_tb.v, line:51:1, endln:62:3 + \_module_inst: work@arbiter (work@top.U), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/arbiter_tb.v, line:51:1, endln:62:3 |vpiRhs: \_constant: , line:8:27, endln:8:28 |vpiDecompile:3 @@ -14059,7 +14059,7 @@ design: (work@dff_async_reset) |vpiNet: \_logic_net: (work@top.U.tmp_prio), line:20:27, endln:20:35 |vpiParent: - \_module: work@arbiter (work@top.U), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/arbiter_tb.v, line:51:1, endln:62:3 + \_module_inst: work@arbiter (work@top.U), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/arbiter_tb.v, line:51:1, endln:62:3 |vpiTypespec: \_logic_typespec: , line:20:2, endln:20:26 |vpiRange: @@ -14086,7 +14086,7 @@ design: (work@dff_async_reset) |vpiNet: \_logic_net: (work@top.U.grant), line:30:23, endln:30:28 |vpiParent: - \_module: work@arbiter (work@top.U), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/arbiter_tb.v, line:51:1, endln:62:3 + \_module_inst: work@arbiter (work@top.U), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/arbiter_tb.v, line:51:1, endln:62:3 |vpiTypespec: \_logic_typespec: , line:30:2, endln:30:22 |vpiRange: @@ -14113,7 +14113,7 @@ design: (work@dff_async_reset) |vpiNet: \_logic_net: (work@top.U.grantD), line:31:23, endln:31:29 |vpiParent: - \_module: work@arbiter (work@top.U), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/arbiter_tb.v, line:51:1, endln:62:3 + \_module_inst: work@arbiter (work@top.U), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/arbiter_tb.v, line:51:1, endln:62:3 |vpiTypespec: \_logic_typespec: , line:31:2, endln:31:22 |vpiRange: @@ -14140,7 +14140,7 @@ design: (work@dff_async_reset) |vpiNet: \_logic_net: (work@top.U.next), line:32:27, endln:32:31 |vpiParent: - \_module: work@arbiter (work@top.U), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/arbiter_tb.v, line:51:1, endln:62:3 + \_module_inst: work@arbiter (work@top.U), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/arbiter_tb.v, line:51:1, endln:62:3 |vpiTypespec: \_logic_typespec: , line:32:2, endln:32:26 |vpiRange: @@ -14167,7 +14167,7 @@ design: (work@dff_async_reset) |vpiNet: \_logic_net: (work@top.U.nextNext), line:33:27, endln:33:35 |vpiParent: - \_module: work@arbiter (work@top.U), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/arbiter_tb.v, line:51:1, endln:62:3 + \_module_inst: work@arbiter (work@top.U), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/arbiter_tb.v, line:51:1, endln:62:3 |vpiTypespec: \_logic_typespec: , line:33:2, endln:33:26 |vpiRange: @@ -14194,7 +14194,7 @@ design: (work@dff_async_reset) |vpiNet: \_logic_net: (work@top.U.found), line:36:23, endln:36:28 |vpiParent: - \_module: work@arbiter (work@top.U), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/arbiter_tb.v, line:51:1, endln:62:3 + \_module_inst: work@arbiter (work@top.U), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/arbiter_tb.v, line:51:1, endln:62:3 |vpiTypespec: \_logic_typespec: , line:36:2, endln:36:22 |vpiRange: @@ -14221,7 +14221,7 @@ design: (work@dff_async_reset) |vpiNet: \_logic_net: (work@top.U.min), line:40:27, endln:40:30 |vpiParent: - \_module: work@arbiter (work@top.U), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/arbiter_tb.v, line:51:1, endln:62:3 + \_module_inst: work@arbiter (work@top.U), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/arbiter_tb.v, line:51:1, endln:62:3 |vpiTypespec: \_logic_typespec: , line:40:2, endln:40:26 |vpiRange: @@ -14248,7 +14248,7 @@ design: (work@dff_async_reset) |vpiNet: \_logic_net: (work@top.U.minPrio), line:42:23, endln:42:30 |vpiParent: - \_module: work@arbiter (work@top.U), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/arbiter_tb.v, line:51:1, endln:62:3 + \_module_inst: work@arbiter (work@top.U), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/arbiter_tb.v, line:51:1, endln:62:3 |vpiTypespec: \_logic_typespec: , line:42:2, endln:42:22 |vpiRange: @@ -14275,7 +14275,7 @@ design: (work@dff_async_reset) |vpiNet: \_logic_net: (work@top.U.prioRequest), line:44:24, endln:44:35 |vpiParent: - \_module: work@arbiter (work@top.U), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/arbiter_tb.v, line:51:1, endln:62:3 + \_module_inst: work@arbiter (work@top.U), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/arbiter_tb.v, line:51:1, endln:62:3 |vpiTypespec: \_logic_typespec: , line:44:2, endln:44:23 |vpiRange: @@ -14302,7 +14302,7 @@ design: (work@dff_async_reset) |vpiNet: \_logic_net: (work@top.U.finalRequest), line:46:23, endln:46:35 |vpiParent: - \_module: work@arbiter (work@top.U), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/arbiter_tb.v, line:51:1, endln:62:3 + \_module_inst: work@arbiter (work@top.U), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/arbiter_tb.v, line:51:1, endln:62:3 |vpiTypespec: \_logic_typespec: , line:46:2, endln:46:22 |vpiRange: @@ -14329,7 +14329,7 @@ design: (work@dff_async_reset) |vpiNet: \_logic_net: (work@top.U.clock), line:2:16, endln:2:21 |vpiParent: - \_module: work@arbiter (work@top.U), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/arbiter_tb.v, line:51:1, endln:62:3 + \_module_inst: work@arbiter (work@top.U), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/arbiter_tb.v, line:51:1, endln:62:3 |vpiTypespec: \_logic_typespec: , line:12:8, endln:12:8 |vpiName:clock @@ -14337,7 +14337,7 @@ design: (work@dff_async_reset) |vpiNet: \_logic_net: (work@top.U.reset), line:2:23, endln:2:28 |vpiParent: - \_module: work@arbiter (work@top.U), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/arbiter_tb.v, line:51:1, endln:62:3 + \_module_inst: work@arbiter (work@top.U), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/arbiter_tb.v, line:51:1, endln:62:3 |vpiTypespec: \_logic_typespec: , line:13:8, endln:13:8 |vpiName:reset @@ -14345,7 +14345,7 @@ design: (work@dff_async_reset) |vpiNet: \_logic_net: (work@top.U.roundORpriority), line:2:30, endln:2:45 |vpiParent: - \_module: work@arbiter (work@top.U), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/arbiter_tb.v, line:51:1, endln:62:3 + \_module_inst: work@arbiter (work@top.U), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/arbiter_tb.v, line:51:1, endln:62:3 |vpiTypespec: \_logic_typespec: , line:14:8, endln:14:8 |vpiName:roundORpriority @@ -14353,7 +14353,7 @@ design: (work@dff_async_reset) |vpiNet: \_logic_net: (work@top.U.request), line:2:47, endln:2:54 |vpiParent: - \_module: work@arbiter (work@top.U), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/arbiter_tb.v, line:51:1, endln:62:3 + \_module_inst: work@arbiter (work@top.U), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/arbiter_tb.v, line:51:1, endln:62:3 |vpiTypespec: \_logic_typespec: , line:15:8, endln:15:24 |vpiRange: @@ -14379,7 +14379,7 @@ design: (work@dff_async_reset) |vpiNet: \_logic_net: (work@top.U.tpriority), line:2:56, endln:2:65 |vpiParent: - \_module: work@arbiter (work@top.U), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/arbiter_tb.v, line:51:1, endln:62:3 + \_module_inst: work@arbiter (work@top.U), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/arbiter_tb.v, line:51:1, endln:62:3 |vpiTypespec: \_logic_typespec: , line:16:8, endln:16:37 |vpiRange: @@ -14405,7 +14405,7 @@ design: (work@dff_async_reset) |vpiArrayNet: \_array_net: (work@top.U.prio), line:19:27, endln:19:31 |vpiParent: - \_module: work@arbiter (work@top.U), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/arbiter_tb.v, line:51:1, endln:62:3 + \_module_inst: work@arbiter (work@top.U), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/arbiter_tb.v, line:51:1, endln:62:3 |vpiSize:8 |vpiName:prio |vpiFullName:work@top.U.prio @@ -14456,7 +14456,7 @@ design: (work@dff_async_reset) |vpiArrayNet: \_array_net: (work@top.U.scan), line:34:27, endln:34:31 |vpiParent: - \_module: work@arbiter (work@top.U), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/arbiter_tb.v, line:51:1, endln:62:3 + \_module_inst: work@arbiter (work@top.U), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/arbiter_tb.v, line:51:1, endln:62:3 |vpiSize:8 |vpiName:scan |vpiFullName:work@top.U.scan @@ -14507,7 +14507,7 @@ design: (work@dff_async_reset) |vpiArrayNet: \_array_net: (work@top.U.selectPrio), line:38:27, endln:38:37 |vpiParent: - \_module: work@arbiter (work@top.U), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/arbiter_tb.v, line:51:1, endln:62:3 + \_module_inst: work@arbiter (work@top.U), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/arbiter_tb.v, line:51:1, endln:62:3 |vpiSize:8 |vpiName:selectPrio |vpiFullName:work@top.U.selectPrio @@ -14556,11 +14556,11 @@ design: (work@dff_async_reset) |vpiFullName:work@top.U.selectPrio |vpiNetType:48 |vpiInstance: - \_module: work@top (work@top), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/arbiter_tb.v, line:3:1, endln:64:10 + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/arbiter_tb.v, line:3:1, endln:64:10 |vpiPort: \_port: (clock), line:2:16, endln:2:21 |vpiParent: - \_module: work@arbiter (work@top.U), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/arbiter_tb.v, line:51:1, endln:62:3 + \_module_inst: work@arbiter (work@top.U), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/arbiter_tb.v, line:51:1, endln:62:3 |vpiName:clock |vpiDirection:1 |vpiHighConn: @@ -14580,7 +14580,7 @@ design: (work@dff_async_reset) |vpiPort: \_port: (reset), line:2:23, endln:2:28 |vpiParent: - \_module: work@arbiter (work@top.U), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/arbiter_tb.v, line:51:1, endln:62:3 + \_module_inst: work@arbiter (work@top.U), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/arbiter_tb.v, line:51:1, endln:62:3 |vpiName:reset |vpiDirection:1 |vpiHighConn: @@ -14600,7 +14600,7 @@ design: (work@dff_async_reset) |vpiPort: \_port: (roundORpriority), line:2:30, endln:2:45 |vpiParent: - \_module: work@arbiter (work@top.U), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/arbiter_tb.v, line:51:1, endln:62:3 + \_module_inst: work@arbiter (work@top.U), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/arbiter_tb.v, line:51:1, endln:62:3 |vpiName:roundORpriority |vpiDirection:1 |vpiHighConn: @@ -14620,7 +14620,7 @@ design: (work@dff_async_reset) |vpiPort: \_port: (request), line:2:47, endln:2:54 |vpiParent: - \_module: work@arbiter (work@top.U), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/arbiter_tb.v, line:51:1, endln:62:3 + \_module_inst: work@arbiter (work@top.U), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/arbiter_tb.v, line:51:1, endln:62:3 |vpiName:request |vpiDirection:1 |vpiHighConn: @@ -14660,7 +14660,7 @@ design: (work@dff_async_reset) |vpiPort: \_port: (tpriority), line:2:56, endln:2:65 |vpiParent: - \_module: work@arbiter (work@top.U), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/arbiter_tb.v, line:51:1, endln:62:3 + \_module_inst: work@arbiter (work@top.U), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/arbiter_tb.v, line:51:1, endln:62:3 |vpiName:tpriority |vpiDirection:1 |vpiHighConn: @@ -14700,7 +14700,7 @@ design: (work@dff_async_reset) |vpiPort: \_port: (grant), line:2:67, endln:2:72 |vpiParent: - \_module: work@arbiter (work@top.U), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/arbiter_tb.v, line:51:1, endln:62:3 + \_module_inst: work@arbiter (work@top.U), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/arbiter_tb.v, line:51:1, endln:62:3 |vpiName:grant |vpiDirection:2 |vpiHighConn: @@ -14784,14 +14784,14 @@ design: (work@dff_async_reset) |vpiActual: \_logic_net: (work@top.U.prioRequest), line:44:24, endln:44:35 |uhdmtopModules: -\_module: work@full_adder_gates (work@full_adder_gates), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/full_adder.v, line:7:1, endln:18:10 +\_module_inst: work@full_adder_gates (work@full_adder_gates), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/full_adder.v, line:7:1, endln:18:10 |vpiName:work@full_adder_gates |vpiDefName:work@full_adder_gates |vpiTop:1 |vpiNet: \_logic_net: (work@full_adder_gates.and1), line:10:6, endln:10:10 |vpiParent: - \_module: work@full_adder_gates (work@full_adder_gates), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/full_adder.v, line:7:1, endln:18:10 + \_module_inst: work@full_adder_gates (work@full_adder_gates), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/full_adder.v, line:7:1, endln:18:10 |vpiTypespec: \_logic_typespec: , line:10:1, endln:10:5 |vpiName:and1 @@ -14800,7 +14800,7 @@ design: (work@dff_async_reset) |vpiNet: \_logic_net: (work@full_adder_gates.and2), line:10:11, endln:10:15 |vpiParent: - \_module: work@full_adder_gates (work@full_adder_gates), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/full_adder.v, line:7:1, endln:18:10 + \_module_inst: work@full_adder_gates (work@full_adder_gates), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/full_adder.v, line:7:1, endln:18:10 |vpiTypespec: \_logic_typespec: , line:10:1, endln:10:5 |vpiName:and2 @@ -14809,7 +14809,7 @@ design: (work@dff_async_reset) |vpiNet: \_logic_net: (work@full_adder_gates.and3), line:10:16, endln:10:20 |vpiParent: - \_module: work@full_adder_gates (work@full_adder_gates), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/full_adder.v, line:7:1, endln:18:10 + \_module_inst: work@full_adder_gates (work@full_adder_gates), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/full_adder.v, line:7:1, endln:18:10 |vpiTypespec: \_logic_typespec: , line:10:1, endln:10:5 |vpiName:and3 @@ -14818,7 +14818,7 @@ design: (work@dff_async_reset) |vpiNet: \_logic_net: (work@full_adder_gates.sum1), line:10:21, endln:10:25 |vpiParent: - \_module: work@full_adder_gates (work@full_adder_gates), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/full_adder.v, line:7:1, endln:18:10 + \_module_inst: work@full_adder_gates (work@full_adder_gates), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/full_adder.v, line:7:1, endln:18:10 |vpiTypespec: \_logic_typespec: , line:10:1, endln:10:5 |vpiName:sum1 @@ -14827,7 +14827,7 @@ design: (work@dff_async_reset) |vpiNet: \_logic_net: (work@full_adder_gates.x), line:7:25, endln:7:26 |vpiParent: - \_module: work@full_adder_gates (work@full_adder_gates), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/full_adder.v, line:7:1, endln:18:10 + \_module_inst: work@full_adder_gates (work@full_adder_gates), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/full_adder.v, line:7:1, endln:18:10 |vpiTypespec: \_logic_typespec: , line:8:7, endln:8:7 |vpiName:x @@ -14835,7 +14835,7 @@ design: (work@dff_async_reset) |vpiNet: \_logic_net: (work@full_adder_gates.y), line:7:27, endln:7:28 |vpiParent: - \_module: work@full_adder_gates (work@full_adder_gates), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/full_adder.v, line:7:1, endln:18:10 + \_module_inst: work@full_adder_gates (work@full_adder_gates), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/full_adder.v, line:7:1, endln:18:10 |vpiTypespec: \_logic_typespec: , line:8:7, endln:8:7 |vpiName:y @@ -14843,7 +14843,7 @@ design: (work@dff_async_reset) |vpiNet: \_logic_net: (work@full_adder_gates.z), line:7:29, endln:7:30 |vpiParent: - \_module: work@full_adder_gates (work@full_adder_gates), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/full_adder.v, line:7:1, endln:18:10 + \_module_inst: work@full_adder_gates (work@full_adder_gates), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/full_adder.v, line:7:1, endln:18:10 |vpiTypespec: \_logic_typespec: , line:8:7, endln:8:7 |vpiName:z @@ -14851,7 +14851,7 @@ design: (work@dff_async_reset) |vpiNet: \_logic_net: (work@full_adder_gates.sum), line:7:31, endln:7:34 |vpiParent: - \_module: work@full_adder_gates (work@full_adder_gates), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/full_adder.v, line:7:1, endln:18:10 + \_module_inst: work@full_adder_gates (work@full_adder_gates), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/full_adder.v, line:7:1, endln:18:10 |vpiTypespec: \_logic_typespec: , line:9:8, endln:9:8 |vpiName:sum @@ -14859,7 +14859,7 @@ design: (work@dff_async_reset) |vpiNet: \_logic_net: (work@full_adder_gates.carry), line:7:35, endln:7:40 |vpiParent: - \_module: work@full_adder_gates (work@full_adder_gates), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/full_adder.v, line:7:1, endln:18:10 + \_module_inst: work@full_adder_gates (work@full_adder_gates), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/full_adder.v, line:7:1, endln:18:10 |vpiTypespec: \_logic_typespec: , line:9:8, endln:9:8 |vpiName:carry @@ -14868,7 +14868,7 @@ design: (work@dff_async_reset) |vpiPort: \_port: (x), line:7:25, endln:7:26 |vpiParent: - \_module: work@full_adder_gates (work@full_adder_gates), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/full_adder.v, line:7:1, endln:18:10 + \_module_inst: work@full_adder_gates (work@full_adder_gates), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/full_adder.v, line:7:1, endln:18:10 |vpiName:x |vpiDirection:1 |vpiLowConn: @@ -14882,7 +14882,7 @@ design: (work@dff_async_reset) |vpiPort: \_port: (y), line:7:27, endln:7:28 |vpiParent: - \_module: work@full_adder_gates (work@full_adder_gates), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/full_adder.v, line:7:1, endln:18:10 + \_module_inst: work@full_adder_gates (work@full_adder_gates), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/full_adder.v, line:7:1, endln:18:10 |vpiName:y |vpiDirection:1 |vpiLowConn: @@ -14896,7 +14896,7 @@ design: (work@dff_async_reset) |vpiPort: \_port: (z), line:7:29, endln:7:30 |vpiParent: - \_module: work@full_adder_gates (work@full_adder_gates), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/full_adder.v, line:7:1, endln:18:10 + \_module_inst: work@full_adder_gates (work@full_adder_gates), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/full_adder.v, line:7:1, endln:18:10 |vpiName:z |vpiDirection:1 |vpiLowConn: @@ -14910,7 +14910,7 @@ design: (work@dff_async_reset) |vpiPort: \_port: (sum), line:7:31, endln:7:34 |vpiParent: - \_module: work@full_adder_gates (work@full_adder_gates), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/full_adder.v, line:7:1, endln:18:10 + \_module_inst: work@full_adder_gates (work@full_adder_gates), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/full_adder.v, line:7:1, endln:18:10 |vpiName:sum |vpiDirection:2 |vpiLowConn: @@ -14924,7 +14924,7 @@ design: (work@dff_async_reset) |vpiPort: \_port: (carry), line:7:35, endln:7:40 |vpiParent: - \_module: work@full_adder_gates (work@full_adder_gates), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/full_adder.v, line:7:1, endln:18:10 + \_module_inst: work@full_adder_gates (work@full_adder_gates), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/full_adder.v, line:7:1, endln:18:10 |vpiName:carry |vpiDirection:2 |vpiLowConn: @@ -14938,7 +14938,7 @@ design: (work@dff_async_reset) |vpiPrimitive: \_gate: work@and (work@full_adder_gates.U_and1), line:12:5, endln:12:22 |vpiParent: - \_module: work@full_adder_gates (work@full_adder_gates), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/full_adder.v, line:7:1, endln:18:10 + \_module_inst: work@full_adder_gates (work@full_adder_gates), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/full_adder.v, line:7:1, endln:18:10 |vpiDefName:work@and |vpiName:U_and1 |vpiFullName:work@full_adder_gates.U_and1 @@ -14987,7 +14987,7 @@ design: (work@dff_async_reset) |vpiPrimitive: \_gate: work@and (work@full_adder_gates.U_and2), line:13:5, endln:13:22 |vpiParent: - \_module: work@full_adder_gates (work@full_adder_gates), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/full_adder.v, line:7:1, endln:18:10 + \_module_inst: work@full_adder_gates (work@full_adder_gates), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/full_adder.v, line:7:1, endln:18:10 |vpiDefName:work@and |vpiName:U_and2 |vpiFullName:work@full_adder_gates.U_and2 @@ -15036,7 +15036,7 @@ design: (work@dff_async_reset) |vpiPrimitive: \_gate: work@and (work@full_adder_gates.U_and3), line:14:5, endln:14:22 |vpiParent: - \_module: work@full_adder_gates (work@full_adder_gates), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/full_adder.v, line:7:1, endln:18:10 + \_module_inst: work@full_adder_gates (work@full_adder_gates), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/full_adder.v, line:7:1, endln:18:10 |vpiDefName:work@and |vpiName:U_and3 |vpiFullName:work@full_adder_gates.U_and3 @@ -15085,7 +15085,7 @@ design: (work@dff_async_reset) |vpiPrimitive: \_gate: work@or (work@full_adder_gates.U_or), line:15:5, endln:15:34 |vpiParent: - \_module: work@full_adder_gates (work@full_adder_gates), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/full_adder.v, line:7:1, endln:18:10 + \_module_inst: work@full_adder_gates (work@full_adder_gates), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/full_adder.v, line:7:1, endln:18:10 |vpiDefName:work@or |vpiName:U_or |vpiFullName:work@full_adder_gates.U_or @@ -15148,7 +15148,7 @@ design: (work@dff_async_reset) |vpiPrimitive: \_gate: work@xor (work@full_adder_gates.U_sum), line:16:5, endln:16:22 |vpiParent: - \_module: work@full_adder_gates (work@full_adder_gates), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/full_adder.v, line:7:1, endln:18:10 + \_module_inst: work@full_adder_gates (work@full_adder_gates), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/full_adder.v, line:7:1, endln:18:10 |vpiDefName:work@xor |vpiName:U_sum |vpiFullName:work@full_adder_gates.U_sum @@ -15209,12 +15209,12 @@ design: (work@dff_async_reset) |vpiActual: \_logic_net: (work@full_adder_gates.z), line:7:29, endln:7:30 |uhdmtopModules: -\_module: work@LFSR_TASK (work@LFSR_TASK), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/lfsr_task.v, line:2:1, endln:37:10 +\_module_inst: work@LFSR_TASK (work@LFSR_TASK), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/lfsr_task.v, line:2:1, endln:37:10 |vpiName:work@LFSR_TASK |vpiParameter: \_parameter: (work@LFSR_TASK.Chain1), line:7:17, endln:7:23 |vpiParent: - \_module: work@LFSR_TASK (work@LFSR_TASK), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/lfsr_task.v, line:2:1, endln:37:10 + \_module_inst: work@LFSR_TASK (work@LFSR_TASK), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/lfsr_task.v, line:2:1, endln:37:10 |BIN:10001110 |vpiTypespec: \_int_typespec: , line:7:11, endln:7:16 @@ -15245,7 +15245,7 @@ design: (work@dff_async_reset) |vpiParameter: \_parameter: (work@LFSR_TASK.Chain2), line:8:17, endln:8:23 |vpiParent: - \_module: work@LFSR_TASK (work@LFSR_TASK), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/lfsr_task.v, line:2:1, endln:37:10 + \_module_inst: work@LFSR_TASK (work@LFSR_TASK), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/lfsr_task.v, line:2:1, endln:37:10 |BIN:10101110 |vpiTypespec: \_int_typespec: , line:8:11, endln:8:16 @@ -15276,7 +15276,7 @@ design: (work@dff_async_reset) |vpiParamAssign: \_param_assign: , line:7:17, endln:7:37 |vpiParent: - \_module: work@LFSR_TASK (work@LFSR_TASK), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/lfsr_task.v, line:2:1, endln:37:10 + \_module_inst: work@LFSR_TASK (work@LFSR_TASK), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/lfsr_task.v, line:2:1, endln:37:10 |vpiRhs: \_constant: , line:7:26, endln:7:37 |vpiDecompile:8'b10001110 @@ -15290,7 +15290,7 @@ design: (work@dff_async_reset) |vpiParamAssign: \_param_assign: , line:8:17, endln:8:37 |vpiParent: - \_module: work@LFSR_TASK (work@LFSR_TASK), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/lfsr_task.v, line:2:1, endln:37:10 + \_module_inst: work@LFSR_TASK (work@LFSR_TASK), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/lfsr_task.v, line:2:1, endln:37:10 |vpiRhs: \_constant: , line:8:26, endln:8:37 |vpiDecompile:8'b10101110 @@ -15308,7 +15308,7 @@ design: (work@dff_async_reset) |vpiNet: \_logic_net: (work@LFSR_TASK.random1), line:6:11, endln:6:18 |vpiParent: - \_module: work@LFSR_TASK (work@LFSR_TASK), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/lfsr_task.v, line:2:1, endln:37:10 + \_module_inst: work@LFSR_TASK (work@LFSR_TASK), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/lfsr_task.v, line:2:1, endln:37:10 |vpiTypespec: \_logic_typespec: , line:6:1, endln:6:10 |vpiRange: @@ -15335,7 +15335,7 @@ design: (work@dff_async_reset) |vpiNet: \_logic_net: (work@LFSR_TASK.random2), line:6:20, endln:6:27 |vpiParent: - \_module: work@LFSR_TASK (work@LFSR_TASK), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/lfsr_task.v, line:2:1, endln:37:10 + \_module_inst: work@LFSR_TASK (work@LFSR_TASK), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/lfsr_task.v, line:2:1, endln:37:10 |vpiTypespec: \_logic_typespec: , line:6:1, endln:6:10 |vpiName:random2 @@ -15344,7 +15344,7 @@ design: (work@dff_async_reset) |vpiNet: \_logic_net: (work@LFSR_TASK.clock), line:2:19, endln:2:24 |vpiParent: - \_module: work@LFSR_TASK (work@LFSR_TASK), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/lfsr_task.v, line:2:1, endln:37:10 + \_module_inst: work@LFSR_TASK (work@LFSR_TASK), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/lfsr_task.v, line:2:1, endln:37:10 |vpiTypespec: \_logic_typespec: , line:3:7, endln:3:7 |vpiName:clock @@ -15352,13 +15352,13 @@ design: (work@dff_async_reset) |vpiNet: \_logic_net: (work@LFSR_TASK.Reset), line:2:26, endln:2:31 |vpiParent: - \_module: work@LFSR_TASK (work@LFSR_TASK), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/lfsr_task.v, line:2:1, endln:37:10 + \_module_inst: work@LFSR_TASK (work@LFSR_TASK), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/lfsr_task.v, line:2:1, endln:37:10 |vpiName:Reset |vpiFullName:work@LFSR_TASK.Reset |vpiNet: \_logic_net: (work@LFSR_TASK.seed1), line:2:33, endln:2:38 |vpiParent: - \_module: work@LFSR_TASK (work@LFSR_TASK), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/lfsr_task.v, line:2:1, endln:37:10 + \_module_inst: work@LFSR_TASK (work@LFSR_TASK), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/lfsr_task.v, line:2:1, endln:37:10 |vpiTypespec: \_logic_typespec: , line:4:7, endln:4:12 |vpiRange: @@ -15384,7 +15384,7 @@ design: (work@dff_async_reset) |vpiNet: \_logic_net: (work@LFSR_TASK.seed2), line:2:40, endln:2:45 |vpiParent: - \_module: work@LFSR_TASK (work@LFSR_TASK), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/lfsr_task.v, line:2:1, endln:37:10 + \_module_inst: work@LFSR_TASK (work@LFSR_TASK), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/lfsr_task.v, line:2:1, endln:37:10 |vpiName:seed2 |vpiFullName:work@LFSR_TASK.seed2 |vpiNet: @@ -15395,7 +15395,7 @@ design: (work@dff_async_reset) |vpiPort: \_port: (clock), line:2:19, endln:2:24 |vpiParent: - \_module: work@LFSR_TASK (work@LFSR_TASK), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/lfsr_task.v, line:2:1, endln:37:10 + \_module_inst: work@LFSR_TASK (work@LFSR_TASK), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/lfsr_task.v, line:2:1, endln:37:10 |vpiName:clock |vpiDirection:1 |vpiLowConn: @@ -15409,7 +15409,7 @@ design: (work@dff_async_reset) |vpiPort: \_port: (Reset), line:2:26, endln:2:31 |vpiParent: - \_module: work@LFSR_TASK (work@LFSR_TASK), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/lfsr_task.v, line:2:1, endln:37:10 + \_module_inst: work@LFSR_TASK (work@LFSR_TASK), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/lfsr_task.v, line:2:1, endln:37:10 |vpiName:Reset |vpiDirection:1 |vpiLowConn: @@ -15421,7 +15421,7 @@ design: (work@dff_async_reset) |vpiPort: \_port: (seed1), line:2:33, endln:2:38 |vpiParent: - \_module: work@LFSR_TASK (work@LFSR_TASK), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/lfsr_task.v, line:2:1, endln:37:10 + \_module_inst: work@LFSR_TASK (work@LFSR_TASK), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/lfsr_task.v, line:2:1, endln:37:10 |vpiName:seed1 |vpiDirection:1 |vpiLowConn: @@ -15455,7 +15455,7 @@ design: (work@dff_async_reset) |vpiPort: \_port: (seed2), line:2:40, endln:2:45 |vpiParent: - \_module: work@LFSR_TASK (work@LFSR_TASK), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/lfsr_task.v, line:2:1, endln:37:10 + \_module_inst: work@LFSR_TASK (work@LFSR_TASK), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/lfsr_task.v, line:2:1, endln:37:10 |vpiName:seed2 |vpiDirection:1 |vpiLowConn: @@ -15467,7 +15467,7 @@ design: (work@dff_async_reset) |vpiPort: \_port: (random1), line:2:47, endln:2:54 |vpiParent: - \_module: work@LFSR_TASK (work@LFSR_TASK), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/lfsr_task.v, line:2:1, endln:37:10 + \_module_inst: work@LFSR_TASK (work@LFSR_TASK), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/lfsr_task.v, line:2:1, endln:37:10 |vpiName:random1 |vpiDirection:2 |vpiLowConn: @@ -15501,7 +15501,7 @@ design: (work@dff_async_reset) |vpiPort: \_port: (random2), line:2:56, endln:2:63 |vpiParent: - \_module: work@LFSR_TASK (work@LFSR_TASK), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/lfsr_task.v, line:2:1, endln:37:10 + \_module_inst: work@LFSR_TASK (work@LFSR_TASK), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/lfsr_task.v, line:2:1, endln:37:10 |vpiName:random2 |vpiDirection:2 |vpiLowConn: @@ -15517,14 +15517,14 @@ design: (work@dff_async_reset) |vpiProcess: \_always: , line:32:1, endln:36:39 |uhdmtopModules: -\_module: work@mux21_switch (work@mux21_switch), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/mux21.v, line:7:1, endln:22:10 +\_module_inst: work@mux21_switch (work@mux21_switch), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/mux21.v, line:7:1, endln:22:10 |vpiName:work@mux21_switch |vpiDefName:work@mux21_switch |vpiTop:1 |vpiNet: \_logic_net: (work@mux21_switch.e), line:11:18, endln:11:19 |vpiParent: - \_module: work@mux21_switch (work@mux21_switch), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/mux21.v, line:7:1, endln:22:10 + \_module_inst: work@mux21_switch (work@mux21_switch), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/mux21.v, line:7:1, endln:22:10 |vpiTypespec: \_logic_typespec: , line:11:4, endln:11:8 |vpiName:e @@ -15533,7 +15533,7 @@ design: (work@dff_async_reset) |vpiNet: \_logic_net: (work@mux21_switch.power), line:13:12, endln:13:17 |vpiParent: - \_module: work@mux21_switch (work@mux21_switch), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/mux21.v, line:7:1, endln:22:10 + \_module_inst: work@mux21_switch (work@mux21_switch), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/mux21.v, line:7:1, endln:22:10 |vpiTypespec: \_logic_typespec: , line:13:4, endln:13:11 |vpiName:power @@ -15542,7 +15542,7 @@ design: (work@dff_async_reset) |vpiNet: \_logic_net: (work@mux21_switch.ground), line:14:12, endln:14:18 |vpiParent: - \_module: work@mux21_switch (work@mux21_switch), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/mux21.v, line:7:1, endln:22:10 + \_module_inst: work@mux21_switch (work@mux21_switch), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/mux21.v, line:7:1, endln:22:10 |vpiTypespec: \_logic_typespec: , line:14:4, endln:14:11 |vpiName:ground @@ -15551,7 +15551,7 @@ design: (work@dff_async_reset) |vpiNet: \_logic_net: (work@mux21_switch.out), line:7:22, endln:7:25 |vpiParent: - \_module: work@mux21_switch (work@mux21_switch), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/mux21.v, line:7:1, endln:22:10 + \_module_inst: work@mux21_switch (work@mux21_switch), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/mux21.v, line:7:1, endln:22:10 |vpiTypespec: \_logic_typespec: , line:9:11, endln:9:11 |vpiName:out @@ -15559,7 +15559,7 @@ design: (work@dff_async_reset) |vpiNet: \_logic_net: (work@mux21_switch.ctrl), line:7:27, endln:7:31 |vpiParent: - \_module: work@mux21_switch (work@mux21_switch), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/mux21.v, line:7:1, endln:22:10 + \_module_inst: work@mux21_switch (work@mux21_switch), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/mux21.v, line:7:1, endln:22:10 |vpiTypespec: \_logic_typespec: , line:10:11, endln:10:11 |vpiName:ctrl @@ -15567,7 +15567,7 @@ design: (work@dff_async_reset) |vpiNet: \_logic_net: (work@mux21_switch.in1), line:7:33, endln:7:36 |vpiParent: - \_module: work@mux21_switch (work@mux21_switch), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/mux21.v, line:7:1, endln:22:10 + \_module_inst: work@mux21_switch (work@mux21_switch), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/mux21.v, line:7:1, endln:22:10 |vpiTypespec: \_logic_typespec: , line:10:11, endln:10:11 |vpiName:in1 @@ -15575,7 +15575,7 @@ design: (work@dff_async_reset) |vpiNet: \_logic_net: (work@mux21_switch.in2), line:7:38, endln:7:41 |vpiParent: - \_module: work@mux21_switch (work@mux21_switch), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/mux21.v, line:7:1, endln:22:10 + \_module_inst: work@mux21_switch (work@mux21_switch), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/mux21.v, line:7:1, endln:22:10 |vpiTypespec: \_logic_typespec: , line:10:11, endln:10:11 |vpiName:in2 @@ -15583,7 +15583,7 @@ design: (work@dff_async_reset) |vpiNet: \_logic_net: (work@mux21_switch.w), line:19:23, endln:19:24 |vpiParent: - \_module: work@mux21_switch (work@mux21_switch), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/mux21.v, line:7:1, endln:22:10 + \_module_inst: work@mux21_switch (work@mux21_switch), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/mux21.v, line:7:1, endln:22:10 |vpiName:w |vpiFullName:work@mux21_switch.w |vpiNetType:1 @@ -15591,7 +15591,7 @@ design: (work@dff_async_reset) |vpiPort: \_port: (out), line:7:22, endln:7:25 |vpiParent: - \_module: work@mux21_switch (work@mux21_switch), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/mux21.v, line:7:1, endln:22:10 + \_module_inst: work@mux21_switch (work@mux21_switch), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/mux21.v, line:7:1, endln:22:10 |vpiName:out |vpiDirection:2 |vpiLowConn: @@ -15605,7 +15605,7 @@ design: (work@dff_async_reset) |vpiPort: \_port: (ctrl), line:7:27, endln:7:31 |vpiParent: - \_module: work@mux21_switch (work@mux21_switch), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/mux21.v, line:7:1, endln:22:10 + \_module_inst: work@mux21_switch (work@mux21_switch), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/mux21.v, line:7:1, endln:22:10 |vpiName:ctrl |vpiDirection:1 |vpiLowConn: @@ -15619,7 +15619,7 @@ design: (work@dff_async_reset) |vpiPort: \_port: (in1), line:7:33, endln:7:36 |vpiParent: - \_module: work@mux21_switch (work@mux21_switch), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/mux21.v, line:7:1, endln:22:10 + \_module_inst: work@mux21_switch (work@mux21_switch), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/mux21.v, line:7:1, endln:22:10 |vpiName:in1 |vpiDirection:1 |vpiLowConn: @@ -15633,7 +15633,7 @@ design: (work@dff_async_reset) |vpiPort: \_port: (in2), line:7:38, endln:7:41 |vpiParent: - \_module: work@mux21_switch (work@mux21_switch), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/mux21.v, line:7:1, endln:22:10 + \_module_inst: work@mux21_switch (work@mux21_switch), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/mux21.v, line:7:1, endln:22:10 |vpiName:in2 |vpiDirection:1 |vpiLowConn: @@ -15647,7 +15647,7 @@ design: (work@dff_async_reset) |vpiPrimitive: \_switch_tran: work@pmos (work@mux21_switch.N1), line:16:9, endln:16:28 |vpiParent: - \_module: work@mux21_switch (work@mux21_switch), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/mux21.v, line:7:1, endln:22:10 + \_module_inst: work@mux21_switch (work@mux21_switch), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/mux21.v, line:7:1, endln:22:10 |vpiDefName:work@pmos |vpiName:N1 |vpiFullName:work@mux21_switch.N1 @@ -15696,7 +15696,7 @@ design: (work@dff_async_reset) |vpiPrimitive: \_switch_tran: work@nmos (work@mux21_switch.N2), line:17:9, endln:17:29 |vpiParent: - \_module: work@mux21_switch (work@mux21_switch), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/mux21.v, line:7:1, endln:22:10 + \_module_inst: work@mux21_switch (work@mux21_switch), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/mux21.v, line:7:1, endln:22:10 |vpiDefName:work@nmos |vpiName:N2 |vpiFullName:work@mux21_switch.N2 @@ -15745,7 +15745,7 @@ design: (work@dff_async_reset) |vpiPrimitive: \_switch_tran: work@cmos (work@mux21_switch.C1), line:19:9, endln:19:31 |vpiParent: - \_module: work@mux21_switch (work@mux21_switch), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/mux21.v, line:7:1, endln:22:10 + \_module_inst: work@mux21_switch (work@mux21_switch), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/mux21.v, line:7:1, endln:22:10 |vpiDefName:work@cmos |vpiName:C1 |vpiFullName:work@mux21_switch.C1 @@ -15808,7 +15808,7 @@ design: (work@dff_async_reset) |vpiPrimitive: \_switch_tran: work@cmos (work@mux21_switch.C2), line:20:9, endln:20:31 |vpiParent: - \_module: work@mux21_switch (work@mux21_switch), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/mux21.v, line:7:1, endln:22:10 + \_module_inst: work@mux21_switch (work@mux21_switch), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/mux21.v, line:7:1, endln:22:10 |vpiDefName:work@cmos |vpiName:C2 |vpiFullName:work@mux21_switch.C2 diff --git a/third_party/tests/SimpleUVM/SimpleUVM.log b/third_party/tests/SimpleUVM/SimpleUVM.log index 4bf57fe538..b2c4d9cfdf 100644 --- a/third_party/tests/SimpleUVM/SimpleUVM.log +++ b/third_party/tests/SimpleUVM/SimpleUVM.log @@ -805,7 +805,7 @@ indexed_part_select 41 initial 3 int_typespec 2433 int_var 1163 -interface 1 +interface_inst 1 interface_typespec 1 io_decl 6908 logic_net 310 @@ -814,7 +814,7 @@ logic_var 39 long_int_typespec 99 long_int_var 7 method_func_call 8000 -module 29 +module_inst 29 named_begin 6 named_event 8 named_fork 3 diff --git a/third_party/tests/SimpleVMM/SimpleVMM.log b/third_party/tests/SimpleVMM/SimpleVMM.log index 8d1f085f57..3b087b9168 100644 --- a/third_party/tests/SimpleVMM/SimpleVMM.log +++ b/third_party/tests/SimpleVMM/SimpleVMM.log @@ -242,7 +242,7 @@ io_decl 911 logic_typespec 26 logic_var 7 method_func_call 976 -module 9 +module_inst 9 named_event 16 operation 861 package 2 diff --git a/third_party/tests/Sky130Cell/Sky130Cell.log b/third_party/tests/Sky130Cell/Sky130Cell.log index d7e208ba74..aa46e31e38 100644 --- a/third_party/tests/Sky130Cell/Sky130Cell.log +++ b/third_party/tests/Sky130Cell/Sky130Cell.log @@ -3084,13 +3084,13 @@ Processing: -cd cells/cells -DUNIT_DELAY -writepp -parse -nocache -nobuiltin -no design: (work@sky130_fd_sc_hd__tapvgnd2) |vpiName:work@sky130_fd_sc_hd__tapvgnd2 |uhdmallModules: -\_module: work@sky130_fd_sc_hd__tapvgnd2 (work@sky130_fd_sc_hd__tapvgnd2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__tapvgnd2.functional.v, line:34:1, endln:36:10 +\_module_inst: work@sky130_fd_sc_hd__tapvgnd2 (work@sky130_fd_sc_hd__tapvgnd2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__tapvgnd2.functional.v, line:34:1, endln:36:10 |vpiParent: \_design: (work@sky130_fd_sc_hd__tapvgnd2) |vpiFullName:work@sky130_fd_sc_hd__tapvgnd2 |vpiDefName:work@sky130_fd_sc_hd__tapvgnd2 |uhdmtopModules: -\_module: work@sky130_fd_sc_hd__tapvgnd2 (work@sky130_fd_sc_hd__tapvgnd2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__tapvgnd2.functional.v, line:34:1, endln:36:10 +\_module_inst: work@sky130_fd_sc_hd__tapvgnd2 (work@sky130_fd_sc_hd__tapvgnd2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__tapvgnd2.functional.v, line:34:1, endln:36:10 |vpiName:work@sky130_fd_sc_hd__tapvgnd2 |vpiDefName:work@sky130_fd_sc_hd__tapvgnd2 |vpiTop:1 @@ -3228,7 +3228,7 @@ design: (work@sky130_fd_sc_hd__dfrtp) |vpiSize:3 |STRING:? b ?x : 0 : 0 |uhdmallModules: -\_module: work@sky130_fd_sc_hd__dfrtp (work@sky130_fd_sc_hd__dfrtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfrtp.functional.v, line:36:1, endln:58:10 +\_module_inst: work@sky130_fd_sc_hd__dfrtp (work@sky130_fd_sc_hd__dfrtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfrtp.functional.v, line:36:1, endln:58:10 |vpiParent: \_design: (work@sky130_fd_sc_hd__dfrtp) |vpiFullName:work@sky130_fd_sc_hd__dfrtp @@ -3236,45 +3236,45 @@ design: (work@sky130_fd_sc_hd__dfrtp) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__dfrtp.buf_Q), line:50:10, endln:50:15 |vpiParent: - \_module: work@sky130_fd_sc_hd__dfrtp (work@sky130_fd_sc_hd__dfrtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfrtp.functional.v, line:36:1, endln:58:10 + \_module_inst: work@sky130_fd_sc_hd__dfrtp (work@sky130_fd_sc_hd__dfrtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfrtp.functional.v, line:36:1, endln:58:10 |vpiName:buf_Q |vpiFullName:work@sky130_fd_sc_hd__dfrtp.buf_Q |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__dfrtp.RESET), line:51:10, endln:51:15 |vpiParent: - \_module: work@sky130_fd_sc_hd__dfrtp (work@sky130_fd_sc_hd__dfrtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfrtp.functional.v, line:36:1, endln:58:10 + \_module_inst: work@sky130_fd_sc_hd__dfrtp (work@sky130_fd_sc_hd__dfrtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfrtp.functional.v, line:36:1, endln:58:10 |vpiName:RESET |vpiFullName:work@sky130_fd_sc_hd__dfrtp.RESET |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__dfrtp.Q), line:37:5, endln:37:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__dfrtp (work@sky130_fd_sc_hd__dfrtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfrtp.functional.v, line:36:1, endln:58:10 + \_module_inst: work@sky130_fd_sc_hd__dfrtp (work@sky130_fd_sc_hd__dfrtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfrtp.functional.v, line:36:1, endln:58:10 |vpiName:Q |vpiFullName:work@sky130_fd_sc_hd__dfrtp.Q |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__dfrtp.CLK), line:38:5, endln:38:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__dfrtp (work@sky130_fd_sc_hd__dfrtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfrtp.functional.v, line:36:1, endln:58:10 + \_module_inst: work@sky130_fd_sc_hd__dfrtp (work@sky130_fd_sc_hd__dfrtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfrtp.functional.v, line:36:1, endln:58:10 |vpiName:CLK |vpiFullName:work@sky130_fd_sc_hd__dfrtp.CLK |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__dfrtp.D), line:39:5, endln:39:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__dfrtp (work@sky130_fd_sc_hd__dfrtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfrtp.functional.v, line:36:1, endln:58:10 + \_module_inst: work@sky130_fd_sc_hd__dfrtp (work@sky130_fd_sc_hd__dfrtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfrtp.functional.v, line:36:1, endln:58:10 |vpiName:D |vpiFullName:work@sky130_fd_sc_hd__dfrtp.D |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__dfrtp.RESET_B), line:40:5, endln:40:12 |vpiParent: - \_module: work@sky130_fd_sc_hd__dfrtp (work@sky130_fd_sc_hd__dfrtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfrtp.functional.v, line:36:1, endln:58:10 + \_module_inst: work@sky130_fd_sc_hd__dfrtp (work@sky130_fd_sc_hd__dfrtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfrtp.functional.v, line:36:1, endln:58:10 |vpiName:RESET_B |vpiFullName:work@sky130_fd_sc_hd__dfrtp.RESET_B |vpiPort: \_port: (Q), line:37:5, endln:37:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__dfrtp (work@sky130_fd_sc_hd__dfrtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfrtp.functional.v, line:36:1, endln:58:10 + \_module_inst: work@sky130_fd_sc_hd__dfrtp (work@sky130_fd_sc_hd__dfrtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfrtp.functional.v, line:36:1, endln:58:10 |vpiName:Q |vpiDirection:2 |vpiLowConn: @@ -3286,7 +3286,7 @@ design: (work@sky130_fd_sc_hd__dfrtp) |vpiPort: \_port: (CLK), line:38:5, endln:38:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__dfrtp (work@sky130_fd_sc_hd__dfrtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfrtp.functional.v, line:36:1, endln:58:10 + \_module_inst: work@sky130_fd_sc_hd__dfrtp (work@sky130_fd_sc_hd__dfrtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfrtp.functional.v, line:36:1, endln:58:10 |vpiName:CLK |vpiDirection:1 |vpiLowConn: @@ -3298,7 +3298,7 @@ design: (work@sky130_fd_sc_hd__dfrtp) |vpiPort: \_port: (D), line:39:5, endln:39:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__dfrtp (work@sky130_fd_sc_hd__dfrtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfrtp.functional.v, line:36:1, endln:58:10 + \_module_inst: work@sky130_fd_sc_hd__dfrtp (work@sky130_fd_sc_hd__dfrtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfrtp.functional.v, line:36:1, endln:58:10 |vpiName:D |vpiDirection:1 |vpiLowConn: @@ -3310,7 +3310,7 @@ design: (work@sky130_fd_sc_hd__dfrtp) |vpiPort: \_port: (RESET_B), line:40:5, endln:40:12 |vpiParent: - \_module: work@sky130_fd_sc_hd__dfrtp (work@sky130_fd_sc_hd__dfrtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfrtp.functional.v, line:36:1, endln:58:10 + \_module_inst: work@sky130_fd_sc_hd__dfrtp (work@sky130_fd_sc_hd__dfrtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfrtp.functional.v, line:36:1, endln:58:10 |vpiName:RESET_B |vpiDirection:1 |vpiLowConn: @@ -3320,14 +3320,14 @@ design: (work@sky130_fd_sc_hd__dfrtp) |vpiTypedef: \_logic_typespec: , line:47:12, endln:47:12 |uhdmtopModules: -\_module: work@sky130_fd_sc_hd__dfrtp (work@sky130_fd_sc_hd__dfrtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfrtp.functional.v, line:36:1, endln:58:10 +\_module_inst: work@sky130_fd_sc_hd__dfrtp (work@sky130_fd_sc_hd__dfrtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfrtp.functional.v, line:36:1, endln:58:10 |vpiName:work@sky130_fd_sc_hd__dfrtp |vpiDefName:work@sky130_fd_sc_hd__dfrtp |vpiTop:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__dfrtp.buf_Q), line:50:10, endln:50:15 |vpiParent: - \_module: work@sky130_fd_sc_hd__dfrtp (work@sky130_fd_sc_hd__dfrtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfrtp.functional.v, line:36:1, endln:58:10 + \_module_inst: work@sky130_fd_sc_hd__dfrtp (work@sky130_fd_sc_hd__dfrtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfrtp.functional.v, line:36:1, endln:58:10 |vpiTypespec: \_logic_typespec: , line:50:5, endln:50:9 |vpiName:buf_Q @@ -3336,7 +3336,7 @@ design: (work@sky130_fd_sc_hd__dfrtp) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__dfrtp.RESET), line:51:10, endln:51:15 |vpiParent: - \_module: work@sky130_fd_sc_hd__dfrtp (work@sky130_fd_sc_hd__dfrtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfrtp.functional.v, line:36:1, endln:58:10 + \_module_inst: work@sky130_fd_sc_hd__dfrtp (work@sky130_fd_sc_hd__dfrtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfrtp.functional.v, line:36:1, endln:58:10 |vpiTypespec: \_logic_typespec: , line:51:5, endln:51:9 |vpiName:RESET @@ -3345,7 +3345,7 @@ design: (work@sky130_fd_sc_hd__dfrtp) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__dfrtp.Q), line:37:5, endln:37:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__dfrtp (work@sky130_fd_sc_hd__dfrtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfrtp.functional.v, line:36:1, endln:58:10 + \_module_inst: work@sky130_fd_sc_hd__dfrtp (work@sky130_fd_sc_hd__dfrtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfrtp.functional.v, line:36:1, endln:58:10 |vpiTypespec: \_logic_typespec: , line:44:12, endln:44:12 |vpiName:Q @@ -3353,7 +3353,7 @@ design: (work@sky130_fd_sc_hd__dfrtp) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__dfrtp.CLK), line:38:5, endln:38:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__dfrtp (work@sky130_fd_sc_hd__dfrtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfrtp.functional.v, line:36:1, endln:58:10 + \_module_inst: work@sky130_fd_sc_hd__dfrtp (work@sky130_fd_sc_hd__dfrtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfrtp.functional.v, line:36:1, endln:58:10 |vpiTypespec: \_logic_typespec: , line:45:12, endln:45:12 |vpiName:CLK @@ -3361,7 +3361,7 @@ design: (work@sky130_fd_sc_hd__dfrtp) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__dfrtp.D), line:39:5, endln:39:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__dfrtp (work@sky130_fd_sc_hd__dfrtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfrtp.functional.v, line:36:1, endln:58:10 + \_module_inst: work@sky130_fd_sc_hd__dfrtp (work@sky130_fd_sc_hd__dfrtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfrtp.functional.v, line:36:1, endln:58:10 |vpiTypespec: \_logic_typespec: , line:46:12, endln:46:12 |vpiName:D @@ -3369,7 +3369,7 @@ design: (work@sky130_fd_sc_hd__dfrtp) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__dfrtp.RESET_B), line:40:5, endln:40:12 |vpiParent: - \_module: work@sky130_fd_sc_hd__dfrtp (work@sky130_fd_sc_hd__dfrtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfrtp.functional.v, line:36:1, endln:58:10 + \_module_inst: work@sky130_fd_sc_hd__dfrtp (work@sky130_fd_sc_hd__dfrtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfrtp.functional.v, line:36:1, endln:58:10 |vpiTypespec: \_logic_typespec: , line:47:12, endln:47:12 |vpiName:RESET_B @@ -3378,7 +3378,7 @@ design: (work@sky130_fd_sc_hd__dfrtp) |vpiPort: \_port: (Q), line:37:5, endln:37:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__dfrtp (work@sky130_fd_sc_hd__dfrtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfrtp.functional.v, line:36:1, endln:58:10 + \_module_inst: work@sky130_fd_sc_hd__dfrtp (work@sky130_fd_sc_hd__dfrtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfrtp.functional.v, line:36:1, endln:58:10 |vpiName:Q |vpiDirection:2 |vpiLowConn: @@ -3392,7 +3392,7 @@ design: (work@sky130_fd_sc_hd__dfrtp) |vpiPort: \_port: (CLK), line:38:5, endln:38:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__dfrtp (work@sky130_fd_sc_hd__dfrtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfrtp.functional.v, line:36:1, endln:58:10 + \_module_inst: work@sky130_fd_sc_hd__dfrtp (work@sky130_fd_sc_hd__dfrtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfrtp.functional.v, line:36:1, endln:58:10 |vpiName:CLK |vpiDirection:1 |vpiLowConn: @@ -3406,7 +3406,7 @@ design: (work@sky130_fd_sc_hd__dfrtp) |vpiPort: \_port: (D), line:39:5, endln:39:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__dfrtp (work@sky130_fd_sc_hd__dfrtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfrtp.functional.v, line:36:1, endln:58:10 + \_module_inst: work@sky130_fd_sc_hd__dfrtp (work@sky130_fd_sc_hd__dfrtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfrtp.functional.v, line:36:1, endln:58:10 |vpiName:D |vpiDirection:1 |vpiLowConn: @@ -3420,7 +3420,7 @@ design: (work@sky130_fd_sc_hd__dfrtp) |vpiPort: \_port: (RESET_B), line:40:5, endln:40:12 |vpiParent: - \_module: work@sky130_fd_sc_hd__dfrtp (work@sky130_fd_sc_hd__dfrtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfrtp.functional.v, line:36:1, endln:58:10 + \_module_inst: work@sky130_fd_sc_hd__dfrtp (work@sky130_fd_sc_hd__dfrtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfrtp.functional.v, line:36:1, endln:58:10 |vpiName:RESET_B |vpiDirection:1 |vpiLowConn: @@ -3434,7 +3434,7 @@ design: (work@sky130_fd_sc_hd__dfrtp) |vpiPrimitive: \_gate: work@not (work@sky130_fd_sc_hd__dfrtp.not0), line:54:45, endln:54:75 |vpiParent: - \_module: work@sky130_fd_sc_hd__dfrtp (work@sky130_fd_sc_hd__dfrtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfrtp.functional.v, line:36:1, endln:58:10 + \_module_inst: work@sky130_fd_sc_hd__dfrtp (work@sky130_fd_sc_hd__dfrtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfrtp.functional.v, line:36:1, endln:58:10 |vpiDefName:work@not |vpiName:not0 |vpiFullName:work@sky130_fd_sc_hd__dfrtp.not0 @@ -3469,7 +3469,7 @@ design: (work@sky130_fd_sc_hd__dfrtp) |vpiPrimitive: \_udp: work@sky130_fd_sc_hd__udp_dff$PR (work@sky130_fd_sc_hd__dfrtp.dff0), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfrtp.functional.v, line:55:5, endln:55:65 |vpiParent: - \_module: work@sky130_fd_sc_hd__dfrtp (work@sky130_fd_sc_hd__dfrtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfrtp.functional.v, line:36:1, endln:58:10 + \_module_inst: work@sky130_fd_sc_hd__dfrtp (work@sky130_fd_sc_hd__dfrtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfrtp.functional.v, line:36:1, endln:58:10 |vpiDefName:work@sky130_fd_sc_hd__udp_dff$PR |vpiName:dff0 |vpiFullName:work@sky130_fd_sc_hd__dfrtp.dff0 @@ -3478,7 +3478,7 @@ design: (work@sky130_fd_sc_hd__dfrtp) |vpiPrimitive: \_gate: work@buf (work@sky130_fd_sc_hd__dfrtp.buf0), line:56:45, endln:56:75 |vpiParent: - \_module: work@sky130_fd_sc_hd__dfrtp (work@sky130_fd_sc_hd__dfrtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfrtp.functional.v, line:36:1, endln:58:10 + \_module_inst: work@sky130_fd_sc_hd__dfrtp (work@sky130_fd_sc_hd__dfrtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfrtp.functional.v, line:36:1, endln:58:10 |vpiDefName:work@buf |vpiName:buf0 |vpiFullName:work@sky130_fd_sc_hd__dfrtp.buf0 @@ -3711,7 +3711,7 @@ design: (work@sky130_fd_sc_hd__sdfxbp) |vpiSize:3 |STRING:? 1 1 : 1 |uhdmallModules: -\_module: work@sky130_fd_sc_hd__sdfxbp (work@sky130_fd_sc_hd__sdfxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfxbp.functional.v, line:37:1, endln:64:10 +\_module_inst: work@sky130_fd_sc_hd__sdfxbp (work@sky130_fd_sc_hd__sdfxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfxbp.functional.v, line:37:1, endln:64:10 |vpiParent: \_design: (work@sky130_fd_sc_hd__sdfxbp) |vpiFullName:work@sky130_fd_sc_hd__sdfxbp @@ -3719,57 +3719,57 @@ design: (work@sky130_fd_sc_hd__sdfxbp) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__sdfxbp.buf_Q), line:55:10, endln:55:15 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfxbp (work@sky130_fd_sc_hd__sdfxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfxbp.functional.v, line:37:1, endln:64:10 + \_module_inst: work@sky130_fd_sc_hd__sdfxbp (work@sky130_fd_sc_hd__sdfxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfxbp.functional.v, line:37:1, endln:64:10 |vpiName:buf_Q |vpiFullName:work@sky130_fd_sc_hd__sdfxbp.buf_Q |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__sdfxbp.mux_out), line:56:10, endln:56:17 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfxbp (work@sky130_fd_sc_hd__sdfxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfxbp.functional.v, line:37:1, endln:64:10 + \_module_inst: work@sky130_fd_sc_hd__sdfxbp (work@sky130_fd_sc_hd__sdfxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfxbp.functional.v, line:37:1, endln:64:10 |vpiName:mux_out |vpiFullName:work@sky130_fd_sc_hd__sdfxbp.mux_out |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__sdfxbp.Q), line:38:5, endln:38:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfxbp (work@sky130_fd_sc_hd__sdfxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfxbp.functional.v, line:37:1, endln:64:10 + \_module_inst: work@sky130_fd_sc_hd__sdfxbp (work@sky130_fd_sc_hd__sdfxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfxbp.functional.v, line:37:1, endln:64:10 |vpiName:Q |vpiFullName:work@sky130_fd_sc_hd__sdfxbp.Q |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__sdfxbp.Q_N), line:39:5, endln:39:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfxbp (work@sky130_fd_sc_hd__sdfxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfxbp.functional.v, line:37:1, endln:64:10 + \_module_inst: work@sky130_fd_sc_hd__sdfxbp (work@sky130_fd_sc_hd__sdfxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfxbp.functional.v, line:37:1, endln:64:10 |vpiName:Q_N |vpiFullName:work@sky130_fd_sc_hd__sdfxbp.Q_N |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__sdfxbp.CLK), line:40:5, endln:40:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfxbp (work@sky130_fd_sc_hd__sdfxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfxbp.functional.v, line:37:1, endln:64:10 + \_module_inst: work@sky130_fd_sc_hd__sdfxbp (work@sky130_fd_sc_hd__sdfxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfxbp.functional.v, line:37:1, endln:64:10 |vpiName:CLK |vpiFullName:work@sky130_fd_sc_hd__sdfxbp.CLK |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__sdfxbp.D), line:41:5, endln:41:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfxbp (work@sky130_fd_sc_hd__sdfxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfxbp.functional.v, line:37:1, endln:64:10 + \_module_inst: work@sky130_fd_sc_hd__sdfxbp (work@sky130_fd_sc_hd__sdfxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfxbp.functional.v, line:37:1, endln:64:10 |vpiName:D |vpiFullName:work@sky130_fd_sc_hd__sdfxbp.D |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__sdfxbp.SCD), line:42:5, endln:42:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfxbp (work@sky130_fd_sc_hd__sdfxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfxbp.functional.v, line:37:1, endln:64:10 + \_module_inst: work@sky130_fd_sc_hd__sdfxbp (work@sky130_fd_sc_hd__sdfxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfxbp.functional.v, line:37:1, endln:64:10 |vpiName:SCD |vpiFullName:work@sky130_fd_sc_hd__sdfxbp.SCD |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__sdfxbp.SCE), line:43:5, endln:43:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfxbp (work@sky130_fd_sc_hd__sdfxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfxbp.functional.v, line:37:1, endln:64:10 + \_module_inst: work@sky130_fd_sc_hd__sdfxbp (work@sky130_fd_sc_hd__sdfxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfxbp.functional.v, line:37:1, endln:64:10 |vpiName:SCE |vpiFullName:work@sky130_fd_sc_hd__sdfxbp.SCE |vpiPort: \_port: (Q), line:38:5, endln:38:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfxbp (work@sky130_fd_sc_hd__sdfxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfxbp.functional.v, line:37:1, endln:64:10 + \_module_inst: work@sky130_fd_sc_hd__sdfxbp (work@sky130_fd_sc_hd__sdfxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfxbp.functional.v, line:37:1, endln:64:10 |vpiName:Q |vpiDirection:2 |vpiLowConn: @@ -3781,7 +3781,7 @@ design: (work@sky130_fd_sc_hd__sdfxbp) |vpiPort: \_port: (Q_N), line:39:5, endln:39:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfxbp (work@sky130_fd_sc_hd__sdfxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfxbp.functional.v, line:37:1, endln:64:10 + \_module_inst: work@sky130_fd_sc_hd__sdfxbp (work@sky130_fd_sc_hd__sdfxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfxbp.functional.v, line:37:1, endln:64:10 |vpiName:Q_N |vpiDirection:2 |vpiLowConn: @@ -3793,7 +3793,7 @@ design: (work@sky130_fd_sc_hd__sdfxbp) |vpiPort: \_port: (CLK), line:40:5, endln:40:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfxbp (work@sky130_fd_sc_hd__sdfxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfxbp.functional.v, line:37:1, endln:64:10 + \_module_inst: work@sky130_fd_sc_hd__sdfxbp (work@sky130_fd_sc_hd__sdfxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfxbp.functional.v, line:37:1, endln:64:10 |vpiName:CLK |vpiDirection:1 |vpiLowConn: @@ -3805,7 +3805,7 @@ design: (work@sky130_fd_sc_hd__sdfxbp) |vpiPort: \_port: (D), line:41:5, endln:41:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfxbp (work@sky130_fd_sc_hd__sdfxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfxbp.functional.v, line:37:1, endln:64:10 + \_module_inst: work@sky130_fd_sc_hd__sdfxbp (work@sky130_fd_sc_hd__sdfxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfxbp.functional.v, line:37:1, endln:64:10 |vpiName:D |vpiDirection:1 |vpiLowConn: @@ -3817,7 +3817,7 @@ design: (work@sky130_fd_sc_hd__sdfxbp) |vpiPort: \_port: (SCD), line:42:5, endln:42:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfxbp (work@sky130_fd_sc_hd__sdfxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfxbp.functional.v, line:37:1, endln:64:10 + \_module_inst: work@sky130_fd_sc_hd__sdfxbp (work@sky130_fd_sc_hd__sdfxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfxbp.functional.v, line:37:1, endln:64:10 |vpiName:SCD |vpiDirection:1 |vpiLowConn: @@ -3829,7 +3829,7 @@ design: (work@sky130_fd_sc_hd__sdfxbp) |vpiPort: \_port: (SCE), line:43:5, endln:43:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfxbp (work@sky130_fd_sc_hd__sdfxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfxbp.functional.v, line:37:1, endln:64:10 + \_module_inst: work@sky130_fd_sc_hd__sdfxbp (work@sky130_fd_sc_hd__sdfxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfxbp.functional.v, line:37:1, endln:64:10 |vpiName:SCE |vpiDirection:1 |vpiLowConn: @@ -3839,14 +3839,14 @@ design: (work@sky130_fd_sc_hd__sdfxbp) |vpiTypedef: \_logic_typespec: , line:52:12, endln:52:12 |uhdmtopModules: -\_module: work@sky130_fd_sc_hd__sdfxbp (work@sky130_fd_sc_hd__sdfxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfxbp.functional.v, line:37:1, endln:64:10 +\_module_inst: work@sky130_fd_sc_hd__sdfxbp (work@sky130_fd_sc_hd__sdfxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfxbp.functional.v, line:37:1, endln:64:10 |vpiName:work@sky130_fd_sc_hd__sdfxbp |vpiDefName:work@sky130_fd_sc_hd__sdfxbp |vpiTop:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__sdfxbp.buf_Q), line:55:10, endln:55:15 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfxbp (work@sky130_fd_sc_hd__sdfxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfxbp.functional.v, line:37:1, endln:64:10 + \_module_inst: work@sky130_fd_sc_hd__sdfxbp (work@sky130_fd_sc_hd__sdfxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfxbp.functional.v, line:37:1, endln:64:10 |vpiTypespec: \_logic_typespec: , line:55:5, endln:55:9 |vpiName:buf_Q @@ -3855,7 +3855,7 @@ design: (work@sky130_fd_sc_hd__sdfxbp) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__sdfxbp.mux_out), line:56:10, endln:56:17 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfxbp (work@sky130_fd_sc_hd__sdfxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfxbp.functional.v, line:37:1, endln:64:10 + \_module_inst: work@sky130_fd_sc_hd__sdfxbp (work@sky130_fd_sc_hd__sdfxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfxbp.functional.v, line:37:1, endln:64:10 |vpiTypespec: \_logic_typespec: , line:56:5, endln:56:9 |vpiName:mux_out @@ -3864,7 +3864,7 @@ design: (work@sky130_fd_sc_hd__sdfxbp) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__sdfxbp.Q), line:38:5, endln:38:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfxbp (work@sky130_fd_sc_hd__sdfxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfxbp.functional.v, line:37:1, endln:64:10 + \_module_inst: work@sky130_fd_sc_hd__sdfxbp (work@sky130_fd_sc_hd__sdfxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfxbp.functional.v, line:37:1, endln:64:10 |vpiTypespec: \_logic_typespec: , line:47:12, endln:47:12 |vpiName:Q @@ -3872,7 +3872,7 @@ design: (work@sky130_fd_sc_hd__sdfxbp) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__sdfxbp.Q_N), line:39:5, endln:39:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfxbp (work@sky130_fd_sc_hd__sdfxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfxbp.functional.v, line:37:1, endln:64:10 + \_module_inst: work@sky130_fd_sc_hd__sdfxbp (work@sky130_fd_sc_hd__sdfxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfxbp.functional.v, line:37:1, endln:64:10 |vpiTypespec: \_logic_typespec: , line:48:12, endln:48:12 |vpiName:Q_N @@ -3880,7 +3880,7 @@ design: (work@sky130_fd_sc_hd__sdfxbp) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__sdfxbp.CLK), line:40:5, endln:40:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfxbp (work@sky130_fd_sc_hd__sdfxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfxbp.functional.v, line:37:1, endln:64:10 + \_module_inst: work@sky130_fd_sc_hd__sdfxbp (work@sky130_fd_sc_hd__sdfxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfxbp.functional.v, line:37:1, endln:64:10 |vpiTypespec: \_logic_typespec: , line:49:12, endln:49:12 |vpiName:CLK @@ -3888,7 +3888,7 @@ design: (work@sky130_fd_sc_hd__sdfxbp) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__sdfxbp.D), line:41:5, endln:41:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfxbp (work@sky130_fd_sc_hd__sdfxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfxbp.functional.v, line:37:1, endln:64:10 + \_module_inst: work@sky130_fd_sc_hd__sdfxbp (work@sky130_fd_sc_hd__sdfxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfxbp.functional.v, line:37:1, endln:64:10 |vpiTypespec: \_logic_typespec: , line:50:12, endln:50:12 |vpiName:D @@ -3896,7 +3896,7 @@ design: (work@sky130_fd_sc_hd__sdfxbp) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__sdfxbp.SCD), line:42:5, endln:42:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfxbp (work@sky130_fd_sc_hd__sdfxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfxbp.functional.v, line:37:1, endln:64:10 + \_module_inst: work@sky130_fd_sc_hd__sdfxbp (work@sky130_fd_sc_hd__sdfxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfxbp.functional.v, line:37:1, endln:64:10 |vpiTypespec: \_logic_typespec: , line:51:12, endln:51:12 |vpiName:SCD @@ -3904,7 +3904,7 @@ design: (work@sky130_fd_sc_hd__sdfxbp) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__sdfxbp.SCE), line:43:5, endln:43:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfxbp (work@sky130_fd_sc_hd__sdfxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfxbp.functional.v, line:37:1, endln:64:10 + \_module_inst: work@sky130_fd_sc_hd__sdfxbp (work@sky130_fd_sc_hd__sdfxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfxbp.functional.v, line:37:1, endln:64:10 |vpiTypespec: \_logic_typespec: , line:52:12, endln:52:12 |vpiName:SCE @@ -3913,7 +3913,7 @@ design: (work@sky130_fd_sc_hd__sdfxbp) |vpiPort: \_port: (Q), line:38:5, endln:38:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfxbp (work@sky130_fd_sc_hd__sdfxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfxbp.functional.v, line:37:1, endln:64:10 + \_module_inst: work@sky130_fd_sc_hd__sdfxbp (work@sky130_fd_sc_hd__sdfxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfxbp.functional.v, line:37:1, endln:64:10 |vpiName:Q |vpiDirection:2 |vpiLowConn: @@ -3927,7 +3927,7 @@ design: (work@sky130_fd_sc_hd__sdfxbp) |vpiPort: \_port: (Q_N), line:39:5, endln:39:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfxbp (work@sky130_fd_sc_hd__sdfxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfxbp.functional.v, line:37:1, endln:64:10 + \_module_inst: work@sky130_fd_sc_hd__sdfxbp (work@sky130_fd_sc_hd__sdfxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfxbp.functional.v, line:37:1, endln:64:10 |vpiName:Q_N |vpiDirection:2 |vpiLowConn: @@ -3941,7 +3941,7 @@ design: (work@sky130_fd_sc_hd__sdfxbp) |vpiPort: \_port: (CLK), line:40:5, endln:40:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfxbp (work@sky130_fd_sc_hd__sdfxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfxbp.functional.v, line:37:1, endln:64:10 + \_module_inst: work@sky130_fd_sc_hd__sdfxbp (work@sky130_fd_sc_hd__sdfxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfxbp.functional.v, line:37:1, endln:64:10 |vpiName:CLK |vpiDirection:1 |vpiLowConn: @@ -3955,7 +3955,7 @@ design: (work@sky130_fd_sc_hd__sdfxbp) |vpiPort: \_port: (D), line:41:5, endln:41:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfxbp (work@sky130_fd_sc_hd__sdfxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfxbp.functional.v, line:37:1, endln:64:10 + \_module_inst: work@sky130_fd_sc_hd__sdfxbp (work@sky130_fd_sc_hd__sdfxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfxbp.functional.v, line:37:1, endln:64:10 |vpiName:D |vpiDirection:1 |vpiLowConn: @@ -3969,7 +3969,7 @@ design: (work@sky130_fd_sc_hd__sdfxbp) |vpiPort: \_port: (SCD), line:42:5, endln:42:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfxbp (work@sky130_fd_sc_hd__sdfxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfxbp.functional.v, line:37:1, endln:64:10 + \_module_inst: work@sky130_fd_sc_hd__sdfxbp (work@sky130_fd_sc_hd__sdfxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfxbp.functional.v, line:37:1, endln:64:10 |vpiName:SCD |vpiDirection:1 |vpiLowConn: @@ -3983,7 +3983,7 @@ design: (work@sky130_fd_sc_hd__sdfxbp) |vpiPort: \_port: (SCE), line:43:5, endln:43:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfxbp (work@sky130_fd_sc_hd__sdfxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfxbp.functional.v, line:37:1, endln:64:10 + \_module_inst: work@sky130_fd_sc_hd__sdfxbp (work@sky130_fd_sc_hd__sdfxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfxbp.functional.v, line:37:1, endln:64:10 |vpiName:SCE |vpiDirection:1 |vpiLowConn: @@ -3997,7 +3997,7 @@ design: (work@sky130_fd_sc_hd__sdfxbp) |vpiPrimitive: \_udp: work@sky130_fd_sc_hd__udp_mux_2to1 (work@sky130_fd_sc_hd__sdfxbp.mux_2to10), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfxbp.functional.v, line:59:5, endln:59:84 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfxbp (work@sky130_fd_sc_hd__sdfxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfxbp.functional.v, line:37:1, endln:64:10 + \_module_inst: work@sky130_fd_sc_hd__sdfxbp (work@sky130_fd_sc_hd__sdfxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfxbp.functional.v, line:37:1, endln:64:10 |vpiDefName:work@sky130_fd_sc_hd__udp_mux_2to1 |vpiName:mux_2to10 |vpiFullName:work@sky130_fd_sc_hd__sdfxbp.mux_2to10 @@ -4006,7 +4006,7 @@ design: (work@sky130_fd_sc_hd__sdfxbp) |vpiPrimitive: \_udp: work@sky130_fd_sc_hd__udp_dff$P (work@sky130_fd_sc_hd__sdfxbp.dff0), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfxbp.functional.v, line:60:5, endln:60:73 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfxbp (work@sky130_fd_sc_hd__sdfxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfxbp.functional.v, line:37:1, endln:64:10 + \_module_inst: work@sky130_fd_sc_hd__sdfxbp (work@sky130_fd_sc_hd__sdfxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfxbp.functional.v, line:37:1, endln:64:10 |vpiDefName:work@sky130_fd_sc_hd__udp_dff$P |vpiName:dff0 |vpiFullName:work@sky130_fd_sc_hd__sdfxbp.dff0 @@ -4015,7 +4015,7 @@ design: (work@sky130_fd_sc_hd__sdfxbp) |vpiPrimitive: \_gate: work@buf (work@sky130_fd_sc_hd__sdfxbp.buf0), line:61:47, endln:61:83 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfxbp (work@sky130_fd_sc_hd__sdfxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfxbp.functional.v, line:37:1, endln:64:10 + \_module_inst: work@sky130_fd_sc_hd__sdfxbp (work@sky130_fd_sc_hd__sdfxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfxbp.functional.v, line:37:1, endln:64:10 |vpiDefName:work@buf |vpiName:buf0 |vpiFullName:work@sky130_fd_sc_hd__sdfxbp.buf0 @@ -4050,7 +4050,7 @@ design: (work@sky130_fd_sc_hd__sdfxbp) |vpiPrimitive: \_gate: work@not (work@sky130_fd_sc_hd__sdfxbp.not0), line:62:47, endln:62:83 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfxbp (work@sky130_fd_sc_hd__sdfxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfxbp.functional.v, line:37:1, endln:64:10 + \_module_inst: work@sky130_fd_sc_hd__sdfxbp (work@sky130_fd_sc_hd__sdfxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfxbp.functional.v, line:37:1, endln:64:10 |vpiDefName:work@not |vpiName:not0 |vpiFullName:work@sky130_fd_sc_hd__sdfxbp.not0 @@ -4093,13 +4093,13 @@ Processing: -cd cells/cells -DUNIT_DELAY -writepp -parse -nocache -nobuiltin -no design: (work@sky130_fd_sc_hd__lpflow_decapkapwr) |vpiName:work@sky130_fd_sc_hd__lpflow_decapkapwr |uhdmallModules: -\_module: work@sky130_fd_sc_hd__lpflow_decapkapwr (work@sky130_fd_sc_hd__lpflow_decapkapwr), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_decapkapwr.functional.v, line:34:1, endln:36:10 +\_module_inst: work@sky130_fd_sc_hd__lpflow_decapkapwr (work@sky130_fd_sc_hd__lpflow_decapkapwr), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_decapkapwr.functional.v, line:34:1, endln:36:10 |vpiParent: \_design: (work@sky130_fd_sc_hd__lpflow_decapkapwr) |vpiFullName:work@sky130_fd_sc_hd__lpflow_decapkapwr |vpiDefName:work@sky130_fd_sc_hd__lpflow_decapkapwr |uhdmtopModules: -\_module: work@sky130_fd_sc_hd__lpflow_decapkapwr (work@sky130_fd_sc_hd__lpflow_decapkapwr), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_decapkapwr.functional.v, line:34:1, endln:36:10 +\_module_inst: work@sky130_fd_sc_hd__lpflow_decapkapwr (work@sky130_fd_sc_hd__lpflow_decapkapwr), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_decapkapwr.functional.v, line:34:1, endln:36:10 |vpiName:work@sky130_fd_sc_hd__lpflow_decapkapwr |vpiDefName:work@sky130_fd_sc_hd__lpflow_decapkapwr |vpiTop:1 @@ -4115,7 +4115,7 @@ Processing: -cd cells/cells -DUNIT_DELAY -writepp -parse -nocache -nobuiltin -no design: (work@sky130_fd_sc_hd__o41ai) |vpiName:work@sky130_fd_sc_hd__o41ai |uhdmallModules: -\_module: work@sky130_fd_sc_hd__o41ai (work@sky130_fd_sc_hd__o41ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o41ai.functional.v, line:35:1, endln:61:10 +\_module_inst: work@sky130_fd_sc_hd__o41ai (work@sky130_fd_sc_hd__o41ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o41ai.functional.v, line:35:1, endln:61:10 |vpiParent: \_design: (work@sky130_fd_sc_hd__o41ai) |vpiFullName:work@sky130_fd_sc_hd__o41ai @@ -4123,57 +4123,57 @@ design: (work@sky130_fd_sc_hd__o41ai) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o41ai.or0_out), line:53:10, endln:53:17 |vpiParent: - \_module: work@sky130_fd_sc_hd__o41ai (work@sky130_fd_sc_hd__o41ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o41ai.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o41ai (work@sky130_fd_sc_hd__o41ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o41ai.functional.v, line:35:1, endln:61:10 |vpiName:or0_out |vpiFullName:work@sky130_fd_sc_hd__o41ai.or0_out |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o41ai.nand0_out_Y), line:54:10, endln:54:21 |vpiParent: - \_module: work@sky130_fd_sc_hd__o41ai (work@sky130_fd_sc_hd__o41ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o41ai.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o41ai (work@sky130_fd_sc_hd__o41ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o41ai.functional.v, line:35:1, endln:61:10 |vpiName:nand0_out_Y |vpiFullName:work@sky130_fd_sc_hd__o41ai.nand0_out_Y |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o41ai.Y), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__o41ai (work@sky130_fd_sc_hd__o41ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o41ai.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o41ai (work@sky130_fd_sc_hd__o41ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o41ai.functional.v, line:35:1, endln:61:10 |vpiName:Y |vpiFullName:work@sky130_fd_sc_hd__o41ai.Y |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o41ai.A1), line:37:5, endln:37:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o41ai (work@sky130_fd_sc_hd__o41ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o41ai.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o41ai (work@sky130_fd_sc_hd__o41ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o41ai.functional.v, line:35:1, endln:61:10 |vpiName:A1 |vpiFullName:work@sky130_fd_sc_hd__o41ai.A1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o41ai.A2), line:38:5, endln:38:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o41ai (work@sky130_fd_sc_hd__o41ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o41ai.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o41ai (work@sky130_fd_sc_hd__o41ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o41ai.functional.v, line:35:1, endln:61:10 |vpiName:A2 |vpiFullName:work@sky130_fd_sc_hd__o41ai.A2 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o41ai.A3), line:39:5, endln:39:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o41ai (work@sky130_fd_sc_hd__o41ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o41ai.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o41ai (work@sky130_fd_sc_hd__o41ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o41ai.functional.v, line:35:1, endln:61:10 |vpiName:A3 |vpiFullName:work@sky130_fd_sc_hd__o41ai.A3 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o41ai.A4), line:40:5, endln:40:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o41ai (work@sky130_fd_sc_hd__o41ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o41ai.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o41ai (work@sky130_fd_sc_hd__o41ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o41ai.functional.v, line:35:1, endln:61:10 |vpiName:A4 |vpiFullName:work@sky130_fd_sc_hd__o41ai.A4 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o41ai.B1), line:41:5, endln:41:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o41ai (work@sky130_fd_sc_hd__o41ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o41ai.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o41ai (work@sky130_fd_sc_hd__o41ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o41ai.functional.v, line:35:1, endln:61:10 |vpiName:B1 |vpiFullName:work@sky130_fd_sc_hd__o41ai.B1 |vpiPort: \_port: (Y), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__o41ai (work@sky130_fd_sc_hd__o41ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o41ai.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o41ai (work@sky130_fd_sc_hd__o41ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o41ai.functional.v, line:35:1, endln:61:10 |vpiName:Y |vpiDirection:2 |vpiLowConn: @@ -4185,7 +4185,7 @@ design: (work@sky130_fd_sc_hd__o41ai) |vpiPort: \_port: (A1), line:37:5, endln:37:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o41ai (work@sky130_fd_sc_hd__o41ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o41ai.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o41ai (work@sky130_fd_sc_hd__o41ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o41ai.functional.v, line:35:1, endln:61:10 |vpiName:A1 |vpiDirection:1 |vpiLowConn: @@ -4197,7 +4197,7 @@ design: (work@sky130_fd_sc_hd__o41ai) |vpiPort: \_port: (A2), line:38:5, endln:38:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o41ai (work@sky130_fd_sc_hd__o41ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o41ai.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o41ai (work@sky130_fd_sc_hd__o41ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o41ai.functional.v, line:35:1, endln:61:10 |vpiName:A2 |vpiDirection:1 |vpiLowConn: @@ -4209,7 +4209,7 @@ design: (work@sky130_fd_sc_hd__o41ai) |vpiPort: \_port: (A3), line:39:5, endln:39:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o41ai (work@sky130_fd_sc_hd__o41ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o41ai.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o41ai (work@sky130_fd_sc_hd__o41ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o41ai.functional.v, line:35:1, endln:61:10 |vpiName:A3 |vpiDirection:1 |vpiLowConn: @@ -4221,7 +4221,7 @@ design: (work@sky130_fd_sc_hd__o41ai) |vpiPort: \_port: (A4), line:40:5, endln:40:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o41ai (work@sky130_fd_sc_hd__o41ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o41ai.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o41ai (work@sky130_fd_sc_hd__o41ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o41ai.functional.v, line:35:1, endln:61:10 |vpiName:A4 |vpiDirection:1 |vpiLowConn: @@ -4233,7 +4233,7 @@ design: (work@sky130_fd_sc_hd__o41ai) |vpiPort: \_port: (B1), line:41:5, endln:41:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o41ai (work@sky130_fd_sc_hd__o41ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o41ai.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o41ai (work@sky130_fd_sc_hd__o41ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o41ai.functional.v, line:35:1, endln:61:10 |vpiName:B1 |vpiDirection:1 |vpiLowConn: @@ -4243,14 +4243,14 @@ design: (work@sky130_fd_sc_hd__o41ai) |vpiTypedef: \_logic_typespec: , line:50:12, endln:50:12 |uhdmtopModules: -\_module: work@sky130_fd_sc_hd__o41ai (work@sky130_fd_sc_hd__o41ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o41ai.functional.v, line:35:1, endln:61:10 +\_module_inst: work@sky130_fd_sc_hd__o41ai (work@sky130_fd_sc_hd__o41ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o41ai.functional.v, line:35:1, endln:61:10 |vpiName:work@sky130_fd_sc_hd__o41ai |vpiDefName:work@sky130_fd_sc_hd__o41ai |vpiTop:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o41ai.or0_out), line:53:10, endln:53:17 |vpiParent: - \_module: work@sky130_fd_sc_hd__o41ai (work@sky130_fd_sc_hd__o41ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o41ai.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o41ai (work@sky130_fd_sc_hd__o41ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o41ai.functional.v, line:35:1, endln:61:10 |vpiTypespec: \_logic_typespec: , line:53:5, endln:53:9 |vpiName:or0_out @@ -4259,7 +4259,7 @@ design: (work@sky130_fd_sc_hd__o41ai) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o41ai.nand0_out_Y), line:54:10, endln:54:21 |vpiParent: - \_module: work@sky130_fd_sc_hd__o41ai (work@sky130_fd_sc_hd__o41ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o41ai.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o41ai (work@sky130_fd_sc_hd__o41ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o41ai.functional.v, line:35:1, endln:61:10 |vpiTypespec: \_logic_typespec: , line:54:5, endln:54:9 |vpiName:nand0_out_Y @@ -4268,7 +4268,7 @@ design: (work@sky130_fd_sc_hd__o41ai) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o41ai.Y), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__o41ai (work@sky130_fd_sc_hd__o41ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o41ai.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o41ai (work@sky130_fd_sc_hd__o41ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o41ai.functional.v, line:35:1, endln:61:10 |vpiTypespec: \_logic_typespec: , line:45:12, endln:45:12 |vpiName:Y @@ -4276,7 +4276,7 @@ design: (work@sky130_fd_sc_hd__o41ai) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o41ai.A1), line:37:5, endln:37:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o41ai (work@sky130_fd_sc_hd__o41ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o41ai.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o41ai (work@sky130_fd_sc_hd__o41ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o41ai.functional.v, line:35:1, endln:61:10 |vpiTypespec: \_logic_typespec: , line:46:12, endln:46:12 |vpiName:A1 @@ -4284,7 +4284,7 @@ design: (work@sky130_fd_sc_hd__o41ai) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o41ai.A2), line:38:5, endln:38:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o41ai (work@sky130_fd_sc_hd__o41ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o41ai.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o41ai (work@sky130_fd_sc_hd__o41ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o41ai.functional.v, line:35:1, endln:61:10 |vpiTypespec: \_logic_typespec: , line:47:12, endln:47:12 |vpiName:A2 @@ -4292,7 +4292,7 @@ design: (work@sky130_fd_sc_hd__o41ai) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o41ai.A3), line:39:5, endln:39:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o41ai (work@sky130_fd_sc_hd__o41ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o41ai.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o41ai (work@sky130_fd_sc_hd__o41ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o41ai.functional.v, line:35:1, endln:61:10 |vpiTypespec: \_logic_typespec: , line:48:12, endln:48:12 |vpiName:A3 @@ -4300,7 +4300,7 @@ design: (work@sky130_fd_sc_hd__o41ai) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o41ai.A4), line:40:5, endln:40:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o41ai (work@sky130_fd_sc_hd__o41ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o41ai.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o41ai (work@sky130_fd_sc_hd__o41ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o41ai.functional.v, line:35:1, endln:61:10 |vpiTypespec: \_logic_typespec: , line:49:12, endln:49:12 |vpiName:A4 @@ -4308,7 +4308,7 @@ design: (work@sky130_fd_sc_hd__o41ai) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o41ai.B1), line:41:5, endln:41:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o41ai (work@sky130_fd_sc_hd__o41ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o41ai.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o41ai (work@sky130_fd_sc_hd__o41ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o41ai.functional.v, line:35:1, endln:61:10 |vpiTypespec: \_logic_typespec: , line:50:12, endln:50:12 |vpiName:B1 @@ -4317,7 +4317,7 @@ design: (work@sky130_fd_sc_hd__o41ai) |vpiPort: \_port: (Y), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__o41ai (work@sky130_fd_sc_hd__o41ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o41ai.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o41ai (work@sky130_fd_sc_hd__o41ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o41ai.functional.v, line:35:1, endln:61:10 |vpiName:Y |vpiDirection:2 |vpiLowConn: @@ -4331,7 +4331,7 @@ design: (work@sky130_fd_sc_hd__o41ai) |vpiPort: \_port: (A1), line:37:5, endln:37:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o41ai (work@sky130_fd_sc_hd__o41ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o41ai.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o41ai (work@sky130_fd_sc_hd__o41ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o41ai.functional.v, line:35:1, endln:61:10 |vpiName:A1 |vpiDirection:1 |vpiLowConn: @@ -4345,7 +4345,7 @@ design: (work@sky130_fd_sc_hd__o41ai) |vpiPort: \_port: (A2), line:38:5, endln:38:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o41ai (work@sky130_fd_sc_hd__o41ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o41ai.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o41ai (work@sky130_fd_sc_hd__o41ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o41ai.functional.v, line:35:1, endln:61:10 |vpiName:A2 |vpiDirection:1 |vpiLowConn: @@ -4359,7 +4359,7 @@ design: (work@sky130_fd_sc_hd__o41ai) |vpiPort: \_port: (A3), line:39:5, endln:39:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o41ai (work@sky130_fd_sc_hd__o41ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o41ai.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o41ai (work@sky130_fd_sc_hd__o41ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o41ai.functional.v, line:35:1, endln:61:10 |vpiName:A3 |vpiDirection:1 |vpiLowConn: @@ -4373,7 +4373,7 @@ design: (work@sky130_fd_sc_hd__o41ai) |vpiPort: \_port: (A4), line:40:5, endln:40:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o41ai (work@sky130_fd_sc_hd__o41ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o41ai.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o41ai (work@sky130_fd_sc_hd__o41ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o41ai.functional.v, line:35:1, endln:61:10 |vpiName:A4 |vpiDirection:1 |vpiLowConn: @@ -4387,7 +4387,7 @@ design: (work@sky130_fd_sc_hd__o41ai) |vpiPort: \_port: (B1), line:41:5, endln:41:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o41ai (work@sky130_fd_sc_hd__o41ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o41ai.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o41ai (work@sky130_fd_sc_hd__o41ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o41ai.functional.v, line:35:1, endln:61:10 |vpiName:B1 |vpiDirection:1 |vpiLowConn: @@ -4401,7 +4401,7 @@ design: (work@sky130_fd_sc_hd__o41ai) |vpiPrimitive: \_gate: work@or (work@sky130_fd_sc_hd__o41ai.or0), line:57:10, endln:57:46 |vpiParent: - \_module: work@sky130_fd_sc_hd__o41ai (work@sky130_fd_sc_hd__o41ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o41ai.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o41ai (work@sky130_fd_sc_hd__o41ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o41ai.functional.v, line:35:1, endln:61:10 |vpiDefName:work@or |vpiName:or0 |vpiFullName:work@sky130_fd_sc_hd__o41ai.or0 @@ -4478,7 +4478,7 @@ design: (work@sky130_fd_sc_hd__o41ai) |vpiPrimitive: \_gate: work@nand (work@sky130_fd_sc_hd__o41ai.nand0), line:58:10, endln:58:46 |vpiParent: - \_module: work@sky130_fd_sc_hd__o41ai (work@sky130_fd_sc_hd__o41ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o41ai.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o41ai (work@sky130_fd_sc_hd__o41ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o41ai.functional.v, line:35:1, endln:61:10 |vpiDefName:work@nand |vpiName:nand0 |vpiFullName:work@sky130_fd_sc_hd__o41ai.nand0 @@ -4527,7 +4527,7 @@ design: (work@sky130_fd_sc_hd__o41ai) |vpiPrimitive: \_gate: work@buf (work@sky130_fd_sc_hd__o41ai.buf0), line:59:10, endln:59:46 |vpiParent: - \_module: work@sky130_fd_sc_hd__o41ai (work@sky130_fd_sc_hd__o41ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o41ai.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o41ai (work@sky130_fd_sc_hd__o41ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o41ai.functional.v, line:35:1, endln:61:10 |vpiDefName:work@buf |vpiName:buf0 |vpiFullName:work@sky130_fd_sc_hd__o41ai.buf0 @@ -4570,7 +4570,7 @@ Processing: -cd cells/cells -DUNIT_DELAY -writepp -parse -nocache -nobuiltin -no design: (work@sky130_fd_sc_hd__clkdlybuf4s15) |vpiName:work@sky130_fd_sc_hd__clkdlybuf4s15 |uhdmallModules: -\_module: work@sky130_fd_sc_hd__clkdlybuf4s15 (work@sky130_fd_sc_hd__clkdlybuf4s15), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__clkdlybuf4s15.functional.v, line:34:1, endln:50:10 +\_module_inst: work@sky130_fd_sc_hd__clkdlybuf4s15 (work@sky130_fd_sc_hd__clkdlybuf4s15), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__clkdlybuf4s15.functional.v, line:34:1, endln:50:10 |vpiParent: \_design: (work@sky130_fd_sc_hd__clkdlybuf4s15) |vpiFullName:work@sky130_fd_sc_hd__clkdlybuf4s15 @@ -4578,26 +4578,26 @@ design: (work@sky130_fd_sc_hd__clkdlybuf4s15) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__clkdlybuf4s15.buf0_out_X), line:44:10, endln:44:20 |vpiParent: - \_module: work@sky130_fd_sc_hd__clkdlybuf4s15 (work@sky130_fd_sc_hd__clkdlybuf4s15), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__clkdlybuf4s15.functional.v, line:34:1, endln:50:10 + \_module_inst: work@sky130_fd_sc_hd__clkdlybuf4s15 (work@sky130_fd_sc_hd__clkdlybuf4s15), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__clkdlybuf4s15.functional.v, line:34:1, endln:50:10 |vpiName:buf0_out_X |vpiFullName:work@sky130_fd_sc_hd__clkdlybuf4s15.buf0_out_X |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__clkdlybuf4s15.X), line:35:5, endln:35:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__clkdlybuf4s15 (work@sky130_fd_sc_hd__clkdlybuf4s15), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__clkdlybuf4s15.functional.v, line:34:1, endln:50:10 + \_module_inst: work@sky130_fd_sc_hd__clkdlybuf4s15 (work@sky130_fd_sc_hd__clkdlybuf4s15), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__clkdlybuf4s15.functional.v, line:34:1, endln:50:10 |vpiName:X |vpiFullName:work@sky130_fd_sc_hd__clkdlybuf4s15.X |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__clkdlybuf4s15.A), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__clkdlybuf4s15 (work@sky130_fd_sc_hd__clkdlybuf4s15), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__clkdlybuf4s15.functional.v, line:34:1, endln:50:10 + \_module_inst: work@sky130_fd_sc_hd__clkdlybuf4s15 (work@sky130_fd_sc_hd__clkdlybuf4s15), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__clkdlybuf4s15.functional.v, line:34:1, endln:50:10 |vpiName:A |vpiFullName:work@sky130_fd_sc_hd__clkdlybuf4s15.A |vpiPort: \_port: (X), line:35:5, endln:35:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__clkdlybuf4s15 (work@sky130_fd_sc_hd__clkdlybuf4s15), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__clkdlybuf4s15.functional.v, line:34:1, endln:50:10 + \_module_inst: work@sky130_fd_sc_hd__clkdlybuf4s15 (work@sky130_fd_sc_hd__clkdlybuf4s15), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__clkdlybuf4s15.functional.v, line:34:1, endln:50:10 |vpiName:X |vpiDirection:2 |vpiLowConn: @@ -4609,7 +4609,7 @@ design: (work@sky130_fd_sc_hd__clkdlybuf4s15) |vpiPort: \_port: (A), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__clkdlybuf4s15 (work@sky130_fd_sc_hd__clkdlybuf4s15), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__clkdlybuf4s15.functional.v, line:34:1, endln:50:10 + \_module_inst: work@sky130_fd_sc_hd__clkdlybuf4s15 (work@sky130_fd_sc_hd__clkdlybuf4s15), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__clkdlybuf4s15.functional.v, line:34:1, endln:50:10 |vpiName:A |vpiDirection:1 |vpiLowConn: @@ -4619,14 +4619,14 @@ design: (work@sky130_fd_sc_hd__clkdlybuf4s15) |vpiTypedef: \_logic_typespec: , line:41:12, endln:41:12 |uhdmtopModules: -\_module: work@sky130_fd_sc_hd__clkdlybuf4s15 (work@sky130_fd_sc_hd__clkdlybuf4s15), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__clkdlybuf4s15.functional.v, line:34:1, endln:50:10 +\_module_inst: work@sky130_fd_sc_hd__clkdlybuf4s15 (work@sky130_fd_sc_hd__clkdlybuf4s15), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__clkdlybuf4s15.functional.v, line:34:1, endln:50:10 |vpiName:work@sky130_fd_sc_hd__clkdlybuf4s15 |vpiDefName:work@sky130_fd_sc_hd__clkdlybuf4s15 |vpiTop:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__clkdlybuf4s15.buf0_out_X), line:44:10, endln:44:20 |vpiParent: - \_module: work@sky130_fd_sc_hd__clkdlybuf4s15 (work@sky130_fd_sc_hd__clkdlybuf4s15), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__clkdlybuf4s15.functional.v, line:34:1, endln:50:10 + \_module_inst: work@sky130_fd_sc_hd__clkdlybuf4s15 (work@sky130_fd_sc_hd__clkdlybuf4s15), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__clkdlybuf4s15.functional.v, line:34:1, endln:50:10 |vpiTypespec: \_logic_typespec: , line:44:5, endln:44:9 |vpiName:buf0_out_X @@ -4635,7 +4635,7 @@ design: (work@sky130_fd_sc_hd__clkdlybuf4s15) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__clkdlybuf4s15.X), line:35:5, endln:35:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__clkdlybuf4s15 (work@sky130_fd_sc_hd__clkdlybuf4s15), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__clkdlybuf4s15.functional.v, line:34:1, endln:50:10 + \_module_inst: work@sky130_fd_sc_hd__clkdlybuf4s15 (work@sky130_fd_sc_hd__clkdlybuf4s15), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__clkdlybuf4s15.functional.v, line:34:1, endln:50:10 |vpiTypespec: \_logic_typespec: , line:40:12, endln:40:12 |vpiName:X @@ -4643,7 +4643,7 @@ design: (work@sky130_fd_sc_hd__clkdlybuf4s15) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__clkdlybuf4s15.A), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__clkdlybuf4s15 (work@sky130_fd_sc_hd__clkdlybuf4s15), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__clkdlybuf4s15.functional.v, line:34:1, endln:50:10 + \_module_inst: work@sky130_fd_sc_hd__clkdlybuf4s15 (work@sky130_fd_sc_hd__clkdlybuf4s15), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__clkdlybuf4s15.functional.v, line:34:1, endln:50:10 |vpiTypespec: \_logic_typespec: , line:41:12, endln:41:12 |vpiName:A @@ -4652,7 +4652,7 @@ design: (work@sky130_fd_sc_hd__clkdlybuf4s15) |vpiPort: \_port: (X), line:35:5, endln:35:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__clkdlybuf4s15 (work@sky130_fd_sc_hd__clkdlybuf4s15), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__clkdlybuf4s15.functional.v, line:34:1, endln:50:10 + \_module_inst: work@sky130_fd_sc_hd__clkdlybuf4s15 (work@sky130_fd_sc_hd__clkdlybuf4s15), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__clkdlybuf4s15.functional.v, line:34:1, endln:50:10 |vpiName:X |vpiDirection:2 |vpiLowConn: @@ -4666,7 +4666,7 @@ design: (work@sky130_fd_sc_hd__clkdlybuf4s15) |vpiPort: \_port: (A), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__clkdlybuf4s15 (work@sky130_fd_sc_hd__clkdlybuf4s15), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__clkdlybuf4s15.functional.v, line:34:1, endln:50:10 + \_module_inst: work@sky130_fd_sc_hd__clkdlybuf4s15 (work@sky130_fd_sc_hd__clkdlybuf4s15), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__clkdlybuf4s15.functional.v, line:34:1, endln:50:10 |vpiName:A |vpiDirection:1 |vpiLowConn: @@ -4680,7 +4680,7 @@ design: (work@sky130_fd_sc_hd__clkdlybuf4s15) |vpiPrimitive: \_gate: work@buf (work@sky130_fd_sc_hd__clkdlybuf4s15.buf0), line:47:9, endln:47:43 |vpiParent: - \_module: work@sky130_fd_sc_hd__clkdlybuf4s15 (work@sky130_fd_sc_hd__clkdlybuf4s15), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__clkdlybuf4s15.functional.v, line:34:1, endln:50:10 + \_module_inst: work@sky130_fd_sc_hd__clkdlybuf4s15 (work@sky130_fd_sc_hd__clkdlybuf4s15), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__clkdlybuf4s15.functional.v, line:34:1, endln:50:10 |vpiDefName:work@buf |vpiName:buf0 |vpiFullName:work@sky130_fd_sc_hd__clkdlybuf4s15.buf0 @@ -4715,7 +4715,7 @@ design: (work@sky130_fd_sc_hd__clkdlybuf4s15) |vpiPrimitive: \_gate: work@buf (work@sky130_fd_sc_hd__clkdlybuf4s15.buf1), line:48:9, endln:48:43 |vpiParent: - \_module: work@sky130_fd_sc_hd__clkdlybuf4s15 (work@sky130_fd_sc_hd__clkdlybuf4s15), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__clkdlybuf4s15.functional.v, line:34:1, endln:50:10 + \_module_inst: work@sky130_fd_sc_hd__clkdlybuf4s15 (work@sky130_fd_sc_hd__clkdlybuf4s15), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__clkdlybuf4s15.functional.v, line:34:1, endln:50:10 |vpiDefName:work@buf |vpiName:buf1 |vpiFullName:work@sky130_fd_sc_hd__clkdlybuf4s15.buf1 @@ -4948,7 +4948,7 @@ design: (work@sky130_fd_sc_hd__sedfxtp) |vpiSize:3 |STRING:? 1 1 : 1 |uhdmallModules: -\_module: work@sky130_fd_sc_hd__sedfxtp (work@sky130_fd_sc_hd__sedfxtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sedfxtp.functional.v, line:38:1, endln:66:10 +\_module_inst: work@sky130_fd_sc_hd__sedfxtp (work@sky130_fd_sc_hd__sedfxtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sedfxtp.functional.v, line:38:1, endln:66:10 |vpiParent: \_design: (work@sky130_fd_sc_hd__sedfxtp) |vpiFullName:work@sky130_fd_sc_hd__sedfxtp @@ -4956,64 +4956,64 @@ design: (work@sky130_fd_sc_hd__sedfxtp) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__sedfxtp.buf_Q), line:56:10, endln:56:15 |vpiParent: - \_module: work@sky130_fd_sc_hd__sedfxtp (work@sky130_fd_sc_hd__sedfxtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sedfxtp.functional.v, line:38:1, endln:66:10 + \_module_inst: work@sky130_fd_sc_hd__sedfxtp (work@sky130_fd_sc_hd__sedfxtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sedfxtp.functional.v, line:38:1, endln:66:10 |vpiName:buf_Q |vpiFullName:work@sky130_fd_sc_hd__sedfxtp.buf_Q |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__sedfxtp.mux_out), line:57:10, endln:57:17 |vpiParent: - \_module: work@sky130_fd_sc_hd__sedfxtp (work@sky130_fd_sc_hd__sedfxtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sedfxtp.functional.v, line:38:1, endln:66:10 + \_module_inst: work@sky130_fd_sc_hd__sedfxtp (work@sky130_fd_sc_hd__sedfxtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sedfxtp.functional.v, line:38:1, endln:66:10 |vpiName:mux_out |vpiFullName:work@sky130_fd_sc_hd__sedfxtp.mux_out |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__sedfxtp.de_d), line:58:10, endln:58:14 |vpiParent: - \_module: work@sky130_fd_sc_hd__sedfxtp (work@sky130_fd_sc_hd__sedfxtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sedfxtp.functional.v, line:38:1, endln:66:10 + \_module_inst: work@sky130_fd_sc_hd__sedfxtp (work@sky130_fd_sc_hd__sedfxtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sedfxtp.functional.v, line:38:1, endln:66:10 |vpiName:de_d |vpiFullName:work@sky130_fd_sc_hd__sedfxtp.de_d |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__sedfxtp.Q), line:39:5, endln:39:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__sedfxtp (work@sky130_fd_sc_hd__sedfxtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sedfxtp.functional.v, line:38:1, endln:66:10 + \_module_inst: work@sky130_fd_sc_hd__sedfxtp (work@sky130_fd_sc_hd__sedfxtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sedfxtp.functional.v, line:38:1, endln:66:10 |vpiName:Q |vpiFullName:work@sky130_fd_sc_hd__sedfxtp.Q |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__sedfxtp.CLK), line:40:5, endln:40:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__sedfxtp (work@sky130_fd_sc_hd__sedfxtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sedfxtp.functional.v, line:38:1, endln:66:10 + \_module_inst: work@sky130_fd_sc_hd__sedfxtp (work@sky130_fd_sc_hd__sedfxtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sedfxtp.functional.v, line:38:1, endln:66:10 |vpiName:CLK |vpiFullName:work@sky130_fd_sc_hd__sedfxtp.CLK |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__sedfxtp.D), line:41:5, endln:41:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__sedfxtp (work@sky130_fd_sc_hd__sedfxtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sedfxtp.functional.v, line:38:1, endln:66:10 + \_module_inst: work@sky130_fd_sc_hd__sedfxtp (work@sky130_fd_sc_hd__sedfxtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sedfxtp.functional.v, line:38:1, endln:66:10 |vpiName:D |vpiFullName:work@sky130_fd_sc_hd__sedfxtp.D |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__sedfxtp.DE), line:42:5, endln:42:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__sedfxtp (work@sky130_fd_sc_hd__sedfxtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sedfxtp.functional.v, line:38:1, endln:66:10 + \_module_inst: work@sky130_fd_sc_hd__sedfxtp (work@sky130_fd_sc_hd__sedfxtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sedfxtp.functional.v, line:38:1, endln:66:10 |vpiName:DE |vpiFullName:work@sky130_fd_sc_hd__sedfxtp.DE |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__sedfxtp.SCD), line:43:5, endln:43:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__sedfxtp (work@sky130_fd_sc_hd__sedfxtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sedfxtp.functional.v, line:38:1, endln:66:10 + \_module_inst: work@sky130_fd_sc_hd__sedfxtp (work@sky130_fd_sc_hd__sedfxtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sedfxtp.functional.v, line:38:1, endln:66:10 |vpiName:SCD |vpiFullName:work@sky130_fd_sc_hd__sedfxtp.SCD |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__sedfxtp.SCE), line:44:5, endln:44:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__sedfxtp (work@sky130_fd_sc_hd__sedfxtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sedfxtp.functional.v, line:38:1, endln:66:10 + \_module_inst: work@sky130_fd_sc_hd__sedfxtp (work@sky130_fd_sc_hd__sedfxtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sedfxtp.functional.v, line:38:1, endln:66:10 |vpiName:SCE |vpiFullName:work@sky130_fd_sc_hd__sedfxtp.SCE |vpiPort: \_port: (Q), line:39:5, endln:39:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__sedfxtp (work@sky130_fd_sc_hd__sedfxtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sedfxtp.functional.v, line:38:1, endln:66:10 + \_module_inst: work@sky130_fd_sc_hd__sedfxtp (work@sky130_fd_sc_hd__sedfxtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sedfxtp.functional.v, line:38:1, endln:66:10 |vpiName:Q |vpiDirection:2 |vpiLowConn: @@ -5025,7 +5025,7 @@ design: (work@sky130_fd_sc_hd__sedfxtp) |vpiPort: \_port: (CLK), line:40:5, endln:40:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__sedfxtp (work@sky130_fd_sc_hd__sedfxtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sedfxtp.functional.v, line:38:1, endln:66:10 + \_module_inst: work@sky130_fd_sc_hd__sedfxtp (work@sky130_fd_sc_hd__sedfxtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sedfxtp.functional.v, line:38:1, endln:66:10 |vpiName:CLK |vpiDirection:1 |vpiLowConn: @@ -5037,7 +5037,7 @@ design: (work@sky130_fd_sc_hd__sedfxtp) |vpiPort: \_port: (D), line:41:5, endln:41:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__sedfxtp (work@sky130_fd_sc_hd__sedfxtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sedfxtp.functional.v, line:38:1, endln:66:10 + \_module_inst: work@sky130_fd_sc_hd__sedfxtp (work@sky130_fd_sc_hd__sedfxtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sedfxtp.functional.v, line:38:1, endln:66:10 |vpiName:D |vpiDirection:1 |vpiLowConn: @@ -5049,7 +5049,7 @@ design: (work@sky130_fd_sc_hd__sedfxtp) |vpiPort: \_port: (DE), line:42:5, endln:42:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__sedfxtp (work@sky130_fd_sc_hd__sedfxtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sedfxtp.functional.v, line:38:1, endln:66:10 + \_module_inst: work@sky130_fd_sc_hd__sedfxtp (work@sky130_fd_sc_hd__sedfxtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sedfxtp.functional.v, line:38:1, endln:66:10 |vpiName:DE |vpiDirection:1 |vpiLowConn: @@ -5061,7 +5061,7 @@ design: (work@sky130_fd_sc_hd__sedfxtp) |vpiPort: \_port: (SCD), line:43:5, endln:43:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__sedfxtp (work@sky130_fd_sc_hd__sedfxtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sedfxtp.functional.v, line:38:1, endln:66:10 + \_module_inst: work@sky130_fd_sc_hd__sedfxtp (work@sky130_fd_sc_hd__sedfxtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sedfxtp.functional.v, line:38:1, endln:66:10 |vpiName:SCD |vpiDirection:1 |vpiLowConn: @@ -5073,7 +5073,7 @@ design: (work@sky130_fd_sc_hd__sedfxtp) |vpiPort: \_port: (SCE), line:44:5, endln:44:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__sedfxtp (work@sky130_fd_sc_hd__sedfxtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sedfxtp.functional.v, line:38:1, endln:66:10 + \_module_inst: work@sky130_fd_sc_hd__sedfxtp (work@sky130_fd_sc_hd__sedfxtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sedfxtp.functional.v, line:38:1, endln:66:10 |vpiName:SCE |vpiDirection:1 |vpiLowConn: @@ -5083,14 +5083,14 @@ design: (work@sky130_fd_sc_hd__sedfxtp) |vpiTypedef: \_logic_typespec: , line:53:12, endln:53:12 |uhdmtopModules: -\_module: work@sky130_fd_sc_hd__sedfxtp (work@sky130_fd_sc_hd__sedfxtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sedfxtp.functional.v, line:38:1, endln:66:10 +\_module_inst: work@sky130_fd_sc_hd__sedfxtp (work@sky130_fd_sc_hd__sedfxtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sedfxtp.functional.v, line:38:1, endln:66:10 |vpiName:work@sky130_fd_sc_hd__sedfxtp |vpiDefName:work@sky130_fd_sc_hd__sedfxtp |vpiTop:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__sedfxtp.buf_Q), line:56:10, endln:56:15 |vpiParent: - \_module: work@sky130_fd_sc_hd__sedfxtp (work@sky130_fd_sc_hd__sedfxtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sedfxtp.functional.v, line:38:1, endln:66:10 + \_module_inst: work@sky130_fd_sc_hd__sedfxtp (work@sky130_fd_sc_hd__sedfxtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sedfxtp.functional.v, line:38:1, endln:66:10 |vpiTypespec: \_logic_typespec: , line:56:5, endln:56:9 |vpiName:buf_Q @@ -5099,7 +5099,7 @@ design: (work@sky130_fd_sc_hd__sedfxtp) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__sedfxtp.mux_out), line:57:10, endln:57:17 |vpiParent: - \_module: work@sky130_fd_sc_hd__sedfxtp (work@sky130_fd_sc_hd__sedfxtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sedfxtp.functional.v, line:38:1, endln:66:10 + \_module_inst: work@sky130_fd_sc_hd__sedfxtp (work@sky130_fd_sc_hd__sedfxtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sedfxtp.functional.v, line:38:1, endln:66:10 |vpiTypespec: \_logic_typespec: , line:57:5, endln:57:9 |vpiName:mux_out @@ -5108,7 +5108,7 @@ design: (work@sky130_fd_sc_hd__sedfxtp) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__sedfxtp.de_d), line:58:10, endln:58:14 |vpiParent: - \_module: work@sky130_fd_sc_hd__sedfxtp (work@sky130_fd_sc_hd__sedfxtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sedfxtp.functional.v, line:38:1, endln:66:10 + \_module_inst: work@sky130_fd_sc_hd__sedfxtp (work@sky130_fd_sc_hd__sedfxtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sedfxtp.functional.v, line:38:1, endln:66:10 |vpiTypespec: \_logic_typespec: , line:58:5, endln:58:9 |vpiName:de_d @@ -5117,7 +5117,7 @@ design: (work@sky130_fd_sc_hd__sedfxtp) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__sedfxtp.Q), line:39:5, endln:39:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__sedfxtp (work@sky130_fd_sc_hd__sedfxtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sedfxtp.functional.v, line:38:1, endln:66:10 + \_module_inst: work@sky130_fd_sc_hd__sedfxtp (work@sky130_fd_sc_hd__sedfxtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sedfxtp.functional.v, line:38:1, endln:66:10 |vpiTypespec: \_logic_typespec: , line:48:12, endln:48:12 |vpiName:Q @@ -5125,7 +5125,7 @@ design: (work@sky130_fd_sc_hd__sedfxtp) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__sedfxtp.CLK), line:40:5, endln:40:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__sedfxtp (work@sky130_fd_sc_hd__sedfxtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sedfxtp.functional.v, line:38:1, endln:66:10 + \_module_inst: work@sky130_fd_sc_hd__sedfxtp (work@sky130_fd_sc_hd__sedfxtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sedfxtp.functional.v, line:38:1, endln:66:10 |vpiTypespec: \_logic_typespec: , line:49:12, endln:49:12 |vpiName:CLK @@ -5133,7 +5133,7 @@ design: (work@sky130_fd_sc_hd__sedfxtp) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__sedfxtp.D), line:41:5, endln:41:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__sedfxtp (work@sky130_fd_sc_hd__sedfxtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sedfxtp.functional.v, line:38:1, endln:66:10 + \_module_inst: work@sky130_fd_sc_hd__sedfxtp (work@sky130_fd_sc_hd__sedfxtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sedfxtp.functional.v, line:38:1, endln:66:10 |vpiTypespec: \_logic_typespec: , line:50:12, endln:50:12 |vpiName:D @@ -5141,7 +5141,7 @@ design: (work@sky130_fd_sc_hd__sedfxtp) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__sedfxtp.DE), line:42:5, endln:42:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__sedfxtp (work@sky130_fd_sc_hd__sedfxtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sedfxtp.functional.v, line:38:1, endln:66:10 + \_module_inst: work@sky130_fd_sc_hd__sedfxtp (work@sky130_fd_sc_hd__sedfxtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sedfxtp.functional.v, line:38:1, endln:66:10 |vpiTypespec: \_logic_typespec: , line:51:12, endln:51:12 |vpiName:DE @@ -5149,7 +5149,7 @@ design: (work@sky130_fd_sc_hd__sedfxtp) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__sedfxtp.SCD), line:43:5, endln:43:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__sedfxtp (work@sky130_fd_sc_hd__sedfxtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sedfxtp.functional.v, line:38:1, endln:66:10 + \_module_inst: work@sky130_fd_sc_hd__sedfxtp (work@sky130_fd_sc_hd__sedfxtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sedfxtp.functional.v, line:38:1, endln:66:10 |vpiTypespec: \_logic_typespec: , line:52:12, endln:52:12 |vpiName:SCD @@ -5157,7 +5157,7 @@ design: (work@sky130_fd_sc_hd__sedfxtp) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__sedfxtp.SCE), line:44:5, endln:44:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__sedfxtp (work@sky130_fd_sc_hd__sedfxtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sedfxtp.functional.v, line:38:1, endln:66:10 + \_module_inst: work@sky130_fd_sc_hd__sedfxtp (work@sky130_fd_sc_hd__sedfxtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sedfxtp.functional.v, line:38:1, endln:66:10 |vpiTypespec: \_logic_typespec: , line:53:12, endln:53:12 |vpiName:SCE @@ -5166,7 +5166,7 @@ design: (work@sky130_fd_sc_hd__sedfxtp) |vpiPort: \_port: (Q), line:39:5, endln:39:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__sedfxtp (work@sky130_fd_sc_hd__sedfxtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sedfxtp.functional.v, line:38:1, endln:66:10 + \_module_inst: work@sky130_fd_sc_hd__sedfxtp (work@sky130_fd_sc_hd__sedfxtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sedfxtp.functional.v, line:38:1, endln:66:10 |vpiName:Q |vpiDirection:2 |vpiLowConn: @@ -5180,7 +5180,7 @@ design: (work@sky130_fd_sc_hd__sedfxtp) |vpiPort: \_port: (CLK), line:40:5, endln:40:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__sedfxtp (work@sky130_fd_sc_hd__sedfxtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sedfxtp.functional.v, line:38:1, endln:66:10 + \_module_inst: work@sky130_fd_sc_hd__sedfxtp (work@sky130_fd_sc_hd__sedfxtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sedfxtp.functional.v, line:38:1, endln:66:10 |vpiName:CLK |vpiDirection:1 |vpiLowConn: @@ -5194,7 +5194,7 @@ design: (work@sky130_fd_sc_hd__sedfxtp) |vpiPort: \_port: (D), line:41:5, endln:41:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__sedfxtp (work@sky130_fd_sc_hd__sedfxtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sedfxtp.functional.v, line:38:1, endln:66:10 + \_module_inst: work@sky130_fd_sc_hd__sedfxtp (work@sky130_fd_sc_hd__sedfxtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sedfxtp.functional.v, line:38:1, endln:66:10 |vpiName:D |vpiDirection:1 |vpiLowConn: @@ -5208,7 +5208,7 @@ design: (work@sky130_fd_sc_hd__sedfxtp) |vpiPort: \_port: (DE), line:42:5, endln:42:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__sedfxtp (work@sky130_fd_sc_hd__sedfxtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sedfxtp.functional.v, line:38:1, endln:66:10 + \_module_inst: work@sky130_fd_sc_hd__sedfxtp (work@sky130_fd_sc_hd__sedfxtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sedfxtp.functional.v, line:38:1, endln:66:10 |vpiName:DE |vpiDirection:1 |vpiLowConn: @@ -5222,7 +5222,7 @@ design: (work@sky130_fd_sc_hd__sedfxtp) |vpiPort: \_port: (SCD), line:43:5, endln:43:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__sedfxtp (work@sky130_fd_sc_hd__sedfxtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sedfxtp.functional.v, line:38:1, endln:66:10 + \_module_inst: work@sky130_fd_sc_hd__sedfxtp (work@sky130_fd_sc_hd__sedfxtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sedfxtp.functional.v, line:38:1, endln:66:10 |vpiName:SCD |vpiDirection:1 |vpiLowConn: @@ -5236,7 +5236,7 @@ design: (work@sky130_fd_sc_hd__sedfxtp) |vpiPort: \_port: (SCE), line:44:5, endln:44:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__sedfxtp (work@sky130_fd_sc_hd__sedfxtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sedfxtp.functional.v, line:38:1, endln:66:10 + \_module_inst: work@sky130_fd_sc_hd__sedfxtp (work@sky130_fd_sc_hd__sedfxtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sedfxtp.functional.v, line:38:1, endln:66:10 |vpiName:SCE |vpiDirection:1 |vpiLowConn: @@ -5250,7 +5250,7 @@ design: (work@sky130_fd_sc_hd__sedfxtp) |vpiPrimitive: \_udp: work@sky130_fd_sc_hd__udp_mux_2to1 (work@sky130_fd_sc_hd__sedfxtp.mux_2to10), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sedfxtp.functional.v, line:61:5, endln:61:84 |vpiParent: - \_module: work@sky130_fd_sc_hd__sedfxtp (work@sky130_fd_sc_hd__sedfxtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sedfxtp.functional.v, line:38:1, endln:66:10 + \_module_inst: work@sky130_fd_sc_hd__sedfxtp (work@sky130_fd_sc_hd__sedfxtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sedfxtp.functional.v, line:38:1, endln:66:10 |vpiDefName:work@sky130_fd_sc_hd__udp_mux_2to1 |vpiName:mux_2to10 |vpiFullName:work@sky130_fd_sc_hd__sedfxtp.mux_2to10 @@ -5259,7 +5259,7 @@ design: (work@sky130_fd_sc_hd__sedfxtp) |vpiPrimitive: \_udp: work@sky130_fd_sc_hd__udp_mux_2to1 (work@sky130_fd_sc_hd__sedfxtp.mux_2to11), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sedfxtp.functional.v, line:62:5, endln:62:84 |vpiParent: - \_module: work@sky130_fd_sc_hd__sedfxtp (work@sky130_fd_sc_hd__sedfxtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sedfxtp.functional.v, line:38:1, endln:66:10 + \_module_inst: work@sky130_fd_sc_hd__sedfxtp (work@sky130_fd_sc_hd__sedfxtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sedfxtp.functional.v, line:38:1, endln:66:10 |vpiDefName:work@sky130_fd_sc_hd__udp_mux_2to1 |vpiName:mux_2to11 |vpiFullName:work@sky130_fd_sc_hd__sedfxtp.mux_2to11 @@ -5268,7 +5268,7 @@ design: (work@sky130_fd_sc_hd__sedfxtp) |vpiPrimitive: \_udp: work@sky130_fd_sc_hd__udp_dff$P (work@sky130_fd_sc_hd__sedfxtp.dff0), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sedfxtp.functional.v, line:63:5, endln:63:73 |vpiParent: - \_module: work@sky130_fd_sc_hd__sedfxtp (work@sky130_fd_sc_hd__sedfxtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sedfxtp.functional.v, line:38:1, endln:66:10 + \_module_inst: work@sky130_fd_sc_hd__sedfxtp (work@sky130_fd_sc_hd__sedfxtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sedfxtp.functional.v, line:38:1, endln:66:10 |vpiDefName:work@sky130_fd_sc_hd__udp_dff$P |vpiName:dff0 |vpiFullName:work@sky130_fd_sc_hd__sedfxtp.dff0 @@ -5277,7 +5277,7 @@ design: (work@sky130_fd_sc_hd__sedfxtp) |vpiPrimitive: \_gate: work@buf (work@sky130_fd_sc_hd__sedfxtp.buf0), line:64:47, endln:64:83 |vpiParent: - \_module: work@sky130_fd_sc_hd__sedfxtp (work@sky130_fd_sc_hd__sedfxtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sedfxtp.functional.v, line:38:1, endln:66:10 + \_module_inst: work@sky130_fd_sc_hd__sedfxtp (work@sky130_fd_sc_hd__sedfxtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sedfxtp.functional.v, line:38:1, endln:66:10 |vpiDefName:work@buf |vpiName:buf0 |vpiFullName:work@sky130_fd_sc_hd__sedfxtp.buf0 @@ -5320,7 +5320,7 @@ Processing: -cd cells/cells -DUNIT_DELAY -writepp -parse -nocache -nobuiltin -no design: (work@sky130_fd_sc_hd__xor2) |vpiName:work@sky130_fd_sc_hd__xor2 |uhdmallModules: -\_module: work@sky130_fd_sc_hd__xor2 (work@sky130_fd_sc_hd__xor2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__xor2.functional.v, line:35:1, endln:53:10 +\_module_inst: work@sky130_fd_sc_hd__xor2 (work@sky130_fd_sc_hd__xor2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__xor2.functional.v, line:35:1, endln:53:10 |vpiParent: \_design: (work@sky130_fd_sc_hd__xor2) |vpiFullName:work@sky130_fd_sc_hd__xor2 @@ -5328,32 +5328,32 @@ design: (work@sky130_fd_sc_hd__xor2) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__xor2.xor0_out_X), line:47:10, endln:47:20 |vpiParent: - \_module: work@sky130_fd_sc_hd__xor2 (work@sky130_fd_sc_hd__xor2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__xor2.functional.v, line:35:1, endln:53:10 + \_module_inst: work@sky130_fd_sc_hd__xor2 (work@sky130_fd_sc_hd__xor2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__xor2.functional.v, line:35:1, endln:53:10 |vpiName:xor0_out_X |vpiFullName:work@sky130_fd_sc_hd__xor2.xor0_out_X |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__xor2.X), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__xor2 (work@sky130_fd_sc_hd__xor2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__xor2.functional.v, line:35:1, endln:53:10 + \_module_inst: work@sky130_fd_sc_hd__xor2 (work@sky130_fd_sc_hd__xor2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__xor2.functional.v, line:35:1, endln:53:10 |vpiName:X |vpiFullName:work@sky130_fd_sc_hd__xor2.X |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__xor2.A), line:37:5, endln:37:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__xor2 (work@sky130_fd_sc_hd__xor2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__xor2.functional.v, line:35:1, endln:53:10 + \_module_inst: work@sky130_fd_sc_hd__xor2 (work@sky130_fd_sc_hd__xor2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__xor2.functional.v, line:35:1, endln:53:10 |vpiName:A |vpiFullName:work@sky130_fd_sc_hd__xor2.A |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__xor2.B), line:38:5, endln:38:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__xor2 (work@sky130_fd_sc_hd__xor2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__xor2.functional.v, line:35:1, endln:53:10 + \_module_inst: work@sky130_fd_sc_hd__xor2 (work@sky130_fd_sc_hd__xor2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__xor2.functional.v, line:35:1, endln:53:10 |vpiName:B |vpiFullName:work@sky130_fd_sc_hd__xor2.B |vpiPort: \_port: (X), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__xor2 (work@sky130_fd_sc_hd__xor2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__xor2.functional.v, line:35:1, endln:53:10 + \_module_inst: work@sky130_fd_sc_hd__xor2 (work@sky130_fd_sc_hd__xor2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__xor2.functional.v, line:35:1, endln:53:10 |vpiName:X |vpiDirection:2 |vpiLowConn: @@ -5365,7 +5365,7 @@ design: (work@sky130_fd_sc_hd__xor2) |vpiPort: \_port: (A), line:37:5, endln:37:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__xor2 (work@sky130_fd_sc_hd__xor2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__xor2.functional.v, line:35:1, endln:53:10 + \_module_inst: work@sky130_fd_sc_hd__xor2 (work@sky130_fd_sc_hd__xor2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__xor2.functional.v, line:35:1, endln:53:10 |vpiName:A |vpiDirection:1 |vpiLowConn: @@ -5377,7 +5377,7 @@ design: (work@sky130_fd_sc_hd__xor2) |vpiPort: \_port: (B), line:38:5, endln:38:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__xor2 (work@sky130_fd_sc_hd__xor2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__xor2.functional.v, line:35:1, endln:53:10 + \_module_inst: work@sky130_fd_sc_hd__xor2 (work@sky130_fd_sc_hd__xor2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__xor2.functional.v, line:35:1, endln:53:10 |vpiName:B |vpiDirection:1 |vpiLowConn: @@ -5387,14 +5387,14 @@ design: (work@sky130_fd_sc_hd__xor2) |vpiTypedef: \_logic_typespec: , line:44:12, endln:44:12 |uhdmtopModules: -\_module: work@sky130_fd_sc_hd__xor2 (work@sky130_fd_sc_hd__xor2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__xor2.functional.v, line:35:1, endln:53:10 +\_module_inst: work@sky130_fd_sc_hd__xor2 (work@sky130_fd_sc_hd__xor2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__xor2.functional.v, line:35:1, endln:53:10 |vpiName:work@sky130_fd_sc_hd__xor2 |vpiDefName:work@sky130_fd_sc_hd__xor2 |vpiTop:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__xor2.xor0_out_X), line:47:10, endln:47:20 |vpiParent: - \_module: work@sky130_fd_sc_hd__xor2 (work@sky130_fd_sc_hd__xor2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__xor2.functional.v, line:35:1, endln:53:10 + \_module_inst: work@sky130_fd_sc_hd__xor2 (work@sky130_fd_sc_hd__xor2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__xor2.functional.v, line:35:1, endln:53:10 |vpiTypespec: \_logic_typespec: , line:47:5, endln:47:9 |vpiName:xor0_out_X @@ -5403,7 +5403,7 @@ design: (work@sky130_fd_sc_hd__xor2) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__xor2.X), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__xor2 (work@sky130_fd_sc_hd__xor2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__xor2.functional.v, line:35:1, endln:53:10 + \_module_inst: work@sky130_fd_sc_hd__xor2 (work@sky130_fd_sc_hd__xor2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__xor2.functional.v, line:35:1, endln:53:10 |vpiTypespec: \_logic_typespec: , line:42:12, endln:42:12 |vpiName:X @@ -5411,7 +5411,7 @@ design: (work@sky130_fd_sc_hd__xor2) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__xor2.A), line:37:5, endln:37:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__xor2 (work@sky130_fd_sc_hd__xor2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__xor2.functional.v, line:35:1, endln:53:10 + \_module_inst: work@sky130_fd_sc_hd__xor2 (work@sky130_fd_sc_hd__xor2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__xor2.functional.v, line:35:1, endln:53:10 |vpiTypespec: \_logic_typespec: , line:43:12, endln:43:12 |vpiName:A @@ -5419,7 +5419,7 @@ design: (work@sky130_fd_sc_hd__xor2) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__xor2.B), line:38:5, endln:38:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__xor2 (work@sky130_fd_sc_hd__xor2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__xor2.functional.v, line:35:1, endln:53:10 + \_module_inst: work@sky130_fd_sc_hd__xor2 (work@sky130_fd_sc_hd__xor2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__xor2.functional.v, line:35:1, endln:53:10 |vpiTypespec: \_logic_typespec: , line:44:12, endln:44:12 |vpiName:B @@ -5428,7 +5428,7 @@ design: (work@sky130_fd_sc_hd__xor2) |vpiPort: \_port: (X), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__xor2 (work@sky130_fd_sc_hd__xor2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__xor2.functional.v, line:35:1, endln:53:10 + \_module_inst: work@sky130_fd_sc_hd__xor2 (work@sky130_fd_sc_hd__xor2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__xor2.functional.v, line:35:1, endln:53:10 |vpiName:X |vpiDirection:2 |vpiLowConn: @@ -5442,7 +5442,7 @@ design: (work@sky130_fd_sc_hd__xor2) |vpiPort: \_port: (A), line:37:5, endln:37:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__xor2 (work@sky130_fd_sc_hd__xor2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__xor2.functional.v, line:35:1, endln:53:10 + \_module_inst: work@sky130_fd_sc_hd__xor2 (work@sky130_fd_sc_hd__xor2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__xor2.functional.v, line:35:1, endln:53:10 |vpiName:A |vpiDirection:1 |vpiLowConn: @@ -5456,7 +5456,7 @@ design: (work@sky130_fd_sc_hd__xor2) |vpiPort: \_port: (B), line:38:5, endln:38:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__xor2 (work@sky130_fd_sc_hd__xor2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__xor2.functional.v, line:35:1, endln:53:10 + \_module_inst: work@sky130_fd_sc_hd__xor2 (work@sky130_fd_sc_hd__xor2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__xor2.functional.v, line:35:1, endln:53:10 |vpiName:B |vpiDirection:1 |vpiLowConn: @@ -5470,7 +5470,7 @@ design: (work@sky130_fd_sc_hd__xor2) |vpiPrimitive: \_gate: work@xor (work@sky130_fd_sc_hd__xor2.xor0), line:50:9, endln:50:43 |vpiParent: - \_module: work@sky130_fd_sc_hd__xor2 (work@sky130_fd_sc_hd__xor2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__xor2.functional.v, line:35:1, endln:53:10 + \_module_inst: work@sky130_fd_sc_hd__xor2 (work@sky130_fd_sc_hd__xor2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__xor2.functional.v, line:35:1, endln:53:10 |vpiDefName:work@xor |vpiName:xor0 |vpiFullName:work@sky130_fd_sc_hd__xor2.xor0 @@ -5519,7 +5519,7 @@ design: (work@sky130_fd_sc_hd__xor2) |vpiPrimitive: \_gate: work@buf (work@sky130_fd_sc_hd__xor2.buf0), line:51:9, endln:51:43 |vpiParent: - \_module: work@sky130_fd_sc_hd__xor2 (work@sky130_fd_sc_hd__xor2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__xor2.functional.v, line:35:1, endln:53:10 + \_module_inst: work@sky130_fd_sc_hd__xor2 (work@sky130_fd_sc_hd__xor2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__xor2.functional.v, line:35:1, endln:53:10 |vpiDefName:work@buf |vpiName:buf0 |vpiFullName:work@sky130_fd_sc_hd__xor2.buf0 @@ -5600,7 +5600,7 @@ design: (work@sky130_fd_sc_hd__macro_sparecell) \_include_file_info: , file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__macro_sparecell.functional.v, line:38:10, endln:38:45 |vpiIncludedFile:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/nand2/sky130_fd_sc_hd__nand2.v |uhdmallModules: -\_module: work@sky130_fd_sc_hd__macro_sparecell (work@sky130_fd_sc_hd__macro_sparecell), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__macro_sparecell.functional.v, line:41:1, endln:68:10 +\_module_inst: work@sky130_fd_sc_hd__macro_sparecell (work@sky130_fd_sc_hd__macro_sparecell), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__macro_sparecell.functional.v, line:41:1, endln:68:10 |vpiParent: \_design: (work@sky130_fd_sc_hd__macro_sparecell) |vpiFullName:work@sky130_fd_sc_hd__macro_sparecell @@ -5608,69 +5608,69 @@ design: (work@sky130_fd_sc_hd__macro_sparecell) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__macro_sparecell.nor2left), line:49:10, endln:49:18 |vpiParent: - \_module: work@sky130_fd_sc_hd__macro_sparecell (work@sky130_fd_sc_hd__macro_sparecell), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__macro_sparecell.functional.v, line:41:1, endln:68:10 + \_module_inst: work@sky130_fd_sc_hd__macro_sparecell (work@sky130_fd_sc_hd__macro_sparecell), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__macro_sparecell.functional.v, line:41:1, endln:68:10 |vpiName:nor2left |vpiFullName:work@sky130_fd_sc_hd__macro_sparecell.nor2left |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__macro_sparecell.invleft), line:50:10, endln:50:17 |vpiParent: - \_module: work@sky130_fd_sc_hd__macro_sparecell (work@sky130_fd_sc_hd__macro_sparecell), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__macro_sparecell.functional.v, line:41:1, endln:68:10 + \_module_inst: work@sky130_fd_sc_hd__macro_sparecell (work@sky130_fd_sc_hd__macro_sparecell), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__macro_sparecell.functional.v, line:41:1, endln:68:10 |vpiName:invleft |vpiFullName:work@sky130_fd_sc_hd__macro_sparecell.invleft |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__macro_sparecell.nor2right), line:51:10, endln:51:19 |vpiParent: - \_module: work@sky130_fd_sc_hd__macro_sparecell (work@sky130_fd_sc_hd__macro_sparecell), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__macro_sparecell.functional.v, line:41:1, endln:68:10 + \_module_inst: work@sky130_fd_sc_hd__macro_sparecell (work@sky130_fd_sc_hd__macro_sparecell), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__macro_sparecell.functional.v, line:41:1, endln:68:10 |vpiName:nor2right |vpiFullName:work@sky130_fd_sc_hd__macro_sparecell.nor2right |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__macro_sparecell.invright), line:52:10, endln:52:18 |vpiParent: - \_module: work@sky130_fd_sc_hd__macro_sparecell (work@sky130_fd_sc_hd__macro_sparecell), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__macro_sparecell.functional.v, line:41:1, endln:68:10 + \_module_inst: work@sky130_fd_sc_hd__macro_sparecell (work@sky130_fd_sc_hd__macro_sparecell), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__macro_sparecell.functional.v, line:41:1, endln:68:10 |vpiName:invright |vpiFullName:work@sky130_fd_sc_hd__macro_sparecell.invright |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__macro_sparecell.nd2left), line:53:10, endln:53:17 |vpiParent: - \_module: work@sky130_fd_sc_hd__macro_sparecell (work@sky130_fd_sc_hd__macro_sparecell), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__macro_sparecell.functional.v, line:41:1, endln:68:10 + \_module_inst: work@sky130_fd_sc_hd__macro_sparecell (work@sky130_fd_sc_hd__macro_sparecell), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__macro_sparecell.functional.v, line:41:1, endln:68:10 |vpiName:nd2left |vpiFullName:work@sky130_fd_sc_hd__macro_sparecell.nd2left |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__macro_sparecell.nd2right), line:54:10, endln:54:18 |vpiParent: - \_module: work@sky130_fd_sc_hd__macro_sparecell (work@sky130_fd_sc_hd__macro_sparecell), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__macro_sparecell.functional.v, line:41:1, endln:68:10 + \_module_inst: work@sky130_fd_sc_hd__macro_sparecell (work@sky130_fd_sc_hd__macro_sparecell), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__macro_sparecell.functional.v, line:41:1, endln:68:10 |vpiName:nd2right |vpiFullName:work@sky130_fd_sc_hd__macro_sparecell.nd2right |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__macro_sparecell.tielo), line:55:10, endln:55:15 |vpiParent: - \_module: work@sky130_fd_sc_hd__macro_sparecell (work@sky130_fd_sc_hd__macro_sparecell), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__macro_sparecell.functional.v, line:41:1, endln:68:10 + \_module_inst: work@sky130_fd_sc_hd__macro_sparecell (work@sky130_fd_sc_hd__macro_sparecell), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__macro_sparecell.functional.v, line:41:1, endln:68:10 |vpiName:tielo |vpiFullName:work@sky130_fd_sc_hd__macro_sparecell.tielo |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__macro_sparecell.net7), line:56:10, endln:56:14 |vpiParent: - \_module: work@sky130_fd_sc_hd__macro_sparecell (work@sky130_fd_sc_hd__macro_sparecell), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__macro_sparecell.functional.v, line:41:1, endln:68:10 + \_module_inst: work@sky130_fd_sc_hd__macro_sparecell (work@sky130_fd_sc_hd__macro_sparecell), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__macro_sparecell.functional.v, line:41:1, endln:68:10 |vpiName:net7 |vpiFullName:work@sky130_fd_sc_hd__macro_sparecell.net7 |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__macro_sparecell.LO), line:42:5, endln:42:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__macro_sparecell (work@sky130_fd_sc_hd__macro_sparecell), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__macro_sparecell.functional.v, line:41:1, endln:68:10 + \_module_inst: work@sky130_fd_sc_hd__macro_sparecell (work@sky130_fd_sc_hd__macro_sparecell), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__macro_sparecell.functional.v, line:41:1, endln:68:10 |vpiName:LO |vpiFullName:work@sky130_fd_sc_hd__macro_sparecell.LO |vpiPort: \_port: (LO), line:42:5, endln:42:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__macro_sparecell (work@sky130_fd_sc_hd__macro_sparecell), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__macro_sparecell.functional.v, line:41:1, endln:68:10 + \_module_inst: work@sky130_fd_sc_hd__macro_sparecell (work@sky130_fd_sc_hd__macro_sparecell), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__macro_sparecell.functional.v, line:41:1, endln:68:10 |vpiName:LO |vpiDirection:2 |vpiLowConn: @@ -5680,14 +5680,14 @@ design: (work@sky130_fd_sc_hd__macro_sparecell) |vpiTypedef: \_logic_typespec: , line:46:12, endln:46:12 |uhdmtopModules: -\_module: work@sky130_fd_sc_hd__macro_sparecell (work@sky130_fd_sc_hd__macro_sparecell), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__macro_sparecell.functional.v, line:41:1, endln:68:10 +\_module_inst: work@sky130_fd_sc_hd__macro_sparecell (work@sky130_fd_sc_hd__macro_sparecell), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__macro_sparecell.functional.v, line:41:1, endln:68:10 |vpiName:work@sky130_fd_sc_hd__macro_sparecell |vpiDefName:work@sky130_fd_sc_hd__macro_sparecell |vpiTop:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__macro_sparecell.nor2left), line:49:10, endln:49:18 |vpiParent: - \_module: work@sky130_fd_sc_hd__macro_sparecell (work@sky130_fd_sc_hd__macro_sparecell), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__macro_sparecell.functional.v, line:41:1, endln:68:10 + \_module_inst: work@sky130_fd_sc_hd__macro_sparecell (work@sky130_fd_sc_hd__macro_sparecell), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__macro_sparecell.functional.v, line:41:1, endln:68:10 |vpiTypespec: \_logic_typespec: , line:49:5, endln:49:9 |vpiName:nor2left @@ -5696,7 +5696,7 @@ design: (work@sky130_fd_sc_hd__macro_sparecell) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__macro_sparecell.invleft), line:50:10, endln:50:17 |vpiParent: - \_module: work@sky130_fd_sc_hd__macro_sparecell (work@sky130_fd_sc_hd__macro_sparecell), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__macro_sparecell.functional.v, line:41:1, endln:68:10 + \_module_inst: work@sky130_fd_sc_hd__macro_sparecell (work@sky130_fd_sc_hd__macro_sparecell), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__macro_sparecell.functional.v, line:41:1, endln:68:10 |vpiTypespec: \_logic_typespec: , line:50:5, endln:50:9 |vpiName:invleft @@ -5705,7 +5705,7 @@ design: (work@sky130_fd_sc_hd__macro_sparecell) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__macro_sparecell.nor2right), line:51:10, endln:51:19 |vpiParent: - \_module: work@sky130_fd_sc_hd__macro_sparecell (work@sky130_fd_sc_hd__macro_sparecell), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__macro_sparecell.functional.v, line:41:1, endln:68:10 + \_module_inst: work@sky130_fd_sc_hd__macro_sparecell (work@sky130_fd_sc_hd__macro_sparecell), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__macro_sparecell.functional.v, line:41:1, endln:68:10 |vpiTypespec: \_logic_typespec: , line:51:5, endln:51:9 |vpiName:nor2right @@ -5714,7 +5714,7 @@ design: (work@sky130_fd_sc_hd__macro_sparecell) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__macro_sparecell.invright), line:52:10, endln:52:18 |vpiParent: - \_module: work@sky130_fd_sc_hd__macro_sparecell (work@sky130_fd_sc_hd__macro_sparecell), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__macro_sparecell.functional.v, line:41:1, endln:68:10 + \_module_inst: work@sky130_fd_sc_hd__macro_sparecell (work@sky130_fd_sc_hd__macro_sparecell), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__macro_sparecell.functional.v, line:41:1, endln:68:10 |vpiTypespec: \_logic_typespec: , line:52:5, endln:52:9 |vpiName:invright @@ -5723,7 +5723,7 @@ design: (work@sky130_fd_sc_hd__macro_sparecell) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__macro_sparecell.nd2left), line:53:10, endln:53:17 |vpiParent: - \_module: work@sky130_fd_sc_hd__macro_sparecell (work@sky130_fd_sc_hd__macro_sparecell), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__macro_sparecell.functional.v, line:41:1, endln:68:10 + \_module_inst: work@sky130_fd_sc_hd__macro_sparecell (work@sky130_fd_sc_hd__macro_sparecell), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__macro_sparecell.functional.v, line:41:1, endln:68:10 |vpiTypespec: \_logic_typespec: , line:53:5, endln:53:9 |vpiName:nd2left @@ -5732,7 +5732,7 @@ design: (work@sky130_fd_sc_hd__macro_sparecell) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__macro_sparecell.nd2right), line:54:10, endln:54:18 |vpiParent: - \_module: work@sky130_fd_sc_hd__macro_sparecell (work@sky130_fd_sc_hd__macro_sparecell), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__macro_sparecell.functional.v, line:41:1, endln:68:10 + \_module_inst: work@sky130_fd_sc_hd__macro_sparecell (work@sky130_fd_sc_hd__macro_sparecell), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__macro_sparecell.functional.v, line:41:1, endln:68:10 |vpiTypespec: \_logic_typespec: , line:54:5, endln:54:9 |vpiName:nd2right @@ -5741,7 +5741,7 @@ design: (work@sky130_fd_sc_hd__macro_sparecell) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__macro_sparecell.tielo), line:55:10, endln:55:15 |vpiParent: - \_module: work@sky130_fd_sc_hd__macro_sparecell (work@sky130_fd_sc_hd__macro_sparecell), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__macro_sparecell.functional.v, line:41:1, endln:68:10 + \_module_inst: work@sky130_fd_sc_hd__macro_sparecell (work@sky130_fd_sc_hd__macro_sparecell), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__macro_sparecell.functional.v, line:41:1, endln:68:10 |vpiTypespec: \_logic_typespec: , line:55:5, endln:55:9 |vpiName:tielo @@ -5750,7 +5750,7 @@ design: (work@sky130_fd_sc_hd__macro_sparecell) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__macro_sparecell.net7), line:56:10, endln:56:14 |vpiParent: - \_module: work@sky130_fd_sc_hd__macro_sparecell (work@sky130_fd_sc_hd__macro_sparecell), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__macro_sparecell.functional.v, line:41:1, endln:68:10 + \_module_inst: work@sky130_fd_sc_hd__macro_sparecell (work@sky130_fd_sc_hd__macro_sparecell), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__macro_sparecell.functional.v, line:41:1, endln:68:10 |vpiTypespec: \_logic_typespec: , line:56:5, endln:56:9 |vpiName:net7 @@ -5759,7 +5759,7 @@ design: (work@sky130_fd_sc_hd__macro_sparecell) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__macro_sparecell.LO), line:42:5, endln:42:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__macro_sparecell (work@sky130_fd_sc_hd__macro_sparecell), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__macro_sparecell.functional.v, line:41:1, endln:68:10 + \_module_inst: work@sky130_fd_sc_hd__macro_sparecell (work@sky130_fd_sc_hd__macro_sparecell), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__macro_sparecell.functional.v, line:41:1, endln:68:10 |vpiTypespec: \_logic_typespec: , line:46:12, endln:46:12 |vpiName:LO @@ -5768,7 +5768,7 @@ design: (work@sky130_fd_sc_hd__macro_sparecell) |vpiPort: \_port: (LO), line:42:5, endln:42:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__macro_sparecell (work@sky130_fd_sc_hd__macro_sparecell), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__macro_sparecell.functional.v, line:41:1, endln:68:10 + \_module_inst: work@sky130_fd_sc_hd__macro_sparecell (work@sky130_fd_sc_hd__macro_sparecell), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__macro_sparecell.functional.v, line:41:1, endln:68:10 |vpiName:LO |vpiDirection:2 |vpiLowConn: @@ -5779,19 +5779,19 @@ design: (work@sky130_fd_sc_hd__macro_sparecell) \_logic_net: (work@sky130_fd_sc_hd__macro_sparecell.LO), line:42:5, endln:42:7 |vpiTypedef: \_logic_typespec: , line:46:12, endln:46:12 - |vpiModule: - \_module: work@sky130_fd_sc_hd__macro_sparecell::sky130_fd_sc_hd__inv_2 (work@sky130_fd_sc_hd__macro_sparecell.inv0), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__macro_sparecell.functional.v, line:59:5, endln:59:82 + |vpiModuleInst: + \_module_inst: work@sky130_fd_sc_hd__macro_sparecell::sky130_fd_sc_hd__inv_2 (work@sky130_fd_sc_hd__macro_sparecell.inv0), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__macro_sparecell.functional.v, line:59:5, endln:59:82 |vpiParent: - \_module: work@sky130_fd_sc_hd__macro_sparecell (work@sky130_fd_sc_hd__macro_sparecell), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__macro_sparecell.functional.v, line:41:1, endln:68:10 + \_module_inst: work@sky130_fd_sc_hd__macro_sparecell (work@sky130_fd_sc_hd__macro_sparecell), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__macro_sparecell.functional.v, line:41:1, endln:68:10 |vpiName:inv0 |vpiFullName:work@sky130_fd_sc_hd__macro_sparecell.inv0 |vpiDefName:work@sky130_fd_sc_hd__macro_sparecell::sky130_fd_sc_hd__inv_2 |vpiInstance: - \_module: work@sky130_fd_sc_hd__macro_sparecell (work@sky130_fd_sc_hd__macro_sparecell), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__macro_sparecell.functional.v, line:41:1, endln:68:10 + \_module_inst: work@sky130_fd_sc_hd__macro_sparecell (work@sky130_fd_sc_hd__macro_sparecell), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__macro_sparecell.functional.v, line:41:1, endln:68:10 |vpiPort: \_port: (A), line:59:39, endln:59:40 |vpiParent: - \_module: work@sky130_fd_sc_hd__macro_sparecell::sky130_fd_sc_hd__inv_2 (work@sky130_fd_sc_hd__macro_sparecell.inv0), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__macro_sparecell.functional.v, line:59:5, endln:59:82 + \_module_inst: work@sky130_fd_sc_hd__macro_sparecell::sky130_fd_sc_hd__inv_2 (work@sky130_fd_sc_hd__macro_sparecell.inv0), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__macro_sparecell.functional.v, line:59:5, endln:59:82 |vpiName:A |vpiHighConn: \_ref_obj: (work@sky130_fd_sc_hd__macro_sparecell.nor2left), line:59:41, endln:59:49 @@ -5802,7 +5802,7 @@ design: (work@sky130_fd_sc_hd__macro_sparecell) |vpiPort: \_port: (Y), line:59:54, endln:59:55 |vpiParent: - \_module: work@sky130_fd_sc_hd__macro_sparecell::sky130_fd_sc_hd__inv_2 (work@sky130_fd_sc_hd__macro_sparecell.inv0), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__macro_sparecell.functional.v, line:59:5, endln:59:82 + \_module_inst: work@sky130_fd_sc_hd__macro_sparecell::sky130_fd_sc_hd__inv_2 (work@sky130_fd_sc_hd__macro_sparecell.inv0), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__macro_sparecell.functional.v, line:59:5, endln:59:82 |vpiName:Y |vpiHighConn: \_ref_obj: (work@sky130_fd_sc_hd__macro_sparecell.invleft), line:59:56, endln:59:63 @@ -5810,19 +5810,19 @@ design: (work@sky130_fd_sc_hd__macro_sparecell) |vpiFullName:work@sky130_fd_sc_hd__macro_sparecell.invleft |vpiActual: \_logic_net: (work@sky130_fd_sc_hd__macro_sparecell.invleft), line:50:10, endln:50:17 - |vpiModule: - \_module: work@sky130_fd_sc_hd__macro_sparecell::sky130_fd_sc_hd__inv_2 (work@sky130_fd_sc_hd__macro_sparecell.inv1), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__macro_sparecell.functional.v, line:60:5, endln:60:82 + |vpiModuleInst: + \_module_inst: work@sky130_fd_sc_hd__macro_sparecell::sky130_fd_sc_hd__inv_2 (work@sky130_fd_sc_hd__macro_sparecell.inv1), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__macro_sparecell.functional.v, line:60:5, endln:60:82 |vpiParent: - \_module: work@sky130_fd_sc_hd__macro_sparecell (work@sky130_fd_sc_hd__macro_sparecell), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__macro_sparecell.functional.v, line:41:1, endln:68:10 + \_module_inst: work@sky130_fd_sc_hd__macro_sparecell (work@sky130_fd_sc_hd__macro_sparecell), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__macro_sparecell.functional.v, line:41:1, endln:68:10 |vpiName:inv1 |vpiFullName:work@sky130_fd_sc_hd__macro_sparecell.inv1 |vpiDefName:work@sky130_fd_sc_hd__macro_sparecell::sky130_fd_sc_hd__inv_2 |vpiInstance: - \_module: work@sky130_fd_sc_hd__macro_sparecell (work@sky130_fd_sc_hd__macro_sparecell), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__macro_sparecell.functional.v, line:41:1, endln:68:10 + \_module_inst: work@sky130_fd_sc_hd__macro_sparecell (work@sky130_fd_sc_hd__macro_sparecell), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__macro_sparecell.functional.v, line:41:1, endln:68:10 |vpiPort: \_port: (A), line:60:39, endln:60:40 |vpiParent: - \_module: work@sky130_fd_sc_hd__macro_sparecell::sky130_fd_sc_hd__inv_2 (work@sky130_fd_sc_hd__macro_sparecell.inv1), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__macro_sparecell.functional.v, line:60:5, endln:60:82 + \_module_inst: work@sky130_fd_sc_hd__macro_sparecell::sky130_fd_sc_hd__inv_2 (work@sky130_fd_sc_hd__macro_sparecell.inv1), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__macro_sparecell.functional.v, line:60:5, endln:60:82 |vpiName:A |vpiHighConn: \_ref_obj: (work@sky130_fd_sc_hd__macro_sparecell.nor2right), line:60:41, endln:60:50 @@ -5833,7 +5833,7 @@ design: (work@sky130_fd_sc_hd__macro_sparecell) |vpiPort: \_port: (Y), line:60:54, endln:60:55 |vpiParent: - \_module: work@sky130_fd_sc_hd__macro_sparecell::sky130_fd_sc_hd__inv_2 (work@sky130_fd_sc_hd__macro_sparecell.inv1), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__macro_sparecell.functional.v, line:60:5, endln:60:82 + \_module_inst: work@sky130_fd_sc_hd__macro_sparecell::sky130_fd_sc_hd__inv_2 (work@sky130_fd_sc_hd__macro_sparecell.inv1), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__macro_sparecell.functional.v, line:60:5, endln:60:82 |vpiName:Y |vpiHighConn: \_ref_obj: (work@sky130_fd_sc_hd__macro_sparecell.invright), line:60:56, endln:60:64 @@ -5841,19 +5841,19 @@ design: (work@sky130_fd_sc_hd__macro_sparecell) |vpiFullName:work@sky130_fd_sc_hd__macro_sparecell.invright |vpiActual: \_logic_net: (work@sky130_fd_sc_hd__macro_sparecell.invright), line:52:10, endln:52:18 - |vpiModule: - \_module: work@sky130_fd_sc_hd__macro_sparecell::sky130_fd_sc_hd__nor2_2 (work@sky130_fd_sc_hd__macro_sparecell.nor20), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__macro_sparecell.functional.v, line:61:5, endln:61:82 + |vpiModuleInst: + \_module_inst: work@sky130_fd_sc_hd__macro_sparecell::sky130_fd_sc_hd__nor2_2 (work@sky130_fd_sc_hd__macro_sparecell.nor20), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__macro_sparecell.functional.v, line:61:5, endln:61:82 |vpiParent: - \_module: work@sky130_fd_sc_hd__macro_sparecell (work@sky130_fd_sc_hd__macro_sparecell), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__macro_sparecell.functional.v, line:41:1, endln:68:10 + \_module_inst: work@sky130_fd_sc_hd__macro_sparecell (work@sky130_fd_sc_hd__macro_sparecell), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__macro_sparecell.functional.v, line:41:1, endln:68:10 |vpiName:nor20 |vpiFullName:work@sky130_fd_sc_hd__macro_sparecell.nor20 |vpiDefName:work@sky130_fd_sc_hd__macro_sparecell::sky130_fd_sc_hd__nor2_2 |vpiInstance: - \_module: work@sky130_fd_sc_hd__macro_sparecell (work@sky130_fd_sc_hd__macro_sparecell), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__macro_sparecell.functional.v, line:41:1, endln:68:10 + \_module_inst: work@sky130_fd_sc_hd__macro_sparecell (work@sky130_fd_sc_hd__macro_sparecell), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__macro_sparecell.functional.v, line:41:1, endln:68:10 |vpiPort: \_port: (B), line:61:39, endln:61:40 |vpiParent: - \_module: work@sky130_fd_sc_hd__macro_sparecell::sky130_fd_sc_hd__nor2_2 (work@sky130_fd_sc_hd__macro_sparecell.nor20), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__macro_sparecell.functional.v, line:61:5, endln:61:82 + \_module_inst: work@sky130_fd_sc_hd__macro_sparecell::sky130_fd_sc_hd__nor2_2 (work@sky130_fd_sc_hd__macro_sparecell.nor20), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__macro_sparecell.functional.v, line:61:5, endln:61:82 |vpiName:B |vpiHighConn: \_ref_obj: (work@sky130_fd_sc_hd__macro_sparecell.nd2left), line:61:41, endln:61:48 @@ -5864,7 +5864,7 @@ design: (work@sky130_fd_sc_hd__macro_sparecell) |vpiPort: \_port: (A), line:61:54, endln:61:55 |vpiParent: - \_module: work@sky130_fd_sc_hd__macro_sparecell::sky130_fd_sc_hd__nor2_2 (work@sky130_fd_sc_hd__macro_sparecell.nor20), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__macro_sparecell.functional.v, line:61:5, endln:61:82 + \_module_inst: work@sky130_fd_sc_hd__macro_sparecell::sky130_fd_sc_hd__nor2_2 (work@sky130_fd_sc_hd__macro_sparecell.nor20), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__macro_sparecell.functional.v, line:61:5, endln:61:82 |vpiName:A |vpiHighConn: \_ref_obj: (work@sky130_fd_sc_hd__macro_sparecell.nd2left), line:61:56, endln:61:63 @@ -5875,7 +5875,7 @@ design: (work@sky130_fd_sc_hd__macro_sparecell) |vpiPort: \_port: (Y), line:61:67, endln:61:68 |vpiParent: - \_module: work@sky130_fd_sc_hd__macro_sparecell::sky130_fd_sc_hd__nor2_2 (work@sky130_fd_sc_hd__macro_sparecell.nor20), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__macro_sparecell.functional.v, line:61:5, endln:61:82 + \_module_inst: work@sky130_fd_sc_hd__macro_sparecell::sky130_fd_sc_hd__nor2_2 (work@sky130_fd_sc_hd__macro_sparecell.nor20), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__macro_sparecell.functional.v, line:61:5, endln:61:82 |vpiName:Y |vpiHighConn: \_ref_obj: (work@sky130_fd_sc_hd__macro_sparecell.nor2left), line:61:69, endln:61:77 @@ -5883,19 +5883,19 @@ design: (work@sky130_fd_sc_hd__macro_sparecell) |vpiFullName:work@sky130_fd_sc_hd__macro_sparecell.nor2left |vpiActual: \_logic_net: (work@sky130_fd_sc_hd__macro_sparecell.nor2left), line:49:10, endln:49:18 - |vpiModule: - \_module: work@sky130_fd_sc_hd__macro_sparecell::sky130_fd_sc_hd__nor2_2 (work@sky130_fd_sc_hd__macro_sparecell.nor21), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__macro_sparecell.functional.v, line:62:5, endln:62:82 + |vpiModuleInst: + \_module_inst: work@sky130_fd_sc_hd__macro_sparecell::sky130_fd_sc_hd__nor2_2 (work@sky130_fd_sc_hd__macro_sparecell.nor21), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__macro_sparecell.functional.v, line:62:5, endln:62:82 |vpiParent: - \_module: work@sky130_fd_sc_hd__macro_sparecell (work@sky130_fd_sc_hd__macro_sparecell), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__macro_sparecell.functional.v, line:41:1, endln:68:10 + \_module_inst: work@sky130_fd_sc_hd__macro_sparecell (work@sky130_fd_sc_hd__macro_sparecell), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__macro_sparecell.functional.v, line:41:1, endln:68:10 |vpiName:nor21 |vpiFullName:work@sky130_fd_sc_hd__macro_sparecell.nor21 |vpiDefName:work@sky130_fd_sc_hd__macro_sparecell::sky130_fd_sc_hd__nor2_2 |vpiInstance: - \_module: work@sky130_fd_sc_hd__macro_sparecell (work@sky130_fd_sc_hd__macro_sparecell), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__macro_sparecell.functional.v, line:41:1, endln:68:10 + \_module_inst: work@sky130_fd_sc_hd__macro_sparecell (work@sky130_fd_sc_hd__macro_sparecell), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__macro_sparecell.functional.v, line:41:1, endln:68:10 |vpiPort: \_port: (B), line:62:39, endln:62:40 |vpiParent: - \_module: work@sky130_fd_sc_hd__macro_sparecell::sky130_fd_sc_hd__nor2_2 (work@sky130_fd_sc_hd__macro_sparecell.nor21), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__macro_sparecell.functional.v, line:62:5, endln:62:82 + \_module_inst: work@sky130_fd_sc_hd__macro_sparecell::sky130_fd_sc_hd__nor2_2 (work@sky130_fd_sc_hd__macro_sparecell.nor21), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__macro_sparecell.functional.v, line:62:5, endln:62:82 |vpiName:B |vpiHighConn: \_ref_obj: (work@sky130_fd_sc_hd__macro_sparecell.nd2right), line:62:41, endln:62:49 @@ -5906,7 +5906,7 @@ design: (work@sky130_fd_sc_hd__macro_sparecell) |vpiPort: \_port: (A), line:62:54, endln:62:55 |vpiParent: - \_module: work@sky130_fd_sc_hd__macro_sparecell::sky130_fd_sc_hd__nor2_2 (work@sky130_fd_sc_hd__macro_sparecell.nor21), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__macro_sparecell.functional.v, line:62:5, endln:62:82 + \_module_inst: work@sky130_fd_sc_hd__macro_sparecell::sky130_fd_sc_hd__nor2_2 (work@sky130_fd_sc_hd__macro_sparecell.nor21), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__macro_sparecell.functional.v, line:62:5, endln:62:82 |vpiName:A |vpiHighConn: \_ref_obj: (work@sky130_fd_sc_hd__macro_sparecell.nd2right), line:62:56, endln:62:64 @@ -5917,7 +5917,7 @@ design: (work@sky130_fd_sc_hd__macro_sparecell) |vpiPort: \_port: (Y), line:62:68, endln:62:69 |vpiParent: - \_module: work@sky130_fd_sc_hd__macro_sparecell::sky130_fd_sc_hd__nor2_2 (work@sky130_fd_sc_hd__macro_sparecell.nor21), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__macro_sparecell.functional.v, line:62:5, endln:62:82 + \_module_inst: work@sky130_fd_sc_hd__macro_sparecell::sky130_fd_sc_hd__nor2_2 (work@sky130_fd_sc_hd__macro_sparecell.nor21), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__macro_sparecell.functional.v, line:62:5, endln:62:82 |vpiName:Y |vpiHighConn: \_ref_obj: (work@sky130_fd_sc_hd__macro_sparecell.nor2right), line:62:70, endln:62:79 @@ -5925,19 +5925,19 @@ design: (work@sky130_fd_sc_hd__macro_sparecell) |vpiFullName:work@sky130_fd_sc_hd__macro_sparecell.nor2right |vpiActual: \_logic_net: (work@sky130_fd_sc_hd__macro_sparecell.nor2right), line:51:10, endln:51:19 - |vpiModule: - \_module: work@sky130_fd_sc_hd__macro_sparecell::sky130_fd_sc_hd__nand2_2 (work@sky130_fd_sc_hd__macro_sparecell.nand20), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__macro_sparecell.functional.v, line:63:5, endln:63:82 + |vpiModuleInst: + \_module_inst: work@sky130_fd_sc_hd__macro_sparecell::sky130_fd_sc_hd__nand2_2 (work@sky130_fd_sc_hd__macro_sparecell.nand20), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__macro_sparecell.functional.v, line:63:5, endln:63:82 |vpiParent: - \_module: work@sky130_fd_sc_hd__macro_sparecell (work@sky130_fd_sc_hd__macro_sparecell), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__macro_sparecell.functional.v, line:41:1, endln:68:10 + \_module_inst: work@sky130_fd_sc_hd__macro_sparecell (work@sky130_fd_sc_hd__macro_sparecell), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__macro_sparecell.functional.v, line:41:1, endln:68:10 |vpiName:nand20 |vpiFullName:work@sky130_fd_sc_hd__macro_sparecell.nand20 |vpiDefName:work@sky130_fd_sc_hd__macro_sparecell::sky130_fd_sc_hd__nand2_2 |vpiInstance: - \_module: work@sky130_fd_sc_hd__macro_sparecell (work@sky130_fd_sc_hd__macro_sparecell), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__macro_sparecell.functional.v, line:41:1, endln:68:10 + \_module_inst: work@sky130_fd_sc_hd__macro_sparecell (work@sky130_fd_sc_hd__macro_sparecell), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__macro_sparecell.functional.v, line:41:1, endln:68:10 |vpiPort: \_port: (B), line:63:39, endln:63:40 |vpiParent: - \_module: work@sky130_fd_sc_hd__macro_sparecell::sky130_fd_sc_hd__nand2_2 (work@sky130_fd_sc_hd__macro_sparecell.nand20), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__macro_sparecell.functional.v, line:63:5, endln:63:82 + \_module_inst: work@sky130_fd_sc_hd__macro_sparecell::sky130_fd_sc_hd__nand2_2 (work@sky130_fd_sc_hd__macro_sparecell.nand20), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__macro_sparecell.functional.v, line:63:5, endln:63:82 |vpiName:B |vpiHighConn: \_ref_obj: (work@sky130_fd_sc_hd__macro_sparecell.tielo), line:63:41, endln:63:46 @@ -5948,7 +5948,7 @@ design: (work@sky130_fd_sc_hd__macro_sparecell) |vpiPort: \_port: (A), line:63:54, endln:63:55 |vpiParent: - \_module: work@sky130_fd_sc_hd__macro_sparecell::sky130_fd_sc_hd__nand2_2 (work@sky130_fd_sc_hd__macro_sparecell.nand20), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__macro_sparecell.functional.v, line:63:5, endln:63:82 + \_module_inst: work@sky130_fd_sc_hd__macro_sparecell::sky130_fd_sc_hd__nand2_2 (work@sky130_fd_sc_hd__macro_sparecell.nand20), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__macro_sparecell.functional.v, line:63:5, endln:63:82 |vpiName:A |vpiHighConn: \_ref_obj: (work@sky130_fd_sc_hd__macro_sparecell.tielo), line:63:56, endln:63:61 @@ -5959,7 +5959,7 @@ design: (work@sky130_fd_sc_hd__macro_sparecell) |vpiPort: \_port: (Y), line:63:65, endln:63:66 |vpiParent: - \_module: work@sky130_fd_sc_hd__macro_sparecell::sky130_fd_sc_hd__nand2_2 (work@sky130_fd_sc_hd__macro_sparecell.nand20), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__macro_sparecell.functional.v, line:63:5, endln:63:82 + \_module_inst: work@sky130_fd_sc_hd__macro_sparecell::sky130_fd_sc_hd__nand2_2 (work@sky130_fd_sc_hd__macro_sparecell.nand20), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__macro_sparecell.functional.v, line:63:5, endln:63:82 |vpiName:Y |vpiHighConn: \_ref_obj: (work@sky130_fd_sc_hd__macro_sparecell.nd2right), line:63:67, endln:63:75 @@ -5967,19 +5967,19 @@ design: (work@sky130_fd_sc_hd__macro_sparecell) |vpiFullName:work@sky130_fd_sc_hd__macro_sparecell.nd2right |vpiActual: \_logic_net: (work@sky130_fd_sc_hd__macro_sparecell.nd2right), line:54:10, endln:54:18 - |vpiModule: - \_module: work@sky130_fd_sc_hd__macro_sparecell::sky130_fd_sc_hd__nand2_2 (work@sky130_fd_sc_hd__macro_sparecell.nand21), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__macro_sparecell.functional.v, line:64:5, endln:64:82 + |vpiModuleInst: + \_module_inst: work@sky130_fd_sc_hd__macro_sparecell::sky130_fd_sc_hd__nand2_2 (work@sky130_fd_sc_hd__macro_sparecell.nand21), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__macro_sparecell.functional.v, line:64:5, endln:64:82 |vpiParent: - \_module: work@sky130_fd_sc_hd__macro_sparecell (work@sky130_fd_sc_hd__macro_sparecell), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__macro_sparecell.functional.v, line:41:1, endln:68:10 + \_module_inst: work@sky130_fd_sc_hd__macro_sparecell (work@sky130_fd_sc_hd__macro_sparecell), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__macro_sparecell.functional.v, line:41:1, endln:68:10 |vpiName:nand21 |vpiFullName:work@sky130_fd_sc_hd__macro_sparecell.nand21 |vpiDefName:work@sky130_fd_sc_hd__macro_sparecell::sky130_fd_sc_hd__nand2_2 |vpiInstance: - \_module: work@sky130_fd_sc_hd__macro_sparecell (work@sky130_fd_sc_hd__macro_sparecell), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__macro_sparecell.functional.v, line:41:1, endln:68:10 + \_module_inst: work@sky130_fd_sc_hd__macro_sparecell (work@sky130_fd_sc_hd__macro_sparecell), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__macro_sparecell.functional.v, line:41:1, endln:68:10 |vpiPort: \_port: (B), line:64:39, endln:64:40 |vpiParent: - \_module: work@sky130_fd_sc_hd__macro_sparecell::sky130_fd_sc_hd__nand2_2 (work@sky130_fd_sc_hd__macro_sparecell.nand21), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__macro_sparecell.functional.v, line:64:5, endln:64:82 + \_module_inst: work@sky130_fd_sc_hd__macro_sparecell::sky130_fd_sc_hd__nand2_2 (work@sky130_fd_sc_hd__macro_sparecell.nand21), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__macro_sparecell.functional.v, line:64:5, endln:64:82 |vpiName:B |vpiHighConn: \_ref_obj: (work@sky130_fd_sc_hd__macro_sparecell.tielo), line:64:41, endln:64:46 @@ -5990,7 +5990,7 @@ design: (work@sky130_fd_sc_hd__macro_sparecell) |vpiPort: \_port: (A), line:64:54, endln:64:55 |vpiParent: - \_module: work@sky130_fd_sc_hd__macro_sparecell::sky130_fd_sc_hd__nand2_2 (work@sky130_fd_sc_hd__macro_sparecell.nand21), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__macro_sparecell.functional.v, line:64:5, endln:64:82 + \_module_inst: work@sky130_fd_sc_hd__macro_sparecell::sky130_fd_sc_hd__nand2_2 (work@sky130_fd_sc_hd__macro_sparecell.nand21), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__macro_sparecell.functional.v, line:64:5, endln:64:82 |vpiName:A |vpiHighConn: \_ref_obj: (work@sky130_fd_sc_hd__macro_sparecell.tielo), line:64:56, endln:64:61 @@ -6001,7 +6001,7 @@ design: (work@sky130_fd_sc_hd__macro_sparecell) |vpiPort: \_port: (Y), line:64:65, endln:64:66 |vpiParent: - \_module: work@sky130_fd_sc_hd__macro_sparecell::sky130_fd_sc_hd__nand2_2 (work@sky130_fd_sc_hd__macro_sparecell.nand21), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__macro_sparecell.functional.v, line:64:5, endln:64:82 + \_module_inst: work@sky130_fd_sc_hd__macro_sparecell::sky130_fd_sc_hd__nand2_2 (work@sky130_fd_sc_hd__macro_sparecell.nand21), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__macro_sparecell.functional.v, line:64:5, endln:64:82 |vpiName:Y |vpiHighConn: \_ref_obj: (work@sky130_fd_sc_hd__macro_sparecell.nd2left), line:64:67, endln:64:74 @@ -6009,19 +6009,19 @@ design: (work@sky130_fd_sc_hd__macro_sparecell) |vpiFullName:work@sky130_fd_sc_hd__macro_sparecell.nd2left |vpiActual: \_logic_net: (work@sky130_fd_sc_hd__macro_sparecell.nd2left), line:53:10, endln:53:17 - |vpiModule: - \_module: work@sky130_fd_sc_hd__macro_sparecell::sky130_fd_sc_hd__conb_1 (work@sky130_fd_sc_hd__macro_sparecell.conb0), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__macro_sparecell.functional.v, line:65:5, endln:65:82 + |vpiModuleInst: + \_module_inst: work@sky130_fd_sc_hd__macro_sparecell::sky130_fd_sc_hd__conb_1 (work@sky130_fd_sc_hd__macro_sparecell.conb0), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__macro_sparecell.functional.v, line:65:5, endln:65:82 |vpiParent: - \_module: work@sky130_fd_sc_hd__macro_sparecell (work@sky130_fd_sc_hd__macro_sparecell), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__macro_sparecell.functional.v, line:41:1, endln:68:10 + \_module_inst: work@sky130_fd_sc_hd__macro_sparecell (work@sky130_fd_sc_hd__macro_sparecell), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__macro_sparecell.functional.v, line:41:1, endln:68:10 |vpiName:conb0 |vpiFullName:work@sky130_fd_sc_hd__macro_sparecell.conb0 |vpiDefName:work@sky130_fd_sc_hd__macro_sparecell::sky130_fd_sc_hd__conb_1 |vpiInstance: - \_module: work@sky130_fd_sc_hd__macro_sparecell (work@sky130_fd_sc_hd__macro_sparecell), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__macro_sparecell.functional.v, line:41:1, endln:68:10 + \_module_inst: work@sky130_fd_sc_hd__macro_sparecell (work@sky130_fd_sc_hd__macro_sparecell), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__macro_sparecell.functional.v, line:41:1, endln:68:10 |vpiPort: \_port: (LO), line:65:39, endln:65:41 |vpiParent: - \_module: work@sky130_fd_sc_hd__macro_sparecell::sky130_fd_sc_hd__conb_1 (work@sky130_fd_sc_hd__macro_sparecell.conb0), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__macro_sparecell.functional.v, line:65:5, endln:65:82 + \_module_inst: work@sky130_fd_sc_hd__macro_sparecell::sky130_fd_sc_hd__conb_1 (work@sky130_fd_sc_hd__macro_sparecell.conb0), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__macro_sparecell.functional.v, line:65:5, endln:65:82 |vpiName:LO |vpiHighConn: \_ref_obj: (work@sky130_fd_sc_hd__macro_sparecell.tielo), line:65:42, endln:65:47 @@ -6032,7 +6032,7 @@ design: (work@sky130_fd_sc_hd__macro_sparecell) |vpiPort: \_port: (HI), line:65:54, endln:65:56 |vpiParent: - \_module: work@sky130_fd_sc_hd__macro_sparecell::sky130_fd_sc_hd__conb_1 (work@sky130_fd_sc_hd__macro_sparecell.conb0), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__macro_sparecell.functional.v, line:65:5, endln:65:82 + \_module_inst: work@sky130_fd_sc_hd__macro_sparecell::sky130_fd_sc_hd__conb_1 (work@sky130_fd_sc_hd__macro_sparecell.conb0), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__macro_sparecell.functional.v, line:65:5, endln:65:82 |vpiName:HI |vpiHighConn: \_ref_obj: (work@sky130_fd_sc_hd__macro_sparecell.net7), line:65:57, endln:65:61 @@ -6043,7 +6043,7 @@ design: (work@sky130_fd_sc_hd__macro_sparecell) |vpiPrimitive: \_gate: work@buf (work@sky130_fd_sc_hd__macro_sparecell.buf0), line:66:30, endln:66:81 |vpiParent: - \_module: work@sky130_fd_sc_hd__macro_sparecell (work@sky130_fd_sc_hd__macro_sparecell), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__macro_sparecell.functional.v, line:41:1, endln:68:10 + \_module_inst: work@sky130_fd_sc_hd__macro_sparecell (work@sky130_fd_sc_hd__macro_sparecell), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__macro_sparecell.functional.v, line:41:1, endln:68:10 |vpiDefName:work@buf |vpiName:buf0 |vpiFullName:work@sky130_fd_sc_hd__macro_sparecell.buf0 @@ -6086,13 +6086,13 @@ Processing: -cd cells/cells -DUNIT_DELAY -writepp -parse -nocache -nobuiltin -no design: (work@sky130_fd_sc_hd__tapvgnd) |vpiName:work@sky130_fd_sc_hd__tapvgnd |uhdmallModules: -\_module: work@sky130_fd_sc_hd__tapvgnd (work@sky130_fd_sc_hd__tapvgnd), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__tapvgnd.functional.v, line:34:1, endln:36:10 +\_module_inst: work@sky130_fd_sc_hd__tapvgnd (work@sky130_fd_sc_hd__tapvgnd), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__tapvgnd.functional.v, line:34:1, endln:36:10 |vpiParent: \_design: (work@sky130_fd_sc_hd__tapvgnd) |vpiFullName:work@sky130_fd_sc_hd__tapvgnd |vpiDefName:work@sky130_fd_sc_hd__tapvgnd |uhdmtopModules: -\_module: work@sky130_fd_sc_hd__tapvgnd (work@sky130_fd_sc_hd__tapvgnd), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__tapvgnd.functional.v, line:34:1, endln:36:10 +\_module_inst: work@sky130_fd_sc_hd__tapvgnd (work@sky130_fd_sc_hd__tapvgnd), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__tapvgnd.functional.v, line:34:1, endln:36:10 |vpiName:work@sky130_fd_sc_hd__tapvgnd |vpiDefName:work@sky130_fd_sc_hd__tapvgnd |vpiTop:1 @@ -6108,7 +6108,7 @@ Processing: -cd cells/cells -DUNIT_DELAY -writepp -parse -nocache -nobuiltin -no design: (work@sky130_fd_sc_hd__inv) |vpiName:work@sky130_fd_sc_hd__inv |uhdmallModules: -\_module: work@sky130_fd_sc_hd__inv (work@sky130_fd_sc_hd__inv), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__inv.functional.v, line:33:1, endln:49:10 +\_module_inst: work@sky130_fd_sc_hd__inv (work@sky130_fd_sc_hd__inv), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__inv.functional.v, line:33:1, endln:49:10 |vpiParent: \_design: (work@sky130_fd_sc_hd__inv) |vpiFullName:work@sky130_fd_sc_hd__inv @@ -6116,26 +6116,26 @@ design: (work@sky130_fd_sc_hd__inv) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__inv.not0_out_Y), line:43:10, endln:43:20 |vpiParent: - \_module: work@sky130_fd_sc_hd__inv (work@sky130_fd_sc_hd__inv), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__inv.functional.v, line:33:1, endln:49:10 + \_module_inst: work@sky130_fd_sc_hd__inv (work@sky130_fd_sc_hd__inv), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__inv.functional.v, line:33:1, endln:49:10 |vpiName:not0_out_Y |vpiFullName:work@sky130_fd_sc_hd__inv.not0_out_Y |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__inv.Y), line:34:5, endln:34:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__inv (work@sky130_fd_sc_hd__inv), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__inv.functional.v, line:33:1, endln:49:10 + \_module_inst: work@sky130_fd_sc_hd__inv (work@sky130_fd_sc_hd__inv), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__inv.functional.v, line:33:1, endln:49:10 |vpiName:Y |vpiFullName:work@sky130_fd_sc_hd__inv.Y |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__inv.A), line:35:5, endln:35:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__inv (work@sky130_fd_sc_hd__inv), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__inv.functional.v, line:33:1, endln:49:10 + \_module_inst: work@sky130_fd_sc_hd__inv (work@sky130_fd_sc_hd__inv), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__inv.functional.v, line:33:1, endln:49:10 |vpiName:A |vpiFullName:work@sky130_fd_sc_hd__inv.A |vpiPort: \_port: (Y), line:34:5, endln:34:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__inv (work@sky130_fd_sc_hd__inv), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__inv.functional.v, line:33:1, endln:49:10 + \_module_inst: work@sky130_fd_sc_hd__inv (work@sky130_fd_sc_hd__inv), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__inv.functional.v, line:33:1, endln:49:10 |vpiName:Y |vpiDirection:2 |vpiLowConn: @@ -6147,7 +6147,7 @@ design: (work@sky130_fd_sc_hd__inv) |vpiPort: \_port: (A), line:35:5, endln:35:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__inv (work@sky130_fd_sc_hd__inv), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__inv.functional.v, line:33:1, endln:49:10 + \_module_inst: work@sky130_fd_sc_hd__inv (work@sky130_fd_sc_hd__inv), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__inv.functional.v, line:33:1, endln:49:10 |vpiName:A |vpiDirection:1 |vpiLowConn: @@ -6157,14 +6157,14 @@ design: (work@sky130_fd_sc_hd__inv) |vpiTypedef: \_logic_typespec: , line:40:12, endln:40:12 |uhdmtopModules: -\_module: work@sky130_fd_sc_hd__inv (work@sky130_fd_sc_hd__inv), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__inv.functional.v, line:33:1, endln:49:10 +\_module_inst: work@sky130_fd_sc_hd__inv (work@sky130_fd_sc_hd__inv), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__inv.functional.v, line:33:1, endln:49:10 |vpiName:work@sky130_fd_sc_hd__inv |vpiDefName:work@sky130_fd_sc_hd__inv |vpiTop:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__inv.not0_out_Y), line:43:10, endln:43:20 |vpiParent: - \_module: work@sky130_fd_sc_hd__inv (work@sky130_fd_sc_hd__inv), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__inv.functional.v, line:33:1, endln:49:10 + \_module_inst: work@sky130_fd_sc_hd__inv (work@sky130_fd_sc_hd__inv), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__inv.functional.v, line:33:1, endln:49:10 |vpiTypespec: \_logic_typespec: , line:43:5, endln:43:9 |vpiName:not0_out_Y @@ -6173,7 +6173,7 @@ design: (work@sky130_fd_sc_hd__inv) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__inv.Y), line:34:5, endln:34:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__inv (work@sky130_fd_sc_hd__inv), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__inv.functional.v, line:33:1, endln:49:10 + \_module_inst: work@sky130_fd_sc_hd__inv (work@sky130_fd_sc_hd__inv), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__inv.functional.v, line:33:1, endln:49:10 |vpiTypespec: \_logic_typespec: , line:39:12, endln:39:12 |vpiName:Y @@ -6181,7 +6181,7 @@ design: (work@sky130_fd_sc_hd__inv) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__inv.A), line:35:5, endln:35:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__inv (work@sky130_fd_sc_hd__inv), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__inv.functional.v, line:33:1, endln:49:10 + \_module_inst: work@sky130_fd_sc_hd__inv (work@sky130_fd_sc_hd__inv), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__inv.functional.v, line:33:1, endln:49:10 |vpiTypespec: \_logic_typespec: , line:40:12, endln:40:12 |vpiName:A @@ -6190,7 +6190,7 @@ design: (work@sky130_fd_sc_hd__inv) |vpiPort: \_port: (Y), line:34:5, endln:34:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__inv (work@sky130_fd_sc_hd__inv), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__inv.functional.v, line:33:1, endln:49:10 + \_module_inst: work@sky130_fd_sc_hd__inv (work@sky130_fd_sc_hd__inv), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__inv.functional.v, line:33:1, endln:49:10 |vpiName:Y |vpiDirection:2 |vpiLowConn: @@ -6204,7 +6204,7 @@ design: (work@sky130_fd_sc_hd__inv) |vpiPort: \_port: (A), line:35:5, endln:35:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__inv (work@sky130_fd_sc_hd__inv), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__inv.functional.v, line:33:1, endln:49:10 + \_module_inst: work@sky130_fd_sc_hd__inv (work@sky130_fd_sc_hd__inv), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__inv.functional.v, line:33:1, endln:49:10 |vpiName:A |vpiDirection:1 |vpiLowConn: @@ -6218,7 +6218,7 @@ design: (work@sky130_fd_sc_hd__inv) |vpiPrimitive: \_gate: work@not (work@sky130_fd_sc_hd__inv.not0), line:46:9, endln:46:43 |vpiParent: - \_module: work@sky130_fd_sc_hd__inv (work@sky130_fd_sc_hd__inv), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__inv.functional.v, line:33:1, endln:49:10 + \_module_inst: work@sky130_fd_sc_hd__inv (work@sky130_fd_sc_hd__inv), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__inv.functional.v, line:33:1, endln:49:10 |vpiDefName:work@not |vpiName:not0 |vpiFullName:work@sky130_fd_sc_hd__inv.not0 @@ -6253,7 +6253,7 @@ design: (work@sky130_fd_sc_hd__inv) |vpiPrimitive: \_gate: work@buf (work@sky130_fd_sc_hd__inv.buf0), line:47:9, endln:47:43 |vpiParent: - \_module: work@sky130_fd_sc_hd__inv (work@sky130_fd_sc_hd__inv), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__inv.functional.v, line:33:1, endln:49:10 + \_module_inst: work@sky130_fd_sc_hd__inv (work@sky130_fd_sc_hd__inv), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__inv.functional.v, line:33:1, endln:49:10 |vpiDefName:work@buf |vpiName:buf0 |vpiFullName:work@sky130_fd_sc_hd__inv.buf0 @@ -6296,7 +6296,7 @@ Processing: -cd cells/cells -DUNIT_DELAY -writepp -parse -nocache -nobuiltin -no design: (work@sky130_fd_sc_hd__lpflow_isobufsrc) |vpiName:work@sky130_fd_sc_hd__lpflow_isobufsrc |uhdmallModules: -\_module: work@sky130_fd_sc_hd__lpflow_isobufsrc (work@sky130_fd_sc_hd__lpflow_isobufsrc), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_isobufsrc.functional.v, line:35:1, endln:55:10 +\_module_inst: work@sky130_fd_sc_hd__lpflow_isobufsrc (work@sky130_fd_sc_hd__lpflow_isobufsrc), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_isobufsrc.functional.v, line:35:1, endln:55:10 |vpiParent: \_design: (work@sky130_fd_sc_hd__lpflow_isobufsrc) |vpiFullName:work@sky130_fd_sc_hd__lpflow_isobufsrc @@ -6304,39 +6304,39 @@ design: (work@sky130_fd_sc_hd__lpflow_isobufsrc) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__lpflow_isobufsrc.not0_out), line:47:10, endln:47:18 |vpiParent: - \_module: work@sky130_fd_sc_hd__lpflow_isobufsrc (work@sky130_fd_sc_hd__lpflow_isobufsrc), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_isobufsrc.functional.v, line:35:1, endln:55:10 + \_module_inst: work@sky130_fd_sc_hd__lpflow_isobufsrc (work@sky130_fd_sc_hd__lpflow_isobufsrc), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_isobufsrc.functional.v, line:35:1, endln:55:10 |vpiName:not0_out |vpiFullName:work@sky130_fd_sc_hd__lpflow_isobufsrc.not0_out |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__lpflow_isobufsrc.and0_out_X), line:48:10, endln:48:20 |vpiParent: - \_module: work@sky130_fd_sc_hd__lpflow_isobufsrc (work@sky130_fd_sc_hd__lpflow_isobufsrc), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_isobufsrc.functional.v, line:35:1, endln:55:10 + \_module_inst: work@sky130_fd_sc_hd__lpflow_isobufsrc (work@sky130_fd_sc_hd__lpflow_isobufsrc), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_isobufsrc.functional.v, line:35:1, endln:55:10 |vpiName:and0_out_X |vpiFullName:work@sky130_fd_sc_hd__lpflow_isobufsrc.and0_out_X |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__lpflow_isobufsrc.X), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__lpflow_isobufsrc (work@sky130_fd_sc_hd__lpflow_isobufsrc), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_isobufsrc.functional.v, line:35:1, endln:55:10 + \_module_inst: work@sky130_fd_sc_hd__lpflow_isobufsrc (work@sky130_fd_sc_hd__lpflow_isobufsrc), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_isobufsrc.functional.v, line:35:1, endln:55:10 |vpiName:X |vpiFullName:work@sky130_fd_sc_hd__lpflow_isobufsrc.X |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__lpflow_isobufsrc.SLEEP), line:37:5, endln:37:10 |vpiParent: - \_module: work@sky130_fd_sc_hd__lpflow_isobufsrc (work@sky130_fd_sc_hd__lpflow_isobufsrc), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_isobufsrc.functional.v, line:35:1, endln:55:10 + \_module_inst: work@sky130_fd_sc_hd__lpflow_isobufsrc (work@sky130_fd_sc_hd__lpflow_isobufsrc), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_isobufsrc.functional.v, line:35:1, endln:55:10 |vpiName:SLEEP |vpiFullName:work@sky130_fd_sc_hd__lpflow_isobufsrc.SLEEP |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__lpflow_isobufsrc.A), line:38:5, endln:38:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__lpflow_isobufsrc (work@sky130_fd_sc_hd__lpflow_isobufsrc), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_isobufsrc.functional.v, line:35:1, endln:55:10 + \_module_inst: work@sky130_fd_sc_hd__lpflow_isobufsrc (work@sky130_fd_sc_hd__lpflow_isobufsrc), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_isobufsrc.functional.v, line:35:1, endln:55:10 |vpiName:A |vpiFullName:work@sky130_fd_sc_hd__lpflow_isobufsrc.A |vpiPort: \_port: (X), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__lpflow_isobufsrc (work@sky130_fd_sc_hd__lpflow_isobufsrc), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_isobufsrc.functional.v, line:35:1, endln:55:10 + \_module_inst: work@sky130_fd_sc_hd__lpflow_isobufsrc (work@sky130_fd_sc_hd__lpflow_isobufsrc), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_isobufsrc.functional.v, line:35:1, endln:55:10 |vpiName:X |vpiDirection:2 |vpiLowConn: @@ -6348,7 +6348,7 @@ design: (work@sky130_fd_sc_hd__lpflow_isobufsrc) |vpiPort: \_port: (SLEEP), line:37:5, endln:37:10 |vpiParent: - \_module: work@sky130_fd_sc_hd__lpflow_isobufsrc (work@sky130_fd_sc_hd__lpflow_isobufsrc), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_isobufsrc.functional.v, line:35:1, endln:55:10 + \_module_inst: work@sky130_fd_sc_hd__lpflow_isobufsrc (work@sky130_fd_sc_hd__lpflow_isobufsrc), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_isobufsrc.functional.v, line:35:1, endln:55:10 |vpiName:SLEEP |vpiDirection:1 |vpiLowConn: @@ -6360,7 +6360,7 @@ design: (work@sky130_fd_sc_hd__lpflow_isobufsrc) |vpiPort: \_port: (A), line:38:5, endln:38:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__lpflow_isobufsrc (work@sky130_fd_sc_hd__lpflow_isobufsrc), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_isobufsrc.functional.v, line:35:1, endln:55:10 + \_module_inst: work@sky130_fd_sc_hd__lpflow_isobufsrc (work@sky130_fd_sc_hd__lpflow_isobufsrc), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_isobufsrc.functional.v, line:35:1, endln:55:10 |vpiName:A |vpiDirection:1 |vpiLowConn: @@ -6370,14 +6370,14 @@ design: (work@sky130_fd_sc_hd__lpflow_isobufsrc) |vpiTypedef: \_logic_typespec: , line:44:12, endln:44:12 |uhdmtopModules: -\_module: work@sky130_fd_sc_hd__lpflow_isobufsrc (work@sky130_fd_sc_hd__lpflow_isobufsrc), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_isobufsrc.functional.v, line:35:1, endln:55:10 +\_module_inst: work@sky130_fd_sc_hd__lpflow_isobufsrc (work@sky130_fd_sc_hd__lpflow_isobufsrc), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_isobufsrc.functional.v, line:35:1, endln:55:10 |vpiName:work@sky130_fd_sc_hd__lpflow_isobufsrc |vpiDefName:work@sky130_fd_sc_hd__lpflow_isobufsrc |vpiTop:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__lpflow_isobufsrc.not0_out), line:47:10, endln:47:18 |vpiParent: - \_module: work@sky130_fd_sc_hd__lpflow_isobufsrc (work@sky130_fd_sc_hd__lpflow_isobufsrc), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_isobufsrc.functional.v, line:35:1, endln:55:10 + \_module_inst: work@sky130_fd_sc_hd__lpflow_isobufsrc (work@sky130_fd_sc_hd__lpflow_isobufsrc), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_isobufsrc.functional.v, line:35:1, endln:55:10 |vpiTypespec: \_logic_typespec: , line:47:5, endln:47:9 |vpiName:not0_out @@ -6386,7 +6386,7 @@ design: (work@sky130_fd_sc_hd__lpflow_isobufsrc) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__lpflow_isobufsrc.and0_out_X), line:48:10, endln:48:20 |vpiParent: - \_module: work@sky130_fd_sc_hd__lpflow_isobufsrc (work@sky130_fd_sc_hd__lpflow_isobufsrc), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_isobufsrc.functional.v, line:35:1, endln:55:10 + \_module_inst: work@sky130_fd_sc_hd__lpflow_isobufsrc (work@sky130_fd_sc_hd__lpflow_isobufsrc), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_isobufsrc.functional.v, line:35:1, endln:55:10 |vpiTypespec: \_logic_typespec: , line:48:5, endln:48:9 |vpiName:and0_out_X @@ -6395,7 +6395,7 @@ design: (work@sky130_fd_sc_hd__lpflow_isobufsrc) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__lpflow_isobufsrc.X), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__lpflow_isobufsrc (work@sky130_fd_sc_hd__lpflow_isobufsrc), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_isobufsrc.functional.v, line:35:1, endln:55:10 + \_module_inst: work@sky130_fd_sc_hd__lpflow_isobufsrc (work@sky130_fd_sc_hd__lpflow_isobufsrc), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_isobufsrc.functional.v, line:35:1, endln:55:10 |vpiTypespec: \_logic_typespec: , line:42:12, endln:42:12 |vpiName:X @@ -6403,7 +6403,7 @@ design: (work@sky130_fd_sc_hd__lpflow_isobufsrc) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__lpflow_isobufsrc.SLEEP), line:37:5, endln:37:10 |vpiParent: - \_module: work@sky130_fd_sc_hd__lpflow_isobufsrc (work@sky130_fd_sc_hd__lpflow_isobufsrc), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_isobufsrc.functional.v, line:35:1, endln:55:10 + \_module_inst: work@sky130_fd_sc_hd__lpflow_isobufsrc (work@sky130_fd_sc_hd__lpflow_isobufsrc), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_isobufsrc.functional.v, line:35:1, endln:55:10 |vpiTypespec: \_logic_typespec: , line:43:12, endln:43:12 |vpiName:SLEEP @@ -6411,7 +6411,7 @@ design: (work@sky130_fd_sc_hd__lpflow_isobufsrc) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__lpflow_isobufsrc.A), line:38:5, endln:38:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__lpflow_isobufsrc (work@sky130_fd_sc_hd__lpflow_isobufsrc), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_isobufsrc.functional.v, line:35:1, endln:55:10 + \_module_inst: work@sky130_fd_sc_hd__lpflow_isobufsrc (work@sky130_fd_sc_hd__lpflow_isobufsrc), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_isobufsrc.functional.v, line:35:1, endln:55:10 |vpiTypespec: \_logic_typespec: , line:44:12, endln:44:12 |vpiName:A @@ -6420,7 +6420,7 @@ design: (work@sky130_fd_sc_hd__lpflow_isobufsrc) |vpiPort: \_port: (X), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__lpflow_isobufsrc (work@sky130_fd_sc_hd__lpflow_isobufsrc), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_isobufsrc.functional.v, line:35:1, endln:55:10 + \_module_inst: work@sky130_fd_sc_hd__lpflow_isobufsrc (work@sky130_fd_sc_hd__lpflow_isobufsrc), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_isobufsrc.functional.v, line:35:1, endln:55:10 |vpiName:X |vpiDirection:2 |vpiLowConn: @@ -6434,7 +6434,7 @@ design: (work@sky130_fd_sc_hd__lpflow_isobufsrc) |vpiPort: \_port: (SLEEP), line:37:5, endln:37:10 |vpiParent: - \_module: work@sky130_fd_sc_hd__lpflow_isobufsrc (work@sky130_fd_sc_hd__lpflow_isobufsrc), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_isobufsrc.functional.v, line:35:1, endln:55:10 + \_module_inst: work@sky130_fd_sc_hd__lpflow_isobufsrc (work@sky130_fd_sc_hd__lpflow_isobufsrc), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_isobufsrc.functional.v, line:35:1, endln:55:10 |vpiName:SLEEP |vpiDirection:1 |vpiLowConn: @@ -6448,7 +6448,7 @@ design: (work@sky130_fd_sc_hd__lpflow_isobufsrc) |vpiPort: \_port: (A), line:38:5, endln:38:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__lpflow_isobufsrc (work@sky130_fd_sc_hd__lpflow_isobufsrc), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_isobufsrc.functional.v, line:35:1, endln:55:10 + \_module_inst: work@sky130_fd_sc_hd__lpflow_isobufsrc (work@sky130_fd_sc_hd__lpflow_isobufsrc), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_isobufsrc.functional.v, line:35:1, endln:55:10 |vpiName:A |vpiDirection:1 |vpiLowConn: @@ -6462,7 +6462,7 @@ design: (work@sky130_fd_sc_hd__lpflow_isobufsrc) |vpiPrimitive: \_gate: work@not (work@sky130_fd_sc_hd__lpflow_isobufsrc.not0), line:51:9, endln:51:43 |vpiParent: - \_module: work@sky130_fd_sc_hd__lpflow_isobufsrc (work@sky130_fd_sc_hd__lpflow_isobufsrc), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_isobufsrc.functional.v, line:35:1, endln:55:10 + \_module_inst: work@sky130_fd_sc_hd__lpflow_isobufsrc (work@sky130_fd_sc_hd__lpflow_isobufsrc), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_isobufsrc.functional.v, line:35:1, endln:55:10 |vpiDefName:work@not |vpiName:not0 |vpiFullName:work@sky130_fd_sc_hd__lpflow_isobufsrc.not0 @@ -6497,7 +6497,7 @@ design: (work@sky130_fd_sc_hd__lpflow_isobufsrc) |vpiPrimitive: \_gate: work@and (work@sky130_fd_sc_hd__lpflow_isobufsrc.and0), line:52:9, endln:52:43 |vpiParent: - \_module: work@sky130_fd_sc_hd__lpflow_isobufsrc (work@sky130_fd_sc_hd__lpflow_isobufsrc), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_isobufsrc.functional.v, line:35:1, endln:55:10 + \_module_inst: work@sky130_fd_sc_hd__lpflow_isobufsrc (work@sky130_fd_sc_hd__lpflow_isobufsrc), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_isobufsrc.functional.v, line:35:1, endln:55:10 |vpiDefName:work@and |vpiName:and0 |vpiFullName:work@sky130_fd_sc_hd__lpflow_isobufsrc.and0 @@ -6546,7 +6546,7 @@ design: (work@sky130_fd_sc_hd__lpflow_isobufsrc) |vpiPrimitive: \_gate: work@buf (work@sky130_fd_sc_hd__lpflow_isobufsrc.buf0), line:53:9, endln:53:43 |vpiParent: - \_module: work@sky130_fd_sc_hd__lpflow_isobufsrc (work@sky130_fd_sc_hd__lpflow_isobufsrc), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_isobufsrc.functional.v, line:35:1, endln:55:10 + \_module_inst: work@sky130_fd_sc_hd__lpflow_isobufsrc (work@sky130_fd_sc_hd__lpflow_isobufsrc), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_isobufsrc.functional.v, line:35:1, endln:55:10 |vpiDefName:work@buf |vpiName:buf0 |vpiFullName:work@sky130_fd_sc_hd__lpflow_isobufsrc.buf0 @@ -6589,7 +6589,7 @@ Processing: -cd cells/cells -DUNIT_DELAY -writepp -parse -nocache -nobuiltin -no design: (work@sky130_fd_sc_hd__clkinvlp) |vpiName:work@sky130_fd_sc_hd__clkinvlp |uhdmallModules: -\_module: work@sky130_fd_sc_hd__clkinvlp (work@sky130_fd_sc_hd__clkinvlp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__clkinvlp.functional.v, line:33:1, endln:49:10 +\_module_inst: work@sky130_fd_sc_hd__clkinvlp (work@sky130_fd_sc_hd__clkinvlp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__clkinvlp.functional.v, line:33:1, endln:49:10 |vpiParent: \_design: (work@sky130_fd_sc_hd__clkinvlp) |vpiFullName:work@sky130_fd_sc_hd__clkinvlp @@ -6597,26 +6597,26 @@ design: (work@sky130_fd_sc_hd__clkinvlp) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__clkinvlp.not0_out_Y), line:43:10, endln:43:20 |vpiParent: - \_module: work@sky130_fd_sc_hd__clkinvlp (work@sky130_fd_sc_hd__clkinvlp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__clkinvlp.functional.v, line:33:1, endln:49:10 + \_module_inst: work@sky130_fd_sc_hd__clkinvlp (work@sky130_fd_sc_hd__clkinvlp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__clkinvlp.functional.v, line:33:1, endln:49:10 |vpiName:not0_out_Y |vpiFullName:work@sky130_fd_sc_hd__clkinvlp.not0_out_Y |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__clkinvlp.Y), line:34:5, endln:34:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__clkinvlp (work@sky130_fd_sc_hd__clkinvlp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__clkinvlp.functional.v, line:33:1, endln:49:10 + \_module_inst: work@sky130_fd_sc_hd__clkinvlp (work@sky130_fd_sc_hd__clkinvlp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__clkinvlp.functional.v, line:33:1, endln:49:10 |vpiName:Y |vpiFullName:work@sky130_fd_sc_hd__clkinvlp.Y |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__clkinvlp.A), line:35:5, endln:35:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__clkinvlp (work@sky130_fd_sc_hd__clkinvlp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__clkinvlp.functional.v, line:33:1, endln:49:10 + \_module_inst: work@sky130_fd_sc_hd__clkinvlp (work@sky130_fd_sc_hd__clkinvlp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__clkinvlp.functional.v, line:33:1, endln:49:10 |vpiName:A |vpiFullName:work@sky130_fd_sc_hd__clkinvlp.A |vpiPort: \_port: (Y), line:34:5, endln:34:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__clkinvlp (work@sky130_fd_sc_hd__clkinvlp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__clkinvlp.functional.v, line:33:1, endln:49:10 + \_module_inst: work@sky130_fd_sc_hd__clkinvlp (work@sky130_fd_sc_hd__clkinvlp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__clkinvlp.functional.v, line:33:1, endln:49:10 |vpiName:Y |vpiDirection:2 |vpiLowConn: @@ -6628,7 +6628,7 @@ design: (work@sky130_fd_sc_hd__clkinvlp) |vpiPort: \_port: (A), line:35:5, endln:35:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__clkinvlp (work@sky130_fd_sc_hd__clkinvlp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__clkinvlp.functional.v, line:33:1, endln:49:10 + \_module_inst: work@sky130_fd_sc_hd__clkinvlp (work@sky130_fd_sc_hd__clkinvlp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__clkinvlp.functional.v, line:33:1, endln:49:10 |vpiName:A |vpiDirection:1 |vpiLowConn: @@ -6638,14 +6638,14 @@ design: (work@sky130_fd_sc_hd__clkinvlp) |vpiTypedef: \_logic_typespec: , line:40:12, endln:40:12 |uhdmtopModules: -\_module: work@sky130_fd_sc_hd__clkinvlp (work@sky130_fd_sc_hd__clkinvlp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__clkinvlp.functional.v, line:33:1, endln:49:10 +\_module_inst: work@sky130_fd_sc_hd__clkinvlp (work@sky130_fd_sc_hd__clkinvlp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__clkinvlp.functional.v, line:33:1, endln:49:10 |vpiName:work@sky130_fd_sc_hd__clkinvlp |vpiDefName:work@sky130_fd_sc_hd__clkinvlp |vpiTop:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__clkinvlp.not0_out_Y), line:43:10, endln:43:20 |vpiParent: - \_module: work@sky130_fd_sc_hd__clkinvlp (work@sky130_fd_sc_hd__clkinvlp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__clkinvlp.functional.v, line:33:1, endln:49:10 + \_module_inst: work@sky130_fd_sc_hd__clkinvlp (work@sky130_fd_sc_hd__clkinvlp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__clkinvlp.functional.v, line:33:1, endln:49:10 |vpiTypespec: \_logic_typespec: , line:43:5, endln:43:9 |vpiName:not0_out_Y @@ -6654,7 +6654,7 @@ design: (work@sky130_fd_sc_hd__clkinvlp) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__clkinvlp.Y), line:34:5, endln:34:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__clkinvlp (work@sky130_fd_sc_hd__clkinvlp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__clkinvlp.functional.v, line:33:1, endln:49:10 + \_module_inst: work@sky130_fd_sc_hd__clkinvlp (work@sky130_fd_sc_hd__clkinvlp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__clkinvlp.functional.v, line:33:1, endln:49:10 |vpiTypespec: \_logic_typespec: , line:39:12, endln:39:12 |vpiName:Y @@ -6662,7 +6662,7 @@ design: (work@sky130_fd_sc_hd__clkinvlp) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__clkinvlp.A), line:35:5, endln:35:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__clkinvlp (work@sky130_fd_sc_hd__clkinvlp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__clkinvlp.functional.v, line:33:1, endln:49:10 + \_module_inst: work@sky130_fd_sc_hd__clkinvlp (work@sky130_fd_sc_hd__clkinvlp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__clkinvlp.functional.v, line:33:1, endln:49:10 |vpiTypespec: \_logic_typespec: , line:40:12, endln:40:12 |vpiName:A @@ -6671,7 +6671,7 @@ design: (work@sky130_fd_sc_hd__clkinvlp) |vpiPort: \_port: (Y), line:34:5, endln:34:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__clkinvlp (work@sky130_fd_sc_hd__clkinvlp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__clkinvlp.functional.v, line:33:1, endln:49:10 + \_module_inst: work@sky130_fd_sc_hd__clkinvlp (work@sky130_fd_sc_hd__clkinvlp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__clkinvlp.functional.v, line:33:1, endln:49:10 |vpiName:Y |vpiDirection:2 |vpiLowConn: @@ -6685,7 +6685,7 @@ design: (work@sky130_fd_sc_hd__clkinvlp) |vpiPort: \_port: (A), line:35:5, endln:35:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__clkinvlp (work@sky130_fd_sc_hd__clkinvlp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__clkinvlp.functional.v, line:33:1, endln:49:10 + \_module_inst: work@sky130_fd_sc_hd__clkinvlp (work@sky130_fd_sc_hd__clkinvlp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__clkinvlp.functional.v, line:33:1, endln:49:10 |vpiName:A |vpiDirection:1 |vpiLowConn: @@ -6699,7 +6699,7 @@ design: (work@sky130_fd_sc_hd__clkinvlp) |vpiPrimitive: \_gate: work@not (work@sky130_fd_sc_hd__clkinvlp.not0), line:46:9, endln:46:43 |vpiParent: - \_module: work@sky130_fd_sc_hd__clkinvlp (work@sky130_fd_sc_hd__clkinvlp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__clkinvlp.functional.v, line:33:1, endln:49:10 + \_module_inst: work@sky130_fd_sc_hd__clkinvlp (work@sky130_fd_sc_hd__clkinvlp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__clkinvlp.functional.v, line:33:1, endln:49:10 |vpiDefName:work@not |vpiName:not0 |vpiFullName:work@sky130_fd_sc_hd__clkinvlp.not0 @@ -6734,7 +6734,7 @@ design: (work@sky130_fd_sc_hd__clkinvlp) |vpiPrimitive: \_gate: work@buf (work@sky130_fd_sc_hd__clkinvlp.buf0), line:47:9, endln:47:43 |vpiParent: - \_module: work@sky130_fd_sc_hd__clkinvlp (work@sky130_fd_sc_hd__clkinvlp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__clkinvlp.functional.v, line:33:1, endln:49:10 + \_module_inst: work@sky130_fd_sc_hd__clkinvlp (work@sky130_fd_sc_hd__clkinvlp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__clkinvlp.functional.v, line:33:1, endln:49:10 |vpiDefName:work@buf |vpiName:buf0 |vpiFullName:work@sky130_fd_sc_hd__clkinvlp.buf0 @@ -6777,7 +6777,7 @@ Processing: -cd cells/cells -DUNIT_DELAY -writepp -parse -nocache -nobuiltin -no design: (work@sky130_fd_sc_hd__bufinv) |vpiName:work@sky130_fd_sc_hd__bufinv |uhdmallModules: -\_module: work@sky130_fd_sc_hd__bufinv (work@sky130_fd_sc_hd__bufinv), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__bufinv.functional.v, line:33:1, endln:49:10 +\_module_inst: work@sky130_fd_sc_hd__bufinv (work@sky130_fd_sc_hd__bufinv), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__bufinv.functional.v, line:33:1, endln:49:10 |vpiParent: \_design: (work@sky130_fd_sc_hd__bufinv) |vpiFullName:work@sky130_fd_sc_hd__bufinv @@ -6785,26 +6785,26 @@ design: (work@sky130_fd_sc_hd__bufinv) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__bufinv.not0_out_Y), line:43:10, endln:43:20 |vpiParent: - \_module: work@sky130_fd_sc_hd__bufinv (work@sky130_fd_sc_hd__bufinv), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__bufinv.functional.v, line:33:1, endln:49:10 + \_module_inst: work@sky130_fd_sc_hd__bufinv (work@sky130_fd_sc_hd__bufinv), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__bufinv.functional.v, line:33:1, endln:49:10 |vpiName:not0_out_Y |vpiFullName:work@sky130_fd_sc_hd__bufinv.not0_out_Y |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__bufinv.Y), line:34:5, endln:34:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__bufinv (work@sky130_fd_sc_hd__bufinv), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__bufinv.functional.v, line:33:1, endln:49:10 + \_module_inst: work@sky130_fd_sc_hd__bufinv (work@sky130_fd_sc_hd__bufinv), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__bufinv.functional.v, line:33:1, endln:49:10 |vpiName:Y |vpiFullName:work@sky130_fd_sc_hd__bufinv.Y |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__bufinv.A), line:35:5, endln:35:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__bufinv (work@sky130_fd_sc_hd__bufinv), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__bufinv.functional.v, line:33:1, endln:49:10 + \_module_inst: work@sky130_fd_sc_hd__bufinv (work@sky130_fd_sc_hd__bufinv), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__bufinv.functional.v, line:33:1, endln:49:10 |vpiName:A |vpiFullName:work@sky130_fd_sc_hd__bufinv.A |vpiPort: \_port: (Y), line:34:5, endln:34:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__bufinv (work@sky130_fd_sc_hd__bufinv), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__bufinv.functional.v, line:33:1, endln:49:10 + \_module_inst: work@sky130_fd_sc_hd__bufinv (work@sky130_fd_sc_hd__bufinv), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__bufinv.functional.v, line:33:1, endln:49:10 |vpiName:Y |vpiDirection:2 |vpiLowConn: @@ -6816,7 +6816,7 @@ design: (work@sky130_fd_sc_hd__bufinv) |vpiPort: \_port: (A), line:35:5, endln:35:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__bufinv (work@sky130_fd_sc_hd__bufinv), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__bufinv.functional.v, line:33:1, endln:49:10 + \_module_inst: work@sky130_fd_sc_hd__bufinv (work@sky130_fd_sc_hd__bufinv), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__bufinv.functional.v, line:33:1, endln:49:10 |vpiName:A |vpiDirection:1 |vpiLowConn: @@ -6826,14 +6826,14 @@ design: (work@sky130_fd_sc_hd__bufinv) |vpiTypedef: \_logic_typespec: , line:40:12, endln:40:12 |uhdmtopModules: -\_module: work@sky130_fd_sc_hd__bufinv (work@sky130_fd_sc_hd__bufinv), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__bufinv.functional.v, line:33:1, endln:49:10 +\_module_inst: work@sky130_fd_sc_hd__bufinv (work@sky130_fd_sc_hd__bufinv), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__bufinv.functional.v, line:33:1, endln:49:10 |vpiName:work@sky130_fd_sc_hd__bufinv |vpiDefName:work@sky130_fd_sc_hd__bufinv |vpiTop:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__bufinv.not0_out_Y), line:43:10, endln:43:20 |vpiParent: - \_module: work@sky130_fd_sc_hd__bufinv (work@sky130_fd_sc_hd__bufinv), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__bufinv.functional.v, line:33:1, endln:49:10 + \_module_inst: work@sky130_fd_sc_hd__bufinv (work@sky130_fd_sc_hd__bufinv), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__bufinv.functional.v, line:33:1, endln:49:10 |vpiTypespec: \_logic_typespec: , line:43:5, endln:43:9 |vpiName:not0_out_Y @@ -6842,7 +6842,7 @@ design: (work@sky130_fd_sc_hd__bufinv) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__bufinv.Y), line:34:5, endln:34:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__bufinv (work@sky130_fd_sc_hd__bufinv), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__bufinv.functional.v, line:33:1, endln:49:10 + \_module_inst: work@sky130_fd_sc_hd__bufinv (work@sky130_fd_sc_hd__bufinv), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__bufinv.functional.v, line:33:1, endln:49:10 |vpiTypespec: \_logic_typespec: , line:39:12, endln:39:12 |vpiName:Y @@ -6850,7 +6850,7 @@ design: (work@sky130_fd_sc_hd__bufinv) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__bufinv.A), line:35:5, endln:35:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__bufinv (work@sky130_fd_sc_hd__bufinv), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__bufinv.functional.v, line:33:1, endln:49:10 + \_module_inst: work@sky130_fd_sc_hd__bufinv (work@sky130_fd_sc_hd__bufinv), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__bufinv.functional.v, line:33:1, endln:49:10 |vpiTypespec: \_logic_typespec: , line:40:12, endln:40:12 |vpiName:A @@ -6859,7 +6859,7 @@ design: (work@sky130_fd_sc_hd__bufinv) |vpiPort: \_port: (Y), line:34:5, endln:34:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__bufinv (work@sky130_fd_sc_hd__bufinv), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__bufinv.functional.v, line:33:1, endln:49:10 + \_module_inst: work@sky130_fd_sc_hd__bufinv (work@sky130_fd_sc_hd__bufinv), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__bufinv.functional.v, line:33:1, endln:49:10 |vpiName:Y |vpiDirection:2 |vpiLowConn: @@ -6873,7 +6873,7 @@ design: (work@sky130_fd_sc_hd__bufinv) |vpiPort: \_port: (A), line:35:5, endln:35:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__bufinv (work@sky130_fd_sc_hd__bufinv), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__bufinv.functional.v, line:33:1, endln:49:10 + \_module_inst: work@sky130_fd_sc_hd__bufinv (work@sky130_fd_sc_hd__bufinv), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__bufinv.functional.v, line:33:1, endln:49:10 |vpiName:A |vpiDirection:1 |vpiLowConn: @@ -6887,7 +6887,7 @@ design: (work@sky130_fd_sc_hd__bufinv) |vpiPrimitive: \_gate: work@not (work@sky130_fd_sc_hd__bufinv.not0), line:46:9, endln:46:43 |vpiParent: - \_module: work@sky130_fd_sc_hd__bufinv (work@sky130_fd_sc_hd__bufinv), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__bufinv.functional.v, line:33:1, endln:49:10 + \_module_inst: work@sky130_fd_sc_hd__bufinv (work@sky130_fd_sc_hd__bufinv), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__bufinv.functional.v, line:33:1, endln:49:10 |vpiDefName:work@not |vpiName:not0 |vpiFullName:work@sky130_fd_sc_hd__bufinv.not0 @@ -6922,7 +6922,7 @@ design: (work@sky130_fd_sc_hd__bufinv) |vpiPrimitive: \_gate: work@buf (work@sky130_fd_sc_hd__bufinv.buf0), line:47:9, endln:47:43 |vpiParent: - \_module: work@sky130_fd_sc_hd__bufinv (work@sky130_fd_sc_hd__bufinv), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__bufinv.functional.v, line:33:1, endln:49:10 + \_module_inst: work@sky130_fd_sc_hd__bufinv (work@sky130_fd_sc_hd__bufinv), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__bufinv.functional.v, line:33:1, endln:49:10 |vpiDefName:work@buf |vpiName:buf0 |vpiFullName:work@sky130_fd_sc_hd__bufinv.buf0 @@ -6965,7 +6965,7 @@ Processing: -cd cells/cells -DUNIT_DELAY -writepp -parse -nocache -nobuiltin -no design: (work@sky130_fd_sc_hd__a32o) |vpiName:work@sky130_fd_sc_hd__a32o |uhdmallModules: -\_module: work@sky130_fd_sc_hd__a32o (work@sky130_fd_sc_hd__a32o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a32o.functional.v, line:36:1, endln:64:10 +\_module_inst: work@sky130_fd_sc_hd__a32o (work@sky130_fd_sc_hd__a32o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a32o.functional.v, line:36:1, endln:64:10 |vpiParent: \_design: (work@sky130_fd_sc_hd__a32o) |vpiFullName:work@sky130_fd_sc_hd__a32o @@ -6973,64 +6973,64 @@ design: (work@sky130_fd_sc_hd__a32o) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a32o.and0_out), line:54:10, endln:54:18 |vpiParent: - \_module: work@sky130_fd_sc_hd__a32o (work@sky130_fd_sc_hd__a32o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a32o.functional.v, line:36:1, endln:64:10 + \_module_inst: work@sky130_fd_sc_hd__a32o (work@sky130_fd_sc_hd__a32o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a32o.functional.v, line:36:1, endln:64:10 |vpiName:and0_out |vpiFullName:work@sky130_fd_sc_hd__a32o.and0_out |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a32o.and1_out), line:55:10, endln:55:18 |vpiParent: - \_module: work@sky130_fd_sc_hd__a32o (work@sky130_fd_sc_hd__a32o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a32o.functional.v, line:36:1, endln:64:10 + \_module_inst: work@sky130_fd_sc_hd__a32o (work@sky130_fd_sc_hd__a32o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a32o.functional.v, line:36:1, endln:64:10 |vpiName:and1_out |vpiFullName:work@sky130_fd_sc_hd__a32o.and1_out |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a32o.or0_out_X), line:56:10, endln:56:19 |vpiParent: - \_module: work@sky130_fd_sc_hd__a32o (work@sky130_fd_sc_hd__a32o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a32o.functional.v, line:36:1, endln:64:10 + \_module_inst: work@sky130_fd_sc_hd__a32o (work@sky130_fd_sc_hd__a32o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a32o.functional.v, line:36:1, endln:64:10 |vpiName:or0_out_X |vpiFullName:work@sky130_fd_sc_hd__a32o.or0_out_X |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a32o.X), line:37:5, endln:37:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__a32o (work@sky130_fd_sc_hd__a32o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a32o.functional.v, line:36:1, endln:64:10 + \_module_inst: work@sky130_fd_sc_hd__a32o (work@sky130_fd_sc_hd__a32o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a32o.functional.v, line:36:1, endln:64:10 |vpiName:X |vpiFullName:work@sky130_fd_sc_hd__a32o.X |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a32o.A1), line:38:5, endln:38:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a32o (work@sky130_fd_sc_hd__a32o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a32o.functional.v, line:36:1, endln:64:10 + \_module_inst: work@sky130_fd_sc_hd__a32o (work@sky130_fd_sc_hd__a32o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a32o.functional.v, line:36:1, endln:64:10 |vpiName:A1 |vpiFullName:work@sky130_fd_sc_hd__a32o.A1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a32o.A2), line:39:5, endln:39:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a32o (work@sky130_fd_sc_hd__a32o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a32o.functional.v, line:36:1, endln:64:10 + \_module_inst: work@sky130_fd_sc_hd__a32o (work@sky130_fd_sc_hd__a32o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a32o.functional.v, line:36:1, endln:64:10 |vpiName:A2 |vpiFullName:work@sky130_fd_sc_hd__a32o.A2 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a32o.A3), line:40:5, endln:40:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a32o (work@sky130_fd_sc_hd__a32o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a32o.functional.v, line:36:1, endln:64:10 + \_module_inst: work@sky130_fd_sc_hd__a32o (work@sky130_fd_sc_hd__a32o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a32o.functional.v, line:36:1, endln:64:10 |vpiName:A3 |vpiFullName:work@sky130_fd_sc_hd__a32o.A3 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a32o.B1), line:41:5, endln:41:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a32o (work@sky130_fd_sc_hd__a32o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a32o.functional.v, line:36:1, endln:64:10 + \_module_inst: work@sky130_fd_sc_hd__a32o (work@sky130_fd_sc_hd__a32o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a32o.functional.v, line:36:1, endln:64:10 |vpiName:B1 |vpiFullName:work@sky130_fd_sc_hd__a32o.B1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a32o.B2), line:42:5, endln:42:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a32o (work@sky130_fd_sc_hd__a32o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a32o.functional.v, line:36:1, endln:64:10 + \_module_inst: work@sky130_fd_sc_hd__a32o (work@sky130_fd_sc_hd__a32o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a32o.functional.v, line:36:1, endln:64:10 |vpiName:B2 |vpiFullName:work@sky130_fd_sc_hd__a32o.B2 |vpiPort: \_port: (X), line:37:5, endln:37:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__a32o (work@sky130_fd_sc_hd__a32o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a32o.functional.v, line:36:1, endln:64:10 + \_module_inst: work@sky130_fd_sc_hd__a32o (work@sky130_fd_sc_hd__a32o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a32o.functional.v, line:36:1, endln:64:10 |vpiName:X |vpiDirection:2 |vpiLowConn: @@ -7042,7 +7042,7 @@ design: (work@sky130_fd_sc_hd__a32o) |vpiPort: \_port: (A1), line:38:5, endln:38:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a32o (work@sky130_fd_sc_hd__a32o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a32o.functional.v, line:36:1, endln:64:10 + \_module_inst: work@sky130_fd_sc_hd__a32o (work@sky130_fd_sc_hd__a32o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a32o.functional.v, line:36:1, endln:64:10 |vpiName:A1 |vpiDirection:1 |vpiLowConn: @@ -7054,7 +7054,7 @@ design: (work@sky130_fd_sc_hd__a32o) |vpiPort: \_port: (A2), line:39:5, endln:39:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a32o (work@sky130_fd_sc_hd__a32o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a32o.functional.v, line:36:1, endln:64:10 + \_module_inst: work@sky130_fd_sc_hd__a32o (work@sky130_fd_sc_hd__a32o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a32o.functional.v, line:36:1, endln:64:10 |vpiName:A2 |vpiDirection:1 |vpiLowConn: @@ -7066,7 +7066,7 @@ design: (work@sky130_fd_sc_hd__a32o) |vpiPort: \_port: (A3), line:40:5, endln:40:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a32o (work@sky130_fd_sc_hd__a32o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a32o.functional.v, line:36:1, endln:64:10 + \_module_inst: work@sky130_fd_sc_hd__a32o (work@sky130_fd_sc_hd__a32o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a32o.functional.v, line:36:1, endln:64:10 |vpiName:A3 |vpiDirection:1 |vpiLowConn: @@ -7078,7 +7078,7 @@ design: (work@sky130_fd_sc_hd__a32o) |vpiPort: \_port: (B1), line:41:5, endln:41:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a32o (work@sky130_fd_sc_hd__a32o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a32o.functional.v, line:36:1, endln:64:10 + \_module_inst: work@sky130_fd_sc_hd__a32o (work@sky130_fd_sc_hd__a32o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a32o.functional.v, line:36:1, endln:64:10 |vpiName:B1 |vpiDirection:1 |vpiLowConn: @@ -7090,7 +7090,7 @@ design: (work@sky130_fd_sc_hd__a32o) |vpiPort: \_port: (B2), line:42:5, endln:42:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a32o (work@sky130_fd_sc_hd__a32o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a32o.functional.v, line:36:1, endln:64:10 + \_module_inst: work@sky130_fd_sc_hd__a32o (work@sky130_fd_sc_hd__a32o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a32o.functional.v, line:36:1, endln:64:10 |vpiName:B2 |vpiDirection:1 |vpiLowConn: @@ -7100,14 +7100,14 @@ design: (work@sky130_fd_sc_hd__a32o) |vpiTypedef: \_logic_typespec: , line:51:12, endln:51:12 |uhdmtopModules: -\_module: work@sky130_fd_sc_hd__a32o (work@sky130_fd_sc_hd__a32o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a32o.functional.v, line:36:1, endln:64:10 +\_module_inst: work@sky130_fd_sc_hd__a32o (work@sky130_fd_sc_hd__a32o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a32o.functional.v, line:36:1, endln:64:10 |vpiName:work@sky130_fd_sc_hd__a32o |vpiDefName:work@sky130_fd_sc_hd__a32o |vpiTop:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a32o.and0_out), line:54:10, endln:54:18 |vpiParent: - \_module: work@sky130_fd_sc_hd__a32o (work@sky130_fd_sc_hd__a32o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a32o.functional.v, line:36:1, endln:64:10 + \_module_inst: work@sky130_fd_sc_hd__a32o (work@sky130_fd_sc_hd__a32o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a32o.functional.v, line:36:1, endln:64:10 |vpiTypespec: \_logic_typespec: , line:54:5, endln:54:9 |vpiName:and0_out @@ -7116,7 +7116,7 @@ design: (work@sky130_fd_sc_hd__a32o) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a32o.and1_out), line:55:10, endln:55:18 |vpiParent: - \_module: work@sky130_fd_sc_hd__a32o (work@sky130_fd_sc_hd__a32o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a32o.functional.v, line:36:1, endln:64:10 + \_module_inst: work@sky130_fd_sc_hd__a32o (work@sky130_fd_sc_hd__a32o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a32o.functional.v, line:36:1, endln:64:10 |vpiTypespec: \_logic_typespec: , line:55:5, endln:55:9 |vpiName:and1_out @@ -7125,7 +7125,7 @@ design: (work@sky130_fd_sc_hd__a32o) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a32o.or0_out_X), line:56:10, endln:56:19 |vpiParent: - \_module: work@sky130_fd_sc_hd__a32o (work@sky130_fd_sc_hd__a32o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a32o.functional.v, line:36:1, endln:64:10 + \_module_inst: work@sky130_fd_sc_hd__a32o (work@sky130_fd_sc_hd__a32o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a32o.functional.v, line:36:1, endln:64:10 |vpiTypespec: \_logic_typespec: , line:56:5, endln:56:9 |vpiName:or0_out_X @@ -7134,7 +7134,7 @@ design: (work@sky130_fd_sc_hd__a32o) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a32o.X), line:37:5, endln:37:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__a32o (work@sky130_fd_sc_hd__a32o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a32o.functional.v, line:36:1, endln:64:10 + \_module_inst: work@sky130_fd_sc_hd__a32o (work@sky130_fd_sc_hd__a32o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a32o.functional.v, line:36:1, endln:64:10 |vpiTypespec: \_logic_typespec: , line:46:12, endln:46:12 |vpiName:X @@ -7142,7 +7142,7 @@ design: (work@sky130_fd_sc_hd__a32o) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a32o.A1), line:38:5, endln:38:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a32o (work@sky130_fd_sc_hd__a32o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a32o.functional.v, line:36:1, endln:64:10 + \_module_inst: work@sky130_fd_sc_hd__a32o (work@sky130_fd_sc_hd__a32o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a32o.functional.v, line:36:1, endln:64:10 |vpiTypespec: \_logic_typespec: , line:47:12, endln:47:12 |vpiName:A1 @@ -7150,7 +7150,7 @@ design: (work@sky130_fd_sc_hd__a32o) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a32o.A2), line:39:5, endln:39:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a32o (work@sky130_fd_sc_hd__a32o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a32o.functional.v, line:36:1, endln:64:10 + \_module_inst: work@sky130_fd_sc_hd__a32o (work@sky130_fd_sc_hd__a32o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a32o.functional.v, line:36:1, endln:64:10 |vpiTypespec: \_logic_typespec: , line:48:12, endln:48:12 |vpiName:A2 @@ -7158,7 +7158,7 @@ design: (work@sky130_fd_sc_hd__a32o) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a32o.A3), line:40:5, endln:40:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a32o (work@sky130_fd_sc_hd__a32o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a32o.functional.v, line:36:1, endln:64:10 + \_module_inst: work@sky130_fd_sc_hd__a32o (work@sky130_fd_sc_hd__a32o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a32o.functional.v, line:36:1, endln:64:10 |vpiTypespec: \_logic_typespec: , line:49:12, endln:49:12 |vpiName:A3 @@ -7166,7 +7166,7 @@ design: (work@sky130_fd_sc_hd__a32o) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a32o.B1), line:41:5, endln:41:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a32o (work@sky130_fd_sc_hd__a32o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a32o.functional.v, line:36:1, endln:64:10 + \_module_inst: work@sky130_fd_sc_hd__a32o (work@sky130_fd_sc_hd__a32o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a32o.functional.v, line:36:1, endln:64:10 |vpiTypespec: \_logic_typespec: , line:50:12, endln:50:12 |vpiName:B1 @@ -7174,7 +7174,7 @@ design: (work@sky130_fd_sc_hd__a32o) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a32o.B2), line:42:5, endln:42:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a32o (work@sky130_fd_sc_hd__a32o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a32o.functional.v, line:36:1, endln:64:10 + \_module_inst: work@sky130_fd_sc_hd__a32o (work@sky130_fd_sc_hd__a32o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a32o.functional.v, line:36:1, endln:64:10 |vpiTypespec: \_logic_typespec: , line:51:12, endln:51:12 |vpiName:B2 @@ -7183,7 +7183,7 @@ design: (work@sky130_fd_sc_hd__a32o) |vpiPort: \_port: (X), line:37:5, endln:37:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__a32o (work@sky130_fd_sc_hd__a32o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a32o.functional.v, line:36:1, endln:64:10 + \_module_inst: work@sky130_fd_sc_hd__a32o (work@sky130_fd_sc_hd__a32o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a32o.functional.v, line:36:1, endln:64:10 |vpiName:X |vpiDirection:2 |vpiLowConn: @@ -7197,7 +7197,7 @@ design: (work@sky130_fd_sc_hd__a32o) |vpiPort: \_port: (A1), line:38:5, endln:38:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a32o (work@sky130_fd_sc_hd__a32o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a32o.functional.v, line:36:1, endln:64:10 + \_module_inst: work@sky130_fd_sc_hd__a32o (work@sky130_fd_sc_hd__a32o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a32o.functional.v, line:36:1, endln:64:10 |vpiName:A1 |vpiDirection:1 |vpiLowConn: @@ -7211,7 +7211,7 @@ design: (work@sky130_fd_sc_hd__a32o) |vpiPort: \_port: (A2), line:39:5, endln:39:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a32o (work@sky130_fd_sc_hd__a32o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a32o.functional.v, line:36:1, endln:64:10 + \_module_inst: work@sky130_fd_sc_hd__a32o (work@sky130_fd_sc_hd__a32o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a32o.functional.v, line:36:1, endln:64:10 |vpiName:A2 |vpiDirection:1 |vpiLowConn: @@ -7225,7 +7225,7 @@ design: (work@sky130_fd_sc_hd__a32o) |vpiPort: \_port: (A3), line:40:5, endln:40:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a32o (work@sky130_fd_sc_hd__a32o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a32o.functional.v, line:36:1, endln:64:10 + \_module_inst: work@sky130_fd_sc_hd__a32o (work@sky130_fd_sc_hd__a32o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a32o.functional.v, line:36:1, endln:64:10 |vpiName:A3 |vpiDirection:1 |vpiLowConn: @@ -7239,7 +7239,7 @@ design: (work@sky130_fd_sc_hd__a32o) |vpiPort: \_port: (B1), line:41:5, endln:41:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a32o (work@sky130_fd_sc_hd__a32o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a32o.functional.v, line:36:1, endln:64:10 + \_module_inst: work@sky130_fd_sc_hd__a32o (work@sky130_fd_sc_hd__a32o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a32o.functional.v, line:36:1, endln:64:10 |vpiName:B1 |vpiDirection:1 |vpiLowConn: @@ -7253,7 +7253,7 @@ design: (work@sky130_fd_sc_hd__a32o) |vpiPort: \_port: (B2), line:42:5, endln:42:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a32o (work@sky130_fd_sc_hd__a32o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a32o.functional.v, line:36:1, endln:64:10 + \_module_inst: work@sky130_fd_sc_hd__a32o (work@sky130_fd_sc_hd__a32o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a32o.functional.v, line:36:1, endln:64:10 |vpiName:B2 |vpiDirection:1 |vpiLowConn: @@ -7267,7 +7267,7 @@ design: (work@sky130_fd_sc_hd__a32o) |vpiPrimitive: \_gate: work@and (work@sky130_fd_sc_hd__a32o.and0), line:59:9, endln:59:45 |vpiParent: - \_module: work@sky130_fd_sc_hd__a32o (work@sky130_fd_sc_hd__a32o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a32o.functional.v, line:36:1, endln:64:10 + \_module_inst: work@sky130_fd_sc_hd__a32o (work@sky130_fd_sc_hd__a32o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a32o.functional.v, line:36:1, endln:64:10 |vpiDefName:work@and |vpiName:and0 |vpiFullName:work@sky130_fd_sc_hd__a32o.and0 @@ -7330,7 +7330,7 @@ design: (work@sky130_fd_sc_hd__a32o) |vpiPrimitive: \_gate: work@and (work@sky130_fd_sc_hd__a32o.and1), line:60:9, endln:60:45 |vpiParent: - \_module: work@sky130_fd_sc_hd__a32o (work@sky130_fd_sc_hd__a32o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a32o.functional.v, line:36:1, endln:64:10 + \_module_inst: work@sky130_fd_sc_hd__a32o (work@sky130_fd_sc_hd__a32o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a32o.functional.v, line:36:1, endln:64:10 |vpiDefName:work@and |vpiName:and1 |vpiFullName:work@sky130_fd_sc_hd__a32o.and1 @@ -7379,7 +7379,7 @@ design: (work@sky130_fd_sc_hd__a32o) |vpiPrimitive: \_gate: work@or (work@sky130_fd_sc_hd__a32o.or0), line:61:9, endln:61:45 |vpiParent: - \_module: work@sky130_fd_sc_hd__a32o (work@sky130_fd_sc_hd__a32o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a32o.functional.v, line:36:1, endln:64:10 + \_module_inst: work@sky130_fd_sc_hd__a32o (work@sky130_fd_sc_hd__a32o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a32o.functional.v, line:36:1, endln:64:10 |vpiDefName:work@or |vpiName:or0 |vpiFullName:work@sky130_fd_sc_hd__a32o.or0 @@ -7428,7 +7428,7 @@ design: (work@sky130_fd_sc_hd__a32o) |vpiPrimitive: \_gate: work@buf (work@sky130_fd_sc_hd__a32o.buf0), line:62:9, endln:62:45 |vpiParent: - \_module: work@sky130_fd_sc_hd__a32o (work@sky130_fd_sc_hd__a32o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a32o.functional.v, line:36:1, endln:64:10 + \_module_inst: work@sky130_fd_sc_hd__a32o (work@sky130_fd_sc_hd__a32o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a32o.functional.v, line:36:1, endln:64:10 |vpiDefName:work@buf |vpiName:buf0 |vpiFullName:work@sky130_fd_sc_hd__a32o.buf0 @@ -7471,7 +7471,7 @@ Processing: -cd cells/cells -DUNIT_DELAY -writepp -parse -nocache -nobuiltin -no design: (work@sky130_fd_sc_hd__fahcon) |vpiName:work@sky130_fd_sc_hd__fahcon |uhdmallModules: -\_module: work@sky130_fd_sc_hd__fahcon (work@sky130_fd_sc_hd__fahcon), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fahcon.functional.v, line:33:1, endln:64:10 +\_module_inst: work@sky130_fd_sc_hd__fahcon (work@sky130_fd_sc_hd__fahcon), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fahcon.functional.v, line:33:1, endln:64:10 |vpiParent: \_design: (work@sky130_fd_sc_hd__fahcon) |vpiFullName:work@sky130_fd_sc_hd__fahcon @@ -7479,72 +7479,72 @@ design: (work@sky130_fd_sc_hd__fahcon) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__fahcon.xor0_out_SUM), line:49:10, endln:49:22 |vpiParent: - \_module: work@sky130_fd_sc_hd__fahcon (work@sky130_fd_sc_hd__fahcon), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fahcon.functional.v, line:33:1, endln:64:10 + \_module_inst: work@sky130_fd_sc_hd__fahcon (work@sky130_fd_sc_hd__fahcon), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fahcon.functional.v, line:33:1, endln:64:10 |vpiName:xor0_out_SUM |vpiFullName:work@sky130_fd_sc_hd__fahcon.xor0_out_SUM |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__fahcon.a_b), line:50:10, endln:50:13 |vpiParent: - \_module: work@sky130_fd_sc_hd__fahcon (work@sky130_fd_sc_hd__fahcon), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fahcon.functional.v, line:33:1, endln:64:10 + \_module_inst: work@sky130_fd_sc_hd__fahcon (work@sky130_fd_sc_hd__fahcon), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fahcon.functional.v, line:33:1, endln:64:10 |vpiName:a_b |vpiFullName:work@sky130_fd_sc_hd__fahcon.a_b |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__fahcon.a_ci), line:51:10, endln:51:14 |vpiParent: - \_module: work@sky130_fd_sc_hd__fahcon (work@sky130_fd_sc_hd__fahcon), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fahcon.functional.v, line:33:1, endln:64:10 + \_module_inst: work@sky130_fd_sc_hd__fahcon (work@sky130_fd_sc_hd__fahcon), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fahcon.functional.v, line:33:1, endln:64:10 |vpiName:a_ci |vpiFullName:work@sky130_fd_sc_hd__fahcon.a_ci |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__fahcon.b_ci), line:52:10, endln:52:14 |vpiParent: - \_module: work@sky130_fd_sc_hd__fahcon (work@sky130_fd_sc_hd__fahcon), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fahcon.functional.v, line:33:1, endln:64:10 + \_module_inst: work@sky130_fd_sc_hd__fahcon (work@sky130_fd_sc_hd__fahcon), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fahcon.functional.v, line:33:1, endln:64:10 |vpiName:b_ci |vpiFullName:work@sky130_fd_sc_hd__fahcon.b_ci |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__fahcon.or0_out_coutn), line:53:10, endln:53:23 |vpiParent: - \_module: work@sky130_fd_sc_hd__fahcon (work@sky130_fd_sc_hd__fahcon), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fahcon.functional.v, line:33:1, endln:64:10 + \_module_inst: work@sky130_fd_sc_hd__fahcon (work@sky130_fd_sc_hd__fahcon), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fahcon.functional.v, line:33:1, endln:64:10 |vpiName:or0_out_coutn |vpiFullName:work@sky130_fd_sc_hd__fahcon.or0_out_coutn |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__fahcon.COUT_N), line:34:5, endln:34:11 |vpiParent: - \_module: work@sky130_fd_sc_hd__fahcon (work@sky130_fd_sc_hd__fahcon), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fahcon.functional.v, line:33:1, endln:64:10 + \_module_inst: work@sky130_fd_sc_hd__fahcon (work@sky130_fd_sc_hd__fahcon), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fahcon.functional.v, line:33:1, endln:64:10 |vpiName:COUT_N |vpiFullName:work@sky130_fd_sc_hd__fahcon.COUT_N |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__fahcon.SUM), line:35:5, endln:35:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__fahcon (work@sky130_fd_sc_hd__fahcon), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fahcon.functional.v, line:33:1, endln:64:10 + \_module_inst: work@sky130_fd_sc_hd__fahcon (work@sky130_fd_sc_hd__fahcon), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fahcon.functional.v, line:33:1, endln:64:10 |vpiName:SUM |vpiFullName:work@sky130_fd_sc_hd__fahcon.SUM |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__fahcon.A), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__fahcon (work@sky130_fd_sc_hd__fahcon), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fahcon.functional.v, line:33:1, endln:64:10 + \_module_inst: work@sky130_fd_sc_hd__fahcon (work@sky130_fd_sc_hd__fahcon), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fahcon.functional.v, line:33:1, endln:64:10 |vpiName:A |vpiFullName:work@sky130_fd_sc_hd__fahcon.A |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__fahcon.B), line:37:5, endln:37:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__fahcon (work@sky130_fd_sc_hd__fahcon), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fahcon.functional.v, line:33:1, endln:64:10 + \_module_inst: work@sky130_fd_sc_hd__fahcon (work@sky130_fd_sc_hd__fahcon), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fahcon.functional.v, line:33:1, endln:64:10 |vpiName:B |vpiFullName:work@sky130_fd_sc_hd__fahcon.B |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__fahcon.CI), line:38:5, endln:38:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__fahcon (work@sky130_fd_sc_hd__fahcon), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fahcon.functional.v, line:33:1, endln:64:10 + \_module_inst: work@sky130_fd_sc_hd__fahcon (work@sky130_fd_sc_hd__fahcon), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fahcon.functional.v, line:33:1, endln:64:10 |vpiName:CI |vpiFullName:work@sky130_fd_sc_hd__fahcon.CI |vpiPort: \_port: (COUT_N), line:34:5, endln:34:11 |vpiParent: - \_module: work@sky130_fd_sc_hd__fahcon (work@sky130_fd_sc_hd__fahcon), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fahcon.functional.v, line:33:1, endln:64:10 + \_module_inst: work@sky130_fd_sc_hd__fahcon (work@sky130_fd_sc_hd__fahcon), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fahcon.functional.v, line:33:1, endln:64:10 |vpiName:COUT_N |vpiDirection:2 |vpiLowConn: @@ -7556,7 +7556,7 @@ design: (work@sky130_fd_sc_hd__fahcon) |vpiPort: \_port: (SUM), line:35:5, endln:35:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__fahcon (work@sky130_fd_sc_hd__fahcon), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fahcon.functional.v, line:33:1, endln:64:10 + \_module_inst: work@sky130_fd_sc_hd__fahcon (work@sky130_fd_sc_hd__fahcon), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fahcon.functional.v, line:33:1, endln:64:10 |vpiName:SUM |vpiDirection:2 |vpiLowConn: @@ -7568,7 +7568,7 @@ design: (work@sky130_fd_sc_hd__fahcon) |vpiPort: \_port: (A), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__fahcon (work@sky130_fd_sc_hd__fahcon), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fahcon.functional.v, line:33:1, endln:64:10 + \_module_inst: work@sky130_fd_sc_hd__fahcon (work@sky130_fd_sc_hd__fahcon), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fahcon.functional.v, line:33:1, endln:64:10 |vpiName:A |vpiDirection:1 |vpiLowConn: @@ -7580,7 +7580,7 @@ design: (work@sky130_fd_sc_hd__fahcon) |vpiPort: \_port: (B), line:37:5, endln:37:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__fahcon (work@sky130_fd_sc_hd__fahcon), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fahcon.functional.v, line:33:1, endln:64:10 + \_module_inst: work@sky130_fd_sc_hd__fahcon (work@sky130_fd_sc_hd__fahcon), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fahcon.functional.v, line:33:1, endln:64:10 |vpiName:B |vpiDirection:1 |vpiLowConn: @@ -7592,7 +7592,7 @@ design: (work@sky130_fd_sc_hd__fahcon) |vpiPort: \_port: (CI), line:38:5, endln:38:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__fahcon (work@sky130_fd_sc_hd__fahcon), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fahcon.functional.v, line:33:1, endln:64:10 + \_module_inst: work@sky130_fd_sc_hd__fahcon (work@sky130_fd_sc_hd__fahcon), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fahcon.functional.v, line:33:1, endln:64:10 |vpiName:CI |vpiDirection:1 |vpiLowConn: @@ -7602,14 +7602,14 @@ design: (work@sky130_fd_sc_hd__fahcon) |vpiTypedef: \_logic_typespec: , line:46:12, endln:46:12 |uhdmtopModules: -\_module: work@sky130_fd_sc_hd__fahcon (work@sky130_fd_sc_hd__fahcon), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fahcon.functional.v, line:33:1, endln:64:10 +\_module_inst: work@sky130_fd_sc_hd__fahcon (work@sky130_fd_sc_hd__fahcon), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fahcon.functional.v, line:33:1, endln:64:10 |vpiName:work@sky130_fd_sc_hd__fahcon |vpiDefName:work@sky130_fd_sc_hd__fahcon |vpiTop:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__fahcon.xor0_out_SUM), line:49:10, endln:49:22 |vpiParent: - \_module: work@sky130_fd_sc_hd__fahcon (work@sky130_fd_sc_hd__fahcon), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fahcon.functional.v, line:33:1, endln:64:10 + \_module_inst: work@sky130_fd_sc_hd__fahcon (work@sky130_fd_sc_hd__fahcon), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fahcon.functional.v, line:33:1, endln:64:10 |vpiTypespec: \_logic_typespec: , line:49:5, endln:49:9 |vpiName:xor0_out_SUM @@ -7618,7 +7618,7 @@ design: (work@sky130_fd_sc_hd__fahcon) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__fahcon.a_b), line:50:10, endln:50:13 |vpiParent: - \_module: work@sky130_fd_sc_hd__fahcon (work@sky130_fd_sc_hd__fahcon), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fahcon.functional.v, line:33:1, endln:64:10 + \_module_inst: work@sky130_fd_sc_hd__fahcon (work@sky130_fd_sc_hd__fahcon), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fahcon.functional.v, line:33:1, endln:64:10 |vpiTypespec: \_logic_typespec: , line:50:5, endln:50:9 |vpiName:a_b @@ -7627,7 +7627,7 @@ design: (work@sky130_fd_sc_hd__fahcon) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__fahcon.a_ci), line:51:10, endln:51:14 |vpiParent: - \_module: work@sky130_fd_sc_hd__fahcon (work@sky130_fd_sc_hd__fahcon), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fahcon.functional.v, line:33:1, endln:64:10 + \_module_inst: work@sky130_fd_sc_hd__fahcon (work@sky130_fd_sc_hd__fahcon), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fahcon.functional.v, line:33:1, endln:64:10 |vpiTypespec: \_logic_typespec: , line:51:5, endln:51:9 |vpiName:a_ci @@ -7636,7 +7636,7 @@ design: (work@sky130_fd_sc_hd__fahcon) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__fahcon.b_ci), line:52:10, endln:52:14 |vpiParent: - \_module: work@sky130_fd_sc_hd__fahcon (work@sky130_fd_sc_hd__fahcon), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fahcon.functional.v, line:33:1, endln:64:10 + \_module_inst: work@sky130_fd_sc_hd__fahcon (work@sky130_fd_sc_hd__fahcon), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fahcon.functional.v, line:33:1, endln:64:10 |vpiTypespec: \_logic_typespec: , line:52:5, endln:52:9 |vpiName:b_ci @@ -7645,7 +7645,7 @@ design: (work@sky130_fd_sc_hd__fahcon) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__fahcon.or0_out_coutn), line:53:10, endln:53:23 |vpiParent: - \_module: work@sky130_fd_sc_hd__fahcon (work@sky130_fd_sc_hd__fahcon), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fahcon.functional.v, line:33:1, endln:64:10 + \_module_inst: work@sky130_fd_sc_hd__fahcon (work@sky130_fd_sc_hd__fahcon), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fahcon.functional.v, line:33:1, endln:64:10 |vpiTypespec: \_logic_typespec: , line:53:5, endln:53:9 |vpiName:or0_out_coutn @@ -7654,7 +7654,7 @@ design: (work@sky130_fd_sc_hd__fahcon) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__fahcon.COUT_N), line:34:5, endln:34:11 |vpiParent: - \_module: work@sky130_fd_sc_hd__fahcon (work@sky130_fd_sc_hd__fahcon), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fahcon.functional.v, line:33:1, endln:64:10 + \_module_inst: work@sky130_fd_sc_hd__fahcon (work@sky130_fd_sc_hd__fahcon), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fahcon.functional.v, line:33:1, endln:64:10 |vpiTypespec: \_logic_typespec: , line:42:12, endln:42:12 |vpiName:COUT_N @@ -7662,7 +7662,7 @@ design: (work@sky130_fd_sc_hd__fahcon) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__fahcon.SUM), line:35:5, endln:35:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__fahcon (work@sky130_fd_sc_hd__fahcon), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fahcon.functional.v, line:33:1, endln:64:10 + \_module_inst: work@sky130_fd_sc_hd__fahcon (work@sky130_fd_sc_hd__fahcon), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fahcon.functional.v, line:33:1, endln:64:10 |vpiTypespec: \_logic_typespec: , line:43:12, endln:43:12 |vpiName:SUM @@ -7670,7 +7670,7 @@ design: (work@sky130_fd_sc_hd__fahcon) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__fahcon.A), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__fahcon (work@sky130_fd_sc_hd__fahcon), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fahcon.functional.v, line:33:1, endln:64:10 + \_module_inst: work@sky130_fd_sc_hd__fahcon (work@sky130_fd_sc_hd__fahcon), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fahcon.functional.v, line:33:1, endln:64:10 |vpiTypespec: \_logic_typespec: , line:44:12, endln:44:12 |vpiName:A @@ -7678,7 +7678,7 @@ design: (work@sky130_fd_sc_hd__fahcon) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__fahcon.B), line:37:5, endln:37:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__fahcon (work@sky130_fd_sc_hd__fahcon), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fahcon.functional.v, line:33:1, endln:64:10 + \_module_inst: work@sky130_fd_sc_hd__fahcon (work@sky130_fd_sc_hd__fahcon), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fahcon.functional.v, line:33:1, endln:64:10 |vpiTypespec: \_logic_typespec: , line:45:12, endln:45:12 |vpiName:B @@ -7686,7 +7686,7 @@ design: (work@sky130_fd_sc_hd__fahcon) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__fahcon.CI), line:38:5, endln:38:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__fahcon (work@sky130_fd_sc_hd__fahcon), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fahcon.functional.v, line:33:1, endln:64:10 + \_module_inst: work@sky130_fd_sc_hd__fahcon (work@sky130_fd_sc_hd__fahcon), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fahcon.functional.v, line:33:1, endln:64:10 |vpiTypespec: \_logic_typespec: , line:46:12, endln:46:12 |vpiName:CI @@ -7695,7 +7695,7 @@ design: (work@sky130_fd_sc_hd__fahcon) |vpiPort: \_port: (COUT_N), line:34:5, endln:34:11 |vpiParent: - \_module: work@sky130_fd_sc_hd__fahcon (work@sky130_fd_sc_hd__fahcon), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fahcon.functional.v, line:33:1, endln:64:10 + \_module_inst: work@sky130_fd_sc_hd__fahcon (work@sky130_fd_sc_hd__fahcon), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fahcon.functional.v, line:33:1, endln:64:10 |vpiName:COUT_N |vpiDirection:2 |vpiLowConn: @@ -7709,7 +7709,7 @@ design: (work@sky130_fd_sc_hd__fahcon) |vpiPort: \_port: (SUM), line:35:5, endln:35:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__fahcon (work@sky130_fd_sc_hd__fahcon), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fahcon.functional.v, line:33:1, endln:64:10 + \_module_inst: work@sky130_fd_sc_hd__fahcon (work@sky130_fd_sc_hd__fahcon), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fahcon.functional.v, line:33:1, endln:64:10 |vpiName:SUM |vpiDirection:2 |vpiLowConn: @@ -7723,7 +7723,7 @@ design: (work@sky130_fd_sc_hd__fahcon) |vpiPort: \_port: (A), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__fahcon (work@sky130_fd_sc_hd__fahcon), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fahcon.functional.v, line:33:1, endln:64:10 + \_module_inst: work@sky130_fd_sc_hd__fahcon (work@sky130_fd_sc_hd__fahcon), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fahcon.functional.v, line:33:1, endln:64:10 |vpiName:A |vpiDirection:1 |vpiLowConn: @@ -7737,7 +7737,7 @@ design: (work@sky130_fd_sc_hd__fahcon) |vpiPort: \_port: (B), line:37:5, endln:37:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__fahcon (work@sky130_fd_sc_hd__fahcon), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fahcon.functional.v, line:33:1, endln:64:10 + \_module_inst: work@sky130_fd_sc_hd__fahcon (work@sky130_fd_sc_hd__fahcon), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fahcon.functional.v, line:33:1, endln:64:10 |vpiName:B |vpiDirection:1 |vpiLowConn: @@ -7751,7 +7751,7 @@ design: (work@sky130_fd_sc_hd__fahcon) |vpiPort: \_port: (CI), line:38:5, endln:38:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__fahcon (work@sky130_fd_sc_hd__fahcon), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fahcon.functional.v, line:33:1, endln:64:10 + \_module_inst: work@sky130_fd_sc_hd__fahcon (work@sky130_fd_sc_hd__fahcon), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fahcon.functional.v, line:33:1, endln:64:10 |vpiName:CI |vpiDirection:1 |vpiLowConn: @@ -7765,7 +7765,7 @@ design: (work@sky130_fd_sc_hd__fahcon) |vpiPrimitive: \_gate: work@xor (work@sky130_fd_sc_hd__fahcon.xor0), line:56:9, endln:56:46 |vpiParent: - \_module: work@sky130_fd_sc_hd__fahcon (work@sky130_fd_sc_hd__fahcon), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fahcon.functional.v, line:33:1, endln:64:10 + \_module_inst: work@sky130_fd_sc_hd__fahcon (work@sky130_fd_sc_hd__fahcon), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fahcon.functional.v, line:33:1, endln:64:10 |vpiDefName:work@xor |vpiName:xor0 |vpiFullName:work@sky130_fd_sc_hd__fahcon.xor0 @@ -7828,7 +7828,7 @@ design: (work@sky130_fd_sc_hd__fahcon) |vpiPrimitive: \_gate: work@buf (work@sky130_fd_sc_hd__fahcon.buf0), line:57:9, endln:57:46 |vpiParent: - \_module: work@sky130_fd_sc_hd__fahcon (work@sky130_fd_sc_hd__fahcon), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fahcon.functional.v, line:33:1, endln:64:10 + \_module_inst: work@sky130_fd_sc_hd__fahcon (work@sky130_fd_sc_hd__fahcon), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fahcon.functional.v, line:33:1, endln:64:10 |vpiDefName:work@buf |vpiName:buf0 |vpiFullName:work@sky130_fd_sc_hd__fahcon.buf0 @@ -7863,7 +7863,7 @@ design: (work@sky130_fd_sc_hd__fahcon) |vpiPrimitive: \_gate: work@nor (work@sky130_fd_sc_hd__fahcon.nor0), line:58:9, endln:58:46 |vpiParent: - \_module: work@sky130_fd_sc_hd__fahcon (work@sky130_fd_sc_hd__fahcon), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fahcon.functional.v, line:33:1, endln:64:10 + \_module_inst: work@sky130_fd_sc_hd__fahcon (work@sky130_fd_sc_hd__fahcon), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fahcon.functional.v, line:33:1, endln:64:10 |vpiDefName:work@nor |vpiName:nor0 |vpiFullName:work@sky130_fd_sc_hd__fahcon.nor0 @@ -7912,7 +7912,7 @@ design: (work@sky130_fd_sc_hd__fahcon) |vpiPrimitive: \_gate: work@nor (work@sky130_fd_sc_hd__fahcon.nor1), line:59:9, endln:59:46 |vpiParent: - \_module: work@sky130_fd_sc_hd__fahcon (work@sky130_fd_sc_hd__fahcon), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fahcon.functional.v, line:33:1, endln:64:10 + \_module_inst: work@sky130_fd_sc_hd__fahcon (work@sky130_fd_sc_hd__fahcon), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fahcon.functional.v, line:33:1, endln:64:10 |vpiDefName:work@nor |vpiName:nor1 |vpiFullName:work@sky130_fd_sc_hd__fahcon.nor1 @@ -7961,7 +7961,7 @@ design: (work@sky130_fd_sc_hd__fahcon) |vpiPrimitive: \_gate: work@nor (work@sky130_fd_sc_hd__fahcon.nor2), line:60:9, endln:60:46 |vpiParent: - \_module: work@sky130_fd_sc_hd__fahcon (work@sky130_fd_sc_hd__fahcon), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fahcon.functional.v, line:33:1, endln:64:10 + \_module_inst: work@sky130_fd_sc_hd__fahcon (work@sky130_fd_sc_hd__fahcon), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fahcon.functional.v, line:33:1, endln:64:10 |vpiDefName:work@nor |vpiName:nor2 |vpiFullName:work@sky130_fd_sc_hd__fahcon.nor2 @@ -8010,7 +8010,7 @@ design: (work@sky130_fd_sc_hd__fahcon) |vpiPrimitive: \_gate: work@or (work@sky130_fd_sc_hd__fahcon.or0), line:61:9, endln:61:46 |vpiParent: - \_module: work@sky130_fd_sc_hd__fahcon (work@sky130_fd_sc_hd__fahcon), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fahcon.functional.v, line:33:1, endln:64:10 + \_module_inst: work@sky130_fd_sc_hd__fahcon (work@sky130_fd_sc_hd__fahcon), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fahcon.functional.v, line:33:1, endln:64:10 |vpiDefName:work@or |vpiName:or0 |vpiFullName:work@sky130_fd_sc_hd__fahcon.or0 @@ -8073,7 +8073,7 @@ design: (work@sky130_fd_sc_hd__fahcon) |vpiPrimitive: \_gate: work@buf (work@sky130_fd_sc_hd__fahcon.buf1), line:62:9, endln:62:46 |vpiParent: - \_module: work@sky130_fd_sc_hd__fahcon (work@sky130_fd_sc_hd__fahcon), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fahcon.functional.v, line:33:1, endln:64:10 + \_module_inst: work@sky130_fd_sc_hd__fahcon (work@sky130_fd_sc_hd__fahcon), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fahcon.functional.v, line:33:1, endln:64:10 |vpiDefName:work@buf |vpiName:buf1 |vpiFullName:work@sky130_fd_sc_hd__fahcon.buf1 @@ -8116,7 +8116,7 @@ Processing: -cd cells/cells -DUNIT_DELAY -writepp -parse -nocache -nobuiltin -no design: (work@sky130_fd_sc_hd__dlymetal6s2s) |vpiName:work@sky130_fd_sc_hd__dlymetal6s2s |uhdmallModules: -\_module: work@sky130_fd_sc_hd__dlymetal6s2s (work@sky130_fd_sc_hd__dlymetal6s2s), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlymetal6s2s.functional.v, line:34:1, endln:50:10 +\_module_inst: work@sky130_fd_sc_hd__dlymetal6s2s (work@sky130_fd_sc_hd__dlymetal6s2s), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlymetal6s2s.functional.v, line:34:1, endln:50:10 |vpiParent: \_design: (work@sky130_fd_sc_hd__dlymetal6s2s) |vpiFullName:work@sky130_fd_sc_hd__dlymetal6s2s @@ -8124,26 +8124,26 @@ design: (work@sky130_fd_sc_hd__dlymetal6s2s) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__dlymetal6s2s.buf0_out_X), line:44:10, endln:44:20 |vpiParent: - \_module: work@sky130_fd_sc_hd__dlymetal6s2s (work@sky130_fd_sc_hd__dlymetal6s2s), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlymetal6s2s.functional.v, line:34:1, endln:50:10 + \_module_inst: work@sky130_fd_sc_hd__dlymetal6s2s (work@sky130_fd_sc_hd__dlymetal6s2s), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlymetal6s2s.functional.v, line:34:1, endln:50:10 |vpiName:buf0_out_X |vpiFullName:work@sky130_fd_sc_hd__dlymetal6s2s.buf0_out_X |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__dlymetal6s2s.X), line:35:5, endln:35:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__dlymetal6s2s (work@sky130_fd_sc_hd__dlymetal6s2s), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlymetal6s2s.functional.v, line:34:1, endln:50:10 + \_module_inst: work@sky130_fd_sc_hd__dlymetal6s2s (work@sky130_fd_sc_hd__dlymetal6s2s), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlymetal6s2s.functional.v, line:34:1, endln:50:10 |vpiName:X |vpiFullName:work@sky130_fd_sc_hd__dlymetal6s2s.X |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__dlymetal6s2s.A), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__dlymetal6s2s (work@sky130_fd_sc_hd__dlymetal6s2s), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlymetal6s2s.functional.v, line:34:1, endln:50:10 + \_module_inst: work@sky130_fd_sc_hd__dlymetal6s2s (work@sky130_fd_sc_hd__dlymetal6s2s), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlymetal6s2s.functional.v, line:34:1, endln:50:10 |vpiName:A |vpiFullName:work@sky130_fd_sc_hd__dlymetal6s2s.A |vpiPort: \_port: (X), line:35:5, endln:35:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__dlymetal6s2s (work@sky130_fd_sc_hd__dlymetal6s2s), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlymetal6s2s.functional.v, line:34:1, endln:50:10 + \_module_inst: work@sky130_fd_sc_hd__dlymetal6s2s (work@sky130_fd_sc_hd__dlymetal6s2s), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlymetal6s2s.functional.v, line:34:1, endln:50:10 |vpiName:X |vpiDirection:2 |vpiLowConn: @@ -8155,7 +8155,7 @@ design: (work@sky130_fd_sc_hd__dlymetal6s2s) |vpiPort: \_port: (A), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__dlymetal6s2s (work@sky130_fd_sc_hd__dlymetal6s2s), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlymetal6s2s.functional.v, line:34:1, endln:50:10 + \_module_inst: work@sky130_fd_sc_hd__dlymetal6s2s (work@sky130_fd_sc_hd__dlymetal6s2s), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlymetal6s2s.functional.v, line:34:1, endln:50:10 |vpiName:A |vpiDirection:1 |vpiLowConn: @@ -8165,14 +8165,14 @@ design: (work@sky130_fd_sc_hd__dlymetal6s2s) |vpiTypedef: \_logic_typespec: , line:41:12, endln:41:12 |uhdmtopModules: -\_module: work@sky130_fd_sc_hd__dlymetal6s2s (work@sky130_fd_sc_hd__dlymetal6s2s), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlymetal6s2s.functional.v, line:34:1, endln:50:10 +\_module_inst: work@sky130_fd_sc_hd__dlymetal6s2s (work@sky130_fd_sc_hd__dlymetal6s2s), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlymetal6s2s.functional.v, line:34:1, endln:50:10 |vpiName:work@sky130_fd_sc_hd__dlymetal6s2s |vpiDefName:work@sky130_fd_sc_hd__dlymetal6s2s |vpiTop:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__dlymetal6s2s.buf0_out_X), line:44:10, endln:44:20 |vpiParent: - \_module: work@sky130_fd_sc_hd__dlymetal6s2s (work@sky130_fd_sc_hd__dlymetal6s2s), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlymetal6s2s.functional.v, line:34:1, endln:50:10 + \_module_inst: work@sky130_fd_sc_hd__dlymetal6s2s (work@sky130_fd_sc_hd__dlymetal6s2s), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlymetal6s2s.functional.v, line:34:1, endln:50:10 |vpiTypespec: \_logic_typespec: , line:44:5, endln:44:9 |vpiName:buf0_out_X @@ -8181,7 +8181,7 @@ design: (work@sky130_fd_sc_hd__dlymetal6s2s) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__dlymetal6s2s.X), line:35:5, endln:35:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__dlymetal6s2s (work@sky130_fd_sc_hd__dlymetal6s2s), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlymetal6s2s.functional.v, line:34:1, endln:50:10 + \_module_inst: work@sky130_fd_sc_hd__dlymetal6s2s (work@sky130_fd_sc_hd__dlymetal6s2s), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlymetal6s2s.functional.v, line:34:1, endln:50:10 |vpiTypespec: \_logic_typespec: , line:40:12, endln:40:12 |vpiName:X @@ -8189,7 +8189,7 @@ design: (work@sky130_fd_sc_hd__dlymetal6s2s) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__dlymetal6s2s.A), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__dlymetal6s2s (work@sky130_fd_sc_hd__dlymetal6s2s), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlymetal6s2s.functional.v, line:34:1, endln:50:10 + \_module_inst: work@sky130_fd_sc_hd__dlymetal6s2s (work@sky130_fd_sc_hd__dlymetal6s2s), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlymetal6s2s.functional.v, line:34:1, endln:50:10 |vpiTypespec: \_logic_typespec: , line:41:12, endln:41:12 |vpiName:A @@ -8198,7 +8198,7 @@ design: (work@sky130_fd_sc_hd__dlymetal6s2s) |vpiPort: \_port: (X), line:35:5, endln:35:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__dlymetal6s2s (work@sky130_fd_sc_hd__dlymetal6s2s), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlymetal6s2s.functional.v, line:34:1, endln:50:10 + \_module_inst: work@sky130_fd_sc_hd__dlymetal6s2s (work@sky130_fd_sc_hd__dlymetal6s2s), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlymetal6s2s.functional.v, line:34:1, endln:50:10 |vpiName:X |vpiDirection:2 |vpiLowConn: @@ -8212,7 +8212,7 @@ design: (work@sky130_fd_sc_hd__dlymetal6s2s) |vpiPort: \_port: (A), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__dlymetal6s2s (work@sky130_fd_sc_hd__dlymetal6s2s), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlymetal6s2s.functional.v, line:34:1, endln:50:10 + \_module_inst: work@sky130_fd_sc_hd__dlymetal6s2s (work@sky130_fd_sc_hd__dlymetal6s2s), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlymetal6s2s.functional.v, line:34:1, endln:50:10 |vpiName:A |vpiDirection:1 |vpiLowConn: @@ -8226,7 +8226,7 @@ design: (work@sky130_fd_sc_hd__dlymetal6s2s) |vpiPrimitive: \_gate: work@buf (work@sky130_fd_sc_hd__dlymetal6s2s.buf0), line:47:9, endln:47:43 |vpiParent: - \_module: work@sky130_fd_sc_hd__dlymetal6s2s (work@sky130_fd_sc_hd__dlymetal6s2s), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlymetal6s2s.functional.v, line:34:1, endln:50:10 + \_module_inst: work@sky130_fd_sc_hd__dlymetal6s2s (work@sky130_fd_sc_hd__dlymetal6s2s), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlymetal6s2s.functional.v, line:34:1, endln:50:10 |vpiDefName:work@buf |vpiName:buf0 |vpiFullName:work@sky130_fd_sc_hd__dlymetal6s2s.buf0 @@ -8261,7 +8261,7 @@ design: (work@sky130_fd_sc_hd__dlymetal6s2s) |vpiPrimitive: \_gate: work@buf (work@sky130_fd_sc_hd__dlymetal6s2s.buf1), line:48:9, endln:48:43 |vpiParent: - \_module: work@sky130_fd_sc_hd__dlymetal6s2s (work@sky130_fd_sc_hd__dlymetal6s2s), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlymetal6s2s.functional.v, line:34:1, endln:50:10 + \_module_inst: work@sky130_fd_sc_hd__dlymetal6s2s (work@sky130_fd_sc_hd__dlymetal6s2s), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlymetal6s2s.functional.v, line:34:1, endln:50:10 |vpiDefName:work@buf |vpiName:buf1 |vpiFullName:work@sky130_fd_sc_hd__dlymetal6s2s.buf1 @@ -8304,7 +8304,7 @@ Processing: -cd cells/cells -DUNIT_DELAY -writepp -parse -nocache -nobuiltin -no design: (work@sky130_fd_sc_hd__o32a) |vpiName:work@sky130_fd_sc_hd__o32a |uhdmallModules: -\_module: work@sky130_fd_sc_hd__o32a (work@sky130_fd_sc_hd__o32a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o32a.functional.v, line:35:1, endln:63:10 +\_module_inst: work@sky130_fd_sc_hd__o32a (work@sky130_fd_sc_hd__o32a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o32a.functional.v, line:35:1, endln:63:10 |vpiParent: \_design: (work@sky130_fd_sc_hd__o32a) |vpiFullName:work@sky130_fd_sc_hd__o32a @@ -8312,64 +8312,64 @@ design: (work@sky130_fd_sc_hd__o32a) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o32a.or0_out), line:53:10, endln:53:17 |vpiParent: - \_module: work@sky130_fd_sc_hd__o32a (work@sky130_fd_sc_hd__o32a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o32a.functional.v, line:35:1, endln:63:10 + \_module_inst: work@sky130_fd_sc_hd__o32a (work@sky130_fd_sc_hd__o32a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o32a.functional.v, line:35:1, endln:63:10 |vpiName:or0_out |vpiFullName:work@sky130_fd_sc_hd__o32a.or0_out |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o32a.or1_out), line:54:10, endln:54:17 |vpiParent: - \_module: work@sky130_fd_sc_hd__o32a (work@sky130_fd_sc_hd__o32a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o32a.functional.v, line:35:1, endln:63:10 + \_module_inst: work@sky130_fd_sc_hd__o32a (work@sky130_fd_sc_hd__o32a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o32a.functional.v, line:35:1, endln:63:10 |vpiName:or1_out |vpiFullName:work@sky130_fd_sc_hd__o32a.or1_out |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o32a.and0_out_X), line:55:10, endln:55:20 |vpiParent: - \_module: work@sky130_fd_sc_hd__o32a (work@sky130_fd_sc_hd__o32a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o32a.functional.v, line:35:1, endln:63:10 + \_module_inst: work@sky130_fd_sc_hd__o32a (work@sky130_fd_sc_hd__o32a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o32a.functional.v, line:35:1, endln:63:10 |vpiName:and0_out_X |vpiFullName:work@sky130_fd_sc_hd__o32a.and0_out_X |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o32a.X), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__o32a (work@sky130_fd_sc_hd__o32a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o32a.functional.v, line:35:1, endln:63:10 + \_module_inst: work@sky130_fd_sc_hd__o32a (work@sky130_fd_sc_hd__o32a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o32a.functional.v, line:35:1, endln:63:10 |vpiName:X |vpiFullName:work@sky130_fd_sc_hd__o32a.X |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o32a.A1), line:37:5, endln:37:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o32a (work@sky130_fd_sc_hd__o32a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o32a.functional.v, line:35:1, endln:63:10 + \_module_inst: work@sky130_fd_sc_hd__o32a (work@sky130_fd_sc_hd__o32a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o32a.functional.v, line:35:1, endln:63:10 |vpiName:A1 |vpiFullName:work@sky130_fd_sc_hd__o32a.A1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o32a.A2), line:38:5, endln:38:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o32a (work@sky130_fd_sc_hd__o32a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o32a.functional.v, line:35:1, endln:63:10 + \_module_inst: work@sky130_fd_sc_hd__o32a (work@sky130_fd_sc_hd__o32a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o32a.functional.v, line:35:1, endln:63:10 |vpiName:A2 |vpiFullName:work@sky130_fd_sc_hd__o32a.A2 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o32a.A3), line:39:5, endln:39:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o32a (work@sky130_fd_sc_hd__o32a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o32a.functional.v, line:35:1, endln:63:10 + \_module_inst: work@sky130_fd_sc_hd__o32a (work@sky130_fd_sc_hd__o32a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o32a.functional.v, line:35:1, endln:63:10 |vpiName:A3 |vpiFullName:work@sky130_fd_sc_hd__o32a.A3 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o32a.B1), line:40:5, endln:40:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o32a (work@sky130_fd_sc_hd__o32a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o32a.functional.v, line:35:1, endln:63:10 + \_module_inst: work@sky130_fd_sc_hd__o32a (work@sky130_fd_sc_hd__o32a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o32a.functional.v, line:35:1, endln:63:10 |vpiName:B1 |vpiFullName:work@sky130_fd_sc_hd__o32a.B1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o32a.B2), line:41:5, endln:41:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o32a (work@sky130_fd_sc_hd__o32a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o32a.functional.v, line:35:1, endln:63:10 + \_module_inst: work@sky130_fd_sc_hd__o32a (work@sky130_fd_sc_hd__o32a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o32a.functional.v, line:35:1, endln:63:10 |vpiName:B2 |vpiFullName:work@sky130_fd_sc_hd__o32a.B2 |vpiPort: \_port: (X), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__o32a (work@sky130_fd_sc_hd__o32a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o32a.functional.v, line:35:1, endln:63:10 + \_module_inst: work@sky130_fd_sc_hd__o32a (work@sky130_fd_sc_hd__o32a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o32a.functional.v, line:35:1, endln:63:10 |vpiName:X |vpiDirection:2 |vpiLowConn: @@ -8381,7 +8381,7 @@ design: (work@sky130_fd_sc_hd__o32a) |vpiPort: \_port: (A1), line:37:5, endln:37:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o32a (work@sky130_fd_sc_hd__o32a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o32a.functional.v, line:35:1, endln:63:10 + \_module_inst: work@sky130_fd_sc_hd__o32a (work@sky130_fd_sc_hd__o32a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o32a.functional.v, line:35:1, endln:63:10 |vpiName:A1 |vpiDirection:1 |vpiLowConn: @@ -8393,7 +8393,7 @@ design: (work@sky130_fd_sc_hd__o32a) |vpiPort: \_port: (A2), line:38:5, endln:38:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o32a (work@sky130_fd_sc_hd__o32a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o32a.functional.v, line:35:1, endln:63:10 + \_module_inst: work@sky130_fd_sc_hd__o32a (work@sky130_fd_sc_hd__o32a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o32a.functional.v, line:35:1, endln:63:10 |vpiName:A2 |vpiDirection:1 |vpiLowConn: @@ -8405,7 +8405,7 @@ design: (work@sky130_fd_sc_hd__o32a) |vpiPort: \_port: (A3), line:39:5, endln:39:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o32a (work@sky130_fd_sc_hd__o32a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o32a.functional.v, line:35:1, endln:63:10 + \_module_inst: work@sky130_fd_sc_hd__o32a (work@sky130_fd_sc_hd__o32a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o32a.functional.v, line:35:1, endln:63:10 |vpiName:A3 |vpiDirection:1 |vpiLowConn: @@ -8417,7 +8417,7 @@ design: (work@sky130_fd_sc_hd__o32a) |vpiPort: \_port: (B1), line:40:5, endln:40:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o32a (work@sky130_fd_sc_hd__o32a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o32a.functional.v, line:35:1, endln:63:10 + \_module_inst: work@sky130_fd_sc_hd__o32a (work@sky130_fd_sc_hd__o32a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o32a.functional.v, line:35:1, endln:63:10 |vpiName:B1 |vpiDirection:1 |vpiLowConn: @@ -8429,7 +8429,7 @@ design: (work@sky130_fd_sc_hd__o32a) |vpiPort: \_port: (B2), line:41:5, endln:41:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o32a (work@sky130_fd_sc_hd__o32a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o32a.functional.v, line:35:1, endln:63:10 + \_module_inst: work@sky130_fd_sc_hd__o32a (work@sky130_fd_sc_hd__o32a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o32a.functional.v, line:35:1, endln:63:10 |vpiName:B2 |vpiDirection:1 |vpiLowConn: @@ -8439,14 +8439,14 @@ design: (work@sky130_fd_sc_hd__o32a) |vpiTypedef: \_logic_typespec: , line:50:12, endln:50:12 |uhdmtopModules: -\_module: work@sky130_fd_sc_hd__o32a (work@sky130_fd_sc_hd__o32a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o32a.functional.v, line:35:1, endln:63:10 +\_module_inst: work@sky130_fd_sc_hd__o32a (work@sky130_fd_sc_hd__o32a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o32a.functional.v, line:35:1, endln:63:10 |vpiName:work@sky130_fd_sc_hd__o32a |vpiDefName:work@sky130_fd_sc_hd__o32a |vpiTop:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o32a.or0_out), line:53:10, endln:53:17 |vpiParent: - \_module: work@sky130_fd_sc_hd__o32a (work@sky130_fd_sc_hd__o32a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o32a.functional.v, line:35:1, endln:63:10 + \_module_inst: work@sky130_fd_sc_hd__o32a (work@sky130_fd_sc_hd__o32a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o32a.functional.v, line:35:1, endln:63:10 |vpiTypespec: \_logic_typespec: , line:53:5, endln:53:9 |vpiName:or0_out @@ -8455,7 +8455,7 @@ design: (work@sky130_fd_sc_hd__o32a) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o32a.or1_out), line:54:10, endln:54:17 |vpiParent: - \_module: work@sky130_fd_sc_hd__o32a (work@sky130_fd_sc_hd__o32a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o32a.functional.v, line:35:1, endln:63:10 + \_module_inst: work@sky130_fd_sc_hd__o32a (work@sky130_fd_sc_hd__o32a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o32a.functional.v, line:35:1, endln:63:10 |vpiTypespec: \_logic_typespec: , line:54:5, endln:54:9 |vpiName:or1_out @@ -8464,7 +8464,7 @@ design: (work@sky130_fd_sc_hd__o32a) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o32a.and0_out_X), line:55:10, endln:55:20 |vpiParent: - \_module: work@sky130_fd_sc_hd__o32a (work@sky130_fd_sc_hd__o32a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o32a.functional.v, line:35:1, endln:63:10 + \_module_inst: work@sky130_fd_sc_hd__o32a (work@sky130_fd_sc_hd__o32a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o32a.functional.v, line:35:1, endln:63:10 |vpiTypespec: \_logic_typespec: , line:55:5, endln:55:9 |vpiName:and0_out_X @@ -8473,7 +8473,7 @@ design: (work@sky130_fd_sc_hd__o32a) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o32a.X), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__o32a (work@sky130_fd_sc_hd__o32a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o32a.functional.v, line:35:1, endln:63:10 + \_module_inst: work@sky130_fd_sc_hd__o32a (work@sky130_fd_sc_hd__o32a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o32a.functional.v, line:35:1, endln:63:10 |vpiTypespec: \_logic_typespec: , line:45:12, endln:45:12 |vpiName:X @@ -8481,7 +8481,7 @@ design: (work@sky130_fd_sc_hd__o32a) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o32a.A1), line:37:5, endln:37:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o32a (work@sky130_fd_sc_hd__o32a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o32a.functional.v, line:35:1, endln:63:10 + \_module_inst: work@sky130_fd_sc_hd__o32a (work@sky130_fd_sc_hd__o32a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o32a.functional.v, line:35:1, endln:63:10 |vpiTypespec: \_logic_typespec: , line:46:12, endln:46:12 |vpiName:A1 @@ -8489,7 +8489,7 @@ design: (work@sky130_fd_sc_hd__o32a) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o32a.A2), line:38:5, endln:38:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o32a (work@sky130_fd_sc_hd__o32a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o32a.functional.v, line:35:1, endln:63:10 + \_module_inst: work@sky130_fd_sc_hd__o32a (work@sky130_fd_sc_hd__o32a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o32a.functional.v, line:35:1, endln:63:10 |vpiTypespec: \_logic_typespec: , line:47:12, endln:47:12 |vpiName:A2 @@ -8497,7 +8497,7 @@ design: (work@sky130_fd_sc_hd__o32a) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o32a.A3), line:39:5, endln:39:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o32a (work@sky130_fd_sc_hd__o32a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o32a.functional.v, line:35:1, endln:63:10 + \_module_inst: work@sky130_fd_sc_hd__o32a (work@sky130_fd_sc_hd__o32a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o32a.functional.v, line:35:1, endln:63:10 |vpiTypespec: \_logic_typespec: , line:48:12, endln:48:12 |vpiName:A3 @@ -8505,7 +8505,7 @@ design: (work@sky130_fd_sc_hd__o32a) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o32a.B1), line:40:5, endln:40:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o32a (work@sky130_fd_sc_hd__o32a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o32a.functional.v, line:35:1, endln:63:10 + \_module_inst: work@sky130_fd_sc_hd__o32a (work@sky130_fd_sc_hd__o32a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o32a.functional.v, line:35:1, endln:63:10 |vpiTypespec: \_logic_typespec: , line:49:12, endln:49:12 |vpiName:B1 @@ -8513,7 +8513,7 @@ design: (work@sky130_fd_sc_hd__o32a) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o32a.B2), line:41:5, endln:41:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o32a (work@sky130_fd_sc_hd__o32a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o32a.functional.v, line:35:1, endln:63:10 + \_module_inst: work@sky130_fd_sc_hd__o32a (work@sky130_fd_sc_hd__o32a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o32a.functional.v, line:35:1, endln:63:10 |vpiTypespec: \_logic_typespec: , line:50:12, endln:50:12 |vpiName:B2 @@ -8522,7 +8522,7 @@ design: (work@sky130_fd_sc_hd__o32a) |vpiPort: \_port: (X), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__o32a (work@sky130_fd_sc_hd__o32a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o32a.functional.v, line:35:1, endln:63:10 + \_module_inst: work@sky130_fd_sc_hd__o32a (work@sky130_fd_sc_hd__o32a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o32a.functional.v, line:35:1, endln:63:10 |vpiName:X |vpiDirection:2 |vpiLowConn: @@ -8536,7 +8536,7 @@ design: (work@sky130_fd_sc_hd__o32a) |vpiPort: \_port: (A1), line:37:5, endln:37:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o32a (work@sky130_fd_sc_hd__o32a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o32a.functional.v, line:35:1, endln:63:10 + \_module_inst: work@sky130_fd_sc_hd__o32a (work@sky130_fd_sc_hd__o32a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o32a.functional.v, line:35:1, endln:63:10 |vpiName:A1 |vpiDirection:1 |vpiLowConn: @@ -8550,7 +8550,7 @@ design: (work@sky130_fd_sc_hd__o32a) |vpiPort: \_port: (A2), line:38:5, endln:38:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o32a (work@sky130_fd_sc_hd__o32a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o32a.functional.v, line:35:1, endln:63:10 + \_module_inst: work@sky130_fd_sc_hd__o32a (work@sky130_fd_sc_hd__o32a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o32a.functional.v, line:35:1, endln:63:10 |vpiName:A2 |vpiDirection:1 |vpiLowConn: @@ -8564,7 +8564,7 @@ design: (work@sky130_fd_sc_hd__o32a) |vpiPort: \_port: (A3), line:39:5, endln:39:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o32a (work@sky130_fd_sc_hd__o32a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o32a.functional.v, line:35:1, endln:63:10 + \_module_inst: work@sky130_fd_sc_hd__o32a (work@sky130_fd_sc_hd__o32a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o32a.functional.v, line:35:1, endln:63:10 |vpiName:A3 |vpiDirection:1 |vpiLowConn: @@ -8578,7 +8578,7 @@ design: (work@sky130_fd_sc_hd__o32a) |vpiPort: \_port: (B1), line:40:5, endln:40:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o32a (work@sky130_fd_sc_hd__o32a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o32a.functional.v, line:35:1, endln:63:10 + \_module_inst: work@sky130_fd_sc_hd__o32a (work@sky130_fd_sc_hd__o32a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o32a.functional.v, line:35:1, endln:63:10 |vpiName:B1 |vpiDirection:1 |vpiLowConn: @@ -8592,7 +8592,7 @@ design: (work@sky130_fd_sc_hd__o32a) |vpiPort: \_port: (B2), line:41:5, endln:41:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o32a (work@sky130_fd_sc_hd__o32a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o32a.functional.v, line:35:1, endln:63:10 + \_module_inst: work@sky130_fd_sc_hd__o32a (work@sky130_fd_sc_hd__o32a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o32a.functional.v, line:35:1, endln:63:10 |vpiName:B2 |vpiDirection:1 |vpiLowConn: @@ -8606,7 +8606,7 @@ design: (work@sky130_fd_sc_hd__o32a) |vpiPrimitive: \_gate: work@or (work@sky130_fd_sc_hd__o32a.or0), line:58:9, endln:58:44 |vpiParent: - \_module: work@sky130_fd_sc_hd__o32a (work@sky130_fd_sc_hd__o32a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o32a.functional.v, line:35:1, endln:63:10 + \_module_inst: work@sky130_fd_sc_hd__o32a (work@sky130_fd_sc_hd__o32a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o32a.functional.v, line:35:1, endln:63:10 |vpiDefName:work@or |vpiName:or0 |vpiFullName:work@sky130_fd_sc_hd__o32a.or0 @@ -8669,7 +8669,7 @@ design: (work@sky130_fd_sc_hd__o32a) |vpiPrimitive: \_gate: work@or (work@sky130_fd_sc_hd__o32a.or1), line:59:9, endln:59:44 |vpiParent: - \_module: work@sky130_fd_sc_hd__o32a (work@sky130_fd_sc_hd__o32a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o32a.functional.v, line:35:1, endln:63:10 + \_module_inst: work@sky130_fd_sc_hd__o32a (work@sky130_fd_sc_hd__o32a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o32a.functional.v, line:35:1, endln:63:10 |vpiDefName:work@or |vpiName:or1 |vpiFullName:work@sky130_fd_sc_hd__o32a.or1 @@ -8718,7 +8718,7 @@ design: (work@sky130_fd_sc_hd__o32a) |vpiPrimitive: \_gate: work@and (work@sky130_fd_sc_hd__o32a.and0), line:60:9, endln:60:44 |vpiParent: - \_module: work@sky130_fd_sc_hd__o32a (work@sky130_fd_sc_hd__o32a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o32a.functional.v, line:35:1, endln:63:10 + \_module_inst: work@sky130_fd_sc_hd__o32a (work@sky130_fd_sc_hd__o32a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o32a.functional.v, line:35:1, endln:63:10 |vpiDefName:work@and |vpiName:and0 |vpiFullName:work@sky130_fd_sc_hd__o32a.and0 @@ -8767,7 +8767,7 @@ design: (work@sky130_fd_sc_hd__o32a) |vpiPrimitive: \_gate: work@buf (work@sky130_fd_sc_hd__o32a.buf0), line:61:9, endln:61:44 |vpiParent: - \_module: work@sky130_fd_sc_hd__o32a (work@sky130_fd_sc_hd__o32a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o32a.functional.v, line:35:1, endln:63:10 + \_module_inst: work@sky130_fd_sc_hd__o32a (work@sky130_fd_sc_hd__o32a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o32a.functional.v, line:35:1, endln:63:10 |vpiDefName:work@buf |vpiName:buf0 |vpiFullName:work@sky130_fd_sc_hd__o32a.buf0 @@ -9030,7 +9030,7 @@ design: (work@sky130_fd_sc_hd__sdfbbn) |vpiSize:3 |STRING:? 1 1 : 1 |uhdmallModules: -\_module: work@sky130_fd_sc_hd__sdfbbn (work@sky130_fd_sc_hd__sdfbbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfbbn.functional.v, line:38:1, endln:75:10 +\_module_inst: work@sky130_fd_sc_hd__sdfbbn (work@sky130_fd_sc_hd__sdfbbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfbbn.functional.v, line:38:1, endln:75:10 |vpiParent: \_design: (work@sky130_fd_sc_hd__sdfbbn) |vpiFullName:work@sky130_fd_sc_hd__sdfbbn @@ -9038,90 +9038,90 @@ design: (work@sky130_fd_sc_hd__sdfbbn) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__sdfbbn.RESET), line:60:10, endln:60:15 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfbbn (work@sky130_fd_sc_hd__sdfbbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfbbn.functional.v, line:38:1, endln:75:10 + \_module_inst: work@sky130_fd_sc_hd__sdfbbn (work@sky130_fd_sc_hd__sdfbbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfbbn.functional.v, line:38:1, endln:75:10 |vpiName:RESET |vpiFullName:work@sky130_fd_sc_hd__sdfbbn.RESET |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__sdfbbn.SET), line:61:10, endln:61:13 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfbbn (work@sky130_fd_sc_hd__sdfbbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfbbn.functional.v, line:38:1, endln:75:10 + \_module_inst: work@sky130_fd_sc_hd__sdfbbn (work@sky130_fd_sc_hd__sdfbbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfbbn.functional.v, line:38:1, endln:75:10 |vpiName:SET |vpiFullName:work@sky130_fd_sc_hd__sdfbbn.SET |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__sdfbbn.CLK), line:62:10, endln:62:13 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfbbn (work@sky130_fd_sc_hd__sdfbbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfbbn.functional.v, line:38:1, endln:75:10 + \_module_inst: work@sky130_fd_sc_hd__sdfbbn (work@sky130_fd_sc_hd__sdfbbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfbbn.functional.v, line:38:1, endln:75:10 |vpiName:CLK |vpiFullName:work@sky130_fd_sc_hd__sdfbbn.CLK |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__sdfbbn.buf_Q), line:63:10, endln:63:15 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfbbn (work@sky130_fd_sc_hd__sdfbbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfbbn.functional.v, line:38:1, endln:75:10 + \_module_inst: work@sky130_fd_sc_hd__sdfbbn (work@sky130_fd_sc_hd__sdfbbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfbbn.functional.v, line:38:1, endln:75:10 |vpiName:buf_Q |vpiFullName:work@sky130_fd_sc_hd__sdfbbn.buf_Q |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__sdfbbn.mux_out), line:64:10, endln:64:17 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfbbn (work@sky130_fd_sc_hd__sdfbbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfbbn.functional.v, line:38:1, endln:75:10 + \_module_inst: work@sky130_fd_sc_hd__sdfbbn (work@sky130_fd_sc_hd__sdfbbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfbbn.functional.v, line:38:1, endln:75:10 |vpiName:mux_out |vpiFullName:work@sky130_fd_sc_hd__sdfbbn.mux_out |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__sdfbbn.Q), line:39:5, endln:39:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfbbn (work@sky130_fd_sc_hd__sdfbbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfbbn.functional.v, line:38:1, endln:75:10 + \_module_inst: work@sky130_fd_sc_hd__sdfbbn (work@sky130_fd_sc_hd__sdfbbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfbbn.functional.v, line:38:1, endln:75:10 |vpiName:Q |vpiFullName:work@sky130_fd_sc_hd__sdfbbn.Q |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__sdfbbn.Q_N), line:40:5, endln:40:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfbbn (work@sky130_fd_sc_hd__sdfbbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfbbn.functional.v, line:38:1, endln:75:10 + \_module_inst: work@sky130_fd_sc_hd__sdfbbn (work@sky130_fd_sc_hd__sdfbbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfbbn.functional.v, line:38:1, endln:75:10 |vpiName:Q_N |vpiFullName:work@sky130_fd_sc_hd__sdfbbn.Q_N |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__sdfbbn.D), line:41:5, endln:41:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfbbn (work@sky130_fd_sc_hd__sdfbbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfbbn.functional.v, line:38:1, endln:75:10 + \_module_inst: work@sky130_fd_sc_hd__sdfbbn (work@sky130_fd_sc_hd__sdfbbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfbbn.functional.v, line:38:1, endln:75:10 |vpiName:D |vpiFullName:work@sky130_fd_sc_hd__sdfbbn.D |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__sdfbbn.SCD), line:42:5, endln:42:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfbbn (work@sky130_fd_sc_hd__sdfbbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfbbn.functional.v, line:38:1, endln:75:10 + \_module_inst: work@sky130_fd_sc_hd__sdfbbn (work@sky130_fd_sc_hd__sdfbbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfbbn.functional.v, line:38:1, endln:75:10 |vpiName:SCD |vpiFullName:work@sky130_fd_sc_hd__sdfbbn.SCD |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__sdfbbn.SCE), line:43:5, endln:43:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfbbn (work@sky130_fd_sc_hd__sdfbbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfbbn.functional.v, line:38:1, endln:75:10 + \_module_inst: work@sky130_fd_sc_hd__sdfbbn (work@sky130_fd_sc_hd__sdfbbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfbbn.functional.v, line:38:1, endln:75:10 |vpiName:SCE |vpiFullName:work@sky130_fd_sc_hd__sdfbbn.SCE |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__sdfbbn.CLK_N), line:44:5, endln:44:10 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfbbn (work@sky130_fd_sc_hd__sdfbbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfbbn.functional.v, line:38:1, endln:75:10 + \_module_inst: work@sky130_fd_sc_hd__sdfbbn (work@sky130_fd_sc_hd__sdfbbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfbbn.functional.v, line:38:1, endln:75:10 |vpiName:CLK_N |vpiFullName:work@sky130_fd_sc_hd__sdfbbn.CLK_N |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__sdfbbn.SET_B), line:45:5, endln:45:10 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfbbn (work@sky130_fd_sc_hd__sdfbbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfbbn.functional.v, line:38:1, endln:75:10 + \_module_inst: work@sky130_fd_sc_hd__sdfbbn (work@sky130_fd_sc_hd__sdfbbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfbbn.functional.v, line:38:1, endln:75:10 |vpiName:SET_B |vpiFullName:work@sky130_fd_sc_hd__sdfbbn.SET_B |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__sdfbbn.RESET_B), line:46:5, endln:46:12 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfbbn (work@sky130_fd_sc_hd__sdfbbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfbbn.functional.v, line:38:1, endln:75:10 + \_module_inst: work@sky130_fd_sc_hd__sdfbbn (work@sky130_fd_sc_hd__sdfbbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfbbn.functional.v, line:38:1, endln:75:10 |vpiName:RESET_B |vpiFullName:work@sky130_fd_sc_hd__sdfbbn.RESET_B |vpiPort: \_port: (Q), line:39:5, endln:39:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfbbn (work@sky130_fd_sc_hd__sdfbbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfbbn.functional.v, line:38:1, endln:75:10 + \_module_inst: work@sky130_fd_sc_hd__sdfbbn (work@sky130_fd_sc_hd__sdfbbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfbbn.functional.v, line:38:1, endln:75:10 |vpiName:Q |vpiDirection:2 |vpiLowConn: @@ -9133,7 +9133,7 @@ design: (work@sky130_fd_sc_hd__sdfbbn) |vpiPort: \_port: (Q_N), line:40:5, endln:40:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfbbn (work@sky130_fd_sc_hd__sdfbbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfbbn.functional.v, line:38:1, endln:75:10 + \_module_inst: work@sky130_fd_sc_hd__sdfbbn (work@sky130_fd_sc_hd__sdfbbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfbbn.functional.v, line:38:1, endln:75:10 |vpiName:Q_N |vpiDirection:2 |vpiLowConn: @@ -9145,7 +9145,7 @@ design: (work@sky130_fd_sc_hd__sdfbbn) |vpiPort: \_port: (D), line:41:5, endln:41:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfbbn (work@sky130_fd_sc_hd__sdfbbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfbbn.functional.v, line:38:1, endln:75:10 + \_module_inst: work@sky130_fd_sc_hd__sdfbbn (work@sky130_fd_sc_hd__sdfbbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfbbn.functional.v, line:38:1, endln:75:10 |vpiName:D |vpiDirection:1 |vpiLowConn: @@ -9157,7 +9157,7 @@ design: (work@sky130_fd_sc_hd__sdfbbn) |vpiPort: \_port: (SCD), line:42:5, endln:42:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfbbn (work@sky130_fd_sc_hd__sdfbbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfbbn.functional.v, line:38:1, endln:75:10 + \_module_inst: work@sky130_fd_sc_hd__sdfbbn (work@sky130_fd_sc_hd__sdfbbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfbbn.functional.v, line:38:1, endln:75:10 |vpiName:SCD |vpiDirection:1 |vpiLowConn: @@ -9169,7 +9169,7 @@ design: (work@sky130_fd_sc_hd__sdfbbn) |vpiPort: \_port: (SCE), line:43:5, endln:43:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfbbn (work@sky130_fd_sc_hd__sdfbbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfbbn.functional.v, line:38:1, endln:75:10 + \_module_inst: work@sky130_fd_sc_hd__sdfbbn (work@sky130_fd_sc_hd__sdfbbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfbbn.functional.v, line:38:1, endln:75:10 |vpiName:SCE |vpiDirection:1 |vpiLowConn: @@ -9181,7 +9181,7 @@ design: (work@sky130_fd_sc_hd__sdfbbn) |vpiPort: \_port: (CLK_N), line:44:5, endln:44:10 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfbbn (work@sky130_fd_sc_hd__sdfbbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfbbn.functional.v, line:38:1, endln:75:10 + \_module_inst: work@sky130_fd_sc_hd__sdfbbn (work@sky130_fd_sc_hd__sdfbbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfbbn.functional.v, line:38:1, endln:75:10 |vpiName:CLK_N |vpiDirection:1 |vpiLowConn: @@ -9193,7 +9193,7 @@ design: (work@sky130_fd_sc_hd__sdfbbn) |vpiPort: \_port: (SET_B), line:45:5, endln:45:10 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfbbn (work@sky130_fd_sc_hd__sdfbbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfbbn.functional.v, line:38:1, endln:75:10 + \_module_inst: work@sky130_fd_sc_hd__sdfbbn (work@sky130_fd_sc_hd__sdfbbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfbbn.functional.v, line:38:1, endln:75:10 |vpiName:SET_B |vpiDirection:1 |vpiLowConn: @@ -9205,7 +9205,7 @@ design: (work@sky130_fd_sc_hd__sdfbbn) |vpiPort: \_port: (RESET_B), line:46:5, endln:46:12 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfbbn (work@sky130_fd_sc_hd__sdfbbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfbbn.functional.v, line:38:1, endln:75:10 + \_module_inst: work@sky130_fd_sc_hd__sdfbbn (work@sky130_fd_sc_hd__sdfbbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfbbn.functional.v, line:38:1, endln:75:10 |vpiName:RESET_B |vpiDirection:1 |vpiLowConn: @@ -9215,14 +9215,14 @@ design: (work@sky130_fd_sc_hd__sdfbbn) |vpiTypedef: \_logic_typespec: , line:57:12, endln:57:12 |uhdmtopModules: -\_module: work@sky130_fd_sc_hd__sdfbbn (work@sky130_fd_sc_hd__sdfbbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfbbn.functional.v, line:38:1, endln:75:10 +\_module_inst: work@sky130_fd_sc_hd__sdfbbn (work@sky130_fd_sc_hd__sdfbbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfbbn.functional.v, line:38:1, endln:75:10 |vpiName:work@sky130_fd_sc_hd__sdfbbn |vpiDefName:work@sky130_fd_sc_hd__sdfbbn |vpiTop:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__sdfbbn.RESET), line:60:10, endln:60:15 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfbbn (work@sky130_fd_sc_hd__sdfbbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfbbn.functional.v, line:38:1, endln:75:10 + \_module_inst: work@sky130_fd_sc_hd__sdfbbn (work@sky130_fd_sc_hd__sdfbbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfbbn.functional.v, line:38:1, endln:75:10 |vpiTypespec: \_logic_typespec: , line:60:5, endln:60:9 |vpiName:RESET @@ -9231,7 +9231,7 @@ design: (work@sky130_fd_sc_hd__sdfbbn) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__sdfbbn.SET), line:61:10, endln:61:13 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfbbn (work@sky130_fd_sc_hd__sdfbbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfbbn.functional.v, line:38:1, endln:75:10 + \_module_inst: work@sky130_fd_sc_hd__sdfbbn (work@sky130_fd_sc_hd__sdfbbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfbbn.functional.v, line:38:1, endln:75:10 |vpiTypespec: \_logic_typespec: , line:61:5, endln:61:9 |vpiName:SET @@ -9240,7 +9240,7 @@ design: (work@sky130_fd_sc_hd__sdfbbn) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__sdfbbn.CLK), line:62:10, endln:62:13 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfbbn (work@sky130_fd_sc_hd__sdfbbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfbbn.functional.v, line:38:1, endln:75:10 + \_module_inst: work@sky130_fd_sc_hd__sdfbbn (work@sky130_fd_sc_hd__sdfbbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfbbn.functional.v, line:38:1, endln:75:10 |vpiTypespec: \_logic_typespec: , line:62:5, endln:62:9 |vpiName:CLK @@ -9249,7 +9249,7 @@ design: (work@sky130_fd_sc_hd__sdfbbn) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__sdfbbn.buf_Q), line:63:10, endln:63:15 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfbbn (work@sky130_fd_sc_hd__sdfbbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfbbn.functional.v, line:38:1, endln:75:10 + \_module_inst: work@sky130_fd_sc_hd__sdfbbn (work@sky130_fd_sc_hd__sdfbbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfbbn.functional.v, line:38:1, endln:75:10 |vpiTypespec: \_logic_typespec: , line:63:5, endln:63:9 |vpiName:buf_Q @@ -9258,7 +9258,7 @@ design: (work@sky130_fd_sc_hd__sdfbbn) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__sdfbbn.mux_out), line:64:10, endln:64:17 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfbbn (work@sky130_fd_sc_hd__sdfbbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfbbn.functional.v, line:38:1, endln:75:10 + \_module_inst: work@sky130_fd_sc_hd__sdfbbn (work@sky130_fd_sc_hd__sdfbbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfbbn.functional.v, line:38:1, endln:75:10 |vpiTypespec: \_logic_typespec: , line:64:5, endln:64:9 |vpiName:mux_out @@ -9267,7 +9267,7 @@ design: (work@sky130_fd_sc_hd__sdfbbn) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__sdfbbn.Q), line:39:5, endln:39:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfbbn (work@sky130_fd_sc_hd__sdfbbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfbbn.functional.v, line:38:1, endln:75:10 + \_module_inst: work@sky130_fd_sc_hd__sdfbbn (work@sky130_fd_sc_hd__sdfbbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfbbn.functional.v, line:38:1, endln:75:10 |vpiTypespec: \_logic_typespec: , line:50:12, endln:50:12 |vpiName:Q @@ -9275,7 +9275,7 @@ design: (work@sky130_fd_sc_hd__sdfbbn) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__sdfbbn.Q_N), line:40:5, endln:40:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfbbn (work@sky130_fd_sc_hd__sdfbbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfbbn.functional.v, line:38:1, endln:75:10 + \_module_inst: work@sky130_fd_sc_hd__sdfbbn (work@sky130_fd_sc_hd__sdfbbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfbbn.functional.v, line:38:1, endln:75:10 |vpiTypespec: \_logic_typespec: , line:51:12, endln:51:12 |vpiName:Q_N @@ -9283,7 +9283,7 @@ design: (work@sky130_fd_sc_hd__sdfbbn) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__sdfbbn.D), line:41:5, endln:41:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfbbn (work@sky130_fd_sc_hd__sdfbbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfbbn.functional.v, line:38:1, endln:75:10 + \_module_inst: work@sky130_fd_sc_hd__sdfbbn (work@sky130_fd_sc_hd__sdfbbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfbbn.functional.v, line:38:1, endln:75:10 |vpiTypespec: \_logic_typespec: , line:52:12, endln:52:12 |vpiName:D @@ -9291,7 +9291,7 @@ design: (work@sky130_fd_sc_hd__sdfbbn) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__sdfbbn.SCD), line:42:5, endln:42:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfbbn (work@sky130_fd_sc_hd__sdfbbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfbbn.functional.v, line:38:1, endln:75:10 + \_module_inst: work@sky130_fd_sc_hd__sdfbbn (work@sky130_fd_sc_hd__sdfbbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfbbn.functional.v, line:38:1, endln:75:10 |vpiTypespec: \_logic_typespec: , line:53:12, endln:53:12 |vpiName:SCD @@ -9299,7 +9299,7 @@ design: (work@sky130_fd_sc_hd__sdfbbn) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__sdfbbn.SCE), line:43:5, endln:43:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfbbn (work@sky130_fd_sc_hd__sdfbbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfbbn.functional.v, line:38:1, endln:75:10 + \_module_inst: work@sky130_fd_sc_hd__sdfbbn (work@sky130_fd_sc_hd__sdfbbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfbbn.functional.v, line:38:1, endln:75:10 |vpiTypespec: \_logic_typespec: , line:54:12, endln:54:12 |vpiName:SCE @@ -9307,7 +9307,7 @@ design: (work@sky130_fd_sc_hd__sdfbbn) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__sdfbbn.CLK_N), line:44:5, endln:44:10 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfbbn (work@sky130_fd_sc_hd__sdfbbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfbbn.functional.v, line:38:1, endln:75:10 + \_module_inst: work@sky130_fd_sc_hd__sdfbbn (work@sky130_fd_sc_hd__sdfbbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfbbn.functional.v, line:38:1, endln:75:10 |vpiTypespec: \_logic_typespec: , line:55:12, endln:55:12 |vpiName:CLK_N @@ -9315,7 +9315,7 @@ design: (work@sky130_fd_sc_hd__sdfbbn) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__sdfbbn.SET_B), line:45:5, endln:45:10 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfbbn (work@sky130_fd_sc_hd__sdfbbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfbbn.functional.v, line:38:1, endln:75:10 + \_module_inst: work@sky130_fd_sc_hd__sdfbbn (work@sky130_fd_sc_hd__sdfbbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfbbn.functional.v, line:38:1, endln:75:10 |vpiTypespec: \_logic_typespec: , line:56:12, endln:56:12 |vpiName:SET_B @@ -9323,7 +9323,7 @@ design: (work@sky130_fd_sc_hd__sdfbbn) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__sdfbbn.RESET_B), line:46:5, endln:46:12 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfbbn (work@sky130_fd_sc_hd__sdfbbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfbbn.functional.v, line:38:1, endln:75:10 + \_module_inst: work@sky130_fd_sc_hd__sdfbbn (work@sky130_fd_sc_hd__sdfbbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfbbn.functional.v, line:38:1, endln:75:10 |vpiTypespec: \_logic_typespec: , line:57:12, endln:57:12 |vpiName:RESET_B @@ -9332,7 +9332,7 @@ design: (work@sky130_fd_sc_hd__sdfbbn) |vpiPort: \_port: (Q), line:39:5, endln:39:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfbbn (work@sky130_fd_sc_hd__sdfbbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfbbn.functional.v, line:38:1, endln:75:10 + \_module_inst: work@sky130_fd_sc_hd__sdfbbn (work@sky130_fd_sc_hd__sdfbbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfbbn.functional.v, line:38:1, endln:75:10 |vpiName:Q |vpiDirection:2 |vpiLowConn: @@ -9346,7 +9346,7 @@ design: (work@sky130_fd_sc_hd__sdfbbn) |vpiPort: \_port: (Q_N), line:40:5, endln:40:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfbbn (work@sky130_fd_sc_hd__sdfbbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfbbn.functional.v, line:38:1, endln:75:10 + \_module_inst: work@sky130_fd_sc_hd__sdfbbn (work@sky130_fd_sc_hd__sdfbbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfbbn.functional.v, line:38:1, endln:75:10 |vpiName:Q_N |vpiDirection:2 |vpiLowConn: @@ -9360,7 +9360,7 @@ design: (work@sky130_fd_sc_hd__sdfbbn) |vpiPort: \_port: (D), line:41:5, endln:41:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfbbn (work@sky130_fd_sc_hd__sdfbbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfbbn.functional.v, line:38:1, endln:75:10 + \_module_inst: work@sky130_fd_sc_hd__sdfbbn (work@sky130_fd_sc_hd__sdfbbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfbbn.functional.v, line:38:1, endln:75:10 |vpiName:D |vpiDirection:1 |vpiLowConn: @@ -9374,7 +9374,7 @@ design: (work@sky130_fd_sc_hd__sdfbbn) |vpiPort: \_port: (SCD), line:42:5, endln:42:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfbbn (work@sky130_fd_sc_hd__sdfbbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfbbn.functional.v, line:38:1, endln:75:10 + \_module_inst: work@sky130_fd_sc_hd__sdfbbn (work@sky130_fd_sc_hd__sdfbbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfbbn.functional.v, line:38:1, endln:75:10 |vpiName:SCD |vpiDirection:1 |vpiLowConn: @@ -9388,7 +9388,7 @@ design: (work@sky130_fd_sc_hd__sdfbbn) |vpiPort: \_port: (SCE), line:43:5, endln:43:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfbbn (work@sky130_fd_sc_hd__sdfbbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfbbn.functional.v, line:38:1, endln:75:10 + \_module_inst: work@sky130_fd_sc_hd__sdfbbn (work@sky130_fd_sc_hd__sdfbbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfbbn.functional.v, line:38:1, endln:75:10 |vpiName:SCE |vpiDirection:1 |vpiLowConn: @@ -9402,7 +9402,7 @@ design: (work@sky130_fd_sc_hd__sdfbbn) |vpiPort: \_port: (CLK_N), line:44:5, endln:44:10 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfbbn (work@sky130_fd_sc_hd__sdfbbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfbbn.functional.v, line:38:1, endln:75:10 + \_module_inst: work@sky130_fd_sc_hd__sdfbbn (work@sky130_fd_sc_hd__sdfbbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfbbn.functional.v, line:38:1, endln:75:10 |vpiName:CLK_N |vpiDirection:1 |vpiLowConn: @@ -9416,7 +9416,7 @@ design: (work@sky130_fd_sc_hd__sdfbbn) |vpiPort: \_port: (SET_B), line:45:5, endln:45:10 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfbbn (work@sky130_fd_sc_hd__sdfbbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfbbn.functional.v, line:38:1, endln:75:10 + \_module_inst: work@sky130_fd_sc_hd__sdfbbn (work@sky130_fd_sc_hd__sdfbbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfbbn.functional.v, line:38:1, endln:75:10 |vpiName:SET_B |vpiDirection:1 |vpiLowConn: @@ -9430,7 +9430,7 @@ design: (work@sky130_fd_sc_hd__sdfbbn) |vpiPort: \_port: (RESET_B), line:46:5, endln:46:12 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfbbn (work@sky130_fd_sc_hd__sdfbbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfbbn.functional.v, line:38:1, endln:75:10 + \_module_inst: work@sky130_fd_sc_hd__sdfbbn (work@sky130_fd_sc_hd__sdfbbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfbbn.functional.v, line:38:1, endln:75:10 |vpiName:RESET_B |vpiDirection:1 |vpiLowConn: @@ -9444,7 +9444,7 @@ design: (work@sky130_fd_sc_hd__sdfbbn) |vpiPrimitive: \_gate: work@not (work@sky130_fd_sc_hd__sdfbbn.not0), line:67:47, endln:67:92 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfbbn (work@sky130_fd_sc_hd__sdfbbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfbbn.functional.v, line:38:1, endln:75:10 + \_module_inst: work@sky130_fd_sc_hd__sdfbbn (work@sky130_fd_sc_hd__sdfbbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfbbn.functional.v, line:38:1, endln:75:10 |vpiDefName:work@not |vpiName:not0 |vpiFullName:work@sky130_fd_sc_hd__sdfbbn.not0 @@ -9479,7 +9479,7 @@ design: (work@sky130_fd_sc_hd__sdfbbn) |vpiPrimitive: \_gate: work@not (work@sky130_fd_sc_hd__sdfbbn.not1), line:68:47, endln:68:92 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfbbn (work@sky130_fd_sc_hd__sdfbbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfbbn.functional.v, line:38:1, endln:75:10 + \_module_inst: work@sky130_fd_sc_hd__sdfbbn (work@sky130_fd_sc_hd__sdfbbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfbbn.functional.v, line:38:1, endln:75:10 |vpiDefName:work@not |vpiName:not1 |vpiFullName:work@sky130_fd_sc_hd__sdfbbn.not1 @@ -9514,7 +9514,7 @@ design: (work@sky130_fd_sc_hd__sdfbbn) |vpiPrimitive: \_gate: work@not (work@sky130_fd_sc_hd__sdfbbn.not2), line:69:47, endln:69:92 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfbbn (work@sky130_fd_sc_hd__sdfbbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfbbn.functional.v, line:38:1, endln:75:10 + \_module_inst: work@sky130_fd_sc_hd__sdfbbn (work@sky130_fd_sc_hd__sdfbbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfbbn.functional.v, line:38:1, endln:75:10 |vpiDefName:work@not |vpiName:not2 |vpiFullName:work@sky130_fd_sc_hd__sdfbbn.not2 @@ -9549,7 +9549,7 @@ design: (work@sky130_fd_sc_hd__sdfbbn) |vpiPrimitive: \_udp: work@sky130_fd_sc_hd__udp_mux_2to1 (work@sky130_fd_sc_hd__sdfbbn.mux_2to10), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfbbn.functional.v, line:70:5, endln:70:93 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfbbn (work@sky130_fd_sc_hd__sdfbbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfbbn.functional.v, line:38:1, endln:75:10 + \_module_inst: work@sky130_fd_sc_hd__sdfbbn (work@sky130_fd_sc_hd__sdfbbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfbbn.functional.v, line:38:1, endln:75:10 |vpiDefName:work@sky130_fd_sc_hd__udp_mux_2to1 |vpiName:mux_2to10 |vpiFullName:work@sky130_fd_sc_hd__sdfbbn.mux_2to10 @@ -9558,7 +9558,7 @@ design: (work@sky130_fd_sc_hd__sdfbbn) |vpiPrimitive: \_udp: work@sky130_fd_sc_hd__udp_dff$NSR (work@sky130_fd_sc_hd__sdfbbn.dff0), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfbbn.functional.v, line:71:5, endln:71:82 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfbbn (work@sky130_fd_sc_hd__sdfbbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfbbn.functional.v, line:38:1, endln:75:10 + \_module_inst: work@sky130_fd_sc_hd__sdfbbn (work@sky130_fd_sc_hd__sdfbbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfbbn.functional.v, line:38:1, endln:75:10 |vpiDefName:work@sky130_fd_sc_hd__udp_dff$NSR |vpiName:dff0 |vpiFullName:work@sky130_fd_sc_hd__sdfbbn.dff0 @@ -9567,7 +9567,7 @@ design: (work@sky130_fd_sc_hd__sdfbbn) |vpiPrimitive: \_gate: work@buf (work@sky130_fd_sc_hd__sdfbbn.buf0), line:72:47, endln:72:92 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfbbn (work@sky130_fd_sc_hd__sdfbbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfbbn.functional.v, line:38:1, endln:75:10 + \_module_inst: work@sky130_fd_sc_hd__sdfbbn (work@sky130_fd_sc_hd__sdfbbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfbbn.functional.v, line:38:1, endln:75:10 |vpiDefName:work@buf |vpiName:buf0 |vpiFullName:work@sky130_fd_sc_hd__sdfbbn.buf0 @@ -9602,7 +9602,7 @@ design: (work@sky130_fd_sc_hd__sdfbbn) |vpiPrimitive: \_gate: work@not (work@sky130_fd_sc_hd__sdfbbn.not3), line:73:47, endln:73:92 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfbbn (work@sky130_fd_sc_hd__sdfbbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfbbn.functional.v, line:38:1, endln:75:10 + \_module_inst: work@sky130_fd_sc_hd__sdfbbn (work@sky130_fd_sc_hd__sdfbbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfbbn.functional.v, line:38:1, endln:75:10 |vpiDefName:work@not |vpiName:not3 |vpiFullName:work@sky130_fd_sc_hd__sdfbbn.not3 @@ -9743,7 +9743,7 @@ design: (work@sky130_fd_sc_hd__dfxbp) |vpiSize:2 |STRING:* ? : ? : - |uhdmallModules: -\_module: work@sky130_fd_sc_hd__dfxbp (work@sky130_fd_sc_hd__dfxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfxbp.functional.v, line:36:1, endln:57:10 +\_module_inst: work@sky130_fd_sc_hd__dfxbp (work@sky130_fd_sc_hd__dfxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfxbp.functional.v, line:36:1, endln:57:10 |vpiParent: \_design: (work@sky130_fd_sc_hd__dfxbp) |vpiFullName:work@sky130_fd_sc_hd__dfxbp @@ -9751,38 +9751,38 @@ design: (work@sky130_fd_sc_hd__dfxbp) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__dfxbp.buf_Q), line:50:10, endln:50:15 |vpiParent: - \_module: work@sky130_fd_sc_hd__dfxbp (work@sky130_fd_sc_hd__dfxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfxbp.functional.v, line:36:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__dfxbp (work@sky130_fd_sc_hd__dfxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfxbp.functional.v, line:36:1, endln:57:10 |vpiName:buf_Q |vpiFullName:work@sky130_fd_sc_hd__dfxbp.buf_Q |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__dfxbp.Q), line:37:5, endln:37:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__dfxbp (work@sky130_fd_sc_hd__dfxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfxbp.functional.v, line:36:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__dfxbp (work@sky130_fd_sc_hd__dfxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfxbp.functional.v, line:36:1, endln:57:10 |vpiName:Q |vpiFullName:work@sky130_fd_sc_hd__dfxbp.Q |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__dfxbp.Q_N), line:38:5, endln:38:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__dfxbp (work@sky130_fd_sc_hd__dfxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfxbp.functional.v, line:36:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__dfxbp (work@sky130_fd_sc_hd__dfxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfxbp.functional.v, line:36:1, endln:57:10 |vpiName:Q_N |vpiFullName:work@sky130_fd_sc_hd__dfxbp.Q_N |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__dfxbp.CLK), line:39:5, endln:39:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__dfxbp (work@sky130_fd_sc_hd__dfxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfxbp.functional.v, line:36:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__dfxbp (work@sky130_fd_sc_hd__dfxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfxbp.functional.v, line:36:1, endln:57:10 |vpiName:CLK |vpiFullName:work@sky130_fd_sc_hd__dfxbp.CLK |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__dfxbp.D), line:40:5, endln:40:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__dfxbp (work@sky130_fd_sc_hd__dfxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfxbp.functional.v, line:36:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__dfxbp (work@sky130_fd_sc_hd__dfxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfxbp.functional.v, line:36:1, endln:57:10 |vpiName:D |vpiFullName:work@sky130_fd_sc_hd__dfxbp.D |vpiPort: \_port: (Q), line:37:5, endln:37:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__dfxbp (work@sky130_fd_sc_hd__dfxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfxbp.functional.v, line:36:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__dfxbp (work@sky130_fd_sc_hd__dfxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfxbp.functional.v, line:36:1, endln:57:10 |vpiName:Q |vpiDirection:2 |vpiLowConn: @@ -9794,7 +9794,7 @@ design: (work@sky130_fd_sc_hd__dfxbp) |vpiPort: \_port: (Q_N), line:38:5, endln:38:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__dfxbp (work@sky130_fd_sc_hd__dfxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfxbp.functional.v, line:36:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__dfxbp (work@sky130_fd_sc_hd__dfxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfxbp.functional.v, line:36:1, endln:57:10 |vpiName:Q_N |vpiDirection:2 |vpiLowConn: @@ -9806,7 +9806,7 @@ design: (work@sky130_fd_sc_hd__dfxbp) |vpiPort: \_port: (CLK), line:39:5, endln:39:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__dfxbp (work@sky130_fd_sc_hd__dfxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfxbp.functional.v, line:36:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__dfxbp (work@sky130_fd_sc_hd__dfxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfxbp.functional.v, line:36:1, endln:57:10 |vpiName:CLK |vpiDirection:1 |vpiLowConn: @@ -9818,7 +9818,7 @@ design: (work@sky130_fd_sc_hd__dfxbp) |vpiPort: \_port: (D), line:40:5, endln:40:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__dfxbp (work@sky130_fd_sc_hd__dfxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfxbp.functional.v, line:36:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__dfxbp (work@sky130_fd_sc_hd__dfxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfxbp.functional.v, line:36:1, endln:57:10 |vpiName:D |vpiDirection:1 |vpiLowConn: @@ -9828,14 +9828,14 @@ design: (work@sky130_fd_sc_hd__dfxbp) |vpiTypedef: \_logic_typespec: , line:47:12, endln:47:12 |uhdmtopModules: -\_module: work@sky130_fd_sc_hd__dfxbp (work@sky130_fd_sc_hd__dfxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfxbp.functional.v, line:36:1, endln:57:10 +\_module_inst: work@sky130_fd_sc_hd__dfxbp (work@sky130_fd_sc_hd__dfxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfxbp.functional.v, line:36:1, endln:57:10 |vpiName:work@sky130_fd_sc_hd__dfxbp |vpiDefName:work@sky130_fd_sc_hd__dfxbp |vpiTop:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__dfxbp.buf_Q), line:50:10, endln:50:15 |vpiParent: - \_module: work@sky130_fd_sc_hd__dfxbp (work@sky130_fd_sc_hd__dfxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfxbp.functional.v, line:36:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__dfxbp (work@sky130_fd_sc_hd__dfxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfxbp.functional.v, line:36:1, endln:57:10 |vpiTypespec: \_logic_typespec: , line:50:5, endln:50:9 |vpiName:buf_Q @@ -9844,7 +9844,7 @@ design: (work@sky130_fd_sc_hd__dfxbp) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__dfxbp.Q), line:37:5, endln:37:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__dfxbp (work@sky130_fd_sc_hd__dfxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfxbp.functional.v, line:36:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__dfxbp (work@sky130_fd_sc_hd__dfxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfxbp.functional.v, line:36:1, endln:57:10 |vpiTypespec: \_logic_typespec: , line:44:12, endln:44:12 |vpiName:Q @@ -9852,7 +9852,7 @@ design: (work@sky130_fd_sc_hd__dfxbp) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__dfxbp.Q_N), line:38:5, endln:38:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__dfxbp (work@sky130_fd_sc_hd__dfxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfxbp.functional.v, line:36:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__dfxbp (work@sky130_fd_sc_hd__dfxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfxbp.functional.v, line:36:1, endln:57:10 |vpiTypespec: \_logic_typespec: , line:45:12, endln:45:12 |vpiName:Q_N @@ -9860,7 +9860,7 @@ design: (work@sky130_fd_sc_hd__dfxbp) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__dfxbp.CLK), line:39:5, endln:39:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__dfxbp (work@sky130_fd_sc_hd__dfxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfxbp.functional.v, line:36:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__dfxbp (work@sky130_fd_sc_hd__dfxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfxbp.functional.v, line:36:1, endln:57:10 |vpiTypespec: \_logic_typespec: , line:46:12, endln:46:12 |vpiName:CLK @@ -9868,7 +9868,7 @@ design: (work@sky130_fd_sc_hd__dfxbp) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__dfxbp.D), line:40:5, endln:40:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__dfxbp (work@sky130_fd_sc_hd__dfxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfxbp.functional.v, line:36:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__dfxbp (work@sky130_fd_sc_hd__dfxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfxbp.functional.v, line:36:1, endln:57:10 |vpiTypespec: \_logic_typespec: , line:47:12, endln:47:12 |vpiName:D @@ -9877,7 +9877,7 @@ design: (work@sky130_fd_sc_hd__dfxbp) |vpiPort: \_port: (Q), line:37:5, endln:37:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__dfxbp (work@sky130_fd_sc_hd__dfxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfxbp.functional.v, line:36:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__dfxbp (work@sky130_fd_sc_hd__dfxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfxbp.functional.v, line:36:1, endln:57:10 |vpiName:Q |vpiDirection:2 |vpiLowConn: @@ -9891,7 +9891,7 @@ design: (work@sky130_fd_sc_hd__dfxbp) |vpiPort: \_port: (Q_N), line:38:5, endln:38:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__dfxbp (work@sky130_fd_sc_hd__dfxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfxbp.functional.v, line:36:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__dfxbp (work@sky130_fd_sc_hd__dfxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfxbp.functional.v, line:36:1, endln:57:10 |vpiName:Q_N |vpiDirection:2 |vpiLowConn: @@ -9905,7 +9905,7 @@ design: (work@sky130_fd_sc_hd__dfxbp) |vpiPort: \_port: (CLK), line:39:5, endln:39:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__dfxbp (work@sky130_fd_sc_hd__dfxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfxbp.functional.v, line:36:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__dfxbp (work@sky130_fd_sc_hd__dfxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfxbp.functional.v, line:36:1, endln:57:10 |vpiName:CLK |vpiDirection:1 |vpiLowConn: @@ -9919,7 +9919,7 @@ design: (work@sky130_fd_sc_hd__dfxbp) |vpiPort: \_port: (D), line:40:5, endln:40:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__dfxbp (work@sky130_fd_sc_hd__dfxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfxbp.functional.v, line:36:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__dfxbp (work@sky130_fd_sc_hd__dfxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfxbp.functional.v, line:36:1, endln:57:10 |vpiName:D |vpiDirection:1 |vpiLowConn: @@ -9933,7 +9933,7 @@ design: (work@sky130_fd_sc_hd__dfxbp) |vpiPrimitive: \_udp: work@sky130_fd_sc_hd__udp_dff$P (work@sky130_fd_sc_hd__dfxbp.dff0), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfxbp.functional.v, line:53:5, endln:53:64 |vpiParent: - \_module: work@sky130_fd_sc_hd__dfxbp (work@sky130_fd_sc_hd__dfxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfxbp.functional.v, line:36:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__dfxbp (work@sky130_fd_sc_hd__dfxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfxbp.functional.v, line:36:1, endln:57:10 |vpiDefName:work@sky130_fd_sc_hd__udp_dff$P |vpiName:dff0 |vpiFullName:work@sky130_fd_sc_hd__dfxbp.dff0 @@ -9942,7 +9942,7 @@ design: (work@sky130_fd_sc_hd__dfxbp) |vpiPrimitive: \_gate: work@buf (work@sky130_fd_sc_hd__dfxbp.buf0), line:54:44, endln:54:74 |vpiParent: - \_module: work@sky130_fd_sc_hd__dfxbp (work@sky130_fd_sc_hd__dfxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfxbp.functional.v, line:36:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__dfxbp (work@sky130_fd_sc_hd__dfxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfxbp.functional.v, line:36:1, endln:57:10 |vpiDefName:work@buf |vpiName:buf0 |vpiFullName:work@sky130_fd_sc_hd__dfxbp.buf0 @@ -9977,7 +9977,7 @@ design: (work@sky130_fd_sc_hd__dfxbp) |vpiPrimitive: \_gate: work@not (work@sky130_fd_sc_hd__dfxbp.not0), line:55:44, endln:55:74 |vpiParent: - \_module: work@sky130_fd_sc_hd__dfxbp (work@sky130_fd_sc_hd__dfxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfxbp.functional.v, line:36:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__dfxbp (work@sky130_fd_sc_hd__dfxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfxbp.functional.v, line:36:1, endln:57:10 |vpiDefName:work@not |vpiName:not0 |vpiFullName:work@sky130_fd_sc_hd__dfxbp.not0 @@ -10130,7 +10130,7 @@ design: (work@sky130_fd_sc_hd__dlrtn) |vpiSize:3 |STRING:0 x x : 0 : 0 |uhdmallModules: -\_module: work@sky130_fd_sc_hd__dlrtn (work@sky130_fd_sc_hd__dlrtn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlrtn.functional.v, line:36:1, endln:60:10 +\_module_inst: work@sky130_fd_sc_hd__dlrtn (work@sky130_fd_sc_hd__dlrtn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlrtn.functional.v, line:36:1, endln:60:10 |vpiParent: \_design: (work@sky130_fd_sc_hd__dlrtn) |vpiFullName:work@sky130_fd_sc_hd__dlrtn @@ -10138,52 +10138,52 @@ design: (work@sky130_fd_sc_hd__dlrtn) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__dlrtn.RESET), line:50:10, endln:50:15 |vpiParent: - \_module: work@sky130_fd_sc_hd__dlrtn (work@sky130_fd_sc_hd__dlrtn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlrtn.functional.v, line:36:1, endln:60:10 + \_module_inst: work@sky130_fd_sc_hd__dlrtn (work@sky130_fd_sc_hd__dlrtn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlrtn.functional.v, line:36:1, endln:60:10 |vpiName:RESET |vpiFullName:work@sky130_fd_sc_hd__dlrtn.RESET |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__dlrtn.intgate), line:51:10, endln:51:17 |vpiParent: - \_module: work@sky130_fd_sc_hd__dlrtn (work@sky130_fd_sc_hd__dlrtn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlrtn.functional.v, line:36:1, endln:60:10 + \_module_inst: work@sky130_fd_sc_hd__dlrtn (work@sky130_fd_sc_hd__dlrtn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlrtn.functional.v, line:36:1, endln:60:10 |vpiName:intgate |vpiFullName:work@sky130_fd_sc_hd__dlrtn.intgate |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__dlrtn.buf_Q), line:52:10, endln:52:15 |vpiParent: - \_module: work@sky130_fd_sc_hd__dlrtn (work@sky130_fd_sc_hd__dlrtn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlrtn.functional.v, line:36:1, endln:60:10 + \_module_inst: work@sky130_fd_sc_hd__dlrtn (work@sky130_fd_sc_hd__dlrtn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlrtn.functional.v, line:36:1, endln:60:10 |vpiName:buf_Q |vpiFullName:work@sky130_fd_sc_hd__dlrtn.buf_Q |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__dlrtn.Q), line:37:5, endln:37:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__dlrtn (work@sky130_fd_sc_hd__dlrtn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlrtn.functional.v, line:36:1, endln:60:10 + \_module_inst: work@sky130_fd_sc_hd__dlrtn (work@sky130_fd_sc_hd__dlrtn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlrtn.functional.v, line:36:1, endln:60:10 |vpiName:Q |vpiFullName:work@sky130_fd_sc_hd__dlrtn.Q |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__dlrtn.RESET_B), line:38:5, endln:38:12 |vpiParent: - \_module: work@sky130_fd_sc_hd__dlrtn (work@sky130_fd_sc_hd__dlrtn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlrtn.functional.v, line:36:1, endln:60:10 + \_module_inst: work@sky130_fd_sc_hd__dlrtn (work@sky130_fd_sc_hd__dlrtn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlrtn.functional.v, line:36:1, endln:60:10 |vpiName:RESET_B |vpiFullName:work@sky130_fd_sc_hd__dlrtn.RESET_B |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__dlrtn.D), line:39:5, endln:39:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__dlrtn (work@sky130_fd_sc_hd__dlrtn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlrtn.functional.v, line:36:1, endln:60:10 + \_module_inst: work@sky130_fd_sc_hd__dlrtn (work@sky130_fd_sc_hd__dlrtn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlrtn.functional.v, line:36:1, endln:60:10 |vpiName:D |vpiFullName:work@sky130_fd_sc_hd__dlrtn.D |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__dlrtn.GATE_N), line:40:5, endln:40:11 |vpiParent: - \_module: work@sky130_fd_sc_hd__dlrtn (work@sky130_fd_sc_hd__dlrtn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlrtn.functional.v, line:36:1, endln:60:10 + \_module_inst: work@sky130_fd_sc_hd__dlrtn (work@sky130_fd_sc_hd__dlrtn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlrtn.functional.v, line:36:1, endln:60:10 |vpiName:GATE_N |vpiFullName:work@sky130_fd_sc_hd__dlrtn.GATE_N |vpiPort: \_port: (Q), line:37:5, endln:37:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__dlrtn (work@sky130_fd_sc_hd__dlrtn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlrtn.functional.v, line:36:1, endln:60:10 + \_module_inst: work@sky130_fd_sc_hd__dlrtn (work@sky130_fd_sc_hd__dlrtn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlrtn.functional.v, line:36:1, endln:60:10 |vpiName:Q |vpiDirection:2 |vpiLowConn: @@ -10195,7 +10195,7 @@ design: (work@sky130_fd_sc_hd__dlrtn) |vpiPort: \_port: (RESET_B), line:38:5, endln:38:12 |vpiParent: - \_module: work@sky130_fd_sc_hd__dlrtn (work@sky130_fd_sc_hd__dlrtn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlrtn.functional.v, line:36:1, endln:60:10 + \_module_inst: work@sky130_fd_sc_hd__dlrtn (work@sky130_fd_sc_hd__dlrtn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlrtn.functional.v, line:36:1, endln:60:10 |vpiName:RESET_B |vpiDirection:1 |vpiLowConn: @@ -10207,7 +10207,7 @@ design: (work@sky130_fd_sc_hd__dlrtn) |vpiPort: \_port: (D), line:39:5, endln:39:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__dlrtn (work@sky130_fd_sc_hd__dlrtn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlrtn.functional.v, line:36:1, endln:60:10 + \_module_inst: work@sky130_fd_sc_hd__dlrtn (work@sky130_fd_sc_hd__dlrtn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlrtn.functional.v, line:36:1, endln:60:10 |vpiName:D |vpiDirection:1 |vpiLowConn: @@ -10219,7 +10219,7 @@ design: (work@sky130_fd_sc_hd__dlrtn) |vpiPort: \_port: (GATE_N), line:40:5, endln:40:11 |vpiParent: - \_module: work@sky130_fd_sc_hd__dlrtn (work@sky130_fd_sc_hd__dlrtn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlrtn.functional.v, line:36:1, endln:60:10 + \_module_inst: work@sky130_fd_sc_hd__dlrtn (work@sky130_fd_sc_hd__dlrtn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlrtn.functional.v, line:36:1, endln:60:10 |vpiName:GATE_N |vpiDirection:1 |vpiLowConn: @@ -10229,14 +10229,14 @@ design: (work@sky130_fd_sc_hd__dlrtn) |vpiTypedef: \_logic_typespec: , line:47:12, endln:47:12 |uhdmtopModules: -\_module: work@sky130_fd_sc_hd__dlrtn (work@sky130_fd_sc_hd__dlrtn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlrtn.functional.v, line:36:1, endln:60:10 +\_module_inst: work@sky130_fd_sc_hd__dlrtn (work@sky130_fd_sc_hd__dlrtn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlrtn.functional.v, line:36:1, endln:60:10 |vpiName:work@sky130_fd_sc_hd__dlrtn |vpiDefName:work@sky130_fd_sc_hd__dlrtn |vpiTop:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__dlrtn.RESET), line:50:10, endln:50:15 |vpiParent: - \_module: work@sky130_fd_sc_hd__dlrtn (work@sky130_fd_sc_hd__dlrtn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlrtn.functional.v, line:36:1, endln:60:10 + \_module_inst: work@sky130_fd_sc_hd__dlrtn (work@sky130_fd_sc_hd__dlrtn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlrtn.functional.v, line:36:1, endln:60:10 |vpiTypespec: \_logic_typespec: , line:50:5, endln:50:9 |vpiName:RESET @@ -10245,7 +10245,7 @@ design: (work@sky130_fd_sc_hd__dlrtn) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__dlrtn.intgate), line:51:10, endln:51:17 |vpiParent: - \_module: work@sky130_fd_sc_hd__dlrtn (work@sky130_fd_sc_hd__dlrtn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlrtn.functional.v, line:36:1, endln:60:10 + \_module_inst: work@sky130_fd_sc_hd__dlrtn (work@sky130_fd_sc_hd__dlrtn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlrtn.functional.v, line:36:1, endln:60:10 |vpiTypespec: \_logic_typespec: , line:51:5, endln:51:9 |vpiName:intgate @@ -10254,7 +10254,7 @@ design: (work@sky130_fd_sc_hd__dlrtn) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__dlrtn.buf_Q), line:52:10, endln:52:15 |vpiParent: - \_module: work@sky130_fd_sc_hd__dlrtn (work@sky130_fd_sc_hd__dlrtn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlrtn.functional.v, line:36:1, endln:60:10 + \_module_inst: work@sky130_fd_sc_hd__dlrtn (work@sky130_fd_sc_hd__dlrtn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlrtn.functional.v, line:36:1, endln:60:10 |vpiTypespec: \_logic_typespec: , line:52:5, endln:52:9 |vpiName:buf_Q @@ -10263,7 +10263,7 @@ design: (work@sky130_fd_sc_hd__dlrtn) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__dlrtn.Q), line:37:5, endln:37:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__dlrtn (work@sky130_fd_sc_hd__dlrtn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlrtn.functional.v, line:36:1, endln:60:10 + \_module_inst: work@sky130_fd_sc_hd__dlrtn (work@sky130_fd_sc_hd__dlrtn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlrtn.functional.v, line:36:1, endln:60:10 |vpiTypespec: \_logic_typespec: , line:44:12, endln:44:12 |vpiName:Q @@ -10271,7 +10271,7 @@ design: (work@sky130_fd_sc_hd__dlrtn) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__dlrtn.RESET_B), line:38:5, endln:38:12 |vpiParent: - \_module: work@sky130_fd_sc_hd__dlrtn (work@sky130_fd_sc_hd__dlrtn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlrtn.functional.v, line:36:1, endln:60:10 + \_module_inst: work@sky130_fd_sc_hd__dlrtn (work@sky130_fd_sc_hd__dlrtn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlrtn.functional.v, line:36:1, endln:60:10 |vpiTypespec: \_logic_typespec: , line:45:12, endln:45:12 |vpiName:RESET_B @@ -10279,7 +10279,7 @@ design: (work@sky130_fd_sc_hd__dlrtn) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__dlrtn.D), line:39:5, endln:39:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__dlrtn (work@sky130_fd_sc_hd__dlrtn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlrtn.functional.v, line:36:1, endln:60:10 + \_module_inst: work@sky130_fd_sc_hd__dlrtn (work@sky130_fd_sc_hd__dlrtn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlrtn.functional.v, line:36:1, endln:60:10 |vpiTypespec: \_logic_typespec: , line:46:12, endln:46:12 |vpiName:D @@ -10287,7 +10287,7 @@ design: (work@sky130_fd_sc_hd__dlrtn) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__dlrtn.GATE_N), line:40:5, endln:40:11 |vpiParent: - \_module: work@sky130_fd_sc_hd__dlrtn (work@sky130_fd_sc_hd__dlrtn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlrtn.functional.v, line:36:1, endln:60:10 + \_module_inst: work@sky130_fd_sc_hd__dlrtn (work@sky130_fd_sc_hd__dlrtn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlrtn.functional.v, line:36:1, endln:60:10 |vpiTypespec: \_logic_typespec: , line:47:12, endln:47:12 |vpiName:GATE_N @@ -10296,7 +10296,7 @@ design: (work@sky130_fd_sc_hd__dlrtn) |vpiPort: \_port: (Q), line:37:5, endln:37:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__dlrtn (work@sky130_fd_sc_hd__dlrtn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlrtn.functional.v, line:36:1, endln:60:10 + \_module_inst: work@sky130_fd_sc_hd__dlrtn (work@sky130_fd_sc_hd__dlrtn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlrtn.functional.v, line:36:1, endln:60:10 |vpiName:Q |vpiDirection:2 |vpiLowConn: @@ -10310,7 +10310,7 @@ design: (work@sky130_fd_sc_hd__dlrtn) |vpiPort: \_port: (RESET_B), line:38:5, endln:38:12 |vpiParent: - \_module: work@sky130_fd_sc_hd__dlrtn (work@sky130_fd_sc_hd__dlrtn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlrtn.functional.v, line:36:1, endln:60:10 + \_module_inst: work@sky130_fd_sc_hd__dlrtn (work@sky130_fd_sc_hd__dlrtn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlrtn.functional.v, line:36:1, endln:60:10 |vpiName:RESET_B |vpiDirection:1 |vpiLowConn: @@ -10324,7 +10324,7 @@ design: (work@sky130_fd_sc_hd__dlrtn) |vpiPort: \_port: (D), line:39:5, endln:39:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__dlrtn (work@sky130_fd_sc_hd__dlrtn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlrtn.functional.v, line:36:1, endln:60:10 + \_module_inst: work@sky130_fd_sc_hd__dlrtn (work@sky130_fd_sc_hd__dlrtn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlrtn.functional.v, line:36:1, endln:60:10 |vpiName:D |vpiDirection:1 |vpiLowConn: @@ -10338,7 +10338,7 @@ design: (work@sky130_fd_sc_hd__dlrtn) |vpiPort: \_port: (GATE_N), line:40:5, endln:40:11 |vpiParent: - \_module: work@sky130_fd_sc_hd__dlrtn (work@sky130_fd_sc_hd__dlrtn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlrtn.functional.v, line:36:1, endln:60:10 + \_module_inst: work@sky130_fd_sc_hd__dlrtn (work@sky130_fd_sc_hd__dlrtn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlrtn.functional.v, line:36:1, endln:60:10 |vpiName:GATE_N |vpiDirection:1 |vpiLowConn: @@ -10352,7 +10352,7 @@ design: (work@sky130_fd_sc_hd__dlrtn) |vpiPrimitive: \_gate: work@not (work@sky130_fd_sc_hd__dlrtn.not0), line:55:48, endln:55:84 |vpiParent: - \_module: work@sky130_fd_sc_hd__dlrtn (work@sky130_fd_sc_hd__dlrtn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlrtn.functional.v, line:36:1, endln:60:10 + \_module_inst: work@sky130_fd_sc_hd__dlrtn (work@sky130_fd_sc_hd__dlrtn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlrtn.functional.v, line:36:1, endln:60:10 |vpiDefName:work@not |vpiName:not0 |vpiFullName:work@sky130_fd_sc_hd__dlrtn.not0 @@ -10387,7 +10387,7 @@ design: (work@sky130_fd_sc_hd__dlrtn) |vpiPrimitive: \_gate: work@not (work@sky130_fd_sc_hd__dlrtn.not1), line:56:48, endln:56:84 |vpiParent: - \_module: work@sky130_fd_sc_hd__dlrtn (work@sky130_fd_sc_hd__dlrtn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlrtn.functional.v, line:36:1, endln:60:10 + \_module_inst: work@sky130_fd_sc_hd__dlrtn (work@sky130_fd_sc_hd__dlrtn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlrtn.functional.v, line:36:1, endln:60:10 |vpiDefName:work@not |vpiName:not1 |vpiFullName:work@sky130_fd_sc_hd__dlrtn.not1 @@ -10422,7 +10422,7 @@ design: (work@sky130_fd_sc_hd__dlrtn) |vpiPrimitive: \_udp: work@sky130_fd_sc_hd__udp_dlatch$PR (work@sky130_fd_sc_hd__dlrtn.dlatch0), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlrtn.functional.v, line:57:5, endln:57:74 |vpiParent: - \_module: work@sky130_fd_sc_hd__dlrtn (work@sky130_fd_sc_hd__dlrtn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlrtn.functional.v, line:36:1, endln:60:10 + \_module_inst: work@sky130_fd_sc_hd__dlrtn (work@sky130_fd_sc_hd__dlrtn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlrtn.functional.v, line:36:1, endln:60:10 |vpiDefName:work@sky130_fd_sc_hd__udp_dlatch$PR |vpiName:dlatch0 |vpiFullName:work@sky130_fd_sc_hd__dlrtn.dlatch0 @@ -10431,7 +10431,7 @@ design: (work@sky130_fd_sc_hd__dlrtn) |vpiPrimitive: \_gate: work@buf (work@sky130_fd_sc_hd__dlrtn.buf0), line:58:48, endln:58:84 |vpiParent: - \_module: work@sky130_fd_sc_hd__dlrtn (work@sky130_fd_sc_hd__dlrtn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlrtn.functional.v, line:36:1, endln:60:10 + \_module_inst: work@sky130_fd_sc_hd__dlrtn (work@sky130_fd_sc_hd__dlrtn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlrtn.functional.v, line:36:1, endln:60:10 |vpiDefName:work@buf |vpiName:buf0 |vpiFullName:work@sky130_fd_sc_hd__dlrtn.buf0 @@ -10566,7 +10566,7 @@ design: (work@sky130_fd_sc_hd__mux2i) |vpiSize:3 |STRING:1 1 ? : 0 |uhdmallModules: -\_module: work@sky130_fd_sc_hd__mux2i (work@sky130_fd_sc_hd__mux2i), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__mux2i.functional.v, line:36:1, endln:56:10 +\_module_inst: work@sky130_fd_sc_hd__mux2i (work@sky130_fd_sc_hd__mux2i), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__mux2i.functional.v, line:36:1, endln:56:10 |vpiParent: \_design: (work@sky130_fd_sc_hd__mux2i) |vpiFullName:work@sky130_fd_sc_hd__mux2i @@ -10574,38 +10574,38 @@ design: (work@sky130_fd_sc_hd__mux2i) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__mux2i.mux_2to1_n0_out_Y), line:50:10, endln:50:27 |vpiParent: - \_module: work@sky130_fd_sc_hd__mux2i (work@sky130_fd_sc_hd__mux2i), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__mux2i.functional.v, line:36:1, endln:56:10 + \_module_inst: work@sky130_fd_sc_hd__mux2i (work@sky130_fd_sc_hd__mux2i), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__mux2i.functional.v, line:36:1, endln:56:10 |vpiName:mux_2to1_n0_out_Y |vpiFullName:work@sky130_fd_sc_hd__mux2i.mux_2to1_n0_out_Y |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__mux2i.Y), line:37:5, endln:37:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__mux2i (work@sky130_fd_sc_hd__mux2i), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__mux2i.functional.v, line:36:1, endln:56:10 + \_module_inst: work@sky130_fd_sc_hd__mux2i (work@sky130_fd_sc_hd__mux2i), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__mux2i.functional.v, line:36:1, endln:56:10 |vpiName:Y |vpiFullName:work@sky130_fd_sc_hd__mux2i.Y |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__mux2i.A0), line:38:5, endln:38:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__mux2i (work@sky130_fd_sc_hd__mux2i), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__mux2i.functional.v, line:36:1, endln:56:10 + \_module_inst: work@sky130_fd_sc_hd__mux2i (work@sky130_fd_sc_hd__mux2i), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__mux2i.functional.v, line:36:1, endln:56:10 |vpiName:A0 |vpiFullName:work@sky130_fd_sc_hd__mux2i.A0 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__mux2i.A1), line:39:5, endln:39:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__mux2i (work@sky130_fd_sc_hd__mux2i), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__mux2i.functional.v, line:36:1, endln:56:10 + \_module_inst: work@sky130_fd_sc_hd__mux2i (work@sky130_fd_sc_hd__mux2i), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__mux2i.functional.v, line:36:1, endln:56:10 |vpiName:A1 |vpiFullName:work@sky130_fd_sc_hd__mux2i.A1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__mux2i.S), line:40:5, endln:40:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__mux2i (work@sky130_fd_sc_hd__mux2i), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__mux2i.functional.v, line:36:1, endln:56:10 + \_module_inst: work@sky130_fd_sc_hd__mux2i (work@sky130_fd_sc_hd__mux2i), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__mux2i.functional.v, line:36:1, endln:56:10 |vpiName:S |vpiFullName:work@sky130_fd_sc_hd__mux2i.S |vpiPort: \_port: (Y), line:37:5, endln:37:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__mux2i (work@sky130_fd_sc_hd__mux2i), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__mux2i.functional.v, line:36:1, endln:56:10 + \_module_inst: work@sky130_fd_sc_hd__mux2i (work@sky130_fd_sc_hd__mux2i), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__mux2i.functional.v, line:36:1, endln:56:10 |vpiName:Y |vpiDirection:2 |vpiLowConn: @@ -10617,7 +10617,7 @@ design: (work@sky130_fd_sc_hd__mux2i) |vpiPort: \_port: (A0), line:38:5, endln:38:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__mux2i (work@sky130_fd_sc_hd__mux2i), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__mux2i.functional.v, line:36:1, endln:56:10 + \_module_inst: work@sky130_fd_sc_hd__mux2i (work@sky130_fd_sc_hd__mux2i), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__mux2i.functional.v, line:36:1, endln:56:10 |vpiName:A0 |vpiDirection:1 |vpiLowConn: @@ -10629,7 +10629,7 @@ design: (work@sky130_fd_sc_hd__mux2i) |vpiPort: \_port: (A1), line:39:5, endln:39:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__mux2i (work@sky130_fd_sc_hd__mux2i), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__mux2i.functional.v, line:36:1, endln:56:10 + \_module_inst: work@sky130_fd_sc_hd__mux2i (work@sky130_fd_sc_hd__mux2i), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__mux2i.functional.v, line:36:1, endln:56:10 |vpiName:A1 |vpiDirection:1 |vpiLowConn: @@ -10641,7 +10641,7 @@ design: (work@sky130_fd_sc_hd__mux2i) |vpiPort: \_port: (S), line:40:5, endln:40:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__mux2i (work@sky130_fd_sc_hd__mux2i), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__mux2i.functional.v, line:36:1, endln:56:10 + \_module_inst: work@sky130_fd_sc_hd__mux2i (work@sky130_fd_sc_hd__mux2i), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__mux2i.functional.v, line:36:1, endln:56:10 |vpiName:S |vpiDirection:1 |vpiLowConn: @@ -10651,14 +10651,14 @@ design: (work@sky130_fd_sc_hd__mux2i) |vpiTypedef: \_logic_typespec: , line:47:12, endln:47:12 |uhdmtopModules: -\_module: work@sky130_fd_sc_hd__mux2i (work@sky130_fd_sc_hd__mux2i), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__mux2i.functional.v, line:36:1, endln:56:10 +\_module_inst: work@sky130_fd_sc_hd__mux2i (work@sky130_fd_sc_hd__mux2i), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__mux2i.functional.v, line:36:1, endln:56:10 |vpiName:work@sky130_fd_sc_hd__mux2i |vpiDefName:work@sky130_fd_sc_hd__mux2i |vpiTop:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__mux2i.mux_2to1_n0_out_Y), line:50:10, endln:50:27 |vpiParent: - \_module: work@sky130_fd_sc_hd__mux2i (work@sky130_fd_sc_hd__mux2i), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__mux2i.functional.v, line:36:1, endln:56:10 + \_module_inst: work@sky130_fd_sc_hd__mux2i (work@sky130_fd_sc_hd__mux2i), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__mux2i.functional.v, line:36:1, endln:56:10 |vpiTypespec: \_logic_typespec: , line:50:5, endln:50:9 |vpiName:mux_2to1_n0_out_Y @@ -10667,7 +10667,7 @@ design: (work@sky130_fd_sc_hd__mux2i) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__mux2i.Y), line:37:5, endln:37:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__mux2i (work@sky130_fd_sc_hd__mux2i), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__mux2i.functional.v, line:36:1, endln:56:10 + \_module_inst: work@sky130_fd_sc_hd__mux2i (work@sky130_fd_sc_hd__mux2i), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__mux2i.functional.v, line:36:1, endln:56:10 |vpiTypespec: \_logic_typespec: , line:44:12, endln:44:12 |vpiName:Y @@ -10675,7 +10675,7 @@ design: (work@sky130_fd_sc_hd__mux2i) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__mux2i.A0), line:38:5, endln:38:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__mux2i (work@sky130_fd_sc_hd__mux2i), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__mux2i.functional.v, line:36:1, endln:56:10 + \_module_inst: work@sky130_fd_sc_hd__mux2i (work@sky130_fd_sc_hd__mux2i), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__mux2i.functional.v, line:36:1, endln:56:10 |vpiTypespec: \_logic_typespec: , line:45:12, endln:45:12 |vpiName:A0 @@ -10683,7 +10683,7 @@ design: (work@sky130_fd_sc_hd__mux2i) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__mux2i.A1), line:39:5, endln:39:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__mux2i (work@sky130_fd_sc_hd__mux2i), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__mux2i.functional.v, line:36:1, endln:56:10 + \_module_inst: work@sky130_fd_sc_hd__mux2i (work@sky130_fd_sc_hd__mux2i), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__mux2i.functional.v, line:36:1, endln:56:10 |vpiTypespec: \_logic_typespec: , line:46:12, endln:46:12 |vpiName:A1 @@ -10691,7 +10691,7 @@ design: (work@sky130_fd_sc_hd__mux2i) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__mux2i.S), line:40:5, endln:40:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__mux2i (work@sky130_fd_sc_hd__mux2i), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__mux2i.functional.v, line:36:1, endln:56:10 + \_module_inst: work@sky130_fd_sc_hd__mux2i (work@sky130_fd_sc_hd__mux2i), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__mux2i.functional.v, line:36:1, endln:56:10 |vpiTypespec: \_logic_typespec: , line:47:12, endln:47:12 |vpiName:S @@ -10700,7 +10700,7 @@ design: (work@sky130_fd_sc_hd__mux2i) |vpiPort: \_port: (Y), line:37:5, endln:37:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__mux2i (work@sky130_fd_sc_hd__mux2i), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__mux2i.functional.v, line:36:1, endln:56:10 + \_module_inst: work@sky130_fd_sc_hd__mux2i (work@sky130_fd_sc_hd__mux2i), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__mux2i.functional.v, line:36:1, endln:56:10 |vpiName:Y |vpiDirection:2 |vpiLowConn: @@ -10714,7 +10714,7 @@ design: (work@sky130_fd_sc_hd__mux2i) |vpiPort: \_port: (A0), line:38:5, endln:38:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__mux2i (work@sky130_fd_sc_hd__mux2i), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__mux2i.functional.v, line:36:1, endln:56:10 + \_module_inst: work@sky130_fd_sc_hd__mux2i (work@sky130_fd_sc_hd__mux2i), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__mux2i.functional.v, line:36:1, endln:56:10 |vpiName:A0 |vpiDirection:1 |vpiLowConn: @@ -10728,7 +10728,7 @@ design: (work@sky130_fd_sc_hd__mux2i) |vpiPort: \_port: (A1), line:39:5, endln:39:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__mux2i (work@sky130_fd_sc_hd__mux2i), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__mux2i.functional.v, line:36:1, endln:56:10 + \_module_inst: work@sky130_fd_sc_hd__mux2i (work@sky130_fd_sc_hd__mux2i), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__mux2i.functional.v, line:36:1, endln:56:10 |vpiName:A1 |vpiDirection:1 |vpiLowConn: @@ -10742,7 +10742,7 @@ design: (work@sky130_fd_sc_hd__mux2i) |vpiPort: \_port: (S), line:40:5, endln:40:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__mux2i (work@sky130_fd_sc_hd__mux2i), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__mux2i.functional.v, line:36:1, endln:56:10 + \_module_inst: work@sky130_fd_sc_hd__mux2i (work@sky130_fd_sc_hd__mux2i), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__mux2i.functional.v, line:36:1, endln:56:10 |vpiName:S |vpiDirection:1 |vpiLowConn: @@ -10756,7 +10756,7 @@ design: (work@sky130_fd_sc_hd__mux2i) |vpiPrimitive: \_udp: work@sky130_fd_sc_hd__udp_mux_2to1_N (work@sky130_fd_sc_hd__mux2i.mux_2to1_n0), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__mux2i.functional.v, line:53:5, endln:53:88 |vpiParent: - \_module: work@sky130_fd_sc_hd__mux2i (work@sky130_fd_sc_hd__mux2i), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__mux2i.functional.v, line:36:1, endln:56:10 + \_module_inst: work@sky130_fd_sc_hd__mux2i (work@sky130_fd_sc_hd__mux2i), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__mux2i.functional.v, line:36:1, endln:56:10 |vpiDefName:work@sky130_fd_sc_hd__udp_mux_2to1_N |vpiName:mux_2to1_n0 |vpiFullName:work@sky130_fd_sc_hd__mux2i.mux_2to1_n0 @@ -10765,7 +10765,7 @@ design: (work@sky130_fd_sc_hd__mux2i) |vpiPrimitive: \_gate: work@buf (work@sky130_fd_sc_hd__mux2i.buf0), line:54:37, endln:54:87 |vpiParent: - \_module: work@sky130_fd_sc_hd__mux2i (work@sky130_fd_sc_hd__mux2i), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__mux2i.functional.v, line:36:1, endln:56:10 + \_module_inst: work@sky130_fd_sc_hd__mux2i (work@sky130_fd_sc_hd__mux2i), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__mux2i.functional.v, line:36:1, endln:56:10 |vpiDefName:work@buf |vpiName:buf0 |vpiFullName:work@sky130_fd_sc_hd__mux2i.buf0 @@ -10808,7 +10808,7 @@ Processing: -cd cells/cells -DUNIT_DELAY -writepp -parse -nocache -nobuiltin -no design: (work@sky130_fd_sc_hd__o2111ai) |vpiName:work@sky130_fd_sc_hd__o2111ai |uhdmallModules: -\_module: work@sky130_fd_sc_hd__o2111ai (work@sky130_fd_sc_hd__o2111ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o2111ai.functional.v, line:35:1, endln:61:10 +\_module_inst: work@sky130_fd_sc_hd__o2111ai (work@sky130_fd_sc_hd__o2111ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o2111ai.functional.v, line:35:1, endln:61:10 |vpiParent: \_design: (work@sky130_fd_sc_hd__o2111ai) |vpiFullName:work@sky130_fd_sc_hd__o2111ai @@ -10816,57 +10816,57 @@ design: (work@sky130_fd_sc_hd__o2111ai) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o2111ai.or0_out), line:53:10, endln:53:17 |vpiParent: - \_module: work@sky130_fd_sc_hd__o2111ai (work@sky130_fd_sc_hd__o2111ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o2111ai.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o2111ai (work@sky130_fd_sc_hd__o2111ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o2111ai.functional.v, line:35:1, endln:61:10 |vpiName:or0_out |vpiFullName:work@sky130_fd_sc_hd__o2111ai.or0_out |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o2111ai.nand0_out_Y), line:54:10, endln:54:21 |vpiParent: - \_module: work@sky130_fd_sc_hd__o2111ai (work@sky130_fd_sc_hd__o2111ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o2111ai.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o2111ai (work@sky130_fd_sc_hd__o2111ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o2111ai.functional.v, line:35:1, endln:61:10 |vpiName:nand0_out_Y |vpiFullName:work@sky130_fd_sc_hd__o2111ai.nand0_out_Y |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o2111ai.Y), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__o2111ai (work@sky130_fd_sc_hd__o2111ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o2111ai.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o2111ai (work@sky130_fd_sc_hd__o2111ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o2111ai.functional.v, line:35:1, endln:61:10 |vpiName:Y |vpiFullName:work@sky130_fd_sc_hd__o2111ai.Y |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o2111ai.A1), line:37:5, endln:37:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o2111ai (work@sky130_fd_sc_hd__o2111ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o2111ai.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o2111ai (work@sky130_fd_sc_hd__o2111ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o2111ai.functional.v, line:35:1, endln:61:10 |vpiName:A1 |vpiFullName:work@sky130_fd_sc_hd__o2111ai.A1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o2111ai.A2), line:38:5, endln:38:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o2111ai (work@sky130_fd_sc_hd__o2111ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o2111ai.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o2111ai (work@sky130_fd_sc_hd__o2111ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o2111ai.functional.v, line:35:1, endln:61:10 |vpiName:A2 |vpiFullName:work@sky130_fd_sc_hd__o2111ai.A2 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o2111ai.B1), line:39:5, endln:39:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o2111ai (work@sky130_fd_sc_hd__o2111ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o2111ai.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o2111ai (work@sky130_fd_sc_hd__o2111ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o2111ai.functional.v, line:35:1, endln:61:10 |vpiName:B1 |vpiFullName:work@sky130_fd_sc_hd__o2111ai.B1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o2111ai.C1), line:40:5, endln:40:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o2111ai (work@sky130_fd_sc_hd__o2111ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o2111ai.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o2111ai (work@sky130_fd_sc_hd__o2111ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o2111ai.functional.v, line:35:1, endln:61:10 |vpiName:C1 |vpiFullName:work@sky130_fd_sc_hd__o2111ai.C1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o2111ai.D1), line:41:5, endln:41:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o2111ai (work@sky130_fd_sc_hd__o2111ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o2111ai.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o2111ai (work@sky130_fd_sc_hd__o2111ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o2111ai.functional.v, line:35:1, endln:61:10 |vpiName:D1 |vpiFullName:work@sky130_fd_sc_hd__o2111ai.D1 |vpiPort: \_port: (Y), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__o2111ai (work@sky130_fd_sc_hd__o2111ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o2111ai.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o2111ai (work@sky130_fd_sc_hd__o2111ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o2111ai.functional.v, line:35:1, endln:61:10 |vpiName:Y |vpiDirection:2 |vpiLowConn: @@ -10878,7 +10878,7 @@ design: (work@sky130_fd_sc_hd__o2111ai) |vpiPort: \_port: (A1), line:37:5, endln:37:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o2111ai (work@sky130_fd_sc_hd__o2111ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o2111ai.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o2111ai (work@sky130_fd_sc_hd__o2111ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o2111ai.functional.v, line:35:1, endln:61:10 |vpiName:A1 |vpiDirection:1 |vpiLowConn: @@ -10890,7 +10890,7 @@ design: (work@sky130_fd_sc_hd__o2111ai) |vpiPort: \_port: (A2), line:38:5, endln:38:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o2111ai (work@sky130_fd_sc_hd__o2111ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o2111ai.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o2111ai (work@sky130_fd_sc_hd__o2111ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o2111ai.functional.v, line:35:1, endln:61:10 |vpiName:A2 |vpiDirection:1 |vpiLowConn: @@ -10902,7 +10902,7 @@ design: (work@sky130_fd_sc_hd__o2111ai) |vpiPort: \_port: (B1), line:39:5, endln:39:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o2111ai (work@sky130_fd_sc_hd__o2111ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o2111ai.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o2111ai (work@sky130_fd_sc_hd__o2111ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o2111ai.functional.v, line:35:1, endln:61:10 |vpiName:B1 |vpiDirection:1 |vpiLowConn: @@ -10914,7 +10914,7 @@ design: (work@sky130_fd_sc_hd__o2111ai) |vpiPort: \_port: (C1), line:40:5, endln:40:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o2111ai (work@sky130_fd_sc_hd__o2111ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o2111ai.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o2111ai (work@sky130_fd_sc_hd__o2111ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o2111ai.functional.v, line:35:1, endln:61:10 |vpiName:C1 |vpiDirection:1 |vpiLowConn: @@ -10926,7 +10926,7 @@ design: (work@sky130_fd_sc_hd__o2111ai) |vpiPort: \_port: (D1), line:41:5, endln:41:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o2111ai (work@sky130_fd_sc_hd__o2111ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o2111ai.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o2111ai (work@sky130_fd_sc_hd__o2111ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o2111ai.functional.v, line:35:1, endln:61:10 |vpiName:D1 |vpiDirection:1 |vpiLowConn: @@ -10936,14 +10936,14 @@ design: (work@sky130_fd_sc_hd__o2111ai) |vpiTypedef: \_logic_typespec: , line:50:12, endln:50:12 |uhdmtopModules: -\_module: work@sky130_fd_sc_hd__o2111ai (work@sky130_fd_sc_hd__o2111ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o2111ai.functional.v, line:35:1, endln:61:10 +\_module_inst: work@sky130_fd_sc_hd__o2111ai (work@sky130_fd_sc_hd__o2111ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o2111ai.functional.v, line:35:1, endln:61:10 |vpiName:work@sky130_fd_sc_hd__o2111ai |vpiDefName:work@sky130_fd_sc_hd__o2111ai |vpiTop:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o2111ai.or0_out), line:53:10, endln:53:17 |vpiParent: - \_module: work@sky130_fd_sc_hd__o2111ai (work@sky130_fd_sc_hd__o2111ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o2111ai.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o2111ai (work@sky130_fd_sc_hd__o2111ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o2111ai.functional.v, line:35:1, endln:61:10 |vpiTypespec: \_logic_typespec: , line:53:5, endln:53:9 |vpiName:or0_out @@ -10952,7 +10952,7 @@ design: (work@sky130_fd_sc_hd__o2111ai) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o2111ai.nand0_out_Y), line:54:10, endln:54:21 |vpiParent: - \_module: work@sky130_fd_sc_hd__o2111ai (work@sky130_fd_sc_hd__o2111ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o2111ai.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o2111ai (work@sky130_fd_sc_hd__o2111ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o2111ai.functional.v, line:35:1, endln:61:10 |vpiTypespec: \_logic_typespec: , line:54:5, endln:54:9 |vpiName:nand0_out_Y @@ -10961,7 +10961,7 @@ design: (work@sky130_fd_sc_hd__o2111ai) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o2111ai.Y), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__o2111ai (work@sky130_fd_sc_hd__o2111ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o2111ai.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o2111ai (work@sky130_fd_sc_hd__o2111ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o2111ai.functional.v, line:35:1, endln:61:10 |vpiTypespec: \_logic_typespec: , line:45:12, endln:45:12 |vpiName:Y @@ -10969,7 +10969,7 @@ design: (work@sky130_fd_sc_hd__o2111ai) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o2111ai.A1), line:37:5, endln:37:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o2111ai (work@sky130_fd_sc_hd__o2111ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o2111ai.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o2111ai (work@sky130_fd_sc_hd__o2111ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o2111ai.functional.v, line:35:1, endln:61:10 |vpiTypespec: \_logic_typespec: , line:46:12, endln:46:12 |vpiName:A1 @@ -10977,7 +10977,7 @@ design: (work@sky130_fd_sc_hd__o2111ai) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o2111ai.A2), line:38:5, endln:38:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o2111ai (work@sky130_fd_sc_hd__o2111ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o2111ai.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o2111ai (work@sky130_fd_sc_hd__o2111ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o2111ai.functional.v, line:35:1, endln:61:10 |vpiTypespec: \_logic_typespec: , line:47:12, endln:47:12 |vpiName:A2 @@ -10985,7 +10985,7 @@ design: (work@sky130_fd_sc_hd__o2111ai) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o2111ai.B1), line:39:5, endln:39:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o2111ai (work@sky130_fd_sc_hd__o2111ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o2111ai.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o2111ai (work@sky130_fd_sc_hd__o2111ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o2111ai.functional.v, line:35:1, endln:61:10 |vpiTypespec: \_logic_typespec: , line:48:12, endln:48:12 |vpiName:B1 @@ -10993,7 +10993,7 @@ design: (work@sky130_fd_sc_hd__o2111ai) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o2111ai.C1), line:40:5, endln:40:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o2111ai (work@sky130_fd_sc_hd__o2111ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o2111ai.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o2111ai (work@sky130_fd_sc_hd__o2111ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o2111ai.functional.v, line:35:1, endln:61:10 |vpiTypespec: \_logic_typespec: , line:49:12, endln:49:12 |vpiName:C1 @@ -11001,7 +11001,7 @@ design: (work@sky130_fd_sc_hd__o2111ai) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o2111ai.D1), line:41:5, endln:41:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o2111ai (work@sky130_fd_sc_hd__o2111ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o2111ai.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o2111ai (work@sky130_fd_sc_hd__o2111ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o2111ai.functional.v, line:35:1, endln:61:10 |vpiTypespec: \_logic_typespec: , line:50:12, endln:50:12 |vpiName:D1 @@ -11010,7 +11010,7 @@ design: (work@sky130_fd_sc_hd__o2111ai) |vpiPort: \_port: (Y), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__o2111ai (work@sky130_fd_sc_hd__o2111ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o2111ai.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o2111ai (work@sky130_fd_sc_hd__o2111ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o2111ai.functional.v, line:35:1, endln:61:10 |vpiName:Y |vpiDirection:2 |vpiLowConn: @@ -11024,7 +11024,7 @@ design: (work@sky130_fd_sc_hd__o2111ai) |vpiPort: \_port: (A1), line:37:5, endln:37:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o2111ai (work@sky130_fd_sc_hd__o2111ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o2111ai.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o2111ai (work@sky130_fd_sc_hd__o2111ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o2111ai.functional.v, line:35:1, endln:61:10 |vpiName:A1 |vpiDirection:1 |vpiLowConn: @@ -11038,7 +11038,7 @@ design: (work@sky130_fd_sc_hd__o2111ai) |vpiPort: \_port: (A2), line:38:5, endln:38:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o2111ai (work@sky130_fd_sc_hd__o2111ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o2111ai.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o2111ai (work@sky130_fd_sc_hd__o2111ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o2111ai.functional.v, line:35:1, endln:61:10 |vpiName:A2 |vpiDirection:1 |vpiLowConn: @@ -11052,7 +11052,7 @@ design: (work@sky130_fd_sc_hd__o2111ai) |vpiPort: \_port: (B1), line:39:5, endln:39:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o2111ai (work@sky130_fd_sc_hd__o2111ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o2111ai.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o2111ai (work@sky130_fd_sc_hd__o2111ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o2111ai.functional.v, line:35:1, endln:61:10 |vpiName:B1 |vpiDirection:1 |vpiLowConn: @@ -11066,7 +11066,7 @@ design: (work@sky130_fd_sc_hd__o2111ai) |vpiPort: \_port: (C1), line:40:5, endln:40:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o2111ai (work@sky130_fd_sc_hd__o2111ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o2111ai.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o2111ai (work@sky130_fd_sc_hd__o2111ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o2111ai.functional.v, line:35:1, endln:61:10 |vpiName:C1 |vpiDirection:1 |vpiLowConn: @@ -11080,7 +11080,7 @@ design: (work@sky130_fd_sc_hd__o2111ai) |vpiPort: \_port: (D1), line:41:5, endln:41:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o2111ai (work@sky130_fd_sc_hd__o2111ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o2111ai.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o2111ai (work@sky130_fd_sc_hd__o2111ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o2111ai.functional.v, line:35:1, endln:61:10 |vpiName:D1 |vpiDirection:1 |vpiLowConn: @@ -11094,7 +11094,7 @@ design: (work@sky130_fd_sc_hd__o2111ai) |vpiPrimitive: \_gate: work@or (work@sky130_fd_sc_hd__o2111ai.or0), line:57:10, endln:57:50 |vpiParent: - \_module: work@sky130_fd_sc_hd__o2111ai (work@sky130_fd_sc_hd__o2111ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o2111ai.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o2111ai (work@sky130_fd_sc_hd__o2111ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o2111ai.functional.v, line:35:1, endln:61:10 |vpiDefName:work@or |vpiName:or0 |vpiFullName:work@sky130_fd_sc_hd__o2111ai.or0 @@ -11143,7 +11143,7 @@ design: (work@sky130_fd_sc_hd__o2111ai) |vpiPrimitive: \_gate: work@nand (work@sky130_fd_sc_hd__o2111ai.nand0), line:58:10, endln:58:50 |vpiParent: - \_module: work@sky130_fd_sc_hd__o2111ai (work@sky130_fd_sc_hd__o2111ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o2111ai.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o2111ai (work@sky130_fd_sc_hd__o2111ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o2111ai.functional.v, line:35:1, endln:61:10 |vpiDefName:work@nand |vpiName:nand0 |vpiFullName:work@sky130_fd_sc_hd__o2111ai.nand0 @@ -11220,7 +11220,7 @@ design: (work@sky130_fd_sc_hd__o2111ai) |vpiPrimitive: \_gate: work@buf (work@sky130_fd_sc_hd__o2111ai.buf0), line:59:10, endln:59:50 |vpiParent: - \_module: work@sky130_fd_sc_hd__o2111ai (work@sky130_fd_sc_hd__o2111ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o2111ai.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o2111ai (work@sky130_fd_sc_hd__o2111ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o2111ai.functional.v, line:35:1, endln:61:10 |vpiDefName:work@buf |vpiName:buf0 |vpiFullName:work@sky130_fd_sc_hd__o2111ai.buf0 @@ -11263,7 +11263,7 @@ Processing: -cd cells/cells -DUNIT_DELAY -writepp -parse -nocache -nobuiltin -no design: (work@sky130_fd_sc_hd__a222oi) |vpiName:work@sky130_fd_sc_hd__a222oi |uhdmallModules: -\_module: work@sky130_fd_sc_hd__a222oi (work@sky130_fd_sc_hd__a222oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a222oi.functional.v, line:35:1, endln:67:10 +\_module_inst: work@sky130_fd_sc_hd__a222oi (work@sky130_fd_sc_hd__a222oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a222oi.functional.v, line:35:1, endln:67:10 |vpiParent: \_design: (work@sky130_fd_sc_hd__a222oi) |vpiFullName:work@sky130_fd_sc_hd__a222oi @@ -11271,77 +11271,77 @@ design: (work@sky130_fd_sc_hd__a222oi) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a222oi.nand0_out), line:55:10, endln:55:19 |vpiParent: - \_module: work@sky130_fd_sc_hd__a222oi (work@sky130_fd_sc_hd__a222oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a222oi.functional.v, line:35:1, endln:67:10 + \_module_inst: work@sky130_fd_sc_hd__a222oi (work@sky130_fd_sc_hd__a222oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a222oi.functional.v, line:35:1, endln:67:10 |vpiName:nand0_out |vpiFullName:work@sky130_fd_sc_hd__a222oi.nand0_out |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a222oi.nand1_out), line:56:10, endln:56:19 |vpiParent: - \_module: work@sky130_fd_sc_hd__a222oi (work@sky130_fd_sc_hd__a222oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a222oi.functional.v, line:35:1, endln:67:10 + \_module_inst: work@sky130_fd_sc_hd__a222oi (work@sky130_fd_sc_hd__a222oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a222oi.functional.v, line:35:1, endln:67:10 |vpiName:nand1_out |vpiFullName:work@sky130_fd_sc_hd__a222oi.nand1_out |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a222oi.nand2_out), line:57:10, endln:57:19 |vpiParent: - \_module: work@sky130_fd_sc_hd__a222oi (work@sky130_fd_sc_hd__a222oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a222oi.functional.v, line:35:1, endln:67:10 + \_module_inst: work@sky130_fd_sc_hd__a222oi (work@sky130_fd_sc_hd__a222oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a222oi.functional.v, line:35:1, endln:67:10 |vpiName:nand2_out |vpiFullName:work@sky130_fd_sc_hd__a222oi.nand2_out |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a222oi.and0_out_Y), line:58:10, endln:58:20 |vpiParent: - \_module: work@sky130_fd_sc_hd__a222oi (work@sky130_fd_sc_hd__a222oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a222oi.functional.v, line:35:1, endln:67:10 + \_module_inst: work@sky130_fd_sc_hd__a222oi (work@sky130_fd_sc_hd__a222oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a222oi.functional.v, line:35:1, endln:67:10 |vpiName:and0_out_Y |vpiFullName:work@sky130_fd_sc_hd__a222oi.and0_out_Y |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a222oi.Y), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__a222oi (work@sky130_fd_sc_hd__a222oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a222oi.functional.v, line:35:1, endln:67:10 + \_module_inst: work@sky130_fd_sc_hd__a222oi (work@sky130_fd_sc_hd__a222oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a222oi.functional.v, line:35:1, endln:67:10 |vpiName:Y |vpiFullName:work@sky130_fd_sc_hd__a222oi.Y |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a222oi.A1), line:37:5, endln:37:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a222oi (work@sky130_fd_sc_hd__a222oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a222oi.functional.v, line:35:1, endln:67:10 + \_module_inst: work@sky130_fd_sc_hd__a222oi (work@sky130_fd_sc_hd__a222oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a222oi.functional.v, line:35:1, endln:67:10 |vpiName:A1 |vpiFullName:work@sky130_fd_sc_hd__a222oi.A1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a222oi.A2), line:38:5, endln:38:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a222oi (work@sky130_fd_sc_hd__a222oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a222oi.functional.v, line:35:1, endln:67:10 + \_module_inst: work@sky130_fd_sc_hd__a222oi (work@sky130_fd_sc_hd__a222oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a222oi.functional.v, line:35:1, endln:67:10 |vpiName:A2 |vpiFullName:work@sky130_fd_sc_hd__a222oi.A2 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a222oi.B1), line:39:5, endln:39:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a222oi (work@sky130_fd_sc_hd__a222oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a222oi.functional.v, line:35:1, endln:67:10 + \_module_inst: work@sky130_fd_sc_hd__a222oi (work@sky130_fd_sc_hd__a222oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a222oi.functional.v, line:35:1, endln:67:10 |vpiName:B1 |vpiFullName:work@sky130_fd_sc_hd__a222oi.B1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a222oi.B2), line:40:5, endln:40:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a222oi (work@sky130_fd_sc_hd__a222oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a222oi.functional.v, line:35:1, endln:67:10 + \_module_inst: work@sky130_fd_sc_hd__a222oi (work@sky130_fd_sc_hd__a222oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a222oi.functional.v, line:35:1, endln:67:10 |vpiName:B2 |vpiFullName:work@sky130_fd_sc_hd__a222oi.B2 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a222oi.C1), line:41:5, endln:41:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a222oi (work@sky130_fd_sc_hd__a222oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a222oi.functional.v, line:35:1, endln:67:10 + \_module_inst: work@sky130_fd_sc_hd__a222oi (work@sky130_fd_sc_hd__a222oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a222oi.functional.v, line:35:1, endln:67:10 |vpiName:C1 |vpiFullName:work@sky130_fd_sc_hd__a222oi.C1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a222oi.C2), line:42:5, endln:42:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a222oi (work@sky130_fd_sc_hd__a222oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a222oi.functional.v, line:35:1, endln:67:10 + \_module_inst: work@sky130_fd_sc_hd__a222oi (work@sky130_fd_sc_hd__a222oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a222oi.functional.v, line:35:1, endln:67:10 |vpiName:C2 |vpiFullName:work@sky130_fd_sc_hd__a222oi.C2 |vpiPort: \_port: (Y), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__a222oi (work@sky130_fd_sc_hd__a222oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a222oi.functional.v, line:35:1, endln:67:10 + \_module_inst: work@sky130_fd_sc_hd__a222oi (work@sky130_fd_sc_hd__a222oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a222oi.functional.v, line:35:1, endln:67:10 |vpiName:Y |vpiDirection:2 |vpiLowConn: @@ -11353,7 +11353,7 @@ design: (work@sky130_fd_sc_hd__a222oi) |vpiPort: \_port: (A1), line:37:5, endln:37:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a222oi (work@sky130_fd_sc_hd__a222oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a222oi.functional.v, line:35:1, endln:67:10 + \_module_inst: work@sky130_fd_sc_hd__a222oi (work@sky130_fd_sc_hd__a222oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a222oi.functional.v, line:35:1, endln:67:10 |vpiName:A1 |vpiDirection:1 |vpiLowConn: @@ -11365,7 +11365,7 @@ design: (work@sky130_fd_sc_hd__a222oi) |vpiPort: \_port: (A2), line:38:5, endln:38:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a222oi (work@sky130_fd_sc_hd__a222oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a222oi.functional.v, line:35:1, endln:67:10 + \_module_inst: work@sky130_fd_sc_hd__a222oi (work@sky130_fd_sc_hd__a222oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a222oi.functional.v, line:35:1, endln:67:10 |vpiName:A2 |vpiDirection:1 |vpiLowConn: @@ -11377,7 +11377,7 @@ design: (work@sky130_fd_sc_hd__a222oi) |vpiPort: \_port: (B1), line:39:5, endln:39:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a222oi (work@sky130_fd_sc_hd__a222oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a222oi.functional.v, line:35:1, endln:67:10 + \_module_inst: work@sky130_fd_sc_hd__a222oi (work@sky130_fd_sc_hd__a222oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a222oi.functional.v, line:35:1, endln:67:10 |vpiName:B1 |vpiDirection:1 |vpiLowConn: @@ -11389,7 +11389,7 @@ design: (work@sky130_fd_sc_hd__a222oi) |vpiPort: \_port: (B2), line:40:5, endln:40:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a222oi (work@sky130_fd_sc_hd__a222oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a222oi.functional.v, line:35:1, endln:67:10 + \_module_inst: work@sky130_fd_sc_hd__a222oi (work@sky130_fd_sc_hd__a222oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a222oi.functional.v, line:35:1, endln:67:10 |vpiName:B2 |vpiDirection:1 |vpiLowConn: @@ -11401,7 +11401,7 @@ design: (work@sky130_fd_sc_hd__a222oi) |vpiPort: \_port: (C1), line:41:5, endln:41:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a222oi (work@sky130_fd_sc_hd__a222oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a222oi.functional.v, line:35:1, endln:67:10 + \_module_inst: work@sky130_fd_sc_hd__a222oi (work@sky130_fd_sc_hd__a222oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a222oi.functional.v, line:35:1, endln:67:10 |vpiName:C1 |vpiDirection:1 |vpiLowConn: @@ -11413,7 +11413,7 @@ design: (work@sky130_fd_sc_hd__a222oi) |vpiPort: \_port: (C2), line:42:5, endln:42:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a222oi (work@sky130_fd_sc_hd__a222oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a222oi.functional.v, line:35:1, endln:67:10 + \_module_inst: work@sky130_fd_sc_hd__a222oi (work@sky130_fd_sc_hd__a222oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a222oi.functional.v, line:35:1, endln:67:10 |vpiName:C2 |vpiDirection:1 |vpiLowConn: @@ -11423,14 +11423,14 @@ design: (work@sky130_fd_sc_hd__a222oi) |vpiTypedef: \_logic_typespec: , line:52:12, endln:52:12 |uhdmtopModules: -\_module: work@sky130_fd_sc_hd__a222oi (work@sky130_fd_sc_hd__a222oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a222oi.functional.v, line:35:1, endln:67:10 +\_module_inst: work@sky130_fd_sc_hd__a222oi (work@sky130_fd_sc_hd__a222oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a222oi.functional.v, line:35:1, endln:67:10 |vpiName:work@sky130_fd_sc_hd__a222oi |vpiDefName:work@sky130_fd_sc_hd__a222oi |vpiTop:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a222oi.nand0_out), line:55:10, endln:55:19 |vpiParent: - \_module: work@sky130_fd_sc_hd__a222oi (work@sky130_fd_sc_hd__a222oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a222oi.functional.v, line:35:1, endln:67:10 + \_module_inst: work@sky130_fd_sc_hd__a222oi (work@sky130_fd_sc_hd__a222oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a222oi.functional.v, line:35:1, endln:67:10 |vpiTypespec: \_logic_typespec: , line:55:5, endln:55:9 |vpiName:nand0_out @@ -11439,7 +11439,7 @@ design: (work@sky130_fd_sc_hd__a222oi) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a222oi.nand1_out), line:56:10, endln:56:19 |vpiParent: - \_module: work@sky130_fd_sc_hd__a222oi (work@sky130_fd_sc_hd__a222oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a222oi.functional.v, line:35:1, endln:67:10 + \_module_inst: work@sky130_fd_sc_hd__a222oi (work@sky130_fd_sc_hd__a222oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a222oi.functional.v, line:35:1, endln:67:10 |vpiTypespec: \_logic_typespec: , line:56:5, endln:56:9 |vpiName:nand1_out @@ -11448,7 +11448,7 @@ design: (work@sky130_fd_sc_hd__a222oi) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a222oi.nand2_out), line:57:10, endln:57:19 |vpiParent: - \_module: work@sky130_fd_sc_hd__a222oi (work@sky130_fd_sc_hd__a222oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a222oi.functional.v, line:35:1, endln:67:10 + \_module_inst: work@sky130_fd_sc_hd__a222oi (work@sky130_fd_sc_hd__a222oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a222oi.functional.v, line:35:1, endln:67:10 |vpiTypespec: \_logic_typespec: , line:57:5, endln:57:9 |vpiName:nand2_out @@ -11457,7 +11457,7 @@ design: (work@sky130_fd_sc_hd__a222oi) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a222oi.and0_out_Y), line:58:10, endln:58:20 |vpiParent: - \_module: work@sky130_fd_sc_hd__a222oi (work@sky130_fd_sc_hd__a222oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a222oi.functional.v, line:35:1, endln:67:10 + \_module_inst: work@sky130_fd_sc_hd__a222oi (work@sky130_fd_sc_hd__a222oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a222oi.functional.v, line:35:1, endln:67:10 |vpiTypespec: \_logic_typespec: , line:58:5, endln:58:9 |vpiName:and0_out_Y @@ -11466,7 +11466,7 @@ design: (work@sky130_fd_sc_hd__a222oi) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a222oi.Y), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__a222oi (work@sky130_fd_sc_hd__a222oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a222oi.functional.v, line:35:1, endln:67:10 + \_module_inst: work@sky130_fd_sc_hd__a222oi (work@sky130_fd_sc_hd__a222oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a222oi.functional.v, line:35:1, endln:67:10 |vpiTypespec: \_logic_typespec: , line:46:12, endln:46:12 |vpiName:Y @@ -11474,7 +11474,7 @@ design: (work@sky130_fd_sc_hd__a222oi) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a222oi.A1), line:37:5, endln:37:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a222oi (work@sky130_fd_sc_hd__a222oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a222oi.functional.v, line:35:1, endln:67:10 + \_module_inst: work@sky130_fd_sc_hd__a222oi (work@sky130_fd_sc_hd__a222oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a222oi.functional.v, line:35:1, endln:67:10 |vpiTypespec: \_logic_typespec: , line:47:12, endln:47:12 |vpiName:A1 @@ -11482,7 +11482,7 @@ design: (work@sky130_fd_sc_hd__a222oi) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a222oi.A2), line:38:5, endln:38:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a222oi (work@sky130_fd_sc_hd__a222oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a222oi.functional.v, line:35:1, endln:67:10 + \_module_inst: work@sky130_fd_sc_hd__a222oi (work@sky130_fd_sc_hd__a222oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a222oi.functional.v, line:35:1, endln:67:10 |vpiTypespec: \_logic_typespec: , line:48:12, endln:48:12 |vpiName:A2 @@ -11490,7 +11490,7 @@ design: (work@sky130_fd_sc_hd__a222oi) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a222oi.B1), line:39:5, endln:39:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a222oi (work@sky130_fd_sc_hd__a222oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a222oi.functional.v, line:35:1, endln:67:10 + \_module_inst: work@sky130_fd_sc_hd__a222oi (work@sky130_fd_sc_hd__a222oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a222oi.functional.v, line:35:1, endln:67:10 |vpiTypespec: \_logic_typespec: , line:49:12, endln:49:12 |vpiName:B1 @@ -11498,7 +11498,7 @@ design: (work@sky130_fd_sc_hd__a222oi) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a222oi.B2), line:40:5, endln:40:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a222oi (work@sky130_fd_sc_hd__a222oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a222oi.functional.v, line:35:1, endln:67:10 + \_module_inst: work@sky130_fd_sc_hd__a222oi (work@sky130_fd_sc_hd__a222oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a222oi.functional.v, line:35:1, endln:67:10 |vpiTypespec: \_logic_typespec: , line:50:12, endln:50:12 |vpiName:B2 @@ -11506,7 +11506,7 @@ design: (work@sky130_fd_sc_hd__a222oi) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a222oi.C1), line:41:5, endln:41:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a222oi (work@sky130_fd_sc_hd__a222oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a222oi.functional.v, line:35:1, endln:67:10 + \_module_inst: work@sky130_fd_sc_hd__a222oi (work@sky130_fd_sc_hd__a222oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a222oi.functional.v, line:35:1, endln:67:10 |vpiTypespec: \_logic_typespec: , line:51:12, endln:51:12 |vpiName:C1 @@ -11514,7 +11514,7 @@ design: (work@sky130_fd_sc_hd__a222oi) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a222oi.C2), line:42:5, endln:42:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a222oi (work@sky130_fd_sc_hd__a222oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a222oi.functional.v, line:35:1, endln:67:10 + \_module_inst: work@sky130_fd_sc_hd__a222oi (work@sky130_fd_sc_hd__a222oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a222oi.functional.v, line:35:1, endln:67:10 |vpiTypespec: \_logic_typespec: , line:52:12, endln:52:12 |vpiName:C2 @@ -11523,7 +11523,7 @@ design: (work@sky130_fd_sc_hd__a222oi) |vpiPort: \_port: (Y), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__a222oi (work@sky130_fd_sc_hd__a222oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a222oi.functional.v, line:35:1, endln:67:10 + \_module_inst: work@sky130_fd_sc_hd__a222oi (work@sky130_fd_sc_hd__a222oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a222oi.functional.v, line:35:1, endln:67:10 |vpiName:Y |vpiDirection:2 |vpiLowConn: @@ -11537,7 +11537,7 @@ design: (work@sky130_fd_sc_hd__a222oi) |vpiPort: \_port: (A1), line:37:5, endln:37:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a222oi (work@sky130_fd_sc_hd__a222oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a222oi.functional.v, line:35:1, endln:67:10 + \_module_inst: work@sky130_fd_sc_hd__a222oi (work@sky130_fd_sc_hd__a222oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a222oi.functional.v, line:35:1, endln:67:10 |vpiName:A1 |vpiDirection:1 |vpiLowConn: @@ -11551,7 +11551,7 @@ design: (work@sky130_fd_sc_hd__a222oi) |vpiPort: \_port: (A2), line:38:5, endln:38:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a222oi (work@sky130_fd_sc_hd__a222oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a222oi.functional.v, line:35:1, endln:67:10 + \_module_inst: work@sky130_fd_sc_hd__a222oi (work@sky130_fd_sc_hd__a222oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a222oi.functional.v, line:35:1, endln:67:10 |vpiName:A2 |vpiDirection:1 |vpiLowConn: @@ -11565,7 +11565,7 @@ design: (work@sky130_fd_sc_hd__a222oi) |vpiPort: \_port: (B1), line:39:5, endln:39:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a222oi (work@sky130_fd_sc_hd__a222oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a222oi.functional.v, line:35:1, endln:67:10 + \_module_inst: work@sky130_fd_sc_hd__a222oi (work@sky130_fd_sc_hd__a222oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a222oi.functional.v, line:35:1, endln:67:10 |vpiName:B1 |vpiDirection:1 |vpiLowConn: @@ -11579,7 +11579,7 @@ design: (work@sky130_fd_sc_hd__a222oi) |vpiPort: \_port: (B2), line:40:5, endln:40:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a222oi (work@sky130_fd_sc_hd__a222oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a222oi.functional.v, line:35:1, endln:67:10 + \_module_inst: work@sky130_fd_sc_hd__a222oi (work@sky130_fd_sc_hd__a222oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a222oi.functional.v, line:35:1, endln:67:10 |vpiName:B2 |vpiDirection:1 |vpiLowConn: @@ -11593,7 +11593,7 @@ design: (work@sky130_fd_sc_hd__a222oi) |vpiPort: \_port: (C1), line:41:5, endln:41:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a222oi (work@sky130_fd_sc_hd__a222oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a222oi.functional.v, line:35:1, endln:67:10 + \_module_inst: work@sky130_fd_sc_hd__a222oi (work@sky130_fd_sc_hd__a222oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a222oi.functional.v, line:35:1, endln:67:10 |vpiName:C1 |vpiDirection:1 |vpiLowConn: @@ -11607,7 +11607,7 @@ design: (work@sky130_fd_sc_hd__a222oi) |vpiPort: \_port: (C2), line:42:5, endln:42:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a222oi (work@sky130_fd_sc_hd__a222oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a222oi.functional.v, line:35:1, endln:67:10 + \_module_inst: work@sky130_fd_sc_hd__a222oi (work@sky130_fd_sc_hd__a222oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a222oi.functional.v, line:35:1, endln:67:10 |vpiName:C2 |vpiDirection:1 |vpiLowConn: @@ -11621,7 +11621,7 @@ design: (work@sky130_fd_sc_hd__a222oi) |vpiPrimitive: \_gate: work@nand (work@sky130_fd_sc_hd__a222oi.nand0), line:61:10, endln:61:61 |vpiParent: - \_module: work@sky130_fd_sc_hd__a222oi (work@sky130_fd_sc_hd__a222oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a222oi.functional.v, line:35:1, endln:67:10 + \_module_inst: work@sky130_fd_sc_hd__a222oi (work@sky130_fd_sc_hd__a222oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a222oi.functional.v, line:35:1, endln:67:10 |vpiDefName:work@nand |vpiName:nand0 |vpiFullName:work@sky130_fd_sc_hd__a222oi.nand0 @@ -11670,7 +11670,7 @@ design: (work@sky130_fd_sc_hd__a222oi) |vpiPrimitive: \_gate: work@nand (work@sky130_fd_sc_hd__a222oi.nand1), line:62:10, endln:62:61 |vpiParent: - \_module: work@sky130_fd_sc_hd__a222oi (work@sky130_fd_sc_hd__a222oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a222oi.functional.v, line:35:1, endln:67:10 + \_module_inst: work@sky130_fd_sc_hd__a222oi (work@sky130_fd_sc_hd__a222oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a222oi.functional.v, line:35:1, endln:67:10 |vpiDefName:work@nand |vpiName:nand1 |vpiFullName:work@sky130_fd_sc_hd__a222oi.nand1 @@ -11719,7 +11719,7 @@ design: (work@sky130_fd_sc_hd__a222oi) |vpiPrimitive: \_gate: work@nand (work@sky130_fd_sc_hd__a222oi.nand2), line:63:10, endln:63:61 |vpiParent: - \_module: work@sky130_fd_sc_hd__a222oi (work@sky130_fd_sc_hd__a222oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a222oi.functional.v, line:35:1, endln:67:10 + \_module_inst: work@sky130_fd_sc_hd__a222oi (work@sky130_fd_sc_hd__a222oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a222oi.functional.v, line:35:1, endln:67:10 |vpiDefName:work@nand |vpiName:nand2 |vpiFullName:work@sky130_fd_sc_hd__a222oi.nand2 @@ -11768,7 +11768,7 @@ design: (work@sky130_fd_sc_hd__a222oi) |vpiPrimitive: \_gate: work@and (work@sky130_fd_sc_hd__a222oi.and0), line:64:10, endln:64:61 |vpiParent: - \_module: work@sky130_fd_sc_hd__a222oi (work@sky130_fd_sc_hd__a222oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a222oi.functional.v, line:35:1, endln:67:10 + \_module_inst: work@sky130_fd_sc_hd__a222oi (work@sky130_fd_sc_hd__a222oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a222oi.functional.v, line:35:1, endln:67:10 |vpiDefName:work@and |vpiName:and0 |vpiFullName:work@sky130_fd_sc_hd__a222oi.and0 @@ -11831,7 +11831,7 @@ design: (work@sky130_fd_sc_hd__a222oi) |vpiPrimitive: \_gate: work@buf (work@sky130_fd_sc_hd__a222oi.buf0), line:65:10, endln:65:61 |vpiParent: - \_module: work@sky130_fd_sc_hd__a222oi (work@sky130_fd_sc_hd__a222oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a222oi.functional.v, line:35:1, endln:67:10 + \_module_inst: work@sky130_fd_sc_hd__a222oi (work@sky130_fd_sc_hd__a222oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a222oi.functional.v, line:35:1, endln:67:10 |vpiDefName:work@buf |vpiName:buf0 |vpiFullName:work@sky130_fd_sc_hd__a222oi.buf0 @@ -11874,7 +11874,7 @@ Processing: -cd cells/cells -DUNIT_DELAY -writepp -parse -nocache -nobuiltin -no design: (work@sky130_fd_sc_hd__clkdlybuf4s25) |vpiName:work@sky130_fd_sc_hd__clkdlybuf4s25 |uhdmallModules: -\_module: work@sky130_fd_sc_hd__clkdlybuf4s25 (work@sky130_fd_sc_hd__clkdlybuf4s25), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__clkdlybuf4s25.functional.v, line:34:1, endln:50:10 +\_module_inst: work@sky130_fd_sc_hd__clkdlybuf4s25 (work@sky130_fd_sc_hd__clkdlybuf4s25), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__clkdlybuf4s25.functional.v, line:34:1, endln:50:10 |vpiParent: \_design: (work@sky130_fd_sc_hd__clkdlybuf4s25) |vpiFullName:work@sky130_fd_sc_hd__clkdlybuf4s25 @@ -11882,26 +11882,26 @@ design: (work@sky130_fd_sc_hd__clkdlybuf4s25) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__clkdlybuf4s25.buf0_out_X), line:44:10, endln:44:20 |vpiParent: - \_module: work@sky130_fd_sc_hd__clkdlybuf4s25 (work@sky130_fd_sc_hd__clkdlybuf4s25), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__clkdlybuf4s25.functional.v, line:34:1, endln:50:10 + \_module_inst: work@sky130_fd_sc_hd__clkdlybuf4s25 (work@sky130_fd_sc_hd__clkdlybuf4s25), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__clkdlybuf4s25.functional.v, line:34:1, endln:50:10 |vpiName:buf0_out_X |vpiFullName:work@sky130_fd_sc_hd__clkdlybuf4s25.buf0_out_X |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__clkdlybuf4s25.X), line:35:5, endln:35:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__clkdlybuf4s25 (work@sky130_fd_sc_hd__clkdlybuf4s25), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__clkdlybuf4s25.functional.v, line:34:1, endln:50:10 + \_module_inst: work@sky130_fd_sc_hd__clkdlybuf4s25 (work@sky130_fd_sc_hd__clkdlybuf4s25), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__clkdlybuf4s25.functional.v, line:34:1, endln:50:10 |vpiName:X |vpiFullName:work@sky130_fd_sc_hd__clkdlybuf4s25.X |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__clkdlybuf4s25.A), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__clkdlybuf4s25 (work@sky130_fd_sc_hd__clkdlybuf4s25), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__clkdlybuf4s25.functional.v, line:34:1, endln:50:10 + \_module_inst: work@sky130_fd_sc_hd__clkdlybuf4s25 (work@sky130_fd_sc_hd__clkdlybuf4s25), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__clkdlybuf4s25.functional.v, line:34:1, endln:50:10 |vpiName:A |vpiFullName:work@sky130_fd_sc_hd__clkdlybuf4s25.A |vpiPort: \_port: (X), line:35:5, endln:35:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__clkdlybuf4s25 (work@sky130_fd_sc_hd__clkdlybuf4s25), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__clkdlybuf4s25.functional.v, line:34:1, endln:50:10 + \_module_inst: work@sky130_fd_sc_hd__clkdlybuf4s25 (work@sky130_fd_sc_hd__clkdlybuf4s25), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__clkdlybuf4s25.functional.v, line:34:1, endln:50:10 |vpiName:X |vpiDirection:2 |vpiLowConn: @@ -11913,7 +11913,7 @@ design: (work@sky130_fd_sc_hd__clkdlybuf4s25) |vpiPort: \_port: (A), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__clkdlybuf4s25 (work@sky130_fd_sc_hd__clkdlybuf4s25), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__clkdlybuf4s25.functional.v, line:34:1, endln:50:10 + \_module_inst: work@sky130_fd_sc_hd__clkdlybuf4s25 (work@sky130_fd_sc_hd__clkdlybuf4s25), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__clkdlybuf4s25.functional.v, line:34:1, endln:50:10 |vpiName:A |vpiDirection:1 |vpiLowConn: @@ -11923,14 +11923,14 @@ design: (work@sky130_fd_sc_hd__clkdlybuf4s25) |vpiTypedef: \_logic_typespec: , line:41:12, endln:41:12 |uhdmtopModules: -\_module: work@sky130_fd_sc_hd__clkdlybuf4s25 (work@sky130_fd_sc_hd__clkdlybuf4s25), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__clkdlybuf4s25.functional.v, line:34:1, endln:50:10 +\_module_inst: work@sky130_fd_sc_hd__clkdlybuf4s25 (work@sky130_fd_sc_hd__clkdlybuf4s25), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__clkdlybuf4s25.functional.v, line:34:1, endln:50:10 |vpiName:work@sky130_fd_sc_hd__clkdlybuf4s25 |vpiDefName:work@sky130_fd_sc_hd__clkdlybuf4s25 |vpiTop:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__clkdlybuf4s25.buf0_out_X), line:44:10, endln:44:20 |vpiParent: - \_module: work@sky130_fd_sc_hd__clkdlybuf4s25 (work@sky130_fd_sc_hd__clkdlybuf4s25), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__clkdlybuf4s25.functional.v, line:34:1, endln:50:10 + \_module_inst: work@sky130_fd_sc_hd__clkdlybuf4s25 (work@sky130_fd_sc_hd__clkdlybuf4s25), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__clkdlybuf4s25.functional.v, line:34:1, endln:50:10 |vpiTypespec: \_logic_typespec: , line:44:5, endln:44:9 |vpiName:buf0_out_X @@ -11939,7 +11939,7 @@ design: (work@sky130_fd_sc_hd__clkdlybuf4s25) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__clkdlybuf4s25.X), line:35:5, endln:35:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__clkdlybuf4s25 (work@sky130_fd_sc_hd__clkdlybuf4s25), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__clkdlybuf4s25.functional.v, line:34:1, endln:50:10 + \_module_inst: work@sky130_fd_sc_hd__clkdlybuf4s25 (work@sky130_fd_sc_hd__clkdlybuf4s25), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__clkdlybuf4s25.functional.v, line:34:1, endln:50:10 |vpiTypespec: \_logic_typespec: , line:40:12, endln:40:12 |vpiName:X @@ -11947,7 +11947,7 @@ design: (work@sky130_fd_sc_hd__clkdlybuf4s25) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__clkdlybuf4s25.A), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__clkdlybuf4s25 (work@sky130_fd_sc_hd__clkdlybuf4s25), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__clkdlybuf4s25.functional.v, line:34:1, endln:50:10 + \_module_inst: work@sky130_fd_sc_hd__clkdlybuf4s25 (work@sky130_fd_sc_hd__clkdlybuf4s25), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__clkdlybuf4s25.functional.v, line:34:1, endln:50:10 |vpiTypespec: \_logic_typespec: , line:41:12, endln:41:12 |vpiName:A @@ -11956,7 +11956,7 @@ design: (work@sky130_fd_sc_hd__clkdlybuf4s25) |vpiPort: \_port: (X), line:35:5, endln:35:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__clkdlybuf4s25 (work@sky130_fd_sc_hd__clkdlybuf4s25), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__clkdlybuf4s25.functional.v, line:34:1, endln:50:10 + \_module_inst: work@sky130_fd_sc_hd__clkdlybuf4s25 (work@sky130_fd_sc_hd__clkdlybuf4s25), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__clkdlybuf4s25.functional.v, line:34:1, endln:50:10 |vpiName:X |vpiDirection:2 |vpiLowConn: @@ -11970,7 +11970,7 @@ design: (work@sky130_fd_sc_hd__clkdlybuf4s25) |vpiPort: \_port: (A), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__clkdlybuf4s25 (work@sky130_fd_sc_hd__clkdlybuf4s25), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__clkdlybuf4s25.functional.v, line:34:1, endln:50:10 + \_module_inst: work@sky130_fd_sc_hd__clkdlybuf4s25 (work@sky130_fd_sc_hd__clkdlybuf4s25), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__clkdlybuf4s25.functional.v, line:34:1, endln:50:10 |vpiName:A |vpiDirection:1 |vpiLowConn: @@ -11984,7 +11984,7 @@ design: (work@sky130_fd_sc_hd__clkdlybuf4s25) |vpiPrimitive: \_gate: work@buf (work@sky130_fd_sc_hd__clkdlybuf4s25.buf0), line:47:9, endln:47:43 |vpiParent: - \_module: work@sky130_fd_sc_hd__clkdlybuf4s25 (work@sky130_fd_sc_hd__clkdlybuf4s25), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__clkdlybuf4s25.functional.v, line:34:1, endln:50:10 + \_module_inst: work@sky130_fd_sc_hd__clkdlybuf4s25 (work@sky130_fd_sc_hd__clkdlybuf4s25), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__clkdlybuf4s25.functional.v, line:34:1, endln:50:10 |vpiDefName:work@buf |vpiName:buf0 |vpiFullName:work@sky130_fd_sc_hd__clkdlybuf4s25.buf0 @@ -12019,7 +12019,7 @@ design: (work@sky130_fd_sc_hd__clkdlybuf4s25) |vpiPrimitive: \_gate: work@buf (work@sky130_fd_sc_hd__clkdlybuf4s25.buf1), line:48:9, endln:48:43 |vpiParent: - \_module: work@sky130_fd_sc_hd__clkdlybuf4s25 (work@sky130_fd_sc_hd__clkdlybuf4s25), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__clkdlybuf4s25.functional.v, line:34:1, endln:50:10 + \_module_inst: work@sky130_fd_sc_hd__clkdlybuf4s25 (work@sky130_fd_sc_hd__clkdlybuf4s25), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__clkdlybuf4s25.functional.v, line:34:1, endln:50:10 |vpiDefName:work@buf |vpiName:buf1 |vpiFullName:work@sky130_fd_sc_hd__clkdlybuf4s25.buf1 @@ -12062,7 +12062,7 @@ Processing: -cd cells/cells -DUNIT_DELAY -writepp -parse -nocache -nobuiltin -no design: (work@sky130_fd_sc_hd__or4bb) |vpiName:work@sky130_fd_sc_hd__or4bb |uhdmallModules: -\_module: work@sky130_fd_sc_hd__or4bb (work@sky130_fd_sc_hd__or4bb), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or4bb.functional.v, line:33:1, endln:57:10 +\_module_inst: work@sky130_fd_sc_hd__or4bb (work@sky130_fd_sc_hd__or4bb), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or4bb.functional.v, line:33:1, endln:57:10 |vpiParent: \_design: (work@sky130_fd_sc_hd__or4bb) |vpiFullName:work@sky130_fd_sc_hd__or4bb @@ -12070,51 +12070,51 @@ design: (work@sky130_fd_sc_hd__or4bb) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__or4bb.nand0_out), line:49:10, endln:49:19 |vpiParent: - \_module: work@sky130_fd_sc_hd__or4bb (work@sky130_fd_sc_hd__or4bb), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or4bb.functional.v, line:33:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__or4bb (work@sky130_fd_sc_hd__or4bb), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or4bb.functional.v, line:33:1, endln:57:10 |vpiName:nand0_out |vpiFullName:work@sky130_fd_sc_hd__or4bb.nand0_out |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__or4bb.or0_out_X), line:50:10, endln:50:19 |vpiParent: - \_module: work@sky130_fd_sc_hd__or4bb (work@sky130_fd_sc_hd__or4bb), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or4bb.functional.v, line:33:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__or4bb (work@sky130_fd_sc_hd__or4bb), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or4bb.functional.v, line:33:1, endln:57:10 |vpiName:or0_out_X |vpiFullName:work@sky130_fd_sc_hd__or4bb.or0_out_X |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__or4bb.X), line:34:5, endln:34:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__or4bb (work@sky130_fd_sc_hd__or4bb), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or4bb.functional.v, line:33:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__or4bb (work@sky130_fd_sc_hd__or4bb), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or4bb.functional.v, line:33:1, endln:57:10 |vpiName:X |vpiFullName:work@sky130_fd_sc_hd__or4bb.X |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__or4bb.A), line:35:5, endln:35:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__or4bb (work@sky130_fd_sc_hd__or4bb), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or4bb.functional.v, line:33:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__or4bb (work@sky130_fd_sc_hd__or4bb), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or4bb.functional.v, line:33:1, endln:57:10 |vpiName:A |vpiFullName:work@sky130_fd_sc_hd__or4bb.A |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__or4bb.B), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__or4bb (work@sky130_fd_sc_hd__or4bb), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or4bb.functional.v, line:33:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__or4bb (work@sky130_fd_sc_hd__or4bb), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or4bb.functional.v, line:33:1, endln:57:10 |vpiName:B |vpiFullName:work@sky130_fd_sc_hd__or4bb.B |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__or4bb.C_N), line:37:5, endln:37:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__or4bb (work@sky130_fd_sc_hd__or4bb), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or4bb.functional.v, line:33:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__or4bb (work@sky130_fd_sc_hd__or4bb), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or4bb.functional.v, line:33:1, endln:57:10 |vpiName:C_N |vpiFullName:work@sky130_fd_sc_hd__or4bb.C_N |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__or4bb.D_N), line:38:5, endln:38:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__or4bb (work@sky130_fd_sc_hd__or4bb), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or4bb.functional.v, line:33:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__or4bb (work@sky130_fd_sc_hd__or4bb), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or4bb.functional.v, line:33:1, endln:57:10 |vpiName:D_N |vpiFullName:work@sky130_fd_sc_hd__or4bb.D_N |vpiPort: \_port: (X), line:34:5, endln:34:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__or4bb (work@sky130_fd_sc_hd__or4bb), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or4bb.functional.v, line:33:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__or4bb (work@sky130_fd_sc_hd__or4bb), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or4bb.functional.v, line:33:1, endln:57:10 |vpiName:X |vpiDirection:2 |vpiLowConn: @@ -12126,7 +12126,7 @@ design: (work@sky130_fd_sc_hd__or4bb) |vpiPort: \_port: (A), line:35:5, endln:35:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__or4bb (work@sky130_fd_sc_hd__or4bb), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or4bb.functional.v, line:33:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__or4bb (work@sky130_fd_sc_hd__or4bb), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or4bb.functional.v, line:33:1, endln:57:10 |vpiName:A |vpiDirection:1 |vpiLowConn: @@ -12138,7 +12138,7 @@ design: (work@sky130_fd_sc_hd__or4bb) |vpiPort: \_port: (B), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__or4bb (work@sky130_fd_sc_hd__or4bb), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or4bb.functional.v, line:33:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__or4bb (work@sky130_fd_sc_hd__or4bb), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or4bb.functional.v, line:33:1, endln:57:10 |vpiName:B |vpiDirection:1 |vpiLowConn: @@ -12150,7 +12150,7 @@ design: (work@sky130_fd_sc_hd__or4bb) |vpiPort: \_port: (C_N), line:37:5, endln:37:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__or4bb (work@sky130_fd_sc_hd__or4bb), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or4bb.functional.v, line:33:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__or4bb (work@sky130_fd_sc_hd__or4bb), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or4bb.functional.v, line:33:1, endln:57:10 |vpiName:C_N |vpiDirection:1 |vpiLowConn: @@ -12162,7 +12162,7 @@ design: (work@sky130_fd_sc_hd__or4bb) |vpiPort: \_port: (D_N), line:38:5, endln:38:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__or4bb (work@sky130_fd_sc_hd__or4bb), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or4bb.functional.v, line:33:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__or4bb (work@sky130_fd_sc_hd__or4bb), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or4bb.functional.v, line:33:1, endln:57:10 |vpiName:D_N |vpiDirection:1 |vpiLowConn: @@ -12172,14 +12172,14 @@ design: (work@sky130_fd_sc_hd__or4bb) |vpiTypedef: \_logic_typespec: , line:46:12, endln:46:12 |uhdmtopModules: -\_module: work@sky130_fd_sc_hd__or4bb (work@sky130_fd_sc_hd__or4bb), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or4bb.functional.v, line:33:1, endln:57:10 +\_module_inst: work@sky130_fd_sc_hd__or4bb (work@sky130_fd_sc_hd__or4bb), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or4bb.functional.v, line:33:1, endln:57:10 |vpiName:work@sky130_fd_sc_hd__or4bb |vpiDefName:work@sky130_fd_sc_hd__or4bb |vpiTop:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__or4bb.nand0_out), line:49:10, endln:49:19 |vpiParent: - \_module: work@sky130_fd_sc_hd__or4bb (work@sky130_fd_sc_hd__or4bb), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or4bb.functional.v, line:33:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__or4bb (work@sky130_fd_sc_hd__or4bb), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or4bb.functional.v, line:33:1, endln:57:10 |vpiTypespec: \_logic_typespec: , line:49:5, endln:49:9 |vpiName:nand0_out @@ -12188,7 +12188,7 @@ design: (work@sky130_fd_sc_hd__or4bb) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__or4bb.or0_out_X), line:50:10, endln:50:19 |vpiParent: - \_module: work@sky130_fd_sc_hd__or4bb (work@sky130_fd_sc_hd__or4bb), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or4bb.functional.v, line:33:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__or4bb (work@sky130_fd_sc_hd__or4bb), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or4bb.functional.v, line:33:1, endln:57:10 |vpiTypespec: \_logic_typespec: , line:50:5, endln:50:9 |vpiName:or0_out_X @@ -12197,7 +12197,7 @@ design: (work@sky130_fd_sc_hd__or4bb) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__or4bb.X), line:34:5, endln:34:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__or4bb (work@sky130_fd_sc_hd__or4bb), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or4bb.functional.v, line:33:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__or4bb (work@sky130_fd_sc_hd__or4bb), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or4bb.functional.v, line:33:1, endln:57:10 |vpiTypespec: \_logic_typespec: , line:42:12, endln:42:12 |vpiName:X @@ -12205,7 +12205,7 @@ design: (work@sky130_fd_sc_hd__or4bb) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__or4bb.A), line:35:5, endln:35:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__or4bb (work@sky130_fd_sc_hd__or4bb), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or4bb.functional.v, line:33:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__or4bb (work@sky130_fd_sc_hd__or4bb), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or4bb.functional.v, line:33:1, endln:57:10 |vpiTypespec: \_logic_typespec: , line:43:12, endln:43:12 |vpiName:A @@ -12213,7 +12213,7 @@ design: (work@sky130_fd_sc_hd__or4bb) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__or4bb.B), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__or4bb (work@sky130_fd_sc_hd__or4bb), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or4bb.functional.v, line:33:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__or4bb (work@sky130_fd_sc_hd__or4bb), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or4bb.functional.v, line:33:1, endln:57:10 |vpiTypespec: \_logic_typespec: , line:44:12, endln:44:12 |vpiName:B @@ -12221,7 +12221,7 @@ design: (work@sky130_fd_sc_hd__or4bb) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__or4bb.C_N), line:37:5, endln:37:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__or4bb (work@sky130_fd_sc_hd__or4bb), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or4bb.functional.v, line:33:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__or4bb (work@sky130_fd_sc_hd__or4bb), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or4bb.functional.v, line:33:1, endln:57:10 |vpiTypespec: \_logic_typespec: , line:45:12, endln:45:12 |vpiName:C_N @@ -12229,7 +12229,7 @@ design: (work@sky130_fd_sc_hd__or4bb) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__or4bb.D_N), line:38:5, endln:38:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__or4bb (work@sky130_fd_sc_hd__or4bb), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or4bb.functional.v, line:33:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__or4bb (work@sky130_fd_sc_hd__or4bb), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or4bb.functional.v, line:33:1, endln:57:10 |vpiTypespec: \_logic_typespec: , line:46:12, endln:46:12 |vpiName:D_N @@ -12238,7 +12238,7 @@ design: (work@sky130_fd_sc_hd__or4bb) |vpiPort: \_port: (X), line:34:5, endln:34:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__or4bb (work@sky130_fd_sc_hd__or4bb), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or4bb.functional.v, line:33:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__or4bb (work@sky130_fd_sc_hd__or4bb), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or4bb.functional.v, line:33:1, endln:57:10 |vpiName:X |vpiDirection:2 |vpiLowConn: @@ -12252,7 +12252,7 @@ design: (work@sky130_fd_sc_hd__or4bb) |vpiPort: \_port: (A), line:35:5, endln:35:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__or4bb (work@sky130_fd_sc_hd__or4bb), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or4bb.functional.v, line:33:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__or4bb (work@sky130_fd_sc_hd__or4bb), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or4bb.functional.v, line:33:1, endln:57:10 |vpiName:A |vpiDirection:1 |vpiLowConn: @@ -12266,7 +12266,7 @@ design: (work@sky130_fd_sc_hd__or4bb) |vpiPort: \_port: (B), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__or4bb (work@sky130_fd_sc_hd__or4bb), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or4bb.functional.v, line:33:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__or4bb (work@sky130_fd_sc_hd__or4bb), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or4bb.functional.v, line:33:1, endln:57:10 |vpiName:B |vpiDirection:1 |vpiLowConn: @@ -12280,7 +12280,7 @@ design: (work@sky130_fd_sc_hd__or4bb) |vpiPort: \_port: (C_N), line:37:5, endln:37:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__or4bb (work@sky130_fd_sc_hd__or4bb), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or4bb.functional.v, line:33:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__or4bb (work@sky130_fd_sc_hd__or4bb), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or4bb.functional.v, line:33:1, endln:57:10 |vpiName:C_N |vpiDirection:1 |vpiLowConn: @@ -12294,7 +12294,7 @@ design: (work@sky130_fd_sc_hd__or4bb) |vpiPort: \_port: (D_N), line:38:5, endln:38:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__or4bb (work@sky130_fd_sc_hd__or4bb), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or4bb.functional.v, line:33:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__or4bb (work@sky130_fd_sc_hd__or4bb), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or4bb.functional.v, line:33:1, endln:57:10 |vpiName:D_N |vpiDirection:1 |vpiLowConn: @@ -12308,7 +12308,7 @@ design: (work@sky130_fd_sc_hd__or4bb) |vpiPrimitive: \_gate: work@nand (work@sky130_fd_sc_hd__or4bb.nand0), line:53:10, endln:53:44 |vpiParent: - \_module: work@sky130_fd_sc_hd__or4bb (work@sky130_fd_sc_hd__or4bb), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or4bb.functional.v, line:33:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__or4bb (work@sky130_fd_sc_hd__or4bb), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or4bb.functional.v, line:33:1, endln:57:10 |vpiDefName:work@nand |vpiName:nand0 |vpiFullName:work@sky130_fd_sc_hd__or4bb.nand0 @@ -12357,7 +12357,7 @@ design: (work@sky130_fd_sc_hd__or4bb) |vpiPrimitive: \_gate: work@or (work@sky130_fd_sc_hd__or4bb.or0), line:54:10, endln:54:44 |vpiParent: - \_module: work@sky130_fd_sc_hd__or4bb (work@sky130_fd_sc_hd__or4bb), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or4bb.functional.v, line:33:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__or4bb (work@sky130_fd_sc_hd__or4bb), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or4bb.functional.v, line:33:1, endln:57:10 |vpiDefName:work@or |vpiName:or0 |vpiFullName:work@sky130_fd_sc_hd__or4bb.or0 @@ -12420,7 +12420,7 @@ design: (work@sky130_fd_sc_hd__or4bb) |vpiPrimitive: \_gate: work@buf (work@sky130_fd_sc_hd__or4bb.buf0), line:55:10, endln:55:44 |vpiParent: - \_module: work@sky130_fd_sc_hd__or4bb (work@sky130_fd_sc_hd__or4bb), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or4bb.functional.v, line:33:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__or4bb (work@sky130_fd_sc_hd__or4bb), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or4bb.functional.v, line:33:1, endln:57:10 |vpiDefName:work@buf |vpiName:buf0 |vpiFullName:work@sky130_fd_sc_hd__or4bb.buf0 @@ -12463,7 +12463,7 @@ Processing: -cd cells/cells -DUNIT_DELAY -writepp -parse -nocache -nobuiltin -no design: (work@sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap) |vpiName:work@sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap |uhdmallModules: -\_module: work@sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap (work@sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap.functional.v, line:36:1, endln:48:10 +\_module_inst: work@sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap (work@sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap.functional.v, line:36:1, endln:48:10 |vpiParent: \_design: (work@sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap) |vpiFullName:work@sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap @@ -12471,19 +12471,19 @@ design: (work@sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap.X), line:37:5, endln:37:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap (work@sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap.functional.v, line:36:1, endln:48:10 + \_module_inst: work@sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap (work@sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap.functional.v, line:36:1, endln:48:10 |vpiName:X |vpiFullName:work@sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap.X |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap.A), line:38:5, endln:38:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap (work@sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap.functional.v, line:36:1, endln:48:10 + \_module_inst: work@sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap (work@sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap.functional.v, line:36:1, endln:48:10 |vpiName:A |vpiFullName:work@sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap.A |vpiPort: \_port: (X), line:37:5, endln:37:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap (work@sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap.functional.v, line:36:1, endln:48:10 + \_module_inst: work@sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap (work@sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap.functional.v, line:36:1, endln:48:10 |vpiName:X |vpiDirection:2 |vpiLowConn: @@ -12495,7 +12495,7 @@ design: (work@sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap) |vpiPort: \_port: (A), line:38:5, endln:38:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap (work@sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap.functional.v, line:36:1, endln:48:10 + \_module_inst: work@sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap (work@sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap.functional.v, line:36:1, endln:48:10 |vpiName:A |vpiDirection:1 |vpiLowConn: @@ -12505,14 +12505,14 @@ design: (work@sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap) |vpiTypedef: \_logic_typespec: , line:43:12, endln:43:12 |uhdmtopModules: -\_module: work@sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap (work@sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap.functional.v, line:36:1, endln:48:10 +\_module_inst: work@sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap (work@sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap.functional.v, line:36:1, endln:48:10 |vpiName:work@sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap |vpiDefName:work@sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap |vpiTop:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap.X), line:37:5, endln:37:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap (work@sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap.functional.v, line:36:1, endln:48:10 + \_module_inst: work@sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap (work@sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap.functional.v, line:36:1, endln:48:10 |vpiTypespec: \_logic_typespec: , line:42:12, endln:42:12 |vpiName:X @@ -12520,7 +12520,7 @@ design: (work@sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap.A), line:38:5, endln:38:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap (work@sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap.functional.v, line:36:1, endln:48:10 + \_module_inst: work@sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap (work@sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap.functional.v, line:36:1, endln:48:10 |vpiTypespec: \_logic_typespec: , line:43:12, endln:43:12 |vpiName:A @@ -12529,7 +12529,7 @@ design: (work@sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap) |vpiPort: \_port: (X), line:37:5, endln:37:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap (work@sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap.functional.v, line:36:1, endln:48:10 + \_module_inst: work@sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap (work@sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap.functional.v, line:36:1, endln:48:10 |vpiName:X |vpiDirection:2 |vpiLowConn: @@ -12543,7 +12543,7 @@ design: (work@sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap) |vpiPort: \_port: (A), line:38:5, endln:38:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap (work@sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap.functional.v, line:36:1, endln:48:10 + \_module_inst: work@sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap (work@sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap.functional.v, line:36:1, endln:48:10 |vpiName:A |vpiDirection:1 |vpiLowConn: @@ -12557,7 +12557,7 @@ design: (work@sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap) |vpiPrimitive: \_gate: work@buf (work@sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap.buf0), line:46:9, endln:46:39 |vpiParent: - \_module: work@sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap (work@sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap.functional.v, line:36:1, endln:48:10 + \_module_inst: work@sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap (work@sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap.functional.v, line:36:1, endln:48:10 |vpiDefName:work@buf |vpiName:buf0 |vpiFullName:work@sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap.buf0 @@ -12600,7 +12600,7 @@ Processing: -cd cells/cells -DUNIT_DELAY -writepp -parse -nocache -nobuiltin -no design: (work@sky130_fd_sc_hd__nor4bb) |vpiName:work@sky130_fd_sc_hd__nor4bb |uhdmallModules: -\_module: work@sky130_fd_sc_hd__nor4bb (work@sky130_fd_sc_hd__nor4bb), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor4bb.functional.v, line:33:1, endln:57:10 +\_module_inst: work@sky130_fd_sc_hd__nor4bb (work@sky130_fd_sc_hd__nor4bb), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor4bb.functional.v, line:33:1, endln:57:10 |vpiParent: \_design: (work@sky130_fd_sc_hd__nor4bb) |vpiFullName:work@sky130_fd_sc_hd__nor4bb @@ -12608,51 +12608,51 @@ design: (work@sky130_fd_sc_hd__nor4bb) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__nor4bb.nor0_out), line:49:10, endln:49:18 |vpiParent: - \_module: work@sky130_fd_sc_hd__nor4bb (work@sky130_fd_sc_hd__nor4bb), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor4bb.functional.v, line:33:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__nor4bb (work@sky130_fd_sc_hd__nor4bb), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor4bb.functional.v, line:33:1, endln:57:10 |vpiName:nor0_out |vpiFullName:work@sky130_fd_sc_hd__nor4bb.nor0_out |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__nor4bb.and0_out_Y), line:50:10, endln:50:20 |vpiParent: - \_module: work@sky130_fd_sc_hd__nor4bb (work@sky130_fd_sc_hd__nor4bb), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor4bb.functional.v, line:33:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__nor4bb (work@sky130_fd_sc_hd__nor4bb), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor4bb.functional.v, line:33:1, endln:57:10 |vpiName:and0_out_Y |vpiFullName:work@sky130_fd_sc_hd__nor4bb.and0_out_Y |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__nor4bb.Y), line:34:5, endln:34:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__nor4bb (work@sky130_fd_sc_hd__nor4bb), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor4bb.functional.v, line:33:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__nor4bb (work@sky130_fd_sc_hd__nor4bb), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor4bb.functional.v, line:33:1, endln:57:10 |vpiName:Y |vpiFullName:work@sky130_fd_sc_hd__nor4bb.Y |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__nor4bb.A), line:35:5, endln:35:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__nor4bb (work@sky130_fd_sc_hd__nor4bb), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor4bb.functional.v, line:33:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__nor4bb (work@sky130_fd_sc_hd__nor4bb), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor4bb.functional.v, line:33:1, endln:57:10 |vpiName:A |vpiFullName:work@sky130_fd_sc_hd__nor4bb.A |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__nor4bb.B), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__nor4bb (work@sky130_fd_sc_hd__nor4bb), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor4bb.functional.v, line:33:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__nor4bb (work@sky130_fd_sc_hd__nor4bb), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor4bb.functional.v, line:33:1, endln:57:10 |vpiName:B |vpiFullName:work@sky130_fd_sc_hd__nor4bb.B |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__nor4bb.C_N), line:37:5, endln:37:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__nor4bb (work@sky130_fd_sc_hd__nor4bb), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor4bb.functional.v, line:33:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__nor4bb (work@sky130_fd_sc_hd__nor4bb), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor4bb.functional.v, line:33:1, endln:57:10 |vpiName:C_N |vpiFullName:work@sky130_fd_sc_hd__nor4bb.C_N |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__nor4bb.D_N), line:38:5, endln:38:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__nor4bb (work@sky130_fd_sc_hd__nor4bb), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor4bb.functional.v, line:33:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__nor4bb (work@sky130_fd_sc_hd__nor4bb), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor4bb.functional.v, line:33:1, endln:57:10 |vpiName:D_N |vpiFullName:work@sky130_fd_sc_hd__nor4bb.D_N |vpiPort: \_port: (Y), line:34:5, endln:34:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__nor4bb (work@sky130_fd_sc_hd__nor4bb), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor4bb.functional.v, line:33:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__nor4bb (work@sky130_fd_sc_hd__nor4bb), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor4bb.functional.v, line:33:1, endln:57:10 |vpiName:Y |vpiDirection:2 |vpiLowConn: @@ -12664,7 +12664,7 @@ design: (work@sky130_fd_sc_hd__nor4bb) |vpiPort: \_port: (A), line:35:5, endln:35:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__nor4bb (work@sky130_fd_sc_hd__nor4bb), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor4bb.functional.v, line:33:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__nor4bb (work@sky130_fd_sc_hd__nor4bb), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor4bb.functional.v, line:33:1, endln:57:10 |vpiName:A |vpiDirection:1 |vpiLowConn: @@ -12676,7 +12676,7 @@ design: (work@sky130_fd_sc_hd__nor4bb) |vpiPort: \_port: (B), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__nor4bb (work@sky130_fd_sc_hd__nor4bb), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor4bb.functional.v, line:33:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__nor4bb (work@sky130_fd_sc_hd__nor4bb), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor4bb.functional.v, line:33:1, endln:57:10 |vpiName:B |vpiDirection:1 |vpiLowConn: @@ -12688,7 +12688,7 @@ design: (work@sky130_fd_sc_hd__nor4bb) |vpiPort: \_port: (C_N), line:37:5, endln:37:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__nor4bb (work@sky130_fd_sc_hd__nor4bb), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor4bb.functional.v, line:33:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__nor4bb (work@sky130_fd_sc_hd__nor4bb), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor4bb.functional.v, line:33:1, endln:57:10 |vpiName:C_N |vpiDirection:1 |vpiLowConn: @@ -12700,7 +12700,7 @@ design: (work@sky130_fd_sc_hd__nor4bb) |vpiPort: \_port: (D_N), line:38:5, endln:38:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__nor4bb (work@sky130_fd_sc_hd__nor4bb), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor4bb.functional.v, line:33:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__nor4bb (work@sky130_fd_sc_hd__nor4bb), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor4bb.functional.v, line:33:1, endln:57:10 |vpiName:D_N |vpiDirection:1 |vpiLowConn: @@ -12710,14 +12710,14 @@ design: (work@sky130_fd_sc_hd__nor4bb) |vpiTypedef: \_logic_typespec: , line:46:12, endln:46:12 |uhdmtopModules: -\_module: work@sky130_fd_sc_hd__nor4bb (work@sky130_fd_sc_hd__nor4bb), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor4bb.functional.v, line:33:1, endln:57:10 +\_module_inst: work@sky130_fd_sc_hd__nor4bb (work@sky130_fd_sc_hd__nor4bb), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor4bb.functional.v, line:33:1, endln:57:10 |vpiName:work@sky130_fd_sc_hd__nor4bb |vpiDefName:work@sky130_fd_sc_hd__nor4bb |vpiTop:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__nor4bb.nor0_out), line:49:10, endln:49:18 |vpiParent: - \_module: work@sky130_fd_sc_hd__nor4bb (work@sky130_fd_sc_hd__nor4bb), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor4bb.functional.v, line:33:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__nor4bb (work@sky130_fd_sc_hd__nor4bb), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor4bb.functional.v, line:33:1, endln:57:10 |vpiTypespec: \_logic_typespec: , line:49:5, endln:49:9 |vpiName:nor0_out @@ -12726,7 +12726,7 @@ design: (work@sky130_fd_sc_hd__nor4bb) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__nor4bb.and0_out_Y), line:50:10, endln:50:20 |vpiParent: - \_module: work@sky130_fd_sc_hd__nor4bb (work@sky130_fd_sc_hd__nor4bb), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor4bb.functional.v, line:33:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__nor4bb (work@sky130_fd_sc_hd__nor4bb), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor4bb.functional.v, line:33:1, endln:57:10 |vpiTypespec: \_logic_typespec: , line:50:5, endln:50:9 |vpiName:and0_out_Y @@ -12735,7 +12735,7 @@ design: (work@sky130_fd_sc_hd__nor4bb) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__nor4bb.Y), line:34:5, endln:34:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__nor4bb (work@sky130_fd_sc_hd__nor4bb), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor4bb.functional.v, line:33:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__nor4bb (work@sky130_fd_sc_hd__nor4bb), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor4bb.functional.v, line:33:1, endln:57:10 |vpiTypespec: \_logic_typespec: , line:42:12, endln:42:12 |vpiName:Y @@ -12743,7 +12743,7 @@ design: (work@sky130_fd_sc_hd__nor4bb) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__nor4bb.A), line:35:5, endln:35:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__nor4bb (work@sky130_fd_sc_hd__nor4bb), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor4bb.functional.v, line:33:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__nor4bb (work@sky130_fd_sc_hd__nor4bb), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor4bb.functional.v, line:33:1, endln:57:10 |vpiTypespec: \_logic_typespec: , line:43:12, endln:43:12 |vpiName:A @@ -12751,7 +12751,7 @@ design: (work@sky130_fd_sc_hd__nor4bb) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__nor4bb.B), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__nor4bb (work@sky130_fd_sc_hd__nor4bb), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor4bb.functional.v, line:33:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__nor4bb (work@sky130_fd_sc_hd__nor4bb), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor4bb.functional.v, line:33:1, endln:57:10 |vpiTypespec: \_logic_typespec: , line:44:12, endln:44:12 |vpiName:B @@ -12759,7 +12759,7 @@ design: (work@sky130_fd_sc_hd__nor4bb) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__nor4bb.C_N), line:37:5, endln:37:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__nor4bb (work@sky130_fd_sc_hd__nor4bb), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor4bb.functional.v, line:33:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__nor4bb (work@sky130_fd_sc_hd__nor4bb), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor4bb.functional.v, line:33:1, endln:57:10 |vpiTypespec: \_logic_typespec: , line:45:12, endln:45:12 |vpiName:C_N @@ -12767,7 +12767,7 @@ design: (work@sky130_fd_sc_hd__nor4bb) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__nor4bb.D_N), line:38:5, endln:38:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__nor4bb (work@sky130_fd_sc_hd__nor4bb), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor4bb.functional.v, line:33:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__nor4bb (work@sky130_fd_sc_hd__nor4bb), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor4bb.functional.v, line:33:1, endln:57:10 |vpiTypespec: \_logic_typespec: , line:46:12, endln:46:12 |vpiName:D_N @@ -12776,7 +12776,7 @@ design: (work@sky130_fd_sc_hd__nor4bb) |vpiPort: \_port: (Y), line:34:5, endln:34:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__nor4bb (work@sky130_fd_sc_hd__nor4bb), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor4bb.functional.v, line:33:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__nor4bb (work@sky130_fd_sc_hd__nor4bb), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor4bb.functional.v, line:33:1, endln:57:10 |vpiName:Y |vpiDirection:2 |vpiLowConn: @@ -12790,7 +12790,7 @@ design: (work@sky130_fd_sc_hd__nor4bb) |vpiPort: \_port: (A), line:35:5, endln:35:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__nor4bb (work@sky130_fd_sc_hd__nor4bb), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor4bb.functional.v, line:33:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__nor4bb (work@sky130_fd_sc_hd__nor4bb), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor4bb.functional.v, line:33:1, endln:57:10 |vpiName:A |vpiDirection:1 |vpiLowConn: @@ -12804,7 +12804,7 @@ design: (work@sky130_fd_sc_hd__nor4bb) |vpiPort: \_port: (B), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__nor4bb (work@sky130_fd_sc_hd__nor4bb), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor4bb.functional.v, line:33:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__nor4bb (work@sky130_fd_sc_hd__nor4bb), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor4bb.functional.v, line:33:1, endln:57:10 |vpiName:B |vpiDirection:1 |vpiLowConn: @@ -12818,7 +12818,7 @@ design: (work@sky130_fd_sc_hd__nor4bb) |vpiPort: \_port: (C_N), line:37:5, endln:37:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__nor4bb (work@sky130_fd_sc_hd__nor4bb), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor4bb.functional.v, line:33:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__nor4bb (work@sky130_fd_sc_hd__nor4bb), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor4bb.functional.v, line:33:1, endln:57:10 |vpiName:C_N |vpiDirection:1 |vpiLowConn: @@ -12832,7 +12832,7 @@ design: (work@sky130_fd_sc_hd__nor4bb) |vpiPort: \_port: (D_N), line:38:5, endln:38:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__nor4bb (work@sky130_fd_sc_hd__nor4bb), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor4bb.functional.v, line:33:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__nor4bb (work@sky130_fd_sc_hd__nor4bb), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor4bb.functional.v, line:33:1, endln:57:10 |vpiName:D_N |vpiDirection:1 |vpiLowConn: @@ -12846,7 +12846,7 @@ design: (work@sky130_fd_sc_hd__nor4bb) |vpiPrimitive: \_gate: work@nor (work@sky130_fd_sc_hd__nor4bb.nor0), line:53:9, endln:53:46 |vpiParent: - \_module: work@sky130_fd_sc_hd__nor4bb (work@sky130_fd_sc_hd__nor4bb), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor4bb.functional.v, line:33:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__nor4bb (work@sky130_fd_sc_hd__nor4bb), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor4bb.functional.v, line:33:1, endln:57:10 |vpiDefName:work@nor |vpiName:nor0 |vpiFullName:work@sky130_fd_sc_hd__nor4bb.nor0 @@ -12895,7 +12895,7 @@ design: (work@sky130_fd_sc_hd__nor4bb) |vpiPrimitive: \_gate: work@and (work@sky130_fd_sc_hd__nor4bb.and0), line:54:9, endln:54:46 |vpiParent: - \_module: work@sky130_fd_sc_hd__nor4bb (work@sky130_fd_sc_hd__nor4bb), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor4bb.functional.v, line:33:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__nor4bb (work@sky130_fd_sc_hd__nor4bb), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor4bb.functional.v, line:33:1, endln:57:10 |vpiDefName:work@and |vpiName:and0 |vpiFullName:work@sky130_fd_sc_hd__nor4bb.and0 @@ -12958,7 +12958,7 @@ design: (work@sky130_fd_sc_hd__nor4bb) |vpiPrimitive: \_gate: work@buf (work@sky130_fd_sc_hd__nor4bb.buf0), line:55:9, endln:55:46 |vpiParent: - \_module: work@sky130_fd_sc_hd__nor4bb (work@sky130_fd_sc_hd__nor4bb), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor4bb.functional.v, line:33:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__nor4bb (work@sky130_fd_sc_hd__nor4bb), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor4bb.functional.v, line:33:1, endln:57:10 |vpiDefName:work@buf |vpiName:buf0 |vpiFullName:work@sky130_fd_sc_hd__nor4bb.buf0 @@ -13001,7 +13001,7 @@ Processing: -cd cells/cells -DUNIT_DELAY -writepp -parse -nocache -nobuiltin -no design: (work@sky130_fd_sc_hd__nand3) |vpiName:work@sky130_fd_sc_hd__nand3 |uhdmallModules: -\_module: work@sky130_fd_sc_hd__nand3 (work@sky130_fd_sc_hd__nand3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand3.functional.v, line:33:1, endln:53:10 +\_module_inst: work@sky130_fd_sc_hd__nand3 (work@sky130_fd_sc_hd__nand3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand3.functional.v, line:33:1, endln:53:10 |vpiParent: \_design: (work@sky130_fd_sc_hd__nand3) |vpiFullName:work@sky130_fd_sc_hd__nand3 @@ -13009,38 +13009,38 @@ design: (work@sky130_fd_sc_hd__nand3) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__nand3.nand0_out_Y), line:47:10, endln:47:21 |vpiParent: - \_module: work@sky130_fd_sc_hd__nand3 (work@sky130_fd_sc_hd__nand3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand3.functional.v, line:33:1, endln:53:10 + \_module_inst: work@sky130_fd_sc_hd__nand3 (work@sky130_fd_sc_hd__nand3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand3.functional.v, line:33:1, endln:53:10 |vpiName:nand0_out_Y |vpiFullName:work@sky130_fd_sc_hd__nand3.nand0_out_Y |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__nand3.Y), line:34:5, endln:34:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__nand3 (work@sky130_fd_sc_hd__nand3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand3.functional.v, line:33:1, endln:53:10 + \_module_inst: work@sky130_fd_sc_hd__nand3 (work@sky130_fd_sc_hd__nand3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand3.functional.v, line:33:1, endln:53:10 |vpiName:Y |vpiFullName:work@sky130_fd_sc_hd__nand3.Y |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__nand3.A), line:35:5, endln:35:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__nand3 (work@sky130_fd_sc_hd__nand3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand3.functional.v, line:33:1, endln:53:10 + \_module_inst: work@sky130_fd_sc_hd__nand3 (work@sky130_fd_sc_hd__nand3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand3.functional.v, line:33:1, endln:53:10 |vpiName:A |vpiFullName:work@sky130_fd_sc_hd__nand3.A |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__nand3.B), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__nand3 (work@sky130_fd_sc_hd__nand3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand3.functional.v, line:33:1, endln:53:10 + \_module_inst: work@sky130_fd_sc_hd__nand3 (work@sky130_fd_sc_hd__nand3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand3.functional.v, line:33:1, endln:53:10 |vpiName:B |vpiFullName:work@sky130_fd_sc_hd__nand3.B |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__nand3.C), line:37:5, endln:37:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__nand3 (work@sky130_fd_sc_hd__nand3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand3.functional.v, line:33:1, endln:53:10 + \_module_inst: work@sky130_fd_sc_hd__nand3 (work@sky130_fd_sc_hd__nand3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand3.functional.v, line:33:1, endln:53:10 |vpiName:C |vpiFullName:work@sky130_fd_sc_hd__nand3.C |vpiPort: \_port: (Y), line:34:5, endln:34:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__nand3 (work@sky130_fd_sc_hd__nand3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand3.functional.v, line:33:1, endln:53:10 + \_module_inst: work@sky130_fd_sc_hd__nand3 (work@sky130_fd_sc_hd__nand3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand3.functional.v, line:33:1, endln:53:10 |vpiName:Y |vpiDirection:2 |vpiLowConn: @@ -13052,7 +13052,7 @@ design: (work@sky130_fd_sc_hd__nand3) |vpiPort: \_port: (A), line:35:5, endln:35:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__nand3 (work@sky130_fd_sc_hd__nand3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand3.functional.v, line:33:1, endln:53:10 + \_module_inst: work@sky130_fd_sc_hd__nand3 (work@sky130_fd_sc_hd__nand3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand3.functional.v, line:33:1, endln:53:10 |vpiName:A |vpiDirection:1 |vpiLowConn: @@ -13064,7 +13064,7 @@ design: (work@sky130_fd_sc_hd__nand3) |vpiPort: \_port: (B), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__nand3 (work@sky130_fd_sc_hd__nand3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand3.functional.v, line:33:1, endln:53:10 + \_module_inst: work@sky130_fd_sc_hd__nand3 (work@sky130_fd_sc_hd__nand3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand3.functional.v, line:33:1, endln:53:10 |vpiName:B |vpiDirection:1 |vpiLowConn: @@ -13076,7 +13076,7 @@ design: (work@sky130_fd_sc_hd__nand3) |vpiPort: \_port: (C), line:37:5, endln:37:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__nand3 (work@sky130_fd_sc_hd__nand3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand3.functional.v, line:33:1, endln:53:10 + \_module_inst: work@sky130_fd_sc_hd__nand3 (work@sky130_fd_sc_hd__nand3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand3.functional.v, line:33:1, endln:53:10 |vpiName:C |vpiDirection:1 |vpiLowConn: @@ -13086,14 +13086,14 @@ design: (work@sky130_fd_sc_hd__nand3) |vpiTypedef: \_logic_typespec: , line:44:12, endln:44:12 |uhdmtopModules: -\_module: work@sky130_fd_sc_hd__nand3 (work@sky130_fd_sc_hd__nand3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand3.functional.v, line:33:1, endln:53:10 +\_module_inst: work@sky130_fd_sc_hd__nand3 (work@sky130_fd_sc_hd__nand3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand3.functional.v, line:33:1, endln:53:10 |vpiName:work@sky130_fd_sc_hd__nand3 |vpiDefName:work@sky130_fd_sc_hd__nand3 |vpiTop:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__nand3.nand0_out_Y), line:47:10, endln:47:21 |vpiParent: - \_module: work@sky130_fd_sc_hd__nand3 (work@sky130_fd_sc_hd__nand3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand3.functional.v, line:33:1, endln:53:10 + \_module_inst: work@sky130_fd_sc_hd__nand3 (work@sky130_fd_sc_hd__nand3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand3.functional.v, line:33:1, endln:53:10 |vpiTypespec: \_logic_typespec: , line:47:5, endln:47:9 |vpiName:nand0_out_Y @@ -13102,7 +13102,7 @@ design: (work@sky130_fd_sc_hd__nand3) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__nand3.Y), line:34:5, endln:34:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__nand3 (work@sky130_fd_sc_hd__nand3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand3.functional.v, line:33:1, endln:53:10 + \_module_inst: work@sky130_fd_sc_hd__nand3 (work@sky130_fd_sc_hd__nand3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand3.functional.v, line:33:1, endln:53:10 |vpiTypespec: \_logic_typespec: , line:41:12, endln:41:12 |vpiName:Y @@ -13110,7 +13110,7 @@ design: (work@sky130_fd_sc_hd__nand3) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__nand3.A), line:35:5, endln:35:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__nand3 (work@sky130_fd_sc_hd__nand3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand3.functional.v, line:33:1, endln:53:10 + \_module_inst: work@sky130_fd_sc_hd__nand3 (work@sky130_fd_sc_hd__nand3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand3.functional.v, line:33:1, endln:53:10 |vpiTypespec: \_logic_typespec: , line:42:12, endln:42:12 |vpiName:A @@ -13118,7 +13118,7 @@ design: (work@sky130_fd_sc_hd__nand3) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__nand3.B), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__nand3 (work@sky130_fd_sc_hd__nand3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand3.functional.v, line:33:1, endln:53:10 + \_module_inst: work@sky130_fd_sc_hd__nand3 (work@sky130_fd_sc_hd__nand3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand3.functional.v, line:33:1, endln:53:10 |vpiTypespec: \_logic_typespec: , line:43:12, endln:43:12 |vpiName:B @@ -13126,7 +13126,7 @@ design: (work@sky130_fd_sc_hd__nand3) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__nand3.C), line:37:5, endln:37:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__nand3 (work@sky130_fd_sc_hd__nand3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand3.functional.v, line:33:1, endln:53:10 + \_module_inst: work@sky130_fd_sc_hd__nand3 (work@sky130_fd_sc_hd__nand3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand3.functional.v, line:33:1, endln:53:10 |vpiTypespec: \_logic_typespec: , line:44:12, endln:44:12 |vpiName:C @@ -13135,7 +13135,7 @@ design: (work@sky130_fd_sc_hd__nand3) |vpiPort: \_port: (Y), line:34:5, endln:34:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__nand3 (work@sky130_fd_sc_hd__nand3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand3.functional.v, line:33:1, endln:53:10 + \_module_inst: work@sky130_fd_sc_hd__nand3 (work@sky130_fd_sc_hd__nand3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand3.functional.v, line:33:1, endln:53:10 |vpiName:Y |vpiDirection:2 |vpiLowConn: @@ -13149,7 +13149,7 @@ design: (work@sky130_fd_sc_hd__nand3) |vpiPort: \_port: (A), line:35:5, endln:35:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__nand3 (work@sky130_fd_sc_hd__nand3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand3.functional.v, line:33:1, endln:53:10 + \_module_inst: work@sky130_fd_sc_hd__nand3 (work@sky130_fd_sc_hd__nand3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand3.functional.v, line:33:1, endln:53:10 |vpiName:A |vpiDirection:1 |vpiLowConn: @@ -13163,7 +13163,7 @@ design: (work@sky130_fd_sc_hd__nand3) |vpiPort: \_port: (B), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__nand3 (work@sky130_fd_sc_hd__nand3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand3.functional.v, line:33:1, endln:53:10 + \_module_inst: work@sky130_fd_sc_hd__nand3 (work@sky130_fd_sc_hd__nand3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand3.functional.v, line:33:1, endln:53:10 |vpiName:B |vpiDirection:1 |vpiLowConn: @@ -13177,7 +13177,7 @@ design: (work@sky130_fd_sc_hd__nand3) |vpiPort: \_port: (C), line:37:5, endln:37:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__nand3 (work@sky130_fd_sc_hd__nand3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand3.functional.v, line:33:1, endln:53:10 + \_module_inst: work@sky130_fd_sc_hd__nand3 (work@sky130_fd_sc_hd__nand3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand3.functional.v, line:33:1, endln:53:10 |vpiName:C |vpiDirection:1 |vpiLowConn: @@ -13191,7 +13191,7 @@ design: (work@sky130_fd_sc_hd__nand3) |vpiPrimitive: \_gate: work@nand (work@sky130_fd_sc_hd__nand3.nand0), line:50:10, endln:50:46 |vpiParent: - \_module: work@sky130_fd_sc_hd__nand3 (work@sky130_fd_sc_hd__nand3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand3.functional.v, line:33:1, endln:53:10 + \_module_inst: work@sky130_fd_sc_hd__nand3 (work@sky130_fd_sc_hd__nand3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand3.functional.v, line:33:1, endln:53:10 |vpiDefName:work@nand |vpiName:nand0 |vpiFullName:work@sky130_fd_sc_hd__nand3.nand0 @@ -13254,7 +13254,7 @@ design: (work@sky130_fd_sc_hd__nand3) |vpiPrimitive: \_gate: work@buf (work@sky130_fd_sc_hd__nand3.buf0), line:51:10, endln:51:46 |vpiParent: - \_module: work@sky130_fd_sc_hd__nand3 (work@sky130_fd_sc_hd__nand3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand3.functional.v, line:33:1, endln:53:10 + \_module_inst: work@sky130_fd_sc_hd__nand3 (work@sky130_fd_sc_hd__nand3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand3.functional.v, line:33:1, endln:53:10 |vpiDefName:work@buf |vpiName:buf0 |vpiFullName:work@sky130_fd_sc_hd__nand3.buf0 @@ -13425,7 +13425,7 @@ design: (work@sky130_fd_sc_hd__dfbbn) |vpiSize:4 |STRING:0 0 ? * : ? : - |uhdmallModules: -\_module: work@sky130_fd_sc_hd__dfbbn (work@sky130_fd_sc_hd__dfbbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfbbn.functional.v, line:37:1, endln:68:10 +\_module_inst: work@sky130_fd_sc_hd__dfbbn (work@sky130_fd_sc_hd__dfbbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfbbn.functional.v, line:37:1, endln:68:10 |vpiParent: \_design: (work@sky130_fd_sc_hd__dfbbn) |vpiFullName:work@sky130_fd_sc_hd__dfbbn @@ -13433,71 +13433,71 @@ design: (work@sky130_fd_sc_hd__dfbbn) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__dfbbn.RESET), line:55:10, endln:55:15 |vpiParent: - \_module: work@sky130_fd_sc_hd__dfbbn (work@sky130_fd_sc_hd__dfbbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfbbn.functional.v, line:37:1, endln:68:10 + \_module_inst: work@sky130_fd_sc_hd__dfbbn (work@sky130_fd_sc_hd__dfbbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfbbn.functional.v, line:37:1, endln:68:10 |vpiName:RESET |vpiFullName:work@sky130_fd_sc_hd__dfbbn.RESET |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__dfbbn.SET), line:56:10, endln:56:13 |vpiParent: - \_module: work@sky130_fd_sc_hd__dfbbn (work@sky130_fd_sc_hd__dfbbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfbbn.functional.v, line:37:1, endln:68:10 + \_module_inst: work@sky130_fd_sc_hd__dfbbn (work@sky130_fd_sc_hd__dfbbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfbbn.functional.v, line:37:1, endln:68:10 |vpiName:SET |vpiFullName:work@sky130_fd_sc_hd__dfbbn.SET |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__dfbbn.CLK), line:57:10, endln:57:13 |vpiParent: - \_module: work@sky130_fd_sc_hd__dfbbn (work@sky130_fd_sc_hd__dfbbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfbbn.functional.v, line:37:1, endln:68:10 + \_module_inst: work@sky130_fd_sc_hd__dfbbn (work@sky130_fd_sc_hd__dfbbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfbbn.functional.v, line:37:1, endln:68:10 |vpiName:CLK |vpiFullName:work@sky130_fd_sc_hd__dfbbn.CLK |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__dfbbn.buf_Q), line:58:10, endln:58:15 |vpiParent: - \_module: work@sky130_fd_sc_hd__dfbbn (work@sky130_fd_sc_hd__dfbbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfbbn.functional.v, line:37:1, endln:68:10 + \_module_inst: work@sky130_fd_sc_hd__dfbbn (work@sky130_fd_sc_hd__dfbbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfbbn.functional.v, line:37:1, endln:68:10 |vpiName:buf_Q |vpiFullName:work@sky130_fd_sc_hd__dfbbn.buf_Q |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__dfbbn.Q), line:38:5, endln:38:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__dfbbn (work@sky130_fd_sc_hd__dfbbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfbbn.functional.v, line:37:1, endln:68:10 + \_module_inst: work@sky130_fd_sc_hd__dfbbn (work@sky130_fd_sc_hd__dfbbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfbbn.functional.v, line:37:1, endln:68:10 |vpiName:Q |vpiFullName:work@sky130_fd_sc_hd__dfbbn.Q |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__dfbbn.Q_N), line:39:5, endln:39:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__dfbbn (work@sky130_fd_sc_hd__dfbbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfbbn.functional.v, line:37:1, endln:68:10 + \_module_inst: work@sky130_fd_sc_hd__dfbbn (work@sky130_fd_sc_hd__dfbbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfbbn.functional.v, line:37:1, endln:68:10 |vpiName:Q_N |vpiFullName:work@sky130_fd_sc_hd__dfbbn.Q_N |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__dfbbn.D), line:40:5, endln:40:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__dfbbn (work@sky130_fd_sc_hd__dfbbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfbbn.functional.v, line:37:1, endln:68:10 + \_module_inst: work@sky130_fd_sc_hd__dfbbn (work@sky130_fd_sc_hd__dfbbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfbbn.functional.v, line:37:1, endln:68:10 |vpiName:D |vpiFullName:work@sky130_fd_sc_hd__dfbbn.D |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__dfbbn.CLK_N), line:41:5, endln:41:10 |vpiParent: - \_module: work@sky130_fd_sc_hd__dfbbn (work@sky130_fd_sc_hd__dfbbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfbbn.functional.v, line:37:1, endln:68:10 + \_module_inst: work@sky130_fd_sc_hd__dfbbn (work@sky130_fd_sc_hd__dfbbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfbbn.functional.v, line:37:1, endln:68:10 |vpiName:CLK_N |vpiFullName:work@sky130_fd_sc_hd__dfbbn.CLK_N |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__dfbbn.SET_B), line:42:5, endln:42:10 |vpiParent: - \_module: work@sky130_fd_sc_hd__dfbbn (work@sky130_fd_sc_hd__dfbbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfbbn.functional.v, line:37:1, endln:68:10 + \_module_inst: work@sky130_fd_sc_hd__dfbbn (work@sky130_fd_sc_hd__dfbbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfbbn.functional.v, line:37:1, endln:68:10 |vpiName:SET_B |vpiFullName:work@sky130_fd_sc_hd__dfbbn.SET_B |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__dfbbn.RESET_B), line:43:5, endln:43:12 |vpiParent: - \_module: work@sky130_fd_sc_hd__dfbbn (work@sky130_fd_sc_hd__dfbbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfbbn.functional.v, line:37:1, endln:68:10 + \_module_inst: work@sky130_fd_sc_hd__dfbbn (work@sky130_fd_sc_hd__dfbbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfbbn.functional.v, line:37:1, endln:68:10 |vpiName:RESET_B |vpiFullName:work@sky130_fd_sc_hd__dfbbn.RESET_B |vpiPort: \_port: (Q), line:38:5, endln:38:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__dfbbn (work@sky130_fd_sc_hd__dfbbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfbbn.functional.v, line:37:1, endln:68:10 + \_module_inst: work@sky130_fd_sc_hd__dfbbn (work@sky130_fd_sc_hd__dfbbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfbbn.functional.v, line:37:1, endln:68:10 |vpiName:Q |vpiDirection:2 |vpiLowConn: @@ -13509,7 +13509,7 @@ design: (work@sky130_fd_sc_hd__dfbbn) |vpiPort: \_port: (Q_N), line:39:5, endln:39:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__dfbbn (work@sky130_fd_sc_hd__dfbbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfbbn.functional.v, line:37:1, endln:68:10 + \_module_inst: work@sky130_fd_sc_hd__dfbbn (work@sky130_fd_sc_hd__dfbbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfbbn.functional.v, line:37:1, endln:68:10 |vpiName:Q_N |vpiDirection:2 |vpiLowConn: @@ -13521,7 +13521,7 @@ design: (work@sky130_fd_sc_hd__dfbbn) |vpiPort: \_port: (D), line:40:5, endln:40:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__dfbbn (work@sky130_fd_sc_hd__dfbbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfbbn.functional.v, line:37:1, endln:68:10 + \_module_inst: work@sky130_fd_sc_hd__dfbbn (work@sky130_fd_sc_hd__dfbbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfbbn.functional.v, line:37:1, endln:68:10 |vpiName:D |vpiDirection:1 |vpiLowConn: @@ -13533,7 +13533,7 @@ design: (work@sky130_fd_sc_hd__dfbbn) |vpiPort: \_port: (CLK_N), line:41:5, endln:41:10 |vpiParent: - \_module: work@sky130_fd_sc_hd__dfbbn (work@sky130_fd_sc_hd__dfbbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfbbn.functional.v, line:37:1, endln:68:10 + \_module_inst: work@sky130_fd_sc_hd__dfbbn (work@sky130_fd_sc_hd__dfbbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfbbn.functional.v, line:37:1, endln:68:10 |vpiName:CLK_N |vpiDirection:1 |vpiLowConn: @@ -13545,7 +13545,7 @@ design: (work@sky130_fd_sc_hd__dfbbn) |vpiPort: \_port: (SET_B), line:42:5, endln:42:10 |vpiParent: - \_module: work@sky130_fd_sc_hd__dfbbn (work@sky130_fd_sc_hd__dfbbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfbbn.functional.v, line:37:1, endln:68:10 + \_module_inst: work@sky130_fd_sc_hd__dfbbn (work@sky130_fd_sc_hd__dfbbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfbbn.functional.v, line:37:1, endln:68:10 |vpiName:SET_B |vpiDirection:1 |vpiLowConn: @@ -13557,7 +13557,7 @@ design: (work@sky130_fd_sc_hd__dfbbn) |vpiPort: \_port: (RESET_B), line:43:5, endln:43:12 |vpiParent: - \_module: work@sky130_fd_sc_hd__dfbbn (work@sky130_fd_sc_hd__dfbbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfbbn.functional.v, line:37:1, endln:68:10 + \_module_inst: work@sky130_fd_sc_hd__dfbbn (work@sky130_fd_sc_hd__dfbbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfbbn.functional.v, line:37:1, endln:68:10 |vpiName:RESET_B |vpiDirection:1 |vpiLowConn: @@ -13567,14 +13567,14 @@ design: (work@sky130_fd_sc_hd__dfbbn) |vpiTypedef: \_logic_typespec: , line:52:12, endln:52:12 |uhdmtopModules: -\_module: work@sky130_fd_sc_hd__dfbbn (work@sky130_fd_sc_hd__dfbbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfbbn.functional.v, line:37:1, endln:68:10 +\_module_inst: work@sky130_fd_sc_hd__dfbbn (work@sky130_fd_sc_hd__dfbbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfbbn.functional.v, line:37:1, endln:68:10 |vpiName:work@sky130_fd_sc_hd__dfbbn |vpiDefName:work@sky130_fd_sc_hd__dfbbn |vpiTop:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__dfbbn.RESET), line:55:10, endln:55:15 |vpiParent: - \_module: work@sky130_fd_sc_hd__dfbbn (work@sky130_fd_sc_hd__dfbbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfbbn.functional.v, line:37:1, endln:68:10 + \_module_inst: work@sky130_fd_sc_hd__dfbbn (work@sky130_fd_sc_hd__dfbbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfbbn.functional.v, line:37:1, endln:68:10 |vpiTypespec: \_logic_typespec: , line:55:5, endln:55:9 |vpiName:RESET @@ -13583,7 +13583,7 @@ design: (work@sky130_fd_sc_hd__dfbbn) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__dfbbn.SET), line:56:10, endln:56:13 |vpiParent: - \_module: work@sky130_fd_sc_hd__dfbbn (work@sky130_fd_sc_hd__dfbbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfbbn.functional.v, line:37:1, endln:68:10 + \_module_inst: work@sky130_fd_sc_hd__dfbbn (work@sky130_fd_sc_hd__dfbbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfbbn.functional.v, line:37:1, endln:68:10 |vpiTypespec: \_logic_typespec: , line:56:5, endln:56:9 |vpiName:SET @@ -13592,7 +13592,7 @@ design: (work@sky130_fd_sc_hd__dfbbn) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__dfbbn.CLK), line:57:10, endln:57:13 |vpiParent: - \_module: work@sky130_fd_sc_hd__dfbbn (work@sky130_fd_sc_hd__dfbbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfbbn.functional.v, line:37:1, endln:68:10 + \_module_inst: work@sky130_fd_sc_hd__dfbbn (work@sky130_fd_sc_hd__dfbbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfbbn.functional.v, line:37:1, endln:68:10 |vpiTypespec: \_logic_typespec: , line:57:5, endln:57:9 |vpiName:CLK @@ -13601,7 +13601,7 @@ design: (work@sky130_fd_sc_hd__dfbbn) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__dfbbn.buf_Q), line:58:10, endln:58:15 |vpiParent: - \_module: work@sky130_fd_sc_hd__dfbbn (work@sky130_fd_sc_hd__dfbbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfbbn.functional.v, line:37:1, endln:68:10 + \_module_inst: work@sky130_fd_sc_hd__dfbbn (work@sky130_fd_sc_hd__dfbbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfbbn.functional.v, line:37:1, endln:68:10 |vpiTypespec: \_logic_typespec: , line:58:5, endln:58:9 |vpiName:buf_Q @@ -13610,7 +13610,7 @@ design: (work@sky130_fd_sc_hd__dfbbn) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__dfbbn.Q), line:38:5, endln:38:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__dfbbn (work@sky130_fd_sc_hd__dfbbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfbbn.functional.v, line:37:1, endln:68:10 + \_module_inst: work@sky130_fd_sc_hd__dfbbn (work@sky130_fd_sc_hd__dfbbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfbbn.functional.v, line:37:1, endln:68:10 |vpiTypespec: \_logic_typespec: , line:47:12, endln:47:12 |vpiName:Q @@ -13618,7 +13618,7 @@ design: (work@sky130_fd_sc_hd__dfbbn) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__dfbbn.Q_N), line:39:5, endln:39:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__dfbbn (work@sky130_fd_sc_hd__dfbbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfbbn.functional.v, line:37:1, endln:68:10 + \_module_inst: work@sky130_fd_sc_hd__dfbbn (work@sky130_fd_sc_hd__dfbbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfbbn.functional.v, line:37:1, endln:68:10 |vpiTypespec: \_logic_typespec: , line:48:12, endln:48:12 |vpiName:Q_N @@ -13626,7 +13626,7 @@ design: (work@sky130_fd_sc_hd__dfbbn) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__dfbbn.D), line:40:5, endln:40:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__dfbbn (work@sky130_fd_sc_hd__dfbbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfbbn.functional.v, line:37:1, endln:68:10 + \_module_inst: work@sky130_fd_sc_hd__dfbbn (work@sky130_fd_sc_hd__dfbbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfbbn.functional.v, line:37:1, endln:68:10 |vpiTypespec: \_logic_typespec: , line:49:12, endln:49:12 |vpiName:D @@ -13634,7 +13634,7 @@ design: (work@sky130_fd_sc_hd__dfbbn) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__dfbbn.CLK_N), line:41:5, endln:41:10 |vpiParent: - \_module: work@sky130_fd_sc_hd__dfbbn (work@sky130_fd_sc_hd__dfbbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfbbn.functional.v, line:37:1, endln:68:10 + \_module_inst: work@sky130_fd_sc_hd__dfbbn (work@sky130_fd_sc_hd__dfbbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfbbn.functional.v, line:37:1, endln:68:10 |vpiTypespec: \_logic_typespec: , line:50:12, endln:50:12 |vpiName:CLK_N @@ -13642,7 +13642,7 @@ design: (work@sky130_fd_sc_hd__dfbbn) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__dfbbn.SET_B), line:42:5, endln:42:10 |vpiParent: - \_module: work@sky130_fd_sc_hd__dfbbn (work@sky130_fd_sc_hd__dfbbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfbbn.functional.v, line:37:1, endln:68:10 + \_module_inst: work@sky130_fd_sc_hd__dfbbn (work@sky130_fd_sc_hd__dfbbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfbbn.functional.v, line:37:1, endln:68:10 |vpiTypespec: \_logic_typespec: , line:51:12, endln:51:12 |vpiName:SET_B @@ -13650,7 +13650,7 @@ design: (work@sky130_fd_sc_hd__dfbbn) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__dfbbn.RESET_B), line:43:5, endln:43:12 |vpiParent: - \_module: work@sky130_fd_sc_hd__dfbbn (work@sky130_fd_sc_hd__dfbbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfbbn.functional.v, line:37:1, endln:68:10 + \_module_inst: work@sky130_fd_sc_hd__dfbbn (work@sky130_fd_sc_hd__dfbbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfbbn.functional.v, line:37:1, endln:68:10 |vpiTypespec: \_logic_typespec: , line:52:12, endln:52:12 |vpiName:RESET_B @@ -13659,7 +13659,7 @@ design: (work@sky130_fd_sc_hd__dfbbn) |vpiPort: \_port: (Q), line:38:5, endln:38:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__dfbbn (work@sky130_fd_sc_hd__dfbbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfbbn.functional.v, line:37:1, endln:68:10 + \_module_inst: work@sky130_fd_sc_hd__dfbbn (work@sky130_fd_sc_hd__dfbbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfbbn.functional.v, line:37:1, endln:68:10 |vpiName:Q |vpiDirection:2 |vpiLowConn: @@ -13673,7 +13673,7 @@ design: (work@sky130_fd_sc_hd__dfbbn) |vpiPort: \_port: (Q_N), line:39:5, endln:39:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__dfbbn (work@sky130_fd_sc_hd__dfbbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfbbn.functional.v, line:37:1, endln:68:10 + \_module_inst: work@sky130_fd_sc_hd__dfbbn (work@sky130_fd_sc_hd__dfbbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfbbn.functional.v, line:37:1, endln:68:10 |vpiName:Q_N |vpiDirection:2 |vpiLowConn: @@ -13687,7 +13687,7 @@ design: (work@sky130_fd_sc_hd__dfbbn) |vpiPort: \_port: (D), line:40:5, endln:40:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__dfbbn (work@sky130_fd_sc_hd__dfbbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfbbn.functional.v, line:37:1, endln:68:10 + \_module_inst: work@sky130_fd_sc_hd__dfbbn (work@sky130_fd_sc_hd__dfbbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfbbn.functional.v, line:37:1, endln:68:10 |vpiName:D |vpiDirection:1 |vpiLowConn: @@ -13701,7 +13701,7 @@ design: (work@sky130_fd_sc_hd__dfbbn) |vpiPort: \_port: (CLK_N), line:41:5, endln:41:10 |vpiParent: - \_module: work@sky130_fd_sc_hd__dfbbn (work@sky130_fd_sc_hd__dfbbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfbbn.functional.v, line:37:1, endln:68:10 + \_module_inst: work@sky130_fd_sc_hd__dfbbn (work@sky130_fd_sc_hd__dfbbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfbbn.functional.v, line:37:1, endln:68:10 |vpiName:CLK_N |vpiDirection:1 |vpiLowConn: @@ -13715,7 +13715,7 @@ design: (work@sky130_fd_sc_hd__dfbbn) |vpiPort: \_port: (SET_B), line:42:5, endln:42:10 |vpiParent: - \_module: work@sky130_fd_sc_hd__dfbbn (work@sky130_fd_sc_hd__dfbbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfbbn.functional.v, line:37:1, endln:68:10 + \_module_inst: work@sky130_fd_sc_hd__dfbbn (work@sky130_fd_sc_hd__dfbbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfbbn.functional.v, line:37:1, endln:68:10 |vpiName:SET_B |vpiDirection:1 |vpiLowConn: @@ -13729,7 +13729,7 @@ design: (work@sky130_fd_sc_hd__dfbbn) |vpiPort: \_port: (RESET_B), line:43:5, endln:43:12 |vpiParent: - \_module: work@sky130_fd_sc_hd__dfbbn (work@sky130_fd_sc_hd__dfbbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfbbn.functional.v, line:37:1, endln:68:10 + \_module_inst: work@sky130_fd_sc_hd__dfbbn (work@sky130_fd_sc_hd__dfbbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfbbn.functional.v, line:37:1, endln:68:10 |vpiName:RESET_B |vpiDirection:1 |vpiLowConn: @@ -13743,7 +13743,7 @@ design: (work@sky130_fd_sc_hd__dfbbn) |vpiPrimitive: \_gate: work@not (work@sky130_fd_sc_hd__dfbbn.not0), line:61:46, endln:61:79 |vpiParent: - \_module: work@sky130_fd_sc_hd__dfbbn (work@sky130_fd_sc_hd__dfbbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfbbn.functional.v, line:37:1, endln:68:10 + \_module_inst: work@sky130_fd_sc_hd__dfbbn (work@sky130_fd_sc_hd__dfbbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfbbn.functional.v, line:37:1, endln:68:10 |vpiDefName:work@not |vpiName:not0 |vpiFullName:work@sky130_fd_sc_hd__dfbbn.not0 @@ -13778,7 +13778,7 @@ design: (work@sky130_fd_sc_hd__dfbbn) |vpiPrimitive: \_gate: work@not (work@sky130_fd_sc_hd__dfbbn.not1), line:62:46, endln:62:79 |vpiParent: - \_module: work@sky130_fd_sc_hd__dfbbn (work@sky130_fd_sc_hd__dfbbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfbbn.functional.v, line:37:1, endln:68:10 + \_module_inst: work@sky130_fd_sc_hd__dfbbn (work@sky130_fd_sc_hd__dfbbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfbbn.functional.v, line:37:1, endln:68:10 |vpiDefName:work@not |vpiName:not1 |vpiFullName:work@sky130_fd_sc_hd__dfbbn.not1 @@ -13813,7 +13813,7 @@ design: (work@sky130_fd_sc_hd__dfbbn) |vpiPrimitive: \_gate: work@not (work@sky130_fd_sc_hd__dfbbn.not2), line:63:46, endln:63:79 |vpiParent: - \_module: work@sky130_fd_sc_hd__dfbbn (work@sky130_fd_sc_hd__dfbbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfbbn.functional.v, line:37:1, endln:68:10 + \_module_inst: work@sky130_fd_sc_hd__dfbbn (work@sky130_fd_sc_hd__dfbbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfbbn.functional.v, line:37:1, endln:68:10 |vpiDefName:work@not |vpiName:not2 |vpiFullName:work@sky130_fd_sc_hd__dfbbn.not2 @@ -13848,7 +13848,7 @@ design: (work@sky130_fd_sc_hd__dfbbn) |vpiPrimitive: \_udp: work@sky130_fd_sc_hd__udp_dff$NSR (work@sky130_fd_sc_hd__dfbbn.dff0), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfbbn.functional.v, line:64:5, endln:64:69 |vpiParent: - \_module: work@sky130_fd_sc_hd__dfbbn (work@sky130_fd_sc_hd__dfbbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfbbn.functional.v, line:37:1, endln:68:10 + \_module_inst: work@sky130_fd_sc_hd__dfbbn (work@sky130_fd_sc_hd__dfbbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfbbn.functional.v, line:37:1, endln:68:10 |vpiDefName:work@sky130_fd_sc_hd__udp_dff$NSR |vpiName:dff0 |vpiFullName:work@sky130_fd_sc_hd__dfbbn.dff0 @@ -13857,7 +13857,7 @@ design: (work@sky130_fd_sc_hd__dfbbn) |vpiPrimitive: \_gate: work@buf (work@sky130_fd_sc_hd__dfbbn.buf0), line:65:46, endln:65:79 |vpiParent: - \_module: work@sky130_fd_sc_hd__dfbbn (work@sky130_fd_sc_hd__dfbbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfbbn.functional.v, line:37:1, endln:68:10 + \_module_inst: work@sky130_fd_sc_hd__dfbbn (work@sky130_fd_sc_hd__dfbbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfbbn.functional.v, line:37:1, endln:68:10 |vpiDefName:work@buf |vpiName:buf0 |vpiFullName:work@sky130_fd_sc_hd__dfbbn.buf0 @@ -13892,7 +13892,7 @@ design: (work@sky130_fd_sc_hd__dfbbn) |vpiPrimitive: \_gate: work@not (work@sky130_fd_sc_hd__dfbbn.not3), line:66:46, endln:66:79 |vpiParent: - \_module: work@sky130_fd_sc_hd__dfbbn (work@sky130_fd_sc_hd__dfbbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfbbn.functional.v, line:37:1, endln:68:10 + \_module_inst: work@sky130_fd_sc_hd__dfbbn (work@sky130_fd_sc_hd__dfbbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfbbn.functional.v, line:37:1, endln:68:10 |vpiDefName:work@not |vpiName:not3 |vpiFullName:work@sky130_fd_sc_hd__dfbbn.not3 @@ -14125,7 +14125,7 @@ design: (work@sky130_fd_sc_hd__sedfxbp) |vpiSize:3 |STRING:? 1 1 : 1 |uhdmallModules: -\_module: work@sky130_fd_sc_hd__sedfxbp (work@sky130_fd_sc_hd__sedfxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sedfxbp.functional.v, line:38:1, endln:69:10 +\_module_inst: work@sky130_fd_sc_hd__sedfxbp (work@sky130_fd_sc_hd__sedfxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sedfxbp.functional.v, line:38:1, endln:69:10 |vpiParent: \_design: (work@sky130_fd_sc_hd__sedfxbp) |vpiFullName:work@sky130_fd_sc_hd__sedfxbp @@ -14133,70 +14133,70 @@ design: (work@sky130_fd_sc_hd__sedfxbp) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__sedfxbp.buf_Q), line:58:10, endln:58:15 |vpiParent: - \_module: work@sky130_fd_sc_hd__sedfxbp (work@sky130_fd_sc_hd__sedfxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sedfxbp.functional.v, line:38:1, endln:69:10 + \_module_inst: work@sky130_fd_sc_hd__sedfxbp (work@sky130_fd_sc_hd__sedfxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sedfxbp.functional.v, line:38:1, endln:69:10 |vpiName:buf_Q |vpiFullName:work@sky130_fd_sc_hd__sedfxbp.buf_Q |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__sedfxbp.mux_out), line:59:10, endln:59:17 |vpiParent: - \_module: work@sky130_fd_sc_hd__sedfxbp (work@sky130_fd_sc_hd__sedfxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sedfxbp.functional.v, line:38:1, endln:69:10 + \_module_inst: work@sky130_fd_sc_hd__sedfxbp (work@sky130_fd_sc_hd__sedfxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sedfxbp.functional.v, line:38:1, endln:69:10 |vpiName:mux_out |vpiFullName:work@sky130_fd_sc_hd__sedfxbp.mux_out |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__sedfxbp.de_d), line:60:10, endln:60:14 |vpiParent: - \_module: work@sky130_fd_sc_hd__sedfxbp (work@sky130_fd_sc_hd__sedfxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sedfxbp.functional.v, line:38:1, endln:69:10 + \_module_inst: work@sky130_fd_sc_hd__sedfxbp (work@sky130_fd_sc_hd__sedfxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sedfxbp.functional.v, line:38:1, endln:69:10 |vpiName:de_d |vpiFullName:work@sky130_fd_sc_hd__sedfxbp.de_d |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__sedfxbp.Q), line:39:5, endln:39:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__sedfxbp (work@sky130_fd_sc_hd__sedfxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sedfxbp.functional.v, line:38:1, endln:69:10 + \_module_inst: work@sky130_fd_sc_hd__sedfxbp (work@sky130_fd_sc_hd__sedfxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sedfxbp.functional.v, line:38:1, endln:69:10 |vpiName:Q |vpiFullName:work@sky130_fd_sc_hd__sedfxbp.Q |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__sedfxbp.Q_N), line:40:5, endln:40:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__sedfxbp (work@sky130_fd_sc_hd__sedfxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sedfxbp.functional.v, line:38:1, endln:69:10 + \_module_inst: work@sky130_fd_sc_hd__sedfxbp (work@sky130_fd_sc_hd__sedfxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sedfxbp.functional.v, line:38:1, endln:69:10 |vpiName:Q_N |vpiFullName:work@sky130_fd_sc_hd__sedfxbp.Q_N |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__sedfxbp.CLK), line:41:5, endln:41:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__sedfxbp (work@sky130_fd_sc_hd__sedfxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sedfxbp.functional.v, line:38:1, endln:69:10 + \_module_inst: work@sky130_fd_sc_hd__sedfxbp (work@sky130_fd_sc_hd__sedfxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sedfxbp.functional.v, line:38:1, endln:69:10 |vpiName:CLK |vpiFullName:work@sky130_fd_sc_hd__sedfxbp.CLK |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__sedfxbp.D), line:42:5, endln:42:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__sedfxbp (work@sky130_fd_sc_hd__sedfxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sedfxbp.functional.v, line:38:1, endln:69:10 + \_module_inst: work@sky130_fd_sc_hd__sedfxbp (work@sky130_fd_sc_hd__sedfxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sedfxbp.functional.v, line:38:1, endln:69:10 |vpiName:D |vpiFullName:work@sky130_fd_sc_hd__sedfxbp.D |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__sedfxbp.DE), line:43:5, endln:43:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__sedfxbp (work@sky130_fd_sc_hd__sedfxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sedfxbp.functional.v, line:38:1, endln:69:10 + \_module_inst: work@sky130_fd_sc_hd__sedfxbp (work@sky130_fd_sc_hd__sedfxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sedfxbp.functional.v, line:38:1, endln:69:10 |vpiName:DE |vpiFullName:work@sky130_fd_sc_hd__sedfxbp.DE |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__sedfxbp.SCD), line:44:5, endln:44:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__sedfxbp (work@sky130_fd_sc_hd__sedfxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sedfxbp.functional.v, line:38:1, endln:69:10 + \_module_inst: work@sky130_fd_sc_hd__sedfxbp (work@sky130_fd_sc_hd__sedfxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sedfxbp.functional.v, line:38:1, endln:69:10 |vpiName:SCD |vpiFullName:work@sky130_fd_sc_hd__sedfxbp.SCD |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__sedfxbp.SCE), line:45:5, endln:45:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__sedfxbp (work@sky130_fd_sc_hd__sedfxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sedfxbp.functional.v, line:38:1, endln:69:10 + \_module_inst: work@sky130_fd_sc_hd__sedfxbp (work@sky130_fd_sc_hd__sedfxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sedfxbp.functional.v, line:38:1, endln:69:10 |vpiName:SCE |vpiFullName:work@sky130_fd_sc_hd__sedfxbp.SCE |vpiPort: \_port: (Q), line:39:5, endln:39:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__sedfxbp (work@sky130_fd_sc_hd__sedfxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sedfxbp.functional.v, line:38:1, endln:69:10 + \_module_inst: work@sky130_fd_sc_hd__sedfxbp (work@sky130_fd_sc_hd__sedfxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sedfxbp.functional.v, line:38:1, endln:69:10 |vpiName:Q |vpiDirection:2 |vpiLowConn: @@ -14208,7 +14208,7 @@ design: (work@sky130_fd_sc_hd__sedfxbp) |vpiPort: \_port: (Q_N), line:40:5, endln:40:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__sedfxbp (work@sky130_fd_sc_hd__sedfxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sedfxbp.functional.v, line:38:1, endln:69:10 + \_module_inst: work@sky130_fd_sc_hd__sedfxbp (work@sky130_fd_sc_hd__sedfxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sedfxbp.functional.v, line:38:1, endln:69:10 |vpiName:Q_N |vpiDirection:2 |vpiLowConn: @@ -14220,7 +14220,7 @@ design: (work@sky130_fd_sc_hd__sedfxbp) |vpiPort: \_port: (CLK), line:41:5, endln:41:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__sedfxbp (work@sky130_fd_sc_hd__sedfxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sedfxbp.functional.v, line:38:1, endln:69:10 + \_module_inst: work@sky130_fd_sc_hd__sedfxbp (work@sky130_fd_sc_hd__sedfxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sedfxbp.functional.v, line:38:1, endln:69:10 |vpiName:CLK |vpiDirection:1 |vpiLowConn: @@ -14232,7 +14232,7 @@ design: (work@sky130_fd_sc_hd__sedfxbp) |vpiPort: \_port: (D), line:42:5, endln:42:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__sedfxbp (work@sky130_fd_sc_hd__sedfxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sedfxbp.functional.v, line:38:1, endln:69:10 + \_module_inst: work@sky130_fd_sc_hd__sedfxbp (work@sky130_fd_sc_hd__sedfxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sedfxbp.functional.v, line:38:1, endln:69:10 |vpiName:D |vpiDirection:1 |vpiLowConn: @@ -14244,7 +14244,7 @@ design: (work@sky130_fd_sc_hd__sedfxbp) |vpiPort: \_port: (DE), line:43:5, endln:43:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__sedfxbp (work@sky130_fd_sc_hd__sedfxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sedfxbp.functional.v, line:38:1, endln:69:10 + \_module_inst: work@sky130_fd_sc_hd__sedfxbp (work@sky130_fd_sc_hd__sedfxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sedfxbp.functional.v, line:38:1, endln:69:10 |vpiName:DE |vpiDirection:1 |vpiLowConn: @@ -14256,7 +14256,7 @@ design: (work@sky130_fd_sc_hd__sedfxbp) |vpiPort: \_port: (SCD), line:44:5, endln:44:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__sedfxbp (work@sky130_fd_sc_hd__sedfxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sedfxbp.functional.v, line:38:1, endln:69:10 + \_module_inst: work@sky130_fd_sc_hd__sedfxbp (work@sky130_fd_sc_hd__sedfxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sedfxbp.functional.v, line:38:1, endln:69:10 |vpiName:SCD |vpiDirection:1 |vpiLowConn: @@ -14268,7 +14268,7 @@ design: (work@sky130_fd_sc_hd__sedfxbp) |vpiPort: \_port: (SCE), line:45:5, endln:45:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__sedfxbp (work@sky130_fd_sc_hd__sedfxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sedfxbp.functional.v, line:38:1, endln:69:10 + \_module_inst: work@sky130_fd_sc_hd__sedfxbp (work@sky130_fd_sc_hd__sedfxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sedfxbp.functional.v, line:38:1, endln:69:10 |vpiName:SCE |vpiDirection:1 |vpiLowConn: @@ -14278,14 +14278,14 @@ design: (work@sky130_fd_sc_hd__sedfxbp) |vpiTypedef: \_logic_typespec: , line:55:12, endln:55:12 |uhdmtopModules: -\_module: work@sky130_fd_sc_hd__sedfxbp (work@sky130_fd_sc_hd__sedfxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sedfxbp.functional.v, line:38:1, endln:69:10 +\_module_inst: work@sky130_fd_sc_hd__sedfxbp (work@sky130_fd_sc_hd__sedfxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sedfxbp.functional.v, line:38:1, endln:69:10 |vpiName:work@sky130_fd_sc_hd__sedfxbp |vpiDefName:work@sky130_fd_sc_hd__sedfxbp |vpiTop:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__sedfxbp.buf_Q), line:58:10, endln:58:15 |vpiParent: - \_module: work@sky130_fd_sc_hd__sedfxbp (work@sky130_fd_sc_hd__sedfxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sedfxbp.functional.v, line:38:1, endln:69:10 + \_module_inst: work@sky130_fd_sc_hd__sedfxbp (work@sky130_fd_sc_hd__sedfxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sedfxbp.functional.v, line:38:1, endln:69:10 |vpiTypespec: \_logic_typespec: , line:58:5, endln:58:9 |vpiName:buf_Q @@ -14294,7 +14294,7 @@ design: (work@sky130_fd_sc_hd__sedfxbp) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__sedfxbp.mux_out), line:59:10, endln:59:17 |vpiParent: - \_module: work@sky130_fd_sc_hd__sedfxbp (work@sky130_fd_sc_hd__sedfxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sedfxbp.functional.v, line:38:1, endln:69:10 + \_module_inst: work@sky130_fd_sc_hd__sedfxbp (work@sky130_fd_sc_hd__sedfxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sedfxbp.functional.v, line:38:1, endln:69:10 |vpiTypespec: \_logic_typespec: , line:59:5, endln:59:9 |vpiName:mux_out @@ -14303,7 +14303,7 @@ design: (work@sky130_fd_sc_hd__sedfxbp) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__sedfxbp.de_d), line:60:10, endln:60:14 |vpiParent: - \_module: work@sky130_fd_sc_hd__sedfxbp (work@sky130_fd_sc_hd__sedfxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sedfxbp.functional.v, line:38:1, endln:69:10 + \_module_inst: work@sky130_fd_sc_hd__sedfxbp (work@sky130_fd_sc_hd__sedfxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sedfxbp.functional.v, line:38:1, endln:69:10 |vpiTypespec: \_logic_typespec: , line:60:5, endln:60:9 |vpiName:de_d @@ -14312,7 +14312,7 @@ design: (work@sky130_fd_sc_hd__sedfxbp) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__sedfxbp.Q), line:39:5, endln:39:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__sedfxbp (work@sky130_fd_sc_hd__sedfxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sedfxbp.functional.v, line:38:1, endln:69:10 + \_module_inst: work@sky130_fd_sc_hd__sedfxbp (work@sky130_fd_sc_hd__sedfxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sedfxbp.functional.v, line:38:1, endln:69:10 |vpiTypespec: \_logic_typespec: , line:49:12, endln:49:12 |vpiName:Q @@ -14320,7 +14320,7 @@ design: (work@sky130_fd_sc_hd__sedfxbp) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__sedfxbp.Q_N), line:40:5, endln:40:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__sedfxbp (work@sky130_fd_sc_hd__sedfxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sedfxbp.functional.v, line:38:1, endln:69:10 + \_module_inst: work@sky130_fd_sc_hd__sedfxbp (work@sky130_fd_sc_hd__sedfxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sedfxbp.functional.v, line:38:1, endln:69:10 |vpiTypespec: \_logic_typespec: , line:50:12, endln:50:12 |vpiName:Q_N @@ -14328,7 +14328,7 @@ design: (work@sky130_fd_sc_hd__sedfxbp) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__sedfxbp.CLK), line:41:5, endln:41:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__sedfxbp (work@sky130_fd_sc_hd__sedfxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sedfxbp.functional.v, line:38:1, endln:69:10 + \_module_inst: work@sky130_fd_sc_hd__sedfxbp (work@sky130_fd_sc_hd__sedfxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sedfxbp.functional.v, line:38:1, endln:69:10 |vpiTypespec: \_logic_typespec: , line:51:12, endln:51:12 |vpiName:CLK @@ -14336,7 +14336,7 @@ design: (work@sky130_fd_sc_hd__sedfxbp) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__sedfxbp.D), line:42:5, endln:42:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__sedfxbp (work@sky130_fd_sc_hd__sedfxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sedfxbp.functional.v, line:38:1, endln:69:10 + \_module_inst: work@sky130_fd_sc_hd__sedfxbp (work@sky130_fd_sc_hd__sedfxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sedfxbp.functional.v, line:38:1, endln:69:10 |vpiTypespec: \_logic_typespec: , line:52:12, endln:52:12 |vpiName:D @@ -14344,7 +14344,7 @@ design: (work@sky130_fd_sc_hd__sedfxbp) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__sedfxbp.DE), line:43:5, endln:43:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__sedfxbp (work@sky130_fd_sc_hd__sedfxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sedfxbp.functional.v, line:38:1, endln:69:10 + \_module_inst: work@sky130_fd_sc_hd__sedfxbp (work@sky130_fd_sc_hd__sedfxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sedfxbp.functional.v, line:38:1, endln:69:10 |vpiTypespec: \_logic_typespec: , line:53:12, endln:53:12 |vpiName:DE @@ -14352,7 +14352,7 @@ design: (work@sky130_fd_sc_hd__sedfxbp) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__sedfxbp.SCD), line:44:5, endln:44:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__sedfxbp (work@sky130_fd_sc_hd__sedfxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sedfxbp.functional.v, line:38:1, endln:69:10 + \_module_inst: work@sky130_fd_sc_hd__sedfxbp (work@sky130_fd_sc_hd__sedfxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sedfxbp.functional.v, line:38:1, endln:69:10 |vpiTypespec: \_logic_typespec: , line:54:12, endln:54:12 |vpiName:SCD @@ -14360,7 +14360,7 @@ design: (work@sky130_fd_sc_hd__sedfxbp) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__sedfxbp.SCE), line:45:5, endln:45:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__sedfxbp (work@sky130_fd_sc_hd__sedfxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sedfxbp.functional.v, line:38:1, endln:69:10 + \_module_inst: work@sky130_fd_sc_hd__sedfxbp (work@sky130_fd_sc_hd__sedfxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sedfxbp.functional.v, line:38:1, endln:69:10 |vpiTypespec: \_logic_typespec: , line:55:12, endln:55:12 |vpiName:SCE @@ -14369,7 +14369,7 @@ design: (work@sky130_fd_sc_hd__sedfxbp) |vpiPort: \_port: (Q), line:39:5, endln:39:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__sedfxbp (work@sky130_fd_sc_hd__sedfxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sedfxbp.functional.v, line:38:1, endln:69:10 + \_module_inst: work@sky130_fd_sc_hd__sedfxbp (work@sky130_fd_sc_hd__sedfxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sedfxbp.functional.v, line:38:1, endln:69:10 |vpiName:Q |vpiDirection:2 |vpiLowConn: @@ -14383,7 +14383,7 @@ design: (work@sky130_fd_sc_hd__sedfxbp) |vpiPort: \_port: (Q_N), line:40:5, endln:40:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__sedfxbp (work@sky130_fd_sc_hd__sedfxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sedfxbp.functional.v, line:38:1, endln:69:10 + \_module_inst: work@sky130_fd_sc_hd__sedfxbp (work@sky130_fd_sc_hd__sedfxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sedfxbp.functional.v, line:38:1, endln:69:10 |vpiName:Q_N |vpiDirection:2 |vpiLowConn: @@ -14397,7 +14397,7 @@ design: (work@sky130_fd_sc_hd__sedfxbp) |vpiPort: \_port: (CLK), line:41:5, endln:41:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__sedfxbp (work@sky130_fd_sc_hd__sedfxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sedfxbp.functional.v, line:38:1, endln:69:10 + \_module_inst: work@sky130_fd_sc_hd__sedfxbp (work@sky130_fd_sc_hd__sedfxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sedfxbp.functional.v, line:38:1, endln:69:10 |vpiName:CLK |vpiDirection:1 |vpiLowConn: @@ -14411,7 +14411,7 @@ design: (work@sky130_fd_sc_hd__sedfxbp) |vpiPort: \_port: (D), line:42:5, endln:42:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__sedfxbp (work@sky130_fd_sc_hd__sedfxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sedfxbp.functional.v, line:38:1, endln:69:10 + \_module_inst: work@sky130_fd_sc_hd__sedfxbp (work@sky130_fd_sc_hd__sedfxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sedfxbp.functional.v, line:38:1, endln:69:10 |vpiName:D |vpiDirection:1 |vpiLowConn: @@ -14425,7 +14425,7 @@ design: (work@sky130_fd_sc_hd__sedfxbp) |vpiPort: \_port: (DE), line:43:5, endln:43:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__sedfxbp (work@sky130_fd_sc_hd__sedfxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sedfxbp.functional.v, line:38:1, endln:69:10 + \_module_inst: work@sky130_fd_sc_hd__sedfxbp (work@sky130_fd_sc_hd__sedfxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sedfxbp.functional.v, line:38:1, endln:69:10 |vpiName:DE |vpiDirection:1 |vpiLowConn: @@ -14439,7 +14439,7 @@ design: (work@sky130_fd_sc_hd__sedfxbp) |vpiPort: \_port: (SCD), line:44:5, endln:44:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__sedfxbp (work@sky130_fd_sc_hd__sedfxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sedfxbp.functional.v, line:38:1, endln:69:10 + \_module_inst: work@sky130_fd_sc_hd__sedfxbp (work@sky130_fd_sc_hd__sedfxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sedfxbp.functional.v, line:38:1, endln:69:10 |vpiName:SCD |vpiDirection:1 |vpiLowConn: @@ -14453,7 +14453,7 @@ design: (work@sky130_fd_sc_hd__sedfxbp) |vpiPort: \_port: (SCE), line:45:5, endln:45:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__sedfxbp (work@sky130_fd_sc_hd__sedfxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sedfxbp.functional.v, line:38:1, endln:69:10 + \_module_inst: work@sky130_fd_sc_hd__sedfxbp (work@sky130_fd_sc_hd__sedfxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sedfxbp.functional.v, line:38:1, endln:69:10 |vpiName:SCE |vpiDirection:1 |vpiLowConn: @@ -14467,7 +14467,7 @@ design: (work@sky130_fd_sc_hd__sedfxbp) |vpiPrimitive: \_udp: work@sky130_fd_sc_hd__udp_mux_2to1 (work@sky130_fd_sc_hd__sedfxbp.mux_2to10), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sedfxbp.functional.v, line:63:5, endln:63:84 |vpiParent: - \_module: work@sky130_fd_sc_hd__sedfxbp (work@sky130_fd_sc_hd__sedfxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sedfxbp.functional.v, line:38:1, endln:69:10 + \_module_inst: work@sky130_fd_sc_hd__sedfxbp (work@sky130_fd_sc_hd__sedfxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sedfxbp.functional.v, line:38:1, endln:69:10 |vpiDefName:work@sky130_fd_sc_hd__udp_mux_2to1 |vpiName:mux_2to10 |vpiFullName:work@sky130_fd_sc_hd__sedfxbp.mux_2to10 @@ -14476,7 +14476,7 @@ design: (work@sky130_fd_sc_hd__sedfxbp) |vpiPrimitive: \_udp: work@sky130_fd_sc_hd__udp_mux_2to1 (work@sky130_fd_sc_hd__sedfxbp.mux_2to11), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sedfxbp.functional.v, line:64:5, endln:64:84 |vpiParent: - \_module: work@sky130_fd_sc_hd__sedfxbp (work@sky130_fd_sc_hd__sedfxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sedfxbp.functional.v, line:38:1, endln:69:10 + \_module_inst: work@sky130_fd_sc_hd__sedfxbp (work@sky130_fd_sc_hd__sedfxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sedfxbp.functional.v, line:38:1, endln:69:10 |vpiDefName:work@sky130_fd_sc_hd__udp_mux_2to1 |vpiName:mux_2to11 |vpiFullName:work@sky130_fd_sc_hd__sedfxbp.mux_2to11 @@ -14485,7 +14485,7 @@ design: (work@sky130_fd_sc_hd__sedfxbp) |vpiPrimitive: \_udp: work@sky130_fd_sc_hd__udp_dff$P (work@sky130_fd_sc_hd__sedfxbp.dff0), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sedfxbp.functional.v, line:65:5, endln:65:73 |vpiParent: - \_module: work@sky130_fd_sc_hd__sedfxbp (work@sky130_fd_sc_hd__sedfxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sedfxbp.functional.v, line:38:1, endln:69:10 + \_module_inst: work@sky130_fd_sc_hd__sedfxbp (work@sky130_fd_sc_hd__sedfxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sedfxbp.functional.v, line:38:1, endln:69:10 |vpiDefName:work@sky130_fd_sc_hd__udp_dff$P |vpiName:dff0 |vpiFullName:work@sky130_fd_sc_hd__sedfxbp.dff0 @@ -14494,7 +14494,7 @@ design: (work@sky130_fd_sc_hd__sedfxbp) |vpiPrimitive: \_gate: work@buf (work@sky130_fd_sc_hd__sedfxbp.buf0), line:66:47, endln:66:83 |vpiParent: - \_module: work@sky130_fd_sc_hd__sedfxbp (work@sky130_fd_sc_hd__sedfxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sedfxbp.functional.v, line:38:1, endln:69:10 + \_module_inst: work@sky130_fd_sc_hd__sedfxbp (work@sky130_fd_sc_hd__sedfxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sedfxbp.functional.v, line:38:1, endln:69:10 |vpiDefName:work@buf |vpiName:buf0 |vpiFullName:work@sky130_fd_sc_hd__sedfxbp.buf0 @@ -14529,7 +14529,7 @@ design: (work@sky130_fd_sc_hd__sedfxbp) |vpiPrimitive: \_gate: work@not (work@sky130_fd_sc_hd__sedfxbp.not0), line:67:47, endln:67:83 |vpiParent: - \_module: work@sky130_fd_sc_hd__sedfxbp (work@sky130_fd_sc_hd__sedfxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sedfxbp.functional.v, line:38:1, endln:69:10 + \_module_inst: work@sky130_fd_sc_hd__sedfxbp (work@sky130_fd_sc_hd__sedfxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sedfxbp.functional.v, line:38:1, endln:69:10 |vpiDefName:work@not |vpiName:not0 |vpiFullName:work@sky130_fd_sc_hd__sedfxbp.not0 @@ -14572,7 +14572,7 @@ Processing: -cd cells/cells -DUNIT_DELAY -writepp -parse -nocache -nobuiltin -no design: (work@sky130_fd_sc_hd__diode) |vpiName:work@sky130_fd_sc_hd__diode |uhdmallModules: -\_module: work@sky130_fd_sc_hd__diode (work@sky130_fd_sc_hd__diode), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__diode.functional.v, line:33:1, endln:40:10 +\_module_inst: work@sky130_fd_sc_hd__diode (work@sky130_fd_sc_hd__diode), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__diode.functional.v, line:33:1, endln:40:10 |vpiParent: \_design: (work@sky130_fd_sc_hd__diode) |vpiFullName:work@sky130_fd_sc_hd__diode @@ -14580,13 +14580,13 @@ design: (work@sky130_fd_sc_hd__diode) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__diode.DIODE), line:34:5, endln:34:10 |vpiParent: - \_module: work@sky130_fd_sc_hd__diode (work@sky130_fd_sc_hd__diode), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__diode.functional.v, line:33:1, endln:40:10 + \_module_inst: work@sky130_fd_sc_hd__diode (work@sky130_fd_sc_hd__diode), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__diode.functional.v, line:33:1, endln:40:10 |vpiName:DIODE |vpiFullName:work@sky130_fd_sc_hd__diode.DIODE |vpiPort: \_port: (DIODE), line:34:5, endln:34:10 |vpiParent: - \_module: work@sky130_fd_sc_hd__diode (work@sky130_fd_sc_hd__diode), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__diode.functional.v, line:33:1, endln:40:10 + \_module_inst: work@sky130_fd_sc_hd__diode (work@sky130_fd_sc_hd__diode), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__diode.functional.v, line:33:1, endln:40:10 |vpiName:DIODE |vpiDirection:1 |vpiLowConn: @@ -14596,14 +14596,14 @@ design: (work@sky130_fd_sc_hd__diode) |vpiTypedef: \_logic_typespec: , line:38:11, endln:38:11 |uhdmtopModules: -\_module: work@sky130_fd_sc_hd__diode (work@sky130_fd_sc_hd__diode), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__diode.functional.v, line:33:1, endln:40:10 +\_module_inst: work@sky130_fd_sc_hd__diode (work@sky130_fd_sc_hd__diode), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__diode.functional.v, line:33:1, endln:40:10 |vpiName:work@sky130_fd_sc_hd__diode |vpiDefName:work@sky130_fd_sc_hd__diode |vpiTop:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__diode.DIODE), line:34:5, endln:34:10 |vpiParent: - \_module: work@sky130_fd_sc_hd__diode (work@sky130_fd_sc_hd__diode), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__diode.functional.v, line:33:1, endln:40:10 + \_module_inst: work@sky130_fd_sc_hd__diode (work@sky130_fd_sc_hd__diode), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__diode.functional.v, line:33:1, endln:40:10 |vpiTypespec: \_logic_typespec: , line:38:11, endln:38:11 |vpiName:DIODE @@ -14612,7 +14612,7 @@ design: (work@sky130_fd_sc_hd__diode) |vpiPort: \_port: (DIODE), line:34:5, endln:34:10 |vpiParent: - \_module: work@sky130_fd_sc_hd__diode (work@sky130_fd_sc_hd__diode), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__diode.functional.v, line:33:1, endln:40:10 + \_module_inst: work@sky130_fd_sc_hd__diode (work@sky130_fd_sc_hd__diode), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__diode.functional.v, line:33:1, endln:40:10 |vpiName:DIODE |vpiDirection:1 |vpiLowConn: @@ -14824,7 +14824,7 @@ design: (work@sky130_fd_sc_hd__sdfxtp) |vpiSize:3 |STRING:? 1 1 : 1 |uhdmallModules: -\_module: work@sky130_fd_sc_hd__sdfxtp (work@sky130_fd_sc_hd__sdfxtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfxtp.functional.v, line:37:1, endln:61:10 +\_module_inst: work@sky130_fd_sc_hd__sdfxtp (work@sky130_fd_sc_hd__sdfxtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfxtp.functional.v, line:37:1, endln:61:10 |vpiParent: \_design: (work@sky130_fd_sc_hd__sdfxtp) |vpiFullName:work@sky130_fd_sc_hd__sdfxtp @@ -14832,51 +14832,51 @@ design: (work@sky130_fd_sc_hd__sdfxtp) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__sdfxtp.buf_Q), line:53:10, endln:53:15 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfxtp (work@sky130_fd_sc_hd__sdfxtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfxtp.functional.v, line:37:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__sdfxtp (work@sky130_fd_sc_hd__sdfxtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfxtp.functional.v, line:37:1, endln:61:10 |vpiName:buf_Q |vpiFullName:work@sky130_fd_sc_hd__sdfxtp.buf_Q |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__sdfxtp.mux_out), line:54:10, endln:54:17 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfxtp (work@sky130_fd_sc_hd__sdfxtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfxtp.functional.v, line:37:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__sdfxtp (work@sky130_fd_sc_hd__sdfxtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfxtp.functional.v, line:37:1, endln:61:10 |vpiName:mux_out |vpiFullName:work@sky130_fd_sc_hd__sdfxtp.mux_out |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__sdfxtp.Q), line:38:5, endln:38:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfxtp (work@sky130_fd_sc_hd__sdfxtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfxtp.functional.v, line:37:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__sdfxtp (work@sky130_fd_sc_hd__sdfxtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfxtp.functional.v, line:37:1, endln:61:10 |vpiName:Q |vpiFullName:work@sky130_fd_sc_hd__sdfxtp.Q |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__sdfxtp.CLK), line:39:5, endln:39:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfxtp (work@sky130_fd_sc_hd__sdfxtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfxtp.functional.v, line:37:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__sdfxtp (work@sky130_fd_sc_hd__sdfxtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfxtp.functional.v, line:37:1, endln:61:10 |vpiName:CLK |vpiFullName:work@sky130_fd_sc_hd__sdfxtp.CLK |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__sdfxtp.D), line:40:5, endln:40:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfxtp (work@sky130_fd_sc_hd__sdfxtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfxtp.functional.v, line:37:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__sdfxtp (work@sky130_fd_sc_hd__sdfxtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfxtp.functional.v, line:37:1, endln:61:10 |vpiName:D |vpiFullName:work@sky130_fd_sc_hd__sdfxtp.D |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__sdfxtp.SCD), line:41:5, endln:41:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfxtp (work@sky130_fd_sc_hd__sdfxtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfxtp.functional.v, line:37:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__sdfxtp (work@sky130_fd_sc_hd__sdfxtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfxtp.functional.v, line:37:1, endln:61:10 |vpiName:SCD |vpiFullName:work@sky130_fd_sc_hd__sdfxtp.SCD |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__sdfxtp.SCE), line:42:5, endln:42:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfxtp (work@sky130_fd_sc_hd__sdfxtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfxtp.functional.v, line:37:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__sdfxtp (work@sky130_fd_sc_hd__sdfxtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfxtp.functional.v, line:37:1, endln:61:10 |vpiName:SCE |vpiFullName:work@sky130_fd_sc_hd__sdfxtp.SCE |vpiPort: \_port: (Q), line:38:5, endln:38:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfxtp (work@sky130_fd_sc_hd__sdfxtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfxtp.functional.v, line:37:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__sdfxtp (work@sky130_fd_sc_hd__sdfxtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfxtp.functional.v, line:37:1, endln:61:10 |vpiName:Q |vpiDirection:2 |vpiLowConn: @@ -14888,7 +14888,7 @@ design: (work@sky130_fd_sc_hd__sdfxtp) |vpiPort: \_port: (CLK), line:39:5, endln:39:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfxtp (work@sky130_fd_sc_hd__sdfxtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfxtp.functional.v, line:37:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__sdfxtp (work@sky130_fd_sc_hd__sdfxtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfxtp.functional.v, line:37:1, endln:61:10 |vpiName:CLK |vpiDirection:1 |vpiLowConn: @@ -14900,7 +14900,7 @@ design: (work@sky130_fd_sc_hd__sdfxtp) |vpiPort: \_port: (D), line:40:5, endln:40:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfxtp (work@sky130_fd_sc_hd__sdfxtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfxtp.functional.v, line:37:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__sdfxtp (work@sky130_fd_sc_hd__sdfxtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfxtp.functional.v, line:37:1, endln:61:10 |vpiName:D |vpiDirection:1 |vpiLowConn: @@ -14912,7 +14912,7 @@ design: (work@sky130_fd_sc_hd__sdfxtp) |vpiPort: \_port: (SCD), line:41:5, endln:41:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfxtp (work@sky130_fd_sc_hd__sdfxtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfxtp.functional.v, line:37:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__sdfxtp (work@sky130_fd_sc_hd__sdfxtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfxtp.functional.v, line:37:1, endln:61:10 |vpiName:SCD |vpiDirection:1 |vpiLowConn: @@ -14924,7 +14924,7 @@ design: (work@sky130_fd_sc_hd__sdfxtp) |vpiPort: \_port: (SCE), line:42:5, endln:42:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfxtp (work@sky130_fd_sc_hd__sdfxtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfxtp.functional.v, line:37:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__sdfxtp (work@sky130_fd_sc_hd__sdfxtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfxtp.functional.v, line:37:1, endln:61:10 |vpiName:SCE |vpiDirection:1 |vpiLowConn: @@ -14934,14 +14934,14 @@ design: (work@sky130_fd_sc_hd__sdfxtp) |vpiTypedef: \_logic_typespec: , line:50:12, endln:50:12 |uhdmtopModules: -\_module: work@sky130_fd_sc_hd__sdfxtp (work@sky130_fd_sc_hd__sdfxtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfxtp.functional.v, line:37:1, endln:61:10 +\_module_inst: work@sky130_fd_sc_hd__sdfxtp (work@sky130_fd_sc_hd__sdfxtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfxtp.functional.v, line:37:1, endln:61:10 |vpiName:work@sky130_fd_sc_hd__sdfxtp |vpiDefName:work@sky130_fd_sc_hd__sdfxtp |vpiTop:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__sdfxtp.buf_Q), line:53:10, endln:53:15 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfxtp (work@sky130_fd_sc_hd__sdfxtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfxtp.functional.v, line:37:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__sdfxtp (work@sky130_fd_sc_hd__sdfxtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfxtp.functional.v, line:37:1, endln:61:10 |vpiTypespec: \_logic_typespec: , line:53:5, endln:53:9 |vpiName:buf_Q @@ -14950,7 +14950,7 @@ design: (work@sky130_fd_sc_hd__sdfxtp) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__sdfxtp.mux_out), line:54:10, endln:54:17 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfxtp (work@sky130_fd_sc_hd__sdfxtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfxtp.functional.v, line:37:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__sdfxtp (work@sky130_fd_sc_hd__sdfxtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfxtp.functional.v, line:37:1, endln:61:10 |vpiTypespec: \_logic_typespec: , line:54:5, endln:54:9 |vpiName:mux_out @@ -14959,7 +14959,7 @@ design: (work@sky130_fd_sc_hd__sdfxtp) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__sdfxtp.Q), line:38:5, endln:38:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfxtp (work@sky130_fd_sc_hd__sdfxtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfxtp.functional.v, line:37:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__sdfxtp (work@sky130_fd_sc_hd__sdfxtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfxtp.functional.v, line:37:1, endln:61:10 |vpiTypespec: \_logic_typespec: , line:46:12, endln:46:12 |vpiName:Q @@ -14967,7 +14967,7 @@ design: (work@sky130_fd_sc_hd__sdfxtp) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__sdfxtp.CLK), line:39:5, endln:39:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfxtp (work@sky130_fd_sc_hd__sdfxtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfxtp.functional.v, line:37:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__sdfxtp (work@sky130_fd_sc_hd__sdfxtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfxtp.functional.v, line:37:1, endln:61:10 |vpiTypespec: \_logic_typespec: , line:47:12, endln:47:12 |vpiName:CLK @@ -14975,7 +14975,7 @@ design: (work@sky130_fd_sc_hd__sdfxtp) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__sdfxtp.D), line:40:5, endln:40:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfxtp (work@sky130_fd_sc_hd__sdfxtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfxtp.functional.v, line:37:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__sdfxtp (work@sky130_fd_sc_hd__sdfxtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfxtp.functional.v, line:37:1, endln:61:10 |vpiTypespec: \_logic_typespec: , line:48:12, endln:48:12 |vpiName:D @@ -14983,7 +14983,7 @@ design: (work@sky130_fd_sc_hd__sdfxtp) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__sdfxtp.SCD), line:41:5, endln:41:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfxtp (work@sky130_fd_sc_hd__sdfxtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfxtp.functional.v, line:37:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__sdfxtp (work@sky130_fd_sc_hd__sdfxtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfxtp.functional.v, line:37:1, endln:61:10 |vpiTypespec: \_logic_typespec: , line:49:12, endln:49:12 |vpiName:SCD @@ -14991,7 +14991,7 @@ design: (work@sky130_fd_sc_hd__sdfxtp) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__sdfxtp.SCE), line:42:5, endln:42:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfxtp (work@sky130_fd_sc_hd__sdfxtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfxtp.functional.v, line:37:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__sdfxtp (work@sky130_fd_sc_hd__sdfxtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfxtp.functional.v, line:37:1, endln:61:10 |vpiTypespec: \_logic_typespec: , line:50:12, endln:50:12 |vpiName:SCE @@ -15000,7 +15000,7 @@ design: (work@sky130_fd_sc_hd__sdfxtp) |vpiPort: \_port: (Q), line:38:5, endln:38:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfxtp (work@sky130_fd_sc_hd__sdfxtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfxtp.functional.v, line:37:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__sdfxtp (work@sky130_fd_sc_hd__sdfxtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfxtp.functional.v, line:37:1, endln:61:10 |vpiName:Q |vpiDirection:2 |vpiLowConn: @@ -15014,7 +15014,7 @@ design: (work@sky130_fd_sc_hd__sdfxtp) |vpiPort: \_port: (CLK), line:39:5, endln:39:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfxtp (work@sky130_fd_sc_hd__sdfxtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfxtp.functional.v, line:37:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__sdfxtp (work@sky130_fd_sc_hd__sdfxtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfxtp.functional.v, line:37:1, endln:61:10 |vpiName:CLK |vpiDirection:1 |vpiLowConn: @@ -15028,7 +15028,7 @@ design: (work@sky130_fd_sc_hd__sdfxtp) |vpiPort: \_port: (D), line:40:5, endln:40:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfxtp (work@sky130_fd_sc_hd__sdfxtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfxtp.functional.v, line:37:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__sdfxtp (work@sky130_fd_sc_hd__sdfxtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfxtp.functional.v, line:37:1, endln:61:10 |vpiName:D |vpiDirection:1 |vpiLowConn: @@ -15042,7 +15042,7 @@ design: (work@sky130_fd_sc_hd__sdfxtp) |vpiPort: \_port: (SCD), line:41:5, endln:41:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfxtp (work@sky130_fd_sc_hd__sdfxtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfxtp.functional.v, line:37:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__sdfxtp (work@sky130_fd_sc_hd__sdfxtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfxtp.functional.v, line:37:1, endln:61:10 |vpiName:SCD |vpiDirection:1 |vpiLowConn: @@ -15056,7 +15056,7 @@ design: (work@sky130_fd_sc_hd__sdfxtp) |vpiPort: \_port: (SCE), line:42:5, endln:42:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfxtp (work@sky130_fd_sc_hd__sdfxtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfxtp.functional.v, line:37:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__sdfxtp (work@sky130_fd_sc_hd__sdfxtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfxtp.functional.v, line:37:1, endln:61:10 |vpiName:SCE |vpiDirection:1 |vpiLowConn: @@ -15070,7 +15070,7 @@ design: (work@sky130_fd_sc_hd__sdfxtp) |vpiPrimitive: \_udp: work@sky130_fd_sc_hd__udp_mux_2to1 (work@sky130_fd_sc_hd__sdfxtp.mux_2to10), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfxtp.functional.v, line:57:5, endln:57:84 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfxtp (work@sky130_fd_sc_hd__sdfxtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfxtp.functional.v, line:37:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__sdfxtp (work@sky130_fd_sc_hd__sdfxtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfxtp.functional.v, line:37:1, endln:61:10 |vpiDefName:work@sky130_fd_sc_hd__udp_mux_2to1 |vpiName:mux_2to10 |vpiFullName:work@sky130_fd_sc_hd__sdfxtp.mux_2to10 @@ -15079,7 +15079,7 @@ design: (work@sky130_fd_sc_hd__sdfxtp) |vpiPrimitive: \_udp: work@sky130_fd_sc_hd__udp_dff$P (work@sky130_fd_sc_hd__sdfxtp.dff0), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfxtp.functional.v, line:58:5, endln:58:73 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfxtp (work@sky130_fd_sc_hd__sdfxtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfxtp.functional.v, line:37:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__sdfxtp (work@sky130_fd_sc_hd__sdfxtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfxtp.functional.v, line:37:1, endln:61:10 |vpiDefName:work@sky130_fd_sc_hd__udp_dff$P |vpiName:dff0 |vpiFullName:work@sky130_fd_sc_hd__sdfxtp.dff0 @@ -15088,7 +15088,7 @@ design: (work@sky130_fd_sc_hd__sdfxtp) |vpiPrimitive: \_gate: work@buf (work@sky130_fd_sc_hd__sdfxtp.buf0), line:59:47, endln:59:83 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfxtp (work@sky130_fd_sc_hd__sdfxtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfxtp.functional.v, line:37:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__sdfxtp (work@sky130_fd_sc_hd__sdfxtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfxtp.functional.v, line:37:1, endln:61:10 |vpiDefName:work@buf |vpiName:buf0 |vpiFullName:work@sky130_fd_sc_hd__sdfxtp.buf0 @@ -15131,7 +15131,7 @@ Processing: -cd cells/cells -DUNIT_DELAY -writepp -parse -nocache -nobuiltin -no design: (work@sky130_fd_sc_hd__probec_p) |vpiName:work@sky130_fd_sc_hd__probec_p |uhdmallModules: -\_module: work@sky130_fd_sc_hd__probec_p (work@sky130_fd_sc_hd__probec_p), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__probec_p.functional.v, line:33:1, endln:49:10 +\_module_inst: work@sky130_fd_sc_hd__probec_p (work@sky130_fd_sc_hd__probec_p), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__probec_p.functional.v, line:33:1, endln:49:10 |vpiParent: \_design: (work@sky130_fd_sc_hd__probec_p) |vpiFullName:work@sky130_fd_sc_hd__probec_p @@ -15139,26 +15139,26 @@ design: (work@sky130_fd_sc_hd__probec_p) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__probec_p.buf0_out_X), line:43:10, endln:43:20 |vpiParent: - \_module: work@sky130_fd_sc_hd__probec_p (work@sky130_fd_sc_hd__probec_p), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__probec_p.functional.v, line:33:1, endln:49:10 + \_module_inst: work@sky130_fd_sc_hd__probec_p (work@sky130_fd_sc_hd__probec_p), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__probec_p.functional.v, line:33:1, endln:49:10 |vpiName:buf0_out_X |vpiFullName:work@sky130_fd_sc_hd__probec_p.buf0_out_X |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__probec_p.X), line:34:5, endln:34:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__probec_p (work@sky130_fd_sc_hd__probec_p), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__probec_p.functional.v, line:33:1, endln:49:10 + \_module_inst: work@sky130_fd_sc_hd__probec_p (work@sky130_fd_sc_hd__probec_p), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__probec_p.functional.v, line:33:1, endln:49:10 |vpiName:X |vpiFullName:work@sky130_fd_sc_hd__probec_p.X |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__probec_p.A), line:35:5, endln:35:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__probec_p (work@sky130_fd_sc_hd__probec_p), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__probec_p.functional.v, line:33:1, endln:49:10 + \_module_inst: work@sky130_fd_sc_hd__probec_p (work@sky130_fd_sc_hd__probec_p), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__probec_p.functional.v, line:33:1, endln:49:10 |vpiName:A |vpiFullName:work@sky130_fd_sc_hd__probec_p.A |vpiPort: \_port: (X), line:34:5, endln:34:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__probec_p (work@sky130_fd_sc_hd__probec_p), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__probec_p.functional.v, line:33:1, endln:49:10 + \_module_inst: work@sky130_fd_sc_hd__probec_p (work@sky130_fd_sc_hd__probec_p), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__probec_p.functional.v, line:33:1, endln:49:10 |vpiName:X |vpiDirection:2 |vpiLowConn: @@ -15170,7 +15170,7 @@ design: (work@sky130_fd_sc_hd__probec_p) |vpiPort: \_port: (A), line:35:5, endln:35:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__probec_p (work@sky130_fd_sc_hd__probec_p), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__probec_p.functional.v, line:33:1, endln:49:10 + \_module_inst: work@sky130_fd_sc_hd__probec_p (work@sky130_fd_sc_hd__probec_p), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__probec_p.functional.v, line:33:1, endln:49:10 |vpiName:A |vpiDirection:1 |vpiLowConn: @@ -15180,14 +15180,14 @@ design: (work@sky130_fd_sc_hd__probec_p) |vpiTypedef: \_logic_typespec: , line:40:12, endln:40:12 |uhdmtopModules: -\_module: work@sky130_fd_sc_hd__probec_p (work@sky130_fd_sc_hd__probec_p), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__probec_p.functional.v, line:33:1, endln:49:10 +\_module_inst: work@sky130_fd_sc_hd__probec_p (work@sky130_fd_sc_hd__probec_p), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__probec_p.functional.v, line:33:1, endln:49:10 |vpiName:work@sky130_fd_sc_hd__probec_p |vpiDefName:work@sky130_fd_sc_hd__probec_p |vpiTop:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__probec_p.buf0_out_X), line:43:10, endln:43:20 |vpiParent: - \_module: work@sky130_fd_sc_hd__probec_p (work@sky130_fd_sc_hd__probec_p), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__probec_p.functional.v, line:33:1, endln:49:10 + \_module_inst: work@sky130_fd_sc_hd__probec_p (work@sky130_fd_sc_hd__probec_p), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__probec_p.functional.v, line:33:1, endln:49:10 |vpiTypespec: \_logic_typespec: , line:43:5, endln:43:9 |vpiName:buf0_out_X @@ -15196,7 +15196,7 @@ design: (work@sky130_fd_sc_hd__probec_p) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__probec_p.X), line:34:5, endln:34:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__probec_p (work@sky130_fd_sc_hd__probec_p), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__probec_p.functional.v, line:33:1, endln:49:10 + \_module_inst: work@sky130_fd_sc_hd__probec_p (work@sky130_fd_sc_hd__probec_p), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__probec_p.functional.v, line:33:1, endln:49:10 |vpiTypespec: \_logic_typespec: , line:39:12, endln:39:12 |vpiName:X @@ -15204,7 +15204,7 @@ design: (work@sky130_fd_sc_hd__probec_p) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__probec_p.A), line:35:5, endln:35:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__probec_p (work@sky130_fd_sc_hd__probec_p), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__probec_p.functional.v, line:33:1, endln:49:10 + \_module_inst: work@sky130_fd_sc_hd__probec_p (work@sky130_fd_sc_hd__probec_p), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__probec_p.functional.v, line:33:1, endln:49:10 |vpiTypespec: \_logic_typespec: , line:40:12, endln:40:12 |vpiName:A @@ -15213,7 +15213,7 @@ design: (work@sky130_fd_sc_hd__probec_p) |vpiPort: \_port: (X), line:34:5, endln:34:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__probec_p (work@sky130_fd_sc_hd__probec_p), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__probec_p.functional.v, line:33:1, endln:49:10 + \_module_inst: work@sky130_fd_sc_hd__probec_p (work@sky130_fd_sc_hd__probec_p), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__probec_p.functional.v, line:33:1, endln:49:10 |vpiName:X |vpiDirection:2 |vpiLowConn: @@ -15227,7 +15227,7 @@ design: (work@sky130_fd_sc_hd__probec_p) |vpiPort: \_port: (A), line:35:5, endln:35:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__probec_p (work@sky130_fd_sc_hd__probec_p), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__probec_p.functional.v, line:33:1, endln:49:10 + \_module_inst: work@sky130_fd_sc_hd__probec_p (work@sky130_fd_sc_hd__probec_p), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__probec_p.functional.v, line:33:1, endln:49:10 |vpiName:A |vpiDirection:1 |vpiLowConn: @@ -15241,7 +15241,7 @@ design: (work@sky130_fd_sc_hd__probec_p) |vpiPrimitive: \_gate: work@buf (work@sky130_fd_sc_hd__probec_p.buf0), line:46:9, endln:46:43 |vpiParent: - \_module: work@sky130_fd_sc_hd__probec_p (work@sky130_fd_sc_hd__probec_p), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__probec_p.functional.v, line:33:1, endln:49:10 + \_module_inst: work@sky130_fd_sc_hd__probec_p (work@sky130_fd_sc_hd__probec_p), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__probec_p.functional.v, line:33:1, endln:49:10 |vpiDefName:work@buf |vpiName:buf0 |vpiFullName:work@sky130_fd_sc_hd__probec_p.buf0 @@ -15276,7 +15276,7 @@ design: (work@sky130_fd_sc_hd__probec_p) |vpiPrimitive: \_gate: work@buf (work@sky130_fd_sc_hd__probec_p.buf1), line:47:9, endln:47:43 |vpiParent: - \_module: work@sky130_fd_sc_hd__probec_p (work@sky130_fd_sc_hd__probec_p), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__probec_p.functional.v, line:33:1, endln:49:10 + \_module_inst: work@sky130_fd_sc_hd__probec_p (work@sky130_fd_sc_hd__probec_p), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__probec_p.functional.v, line:33:1, endln:49:10 |vpiDefName:work@buf |vpiName:buf1 |vpiFullName:work@sky130_fd_sc_hd__probec_p.buf1 @@ -15319,7 +15319,7 @@ Processing: -cd cells/cells -DUNIT_DELAY -writepp -parse -nocache -nobuiltin -no design: (work@sky130_fd_sc_hd__a211oi) |vpiName:work@sky130_fd_sc_hd__a211oi |uhdmallModules: -\_module: work@sky130_fd_sc_hd__a211oi (work@sky130_fd_sc_hd__a211oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a211oi.functional.v, line:35:1, endln:59:10 +\_module_inst: work@sky130_fd_sc_hd__a211oi (work@sky130_fd_sc_hd__a211oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a211oi.functional.v, line:35:1, endln:59:10 |vpiParent: \_design: (work@sky130_fd_sc_hd__a211oi) |vpiFullName:work@sky130_fd_sc_hd__a211oi @@ -15327,51 +15327,51 @@ design: (work@sky130_fd_sc_hd__a211oi) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a211oi.and0_out), line:51:10, endln:51:18 |vpiParent: - \_module: work@sky130_fd_sc_hd__a211oi (work@sky130_fd_sc_hd__a211oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a211oi.functional.v, line:35:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__a211oi (work@sky130_fd_sc_hd__a211oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a211oi.functional.v, line:35:1, endln:59:10 |vpiName:and0_out |vpiFullName:work@sky130_fd_sc_hd__a211oi.and0_out |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a211oi.nor0_out_Y), line:52:10, endln:52:20 |vpiParent: - \_module: work@sky130_fd_sc_hd__a211oi (work@sky130_fd_sc_hd__a211oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a211oi.functional.v, line:35:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__a211oi (work@sky130_fd_sc_hd__a211oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a211oi.functional.v, line:35:1, endln:59:10 |vpiName:nor0_out_Y |vpiFullName:work@sky130_fd_sc_hd__a211oi.nor0_out_Y |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a211oi.Y), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__a211oi (work@sky130_fd_sc_hd__a211oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a211oi.functional.v, line:35:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__a211oi (work@sky130_fd_sc_hd__a211oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a211oi.functional.v, line:35:1, endln:59:10 |vpiName:Y |vpiFullName:work@sky130_fd_sc_hd__a211oi.Y |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a211oi.A1), line:37:5, endln:37:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a211oi (work@sky130_fd_sc_hd__a211oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a211oi.functional.v, line:35:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__a211oi (work@sky130_fd_sc_hd__a211oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a211oi.functional.v, line:35:1, endln:59:10 |vpiName:A1 |vpiFullName:work@sky130_fd_sc_hd__a211oi.A1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a211oi.A2), line:38:5, endln:38:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a211oi (work@sky130_fd_sc_hd__a211oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a211oi.functional.v, line:35:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__a211oi (work@sky130_fd_sc_hd__a211oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a211oi.functional.v, line:35:1, endln:59:10 |vpiName:A2 |vpiFullName:work@sky130_fd_sc_hd__a211oi.A2 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a211oi.B1), line:39:5, endln:39:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a211oi (work@sky130_fd_sc_hd__a211oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a211oi.functional.v, line:35:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__a211oi (work@sky130_fd_sc_hd__a211oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a211oi.functional.v, line:35:1, endln:59:10 |vpiName:B1 |vpiFullName:work@sky130_fd_sc_hd__a211oi.B1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a211oi.C1), line:40:5, endln:40:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a211oi (work@sky130_fd_sc_hd__a211oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a211oi.functional.v, line:35:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__a211oi (work@sky130_fd_sc_hd__a211oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a211oi.functional.v, line:35:1, endln:59:10 |vpiName:C1 |vpiFullName:work@sky130_fd_sc_hd__a211oi.C1 |vpiPort: \_port: (Y), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__a211oi (work@sky130_fd_sc_hd__a211oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a211oi.functional.v, line:35:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__a211oi (work@sky130_fd_sc_hd__a211oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a211oi.functional.v, line:35:1, endln:59:10 |vpiName:Y |vpiDirection:2 |vpiLowConn: @@ -15383,7 +15383,7 @@ design: (work@sky130_fd_sc_hd__a211oi) |vpiPort: \_port: (A1), line:37:5, endln:37:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a211oi (work@sky130_fd_sc_hd__a211oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a211oi.functional.v, line:35:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__a211oi (work@sky130_fd_sc_hd__a211oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a211oi.functional.v, line:35:1, endln:59:10 |vpiName:A1 |vpiDirection:1 |vpiLowConn: @@ -15395,7 +15395,7 @@ design: (work@sky130_fd_sc_hd__a211oi) |vpiPort: \_port: (A2), line:38:5, endln:38:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a211oi (work@sky130_fd_sc_hd__a211oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a211oi.functional.v, line:35:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__a211oi (work@sky130_fd_sc_hd__a211oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a211oi.functional.v, line:35:1, endln:59:10 |vpiName:A2 |vpiDirection:1 |vpiLowConn: @@ -15407,7 +15407,7 @@ design: (work@sky130_fd_sc_hd__a211oi) |vpiPort: \_port: (B1), line:39:5, endln:39:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a211oi (work@sky130_fd_sc_hd__a211oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a211oi.functional.v, line:35:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__a211oi (work@sky130_fd_sc_hd__a211oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a211oi.functional.v, line:35:1, endln:59:10 |vpiName:B1 |vpiDirection:1 |vpiLowConn: @@ -15419,7 +15419,7 @@ design: (work@sky130_fd_sc_hd__a211oi) |vpiPort: \_port: (C1), line:40:5, endln:40:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a211oi (work@sky130_fd_sc_hd__a211oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a211oi.functional.v, line:35:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__a211oi (work@sky130_fd_sc_hd__a211oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a211oi.functional.v, line:35:1, endln:59:10 |vpiName:C1 |vpiDirection:1 |vpiLowConn: @@ -15429,14 +15429,14 @@ design: (work@sky130_fd_sc_hd__a211oi) |vpiTypedef: \_logic_typespec: , line:48:12, endln:48:12 |uhdmtopModules: -\_module: work@sky130_fd_sc_hd__a211oi (work@sky130_fd_sc_hd__a211oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a211oi.functional.v, line:35:1, endln:59:10 +\_module_inst: work@sky130_fd_sc_hd__a211oi (work@sky130_fd_sc_hd__a211oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a211oi.functional.v, line:35:1, endln:59:10 |vpiName:work@sky130_fd_sc_hd__a211oi |vpiDefName:work@sky130_fd_sc_hd__a211oi |vpiTop:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a211oi.and0_out), line:51:10, endln:51:18 |vpiParent: - \_module: work@sky130_fd_sc_hd__a211oi (work@sky130_fd_sc_hd__a211oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a211oi.functional.v, line:35:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__a211oi (work@sky130_fd_sc_hd__a211oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a211oi.functional.v, line:35:1, endln:59:10 |vpiTypespec: \_logic_typespec: , line:51:5, endln:51:9 |vpiName:and0_out @@ -15445,7 +15445,7 @@ design: (work@sky130_fd_sc_hd__a211oi) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a211oi.nor0_out_Y), line:52:10, endln:52:20 |vpiParent: - \_module: work@sky130_fd_sc_hd__a211oi (work@sky130_fd_sc_hd__a211oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a211oi.functional.v, line:35:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__a211oi (work@sky130_fd_sc_hd__a211oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a211oi.functional.v, line:35:1, endln:59:10 |vpiTypespec: \_logic_typespec: , line:52:5, endln:52:9 |vpiName:nor0_out_Y @@ -15454,7 +15454,7 @@ design: (work@sky130_fd_sc_hd__a211oi) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a211oi.Y), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__a211oi (work@sky130_fd_sc_hd__a211oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a211oi.functional.v, line:35:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__a211oi (work@sky130_fd_sc_hd__a211oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a211oi.functional.v, line:35:1, endln:59:10 |vpiTypespec: \_logic_typespec: , line:44:12, endln:44:12 |vpiName:Y @@ -15462,7 +15462,7 @@ design: (work@sky130_fd_sc_hd__a211oi) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a211oi.A1), line:37:5, endln:37:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a211oi (work@sky130_fd_sc_hd__a211oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a211oi.functional.v, line:35:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__a211oi (work@sky130_fd_sc_hd__a211oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a211oi.functional.v, line:35:1, endln:59:10 |vpiTypespec: \_logic_typespec: , line:45:12, endln:45:12 |vpiName:A1 @@ -15470,7 +15470,7 @@ design: (work@sky130_fd_sc_hd__a211oi) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a211oi.A2), line:38:5, endln:38:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a211oi (work@sky130_fd_sc_hd__a211oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a211oi.functional.v, line:35:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__a211oi (work@sky130_fd_sc_hd__a211oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a211oi.functional.v, line:35:1, endln:59:10 |vpiTypespec: \_logic_typespec: , line:46:12, endln:46:12 |vpiName:A2 @@ -15478,7 +15478,7 @@ design: (work@sky130_fd_sc_hd__a211oi) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a211oi.B1), line:39:5, endln:39:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a211oi (work@sky130_fd_sc_hd__a211oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a211oi.functional.v, line:35:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__a211oi (work@sky130_fd_sc_hd__a211oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a211oi.functional.v, line:35:1, endln:59:10 |vpiTypespec: \_logic_typespec: , line:47:12, endln:47:12 |vpiName:B1 @@ -15486,7 +15486,7 @@ design: (work@sky130_fd_sc_hd__a211oi) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a211oi.C1), line:40:5, endln:40:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a211oi (work@sky130_fd_sc_hd__a211oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a211oi.functional.v, line:35:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__a211oi (work@sky130_fd_sc_hd__a211oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a211oi.functional.v, line:35:1, endln:59:10 |vpiTypespec: \_logic_typespec: , line:48:12, endln:48:12 |vpiName:C1 @@ -15495,7 +15495,7 @@ design: (work@sky130_fd_sc_hd__a211oi) |vpiPort: \_port: (Y), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__a211oi (work@sky130_fd_sc_hd__a211oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a211oi.functional.v, line:35:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__a211oi (work@sky130_fd_sc_hd__a211oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a211oi.functional.v, line:35:1, endln:59:10 |vpiName:Y |vpiDirection:2 |vpiLowConn: @@ -15509,7 +15509,7 @@ design: (work@sky130_fd_sc_hd__a211oi) |vpiPort: \_port: (A1), line:37:5, endln:37:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a211oi (work@sky130_fd_sc_hd__a211oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a211oi.functional.v, line:35:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__a211oi (work@sky130_fd_sc_hd__a211oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a211oi.functional.v, line:35:1, endln:59:10 |vpiName:A1 |vpiDirection:1 |vpiLowConn: @@ -15523,7 +15523,7 @@ design: (work@sky130_fd_sc_hd__a211oi) |vpiPort: \_port: (A2), line:38:5, endln:38:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a211oi (work@sky130_fd_sc_hd__a211oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a211oi.functional.v, line:35:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__a211oi (work@sky130_fd_sc_hd__a211oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a211oi.functional.v, line:35:1, endln:59:10 |vpiName:A2 |vpiDirection:1 |vpiLowConn: @@ -15537,7 +15537,7 @@ design: (work@sky130_fd_sc_hd__a211oi) |vpiPort: \_port: (B1), line:39:5, endln:39:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a211oi (work@sky130_fd_sc_hd__a211oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a211oi.functional.v, line:35:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__a211oi (work@sky130_fd_sc_hd__a211oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a211oi.functional.v, line:35:1, endln:59:10 |vpiName:B1 |vpiDirection:1 |vpiLowConn: @@ -15551,7 +15551,7 @@ design: (work@sky130_fd_sc_hd__a211oi) |vpiPort: \_port: (C1), line:40:5, endln:40:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a211oi (work@sky130_fd_sc_hd__a211oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a211oi.functional.v, line:35:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__a211oi (work@sky130_fd_sc_hd__a211oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a211oi.functional.v, line:35:1, endln:59:10 |vpiName:C1 |vpiDirection:1 |vpiLowConn: @@ -15565,7 +15565,7 @@ design: (work@sky130_fd_sc_hd__a211oi) |vpiPrimitive: \_gate: work@and (work@sky130_fd_sc_hd__a211oi.and0), line:55:9, endln:55:44 |vpiParent: - \_module: work@sky130_fd_sc_hd__a211oi (work@sky130_fd_sc_hd__a211oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a211oi.functional.v, line:35:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__a211oi (work@sky130_fd_sc_hd__a211oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a211oi.functional.v, line:35:1, endln:59:10 |vpiDefName:work@and |vpiName:and0 |vpiFullName:work@sky130_fd_sc_hd__a211oi.and0 @@ -15614,7 +15614,7 @@ design: (work@sky130_fd_sc_hd__a211oi) |vpiPrimitive: \_gate: work@nor (work@sky130_fd_sc_hd__a211oi.nor0), line:56:9, endln:56:44 |vpiParent: - \_module: work@sky130_fd_sc_hd__a211oi (work@sky130_fd_sc_hd__a211oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a211oi.functional.v, line:35:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__a211oi (work@sky130_fd_sc_hd__a211oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a211oi.functional.v, line:35:1, endln:59:10 |vpiDefName:work@nor |vpiName:nor0 |vpiFullName:work@sky130_fd_sc_hd__a211oi.nor0 @@ -15677,7 +15677,7 @@ design: (work@sky130_fd_sc_hd__a211oi) |vpiPrimitive: \_gate: work@buf (work@sky130_fd_sc_hd__a211oi.buf0), line:57:9, endln:57:44 |vpiParent: - \_module: work@sky130_fd_sc_hd__a211oi (work@sky130_fd_sc_hd__a211oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a211oi.functional.v, line:35:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__a211oi (work@sky130_fd_sc_hd__a211oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a211oi.functional.v, line:35:1, endln:59:10 |vpiDefName:work@buf |vpiName:buf0 |vpiFullName:work@sky130_fd_sc_hd__a211oi.buf0 @@ -15720,7 +15720,7 @@ Processing: -cd cells/cells -DUNIT_DELAY -writepp -parse -nocache -nobuiltin -no design: (work@sky130_fd_sc_hd__o22a) |vpiName:work@sky130_fd_sc_hd__o22a |uhdmallModules: -\_module: work@sky130_fd_sc_hd__o22a (work@sky130_fd_sc_hd__o22a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o22a.functional.v, line:35:1, endln:61:10 +\_module_inst: work@sky130_fd_sc_hd__o22a (work@sky130_fd_sc_hd__o22a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o22a.functional.v, line:35:1, endln:61:10 |vpiParent: \_design: (work@sky130_fd_sc_hd__o22a) |vpiFullName:work@sky130_fd_sc_hd__o22a @@ -15728,58 +15728,58 @@ design: (work@sky130_fd_sc_hd__o22a) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o22a.or0_out), line:51:10, endln:51:17 |vpiParent: - \_module: work@sky130_fd_sc_hd__o22a (work@sky130_fd_sc_hd__o22a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o22a.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o22a (work@sky130_fd_sc_hd__o22a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o22a.functional.v, line:35:1, endln:61:10 |vpiName:or0_out |vpiFullName:work@sky130_fd_sc_hd__o22a.or0_out |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o22a.or1_out), line:52:10, endln:52:17 |vpiParent: - \_module: work@sky130_fd_sc_hd__o22a (work@sky130_fd_sc_hd__o22a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o22a.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o22a (work@sky130_fd_sc_hd__o22a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o22a.functional.v, line:35:1, endln:61:10 |vpiName:or1_out |vpiFullName:work@sky130_fd_sc_hd__o22a.or1_out |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o22a.and0_out_X), line:53:10, endln:53:20 |vpiParent: - \_module: work@sky130_fd_sc_hd__o22a (work@sky130_fd_sc_hd__o22a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o22a.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o22a (work@sky130_fd_sc_hd__o22a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o22a.functional.v, line:35:1, endln:61:10 |vpiName:and0_out_X |vpiFullName:work@sky130_fd_sc_hd__o22a.and0_out_X |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o22a.X), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__o22a (work@sky130_fd_sc_hd__o22a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o22a.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o22a (work@sky130_fd_sc_hd__o22a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o22a.functional.v, line:35:1, endln:61:10 |vpiName:X |vpiFullName:work@sky130_fd_sc_hd__o22a.X |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o22a.A1), line:37:5, endln:37:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o22a (work@sky130_fd_sc_hd__o22a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o22a.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o22a (work@sky130_fd_sc_hd__o22a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o22a.functional.v, line:35:1, endln:61:10 |vpiName:A1 |vpiFullName:work@sky130_fd_sc_hd__o22a.A1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o22a.A2), line:38:5, endln:38:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o22a (work@sky130_fd_sc_hd__o22a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o22a.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o22a (work@sky130_fd_sc_hd__o22a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o22a.functional.v, line:35:1, endln:61:10 |vpiName:A2 |vpiFullName:work@sky130_fd_sc_hd__o22a.A2 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o22a.B1), line:39:5, endln:39:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o22a (work@sky130_fd_sc_hd__o22a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o22a.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o22a (work@sky130_fd_sc_hd__o22a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o22a.functional.v, line:35:1, endln:61:10 |vpiName:B1 |vpiFullName:work@sky130_fd_sc_hd__o22a.B1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o22a.B2), line:40:5, endln:40:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o22a (work@sky130_fd_sc_hd__o22a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o22a.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o22a (work@sky130_fd_sc_hd__o22a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o22a.functional.v, line:35:1, endln:61:10 |vpiName:B2 |vpiFullName:work@sky130_fd_sc_hd__o22a.B2 |vpiPort: \_port: (X), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__o22a (work@sky130_fd_sc_hd__o22a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o22a.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o22a (work@sky130_fd_sc_hd__o22a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o22a.functional.v, line:35:1, endln:61:10 |vpiName:X |vpiDirection:2 |vpiLowConn: @@ -15791,7 +15791,7 @@ design: (work@sky130_fd_sc_hd__o22a) |vpiPort: \_port: (A1), line:37:5, endln:37:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o22a (work@sky130_fd_sc_hd__o22a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o22a.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o22a (work@sky130_fd_sc_hd__o22a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o22a.functional.v, line:35:1, endln:61:10 |vpiName:A1 |vpiDirection:1 |vpiLowConn: @@ -15803,7 +15803,7 @@ design: (work@sky130_fd_sc_hd__o22a) |vpiPort: \_port: (A2), line:38:5, endln:38:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o22a (work@sky130_fd_sc_hd__o22a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o22a.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o22a (work@sky130_fd_sc_hd__o22a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o22a.functional.v, line:35:1, endln:61:10 |vpiName:A2 |vpiDirection:1 |vpiLowConn: @@ -15815,7 +15815,7 @@ design: (work@sky130_fd_sc_hd__o22a) |vpiPort: \_port: (B1), line:39:5, endln:39:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o22a (work@sky130_fd_sc_hd__o22a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o22a.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o22a (work@sky130_fd_sc_hd__o22a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o22a.functional.v, line:35:1, endln:61:10 |vpiName:B1 |vpiDirection:1 |vpiLowConn: @@ -15827,7 +15827,7 @@ design: (work@sky130_fd_sc_hd__o22a) |vpiPort: \_port: (B2), line:40:5, endln:40:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o22a (work@sky130_fd_sc_hd__o22a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o22a.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o22a (work@sky130_fd_sc_hd__o22a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o22a.functional.v, line:35:1, endln:61:10 |vpiName:B2 |vpiDirection:1 |vpiLowConn: @@ -15837,14 +15837,14 @@ design: (work@sky130_fd_sc_hd__o22a) |vpiTypedef: \_logic_typespec: , line:48:12, endln:48:12 |uhdmtopModules: -\_module: work@sky130_fd_sc_hd__o22a (work@sky130_fd_sc_hd__o22a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o22a.functional.v, line:35:1, endln:61:10 +\_module_inst: work@sky130_fd_sc_hd__o22a (work@sky130_fd_sc_hd__o22a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o22a.functional.v, line:35:1, endln:61:10 |vpiName:work@sky130_fd_sc_hd__o22a |vpiDefName:work@sky130_fd_sc_hd__o22a |vpiTop:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o22a.or0_out), line:51:10, endln:51:17 |vpiParent: - \_module: work@sky130_fd_sc_hd__o22a (work@sky130_fd_sc_hd__o22a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o22a.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o22a (work@sky130_fd_sc_hd__o22a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o22a.functional.v, line:35:1, endln:61:10 |vpiTypespec: \_logic_typespec: , line:51:5, endln:51:9 |vpiName:or0_out @@ -15853,7 +15853,7 @@ design: (work@sky130_fd_sc_hd__o22a) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o22a.or1_out), line:52:10, endln:52:17 |vpiParent: - \_module: work@sky130_fd_sc_hd__o22a (work@sky130_fd_sc_hd__o22a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o22a.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o22a (work@sky130_fd_sc_hd__o22a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o22a.functional.v, line:35:1, endln:61:10 |vpiTypespec: \_logic_typespec: , line:52:5, endln:52:9 |vpiName:or1_out @@ -15862,7 +15862,7 @@ design: (work@sky130_fd_sc_hd__o22a) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o22a.and0_out_X), line:53:10, endln:53:20 |vpiParent: - \_module: work@sky130_fd_sc_hd__o22a (work@sky130_fd_sc_hd__o22a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o22a.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o22a (work@sky130_fd_sc_hd__o22a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o22a.functional.v, line:35:1, endln:61:10 |vpiTypespec: \_logic_typespec: , line:53:5, endln:53:9 |vpiName:and0_out_X @@ -15871,7 +15871,7 @@ design: (work@sky130_fd_sc_hd__o22a) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o22a.X), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__o22a (work@sky130_fd_sc_hd__o22a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o22a.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o22a (work@sky130_fd_sc_hd__o22a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o22a.functional.v, line:35:1, endln:61:10 |vpiTypespec: \_logic_typespec: , line:44:12, endln:44:12 |vpiName:X @@ -15879,7 +15879,7 @@ design: (work@sky130_fd_sc_hd__o22a) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o22a.A1), line:37:5, endln:37:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o22a (work@sky130_fd_sc_hd__o22a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o22a.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o22a (work@sky130_fd_sc_hd__o22a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o22a.functional.v, line:35:1, endln:61:10 |vpiTypespec: \_logic_typespec: , line:45:12, endln:45:12 |vpiName:A1 @@ -15887,7 +15887,7 @@ design: (work@sky130_fd_sc_hd__o22a) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o22a.A2), line:38:5, endln:38:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o22a (work@sky130_fd_sc_hd__o22a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o22a.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o22a (work@sky130_fd_sc_hd__o22a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o22a.functional.v, line:35:1, endln:61:10 |vpiTypespec: \_logic_typespec: , line:46:12, endln:46:12 |vpiName:A2 @@ -15895,7 +15895,7 @@ design: (work@sky130_fd_sc_hd__o22a) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o22a.B1), line:39:5, endln:39:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o22a (work@sky130_fd_sc_hd__o22a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o22a.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o22a (work@sky130_fd_sc_hd__o22a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o22a.functional.v, line:35:1, endln:61:10 |vpiTypespec: \_logic_typespec: , line:47:12, endln:47:12 |vpiName:B1 @@ -15903,7 +15903,7 @@ design: (work@sky130_fd_sc_hd__o22a) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o22a.B2), line:40:5, endln:40:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o22a (work@sky130_fd_sc_hd__o22a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o22a.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o22a (work@sky130_fd_sc_hd__o22a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o22a.functional.v, line:35:1, endln:61:10 |vpiTypespec: \_logic_typespec: , line:48:12, endln:48:12 |vpiName:B2 @@ -15912,7 +15912,7 @@ design: (work@sky130_fd_sc_hd__o22a) |vpiPort: \_port: (X), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__o22a (work@sky130_fd_sc_hd__o22a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o22a.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o22a (work@sky130_fd_sc_hd__o22a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o22a.functional.v, line:35:1, endln:61:10 |vpiName:X |vpiDirection:2 |vpiLowConn: @@ -15926,7 +15926,7 @@ design: (work@sky130_fd_sc_hd__o22a) |vpiPort: \_port: (A1), line:37:5, endln:37:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o22a (work@sky130_fd_sc_hd__o22a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o22a.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o22a (work@sky130_fd_sc_hd__o22a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o22a.functional.v, line:35:1, endln:61:10 |vpiName:A1 |vpiDirection:1 |vpiLowConn: @@ -15940,7 +15940,7 @@ design: (work@sky130_fd_sc_hd__o22a) |vpiPort: \_port: (A2), line:38:5, endln:38:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o22a (work@sky130_fd_sc_hd__o22a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o22a.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o22a (work@sky130_fd_sc_hd__o22a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o22a.functional.v, line:35:1, endln:61:10 |vpiName:A2 |vpiDirection:1 |vpiLowConn: @@ -15954,7 +15954,7 @@ design: (work@sky130_fd_sc_hd__o22a) |vpiPort: \_port: (B1), line:39:5, endln:39:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o22a (work@sky130_fd_sc_hd__o22a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o22a.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o22a (work@sky130_fd_sc_hd__o22a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o22a.functional.v, line:35:1, endln:61:10 |vpiName:B1 |vpiDirection:1 |vpiLowConn: @@ -15968,7 +15968,7 @@ design: (work@sky130_fd_sc_hd__o22a) |vpiPort: \_port: (B2), line:40:5, endln:40:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o22a (work@sky130_fd_sc_hd__o22a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o22a.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o22a (work@sky130_fd_sc_hd__o22a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o22a.functional.v, line:35:1, endln:61:10 |vpiName:B2 |vpiDirection:1 |vpiLowConn: @@ -15982,7 +15982,7 @@ design: (work@sky130_fd_sc_hd__o22a) |vpiPrimitive: \_gate: work@or (work@sky130_fd_sc_hd__o22a.or0), line:56:9, endln:56:44 |vpiParent: - \_module: work@sky130_fd_sc_hd__o22a (work@sky130_fd_sc_hd__o22a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o22a.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o22a (work@sky130_fd_sc_hd__o22a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o22a.functional.v, line:35:1, endln:61:10 |vpiDefName:work@or |vpiName:or0 |vpiFullName:work@sky130_fd_sc_hd__o22a.or0 @@ -16031,7 +16031,7 @@ design: (work@sky130_fd_sc_hd__o22a) |vpiPrimitive: \_gate: work@or (work@sky130_fd_sc_hd__o22a.or1), line:57:9, endln:57:44 |vpiParent: - \_module: work@sky130_fd_sc_hd__o22a (work@sky130_fd_sc_hd__o22a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o22a.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o22a (work@sky130_fd_sc_hd__o22a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o22a.functional.v, line:35:1, endln:61:10 |vpiDefName:work@or |vpiName:or1 |vpiFullName:work@sky130_fd_sc_hd__o22a.or1 @@ -16080,7 +16080,7 @@ design: (work@sky130_fd_sc_hd__o22a) |vpiPrimitive: \_gate: work@and (work@sky130_fd_sc_hd__o22a.and0), line:58:9, endln:58:44 |vpiParent: - \_module: work@sky130_fd_sc_hd__o22a (work@sky130_fd_sc_hd__o22a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o22a.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o22a (work@sky130_fd_sc_hd__o22a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o22a.functional.v, line:35:1, endln:61:10 |vpiDefName:work@and |vpiName:and0 |vpiFullName:work@sky130_fd_sc_hd__o22a.and0 @@ -16129,7 +16129,7 @@ design: (work@sky130_fd_sc_hd__o22a) |vpiPrimitive: \_gate: work@buf (work@sky130_fd_sc_hd__o22a.buf0), line:59:9, endln:59:44 |vpiParent: - \_module: work@sky130_fd_sc_hd__o22a (work@sky130_fd_sc_hd__o22a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o22a.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o22a (work@sky130_fd_sc_hd__o22a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o22a.functional.v, line:35:1, endln:61:10 |vpiDefName:work@buf |vpiName:buf0 |vpiFullName:work@sky130_fd_sc_hd__o22a.buf0 @@ -16270,7 +16270,7 @@ design: (work@sky130_fd_sc_hd__dfxtp) |vpiSize:2 |STRING:* ? : ? : - |uhdmallModules: -\_module: work@sky130_fd_sc_hd__dfxtp (work@sky130_fd_sc_hd__dfxtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfxtp.functional.v, line:36:1, endln:54:10 +\_module_inst: work@sky130_fd_sc_hd__dfxtp (work@sky130_fd_sc_hd__dfxtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfxtp.functional.v, line:36:1, endln:54:10 |vpiParent: \_design: (work@sky130_fd_sc_hd__dfxtp) |vpiFullName:work@sky130_fd_sc_hd__dfxtp @@ -16278,32 +16278,32 @@ design: (work@sky130_fd_sc_hd__dfxtp) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__dfxtp.buf_Q), line:48:10, endln:48:15 |vpiParent: - \_module: work@sky130_fd_sc_hd__dfxtp (work@sky130_fd_sc_hd__dfxtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfxtp.functional.v, line:36:1, endln:54:10 + \_module_inst: work@sky130_fd_sc_hd__dfxtp (work@sky130_fd_sc_hd__dfxtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfxtp.functional.v, line:36:1, endln:54:10 |vpiName:buf_Q |vpiFullName:work@sky130_fd_sc_hd__dfxtp.buf_Q |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__dfxtp.Q), line:37:5, endln:37:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__dfxtp (work@sky130_fd_sc_hd__dfxtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfxtp.functional.v, line:36:1, endln:54:10 + \_module_inst: work@sky130_fd_sc_hd__dfxtp (work@sky130_fd_sc_hd__dfxtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfxtp.functional.v, line:36:1, endln:54:10 |vpiName:Q |vpiFullName:work@sky130_fd_sc_hd__dfxtp.Q |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__dfxtp.CLK), line:38:5, endln:38:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__dfxtp (work@sky130_fd_sc_hd__dfxtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfxtp.functional.v, line:36:1, endln:54:10 + \_module_inst: work@sky130_fd_sc_hd__dfxtp (work@sky130_fd_sc_hd__dfxtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfxtp.functional.v, line:36:1, endln:54:10 |vpiName:CLK |vpiFullName:work@sky130_fd_sc_hd__dfxtp.CLK |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__dfxtp.D), line:39:5, endln:39:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__dfxtp (work@sky130_fd_sc_hd__dfxtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfxtp.functional.v, line:36:1, endln:54:10 + \_module_inst: work@sky130_fd_sc_hd__dfxtp (work@sky130_fd_sc_hd__dfxtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfxtp.functional.v, line:36:1, endln:54:10 |vpiName:D |vpiFullName:work@sky130_fd_sc_hd__dfxtp.D |vpiPort: \_port: (Q), line:37:5, endln:37:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__dfxtp (work@sky130_fd_sc_hd__dfxtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfxtp.functional.v, line:36:1, endln:54:10 + \_module_inst: work@sky130_fd_sc_hd__dfxtp (work@sky130_fd_sc_hd__dfxtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfxtp.functional.v, line:36:1, endln:54:10 |vpiName:Q |vpiDirection:2 |vpiLowConn: @@ -16315,7 +16315,7 @@ design: (work@sky130_fd_sc_hd__dfxtp) |vpiPort: \_port: (CLK), line:38:5, endln:38:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__dfxtp (work@sky130_fd_sc_hd__dfxtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfxtp.functional.v, line:36:1, endln:54:10 + \_module_inst: work@sky130_fd_sc_hd__dfxtp (work@sky130_fd_sc_hd__dfxtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfxtp.functional.v, line:36:1, endln:54:10 |vpiName:CLK |vpiDirection:1 |vpiLowConn: @@ -16327,7 +16327,7 @@ design: (work@sky130_fd_sc_hd__dfxtp) |vpiPort: \_port: (D), line:39:5, endln:39:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__dfxtp (work@sky130_fd_sc_hd__dfxtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfxtp.functional.v, line:36:1, endln:54:10 + \_module_inst: work@sky130_fd_sc_hd__dfxtp (work@sky130_fd_sc_hd__dfxtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfxtp.functional.v, line:36:1, endln:54:10 |vpiName:D |vpiDirection:1 |vpiLowConn: @@ -16337,14 +16337,14 @@ design: (work@sky130_fd_sc_hd__dfxtp) |vpiTypedef: \_logic_typespec: , line:45:12, endln:45:12 |uhdmtopModules: -\_module: work@sky130_fd_sc_hd__dfxtp (work@sky130_fd_sc_hd__dfxtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfxtp.functional.v, line:36:1, endln:54:10 +\_module_inst: work@sky130_fd_sc_hd__dfxtp (work@sky130_fd_sc_hd__dfxtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfxtp.functional.v, line:36:1, endln:54:10 |vpiName:work@sky130_fd_sc_hd__dfxtp |vpiDefName:work@sky130_fd_sc_hd__dfxtp |vpiTop:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__dfxtp.buf_Q), line:48:10, endln:48:15 |vpiParent: - \_module: work@sky130_fd_sc_hd__dfxtp (work@sky130_fd_sc_hd__dfxtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfxtp.functional.v, line:36:1, endln:54:10 + \_module_inst: work@sky130_fd_sc_hd__dfxtp (work@sky130_fd_sc_hd__dfxtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfxtp.functional.v, line:36:1, endln:54:10 |vpiTypespec: \_logic_typespec: , line:48:5, endln:48:9 |vpiName:buf_Q @@ -16353,7 +16353,7 @@ design: (work@sky130_fd_sc_hd__dfxtp) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__dfxtp.Q), line:37:5, endln:37:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__dfxtp (work@sky130_fd_sc_hd__dfxtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfxtp.functional.v, line:36:1, endln:54:10 + \_module_inst: work@sky130_fd_sc_hd__dfxtp (work@sky130_fd_sc_hd__dfxtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfxtp.functional.v, line:36:1, endln:54:10 |vpiTypespec: \_logic_typespec: , line:43:12, endln:43:12 |vpiName:Q @@ -16361,7 +16361,7 @@ design: (work@sky130_fd_sc_hd__dfxtp) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__dfxtp.CLK), line:38:5, endln:38:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__dfxtp (work@sky130_fd_sc_hd__dfxtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfxtp.functional.v, line:36:1, endln:54:10 + \_module_inst: work@sky130_fd_sc_hd__dfxtp (work@sky130_fd_sc_hd__dfxtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfxtp.functional.v, line:36:1, endln:54:10 |vpiTypespec: \_logic_typespec: , line:44:12, endln:44:12 |vpiName:CLK @@ -16369,7 +16369,7 @@ design: (work@sky130_fd_sc_hd__dfxtp) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__dfxtp.D), line:39:5, endln:39:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__dfxtp (work@sky130_fd_sc_hd__dfxtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfxtp.functional.v, line:36:1, endln:54:10 + \_module_inst: work@sky130_fd_sc_hd__dfxtp (work@sky130_fd_sc_hd__dfxtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfxtp.functional.v, line:36:1, endln:54:10 |vpiTypespec: \_logic_typespec: , line:45:12, endln:45:12 |vpiName:D @@ -16378,7 +16378,7 @@ design: (work@sky130_fd_sc_hd__dfxtp) |vpiPort: \_port: (Q), line:37:5, endln:37:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__dfxtp (work@sky130_fd_sc_hd__dfxtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfxtp.functional.v, line:36:1, endln:54:10 + \_module_inst: work@sky130_fd_sc_hd__dfxtp (work@sky130_fd_sc_hd__dfxtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfxtp.functional.v, line:36:1, endln:54:10 |vpiName:Q |vpiDirection:2 |vpiLowConn: @@ -16392,7 +16392,7 @@ design: (work@sky130_fd_sc_hd__dfxtp) |vpiPort: \_port: (CLK), line:38:5, endln:38:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__dfxtp (work@sky130_fd_sc_hd__dfxtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfxtp.functional.v, line:36:1, endln:54:10 + \_module_inst: work@sky130_fd_sc_hd__dfxtp (work@sky130_fd_sc_hd__dfxtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfxtp.functional.v, line:36:1, endln:54:10 |vpiName:CLK |vpiDirection:1 |vpiLowConn: @@ -16406,7 +16406,7 @@ design: (work@sky130_fd_sc_hd__dfxtp) |vpiPort: \_port: (D), line:39:5, endln:39:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__dfxtp (work@sky130_fd_sc_hd__dfxtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfxtp.functional.v, line:36:1, endln:54:10 + \_module_inst: work@sky130_fd_sc_hd__dfxtp (work@sky130_fd_sc_hd__dfxtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfxtp.functional.v, line:36:1, endln:54:10 |vpiName:D |vpiDirection:1 |vpiLowConn: @@ -16420,7 +16420,7 @@ design: (work@sky130_fd_sc_hd__dfxtp) |vpiPrimitive: \_udp: work@sky130_fd_sc_hd__udp_dff$P (work@sky130_fd_sc_hd__dfxtp.dff0), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfxtp.functional.v, line:51:5, endln:51:64 |vpiParent: - \_module: work@sky130_fd_sc_hd__dfxtp (work@sky130_fd_sc_hd__dfxtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfxtp.functional.v, line:36:1, endln:54:10 + \_module_inst: work@sky130_fd_sc_hd__dfxtp (work@sky130_fd_sc_hd__dfxtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfxtp.functional.v, line:36:1, endln:54:10 |vpiDefName:work@sky130_fd_sc_hd__udp_dff$P |vpiName:dff0 |vpiFullName:work@sky130_fd_sc_hd__dfxtp.dff0 @@ -16429,7 +16429,7 @@ design: (work@sky130_fd_sc_hd__dfxtp) |vpiPrimitive: \_gate: work@buf (work@sky130_fd_sc_hd__dfxtp.buf0), line:52:44, endln:52:74 |vpiParent: - \_module: work@sky130_fd_sc_hd__dfxtp (work@sky130_fd_sc_hd__dfxtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfxtp.functional.v, line:36:1, endln:54:10 + \_module_inst: work@sky130_fd_sc_hd__dfxtp (work@sky130_fd_sc_hd__dfxtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfxtp.functional.v, line:36:1, endln:54:10 |vpiDefName:work@buf |vpiName:buf0 |vpiFullName:work@sky130_fd_sc_hd__dfxtp.buf0 @@ -16472,7 +16472,7 @@ Processing: -cd cells/cells -DUNIT_DELAY -writepp -parse -nocache -nobuiltin -no design: (work@sky130_fd_sc_hd__a21oi) |vpiName:work@sky130_fd_sc_hd__a21oi |uhdmallModules: -\_module: work@sky130_fd_sc_hd__a21oi (work@sky130_fd_sc_hd__a21oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a21oi.functional.v, line:35:1, endln:57:10 +\_module_inst: work@sky130_fd_sc_hd__a21oi (work@sky130_fd_sc_hd__a21oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a21oi.functional.v, line:35:1, endln:57:10 |vpiParent: \_design: (work@sky130_fd_sc_hd__a21oi) |vpiFullName:work@sky130_fd_sc_hd__a21oi @@ -16480,45 +16480,45 @@ design: (work@sky130_fd_sc_hd__a21oi) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a21oi.and0_out), line:49:10, endln:49:18 |vpiParent: - \_module: work@sky130_fd_sc_hd__a21oi (work@sky130_fd_sc_hd__a21oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a21oi.functional.v, line:35:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__a21oi (work@sky130_fd_sc_hd__a21oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a21oi.functional.v, line:35:1, endln:57:10 |vpiName:and0_out |vpiFullName:work@sky130_fd_sc_hd__a21oi.and0_out |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a21oi.nor0_out_Y), line:50:10, endln:50:20 |vpiParent: - \_module: work@sky130_fd_sc_hd__a21oi (work@sky130_fd_sc_hd__a21oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a21oi.functional.v, line:35:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__a21oi (work@sky130_fd_sc_hd__a21oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a21oi.functional.v, line:35:1, endln:57:10 |vpiName:nor0_out_Y |vpiFullName:work@sky130_fd_sc_hd__a21oi.nor0_out_Y |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a21oi.Y), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__a21oi (work@sky130_fd_sc_hd__a21oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a21oi.functional.v, line:35:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__a21oi (work@sky130_fd_sc_hd__a21oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a21oi.functional.v, line:35:1, endln:57:10 |vpiName:Y |vpiFullName:work@sky130_fd_sc_hd__a21oi.Y |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a21oi.A1), line:37:5, endln:37:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a21oi (work@sky130_fd_sc_hd__a21oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a21oi.functional.v, line:35:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__a21oi (work@sky130_fd_sc_hd__a21oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a21oi.functional.v, line:35:1, endln:57:10 |vpiName:A1 |vpiFullName:work@sky130_fd_sc_hd__a21oi.A1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a21oi.A2), line:38:5, endln:38:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a21oi (work@sky130_fd_sc_hd__a21oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a21oi.functional.v, line:35:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__a21oi (work@sky130_fd_sc_hd__a21oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a21oi.functional.v, line:35:1, endln:57:10 |vpiName:A2 |vpiFullName:work@sky130_fd_sc_hd__a21oi.A2 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a21oi.B1), line:39:5, endln:39:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a21oi (work@sky130_fd_sc_hd__a21oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a21oi.functional.v, line:35:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__a21oi (work@sky130_fd_sc_hd__a21oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a21oi.functional.v, line:35:1, endln:57:10 |vpiName:B1 |vpiFullName:work@sky130_fd_sc_hd__a21oi.B1 |vpiPort: \_port: (Y), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__a21oi (work@sky130_fd_sc_hd__a21oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a21oi.functional.v, line:35:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__a21oi (work@sky130_fd_sc_hd__a21oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a21oi.functional.v, line:35:1, endln:57:10 |vpiName:Y |vpiDirection:2 |vpiLowConn: @@ -16530,7 +16530,7 @@ design: (work@sky130_fd_sc_hd__a21oi) |vpiPort: \_port: (A1), line:37:5, endln:37:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a21oi (work@sky130_fd_sc_hd__a21oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a21oi.functional.v, line:35:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__a21oi (work@sky130_fd_sc_hd__a21oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a21oi.functional.v, line:35:1, endln:57:10 |vpiName:A1 |vpiDirection:1 |vpiLowConn: @@ -16542,7 +16542,7 @@ design: (work@sky130_fd_sc_hd__a21oi) |vpiPort: \_port: (A2), line:38:5, endln:38:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a21oi (work@sky130_fd_sc_hd__a21oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a21oi.functional.v, line:35:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__a21oi (work@sky130_fd_sc_hd__a21oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a21oi.functional.v, line:35:1, endln:57:10 |vpiName:A2 |vpiDirection:1 |vpiLowConn: @@ -16554,7 +16554,7 @@ design: (work@sky130_fd_sc_hd__a21oi) |vpiPort: \_port: (B1), line:39:5, endln:39:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a21oi (work@sky130_fd_sc_hd__a21oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a21oi.functional.v, line:35:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__a21oi (work@sky130_fd_sc_hd__a21oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a21oi.functional.v, line:35:1, endln:57:10 |vpiName:B1 |vpiDirection:1 |vpiLowConn: @@ -16564,14 +16564,14 @@ design: (work@sky130_fd_sc_hd__a21oi) |vpiTypedef: \_logic_typespec: , line:46:12, endln:46:12 |uhdmtopModules: -\_module: work@sky130_fd_sc_hd__a21oi (work@sky130_fd_sc_hd__a21oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a21oi.functional.v, line:35:1, endln:57:10 +\_module_inst: work@sky130_fd_sc_hd__a21oi (work@sky130_fd_sc_hd__a21oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a21oi.functional.v, line:35:1, endln:57:10 |vpiName:work@sky130_fd_sc_hd__a21oi |vpiDefName:work@sky130_fd_sc_hd__a21oi |vpiTop:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a21oi.and0_out), line:49:10, endln:49:18 |vpiParent: - \_module: work@sky130_fd_sc_hd__a21oi (work@sky130_fd_sc_hd__a21oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a21oi.functional.v, line:35:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__a21oi (work@sky130_fd_sc_hd__a21oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a21oi.functional.v, line:35:1, endln:57:10 |vpiTypespec: \_logic_typespec: , line:49:5, endln:49:9 |vpiName:and0_out @@ -16580,7 +16580,7 @@ design: (work@sky130_fd_sc_hd__a21oi) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a21oi.nor0_out_Y), line:50:10, endln:50:20 |vpiParent: - \_module: work@sky130_fd_sc_hd__a21oi (work@sky130_fd_sc_hd__a21oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a21oi.functional.v, line:35:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__a21oi (work@sky130_fd_sc_hd__a21oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a21oi.functional.v, line:35:1, endln:57:10 |vpiTypespec: \_logic_typespec: , line:50:5, endln:50:9 |vpiName:nor0_out_Y @@ -16589,7 +16589,7 @@ design: (work@sky130_fd_sc_hd__a21oi) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a21oi.Y), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__a21oi (work@sky130_fd_sc_hd__a21oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a21oi.functional.v, line:35:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__a21oi (work@sky130_fd_sc_hd__a21oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a21oi.functional.v, line:35:1, endln:57:10 |vpiTypespec: \_logic_typespec: , line:43:12, endln:43:12 |vpiName:Y @@ -16597,7 +16597,7 @@ design: (work@sky130_fd_sc_hd__a21oi) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a21oi.A1), line:37:5, endln:37:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a21oi (work@sky130_fd_sc_hd__a21oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a21oi.functional.v, line:35:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__a21oi (work@sky130_fd_sc_hd__a21oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a21oi.functional.v, line:35:1, endln:57:10 |vpiTypespec: \_logic_typespec: , line:44:12, endln:44:12 |vpiName:A1 @@ -16605,7 +16605,7 @@ design: (work@sky130_fd_sc_hd__a21oi) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a21oi.A2), line:38:5, endln:38:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a21oi (work@sky130_fd_sc_hd__a21oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a21oi.functional.v, line:35:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__a21oi (work@sky130_fd_sc_hd__a21oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a21oi.functional.v, line:35:1, endln:57:10 |vpiTypespec: \_logic_typespec: , line:45:12, endln:45:12 |vpiName:A2 @@ -16613,7 +16613,7 @@ design: (work@sky130_fd_sc_hd__a21oi) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a21oi.B1), line:39:5, endln:39:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a21oi (work@sky130_fd_sc_hd__a21oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a21oi.functional.v, line:35:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__a21oi (work@sky130_fd_sc_hd__a21oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a21oi.functional.v, line:35:1, endln:57:10 |vpiTypespec: \_logic_typespec: , line:46:12, endln:46:12 |vpiName:B1 @@ -16622,7 +16622,7 @@ design: (work@sky130_fd_sc_hd__a21oi) |vpiPort: \_port: (Y), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__a21oi (work@sky130_fd_sc_hd__a21oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a21oi.functional.v, line:35:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__a21oi (work@sky130_fd_sc_hd__a21oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a21oi.functional.v, line:35:1, endln:57:10 |vpiName:Y |vpiDirection:2 |vpiLowConn: @@ -16636,7 +16636,7 @@ design: (work@sky130_fd_sc_hd__a21oi) |vpiPort: \_port: (A1), line:37:5, endln:37:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a21oi (work@sky130_fd_sc_hd__a21oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a21oi.functional.v, line:35:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__a21oi (work@sky130_fd_sc_hd__a21oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a21oi.functional.v, line:35:1, endln:57:10 |vpiName:A1 |vpiDirection:1 |vpiLowConn: @@ -16650,7 +16650,7 @@ design: (work@sky130_fd_sc_hd__a21oi) |vpiPort: \_port: (A2), line:38:5, endln:38:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a21oi (work@sky130_fd_sc_hd__a21oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a21oi.functional.v, line:35:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__a21oi (work@sky130_fd_sc_hd__a21oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a21oi.functional.v, line:35:1, endln:57:10 |vpiName:A2 |vpiDirection:1 |vpiLowConn: @@ -16664,7 +16664,7 @@ design: (work@sky130_fd_sc_hd__a21oi) |vpiPort: \_port: (B1), line:39:5, endln:39:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a21oi (work@sky130_fd_sc_hd__a21oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a21oi.functional.v, line:35:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__a21oi (work@sky130_fd_sc_hd__a21oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a21oi.functional.v, line:35:1, endln:57:10 |vpiName:B1 |vpiDirection:1 |vpiLowConn: @@ -16678,7 +16678,7 @@ design: (work@sky130_fd_sc_hd__a21oi) |vpiPrimitive: \_gate: work@and (work@sky130_fd_sc_hd__a21oi.and0), line:53:9, endln:53:43 |vpiParent: - \_module: work@sky130_fd_sc_hd__a21oi (work@sky130_fd_sc_hd__a21oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a21oi.functional.v, line:35:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__a21oi (work@sky130_fd_sc_hd__a21oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a21oi.functional.v, line:35:1, endln:57:10 |vpiDefName:work@and |vpiName:and0 |vpiFullName:work@sky130_fd_sc_hd__a21oi.and0 @@ -16727,7 +16727,7 @@ design: (work@sky130_fd_sc_hd__a21oi) |vpiPrimitive: \_gate: work@nor (work@sky130_fd_sc_hd__a21oi.nor0), line:54:9, endln:54:43 |vpiParent: - \_module: work@sky130_fd_sc_hd__a21oi (work@sky130_fd_sc_hd__a21oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a21oi.functional.v, line:35:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__a21oi (work@sky130_fd_sc_hd__a21oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a21oi.functional.v, line:35:1, endln:57:10 |vpiDefName:work@nor |vpiName:nor0 |vpiFullName:work@sky130_fd_sc_hd__a21oi.nor0 @@ -16776,7 +16776,7 @@ design: (work@sky130_fd_sc_hd__a21oi) |vpiPrimitive: \_gate: work@buf (work@sky130_fd_sc_hd__a21oi.buf0), line:55:9, endln:55:43 |vpiParent: - \_module: work@sky130_fd_sc_hd__a21oi (work@sky130_fd_sc_hd__a21oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a21oi.functional.v, line:35:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__a21oi (work@sky130_fd_sc_hd__a21oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a21oi.functional.v, line:35:1, endln:57:10 |vpiDefName:work@buf |vpiName:buf0 |vpiFullName:work@sky130_fd_sc_hd__a21oi.buf0 @@ -16819,7 +16819,7 @@ Processing: -cd cells/cells -DUNIT_DELAY -writepp -parse -nocache -nobuiltin -no design: (work@sky130_fd_sc_hd__a22oi) |vpiName:work@sky130_fd_sc_hd__a22oi |uhdmallModules: -\_module: work@sky130_fd_sc_hd__a22oi (work@sky130_fd_sc_hd__a22oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a22oi.functional.v, line:35:1, endln:61:10 +\_module_inst: work@sky130_fd_sc_hd__a22oi (work@sky130_fd_sc_hd__a22oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a22oi.functional.v, line:35:1, endln:61:10 |vpiParent: \_design: (work@sky130_fd_sc_hd__a22oi) |vpiFullName:work@sky130_fd_sc_hd__a22oi @@ -16827,58 +16827,58 @@ design: (work@sky130_fd_sc_hd__a22oi) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a22oi.nand0_out), line:51:10, endln:51:19 |vpiParent: - \_module: work@sky130_fd_sc_hd__a22oi (work@sky130_fd_sc_hd__a22oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a22oi.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__a22oi (work@sky130_fd_sc_hd__a22oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a22oi.functional.v, line:35:1, endln:61:10 |vpiName:nand0_out |vpiFullName:work@sky130_fd_sc_hd__a22oi.nand0_out |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a22oi.nand1_out), line:52:10, endln:52:19 |vpiParent: - \_module: work@sky130_fd_sc_hd__a22oi (work@sky130_fd_sc_hd__a22oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a22oi.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__a22oi (work@sky130_fd_sc_hd__a22oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a22oi.functional.v, line:35:1, endln:61:10 |vpiName:nand1_out |vpiFullName:work@sky130_fd_sc_hd__a22oi.nand1_out |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a22oi.and0_out_Y), line:53:10, endln:53:20 |vpiParent: - \_module: work@sky130_fd_sc_hd__a22oi (work@sky130_fd_sc_hd__a22oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a22oi.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__a22oi (work@sky130_fd_sc_hd__a22oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a22oi.functional.v, line:35:1, endln:61:10 |vpiName:and0_out_Y |vpiFullName:work@sky130_fd_sc_hd__a22oi.and0_out_Y |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a22oi.Y), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__a22oi (work@sky130_fd_sc_hd__a22oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a22oi.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__a22oi (work@sky130_fd_sc_hd__a22oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a22oi.functional.v, line:35:1, endln:61:10 |vpiName:Y |vpiFullName:work@sky130_fd_sc_hd__a22oi.Y |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a22oi.A1), line:37:5, endln:37:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a22oi (work@sky130_fd_sc_hd__a22oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a22oi.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__a22oi (work@sky130_fd_sc_hd__a22oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a22oi.functional.v, line:35:1, endln:61:10 |vpiName:A1 |vpiFullName:work@sky130_fd_sc_hd__a22oi.A1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a22oi.A2), line:38:5, endln:38:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a22oi (work@sky130_fd_sc_hd__a22oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a22oi.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__a22oi (work@sky130_fd_sc_hd__a22oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a22oi.functional.v, line:35:1, endln:61:10 |vpiName:A2 |vpiFullName:work@sky130_fd_sc_hd__a22oi.A2 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a22oi.B1), line:39:5, endln:39:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a22oi (work@sky130_fd_sc_hd__a22oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a22oi.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__a22oi (work@sky130_fd_sc_hd__a22oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a22oi.functional.v, line:35:1, endln:61:10 |vpiName:B1 |vpiFullName:work@sky130_fd_sc_hd__a22oi.B1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a22oi.B2), line:40:5, endln:40:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a22oi (work@sky130_fd_sc_hd__a22oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a22oi.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__a22oi (work@sky130_fd_sc_hd__a22oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a22oi.functional.v, line:35:1, endln:61:10 |vpiName:B2 |vpiFullName:work@sky130_fd_sc_hd__a22oi.B2 |vpiPort: \_port: (Y), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__a22oi (work@sky130_fd_sc_hd__a22oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a22oi.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__a22oi (work@sky130_fd_sc_hd__a22oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a22oi.functional.v, line:35:1, endln:61:10 |vpiName:Y |vpiDirection:2 |vpiLowConn: @@ -16890,7 +16890,7 @@ design: (work@sky130_fd_sc_hd__a22oi) |vpiPort: \_port: (A1), line:37:5, endln:37:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a22oi (work@sky130_fd_sc_hd__a22oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a22oi.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__a22oi (work@sky130_fd_sc_hd__a22oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a22oi.functional.v, line:35:1, endln:61:10 |vpiName:A1 |vpiDirection:1 |vpiLowConn: @@ -16902,7 +16902,7 @@ design: (work@sky130_fd_sc_hd__a22oi) |vpiPort: \_port: (A2), line:38:5, endln:38:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a22oi (work@sky130_fd_sc_hd__a22oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a22oi.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__a22oi (work@sky130_fd_sc_hd__a22oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a22oi.functional.v, line:35:1, endln:61:10 |vpiName:A2 |vpiDirection:1 |vpiLowConn: @@ -16914,7 +16914,7 @@ design: (work@sky130_fd_sc_hd__a22oi) |vpiPort: \_port: (B1), line:39:5, endln:39:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a22oi (work@sky130_fd_sc_hd__a22oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a22oi.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__a22oi (work@sky130_fd_sc_hd__a22oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a22oi.functional.v, line:35:1, endln:61:10 |vpiName:B1 |vpiDirection:1 |vpiLowConn: @@ -16926,7 +16926,7 @@ design: (work@sky130_fd_sc_hd__a22oi) |vpiPort: \_port: (B2), line:40:5, endln:40:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a22oi (work@sky130_fd_sc_hd__a22oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a22oi.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__a22oi (work@sky130_fd_sc_hd__a22oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a22oi.functional.v, line:35:1, endln:61:10 |vpiName:B2 |vpiDirection:1 |vpiLowConn: @@ -16936,14 +16936,14 @@ design: (work@sky130_fd_sc_hd__a22oi) |vpiTypedef: \_logic_typespec: , line:48:12, endln:48:12 |uhdmtopModules: -\_module: work@sky130_fd_sc_hd__a22oi (work@sky130_fd_sc_hd__a22oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a22oi.functional.v, line:35:1, endln:61:10 +\_module_inst: work@sky130_fd_sc_hd__a22oi (work@sky130_fd_sc_hd__a22oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a22oi.functional.v, line:35:1, endln:61:10 |vpiName:work@sky130_fd_sc_hd__a22oi |vpiDefName:work@sky130_fd_sc_hd__a22oi |vpiTop:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a22oi.nand0_out), line:51:10, endln:51:19 |vpiParent: - \_module: work@sky130_fd_sc_hd__a22oi (work@sky130_fd_sc_hd__a22oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a22oi.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__a22oi (work@sky130_fd_sc_hd__a22oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a22oi.functional.v, line:35:1, endln:61:10 |vpiTypespec: \_logic_typespec: , line:51:5, endln:51:9 |vpiName:nand0_out @@ -16952,7 +16952,7 @@ design: (work@sky130_fd_sc_hd__a22oi) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a22oi.nand1_out), line:52:10, endln:52:19 |vpiParent: - \_module: work@sky130_fd_sc_hd__a22oi (work@sky130_fd_sc_hd__a22oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a22oi.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__a22oi (work@sky130_fd_sc_hd__a22oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a22oi.functional.v, line:35:1, endln:61:10 |vpiTypespec: \_logic_typespec: , line:52:5, endln:52:9 |vpiName:nand1_out @@ -16961,7 +16961,7 @@ design: (work@sky130_fd_sc_hd__a22oi) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a22oi.and0_out_Y), line:53:10, endln:53:20 |vpiParent: - \_module: work@sky130_fd_sc_hd__a22oi (work@sky130_fd_sc_hd__a22oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a22oi.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__a22oi (work@sky130_fd_sc_hd__a22oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a22oi.functional.v, line:35:1, endln:61:10 |vpiTypespec: \_logic_typespec: , line:53:5, endln:53:9 |vpiName:and0_out_Y @@ -16970,7 +16970,7 @@ design: (work@sky130_fd_sc_hd__a22oi) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a22oi.Y), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__a22oi (work@sky130_fd_sc_hd__a22oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a22oi.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__a22oi (work@sky130_fd_sc_hd__a22oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a22oi.functional.v, line:35:1, endln:61:10 |vpiTypespec: \_logic_typespec: , line:44:12, endln:44:12 |vpiName:Y @@ -16978,7 +16978,7 @@ design: (work@sky130_fd_sc_hd__a22oi) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a22oi.A1), line:37:5, endln:37:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a22oi (work@sky130_fd_sc_hd__a22oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a22oi.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__a22oi (work@sky130_fd_sc_hd__a22oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a22oi.functional.v, line:35:1, endln:61:10 |vpiTypespec: \_logic_typespec: , line:45:12, endln:45:12 |vpiName:A1 @@ -16986,7 +16986,7 @@ design: (work@sky130_fd_sc_hd__a22oi) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a22oi.A2), line:38:5, endln:38:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a22oi (work@sky130_fd_sc_hd__a22oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a22oi.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__a22oi (work@sky130_fd_sc_hd__a22oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a22oi.functional.v, line:35:1, endln:61:10 |vpiTypespec: \_logic_typespec: , line:46:12, endln:46:12 |vpiName:A2 @@ -16994,7 +16994,7 @@ design: (work@sky130_fd_sc_hd__a22oi) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a22oi.B1), line:39:5, endln:39:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a22oi (work@sky130_fd_sc_hd__a22oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a22oi.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__a22oi (work@sky130_fd_sc_hd__a22oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a22oi.functional.v, line:35:1, endln:61:10 |vpiTypespec: \_logic_typespec: , line:47:12, endln:47:12 |vpiName:B1 @@ -17002,7 +17002,7 @@ design: (work@sky130_fd_sc_hd__a22oi) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a22oi.B2), line:40:5, endln:40:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a22oi (work@sky130_fd_sc_hd__a22oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a22oi.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__a22oi (work@sky130_fd_sc_hd__a22oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a22oi.functional.v, line:35:1, endln:61:10 |vpiTypespec: \_logic_typespec: , line:48:12, endln:48:12 |vpiName:B2 @@ -17011,7 +17011,7 @@ design: (work@sky130_fd_sc_hd__a22oi) |vpiPort: \_port: (Y), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__a22oi (work@sky130_fd_sc_hd__a22oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a22oi.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__a22oi (work@sky130_fd_sc_hd__a22oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a22oi.functional.v, line:35:1, endln:61:10 |vpiName:Y |vpiDirection:2 |vpiLowConn: @@ -17025,7 +17025,7 @@ design: (work@sky130_fd_sc_hd__a22oi) |vpiPort: \_port: (A1), line:37:5, endln:37:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a22oi (work@sky130_fd_sc_hd__a22oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a22oi.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__a22oi (work@sky130_fd_sc_hd__a22oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a22oi.functional.v, line:35:1, endln:61:10 |vpiName:A1 |vpiDirection:1 |vpiLowConn: @@ -17039,7 +17039,7 @@ design: (work@sky130_fd_sc_hd__a22oi) |vpiPort: \_port: (A2), line:38:5, endln:38:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a22oi (work@sky130_fd_sc_hd__a22oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a22oi.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__a22oi (work@sky130_fd_sc_hd__a22oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a22oi.functional.v, line:35:1, endln:61:10 |vpiName:A2 |vpiDirection:1 |vpiLowConn: @@ -17053,7 +17053,7 @@ design: (work@sky130_fd_sc_hd__a22oi) |vpiPort: \_port: (B1), line:39:5, endln:39:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a22oi (work@sky130_fd_sc_hd__a22oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a22oi.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__a22oi (work@sky130_fd_sc_hd__a22oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a22oi.functional.v, line:35:1, endln:61:10 |vpiName:B1 |vpiDirection:1 |vpiLowConn: @@ -17067,7 +17067,7 @@ design: (work@sky130_fd_sc_hd__a22oi) |vpiPort: \_port: (B2), line:40:5, endln:40:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a22oi (work@sky130_fd_sc_hd__a22oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a22oi.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__a22oi (work@sky130_fd_sc_hd__a22oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a22oi.functional.v, line:35:1, endln:61:10 |vpiName:B2 |vpiDirection:1 |vpiLowConn: @@ -17081,7 +17081,7 @@ design: (work@sky130_fd_sc_hd__a22oi) |vpiPrimitive: \_gate: work@nand (work@sky130_fd_sc_hd__a22oi.nand0), line:56:10, endln:56:50 |vpiParent: - \_module: work@sky130_fd_sc_hd__a22oi (work@sky130_fd_sc_hd__a22oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a22oi.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__a22oi (work@sky130_fd_sc_hd__a22oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a22oi.functional.v, line:35:1, endln:61:10 |vpiDefName:work@nand |vpiName:nand0 |vpiFullName:work@sky130_fd_sc_hd__a22oi.nand0 @@ -17130,7 +17130,7 @@ design: (work@sky130_fd_sc_hd__a22oi) |vpiPrimitive: \_gate: work@nand (work@sky130_fd_sc_hd__a22oi.nand1), line:57:10, endln:57:50 |vpiParent: - \_module: work@sky130_fd_sc_hd__a22oi (work@sky130_fd_sc_hd__a22oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a22oi.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__a22oi (work@sky130_fd_sc_hd__a22oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a22oi.functional.v, line:35:1, endln:61:10 |vpiDefName:work@nand |vpiName:nand1 |vpiFullName:work@sky130_fd_sc_hd__a22oi.nand1 @@ -17179,7 +17179,7 @@ design: (work@sky130_fd_sc_hd__a22oi) |vpiPrimitive: \_gate: work@and (work@sky130_fd_sc_hd__a22oi.and0), line:58:10, endln:58:50 |vpiParent: - \_module: work@sky130_fd_sc_hd__a22oi (work@sky130_fd_sc_hd__a22oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a22oi.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__a22oi (work@sky130_fd_sc_hd__a22oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a22oi.functional.v, line:35:1, endln:61:10 |vpiDefName:work@and |vpiName:and0 |vpiFullName:work@sky130_fd_sc_hd__a22oi.and0 @@ -17228,7 +17228,7 @@ design: (work@sky130_fd_sc_hd__a22oi) |vpiPrimitive: \_gate: work@buf (work@sky130_fd_sc_hd__a22oi.buf0), line:59:10, endln:59:50 |vpiParent: - \_module: work@sky130_fd_sc_hd__a22oi (work@sky130_fd_sc_hd__a22oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a22oi.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__a22oi (work@sky130_fd_sc_hd__a22oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a22oi.functional.v, line:35:1, endln:61:10 |vpiDefName:work@buf |vpiName:buf0 |vpiFullName:work@sky130_fd_sc_hd__a22oi.buf0 @@ -17271,7 +17271,7 @@ Processing: -cd cells/cells -DUNIT_DELAY -writepp -parse -nocache -nobuiltin -no design: (work@sky130_fd_sc_hd__lpflow_clkinvkapwr) |vpiName:work@sky130_fd_sc_hd__lpflow_clkinvkapwr |uhdmallModules: -\_module: work@sky130_fd_sc_hd__lpflow_clkinvkapwr (work@sky130_fd_sc_hd__lpflow_clkinvkapwr), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_clkinvkapwr.functional.v, line:33:1, endln:49:10 +\_module_inst: work@sky130_fd_sc_hd__lpflow_clkinvkapwr (work@sky130_fd_sc_hd__lpflow_clkinvkapwr), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_clkinvkapwr.functional.v, line:33:1, endln:49:10 |vpiParent: \_design: (work@sky130_fd_sc_hd__lpflow_clkinvkapwr) |vpiFullName:work@sky130_fd_sc_hd__lpflow_clkinvkapwr @@ -17279,26 +17279,26 @@ design: (work@sky130_fd_sc_hd__lpflow_clkinvkapwr) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__lpflow_clkinvkapwr.not0_out_Y), line:43:10, endln:43:20 |vpiParent: - \_module: work@sky130_fd_sc_hd__lpflow_clkinvkapwr (work@sky130_fd_sc_hd__lpflow_clkinvkapwr), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_clkinvkapwr.functional.v, line:33:1, endln:49:10 + \_module_inst: work@sky130_fd_sc_hd__lpflow_clkinvkapwr (work@sky130_fd_sc_hd__lpflow_clkinvkapwr), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_clkinvkapwr.functional.v, line:33:1, endln:49:10 |vpiName:not0_out_Y |vpiFullName:work@sky130_fd_sc_hd__lpflow_clkinvkapwr.not0_out_Y |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__lpflow_clkinvkapwr.Y), line:34:5, endln:34:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__lpflow_clkinvkapwr (work@sky130_fd_sc_hd__lpflow_clkinvkapwr), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_clkinvkapwr.functional.v, line:33:1, endln:49:10 + \_module_inst: work@sky130_fd_sc_hd__lpflow_clkinvkapwr (work@sky130_fd_sc_hd__lpflow_clkinvkapwr), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_clkinvkapwr.functional.v, line:33:1, endln:49:10 |vpiName:Y |vpiFullName:work@sky130_fd_sc_hd__lpflow_clkinvkapwr.Y |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__lpflow_clkinvkapwr.A), line:35:5, endln:35:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__lpflow_clkinvkapwr (work@sky130_fd_sc_hd__lpflow_clkinvkapwr), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_clkinvkapwr.functional.v, line:33:1, endln:49:10 + \_module_inst: work@sky130_fd_sc_hd__lpflow_clkinvkapwr (work@sky130_fd_sc_hd__lpflow_clkinvkapwr), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_clkinvkapwr.functional.v, line:33:1, endln:49:10 |vpiName:A |vpiFullName:work@sky130_fd_sc_hd__lpflow_clkinvkapwr.A |vpiPort: \_port: (Y), line:34:5, endln:34:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__lpflow_clkinvkapwr (work@sky130_fd_sc_hd__lpflow_clkinvkapwr), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_clkinvkapwr.functional.v, line:33:1, endln:49:10 + \_module_inst: work@sky130_fd_sc_hd__lpflow_clkinvkapwr (work@sky130_fd_sc_hd__lpflow_clkinvkapwr), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_clkinvkapwr.functional.v, line:33:1, endln:49:10 |vpiName:Y |vpiDirection:2 |vpiLowConn: @@ -17310,7 +17310,7 @@ design: (work@sky130_fd_sc_hd__lpflow_clkinvkapwr) |vpiPort: \_port: (A), line:35:5, endln:35:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__lpflow_clkinvkapwr (work@sky130_fd_sc_hd__lpflow_clkinvkapwr), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_clkinvkapwr.functional.v, line:33:1, endln:49:10 + \_module_inst: work@sky130_fd_sc_hd__lpflow_clkinvkapwr (work@sky130_fd_sc_hd__lpflow_clkinvkapwr), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_clkinvkapwr.functional.v, line:33:1, endln:49:10 |vpiName:A |vpiDirection:1 |vpiLowConn: @@ -17320,14 +17320,14 @@ design: (work@sky130_fd_sc_hd__lpflow_clkinvkapwr) |vpiTypedef: \_logic_typespec: , line:40:12, endln:40:12 |uhdmtopModules: -\_module: work@sky130_fd_sc_hd__lpflow_clkinvkapwr (work@sky130_fd_sc_hd__lpflow_clkinvkapwr), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_clkinvkapwr.functional.v, line:33:1, endln:49:10 +\_module_inst: work@sky130_fd_sc_hd__lpflow_clkinvkapwr (work@sky130_fd_sc_hd__lpflow_clkinvkapwr), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_clkinvkapwr.functional.v, line:33:1, endln:49:10 |vpiName:work@sky130_fd_sc_hd__lpflow_clkinvkapwr |vpiDefName:work@sky130_fd_sc_hd__lpflow_clkinvkapwr |vpiTop:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__lpflow_clkinvkapwr.not0_out_Y), line:43:10, endln:43:20 |vpiParent: - \_module: work@sky130_fd_sc_hd__lpflow_clkinvkapwr (work@sky130_fd_sc_hd__lpflow_clkinvkapwr), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_clkinvkapwr.functional.v, line:33:1, endln:49:10 + \_module_inst: work@sky130_fd_sc_hd__lpflow_clkinvkapwr (work@sky130_fd_sc_hd__lpflow_clkinvkapwr), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_clkinvkapwr.functional.v, line:33:1, endln:49:10 |vpiTypespec: \_logic_typespec: , line:43:5, endln:43:9 |vpiName:not0_out_Y @@ -17336,7 +17336,7 @@ design: (work@sky130_fd_sc_hd__lpflow_clkinvkapwr) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__lpflow_clkinvkapwr.Y), line:34:5, endln:34:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__lpflow_clkinvkapwr (work@sky130_fd_sc_hd__lpflow_clkinvkapwr), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_clkinvkapwr.functional.v, line:33:1, endln:49:10 + \_module_inst: work@sky130_fd_sc_hd__lpflow_clkinvkapwr (work@sky130_fd_sc_hd__lpflow_clkinvkapwr), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_clkinvkapwr.functional.v, line:33:1, endln:49:10 |vpiTypespec: \_logic_typespec: , line:39:12, endln:39:12 |vpiName:Y @@ -17344,7 +17344,7 @@ design: (work@sky130_fd_sc_hd__lpflow_clkinvkapwr) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__lpflow_clkinvkapwr.A), line:35:5, endln:35:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__lpflow_clkinvkapwr (work@sky130_fd_sc_hd__lpflow_clkinvkapwr), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_clkinvkapwr.functional.v, line:33:1, endln:49:10 + \_module_inst: work@sky130_fd_sc_hd__lpflow_clkinvkapwr (work@sky130_fd_sc_hd__lpflow_clkinvkapwr), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_clkinvkapwr.functional.v, line:33:1, endln:49:10 |vpiTypespec: \_logic_typespec: , line:40:12, endln:40:12 |vpiName:A @@ -17353,7 +17353,7 @@ design: (work@sky130_fd_sc_hd__lpflow_clkinvkapwr) |vpiPort: \_port: (Y), line:34:5, endln:34:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__lpflow_clkinvkapwr (work@sky130_fd_sc_hd__lpflow_clkinvkapwr), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_clkinvkapwr.functional.v, line:33:1, endln:49:10 + \_module_inst: work@sky130_fd_sc_hd__lpflow_clkinvkapwr (work@sky130_fd_sc_hd__lpflow_clkinvkapwr), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_clkinvkapwr.functional.v, line:33:1, endln:49:10 |vpiName:Y |vpiDirection:2 |vpiLowConn: @@ -17367,7 +17367,7 @@ design: (work@sky130_fd_sc_hd__lpflow_clkinvkapwr) |vpiPort: \_port: (A), line:35:5, endln:35:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__lpflow_clkinvkapwr (work@sky130_fd_sc_hd__lpflow_clkinvkapwr), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_clkinvkapwr.functional.v, line:33:1, endln:49:10 + \_module_inst: work@sky130_fd_sc_hd__lpflow_clkinvkapwr (work@sky130_fd_sc_hd__lpflow_clkinvkapwr), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_clkinvkapwr.functional.v, line:33:1, endln:49:10 |vpiName:A |vpiDirection:1 |vpiLowConn: @@ -17381,7 +17381,7 @@ design: (work@sky130_fd_sc_hd__lpflow_clkinvkapwr) |vpiPrimitive: \_gate: work@not (work@sky130_fd_sc_hd__lpflow_clkinvkapwr.not0), line:46:9, endln:46:43 |vpiParent: - \_module: work@sky130_fd_sc_hd__lpflow_clkinvkapwr (work@sky130_fd_sc_hd__lpflow_clkinvkapwr), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_clkinvkapwr.functional.v, line:33:1, endln:49:10 + \_module_inst: work@sky130_fd_sc_hd__lpflow_clkinvkapwr (work@sky130_fd_sc_hd__lpflow_clkinvkapwr), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_clkinvkapwr.functional.v, line:33:1, endln:49:10 |vpiDefName:work@not |vpiName:not0 |vpiFullName:work@sky130_fd_sc_hd__lpflow_clkinvkapwr.not0 @@ -17416,7 +17416,7 @@ design: (work@sky130_fd_sc_hd__lpflow_clkinvkapwr) |vpiPrimitive: \_gate: work@buf (work@sky130_fd_sc_hd__lpflow_clkinvkapwr.buf0), line:47:9, endln:47:43 |vpiParent: - \_module: work@sky130_fd_sc_hd__lpflow_clkinvkapwr (work@sky130_fd_sc_hd__lpflow_clkinvkapwr), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_clkinvkapwr.functional.v, line:33:1, endln:49:10 + \_module_inst: work@sky130_fd_sc_hd__lpflow_clkinvkapwr (work@sky130_fd_sc_hd__lpflow_clkinvkapwr), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_clkinvkapwr.functional.v, line:33:1, endln:49:10 |vpiDefName:work@buf |vpiName:buf0 |vpiFullName:work@sky130_fd_sc_hd__lpflow_clkinvkapwr.buf0 @@ -17459,13 +17459,13 @@ Processing: -cd cells/cells -DUNIT_DELAY -writepp -parse -nocache -nobuiltin -no design: (work@sky130_fd_sc_hd__decap) |vpiName:work@sky130_fd_sc_hd__decap |uhdmallModules: -\_module: work@sky130_fd_sc_hd__decap (work@sky130_fd_sc_hd__decap), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__decap.functional.v, line:33:1, endln:35:10 +\_module_inst: work@sky130_fd_sc_hd__decap (work@sky130_fd_sc_hd__decap), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__decap.functional.v, line:33:1, endln:35:10 |vpiParent: \_design: (work@sky130_fd_sc_hd__decap) |vpiFullName:work@sky130_fd_sc_hd__decap |vpiDefName:work@sky130_fd_sc_hd__decap |uhdmtopModules: -\_module: work@sky130_fd_sc_hd__decap (work@sky130_fd_sc_hd__decap), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__decap.functional.v, line:33:1, endln:35:10 +\_module_inst: work@sky130_fd_sc_hd__decap (work@sky130_fd_sc_hd__decap), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__decap.functional.v, line:33:1, endln:35:10 |vpiName:work@sky130_fd_sc_hd__decap |vpiDefName:work@sky130_fd_sc_hd__decap |vpiTop:1 @@ -17481,7 +17481,7 @@ Processing: -cd cells/cells -DUNIT_DELAY -writepp -parse -nocache -nobuiltin -no design: (work@sky130_fd_sc_hd__and3) |vpiName:work@sky130_fd_sc_hd__and3 |uhdmallModules: -\_module: work@sky130_fd_sc_hd__and3 (work@sky130_fd_sc_hd__and3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and3.functional.v, line:33:1, endln:53:10 +\_module_inst: work@sky130_fd_sc_hd__and3 (work@sky130_fd_sc_hd__and3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and3.functional.v, line:33:1, endln:53:10 |vpiParent: \_design: (work@sky130_fd_sc_hd__and3) |vpiFullName:work@sky130_fd_sc_hd__and3 @@ -17489,38 +17489,38 @@ design: (work@sky130_fd_sc_hd__and3) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__and3.and0_out_X), line:47:10, endln:47:20 |vpiParent: - \_module: work@sky130_fd_sc_hd__and3 (work@sky130_fd_sc_hd__and3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and3.functional.v, line:33:1, endln:53:10 + \_module_inst: work@sky130_fd_sc_hd__and3 (work@sky130_fd_sc_hd__and3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and3.functional.v, line:33:1, endln:53:10 |vpiName:and0_out_X |vpiFullName:work@sky130_fd_sc_hd__and3.and0_out_X |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__and3.X), line:34:5, endln:34:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__and3 (work@sky130_fd_sc_hd__and3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and3.functional.v, line:33:1, endln:53:10 + \_module_inst: work@sky130_fd_sc_hd__and3 (work@sky130_fd_sc_hd__and3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and3.functional.v, line:33:1, endln:53:10 |vpiName:X |vpiFullName:work@sky130_fd_sc_hd__and3.X |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__and3.A), line:35:5, endln:35:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__and3 (work@sky130_fd_sc_hd__and3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and3.functional.v, line:33:1, endln:53:10 + \_module_inst: work@sky130_fd_sc_hd__and3 (work@sky130_fd_sc_hd__and3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and3.functional.v, line:33:1, endln:53:10 |vpiName:A |vpiFullName:work@sky130_fd_sc_hd__and3.A |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__and3.B), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__and3 (work@sky130_fd_sc_hd__and3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and3.functional.v, line:33:1, endln:53:10 + \_module_inst: work@sky130_fd_sc_hd__and3 (work@sky130_fd_sc_hd__and3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and3.functional.v, line:33:1, endln:53:10 |vpiName:B |vpiFullName:work@sky130_fd_sc_hd__and3.B |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__and3.C), line:37:5, endln:37:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__and3 (work@sky130_fd_sc_hd__and3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and3.functional.v, line:33:1, endln:53:10 + \_module_inst: work@sky130_fd_sc_hd__and3 (work@sky130_fd_sc_hd__and3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and3.functional.v, line:33:1, endln:53:10 |vpiName:C |vpiFullName:work@sky130_fd_sc_hd__and3.C |vpiPort: \_port: (X), line:34:5, endln:34:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__and3 (work@sky130_fd_sc_hd__and3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and3.functional.v, line:33:1, endln:53:10 + \_module_inst: work@sky130_fd_sc_hd__and3 (work@sky130_fd_sc_hd__and3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and3.functional.v, line:33:1, endln:53:10 |vpiName:X |vpiDirection:2 |vpiLowConn: @@ -17532,7 +17532,7 @@ design: (work@sky130_fd_sc_hd__and3) |vpiPort: \_port: (A), line:35:5, endln:35:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__and3 (work@sky130_fd_sc_hd__and3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and3.functional.v, line:33:1, endln:53:10 + \_module_inst: work@sky130_fd_sc_hd__and3 (work@sky130_fd_sc_hd__and3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and3.functional.v, line:33:1, endln:53:10 |vpiName:A |vpiDirection:1 |vpiLowConn: @@ -17544,7 +17544,7 @@ design: (work@sky130_fd_sc_hd__and3) |vpiPort: \_port: (B), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__and3 (work@sky130_fd_sc_hd__and3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and3.functional.v, line:33:1, endln:53:10 + \_module_inst: work@sky130_fd_sc_hd__and3 (work@sky130_fd_sc_hd__and3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and3.functional.v, line:33:1, endln:53:10 |vpiName:B |vpiDirection:1 |vpiLowConn: @@ -17556,7 +17556,7 @@ design: (work@sky130_fd_sc_hd__and3) |vpiPort: \_port: (C), line:37:5, endln:37:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__and3 (work@sky130_fd_sc_hd__and3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and3.functional.v, line:33:1, endln:53:10 + \_module_inst: work@sky130_fd_sc_hd__and3 (work@sky130_fd_sc_hd__and3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and3.functional.v, line:33:1, endln:53:10 |vpiName:C |vpiDirection:1 |vpiLowConn: @@ -17566,14 +17566,14 @@ design: (work@sky130_fd_sc_hd__and3) |vpiTypedef: \_logic_typespec: , line:44:12, endln:44:12 |uhdmtopModules: -\_module: work@sky130_fd_sc_hd__and3 (work@sky130_fd_sc_hd__and3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and3.functional.v, line:33:1, endln:53:10 +\_module_inst: work@sky130_fd_sc_hd__and3 (work@sky130_fd_sc_hd__and3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and3.functional.v, line:33:1, endln:53:10 |vpiName:work@sky130_fd_sc_hd__and3 |vpiDefName:work@sky130_fd_sc_hd__and3 |vpiTop:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__and3.and0_out_X), line:47:10, endln:47:20 |vpiParent: - \_module: work@sky130_fd_sc_hd__and3 (work@sky130_fd_sc_hd__and3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and3.functional.v, line:33:1, endln:53:10 + \_module_inst: work@sky130_fd_sc_hd__and3 (work@sky130_fd_sc_hd__and3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and3.functional.v, line:33:1, endln:53:10 |vpiTypespec: \_logic_typespec: , line:47:5, endln:47:9 |vpiName:and0_out_X @@ -17582,7 +17582,7 @@ design: (work@sky130_fd_sc_hd__and3) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__and3.X), line:34:5, endln:34:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__and3 (work@sky130_fd_sc_hd__and3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and3.functional.v, line:33:1, endln:53:10 + \_module_inst: work@sky130_fd_sc_hd__and3 (work@sky130_fd_sc_hd__and3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and3.functional.v, line:33:1, endln:53:10 |vpiTypespec: \_logic_typespec: , line:41:12, endln:41:12 |vpiName:X @@ -17590,7 +17590,7 @@ design: (work@sky130_fd_sc_hd__and3) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__and3.A), line:35:5, endln:35:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__and3 (work@sky130_fd_sc_hd__and3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and3.functional.v, line:33:1, endln:53:10 + \_module_inst: work@sky130_fd_sc_hd__and3 (work@sky130_fd_sc_hd__and3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and3.functional.v, line:33:1, endln:53:10 |vpiTypespec: \_logic_typespec: , line:42:12, endln:42:12 |vpiName:A @@ -17598,7 +17598,7 @@ design: (work@sky130_fd_sc_hd__and3) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__and3.B), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__and3 (work@sky130_fd_sc_hd__and3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and3.functional.v, line:33:1, endln:53:10 + \_module_inst: work@sky130_fd_sc_hd__and3 (work@sky130_fd_sc_hd__and3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and3.functional.v, line:33:1, endln:53:10 |vpiTypespec: \_logic_typespec: , line:43:12, endln:43:12 |vpiName:B @@ -17606,7 +17606,7 @@ design: (work@sky130_fd_sc_hd__and3) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__and3.C), line:37:5, endln:37:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__and3 (work@sky130_fd_sc_hd__and3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and3.functional.v, line:33:1, endln:53:10 + \_module_inst: work@sky130_fd_sc_hd__and3 (work@sky130_fd_sc_hd__and3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and3.functional.v, line:33:1, endln:53:10 |vpiTypespec: \_logic_typespec: , line:44:12, endln:44:12 |vpiName:C @@ -17615,7 +17615,7 @@ design: (work@sky130_fd_sc_hd__and3) |vpiPort: \_port: (X), line:34:5, endln:34:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__and3 (work@sky130_fd_sc_hd__and3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and3.functional.v, line:33:1, endln:53:10 + \_module_inst: work@sky130_fd_sc_hd__and3 (work@sky130_fd_sc_hd__and3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and3.functional.v, line:33:1, endln:53:10 |vpiName:X |vpiDirection:2 |vpiLowConn: @@ -17629,7 +17629,7 @@ design: (work@sky130_fd_sc_hd__and3) |vpiPort: \_port: (A), line:35:5, endln:35:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__and3 (work@sky130_fd_sc_hd__and3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and3.functional.v, line:33:1, endln:53:10 + \_module_inst: work@sky130_fd_sc_hd__and3 (work@sky130_fd_sc_hd__and3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and3.functional.v, line:33:1, endln:53:10 |vpiName:A |vpiDirection:1 |vpiLowConn: @@ -17643,7 +17643,7 @@ design: (work@sky130_fd_sc_hd__and3) |vpiPort: \_port: (B), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__and3 (work@sky130_fd_sc_hd__and3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and3.functional.v, line:33:1, endln:53:10 + \_module_inst: work@sky130_fd_sc_hd__and3 (work@sky130_fd_sc_hd__and3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and3.functional.v, line:33:1, endln:53:10 |vpiName:B |vpiDirection:1 |vpiLowConn: @@ -17657,7 +17657,7 @@ design: (work@sky130_fd_sc_hd__and3) |vpiPort: \_port: (C), line:37:5, endln:37:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__and3 (work@sky130_fd_sc_hd__and3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and3.functional.v, line:33:1, endln:53:10 + \_module_inst: work@sky130_fd_sc_hd__and3 (work@sky130_fd_sc_hd__and3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and3.functional.v, line:33:1, endln:53:10 |vpiName:C |vpiDirection:1 |vpiLowConn: @@ -17671,7 +17671,7 @@ design: (work@sky130_fd_sc_hd__and3) |vpiPrimitive: \_gate: work@and (work@sky130_fd_sc_hd__and3.and0), line:50:9, endln:50:43 |vpiParent: - \_module: work@sky130_fd_sc_hd__and3 (work@sky130_fd_sc_hd__and3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and3.functional.v, line:33:1, endln:53:10 + \_module_inst: work@sky130_fd_sc_hd__and3 (work@sky130_fd_sc_hd__and3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and3.functional.v, line:33:1, endln:53:10 |vpiDefName:work@and |vpiName:and0 |vpiFullName:work@sky130_fd_sc_hd__and3.and0 @@ -17734,7 +17734,7 @@ design: (work@sky130_fd_sc_hd__and3) |vpiPrimitive: \_gate: work@buf (work@sky130_fd_sc_hd__and3.buf0), line:51:9, endln:51:43 |vpiParent: - \_module: work@sky130_fd_sc_hd__and3 (work@sky130_fd_sc_hd__and3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and3.functional.v, line:33:1, endln:53:10 + \_module_inst: work@sky130_fd_sc_hd__and3 (work@sky130_fd_sc_hd__and3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and3.functional.v, line:33:1, endln:53:10 |vpiDefName:work@buf |vpiName:buf0 |vpiFullName:work@sky130_fd_sc_hd__and3.buf0 @@ -17777,7 +17777,7 @@ Processing: -cd cells/cells -DUNIT_DELAY -writepp -parse -nocache -nobuiltin -no design: (work@sky130_fd_sc_hd__o211ai) |vpiName:work@sky130_fd_sc_hd__o211ai |uhdmallModules: -\_module: work@sky130_fd_sc_hd__o211ai (work@sky130_fd_sc_hd__o211ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o211ai.functional.v, line:35:1, endln:59:10 +\_module_inst: work@sky130_fd_sc_hd__o211ai (work@sky130_fd_sc_hd__o211ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o211ai.functional.v, line:35:1, endln:59:10 |vpiParent: \_design: (work@sky130_fd_sc_hd__o211ai) |vpiFullName:work@sky130_fd_sc_hd__o211ai @@ -17785,51 +17785,51 @@ design: (work@sky130_fd_sc_hd__o211ai) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o211ai.or0_out), line:51:10, endln:51:17 |vpiParent: - \_module: work@sky130_fd_sc_hd__o211ai (work@sky130_fd_sc_hd__o211ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o211ai.functional.v, line:35:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__o211ai (work@sky130_fd_sc_hd__o211ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o211ai.functional.v, line:35:1, endln:59:10 |vpiName:or0_out |vpiFullName:work@sky130_fd_sc_hd__o211ai.or0_out |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o211ai.nand0_out_Y), line:52:10, endln:52:21 |vpiParent: - \_module: work@sky130_fd_sc_hd__o211ai (work@sky130_fd_sc_hd__o211ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o211ai.functional.v, line:35:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__o211ai (work@sky130_fd_sc_hd__o211ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o211ai.functional.v, line:35:1, endln:59:10 |vpiName:nand0_out_Y |vpiFullName:work@sky130_fd_sc_hd__o211ai.nand0_out_Y |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o211ai.Y), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__o211ai (work@sky130_fd_sc_hd__o211ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o211ai.functional.v, line:35:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__o211ai (work@sky130_fd_sc_hd__o211ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o211ai.functional.v, line:35:1, endln:59:10 |vpiName:Y |vpiFullName:work@sky130_fd_sc_hd__o211ai.Y |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o211ai.A1), line:37:5, endln:37:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o211ai (work@sky130_fd_sc_hd__o211ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o211ai.functional.v, line:35:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__o211ai (work@sky130_fd_sc_hd__o211ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o211ai.functional.v, line:35:1, endln:59:10 |vpiName:A1 |vpiFullName:work@sky130_fd_sc_hd__o211ai.A1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o211ai.A2), line:38:5, endln:38:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o211ai (work@sky130_fd_sc_hd__o211ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o211ai.functional.v, line:35:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__o211ai (work@sky130_fd_sc_hd__o211ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o211ai.functional.v, line:35:1, endln:59:10 |vpiName:A2 |vpiFullName:work@sky130_fd_sc_hd__o211ai.A2 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o211ai.B1), line:39:5, endln:39:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o211ai (work@sky130_fd_sc_hd__o211ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o211ai.functional.v, line:35:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__o211ai (work@sky130_fd_sc_hd__o211ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o211ai.functional.v, line:35:1, endln:59:10 |vpiName:B1 |vpiFullName:work@sky130_fd_sc_hd__o211ai.B1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o211ai.C1), line:40:5, endln:40:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o211ai (work@sky130_fd_sc_hd__o211ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o211ai.functional.v, line:35:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__o211ai (work@sky130_fd_sc_hd__o211ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o211ai.functional.v, line:35:1, endln:59:10 |vpiName:C1 |vpiFullName:work@sky130_fd_sc_hd__o211ai.C1 |vpiPort: \_port: (Y), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__o211ai (work@sky130_fd_sc_hd__o211ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o211ai.functional.v, line:35:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__o211ai (work@sky130_fd_sc_hd__o211ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o211ai.functional.v, line:35:1, endln:59:10 |vpiName:Y |vpiDirection:2 |vpiLowConn: @@ -17841,7 +17841,7 @@ design: (work@sky130_fd_sc_hd__o211ai) |vpiPort: \_port: (A1), line:37:5, endln:37:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o211ai (work@sky130_fd_sc_hd__o211ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o211ai.functional.v, line:35:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__o211ai (work@sky130_fd_sc_hd__o211ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o211ai.functional.v, line:35:1, endln:59:10 |vpiName:A1 |vpiDirection:1 |vpiLowConn: @@ -17853,7 +17853,7 @@ design: (work@sky130_fd_sc_hd__o211ai) |vpiPort: \_port: (A2), line:38:5, endln:38:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o211ai (work@sky130_fd_sc_hd__o211ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o211ai.functional.v, line:35:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__o211ai (work@sky130_fd_sc_hd__o211ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o211ai.functional.v, line:35:1, endln:59:10 |vpiName:A2 |vpiDirection:1 |vpiLowConn: @@ -17865,7 +17865,7 @@ design: (work@sky130_fd_sc_hd__o211ai) |vpiPort: \_port: (B1), line:39:5, endln:39:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o211ai (work@sky130_fd_sc_hd__o211ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o211ai.functional.v, line:35:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__o211ai (work@sky130_fd_sc_hd__o211ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o211ai.functional.v, line:35:1, endln:59:10 |vpiName:B1 |vpiDirection:1 |vpiLowConn: @@ -17877,7 +17877,7 @@ design: (work@sky130_fd_sc_hd__o211ai) |vpiPort: \_port: (C1), line:40:5, endln:40:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o211ai (work@sky130_fd_sc_hd__o211ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o211ai.functional.v, line:35:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__o211ai (work@sky130_fd_sc_hd__o211ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o211ai.functional.v, line:35:1, endln:59:10 |vpiName:C1 |vpiDirection:1 |vpiLowConn: @@ -17887,14 +17887,14 @@ design: (work@sky130_fd_sc_hd__o211ai) |vpiTypedef: \_logic_typespec: , line:48:12, endln:48:12 |uhdmtopModules: -\_module: work@sky130_fd_sc_hd__o211ai (work@sky130_fd_sc_hd__o211ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o211ai.functional.v, line:35:1, endln:59:10 +\_module_inst: work@sky130_fd_sc_hd__o211ai (work@sky130_fd_sc_hd__o211ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o211ai.functional.v, line:35:1, endln:59:10 |vpiName:work@sky130_fd_sc_hd__o211ai |vpiDefName:work@sky130_fd_sc_hd__o211ai |vpiTop:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o211ai.or0_out), line:51:10, endln:51:17 |vpiParent: - \_module: work@sky130_fd_sc_hd__o211ai (work@sky130_fd_sc_hd__o211ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o211ai.functional.v, line:35:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__o211ai (work@sky130_fd_sc_hd__o211ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o211ai.functional.v, line:35:1, endln:59:10 |vpiTypespec: \_logic_typespec: , line:51:5, endln:51:9 |vpiName:or0_out @@ -17903,7 +17903,7 @@ design: (work@sky130_fd_sc_hd__o211ai) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o211ai.nand0_out_Y), line:52:10, endln:52:21 |vpiParent: - \_module: work@sky130_fd_sc_hd__o211ai (work@sky130_fd_sc_hd__o211ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o211ai.functional.v, line:35:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__o211ai (work@sky130_fd_sc_hd__o211ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o211ai.functional.v, line:35:1, endln:59:10 |vpiTypespec: \_logic_typespec: , line:52:5, endln:52:9 |vpiName:nand0_out_Y @@ -17912,7 +17912,7 @@ design: (work@sky130_fd_sc_hd__o211ai) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o211ai.Y), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__o211ai (work@sky130_fd_sc_hd__o211ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o211ai.functional.v, line:35:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__o211ai (work@sky130_fd_sc_hd__o211ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o211ai.functional.v, line:35:1, endln:59:10 |vpiTypespec: \_logic_typespec: , line:44:12, endln:44:12 |vpiName:Y @@ -17920,7 +17920,7 @@ design: (work@sky130_fd_sc_hd__o211ai) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o211ai.A1), line:37:5, endln:37:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o211ai (work@sky130_fd_sc_hd__o211ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o211ai.functional.v, line:35:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__o211ai (work@sky130_fd_sc_hd__o211ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o211ai.functional.v, line:35:1, endln:59:10 |vpiTypespec: \_logic_typespec: , line:45:12, endln:45:12 |vpiName:A1 @@ -17928,7 +17928,7 @@ design: (work@sky130_fd_sc_hd__o211ai) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o211ai.A2), line:38:5, endln:38:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o211ai (work@sky130_fd_sc_hd__o211ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o211ai.functional.v, line:35:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__o211ai (work@sky130_fd_sc_hd__o211ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o211ai.functional.v, line:35:1, endln:59:10 |vpiTypespec: \_logic_typespec: , line:46:12, endln:46:12 |vpiName:A2 @@ -17936,7 +17936,7 @@ design: (work@sky130_fd_sc_hd__o211ai) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o211ai.B1), line:39:5, endln:39:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o211ai (work@sky130_fd_sc_hd__o211ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o211ai.functional.v, line:35:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__o211ai (work@sky130_fd_sc_hd__o211ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o211ai.functional.v, line:35:1, endln:59:10 |vpiTypespec: \_logic_typespec: , line:47:12, endln:47:12 |vpiName:B1 @@ -17944,7 +17944,7 @@ design: (work@sky130_fd_sc_hd__o211ai) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o211ai.C1), line:40:5, endln:40:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o211ai (work@sky130_fd_sc_hd__o211ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o211ai.functional.v, line:35:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__o211ai (work@sky130_fd_sc_hd__o211ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o211ai.functional.v, line:35:1, endln:59:10 |vpiTypespec: \_logic_typespec: , line:48:12, endln:48:12 |vpiName:C1 @@ -17953,7 +17953,7 @@ design: (work@sky130_fd_sc_hd__o211ai) |vpiPort: \_port: (Y), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__o211ai (work@sky130_fd_sc_hd__o211ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o211ai.functional.v, line:35:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__o211ai (work@sky130_fd_sc_hd__o211ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o211ai.functional.v, line:35:1, endln:59:10 |vpiName:Y |vpiDirection:2 |vpiLowConn: @@ -17967,7 +17967,7 @@ design: (work@sky130_fd_sc_hd__o211ai) |vpiPort: \_port: (A1), line:37:5, endln:37:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o211ai (work@sky130_fd_sc_hd__o211ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o211ai.functional.v, line:35:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__o211ai (work@sky130_fd_sc_hd__o211ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o211ai.functional.v, line:35:1, endln:59:10 |vpiName:A1 |vpiDirection:1 |vpiLowConn: @@ -17981,7 +17981,7 @@ design: (work@sky130_fd_sc_hd__o211ai) |vpiPort: \_port: (A2), line:38:5, endln:38:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o211ai (work@sky130_fd_sc_hd__o211ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o211ai.functional.v, line:35:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__o211ai (work@sky130_fd_sc_hd__o211ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o211ai.functional.v, line:35:1, endln:59:10 |vpiName:A2 |vpiDirection:1 |vpiLowConn: @@ -17995,7 +17995,7 @@ design: (work@sky130_fd_sc_hd__o211ai) |vpiPort: \_port: (B1), line:39:5, endln:39:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o211ai (work@sky130_fd_sc_hd__o211ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o211ai.functional.v, line:35:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__o211ai (work@sky130_fd_sc_hd__o211ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o211ai.functional.v, line:35:1, endln:59:10 |vpiName:B1 |vpiDirection:1 |vpiLowConn: @@ -18009,7 +18009,7 @@ design: (work@sky130_fd_sc_hd__o211ai) |vpiPort: \_port: (C1), line:40:5, endln:40:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o211ai (work@sky130_fd_sc_hd__o211ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o211ai.functional.v, line:35:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__o211ai (work@sky130_fd_sc_hd__o211ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o211ai.functional.v, line:35:1, endln:59:10 |vpiName:C1 |vpiDirection:1 |vpiLowConn: @@ -18023,7 +18023,7 @@ design: (work@sky130_fd_sc_hd__o211ai) |vpiPrimitive: \_gate: work@or (work@sky130_fd_sc_hd__o211ai.or0), line:55:10, endln:55:46 |vpiParent: - \_module: work@sky130_fd_sc_hd__o211ai (work@sky130_fd_sc_hd__o211ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o211ai.functional.v, line:35:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__o211ai (work@sky130_fd_sc_hd__o211ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o211ai.functional.v, line:35:1, endln:59:10 |vpiDefName:work@or |vpiName:or0 |vpiFullName:work@sky130_fd_sc_hd__o211ai.or0 @@ -18072,7 +18072,7 @@ design: (work@sky130_fd_sc_hd__o211ai) |vpiPrimitive: \_gate: work@nand (work@sky130_fd_sc_hd__o211ai.nand0), line:56:10, endln:56:46 |vpiParent: - \_module: work@sky130_fd_sc_hd__o211ai (work@sky130_fd_sc_hd__o211ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o211ai.functional.v, line:35:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__o211ai (work@sky130_fd_sc_hd__o211ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o211ai.functional.v, line:35:1, endln:59:10 |vpiDefName:work@nand |vpiName:nand0 |vpiFullName:work@sky130_fd_sc_hd__o211ai.nand0 @@ -18135,7 +18135,7 @@ design: (work@sky130_fd_sc_hd__o211ai) |vpiPrimitive: \_gate: work@buf (work@sky130_fd_sc_hd__o211ai.buf0), line:57:10, endln:57:46 |vpiParent: - \_module: work@sky130_fd_sc_hd__o211ai (work@sky130_fd_sc_hd__o211ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o211ai.functional.v, line:35:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__o211ai (work@sky130_fd_sc_hd__o211ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o211ai.functional.v, line:35:1, endln:59:10 |vpiDefName:work@buf |vpiName:buf0 |vpiFullName:work@sky130_fd_sc_hd__o211ai.buf0 @@ -18178,7 +18178,7 @@ Processing: -cd cells/cells -DUNIT_DELAY -writepp -parse -nocache -nobuiltin -no design: (work@sky130_fd_sc_hd__clkdlybuf4s18) |vpiName:work@sky130_fd_sc_hd__clkdlybuf4s18 |uhdmallModules: -\_module: work@sky130_fd_sc_hd__clkdlybuf4s18 (work@sky130_fd_sc_hd__clkdlybuf4s18), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__clkdlybuf4s18.functional.v, line:34:1, endln:50:10 +\_module_inst: work@sky130_fd_sc_hd__clkdlybuf4s18 (work@sky130_fd_sc_hd__clkdlybuf4s18), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__clkdlybuf4s18.functional.v, line:34:1, endln:50:10 |vpiParent: \_design: (work@sky130_fd_sc_hd__clkdlybuf4s18) |vpiFullName:work@sky130_fd_sc_hd__clkdlybuf4s18 @@ -18186,26 +18186,26 @@ design: (work@sky130_fd_sc_hd__clkdlybuf4s18) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__clkdlybuf4s18.buf0_out_X), line:44:10, endln:44:20 |vpiParent: - \_module: work@sky130_fd_sc_hd__clkdlybuf4s18 (work@sky130_fd_sc_hd__clkdlybuf4s18), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__clkdlybuf4s18.functional.v, line:34:1, endln:50:10 + \_module_inst: work@sky130_fd_sc_hd__clkdlybuf4s18 (work@sky130_fd_sc_hd__clkdlybuf4s18), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__clkdlybuf4s18.functional.v, line:34:1, endln:50:10 |vpiName:buf0_out_X |vpiFullName:work@sky130_fd_sc_hd__clkdlybuf4s18.buf0_out_X |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__clkdlybuf4s18.X), line:35:5, endln:35:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__clkdlybuf4s18 (work@sky130_fd_sc_hd__clkdlybuf4s18), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__clkdlybuf4s18.functional.v, line:34:1, endln:50:10 + \_module_inst: work@sky130_fd_sc_hd__clkdlybuf4s18 (work@sky130_fd_sc_hd__clkdlybuf4s18), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__clkdlybuf4s18.functional.v, line:34:1, endln:50:10 |vpiName:X |vpiFullName:work@sky130_fd_sc_hd__clkdlybuf4s18.X |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__clkdlybuf4s18.A), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__clkdlybuf4s18 (work@sky130_fd_sc_hd__clkdlybuf4s18), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__clkdlybuf4s18.functional.v, line:34:1, endln:50:10 + \_module_inst: work@sky130_fd_sc_hd__clkdlybuf4s18 (work@sky130_fd_sc_hd__clkdlybuf4s18), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__clkdlybuf4s18.functional.v, line:34:1, endln:50:10 |vpiName:A |vpiFullName:work@sky130_fd_sc_hd__clkdlybuf4s18.A |vpiPort: \_port: (X), line:35:5, endln:35:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__clkdlybuf4s18 (work@sky130_fd_sc_hd__clkdlybuf4s18), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__clkdlybuf4s18.functional.v, line:34:1, endln:50:10 + \_module_inst: work@sky130_fd_sc_hd__clkdlybuf4s18 (work@sky130_fd_sc_hd__clkdlybuf4s18), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__clkdlybuf4s18.functional.v, line:34:1, endln:50:10 |vpiName:X |vpiDirection:2 |vpiLowConn: @@ -18217,7 +18217,7 @@ design: (work@sky130_fd_sc_hd__clkdlybuf4s18) |vpiPort: \_port: (A), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__clkdlybuf4s18 (work@sky130_fd_sc_hd__clkdlybuf4s18), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__clkdlybuf4s18.functional.v, line:34:1, endln:50:10 + \_module_inst: work@sky130_fd_sc_hd__clkdlybuf4s18 (work@sky130_fd_sc_hd__clkdlybuf4s18), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__clkdlybuf4s18.functional.v, line:34:1, endln:50:10 |vpiName:A |vpiDirection:1 |vpiLowConn: @@ -18227,14 +18227,14 @@ design: (work@sky130_fd_sc_hd__clkdlybuf4s18) |vpiTypedef: \_logic_typespec: , line:41:12, endln:41:12 |uhdmtopModules: -\_module: work@sky130_fd_sc_hd__clkdlybuf4s18 (work@sky130_fd_sc_hd__clkdlybuf4s18), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__clkdlybuf4s18.functional.v, line:34:1, endln:50:10 +\_module_inst: work@sky130_fd_sc_hd__clkdlybuf4s18 (work@sky130_fd_sc_hd__clkdlybuf4s18), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__clkdlybuf4s18.functional.v, line:34:1, endln:50:10 |vpiName:work@sky130_fd_sc_hd__clkdlybuf4s18 |vpiDefName:work@sky130_fd_sc_hd__clkdlybuf4s18 |vpiTop:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__clkdlybuf4s18.buf0_out_X), line:44:10, endln:44:20 |vpiParent: - \_module: work@sky130_fd_sc_hd__clkdlybuf4s18 (work@sky130_fd_sc_hd__clkdlybuf4s18), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__clkdlybuf4s18.functional.v, line:34:1, endln:50:10 + \_module_inst: work@sky130_fd_sc_hd__clkdlybuf4s18 (work@sky130_fd_sc_hd__clkdlybuf4s18), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__clkdlybuf4s18.functional.v, line:34:1, endln:50:10 |vpiTypespec: \_logic_typespec: , line:44:5, endln:44:9 |vpiName:buf0_out_X @@ -18243,7 +18243,7 @@ design: (work@sky130_fd_sc_hd__clkdlybuf4s18) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__clkdlybuf4s18.X), line:35:5, endln:35:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__clkdlybuf4s18 (work@sky130_fd_sc_hd__clkdlybuf4s18), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__clkdlybuf4s18.functional.v, line:34:1, endln:50:10 + \_module_inst: work@sky130_fd_sc_hd__clkdlybuf4s18 (work@sky130_fd_sc_hd__clkdlybuf4s18), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__clkdlybuf4s18.functional.v, line:34:1, endln:50:10 |vpiTypespec: \_logic_typespec: , line:40:12, endln:40:12 |vpiName:X @@ -18251,7 +18251,7 @@ design: (work@sky130_fd_sc_hd__clkdlybuf4s18) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__clkdlybuf4s18.A), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__clkdlybuf4s18 (work@sky130_fd_sc_hd__clkdlybuf4s18), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__clkdlybuf4s18.functional.v, line:34:1, endln:50:10 + \_module_inst: work@sky130_fd_sc_hd__clkdlybuf4s18 (work@sky130_fd_sc_hd__clkdlybuf4s18), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__clkdlybuf4s18.functional.v, line:34:1, endln:50:10 |vpiTypespec: \_logic_typespec: , line:41:12, endln:41:12 |vpiName:A @@ -18260,7 +18260,7 @@ design: (work@sky130_fd_sc_hd__clkdlybuf4s18) |vpiPort: \_port: (X), line:35:5, endln:35:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__clkdlybuf4s18 (work@sky130_fd_sc_hd__clkdlybuf4s18), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__clkdlybuf4s18.functional.v, line:34:1, endln:50:10 + \_module_inst: work@sky130_fd_sc_hd__clkdlybuf4s18 (work@sky130_fd_sc_hd__clkdlybuf4s18), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__clkdlybuf4s18.functional.v, line:34:1, endln:50:10 |vpiName:X |vpiDirection:2 |vpiLowConn: @@ -18274,7 +18274,7 @@ design: (work@sky130_fd_sc_hd__clkdlybuf4s18) |vpiPort: \_port: (A), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__clkdlybuf4s18 (work@sky130_fd_sc_hd__clkdlybuf4s18), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__clkdlybuf4s18.functional.v, line:34:1, endln:50:10 + \_module_inst: work@sky130_fd_sc_hd__clkdlybuf4s18 (work@sky130_fd_sc_hd__clkdlybuf4s18), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__clkdlybuf4s18.functional.v, line:34:1, endln:50:10 |vpiName:A |vpiDirection:1 |vpiLowConn: @@ -18288,7 +18288,7 @@ design: (work@sky130_fd_sc_hd__clkdlybuf4s18) |vpiPrimitive: \_gate: work@buf (work@sky130_fd_sc_hd__clkdlybuf4s18.buf0), line:47:9, endln:47:43 |vpiParent: - \_module: work@sky130_fd_sc_hd__clkdlybuf4s18 (work@sky130_fd_sc_hd__clkdlybuf4s18), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__clkdlybuf4s18.functional.v, line:34:1, endln:50:10 + \_module_inst: work@sky130_fd_sc_hd__clkdlybuf4s18 (work@sky130_fd_sc_hd__clkdlybuf4s18), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__clkdlybuf4s18.functional.v, line:34:1, endln:50:10 |vpiDefName:work@buf |vpiName:buf0 |vpiFullName:work@sky130_fd_sc_hd__clkdlybuf4s18.buf0 @@ -18323,7 +18323,7 @@ design: (work@sky130_fd_sc_hd__clkdlybuf4s18) |vpiPrimitive: \_gate: work@buf (work@sky130_fd_sc_hd__clkdlybuf4s18.buf1), line:48:9, endln:48:43 |vpiParent: - \_module: work@sky130_fd_sc_hd__clkdlybuf4s18 (work@sky130_fd_sc_hd__clkdlybuf4s18), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__clkdlybuf4s18.functional.v, line:34:1, endln:50:10 + \_module_inst: work@sky130_fd_sc_hd__clkdlybuf4s18 (work@sky130_fd_sc_hd__clkdlybuf4s18), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__clkdlybuf4s18.functional.v, line:34:1, endln:50:10 |vpiDefName:work@buf |vpiName:buf1 |vpiFullName:work@sky130_fd_sc_hd__clkdlybuf4s18.buf1 @@ -18366,7 +18366,7 @@ Processing: -cd cells/cells -DUNIT_DELAY -writepp -parse -nocache -nobuiltin -no design: (work@sky130_fd_sc_hd__or2b) |vpiName:work@sky130_fd_sc_hd__or2b |uhdmallModules: -\_module: work@sky130_fd_sc_hd__or2b (work@sky130_fd_sc_hd__or2b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or2b.functional.v, line:33:1, endln:53:10 +\_module_inst: work@sky130_fd_sc_hd__or2b (work@sky130_fd_sc_hd__or2b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or2b.functional.v, line:33:1, endln:53:10 |vpiParent: \_design: (work@sky130_fd_sc_hd__or2b) |vpiFullName:work@sky130_fd_sc_hd__or2b @@ -18374,39 +18374,39 @@ design: (work@sky130_fd_sc_hd__or2b) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__or2b.not0_out), line:45:10, endln:45:18 |vpiParent: - \_module: work@sky130_fd_sc_hd__or2b (work@sky130_fd_sc_hd__or2b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or2b.functional.v, line:33:1, endln:53:10 + \_module_inst: work@sky130_fd_sc_hd__or2b (work@sky130_fd_sc_hd__or2b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or2b.functional.v, line:33:1, endln:53:10 |vpiName:not0_out |vpiFullName:work@sky130_fd_sc_hd__or2b.not0_out |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__or2b.or0_out_X), line:46:10, endln:46:19 |vpiParent: - \_module: work@sky130_fd_sc_hd__or2b (work@sky130_fd_sc_hd__or2b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or2b.functional.v, line:33:1, endln:53:10 + \_module_inst: work@sky130_fd_sc_hd__or2b (work@sky130_fd_sc_hd__or2b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or2b.functional.v, line:33:1, endln:53:10 |vpiName:or0_out_X |vpiFullName:work@sky130_fd_sc_hd__or2b.or0_out_X |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__or2b.X), line:34:5, endln:34:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__or2b (work@sky130_fd_sc_hd__or2b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or2b.functional.v, line:33:1, endln:53:10 + \_module_inst: work@sky130_fd_sc_hd__or2b (work@sky130_fd_sc_hd__or2b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or2b.functional.v, line:33:1, endln:53:10 |vpiName:X |vpiFullName:work@sky130_fd_sc_hd__or2b.X |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__or2b.A), line:35:5, endln:35:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__or2b (work@sky130_fd_sc_hd__or2b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or2b.functional.v, line:33:1, endln:53:10 + \_module_inst: work@sky130_fd_sc_hd__or2b (work@sky130_fd_sc_hd__or2b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or2b.functional.v, line:33:1, endln:53:10 |vpiName:A |vpiFullName:work@sky130_fd_sc_hd__or2b.A |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__or2b.B_N), line:36:5, endln:36:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__or2b (work@sky130_fd_sc_hd__or2b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or2b.functional.v, line:33:1, endln:53:10 + \_module_inst: work@sky130_fd_sc_hd__or2b (work@sky130_fd_sc_hd__or2b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or2b.functional.v, line:33:1, endln:53:10 |vpiName:B_N |vpiFullName:work@sky130_fd_sc_hd__or2b.B_N |vpiPort: \_port: (X), line:34:5, endln:34:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__or2b (work@sky130_fd_sc_hd__or2b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or2b.functional.v, line:33:1, endln:53:10 + \_module_inst: work@sky130_fd_sc_hd__or2b (work@sky130_fd_sc_hd__or2b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or2b.functional.v, line:33:1, endln:53:10 |vpiName:X |vpiDirection:2 |vpiLowConn: @@ -18418,7 +18418,7 @@ design: (work@sky130_fd_sc_hd__or2b) |vpiPort: \_port: (A), line:35:5, endln:35:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__or2b (work@sky130_fd_sc_hd__or2b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or2b.functional.v, line:33:1, endln:53:10 + \_module_inst: work@sky130_fd_sc_hd__or2b (work@sky130_fd_sc_hd__or2b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or2b.functional.v, line:33:1, endln:53:10 |vpiName:A |vpiDirection:1 |vpiLowConn: @@ -18430,7 +18430,7 @@ design: (work@sky130_fd_sc_hd__or2b) |vpiPort: \_port: (B_N), line:36:5, endln:36:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__or2b (work@sky130_fd_sc_hd__or2b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or2b.functional.v, line:33:1, endln:53:10 + \_module_inst: work@sky130_fd_sc_hd__or2b (work@sky130_fd_sc_hd__or2b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or2b.functional.v, line:33:1, endln:53:10 |vpiName:B_N |vpiDirection:1 |vpiLowConn: @@ -18440,14 +18440,14 @@ design: (work@sky130_fd_sc_hd__or2b) |vpiTypedef: \_logic_typespec: , line:42:12, endln:42:12 |uhdmtopModules: -\_module: work@sky130_fd_sc_hd__or2b (work@sky130_fd_sc_hd__or2b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or2b.functional.v, line:33:1, endln:53:10 +\_module_inst: work@sky130_fd_sc_hd__or2b (work@sky130_fd_sc_hd__or2b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or2b.functional.v, line:33:1, endln:53:10 |vpiName:work@sky130_fd_sc_hd__or2b |vpiDefName:work@sky130_fd_sc_hd__or2b |vpiTop:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__or2b.not0_out), line:45:10, endln:45:18 |vpiParent: - \_module: work@sky130_fd_sc_hd__or2b (work@sky130_fd_sc_hd__or2b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or2b.functional.v, line:33:1, endln:53:10 + \_module_inst: work@sky130_fd_sc_hd__or2b (work@sky130_fd_sc_hd__or2b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or2b.functional.v, line:33:1, endln:53:10 |vpiTypespec: \_logic_typespec: , line:45:5, endln:45:9 |vpiName:not0_out @@ -18456,7 +18456,7 @@ design: (work@sky130_fd_sc_hd__or2b) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__or2b.or0_out_X), line:46:10, endln:46:19 |vpiParent: - \_module: work@sky130_fd_sc_hd__or2b (work@sky130_fd_sc_hd__or2b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or2b.functional.v, line:33:1, endln:53:10 + \_module_inst: work@sky130_fd_sc_hd__or2b (work@sky130_fd_sc_hd__or2b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or2b.functional.v, line:33:1, endln:53:10 |vpiTypespec: \_logic_typespec: , line:46:5, endln:46:9 |vpiName:or0_out_X @@ -18465,7 +18465,7 @@ design: (work@sky130_fd_sc_hd__or2b) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__or2b.X), line:34:5, endln:34:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__or2b (work@sky130_fd_sc_hd__or2b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or2b.functional.v, line:33:1, endln:53:10 + \_module_inst: work@sky130_fd_sc_hd__or2b (work@sky130_fd_sc_hd__or2b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or2b.functional.v, line:33:1, endln:53:10 |vpiTypespec: \_logic_typespec: , line:40:12, endln:40:12 |vpiName:X @@ -18473,7 +18473,7 @@ design: (work@sky130_fd_sc_hd__or2b) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__or2b.A), line:35:5, endln:35:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__or2b (work@sky130_fd_sc_hd__or2b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or2b.functional.v, line:33:1, endln:53:10 + \_module_inst: work@sky130_fd_sc_hd__or2b (work@sky130_fd_sc_hd__or2b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or2b.functional.v, line:33:1, endln:53:10 |vpiTypespec: \_logic_typespec: , line:41:12, endln:41:12 |vpiName:A @@ -18481,7 +18481,7 @@ design: (work@sky130_fd_sc_hd__or2b) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__or2b.B_N), line:36:5, endln:36:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__or2b (work@sky130_fd_sc_hd__or2b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or2b.functional.v, line:33:1, endln:53:10 + \_module_inst: work@sky130_fd_sc_hd__or2b (work@sky130_fd_sc_hd__or2b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or2b.functional.v, line:33:1, endln:53:10 |vpiTypespec: \_logic_typespec: , line:42:12, endln:42:12 |vpiName:B_N @@ -18490,7 +18490,7 @@ design: (work@sky130_fd_sc_hd__or2b) |vpiPort: \_port: (X), line:34:5, endln:34:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__or2b (work@sky130_fd_sc_hd__or2b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or2b.functional.v, line:33:1, endln:53:10 + \_module_inst: work@sky130_fd_sc_hd__or2b (work@sky130_fd_sc_hd__or2b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or2b.functional.v, line:33:1, endln:53:10 |vpiName:X |vpiDirection:2 |vpiLowConn: @@ -18504,7 +18504,7 @@ design: (work@sky130_fd_sc_hd__or2b) |vpiPort: \_port: (A), line:35:5, endln:35:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__or2b (work@sky130_fd_sc_hd__or2b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or2b.functional.v, line:33:1, endln:53:10 + \_module_inst: work@sky130_fd_sc_hd__or2b (work@sky130_fd_sc_hd__or2b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or2b.functional.v, line:33:1, endln:53:10 |vpiName:A |vpiDirection:1 |vpiLowConn: @@ -18518,7 +18518,7 @@ design: (work@sky130_fd_sc_hd__or2b) |vpiPort: \_port: (B_N), line:36:5, endln:36:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__or2b (work@sky130_fd_sc_hd__or2b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or2b.functional.v, line:33:1, endln:53:10 + \_module_inst: work@sky130_fd_sc_hd__or2b (work@sky130_fd_sc_hd__or2b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or2b.functional.v, line:33:1, endln:53:10 |vpiName:B_N |vpiDirection:1 |vpiLowConn: @@ -18532,7 +18532,7 @@ design: (work@sky130_fd_sc_hd__or2b) |vpiPrimitive: \_gate: work@not (work@sky130_fd_sc_hd__or2b.not0), line:49:9, endln:49:42 |vpiParent: - \_module: work@sky130_fd_sc_hd__or2b (work@sky130_fd_sc_hd__or2b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or2b.functional.v, line:33:1, endln:53:10 + \_module_inst: work@sky130_fd_sc_hd__or2b (work@sky130_fd_sc_hd__or2b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or2b.functional.v, line:33:1, endln:53:10 |vpiDefName:work@not |vpiName:not0 |vpiFullName:work@sky130_fd_sc_hd__or2b.not0 @@ -18567,7 +18567,7 @@ design: (work@sky130_fd_sc_hd__or2b) |vpiPrimitive: \_gate: work@or (work@sky130_fd_sc_hd__or2b.or0), line:50:9, endln:50:42 |vpiParent: - \_module: work@sky130_fd_sc_hd__or2b (work@sky130_fd_sc_hd__or2b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or2b.functional.v, line:33:1, endln:53:10 + \_module_inst: work@sky130_fd_sc_hd__or2b (work@sky130_fd_sc_hd__or2b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or2b.functional.v, line:33:1, endln:53:10 |vpiDefName:work@or |vpiName:or0 |vpiFullName:work@sky130_fd_sc_hd__or2b.or0 @@ -18616,7 +18616,7 @@ design: (work@sky130_fd_sc_hd__or2b) |vpiPrimitive: \_gate: work@buf (work@sky130_fd_sc_hd__or2b.buf0), line:51:9, endln:51:42 |vpiParent: - \_module: work@sky130_fd_sc_hd__or2b (work@sky130_fd_sc_hd__or2b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or2b.functional.v, line:33:1, endln:53:10 + \_module_inst: work@sky130_fd_sc_hd__or2b (work@sky130_fd_sc_hd__or2b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or2b.functional.v, line:33:1, endln:53:10 |vpiDefName:work@buf |vpiName:buf0 |vpiFullName:work@sky130_fd_sc_hd__or2b.buf0 @@ -18873,7 +18873,7 @@ design: (work@sky130_fd_sc_hd__sdfrbp) |vpiSize:3 |STRING:? 1 1 : 1 |uhdmallModules: -\_module: work@sky130_fd_sc_hd__sdfrbp (work@sky130_fd_sc_hd__sdfrbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfrbp.functional.v, line:38:1, endln:69:10 +\_module_inst: work@sky130_fd_sc_hd__sdfrbp (work@sky130_fd_sc_hd__sdfrbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfrbp.functional.v, line:38:1, endln:69:10 |vpiParent: \_design: (work@sky130_fd_sc_hd__sdfrbp) |vpiFullName:work@sky130_fd_sc_hd__sdfrbp @@ -18881,70 +18881,70 @@ design: (work@sky130_fd_sc_hd__sdfrbp) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__sdfrbp.buf_Q), line:58:10, endln:58:15 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfrbp (work@sky130_fd_sc_hd__sdfrbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfrbp.functional.v, line:38:1, endln:69:10 + \_module_inst: work@sky130_fd_sc_hd__sdfrbp (work@sky130_fd_sc_hd__sdfrbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfrbp.functional.v, line:38:1, endln:69:10 |vpiName:buf_Q |vpiFullName:work@sky130_fd_sc_hd__sdfrbp.buf_Q |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__sdfrbp.RESET), line:59:10, endln:59:15 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfrbp (work@sky130_fd_sc_hd__sdfrbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfrbp.functional.v, line:38:1, endln:69:10 + \_module_inst: work@sky130_fd_sc_hd__sdfrbp (work@sky130_fd_sc_hd__sdfrbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfrbp.functional.v, line:38:1, endln:69:10 |vpiName:RESET |vpiFullName:work@sky130_fd_sc_hd__sdfrbp.RESET |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__sdfrbp.mux_out), line:60:10, endln:60:17 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfrbp (work@sky130_fd_sc_hd__sdfrbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfrbp.functional.v, line:38:1, endln:69:10 + \_module_inst: work@sky130_fd_sc_hd__sdfrbp (work@sky130_fd_sc_hd__sdfrbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfrbp.functional.v, line:38:1, endln:69:10 |vpiName:mux_out |vpiFullName:work@sky130_fd_sc_hd__sdfrbp.mux_out |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__sdfrbp.Q), line:39:5, endln:39:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfrbp (work@sky130_fd_sc_hd__sdfrbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfrbp.functional.v, line:38:1, endln:69:10 + \_module_inst: work@sky130_fd_sc_hd__sdfrbp (work@sky130_fd_sc_hd__sdfrbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfrbp.functional.v, line:38:1, endln:69:10 |vpiName:Q |vpiFullName:work@sky130_fd_sc_hd__sdfrbp.Q |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__sdfrbp.Q_N), line:40:5, endln:40:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfrbp (work@sky130_fd_sc_hd__sdfrbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfrbp.functional.v, line:38:1, endln:69:10 + \_module_inst: work@sky130_fd_sc_hd__sdfrbp (work@sky130_fd_sc_hd__sdfrbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfrbp.functional.v, line:38:1, endln:69:10 |vpiName:Q_N |vpiFullName:work@sky130_fd_sc_hd__sdfrbp.Q_N |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__sdfrbp.CLK), line:41:5, endln:41:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfrbp (work@sky130_fd_sc_hd__sdfrbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfrbp.functional.v, line:38:1, endln:69:10 + \_module_inst: work@sky130_fd_sc_hd__sdfrbp (work@sky130_fd_sc_hd__sdfrbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfrbp.functional.v, line:38:1, endln:69:10 |vpiName:CLK |vpiFullName:work@sky130_fd_sc_hd__sdfrbp.CLK |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__sdfrbp.D), line:42:5, endln:42:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfrbp (work@sky130_fd_sc_hd__sdfrbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfrbp.functional.v, line:38:1, endln:69:10 + \_module_inst: work@sky130_fd_sc_hd__sdfrbp (work@sky130_fd_sc_hd__sdfrbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfrbp.functional.v, line:38:1, endln:69:10 |vpiName:D |vpiFullName:work@sky130_fd_sc_hd__sdfrbp.D |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__sdfrbp.SCD), line:43:5, endln:43:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfrbp (work@sky130_fd_sc_hd__sdfrbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfrbp.functional.v, line:38:1, endln:69:10 + \_module_inst: work@sky130_fd_sc_hd__sdfrbp (work@sky130_fd_sc_hd__sdfrbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfrbp.functional.v, line:38:1, endln:69:10 |vpiName:SCD |vpiFullName:work@sky130_fd_sc_hd__sdfrbp.SCD |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__sdfrbp.SCE), line:44:5, endln:44:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfrbp (work@sky130_fd_sc_hd__sdfrbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfrbp.functional.v, line:38:1, endln:69:10 + \_module_inst: work@sky130_fd_sc_hd__sdfrbp (work@sky130_fd_sc_hd__sdfrbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfrbp.functional.v, line:38:1, endln:69:10 |vpiName:SCE |vpiFullName:work@sky130_fd_sc_hd__sdfrbp.SCE |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__sdfrbp.RESET_B), line:45:5, endln:45:12 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfrbp (work@sky130_fd_sc_hd__sdfrbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfrbp.functional.v, line:38:1, endln:69:10 + \_module_inst: work@sky130_fd_sc_hd__sdfrbp (work@sky130_fd_sc_hd__sdfrbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfrbp.functional.v, line:38:1, endln:69:10 |vpiName:RESET_B |vpiFullName:work@sky130_fd_sc_hd__sdfrbp.RESET_B |vpiPort: \_port: (Q), line:39:5, endln:39:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfrbp (work@sky130_fd_sc_hd__sdfrbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfrbp.functional.v, line:38:1, endln:69:10 + \_module_inst: work@sky130_fd_sc_hd__sdfrbp (work@sky130_fd_sc_hd__sdfrbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfrbp.functional.v, line:38:1, endln:69:10 |vpiName:Q |vpiDirection:2 |vpiLowConn: @@ -18956,7 +18956,7 @@ design: (work@sky130_fd_sc_hd__sdfrbp) |vpiPort: \_port: (Q_N), line:40:5, endln:40:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfrbp (work@sky130_fd_sc_hd__sdfrbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfrbp.functional.v, line:38:1, endln:69:10 + \_module_inst: work@sky130_fd_sc_hd__sdfrbp (work@sky130_fd_sc_hd__sdfrbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfrbp.functional.v, line:38:1, endln:69:10 |vpiName:Q_N |vpiDirection:2 |vpiLowConn: @@ -18968,7 +18968,7 @@ design: (work@sky130_fd_sc_hd__sdfrbp) |vpiPort: \_port: (CLK), line:41:5, endln:41:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfrbp (work@sky130_fd_sc_hd__sdfrbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfrbp.functional.v, line:38:1, endln:69:10 + \_module_inst: work@sky130_fd_sc_hd__sdfrbp (work@sky130_fd_sc_hd__sdfrbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfrbp.functional.v, line:38:1, endln:69:10 |vpiName:CLK |vpiDirection:1 |vpiLowConn: @@ -18980,7 +18980,7 @@ design: (work@sky130_fd_sc_hd__sdfrbp) |vpiPort: \_port: (D), line:42:5, endln:42:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfrbp (work@sky130_fd_sc_hd__sdfrbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfrbp.functional.v, line:38:1, endln:69:10 + \_module_inst: work@sky130_fd_sc_hd__sdfrbp (work@sky130_fd_sc_hd__sdfrbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfrbp.functional.v, line:38:1, endln:69:10 |vpiName:D |vpiDirection:1 |vpiLowConn: @@ -18992,7 +18992,7 @@ design: (work@sky130_fd_sc_hd__sdfrbp) |vpiPort: \_port: (SCD), line:43:5, endln:43:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfrbp (work@sky130_fd_sc_hd__sdfrbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfrbp.functional.v, line:38:1, endln:69:10 + \_module_inst: work@sky130_fd_sc_hd__sdfrbp (work@sky130_fd_sc_hd__sdfrbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfrbp.functional.v, line:38:1, endln:69:10 |vpiName:SCD |vpiDirection:1 |vpiLowConn: @@ -19004,7 +19004,7 @@ design: (work@sky130_fd_sc_hd__sdfrbp) |vpiPort: \_port: (SCE), line:44:5, endln:44:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfrbp (work@sky130_fd_sc_hd__sdfrbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfrbp.functional.v, line:38:1, endln:69:10 + \_module_inst: work@sky130_fd_sc_hd__sdfrbp (work@sky130_fd_sc_hd__sdfrbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfrbp.functional.v, line:38:1, endln:69:10 |vpiName:SCE |vpiDirection:1 |vpiLowConn: @@ -19016,7 +19016,7 @@ design: (work@sky130_fd_sc_hd__sdfrbp) |vpiPort: \_port: (RESET_B), line:45:5, endln:45:12 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfrbp (work@sky130_fd_sc_hd__sdfrbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfrbp.functional.v, line:38:1, endln:69:10 + \_module_inst: work@sky130_fd_sc_hd__sdfrbp (work@sky130_fd_sc_hd__sdfrbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfrbp.functional.v, line:38:1, endln:69:10 |vpiName:RESET_B |vpiDirection:1 |vpiLowConn: @@ -19026,14 +19026,14 @@ design: (work@sky130_fd_sc_hd__sdfrbp) |vpiTypedef: \_logic_typespec: , line:55:12, endln:55:12 |uhdmtopModules: -\_module: work@sky130_fd_sc_hd__sdfrbp (work@sky130_fd_sc_hd__sdfrbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfrbp.functional.v, line:38:1, endln:69:10 +\_module_inst: work@sky130_fd_sc_hd__sdfrbp (work@sky130_fd_sc_hd__sdfrbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfrbp.functional.v, line:38:1, endln:69:10 |vpiName:work@sky130_fd_sc_hd__sdfrbp |vpiDefName:work@sky130_fd_sc_hd__sdfrbp |vpiTop:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__sdfrbp.buf_Q), line:58:10, endln:58:15 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfrbp (work@sky130_fd_sc_hd__sdfrbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfrbp.functional.v, line:38:1, endln:69:10 + \_module_inst: work@sky130_fd_sc_hd__sdfrbp (work@sky130_fd_sc_hd__sdfrbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfrbp.functional.v, line:38:1, endln:69:10 |vpiTypespec: \_logic_typespec: , line:58:5, endln:58:9 |vpiName:buf_Q @@ -19042,7 +19042,7 @@ design: (work@sky130_fd_sc_hd__sdfrbp) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__sdfrbp.RESET), line:59:10, endln:59:15 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfrbp (work@sky130_fd_sc_hd__sdfrbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfrbp.functional.v, line:38:1, endln:69:10 + \_module_inst: work@sky130_fd_sc_hd__sdfrbp (work@sky130_fd_sc_hd__sdfrbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfrbp.functional.v, line:38:1, endln:69:10 |vpiTypespec: \_logic_typespec: , line:59:5, endln:59:9 |vpiName:RESET @@ -19051,7 +19051,7 @@ design: (work@sky130_fd_sc_hd__sdfrbp) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__sdfrbp.mux_out), line:60:10, endln:60:17 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfrbp (work@sky130_fd_sc_hd__sdfrbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfrbp.functional.v, line:38:1, endln:69:10 + \_module_inst: work@sky130_fd_sc_hd__sdfrbp (work@sky130_fd_sc_hd__sdfrbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfrbp.functional.v, line:38:1, endln:69:10 |vpiTypespec: \_logic_typespec: , line:60:5, endln:60:9 |vpiName:mux_out @@ -19060,7 +19060,7 @@ design: (work@sky130_fd_sc_hd__sdfrbp) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__sdfrbp.Q), line:39:5, endln:39:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfrbp (work@sky130_fd_sc_hd__sdfrbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfrbp.functional.v, line:38:1, endln:69:10 + \_module_inst: work@sky130_fd_sc_hd__sdfrbp (work@sky130_fd_sc_hd__sdfrbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfrbp.functional.v, line:38:1, endln:69:10 |vpiTypespec: \_logic_typespec: , line:49:12, endln:49:12 |vpiName:Q @@ -19068,7 +19068,7 @@ design: (work@sky130_fd_sc_hd__sdfrbp) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__sdfrbp.Q_N), line:40:5, endln:40:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfrbp (work@sky130_fd_sc_hd__sdfrbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfrbp.functional.v, line:38:1, endln:69:10 + \_module_inst: work@sky130_fd_sc_hd__sdfrbp (work@sky130_fd_sc_hd__sdfrbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfrbp.functional.v, line:38:1, endln:69:10 |vpiTypespec: \_logic_typespec: , line:50:12, endln:50:12 |vpiName:Q_N @@ -19076,7 +19076,7 @@ design: (work@sky130_fd_sc_hd__sdfrbp) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__sdfrbp.CLK), line:41:5, endln:41:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfrbp (work@sky130_fd_sc_hd__sdfrbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfrbp.functional.v, line:38:1, endln:69:10 + \_module_inst: work@sky130_fd_sc_hd__sdfrbp (work@sky130_fd_sc_hd__sdfrbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfrbp.functional.v, line:38:1, endln:69:10 |vpiTypespec: \_logic_typespec: , line:51:12, endln:51:12 |vpiName:CLK @@ -19084,7 +19084,7 @@ design: (work@sky130_fd_sc_hd__sdfrbp) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__sdfrbp.D), line:42:5, endln:42:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfrbp (work@sky130_fd_sc_hd__sdfrbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfrbp.functional.v, line:38:1, endln:69:10 + \_module_inst: work@sky130_fd_sc_hd__sdfrbp (work@sky130_fd_sc_hd__sdfrbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfrbp.functional.v, line:38:1, endln:69:10 |vpiTypespec: \_logic_typespec: , line:52:12, endln:52:12 |vpiName:D @@ -19092,7 +19092,7 @@ design: (work@sky130_fd_sc_hd__sdfrbp) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__sdfrbp.SCD), line:43:5, endln:43:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfrbp (work@sky130_fd_sc_hd__sdfrbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfrbp.functional.v, line:38:1, endln:69:10 + \_module_inst: work@sky130_fd_sc_hd__sdfrbp (work@sky130_fd_sc_hd__sdfrbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfrbp.functional.v, line:38:1, endln:69:10 |vpiTypespec: \_logic_typespec: , line:53:12, endln:53:12 |vpiName:SCD @@ -19100,7 +19100,7 @@ design: (work@sky130_fd_sc_hd__sdfrbp) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__sdfrbp.SCE), line:44:5, endln:44:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfrbp (work@sky130_fd_sc_hd__sdfrbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfrbp.functional.v, line:38:1, endln:69:10 + \_module_inst: work@sky130_fd_sc_hd__sdfrbp (work@sky130_fd_sc_hd__sdfrbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfrbp.functional.v, line:38:1, endln:69:10 |vpiTypespec: \_logic_typespec: , line:54:12, endln:54:12 |vpiName:SCE @@ -19108,7 +19108,7 @@ design: (work@sky130_fd_sc_hd__sdfrbp) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__sdfrbp.RESET_B), line:45:5, endln:45:12 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfrbp (work@sky130_fd_sc_hd__sdfrbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfrbp.functional.v, line:38:1, endln:69:10 + \_module_inst: work@sky130_fd_sc_hd__sdfrbp (work@sky130_fd_sc_hd__sdfrbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfrbp.functional.v, line:38:1, endln:69:10 |vpiTypespec: \_logic_typespec: , line:55:12, endln:55:12 |vpiName:RESET_B @@ -19117,7 +19117,7 @@ design: (work@sky130_fd_sc_hd__sdfrbp) |vpiPort: \_port: (Q), line:39:5, endln:39:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfrbp (work@sky130_fd_sc_hd__sdfrbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfrbp.functional.v, line:38:1, endln:69:10 + \_module_inst: work@sky130_fd_sc_hd__sdfrbp (work@sky130_fd_sc_hd__sdfrbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfrbp.functional.v, line:38:1, endln:69:10 |vpiName:Q |vpiDirection:2 |vpiLowConn: @@ -19131,7 +19131,7 @@ design: (work@sky130_fd_sc_hd__sdfrbp) |vpiPort: \_port: (Q_N), line:40:5, endln:40:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfrbp (work@sky130_fd_sc_hd__sdfrbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfrbp.functional.v, line:38:1, endln:69:10 + \_module_inst: work@sky130_fd_sc_hd__sdfrbp (work@sky130_fd_sc_hd__sdfrbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfrbp.functional.v, line:38:1, endln:69:10 |vpiName:Q_N |vpiDirection:2 |vpiLowConn: @@ -19145,7 +19145,7 @@ design: (work@sky130_fd_sc_hd__sdfrbp) |vpiPort: \_port: (CLK), line:41:5, endln:41:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfrbp (work@sky130_fd_sc_hd__sdfrbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfrbp.functional.v, line:38:1, endln:69:10 + \_module_inst: work@sky130_fd_sc_hd__sdfrbp (work@sky130_fd_sc_hd__sdfrbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfrbp.functional.v, line:38:1, endln:69:10 |vpiName:CLK |vpiDirection:1 |vpiLowConn: @@ -19159,7 +19159,7 @@ design: (work@sky130_fd_sc_hd__sdfrbp) |vpiPort: \_port: (D), line:42:5, endln:42:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfrbp (work@sky130_fd_sc_hd__sdfrbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfrbp.functional.v, line:38:1, endln:69:10 + \_module_inst: work@sky130_fd_sc_hd__sdfrbp (work@sky130_fd_sc_hd__sdfrbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfrbp.functional.v, line:38:1, endln:69:10 |vpiName:D |vpiDirection:1 |vpiLowConn: @@ -19173,7 +19173,7 @@ design: (work@sky130_fd_sc_hd__sdfrbp) |vpiPort: \_port: (SCD), line:43:5, endln:43:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfrbp (work@sky130_fd_sc_hd__sdfrbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfrbp.functional.v, line:38:1, endln:69:10 + \_module_inst: work@sky130_fd_sc_hd__sdfrbp (work@sky130_fd_sc_hd__sdfrbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfrbp.functional.v, line:38:1, endln:69:10 |vpiName:SCD |vpiDirection:1 |vpiLowConn: @@ -19187,7 +19187,7 @@ design: (work@sky130_fd_sc_hd__sdfrbp) |vpiPort: \_port: (SCE), line:44:5, endln:44:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfrbp (work@sky130_fd_sc_hd__sdfrbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfrbp.functional.v, line:38:1, endln:69:10 + \_module_inst: work@sky130_fd_sc_hd__sdfrbp (work@sky130_fd_sc_hd__sdfrbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfrbp.functional.v, line:38:1, endln:69:10 |vpiName:SCE |vpiDirection:1 |vpiLowConn: @@ -19201,7 +19201,7 @@ design: (work@sky130_fd_sc_hd__sdfrbp) |vpiPort: \_port: (RESET_B), line:45:5, endln:45:12 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfrbp (work@sky130_fd_sc_hd__sdfrbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfrbp.functional.v, line:38:1, endln:69:10 + \_module_inst: work@sky130_fd_sc_hd__sdfrbp (work@sky130_fd_sc_hd__sdfrbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfrbp.functional.v, line:38:1, endln:69:10 |vpiName:RESET_B |vpiDirection:1 |vpiLowConn: @@ -19215,7 +19215,7 @@ design: (work@sky130_fd_sc_hd__sdfrbp) |vpiPrimitive: \_gate: work@not (work@sky130_fd_sc_hd__sdfrbp.not0), line:63:47, endln:63:87 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfrbp (work@sky130_fd_sc_hd__sdfrbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfrbp.functional.v, line:38:1, endln:69:10 + \_module_inst: work@sky130_fd_sc_hd__sdfrbp (work@sky130_fd_sc_hd__sdfrbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfrbp.functional.v, line:38:1, endln:69:10 |vpiDefName:work@not |vpiName:not0 |vpiFullName:work@sky130_fd_sc_hd__sdfrbp.not0 @@ -19250,7 +19250,7 @@ design: (work@sky130_fd_sc_hd__sdfrbp) |vpiPrimitive: \_udp: work@sky130_fd_sc_hd__udp_mux_2to1 (work@sky130_fd_sc_hd__sdfrbp.mux_2to10), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfrbp.functional.v, line:64:5, endln:64:88 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfrbp (work@sky130_fd_sc_hd__sdfrbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfrbp.functional.v, line:38:1, endln:69:10 + \_module_inst: work@sky130_fd_sc_hd__sdfrbp (work@sky130_fd_sc_hd__sdfrbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfrbp.functional.v, line:38:1, endln:69:10 |vpiDefName:work@sky130_fd_sc_hd__udp_mux_2to1 |vpiName:mux_2to10 |vpiFullName:work@sky130_fd_sc_hd__sdfrbp.mux_2to10 @@ -19259,7 +19259,7 @@ design: (work@sky130_fd_sc_hd__sdfrbp) |vpiPrimitive: \_udp: work@sky130_fd_sc_hd__udp_dff$PR (work@sky130_fd_sc_hd__sdfrbp.dff0), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfrbp.functional.v, line:65:5, endln:65:77 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfrbp (work@sky130_fd_sc_hd__sdfrbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfrbp.functional.v, line:38:1, endln:69:10 + \_module_inst: work@sky130_fd_sc_hd__sdfrbp (work@sky130_fd_sc_hd__sdfrbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfrbp.functional.v, line:38:1, endln:69:10 |vpiDefName:work@sky130_fd_sc_hd__udp_dff$PR |vpiName:dff0 |vpiFullName:work@sky130_fd_sc_hd__sdfrbp.dff0 @@ -19268,7 +19268,7 @@ design: (work@sky130_fd_sc_hd__sdfrbp) |vpiPrimitive: \_gate: work@buf (work@sky130_fd_sc_hd__sdfrbp.buf0), line:66:47, endln:66:87 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfrbp (work@sky130_fd_sc_hd__sdfrbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfrbp.functional.v, line:38:1, endln:69:10 + \_module_inst: work@sky130_fd_sc_hd__sdfrbp (work@sky130_fd_sc_hd__sdfrbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfrbp.functional.v, line:38:1, endln:69:10 |vpiDefName:work@buf |vpiName:buf0 |vpiFullName:work@sky130_fd_sc_hd__sdfrbp.buf0 @@ -19303,7 +19303,7 @@ design: (work@sky130_fd_sc_hd__sdfrbp) |vpiPrimitive: \_gate: work@not (work@sky130_fd_sc_hd__sdfrbp.not1), line:67:47, endln:67:87 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfrbp (work@sky130_fd_sc_hd__sdfrbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfrbp.functional.v, line:38:1, endln:69:10 + \_module_inst: work@sky130_fd_sc_hd__sdfrbp (work@sky130_fd_sc_hd__sdfrbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfrbp.functional.v, line:38:1, endln:69:10 |vpiDefName:work@not |vpiName:not1 |vpiFullName:work@sky130_fd_sc_hd__sdfrbp.not1 @@ -19420,7 +19420,7 @@ design: (work@sky130_fd_sc_hd__dlclkp) |vpiSize:2 |STRING:1 x : 1 : 1 |uhdmallModules: -\_module: work@sky130_fd_sc_hd__dlclkp (work@sky130_fd_sc_hd__dlclkp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlclkp.functional.v, line:36:1, endln:56:10 +\_module_inst: work@sky130_fd_sc_hd__dlclkp (work@sky130_fd_sc_hd__dlclkp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlclkp.functional.v, line:36:1, endln:56:10 |vpiParent: \_design: (work@sky130_fd_sc_hd__dlclkp) |vpiFullName:work@sky130_fd_sc_hd__dlclkp @@ -19428,39 +19428,39 @@ design: (work@sky130_fd_sc_hd__dlclkp) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__dlclkp.m0), line:48:10, endln:48:12 |vpiParent: - \_module: work@sky130_fd_sc_hd__dlclkp (work@sky130_fd_sc_hd__dlclkp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlclkp.functional.v, line:36:1, endln:56:10 + \_module_inst: work@sky130_fd_sc_hd__dlclkp (work@sky130_fd_sc_hd__dlclkp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlclkp.functional.v, line:36:1, endln:56:10 |vpiName:m0 |vpiFullName:work@sky130_fd_sc_hd__dlclkp.m0 |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__dlclkp.clkn), line:49:10, endln:49:14 |vpiParent: - \_module: work@sky130_fd_sc_hd__dlclkp (work@sky130_fd_sc_hd__dlclkp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlclkp.functional.v, line:36:1, endln:56:10 + \_module_inst: work@sky130_fd_sc_hd__dlclkp (work@sky130_fd_sc_hd__dlclkp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlclkp.functional.v, line:36:1, endln:56:10 |vpiName:clkn |vpiFullName:work@sky130_fd_sc_hd__dlclkp.clkn |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__dlclkp.GCLK), line:37:5, endln:37:9 |vpiParent: - \_module: work@sky130_fd_sc_hd__dlclkp (work@sky130_fd_sc_hd__dlclkp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlclkp.functional.v, line:36:1, endln:56:10 + \_module_inst: work@sky130_fd_sc_hd__dlclkp (work@sky130_fd_sc_hd__dlclkp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlclkp.functional.v, line:36:1, endln:56:10 |vpiName:GCLK |vpiFullName:work@sky130_fd_sc_hd__dlclkp.GCLK |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__dlclkp.GATE), line:38:5, endln:38:9 |vpiParent: - \_module: work@sky130_fd_sc_hd__dlclkp (work@sky130_fd_sc_hd__dlclkp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlclkp.functional.v, line:36:1, endln:56:10 + \_module_inst: work@sky130_fd_sc_hd__dlclkp (work@sky130_fd_sc_hd__dlclkp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlclkp.functional.v, line:36:1, endln:56:10 |vpiName:GATE |vpiFullName:work@sky130_fd_sc_hd__dlclkp.GATE |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__dlclkp.CLK), line:39:5, endln:39:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__dlclkp (work@sky130_fd_sc_hd__dlclkp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlclkp.functional.v, line:36:1, endln:56:10 + \_module_inst: work@sky130_fd_sc_hd__dlclkp (work@sky130_fd_sc_hd__dlclkp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlclkp.functional.v, line:36:1, endln:56:10 |vpiName:CLK |vpiFullName:work@sky130_fd_sc_hd__dlclkp.CLK |vpiPort: \_port: (GCLK), line:37:5, endln:37:9 |vpiParent: - \_module: work@sky130_fd_sc_hd__dlclkp (work@sky130_fd_sc_hd__dlclkp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlclkp.functional.v, line:36:1, endln:56:10 + \_module_inst: work@sky130_fd_sc_hd__dlclkp (work@sky130_fd_sc_hd__dlclkp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlclkp.functional.v, line:36:1, endln:56:10 |vpiName:GCLK |vpiDirection:2 |vpiLowConn: @@ -19472,7 +19472,7 @@ design: (work@sky130_fd_sc_hd__dlclkp) |vpiPort: \_port: (GATE), line:38:5, endln:38:9 |vpiParent: - \_module: work@sky130_fd_sc_hd__dlclkp (work@sky130_fd_sc_hd__dlclkp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlclkp.functional.v, line:36:1, endln:56:10 + \_module_inst: work@sky130_fd_sc_hd__dlclkp (work@sky130_fd_sc_hd__dlclkp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlclkp.functional.v, line:36:1, endln:56:10 |vpiName:GATE |vpiDirection:1 |vpiLowConn: @@ -19484,7 +19484,7 @@ design: (work@sky130_fd_sc_hd__dlclkp) |vpiPort: \_port: (CLK), line:39:5, endln:39:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__dlclkp (work@sky130_fd_sc_hd__dlclkp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlclkp.functional.v, line:36:1, endln:56:10 + \_module_inst: work@sky130_fd_sc_hd__dlclkp (work@sky130_fd_sc_hd__dlclkp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlclkp.functional.v, line:36:1, endln:56:10 |vpiName:CLK |vpiDirection:1 |vpiLowConn: @@ -19494,14 +19494,14 @@ design: (work@sky130_fd_sc_hd__dlclkp) |vpiTypedef: \_logic_typespec: , line:45:12, endln:45:12 |uhdmtopModules: -\_module: work@sky130_fd_sc_hd__dlclkp (work@sky130_fd_sc_hd__dlclkp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlclkp.functional.v, line:36:1, endln:56:10 +\_module_inst: work@sky130_fd_sc_hd__dlclkp (work@sky130_fd_sc_hd__dlclkp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlclkp.functional.v, line:36:1, endln:56:10 |vpiName:work@sky130_fd_sc_hd__dlclkp |vpiDefName:work@sky130_fd_sc_hd__dlclkp |vpiTop:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__dlclkp.m0), line:48:10, endln:48:12 |vpiParent: - \_module: work@sky130_fd_sc_hd__dlclkp (work@sky130_fd_sc_hd__dlclkp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlclkp.functional.v, line:36:1, endln:56:10 + \_module_inst: work@sky130_fd_sc_hd__dlclkp (work@sky130_fd_sc_hd__dlclkp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlclkp.functional.v, line:36:1, endln:56:10 |vpiTypespec: \_logic_typespec: , line:48:5, endln:48:9 |vpiName:m0 @@ -19510,7 +19510,7 @@ design: (work@sky130_fd_sc_hd__dlclkp) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__dlclkp.clkn), line:49:10, endln:49:14 |vpiParent: - \_module: work@sky130_fd_sc_hd__dlclkp (work@sky130_fd_sc_hd__dlclkp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlclkp.functional.v, line:36:1, endln:56:10 + \_module_inst: work@sky130_fd_sc_hd__dlclkp (work@sky130_fd_sc_hd__dlclkp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlclkp.functional.v, line:36:1, endln:56:10 |vpiTypespec: \_logic_typespec: , line:49:5, endln:49:9 |vpiName:clkn @@ -19519,7 +19519,7 @@ design: (work@sky130_fd_sc_hd__dlclkp) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__dlclkp.GCLK), line:37:5, endln:37:9 |vpiParent: - \_module: work@sky130_fd_sc_hd__dlclkp (work@sky130_fd_sc_hd__dlclkp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlclkp.functional.v, line:36:1, endln:56:10 + \_module_inst: work@sky130_fd_sc_hd__dlclkp (work@sky130_fd_sc_hd__dlclkp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlclkp.functional.v, line:36:1, endln:56:10 |vpiTypespec: \_logic_typespec: , line:43:12, endln:43:12 |vpiName:GCLK @@ -19527,7 +19527,7 @@ design: (work@sky130_fd_sc_hd__dlclkp) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__dlclkp.GATE), line:38:5, endln:38:9 |vpiParent: - \_module: work@sky130_fd_sc_hd__dlclkp (work@sky130_fd_sc_hd__dlclkp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlclkp.functional.v, line:36:1, endln:56:10 + \_module_inst: work@sky130_fd_sc_hd__dlclkp (work@sky130_fd_sc_hd__dlclkp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlclkp.functional.v, line:36:1, endln:56:10 |vpiTypespec: \_logic_typespec: , line:44:12, endln:44:12 |vpiName:GATE @@ -19535,7 +19535,7 @@ design: (work@sky130_fd_sc_hd__dlclkp) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__dlclkp.CLK), line:39:5, endln:39:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__dlclkp (work@sky130_fd_sc_hd__dlclkp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlclkp.functional.v, line:36:1, endln:56:10 + \_module_inst: work@sky130_fd_sc_hd__dlclkp (work@sky130_fd_sc_hd__dlclkp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlclkp.functional.v, line:36:1, endln:56:10 |vpiTypespec: \_logic_typespec: , line:45:12, endln:45:12 |vpiName:CLK @@ -19544,7 +19544,7 @@ design: (work@sky130_fd_sc_hd__dlclkp) |vpiPort: \_port: (GCLK), line:37:5, endln:37:9 |vpiParent: - \_module: work@sky130_fd_sc_hd__dlclkp (work@sky130_fd_sc_hd__dlclkp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlclkp.functional.v, line:36:1, endln:56:10 + \_module_inst: work@sky130_fd_sc_hd__dlclkp (work@sky130_fd_sc_hd__dlclkp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlclkp.functional.v, line:36:1, endln:56:10 |vpiName:GCLK |vpiDirection:2 |vpiLowConn: @@ -19558,7 +19558,7 @@ design: (work@sky130_fd_sc_hd__dlclkp) |vpiPort: \_port: (GATE), line:38:5, endln:38:9 |vpiParent: - \_module: work@sky130_fd_sc_hd__dlclkp (work@sky130_fd_sc_hd__dlclkp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlclkp.functional.v, line:36:1, endln:56:10 + \_module_inst: work@sky130_fd_sc_hd__dlclkp (work@sky130_fd_sc_hd__dlclkp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlclkp.functional.v, line:36:1, endln:56:10 |vpiName:GATE |vpiDirection:1 |vpiLowConn: @@ -19572,7 +19572,7 @@ design: (work@sky130_fd_sc_hd__dlclkp) |vpiPort: \_port: (CLK), line:39:5, endln:39:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__dlclkp (work@sky130_fd_sc_hd__dlclkp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlclkp.functional.v, line:36:1, endln:56:10 + \_module_inst: work@sky130_fd_sc_hd__dlclkp (work@sky130_fd_sc_hd__dlclkp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlclkp.functional.v, line:36:1, endln:56:10 |vpiName:CLK |vpiDirection:1 |vpiLowConn: @@ -19586,7 +19586,7 @@ design: (work@sky130_fd_sc_hd__dlclkp) |vpiPrimitive: \_gate: work@not (work@sky130_fd_sc_hd__dlclkp.not0), line:52:35, endln:52:68 |vpiParent: - \_module: work@sky130_fd_sc_hd__dlclkp (work@sky130_fd_sc_hd__dlclkp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlclkp.functional.v, line:36:1, endln:56:10 + \_module_inst: work@sky130_fd_sc_hd__dlclkp (work@sky130_fd_sc_hd__dlclkp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlclkp.functional.v, line:36:1, endln:56:10 |vpiDefName:work@not |vpiName:not0 |vpiFullName:work@sky130_fd_sc_hd__dlclkp.not0 @@ -19621,7 +19621,7 @@ design: (work@sky130_fd_sc_hd__dlclkp) |vpiPrimitive: \_udp: work@sky130_fd_sc_hd__udp_dlatch$P (work@sky130_fd_sc_hd__dlclkp.dlatch0), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlclkp.functional.v, line:53:5, endln:53:69 |vpiParent: - \_module: work@sky130_fd_sc_hd__dlclkp (work@sky130_fd_sc_hd__dlclkp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlclkp.functional.v, line:36:1, endln:56:10 + \_module_inst: work@sky130_fd_sc_hd__dlclkp (work@sky130_fd_sc_hd__dlclkp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlclkp.functional.v, line:36:1, endln:56:10 |vpiDefName:work@sky130_fd_sc_hd__udp_dlatch$P |vpiName:dlatch0 |vpiFullName:work@sky130_fd_sc_hd__dlclkp.dlatch0 @@ -19630,7 +19630,7 @@ design: (work@sky130_fd_sc_hd__dlclkp) |vpiPrimitive: \_gate: work@and (work@sky130_fd_sc_hd__dlclkp.and0), line:54:35, endln:54:68 |vpiParent: - \_module: work@sky130_fd_sc_hd__dlclkp (work@sky130_fd_sc_hd__dlclkp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlclkp.functional.v, line:36:1, endln:56:10 + \_module_inst: work@sky130_fd_sc_hd__dlclkp (work@sky130_fd_sc_hd__dlclkp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlclkp.functional.v, line:36:1, endln:56:10 |vpiDefName:work@and |vpiName:and0 |vpiFullName:work@sky130_fd_sc_hd__dlclkp.and0 @@ -19687,7 +19687,7 @@ Processing: -cd cells/cells -DUNIT_DELAY -writepp -parse -nocache -nobuiltin -no design: (work@sky130_fd_sc_hd__clkinv) |vpiName:work@sky130_fd_sc_hd__clkinv |uhdmallModules: -\_module: work@sky130_fd_sc_hd__clkinv (work@sky130_fd_sc_hd__clkinv), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__clkinv.functional.v, line:33:1, endln:49:10 +\_module_inst: work@sky130_fd_sc_hd__clkinv (work@sky130_fd_sc_hd__clkinv), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__clkinv.functional.v, line:33:1, endln:49:10 |vpiParent: \_design: (work@sky130_fd_sc_hd__clkinv) |vpiFullName:work@sky130_fd_sc_hd__clkinv @@ -19695,26 +19695,26 @@ design: (work@sky130_fd_sc_hd__clkinv) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__clkinv.not0_out_Y), line:43:10, endln:43:20 |vpiParent: - \_module: work@sky130_fd_sc_hd__clkinv (work@sky130_fd_sc_hd__clkinv), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__clkinv.functional.v, line:33:1, endln:49:10 + \_module_inst: work@sky130_fd_sc_hd__clkinv (work@sky130_fd_sc_hd__clkinv), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__clkinv.functional.v, line:33:1, endln:49:10 |vpiName:not0_out_Y |vpiFullName:work@sky130_fd_sc_hd__clkinv.not0_out_Y |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__clkinv.Y), line:34:5, endln:34:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__clkinv (work@sky130_fd_sc_hd__clkinv), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__clkinv.functional.v, line:33:1, endln:49:10 + \_module_inst: work@sky130_fd_sc_hd__clkinv (work@sky130_fd_sc_hd__clkinv), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__clkinv.functional.v, line:33:1, endln:49:10 |vpiName:Y |vpiFullName:work@sky130_fd_sc_hd__clkinv.Y |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__clkinv.A), line:35:5, endln:35:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__clkinv (work@sky130_fd_sc_hd__clkinv), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__clkinv.functional.v, line:33:1, endln:49:10 + \_module_inst: work@sky130_fd_sc_hd__clkinv (work@sky130_fd_sc_hd__clkinv), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__clkinv.functional.v, line:33:1, endln:49:10 |vpiName:A |vpiFullName:work@sky130_fd_sc_hd__clkinv.A |vpiPort: \_port: (Y), line:34:5, endln:34:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__clkinv (work@sky130_fd_sc_hd__clkinv), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__clkinv.functional.v, line:33:1, endln:49:10 + \_module_inst: work@sky130_fd_sc_hd__clkinv (work@sky130_fd_sc_hd__clkinv), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__clkinv.functional.v, line:33:1, endln:49:10 |vpiName:Y |vpiDirection:2 |vpiLowConn: @@ -19726,7 +19726,7 @@ design: (work@sky130_fd_sc_hd__clkinv) |vpiPort: \_port: (A), line:35:5, endln:35:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__clkinv (work@sky130_fd_sc_hd__clkinv), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__clkinv.functional.v, line:33:1, endln:49:10 + \_module_inst: work@sky130_fd_sc_hd__clkinv (work@sky130_fd_sc_hd__clkinv), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__clkinv.functional.v, line:33:1, endln:49:10 |vpiName:A |vpiDirection:1 |vpiLowConn: @@ -19736,14 +19736,14 @@ design: (work@sky130_fd_sc_hd__clkinv) |vpiTypedef: \_logic_typespec: , line:40:12, endln:40:12 |uhdmtopModules: -\_module: work@sky130_fd_sc_hd__clkinv (work@sky130_fd_sc_hd__clkinv), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__clkinv.functional.v, line:33:1, endln:49:10 +\_module_inst: work@sky130_fd_sc_hd__clkinv (work@sky130_fd_sc_hd__clkinv), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__clkinv.functional.v, line:33:1, endln:49:10 |vpiName:work@sky130_fd_sc_hd__clkinv |vpiDefName:work@sky130_fd_sc_hd__clkinv |vpiTop:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__clkinv.not0_out_Y), line:43:10, endln:43:20 |vpiParent: - \_module: work@sky130_fd_sc_hd__clkinv (work@sky130_fd_sc_hd__clkinv), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__clkinv.functional.v, line:33:1, endln:49:10 + \_module_inst: work@sky130_fd_sc_hd__clkinv (work@sky130_fd_sc_hd__clkinv), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__clkinv.functional.v, line:33:1, endln:49:10 |vpiTypespec: \_logic_typespec: , line:43:5, endln:43:9 |vpiName:not0_out_Y @@ -19752,7 +19752,7 @@ design: (work@sky130_fd_sc_hd__clkinv) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__clkinv.Y), line:34:5, endln:34:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__clkinv (work@sky130_fd_sc_hd__clkinv), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__clkinv.functional.v, line:33:1, endln:49:10 + \_module_inst: work@sky130_fd_sc_hd__clkinv (work@sky130_fd_sc_hd__clkinv), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__clkinv.functional.v, line:33:1, endln:49:10 |vpiTypespec: \_logic_typespec: , line:39:12, endln:39:12 |vpiName:Y @@ -19760,7 +19760,7 @@ design: (work@sky130_fd_sc_hd__clkinv) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__clkinv.A), line:35:5, endln:35:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__clkinv (work@sky130_fd_sc_hd__clkinv), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__clkinv.functional.v, line:33:1, endln:49:10 + \_module_inst: work@sky130_fd_sc_hd__clkinv (work@sky130_fd_sc_hd__clkinv), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__clkinv.functional.v, line:33:1, endln:49:10 |vpiTypespec: \_logic_typespec: , line:40:12, endln:40:12 |vpiName:A @@ -19769,7 +19769,7 @@ design: (work@sky130_fd_sc_hd__clkinv) |vpiPort: \_port: (Y), line:34:5, endln:34:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__clkinv (work@sky130_fd_sc_hd__clkinv), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__clkinv.functional.v, line:33:1, endln:49:10 + \_module_inst: work@sky130_fd_sc_hd__clkinv (work@sky130_fd_sc_hd__clkinv), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__clkinv.functional.v, line:33:1, endln:49:10 |vpiName:Y |vpiDirection:2 |vpiLowConn: @@ -19783,7 +19783,7 @@ design: (work@sky130_fd_sc_hd__clkinv) |vpiPort: \_port: (A), line:35:5, endln:35:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__clkinv (work@sky130_fd_sc_hd__clkinv), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__clkinv.functional.v, line:33:1, endln:49:10 + \_module_inst: work@sky130_fd_sc_hd__clkinv (work@sky130_fd_sc_hd__clkinv), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__clkinv.functional.v, line:33:1, endln:49:10 |vpiName:A |vpiDirection:1 |vpiLowConn: @@ -19797,7 +19797,7 @@ design: (work@sky130_fd_sc_hd__clkinv) |vpiPrimitive: \_gate: work@not (work@sky130_fd_sc_hd__clkinv.not0), line:46:9, endln:46:43 |vpiParent: - \_module: work@sky130_fd_sc_hd__clkinv (work@sky130_fd_sc_hd__clkinv), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__clkinv.functional.v, line:33:1, endln:49:10 + \_module_inst: work@sky130_fd_sc_hd__clkinv (work@sky130_fd_sc_hd__clkinv), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__clkinv.functional.v, line:33:1, endln:49:10 |vpiDefName:work@not |vpiName:not0 |vpiFullName:work@sky130_fd_sc_hd__clkinv.not0 @@ -19832,7 +19832,7 @@ design: (work@sky130_fd_sc_hd__clkinv) |vpiPrimitive: \_gate: work@buf (work@sky130_fd_sc_hd__clkinv.buf0), line:47:9, endln:47:43 |vpiParent: - \_module: work@sky130_fd_sc_hd__clkinv (work@sky130_fd_sc_hd__clkinv), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__clkinv.functional.v, line:33:1, endln:49:10 + \_module_inst: work@sky130_fd_sc_hd__clkinv (work@sky130_fd_sc_hd__clkinv), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__clkinv.functional.v, line:33:1, endln:49:10 |vpiDefName:work@buf |vpiName:buf0 |vpiFullName:work@sky130_fd_sc_hd__clkinv.buf0 @@ -20075,7 +20075,7 @@ design: (work@sky130_fd_sc_hd__mux4) |vpiSize:6 |STRING:? 1 ? 1 1 ? : 1 |uhdmallModules: -\_module: work@sky130_fd_sc_hd__mux4 (work@sky130_fd_sc_hd__mux4), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__mux4.functional.v, line:36:1, endln:62:10 +\_module_inst: work@sky130_fd_sc_hd__mux4 (work@sky130_fd_sc_hd__mux4), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__mux4.functional.v, line:36:1, endln:62:10 |vpiParent: \_design: (work@sky130_fd_sc_hd__mux4) |vpiFullName:work@sky130_fd_sc_hd__mux4 @@ -20083,56 +20083,56 @@ design: (work@sky130_fd_sc_hd__mux4) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__mux4.mux_4to20_out_X), line:56:10, endln:56:25 |vpiParent: - \_module: work@sky130_fd_sc_hd__mux4 (work@sky130_fd_sc_hd__mux4), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__mux4.functional.v, line:36:1, endln:62:10 + \_module_inst: work@sky130_fd_sc_hd__mux4 (work@sky130_fd_sc_hd__mux4), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__mux4.functional.v, line:36:1, endln:62:10 |vpiName:mux_4to20_out_X |vpiFullName:work@sky130_fd_sc_hd__mux4.mux_4to20_out_X |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__mux4.X), line:37:5, endln:37:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__mux4 (work@sky130_fd_sc_hd__mux4), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__mux4.functional.v, line:36:1, endln:62:10 + \_module_inst: work@sky130_fd_sc_hd__mux4 (work@sky130_fd_sc_hd__mux4), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__mux4.functional.v, line:36:1, endln:62:10 |vpiName:X |vpiFullName:work@sky130_fd_sc_hd__mux4.X |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__mux4.A0), line:38:5, endln:38:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__mux4 (work@sky130_fd_sc_hd__mux4), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__mux4.functional.v, line:36:1, endln:62:10 + \_module_inst: work@sky130_fd_sc_hd__mux4 (work@sky130_fd_sc_hd__mux4), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__mux4.functional.v, line:36:1, endln:62:10 |vpiName:A0 |vpiFullName:work@sky130_fd_sc_hd__mux4.A0 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__mux4.A1), line:39:5, endln:39:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__mux4 (work@sky130_fd_sc_hd__mux4), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__mux4.functional.v, line:36:1, endln:62:10 + \_module_inst: work@sky130_fd_sc_hd__mux4 (work@sky130_fd_sc_hd__mux4), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__mux4.functional.v, line:36:1, endln:62:10 |vpiName:A1 |vpiFullName:work@sky130_fd_sc_hd__mux4.A1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__mux4.A2), line:40:5, endln:40:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__mux4 (work@sky130_fd_sc_hd__mux4), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__mux4.functional.v, line:36:1, endln:62:10 + \_module_inst: work@sky130_fd_sc_hd__mux4 (work@sky130_fd_sc_hd__mux4), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__mux4.functional.v, line:36:1, endln:62:10 |vpiName:A2 |vpiFullName:work@sky130_fd_sc_hd__mux4.A2 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__mux4.A3), line:41:5, endln:41:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__mux4 (work@sky130_fd_sc_hd__mux4), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__mux4.functional.v, line:36:1, endln:62:10 + \_module_inst: work@sky130_fd_sc_hd__mux4 (work@sky130_fd_sc_hd__mux4), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__mux4.functional.v, line:36:1, endln:62:10 |vpiName:A3 |vpiFullName:work@sky130_fd_sc_hd__mux4.A3 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__mux4.S0), line:42:5, endln:42:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__mux4 (work@sky130_fd_sc_hd__mux4), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__mux4.functional.v, line:36:1, endln:62:10 + \_module_inst: work@sky130_fd_sc_hd__mux4 (work@sky130_fd_sc_hd__mux4), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__mux4.functional.v, line:36:1, endln:62:10 |vpiName:S0 |vpiFullName:work@sky130_fd_sc_hd__mux4.S0 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__mux4.S1), line:43:5, endln:43:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__mux4 (work@sky130_fd_sc_hd__mux4), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__mux4.functional.v, line:36:1, endln:62:10 + \_module_inst: work@sky130_fd_sc_hd__mux4 (work@sky130_fd_sc_hd__mux4), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__mux4.functional.v, line:36:1, endln:62:10 |vpiName:S1 |vpiFullName:work@sky130_fd_sc_hd__mux4.S1 |vpiPort: \_port: (X), line:37:5, endln:37:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__mux4 (work@sky130_fd_sc_hd__mux4), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__mux4.functional.v, line:36:1, endln:62:10 + \_module_inst: work@sky130_fd_sc_hd__mux4 (work@sky130_fd_sc_hd__mux4), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__mux4.functional.v, line:36:1, endln:62:10 |vpiName:X |vpiDirection:2 |vpiLowConn: @@ -20144,7 +20144,7 @@ design: (work@sky130_fd_sc_hd__mux4) |vpiPort: \_port: (A0), line:38:5, endln:38:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__mux4 (work@sky130_fd_sc_hd__mux4), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__mux4.functional.v, line:36:1, endln:62:10 + \_module_inst: work@sky130_fd_sc_hd__mux4 (work@sky130_fd_sc_hd__mux4), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__mux4.functional.v, line:36:1, endln:62:10 |vpiName:A0 |vpiDirection:1 |vpiLowConn: @@ -20156,7 +20156,7 @@ design: (work@sky130_fd_sc_hd__mux4) |vpiPort: \_port: (A1), line:39:5, endln:39:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__mux4 (work@sky130_fd_sc_hd__mux4), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__mux4.functional.v, line:36:1, endln:62:10 + \_module_inst: work@sky130_fd_sc_hd__mux4 (work@sky130_fd_sc_hd__mux4), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__mux4.functional.v, line:36:1, endln:62:10 |vpiName:A1 |vpiDirection:1 |vpiLowConn: @@ -20168,7 +20168,7 @@ design: (work@sky130_fd_sc_hd__mux4) |vpiPort: \_port: (A2), line:40:5, endln:40:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__mux4 (work@sky130_fd_sc_hd__mux4), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__mux4.functional.v, line:36:1, endln:62:10 + \_module_inst: work@sky130_fd_sc_hd__mux4 (work@sky130_fd_sc_hd__mux4), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__mux4.functional.v, line:36:1, endln:62:10 |vpiName:A2 |vpiDirection:1 |vpiLowConn: @@ -20180,7 +20180,7 @@ design: (work@sky130_fd_sc_hd__mux4) |vpiPort: \_port: (A3), line:41:5, endln:41:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__mux4 (work@sky130_fd_sc_hd__mux4), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__mux4.functional.v, line:36:1, endln:62:10 + \_module_inst: work@sky130_fd_sc_hd__mux4 (work@sky130_fd_sc_hd__mux4), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__mux4.functional.v, line:36:1, endln:62:10 |vpiName:A3 |vpiDirection:1 |vpiLowConn: @@ -20192,7 +20192,7 @@ design: (work@sky130_fd_sc_hd__mux4) |vpiPort: \_port: (S0), line:42:5, endln:42:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__mux4 (work@sky130_fd_sc_hd__mux4), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__mux4.functional.v, line:36:1, endln:62:10 + \_module_inst: work@sky130_fd_sc_hd__mux4 (work@sky130_fd_sc_hd__mux4), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__mux4.functional.v, line:36:1, endln:62:10 |vpiName:S0 |vpiDirection:1 |vpiLowConn: @@ -20204,7 +20204,7 @@ design: (work@sky130_fd_sc_hd__mux4) |vpiPort: \_port: (S1), line:43:5, endln:43:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__mux4 (work@sky130_fd_sc_hd__mux4), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__mux4.functional.v, line:36:1, endln:62:10 + \_module_inst: work@sky130_fd_sc_hd__mux4 (work@sky130_fd_sc_hd__mux4), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__mux4.functional.v, line:36:1, endln:62:10 |vpiName:S1 |vpiDirection:1 |vpiLowConn: @@ -20214,14 +20214,14 @@ design: (work@sky130_fd_sc_hd__mux4) |vpiTypedef: \_logic_typespec: , line:53:12, endln:53:12 |uhdmtopModules: -\_module: work@sky130_fd_sc_hd__mux4 (work@sky130_fd_sc_hd__mux4), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__mux4.functional.v, line:36:1, endln:62:10 +\_module_inst: work@sky130_fd_sc_hd__mux4 (work@sky130_fd_sc_hd__mux4), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__mux4.functional.v, line:36:1, endln:62:10 |vpiName:work@sky130_fd_sc_hd__mux4 |vpiDefName:work@sky130_fd_sc_hd__mux4 |vpiTop:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__mux4.mux_4to20_out_X), line:56:10, endln:56:25 |vpiParent: - \_module: work@sky130_fd_sc_hd__mux4 (work@sky130_fd_sc_hd__mux4), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__mux4.functional.v, line:36:1, endln:62:10 + \_module_inst: work@sky130_fd_sc_hd__mux4 (work@sky130_fd_sc_hd__mux4), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__mux4.functional.v, line:36:1, endln:62:10 |vpiTypespec: \_logic_typespec: , line:56:5, endln:56:9 |vpiName:mux_4to20_out_X @@ -20230,7 +20230,7 @@ design: (work@sky130_fd_sc_hd__mux4) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__mux4.X), line:37:5, endln:37:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__mux4 (work@sky130_fd_sc_hd__mux4), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__mux4.functional.v, line:36:1, endln:62:10 + \_module_inst: work@sky130_fd_sc_hd__mux4 (work@sky130_fd_sc_hd__mux4), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__mux4.functional.v, line:36:1, endln:62:10 |vpiTypespec: \_logic_typespec: , line:47:12, endln:47:12 |vpiName:X @@ -20238,7 +20238,7 @@ design: (work@sky130_fd_sc_hd__mux4) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__mux4.A0), line:38:5, endln:38:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__mux4 (work@sky130_fd_sc_hd__mux4), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__mux4.functional.v, line:36:1, endln:62:10 + \_module_inst: work@sky130_fd_sc_hd__mux4 (work@sky130_fd_sc_hd__mux4), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__mux4.functional.v, line:36:1, endln:62:10 |vpiTypespec: \_logic_typespec: , line:48:12, endln:48:12 |vpiName:A0 @@ -20246,7 +20246,7 @@ design: (work@sky130_fd_sc_hd__mux4) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__mux4.A1), line:39:5, endln:39:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__mux4 (work@sky130_fd_sc_hd__mux4), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__mux4.functional.v, line:36:1, endln:62:10 + \_module_inst: work@sky130_fd_sc_hd__mux4 (work@sky130_fd_sc_hd__mux4), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__mux4.functional.v, line:36:1, endln:62:10 |vpiTypespec: \_logic_typespec: , line:49:12, endln:49:12 |vpiName:A1 @@ -20254,7 +20254,7 @@ design: (work@sky130_fd_sc_hd__mux4) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__mux4.A2), line:40:5, endln:40:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__mux4 (work@sky130_fd_sc_hd__mux4), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__mux4.functional.v, line:36:1, endln:62:10 + \_module_inst: work@sky130_fd_sc_hd__mux4 (work@sky130_fd_sc_hd__mux4), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__mux4.functional.v, line:36:1, endln:62:10 |vpiTypespec: \_logic_typespec: , line:50:12, endln:50:12 |vpiName:A2 @@ -20262,7 +20262,7 @@ design: (work@sky130_fd_sc_hd__mux4) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__mux4.A3), line:41:5, endln:41:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__mux4 (work@sky130_fd_sc_hd__mux4), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__mux4.functional.v, line:36:1, endln:62:10 + \_module_inst: work@sky130_fd_sc_hd__mux4 (work@sky130_fd_sc_hd__mux4), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__mux4.functional.v, line:36:1, endln:62:10 |vpiTypespec: \_logic_typespec: , line:51:12, endln:51:12 |vpiName:A3 @@ -20270,7 +20270,7 @@ design: (work@sky130_fd_sc_hd__mux4) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__mux4.S0), line:42:5, endln:42:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__mux4 (work@sky130_fd_sc_hd__mux4), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__mux4.functional.v, line:36:1, endln:62:10 + \_module_inst: work@sky130_fd_sc_hd__mux4 (work@sky130_fd_sc_hd__mux4), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__mux4.functional.v, line:36:1, endln:62:10 |vpiTypespec: \_logic_typespec: , line:52:12, endln:52:12 |vpiName:S0 @@ -20278,7 +20278,7 @@ design: (work@sky130_fd_sc_hd__mux4) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__mux4.S1), line:43:5, endln:43:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__mux4 (work@sky130_fd_sc_hd__mux4), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__mux4.functional.v, line:36:1, endln:62:10 + \_module_inst: work@sky130_fd_sc_hd__mux4 (work@sky130_fd_sc_hd__mux4), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__mux4.functional.v, line:36:1, endln:62:10 |vpiTypespec: \_logic_typespec: , line:53:12, endln:53:12 |vpiName:S1 @@ -20287,7 +20287,7 @@ design: (work@sky130_fd_sc_hd__mux4) |vpiPort: \_port: (X), line:37:5, endln:37:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__mux4 (work@sky130_fd_sc_hd__mux4), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__mux4.functional.v, line:36:1, endln:62:10 + \_module_inst: work@sky130_fd_sc_hd__mux4 (work@sky130_fd_sc_hd__mux4), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__mux4.functional.v, line:36:1, endln:62:10 |vpiName:X |vpiDirection:2 |vpiLowConn: @@ -20301,7 +20301,7 @@ design: (work@sky130_fd_sc_hd__mux4) |vpiPort: \_port: (A0), line:38:5, endln:38:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__mux4 (work@sky130_fd_sc_hd__mux4), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__mux4.functional.v, line:36:1, endln:62:10 + \_module_inst: work@sky130_fd_sc_hd__mux4 (work@sky130_fd_sc_hd__mux4), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__mux4.functional.v, line:36:1, endln:62:10 |vpiName:A0 |vpiDirection:1 |vpiLowConn: @@ -20315,7 +20315,7 @@ design: (work@sky130_fd_sc_hd__mux4) |vpiPort: \_port: (A1), line:39:5, endln:39:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__mux4 (work@sky130_fd_sc_hd__mux4), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__mux4.functional.v, line:36:1, endln:62:10 + \_module_inst: work@sky130_fd_sc_hd__mux4 (work@sky130_fd_sc_hd__mux4), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__mux4.functional.v, line:36:1, endln:62:10 |vpiName:A1 |vpiDirection:1 |vpiLowConn: @@ -20329,7 +20329,7 @@ design: (work@sky130_fd_sc_hd__mux4) |vpiPort: \_port: (A2), line:40:5, endln:40:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__mux4 (work@sky130_fd_sc_hd__mux4), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__mux4.functional.v, line:36:1, endln:62:10 + \_module_inst: work@sky130_fd_sc_hd__mux4 (work@sky130_fd_sc_hd__mux4), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__mux4.functional.v, line:36:1, endln:62:10 |vpiName:A2 |vpiDirection:1 |vpiLowConn: @@ -20343,7 +20343,7 @@ design: (work@sky130_fd_sc_hd__mux4) |vpiPort: \_port: (A3), line:41:5, endln:41:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__mux4 (work@sky130_fd_sc_hd__mux4), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__mux4.functional.v, line:36:1, endln:62:10 + \_module_inst: work@sky130_fd_sc_hd__mux4 (work@sky130_fd_sc_hd__mux4), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__mux4.functional.v, line:36:1, endln:62:10 |vpiName:A3 |vpiDirection:1 |vpiLowConn: @@ -20357,7 +20357,7 @@ design: (work@sky130_fd_sc_hd__mux4) |vpiPort: \_port: (S0), line:42:5, endln:42:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__mux4 (work@sky130_fd_sc_hd__mux4), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__mux4.functional.v, line:36:1, endln:62:10 + \_module_inst: work@sky130_fd_sc_hd__mux4 (work@sky130_fd_sc_hd__mux4), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__mux4.functional.v, line:36:1, endln:62:10 |vpiName:S0 |vpiDirection:1 |vpiLowConn: @@ -20371,7 +20371,7 @@ design: (work@sky130_fd_sc_hd__mux4) |vpiPort: \_port: (S1), line:43:5, endln:43:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__mux4 (work@sky130_fd_sc_hd__mux4), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__mux4.functional.v, line:36:1, endln:62:10 + \_module_inst: work@sky130_fd_sc_hd__mux4 (work@sky130_fd_sc_hd__mux4), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__mux4.functional.v, line:36:1, endln:62:10 |vpiName:S1 |vpiDirection:1 |vpiLowConn: @@ -20385,7 +20385,7 @@ design: (work@sky130_fd_sc_hd__mux4) |vpiPrimitive: \_udp: work@sky130_fd_sc_hd__udp_mux_4to2 (work@sky130_fd_sc_hd__mux4.mux_4to20), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__mux4.functional.v, line:59:5, endln:59:87 |vpiParent: - \_module: work@sky130_fd_sc_hd__mux4 (work@sky130_fd_sc_hd__mux4), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__mux4.functional.v, line:36:1, endln:62:10 + \_module_inst: work@sky130_fd_sc_hd__mux4 (work@sky130_fd_sc_hd__mux4), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__mux4.functional.v, line:36:1, endln:62:10 |vpiDefName:work@sky130_fd_sc_hd__udp_mux_4to2 |vpiName:mux_4to20 |vpiFullName:work@sky130_fd_sc_hd__mux4.mux_4to20 @@ -20394,7 +20394,7 @@ design: (work@sky130_fd_sc_hd__mux4) |vpiPrimitive: \_gate: work@buf (work@sky130_fd_sc_hd__mux4.buf0), line:60:35, endln:60:86 |vpiParent: - \_module: work@sky130_fd_sc_hd__mux4 (work@sky130_fd_sc_hd__mux4), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__mux4.functional.v, line:36:1, endln:62:10 + \_module_inst: work@sky130_fd_sc_hd__mux4 (work@sky130_fd_sc_hd__mux4), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__mux4.functional.v, line:36:1, endln:62:10 |vpiDefName:work@buf |vpiName:buf0 |vpiFullName:work@sky130_fd_sc_hd__mux4.buf0 @@ -20437,7 +20437,7 @@ Processing: -cd cells/cells -DUNIT_DELAY -writepp -parse -nocache -nobuiltin -no design: (work@sky130_fd_sc_hd__a21o) |vpiName:work@sky130_fd_sc_hd__a21o |uhdmallModules: -\_module: work@sky130_fd_sc_hd__a21o (work@sky130_fd_sc_hd__a21o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a21o.functional.v, line:35:1, endln:57:10 +\_module_inst: work@sky130_fd_sc_hd__a21o (work@sky130_fd_sc_hd__a21o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a21o.functional.v, line:35:1, endln:57:10 |vpiParent: \_design: (work@sky130_fd_sc_hd__a21o) |vpiFullName:work@sky130_fd_sc_hd__a21o @@ -20445,45 +20445,45 @@ design: (work@sky130_fd_sc_hd__a21o) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a21o.and0_out), line:49:10, endln:49:18 |vpiParent: - \_module: work@sky130_fd_sc_hd__a21o (work@sky130_fd_sc_hd__a21o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a21o.functional.v, line:35:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__a21o (work@sky130_fd_sc_hd__a21o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a21o.functional.v, line:35:1, endln:57:10 |vpiName:and0_out |vpiFullName:work@sky130_fd_sc_hd__a21o.and0_out |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a21o.or0_out_X), line:50:10, endln:50:19 |vpiParent: - \_module: work@sky130_fd_sc_hd__a21o (work@sky130_fd_sc_hd__a21o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a21o.functional.v, line:35:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__a21o (work@sky130_fd_sc_hd__a21o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a21o.functional.v, line:35:1, endln:57:10 |vpiName:or0_out_X |vpiFullName:work@sky130_fd_sc_hd__a21o.or0_out_X |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a21o.X), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__a21o (work@sky130_fd_sc_hd__a21o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a21o.functional.v, line:35:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__a21o (work@sky130_fd_sc_hd__a21o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a21o.functional.v, line:35:1, endln:57:10 |vpiName:X |vpiFullName:work@sky130_fd_sc_hd__a21o.X |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a21o.A1), line:37:5, endln:37:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a21o (work@sky130_fd_sc_hd__a21o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a21o.functional.v, line:35:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__a21o (work@sky130_fd_sc_hd__a21o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a21o.functional.v, line:35:1, endln:57:10 |vpiName:A1 |vpiFullName:work@sky130_fd_sc_hd__a21o.A1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a21o.A2), line:38:5, endln:38:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a21o (work@sky130_fd_sc_hd__a21o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a21o.functional.v, line:35:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__a21o (work@sky130_fd_sc_hd__a21o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a21o.functional.v, line:35:1, endln:57:10 |vpiName:A2 |vpiFullName:work@sky130_fd_sc_hd__a21o.A2 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a21o.B1), line:39:5, endln:39:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a21o (work@sky130_fd_sc_hd__a21o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a21o.functional.v, line:35:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__a21o (work@sky130_fd_sc_hd__a21o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a21o.functional.v, line:35:1, endln:57:10 |vpiName:B1 |vpiFullName:work@sky130_fd_sc_hd__a21o.B1 |vpiPort: \_port: (X), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__a21o (work@sky130_fd_sc_hd__a21o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a21o.functional.v, line:35:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__a21o (work@sky130_fd_sc_hd__a21o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a21o.functional.v, line:35:1, endln:57:10 |vpiName:X |vpiDirection:2 |vpiLowConn: @@ -20495,7 +20495,7 @@ design: (work@sky130_fd_sc_hd__a21o) |vpiPort: \_port: (A1), line:37:5, endln:37:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a21o (work@sky130_fd_sc_hd__a21o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a21o.functional.v, line:35:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__a21o (work@sky130_fd_sc_hd__a21o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a21o.functional.v, line:35:1, endln:57:10 |vpiName:A1 |vpiDirection:1 |vpiLowConn: @@ -20507,7 +20507,7 @@ design: (work@sky130_fd_sc_hd__a21o) |vpiPort: \_port: (A2), line:38:5, endln:38:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a21o (work@sky130_fd_sc_hd__a21o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a21o.functional.v, line:35:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__a21o (work@sky130_fd_sc_hd__a21o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a21o.functional.v, line:35:1, endln:57:10 |vpiName:A2 |vpiDirection:1 |vpiLowConn: @@ -20519,7 +20519,7 @@ design: (work@sky130_fd_sc_hd__a21o) |vpiPort: \_port: (B1), line:39:5, endln:39:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a21o (work@sky130_fd_sc_hd__a21o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a21o.functional.v, line:35:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__a21o (work@sky130_fd_sc_hd__a21o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a21o.functional.v, line:35:1, endln:57:10 |vpiName:B1 |vpiDirection:1 |vpiLowConn: @@ -20529,14 +20529,14 @@ design: (work@sky130_fd_sc_hd__a21o) |vpiTypedef: \_logic_typespec: , line:46:12, endln:46:12 |uhdmtopModules: -\_module: work@sky130_fd_sc_hd__a21o (work@sky130_fd_sc_hd__a21o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a21o.functional.v, line:35:1, endln:57:10 +\_module_inst: work@sky130_fd_sc_hd__a21o (work@sky130_fd_sc_hd__a21o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a21o.functional.v, line:35:1, endln:57:10 |vpiName:work@sky130_fd_sc_hd__a21o |vpiDefName:work@sky130_fd_sc_hd__a21o |vpiTop:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a21o.and0_out), line:49:10, endln:49:18 |vpiParent: - \_module: work@sky130_fd_sc_hd__a21o (work@sky130_fd_sc_hd__a21o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a21o.functional.v, line:35:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__a21o (work@sky130_fd_sc_hd__a21o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a21o.functional.v, line:35:1, endln:57:10 |vpiTypespec: \_logic_typespec: , line:49:5, endln:49:9 |vpiName:and0_out @@ -20545,7 +20545,7 @@ design: (work@sky130_fd_sc_hd__a21o) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a21o.or0_out_X), line:50:10, endln:50:19 |vpiParent: - \_module: work@sky130_fd_sc_hd__a21o (work@sky130_fd_sc_hd__a21o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a21o.functional.v, line:35:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__a21o (work@sky130_fd_sc_hd__a21o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a21o.functional.v, line:35:1, endln:57:10 |vpiTypespec: \_logic_typespec: , line:50:5, endln:50:9 |vpiName:or0_out_X @@ -20554,7 +20554,7 @@ design: (work@sky130_fd_sc_hd__a21o) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a21o.X), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__a21o (work@sky130_fd_sc_hd__a21o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a21o.functional.v, line:35:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__a21o (work@sky130_fd_sc_hd__a21o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a21o.functional.v, line:35:1, endln:57:10 |vpiTypespec: \_logic_typespec: , line:43:12, endln:43:12 |vpiName:X @@ -20562,7 +20562,7 @@ design: (work@sky130_fd_sc_hd__a21o) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a21o.A1), line:37:5, endln:37:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a21o (work@sky130_fd_sc_hd__a21o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a21o.functional.v, line:35:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__a21o (work@sky130_fd_sc_hd__a21o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a21o.functional.v, line:35:1, endln:57:10 |vpiTypespec: \_logic_typespec: , line:44:12, endln:44:12 |vpiName:A1 @@ -20570,7 +20570,7 @@ design: (work@sky130_fd_sc_hd__a21o) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a21o.A2), line:38:5, endln:38:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a21o (work@sky130_fd_sc_hd__a21o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a21o.functional.v, line:35:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__a21o (work@sky130_fd_sc_hd__a21o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a21o.functional.v, line:35:1, endln:57:10 |vpiTypespec: \_logic_typespec: , line:45:12, endln:45:12 |vpiName:A2 @@ -20578,7 +20578,7 @@ design: (work@sky130_fd_sc_hd__a21o) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a21o.B1), line:39:5, endln:39:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a21o (work@sky130_fd_sc_hd__a21o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a21o.functional.v, line:35:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__a21o (work@sky130_fd_sc_hd__a21o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a21o.functional.v, line:35:1, endln:57:10 |vpiTypespec: \_logic_typespec: , line:46:12, endln:46:12 |vpiName:B1 @@ -20587,7 +20587,7 @@ design: (work@sky130_fd_sc_hd__a21o) |vpiPort: \_port: (X), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__a21o (work@sky130_fd_sc_hd__a21o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a21o.functional.v, line:35:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__a21o (work@sky130_fd_sc_hd__a21o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a21o.functional.v, line:35:1, endln:57:10 |vpiName:X |vpiDirection:2 |vpiLowConn: @@ -20601,7 +20601,7 @@ design: (work@sky130_fd_sc_hd__a21o) |vpiPort: \_port: (A1), line:37:5, endln:37:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a21o (work@sky130_fd_sc_hd__a21o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a21o.functional.v, line:35:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__a21o (work@sky130_fd_sc_hd__a21o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a21o.functional.v, line:35:1, endln:57:10 |vpiName:A1 |vpiDirection:1 |vpiLowConn: @@ -20615,7 +20615,7 @@ design: (work@sky130_fd_sc_hd__a21o) |vpiPort: \_port: (A2), line:38:5, endln:38:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a21o (work@sky130_fd_sc_hd__a21o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a21o.functional.v, line:35:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__a21o (work@sky130_fd_sc_hd__a21o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a21o.functional.v, line:35:1, endln:57:10 |vpiName:A2 |vpiDirection:1 |vpiLowConn: @@ -20629,7 +20629,7 @@ design: (work@sky130_fd_sc_hd__a21o) |vpiPort: \_port: (B1), line:39:5, endln:39:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a21o (work@sky130_fd_sc_hd__a21o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a21o.functional.v, line:35:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__a21o (work@sky130_fd_sc_hd__a21o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a21o.functional.v, line:35:1, endln:57:10 |vpiName:B1 |vpiDirection:1 |vpiLowConn: @@ -20643,7 +20643,7 @@ design: (work@sky130_fd_sc_hd__a21o) |vpiPrimitive: \_gate: work@and (work@sky130_fd_sc_hd__a21o.and0), line:53:9, endln:53:42 |vpiParent: - \_module: work@sky130_fd_sc_hd__a21o (work@sky130_fd_sc_hd__a21o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a21o.functional.v, line:35:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__a21o (work@sky130_fd_sc_hd__a21o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a21o.functional.v, line:35:1, endln:57:10 |vpiDefName:work@and |vpiName:and0 |vpiFullName:work@sky130_fd_sc_hd__a21o.and0 @@ -20692,7 +20692,7 @@ design: (work@sky130_fd_sc_hd__a21o) |vpiPrimitive: \_gate: work@or (work@sky130_fd_sc_hd__a21o.or0), line:54:9, endln:54:42 |vpiParent: - \_module: work@sky130_fd_sc_hd__a21o (work@sky130_fd_sc_hd__a21o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a21o.functional.v, line:35:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__a21o (work@sky130_fd_sc_hd__a21o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a21o.functional.v, line:35:1, endln:57:10 |vpiDefName:work@or |vpiName:or0 |vpiFullName:work@sky130_fd_sc_hd__a21o.or0 @@ -20741,7 +20741,7 @@ design: (work@sky130_fd_sc_hd__a21o) |vpiPrimitive: \_gate: work@buf (work@sky130_fd_sc_hd__a21o.buf0), line:55:9, endln:55:42 |vpiParent: - \_module: work@sky130_fd_sc_hd__a21o (work@sky130_fd_sc_hd__a21o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a21o.functional.v, line:35:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__a21o (work@sky130_fd_sc_hd__a21o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a21o.functional.v, line:35:1, endln:57:10 |vpiDefName:work@buf |vpiName:buf0 |vpiFullName:work@sky130_fd_sc_hd__a21o.buf0 @@ -20784,7 +20784,7 @@ Processing: -cd cells/cells -DUNIT_DELAY -writepp -parse -nocache -nobuiltin -no design: (work@sky130_fd_sc_hd__or4) |vpiName:work@sky130_fd_sc_hd__or4 |uhdmallModules: -\_module: work@sky130_fd_sc_hd__or4 (work@sky130_fd_sc_hd__or4), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or4.functional.v, line:33:1, endln:55:10 +\_module_inst: work@sky130_fd_sc_hd__or4 (work@sky130_fd_sc_hd__or4), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or4.functional.v, line:33:1, endln:55:10 |vpiParent: \_design: (work@sky130_fd_sc_hd__or4) |vpiFullName:work@sky130_fd_sc_hd__or4 @@ -20792,44 +20792,44 @@ design: (work@sky130_fd_sc_hd__or4) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__or4.or0_out_X), line:49:10, endln:49:19 |vpiParent: - \_module: work@sky130_fd_sc_hd__or4 (work@sky130_fd_sc_hd__or4), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or4.functional.v, line:33:1, endln:55:10 + \_module_inst: work@sky130_fd_sc_hd__or4 (work@sky130_fd_sc_hd__or4), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or4.functional.v, line:33:1, endln:55:10 |vpiName:or0_out_X |vpiFullName:work@sky130_fd_sc_hd__or4.or0_out_X |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__or4.X), line:34:5, endln:34:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__or4 (work@sky130_fd_sc_hd__or4), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or4.functional.v, line:33:1, endln:55:10 + \_module_inst: work@sky130_fd_sc_hd__or4 (work@sky130_fd_sc_hd__or4), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or4.functional.v, line:33:1, endln:55:10 |vpiName:X |vpiFullName:work@sky130_fd_sc_hd__or4.X |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__or4.A), line:35:5, endln:35:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__or4 (work@sky130_fd_sc_hd__or4), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or4.functional.v, line:33:1, endln:55:10 + \_module_inst: work@sky130_fd_sc_hd__or4 (work@sky130_fd_sc_hd__or4), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or4.functional.v, line:33:1, endln:55:10 |vpiName:A |vpiFullName:work@sky130_fd_sc_hd__or4.A |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__or4.B), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__or4 (work@sky130_fd_sc_hd__or4), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or4.functional.v, line:33:1, endln:55:10 + \_module_inst: work@sky130_fd_sc_hd__or4 (work@sky130_fd_sc_hd__or4), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or4.functional.v, line:33:1, endln:55:10 |vpiName:B |vpiFullName:work@sky130_fd_sc_hd__or4.B |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__or4.C), line:37:5, endln:37:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__or4 (work@sky130_fd_sc_hd__or4), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or4.functional.v, line:33:1, endln:55:10 + \_module_inst: work@sky130_fd_sc_hd__or4 (work@sky130_fd_sc_hd__or4), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or4.functional.v, line:33:1, endln:55:10 |vpiName:C |vpiFullName:work@sky130_fd_sc_hd__or4.C |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__or4.D), line:38:5, endln:38:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__or4 (work@sky130_fd_sc_hd__or4), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or4.functional.v, line:33:1, endln:55:10 + \_module_inst: work@sky130_fd_sc_hd__or4 (work@sky130_fd_sc_hd__or4), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or4.functional.v, line:33:1, endln:55:10 |vpiName:D |vpiFullName:work@sky130_fd_sc_hd__or4.D |vpiPort: \_port: (X), line:34:5, endln:34:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__or4 (work@sky130_fd_sc_hd__or4), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or4.functional.v, line:33:1, endln:55:10 + \_module_inst: work@sky130_fd_sc_hd__or4 (work@sky130_fd_sc_hd__or4), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or4.functional.v, line:33:1, endln:55:10 |vpiName:X |vpiDirection:2 |vpiLowConn: @@ -20841,7 +20841,7 @@ design: (work@sky130_fd_sc_hd__or4) |vpiPort: \_port: (A), line:35:5, endln:35:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__or4 (work@sky130_fd_sc_hd__or4), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or4.functional.v, line:33:1, endln:55:10 + \_module_inst: work@sky130_fd_sc_hd__or4 (work@sky130_fd_sc_hd__or4), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or4.functional.v, line:33:1, endln:55:10 |vpiName:A |vpiDirection:1 |vpiLowConn: @@ -20853,7 +20853,7 @@ design: (work@sky130_fd_sc_hd__or4) |vpiPort: \_port: (B), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__or4 (work@sky130_fd_sc_hd__or4), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or4.functional.v, line:33:1, endln:55:10 + \_module_inst: work@sky130_fd_sc_hd__or4 (work@sky130_fd_sc_hd__or4), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or4.functional.v, line:33:1, endln:55:10 |vpiName:B |vpiDirection:1 |vpiLowConn: @@ -20865,7 +20865,7 @@ design: (work@sky130_fd_sc_hd__or4) |vpiPort: \_port: (C), line:37:5, endln:37:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__or4 (work@sky130_fd_sc_hd__or4), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or4.functional.v, line:33:1, endln:55:10 + \_module_inst: work@sky130_fd_sc_hd__or4 (work@sky130_fd_sc_hd__or4), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or4.functional.v, line:33:1, endln:55:10 |vpiName:C |vpiDirection:1 |vpiLowConn: @@ -20877,7 +20877,7 @@ design: (work@sky130_fd_sc_hd__or4) |vpiPort: \_port: (D), line:38:5, endln:38:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__or4 (work@sky130_fd_sc_hd__or4), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or4.functional.v, line:33:1, endln:55:10 + \_module_inst: work@sky130_fd_sc_hd__or4 (work@sky130_fd_sc_hd__or4), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or4.functional.v, line:33:1, endln:55:10 |vpiName:D |vpiDirection:1 |vpiLowConn: @@ -20887,14 +20887,14 @@ design: (work@sky130_fd_sc_hd__or4) |vpiTypedef: \_logic_typespec: , line:46:12, endln:46:12 |uhdmtopModules: -\_module: work@sky130_fd_sc_hd__or4 (work@sky130_fd_sc_hd__or4), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or4.functional.v, line:33:1, endln:55:10 +\_module_inst: work@sky130_fd_sc_hd__or4 (work@sky130_fd_sc_hd__or4), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or4.functional.v, line:33:1, endln:55:10 |vpiName:work@sky130_fd_sc_hd__or4 |vpiDefName:work@sky130_fd_sc_hd__or4 |vpiTop:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__or4.or0_out_X), line:49:10, endln:49:19 |vpiParent: - \_module: work@sky130_fd_sc_hd__or4 (work@sky130_fd_sc_hd__or4), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or4.functional.v, line:33:1, endln:55:10 + \_module_inst: work@sky130_fd_sc_hd__or4 (work@sky130_fd_sc_hd__or4), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or4.functional.v, line:33:1, endln:55:10 |vpiTypespec: \_logic_typespec: , line:49:5, endln:49:9 |vpiName:or0_out_X @@ -20903,7 +20903,7 @@ design: (work@sky130_fd_sc_hd__or4) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__or4.X), line:34:5, endln:34:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__or4 (work@sky130_fd_sc_hd__or4), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or4.functional.v, line:33:1, endln:55:10 + \_module_inst: work@sky130_fd_sc_hd__or4 (work@sky130_fd_sc_hd__or4), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or4.functional.v, line:33:1, endln:55:10 |vpiTypespec: \_logic_typespec: , line:42:12, endln:42:12 |vpiName:X @@ -20911,7 +20911,7 @@ design: (work@sky130_fd_sc_hd__or4) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__or4.A), line:35:5, endln:35:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__or4 (work@sky130_fd_sc_hd__or4), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or4.functional.v, line:33:1, endln:55:10 + \_module_inst: work@sky130_fd_sc_hd__or4 (work@sky130_fd_sc_hd__or4), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or4.functional.v, line:33:1, endln:55:10 |vpiTypespec: \_logic_typespec: , line:43:12, endln:43:12 |vpiName:A @@ -20919,7 +20919,7 @@ design: (work@sky130_fd_sc_hd__or4) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__or4.B), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__or4 (work@sky130_fd_sc_hd__or4), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or4.functional.v, line:33:1, endln:55:10 + \_module_inst: work@sky130_fd_sc_hd__or4 (work@sky130_fd_sc_hd__or4), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or4.functional.v, line:33:1, endln:55:10 |vpiTypespec: \_logic_typespec: , line:44:12, endln:44:12 |vpiName:B @@ -20927,7 +20927,7 @@ design: (work@sky130_fd_sc_hd__or4) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__or4.C), line:37:5, endln:37:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__or4 (work@sky130_fd_sc_hd__or4), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or4.functional.v, line:33:1, endln:55:10 + \_module_inst: work@sky130_fd_sc_hd__or4 (work@sky130_fd_sc_hd__or4), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or4.functional.v, line:33:1, endln:55:10 |vpiTypespec: \_logic_typespec: , line:45:12, endln:45:12 |vpiName:C @@ -20935,7 +20935,7 @@ design: (work@sky130_fd_sc_hd__or4) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__or4.D), line:38:5, endln:38:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__or4 (work@sky130_fd_sc_hd__or4), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or4.functional.v, line:33:1, endln:55:10 + \_module_inst: work@sky130_fd_sc_hd__or4 (work@sky130_fd_sc_hd__or4), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or4.functional.v, line:33:1, endln:55:10 |vpiTypespec: \_logic_typespec: , line:46:12, endln:46:12 |vpiName:D @@ -20944,7 +20944,7 @@ design: (work@sky130_fd_sc_hd__or4) |vpiPort: \_port: (X), line:34:5, endln:34:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__or4 (work@sky130_fd_sc_hd__or4), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or4.functional.v, line:33:1, endln:55:10 + \_module_inst: work@sky130_fd_sc_hd__or4 (work@sky130_fd_sc_hd__or4), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or4.functional.v, line:33:1, endln:55:10 |vpiName:X |vpiDirection:2 |vpiLowConn: @@ -20958,7 +20958,7 @@ design: (work@sky130_fd_sc_hd__or4) |vpiPort: \_port: (A), line:35:5, endln:35:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__or4 (work@sky130_fd_sc_hd__or4), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or4.functional.v, line:33:1, endln:55:10 + \_module_inst: work@sky130_fd_sc_hd__or4 (work@sky130_fd_sc_hd__or4), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or4.functional.v, line:33:1, endln:55:10 |vpiName:A |vpiDirection:1 |vpiLowConn: @@ -20972,7 +20972,7 @@ design: (work@sky130_fd_sc_hd__or4) |vpiPort: \_port: (B), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__or4 (work@sky130_fd_sc_hd__or4), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or4.functional.v, line:33:1, endln:55:10 + \_module_inst: work@sky130_fd_sc_hd__or4 (work@sky130_fd_sc_hd__or4), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or4.functional.v, line:33:1, endln:55:10 |vpiName:B |vpiDirection:1 |vpiLowConn: @@ -20986,7 +20986,7 @@ design: (work@sky130_fd_sc_hd__or4) |vpiPort: \_port: (C), line:37:5, endln:37:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__or4 (work@sky130_fd_sc_hd__or4), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or4.functional.v, line:33:1, endln:55:10 + \_module_inst: work@sky130_fd_sc_hd__or4 (work@sky130_fd_sc_hd__or4), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or4.functional.v, line:33:1, endln:55:10 |vpiName:C |vpiDirection:1 |vpiLowConn: @@ -21000,7 +21000,7 @@ design: (work@sky130_fd_sc_hd__or4) |vpiPort: \_port: (D), line:38:5, endln:38:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__or4 (work@sky130_fd_sc_hd__or4), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or4.functional.v, line:33:1, endln:55:10 + \_module_inst: work@sky130_fd_sc_hd__or4 (work@sky130_fd_sc_hd__or4), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or4.functional.v, line:33:1, endln:55:10 |vpiName:D |vpiDirection:1 |vpiLowConn: @@ -21014,7 +21014,7 @@ design: (work@sky130_fd_sc_hd__or4) |vpiPrimitive: \_gate: work@or (work@sky130_fd_sc_hd__or4.or0), line:52:9, endln:52:42 |vpiParent: - \_module: work@sky130_fd_sc_hd__or4 (work@sky130_fd_sc_hd__or4), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or4.functional.v, line:33:1, endln:55:10 + \_module_inst: work@sky130_fd_sc_hd__or4 (work@sky130_fd_sc_hd__or4), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or4.functional.v, line:33:1, endln:55:10 |vpiDefName:work@or |vpiName:or0 |vpiFullName:work@sky130_fd_sc_hd__or4.or0 @@ -21091,7 +21091,7 @@ design: (work@sky130_fd_sc_hd__or4) |vpiPrimitive: \_gate: work@buf (work@sky130_fd_sc_hd__or4.buf0), line:53:9, endln:53:42 |vpiParent: - \_module: work@sky130_fd_sc_hd__or4 (work@sky130_fd_sc_hd__or4), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or4.functional.v, line:33:1, endln:55:10 + \_module_inst: work@sky130_fd_sc_hd__or4 (work@sky130_fd_sc_hd__or4), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or4.functional.v, line:33:1, endln:55:10 |vpiDefName:work@buf |vpiName:buf0 |vpiFullName:work@sky130_fd_sc_hd__or4.buf0 @@ -21134,7 +21134,7 @@ Processing: -cd cells/cells -DUNIT_DELAY -writepp -parse -nocache -nobuiltin -no design: (work@sky130_fd_sc_hd__dlygate4sd2) |vpiName:work@sky130_fd_sc_hd__dlygate4sd2 |uhdmallModules: -\_module: work@sky130_fd_sc_hd__dlygate4sd2 (work@sky130_fd_sc_hd__dlygate4sd2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlygate4sd2.functional.v, line:33:1, endln:49:10 +\_module_inst: work@sky130_fd_sc_hd__dlygate4sd2 (work@sky130_fd_sc_hd__dlygate4sd2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlygate4sd2.functional.v, line:33:1, endln:49:10 |vpiParent: \_design: (work@sky130_fd_sc_hd__dlygate4sd2) |vpiFullName:work@sky130_fd_sc_hd__dlygate4sd2 @@ -21142,26 +21142,26 @@ design: (work@sky130_fd_sc_hd__dlygate4sd2) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__dlygate4sd2.buf0_out_X), line:43:10, endln:43:20 |vpiParent: - \_module: work@sky130_fd_sc_hd__dlygate4sd2 (work@sky130_fd_sc_hd__dlygate4sd2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlygate4sd2.functional.v, line:33:1, endln:49:10 + \_module_inst: work@sky130_fd_sc_hd__dlygate4sd2 (work@sky130_fd_sc_hd__dlygate4sd2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlygate4sd2.functional.v, line:33:1, endln:49:10 |vpiName:buf0_out_X |vpiFullName:work@sky130_fd_sc_hd__dlygate4sd2.buf0_out_X |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__dlygate4sd2.X), line:34:5, endln:34:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__dlygate4sd2 (work@sky130_fd_sc_hd__dlygate4sd2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlygate4sd2.functional.v, line:33:1, endln:49:10 + \_module_inst: work@sky130_fd_sc_hd__dlygate4sd2 (work@sky130_fd_sc_hd__dlygate4sd2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlygate4sd2.functional.v, line:33:1, endln:49:10 |vpiName:X |vpiFullName:work@sky130_fd_sc_hd__dlygate4sd2.X |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__dlygate4sd2.A), line:35:5, endln:35:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__dlygate4sd2 (work@sky130_fd_sc_hd__dlygate4sd2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlygate4sd2.functional.v, line:33:1, endln:49:10 + \_module_inst: work@sky130_fd_sc_hd__dlygate4sd2 (work@sky130_fd_sc_hd__dlygate4sd2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlygate4sd2.functional.v, line:33:1, endln:49:10 |vpiName:A |vpiFullName:work@sky130_fd_sc_hd__dlygate4sd2.A |vpiPort: \_port: (X), line:34:5, endln:34:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__dlygate4sd2 (work@sky130_fd_sc_hd__dlygate4sd2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlygate4sd2.functional.v, line:33:1, endln:49:10 + \_module_inst: work@sky130_fd_sc_hd__dlygate4sd2 (work@sky130_fd_sc_hd__dlygate4sd2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlygate4sd2.functional.v, line:33:1, endln:49:10 |vpiName:X |vpiDirection:2 |vpiLowConn: @@ -21173,7 +21173,7 @@ design: (work@sky130_fd_sc_hd__dlygate4sd2) |vpiPort: \_port: (A), line:35:5, endln:35:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__dlygate4sd2 (work@sky130_fd_sc_hd__dlygate4sd2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlygate4sd2.functional.v, line:33:1, endln:49:10 + \_module_inst: work@sky130_fd_sc_hd__dlygate4sd2 (work@sky130_fd_sc_hd__dlygate4sd2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlygate4sd2.functional.v, line:33:1, endln:49:10 |vpiName:A |vpiDirection:1 |vpiLowConn: @@ -21183,14 +21183,14 @@ design: (work@sky130_fd_sc_hd__dlygate4sd2) |vpiTypedef: \_logic_typespec: , line:40:12, endln:40:12 |uhdmtopModules: -\_module: work@sky130_fd_sc_hd__dlygate4sd2 (work@sky130_fd_sc_hd__dlygate4sd2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlygate4sd2.functional.v, line:33:1, endln:49:10 +\_module_inst: work@sky130_fd_sc_hd__dlygate4sd2 (work@sky130_fd_sc_hd__dlygate4sd2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlygate4sd2.functional.v, line:33:1, endln:49:10 |vpiName:work@sky130_fd_sc_hd__dlygate4sd2 |vpiDefName:work@sky130_fd_sc_hd__dlygate4sd2 |vpiTop:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__dlygate4sd2.buf0_out_X), line:43:10, endln:43:20 |vpiParent: - \_module: work@sky130_fd_sc_hd__dlygate4sd2 (work@sky130_fd_sc_hd__dlygate4sd2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlygate4sd2.functional.v, line:33:1, endln:49:10 + \_module_inst: work@sky130_fd_sc_hd__dlygate4sd2 (work@sky130_fd_sc_hd__dlygate4sd2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlygate4sd2.functional.v, line:33:1, endln:49:10 |vpiTypespec: \_logic_typespec: , line:43:5, endln:43:9 |vpiName:buf0_out_X @@ -21199,7 +21199,7 @@ design: (work@sky130_fd_sc_hd__dlygate4sd2) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__dlygate4sd2.X), line:34:5, endln:34:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__dlygate4sd2 (work@sky130_fd_sc_hd__dlygate4sd2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlygate4sd2.functional.v, line:33:1, endln:49:10 + \_module_inst: work@sky130_fd_sc_hd__dlygate4sd2 (work@sky130_fd_sc_hd__dlygate4sd2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlygate4sd2.functional.v, line:33:1, endln:49:10 |vpiTypespec: \_logic_typespec: , line:39:12, endln:39:12 |vpiName:X @@ -21207,7 +21207,7 @@ design: (work@sky130_fd_sc_hd__dlygate4sd2) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__dlygate4sd2.A), line:35:5, endln:35:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__dlygate4sd2 (work@sky130_fd_sc_hd__dlygate4sd2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlygate4sd2.functional.v, line:33:1, endln:49:10 + \_module_inst: work@sky130_fd_sc_hd__dlygate4sd2 (work@sky130_fd_sc_hd__dlygate4sd2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlygate4sd2.functional.v, line:33:1, endln:49:10 |vpiTypespec: \_logic_typespec: , line:40:12, endln:40:12 |vpiName:A @@ -21216,7 +21216,7 @@ design: (work@sky130_fd_sc_hd__dlygate4sd2) |vpiPort: \_port: (X), line:34:5, endln:34:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__dlygate4sd2 (work@sky130_fd_sc_hd__dlygate4sd2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlygate4sd2.functional.v, line:33:1, endln:49:10 + \_module_inst: work@sky130_fd_sc_hd__dlygate4sd2 (work@sky130_fd_sc_hd__dlygate4sd2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlygate4sd2.functional.v, line:33:1, endln:49:10 |vpiName:X |vpiDirection:2 |vpiLowConn: @@ -21230,7 +21230,7 @@ design: (work@sky130_fd_sc_hd__dlygate4sd2) |vpiPort: \_port: (A), line:35:5, endln:35:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__dlygate4sd2 (work@sky130_fd_sc_hd__dlygate4sd2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlygate4sd2.functional.v, line:33:1, endln:49:10 + \_module_inst: work@sky130_fd_sc_hd__dlygate4sd2 (work@sky130_fd_sc_hd__dlygate4sd2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlygate4sd2.functional.v, line:33:1, endln:49:10 |vpiName:A |vpiDirection:1 |vpiLowConn: @@ -21244,7 +21244,7 @@ design: (work@sky130_fd_sc_hd__dlygate4sd2) |vpiPrimitive: \_gate: work@buf (work@sky130_fd_sc_hd__dlygate4sd2.buf0), line:46:9, endln:46:43 |vpiParent: - \_module: work@sky130_fd_sc_hd__dlygate4sd2 (work@sky130_fd_sc_hd__dlygate4sd2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlygate4sd2.functional.v, line:33:1, endln:49:10 + \_module_inst: work@sky130_fd_sc_hd__dlygate4sd2 (work@sky130_fd_sc_hd__dlygate4sd2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlygate4sd2.functional.v, line:33:1, endln:49:10 |vpiDefName:work@buf |vpiName:buf0 |vpiFullName:work@sky130_fd_sc_hd__dlygate4sd2.buf0 @@ -21279,7 +21279,7 @@ design: (work@sky130_fd_sc_hd__dlygate4sd2) |vpiPrimitive: \_gate: work@buf (work@sky130_fd_sc_hd__dlygate4sd2.buf1), line:47:9, endln:47:43 |vpiParent: - \_module: work@sky130_fd_sc_hd__dlygate4sd2 (work@sky130_fd_sc_hd__dlygate4sd2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlygate4sd2.functional.v, line:33:1, endln:49:10 + \_module_inst: work@sky130_fd_sc_hd__dlygate4sd2 (work@sky130_fd_sc_hd__dlygate4sd2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlygate4sd2.functional.v, line:33:1, endln:49:10 |vpiDefName:work@buf |vpiName:buf1 |vpiFullName:work@sky130_fd_sc_hd__dlygate4sd2.buf1 @@ -21322,7 +21322,7 @@ Processing: -cd cells/cells -DUNIT_DELAY -writepp -parse -nocache -nobuiltin -no design: (work@sky130_fd_sc_hd__or3) |vpiName:work@sky130_fd_sc_hd__or3 |uhdmallModules: -\_module: work@sky130_fd_sc_hd__or3 (work@sky130_fd_sc_hd__or3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or3.functional.v, line:33:1, endln:53:10 +\_module_inst: work@sky130_fd_sc_hd__or3 (work@sky130_fd_sc_hd__or3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or3.functional.v, line:33:1, endln:53:10 |vpiParent: \_design: (work@sky130_fd_sc_hd__or3) |vpiFullName:work@sky130_fd_sc_hd__or3 @@ -21330,38 +21330,38 @@ design: (work@sky130_fd_sc_hd__or3) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__or3.or0_out_X), line:47:10, endln:47:19 |vpiParent: - \_module: work@sky130_fd_sc_hd__or3 (work@sky130_fd_sc_hd__or3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or3.functional.v, line:33:1, endln:53:10 + \_module_inst: work@sky130_fd_sc_hd__or3 (work@sky130_fd_sc_hd__or3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or3.functional.v, line:33:1, endln:53:10 |vpiName:or0_out_X |vpiFullName:work@sky130_fd_sc_hd__or3.or0_out_X |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__or3.X), line:34:5, endln:34:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__or3 (work@sky130_fd_sc_hd__or3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or3.functional.v, line:33:1, endln:53:10 + \_module_inst: work@sky130_fd_sc_hd__or3 (work@sky130_fd_sc_hd__or3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or3.functional.v, line:33:1, endln:53:10 |vpiName:X |vpiFullName:work@sky130_fd_sc_hd__or3.X |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__or3.A), line:35:5, endln:35:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__or3 (work@sky130_fd_sc_hd__or3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or3.functional.v, line:33:1, endln:53:10 + \_module_inst: work@sky130_fd_sc_hd__or3 (work@sky130_fd_sc_hd__or3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or3.functional.v, line:33:1, endln:53:10 |vpiName:A |vpiFullName:work@sky130_fd_sc_hd__or3.A |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__or3.B), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__or3 (work@sky130_fd_sc_hd__or3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or3.functional.v, line:33:1, endln:53:10 + \_module_inst: work@sky130_fd_sc_hd__or3 (work@sky130_fd_sc_hd__or3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or3.functional.v, line:33:1, endln:53:10 |vpiName:B |vpiFullName:work@sky130_fd_sc_hd__or3.B |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__or3.C), line:37:5, endln:37:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__or3 (work@sky130_fd_sc_hd__or3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or3.functional.v, line:33:1, endln:53:10 + \_module_inst: work@sky130_fd_sc_hd__or3 (work@sky130_fd_sc_hd__or3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or3.functional.v, line:33:1, endln:53:10 |vpiName:C |vpiFullName:work@sky130_fd_sc_hd__or3.C |vpiPort: \_port: (X), line:34:5, endln:34:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__or3 (work@sky130_fd_sc_hd__or3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or3.functional.v, line:33:1, endln:53:10 + \_module_inst: work@sky130_fd_sc_hd__or3 (work@sky130_fd_sc_hd__or3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or3.functional.v, line:33:1, endln:53:10 |vpiName:X |vpiDirection:2 |vpiLowConn: @@ -21373,7 +21373,7 @@ design: (work@sky130_fd_sc_hd__or3) |vpiPort: \_port: (A), line:35:5, endln:35:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__or3 (work@sky130_fd_sc_hd__or3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or3.functional.v, line:33:1, endln:53:10 + \_module_inst: work@sky130_fd_sc_hd__or3 (work@sky130_fd_sc_hd__or3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or3.functional.v, line:33:1, endln:53:10 |vpiName:A |vpiDirection:1 |vpiLowConn: @@ -21385,7 +21385,7 @@ design: (work@sky130_fd_sc_hd__or3) |vpiPort: \_port: (B), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__or3 (work@sky130_fd_sc_hd__or3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or3.functional.v, line:33:1, endln:53:10 + \_module_inst: work@sky130_fd_sc_hd__or3 (work@sky130_fd_sc_hd__or3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or3.functional.v, line:33:1, endln:53:10 |vpiName:B |vpiDirection:1 |vpiLowConn: @@ -21397,7 +21397,7 @@ design: (work@sky130_fd_sc_hd__or3) |vpiPort: \_port: (C), line:37:5, endln:37:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__or3 (work@sky130_fd_sc_hd__or3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or3.functional.v, line:33:1, endln:53:10 + \_module_inst: work@sky130_fd_sc_hd__or3 (work@sky130_fd_sc_hd__or3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or3.functional.v, line:33:1, endln:53:10 |vpiName:C |vpiDirection:1 |vpiLowConn: @@ -21407,14 +21407,14 @@ design: (work@sky130_fd_sc_hd__or3) |vpiTypedef: \_logic_typespec: , line:44:12, endln:44:12 |uhdmtopModules: -\_module: work@sky130_fd_sc_hd__or3 (work@sky130_fd_sc_hd__or3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or3.functional.v, line:33:1, endln:53:10 +\_module_inst: work@sky130_fd_sc_hd__or3 (work@sky130_fd_sc_hd__or3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or3.functional.v, line:33:1, endln:53:10 |vpiName:work@sky130_fd_sc_hd__or3 |vpiDefName:work@sky130_fd_sc_hd__or3 |vpiTop:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__or3.or0_out_X), line:47:10, endln:47:19 |vpiParent: - \_module: work@sky130_fd_sc_hd__or3 (work@sky130_fd_sc_hd__or3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or3.functional.v, line:33:1, endln:53:10 + \_module_inst: work@sky130_fd_sc_hd__or3 (work@sky130_fd_sc_hd__or3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or3.functional.v, line:33:1, endln:53:10 |vpiTypespec: \_logic_typespec: , line:47:5, endln:47:9 |vpiName:or0_out_X @@ -21423,7 +21423,7 @@ design: (work@sky130_fd_sc_hd__or3) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__or3.X), line:34:5, endln:34:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__or3 (work@sky130_fd_sc_hd__or3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or3.functional.v, line:33:1, endln:53:10 + \_module_inst: work@sky130_fd_sc_hd__or3 (work@sky130_fd_sc_hd__or3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or3.functional.v, line:33:1, endln:53:10 |vpiTypespec: \_logic_typespec: , line:41:12, endln:41:12 |vpiName:X @@ -21431,7 +21431,7 @@ design: (work@sky130_fd_sc_hd__or3) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__or3.A), line:35:5, endln:35:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__or3 (work@sky130_fd_sc_hd__or3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or3.functional.v, line:33:1, endln:53:10 + \_module_inst: work@sky130_fd_sc_hd__or3 (work@sky130_fd_sc_hd__or3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or3.functional.v, line:33:1, endln:53:10 |vpiTypespec: \_logic_typespec: , line:42:12, endln:42:12 |vpiName:A @@ -21439,7 +21439,7 @@ design: (work@sky130_fd_sc_hd__or3) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__or3.B), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__or3 (work@sky130_fd_sc_hd__or3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or3.functional.v, line:33:1, endln:53:10 + \_module_inst: work@sky130_fd_sc_hd__or3 (work@sky130_fd_sc_hd__or3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or3.functional.v, line:33:1, endln:53:10 |vpiTypespec: \_logic_typespec: , line:43:12, endln:43:12 |vpiName:B @@ -21447,7 +21447,7 @@ design: (work@sky130_fd_sc_hd__or3) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__or3.C), line:37:5, endln:37:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__or3 (work@sky130_fd_sc_hd__or3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or3.functional.v, line:33:1, endln:53:10 + \_module_inst: work@sky130_fd_sc_hd__or3 (work@sky130_fd_sc_hd__or3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or3.functional.v, line:33:1, endln:53:10 |vpiTypespec: \_logic_typespec: , line:44:12, endln:44:12 |vpiName:C @@ -21456,7 +21456,7 @@ design: (work@sky130_fd_sc_hd__or3) |vpiPort: \_port: (X), line:34:5, endln:34:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__or3 (work@sky130_fd_sc_hd__or3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or3.functional.v, line:33:1, endln:53:10 + \_module_inst: work@sky130_fd_sc_hd__or3 (work@sky130_fd_sc_hd__or3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or3.functional.v, line:33:1, endln:53:10 |vpiName:X |vpiDirection:2 |vpiLowConn: @@ -21470,7 +21470,7 @@ design: (work@sky130_fd_sc_hd__or3) |vpiPort: \_port: (A), line:35:5, endln:35:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__or3 (work@sky130_fd_sc_hd__or3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or3.functional.v, line:33:1, endln:53:10 + \_module_inst: work@sky130_fd_sc_hd__or3 (work@sky130_fd_sc_hd__or3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or3.functional.v, line:33:1, endln:53:10 |vpiName:A |vpiDirection:1 |vpiLowConn: @@ -21484,7 +21484,7 @@ design: (work@sky130_fd_sc_hd__or3) |vpiPort: \_port: (B), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__or3 (work@sky130_fd_sc_hd__or3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or3.functional.v, line:33:1, endln:53:10 + \_module_inst: work@sky130_fd_sc_hd__or3 (work@sky130_fd_sc_hd__or3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or3.functional.v, line:33:1, endln:53:10 |vpiName:B |vpiDirection:1 |vpiLowConn: @@ -21498,7 +21498,7 @@ design: (work@sky130_fd_sc_hd__or3) |vpiPort: \_port: (C), line:37:5, endln:37:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__or3 (work@sky130_fd_sc_hd__or3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or3.functional.v, line:33:1, endln:53:10 + \_module_inst: work@sky130_fd_sc_hd__or3 (work@sky130_fd_sc_hd__or3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or3.functional.v, line:33:1, endln:53:10 |vpiName:C |vpiDirection:1 |vpiLowConn: @@ -21512,7 +21512,7 @@ design: (work@sky130_fd_sc_hd__or3) |vpiPrimitive: \_gate: work@or (work@sky130_fd_sc_hd__or3.or0), line:50:9, endln:50:42 |vpiParent: - \_module: work@sky130_fd_sc_hd__or3 (work@sky130_fd_sc_hd__or3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or3.functional.v, line:33:1, endln:53:10 + \_module_inst: work@sky130_fd_sc_hd__or3 (work@sky130_fd_sc_hd__or3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or3.functional.v, line:33:1, endln:53:10 |vpiDefName:work@or |vpiName:or0 |vpiFullName:work@sky130_fd_sc_hd__or3.or0 @@ -21575,7 +21575,7 @@ design: (work@sky130_fd_sc_hd__or3) |vpiPrimitive: \_gate: work@buf (work@sky130_fd_sc_hd__or3.buf0), line:51:9, endln:51:42 |vpiParent: - \_module: work@sky130_fd_sc_hd__or3 (work@sky130_fd_sc_hd__or3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or3.functional.v, line:33:1, endln:53:10 + \_module_inst: work@sky130_fd_sc_hd__or3 (work@sky130_fd_sc_hd__or3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or3.functional.v, line:33:1, endln:53:10 |vpiDefName:work@buf |vpiName:buf0 |vpiFullName:work@sky130_fd_sc_hd__or3.buf0 @@ -21618,7 +21618,7 @@ Processing: -cd cells/cells -DUNIT_DELAY -writepp -parse -nocache -nobuiltin -no design: (work@sky130_fd_sc_hd__probe_p) |vpiName:work@sky130_fd_sc_hd__probe_p |uhdmallModules: -\_module: work@sky130_fd_sc_hd__probe_p (work@sky130_fd_sc_hd__probe_p), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__probe_p.functional.v, line:33:1, endln:49:10 +\_module_inst: work@sky130_fd_sc_hd__probe_p (work@sky130_fd_sc_hd__probe_p), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__probe_p.functional.v, line:33:1, endln:49:10 |vpiParent: \_design: (work@sky130_fd_sc_hd__probe_p) |vpiFullName:work@sky130_fd_sc_hd__probe_p @@ -21626,26 +21626,26 @@ design: (work@sky130_fd_sc_hd__probe_p) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__probe_p.buf0_out_X), line:43:10, endln:43:20 |vpiParent: - \_module: work@sky130_fd_sc_hd__probe_p (work@sky130_fd_sc_hd__probe_p), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__probe_p.functional.v, line:33:1, endln:49:10 + \_module_inst: work@sky130_fd_sc_hd__probe_p (work@sky130_fd_sc_hd__probe_p), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__probe_p.functional.v, line:33:1, endln:49:10 |vpiName:buf0_out_X |vpiFullName:work@sky130_fd_sc_hd__probe_p.buf0_out_X |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__probe_p.X), line:34:5, endln:34:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__probe_p (work@sky130_fd_sc_hd__probe_p), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__probe_p.functional.v, line:33:1, endln:49:10 + \_module_inst: work@sky130_fd_sc_hd__probe_p (work@sky130_fd_sc_hd__probe_p), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__probe_p.functional.v, line:33:1, endln:49:10 |vpiName:X |vpiFullName:work@sky130_fd_sc_hd__probe_p.X |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__probe_p.A), line:35:5, endln:35:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__probe_p (work@sky130_fd_sc_hd__probe_p), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__probe_p.functional.v, line:33:1, endln:49:10 + \_module_inst: work@sky130_fd_sc_hd__probe_p (work@sky130_fd_sc_hd__probe_p), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__probe_p.functional.v, line:33:1, endln:49:10 |vpiName:A |vpiFullName:work@sky130_fd_sc_hd__probe_p.A |vpiPort: \_port: (X), line:34:5, endln:34:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__probe_p (work@sky130_fd_sc_hd__probe_p), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__probe_p.functional.v, line:33:1, endln:49:10 + \_module_inst: work@sky130_fd_sc_hd__probe_p (work@sky130_fd_sc_hd__probe_p), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__probe_p.functional.v, line:33:1, endln:49:10 |vpiName:X |vpiDirection:2 |vpiLowConn: @@ -21657,7 +21657,7 @@ design: (work@sky130_fd_sc_hd__probe_p) |vpiPort: \_port: (A), line:35:5, endln:35:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__probe_p (work@sky130_fd_sc_hd__probe_p), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__probe_p.functional.v, line:33:1, endln:49:10 + \_module_inst: work@sky130_fd_sc_hd__probe_p (work@sky130_fd_sc_hd__probe_p), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__probe_p.functional.v, line:33:1, endln:49:10 |vpiName:A |vpiDirection:1 |vpiLowConn: @@ -21667,14 +21667,14 @@ design: (work@sky130_fd_sc_hd__probe_p) |vpiTypedef: \_logic_typespec: , line:40:12, endln:40:12 |uhdmtopModules: -\_module: work@sky130_fd_sc_hd__probe_p (work@sky130_fd_sc_hd__probe_p), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__probe_p.functional.v, line:33:1, endln:49:10 +\_module_inst: work@sky130_fd_sc_hd__probe_p (work@sky130_fd_sc_hd__probe_p), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__probe_p.functional.v, line:33:1, endln:49:10 |vpiName:work@sky130_fd_sc_hd__probe_p |vpiDefName:work@sky130_fd_sc_hd__probe_p |vpiTop:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__probe_p.buf0_out_X), line:43:10, endln:43:20 |vpiParent: - \_module: work@sky130_fd_sc_hd__probe_p (work@sky130_fd_sc_hd__probe_p), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__probe_p.functional.v, line:33:1, endln:49:10 + \_module_inst: work@sky130_fd_sc_hd__probe_p (work@sky130_fd_sc_hd__probe_p), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__probe_p.functional.v, line:33:1, endln:49:10 |vpiTypespec: \_logic_typespec: , line:43:5, endln:43:9 |vpiName:buf0_out_X @@ -21683,7 +21683,7 @@ design: (work@sky130_fd_sc_hd__probe_p) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__probe_p.X), line:34:5, endln:34:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__probe_p (work@sky130_fd_sc_hd__probe_p), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__probe_p.functional.v, line:33:1, endln:49:10 + \_module_inst: work@sky130_fd_sc_hd__probe_p (work@sky130_fd_sc_hd__probe_p), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__probe_p.functional.v, line:33:1, endln:49:10 |vpiTypespec: \_logic_typespec: , line:39:12, endln:39:12 |vpiName:X @@ -21691,7 +21691,7 @@ design: (work@sky130_fd_sc_hd__probe_p) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__probe_p.A), line:35:5, endln:35:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__probe_p (work@sky130_fd_sc_hd__probe_p), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__probe_p.functional.v, line:33:1, endln:49:10 + \_module_inst: work@sky130_fd_sc_hd__probe_p (work@sky130_fd_sc_hd__probe_p), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__probe_p.functional.v, line:33:1, endln:49:10 |vpiTypespec: \_logic_typespec: , line:40:12, endln:40:12 |vpiName:A @@ -21700,7 +21700,7 @@ design: (work@sky130_fd_sc_hd__probe_p) |vpiPort: \_port: (X), line:34:5, endln:34:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__probe_p (work@sky130_fd_sc_hd__probe_p), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__probe_p.functional.v, line:33:1, endln:49:10 + \_module_inst: work@sky130_fd_sc_hd__probe_p (work@sky130_fd_sc_hd__probe_p), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__probe_p.functional.v, line:33:1, endln:49:10 |vpiName:X |vpiDirection:2 |vpiLowConn: @@ -21714,7 +21714,7 @@ design: (work@sky130_fd_sc_hd__probe_p) |vpiPort: \_port: (A), line:35:5, endln:35:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__probe_p (work@sky130_fd_sc_hd__probe_p), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__probe_p.functional.v, line:33:1, endln:49:10 + \_module_inst: work@sky130_fd_sc_hd__probe_p (work@sky130_fd_sc_hd__probe_p), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__probe_p.functional.v, line:33:1, endln:49:10 |vpiName:A |vpiDirection:1 |vpiLowConn: @@ -21728,7 +21728,7 @@ design: (work@sky130_fd_sc_hd__probe_p) |vpiPrimitive: \_gate: work@buf (work@sky130_fd_sc_hd__probe_p.buf0), line:46:9, endln:46:43 |vpiParent: - \_module: work@sky130_fd_sc_hd__probe_p (work@sky130_fd_sc_hd__probe_p), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__probe_p.functional.v, line:33:1, endln:49:10 + \_module_inst: work@sky130_fd_sc_hd__probe_p (work@sky130_fd_sc_hd__probe_p), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__probe_p.functional.v, line:33:1, endln:49:10 |vpiDefName:work@buf |vpiName:buf0 |vpiFullName:work@sky130_fd_sc_hd__probe_p.buf0 @@ -21763,7 +21763,7 @@ design: (work@sky130_fd_sc_hd__probe_p) |vpiPrimitive: \_gate: work@buf (work@sky130_fd_sc_hd__probe_p.buf1), line:47:9, endln:47:43 |vpiParent: - \_module: work@sky130_fd_sc_hd__probe_p (work@sky130_fd_sc_hd__probe_p), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__probe_p.functional.v, line:33:1, endln:49:10 + \_module_inst: work@sky130_fd_sc_hd__probe_p (work@sky130_fd_sc_hd__probe_p), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__probe_p.functional.v, line:33:1, endln:49:10 |vpiDefName:work@buf |vpiName:buf1 |vpiFullName:work@sky130_fd_sc_hd__probe_p.buf1 @@ -21806,7 +21806,7 @@ Processing: -cd cells/cells -DUNIT_DELAY -writepp -parse -nocache -nobuiltin -no design: (work@sky130_fd_sc_hd__fahcin) |vpiName:work@sky130_fd_sc_hd__fahcin |uhdmallModules: -\_module: work@sky130_fd_sc_hd__fahcin (work@sky130_fd_sc_hd__fahcin), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fahcin.functional.v, line:33:1, endln:66:10 +\_module_inst: work@sky130_fd_sc_hd__fahcin (work@sky130_fd_sc_hd__fahcin), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fahcin.functional.v, line:33:1, endln:66:10 |vpiParent: \_design: (work@sky130_fd_sc_hd__fahcin) |vpiFullName:work@sky130_fd_sc_hd__fahcin @@ -21814,79 +21814,79 @@ design: (work@sky130_fd_sc_hd__fahcin) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__fahcin.ci), line:49:10, endln:49:12 |vpiParent: - \_module: work@sky130_fd_sc_hd__fahcin (work@sky130_fd_sc_hd__fahcin), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fahcin.functional.v, line:33:1, endln:66:10 + \_module_inst: work@sky130_fd_sc_hd__fahcin (work@sky130_fd_sc_hd__fahcin), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fahcin.functional.v, line:33:1, endln:66:10 |vpiName:ci |vpiFullName:work@sky130_fd_sc_hd__fahcin.ci |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__fahcin.xor0_out_SUM), line:50:10, endln:50:22 |vpiParent: - \_module: work@sky130_fd_sc_hd__fahcin (work@sky130_fd_sc_hd__fahcin), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fahcin.functional.v, line:33:1, endln:66:10 + \_module_inst: work@sky130_fd_sc_hd__fahcin (work@sky130_fd_sc_hd__fahcin), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fahcin.functional.v, line:33:1, endln:66:10 |vpiName:xor0_out_SUM |vpiFullName:work@sky130_fd_sc_hd__fahcin.xor0_out_SUM |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__fahcin.a_b), line:51:10, endln:51:13 |vpiParent: - \_module: work@sky130_fd_sc_hd__fahcin (work@sky130_fd_sc_hd__fahcin), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fahcin.functional.v, line:33:1, endln:66:10 + \_module_inst: work@sky130_fd_sc_hd__fahcin (work@sky130_fd_sc_hd__fahcin), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fahcin.functional.v, line:33:1, endln:66:10 |vpiName:a_b |vpiFullName:work@sky130_fd_sc_hd__fahcin.a_b |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__fahcin.a_ci), line:52:10, endln:52:14 |vpiParent: - \_module: work@sky130_fd_sc_hd__fahcin (work@sky130_fd_sc_hd__fahcin), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fahcin.functional.v, line:33:1, endln:66:10 + \_module_inst: work@sky130_fd_sc_hd__fahcin (work@sky130_fd_sc_hd__fahcin), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fahcin.functional.v, line:33:1, endln:66:10 |vpiName:a_ci |vpiFullName:work@sky130_fd_sc_hd__fahcin.a_ci |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__fahcin.b_ci), line:53:10, endln:53:14 |vpiParent: - \_module: work@sky130_fd_sc_hd__fahcin (work@sky130_fd_sc_hd__fahcin), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fahcin.functional.v, line:33:1, endln:66:10 + \_module_inst: work@sky130_fd_sc_hd__fahcin (work@sky130_fd_sc_hd__fahcin), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fahcin.functional.v, line:33:1, endln:66:10 |vpiName:b_ci |vpiFullName:work@sky130_fd_sc_hd__fahcin.b_ci |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__fahcin.or0_out_COUT), line:54:10, endln:54:22 |vpiParent: - \_module: work@sky130_fd_sc_hd__fahcin (work@sky130_fd_sc_hd__fahcin), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fahcin.functional.v, line:33:1, endln:66:10 + \_module_inst: work@sky130_fd_sc_hd__fahcin (work@sky130_fd_sc_hd__fahcin), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fahcin.functional.v, line:33:1, endln:66:10 |vpiName:or0_out_COUT |vpiFullName:work@sky130_fd_sc_hd__fahcin.or0_out_COUT |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__fahcin.COUT), line:34:5, endln:34:9 |vpiParent: - \_module: work@sky130_fd_sc_hd__fahcin (work@sky130_fd_sc_hd__fahcin), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fahcin.functional.v, line:33:1, endln:66:10 + \_module_inst: work@sky130_fd_sc_hd__fahcin (work@sky130_fd_sc_hd__fahcin), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fahcin.functional.v, line:33:1, endln:66:10 |vpiName:COUT |vpiFullName:work@sky130_fd_sc_hd__fahcin.COUT |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__fahcin.SUM), line:35:5, endln:35:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__fahcin (work@sky130_fd_sc_hd__fahcin), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fahcin.functional.v, line:33:1, endln:66:10 + \_module_inst: work@sky130_fd_sc_hd__fahcin (work@sky130_fd_sc_hd__fahcin), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fahcin.functional.v, line:33:1, endln:66:10 |vpiName:SUM |vpiFullName:work@sky130_fd_sc_hd__fahcin.SUM |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__fahcin.A), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__fahcin (work@sky130_fd_sc_hd__fahcin), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fahcin.functional.v, line:33:1, endln:66:10 + \_module_inst: work@sky130_fd_sc_hd__fahcin (work@sky130_fd_sc_hd__fahcin), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fahcin.functional.v, line:33:1, endln:66:10 |vpiName:A |vpiFullName:work@sky130_fd_sc_hd__fahcin.A |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__fahcin.B), line:37:5, endln:37:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__fahcin (work@sky130_fd_sc_hd__fahcin), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fahcin.functional.v, line:33:1, endln:66:10 + \_module_inst: work@sky130_fd_sc_hd__fahcin (work@sky130_fd_sc_hd__fahcin), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fahcin.functional.v, line:33:1, endln:66:10 |vpiName:B |vpiFullName:work@sky130_fd_sc_hd__fahcin.B |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__fahcin.CIN), line:38:5, endln:38:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__fahcin (work@sky130_fd_sc_hd__fahcin), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fahcin.functional.v, line:33:1, endln:66:10 + \_module_inst: work@sky130_fd_sc_hd__fahcin (work@sky130_fd_sc_hd__fahcin), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fahcin.functional.v, line:33:1, endln:66:10 |vpiName:CIN |vpiFullName:work@sky130_fd_sc_hd__fahcin.CIN |vpiPort: \_port: (COUT), line:34:5, endln:34:9 |vpiParent: - \_module: work@sky130_fd_sc_hd__fahcin (work@sky130_fd_sc_hd__fahcin), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fahcin.functional.v, line:33:1, endln:66:10 + \_module_inst: work@sky130_fd_sc_hd__fahcin (work@sky130_fd_sc_hd__fahcin), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fahcin.functional.v, line:33:1, endln:66:10 |vpiName:COUT |vpiDirection:2 |vpiLowConn: @@ -21898,7 +21898,7 @@ design: (work@sky130_fd_sc_hd__fahcin) |vpiPort: \_port: (SUM), line:35:5, endln:35:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__fahcin (work@sky130_fd_sc_hd__fahcin), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fahcin.functional.v, line:33:1, endln:66:10 + \_module_inst: work@sky130_fd_sc_hd__fahcin (work@sky130_fd_sc_hd__fahcin), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fahcin.functional.v, line:33:1, endln:66:10 |vpiName:SUM |vpiDirection:2 |vpiLowConn: @@ -21910,7 +21910,7 @@ design: (work@sky130_fd_sc_hd__fahcin) |vpiPort: \_port: (A), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__fahcin (work@sky130_fd_sc_hd__fahcin), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fahcin.functional.v, line:33:1, endln:66:10 + \_module_inst: work@sky130_fd_sc_hd__fahcin (work@sky130_fd_sc_hd__fahcin), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fahcin.functional.v, line:33:1, endln:66:10 |vpiName:A |vpiDirection:1 |vpiLowConn: @@ -21922,7 +21922,7 @@ design: (work@sky130_fd_sc_hd__fahcin) |vpiPort: \_port: (B), line:37:5, endln:37:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__fahcin (work@sky130_fd_sc_hd__fahcin), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fahcin.functional.v, line:33:1, endln:66:10 + \_module_inst: work@sky130_fd_sc_hd__fahcin (work@sky130_fd_sc_hd__fahcin), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fahcin.functional.v, line:33:1, endln:66:10 |vpiName:B |vpiDirection:1 |vpiLowConn: @@ -21934,7 +21934,7 @@ design: (work@sky130_fd_sc_hd__fahcin) |vpiPort: \_port: (CIN), line:38:5, endln:38:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__fahcin (work@sky130_fd_sc_hd__fahcin), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fahcin.functional.v, line:33:1, endln:66:10 + \_module_inst: work@sky130_fd_sc_hd__fahcin (work@sky130_fd_sc_hd__fahcin), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fahcin.functional.v, line:33:1, endln:66:10 |vpiName:CIN |vpiDirection:1 |vpiLowConn: @@ -21944,14 +21944,14 @@ design: (work@sky130_fd_sc_hd__fahcin) |vpiTypedef: \_logic_typespec: , line:46:12, endln:46:12 |uhdmtopModules: -\_module: work@sky130_fd_sc_hd__fahcin (work@sky130_fd_sc_hd__fahcin), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fahcin.functional.v, line:33:1, endln:66:10 +\_module_inst: work@sky130_fd_sc_hd__fahcin (work@sky130_fd_sc_hd__fahcin), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fahcin.functional.v, line:33:1, endln:66:10 |vpiName:work@sky130_fd_sc_hd__fahcin |vpiDefName:work@sky130_fd_sc_hd__fahcin |vpiTop:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__fahcin.ci), line:49:10, endln:49:12 |vpiParent: - \_module: work@sky130_fd_sc_hd__fahcin (work@sky130_fd_sc_hd__fahcin), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fahcin.functional.v, line:33:1, endln:66:10 + \_module_inst: work@sky130_fd_sc_hd__fahcin (work@sky130_fd_sc_hd__fahcin), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fahcin.functional.v, line:33:1, endln:66:10 |vpiTypespec: \_logic_typespec: , line:49:5, endln:49:9 |vpiName:ci @@ -21960,7 +21960,7 @@ design: (work@sky130_fd_sc_hd__fahcin) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__fahcin.xor0_out_SUM), line:50:10, endln:50:22 |vpiParent: - \_module: work@sky130_fd_sc_hd__fahcin (work@sky130_fd_sc_hd__fahcin), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fahcin.functional.v, line:33:1, endln:66:10 + \_module_inst: work@sky130_fd_sc_hd__fahcin (work@sky130_fd_sc_hd__fahcin), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fahcin.functional.v, line:33:1, endln:66:10 |vpiTypespec: \_logic_typespec: , line:50:5, endln:50:9 |vpiName:xor0_out_SUM @@ -21969,7 +21969,7 @@ design: (work@sky130_fd_sc_hd__fahcin) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__fahcin.a_b), line:51:10, endln:51:13 |vpiParent: - \_module: work@sky130_fd_sc_hd__fahcin (work@sky130_fd_sc_hd__fahcin), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fahcin.functional.v, line:33:1, endln:66:10 + \_module_inst: work@sky130_fd_sc_hd__fahcin (work@sky130_fd_sc_hd__fahcin), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fahcin.functional.v, line:33:1, endln:66:10 |vpiTypespec: \_logic_typespec: , line:51:5, endln:51:9 |vpiName:a_b @@ -21978,7 +21978,7 @@ design: (work@sky130_fd_sc_hd__fahcin) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__fahcin.a_ci), line:52:10, endln:52:14 |vpiParent: - \_module: work@sky130_fd_sc_hd__fahcin (work@sky130_fd_sc_hd__fahcin), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fahcin.functional.v, line:33:1, endln:66:10 + \_module_inst: work@sky130_fd_sc_hd__fahcin (work@sky130_fd_sc_hd__fahcin), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fahcin.functional.v, line:33:1, endln:66:10 |vpiTypespec: \_logic_typespec: , line:52:5, endln:52:9 |vpiName:a_ci @@ -21987,7 +21987,7 @@ design: (work@sky130_fd_sc_hd__fahcin) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__fahcin.b_ci), line:53:10, endln:53:14 |vpiParent: - \_module: work@sky130_fd_sc_hd__fahcin (work@sky130_fd_sc_hd__fahcin), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fahcin.functional.v, line:33:1, endln:66:10 + \_module_inst: work@sky130_fd_sc_hd__fahcin (work@sky130_fd_sc_hd__fahcin), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fahcin.functional.v, line:33:1, endln:66:10 |vpiTypespec: \_logic_typespec: , line:53:5, endln:53:9 |vpiName:b_ci @@ -21996,7 +21996,7 @@ design: (work@sky130_fd_sc_hd__fahcin) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__fahcin.or0_out_COUT), line:54:10, endln:54:22 |vpiParent: - \_module: work@sky130_fd_sc_hd__fahcin (work@sky130_fd_sc_hd__fahcin), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fahcin.functional.v, line:33:1, endln:66:10 + \_module_inst: work@sky130_fd_sc_hd__fahcin (work@sky130_fd_sc_hd__fahcin), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fahcin.functional.v, line:33:1, endln:66:10 |vpiTypespec: \_logic_typespec: , line:54:5, endln:54:9 |vpiName:or0_out_COUT @@ -22005,7 +22005,7 @@ design: (work@sky130_fd_sc_hd__fahcin) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__fahcin.COUT), line:34:5, endln:34:9 |vpiParent: - \_module: work@sky130_fd_sc_hd__fahcin (work@sky130_fd_sc_hd__fahcin), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fahcin.functional.v, line:33:1, endln:66:10 + \_module_inst: work@sky130_fd_sc_hd__fahcin (work@sky130_fd_sc_hd__fahcin), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fahcin.functional.v, line:33:1, endln:66:10 |vpiTypespec: \_logic_typespec: , line:42:12, endln:42:12 |vpiName:COUT @@ -22013,7 +22013,7 @@ design: (work@sky130_fd_sc_hd__fahcin) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__fahcin.SUM), line:35:5, endln:35:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__fahcin (work@sky130_fd_sc_hd__fahcin), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fahcin.functional.v, line:33:1, endln:66:10 + \_module_inst: work@sky130_fd_sc_hd__fahcin (work@sky130_fd_sc_hd__fahcin), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fahcin.functional.v, line:33:1, endln:66:10 |vpiTypespec: \_logic_typespec: , line:43:12, endln:43:12 |vpiName:SUM @@ -22021,7 +22021,7 @@ design: (work@sky130_fd_sc_hd__fahcin) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__fahcin.A), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__fahcin (work@sky130_fd_sc_hd__fahcin), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fahcin.functional.v, line:33:1, endln:66:10 + \_module_inst: work@sky130_fd_sc_hd__fahcin (work@sky130_fd_sc_hd__fahcin), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fahcin.functional.v, line:33:1, endln:66:10 |vpiTypespec: \_logic_typespec: , line:44:12, endln:44:12 |vpiName:A @@ -22029,7 +22029,7 @@ design: (work@sky130_fd_sc_hd__fahcin) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__fahcin.B), line:37:5, endln:37:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__fahcin (work@sky130_fd_sc_hd__fahcin), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fahcin.functional.v, line:33:1, endln:66:10 + \_module_inst: work@sky130_fd_sc_hd__fahcin (work@sky130_fd_sc_hd__fahcin), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fahcin.functional.v, line:33:1, endln:66:10 |vpiTypespec: \_logic_typespec: , line:45:12, endln:45:12 |vpiName:B @@ -22037,7 +22037,7 @@ design: (work@sky130_fd_sc_hd__fahcin) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__fahcin.CIN), line:38:5, endln:38:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__fahcin (work@sky130_fd_sc_hd__fahcin), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fahcin.functional.v, line:33:1, endln:66:10 + \_module_inst: work@sky130_fd_sc_hd__fahcin (work@sky130_fd_sc_hd__fahcin), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fahcin.functional.v, line:33:1, endln:66:10 |vpiTypespec: \_logic_typespec: , line:46:12, endln:46:12 |vpiName:CIN @@ -22046,7 +22046,7 @@ design: (work@sky130_fd_sc_hd__fahcin) |vpiPort: \_port: (COUT), line:34:5, endln:34:9 |vpiParent: - \_module: work@sky130_fd_sc_hd__fahcin (work@sky130_fd_sc_hd__fahcin), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fahcin.functional.v, line:33:1, endln:66:10 + \_module_inst: work@sky130_fd_sc_hd__fahcin (work@sky130_fd_sc_hd__fahcin), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fahcin.functional.v, line:33:1, endln:66:10 |vpiName:COUT |vpiDirection:2 |vpiLowConn: @@ -22060,7 +22060,7 @@ design: (work@sky130_fd_sc_hd__fahcin) |vpiPort: \_port: (SUM), line:35:5, endln:35:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__fahcin (work@sky130_fd_sc_hd__fahcin), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fahcin.functional.v, line:33:1, endln:66:10 + \_module_inst: work@sky130_fd_sc_hd__fahcin (work@sky130_fd_sc_hd__fahcin), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fahcin.functional.v, line:33:1, endln:66:10 |vpiName:SUM |vpiDirection:2 |vpiLowConn: @@ -22074,7 +22074,7 @@ design: (work@sky130_fd_sc_hd__fahcin) |vpiPort: \_port: (A), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__fahcin (work@sky130_fd_sc_hd__fahcin), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fahcin.functional.v, line:33:1, endln:66:10 + \_module_inst: work@sky130_fd_sc_hd__fahcin (work@sky130_fd_sc_hd__fahcin), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fahcin.functional.v, line:33:1, endln:66:10 |vpiName:A |vpiDirection:1 |vpiLowConn: @@ -22088,7 +22088,7 @@ design: (work@sky130_fd_sc_hd__fahcin) |vpiPort: \_port: (B), line:37:5, endln:37:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__fahcin (work@sky130_fd_sc_hd__fahcin), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fahcin.functional.v, line:33:1, endln:66:10 + \_module_inst: work@sky130_fd_sc_hd__fahcin (work@sky130_fd_sc_hd__fahcin), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fahcin.functional.v, line:33:1, endln:66:10 |vpiName:B |vpiDirection:1 |vpiLowConn: @@ -22102,7 +22102,7 @@ design: (work@sky130_fd_sc_hd__fahcin) |vpiPort: \_port: (CIN), line:38:5, endln:38:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__fahcin (work@sky130_fd_sc_hd__fahcin), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fahcin.functional.v, line:33:1, endln:66:10 + \_module_inst: work@sky130_fd_sc_hd__fahcin (work@sky130_fd_sc_hd__fahcin), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fahcin.functional.v, line:33:1, endln:66:10 |vpiName:CIN |vpiDirection:1 |vpiLowConn: @@ -22116,7 +22116,7 @@ design: (work@sky130_fd_sc_hd__fahcin) |vpiPrimitive: \_gate: work@not (work@sky130_fd_sc_hd__fahcin.not0), line:57:9, endln:57:45 |vpiParent: - \_module: work@sky130_fd_sc_hd__fahcin (work@sky130_fd_sc_hd__fahcin), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fahcin.functional.v, line:33:1, endln:66:10 + \_module_inst: work@sky130_fd_sc_hd__fahcin (work@sky130_fd_sc_hd__fahcin), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fahcin.functional.v, line:33:1, endln:66:10 |vpiDefName:work@not |vpiName:not0 |vpiFullName:work@sky130_fd_sc_hd__fahcin.not0 @@ -22151,7 +22151,7 @@ design: (work@sky130_fd_sc_hd__fahcin) |vpiPrimitive: \_gate: work@xor (work@sky130_fd_sc_hd__fahcin.xor0), line:58:9, endln:58:45 |vpiParent: - \_module: work@sky130_fd_sc_hd__fahcin (work@sky130_fd_sc_hd__fahcin), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fahcin.functional.v, line:33:1, endln:66:10 + \_module_inst: work@sky130_fd_sc_hd__fahcin (work@sky130_fd_sc_hd__fahcin), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fahcin.functional.v, line:33:1, endln:66:10 |vpiDefName:work@xor |vpiName:xor0 |vpiFullName:work@sky130_fd_sc_hd__fahcin.xor0 @@ -22214,7 +22214,7 @@ design: (work@sky130_fd_sc_hd__fahcin) |vpiPrimitive: \_gate: work@buf (work@sky130_fd_sc_hd__fahcin.buf0), line:59:9, endln:59:45 |vpiParent: - \_module: work@sky130_fd_sc_hd__fahcin (work@sky130_fd_sc_hd__fahcin), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fahcin.functional.v, line:33:1, endln:66:10 + \_module_inst: work@sky130_fd_sc_hd__fahcin (work@sky130_fd_sc_hd__fahcin), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fahcin.functional.v, line:33:1, endln:66:10 |vpiDefName:work@buf |vpiName:buf0 |vpiFullName:work@sky130_fd_sc_hd__fahcin.buf0 @@ -22249,7 +22249,7 @@ design: (work@sky130_fd_sc_hd__fahcin) |vpiPrimitive: \_gate: work@and (work@sky130_fd_sc_hd__fahcin.and0), line:60:9, endln:60:45 |vpiParent: - \_module: work@sky130_fd_sc_hd__fahcin (work@sky130_fd_sc_hd__fahcin), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fahcin.functional.v, line:33:1, endln:66:10 + \_module_inst: work@sky130_fd_sc_hd__fahcin (work@sky130_fd_sc_hd__fahcin), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fahcin.functional.v, line:33:1, endln:66:10 |vpiDefName:work@and |vpiName:and0 |vpiFullName:work@sky130_fd_sc_hd__fahcin.and0 @@ -22298,7 +22298,7 @@ design: (work@sky130_fd_sc_hd__fahcin) |vpiPrimitive: \_gate: work@and (work@sky130_fd_sc_hd__fahcin.and1), line:61:9, endln:61:45 |vpiParent: - \_module: work@sky130_fd_sc_hd__fahcin (work@sky130_fd_sc_hd__fahcin), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fahcin.functional.v, line:33:1, endln:66:10 + \_module_inst: work@sky130_fd_sc_hd__fahcin (work@sky130_fd_sc_hd__fahcin), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fahcin.functional.v, line:33:1, endln:66:10 |vpiDefName:work@and |vpiName:and1 |vpiFullName:work@sky130_fd_sc_hd__fahcin.and1 @@ -22347,7 +22347,7 @@ design: (work@sky130_fd_sc_hd__fahcin) |vpiPrimitive: \_gate: work@and (work@sky130_fd_sc_hd__fahcin.and2), line:62:9, endln:62:45 |vpiParent: - \_module: work@sky130_fd_sc_hd__fahcin (work@sky130_fd_sc_hd__fahcin), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fahcin.functional.v, line:33:1, endln:66:10 + \_module_inst: work@sky130_fd_sc_hd__fahcin (work@sky130_fd_sc_hd__fahcin), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fahcin.functional.v, line:33:1, endln:66:10 |vpiDefName:work@and |vpiName:and2 |vpiFullName:work@sky130_fd_sc_hd__fahcin.and2 @@ -22396,7 +22396,7 @@ design: (work@sky130_fd_sc_hd__fahcin) |vpiPrimitive: \_gate: work@or (work@sky130_fd_sc_hd__fahcin.or0), line:63:9, endln:63:45 |vpiParent: - \_module: work@sky130_fd_sc_hd__fahcin (work@sky130_fd_sc_hd__fahcin), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fahcin.functional.v, line:33:1, endln:66:10 + \_module_inst: work@sky130_fd_sc_hd__fahcin (work@sky130_fd_sc_hd__fahcin), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fahcin.functional.v, line:33:1, endln:66:10 |vpiDefName:work@or |vpiName:or0 |vpiFullName:work@sky130_fd_sc_hd__fahcin.or0 @@ -22459,7 +22459,7 @@ design: (work@sky130_fd_sc_hd__fahcin) |vpiPrimitive: \_gate: work@buf (work@sky130_fd_sc_hd__fahcin.buf1), line:64:9, endln:64:45 |vpiParent: - \_module: work@sky130_fd_sc_hd__fahcin (work@sky130_fd_sc_hd__fahcin), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fahcin.functional.v, line:33:1, endln:66:10 + \_module_inst: work@sky130_fd_sc_hd__fahcin (work@sky130_fd_sc_hd__fahcin), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fahcin.functional.v, line:33:1, endln:66:10 |vpiDefName:work@buf |vpiName:buf1 |vpiFullName:work@sky130_fd_sc_hd__fahcin.buf1 @@ -22502,7 +22502,7 @@ Processing: -cd cells/cells -DUNIT_DELAY -writepp -parse -nocache -nobuiltin -no design: (work@sky130_fd_sc_hd__a2111oi) |vpiName:work@sky130_fd_sc_hd__a2111oi |uhdmallModules: -\_module: work@sky130_fd_sc_hd__a2111oi (work@sky130_fd_sc_hd__a2111oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a2111oi.functional.v, line:35:1, endln:61:10 +\_module_inst: work@sky130_fd_sc_hd__a2111oi (work@sky130_fd_sc_hd__a2111oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a2111oi.functional.v, line:35:1, endln:61:10 |vpiParent: \_design: (work@sky130_fd_sc_hd__a2111oi) |vpiFullName:work@sky130_fd_sc_hd__a2111oi @@ -22510,57 +22510,57 @@ design: (work@sky130_fd_sc_hd__a2111oi) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a2111oi.and0_out), line:53:10, endln:53:18 |vpiParent: - \_module: work@sky130_fd_sc_hd__a2111oi (work@sky130_fd_sc_hd__a2111oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a2111oi.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__a2111oi (work@sky130_fd_sc_hd__a2111oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a2111oi.functional.v, line:35:1, endln:61:10 |vpiName:and0_out |vpiFullName:work@sky130_fd_sc_hd__a2111oi.and0_out |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a2111oi.nor0_out_Y), line:54:10, endln:54:20 |vpiParent: - \_module: work@sky130_fd_sc_hd__a2111oi (work@sky130_fd_sc_hd__a2111oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a2111oi.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__a2111oi (work@sky130_fd_sc_hd__a2111oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a2111oi.functional.v, line:35:1, endln:61:10 |vpiName:nor0_out_Y |vpiFullName:work@sky130_fd_sc_hd__a2111oi.nor0_out_Y |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a2111oi.Y), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__a2111oi (work@sky130_fd_sc_hd__a2111oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a2111oi.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__a2111oi (work@sky130_fd_sc_hd__a2111oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a2111oi.functional.v, line:35:1, endln:61:10 |vpiName:Y |vpiFullName:work@sky130_fd_sc_hd__a2111oi.Y |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a2111oi.A1), line:37:5, endln:37:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a2111oi (work@sky130_fd_sc_hd__a2111oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a2111oi.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__a2111oi (work@sky130_fd_sc_hd__a2111oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a2111oi.functional.v, line:35:1, endln:61:10 |vpiName:A1 |vpiFullName:work@sky130_fd_sc_hd__a2111oi.A1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a2111oi.A2), line:38:5, endln:38:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a2111oi (work@sky130_fd_sc_hd__a2111oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a2111oi.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__a2111oi (work@sky130_fd_sc_hd__a2111oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a2111oi.functional.v, line:35:1, endln:61:10 |vpiName:A2 |vpiFullName:work@sky130_fd_sc_hd__a2111oi.A2 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a2111oi.B1), line:39:5, endln:39:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a2111oi (work@sky130_fd_sc_hd__a2111oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a2111oi.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__a2111oi (work@sky130_fd_sc_hd__a2111oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a2111oi.functional.v, line:35:1, endln:61:10 |vpiName:B1 |vpiFullName:work@sky130_fd_sc_hd__a2111oi.B1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a2111oi.C1), line:40:5, endln:40:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a2111oi (work@sky130_fd_sc_hd__a2111oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a2111oi.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__a2111oi (work@sky130_fd_sc_hd__a2111oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a2111oi.functional.v, line:35:1, endln:61:10 |vpiName:C1 |vpiFullName:work@sky130_fd_sc_hd__a2111oi.C1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a2111oi.D1), line:41:5, endln:41:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a2111oi (work@sky130_fd_sc_hd__a2111oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a2111oi.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__a2111oi (work@sky130_fd_sc_hd__a2111oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a2111oi.functional.v, line:35:1, endln:61:10 |vpiName:D1 |vpiFullName:work@sky130_fd_sc_hd__a2111oi.D1 |vpiPort: \_port: (Y), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__a2111oi (work@sky130_fd_sc_hd__a2111oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a2111oi.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__a2111oi (work@sky130_fd_sc_hd__a2111oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a2111oi.functional.v, line:35:1, endln:61:10 |vpiName:Y |vpiDirection:2 |vpiLowConn: @@ -22572,7 +22572,7 @@ design: (work@sky130_fd_sc_hd__a2111oi) |vpiPort: \_port: (A1), line:37:5, endln:37:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a2111oi (work@sky130_fd_sc_hd__a2111oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a2111oi.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__a2111oi (work@sky130_fd_sc_hd__a2111oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a2111oi.functional.v, line:35:1, endln:61:10 |vpiName:A1 |vpiDirection:1 |vpiLowConn: @@ -22584,7 +22584,7 @@ design: (work@sky130_fd_sc_hd__a2111oi) |vpiPort: \_port: (A2), line:38:5, endln:38:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a2111oi (work@sky130_fd_sc_hd__a2111oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a2111oi.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__a2111oi (work@sky130_fd_sc_hd__a2111oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a2111oi.functional.v, line:35:1, endln:61:10 |vpiName:A2 |vpiDirection:1 |vpiLowConn: @@ -22596,7 +22596,7 @@ design: (work@sky130_fd_sc_hd__a2111oi) |vpiPort: \_port: (B1), line:39:5, endln:39:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a2111oi (work@sky130_fd_sc_hd__a2111oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a2111oi.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__a2111oi (work@sky130_fd_sc_hd__a2111oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a2111oi.functional.v, line:35:1, endln:61:10 |vpiName:B1 |vpiDirection:1 |vpiLowConn: @@ -22608,7 +22608,7 @@ design: (work@sky130_fd_sc_hd__a2111oi) |vpiPort: \_port: (C1), line:40:5, endln:40:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a2111oi (work@sky130_fd_sc_hd__a2111oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a2111oi.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__a2111oi (work@sky130_fd_sc_hd__a2111oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a2111oi.functional.v, line:35:1, endln:61:10 |vpiName:C1 |vpiDirection:1 |vpiLowConn: @@ -22620,7 +22620,7 @@ design: (work@sky130_fd_sc_hd__a2111oi) |vpiPort: \_port: (D1), line:41:5, endln:41:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a2111oi (work@sky130_fd_sc_hd__a2111oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a2111oi.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__a2111oi (work@sky130_fd_sc_hd__a2111oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a2111oi.functional.v, line:35:1, endln:61:10 |vpiName:D1 |vpiDirection:1 |vpiLowConn: @@ -22630,14 +22630,14 @@ design: (work@sky130_fd_sc_hd__a2111oi) |vpiTypedef: \_logic_typespec: , line:50:12, endln:50:12 |uhdmtopModules: -\_module: work@sky130_fd_sc_hd__a2111oi (work@sky130_fd_sc_hd__a2111oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a2111oi.functional.v, line:35:1, endln:61:10 +\_module_inst: work@sky130_fd_sc_hd__a2111oi (work@sky130_fd_sc_hd__a2111oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a2111oi.functional.v, line:35:1, endln:61:10 |vpiName:work@sky130_fd_sc_hd__a2111oi |vpiDefName:work@sky130_fd_sc_hd__a2111oi |vpiTop:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a2111oi.and0_out), line:53:10, endln:53:18 |vpiParent: - \_module: work@sky130_fd_sc_hd__a2111oi (work@sky130_fd_sc_hd__a2111oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a2111oi.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__a2111oi (work@sky130_fd_sc_hd__a2111oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a2111oi.functional.v, line:35:1, endln:61:10 |vpiTypespec: \_logic_typespec: , line:53:5, endln:53:9 |vpiName:and0_out @@ -22646,7 +22646,7 @@ design: (work@sky130_fd_sc_hd__a2111oi) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a2111oi.nor0_out_Y), line:54:10, endln:54:20 |vpiParent: - \_module: work@sky130_fd_sc_hd__a2111oi (work@sky130_fd_sc_hd__a2111oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a2111oi.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__a2111oi (work@sky130_fd_sc_hd__a2111oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a2111oi.functional.v, line:35:1, endln:61:10 |vpiTypespec: \_logic_typespec: , line:54:5, endln:54:9 |vpiName:nor0_out_Y @@ -22655,7 +22655,7 @@ design: (work@sky130_fd_sc_hd__a2111oi) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a2111oi.Y), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__a2111oi (work@sky130_fd_sc_hd__a2111oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a2111oi.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__a2111oi (work@sky130_fd_sc_hd__a2111oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a2111oi.functional.v, line:35:1, endln:61:10 |vpiTypespec: \_logic_typespec: , line:45:12, endln:45:12 |vpiName:Y @@ -22663,7 +22663,7 @@ design: (work@sky130_fd_sc_hd__a2111oi) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a2111oi.A1), line:37:5, endln:37:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a2111oi (work@sky130_fd_sc_hd__a2111oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a2111oi.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__a2111oi (work@sky130_fd_sc_hd__a2111oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a2111oi.functional.v, line:35:1, endln:61:10 |vpiTypespec: \_logic_typespec: , line:46:12, endln:46:12 |vpiName:A1 @@ -22671,7 +22671,7 @@ design: (work@sky130_fd_sc_hd__a2111oi) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a2111oi.A2), line:38:5, endln:38:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a2111oi (work@sky130_fd_sc_hd__a2111oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a2111oi.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__a2111oi (work@sky130_fd_sc_hd__a2111oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a2111oi.functional.v, line:35:1, endln:61:10 |vpiTypespec: \_logic_typespec: , line:47:12, endln:47:12 |vpiName:A2 @@ -22679,7 +22679,7 @@ design: (work@sky130_fd_sc_hd__a2111oi) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a2111oi.B1), line:39:5, endln:39:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a2111oi (work@sky130_fd_sc_hd__a2111oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a2111oi.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__a2111oi (work@sky130_fd_sc_hd__a2111oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a2111oi.functional.v, line:35:1, endln:61:10 |vpiTypespec: \_logic_typespec: , line:48:12, endln:48:12 |vpiName:B1 @@ -22687,7 +22687,7 @@ design: (work@sky130_fd_sc_hd__a2111oi) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a2111oi.C1), line:40:5, endln:40:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a2111oi (work@sky130_fd_sc_hd__a2111oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a2111oi.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__a2111oi (work@sky130_fd_sc_hd__a2111oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a2111oi.functional.v, line:35:1, endln:61:10 |vpiTypespec: \_logic_typespec: , line:49:12, endln:49:12 |vpiName:C1 @@ -22695,7 +22695,7 @@ design: (work@sky130_fd_sc_hd__a2111oi) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a2111oi.D1), line:41:5, endln:41:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a2111oi (work@sky130_fd_sc_hd__a2111oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a2111oi.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__a2111oi (work@sky130_fd_sc_hd__a2111oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a2111oi.functional.v, line:35:1, endln:61:10 |vpiTypespec: \_logic_typespec: , line:50:12, endln:50:12 |vpiName:D1 @@ -22704,7 +22704,7 @@ design: (work@sky130_fd_sc_hd__a2111oi) |vpiPort: \_port: (Y), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__a2111oi (work@sky130_fd_sc_hd__a2111oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a2111oi.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__a2111oi (work@sky130_fd_sc_hd__a2111oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a2111oi.functional.v, line:35:1, endln:61:10 |vpiName:Y |vpiDirection:2 |vpiLowConn: @@ -22718,7 +22718,7 @@ design: (work@sky130_fd_sc_hd__a2111oi) |vpiPort: \_port: (A1), line:37:5, endln:37:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a2111oi (work@sky130_fd_sc_hd__a2111oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a2111oi.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__a2111oi (work@sky130_fd_sc_hd__a2111oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a2111oi.functional.v, line:35:1, endln:61:10 |vpiName:A1 |vpiDirection:1 |vpiLowConn: @@ -22732,7 +22732,7 @@ design: (work@sky130_fd_sc_hd__a2111oi) |vpiPort: \_port: (A2), line:38:5, endln:38:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a2111oi (work@sky130_fd_sc_hd__a2111oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a2111oi.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__a2111oi (work@sky130_fd_sc_hd__a2111oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a2111oi.functional.v, line:35:1, endln:61:10 |vpiName:A2 |vpiDirection:1 |vpiLowConn: @@ -22746,7 +22746,7 @@ design: (work@sky130_fd_sc_hd__a2111oi) |vpiPort: \_port: (B1), line:39:5, endln:39:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a2111oi (work@sky130_fd_sc_hd__a2111oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a2111oi.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__a2111oi (work@sky130_fd_sc_hd__a2111oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a2111oi.functional.v, line:35:1, endln:61:10 |vpiName:B1 |vpiDirection:1 |vpiLowConn: @@ -22760,7 +22760,7 @@ design: (work@sky130_fd_sc_hd__a2111oi) |vpiPort: \_port: (C1), line:40:5, endln:40:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a2111oi (work@sky130_fd_sc_hd__a2111oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a2111oi.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__a2111oi (work@sky130_fd_sc_hd__a2111oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a2111oi.functional.v, line:35:1, endln:61:10 |vpiName:C1 |vpiDirection:1 |vpiLowConn: @@ -22774,7 +22774,7 @@ design: (work@sky130_fd_sc_hd__a2111oi) |vpiPort: \_port: (D1), line:41:5, endln:41:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a2111oi (work@sky130_fd_sc_hd__a2111oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a2111oi.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__a2111oi (work@sky130_fd_sc_hd__a2111oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a2111oi.functional.v, line:35:1, endln:61:10 |vpiName:D1 |vpiDirection:1 |vpiLowConn: @@ -22788,7 +22788,7 @@ design: (work@sky130_fd_sc_hd__a2111oi) |vpiPrimitive: \_gate: work@and (work@sky130_fd_sc_hd__a2111oi.and0), line:57:9, endln:57:48 |vpiParent: - \_module: work@sky130_fd_sc_hd__a2111oi (work@sky130_fd_sc_hd__a2111oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a2111oi.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__a2111oi (work@sky130_fd_sc_hd__a2111oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a2111oi.functional.v, line:35:1, endln:61:10 |vpiDefName:work@and |vpiName:and0 |vpiFullName:work@sky130_fd_sc_hd__a2111oi.and0 @@ -22837,7 +22837,7 @@ design: (work@sky130_fd_sc_hd__a2111oi) |vpiPrimitive: \_gate: work@nor (work@sky130_fd_sc_hd__a2111oi.nor0), line:58:9, endln:58:48 |vpiParent: - \_module: work@sky130_fd_sc_hd__a2111oi (work@sky130_fd_sc_hd__a2111oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a2111oi.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__a2111oi (work@sky130_fd_sc_hd__a2111oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a2111oi.functional.v, line:35:1, endln:61:10 |vpiDefName:work@nor |vpiName:nor0 |vpiFullName:work@sky130_fd_sc_hd__a2111oi.nor0 @@ -22914,7 +22914,7 @@ design: (work@sky130_fd_sc_hd__a2111oi) |vpiPrimitive: \_gate: work@buf (work@sky130_fd_sc_hd__a2111oi.buf0), line:59:9, endln:59:48 |vpiParent: - \_module: work@sky130_fd_sc_hd__a2111oi (work@sky130_fd_sc_hd__a2111oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a2111oi.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__a2111oi (work@sky130_fd_sc_hd__a2111oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a2111oi.functional.v, line:35:1, endln:61:10 |vpiDefName:work@buf |vpiName:buf0 |vpiFullName:work@sky130_fd_sc_hd__a2111oi.buf0 @@ -22957,7 +22957,7 @@ Processing: -cd cells/cells -DUNIT_DELAY -writepp -parse -nocache -nobuiltin -no design: (work@sky130_fd_sc_hd__o21ba) |vpiName:work@sky130_fd_sc_hd__o21ba |uhdmallModules: -\_module: work@sky130_fd_sc_hd__o21ba (work@sky130_fd_sc_hd__o21ba), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o21ba.functional.v, line:36:1, endln:58:10 +\_module_inst: work@sky130_fd_sc_hd__o21ba (work@sky130_fd_sc_hd__o21ba), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o21ba.functional.v, line:36:1, endln:58:10 |vpiParent: \_design: (work@sky130_fd_sc_hd__o21ba) |vpiFullName:work@sky130_fd_sc_hd__o21ba @@ -22965,45 +22965,45 @@ design: (work@sky130_fd_sc_hd__o21ba) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o21ba.nor0_out), line:50:10, endln:50:18 |vpiParent: - \_module: work@sky130_fd_sc_hd__o21ba (work@sky130_fd_sc_hd__o21ba), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o21ba.functional.v, line:36:1, endln:58:10 + \_module_inst: work@sky130_fd_sc_hd__o21ba (work@sky130_fd_sc_hd__o21ba), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o21ba.functional.v, line:36:1, endln:58:10 |vpiName:nor0_out |vpiFullName:work@sky130_fd_sc_hd__o21ba.nor0_out |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o21ba.nor1_out_X), line:51:10, endln:51:20 |vpiParent: - \_module: work@sky130_fd_sc_hd__o21ba (work@sky130_fd_sc_hd__o21ba), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o21ba.functional.v, line:36:1, endln:58:10 + \_module_inst: work@sky130_fd_sc_hd__o21ba (work@sky130_fd_sc_hd__o21ba), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o21ba.functional.v, line:36:1, endln:58:10 |vpiName:nor1_out_X |vpiFullName:work@sky130_fd_sc_hd__o21ba.nor1_out_X |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o21ba.X), line:37:5, endln:37:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__o21ba (work@sky130_fd_sc_hd__o21ba), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o21ba.functional.v, line:36:1, endln:58:10 + \_module_inst: work@sky130_fd_sc_hd__o21ba (work@sky130_fd_sc_hd__o21ba), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o21ba.functional.v, line:36:1, endln:58:10 |vpiName:X |vpiFullName:work@sky130_fd_sc_hd__o21ba.X |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o21ba.A1), line:38:5, endln:38:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o21ba (work@sky130_fd_sc_hd__o21ba), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o21ba.functional.v, line:36:1, endln:58:10 + \_module_inst: work@sky130_fd_sc_hd__o21ba (work@sky130_fd_sc_hd__o21ba), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o21ba.functional.v, line:36:1, endln:58:10 |vpiName:A1 |vpiFullName:work@sky130_fd_sc_hd__o21ba.A1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o21ba.A2), line:39:5, endln:39:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o21ba (work@sky130_fd_sc_hd__o21ba), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o21ba.functional.v, line:36:1, endln:58:10 + \_module_inst: work@sky130_fd_sc_hd__o21ba (work@sky130_fd_sc_hd__o21ba), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o21ba.functional.v, line:36:1, endln:58:10 |vpiName:A2 |vpiFullName:work@sky130_fd_sc_hd__o21ba.A2 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o21ba.B1_N), line:40:5, endln:40:9 |vpiParent: - \_module: work@sky130_fd_sc_hd__o21ba (work@sky130_fd_sc_hd__o21ba), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o21ba.functional.v, line:36:1, endln:58:10 + \_module_inst: work@sky130_fd_sc_hd__o21ba (work@sky130_fd_sc_hd__o21ba), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o21ba.functional.v, line:36:1, endln:58:10 |vpiName:B1_N |vpiFullName:work@sky130_fd_sc_hd__o21ba.B1_N |vpiPort: \_port: (X), line:37:5, endln:37:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__o21ba (work@sky130_fd_sc_hd__o21ba), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o21ba.functional.v, line:36:1, endln:58:10 + \_module_inst: work@sky130_fd_sc_hd__o21ba (work@sky130_fd_sc_hd__o21ba), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o21ba.functional.v, line:36:1, endln:58:10 |vpiName:X |vpiDirection:2 |vpiLowConn: @@ -23015,7 +23015,7 @@ design: (work@sky130_fd_sc_hd__o21ba) |vpiPort: \_port: (A1), line:38:5, endln:38:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o21ba (work@sky130_fd_sc_hd__o21ba), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o21ba.functional.v, line:36:1, endln:58:10 + \_module_inst: work@sky130_fd_sc_hd__o21ba (work@sky130_fd_sc_hd__o21ba), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o21ba.functional.v, line:36:1, endln:58:10 |vpiName:A1 |vpiDirection:1 |vpiLowConn: @@ -23027,7 +23027,7 @@ design: (work@sky130_fd_sc_hd__o21ba) |vpiPort: \_port: (A2), line:39:5, endln:39:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o21ba (work@sky130_fd_sc_hd__o21ba), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o21ba.functional.v, line:36:1, endln:58:10 + \_module_inst: work@sky130_fd_sc_hd__o21ba (work@sky130_fd_sc_hd__o21ba), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o21ba.functional.v, line:36:1, endln:58:10 |vpiName:A2 |vpiDirection:1 |vpiLowConn: @@ -23039,7 +23039,7 @@ design: (work@sky130_fd_sc_hd__o21ba) |vpiPort: \_port: (B1_N), line:40:5, endln:40:9 |vpiParent: - \_module: work@sky130_fd_sc_hd__o21ba (work@sky130_fd_sc_hd__o21ba), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o21ba.functional.v, line:36:1, endln:58:10 + \_module_inst: work@sky130_fd_sc_hd__o21ba (work@sky130_fd_sc_hd__o21ba), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o21ba.functional.v, line:36:1, endln:58:10 |vpiName:B1_N |vpiDirection:1 |vpiLowConn: @@ -23049,14 +23049,14 @@ design: (work@sky130_fd_sc_hd__o21ba) |vpiTypedef: \_logic_typespec: , line:47:12, endln:47:12 |uhdmtopModules: -\_module: work@sky130_fd_sc_hd__o21ba (work@sky130_fd_sc_hd__o21ba), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o21ba.functional.v, line:36:1, endln:58:10 +\_module_inst: work@sky130_fd_sc_hd__o21ba (work@sky130_fd_sc_hd__o21ba), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o21ba.functional.v, line:36:1, endln:58:10 |vpiName:work@sky130_fd_sc_hd__o21ba |vpiDefName:work@sky130_fd_sc_hd__o21ba |vpiTop:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o21ba.nor0_out), line:50:10, endln:50:18 |vpiParent: - \_module: work@sky130_fd_sc_hd__o21ba (work@sky130_fd_sc_hd__o21ba), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o21ba.functional.v, line:36:1, endln:58:10 + \_module_inst: work@sky130_fd_sc_hd__o21ba (work@sky130_fd_sc_hd__o21ba), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o21ba.functional.v, line:36:1, endln:58:10 |vpiTypespec: \_logic_typespec: , line:50:5, endln:50:9 |vpiName:nor0_out @@ -23065,7 +23065,7 @@ design: (work@sky130_fd_sc_hd__o21ba) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o21ba.nor1_out_X), line:51:10, endln:51:20 |vpiParent: - \_module: work@sky130_fd_sc_hd__o21ba (work@sky130_fd_sc_hd__o21ba), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o21ba.functional.v, line:36:1, endln:58:10 + \_module_inst: work@sky130_fd_sc_hd__o21ba (work@sky130_fd_sc_hd__o21ba), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o21ba.functional.v, line:36:1, endln:58:10 |vpiTypespec: \_logic_typespec: , line:51:5, endln:51:9 |vpiName:nor1_out_X @@ -23074,7 +23074,7 @@ design: (work@sky130_fd_sc_hd__o21ba) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o21ba.X), line:37:5, endln:37:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__o21ba (work@sky130_fd_sc_hd__o21ba), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o21ba.functional.v, line:36:1, endln:58:10 + \_module_inst: work@sky130_fd_sc_hd__o21ba (work@sky130_fd_sc_hd__o21ba), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o21ba.functional.v, line:36:1, endln:58:10 |vpiTypespec: \_logic_typespec: , line:44:12, endln:44:12 |vpiName:X @@ -23082,7 +23082,7 @@ design: (work@sky130_fd_sc_hd__o21ba) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o21ba.A1), line:38:5, endln:38:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o21ba (work@sky130_fd_sc_hd__o21ba), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o21ba.functional.v, line:36:1, endln:58:10 + \_module_inst: work@sky130_fd_sc_hd__o21ba (work@sky130_fd_sc_hd__o21ba), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o21ba.functional.v, line:36:1, endln:58:10 |vpiTypespec: \_logic_typespec: , line:45:12, endln:45:12 |vpiName:A1 @@ -23090,7 +23090,7 @@ design: (work@sky130_fd_sc_hd__o21ba) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o21ba.A2), line:39:5, endln:39:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o21ba (work@sky130_fd_sc_hd__o21ba), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o21ba.functional.v, line:36:1, endln:58:10 + \_module_inst: work@sky130_fd_sc_hd__o21ba (work@sky130_fd_sc_hd__o21ba), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o21ba.functional.v, line:36:1, endln:58:10 |vpiTypespec: \_logic_typespec: , line:46:12, endln:46:12 |vpiName:A2 @@ -23098,7 +23098,7 @@ design: (work@sky130_fd_sc_hd__o21ba) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o21ba.B1_N), line:40:5, endln:40:9 |vpiParent: - \_module: work@sky130_fd_sc_hd__o21ba (work@sky130_fd_sc_hd__o21ba), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o21ba.functional.v, line:36:1, endln:58:10 + \_module_inst: work@sky130_fd_sc_hd__o21ba (work@sky130_fd_sc_hd__o21ba), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o21ba.functional.v, line:36:1, endln:58:10 |vpiTypespec: \_logic_typespec: , line:47:12, endln:47:12 |vpiName:B1_N @@ -23107,7 +23107,7 @@ design: (work@sky130_fd_sc_hd__o21ba) |vpiPort: \_port: (X), line:37:5, endln:37:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__o21ba (work@sky130_fd_sc_hd__o21ba), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o21ba.functional.v, line:36:1, endln:58:10 + \_module_inst: work@sky130_fd_sc_hd__o21ba (work@sky130_fd_sc_hd__o21ba), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o21ba.functional.v, line:36:1, endln:58:10 |vpiName:X |vpiDirection:2 |vpiLowConn: @@ -23121,7 +23121,7 @@ design: (work@sky130_fd_sc_hd__o21ba) |vpiPort: \_port: (A1), line:38:5, endln:38:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o21ba (work@sky130_fd_sc_hd__o21ba), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o21ba.functional.v, line:36:1, endln:58:10 + \_module_inst: work@sky130_fd_sc_hd__o21ba (work@sky130_fd_sc_hd__o21ba), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o21ba.functional.v, line:36:1, endln:58:10 |vpiName:A1 |vpiDirection:1 |vpiLowConn: @@ -23135,7 +23135,7 @@ design: (work@sky130_fd_sc_hd__o21ba) |vpiPort: \_port: (A2), line:39:5, endln:39:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o21ba (work@sky130_fd_sc_hd__o21ba), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o21ba.functional.v, line:36:1, endln:58:10 + \_module_inst: work@sky130_fd_sc_hd__o21ba (work@sky130_fd_sc_hd__o21ba), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o21ba.functional.v, line:36:1, endln:58:10 |vpiName:A2 |vpiDirection:1 |vpiLowConn: @@ -23149,7 +23149,7 @@ design: (work@sky130_fd_sc_hd__o21ba) |vpiPort: \_port: (B1_N), line:40:5, endln:40:9 |vpiParent: - \_module: work@sky130_fd_sc_hd__o21ba (work@sky130_fd_sc_hd__o21ba), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o21ba.functional.v, line:36:1, endln:58:10 + \_module_inst: work@sky130_fd_sc_hd__o21ba (work@sky130_fd_sc_hd__o21ba), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o21ba.functional.v, line:36:1, endln:58:10 |vpiName:B1_N |vpiDirection:1 |vpiLowConn: @@ -23163,7 +23163,7 @@ design: (work@sky130_fd_sc_hd__o21ba) |vpiPrimitive: \_gate: work@nor (work@sky130_fd_sc_hd__o21ba.nor0), line:54:9, endln:54:43 |vpiParent: - \_module: work@sky130_fd_sc_hd__o21ba (work@sky130_fd_sc_hd__o21ba), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o21ba.functional.v, line:36:1, endln:58:10 + \_module_inst: work@sky130_fd_sc_hd__o21ba (work@sky130_fd_sc_hd__o21ba), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o21ba.functional.v, line:36:1, endln:58:10 |vpiDefName:work@nor |vpiName:nor0 |vpiFullName:work@sky130_fd_sc_hd__o21ba.nor0 @@ -23212,7 +23212,7 @@ design: (work@sky130_fd_sc_hd__o21ba) |vpiPrimitive: \_gate: work@nor (work@sky130_fd_sc_hd__o21ba.nor1), line:55:9, endln:55:43 |vpiParent: - \_module: work@sky130_fd_sc_hd__o21ba (work@sky130_fd_sc_hd__o21ba), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o21ba.functional.v, line:36:1, endln:58:10 + \_module_inst: work@sky130_fd_sc_hd__o21ba (work@sky130_fd_sc_hd__o21ba), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o21ba.functional.v, line:36:1, endln:58:10 |vpiDefName:work@nor |vpiName:nor1 |vpiFullName:work@sky130_fd_sc_hd__o21ba.nor1 @@ -23261,7 +23261,7 @@ design: (work@sky130_fd_sc_hd__o21ba) |vpiPrimitive: \_gate: work@buf (work@sky130_fd_sc_hd__o21ba.buf0), line:56:9, endln:56:43 |vpiParent: - \_module: work@sky130_fd_sc_hd__o21ba (work@sky130_fd_sc_hd__o21ba), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o21ba.functional.v, line:36:1, endln:58:10 + \_module_inst: work@sky130_fd_sc_hd__o21ba (work@sky130_fd_sc_hd__o21ba), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o21ba.functional.v, line:36:1, endln:58:10 |vpiDefName:work@buf |vpiName:buf0 |vpiFullName:work@sky130_fd_sc_hd__o21ba.buf0 @@ -23304,7 +23304,7 @@ Processing: -cd cells/cells -DUNIT_DELAY -writepp -parse -nocache -nobuiltin -no design: (work@sky130_fd_sc_hd__nand3b) |vpiName:work@sky130_fd_sc_hd__nand3b |uhdmallModules: -\_module: work@sky130_fd_sc_hd__nand3b (work@sky130_fd_sc_hd__nand3b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand3b.functional.v, line:33:1, endln:55:10 +\_module_inst: work@sky130_fd_sc_hd__nand3b (work@sky130_fd_sc_hd__nand3b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand3b.functional.v, line:33:1, endln:55:10 |vpiParent: \_design: (work@sky130_fd_sc_hd__nand3b) |vpiFullName:work@sky130_fd_sc_hd__nand3b @@ -23312,45 +23312,45 @@ design: (work@sky130_fd_sc_hd__nand3b) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__nand3b.not0_out), line:47:10, endln:47:18 |vpiParent: - \_module: work@sky130_fd_sc_hd__nand3b (work@sky130_fd_sc_hd__nand3b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand3b.functional.v, line:33:1, endln:55:10 + \_module_inst: work@sky130_fd_sc_hd__nand3b (work@sky130_fd_sc_hd__nand3b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand3b.functional.v, line:33:1, endln:55:10 |vpiName:not0_out |vpiFullName:work@sky130_fd_sc_hd__nand3b.not0_out |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__nand3b.nand0_out_Y), line:48:10, endln:48:21 |vpiParent: - \_module: work@sky130_fd_sc_hd__nand3b (work@sky130_fd_sc_hd__nand3b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand3b.functional.v, line:33:1, endln:55:10 + \_module_inst: work@sky130_fd_sc_hd__nand3b (work@sky130_fd_sc_hd__nand3b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand3b.functional.v, line:33:1, endln:55:10 |vpiName:nand0_out_Y |vpiFullName:work@sky130_fd_sc_hd__nand3b.nand0_out_Y |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__nand3b.Y), line:34:5, endln:34:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__nand3b (work@sky130_fd_sc_hd__nand3b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand3b.functional.v, line:33:1, endln:55:10 + \_module_inst: work@sky130_fd_sc_hd__nand3b (work@sky130_fd_sc_hd__nand3b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand3b.functional.v, line:33:1, endln:55:10 |vpiName:Y |vpiFullName:work@sky130_fd_sc_hd__nand3b.Y |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__nand3b.A_N), line:35:5, endln:35:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__nand3b (work@sky130_fd_sc_hd__nand3b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand3b.functional.v, line:33:1, endln:55:10 + \_module_inst: work@sky130_fd_sc_hd__nand3b (work@sky130_fd_sc_hd__nand3b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand3b.functional.v, line:33:1, endln:55:10 |vpiName:A_N |vpiFullName:work@sky130_fd_sc_hd__nand3b.A_N |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__nand3b.B), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__nand3b (work@sky130_fd_sc_hd__nand3b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand3b.functional.v, line:33:1, endln:55:10 + \_module_inst: work@sky130_fd_sc_hd__nand3b (work@sky130_fd_sc_hd__nand3b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand3b.functional.v, line:33:1, endln:55:10 |vpiName:B |vpiFullName:work@sky130_fd_sc_hd__nand3b.B |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__nand3b.C), line:37:5, endln:37:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__nand3b (work@sky130_fd_sc_hd__nand3b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand3b.functional.v, line:33:1, endln:55:10 + \_module_inst: work@sky130_fd_sc_hd__nand3b (work@sky130_fd_sc_hd__nand3b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand3b.functional.v, line:33:1, endln:55:10 |vpiName:C |vpiFullName:work@sky130_fd_sc_hd__nand3b.C |vpiPort: \_port: (Y), line:34:5, endln:34:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__nand3b (work@sky130_fd_sc_hd__nand3b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand3b.functional.v, line:33:1, endln:55:10 + \_module_inst: work@sky130_fd_sc_hd__nand3b (work@sky130_fd_sc_hd__nand3b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand3b.functional.v, line:33:1, endln:55:10 |vpiName:Y |vpiDirection:2 |vpiLowConn: @@ -23362,7 +23362,7 @@ design: (work@sky130_fd_sc_hd__nand3b) |vpiPort: \_port: (A_N), line:35:5, endln:35:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__nand3b (work@sky130_fd_sc_hd__nand3b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand3b.functional.v, line:33:1, endln:55:10 + \_module_inst: work@sky130_fd_sc_hd__nand3b (work@sky130_fd_sc_hd__nand3b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand3b.functional.v, line:33:1, endln:55:10 |vpiName:A_N |vpiDirection:1 |vpiLowConn: @@ -23374,7 +23374,7 @@ design: (work@sky130_fd_sc_hd__nand3b) |vpiPort: \_port: (B), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__nand3b (work@sky130_fd_sc_hd__nand3b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand3b.functional.v, line:33:1, endln:55:10 + \_module_inst: work@sky130_fd_sc_hd__nand3b (work@sky130_fd_sc_hd__nand3b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand3b.functional.v, line:33:1, endln:55:10 |vpiName:B |vpiDirection:1 |vpiLowConn: @@ -23386,7 +23386,7 @@ design: (work@sky130_fd_sc_hd__nand3b) |vpiPort: \_port: (C), line:37:5, endln:37:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__nand3b (work@sky130_fd_sc_hd__nand3b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand3b.functional.v, line:33:1, endln:55:10 + \_module_inst: work@sky130_fd_sc_hd__nand3b (work@sky130_fd_sc_hd__nand3b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand3b.functional.v, line:33:1, endln:55:10 |vpiName:C |vpiDirection:1 |vpiLowConn: @@ -23396,14 +23396,14 @@ design: (work@sky130_fd_sc_hd__nand3b) |vpiTypedef: \_logic_typespec: , line:44:12, endln:44:12 |uhdmtopModules: -\_module: work@sky130_fd_sc_hd__nand3b (work@sky130_fd_sc_hd__nand3b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand3b.functional.v, line:33:1, endln:55:10 +\_module_inst: work@sky130_fd_sc_hd__nand3b (work@sky130_fd_sc_hd__nand3b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand3b.functional.v, line:33:1, endln:55:10 |vpiName:work@sky130_fd_sc_hd__nand3b |vpiDefName:work@sky130_fd_sc_hd__nand3b |vpiTop:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__nand3b.not0_out), line:47:10, endln:47:18 |vpiParent: - \_module: work@sky130_fd_sc_hd__nand3b (work@sky130_fd_sc_hd__nand3b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand3b.functional.v, line:33:1, endln:55:10 + \_module_inst: work@sky130_fd_sc_hd__nand3b (work@sky130_fd_sc_hd__nand3b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand3b.functional.v, line:33:1, endln:55:10 |vpiTypespec: \_logic_typespec: , line:47:5, endln:47:9 |vpiName:not0_out @@ -23412,7 +23412,7 @@ design: (work@sky130_fd_sc_hd__nand3b) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__nand3b.nand0_out_Y), line:48:10, endln:48:21 |vpiParent: - \_module: work@sky130_fd_sc_hd__nand3b (work@sky130_fd_sc_hd__nand3b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand3b.functional.v, line:33:1, endln:55:10 + \_module_inst: work@sky130_fd_sc_hd__nand3b (work@sky130_fd_sc_hd__nand3b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand3b.functional.v, line:33:1, endln:55:10 |vpiTypespec: \_logic_typespec: , line:48:5, endln:48:9 |vpiName:nand0_out_Y @@ -23421,7 +23421,7 @@ design: (work@sky130_fd_sc_hd__nand3b) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__nand3b.Y), line:34:5, endln:34:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__nand3b (work@sky130_fd_sc_hd__nand3b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand3b.functional.v, line:33:1, endln:55:10 + \_module_inst: work@sky130_fd_sc_hd__nand3b (work@sky130_fd_sc_hd__nand3b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand3b.functional.v, line:33:1, endln:55:10 |vpiTypespec: \_logic_typespec: , line:41:12, endln:41:12 |vpiName:Y @@ -23429,7 +23429,7 @@ design: (work@sky130_fd_sc_hd__nand3b) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__nand3b.A_N), line:35:5, endln:35:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__nand3b (work@sky130_fd_sc_hd__nand3b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand3b.functional.v, line:33:1, endln:55:10 + \_module_inst: work@sky130_fd_sc_hd__nand3b (work@sky130_fd_sc_hd__nand3b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand3b.functional.v, line:33:1, endln:55:10 |vpiTypespec: \_logic_typespec: , line:42:12, endln:42:12 |vpiName:A_N @@ -23437,7 +23437,7 @@ design: (work@sky130_fd_sc_hd__nand3b) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__nand3b.B), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__nand3b (work@sky130_fd_sc_hd__nand3b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand3b.functional.v, line:33:1, endln:55:10 + \_module_inst: work@sky130_fd_sc_hd__nand3b (work@sky130_fd_sc_hd__nand3b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand3b.functional.v, line:33:1, endln:55:10 |vpiTypespec: \_logic_typespec: , line:43:12, endln:43:12 |vpiName:B @@ -23445,7 +23445,7 @@ design: (work@sky130_fd_sc_hd__nand3b) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__nand3b.C), line:37:5, endln:37:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__nand3b (work@sky130_fd_sc_hd__nand3b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand3b.functional.v, line:33:1, endln:55:10 + \_module_inst: work@sky130_fd_sc_hd__nand3b (work@sky130_fd_sc_hd__nand3b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand3b.functional.v, line:33:1, endln:55:10 |vpiTypespec: \_logic_typespec: , line:44:12, endln:44:12 |vpiName:C @@ -23454,7 +23454,7 @@ design: (work@sky130_fd_sc_hd__nand3b) |vpiPort: \_port: (Y), line:34:5, endln:34:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__nand3b (work@sky130_fd_sc_hd__nand3b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand3b.functional.v, line:33:1, endln:55:10 + \_module_inst: work@sky130_fd_sc_hd__nand3b (work@sky130_fd_sc_hd__nand3b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand3b.functional.v, line:33:1, endln:55:10 |vpiName:Y |vpiDirection:2 |vpiLowConn: @@ -23468,7 +23468,7 @@ design: (work@sky130_fd_sc_hd__nand3b) |vpiPort: \_port: (A_N), line:35:5, endln:35:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__nand3b (work@sky130_fd_sc_hd__nand3b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand3b.functional.v, line:33:1, endln:55:10 + \_module_inst: work@sky130_fd_sc_hd__nand3b (work@sky130_fd_sc_hd__nand3b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand3b.functional.v, line:33:1, endln:55:10 |vpiName:A_N |vpiDirection:1 |vpiLowConn: @@ -23482,7 +23482,7 @@ design: (work@sky130_fd_sc_hd__nand3b) |vpiPort: \_port: (B), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__nand3b (work@sky130_fd_sc_hd__nand3b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand3b.functional.v, line:33:1, endln:55:10 + \_module_inst: work@sky130_fd_sc_hd__nand3b (work@sky130_fd_sc_hd__nand3b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand3b.functional.v, line:33:1, endln:55:10 |vpiName:B |vpiDirection:1 |vpiLowConn: @@ -23496,7 +23496,7 @@ design: (work@sky130_fd_sc_hd__nand3b) |vpiPort: \_port: (C), line:37:5, endln:37:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__nand3b (work@sky130_fd_sc_hd__nand3b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand3b.functional.v, line:33:1, endln:55:10 + \_module_inst: work@sky130_fd_sc_hd__nand3b (work@sky130_fd_sc_hd__nand3b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand3b.functional.v, line:33:1, endln:55:10 |vpiName:C |vpiDirection:1 |vpiLowConn: @@ -23510,7 +23510,7 @@ design: (work@sky130_fd_sc_hd__nand3b) |vpiPrimitive: \_gate: work@not (work@sky130_fd_sc_hd__nand3b.not0), line:51:10, endln:51:46 |vpiParent: - \_module: work@sky130_fd_sc_hd__nand3b (work@sky130_fd_sc_hd__nand3b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand3b.functional.v, line:33:1, endln:55:10 + \_module_inst: work@sky130_fd_sc_hd__nand3b (work@sky130_fd_sc_hd__nand3b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand3b.functional.v, line:33:1, endln:55:10 |vpiDefName:work@not |vpiName:not0 |vpiFullName:work@sky130_fd_sc_hd__nand3b.not0 @@ -23545,7 +23545,7 @@ design: (work@sky130_fd_sc_hd__nand3b) |vpiPrimitive: \_gate: work@nand (work@sky130_fd_sc_hd__nand3b.nand0), line:52:10, endln:52:46 |vpiParent: - \_module: work@sky130_fd_sc_hd__nand3b (work@sky130_fd_sc_hd__nand3b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand3b.functional.v, line:33:1, endln:55:10 + \_module_inst: work@sky130_fd_sc_hd__nand3b (work@sky130_fd_sc_hd__nand3b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand3b.functional.v, line:33:1, endln:55:10 |vpiDefName:work@nand |vpiName:nand0 |vpiFullName:work@sky130_fd_sc_hd__nand3b.nand0 @@ -23608,7 +23608,7 @@ design: (work@sky130_fd_sc_hd__nand3b) |vpiPrimitive: \_gate: work@buf (work@sky130_fd_sc_hd__nand3b.buf0), line:53:10, endln:53:46 |vpiParent: - \_module: work@sky130_fd_sc_hd__nand3b (work@sky130_fd_sc_hd__nand3b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand3b.functional.v, line:33:1, endln:55:10 + \_module_inst: work@sky130_fd_sc_hd__nand3b (work@sky130_fd_sc_hd__nand3b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand3b.functional.v, line:33:1, endln:55:10 |vpiDefName:work@buf |vpiName:buf0 |vpiFullName:work@sky130_fd_sc_hd__nand3b.buf0 @@ -23651,7 +23651,7 @@ Processing: -cd cells/cells -DUNIT_DELAY -writepp -parse -nocache -nobuiltin -no design: (work@sky130_fd_sc_hd__clkbuf) |vpiName:work@sky130_fd_sc_hd__clkbuf |uhdmallModules: -\_module: work@sky130_fd_sc_hd__clkbuf (work@sky130_fd_sc_hd__clkbuf), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__clkbuf.functional.v, line:33:1, endln:49:10 +\_module_inst: work@sky130_fd_sc_hd__clkbuf (work@sky130_fd_sc_hd__clkbuf), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__clkbuf.functional.v, line:33:1, endln:49:10 |vpiParent: \_design: (work@sky130_fd_sc_hd__clkbuf) |vpiFullName:work@sky130_fd_sc_hd__clkbuf @@ -23659,26 +23659,26 @@ design: (work@sky130_fd_sc_hd__clkbuf) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__clkbuf.buf0_out_X), line:43:10, endln:43:20 |vpiParent: - \_module: work@sky130_fd_sc_hd__clkbuf (work@sky130_fd_sc_hd__clkbuf), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__clkbuf.functional.v, line:33:1, endln:49:10 + \_module_inst: work@sky130_fd_sc_hd__clkbuf (work@sky130_fd_sc_hd__clkbuf), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__clkbuf.functional.v, line:33:1, endln:49:10 |vpiName:buf0_out_X |vpiFullName:work@sky130_fd_sc_hd__clkbuf.buf0_out_X |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__clkbuf.X), line:34:5, endln:34:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__clkbuf (work@sky130_fd_sc_hd__clkbuf), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__clkbuf.functional.v, line:33:1, endln:49:10 + \_module_inst: work@sky130_fd_sc_hd__clkbuf (work@sky130_fd_sc_hd__clkbuf), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__clkbuf.functional.v, line:33:1, endln:49:10 |vpiName:X |vpiFullName:work@sky130_fd_sc_hd__clkbuf.X |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__clkbuf.A), line:35:5, endln:35:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__clkbuf (work@sky130_fd_sc_hd__clkbuf), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__clkbuf.functional.v, line:33:1, endln:49:10 + \_module_inst: work@sky130_fd_sc_hd__clkbuf (work@sky130_fd_sc_hd__clkbuf), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__clkbuf.functional.v, line:33:1, endln:49:10 |vpiName:A |vpiFullName:work@sky130_fd_sc_hd__clkbuf.A |vpiPort: \_port: (X), line:34:5, endln:34:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__clkbuf (work@sky130_fd_sc_hd__clkbuf), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__clkbuf.functional.v, line:33:1, endln:49:10 + \_module_inst: work@sky130_fd_sc_hd__clkbuf (work@sky130_fd_sc_hd__clkbuf), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__clkbuf.functional.v, line:33:1, endln:49:10 |vpiName:X |vpiDirection:2 |vpiLowConn: @@ -23690,7 +23690,7 @@ design: (work@sky130_fd_sc_hd__clkbuf) |vpiPort: \_port: (A), line:35:5, endln:35:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__clkbuf (work@sky130_fd_sc_hd__clkbuf), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__clkbuf.functional.v, line:33:1, endln:49:10 + \_module_inst: work@sky130_fd_sc_hd__clkbuf (work@sky130_fd_sc_hd__clkbuf), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__clkbuf.functional.v, line:33:1, endln:49:10 |vpiName:A |vpiDirection:1 |vpiLowConn: @@ -23700,14 +23700,14 @@ design: (work@sky130_fd_sc_hd__clkbuf) |vpiTypedef: \_logic_typespec: , line:40:12, endln:40:12 |uhdmtopModules: -\_module: work@sky130_fd_sc_hd__clkbuf (work@sky130_fd_sc_hd__clkbuf), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__clkbuf.functional.v, line:33:1, endln:49:10 +\_module_inst: work@sky130_fd_sc_hd__clkbuf (work@sky130_fd_sc_hd__clkbuf), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__clkbuf.functional.v, line:33:1, endln:49:10 |vpiName:work@sky130_fd_sc_hd__clkbuf |vpiDefName:work@sky130_fd_sc_hd__clkbuf |vpiTop:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__clkbuf.buf0_out_X), line:43:10, endln:43:20 |vpiParent: - \_module: work@sky130_fd_sc_hd__clkbuf (work@sky130_fd_sc_hd__clkbuf), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__clkbuf.functional.v, line:33:1, endln:49:10 + \_module_inst: work@sky130_fd_sc_hd__clkbuf (work@sky130_fd_sc_hd__clkbuf), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__clkbuf.functional.v, line:33:1, endln:49:10 |vpiTypespec: \_logic_typespec: , line:43:5, endln:43:9 |vpiName:buf0_out_X @@ -23716,7 +23716,7 @@ design: (work@sky130_fd_sc_hd__clkbuf) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__clkbuf.X), line:34:5, endln:34:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__clkbuf (work@sky130_fd_sc_hd__clkbuf), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__clkbuf.functional.v, line:33:1, endln:49:10 + \_module_inst: work@sky130_fd_sc_hd__clkbuf (work@sky130_fd_sc_hd__clkbuf), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__clkbuf.functional.v, line:33:1, endln:49:10 |vpiTypespec: \_logic_typespec: , line:39:12, endln:39:12 |vpiName:X @@ -23724,7 +23724,7 @@ design: (work@sky130_fd_sc_hd__clkbuf) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__clkbuf.A), line:35:5, endln:35:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__clkbuf (work@sky130_fd_sc_hd__clkbuf), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__clkbuf.functional.v, line:33:1, endln:49:10 + \_module_inst: work@sky130_fd_sc_hd__clkbuf (work@sky130_fd_sc_hd__clkbuf), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__clkbuf.functional.v, line:33:1, endln:49:10 |vpiTypespec: \_logic_typespec: , line:40:12, endln:40:12 |vpiName:A @@ -23733,7 +23733,7 @@ design: (work@sky130_fd_sc_hd__clkbuf) |vpiPort: \_port: (X), line:34:5, endln:34:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__clkbuf (work@sky130_fd_sc_hd__clkbuf), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__clkbuf.functional.v, line:33:1, endln:49:10 + \_module_inst: work@sky130_fd_sc_hd__clkbuf (work@sky130_fd_sc_hd__clkbuf), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__clkbuf.functional.v, line:33:1, endln:49:10 |vpiName:X |vpiDirection:2 |vpiLowConn: @@ -23747,7 +23747,7 @@ design: (work@sky130_fd_sc_hd__clkbuf) |vpiPort: \_port: (A), line:35:5, endln:35:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__clkbuf (work@sky130_fd_sc_hd__clkbuf), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__clkbuf.functional.v, line:33:1, endln:49:10 + \_module_inst: work@sky130_fd_sc_hd__clkbuf (work@sky130_fd_sc_hd__clkbuf), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__clkbuf.functional.v, line:33:1, endln:49:10 |vpiName:A |vpiDirection:1 |vpiLowConn: @@ -23761,7 +23761,7 @@ design: (work@sky130_fd_sc_hd__clkbuf) |vpiPrimitive: \_gate: work@buf (work@sky130_fd_sc_hd__clkbuf.buf0), line:46:9, endln:46:43 |vpiParent: - \_module: work@sky130_fd_sc_hd__clkbuf (work@sky130_fd_sc_hd__clkbuf), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__clkbuf.functional.v, line:33:1, endln:49:10 + \_module_inst: work@sky130_fd_sc_hd__clkbuf (work@sky130_fd_sc_hd__clkbuf), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__clkbuf.functional.v, line:33:1, endln:49:10 |vpiDefName:work@buf |vpiName:buf0 |vpiFullName:work@sky130_fd_sc_hd__clkbuf.buf0 @@ -23796,7 +23796,7 @@ design: (work@sky130_fd_sc_hd__clkbuf) |vpiPrimitive: \_gate: work@buf (work@sky130_fd_sc_hd__clkbuf.buf1), line:47:9, endln:47:43 |vpiParent: - \_module: work@sky130_fd_sc_hd__clkbuf (work@sky130_fd_sc_hd__clkbuf), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__clkbuf.functional.v, line:33:1, endln:49:10 + \_module_inst: work@sky130_fd_sc_hd__clkbuf (work@sky130_fd_sc_hd__clkbuf), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__clkbuf.functional.v, line:33:1, endln:49:10 |vpiDefName:work@buf |vpiName:buf1 |vpiFullName:work@sky130_fd_sc_hd__clkbuf.buf1 @@ -23839,7 +23839,7 @@ Processing: -cd cells/cells -DUNIT_DELAY -writepp -parse -nocache -nobuiltin -no design: (work@sky130_fd_sc_hd__o221a) |vpiName:work@sky130_fd_sc_hd__o221a |uhdmallModules: -\_module: work@sky130_fd_sc_hd__o221a (work@sky130_fd_sc_hd__o221a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o221a.functional.v, line:35:1, endln:63:10 +\_module_inst: work@sky130_fd_sc_hd__o221a (work@sky130_fd_sc_hd__o221a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o221a.functional.v, line:35:1, endln:63:10 |vpiParent: \_design: (work@sky130_fd_sc_hd__o221a) |vpiFullName:work@sky130_fd_sc_hd__o221a @@ -23847,64 +23847,64 @@ design: (work@sky130_fd_sc_hd__o221a) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o221a.or0_out), line:53:10, endln:53:17 |vpiParent: - \_module: work@sky130_fd_sc_hd__o221a (work@sky130_fd_sc_hd__o221a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o221a.functional.v, line:35:1, endln:63:10 + \_module_inst: work@sky130_fd_sc_hd__o221a (work@sky130_fd_sc_hd__o221a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o221a.functional.v, line:35:1, endln:63:10 |vpiName:or0_out |vpiFullName:work@sky130_fd_sc_hd__o221a.or0_out |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o221a.or1_out), line:54:10, endln:54:17 |vpiParent: - \_module: work@sky130_fd_sc_hd__o221a (work@sky130_fd_sc_hd__o221a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o221a.functional.v, line:35:1, endln:63:10 + \_module_inst: work@sky130_fd_sc_hd__o221a (work@sky130_fd_sc_hd__o221a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o221a.functional.v, line:35:1, endln:63:10 |vpiName:or1_out |vpiFullName:work@sky130_fd_sc_hd__o221a.or1_out |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o221a.and0_out_X), line:55:10, endln:55:20 |vpiParent: - \_module: work@sky130_fd_sc_hd__o221a (work@sky130_fd_sc_hd__o221a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o221a.functional.v, line:35:1, endln:63:10 + \_module_inst: work@sky130_fd_sc_hd__o221a (work@sky130_fd_sc_hd__o221a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o221a.functional.v, line:35:1, endln:63:10 |vpiName:and0_out_X |vpiFullName:work@sky130_fd_sc_hd__o221a.and0_out_X |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o221a.X), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__o221a (work@sky130_fd_sc_hd__o221a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o221a.functional.v, line:35:1, endln:63:10 + \_module_inst: work@sky130_fd_sc_hd__o221a (work@sky130_fd_sc_hd__o221a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o221a.functional.v, line:35:1, endln:63:10 |vpiName:X |vpiFullName:work@sky130_fd_sc_hd__o221a.X |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o221a.A1), line:37:5, endln:37:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o221a (work@sky130_fd_sc_hd__o221a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o221a.functional.v, line:35:1, endln:63:10 + \_module_inst: work@sky130_fd_sc_hd__o221a (work@sky130_fd_sc_hd__o221a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o221a.functional.v, line:35:1, endln:63:10 |vpiName:A1 |vpiFullName:work@sky130_fd_sc_hd__o221a.A1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o221a.A2), line:38:5, endln:38:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o221a (work@sky130_fd_sc_hd__o221a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o221a.functional.v, line:35:1, endln:63:10 + \_module_inst: work@sky130_fd_sc_hd__o221a (work@sky130_fd_sc_hd__o221a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o221a.functional.v, line:35:1, endln:63:10 |vpiName:A2 |vpiFullName:work@sky130_fd_sc_hd__o221a.A2 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o221a.B1), line:39:5, endln:39:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o221a (work@sky130_fd_sc_hd__o221a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o221a.functional.v, line:35:1, endln:63:10 + \_module_inst: work@sky130_fd_sc_hd__o221a (work@sky130_fd_sc_hd__o221a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o221a.functional.v, line:35:1, endln:63:10 |vpiName:B1 |vpiFullName:work@sky130_fd_sc_hd__o221a.B1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o221a.B2), line:40:5, endln:40:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o221a (work@sky130_fd_sc_hd__o221a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o221a.functional.v, line:35:1, endln:63:10 + \_module_inst: work@sky130_fd_sc_hd__o221a (work@sky130_fd_sc_hd__o221a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o221a.functional.v, line:35:1, endln:63:10 |vpiName:B2 |vpiFullName:work@sky130_fd_sc_hd__o221a.B2 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o221a.C1), line:41:5, endln:41:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o221a (work@sky130_fd_sc_hd__o221a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o221a.functional.v, line:35:1, endln:63:10 + \_module_inst: work@sky130_fd_sc_hd__o221a (work@sky130_fd_sc_hd__o221a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o221a.functional.v, line:35:1, endln:63:10 |vpiName:C1 |vpiFullName:work@sky130_fd_sc_hd__o221a.C1 |vpiPort: \_port: (X), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__o221a (work@sky130_fd_sc_hd__o221a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o221a.functional.v, line:35:1, endln:63:10 + \_module_inst: work@sky130_fd_sc_hd__o221a (work@sky130_fd_sc_hd__o221a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o221a.functional.v, line:35:1, endln:63:10 |vpiName:X |vpiDirection:2 |vpiLowConn: @@ -23916,7 +23916,7 @@ design: (work@sky130_fd_sc_hd__o221a) |vpiPort: \_port: (A1), line:37:5, endln:37:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o221a (work@sky130_fd_sc_hd__o221a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o221a.functional.v, line:35:1, endln:63:10 + \_module_inst: work@sky130_fd_sc_hd__o221a (work@sky130_fd_sc_hd__o221a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o221a.functional.v, line:35:1, endln:63:10 |vpiName:A1 |vpiDirection:1 |vpiLowConn: @@ -23928,7 +23928,7 @@ design: (work@sky130_fd_sc_hd__o221a) |vpiPort: \_port: (A2), line:38:5, endln:38:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o221a (work@sky130_fd_sc_hd__o221a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o221a.functional.v, line:35:1, endln:63:10 + \_module_inst: work@sky130_fd_sc_hd__o221a (work@sky130_fd_sc_hd__o221a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o221a.functional.v, line:35:1, endln:63:10 |vpiName:A2 |vpiDirection:1 |vpiLowConn: @@ -23940,7 +23940,7 @@ design: (work@sky130_fd_sc_hd__o221a) |vpiPort: \_port: (B1), line:39:5, endln:39:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o221a (work@sky130_fd_sc_hd__o221a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o221a.functional.v, line:35:1, endln:63:10 + \_module_inst: work@sky130_fd_sc_hd__o221a (work@sky130_fd_sc_hd__o221a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o221a.functional.v, line:35:1, endln:63:10 |vpiName:B1 |vpiDirection:1 |vpiLowConn: @@ -23952,7 +23952,7 @@ design: (work@sky130_fd_sc_hd__o221a) |vpiPort: \_port: (B2), line:40:5, endln:40:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o221a (work@sky130_fd_sc_hd__o221a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o221a.functional.v, line:35:1, endln:63:10 + \_module_inst: work@sky130_fd_sc_hd__o221a (work@sky130_fd_sc_hd__o221a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o221a.functional.v, line:35:1, endln:63:10 |vpiName:B2 |vpiDirection:1 |vpiLowConn: @@ -23964,7 +23964,7 @@ design: (work@sky130_fd_sc_hd__o221a) |vpiPort: \_port: (C1), line:41:5, endln:41:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o221a (work@sky130_fd_sc_hd__o221a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o221a.functional.v, line:35:1, endln:63:10 + \_module_inst: work@sky130_fd_sc_hd__o221a (work@sky130_fd_sc_hd__o221a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o221a.functional.v, line:35:1, endln:63:10 |vpiName:C1 |vpiDirection:1 |vpiLowConn: @@ -23974,14 +23974,14 @@ design: (work@sky130_fd_sc_hd__o221a) |vpiTypedef: \_logic_typespec: , line:50:12, endln:50:12 |uhdmtopModules: -\_module: work@sky130_fd_sc_hd__o221a (work@sky130_fd_sc_hd__o221a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o221a.functional.v, line:35:1, endln:63:10 +\_module_inst: work@sky130_fd_sc_hd__o221a (work@sky130_fd_sc_hd__o221a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o221a.functional.v, line:35:1, endln:63:10 |vpiName:work@sky130_fd_sc_hd__o221a |vpiDefName:work@sky130_fd_sc_hd__o221a |vpiTop:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o221a.or0_out), line:53:10, endln:53:17 |vpiParent: - \_module: work@sky130_fd_sc_hd__o221a (work@sky130_fd_sc_hd__o221a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o221a.functional.v, line:35:1, endln:63:10 + \_module_inst: work@sky130_fd_sc_hd__o221a (work@sky130_fd_sc_hd__o221a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o221a.functional.v, line:35:1, endln:63:10 |vpiTypespec: \_logic_typespec: , line:53:5, endln:53:9 |vpiName:or0_out @@ -23990,7 +23990,7 @@ design: (work@sky130_fd_sc_hd__o221a) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o221a.or1_out), line:54:10, endln:54:17 |vpiParent: - \_module: work@sky130_fd_sc_hd__o221a (work@sky130_fd_sc_hd__o221a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o221a.functional.v, line:35:1, endln:63:10 + \_module_inst: work@sky130_fd_sc_hd__o221a (work@sky130_fd_sc_hd__o221a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o221a.functional.v, line:35:1, endln:63:10 |vpiTypespec: \_logic_typespec: , line:54:5, endln:54:9 |vpiName:or1_out @@ -23999,7 +23999,7 @@ design: (work@sky130_fd_sc_hd__o221a) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o221a.and0_out_X), line:55:10, endln:55:20 |vpiParent: - \_module: work@sky130_fd_sc_hd__o221a (work@sky130_fd_sc_hd__o221a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o221a.functional.v, line:35:1, endln:63:10 + \_module_inst: work@sky130_fd_sc_hd__o221a (work@sky130_fd_sc_hd__o221a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o221a.functional.v, line:35:1, endln:63:10 |vpiTypespec: \_logic_typespec: , line:55:5, endln:55:9 |vpiName:and0_out_X @@ -24008,7 +24008,7 @@ design: (work@sky130_fd_sc_hd__o221a) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o221a.X), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__o221a (work@sky130_fd_sc_hd__o221a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o221a.functional.v, line:35:1, endln:63:10 + \_module_inst: work@sky130_fd_sc_hd__o221a (work@sky130_fd_sc_hd__o221a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o221a.functional.v, line:35:1, endln:63:10 |vpiTypespec: \_logic_typespec: , line:45:12, endln:45:12 |vpiName:X @@ -24016,7 +24016,7 @@ design: (work@sky130_fd_sc_hd__o221a) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o221a.A1), line:37:5, endln:37:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o221a (work@sky130_fd_sc_hd__o221a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o221a.functional.v, line:35:1, endln:63:10 + \_module_inst: work@sky130_fd_sc_hd__o221a (work@sky130_fd_sc_hd__o221a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o221a.functional.v, line:35:1, endln:63:10 |vpiTypespec: \_logic_typespec: , line:46:12, endln:46:12 |vpiName:A1 @@ -24024,7 +24024,7 @@ design: (work@sky130_fd_sc_hd__o221a) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o221a.A2), line:38:5, endln:38:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o221a (work@sky130_fd_sc_hd__o221a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o221a.functional.v, line:35:1, endln:63:10 + \_module_inst: work@sky130_fd_sc_hd__o221a (work@sky130_fd_sc_hd__o221a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o221a.functional.v, line:35:1, endln:63:10 |vpiTypespec: \_logic_typespec: , line:47:12, endln:47:12 |vpiName:A2 @@ -24032,7 +24032,7 @@ design: (work@sky130_fd_sc_hd__o221a) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o221a.B1), line:39:5, endln:39:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o221a (work@sky130_fd_sc_hd__o221a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o221a.functional.v, line:35:1, endln:63:10 + \_module_inst: work@sky130_fd_sc_hd__o221a (work@sky130_fd_sc_hd__o221a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o221a.functional.v, line:35:1, endln:63:10 |vpiTypespec: \_logic_typespec: , line:48:12, endln:48:12 |vpiName:B1 @@ -24040,7 +24040,7 @@ design: (work@sky130_fd_sc_hd__o221a) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o221a.B2), line:40:5, endln:40:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o221a (work@sky130_fd_sc_hd__o221a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o221a.functional.v, line:35:1, endln:63:10 + \_module_inst: work@sky130_fd_sc_hd__o221a (work@sky130_fd_sc_hd__o221a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o221a.functional.v, line:35:1, endln:63:10 |vpiTypespec: \_logic_typespec: , line:49:12, endln:49:12 |vpiName:B2 @@ -24048,7 +24048,7 @@ design: (work@sky130_fd_sc_hd__o221a) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o221a.C1), line:41:5, endln:41:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o221a (work@sky130_fd_sc_hd__o221a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o221a.functional.v, line:35:1, endln:63:10 + \_module_inst: work@sky130_fd_sc_hd__o221a (work@sky130_fd_sc_hd__o221a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o221a.functional.v, line:35:1, endln:63:10 |vpiTypespec: \_logic_typespec: , line:50:12, endln:50:12 |vpiName:C1 @@ -24057,7 +24057,7 @@ design: (work@sky130_fd_sc_hd__o221a) |vpiPort: \_port: (X), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__o221a (work@sky130_fd_sc_hd__o221a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o221a.functional.v, line:35:1, endln:63:10 + \_module_inst: work@sky130_fd_sc_hd__o221a (work@sky130_fd_sc_hd__o221a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o221a.functional.v, line:35:1, endln:63:10 |vpiName:X |vpiDirection:2 |vpiLowConn: @@ -24071,7 +24071,7 @@ design: (work@sky130_fd_sc_hd__o221a) |vpiPort: \_port: (A1), line:37:5, endln:37:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o221a (work@sky130_fd_sc_hd__o221a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o221a.functional.v, line:35:1, endln:63:10 + \_module_inst: work@sky130_fd_sc_hd__o221a (work@sky130_fd_sc_hd__o221a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o221a.functional.v, line:35:1, endln:63:10 |vpiName:A1 |vpiDirection:1 |vpiLowConn: @@ -24085,7 +24085,7 @@ design: (work@sky130_fd_sc_hd__o221a) |vpiPort: \_port: (A2), line:38:5, endln:38:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o221a (work@sky130_fd_sc_hd__o221a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o221a.functional.v, line:35:1, endln:63:10 + \_module_inst: work@sky130_fd_sc_hd__o221a (work@sky130_fd_sc_hd__o221a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o221a.functional.v, line:35:1, endln:63:10 |vpiName:A2 |vpiDirection:1 |vpiLowConn: @@ -24099,7 +24099,7 @@ design: (work@sky130_fd_sc_hd__o221a) |vpiPort: \_port: (B1), line:39:5, endln:39:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o221a (work@sky130_fd_sc_hd__o221a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o221a.functional.v, line:35:1, endln:63:10 + \_module_inst: work@sky130_fd_sc_hd__o221a (work@sky130_fd_sc_hd__o221a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o221a.functional.v, line:35:1, endln:63:10 |vpiName:B1 |vpiDirection:1 |vpiLowConn: @@ -24113,7 +24113,7 @@ design: (work@sky130_fd_sc_hd__o221a) |vpiPort: \_port: (B2), line:40:5, endln:40:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o221a (work@sky130_fd_sc_hd__o221a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o221a.functional.v, line:35:1, endln:63:10 + \_module_inst: work@sky130_fd_sc_hd__o221a (work@sky130_fd_sc_hd__o221a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o221a.functional.v, line:35:1, endln:63:10 |vpiName:B2 |vpiDirection:1 |vpiLowConn: @@ -24127,7 +24127,7 @@ design: (work@sky130_fd_sc_hd__o221a) |vpiPort: \_port: (C1), line:41:5, endln:41:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o221a (work@sky130_fd_sc_hd__o221a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o221a.functional.v, line:35:1, endln:63:10 + \_module_inst: work@sky130_fd_sc_hd__o221a (work@sky130_fd_sc_hd__o221a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o221a.functional.v, line:35:1, endln:63:10 |vpiName:C1 |vpiDirection:1 |vpiLowConn: @@ -24141,7 +24141,7 @@ design: (work@sky130_fd_sc_hd__o221a) |vpiPrimitive: \_gate: work@or (work@sky130_fd_sc_hd__o221a.or0), line:58:9, endln:58:48 |vpiParent: - \_module: work@sky130_fd_sc_hd__o221a (work@sky130_fd_sc_hd__o221a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o221a.functional.v, line:35:1, endln:63:10 + \_module_inst: work@sky130_fd_sc_hd__o221a (work@sky130_fd_sc_hd__o221a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o221a.functional.v, line:35:1, endln:63:10 |vpiDefName:work@or |vpiName:or0 |vpiFullName:work@sky130_fd_sc_hd__o221a.or0 @@ -24190,7 +24190,7 @@ design: (work@sky130_fd_sc_hd__o221a) |vpiPrimitive: \_gate: work@or (work@sky130_fd_sc_hd__o221a.or1), line:59:9, endln:59:48 |vpiParent: - \_module: work@sky130_fd_sc_hd__o221a (work@sky130_fd_sc_hd__o221a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o221a.functional.v, line:35:1, endln:63:10 + \_module_inst: work@sky130_fd_sc_hd__o221a (work@sky130_fd_sc_hd__o221a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o221a.functional.v, line:35:1, endln:63:10 |vpiDefName:work@or |vpiName:or1 |vpiFullName:work@sky130_fd_sc_hd__o221a.or1 @@ -24239,7 +24239,7 @@ design: (work@sky130_fd_sc_hd__o221a) |vpiPrimitive: \_gate: work@and (work@sky130_fd_sc_hd__o221a.and0), line:60:9, endln:60:48 |vpiParent: - \_module: work@sky130_fd_sc_hd__o221a (work@sky130_fd_sc_hd__o221a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o221a.functional.v, line:35:1, endln:63:10 + \_module_inst: work@sky130_fd_sc_hd__o221a (work@sky130_fd_sc_hd__o221a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o221a.functional.v, line:35:1, endln:63:10 |vpiDefName:work@and |vpiName:and0 |vpiFullName:work@sky130_fd_sc_hd__o221a.and0 @@ -24302,7 +24302,7 @@ design: (work@sky130_fd_sc_hd__o221a) |vpiPrimitive: \_gate: work@buf (work@sky130_fd_sc_hd__o221a.buf0), line:61:9, endln:61:48 |vpiParent: - \_module: work@sky130_fd_sc_hd__o221a (work@sky130_fd_sc_hd__o221a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o221a.functional.v, line:35:1, endln:63:10 + \_module_inst: work@sky130_fd_sc_hd__o221a (work@sky130_fd_sc_hd__o221a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o221a.functional.v, line:35:1, endln:63:10 |vpiDefName:work@buf |vpiName:buf0 |vpiFullName:work@sky130_fd_sc_hd__o221a.buf0 @@ -24345,7 +24345,7 @@ Processing: -cd cells/cells -DUNIT_DELAY -writepp -parse -nocache -nobuiltin -no design: (work@sky130_fd_sc_hd__o32ai) |vpiName:work@sky130_fd_sc_hd__o32ai |uhdmallModules: -\_module: work@sky130_fd_sc_hd__o32ai (work@sky130_fd_sc_hd__o32ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o32ai.functional.v, line:35:1, endln:63:10 +\_module_inst: work@sky130_fd_sc_hd__o32ai (work@sky130_fd_sc_hd__o32ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o32ai.functional.v, line:35:1, endln:63:10 |vpiParent: \_design: (work@sky130_fd_sc_hd__o32ai) |vpiFullName:work@sky130_fd_sc_hd__o32ai @@ -24353,64 +24353,64 @@ design: (work@sky130_fd_sc_hd__o32ai) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o32ai.nor0_out), line:53:10, endln:53:18 |vpiParent: - \_module: work@sky130_fd_sc_hd__o32ai (work@sky130_fd_sc_hd__o32ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o32ai.functional.v, line:35:1, endln:63:10 + \_module_inst: work@sky130_fd_sc_hd__o32ai (work@sky130_fd_sc_hd__o32ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o32ai.functional.v, line:35:1, endln:63:10 |vpiName:nor0_out |vpiFullName:work@sky130_fd_sc_hd__o32ai.nor0_out |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o32ai.nor1_out), line:54:10, endln:54:18 |vpiParent: - \_module: work@sky130_fd_sc_hd__o32ai (work@sky130_fd_sc_hd__o32ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o32ai.functional.v, line:35:1, endln:63:10 + \_module_inst: work@sky130_fd_sc_hd__o32ai (work@sky130_fd_sc_hd__o32ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o32ai.functional.v, line:35:1, endln:63:10 |vpiName:nor1_out |vpiFullName:work@sky130_fd_sc_hd__o32ai.nor1_out |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o32ai.or0_out_Y), line:55:10, endln:55:19 |vpiParent: - \_module: work@sky130_fd_sc_hd__o32ai (work@sky130_fd_sc_hd__o32ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o32ai.functional.v, line:35:1, endln:63:10 + \_module_inst: work@sky130_fd_sc_hd__o32ai (work@sky130_fd_sc_hd__o32ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o32ai.functional.v, line:35:1, endln:63:10 |vpiName:or0_out_Y |vpiFullName:work@sky130_fd_sc_hd__o32ai.or0_out_Y |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o32ai.Y), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__o32ai (work@sky130_fd_sc_hd__o32ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o32ai.functional.v, line:35:1, endln:63:10 + \_module_inst: work@sky130_fd_sc_hd__o32ai (work@sky130_fd_sc_hd__o32ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o32ai.functional.v, line:35:1, endln:63:10 |vpiName:Y |vpiFullName:work@sky130_fd_sc_hd__o32ai.Y |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o32ai.A1), line:37:5, endln:37:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o32ai (work@sky130_fd_sc_hd__o32ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o32ai.functional.v, line:35:1, endln:63:10 + \_module_inst: work@sky130_fd_sc_hd__o32ai (work@sky130_fd_sc_hd__o32ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o32ai.functional.v, line:35:1, endln:63:10 |vpiName:A1 |vpiFullName:work@sky130_fd_sc_hd__o32ai.A1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o32ai.A2), line:38:5, endln:38:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o32ai (work@sky130_fd_sc_hd__o32ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o32ai.functional.v, line:35:1, endln:63:10 + \_module_inst: work@sky130_fd_sc_hd__o32ai (work@sky130_fd_sc_hd__o32ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o32ai.functional.v, line:35:1, endln:63:10 |vpiName:A2 |vpiFullName:work@sky130_fd_sc_hd__o32ai.A2 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o32ai.A3), line:39:5, endln:39:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o32ai (work@sky130_fd_sc_hd__o32ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o32ai.functional.v, line:35:1, endln:63:10 + \_module_inst: work@sky130_fd_sc_hd__o32ai (work@sky130_fd_sc_hd__o32ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o32ai.functional.v, line:35:1, endln:63:10 |vpiName:A3 |vpiFullName:work@sky130_fd_sc_hd__o32ai.A3 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o32ai.B1), line:40:5, endln:40:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o32ai (work@sky130_fd_sc_hd__o32ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o32ai.functional.v, line:35:1, endln:63:10 + \_module_inst: work@sky130_fd_sc_hd__o32ai (work@sky130_fd_sc_hd__o32ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o32ai.functional.v, line:35:1, endln:63:10 |vpiName:B1 |vpiFullName:work@sky130_fd_sc_hd__o32ai.B1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o32ai.B2), line:41:5, endln:41:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o32ai (work@sky130_fd_sc_hd__o32ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o32ai.functional.v, line:35:1, endln:63:10 + \_module_inst: work@sky130_fd_sc_hd__o32ai (work@sky130_fd_sc_hd__o32ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o32ai.functional.v, line:35:1, endln:63:10 |vpiName:B2 |vpiFullName:work@sky130_fd_sc_hd__o32ai.B2 |vpiPort: \_port: (Y), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__o32ai (work@sky130_fd_sc_hd__o32ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o32ai.functional.v, line:35:1, endln:63:10 + \_module_inst: work@sky130_fd_sc_hd__o32ai (work@sky130_fd_sc_hd__o32ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o32ai.functional.v, line:35:1, endln:63:10 |vpiName:Y |vpiDirection:2 |vpiLowConn: @@ -24422,7 +24422,7 @@ design: (work@sky130_fd_sc_hd__o32ai) |vpiPort: \_port: (A1), line:37:5, endln:37:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o32ai (work@sky130_fd_sc_hd__o32ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o32ai.functional.v, line:35:1, endln:63:10 + \_module_inst: work@sky130_fd_sc_hd__o32ai (work@sky130_fd_sc_hd__o32ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o32ai.functional.v, line:35:1, endln:63:10 |vpiName:A1 |vpiDirection:1 |vpiLowConn: @@ -24434,7 +24434,7 @@ design: (work@sky130_fd_sc_hd__o32ai) |vpiPort: \_port: (A2), line:38:5, endln:38:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o32ai (work@sky130_fd_sc_hd__o32ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o32ai.functional.v, line:35:1, endln:63:10 + \_module_inst: work@sky130_fd_sc_hd__o32ai (work@sky130_fd_sc_hd__o32ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o32ai.functional.v, line:35:1, endln:63:10 |vpiName:A2 |vpiDirection:1 |vpiLowConn: @@ -24446,7 +24446,7 @@ design: (work@sky130_fd_sc_hd__o32ai) |vpiPort: \_port: (A3), line:39:5, endln:39:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o32ai (work@sky130_fd_sc_hd__o32ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o32ai.functional.v, line:35:1, endln:63:10 + \_module_inst: work@sky130_fd_sc_hd__o32ai (work@sky130_fd_sc_hd__o32ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o32ai.functional.v, line:35:1, endln:63:10 |vpiName:A3 |vpiDirection:1 |vpiLowConn: @@ -24458,7 +24458,7 @@ design: (work@sky130_fd_sc_hd__o32ai) |vpiPort: \_port: (B1), line:40:5, endln:40:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o32ai (work@sky130_fd_sc_hd__o32ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o32ai.functional.v, line:35:1, endln:63:10 + \_module_inst: work@sky130_fd_sc_hd__o32ai (work@sky130_fd_sc_hd__o32ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o32ai.functional.v, line:35:1, endln:63:10 |vpiName:B1 |vpiDirection:1 |vpiLowConn: @@ -24470,7 +24470,7 @@ design: (work@sky130_fd_sc_hd__o32ai) |vpiPort: \_port: (B2), line:41:5, endln:41:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o32ai (work@sky130_fd_sc_hd__o32ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o32ai.functional.v, line:35:1, endln:63:10 + \_module_inst: work@sky130_fd_sc_hd__o32ai (work@sky130_fd_sc_hd__o32ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o32ai.functional.v, line:35:1, endln:63:10 |vpiName:B2 |vpiDirection:1 |vpiLowConn: @@ -24480,14 +24480,14 @@ design: (work@sky130_fd_sc_hd__o32ai) |vpiTypedef: \_logic_typespec: , line:50:12, endln:50:12 |uhdmtopModules: -\_module: work@sky130_fd_sc_hd__o32ai (work@sky130_fd_sc_hd__o32ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o32ai.functional.v, line:35:1, endln:63:10 +\_module_inst: work@sky130_fd_sc_hd__o32ai (work@sky130_fd_sc_hd__o32ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o32ai.functional.v, line:35:1, endln:63:10 |vpiName:work@sky130_fd_sc_hd__o32ai |vpiDefName:work@sky130_fd_sc_hd__o32ai |vpiTop:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o32ai.nor0_out), line:53:10, endln:53:18 |vpiParent: - \_module: work@sky130_fd_sc_hd__o32ai (work@sky130_fd_sc_hd__o32ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o32ai.functional.v, line:35:1, endln:63:10 + \_module_inst: work@sky130_fd_sc_hd__o32ai (work@sky130_fd_sc_hd__o32ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o32ai.functional.v, line:35:1, endln:63:10 |vpiTypespec: \_logic_typespec: , line:53:5, endln:53:9 |vpiName:nor0_out @@ -24496,7 +24496,7 @@ design: (work@sky130_fd_sc_hd__o32ai) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o32ai.nor1_out), line:54:10, endln:54:18 |vpiParent: - \_module: work@sky130_fd_sc_hd__o32ai (work@sky130_fd_sc_hd__o32ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o32ai.functional.v, line:35:1, endln:63:10 + \_module_inst: work@sky130_fd_sc_hd__o32ai (work@sky130_fd_sc_hd__o32ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o32ai.functional.v, line:35:1, endln:63:10 |vpiTypespec: \_logic_typespec: , line:54:5, endln:54:9 |vpiName:nor1_out @@ -24505,7 +24505,7 @@ design: (work@sky130_fd_sc_hd__o32ai) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o32ai.or0_out_Y), line:55:10, endln:55:19 |vpiParent: - \_module: work@sky130_fd_sc_hd__o32ai (work@sky130_fd_sc_hd__o32ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o32ai.functional.v, line:35:1, endln:63:10 + \_module_inst: work@sky130_fd_sc_hd__o32ai (work@sky130_fd_sc_hd__o32ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o32ai.functional.v, line:35:1, endln:63:10 |vpiTypespec: \_logic_typespec: , line:55:5, endln:55:9 |vpiName:or0_out_Y @@ -24514,7 +24514,7 @@ design: (work@sky130_fd_sc_hd__o32ai) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o32ai.Y), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__o32ai (work@sky130_fd_sc_hd__o32ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o32ai.functional.v, line:35:1, endln:63:10 + \_module_inst: work@sky130_fd_sc_hd__o32ai (work@sky130_fd_sc_hd__o32ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o32ai.functional.v, line:35:1, endln:63:10 |vpiTypespec: \_logic_typespec: , line:45:12, endln:45:12 |vpiName:Y @@ -24522,7 +24522,7 @@ design: (work@sky130_fd_sc_hd__o32ai) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o32ai.A1), line:37:5, endln:37:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o32ai (work@sky130_fd_sc_hd__o32ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o32ai.functional.v, line:35:1, endln:63:10 + \_module_inst: work@sky130_fd_sc_hd__o32ai (work@sky130_fd_sc_hd__o32ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o32ai.functional.v, line:35:1, endln:63:10 |vpiTypespec: \_logic_typespec: , line:46:12, endln:46:12 |vpiName:A1 @@ -24530,7 +24530,7 @@ design: (work@sky130_fd_sc_hd__o32ai) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o32ai.A2), line:38:5, endln:38:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o32ai (work@sky130_fd_sc_hd__o32ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o32ai.functional.v, line:35:1, endln:63:10 + \_module_inst: work@sky130_fd_sc_hd__o32ai (work@sky130_fd_sc_hd__o32ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o32ai.functional.v, line:35:1, endln:63:10 |vpiTypespec: \_logic_typespec: , line:47:12, endln:47:12 |vpiName:A2 @@ -24538,7 +24538,7 @@ design: (work@sky130_fd_sc_hd__o32ai) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o32ai.A3), line:39:5, endln:39:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o32ai (work@sky130_fd_sc_hd__o32ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o32ai.functional.v, line:35:1, endln:63:10 + \_module_inst: work@sky130_fd_sc_hd__o32ai (work@sky130_fd_sc_hd__o32ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o32ai.functional.v, line:35:1, endln:63:10 |vpiTypespec: \_logic_typespec: , line:48:12, endln:48:12 |vpiName:A3 @@ -24546,7 +24546,7 @@ design: (work@sky130_fd_sc_hd__o32ai) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o32ai.B1), line:40:5, endln:40:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o32ai (work@sky130_fd_sc_hd__o32ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o32ai.functional.v, line:35:1, endln:63:10 + \_module_inst: work@sky130_fd_sc_hd__o32ai (work@sky130_fd_sc_hd__o32ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o32ai.functional.v, line:35:1, endln:63:10 |vpiTypespec: \_logic_typespec: , line:49:12, endln:49:12 |vpiName:B1 @@ -24554,7 +24554,7 @@ design: (work@sky130_fd_sc_hd__o32ai) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o32ai.B2), line:41:5, endln:41:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o32ai (work@sky130_fd_sc_hd__o32ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o32ai.functional.v, line:35:1, endln:63:10 + \_module_inst: work@sky130_fd_sc_hd__o32ai (work@sky130_fd_sc_hd__o32ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o32ai.functional.v, line:35:1, endln:63:10 |vpiTypespec: \_logic_typespec: , line:50:12, endln:50:12 |vpiName:B2 @@ -24563,7 +24563,7 @@ design: (work@sky130_fd_sc_hd__o32ai) |vpiPort: \_port: (Y), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__o32ai (work@sky130_fd_sc_hd__o32ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o32ai.functional.v, line:35:1, endln:63:10 + \_module_inst: work@sky130_fd_sc_hd__o32ai (work@sky130_fd_sc_hd__o32ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o32ai.functional.v, line:35:1, endln:63:10 |vpiName:Y |vpiDirection:2 |vpiLowConn: @@ -24577,7 +24577,7 @@ design: (work@sky130_fd_sc_hd__o32ai) |vpiPort: \_port: (A1), line:37:5, endln:37:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o32ai (work@sky130_fd_sc_hd__o32ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o32ai.functional.v, line:35:1, endln:63:10 + \_module_inst: work@sky130_fd_sc_hd__o32ai (work@sky130_fd_sc_hd__o32ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o32ai.functional.v, line:35:1, endln:63:10 |vpiName:A1 |vpiDirection:1 |vpiLowConn: @@ -24591,7 +24591,7 @@ design: (work@sky130_fd_sc_hd__o32ai) |vpiPort: \_port: (A2), line:38:5, endln:38:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o32ai (work@sky130_fd_sc_hd__o32ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o32ai.functional.v, line:35:1, endln:63:10 + \_module_inst: work@sky130_fd_sc_hd__o32ai (work@sky130_fd_sc_hd__o32ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o32ai.functional.v, line:35:1, endln:63:10 |vpiName:A2 |vpiDirection:1 |vpiLowConn: @@ -24605,7 +24605,7 @@ design: (work@sky130_fd_sc_hd__o32ai) |vpiPort: \_port: (A3), line:39:5, endln:39:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o32ai (work@sky130_fd_sc_hd__o32ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o32ai.functional.v, line:35:1, endln:63:10 + \_module_inst: work@sky130_fd_sc_hd__o32ai (work@sky130_fd_sc_hd__o32ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o32ai.functional.v, line:35:1, endln:63:10 |vpiName:A3 |vpiDirection:1 |vpiLowConn: @@ -24619,7 +24619,7 @@ design: (work@sky130_fd_sc_hd__o32ai) |vpiPort: \_port: (B1), line:40:5, endln:40:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o32ai (work@sky130_fd_sc_hd__o32ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o32ai.functional.v, line:35:1, endln:63:10 + \_module_inst: work@sky130_fd_sc_hd__o32ai (work@sky130_fd_sc_hd__o32ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o32ai.functional.v, line:35:1, endln:63:10 |vpiName:B1 |vpiDirection:1 |vpiLowConn: @@ -24633,7 +24633,7 @@ design: (work@sky130_fd_sc_hd__o32ai) |vpiPort: \_port: (B2), line:41:5, endln:41:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o32ai (work@sky130_fd_sc_hd__o32ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o32ai.functional.v, line:35:1, endln:63:10 + \_module_inst: work@sky130_fd_sc_hd__o32ai (work@sky130_fd_sc_hd__o32ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o32ai.functional.v, line:35:1, endln:63:10 |vpiName:B2 |vpiDirection:1 |vpiLowConn: @@ -24647,7 +24647,7 @@ design: (work@sky130_fd_sc_hd__o32ai) |vpiPrimitive: \_gate: work@nor (work@sky130_fd_sc_hd__o32ai.nor0), line:58:9, endln:58:45 |vpiParent: - \_module: work@sky130_fd_sc_hd__o32ai (work@sky130_fd_sc_hd__o32ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o32ai.functional.v, line:35:1, endln:63:10 + \_module_inst: work@sky130_fd_sc_hd__o32ai (work@sky130_fd_sc_hd__o32ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o32ai.functional.v, line:35:1, endln:63:10 |vpiDefName:work@nor |vpiName:nor0 |vpiFullName:work@sky130_fd_sc_hd__o32ai.nor0 @@ -24710,7 +24710,7 @@ design: (work@sky130_fd_sc_hd__o32ai) |vpiPrimitive: \_gate: work@nor (work@sky130_fd_sc_hd__o32ai.nor1), line:59:9, endln:59:45 |vpiParent: - \_module: work@sky130_fd_sc_hd__o32ai (work@sky130_fd_sc_hd__o32ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o32ai.functional.v, line:35:1, endln:63:10 + \_module_inst: work@sky130_fd_sc_hd__o32ai (work@sky130_fd_sc_hd__o32ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o32ai.functional.v, line:35:1, endln:63:10 |vpiDefName:work@nor |vpiName:nor1 |vpiFullName:work@sky130_fd_sc_hd__o32ai.nor1 @@ -24759,7 +24759,7 @@ design: (work@sky130_fd_sc_hd__o32ai) |vpiPrimitive: \_gate: work@or (work@sky130_fd_sc_hd__o32ai.or0), line:60:9, endln:60:45 |vpiParent: - \_module: work@sky130_fd_sc_hd__o32ai (work@sky130_fd_sc_hd__o32ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o32ai.functional.v, line:35:1, endln:63:10 + \_module_inst: work@sky130_fd_sc_hd__o32ai (work@sky130_fd_sc_hd__o32ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o32ai.functional.v, line:35:1, endln:63:10 |vpiDefName:work@or |vpiName:or0 |vpiFullName:work@sky130_fd_sc_hd__o32ai.or0 @@ -24808,7 +24808,7 @@ design: (work@sky130_fd_sc_hd__o32ai) |vpiPrimitive: \_gate: work@buf (work@sky130_fd_sc_hd__o32ai.buf0), line:61:9, endln:61:45 |vpiParent: - \_module: work@sky130_fd_sc_hd__o32ai (work@sky130_fd_sc_hd__o32ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o32ai.functional.v, line:35:1, endln:63:10 + \_module_inst: work@sky130_fd_sc_hd__o32ai (work@sky130_fd_sc_hd__o32ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o32ai.functional.v, line:35:1, endln:63:10 |vpiDefName:work@buf |vpiName:buf0 |vpiFullName:work@sky130_fd_sc_hd__o32ai.buf0 @@ -24851,7 +24851,7 @@ Processing: -cd cells/cells -DUNIT_DELAY -writepp -parse -nocache -nobuiltin -no design: (work@sky130_fd_sc_hd__lpflow_inputiso1n) |vpiName:work@sky130_fd_sc_hd__lpflow_inputiso1n |uhdmallModules: -\_module: work@sky130_fd_sc_hd__lpflow_inputiso1n (work@sky130_fd_sc_hd__lpflow_inputiso1n), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_inputiso1n.functional.v, line:35:1, endln:53:10 +\_module_inst: work@sky130_fd_sc_hd__lpflow_inputiso1n (work@sky130_fd_sc_hd__lpflow_inputiso1n), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_inputiso1n.functional.v, line:35:1, endln:53:10 |vpiParent: \_design: (work@sky130_fd_sc_hd__lpflow_inputiso1n) |vpiFullName:work@sky130_fd_sc_hd__lpflow_inputiso1n @@ -24859,32 +24859,32 @@ design: (work@sky130_fd_sc_hd__lpflow_inputiso1n) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__lpflow_inputiso1n.SLEEP), line:47:10, endln:47:15 |vpiParent: - \_module: work@sky130_fd_sc_hd__lpflow_inputiso1n (work@sky130_fd_sc_hd__lpflow_inputiso1n), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_inputiso1n.functional.v, line:35:1, endln:53:10 + \_module_inst: work@sky130_fd_sc_hd__lpflow_inputiso1n (work@sky130_fd_sc_hd__lpflow_inputiso1n), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_inputiso1n.functional.v, line:35:1, endln:53:10 |vpiName:SLEEP |vpiFullName:work@sky130_fd_sc_hd__lpflow_inputiso1n.SLEEP |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__lpflow_inputiso1n.X), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__lpflow_inputiso1n (work@sky130_fd_sc_hd__lpflow_inputiso1n), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_inputiso1n.functional.v, line:35:1, endln:53:10 + \_module_inst: work@sky130_fd_sc_hd__lpflow_inputiso1n (work@sky130_fd_sc_hd__lpflow_inputiso1n), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_inputiso1n.functional.v, line:35:1, endln:53:10 |vpiName:X |vpiFullName:work@sky130_fd_sc_hd__lpflow_inputiso1n.X |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__lpflow_inputiso1n.A), line:37:5, endln:37:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__lpflow_inputiso1n (work@sky130_fd_sc_hd__lpflow_inputiso1n), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_inputiso1n.functional.v, line:35:1, endln:53:10 + \_module_inst: work@sky130_fd_sc_hd__lpflow_inputiso1n (work@sky130_fd_sc_hd__lpflow_inputiso1n), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_inputiso1n.functional.v, line:35:1, endln:53:10 |vpiName:A |vpiFullName:work@sky130_fd_sc_hd__lpflow_inputiso1n.A |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__lpflow_inputiso1n.SLEEP_B), line:38:5, endln:38:12 |vpiParent: - \_module: work@sky130_fd_sc_hd__lpflow_inputiso1n (work@sky130_fd_sc_hd__lpflow_inputiso1n), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_inputiso1n.functional.v, line:35:1, endln:53:10 + \_module_inst: work@sky130_fd_sc_hd__lpflow_inputiso1n (work@sky130_fd_sc_hd__lpflow_inputiso1n), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_inputiso1n.functional.v, line:35:1, endln:53:10 |vpiName:SLEEP_B |vpiFullName:work@sky130_fd_sc_hd__lpflow_inputiso1n.SLEEP_B |vpiPort: \_port: (X), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__lpflow_inputiso1n (work@sky130_fd_sc_hd__lpflow_inputiso1n), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_inputiso1n.functional.v, line:35:1, endln:53:10 + \_module_inst: work@sky130_fd_sc_hd__lpflow_inputiso1n (work@sky130_fd_sc_hd__lpflow_inputiso1n), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_inputiso1n.functional.v, line:35:1, endln:53:10 |vpiName:X |vpiDirection:2 |vpiLowConn: @@ -24896,7 +24896,7 @@ design: (work@sky130_fd_sc_hd__lpflow_inputiso1n) |vpiPort: \_port: (A), line:37:5, endln:37:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__lpflow_inputiso1n (work@sky130_fd_sc_hd__lpflow_inputiso1n), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_inputiso1n.functional.v, line:35:1, endln:53:10 + \_module_inst: work@sky130_fd_sc_hd__lpflow_inputiso1n (work@sky130_fd_sc_hd__lpflow_inputiso1n), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_inputiso1n.functional.v, line:35:1, endln:53:10 |vpiName:A |vpiDirection:1 |vpiLowConn: @@ -24908,7 +24908,7 @@ design: (work@sky130_fd_sc_hd__lpflow_inputiso1n) |vpiPort: \_port: (SLEEP_B), line:38:5, endln:38:12 |vpiParent: - \_module: work@sky130_fd_sc_hd__lpflow_inputiso1n (work@sky130_fd_sc_hd__lpflow_inputiso1n), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_inputiso1n.functional.v, line:35:1, endln:53:10 + \_module_inst: work@sky130_fd_sc_hd__lpflow_inputiso1n (work@sky130_fd_sc_hd__lpflow_inputiso1n), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_inputiso1n.functional.v, line:35:1, endln:53:10 |vpiName:SLEEP_B |vpiDirection:1 |vpiLowConn: @@ -24918,14 +24918,14 @@ design: (work@sky130_fd_sc_hd__lpflow_inputiso1n) |vpiTypedef: \_logic_typespec: , line:44:12, endln:44:12 |uhdmtopModules: -\_module: work@sky130_fd_sc_hd__lpflow_inputiso1n (work@sky130_fd_sc_hd__lpflow_inputiso1n), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_inputiso1n.functional.v, line:35:1, endln:53:10 +\_module_inst: work@sky130_fd_sc_hd__lpflow_inputiso1n (work@sky130_fd_sc_hd__lpflow_inputiso1n), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_inputiso1n.functional.v, line:35:1, endln:53:10 |vpiName:work@sky130_fd_sc_hd__lpflow_inputiso1n |vpiDefName:work@sky130_fd_sc_hd__lpflow_inputiso1n |vpiTop:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__lpflow_inputiso1n.SLEEP), line:47:10, endln:47:15 |vpiParent: - \_module: work@sky130_fd_sc_hd__lpflow_inputiso1n (work@sky130_fd_sc_hd__lpflow_inputiso1n), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_inputiso1n.functional.v, line:35:1, endln:53:10 + \_module_inst: work@sky130_fd_sc_hd__lpflow_inputiso1n (work@sky130_fd_sc_hd__lpflow_inputiso1n), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_inputiso1n.functional.v, line:35:1, endln:53:10 |vpiTypespec: \_logic_typespec: , line:47:5, endln:47:9 |vpiName:SLEEP @@ -24934,7 +24934,7 @@ design: (work@sky130_fd_sc_hd__lpflow_inputiso1n) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__lpflow_inputiso1n.X), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__lpflow_inputiso1n (work@sky130_fd_sc_hd__lpflow_inputiso1n), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_inputiso1n.functional.v, line:35:1, endln:53:10 + \_module_inst: work@sky130_fd_sc_hd__lpflow_inputiso1n (work@sky130_fd_sc_hd__lpflow_inputiso1n), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_inputiso1n.functional.v, line:35:1, endln:53:10 |vpiTypespec: \_logic_typespec: , line:42:12, endln:42:12 |vpiName:X @@ -24942,7 +24942,7 @@ design: (work@sky130_fd_sc_hd__lpflow_inputiso1n) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__lpflow_inputiso1n.A), line:37:5, endln:37:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__lpflow_inputiso1n (work@sky130_fd_sc_hd__lpflow_inputiso1n), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_inputiso1n.functional.v, line:35:1, endln:53:10 + \_module_inst: work@sky130_fd_sc_hd__lpflow_inputiso1n (work@sky130_fd_sc_hd__lpflow_inputiso1n), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_inputiso1n.functional.v, line:35:1, endln:53:10 |vpiTypespec: \_logic_typespec: , line:43:12, endln:43:12 |vpiName:A @@ -24950,7 +24950,7 @@ design: (work@sky130_fd_sc_hd__lpflow_inputiso1n) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__lpflow_inputiso1n.SLEEP_B), line:38:5, endln:38:12 |vpiParent: - \_module: work@sky130_fd_sc_hd__lpflow_inputiso1n (work@sky130_fd_sc_hd__lpflow_inputiso1n), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_inputiso1n.functional.v, line:35:1, endln:53:10 + \_module_inst: work@sky130_fd_sc_hd__lpflow_inputiso1n (work@sky130_fd_sc_hd__lpflow_inputiso1n), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_inputiso1n.functional.v, line:35:1, endln:53:10 |vpiTypespec: \_logic_typespec: , line:44:12, endln:44:12 |vpiName:SLEEP_B @@ -24959,7 +24959,7 @@ design: (work@sky130_fd_sc_hd__lpflow_inputiso1n) |vpiPort: \_port: (X), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__lpflow_inputiso1n (work@sky130_fd_sc_hd__lpflow_inputiso1n), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_inputiso1n.functional.v, line:35:1, endln:53:10 + \_module_inst: work@sky130_fd_sc_hd__lpflow_inputiso1n (work@sky130_fd_sc_hd__lpflow_inputiso1n), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_inputiso1n.functional.v, line:35:1, endln:53:10 |vpiName:X |vpiDirection:2 |vpiLowConn: @@ -24973,7 +24973,7 @@ design: (work@sky130_fd_sc_hd__lpflow_inputiso1n) |vpiPort: \_port: (A), line:37:5, endln:37:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__lpflow_inputiso1n (work@sky130_fd_sc_hd__lpflow_inputiso1n), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_inputiso1n.functional.v, line:35:1, endln:53:10 + \_module_inst: work@sky130_fd_sc_hd__lpflow_inputiso1n (work@sky130_fd_sc_hd__lpflow_inputiso1n), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_inputiso1n.functional.v, line:35:1, endln:53:10 |vpiName:A |vpiDirection:1 |vpiLowConn: @@ -24987,7 +24987,7 @@ design: (work@sky130_fd_sc_hd__lpflow_inputiso1n) |vpiPort: \_port: (SLEEP_B), line:38:5, endln:38:12 |vpiParent: - \_module: work@sky130_fd_sc_hd__lpflow_inputiso1n (work@sky130_fd_sc_hd__lpflow_inputiso1n), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_inputiso1n.functional.v, line:35:1, endln:53:10 + \_module_inst: work@sky130_fd_sc_hd__lpflow_inputiso1n (work@sky130_fd_sc_hd__lpflow_inputiso1n), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_inputiso1n.functional.v, line:35:1, endln:53:10 |vpiName:SLEEP_B |vpiDirection:1 |vpiLowConn: @@ -25001,7 +25001,7 @@ design: (work@sky130_fd_sc_hd__lpflow_inputiso1n) |vpiPrimitive: \_gate: work@not (work@sky130_fd_sc_hd__lpflow_inputiso1n.not0), line:50:9, endln:50:39 |vpiParent: - \_module: work@sky130_fd_sc_hd__lpflow_inputiso1n (work@sky130_fd_sc_hd__lpflow_inputiso1n), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_inputiso1n.functional.v, line:35:1, endln:53:10 + \_module_inst: work@sky130_fd_sc_hd__lpflow_inputiso1n (work@sky130_fd_sc_hd__lpflow_inputiso1n), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_inputiso1n.functional.v, line:35:1, endln:53:10 |vpiDefName:work@not |vpiName:not0 |vpiFullName:work@sky130_fd_sc_hd__lpflow_inputiso1n.not0 @@ -25036,7 +25036,7 @@ design: (work@sky130_fd_sc_hd__lpflow_inputiso1n) |vpiPrimitive: \_gate: work@or (work@sky130_fd_sc_hd__lpflow_inputiso1n.or0), line:51:9, endln:51:39 |vpiParent: - \_module: work@sky130_fd_sc_hd__lpflow_inputiso1n (work@sky130_fd_sc_hd__lpflow_inputiso1n), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_inputiso1n.functional.v, line:35:1, endln:53:10 + \_module_inst: work@sky130_fd_sc_hd__lpflow_inputiso1n (work@sky130_fd_sc_hd__lpflow_inputiso1n), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_inputiso1n.functional.v, line:35:1, endln:53:10 |vpiDefName:work@or |vpiName:or0 |vpiFullName:work@sky130_fd_sc_hd__lpflow_inputiso1n.or0 @@ -25307,7 +25307,7 @@ design: (work@sky130_fd_sc_hd__sdfrtn) |vpiSize:3 |STRING:? 1 1 : 1 |uhdmallModules: -\_module: work@sky130_fd_sc_hd__sdfrtn (work@sky130_fd_sc_hd__sdfrtn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfrtn.functional.v, line:38:1, endln:68:10 +\_module_inst: work@sky130_fd_sc_hd__sdfrtn (work@sky130_fd_sc_hd__sdfrtn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfrtn.functional.v, line:38:1, endln:68:10 |vpiParent: \_design: (work@sky130_fd_sc_hd__sdfrtn) |vpiFullName:work@sky130_fd_sc_hd__sdfrtn @@ -25315,71 +25315,71 @@ design: (work@sky130_fd_sc_hd__sdfrtn) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__sdfrtn.buf_Q), line:56:10, endln:56:15 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfrtn (work@sky130_fd_sc_hd__sdfrtn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfrtn.functional.v, line:38:1, endln:68:10 + \_module_inst: work@sky130_fd_sc_hd__sdfrtn (work@sky130_fd_sc_hd__sdfrtn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfrtn.functional.v, line:38:1, endln:68:10 |vpiName:buf_Q |vpiFullName:work@sky130_fd_sc_hd__sdfrtn.buf_Q |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__sdfrtn.RESET), line:57:10, endln:57:15 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfrtn (work@sky130_fd_sc_hd__sdfrtn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfrtn.functional.v, line:38:1, endln:68:10 + \_module_inst: work@sky130_fd_sc_hd__sdfrtn (work@sky130_fd_sc_hd__sdfrtn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfrtn.functional.v, line:38:1, endln:68:10 |vpiName:RESET |vpiFullName:work@sky130_fd_sc_hd__sdfrtn.RESET |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__sdfrtn.intclk), line:58:10, endln:58:16 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfrtn (work@sky130_fd_sc_hd__sdfrtn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfrtn.functional.v, line:38:1, endln:68:10 + \_module_inst: work@sky130_fd_sc_hd__sdfrtn (work@sky130_fd_sc_hd__sdfrtn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfrtn.functional.v, line:38:1, endln:68:10 |vpiName:intclk |vpiFullName:work@sky130_fd_sc_hd__sdfrtn.intclk |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__sdfrtn.mux_out), line:59:10, endln:59:17 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfrtn (work@sky130_fd_sc_hd__sdfrtn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfrtn.functional.v, line:38:1, endln:68:10 + \_module_inst: work@sky130_fd_sc_hd__sdfrtn (work@sky130_fd_sc_hd__sdfrtn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfrtn.functional.v, line:38:1, endln:68:10 |vpiName:mux_out |vpiFullName:work@sky130_fd_sc_hd__sdfrtn.mux_out |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__sdfrtn.Q), line:39:5, endln:39:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfrtn (work@sky130_fd_sc_hd__sdfrtn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfrtn.functional.v, line:38:1, endln:68:10 + \_module_inst: work@sky130_fd_sc_hd__sdfrtn (work@sky130_fd_sc_hd__sdfrtn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfrtn.functional.v, line:38:1, endln:68:10 |vpiName:Q |vpiFullName:work@sky130_fd_sc_hd__sdfrtn.Q |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__sdfrtn.CLK_N), line:40:5, endln:40:10 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfrtn (work@sky130_fd_sc_hd__sdfrtn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfrtn.functional.v, line:38:1, endln:68:10 + \_module_inst: work@sky130_fd_sc_hd__sdfrtn (work@sky130_fd_sc_hd__sdfrtn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfrtn.functional.v, line:38:1, endln:68:10 |vpiName:CLK_N |vpiFullName:work@sky130_fd_sc_hd__sdfrtn.CLK_N |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__sdfrtn.D), line:41:5, endln:41:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfrtn (work@sky130_fd_sc_hd__sdfrtn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfrtn.functional.v, line:38:1, endln:68:10 + \_module_inst: work@sky130_fd_sc_hd__sdfrtn (work@sky130_fd_sc_hd__sdfrtn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfrtn.functional.v, line:38:1, endln:68:10 |vpiName:D |vpiFullName:work@sky130_fd_sc_hd__sdfrtn.D |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__sdfrtn.SCD), line:42:5, endln:42:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfrtn (work@sky130_fd_sc_hd__sdfrtn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfrtn.functional.v, line:38:1, endln:68:10 + \_module_inst: work@sky130_fd_sc_hd__sdfrtn (work@sky130_fd_sc_hd__sdfrtn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfrtn.functional.v, line:38:1, endln:68:10 |vpiName:SCD |vpiFullName:work@sky130_fd_sc_hd__sdfrtn.SCD |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__sdfrtn.SCE), line:43:5, endln:43:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfrtn (work@sky130_fd_sc_hd__sdfrtn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfrtn.functional.v, line:38:1, endln:68:10 + \_module_inst: work@sky130_fd_sc_hd__sdfrtn (work@sky130_fd_sc_hd__sdfrtn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfrtn.functional.v, line:38:1, endln:68:10 |vpiName:SCE |vpiFullName:work@sky130_fd_sc_hd__sdfrtn.SCE |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__sdfrtn.RESET_B), line:44:5, endln:44:12 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfrtn (work@sky130_fd_sc_hd__sdfrtn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfrtn.functional.v, line:38:1, endln:68:10 + \_module_inst: work@sky130_fd_sc_hd__sdfrtn (work@sky130_fd_sc_hd__sdfrtn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfrtn.functional.v, line:38:1, endln:68:10 |vpiName:RESET_B |vpiFullName:work@sky130_fd_sc_hd__sdfrtn.RESET_B |vpiPort: \_port: (Q), line:39:5, endln:39:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfrtn (work@sky130_fd_sc_hd__sdfrtn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfrtn.functional.v, line:38:1, endln:68:10 + \_module_inst: work@sky130_fd_sc_hd__sdfrtn (work@sky130_fd_sc_hd__sdfrtn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfrtn.functional.v, line:38:1, endln:68:10 |vpiName:Q |vpiDirection:2 |vpiLowConn: @@ -25391,7 +25391,7 @@ design: (work@sky130_fd_sc_hd__sdfrtn) |vpiPort: \_port: (CLK_N), line:40:5, endln:40:10 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfrtn (work@sky130_fd_sc_hd__sdfrtn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfrtn.functional.v, line:38:1, endln:68:10 + \_module_inst: work@sky130_fd_sc_hd__sdfrtn (work@sky130_fd_sc_hd__sdfrtn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfrtn.functional.v, line:38:1, endln:68:10 |vpiName:CLK_N |vpiDirection:1 |vpiLowConn: @@ -25403,7 +25403,7 @@ design: (work@sky130_fd_sc_hd__sdfrtn) |vpiPort: \_port: (D), line:41:5, endln:41:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfrtn (work@sky130_fd_sc_hd__sdfrtn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfrtn.functional.v, line:38:1, endln:68:10 + \_module_inst: work@sky130_fd_sc_hd__sdfrtn (work@sky130_fd_sc_hd__sdfrtn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfrtn.functional.v, line:38:1, endln:68:10 |vpiName:D |vpiDirection:1 |vpiLowConn: @@ -25415,7 +25415,7 @@ design: (work@sky130_fd_sc_hd__sdfrtn) |vpiPort: \_port: (SCD), line:42:5, endln:42:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfrtn (work@sky130_fd_sc_hd__sdfrtn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfrtn.functional.v, line:38:1, endln:68:10 + \_module_inst: work@sky130_fd_sc_hd__sdfrtn (work@sky130_fd_sc_hd__sdfrtn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfrtn.functional.v, line:38:1, endln:68:10 |vpiName:SCD |vpiDirection:1 |vpiLowConn: @@ -25427,7 +25427,7 @@ design: (work@sky130_fd_sc_hd__sdfrtn) |vpiPort: \_port: (SCE), line:43:5, endln:43:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfrtn (work@sky130_fd_sc_hd__sdfrtn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfrtn.functional.v, line:38:1, endln:68:10 + \_module_inst: work@sky130_fd_sc_hd__sdfrtn (work@sky130_fd_sc_hd__sdfrtn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfrtn.functional.v, line:38:1, endln:68:10 |vpiName:SCE |vpiDirection:1 |vpiLowConn: @@ -25439,7 +25439,7 @@ design: (work@sky130_fd_sc_hd__sdfrtn) |vpiPort: \_port: (RESET_B), line:44:5, endln:44:12 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfrtn (work@sky130_fd_sc_hd__sdfrtn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfrtn.functional.v, line:38:1, endln:68:10 + \_module_inst: work@sky130_fd_sc_hd__sdfrtn (work@sky130_fd_sc_hd__sdfrtn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfrtn.functional.v, line:38:1, endln:68:10 |vpiName:RESET_B |vpiDirection:1 |vpiLowConn: @@ -25449,14 +25449,14 @@ design: (work@sky130_fd_sc_hd__sdfrtn) |vpiTypedef: \_logic_typespec: , line:53:12, endln:53:12 |uhdmtopModules: -\_module: work@sky130_fd_sc_hd__sdfrtn (work@sky130_fd_sc_hd__sdfrtn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfrtn.functional.v, line:38:1, endln:68:10 +\_module_inst: work@sky130_fd_sc_hd__sdfrtn (work@sky130_fd_sc_hd__sdfrtn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfrtn.functional.v, line:38:1, endln:68:10 |vpiName:work@sky130_fd_sc_hd__sdfrtn |vpiDefName:work@sky130_fd_sc_hd__sdfrtn |vpiTop:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__sdfrtn.buf_Q), line:56:10, endln:56:15 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfrtn (work@sky130_fd_sc_hd__sdfrtn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfrtn.functional.v, line:38:1, endln:68:10 + \_module_inst: work@sky130_fd_sc_hd__sdfrtn (work@sky130_fd_sc_hd__sdfrtn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfrtn.functional.v, line:38:1, endln:68:10 |vpiTypespec: \_logic_typespec: , line:56:5, endln:56:9 |vpiName:buf_Q @@ -25465,7 +25465,7 @@ design: (work@sky130_fd_sc_hd__sdfrtn) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__sdfrtn.RESET), line:57:10, endln:57:15 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfrtn (work@sky130_fd_sc_hd__sdfrtn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfrtn.functional.v, line:38:1, endln:68:10 + \_module_inst: work@sky130_fd_sc_hd__sdfrtn (work@sky130_fd_sc_hd__sdfrtn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfrtn.functional.v, line:38:1, endln:68:10 |vpiTypespec: \_logic_typespec: , line:57:5, endln:57:9 |vpiName:RESET @@ -25474,7 +25474,7 @@ design: (work@sky130_fd_sc_hd__sdfrtn) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__sdfrtn.intclk), line:58:10, endln:58:16 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfrtn (work@sky130_fd_sc_hd__sdfrtn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfrtn.functional.v, line:38:1, endln:68:10 + \_module_inst: work@sky130_fd_sc_hd__sdfrtn (work@sky130_fd_sc_hd__sdfrtn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfrtn.functional.v, line:38:1, endln:68:10 |vpiTypespec: \_logic_typespec: , line:58:5, endln:58:9 |vpiName:intclk @@ -25483,7 +25483,7 @@ design: (work@sky130_fd_sc_hd__sdfrtn) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__sdfrtn.mux_out), line:59:10, endln:59:17 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfrtn (work@sky130_fd_sc_hd__sdfrtn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfrtn.functional.v, line:38:1, endln:68:10 + \_module_inst: work@sky130_fd_sc_hd__sdfrtn (work@sky130_fd_sc_hd__sdfrtn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfrtn.functional.v, line:38:1, endln:68:10 |vpiTypespec: \_logic_typespec: , line:59:5, endln:59:9 |vpiName:mux_out @@ -25492,7 +25492,7 @@ design: (work@sky130_fd_sc_hd__sdfrtn) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__sdfrtn.Q), line:39:5, endln:39:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfrtn (work@sky130_fd_sc_hd__sdfrtn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfrtn.functional.v, line:38:1, endln:68:10 + \_module_inst: work@sky130_fd_sc_hd__sdfrtn (work@sky130_fd_sc_hd__sdfrtn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfrtn.functional.v, line:38:1, endln:68:10 |vpiTypespec: \_logic_typespec: , line:48:12, endln:48:12 |vpiName:Q @@ -25500,7 +25500,7 @@ design: (work@sky130_fd_sc_hd__sdfrtn) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__sdfrtn.CLK_N), line:40:5, endln:40:10 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfrtn (work@sky130_fd_sc_hd__sdfrtn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfrtn.functional.v, line:38:1, endln:68:10 + \_module_inst: work@sky130_fd_sc_hd__sdfrtn (work@sky130_fd_sc_hd__sdfrtn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfrtn.functional.v, line:38:1, endln:68:10 |vpiTypespec: \_logic_typespec: , line:49:12, endln:49:12 |vpiName:CLK_N @@ -25508,7 +25508,7 @@ design: (work@sky130_fd_sc_hd__sdfrtn) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__sdfrtn.D), line:41:5, endln:41:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfrtn (work@sky130_fd_sc_hd__sdfrtn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfrtn.functional.v, line:38:1, endln:68:10 + \_module_inst: work@sky130_fd_sc_hd__sdfrtn (work@sky130_fd_sc_hd__sdfrtn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfrtn.functional.v, line:38:1, endln:68:10 |vpiTypespec: \_logic_typespec: , line:50:12, endln:50:12 |vpiName:D @@ -25516,7 +25516,7 @@ design: (work@sky130_fd_sc_hd__sdfrtn) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__sdfrtn.SCD), line:42:5, endln:42:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfrtn (work@sky130_fd_sc_hd__sdfrtn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfrtn.functional.v, line:38:1, endln:68:10 + \_module_inst: work@sky130_fd_sc_hd__sdfrtn (work@sky130_fd_sc_hd__sdfrtn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfrtn.functional.v, line:38:1, endln:68:10 |vpiTypespec: \_logic_typespec: , line:51:12, endln:51:12 |vpiName:SCD @@ -25524,7 +25524,7 @@ design: (work@sky130_fd_sc_hd__sdfrtn) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__sdfrtn.SCE), line:43:5, endln:43:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfrtn (work@sky130_fd_sc_hd__sdfrtn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfrtn.functional.v, line:38:1, endln:68:10 + \_module_inst: work@sky130_fd_sc_hd__sdfrtn (work@sky130_fd_sc_hd__sdfrtn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfrtn.functional.v, line:38:1, endln:68:10 |vpiTypespec: \_logic_typespec: , line:52:12, endln:52:12 |vpiName:SCE @@ -25532,7 +25532,7 @@ design: (work@sky130_fd_sc_hd__sdfrtn) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__sdfrtn.RESET_B), line:44:5, endln:44:12 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfrtn (work@sky130_fd_sc_hd__sdfrtn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfrtn.functional.v, line:38:1, endln:68:10 + \_module_inst: work@sky130_fd_sc_hd__sdfrtn (work@sky130_fd_sc_hd__sdfrtn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfrtn.functional.v, line:38:1, endln:68:10 |vpiTypespec: \_logic_typespec: , line:53:12, endln:53:12 |vpiName:RESET_B @@ -25541,7 +25541,7 @@ design: (work@sky130_fd_sc_hd__sdfrtn) |vpiPort: \_port: (Q), line:39:5, endln:39:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfrtn (work@sky130_fd_sc_hd__sdfrtn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfrtn.functional.v, line:38:1, endln:68:10 + \_module_inst: work@sky130_fd_sc_hd__sdfrtn (work@sky130_fd_sc_hd__sdfrtn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfrtn.functional.v, line:38:1, endln:68:10 |vpiName:Q |vpiDirection:2 |vpiLowConn: @@ -25555,7 +25555,7 @@ design: (work@sky130_fd_sc_hd__sdfrtn) |vpiPort: \_port: (CLK_N), line:40:5, endln:40:10 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfrtn (work@sky130_fd_sc_hd__sdfrtn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfrtn.functional.v, line:38:1, endln:68:10 + \_module_inst: work@sky130_fd_sc_hd__sdfrtn (work@sky130_fd_sc_hd__sdfrtn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfrtn.functional.v, line:38:1, endln:68:10 |vpiName:CLK_N |vpiDirection:1 |vpiLowConn: @@ -25569,7 +25569,7 @@ design: (work@sky130_fd_sc_hd__sdfrtn) |vpiPort: \_port: (D), line:41:5, endln:41:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfrtn (work@sky130_fd_sc_hd__sdfrtn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfrtn.functional.v, line:38:1, endln:68:10 + \_module_inst: work@sky130_fd_sc_hd__sdfrtn (work@sky130_fd_sc_hd__sdfrtn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfrtn.functional.v, line:38:1, endln:68:10 |vpiName:D |vpiDirection:1 |vpiLowConn: @@ -25583,7 +25583,7 @@ design: (work@sky130_fd_sc_hd__sdfrtn) |vpiPort: \_port: (SCD), line:42:5, endln:42:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfrtn (work@sky130_fd_sc_hd__sdfrtn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfrtn.functional.v, line:38:1, endln:68:10 + \_module_inst: work@sky130_fd_sc_hd__sdfrtn (work@sky130_fd_sc_hd__sdfrtn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfrtn.functional.v, line:38:1, endln:68:10 |vpiName:SCD |vpiDirection:1 |vpiLowConn: @@ -25597,7 +25597,7 @@ design: (work@sky130_fd_sc_hd__sdfrtn) |vpiPort: \_port: (SCE), line:43:5, endln:43:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfrtn (work@sky130_fd_sc_hd__sdfrtn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfrtn.functional.v, line:38:1, endln:68:10 + \_module_inst: work@sky130_fd_sc_hd__sdfrtn (work@sky130_fd_sc_hd__sdfrtn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfrtn.functional.v, line:38:1, endln:68:10 |vpiName:SCE |vpiDirection:1 |vpiLowConn: @@ -25611,7 +25611,7 @@ design: (work@sky130_fd_sc_hd__sdfrtn) |vpiPort: \_port: (RESET_B), line:44:5, endln:44:12 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfrtn (work@sky130_fd_sc_hd__sdfrtn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfrtn.functional.v, line:38:1, endln:68:10 + \_module_inst: work@sky130_fd_sc_hd__sdfrtn (work@sky130_fd_sc_hd__sdfrtn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfrtn.functional.v, line:38:1, endln:68:10 |vpiName:RESET_B |vpiDirection:1 |vpiLowConn: @@ -25625,7 +25625,7 @@ design: (work@sky130_fd_sc_hd__sdfrtn) |vpiPrimitive: \_gate: work@not (work@sky130_fd_sc_hd__sdfrtn.not0), line:62:47, endln:62:90 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfrtn (work@sky130_fd_sc_hd__sdfrtn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfrtn.functional.v, line:38:1, endln:68:10 + \_module_inst: work@sky130_fd_sc_hd__sdfrtn (work@sky130_fd_sc_hd__sdfrtn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfrtn.functional.v, line:38:1, endln:68:10 |vpiDefName:work@not |vpiName:not0 |vpiFullName:work@sky130_fd_sc_hd__sdfrtn.not0 @@ -25660,7 +25660,7 @@ design: (work@sky130_fd_sc_hd__sdfrtn) |vpiPrimitive: \_gate: work@not (work@sky130_fd_sc_hd__sdfrtn.not1), line:63:47, endln:63:90 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfrtn (work@sky130_fd_sc_hd__sdfrtn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfrtn.functional.v, line:38:1, endln:68:10 + \_module_inst: work@sky130_fd_sc_hd__sdfrtn (work@sky130_fd_sc_hd__sdfrtn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfrtn.functional.v, line:38:1, endln:68:10 |vpiDefName:work@not |vpiName:not1 |vpiFullName:work@sky130_fd_sc_hd__sdfrtn.not1 @@ -25695,7 +25695,7 @@ design: (work@sky130_fd_sc_hd__sdfrtn) |vpiPrimitive: \_udp: work@sky130_fd_sc_hd__udp_mux_2to1 (work@sky130_fd_sc_hd__sdfrtn.mux_2to10), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfrtn.functional.v, line:64:5, endln:64:91 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfrtn (work@sky130_fd_sc_hd__sdfrtn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfrtn.functional.v, line:38:1, endln:68:10 + \_module_inst: work@sky130_fd_sc_hd__sdfrtn (work@sky130_fd_sc_hd__sdfrtn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfrtn.functional.v, line:38:1, endln:68:10 |vpiDefName:work@sky130_fd_sc_hd__udp_mux_2to1 |vpiName:mux_2to10 |vpiFullName:work@sky130_fd_sc_hd__sdfrtn.mux_2to10 @@ -25704,7 +25704,7 @@ design: (work@sky130_fd_sc_hd__sdfrtn) |vpiPrimitive: \_udp: work@sky130_fd_sc_hd__udp_dff$PR (work@sky130_fd_sc_hd__sdfrtn.dff0), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfrtn.functional.v, line:65:5, endln:65:80 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfrtn (work@sky130_fd_sc_hd__sdfrtn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfrtn.functional.v, line:38:1, endln:68:10 + \_module_inst: work@sky130_fd_sc_hd__sdfrtn (work@sky130_fd_sc_hd__sdfrtn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfrtn.functional.v, line:38:1, endln:68:10 |vpiDefName:work@sky130_fd_sc_hd__udp_dff$PR |vpiName:dff0 |vpiFullName:work@sky130_fd_sc_hd__sdfrtn.dff0 @@ -25713,7 +25713,7 @@ design: (work@sky130_fd_sc_hd__sdfrtn) |vpiPrimitive: \_gate: work@buf (work@sky130_fd_sc_hd__sdfrtn.buf0), line:66:47, endln:66:90 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfrtn (work@sky130_fd_sc_hd__sdfrtn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfrtn.functional.v, line:38:1, endln:68:10 + \_module_inst: work@sky130_fd_sc_hd__sdfrtn (work@sky130_fd_sc_hd__sdfrtn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfrtn.functional.v, line:38:1, endln:68:10 |vpiDefName:work@buf |vpiName:buf0 |vpiFullName:work@sky130_fd_sc_hd__sdfrtn.buf0 @@ -25756,7 +25756,7 @@ Processing: -cd cells/cells -DUNIT_DELAY -writepp -parse -nocache -nobuiltin -no design: (work@sky130_fd_sc_hd__nor4b) |vpiName:work@sky130_fd_sc_hd__nor4b |uhdmallModules: -\_module: work@sky130_fd_sc_hd__nor4b (work@sky130_fd_sc_hd__nor4b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor4b.functional.v, line:33:1, endln:57:10 +\_module_inst: work@sky130_fd_sc_hd__nor4b (work@sky130_fd_sc_hd__nor4b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor4b.functional.v, line:33:1, endln:57:10 |vpiParent: \_design: (work@sky130_fd_sc_hd__nor4b) |vpiFullName:work@sky130_fd_sc_hd__nor4b @@ -25764,51 +25764,51 @@ design: (work@sky130_fd_sc_hd__nor4b) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__nor4b.not0_out), line:49:10, endln:49:18 |vpiParent: - \_module: work@sky130_fd_sc_hd__nor4b (work@sky130_fd_sc_hd__nor4b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor4b.functional.v, line:33:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__nor4b (work@sky130_fd_sc_hd__nor4b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor4b.functional.v, line:33:1, endln:57:10 |vpiName:not0_out |vpiFullName:work@sky130_fd_sc_hd__nor4b.not0_out |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__nor4b.nor0_out_Y), line:50:10, endln:50:20 |vpiParent: - \_module: work@sky130_fd_sc_hd__nor4b (work@sky130_fd_sc_hd__nor4b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor4b.functional.v, line:33:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__nor4b (work@sky130_fd_sc_hd__nor4b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor4b.functional.v, line:33:1, endln:57:10 |vpiName:nor0_out_Y |vpiFullName:work@sky130_fd_sc_hd__nor4b.nor0_out_Y |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__nor4b.Y), line:34:5, endln:34:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__nor4b (work@sky130_fd_sc_hd__nor4b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor4b.functional.v, line:33:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__nor4b (work@sky130_fd_sc_hd__nor4b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor4b.functional.v, line:33:1, endln:57:10 |vpiName:Y |vpiFullName:work@sky130_fd_sc_hd__nor4b.Y |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__nor4b.A), line:35:5, endln:35:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__nor4b (work@sky130_fd_sc_hd__nor4b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor4b.functional.v, line:33:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__nor4b (work@sky130_fd_sc_hd__nor4b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor4b.functional.v, line:33:1, endln:57:10 |vpiName:A |vpiFullName:work@sky130_fd_sc_hd__nor4b.A |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__nor4b.B), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__nor4b (work@sky130_fd_sc_hd__nor4b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor4b.functional.v, line:33:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__nor4b (work@sky130_fd_sc_hd__nor4b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor4b.functional.v, line:33:1, endln:57:10 |vpiName:B |vpiFullName:work@sky130_fd_sc_hd__nor4b.B |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__nor4b.C), line:37:5, endln:37:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__nor4b (work@sky130_fd_sc_hd__nor4b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor4b.functional.v, line:33:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__nor4b (work@sky130_fd_sc_hd__nor4b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor4b.functional.v, line:33:1, endln:57:10 |vpiName:C |vpiFullName:work@sky130_fd_sc_hd__nor4b.C |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__nor4b.D_N), line:38:5, endln:38:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__nor4b (work@sky130_fd_sc_hd__nor4b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor4b.functional.v, line:33:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__nor4b (work@sky130_fd_sc_hd__nor4b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor4b.functional.v, line:33:1, endln:57:10 |vpiName:D_N |vpiFullName:work@sky130_fd_sc_hd__nor4b.D_N |vpiPort: \_port: (Y), line:34:5, endln:34:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__nor4b (work@sky130_fd_sc_hd__nor4b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor4b.functional.v, line:33:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__nor4b (work@sky130_fd_sc_hd__nor4b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor4b.functional.v, line:33:1, endln:57:10 |vpiName:Y |vpiDirection:2 |vpiLowConn: @@ -25820,7 +25820,7 @@ design: (work@sky130_fd_sc_hd__nor4b) |vpiPort: \_port: (A), line:35:5, endln:35:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__nor4b (work@sky130_fd_sc_hd__nor4b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor4b.functional.v, line:33:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__nor4b (work@sky130_fd_sc_hd__nor4b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor4b.functional.v, line:33:1, endln:57:10 |vpiName:A |vpiDirection:1 |vpiLowConn: @@ -25832,7 +25832,7 @@ design: (work@sky130_fd_sc_hd__nor4b) |vpiPort: \_port: (B), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__nor4b (work@sky130_fd_sc_hd__nor4b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor4b.functional.v, line:33:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__nor4b (work@sky130_fd_sc_hd__nor4b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor4b.functional.v, line:33:1, endln:57:10 |vpiName:B |vpiDirection:1 |vpiLowConn: @@ -25844,7 +25844,7 @@ design: (work@sky130_fd_sc_hd__nor4b) |vpiPort: \_port: (C), line:37:5, endln:37:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__nor4b (work@sky130_fd_sc_hd__nor4b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor4b.functional.v, line:33:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__nor4b (work@sky130_fd_sc_hd__nor4b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor4b.functional.v, line:33:1, endln:57:10 |vpiName:C |vpiDirection:1 |vpiLowConn: @@ -25856,7 +25856,7 @@ design: (work@sky130_fd_sc_hd__nor4b) |vpiPort: \_port: (D_N), line:38:5, endln:38:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__nor4b (work@sky130_fd_sc_hd__nor4b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor4b.functional.v, line:33:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__nor4b (work@sky130_fd_sc_hd__nor4b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor4b.functional.v, line:33:1, endln:57:10 |vpiName:D_N |vpiDirection:1 |vpiLowConn: @@ -25866,14 +25866,14 @@ design: (work@sky130_fd_sc_hd__nor4b) |vpiTypedef: \_logic_typespec: , line:46:12, endln:46:12 |uhdmtopModules: -\_module: work@sky130_fd_sc_hd__nor4b (work@sky130_fd_sc_hd__nor4b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor4b.functional.v, line:33:1, endln:57:10 +\_module_inst: work@sky130_fd_sc_hd__nor4b (work@sky130_fd_sc_hd__nor4b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor4b.functional.v, line:33:1, endln:57:10 |vpiName:work@sky130_fd_sc_hd__nor4b |vpiDefName:work@sky130_fd_sc_hd__nor4b |vpiTop:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__nor4b.not0_out), line:49:10, endln:49:18 |vpiParent: - \_module: work@sky130_fd_sc_hd__nor4b (work@sky130_fd_sc_hd__nor4b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor4b.functional.v, line:33:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__nor4b (work@sky130_fd_sc_hd__nor4b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor4b.functional.v, line:33:1, endln:57:10 |vpiTypespec: \_logic_typespec: , line:49:5, endln:49:9 |vpiName:not0_out @@ -25882,7 +25882,7 @@ design: (work@sky130_fd_sc_hd__nor4b) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__nor4b.nor0_out_Y), line:50:10, endln:50:20 |vpiParent: - \_module: work@sky130_fd_sc_hd__nor4b (work@sky130_fd_sc_hd__nor4b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor4b.functional.v, line:33:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__nor4b (work@sky130_fd_sc_hd__nor4b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor4b.functional.v, line:33:1, endln:57:10 |vpiTypespec: \_logic_typespec: , line:50:5, endln:50:9 |vpiName:nor0_out_Y @@ -25891,7 +25891,7 @@ design: (work@sky130_fd_sc_hd__nor4b) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__nor4b.Y), line:34:5, endln:34:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__nor4b (work@sky130_fd_sc_hd__nor4b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor4b.functional.v, line:33:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__nor4b (work@sky130_fd_sc_hd__nor4b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor4b.functional.v, line:33:1, endln:57:10 |vpiTypespec: \_logic_typespec: , line:42:12, endln:42:12 |vpiName:Y @@ -25899,7 +25899,7 @@ design: (work@sky130_fd_sc_hd__nor4b) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__nor4b.A), line:35:5, endln:35:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__nor4b (work@sky130_fd_sc_hd__nor4b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor4b.functional.v, line:33:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__nor4b (work@sky130_fd_sc_hd__nor4b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor4b.functional.v, line:33:1, endln:57:10 |vpiTypespec: \_logic_typespec: , line:43:12, endln:43:12 |vpiName:A @@ -25907,7 +25907,7 @@ design: (work@sky130_fd_sc_hd__nor4b) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__nor4b.B), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__nor4b (work@sky130_fd_sc_hd__nor4b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor4b.functional.v, line:33:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__nor4b (work@sky130_fd_sc_hd__nor4b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor4b.functional.v, line:33:1, endln:57:10 |vpiTypespec: \_logic_typespec: , line:44:12, endln:44:12 |vpiName:B @@ -25915,7 +25915,7 @@ design: (work@sky130_fd_sc_hd__nor4b) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__nor4b.C), line:37:5, endln:37:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__nor4b (work@sky130_fd_sc_hd__nor4b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor4b.functional.v, line:33:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__nor4b (work@sky130_fd_sc_hd__nor4b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor4b.functional.v, line:33:1, endln:57:10 |vpiTypespec: \_logic_typespec: , line:45:12, endln:45:12 |vpiName:C @@ -25923,7 +25923,7 @@ design: (work@sky130_fd_sc_hd__nor4b) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__nor4b.D_N), line:38:5, endln:38:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__nor4b (work@sky130_fd_sc_hd__nor4b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor4b.functional.v, line:33:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__nor4b (work@sky130_fd_sc_hd__nor4b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor4b.functional.v, line:33:1, endln:57:10 |vpiTypespec: \_logic_typespec: , line:46:12, endln:46:12 |vpiName:D_N @@ -25932,7 +25932,7 @@ design: (work@sky130_fd_sc_hd__nor4b) |vpiPort: \_port: (Y), line:34:5, endln:34:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__nor4b (work@sky130_fd_sc_hd__nor4b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor4b.functional.v, line:33:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__nor4b (work@sky130_fd_sc_hd__nor4b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor4b.functional.v, line:33:1, endln:57:10 |vpiName:Y |vpiDirection:2 |vpiLowConn: @@ -25946,7 +25946,7 @@ design: (work@sky130_fd_sc_hd__nor4b) |vpiPort: \_port: (A), line:35:5, endln:35:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__nor4b (work@sky130_fd_sc_hd__nor4b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor4b.functional.v, line:33:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__nor4b (work@sky130_fd_sc_hd__nor4b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor4b.functional.v, line:33:1, endln:57:10 |vpiName:A |vpiDirection:1 |vpiLowConn: @@ -25960,7 +25960,7 @@ design: (work@sky130_fd_sc_hd__nor4b) |vpiPort: \_port: (B), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__nor4b (work@sky130_fd_sc_hd__nor4b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor4b.functional.v, line:33:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__nor4b (work@sky130_fd_sc_hd__nor4b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor4b.functional.v, line:33:1, endln:57:10 |vpiName:B |vpiDirection:1 |vpiLowConn: @@ -25974,7 +25974,7 @@ design: (work@sky130_fd_sc_hd__nor4b) |vpiPort: \_port: (C), line:37:5, endln:37:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__nor4b (work@sky130_fd_sc_hd__nor4b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor4b.functional.v, line:33:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__nor4b (work@sky130_fd_sc_hd__nor4b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor4b.functional.v, line:33:1, endln:57:10 |vpiName:C |vpiDirection:1 |vpiLowConn: @@ -25988,7 +25988,7 @@ design: (work@sky130_fd_sc_hd__nor4b) |vpiPort: \_port: (D_N), line:38:5, endln:38:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__nor4b (work@sky130_fd_sc_hd__nor4b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor4b.functional.v, line:33:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__nor4b (work@sky130_fd_sc_hd__nor4b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor4b.functional.v, line:33:1, endln:57:10 |vpiName:D_N |vpiDirection:1 |vpiLowConn: @@ -26002,7 +26002,7 @@ design: (work@sky130_fd_sc_hd__nor4b) |vpiPrimitive: \_gate: work@not (work@sky130_fd_sc_hd__nor4b.not0), line:53:9, endln:53:45 |vpiParent: - \_module: work@sky130_fd_sc_hd__nor4b (work@sky130_fd_sc_hd__nor4b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor4b.functional.v, line:33:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__nor4b (work@sky130_fd_sc_hd__nor4b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor4b.functional.v, line:33:1, endln:57:10 |vpiDefName:work@not |vpiName:not0 |vpiFullName:work@sky130_fd_sc_hd__nor4b.not0 @@ -26037,7 +26037,7 @@ design: (work@sky130_fd_sc_hd__nor4b) |vpiPrimitive: \_gate: work@nor (work@sky130_fd_sc_hd__nor4b.nor0), line:54:9, endln:54:45 |vpiParent: - \_module: work@sky130_fd_sc_hd__nor4b (work@sky130_fd_sc_hd__nor4b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor4b.functional.v, line:33:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__nor4b (work@sky130_fd_sc_hd__nor4b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor4b.functional.v, line:33:1, endln:57:10 |vpiDefName:work@nor |vpiName:nor0 |vpiFullName:work@sky130_fd_sc_hd__nor4b.nor0 @@ -26114,7 +26114,7 @@ design: (work@sky130_fd_sc_hd__nor4b) |vpiPrimitive: \_gate: work@buf (work@sky130_fd_sc_hd__nor4b.buf0), line:55:9, endln:55:45 |vpiParent: - \_module: work@sky130_fd_sc_hd__nor4b (work@sky130_fd_sc_hd__nor4b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor4b.functional.v, line:33:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__nor4b (work@sky130_fd_sc_hd__nor4b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor4b.functional.v, line:33:1, endln:57:10 |vpiDefName:work@buf |vpiName:buf0 |vpiFullName:work@sky130_fd_sc_hd__nor4b.buf0 @@ -26157,7 +26157,7 @@ Processing: -cd cells/cells -DUNIT_DELAY -writepp -parse -nocache -nobuiltin -no design: (work@sky130_fd_sc_hd__a2111o) |vpiName:work@sky130_fd_sc_hd__a2111o |uhdmallModules: -\_module: work@sky130_fd_sc_hd__a2111o (work@sky130_fd_sc_hd__a2111o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a2111o.functional.v, line:35:1, endln:61:10 +\_module_inst: work@sky130_fd_sc_hd__a2111o (work@sky130_fd_sc_hd__a2111o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a2111o.functional.v, line:35:1, endln:61:10 |vpiParent: \_design: (work@sky130_fd_sc_hd__a2111o) |vpiFullName:work@sky130_fd_sc_hd__a2111o @@ -26165,57 +26165,57 @@ design: (work@sky130_fd_sc_hd__a2111o) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a2111o.and0_out), line:53:10, endln:53:18 |vpiParent: - \_module: work@sky130_fd_sc_hd__a2111o (work@sky130_fd_sc_hd__a2111o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a2111o.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__a2111o (work@sky130_fd_sc_hd__a2111o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a2111o.functional.v, line:35:1, endln:61:10 |vpiName:and0_out |vpiFullName:work@sky130_fd_sc_hd__a2111o.and0_out |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a2111o.or0_out_X), line:54:10, endln:54:19 |vpiParent: - \_module: work@sky130_fd_sc_hd__a2111o (work@sky130_fd_sc_hd__a2111o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a2111o.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__a2111o (work@sky130_fd_sc_hd__a2111o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a2111o.functional.v, line:35:1, endln:61:10 |vpiName:or0_out_X |vpiFullName:work@sky130_fd_sc_hd__a2111o.or0_out_X |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a2111o.X), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__a2111o (work@sky130_fd_sc_hd__a2111o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a2111o.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__a2111o (work@sky130_fd_sc_hd__a2111o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a2111o.functional.v, line:35:1, endln:61:10 |vpiName:X |vpiFullName:work@sky130_fd_sc_hd__a2111o.X |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a2111o.A1), line:37:5, endln:37:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a2111o (work@sky130_fd_sc_hd__a2111o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a2111o.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__a2111o (work@sky130_fd_sc_hd__a2111o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a2111o.functional.v, line:35:1, endln:61:10 |vpiName:A1 |vpiFullName:work@sky130_fd_sc_hd__a2111o.A1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a2111o.A2), line:38:5, endln:38:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a2111o (work@sky130_fd_sc_hd__a2111o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a2111o.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__a2111o (work@sky130_fd_sc_hd__a2111o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a2111o.functional.v, line:35:1, endln:61:10 |vpiName:A2 |vpiFullName:work@sky130_fd_sc_hd__a2111o.A2 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a2111o.B1), line:39:5, endln:39:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a2111o (work@sky130_fd_sc_hd__a2111o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a2111o.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__a2111o (work@sky130_fd_sc_hd__a2111o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a2111o.functional.v, line:35:1, endln:61:10 |vpiName:B1 |vpiFullName:work@sky130_fd_sc_hd__a2111o.B1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a2111o.C1), line:40:5, endln:40:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a2111o (work@sky130_fd_sc_hd__a2111o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a2111o.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__a2111o (work@sky130_fd_sc_hd__a2111o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a2111o.functional.v, line:35:1, endln:61:10 |vpiName:C1 |vpiFullName:work@sky130_fd_sc_hd__a2111o.C1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a2111o.D1), line:41:5, endln:41:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a2111o (work@sky130_fd_sc_hd__a2111o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a2111o.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__a2111o (work@sky130_fd_sc_hd__a2111o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a2111o.functional.v, line:35:1, endln:61:10 |vpiName:D1 |vpiFullName:work@sky130_fd_sc_hd__a2111o.D1 |vpiPort: \_port: (X), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__a2111o (work@sky130_fd_sc_hd__a2111o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a2111o.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__a2111o (work@sky130_fd_sc_hd__a2111o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a2111o.functional.v, line:35:1, endln:61:10 |vpiName:X |vpiDirection:2 |vpiLowConn: @@ -26227,7 +26227,7 @@ design: (work@sky130_fd_sc_hd__a2111o) |vpiPort: \_port: (A1), line:37:5, endln:37:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a2111o (work@sky130_fd_sc_hd__a2111o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a2111o.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__a2111o (work@sky130_fd_sc_hd__a2111o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a2111o.functional.v, line:35:1, endln:61:10 |vpiName:A1 |vpiDirection:1 |vpiLowConn: @@ -26239,7 +26239,7 @@ design: (work@sky130_fd_sc_hd__a2111o) |vpiPort: \_port: (A2), line:38:5, endln:38:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a2111o (work@sky130_fd_sc_hd__a2111o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a2111o.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__a2111o (work@sky130_fd_sc_hd__a2111o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a2111o.functional.v, line:35:1, endln:61:10 |vpiName:A2 |vpiDirection:1 |vpiLowConn: @@ -26251,7 +26251,7 @@ design: (work@sky130_fd_sc_hd__a2111o) |vpiPort: \_port: (B1), line:39:5, endln:39:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a2111o (work@sky130_fd_sc_hd__a2111o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a2111o.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__a2111o (work@sky130_fd_sc_hd__a2111o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a2111o.functional.v, line:35:1, endln:61:10 |vpiName:B1 |vpiDirection:1 |vpiLowConn: @@ -26263,7 +26263,7 @@ design: (work@sky130_fd_sc_hd__a2111o) |vpiPort: \_port: (C1), line:40:5, endln:40:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a2111o (work@sky130_fd_sc_hd__a2111o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a2111o.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__a2111o (work@sky130_fd_sc_hd__a2111o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a2111o.functional.v, line:35:1, endln:61:10 |vpiName:C1 |vpiDirection:1 |vpiLowConn: @@ -26275,7 +26275,7 @@ design: (work@sky130_fd_sc_hd__a2111o) |vpiPort: \_port: (D1), line:41:5, endln:41:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a2111o (work@sky130_fd_sc_hd__a2111o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a2111o.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__a2111o (work@sky130_fd_sc_hd__a2111o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a2111o.functional.v, line:35:1, endln:61:10 |vpiName:D1 |vpiDirection:1 |vpiLowConn: @@ -26285,14 +26285,14 @@ design: (work@sky130_fd_sc_hd__a2111o) |vpiTypedef: \_logic_typespec: , line:50:12, endln:50:12 |uhdmtopModules: -\_module: work@sky130_fd_sc_hd__a2111o (work@sky130_fd_sc_hd__a2111o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a2111o.functional.v, line:35:1, endln:61:10 +\_module_inst: work@sky130_fd_sc_hd__a2111o (work@sky130_fd_sc_hd__a2111o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a2111o.functional.v, line:35:1, endln:61:10 |vpiName:work@sky130_fd_sc_hd__a2111o |vpiDefName:work@sky130_fd_sc_hd__a2111o |vpiTop:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a2111o.and0_out), line:53:10, endln:53:18 |vpiParent: - \_module: work@sky130_fd_sc_hd__a2111o (work@sky130_fd_sc_hd__a2111o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a2111o.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__a2111o (work@sky130_fd_sc_hd__a2111o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a2111o.functional.v, line:35:1, endln:61:10 |vpiTypespec: \_logic_typespec: , line:53:5, endln:53:9 |vpiName:and0_out @@ -26301,7 +26301,7 @@ design: (work@sky130_fd_sc_hd__a2111o) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a2111o.or0_out_X), line:54:10, endln:54:19 |vpiParent: - \_module: work@sky130_fd_sc_hd__a2111o (work@sky130_fd_sc_hd__a2111o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a2111o.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__a2111o (work@sky130_fd_sc_hd__a2111o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a2111o.functional.v, line:35:1, endln:61:10 |vpiTypespec: \_logic_typespec: , line:54:5, endln:54:9 |vpiName:or0_out_X @@ -26310,7 +26310,7 @@ design: (work@sky130_fd_sc_hd__a2111o) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a2111o.X), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__a2111o (work@sky130_fd_sc_hd__a2111o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a2111o.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__a2111o (work@sky130_fd_sc_hd__a2111o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a2111o.functional.v, line:35:1, endln:61:10 |vpiTypespec: \_logic_typespec: , line:45:12, endln:45:12 |vpiName:X @@ -26318,7 +26318,7 @@ design: (work@sky130_fd_sc_hd__a2111o) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a2111o.A1), line:37:5, endln:37:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a2111o (work@sky130_fd_sc_hd__a2111o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a2111o.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__a2111o (work@sky130_fd_sc_hd__a2111o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a2111o.functional.v, line:35:1, endln:61:10 |vpiTypespec: \_logic_typespec: , line:46:12, endln:46:12 |vpiName:A1 @@ -26326,7 +26326,7 @@ design: (work@sky130_fd_sc_hd__a2111o) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a2111o.A2), line:38:5, endln:38:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a2111o (work@sky130_fd_sc_hd__a2111o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a2111o.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__a2111o (work@sky130_fd_sc_hd__a2111o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a2111o.functional.v, line:35:1, endln:61:10 |vpiTypespec: \_logic_typespec: , line:47:12, endln:47:12 |vpiName:A2 @@ -26334,7 +26334,7 @@ design: (work@sky130_fd_sc_hd__a2111o) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a2111o.B1), line:39:5, endln:39:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a2111o (work@sky130_fd_sc_hd__a2111o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a2111o.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__a2111o (work@sky130_fd_sc_hd__a2111o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a2111o.functional.v, line:35:1, endln:61:10 |vpiTypespec: \_logic_typespec: , line:48:12, endln:48:12 |vpiName:B1 @@ -26342,7 +26342,7 @@ design: (work@sky130_fd_sc_hd__a2111o) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a2111o.C1), line:40:5, endln:40:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a2111o (work@sky130_fd_sc_hd__a2111o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a2111o.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__a2111o (work@sky130_fd_sc_hd__a2111o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a2111o.functional.v, line:35:1, endln:61:10 |vpiTypespec: \_logic_typespec: , line:49:12, endln:49:12 |vpiName:C1 @@ -26350,7 +26350,7 @@ design: (work@sky130_fd_sc_hd__a2111o) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a2111o.D1), line:41:5, endln:41:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a2111o (work@sky130_fd_sc_hd__a2111o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a2111o.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__a2111o (work@sky130_fd_sc_hd__a2111o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a2111o.functional.v, line:35:1, endln:61:10 |vpiTypespec: \_logic_typespec: , line:50:12, endln:50:12 |vpiName:D1 @@ -26359,7 +26359,7 @@ design: (work@sky130_fd_sc_hd__a2111o) |vpiPort: \_port: (X), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__a2111o (work@sky130_fd_sc_hd__a2111o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a2111o.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__a2111o (work@sky130_fd_sc_hd__a2111o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a2111o.functional.v, line:35:1, endln:61:10 |vpiName:X |vpiDirection:2 |vpiLowConn: @@ -26373,7 +26373,7 @@ design: (work@sky130_fd_sc_hd__a2111o) |vpiPort: \_port: (A1), line:37:5, endln:37:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a2111o (work@sky130_fd_sc_hd__a2111o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a2111o.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__a2111o (work@sky130_fd_sc_hd__a2111o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a2111o.functional.v, line:35:1, endln:61:10 |vpiName:A1 |vpiDirection:1 |vpiLowConn: @@ -26387,7 +26387,7 @@ design: (work@sky130_fd_sc_hd__a2111o) |vpiPort: \_port: (A2), line:38:5, endln:38:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a2111o (work@sky130_fd_sc_hd__a2111o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a2111o.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__a2111o (work@sky130_fd_sc_hd__a2111o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a2111o.functional.v, line:35:1, endln:61:10 |vpiName:A2 |vpiDirection:1 |vpiLowConn: @@ -26401,7 +26401,7 @@ design: (work@sky130_fd_sc_hd__a2111o) |vpiPort: \_port: (B1), line:39:5, endln:39:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a2111o (work@sky130_fd_sc_hd__a2111o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a2111o.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__a2111o (work@sky130_fd_sc_hd__a2111o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a2111o.functional.v, line:35:1, endln:61:10 |vpiName:B1 |vpiDirection:1 |vpiLowConn: @@ -26415,7 +26415,7 @@ design: (work@sky130_fd_sc_hd__a2111o) |vpiPort: \_port: (C1), line:40:5, endln:40:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a2111o (work@sky130_fd_sc_hd__a2111o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a2111o.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__a2111o (work@sky130_fd_sc_hd__a2111o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a2111o.functional.v, line:35:1, endln:61:10 |vpiName:C1 |vpiDirection:1 |vpiLowConn: @@ -26429,7 +26429,7 @@ design: (work@sky130_fd_sc_hd__a2111o) |vpiPort: \_port: (D1), line:41:5, endln:41:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a2111o (work@sky130_fd_sc_hd__a2111o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a2111o.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__a2111o (work@sky130_fd_sc_hd__a2111o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a2111o.functional.v, line:35:1, endln:61:10 |vpiName:D1 |vpiDirection:1 |vpiLowConn: @@ -26443,7 +26443,7 @@ design: (work@sky130_fd_sc_hd__a2111o) |vpiPrimitive: \_gate: work@and (work@sky130_fd_sc_hd__a2111o.and0), line:57:9, endln:57:47 |vpiParent: - \_module: work@sky130_fd_sc_hd__a2111o (work@sky130_fd_sc_hd__a2111o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a2111o.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__a2111o (work@sky130_fd_sc_hd__a2111o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a2111o.functional.v, line:35:1, endln:61:10 |vpiDefName:work@and |vpiName:and0 |vpiFullName:work@sky130_fd_sc_hd__a2111o.and0 @@ -26492,7 +26492,7 @@ design: (work@sky130_fd_sc_hd__a2111o) |vpiPrimitive: \_gate: work@or (work@sky130_fd_sc_hd__a2111o.or0), line:58:9, endln:58:47 |vpiParent: - \_module: work@sky130_fd_sc_hd__a2111o (work@sky130_fd_sc_hd__a2111o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a2111o.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__a2111o (work@sky130_fd_sc_hd__a2111o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a2111o.functional.v, line:35:1, endln:61:10 |vpiDefName:work@or |vpiName:or0 |vpiFullName:work@sky130_fd_sc_hd__a2111o.or0 @@ -26569,7 +26569,7 @@ design: (work@sky130_fd_sc_hd__a2111o) |vpiPrimitive: \_gate: work@buf (work@sky130_fd_sc_hd__a2111o.buf0), line:59:9, endln:59:47 |vpiParent: - \_module: work@sky130_fd_sc_hd__a2111o (work@sky130_fd_sc_hd__a2111o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a2111o.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__a2111o (work@sky130_fd_sc_hd__a2111o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a2111o.functional.v, line:35:1, endln:61:10 |vpiDefName:work@buf |vpiName:buf0 |vpiFullName:work@sky130_fd_sc_hd__a2111o.buf0 @@ -26612,7 +26612,7 @@ Processing: -cd cells/cells -DUNIT_DELAY -writepp -parse -nocache -nobuiltin -no design: (work@sky130_fd_sc_hd__nand4) |vpiName:work@sky130_fd_sc_hd__nand4 |uhdmallModules: -\_module: work@sky130_fd_sc_hd__nand4 (work@sky130_fd_sc_hd__nand4), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand4.functional.v, line:33:1, endln:55:10 +\_module_inst: work@sky130_fd_sc_hd__nand4 (work@sky130_fd_sc_hd__nand4), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand4.functional.v, line:33:1, endln:55:10 |vpiParent: \_design: (work@sky130_fd_sc_hd__nand4) |vpiFullName:work@sky130_fd_sc_hd__nand4 @@ -26620,44 +26620,44 @@ design: (work@sky130_fd_sc_hd__nand4) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__nand4.nand0_out_Y), line:49:10, endln:49:21 |vpiParent: - \_module: work@sky130_fd_sc_hd__nand4 (work@sky130_fd_sc_hd__nand4), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand4.functional.v, line:33:1, endln:55:10 + \_module_inst: work@sky130_fd_sc_hd__nand4 (work@sky130_fd_sc_hd__nand4), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand4.functional.v, line:33:1, endln:55:10 |vpiName:nand0_out_Y |vpiFullName:work@sky130_fd_sc_hd__nand4.nand0_out_Y |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__nand4.Y), line:34:5, endln:34:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__nand4 (work@sky130_fd_sc_hd__nand4), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand4.functional.v, line:33:1, endln:55:10 + \_module_inst: work@sky130_fd_sc_hd__nand4 (work@sky130_fd_sc_hd__nand4), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand4.functional.v, line:33:1, endln:55:10 |vpiName:Y |vpiFullName:work@sky130_fd_sc_hd__nand4.Y |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__nand4.A), line:35:5, endln:35:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__nand4 (work@sky130_fd_sc_hd__nand4), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand4.functional.v, line:33:1, endln:55:10 + \_module_inst: work@sky130_fd_sc_hd__nand4 (work@sky130_fd_sc_hd__nand4), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand4.functional.v, line:33:1, endln:55:10 |vpiName:A |vpiFullName:work@sky130_fd_sc_hd__nand4.A |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__nand4.B), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__nand4 (work@sky130_fd_sc_hd__nand4), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand4.functional.v, line:33:1, endln:55:10 + \_module_inst: work@sky130_fd_sc_hd__nand4 (work@sky130_fd_sc_hd__nand4), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand4.functional.v, line:33:1, endln:55:10 |vpiName:B |vpiFullName:work@sky130_fd_sc_hd__nand4.B |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__nand4.C), line:37:5, endln:37:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__nand4 (work@sky130_fd_sc_hd__nand4), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand4.functional.v, line:33:1, endln:55:10 + \_module_inst: work@sky130_fd_sc_hd__nand4 (work@sky130_fd_sc_hd__nand4), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand4.functional.v, line:33:1, endln:55:10 |vpiName:C |vpiFullName:work@sky130_fd_sc_hd__nand4.C |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__nand4.D), line:38:5, endln:38:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__nand4 (work@sky130_fd_sc_hd__nand4), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand4.functional.v, line:33:1, endln:55:10 + \_module_inst: work@sky130_fd_sc_hd__nand4 (work@sky130_fd_sc_hd__nand4), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand4.functional.v, line:33:1, endln:55:10 |vpiName:D |vpiFullName:work@sky130_fd_sc_hd__nand4.D |vpiPort: \_port: (Y), line:34:5, endln:34:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__nand4 (work@sky130_fd_sc_hd__nand4), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand4.functional.v, line:33:1, endln:55:10 + \_module_inst: work@sky130_fd_sc_hd__nand4 (work@sky130_fd_sc_hd__nand4), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand4.functional.v, line:33:1, endln:55:10 |vpiName:Y |vpiDirection:2 |vpiLowConn: @@ -26669,7 +26669,7 @@ design: (work@sky130_fd_sc_hd__nand4) |vpiPort: \_port: (A), line:35:5, endln:35:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__nand4 (work@sky130_fd_sc_hd__nand4), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand4.functional.v, line:33:1, endln:55:10 + \_module_inst: work@sky130_fd_sc_hd__nand4 (work@sky130_fd_sc_hd__nand4), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand4.functional.v, line:33:1, endln:55:10 |vpiName:A |vpiDirection:1 |vpiLowConn: @@ -26681,7 +26681,7 @@ design: (work@sky130_fd_sc_hd__nand4) |vpiPort: \_port: (B), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__nand4 (work@sky130_fd_sc_hd__nand4), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand4.functional.v, line:33:1, endln:55:10 + \_module_inst: work@sky130_fd_sc_hd__nand4 (work@sky130_fd_sc_hd__nand4), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand4.functional.v, line:33:1, endln:55:10 |vpiName:B |vpiDirection:1 |vpiLowConn: @@ -26693,7 +26693,7 @@ design: (work@sky130_fd_sc_hd__nand4) |vpiPort: \_port: (C), line:37:5, endln:37:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__nand4 (work@sky130_fd_sc_hd__nand4), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand4.functional.v, line:33:1, endln:55:10 + \_module_inst: work@sky130_fd_sc_hd__nand4 (work@sky130_fd_sc_hd__nand4), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand4.functional.v, line:33:1, endln:55:10 |vpiName:C |vpiDirection:1 |vpiLowConn: @@ -26705,7 +26705,7 @@ design: (work@sky130_fd_sc_hd__nand4) |vpiPort: \_port: (D), line:38:5, endln:38:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__nand4 (work@sky130_fd_sc_hd__nand4), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand4.functional.v, line:33:1, endln:55:10 + \_module_inst: work@sky130_fd_sc_hd__nand4 (work@sky130_fd_sc_hd__nand4), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand4.functional.v, line:33:1, endln:55:10 |vpiName:D |vpiDirection:1 |vpiLowConn: @@ -26715,14 +26715,14 @@ design: (work@sky130_fd_sc_hd__nand4) |vpiTypedef: \_logic_typespec: , line:46:12, endln:46:12 |uhdmtopModules: -\_module: work@sky130_fd_sc_hd__nand4 (work@sky130_fd_sc_hd__nand4), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand4.functional.v, line:33:1, endln:55:10 +\_module_inst: work@sky130_fd_sc_hd__nand4 (work@sky130_fd_sc_hd__nand4), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand4.functional.v, line:33:1, endln:55:10 |vpiName:work@sky130_fd_sc_hd__nand4 |vpiDefName:work@sky130_fd_sc_hd__nand4 |vpiTop:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__nand4.nand0_out_Y), line:49:10, endln:49:21 |vpiParent: - \_module: work@sky130_fd_sc_hd__nand4 (work@sky130_fd_sc_hd__nand4), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand4.functional.v, line:33:1, endln:55:10 + \_module_inst: work@sky130_fd_sc_hd__nand4 (work@sky130_fd_sc_hd__nand4), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand4.functional.v, line:33:1, endln:55:10 |vpiTypespec: \_logic_typespec: , line:49:5, endln:49:9 |vpiName:nand0_out_Y @@ -26731,7 +26731,7 @@ design: (work@sky130_fd_sc_hd__nand4) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__nand4.Y), line:34:5, endln:34:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__nand4 (work@sky130_fd_sc_hd__nand4), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand4.functional.v, line:33:1, endln:55:10 + \_module_inst: work@sky130_fd_sc_hd__nand4 (work@sky130_fd_sc_hd__nand4), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand4.functional.v, line:33:1, endln:55:10 |vpiTypespec: \_logic_typespec: , line:42:12, endln:42:12 |vpiName:Y @@ -26739,7 +26739,7 @@ design: (work@sky130_fd_sc_hd__nand4) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__nand4.A), line:35:5, endln:35:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__nand4 (work@sky130_fd_sc_hd__nand4), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand4.functional.v, line:33:1, endln:55:10 + \_module_inst: work@sky130_fd_sc_hd__nand4 (work@sky130_fd_sc_hd__nand4), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand4.functional.v, line:33:1, endln:55:10 |vpiTypespec: \_logic_typespec: , line:43:12, endln:43:12 |vpiName:A @@ -26747,7 +26747,7 @@ design: (work@sky130_fd_sc_hd__nand4) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__nand4.B), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__nand4 (work@sky130_fd_sc_hd__nand4), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand4.functional.v, line:33:1, endln:55:10 + \_module_inst: work@sky130_fd_sc_hd__nand4 (work@sky130_fd_sc_hd__nand4), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand4.functional.v, line:33:1, endln:55:10 |vpiTypespec: \_logic_typespec: , line:44:12, endln:44:12 |vpiName:B @@ -26755,7 +26755,7 @@ design: (work@sky130_fd_sc_hd__nand4) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__nand4.C), line:37:5, endln:37:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__nand4 (work@sky130_fd_sc_hd__nand4), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand4.functional.v, line:33:1, endln:55:10 + \_module_inst: work@sky130_fd_sc_hd__nand4 (work@sky130_fd_sc_hd__nand4), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand4.functional.v, line:33:1, endln:55:10 |vpiTypespec: \_logic_typespec: , line:45:12, endln:45:12 |vpiName:C @@ -26763,7 +26763,7 @@ design: (work@sky130_fd_sc_hd__nand4) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__nand4.D), line:38:5, endln:38:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__nand4 (work@sky130_fd_sc_hd__nand4), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand4.functional.v, line:33:1, endln:55:10 + \_module_inst: work@sky130_fd_sc_hd__nand4 (work@sky130_fd_sc_hd__nand4), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand4.functional.v, line:33:1, endln:55:10 |vpiTypespec: \_logic_typespec: , line:46:12, endln:46:12 |vpiName:D @@ -26772,7 +26772,7 @@ design: (work@sky130_fd_sc_hd__nand4) |vpiPort: \_port: (Y), line:34:5, endln:34:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__nand4 (work@sky130_fd_sc_hd__nand4), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand4.functional.v, line:33:1, endln:55:10 + \_module_inst: work@sky130_fd_sc_hd__nand4 (work@sky130_fd_sc_hd__nand4), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand4.functional.v, line:33:1, endln:55:10 |vpiName:Y |vpiDirection:2 |vpiLowConn: @@ -26786,7 +26786,7 @@ design: (work@sky130_fd_sc_hd__nand4) |vpiPort: \_port: (A), line:35:5, endln:35:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__nand4 (work@sky130_fd_sc_hd__nand4), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand4.functional.v, line:33:1, endln:55:10 + \_module_inst: work@sky130_fd_sc_hd__nand4 (work@sky130_fd_sc_hd__nand4), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand4.functional.v, line:33:1, endln:55:10 |vpiName:A |vpiDirection:1 |vpiLowConn: @@ -26800,7 +26800,7 @@ design: (work@sky130_fd_sc_hd__nand4) |vpiPort: \_port: (B), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__nand4 (work@sky130_fd_sc_hd__nand4), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand4.functional.v, line:33:1, endln:55:10 + \_module_inst: work@sky130_fd_sc_hd__nand4 (work@sky130_fd_sc_hd__nand4), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand4.functional.v, line:33:1, endln:55:10 |vpiName:B |vpiDirection:1 |vpiLowConn: @@ -26814,7 +26814,7 @@ design: (work@sky130_fd_sc_hd__nand4) |vpiPort: \_port: (C), line:37:5, endln:37:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__nand4 (work@sky130_fd_sc_hd__nand4), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand4.functional.v, line:33:1, endln:55:10 + \_module_inst: work@sky130_fd_sc_hd__nand4 (work@sky130_fd_sc_hd__nand4), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand4.functional.v, line:33:1, endln:55:10 |vpiName:C |vpiDirection:1 |vpiLowConn: @@ -26828,7 +26828,7 @@ design: (work@sky130_fd_sc_hd__nand4) |vpiPort: \_port: (D), line:38:5, endln:38:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__nand4 (work@sky130_fd_sc_hd__nand4), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand4.functional.v, line:33:1, endln:55:10 + \_module_inst: work@sky130_fd_sc_hd__nand4 (work@sky130_fd_sc_hd__nand4), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand4.functional.v, line:33:1, endln:55:10 |vpiName:D |vpiDirection:1 |vpiLowConn: @@ -26842,7 +26842,7 @@ design: (work@sky130_fd_sc_hd__nand4) |vpiPrimitive: \_gate: work@nand (work@sky130_fd_sc_hd__nand4.nand0), line:52:10, endln:52:46 |vpiParent: - \_module: work@sky130_fd_sc_hd__nand4 (work@sky130_fd_sc_hd__nand4), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand4.functional.v, line:33:1, endln:55:10 + \_module_inst: work@sky130_fd_sc_hd__nand4 (work@sky130_fd_sc_hd__nand4), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand4.functional.v, line:33:1, endln:55:10 |vpiDefName:work@nand |vpiName:nand0 |vpiFullName:work@sky130_fd_sc_hd__nand4.nand0 @@ -26919,7 +26919,7 @@ design: (work@sky130_fd_sc_hd__nand4) |vpiPrimitive: \_gate: work@buf (work@sky130_fd_sc_hd__nand4.buf0), line:53:10, endln:53:46 |vpiParent: - \_module: work@sky130_fd_sc_hd__nand4 (work@sky130_fd_sc_hd__nand4), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand4.functional.v, line:33:1, endln:55:10 + \_module_inst: work@sky130_fd_sc_hd__nand4 (work@sky130_fd_sc_hd__nand4), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand4.functional.v, line:33:1, endln:55:10 |vpiDefName:work@buf |vpiName:buf0 |vpiFullName:work@sky130_fd_sc_hd__nand4.buf0 @@ -27054,7 +27054,7 @@ design: (work@sky130_fd_sc_hd__mux2) |vpiSize:3 |STRING:? 1 1 : 1 |uhdmallModules: -\_module: work@sky130_fd_sc_hd__mux2 (work@sky130_fd_sc_hd__mux2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__mux2.functional.v, line:36:1, endln:56:10 +\_module_inst: work@sky130_fd_sc_hd__mux2 (work@sky130_fd_sc_hd__mux2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__mux2.functional.v, line:36:1, endln:56:10 |vpiParent: \_design: (work@sky130_fd_sc_hd__mux2) |vpiFullName:work@sky130_fd_sc_hd__mux2 @@ -27062,38 +27062,38 @@ design: (work@sky130_fd_sc_hd__mux2) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__mux2.mux_2to10_out_X), line:50:10, endln:50:25 |vpiParent: - \_module: work@sky130_fd_sc_hd__mux2 (work@sky130_fd_sc_hd__mux2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__mux2.functional.v, line:36:1, endln:56:10 + \_module_inst: work@sky130_fd_sc_hd__mux2 (work@sky130_fd_sc_hd__mux2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__mux2.functional.v, line:36:1, endln:56:10 |vpiName:mux_2to10_out_X |vpiFullName:work@sky130_fd_sc_hd__mux2.mux_2to10_out_X |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__mux2.X), line:37:5, endln:37:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__mux2 (work@sky130_fd_sc_hd__mux2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__mux2.functional.v, line:36:1, endln:56:10 + \_module_inst: work@sky130_fd_sc_hd__mux2 (work@sky130_fd_sc_hd__mux2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__mux2.functional.v, line:36:1, endln:56:10 |vpiName:X |vpiFullName:work@sky130_fd_sc_hd__mux2.X |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__mux2.A0), line:38:5, endln:38:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__mux2 (work@sky130_fd_sc_hd__mux2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__mux2.functional.v, line:36:1, endln:56:10 + \_module_inst: work@sky130_fd_sc_hd__mux2 (work@sky130_fd_sc_hd__mux2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__mux2.functional.v, line:36:1, endln:56:10 |vpiName:A0 |vpiFullName:work@sky130_fd_sc_hd__mux2.A0 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__mux2.A1), line:39:5, endln:39:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__mux2 (work@sky130_fd_sc_hd__mux2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__mux2.functional.v, line:36:1, endln:56:10 + \_module_inst: work@sky130_fd_sc_hd__mux2 (work@sky130_fd_sc_hd__mux2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__mux2.functional.v, line:36:1, endln:56:10 |vpiName:A1 |vpiFullName:work@sky130_fd_sc_hd__mux2.A1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__mux2.S), line:40:5, endln:40:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__mux2 (work@sky130_fd_sc_hd__mux2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__mux2.functional.v, line:36:1, endln:56:10 + \_module_inst: work@sky130_fd_sc_hd__mux2 (work@sky130_fd_sc_hd__mux2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__mux2.functional.v, line:36:1, endln:56:10 |vpiName:S |vpiFullName:work@sky130_fd_sc_hd__mux2.S |vpiPort: \_port: (X), line:37:5, endln:37:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__mux2 (work@sky130_fd_sc_hd__mux2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__mux2.functional.v, line:36:1, endln:56:10 + \_module_inst: work@sky130_fd_sc_hd__mux2 (work@sky130_fd_sc_hd__mux2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__mux2.functional.v, line:36:1, endln:56:10 |vpiName:X |vpiDirection:2 |vpiLowConn: @@ -27105,7 +27105,7 @@ design: (work@sky130_fd_sc_hd__mux2) |vpiPort: \_port: (A0), line:38:5, endln:38:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__mux2 (work@sky130_fd_sc_hd__mux2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__mux2.functional.v, line:36:1, endln:56:10 + \_module_inst: work@sky130_fd_sc_hd__mux2 (work@sky130_fd_sc_hd__mux2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__mux2.functional.v, line:36:1, endln:56:10 |vpiName:A0 |vpiDirection:1 |vpiLowConn: @@ -27117,7 +27117,7 @@ design: (work@sky130_fd_sc_hd__mux2) |vpiPort: \_port: (A1), line:39:5, endln:39:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__mux2 (work@sky130_fd_sc_hd__mux2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__mux2.functional.v, line:36:1, endln:56:10 + \_module_inst: work@sky130_fd_sc_hd__mux2 (work@sky130_fd_sc_hd__mux2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__mux2.functional.v, line:36:1, endln:56:10 |vpiName:A1 |vpiDirection:1 |vpiLowConn: @@ -27129,7 +27129,7 @@ design: (work@sky130_fd_sc_hd__mux2) |vpiPort: \_port: (S), line:40:5, endln:40:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__mux2 (work@sky130_fd_sc_hd__mux2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__mux2.functional.v, line:36:1, endln:56:10 + \_module_inst: work@sky130_fd_sc_hd__mux2 (work@sky130_fd_sc_hd__mux2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__mux2.functional.v, line:36:1, endln:56:10 |vpiName:S |vpiDirection:1 |vpiLowConn: @@ -27139,14 +27139,14 @@ design: (work@sky130_fd_sc_hd__mux2) |vpiTypedef: \_logic_typespec: , line:47:12, endln:47:12 |uhdmtopModules: -\_module: work@sky130_fd_sc_hd__mux2 (work@sky130_fd_sc_hd__mux2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__mux2.functional.v, line:36:1, endln:56:10 +\_module_inst: work@sky130_fd_sc_hd__mux2 (work@sky130_fd_sc_hd__mux2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__mux2.functional.v, line:36:1, endln:56:10 |vpiName:work@sky130_fd_sc_hd__mux2 |vpiDefName:work@sky130_fd_sc_hd__mux2 |vpiTop:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__mux2.mux_2to10_out_X), line:50:10, endln:50:25 |vpiParent: - \_module: work@sky130_fd_sc_hd__mux2 (work@sky130_fd_sc_hd__mux2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__mux2.functional.v, line:36:1, endln:56:10 + \_module_inst: work@sky130_fd_sc_hd__mux2 (work@sky130_fd_sc_hd__mux2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__mux2.functional.v, line:36:1, endln:56:10 |vpiTypespec: \_logic_typespec: , line:50:5, endln:50:9 |vpiName:mux_2to10_out_X @@ -27155,7 +27155,7 @@ design: (work@sky130_fd_sc_hd__mux2) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__mux2.X), line:37:5, endln:37:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__mux2 (work@sky130_fd_sc_hd__mux2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__mux2.functional.v, line:36:1, endln:56:10 + \_module_inst: work@sky130_fd_sc_hd__mux2 (work@sky130_fd_sc_hd__mux2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__mux2.functional.v, line:36:1, endln:56:10 |vpiTypespec: \_logic_typespec: , line:44:12, endln:44:12 |vpiName:X @@ -27163,7 +27163,7 @@ design: (work@sky130_fd_sc_hd__mux2) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__mux2.A0), line:38:5, endln:38:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__mux2 (work@sky130_fd_sc_hd__mux2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__mux2.functional.v, line:36:1, endln:56:10 + \_module_inst: work@sky130_fd_sc_hd__mux2 (work@sky130_fd_sc_hd__mux2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__mux2.functional.v, line:36:1, endln:56:10 |vpiTypespec: \_logic_typespec: , line:45:12, endln:45:12 |vpiName:A0 @@ -27171,7 +27171,7 @@ design: (work@sky130_fd_sc_hd__mux2) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__mux2.A1), line:39:5, endln:39:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__mux2 (work@sky130_fd_sc_hd__mux2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__mux2.functional.v, line:36:1, endln:56:10 + \_module_inst: work@sky130_fd_sc_hd__mux2 (work@sky130_fd_sc_hd__mux2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__mux2.functional.v, line:36:1, endln:56:10 |vpiTypespec: \_logic_typespec: , line:46:12, endln:46:12 |vpiName:A1 @@ -27179,7 +27179,7 @@ design: (work@sky130_fd_sc_hd__mux2) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__mux2.S), line:40:5, endln:40:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__mux2 (work@sky130_fd_sc_hd__mux2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__mux2.functional.v, line:36:1, endln:56:10 + \_module_inst: work@sky130_fd_sc_hd__mux2 (work@sky130_fd_sc_hd__mux2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__mux2.functional.v, line:36:1, endln:56:10 |vpiTypespec: \_logic_typespec: , line:47:12, endln:47:12 |vpiName:S @@ -27188,7 +27188,7 @@ design: (work@sky130_fd_sc_hd__mux2) |vpiPort: \_port: (X), line:37:5, endln:37:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__mux2 (work@sky130_fd_sc_hd__mux2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__mux2.functional.v, line:36:1, endln:56:10 + \_module_inst: work@sky130_fd_sc_hd__mux2 (work@sky130_fd_sc_hd__mux2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__mux2.functional.v, line:36:1, endln:56:10 |vpiName:X |vpiDirection:2 |vpiLowConn: @@ -27202,7 +27202,7 @@ design: (work@sky130_fd_sc_hd__mux2) |vpiPort: \_port: (A0), line:38:5, endln:38:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__mux2 (work@sky130_fd_sc_hd__mux2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__mux2.functional.v, line:36:1, endln:56:10 + \_module_inst: work@sky130_fd_sc_hd__mux2 (work@sky130_fd_sc_hd__mux2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__mux2.functional.v, line:36:1, endln:56:10 |vpiName:A0 |vpiDirection:1 |vpiLowConn: @@ -27216,7 +27216,7 @@ design: (work@sky130_fd_sc_hd__mux2) |vpiPort: \_port: (A1), line:39:5, endln:39:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__mux2 (work@sky130_fd_sc_hd__mux2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__mux2.functional.v, line:36:1, endln:56:10 + \_module_inst: work@sky130_fd_sc_hd__mux2 (work@sky130_fd_sc_hd__mux2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__mux2.functional.v, line:36:1, endln:56:10 |vpiName:A1 |vpiDirection:1 |vpiLowConn: @@ -27230,7 +27230,7 @@ design: (work@sky130_fd_sc_hd__mux2) |vpiPort: \_port: (S), line:40:5, endln:40:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__mux2 (work@sky130_fd_sc_hd__mux2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__mux2.functional.v, line:36:1, endln:56:10 + \_module_inst: work@sky130_fd_sc_hd__mux2 (work@sky130_fd_sc_hd__mux2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__mux2.functional.v, line:36:1, endln:56:10 |vpiName:S |vpiDirection:1 |vpiLowConn: @@ -27244,7 +27244,7 @@ design: (work@sky130_fd_sc_hd__mux2) |vpiPrimitive: \_udp: work@sky130_fd_sc_hd__udp_mux_2to1 (work@sky130_fd_sc_hd__mux2.mux_2to10), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__mux2.functional.v, line:53:5, endln:53:80 |vpiParent: - \_module: work@sky130_fd_sc_hd__mux2 (work@sky130_fd_sc_hd__mux2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__mux2.functional.v, line:36:1, endln:56:10 + \_module_inst: work@sky130_fd_sc_hd__mux2 (work@sky130_fd_sc_hd__mux2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__mux2.functional.v, line:36:1, endln:56:10 |vpiDefName:work@sky130_fd_sc_hd__udp_mux_2to1 |vpiName:mux_2to10 |vpiFullName:work@sky130_fd_sc_hd__mux2.mux_2to10 @@ -27253,7 +27253,7 @@ design: (work@sky130_fd_sc_hd__mux2) |vpiPrimitive: \_gate: work@buf (work@sky130_fd_sc_hd__mux2.buf0), line:54:35, endln:54:79 |vpiParent: - \_module: work@sky130_fd_sc_hd__mux2 (work@sky130_fd_sc_hd__mux2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__mux2.functional.v, line:36:1, endln:56:10 + \_module_inst: work@sky130_fd_sc_hd__mux2 (work@sky130_fd_sc_hd__mux2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__mux2.functional.v, line:36:1, endln:56:10 |vpiDefName:work@buf |vpiName:buf0 |vpiFullName:work@sky130_fd_sc_hd__mux2.buf0 @@ -27296,7 +27296,7 @@ Processing: -cd cells/cells -DUNIT_DELAY -writepp -parse -nocache -nobuiltin -no design: (work@sky130_fd_sc_hd__nand2) |vpiName:work@sky130_fd_sc_hd__nand2 |uhdmallModules: -\_module: work@sky130_fd_sc_hd__nand2 (work@sky130_fd_sc_hd__nand2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand2.functional.v, line:33:1, endln:51:10 +\_module_inst: work@sky130_fd_sc_hd__nand2 (work@sky130_fd_sc_hd__nand2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand2.functional.v, line:33:1, endln:51:10 |vpiParent: \_design: (work@sky130_fd_sc_hd__nand2) |vpiFullName:work@sky130_fd_sc_hd__nand2 @@ -27304,32 +27304,32 @@ design: (work@sky130_fd_sc_hd__nand2) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__nand2.nand0_out_Y), line:45:10, endln:45:21 |vpiParent: - \_module: work@sky130_fd_sc_hd__nand2 (work@sky130_fd_sc_hd__nand2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand2.functional.v, line:33:1, endln:51:10 + \_module_inst: work@sky130_fd_sc_hd__nand2 (work@sky130_fd_sc_hd__nand2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand2.functional.v, line:33:1, endln:51:10 |vpiName:nand0_out_Y |vpiFullName:work@sky130_fd_sc_hd__nand2.nand0_out_Y |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__nand2.Y), line:34:5, endln:34:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__nand2 (work@sky130_fd_sc_hd__nand2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand2.functional.v, line:33:1, endln:51:10 + \_module_inst: work@sky130_fd_sc_hd__nand2 (work@sky130_fd_sc_hd__nand2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand2.functional.v, line:33:1, endln:51:10 |vpiName:Y |vpiFullName:work@sky130_fd_sc_hd__nand2.Y |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__nand2.A), line:35:5, endln:35:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__nand2 (work@sky130_fd_sc_hd__nand2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand2.functional.v, line:33:1, endln:51:10 + \_module_inst: work@sky130_fd_sc_hd__nand2 (work@sky130_fd_sc_hd__nand2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand2.functional.v, line:33:1, endln:51:10 |vpiName:A |vpiFullName:work@sky130_fd_sc_hd__nand2.A |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__nand2.B), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__nand2 (work@sky130_fd_sc_hd__nand2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand2.functional.v, line:33:1, endln:51:10 + \_module_inst: work@sky130_fd_sc_hd__nand2 (work@sky130_fd_sc_hd__nand2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand2.functional.v, line:33:1, endln:51:10 |vpiName:B |vpiFullName:work@sky130_fd_sc_hd__nand2.B |vpiPort: \_port: (Y), line:34:5, endln:34:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__nand2 (work@sky130_fd_sc_hd__nand2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand2.functional.v, line:33:1, endln:51:10 + \_module_inst: work@sky130_fd_sc_hd__nand2 (work@sky130_fd_sc_hd__nand2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand2.functional.v, line:33:1, endln:51:10 |vpiName:Y |vpiDirection:2 |vpiLowConn: @@ -27341,7 +27341,7 @@ design: (work@sky130_fd_sc_hd__nand2) |vpiPort: \_port: (A), line:35:5, endln:35:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__nand2 (work@sky130_fd_sc_hd__nand2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand2.functional.v, line:33:1, endln:51:10 + \_module_inst: work@sky130_fd_sc_hd__nand2 (work@sky130_fd_sc_hd__nand2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand2.functional.v, line:33:1, endln:51:10 |vpiName:A |vpiDirection:1 |vpiLowConn: @@ -27353,7 +27353,7 @@ design: (work@sky130_fd_sc_hd__nand2) |vpiPort: \_port: (B), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__nand2 (work@sky130_fd_sc_hd__nand2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand2.functional.v, line:33:1, endln:51:10 + \_module_inst: work@sky130_fd_sc_hd__nand2 (work@sky130_fd_sc_hd__nand2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand2.functional.v, line:33:1, endln:51:10 |vpiName:B |vpiDirection:1 |vpiLowConn: @@ -27363,14 +27363,14 @@ design: (work@sky130_fd_sc_hd__nand2) |vpiTypedef: \_logic_typespec: , line:42:12, endln:42:12 |uhdmtopModules: -\_module: work@sky130_fd_sc_hd__nand2 (work@sky130_fd_sc_hd__nand2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand2.functional.v, line:33:1, endln:51:10 +\_module_inst: work@sky130_fd_sc_hd__nand2 (work@sky130_fd_sc_hd__nand2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand2.functional.v, line:33:1, endln:51:10 |vpiName:work@sky130_fd_sc_hd__nand2 |vpiDefName:work@sky130_fd_sc_hd__nand2 |vpiTop:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__nand2.nand0_out_Y), line:45:10, endln:45:21 |vpiParent: - \_module: work@sky130_fd_sc_hd__nand2 (work@sky130_fd_sc_hd__nand2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand2.functional.v, line:33:1, endln:51:10 + \_module_inst: work@sky130_fd_sc_hd__nand2 (work@sky130_fd_sc_hd__nand2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand2.functional.v, line:33:1, endln:51:10 |vpiTypespec: \_logic_typespec: , line:45:5, endln:45:9 |vpiName:nand0_out_Y @@ -27379,7 +27379,7 @@ design: (work@sky130_fd_sc_hd__nand2) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__nand2.Y), line:34:5, endln:34:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__nand2 (work@sky130_fd_sc_hd__nand2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand2.functional.v, line:33:1, endln:51:10 + \_module_inst: work@sky130_fd_sc_hd__nand2 (work@sky130_fd_sc_hd__nand2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand2.functional.v, line:33:1, endln:51:10 |vpiTypespec: \_logic_typespec: , line:40:12, endln:40:12 |vpiName:Y @@ -27387,7 +27387,7 @@ design: (work@sky130_fd_sc_hd__nand2) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__nand2.A), line:35:5, endln:35:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__nand2 (work@sky130_fd_sc_hd__nand2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand2.functional.v, line:33:1, endln:51:10 + \_module_inst: work@sky130_fd_sc_hd__nand2 (work@sky130_fd_sc_hd__nand2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand2.functional.v, line:33:1, endln:51:10 |vpiTypespec: \_logic_typespec: , line:41:12, endln:41:12 |vpiName:A @@ -27395,7 +27395,7 @@ design: (work@sky130_fd_sc_hd__nand2) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__nand2.B), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__nand2 (work@sky130_fd_sc_hd__nand2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand2.functional.v, line:33:1, endln:51:10 + \_module_inst: work@sky130_fd_sc_hd__nand2 (work@sky130_fd_sc_hd__nand2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand2.functional.v, line:33:1, endln:51:10 |vpiTypespec: \_logic_typespec: , line:42:12, endln:42:12 |vpiName:B @@ -27404,7 +27404,7 @@ design: (work@sky130_fd_sc_hd__nand2) |vpiPort: \_port: (Y), line:34:5, endln:34:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__nand2 (work@sky130_fd_sc_hd__nand2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand2.functional.v, line:33:1, endln:51:10 + \_module_inst: work@sky130_fd_sc_hd__nand2 (work@sky130_fd_sc_hd__nand2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand2.functional.v, line:33:1, endln:51:10 |vpiName:Y |vpiDirection:2 |vpiLowConn: @@ -27418,7 +27418,7 @@ design: (work@sky130_fd_sc_hd__nand2) |vpiPort: \_port: (A), line:35:5, endln:35:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__nand2 (work@sky130_fd_sc_hd__nand2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand2.functional.v, line:33:1, endln:51:10 + \_module_inst: work@sky130_fd_sc_hd__nand2 (work@sky130_fd_sc_hd__nand2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand2.functional.v, line:33:1, endln:51:10 |vpiName:A |vpiDirection:1 |vpiLowConn: @@ -27432,7 +27432,7 @@ design: (work@sky130_fd_sc_hd__nand2) |vpiPort: \_port: (B), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__nand2 (work@sky130_fd_sc_hd__nand2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand2.functional.v, line:33:1, endln:51:10 + \_module_inst: work@sky130_fd_sc_hd__nand2 (work@sky130_fd_sc_hd__nand2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand2.functional.v, line:33:1, endln:51:10 |vpiName:B |vpiDirection:1 |vpiLowConn: @@ -27446,7 +27446,7 @@ design: (work@sky130_fd_sc_hd__nand2) |vpiPrimitive: \_gate: work@nand (work@sky130_fd_sc_hd__nand2.nand0), line:48:10, endln:48:46 |vpiParent: - \_module: work@sky130_fd_sc_hd__nand2 (work@sky130_fd_sc_hd__nand2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand2.functional.v, line:33:1, endln:51:10 + \_module_inst: work@sky130_fd_sc_hd__nand2 (work@sky130_fd_sc_hd__nand2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand2.functional.v, line:33:1, endln:51:10 |vpiDefName:work@nand |vpiName:nand0 |vpiFullName:work@sky130_fd_sc_hd__nand2.nand0 @@ -27495,7 +27495,7 @@ design: (work@sky130_fd_sc_hd__nand2) |vpiPrimitive: \_gate: work@buf (work@sky130_fd_sc_hd__nand2.buf0), line:49:10, endln:49:46 |vpiParent: - \_module: work@sky130_fd_sc_hd__nand2 (work@sky130_fd_sc_hd__nand2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand2.functional.v, line:33:1, endln:51:10 + \_module_inst: work@sky130_fd_sc_hd__nand2 (work@sky130_fd_sc_hd__nand2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand2.functional.v, line:33:1, endln:51:10 |vpiDefName:work@buf |vpiName:buf0 |vpiFullName:work@sky130_fd_sc_hd__nand2.buf0 @@ -27648,7 +27648,7 @@ design: (work@sky130_fd_sc_hd__dlrbp) |vpiSize:3 |STRING:0 x x : 0 : 0 |uhdmallModules: -\_module: work@sky130_fd_sc_hd__dlrbp (work@sky130_fd_sc_hd__dlrbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlrbp.functional.v, line:37:1, endln:62:10 +\_module_inst: work@sky130_fd_sc_hd__dlrbp (work@sky130_fd_sc_hd__dlrbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlrbp.functional.v, line:37:1, endln:62:10 |vpiParent: \_design: (work@sky130_fd_sc_hd__dlrbp) |vpiFullName:work@sky130_fd_sc_hd__dlrbp @@ -27656,51 +27656,51 @@ design: (work@sky130_fd_sc_hd__dlrbp) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__dlrbp.RESET), line:53:10, endln:53:15 |vpiParent: - \_module: work@sky130_fd_sc_hd__dlrbp (work@sky130_fd_sc_hd__dlrbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlrbp.functional.v, line:37:1, endln:62:10 + \_module_inst: work@sky130_fd_sc_hd__dlrbp (work@sky130_fd_sc_hd__dlrbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlrbp.functional.v, line:37:1, endln:62:10 |vpiName:RESET |vpiFullName:work@sky130_fd_sc_hd__dlrbp.RESET |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__dlrbp.buf_Q), line:54:10, endln:54:15 |vpiParent: - \_module: work@sky130_fd_sc_hd__dlrbp (work@sky130_fd_sc_hd__dlrbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlrbp.functional.v, line:37:1, endln:62:10 + \_module_inst: work@sky130_fd_sc_hd__dlrbp (work@sky130_fd_sc_hd__dlrbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlrbp.functional.v, line:37:1, endln:62:10 |vpiName:buf_Q |vpiFullName:work@sky130_fd_sc_hd__dlrbp.buf_Q |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__dlrbp.Q), line:38:5, endln:38:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__dlrbp (work@sky130_fd_sc_hd__dlrbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlrbp.functional.v, line:37:1, endln:62:10 + \_module_inst: work@sky130_fd_sc_hd__dlrbp (work@sky130_fd_sc_hd__dlrbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlrbp.functional.v, line:37:1, endln:62:10 |vpiName:Q |vpiFullName:work@sky130_fd_sc_hd__dlrbp.Q |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__dlrbp.Q_N), line:39:5, endln:39:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__dlrbp (work@sky130_fd_sc_hd__dlrbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlrbp.functional.v, line:37:1, endln:62:10 + \_module_inst: work@sky130_fd_sc_hd__dlrbp (work@sky130_fd_sc_hd__dlrbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlrbp.functional.v, line:37:1, endln:62:10 |vpiName:Q_N |vpiFullName:work@sky130_fd_sc_hd__dlrbp.Q_N |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__dlrbp.RESET_B), line:40:5, endln:40:12 |vpiParent: - \_module: work@sky130_fd_sc_hd__dlrbp (work@sky130_fd_sc_hd__dlrbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlrbp.functional.v, line:37:1, endln:62:10 + \_module_inst: work@sky130_fd_sc_hd__dlrbp (work@sky130_fd_sc_hd__dlrbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlrbp.functional.v, line:37:1, endln:62:10 |vpiName:RESET_B |vpiFullName:work@sky130_fd_sc_hd__dlrbp.RESET_B |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__dlrbp.D), line:41:5, endln:41:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__dlrbp (work@sky130_fd_sc_hd__dlrbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlrbp.functional.v, line:37:1, endln:62:10 + \_module_inst: work@sky130_fd_sc_hd__dlrbp (work@sky130_fd_sc_hd__dlrbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlrbp.functional.v, line:37:1, endln:62:10 |vpiName:D |vpiFullName:work@sky130_fd_sc_hd__dlrbp.D |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__dlrbp.GATE), line:42:5, endln:42:9 |vpiParent: - \_module: work@sky130_fd_sc_hd__dlrbp (work@sky130_fd_sc_hd__dlrbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlrbp.functional.v, line:37:1, endln:62:10 + \_module_inst: work@sky130_fd_sc_hd__dlrbp (work@sky130_fd_sc_hd__dlrbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlrbp.functional.v, line:37:1, endln:62:10 |vpiName:GATE |vpiFullName:work@sky130_fd_sc_hd__dlrbp.GATE |vpiPort: \_port: (Q), line:38:5, endln:38:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__dlrbp (work@sky130_fd_sc_hd__dlrbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlrbp.functional.v, line:37:1, endln:62:10 + \_module_inst: work@sky130_fd_sc_hd__dlrbp (work@sky130_fd_sc_hd__dlrbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlrbp.functional.v, line:37:1, endln:62:10 |vpiName:Q |vpiDirection:2 |vpiLowConn: @@ -27712,7 +27712,7 @@ design: (work@sky130_fd_sc_hd__dlrbp) |vpiPort: \_port: (Q_N), line:39:5, endln:39:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__dlrbp (work@sky130_fd_sc_hd__dlrbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlrbp.functional.v, line:37:1, endln:62:10 + \_module_inst: work@sky130_fd_sc_hd__dlrbp (work@sky130_fd_sc_hd__dlrbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlrbp.functional.v, line:37:1, endln:62:10 |vpiName:Q_N |vpiDirection:2 |vpiLowConn: @@ -27724,7 +27724,7 @@ design: (work@sky130_fd_sc_hd__dlrbp) |vpiPort: \_port: (RESET_B), line:40:5, endln:40:12 |vpiParent: - \_module: work@sky130_fd_sc_hd__dlrbp (work@sky130_fd_sc_hd__dlrbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlrbp.functional.v, line:37:1, endln:62:10 + \_module_inst: work@sky130_fd_sc_hd__dlrbp (work@sky130_fd_sc_hd__dlrbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlrbp.functional.v, line:37:1, endln:62:10 |vpiName:RESET_B |vpiDirection:1 |vpiLowConn: @@ -27736,7 +27736,7 @@ design: (work@sky130_fd_sc_hd__dlrbp) |vpiPort: \_port: (D), line:41:5, endln:41:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__dlrbp (work@sky130_fd_sc_hd__dlrbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlrbp.functional.v, line:37:1, endln:62:10 + \_module_inst: work@sky130_fd_sc_hd__dlrbp (work@sky130_fd_sc_hd__dlrbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlrbp.functional.v, line:37:1, endln:62:10 |vpiName:D |vpiDirection:1 |vpiLowConn: @@ -27748,7 +27748,7 @@ design: (work@sky130_fd_sc_hd__dlrbp) |vpiPort: \_port: (GATE), line:42:5, endln:42:9 |vpiParent: - \_module: work@sky130_fd_sc_hd__dlrbp (work@sky130_fd_sc_hd__dlrbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlrbp.functional.v, line:37:1, endln:62:10 + \_module_inst: work@sky130_fd_sc_hd__dlrbp (work@sky130_fd_sc_hd__dlrbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlrbp.functional.v, line:37:1, endln:62:10 |vpiName:GATE |vpiDirection:1 |vpiLowConn: @@ -27758,14 +27758,14 @@ design: (work@sky130_fd_sc_hd__dlrbp) |vpiTypedef: \_logic_typespec: , line:50:12, endln:50:12 |uhdmtopModules: -\_module: work@sky130_fd_sc_hd__dlrbp (work@sky130_fd_sc_hd__dlrbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlrbp.functional.v, line:37:1, endln:62:10 +\_module_inst: work@sky130_fd_sc_hd__dlrbp (work@sky130_fd_sc_hd__dlrbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlrbp.functional.v, line:37:1, endln:62:10 |vpiName:work@sky130_fd_sc_hd__dlrbp |vpiDefName:work@sky130_fd_sc_hd__dlrbp |vpiTop:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__dlrbp.RESET), line:53:10, endln:53:15 |vpiParent: - \_module: work@sky130_fd_sc_hd__dlrbp (work@sky130_fd_sc_hd__dlrbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlrbp.functional.v, line:37:1, endln:62:10 + \_module_inst: work@sky130_fd_sc_hd__dlrbp (work@sky130_fd_sc_hd__dlrbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlrbp.functional.v, line:37:1, endln:62:10 |vpiTypespec: \_logic_typespec: , line:53:5, endln:53:9 |vpiName:RESET @@ -27774,7 +27774,7 @@ design: (work@sky130_fd_sc_hd__dlrbp) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__dlrbp.buf_Q), line:54:10, endln:54:15 |vpiParent: - \_module: work@sky130_fd_sc_hd__dlrbp (work@sky130_fd_sc_hd__dlrbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlrbp.functional.v, line:37:1, endln:62:10 + \_module_inst: work@sky130_fd_sc_hd__dlrbp (work@sky130_fd_sc_hd__dlrbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlrbp.functional.v, line:37:1, endln:62:10 |vpiTypespec: \_logic_typespec: , line:54:5, endln:54:9 |vpiName:buf_Q @@ -27783,7 +27783,7 @@ design: (work@sky130_fd_sc_hd__dlrbp) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__dlrbp.Q), line:38:5, endln:38:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__dlrbp (work@sky130_fd_sc_hd__dlrbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlrbp.functional.v, line:37:1, endln:62:10 + \_module_inst: work@sky130_fd_sc_hd__dlrbp (work@sky130_fd_sc_hd__dlrbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlrbp.functional.v, line:37:1, endln:62:10 |vpiTypespec: \_logic_typespec: , line:46:12, endln:46:12 |vpiName:Q @@ -27791,7 +27791,7 @@ design: (work@sky130_fd_sc_hd__dlrbp) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__dlrbp.Q_N), line:39:5, endln:39:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__dlrbp (work@sky130_fd_sc_hd__dlrbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlrbp.functional.v, line:37:1, endln:62:10 + \_module_inst: work@sky130_fd_sc_hd__dlrbp (work@sky130_fd_sc_hd__dlrbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlrbp.functional.v, line:37:1, endln:62:10 |vpiTypespec: \_logic_typespec: , line:47:12, endln:47:12 |vpiName:Q_N @@ -27799,7 +27799,7 @@ design: (work@sky130_fd_sc_hd__dlrbp) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__dlrbp.RESET_B), line:40:5, endln:40:12 |vpiParent: - \_module: work@sky130_fd_sc_hd__dlrbp (work@sky130_fd_sc_hd__dlrbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlrbp.functional.v, line:37:1, endln:62:10 + \_module_inst: work@sky130_fd_sc_hd__dlrbp (work@sky130_fd_sc_hd__dlrbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlrbp.functional.v, line:37:1, endln:62:10 |vpiTypespec: \_logic_typespec: , line:48:12, endln:48:12 |vpiName:RESET_B @@ -27807,7 +27807,7 @@ design: (work@sky130_fd_sc_hd__dlrbp) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__dlrbp.D), line:41:5, endln:41:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__dlrbp (work@sky130_fd_sc_hd__dlrbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlrbp.functional.v, line:37:1, endln:62:10 + \_module_inst: work@sky130_fd_sc_hd__dlrbp (work@sky130_fd_sc_hd__dlrbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlrbp.functional.v, line:37:1, endln:62:10 |vpiTypespec: \_logic_typespec: , line:49:12, endln:49:12 |vpiName:D @@ -27815,7 +27815,7 @@ design: (work@sky130_fd_sc_hd__dlrbp) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__dlrbp.GATE), line:42:5, endln:42:9 |vpiParent: - \_module: work@sky130_fd_sc_hd__dlrbp (work@sky130_fd_sc_hd__dlrbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlrbp.functional.v, line:37:1, endln:62:10 + \_module_inst: work@sky130_fd_sc_hd__dlrbp (work@sky130_fd_sc_hd__dlrbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlrbp.functional.v, line:37:1, endln:62:10 |vpiTypespec: \_logic_typespec: , line:50:12, endln:50:12 |vpiName:GATE @@ -27824,7 +27824,7 @@ design: (work@sky130_fd_sc_hd__dlrbp) |vpiPort: \_port: (Q), line:38:5, endln:38:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__dlrbp (work@sky130_fd_sc_hd__dlrbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlrbp.functional.v, line:37:1, endln:62:10 + \_module_inst: work@sky130_fd_sc_hd__dlrbp (work@sky130_fd_sc_hd__dlrbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlrbp.functional.v, line:37:1, endln:62:10 |vpiName:Q |vpiDirection:2 |vpiLowConn: @@ -27838,7 +27838,7 @@ design: (work@sky130_fd_sc_hd__dlrbp) |vpiPort: \_port: (Q_N), line:39:5, endln:39:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__dlrbp (work@sky130_fd_sc_hd__dlrbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlrbp.functional.v, line:37:1, endln:62:10 + \_module_inst: work@sky130_fd_sc_hd__dlrbp (work@sky130_fd_sc_hd__dlrbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlrbp.functional.v, line:37:1, endln:62:10 |vpiName:Q_N |vpiDirection:2 |vpiLowConn: @@ -27852,7 +27852,7 @@ design: (work@sky130_fd_sc_hd__dlrbp) |vpiPort: \_port: (RESET_B), line:40:5, endln:40:12 |vpiParent: - \_module: work@sky130_fd_sc_hd__dlrbp (work@sky130_fd_sc_hd__dlrbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlrbp.functional.v, line:37:1, endln:62:10 + \_module_inst: work@sky130_fd_sc_hd__dlrbp (work@sky130_fd_sc_hd__dlrbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlrbp.functional.v, line:37:1, endln:62:10 |vpiName:RESET_B |vpiDirection:1 |vpiLowConn: @@ -27866,7 +27866,7 @@ design: (work@sky130_fd_sc_hd__dlrbp) |vpiPort: \_port: (D), line:41:5, endln:41:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__dlrbp (work@sky130_fd_sc_hd__dlrbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlrbp.functional.v, line:37:1, endln:62:10 + \_module_inst: work@sky130_fd_sc_hd__dlrbp (work@sky130_fd_sc_hd__dlrbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlrbp.functional.v, line:37:1, endln:62:10 |vpiName:D |vpiDirection:1 |vpiLowConn: @@ -27880,7 +27880,7 @@ design: (work@sky130_fd_sc_hd__dlrbp) |vpiPort: \_port: (GATE), line:42:5, endln:42:9 |vpiParent: - \_module: work@sky130_fd_sc_hd__dlrbp (work@sky130_fd_sc_hd__dlrbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlrbp.functional.v, line:37:1, endln:62:10 + \_module_inst: work@sky130_fd_sc_hd__dlrbp (work@sky130_fd_sc_hd__dlrbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlrbp.functional.v, line:37:1, endln:62:10 |vpiName:GATE |vpiDirection:1 |vpiLowConn: @@ -27894,7 +27894,7 @@ design: (work@sky130_fd_sc_hd__dlrbp) |vpiPrimitive: \_gate: work@not (work@sky130_fd_sc_hd__dlrbp.not0), line:57:48, endln:57:81 |vpiParent: - \_module: work@sky130_fd_sc_hd__dlrbp (work@sky130_fd_sc_hd__dlrbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlrbp.functional.v, line:37:1, endln:62:10 + \_module_inst: work@sky130_fd_sc_hd__dlrbp (work@sky130_fd_sc_hd__dlrbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlrbp.functional.v, line:37:1, endln:62:10 |vpiDefName:work@not |vpiName:not0 |vpiFullName:work@sky130_fd_sc_hd__dlrbp.not0 @@ -27929,7 +27929,7 @@ design: (work@sky130_fd_sc_hd__dlrbp) |vpiPrimitive: \_udp: work@sky130_fd_sc_hd__udp_dlatch$PR (work@sky130_fd_sc_hd__dlrbp.dlatch0), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlrbp.functional.v, line:58:5, endln:58:71 |vpiParent: - \_module: work@sky130_fd_sc_hd__dlrbp (work@sky130_fd_sc_hd__dlrbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlrbp.functional.v, line:37:1, endln:62:10 + \_module_inst: work@sky130_fd_sc_hd__dlrbp (work@sky130_fd_sc_hd__dlrbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlrbp.functional.v, line:37:1, endln:62:10 |vpiDefName:work@sky130_fd_sc_hd__udp_dlatch$PR |vpiName:dlatch0 |vpiFullName:work@sky130_fd_sc_hd__dlrbp.dlatch0 @@ -27938,7 +27938,7 @@ design: (work@sky130_fd_sc_hd__dlrbp) |vpiPrimitive: \_gate: work@buf (work@sky130_fd_sc_hd__dlrbp.buf0), line:59:48, endln:59:81 |vpiParent: - \_module: work@sky130_fd_sc_hd__dlrbp (work@sky130_fd_sc_hd__dlrbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlrbp.functional.v, line:37:1, endln:62:10 + \_module_inst: work@sky130_fd_sc_hd__dlrbp (work@sky130_fd_sc_hd__dlrbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlrbp.functional.v, line:37:1, endln:62:10 |vpiDefName:work@buf |vpiName:buf0 |vpiFullName:work@sky130_fd_sc_hd__dlrbp.buf0 @@ -27973,7 +27973,7 @@ design: (work@sky130_fd_sc_hd__dlrbp) |vpiPrimitive: \_gate: work@not (work@sky130_fd_sc_hd__dlrbp.not1), line:60:48, endln:60:81 |vpiParent: - \_module: work@sky130_fd_sc_hd__dlrbp (work@sky130_fd_sc_hd__dlrbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlrbp.functional.v, line:37:1, endln:62:10 + \_module_inst: work@sky130_fd_sc_hd__dlrbp (work@sky130_fd_sc_hd__dlrbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlrbp.functional.v, line:37:1, endln:62:10 |vpiDefName:work@not |vpiName:not1 |vpiFullName:work@sky130_fd_sc_hd__dlrbp.not1 @@ -28016,7 +28016,7 @@ Processing: -cd cells/cells -DUNIT_DELAY -writepp -parse -nocache -nobuiltin -no design: (work@sky130_fd_sc_hd__o2bb2a) |vpiName:work@sky130_fd_sc_hd__o2bb2a |uhdmallModules: -\_module: work@sky130_fd_sc_hd__o2bb2a (work@sky130_fd_sc_hd__o2bb2a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o2bb2a.functional.v, line:35:1, endln:61:10 +\_module_inst: work@sky130_fd_sc_hd__o2bb2a (work@sky130_fd_sc_hd__o2bb2a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o2bb2a.functional.v, line:35:1, endln:61:10 |vpiParent: \_design: (work@sky130_fd_sc_hd__o2bb2a) |vpiFullName:work@sky130_fd_sc_hd__o2bb2a @@ -28024,58 +28024,58 @@ design: (work@sky130_fd_sc_hd__o2bb2a) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o2bb2a.nand0_out), line:51:10, endln:51:19 |vpiParent: - \_module: work@sky130_fd_sc_hd__o2bb2a (work@sky130_fd_sc_hd__o2bb2a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o2bb2a.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o2bb2a (work@sky130_fd_sc_hd__o2bb2a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o2bb2a.functional.v, line:35:1, endln:61:10 |vpiName:nand0_out |vpiFullName:work@sky130_fd_sc_hd__o2bb2a.nand0_out |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o2bb2a.or0_out), line:52:10, endln:52:17 |vpiParent: - \_module: work@sky130_fd_sc_hd__o2bb2a (work@sky130_fd_sc_hd__o2bb2a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o2bb2a.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o2bb2a (work@sky130_fd_sc_hd__o2bb2a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o2bb2a.functional.v, line:35:1, endln:61:10 |vpiName:or0_out |vpiFullName:work@sky130_fd_sc_hd__o2bb2a.or0_out |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o2bb2a.and0_out_X), line:53:10, endln:53:20 |vpiParent: - \_module: work@sky130_fd_sc_hd__o2bb2a (work@sky130_fd_sc_hd__o2bb2a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o2bb2a.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o2bb2a (work@sky130_fd_sc_hd__o2bb2a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o2bb2a.functional.v, line:35:1, endln:61:10 |vpiName:and0_out_X |vpiFullName:work@sky130_fd_sc_hd__o2bb2a.and0_out_X |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o2bb2a.X), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__o2bb2a (work@sky130_fd_sc_hd__o2bb2a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o2bb2a.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o2bb2a (work@sky130_fd_sc_hd__o2bb2a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o2bb2a.functional.v, line:35:1, endln:61:10 |vpiName:X |vpiFullName:work@sky130_fd_sc_hd__o2bb2a.X |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o2bb2a.A1_N), line:37:5, endln:37:9 |vpiParent: - \_module: work@sky130_fd_sc_hd__o2bb2a (work@sky130_fd_sc_hd__o2bb2a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o2bb2a.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o2bb2a (work@sky130_fd_sc_hd__o2bb2a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o2bb2a.functional.v, line:35:1, endln:61:10 |vpiName:A1_N |vpiFullName:work@sky130_fd_sc_hd__o2bb2a.A1_N |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o2bb2a.A2_N), line:38:5, endln:38:9 |vpiParent: - \_module: work@sky130_fd_sc_hd__o2bb2a (work@sky130_fd_sc_hd__o2bb2a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o2bb2a.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o2bb2a (work@sky130_fd_sc_hd__o2bb2a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o2bb2a.functional.v, line:35:1, endln:61:10 |vpiName:A2_N |vpiFullName:work@sky130_fd_sc_hd__o2bb2a.A2_N |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o2bb2a.B1), line:39:5, endln:39:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o2bb2a (work@sky130_fd_sc_hd__o2bb2a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o2bb2a.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o2bb2a (work@sky130_fd_sc_hd__o2bb2a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o2bb2a.functional.v, line:35:1, endln:61:10 |vpiName:B1 |vpiFullName:work@sky130_fd_sc_hd__o2bb2a.B1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o2bb2a.B2), line:40:5, endln:40:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o2bb2a (work@sky130_fd_sc_hd__o2bb2a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o2bb2a.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o2bb2a (work@sky130_fd_sc_hd__o2bb2a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o2bb2a.functional.v, line:35:1, endln:61:10 |vpiName:B2 |vpiFullName:work@sky130_fd_sc_hd__o2bb2a.B2 |vpiPort: \_port: (X), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__o2bb2a (work@sky130_fd_sc_hd__o2bb2a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o2bb2a.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o2bb2a (work@sky130_fd_sc_hd__o2bb2a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o2bb2a.functional.v, line:35:1, endln:61:10 |vpiName:X |vpiDirection:2 |vpiLowConn: @@ -28087,7 +28087,7 @@ design: (work@sky130_fd_sc_hd__o2bb2a) |vpiPort: \_port: (A1_N), line:37:5, endln:37:9 |vpiParent: - \_module: work@sky130_fd_sc_hd__o2bb2a (work@sky130_fd_sc_hd__o2bb2a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o2bb2a.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o2bb2a (work@sky130_fd_sc_hd__o2bb2a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o2bb2a.functional.v, line:35:1, endln:61:10 |vpiName:A1_N |vpiDirection:1 |vpiLowConn: @@ -28099,7 +28099,7 @@ design: (work@sky130_fd_sc_hd__o2bb2a) |vpiPort: \_port: (A2_N), line:38:5, endln:38:9 |vpiParent: - \_module: work@sky130_fd_sc_hd__o2bb2a (work@sky130_fd_sc_hd__o2bb2a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o2bb2a.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o2bb2a (work@sky130_fd_sc_hd__o2bb2a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o2bb2a.functional.v, line:35:1, endln:61:10 |vpiName:A2_N |vpiDirection:1 |vpiLowConn: @@ -28111,7 +28111,7 @@ design: (work@sky130_fd_sc_hd__o2bb2a) |vpiPort: \_port: (B1), line:39:5, endln:39:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o2bb2a (work@sky130_fd_sc_hd__o2bb2a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o2bb2a.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o2bb2a (work@sky130_fd_sc_hd__o2bb2a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o2bb2a.functional.v, line:35:1, endln:61:10 |vpiName:B1 |vpiDirection:1 |vpiLowConn: @@ -28123,7 +28123,7 @@ design: (work@sky130_fd_sc_hd__o2bb2a) |vpiPort: \_port: (B2), line:40:5, endln:40:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o2bb2a (work@sky130_fd_sc_hd__o2bb2a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o2bb2a.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o2bb2a (work@sky130_fd_sc_hd__o2bb2a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o2bb2a.functional.v, line:35:1, endln:61:10 |vpiName:B2 |vpiDirection:1 |vpiLowConn: @@ -28133,14 +28133,14 @@ design: (work@sky130_fd_sc_hd__o2bb2a) |vpiTypedef: \_logic_typespec: , line:48:12, endln:48:12 |uhdmtopModules: -\_module: work@sky130_fd_sc_hd__o2bb2a (work@sky130_fd_sc_hd__o2bb2a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o2bb2a.functional.v, line:35:1, endln:61:10 +\_module_inst: work@sky130_fd_sc_hd__o2bb2a (work@sky130_fd_sc_hd__o2bb2a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o2bb2a.functional.v, line:35:1, endln:61:10 |vpiName:work@sky130_fd_sc_hd__o2bb2a |vpiDefName:work@sky130_fd_sc_hd__o2bb2a |vpiTop:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o2bb2a.nand0_out), line:51:10, endln:51:19 |vpiParent: - \_module: work@sky130_fd_sc_hd__o2bb2a (work@sky130_fd_sc_hd__o2bb2a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o2bb2a.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o2bb2a (work@sky130_fd_sc_hd__o2bb2a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o2bb2a.functional.v, line:35:1, endln:61:10 |vpiTypespec: \_logic_typespec: , line:51:5, endln:51:9 |vpiName:nand0_out @@ -28149,7 +28149,7 @@ design: (work@sky130_fd_sc_hd__o2bb2a) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o2bb2a.or0_out), line:52:10, endln:52:17 |vpiParent: - \_module: work@sky130_fd_sc_hd__o2bb2a (work@sky130_fd_sc_hd__o2bb2a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o2bb2a.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o2bb2a (work@sky130_fd_sc_hd__o2bb2a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o2bb2a.functional.v, line:35:1, endln:61:10 |vpiTypespec: \_logic_typespec: , line:52:5, endln:52:9 |vpiName:or0_out @@ -28158,7 +28158,7 @@ design: (work@sky130_fd_sc_hd__o2bb2a) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o2bb2a.and0_out_X), line:53:10, endln:53:20 |vpiParent: - \_module: work@sky130_fd_sc_hd__o2bb2a (work@sky130_fd_sc_hd__o2bb2a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o2bb2a.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o2bb2a (work@sky130_fd_sc_hd__o2bb2a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o2bb2a.functional.v, line:35:1, endln:61:10 |vpiTypespec: \_logic_typespec: , line:53:5, endln:53:9 |vpiName:and0_out_X @@ -28167,7 +28167,7 @@ design: (work@sky130_fd_sc_hd__o2bb2a) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o2bb2a.X), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__o2bb2a (work@sky130_fd_sc_hd__o2bb2a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o2bb2a.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o2bb2a (work@sky130_fd_sc_hd__o2bb2a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o2bb2a.functional.v, line:35:1, endln:61:10 |vpiTypespec: \_logic_typespec: , line:44:12, endln:44:12 |vpiName:X @@ -28175,7 +28175,7 @@ design: (work@sky130_fd_sc_hd__o2bb2a) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o2bb2a.A1_N), line:37:5, endln:37:9 |vpiParent: - \_module: work@sky130_fd_sc_hd__o2bb2a (work@sky130_fd_sc_hd__o2bb2a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o2bb2a.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o2bb2a (work@sky130_fd_sc_hd__o2bb2a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o2bb2a.functional.v, line:35:1, endln:61:10 |vpiTypespec: \_logic_typespec: , line:45:12, endln:45:12 |vpiName:A1_N @@ -28183,7 +28183,7 @@ design: (work@sky130_fd_sc_hd__o2bb2a) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o2bb2a.A2_N), line:38:5, endln:38:9 |vpiParent: - \_module: work@sky130_fd_sc_hd__o2bb2a (work@sky130_fd_sc_hd__o2bb2a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o2bb2a.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o2bb2a (work@sky130_fd_sc_hd__o2bb2a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o2bb2a.functional.v, line:35:1, endln:61:10 |vpiTypespec: \_logic_typespec: , line:46:12, endln:46:12 |vpiName:A2_N @@ -28191,7 +28191,7 @@ design: (work@sky130_fd_sc_hd__o2bb2a) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o2bb2a.B1), line:39:5, endln:39:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o2bb2a (work@sky130_fd_sc_hd__o2bb2a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o2bb2a.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o2bb2a (work@sky130_fd_sc_hd__o2bb2a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o2bb2a.functional.v, line:35:1, endln:61:10 |vpiTypespec: \_logic_typespec: , line:47:12, endln:47:12 |vpiName:B1 @@ -28199,7 +28199,7 @@ design: (work@sky130_fd_sc_hd__o2bb2a) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o2bb2a.B2), line:40:5, endln:40:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o2bb2a (work@sky130_fd_sc_hd__o2bb2a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o2bb2a.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o2bb2a (work@sky130_fd_sc_hd__o2bb2a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o2bb2a.functional.v, line:35:1, endln:61:10 |vpiTypespec: \_logic_typespec: , line:48:12, endln:48:12 |vpiName:B2 @@ -28208,7 +28208,7 @@ design: (work@sky130_fd_sc_hd__o2bb2a) |vpiPort: \_port: (X), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__o2bb2a (work@sky130_fd_sc_hd__o2bb2a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o2bb2a.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o2bb2a (work@sky130_fd_sc_hd__o2bb2a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o2bb2a.functional.v, line:35:1, endln:61:10 |vpiName:X |vpiDirection:2 |vpiLowConn: @@ -28222,7 +28222,7 @@ design: (work@sky130_fd_sc_hd__o2bb2a) |vpiPort: \_port: (A1_N), line:37:5, endln:37:9 |vpiParent: - \_module: work@sky130_fd_sc_hd__o2bb2a (work@sky130_fd_sc_hd__o2bb2a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o2bb2a.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o2bb2a (work@sky130_fd_sc_hd__o2bb2a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o2bb2a.functional.v, line:35:1, endln:61:10 |vpiName:A1_N |vpiDirection:1 |vpiLowConn: @@ -28236,7 +28236,7 @@ design: (work@sky130_fd_sc_hd__o2bb2a) |vpiPort: \_port: (A2_N), line:38:5, endln:38:9 |vpiParent: - \_module: work@sky130_fd_sc_hd__o2bb2a (work@sky130_fd_sc_hd__o2bb2a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o2bb2a.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o2bb2a (work@sky130_fd_sc_hd__o2bb2a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o2bb2a.functional.v, line:35:1, endln:61:10 |vpiName:A2_N |vpiDirection:1 |vpiLowConn: @@ -28250,7 +28250,7 @@ design: (work@sky130_fd_sc_hd__o2bb2a) |vpiPort: \_port: (B1), line:39:5, endln:39:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o2bb2a (work@sky130_fd_sc_hd__o2bb2a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o2bb2a.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o2bb2a (work@sky130_fd_sc_hd__o2bb2a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o2bb2a.functional.v, line:35:1, endln:61:10 |vpiName:B1 |vpiDirection:1 |vpiLowConn: @@ -28264,7 +28264,7 @@ design: (work@sky130_fd_sc_hd__o2bb2a) |vpiPort: \_port: (B2), line:40:5, endln:40:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o2bb2a (work@sky130_fd_sc_hd__o2bb2a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o2bb2a.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o2bb2a (work@sky130_fd_sc_hd__o2bb2a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o2bb2a.functional.v, line:35:1, endln:61:10 |vpiName:B2 |vpiDirection:1 |vpiLowConn: @@ -28278,7 +28278,7 @@ design: (work@sky130_fd_sc_hd__o2bb2a) |vpiPrimitive: \_gate: work@nand (work@sky130_fd_sc_hd__o2bb2a.nand0), line:56:10, endln:56:48 |vpiParent: - \_module: work@sky130_fd_sc_hd__o2bb2a (work@sky130_fd_sc_hd__o2bb2a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o2bb2a.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o2bb2a (work@sky130_fd_sc_hd__o2bb2a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o2bb2a.functional.v, line:35:1, endln:61:10 |vpiDefName:work@nand |vpiName:nand0 |vpiFullName:work@sky130_fd_sc_hd__o2bb2a.nand0 @@ -28327,7 +28327,7 @@ design: (work@sky130_fd_sc_hd__o2bb2a) |vpiPrimitive: \_gate: work@or (work@sky130_fd_sc_hd__o2bb2a.or0), line:57:10, endln:57:48 |vpiParent: - \_module: work@sky130_fd_sc_hd__o2bb2a (work@sky130_fd_sc_hd__o2bb2a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o2bb2a.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o2bb2a (work@sky130_fd_sc_hd__o2bb2a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o2bb2a.functional.v, line:35:1, endln:61:10 |vpiDefName:work@or |vpiName:or0 |vpiFullName:work@sky130_fd_sc_hd__o2bb2a.or0 @@ -28376,7 +28376,7 @@ design: (work@sky130_fd_sc_hd__o2bb2a) |vpiPrimitive: \_gate: work@and (work@sky130_fd_sc_hd__o2bb2a.and0), line:58:10, endln:58:48 |vpiParent: - \_module: work@sky130_fd_sc_hd__o2bb2a (work@sky130_fd_sc_hd__o2bb2a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o2bb2a.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o2bb2a (work@sky130_fd_sc_hd__o2bb2a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o2bb2a.functional.v, line:35:1, endln:61:10 |vpiDefName:work@and |vpiName:and0 |vpiFullName:work@sky130_fd_sc_hd__o2bb2a.and0 @@ -28425,7 +28425,7 @@ design: (work@sky130_fd_sc_hd__o2bb2a) |vpiPrimitive: \_gate: work@buf (work@sky130_fd_sc_hd__o2bb2a.buf0), line:59:10, endln:59:48 |vpiParent: - \_module: work@sky130_fd_sc_hd__o2bb2a (work@sky130_fd_sc_hd__o2bb2a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o2bb2a.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o2bb2a (work@sky130_fd_sc_hd__o2bb2a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o2bb2a.functional.v, line:35:1, endln:61:10 |vpiDefName:work@buf |vpiName:buf0 |vpiFullName:work@sky130_fd_sc_hd__o2bb2a.buf0 @@ -28658,7 +28658,7 @@ design: (work@sky130_fd_sc_hd__edfxtp) |vpiSize:3 |STRING:? 1 1 : 1 |uhdmallModules: -\_module: work@sky130_fd_sc_hd__edfxtp (work@sky130_fd_sc_hd__edfxtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__edfxtp.functional.v, line:38:1, endln:60:10 +\_module_inst: work@sky130_fd_sc_hd__edfxtp (work@sky130_fd_sc_hd__edfxtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__edfxtp.functional.v, line:38:1, endln:60:10 |vpiParent: \_design: (work@sky130_fd_sc_hd__edfxtp) |vpiFullName:work@sky130_fd_sc_hd__edfxtp @@ -28666,45 +28666,45 @@ design: (work@sky130_fd_sc_hd__edfxtp) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__edfxtp.buf_Q), line:52:10, endln:52:15 |vpiParent: - \_module: work@sky130_fd_sc_hd__edfxtp (work@sky130_fd_sc_hd__edfxtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__edfxtp.functional.v, line:38:1, endln:60:10 + \_module_inst: work@sky130_fd_sc_hd__edfxtp (work@sky130_fd_sc_hd__edfxtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__edfxtp.functional.v, line:38:1, endln:60:10 |vpiName:buf_Q |vpiFullName:work@sky130_fd_sc_hd__edfxtp.buf_Q |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__edfxtp.mux_out), line:53:10, endln:53:17 |vpiParent: - \_module: work@sky130_fd_sc_hd__edfxtp (work@sky130_fd_sc_hd__edfxtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__edfxtp.functional.v, line:38:1, endln:60:10 + \_module_inst: work@sky130_fd_sc_hd__edfxtp (work@sky130_fd_sc_hd__edfxtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__edfxtp.functional.v, line:38:1, endln:60:10 |vpiName:mux_out |vpiFullName:work@sky130_fd_sc_hd__edfxtp.mux_out |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__edfxtp.Q), line:39:5, endln:39:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__edfxtp (work@sky130_fd_sc_hd__edfxtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__edfxtp.functional.v, line:38:1, endln:60:10 + \_module_inst: work@sky130_fd_sc_hd__edfxtp (work@sky130_fd_sc_hd__edfxtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__edfxtp.functional.v, line:38:1, endln:60:10 |vpiName:Q |vpiFullName:work@sky130_fd_sc_hd__edfxtp.Q |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__edfxtp.CLK), line:40:5, endln:40:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__edfxtp (work@sky130_fd_sc_hd__edfxtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__edfxtp.functional.v, line:38:1, endln:60:10 + \_module_inst: work@sky130_fd_sc_hd__edfxtp (work@sky130_fd_sc_hd__edfxtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__edfxtp.functional.v, line:38:1, endln:60:10 |vpiName:CLK |vpiFullName:work@sky130_fd_sc_hd__edfxtp.CLK |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__edfxtp.D), line:41:5, endln:41:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__edfxtp (work@sky130_fd_sc_hd__edfxtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__edfxtp.functional.v, line:38:1, endln:60:10 + \_module_inst: work@sky130_fd_sc_hd__edfxtp (work@sky130_fd_sc_hd__edfxtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__edfxtp.functional.v, line:38:1, endln:60:10 |vpiName:D |vpiFullName:work@sky130_fd_sc_hd__edfxtp.D |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__edfxtp.DE), line:42:5, endln:42:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__edfxtp (work@sky130_fd_sc_hd__edfxtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__edfxtp.functional.v, line:38:1, endln:60:10 + \_module_inst: work@sky130_fd_sc_hd__edfxtp (work@sky130_fd_sc_hd__edfxtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__edfxtp.functional.v, line:38:1, endln:60:10 |vpiName:DE |vpiFullName:work@sky130_fd_sc_hd__edfxtp.DE |vpiPort: \_port: (Q), line:39:5, endln:39:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__edfxtp (work@sky130_fd_sc_hd__edfxtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__edfxtp.functional.v, line:38:1, endln:60:10 + \_module_inst: work@sky130_fd_sc_hd__edfxtp (work@sky130_fd_sc_hd__edfxtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__edfxtp.functional.v, line:38:1, endln:60:10 |vpiName:Q |vpiDirection:2 |vpiLowConn: @@ -28716,7 +28716,7 @@ design: (work@sky130_fd_sc_hd__edfxtp) |vpiPort: \_port: (CLK), line:40:5, endln:40:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__edfxtp (work@sky130_fd_sc_hd__edfxtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__edfxtp.functional.v, line:38:1, endln:60:10 + \_module_inst: work@sky130_fd_sc_hd__edfxtp (work@sky130_fd_sc_hd__edfxtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__edfxtp.functional.v, line:38:1, endln:60:10 |vpiName:CLK |vpiDirection:1 |vpiLowConn: @@ -28728,7 +28728,7 @@ design: (work@sky130_fd_sc_hd__edfxtp) |vpiPort: \_port: (D), line:41:5, endln:41:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__edfxtp (work@sky130_fd_sc_hd__edfxtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__edfxtp.functional.v, line:38:1, endln:60:10 + \_module_inst: work@sky130_fd_sc_hd__edfxtp (work@sky130_fd_sc_hd__edfxtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__edfxtp.functional.v, line:38:1, endln:60:10 |vpiName:D |vpiDirection:1 |vpiLowConn: @@ -28740,7 +28740,7 @@ design: (work@sky130_fd_sc_hd__edfxtp) |vpiPort: \_port: (DE), line:42:5, endln:42:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__edfxtp (work@sky130_fd_sc_hd__edfxtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__edfxtp.functional.v, line:38:1, endln:60:10 + \_module_inst: work@sky130_fd_sc_hd__edfxtp (work@sky130_fd_sc_hd__edfxtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__edfxtp.functional.v, line:38:1, endln:60:10 |vpiName:DE |vpiDirection:1 |vpiLowConn: @@ -28750,14 +28750,14 @@ design: (work@sky130_fd_sc_hd__edfxtp) |vpiTypedef: \_logic_typespec: , line:49:12, endln:49:12 |uhdmtopModules: -\_module: work@sky130_fd_sc_hd__edfxtp (work@sky130_fd_sc_hd__edfxtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__edfxtp.functional.v, line:38:1, endln:60:10 +\_module_inst: work@sky130_fd_sc_hd__edfxtp (work@sky130_fd_sc_hd__edfxtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__edfxtp.functional.v, line:38:1, endln:60:10 |vpiName:work@sky130_fd_sc_hd__edfxtp |vpiDefName:work@sky130_fd_sc_hd__edfxtp |vpiTop:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__edfxtp.buf_Q), line:52:10, endln:52:15 |vpiParent: - \_module: work@sky130_fd_sc_hd__edfxtp (work@sky130_fd_sc_hd__edfxtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__edfxtp.functional.v, line:38:1, endln:60:10 + \_module_inst: work@sky130_fd_sc_hd__edfxtp (work@sky130_fd_sc_hd__edfxtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__edfxtp.functional.v, line:38:1, endln:60:10 |vpiTypespec: \_logic_typespec: , line:52:5, endln:52:9 |vpiName:buf_Q @@ -28766,7 +28766,7 @@ design: (work@sky130_fd_sc_hd__edfxtp) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__edfxtp.mux_out), line:53:10, endln:53:17 |vpiParent: - \_module: work@sky130_fd_sc_hd__edfxtp (work@sky130_fd_sc_hd__edfxtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__edfxtp.functional.v, line:38:1, endln:60:10 + \_module_inst: work@sky130_fd_sc_hd__edfxtp (work@sky130_fd_sc_hd__edfxtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__edfxtp.functional.v, line:38:1, endln:60:10 |vpiTypespec: \_logic_typespec: , line:53:5, endln:53:9 |vpiName:mux_out @@ -28775,7 +28775,7 @@ design: (work@sky130_fd_sc_hd__edfxtp) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__edfxtp.Q), line:39:5, endln:39:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__edfxtp (work@sky130_fd_sc_hd__edfxtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__edfxtp.functional.v, line:38:1, endln:60:10 + \_module_inst: work@sky130_fd_sc_hd__edfxtp (work@sky130_fd_sc_hd__edfxtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__edfxtp.functional.v, line:38:1, endln:60:10 |vpiTypespec: \_logic_typespec: , line:46:12, endln:46:12 |vpiName:Q @@ -28783,7 +28783,7 @@ design: (work@sky130_fd_sc_hd__edfxtp) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__edfxtp.CLK), line:40:5, endln:40:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__edfxtp (work@sky130_fd_sc_hd__edfxtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__edfxtp.functional.v, line:38:1, endln:60:10 + \_module_inst: work@sky130_fd_sc_hd__edfxtp (work@sky130_fd_sc_hd__edfxtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__edfxtp.functional.v, line:38:1, endln:60:10 |vpiTypespec: \_logic_typespec: , line:47:12, endln:47:12 |vpiName:CLK @@ -28791,7 +28791,7 @@ design: (work@sky130_fd_sc_hd__edfxtp) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__edfxtp.D), line:41:5, endln:41:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__edfxtp (work@sky130_fd_sc_hd__edfxtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__edfxtp.functional.v, line:38:1, endln:60:10 + \_module_inst: work@sky130_fd_sc_hd__edfxtp (work@sky130_fd_sc_hd__edfxtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__edfxtp.functional.v, line:38:1, endln:60:10 |vpiTypespec: \_logic_typespec: , line:48:12, endln:48:12 |vpiName:D @@ -28799,7 +28799,7 @@ design: (work@sky130_fd_sc_hd__edfxtp) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__edfxtp.DE), line:42:5, endln:42:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__edfxtp (work@sky130_fd_sc_hd__edfxtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__edfxtp.functional.v, line:38:1, endln:60:10 + \_module_inst: work@sky130_fd_sc_hd__edfxtp (work@sky130_fd_sc_hd__edfxtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__edfxtp.functional.v, line:38:1, endln:60:10 |vpiTypespec: \_logic_typespec: , line:49:12, endln:49:12 |vpiName:DE @@ -28808,7 +28808,7 @@ design: (work@sky130_fd_sc_hd__edfxtp) |vpiPort: \_port: (Q), line:39:5, endln:39:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__edfxtp (work@sky130_fd_sc_hd__edfxtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__edfxtp.functional.v, line:38:1, endln:60:10 + \_module_inst: work@sky130_fd_sc_hd__edfxtp (work@sky130_fd_sc_hd__edfxtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__edfxtp.functional.v, line:38:1, endln:60:10 |vpiName:Q |vpiDirection:2 |vpiLowConn: @@ -28822,7 +28822,7 @@ design: (work@sky130_fd_sc_hd__edfxtp) |vpiPort: \_port: (CLK), line:40:5, endln:40:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__edfxtp (work@sky130_fd_sc_hd__edfxtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__edfxtp.functional.v, line:38:1, endln:60:10 + \_module_inst: work@sky130_fd_sc_hd__edfxtp (work@sky130_fd_sc_hd__edfxtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__edfxtp.functional.v, line:38:1, endln:60:10 |vpiName:CLK |vpiDirection:1 |vpiLowConn: @@ -28836,7 +28836,7 @@ design: (work@sky130_fd_sc_hd__edfxtp) |vpiPort: \_port: (D), line:41:5, endln:41:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__edfxtp (work@sky130_fd_sc_hd__edfxtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__edfxtp.functional.v, line:38:1, endln:60:10 + \_module_inst: work@sky130_fd_sc_hd__edfxtp (work@sky130_fd_sc_hd__edfxtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__edfxtp.functional.v, line:38:1, endln:60:10 |vpiName:D |vpiDirection:1 |vpiLowConn: @@ -28850,7 +28850,7 @@ design: (work@sky130_fd_sc_hd__edfxtp) |vpiPort: \_port: (DE), line:42:5, endln:42:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__edfxtp (work@sky130_fd_sc_hd__edfxtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__edfxtp.functional.v, line:38:1, endln:60:10 + \_module_inst: work@sky130_fd_sc_hd__edfxtp (work@sky130_fd_sc_hd__edfxtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__edfxtp.functional.v, line:38:1, endln:60:10 |vpiName:DE |vpiDirection:1 |vpiLowConn: @@ -28864,7 +28864,7 @@ design: (work@sky130_fd_sc_hd__edfxtp) |vpiPrimitive: \_udp: work@sky130_fd_sc_hd__udp_mux_2to1 (work@sky130_fd_sc_hd__edfxtp.mux_2to10), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__edfxtp.functional.v, line:56:5, endln:56:84 |vpiParent: - \_module: work@sky130_fd_sc_hd__edfxtp (work@sky130_fd_sc_hd__edfxtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__edfxtp.functional.v, line:38:1, endln:60:10 + \_module_inst: work@sky130_fd_sc_hd__edfxtp (work@sky130_fd_sc_hd__edfxtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__edfxtp.functional.v, line:38:1, endln:60:10 |vpiDefName:work@sky130_fd_sc_hd__udp_mux_2to1 |vpiName:mux_2to10 |vpiFullName:work@sky130_fd_sc_hd__edfxtp.mux_2to10 @@ -28873,7 +28873,7 @@ design: (work@sky130_fd_sc_hd__edfxtp) |vpiPrimitive: \_udp: work@sky130_fd_sc_hd__udp_dff$P (work@sky130_fd_sc_hd__edfxtp.dff0), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__edfxtp.functional.v, line:57:5, endln:57:73 |vpiParent: - \_module: work@sky130_fd_sc_hd__edfxtp (work@sky130_fd_sc_hd__edfxtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__edfxtp.functional.v, line:38:1, endln:60:10 + \_module_inst: work@sky130_fd_sc_hd__edfxtp (work@sky130_fd_sc_hd__edfxtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__edfxtp.functional.v, line:38:1, endln:60:10 |vpiDefName:work@sky130_fd_sc_hd__udp_dff$P |vpiName:dff0 |vpiFullName:work@sky130_fd_sc_hd__edfxtp.dff0 @@ -28882,7 +28882,7 @@ design: (work@sky130_fd_sc_hd__edfxtp) |vpiPrimitive: \_gate: work@buf (work@sky130_fd_sc_hd__edfxtp.buf0), line:58:47, endln:58:83 |vpiParent: - \_module: work@sky130_fd_sc_hd__edfxtp (work@sky130_fd_sc_hd__edfxtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__edfxtp.functional.v, line:38:1, endln:60:10 + \_module_inst: work@sky130_fd_sc_hd__edfxtp (work@sky130_fd_sc_hd__edfxtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__edfxtp.functional.v, line:38:1, endln:60:10 |vpiDefName:work@buf |vpiName:buf0 |vpiFullName:work@sky130_fd_sc_hd__edfxtp.buf0 @@ -29145,7 +29145,7 @@ design: (work@sky130_fd_sc_hd__sdfbbp) |vpiSize:3 |STRING:? 1 1 : 1 |uhdmallModules: -\_module: work@sky130_fd_sc_hd__sdfbbp (work@sky130_fd_sc_hd__sdfbbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfbbp.functional.v, line:38:1, endln:73:10 +\_module_inst: work@sky130_fd_sc_hd__sdfbbp (work@sky130_fd_sc_hd__sdfbbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfbbp.functional.v, line:38:1, endln:73:10 |vpiParent: \_design: (work@sky130_fd_sc_hd__sdfbbp) |vpiFullName:work@sky130_fd_sc_hd__sdfbbp @@ -29153,83 +29153,83 @@ design: (work@sky130_fd_sc_hd__sdfbbp) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__sdfbbp.RESET), line:60:10, endln:60:15 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfbbp (work@sky130_fd_sc_hd__sdfbbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfbbp.functional.v, line:38:1, endln:73:10 + \_module_inst: work@sky130_fd_sc_hd__sdfbbp (work@sky130_fd_sc_hd__sdfbbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfbbp.functional.v, line:38:1, endln:73:10 |vpiName:RESET |vpiFullName:work@sky130_fd_sc_hd__sdfbbp.RESET |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__sdfbbp.SET), line:61:10, endln:61:13 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfbbp (work@sky130_fd_sc_hd__sdfbbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfbbp.functional.v, line:38:1, endln:73:10 + \_module_inst: work@sky130_fd_sc_hd__sdfbbp (work@sky130_fd_sc_hd__sdfbbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfbbp.functional.v, line:38:1, endln:73:10 |vpiName:SET |vpiFullName:work@sky130_fd_sc_hd__sdfbbp.SET |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__sdfbbp.buf_Q), line:62:10, endln:62:15 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfbbp (work@sky130_fd_sc_hd__sdfbbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfbbp.functional.v, line:38:1, endln:73:10 + \_module_inst: work@sky130_fd_sc_hd__sdfbbp (work@sky130_fd_sc_hd__sdfbbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfbbp.functional.v, line:38:1, endln:73:10 |vpiName:buf_Q |vpiFullName:work@sky130_fd_sc_hd__sdfbbp.buf_Q |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__sdfbbp.mux_out), line:63:10, endln:63:17 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfbbp (work@sky130_fd_sc_hd__sdfbbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfbbp.functional.v, line:38:1, endln:73:10 + \_module_inst: work@sky130_fd_sc_hd__sdfbbp (work@sky130_fd_sc_hd__sdfbbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfbbp.functional.v, line:38:1, endln:73:10 |vpiName:mux_out |vpiFullName:work@sky130_fd_sc_hd__sdfbbp.mux_out |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__sdfbbp.Q), line:39:5, endln:39:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfbbp (work@sky130_fd_sc_hd__sdfbbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfbbp.functional.v, line:38:1, endln:73:10 + \_module_inst: work@sky130_fd_sc_hd__sdfbbp (work@sky130_fd_sc_hd__sdfbbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfbbp.functional.v, line:38:1, endln:73:10 |vpiName:Q |vpiFullName:work@sky130_fd_sc_hd__sdfbbp.Q |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__sdfbbp.Q_N), line:40:5, endln:40:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfbbp (work@sky130_fd_sc_hd__sdfbbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfbbp.functional.v, line:38:1, endln:73:10 + \_module_inst: work@sky130_fd_sc_hd__sdfbbp (work@sky130_fd_sc_hd__sdfbbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfbbp.functional.v, line:38:1, endln:73:10 |vpiName:Q_N |vpiFullName:work@sky130_fd_sc_hd__sdfbbp.Q_N |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__sdfbbp.D), line:41:5, endln:41:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfbbp (work@sky130_fd_sc_hd__sdfbbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfbbp.functional.v, line:38:1, endln:73:10 + \_module_inst: work@sky130_fd_sc_hd__sdfbbp (work@sky130_fd_sc_hd__sdfbbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfbbp.functional.v, line:38:1, endln:73:10 |vpiName:D |vpiFullName:work@sky130_fd_sc_hd__sdfbbp.D |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__sdfbbp.SCD), line:42:5, endln:42:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfbbp (work@sky130_fd_sc_hd__sdfbbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfbbp.functional.v, line:38:1, endln:73:10 + \_module_inst: work@sky130_fd_sc_hd__sdfbbp (work@sky130_fd_sc_hd__sdfbbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfbbp.functional.v, line:38:1, endln:73:10 |vpiName:SCD |vpiFullName:work@sky130_fd_sc_hd__sdfbbp.SCD |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__sdfbbp.SCE), line:43:5, endln:43:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfbbp (work@sky130_fd_sc_hd__sdfbbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfbbp.functional.v, line:38:1, endln:73:10 + \_module_inst: work@sky130_fd_sc_hd__sdfbbp (work@sky130_fd_sc_hd__sdfbbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfbbp.functional.v, line:38:1, endln:73:10 |vpiName:SCE |vpiFullName:work@sky130_fd_sc_hd__sdfbbp.SCE |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__sdfbbp.CLK), line:44:5, endln:44:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfbbp (work@sky130_fd_sc_hd__sdfbbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfbbp.functional.v, line:38:1, endln:73:10 + \_module_inst: work@sky130_fd_sc_hd__sdfbbp (work@sky130_fd_sc_hd__sdfbbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfbbp.functional.v, line:38:1, endln:73:10 |vpiName:CLK |vpiFullName:work@sky130_fd_sc_hd__sdfbbp.CLK |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__sdfbbp.SET_B), line:45:5, endln:45:10 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfbbp (work@sky130_fd_sc_hd__sdfbbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfbbp.functional.v, line:38:1, endln:73:10 + \_module_inst: work@sky130_fd_sc_hd__sdfbbp (work@sky130_fd_sc_hd__sdfbbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfbbp.functional.v, line:38:1, endln:73:10 |vpiName:SET_B |vpiFullName:work@sky130_fd_sc_hd__sdfbbp.SET_B |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__sdfbbp.RESET_B), line:46:5, endln:46:12 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfbbp (work@sky130_fd_sc_hd__sdfbbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfbbp.functional.v, line:38:1, endln:73:10 + \_module_inst: work@sky130_fd_sc_hd__sdfbbp (work@sky130_fd_sc_hd__sdfbbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfbbp.functional.v, line:38:1, endln:73:10 |vpiName:RESET_B |vpiFullName:work@sky130_fd_sc_hd__sdfbbp.RESET_B |vpiPort: \_port: (Q), line:39:5, endln:39:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfbbp (work@sky130_fd_sc_hd__sdfbbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfbbp.functional.v, line:38:1, endln:73:10 + \_module_inst: work@sky130_fd_sc_hd__sdfbbp (work@sky130_fd_sc_hd__sdfbbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfbbp.functional.v, line:38:1, endln:73:10 |vpiName:Q |vpiDirection:2 |vpiLowConn: @@ -29241,7 +29241,7 @@ design: (work@sky130_fd_sc_hd__sdfbbp) |vpiPort: \_port: (Q_N), line:40:5, endln:40:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfbbp (work@sky130_fd_sc_hd__sdfbbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfbbp.functional.v, line:38:1, endln:73:10 + \_module_inst: work@sky130_fd_sc_hd__sdfbbp (work@sky130_fd_sc_hd__sdfbbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfbbp.functional.v, line:38:1, endln:73:10 |vpiName:Q_N |vpiDirection:2 |vpiLowConn: @@ -29253,7 +29253,7 @@ design: (work@sky130_fd_sc_hd__sdfbbp) |vpiPort: \_port: (D), line:41:5, endln:41:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfbbp (work@sky130_fd_sc_hd__sdfbbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfbbp.functional.v, line:38:1, endln:73:10 + \_module_inst: work@sky130_fd_sc_hd__sdfbbp (work@sky130_fd_sc_hd__sdfbbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfbbp.functional.v, line:38:1, endln:73:10 |vpiName:D |vpiDirection:1 |vpiLowConn: @@ -29265,7 +29265,7 @@ design: (work@sky130_fd_sc_hd__sdfbbp) |vpiPort: \_port: (SCD), line:42:5, endln:42:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfbbp (work@sky130_fd_sc_hd__sdfbbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfbbp.functional.v, line:38:1, endln:73:10 + \_module_inst: work@sky130_fd_sc_hd__sdfbbp (work@sky130_fd_sc_hd__sdfbbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfbbp.functional.v, line:38:1, endln:73:10 |vpiName:SCD |vpiDirection:1 |vpiLowConn: @@ -29277,7 +29277,7 @@ design: (work@sky130_fd_sc_hd__sdfbbp) |vpiPort: \_port: (SCE), line:43:5, endln:43:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfbbp (work@sky130_fd_sc_hd__sdfbbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfbbp.functional.v, line:38:1, endln:73:10 + \_module_inst: work@sky130_fd_sc_hd__sdfbbp (work@sky130_fd_sc_hd__sdfbbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfbbp.functional.v, line:38:1, endln:73:10 |vpiName:SCE |vpiDirection:1 |vpiLowConn: @@ -29289,7 +29289,7 @@ design: (work@sky130_fd_sc_hd__sdfbbp) |vpiPort: \_port: (CLK), line:44:5, endln:44:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfbbp (work@sky130_fd_sc_hd__sdfbbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfbbp.functional.v, line:38:1, endln:73:10 + \_module_inst: work@sky130_fd_sc_hd__sdfbbp (work@sky130_fd_sc_hd__sdfbbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfbbp.functional.v, line:38:1, endln:73:10 |vpiName:CLK |vpiDirection:1 |vpiLowConn: @@ -29301,7 +29301,7 @@ design: (work@sky130_fd_sc_hd__sdfbbp) |vpiPort: \_port: (SET_B), line:45:5, endln:45:10 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfbbp (work@sky130_fd_sc_hd__sdfbbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfbbp.functional.v, line:38:1, endln:73:10 + \_module_inst: work@sky130_fd_sc_hd__sdfbbp (work@sky130_fd_sc_hd__sdfbbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfbbp.functional.v, line:38:1, endln:73:10 |vpiName:SET_B |vpiDirection:1 |vpiLowConn: @@ -29313,7 +29313,7 @@ design: (work@sky130_fd_sc_hd__sdfbbp) |vpiPort: \_port: (RESET_B), line:46:5, endln:46:12 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfbbp (work@sky130_fd_sc_hd__sdfbbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfbbp.functional.v, line:38:1, endln:73:10 + \_module_inst: work@sky130_fd_sc_hd__sdfbbp (work@sky130_fd_sc_hd__sdfbbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfbbp.functional.v, line:38:1, endln:73:10 |vpiName:RESET_B |vpiDirection:1 |vpiLowConn: @@ -29323,14 +29323,14 @@ design: (work@sky130_fd_sc_hd__sdfbbp) |vpiTypedef: \_logic_typespec: , line:57:12, endln:57:12 |uhdmtopModules: -\_module: work@sky130_fd_sc_hd__sdfbbp (work@sky130_fd_sc_hd__sdfbbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfbbp.functional.v, line:38:1, endln:73:10 +\_module_inst: work@sky130_fd_sc_hd__sdfbbp (work@sky130_fd_sc_hd__sdfbbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfbbp.functional.v, line:38:1, endln:73:10 |vpiName:work@sky130_fd_sc_hd__sdfbbp |vpiDefName:work@sky130_fd_sc_hd__sdfbbp |vpiTop:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__sdfbbp.RESET), line:60:10, endln:60:15 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfbbp (work@sky130_fd_sc_hd__sdfbbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfbbp.functional.v, line:38:1, endln:73:10 + \_module_inst: work@sky130_fd_sc_hd__sdfbbp (work@sky130_fd_sc_hd__sdfbbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfbbp.functional.v, line:38:1, endln:73:10 |vpiTypespec: \_logic_typespec: , line:60:5, endln:60:9 |vpiName:RESET @@ -29339,7 +29339,7 @@ design: (work@sky130_fd_sc_hd__sdfbbp) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__sdfbbp.SET), line:61:10, endln:61:13 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfbbp (work@sky130_fd_sc_hd__sdfbbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfbbp.functional.v, line:38:1, endln:73:10 + \_module_inst: work@sky130_fd_sc_hd__sdfbbp (work@sky130_fd_sc_hd__sdfbbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfbbp.functional.v, line:38:1, endln:73:10 |vpiTypespec: \_logic_typespec: , line:61:5, endln:61:9 |vpiName:SET @@ -29348,7 +29348,7 @@ design: (work@sky130_fd_sc_hd__sdfbbp) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__sdfbbp.buf_Q), line:62:10, endln:62:15 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfbbp (work@sky130_fd_sc_hd__sdfbbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfbbp.functional.v, line:38:1, endln:73:10 + \_module_inst: work@sky130_fd_sc_hd__sdfbbp (work@sky130_fd_sc_hd__sdfbbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfbbp.functional.v, line:38:1, endln:73:10 |vpiTypespec: \_logic_typespec: , line:62:5, endln:62:9 |vpiName:buf_Q @@ -29357,7 +29357,7 @@ design: (work@sky130_fd_sc_hd__sdfbbp) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__sdfbbp.mux_out), line:63:10, endln:63:17 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfbbp (work@sky130_fd_sc_hd__sdfbbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfbbp.functional.v, line:38:1, endln:73:10 + \_module_inst: work@sky130_fd_sc_hd__sdfbbp (work@sky130_fd_sc_hd__sdfbbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfbbp.functional.v, line:38:1, endln:73:10 |vpiTypespec: \_logic_typespec: , line:63:5, endln:63:9 |vpiName:mux_out @@ -29366,7 +29366,7 @@ design: (work@sky130_fd_sc_hd__sdfbbp) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__sdfbbp.Q), line:39:5, endln:39:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfbbp (work@sky130_fd_sc_hd__sdfbbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfbbp.functional.v, line:38:1, endln:73:10 + \_module_inst: work@sky130_fd_sc_hd__sdfbbp (work@sky130_fd_sc_hd__sdfbbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfbbp.functional.v, line:38:1, endln:73:10 |vpiTypespec: \_logic_typespec: , line:50:12, endln:50:12 |vpiName:Q @@ -29374,7 +29374,7 @@ design: (work@sky130_fd_sc_hd__sdfbbp) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__sdfbbp.Q_N), line:40:5, endln:40:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfbbp (work@sky130_fd_sc_hd__sdfbbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfbbp.functional.v, line:38:1, endln:73:10 + \_module_inst: work@sky130_fd_sc_hd__sdfbbp (work@sky130_fd_sc_hd__sdfbbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfbbp.functional.v, line:38:1, endln:73:10 |vpiTypespec: \_logic_typespec: , line:51:12, endln:51:12 |vpiName:Q_N @@ -29382,7 +29382,7 @@ design: (work@sky130_fd_sc_hd__sdfbbp) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__sdfbbp.D), line:41:5, endln:41:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfbbp (work@sky130_fd_sc_hd__sdfbbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfbbp.functional.v, line:38:1, endln:73:10 + \_module_inst: work@sky130_fd_sc_hd__sdfbbp (work@sky130_fd_sc_hd__sdfbbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfbbp.functional.v, line:38:1, endln:73:10 |vpiTypespec: \_logic_typespec: , line:52:12, endln:52:12 |vpiName:D @@ -29390,7 +29390,7 @@ design: (work@sky130_fd_sc_hd__sdfbbp) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__sdfbbp.SCD), line:42:5, endln:42:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfbbp (work@sky130_fd_sc_hd__sdfbbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfbbp.functional.v, line:38:1, endln:73:10 + \_module_inst: work@sky130_fd_sc_hd__sdfbbp (work@sky130_fd_sc_hd__sdfbbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfbbp.functional.v, line:38:1, endln:73:10 |vpiTypespec: \_logic_typespec: , line:53:12, endln:53:12 |vpiName:SCD @@ -29398,7 +29398,7 @@ design: (work@sky130_fd_sc_hd__sdfbbp) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__sdfbbp.SCE), line:43:5, endln:43:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfbbp (work@sky130_fd_sc_hd__sdfbbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfbbp.functional.v, line:38:1, endln:73:10 + \_module_inst: work@sky130_fd_sc_hd__sdfbbp (work@sky130_fd_sc_hd__sdfbbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfbbp.functional.v, line:38:1, endln:73:10 |vpiTypespec: \_logic_typespec: , line:54:12, endln:54:12 |vpiName:SCE @@ -29406,7 +29406,7 @@ design: (work@sky130_fd_sc_hd__sdfbbp) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__sdfbbp.CLK), line:44:5, endln:44:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfbbp (work@sky130_fd_sc_hd__sdfbbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfbbp.functional.v, line:38:1, endln:73:10 + \_module_inst: work@sky130_fd_sc_hd__sdfbbp (work@sky130_fd_sc_hd__sdfbbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfbbp.functional.v, line:38:1, endln:73:10 |vpiTypespec: \_logic_typespec: , line:55:12, endln:55:12 |vpiName:CLK @@ -29414,7 +29414,7 @@ design: (work@sky130_fd_sc_hd__sdfbbp) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__sdfbbp.SET_B), line:45:5, endln:45:10 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfbbp (work@sky130_fd_sc_hd__sdfbbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfbbp.functional.v, line:38:1, endln:73:10 + \_module_inst: work@sky130_fd_sc_hd__sdfbbp (work@sky130_fd_sc_hd__sdfbbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfbbp.functional.v, line:38:1, endln:73:10 |vpiTypespec: \_logic_typespec: , line:56:12, endln:56:12 |vpiName:SET_B @@ -29422,7 +29422,7 @@ design: (work@sky130_fd_sc_hd__sdfbbp) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__sdfbbp.RESET_B), line:46:5, endln:46:12 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfbbp (work@sky130_fd_sc_hd__sdfbbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfbbp.functional.v, line:38:1, endln:73:10 + \_module_inst: work@sky130_fd_sc_hd__sdfbbp (work@sky130_fd_sc_hd__sdfbbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfbbp.functional.v, line:38:1, endln:73:10 |vpiTypespec: \_logic_typespec: , line:57:12, endln:57:12 |vpiName:RESET_B @@ -29431,7 +29431,7 @@ design: (work@sky130_fd_sc_hd__sdfbbp) |vpiPort: \_port: (Q), line:39:5, endln:39:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfbbp (work@sky130_fd_sc_hd__sdfbbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfbbp.functional.v, line:38:1, endln:73:10 + \_module_inst: work@sky130_fd_sc_hd__sdfbbp (work@sky130_fd_sc_hd__sdfbbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfbbp.functional.v, line:38:1, endln:73:10 |vpiName:Q |vpiDirection:2 |vpiLowConn: @@ -29445,7 +29445,7 @@ design: (work@sky130_fd_sc_hd__sdfbbp) |vpiPort: \_port: (Q_N), line:40:5, endln:40:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfbbp (work@sky130_fd_sc_hd__sdfbbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfbbp.functional.v, line:38:1, endln:73:10 + \_module_inst: work@sky130_fd_sc_hd__sdfbbp (work@sky130_fd_sc_hd__sdfbbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfbbp.functional.v, line:38:1, endln:73:10 |vpiName:Q_N |vpiDirection:2 |vpiLowConn: @@ -29459,7 +29459,7 @@ design: (work@sky130_fd_sc_hd__sdfbbp) |vpiPort: \_port: (D), line:41:5, endln:41:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfbbp (work@sky130_fd_sc_hd__sdfbbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfbbp.functional.v, line:38:1, endln:73:10 + \_module_inst: work@sky130_fd_sc_hd__sdfbbp (work@sky130_fd_sc_hd__sdfbbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfbbp.functional.v, line:38:1, endln:73:10 |vpiName:D |vpiDirection:1 |vpiLowConn: @@ -29473,7 +29473,7 @@ design: (work@sky130_fd_sc_hd__sdfbbp) |vpiPort: \_port: (SCD), line:42:5, endln:42:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfbbp (work@sky130_fd_sc_hd__sdfbbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfbbp.functional.v, line:38:1, endln:73:10 + \_module_inst: work@sky130_fd_sc_hd__sdfbbp (work@sky130_fd_sc_hd__sdfbbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfbbp.functional.v, line:38:1, endln:73:10 |vpiName:SCD |vpiDirection:1 |vpiLowConn: @@ -29487,7 +29487,7 @@ design: (work@sky130_fd_sc_hd__sdfbbp) |vpiPort: \_port: (SCE), line:43:5, endln:43:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfbbp (work@sky130_fd_sc_hd__sdfbbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfbbp.functional.v, line:38:1, endln:73:10 + \_module_inst: work@sky130_fd_sc_hd__sdfbbp (work@sky130_fd_sc_hd__sdfbbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfbbp.functional.v, line:38:1, endln:73:10 |vpiName:SCE |vpiDirection:1 |vpiLowConn: @@ -29501,7 +29501,7 @@ design: (work@sky130_fd_sc_hd__sdfbbp) |vpiPort: \_port: (CLK), line:44:5, endln:44:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfbbp (work@sky130_fd_sc_hd__sdfbbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfbbp.functional.v, line:38:1, endln:73:10 + \_module_inst: work@sky130_fd_sc_hd__sdfbbp (work@sky130_fd_sc_hd__sdfbbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfbbp.functional.v, line:38:1, endln:73:10 |vpiName:CLK |vpiDirection:1 |vpiLowConn: @@ -29515,7 +29515,7 @@ design: (work@sky130_fd_sc_hd__sdfbbp) |vpiPort: \_port: (SET_B), line:45:5, endln:45:10 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfbbp (work@sky130_fd_sc_hd__sdfbbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfbbp.functional.v, line:38:1, endln:73:10 + \_module_inst: work@sky130_fd_sc_hd__sdfbbp (work@sky130_fd_sc_hd__sdfbbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfbbp.functional.v, line:38:1, endln:73:10 |vpiName:SET_B |vpiDirection:1 |vpiLowConn: @@ -29529,7 +29529,7 @@ design: (work@sky130_fd_sc_hd__sdfbbp) |vpiPort: \_port: (RESET_B), line:46:5, endln:46:12 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfbbp (work@sky130_fd_sc_hd__sdfbbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfbbp.functional.v, line:38:1, endln:73:10 + \_module_inst: work@sky130_fd_sc_hd__sdfbbp (work@sky130_fd_sc_hd__sdfbbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfbbp.functional.v, line:38:1, endln:73:10 |vpiName:RESET_B |vpiDirection:1 |vpiLowConn: @@ -29543,7 +29543,7 @@ design: (work@sky130_fd_sc_hd__sdfbbp) |vpiPrimitive: \_gate: work@not (work@sky130_fd_sc_hd__sdfbbp.not0), line:66:47, endln:66:92 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfbbp (work@sky130_fd_sc_hd__sdfbbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfbbp.functional.v, line:38:1, endln:73:10 + \_module_inst: work@sky130_fd_sc_hd__sdfbbp (work@sky130_fd_sc_hd__sdfbbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfbbp.functional.v, line:38:1, endln:73:10 |vpiDefName:work@not |vpiName:not0 |vpiFullName:work@sky130_fd_sc_hd__sdfbbp.not0 @@ -29578,7 +29578,7 @@ design: (work@sky130_fd_sc_hd__sdfbbp) |vpiPrimitive: \_gate: work@not (work@sky130_fd_sc_hd__sdfbbp.not1), line:67:47, endln:67:92 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfbbp (work@sky130_fd_sc_hd__sdfbbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfbbp.functional.v, line:38:1, endln:73:10 + \_module_inst: work@sky130_fd_sc_hd__sdfbbp (work@sky130_fd_sc_hd__sdfbbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfbbp.functional.v, line:38:1, endln:73:10 |vpiDefName:work@not |vpiName:not1 |vpiFullName:work@sky130_fd_sc_hd__sdfbbp.not1 @@ -29613,7 +29613,7 @@ design: (work@sky130_fd_sc_hd__sdfbbp) |vpiPrimitive: \_udp: work@sky130_fd_sc_hd__udp_mux_2to1 (work@sky130_fd_sc_hd__sdfbbp.mux_2to10), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfbbp.functional.v, line:68:5, endln:68:93 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfbbp (work@sky130_fd_sc_hd__sdfbbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfbbp.functional.v, line:38:1, endln:73:10 + \_module_inst: work@sky130_fd_sc_hd__sdfbbp (work@sky130_fd_sc_hd__sdfbbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfbbp.functional.v, line:38:1, endln:73:10 |vpiDefName:work@sky130_fd_sc_hd__udp_mux_2to1 |vpiName:mux_2to10 |vpiFullName:work@sky130_fd_sc_hd__sdfbbp.mux_2to10 @@ -29622,7 +29622,7 @@ design: (work@sky130_fd_sc_hd__sdfbbp) |vpiPrimitive: \_udp: work@sky130_fd_sc_hd__udp_dff$NSR (work@sky130_fd_sc_hd__sdfbbp.dff0), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfbbp.functional.v, line:69:5, endln:69:82 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfbbp (work@sky130_fd_sc_hd__sdfbbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfbbp.functional.v, line:38:1, endln:73:10 + \_module_inst: work@sky130_fd_sc_hd__sdfbbp (work@sky130_fd_sc_hd__sdfbbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfbbp.functional.v, line:38:1, endln:73:10 |vpiDefName:work@sky130_fd_sc_hd__udp_dff$NSR |vpiName:dff0 |vpiFullName:work@sky130_fd_sc_hd__sdfbbp.dff0 @@ -29631,7 +29631,7 @@ design: (work@sky130_fd_sc_hd__sdfbbp) |vpiPrimitive: \_gate: work@buf (work@sky130_fd_sc_hd__sdfbbp.buf0), line:70:47, endln:70:92 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfbbp (work@sky130_fd_sc_hd__sdfbbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfbbp.functional.v, line:38:1, endln:73:10 + \_module_inst: work@sky130_fd_sc_hd__sdfbbp (work@sky130_fd_sc_hd__sdfbbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfbbp.functional.v, line:38:1, endln:73:10 |vpiDefName:work@buf |vpiName:buf0 |vpiFullName:work@sky130_fd_sc_hd__sdfbbp.buf0 @@ -29666,7 +29666,7 @@ design: (work@sky130_fd_sc_hd__sdfbbp) |vpiPrimitive: \_gate: work@not (work@sky130_fd_sc_hd__sdfbbp.not2), line:71:47, endln:71:92 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfbbp (work@sky130_fd_sc_hd__sdfbbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfbbp.functional.v, line:38:1, endln:73:10 + \_module_inst: work@sky130_fd_sc_hd__sdfbbp (work@sky130_fd_sc_hd__sdfbbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfbbp.functional.v, line:38:1, endln:73:10 |vpiDefName:work@not |vpiName:not2 |vpiFullName:work@sky130_fd_sc_hd__sdfbbp.not2 @@ -29923,7 +29923,7 @@ design: (work@sky130_fd_sc_hd__sdfrtp) |vpiSize:3 |STRING:? 1 1 : 1 |uhdmallModules: -\_module: work@sky130_fd_sc_hd__sdfrtp (work@sky130_fd_sc_hd__sdfrtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfrtp.functional.v, line:38:1, endln:66:10 +\_module_inst: work@sky130_fd_sc_hd__sdfrtp (work@sky130_fd_sc_hd__sdfrtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfrtp.functional.v, line:38:1, endln:66:10 |vpiParent: \_design: (work@sky130_fd_sc_hd__sdfrtp) |vpiFullName:work@sky130_fd_sc_hd__sdfrtp @@ -29931,64 +29931,64 @@ design: (work@sky130_fd_sc_hd__sdfrtp) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__sdfrtp.buf_Q), line:56:10, endln:56:15 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfrtp (work@sky130_fd_sc_hd__sdfrtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfrtp.functional.v, line:38:1, endln:66:10 + \_module_inst: work@sky130_fd_sc_hd__sdfrtp (work@sky130_fd_sc_hd__sdfrtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfrtp.functional.v, line:38:1, endln:66:10 |vpiName:buf_Q |vpiFullName:work@sky130_fd_sc_hd__sdfrtp.buf_Q |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__sdfrtp.RESET), line:57:10, endln:57:15 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfrtp (work@sky130_fd_sc_hd__sdfrtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfrtp.functional.v, line:38:1, endln:66:10 + \_module_inst: work@sky130_fd_sc_hd__sdfrtp (work@sky130_fd_sc_hd__sdfrtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfrtp.functional.v, line:38:1, endln:66:10 |vpiName:RESET |vpiFullName:work@sky130_fd_sc_hd__sdfrtp.RESET |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__sdfrtp.mux_out), line:58:10, endln:58:17 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfrtp (work@sky130_fd_sc_hd__sdfrtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfrtp.functional.v, line:38:1, endln:66:10 + \_module_inst: work@sky130_fd_sc_hd__sdfrtp (work@sky130_fd_sc_hd__sdfrtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfrtp.functional.v, line:38:1, endln:66:10 |vpiName:mux_out |vpiFullName:work@sky130_fd_sc_hd__sdfrtp.mux_out |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__sdfrtp.Q), line:39:5, endln:39:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfrtp (work@sky130_fd_sc_hd__sdfrtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfrtp.functional.v, line:38:1, endln:66:10 + \_module_inst: work@sky130_fd_sc_hd__sdfrtp (work@sky130_fd_sc_hd__sdfrtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfrtp.functional.v, line:38:1, endln:66:10 |vpiName:Q |vpiFullName:work@sky130_fd_sc_hd__sdfrtp.Q |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__sdfrtp.CLK), line:40:5, endln:40:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfrtp (work@sky130_fd_sc_hd__sdfrtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfrtp.functional.v, line:38:1, endln:66:10 + \_module_inst: work@sky130_fd_sc_hd__sdfrtp (work@sky130_fd_sc_hd__sdfrtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfrtp.functional.v, line:38:1, endln:66:10 |vpiName:CLK |vpiFullName:work@sky130_fd_sc_hd__sdfrtp.CLK |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__sdfrtp.D), line:41:5, endln:41:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfrtp (work@sky130_fd_sc_hd__sdfrtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfrtp.functional.v, line:38:1, endln:66:10 + \_module_inst: work@sky130_fd_sc_hd__sdfrtp (work@sky130_fd_sc_hd__sdfrtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfrtp.functional.v, line:38:1, endln:66:10 |vpiName:D |vpiFullName:work@sky130_fd_sc_hd__sdfrtp.D |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__sdfrtp.SCD), line:42:5, endln:42:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfrtp (work@sky130_fd_sc_hd__sdfrtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfrtp.functional.v, line:38:1, endln:66:10 + \_module_inst: work@sky130_fd_sc_hd__sdfrtp (work@sky130_fd_sc_hd__sdfrtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfrtp.functional.v, line:38:1, endln:66:10 |vpiName:SCD |vpiFullName:work@sky130_fd_sc_hd__sdfrtp.SCD |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__sdfrtp.SCE), line:43:5, endln:43:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfrtp (work@sky130_fd_sc_hd__sdfrtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfrtp.functional.v, line:38:1, endln:66:10 + \_module_inst: work@sky130_fd_sc_hd__sdfrtp (work@sky130_fd_sc_hd__sdfrtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfrtp.functional.v, line:38:1, endln:66:10 |vpiName:SCE |vpiFullName:work@sky130_fd_sc_hd__sdfrtp.SCE |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__sdfrtp.RESET_B), line:44:5, endln:44:12 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfrtp (work@sky130_fd_sc_hd__sdfrtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfrtp.functional.v, line:38:1, endln:66:10 + \_module_inst: work@sky130_fd_sc_hd__sdfrtp (work@sky130_fd_sc_hd__sdfrtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfrtp.functional.v, line:38:1, endln:66:10 |vpiName:RESET_B |vpiFullName:work@sky130_fd_sc_hd__sdfrtp.RESET_B |vpiPort: \_port: (Q), line:39:5, endln:39:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfrtp (work@sky130_fd_sc_hd__sdfrtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfrtp.functional.v, line:38:1, endln:66:10 + \_module_inst: work@sky130_fd_sc_hd__sdfrtp (work@sky130_fd_sc_hd__sdfrtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfrtp.functional.v, line:38:1, endln:66:10 |vpiName:Q |vpiDirection:2 |vpiLowConn: @@ -30000,7 +30000,7 @@ design: (work@sky130_fd_sc_hd__sdfrtp) |vpiPort: \_port: (CLK), line:40:5, endln:40:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfrtp (work@sky130_fd_sc_hd__sdfrtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfrtp.functional.v, line:38:1, endln:66:10 + \_module_inst: work@sky130_fd_sc_hd__sdfrtp (work@sky130_fd_sc_hd__sdfrtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfrtp.functional.v, line:38:1, endln:66:10 |vpiName:CLK |vpiDirection:1 |vpiLowConn: @@ -30012,7 +30012,7 @@ design: (work@sky130_fd_sc_hd__sdfrtp) |vpiPort: \_port: (D), line:41:5, endln:41:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfrtp (work@sky130_fd_sc_hd__sdfrtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfrtp.functional.v, line:38:1, endln:66:10 + \_module_inst: work@sky130_fd_sc_hd__sdfrtp (work@sky130_fd_sc_hd__sdfrtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfrtp.functional.v, line:38:1, endln:66:10 |vpiName:D |vpiDirection:1 |vpiLowConn: @@ -30024,7 +30024,7 @@ design: (work@sky130_fd_sc_hd__sdfrtp) |vpiPort: \_port: (SCD), line:42:5, endln:42:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfrtp (work@sky130_fd_sc_hd__sdfrtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfrtp.functional.v, line:38:1, endln:66:10 + \_module_inst: work@sky130_fd_sc_hd__sdfrtp (work@sky130_fd_sc_hd__sdfrtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfrtp.functional.v, line:38:1, endln:66:10 |vpiName:SCD |vpiDirection:1 |vpiLowConn: @@ -30036,7 +30036,7 @@ design: (work@sky130_fd_sc_hd__sdfrtp) |vpiPort: \_port: (SCE), line:43:5, endln:43:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfrtp (work@sky130_fd_sc_hd__sdfrtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfrtp.functional.v, line:38:1, endln:66:10 + \_module_inst: work@sky130_fd_sc_hd__sdfrtp (work@sky130_fd_sc_hd__sdfrtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfrtp.functional.v, line:38:1, endln:66:10 |vpiName:SCE |vpiDirection:1 |vpiLowConn: @@ -30048,7 +30048,7 @@ design: (work@sky130_fd_sc_hd__sdfrtp) |vpiPort: \_port: (RESET_B), line:44:5, endln:44:12 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfrtp (work@sky130_fd_sc_hd__sdfrtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfrtp.functional.v, line:38:1, endln:66:10 + \_module_inst: work@sky130_fd_sc_hd__sdfrtp (work@sky130_fd_sc_hd__sdfrtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfrtp.functional.v, line:38:1, endln:66:10 |vpiName:RESET_B |vpiDirection:1 |vpiLowConn: @@ -30058,14 +30058,14 @@ design: (work@sky130_fd_sc_hd__sdfrtp) |vpiTypedef: \_logic_typespec: , line:53:12, endln:53:12 |uhdmtopModules: -\_module: work@sky130_fd_sc_hd__sdfrtp (work@sky130_fd_sc_hd__sdfrtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfrtp.functional.v, line:38:1, endln:66:10 +\_module_inst: work@sky130_fd_sc_hd__sdfrtp (work@sky130_fd_sc_hd__sdfrtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfrtp.functional.v, line:38:1, endln:66:10 |vpiName:work@sky130_fd_sc_hd__sdfrtp |vpiDefName:work@sky130_fd_sc_hd__sdfrtp |vpiTop:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__sdfrtp.buf_Q), line:56:10, endln:56:15 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfrtp (work@sky130_fd_sc_hd__sdfrtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfrtp.functional.v, line:38:1, endln:66:10 + \_module_inst: work@sky130_fd_sc_hd__sdfrtp (work@sky130_fd_sc_hd__sdfrtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfrtp.functional.v, line:38:1, endln:66:10 |vpiTypespec: \_logic_typespec: , line:56:5, endln:56:9 |vpiName:buf_Q @@ -30074,7 +30074,7 @@ design: (work@sky130_fd_sc_hd__sdfrtp) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__sdfrtp.RESET), line:57:10, endln:57:15 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfrtp (work@sky130_fd_sc_hd__sdfrtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfrtp.functional.v, line:38:1, endln:66:10 + \_module_inst: work@sky130_fd_sc_hd__sdfrtp (work@sky130_fd_sc_hd__sdfrtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfrtp.functional.v, line:38:1, endln:66:10 |vpiTypespec: \_logic_typespec: , line:57:5, endln:57:9 |vpiName:RESET @@ -30083,7 +30083,7 @@ design: (work@sky130_fd_sc_hd__sdfrtp) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__sdfrtp.mux_out), line:58:10, endln:58:17 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfrtp (work@sky130_fd_sc_hd__sdfrtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfrtp.functional.v, line:38:1, endln:66:10 + \_module_inst: work@sky130_fd_sc_hd__sdfrtp (work@sky130_fd_sc_hd__sdfrtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfrtp.functional.v, line:38:1, endln:66:10 |vpiTypespec: \_logic_typespec: , line:58:5, endln:58:9 |vpiName:mux_out @@ -30092,7 +30092,7 @@ design: (work@sky130_fd_sc_hd__sdfrtp) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__sdfrtp.Q), line:39:5, endln:39:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfrtp (work@sky130_fd_sc_hd__sdfrtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfrtp.functional.v, line:38:1, endln:66:10 + \_module_inst: work@sky130_fd_sc_hd__sdfrtp (work@sky130_fd_sc_hd__sdfrtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfrtp.functional.v, line:38:1, endln:66:10 |vpiTypespec: \_logic_typespec: , line:48:12, endln:48:12 |vpiName:Q @@ -30100,7 +30100,7 @@ design: (work@sky130_fd_sc_hd__sdfrtp) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__sdfrtp.CLK), line:40:5, endln:40:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfrtp (work@sky130_fd_sc_hd__sdfrtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfrtp.functional.v, line:38:1, endln:66:10 + \_module_inst: work@sky130_fd_sc_hd__sdfrtp (work@sky130_fd_sc_hd__sdfrtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfrtp.functional.v, line:38:1, endln:66:10 |vpiTypespec: \_logic_typespec: , line:49:12, endln:49:12 |vpiName:CLK @@ -30108,7 +30108,7 @@ design: (work@sky130_fd_sc_hd__sdfrtp) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__sdfrtp.D), line:41:5, endln:41:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfrtp (work@sky130_fd_sc_hd__sdfrtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfrtp.functional.v, line:38:1, endln:66:10 + \_module_inst: work@sky130_fd_sc_hd__sdfrtp (work@sky130_fd_sc_hd__sdfrtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfrtp.functional.v, line:38:1, endln:66:10 |vpiTypespec: \_logic_typespec: , line:50:12, endln:50:12 |vpiName:D @@ -30116,7 +30116,7 @@ design: (work@sky130_fd_sc_hd__sdfrtp) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__sdfrtp.SCD), line:42:5, endln:42:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfrtp (work@sky130_fd_sc_hd__sdfrtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfrtp.functional.v, line:38:1, endln:66:10 + \_module_inst: work@sky130_fd_sc_hd__sdfrtp (work@sky130_fd_sc_hd__sdfrtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfrtp.functional.v, line:38:1, endln:66:10 |vpiTypespec: \_logic_typespec: , line:51:12, endln:51:12 |vpiName:SCD @@ -30124,7 +30124,7 @@ design: (work@sky130_fd_sc_hd__sdfrtp) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__sdfrtp.SCE), line:43:5, endln:43:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfrtp (work@sky130_fd_sc_hd__sdfrtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfrtp.functional.v, line:38:1, endln:66:10 + \_module_inst: work@sky130_fd_sc_hd__sdfrtp (work@sky130_fd_sc_hd__sdfrtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfrtp.functional.v, line:38:1, endln:66:10 |vpiTypespec: \_logic_typespec: , line:52:12, endln:52:12 |vpiName:SCE @@ -30132,7 +30132,7 @@ design: (work@sky130_fd_sc_hd__sdfrtp) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__sdfrtp.RESET_B), line:44:5, endln:44:12 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfrtp (work@sky130_fd_sc_hd__sdfrtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfrtp.functional.v, line:38:1, endln:66:10 + \_module_inst: work@sky130_fd_sc_hd__sdfrtp (work@sky130_fd_sc_hd__sdfrtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfrtp.functional.v, line:38:1, endln:66:10 |vpiTypespec: \_logic_typespec: , line:53:12, endln:53:12 |vpiName:RESET_B @@ -30141,7 +30141,7 @@ design: (work@sky130_fd_sc_hd__sdfrtp) |vpiPort: \_port: (Q), line:39:5, endln:39:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfrtp (work@sky130_fd_sc_hd__sdfrtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfrtp.functional.v, line:38:1, endln:66:10 + \_module_inst: work@sky130_fd_sc_hd__sdfrtp (work@sky130_fd_sc_hd__sdfrtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfrtp.functional.v, line:38:1, endln:66:10 |vpiName:Q |vpiDirection:2 |vpiLowConn: @@ -30155,7 +30155,7 @@ design: (work@sky130_fd_sc_hd__sdfrtp) |vpiPort: \_port: (CLK), line:40:5, endln:40:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfrtp (work@sky130_fd_sc_hd__sdfrtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfrtp.functional.v, line:38:1, endln:66:10 + \_module_inst: work@sky130_fd_sc_hd__sdfrtp (work@sky130_fd_sc_hd__sdfrtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfrtp.functional.v, line:38:1, endln:66:10 |vpiName:CLK |vpiDirection:1 |vpiLowConn: @@ -30169,7 +30169,7 @@ design: (work@sky130_fd_sc_hd__sdfrtp) |vpiPort: \_port: (D), line:41:5, endln:41:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfrtp (work@sky130_fd_sc_hd__sdfrtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfrtp.functional.v, line:38:1, endln:66:10 + \_module_inst: work@sky130_fd_sc_hd__sdfrtp (work@sky130_fd_sc_hd__sdfrtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfrtp.functional.v, line:38:1, endln:66:10 |vpiName:D |vpiDirection:1 |vpiLowConn: @@ -30183,7 +30183,7 @@ design: (work@sky130_fd_sc_hd__sdfrtp) |vpiPort: \_port: (SCD), line:42:5, endln:42:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfrtp (work@sky130_fd_sc_hd__sdfrtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfrtp.functional.v, line:38:1, endln:66:10 + \_module_inst: work@sky130_fd_sc_hd__sdfrtp (work@sky130_fd_sc_hd__sdfrtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfrtp.functional.v, line:38:1, endln:66:10 |vpiName:SCD |vpiDirection:1 |vpiLowConn: @@ -30197,7 +30197,7 @@ design: (work@sky130_fd_sc_hd__sdfrtp) |vpiPort: \_port: (SCE), line:43:5, endln:43:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfrtp (work@sky130_fd_sc_hd__sdfrtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfrtp.functional.v, line:38:1, endln:66:10 + \_module_inst: work@sky130_fd_sc_hd__sdfrtp (work@sky130_fd_sc_hd__sdfrtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfrtp.functional.v, line:38:1, endln:66:10 |vpiName:SCE |vpiDirection:1 |vpiLowConn: @@ -30211,7 +30211,7 @@ design: (work@sky130_fd_sc_hd__sdfrtp) |vpiPort: \_port: (RESET_B), line:44:5, endln:44:12 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfrtp (work@sky130_fd_sc_hd__sdfrtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfrtp.functional.v, line:38:1, endln:66:10 + \_module_inst: work@sky130_fd_sc_hd__sdfrtp (work@sky130_fd_sc_hd__sdfrtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfrtp.functional.v, line:38:1, endln:66:10 |vpiName:RESET_B |vpiDirection:1 |vpiLowConn: @@ -30225,7 +30225,7 @@ design: (work@sky130_fd_sc_hd__sdfrtp) |vpiPrimitive: \_gate: work@not (work@sky130_fd_sc_hd__sdfrtp.not0), line:61:47, endln:61:87 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfrtp (work@sky130_fd_sc_hd__sdfrtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfrtp.functional.v, line:38:1, endln:66:10 + \_module_inst: work@sky130_fd_sc_hd__sdfrtp (work@sky130_fd_sc_hd__sdfrtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfrtp.functional.v, line:38:1, endln:66:10 |vpiDefName:work@not |vpiName:not0 |vpiFullName:work@sky130_fd_sc_hd__sdfrtp.not0 @@ -30260,7 +30260,7 @@ design: (work@sky130_fd_sc_hd__sdfrtp) |vpiPrimitive: \_udp: work@sky130_fd_sc_hd__udp_mux_2to1 (work@sky130_fd_sc_hd__sdfrtp.mux_2to10), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfrtp.functional.v, line:62:5, endln:62:88 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfrtp (work@sky130_fd_sc_hd__sdfrtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfrtp.functional.v, line:38:1, endln:66:10 + \_module_inst: work@sky130_fd_sc_hd__sdfrtp (work@sky130_fd_sc_hd__sdfrtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfrtp.functional.v, line:38:1, endln:66:10 |vpiDefName:work@sky130_fd_sc_hd__udp_mux_2to1 |vpiName:mux_2to10 |vpiFullName:work@sky130_fd_sc_hd__sdfrtp.mux_2to10 @@ -30269,7 +30269,7 @@ design: (work@sky130_fd_sc_hd__sdfrtp) |vpiPrimitive: \_udp: work@sky130_fd_sc_hd__udp_dff$PR (work@sky130_fd_sc_hd__sdfrtp.dff0), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfrtp.functional.v, line:63:5, endln:63:77 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfrtp (work@sky130_fd_sc_hd__sdfrtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfrtp.functional.v, line:38:1, endln:66:10 + \_module_inst: work@sky130_fd_sc_hd__sdfrtp (work@sky130_fd_sc_hd__sdfrtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfrtp.functional.v, line:38:1, endln:66:10 |vpiDefName:work@sky130_fd_sc_hd__udp_dff$PR |vpiName:dff0 |vpiFullName:work@sky130_fd_sc_hd__sdfrtp.dff0 @@ -30278,7 +30278,7 @@ design: (work@sky130_fd_sc_hd__sdfrtp) |vpiPrimitive: \_gate: work@buf (work@sky130_fd_sc_hd__sdfrtp.buf0), line:64:47, endln:64:87 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfrtp (work@sky130_fd_sc_hd__sdfrtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfrtp.functional.v, line:38:1, endln:66:10 + \_module_inst: work@sky130_fd_sc_hd__sdfrtp (work@sky130_fd_sc_hd__sdfrtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfrtp.functional.v, line:38:1, endln:66:10 |vpiDefName:work@buf |vpiName:buf0 |vpiFullName:work@sky130_fd_sc_hd__sdfrtp.buf0 @@ -30321,13 +30321,13 @@ Processing: -cd cells/cells -DUNIT_DELAY -writepp -parse -nocache -nobuiltin -no design: (work@sky130_fd_sc_hd__tap) |vpiName:work@sky130_fd_sc_hd__tap |uhdmallModules: -\_module: work@sky130_fd_sc_hd__tap (work@sky130_fd_sc_hd__tap), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__tap.functional.v, line:33:1, endln:35:10 +\_module_inst: work@sky130_fd_sc_hd__tap (work@sky130_fd_sc_hd__tap), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__tap.functional.v, line:33:1, endln:35:10 |vpiParent: \_design: (work@sky130_fd_sc_hd__tap) |vpiFullName:work@sky130_fd_sc_hd__tap |vpiDefName:work@sky130_fd_sc_hd__tap |uhdmtopModules: -\_module: work@sky130_fd_sc_hd__tap (work@sky130_fd_sc_hd__tap), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__tap.functional.v, line:33:1, endln:35:10 +\_module_inst: work@sky130_fd_sc_hd__tap (work@sky130_fd_sc_hd__tap), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__tap.functional.v, line:33:1, endln:35:10 |vpiName:work@sky130_fd_sc_hd__tap |vpiDefName:work@sky130_fd_sc_hd__tap |vpiTop:1 @@ -30557,7 +30557,7 @@ design: (work@sky130_fd_sc_hd__sdfstp) |vpiSize:3 |STRING:? 1 1 : 1 |uhdmallModules: -\_module: work@sky130_fd_sc_hd__sdfstp (work@sky130_fd_sc_hd__sdfstp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfstp.functional.v, line:38:1, endln:66:10 +\_module_inst: work@sky130_fd_sc_hd__sdfstp (work@sky130_fd_sc_hd__sdfstp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfstp.functional.v, line:38:1, endln:66:10 |vpiParent: \_design: (work@sky130_fd_sc_hd__sdfstp) |vpiFullName:work@sky130_fd_sc_hd__sdfstp @@ -30565,64 +30565,64 @@ design: (work@sky130_fd_sc_hd__sdfstp) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__sdfstp.buf_Q), line:56:10, endln:56:15 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfstp (work@sky130_fd_sc_hd__sdfstp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfstp.functional.v, line:38:1, endln:66:10 + \_module_inst: work@sky130_fd_sc_hd__sdfstp (work@sky130_fd_sc_hd__sdfstp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfstp.functional.v, line:38:1, endln:66:10 |vpiName:buf_Q |vpiFullName:work@sky130_fd_sc_hd__sdfstp.buf_Q |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__sdfstp.SET), line:57:10, endln:57:13 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfstp (work@sky130_fd_sc_hd__sdfstp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfstp.functional.v, line:38:1, endln:66:10 + \_module_inst: work@sky130_fd_sc_hd__sdfstp (work@sky130_fd_sc_hd__sdfstp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfstp.functional.v, line:38:1, endln:66:10 |vpiName:SET |vpiFullName:work@sky130_fd_sc_hd__sdfstp.SET |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__sdfstp.mux_out), line:58:10, endln:58:17 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfstp (work@sky130_fd_sc_hd__sdfstp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfstp.functional.v, line:38:1, endln:66:10 + \_module_inst: work@sky130_fd_sc_hd__sdfstp (work@sky130_fd_sc_hd__sdfstp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfstp.functional.v, line:38:1, endln:66:10 |vpiName:mux_out |vpiFullName:work@sky130_fd_sc_hd__sdfstp.mux_out |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__sdfstp.Q), line:39:5, endln:39:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfstp (work@sky130_fd_sc_hd__sdfstp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfstp.functional.v, line:38:1, endln:66:10 + \_module_inst: work@sky130_fd_sc_hd__sdfstp (work@sky130_fd_sc_hd__sdfstp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfstp.functional.v, line:38:1, endln:66:10 |vpiName:Q |vpiFullName:work@sky130_fd_sc_hd__sdfstp.Q |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__sdfstp.CLK), line:40:5, endln:40:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfstp (work@sky130_fd_sc_hd__sdfstp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfstp.functional.v, line:38:1, endln:66:10 + \_module_inst: work@sky130_fd_sc_hd__sdfstp (work@sky130_fd_sc_hd__sdfstp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfstp.functional.v, line:38:1, endln:66:10 |vpiName:CLK |vpiFullName:work@sky130_fd_sc_hd__sdfstp.CLK |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__sdfstp.D), line:41:5, endln:41:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfstp (work@sky130_fd_sc_hd__sdfstp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfstp.functional.v, line:38:1, endln:66:10 + \_module_inst: work@sky130_fd_sc_hd__sdfstp (work@sky130_fd_sc_hd__sdfstp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfstp.functional.v, line:38:1, endln:66:10 |vpiName:D |vpiFullName:work@sky130_fd_sc_hd__sdfstp.D |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__sdfstp.SCD), line:42:5, endln:42:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfstp (work@sky130_fd_sc_hd__sdfstp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfstp.functional.v, line:38:1, endln:66:10 + \_module_inst: work@sky130_fd_sc_hd__sdfstp (work@sky130_fd_sc_hd__sdfstp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfstp.functional.v, line:38:1, endln:66:10 |vpiName:SCD |vpiFullName:work@sky130_fd_sc_hd__sdfstp.SCD |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__sdfstp.SCE), line:43:5, endln:43:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfstp (work@sky130_fd_sc_hd__sdfstp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfstp.functional.v, line:38:1, endln:66:10 + \_module_inst: work@sky130_fd_sc_hd__sdfstp (work@sky130_fd_sc_hd__sdfstp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfstp.functional.v, line:38:1, endln:66:10 |vpiName:SCE |vpiFullName:work@sky130_fd_sc_hd__sdfstp.SCE |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__sdfstp.SET_B), line:44:5, endln:44:10 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfstp (work@sky130_fd_sc_hd__sdfstp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfstp.functional.v, line:38:1, endln:66:10 + \_module_inst: work@sky130_fd_sc_hd__sdfstp (work@sky130_fd_sc_hd__sdfstp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfstp.functional.v, line:38:1, endln:66:10 |vpiName:SET_B |vpiFullName:work@sky130_fd_sc_hd__sdfstp.SET_B |vpiPort: \_port: (Q), line:39:5, endln:39:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfstp (work@sky130_fd_sc_hd__sdfstp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfstp.functional.v, line:38:1, endln:66:10 + \_module_inst: work@sky130_fd_sc_hd__sdfstp (work@sky130_fd_sc_hd__sdfstp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfstp.functional.v, line:38:1, endln:66:10 |vpiName:Q |vpiDirection:2 |vpiLowConn: @@ -30634,7 +30634,7 @@ design: (work@sky130_fd_sc_hd__sdfstp) |vpiPort: \_port: (CLK), line:40:5, endln:40:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfstp (work@sky130_fd_sc_hd__sdfstp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfstp.functional.v, line:38:1, endln:66:10 + \_module_inst: work@sky130_fd_sc_hd__sdfstp (work@sky130_fd_sc_hd__sdfstp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfstp.functional.v, line:38:1, endln:66:10 |vpiName:CLK |vpiDirection:1 |vpiLowConn: @@ -30646,7 +30646,7 @@ design: (work@sky130_fd_sc_hd__sdfstp) |vpiPort: \_port: (D), line:41:5, endln:41:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfstp (work@sky130_fd_sc_hd__sdfstp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfstp.functional.v, line:38:1, endln:66:10 + \_module_inst: work@sky130_fd_sc_hd__sdfstp (work@sky130_fd_sc_hd__sdfstp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfstp.functional.v, line:38:1, endln:66:10 |vpiName:D |vpiDirection:1 |vpiLowConn: @@ -30658,7 +30658,7 @@ design: (work@sky130_fd_sc_hd__sdfstp) |vpiPort: \_port: (SCD), line:42:5, endln:42:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfstp (work@sky130_fd_sc_hd__sdfstp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfstp.functional.v, line:38:1, endln:66:10 + \_module_inst: work@sky130_fd_sc_hd__sdfstp (work@sky130_fd_sc_hd__sdfstp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfstp.functional.v, line:38:1, endln:66:10 |vpiName:SCD |vpiDirection:1 |vpiLowConn: @@ -30670,7 +30670,7 @@ design: (work@sky130_fd_sc_hd__sdfstp) |vpiPort: \_port: (SCE), line:43:5, endln:43:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfstp (work@sky130_fd_sc_hd__sdfstp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfstp.functional.v, line:38:1, endln:66:10 + \_module_inst: work@sky130_fd_sc_hd__sdfstp (work@sky130_fd_sc_hd__sdfstp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfstp.functional.v, line:38:1, endln:66:10 |vpiName:SCE |vpiDirection:1 |vpiLowConn: @@ -30682,7 +30682,7 @@ design: (work@sky130_fd_sc_hd__sdfstp) |vpiPort: \_port: (SET_B), line:44:5, endln:44:10 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfstp (work@sky130_fd_sc_hd__sdfstp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfstp.functional.v, line:38:1, endln:66:10 + \_module_inst: work@sky130_fd_sc_hd__sdfstp (work@sky130_fd_sc_hd__sdfstp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfstp.functional.v, line:38:1, endln:66:10 |vpiName:SET_B |vpiDirection:1 |vpiLowConn: @@ -30692,14 +30692,14 @@ design: (work@sky130_fd_sc_hd__sdfstp) |vpiTypedef: \_logic_typespec: , line:53:12, endln:53:12 |uhdmtopModules: -\_module: work@sky130_fd_sc_hd__sdfstp (work@sky130_fd_sc_hd__sdfstp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfstp.functional.v, line:38:1, endln:66:10 +\_module_inst: work@sky130_fd_sc_hd__sdfstp (work@sky130_fd_sc_hd__sdfstp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfstp.functional.v, line:38:1, endln:66:10 |vpiName:work@sky130_fd_sc_hd__sdfstp |vpiDefName:work@sky130_fd_sc_hd__sdfstp |vpiTop:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__sdfstp.buf_Q), line:56:10, endln:56:15 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfstp (work@sky130_fd_sc_hd__sdfstp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfstp.functional.v, line:38:1, endln:66:10 + \_module_inst: work@sky130_fd_sc_hd__sdfstp (work@sky130_fd_sc_hd__sdfstp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfstp.functional.v, line:38:1, endln:66:10 |vpiTypespec: \_logic_typespec: , line:56:5, endln:56:9 |vpiName:buf_Q @@ -30708,7 +30708,7 @@ design: (work@sky130_fd_sc_hd__sdfstp) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__sdfstp.SET), line:57:10, endln:57:13 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfstp (work@sky130_fd_sc_hd__sdfstp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfstp.functional.v, line:38:1, endln:66:10 + \_module_inst: work@sky130_fd_sc_hd__sdfstp (work@sky130_fd_sc_hd__sdfstp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfstp.functional.v, line:38:1, endln:66:10 |vpiTypespec: \_logic_typespec: , line:57:5, endln:57:9 |vpiName:SET @@ -30717,7 +30717,7 @@ design: (work@sky130_fd_sc_hd__sdfstp) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__sdfstp.mux_out), line:58:10, endln:58:17 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfstp (work@sky130_fd_sc_hd__sdfstp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfstp.functional.v, line:38:1, endln:66:10 + \_module_inst: work@sky130_fd_sc_hd__sdfstp (work@sky130_fd_sc_hd__sdfstp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfstp.functional.v, line:38:1, endln:66:10 |vpiTypespec: \_logic_typespec: , line:58:5, endln:58:9 |vpiName:mux_out @@ -30726,7 +30726,7 @@ design: (work@sky130_fd_sc_hd__sdfstp) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__sdfstp.Q), line:39:5, endln:39:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfstp (work@sky130_fd_sc_hd__sdfstp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfstp.functional.v, line:38:1, endln:66:10 + \_module_inst: work@sky130_fd_sc_hd__sdfstp (work@sky130_fd_sc_hd__sdfstp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfstp.functional.v, line:38:1, endln:66:10 |vpiTypespec: \_logic_typespec: , line:48:12, endln:48:12 |vpiName:Q @@ -30734,7 +30734,7 @@ design: (work@sky130_fd_sc_hd__sdfstp) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__sdfstp.CLK), line:40:5, endln:40:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfstp (work@sky130_fd_sc_hd__sdfstp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfstp.functional.v, line:38:1, endln:66:10 + \_module_inst: work@sky130_fd_sc_hd__sdfstp (work@sky130_fd_sc_hd__sdfstp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfstp.functional.v, line:38:1, endln:66:10 |vpiTypespec: \_logic_typespec: , line:49:12, endln:49:12 |vpiName:CLK @@ -30742,7 +30742,7 @@ design: (work@sky130_fd_sc_hd__sdfstp) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__sdfstp.D), line:41:5, endln:41:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfstp (work@sky130_fd_sc_hd__sdfstp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfstp.functional.v, line:38:1, endln:66:10 + \_module_inst: work@sky130_fd_sc_hd__sdfstp (work@sky130_fd_sc_hd__sdfstp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfstp.functional.v, line:38:1, endln:66:10 |vpiTypespec: \_logic_typespec: , line:50:12, endln:50:12 |vpiName:D @@ -30750,7 +30750,7 @@ design: (work@sky130_fd_sc_hd__sdfstp) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__sdfstp.SCD), line:42:5, endln:42:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfstp (work@sky130_fd_sc_hd__sdfstp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfstp.functional.v, line:38:1, endln:66:10 + \_module_inst: work@sky130_fd_sc_hd__sdfstp (work@sky130_fd_sc_hd__sdfstp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfstp.functional.v, line:38:1, endln:66:10 |vpiTypespec: \_logic_typespec: , line:51:12, endln:51:12 |vpiName:SCD @@ -30758,7 +30758,7 @@ design: (work@sky130_fd_sc_hd__sdfstp) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__sdfstp.SCE), line:43:5, endln:43:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfstp (work@sky130_fd_sc_hd__sdfstp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfstp.functional.v, line:38:1, endln:66:10 + \_module_inst: work@sky130_fd_sc_hd__sdfstp (work@sky130_fd_sc_hd__sdfstp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfstp.functional.v, line:38:1, endln:66:10 |vpiTypespec: \_logic_typespec: , line:52:12, endln:52:12 |vpiName:SCE @@ -30766,7 +30766,7 @@ design: (work@sky130_fd_sc_hd__sdfstp) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__sdfstp.SET_B), line:44:5, endln:44:10 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfstp (work@sky130_fd_sc_hd__sdfstp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfstp.functional.v, line:38:1, endln:66:10 + \_module_inst: work@sky130_fd_sc_hd__sdfstp (work@sky130_fd_sc_hd__sdfstp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfstp.functional.v, line:38:1, endln:66:10 |vpiTypespec: \_logic_typespec: , line:53:12, endln:53:12 |vpiName:SET_B @@ -30775,7 +30775,7 @@ design: (work@sky130_fd_sc_hd__sdfstp) |vpiPort: \_port: (Q), line:39:5, endln:39:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfstp (work@sky130_fd_sc_hd__sdfstp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfstp.functional.v, line:38:1, endln:66:10 + \_module_inst: work@sky130_fd_sc_hd__sdfstp (work@sky130_fd_sc_hd__sdfstp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfstp.functional.v, line:38:1, endln:66:10 |vpiName:Q |vpiDirection:2 |vpiLowConn: @@ -30789,7 +30789,7 @@ design: (work@sky130_fd_sc_hd__sdfstp) |vpiPort: \_port: (CLK), line:40:5, endln:40:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfstp (work@sky130_fd_sc_hd__sdfstp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfstp.functional.v, line:38:1, endln:66:10 + \_module_inst: work@sky130_fd_sc_hd__sdfstp (work@sky130_fd_sc_hd__sdfstp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfstp.functional.v, line:38:1, endln:66:10 |vpiName:CLK |vpiDirection:1 |vpiLowConn: @@ -30803,7 +30803,7 @@ design: (work@sky130_fd_sc_hd__sdfstp) |vpiPort: \_port: (D), line:41:5, endln:41:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfstp (work@sky130_fd_sc_hd__sdfstp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfstp.functional.v, line:38:1, endln:66:10 + \_module_inst: work@sky130_fd_sc_hd__sdfstp (work@sky130_fd_sc_hd__sdfstp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfstp.functional.v, line:38:1, endln:66:10 |vpiName:D |vpiDirection:1 |vpiLowConn: @@ -30817,7 +30817,7 @@ design: (work@sky130_fd_sc_hd__sdfstp) |vpiPort: \_port: (SCD), line:42:5, endln:42:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfstp (work@sky130_fd_sc_hd__sdfstp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfstp.functional.v, line:38:1, endln:66:10 + \_module_inst: work@sky130_fd_sc_hd__sdfstp (work@sky130_fd_sc_hd__sdfstp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfstp.functional.v, line:38:1, endln:66:10 |vpiName:SCD |vpiDirection:1 |vpiLowConn: @@ -30831,7 +30831,7 @@ design: (work@sky130_fd_sc_hd__sdfstp) |vpiPort: \_port: (SCE), line:43:5, endln:43:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfstp (work@sky130_fd_sc_hd__sdfstp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfstp.functional.v, line:38:1, endln:66:10 + \_module_inst: work@sky130_fd_sc_hd__sdfstp (work@sky130_fd_sc_hd__sdfstp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfstp.functional.v, line:38:1, endln:66:10 |vpiName:SCE |vpiDirection:1 |vpiLowConn: @@ -30845,7 +30845,7 @@ design: (work@sky130_fd_sc_hd__sdfstp) |vpiPort: \_port: (SET_B), line:44:5, endln:44:10 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfstp (work@sky130_fd_sc_hd__sdfstp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfstp.functional.v, line:38:1, endln:66:10 + \_module_inst: work@sky130_fd_sc_hd__sdfstp (work@sky130_fd_sc_hd__sdfstp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfstp.functional.v, line:38:1, endln:66:10 |vpiName:SET_B |vpiDirection:1 |vpiLowConn: @@ -30859,7 +30859,7 @@ design: (work@sky130_fd_sc_hd__sdfstp) |vpiPrimitive: \_gate: work@not (work@sky130_fd_sc_hd__sdfstp.not0), line:61:47, endln:61:85 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfstp (work@sky130_fd_sc_hd__sdfstp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfstp.functional.v, line:38:1, endln:66:10 + \_module_inst: work@sky130_fd_sc_hd__sdfstp (work@sky130_fd_sc_hd__sdfstp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfstp.functional.v, line:38:1, endln:66:10 |vpiDefName:work@not |vpiName:not0 |vpiFullName:work@sky130_fd_sc_hd__sdfstp.not0 @@ -30894,7 +30894,7 @@ design: (work@sky130_fd_sc_hd__sdfstp) |vpiPrimitive: \_udp: work@sky130_fd_sc_hd__udp_mux_2to1 (work@sky130_fd_sc_hd__sdfstp.mux_2to10), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfstp.functional.v, line:62:5, endln:62:86 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfstp (work@sky130_fd_sc_hd__sdfstp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfstp.functional.v, line:38:1, endln:66:10 + \_module_inst: work@sky130_fd_sc_hd__sdfstp (work@sky130_fd_sc_hd__sdfstp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfstp.functional.v, line:38:1, endln:66:10 |vpiDefName:work@sky130_fd_sc_hd__udp_mux_2to1 |vpiName:mux_2to10 |vpiFullName:work@sky130_fd_sc_hd__sdfstp.mux_2to10 @@ -30903,7 +30903,7 @@ design: (work@sky130_fd_sc_hd__sdfstp) |vpiPrimitive: \_udp: work@sky130_fd_sc_hd__udp_dff$PS (work@sky130_fd_sc_hd__sdfstp.dff0), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfstp.functional.v, line:63:5, endln:63:75 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfstp (work@sky130_fd_sc_hd__sdfstp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfstp.functional.v, line:38:1, endln:66:10 + \_module_inst: work@sky130_fd_sc_hd__sdfstp (work@sky130_fd_sc_hd__sdfstp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfstp.functional.v, line:38:1, endln:66:10 |vpiDefName:work@sky130_fd_sc_hd__udp_dff$PS |vpiName:dff0 |vpiFullName:work@sky130_fd_sc_hd__sdfstp.dff0 @@ -30912,7 +30912,7 @@ design: (work@sky130_fd_sc_hd__sdfstp) |vpiPrimitive: \_gate: work@buf (work@sky130_fd_sc_hd__sdfstp.buf0), line:64:47, endln:64:85 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfstp (work@sky130_fd_sc_hd__sdfstp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfstp.functional.v, line:38:1, endln:66:10 + \_module_inst: work@sky130_fd_sc_hd__sdfstp (work@sky130_fd_sc_hd__sdfstp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfstp.functional.v, line:38:1, endln:66:10 |vpiDefName:work@buf |vpiName:buf0 |vpiFullName:work@sky130_fd_sc_hd__sdfstp.buf0 @@ -30955,7 +30955,7 @@ Processing: -cd cells/cells -DUNIT_DELAY -writepp -parse -nocache -nobuiltin -no design: (work@sky130_fd_sc_hd__a22o) |vpiName:work@sky130_fd_sc_hd__a22o |uhdmallModules: -\_module: work@sky130_fd_sc_hd__a22o (work@sky130_fd_sc_hd__a22o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a22o.functional.v, line:35:1, endln:61:10 +\_module_inst: work@sky130_fd_sc_hd__a22o (work@sky130_fd_sc_hd__a22o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a22o.functional.v, line:35:1, endln:61:10 |vpiParent: \_design: (work@sky130_fd_sc_hd__a22o) |vpiFullName:work@sky130_fd_sc_hd__a22o @@ -30963,58 +30963,58 @@ design: (work@sky130_fd_sc_hd__a22o) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a22o.and0_out), line:51:10, endln:51:18 |vpiParent: - \_module: work@sky130_fd_sc_hd__a22o (work@sky130_fd_sc_hd__a22o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a22o.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__a22o (work@sky130_fd_sc_hd__a22o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a22o.functional.v, line:35:1, endln:61:10 |vpiName:and0_out |vpiFullName:work@sky130_fd_sc_hd__a22o.and0_out |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a22o.and1_out), line:52:10, endln:52:18 |vpiParent: - \_module: work@sky130_fd_sc_hd__a22o (work@sky130_fd_sc_hd__a22o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a22o.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__a22o (work@sky130_fd_sc_hd__a22o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a22o.functional.v, line:35:1, endln:61:10 |vpiName:and1_out |vpiFullName:work@sky130_fd_sc_hd__a22o.and1_out |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a22o.or0_out_X), line:53:10, endln:53:19 |vpiParent: - \_module: work@sky130_fd_sc_hd__a22o (work@sky130_fd_sc_hd__a22o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a22o.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__a22o (work@sky130_fd_sc_hd__a22o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a22o.functional.v, line:35:1, endln:61:10 |vpiName:or0_out_X |vpiFullName:work@sky130_fd_sc_hd__a22o.or0_out_X |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a22o.X), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__a22o (work@sky130_fd_sc_hd__a22o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a22o.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__a22o (work@sky130_fd_sc_hd__a22o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a22o.functional.v, line:35:1, endln:61:10 |vpiName:X |vpiFullName:work@sky130_fd_sc_hd__a22o.X |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a22o.A1), line:37:5, endln:37:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a22o (work@sky130_fd_sc_hd__a22o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a22o.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__a22o (work@sky130_fd_sc_hd__a22o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a22o.functional.v, line:35:1, endln:61:10 |vpiName:A1 |vpiFullName:work@sky130_fd_sc_hd__a22o.A1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a22o.A2), line:38:5, endln:38:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a22o (work@sky130_fd_sc_hd__a22o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a22o.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__a22o (work@sky130_fd_sc_hd__a22o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a22o.functional.v, line:35:1, endln:61:10 |vpiName:A2 |vpiFullName:work@sky130_fd_sc_hd__a22o.A2 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a22o.B1), line:39:5, endln:39:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a22o (work@sky130_fd_sc_hd__a22o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a22o.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__a22o (work@sky130_fd_sc_hd__a22o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a22o.functional.v, line:35:1, endln:61:10 |vpiName:B1 |vpiFullName:work@sky130_fd_sc_hd__a22o.B1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a22o.B2), line:40:5, endln:40:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a22o (work@sky130_fd_sc_hd__a22o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a22o.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__a22o (work@sky130_fd_sc_hd__a22o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a22o.functional.v, line:35:1, endln:61:10 |vpiName:B2 |vpiFullName:work@sky130_fd_sc_hd__a22o.B2 |vpiPort: \_port: (X), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__a22o (work@sky130_fd_sc_hd__a22o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a22o.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__a22o (work@sky130_fd_sc_hd__a22o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a22o.functional.v, line:35:1, endln:61:10 |vpiName:X |vpiDirection:2 |vpiLowConn: @@ -31026,7 +31026,7 @@ design: (work@sky130_fd_sc_hd__a22o) |vpiPort: \_port: (A1), line:37:5, endln:37:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a22o (work@sky130_fd_sc_hd__a22o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a22o.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__a22o (work@sky130_fd_sc_hd__a22o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a22o.functional.v, line:35:1, endln:61:10 |vpiName:A1 |vpiDirection:1 |vpiLowConn: @@ -31038,7 +31038,7 @@ design: (work@sky130_fd_sc_hd__a22o) |vpiPort: \_port: (A2), line:38:5, endln:38:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a22o (work@sky130_fd_sc_hd__a22o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a22o.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__a22o (work@sky130_fd_sc_hd__a22o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a22o.functional.v, line:35:1, endln:61:10 |vpiName:A2 |vpiDirection:1 |vpiLowConn: @@ -31050,7 +31050,7 @@ design: (work@sky130_fd_sc_hd__a22o) |vpiPort: \_port: (B1), line:39:5, endln:39:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a22o (work@sky130_fd_sc_hd__a22o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a22o.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__a22o (work@sky130_fd_sc_hd__a22o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a22o.functional.v, line:35:1, endln:61:10 |vpiName:B1 |vpiDirection:1 |vpiLowConn: @@ -31062,7 +31062,7 @@ design: (work@sky130_fd_sc_hd__a22o) |vpiPort: \_port: (B2), line:40:5, endln:40:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a22o (work@sky130_fd_sc_hd__a22o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a22o.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__a22o (work@sky130_fd_sc_hd__a22o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a22o.functional.v, line:35:1, endln:61:10 |vpiName:B2 |vpiDirection:1 |vpiLowConn: @@ -31072,14 +31072,14 @@ design: (work@sky130_fd_sc_hd__a22o) |vpiTypedef: \_logic_typespec: , line:48:12, endln:48:12 |uhdmtopModules: -\_module: work@sky130_fd_sc_hd__a22o (work@sky130_fd_sc_hd__a22o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a22o.functional.v, line:35:1, endln:61:10 +\_module_inst: work@sky130_fd_sc_hd__a22o (work@sky130_fd_sc_hd__a22o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a22o.functional.v, line:35:1, endln:61:10 |vpiName:work@sky130_fd_sc_hd__a22o |vpiDefName:work@sky130_fd_sc_hd__a22o |vpiTop:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a22o.and0_out), line:51:10, endln:51:18 |vpiParent: - \_module: work@sky130_fd_sc_hd__a22o (work@sky130_fd_sc_hd__a22o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a22o.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__a22o (work@sky130_fd_sc_hd__a22o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a22o.functional.v, line:35:1, endln:61:10 |vpiTypespec: \_logic_typespec: , line:51:5, endln:51:9 |vpiName:and0_out @@ -31088,7 +31088,7 @@ design: (work@sky130_fd_sc_hd__a22o) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a22o.and1_out), line:52:10, endln:52:18 |vpiParent: - \_module: work@sky130_fd_sc_hd__a22o (work@sky130_fd_sc_hd__a22o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a22o.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__a22o (work@sky130_fd_sc_hd__a22o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a22o.functional.v, line:35:1, endln:61:10 |vpiTypespec: \_logic_typespec: , line:52:5, endln:52:9 |vpiName:and1_out @@ -31097,7 +31097,7 @@ design: (work@sky130_fd_sc_hd__a22o) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a22o.or0_out_X), line:53:10, endln:53:19 |vpiParent: - \_module: work@sky130_fd_sc_hd__a22o (work@sky130_fd_sc_hd__a22o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a22o.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__a22o (work@sky130_fd_sc_hd__a22o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a22o.functional.v, line:35:1, endln:61:10 |vpiTypespec: \_logic_typespec: , line:53:5, endln:53:9 |vpiName:or0_out_X @@ -31106,7 +31106,7 @@ design: (work@sky130_fd_sc_hd__a22o) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a22o.X), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__a22o (work@sky130_fd_sc_hd__a22o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a22o.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__a22o (work@sky130_fd_sc_hd__a22o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a22o.functional.v, line:35:1, endln:61:10 |vpiTypespec: \_logic_typespec: , line:44:12, endln:44:12 |vpiName:X @@ -31114,7 +31114,7 @@ design: (work@sky130_fd_sc_hd__a22o) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a22o.A1), line:37:5, endln:37:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a22o (work@sky130_fd_sc_hd__a22o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a22o.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__a22o (work@sky130_fd_sc_hd__a22o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a22o.functional.v, line:35:1, endln:61:10 |vpiTypespec: \_logic_typespec: , line:45:12, endln:45:12 |vpiName:A1 @@ -31122,7 +31122,7 @@ design: (work@sky130_fd_sc_hd__a22o) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a22o.A2), line:38:5, endln:38:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a22o (work@sky130_fd_sc_hd__a22o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a22o.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__a22o (work@sky130_fd_sc_hd__a22o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a22o.functional.v, line:35:1, endln:61:10 |vpiTypespec: \_logic_typespec: , line:46:12, endln:46:12 |vpiName:A2 @@ -31130,7 +31130,7 @@ design: (work@sky130_fd_sc_hd__a22o) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a22o.B1), line:39:5, endln:39:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a22o (work@sky130_fd_sc_hd__a22o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a22o.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__a22o (work@sky130_fd_sc_hd__a22o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a22o.functional.v, line:35:1, endln:61:10 |vpiTypespec: \_logic_typespec: , line:47:12, endln:47:12 |vpiName:B1 @@ -31138,7 +31138,7 @@ design: (work@sky130_fd_sc_hd__a22o) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a22o.B2), line:40:5, endln:40:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a22o (work@sky130_fd_sc_hd__a22o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a22o.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__a22o (work@sky130_fd_sc_hd__a22o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a22o.functional.v, line:35:1, endln:61:10 |vpiTypespec: \_logic_typespec: , line:48:12, endln:48:12 |vpiName:B2 @@ -31147,7 +31147,7 @@ design: (work@sky130_fd_sc_hd__a22o) |vpiPort: \_port: (X), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__a22o (work@sky130_fd_sc_hd__a22o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a22o.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__a22o (work@sky130_fd_sc_hd__a22o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a22o.functional.v, line:35:1, endln:61:10 |vpiName:X |vpiDirection:2 |vpiLowConn: @@ -31161,7 +31161,7 @@ design: (work@sky130_fd_sc_hd__a22o) |vpiPort: \_port: (A1), line:37:5, endln:37:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a22o (work@sky130_fd_sc_hd__a22o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a22o.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__a22o (work@sky130_fd_sc_hd__a22o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a22o.functional.v, line:35:1, endln:61:10 |vpiName:A1 |vpiDirection:1 |vpiLowConn: @@ -31175,7 +31175,7 @@ design: (work@sky130_fd_sc_hd__a22o) |vpiPort: \_port: (A2), line:38:5, endln:38:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a22o (work@sky130_fd_sc_hd__a22o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a22o.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__a22o (work@sky130_fd_sc_hd__a22o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a22o.functional.v, line:35:1, endln:61:10 |vpiName:A2 |vpiDirection:1 |vpiLowConn: @@ -31189,7 +31189,7 @@ design: (work@sky130_fd_sc_hd__a22o) |vpiPort: \_port: (B1), line:39:5, endln:39:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a22o (work@sky130_fd_sc_hd__a22o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a22o.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__a22o (work@sky130_fd_sc_hd__a22o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a22o.functional.v, line:35:1, endln:61:10 |vpiName:B1 |vpiDirection:1 |vpiLowConn: @@ -31203,7 +31203,7 @@ design: (work@sky130_fd_sc_hd__a22o) |vpiPort: \_port: (B2), line:40:5, endln:40:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a22o (work@sky130_fd_sc_hd__a22o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a22o.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__a22o (work@sky130_fd_sc_hd__a22o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a22o.functional.v, line:35:1, endln:61:10 |vpiName:B2 |vpiDirection:1 |vpiLowConn: @@ -31217,7 +31217,7 @@ design: (work@sky130_fd_sc_hd__a22o) |vpiPrimitive: \_gate: work@and (work@sky130_fd_sc_hd__a22o.and0), line:56:9, endln:56:45 |vpiParent: - \_module: work@sky130_fd_sc_hd__a22o (work@sky130_fd_sc_hd__a22o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a22o.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__a22o (work@sky130_fd_sc_hd__a22o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a22o.functional.v, line:35:1, endln:61:10 |vpiDefName:work@and |vpiName:and0 |vpiFullName:work@sky130_fd_sc_hd__a22o.and0 @@ -31266,7 +31266,7 @@ design: (work@sky130_fd_sc_hd__a22o) |vpiPrimitive: \_gate: work@and (work@sky130_fd_sc_hd__a22o.and1), line:57:9, endln:57:45 |vpiParent: - \_module: work@sky130_fd_sc_hd__a22o (work@sky130_fd_sc_hd__a22o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a22o.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__a22o (work@sky130_fd_sc_hd__a22o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a22o.functional.v, line:35:1, endln:61:10 |vpiDefName:work@and |vpiName:and1 |vpiFullName:work@sky130_fd_sc_hd__a22o.and1 @@ -31315,7 +31315,7 @@ design: (work@sky130_fd_sc_hd__a22o) |vpiPrimitive: \_gate: work@or (work@sky130_fd_sc_hd__a22o.or0), line:58:9, endln:58:45 |vpiParent: - \_module: work@sky130_fd_sc_hd__a22o (work@sky130_fd_sc_hd__a22o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a22o.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__a22o (work@sky130_fd_sc_hd__a22o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a22o.functional.v, line:35:1, endln:61:10 |vpiDefName:work@or |vpiName:or0 |vpiFullName:work@sky130_fd_sc_hd__a22o.or0 @@ -31364,7 +31364,7 @@ design: (work@sky130_fd_sc_hd__a22o) |vpiPrimitive: \_gate: work@buf (work@sky130_fd_sc_hd__a22o.buf0), line:59:9, endln:59:45 |vpiParent: - \_module: work@sky130_fd_sc_hd__a22o (work@sky130_fd_sc_hd__a22o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a22o.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__a22o (work@sky130_fd_sc_hd__a22o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a22o.functional.v, line:35:1, endln:61:10 |vpiDefName:work@buf |vpiName:buf0 |vpiFullName:work@sky130_fd_sc_hd__a22o.buf0 @@ -31407,13 +31407,13 @@ Processing: -cd cells/cells -DUNIT_DELAY -writepp -parse -nocache -nobuiltin -no design: (work@sky130_fd_sc_hd__tapvpwrvgnd) |vpiName:work@sky130_fd_sc_hd__tapvpwrvgnd |uhdmallModules: -\_module: work@sky130_fd_sc_hd__tapvpwrvgnd (work@sky130_fd_sc_hd__tapvpwrvgnd), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__tapvpwrvgnd.functional.v, line:33:1, endln:35:10 +\_module_inst: work@sky130_fd_sc_hd__tapvpwrvgnd (work@sky130_fd_sc_hd__tapvpwrvgnd), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__tapvpwrvgnd.functional.v, line:33:1, endln:35:10 |vpiParent: \_design: (work@sky130_fd_sc_hd__tapvpwrvgnd) |vpiFullName:work@sky130_fd_sc_hd__tapvpwrvgnd |vpiDefName:work@sky130_fd_sc_hd__tapvpwrvgnd |uhdmtopModules: -\_module: work@sky130_fd_sc_hd__tapvpwrvgnd (work@sky130_fd_sc_hd__tapvpwrvgnd), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__tapvpwrvgnd.functional.v, line:33:1, endln:35:10 +\_module_inst: work@sky130_fd_sc_hd__tapvpwrvgnd (work@sky130_fd_sc_hd__tapvpwrvgnd), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__tapvpwrvgnd.functional.v, line:33:1, endln:35:10 |vpiName:work@sky130_fd_sc_hd__tapvpwrvgnd |vpiDefName:work@sky130_fd_sc_hd__tapvpwrvgnd |vpiTop:1 @@ -31429,7 +31429,7 @@ Processing: -cd cells/cells -DUNIT_DELAY -writepp -parse -nocache -nobuiltin -no design: (work@sky130_fd_sc_hd__o31a) |vpiName:work@sky130_fd_sc_hd__o31a |uhdmallModules: -\_module: work@sky130_fd_sc_hd__o31a (work@sky130_fd_sc_hd__o31a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o31a.functional.v, line:35:1, endln:59:10 +\_module_inst: work@sky130_fd_sc_hd__o31a (work@sky130_fd_sc_hd__o31a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o31a.functional.v, line:35:1, endln:59:10 |vpiParent: \_design: (work@sky130_fd_sc_hd__o31a) |vpiFullName:work@sky130_fd_sc_hd__o31a @@ -31437,51 +31437,51 @@ design: (work@sky130_fd_sc_hd__o31a) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o31a.or0_out), line:51:10, endln:51:17 |vpiParent: - \_module: work@sky130_fd_sc_hd__o31a (work@sky130_fd_sc_hd__o31a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o31a.functional.v, line:35:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__o31a (work@sky130_fd_sc_hd__o31a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o31a.functional.v, line:35:1, endln:59:10 |vpiName:or0_out |vpiFullName:work@sky130_fd_sc_hd__o31a.or0_out |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o31a.and0_out_X), line:52:10, endln:52:20 |vpiParent: - \_module: work@sky130_fd_sc_hd__o31a (work@sky130_fd_sc_hd__o31a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o31a.functional.v, line:35:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__o31a (work@sky130_fd_sc_hd__o31a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o31a.functional.v, line:35:1, endln:59:10 |vpiName:and0_out_X |vpiFullName:work@sky130_fd_sc_hd__o31a.and0_out_X |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o31a.X), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__o31a (work@sky130_fd_sc_hd__o31a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o31a.functional.v, line:35:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__o31a (work@sky130_fd_sc_hd__o31a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o31a.functional.v, line:35:1, endln:59:10 |vpiName:X |vpiFullName:work@sky130_fd_sc_hd__o31a.X |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o31a.A1), line:37:5, endln:37:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o31a (work@sky130_fd_sc_hd__o31a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o31a.functional.v, line:35:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__o31a (work@sky130_fd_sc_hd__o31a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o31a.functional.v, line:35:1, endln:59:10 |vpiName:A1 |vpiFullName:work@sky130_fd_sc_hd__o31a.A1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o31a.A2), line:38:5, endln:38:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o31a (work@sky130_fd_sc_hd__o31a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o31a.functional.v, line:35:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__o31a (work@sky130_fd_sc_hd__o31a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o31a.functional.v, line:35:1, endln:59:10 |vpiName:A2 |vpiFullName:work@sky130_fd_sc_hd__o31a.A2 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o31a.A3), line:39:5, endln:39:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o31a (work@sky130_fd_sc_hd__o31a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o31a.functional.v, line:35:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__o31a (work@sky130_fd_sc_hd__o31a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o31a.functional.v, line:35:1, endln:59:10 |vpiName:A3 |vpiFullName:work@sky130_fd_sc_hd__o31a.A3 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o31a.B1), line:40:5, endln:40:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o31a (work@sky130_fd_sc_hd__o31a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o31a.functional.v, line:35:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__o31a (work@sky130_fd_sc_hd__o31a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o31a.functional.v, line:35:1, endln:59:10 |vpiName:B1 |vpiFullName:work@sky130_fd_sc_hd__o31a.B1 |vpiPort: \_port: (X), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__o31a (work@sky130_fd_sc_hd__o31a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o31a.functional.v, line:35:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__o31a (work@sky130_fd_sc_hd__o31a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o31a.functional.v, line:35:1, endln:59:10 |vpiName:X |vpiDirection:2 |vpiLowConn: @@ -31493,7 +31493,7 @@ design: (work@sky130_fd_sc_hd__o31a) |vpiPort: \_port: (A1), line:37:5, endln:37:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o31a (work@sky130_fd_sc_hd__o31a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o31a.functional.v, line:35:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__o31a (work@sky130_fd_sc_hd__o31a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o31a.functional.v, line:35:1, endln:59:10 |vpiName:A1 |vpiDirection:1 |vpiLowConn: @@ -31505,7 +31505,7 @@ design: (work@sky130_fd_sc_hd__o31a) |vpiPort: \_port: (A2), line:38:5, endln:38:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o31a (work@sky130_fd_sc_hd__o31a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o31a.functional.v, line:35:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__o31a (work@sky130_fd_sc_hd__o31a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o31a.functional.v, line:35:1, endln:59:10 |vpiName:A2 |vpiDirection:1 |vpiLowConn: @@ -31517,7 +31517,7 @@ design: (work@sky130_fd_sc_hd__o31a) |vpiPort: \_port: (A3), line:39:5, endln:39:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o31a (work@sky130_fd_sc_hd__o31a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o31a.functional.v, line:35:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__o31a (work@sky130_fd_sc_hd__o31a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o31a.functional.v, line:35:1, endln:59:10 |vpiName:A3 |vpiDirection:1 |vpiLowConn: @@ -31529,7 +31529,7 @@ design: (work@sky130_fd_sc_hd__o31a) |vpiPort: \_port: (B1), line:40:5, endln:40:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o31a (work@sky130_fd_sc_hd__o31a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o31a.functional.v, line:35:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__o31a (work@sky130_fd_sc_hd__o31a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o31a.functional.v, line:35:1, endln:59:10 |vpiName:B1 |vpiDirection:1 |vpiLowConn: @@ -31539,14 +31539,14 @@ design: (work@sky130_fd_sc_hd__o31a) |vpiTypedef: \_logic_typespec: , line:48:12, endln:48:12 |uhdmtopModules: -\_module: work@sky130_fd_sc_hd__o31a (work@sky130_fd_sc_hd__o31a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o31a.functional.v, line:35:1, endln:59:10 +\_module_inst: work@sky130_fd_sc_hd__o31a (work@sky130_fd_sc_hd__o31a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o31a.functional.v, line:35:1, endln:59:10 |vpiName:work@sky130_fd_sc_hd__o31a |vpiDefName:work@sky130_fd_sc_hd__o31a |vpiTop:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o31a.or0_out), line:51:10, endln:51:17 |vpiParent: - \_module: work@sky130_fd_sc_hd__o31a (work@sky130_fd_sc_hd__o31a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o31a.functional.v, line:35:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__o31a (work@sky130_fd_sc_hd__o31a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o31a.functional.v, line:35:1, endln:59:10 |vpiTypespec: \_logic_typespec: , line:51:5, endln:51:9 |vpiName:or0_out @@ -31555,7 +31555,7 @@ design: (work@sky130_fd_sc_hd__o31a) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o31a.and0_out_X), line:52:10, endln:52:20 |vpiParent: - \_module: work@sky130_fd_sc_hd__o31a (work@sky130_fd_sc_hd__o31a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o31a.functional.v, line:35:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__o31a (work@sky130_fd_sc_hd__o31a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o31a.functional.v, line:35:1, endln:59:10 |vpiTypespec: \_logic_typespec: , line:52:5, endln:52:9 |vpiName:and0_out_X @@ -31564,7 +31564,7 @@ design: (work@sky130_fd_sc_hd__o31a) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o31a.X), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__o31a (work@sky130_fd_sc_hd__o31a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o31a.functional.v, line:35:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__o31a (work@sky130_fd_sc_hd__o31a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o31a.functional.v, line:35:1, endln:59:10 |vpiTypespec: \_logic_typespec: , line:44:12, endln:44:12 |vpiName:X @@ -31572,7 +31572,7 @@ design: (work@sky130_fd_sc_hd__o31a) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o31a.A1), line:37:5, endln:37:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o31a (work@sky130_fd_sc_hd__o31a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o31a.functional.v, line:35:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__o31a (work@sky130_fd_sc_hd__o31a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o31a.functional.v, line:35:1, endln:59:10 |vpiTypespec: \_logic_typespec: , line:45:12, endln:45:12 |vpiName:A1 @@ -31580,7 +31580,7 @@ design: (work@sky130_fd_sc_hd__o31a) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o31a.A2), line:38:5, endln:38:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o31a (work@sky130_fd_sc_hd__o31a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o31a.functional.v, line:35:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__o31a (work@sky130_fd_sc_hd__o31a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o31a.functional.v, line:35:1, endln:59:10 |vpiTypespec: \_logic_typespec: , line:46:12, endln:46:12 |vpiName:A2 @@ -31588,7 +31588,7 @@ design: (work@sky130_fd_sc_hd__o31a) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o31a.A3), line:39:5, endln:39:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o31a (work@sky130_fd_sc_hd__o31a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o31a.functional.v, line:35:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__o31a (work@sky130_fd_sc_hd__o31a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o31a.functional.v, line:35:1, endln:59:10 |vpiTypespec: \_logic_typespec: , line:47:12, endln:47:12 |vpiName:A3 @@ -31596,7 +31596,7 @@ design: (work@sky130_fd_sc_hd__o31a) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o31a.B1), line:40:5, endln:40:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o31a (work@sky130_fd_sc_hd__o31a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o31a.functional.v, line:35:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__o31a (work@sky130_fd_sc_hd__o31a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o31a.functional.v, line:35:1, endln:59:10 |vpiTypespec: \_logic_typespec: , line:48:12, endln:48:12 |vpiName:B1 @@ -31605,7 +31605,7 @@ design: (work@sky130_fd_sc_hd__o31a) |vpiPort: \_port: (X), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__o31a (work@sky130_fd_sc_hd__o31a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o31a.functional.v, line:35:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__o31a (work@sky130_fd_sc_hd__o31a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o31a.functional.v, line:35:1, endln:59:10 |vpiName:X |vpiDirection:2 |vpiLowConn: @@ -31619,7 +31619,7 @@ design: (work@sky130_fd_sc_hd__o31a) |vpiPort: \_port: (A1), line:37:5, endln:37:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o31a (work@sky130_fd_sc_hd__o31a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o31a.functional.v, line:35:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__o31a (work@sky130_fd_sc_hd__o31a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o31a.functional.v, line:35:1, endln:59:10 |vpiName:A1 |vpiDirection:1 |vpiLowConn: @@ -31633,7 +31633,7 @@ design: (work@sky130_fd_sc_hd__o31a) |vpiPort: \_port: (A2), line:38:5, endln:38:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o31a (work@sky130_fd_sc_hd__o31a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o31a.functional.v, line:35:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__o31a (work@sky130_fd_sc_hd__o31a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o31a.functional.v, line:35:1, endln:59:10 |vpiName:A2 |vpiDirection:1 |vpiLowConn: @@ -31647,7 +31647,7 @@ design: (work@sky130_fd_sc_hd__o31a) |vpiPort: \_port: (A3), line:39:5, endln:39:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o31a (work@sky130_fd_sc_hd__o31a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o31a.functional.v, line:35:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__o31a (work@sky130_fd_sc_hd__o31a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o31a.functional.v, line:35:1, endln:59:10 |vpiName:A3 |vpiDirection:1 |vpiLowConn: @@ -31661,7 +31661,7 @@ design: (work@sky130_fd_sc_hd__o31a) |vpiPort: \_port: (B1), line:40:5, endln:40:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o31a (work@sky130_fd_sc_hd__o31a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o31a.functional.v, line:35:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__o31a (work@sky130_fd_sc_hd__o31a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o31a.functional.v, line:35:1, endln:59:10 |vpiName:B1 |vpiDirection:1 |vpiLowConn: @@ -31675,7 +31675,7 @@ design: (work@sky130_fd_sc_hd__o31a) |vpiPrimitive: \_gate: work@or (work@sky130_fd_sc_hd__o31a.or0), line:55:9, endln:55:43 |vpiParent: - \_module: work@sky130_fd_sc_hd__o31a (work@sky130_fd_sc_hd__o31a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o31a.functional.v, line:35:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__o31a (work@sky130_fd_sc_hd__o31a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o31a.functional.v, line:35:1, endln:59:10 |vpiDefName:work@or |vpiName:or0 |vpiFullName:work@sky130_fd_sc_hd__o31a.or0 @@ -31738,7 +31738,7 @@ design: (work@sky130_fd_sc_hd__o31a) |vpiPrimitive: \_gate: work@and (work@sky130_fd_sc_hd__o31a.and0), line:56:9, endln:56:43 |vpiParent: - \_module: work@sky130_fd_sc_hd__o31a (work@sky130_fd_sc_hd__o31a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o31a.functional.v, line:35:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__o31a (work@sky130_fd_sc_hd__o31a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o31a.functional.v, line:35:1, endln:59:10 |vpiDefName:work@and |vpiName:and0 |vpiFullName:work@sky130_fd_sc_hd__o31a.and0 @@ -31787,7 +31787,7 @@ design: (work@sky130_fd_sc_hd__o31a) |vpiPrimitive: \_gate: work@buf (work@sky130_fd_sc_hd__o31a.buf0), line:57:9, endln:57:43 |vpiParent: - \_module: work@sky130_fd_sc_hd__o31a (work@sky130_fd_sc_hd__o31a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o31a.functional.v, line:35:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__o31a (work@sky130_fd_sc_hd__o31a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o31a.functional.v, line:35:1, endln:59:10 |vpiDefName:work@buf |vpiName:buf0 |vpiFullName:work@sky130_fd_sc_hd__o31a.buf0 @@ -31830,7 +31830,7 @@ Processing: -cd cells/cells -DUNIT_DELAY -writepp -parse -nocache -nobuiltin -no design: (work@sky130_fd_sc_hd__lpflow_clkbufkapwr) |vpiName:work@sky130_fd_sc_hd__lpflow_clkbufkapwr |uhdmallModules: -\_module: work@sky130_fd_sc_hd__lpflow_clkbufkapwr (work@sky130_fd_sc_hd__lpflow_clkbufkapwr), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_clkbufkapwr.functional.v, line:33:1, endln:49:10 +\_module_inst: work@sky130_fd_sc_hd__lpflow_clkbufkapwr (work@sky130_fd_sc_hd__lpflow_clkbufkapwr), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_clkbufkapwr.functional.v, line:33:1, endln:49:10 |vpiParent: \_design: (work@sky130_fd_sc_hd__lpflow_clkbufkapwr) |vpiFullName:work@sky130_fd_sc_hd__lpflow_clkbufkapwr @@ -31838,26 +31838,26 @@ design: (work@sky130_fd_sc_hd__lpflow_clkbufkapwr) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__lpflow_clkbufkapwr.buf0_out_X), line:43:10, endln:43:20 |vpiParent: - \_module: work@sky130_fd_sc_hd__lpflow_clkbufkapwr (work@sky130_fd_sc_hd__lpflow_clkbufkapwr), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_clkbufkapwr.functional.v, line:33:1, endln:49:10 + \_module_inst: work@sky130_fd_sc_hd__lpflow_clkbufkapwr (work@sky130_fd_sc_hd__lpflow_clkbufkapwr), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_clkbufkapwr.functional.v, line:33:1, endln:49:10 |vpiName:buf0_out_X |vpiFullName:work@sky130_fd_sc_hd__lpflow_clkbufkapwr.buf0_out_X |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__lpflow_clkbufkapwr.X), line:34:5, endln:34:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__lpflow_clkbufkapwr (work@sky130_fd_sc_hd__lpflow_clkbufkapwr), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_clkbufkapwr.functional.v, line:33:1, endln:49:10 + \_module_inst: work@sky130_fd_sc_hd__lpflow_clkbufkapwr (work@sky130_fd_sc_hd__lpflow_clkbufkapwr), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_clkbufkapwr.functional.v, line:33:1, endln:49:10 |vpiName:X |vpiFullName:work@sky130_fd_sc_hd__lpflow_clkbufkapwr.X |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__lpflow_clkbufkapwr.A), line:35:5, endln:35:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__lpflow_clkbufkapwr (work@sky130_fd_sc_hd__lpflow_clkbufkapwr), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_clkbufkapwr.functional.v, line:33:1, endln:49:10 + \_module_inst: work@sky130_fd_sc_hd__lpflow_clkbufkapwr (work@sky130_fd_sc_hd__lpflow_clkbufkapwr), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_clkbufkapwr.functional.v, line:33:1, endln:49:10 |vpiName:A |vpiFullName:work@sky130_fd_sc_hd__lpflow_clkbufkapwr.A |vpiPort: \_port: (X), line:34:5, endln:34:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__lpflow_clkbufkapwr (work@sky130_fd_sc_hd__lpflow_clkbufkapwr), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_clkbufkapwr.functional.v, line:33:1, endln:49:10 + \_module_inst: work@sky130_fd_sc_hd__lpflow_clkbufkapwr (work@sky130_fd_sc_hd__lpflow_clkbufkapwr), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_clkbufkapwr.functional.v, line:33:1, endln:49:10 |vpiName:X |vpiDirection:2 |vpiLowConn: @@ -31869,7 +31869,7 @@ design: (work@sky130_fd_sc_hd__lpflow_clkbufkapwr) |vpiPort: \_port: (A), line:35:5, endln:35:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__lpflow_clkbufkapwr (work@sky130_fd_sc_hd__lpflow_clkbufkapwr), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_clkbufkapwr.functional.v, line:33:1, endln:49:10 + \_module_inst: work@sky130_fd_sc_hd__lpflow_clkbufkapwr (work@sky130_fd_sc_hd__lpflow_clkbufkapwr), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_clkbufkapwr.functional.v, line:33:1, endln:49:10 |vpiName:A |vpiDirection:1 |vpiLowConn: @@ -31879,14 +31879,14 @@ design: (work@sky130_fd_sc_hd__lpflow_clkbufkapwr) |vpiTypedef: \_logic_typespec: , line:40:12, endln:40:12 |uhdmtopModules: -\_module: work@sky130_fd_sc_hd__lpflow_clkbufkapwr (work@sky130_fd_sc_hd__lpflow_clkbufkapwr), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_clkbufkapwr.functional.v, line:33:1, endln:49:10 +\_module_inst: work@sky130_fd_sc_hd__lpflow_clkbufkapwr (work@sky130_fd_sc_hd__lpflow_clkbufkapwr), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_clkbufkapwr.functional.v, line:33:1, endln:49:10 |vpiName:work@sky130_fd_sc_hd__lpflow_clkbufkapwr |vpiDefName:work@sky130_fd_sc_hd__lpflow_clkbufkapwr |vpiTop:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__lpflow_clkbufkapwr.buf0_out_X), line:43:10, endln:43:20 |vpiParent: - \_module: work@sky130_fd_sc_hd__lpflow_clkbufkapwr (work@sky130_fd_sc_hd__lpflow_clkbufkapwr), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_clkbufkapwr.functional.v, line:33:1, endln:49:10 + \_module_inst: work@sky130_fd_sc_hd__lpflow_clkbufkapwr (work@sky130_fd_sc_hd__lpflow_clkbufkapwr), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_clkbufkapwr.functional.v, line:33:1, endln:49:10 |vpiTypespec: \_logic_typespec: , line:43:5, endln:43:9 |vpiName:buf0_out_X @@ -31895,7 +31895,7 @@ design: (work@sky130_fd_sc_hd__lpflow_clkbufkapwr) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__lpflow_clkbufkapwr.X), line:34:5, endln:34:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__lpflow_clkbufkapwr (work@sky130_fd_sc_hd__lpflow_clkbufkapwr), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_clkbufkapwr.functional.v, line:33:1, endln:49:10 + \_module_inst: work@sky130_fd_sc_hd__lpflow_clkbufkapwr (work@sky130_fd_sc_hd__lpflow_clkbufkapwr), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_clkbufkapwr.functional.v, line:33:1, endln:49:10 |vpiTypespec: \_logic_typespec: , line:39:12, endln:39:12 |vpiName:X @@ -31903,7 +31903,7 @@ design: (work@sky130_fd_sc_hd__lpflow_clkbufkapwr) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__lpflow_clkbufkapwr.A), line:35:5, endln:35:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__lpflow_clkbufkapwr (work@sky130_fd_sc_hd__lpflow_clkbufkapwr), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_clkbufkapwr.functional.v, line:33:1, endln:49:10 + \_module_inst: work@sky130_fd_sc_hd__lpflow_clkbufkapwr (work@sky130_fd_sc_hd__lpflow_clkbufkapwr), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_clkbufkapwr.functional.v, line:33:1, endln:49:10 |vpiTypespec: \_logic_typespec: , line:40:12, endln:40:12 |vpiName:A @@ -31912,7 +31912,7 @@ design: (work@sky130_fd_sc_hd__lpflow_clkbufkapwr) |vpiPort: \_port: (X), line:34:5, endln:34:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__lpflow_clkbufkapwr (work@sky130_fd_sc_hd__lpflow_clkbufkapwr), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_clkbufkapwr.functional.v, line:33:1, endln:49:10 + \_module_inst: work@sky130_fd_sc_hd__lpflow_clkbufkapwr (work@sky130_fd_sc_hd__lpflow_clkbufkapwr), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_clkbufkapwr.functional.v, line:33:1, endln:49:10 |vpiName:X |vpiDirection:2 |vpiLowConn: @@ -31926,7 +31926,7 @@ design: (work@sky130_fd_sc_hd__lpflow_clkbufkapwr) |vpiPort: \_port: (A), line:35:5, endln:35:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__lpflow_clkbufkapwr (work@sky130_fd_sc_hd__lpflow_clkbufkapwr), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_clkbufkapwr.functional.v, line:33:1, endln:49:10 + \_module_inst: work@sky130_fd_sc_hd__lpflow_clkbufkapwr (work@sky130_fd_sc_hd__lpflow_clkbufkapwr), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_clkbufkapwr.functional.v, line:33:1, endln:49:10 |vpiName:A |vpiDirection:1 |vpiLowConn: @@ -31940,7 +31940,7 @@ design: (work@sky130_fd_sc_hd__lpflow_clkbufkapwr) |vpiPrimitive: \_gate: work@buf (work@sky130_fd_sc_hd__lpflow_clkbufkapwr.buf0), line:46:9, endln:46:43 |vpiParent: - \_module: work@sky130_fd_sc_hd__lpflow_clkbufkapwr (work@sky130_fd_sc_hd__lpflow_clkbufkapwr), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_clkbufkapwr.functional.v, line:33:1, endln:49:10 + \_module_inst: work@sky130_fd_sc_hd__lpflow_clkbufkapwr (work@sky130_fd_sc_hd__lpflow_clkbufkapwr), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_clkbufkapwr.functional.v, line:33:1, endln:49:10 |vpiDefName:work@buf |vpiName:buf0 |vpiFullName:work@sky130_fd_sc_hd__lpflow_clkbufkapwr.buf0 @@ -31975,7 +31975,7 @@ design: (work@sky130_fd_sc_hd__lpflow_clkbufkapwr) |vpiPrimitive: \_gate: work@buf (work@sky130_fd_sc_hd__lpflow_clkbufkapwr.buf1), line:47:9, endln:47:43 |vpiParent: - \_module: work@sky130_fd_sc_hd__lpflow_clkbufkapwr (work@sky130_fd_sc_hd__lpflow_clkbufkapwr), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_clkbufkapwr.functional.v, line:33:1, endln:49:10 + \_module_inst: work@sky130_fd_sc_hd__lpflow_clkbufkapwr (work@sky130_fd_sc_hd__lpflow_clkbufkapwr), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_clkbufkapwr.functional.v, line:33:1, endln:49:10 |vpiDefName:work@buf |vpiName:buf1 |vpiFullName:work@sky130_fd_sc_hd__lpflow_clkbufkapwr.buf1 @@ -32018,7 +32018,7 @@ Processing: -cd cells/cells -DUNIT_DELAY -writepp -parse -nocache -nobuiltin -no design: (work@sky130_fd_sc_hd__lpflow_inputiso0n) |vpiName:work@sky130_fd_sc_hd__lpflow_inputiso0n |uhdmallModules: -\_module: work@sky130_fd_sc_hd__lpflow_inputiso0n (work@sky130_fd_sc_hd__lpflow_inputiso0n), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_inputiso0n.functional.v, line:35:1, endln:49:10 +\_module_inst: work@sky130_fd_sc_hd__lpflow_inputiso0n (work@sky130_fd_sc_hd__lpflow_inputiso0n), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_inputiso0n.functional.v, line:35:1, endln:49:10 |vpiParent: \_design: (work@sky130_fd_sc_hd__lpflow_inputiso0n) |vpiFullName:work@sky130_fd_sc_hd__lpflow_inputiso0n @@ -32026,25 +32026,25 @@ design: (work@sky130_fd_sc_hd__lpflow_inputiso0n) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__lpflow_inputiso0n.X), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__lpflow_inputiso0n (work@sky130_fd_sc_hd__lpflow_inputiso0n), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_inputiso0n.functional.v, line:35:1, endln:49:10 + \_module_inst: work@sky130_fd_sc_hd__lpflow_inputiso0n (work@sky130_fd_sc_hd__lpflow_inputiso0n), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_inputiso0n.functional.v, line:35:1, endln:49:10 |vpiName:X |vpiFullName:work@sky130_fd_sc_hd__lpflow_inputiso0n.X |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__lpflow_inputiso0n.A), line:37:5, endln:37:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__lpflow_inputiso0n (work@sky130_fd_sc_hd__lpflow_inputiso0n), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_inputiso0n.functional.v, line:35:1, endln:49:10 + \_module_inst: work@sky130_fd_sc_hd__lpflow_inputiso0n (work@sky130_fd_sc_hd__lpflow_inputiso0n), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_inputiso0n.functional.v, line:35:1, endln:49:10 |vpiName:A |vpiFullName:work@sky130_fd_sc_hd__lpflow_inputiso0n.A |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__lpflow_inputiso0n.SLEEP_B), line:38:5, endln:38:12 |vpiParent: - \_module: work@sky130_fd_sc_hd__lpflow_inputiso0n (work@sky130_fd_sc_hd__lpflow_inputiso0n), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_inputiso0n.functional.v, line:35:1, endln:49:10 + \_module_inst: work@sky130_fd_sc_hd__lpflow_inputiso0n (work@sky130_fd_sc_hd__lpflow_inputiso0n), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_inputiso0n.functional.v, line:35:1, endln:49:10 |vpiName:SLEEP_B |vpiFullName:work@sky130_fd_sc_hd__lpflow_inputiso0n.SLEEP_B |vpiPort: \_port: (X), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__lpflow_inputiso0n (work@sky130_fd_sc_hd__lpflow_inputiso0n), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_inputiso0n.functional.v, line:35:1, endln:49:10 + \_module_inst: work@sky130_fd_sc_hd__lpflow_inputiso0n (work@sky130_fd_sc_hd__lpflow_inputiso0n), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_inputiso0n.functional.v, line:35:1, endln:49:10 |vpiName:X |vpiDirection:2 |vpiLowConn: @@ -32056,7 +32056,7 @@ design: (work@sky130_fd_sc_hd__lpflow_inputiso0n) |vpiPort: \_port: (A), line:37:5, endln:37:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__lpflow_inputiso0n (work@sky130_fd_sc_hd__lpflow_inputiso0n), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_inputiso0n.functional.v, line:35:1, endln:49:10 + \_module_inst: work@sky130_fd_sc_hd__lpflow_inputiso0n (work@sky130_fd_sc_hd__lpflow_inputiso0n), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_inputiso0n.functional.v, line:35:1, endln:49:10 |vpiName:A |vpiDirection:1 |vpiLowConn: @@ -32068,7 +32068,7 @@ design: (work@sky130_fd_sc_hd__lpflow_inputiso0n) |vpiPort: \_port: (SLEEP_B), line:38:5, endln:38:12 |vpiParent: - \_module: work@sky130_fd_sc_hd__lpflow_inputiso0n (work@sky130_fd_sc_hd__lpflow_inputiso0n), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_inputiso0n.functional.v, line:35:1, endln:49:10 + \_module_inst: work@sky130_fd_sc_hd__lpflow_inputiso0n (work@sky130_fd_sc_hd__lpflow_inputiso0n), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_inputiso0n.functional.v, line:35:1, endln:49:10 |vpiName:SLEEP_B |vpiDirection:1 |vpiLowConn: @@ -32078,14 +32078,14 @@ design: (work@sky130_fd_sc_hd__lpflow_inputiso0n) |vpiTypedef: \_logic_typespec: , line:44:12, endln:44:12 |uhdmtopModules: -\_module: work@sky130_fd_sc_hd__lpflow_inputiso0n (work@sky130_fd_sc_hd__lpflow_inputiso0n), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_inputiso0n.functional.v, line:35:1, endln:49:10 +\_module_inst: work@sky130_fd_sc_hd__lpflow_inputiso0n (work@sky130_fd_sc_hd__lpflow_inputiso0n), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_inputiso0n.functional.v, line:35:1, endln:49:10 |vpiName:work@sky130_fd_sc_hd__lpflow_inputiso0n |vpiDefName:work@sky130_fd_sc_hd__lpflow_inputiso0n |vpiTop:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__lpflow_inputiso0n.X), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__lpflow_inputiso0n (work@sky130_fd_sc_hd__lpflow_inputiso0n), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_inputiso0n.functional.v, line:35:1, endln:49:10 + \_module_inst: work@sky130_fd_sc_hd__lpflow_inputiso0n (work@sky130_fd_sc_hd__lpflow_inputiso0n), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_inputiso0n.functional.v, line:35:1, endln:49:10 |vpiTypespec: \_logic_typespec: , line:42:12, endln:42:12 |vpiName:X @@ -32093,7 +32093,7 @@ design: (work@sky130_fd_sc_hd__lpflow_inputiso0n) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__lpflow_inputiso0n.A), line:37:5, endln:37:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__lpflow_inputiso0n (work@sky130_fd_sc_hd__lpflow_inputiso0n), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_inputiso0n.functional.v, line:35:1, endln:49:10 + \_module_inst: work@sky130_fd_sc_hd__lpflow_inputiso0n (work@sky130_fd_sc_hd__lpflow_inputiso0n), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_inputiso0n.functional.v, line:35:1, endln:49:10 |vpiTypespec: \_logic_typespec: , line:43:12, endln:43:12 |vpiName:A @@ -32101,7 +32101,7 @@ design: (work@sky130_fd_sc_hd__lpflow_inputiso0n) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__lpflow_inputiso0n.SLEEP_B), line:38:5, endln:38:12 |vpiParent: - \_module: work@sky130_fd_sc_hd__lpflow_inputiso0n (work@sky130_fd_sc_hd__lpflow_inputiso0n), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_inputiso0n.functional.v, line:35:1, endln:49:10 + \_module_inst: work@sky130_fd_sc_hd__lpflow_inputiso0n (work@sky130_fd_sc_hd__lpflow_inputiso0n), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_inputiso0n.functional.v, line:35:1, endln:49:10 |vpiTypespec: \_logic_typespec: , line:44:12, endln:44:12 |vpiName:SLEEP_B @@ -32110,7 +32110,7 @@ design: (work@sky130_fd_sc_hd__lpflow_inputiso0n) |vpiPort: \_port: (X), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__lpflow_inputiso0n (work@sky130_fd_sc_hd__lpflow_inputiso0n), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_inputiso0n.functional.v, line:35:1, endln:49:10 + \_module_inst: work@sky130_fd_sc_hd__lpflow_inputiso0n (work@sky130_fd_sc_hd__lpflow_inputiso0n), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_inputiso0n.functional.v, line:35:1, endln:49:10 |vpiName:X |vpiDirection:2 |vpiLowConn: @@ -32124,7 +32124,7 @@ design: (work@sky130_fd_sc_hd__lpflow_inputiso0n) |vpiPort: \_port: (A), line:37:5, endln:37:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__lpflow_inputiso0n (work@sky130_fd_sc_hd__lpflow_inputiso0n), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_inputiso0n.functional.v, line:35:1, endln:49:10 + \_module_inst: work@sky130_fd_sc_hd__lpflow_inputiso0n (work@sky130_fd_sc_hd__lpflow_inputiso0n), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_inputiso0n.functional.v, line:35:1, endln:49:10 |vpiName:A |vpiDirection:1 |vpiLowConn: @@ -32138,7 +32138,7 @@ design: (work@sky130_fd_sc_hd__lpflow_inputiso0n) |vpiPort: \_port: (SLEEP_B), line:38:5, endln:38:12 |vpiParent: - \_module: work@sky130_fd_sc_hd__lpflow_inputiso0n (work@sky130_fd_sc_hd__lpflow_inputiso0n), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_inputiso0n.functional.v, line:35:1, endln:49:10 + \_module_inst: work@sky130_fd_sc_hd__lpflow_inputiso0n (work@sky130_fd_sc_hd__lpflow_inputiso0n), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_inputiso0n.functional.v, line:35:1, endln:49:10 |vpiName:SLEEP_B |vpiDirection:1 |vpiLowConn: @@ -32152,7 +32152,7 @@ design: (work@sky130_fd_sc_hd__lpflow_inputiso0n) |vpiPrimitive: \_gate: work@and (work@sky130_fd_sc_hd__lpflow_inputiso0n.and0), line:47:9, endln:47:39 |vpiParent: - \_module: work@sky130_fd_sc_hd__lpflow_inputiso0n (work@sky130_fd_sc_hd__lpflow_inputiso0n), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_inputiso0n.functional.v, line:35:1, endln:49:10 + \_module_inst: work@sky130_fd_sc_hd__lpflow_inputiso0n (work@sky130_fd_sc_hd__lpflow_inputiso0n), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_inputiso0n.functional.v, line:35:1, endln:49:10 |vpiDefName:work@and |vpiName:and0 |vpiFullName:work@sky130_fd_sc_hd__lpflow_inputiso0n.and0 @@ -32209,7 +32209,7 @@ Processing: -cd cells/cells -DUNIT_DELAY -writepp -parse -nocache -nobuiltin -no design: (work@sky130_fd_sc_hd__fill) |vpiName:work@sky130_fd_sc_hd__fill |uhdmallModules: -\_module: work@sky130_fd_sc_hd__fill (work@sky130_fd_sc_hd__fill), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fill.functional.v, line:33:1, endln:41:10 +\_module_inst: work@sky130_fd_sc_hd__fill (work@sky130_fd_sc_hd__fill), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fill.functional.v, line:33:1, endln:41:10 |vpiParent: \_design: (work@sky130_fd_sc_hd__fill) |vpiFullName:work@sky130_fd_sc_hd__fill @@ -32217,40 +32217,40 @@ design: (work@sky130_fd_sc_hd__fill) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__fill.VPWR), line:36:13, endln:36:17 |vpiParent: - \_module: work@sky130_fd_sc_hd__fill (work@sky130_fd_sc_hd__fill), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fill.functional.v, line:33:1, endln:41:10 + \_module_inst: work@sky130_fd_sc_hd__fill (work@sky130_fd_sc_hd__fill), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fill.functional.v, line:33:1, endln:41:10 |vpiName:VPWR |vpiFullName:work@sky130_fd_sc_hd__fill.VPWR |vpiNetType:10 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__fill.VGND), line:37:13, endln:37:17 |vpiParent: - \_module: work@sky130_fd_sc_hd__fill (work@sky130_fd_sc_hd__fill), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fill.functional.v, line:33:1, endln:41:10 + \_module_inst: work@sky130_fd_sc_hd__fill (work@sky130_fd_sc_hd__fill), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fill.functional.v, line:33:1, endln:41:10 |vpiName:VGND |vpiFullName:work@sky130_fd_sc_hd__fill.VGND |vpiNetType:11 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__fill.VPB), line:38:13, endln:38:16 |vpiParent: - \_module: work@sky130_fd_sc_hd__fill (work@sky130_fd_sc_hd__fill), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fill.functional.v, line:33:1, endln:41:10 + \_module_inst: work@sky130_fd_sc_hd__fill (work@sky130_fd_sc_hd__fill), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fill.functional.v, line:33:1, endln:41:10 |vpiName:VPB |vpiFullName:work@sky130_fd_sc_hd__fill.VPB |vpiNetType:10 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__fill.VNB), line:39:13, endln:39:16 |vpiParent: - \_module: work@sky130_fd_sc_hd__fill (work@sky130_fd_sc_hd__fill), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fill.functional.v, line:33:1, endln:41:10 + \_module_inst: work@sky130_fd_sc_hd__fill (work@sky130_fd_sc_hd__fill), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fill.functional.v, line:33:1, endln:41:10 |vpiName:VNB |vpiFullName:work@sky130_fd_sc_hd__fill.VNB |vpiNetType:11 |uhdmtopModules: -\_module: work@sky130_fd_sc_hd__fill (work@sky130_fd_sc_hd__fill), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fill.functional.v, line:33:1, endln:41:10 +\_module_inst: work@sky130_fd_sc_hd__fill (work@sky130_fd_sc_hd__fill), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fill.functional.v, line:33:1, endln:41:10 |vpiName:work@sky130_fd_sc_hd__fill |vpiDefName:work@sky130_fd_sc_hd__fill |vpiTop:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__fill.VPWR), line:36:13, endln:36:17 |vpiParent: - \_module: work@sky130_fd_sc_hd__fill (work@sky130_fd_sc_hd__fill), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fill.functional.v, line:33:1, endln:41:10 + \_module_inst: work@sky130_fd_sc_hd__fill (work@sky130_fd_sc_hd__fill), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fill.functional.v, line:33:1, endln:41:10 |vpiTypespec: \_logic_typespec: , line:36:5, endln:36:12 |vpiName:VPWR @@ -32259,7 +32259,7 @@ design: (work@sky130_fd_sc_hd__fill) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__fill.VGND), line:37:13, endln:37:17 |vpiParent: - \_module: work@sky130_fd_sc_hd__fill (work@sky130_fd_sc_hd__fill), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fill.functional.v, line:33:1, endln:41:10 + \_module_inst: work@sky130_fd_sc_hd__fill (work@sky130_fd_sc_hd__fill), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fill.functional.v, line:33:1, endln:41:10 |vpiTypespec: \_logic_typespec: , line:37:5, endln:37:12 |vpiName:VGND @@ -32268,7 +32268,7 @@ design: (work@sky130_fd_sc_hd__fill) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__fill.VPB), line:38:13, endln:38:16 |vpiParent: - \_module: work@sky130_fd_sc_hd__fill (work@sky130_fd_sc_hd__fill), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fill.functional.v, line:33:1, endln:41:10 + \_module_inst: work@sky130_fd_sc_hd__fill (work@sky130_fd_sc_hd__fill), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fill.functional.v, line:33:1, endln:41:10 |vpiTypespec: \_logic_typespec: , line:38:5, endln:38:12 |vpiName:VPB @@ -32277,7 +32277,7 @@ design: (work@sky130_fd_sc_hd__fill) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__fill.VNB), line:39:13, endln:39:16 |vpiParent: - \_module: work@sky130_fd_sc_hd__fill (work@sky130_fd_sc_hd__fill), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fill.functional.v, line:33:1, endln:41:10 + \_module_inst: work@sky130_fd_sc_hd__fill (work@sky130_fd_sc_hd__fill), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fill.functional.v, line:33:1, endln:41:10 |vpiTypespec: \_logic_typespec: , line:39:5, endln:39:12 |vpiName:VNB @@ -32295,7 +32295,7 @@ Processing: -cd cells/cells -DUNIT_DELAY -writepp -parse -nocache -nobuiltin -no design: (work@sky130_fd_sc_hd__or2) |vpiName:work@sky130_fd_sc_hd__or2 |uhdmallModules: -\_module: work@sky130_fd_sc_hd__or2 (work@sky130_fd_sc_hd__or2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or2.functional.v, line:33:1, endln:51:10 +\_module_inst: work@sky130_fd_sc_hd__or2 (work@sky130_fd_sc_hd__or2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or2.functional.v, line:33:1, endln:51:10 |vpiParent: \_design: (work@sky130_fd_sc_hd__or2) |vpiFullName:work@sky130_fd_sc_hd__or2 @@ -32303,32 +32303,32 @@ design: (work@sky130_fd_sc_hd__or2) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__or2.or0_out_X), line:45:10, endln:45:19 |vpiParent: - \_module: work@sky130_fd_sc_hd__or2 (work@sky130_fd_sc_hd__or2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or2.functional.v, line:33:1, endln:51:10 + \_module_inst: work@sky130_fd_sc_hd__or2 (work@sky130_fd_sc_hd__or2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or2.functional.v, line:33:1, endln:51:10 |vpiName:or0_out_X |vpiFullName:work@sky130_fd_sc_hd__or2.or0_out_X |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__or2.X), line:34:5, endln:34:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__or2 (work@sky130_fd_sc_hd__or2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or2.functional.v, line:33:1, endln:51:10 + \_module_inst: work@sky130_fd_sc_hd__or2 (work@sky130_fd_sc_hd__or2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or2.functional.v, line:33:1, endln:51:10 |vpiName:X |vpiFullName:work@sky130_fd_sc_hd__or2.X |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__or2.A), line:35:5, endln:35:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__or2 (work@sky130_fd_sc_hd__or2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or2.functional.v, line:33:1, endln:51:10 + \_module_inst: work@sky130_fd_sc_hd__or2 (work@sky130_fd_sc_hd__or2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or2.functional.v, line:33:1, endln:51:10 |vpiName:A |vpiFullName:work@sky130_fd_sc_hd__or2.A |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__or2.B), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__or2 (work@sky130_fd_sc_hd__or2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or2.functional.v, line:33:1, endln:51:10 + \_module_inst: work@sky130_fd_sc_hd__or2 (work@sky130_fd_sc_hd__or2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or2.functional.v, line:33:1, endln:51:10 |vpiName:B |vpiFullName:work@sky130_fd_sc_hd__or2.B |vpiPort: \_port: (X), line:34:5, endln:34:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__or2 (work@sky130_fd_sc_hd__or2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or2.functional.v, line:33:1, endln:51:10 + \_module_inst: work@sky130_fd_sc_hd__or2 (work@sky130_fd_sc_hd__or2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or2.functional.v, line:33:1, endln:51:10 |vpiName:X |vpiDirection:2 |vpiLowConn: @@ -32340,7 +32340,7 @@ design: (work@sky130_fd_sc_hd__or2) |vpiPort: \_port: (A), line:35:5, endln:35:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__or2 (work@sky130_fd_sc_hd__or2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or2.functional.v, line:33:1, endln:51:10 + \_module_inst: work@sky130_fd_sc_hd__or2 (work@sky130_fd_sc_hd__or2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or2.functional.v, line:33:1, endln:51:10 |vpiName:A |vpiDirection:1 |vpiLowConn: @@ -32352,7 +32352,7 @@ design: (work@sky130_fd_sc_hd__or2) |vpiPort: \_port: (B), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__or2 (work@sky130_fd_sc_hd__or2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or2.functional.v, line:33:1, endln:51:10 + \_module_inst: work@sky130_fd_sc_hd__or2 (work@sky130_fd_sc_hd__or2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or2.functional.v, line:33:1, endln:51:10 |vpiName:B |vpiDirection:1 |vpiLowConn: @@ -32362,14 +32362,14 @@ design: (work@sky130_fd_sc_hd__or2) |vpiTypedef: \_logic_typespec: , line:42:12, endln:42:12 |uhdmtopModules: -\_module: work@sky130_fd_sc_hd__or2 (work@sky130_fd_sc_hd__or2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or2.functional.v, line:33:1, endln:51:10 +\_module_inst: work@sky130_fd_sc_hd__or2 (work@sky130_fd_sc_hd__or2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or2.functional.v, line:33:1, endln:51:10 |vpiName:work@sky130_fd_sc_hd__or2 |vpiDefName:work@sky130_fd_sc_hd__or2 |vpiTop:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__or2.or0_out_X), line:45:10, endln:45:19 |vpiParent: - \_module: work@sky130_fd_sc_hd__or2 (work@sky130_fd_sc_hd__or2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or2.functional.v, line:33:1, endln:51:10 + \_module_inst: work@sky130_fd_sc_hd__or2 (work@sky130_fd_sc_hd__or2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or2.functional.v, line:33:1, endln:51:10 |vpiTypespec: \_logic_typespec: , line:45:5, endln:45:9 |vpiName:or0_out_X @@ -32378,7 +32378,7 @@ design: (work@sky130_fd_sc_hd__or2) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__or2.X), line:34:5, endln:34:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__or2 (work@sky130_fd_sc_hd__or2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or2.functional.v, line:33:1, endln:51:10 + \_module_inst: work@sky130_fd_sc_hd__or2 (work@sky130_fd_sc_hd__or2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or2.functional.v, line:33:1, endln:51:10 |vpiTypespec: \_logic_typespec: , line:40:12, endln:40:12 |vpiName:X @@ -32386,7 +32386,7 @@ design: (work@sky130_fd_sc_hd__or2) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__or2.A), line:35:5, endln:35:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__or2 (work@sky130_fd_sc_hd__or2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or2.functional.v, line:33:1, endln:51:10 + \_module_inst: work@sky130_fd_sc_hd__or2 (work@sky130_fd_sc_hd__or2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or2.functional.v, line:33:1, endln:51:10 |vpiTypespec: \_logic_typespec: , line:41:12, endln:41:12 |vpiName:A @@ -32394,7 +32394,7 @@ design: (work@sky130_fd_sc_hd__or2) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__or2.B), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__or2 (work@sky130_fd_sc_hd__or2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or2.functional.v, line:33:1, endln:51:10 + \_module_inst: work@sky130_fd_sc_hd__or2 (work@sky130_fd_sc_hd__or2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or2.functional.v, line:33:1, endln:51:10 |vpiTypespec: \_logic_typespec: , line:42:12, endln:42:12 |vpiName:B @@ -32403,7 +32403,7 @@ design: (work@sky130_fd_sc_hd__or2) |vpiPort: \_port: (X), line:34:5, endln:34:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__or2 (work@sky130_fd_sc_hd__or2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or2.functional.v, line:33:1, endln:51:10 + \_module_inst: work@sky130_fd_sc_hd__or2 (work@sky130_fd_sc_hd__or2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or2.functional.v, line:33:1, endln:51:10 |vpiName:X |vpiDirection:2 |vpiLowConn: @@ -32417,7 +32417,7 @@ design: (work@sky130_fd_sc_hd__or2) |vpiPort: \_port: (A), line:35:5, endln:35:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__or2 (work@sky130_fd_sc_hd__or2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or2.functional.v, line:33:1, endln:51:10 + \_module_inst: work@sky130_fd_sc_hd__or2 (work@sky130_fd_sc_hd__or2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or2.functional.v, line:33:1, endln:51:10 |vpiName:A |vpiDirection:1 |vpiLowConn: @@ -32431,7 +32431,7 @@ design: (work@sky130_fd_sc_hd__or2) |vpiPort: \_port: (B), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__or2 (work@sky130_fd_sc_hd__or2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or2.functional.v, line:33:1, endln:51:10 + \_module_inst: work@sky130_fd_sc_hd__or2 (work@sky130_fd_sc_hd__or2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or2.functional.v, line:33:1, endln:51:10 |vpiName:B |vpiDirection:1 |vpiLowConn: @@ -32445,7 +32445,7 @@ design: (work@sky130_fd_sc_hd__or2) |vpiPrimitive: \_gate: work@or (work@sky130_fd_sc_hd__or2.or0), line:48:9, endln:48:42 |vpiParent: - \_module: work@sky130_fd_sc_hd__or2 (work@sky130_fd_sc_hd__or2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or2.functional.v, line:33:1, endln:51:10 + \_module_inst: work@sky130_fd_sc_hd__or2 (work@sky130_fd_sc_hd__or2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or2.functional.v, line:33:1, endln:51:10 |vpiDefName:work@or |vpiName:or0 |vpiFullName:work@sky130_fd_sc_hd__or2.or0 @@ -32494,7 +32494,7 @@ design: (work@sky130_fd_sc_hd__or2) |vpiPrimitive: \_gate: work@buf (work@sky130_fd_sc_hd__or2.buf0), line:49:9, endln:49:42 |vpiParent: - \_module: work@sky130_fd_sc_hd__or2 (work@sky130_fd_sc_hd__or2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or2.functional.v, line:33:1, endln:51:10 + \_module_inst: work@sky130_fd_sc_hd__or2 (work@sky130_fd_sc_hd__or2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or2.functional.v, line:33:1, endln:51:10 |vpiDefName:work@buf |vpiName:buf0 |vpiFullName:work@sky130_fd_sc_hd__or2.buf0 @@ -32537,7 +32537,7 @@ Processing: -cd cells/cells -DUNIT_DELAY -writepp -parse -nocache -nobuiltin -no design: (work@sky130_fd_sc_hd__a221o) |vpiName:work@sky130_fd_sc_hd__a221o |uhdmallModules: -\_module: work@sky130_fd_sc_hd__a221o (work@sky130_fd_sc_hd__a221o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a221o.functional.v, line:35:1, endln:63:10 +\_module_inst: work@sky130_fd_sc_hd__a221o (work@sky130_fd_sc_hd__a221o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a221o.functional.v, line:35:1, endln:63:10 |vpiParent: \_design: (work@sky130_fd_sc_hd__a221o) |vpiFullName:work@sky130_fd_sc_hd__a221o @@ -32545,64 +32545,64 @@ design: (work@sky130_fd_sc_hd__a221o) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a221o.and0_out), line:53:10, endln:53:18 |vpiParent: - \_module: work@sky130_fd_sc_hd__a221o (work@sky130_fd_sc_hd__a221o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a221o.functional.v, line:35:1, endln:63:10 + \_module_inst: work@sky130_fd_sc_hd__a221o (work@sky130_fd_sc_hd__a221o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a221o.functional.v, line:35:1, endln:63:10 |vpiName:and0_out |vpiFullName:work@sky130_fd_sc_hd__a221o.and0_out |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a221o.and1_out), line:54:10, endln:54:18 |vpiParent: - \_module: work@sky130_fd_sc_hd__a221o (work@sky130_fd_sc_hd__a221o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a221o.functional.v, line:35:1, endln:63:10 + \_module_inst: work@sky130_fd_sc_hd__a221o (work@sky130_fd_sc_hd__a221o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a221o.functional.v, line:35:1, endln:63:10 |vpiName:and1_out |vpiFullName:work@sky130_fd_sc_hd__a221o.and1_out |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a221o.or0_out_X), line:55:10, endln:55:19 |vpiParent: - \_module: work@sky130_fd_sc_hd__a221o (work@sky130_fd_sc_hd__a221o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a221o.functional.v, line:35:1, endln:63:10 + \_module_inst: work@sky130_fd_sc_hd__a221o (work@sky130_fd_sc_hd__a221o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a221o.functional.v, line:35:1, endln:63:10 |vpiName:or0_out_X |vpiFullName:work@sky130_fd_sc_hd__a221o.or0_out_X |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a221o.X), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__a221o (work@sky130_fd_sc_hd__a221o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a221o.functional.v, line:35:1, endln:63:10 + \_module_inst: work@sky130_fd_sc_hd__a221o (work@sky130_fd_sc_hd__a221o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a221o.functional.v, line:35:1, endln:63:10 |vpiName:X |vpiFullName:work@sky130_fd_sc_hd__a221o.X |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a221o.A1), line:37:5, endln:37:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a221o (work@sky130_fd_sc_hd__a221o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a221o.functional.v, line:35:1, endln:63:10 + \_module_inst: work@sky130_fd_sc_hd__a221o (work@sky130_fd_sc_hd__a221o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a221o.functional.v, line:35:1, endln:63:10 |vpiName:A1 |vpiFullName:work@sky130_fd_sc_hd__a221o.A1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a221o.A2), line:38:5, endln:38:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a221o (work@sky130_fd_sc_hd__a221o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a221o.functional.v, line:35:1, endln:63:10 + \_module_inst: work@sky130_fd_sc_hd__a221o (work@sky130_fd_sc_hd__a221o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a221o.functional.v, line:35:1, endln:63:10 |vpiName:A2 |vpiFullName:work@sky130_fd_sc_hd__a221o.A2 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a221o.B1), line:39:5, endln:39:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a221o (work@sky130_fd_sc_hd__a221o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a221o.functional.v, line:35:1, endln:63:10 + \_module_inst: work@sky130_fd_sc_hd__a221o (work@sky130_fd_sc_hd__a221o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a221o.functional.v, line:35:1, endln:63:10 |vpiName:B1 |vpiFullName:work@sky130_fd_sc_hd__a221o.B1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a221o.B2), line:40:5, endln:40:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a221o (work@sky130_fd_sc_hd__a221o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a221o.functional.v, line:35:1, endln:63:10 + \_module_inst: work@sky130_fd_sc_hd__a221o (work@sky130_fd_sc_hd__a221o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a221o.functional.v, line:35:1, endln:63:10 |vpiName:B2 |vpiFullName:work@sky130_fd_sc_hd__a221o.B2 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a221o.C1), line:41:5, endln:41:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a221o (work@sky130_fd_sc_hd__a221o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a221o.functional.v, line:35:1, endln:63:10 + \_module_inst: work@sky130_fd_sc_hd__a221o (work@sky130_fd_sc_hd__a221o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a221o.functional.v, line:35:1, endln:63:10 |vpiName:C1 |vpiFullName:work@sky130_fd_sc_hd__a221o.C1 |vpiPort: \_port: (X), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__a221o (work@sky130_fd_sc_hd__a221o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a221o.functional.v, line:35:1, endln:63:10 + \_module_inst: work@sky130_fd_sc_hd__a221o (work@sky130_fd_sc_hd__a221o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a221o.functional.v, line:35:1, endln:63:10 |vpiName:X |vpiDirection:2 |vpiLowConn: @@ -32614,7 +32614,7 @@ design: (work@sky130_fd_sc_hd__a221o) |vpiPort: \_port: (A1), line:37:5, endln:37:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a221o (work@sky130_fd_sc_hd__a221o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a221o.functional.v, line:35:1, endln:63:10 + \_module_inst: work@sky130_fd_sc_hd__a221o (work@sky130_fd_sc_hd__a221o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a221o.functional.v, line:35:1, endln:63:10 |vpiName:A1 |vpiDirection:1 |vpiLowConn: @@ -32626,7 +32626,7 @@ design: (work@sky130_fd_sc_hd__a221o) |vpiPort: \_port: (A2), line:38:5, endln:38:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a221o (work@sky130_fd_sc_hd__a221o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a221o.functional.v, line:35:1, endln:63:10 + \_module_inst: work@sky130_fd_sc_hd__a221o (work@sky130_fd_sc_hd__a221o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a221o.functional.v, line:35:1, endln:63:10 |vpiName:A2 |vpiDirection:1 |vpiLowConn: @@ -32638,7 +32638,7 @@ design: (work@sky130_fd_sc_hd__a221o) |vpiPort: \_port: (B1), line:39:5, endln:39:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a221o (work@sky130_fd_sc_hd__a221o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a221o.functional.v, line:35:1, endln:63:10 + \_module_inst: work@sky130_fd_sc_hd__a221o (work@sky130_fd_sc_hd__a221o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a221o.functional.v, line:35:1, endln:63:10 |vpiName:B1 |vpiDirection:1 |vpiLowConn: @@ -32650,7 +32650,7 @@ design: (work@sky130_fd_sc_hd__a221o) |vpiPort: \_port: (B2), line:40:5, endln:40:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a221o (work@sky130_fd_sc_hd__a221o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a221o.functional.v, line:35:1, endln:63:10 + \_module_inst: work@sky130_fd_sc_hd__a221o (work@sky130_fd_sc_hd__a221o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a221o.functional.v, line:35:1, endln:63:10 |vpiName:B2 |vpiDirection:1 |vpiLowConn: @@ -32662,7 +32662,7 @@ design: (work@sky130_fd_sc_hd__a221o) |vpiPort: \_port: (C1), line:41:5, endln:41:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a221o (work@sky130_fd_sc_hd__a221o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a221o.functional.v, line:35:1, endln:63:10 + \_module_inst: work@sky130_fd_sc_hd__a221o (work@sky130_fd_sc_hd__a221o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a221o.functional.v, line:35:1, endln:63:10 |vpiName:C1 |vpiDirection:1 |vpiLowConn: @@ -32672,14 +32672,14 @@ design: (work@sky130_fd_sc_hd__a221o) |vpiTypedef: \_logic_typespec: , line:50:12, endln:50:12 |uhdmtopModules: -\_module: work@sky130_fd_sc_hd__a221o (work@sky130_fd_sc_hd__a221o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a221o.functional.v, line:35:1, endln:63:10 +\_module_inst: work@sky130_fd_sc_hd__a221o (work@sky130_fd_sc_hd__a221o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a221o.functional.v, line:35:1, endln:63:10 |vpiName:work@sky130_fd_sc_hd__a221o |vpiDefName:work@sky130_fd_sc_hd__a221o |vpiTop:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a221o.and0_out), line:53:10, endln:53:18 |vpiParent: - \_module: work@sky130_fd_sc_hd__a221o (work@sky130_fd_sc_hd__a221o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a221o.functional.v, line:35:1, endln:63:10 + \_module_inst: work@sky130_fd_sc_hd__a221o (work@sky130_fd_sc_hd__a221o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a221o.functional.v, line:35:1, endln:63:10 |vpiTypespec: \_logic_typespec: , line:53:5, endln:53:9 |vpiName:and0_out @@ -32688,7 +32688,7 @@ design: (work@sky130_fd_sc_hd__a221o) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a221o.and1_out), line:54:10, endln:54:18 |vpiParent: - \_module: work@sky130_fd_sc_hd__a221o (work@sky130_fd_sc_hd__a221o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a221o.functional.v, line:35:1, endln:63:10 + \_module_inst: work@sky130_fd_sc_hd__a221o (work@sky130_fd_sc_hd__a221o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a221o.functional.v, line:35:1, endln:63:10 |vpiTypespec: \_logic_typespec: , line:54:5, endln:54:9 |vpiName:and1_out @@ -32697,7 +32697,7 @@ design: (work@sky130_fd_sc_hd__a221o) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a221o.or0_out_X), line:55:10, endln:55:19 |vpiParent: - \_module: work@sky130_fd_sc_hd__a221o (work@sky130_fd_sc_hd__a221o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a221o.functional.v, line:35:1, endln:63:10 + \_module_inst: work@sky130_fd_sc_hd__a221o (work@sky130_fd_sc_hd__a221o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a221o.functional.v, line:35:1, endln:63:10 |vpiTypespec: \_logic_typespec: , line:55:5, endln:55:9 |vpiName:or0_out_X @@ -32706,7 +32706,7 @@ design: (work@sky130_fd_sc_hd__a221o) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a221o.X), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__a221o (work@sky130_fd_sc_hd__a221o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a221o.functional.v, line:35:1, endln:63:10 + \_module_inst: work@sky130_fd_sc_hd__a221o (work@sky130_fd_sc_hd__a221o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a221o.functional.v, line:35:1, endln:63:10 |vpiTypespec: \_logic_typespec: , line:45:12, endln:45:12 |vpiName:X @@ -32714,7 +32714,7 @@ design: (work@sky130_fd_sc_hd__a221o) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a221o.A1), line:37:5, endln:37:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a221o (work@sky130_fd_sc_hd__a221o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a221o.functional.v, line:35:1, endln:63:10 + \_module_inst: work@sky130_fd_sc_hd__a221o (work@sky130_fd_sc_hd__a221o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a221o.functional.v, line:35:1, endln:63:10 |vpiTypespec: \_logic_typespec: , line:46:12, endln:46:12 |vpiName:A1 @@ -32722,7 +32722,7 @@ design: (work@sky130_fd_sc_hd__a221o) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a221o.A2), line:38:5, endln:38:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a221o (work@sky130_fd_sc_hd__a221o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a221o.functional.v, line:35:1, endln:63:10 + \_module_inst: work@sky130_fd_sc_hd__a221o (work@sky130_fd_sc_hd__a221o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a221o.functional.v, line:35:1, endln:63:10 |vpiTypespec: \_logic_typespec: , line:47:12, endln:47:12 |vpiName:A2 @@ -32730,7 +32730,7 @@ design: (work@sky130_fd_sc_hd__a221o) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a221o.B1), line:39:5, endln:39:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a221o (work@sky130_fd_sc_hd__a221o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a221o.functional.v, line:35:1, endln:63:10 + \_module_inst: work@sky130_fd_sc_hd__a221o (work@sky130_fd_sc_hd__a221o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a221o.functional.v, line:35:1, endln:63:10 |vpiTypespec: \_logic_typespec: , line:48:12, endln:48:12 |vpiName:B1 @@ -32738,7 +32738,7 @@ design: (work@sky130_fd_sc_hd__a221o) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a221o.B2), line:40:5, endln:40:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a221o (work@sky130_fd_sc_hd__a221o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a221o.functional.v, line:35:1, endln:63:10 + \_module_inst: work@sky130_fd_sc_hd__a221o (work@sky130_fd_sc_hd__a221o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a221o.functional.v, line:35:1, endln:63:10 |vpiTypespec: \_logic_typespec: , line:49:12, endln:49:12 |vpiName:B2 @@ -32746,7 +32746,7 @@ design: (work@sky130_fd_sc_hd__a221o) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a221o.C1), line:41:5, endln:41:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a221o (work@sky130_fd_sc_hd__a221o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a221o.functional.v, line:35:1, endln:63:10 + \_module_inst: work@sky130_fd_sc_hd__a221o (work@sky130_fd_sc_hd__a221o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a221o.functional.v, line:35:1, endln:63:10 |vpiTypespec: \_logic_typespec: , line:50:12, endln:50:12 |vpiName:C1 @@ -32755,7 +32755,7 @@ design: (work@sky130_fd_sc_hd__a221o) |vpiPort: \_port: (X), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__a221o (work@sky130_fd_sc_hd__a221o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a221o.functional.v, line:35:1, endln:63:10 + \_module_inst: work@sky130_fd_sc_hd__a221o (work@sky130_fd_sc_hd__a221o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a221o.functional.v, line:35:1, endln:63:10 |vpiName:X |vpiDirection:2 |vpiLowConn: @@ -32769,7 +32769,7 @@ design: (work@sky130_fd_sc_hd__a221o) |vpiPort: \_port: (A1), line:37:5, endln:37:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a221o (work@sky130_fd_sc_hd__a221o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a221o.functional.v, line:35:1, endln:63:10 + \_module_inst: work@sky130_fd_sc_hd__a221o (work@sky130_fd_sc_hd__a221o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a221o.functional.v, line:35:1, endln:63:10 |vpiName:A1 |vpiDirection:1 |vpiLowConn: @@ -32783,7 +32783,7 @@ design: (work@sky130_fd_sc_hd__a221o) |vpiPort: \_port: (A2), line:38:5, endln:38:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a221o (work@sky130_fd_sc_hd__a221o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a221o.functional.v, line:35:1, endln:63:10 + \_module_inst: work@sky130_fd_sc_hd__a221o (work@sky130_fd_sc_hd__a221o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a221o.functional.v, line:35:1, endln:63:10 |vpiName:A2 |vpiDirection:1 |vpiLowConn: @@ -32797,7 +32797,7 @@ design: (work@sky130_fd_sc_hd__a221o) |vpiPort: \_port: (B1), line:39:5, endln:39:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a221o (work@sky130_fd_sc_hd__a221o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a221o.functional.v, line:35:1, endln:63:10 + \_module_inst: work@sky130_fd_sc_hd__a221o (work@sky130_fd_sc_hd__a221o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a221o.functional.v, line:35:1, endln:63:10 |vpiName:B1 |vpiDirection:1 |vpiLowConn: @@ -32811,7 +32811,7 @@ design: (work@sky130_fd_sc_hd__a221o) |vpiPort: \_port: (B2), line:40:5, endln:40:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a221o (work@sky130_fd_sc_hd__a221o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a221o.functional.v, line:35:1, endln:63:10 + \_module_inst: work@sky130_fd_sc_hd__a221o (work@sky130_fd_sc_hd__a221o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a221o.functional.v, line:35:1, endln:63:10 |vpiName:B2 |vpiDirection:1 |vpiLowConn: @@ -32825,7 +32825,7 @@ design: (work@sky130_fd_sc_hd__a221o) |vpiPort: \_port: (C1), line:41:5, endln:41:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a221o (work@sky130_fd_sc_hd__a221o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a221o.functional.v, line:35:1, endln:63:10 + \_module_inst: work@sky130_fd_sc_hd__a221o (work@sky130_fd_sc_hd__a221o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a221o.functional.v, line:35:1, endln:63:10 |vpiName:C1 |vpiDirection:1 |vpiLowConn: @@ -32839,7 +32839,7 @@ design: (work@sky130_fd_sc_hd__a221o) |vpiPrimitive: \_gate: work@and (work@sky130_fd_sc_hd__a221o.and0), line:58:9, endln:58:49 |vpiParent: - \_module: work@sky130_fd_sc_hd__a221o (work@sky130_fd_sc_hd__a221o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a221o.functional.v, line:35:1, endln:63:10 + \_module_inst: work@sky130_fd_sc_hd__a221o (work@sky130_fd_sc_hd__a221o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a221o.functional.v, line:35:1, endln:63:10 |vpiDefName:work@and |vpiName:and0 |vpiFullName:work@sky130_fd_sc_hd__a221o.and0 @@ -32888,7 +32888,7 @@ design: (work@sky130_fd_sc_hd__a221o) |vpiPrimitive: \_gate: work@and (work@sky130_fd_sc_hd__a221o.and1), line:59:9, endln:59:49 |vpiParent: - \_module: work@sky130_fd_sc_hd__a221o (work@sky130_fd_sc_hd__a221o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a221o.functional.v, line:35:1, endln:63:10 + \_module_inst: work@sky130_fd_sc_hd__a221o (work@sky130_fd_sc_hd__a221o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a221o.functional.v, line:35:1, endln:63:10 |vpiDefName:work@and |vpiName:and1 |vpiFullName:work@sky130_fd_sc_hd__a221o.and1 @@ -32937,7 +32937,7 @@ design: (work@sky130_fd_sc_hd__a221o) |vpiPrimitive: \_gate: work@or (work@sky130_fd_sc_hd__a221o.or0), line:60:9, endln:60:49 |vpiParent: - \_module: work@sky130_fd_sc_hd__a221o (work@sky130_fd_sc_hd__a221o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a221o.functional.v, line:35:1, endln:63:10 + \_module_inst: work@sky130_fd_sc_hd__a221o (work@sky130_fd_sc_hd__a221o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a221o.functional.v, line:35:1, endln:63:10 |vpiDefName:work@or |vpiName:or0 |vpiFullName:work@sky130_fd_sc_hd__a221o.or0 @@ -33000,7 +33000,7 @@ design: (work@sky130_fd_sc_hd__a221o) |vpiPrimitive: \_gate: work@buf (work@sky130_fd_sc_hd__a221o.buf0), line:61:9, endln:61:49 |vpiParent: - \_module: work@sky130_fd_sc_hd__a221o (work@sky130_fd_sc_hd__a221o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a221o.functional.v, line:35:1, endln:63:10 + \_module_inst: work@sky130_fd_sc_hd__a221o (work@sky130_fd_sc_hd__a221o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a221o.functional.v, line:35:1, endln:63:10 |vpiDefName:work@buf |vpiName:buf0 |vpiFullName:work@sky130_fd_sc_hd__a221o.buf0 @@ -33043,7 +33043,7 @@ Processing: -cd cells/cells -DUNIT_DELAY -writepp -parse -nocache -nobuiltin -no design: (work@sky130_fd_sc_hd__and4) |vpiName:work@sky130_fd_sc_hd__and4 |uhdmallModules: -\_module: work@sky130_fd_sc_hd__and4 (work@sky130_fd_sc_hd__and4), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and4.functional.v, line:33:1, endln:55:10 +\_module_inst: work@sky130_fd_sc_hd__and4 (work@sky130_fd_sc_hd__and4), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and4.functional.v, line:33:1, endln:55:10 |vpiParent: \_design: (work@sky130_fd_sc_hd__and4) |vpiFullName:work@sky130_fd_sc_hd__and4 @@ -33051,44 +33051,44 @@ design: (work@sky130_fd_sc_hd__and4) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__and4.and0_out_X), line:49:10, endln:49:20 |vpiParent: - \_module: work@sky130_fd_sc_hd__and4 (work@sky130_fd_sc_hd__and4), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and4.functional.v, line:33:1, endln:55:10 + \_module_inst: work@sky130_fd_sc_hd__and4 (work@sky130_fd_sc_hd__and4), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and4.functional.v, line:33:1, endln:55:10 |vpiName:and0_out_X |vpiFullName:work@sky130_fd_sc_hd__and4.and0_out_X |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__and4.X), line:34:5, endln:34:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__and4 (work@sky130_fd_sc_hd__and4), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and4.functional.v, line:33:1, endln:55:10 + \_module_inst: work@sky130_fd_sc_hd__and4 (work@sky130_fd_sc_hd__and4), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and4.functional.v, line:33:1, endln:55:10 |vpiName:X |vpiFullName:work@sky130_fd_sc_hd__and4.X |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__and4.A), line:35:5, endln:35:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__and4 (work@sky130_fd_sc_hd__and4), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and4.functional.v, line:33:1, endln:55:10 + \_module_inst: work@sky130_fd_sc_hd__and4 (work@sky130_fd_sc_hd__and4), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and4.functional.v, line:33:1, endln:55:10 |vpiName:A |vpiFullName:work@sky130_fd_sc_hd__and4.A |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__and4.B), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__and4 (work@sky130_fd_sc_hd__and4), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and4.functional.v, line:33:1, endln:55:10 + \_module_inst: work@sky130_fd_sc_hd__and4 (work@sky130_fd_sc_hd__and4), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and4.functional.v, line:33:1, endln:55:10 |vpiName:B |vpiFullName:work@sky130_fd_sc_hd__and4.B |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__and4.C), line:37:5, endln:37:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__and4 (work@sky130_fd_sc_hd__and4), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and4.functional.v, line:33:1, endln:55:10 + \_module_inst: work@sky130_fd_sc_hd__and4 (work@sky130_fd_sc_hd__and4), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and4.functional.v, line:33:1, endln:55:10 |vpiName:C |vpiFullName:work@sky130_fd_sc_hd__and4.C |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__and4.D), line:38:5, endln:38:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__and4 (work@sky130_fd_sc_hd__and4), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and4.functional.v, line:33:1, endln:55:10 + \_module_inst: work@sky130_fd_sc_hd__and4 (work@sky130_fd_sc_hd__and4), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and4.functional.v, line:33:1, endln:55:10 |vpiName:D |vpiFullName:work@sky130_fd_sc_hd__and4.D |vpiPort: \_port: (X), line:34:5, endln:34:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__and4 (work@sky130_fd_sc_hd__and4), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and4.functional.v, line:33:1, endln:55:10 + \_module_inst: work@sky130_fd_sc_hd__and4 (work@sky130_fd_sc_hd__and4), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and4.functional.v, line:33:1, endln:55:10 |vpiName:X |vpiDirection:2 |vpiLowConn: @@ -33100,7 +33100,7 @@ design: (work@sky130_fd_sc_hd__and4) |vpiPort: \_port: (A), line:35:5, endln:35:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__and4 (work@sky130_fd_sc_hd__and4), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and4.functional.v, line:33:1, endln:55:10 + \_module_inst: work@sky130_fd_sc_hd__and4 (work@sky130_fd_sc_hd__and4), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and4.functional.v, line:33:1, endln:55:10 |vpiName:A |vpiDirection:1 |vpiLowConn: @@ -33112,7 +33112,7 @@ design: (work@sky130_fd_sc_hd__and4) |vpiPort: \_port: (B), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__and4 (work@sky130_fd_sc_hd__and4), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and4.functional.v, line:33:1, endln:55:10 + \_module_inst: work@sky130_fd_sc_hd__and4 (work@sky130_fd_sc_hd__and4), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and4.functional.v, line:33:1, endln:55:10 |vpiName:B |vpiDirection:1 |vpiLowConn: @@ -33124,7 +33124,7 @@ design: (work@sky130_fd_sc_hd__and4) |vpiPort: \_port: (C), line:37:5, endln:37:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__and4 (work@sky130_fd_sc_hd__and4), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and4.functional.v, line:33:1, endln:55:10 + \_module_inst: work@sky130_fd_sc_hd__and4 (work@sky130_fd_sc_hd__and4), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and4.functional.v, line:33:1, endln:55:10 |vpiName:C |vpiDirection:1 |vpiLowConn: @@ -33136,7 +33136,7 @@ design: (work@sky130_fd_sc_hd__and4) |vpiPort: \_port: (D), line:38:5, endln:38:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__and4 (work@sky130_fd_sc_hd__and4), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and4.functional.v, line:33:1, endln:55:10 + \_module_inst: work@sky130_fd_sc_hd__and4 (work@sky130_fd_sc_hd__and4), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and4.functional.v, line:33:1, endln:55:10 |vpiName:D |vpiDirection:1 |vpiLowConn: @@ -33146,14 +33146,14 @@ design: (work@sky130_fd_sc_hd__and4) |vpiTypedef: \_logic_typespec: , line:46:12, endln:46:12 |uhdmtopModules: -\_module: work@sky130_fd_sc_hd__and4 (work@sky130_fd_sc_hd__and4), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and4.functional.v, line:33:1, endln:55:10 +\_module_inst: work@sky130_fd_sc_hd__and4 (work@sky130_fd_sc_hd__and4), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and4.functional.v, line:33:1, endln:55:10 |vpiName:work@sky130_fd_sc_hd__and4 |vpiDefName:work@sky130_fd_sc_hd__and4 |vpiTop:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__and4.and0_out_X), line:49:10, endln:49:20 |vpiParent: - \_module: work@sky130_fd_sc_hd__and4 (work@sky130_fd_sc_hd__and4), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and4.functional.v, line:33:1, endln:55:10 + \_module_inst: work@sky130_fd_sc_hd__and4 (work@sky130_fd_sc_hd__and4), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and4.functional.v, line:33:1, endln:55:10 |vpiTypespec: \_logic_typespec: , line:49:5, endln:49:9 |vpiName:and0_out_X @@ -33162,7 +33162,7 @@ design: (work@sky130_fd_sc_hd__and4) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__and4.X), line:34:5, endln:34:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__and4 (work@sky130_fd_sc_hd__and4), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and4.functional.v, line:33:1, endln:55:10 + \_module_inst: work@sky130_fd_sc_hd__and4 (work@sky130_fd_sc_hd__and4), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and4.functional.v, line:33:1, endln:55:10 |vpiTypespec: \_logic_typespec: , line:42:12, endln:42:12 |vpiName:X @@ -33170,7 +33170,7 @@ design: (work@sky130_fd_sc_hd__and4) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__and4.A), line:35:5, endln:35:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__and4 (work@sky130_fd_sc_hd__and4), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and4.functional.v, line:33:1, endln:55:10 + \_module_inst: work@sky130_fd_sc_hd__and4 (work@sky130_fd_sc_hd__and4), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and4.functional.v, line:33:1, endln:55:10 |vpiTypespec: \_logic_typespec: , line:43:12, endln:43:12 |vpiName:A @@ -33178,7 +33178,7 @@ design: (work@sky130_fd_sc_hd__and4) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__and4.B), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__and4 (work@sky130_fd_sc_hd__and4), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and4.functional.v, line:33:1, endln:55:10 + \_module_inst: work@sky130_fd_sc_hd__and4 (work@sky130_fd_sc_hd__and4), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and4.functional.v, line:33:1, endln:55:10 |vpiTypespec: \_logic_typespec: , line:44:12, endln:44:12 |vpiName:B @@ -33186,7 +33186,7 @@ design: (work@sky130_fd_sc_hd__and4) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__and4.C), line:37:5, endln:37:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__and4 (work@sky130_fd_sc_hd__and4), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and4.functional.v, line:33:1, endln:55:10 + \_module_inst: work@sky130_fd_sc_hd__and4 (work@sky130_fd_sc_hd__and4), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and4.functional.v, line:33:1, endln:55:10 |vpiTypespec: \_logic_typespec: , line:45:12, endln:45:12 |vpiName:C @@ -33194,7 +33194,7 @@ design: (work@sky130_fd_sc_hd__and4) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__and4.D), line:38:5, endln:38:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__and4 (work@sky130_fd_sc_hd__and4), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and4.functional.v, line:33:1, endln:55:10 + \_module_inst: work@sky130_fd_sc_hd__and4 (work@sky130_fd_sc_hd__and4), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and4.functional.v, line:33:1, endln:55:10 |vpiTypespec: \_logic_typespec: , line:46:12, endln:46:12 |vpiName:D @@ -33203,7 +33203,7 @@ design: (work@sky130_fd_sc_hd__and4) |vpiPort: \_port: (X), line:34:5, endln:34:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__and4 (work@sky130_fd_sc_hd__and4), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and4.functional.v, line:33:1, endln:55:10 + \_module_inst: work@sky130_fd_sc_hd__and4 (work@sky130_fd_sc_hd__and4), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and4.functional.v, line:33:1, endln:55:10 |vpiName:X |vpiDirection:2 |vpiLowConn: @@ -33217,7 +33217,7 @@ design: (work@sky130_fd_sc_hd__and4) |vpiPort: \_port: (A), line:35:5, endln:35:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__and4 (work@sky130_fd_sc_hd__and4), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and4.functional.v, line:33:1, endln:55:10 + \_module_inst: work@sky130_fd_sc_hd__and4 (work@sky130_fd_sc_hd__and4), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and4.functional.v, line:33:1, endln:55:10 |vpiName:A |vpiDirection:1 |vpiLowConn: @@ -33231,7 +33231,7 @@ design: (work@sky130_fd_sc_hd__and4) |vpiPort: \_port: (B), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__and4 (work@sky130_fd_sc_hd__and4), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and4.functional.v, line:33:1, endln:55:10 + \_module_inst: work@sky130_fd_sc_hd__and4 (work@sky130_fd_sc_hd__and4), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and4.functional.v, line:33:1, endln:55:10 |vpiName:B |vpiDirection:1 |vpiLowConn: @@ -33245,7 +33245,7 @@ design: (work@sky130_fd_sc_hd__and4) |vpiPort: \_port: (C), line:37:5, endln:37:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__and4 (work@sky130_fd_sc_hd__and4), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and4.functional.v, line:33:1, endln:55:10 + \_module_inst: work@sky130_fd_sc_hd__and4 (work@sky130_fd_sc_hd__and4), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and4.functional.v, line:33:1, endln:55:10 |vpiName:C |vpiDirection:1 |vpiLowConn: @@ -33259,7 +33259,7 @@ design: (work@sky130_fd_sc_hd__and4) |vpiPort: \_port: (D), line:38:5, endln:38:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__and4 (work@sky130_fd_sc_hd__and4), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and4.functional.v, line:33:1, endln:55:10 + \_module_inst: work@sky130_fd_sc_hd__and4 (work@sky130_fd_sc_hd__and4), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and4.functional.v, line:33:1, endln:55:10 |vpiName:D |vpiDirection:1 |vpiLowConn: @@ -33273,7 +33273,7 @@ design: (work@sky130_fd_sc_hd__and4) |vpiPrimitive: \_gate: work@and (work@sky130_fd_sc_hd__and4.and0), line:52:9, endln:52:43 |vpiParent: - \_module: work@sky130_fd_sc_hd__and4 (work@sky130_fd_sc_hd__and4), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and4.functional.v, line:33:1, endln:55:10 + \_module_inst: work@sky130_fd_sc_hd__and4 (work@sky130_fd_sc_hd__and4), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and4.functional.v, line:33:1, endln:55:10 |vpiDefName:work@and |vpiName:and0 |vpiFullName:work@sky130_fd_sc_hd__and4.and0 @@ -33350,7 +33350,7 @@ design: (work@sky130_fd_sc_hd__and4) |vpiPrimitive: \_gate: work@buf (work@sky130_fd_sc_hd__and4.buf0), line:53:9, endln:53:43 |vpiParent: - \_module: work@sky130_fd_sc_hd__and4 (work@sky130_fd_sc_hd__and4), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and4.functional.v, line:33:1, endln:55:10 + \_module_inst: work@sky130_fd_sc_hd__and4 (work@sky130_fd_sc_hd__and4), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and4.functional.v, line:33:1, endln:55:10 |vpiDefName:work@buf |vpiName:buf0 |vpiFullName:work@sky130_fd_sc_hd__and4.buf0 @@ -33393,7 +33393,7 @@ Processing: -cd cells/cells -DUNIT_DELAY -writepp -parse -nocache -nobuiltin -no design: (work@sky130_fd_sc_hd__lpflow_inputiso0p) |vpiName:work@sky130_fd_sc_hd__lpflow_inputiso0p |uhdmallModules: -\_module: work@sky130_fd_sc_hd__lpflow_inputiso0p (work@sky130_fd_sc_hd__lpflow_inputiso0p), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_inputiso0p.functional.v, line:35:1, endln:53:10 +\_module_inst: work@sky130_fd_sc_hd__lpflow_inputiso0p (work@sky130_fd_sc_hd__lpflow_inputiso0p), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_inputiso0p.functional.v, line:35:1, endln:53:10 |vpiParent: \_design: (work@sky130_fd_sc_hd__lpflow_inputiso0p) |vpiFullName:work@sky130_fd_sc_hd__lpflow_inputiso0p @@ -33401,32 +33401,32 @@ design: (work@sky130_fd_sc_hd__lpflow_inputiso0p) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__lpflow_inputiso0p.sleepn), line:47:10, endln:47:16 |vpiParent: - \_module: work@sky130_fd_sc_hd__lpflow_inputiso0p (work@sky130_fd_sc_hd__lpflow_inputiso0p), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_inputiso0p.functional.v, line:35:1, endln:53:10 + \_module_inst: work@sky130_fd_sc_hd__lpflow_inputiso0p (work@sky130_fd_sc_hd__lpflow_inputiso0p), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_inputiso0p.functional.v, line:35:1, endln:53:10 |vpiName:sleepn |vpiFullName:work@sky130_fd_sc_hd__lpflow_inputiso0p.sleepn |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__lpflow_inputiso0p.X), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__lpflow_inputiso0p (work@sky130_fd_sc_hd__lpflow_inputiso0p), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_inputiso0p.functional.v, line:35:1, endln:53:10 + \_module_inst: work@sky130_fd_sc_hd__lpflow_inputiso0p (work@sky130_fd_sc_hd__lpflow_inputiso0p), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_inputiso0p.functional.v, line:35:1, endln:53:10 |vpiName:X |vpiFullName:work@sky130_fd_sc_hd__lpflow_inputiso0p.X |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__lpflow_inputiso0p.A), line:37:5, endln:37:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__lpflow_inputiso0p (work@sky130_fd_sc_hd__lpflow_inputiso0p), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_inputiso0p.functional.v, line:35:1, endln:53:10 + \_module_inst: work@sky130_fd_sc_hd__lpflow_inputiso0p (work@sky130_fd_sc_hd__lpflow_inputiso0p), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_inputiso0p.functional.v, line:35:1, endln:53:10 |vpiName:A |vpiFullName:work@sky130_fd_sc_hd__lpflow_inputiso0p.A |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__lpflow_inputiso0p.SLEEP), line:38:5, endln:38:10 |vpiParent: - \_module: work@sky130_fd_sc_hd__lpflow_inputiso0p (work@sky130_fd_sc_hd__lpflow_inputiso0p), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_inputiso0p.functional.v, line:35:1, endln:53:10 + \_module_inst: work@sky130_fd_sc_hd__lpflow_inputiso0p (work@sky130_fd_sc_hd__lpflow_inputiso0p), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_inputiso0p.functional.v, line:35:1, endln:53:10 |vpiName:SLEEP |vpiFullName:work@sky130_fd_sc_hd__lpflow_inputiso0p.SLEEP |vpiPort: \_port: (X), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__lpflow_inputiso0p (work@sky130_fd_sc_hd__lpflow_inputiso0p), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_inputiso0p.functional.v, line:35:1, endln:53:10 + \_module_inst: work@sky130_fd_sc_hd__lpflow_inputiso0p (work@sky130_fd_sc_hd__lpflow_inputiso0p), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_inputiso0p.functional.v, line:35:1, endln:53:10 |vpiName:X |vpiDirection:2 |vpiLowConn: @@ -33438,7 +33438,7 @@ design: (work@sky130_fd_sc_hd__lpflow_inputiso0p) |vpiPort: \_port: (A), line:37:5, endln:37:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__lpflow_inputiso0p (work@sky130_fd_sc_hd__lpflow_inputiso0p), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_inputiso0p.functional.v, line:35:1, endln:53:10 + \_module_inst: work@sky130_fd_sc_hd__lpflow_inputiso0p (work@sky130_fd_sc_hd__lpflow_inputiso0p), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_inputiso0p.functional.v, line:35:1, endln:53:10 |vpiName:A |vpiDirection:1 |vpiLowConn: @@ -33450,7 +33450,7 @@ design: (work@sky130_fd_sc_hd__lpflow_inputiso0p) |vpiPort: \_port: (SLEEP), line:38:5, endln:38:10 |vpiParent: - \_module: work@sky130_fd_sc_hd__lpflow_inputiso0p (work@sky130_fd_sc_hd__lpflow_inputiso0p), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_inputiso0p.functional.v, line:35:1, endln:53:10 + \_module_inst: work@sky130_fd_sc_hd__lpflow_inputiso0p (work@sky130_fd_sc_hd__lpflow_inputiso0p), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_inputiso0p.functional.v, line:35:1, endln:53:10 |vpiName:SLEEP |vpiDirection:1 |vpiLowConn: @@ -33460,14 +33460,14 @@ design: (work@sky130_fd_sc_hd__lpflow_inputiso0p) |vpiTypedef: \_logic_typespec: , line:44:12, endln:44:12 |uhdmtopModules: -\_module: work@sky130_fd_sc_hd__lpflow_inputiso0p (work@sky130_fd_sc_hd__lpflow_inputiso0p), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_inputiso0p.functional.v, line:35:1, endln:53:10 +\_module_inst: work@sky130_fd_sc_hd__lpflow_inputiso0p (work@sky130_fd_sc_hd__lpflow_inputiso0p), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_inputiso0p.functional.v, line:35:1, endln:53:10 |vpiName:work@sky130_fd_sc_hd__lpflow_inputiso0p |vpiDefName:work@sky130_fd_sc_hd__lpflow_inputiso0p |vpiTop:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__lpflow_inputiso0p.sleepn), line:47:10, endln:47:16 |vpiParent: - \_module: work@sky130_fd_sc_hd__lpflow_inputiso0p (work@sky130_fd_sc_hd__lpflow_inputiso0p), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_inputiso0p.functional.v, line:35:1, endln:53:10 + \_module_inst: work@sky130_fd_sc_hd__lpflow_inputiso0p (work@sky130_fd_sc_hd__lpflow_inputiso0p), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_inputiso0p.functional.v, line:35:1, endln:53:10 |vpiTypespec: \_logic_typespec: , line:47:5, endln:47:9 |vpiName:sleepn @@ -33476,7 +33476,7 @@ design: (work@sky130_fd_sc_hd__lpflow_inputiso0p) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__lpflow_inputiso0p.X), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__lpflow_inputiso0p (work@sky130_fd_sc_hd__lpflow_inputiso0p), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_inputiso0p.functional.v, line:35:1, endln:53:10 + \_module_inst: work@sky130_fd_sc_hd__lpflow_inputiso0p (work@sky130_fd_sc_hd__lpflow_inputiso0p), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_inputiso0p.functional.v, line:35:1, endln:53:10 |vpiTypespec: \_logic_typespec: , line:42:12, endln:42:12 |vpiName:X @@ -33484,7 +33484,7 @@ design: (work@sky130_fd_sc_hd__lpflow_inputiso0p) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__lpflow_inputiso0p.A), line:37:5, endln:37:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__lpflow_inputiso0p (work@sky130_fd_sc_hd__lpflow_inputiso0p), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_inputiso0p.functional.v, line:35:1, endln:53:10 + \_module_inst: work@sky130_fd_sc_hd__lpflow_inputiso0p (work@sky130_fd_sc_hd__lpflow_inputiso0p), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_inputiso0p.functional.v, line:35:1, endln:53:10 |vpiTypespec: \_logic_typespec: , line:43:12, endln:43:12 |vpiName:A @@ -33492,7 +33492,7 @@ design: (work@sky130_fd_sc_hd__lpflow_inputiso0p) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__lpflow_inputiso0p.SLEEP), line:38:5, endln:38:10 |vpiParent: - \_module: work@sky130_fd_sc_hd__lpflow_inputiso0p (work@sky130_fd_sc_hd__lpflow_inputiso0p), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_inputiso0p.functional.v, line:35:1, endln:53:10 + \_module_inst: work@sky130_fd_sc_hd__lpflow_inputiso0p (work@sky130_fd_sc_hd__lpflow_inputiso0p), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_inputiso0p.functional.v, line:35:1, endln:53:10 |vpiTypespec: \_logic_typespec: , line:44:12, endln:44:12 |vpiName:SLEEP @@ -33501,7 +33501,7 @@ design: (work@sky130_fd_sc_hd__lpflow_inputiso0p) |vpiPort: \_port: (X), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__lpflow_inputiso0p (work@sky130_fd_sc_hd__lpflow_inputiso0p), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_inputiso0p.functional.v, line:35:1, endln:53:10 + \_module_inst: work@sky130_fd_sc_hd__lpflow_inputiso0p (work@sky130_fd_sc_hd__lpflow_inputiso0p), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_inputiso0p.functional.v, line:35:1, endln:53:10 |vpiName:X |vpiDirection:2 |vpiLowConn: @@ -33515,7 +33515,7 @@ design: (work@sky130_fd_sc_hd__lpflow_inputiso0p) |vpiPort: \_port: (A), line:37:5, endln:37:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__lpflow_inputiso0p (work@sky130_fd_sc_hd__lpflow_inputiso0p), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_inputiso0p.functional.v, line:35:1, endln:53:10 + \_module_inst: work@sky130_fd_sc_hd__lpflow_inputiso0p (work@sky130_fd_sc_hd__lpflow_inputiso0p), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_inputiso0p.functional.v, line:35:1, endln:53:10 |vpiName:A |vpiDirection:1 |vpiLowConn: @@ -33529,7 +33529,7 @@ design: (work@sky130_fd_sc_hd__lpflow_inputiso0p) |vpiPort: \_port: (SLEEP), line:38:5, endln:38:10 |vpiParent: - \_module: work@sky130_fd_sc_hd__lpflow_inputiso0p (work@sky130_fd_sc_hd__lpflow_inputiso0p), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_inputiso0p.functional.v, line:35:1, endln:53:10 + \_module_inst: work@sky130_fd_sc_hd__lpflow_inputiso0p (work@sky130_fd_sc_hd__lpflow_inputiso0p), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_inputiso0p.functional.v, line:35:1, endln:53:10 |vpiName:SLEEP |vpiDirection:1 |vpiLowConn: @@ -33543,7 +33543,7 @@ design: (work@sky130_fd_sc_hd__lpflow_inputiso0p) |vpiPrimitive: \_gate: work@not (work@sky130_fd_sc_hd__lpflow_inputiso0p.not0), line:50:9, endln:50:39 |vpiParent: - \_module: work@sky130_fd_sc_hd__lpflow_inputiso0p (work@sky130_fd_sc_hd__lpflow_inputiso0p), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_inputiso0p.functional.v, line:35:1, endln:53:10 + \_module_inst: work@sky130_fd_sc_hd__lpflow_inputiso0p (work@sky130_fd_sc_hd__lpflow_inputiso0p), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_inputiso0p.functional.v, line:35:1, endln:53:10 |vpiDefName:work@not |vpiName:not0 |vpiFullName:work@sky130_fd_sc_hd__lpflow_inputiso0p.not0 @@ -33578,7 +33578,7 @@ design: (work@sky130_fd_sc_hd__lpflow_inputiso0p) |vpiPrimitive: \_gate: work@and (work@sky130_fd_sc_hd__lpflow_inputiso0p.and0), line:51:9, endln:51:39 |vpiParent: - \_module: work@sky130_fd_sc_hd__lpflow_inputiso0p (work@sky130_fd_sc_hd__lpflow_inputiso0p), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_inputiso0p.functional.v, line:35:1, endln:53:10 + \_module_inst: work@sky130_fd_sc_hd__lpflow_inputiso0p (work@sky130_fd_sc_hd__lpflow_inputiso0p), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_inputiso0p.functional.v, line:35:1, endln:53:10 |vpiDefName:work@and |vpiName:and0 |vpiFullName:work@sky130_fd_sc_hd__lpflow_inputiso0p.and0 @@ -33635,7 +33635,7 @@ Processing: -cd cells/cells -DUNIT_DELAY -writepp -parse -nocache -nobuiltin -no design: (work@sky130_fd_sc_hd__buf) |vpiName:work@sky130_fd_sc_hd__buf |uhdmallModules: -\_module: work@sky130_fd_sc_hd__buf (work@sky130_fd_sc_hd__buf), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__buf.functional.v, line:33:1, endln:49:10 +\_module_inst: work@sky130_fd_sc_hd__buf (work@sky130_fd_sc_hd__buf), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__buf.functional.v, line:33:1, endln:49:10 |vpiParent: \_design: (work@sky130_fd_sc_hd__buf) |vpiFullName:work@sky130_fd_sc_hd__buf @@ -33643,26 +33643,26 @@ design: (work@sky130_fd_sc_hd__buf) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__buf.buf0_out_X), line:43:10, endln:43:20 |vpiParent: - \_module: work@sky130_fd_sc_hd__buf (work@sky130_fd_sc_hd__buf), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__buf.functional.v, line:33:1, endln:49:10 + \_module_inst: work@sky130_fd_sc_hd__buf (work@sky130_fd_sc_hd__buf), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__buf.functional.v, line:33:1, endln:49:10 |vpiName:buf0_out_X |vpiFullName:work@sky130_fd_sc_hd__buf.buf0_out_X |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__buf.X), line:34:5, endln:34:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__buf (work@sky130_fd_sc_hd__buf), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__buf.functional.v, line:33:1, endln:49:10 + \_module_inst: work@sky130_fd_sc_hd__buf (work@sky130_fd_sc_hd__buf), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__buf.functional.v, line:33:1, endln:49:10 |vpiName:X |vpiFullName:work@sky130_fd_sc_hd__buf.X |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__buf.A), line:35:5, endln:35:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__buf (work@sky130_fd_sc_hd__buf), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__buf.functional.v, line:33:1, endln:49:10 + \_module_inst: work@sky130_fd_sc_hd__buf (work@sky130_fd_sc_hd__buf), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__buf.functional.v, line:33:1, endln:49:10 |vpiName:A |vpiFullName:work@sky130_fd_sc_hd__buf.A |vpiPort: \_port: (X), line:34:5, endln:34:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__buf (work@sky130_fd_sc_hd__buf), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__buf.functional.v, line:33:1, endln:49:10 + \_module_inst: work@sky130_fd_sc_hd__buf (work@sky130_fd_sc_hd__buf), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__buf.functional.v, line:33:1, endln:49:10 |vpiName:X |vpiDirection:2 |vpiLowConn: @@ -33674,7 +33674,7 @@ design: (work@sky130_fd_sc_hd__buf) |vpiPort: \_port: (A), line:35:5, endln:35:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__buf (work@sky130_fd_sc_hd__buf), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__buf.functional.v, line:33:1, endln:49:10 + \_module_inst: work@sky130_fd_sc_hd__buf (work@sky130_fd_sc_hd__buf), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__buf.functional.v, line:33:1, endln:49:10 |vpiName:A |vpiDirection:1 |vpiLowConn: @@ -33684,14 +33684,14 @@ design: (work@sky130_fd_sc_hd__buf) |vpiTypedef: \_logic_typespec: , line:40:12, endln:40:12 |uhdmtopModules: -\_module: work@sky130_fd_sc_hd__buf (work@sky130_fd_sc_hd__buf), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__buf.functional.v, line:33:1, endln:49:10 +\_module_inst: work@sky130_fd_sc_hd__buf (work@sky130_fd_sc_hd__buf), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__buf.functional.v, line:33:1, endln:49:10 |vpiName:work@sky130_fd_sc_hd__buf |vpiDefName:work@sky130_fd_sc_hd__buf |vpiTop:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__buf.buf0_out_X), line:43:10, endln:43:20 |vpiParent: - \_module: work@sky130_fd_sc_hd__buf (work@sky130_fd_sc_hd__buf), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__buf.functional.v, line:33:1, endln:49:10 + \_module_inst: work@sky130_fd_sc_hd__buf (work@sky130_fd_sc_hd__buf), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__buf.functional.v, line:33:1, endln:49:10 |vpiTypespec: \_logic_typespec: , line:43:5, endln:43:9 |vpiName:buf0_out_X @@ -33700,7 +33700,7 @@ design: (work@sky130_fd_sc_hd__buf) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__buf.X), line:34:5, endln:34:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__buf (work@sky130_fd_sc_hd__buf), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__buf.functional.v, line:33:1, endln:49:10 + \_module_inst: work@sky130_fd_sc_hd__buf (work@sky130_fd_sc_hd__buf), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__buf.functional.v, line:33:1, endln:49:10 |vpiTypespec: \_logic_typespec: , line:39:12, endln:39:12 |vpiName:X @@ -33708,7 +33708,7 @@ design: (work@sky130_fd_sc_hd__buf) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__buf.A), line:35:5, endln:35:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__buf (work@sky130_fd_sc_hd__buf), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__buf.functional.v, line:33:1, endln:49:10 + \_module_inst: work@sky130_fd_sc_hd__buf (work@sky130_fd_sc_hd__buf), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__buf.functional.v, line:33:1, endln:49:10 |vpiTypespec: \_logic_typespec: , line:40:12, endln:40:12 |vpiName:A @@ -33717,7 +33717,7 @@ design: (work@sky130_fd_sc_hd__buf) |vpiPort: \_port: (X), line:34:5, endln:34:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__buf (work@sky130_fd_sc_hd__buf), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__buf.functional.v, line:33:1, endln:49:10 + \_module_inst: work@sky130_fd_sc_hd__buf (work@sky130_fd_sc_hd__buf), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__buf.functional.v, line:33:1, endln:49:10 |vpiName:X |vpiDirection:2 |vpiLowConn: @@ -33731,7 +33731,7 @@ design: (work@sky130_fd_sc_hd__buf) |vpiPort: \_port: (A), line:35:5, endln:35:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__buf (work@sky130_fd_sc_hd__buf), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__buf.functional.v, line:33:1, endln:49:10 + \_module_inst: work@sky130_fd_sc_hd__buf (work@sky130_fd_sc_hd__buf), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__buf.functional.v, line:33:1, endln:49:10 |vpiName:A |vpiDirection:1 |vpiLowConn: @@ -33745,7 +33745,7 @@ design: (work@sky130_fd_sc_hd__buf) |vpiPrimitive: \_gate: work@buf (work@sky130_fd_sc_hd__buf.buf0), line:46:9, endln:46:43 |vpiParent: - \_module: work@sky130_fd_sc_hd__buf (work@sky130_fd_sc_hd__buf), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__buf.functional.v, line:33:1, endln:49:10 + \_module_inst: work@sky130_fd_sc_hd__buf (work@sky130_fd_sc_hd__buf), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__buf.functional.v, line:33:1, endln:49:10 |vpiDefName:work@buf |vpiName:buf0 |vpiFullName:work@sky130_fd_sc_hd__buf.buf0 @@ -33780,7 +33780,7 @@ design: (work@sky130_fd_sc_hd__buf) |vpiPrimitive: \_gate: work@buf (work@sky130_fd_sc_hd__buf.buf1), line:47:9, endln:47:43 |vpiParent: - \_module: work@sky130_fd_sc_hd__buf (work@sky130_fd_sc_hd__buf), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__buf.functional.v, line:33:1, endln:49:10 + \_module_inst: work@sky130_fd_sc_hd__buf (work@sky130_fd_sc_hd__buf), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__buf.functional.v, line:33:1, endln:49:10 |vpiDefName:work@buf |vpiName:buf1 |vpiFullName:work@sky130_fd_sc_hd__buf.buf1 @@ -33823,7 +33823,7 @@ Processing: -cd cells/cells -DUNIT_DELAY -writepp -parse -nocache -nobuiltin -no design: (work@sky130_fd_sc_hd__o21a) |vpiName:work@sky130_fd_sc_hd__o21a |uhdmallModules: -\_module: work@sky130_fd_sc_hd__o21a (work@sky130_fd_sc_hd__o21a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o21a.functional.v, line:35:1, endln:57:10 +\_module_inst: work@sky130_fd_sc_hd__o21a (work@sky130_fd_sc_hd__o21a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o21a.functional.v, line:35:1, endln:57:10 |vpiParent: \_design: (work@sky130_fd_sc_hd__o21a) |vpiFullName:work@sky130_fd_sc_hd__o21a @@ -33831,45 +33831,45 @@ design: (work@sky130_fd_sc_hd__o21a) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o21a.or0_out), line:49:10, endln:49:17 |vpiParent: - \_module: work@sky130_fd_sc_hd__o21a (work@sky130_fd_sc_hd__o21a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o21a.functional.v, line:35:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__o21a (work@sky130_fd_sc_hd__o21a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o21a.functional.v, line:35:1, endln:57:10 |vpiName:or0_out |vpiFullName:work@sky130_fd_sc_hd__o21a.or0_out |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o21a.and0_out_X), line:50:10, endln:50:20 |vpiParent: - \_module: work@sky130_fd_sc_hd__o21a (work@sky130_fd_sc_hd__o21a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o21a.functional.v, line:35:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__o21a (work@sky130_fd_sc_hd__o21a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o21a.functional.v, line:35:1, endln:57:10 |vpiName:and0_out_X |vpiFullName:work@sky130_fd_sc_hd__o21a.and0_out_X |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o21a.X), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__o21a (work@sky130_fd_sc_hd__o21a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o21a.functional.v, line:35:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__o21a (work@sky130_fd_sc_hd__o21a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o21a.functional.v, line:35:1, endln:57:10 |vpiName:X |vpiFullName:work@sky130_fd_sc_hd__o21a.X |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o21a.A1), line:37:5, endln:37:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o21a (work@sky130_fd_sc_hd__o21a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o21a.functional.v, line:35:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__o21a (work@sky130_fd_sc_hd__o21a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o21a.functional.v, line:35:1, endln:57:10 |vpiName:A1 |vpiFullName:work@sky130_fd_sc_hd__o21a.A1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o21a.A2), line:38:5, endln:38:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o21a (work@sky130_fd_sc_hd__o21a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o21a.functional.v, line:35:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__o21a (work@sky130_fd_sc_hd__o21a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o21a.functional.v, line:35:1, endln:57:10 |vpiName:A2 |vpiFullName:work@sky130_fd_sc_hd__o21a.A2 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o21a.B1), line:39:5, endln:39:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o21a (work@sky130_fd_sc_hd__o21a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o21a.functional.v, line:35:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__o21a (work@sky130_fd_sc_hd__o21a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o21a.functional.v, line:35:1, endln:57:10 |vpiName:B1 |vpiFullName:work@sky130_fd_sc_hd__o21a.B1 |vpiPort: \_port: (X), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__o21a (work@sky130_fd_sc_hd__o21a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o21a.functional.v, line:35:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__o21a (work@sky130_fd_sc_hd__o21a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o21a.functional.v, line:35:1, endln:57:10 |vpiName:X |vpiDirection:2 |vpiLowConn: @@ -33881,7 +33881,7 @@ design: (work@sky130_fd_sc_hd__o21a) |vpiPort: \_port: (A1), line:37:5, endln:37:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o21a (work@sky130_fd_sc_hd__o21a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o21a.functional.v, line:35:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__o21a (work@sky130_fd_sc_hd__o21a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o21a.functional.v, line:35:1, endln:57:10 |vpiName:A1 |vpiDirection:1 |vpiLowConn: @@ -33893,7 +33893,7 @@ design: (work@sky130_fd_sc_hd__o21a) |vpiPort: \_port: (A2), line:38:5, endln:38:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o21a (work@sky130_fd_sc_hd__o21a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o21a.functional.v, line:35:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__o21a (work@sky130_fd_sc_hd__o21a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o21a.functional.v, line:35:1, endln:57:10 |vpiName:A2 |vpiDirection:1 |vpiLowConn: @@ -33905,7 +33905,7 @@ design: (work@sky130_fd_sc_hd__o21a) |vpiPort: \_port: (B1), line:39:5, endln:39:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o21a (work@sky130_fd_sc_hd__o21a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o21a.functional.v, line:35:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__o21a (work@sky130_fd_sc_hd__o21a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o21a.functional.v, line:35:1, endln:57:10 |vpiName:B1 |vpiDirection:1 |vpiLowConn: @@ -33915,14 +33915,14 @@ design: (work@sky130_fd_sc_hd__o21a) |vpiTypedef: \_logic_typespec: , line:46:12, endln:46:12 |uhdmtopModules: -\_module: work@sky130_fd_sc_hd__o21a (work@sky130_fd_sc_hd__o21a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o21a.functional.v, line:35:1, endln:57:10 +\_module_inst: work@sky130_fd_sc_hd__o21a (work@sky130_fd_sc_hd__o21a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o21a.functional.v, line:35:1, endln:57:10 |vpiName:work@sky130_fd_sc_hd__o21a |vpiDefName:work@sky130_fd_sc_hd__o21a |vpiTop:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o21a.or0_out), line:49:10, endln:49:17 |vpiParent: - \_module: work@sky130_fd_sc_hd__o21a (work@sky130_fd_sc_hd__o21a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o21a.functional.v, line:35:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__o21a (work@sky130_fd_sc_hd__o21a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o21a.functional.v, line:35:1, endln:57:10 |vpiTypespec: \_logic_typespec: , line:49:5, endln:49:9 |vpiName:or0_out @@ -33931,7 +33931,7 @@ design: (work@sky130_fd_sc_hd__o21a) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o21a.and0_out_X), line:50:10, endln:50:20 |vpiParent: - \_module: work@sky130_fd_sc_hd__o21a (work@sky130_fd_sc_hd__o21a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o21a.functional.v, line:35:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__o21a (work@sky130_fd_sc_hd__o21a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o21a.functional.v, line:35:1, endln:57:10 |vpiTypespec: \_logic_typespec: , line:50:5, endln:50:9 |vpiName:and0_out_X @@ -33940,7 +33940,7 @@ design: (work@sky130_fd_sc_hd__o21a) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o21a.X), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__o21a (work@sky130_fd_sc_hd__o21a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o21a.functional.v, line:35:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__o21a (work@sky130_fd_sc_hd__o21a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o21a.functional.v, line:35:1, endln:57:10 |vpiTypespec: \_logic_typespec: , line:43:12, endln:43:12 |vpiName:X @@ -33948,7 +33948,7 @@ design: (work@sky130_fd_sc_hd__o21a) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o21a.A1), line:37:5, endln:37:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o21a (work@sky130_fd_sc_hd__o21a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o21a.functional.v, line:35:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__o21a (work@sky130_fd_sc_hd__o21a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o21a.functional.v, line:35:1, endln:57:10 |vpiTypespec: \_logic_typespec: , line:44:12, endln:44:12 |vpiName:A1 @@ -33956,7 +33956,7 @@ design: (work@sky130_fd_sc_hd__o21a) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o21a.A2), line:38:5, endln:38:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o21a (work@sky130_fd_sc_hd__o21a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o21a.functional.v, line:35:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__o21a (work@sky130_fd_sc_hd__o21a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o21a.functional.v, line:35:1, endln:57:10 |vpiTypespec: \_logic_typespec: , line:45:12, endln:45:12 |vpiName:A2 @@ -33964,7 +33964,7 @@ design: (work@sky130_fd_sc_hd__o21a) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o21a.B1), line:39:5, endln:39:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o21a (work@sky130_fd_sc_hd__o21a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o21a.functional.v, line:35:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__o21a (work@sky130_fd_sc_hd__o21a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o21a.functional.v, line:35:1, endln:57:10 |vpiTypespec: \_logic_typespec: , line:46:12, endln:46:12 |vpiName:B1 @@ -33973,7 +33973,7 @@ design: (work@sky130_fd_sc_hd__o21a) |vpiPort: \_port: (X), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__o21a (work@sky130_fd_sc_hd__o21a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o21a.functional.v, line:35:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__o21a (work@sky130_fd_sc_hd__o21a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o21a.functional.v, line:35:1, endln:57:10 |vpiName:X |vpiDirection:2 |vpiLowConn: @@ -33987,7 +33987,7 @@ design: (work@sky130_fd_sc_hd__o21a) |vpiPort: \_port: (A1), line:37:5, endln:37:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o21a (work@sky130_fd_sc_hd__o21a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o21a.functional.v, line:35:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__o21a (work@sky130_fd_sc_hd__o21a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o21a.functional.v, line:35:1, endln:57:10 |vpiName:A1 |vpiDirection:1 |vpiLowConn: @@ -34001,7 +34001,7 @@ design: (work@sky130_fd_sc_hd__o21a) |vpiPort: \_port: (A2), line:38:5, endln:38:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o21a (work@sky130_fd_sc_hd__o21a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o21a.functional.v, line:35:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__o21a (work@sky130_fd_sc_hd__o21a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o21a.functional.v, line:35:1, endln:57:10 |vpiName:A2 |vpiDirection:1 |vpiLowConn: @@ -34015,7 +34015,7 @@ design: (work@sky130_fd_sc_hd__o21a) |vpiPort: \_port: (B1), line:39:5, endln:39:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o21a (work@sky130_fd_sc_hd__o21a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o21a.functional.v, line:35:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__o21a (work@sky130_fd_sc_hd__o21a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o21a.functional.v, line:35:1, endln:57:10 |vpiName:B1 |vpiDirection:1 |vpiLowConn: @@ -34029,7 +34029,7 @@ design: (work@sky130_fd_sc_hd__o21a) |vpiPrimitive: \_gate: work@or (work@sky130_fd_sc_hd__o21a.or0), line:53:9, endln:53:43 |vpiParent: - \_module: work@sky130_fd_sc_hd__o21a (work@sky130_fd_sc_hd__o21a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o21a.functional.v, line:35:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__o21a (work@sky130_fd_sc_hd__o21a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o21a.functional.v, line:35:1, endln:57:10 |vpiDefName:work@or |vpiName:or0 |vpiFullName:work@sky130_fd_sc_hd__o21a.or0 @@ -34078,7 +34078,7 @@ design: (work@sky130_fd_sc_hd__o21a) |vpiPrimitive: \_gate: work@and (work@sky130_fd_sc_hd__o21a.and0), line:54:9, endln:54:43 |vpiParent: - \_module: work@sky130_fd_sc_hd__o21a (work@sky130_fd_sc_hd__o21a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o21a.functional.v, line:35:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__o21a (work@sky130_fd_sc_hd__o21a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o21a.functional.v, line:35:1, endln:57:10 |vpiDefName:work@and |vpiName:and0 |vpiFullName:work@sky130_fd_sc_hd__o21a.and0 @@ -34127,7 +34127,7 @@ design: (work@sky130_fd_sc_hd__o21a) |vpiPrimitive: \_gate: work@buf (work@sky130_fd_sc_hd__o21a.buf0), line:55:9, endln:55:43 |vpiParent: - \_module: work@sky130_fd_sc_hd__o21a (work@sky130_fd_sc_hd__o21a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o21a.functional.v, line:35:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__o21a (work@sky130_fd_sc_hd__o21a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o21a.functional.v, line:35:1, endln:57:10 |vpiDefName:work@buf |vpiName:buf0 |vpiFullName:work@sky130_fd_sc_hd__o21a.buf0 @@ -34170,7 +34170,7 @@ Processing: -cd cells/cells -DUNIT_DELAY -writepp -parse -nocache -nobuiltin -no design: (work@sky130_fd_sc_hd__xnor3) |vpiName:work@sky130_fd_sc_hd__xnor3 |uhdmallModules: -\_module: work@sky130_fd_sc_hd__xnor3 (work@sky130_fd_sc_hd__xnor3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__xnor3.functional.v, line:33:1, endln:53:10 +\_module_inst: work@sky130_fd_sc_hd__xnor3 (work@sky130_fd_sc_hd__xnor3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__xnor3.functional.v, line:33:1, endln:53:10 |vpiParent: \_design: (work@sky130_fd_sc_hd__xnor3) |vpiFullName:work@sky130_fd_sc_hd__xnor3 @@ -34178,38 +34178,38 @@ design: (work@sky130_fd_sc_hd__xnor3) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__xnor3.xnor0_out_X), line:47:10, endln:47:21 |vpiParent: - \_module: work@sky130_fd_sc_hd__xnor3 (work@sky130_fd_sc_hd__xnor3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__xnor3.functional.v, line:33:1, endln:53:10 + \_module_inst: work@sky130_fd_sc_hd__xnor3 (work@sky130_fd_sc_hd__xnor3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__xnor3.functional.v, line:33:1, endln:53:10 |vpiName:xnor0_out_X |vpiFullName:work@sky130_fd_sc_hd__xnor3.xnor0_out_X |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__xnor3.X), line:34:5, endln:34:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__xnor3 (work@sky130_fd_sc_hd__xnor3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__xnor3.functional.v, line:33:1, endln:53:10 + \_module_inst: work@sky130_fd_sc_hd__xnor3 (work@sky130_fd_sc_hd__xnor3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__xnor3.functional.v, line:33:1, endln:53:10 |vpiName:X |vpiFullName:work@sky130_fd_sc_hd__xnor3.X |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__xnor3.A), line:35:5, endln:35:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__xnor3 (work@sky130_fd_sc_hd__xnor3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__xnor3.functional.v, line:33:1, endln:53:10 + \_module_inst: work@sky130_fd_sc_hd__xnor3 (work@sky130_fd_sc_hd__xnor3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__xnor3.functional.v, line:33:1, endln:53:10 |vpiName:A |vpiFullName:work@sky130_fd_sc_hd__xnor3.A |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__xnor3.B), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__xnor3 (work@sky130_fd_sc_hd__xnor3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__xnor3.functional.v, line:33:1, endln:53:10 + \_module_inst: work@sky130_fd_sc_hd__xnor3 (work@sky130_fd_sc_hd__xnor3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__xnor3.functional.v, line:33:1, endln:53:10 |vpiName:B |vpiFullName:work@sky130_fd_sc_hd__xnor3.B |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__xnor3.C), line:37:5, endln:37:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__xnor3 (work@sky130_fd_sc_hd__xnor3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__xnor3.functional.v, line:33:1, endln:53:10 + \_module_inst: work@sky130_fd_sc_hd__xnor3 (work@sky130_fd_sc_hd__xnor3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__xnor3.functional.v, line:33:1, endln:53:10 |vpiName:C |vpiFullName:work@sky130_fd_sc_hd__xnor3.C |vpiPort: \_port: (X), line:34:5, endln:34:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__xnor3 (work@sky130_fd_sc_hd__xnor3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__xnor3.functional.v, line:33:1, endln:53:10 + \_module_inst: work@sky130_fd_sc_hd__xnor3 (work@sky130_fd_sc_hd__xnor3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__xnor3.functional.v, line:33:1, endln:53:10 |vpiName:X |vpiDirection:2 |vpiLowConn: @@ -34221,7 +34221,7 @@ design: (work@sky130_fd_sc_hd__xnor3) |vpiPort: \_port: (A), line:35:5, endln:35:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__xnor3 (work@sky130_fd_sc_hd__xnor3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__xnor3.functional.v, line:33:1, endln:53:10 + \_module_inst: work@sky130_fd_sc_hd__xnor3 (work@sky130_fd_sc_hd__xnor3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__xnor3.functional.v, line:33:1, endln:53:10 |vpiName:A |vpiDirection:1 |vpiLowConn: @@ -34233,7 +34233,7 @@ design: (work@sky130_fd_sc_hd__xnor3) |vpiPort: \_port: (B), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__xnor3 (work@sky130_fd_sc_hd__xnor3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__xnor3.functional.v, line:33:1, endln:53:10 + \_module_inst: work@sky130_fd_sc_hd__xnor3 (work@sky130_fd_sc_hd__xnor3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__xnor3.functional.v, line:33:1, endln:53:10 |vpiName:B |vpiDirection:1 |vpiLowConn: @@ -34245,7 +34245,7 @@ design: (work@sky130_fd_sc_hd__xnor3) |vpiPort: \_port: (C), line:37:5, endln:37:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__xnor3 (work@sky130_fd_sc_hd__xnor3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__xnor3.functional.v, line:33:1, endln:53:10 + \_module_inst: work@sky130_fd_sc_hd__xnor3 (work@sky130_fd_sc_hd__xnor3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__xnor3.functional.v, line:33:1, endln:53:10 |vpiName:C |vpiDirection:1 |vpiLowConn: @@ -34255,14 +34255,14 @@ design: (work@sky130_fd_sc_hd__xnor3) |vpiTypedef: \_logic_typespec: , line:44:12, endln:44:12 |uhdmtopModules: -\_module: work@sky130_fd_sc_hd__xnor3 (work@sky130_fd_sc_hd__xnor3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__xnor3.functional.v, line:33:1, endln:53:10 +\_module_inst: work@sky130_fd_sc_hd__xnor3 (work@sky130_fd_sc_hd__xnor3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__xnor3.functional.v, line:33:1, endln:53:10 |vpiName:work@sky130_fd_sc_hd__xnor3 |vpiDefName:work@sky130_fd_sc_hd__xnor3 |vpiTop:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__xnor3.xnor0_out_X), line:47:10, endln:47:21 |vpiParent: - \_module: work@sky130_fd_sc_hd__xnor3 (work@sky130_fd_sc_hd__xnor3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__xnor3.functional.v, line:33:1, endln:53:10 + \_module_inst: work@sky130_fd_sc_hd__xnor3 (work@sky130_fd_sc_hd__xnor3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__xnor3.functional.v, line:33:1, endln:53:10 |vpiTypespec: \_logic_typespec: , line:47:5, endln:47:9 |vpiName:xnor0_out_X @@ -34271,7 +34271,7 @@ design: (work@sky130_fd_sc_hd__xnor3) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__xnor3.X), line:34:5, endln:34:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__xnor3 (work@sky130_fd_sc_hd__xnor3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__xnor3.functional.v, line:33:1, endln:53:10 + \_module_inst: work@sky130_fd_sc_hd__xnor3 (work@sky130_fd_sc_hd__xnor3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__xnor3.functional.v, line:33:1, endln:53:10 |vpiTypespec: \_logic_typespec: , line:41:12, endln:41:12 |vpiName:X @@ -34279,7 +34279,7 @@ design: (work@sky130_fd_sc_hd__xnor3) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__xnor3.A), line:35:5, endln:35:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__xnor3 (work@sky130_fd_sc_hd__xnor3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__xnor3.functional.v, line:33:1, endln:53:10 + \_module_inst: work@sky130_fd_sc_hd__xnor3 (work@sky130_fd_sc_hd__xnor3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__xnor3.functional.v, line:33:1, endln:53:10 |vpiTypespec: \_logic_typespec: , line:42:12, endln:42:12 |vpiName:A @@ -34287,7 +34287,7 @@ design: (work@sky130_fd_sc_hd__xnor3) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__xnor3.B), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__xnor3 (work@sky130_fd_sc_hd__xnor3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__xnor3.functional.v, line:33:1, endln:53:10 + \_module_inst: work@sky130_fd_sc_hd__xnor3 (work@sky130_fd_sc_hd__xnor3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__xnor3.functional.v, line:33:1, endln:53:10 |vpiTypespec: \_logic_typespec: , line:43:12, endln:43:12 |vpiName:B @@ -34295,7 +34295,7 @@ design: (work@sky130_fd_sc_hd__xnor3) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__xnor3.C), line:37:5, endln:37:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__xnor3 (work@sky130_fd_sc_hd__xnor3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__xnor3.functional.v, line:33:1, endln:53:10 + \_module_inst: work@sky130_fd_sc_hd__xnor3 (work@sky130_fd_sc_hd__xnor3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__xnor3.functional.v, line:33:1, endln:53:10 |vpiTypespec: \_logic_typespec: , line:44:12, endln:44:12 |vpiName:C @@ -34304,7 +34304,7 @@ design: (work@sky130_fd_sc_hd__xnor3) |vpiPort: \_port: (X), line:34:5, endln:34:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__xnor3 (work@sky130_fd_sc_hd__xnor3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__xnor3.functional.v, line:33:1, endln:53:10 + \_module_inst: work@sky130_fd_sc_hd__xnor3 (work@sky130_fd_sc_hd__xnor3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__xnor3.functional.v, line:33:1, endln:53:10 |vpiName:X |vpiDirection:2 |vpiLowConn: @@ -34318,7 +34318,7 @@ design: (work@sky130_fd_sc_hd__xnor3) |vpiPort: \_port: (A), line:35:5, endln:35:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__xnor3 (work@sky130_fd_sc_hd__xnor3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__xnor3.functional.v, line:33:1, endln:53:10 + \_module_inst: work@sky130_fd_sc_hd__xnor3 (work@sky130_fd_sc_hd__xnor3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__xnor3.functional.v, line:33:1, endln:53:10 |vpiName:A |vpiDirection:1 |vpiLowConn: @@ -34332,7 +34332,7 @@ design: (work@sky130_fd_sc_hd__xnor3) |vpiPort: \_port: (B), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__xnor3 (work@sky130_fd_sc_hd__xnor3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__xnor3.functional.v, line:33:1, endln:53:10 + \_module_inst: work@sky130_fd_sc_hd__xnor3 (work@sky130_fd_sc_hd__xnor3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__xnor3.functional.v, line:33:1, endln:53:10 |vpiName:B |vpiDirection:1 |vpiLowConn: @@ -34346,7 +34346,7 @@ design: (work@sky130_fd_sc_hd__xnor3) |vpiPort: \_port: (C), line:37:5, endln:37:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__xnor3 (work@sky130_fd_sc_hd__xnor3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__xnor3.functional.v, line:33:1, endln:53:10 + \_module_inst: work@sky130_fd_sc_hd__xnor3 (work@sky130_fd_sc_hd__xnor3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__xnor3.functional.v, line:33:1, endln:53:10 |vpiName:C |vpiDirection:1 |vpiLowConn: @@ -34360,7 +34360,7 @@ design: (work@sky130_fd_sc_hd__xnor3) |vpiPrimitive: \_gate: work@xnor (work@sky130_fd_sc_hd__xnor3.xnor0), line:50:10, endln:50:46 |vpiParent: - \_module: work@sky130_fd_sc_hd__xnor3 (work@sky130_fd_sc_hd__xnor3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__xnor3.functional.v, line:33:1, endln:53:10 + \_module_inst: work@sky130_fd_sc_hd__xnor3 (work@sky130_fd_sc_hd__xnor3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__xnor3.functional.v, line:33:1, endln:53:10 |vpiDefName:work@xnor |vpiName:xnor0 |vpiFullName:work@sky130_fd_sc_hd__xnor3.xnor0 @@ -34423,7 +34423,7 @@ design: (work@sky130_fd_sc_hd__xnor3) |vpiPrimitive: \_gate: work@buf (work@sky130_fd_sc_hd__xnor3.buf0), line:51:10, endln:51:46 |vpiParent: - \_module: work@sky130_fd_sc_hd__xnor3 (work@sky130_fd_sc_hd__xnor3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__xnor3.functional.v, line:33:1, endln:53:10 + \_module_inst: work@sky130_fd_sc_hd__xnor3 (work@sky130_fd_sc_hd__xnor3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__xnor3.functional.v, line:33:1, endln:53:10 |vpiDefName:work@buf |vpiName:buf0 |vpiFullName:work@sky130_fd_sc_hd__xnor3.buf0 @@ -34466,7 +34466,7 @@ Processing: -cd cells/cells -DUNIT_DELAY -writepp -parse -nocache -nobuiltin -no design: (work@sky130_fd_sc_hd__and3b) |vpiName:work@sky130_fd_sc_hd__and3b |uhdmallModules: -\_module: work@sky130_fd_sc_hd__and3b (work@sky130_fd_sc_hd__and3b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and3b.functional.v, line:33:1, endln:55:10 +\_module_inst: work@sky130_fd_sc_hd__and3b (work@sky130_fd_sc_hd__and3b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and3b.functional.v, line:33:1, endln:55:10 |vpiParent: \_design: (work@sky130_fd_sc_hd__and3b) |vpiFullName:work@sky130_fd_sc_hd__and3b @@ -34474,45 +34474,45 @@ design: (work@sky130_fd_sc_hd__and3b) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__and3b.not0_out), line:47:10, endln:47:18 |vpiParent: - \_module: work@sky130_fd_sc_hd__and3b (work@sky130_fd_sc_hd__and3b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and3b.functional.v, line:33:1, endln:55:10 + \_module_inst: work@sky130_fd_sc_hd__and3b (work@sky130_fd_sc_hd__and3b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and3b.functional.v, line:33:1, endln:55:10 |vpiName:not0_out |vpiFullName:work@sky130_fd_sc_hd__and3b.not0_out |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__and3b.and0_out_X), line:48:10, endln:48:20 |vpiParent: - \_module: work@sky130_fd_sc_hd__and3b (work@sky130_fd_sc_hd__and3b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and3b.functional.v, line:33:1, endln:55:10 + \_module_inst: work@sky130_fd_sc_hd__and3b (work@sky130_fd_sc_hd__and3b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and3b.functional.v, line:33:1, endln:55:10 |vpiName:and0_out_X |vpiFullName:work@sky130_fd_sc_hd__and3b.and0_out_X |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__and3b.X), line:34:5, endln:34:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__and3b (work@sky130_fd_sc_hd__and3b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and3b.functional.v, line:33:1, endln:55:10 + \_module_inst: work@sky130_fd_sc_hd__and3b (work@sky130_fd_sc_hd__and3b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and3b.functional.v, line:33:1, endln:55:10 |vpiName:X |vpiFullName:work@sky130_fd_sc_hd__and3b.X |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__and3b.A_N), line:35:5, endln:35:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__and3b (work@sky130_fd_sc_hd__and3b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and3b.functional.v, line:33:1, endln:55:10 + \_module_inst: work@sky130_fd_sc_hd__and3b (work@sky130_fd_sc_hd__and3b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and3b.functional.v, line:33:1, endln:55:10 |vpiName:A_N |vpiFullName:work@sky130_fd_sc_hd__and3b.A_N |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__and3b.B), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__and3b (work@sky130_fd_sc_hd__and3b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and3b.functional.v, line:33:1, endln:55:10 + \_module_inst: work@sky130_fd_sc_hd__and3b (work@sky130_fd_sc_hd__and3b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and3b.functional.v, line:33:1, endln:55:10 |vpiName:B |vpiFullName:work@sky130_fd_sc_hd__and3b.B |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__and3b.C), line:37:5, endln:37:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__and3b (work@sky130_fd_sc_hd__and3b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and3b.functional.v, line:33:1, endln:55:10 + \_module_inst: work@sky130_fd_sc_hd__and3b (work@sky130_fd_sc_hd__and3b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and3b.functional.v, line:33:1, endln:55:10 |vpiName:C |vpiFullName:work@sky130_fd_sc_hd__and3b.C |vpiPort: \_port: (X), line:34:5, endln:34:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__and3b (work@sky130_fd_sc_hd__and3b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and3b.functional.v, line:33:1, endln:55:10 + \_module_inst: work@sky130_fd_sc_hd__and3b (work@sky130_fd_sc_hd__and3b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and3b.functional.v, line:33:1, endln:55:10 |vpiName:X |vpiDirection:2 |vpiLowConn: @@ -34524,7 +34524,7 @@ design: (work@sky130_fd_sc_hd__and3b) |vpiPort: \_port: (A_N), line:35:5, endln:35:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__and3b (work@sky130_fd_sc_hd__and3b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and3b.functional.v, line:33:1, endln:55:10 + \_module_inst: work@sky130_fd_sc_hd__and3b (work@sky130_fd_sc_hd__and3b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and3b.functional.v, line:33:1, endln:55:10 |vpiName:A_N |vpiDirection:1 |vpiLowConn: @@ -34536,7 +34536,7 @@ design: (work@sky130_fd_sc_hd__and3b) |vpiPort: \_port: (B), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__and3b (work@sky130_fd_sc_hd__and3b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and3b.functional.v, line:33:1, endln:55:10 + \_module_inst: work@sky130_fd_sc_hd__and3b (work@sky130_fd_sc_hd__and3b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and3b.functional.v, line:33:1, endln:55:10 |vpiName:B |vpiDirection:1 |vpiLowConn: @@ -34548,7 +34548,7 @@ design: (work@sky130_fd_sc_hd__and3b) |vpiPort: \_port: (C), line:37:5, endln:37:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__and3b (work@sky130_fd_sc_hd__and3b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and3b.functional.v, line:33:1, endln:55:10 + \_module_inst: work@sky130_fd_sc_hd__and3b (work@sky130_fd_sc_hd__and3b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and3b.functional.v, line:33:1, endln:55:10 |vpiName:C |vpiDirection:1 |vpiLowConn: @@ -34558,14 +34558,14 @@ design: (work@sky130_fd_sc_hd__and3b) |vpiTypedef: \_logic_typespec: , line:44:12, endln:44:12 |uhdmtopModules: -\_module: work@sky130_fd_sc_hd__and3b (work@sky130_fd_sc_hd__and3b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and3b.functional.v, line:33:1, endln:55:10 +\_module_inst: work@sky130_fd_sc_hd__and3b (work@sky130_fd_sc_hd__and3b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and3b.functional.v, line:33:1, endln:55:10 |vpiName:work@sky130_fd_sc_hd__and3b |vpiDefName:work@sky130_fd_sc_hd__and3b |vpiTop:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__and3b.not0_out), line:47:10, endln:47:18 |vpiParent: - \_module: work@sky130_fd_sc_hd__and3b (work@sky130_fd_sc_hd__and3b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and3b.functional.v, line:33:1, endln:55:10 + \_module_inst: work@sky130_fd_sc_hd__and3b (work@sky130_fd_sc_hd__and3b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and3b.functional.v, line:33:1, endln:55:10 |vpiTypespec: \_logic_typespec: , line:47:5, endln:47:9 |vpiName:not0_out @@ -34574,7 +34574,7 @@ design: (work@sky130_fd_sc_hd__and3b) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__and3b.and0_out_X), line:48:10, endln:48:20 |vpiParent: - \_module: work@sky130_fd_sc_hd__and3b (work@sky130_fd_sc_hd__and3b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and3b.functional.v, line:33:1, endln:55:10 + \_module_inst: work@sky130_fd_sc_hd__and3b (work@sky130_fd_sc_hd__and3b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and3b.functional.v, line:33:1, endln:55:10 |vpiTypespec: \_logic_typespec: , line:48:5, endln:48:9 |vpiName:and0_out_X @@ -34583,7 +34583,7 @@ design: (work@sky130_fd_sc_hd__and3b) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__and3b.X), line:34:5, endln:34:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__and3b (work@sky130_fd_sc_hd__and3b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and3b.functional.v, line:33:1, endln:55:10 + \_module_inst: work@sky130_fd_sc_hd__and3b (work@sky130_fd_sc_hd__and3b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and3b.functional.v, line:33:1, endln:55:10 |vpiTypespec: \_logic_typespec: , line:41:12, endln:41:12 |vpiName:X @@ -34591,7 +34591,7 @@ design: (work@sky130_fd_sc_hd__and3b) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__and3b.A_N), line:35:5, endln:35:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__and3b (work@sky130_fd_sc_hd__and3b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and3b.functional.v, line:33:1, endln:55:10 + \_module_inst: work@sky130_fd_sc_hd__and3b (work@sky130_fd_sc_hd__and3b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and3b.functional.v, line:33:1, endln:55:10 |vpiTypespec: \_logic_typespec: , line:42:12, endln:42:12 |vpiName:A_N @@ -34599,7 +34599,7 @@ design: (work@sky130_fd_sc_hd__and3b) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__and3b.B), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__and3b (work@sky130_fd_sc_hd__and3b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and3b.functional.v, line:33:1, endln:55:10 + \_module_inst: work@sky130_fd_sc_hd__and3b (work@sky130_fd_sc_hd__and3b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and3b.functional.v, line:33:1, endln:55:10 |vpiTypespec: \_logic_typespec: , line:43:12, endln:43:12 |vpiName:B @@ -34607,7 +34607,7 @@ design: (work@sky130_fd_sc_hd__and3b) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__and3b.C), line:37:5, endln:37:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__and3b (work@sky130_fd_sc_hd__and3b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and3b.functional.v, line:33:1, endln:55:10 + \_module_inst: work@sky130_fd_sc_hd__and3b (work@sky130_fd_sc_hd__and3b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and3b.functional.v, line:33:1, endln:55:10 |vpiTypespec: \_logic_typespec: , line:44:12, endln:44:12 |vpiName:C @@ -34616,7 +34616,7 @@ design: (work@sky130_fd_sc_hd__and3b) |vpiPort: \_port: (X), line:34:5, endln:34:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__and3b (work@sky130_fd_sc_hd__and3b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and3b.functional.v, line:33:1, endln:55:10 + \_module_inst: work@sky130_fd_sc_hd__and3b (work@sky130_fd_sc_hd__and3b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and3b.functional.v, line:33:1, endln:55:10 |vpiName:X |vpiDirection:2 |vpiLowConn: @@ -34630,7 +34630,7 @@ design: (work@sky130_fd_sc_hd__and3b) |vpiPort: \_port: (A_N), line:35:5, endln:35:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__and3b (work@sky130_fd_sc_hd__and3b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and3b.functional.v, line:33:1, endln:55:10 + \_module_inst: work@sky130_fd_sc_hd__and3b (work@sky130_fd_sc_hd__and3b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and3b.functional.v, line:33:1, endln:55:10 |vpiName:A_N |vpiDirection:1 |vpiLowConn: @@ -34644,7 +34644,7 @@ design: (work@sky130_fd_sc_hd__and3b) |vpiPort: \_port: (B), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__and3b (work@sky130_fd_sc_hd__and3b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and3b.functional.v, line:33:1, endln:55:10 + \_module_inst: work@sky130_fd_sc_hd__and3b (work@sky130_fd_sc_hd__and3b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and3b.functional.v, line:33:1, endln:55:10 |vpiName:B |vpiDirection:1 |vpiLowConn: @@ -34658,7 +34658,7 @@ design: (work@sky130_fd_sc_hd__and3b) |vpiPort: \_port: (C), line:37:5, endln:37:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__and3b (work@sky130_fd_sc_hd__and3b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and3b.functional.v, line:33:1, endln:55:10 + \_module_inst: work@sky130_fd_sc_hd__and3b (work@sky130_fd_sc_hd__and3b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and3b.functional.v, line:33:1, endln:55:10 |vpiName:C |vpiDirection:1 |vpiLowConn: @@ -34672,7 +34672,7 @@ design: (work@sky130_fd_sc_hd__and3b) |vpiPrimitive: \_gate: work@not (work@sky130_fd_sc_hd__and3b.not0), line:51:9, endln:51:43 |vpiParent: - \_module: work@sky130_fd_sc_hd__and3b (work@sky130_fd_sc_hd__and3b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and3b.functional.v, line:33:1, endln:55:10 + \_module_inst: work@sky130_fd_sc_hd__and3b (work@sky130_fd_sc_hd__and3b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and3b.functional.v, line:33:1, endln:55:10 |vpiDefName:work@not |vpiName:not0 |vpiFullName:work@sky130_fd_sc_hd__and3b.not0 @@ -34707,7 +34707,7 @@ design: (work@sky130_fd_sc_hd__and3b) |vpiPrimitive: \_gate: work@and (work@sky130_fd_sc_hd__and3b.and0), line:52:9, endln:52:43 |vpiParent: - \_module: work@sky130_fd_sc_hd__and3b (work@sky130_fd_sc_hd__and3b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and3b.functional.v, line:33:1, endln:55:10 + \_module_inst: work@sky130_fd_sc_hd__and3b (work@sky130_fd_sc_hd__and3b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and3b.functional.v, line:33:1, endln:55:10 |vpiDefName:work@and |vpiName:and0 |vpiFullName:work@sky130_fd_sc_hd__and3b.and0 @@ -34770,7 +34770,7 @@ design: (work@sky130_fd_sc_hd__and3b) |vpiPrimitive: \_gate: work@buf (work@sky130_fd_sc_hd__and3b.buf0), line:53:9, endln:53:43 |vpiParent: - \_module: work@sky130_fd_sc_hd__and3b (work@sky130_fd_sc_hd__and3b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and3b.functional.v, line:33:1, endln:55:10 + \_module_inst: work@sky130_fd_sc_hd__and3b (work@sky130_fd_sc_hd__and3b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and3b.functional.v, line:33:1, endln:55:10 |vpiDefName:work@buf |vpiName:buf0 |vpiFullName:work@sky130_fd_sc_hd__and3b.buf0 @@ -34813,7 +34813,7 @@ Processing: -cd cells/cells -DUNIT_DELAY -writepp -parse -nocache -nobuiltin -no design: (work@sky130_fd_sc_hd__o22ai) |vpiName:work@sky130_fd_sc_hd__o22ai |uhdmallModules: -\_module: work@sky130_fd_sc_hd__o22ai (work@sky130_fd_sc_hd__o22ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o22ai.functional.v, line:35:1, endln:61:10 +\_module_inst: work@sky130_fd_sc_hd__o22ai (work@sky130_fd_sc_hd__o22ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o22ai.functional.v, line:35:1, endln:61:10 |vpiParent: \_design: (work@sky130_fd_sc_hd__o22ai) |vpiFullName:work@sky130_fd_sc_hd__o22ai @@ -34821,58 +34821,58 @@ design: (work@sky130_fd_sc_hd__o22ai) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o22ai.nor0_out), line:51:10, endln:51:18 |vpiParent: - \_module: work@sky130_fd_sc_hd__o22ai (work@sky130_fd_sc_hd__o22ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o22ai.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o22ai (work@sky130_fd_sc_hd__o22ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o22ai.functional.v, line:35:1, endln:61:10 |vpiName:nor0_out |vpiFullName:work@sky130_fd_sc_hd__o22ai.nor0_out |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o22ai.nor1_out), line:52:10, endln:52:18 |vpiParent: - \_module: work@sky130_fd_sc_hd__o22ai (work@sky130_fd_sc_hd__o22ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o22ai.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o22ai (work@sky130_fd_sc_hd__o22ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o22ai.functional.v, line:35:1, endln:61:10 |vpiName:nor1_out |vpiFullName:work@sky130_fd_sc_hd__o22ai.nor1_out |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o22ai.or0_out_Y), line:53:10, endln:53:19 |vpiParent: - \_module: work@sky130_fd_sc_hd__o22ai (work@sky130_fd_sc_hd__o22ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o22ai.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o22ai (work@sky130_fd_sc_hd__o22ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o22ai.functional.v, line:35:1, endln:61:10 |vpiName:or0_out_Y |vpiFullName:work@sky130_fd_sc_hd__o22ai.or0_out_Y |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o22ai.Y), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__o22ai (work@sky130_fd_sc_hd__o22ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o22ai.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o22ai (work@sky130_fd_sc_hd__o22ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o22ai.functional.v, line:35:1, endln:61:10 |vpiName:Y |vpiFullName:work@sky130_fd_sc_hd__o22ai.Y |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o22ai.A1), line:37:5, endln:37:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o22ai (work@sky130_fd_sc_hd__o22ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o22ai.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o22ai (work@sky130_fd_sc_hd__o22ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o22ai.functional.v, line:35:1, endln:61:10 |vpiName:A1 |vpiFullName:work@sky130_fd_sc_hd__o22ai.A1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o22ai.A2), line:38:5, endln:38:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o22ai (work@sky130_fd_sc_hd__o22ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o22ai.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o22ai (work@sky130_fd_sc_hd__o22ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o22ai.functional.v, line:35:1, endln:61:10 |vpiName:A2 |vpiFullName:work@sky130_fd_sc_hd__o22ai.A2 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o22ai.B1), line:39:5, endln:39:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o22ai (work@sky130_fd_sc_hd__o22ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o22ai.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o22ai (work@sky130_fd_sc_hd__o22ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o22ai.functional.v, line:35:1, endln:61:10 |vpiName:B1 |vpiFullName:work@sky130_fd_sc_hd__o22ai.B1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o22ai.B2), line:40:5, endln:40:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o22ai (work@sky130_fd_sc_hd__o22ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o22ai.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o22ai (work@sky130_fd_sc_hd__o22ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o22ai.functional.v, line:35:1, endln:61:10 |vpiName:B2 |vpiFullName:work@sky130_fd_sc_hd__o22ai.B2 |vpiPort: \_port: (Y), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__o22ai (work@sky130_fd_sc_hd__o22ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o22ai.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o22ai (work@sky130_fd_sc_hd__o22ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o22ai.functional.v, line:35:1, endln:61:10 |vpiName:Y |vpiDirection:2 |vpiLowConn: @@ -34884,7 +34884,7 @@ design: (work@sky130_fd_sc_hd__o22ai) |vpiPort: \_port: (A1), line:37:5, endln:37:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o22ai (work@sky130_fd_sc_hd__o22ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o22ai.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o22ai (work@sky130_fd_sc_hd__o22ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o22ai.functional.v, line:35:1, endln:61:10 |vpiName:A1 |vpiDirection:1 |vpiLowConn: @@ -34896,7 +34896,7 @@ design: (work@sky130_fd_sc_hd__o22ai) |vpiPort: \_port: (A2), line:38:5, endln:38:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o22ai (work@sky130_fd_sc_hd__o22ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o22ai.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o22ai (work@sky130_fd_sc_hd__o22ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o22ai.functional.v, line:35:1, endln:61:10 |vpiName:A2 |vpiDirection:1 |vpiLowConn: @@ -34908,7 +34908,7 @@ design: (work@sky130_fd_sc_hd__o22ai) |vpiPort: \_port: (B1), line:39:5, endln:39:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o22ai (work@sky130_fd_sc_hd__o22ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o22ai.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o22ai (work@sky130_fd_sc_hd__o22ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o22ai.functional.v, line:35:1, endln:61:10 |vpiName:B1 |vpiDirection:1 |vpiLowConn: @@ -34920,7 +34920,7 @@ design: (work@sky130_fd_sc_hd__o22ai) |vpiPort: \_port: (B2), line:40:5, endln:40:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o22ai (work@sky130_fd_sc_hd__o22ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o22ai.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o22ai (work@sky130_fd_sc_hd__o22ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o22ai.functional.v, line:35:1, endln:61:10 |vpiName:B2 |vpiDirection:1 |vpiLowConn: @@ -34930,14 +34930,14 @@ design: (work@sky130_fd_sc_hd__o22ai) |vpiTypedef: \_logic_typespec: , line:48:12, endln:48:12 |uhdmtopModules: -\_module: work@sky130_fd_sc_hd__o22ai (work@sky130_fd_sc_hd__o22ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o22ai.functional.v, line:35:1, endln:61:10 +\_module_inst: work@sky130_fd_sc_hd__o22ai (work@sky130_fd_sc_hd__o22ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o22ai.functional.v, line:35:1, endln:61:10 |vpiName:work@sky130_fd_sc_hd__o22ai |vpiDefName:work@sky130_fd_sc_hd__o22ai |vpiTop:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o22ai.nor0_out), line:51:10, endln:51:18 |vpiParent: - \_module: work@sky130_fd_sc_hd__o22ai (work@sky130_fd_sc_hd__o22ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o22ai.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o22ai (work@sky130_fd_sc_hd__o22ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o22ai.functional.v, line:35:1, endln:61:10 |vpiTypespec: \_logic_typespec: , line:51:5, endln:51:9 |vpiName:nor0_out @@ -34946,7 +34946,7 @@ design: (work@sky130_fd_sc_hd__o22ai) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o22ai.nor1_out), line:52:10, endln:52:18 |vpiParent: - \_module: work@sky130_fd_sc_hd__o22ai (work@sky130_fd_sc_hd__o22ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o22ai.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o22ai (work@sky130_fd_sc_hd__o22ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o22ai.functional.v, line:35:1, endln:61:10 |vpiTypespec: \_logic_typespec: , line:52:5, endln:52:9 |vpiName:nor1_out @@ -34955,7 +34955,7 @@ design: (work@sky130_fd_sc_hd__o22ai) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o22ai.or0_out_Y), line:53:10, endln:53:19 |vpiParent: - \_module: work@sky130_fd_sc_hd__o22ai (work@sky130_fd_sc_hd__o22ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o22ai.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o22ai (work@sky130_fd_sc_hd__o22ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o22ai.functional.v, line:35:1, endln:61:10 |vpiTypespec: \_logic_typespec: , line:53:5, endln:53:9 |vpiName:or0_out_Y @@ -34964,7 +34964,7 @@ design: (work@sky130_fd_sc_hd__o22ai) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o22ai.Y), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__o22ai (work@sky130_fd_sc_hd__o22ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o22ai.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o22ai (work@sky130_fd_sc_hd__o22ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o22ai.functional.v, line:35:1, endln:61:10 |vpiTypespec: \_logic_typespec: , line:44:12, endln:44:12 |vpiName:Y @@ -34972,7 +34972,7 @@ design: (work@sky130_fd_sc_hd__o22ai) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o22ai.A1), line:37:5, endln:37:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o22ai (work@sky130_fd_sc_hd__o22ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o22ai.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o22ai (work@sky130_fd_sc_hd__o22ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o22ai.functional.v, line:35:1, endln:61:10 |vpiTypespec: \_logic_typespec: , line:45:12, endln:45:12 |vpiName:A1 @@ -34980,7 +34980,7 @@ design: (work@sky130_fd_sc_hd__o22ai) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o22ai.A2), line:38:5, endln:38:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o22ai (work@sky130_fd_sc_hd__o22ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o22ai.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o22ai (work@sky130_fd_sc_hd__o22ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o22ai.functional.v, line:35:1, endln:61:10 |vpiTypespec: \_logic_typespec: , line:46:12, endln:46:12 |vpiName:A2 @@ -34988,7 +34988,7 @@ design: (work@sky130_fd_sc_hd__o22ai) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o22ai.B1), line:39:5, endln:39:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o22ai (work@sky130_fd_sc_hd__o22ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o22ai.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o22ai (work@sky130_fd_sc_hd__o22ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o22ai.functional.v, line:35:1, endln:61:10 |vpiTypespec: \_logic_typespec: , line:47:12, endln:47:12 |vpiName:B1 @@ -34996,7 +34996,7 @@ design: (work@sky130_fd_sc_hd__o22ai) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o22ai.B2), line:40:5, endln:40:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o22ai (work@sky130_fd_sc_hd__o22ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o22ai.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o22ai (work@sky130_fd_sc_hd__o22ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o22ai.functional.v, line:35:1, endln:61:10 |vpiTypespec: \_logic_typespec: , line:48:12, endln:48:12 |vpiName:B2 @@ -35005,7 +35005,7 @@ design: (work@sky130_fd_sc_hd__o22ai) |vpiPort: \_port: (Y), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__o22ai (work@sky130_fd_sc_hd__o22ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o22ai.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o22ai (work@sky130_fd_sc_hd__o22ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o22ai.functional.v, line:35:1, endln:61:10 |vpiName:Y |vpiDirection:2 |vpiLowConn: @@ -35019,7 +35019,7 @@ design: (work@sky130_fd_sc_hd__o22ai) |vpiPort: \_port: (A1), line:37:5, endln:37:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o22ai (work@sky130_fd_sc_hd__o22ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o22ai.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o22ai (work@sky130_fd_sc_hd__o22ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o22ai.functional.v, line:35:1, endln:61:10 |vpiName:A1 |vpiDirection:1 |vpiLowConn: @@ -35033,7 +35033,7 @@ design: (work@sky130_fd_sc_hd__o22ai) |vpiPort: \_port: (A2), line:38:5, endln:38:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o22ai (work@sky130_fd_sc_hd__o22ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o22ai.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o22ai (work@sky130_fd_sc_hd__o22ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o22ai.functional.v, line:35:1, endln:61:10 |vpiName:A2 |vpiDirection:1 |vpiLowConn: @@ -35047,7 +35047,7 @@ design: (work@sky130_fd_sc_hd__o22ai) |vpiPort: \_port: (B1), line:39:5, endln:39:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o22ai (work@sky130_fd_sc_hd__o22ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o22ai.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o22ai (work@sky130_fd_sc_hd__o22ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o22ai.functional.v, line:35:1, endln:61:10 |vpiName:B1 |vpiDirection:1 |vpiLowConn: @@ -35061,7 +35061,7 @@ design: (work@sky130_fd_sc_hd__o22ai) |vpiPort: \_port: (B2), line:40:5, endln:40:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o22ai (work@sky130_fd_sc_hd__o22ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o22ai.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o22ai (work@sky130_fd_sc_hd__o22ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o22ai.functional.v, line:35:1, endln:61:10 |vpiName:B2 |vpiDirection:1 |vpiLowConn: @@ -35075,7 +35075,7 @@ design: (work@sky130_fd_sc_hd__o22ai) |vpiPrimitive: \_gate: work@nor (work@sky130_fd_sc_hd__o22ai.nor0), line:56:9, endln:56:45 |vpiParent: - \_module: work@sky130_fd_sc_hd__o22ai (work@sky130_fd_sc_hd__o22ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o22ai.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o22ai (work@sky130_fd_sc_hd__o22ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o22ai.functional.v, line:35:1, endln:61:10 |vpiDefName:work@nor |vpiName:nor0 |vpiFullName:work@sky130_fd_sc_hd__o22ai.nor0 @@ -35124,7 +35124,7 @@ design: (work@sky130_fd_sc_hd__o22ai) |vpiPrimitive: \_gate: work@nor (work@sky130_fd_sc_hd__o22ai.nor1), line:57:9, endln:57:45 |vpiParent: - \_module: work@sky130_fd_sc_hd__o22ai (work@sky130_fd_sc_hd__o22ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o22ai.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o22ai (work@sky130_fd_sc_hd__o22ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o22ai.functional.v, line:35:1, endln:61:10 |vpiDefName:work@nor |vpiName:nor1 |vpiFullName:work@sky130_fd_sc_hd__o22ai.nor1 @@ -35173,7 +35173,7 @@ design: (work@sky130_fd_sc_hd__o22ai) |vpiPrimitive: \_gate: work@or (work@sky130_fd_sc_hd__o22ai.or0), line:58:9, endln:58:45 |vpiParent: - \_module: work@sky130_fd_sc_hd__o22ai (work@sky130_fd_sc_hd__o22ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o22ai.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o22ai (work@sky130_fd_sc_hd__o22ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o22ai.functional.v, line:35:1, endln:61:10 |vpiDefName:work@or |vpiName:or0 |vpiFullName:work@sky130_fd_sc_hd__o22ai.or0 @@ -35222,7 +35222,7 @@ design: (work@sky130_fd_sc_hd__o22ai) |vpiPrimitive: \_gate: work@buf (work@sky130_fd_sc_hd__o22ai.buf0), line:59:9, endln:59:45 |vpiParent: - \_module: work@sky130_fd_sc_hd__o22ai (work@sky130_fd_sc_hd__o22ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o22ai.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o22ai (work@sky130_fd_sc_hd__o22ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o22ai.functional.v, line:35:1, endln:61:10 |vpiDefName:work@buf |vpiName:buf0 |vpiFullName:work@sky130_fd_sc_hd__o22ai.buf0 @@ -35265,7 +35265,7 @@ Processing: -cd cells/cells -DUNIT_DELAY -writepp -parse -nocache -nobuiltin -no design: (work@sky130_fd_sc_hd__o21ai) |vpiName:work@sky130_fd_sc_hd__o21ai |uhdmallModules: -\_module: work@sky130_fd_sc_hd__o21ai (work@sky130_fd_sc_hd__o21ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o21ai.functional.v, line:35:1, endln:57:10 +\_module_inst: work@sky130_fd_sc_hd__o21ai (work@sky130_fd_sc_hd__o21ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o21ai.functional.v, line:35:1, endln:57:10 |vpiParent: \_design: (work@sky130_fd_sc_hd__o21ai) |vpiFullName:work@sky130_fd_sc_hd__o21ai @@ -35273,45 +35273,45 @@ design: (work@sky130_fd_sc_hd__o21ai) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o21ai.or0_out), line:49:10, endln:49:17 |vpiParent: - \_module: work@sky130_fd_sc_hd__o21ai (work@sky130_fd_sc_hd__o21ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o21ai.functional.v, line:35:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__o21ai (work@sky130_fd_sc_hd__o21ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o21ai.functional.v, line:35:1, endln:57:10 |vpiName:or0_out |vpiFullName:work@sky130_fd_sc_hd__o21ai.or0_out |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o21ai.nand0_out_Y), line:50:10, endln:50:21 |vpiParent: - \_module: work@sky130_fd_sc_hd__o21ai (work@sky130_fd_sc_hd__o21ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o21ai.functional.v, line:35:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__o21ai (work@sky130_fd_sc_hd__o21ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o21ai.functional.v, line:35:1, endln:57:10 |vpiName:nand0_out_Y |vpiFullName:work@sky130_fd_sc_hd__o21ai.nand0_out_Y |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o21ai.Y), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__o21ai (work@sky130_fd_sc_hd__o21ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o21ai.functional.v, line:35:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__o21ai (work@sky130_fd_sc_hd__o21ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o21ai.functional.v, line:35:1, endln:57:10 |vpiName:Y |vpiFullName:work@sky130_fd_sc_hd__o21ai.Y |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o21ai.A1), line:37:5, endln:37:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o21ai (work@sky130_fd_sc_hd__o21ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o21ai.functional.v, line:35:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__o21ai (work@sky130_fd_sc_hd__o21ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o21ai.functional.v, line:35:1, endln:57:10 |vpiName:A1 |vpiFullName:work@sky130_fd_sc_hd__o21ai.A1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o21ai.A2), line:38:5, endln:38:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o21ai (work@sky130_fd_sc_hd__o21ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o21ai.functional.v, line:35:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__o21ai (work@sky130_fd_sc_hd__o21ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o21ai.functional.v, line:35:1, endln:57:10 |vpiName:A2 |vpiFullName:work@sky130_fd_sc_hd__o21ai.A2 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o21ai.B1), line:39:5, endln:39:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o21ai (work@sky130_fd_sc_hd__o21ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o21ai.functional.v, line:35:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__o21ai (work@sky130_fd_sc_hd__o21ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o21ai.functional.v, line:35:1, endln:57:10 |vpiName:B1 |vpiFullName:work@sky130_fd_sc_hd__o21ai.B1 |vpiPort: \_port: (Y), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__o21ai (work@sky130_fd_sc_hd__o21ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o21ai.functional.v, line:35:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__o21ai (work@sky130_fd_sc_hd__o21ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o21ai.functional.v, line:35:1, endln:57:10 |vpiName:Y |vpiDirection:2 |vpiLowConn: @@ -35323,7 +35323,7 @@ design: (work@sky130_fd_sc_hd__o21ai) |vpiPort: \_port: (A1), line:37:5, endln:37:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o21ai (work@sky130_fd_sc_hd__o21ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o21ai.functional.v, line:35:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__o21ai (work@sky130_fd_sc_hd__o21ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o21ai.functional.v, line:35:1, endln:57:10 |vpiName:A1 |vpiDirection:1 |vpiLowConn: @@ -35335,7 +35335,7 @@ design: (work@sky130_fd_sc_hd__o21ai) |vpiPort: \_port: (A2), line:38:5, endln:38:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o21ai (work@sky130_fd_sc_hd__o21ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o21ai.functional.v, line:35:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__o21ai (work@sky130_fd_sc_hd__o21ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o21ai.functional.v, line:35:1, endln:57:10 |vpiName:A2 |vpiDirection:1 |vpiLowConn: @@ -35347,7 +35347,7 @@ design: (work@sky130_fd_sc_hd__o21ai) |vpiPort: \_port: (B1), line:39:5, endln:39:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o21ai (work@sky130_fd_sc_hd__o21ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o21ai.functional.v, line:35:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__o21ai (work@sky130_fd_sc_hd__o21ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o21ai.functional.v, line:35:1, endln:57:10 |vpiName:B1 |vpiDirection:1 |vpiLowConn: @@ -35357,14 +35357,14 @@ design: (work@sky130_fd_sc_hd__o21ai) |vpiTypedef: \_logic_typespec: , line:46:12, endln:46:12 |uhdmtopModules: -\_module: work@sky130_fd_sc_hd__o21ai (work@sky130_fd_sc_hd__o21ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o21ai.functional.v, line:35:1, endln:57:10 +\_module_inst: work@sky130_fd_sc_hd__o21ai (work@sky130_fd_sc_hd__o21ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o21ai.functional.v, line:35:1, endln:57:10 |vpiName:work@sky130_fd_sc_hd__o21ai |vpiDefName:work@sky130_fd_sc_hd__o21ai |vpiTop:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o21ai.or0_out), line:49:10, endln:49:17 |vpiParent: - \_module: work@sky130_fd_sc_hd__o21ai (work@sky130_fd_sc_hd__o21ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o21ai.functional.v, line:35:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__o21ai (work@sky130_fd_sc_hd__o21ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o21ai.functional.v, line:35:1, endln:57:10 |vpiTypespec: \_logic_typespec: , line:49:5, endln:49:9 |vpiName:or0_out @@ -35373,7 +35373,7 @@ design: (work@sky130_fd_sc_hd__o21ai) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o21ai.nand0_out_Y), line:50:10, endln:50:21 |vpiParent: - \_module: work@sky130_fd_sc_hd__o21ai (work@sky130_fd_sc_hd__o21ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o21ai.functional.v, line:35:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__o21ai (work@sky130_fd_sc_hd__o21ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o21ai.functional.v, line:35:1, endln:57:10 |vpiTypespec: \_logic_typespec: , line:50:5, endln:50:9 |vpiName:nand0_out_Y @@ -35382,7 +35382,7 @@ design: (work@sky130_fd_sc_hd__o21ai) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o21ai.Y), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__o21ai (work@sky130_fd_sc_hd__o21ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o21ai.functional.v, line:35:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__o21ai (work@sky130_fd_sc_hd__o21ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o21ai.functional.v, line:35:1, endln:57:10 |vpiTypespec: \_logic_typespec: , line:43:12, endln:43:12 |vpiName:Y @@ -35390,7 +35390,7 @@ design: (work@sky130_fd_sc_hd__o21ai) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o21ai.A1), line:37:5, endln:37:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o21ai (work@sky130_fd_sc_hd__o21ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o21ai.functional.v, line:35:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__o21ai (work@sky130_fd_sc_hd__o21ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o21ai.functional.v, line:35:1, endln:57:10 |vpiTypespec: \_logic_typespec: , line:44:12, endln:44:12 |vpiName:A1 @@ -35398,7 +35398,7 @@ design: (work@sky130_fd_sc_hd__o21ai) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o21ai.A2), line:38:5, endln:38:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o21ai (work@sky130_fd_sc_hd__o21ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o21ai.functional.v, line:35:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__o21ai (work@sky130_fd_sc_hd__o21ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o21ai.functional.v, line:35:1, endln:57:10 |vpiTypespec: \_logic_typespec: , line:45:12, endln:45:12 |vpiName:A2 @@ -35406,7 +35406,7 @@ design: (work@sky130_fd_sc_hd__o21ai) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o21ai.B1), line:39:5, endln:39:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o21ai (work@sky130_fd_sc_hd__o21ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o21ai.functional.v, line:35:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__o21ai (work@sky130_fd_sc_hd__o21ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o21ai.functional.v, line:35:1, endln:57:10 |vpiTypespec: \_logic_typespec: , line:46:12, endln:46:12 |vpiName:B1 @@ -35415,7 +35415,7 @@ design: (work@sky130_fd_sc_hd__o21ai) |vpiPort: \_port: (Y), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__o21ai (work@sky130_fd_sc_hd__o21ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o21ai.functional.v, line:35:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__o21ai (work@sky130_fd_sc_hd__o21ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o21ai.functional.v, line:35:1, endln:57:10 |vpiName:Y |vpiDirection:2 |vpiLowConn: @@ -35429,7 +35429,7 @@ design: (work@sky130_fd_sc_hd__o21ai) |vpiPort: \_port: (A1), line:37:5, endln:37:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o21ai (work@sky130_fd_sc_hd__o21ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o21ai.functional.v, line:35:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__o21ai (work@sky130_fd_sc_hd__o21ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o21ai.functional.v, line:35:1, endln:57:10 |vpiName:A1 |vpiDirection:1 |vpiLowConn: @@ -35443,7 +35443,7 @@ design: (work@sky130_fd_sc_hd__o21ai) |vpiPort: \_port: (A2), line:38:5, endln:38:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o21ai (work@sky130_fd_sc_hd__o21ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o21ai.functional.v, line:35:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__o21ai (work@sky130_fd_sc_hd__o21ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o21ai.functional.v, line:35:1, endln:57:10 |vpiName:A2 |vpiDirection:1 |vpiLowConn: @@ -35457,7 +35457,7 @@ design: (work@sky130_fd_sc_hd__o21ai) |vpiPort: \_port: (B1), line:39:5, endln:39:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o21ai (work@sky130_fd_sc_hd__o21ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o21ai.functional.v, line:35:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__o21ai (work@sky130_fd_sc_hd__o21ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o21ai.functional.v, line:35:1, endln:57:10 |vpiName:B1 |vpiDirection:1 |vpiLowConn: @@ -35471,7 +35471,7 @@ design: (work@sky130_fd_sc_hd__o21ai) |vpiPrimitive: \_gate: work@or (work@sky130_fd_sc_hd__o21ai.or0), line:53:10, endln:53:46 |vpiParent: - \_module: work@sky130_fd_sc_hd__o21ai (work@sky130_fd_sc_hd__o21ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o21ai.functional.v, line:35:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__o21ai (work@sky130_fd_sc_hd__o21ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o21ai.functional.v, line:35:1, endln:57:10 |vpiDefName:work@or |vpiName:or0 |vpiFullName:work@sky130_fd_sc_hd__o21ai.or0 @@ -35520,7 +35520,7 @@ design: (work@sky130_fd_sc_hd__o21ai) |vpiPrimitive: \_gate: work@nand (work@sky130_fd_sc_hd__o21ai.nand0), line:54:10, endln:54:46 |vpiParent: - \_module: work@sky130_fd_sc_hd__o21ai (work@sky130_fd_sc_hd__o21ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o21ai.functional.v, line:35:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__o21ai (work@sky130_fd_sc_hd__o21ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o21ai.functional.v, line:35:1, endln:57:10 |vpiDefName:work@nand |vpiName:nand0 |vpiFullName:work@sky130_fd_sc_hd__o21ai.nand0 @@ -35569,7 +35569,7 @@ design: (work@sky130_fd_sc_hd__o21ai) |vpiPrimitive: \_gate: work@buf (work@sky130_fd_sc_hd__o21ai.buf0), line:55:10, endln:55:46 |vpiParent: - \_module: work@sky130_fd_sc_hd__o21ai (work@sky130_fd_sc_hd__o21ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o21ai.functional.v, line:35:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__o21ai (work@sky130_fd_sc_hd__o21ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o21ai.functional.v, line:35:1, endln:57:10 |vpiDefName:work@buf |vpiName:buf0 |vpiFullName:work@sky130_fd_sc_hd__o21ai.buf0 @@ -35612,7 +35612,7 @@ Processing: -cd cells/cells -DUNIT_DELAY -writepp -parse -nocache -nobuiltin -no design: (work@sky130_fd_sc_hd__o41a) |vpiName:work@sky130_fd_sc_hd__o41a |uhdmallModules: -\_module: work@sky130_fd_sc_hd__o41a (work@sky130_fd_sc_hd__o41a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o41a.functional.v, line:35:1, endln:61:10 +\_module_inst: work@sky130_fd_sc_hd__o41a (work@sky130_fd_sc_hd__o41a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o41a.functional.v, line:35:1, endln:61:10 |vpiParent: \_design: (work@sky130_fd_sc_hd__o41a) |vpiFullName:work@sky130_fd_sc_hd__o41a @@ -35620,57 +35620,57 @@ design: (work@sky130_fd_sc_hd__o41a) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o41a.or0_out), line:53:10, endln:53:17 |vpiParent: - \_module: work@sky130_fd_sc_hd__o41a (work@sky130_fd_sc_hd__o41a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o41a.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o41a (work@sky130_fd_sc_hd__o41a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o41a.functional.v, line:35:1, endln:61:10 |vpiName:or0_out |vpiFullName:work@sky130_fd_sc_hd__o41a.or0_out |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o41a.and0_out_X), line:54:10, endln:54:20 |vpiParent: - \_module: work@sky130_fd_sc_hd__o41a (work@sky130_fd_sc_hd__o41a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o41a.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o41a (work@sky130_fd_sc_hd__o41a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o41a.functional.v, line:35:1, endln:61:10 |vpiName:and0_out_X |vpiFullName:work@sky130_fd_sc_hd__o41a.and0_out_X |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o41a.X), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__o41a (work@sky130_fd_sc_hd__o41a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o41a.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o41a (work@sky130_fd_sc_hd__o41a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o41a.functional.v, line:35:1, endln:61:10 |vpiName:X |vpiFullName:work@sky130_fd_sc_hd__o41a.X |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o41a.A1), line:37:5, endln:37:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o41a (work@sky130_fd_sc_hd__o41a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o41a.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o41a (work@sky130_fd_sc_hd__o41a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o41a.functional.v, line:35:1, endln:61:10 |vpiName:A1 |vpiFullName:work@sky130_fd_sc_hd__o41a.A1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o41a.A2), line:38:5, endln:38:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o41a (work@sky130_fd_sc_hd__o41a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o41a.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o41a (work@sky130_fd_sc_hd__o41a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o41a.functional.v, line:35:1, endln:61:10 |vpiName:A2 |vpiFullName:work@sky130_fd_sc_hd__o41a.A2 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o41a.A3), line:39:5, endln:39:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o41a (work@sky130_fd_sc_hd__o41a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o41a.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o41a (work@sky130_fd_sc_hd__o41a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o41a.functional.v, line:35:1, endln:61:10 |vpiName:A3 |vpiFullName:work@sky130_fd_sc_hd__o41a.A3 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o41a.A4), line:40:5, endln:40:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o41a (work@sky130_fd_sc_hd__o41a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o41a.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o41a (work@sky130_fd_sc_hd__o41a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o41a.functional.v, line:35:1, endln:61:10 |vpiName:A4 |vpiFullName:work@sky130_fd_sc_hd__o41a.A4 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o41a.B1), line:41:5, endln:41:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o41a (work@sky130_fd_sc_hd__o41a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o41a.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o41a (work@sky130_fd_sc_hd__o41a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o41a.functional.v, line:35:1, endln:61:10 |vpiName:B1 |vpiFullName:work@sky130_fd_sc_hd__o41a.B1 |vpiPort: \_port: (X), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__o41a (work@sky130_fd_sc_hd__o41a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o41a.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o41a (work@sky130_fd_sc_hd__o41a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o41a.functional.v, line:35:1, endln:61:10 |vpiName:X |vpiDirection:2 |vpiLowConn: @@ -35682,7 +35682,7 @@ design: (work@sky130_fd_sc_hd__o41a) |vpiPort: \_port: (A1), line:37:5, endln:37:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o41a (work@sky130_fd_sc_hd__o41a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o41a.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o41a (work@sky130_fd_sc_hd__o41a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o41a.functional.v, line:35:1, endln:61:10 |vpiName:A1 |vpiDirection:1 |vpiLowConn: @@ -35694,7 +35694,7 @@ design: (work@sky130_fd_sc_hd__o41a) |vpiPort: \_port: (A2), line:38:5, endln:38:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o41a (work@sky130_fd_sc_hd__o41a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o41a.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o41a (work@sky130_fd_sc_hd__o41a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o41a.functional.v, line:35:1, endln:61:10 |vpiName:A2 |vpiDirection:1 |vpiLowConn: @@ -35706,7 +35706,7 @@ design: (work@sky130_fd_sc_hd__o41a) |vpiPort: \_port: (A3), line:39:5, endln:39:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o41a (work@sky130_fd_sc_hd__o41a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o41a.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o41a (work@sky130_fd_sc_hd__o41a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o41a.functional.v, line:35:1, endln:61:10 |vpiName:A3 |vpiDirection:1 |vpiLowConn: @@ -35718,7 +35718,7 @@ design: (work@sky130_fd_sc_hd__o41a) |vpiPort: \_port: (A4), line:40:5, endln:40:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o41a (work@sky130_fd_sc_hd__o41a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o41a.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o41a (work@sky130_fd_sc_hd__o41a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o41a.functional.v, line:35:1, endln:61:10 |vpiName:A4 |vpiDirection:1 |vpiLowConn: @@ -35730,7 +35730,7 @@ design: (work@sky130_fd_sc_hd__o41a) |vpiPort: \_port: (B1), line:41:5, endln:41:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o41a (work@sky130_fd_sc_hd__o41a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o41a.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o41a (work@sky130_fd_sc_hd__o41a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o41a.functional.v, line:35:1, endln:61:10 |vpiName:B1 |vpiDirection:1 |vpiLowConn: @@ -35740,14 +35740,14 @@ design: (work@sky130_fd_sc_hd__o41a) |vpiTypedef: \_logic_typespec: , line:50:12, endln:50:12 |uhdmtopModules: -\_module: work@sky130_fd_sc_hd__o41a (work@sky130_fd_sc_hd__o41a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o41a.functional.v, line:35:1, endln:61:10 +\_module_inst: work@sky130_fd_sc_hd__o41a (work@sky130_fd_sc_hd__o41a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o41a.functional.v, line:35:1, endln:61:10 |vpiName:work@sky130_fd_sc_hd__o41a |vpiDefName:work@sky130_fd_sc_hd__o41a |vpiTop:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o41a.or0_out), line:53:10, endln:53:17 |vpiParent: - \_module: work@sky130_fd_sc_hd__o41a (work@sky130_fd_sc_hd__o41a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o41a.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o41a (work@sky130_fd_sc_hd__o41a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o41a.functional.v, line:35:1, endln:61:10 |vpiTypespec: \_logic_typespec: , line:53:5, endln:53:9 |vpiName:or0_out @@ -35756,7 +35756,7 @@ design: (work@sky130_fd_sc_hd__o41a) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o41a.and0_out_X), line:54:10, endln:54:20 |vpiParent: - \_module: work@sky130_fd_sc_hd__o41a (work@sky130_fd_sc_hd__o41a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o41a.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o41a (work@sky130_fd_sc_hd__o41a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o41a.functional.v, line:35:1, endln:61:10 |vpiTypespec: \_logic_typespec: , line:54:5, endln:54:9 |vpiName:and0_out_X @@ -35765,7 +35765,7 @@ design: (work@sky130_fd_sc_hd__o41a) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o41a.X), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__o41a (work@sky130_fd_sc_hd__o41a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o41a.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o41a (work@sky130_fd_sc_hd__o41a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o41a.functional.v, line:35:1, endln:61:10 |vpiTypespec: \_logic_typespec: , line:45:12, endln:45:12 |vpiName:X @@ -35773,7 +35773,7 @@ design: (work@sky130_fd_sc_hd__o41a) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o41a.A1), line:37:5, endln:37:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o41a (work@sky130_fd_sc_hd__o41a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o41a.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o41a (work@sky130_fd_sc_hd__o41a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o41a.functional.v, line:35:1, endln:61:10 |vpiTypespec: \_logic_typespec: , line:46:12, endln:46:12 |vpiName:A1 @@ -35781,7 +35781,7 @@ design: (work@sky130_fd_sc_hd__o41a) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o41a.A2), line:38:5, endln:38:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o41a (work@sky130_fd_sc_hd__o41a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o41a.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o41a (work@sky130_fd_sc_hd__o41a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o41a.functional.v, line:35:1, endln:61:10 |vpiTypespec: \_logic_typespec: , line:47:12, endln:47:12 |vpiName:A2 @@ -35789,7 +35789,7 @@ design: (work@sky130_fd_sc_hd__o41a) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o41a.A3), line:39:5, endln:39:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o41a (work@sky130_fd_sc_hd__o41a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o41a.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o41a (work@sky130_fd_sc_hd__o41a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o41a.functional.v, line:35:1, endln:61:10 |vpiTypespec: \_logic_typespec: , line:48:12, endln:48:12 |vpiName:A3 @@ -35797,7 +35797,7 @@ design: (work@sky130_fd_sc_hd__o41a) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o41a.A4), line:40:5, endln:40:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o41a (work@sky130_fd_sc_hd__o41a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o41a.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o41a (work@sky130_fd_sc_hd__o41a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o41a.functional.v, line:35:1, endln:61:10 |vpiTypespec: \_logic_typespec: , line:49:12, endln:49:12 |vpiName:A4 @@ -35805,7 +35805,7 @@ design: (work@sky130_fd_sc_hd__o41a) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o41a.B1), line:41:5, endln:41:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o41a (work@sky130_fd_sc_hd__o41a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o41a.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o41a (work@sky130_fd_sc_hd__o41a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o41a.functional.v, line:35:1, endln:61:10 |vpiTypespec: \_logic_typespec: , line:50:12, endln:50:12 |vpiName:B1 @@ -35814,7 +35814,7 @@ design: (work@sky130_fd_sc_hd__o41a) |vpiPort: \_port: (X), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__o41a (work@sky130_fd_sc_hd__o41a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o41a.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o41a (work@sky130_fd_sc_hd__o41a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o41a.functional.v, line:35:1, endln:61:10 |vpiName:X |vpiDirection:2 |vpiLowConn: @@ -35828,7 +35828,7 @@ design: (work@sky130_fd_sc_hd__o41a) |vpiPort: \_port: (A1), line:37:5, endln:37:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o41a (work@sky130_fd_sc_hd__o41a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o41a.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o41a (work@sky130_fd_sc_hd__o41a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o41a.functional.v, line:35:1, endln:61:10 |vpiName:A1 |vpiDirection:1 |vpiLowConn: @@ -35842,7 +35842,7 @@ design: (work@sky130_fd_sc_hd__o41a) |vpiPort: \_port: (A2), line:38:5, endln:38:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o41a (work@sky130_fd_sc_hd__o41a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o41a.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o41a (work@sky130_fd_sc_hd__o41a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o41a.functional.v, line:35:1, endln:61:10 |vpiName:A2 |vpiDirection:1 |vpiLowConn: @@ -35856,7 +35856,7 @@ design: (work@sky130_fd_sc_hd__o41a) |vpiPort: \_port: (A3), line:39:5, endln:39:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o41a (work@sky130_fd_sc_hd__o41a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o41a.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o41a (work@sky130_fd_sc_hd__o41a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o41a.functional.v, line:35:1, endln:61:10 |vpiName:A3 |vpiDirection:1 |vpiLowConn: @@ -35870,7 +35870,7 @@ design: (work@sky130_fd_sc_hd__o41a) |vpiPort: \_port: (A4), line:40:5, endln:40:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o41a (work@sky130_fd_sc_hd__o41a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o41a.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o41a (work@sky130_fd_sc_hd__o41a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o41a.functional.v, line:35:1, endln:61:10 |vpiName:A4 |vpiDirection:1 |vpiLowConn: @@ -35884,7 +35884,7 @@ design: (work@sky130_fd_sc_hd__o41a) |vpiPort: \_port: (B1), line:41:5, endln:41:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o41a (work@sky130_fd_sc_hd__o41a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o41a.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o41a (work@sky130_fd_sc_hd__o41a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o41a.functional.v, line:35:1, endln:61:10 |vpiName:B1 |vpiDirection:1 |vpiLowConn: @@ -35898,7 +35898,7 @@ design: (work@sky130_fd_sc_hd__o41a) |vpiPrimitive: \_gate: work@or (work@sky130_fd_sc_hd__o41a.or0), line:57:9, endln:57:43 |vpiParent: - \_module: work@sky130_fd_sc_hd__o41a (work@sky130_fd_sc_hd__o41a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o41a.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o41a (work@sky130_fd_sc_hd__o41a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o41a.functional.v, line:35:1, endln:61:10 |vpiDefName:work@or |vpiName:or0 |vpiFullName:work@sky130_fd_sc_hd__o41a.or0 @@ -35975,7 +35975,7 @@ design: (work@sky130_fd_sc_hd__o41a) |vpiPrimitive: \_gate: work@and (work@sky130_fd_sc_hd__o41a.and0), line:58:9, endln:58:43 |vpiParent: - \_module: work@sky130_fd_sc_hd__o41a (work@sky130_fd_sc_hd__o41a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o41a.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o41a (work@sky130_fd_sc_hd__o41a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o41a.functional.v, line:35:1, endln:61:10 |vpiDefName:work@and |vpiName:and0 |vpiFullName:work@sky130_fd_sc_hd__o41a.and0 @@ -36024,7 +36024,7 @@ design: (work@sky130_fd_sc_hd__o41a) |vpiPrimitive: \_gate: work@buf (work@sky130_fd_sc_hd__o41a.buf0), line:59:9, endln:59:43 |vpiParent: - \_module: work@sky130_fd_sc_hd__o41a (work@sky130_fd_sc_hd__o41a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o41a.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o41a (work@sky130_fd_sc_hd__o41a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o41a.functional.v, line:35:1, endln:61:10 |vpiDefName:work@buf |vpiName:buf0 |vpiFullName:work@sky130_fd_sc_hd__o41a.buf0 @@ -36067,7 +36067,7 @@ Processing: -cd cells/cells -DUNIT_DELAY -writepp -parse -nocache -nobuiltin -no design: (work@sky130_fd_sc_hd__einvn) |vpiName:work@sky130_fd_sc_hd__einvn |uhdmallModules: -\_module: work@sky130_fd_sc_hd__einvn (work@sky130_fd_sc_hd__einvn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__einvn.functional.v, line:33:1, endln:47:10 +\_module_inst: work@sky130_fd_sc_hd__einvn (work@sky130_fd_sc_hd__einvn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__einvn.functional.v, line:33:1, endln:47:10 |vpiParent: \_design: (work@sky130_fd_sc_hd__einvn) |vpiFullName:work@sky130_fd_sc_hd__einvn @@ -36075,25 +36075,25 @@ design: (work@sky130_fd_sc_hd__einvn) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__einvn.Z), line:34:5, endln:34:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__einvn (work@sky130_fd_sc_hd__einvn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__einvn.functional.v, line:33:1, endln:47:10 + \_module_inst: work@sky130_fd_sc_hd__einvn (work@sky130_fd_sc_hd__einvn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__einvn.functional.v, line:33:1, endln:47:10 |vpiName:Z |vpiFullName:work@sky130_fd_sc_hd__einvn.Z |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__einvn.A), line:35:5, endln:35:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__einvn (work@sky130_fd_sc_hd__einvn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__einvn.functional.v, line:33:1, endln:47:10 + \_module_inst: work@sky130_fd_sc_hd__einvn (work@sky130_fd_sc_hd__einvn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__einvn.functional.v, line:33:1, endln:47:10 |vpiName:A |vpiFullName:work@sky130_fd_sc_hd__einvn.A |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__einvn.TE_B), line:36:5, endln:36:9 |vpiParent: - \_module: work@sky130_fd_sc_hd__einvn (work@sky130_fd_sc_hd__einvn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__einvn.functional.v, line:33:1, endln:47:10 + \_module_inst: work@sky130_fd_sc_hd__einvn (work@sky130_fd_sc_hd__einvn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__einvn.functional.v, line:33:1, endln:47:10 |vpiName:TE_B |vpiFullName:work@sky130_fd_sc_hd__einvn.TE_B |vpiPort: \_port: (Z), line:34:5, endln:34:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__einvn (work@sky130_fd_sc_hd__einvn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__einvn.functional.v, line:33:1, endln:47:10 + \_module_inst: work@sky130_fd_sc_hd__einvn (work@sky130_fd_sc_hd__einvn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__einvn.functional.v, line:33:1, endln:47:10 |vpiName:Z |vpiDirection:2 |vpiLowConn: @@ -36105,7 +36105,7 @@ design: (work@sky130_fd_sc_hd__einvn) |vpiPort: \_port: (A), line:35:5, endln:35:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__einvn (work@sky130_fd_sc_hd__einvn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__einvn.functional.v, line:33:1, endln:47:10 + \_module_inst: work@sky130_fd_sc_hd__einvn (work@sky130_fd_sc_hd__einvn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__einvn.functional.v, line:33:1, endln:47:10 |vpiName:A |vpiDirection:1 |vpiLowConn: @@ -36117,7 +36117,7 @@ design: (work@sky130_fd_sc_hd__einvn) |vpiPort: \_port: (TE_B), line:36:5, endln:36:9 |vpiParent: - \_module: work@sky130_fd_sc_hd__einvn (work@sky130_fd_sc_hd__einvn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__einvn.functional.v, line:33:1, endln:47:10 + \_module_inst: work@sky130_fd_sc_hd__einvn (work@sky130_fd_sc_hd__einvn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__einvn.functional.v, line:33:1, endln:47:10 |vpiName:TE_B |vpiDirection:1 |vpiLowConn: @@ -36127,14 +36127,14 @@ design: (work@sky130_fd_sc_hd__einvn) |vpiTypedef: \_logic_typespec: , line:42:12, endln:42:12 |uhdmtopModules: -\_module: work@sky130_fd_sc_hd__einvn (work@sky130_fd_sc_hd__einvn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__einvn.functional.v, line:33:1, endln:47:10 +\_module_inst: work@sky130_fd_sc_hd__einvn (work@sky130_fd_sc_hd__einvn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__einvn.functional.v, line:33:1, endln:47:10 |vpiName:work@sky130_fd_sc_hd__einvn |vpiDefName:work@sky130_fd_sc_hd__einvn |vpiTop:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__einvn.Z), line:34:5, endln:34:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__einvn (work@sky130_fd_sc_hd__einvn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__einvn.functional.v, line:33:1, endln:47:10 + \_module_inst: work@sky130_fd_sc_hd__einvn (work@sky130_fd_sc_hd__einvn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__einvn.functional.v, line:33:1, endln:47:10 |vpiTypespec: \_logic_typespec: , line:40:12, endln:40:12 |vpiName:Z @@ -36142,7 +36142,7 @@ design: (work@sky130_fd_sc_hd__einvn) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__einvn.A), line:35:5, endln:35:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__einvn (work@sky130_fd_sc_hd__einvn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__einvn.functional.v, line:33:1, endln:47:10 + \_module_inst: work@sky130_fd_sc_hd__einvn (work@sky130_fd_sc_hd__einvn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__einvn.functional.v, line:33:1, endln:47:10 |vpiTypespec: \_logic_typespec: , line:41:12, endln:41:12 |vpiName:A @@ -36150,7 +36150,7 @@ design: (work@sky130_fd_sc_hd__einvn) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__einvn.TE_B), line:36:5, endln:36:9 |vpiParent: - \_module: work@sky130_fd_sc_hd__einvn (work@sky130_fd_sc_hd__einvn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__einvn.functional.v, line:33:1, endln:47:10 + \_module_inst: work@sky130_fd_sc_hd__einvn (work@sky130_fd_sc_hd__einvn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__einvn.functional.v, line:33:1, endln:47:10 |vpiTypespec: \_logic_typespec: , line:42:12, endln:42:12 |vpiName:TE_B @@ -36159,7 +36159,7 @@ design: (work@sky130_fd_sc_hd__einvn) |vpiPort: \_port: (Z), line:34:5, endln:34:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__einvn (work@sky130_fd_sc_hd__einvn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__einvn.functional.v, line:33:1, endln:47:10 + \_module_inst: work@sky130_fd_sc_hd__einvn (work@sky130_fd_sc_hd__einvn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__einvn.functional.v, line:33:1, endln:47:10 |vpiName:Z |vpiDirection:2 |vpiLowConn: @@ -36173,7 +36173,7 @@ design: (work@sky130_fd_sc_hd__einvn) |vpiPort: \_port: (A), line:35:5, endln:35:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__einvn (work@sky130_fd_sc_hd__einvn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__einvn.functional.v, line:33:1, endln:47:10 + \_module_inst: work@sky130_fd_sc_hd__einvn (work@sky130_fd_sc_hd__einvn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__einvn.functional.v, line:33:1, endln:47:10 |vpiName:A |vpiDirection:1 |vpiLowConn: @@ -36187,7 +36187,7 @@ design: (work@sky130_fd_sc_hd__einvn) |vpiPort: \_port: (TE_B), line:36:5, endln:36:9 |vpiParent: - \_module: work@sky130_fd_sc_hd__einvn (work@sky130_fd_sc_hd__einvn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__einvn.functional.v, line:33:1, endln:47:10 + \_module_inst: work@sky130_fd_sc_hd__einvn (work@sky130_fd_sc_hd__einvn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__einvn.functional.v, line:33:1, endln:47:10 |vpiName:TE_B |vpiDirection:1 |vpiLowConn: @@ -36201,7 +36201,7 @@ design: (work@sky130_fd_sc_hd__einvn) |vpiPrimitive: \_gate: work@notif0 (work@sky130_fd_sc_hd__einvn.notif00), line:45:12, endln:45:45 |vpiParent: - \_module: work@sky130_fd_sc_hd__einvn (work@sky130_fd_sc_hd__einvn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__einvn.functional.v, line:33:1, endln:47:10 + \_module_inst: work@sky130_fd_sc_hd__einvn (work@sky130_fd_sc_hd__einvn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__einvn.functional.v, line:33:1, endln:47:10 |vpiDefName:work@notif0 |vpiName:notif00 |vpiFullName:work@sky130_fd_sc_hd__einvn.notif00 @@ -36258,7 +36258,7 @@ Processing: -cd cells/cells -DUNIT_DELAY -writepp -parse -nocache -nobuiltin -no design: (work@sky130_fd_sc_hd__clkdlybuf4s50) |vpiName:work@sky130_fd_sc_hd__clkdlybuf4s50 |uhdmallModules: -\_module: work@sky130_fd_sc_hd__clkdlybuf4s50 (work@sky130_fd_sc_hd__clkdlybuf4s50), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__clkdlybuf4s50.functional.v, line:34:1, endln:50:10 +\_module_inst: work@sky130_fd_sc_hd__clkdlybuf4s50 (work@sky130_fd_sc_hd__clkdlybuf4s50), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__clkdlybuf4s50.functional.v, line:34:1, endln:50:10 |vpiParent: \_design: (work@sky130_fd_sc_hd__clkdlybuf4s50) |vpiFullName:work@sky130_fd_sc_hd__clkdlybuf4s50 @@ -36266,26 +36266,26 @@ design: (work@sky130_fd_sc_hd__clkdlybuf4s50) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__clkdlybuf4s50.buf0_out_X), line:44:10, endln:44:20 |vpiParent: - \_module: work@sky130_fd_sc_hd__clkdlybuf4s50 (work@sky130_fd_sc_hd__clkdlybuf4s50), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__clkdlybuf4s50.functional.v, line:34:1, endln:50:10 + \_module_inst: work@sky130_fd_sc_hd__clkdlybuf4s50 (work@sky130_fd_sc_hd__clkdlybuf4s50), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__clkdlybuf4s50.functional.v, line:34:1, endln:50:10 |vpiName:buf0_out_X |vpiFullName:work@sky130_fd_sc_hd__clkdlybuf4s50.buf0_out_X |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__clkdlybuf4s50.X), line:35:5, endln:35:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__clkdlybuf4s50 (work@sky130_fd_sc_hd__clkdlybuf4s50), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__clkdlybuf4s50.functional.v, line:34:1, endln:50:10 + \_module_inst: work@sky130_fd_sc_hd__clkdlybuf4s50 (work@sky130_fd_sc_hd__clkdlybuf4s50), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__clkdlybuf4s50.functional.v, line:34:1, endln:50:10 |vpiName:X |vpiFullName:work@sky130_fd_sc_hd__clkdlybuf4s50.X |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__clkdlybuf4s50.A), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__clkdlybuf4s50 (work@sky130_fd_sc_hd__clkdlybuf4s50), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__clkdlybuf4s50.functional.v, line:34:1, endln:50:10 + \_module_inst: work@sky130_fd_sc_hd__clkdlybuf4s50 (work@sky130_fd_sc_hd__clkdlybuf4s50), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__clkdlybuf4s50.functional.v, line:34:1, endln:50:10 |vpiName:A |vpiFullName:work@sky130_fd_sc_hd__clkdlybuf4s50.A |vpiPort: \_port: (X), line:35:5, endln:35:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__clkdlybuf4s50 (work@sky130_fd_sc_hd__clkdlybuf4s50), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__clkdlybuf4s50.functional.v, line:34:1, endln:50:10 + \_module_inst: work@sky130_fd_sc_hd__clkdlybuf4s50 (work@sky130_fd_sc_hd__clkdlybuf4s50), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__clkdlybuf4s50.functional.v, line:34:1, endln:50:10 |vpiName:X |vpiDirection:2 |vpiLowConn: @@ -36297,7 +36297,7 @@ design: (work@sky130_fd_sc_hd__clkdlybuf4s50) |vpiPort: \_port: (A), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__clkdlybuf4s50 (work@sky130_fd_sc_hd__clkdlybuf4s50), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__clkdlybuf4s50.functional.v, line:34:1, endln:50:10 + \_module_inst: work@sky130_fd_sc_hd__clkdlybuf4s50 (work@sky130_fd_sc_hd__clkdlybuf4s50), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__clkdlybuf4s50.functional.v, line:34:1, endln:50:10 |vpiName:A |vpiDirection:1 |vpiLowConn: @@ -36307,14 +36307,14 @@ design: (work@sky130_fd_sc_hd__clkdlybuf4s50) |vpiTypedef: \_logic_typespec: , line:41:12, endln:41:12 |uhdmtopModules: -\_module: work@sky130_fd_sc_hd__clkdlybuf4s50 (work@sky130_fd_sc_hd__clkdlybuf4s50), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__clkdlybuf4s50.functional.v, line:34:1, endln:50:10 +\_module_inst: work@sky130_fd_sc_hd__clkdlybuf4s50 (work@sky130_fd_sc_hd__clkdlybuf4s50), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__clkdlybuf4s50.functional.v, line:34:1, endln:50:10 |vpiName:work@sky130_fd_sc_hd__clkdlybuf4s50 |vpiDefName:work@sky130_fd_sc_hd__clkdlybuf4s50 |vpiTop:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__clkdlybuf4s50.buf0_out_X), line:44:10, endln:44:20 |vpiParent: - \_module: work@sky130_fd_sc_hd__clkdlybuf4s50 (work@sky130_fd_sc_hd__clkdlybuf4s50), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__clkdlybuf4s50.functional.v, line:34:1, endln:50:10 + \_module_inst: work@sky130_fd_sc_hd__clkdlybuf4s50 (work@sky130_fd_sc_hd__clkdlybuf4s50), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__clkdlybuf4s50.functional.v, line:34:1, endln:50:10 |vpiTypespec: \_logic_typespec: , line:44:5, endln:44:9 |vpiName:buf0_out_X @@ -36323,7 +36323,7 @@ design: (work@sky130_fd_sc_hd__clkdlybuf4s50) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__clkdlybuf4s50.X), line:35:5, endln:35:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__clkdlybuf4s50 (work@sky130_fd_sc_hd__clkdlybuf4s50), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__clkdlybuf4s50.functional.v, line:34:1, endln:50:10 + \_module_inst: work@sky130_fd_sc_hd__clkdlybuf4s50 (work@sky130_fd_sc_hd__clkdlybuf4s50), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__clkdlybuf4s50.functional.v, line:34:1, endln:50:10 |vpiTypespec: \_logic_typespec: , line:40:12, endln:40:12 |vpiName:X @@ -36331,7 +36331,7 @@ design: (work@sky130_fd_sc_hd__clkdlybuf4s50) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__clkdlybuf4s50.A), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__clkdlybuf4s50 (work@sky130_fd_sc_hd__clkdlybuf4s50), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__clkdlybuf4s50.functional.v, line:34:1, endln:50:10 + \_module_inst: work@sky130_fd_sc_hd__clkdlybuf4s50 (work@sky130_fd_sc_hd__clkdlybuf4s50), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__clkdlybuf4s50.functional.v, line:34:1, endln:50:10 |vpiTypespec: \_logic_typespec: , line:41:12, endln:41:12 |vpiName:A @@ -36340,7 +36340,7 @@ design: (work@sky130_fd_sc_hd__clkdlybuf4s50) |vpiPort: \_port: (X), line:35:5, endln:35:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__clkdlybuf4s50 (work@sky130_fd_sc_hd__clkdlybuf4s50), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__clkdlybuf4s50.functional.v, line:34:1, endln:50:10 + \_module_inst: work@sky130_fd_sc_hd__clkdlybuf4s50 (work@sky130_fd_sc_hd__clkdlybuf4s50), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__clkdlybuf4s50.functional.v, line:34:1, endln:50:10 |vpiName:X |vpiDirection:2 |vpiLowConn: @@ -36354,7 +36354,7 @@ design: (work@sky130_fd_sc_hd__clkdlybuf4s50) |vpiPort: \_port: (A), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__clkdlybuf4s50 (work@sky130_fd_sc_hd__clkdlybuf4s50), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__clkdlybuf4s50.functional.v, line:34:1, endln:50:10 + \_module_inst: work@sky130_fd_sc_hd__clkdlybuf4s50 (work@sky130_fd_sc_hd__clkdlybuf4s50), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__clkdlybuf4s50.functional.v, line:34:1, endln:50:10 |vpiName:A |vpiDirection:1 |vpiLowConn: @@ -36368,7 +36368,7 @@ design: (work@sky130_fd_sc_hd__clkdlybuf4s50) |vpiPrimitive: \_gate: work@buf (work@sky130_fd_sc_hd__clkdlybuf4s50.buf0), line:47:9, endln:47:43 |vpiParent: - \_module: work@sky130_fd_sc_hd__clkdlybuf4s50 (work@sky130_fd_sc_hd__clkdlybuf4s50), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__clkdlybuf4s50.functional.v, line:34:1, endln:50:10 + \_module_inst: work@sky130_fd_sc_hd__clkdlybuf4s50 (work@sky130_fd_sc_hd__clkdlybuf4s50), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__clkdlybuf4s50.functional.v, line:34:1, endln:50:10 |vpiDefName:work@buf |vpiName:buf0 |vpiFullName:work@sky130_fd_sc_hd__clkdlybuf4s50.buf0 @@ -36403,7 +36403,7 @@ design: (work@sky130_fd_sc_hd__clkdlybuf4s50) |vpiPrimitive: \_gate: work@buf (work@sky130_fd_sc_hd__clkdlybuf4s50.buf1), line:48:9, endln:48:43 |vpiParent: - \_module: work@sky130_fd_sc_hd__clkdlybuf4s50 (work@sky130_fd_sc_hd__clkdlybuf4s50), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__clkdlybuf4s50.functional.v, line:34:1, endln:50:10 + \_module_inst: work@sky130_fd_sc_hd__clkdlybuf4s50 (work@sky130_fd_sc_hd__clkdlybuf4s50), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__clkdlybuf4s50.functional.v, line:34:1, endln:50:10 |vpiDefName:work@buf |vpiName:buf1 |vpiFullName:work@sky130_fd_sc_hd__clkdlybuf4s50.buf1 @@ -36446,7 +36446,7 @@ Processing: -cd cells/cells -DUNIT_DELAY -writepp -parse -nocache -nobuiltin -no design: (work@sky130_fd_sc_hd__or4b) |vpiName:work@sky130_fd_sc_hd__or4b |uhdmallModules: -\_module: work@sky130_fd_sc_hd__or4b (work@sky130_fd_sc_hd__or4b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or4b.functional.v, line:33:1, endln:57:10 +\_module_inst: work@sky130_fd_sc_hd__or4b (work@sky130_fd_sc_hd__or4b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or4b.functional.v, line:33:1, endln:57:10 |vpiParent: \_design: (work@sky130_fd_sc_hd__or4b) |vpiFullName:work@sky130_fd_sc_hd__or4b @@ -36454,51 +36454,51 @@ design: (work@sky130_fd_sc_hd__or4b) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__or4b.not0_out), line:49:10, endln:49:18 |vpiParent: - \_module: work@sky130_fd_sc_hd__or4b (work@sky130_fd_sc_hd__or4b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or4b.functional.v, line:33:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__or4b (work@sky130_fd_sc_hd__or4b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or4b.functional.v, line:33:1, endln:57:10 |vpiName:not0_out |vpiFullName:work@sky130_fd_sc_hd__or4b.not0_out |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__or4b.or0_out_X), line:50:10, endln:50:19 |vpiParent: - \_module: work@sky130_fd_sc_hd__or4b (work@sky130_fd_sc_hd__or4b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or4b.functional.v, line:33:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__or4b (work@sky130_fd_sc_hd__or4b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or4b.functional.v, line:33:1, endln:57:10 |vpiName:or0_out_X |vpiFullName:work@sky130_fd_sc_hd__or4b.or0_out_X |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__or4b.X), line:34:5, endln:34:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__or4b (work@sky130_fd_sc_hd__or4b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or4b.functional.v, line:33:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__or4b (work@sky130_fd_sc_hd__or4b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or4b.functional.v, line:33:1, endln:57:10 |vpiName:X |vpiFullName:work@sky130_fd_sc_hd__or4b.X |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__or4b.A), line:35:5, endln:35:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__or4b (work@sky130_fd_sc_hd__or4b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or4b.functional.v, line:33:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__or4b (work@sky130_fd_sc_hd__or4b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or4b.functional.v, line:33:1, endln:57:10 |vpiName:A |vpiFullName:work@sky130_fd_sc_hd__or4b.A |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__or4b.B), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__or4b (work@sky130_fd_sc_hd__or4b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or4b.functional.v, line:33:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__or4b (work@sky130_fd_sc_hd__or4b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or4b.functional.v, line:33:1, endln:57:10 |vpiName:B |vpiFullName:work@sky130_fd_sc_hd__or4b.B |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__or4b.C), line:37:5, endln:37:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__or4b (work@sky130_fd_sc_hd__or4b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or4b.functional.v, line:33:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__or4b (work@sky130_fd_sc_hd__or4b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or4b.functional.v, line:33:1, endln:57:10 |vpiName:C |vpiFullName:work@sky130_fd_sc_hd__or4b.C |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__or4b.D_N), line:38:5, endln:38:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__or4b (work@sky130_fd_sc_hd__or4b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or4b.functional.v, line:33:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__or4b (work@sky130_fd_sc_hd__or4b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or4b.functional.v, line:33:1, endln:57:10 |vpiName:D_N |vpiFullName:work@sky130_fd_sc_hd__or4b.D_N |vpiPort: \_port: (X), line:34:5, endln:34:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__or4b (work@sky130_fd_sc_hd__or4b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or4b.functional.v, line:33:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__or4b (work@sky130_fd_sc_hd__or4b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or4b.functional.v, line:33:1, endln:57:10 |vpiName:X |vpiDirection:2 |vpiLowConn: @@ -36510,7 +36510,7 @@ design: (work@sky130_fd_sc_hd__or4b) |vpiPort: \_port: (A), line:35:5, endln:35:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__or4b (work@sky130_fd_sc_hd__or4b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or4b.functional.v, line:33:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__or4b (work@sky130_fd_sc_hd__or4b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or4b.functional.v, line:33:1, endln:57:10 |vpiName:A |vpiDirection:1 |vpiLowConn: @@ -36522,7 +36522,7 @@ design: (work@sky130_fd_sc_hd__or4b) |vpiPort: \_port: (B), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__or4b (work@sky130_fd_sc_hd__or4b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or4b.functional.v, line:33:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__or4b (work@sky130_fd_sc_hd__or4b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or4b.functional.v, line:33:1, endln:57:10 |vpiName:B |vpiDirection:1 |vpiLowConn: @@ -36534,7 +36534,7 @@ design: (work@sky130_fd_sc_hd__or4b) |vpiPort: \_port: (C), line:37:5, endln:37:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__or4b (work@sky130_fd_sc_hd__or4b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or4b.functional.v, line:33:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__or4b (work@sky130_fd_sc_hd__or4b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or4b.functional.v, line:33:1, endln:57:10 |vpiName:C |vpiDirection:1 |vpiLowConn: @@ -36546,7 +36546,7 @@ design: (work@sky130_fd_sc_hd__or4b) |vpiPort: \_port: (D_N), line:38:5, endln:38:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__or4b (work@sky130_fd_sc_hd__or4b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or4b.functional.v, line:33:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__or4b (work@sky130_fd_sc_hd__or4b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or4b.functional.v, line:33:1, endln:57:10 |vpiName:D_N |vpiDirection:1 |vpiLowConn: @@ -36556,14 +36556,14 @@ design: (work@sky130_fd_sc_hd__or4b) |vpiTypedef: \_logic_typespec: , line:46:12, endln:46:12 |uhdmtopModules: -\_module: work@sky130_fd_sc_hd__or4b (work@sky130_fd_sc_hd__or4b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or4b.functional.v, line:33:1, endln:57:10 +\_module_inst: work@sky130_fd_sc_hd__or4b (work@sky130_fd_sc_hd__or4b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or4b.functional.v, line:33:1, endln:57:10 |vpiName:work@sky130_fd_sc_hd__or4b |vpiDefName:work@sky130_fd_sc_hd__or4b |vpiTop:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__or4b.not0_out), line:49:10, endln:49:18 |vpiParent: - \_module: work@sky130_fd_sc_hd__or4b (work@sky130_fd_sc_hd__or4b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or4b.functional.v, line:33:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__or4b (work@sky130_fd_sc_hd__or4b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or4b.functional.v, line:33:1, endln:57:10 |vpiTypespec: \_logic_typespec: , line:49:5, endln:49:9 |vpiName:not0_out @@ -36572,7 +36572,7 @@ design: (work@sky130_fd_sc_hd__or4b) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__or4b.or0_out_X), line:50:10, endln:50:19 |vpiParent: - \_module: work@sky130_fd_sc_hd__or4b (work@sky130_fd_sc_hd__or4b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or4b.functional.v, line:33:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__or4b (work@sky130_fd_sc_hd__or4b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or4b.functional.v, line:33:1, endln:57:10 |vpiTypespec: \_logic_typespec: , line:50:5, endln:50:9 |vpiName:or0_out_X @@ -36581,7 +36581,7 @@ design: (work@sky130_fd_sc_hd__or4b) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__or4b.X), line:34:5, endln:34:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__or4b (work@sky130_fd_sc_hd__or4b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or4b.functional.v, line:33:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__or4b (work@sky130_fd_sc_hd__or4b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or4b.functional.v, line:33:1, endln:57:10 |vpiTypespec: \_logic_typespec: , line:42:12, endln:42:12 |vpiName:X @@ -36589,7 +36589,7 @@ design: (work@sky130_fd_sc_hd__or4b) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__or4b.A), line:35:5, endln:35:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__or4b (work@sky130_fd_sc_hd__or4b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or4b.functional.v, line:33:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__or4b (work@sky130_fd_sc_hd__or4b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or4b.functional.v, line:33:1, endln:57:10 |vpiTypespec: \_logic_typespec: , line:43:12, endln:43:12 |vpiName:A @@ -36597,7 +36597,7 @@ design: (work@sky130_fd_sc_hd__or4b) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__or4b.B), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__or4b (work@sky130_fd_sc_hd__or4b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or4b.functional.v, line:33:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__or4b (work@sky130_fd_sc_hd__or4b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or4b.functional.v, line:33:1, endln:57:10 |vpiTypespec: \_logic_typespec: , line:44:12, endln:44:12 |vpiName:B @@ -36605,7 +36605,7 @@ design: (work@sky130_fd_sc_hd__or4b) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__or4b.C), line:37:5, endln:37:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__or4b (work@sky130_fd_sc_hd__or4b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or4b.functional.v, line:33:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__or4b (work@sky130_fd_sc_hd__or4b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or4b.functional.v, line:33:1, endln:57:10 |vpiTypespec: \_logic_typespec: , line:45:12, endln:45:12 |vpiName:C @@ -36613,7 +36613,7 @@ design: (work@sky130_fd_sc_hd__or4b) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__or4b.D_N), line:38:5, endln:38:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__or4b (work@sky130_fd_sc_hd__or4b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or4b.functional.v, line:33:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__or4b (work@sky130_fd_sc_hd__or4b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or4b.functional.v, line:33:1, endln:57:10 |vpiTypespec: \_logic_typespec: , line:46:12, endln:46:12 |vpiName:D_N @@ -36622,7 +36622,7 @@ design: (work@sky130_fd_sc_hd__or4b) |vpiPort: \_port: (X), line:34:5, endln:34:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__or4b (work@sky130_fd_sc_hd__or4b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or4b.functional.v, line:33:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__or4b (work@sky130_fd_sc_hd__or4b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or4b.functional.v, line:33:1, endln:57:10 |vpiName:X |vpiDirection:2 |vpiLowConn: @@ -36636,7 +36636,7 @@ design: (work@sky130_fd_sc_hd__or4b) |vpiPort: \_port: (A), line:35:5, endln:35:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__or4b (work@sky130_fd_sc_hd__or4b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or4b.functional.v, line:33:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__or4b (work@sky130_fd_sc_hd__or4b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or4b.functional.v, line:33:1, endln:57:10 |vpiName:A |vpiDirection:1 |vpiLowConn: @@ -36650,7 +36650,7 @@ design: (work@sky130_fd_sc_hd__or4b) |vpiPort: \_port: (B), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__or4b (work@sky130_fd_sc_hd__or4b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or4b.functional.v, line:33:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__or4b (work@sky130_fd_sc_hd__or4b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or4b.functional.v, line:33:1, endln:57:10 |vpiName:B |vpiDirection:1 |vpiLowConn: @@ -36664,7 +36664,7 @@ design: (work@sky130_fd_sc_hd__or4b) |vpiPort: \_port: (C), line:37:5, endln:37:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__or4b (work@sky130_fd_sc_hd__or4b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or4b.functional.v, line:33:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__or4b (work@sky130_fd_sc_hd__or4b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or4b.functional.v, line:33:1, endln:57:10 |vpiName:C |vpiDirection:1 |vpiLowConn: @@ -36678,7 +36678,7 @@ design: (work@sky130_fd_sc_hd__or4b) |vpiPort: \_port: (D_N), line:38:5, endln:38:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__or4b (work@sky130_fd_sc_hd__or4b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or4b.functional.v, line:33:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__or4b (work@sky130_fd_sc_hd__or4b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or4b.functional.v, line:33:1, endln:57:10 |vpiName:D_N |vpiDirection:1 |vpiLowConn: @@ -36692,7 +36692,7 @@ design: (work@sky130_fd_sc_hd__or4b) |vpiPrimitive: \_gate: work@not (work@sky130_fd_sc_hd__or4b.not0), line:53:9, endln:53:44 |vpiParent: - \_module: work@sky130_fd_sc_hd__or4b (work@sky130_fd_sc_hd__or4b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or4b.functional.v, line:33:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__or4b (work@sky130_fd_sc_hd__or4b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or4b.functional.v, line:33:1, endln:57:10 |vpiDefName:work@not |vpiName:not0 |vpiFullName:work@sky130_fd_sc_hd__or4b.not0 @@ -36727,7 +36727,7 @@ design: (work@sky130_fd_sc_hd__or4b) |vpiPrimitive: \_gate: work@or (work@sky130_fd_sc_hd__or4b.or0), line:54:9, endln:54:44 |vpiParent: - \_module: work@sky130_fd_sc_hd__or4b (work@sky130_fd_sc_hd__or4b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or4b.functional.v, line:33:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__or4b (work@sky130_fd_sc_hd__or4b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or4b.functional.v, line:33:1, endln:57:10 |vpiDefName:work@or |vpiName:or0 |vpiFullName:work@sky130_fd_sc_hd__or4b.or0 @@ -36804,7 +36804,7 @@ design: (work@sky130_fd_sc_hd__or4b) |vpiPrimitive: \_gate: work@buf (work@sky130_fd_sc_hd__or4b.buf0), line:55:9, endln:55:44 |vpiParent: - \_module: work@sky130_fd_sc_hd__or4b (work@sky130_fd_sc_hd__or4b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or4b.functional.v, line:33:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__or4b (work@sky130_fd_sc_hd__or4b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or4b.functional.v, line:33:1, endln:57:10 |vpiDefName:work@buf |vpiName:buf0 |vpiFullName:work@sky130_fd_sc_hd__or4b.buf0 @@ -36847,7 +36847,7 @@ Processing: -cd cells/cells -DUNIT_DELAY -writepp -parse -nocache -nobuiltin -no design: (work@sky130_fd_sc_hd__dlymetal6s4s) |vpiName:work@sky130_fd_sc_hd__dlymetal6s4s |uhdmallModules: -\_module: work@sky130_fd_sc_hd__dlymetal6s4s (work@sky130_fd_sc_hd__dlymetal6s4s), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlymetal6s4s.functional.v, line:34:1, endln:50:10 +\_module_inst: work@sky130_fd_sc_hd__dlymetal6s4s (work@sky130_fd_sc_hd__dlymetal6s4s), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlymetal6s4s.functional.v, line:34:1, endln:50:10 |vpiParent: \_design: (work@sky130_fd_sc_hd__dlymetal6s4s) |vpiFullName:work@sky130_fd_sc_hd__dlymetal6s4s @@ -36855,26 +36855,26 @@ design: (work@sky130_fd_sc_hd__dlymetal6s4s) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__dlymetal6s4s.buf0_out_X), line:44:10, endln:44:20 |vpiParent: - \_module: work@sky130_fd_sc_hd__dlymetal6s4s (work@sky130_fd_sc_hd__dlymetal6s4s), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlymetal6s4s.functional.v, line:34:1, endln:50:10 + \_module_inst: work@sky130_fd_sc_hd__dlymetal6s4s (work@sky130_fd_sc_hd__dlymetal6s4s), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlymetal6s4s.functional.v, line:34:1, endln:50:10 |vpiName:buf0_out_X |vpiFullName:work@sky130_fd_sc_hd__dlymetal6s4s.buf0_out_X |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__dlymetal6s4s.X), line:35:5, endln:35:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__dlymetal6s4s (work@sky130_fd_sc_hd__dlymetal6s4s), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlymetal6s4s.functional.v, line:34:1, endln:50:10 + \_module_inst: work@sky130_fd_sc_hd__dlymetal6s4s (work@sky130_fd_sc_hd__dlymetal6s4s), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlymetal6s4s.functional.v, line:34:1, endln:50:10 |vpiName:X |vpiFullName:work@sky130_fd_sc_hd__dlymetal6s4s.X |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__dlymetal6s4s.A), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__dlymetal6s4s (work@sky130_fd_sc_hd__dlymetal6s4s), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlymetal6s4s.functional.v, line:34:1, endln:50:10 + \_module_inst: work@sky130_fd_sc_hd__dlymetal6s4s (work@sky130_fd_sc_hd__dlymetal6s4s), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlymetal6s4s.functional.v, line:34:1, endln:50:10 |vpiName:A |vpiFullName:work@sky130_fd_sc_hd__dlymetal6s4s.A |vpiPort: \_port: (X), line:35:5, endln:35:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__dlymetal6s4s (work@sky130_fd_sc_hd__dlymetal6s4s), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlymetal6s4s.functional.v, line:34:1, endln:50:10 + \_module_inst: work@sky130_fd_sc_hd__dlymetal6s4s (work@sky130_fd_sc_hd__dlymetal6s4s), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlymetal6s4s.functional.v, line:34:1, endln:50:10 |vpiName:X |vpiDirection:2 |vpiLowConn: @@ -36886,7 +36886,7 @@ design: (work@sky130_fd_sc_hd__dlymetal6s4s) |vpiPort: \_port: (A), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__dlymetal6s4s (work@sky130_fd_sc_hd__dlymetal6s4s), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlymetal6s4s.functional.v, line:34:1, endln:50:10 + \_module_inst: work@sky130_fd_sc_hd__dlymetal6s4s (work@sky130_fd_sc_hd__dlymetal6s4s), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlymetal6s4s.functional.v, line:34:1, endln:50:10 |vpiName:A |vpiDirection:1 |vpiLowConn: @@ -36896,14 +36896,14 @@ design: (work@sky130_fd_sc_hd__dlymetal6s4s) |vpiTypedef: \_logic_typespec: , line:41:12, endln:41:12 |uhdmtopModules: -\_module: work@sky130_fd_sc_hd__dlymetal6s4s (work@sky130_fd_sc_hd__dlymetal6s4s), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlymetal6s4s.functional.v, line:34:1, endln:50:10 +\_module_inst: work@sky130_fd_sc_hd__dlymetal6s4s (work@sky130_fd_sc_hd__dlymetal6s4s), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlymetal6s4s.functional.v, line:34:1, endln:50:10 |vpiName:work@sky130_fd_sc_hd__dlymetal6s4s |vpiDefName:work@sky130_fd_sc_hd__dlymetal6s4s |vpiTop:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__dlymetal6s4s.buf0_out_X), line:44:10, endln:44:20 |vpiParent: - \_module: work@sky130_fd_sc_hd__dlymetal6s4s (work@sky130_fd_sc_hd__dlymetal6s4s), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlymetal6s4s.functional.v, line:34:1, endln:50:10 + \_module_inst: work@sky130_fd_sc_hd__dlymetal6s4s (work@sky130_fd_sc_hd__dlymetal6s4s), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlymetal6s4s.functional.v, line:34:1, endln:50:10 |vpiTypespec: \_logic_typespec: , line:44:5, endln:44:9 |vpiName:buf0_out_X @@ -36912,7 +36912,7 @@ design: (work@sky130_fd_sc_hd__dlymetal6s4s) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__dlymetal6s4s.X), line:35:5, endln:35:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__dlymetal6s4s (work@sky130_fd_sc_hd__dlymetal6s4s), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlymetal6s4s.functional.v, line:34:1, endln:50:10 + \_module_inst: work@sky130_fd_sc_hd__dlymetal6s4s (work@sky130_fd_sc_hd__dlymetal6s4s), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlymetal6s4s.functional.v, line:34:1, endln:50:10 |vpiTypespec: \_logic_typespec: , line:40:12, endln:40:12 |vpiName:X @@ -36920,7 +36920,7 @@ design: (work@sky130_fd_sc_hd__dlymetal6s4s) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__dlymetal6s4s.A), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__dlymetal6s4s (work@sky130_fd_sc_hd__dlymetal6s4s), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlymetal6s4s.functional.v, line:34:1, endln:50:10 + \_module_inst: work@sky130_fd_sc_hd__dlymetal6s4s (work@sky130_fd_sc_hd__dlymetal6s4s), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlymetal6s4s.functional.v, line:34:1, endln:50:10 |vpiTypespec: \_logic_typespec: , line:41:12, endln:41:12 |vpiName:A @@ -36929,7 +36929,7 @@ design: (work@sky130_fd_sc_hd__dlymetal6s4s) |vpiPort: \_port: (X), line:35:5, endln:35:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__dlymetal6s4s (work@sky130_fd_sc_hd__dlymetal6s4s), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlymetal6s4s.functional.v, line:34:1, endln:50:10 + \_module_inst: work@sky130_fd_sc_hd__dlymetal6s4s (work@sky130_fd_sc_hd__dlymetal6s4s), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlymetal6s4s.functional.v, line:34:1, endln:50:10 |vpiName:X |vpiDirection:2 |vpiLowConn: @@ -36943,7 +36943,7 @@ design: (work@sky130_fd_sc_hd__dlymetal6s4s) |vpiPort: \_port: (A), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__dlymetal6s4s (work@sky130_fd_sc_hd__dlymetal6s4s), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlymetal6s4s.functional.v, line:34:1, endln:50:10 + \_module_inst: work@sky130_fd_sc_hd__dlymetal6s4s (work@sky130_fd_sc_hd__dlymetal6s4s), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlymetal6s4s.functional.v, line:34:1, endln:50:10 |vpiName:A |vpiDirection:1 |vpiLowConn: @@ -36957,7 +36957,7 @@ design: (work@sky130_fd_sc_hd__dlymetal6s4s) |vpiPrimitive: \_gate: work@buf (work@sky130_fd_sc_hd__dlymetal6s4s.buf0), line:47:9, endln:47:43 |vpiParent: - \_module: work@sky130_fd_sc_hd__dlymetal6s4s (work@sky130_fd_sc_hd__dlymetal6s4s), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlymetal6s4s.functional.v, line:34:1, endln:50:10 + \_module_inst: work@sky130_fd_sc_hd__dlymetal6s4s (work@sky130_fd_sc_hd__dlymetal6s4s), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlymetal6s4s.functional.v, line:34:1, endln:50:10 |vpiDefName:work@buf |vpiName:buf0 |vpiFullName:work@sky130_fd_sc_hd__dlymetal6s4s.buf0 @@ -36992,7 +36992,7 @@ design: (work@sky130_fd_sc_hd__dlymetal6s4s) |vpiPrimitive: \_gate: work@buf (work@sky130_fd_sc_hd__dlymetal6s4s.buf1), line:48:9, endln:48:43 |vpiParent: - \_module: work@sky130_fd_sc_hd__dlymetal6s4s (work@sky130_fd_sc_hd__dlymetal6s4s), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlymetal6s4s.functional.v, line:34:1, endln:50:10 + \_module_inst: work@sky130_fd_sc_hd__dlymetal6s4s (work@sky130_fd_sc_hd__dlymetal6s4s), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlymetal6s4s.functional.v, line:34:1, endln:50:10 |vpiDefName:work@buf |vpiName:buf1 |vpiFullName:work@sky130_fd_sc_hd__dlymetal6s4s.buf1 @@ -37045,7 +37045,7 @@ Processing: -cd cells/cells -DUNIT_DELAY -writepp -parse -nocache -nobuiltin -no design: (work@sky130_fd_sc_hd__a2bb2o) |vpiName:work@sky130_fd_sc_hd__a2bb2o |uhdmallModules: -\_module: work@sky130_fd_sc_hd__a2bb2o (work@sky130_fd_sc_hd__a2bb2o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a2bb2o.functional.v, line:36:1, endln:62:10 +\_module_inst: work@sky130_fd_sc_hd__a2bb2o (work@sky130_fd_sc_hd__a2bb2o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a2bb2o.functional.v, line:36:1, endln:62:10 |vpiParent: \_design: (work@sky130_fd_sc_hd__a2bb2o) |vpiFullName:work@sky130_fd_sc_hd__a2bb2o @@ -37053,58 +37053,58 @@ design: (work@sky130_fd_sc_hd__a2bb2o) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a2bb2o.and0_out), line:52:10, endln:52:18 |vpiParent: - \_module: work@sky130_fd_sc_hd__a2bb2o (work@sky130_fd_sc_hd__a2bb2o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a2bb2o.functional.v, line:36:1, endln:62:10 + \_module_inst: work@sky130_fd_sc_hd__a2bb2o (work@sky130_fd_sc_hd__a2bb2o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a2bb2o.functional.v, line:36:1, endln:62:10 |vpiName:and0_out |vpiFullName:work@sky130_fd_sc_hd__a2bb2o.and0_out |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a2bb2o.nor0_out), line:53:10, endln:53:18 |vpiParent: - \_module: work@sky130_fd_sc_hd__a2bb2o (work@sky130_fd_sc_hd__a2bb2o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a2bb2o.functional.v, line:36:1, endln:62:10 + \_module_inst: work@sky130_fd_sc_hd__a2bb2o (work@sky130_fd_sc_hd__a2bb2o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a2bb2o.functional.v, line:36:1, endln:62:10 |vpiName:nor0_out |vpiFullName:work@sky130_fd_sc_hd__a2bb2o.nor0_out |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a2bb2o.or0_out_X), line:54:10, endln:54:19 |vpiParent: - \_module: work@sky130_fd_sc_hd__a2bb2o (work@sky130_fd_sc_hd__a2bb2o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a2bb2o.functional.v, line:36:1, endln:62:10 + \_module_inst: work@sky130_fd_sc_hd__a2bb2o (work@sky130_fd_sc_hd__a2bb2o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a2bb2o.functional.v, line:36:1, endln:62:10 |vpiName:or0_out_X |vpiFullName:work@sky130_fd_sc_hd__a2bb2o.or0_out_X |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a2bb2o.X), line:37:5, endln:37:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__a2bb2o (work@sky130_fd_sc_hd__a2bb2o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a2bb2o.functional.v, line:36:1, endln:62:10 + \_module_inst: work@sky130_fd_sc_hd__a2bb2o (work@sky130_fd_sc_hd__a2bb2o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a2bb2o.functional.v, line:36:1, endln:62:10 |vpiName:X |vpiFullName:work@sky130_fd_sc_hd__a2bb2o.X |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a2bb2o.A1_N), line:38:5, endln:38:9 |vpiParent: - \_module: work@sky130_fd_sc_hd__a2bb2o (work@sky130_fd_sc_hd__a2bb2o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a2bb2o.functional.v, line:36:1, endln:62:10 + \_module_inst: work@sky130_fd_sc_hd__a2bb2o (work@sky130_fd_sc_hd__a2bb2o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a2bb2o.functional.v, line:36:1, endln:62:10 |vpiName:A1_N |vpiFullName:work@sky130_fd_sc_hd__a2bb2o.A1_N |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a2bb2o.A2_N), line:39:5, endln:39:9 |vpiParent: - \_module: work@sky130_fd_sc_hd__a2bb2o (work@sky130_fd_sc_hd__a2bb2o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a2bb2o.functional.v, line:36:1, endln:62:10 + \_module_inst: work@sky130_fd_sc_hd__a2bb2o (work@sky130_fd_sc_hd__a2bb2o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a2bb2o.functional.v, line:36:1, endln:62:10 |vpiName:A2_N |vpiFullName:work@sky130_fd_sc_hd__a2bb2o.A2_N |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a2bb2o.B1), line:40:5, endln:40:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a2bb2o (work@sky130_fd_sc_hd__a2bb2o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a2bb2o.functional.v, line:36:1, endln:62:10 + \_module_inst: work@sky130_fd_sc_hd__a2bb2o (work@sky130_fd_sc_hd__a2bb2o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a2bb2o.functional.v, line:36:1, endln:62:10 |vpiName:B1 |vpiFullName:work@sky130_fd_sc_hd__a2bb2o.B1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a2bb2o.B2), line:41:5, endln:41:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a2bb2o (work@sky130_fd_sc_hd__a2bb2o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a2bb2o.functional.v, line:36:1, endln:62:10 + \_module_inst: work@sky130_fd_sc_hd__a2bb2o (work@sky130_fd_sc_hd__a2bb2o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a2bb2o.functional.v, line:36:1, endln:62:10 |vpiName:B2 |vpiFullName:work@sky130_fd_sc_hd__a2bb2o.B2 |vpiPort: \_port: (X), line:37:5, endln:37:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__a2bb2o (work@sky130_fd_sc_hd__a2bb2o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a2bb2o.functional.v, line:36:1, endln:62:10 + \_module_inst: work@sky130_fd_sc_hd__a2bb2o (work@sky130_fd_sc_hd__a2bb2o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a2bb2o.functional.v, line:36:1, endln:62:10 |vpiName:X |vpiDirection:2 |vpiLowConn: @@ -37116,7 +37116,7 @@ design: (work@sky130_fd_sc_hd__a2bb2o) |vpiPort: \_port: (A1_N), line:38:5, endln:38:9 |vpiParent: - \_module: work@sky130_fd_sc_hd__a2bb2o (work@sky130_fd_sc_hd__a2bb2o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a2bb2o.functional.v, line:36:1, endln:62:10 + \_module_inst: work@sky130_fd_sc_hd__a2bb2o (work@sky130_fd_sc_hd__a2bb2o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a2bb2o.functional.v, line:36:1, endln:62:10 |vpiName:A1_N |vpiDirection:1 |vpiLowConn: @@ -37128,7 +37128,7 @@ design: (work@sky130_fd_sc_hd__a2bb2o) |vpiPort: \_port: (A2_N), line:39:5, endln:39:9 |vpiParent: - \_module: work@sky130_fd_sc_hd__a2bb2o (work@sky130_fd_sc_hd__a2bb2o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a2bb2o.functional.v, line:36:1, endln:62:10 + \_module_inst: work@sky130_fd_sc_hd__a2bb2o (work@sky130_fd_sc_hd__a2bb2o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a2bb2o.functional.v, line:36:1, endln:62:10 |vpiName:A2_N |vpiDirection:1 |vpiLowConn: @@ -37140,7 +37140,7 @@ design: (work@sky130_fd_sc_hd__a2bb2o) |vpiPort: \_port: (B1), line:40:5, endln:40:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a2bb2o (work@sky130_fd_sc_hd__a2bb2o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a2bb2o.functional.v, line:36:1, endln:62:10 + \_module_inst: work@sky130_fd_sc_hd__a2bb2o (work@sky130_fd_sc_hd__a2bb2o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a2bb2o.functional.v, line:36:1, endln:62:10 |vpiName:B1 |vpiDirection:1 |vpiLowConn: @@ -37152,7 +37152,7 @@ design: (work@sky130_fd_sc_hd__a2bb2o) |vpiPort: \_port: (B2), line:41:5, endln:41:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a2bb2o (work@sky130_fd_sc_hd__a2bb2o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a2bb2o.functional.v, line:36:1, endln:62:10 + \_module_inst: work@sky130_fd_sc_hd__a2bb2o (work@sky130_fd_sc_hd__a2bb2o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a2bb2o.functional.v, line:36:1, endln:62:10 |vpiName:B2 |vpiDirection:1 |vpiLowConn: @@ -37162,14 +37162,14 @@ design: (work@sky130_fd_sc_hd__a2bb2o) |vpiTypedef: \_logic_typespec: , line:49:12, endln:49:12 |uhdmtopModules: -\_module: work@sky130_fd_sc_hd__a2bb2o (work@sky130_fd_sc_hd__a2bb2o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a2bb2o.functional.v, line:36:1, endln:62:10 +\_module_inst: work@sky130_fd_sc_hd__a2bb2o (work@sky130_fd_sc_hd__a2bb2o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a2bb2o.functional.v, line:36:1, endln:62:10 |vpiName:work@sky130_fd_sc_hd__a2bb2o |vpiDefName:work@sky130_fd_sc_hd__a2bb2o |vpiTop:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a2bb2o.and0_out), line:52:10, endln:52:18 |vpiParent: - \_module: work@sky130_fd_sc_hd__a2bb2o (work@sky130_fd_sc_hd__a2bb2o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a2bb2o.functional.v, line:36:1, endln:62:10 + \_module_inst: work@sky130_fd_sc_hd__a2bb2o (work@sky130_fd_sc_hd__a2bb2o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a2bb2o.functional.v, line:36:1, endln:62:10 |vpiTypespec: \_logic_typespec: , line:52:5, endln:52:9 |vpiName:and0_out @@ -37178,7 +37178,7 @@ design: (work@sky130_fd_sc_hd__a2bb2o) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a2bb2o.nor0_out), line:53:10, endln:53:18 |vpiParent: - \_module: work@sky130_fd_sc_hd__a2bb2o (work@sky130_fd_sc_hd__a2bb2o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a2bb2o.functional.v, line:36:1, endln:62:10 + \_module_inst: work@sky130_fd_sc_hd__a2bb2o (work@sky130_fd_sc_hd__a2bb2o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a2bb2o.functional.v, line:36:1, endln:62:10 |vpiTypespec: \_logic_typespec: , line:53:5, endln:53:9 |vpiName:nor0_out @@ -37187,7 +37187,7 @@ design: (work@sky130_fd_sc_hd__a2bb2o) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a2bb2o.or0_out_X), line:54:10, endln:54:19 |vpiParent: - \_module: work@sky130_fd_sc_hd__a2bb2o (work@sky130_fd_sc_hd__a2bb2o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a2bb2o.functional.v, line:36:1, endln:62:10 + \_module_inst: work@sky130_fd_sc_hd__a2bb2o (work@sky130_fd_sc_hd__a2bb2o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a2bb2o.functional.v, line:36:1, endln:62:10 |vpiTypespec: \_logic_typespec: , line:54:5, endln:54:9 |vpiName:or0_out_X @@ -37196,7 +37196,7 @@ design: (work@sky130_fd_sc_hd__a2bb2o) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a2bb2o.X), line:37:5, endln:37:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__a2bb2o (work@sky130_fd_sc_hd__a2bb2o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a2bb2o.functional.v, line:36:1, endln:62:10 + \_module_inst: work@sky130_fd_sc_hd__a2bb2o (work@sky130_fd_sc_hd__a2bb2o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a2bb2o.functional.v, line:36:1, endln:62:10 |vpiTypespec: \_logic_typespec: , line:45:12, endln:45:12 |vpiName:X @@ -37204,7 +37204,7 @@ design: (work@sky130_fd_sc_hd__a2bb2o) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a2bb2o.A1_N), line:38:5, endln:38:9 |vpiParent: - \_module: work@sky130_fd_sc_hd__a2bb2o (work@sky130_fd_sc_hd__a2bb2o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a2bb2o.functional.v, line:36:1, endln:62:10 + \_module_inst: work@sky130_fd_sc_hd__a2bb2o (work@sky130_fd_sc_hd__a2bb2o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a2bb2o.functional.v, line:36:1, endln:62:10 |vpiTypespec: \_logic_typespec: , line:46:12, endln:46:12 |vpiName:A1_N @@ -37212,7 +37212,7 @@ design: (work@sky130_fd_sc_hd__a2bb2o) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a2bb2o.A2_N), line:39:5, endln:39:9 |vpiParent: - \_module: work@sky130_fd_sc_hd__a2bb2o (work@sky130_fd_sc_hd__a2bb2o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a2bb2o.functional.v, line:36:1, endln:62:10 + \_module_inst: work@sky130_fd_sc_hd__a2bb2o (work@sky130_fd_sc_hd__a2bb2o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a2bb2o.functional.v, line:36:1, endln:62:10 |vpiTypespec: \_logic_typespec: , line:47:12, endln:47:12 |vpiName:A2_N @@ -37220,7 +37220,7 @@ design: (work@sky130_fd_sc_hd__a2bb2o) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a2bb2o.B1), line:40:5, endln:40:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a2bb2o (work@sky130_fd_sc_hd__a2bb2o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a2bb2o.functional.v, line:36:1, endln:62:10 + \_module_inst: work@sky130_fd_sc_hd__a2bb2o (work@sky130_fd_sc_hd__a2bb2o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a2bb2o.functional.v, line:36:1, endln:62:10 |vpiTypespec: \_logic_typespec: , line:48:12, endln:48:12 |vpiName:B1 @@ -37228,7 +37228,7 @@ design: (work@sky130_fd_sc_hd__a2bb2o) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a2bb2o.B2), line:41:5, endln:41:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a2bb2o (work@sky130_fd_sc_hd__a2bb2o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a2bb2o.functional.v, line:36:1, endln:62:10 + \_module_inst: work@sky130_fd_sc_hd__a2bb2o (work@sky130_fd_sc_hd__a2bb2o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a2bb2o.functional.v, line:36:1, endln:62:10 |vpiTypespec: \_logic_typespec: , line:49:12, endln:49:12 |vpiName:B2 @@ -37237,7 +37237,7 @@ design: (work@sky130_fd_sc_hd__a2bb2o) |vpiPort: \_port: (X), line:37:5, endln:37:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__a2bb2o (work@sky130_fd_sc_hd__a2bb2o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a2bb2o.functional.v, line:36:1, endln:62:10 + \_module_inst: work@sky130_fd_sc_hd__a2bb2o (work@sky130_fd_sc_hd__a2bb2o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a2bb2o.functional.v, line:36:1, endln:62:10 |vpiName:X |vpiDirection:2 |vpiLowConn: @@ -37251,7 +37251,7 @@ design: (work@sky130_fd_sc_hd__a2bb2o) |vpiPort: \_port: (A1_N), line:38:5, endln:38:9 |vpiParent: - \_module: work@sky130_fd_sc_hd__a2bb2o (work@sky130_fd_sc_hd__a2bb2o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a2bb2o.functional.v, line:36:1, endln:62:10 + \_module_inst: work@sky130_fd_sc_hd__a2bb2o (work@sky130_fd_sc_hd__a2bb2o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a2bb2o.functional.v, line:36:1, endln:62:10 |vpiName:A1_N |vpiDirection:1 |vpiLowConn: @@ -37265,7 +37265,7 @@ design: (work@sky130_fd_sc_hd__a2bb2o) |vpiPort: \_port: (A2_N), line:39:5, endln:39:9 |vpiParent: - \_module: work@sky130_fd_sc_hd__a2bb2o (work@sky130_fd_sc_hd__a2bb2o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a2bb2o.functional.v, line:36:1, endln:62:10 + \_module_inst: work@sky130_fd_sc_hd__a2bb2o (work@sky130_fd_sc_hd__a2bb2o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a2bb2o.functional.v, line:36:1, endln:62:10 |vpiName:A2_N |vpiDirection:1 |vpiLowConn: @@ -37279,7 +37279,7 @@ design: (work@sky130_fd_sc_hd__a2bb2o) |vpiPort: \_port: (B1), line:40:5, endln:40:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a2bb2o (work@sky130_fd_sc_hd__a2bb2o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a2bb2o.functional.v, line:36:1, endln:62:10 + \_module_inst: work@sky130_fd_sc_hd__a2bb2o (work@sky130_fd_sc_hd__a2bb2o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a2bb2o.functional.v, line:36:1, endln:62:10 |vpiName:B1 |vpiDirection:1 |vpiLowConn: @@ -37293,7 +37293,7 @@ design: (work@sky130_fd_sc_hd__a2bb2o) |vpiPort: \_port: (B2), line:41:5, endln:41:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a2bb2o (work@sky130_fd_sc_hd__a2bb2o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a2bb2o.functional.v, line:36:1, endln:62:10 + \_module_inst: work@sky130_fd_sc_hd__a2bb2o (work@sky130_fd_sc_hd__a2bb2o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a2bb2o.functional.v, line:36:1, endln:62:10 |vpiName:B2 |vpiDirection:1 |vpiLowConn: @@ -37307,7 +37307,7 @@ design: (work@sky130_fd_sc_hd__a2bb2o) |vpiPrimitive: \_gate: work@and (work@sky130_fd_sc_hd__a2bb2o.and0), line:57:9, endln:57:45 |vpiParent: - \_module: work@sky130_fd_sc_hd__a2bb2o (work@sky130_fd_sc_hd__a2bb2o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a2bb2o.functional.v, line:36:1, endln:62:10 + \_module_inst: work@sky130_fd_sc_hd__a2bb2o (work@sky130_fd_sc_hd__a2bb2o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a2bb2o.functional.v, line:36:1, endln:62:10 |vpiDefName:work@and |vpiName:and0 |vpiFullName:work@sky130_fd_sc_hd__a2bb2o.and0 @@ -37356,7 +37356,7 @@ design: (work@sky130_fd_sc_hd__a2bb2o) |vpiPrimitive: \_gate: work@nor (work@sky130_fd_sc_hd__a2bb2o.nor0), line:58:9, endln:58:45 |vpiParent: - \_module: work@sky130_fd_sc_hd__a2bb2o (work@sky130_fd_sc_hd__a2bb2o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a2bb2o.functional.v, line:36:1, endln:62:10 + \_module_inst: work@sky130_fd_sc_hd__a2bb2o (work@sky130_fd_sc_hd__a2bb2o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a2bb2o.functional.v, line:36:1, endln:62:10 |vpiDefName:work@nor |vpiName:nor0 |vpiFullName:work@sky130_fd_sc_hd__a2bb2o.nor0 @@ -37405,7 +37405,7 @@ design: (work@sky130_fd_sc_hd__a2bb2o) |vpiPrimitive: \_gate: work@or (work@sky130_fd_sc_hd__a2bb2o.or0), line:59:9, endln:59:45 |vpiParent: - \_module: work@sky130_fd_sc_hd__a2bb2o (work@sky130_fd_sc_hd__a2bb2o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a2bb2o.functional.v, line:36:1, endln:62:10 + \_module_inst: work@sky130_fd_sc_hd__a2bb2o (work@sky130_fd_sc_hd__a2bb2o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a2bb2o.functional.v, line:36:1, endln:62:10 |vpiDefName:work@or |vpiName:or0 |vpiFullName:work@sky130_fd_sc_hd__a2bb2o.or0 @@ -37454,7 +37454,7 @@ design: (work@sky130_fd_sc_hd__a2bb2o) |vpiPrimitive: \_gate: work@buf (work@sky130_fd_sc_hd__a2bb2o.buf0), line:60:9, endln:60:45 |vpiParent: - \_module: work@sky130_fd_sc_hd__a2bb2o (work@sky130_fd_sc_hd__a2bb2o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a2bb2o.functional.v, line:36:1, endln:62:10 + \_module_inst: work@sky130_fd_sc_hd__a2bb2o (work@sky130_fd_sc_hd__a2bb2o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a2bb2o.functional.v, line:36:1, endln:62:10 |vpiDefName:work@buf |vpiName:buf0 |vpiFullName:work@sky130_fd_sc_hd__a2bb2o.buf0 @@ -37687,7 +37687,7 @@ design: (work@sky130_fd_sc_hd__edfxbp) |vpiSize:3 |STRING:? 1 1 : 1 |uhdmallModules: -\_module: work@sky130_fd_sc_hd__edfxbp (work@sky130_fd_sc_hd__edfxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__edfxbp.functional.v, line:38:1, endln:63:10 +\_module_inst: work@sky130_fd_sc_hd__edfxbp (work@sky130_fd_sc_hd__edfxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__edfxbp.functional.v, line:38:1, endln:63:10 |vpiParent: \_design: (work@sky130_fd_sc_hd__edfxbp) |vpiFullName:work@sky130_fd_sc_hd__edfxbp @@ -37695,51 +37695,51 @@ design: (work@sky130_fd_sc_hd__edfxbp) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__edfxbp.buf_Q), line:54:10, endln:54:15 |vpiParent: - \_module: work@sky130_fd_sc_hd__edfxbp (work@sky130_fd_sc_hd__edfxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__edfxbp.functional.v, line:38:1, endln:63:10 + \_module_inst: work@sky130_fd_sc_hd__edfxbp (work@sky130_fd_sc_hd__edfxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__edfxbp.functional.v, line:38:1, endln:63:10 |vpiName:buf_Q |vpiFullName:work@sky130_fd_sc_hd__edfxbp.buf_Q |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__edfxbp.mux_out), line:55:10, endln:55:17 |vpiParent: - \_module: work@sky130_fd_sc_hd__edfxbp (work@sky130_fd_sc_hd__edfxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__edfxbp.functional.v, line:38:1, endln:63:10 + \_module_inst: work@sky130_fd_sc_hd__edfxbp (work@sky130_fd_sc_hd__edfxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__edfxbp.functional.v, line:38:1, endln:63:10 |vpiName:mux_out |vpiFullName:work@sky130_fd_sc_hd__edfxbp.mux_out |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__edfxbp.Q), line:39:5, endln:39:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__edfxbp (work@sky130_fd_sc_hd__edfxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__edfxbp.functional.v, line:38:1, endln:63:10 + \_module_inst: work@sky130_fd_sc_hd__edfxbp (work@sky130_fd_sc_hd__edfxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__edfxbp.functional.v, line:38:1, endln:63:10 |vpiName:Q |vpiFullName:work@sky130_fd_sc_hd__edfxbp.Q |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__edfxbp.Q_N), line:40:5, endln:40:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__edfxbp (work@sky130_fd_sc_hd__edfxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__edfxbp.functional.v, line:38:1, endln:63:10 + \_module_inst: work@sky130_fd_sc_hd__edfxbp (work@sky130_fd_sc_hd__edfxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__edfxbp.functional.v, line:38:1, endln:63:10 |vpiName:Q_N |vpiFullName:work@sky130_fd_sc_hd__edfxbp.Q_N |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__edfxbp.CLK), line:41:5, endln:41:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__edfxbp (work@sky130_fd_sc_hd__edfxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__edfxbp.functional.v, line:38:1, endln:63:10 + \_module_inst: work@sky130_fd_sc_hd__edfxbp (work@sky130_fd_sc_hd__edfxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__edfxbp.functional.v, line:38:1, endln:63:10 |vpiName:CLK |vpiFullName:work@sky130_fd_sc_hd__edfxbp.CLK |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__edfxbp.D), line:42:5, endln:42:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__edfxbp (work@sky130_fd_sc_hd__edfxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__edfxbp.functional.v, line:38:1, endln:63:10 + \_module_inst: work@sky130_fd_sc_hd__edfxbp (work@sky130_fd_sc_hd__edfxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__edfxbp.functional.v, line:38:1, endln:63:10 |vpiName:D |vpiFullName:work@sky130_fd_sc_hd__edfxbp.D |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__edfxbp.DE), line:43:5, endln:43:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__edfxbp (work@sky130_fd_sc_hd__edfxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__edfxbp.functional.v, line:38:1, endln:63:10 + \_module_inst: work@sky130_fd_sc_hd__edfxbp (work@sky130_fd_sc_hd__edfxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__edfxbp.functional.v, line:38:1, endln:63:10 |vpiName:DE |vpiFullName:work@sky130_fd_sc_hd__edfxbp.DE |vpiPort: \_port: (Q), line:39:5, endln:39:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__edfxbp (work@sky130_fd_sc_hd__edfxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__edfxbp.functional.v, line:38:1, endln:63:10 + \_module_inst: work@sky130_fd_sc_hd__edfxbp (work@sky130_fd_sc_hd__edfxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__edfxbp.functional.v, line:38:1, endln:63:10 |vpiName:Q |vpiDirection:2 |vpiLowConn: @@ -37751,7 +37751,7 @@ design: (work@sky130_fd_sc_hd__edfxbp) |vpiPort: \_port: (Q_N), line:40:5, endln:40:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__edfxbp (work@sky130_fd_sc_hd__edfxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__edfxbp.functional.v, line:38:1, endln:63:10 + \_module_inst: work@sky130_fd_sc_hd__edfxbp (work@sky130_fd_sc_hd__edfxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__edfxbp.functional.v, line:38:1, endln:63:10 |vpiName:Q_N |vpiDirection:2 |vpiLowConn: @@ -37763,7 +37763,7 @@ design: (work@sky130_fd_sc_hd__edfxbp) |vpiPort: \_port: (CLK), line:41:5, endln:41:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__edfxbp (work@sky130_fd_sc_hd__edfxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__edfxbp.functional.v, line:38:1, endln:63:10 + \_module_inst: work@sky130_fd_sc_hd__edfxbp (work@sky130_fd_sc_hd__edfxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__edfxbp.functional.v, line:38:1, endln:63:10 |vpiName:CLK |vpiDirection:1 |vpiLowConn: @@ -37775,7 +37775,7 @@ design: (work@sky130_fd_sc_hd__edfxbp) |vpiPort: \_port: (D), line:42:5, endln:42:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__edfxbp (work@sky130_fd_sc_hd__edfxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__edfxbp.functional.v, line:38:1, endln:63:10 + \_module_inst: work@sky130_fd_sc_hd__edfxbp (work@sky130_fd_sc_hd__edfxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__edfxbp.functional.v, line:38:1, endln:63:10 |vpiName:D |vpiDirection:1 |vpiLowConn: @@ -37787,7 +37787,7 @@ design: (work@sky130_fd_sc_hd__edfxbp) |vpiPort: \_port: (DE), line:43:5, endln:43:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__edfxbp (work@sky130_fd_sc_hd__edfxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__edfxbp.functional.v, line:38:1, endln:63:10 + \_module_inst: work@sky130_fd_sc_hd__edfxbp (work@sky130_fd_sc_hd__edfxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__edfxbp.functional.v, line:38:1, endln:63:10 |vpiName:DE |vpiDirection:1 |vpiLowConn: @@ -37797,14 +37797,14 @@ design: (work@sky130_fd_sc_hd__edfxbp) |vpiTypedef: \_logic_typespec: , line:51:12, endln:51:12 |uhdmtopModules: -\_module: work@sky130_fd_sc_hd__edfxbp (work@sky130_fd_sc_hd__edfxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__edfxbp.functional.v, line:38:1, endln:63:10 +\_module_inst: work@sky130_fd_sc_hd__edfxbp (work@sky130_fd_sc_hd__edfxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__edfxbp.functional.v, line:38:1, endln:63:10 |vpiName:work@sky130_fd_sc_hd__edfxbp |vpiDefName:work@sky130_fd_sc_hd__edfxbp |vpiTop:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__edfxbp.buf_Q), line:54:10, endln:54:15 |vpiParent: - \_module: work@sky130_fd_sc_hd__edfxbp (work@sky130_fd_sc_hd__edfxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__edfxbp.functional.v, line:38:1, endln:63:10 + \_module_inst: work@sky130_fd_sc_hd__edfxbp (work@sky130_fd_sc_hd__edfxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__edfxbp.functional.v, line:38:1, endln:63:10 |vpiTypespec: \_logic_typespec: , line:54:5, endln:54:9 |vpiName:buf_Q @@ -37813,7 +37813,7 @@ design: (work@sky130_fd_sc_hd__edfxbp) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__edfxbp.mux_out), line:55:10, endln:55:17 |vpiParent: - \_module: work@sky130_fd_sc_hd__edfxbp (work@sky130_fd_sc_hd__edfxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__edfxbp.functional.v, line:38:1, endln:63:10 + \_module_inst: work@sky130_fd_sc_hd__edfxbp (work@sky130_fd_sc_hd__edfxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__edfxbp.functional.v, line:38:1, endln:63:10 |vpiTypespec: \_logic_typespec: , line:55:5, endln:55:9 |vpiName:mux_out @@ -37822,7 +37822,7 @@ design: (work@sky130_fd_sc_hd__edfxbp) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__edfxbp.Q), line:39:5, endln:39:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__edfxbp (work@sky130_fd_sc_hd__edfxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__edfxbp.functional.v, line:38:1, endln:63:10 + \_module_inst: work@sky130_fd_sc_hd__edfxbp (work@sky130_fd_sc_hd__edfxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__edfxbp.functional.v, line:38:1, endln:63:10 |vpiTypespec: \_logic_typespec: , line:47:12, endln:47:12 |vpiName:Q @@ -37830,7 +37830,7 @@ design: (work@sky130_fd_sc_hd__edfxbp) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__edfxbp.Q_N), line:40:5, endln:40:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__edfxbp (work@sky130_fd_sc_hd__edfxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__edfxbp.functional.v, line:38:1, endln:63:10 + \_module_inst: work@sky130_fd_sc_hd__edfxbp (work@sky130_fd_sc_hd__edfxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__edfxbp.functional.v, line:38:1, endln:63:10 |vpiTypespec: \_logic_typespec: , line:48:12, endln:48:12 |vpiName:Q_N @@ -37838,7 +37838,7 @@ design: (work@sky130_fd_sc_hd__edfxbp) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__edfxbp.CLK), line:41:5, endln:41:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__edfxbp (work@sky130_fd_sc_hd__edfxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__edfxbp.functional.v, line:38:1, endln:63:10 + \_module_inst: work@sky130_fd_sc_hd__edfxbp (work@sky130_fd_sc_hd__edfxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__edfxbp.functional.v, line:38:1, endln:63:10 |vpiTypespec: \_logic_typespec: , line:49:12, endln:49:12 |vpiName:CLK @@ -37846,7 +37846,7 @@ design: (work@sky130_fd_sc_hd__edfxbp) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__edfxbp.D), line:42:5, endln:42:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__edfxbp (work@sky130_fd_sc_hd__edfxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__edfxbp.functional.v, line:38:1, endln:63:10 + \_module_inst: work@sky130_fd_sc_hd__edfxbp (work@sky130_fd_sc_hd__edfxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__edfxbp.functional.v, line:38:1, endln:63:10 |vpiTypespec: \_logic_typespec: , line:50:12, endln:50:12 |vpiName:D @@ -37854,7 +37854,7 @@ design: (work@sky130_fd_sc_hd__edfxbp) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__edfxbp.DE), line:43:5, endln:43:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__edfxbp (work@sky130_fd_sc_hd__edfxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__edfxbp.functional.v, line:38:1, endln:63:10 + \_module_inst: work@sky130_fd_sc_hd__edfxbp (work@sky130_fd_sc_hd__edfxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__edfxbp.functional.v, line:38:1, endln:63:10 |vpiTypespec: \_logic_typespec: , line:51:12, endln:51:12 |vpiName:DE @@ -37863,7 +37863,7 @@ design: (work@sky130_fd_sc_hd__edfxbp) |vpiPort: \_port: (Q), line:39:5, endln:39:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__edfxbp (work@sky130_fd_sc_hd__edfxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__edfxbp.functional.v, line:38:1, endln:63:10 + \_module_inst: work@sky130_fd_sc_hd__edfxbp (work@sky130_fd_sc_hd__edfxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__edfxbp.functional.v, line:38:1, endln:63:10 |vpiName:Q |vpiDirection:2 |vpiLowConn: @@ -37877,7 +37877,7 @@ design: (work@sky130_fd_sc_hd__edfxbp) |vpiPort: \_port: (Q_N), line:40:5, endln:40:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__edfxbp (work@sky130_fd_sc_hd__edfxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__edfxbp.functional.v, line:38:1, endln:63:10 + \_module_inst: work@sky130_fd_sc_hd__edfxbp (work@sky130_fd_sc_hd__edfxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__edfxbp.functional.v, line:38:1, endln:63:10 |vpiName:Q_N |vpiDirection:2 |vpiLowConn: @@ -37891,7 +37891,7 @@ design: (work@sky130_fd_sc_hd__edfxbp) |vpiPort: \_port: (CLK), line:41:5, endln:41:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__edfxbp (work@sky130_fd_sc_hd__edfxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__edfxbp.functional.v, line:38:1, endln:63:10 + \_module_inst: work@sky130_fd_sc_hd__edfxbp (work@sky130_fd_sc_hd__edfxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__edfxbp.functional.v, line:38:1, endln:63:10 |vpiName:CLK |vpiDirection:1 |vpiLowConn: @@ -37905,7 +37905,7 @@ design: (work@sky130_fd_sc_hd__edfxbp) |vpiPort: \_port: (D), line:42:5, endln:42:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__edfxbp (work@sky130_fd_sc_hd__edfxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__edfxbp.functional.v, line:38:1, endln:63:10 + \_module_inst: work@sky130_fd_sc_hd__edfxbp (work@sky130_fd_sc_hd__edfxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__edfxbp.functional.v, line:38:1, endln:63:10 |vpiName:D |vpiDirection:1 |vpiLowConn: @@ -37919,7 +37919,7 @@ design: (work@sky130_fd_sc_hd__edfxbp) |vpiPort: \_port: (DE), line:43:5, endln:43:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__edfxbp (work@sky130_fd_sc_hd__edfxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__edfxbp.functional.v, line:38:1, endln:63:10 + \_module_inst: work@sky130_fd_sc_hd__edfxbp (work@sky130_fd_sc_hd__edfxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__edfxbp.functional.v, line:38:1, endln:63:10 |vpiName:DE |vpiDirection:1 |vpiLowConn: @@ -37933,7 +37933,7 @@ design: (work@sky130_fd_sc_hd__edfxbp) |vpiPrimitive: \_udp: work@sky130_fd_sc_hd__udp_mux_2to1 (work@sky130_fd_sc_hd__edfxbp.mux_2to10), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__edfxbp.functional.v, line:58:5, endln:58:84 |vpiParent: - \_module: work@sky130_fd_sc_hd__edfxbp (work@sky130_fd_sc_hd__edfxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__edfxbp.functional.v, line:38:1, endln:63:10 + \_module_inst: work@sky130_fd_sc_hd__edfxbp (work@sky130_fd_sc_hd__edfxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__edfxbp.functional.v, line:38:1, endln:63:10 |vpiDefName:work@sky130_fd_sc_hd__udp_mux_2to1 |vpiName:mux_2to10 |vpiFullName:work@sky130_fd_sc_hd__edfxbp.mux_2to10 @@ -37942,7 +37942,7 @@ design: (work@sky130_fd_sc_hd__edfxbp) |vpiPrimitive: \_udp: work@sky130_fd_sc_hd__udp_dff$P (work@sky130_fd_sc_hd__edfxbp.dff0), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__edfxbp.functional.v, line:59:5, endln:59:73 |vpiParent: - \_module: work@sky130_fd_sc_hd__edfxbp (work@sky130_fd_sc_hd__edfxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__edfxbp.functional.v, line:38:1, endln:63:10 + \_module_inst: work@sky130_fd_sc_hd__edfxbp (work@sky130_fd_sc_hd__edfxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__edfxbp.functional.v, line:38:1, endln:63:10 |vpiDefName:work@sky130_fd_sc_hd__udp_dff$P |vpiName:dff0 |vpiFullName:work@sky130_fd_sc_hd__edfxbp.dff0 @@ -37951,7 +37951,7 @@ design: (work@sky130_fd_sc_hd__edfxbp) |vpiPrimitive: \_gate: work@buf (work@sky130_fd_sc_hd__edfxbp.buf0), line:60:47, endln:60:83 |vpiParent: - \_module: work@sky130_fd_sc_hd__edfxbp (work@sky130_fd_sc_hd__edfxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__edfxbp.functional.v, line:38:1, endln:63:10 + \_module_inst: work@sky130_fd_sc_hd__edfxbp (work@sky130_fd_sc_hd__edfxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__edfxbp.functional.v, line:38:1, endln:63:10 |vpiDefName:work@buf |vpiName:buf0 |vpiFullName:work@sky130_fd_sc_hd__edfxbp.buf0 @@ -37986,7 +37986,7 @@ design: (work@sky130_fd_sc_hd__edfxbp) |vpiPrimitive: \_gate: work@not (work@sky130_fd_sc_hd__edfxbp.not0), line:61:47, endln:61:83 |vpiParent: - \_module: work@sky130_fd_sc_hd__edfxbp (work@sky130_fd_sc_hd__edfxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__edfxbp.functional.v, line:38:1, endln:63:10 + \_module_inst: work@sky130_fd_sc_hd__edfxbp (work@sky130_fd_sc_hd__edfxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__edfxbp.functional.v, line:38:1, endln:63:10 |vpiDefName:work@not |vpiName:not0 |vpiFullName:work@sky130_fd_sc_hd__edfxbp.not0 @@ -38151,7 +38151,7 @@ design: (work@sky130_fd_sc_hd__dfrbp) |vpiSize:3 |STRING:? b ?x : 0 : 0 |uhdmallModules: -\_module: work@sky130_fd_sc_hd__dfrbp (work@sky130_fd_sc_hd__dfrbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfrbp.functional.v, line:36:1, endln:61:10 +\_module_inst: work@sky130_fd_sc_hd__dfrbp (work@sky130_fd_sc_hd__dfrbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfrbp.functional.v, line:36:1, endln:61:10 |vpiParent: \_design: (work@sky130_fd_sc_hd__dfrbp) |vpiFullName:work@sky130_fd_sc_hd__dfrbp @@ -38159,51 +38159,51 @@ design: (work@sky130_fd_sc_hd__dfrbp) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__dfrbp.buf_Q), line:52:10, endln:52:15 |vpiParent: - \_module: work@sky130_fd_sc_hd__dfrbp (work@sky130_fd_sc_hd__dfrbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfrbp.functional.v, line:36:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__dfrbp (work@sky130_fd_sc_hd__dfrbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfrbp.functional.v, line:36:1, endln:61:10 |vpiName:buf_Q |vpiFullName:work@sky130_fd_sc_hd__dfrbp.buf_Q |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__dfrbp.RESET), line:53:10, endln:53:15 |vpiParent: - \_module: work@sky130_fd_sc_hd__dfrbp (work@sky130_fd_sc_hd__dfrbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfrbp.functional.v, line:36:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__dfrbp (work@sky130_fd_sc_hd__dfrbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfrbp.functional.v, line:36:1, endln:61:10 |vpiName:RESET |vpiFullName:work@sky130_fd_sc_hd__dfrbp.RESET |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__dfrbp.Q), line:37:5, endln:37:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__dfrbp (work@sky130_fd_sc_hd__dfrbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfrbp.functional.v, line:36:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__dfrbp (work@sky130_fd_sc_hd__dfrbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfrbp.functional.v, line:36:1, endln:61:10 |vpiName:Q |vpiFullName:work@sky130_fd_sc_hd__dfrbp.Q |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__dfrbp.Q_N), line:38:5, endln:38:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__dfrbp (work@sky130_fd_sc_hd__dfrbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfrbp.functional.v, line:36:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__dfrbp (work@sky130_fd_sc_hd__dfrbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfrbp.functional.v, line:36:1, endln:61:10 |vpiName:Q_N |vpiFullName:work@sky130_fd_sc_hd__dfrbp.Q_N |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__dfrbp.CLK), line:39:5, endln:39:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__dfrbp (work@sky130_fd_sc_hd__dfrbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfrbp.functional.v, line:36:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__dfrbp (work@sky130_fd_sc_hd__dfrbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfrbp.functional.v, line:36:1, endln:61:10 |vpiName:CLK |vpiFullName:work@sky130_fd_sc_hd__dfrbp.CLK |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__dfrbp.D), line:40:5, endln:40:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__dfrbp (work@sky130_fd_sc_hd__dfrbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfrbp.functional.v, line:36:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__dfrbp (work@sky130_fd_sc_hd__dfrbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfrbp.functional.v, line:36:1, endln:61:10 |vpiName:D |vpiFullName:work@sky130_fd_sc_hd__dfrbp.D |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__dfrbp.RESET_B), line:41:5, endln:41:12 |vpiParent: - \_module: work@sky130_fd_sc_hd__dfrbp (work@sky130_fd_sc_hd__dfrbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfrbp.functional.v, line:36:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__dfrbp (work@sky130_fd_sc_hd__dfrbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfrbp.functional.v, line:36:1, endln:61:10 |vpiName:RESET_B |vpiFullName:work@sky130_fd_sc_hd__dfrbp.RESET_B |vpiPort: \_port: (Q), line:37:5, endln:37:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__dfrbp (work@sky130_fd_sc_hd__dfrbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfrbp.functional.v, line:36:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__dfrbp (work@sky130_fd_sc_hd__dfrbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfrbp.functional.v, line:36:1, endln:61:10 |vpiName:Q |vpiDirection:2 |vpiLowConn: @@ -38215,7 +38215,7 @@ design: (work@sky130_fd_sc_hd__dfrbp) |vpiPort: \_port: (Q_N), line:38:5, endln:38:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__dfrbp (work@sky130_fd_sc_hd__dfrbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfrbp.functional.v, line:36:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__dfrbp (work@sky130_fd_sc_hd__dfrbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfrbp.functional.v, line:36:1, endln:61:10 |vpiName:Q_N |vpiDirection:2 |vpiLowConn: @@ -38227,7 +38227,7 @@ design: (work@sky130_fd_sc_hd__dfrbp) |vpiPort: \_port: (CLK), line:39:5, endln:39:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__dfrbp (work@sky130_fd_sc_hd__dfrbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfrbp.functional.v, line:36:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__dfrbp (work@sky130_fd_sc_hd__dfrbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfrbp.functional.v, line:36:1, endln:61:10 |vpiName:CLK |vpiDirection:1 |vpiLowConn: @@ -38239,7 +38239,7 @@ design: (work@sky130_fd_sc_hd__dfrbp) |vpiPort: \_port: (D), line:40:5, endln:40:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__dfrbp (work@sky130_fd_sc_hd__dfrbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfrbp.functional.v, line:36:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__dfrbp (work@sky130_fd_sc_hd__dfrbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfrbp.functional.v, line:36:1, endln:61:10 |vpiName:D |vpiDirection:1 |vpiLowConn: @@ -38251,7 +38251,7 @@ design: (work@sky130_fd_sc_hd__dfrbp) |vpiPort: \_port: (RESET_B), line:41:5, endln:41:12 |vpiParent: - \_module: work@sky130_fd_sc_hd__dfrbp (work@sky130_fd_sc_hd__dfrbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfrbp.functional.v, line:36:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__dfrbp (work@sky130_fd_sc_hd__dfrbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfrbp.functional.v, line:36:1, endln:61:10 |vpiName:RESET_B |vpiDirection:1 |vpiLowConn: @@ -38261,14 +38261,14 @@ design: (work@sky130_fd_sc_hd__dfrbp) |vpiTypedef: \_logic_typespec: , line:49:12, endln:49:12 |uhdmtopModules: -\_module: work@sky130_fd_sc_hd__dfrbp (work@sky130_fd_sc_hd__dfrbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfrbp.functional.v, line:36:1, endln:61:10 +\_module_inst: work@sky130_fd_sc_hd__dfrbp (work@sky130_fd_sc_hd__dfrbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfrbp.functional.v, line:36:1, endln:61:10 |vpiName:work@sky130_fd_sc_hd__dfrbp |vpiDefName:work@sky130_fd_sc_hd__dfrbp |vpiTop:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__dfrbp.buf_Q), line:52:10, endln:52:15 |vpiParent: - \_module: work@sky130_fd_sc_hd__dfrbp (work@sky130_fd_sc_hd__dfrbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfrbp.functional.v, line:36:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__dfrbp (work@sky130_fd_sc_hd__dfrbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfrbp.functional.v, line:36:1, endln:61:10 |vpiTypespec: \_logic_typespec: , line:52:5, endln:52:9 |vpiName:buf_Q @@ -38277,7 +38277,7 @@ design: (work@sky130_fd_sc_hd__dfrbp) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__dfrbp.RESET), line:53:10, endln:53:15 |vpiParent: - \_module: work@sky130_fd_sc_hd__dfrbp (work@sky130_fd_sc_hd__dfrbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfrbp.functional.v, line:36:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__dfrbp (work@sky130_fd_sc_hd__dfrbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfrbp.functional.v, line:36:1, endln:61:10 |vpiTypespec: \_logic_typespec: , line:53:5, endln:53:9 |vpiName:RESET @@ -38286,7 +38286,7 @@ design: (work@sky130_fd_sc_hd__dfrbp) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__dfrbp.Q), line:37:5, endln:37:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__dfrbp (work@sky130_fd_sc_hd__dfrbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfrbp.functional.v, line:36:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__dfrbp (work@sky130_fd_sc_hd__dfrbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfrbp.functional.v, line:36:1, endln:61:10 |vpiTypespec: \_logic_typespec: , line:45:12, endln:45:12 |vpiName:Q @@ -38294,7 +38294,7 @@ design: (work@sky130_fd_sc_hd__dfrbp) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__dfrbp.Q_N), line:38:5, endln:38:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__dfrbp (work@sky130_fd_sc_hd__dfrbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfrbp.functional.v, line:36:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__dfrbp (work@sky130_fd_sc_hd__dfrbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfrbp.functional.v, line:36:1, endln:61:10 |vpiTypespec: \_logic_typespec: , line:46:12, endln:46:12 |vpiName:Q_N @@ -38302,7 +38302,7 @@ design: (work@sky130_fd_sc_hd__dfrbp) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__dfrbp.CLK), line:39:5, endln:39:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__dfrbp (work@sky130_fd_sc_hd__dfrbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfrbp.functional.v, line:36:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__dfrbp (work@sky130_fd_sc_hd__dfrbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfrbp.functional.v, line:36:1, endln:61:10 |vpiTypespec: \_logic_typespec: , line:47:12, endln:47:12 |vpiName:CLK @@ -38310,7 +38310,7 @@ design: (work@sky130_fd_sc_hd__dfrbp) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__dfrbp.D), line:40:5, endln:40:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__dfrbp (work@sky130_fd_sc_hd__dfrbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfrbp.functional.v, line:36:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__dfrbp (work@sky130_fd_sc_hd__dfrbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfrbp.functional.v, line:36:1, endln:61:10 |vpiTypespec: \_logic_typespec: , line:48:12, endln:48:12 |vpiName:D @@ -38318,7 +38318,7 @@ design: (work@sky130_fd_sc_hd__dfrbp) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__dfrbp.RESET_B), line:41:5, endln:41:12 |vpiParent: - \_module: work@sky130_fd_sc_hd__dfrbp (work@sky130_fd_sc_hd__dfrbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfrbp.functional.v, line:36:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__dfrbp (work@sky130_fd_sc_hd__dfrbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfrbp.functional.v, line:36:1, endln:61:10 |vpiTypespec: \_logic_typespec: , line:49:12, endln:49:12 |vpiName:RESET_B @@ -38327,7 +38327,7 @@ design: (work@sky130_fd_sc_hd__dfrbp) |vpiPort: \_port: (Q), line:37:5, endln:37:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__dfrbp (work@sky130_fd_sc_hd__dfrbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfrbp.functional.v, line:36:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__dfrbp (work@sky130_fd_sc_hd__dfrbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfrbp.functional.v, line:36:1, endln:61:10 |vpiName:Q |vpiDirection:2 |vpiLowConn: @@ -38341,7 +38341,7 @@ design: (work@sky130_fd_sc_hd__dfrbp) |vpiPort: \_port: (Q_N), line:38:5, endln:38:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__dfrbp (work@sky130_fd_sc_hd__dfrbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfrbp.functional.v, line:36:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__dfrbp (work@sky130_fd_sc_hd__dfrbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfrbp.functional.v, line:36:1, endln:61:10 |vpiName:Q_N |vpiDirection:2 |vpiLowConn: @@ -38355,7 +38355,7 @@ design: (work@sky130_fd_sc_hd__dfrbp) |vpiPort: \_port: (CLK), line:39:5, endln:39:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__dfrbp (work@sky130_fd_sc_hd__dfrbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfrbp.functional.v, line:36:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__dfrbp (work@sky130_fd_sc_hd__dfrbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfrbp.functional.v, line:36:1, endln:61:10 |vpiName:CLK |vpiDirection:1 |vpiLowConn: @@ -38369,7 +38369,7 @@ design: (work@sky130_fd_sc_hd__dfrbp) |vpiPort: \_port: (D), line:40:5, endln:40:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__dfrbp (work@sky130_fd_sc_hd__dfrbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfrbp.functional.v, line:36:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__dfrbp (work@sky130_fd_sc_hd__dfrbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfrbp.functional.v, line:36:1, endln:61:10 |vpiName:D |vpiDirection:1 |vpiLowConn: @@ -38383,7 +38383,7 @@ design: (work@sky130_fd_sc_hd__dfrbp) |vpiPort: \_port: (RESET_B), line:41:5, endln:41:12 |vpiParent: - \_module: work@sky130_fd_sc_hd__dfrbp (work@sky130_fd_sc_hd__dfrbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfrbp.functional.v, line:36:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__dfrbp (work@sky130_fd_sc_hd__dfrbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfrbp.functional.v, line:36:1, endln:61:10 |vpiName:RESET_B |vpiDirection:1 |vpiLowConn: @@ -38397,7 +38397,7 @@ design: (work@sky130_fd_sc_hd__dfrbp) |vpiPrimitive: \_gate: work@not (work@sky130_fd_sc_hd__dfrbp.not0), line:56:45, endln:56:75 |vpiParent: - \_module: work@sky130_fd_sc_hd__dfrbp (work@sky130_fd_sc_hd__dfrbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfrbp.functional.v, line:36:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__dfrbp (work@sky130_fd_sc_hd__dfrbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfrbp.functional.v, line:36:1, endln:61:10 |vpiDefName:work@not |vpiName:not0 |vpiFullName:work@sky130_fd_sc_hd__dfrbp.not0 @@ -38432,7 +38432,7 @@ design: (work@sky130_fd_sc_hd__dfrbp) |vpiPrimitive: \_udp: work@sky130_fd_sc_hd__udp_dff$PR (work@sky130_fd_sc_hd__dfrbp.dff0), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfrbp.functional.v, line:57:5, endln:57:65 |vpiParent: - \_module: work@sky130_fd_sc_hd__dfrbp (work@sky130_fd_sc_hd__dfrbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfrbp.functional.v, line:36:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__dfrbp (work@sky130_fd_sc_hd__dfrbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfrbp.functional.v, line:36:1, endln:61:10 |vpiDefName:work@sky130_fd_sc_hd__udp_dff$PR |vpiName:dff0 |vpiFullName:work@sky130_fd_sc_hd__dfrbp.dff0 @@ -38441,7 +38441,7 @@ design: (work@sky130_fd_sc_hd__dfrbp) |vpiPrimitive: \_gate: work@buf (work@sky130_fd_sc_hd__dfrbp.buf0), line:58:45, endln:58:75 |vpiParent: - \_module: work@sky130_fd_sc_hd__dfrbp (work@sky130_fd_sc_hd__dfrbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfrbp.functional.v, line:36:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__dfrbp (work@sky130_fd_sc_hd__dfrbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfrbp.functional.v, line:36:1, endln:61:10 |vpiDefName:work@buf |vpiName:buf0 |vpiFullName:work@sky130_fd_sc_hd__dfrbp.buf0 @@ -38476,7 +38476,7 @@ design: (work@sky130_fd_sc_hd__dfrbp) |vpiPrimitive: \_gate: work@not (work@sky130_fd_sc_hd__dfrbp.not1), line:59:45, endln:59:75 |vpiParent: - \_module: work@sky130_fd_sc_hd__dfrbp (work@sky130_fd_sc_hd__dfrbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfrbp.functional.v, line:36:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__dfrbp (work@sky130_fd_sc_hd__dfrbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfrbp.functional.v, line:36:1, endln:61:10 |vpiDefName:work@not |vpiName:not1 |vpiFullName:work@sky130_fd_sc_hd__dfrbp.not1 @@ -38593,7 +38593,7 @@ design: (work@sky130_fd_sc_hd__sdlclkp) |vpiSize:2 |STRING:1 x : 1 : 1 |uhdmallModules: -\_module: work@sky130_fd_sc_hd__sdlclkp (work@sky130_fd_sc_hd__sdlclkp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdlclkp.functional.v, line:36:1, endln:62:10 +\_module_inst: work@sky130_fd_sc_hd__sdlclkp (work@sky130_fd_sc_hd__sdlclkp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdlclkp.functional.v, line:36:1, endln:62:10 |vpiParent: \_design: (work@sky130_fd_sc_hd__sdlclkp) |vpiFullName:work@sky130_fd_sc_hd__sdlclkp @@ -38601,59 +38601,59 @@ design: (work@sky130_fd_sc_hd__sdlclkp) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__sdlclkp.m0), line:50:10, endln:50:12 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdlclkp (work@sky130_fd_sc_hd__sdlclkp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdlclkp.functional.v, line:36:1, endln:62:10 + \_module_inst: work@sky130_fd_sc_hd__sdlclkp (work@sky130_fd_sc_hd__sdlclkp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdlclkp.functional.v, line:36:1, endln:62:10 |vpiName:m0 |vpiFullName:work@sky130_fd_sc_hd__sdlclkp.m0 |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__sdlclkp.m0n), line:51:10, endln:51:13 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdlclkp (work@sky130_fd_sc_hd__sdlclkp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdlclkp.functional.v, line:36:1, endln:62:10 + \_module_inst: work@sky130_fd_sc_hd__sdlclkp (work@sky130_fd_sc_hd__sdlclkp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdlclkp.functional.v, line:36:1, endln:62:10 |vpiName:m0n |vpiFullName:work@sky130_fd_sc_hd__sdlclkp.m0n |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__sdlclkp.clkn), line:52:10, endln:52:14 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdlclkp (work@sky130_fd_sc_hd__sdlclkp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdlclkp.functional.v, line:36:1, endln:62:10 + \_module_inst: work@sky130_fd_sc_hd__sdlclkp (work@sky130_fd_sc_hd__sdlclkp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdlclkp.functional.v, line:36:1, endln:62:10 |vpiName:clkn |vpiFullName:work@sky130_fd_sc_hd__sdlclkp.clkn |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__sdlclkp.SCE_GATE), line:53:10, endln:53:18 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdlclkp (work@sky130_fd_sc_hd__sdlclkp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdlclkp.functional.v, line:36:1, endln:62:10 + \_module_inst: work@sky130_fd_sc_hd__sdlclkp (work@sky130_fd_sc_hd__sdlclkp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdlclkp.functional.v, line:36:1, endln:62:10 |vpiName:SCE_GATE |vpiFullName:work@sky130_fd_sc_hd__sdlclkp.SCE_GATE |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__sdlclkp.GCLK), line:37:5, endln:37:9 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdlclkp (work@sky130_fd_sc_hd__sdlclkp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdlclkp.functional.v, line:36:1, endln:62:10 + \_module_inst: work@sky130_fd_sc_hd__sdlclkp (work@sky130_fd_sc_hd__sdlclkp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdlclkp.functional.v, line:36:1, endln:62:10 |vpiName:GCLK |vpiFullName:work@sky130_fd_sc_hd__sdlclkp.GCLK |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__sdlclkp.SCE), line:38:5, endln:38:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdlclkp (work@sky130_fd_sc_hd__sdlclkp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdlclkp.functional.v, line:36:1, endln:62:10 + \_module_inst: work@sky130_fd_sc_hd__sdlclkp (work@sky130_fd_sc_hd__sdlclkp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdlclkp.functional.v, line:36:1, endln:62:10 |vpiName:SCE |vpiFullName:work@sky130_fd_sc_hd__sdlclkp.SCE |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__sdlclkp.GATE), line:39:5, endln:39:9 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdlclkp (work@sky130_fd_sc_hd__sdlclkp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdlclkp.functional.v, line:36:1, endln:62:10 + \_module_inst: work@sky130_fd_sc_hd__sdlclkp (work@sky130_fd_sc_hd__sdlclkp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdlclkp.functional.v, line:36:1, endln:62:10 |vpiName:GATE |vpiFullName:work@sky130_fd_sc_hd__sdlclkp.GATE |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__sdlclkp.CLK), line:40:5, endln:40:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdlclkp (work@sky130_fd_sc_hd__sdlclkp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdlclkp.functional.v, line:36:1, endln:62:10 + \_module_inst: work@sky130_fd_sc_hd__sdlclkp (work@sky130_fd_sc_hd__sdlclkp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdlclkp.functional.v, line:36:1, endln:62:10 |vpiName:CLK |vpiFullName:work@sky130_fd_sc_hd__sdlclkp.CLK |vpiPort: \_port: (GCLK), line:37:5, endln:37:9 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdlclkp (work@sky130_fd_sc_hd__sdlclkp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdlclkp.functional.v, line:36:1, endln:62:10 + \_module_inst: work@sky130_fd_sc_hd__sdlclkp (work@sky130_fd_sc_hd__sdlclkp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdlclkp.functional.v, line:36:1, endln:62:10 |vpiName:GCLK |vpiDirection:2 |vpiLowConn: @@ -38665,7 +38665,7 @@ design: (work@sky130_fd_sc_hd__sdlclkp) |vpiPort: \_port: (SCE), line:38:5, endln:38:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdlclkp (work@sky130_fd_sc_hd__sdlclkp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdlclkp.functional.v, line:36:1, endln:62:10 + \_module_inst: work@sky130_fd_sc_hd__sdlclkp (work@sky130_fd_sc_hd__sdlclkp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdlclkp.functional.v, line:36:1, endln:62:10 |vpiName:SCE |vpiDirection:1 |vpiLowConn: @@ -38677,7 +38677,7 @@ design: (work@sky130_fd_sc_hd__sdlclkp) |vpiPort: \_port: (GATE), line:39:5, endln:39:9 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdlclkp (work@sky130_fd_sc_hd__sdlclkp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdlclkp.functional.v, line:36:1, endln:62:10 + \_module_inst: work@sky130_fd_sc_hd__sdlclkp (work@sky130_fd_sc_hd__sdlclkp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdlclkp.functional.v, line:36:1, endln:62:10 |vpiName:GATE |vpiDirection:1 |vpiLowConn: @@ -38689,7 +38689,7 @@ design: (work@sky130_fd_sc_hd__sdlclkp) |vpiPort: \_port: (CLK), line:40:5, endln:40:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdlclkp (work@sky130_fd_sc_hd__sdlclkp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdlclkp.functional.v, line:36:1, endln:62:10 + \_module_inst: work@sky130_fd_sc_hd__sdlclkp (work@sky130_fd_sc_hd__sdlclkp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdlclkp.functional.v, line:36:1, endln:62:10 |vpiName:CLK |vpiDirection:1 |vpiLowConn: @@ -38699,14 +38699,14 @@ design: (work@sky130_fd_sc_hd__sdlclkp) |vpiTypedef: \_logic_typespec: , line:47:12, endln:47:12 |uhdmtopModules: -\_module: work@sky130_fd_sc_hd__sdlclkp (work@sky130_fd_sc_hd__sdlclkp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdlclkp.functional.v, line:36:1, endln:62:10 +\_module_inst: work@sky130_fd_sc_hd__sdlclkp (work@sky130_fd_sc_hd__sdlclkp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdlclkp.functional.v, line:36:1, endln:62:10 |vpiName:work@sky130_fd_sc_hd__sdlclkp |vpiDefName:work@sky130_fd_sc_hd__sdlclkp |vpiTop:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__sdlclkp.m0), line:50:10, endln:50:12 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdlclkp (work@sky130_fd_sc_hd__sdlclkp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdlclkp.functional.v, line:36:1, endln:62:10 + \_module_inst: work@sky130_fd_sc_hd__sdlclkp (work@sky130_fd_sc_hd__sdlclkp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdlclkp.functional.v, line:36:1, endln:62:10 |vpiTypespec: \_logic_typespec: , line:50:5, endln:50:9 |vpiName:m0 @@ -38715,7 +38715,7 @@ design: (work@sky130_fd_sc_hd__sdlclkp) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__sdlclkp.m0n), line:51:10, endln:51:13 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdlclkp (work@sky130_fd_sc_hd__sdlclkp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdlclkp.functional.v, line:36:1, endln:62:10 + \_module_inst: work@sky130_fd_sc_hd__sdlclkp (work@sky130_fd_sc_hd__sdlclkp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdlclkp.functional.v, line:36:1, endln:62:10 |vpiTypespec: \_logic_typespec: , line:51:5, endln:51:9 |vpiName:m0n @@ -38724,7 +38724,7 @@ design: (work@sky130_fd_sc_hd__sdlclkp) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__sdlclkp.clkn), line:52:10, endln:52:14 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdlclkp (work@sky130_fd_sc_hd__sdlclkp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdlclkp.functional.v, line:36:1, endln:62:10 + \_module_inst: work@sky130_fd_sc_hd__sdlclkp (work@sky130_fd_sc_hd__sdlclkp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdlclkp.functional.v, line:36:1, endln:62:10 |vpiTypespec: \_logic_typespec: , line:52:5, endln:52:9 |vpiName:clkn @@ -38733,7 +38733,7 @@ design: (work@sky130_fd_sc_hd__sdlclkp) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__sdlclkp.SCE_GATE), line:53:10, endln:53:18 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdlclkp (work@sky130_fd_sc_hd__sdlclkp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdlclkp.functional.v, line:36:1, endln:62:10 + \_module_inst: work@sky130_fd_sc_hd__sdlclkp (work@sky130_fd_sc_hd__sdlclkp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdlclkp.functional.v, line:36:1, endln:62:10 |vpiTypespec: \_logic_typespec: , line:53:5, endln:53:9 |vpiName:SCE_GATE @@ -38742,7 +38742,7 @@ design: (work@sky130_fd_sc_hd__sdlclkp) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__sdlclkp.GCLK), line:37:5, endln:37:9 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdlclkp (work@sky130_fd_sc_hd__sdlclkp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdlclkp.functional.v, line:36:1, endln:62:10 + \_module_inst: work@sky130_fd_sc_hd__sdlclkp (work@sky130_fd_sc_hd__sdlclkp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdlclkp.functional.v, line:36:1, endln:62:10 |vpiTypespec: \_logic_typespec: , line:44:12, endln:44:12 |vpiName:GCLK @@ -38750,7 +38750,7 @@ design: (work@sky130_fd_sc_hd__sdlclkp) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__sdlclkp.SCE), line:38:5, endln:38:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdlclkp (work@sky130_fd_sc_hd__sdlclkp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdlclkp.functional.v, line:36:1, endln:62:10 + \_module_inst: work@sky130_fd_sc_hd__sdlclkp (work@sky130_fd_sc_hd__sdlclkp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdlclkp.functional.v, line:36:1, endln:62:10 |vpiTypespec: \_logic_typespec: , line:45:12, endln:45:12 |vpiName:SCE @@ -38758,7 +38758,7 @@ design: (work@sky130_fd_sc_hd__sdlclkp) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__sdlclkp.GATE), line:39:5, endln:39:9 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdlclkp (work@sky130_fd_sc_hd__sdlclkp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdlclkp.functional.v, line:36:1, endln:62:10 + \_module_inst: work@sky130_fd_sc_hd__sdlclkp (work@sky130_fd_sc_hd__sdlclkp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdlclkp.functional.v, line:36:1, endln:62:10 |vpiTypespec: \_logic_typespec: , line:46:12, endln:46:12 |vpiName:GATE @@ -38766,7 +38766,7 @@ design: (work@sky130_fd_sc_hd__sdlclkp) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__sdlclkp.CLK), line:40:5, endln:40:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdlclkp (work@sky130_fd_sc_hd__sdlclkp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdlclkp.functional.v, line:36:1, endln:62:10 + \_module_inst: work@sky130_fd_sc_hd__sdlclkp (work@sky130_fd_sc_hd__sdlclkp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdlclkp.functional.v, line:36:1, endln:62:10 |vpiTypespec: \_logic_typespec: , line:47:12, endln:47:12 |vpiName:CLK @@ -38775,7 +38775,7 @@ design: (work@sky130_fd_sc_hd__sdlclkp) |vpiPort: \_port: (GCLK), line:37:5, endln:37:9 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdlclkp (work@sky130_fd_sc_hd__sdlclkp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdlclkp.functional.v, line:36:1, endln:62:10 + \_module_inst: work@sky130_fd_sc_hd__sdlclkp (work@sky130_fd_sc_hd__sdlclkp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdlclkp.functional.v, line:36:1, endln:62:10 |vpiName:GCLK |vpiDirection:2 |vpiLowConn: @@ -38789,7 +38789,7 @@ design: (work@sky130_fd_sc_hd__sdlclkp) |vpiPort: \_port: (SCE), line:38:5, endln:38:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdlclkp (work@sky130_fd_sc_hd__sdlclkp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdlclkp.functional.v, line:36:1, endln:62:10 + \_module_inst: work@sky130_fd_sc_hd__sdlclkp (work@sky130_fd_sc_hd__sdlclkp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdlclkp.functional.v, line:36:1, endln:62:10 |vpiName:SCE |vpiDirection:1 |vpiLowConn: @@ -38803,7 +38803,7 @@ design: (work@sky130_fd_sc_hd__sdlclkp) |vpiPort: \_port: (GATE), line:39:5, endln:39:9 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdlclkp (work@sky130_fd_sc_hd__sdlclkp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdlclkp.functional.v, line:36:1, endln:62:10 + \_module_inst: work@sky130_fd_sc_hd__sdlclkp (work@sky130_fd_sc_hd__sdlclkp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdlclkp.functional.v, line:36:1, endln:62:10 |vpiName:GATE |vpiDirection:1 |vpiLowConn: @@ -38817,7 +38817,7 @@ design: (work@sky130_fd_sc_hd__sdlclkp) |vpiPort: \_port: (CLK), line:40:5, endln:40:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdlclkp (work@sky130_fd_sc_hd__sdlclkp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdlclkp.functional.v, line:36:1, endln:62:10 + \_module_inst: work@sky130_fd_sc_hd__sdlclkp (work@sky130_fd_sc_hd__sdlclkp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdlclkp.functional.v, line:36:1, endln:62:10 |vpiName:CLK |vpiDirection:1 |vpiLowConn: @@ -38831,7 +38831,7 @@ design: (work@sky130_fd_sc_hd__sdlclkp) |vpiPrimitive: \_gate: work@not (work@sky130_fd_sc_hd__sdlclkp.not0), line:56:35, endln:56:70 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdlclkp (work@sky130_fd_sc_hd__sdlclkp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdlclkp.functional.v, line:36:1, endln:62:10 + \_module_inst: work@sky130_fd_sc_hd__sdlclkp (work@sky130_fd_sc_hd__sdlclkp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdlclkp.functional.v, line:36:1, endln:62:10 |vpiDefName:work@not |vpiName:not0 |vpiFullName:work@sky130_fd_sc_hd__sdlclkp.not0 @@ -38866,7 +38866,7 @@ design: (work@sky130_fd_sc_hd__sdlclkp) |vpiPrimitive: \_gate: work@not (work@sky130_fd_sc_hd__sdlclkp.not1), line:57:35, endln:57:70 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdlclkp (work@sky130_fd_sc_hd__sdlclkp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdlclkp.functional.v, line:36:1, endln:62:10 + \_module_inst: work@sky130_fd_sc_hd__sdlclkp (work@sky130_fd_sc_hd__sdlclkp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdlclkp.functional.v, line:36:1, endln:62:10 |vpiDefName:work@not |vpiName:not1 |vpiFullName:work@sky130_fd_sc_hd__sdlclkp.not1 @@ -38901,7 +38901,7 @@ design: (work@sky130_fd_sc_hd__sdlclkp) |vpiPrimitive: \_gate: work@nor (work@sky130_fd_sc_hd__sdlclkp.nor0), line:58:35, endln:58:70 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdlclkp (work@sky130_fd_sc_hd__sdlclkp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdlclkp.functional.v, line:36:1, endln:62:10 + \_module_inst: work@sky130_fd_sc_hd__sdlclkp (work@sky130_fd_sc_hd__sdlclkp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdlclkp.functional.v, line:36:1, endln:62:10 |vpiDefName:work@nor |vpiName:nor0 |vpiFullName:work@sky130_fd_sc_hd__sdlclkp.nor0 @@ -38950,7 +38950,7 @@ design: (work@sky130_fd_sc_hd__sdlclkp) |vpiPrimitive: \_udp: work@sky130_fd_sc_hd__udp_dlatch$P (work@sky130_fd_sc_hd__sdlclkp.dlatch0), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdlclkp.functional.v, line:59:5, endln:59:71 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdlclkp (work@sky130_fd_sc_hd__sdlclkp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdlclkp.functional.v, line:36:1, endln:62:10 + \_module_inst: work@sky130_fd_sc_hd__sdlclkp (work@sky130_fd_sc_hd__sdlclkp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdlclkp.functional.v, line:36:1, endln:62:10 |vpiDefName:work@sky130_fd_sc_hd__udp_dlatch$P |vpiName:dlatch0 |vpiFullName:work@sky130_fd_sc_hd__sdlclkp.dlatch0 @@ -38959,7 +38959,7 @@ design: (work@sky130_fd_sc_hd__sdlclkp) |vpiPrimitive: \_gate: work@and (work@sky130_fd_sc_hd__sdlclkp.and0), line:60:35, endln:60:70 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdlclkp (work@sky130_fd_sc_hd__sdlclkp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdlclkp.functional.v, line:36:1, endln:62:10 + \_module_inst: work@sky130_fd_sc_hd__sdlclkp (work@sky130_fd_sc_hd__sdlclkp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdlclkp.functional.v, line:36:1, endln:62:10 |vpiDefName:work@and |vpiName:and0 |vpiFullName:work@sky130_fd_sc_hd__sdlclkp.and0 @@ -39016,7 +39016,7 @@ Processing: -cd cells/cells -DUNIT_DELAY -writepp -parse -nocache -nobuiltin -no design: (work@sky130_fd_sc_hd__o311ai) |vpiName:work@sky130_fd_sc_hd__o311ai |uhdmallModules: -\_module: work@sky130_fd_sc_hd__o311ai (work@sky130_fd_sc_hd__o311ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o311ai.functional.v, line:35:1, endln:61:10 +\_module_inst: work@sky130_fd_sc_hd__o311ai (work@sky130_fd_sc_hd__o311ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o311ai.functional.v, line:35:1, endln:61:10 |vpiParent: \_design: (work@sky130_fd_sc_hd__o311ai) |vpiFullName:work@sky130_fd_sc_hd__o311ai @@ -39024,57 +39024,57 @@ design: (work@sky130_fd_sc_hd__o311ai) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o311ai.or0_out), line:53:10, endln:53:17 |vpiParent: - \_module: work@sky130_fd_sc_hd__o311ai (work@sky130_fd_sc_hd__o311ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o311ai.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o311ai (work@sky130_fd_sc_hd__o311ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o311ai.functional.v, line:35:1, endln:61:10 |vpiName:or0_out |vpiFullName:work@sky130_fd_sc_hd__o311ai.or0_out |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o311ai.nand0_out_Y), line:54:10, endln:54:21 |vpiParent: - \_module: work@sky130_fd_sc_hd__o311ai (work@sky130_fd_sc_hd__o311ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o311ai.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o311ai (work@sky130_fd_sc_hd__o311ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o311ai.functional.v, line:35:1, endln:61:10 |vpiName:nand0_out_Y |vpiFullName:work@sky130_fd_sc_hd__o311ai.nand0_out_Y |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o311ai.Y), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__o311ai (work@sky130_fd_sc_hd__o311ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o311ai.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o311ai (work@sky130_fd_sc_hd__o311ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o311ai.functional.v, line:35:1, endln:61:10 |vpiName:Y |vpiFullName:work@sky130_fd_sc_hd__o311ai.Y |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o311ai.A1), line:37:5, endln:37:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o311ai (work@sky130_fd_sc_hd__o311ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o311ai.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o311ai (work@sky130_fd_sc_hd__o311ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o311ai.functional.v, line:35:1, endln:61:10 |vpiName:A1 |vpiFullName:work@sky130_fd_sc_hd__o311ai.A1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o311ai.A2), line:38:5, endln:38:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o311ai (work@sky130_fd_sc_hd__o311ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o311ai.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o311ai (work@sky130_fd_sc_hd__o311ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o311ai.functional.v, line:35:1, endln:61:10 |vpiName:A2 |vpiFullName:work@sky130_fd_sc_hd__o311ai.A2 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o311ai.A3), line:39:5, endln:39:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o311ai (work@sky130_fd_sc_hd__o311ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o311ai.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o311ai (work@sky130_fd_sc_hd__o311ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o311ai.functional.v, line:35:1, endln:61:10 |vpiName:A3 |vpiFullName:work@sky130_fd_sc_hd__o311ai.A3 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o311ai.B1), line:40:5, endln:40:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o311ai (work@sky130_fd_sc_hd__o311ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o311ai.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o311ai (work@sky130_fd_sc_hd__o311ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o311ai.functional.v, line:35:1, endln:61:10 |vpiName:B1 |vpiFullName:work@sky130_fd_sc_hd__o311ai.B1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o311ai.C1), line:41:5, endln:41:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o311ai (work@sky130_fd_sc_hd__o311ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o311ai.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o311ai (work@sky130_fd_sc_hd__o311ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o311ai.functional.v, line:35:1, endln:61:10 |vpiName:C1 |vpiFullName:work@sky130_fd_sc_hd__o311ai.C1 |vpiPort: \_port: (Y), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__o311ai (work@sky130_fd_sc_hd__o311ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o311ai.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o311ai (work@sky130_fd_sc_hd__o311ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o311ai.functional.v, line:35:1, endln:61:10 |vpiName:Y |vpiDirection:2 |vpiLowConn: @@ -39086,7 +39086,7 @@ design: (work@sky130_fd_sc_hd__o311ai) |vpiPort: \_port: (A1), line:37:5, endln:37:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o311ai (work@sky130_fd_sc_hd__o311ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o311ai.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o311ai (work@sky130_fd_sc_hd__o311ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o311ai.functional.v, line:35:1, endln:61:10 |vpiName:A1 |vpiDirection:1 |vpiLowConn: @@ -39098,7 +39098,7 @@ design: (work@sky130_fd_sc_hd__o311ai) |vpiPort: \_port: (A2), line:38:5, endln:38:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o311ai (work@sky130_fd_sc_hd__o311ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o311ai.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o311ai (work@sky130_fd_sc_hd__o311ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o311ai.functional.v, line:35:1, endln:61:10 |vpiName:A2 |vpiDirection:1 |vpiLowConn: @@ -39110,7 +39110,7 @@ design: (work@sky130_fd_sc_hd__o311ai) |vpiPort: \_port: (A3), line:39:5, endln:39:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o311ai (work@sky130_fd_sc_hd__o311ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o311ai.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o311ai (work@sky130_fd_sc_hd__o311ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o311ai.functional.v, line:35:1, endln:61:10 |vpiName:A3 |vpiDirection:1 |vpiLowConn: @@ -39122,7 +39122,7 @@ design: (work@sky130_fd_sc_hd__o311ai) |vpiPort: \_port: (B1), line:40:5, endln:40:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o311ai (work@sky130_fd_sc_hd__o311ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o311ai.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o311ai (work@sky130_fd_sc_hd__o311ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o311ai.functional.v, line:35:1, endln:61:10 |vpiName:B1 |vpiDirection:1 |vpiLowConn: @@ -39134,7 +39134,7 @@ design: (work@sky130_fd_sc_hd__o311ai) |vpiPort: \_port: (C1), line:41:5, endln:41:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o311ai (work@sky130_fd_sc_hd__o311ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o311ai.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o311ai (work@sky130_fd_sc_hd__o311ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o311ai.functional.v, line:35:1, endln:61:10 |vpiName:C1 |vpiDirection:1 |vpiLowConn: @@ -39144,14 +39144,14 @@ design: (work@sky130_fd_sc_hd__o311ai) |vpiTypedef: \_logic_typespec: , line:50:12, endln:50:12 |uhdmtopModules: -\_module: work@sky130_fd_sc_hd__o311ai (work@sky130_fd_sc_hd__o311ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o311ai.functional.v, line:35:1, endln:61:10 +\_module_inst: work@sky130_fd_sc_hd__o311ai (work@sky130_fd_sc_hd__o311ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o311ai.functional.v, line:35:1, endln:61:10 |vpiName:work@sky130_fd_sc_hd__o311ai |vpiDefName:work@sky130_fd_sc_hd__o311ai |vpiTop:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o311ai.or0_out), line:53:10, endln:53:17 |vpiParent: - \_module: work@sky130_fd_sc_hd__o311ai (work@sky130_fd_sc_hd__o311ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o311ai.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o311ai (work@sky130_fd_sc_hd__o311ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o311ai.functional.v, line:35:1, endln:61:10 |vpiTypespec: \_logic_typespec: , line:53:5, endln:53:9 |vpiName:or0_out @@ -39160,7 +39160,7 @@ design: (work@sky130_fd_sc_hd__o311ai) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o311ai.nand0_out_Y), line:54:10, endln:54:21 |vpiParent: - \_module: work@sky130_fd_sc_hd__o311ai (work@sky130_fd_sc_hd__o311ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o311ai.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o311ai (work@sky130_fd_sc_hd__o311ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o311ai.functional.v, line:35:1, endln:61:10 |vpiTypespec: \_logic_typespec: , line:54:5, endln:54:9 |vpiName:nand0_out_Y @@ -39169,7 +39169,7 @@ design: (work@sky130_fd_sc_hd__o311ai) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o311ai.Y), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__o311ai (work@sky130_fd_sc_hd__o311ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o311ai.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o311ai (work@sky130_fd_sc_hd__o311ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o311ai.functional.v, line:35:1, endln:61:10 |vpiTypespec: \_logic_typespec: , line:45:12, endln:45:12 |vpiName:Y @@ -39177,7 +39177,7 @@ design: (work@sky130_fd_sc_hd__o311ai) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o311ai.A1), line:37:5, endln:37:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o311ai (work@sky130_fd_sc_hd__o311ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o311ai.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o311ai (work@sky130_fd_sc_hd__o311ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o311ai.functional.v, line:35:1, endln:61:10 |vpiTypespec: \_logic_typespec: , line:46:12, endln:46:12 |vpiName:A1 @@ -39185,7 +39185,7 @@ design: (work@sky130_fd_sc_hd__o311ai) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o311ai.A2), line:38:5, endln:38:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o311ai (work@sky130_fd_sc_hd__o311ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o311ai.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o311ai (work@sky130_fd_sc_hd__o311ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o311ai.functional.v, line:35:1, endln:61:10 |vpiTypespec: \_logic_typespec: , line:47:12, endln:47:12 |vpiName:A2 @@ -39193,7 +39193,7 @@ design: (work@sky130_fd_sc_hd__o311ai) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o311ai.A3), line:39:5, endln:39:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o311ai (work@sky130_fd_sc_hd__o311ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o311ai.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o311ai (work@sky130_fd_sc_hd__o311ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o311ai.functional.v, line:35:1, endln:61:10 |vpiTypespec: \_logic_typespec: , line:48:12, endln:48:12 |vpiName:A3 @@ -39201,7 +39201,7 @@ design: (work@sky130_fd_sc_hd__o311ai) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o311ai.B1), line:40:5, endln:40:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o311ai (work@sky130_fd_sc_hd__o311ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o311ai.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o311ai (work@sky130_fd_sc_hd__o311ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o311ai.functional.v, line:35:1, endln:61:10 |vpiTypespec: \_logic_typespec: , line:49:12, endln:49:12 |vpiName:B1 @@ -39209,7 +39209,7 @@ design: (work@sky130_fd_sc_hd__o311ai) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o311ai.C1), line:41:5, endln:41:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o311ai (work@sky130_fd_sc_hd__o311ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o311ai.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o311ai (work@sky130_fd_sc_hd__o311ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o311ai.functional.v, line:35:1, endln:61:10 |vpiTypespec: \_logic_typespec: , line:50:12, endln:50:12 |vpiName:C1 @@ -39218,7 +39218,7 @@ design: (work@sky130_fd_sc_hd__o311ai) |vpiPort: \_port: (Y), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__o311ai (work@sky130_fd_sc_hd__o311ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o311ai.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o311ai (work@sky130_fd_sc_hd__o311ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o311ai.functional.v, line:35:1, endln:61:10 |vpiName:Y |vpiDirection:2 |vpiLowConn: @@ -39232,7 +39232,7 @@ design: (work@sky130_fd_sc_hd__o311ai) |vpiPort: \_port: (A1), line:37:5, endln:37:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o311ai (work@sky130_fd_sc_hd__o311ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o311ai.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o311ai (work@sky130_fd_sc_hd__o311ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o311ai.functional.v, line:35:1, endln:61:10 |vpiName:A1 |vpiDirection:1 |vpiLowConn: @@ -39246,7 +39246,7 @@ design: (work@sky130_fd_sc_hd__o311ai) |vpiPort: \_port: (A2), line:38:5, endln:38:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o311ai (work@sky130_fd_sc_hd__o311ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o311ai.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o311ai (work@sky130_fd_sc_hd__o311ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o311ai.functional.v, line:35:1, endln:61:10 |vpiName:A2 |vpiDirection:1 |vpiLowConn: @@ -39260,7 +39260,7 @@ design: (work@sky130_fd_sc_hd__o311ai) |vpiPort: \_port: (A3), line:39:5, endln:39:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o311ai (work@sky130_fd_sc_hd__o311ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o311ai.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o311ai (work@sky130_fd_sc_hd__o311ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o311ai.functional.v, line:35:1, endln:61:10 |vpiName:A3 |vpiDirection:1 |vpiLowConn: @@ -39274,7 +39274,7 @@ design: (work@sky130_fd_sc_hd__o311ai) |vpiPort: \_port: (B1), line:40:5, endln:40:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o311ai (work@sky130_fd_sc_hd__o311ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o311ai.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o311ai (work@sky130_fd_sc_hd__o311ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o311ai.functional.v, line:35:1, endln:61:10 |vpiName:B1 |vpiDirection:1 |vpiLowConn: @@ -39288,7 +39288,7 @@ design: (work@sky130_fd_sc_hd__o311ai) |vpiPort: \_port: (C1), line:41:5, endln:41:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o311ai (work@sky130_fd_sc_hd__o311ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o311ai.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o311ai (work@sky130_fd_sc_hd__o311ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o311ai.functional.v, line:35:1, endln:61:10 |vpiName:C1 |vpiDirection:1 |vpiLowConn: @@ -39302,7 +39302,7 @@ design: (work@sky130_fd_sc_hd__o311ai) |vpiPrimitive: \_gate: work@or (work@sky130_fd_sc_hd__o311ai.or0), line:57:10, endln:57:46 |vpiParent: - \_module: work@sky130_fd_sc_hd__o311ai (work@sky130_fd_sc_hd__o311ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o311ai.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o311ai (work@sky130_fd_sc_hd__o311ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o311ai.functional.v, line:35:1, endln:61:10 |vpiDefName:work@or |vpiName:or0 |vpiFullName:work@sky130_fd_sc_hd__o311ai.or0 @@ -39365,7 +39365,7 @@ design: (work@sky130_fd_sc_hd__o311ai) |vpiPrimitive: \_gate: work@nand (work@sky130_fd_sc_hd__o311ai.nand0), line:58:10, endln:58:46 |vpiParent: - \_module: work@sky130_fd_sc_hd__o311ai (work@sky130_fd_sc_hd__o311ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o311ai.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o311ai (work@sky130_fd_sc_hd__o311ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o311ai.functional.v, line:35:1, endln:61:10 |vpiDefName:work@nand |vpiName:nand0 |vpiFullName:work@sky130_fd_sc_hd__o311ai.nand0 @@ -39428,7 +39428,7 @@ design: (work@sky130_fd_sc_hd__o311ai) |vpiPrimitive: \_gate: work@buf (work@sky130_fd_sc_hd__o311ai.buf0), line:59:10, endln:59:46 |vpiParent: - \_module: work@sky130_fd_sc_hd__o311ai (work@sky130_fd_sc_hd__o311ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o311ai.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o311ai (work@sky130_fd_sc_hd__o311ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o311ai.functional.v, line:35:1, endln:61:10 |vpiDefName:work@buf |vpiName:buf0 |vpiFullName:work@sky130_fd_sc_hd__o311ai.buf0 @@ -39471,7 +39471,7 @@ Processing: -cd cells/cells -DUNIT_DELAY -writepp -parse -nocache -nobuiltin -no design: (work@sky130_fd_sc_hd__fah) |vpiName:work@sky130_fd_sc_hd__fah |uhdmallModules: -\_module: work@sky130_fd_sc_hd__fah (work@sky130_fd_sc_hd__fah), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fah.functional.v, line:33:1, endln:64:10 +\_module_inst: work@sky130_fd_sc_hd__fah (work@sky130_fd_sc_hd__fah), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fah.functional.v, line:33:1, endln:64:10 |vpiParent: \_design: (work@sky130_fd_sc_hd__fah) |vpiFullName:work@sky130_fd_sc_hd__fah @@ -39479,72 +39479,72 @@ design: (work@sky130_fd_sc_hd__fah) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__fah.xor0_out_SUM), line:49:10, endln:49:22 |vpiParent: - \_module: work@sky130_fd_sc_hd__fah (work@sky130_fd_sc_hd__fah), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fah.functional.v, line:33:1, endln:64:10 + \_module_inst: work@sky130_fd_sc_hd__fah (work@sky130_fd_sc_hd__fah), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fah.functional.v, line:33:1, endln:64:10 |vpiName:xor0_out_SUM |vpiFullName:work@sky130_fd_sc_hd__fah.xor0_out_SUM |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__fah.a_b), line:50:10, endln:50:13 |vpiParent: - \_module: work@sky130_fd_sc_hd__fah (work@sky130_fd_sc_hd__fah), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fah.functional.v, line:33:1, endln:64:10 + \_module_inst: work@sky130_fd_sc_hd__fah (work@sky130_fd_sc_hd__fah), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fah.functional.v, line:33:1, endln:64:10 |vpiName:a_b |vpiFullName:work@sky130_fd_sc_hd__fah.a_b |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__fah.a_ci), line:51:10, endln:51:14 |vpiParent: - \_module: work@sky130_fd_sc_hd__fah (work@sky130_fd_sc_hd__fah), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fah.functional.v, line:33:1, endln:64:10 + \_module_inst: work@sky130_fd_sc_hd__fah (work@sky130_fd_sc_hd__fah), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fah.functional.v, line:33:1, endln:64:10 |vpiName:a_ci |vpiFullName:work@sky130_fd_sc_hd__fah.a_ci |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__fah.b_ci), line:52:10, endln:52:14 |vpiParent: - \_module: work@sky130_fd_sc_hd__fah (work@sky130_fd_sc_hd__fah), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fah.functional.v, line:33:1, endln:64:10 + \_module_inst: work@sky130_fd_sc_hd__fah (work@sky130_fd_sc_hd__fah), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fah.functional.v, line:33:1, endln:64:10 |vpiName:b_ci |vpiFullName:work@sky130_fd_sc_hd__fah.b_ci |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__fah.or0_out_COUT), line:53:10, endln:53:22 |vpiParent: - \_module: work@sky130_fd_sc_hd__fah (work@sky130_fd_sc_hd__fah), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fah.functional.v, line:33:1, endln:64:10 + \_module_inst: work@sky130_fd_sc_hd__fah (work@sky130_fd_sc_hd__fah), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fah.functional.v, line:33:1, endln:64:10 |vpiName:or0_out_COUT |vpiFullName:work@sky130_fd_sc_hd__fah.or0_out_COUT |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__fah.COUT), line:34:5, endln:34:9 |vpiParent: - \_module: work@sky130_fd_sc_hd__fah (work@sky130_fd_sc_hd__fah), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fah.functional.v, line:33:1, endln:64:10 + \_module_inst: work@sky130_fd_sc_hd__fah (work@sky130_fd_sc_hd__fah), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fah.functional.v, line:33:1, endln:64:10 |vpiName:COUT |vpiFullName:work@sky130_fd_sc_hd__fah.COUT |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__fah.SUM), line:35:5, endln:35:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__fah (work@sky130_fd_sc_hd__fah), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fah.functional.v, line:33:1, endln:64:10 + \_module_inst: work@sky130_fd_sc_hd__fah (work@sky130_fd_sc_hd__fah), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fah.functional.v, line:33:1, endln:64:10 |vpiName:SUM |vpiFullName:work@sky130_fd_sc_hd__fah.SUM |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__fah.A), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__fah (work@sky130_fd_sc_hd__fah), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fah.functional.v, line:33:1, endln:64:10 + \_module_inst: work@sky130_fd_sc_hd__fah (work@sky130_fd_sc_hd__fah), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fah.functional.v, line:33:1, endln:64:10 |vpiName:A |vpiFullName:work@sky130_fd_sc_hd__fah.A |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__fah.B), line:37:5, endln:37:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__fah (work@sky130_fd_sc_hd__fah), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fah.functional.v, line:33:1, endln:64:10 + \_module_inst: work@sky130_fd_sc_hd__fah (work@sky130_fd_sc_hd__fah), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fah.functional.v, line:33:1, endln:64:10 |vpiName:B |vpiFullName:work@sky130_fd_sc_hd__fah.B |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__fah.CI), line:38:5, endln:38:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__fah (work@sky130_fd_sc_hd__fah), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fah.functional.v, line:33:1, endln:64:10 + \_module_inst: work@sky130_fd_sc_hd__fah (work@sky130_fd_sc_hd__fah), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fah.functional.v, line:33:1, endln:64:10 |vpiName:CI |vpiFullName:work@sky130_fd_sc_hd__fah.CI |vpiPort: \_port: (COUT), line:34:5, endln:34:9 |vpiParent: - \_module: work@sky130_fd_sc_hd__fah (work@sky130_fd_sc_hd__fah), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fah.functional.v, line:33:1, endln:64:10 + \_module_inst: work@sky130_fd_sc_hd__fah (work@sky130_fd_sc_hd__fah), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fah.functional.v, line:33:1, endln:64:10 |vpiName:COUT |vpiDirection:2 |vpiLowConn: @@ -39556,7 +39556,7 @@ design: (work@sky130_fd_sc_hd__fah) |vpiPort: \_port: (SUM), line:35:5, endln:35:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__fah (work@sky130_fd_sc_hd__fah), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fah.functional.v, line:33:1, endln:64:10 + \_module_inst: work@sky130_fd_sc_hd__fah (work@sky130_fd_sc_hd__fah), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fah.functional.v, line:33:1, endln:64:10 |vpiName:SUM |vpiDirection:2 |vpiLowConn: @@ -39568,7 +39568,7 @@ design: (work@sky130_fd_sc_hd__fah) |vpiPort: \_port: (A), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__fah (work@sky130_fd_sc_hd__fah), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fah.functional.v, line:33:1, endln:64:10 + \_module_inst: work@sky130_fd_sc_hd__fah (work@sky130_fd_sc_hd__fah), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fah.functional.v, line:33:1, endln:64:10 |vpiName:A |vpiDirection:1 |vpiLowConn: @@ -39580,7 +39580,7 @@ design: (work@sky130_fd_sc_hd__fah) |vpiPort: \_port: (B), line:37:5, endln:37:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__fah (work@sky130_fd_sc_hd__fah), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fah.functional.v, line:33:1, endln:64:10 + \_module_inst: work@sky130_fd_sc_hd__fah (work@sky130_fd_sc_hd__fah), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fah.functional.v, line:33:1, endln:64:10 |vpiName:B |vpiDirection:1 |vpiLowConn: @@ -39592,7 +39592,7 @@ design: (work@sky130_fd_sc_hd__fah) |vpiPort: \_port: (CI), line:38:5, endln:38:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__fah (work@sky130_fd_sc_hd__fah), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fah.functional.v, line:33:1, endln:64:10 + \_module_inst: work@sky130_fd_sc_hd__fah (work@sky130_fd_sc_hd__fah), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fah.functional.v, line:33:1, endln:64:10 |vpiName:CI |vpiDirection:1 |vpiLowConn: @@ -39602,14 +39602,14 @@ design: (work@sky130_fd_sc_hd__fah) |vpiTypedef: \_logic_typespec: , line:46:12, endln:46:12 |uhdmtopModules: -\_module: work@sky130_fd_sc_hd__fah (work@sky130_fd_sc_hd__fah), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fah.functional.v, line:33:1, endln:64:10 +\_module_inst: work@sky130_fd_sc_hd__fah (work@sky130_fd_sc_hd__fah), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fah.functional.v, line:33:1, endln:64:10 |vpiName:work@sky130_fd_sc_hd__fah |vpiDefName:work@sky130_fd_sc_hd__fah |vpiTop:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__fah.xor0_out_SUM), line:49:10, endln:49:22 |vpiParent: - \_module: work@sky130_fd_sc_hd__fah (work@sky130_fd_sc_hd__fah), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fah.functional.v, line:33:1, endln:64:10 + \_module_inst: work@sky130_fd_sc_hd__fah (work@sky130_fd_sc_hd__fah), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fah.functional.v, line:33:1, endln:64:10 |vpiTypespec: \_logic_typespec: , line:49:5, endln:49:9 |vpiName:xor0_out_SUM @@ -39618,7 +39618,7 @@ design: (work@sky130_fd_sc_hd__fah) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__fah.a_b), line:50:10, endln:50:13 |vpiParent: - \_module: work@sky130_fd_sc_hd__fah (work@sky130_fd_sc_hd__fah), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fah.functional.v, line:33:1, endln:64:10 + \_module_inst: work@sky130_fd_sc_hd__fah (work@sky130_fd_sc_hd__fah), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fah.functional.v, line:33:1, endln:64:10 |vpiTypespec: \_logic_typespec: , line:50:5, endln:50:9 |vpiName:a_b @@ -39627,7 +39627,7 @@ design: (work@sky130_fd_sc_hd__fah) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__fah.a_ci), line:51:10, endln:51:14 |vpiParent: - \_module: work@sky130_fd_sc_hd__fah (work@sky130_fd_sc_hd__fah), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fah.functional.v, line:33:1, endln:64:10 + \_module_inst: work@sky130_fd_sc_hd__fah (work@sky130_fd_sc_hd__fah), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fah.functional.v, line:33:1, endln:64:10 |vpiTypespec: \_logic_typespec: , line:51:5, endln:51:9 |vpiName:a_ci @@ -39636,7 +39636,7 @@ design: (work@sky130_fd_sc_hd__fah) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__fah.b_ci), line:52:10, endln:52:14 |vpiParent: - \_module: work@sky130_fd_sc_hd__fah (work@sky130_fd_sc_hd__fah), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fah.functional.v, line:33:1, endln:64:10 + \_module_inst: work@sky130_fd_sc_hd__fah (work@sky130_fd_sc_hd__fah), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fah.functional.v, line:33:1, endln:64:10 |vpiTypespec: \_logic_typespec: , line:52:5, endln:52:9 |vpiName:b_ci @@ -39645,7 +39645,7 @@ design: (work@sky130_fd_sc_hd__fah) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__fah.or0_out_COUT), line:53:10, endln:53:22 |vpiParent: - \_module: work@sky130_fd_sc_hd__fah (work@sky130_fd_sc_hd__fah), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fah.functional.v, line:33:1, endln:64:10 + \_module_inst: work@sky130_fd_sc_hd__fah (work@sky130_fd_sc_hd__fah), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fah.functional.v, line:33:1, endln:64:10 |vpiTypespec: \_logic_typespec: , line:53:5, endln:53:9 |vpiName:or0_out_COUT @@ -39654,7 +39654,7 @@ design: (work@sky130_fd_sc_hd__fah) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__fah.COUT), line:34:5, endln:34:9 |vpiParent: - \_module: work@sky130_fd_sc_hd__fah (work@sky130_fd_sc_hd__fah), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fah.functional.v, line:33:1, endln:64:10 + \_module_inst: work@sky130_fd_sc_hd__fah (work@sky130_fd_sc_hd__fah), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fah.functional.v, line:33:1, endln:64:10 |vpiTypespec: \_logic_typespec: , line:42:12, endln:42:12 |vpiName:COUT @@ -39662,7 +39662,7 @@ design: (work@sky130_fd_sc_hd__fah) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__fah.SUM), line:35:5, endln:35:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__fah (work@sky130_fd_sc_hd__fah), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fah.functional.v, line:33:1, endln:64:10 + \_module_inst: work@sky130_fd_sc_hd__fah (work@sky130_fd_sc_hd__fah), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fah.functional.v, line:33:1, endln:64:10 |vpiTypespec: \_logic_typespec: , line:43:12, endln:43:12 |vpiName:SUM @@ -39670,7 +39670,7 @@ design: (work@sky130_fd_sc_hd__fah) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__fah.A), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__fah (work@sky130_fd_sc_hd__fah), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fah.functional.v, line:33:1, endln:64:10 + \_module_inst: work@sky130_fd_sc_hd__fah (work@sky130_fd_sc_hd__fah), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fah.functional.v, line:33:1, endln:64:10 |vpiTypespec: \_logic_typespec: , line:44:12, endln:44:12 |vpiName:A @@ -39678,7 +39678,7 @@ design: (work@sky130_fd_sc_hd__fah) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__fah.B), line:37:5, endln:37:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__fah (work@sky130_fd_sc_hd__fah), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fah.functional.v, line:33:1, endln:64:10 + \_module_inst: work@sky130_fd_sc_hd__fah (work@sky130_fd_sc_hd__fah), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fah.functional.v, line:33:1, endln:64:10 |vpiTypespec: \_logic_typespec: , line:45:12, endln:45:12 |vpiName:B @@ -39686,7 +39686,7 @@ design: (work@sky130_fd_sc_hd__fah) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__fah.CI), line:38:5, endln:38:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__fah (work@sky130_fd_sc_hd__fah), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fah.functional.v, line:33:1, endln:64:10 + \_module_inst: work@sky130_fd_sc_hd__fah (work@sky130_fd_sc_hd__fah), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fah.functional.v, line:33:1, endln:64:10 |vpiTypespec: \_logic_typespec: , line:46:12, endln:46:12 |vpiName:CI @@ -39695,7 +39695,7 @@ design: (work@sky130_fd_sc_hd__fah) |vpiPort: \_port: (COUT), line:34:5, endln:34:9 |vpiParent: - \_module: work@sky130_fd_sc_hd__fah (work@sky130_fd_sc_hd__fah), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fah.functional.v, line:33:1, endln:64:10 + \_module_inst: work@sky130_fd_sc_hd__fah (work@sky130_fd_sc_hd__fah), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fah.functional.v, line:33:1, endln:64:10 |vpiName:COUT |vpiDirection:2 |vpiLowConn: @@ -39709,7 +39709,7 @@ design: (work@sky130_fd_sc_hd__fah) |vpiPort: \_port: (SUM), line:35:5, endln:35:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__fah (work@sky130_fd_sc_hd__fah), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fah.functional.v, line:33:1, endln:64:10 + \_module_inst: work@sky130_fd_sc_hd__fah (work@sky130_fd_sc_hd__fah), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fah.functional.v, line:33:1, endln:64:10 |vpiName:SUM |vpiDirection:2 |vpiLowConn: @@ -39723,7 +39723,7 @@ design: (work@sky130_fd_sc_hd__fah) |vpiPort: \_port: (A), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__fah (work@sky130_fd_sc_hd__fah), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fah.functional.v, line:33:1, endln:64:10 + \_module_inst: work@sky130_fd_sc_hd__fah (work@sky130_fd_sc_hd__fah), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fah.functional.v, line:33:1, endln:64:10 |vpiName:A |vpiDirection:1 |vpiLowConn: @@ -39737,7 +39737,7 @@ design: (work@sky130_fd_sc_hd__fah) |vpiPort: \_port: (B), line:37:5, endln:37:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__fah (work@sky130_fd_sc_hd__fah), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fah.functional.v, line:33:1, endln:64:10 + \_module_inst: work@sky130_fd_sc_hd__fah (work@sky130_fd_sc_hd__fah), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fah.functional.v, line:33:1, endln:64:10 |vpiName:B |vpiDirection:1 |vpiLowConn: @@ -39751,7 +39751,7 @@ design: (work@sky130_fd_sc_hd__fah) |vpiPort: \_port: (CI), line:38:5, endln:38:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__fah (work@sky130_fd_sc_hd__fah), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fah.functional.v, line:33:1, endln:64:10 + \_module_inst: work@sky130_fd_sc_hd__fah (work@sky130_fd_sc_hd__fah), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fah.functional.v, line:33:1, endln:64:10 |vpiName:CI |vpiDirection:1 |vpiLowConn: @@ -39765,7 +39765,7 @@ design: (work@sky130_fd_sc_hd__fah) |vpiPrimitive: \_gate: work@xor (work@sky130_fd_sc_hd__fah.xor0), line:56:9, endln:56:45 |vpiParent: - \_module: work@sky130_fd_sc_hd__fah (work@sky130_fd_sc_hd__fah), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fah.functional.v, line:33:1, endln:64:10 + \_module_inst: work@sky130_fd_sc_hd__fah (work@sky130_fd_sc_hd__fah), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fah.functional.v, line:33:1, endln:64:10 |vpiDefName:work@xor |vpiName:xor0 |vpiFullName:work@sky130_fd_sc_hd__fah.xor0 @@ -39828,7 +39828,7 @@ design: (work@sky130_fd_sc_hd__fah) |vpiPrimitive: \_gate: work@buf (work@sky130_fd_sc_hd__fah.buf0), line:57:9, endln:57:45 |vpiParent: - \_module: work@sky130_fd_sc_hd__fah (work@sky130_fd_sc_hd__fah), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fah.functional.v, line:33:1, endln:64:10 + \_module_inst: work@sky130_fd_sc_hd__fah (work@sky130_fd_sc_hd__fah), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fah.functional.v, line:33:1, endln:64:10 |vpiDefName:work@buf |vpiName:buf0 |vpiFullName:work@sky130_fd_sc_hd__fah.buf0 @@ -39863,7 +39863,7 @@ design: (work@sky130_fd_sc_hd__fah) |vpiPrimitive: \_gate: work@and (work@sky130_fd_sc_hd__fah.and0), line:58:9, endln:58:45 |vpiParent: - \_module: work@sky130_fd_sc_hd__fah (work@sky130_fd_sc_hd__fah), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fah.functional.v, line:33:1, endln:64:10 + \_module_inst: work@sky130_fd_sc_hd__fah (work@sky130_fd_sc_hd__fah), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fah.functional.v, line:33:1, endln:64:10 |vpiDefName:work@and |vpiName:and0 |vpiFullName:work@sky130_fd_sc_hd__fah.and0 @@ -39912,7 +39912,7 @@ design: (work@sky130_fd_sc_hd__fah) |vpiPrimitive: \_gate: work@and (work@sky130_fd_sc_hd__fah.and1), line:59:9, endln:59:45 |vpiParent: - \_module: work@sky130_fd_sc_hd__fah (work@sky130_fd_sc_hd__fah), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fah.functional.v, line:33:1, endln:64:10 + \_module_inst: work@sky130_fd_sc_hd__fah (work@sky130_fd_sc_hd__fah), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fah.functional.v, line:33:1, endln:64:10 |vpiDefName:work@and |vpiName:and1 |vpiFullName:work@sky130_fd_sc_hd__fah.and1 @@ -39961,7 +39961,7 @@ design: (work@sky130_fd_sc_hd__fah) |vpiPrimitive: \_gate: work@and (work@sky130_fd_sc_hd__fah.and2), line:60:9, endln:60:45 |vpiParent: - \_module: work@sky130_fd_sc_hd__fah (work@sky130_fd_sc_hd__fah), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fah.functional.v, line:33:1, endln:64:10 + \_module_inst: work@sky130_fd_sc_hd__fah (work@sky130_fd_sc_hd__fah), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fah.functional.v, line:33:1, endln:64:10 |vpiDefName:work@and |vpiName:and2 |vpiFullName:work@sky130_fd_sc_hd__fah.and2 @@ -40010,7 +40010,7 @@ design: (work@sky130_fd_sc_hd__fah) |vpiPrimitive: \_gate: work@or (work@sky130_fd_sc_hd__fah.or0), line:61:9, endln:61:45 |vpiParent: - \_module: work@sky130_fd_sc_hd__fah (work@sky130_fd_sc_hd__fah), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fah.functional.v, line:33:1, endln:64:10 + \_module_inst: work@sky130_fd_sc_hd__fah (work@sky130_fd_sc_hd__fah), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fah.functional.v, line:33:1, endln:64:10 |vpiDefName:work@or |vpiName:or0 |vpiFullName:work@sky130_fd_sc_hd__fah.or0 @@ -40073,7 +40073,7 @@ design: (work@sky130_fd_sc_hd__fah) |vpiPrimitive: \_gate: work@buf (work@sky130_fd_sc_hd__fah.buf1), line:62:9, endln:62:45 |vpiParent: - \_module: work@sky130_fd_sc_hd__fah (work@sky130_fd_sc_hd__fah), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fah.functional.v, line:33:1, endln:64:10 + \_module_inst: work@sky130_fd_sc_hd__fah (work@sky130_fd_sc_hd__fah), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fah.functional.v, line:33:1, endln:64:10 |vpiDefName:work@buf |vpiName:buf1 |vpiFullName:work@sky130_fd_sc_hd__fah.buf1 @@ -40116,7 +40116,7 @@ Processing: -cd cells/cells -DUNIT_DELAY -writepp -parse -nocache -nobuiltin -no design: (work@sky130_fd_sc_hd__nand4bb) |vpiName:work@sky130_fd_sc_hd__nand4bb |uhdmallModules: -\_module: work@sky130_fd_sc_hd__nand4bb (work@sky130_fd_sc_hd__nand4bb), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand4bb.functional.v, line:33:1, endln:57:10 +\_module_inst: work@sky130_fd_sc_hd__nand4bb (work@sky130_fd_sc_hd__nand4bb), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand4bb.functional.v, line:33:1, endln:57:10 |vpiParent: \_design: (work@sky130_fd_sc_hd__nand4bb) |vpiFullName:work@sky130_fd_sc_hd__nand4bb @@ -40124,51 +40124,51 @@ design: (work@sky130_fd_sc_hd__nand4bb) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__nand4bb.nand0_out), line:49:10, endln:49:19 |vpiParent: - \_module: work@sky130_fd_sc_hd__nand4bb (work@sky130_fd_sc_hd__nand4bb), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand4bb.functional.v, line:33:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__nand4bb (work@sky130_fd_sc_hd__nand4bb), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand4bb.functional.v, line:33:1, endln:57:10 |vpiName:nand0_out |vpiFullName:work@sky130_fd_sc_hd__nand4bb.nand0_out |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__nand4bb.or0_out_Y), line:50:10, endln:50:19 |vpiParent: - \_module: work@sky130_fd_sc_hd__nand4bb (work@sky130_fd_sc_hd__nand4bb), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand4bb.functional.v, line:33:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__nand4bb (work@sky130_fd_sc_hd__nand4bb), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand4bb.functional.v, line:33:1, endln:57:10 |vpiName:or0_out_Y |vpiFullName:work@sky130_fd_sc_hd__nand4bb.or0_out_Y |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__nand4bb.Y), line:34:5, endln:34:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__nand4bb (work@sky130_fd_sc_hd__nand4bb), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand4bb.functional.v, line:33:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__nand4bb (work@sky130_fd_sc_hd__nand4bb), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand4bb.functional.v, line:33:1, endln:57:10 |vpiName:Y |vpiFullName:work@sky130_fd_sc_hd__nand4bb.Y |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__nand4bb.A_N), line:35:5, endln:35:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__nand4bb (work@sky130_fd_sc_hd__nand4bb), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand4bb.functional.v, line:33:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__nand4bb (work@sky130_fd_sc_hd__nand4bb), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand4bb.functional.v, line:33:1, endln:57:10 |vpiName:A_N |vpiFullName:work@sky130_fd_sc_hd__nand4bb.A_N |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__nand4bb.B_N), line:36:5, endln:36:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__nand4bb (work@sky130_fd_sc_hd__nand4bb), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand4bb.functional.v, line:33:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__nand4bb (work@sky130_fd_sc_hd__nand4bb), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand4bb.functional.v, line:33:1, endln:57:10 |vpiName:B_N |vpiFullName:work@sky130_fd_sc_hd__nand4bb.B_N |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__nand4bb.C), line:37:5, endln:37:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__nand4bb (work@sky130_fd_sc_hd__nand4bb), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand4bb.functional.v, line:33:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__nand4bb (work@sky130_fd_sc_hd__nand4bb), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand4bb.functional.v, line:33:1, endln:57:10 |vpiName:C |vpiFullName:work@sky130_fd_sc_hd__nand4bb.C |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__nand4bb.D), line:38:5, endln:38:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__nand4bb (work@sky130_fd_sc_hd__nand4bb), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand4bb.functional.v, line:33:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__nand4bb (work@sky130_fd_sc_hd__nand4bb), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand4bb.functional.v, line:33:1, endln:57:10 |vpiName:D |vpiFullName:work@sky130_fd_sc_hd__nand4bb.D |vpiPort: \_port: (Y), line:34:5, endln:34:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__nand4bb (work@sky130_fd_sc_hd__nand4bb), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand4bb.functional.v, line:33:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__nand4bb (work@sky130_fd_sc_hd__nand4bb), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand4bb.functional.v, line:33:1, endln:57:10 |vpiName:Y |vpiDirection:2 |vpiLowConn: @@ -40180,7 +40180,7 @@ design: (work@sky130_fd_sc_hd__nand4bb) |vpiPort: \_port: (A_N), line:35:5, endln:35:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__nand4bb (work@sky130_fd_sc_hd__nand4bb), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand4bb.functional.v, line:33:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__nand4bb (work@sky130_fd_sc_hd__nand4bb), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand4bb.functional.v, line:33:1, endln:57:10 |vpiName:A_N |vpiDirection:1 |vpiLowConn: @@ -40192,7 +40192,7 @@ design: (work@sky130_fd_sc_hd__nand4bb) |vpiPort: \_port: (B_N), line:36:5, endln:36:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__nand4bb (work@sky130_fd_sc_hd__nand4bb), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand4bb.functional.v, line:33:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__nand4bb (work@sky130_fd_sc_hd__nand4bb), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand4bb.functional.v, line:33:1, endln:57:10 |vpiName:B_N |vpiDirection:1 |vpiLowConn: @@ -40204,7 +40204,7 @@ design: (work@sky130_fd_sc_hd__nand4bb) |vpiPort: \_port: (C), line:37:5, endln:37:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__nand4bb (work@sky130_fd_sc_hd__nand4bb), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand4bb.functional.v, line:33:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__nand4bb (work@sky130_fd_sc_hd__nand4bb), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand4bb.functional.v, line:33:1, endln:57:10 |vpiName:C |vpiDirection:1 |vpiLowConn: @@ -40216,7 +40216,7 @@ design: (work@sky130_fd_sc_hd__nand4bb) |vpiPort: \_port: (D), line:38:5, endln:38:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__nand4bb (work@sky130_fd_sc_hd__nand4bb), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand4bb.functional.v, line:33:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__nand4bb (work@sky130_fd_sc_hd__nand4bb), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand4bb.functional.v, line:33:1, endln:57:10 |vpiName:D |vpiDirection:1 |vpiLowConn: @@ -40226,14 +40226,14 @@ design: (work@sky130_fd_sc_hd__nand4bb) |vpiTypedef: \_logic_typespec: , line:46:12, endln:46:12 |uhdmtopModules: -\_module: work@sky130_fd_sc_hd__nand4bb (work@sky130_fd_sc_hd__nand4bb), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand4bb.functional.v, line:33:1, endln:57:10 +\_module_inst: work@sky130_fd_sc_hd__nand4bb (work@sky130_fd_sc_hd__nand4bb), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand4bb.functional.v, line:33:1, endln:57:10 |vpiName:work@sky130_fd_sc_hd__nand4bb |vpiDefName:work@sky130_fd_sc_hd__nand4bb |vpiTop:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__nand4bb.nand0_out), line:49:10, endln:49:19 |vpiParent: - \_module: work@sky130_fd_sc_hd__nand4bb (work@sky130_fd_sc_hd__nand4bb), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand4bb.functional.v, line:33:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__nand4bb (work@sky130_fd_sc_hd__nand4bb), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand4bb.functional.v, line:33:1, endln:57:10 |vpiTypespec: \_logic_typespec: , line:49:5, endln:49:9 |vpiName:nand0_out @@ -40242,7 +40242,7 @@ design: (work@sky130_fd_sc_hd__nand4bb) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__nand4bb.or0_out_Y), line:50:10, endln:50:19 |vpiParent: - \_module: work@sky130_fd_sc_hd__nand4bb (work@sky130_fd_sc_hd__nand4bb), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand4bb.functional.v, line:33:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__nand4bb (work@sky130_fd_sc_hd__nand4bb), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand4bb.functional.v, line:33:1, endln:57:10 |vpiTypespec: \_logic_typespec: , line:50:5, endln:50:9 |vpiName:or0_out_Y @@ -40251,7 +40251,7 @@ design: (work@sky130_fd_sc_hd__nand4bb) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__nand4bb.Y), line:34:5, endln:34:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__nand4bb (work@sky130_fd_sc_hd__nand4bb), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand4bb.functional.v, line:33:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__nand4bb (work@sky130_fd_sc_hd__nand4bb), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand4bb.functional.v, line:33:1, endln:57:10 |vpiTypespec: \_logic_typespec: , line:42:12, endln:42:12 |vpiName:Y @@ -40259,7 +40259,7 @@ design: (work@sky130_fd_sc_hd__nand4bb) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__nand4bb.A_N), line:35:5, endln:35:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__nand4bb (work@sky130_fd_sc_hd__nand4bb), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand4bb.functional.v, line:33:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__nand4bb (work@sky130_fd_sc_hd__nand4bb), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand4bb.functional.v, line:33:1, endln:57:10 |vpiTypespec: \_logic_typespec: , line:43:12, endln:43:12 |vpiName:A_N @@ -40267,7 +40267,7 @@ design: (work@sky130_fd_sc_hd__nand4bb) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__nand4bb.B_N), line:36:5, endln:36:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__nand4bb (work@sky130_fd_sc_hd__nand4bb), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand4bb.functional.v, line:33:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__nand4bb (work@sky130_fd_sc_hd__nand4bb), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand4bb.functional.v, line:33:1, endln:57:10 |vpiTypespec: \_logic_typespec: , line:44:12, endln:44:12 |vpiName:B_N @@ -40275,7 +40275,7 @@ design: (work@sky130_fd_sc_hd__nand4bb) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__nand4bb.C), line:37:5, endln:37:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__nand4bb (work@sky130_fd_sc_hd__nand4bb), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand4bb.functional.v, line:33:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__nand4bb (work@sky130_fd_sc_hd__nand4bb), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand4bb.functional.v, line:33:1, endln:57:10 |vpiTypespec: \_logic_typespec: , line:45:12, endln:45:12 |vpiName:C @@ -40283,7 +40283,7 @@ design: (work@sky130_fd_sc_hd__nand4bb) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__nand4bb.D), line:38:5, endln:38:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__nand4bb (work@sky130_fd_sc_hd__nand4bb), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand4bb.functional.v, line:33:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__nand4bb (work@sky130_fd_sc_hd__nand4bb), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand4bb.functional.v, line:33:1, endln:57:10 |vpiTypespec: \_logic_typespec: , line:46:12, endln:46:12 |vpiName:D @@ -40292,7 +40292,7 @@ design: (work@sky130_fd_sc_hd__nand4bb) |vpiPort: \_port: (Y), line:34:5, endln:34:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__nand4bb (work@sky130_fd_sc_hd__nand4bb), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand4bb.functional.v, line:33:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__nand4bb (work@sky130_fd_sc_hd__nand4bb), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand4bb.functional.v, line:33:1, endln:57:10 |vpiName:Y |vpiDirection:2 |vpiLowConn: @@ -40306,7 +40306,7 @@ design: (work@sky130_fd_sc_hd__nand4bb) |vpiPort: \_port: (A_N), line:35:5, endln:35:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__nand4bb (work@sky130_fd_sc_hd__nand4bb), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand4bb.functional.v, line:33:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__nand4bb (work@sky130_fd_sc_hd__nand4bb), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand4bb.functional.v, line:33:1, endln:57:10 |vpiName:A_N |vpiDirection:1 |vpiLowConn: @@ -40320,7 +40320,7 @@ design: (work@sky130_fd_sc_hd__nand4bb) |vpiPort: \_port: (B_N), line:36:5, endln:36:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__nand4bb (work@sky130_fd_sc_hd__nand4bb), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand4bb.functional.v, line:33:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__nand4bb (work@sky130_fd_sc_hd__nand4bb), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand4bb.functional.v, line:33:1, endln:57:10 |vpiName:B_N |vpiDirection:1 |vpiLowConn: @@ -40334,7 +40334,7 @@ design: (work@sky130_fd_sc_hd__nand4bb) |vpiPort: \_port: (C), line:37:5, endln:37:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__nand4bb (work@sky130_fd_sc_hd__nand4bb), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand4bb.functional.v, line:33:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__nand4bb (work@sky130_fd_sc_hd__nand4bb), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand4bb.functional.v, line:33:1, endln:57:10 |vpiName:C |vpiDirection:1 |vpiLowConn: @@ -40348,7 +40348,7 @@ design: (work@sky130_fd_sc_hd__nand4bb) |vpiPort: \_port: (D), line:38:5, endln:38:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__nand4bb (work@sky130_fd_sc_hd__nand4bb), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand4bb.functional.v, line:33:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__nand4bb (work@sky130_fd_sc_hd__nand4bb), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand4bb.functional.v, line:33:1, endln:57:10 |vpiName:D |vpiDirection:1 |vpiLowConn: @@ -40362,7 +40362,7 @@ design: (work@sky130_fd_sc_hd__nand4bb) |vpiPrimitive: \_gate: work@nand (work@sky130_fd_sc_hd__nand4bb.nand0), line:53:10, endln:53:48 |vpiParent: - \_module: work@sky130_fd_sc_hd__nand4bb (work@sky130_fd_sc_hd__nand4bb), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand4bb.functional.v, line:33:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__nand4bb (work@sky130_fd_sc_hd__nand4bb), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand4bb.functional.v, line:33:1, endln:57:10 |vpiDefName:work@nand |vpiName:nand0 |vpiFullName:work@sky130_fd_sc_hd__nand4bb.nand0 @@ -40411,7 +40411,7 @@ design: (work@sky130_fd_sc_hd__nand4bb) |vpiPrimitive: \_gate: work@or (work@sky130_fd_sc_hd__nand4bb.or0), line:54:10, endln:54:48 |vpiParent: - \_module: work@sky130_fd_sc_hd__nand4bb (work@sky130_fd_sc_hd__nand4bb), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand4bb.functional.v, line:33:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__nand4bb (work@sky130_fd_sc_hd__nand4bb), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand4bb.functional.v, line:33:1, endln:57:10 |vpiDefName:work@or |vpiName:or0 |vpiFullName:work@sky130_fd_sc_hd__nand4bb.or0 @@ -40474,7 +40474,7 @@ design: (work@sky130_fd_sc_hd__nand4bb) |vpiPrimitive: \_gate: work@buf (work@sky130_fd_sc_hd__nand4bb.buf0), line:55:10, endln:55:48 |vpiParent: - \_module: work@sky130_fd_sc_hd__nand4bb (work@sky130_fd_sc_hd__nand4bb), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand4bb.functional.v, line:33:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__nand4bb (work@sky130_fd_sc_hd__nand4bb), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand4bb.functional.v, line:33:1, endln:57:10 |vpiDefName:work@buf |vpiName:buf0 |vpiFullName:work@sky130_fd_sc_hd__nand4bb.buf0 @@ -40517,7 +40517,7 @@ Processing: -cd cells/cells -DUNIT_DELAY -writepp -parse -nocache -nobuiltin -no design: (work@sky130_fd_sc_hd__nand2b) |vpiName:work@sky130_fd_sc_hd__nand2b |uhdmallModules: -\_module: work@sky130_fd_sc_hd__nand2b (work@sky130_fd_sc_hd__nand2b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand2b.functional.v, line:33:1, endln:53:10 +\_module_inst: work@sky130_fd_sc_hd__nand2b (work@sky130_fd_sc_hd__nand2b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand2b.functional.v, line:33:1, endln:53:10 |vpiParent: \_design: (work@sky130_fd_sc_hd__nand2b) |vpiFullName:work@sky130_fd_sc_hd__nand2b @@ -40525,39 +40525,39 @@ design: (work@sky130_fd_sc_hd__nand2b) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__nand2b.not0_out), line:45:10, endln:45:18 |vpiParent: - \_module: work@sky130_fd_sc_hd__nand2b (work@sky130_fd_sc_hd__nand2b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand2b.functional.v, line:33:1, endln:53:10 + \_module_inst: work@sky130_fd_sc_hd__nand2b (work@sky130_fd_sc_hd__nand2b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand2b.functional.v, line:33:1, endln:53:10 |vpiName:not0_out |vpiFullName:work@sky130_fd_sc_hd__nand2b.not0_out |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__nand2b.or0_out_Y), line:46:10, endln:46:19 |vpiParent: - \_module: work@sky130_fd_sc_hd__nand2b (work@sky130_fd_sc_hd__nand2b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand2b.functional.v, line:33:1, endln:53:10 + \_module_inst: work@sky130_fd_sc_hd__nand2b (work@sky130_fd_sc_hd__nand2b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand2b.functional.v, line:33:1, endln:53:10 |vpiName:or0_out_Y |vpiFullName:work@sky130_fd_sc_hd__nand2b.or0_out_Y |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__nand2b.Y), line:34:5, endln:34:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__nand2b (work@sky130_fd_sc_hd__nand2b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand2b.functional.v, line:33:1, endln:53:10 + \_module_inst: work@sky130_fd_sc_hd__nand2b (work@sky130_fd_sc_hd__nand2b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand2b.functional.v, line:33:1, endln:53:10 |vpiName:Y |vpiFullName:work@sky130_fd_sc_hd__nand2b.Y |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__nand2b.A_N), line:35:5, endln:35:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__nand2b (work@sky130_fd_sc_hd__nand2b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand2b.functional.v, line:33:1, endln:53:10 + \_module_inst: work@sky130_fd_sc_hd__nand2b (work@sky130_fd_sc_hd__nand2b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand2b.functional.v, line:33:1, endln:53:10 |vpiName:A_N |vpiFullName:work@sky130_fd_sc_hd__nand2b.A_N |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__nand2b.B), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__nand2b (work@sky130_fd_sc_hd__nand2b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand2b.functional.v, line:33:1, endln:53:10 + \_module_inst: work@sky130_fd_sc_hd__nand2b (work@sky130_fd_sc_hd__nand2b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand2b.functional.v, line:33:1, endln:53:10 |vpiName:B |vpiFullName:work@sky130_fd_sc_hd__nand2b.B |vpiPort: \_port: (Y), line:34:5, endln:34:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__nand2b (work@sky130_fd_sc_hd__nand2b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand2b.functional.v, line:33:1, endln:53:10 + \_module_inst: work@sky130_fd_sc_hd__nand2b (work@sky130_fd_sc_hd__nand2b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand2b.functional.v, line:33:1, endln:53:10 |vpiName:Y |vpiDirection:2 |vpiLowConn: @@ -40569,7 +40569,7 @@ design: (work@sky130_fd_sc_hd__nand2b) |vpiPort: \_port: (A_N), line:35:5, endln:35:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__nand2b (work@sky130_fd_sc_hd__nand2b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand2b.functional.v, line:33:1, endln:53:10 + \_module_inst: work@sky130_fd_sc_hd__nand2b (work@sky130_fd_sc_hd__nand2b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand2b.functional.v, line:33:1, endln:53:10 |vpiName:A_N |vpiDirection:1 |vpiLowConn: @@ -40581,7 +40581,7 @@ design: (work@sky130_fd_sc_hd__nand2b) |vpiPort: \_port: (B), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__nand2b (work@sky130_fd_sc_hd__nand2b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand2b.functional.v, line:33:1, endln:53:10 + \_module_inst: work@sky130_fd_sc_hd__nand2b (work@sky130_fd_sc_hd__nand2b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand2b.functional.v, line:33:1, endln:53:10 |vpiName:B |vpiDirection:1 |vpiLowConn: @@ -40591,14 +40591,14 @@ design: (work@sky130_fd_sc_hd__nand2b) |vpiTypedef: \_logic_typespec: , line:42:12, endln:42:12 |uhdmtopModules: -\_module: work@sky130_fd_sc_hd__nand2b (work@sky130_fd_sc_hd__nand2b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand2b.functional.v, line:33:1, endln:53:10 +\_module_inst: work@sky130_fd_sc_hd__nand2b (work@sky130_fd_sc_hd__nand2b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand2b.functional.v, line:33:1, endln:53:10 |vpiName:work@sky130_fd_sc_hd__nand2b |vpiDefName:work@sky130_fd_sc_hd__nand2b |vpiTop:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__nand2b.not0_out), line:45:10, endln:45:18 |vpiParent: - \_module: work@sky130_fd_sc_hd__nand2b (work@sky130_fd_sc_hd__nand2b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand2b.functional.v, line:33:1, endln:53:10 + \_module_inst: work@sky130_fd_sc_hd__nand2b (work@sky130_fd_sc_hd__nand2b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand2b.functional.v, line:33:1, endln:53:10 |vpiTypespec: \_logic_typespec: , line:45:5, endln:45:9 |vpiName:not0_out @@ -40607,7 +40607,7 @@ design: (work@sky130_fd_sc_hd__nand2b) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__nand2b.or0_out_Y), line:46:10, endln:46:19 |vpiParent: - \_module: work@sky130_fd_sc_hd__nand2b (work@sky130_fd_sc_hd__nand2b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand2b.functional.v, line:33:1, endln:53:10 + \_module_inst: work@sky130_fd_sc_hd__nand2b (work@sky130_fd_sc_hd__nand2b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand2b.functional.v, line:33:1, endln:53:10 |vpiTypespec: \_logic_typespec: , line:46:5, endln:46:9 |vpiName:or0_out_Y @@ -40616,7 +40616,7 @@ design: (work@sky130_fd_sc_hd__nand2b) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__nand2b.Y), line:34:5, endln:34:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__nand2b (work@sky130_fd_sc_hd__nand2b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand2b.functional.v, line:33:1, endln:53:10 + \_module_inst: work@sky130_fd_sc_hd__nand2b (work@sky130_fd_sc_hd__nand2b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand2b.functional.v, line:33:1, endln:53:10 |vpiTypespec: \_logic_typespec: , line:40:12, endln:40:12 |vpiName:Y @@ -40624,7 +40624,7 @@ design: (work@sky130_fd_sc_hd__nand2b) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__nand2b.A_N), line:35:5, endln:35:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__nand2b (work@sky130_fd_sc_hd__nand2b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand2b.functional.v, line:33:1, endln:53:10 + \_module_inst: work@sky130_fd_sc_hd__nand2b (work@sky130_fd_sc_hd__nand2b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand2b.functional.v, line:33:1, endln:53:10 |vpiTypespec: \_logic_typespec: , line:41:12, endln:41:12 |vpiName:A_N @@ -40632,7 +40632,7 @@ design: (work@sky130_fd_sc_hd__nand2b) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__nand2b.B), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__nand2b (work@sky130_fd_sc_hd__nand2b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand2b.functional.v, line:33:1, endln:53:10 + \_module_inst: work@sky130_fd_sc_hd__nand2b (work@sky130_fd_sc_hd__nand2b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand2b.functional.v, line:33:1, endln:53:10 |vpiTypespec: \_logic_typespec: , line:42:12, endln:42:12 |vpiName:B @@ -40641,7 +40641,7 @@ design: (work@sky130_fd_sc_hd__nand2b) |vpiPort: \_port: (Y), line:34:5, endln:34:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__nand2b (work@sky130_fd_sc_hd__nand2b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand2b.functional.v, line:33:1, endln:53:10 + \_module_inst: work@sky130_fd_sc_hd__nand2b (work@sky130_fd_sc_hd__nand2b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand2b.functional.v, line:33:1, endln:53:10 |vpiName:Y |vpiDirection:2 |vpiLowConn: @@ -40655,7 +40655,7 @@ design: (work@sky130_fd_sc_hd__nand2b) |vpiPort: \_port: (A_N), line:35:5, endln:35:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__nand2b (work@sky130_fd_sc_hd__nand2b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand2b.functional.v, line:33:1, endln:53:10 + \_module_inst: work@sky130_fd_sc_hd__nand2b (work@sky130_fd_sc_hd__nand2b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand2b.functional.v, line:33:1, endln:53:10 |vpiName:A_N |vpiDirection:1 |vpiLowConn: @@ -40669,7 +40669,7 @@ design: (work@sky130_fd_sc_hd__nand2b) |vpiPort: \_port: (B), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__nand2b (work@sky130_fd_sc_hd__nand2b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand2b.functional.v, line:33:1, endln:53:10 + \_module_inst: work@sky130_fd_sc_hd__nand2b (work@sky130_fd_sc_hd__nand2b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand2b.functional.v, line:33:1, endln:53:10 |vpiName:B |vpiDirection:1 |vpiLowConn: @@ -40683,7 +40683,7 @@ design: (work@sky130_fd_sc_hd__nand2b) |vpiPrimitive: \_gate: work@not (work@sky130_fd_sc_hd__nand2b.not0), line:49:9, endln:49:42 |vpiParent: - \_module: work@sky130_fd_sc_hd__nand2b (work@sky130_fd_sc_hd__nand2b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand2b.functional.v, line:33:1, endln:53:10 + \_module_inst: work@sky130_fd_sc_hd__nand2b (work@sky130_fd_sc_hd__nand2b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand2b.functional.v, line:33:1, endln:53:10 |vpiDefName:work@not |vpiName:not0 |vpiFullName:work@sky130_fd_sc_hd__nand2b.not0 @@ -40718,7 +40718,7 @@ design: (work@sky130_fd_sc_hd__nand2b) |vpiPrimitive: \_gate: work@or (work@sky130_fd_sc_hd__nand2b.or0), line:50:9, endln:50:42 |vpiParent: - \_module: work@sky130_fd_sc_hd__nand2b (work@sky130_fd_sc_hd__nand2b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand2b.functional.v, line:33:1, endln:53:10 + \_module_inst: work@sky130_fd_sc_hd__nand2b (work@sky130_fd_sc_hd__nand2b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand2b.functional.v, line:33:1, endln:53:10 |vpiDefName:work@or |vpiName:or0 |vpiFullName:work@sky130_fd_sc_hd__nand2b.or0 @@ -40767,7 +40767,7 @@ design: (work@sky130_fd_sc_hd__nand2b) |vpiPrimitive: \_gate: work@buf (work@sky130_fd_sc_hd__nand2b.buf0), line:51:9, endln:51:42 |vpiParent: - \_module: work@sky130_fd_sc_hd__nand2b (work@sky130_fd_sc_hd__nand2b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand2b.functional.v, line:33:1, endln:53:10 + \_module_inst: work@sky130_fd_sc_hd__nand2b (work@sky130_fd_sc_hd__nand2b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand2b.functional.v, line:33:1, endln:53:10 |vpiDefName:work@buf |vpiName:buf0 |vpiFullName:work@sky130_fd_sc_hd__nand2b.buf0 @@ -40810,7 +40810,7 @@ Processing: -cd cells/cells -DUNIT_DELAY -writepp -parse -nocache -nobuiltin -no design: (work@sky130_fd_sc_hd__nor3) |vpiName:work@sky130_fd_sc_hd__nor3 |uhdmallModules: -\_module: work@sky130_fd_sc_hd__nor3 (work@sky130_fd_sc_hd__nor3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor3.functional.v, line:35:1, endln:55:10 +\_module_inst: work@sky130_fd_sc_hd__nor3 (work@sky130_fd_sc_hd__nor3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor3.functional.v, line:35:1, endln:55:10 |vpiParent: \_design: (work@sky130_fd_sc_hd__nor3) |vpiFullName:work@sky130_fd_sc_hd__nor3 @@ -40818,38 +40818,38 @@ design: (work@sky130_fd_sc_hd__nor3) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__nor3.nor0_out_Y), line:49:10, endln:49:20 |vpiParent: - \_module: work@sky130_fd_sc_hd__nor3 (work@sky130_fd_sc_hd__nor3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor3.functional.v, line:35:1, endln:55:10 + \_module_inst: work@sky130_fd_sc_hd__nor3 (work@sky130_fd_sc_hd__nor3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor3.functional.v, line:35:1, endln:55:10 |vpiName:nor0_out_Y |vpiFullName:work@sky130_fd_sc_hd__nor3.nor0_out_Y |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__nor3.Y), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__nor3 (work@sky130_fd_sc_hd__nor3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor3.functional.v, line:35:1, endln:55:10 + \_module_inst: work@sky130_fd_sc_hd__nor3 (work@sky130_fd_sc_hd__nor3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor3.functional.v, line:35:1, endln:55:10 |vpiName:Y |vpiFullName:work@sky130_fd_sc_hd__nor3.Y |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__nor3.A), line:37:5, endln:37:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__nor3 (work@sky130_fd_sc_hd__nor3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor3.functional.v, line:35:1, endln:55:10 + \_module_inst: work@sky130_fd_sc_hd__nor3 (work@sky130_fd_sc_hd__nor3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor3.functional.v, line:35:1, endln:55:10 |vpiName:A |vpiFullName:work@sky130_fd_sc_hd__nor3.A |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__nor3.B), line:38:5, endln:38:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__nor3 (work@sky130_fd_sc_hd__nor3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor3.functional.v, line:35:1, endln:55:10 + \_module_inst: work@sky130_fd_sc_hd__nor3 (work@sky130_fd_sc_hd__nor3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor3.functional.v, line:35:1, endln:55:10 |vpiName:B |vpiFullName:work@sky130_fd_sc_hd__nor3.B |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__nor3.C), line:39:5, endln:39:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__nor3 (work@sky130_fd_sc_hd__nor3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor3.functional.v, line:35:1, endln:55:10 + \_module_inst: work@sky130_fd_sc_hd__nor3 (work@sky130_fd_sc_hd__nor3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor3.functional.v, line:35:1, endln:55:10 |vpiName:C |vpiFullName:work@sky130_fd_sc_hd__nor3.C |vpiPort: \_port: (Y), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__nor3 (work@sky130_fd_sc_hd__nor3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor3.functional.v, line:35:1, endln:55:10 + \_module_inst: work@sky130_fd_sc_hd__nor3 (work@sky130_fd_sc_hd__nor3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor3.functional.v, line:35:1, endln:55:10 |vpiName:Y |vpiDirection:2 |vpiLowConn: @@ -40861,7 +40861,7 @@ design: (work@sky130_fd_sc_hd__nor3) |vpiPort: \_port: (A), line:37:5, endln:37:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__nor3 (work@sky130_fd_sc_hd__nor3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor3.functional.v, line:35:1, endln:55:10 + \_module_inst: work@sky130_fd_sc_hd__nor3 (work@sky130_fd_sc_hd__nor3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor3.functional.v, line:35:1, endln:55:10 |vpiName:A |vpiDirection:1 |vpiLowConn: @@ -40873,7 +40873,7 @@ design: (work@sky130_fd_sc_hd__nor3) |vpiPort: \_port: (B), line:38:5, endln:38:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__nor3 (work@sky130_fd_sc_hd__nor3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor3.functional.v, line:35:1, endln:55:10 + \_module_inst: work@sky130_fd_sc_hd__nor3 (work@sky130_fd_sc_hd__nor3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor3.functional.v, line:35:1, endln:55:10 |vpiName:B |vpiDirection:1 |vpiLowConn: @@ -40885,7 +40885,7 @@ design: (work@sky130_fd_sc_hd__nor3) |vpiPort: \_port: (C), line:39:5, endln:39:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__nor3 (work@sky130_fd_sc_hd__nor3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor3.functional.v, line:35:1, endln:55:10 + \_module_inst: work@sky130_fd_sc_hd__nor3 (work@sky130_fd_sc_hd__nor3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor3.functional.v, line:35:1, endln:55:10 |vpiName:C |vpiDirection:1 |vpiLowConn: @@ -40895,14 +40895,14 @@ design: (work@sky130_fd_sc_hd__nor3) |vpiTypedef: \_logic_typespec: , line:46:12, endln:46:12 |uhdmtopModules: -\_module: work@sky130_fd_sc_hd__nor3 (work@sky130_fd_sc_hd__nor3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor3.functional.v, line:35:1, endln:55:10 +\_module_inst: work@sky130_fd_sc_hd__nor3 (work@sky130_fd_sc_hd__nor3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor3.functional.v, line:35:1, endln:55:10 |vpiName:work@sky130_fd_sc_hd__nor3 |vpiDefName:work@sky130_fd_sc_hd__nor3 |vpiTop:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__nor3.nor0_out_Y), line:49:10, endln:49:20 |vpiParent: - \_module: work@sky130_fd_sc_hd__nor3 (work@sky130_fd_sc_hd__nor3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor3.functional.v, line:35:1, endln:55:10 + \_module_inst: work@sky130_fd_sc_hd__nor3 (work@sky130_fd_sc_hd__nor3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor3.functional.v, line:35:1, endln:55:10 |vpiTypespec: \_logic_typespec: , line:49:5, endln:49:9 |vpiName:nor0_out_Y @@ -40911,7 +40911,7 @@ design: (work@sky130_fd_sc_hd__nor3) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__nor3.Y), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__nor3 (work@sky130_fd_sc_hd__nor3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor3.functional.v, line:35:1, endln:55:10 + \_module_inst: work@sky130_fd_sc_hd__nor3 (work@sky130_fd_sc_hd__nor3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor3.functional.v, line:35:1, endln:55:10 |vpiTypespec: \_logic_typespec: , line:43:12, endln:43:12 |vpiName:Y @@ -40919,7 +40919,7 @@ design: (work@sky130_fd_sc_hd__nor3) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__nor3.A), line:37:5, endln:37:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__nor3 (work@sky130_fd_sc_hd__nor3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor3.functional.v, line:35:1, endln:55:10 + \_module_inst: work@sky130_fd_sc_hd__nor3 (work@sky130_fd_sc_hd__nor3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor3.functional.v, line:35:1, endln:55:10 |vpiTypespec: \_logic_typespec: , line:44:12, endln:44:12 |vpiName:A @@ -40927,7 +40927,7 @@ design: (work@sky130_fd_sc_hd__nor3) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__nor3.B), line:38:5, endln:38:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__nor3 (work@sky130_fd_sc_hd__nor3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor3.functional.v, line:35:1, endln:55:10 + \_module_inst: work@sky130_fd_sc_hd__nor3 (work@sky130_fd_sc_hd__nor3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor3.functional.v, line:35:1, endln:55:10 |vpiTypespec: \_logic_typespec: , line:45:12, endln:45:12 |vpiName:B @@ -40935,7 +40935,7 @@ design: (work@sky130_fd_sc_hd__nor3) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__nor3.C), line:39:5, endln:39:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__nor3 (work@sky130_fd_sc_hd__nor3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor3.functional.v, line:35:1, endln:55:10 + \_module_inst: work@sky130_fd_sc_hd__nor3 (work@sky130_fd_sc_hd__nor3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor3.functional.v, line:35:1, endln:55:10 |vpiTypespec: \_logic_typespec: , line:46:12, endln:46:12 |vpiName:C @@ -40944,7 +40944,7 @@ design: (work@sky130_fd_sc_hd__nor3) |vpiPort: \_port: (Y), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__nor3 (work@sky130_fd_sc_hd__nor3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor3.functional.v, line:35:1, endln:55:10 + \_module_inst: work@sky130_fd_sc_hd__nor3 (work@sky130_fd_sc_hd__nor3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor3.functional.v, line:35:1, endln:55:10 |vpiName:Y |vpiDirection:2 |vpiLowConn: @@ -40958,7 +40958,7 @@ design: (work@sky130_fd_sc_hd__nor3) |vpiPort: \_port: (A), line:37:5, endln:37:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__nor3 (work@sky130_fd_sc_hd__nor3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor3.functional.v, line:35:1, endln:55:10 + \_module_inst: work@sky130_fd_sc_hd__nor3 (work@sky130_fd_sc_hd__nor3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor3.functional.v, line:35:1, endln:55:10 |vpiName:A |vpiDirection:1 |vpiLowConn: @@ -40972,7 +40972,7 @@ design: (work@sky130_fd_sc_hd__nor3) |vpiPort: \_port: (B), line:38:5, endln:38:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__nor3 (work@sky130_fd_sc_hd__nor3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor3.functional.v, line:35:1, endln:55:10 + \_module_inst: work@sky130_fd_sc_hd__nor3 (work@sky130_fd_sc_hd__nor3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor3.functional.v, line:35:1, endln:55:10 |vpiName:B |vpiDirection:1 |vpiLowConn: @@ -40986,7 +40986,7 @@ design: (work@sky130_fd_sc_hd__nor3) |vpiPort: \_port: (C), line:39:5, endln:39:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__nor3 (work@sky130_fd_sc_hd__nor3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor3.functional.v, line:35:1, endln:55:10 + \_module_inst: work@sky130_fd_sc_hd__nor3 (work@sky130_fd_sc_hd__nor3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor3.functional.v, line:35:1, endln:55:10 |vpiName:C |vpiDirection:1 |vpiLowConn: @@ -41000,7 +41000,7 @@ design: (work@sky130_fd_sc_hd__nor3) |vpiPrimitive: \_gate: work@nor (work@sky130_fd_sc_hd__nor3.nor0), line:52:9, endln:52:43 |vpiParent: - \_module: work@sky130_fd_sc_hd__nor3 (work@sky130_fd_sc_hd__nor3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor3.functional.v, line:35:1, endln:55:10 + \_module_inst: work@sky130_fd_sc_hd__nor3 (work@sky130_fd_sc_hd__nor3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor3.functional.v, line:35:1, endln:55:10 |vpiDefName:work@nor |vpiName:nor0 |vpiFullName:work@sky130_fd_sc_hd__nor3.nor0 @@ -41063,7 +41063,7 @@ design: (work@sky130_fd_sc_hd__nor3) |vpiPrimitive: \_gate: work@buf (work@sky130_fd_sc_hd__nor3.buf0), line:53:9, endln:53:43 |vpiParent: - \_module: work@sky130_fd_sc_hd__nor3 (work@sky130_fd_sc_hd__nor3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor3.functional.v, line:35:1, endln:55:10 + \_module_inst: work@sky130_fd_sc_hd__nor3 (work@sky130_fd_sc_hd__nor3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor3.functional.v, line:35:1, endln:55:10 |vpiDefName:work@buf |vpiName:buf0 |vpiFullName:work@sky130_fd_sc_hd__nor3.buf0 @@ -41106,7 +41106,7 @@ Processing: -cd cells/cells -DUNIT_DELAY -writepp -parse -nocache -nobuiltin -no design: (work@sky130_fd_sc_hd__a211o) |vpiName:work@sky130_fd_sc_hd__a211o |uhdmallModules: -\_module: work@sky130_fd_sc_hd__a211o (work@sky130_fd_sc_hd__a211o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a211o.functional.v, line:35:1, endln:59:10 +\_module_inst: work@sky130_fd_sc_hd__a211o (work@sky130_fd_sc_hd__a211o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a211o.functional.v, line:35:1, endln:59:10 |vpiParent: \_design: (work@sky130_fd_sc_hd__a211o) |vpiFullName:work@sky130_fd_sc_hd__a211o @@ -41114,51 +41114,51 @@ design: (work@sky130_fd_sc_hd__a211o) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a211o.and0_out), line:51:10, endln:51:18 |vpiParent: - \_module: work@sky130_fd_sc_hd__a211o (work@sky130_fd_sc_hd__a211o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a211o.functional.v, line:35:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__a211o (work@sky130_fd_sc_hd__a211o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a211o.functional.v, line:35:1, endln:59:10 |vpiName:and0_out |vpiFullName:work@sky130_fd_sc_hd__a211o.and0_out |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a211o.or0_out_X), line:52:10, endln:52:19 |vpiParent: - \_module: work@sky130_fd_sc_hd__a211o (work@sky130_fd_sc_hd__a211o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a211o.functional.v, line:35:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__a211o (work@sky130_fd_sc_hd__a211o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a211o.functional.v, line:35:1, endln:59:10 |vpiName:or0_out_X |vpiFullName:work@sky130_fd_sc_hd__a211o.or0_out_X |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a211o.X), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__a211o (work@sky130_fd_sc_hd__a211o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a211o.functional.v, line:35:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__a211o (work@sky130_fd_sc_hd__a211o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a211o.functional.v, line:35:1, endln:59:10 |vpiName:X |vpiFullName:work@sky130_fd_sc_hd__a211o.X |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a211o.A1), line:37:5, endln:37:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a211o (work@sky130_fd_sc_hd__a211o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a211o.functional.v, line:35:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__a211o (work@sky130_fd_sc_hd__a211o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a211o.functional.v, line:35:1, endln:59:10 |vpiName:A1 |vpiFullName:work@sky130_fd_sc_hd__a211o.A1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a211o.A2), line:38:5, endln:38:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a211o (work@sky130_fd_sc_hd__a211o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a211o.functional.v, line:35:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__a211o (work@sky130_fd_sc_hd__a211o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a211o.functional.v, line:35:1, endln:59:10 |vpiName:A2 |vpiFullName:work@sky130_fd_sc_hd__a211o.A2 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a211o.B1), line:39:5, endln:39:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a211o (work@sky130_fd_sc_hd__a211o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a211o.functional.v, line:35:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__a211o (work@sky130_fd_sc_hd__a211o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a211o.functional.v, line:35:1, endln:59:10 |vpiName:B1 |vpiFullName:work@sky130_fd_sc_hd__a211o.B1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a211o.C1), line:40:5, endln:40:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a211o (work@sky130_fd_sc_hd__a211o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a211o.functional.v, line:35:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__a211o (work@sky130_fd_sc_hd__a211o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a211o.functional.v, line:35:1, endln:59:10 |vpiName:C1 |vpiFullName:work@sky130_fd_sc_hd__a211o.C1 |vpiPort: \_port: (X), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__a211o (work@sky130_fd_sc_hd__a211o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a211o.functional.v, line:35:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__a211o (work@sky130_fd_sc_hd__a211o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a211o.functional.v, line:35:1, endln:59:10 |vpiName:X |vpiDirection:2 |vpiLowConn: @@ -41170,7 +41170,7 @@ design: (work@sky130_fd_sc_hd__a211o) |vpiPort: \_port: (A1), line:37:5, endln:37:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a211o (work@sky130_fd_sc_hd__a211o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a211o.functional.v, line:35:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__a211o (work@sky130_fd_sc_hd__a211o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a211o.functional.v, line:35:1, endln:59:10 |vpiName:A1 |vpiDirection:1 |vpiLowConn: @@ -41182,7 +41182,7 @@ design: (work@sky130_fd_sc_hd__a211o) |vpiPort: \_port: (A2), line:38:5, endln:38:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a211o (work@sky130_fd_sc_hd__a211o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a211o.functional.v, line:35:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__a211o (work@sky130_fd_sc_hd__a211o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a211o.functional.v, line:35:1, endln:59:10 |vpiName:A2 |vpiDirection:1 |vpiLowConn: @@ -41194,7 +41194,7 @@ design: (work@sky130_fd_sc_hd__a211o) |vpiPort: \_port: (B1), line:39:5, endln:39:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a211o (work@sky130_fd_sc_hd__a211o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a211o.functional.v, line:35:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__a211o (work@sky130_fd_sc_hd__a211o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a211o.functional.v, line:35:1, endln:59:10 |vpiName:B1 |vpiDirection:1 |vpiLowConn: @@ -41206,7 +41206,7 @@ design: (work@sky130_fd_sc_hd__a211o) |vpiPort: \_port: (C1), line:40:5, endln:40:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a211o (work@sky130_fd_sc_hd__a211o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a211o.functional.v, line:35:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__a211o (work@sky130_fd_sc_hd__a211o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a211o.functional.v, line:35:1, endln:59:10 |vpiName:C1 |vpiDirection:1 |vpiLowConn: @@ -41216,14 +41216,14 @@ design: (work@sky130_fd_sc_hd__a211o) |vpiTypedef: \_logic_typespec: , line:48:12, endln:48:12 |uhdmtopModules: -\_module: work@sky130_fd_sc_hd__a211o (work@sky130_fd_sc_hd__a211o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a211o.functional.v, line:35:1, endln:59:10 +\_module_inst: work@sky130_fd_sc_hd__a211o (work@sky130_fd_sc_hd__a211o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a211o.functional.v, line:35:1, endln:59:10 |vpiName:work@sky130_fd_sc_hd__a211o |vpiDefName:work@sky130_fd_sc_hd__a211o |vpiTop:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a211o.and0_out), line:51:10, endln:51:18 |vpiParent: - \_module: work@sky130_fd_sc_hd__a211o (work@sky130_fd_sc_hd__a211o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a211o.functional.v, line:35:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__a211o (work@sky130_fd_sc_hd__a211o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a211o.functional.v, line:35:1, endln:59:10 |vpiTypespec: \_logic_typespec: , line:51:5, endln:51:9 |vpiName:and0_out @@ -41232,7 +41232,7 @@ design: (work@sky130_fd_sc_hd__a211o) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a211o.or0_out_X), line:52:10, endln:52:19 |vpiParent: - \_module: work@sky130_fd_sc_hd__a211o (work@sky130_fd_sc_hd__a211o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a211o.functional.v, line:35:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__a211o (work@sky130_fd_sc_hd__a211o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a211o.functional.v, line:35:1, endln:59:10 |vpiTypespec: \_logic_typespec: , line:52:5, endln:52:9 |vpiName:or0_out_X @@ -41241,7 +41241,7 @@ design: (work@sky130_fd_sc_hd__a211o) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a211o.X), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__a211o (work@sky130_fd_sc_hd__a211o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a211o.functional.v, line:35:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__a211o (work@sky130_fd_sc_hd__a211o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a211o.functional.v, line:35:1, endln:59:10 |vpiTypespec: \_logic_typespec: , line:44:12, endln:44:12 |vpiName:X @@ -41249,7 +41249,7 @@ design: (work@sky130_fd_sc_hd__a211o) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a211o.A1), line:37:5, endln:37:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a211o (work@sky130_fd_sc_hd__a211o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a211o.functional.v, line:35:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__a211o (work@sky130_fd_sc_hd__a211o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a211o.functional.v, line:35:1, endln:59:10 |vpiTypespec: \_logic_typespec: , line:45:12, endln:45:12 |vpiName:A1 @@ -41257,7 +41257,7 @@ design: (work@sky130_fd_sc_hd__a211o) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a211o.A2), line:38:5, endln:38:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a211o (work@sky130_fd_sc_hd__a211o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a211o.functional.v, line:35:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__a211o (work@sky130_fd_sc_hd__a211o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a211o.functional.v, line:35:1, endln:59:10 |vpiTypespec: \_logic_typespec: , line:46:12, endln:46:12 |vpiName:A2 @@ -41265,7 +41265,7 @@ design: (work@sky130_fd_sc_hd__a211o) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a211o.B1), line:39:5, endln:39:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a211o (work@sky130_fd_sc_hd__a211o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a211o.functional.v, line:35:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__a211o (work@sky130_fd_sc_hd__a211o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a211o.functional.v, line:35:1, endln:59:10 |vpiTypespec: \_logic_typespec: , line:47:12, endln:47:12 |vpiName:B1 @@ -41273,7 +41273,7 @@ design: (work@sky130_fd_sc_hd__a211o) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a211o.C1), line:40:5, endln:40:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a211o (work@sky130_fd_sc_hd__a211o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a211o.functional.v, line:35:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__a211o (work@sky130_fd_sc_hd__a211o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a211o.functional.v, line:35:1, endln:59:10 |vpiTypespec: \_logic_typespec: , line:48:12, endln:48:12 |vpiName:C1 @@ -41282,7 +41282,7 @@ design: (work@sky130_fd_sc_hd__a211o) |vpiPort: \_port: (X), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__a211o (work@sky130_fd_sc_hd__a211o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a211o.functional.v, line:35:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__a211o (work@sky130_fd_sc_hd__a211o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a211o.functional.v, line:35:1, endln:59:10 |vpiName:X |vpiDirection:2 |vpiLowConn: @@ -41296,7 +41296,7 @@ design: (work@sky130_fd_sc_hd__a211o) |vpiPort: \_port: (A1), line:37:5, endln:37:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a211o (work@sky130_fd_sc_hd__a211o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a211o.functional.v, line:35:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__a211o (work@sky130_fd_sc_hd__a211o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a211o.functional.v, line:35:1, endln:59:10 |vpiName:A1 |vpiDirection:1 |vpiLowConn: @@ -41310,7 +41310,7 @@ design: (work@sky130_fd_sc_hd__a211o) |vpiPort: \_port: (A2), line:38:5, endln:38:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a211o (work@sky130_fd_sc_hd__a211o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a211o.functional.v, line:35:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__a211o (work@sky130_fd_sc_hd__a211o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a211o.functional.v, line:35:1, endln:59:10 |vpiName:A2 |vpiDirection:1 |vpiLowConn: @@ -41324,7 +41324,7 @@ design: (work@sky130_fd_sc_hd__a211o) |vpiPort: \_port: (B1), line:39:5, endln:39:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a211o (work@sky130_fd_sc_hd__a211o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a211o.functional.v, line:35:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__a211o (work@sky130_fd_sc_hd__a211o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a211o.functional.v, line:35:1, endln:59:10 |vpiName:B1 |vpiDirection:1 |vpiLowConn: @@ -41338,7 +41338,7 @@ design: (work@sky130_fd_sc_hd__a211o) |vpiPort: \_port: (C1), line:40:5, endln:40:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a211o (work@sky130_fd_sc_hd__a211o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a211o.functional.v, line:35:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__a211o (work@sky130_fd_sc_hd__a211o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a211o.functional.v, line:35:1, endln:59:10 |vpiName:C1 |vpiDirection:1 |vpiLowConn: @@ -41352,7 +41352,7 @@ design: (work@sky130_fd_sc_hd__a211o) |vpiPrimitive: \_gate: work@and (work@sky130_fd_sc_hd__a211o.and0), line:55:9, endln:55:43 |vpiParent: - \_module: work@sky130_fd_sc_hd__a211o (work@sky130_fd_sc_hd__a211o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a211o.functional.v, line:35:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__a211o (work@sky130_fd_sc_hd__a211o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a211o.functional.v, line:35:1, endln:59:10 |vpiDefName:work@and |vpiName:and0 |vpiFullName:work@sky130_fd_sc_hd__a211o.and0 @@ -41401,7 +41401,7 @@ design: (work@sky130_fd_sc_hd__a211o) |vpiPrimitive: \_gate: work@or (work@sky130_fd_sc_hd__a211o.or0), line:56:9, endln:56:43 |vpiParent: - \_module: work@sky130_fd_sc_hd__a211o (work@sky130_fd_sc_hd__a211o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a211o.functional.v, line:35:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__a211o (work@sky130_fd_sc_hd__a211o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a211o.functional.v, line:35:1, endln:59:10 |vpiDefName:work@or |vpiName:or0 |vpiFullName:work@sky130_fd_sc_hd__a211o.or0 @@ -41464,7 +41464,7 @@ design: (work@sky130_fd_sc_hd__a211o) |vpiPrimitive: \_gate: work@buf (work@sky130_fd_sc_hd__a211o.buf0), line:57:9, endln:57:43 |vpiParent: - \_module: work@sky130_fd_sc_hd__a211o (work@sky130_fd_sc_hd__a211o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a211o.functional.v, line:35:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__a211o (work@sky130_fd_sc_hd__a211o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a211o.functional.v, line:35:1, endln:59:10 |vpiDefName:work@buf |vpiName:buf0 |vpiFullName:work@sky130_fd_sc_hd__a211o.buf0 @@ -41581,7 +41581,7 @@ design: (work@sky130_fd_sc_hd__dlxbn) |vpiSize:2 |STRING:1 x : 1 : 1 |uhdmallModules: -\_module: work@sky130_fd_sc_hd__dlxbn (work@sky130_fd_sc_hd__dlxbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlxbn.functional.v, line:36:1, endln:59:10 +\_module_inst: work@sky130_fd_sc_hd__dlxbn (work@sky130_fd_sc_hd__dlxbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlxbn.functional.v, line:36:1, endln:59:10 |vpiParent: \_design: (work@sky130_fd_sc_hd__dlxbn) |vpiFullName:work@sky130_fd_sc_hd__dlxbn @@ -41589,45 +41589,45 @@ design: (work@sky130_fd_sc_hd__dlxbn) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__dlxbn.GATE), line:50:10, endln:50:14 |vpiParent: - \_module: work@sky130_fd_sc_hd__dlxbn (work@sky130_fd_sc_hd__dlxbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlxbn.functional.v, line:36:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__dlxbn (work@sky130_fd_sc_hd__dlxbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlxbn.functional.v, line:36:1, endln:59:10 |vpiName:GATE |vpiFullName:work@sky130_fd_sc_hd__dlxbn.GATE |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__dlxbn.buf_Q), line:51:10, endln:51:15 |vpiParent: - \_module: work@sky130_fd_sc_hd__dlxbn (work@sky130_fd_sc_hd__dlxbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlxbn.functional.v, line:36:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__dlxbn (work@sky130_fd_sc_hd__dlxbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlxbn.functional.v, line:36:1, endln:59:10 |vpiName:buf_Q |vpiFullName:work@sky130_fd_sc_hd__dlxbn.buf_Q |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__dlxbn.Q), line:37:5, endln:37:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__dlxbn (work@sky130_fd_sc_hd__dlxbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlxbn.functional.v, line:36:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__dlxbn (work@sky130_fd_sc_hd__dlxbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlxbn.functional.v, line:36:1, endln:59:10 |vpiName:Q |vpiFullName:work@sky130_fd_sc_hd__dlxbn.Q |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__dlxbn.Q_N), line:38:5, endln:38:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__dlxbn (work@sky130_fd_sc_hd__dlxbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlxbn.functional.v, line:36:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__dlxbn (work@sky130_fd_sc_hd__dlxbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlxbn.functional.v, line:36:1, endln:59:10 |vpiName:Q_N |vpiFullName:work@sky130_fd_sc_hd__dlxbn.Q_N |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__dlxbn.D), line:39:5, endln:39:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__dlxbn (work@sky130_fd_sc_hd__dlxbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlxbn.functional.v, line:36:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__dlxbn (work@sky130_fd_sc_hd__dlxbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlxbn.functional.v, line:36:1, endln:59:10 |vpiName:D |vpiFullName:work@sky130_fd_sc_hd__dlxbn.D |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__dlxbn.GATE_N), line:40:5, endln:40:11 |vpiParent: - \_module: work@sky130_fd_sc_hd__dlxbn (work@sky130_fd_sc_hd__dlxbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlxbn.functional.v, line:36:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__dlxbn (work@sky130_fd_sc_hd__dlxbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlxbn.functional.v, line:36:1, endln:59:10 |vpiName:GATE_N |vpiFullName:work@sky130_fd_sc_hd__dlxbn.GATE_N |vpiPort: \_port: (Q), line:37:5, endln:37:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__dlxbn (work@sky130_fd_sc_hd__dlxbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlxbn.functional.v, line:36:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__dlxbn (work@sky130_fd_sc_hd__dlxbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlxbn.functional.v, line:36:1, endln:59:10 |vpiName:Q |vpiDirection:2 |vpiLowConn: @@ -41639,7 +41639,7 @@ design: (work@sky130_fd_sc_hd__dlxbn) |vpiPort: \_port: (Q_N), line:38:5, endln:38:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__dlxbn (work@sky130_fd_sc_hd__dlxbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlxbn.functional.v, line:36:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__dlxbn (work@sky130_fd_sc_hd__dlxbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlxbn.functional.v, line:36:1, endln:59:10 |vpiName:Q_N |vpiDirection:2 |vpiLowConn: @@ -41651,7 +41651,7 @@ design: (work@sky130_fd_sc_hd__dlxbn) |vpiPort: \_port: (D), line:39:5, endln:39:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__dlxbn (work@sky130_fd_sc_hd__dlxbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlxbn.functional.v, line:36:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__dlxbn (work@sky130_fd_sc_hd__dlxbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlxbn.functional.v, line:36:1, endln:59:10 |vpiName:D |vpiDirection:1 |vpiLowConn: @@ -41663,7 +41663,7 @@ design: (work@sky130_fd_sc_hd__dlxbn) |vpiPort: \_port: (GATE_N), line:40:5, endln:40:11 |vpiParent: - \_module: work@sky130_fd_sc_hd__dlxbn (work@sky130_fd_sc_hd__dlxbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlxbn.functional.v, line:36:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__dlxbn (work@sky130_fd_sc_hd__dlxbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlxbn.functional.v, line:36:1, endln:59:10 |vpiName:GATE_N |vpiDirection:1 |vpiLowConn: @@ -41673,14 +41673,14 @@ design: (work@sky130_fd_sc_hd__dlxbn) |vpiTypedef: \_logic_typespec: , line:47:12, endln:47:12 |uhdmtopModules: -\_module: work@sky130_fd_sc_hd__dlxbn (work@sky130_fd_sc_hd__dlxbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlxbn.functional.v, line:36:1, endln:59:10 +\_module_inst: work@sky130_fd_sc_hd__dlxbn (work@sky130_fd_sc_hd__dlxbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlxbn.functional.v, line:36:1, endln:59:10 |vpiName:work@sky130_fd_sc_hd__dlxbn |vpiDefName:work@sky130_fd_sc_hd__dlxbn |vpiTop:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__dlxbn.GATE), line:50:10, endln:50:14 |vpiParent: - \_module: work@sky130_fd_sc_hd__dlxbn (work@sky130_fd_sc_hd__dlxbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlxbn.functional.v, line:36:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__dlxbn (work@sky130_fd_sc_hd__dlxbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlxbn.functional.v, line:36:1, endln:59:10 |vpiTypespec: \_logic_typespec: , line:50:5, endln:50:9 |vpiName:GATE @@ -41689,7 +41689,7 @@ design: (work@sky130_fd_sc_hd__dlxbn) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__dlxbn.buf_Q), line:51:10, endln:51:15 |vpiParent: - \_module: work@sky130_fd_sc_hd__dlxbn (work@sky130_fd_sc_hd__dlxbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlxbn.functional.v, line:36:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__dlxbn (work@sky130_fd_sc_hd__dlxbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlxbn.functional.v, line:36:1, endln:59:10 |vpiTypespec: \_logic_typespec: , line:51:5, endln:51:9 |vpiName:buf_Q @@ -41698,7 +41698,7 @@ design: (work@sky130_fd_sc_hd__dlxbn) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__dlxbn.Q), line:37:5, endln:37:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__dlxbn (work@sky130_fd_sc_hd__dlxbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlxbn.functional.v, line:36:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__dlxbn (work@sky130_fd_sc_hd__dlxbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlxbn.functional.v, line:36:1, endln:59:10 |vpiTypespec: \_logic_typespec: , line:44:12, endln:44:12 |vpiName:Q @@ -41706,7 +41706,7 @@ design: (work@sky130_fd_sc_hd__dlxbn) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__dlxbn.Q_N), line:38:5, endln:38:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__dlxbn (work@sky130_fd_sc_hd__dlxbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlxbn.functional.v, line:36:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__dlxbn (work@sky130_fd_sc_hd__dlxbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlxbn.functional.v, line:36:1, endln:59:10 |vpiTypespec: \_logic_typespec: , line:45:12, endln:45:12 |vpiName:Q_N @@ -41714,7 +41714,7 @@ design: (work@sky130_fd_sc_hd__dlxbn) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__dlxbn.D), line:39:5, endln:39:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__dlxbn (work@sky130_fd_sc_hd__dlxbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlxbn.functional.v, line:36:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__dlxbn (work@sky130_fd_sc_hd__dlxbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlxbn.functional.v, line:36:1, endln:59:10 |vpiTypespec: \_logic_typespec: , line:46:12, endln:46:12 |vpiName:D @@ -41722,7 +41722,7 @@ design: (work@sky130_fd_sc_hd__dlxbn) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__dlxbn.GATE_N), line:40:5, endln:40:11 |vpiParent: - \_module: work@sky130_fd_sc_hd__dlxbn (work@sky130_fd_sc_hd__dlxbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlxbn.functional.v, line:36:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__dlxbn (work@sky130_fd_sc_hd__dlxbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlxbn.functional.v, line:36:1, endln:59:10 |vpiTypespec: \_logic_typespec: , line:47:12, endln:47:12 |vpiName:GATE_N @@ -41731,7 +41731,7 @@ design: (work@sky130_fd_sc_hd__dlxbn) |vpiPort: \_port: (Q), line:37:5, endln:37:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__dlxbn (work@sky130_fd_sc_hd__dlxbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlxbn.functional.v, line:36:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__dlxbn (work@sky130_fd_sc_hd__dlxbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlxbn.functional.v, line:36:1, endln:59:10 |vpiName:Q |vpiDirection:2 |vpiLowConn: @@ -41745,7 +41745,7 @@ design: (work@sky130_fd_sc_hd__dlxbn) |vpiPort: \_port: (Q_N), line:38:5, endln:38:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__dlxbn (work@sky130_fd_sc_hd__dlxbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlxbn.functional.v, line:36:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__dlxbn (work@sky130_fd_sc_hd__dlxbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlxbn.functional.v, line:36:1, endln:59:10 |vpiName:Q_N |vpiDirection:2 |vpiLowConn: @@ -41759,7 +41759,7 @@ design: (work@sky130_fd_sc_hd__dlxbn) |vpiPort: \_port: (D), line:39:5, endln:39:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__dlxbn (work@sky130_fd_sc_hd__dlxbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlxbn.functional.v, line:36:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__dlxbn (work@sky130_fd_sc_hd__dlxbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlxbn.functional.v, line:36:1, endln:59:10 |vpiName:D |vpiDirection:1 |vpiLowConn: @@ -41773,7 +41773,7 @@ design: (work@sky130_fd_sc_hd__dlxbn) |vpiPort: \_port: (GATE_N), line:40:5, endln:40:11 |vpiParent: - \_module: work@sky130_fd_sc_hd__dlxbn (work@sky130_fd_sc_hd__dlxbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlxbn.functional.v, line:36:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__dlxbn (work@sky130_fd_sc_hd__dlxbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlxbn.functional.v, line:36:1, endln:59:10 |vpiName:GATE_N |vpiDirection:1 |vpiLowConn: @@ -41787,7 +41787,7 @@ design: (work@sky130_fd_sc_hd__dlxbn) |vpiPrimitive: \_gate: work@not (work@sky130_fd_sc_hd__dlxbn.not0), line:54:47, endln:54:80 |vpiParent: - \_module: work@sky130_fd_sc_hd__dlxbn (work@sky130_fd_sc_hd__dlxbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlxbn.functional.v, line:36:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__dlxbn (work@sky130_fd_sc_hd__dlxbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlxbn.functional.v, line:36:1, endln:59:10 |vpiDefName:work@not |vpiName:not0 |vpiFullName:work@sky130_fd_sc_hd__dlxbn.not0 @@ -41822,7 +41822,7 @@ design: (work@sky130_fd_sc_hd__dlxbn) |vpiPrimitive: \_udp: work@sky130_fd_sc_hd__udp_dlatch$P (work@sky130_fd_sc_hd__dlxbn.dlatch0), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlxbn.functional.v, line:55:5, endln:55:70 |vpiParent: - \_module: work@sky130_fd_sc_hd__dlxbn (work@sky130_fd_sc_hd__dlxbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlxbn.functional.v, line:36:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__dlxbn (work@sky130_fd_sc_hd__dlxbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlxbn.functional.v, line:36:1, endln:59:10 |vpiDefName:work@sky130_fd_sc_hd__udp_dlatch$P |vpiName:dlatch0 |vpiFullName:work@sky130_fd_sc_hd__dlxbn.dlatch0 @@ -41831,7 +41831,7 @@ design: (work@sky130_fd_sc_hd__dlxbn) |vpiPrimitive: \_gate: work@buf (work@sky130_fd_sc_hd__dlxbn.buf0), line:56:47, endln:56:80 |vpiParent: - \_module: work@sky130_fd_sc_hd__dlxbn (work@sky130_fd_sc_hd__dlxbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlxbn.functional.v, line:36:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__dlxbn (work@sky130_fd_sc_hd__dlxbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlxbn.functional.v, line:36:1, endln:59:10 |vpiDefName:work@buf |vpiName:buf0 |vpiFullName:work@sky130_fd_sc_hd__dlxbn.buf0 @@ -41866,7 +41866,7 @@ design: (work@sky130_fd_sc_hd__dlxbn) |vpiPrimitive: \_gate: work@not (work@sky130_fd_sc_hd__dlxbn.not1), line:57:47, endln:57:80 |vpiParent: - \_module: work@sky130_fd_sc_hd__dlxbn (work@sky130_fd_sc_hd__dlxbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlxbn.functional.v, line:36:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__dlxbn (work@sky130_fd_sc_hd__dlxbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlxbn.functional.v, line:36:1, endln:59:10 |vpiDefName:work@not |vpiName:not1 |vpiFullName:work@sky130_fd_sc_hd__dlxbn.not1 @@ -41909,7 +41909,7 @@ Processing: -cd cells/cells -DUNIT_DELAY -writepp -parse -nocache -nobuiltin -no design: (work@sky130_fd_sc_hd__maj3) |vpiName:work@sky130_fd_sc_hd__maj3 |uhdmallModules: -\_module: work@sky130_fd_sc_hd__maj3 (work@sky130_fd_sc_hd__maj3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__maj3.functional.v, line:33:1, endln:59:10 +\_module_inst: work@sky130_fd_sc_hd__maj3 (work@sky130_fd_sc_hd__maj3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__maj3.functional.v, line:33:1, endln:59:10 |vpiParent: \_design: (work@sky130_fd_sc_hd__maj3) |vpiFullName:work@sky130_fd_sc_hd__maj3 @@ -41917,59 +41917,59 @@ design: (work@sky130_fd_sc_hd__maj3) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__maj3.or0_out), line:47:10, endln:47:17 |vpiParent: - \_module: work@sky130_fd_sc_hd__maj3 (work@sky130_fd_sc_hd__maj3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__maj3.functional.v, line:33:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__maj3 (work@sky130_fd_sc_hd__maj3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__maj3.functional.v, line:33:1, endln:59:10 |vpiName:or0_out |vpiFullName:work@sky130_fd_sc_hd__maj3.or0_out |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__maj3.and0_out), line:48:10, endln:48:18 |vpiParent: - \_module: work@sky130_fd_sc_hd__maj3 (work@sky130_fd_sc_hd__maj3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__maj3.functional.v, line:33:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__maj3 (work@sky130_fd_sc_hd__maj3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__maj3.functional.v, line:33:1, endln:59:10 |vpiName:and0_out |vpiFullName:work@sky130_fd_sc_hd__maj3.and0_out |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__maj3.and1_out), line:49:10, endln:49:18 |vpiParent: - \_module: work@sky130_fd_sc_hd__maj3 (work@sky130_fd_sc_hd__maj3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__maj3.functional.v, line:33:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__maj3 (work@sky130_fd_sc_hd__maj3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__maj3.functional.v, line:33:1, endln:59:10 |vpiName:and1_out |vpiFullName:work@sky130_fd_sc_hd__maj3.and1_out |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__maj3.or1_out_X), line:50:10, endln:50:19 |vpiParent: - \_module: work@sky130_fd_sc_hd__maj3 (work@sky130_fd_sc_hd__maj3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__maj3.functional.v, line:33:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__maj3 (work@sky130_fd_sc_hd__maj3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__maj3.functional.v, line:33:1, endln:59:10 |vpiName:or1_out_X |vpiFullName:work@sky130_fd_sc_hd__maj3.or1_out_X |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__maj3.X), line:34:5, endln:34:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__maj3 (work@sky130_fd_sc_hd__maj3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__maj3.functional.v, line:33:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__maj3 (work@sky130_fd_sc_hd__maj3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__maj3.functional.v, line:33:1, endln:59:10 |vpiName:X |vpiFullName:work@sky130_fd_sc_hd__maj3.X |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__maj3.A), line:35:5, endln:35:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__maj3 (work@sky130_fd_sc_hd__maj3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__maj3.functional.v, line:33:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__maj3 (work@sky130_fd_sc_hd__maj3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__maj3.functional.v, line:33:1, endln:59:10 |vpiName:A |vpiFullName:work@sky130_fd_sc_hd__maj3.A |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__maj3.B), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__maj3 (work@sky130_fd_sc_hd__maj3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__maj3.functional.v, line:33:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__maj3 (work@sky130_fd_sc_hd__maj3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__maj3.functional.v, line:33:1, endln:59:10 |vpiName:B |vpiFullName:work@sky130_fd_sc_hd__maj3.B |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__maj3.C), line:37:5, endln:37:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__maj3 (work@sky130_fd_sc_hd__maj3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__maj3.functional.v, line:33:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__maj3 (work@sky130_fd_sc_hd__maj3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__maj3.functional.v, line:33:1, endln:59:10 |vpiName:C |vpiFullName:work@sky130_fd_sc_hd__maj3.C |vpiPort: \_port: (X), line:34:5, endln:34:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__maj3 (work@sky130_fd_sc_hd__maj3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__maj3.functional.v, line:33:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__maj3 (work@sky130_fd_sc_hd__maj3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__maj3.functional.v, line:33:1, endln:59:10 |vpiName:X |vpiDirection:2 |vpiLowConn: @@ -41981,7 +41981,7 @@ design: (work@sky130_fd_sc_hd__maj3) |vpiPort: \_port: (A), line:35:5, endln:35:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__maj3 (work@sky130_fd_sc_hd__maj3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__maj3.functional.v, line:33:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__maj3 (work@sky130_fd_sc_hd__maj3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__maj3.functional.v, line:33:1, endln:59:10 |vpiName:A |vpiDirection:1 |vpiLowConn: @@ -41993,7 +41993,7 @@ design: (work@sky130_fd_sc_hd__maj3) |vpiPort: \_port: (B), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__maj3 (work@sky130_fd_sc_hd__maj3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__maj3.functional.v, line:33:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__maj3 (work@sky130_fd_sc_hd__maj3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__maj3.functional.v, line:33:1, endln:59:10 |vpiName:B |vpiDirection:1 |vpiLowConn: @@ -42005,7 +42005,7 @@ design: (work@sky130_fd_sc_hd__maj3) |vpiPort: \_port: (C), line:37:5, endln:37:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__maj3 (work@sky130_fd_sc_hd__maj3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__maj3.functional.v, line:33:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__maj3 (work@sky130_fd_sc_hd__maj3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__maj3.functional.v, line:33:1, endln:59:10 |vpiName:C |vpiDirection:1 |vpiLowConn: @@ -42015,14 +42015,14 @@ design: (work@sky130_fd_sc_hd__maj3) |vpiTypedef: \_logic_typespec: , line:44:12, endln:44:12 |uhdmtopModules: -\_module: work@sky130_fd_sc_hd__maj3 (work@sky130_fd_sc_hd__maj3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__maj3.functional.v, line:33:1, endln:59:10 +\_module_inst: work@sky130_fd_sc_hd__maj3 (work@sky130_fd_sc_hd__maj3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__maj3.functional.v, line:33:1, endln:59:10 |vpiName:work@sky130_fd_sc_hd__maj3 |vpiDefName:work@sky130_fd_sc_hd__maj3 |vpiTop:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__maj3.or0_out), line:47:10, endln:47:17 |vpiParent: - \_module: work@sky130_fd_sc_hd__maj3 (work@sky130_fd_sc_hd__maj3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__maj3.functional.v, line:33:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__maj3 (work@sky130_fd_sc_hd__maj3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__maj3.functional.v, line:33:1, endln:59:10 |vpiTypespec: \_logic_typespec: , line:47:5, endln:47:9 |vpiName:or0_out @@ -42031,7 +42031,7 @@ design: (work@sky130_fd_sc_hd__maj3) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__maj3.and0_out), line:48:10, endln:48:18 |vpiParent: - \_module: work@sky130_fd_sc_hd__maj3 (work@sky130_fd_sc_hd__maj3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__maj3.functional.v, line:33:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__maj3 (work@sky130_fd_sc_hd__maj3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__maj3.functional.v, line:33:1, endln:59:10 |vpiTypespec: \_logic_typespec: , line:48:5, endln:48:9 |vpiName:and0_out @@ -42040,7 +42040,7 @@ design: (work@sky130_fd_sc_hd__maj3) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__maj3.and1_out), line:49:10, endln:49:18 |vpiParent: - \_module: work@sky130_fd_sc_hd__maj3 (work@sky130_fd_sc_hd__maj3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__maj3.functional.v, line:33:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__maj3 (work@sky130_fd_sc_hd__maj3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__maj3.functional.v, line:33:1, endln:59:10 |vpiTypespec: \_logic_typespec: , line:49:5, endln:49:9 |vpiName:and1_out @@ -42049,7 +42049,7 @@ design: (work@sky130_fd_sc_hd__maj3) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__maj3.or1_out_X), line:50:10, endln:50:19 |vpiParent: - \_module: work@sky130_fd_sc_hd__maj3 (work@sky130_fd_sc_hd__maj3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__maj3.functional.v, line:33:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__maj3 (work@sky130_fd_sc_hd__maj3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__maj3.functional.v, line:33:1, endln:59:10 |vpiTypespec: \_logic_typespec: , line:50:5, endln:50:9 |vpiName:or1_out_X @@ -42058,7 +42058,7 @@ design: (work@sky130_fd_sc_hd__maj3) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__maj3.X), line:34:5, endln:34:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__maj3 (work@sky130_fd_sc_hd__maj3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__maj3.functional.v, line:33:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__maj3 (work@sky130_fd_sc_hd__maj3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__maj3.functional.v, line:33:1, endln:59:10 |vpiTypespec: \_logic_typespec: , line:41:12, endln:41:12 |vpiName:X @@ -42066,7 +42066,7 @@ design: (work@sky130_fd_sc_hd__maj3) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__maj3.A), line:35:5, endln:35:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__maj3 (work@sky130_fd_sc_hd__maj3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__maj3.functional.v, line:33:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__maj3 (work@sky130_fd_sc_hd__maj3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__maj3.functional.v, line:33:1, endln:59:10 |vpiTypespec: \_logic_typespec: , line:42:12, endln:42:12 |vpiName:A @@ -42074,7 +42074,7 @@ design: (work@sky130_fd_sc_hd__maj3) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__maj3.B), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__maj3 (work@sky130_fd_sc_hd__maj3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__maj3.functional.v, line:33:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__maj3 (work@sky130_fd_sc_hd__maj3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__maj3.functional.v, line:33:1, endln:59:10 |vpiTypespec: \_logic_typespec: , line:43:12, endln:43:12 |vpiName:B @@ -42082,7 +42082,7 @@ design: (work@sky130_fd_sc_hd__maj3) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__maj3.C), line:37:5, endln:37:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__maj3 (work@sky130_fd_sc_hd__maj3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__maj3.functional.v, line:33:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__maj3 (work@sky130_fd_sc_hd__maj3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__maj3.functional.v, line:33:1, endln:59:10 |vpiTypespec: \_logic_typespec: , line:44:12, endln:44:12 |vpiName:C @@ -42091,7 +42091,7 @@ design: (work@sky130_fd_sc_hd__maj3) |vpiPort: \_port: (X), line:34:5, endln:34:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__maj3 (work@sky130_fd_sc_hd__maj3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__maj3.functional.v, line:33:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__maj3 (work@sky130_fd_sc_hd__maj3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__maj3.functional.v, line:33:1, endln:59:10 |vpiName:X |vpiDirection:2 |vpiLowConn: @@ -42105,7 +42105,7 @@ design: (work@sky130_fd_sc_hd__maj3) |vpiPort: \_port: (A), line:35:5, endln:35:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__maj3 (work@sky130_fd_sc_hd__maj3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__maj3.functional.v, line:33:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__maj3 (work@sky130_fd_sc_hd__maj3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__maj3.functional.v, line:33:1, endln:59:10 |vpiName:A |vpiDirection:1 |vpiLowConn: @@ -42119,7 +42119,7 @@ design: (work@sky130_fd_sc_hd__maj3) |vpiPort: \_port: (B), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__maj3 (work@sky130_fd_sc_hd__maj3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__maj3.functional.v, line:33:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__maj3 (work@sky130_fd_sc_hd__maj3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__maj3.functional.v, line:33:1, endln:59:10 |vpiName:B |vpiDirection:1 |vpiLowConn: @@ -42133,7 +42133,7 @@ design: (work@sky130_fd_sc_hd__maj3) |vpiPort: \_port: (C), line:37:5, endln:37:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__maj3 (work@sky130_fd_sc_hd__maj3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__maj3.functional.v, line:33:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__maj3 (work@sky130_fd_sc_hd__maj3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__maj3.functional.v, line:33:1, endln:59:10 |vpiName:C |vpiDirection:1 |vpiLowConn: @@ -42147,7 +42147,7 @@ design: (work@sky130_fd_sc_hd__maj3) |vpiPrimitive: \_gate: work@or (work@sky130_fd_sc_hd__maj3.or0), line:53:9, endln:53:45 |vpiParent: - \_module: work@sky130_fd_sc_hd__maj3 (work@sky130_fd_sc_hd__maj3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__maj3.functional.v, line:33:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__maj3 (work@sky130_fd_sc_hd__maj3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__maj3.functional.v, line:33:1, endln:59:10 |vpiDefName:work@or |vpiName:or0 |vpiFullName:work@sky130_fd_sc_hd__maj3.or0 @@ -42196,7 +42196,7 @@ design: (work@sky130_fd_sc_hd__maj3) |vpiPrimitive: \_gate: work@and (work@sky130_fd_sc_hd__maj3.and0), line:54:9, endln:54:45 |vpiParent: - \_module: work@sky130_fd_sc_hd__maj3 (work@sky130_fd_sc_hd__maj3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__maj3.functional.v, line:33:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__maj3 (work@sky130_fd_sc_hd__maj3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__maj3.functional.v, line:33:1, endln:59:10 |vpiDefName:work@and |vpiName:and0 |vpiFullName:work@sky130_fd_sc_hd__maj3.and0 @@ -42245,7 +42245,7 @@ design: (work@sky130_fd_sc_hd__maj3) |vpiPrimitive: \_gate: work@and (work@sky130_fd_sc_hd__maj3.and1), line:55:9, endln:55:45 |vpiParent: - \_module: work@sky130_fd_sc_hd__maj3 (work@sky130_fd_sc_hd__maj3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__maj3.functional.v, line:33:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__maj3 (work@sky130_fd_sc_hd__maj3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__maj3.functional.v, line:33:1, endln:59:10 |vpiDefName:work@and |vpiName:and1 |vpiFullName:work@sky130_fd_sc_hd__maj3.and1 @@ -42294,7 +42294,7 @@ design: (work@sky130_fd_sc_hd__maj3) |vpiPrimitive: \_gate: work@or (work@sky130_fd_sc_hd__maj3.or1), line:56:9, endln:56:45 |vpiParent: - \_module: work@sky130_fd_sc_hd__maj3 (work@sky130_fd_sc_hd__maj3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__maj3.functional.v, line:33:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__maj3 (work@sky130_fd_sc_hd__maj3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__maj3.functional.v, line:33:1, endln:59:10 |vpiDefName:work@or |vpiName:or1 |vpiFullName:work@sky130_fd_sc_hd__maj3.or1 @@ -42343,7 +42343,7 @@ design: (work@sky130_fd_sc_hd__maj3) |vpiPrimitive: \_gate: work@buf (work@sky130_fd_sc_hd__maj3.buf0), line:57:9, endln:57:45 |vpiParent: - \_module: work@sky130_fd_sc_hd__maj3 (work@sky130_fd_sc_hd__maj3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__maj3.functional.v, line:33:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__maj3 (work@sky130_fd_sc_hd__maj3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__maj3.functional.v, line:33:1, endln:59:10 |vpiDefName:work@buf |vpiName:buf0 |vpiFullName:work@sky130_fd_sc_hd__maj3.buf0 @@ -42386,7 +42386,7 @@ Processing: -cd cells/cells -DUNIT_DELAY -writepp -parse -nocache -nobuiltin -no design: (work@sky130_fd_sc_hd__a21bo) |vpiName:work@sky130_fd_sc_hd__a21bo |uhdmallModules: -\_module: work@sky130_fd_sc_hd__a21bo (work@sky130_fd_sc_hd__a21bo), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a21bo.functional.v, line:36:1, endln:58:10 +\_module_inst: work@sky130_fd_sc_hd__a21bo (work@sky130_fd_sc_hd__a21bo), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a21bo.functional.v, line:36:1, endln:58:10 |vpiParent: \_design: (work@sky130_fd_sc_hd__a21bo) |vpiFullName:work@sky130_fd_sc_hd__a21bo @@ -42394,45 +42394,45 @@ design: (work@sky130_fd_sc_hd__a21bo) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a21bo.nand0_out), line:50:10, endln:50:19 |vpiParent: - \_module: work@sky130_fd_sc_hd__a21bo (work@sky130_fd_sc_hd__a21bo), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a21bo.functional.v, line:36:1, endln:58:10 + \_module_inst: work@sky130_fd_sc_hd__a21bo (work@sky130_fd_sc_hd__a21bo), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a21bo.functional.v, line:36:1, endln:58:10 |vpiName:nand0_out |vpiFullName:work@sky130_fd_sc_hd__a21bo.nand0_out |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a21bo.nand1_out_X), line:51:10, endln:51:21 |vpiParent: - \_module: work@sky130_fd_sc_hd__a21bo (work@sky130_fd_sc_hd__a21bo), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a21bo.functional.v, line:36:1, endln:58:10 + \_module_inst: work@sky130_fd_sc_hd__a21bo (work@sky130_fd_sc_hd__a21bo), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a21bo.functional.v, line:36:1, endln:58:10 |vpiName:nand1_out_X |vpiFullName:work@sky130_fd_sc_hd__a21bo.nand1_out_X |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a21bo.X), line:37:5, endln:37:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__a21bo (work@sky130_fd_sc_hd__a21bo), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a21bo.functional.v, line:36:1, endln:58:10 + \_module_inst: work@sky130_fd_sc_hd__a21bo (work@sky130_fd_sc_hd__a21bo), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a21bo.functional.v, line:36:1, endln:58:10 |vpiName:X |vpiFullName:work@sky130_fd_sc_hd__a21bo.X |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a21bo.A1), line:38:5, endln:38:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a21bo (work@sky130_fd_sc_hd__a21bo), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a21bo.functional.v, line:36:1, endln:58:10 + \_module_inst: work@sky130_fd_sc_hd__a21bo (work@sky130_fd_sc_hd__a21bo), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a21bo.functional.v, line:36:1, endln:58:10 |vpiName:A1 |vpiFullName:work@sky130_fd_sc_hd__a21bo.A1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a21bo.A2), line:39:5, endln:39:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a21bo (work@sky130_fd_sc_hd__a21bo), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a21bo.functional.v, line:36:1, endln:58:10 + \_module_inst: work@sky130_fd_sc_hd__a21bo (work@sky130_fd_sc_hd__a21bo), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a21bo.functional.v, line:36:1, endln:58:10 |vpiName:A2 |vpiFullName:work@sky130_fd_sc_hd__a21bo.A2 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a21bo.B1_N), line:40:5, endln:40:9 |vpiParent: - \_module: work@sky130_fd_sc_hd__a21bo (work@sky130_fd_sc_hd__a21bo), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a21bo.functional.v, line:36:1, endln:58:10 + \_module_inst: work@sky130_fd_sc_hd__a21bo (work@sky130_fd_sc_hd__a21bo), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a21bo.functional.v, line:36:1, endln:58:10 |vpiName:B1_N |vpiFullName:work@sky130_fd_sc_hd__a21bo.B1_N |vpiPort: \_port: (X), line:37:5, endln:37:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__a21bo (work@sky130_fd_sc_hd__a21bo), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a21bo.functional.v, line:36:1, endln:58:10 + \_module_inst: work@sky130_fd_sc_hd__a21bo (work@sky130_fd_sc_hd__a21bo), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a21bo.functional.v, line:36:1, endln:58:10 |vpiName:X |vpiDirection:2 |vpiLowConn: @@ -42444,7 +42444,7 @@ design: (work@sky130_fd_sc_hd__a21bo) |vpiPort: \_port: (A1), line:38:5, endln:38:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a21bo (work@sky130_fd_sc_hd__a21bo), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a21bo.functional.v, line:36:1, endln:58:10 + \_module_inst: work@sky130_fd_sc_hd__a21bo (work@sky130_fd_sc_hd__a21bo), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a21bo.functional.v, line:36:1, endln:58:10 |vpiName:A1 |vpiDirection:1 |vpiLowConn: @@ -42456,7 +42456,7 @@ design: (work@sky130_fd_sc_hd__a21bo) |vpiPort: \_port: (A2), line:39:5, endln:39:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a21bo (work@sky130_fd_sc_hd__a21bo), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a21bo.functional.v, line:36:1, endln:58:10 + \_module_inst: work@sky130_fd_sc_hd__a21bo (work@sky130_fd_sc_hd__a21bo), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a21bo.functional.v, line:36:1, endln:58:10 |vpiName:A2 |vpiDirection:1 |vpiLowConn: @@ -42468,7 +42468,7 @@ design: (work@sky130_fd_sc_hd__a21bo) |vpiPort: \_port: (B1_N), line:40:5, endln:40:9 |vpiParent: - \_module: work@sky130_fd_sc_hd__a21bo (work@sky130_fd_sc_hd__a21bo), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a21bo.functional.v, line:36:1, endln:58:10 + \_module_inst: work@sky130_fd_sc_hd__a21bo (work@sky130_fd_sc_hd__a21bo), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a21bo.functional.v, line:36:1, endln:58:10 |vpiName:B1_N |vpiDirection:1 |vpiLowConn: @@ -42478,14 +42478,14 @@ design: (work@sky130_fd_sc_hd__a21bo) |vpiTypedef: \_logic_typespec: , line:47:12, endln:47:12 |uhdmtopModules: -\_module: work@sky130_fd_sc_hd__a21bo (work@sky130_fd_sc_hd__a21bo), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a21bo.functional.v, line:36:1, endln:58:10 +\_module_inst: work@sky130_fd_sc_hd__a21bo (work@sky130_fd_sc_hd__a21bo), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a21bo.functional.v, line:36:1, endln:58:10 |vpiName:work@sky130_fd_sc_hd__a21bo |vpiDefName:work@sky130_fd_sc_hd__a21bo |vpiTop:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a21bo.nand0_out), line:50:10, endln:50:19 |vpiParent: - \_module: work@sky130_fd_sc_hd__a21bo (work@sky130_fd_sc_hd__a21bo), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a21bo.functional.v, line:36:1, endln:58:10 + \_module_inst: work@sky130_fd_sc_hd__a21bo (work@sky130_fd_sc_hd__a21bo), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a21bo.functional.v, line:36:1, endln:58:10 |vpiTypespec: \_logic_typespec: , line:50:5, endln:50:9 |vpiName:nand0_out @@ -42494,7 +42494,7 @@ design: (work@sky130_fd_sc_hd__a21bo) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a21bo.nand1_out_X), line:51:10, endln:51:21 |vpiParent: - \_module: work@sky130_fd_sc_hd__a21bo (work@sky130_fd_sc_hd__a21bo), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a21bo.functional.v, line:36:1, endln:58:10 + \_module_inst: work@sky130_fd_sc_hd__a21bo (work@sky130_fd_sc_hd__a21bo), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a21bo.functional.v, line:36:1, endln:58:10 |vpiTypespec: \_logic_typespec: , line:51:5, endln:51:9 |vpiName:nand1_out_X @@ -42503,7 +42503,7 @@ design: (work@sky130_fd_sc_hd__a21bo) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a21bo.X), line:37:5, endln:37:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__a21bo (work@sky130_fd_sc_hd__a21bo), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a21bo.functional.v, line:36:1, endln:58:10 + \_module_inst: work@sky130_fd_sc_hd__a21bo (work@sky130_fd_sc_hd__a21bo), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a21bo.functional.v, line:36:1, endln:58:10 |vpiTypespec: \_logic_typespec: , line:44:12, endln:44:12 |vpiName:X @@ -42511,7 +42511,7 @@ design: (work@sky130_fd_sc_hd__a21bo) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a21bo.A1), line:38:5, endln:38:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a21bo (work@sky130_fd_sc_hd__a21bo), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a21bo.functional.v, line:36:1, endln:58:10 + \_module_inst: work@sky130_fd_sc_hd__a21bo (work@sky130_fd_sc_hd__a21bo), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a21bo.functional.v, line:36:1, endln:58:10 |vpiTypespec: \_logic_typespec: , line:45:12, endln:45:12 |vpiName:A1 @@ -42519,7 +42519,7 @@ design: (work@sky130_fd_sc_hd__a21bo) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a21bo.A2), line:39:5, endln:39:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a21bo (work@sky130_fd_sc_hd__a21bo), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a21bo.functional.v, line:36:1, endln:58:10 + \_module_inst: work@sky130_fd_sc_hd__a21bo (work@sky130_fd_sc_hd__a21bo), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a21bo.functional.v, line:36:1, endln:58:10 |vpiTypespec: \_logic_typespec: , line:46:12, endln:46:12 |vpiName:A2 @@ -42527,7 +42527,7 @@ design: (work@sky130_fd_sc_hd__a21bo) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a21bo.B1_N), line:40:5, endln:40:9 |vpiParent: - \_module: work@sky130_fd_sc_hd__a21bo (work@sky130_fd_sc_hd__a21bo), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a21bo.functional.v, line:36:1, endln:58:10 + \_module_inst: work@sky130_fd_sc_hd__a21bo (work@sky130_fd_sc_hd__a21bo), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a21bo.functional.v, line:36:1, endln:58:10 |vpiTypespec: \_logic_typespec: , line:47:12, endln:47:12 |vpiName:B1_N @@ -42536,7 +42536,7 @@ design: (work@sky130_fd_sc_hd__a21bo) |vpiPort: \_port: (X), line:37:5, endln:37:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__a21bo (work@sky130_fd_sc_hd__a21bo), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a21bo.functional.v, line:36:1, endln:58:10 + \_module_inst: work@sky130_fd_sc_hd__a21bo (work@sky130_fd_sc_hd__a21bo), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a21bo.functional.v, line:36:1, endln:58:10 |vpiName:X |vpiDirection:2 |vpiLowConn: @@ -42550,7 +42550,7 @@ design: (work@sky130_fd_sc_hd__a21bo) |vpiPort: \_port: (A1), line:38:5, endln:38:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a21bo (work@sky130_fd_sc_hd__a21bo), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a21bo.functional.v, line:36:1, endln:58:10 + \_module_inst: work@sky130_fd_sc_hd__a21bo (work@sky130_fd_sc_hd__a21bo), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a21bo.functional.v, line:36:1, endln:58:10 |vpiName:A1 |vpiDirection:1 |vpiLowConn: @@ -42564,7 +42564,7 @@ design: (work@sky130_fd_sc_hd__a21bo) |vpiPort: \_port: (A2), line:39:5, endln:39:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a21bo (work@sky130_fd_sc_hd__a21bo), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a21bo.functional.v, line:36:1, endln:58:10 + \_module_inst: work@sky130_fd_sc_hd__a21bo (work@sky130_fd_sc_hd__a21bo), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a21bo.functional.v, line:36:1, endln:58:10 |vpiName:A2 |vpiDirection:1 |vpiLowConn: @@ -42578,7 +42578,7 @@ design: (work@sky130_fd_sc_hd__a21bo) |vpiPort: \_port: (B1_N), line:40:5, endln:40:9 |vpiParent: - \_module: work@sky130_fd_sc_hd__a21bo (work@sky130_fd_sc_hd__a21bo), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a21bo.functional.v, line:36:1, endln:58:10 + \_module_inst: work@sky130_fd_sc_hd__a21bo (work@sky130_fd_sc_hd__a21bo), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a21bo.functional.v, line:36:1, endln:58:10 |vpiName:B1_N |vpiDirection:1 |vpiLowConn: @@ -42592,7 +42592,7 @@ design: (work@sky130_fd_sc_hd__a21bo) |vpiPrimitive: \_gate: work@nand (work@sky130_fd_sc_hd__a21bo.nand0), line:54:10, endln:54:46 |vpiParent: - \_module: work@sky130_fd_sc_hd__a21bo (work@sky130_fd_sc_hd__a21bo), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a21bo.functional.v, line:36:1, endln:58:10 + \_module_inst: work@sky130_fd_sc_hd__a21bo (work@sky130_fd_sc_hd__a21bo), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a21bo.functional.v, line:36:1, endln:58:10 |vpiDefName:work@nand |vpiName:nand0 |vpiFullName:work@sky130_fd_sc_hd__a21bo.nand0 @@ -42641,7 +42641,7 @@ design: (work@sky130_fd_sc_hd__a21bo) |vpiPrimitive: \_gate: work@nand (work@sky130_fd_sc_hd__a21bo.nand1), line:55:10, endln:55:46 |vpiParent: - \_module: work@sky130_fd_sc_hd__a21bo (work@sky130_fd_sc_hd__a21bo), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a21bo.functional.v, line:36:1, endln:58:10 + \_module_inst: work@sky130_fd_sc_hd__a21bo (work@sky130_fd_sc_hd__a21bo), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a21bo.functional.v, line:36:1, endln:58:10 |vpiDefName:work@nand |vpiName:nand1 |vpiFullName:work@sky130_fd_sc_hd__a21bo.nand1 @@ -42690,7 +42690,7 @@ design: (work@sky130_fd_sc_hd__a21bo) |vpiPrimitive: \_gate: work@buf (work@sky130_fd_sc_hd__a21bo.buf0), line:56:10, endln:56:46 |vpiParent: - \_module: work@sky130_fd_sc_hd__a21bo (work@sky130_fd_sc_hd__a21bo), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a21bo.functional.v, line:36:1, endln:58:10 + \_module_inst: work@sky130_fd_sc_hd__a21bo (work@sky130_fd_sc_hd__a21bo), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a21bo.functional.v, line:36:1, endln:58:10 |vpiDefName:work@buf |vpiName:buf0 |vpiFullName:work@sky130_fd_sc_hd__a21bo.buf0 @@ -42843,7 +42843,7 @@ design: (work@sky130_fd_sc_hd__dlrbn) |vpiSize:3 |STRING:0 x x : 0 : 0 |uhdmallModules: -\_module: work@sky130_fd_sc_hd__dlrbn (work@sky130_fd_sc_hd__dlrbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlrbn.functional.v, line:37:1, endln:64:10 +\_module_inst: work@sky130_fd_sc_hd__dlrbn (work@sky130_fd_sc_hd__dlrbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlrbn.functional.v, line:37:1, endln:64:10 |vpiParent: \_design: (work@sky130_fd_sc_hd__dlrbn) |vpiFullName:work@sky130_fd_sc_hd__dlrbn @@ -42851,58 +42851,58 @@ design: (work@sky130_fd_sc_hd__dlrbn) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__dlrbn.RESET), line:53:10, endln:53:15 |vpiParent: - \_module: work@sky130_fd_sc_hd__dlrbn (work@sky130_fd_sc_hd__dlrbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlrbn.functional.v, line:37:1, endln:64:10 + \_module_inst: work@sky130_fd_sc_hd__dlrbn (work@sky130_fd_sc_hd__dlrbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlrbn.functional.v, line:37:1, endln:64:10 |vpiName:RESET |vpiFullName:work@sky130_fd_sc_hd__dlrbn.RESET |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__dlrbn.intgate), line:54:10, endln:54:17 |vpiParent: - \_module: work@sky130_fd_sc_hd__dlrbn (work@sky130_fd_sc_hd__dlrbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlrbn.functional.v, line:37:1, endln:64:10 + \_module_inst: work@sky130_fd_sc_hd__dlrbn (work@sky130_fd_sc_hd__dlrbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlrbn.functional.v, line:37:1, endln:64:10 |vpiName:intgate |vpiFullName:work@sky130_fd_sc_hd__dlrbn.intgate |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__dlrbn.buf_Q), line:55:10, endln:55:15 |vpiParent: - \_module: work@sky130_fd_sc_hd__dlrbn (work@sky130_fd_sc_hd__dlrbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlrbn.functional.v, line:37:1, endln:64:10 + \_module_inst: work@sky130_fd_sc_hd__dlrbn (work@sky130_fd_sc_hd__dlrbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlrbn.functional.v, line:37:1, endln:64:10 |vpiName:buf_Q |vpiFullName:work@sky130_fd_sc_hd__dlrbn.buf_Q |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__dlrbn.Q), line:38:5, endln:38:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__dlrbn (work@sky130_fd_sc_hd__dlrbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlrbn.functional.v, line:37:1, endln:64:10 + \_module_inst: work@sky130_fd_sc_hd__dlrbn (work@sky130_fd_sc_hd__dlrbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlrbn.functional.v, line:37:1, endln:64:10 |vpiName:Q |vpiFullName:work@sky130_fd_sc_hd__dlrbn.Q |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__dlrbn.Q_N), line:39:5, endln:39:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__dlrbn (work@sky130_fd_sc_hd__dlrbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlrbn.functional.v, line:37:1, endln:64:10 + \_module_inst: work@sky130_fd_sc_hd__dlrbn (work@sky130_fd_sc_hd__dlrbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlrbn.functional.v, line:37:1, endln:64:10 |vpiName:Q_N |vpiFullName:work@sky130_fd_sc_hd__dlrbn.Q_N |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__dlrbn.RESET_B), line:40:5, endln:40:12 |vpiParent: - \_module: work@sky130_fd_sc_hd__dlrbn (work@sky130_fd_sc_hd__dlrbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlrbn.functional.v, line:37:1, endln:64:10 + \_module_inst: work@sky130_fd_sc_hd__dlrbn (work@sky130_fd_sc_hd__dlrbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlrbn.functional.v, line:37:1, endln:64:10 |vpiName:RESET_B |vpiFullName:work@sky130_fd_sc_hd__dlrbn.RESET_B |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__dlrbn.D), line:41:5, endln:41:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__dlrbn (work@sky130_fd_sc_hd__dlrbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlrbn.functional.v, line:37:1, endln:64:10 + \_module_inst: work@sky130_fd_sc_hd__dlrbn (work@sky130_fd_sc_hd__dlrbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlrbn.functional.v, line:37:1, endln:64:10 |vpiName:D |vpiFullName:work@sky130_fd_sc_hd__dlrbn.D |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__dlrbn.GATE_N), line:42:5, endln:42:11 |vpiParent: - \_module: work@sky130_fd_sc_hd__dlrbn (work@sky130_fd_sc_hd__dlrbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlrbn.functional.v, line:37:1, endln:64:10 + \_module_inst: work@sky130_fd_sc_hd__dlrbn (work@sky130_fd_sc_hd__dlrbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlrbn.functional.v, line:37:1, endln:64:10 |vpiName:GATE_N |vpiFullName:work@sky130_fd_sc_hd__dlrbn.GATE_N |vpiPort: \_port: (Q), line:38:5, endln:38:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__dlrbn (work@sky130_fd_sc_hd__dlrbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlrbn.functional.v, line:37:1, endln:64:10 + \_module_inst: work@sky130_fd_sc_hd__dlrbn (work@sky130_fd_sc_hd__dlrbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlrbn.functional.v, line:37:1, endln:64:10 |vpiName:Q |vpiDirection:2 |vpiLowConn: @@ -42914,7 +42914,7 @@ design: (work@sky130_fd_sc_hd__dlrbn) |vpiPort: \_port: (Q_N), line:39:5, endln:39:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__dlrbn (work@sky130_fd_sc_hd__dlrbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlrbn.functional.v, line:37:1, endln:64:10 + \_module_inst: work@sky130_fd_sc_hd__dlrbn (work@sky130_fd_sc_hd__dlrbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlrbn.functional.v, line:37:1, endln:64:10 |vpiName:Q_N |vpiDirection:2 |vpiLowConn: @@ -42926,7 +42926,7 @@ design: (work@sky130_fd_sc_hd__dlrbn) |vpiPort: \_port: (RESET_B), line:40:5, endln:40:12 |vpiParent: - \_module: work@sky130_fd_sc_hd__dlrbn (work@sky130_fd_sc_hd__dlrbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlrbn.functional.v, line:37:1, endln:64:10 + \_module_inst: work@sky130_fd_sc_hd__dlrbn (work@sky130_fd_sc_hd__dlrbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlrbn.functional.v, line:37:1, endln:64:10 |vpiName:RESET_B |vpiDirection:1 |vpiLowConn: @@ -42938,7 +42938,7 @@ design: (work@sky130_fd_sc_hd__dlrbn) |vpiPort: \_port: (D), line:41:5, endln:41:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__dlrbn (work@sky130_fd_sc_hd__dlrbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlrbn.functional.v, line:37:1, endln:64:10 + \_module_inst: work@sky130_fd_sc_hd__dlrbn (work@sky130_fd_sc_hd__dlrbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlrbn.functional.v, line:37:1, endln:64:10 |vpiName:D |vpiDirection:1 |vpiLowConn: @@ -42950,7 +42950,7 @@ design: (work@sky130_fd_sc_hd__dlrbn) |vpiPort: \_port: (GATE_N), line:42:5, endln:42:11 |vpiParent: - \_module: work@sky130_fd_sc_hd__dlrbn (work@sky130_fd_sc_hd__dlrbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlrbn.functional.v, line:37:1, endln:64:10 + \_module_inst: work@sky130_fd_sc_hd__dlrbn (work@sky130_fd_sc_hd__dlrbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlrbn.functional.v, line:37:1, endln:64:10 |vpiName:GATE_N |vpiDirection:1 |vpiLowConn: @@ -42960,14 +42960,14 @@ design: (work@sky130_fd_sc_hd__dlrbn) |vpiTypedef: \_logic_typespec: , line:50:12, endln:50:12 |uhdmtopModules: -\_module: work@sky130_fd_sc_hd__dlrbn (work@sky130_fd_sc_hd__dlrbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlrbn.functional.v, line:37:1, endln:64:10 +\_module_inst: work@sky130_fd_sc_hd__dlrbn (work@sky130_fd_sc_hd__dlrbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlrbn.functional.v, line:37:1, endln:64:10 |vpiName:work@sky130_fd_sc_hd__dlrbn |vpiDefName:work@sky130_fd_sc_hd__dlrbn |vpiTop:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__dlrbn.RESET), line:53:10, endln:53:15 |vpiParent: - \_module: work@sky130_fd_sc_hd__dlrbn (work@sky130_fd_sc_hd__dlrbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlrbn.functional.v, line:37:1, endln:64:10 + \_module_inst: work@sky130_fd_sc_hd__dlrbn (work@sky130_fd_sc_hd__dlrbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlrbn.functional.v, line:37:1, endln:64:10 |vpiTypespec: \_logic_typespec: , line:53:5, endln:53:9 |vpiName:RESET @@ -42976,7 +42976,7 @@ design: (work@sky130_fd_sc_hd__dlrbn) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__dlrbn.intgate), line:54:10, endln:54:17 |vpiParent: - \_module: work@sky130_fd_sc_hd__dlrbn (work@sky130_fd_sc_hd__dlrbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlrbn.functional.v, line:37:1, endln:64:10 + \_module_inst: work@sky130_fd_sc_hd__dlrbn (work@sky130_fd_sc_hd__dlrbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlrbn.functional.v, line:37:1, endln:64:10 |vpiTypespec: \_logic_typespec: , line:54:5, endln:54:9 |vpiName:intgate @@ -42985,7 +42985,7 @@ design: (work@sky130_fd_sc_hd__dlrbn) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__dlrbn.buf_Q), line:55:10, endln:55:15 |vpiParent: - \_module: work@sky130_fd_sc_hd__dlrbn (work@sky130_fd_sc_hd__dlrbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlrbn.functional.v, line:37:1, endln:64:10 + \_module_inst: work@sky130_fd_sc_hd__dlrbn (work@sky130_fd_sc_hd__dlrbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlrbn.functional.v, line:37:1, endln:64:10 |vpiTypespec: \_logic_typespec: , line:55:5, endln:55:9 |vpiName:buf_Q @@ -42994,7 +42994,7 @@ design: (work@sky130_fd_sc_hd__dlrbn) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__dlrbn.Q), line:38:5, endln:38:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__dlrbn (work@sky130_fd_sc_hd__dlrbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlrbn.functional.v, line:37:1, endln:64:10 + \_module_inst: work@sky130_fd_sc_hd__dlrbn (work@sky130_fd_sc_hd__dlrbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlrbn.functional.v, line:37:1, endln:64:10 |vpiTypespec: \_logic_typespec: , line:46:12, endln:46:12 |vpiName:Q @@ -43002,7 +43002,7 @@ design: (work@sky130_fd_sc_hd__dlrbn) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__dlrbn.Q_N), line:39:5, endln:39:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__dlrbn (work@sky130_fd_sc_hd__dlrbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlrbn.functional.v, line:37:1, endln:64:10 + \_module_inst: work@sky130_fd_sc_hd__dlrbn (work@sky130_fd_sc_hd__dlrbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlrbn.functional.v, line:37:1, endln:64:10 |vpiTypespec: \_logic_typespec: , line:47:12, endln:47:12 |vpiName:Q_N @@ -43010,7 +43010,7 @@ design: (work@sky130_fd_sc_hd__dlrbn) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__dlrbn.RESET_B), line:40:5, endln:40:12 |vpiParent: - \_module: work@sky130_fd_sc_hd__dlrbn (work@sky130_fd_sc_hd__dlrbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlrbn.functional.v, line:37:1, endln:64:10 + \_module_inst: work@sky130_fd_sc_hd__dlrbn (work@sky130_fd_sc_hd__dlrbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlrbn.functional.v, line:37:1, endln:64:10 |vpiTypespec: \_logic_typespec: , line:48:12, endln:48:12 |vpiName:RESET_B @@ -43018,7 +43018,7 @@ design: (work@sky130_fd_sc_hd__dlrbn) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__dlrbn.D), line:41:5, endln:41:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__dlrbn (work@sky130_fd_sc_hd__dlrbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlrbn.functional.v, line:37:1, endln:64:10 + \_module_inst: work@sky130_fd_sc_hd__dlrbn (work@sky130_fd_sc_hd__dlrbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlrbn.functional.v, line:37:1, endln:64:10 |vpiTypespec: \_logic_typespec: , line:49:12, endln:49:12 |vpiName:D @@ -43026,7 +43026,7 @@ design: (work@sky130_fd_sc_hd__dlrbn) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__dlrbn.GATE_N), line:42:5, endln:42:11 |vpiParent: - \_module: work@sky130_fd_sc_hd__dlrbn (work@sky130_fd_sc_hd__dlrbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlrbn.functional.v, line:37:1, endln:64:10 + \_module_inst: work@sky130_fd_sc_hd__dlrbn (work@sky130_fd_sc_hd__dlrbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlrbn.functional.v, line:37:1, endln:64:10 |vpiTypespec: \_logic_typespec: , line:50:12, endln:50:12 |vpiName:GATE_N @@ -43035,7 +43035,7 @@ design: (work@sky130_fd_sc_hd__dlrbn) |vpiPort: \_port: (Q), line:38:5, endln:38:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__dlrbn (work@sky130_fd_sc_hd__dlrbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlrbn.functional.v, line:37:1, endln:64:10 + \_module_inst: work@sky130_fd_sc_hd__dlrbn (work@sky130_fd_sc_hd__dlrbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlrbn.functional.v, line:37:1, endln:64:10 |vpiName:Q |vpiDirection:2 |vpiLowConn: @@ -43049,7 +43049,7 @@ design: (work@sky130_fd_sc_hd__dlrbn) |vpiPort: \_port: (Q_N), line:39:5, endln:39:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__dlrbn (work@sky130_fd_sc_hd__dlrbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlrbn.functional.v, line:37:1, endln:64:10 + \_module_inst: work@sky130_fd_sc_hd__dlrbn (work@sky130_fd_sc_hd__dlrbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlrbn.functional.v, line:37:1, endln:64:10 |vpiName:Q_N |vpiDirection:2 |vpiLowConn: @@ -43063,7 +43063,7 @@ design: (work@sky130_fd_sc_hd__dlrbn) |vpiPort: \_port: (RESET_B), line:40:5, endln:40:12 |vpiParent: - \_module: work@sky130_fd_sc_hd__dlrbn (work@sky130_fd_sc_hd__dlrbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlrbn.functional.v, line:37:1, endln:64:10 + \_module_inst: work@sky130_fd_sc_hd__dlrbn (work@sky130_fd_sc_hd__dlrbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlrbn.functional.v, line:37:1, endln:64:10 |vpiName:RESET_B |vpiDirection:1 |vpiLowConn: @@ -43077,7 +43077,7 @@ design: (work@sky130_fd_sc_hd__dlrbn) |vpiPort: \_port: (D), line:41:5, endln:41:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__dlrbn (work@sky130_fd_sc_hd__dlrbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlrbn.functional.v, line:37:1, endln:64:10 + \_module_inst: work@sky130_fd_sc_hd__dlrbn (work@sky130_fd_sc_hd__dlrbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlrbn.functional.v, line:37:1, endln:64:10 |vpiName:D |vpiDirection:1 |vpiLowConn: @@ -43091,7 +43091,7 @@ design: (work@sky130_fd_sc_hd__dlrbn) |vpiPort: \_port: (GATE_N), line:42:5, endln:42:11 |vpiParent: - \_module: work@sky130_fd_sc_hd__dlrbn (work@sky130_fd_sc_hd__dlrbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlrbn.functional.v, line:37:1, endln:64:10 + \_module_inst: work@sky130_fd_sc_hd__dlrbn (work@sky130_fd_sc_hd__dlrbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlrbn.functional.v, line:37:1, endln:64:10 |vpiName:GATE_N |vpiDirection:1 |vpiLowConn: @@ -43105,7 +43105,7 @@ design: (work@sky130_fd_sc_hd__dlrbn) |vpiPrimitive: \_gate: work@not (work@sky130_fd_sc_hd__dlrbn.not0), line:58:48, endln:58:84 |vpiParent: - \_module: work@sky130_fd_sc_hd__dlrbn (work@sky130_fd_sc_hd__dlrbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlrbn.functional.v, line:37:1, endln:64:10 + \_module_inst: work@sky130_fd_sc_hd__dlrbn (work@sky130_fd_sc_hd__dlrbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlrbn.functional.v, line:37:1, endln:64:10 |vpiDefName:work@not |vpiName:not0 |vpiFullName:work@sky130_fd_sc_hd__dlrbn.not0 @@ -43140,7 +43140,7 @@ design: (work@sky130_fd_sc_hd__dlrbn) |vpiPrimitive: \_gate: work@not (work@sky130_fd_sc_hd__dlrbn.not1), line:59:48, endln:59:84 |vpiParent: - \_module: work@sky130_fd_sc_hd__dlrbn (work@sky130_fd_sc_hd__dlrbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlrbn.functional.v, line:37:1, endln:64:10 + \_module_inst: work@sky130_fd_sc_hd__dlrbn (work@sky130_fd_sc_hd__dlrbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlrbn.functional.v, line:37:1, endln:64:10 |vpiDefName:work@not |vpiName:not1 |vpiFullName:work@sky130_fd_sc_hd__dlrbn.not1 @@ -43175,7 +43175,7 @@ design: (work@sky130_fd_sc_hd__dlrbn) |vpiPrimitive: \_udp: work@sky130_fd_sc_hd__udp_dlatch$PR (work@sky130_fd_sc_hd__dlrbn.dlatch0), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlrbn.functional.v, line:60:5, endln:60:74 |vpiParent: - \_module: work@sky130_fd_sc_hd__dlrbn (work@sky130_fd_sc_hd__dlrbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlrbn.functional.v, line:37:1, endln:64:10 + \_module_inst: work@sky130_fd_sc_hd__dlrbn (work@sky130_fd_sc_hd__dlrbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlrbn.functional.v, line:37:1, endln:64:10 |vpiDefName:work@sky130_fd_sc_hd__udp_dlatch$PR |vpiName:dlatch0 |vpiFullName:work@sky130_fd_sc_hd__dlrbn.dlatch0 @@ -43184,7 +43184,7 @@ design: (work@sky130_fd_sc_hd__dlrbn) |vpiPrimitive: \_gate: work@buf (work@sky130_fd_sc_hd__dlrbn.buf0), line:61:48, endln:61:84 |vpiParent: - \_module: work@sky130_fd_sc_hd__dlrbn (work@sky130_fd_sc_hd__dlrbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlrbn.functional.v, line:37:1, endln:64:10 + \_module_inst: work@sky130_fd_sc_hd__dlrbn (work@sky130_fd_sc_hd__dlrbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlrbn.functional.v, line:37:1, endln:64:10 |vpiDefName:work@buf |vpiName:buf0 |vpiFullName:work@sky130_fd_sc_hd__dlrbn.buf0 @@ -43219,7 +43219,7 @@ design: (work@sky130_fd_sc_hd__dlrbn) |vpiPrimitive: \_gate: work@not (work@sky130_fd_sc_hd__dlrbn.not2), line:62:48, endln:62:84 |vpiParent: - \_module: work@sky130_fd_sc_hd__dlrbn (work@sky130_fd_sc_hd__dlrbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlrbn.functional.v, line:37:1, endln:64:10 + \_module_inst: work@sky130_fd_sc_hd__dlrbn (work@sky130_fd_sc_hd__dlrbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlrbn.functional.v, line:37:1, endln:64:10 |vpiDefName:work@not |vpiName:not2 |vpiFullName:work@sky130_fd_sc_hd__dlrbn.not2 @@ -43336,7 +43336,7 @@ design: (work@sky130_fd_sc_hd__lpflow_inputisolatch) |vpiSize:2 |STRING:1 x : 1 : 1 |uhdmallModules: -\_module: work@sky130_fd_sc_hd__lpflow_inputisolatch (work@sky130_fd_sc_hd__lpflow_inputisolatch), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_inputisolatch.functional.v, line:36:1, endln:54:10 +\_module_inst: work@sky130_fd_sc_hd__lpflow_inputisolatch (work@sky130_fd_sc_hd__lpflow_inputisolatch), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_inputisolatch.functional.v, line:36:1, endln:54:10 |vpiParent: \_design: (work@sky130_fd_sc_hd__lpflow_inputisolatch) |vpiFullName:work@sky130_fd_sc_hd__lpflow_inputisolatch @@ -43344,32 +43344,32 @@ design: (work@sky130_fd_sc_hd__lpflow_inputisolatch) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__lpflow_inputisolatch.buf_Q), line:48:10, endln:48:15 |vpiParent: - \_module: work@sky130_fd_sc_hd__lpflow_inputisolatch (work@sky130_fd_sc_hd__lpflow_inputisolatch), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_inputisolatch.functional.v, line:36:1, endln:54:10 + \_module_inst: work@sky130_fd_sc_hd__lpflow_inputisolatch (work@sky130_fd_sc_hd__lpflow_inputisolatch), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_inputisolatch.functional.v, line:36:1, endln:54:10 |vpiName:buf_Q |vpiFullName:work@sky130_fd_sc_hd__lpflow_inputisolatch.buf_Q |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__lpflow_inputisolatch.Q), line:37:5, endln:37:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__lpflow_inputisolatch (work@sky130_fd_sc_hd__lpflow_inputisolatch), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_inputisolatch.functional.v, line:36:1, endln:54:10 + \_module_inst: work@sky130_fd_sc_hd__lpflow_inputisolatch (work@sky130_fd_sc_hd__lpflow_inputisolatch), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_inputisolatch.functional.v, line:36:1, endln:54:10 |vpiName:Q |vpiFullName:work@sky130_fd_sc_hd__lpflow_inputisolatch.Q |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__lpflow_inputisolatch.D), line:38:5, endln:38:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__lpflow_inputisolatch (work@sky130_fd_sc_hd__lpflow_inputisolatch), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_inputisolatch.functional.v, line:36:1, endln:54:10 + \_module_inst: work@sky130_fd_sc_hd__lpflow_inputisolatch (work@sky130_fd_sc_hd__lpflow_inputisolatch), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_inputisolatch.functional.v, line:36:1, endln:54:10 |vpiName:D |vpiFullName:work@sky130_fd_sc_hd__lpflow_inputisolatch.D |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__lpflow_inputisolatch.SLEEP_B), line:39:5, endln:39:12 |vpiParent: - \_module: work@sky130_fd_sc_hd__lpflow_inputisolatch (work@sky130_fd_sc_hd__lpflow_inputisolatch), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_inputisolatch.functional.v, line:36:1, endln:54:10 + \_module_inst: work@sky130_fd_sc_hd__lpflow_inputisolatch (work@sky130_fd_sc_hd__lpflow_inputisolatch), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_inputisolatch.functional.v, line:36:1, endln:54:10 |vpiName:SLEEP_B |vpiFullName:work@sky130_fd_sc_hd__lpflow_inputisolatch.SLEEP_B |vpiPort: \_port: (Q), line:37:5, endln:37:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__lpflow_inputisolatch (work@sky130_fd_sc_hd__lpflow_inputisolatch), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_inputisolatch.functional.v, line:36:1, endln:54:10 + \_module_inst: work@sky130_fd_sc_hd__lpflow_inputisolatch (work@sky130_fd_sc_hd__lpflow_inputisolatch), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_inputisolatch.functional.v, line:36:1, endln:54:10 |vpiName:Q |vpiDirection:2 |vpiLowConn: @@ -43381,7 +43381,7 @@ design: (work@sky130_fd_sc_hd__lpflow_inputisolatch) |vpiPort: \_port: (D), line:38:5, endln:38:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__lpflow_inputisolatch (work@sky130_fd_sc_hd__lpflow_inputisolatch), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_inputisolatch.functional.v, line:36:1, endln:54:10 + \_module_inst: work@sky130_fd_sc_hd__lpflow_inputisolatch (work@sky130_fd_sc_hd__lpflow_inputisolatch), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_inputisolatch.functional.v, line:36:1, endln:54:10 |vpiName:D |vpiDirection:1 |vpiLowConn: @@ -43393,7 +43393,7 @@ design: (work@sky130_fd_sc_hd__lpflow_inputisolatch) |vpiPort: \_port: (SLEEP_B), line:39:5, endln:39:12 |vpiParent: - \_module: work@sky130_fd_sc_hd__lpflow_inputisolatch (work@sky130_fd_sc_hd__lpflow_inputisolatch), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_inputisolatch.functional.v, line:36:1, endln:54:10 + \_module_inst: work@sky130_fd_sc_hd__lpflow_inputisolatch (work@sky130_fd_sc_hd__lpflow_inputisolatch), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_inputisolatch.functional.v, line:36:1, endln:54:10 |vpiName:SLEEP_B |vpiDirection:1 |vpiLowConn: @@ -43403,14 +43403,14 @@ design: (work@sky130_fd_sc_hd__lpflow_inputisolatch) |vpiTypedef: \_logic_typespec: , line:45:12, endln:45:12 |uhdmtopModules: -\_module: work@sky130_fd_sc_hd__lpflow_inputisolatch (work@sky130_fd_sc_hd__lpflow_inputisolatch), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_inputisolatch.functional.v, line:36:1, endln:54:10 +\_module_inst: work@sky130_fd_sc_hd__lpflow_inputisolatch (work@sky130_fd_sc_hd__lpflow_inputisolatch), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_inputisolatch.functional.v, line:36:1, endln:54:10 |vpiName:work@sky130_fd_sc_hd__lpflow_inputisolatch |vpiDefName:work@sky130_fd_sc_hd__lpflow_inputisolatch |vpiTop:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__lpflow_inputisolatch.buf_Q), line:48:10, endln:48:15 |vpiParent: - \_module: work@sky130_fd_sc_hd__lpflow_inputisolatch (work@sky130_fd_sc_hd__lpflow_inputisolatch), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_inputisolatch.functional.v, line:36:1, endln:54:10 + \_module_inst: work@sky130_fd_sc_hd__lpflow_inputisolatch (work@sky130_fd_sc_hd__lpflow_inputisolatch), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_inputisolatch.functional.v, line:36:1, endln:54:10 |vpiTypespec: \_logic_typespec: , line:48:5, endln:48:9 |vpiName:buf_Q @@ -43419,7 +43419,7 @@ design: (work@sky130_fd_sc_hd__lpflow_inputisolatch) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__lpflow_inputisolatch.Q), line:37:5, endln:37:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__lpflow_inputisolatch (work@sky130_fd_sc_hd__lpflow_inputisolatch), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_inputisolatch.functional.v, line:36:1, endln:54:10 + \_module_inst: work@sky130_fd_sc_hd__lpflow_inputisolatch (work@sky130_fd_sc_hd__lpflow_inputisolatch), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_inputisolatch.functional.v, line:36:1, endln:54:10 |vpiTypespec: \_logic_typespec: , line:43:12, endln:43:12 |vpiName:Q @@ -43427,7 +43427,7 @@ design: (work@sky130_fd_sc_hd__lpflow_inputisolatch) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__lpflow_inputisolatch.D), line:38:5, endln:38:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__lpflow_inputisolatch (work@sky130_fd_sc_hd__lpflow_inputisolatch), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_inputisolatch.functional.v, line:36:1, endln:54:10 + \_module_inst: work@sky130_fd_sc_hd__lpflow_inputisolatch (work@sky130_fd_sc_hd__lpflow_inputisolatch), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_inputisolatch.functional.v, line:36:1, endln:54:10 |vpiTypespec: \_logic_typespec: , line:44:12, endln:44:12 |vpiName:D @@ -43435,7 +43435,7 @@ design: (work@sky130_fd_sc_hd__lpflow_inputisolatch) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__lpflow_inputisolatch.SLEEP_B), line:39:5, endln:39:12 |vpiParent: - \_module: work@sky130_fd_sc_hd__lpflow_inputisolatch (work@sky130_fd_sc_hd__lpflow_inputisolatch), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_inputisolatch.functional.v, line:36:1, endln:54:10 + \_module_inst: work@sky130_fd_sc_hd__lpflow_inputisolatch (work@sky130_fd_sc_hd__lpflow_inputisolatch), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_inputisolatch.functional.v, line:36:1, endln:54:10 |vpiTypespec: \_logic_typespec: , line:45:12, endln:45:12 |vpiName:SLEEP_B @@ -43444,7 +43444,7 @@ design: (work@sky130_fd_sc_hd__lpflow_inputisolatch) |vpiPort: \_port: (Q), line:37:5, endln:37:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__lpflow_inputisolatch (work@sky130_fd_sc_hd__lpflow_inputisolatch), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_inputisolatch.functional.v, line:36:1, endln:54:10 + \_module_inst: work@sky130_fd_sc_hd__lpflow_inputisolatch (work@sky130_fd_sc_hd__lpflow_inputisolatch), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_inputisolatch.functional.v, line:36:1, endln:54:10 |vpiName:Q |vpiDirection:2 |vpiLowConn: @@ -43458,7 +43458,7 @@ design: (work@sky130_fd_sc_hd__lpflow_inputisolatch) |vpiPort: \_port: (D), line:38:5, endln:38:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__lpflow_inputisolatch (work@sky130_fd_sc_hd__lpflow_inputisolatch), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_inputisolatch.functional.v, line:36:1, endln:54:10 + \_module_inst: work@sky130_fd_sc_hd__lpflow_inputisolatch (work@sky130_fd_sc_hd__lpflow_inputisolatch), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_inputisolatch.functional.v, line:36:1, endln:54:10 |vpiName:D |vpiDirection:1 |vpiLowConn: @@ -43472,7 +43472,7 @@ design: (work@sky130_fd_sc_hd__lpflow_inputisolatch) |vpiPort: \_port: (SLEEP_B), line:39:5, endln:39:12 |vpiParent: - \_module: work@sky130_fd_sc_hd__lpflow_inputisolatch (work@sky130_fd_sc_hd__lpflow_inputisolatch), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_inputisolatch.functional.v, line:36:1, endln:54:10 + \_module_inst: work@sky130_fd_sc_hd__lpflow_inputisolatch (work@sky130_fd_sc_hd__lpflow_inputisolatch), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_inputisolatch.functional.v, line:36:1, endln:54:10 |vpiName:SLEEP_B |vpiDirection:1 |vpiLowConn: @@ -43486,7 +43486,7 @@ design: (work@sky130_fd_sc_hd__lpflow_inputisolatch) |vpiPrimitive: \_udp: work@sky130_fd_sc_hd__udp_dlatch$lP (work@sky130_fd_sc_hd__lpflow_inputisolatch.dlatch0), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_inputisolatch.functional.v, line:51:5, endln:51:70 |vpiParent: - \_module: work@sky130_fd_sc_hd__lpflow_inputisolatch (work@sky130_fd_sc_hd__lpflow_inputisolatch), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_inputisolatch.functional.v, line:36:1, endln:54:10 + \_module_inst: work@sky130_fd_sc_hd__lpflow_inputisolatch (work@sky130_fd_sc_hd__lpflow_inputisolatch), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_inputisolatch.functional.v, line:36:1, endln:54:10 |vpiDefName:work@sky130_fd_sc_hd__udp_dlatch$lP |vpiName:dlatch0 |vpiFullName:work@sky130_fd_sc_hd__lpflow_inputisolatch.dlatch0 @@ -43495,7 +43495,7 @@ design: (work@sky130_fd_sc_hd__lpflow_inputisolatch) |vpiPrimitive: \_gate: work@buf (work@sky130_fd_sc_hd__lpflow_inputisolatch.buf0), line:52:36, endln:52:69 |vpiParent: - \_module: work@sky130_fd_sc_hd__lpflow_inputisolatch (work@sky130_fd_sc_hd__lpflow_inputisolatch), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_inputisolatch.functional.v, line:36:1, endln:54:10 + \_module_inst: work@sky130_fd_sc_hd__lpflow_inputisolatch (work@sky130_fd_sc_hd__lpflow_inputisolatch), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_inputisolatch.functional.v, line:36:1, endln:54:10 |vpiDefName:work@buf |vpiName:buf0 |vpiFullName:work@sky130_fd_sc_hd__lpflow_inputisolatch.buf0 @@ -43538,7 +43538,7 @@ Processing: -cd cells/cells -DUNIT_DELAY -writepp -parse -nocache -nobuiltin -no design: (work@sky130_fd_sc_hd__o221ai) |vpiName:work@sky130_fd_sc_hd__o221ai |uhdmallModules: -\_module: work@sky130_fd_sc_hd__o221ai (work@sky130_fd_sc_hd__o221ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o221ai.functional.v, line:35:1, endln:63:10 +\_module_inst: work@sky130_fd_sc_hd__o221ai (work@sky130_fd_sc_hd__o221ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o221ai.functional.v, line:35:1, endln:63:10 |vpiParent: \_design: (work@sky130_fd_sc_hd__o221ai) |vpiFullName:work@sky130_fd_sc_hd__o221ai @@ -43546,64 +43546,64 @@ design: (work@sky130_fd_sc_hd__o221ai) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o221ai.or0_out), line:53:10, endln:53:17 |vpiParent: - \_module: work@sky130_fd_sc_hd__o221ai (work@sky130_fd_sc_hd__o221ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o221ai.functional.v, line:35:1, endln:63:10 + \_module_inst: work@sky130_fd_sc_hd__o221ai (work@sky130_fd_sc_hd__o221ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o221ai.functional.v, line:35:1, endln:63:10 |vpiName:or0_out |vpiFullName:work@sky130_fd_sc_hd__o221ai.or0_out |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o221ai.or1_out), line:54:10, endln:54:17 |vpiParent: - \_module: work@sky130_fd_sc_hd__o221ai (work@sky130_fd_sc_hd__o221ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o221ai.functional.v, line:35:1, endln:63:10 + \_module_inst: work@sky130_fd_sc_hd__o221ai (work@sky130_fd_sc_hd__o221ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o221ai.functional.v, line:35:1, endln:63:10 |vpiName:or1_out |vpiFullName:work@sky130_fd_sc_hd__o221ai.or1_out |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o221ai.nand0_out_Y), line:55:10, endln:55:21 |vpiParent: - \_module: work@sky130_fd_sc_hd__o221ai (work@sky130_fd_sc_hd__o221ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o221ai.functional.v, line:35:1, endln:63:10 + \_module_inst: work@sky130_fd_sc_hd__o221ai (work@sky130_fd_sc_hd__o221ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o221ai.functional.v, line:35:1, endln:63:10 |vpiName:nand0_out_Y |vpiFullName:work@sky130_fd_sc_hd__o221ai.nand0_out_Y |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o221ai.Y), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__o221ai (work@sky130_fd_sc_hd__o221ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o221ai.functional.v, line:35:1, endln:63:10 + \_module_inst: work@sky130_fd_sc_hd__o221ai (work@sky130_fd_sc_hd__o221ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o221ai.functional.v, line:35:1, endln:63:10 |vpiName:Y |vpiFullName:work@sky130_fd_sc_hd__o221ai.Y |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o221ai.A1), line:37:5, endln:37:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o221ai (work@sky130_fd_sc_hd__o221ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o221ai.functional.v, line:35:1, endln:63:10 + \_module_inst: work@sky130_fd_sc_hd__o221ai (work@sky130_fd_sc_hd__o221ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o221ai.functional.v, line:35:1, endln:63:10 |vpiName:A1 |vpiFullName:work@sky130_fd_sc_hd__o221ai.A1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o221ai.A2), line:38:5, endln:38:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o221ai (work@sky130_fd_sc_hd__o221ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o221ai.functional.v, line:35:1, endln:63:10 + \_module_inst: work@sky130_fd_sc_hd__o221ai (work@sky130_fd_sc_hd__o221ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o221ai.functional.v, line:35:1, endln:63:10 |vpiName:A2 |vpiFullName:work@sky130_fd_sc_hd__o221ai.A2 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o221ai.B1), line:39:5, endln:39:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o221ai (work@sky130_fd_sc_hd__o221ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o221ai.functional.v, line:35:1, endln:63:10 + \_module_inst: work@sky130_fd_sc_hd__o221ai (work@sky130_fd_sc_hd__o221ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o221ai.functional.v, line:35:1, endln:63:10 |vpiName:B1 |vpiFullName:work@sky130_fd_sc_hd__o221ai.B1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o221ai.B2), line:40:5, endln:40:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o221ai (work@sky130_fd_sc_hd__o221ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o221ai.functional.v, line:35:1, endln:63:10 + \_module_inst: work@sky130_fd_sc_hd__o221ai (work@sky130_fd_sc_hd__o221ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o221ai.functional.v, line:35:1, endln:63:10 |vpiName:B2 |vpiFullName:work@sky130_fd_sc_hd__o221ai.B2 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o221ai.C1), line:41:5, endln:41:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o221ai (work@sky130_fd_sc_hd__o221ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o221ai.functional.v, line:35:1, endln:63:10 + \_module_inst: work@sky130_fd_sc_hd__o221ai (work@sky130_fd_sc_hd__o221ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o221ai.functional.v, line:35:1, endln:63:10 |vpiName:C1 |vpiFullName:work@sky130_fd_sc_hd__o221ai.C1 |vpiPort: \_port: (Y), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__o221ai (work@sky130_fd_sc_hd__o221ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o221ai.functional.v, line:35:1, endln:63:10 + \_module_inst: work@sky130_fd_sc_hd__o221ai (work@sky130_fd_sc_hd__o221ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o221ai.functional.v, line:35:1, endln:63:10 |vpiName:Y |vpiDirection:2 |vpiLowConn: @@ -43615,7 +43615,7 @@ design: (work@sky130_fd_sc_hd__o221ai) |vpiPort: \_port: (A1), line:37:5, endln:37:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o221ai (work@sky130_fd_sc_hd__o221ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o221ai.functional.v, line:35:1, endln:63:10 + \_module_inst: work@sky130_fd_sc_hd__o221ai (work@sky130_fd_sc_hd__o221ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o221ai.functional.v, line:35:1, endln:63:10 |vpiName:A1 |vpiDirection:1 |vpiLowConn: @@ -43627,7 +43627,7 @@ design: (work@sky130_fd_sc_hd__o221ai) |vpiPort: \_port: (A2), line:38:5, endln:38:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o221ai (work@sky130_fd_sc_hd__o221ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o221ai.functional.v, line:35:1, endln:63:10 + \_module_inst: work@sky130_fd_sc_hd__o221ai (work@sky130_fd_sc_hd__o221ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o221ai.functional.v, line:35:1, endln:63:10 |vpiName:A2 |vpiDirection:1 |vpiLowConn: @@ -43639,7 +43639,7 @@ design: (work@sky130_fd_sc_hd__o221ai) |vpiPort: \_port: (B1), line:39:5, endln:39:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o221ai (work@sky130_fd_sc_hd__o221ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o221ai.functional.v, line:35:1, endln:63:10 + \_module_inst: work@sky130_fd_sc_hd__o221ai (work@sky130_fd_sc_hd__o221ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o221ai.functional.v, line:35:1, endln:63:10 |vpiName:B1 |vpiDirection:1 |vpiLowConn: @@ -43651,7 +43651,7 @@ design: (work@sky130_fd_sc_hd__o221ai) |vpiPort: \_port: (B2), line:40:5, endln:40:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o221ai (work@sky130_fd_sc_hd__o221ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o221ai.functional.v, line:35:1, endln:63:10 + \_module_inst: work@sky130_fd_sc_hd__o221ai (work@sky130_fd_sc_hd__o221ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o221ai.functional.v, line:35:1, endln:63:10 |vpiName:B2 |vpiDirection:1 |vpiLowConn: @@ -43663,7 +43663,7 @@ design: (work@sky130_fd_sc_hd__o221ai) |vpiPort: \_port: (C1), line:41:5, endln:41:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o221ai (work@sky130_fd_sc_hd__o221ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o221ai.functional.v, line:35:1, endln:63:10 + \_module_inst: work@sky130_fd_sc_hd__o221ai (work@sky130_fd_sc_hd__o221ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o221ai.functional.v, line:35:1, endln:63:10 |vpiName:C1 |vpiDirection:1 |vpiLowConn: @@ -43673,14 +43673,14 @@ design: (work@sky130_fd_sc_hd__o221ai) |vpiTypedef: \_logic_typespec: , line:50:12, endln:50:12 |uhdmtopModules: -\_module: work@sky130_fd_sc_hd__o221ai (work@sky130_fd_sc_hd__o221ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o221ai.functional.v, line:35:1, endln:63:10 +\_module_inst: work@sky130_fd_sc_hd__o221ai (work@sky130_fd_sc_hd__o221ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o221ai.functional.v, line:35:1, endln:63:10 |vpiName:work@sky130_fd_sc_hd__o221ai |vpiDefName:work@sky130_fd_sc_hd__o221ai |vpiTop:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o221ai.or0_out), line:53:10, endln:53:17 |vpiParent: - \_module: work@sky130_fd_sc_hd__o221ai (work@sky130_fd_sc_hd__o221ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o221ai.functional.v, line:35:1, endln:63:10 + \_module_inst: work@sky130_fd_sc_hd__o221ai (work@sky130_fd_sc_hd__o221ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o221ai.functional.v, line:35:1, endln:63:10 |vpiTypespec: \_logic_typespec: , line:53:5, endln:53:9 |vpiName:or0_out @@ -43689,7 +43689,7 @@ design: (work@sky130_fd_sc_hd__o221ai) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o221ai.or1_out), line:54:10, endln:54:17 |vpiParent: - \_module: work@sky130_fd_sc_hd__o221ai (work@sky130_fd_sc_hd__o221ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o221ai.functional.v, line:35:1, endln:63:10 + \_module_inst: work@sky130_fd_sc_hd__o221ai (work@sky130_fd_sc_hd__o221ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o221ai.functional.v, line:35:1, endln:63:10 |vpiTypespec: \_logic_typespec: , line:54:5, endln:54:9 |vpiName:or1_out @@ -43698,7 +43698,7 @@ design: (work@sky130_fd_sc_hd__o221ai) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o221ai.nand0_out_Y), line:55:10, endln:55:21 |vpiParent: - \_module: work@sky130_fd_sc_hd__o221ai (work@sky130_fd_sc_hd__o221ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o221ai.functional.v, line:35:1, endln:63:10 + \_module_inst: work@sky130_fd_sc_hd__o221ai (work@sky130_fd_sc_hd__o221ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o221ai.functional.v, line:35:1, endln:63:10 |vpiTypespec: \_logic_typespec: , line:55:5, endln:55:9 |vpiName:nand0_out_Y @@ -43707,7 +43707,7 @@ design: (work@sky130_fd_sc_hd__o221ai) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o221ai.Y), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__o221ai (work@sky130_fd_sc_hd__o221ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o221ai.functional.v, line:35:1, endln:63:10 + \_module_inst: work@sky130_fd_sc_hd__o221ai (work@sky130_fd_sc_hd__o221ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o221ai.functional.v, line:35:1, endln:63:10 |vpiTypespec: \_logic_typespec: , line:45:12, endln:45:12 |vpiName:Y @@ -43715,7 +43715,7 @@ design: (work@sky130_fd_sc_hd__o221ai) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o221ai.A1), line:37:5, endln:37:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o221ai (work@sky130_fd_sc_hd__o221ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o221ai.functional.v, line:35:1, endln:63:10 + \_module_inst: work@sky130_fd_sc_hd__o221ai (work@sky130_fd_sc_hd__o221ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o221ai.functional.v, line:35:1, endln:63:10 |vpiTypespec: \_logic_typespec: , line:46:12, endln:46:12 |vpiName:A1 @@ -43723,7 +43723,7 @@ design: (work@sky130_fd_sc_hd__o221ai) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o221ai.A2), line:38:5, endln:38:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o221ai (work@sky130_fd_sc_hd__o221ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o221ai.functional.v, line:35:1, endln:63:10 + \_module_inst: work@sky130_fd_sc_hd__o221ai (work@sky130_fd_sc_hd__o221ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o221ai.functional.v, line:35:1, endln:63:10 |vpiTypespec: \_logic_typespec: , line:47:12, endln:47:12 |vpiName:A2 @@ -43731,7 +43731,7 @@ design: (work@sky130_fd_sc_hd__o221ai) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o221ai.B1), line:39:5, endln:39:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o221ai (work@sky130_fd_sc_hd__o221ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o221ai.functional.v, line:35:1, endln:63:10 + \_module_inst: work@sky130_fd_sc_hd__o221ai (work@sky130_fd_sc_hd__o221ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o221ai.functional.v, line:35:1, endln:63:10 |vpiTypespec: \_logic_typespec: , line:48:12, endln:48:12 |vpiName:B1 @@ -43739,7 +43739,7 @@ design: (work@sky130_fd_sc_hd__o221ai) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o221ai.B2), line:40:5, endln:40:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o221ai (work@sky130_fd_sc_hd__o221ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o221ai.functional.v, line:35:1, endln:63:10 + \_module_inst: work@sky130_fd_sc_hd__o221ai (work@sky130_fd_sc_hd__o221ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o221ai.functional.v, line:35:1, endln:63:10 |vpiTypespec: \_logic_typespec: , line:49:12, endln:49:12 |vpiName:B2 @@ -43747,7 +43747,7 @@ design: (work@sky130_fd_sc_hd__o221ai) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o221ai.C1), line:41:5, endln:41:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o221ai (work@sky130_fd_sc_hd__o221ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o221ai.functional.v, line:35:1, endln:63:10 + \_module_inst: work@sky130_fd_sc_hd__o221ai (work@sky130_fd_sc_hd__o221ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o221ai.functional.v, line:35:1, endln:63:10 |vpiTypespec: \_logic_typespec: , line:50:12, endln:50:12 |vpiName:C1 @@ -43756,7 +43756,7 @@ design: (work@sky130_fd_sc_hd__o221ai) |vpiPort: \_port: (Y), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__o221ai (work@sky130_fd_sc_hd__o221ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o221ai.functional.v, line:35:1, endln:63:10 + \_module_inst: work@sky130_fd_sc_hd__o221ai (work@sky130_fd_sc_hd__o221ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o221ai.functional.v, line:35:1, endln:63:10 |vpiName:Y |vpiDirection:2 |vpiLowConn: @@ -43770,7 +43770,7 @@ design: (work@sky130_fd_sc_hd__o221ai) |vpiPort: \_port: (A1), line:37:5, endln:37:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o221ai (work@sky130_fd_sc_hd__o221ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o221ai.functional.v, line:35:1, endln:63:10 + \_module_inst: work@sky130_fd_sc_hd__o221ai (work@sky130_fd_sc_hd__o221ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o221ai.functional.v, line:35:1, endln:63:10 |vpiName:A1 |vpiDirection:1 |vpiLowConn: @@ -43784,7 +43784,7 @@ design: (work@sky130_fd_sc_hd__o221ai) |vpiPort: \_port: (A2), line:38:5, endln:38:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o221ai (work@sky130_fd_sc_hd__o221ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o221ai.functional.v, line:35:1, endln:63:10 + \_module_inst: work@sky130_fd_sc_hd__o221ai (work@sky130_fd_sc_hd__o221ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o221ai.functional.v, line:35:1, endln:63:10 |vpiName:A2 |vpiDirection:1 |vpiLowConn: @@ -43798,7 +43798,7 @@ design: (work@sky130_fd_sc_hd__o221ai) |vpiPort: \_port: (B1), line:39:5, endln:39:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o221ai (work@sky130_fd_sc_hd__o221ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o221ai.functional.v, line:35:1, endln:63:10 + \_module_inst: work@sky130_fd_sc_hd__o221ai (work@sky130_fd_sc_hd__o221ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o221ai.functional.v, line:35:1, endln:63:10 |vpiName:B1 |vpiDirection:1 |vpiLowConn: @@ -43812,7 +43812,7 @@ design: (work@sky130_fd_sc_hd__o221ai) |vpiPort: \_port: (B2), line:40:5, endln:40:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o221ai (work@sky130_fd_sc_hd__o221ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o221ai.functional.v, line:35:1, endln:63:10 + \_module_inst: work@sky130_fd_sc_hd__o221ai (work@sky130_fd_sc_hd__o221ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o221ai.functional.v, line:35:1, endln:63:10 |vpiName:B2 |vpiDirection:1 |vpiLowConn: @@ -43826,7 +43826,7 @@ design: (work@sky130_fd_sc_hd__o221ai) |vpiPort: \_port: (C1), line:41:5, endln:41:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o221ai (work@sky130_fd_sc_hd__o221ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o221ai.functional.v, line:35:1, endln:63:10 + \_module_inst: work@sky130_fd_sc_hd__o221ai (work@sky130_fd_sc_hd__o221ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o221ai.functional.v, line:35:1, endln:63:10 |vpiName:C1 |vpiDirection:1 |vpiLowConn: @@ -43840,7 +43840,7 @@ design: (work@sky130_fd_sc_hd__o221ai) |vpiPrimitive: \_gate: work@or (work@sky130_fd_sc_hd__o221ai.or0), line:58:10, endln:58:51 |vpiParent: - \_module: work@sky130_fd_sc_hd__o221ai (work@sky130_fd_sc_hd__o221ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o221ai.functional.v, line:35:1, endln:63:10 + \_module_inst: work@sky130_fd_sc_hd__o221ai (work@sky130_fd_sc_hd__o221ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o221ai.functional.v, line:35:1, endln:63:10 |vpiDefName:work@or |vpiName:or0 |vpiFullName:work@sky130_fd_sc_hd__o221ai.or0 @@ -43889,7 +43889,7 @@ design: (work@sky130_fd_sc_hd__o221ai) |vpiPrimitive: \_gate: work@or (work@sky130_fd_sc_hd__o221ai.or1), line:59:10, endln:59:51 |vpiParent: - \_module: work@sky130_fd_sc_hd__o221ai (work@sky130_fd_sc_hd__o221ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o221ai.functional.v, line:35:1, endln:63:10 + \_module_inst: work@sky130_fd_sc_hd__o221ai (work@sky130_fd_sc_hd__o221ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o221ai.functional.v, line:35:1, endln:63:10 |vpiDefName:work@or |vpiName:or1 |vpiFullName:work@sky130_fd_sc_hd__o221ai.or1 @@ -43938,7 +43938,7 @@ design: (work@sky130_fd_sc_hd__o221ai) |vpiPrimitive: \_gate: work@nand (work@sky130_fd_sc_hd__o221ai.nand0), line:60:10, endln:60:51 |vpiParent: - \_module: work@sky130_fd_sc_hd__o221ai (work@sky130_fd_sc_hd__o221ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o221ai.functional.v, line:35:1, endln:63:10 + \_module_inst: work@sky130_fd_sc_hd__o221ai (work@sky130_fd_sc_hd__o221ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o221ai.functional.v, line:35:1, endln:63:10 |vpiDefName:work@nand |vpiName:nand0 |vpiFullName:work@sky130_fd_sc_hd__o221ai.nand0 @@ -44001,7 +44001,7 @@ design: (work@sky130_fd_sc_hd__o221ai) |vpiPrimitive: \_gate: work@buf (work@sky130_fd_sc_hd__o221ai.buf0), line:61:10, endln:61:51 |vpiParent: - \_module: work@sky130_fd_sc_hd__o221ai (work@sky130_fd_sc_hd__o221ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o221ai.functional.v, line:35:1, endln:63:10 + \_module_inst: work@sky130_fd_sc_hd__o221ai (work@sky130_fd_sc_hd__o221ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o221ai.functional.v, line:35:1, endln:63:10 |vpiDefName:work@buf |vpiName:buf0 |vpiFullName:work@sky130_fd_sc_hd__o221ai.buf0 @@ -44044,7 +44044,7 @@ Processing: -cd cells/cells -DUNIT_DELAY -writepp -parse -nocache -nobuiltin -no design: (work@sky130_fd_sc_hd__o2111a) |vpiName:work@sky130_fd_sc_hd__o2111a |uhdmallModules: -\_module: work@sky130_fd_sc_hd__o2111a (work@sky130_fd_sc_hd__o2111a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o2111a.functional.v, line:35:1, endln:61:10 +\_module_inst: work@sky130_fd_sc_hd__o2111a (work@sky130_fd_sc_hd__o2111a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o2111a.functional.v, line:35:1, endln:61:10 |vpiParent: \_design: (work@sky130_fd_sc_hd__o2111a) |vpiFullName:work@sky130_fd_sc_hd__o2111a @@ -44052,57 +44052,57 @@ design: (work@sky130_fd_sc_hd__o2111a) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o2111a.or0_out), line:53:10, endln:53:17 |vpiParent: - \_module: work@sky130_fd_sc_hd__o2111a (work@sky130_fd_sc_hd__o2111a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o2111a.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o2111a (work@sky130_fd_sc_hd__o2111a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o2111a.functional.v, line:35:1, endln:61:10 |vpiName:or0_out |vpiFullName:work@sky130_fd_sc_hd__o2111a.or0_out |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o2111a.and0_out_X), line:54:10, endln:54:20 |vpiParent: - \_module: work@sky130_fd_sc_hd__o2111a (work@sky130_fd_sc_hd__o2111a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o2111a.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o2111a (work@sky130_fd_sc_hd__o2111a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o2111a.functional.v, line:35:1, endln:61:10 |vpiName:and0_out_X |vpiFullName:work@sky130_fd_sc_hd__o2111a.and0_out_X |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o2111a.X), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__o2111a (work@sky130_fd_sc_hd__o2111a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o2111a.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o2111a (work@sky130_fd_sc_hd__o2111a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o2111a.functional.v, line:35:1, endln:61:10 |vpiName:X |vpiFullName:work@sky130_fd_sc_hd__o2111a.X |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o2111a.A1), line:37:5, endln:37:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o2111a (work@sky130_fd_sc_hd__o2111a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o2111a.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o2111a (work@sky130_fd_sc_hd__o2111a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o2111a.functional.v, line:35:1, endln:61:10 |vpiName:A1 |vpiFullName:work@sky130_fd_sc_hd__o2111a.A1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o2111a.A2), line:38:5, endln:38:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o2111a (work@sky130_fd_sc_hd__o2111a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o2111a.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o2111a (work@sky130_fd_sc_hd__o2111a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o2111a.functional.v, line:35:1, endln:61:10 |vpiName:A2 |vpiFullName:work@sky130_fd_sc_hd__o2111a.A2 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o2111a.B1), line:39:5, endln:39:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o2111a (work@sky130_fd_sc_hd__o2111a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o2111a.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o2111a (work@sky130_fd_sc_hd__o2111a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o2111a.functional.v, line:35:1, endln:61:10 |vpiName:B1 |vpiFullName:work@sky130_fd_sc_hd__o2111a.B1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o2111a.C1), line:40:5, endln:40:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o2111a (work@sky130_fd_sc_hd__o2111a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o2111a.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o2111a (work@sky130_fd_sc_hd__o2111a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o2111a.functional.v, line:35:1, endln:61:10 |vpiName:C1 |vpiFullName:work@sky130_fd_sc_hd__o2111a.C1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o2111a.D1), line:41:5, endln:41:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o2111a (work@sky130_fd_sc_hd__o2111a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o2111a.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o2111a (work@sky130_fd_sc_hd__o2111a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o2111a.functional.v, line:35:1, endln:61:10 |vpiName:D1 |vpiFullName:work@sky130_fd_sc_hd__o2111a.D1 |vpiPort: \_port: (X), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__o2111a (work@sky130_fd_sc_hd__o2111a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o2111a.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o2111a (work@sky130_fd_sc_hd__o2111a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o2111a.functional.v, line:35:1, endln:61:10 |vpiName:X |vpiDirection:2 |vpiLowConn: @@ -44114,7 +44114,7 @@ design: (work@sky130_fd_sc_hd__o2111a) |vpiPort: \_port: (A1), line:37:5, endln:37:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o2111a (work@sky130_fd_sc_hd__o2111a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o2111a.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o2111a (work@sky130_fd_sc_hd__o2111a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o2111a.functional.v, line:35:1, endln:61:10 |vpiName:A1 |vpiDirection:1 |vpiLowConn: @@ -44126,7 +44126,7 @@ design: (work@sky130_fd_sc_hd__o2111a) |vpiPort: \_port: (A2), line:38:5, endln:38:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o2111a (work@sky130_fd_sc_hd__o2111a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o2111a.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o2111a (work@sky130_fd_sc_hd__o2111a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o2111a.functional.v, line:35:1, endln:61:10 |vpiName:A2 |vpiDirection:1 |vpiLowConn: @@ -44138,7 +44138,7 @@ design: (work@sky130_fd_sc_hd__o2111a) |vpiPort: \_port: (B1), line:39:5, endln:39:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o2111a (work@sky130_fd_sc_hd__o2111a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o2111a.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o2111a (work@sky130_fd_sc_hd__o2111a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o2111a.functional.v, line:35:1, endln:61:10 |vpiName:B1 |vpiDirection:1 |vpiLowConn: @@ -44150,7 +44150,7 @@ design: (work@sky130_fd_sc_hd__o2111a) |vpiPort: \_port: (C1), line:40:5, endln:40:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o2111a (work@sky130_fd_sc_hd__o2111a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o2111a.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o2111a (work@sky130_fd_sc_hd__o2111a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o2111a.functional.v, line:35:1, endln:61:10 |vpiName:C1 |vpiDirection:1 |vpiLowConn: @@ -44162,7 +44162,7 @@ design: (work@sky130_fd_sc_hd__o2111a) |vpiPort: \_port: (D1), line:41:5, endln:41:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o2111a (work@sky130_fd_sc_hd__o2111a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o2111a.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o2111a (work@sky130_fd_sc_hd__o2111a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o2111a.functional.v, line:35:1, endln:61:10 |vpiName:D1 |vpiDirection:1 |vpiLowConn: @@ -44172,14 +44172,14 @@ design: (work@sky130_fd_sc_hd__o2111a) |vpiTypedef: \_logic_typespec: , line:50:12, endln:50:12 |uhdmtopModules: -\_module: work@sky130_fd_sc_hd__o2111a (work@sky130_fd_sc_hd__o2111a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o2111a.functional.v, line:35:1, endln:61:10 +\_module_inst: work@sky130_fd_sc_hd__o2111a (work@sky130_fd_sc_hd__o2111a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o2111a.functional.v, line:35:1, endln:61:10 |vpiName:work@sky130_fd_sc_hd__o2111a |vpiDefName:work@sky130_fd_sc_hd__o2111a |vpiTop:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o2111a.or0_out), line:53:10, endln:53:17 |vpiParent: - \_module: work@sky130_fd_sc_hd__o2111a (work@sky130_fd_sc_hd__o2111a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o2111a.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o2111a (work@sky130_fd_sc_hd__o2111a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o2111a.functional.v, line:35:1, endln:61:10 |vpiTypespec: \_logic_typespec: , line:53:5, endln:53:9 |vpiName:or0_out @@ -44188,7 +44188,7 @@ design: (work@sky130_fd_sc_hd__o2111a) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o2111a.and0_out_X), line:54:10, endln:54:20 |vpiParent: - \_module: work@sky130_fd_sc_hd__o2111a (work@sky130_fd_sc_hd__o2111a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o2111a.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o2111a (work@sky130_fd_sc_hd__o2111a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o2111a.functional.v, line:35:1, endln:61:10 |vpiTypespec: \_logic_typespec: , line:54:5, endln:54:9 |vpiName:and0_out_X @@ -44197,7 +44197,7 @@ design: (work@sky130_fd_sc_hd__o2111a) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o2111a.X), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__o2111a (work@sky130_fd_sc_hd__o2111a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o2111a.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o2111a (work@sky130_fd_sc_hd__o2111a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o2111a.functional.v, line:35:1, endln:61:10 |vpiTypespec: \_logic_typespec: , line:45:12, endln:45:12 |vpiName:X @@ -44205,7 +44205,7 @@ design: (work@sky130_fd_sc_hd__o2111a) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o2111a.A1), line:37:5, endln:37:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o2111a (work@sky130_fd_sc_hd__o2111a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o2111a.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o2111a (work@sky130_fd_sc_hd__o2111a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o2111a.functional.v, line:35:1, endln:61:10 |vpiTypespec: \_logic_typespec: , line:46:12, endln:46:12 |vpiName:A1 @@ -44213,7 +44213,7 @@ design: (work@sky130_fd_sc_hd__o2111a) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o2111a.A2), line:38:5, endln:38:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o2111a (work@sky130_fd_sc_hd__o2111a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o2111a.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o2111a (work@sky130_fd_sc_hd__o2111a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o2111a.functional.v, line:35:1, endln:61:10 |vpiTypespec: \_logic_typespec: , line:47:12, endln:47:12 |vpiName:A2 @@ -44221,7 +44221,7 @@ design: (work@sky130_fd_sc_hd__o2111a) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o2111a.B1), line:39:5, endln:39:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o2111a (work@sky130_fd_sc_hd__o2111a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o2111a.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o2111a (work@sky130_fd_sc_hd__o2111a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o2111a.functional.v, line:35:1, endln:61:10 |vpiTypespec: \_logic_typespec: , line:48:12, endln:48:12 |vpiName:B1 @@ -44229,7 +44229,7 @@ design: (work@sky130_fd_sc_hd__o2111a) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o2111a.C1), line:40:5, endln:40:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o2111a (work@sky130_fd_sc_hd__o2111a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o2111a.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o2111a (work@sky130_fd_sc_hd__o2111a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o2111a.functional.v, line:35:1, endln:61:10 |vpiTypespec: \_logic_typespec: , line:49:12, endln:49:12 |vpiName:C1 @@ -44237,7 +44237,7 @@ design: (work@sky130_fd_sc_hd__o2111a) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o2111a.D1), line:41:5, endln:41:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o2111a (work@sky130_fd_sc_hd__o2111a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o2111a.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o2111a (work@sky130_fd_sc_hd__o2111a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o2111a.functional.v, line:35:1, endln:61:10 |vpiTypespec: \_logic_typespec: , line:50:12, endln:50:12 |vpiName:D1 @@ -44246,7 +44246,7 @@ design: (work@sky130_fd_sc_hd__o2111a) |vpiPort: \_port: (X), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__o2111a (work@sky130_fd_sc_hd__o2111a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o2111a.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o2111a (work@sky130_fd_sc_hd__o2111a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o2111a.functional.v, line:35:1, endln:61:10 |vpiName:X |vpiDirection:2 |vpiLowConn: @@ -44260,7 +44260,7 @@ design: (work@sky130_fd_sc_hd__o2111a) |vpiPort: \_port: (A1), line:37:5, endln:37:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o2111a (work@sky130_fd_sc_hd__o2111a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o2111a.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o2111a (work@sky130_fd_sc_hd__o2111a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o2111a.functional.v, line:35:1, endln:61:10 |vpiName:A1 |vpiDirection:1 |vpiLowConn: @@ -44274,7 +44274,7 @@ design: (work@sky130_fd_sc_hd__o2111a) |vpiPort: \_port: (A2), line:38:5, endln:38:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o2111a (work@sky130_fd_sc_hd__o2111a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o2111a.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o2111a (work@sky130_fd_sc_hd__o2111a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o2111a.functional.v, line:35:1, endln:61:10 |vpiName:A2 |vpiDirection:1 |vpiLowConn: @@ -44288,7 +44288,7 @@ design: (work@sky130_fd_sc_hd__o2111a) |vpiPort: \_port: (B1), line:39:5, endln:39:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o2111a (work@sky130_fd_sc_hd__o2111a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o2111a.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o2111a (work@sky130_fd_sc_hd__o2111a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o2111a.functional.v, line:35:1, endln:61:10 |vpiName:B1 |vpiDirection:1 |vpiLowConn: @@ -44302,7 +44302,7 @@ design: (work@sky130_fd_sc_hd__o2111a) |vpiPort: \_port: (C1), line:40:5, endln:40:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o2111a (work@sky130_fd_sc_hd__o2111a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o2111a.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o2111a (work@sky130_fd_sc_hd__o2111a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o2111a.functional.v, line:35:1, endln:61:10 |vpiName:C1 |vpiDirection:1 |vpiLowConn: @@ -44316,7 +44316,7 @@ design: (work@sky130_fd_sc_hd__o2111a) |vpiPort: \_port: (D1), line:41:5, endln:41:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o2111a (work@sky130_fd_sc_hd__o2111a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o2111a.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o2111a (work@sky130_fd_sc_hd__o2111a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o2111a.functional.v, line:35:1, endln:61:10 |vpiName:D1 |vpiDirection:1 |vpiLowConn: @@ -44330,7 +44330,7 @@ design: (work@sky130_fd_sc_hd__o2111a) |vpiPrimitive: \_gate: work@or (work@sky130_fd_sc_hd__o2111a.or0), line:57:9, endln:57:47 |vpiParent: - \_module: work@sky130_fd_sc_hd__o2111a (work@sky130_fd_sc_hd__o2111a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o2111a.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o2111a (work@sky130_fd_sc_hd__o2111a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o2111a.functional.v, line:35:1, endln:61:10 |vpiDefName:work@or |vpiName:or0 |vpiFullName:work@sky130_fd_sc_hd__o2111a.or0 @@ -44379,7 +44379,7 @@ design: (work@sky130_fd_sc_hd__o2111a) |vpiPrimitive: \_gate: work@and (work@sky130_fd_sc_hd__o2111a.and0), line:58:9, endln:58:47 |vpiParent: - \_module: work@sky130_fd_sc_hd__o2111a (work@sky130_fd_sc_hd__o2111a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o2111a.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o2111a (work@sky130_fd_sc_hd__o2111a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o2111a.functional.v, line:35:1, endln:61:10 |vpiDefName:work@and |vpiName:and0 |vpiFullName:work@sky130_fd_sc_hd__o2111a.and0 @@ -44456,7 +44456,7 @@ design: (work@sky130_fd_sc_hd__o2111a) |vpiPrimitive: \_gate: work@buf (work@sky130_fd_sc_hd__o2111a.buf0), line:59:9, endln:59:47 |vpiParent: - \_module: work@sky130_fd_sc_hd__o2111a (work@sky130_fd_sc_hd__o2111a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o2111a.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o2111a (work@sky130_fd_sc_hd__o2111a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o2111a.functional.v, line:35:1, endln:61:10 |vpiDefName:work@buf |vpiName:buf0 |vpiFullName:work@sky130_fd_sc_hd__o2111a.buf0 @@ -44499,7 +44499,7 @@ Processing: -cd cells/cells -DUNIT_DELAY -writepp -parse -nocache -nobuiltin -no design: (work@sky130_fd_sc_hd__and4b) |vpiName:work@sky130_fd_sc_hd__and4b |uhdmallModules: -\_module: work@sky130_fd_sc_hd__and4b (work@sky130_fd_sc_hd__and4b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and4b.functional.v, line:33:1, endln:57:10 +\_module_inst: work@sky130_fd_sc_hd__and4b (work@sky130_fd_sc_hd__and4b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and4b.functional.v, line:33:1, endln:57:10 |vpiParent: \_design: (work@sky130_fd_sc_hd__and4b) |vpiFullName:work@sky130_fd_sc_hd__and4b @@ -44507,51 +44507,51 @@ design: (work@sky130_fd_sc_hd__and4b) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__and4b.not0_out), line:49:10, endln:49:18 |vpiParent: - \_module: work@sky130_fd_sc_hd__and4b (work@sky130_fd_sc_hd__and4b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and4b.functional.v, line:33:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__and4b (work@sky130_fd_sc_hd__and4b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and4b.functional.v, line:33:1, endln:57:10 |vpiName:not0_out |vpiFullName:work@sky130_fd_sc_hd__and4b.not0_out |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__and4b.and0_out_X), line:50:10, endln:50:20 |vpiParent: - \_module: work@sky130_fd_sc_hd__and4b (work@sky130_fd_sc_hd__and4b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and4b.functional.v, line:33:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__and4b (work@sky130_fd_sc_hd__and4b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and4b.functional.v, line:33:1, endln:57:10 |vpiName:and0_out_X |vpiFullName:work@sky130_fd_sc_hd__and4b.and0_out_X |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__and4b.X), line:34:5, endln:34:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__and4b (work@sky130_fd_sc_hd__and4b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and4b.functional.v, line:33:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__and4b (work@sky130_fd_sc_hd__and4b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and4b.functional.v, line:33:1, endln:57:10 |vpiName:X |vpiFullName:work@sky130_fd_sc_hd__and4b.X |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__and4b.A_N), line:35:5, endln:35:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__and4b (work@sky130_fd_sc_hd__and4b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and4b.functional.v, line:33:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__and4b (work@sky130_fd_sc_hd__and4b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and4b.functional.v, line:33:1, endln:57:10 |vpiName:A_N |vpiFullName:work@sky130_fd_sc_hd__and4b.A_N |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__and4b.B), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__and4b (work@sky130_fd_sc_hd__and4b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and4b.functional.v, line:33:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__and4b (work@sky130_fd_sc_hd__and4b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and4b.functional.v, line:33:1, endln:57:10 |vpiName:B |vpiFullName:work@sky130_fd_sc_hd__and4b.B |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__and4b.C), line:37:5, endln:37:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__and4b (work@sky130_fd_sc_hd__and4b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and4b.functional.v, line:33:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__and4b (work@sky130_fd_sc_hd__and4b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and4b.functional.v, line:33:1, endln:57:10 |vpiName:C |vpiFullName:work@sky130_fd_sc_hd__and4b.C |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__and4b.D), line:38:5, endln:38:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__and4b (work@sky130_fd_sc_hd__and4b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and4b.functional.v, line:33:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__and4b (work@sky130_fd_sc_hd__and4b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and4b.functional.v, line:33:1, endln:57:10 |vpiName:D |vpiFullName:work@sky130_fd_sc_hd__and4b.D |vpiPort: \_port: (X), line:34:5, endln:34:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__and4b (work@sky130_fd_sc_hd__and4b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and4b.functional.v, line:33:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__and4b (work@sky130_fd_sc_hd__and4b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and4b.functional.v, line:33:1, endln:57:10 |vpiName:X |vpiDirection:2 |vpiLowConn: @@ -44563,7 +44563,7 @@ design: (work@sky130_fd_sc_hd__and4b) |vpiPort: \_port: (A_N), line:35:5, endln:35:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__and4b (work@sky130_fd_sc_hd__and4b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and4b.functional.v, line:33:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__and4b (work@sky130_fd_sc_hd__and4b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and4b.functional.v, line:33:1, endln:57:10 |vpiName:A_N |vpiDirection:1 |vpiLowConn: @@ -44575,7 +44575,7 @@ design: (work@sky130_fd_sc_hd__and4b) |vpiPort: \_port: (B), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__and4b (work@sky130_fd_sc_hd__and4b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and4b.functional.v, line:33:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__and4b (work@sky130_fd_sc_hd__and4b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and4b.functional.v, line:33:1, endln:57:10 |vpiName:B |vpiDirection:1 |vpiLowConn: @@ -44587,7 +44587,7 @@ design: (work@sky130_fd_sc_hd__and4b) |vpiPort: \_port: (C), line:37:5, endln:37:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__and4b (work@sky130_fd_sc_hd__and4b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and4b.functional.v, line:33:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__and4b (work@sky130_fd_sc_hd__and4b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and4b.functional.v, line:33:1, endln:57:10 |vpiName:C |vpiDirection:1 |vpiLowConn: @@ -44599,7 +44599,7 @@ design: (work@sky130_fd_sc_hd__and4b) |vpiPort: \_port: (D), line:38:5, endln:38:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__and4b (work@sky130_fd_sc_hd__and4b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and4b.functional.v, line:33:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__and4b (work@sky130_fd_sc_hd__and4b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and4b.functional.v, line:33:1, endln:57:10 |vpiName:D |vpiDirection:1 |vpiLowConn: @@ -44609,14 +44609,14 @@ design: (work@sky130_fd_sc_hd__and4b) |vpiTypedef: \_logic_typespec: , line:46:12, endln:46:12 |uhdmtopModules: -\_module: work@sky130_fd_sc_hd__and4b (work@sky130_fd_sc_hd__and4b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and4b.functional.v, line:33:1, endln:57:10 +\_module_inst: work@sky130_fd_sc_hd__and4b (work@sky130_fd_sc_hd__and4b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and4b.functional.v, line:33:1, endln:57:10 |vpiName:work@sky130_fd_sc_hd__and4b |vpiDefName:work@sky130_fd_sc_hd__and4b |vpiTop:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__and4b.not0_out), line:49:10, endln:49:18 |vpiParent: - \_module: work@sky130_fd_sc_hd__and4b (work@sky130_fd_sc_hd__and4b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and4b.functional.v, line:33:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__and4b (work@sky130_fd_sc_hd__and4b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and4b.functional.v, line:33:1, endln:57:10 |vpiTypespec: \_logic_typespec: , line:49:5, endln:49:9 |vpiName:not0_out @@ -44625,7 +44625,7 @@ design: (work@sky130_fd_sc_hd__and4b) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__and4b.and0_out_X), line:50:10, endln:50:20 |vpiParent: - \_module: work@sky130_fd_sc_hd__and4b (work@sky130_fd_sc_hd__and4b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and4b.functional.v, line:33:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__and4b (work@sky130_fd_sc_hd__and4b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and4b.functional.v, line:33:1, endln:57:10 |vpiTypespec: \_logic_typespec: , line:50:5, endln:50:9 |vpiName:and0_out_X @@ -44634,7 +44634,7 @@ design: (work@sky130_fd_sc_hd__and4b) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__and4b.X), line:34:5, endln:34:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__and4b (work@sky130_fd_sc_hd__and4b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and4b.functional.v, line:33:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__and4b (work@sky130_fd_sc_hd__and4b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and4b.functional.v, line:33:1, endln:57:10 |vpiTypespec: \_logic_typespec: , line:42:12, endln:42:12 |vpiName:X @@ -44642,7 +44642,7 @@ design: (work@sky130_fd_sc_hd__and4b) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__and4b.A_N), line:35:5, endln:35:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__and4b (work@sky130_fd_sc_hd__and4b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and4b.functional.v, line:33:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__and4b (work@sky130_fd_sc_hd__and4b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and4b.functional.v, line:33:1, endln:57:10 |vpiTypespec: \_logic_typespec: , line:43:12, endln:43:12 |vpiName:A_N @@ -44650,7 +44650,7 @@ design: (work@sky130_fd_sc_hd__and4b) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__and4b.B), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__and4b (work@sky130_fd_sc_hd__and4b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and4b.functional.v, line:33:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__and4b (work@sky130_fd_sc_hd__and4b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and4b.functional.v, line:33:1, endln:57:10 |vpiTypespec: \_logic_typespec: , line:44:12, endln:44:12 |vpiName:B @@ -44658,7 +44658,7 @@ design: (work@sky130_fd_sc_hd__and4b) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__and4b.C), line:37:5, endln:37:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__and4b (work@sky130_fd_sc_hd__and4b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and4b.functional.v, line:33:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__and4b (work@sky130_fd_sc_hd__and4b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and4b.functional.v, line:33:1, endln:57:10 |vpiTypespec: \_logic_typespec: , line:45:12, endln:45:12 |vpiName:C @@ -44666,7 +44666,7 @@ design: (work@sky130_fd_sc_hd__and4b) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__and4b.D), line:38:5, endln:38:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__and4b (work@sky130_fd_sc_hd__and4b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and4b.functional.v, line:33:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__and4b (work@sky130_fd_sc_hd__and4b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and4b.functional.v, line:33:1, endln:57:10 |vpiTypespec: \_logic_typespec: , line:46:12, endln:46:12 |vpiName:D @@ -44675,7 +44675,7 @@ design: (work@sky130_fd_sc_hd__and4b) |vpiPort: \_port: (X), line:34:5, endln:34:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__and4b (work@sky130_fd_sc_hd__and4b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and4b.functional.v, line:33:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__and4b (work@sky130_fd_sc_hd__and4b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and4b.functional.v, line:33:1, endln:57:10 |vpiName:X |vpiDirection:2 |vpiLowConn: @@ -44689,7 +44689,7 @@ design: (work@sky130_fd_sc_hd__and4b) |vpiPort: \_port: (A_N), line:35:5, endln:35:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__and4b (work@sky130_fd_sc_hd__and4b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and4b.functional.v, line:33:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__and4b (work@sky130_fd_sc_hd__and4b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and4b.functional.v, line:33:1, endln:57:10 |vpiName:A_N |vpiDirection:1 |vpiLowConn: @@ -44703,7 +44703,7 @@ design: (work@sky130_fd_sc_hd__and4b) |vpiPort: \_port: (B), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__and4b (work@sky130_fd_sc_hd__and4b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and4b.functional.v, line:33:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__and4b (work@sky130_fd_sc_hd__and4b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and4b.functional.v, line:33:1, endln:57:10 |vpiName:B |vpiDirection:1 |vpiLowConn: @@ -44717,7 +44717,7 @@ design: (work@sky130_fd_sc_hd__and4b) |vpiPort: \_port: (C), line:37:5, endln:37:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__and4b (work@sky130_fd_sc_hd__and4b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and4b.functional.v, line:33:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__and4b (work@sky130_fd_sc_hd__and4b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and4b.functional.v, line:33:1, endln:57:10 |vpiName:C |vpiDirection:1 |vpiLowConn: @@ -44731,7 +44731,7 @@ design: (work@sky130_fd_sc_hd__and4b) |vpiPort: \_port: (D), line:38:5, endln:38:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__and4b (work@sky130_fd_sc_hd__and4b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and4b.functional.v, line:33:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__and4b (work@sky130_fd_sc_hd__and4b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and4b.functional.v, line:33:1, endln:57:10 |vpiName:D |vpiDirection:1 |vpiLowConn: @@ -44745,7 +44745,7 @@ design: (work@sky130_fd_sc_hd__and4b) |vpiPrimitive: \_gate: work@not (work@sky130_fd_sc_hd__and4b.not0), line:53:9, endln:53:45 |vpiParent: - \_module: work@sky130_fd_sc_hd__and4b (work@sky130_fd_sc_hd__and4b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and4b.functional.v, line:33:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__and4b (work@sky130_fd_sc_hd__and4b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and4b.functional.v, line:33:1, endln:57:10 |vpiDefName:work@not |vpiName:not0 |vpiFullName:work@sky130_fd_sc_hd__and4b.not0 @@ -44780,7 +44780,7 @@ design: (work@sky130_fd_sc_hd__and4b) |vpiPrimitive: \_gate: work@and (work@sky130_fd_sc_hd__and4b.and0), line:54:9, endln:54:45 |vpiParent: - \_module: work@sky130_fd_sc_hd__and4b (work@sky130_fd_sc_hd__and4b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and4b.functional.v, line:33:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__and4b (work@sky130_fd_sc_hd__and4b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and4b.functional.v, line:33:1, endln:57:10 |vpiDefName:work@and |vpiName:and0 |vpiFullName:work@sky130_fd_sc_hd__and4b.and0 @@ -44857,7 +44857,7 @@ design: (work@sky130_fd_sc_hd__and4b) |vpiPrimitive: \_gate: work@buf (work@sky130_fd_sc_hd__and4b.buf0), line:55:9, endln:55:45 |vpiParent: - \_module: work@sky130_fd_sc_hd__and4b (work@sky130_fd_sc_hd__and4b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and4b.functional.v, line:33:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__and4b (work@sky130_fd_sc_hd__and4b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and4b.functional.v, line:33:1, endln:57:10 |vpiDefName:work@buf |vpiName:buf0 |vpiFullName:work@sky130_fd_sc_hd__and4b.buf0 @@ -44900,7 +44900,7 @@ Processing: -cd cells/cells -DUNIT_DELAY -writepp -parse -nocache -nobuiltin -no design: (work@sky130_fd_sc_hd__and2) |vpiName:work@sky130_fd_sc_hd__and2 |uhdmallModules: -\_module: work@sky130_fd_sc_hd__and2 (work@sky130_fd_sc_hd__and2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and2.functional.v, line:33:1, endln:51:10 +\_module_inst: work@sky130_fd_sc_hd__and2 (work@sky130_fd_sc_hd__and2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and2.functional.v, line:33:1, endln:51:10 |vpiParent: \_design: (work@sky130_fd_sc_hd__and2) |vpiFullName:work@sky130_fd_sc_hd__and2 @@ -44908,32 +44908,32 @@ design: (work@sky130_fd_sc_hd__and2) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__and2.and0_out_X), line:45:10, endln:45:20 |vpiParent: - \_module: work@sky130_fd_sc_hd__and2 (work@sky130_fd_sc_hd__and2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and2.functional.v, line:33:1, endln:51:10 + \_module_inst: work@sky130_fd_sc_hd__and2 (work@sky130_fd_sc_hd__and2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and2.functional.v, line:33:1, endln:51:10 |vpiName:and0_out_X |vpiFullName:work@sky130_fd_sc_hd__and2.and0_out_X |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__and2.X), line:34:5, endln:34:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__and2 (work@sky130_fd_sc_hd__and2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and2.functional.v, line:33:1, endln:51:10 + \_module_inst: work@sky130_fd_sc_hd__and2 (work@sky130_fd_sc_hd__and2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and2.functional.v, line:33:1, endln:51:10 |vpiName:X |vpiFullName:work@sky130_fd_sc_hd__and2.X |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__and2.A), line:35:5, endln:35:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__and2 (work@sky130_fd_sc_hd__and2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and2.functional.v, line:33:1, endln:51:10 + \_module_inst: work@sky130_fd_sc_hd__and2 (work@sky130_fd_sc_hd__and2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and2.functional.v, line:33:1, endln:51:10 |vpiName:A |vpiFullName:work@sky130_fd_sc_hd__and2.A |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__and2.B), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__and2 (work@sky130_fd_sc_hd__and2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and2.functional.v, line:33:1, endln:51:10 + \_module_inst: work@sky130_fd_sc_hd__and2 (work@sky130_fd_sc_hd__and2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and2.functional.v, line:33:1, endln:51:10 |vpiName:B |vpiFullName:work@sky130_fd_sc_hd__and2.B |vpiPort: \_port: (X), line:34:5, endln:34:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__and2 (work@sky130_fd_sc_hd__and2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and2.functional.v, line:33:1, endln:51:10 + \_module_inst: work@sky130_fd_sc_hd__and2 (work@sky130_fd_sc_hd__and2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and2.functional.v, line:33:1, endln:51:10 |vpiName:X |vpiDirection:2 |vpiLowConn: @@ -44945,7 +44945,7 @@ design: (work@sky130_fd_sc_hd__and2) |vpiPort: \_port: (A), line:35:5, endln:35:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__and2 (work@sky130_fd_sc_hd__and2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and2.functional.v, line:33:1, endln:51:10 + \_module_inst: work@sky130_fd_sc_hd__and2 (work@sky130_fd_sc_hd__and2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and2.functional.v, line:33:1, endln:51:10 |vpiName:A |vpiDirection:1 |vpiLowConn: @@ -44957,7 +44957,7 @@ design: (work@sky130_fd_sc_hd__and2) |vpiPort: \_port: (B), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__and2 (work@sky130_fd_sc_hd__and2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and2.functional.v, line:33:1, endln:51:10 + \_module_inst: work@sky130_fd_sc_hd__and2 (work@sky130_fd_sc_hd__and2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and2.functional.v, line:33:1, endln:51:10 |vpiName:B |vpiDirection:1 |vpiLowConn: @@ -44967,14 +44967,14 @@ design: (work@sky130_fd_sc_hd__and2) |vpiTypedef: \_logic_typespec: , line:42:12, endln:42:12 |uhdmtopModules: -\_module: work@sky130_fd_sc_hd__and2 (work@sky130_fd_sc_hd__and2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and2.functional.v, line:33:1, endln:51:10 +\_module_inst: work@sky130_fd_sc_hd__and2 (work@sky130_fd_sc_hd__and2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and2.functional.v, line:33:1, endln:51:10 |vpiName:work@sky130_fd_sc_hd__and2 |vpiDefName:work@sky130_fd_sc_hd__and2 |vpiTop:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__and2.and0_out_X), line:45:10, endln:45:20 |vpiParent: - \_module: work@sky130_fd_sc_hd__and2 (work@sky130_fd_sc_hd__and2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and2.functional.v, line:33:1, endln:51:10 + \_module_inst: work@sky130_fd_sc_hd__and2 (work@sky130_fd_sc_hd__and2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and2.functional.v, line:33:1, endln:51:10 |vpiTypespec: \_logic_typespec: , line:45:5, endln:45:9 |vpiName:and0_out_X @@ -44983,7 +44983,7 @@ design: (work@sky130_fd_sc_hd__and2) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__and2.X), line:34:5, endln:34:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__and2 (work@sky130_fd_sc_hd__and2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and2.functional.v, line:33:1, endln:51:10 + \_module_inst: work@sky130_fd_sc_hd__and2 (work@sky130_fd_sc_hd__and2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and2.functional.v, line:33:1, endln:51:10 |vpiTypespec: \_logic_typespec: , line:40:12, endln:40:12 |vpiName:X @@ -44991,7 +44991,7 @@ design: (work@sky130_fd_sc_hd__and2) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__and2.A), line:35:5, endln:35:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__and2 (work@sky130_fd_sc_hd__and2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and2.functional.v, line:33:1, endln:51:10 + \_module_inst: work@sky130_fd_sc_hd__and2 (work@sky130_fd_sc_hd__and2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and2.functional.v, line:33:1, endln:51:10 |vpiTypespec: \_logic_typespec: , line:41:12, endln:41:12 |vpiName:A @@ -44999,7 +44999,7 @@ design: (work@sky130_fd_sc_hd__and2) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__and2.B), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__and2 (work@sky130_fd_sc_hd__and2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and2.functional.v, line:33:1, endln:51:10 + \_module_inst: work@sky130_fd_sc_hd__and2 (work@sky130_fd_sc_hd__and2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and2.functional.v, line:33:1, endln:51:10 |vpiTypespec: \_logic_typespec: , line:42:12, endln:42:12 |vpiName:B @@ -45008,7 +45008,7 @@ design: (work@sky130_fd_sc_hd__and2) |vpiPort: \_port: (X), line:34:5, endln:34:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__and2 (work@sky130_fd_sc_hd__and2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and2.functional.v, line:33:1, endln:51:10 + \_module_inst: work@sky130_fd_sc_hd__and2 (work@sky130_fd_sc_hd__and2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and2.functional.v, line:33:1, endln:51:10 |vpiName:X |vpiDirection:2 |vpiLowConn: @@ -45022,7 +45022,7 @@ design: (work@sky130_fd_sc_hd__and2) |vpiPort: \_port: (A), line:35:5, endln:35:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__and2 (work@sky130_fd_sc_hd__and2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and2.functional.v, line:33:1, endln:51:10 + \_module_inst: work@sky130_fd_sc_hd__and2 (work@sky130_fd_sc_hd__and2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and2.functional.v, line:33:1, endln:51:10 |vpiName:A |vpiDirection:1 |vpiLowConn: @@ -45036,7 +45036,7 @@ design: (work@sky130_fd_sc_hd__and2) |vpiPort: \_port: (B), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__and2 (work@sky130_fd_sc_hd__and2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and2.functional.v, line:33:1, endln:51:10 + \_module_inst: work@sky130_fd_sc_hd__and2 (work@sky130_fd_sc_hd__and2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and2.functional.v, line:33:1, endln:51:10 |vpiName:B |vpiDirection:1 |vpiLowConn: @@ -45050,7 +45050,7 @@ design: (work@sky130_fd_sc_hd__and2) |vpiPrimitive: \_gate: work@and (work@sky130_fd_sc_hd__and2.and0), line:48:9, endln:48:43 |vpiParent: - \_module: work@sky130_fd_sc_hd__and2 (work@sky130_fd_sc_hd__and2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and2.functional.v, line:33:1, endln:51:10 + \_module_inst: work@sky130_fd_sc_hd__and2 (work@sky130_fd_sc_hd__and2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and2.functional.v, line:33:1, endln:51:10 |vpiDefName:work@and |vpiName:and0 |vpiFullName:work@sky130_fd_sc_hd__and2.and0 @@ -45099,7 +45099,7 @@ design: (work@sky130_fd_sc_hd__and2) |vpiPrimitive: \_gate: work@buf (work@sky130_fd_sc_hd__and2.buf0), line:49:9, endln:49:43 |vpiParent: - \_module: work@sky130_fd_sc_hd__and2 (work@sky130_fd_sc_hd__and2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and2.functional.v, line:33:1, endln:51:10 + \_module_inst: work@sky130_fd_sc_hd__and2 (work@sky130_fd_sc_hd__and2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and2.functional.v, line:33:1, endln:51:10 |vpiDefName:work@buf |vpiName:buf0 |vpiFullName:work@sky130_fd_sc_hd__and2.buf0 @@ -45142,7 +45142,7 @@ Processing: -cd cells/cells -DUNIT_DELAY -writepp -parse -nocache -nobuiltin -no design: (work@sky130_fd_sc_hd__o21bai) |vpiName:work@sky130_fd_sc_hd__o21bai |uhdmallModules: -\_module: work@sky130_fd_sc_hd__o21bai (work@sky130_fd_sc_hd__o21bai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o21bai.functional.v, line:36:1, endln:60:10 +\_module_inst: work@sky130_fd_sc_hd__o21bai (work@sky130_fd_sc_hd__o21bai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o21bai.functional.v, line:36:1, endln:60:10 |vpiParent: \_design: (work@sky130_fd_sc_hd__o21bai) |vpiFullName:work@sky130_fd_sc_hd__o21bai @@ -45150,52 +45150,52 @@ design: (work@sky130_fd_sc_hd__o21bai) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o21bai.b), line:50:10, endln:50:11 |vpiParent: - \_module: work@sky130_fd_sc_hd__o21bai (work@sky130_fd_sc_hd__o21bai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o21bai.functional.v, line:36:1, endln:60:10 + \_module_inst: work@sky130_fd_sc_hd__o21bai (work@sky130_fd_sc_hd__o21bai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o21bai.functional.v, line:36:1, endln:60:10 |vpiName:b |vpiFullName:work@sky130_fd_sc_hd__o21bai.b |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o21bai.or0_out), line:51:10, endln:51:17 |vpiParent: - \_module: work@sky130_fd_sc_hd__o21bai (work@sky130_fd_sc_hd__o21bai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o21bai.functional.v, line:36:1, endln:60:10 + \_module_inst: work@sky130_fd_sc_hd__o21bai (work@sky130_fd_sc_hd__o21bai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o21bai.functional.v, line:36:1, endln:60:10 |vpiName:or0_out |vpiFullName:work@sky130_fd_sc_hd__o21bai.or0_out |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o21bai.nand0_out_Y), line:52:10, endln:52:21 |vpiParent: - \_module: work@sky130_fd_sc_hd__o21bai (work@sky130_fd_sc_hd__o21bai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o21bai.functional.v, line:36:1, endln:60:10 + \_module_inst: work@sky130_fd_sc_hd__o21bai (work@sky130_fd_sc_hd__o21bai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o21bai.functional.v, line:36:1, endln:60:10 |vpiName:nand0_out_Y |vpiFullName:work@sky130_fd_sc_hd__o21bai.nand0_out_Y |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o21bai.Y), line:37:5, endln:37:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__o21bai (work@sky130_fd_sc_hd__o21bai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o21bai.functional.v, line:36:1, endln:60:10 + \_module_inst: work@sky130_fd_sc_hd__o21bai (work@sky130_fd_sc_hd__o21bai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o21bai.functional.v, line:36:1, endln:60:10 |vpiName:Y |vpiFullName:work@sky130_fd_sc_hd__o21bai.Y |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o21bai.A1), line:38:5, endln:38:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o21bai (work@sky130_fd_sc_hd__o21bai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o21bai.functional.v, line:36:1, endln:60:10 + \_module_inst: work@sky130_fd_sc_hd__o21bai (work@sky130_fd_sc_hd__o21bai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o21bai.functional.v, line:36:1, endln:60:10 |vpiName:A1 |vpiFullName:work@sky130_fd_sc_hd__o21bai.A1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o21bai.A2), line:39:5, endln:39:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o21bai (work@sky130_fd_sc_hd__o21bai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o21bai.functional.v, line:36:1, endln:60:10 + \_module_inst: work@sky130_fd_sc_hd__o21bai (work@sky130_fd_sc_hd__o21bai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o21bai.functional.v, line:36:1, endln:60:10 |vpiName:A2 |vpiFullName:work@sky130_fd_sc_hd__o21bai.A2 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o21bai.B1_N), line:40:5, endln:40:9 |vpiParent: - \_module: work@sky130_fd_sc_hd__o21bai (work@sky130_fd_sc_hd__o21bai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o21bai.functional.v, line:36:1, endln:60:10 + \_module_inst: work@sky130_fd_sc_hd__o21bai (work@sky130_fd_sc_hd__o21bai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o21bai.functional.v, line:36:1, endln:60:10 |vpiName:B1_N |vpiFullName:work@sky130_fd_sc_hd__o21bai.B1_N |vpiPort: \_port: (Y), line:37:5, endln:37:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__o21bai (work@sky130_fd_sc_hd__o21bai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o21bai.functional.v, line:36:1, endln:60:10 + \_module_inst: work@sky130_fd_sc_hd__o21bai (work@sky130_fd_sc_hd__o21bai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o21bai.functional.v, line:36:1, endln:60:10 |vpiName:Y |vpiDirection:2 |vpiLowConn: @@ -45207,7 +45207,7 @@ design: (work@sky130_fd_sc_hd__o21bai) |vpiPort: \_port: (A1), line:38:5, endln:38:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o21bai (work@sky130_fd_sc_hd__o21bai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o21bai.functional.v, line:36:1, endln:60:10 + \_module_inst: work@sky130_fd_sc_hd__o21bai (work@sky130_fd_sc_hd__o21bai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o21bai.functional.v, line:36:1, endln:60:10 |vpiName:A1 |vpiDirection:1 |vpiLowConn: @@ -45219,7 +45219,7 @@ design: (work@sky130_fd_sc_hd__o21bai) |vpiPort: \_port: (A2), line:39:5, endln:39:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o21bai (work@sky130_fd_sc_hd__o21bai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o21bai.functional.v, line:36:1, endln:60:10 + \_module_inst: work@sky130_fd_sc_hd__o21bai (work@sky130_fd_sc_hd__o21bai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o21bai.functional.v, line:36:1, endln:60:10 |vpiName:A2 |vpiDirection:1 |vpiLowConn: @@ -45231,7 +45231,7 @@ design: (work@sky130_fd_sc_hd__o21bai) |vpiPort: \_port: (B1_N), line:40:5, endln:40:9 |vpiParent: - \_module: work@sky130_fd_sc_hd__o21bai (work@sky130_fd_sc_hd__o21bai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o21bai.functional.v, line:36:1, endln:60:10 + \_module_inst: work@sky130_fd_sc_hd__o21bai (work@sky130_fd_sc_hd__o21bai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o21bai.functional.v, line:36:1, endln:60:10 |vpiName:B1_N |vpiDirection:1 |vpiLowConn: @@ -45241,14 +45241,14 @@ design: (work@sky130_fd_sc_hd__o21bai) |vpiTypedef: \_logic_typespec: , line:47:12, endln:47:12 |uhdmtopModules: -\_module: work@sky130_fd_sc_hd__o21bai (work@sky130_fd_sc_hd__o21bai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o21bai.functional.v, line:36:1, endln:60:10 +\_module_inst: work@sky130_fd_sc_hd__o21bai (work@sky130_fd_sc_hd__o21bai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o21bai.functional.v, line:36:1, endln:60:10 |vpiName:work@sky130_fd_sc_hd__o21bai |vpiDefName:work@sky130_fd_sc_hd__o21bai |vpiTop:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o21bai.b), line:50:10, endln:50:11 |vpiParent: - \_module: work@sky130_fd_sc_hd__o21bai (work@sky130_fd_sc_hd__o21bai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o21bai.functional.v, line:36:1, endln:60:10 + \_module_inst: work@sky130_fd_sc_hd__o21bai (work@sky130_fd_sc_hd__o21bai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o21bai.functional.v, line:36:1, endln:60:10 |vpiTypespec: \_logic_typespec: , line:50:5, endln:50:9 |vpiName:b @@ -45257,7 +45257,7 @@ design: (work@sky130_fd_sc_hd__o21bai) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o21bai.or0_out), line:51:10, endln:51:17 |vpiParent: - \_module: work@sky130_fd_sc_hd__o21bai (work@sky130_fd_sc_hd__o21bai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o21bai.functional.v, line:36:1, endln:60:10 + \_module_inst: work@sky130_fd_sc_hd__o21bai (work@sky130_fd_sc_hd__o21bai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o21bai.functional.v, line:36:1, endln:60:10 |vpiTypespec: \_logic_typespec: , line:51:5, endln:51:9 |vpiName:or0_out @@ -45266,7 +45266,7 @@ design: (work@sky130_fd_sc_hd__o21bai) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o21bai.nand0_out_Y), line:52:10, endln:52:21 |vpiParent: - \_module: work@sky130_fd_sc_hd__o21bai (work@sky130_fd_sc_hd__o21bai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o21bai.functional.v, line:36:1, endln:60:10 + \_module_inst: work@sky130_fd_sc_hd__o21bai (work@sky130_fd_sc_hd__o21bai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o21bai.functional.v, line:36:1, endln:60:10 |vpiTypespec: \_logic_typespec: , line:52:5, endln:52:9 |vpiName:nand0_out_Y @@ -45275,7 +45275,7 @@ design: (work@sky130_fd_sc_hd__o21bai) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o21bai.Y), line:37:5, endln:37:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__o21bai (work@sky130_fd_sc_hd__o21bai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o21bai.functional.v, line:36:1, endln:60:10 + \_module_inst: work@sky130_fd_sc_hd__o21bai (work@sky130_fd_sc_hd__o21bai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o21bai.functional.v, line:36:1, endln:60:10 |vpiTypespec: \_logic_typespec: , line:44:12, endln:44:12 |vpiName:Y @@ -45283,7 +45283,7 @@ design: (work@sky130_fd_sc_hd__o21bai) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o21bai.A1), line:38:5, endln:38:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o21bai (work@sky130_fd_sc_hd__o21bai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o21bai.functional.v, line:36:1, endln:60:10 + \_module_inst: work@sky130_fd_sc_hd__o21bai (work@sky130_fd_sc_hd__o21bai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o21bai.functional.v, line:36:1, endln:60:10 |vpiTypespec: \_logic_typespec: , line:45:12, endln:45:12 |vpiName:A1 @@ -45291,7 +45291,7 @@ design: (work@sky130_fd_sc_hd__o21bai) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o21bai.A2), line:39:5, endln:39:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o21bai (work@sky130_fd_sc_hd__o21bai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o21bai.functional.v, line:36:1, endln:60:10 + \_module_inst: work@sky130_fd_sc_hd__o21bai (work@sky130_fd_sc_hd__o21bai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o21bai.functional.v, line:36:1, endln:60:10 |vpiTypespec: \_logic_typespec: , line:46:12, endln:46:12 |vpiName:A2 @@ -45299,7 +45299,7 @@ design: (work@sky130_fd_sc_hd__o21bai) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o21bai.B1_N), line:40:5, endln:40:9 |vpiParent: - \_module: work@sky130_fd_sc_hd__o21bai (work@sky130_fd_sc_hd__o21bai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o21bai.functional.v, line:36:1, endln:60:10 + \_module_inst: work@sky130_fd_sc_hd__o21bai (work@sky130_fd_sc_hd__o21bai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o21bai.functional.v, line:36:1, endln:60:10 |vpiTypespec: \_logic_typespec: , line:47:12, endln:47:12 |vpiName:B1_N @@ -45308,7 +45308,7 @@ design: (work@sky130_fd_sc_hd__o21bai) |vpiPort: \_port: (Y), line:37:5, endln:37:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__o21bai (work@sky130_fd_sc_hd__o21bai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o21bai.functional.v, line:36:1, endln:60:10 + \_module_inst: work@sky130_fd_sc_hd__o21bai (work@sky130_fd_sc_hd__o21bai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o21bai.functional.v, line:36:1, endln:60:10 |vpiName:Y |vpiDirection:2 |vpiLowConn: @@ -45322,7 +45322,7 @@ design: (work@sky130_fd_sc_hd__o21bai) |vpiPort: \_port: (A1), line:38:5, endln:38:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o21bai (work@sky130_fd_sc_hd__o21bai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o21bai.functional.v, line:36:1, endln:60:10 + \_module_inst: work@sky130_fd_sc_hd__o21bai (work@sky130_fd_sc_hd__o21bai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o21bai.functional.v, line:36:1, endln:60:10 |vpiName:A1 |vpiDirection:1 |vpiLowConn: @@ -45336,7 +45336,7 @@ design: (work@sky130_fd_sc_hd__o21bai) |vpiPort: \_port: (A2), line:39:5, endln:39:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o21bai (work@sky130_fd_sc_hd__o21bai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o21bai.functional.v, line:36:1, endln:60:10 + \_module_inst: work@sky130_fd_sc_hd__o21bai (work@sky130_fd_sc_hd__o21bai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o21bai.functional.v, line:36:1, endln:60:10 |vpiName:A2 |vpiDirection:1 |vpiLowConn: @@ -45350,7 +45350,7 @@ design: (work@sky130_fd_sc_hd__o21bai) |vpiPort: \_port: (B1_N), line:40:5, endln:40:9 |vpiParent: - \_module: work@sky130_fd_sc_hd__o21bai (work@sky130_fd_sc_hd__o21bai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o21bai.functional.v, line:36:1, endln:60:10 + \_module_inst: work@sky130_fd_sc_hd__o21bai (work@sky130_fd_sc_hd__o21bai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o21bai.functional.v, line:36:1, endln:60:10 |vpiName:B1_N |vpiDirection:1 |vpiLowConn: @@ -45364,7 +45364,7 @@ design: (work@sky130_fd_sc_hd__o21bai) |vpiPrimitive: \_gate: work@not (work@sky130_fd_sc_hd__o21bai.not0), line:55:10, endln:55:46 |vpiParent: - \_module: work@sky130_fd_sc_hd__o21bai (work@sky130_fd_sc_hd__o21bai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o21bai.functional.v, line:36:1, endln:60:10 + \_module_inst: work@sky130_fd_sc_hd__o21bai (work@sky130_fd_sc_hd__o21bai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o21bai.functional.v, line:36:1, endln:60:10 |vpiDefName:work@not |vpiName:not0 |vpiFullName:work@sky130_fd_sc_hd__o21bai.not0 @@ -45399,7 +45399,7 @@ design: (work@sky130_fd_sc_hd__o21bai) |vpiPrimitive: \_gate: work@or (work@sky130_fd_sc_hd__o21bai.or0), line:56:10, endln:56:46 |vpiParent: - \_module: work@sky130_fd_sc_hd__o21bai (work@sky130_fd_sc_hd__o21bai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o21bai.functional.v, line:36:1, endln:60:10 + \_module_inst: work@sky130_fd_sc_hd__o21bai (work@sky130_fd_sc_hd__o21bai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o21bai.functional.v, line:36:1, endln:60:10 |vpiDefName:work@or |vpiName:or0 |vpiFullName:work@sky130_fd_sc_hd__o21bai.or0 @@ -45448,7 +45448,7 @@ design: (work@sky130_fd_sc_hd__o21bai) |vpiPrimitive: \_gate: work@nand (work@sky130_fd_sc_hd__o21bai.nand0), line:57:10, endln:57:46 |vpiParent: - \_module: work@sky130_fd_sc_hd__o21bai (work@sky130_fd_sc_hd__o21bai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o21bai.functional.v, line:36:1, endln:60:10 + \_module_inst: work@sky130_fd_sc_hd__o21bai (work@sky130_fd_sc_hd__o21bai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o21bai.functional.v, line:36:1, endln:60:10 |vpiDefName:work@nand |vpiName:nand0 |vpiFullName:work@sky130_fd_sc_hd__o21bai.nand0 @@ -45497,7 +45497,7 @@ design: (work@sky130_fd_sc_hd__o21bai) |vpiPrimitive: \_gate: work@buf (work@sky130_fd_sc_hd__o21bai.buf0), line:58:10, endln:58:46 |vpiParent: - \_module: work@sky130_fd_sc_hd__o21bai (work@sky130_fd_sc_hd__o21bai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o21bai.functional.v, line:36:1, endln:60:10 + \_module_inst: work@sky130_fd_sc_hd__o21bai (work@sky130_fd_sc_hd__o21bai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o21bai.functional.v, line:36:1, endln:60:10 |vpiDefName:work@buf |vpiName:buf0 |vpiFullName:work@sky130_fd_sc_hd__o21bai.buf0 @@ -45540,7 +45540,7 @@ Processing: -cd cells/cells -DUNIT_DELAY -writepp -parse -nocache -nobuiltin -no design: (work@sky130_fd_sc_hd__fa) |vpiName:work@sky130_fd_sc_hd__fa |uhdmallModules: -\_module: work@sky130_fd_sc_hd__fa (work@sky130_fd_sc_hd__fa), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fa.functional.v, line:33:1, endln:70:10 +\_module_inst: work@sky130_fd_sc_hd__fa (work@sky130_fd_sc_hd__fa), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fa.functional.v, line:33:1, endln:70:10 |vpiParent: \_design: (work@sky130_fd_sc_hd__fa) |vpiFullName:work@sky130_fd_sc_hd__fa @@ -45548,93 +45548,93 @@ design: (work@sky130_fd_sc_hd__fa) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__fa.or0_out), line:49:10, endln:49:17 |vpiParent: - \_module: work@sky130_fd_sc_hd__fa (work@sky130_fd_sc_hd__fa), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fa.functional.v, line:33:1, endln:70:10 + \_module_inst: work@sky130_fd_sc_hd__fa (work@sky130_fd_sc_hd__fa), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fa.functional.v, line:33:1, endln:70:10 |vpiName:or0_out |vpiFullName:work@sky130_fd_sc_hd__fa.or0_out |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__fa.and0_out), line:50:10, endln:50:18 |vpiParent: - \_module: work@sky130_fd_sc_hd__fa (work@sky130_fd_sc_hd__fa), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fa.functional.v, line:33:1, endln:70:10 + \_module_inst: work@sky130_fd_sc_hd__fa (work@sky130_fd_sc_hd__fa), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fa.functional.v, line:33:1, endln:70:10 |vpiName:and0_out |vpiFullName:work@sky130_fd_sc_hd__fa.and0_out |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__fa.and1_out), line:51:10, endln:51:18 |vpiParent: - \_module: work@sky130_fd_sc_hd__fa (work@sky130_fd_sc_hd__fa), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fa.functional.v, line:33:1, endln:70:10 + \_module_inst: work@sky130_fd_sc_hd__fa (work@sky130_fd_sc_hd__fa), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fa.functional.v, line:33:1, endln:70:10 |vpiName:and1_out |vpiFullName:work@sky130_fd_sc_hd__fa.and1_out |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__fa.and2_out), line:52:10, endln:52:18 |vpiParent: - \_module: work@sky130_fd_sc_hd__fa (work@sky130_fd_sc_hd__fa), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fa.functional.v, line:33:1, endln:70:10 + \_module_inst: work@sky130_fd_sc_hd__fa (work@sky130_fd_sc_hd__fa), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fa.functional.v, line:33:1, endln:70:10 |vpiName:and2_out |vpiFullName:work@sky130_fd_sc_hd__fa.and2_out |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__fa.nor0_out), line:53:10, endln:53:18 |vpiParent: - \_module: work@sky130_fd_sc_hd__fa (work@sky130_fd_sc_hd__fa), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fa.functional.v, line:33:1, endln:70:10 + \_module_inst: work@sky130_fd_sc_hd__fa (work@sky130_fd_sc_hd__fa), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fa.functional.v, line:33:1, endln:70:10 |vpiName:nor0_out |vpiFullName:work@sky130_fd_sc_hd__fa.nor0_out |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__fa.nor1_out), line:54:10, endln:54:18 |vpiParent: - \_module: work@sky130_fd_sc_hd__fa (work@sky130_fd_sc_hd__fa), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fa.functional.v, line:33:1, endln:70:10 + \_module_inst: work@sky130_fd_sc_hd__fa (work@sky130_fd_sc_hd__fa), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fa.functional.v, line:33:1, endln:70:10 |vpiName:nor1_out |vpiFullName:work@sky130_fd_sc_hd__fa.nor1_out |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__fa.or1_out_COUT), line:55:10, endln:55:22 |vpiParent: - \_module: work@sky130_fd_sc_hd__fa (work@sky130_fd_sc_hd__fa), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fa.functional.v, line:33:1, endln:70:10 + \_module_inst: work@sky130_fd_sc_hd__fa (work@sky130_fd_sc_hd__fa), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fa.functional.v, line:33:1, endln:70:10 |vpiName:or1_out_COUT |vpiFullName:work@sky130_fd_sc_hd__fa.or1_out_COUT |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__fa.or2_out_SUM), line:56:10, endln:56:21 |vpiParent: - \_module: work@sky130_fd_sc_hd__fa (work@sky130_fd_sc_hd__fa), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fa.functional.v, line:33:1, endln:70:10 + \_module_inst: work@sky130_fd_sc_hd__fa (work@sky130_fd_sc_hd__fa), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fa.functional.v, line:33:1, endln:70:10 |vpiName:or2_out_SUM |vpiFullName:work@sky130_fd_sc_hd__fa.or2_out_SUM |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__fa.COUT), line:34:5, endln:34:9 |vpiParent: - \_module: work@sky130_fd_sc_hd__fa (work@sky130_fd_sc_hd__fa), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fa.functional.v, line:33:1, endln:70:10 + \_module_inst: work@sky130_fd_sc_hd__fa (work@sky130_fd_sc_hd__fa), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fa.functional.v, line:33:1, endln:70:10 |vpiName:COUT |vpiFullName:work@sky130_fd_sc_hd__fa.COUT |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__fa.SUM), line:35:5, endln:35:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__fa (work@sky130_fd_sc_hd__fa), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fa.functional.v, line:33:1, endln:70:10 + \_module_inst: work@sky130_fd_sc_hd__fa (work@sky130_fd_sc_hd__fa), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fa.functional.v, line:33:1, endln:70:10 |vpiName:SUM |vpiFullName:work@sky130_fd_sc_hd__fa.SUM |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__fa.A), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__fa (work@sky130_fd_sc_hd__fa), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fa.functional.v, line:33:1, endln:70:10 + \_module_inst: work@sky130_fd_sc_hd__fa (work@sky130_fd_sc_hd__fa), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fa.functional.v, line:33:1, endln:70:10 |vpiName:A |vpiFullName:work@sky130_fd_sc_hd__fa.A |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__fa.B), line:37:5, endln:37:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__fa (work@sky130_fd_sc_hd__fa), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fa.functional.v, line:33:1, endln:70:10 + \_module_inst: work@sky130_fd_sc_hd__fa (work@sky130_fd_sc_hd__fa), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fa.functional.v, line:33:1, endln:70:10 |vpiName:B |vpiFullName:work@sky130_fd_sc_hd__fa.B |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__fa.CIN), line:38:5, endln:38:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__fa (work@sky130_fd_sc_hd__fa), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fa.functional.v, line:33:1, endln:70:10 + \_module_inst: work@sky130_fd_sc_hd__fa (work@sky130_fd_sc_hd__fa), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fa.functional.v, line:33:1, endln:70:10 |vpiName:CIN |vpiFullName:work@sky130_fd_sc_hd__fa.CIN |vpiPort: \_port: (COUT), line:34:5, endln:34:9 |vpiParent: - \_module: work@sky130_fd_sc_hd__fa (work@sky130_fd_sc_hd__fa), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fa.functional.v, line:33:1, endln:70:10 + \_module_inst: work@sky130_fd_sc_hd__fa (work@sky130_fd_sc_hd__fa), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fa.functional.v, line:33:1, endln:70:10 |vpiName:COUT |vpiDirection:2 |vpiLowConn: @@ -45646,7 +45646,7 @@ design: (work@sky130_fd_sc_hd__fa) |vpiPort: \_port: (SUM), line:35:5, endln:35:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__fa (work@sky130_fd_sc_hd__fa), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fa.functional.v, line:33:1, endln:70:10 + \_module_inst: work@sky130_fd_sc_hd__fa (work@sky130_fd_sc_hd__fa), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fa.functional.v, line:33:1, endln:70:10 |vpiName:SUM |vpiDirection:2 |vpiLowConn: @@ -45658,7 +45658,7 @@ design: (work@sky130_fd_sc_hd__fa) |vpiPort: \_port: (A), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__fa (work@sky130_fd_sc_hd__fa), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fa.functional.v, line:33:1, endln:70:10 + \_module_inst: work@sky130_fd_sc_hd__fa (work@sky130_fd_sc_hd__fa), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fa.functional.v, line:33:1, endln:70:10 |vpiName:A |vpiDirection:1 |vpiLowConn: @@ -45670,7 +45670,7 @@ design: (work@sky130_fd_sc_hd__fa) |vpiPort: \_port: (B), line:37:5, endln:37:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__fa (work@sky130_fd_sc_hd__fa), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fa.functional.v, line:33:1, endln:70:10 + \_module_inst: work@sky130_fd_sc_hd__fa (work@sky130_fd_sc_hd__fa), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fa.functional.v, line:33:1, endln:70:10 |vpiName:B |vpiDirection:1 |vpiLowConn: @@ -45682,7 +45682,7 @@ design: (work@sky130_fd_sc_hd__fa) |vpiPort: \_port: (CIN), line:38:5, endln:38:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__fa (work@sky130_fd_sc_hd__fa), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fa.functional.v, line:33:1, endln:70:10 + \_module_inst: work@sky130_fd_sc_hd__fa (work@sky130_fd_sc_hd__fa), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fa.functional.v, line:33:1, endln:70:10 |vpiName:CIN |vpiDirection:1 |vpiLowConn: @@ -45692,14 +45692,14 @@ design: (work@sky130_fd_sc_hd__fa) |vpiTypedef: \_logic_typespec: , line:46:12, endln:46:12 |uhdmtopModules: -\_module: work@sky130_fd_sc_hd__fa (work@sky130_fd_sc_hd__fa), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fa.functional.v, line:33:1, endln:70:10 +\_module_inst: work@sky130_fd_sc_hd__fa (work@sky130_fd_sc_hd__fa), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fa.functional.v, line:33:1, endln:70:10 |vpiName:work@sky130_fd_sc_hd__fa |vpiDefName:work@sky130_fd_sc_hd__fa |vpiTop:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__fa.or0_out), line:49:10, endln:49:17 |vpiParent: - \_module: work@sky130_fd_sc_hd__fa (work@sky130_fd_sc_hd__fa), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fa.functional.v, line:33:1, endln:70:10 + \_module_inst: work@sky130_fd_sc_hd__fa (work@sky130_fd_sc_hd__fa), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fa.functional.v, line:33:1, endln:70:10 |vpiTypespec: \_logic_typespec: , line:49:5, endln:49:9 |vpiName:or0_out @@ -45708,7 +45708,7 @@ design: (work@sky130_fd_sc_hd__fa) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__fa.and0_out), line:50:10, endln:50:18 |vpiParent: - \_module: work@sky130_fd_sc_hd__fa (work@sky130_fd_sc_hd__fa), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fa.functional.v, line:33:1, endln:70:10 + \_module_inst: work@sky130_fd_sc_hd__fa (work@sky130_fd_sc_hd__fa), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fa.functional.v, line:33:1, endln:70:10 |vpiTypespec: \_logic_typespec: , line:50:5, endln:50:9 |vpiName:and0_out @@ -45717,7 +45717,7 @@ design: (work@sky130_fd_sc_hd__fa) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__fa.and1_out), line:51:10, endln:51:18 |vpiParent: - \_module: work@sky130_fd_sc_hd__fa (work@sky130_fd_sc_hd__fa), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fa.functional.v, line:33:1, endln:70:10 + \_module_inst: work@sky130_fd_sc_hd__fa (work@sky130_fd_sc_hd__fa), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fa.functional.v, line:33:1, endln:70:10 |vpiTypespec: \_logic_typespec: , line:51:5, endln:51:9 |vpiName:and1_out @@ -45726,7 +45726,7 @@ design: (work@sky130_fd_sc_hd__fa) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__fa.and2_out), line:52:10, endln:52:18 |vpiParent: - \_module: work@sky130_fd_sc_hd__fa (work@sky130_fd_sc_hd__fa), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fa.functional.v, line:33:1, endln:70:10 + \_module_inst: work@sky130_fd_sc_hd__fa (work@sky130_fd_sc_hd__fa), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fa.functional.v, line:33:1, endln:70:10 |vpiTypespec: \_logic_typespec: , line:52:5, endln:52:9 |vpiName:and2_out @@ -45735,7 +45735,7 @@ design: (work@sky130_fd_sc_hd__fa) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__fa.nor0_out), line:53:10, endln:53:18 |vpiParent: - \_module: work@sky130_fd_sc_hd__fa (work@sky130_fd_sc_hd__fa), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fa.functional.v, line:33:1, endln:70:10 + \_module_inst: work@sky130_fd_sc_hd__fa (work@sky130_fd_sc_hd__fa), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fa.functional.v, line:33:1, endln:70:10 |vpiTypespec: \_logic_typespec: , line:53:5, endln:53:9 |vpiName:nor0_out @@ -45744,7 +45744,7 @@ design: (work@sky130_fd_sc_hd__fa) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__fa.nor1_out), line:54:10, endln:54:18 |vpiParent: - \_module: work@sky130_fd_sc_hd__fa (work@sky130_fd_sc_hd__fa), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fa.functional.v, line:33:1, endln:70:10 + \_module_inst: work@sky130_fd_sc_hd__fa (work@sky130_fd_sc_hd__fa), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fa.functional.v, line:33:1, endln:70:10 |vpiTypespec: \_logic_typespec: , line:54:5, endln:54:9 |vpiName:nor1_out @@ -45753,7 +45753,7 @@ design: (work@sky130_fd_sc_hd__fa) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__fa.or1_out_COUT), line:55:10, endln:55:22 |vpiParent: - \_module: work@sky130_fd_sc_hd__fa (work@sky130_fd_sc_hd__fa), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fa.functional.v, line:33:1, endln:70:10 + \_module_inst: work@sky130_fd_sc_hd__fa (work@sky130_fd_sc_hd__fa), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fa.functional.v, line:33:1, endln:70:10 |vpiTypespec: \_logic_typespec: , line:55:5, endln:55:9 |vpiName:or1_out_COUT @@ -45762,7 +45762,7 @@ design: (work@sky130_fd_sc_hd__fa) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__fa.or2_out_SUM), line:56:10, endln:56:21 |vpiParent: - \_module: work@sky130_fd_sc_hd__fa (work@sky130_fd_sc_hd__fa), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fa.functional.v, line:33:1, endln:70:10 + \_module_inst: work@sky130_fd_sc_hd__fa (work@sky130_fd_sc_hd__fa), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fa.functional.v, line:33:1, endln:70:10 |vpiTypespec: \_logic_typespec: , line:56:5, endln:56:9 |vpiName:or2_out_SUM @@ -45771,7 +45771,7 @@ design: (work@sky130_fd_sc_hd__fa) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__fa.COUT), line:34:5, endln:34:9 |vpiParent: - \_module: work@sky130_fd_sc_hd__fa (work@sky130_fd_sc_hd__fa), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fa.functional.v, line:33:1, endln:70:10 + \_module_inst: work@sky130_fd_sc_hd__fa (work@sky130_fd_sc_hd__fa), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fa.functional.v, line:33:1, endln:70:10 |vpiTypespec: \_logic_typespec: , line:42:12, endln:42:12 |vpiName:COUT @@ -45779,7 +45779,7 @@ design: (work@sky130_fd_sc_hd__fa) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__fa.SUM), line:35:5, endln:35:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__fa (work@sky130_fd_sc_hd__fa), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fa.functional.v, line:33:1, endln:70:10 + \_module_inst: work@sky130_fd_sc_hd__fa (work@sky130_fd_sc_hd__fa), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fa.functional.v, line:33:1, endln:70:10 |vpiTypespec: \_logic_typespec: , line:43:12, endln:43:12 |vpiName:SUM @@ -45787,7 +45787,7 @@ design: (work@sky130_fd_sc_hd__fa) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__fa.A), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__fa (work@sky130_fd_sc_hd__fa), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fa.functional.v, line:33:1, endln:70:10 + \_module_inst: work@sky130_fd_sc_hd__fa (work@sky130_fd_sc_hd__fa), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fa.functional.v, line:33:1, endln:70:10 |vpiTypespec: \_logic_typespec: , line:44:12, endln:44:12 |vpiName:A @@ -45795,7 +45795,7 @@ design: (work@sky130_fd_sc_hd__fa) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__fa.B), line:37:5, endln:37:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__fa (work@sky130_fd_sc_hd__fa), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fa.functional.v, line:33:1, endln:70:10 + \_module_inst: work@sky130_fd_sc_hd__fa (work@sky130_fd_sc_hd__fa), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fa.functional.v, line:33:1, endln:70:10 |vpiTypespec: \_logic_typespec: , line:45:12, endln:45:12 |vpiName:B @@ -45803,7 +45803,7 @@ design: (work@sky130_fd_sc_hd__fa) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__fa.CIN), line:38:5, endln:38:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__fa (work@sky130_fd_sc_hd__fa), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fa.functional.v, line:33:1, endln:70:10 + \_module_inst: work@sky130_fd_sc_hd__fa (work@sky130_fd_sc_hd__fa), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fa.functional.v, line:33:1, endln:70:10 |vpiTypespec: \_logic_typespec: , line:46:12, endln:46:12 |vpiName:CIN @@ -45812,7 +45812,7 @@ design: (work@sky130_fd_sc_hd__fa) |vpiPort: \_port: (COUT), line:34:5, endln:34:9 |vpiParent: - \_module: work@sky130_fd_sc_hd__fa (work@sky130_fd_sc_hd__fa), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fa.functional.v, line:33:1, endln:70:10 + \_module_inst: work@sky130_fd_sc_hd__fa (work@sky130_fd_sc_hd__fa), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fa.functional.v, line:33:1, endln:70:10 |vpiName:COUT |vpiDirection:2 |vpiLowConn: @@ -45826,7 +45826,7 @@ design: (work@sky130_fd_sc_hd__fa) |vpiPort: \_port: (SUM), line:35:5, endln:35:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__fa (work@sky130_fd_sc_hd__fa), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fa.functional.v, line:33:1, endln:70:10 + \_module_inst: work@sky130_fd_sc_hd__fa (work@sky130_fd_sc_hd__fa), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fa.functional.v, line:33:1, endln:70:10 |vpiName:SUM |vpiDirection:2 |vpiLowConn: @@ -45840,7 +45840,7 @@ design: (work@sky130_fd_sc_hd__fa) |vpiPort: \_port: (A), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__fa (work@sky130_fd_sc_hd__fa), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fa.functional.v, line:33:1, endln:70:10 + \_module_inst: work@sky130_fd_sc_hd__fa (work@sky130_fd_sc_hd__fa), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fa.functional.v, line:33:1, endln:70:10 |vpiName:A |vpiDirection:1 |vpiLowConn: @@ -45854,7 +45854,7 @@ design: (work@sky130_fd_sc_hd__fa) |vpiPort: \_port: (B), line:37:5, endln:37:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__fa (work@sky130_fd_sc_hd__fa), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fa.functional.v, line:33:1, endln:70:10 + \_module_inst: work@sky130_fd_sc_hd__fa (work@sky130_fd_sc_hd__fa), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fa.functional.v, line:33:1, endln:70:10 |vpiName:B |vpiDirection:1 |vpiLowConn: @@ -45868,7 +45868,7 @@ design: (work@sky130_fd_sc_hd__fa) |vpiPort: \_port: (CIN), line:38:5, endln:38:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__fa (work@sky130_fd_sc_hd__fa), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fa.functional.v, line:33:1, endln:70:10 + \_module_inst: work@sky130_fd_sc_hd__fa (work@sky130_fd_sc_hd__fa), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fa.functional.v, line:33:1, endln:70:10 |vpiName:CIN |vpiDirection:1 |vpiLowConn: @@ -45882,7 +45882,7 @@ design: (work@sky130_fd_sc_hd__fa) |vpiPrimitive: \_gate: work@or (work@sky130_fd_sc_hd__fa.or0), line:59:9, endln:59:48 |vpiParent: - \_module: work@sky130_fd_sc_hd__fa (work@sky130_fd_sc_hd__fa), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fa.functional.v, line:33:1, endln:70:10 + \_module_inst: work@sky130_fd_sc_hd__fa (work@sky130_fd_sc_hd__fa), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fa.functional.v, line:33:1, endln:70:10 |vpiDefName:work@or |vpiName:or0 |vpiFullName:work@sky130_fd_sc_hd__fa.or0 @@ -45931,7 +45931,7 @@ design: (work@sky130_fd_sc_hd__fa) |vpiPrimitive: \_gate: work@and (work@sky130_fd_sc_hd__fa.and0), line:60:9, endln:60:48 |vpiParent: - \_module: work@sky130_fd_sc_hd__fa (work@sky130_fd_sc_hd__fa), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fa.functional.v, line:33:1, endln:70:10 + \_module_inst: work@sky130_fd_sc_hd__fa (work@sky130_fd_sc_hd__fa), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fa.functional.v, line:33:1, endln:70:10 |vpiDefName:work@and |vpiName:and0 |vpiFullName:work@sky130_fd_sc_hd__fa.and0 @@ -45980,7 +45980,7 @@ design: (work@sky130_fd_sc_hd__fa) |vpiPrimitive: \_gate: work@and (work@sky130_fd_sc_hd__fa.and1), line:61:9, endln:61:48 |vpiParent: - \_module: work@sky130_fd_sc_hd__fa (work@sky130_fd_sc_hd__fa), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fa.functional.v, line:33:1, endln:70:10 + \_module_inst: work@sky130_fd_sc_hd__fa (work@sky130_fd_sc_hd__fa), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fa.functional.v, line:33:1, endln:70:10 |vpiDefName:work@and |vpiName:and1 |vpiFullName:work@sky130_fd_sc_hd__fa.and1 @@ -46029,7 +46029,7 @@ design: (work@sky130_fd_sc_hd__fa) |vpiPrimitive: \_gate: work@or (work@sky130_fd_sc_hd__fa.or1), line:62:9, endln:62:48 |vpiParent: - \_module: work@sky130_fd_sc_hd__fa (work@sky130_fd_sc_hd__fa), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fa.functional.v, line:33:1, endln:70:10 + \_module_inst: work@sky130_fd_sc_hd__fa (work@sky130_fd_sc_hd__fa), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fa.functional.v, line:33:1, endln:70:10 |vpiDefName:work@or |vpiName:or1 |vpiFullName:work@sky130_fd_sc_hd__fa.or1 @@ -46078,7 +46078,7 @@ design: (work@sky130_fd_sc_hd__fa) |vpiPrimitive: \_gate: work@buf (work@sky130_fd_sc_hd__fa.buf0), line:63:9, endln:63:48 |vpiParent: - \_module: work@sky130_fd_sc_hd__fa (work@sky130_fd_sc_hd__fa), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fa.functional.v, line:33:1, endln:70:10 + \_module_inst: work@sky130_fd_sc_hd__fa (work@sky130_fd_sc_hd__fa), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fa.functional.v, line:33:1, endln:70:10 |vpiDefName:work@buf |vpiName:buf0 |vpiFullName:work@sky130_fd_sc_hd__fa.buf0 @@ -46113,7 +46113,7 @@ design: (work@sky130_fd_sc_hd__fa) |vpiPrimitive: \_gate: work@and (work@sky130_fd_sc_hd__fa.and2), line:64:9, endln:64:48 |vpiParent: - \_module: work@sky130_fd_sc_hd__fa (work@sky130_fd_sc_hd__fa), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fa.functional.v, line:33:1, endln:70:10 + \_module_inst: work@sky130_fd_sc_hd__fa (work@sky130_fd_sc_hd__fa), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fa.functional.v, line:33:1, endln:70:10 |vpiDefName:work@and |vpiName:and2 |vpiFullName:work@sky130_fd_sc_hd__fa.and2 @@ -46176,7 +46176,7 @@ design: (work@sky130_fd_sc_hd__fa) |vpiPrimitive: \_gate: work@nor (work@sky130_fd_sc_hd__fa.nor0), line:65:9, endln:65:48 |vpiParent: - \_module: work@sky130_fd_sc_hd__fa (work@sky130_fd_sc_hd__fa), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fa.functional.v, line:33:1, endln:70:10 + \_module_inst: work@sky130_fd_sc_hd__fa (work@sky130_fd_sc_hd__fa), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fa.functional.v, line:33:1, endln:70:10 |vpiDefName:work@nor |vpiName:nor0 |vpiFullName:work@sky130_fd_sc_hd__fa.nor0 @@ -46225,7 +46225,7 @@ design: (work@sky130_fd_sc_hd__fa) |vpiPrimitive: \_gate: work@nor (work@sky130_fd_sc_hd__fa.nor1), line:66:9, endln:66:48 |vpiParent: - \_module: work@sky130_fd_sc_hd__fa (work@sky130_fd_sc_hd__fa), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fa.functional.v, line:33:1, endln:70:10 + \_module_inst: work@sky130_fd_sc_hd__fa (work@sky130_fd_sc_hd__fa), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fa.functional.v, line:33:1, endln:70:10 |vpiDefName:work@nor |vpiName:nor1 |vpiFullName:work@sky130_fd_sc_hd__fa.nor1 @@ -46274,7 +46274,7 @@ design: (work@sky130_fd_sc_hd__fa) |vpiPrimitive: \_gate: work@or (work@sky130_fd_sc_hd__fa.or2), line:67:9, endln:67:48 |vpiParent: - \_module: work@sky130_fd_sc_hd__fa (work@sky130_fd_sc_hd__fa), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fa.functional.v, line:33:1, endln:70:10 + \_module_inst: work@sky130_fd_sc_hd__fa (work@sky130_fd_sc_hd__fa), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fa.functional.v, line:33:1, endln:70:10 |vpiDefName:work@or |vpiName:or2 |vpiFullName:work@sky130_fd_sc_hd__fa.or2 @@ -46323,7 +46323,7 @@ design: (work@sky130_fd_sc_hd__fa) |vpiPrimitive: \_gate: work@buf (work@sky130_fd_sc_hd__fa.buf1), line:68:9, endln:68:48 |vpiParent: - \_module: work@sky130_fd_sc_hd__fa (work@sky130_fd_sc_hd__fa), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fa.functional.v, line:33:1, endln:70:10 + \_module_inst: work@sky130_fd_sc_hd__fa (work@sky130_fd_sc_hd__fa), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fa.functional.v, line:33:1, endln:70:10 |vpiDefName:work@buf |vpiName:buf1 |vpiFullName:work@sky130_fd_sc_hd__fa.buf1 @@ -46366,7 +46366,7 @@ Processing: -cd cells/cells -DUNIT_DELAY -writepp -parse -nocache -nobuiltin -no design: (work@sky130_fd_sc_hd__a31oi) |vpiName:work@sky130_fd_sc_hd__a31oi |uhdmallModules: -\_module: work@sky130_fd_sc_hd__a31oi (work@sky130_fd_sc_hd__a31oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a31oi.functional.v, line:35:1, endln:59:10 +\_module_inst: work@sky130_fd_sc_hd__a31oi (work@sky130_fd_sc_hd__a31oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a31oi.functional.v, line:35:1, endln:59:10 |vpiParent: \_design: (work@sky130_fd_sc_hd__a31oi) |vpiFullName:work@sky130_fd_sc_hd__a31oi @@ -46374,51 +46374,51 @@ design: (work@sky130_fd_sc_hd__a31oi) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a31oi.and0_out), line:51:10, endln:51:18 |vpiParent: - \_module: work@sky130_fd_sc_hd__a31oi (work@sky130_fd_sc_hd__a31oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a31oi.functional.v, line:35:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__a31oi (work@sky130_fd_sc_hd__a31oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a31oi.functional.v, line:35:1, endln:59:10 |vpiName:and0_out |vpiFullName:work@sky130_fd_sc_hd__a31oi.and0_out |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a31oi.nor0_out_Y), line:52:10, endln:52:20 |vpiParent: - \_module: work@sky130_fd_sc_hd__a31oi (work@sky130_fd_sc_hd__a31oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a31oi.functional.v, line:35:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__a31oi (work@sky130_fd_sc_hd__a31oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a31oi.functional.v, line:35:1, endln:59:10 |vpiName:nor0_out_Y |vpiFullName:work@sky130_fd_sc_hd__a31oi.nor0_out_Y |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a31oi.Y), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__a31oi (work@sky130_fd_sc_hd__a31oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a31oi.functional.v, line:35:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__a31oi (work@sky130_fd_sc_hd__a31oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a31oi.functional.v, line:35:1, endln:59:10 |vpiName:Y |vpiFullName:work@sky130_fd_sc_hd__a31oi.Y |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a31oi.A1), line:37:5, endln:37:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a31oi (work@sky130_fd_sc_hd__a31oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a31oi.functional.v, line:35:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__a31oi (work@sky130_fd_sc_hd__a31oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a31oi.functional.v, line:35:1, endln:59:10 |vpiName:A1 |vpiFullName:work@sky130_fd_sc_hd__a31oi.A1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a31oi.A2), line:38:5, endln:38:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a31oi (work@sky130_fd_sc_hd__a31oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a31oi.functional.v, line:35:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__a31oi (work@sky130_fd_sc_hd__a31oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a31oi.functional.v, line:35:1, endln:59:10 |vpiName:A2 |vpiFullName:work@sky130_fd_sc_hd__a31oi.A2 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a31oi.A3), line:39:5, endln:39:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a31oi (work@sky130_fd_sc_hd__a31oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a31oi.functional.v, line:35:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__a31oi (work@sky130_fd_sc_hd__a31oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a31oi.functional.v, line:35:1, endln:59:10 |vpiName:A3 |vpiFullName:work@sky130_fd_sc_hd__a31oi.A3 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a31oi.B1), line:40:5, endln:40:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a31oi (work@sky130_fd_sc_hd__a31oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a31oi.functional.v, line:35:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__a31oi (work@sky130_fd_sc_hd__a31oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a31oi.functional.v, line:35:1, endln:59:10 |vpiName:B1 |vpiFullName:work@sky130_fd_sc_hd__a31oi.B1 |vpiPort: \_port: (Y), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__a31oi (work@sky130_fd_sc_hd__a31oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a31oi.functional.v, line:35:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__a31oi (work@sky130_fd_sc_hd__a31oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a31oi.functional.v, line:35:1, endln:59:10 |vpiName:Y |vpiDirection:2 |vpiLowConn: @@ -46430,7 +46430,7 @@ design: (work@sky130_fd_sc_hd__a31oi) |vpiPort: \_port: (A1), line:37:5, endln:37:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a31oi (work@sky130_fd_sc_hd__a31oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a31oi.functional.v, line:35:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__a31oi (work@sky130_fd_sc_hd__a31oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a31oi.functional.v, line:35:1, endln:59:10 |vpiName:A1 |vpiDirection:1 |vpiLowConn: @@ -46442,7 +46442,7 @@ design: (work@sky130_fd_sc_hd__a31oi) |vpiPort: \_port: (A2), line:38:5, endln:38:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a31oi (work@sky130_fd_sc_hd__a31oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a31oi.functional.v, line:35:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__a31oi (work@sky130_fd_sc_hd__a31oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a31oi.functional.v, line:35:1, endln:59:10 |vpiName:A2 |vpiDirection:1 |vpiLowConn: @@ -46454,7 +46454,7 @@ design: (work@sky130_fd_sc_hd__a31oi) |vpiPort: \_port: (A3), line:39:5, endln:39:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a31oi (work@sky130_fd_sc_hd__a31oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a31oi.functional.v, line:35:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__a31oi (work@sky130_fd_sc_hd__a31oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a31oi.functional.v, line:35:1, endln:59:10 |vpiName:A3 |vpiDirection:1 |vpiLowConn: @@ -46466,7 +46466,7 @@ design: (work@sky130_fd_sc_hd__a31oi) |vpiPort: \_port: (B1), line:40:5, endln:40:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a31oi (work@sky130_fd_sc_hd__a31oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a31oi.functional.v, line:35:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__a31oi (work@sky130_fd_sc_hd__a31oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a31oi.functional.v, line:35:1, endln:59:10 |vpiName:B1 |vpiDirection:1 |vpiLowConn: @@ -46476,14 +46476,14 @@ design: (work@sky130_fd_sc_hd__a31oi) |vpiTypedef: \_logic_typespec: , line:48:12, endln:48:12 |uhdmtopModules: -\_module: work@sky130_fd_sc_hd__a31oi (work@sky130_fd_sc_hd__a31oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a31oi.functional.v, line:35:1, endln:59:10 +\_module_inst: work@sky130_fd_sc_hd__a31oi (work@sky130_fd_sc_hd__a31oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a31oi.functional.v, line:35:1, endln:59:10 |vpiName:work@sky130_fd_sc_hd__a31oi |vpiDefName:work@sky130_fd_sc_hd__a31oi |vpiTop:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a31oi.and0_out), line:51:10, endln:51:18 |vpiParent: - \_module: work@sky130_fd_sc_hd__a31oi (work@sky130_fd_sc_hd__a31oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a31oi.functional.v, line:35:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__a31oi (work@sky130_fd_sc_hd__a31oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a31oi.functional.v, line:35:1, endln:59:10 |vpiTypespec: \_logic_typespec: , line:51:5, endln:51:9 |vpiName:and0_out @@ -46492,7 +46492,7 @@ design: (work@sky130_fd_sc_hd__a31oi) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a31oi.nor0_out_Y), line:52:10, endln:52:20 |vpiParent: - \_module: work@sky130_fd_sc_hd__a31oi (work@sky130_fd_sc_hd__a31oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a31oi.functional.v, line:35:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__a31oi (work@sky130_fd_sc_hd__a31oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a31oi.functional.v, line:35:1, endln:59:10 |vpiTypespec: \_logic_typespec: , line:52:5, endln:52:9 |vpiName:nor0_out_Y @@ -46501,7 +46501,7 @@ design: (work@sky130_fd_sc_hd__a31oi) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a31oi.Y), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__a31oi (work@sky130_fd_sc_hd__a31oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a31oi.functional.v, line:35:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__a31oi (work@sky130_fd_sc_hd__a31oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a31oi.functional.v, line:35:1, endln:59:10 |vpiTypespec: \_logic_typespec: , line:44:12, endln:44:12 |vpiName:Y @@ -46509,7 +46509,7 @@ design: (work@sky130_fd_sc_hd__a31oi) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a31oi.A1), line:37:5, endln:37:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a31oi (work@sky130_fd_sc_hd__a31oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a31oi.functional.v, line:35:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__a31oi (work@sky130_fd_sc_hd__a31oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a31oi.functional.v, line:35:1, endln:59:10 |vpiTypespec: \_logic_typespec: , line:45:12, endln:45:12 |vpiName:A1 @@ -46517,7 +46517,7 @@ design: (work@sky130_fd_sc_hd__a31oi) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a31oi.A2), line:38:5, endln:38:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a31oi (work@sky130_fd_sc_hd__a31oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a31oi.functional.v, line:35:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__a31oi (work@sky130_fd_sc_hd__a31oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a31oi.functional.v, line:35:1, endln:59:10 |vpiTypespec: \_logic_typespec: , line:46:12, endln:46:12 |vpiName:A2 @@ -46525,7 +46525,7 @@ design: (work@sky130_fd_sc_hd__a31oi) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a31oi.A3), line:39:5, endln:39:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a31oi (work@sky130_fd_sc_hd__a31oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a31oi.functional.v, line:35:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__a31oi (work@sky130_fd_sc_hd__a31oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a31oi.functional.v, line:35:1, endln:59:10 |vpiTypespec: \_logic_typespec: , line:47:12, endln:47:12 |vpiName:A3 @@ -46533,7 +46533,7 @@ design: (work@sky130_fd_sc_hd__a31oi) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a31oi.B1), line:40:5, endln:40:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a31oi (work@sky130_fd_sc_hd__a31oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a31oi.functional.v, line:35:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__a31oi (work@sky130_fd_sc_hd__a31oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a31oi.functional.v, line:35:1, endln:59:10 |vpiTypespec: \_logic_typespec: , line:48:12, endln:48:12 |vpiName:B1 @@ -46542,7 +46542,7 @@ design: (work@sky130_fd_sc_hd__a31oi) |vpiPort: \_port: (Y), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__a31oi (work@sky130_fd_sc_hd__a31oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a31oi.functional.v, line:35:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__a31oi (work@sky130_fd_sc_hd__a31oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a31oi.functional.v, line:35:1, endln:59:10 |vpiName:Y |vpiDirection:2 |vpiLowConn: @@ -46556,7 +46556,7 @@ design: (work@sky130_fd_sc_hd__a31oi) |vpiPort: \_port: (A1), line:37:5, endln:37:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a31oi (work@sky130_fd_sc_hd__a31oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a31oi.functional.v, line:35:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__a31oi (work@sky130_fd_sc_hd__a31oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a31oi.functional.v, line:35:1, endln:59:10 |vpiName:A1 |vpiDirection:1 |vpiLowConn: @@ -46570,7 +46570,7 @@ design: (work@sky130_fd_sc_hd__a31oi) |vpiPort: \_port: (A2), line:38:5, endln:38:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a31oi (work@sky130_fd_sc_hd__a31oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a31oi.functional.v, line:35:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__a31oi (work@sky130_fd_sc_hd__a31oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a31oi.functional.v, line:35:1, endln:59:10 |vpiName:A2 |vpiDirection:1 |vpiLowConn: @@ -46584,7 +46584,7 @@ design: (work@sky130_fd_sc_hd__a31oi) |vpiPort: \_port: (A3), line:39:5, endln:39:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a31oi (work@sky130_fd_sc_hd__a31oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a31oi.functional.v, line:35:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__a31oi (work@sky130_fd_sc_hd__a31oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a31oi.functional.v, line:35:1, endln:59:10 |vpiName:A3 |vpiDirection:1 |vpiLowConn: @@ -46598,7 +46598,7 @@ design: (work@sky130_fd_sc_hd__a31oi) |vpiPort: \_port: (B1), line:40:5, endln:40:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a31oi (work@sky130_fd_sc_hd__a31oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a31oi.functional.v, line:35:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__a31oi (work@sky130_fd_sc_hd__a31oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a31oi.functional.v, line:35:1, endln:59:10 |vpiName:B1 |vpiDirection:1 |vpiLowConn: @@ -46612,7 +46612,7 @@ design: (work@sky130_fd_sc_hd__a31oi) |vpiPrimitive: \_gate: work@and (work@sky130_fd_sc_hd__a31oi.and0), line:55:9, endln:55:43 |vpiParent: - \_module: work@sky130_fd_sc_hd__a31oi (work@sky130_fd_sc_hd__a31oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a31oi.functional.v, line:35:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__a31oi (work@sky130_fd_sc_hd__a31oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a31oi.functional.v, line:35:1, endln:59:10 |vpiDefName:work@and |vpiName:and0 |vpiFullName:work@sky130_fd_sc_hd__a31oi.and0 @@ -46675,7 +46675,7 @@ design: (work@sky130_fd_sc_hd__a31oi) |vpiPrimitive: \_gate: work@nor (work@sky130_fd_sc_hd__a31oi.nor0), line:56:9, endln:56:43 |vpiParent: - \_module: work@sky130_fd_sc_hd__a31oi (work@sky130_fd_sc_hd__a31oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a31oi.functional.v, line:35:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__a31oi (work@sky130_fd_sc_hd__a31oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a31oi.functional.v, line:35:1, endln:59:10 |vpiDefName:work@nor |vpiName:nor0 |vpiFullName:work@sky130_fd_sc_hd__a31oi.nor0 @@ -46724,7 +46724,7 @@ design: (work@sky130_fd_sc_hd__a31oi) |vpiPrimitive: \_gate: work@buf (work@sky130_fd_sc_hd__a31oi.buf0), line:57:9, endln:57:43 |vpiParent: - \_module: work@sky130_fd_sc_hd__a31oi (work@sky130_fd_sc_hd__a31oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a31oi.functional.v, line:35:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__a31oi (work@sky130_fd_sc_hd__a31oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a31oi.functional.v, line:35:1, endln:59:10 |vpiDefName:work@buf |vpiName:buf0 |vpiFullName:work@sky130_fd_sc_hd__a31oi.buf0 @@ -46767,7 +46767,7 @@ Processing: -cd cells/cells -DUNIT_DELAY -writepp -parse -nocache -nobuiltin -no design: (work@sky130_fd_sc_hd__nor2b) |vpiName:work@sky130_fd_sc_hd__nor2b |uhdmallModules: -\_module: work@sky130_fd_sc_hd__nor2b (work@sky130_fd_sc_hd__nor2b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor2b.functional.v, line:35:1, endln:55:10 +\_module_inst: work@sky130_fd_sc_hd__nor2b (work@sky130_fd_sc_hd__nor2b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor2b.functional.v, line:35:1, endln:55:10 |vpiParent: \_design: (work@sky130_fd_sc_hd__nor2b) |vpiFullName:work@sky130_fd_sc_hd__nor2b @@ -46775,39 +46775,39 @@ design: (work@sky130_fd_sc_hd__nor2b) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__nor2b.not0_out), line:47:10, endln:47:18 |vpiParent: - \_module: work@sky130_fd_sc_hd__nor2b (work@sky130_fd_sc_hd__nor2b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor2b.functional.v, line:35:1, endln:55:10 + \_module_inst: work@sky130_fd_sc_hd__nor2b (work@sky130_fd_sc_hd__nor2b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor2b.functional.v, line:35:1, endln:55:10 |vpiName:not0_out |vpiFullName:work@sky130_fd_sc_hd__nor2b.not0_out |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__nor2b.and0_out_Y), line:48:10, endln:48:20 |vpiParent: - \_module: work@sky130_fd_sc_hd__nor2b (work@sky130_fd_sc_hd__nor2b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor2b.functional.v, line:35:1, endln:55:10 + \_module_inst: work@sky130_fd_sc_hd__nor2b (work@sky130_fd_sc_hd__nor2b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor2b.functional.v, line:35:1, endln:55:10 |vpiName:and0_out_Y |vpiFullName:work@sky130_fd_sc_hd__nor2b.and0_out_Y |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__nor2b.Y), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__nor2b (work@sky130_fd_sc_hd__nor2b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor2b.functional.v, line:35:1, endln:55:10 + \_module_inst: work@sky130_fd_sc_hd__nor2b (work@sky130_fd_sc_hd__nor2b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor2b.functional.v, line:35:1, endln:55:10 |vpiName:Y |vpiFullName:work@sky130_fd_sc_hd__nor2b.Y |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__nor2b.A), line:37:5, endln:37:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__nor2b (work@sky130_fd_sc_hd__nor2b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor2b.functional.v, line:35:1, endln:55:10 + \_module_inst: work@sky130_fd_sc_hd__nor2b (work@sky130_fd_sc_hd__nor2b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor2b.functional.v, line:35:1, endln:55:10 |vpiName:A |vpiFullName:work@sky130_fd_sc_hd__nor2b.A |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__nor2b.B_N), line:38:5, endln:38:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__nor2b (work@sky130_fd_sc_hd__nor2b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor2b.functional.v, line:35:1, endln:55:10 + \_module_inst: work@sky130_fd_sc_hd__nor2b (work@sky130_fd_sc_hd__nor2b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor2b.functional.v, line:35:1, endln:55:10 |vpiName:B_N |vpiFullName:work@sky130_fd_sc_hd__nor2b.B_N |vpiPort: \_port: (Y), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__nor2b (work@sky130_fd_sc_hd__nor2b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor2b.functional.v, line:35:1, endln:55:10 + \_module_inst: work@sky130_fd_sc_hd__nor2b (work@sky130_fd_sc_hd__nor2b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor2b.functional.v, line:35:1, endln:55:10 |vpiName:Y |vpiDirection:2 |vpiLowConn: @@ -46819,7 +46819,7 @@ design: (work@sky130_fd_sc_hd__nor2b) |vpiPort: \_port: (A), line:37:5, endln:37:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__nor2b (work@sky130_fd_sc_hd__nor2b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor2b.functional.v, line:35:1, endln:55:10 + \_module_inst: work@sky130_fd_sc_hd__nor2b (work@sky130_fd_sc_hd__nor2b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor2b.functional.v, line:35:1, endln:55:10 |vpiName:A |vpiDirection:1 |vpiLowConn: @@ -46831,7 +46831,7 @@ design: (work@sky130_fd_sc_hd__nor2b) |vpiPort: \_port: (B_N), line:38:5, endln:38:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__nor2b (work@sky130_fd_sc_hd__nor2b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor2b.functional.v, line:35:1, endln:55:10 + \_module_inst: work@sky130_fd_sc_hd__nor2b (work@sky130_fd_sc_hd__nor2b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor2b.functional.v, line:35:1, endln:55:10 |vpiName:B_N |vpiDirection:1 |vpiLowConn: @@ -46841,14 +46841,14 @@ design: (work@sky130_fd_sc_hd__nor2b) |vpiTypedef: \_logic_typespec: , line:44:12, endln:44:12 |uhdmtopModules: -\_module: work@sky130_fd_sc_hd__nor2b (work@sky130_fd_sc_hd__nor2b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor2b.functional.v, line:35:1, endln:55:10 +\_module_inst: work@sky130_fd_sc_hd__nor2b (work@sky130_fd_sc_hd__nor2b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor2b.functional.v, line:35:1, endln:55:10 |vpiName:work@sky130_fd_sc_hd__nor2b |vpiDefName:work@sky130_fd_sc_hd__nor2b |vpiTop:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__nor2b.not0_out), line:47:10, endln:47:18 |vpiParent: - \_module: work@sky130_fd_sc_hd__nor2b (work@sky130_fd_sc_hd__nor2b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor2b.functional.v, line:35:1, endln:55:10 + \_module_inst: work@sky130_fd_sc_hd__nor2b (work@sky130_fd_sc_hd__nor2b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor2b.functional.v, line:35:1, endln:55:10 |vpiTypespec: \_logic_typespec: , line:47:5, endln:47:9 |vpiName:not0_out @@ -46857,7 +46857,7 @@ design: (work@sky130_fd_sc_hd__nor2b) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__nor2b.and0_out_Y), line:48:10, endln:48:20 |vpiParent: - \_module: work@sky130_fd_sc_hd__nor2b (work@sky130_fd_sc_hd__nor2b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor2b.functional.v, line:35:1, endln:55:10 + \_module_inst: work@sky130_fd_sc_hd__nor2b (work@sky130_fd_sc_hd__nor2b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor2b.functional.v, line:35:1, endln:55:10 |vpiTypespec: \_logic_typespec: , line:48:5, endln:48:9 |vpiName:and0_out_Y @@ -46866,7 +46866,7 @@ design: (work@sky130_fd_sc_hd__nor2b) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__nor2b.Y), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__nor2b (work@sky130_fd_sc_hd__nor2b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor2b.functional.v, line:35:1, endln:55:10 + \_module_inst: work@sky130_fd_sc_hd__nor2b (work@sky130_fd_sc_hd__nor2b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor2b.functional.v, line:35:1, endln:55:10 |vpiTypespec: \_logic_typespec: , line:42:12, endln:42:12 |vpiName:Y @@ -46874,7 +46874,7 @@ design: (work@sky130_fd_sc_hd__nor2b) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__nor2b.A), line:37:5, endln:37:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__nor2b (work@sky130_fd_sc_hd__nor2b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor2b.functional.v, line:35:1, endln:55:10 + \_module_inst: work@sky130_fd_sc_hd__nor2b (work@sky130_fd_sc_hd__nor2b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor2b.functional.v, line:35:1, endln:55:10 |vpiTypespec: \_logic_typespec: , line:43:12, endln:43:12 |vpiName:A @@ -46882,7 +46882,7 @@ design: (work@sky130_fd_sc_hd__nor2b) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__nor2b.B_N), line:38:5, endln:38:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__nor2b (work@sky130_fd_sc_hd__nor2b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor2b.functional.v, line:35:1, endln:55:10 + \_module_inst: work@sky130_fd_sc_hd__nor2b (work@sky130_fd_sc_hd__nor2b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor2b.functional.v, line:35:1, endln:55:10 |vpiTypespec: \_logic_typespec: , line:44:12, endln:44:12 |vpiName:B_N @@ -46891,7 +46891,7 @@ design: (work@sky130_fd_sc_hd__nor2b) |vpiPort: \_port: (Y), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__nor2b (work@sky130_fd_sc_hd__nor2b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor2b.functional.v, line:35:1, endln:55:10 + \_module_inst: work@sky130_fd_sc_hd__nor2b (work@sky130_fd_sc_hd__nor2b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor2b.functional.v, line:35:1, endln:55:10 |vpiName:Y |vpiDirection:2 |vpiLowConn: @@ -46905,7 +46905,7 @@ design: (work@sky130_fd_sc_hd__nor2b) |vpiPort: \_port: (A), line:37:5, endln:37:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__nor2b (work@sky130_fd_sc_hd__nor2b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor2b.functional.v, line:35:1, endln:55:10 + \_module_inst: work@sky130_fd_sc_hd__nor2b (work@sky130_fd_sc_hd__nor2b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor2b.functional.v, line:35:1, endln:55:10 |vpiName:A |vpiDirection:1 |vpiLowConn: @@ -46919,7 +46919,7 @@ design: (work@sky130_fd_sc_hd__nor2b) |vpiPort: \_port: (B_N), line:38:5, endln:38:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__nor2b (work@sky130_fd_sc_hd__nor2b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor2b.functional.v, line:35:1, endln:55:10 + \_module_inst: work@sky130_fd_sc_hd__nor2b (work@sky130_fd_sc_hd__nor2b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor2b.functional.v, line:35:1, endln:55:10 |vpiName:B_N |vpiDirection:1 |vpiLowConn: @@ -46933,7 +46933,7 @@ design: (work@sky130_fd_sc_hd__nor2b) |vpiPrimitive: \_gate: work@not (work@sky130_fd_sc_hd__nor2b.not0), line:51:9, endln:51:43 |vpiParent: - \_module: work@sky130_fd_sc_hd__nor2b (work@sky130_fd_sc_hd__nor2b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor2b.functional.v, line:35:1, endln:55:10 + \_module_inst: work@sky130_fd_sc_hd__nor2b (work@sky130_fd_sc_hd__nor2b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor2b.functional.v, line:35:1, endln:55:10 |vpiDefName:work@not |vpiName:not0 |vpiFullName:work@sky130_fd_sc_hd__nor2b.not0 @@ -46968,7 +46968,7 @@ design: (work@sky130_fd_sc_hd__nor2b) |vpiPrimitive: \_gate: work@and (work@sky130_fd_sc_hd__nor2b.and0), line:52:9, endln:52:43 |vpiParent: - \_module: work@sky130_fd_sc_hd__nor2b (work@sky130_fd_sc_hd__nor2b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor2b.functional.v, line:35:1, endln:55:10 + \_module_inst: work@sky130_fd_sc_hd__nor2b (work@sky130_fd_sc_hd__nor2b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor2b.functional.v, line:35:1, endln:55:10 |vpiDefName:work@and |vpiName:and0 |vpiFullName:work@sky130_fd_sc_hd__nor2b.and0 @@ -47017,7 +47017,7 @@ design: (work@sky130_fd_sc_hd__nor2b) |vpiPrimitive: \_gate: work@buf (work@sky130_fd_sc_hd__nor2b.buf0), line:53:9, endln:53:43 |vpiParent: - \_module: work@sky130_fd_sc_hd__nor2b (work@sky130_fd_sc_hd__nor2b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor2b.functional.v, line:35:1, endln:55:10 + \_module_inst: work@sky130_fd_sc_hd__nor2b (work@sky130_fd_sc_hd__nor2b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor2b.functional.v, line:35:1, endln:55:10 |vpiDefName:work@buf |vpiName:buf0 |vpiFullName:work@sky130_fd_sc_hd__nor2b.buf0 @@ -47060,7 +47060,7 @@ Processing: -cd cells/cells -DUNIT_DELAY -writepp -parse -nocache -nobuiltin -no design: (work@sky130_fd_sc_hd__ebufn) |vpiName:work@sky130_fd_sc_hd__ebufn |uhdmallModules: -\_module: work@sky130_fd_sc_hd__ebufn (work@sky130_fd_sc_hd__ebufn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__ebufn.functional.v, line:33:1, endln:47:10 +\_module_inst: work@sky130_fd_sc_hd__ebufn (work@sky130_fd_sc_hd__ebufn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__ebufn.functional.v, line:33:1, endln:47:10 |vpiParent: \_design: (work@sky130_fd_sc_hd__ebufn) |vpiFullName:work@sky130_fd_sc_hd__ebufn @@ -47068,25 +47068,25 @@ design: (work@sky130_fd_sc_hd__ebufn) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__ebufn.Z), line:34:5, endln:34:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__ebufn (work@sky130_fd_sc_hd__ebufn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__ebufn.functional.v, line:33:1, endln:47:10 + \_module_inst: work@sky130_fd_sc_hd__ebufn (work@sky130_fd_sc_hd__ebufn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__ebufn.functional.v, line:33:1, endln:47:10 |vpiName:Z |vpiFullName:work@sky130_fd_sc_hd__ebufn.Z |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__ebufn.A), line:35:5, endln:35:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__ebufn (work@sky130_fd_sc_hd__ebufn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__ebufn.functional.v, line:33:1, endln:47:10 + \_module_inst: work@sky130_fd_sc_hd__ebufn (work@sky130_fd_sc_hd__ebufn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__ebufn.functional.v, line:33:1, endln:47:10 |vpiName:A |vpiFullName:work@sky130_fd_sc_hd__ebufn.A |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__ebufn.TE_B), line:36:5, endln:36:9 |vpiParent: - \_module: work@sky130_fd_sc_hd__ebufn (work@sky130_fd_sc_hd__ebufn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__ebufn.functional.v, line:33:1, endln:47:10 + \_module_inst: work@sky130_fd_sc_hd__ebufn (work@sky130_fd_sc_hd__ebufn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__ebufn.functional.v, line:33:1, endln:47:10 |vpiName:TE_B |vpiFullName:work@sky130_fd_sc_hd__ebufn.TE_B |vpiPort: \_port: (Z), line:34:5, endln:34:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__ebufn (work@sky130_fd_sc_hd__ebufn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__ebufn.functional.v, line:33:1, endln:47:10 + \_module_inst: work@sky130_fd_sc_hd__ebufn (work@sky130_fd_sc_hd__ebufn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__ebufn.functional.v, line:33:1, endln:47:10 |vpiName:Z |vpiDirection:2 |vpiLowConn: @@ -47098,7 +47098,7 @@ design: (work@sky130_fd_sc_hd__ebufn) |vpiPort: \_port: (A), line:35:5, endln:35:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__ebufn (work@sky130_fd_sc_hd__ebufn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__ebufn.functional.v, line:33:1, endln:47:10 + \_module_inst: work@sky130_fd_sc_hd__ebufn (work@sky130_fd_sc_hd__ebufn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__ebufn.functional.v, line:33:1, endln:47:10 |vpiName:A |vpiDirection:1 |vpiLowConn: @@ -47110,7 +47110,7 @@ design: (work@sky130_fd_sc_hd__ebufn) |vpiPort: \_port: (TE_B), line:36:5, endln:36:9 |vpiParent: - \_module: work@sky130_fd_sc_hd__ebufn (work@sky130_fd_sc_hd__ebufn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__ebufn.functional.v, line:33:1, endln:47:10 + \_module_inst: work@sky130_fd_sc_hd__ebufn (work@sky130_fd_sc_hd__ebufn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__ebufn.functional.v, line:33:1, endln:47:10 |vpiName:TE_B |vpiDirection:1 |vpiLowConn: @@ -47120,14 +47120,14 @@ design: (work@sky130_fd_sc_hd__ebufn) |vpiTypedef: \_logic_typespec: , line:42:12, endln:42:12 |uhdmtopModules: -\_module: work@sky130_fd_sc_hd__ebufn (work@sky130_fd_sc_hd__ebufn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__ebufn.functional.v, line:33:1, endln:47:10 +\_module_inst: work@sky130_fd_sc_hd__ebufn (work@sky130_fd_sc_hd__ebufn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__ebufn.functional.v, line:33:1, endln:47:10 |vpiName:work@sky130_fd_sc_hd__ebufn |vpiDefName:work@sky130_fd_sc_hd__ebufn |vpiTop:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__ebufn.Z), line:34:5, endln:34:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__ebufn (work@sky130_fd_sc_hd__ebufn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__ebufn.functional.v, line:33:1, endln:47:10 + \_module_inst: work@sky130_fd_sc_hd__ebufn (work@sky130_fd_sc_hd__ebufn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__ebufn.functional.v, line:33:1, endln:47:10 |vpiTypespec: \_logic_typespec: , line:40:12, endln:40:12 |vpiName:Z @@ -47135,7 +47135,7 @@ design: (work@sky130_fd_sc_hd__ebufn) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__ebufn.A), line:35:5, endln:35:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__ebufn (work@sky130_fd_sc_hd__ebufn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__ebufn.functional.v, line:33:1, endln:47:10 + \_module_inst: work@sky130_fd_sc_hd__ebufn (work@sky130_fd_sc_hd__ebufn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__ebufn.functional.v, line:33:1, endln:47:10 |vpiTypespec: \_logic_typespec: , line:41:12, endln:41:12 |vpiName:A @@ -47143,7 +47143,7 @@ design: (work@sky130_fd_sc_hd__ebufn) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__ebufn.TE_B), line:36:5, endln:36:9 |vpiParent: - \_module: work@sky130_fd_sc_hd__ebufn (work@sky130_fd_sc_hd__ebufn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__ebufn.functional.v, line:33:1, endln:47:10 + \_module_inst: work@sky130_fd_sc_hd__ebufn (work@sky130_fd_sc_hd__ebufn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__ebufn.functional.v, line:33:1, endln:47:10 |vpiTypespec: \_logic_typespec: , line:42:12, endln:42:12 |vpiName:TE_B @@ -47152,7 +47152,7 @@ design: (work@sky130_fd_sc_hd__ebufn) |vpiPort: \_port: (Z), line:34:5, endln:34:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__ebufn (work@sky130_fd_sc_hd__ebufn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__ebufn.functional.v, line:33:1, endln:47:10 + \_module_inst: work@sky130_fd_sc_hd__ebufn (work@sky130_fd_sc_hd__ebufn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__ebufn.functional.v, line:33:1, endln:47:10 |vpiName:Z |vpiDirection:2 |vpiLowConn: @@ -47166,7 +47166,7 @@ design: (work@sky130_fd_sc_hd__ebufn) |vpiPort: \_port: (A), line:35:5, endln:35:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__ebufn (work@sky130_fd_sc_hd__ebufn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__ebufn.functional.v, line:33:1, endln:47:10 + \_module_inst: work@sky130_fd_sc_hd__ebufn (work@sky130_fd_sc_hd__ebufn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__ebufn.functional.v, line:33:1, endln:47:10 |vpiName:A |vpiDirection:1 |vpiLowConn: @@ -47180,7 +47180,7 @@ design: (work@sky130_fd_sc_hd__ebufn) |vpiPort: \_port: (TE_B), line:36:5, endln:36:9 |vpiParent: - \_module: work@sky130_fd_sc_hd__ebufn (work@sky130_fd_sc_hd__ebufn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__ebufn.functional.v, line:33:1, endln:47:10 + \_module_inst: work@sky130_fd_sc_hd__ebufn (work@sky130_fd_sc_hd__ebufn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__ebufn.functional.v, line:33:1, endln:47:10 |vpiName:TE_B |vpiDirection:1 |vpiLowConn: @@ -47194,7 +47194,7 @@ design: (work@sky130_fd_sc_hd__ebufn) |vpiPrimitive: \_gate: work@bufif0 (work@sky130_fd_sc_hd__ebufn.bufif00), line:45:12, endln:45:45 |vpiParent: - \_module: work@sky130_fd_sc_hd__ebufn (work@sky130_fd_sc_hd__ebufn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__ebufn.functional.v, line:33:1, endln:47:10 + \_module_inst: work@sky130_fd_sc_hd__ebufn (work@sky130_fd_sc_hd__ebufn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__ebufn.functional.v, line:33:1, endln:47:10 |vpiDefName:work@bufif0 |vpiName:bufif00 |vpiFullName:work@sky130_fd_sc_hd__ebufn.bufif00 @@ -47373,7 +47373,7 @@ design: (work@sky130_fd_sc_hd__dfsbp) |vpiSize:3 |STRING:? b ?x : 1 : 1 |uhdmallModules: -\_module: work@sky130_fd_sc_hd__dfsbp (work@sky130_fd_sc_hd__dfsbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfsbp.functional.v, line:36:1, endln:61:10 +\_module_inst: work@sky130_fd_sc_hd__dfsbp (work@sky130_fd_sc_hd__dfsbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfsbp.functional.v, line:36:1, endln:61:10 |vpiParent: \_design: (work@sky130_fd_sc_hd__dfsbp) |vpiFullName:work@sky130_fd_sc_hd__dfsbp @@ -47381,51 +47381,51 @@ design: (work@sky130_fd_sc_hd__dfsbp) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__dfsbp.buf_Q), line:52:10, endln:52:15 |vpiParent: - \_module: work@sky130_fd_sc_hd__dfsbp (work@sky130_fd_sc_hd__dfsbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfsbp.functional.v, line:36:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__dfsbp (work@sky130_fd_sc_hd__dfsbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfsbp.functional.v, line:36:1, endln:61:10 |vpiName:buf_Q |vpiFullName:work@sky130_fd_sc_hd__dfsbp.buf_Q |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__dfsbp.SET), line:53:10, endln:53:13 |vpiParent: - \_module: work@sky130_fd_sc_hd__dfsbp (work@sky130_fd_sc_hd__dfsbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfsbp.functional.v, line:36:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__dfsbp (work@sky130_fd_sc_hd__dfsbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfsbp.functional.v, line:36:1, endln:61:10 |vpiName:SET |vpiFullName:work@sky130_fd_sc_hd__dfsbp.SET |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__dfsbp.Q), line:37:5, endln:37:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__dfsbp (work@sky130_fd_sc_hd__dfsbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfsbp.functional.v, line:36:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__dfsbp (work@sky130_fd_sc_hd__dfsbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfsbp.functional.v, line:36:1, endln:61:10 |vpiName:Q |vpiFullName:work@sky130_fd_sc_hd__dfsbp.Q |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__dfsbp.Q_N), line:38:5, endln:38:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__dfsbp (work@sky130_fd_sc_hd__dfsbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfsbp.functional.v, line:36:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__dfsbp (work@sky130_fd_sc_hd__dfsbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfsbp.functional.v, line:36:1, endln:61:10 |vpiName:Q_N |vpiFullName:work@sky130_fd_sc_hd__dfsbp.Q_N |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__dfsbp.CLK), line:39:5, endln:39:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__dfsbp (work@sky130_fd_sc_hd__dfsbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfsbp.functional.v, line:36:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__dfsbp (work@sky130_fd_sc_hd__dfsbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfsbp.functional.v, line:36:1, endln:61:10 |vpiName:CLK |vpiFullName:work@sky130_fd_sc_hd__dfsbp.CLK |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__dfsbp.D), line:40:5, endln:40:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__dfsbp (work@sky130_fd_sc_hd__dfsbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfsbp.functional.v, line:36:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__dfsbp (work@sky130_fd_sc_hd__dfsbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfsbp.functional.v, line:36:1, endln:61:10 |vpiName:D |vpiFullName:work@sky130_fd_sc_hd__dfsbp.D |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__dfsbp.SET_B), line:41:5, endln:41:10 |vpiParent: - \_module: work@sky130_fd_sc_hd__dfsbp (work@sky130_fd_sc_hd__dfsbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfsbp.functional.v, line:36:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__dfsbp (work@sky130_fd_sc_hd__dfsbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfsbp.functional.v, line:36:1, endln:61:10 |vpiName:SET_B |vpiFullName:work@sky130_fd_sc_hd__dfsbp.SET_B |vpiPort: \_port: (Q), line:37:5, endln:37:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__dfsbp (work@sky130_fd_sc_hd__dfsbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfsbp.functional.v, line:36:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__dfsbp (work@sky130_fd_sc_hd__dfsbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfsbp.functional.v, line:36:1, endln:61:10 |vpiName:Q |vpiDirection:2 |vpiLowConn: @@ -47437,7 +47437,7 @@ design: (work@sky130_fd_sc_hd__dfsbp) |vpiPort: \_port: (Q_N), line:38:5, endln:38:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__dfsbp (work@sky130_fd_sc_hd__dfsbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfsbp.functional.v, line:36:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__dfsbp (work@sky130_fd_sc_hd__dfsbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfsbp.functional.v, line:36:1, endln:61:10 |vpiName:Q_N |vpiDirection:2 |vpiLowConn: @@ -47449,7 +47449,7 @@ design: (work@sky130_fd_sc_hd__dfsbp) |vpiPort: \_port: (CLK), line:39:5, endln:39:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__dfsbp (work@sky130_fd_sc_hd__dfsbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfsbp.functional.v, line:36:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__dfsbp (work@sky130_fd_sc_hd__dfsbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfsbp.functional.v, line:36:1, endln:61:10 |vpiName:CLK |vpiDirection:1 |vpiLowConn: @@ -47461,7 +47461,7 @@ design: (work@sky130_fd_sc_hd__dfsbp) |vpiPort: \_port: (D), line:40:5, endln:40:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__dfsbp (work@sky130_fd_sc_hd__dfsbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfsbp.functional.v, line:36:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__dfsbp (work@sky130_fd_sc_hd__dfsbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfsbp.functional.v, line:36:1, endln:61:10 |vpiName:D |vpiDirection:1 |vpiLowConn: @@ -47473,7 +47473,7 @@ design: (work@sky130_fd_sc_hd__dfsbp) |vpiPort: \_port: (SET_B), line:41:5, endln:41:10 |vpiParent: - \_module: work@sky130_fd_sc_hd__dfsbp (work@sky130_fd_sc_hd__dfsbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfsbp.functional.v, line:36:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__dfsbp (work@sky130_fd_sc_hd__dfsbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfsbp.functional.v, line:36:1, endln:61:10 |vpiName:SET_B |vpiDirection:1 |vpiLowConn: @@ -47483,14 +47483,14 @@ design: (work@sky130_fd_sc_hd__dfsbp) |vpiTypedef: \_logic_typespec: , line:49:12, endln:49:12 |uhdmtopModules: -\_module: work@sky130_fd_sc_hd__dfsbp (work@sky130_fd_sc_hd__dfsbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfsbp.functional.v, line:36:1, endln:61:10 +\_module_inst: work@sky130_fd_sc_hd__dfsbp (work@sky130_fd_sc_hd__dfsbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfsbp.functional.v, line:36:1, endln:61:10 |vpiName:work@sky130_fd_sc_hd__dfsbp |vpiDefName:work@sky130_fd_sc_hd__dfsbp |vpiTop:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__dfsbp.buf_Q), line:52:10, endln:52:15 |vpiParent: - \_module: work@sky130_fd_sc_hd__dfsbp (work@sky130_fd_sc_hd__dfsbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfsbp.functional.v, line:36:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__dfsbp (work@sky130_fd_sc_hd__dfsbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfsbp.functional.v, line:36:1, endln:61:10 |vpiTypespec: \_logic_typespec: , line:52:5, endln:52:9 |vpiName:buf_Q @@ -47499,7 +47499,7 @@ design: (work@sky130_fd_sc_hd__dfsbp) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__dfsbp.SET), line:53:10, endln:53:13 |vpiParent: - \_module: work@sky130_fd_sc_hd__dfsbp (work@sky130_fd_sc_hd__dfsbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfsbp.functional.v, line:36:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__dfsbp (work@sky130_fd_sc_hd__dfsbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfsbp.functional.v, line:36:1, endln:61:10 |vpiTypespec: \_logic_typespec: , line:53:5, endln:53:9 |vpiName:SET @@ -47508,7 +47508,7 @@ design: (work@sky130_fd_sc_hd__dfsbp) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__dfsbp.Q), line:37:5, endln:37:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__dfsbp (work@sky130_fd_sc_hd__dfsbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfsbp.functional.v, line:36:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__dfsbp (work@sky130_fd_sc_hd__dfsbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfsbp.functional.v, line:36:1, endln:61:10 |vpiTypespec: \_logic_typespec: , line:45:12, endln:45:12 |vpiName:Q @@ -47516,7 +47516,7 @@ design: (work@sky130_fd_sc_hd__dfsbp) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__dfsbp.Q_N), line:38:5, endln:38:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__dfsbp (work@sky130_fd_sc_hd__dfsbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfsbp.functional.v, line:36:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__dfsbp (work@sky130_fd_sc_hd__dfsbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfsbp.functional.v, line:36:1, endln:61:10 |vpiTypespec: \_logic_typespec: , line:46:12, endln:46:12 |vpiName:Q_N @@ -47524,7 +47524,7 @@ design: (work@sky130_fd_sc_hd__dfsbp) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__dfsbp.CLK), line:39:5, endln:39:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__dfsbp (work@sky130_fd_sc_hd__dfsbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfsbp.functional.v, line:36:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__dfsbp (work@sky130_fd_sc_hd__dfsbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfsbp.functional.v, line:36:1, endln:61:10 |vpiTypespec: \_logic_typespec: , line:47:12, endln:47:12 |vpiName:CLK @@ -47532,7 +47532,7 @@ design: (work@sky130_fd_sc_hd__dfsbp) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__dfsbp.D), line:40:5, endln:40:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__dfsbp (work@sky130_fd_sc_hd__dfsbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfsbp.functional.v, line:36:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__dfsbp (work@sky130_fd_sc_hd__dfsbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfsbp.functional.v, line:36:1, endln:61:10 |vpiTypespec: \_logic_typespec: , line:48:12, endln:48:12 |vpiName:D @@ -47540,7 +47540,7 @@ design: (work@sky130_fd_sc_hd__dfsbp) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__dfsbp.SET_B), line:41:5, endln:41:10 |vpiParent: - \_module: work@sky130_fd_sc_hd__dfsbp (work@sky130_fd_sc_hd__dfsbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfsbp.functional.v, line:36:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__dfsbp (work@sky130_fd_sc_hd__dfsbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfsbp.functional.v, line:36:1, endln:61:10 |vpiTypespec: \_logic_typespec: , line:49:12, endln:49:12 |vpiName:SET_B @@ -47549,7 +47549,7 @@ design: (work@sky130_fd_sc_hd__dfsbp) |vpiPort: \_port: (Q), line:37:5, endln:37:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__dfsbp (work@sky130_fd_sc_hd__dfsbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfsbp.functional.v, line:36:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__dfsbp (work@sky130_fd_sc_hd__dfsbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfsbp.functional.v, line:36:1, endln:61:10 |vpiName:Q |vpiDirection:2 |vpiLowConn: @@ -47563,7 +47563,7 @@ design: (work@sky130_fd_sc_hd__dfsbp) |vpiPort: \_port: (Q_N), line:38:5, endln:38:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__dfsbp (work@sky130_fd_sc_hd__dfsbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfsbp.functional.v, line:36:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__dfsbp (work@sky130_fd_sc_hd__dfsbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfsbp.functional.v, line:36:1, endln:61:10 |vpiName:Q_N |vpiDirection:2 |vpiLowConn: @@ -47577,7 +47577,7 @@ design: (work@sky130_fd_sc_hd__dfsbp) |vpiPort: \_port: (CLK), line:39:5, endln:39:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__dfsbp (work@sky130_fd_sc_hd__dfsbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfsbp.functional.v, line:36:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__dfsbp (work@sky130_fd_sc_hd__dfsbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfsbp.functional.v, line:36:1, endln:61:10 |vpiName:CLK |vpiDirection:1 |vpiLowConn: @@ -47591,7 +47591,7 @@ design: (work@sky130_fd_sc_hd__dfsbp) |vpiPort: \_port: (D), line:40:5, endln:40:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__dfsbp (work@sky130_fd_sc_hd__dfsbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfsbp.functional.v, line:36:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__dfsbp (work@sky130_fd_sc_hd__dfsbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfsbp.functional.v, line:36:1, endln:61:10 |vpiName:D |vpiDirection:1 |vpiLowConn: @@ -47605,7 +47605,7 @@ design: (work@sky130_fd_sc_hd__dfsbp) |vpiPort: \_port: (SET_B), line:41:5, endln:41:10 |vpiParent: - \_module: work@sky130_fd_sc_hd__dfsbp (work@sky130_fd_sc_hd__dfsbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfsbp.functional.v, line:36:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__dfsbp (work@sky130_fd_sc_hd__dfsbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfsbp.functional.v, line:36:1, endln:61:10 |vpiName:SET_B |vpiDirection:1 |vpiLowConn: @@ -47619,7 +47619,7 @@ design: (work@sky130_fd_sc_hd__dfsbp) |vpiPrimitive: \_gate: work@not (work@sky130_fd_sc_hd__dfsbp.not0), line:56:45, endln:56:75 |vpiParent: - \_module: work@sky130_fd_sc_hd__dfsbp (work@sky130_fd_sc_hd__dfsbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfsbp.functional.v, line:36:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__dfsbp (work@sky130_fd_sc_hd__dfsbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfsbp.functional.v, line:36:1, endln:61:10 |vpiDefName:work@not |vpiName:not0 |vpiFullName:work@sky130_fd_sc_hd__dfsbp.not0 @@ -47654,7 +47654,7 @@ design: (work@sky130_fd_sc_hd__dfsbp) |vpiPrimitive: \_udp: work@sky130_fd_sc_hd__udp_dff$PS (work@sky130_fd_sc_hd__dfsbp.dff0), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfsbp.functional.v, line:57:5, endln:57:65 |vpiParent: - \_module: work@sky130_fd_sc_hd__dfsbp (work@sky130_fd_sc_hd__dfsbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfsbp.functional.v, line:36:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__dfsbp (work@sky130_fd_sc_hd__dfsbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfsbp.functional.v, line:36:1, endln:61:10 |vpiDefName:work@sky130_fd_sc_hd__udp_dff$PS |vpiName:dff0 |vpiFullName:work@sky130_fd_sc_hd__dfsbp.dff0 @@ -47663,7 +47663,7 @@ design: (work@sky130_fd_sc_hd__dfsbp) |vpiPrimitive: \_gate: work@buf (work@sky130_fd_sc_hd__dfsbp.buf0), line:58:45, endln:58:75 |vpiParent: - \_module: work@sky130_fd_sc_hd__dfsbp (work@sky130_fd_sc_hd__dfsbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfsbp.functional.v, line:36:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__dfsbp (work@sky130_fd_sc_hd__dfsbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfsbp.functional.v, line:36:1, endln:61:10 |vpiDefName:work@buf |vpiName:buf0 |vpiFullName:work@sky130_fd_sc_hd__dfsbp.buf0 @@ -47698,7 +47698,7 @@ design: (work@sky130_fd_sc_hd__dfsbp) |vpiPrimitive: \_gate: work@not (work@sky130_fd_sc_hd__dfsbp.not1), line:59:45, endln:59:75 |vpiParent: - \_module: work@sky130_fd_sc_hd__dfsbp (work@sky130_fd_sc_hd__dfsbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfsbp.functional.v, line:36:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__dfsbp (work@sky130_fd_sc_hd__dfsbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfsbp.functional.v, line:36:1, endln:61:10 |vpiDefName:work@not |vpiName:not1 |vpiFullName:work@sky130_fd_sc_hd__dfsbp.not1 @@ -47741,7 +47741,7 @@ Processing: -cd cells/cells -DUNIT_DELAY -writepp -parse -nocache -nobuiltin -no design: (work@sky130_fd_sc_hd__a2bb2oi) |vpiName:work@sky130_fd_sc_hd__a2bb2oi |uhdmallModules: -\_module: work@sky130_fd_sc_hd__a2bb2oi (work@sky130_fd_sc_hd__a2bb2oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a2bb2oi.functional.v, line:36:1, endln:62:10 +\_module_inst: work@sky130_fd_sc_hd__a2bb2oi (work@sky130_fd_sc_hd__a2bb2oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a2bb2oi.functional.v, line:36:1, endln:62:10 |vpiParent: \_design: (work@sky130_fd_sc_hd__a2bb2oi) |vpiFullName:work@sky130_fd_sc_hd__a2bb2oi @@ -47749,58 +47749,58 @@ design: (work@sky130_fd_sc_hd__a2bb2oi) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a2bb2oi.and0_out), line:52:10, endln:52:18 |vpiParent: - \_module: work@sky130_fd_sc_hd__a2bb2oi (work@sky130_fd_sc_hd__a2bb2oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a2bb2oi.functional.v, line:36:1, endln:62:10 + \_module_inst: work@sky130_fd_sc_hd__a2bb2oi (work@sky130_fd_sc_hd__a2bb2oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a2bb2oi.functional.v, line:36:1, endln:62:10 |vpiName:and0_out |vpiFullName:work@sky130_fd_sc_hd__a2bb2oi.and0_out |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a2bb2oi.nor0_out), line:53:10, endln:53:18 |vpiParent: - \_module: work@sky130_fd_sc_hd__a2bb2oi (work@sky130_fd_sc_hd__a2bb2oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a2bb2oi.functional.v, line:36:1, endln:62:10 + \_module_inst: work@sky130_fd_sc_hd__a2bb2oi (work@sky130_fd_sc_hd__a2bb2oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a2bb2oi.functional.v, line:36:1, endln:62:10 |vpiName:nor0_out |vpiFullName:work@sky130_fd_sc_hd__a2bb2oi.nor0_out |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a2bb2oi.nor1_out_Y), line:54:10, endln:54:20 |vpiParent: - \_module: work@sky130_fd_sc_hd__a2bb2oi (work@sky130_fd_sc_hd__a2bb2oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a2bb2oi.functional.v, line:36:1, endln:62:10 + \_module_inst: work@sky130_fd_sc_hd__a2bb2oi (work@sky130_fd_sc_hd__a2bb2oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a2bb2oi.functional.v, line:36:1, endln:62:10 |vpiName:nor1_out_Y |vpiFullName:work@sky130_fd_sc_hd__a2bb2oi.nor1_out_Y |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a2bb2oi.Y), line:37:5, endln:37:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__a2bb2oi (work@sky130_fd_sc_hd__a2bb2oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a2bb2oi.functional.v, line:36:1, endln:62:10 + \_module_inst: work@sky130_fd_sc_hd__a2bb2oi (work@sky130_fd_sc_hd__a2bb2oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a2bb2oi.functional.v, line:36:1, endln:62:10 |vpiName:Y |vpiFullName:work@sky130_fd_sc_hd__a2bb2oi.Y |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a2bb2oi.A1_N), line:38:5, endln:38:9 |vpiParent: - \_module: work@sky130_fd_sc_hd__a2bb2oi (work@sky130_fd_sc_hd__a2bb2oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a2bb2oi.functional.v, line:36:1, endln:62:10 + \_module_inst: work@sky130_fd_sc_hd__a2bb2oi (work@sky130_fd_sc_hd__a2bb2oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a2bb2oi.functional.v, line:36:1, endln:62:10 |vpiName:A1_N |vpiFullName:work@sky130_fd_sc_hd__a2bb2oi.A1_N |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a2bb2oi.A2_N), line:39:5, endln:39:9 |vpiParent: - \_module: work@sky130_fd_sc_hd__a2bb2oi (work@sky130_fd_sc_hd__a2bb2oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a2bb2oi.functional.v, line:36:1, endln:62:10 + \_module_inst: work@sky130_fd_sc_hd__a2bb2oi (work@sky130_fd_sc_hd__a2bb2oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a2bb2oi.functional.v, line:36:1, endln:62:10 |vpiName:A2_N |vpiFullName:work@sky130_fd_sc_hd__a2bb2oi.A2_N |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a2bb2oi.B1), line:40:5, endln:40:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a2bb2oi (work@sky130_fd_sc_hd__a2bb2oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a2bb2oi.functional.v, line:36:1, endln:62:10 + \_module_inst: work@sky130_fd_sc_hd__a2bb2oi (work@sky130_fd_sc_hd__a2bb2oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a2bb2oi.functional.v, line:36:1, endln:62:10 |vpiName:B1 |vpiFullName:work@sky130_fd_sc_hd__a2bb2oi.B1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a2bb2oi.B2), line:41:5, endln:41:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a2bb2oi (work@sky130_fd_sc_hd__a2bb2oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a2bb2oi.functional.v, line:36:1, endln:62:10 + \_module_inst: work@sky130_fd_sc_hd__a2bb2oi (work@sky130_fd_sc_hd__a2bb2oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a2bb2oi.functional.v, line:36:1, endln:62:10 |vpiName:B2 |vpiFullName:work@sky130_fd_sc_hd__a2bb2oi.B2 |vpiPort: \_port: (Y), line:37:5, endln:37:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__a2bb2oi (work@sky130_fd_sc_hd__a2bb2oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a2bb2oi.functional.v, line:36:1, endln:62:10 + \_module_inst: work@sky130_fd_sc_hd__a2bb2oi (work@sky130_fd_sc_hd__a2bb2oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a2bb2oi.functional.v, line:36:1, endln:62:10 |vpiName:Y |vpiDirection:2 |vpiLowConn: @@ -47812,7 +47812,7 @@ design: (work@sky130_fd_sc_hd__a2bb2oi) |vpiPort: \_port: (A1_N), line:38:5, endln:38:9 |vpiParent: - \_module: work@sky130_fd_sc_hd__a2bb2oi (work@sky130_fd_sc_hd__a2bb2oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a2bb2oi.functional.v, line:36:1, endln:62:10 + \_module_inst: work@sky130_fd_sc_hd__a2bb2oi (work@sky130_fd_sc_hd__a2bb2oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a2bb2oi.functional.v, line:36:1, endln:62:10 |vpiName:A1_N |vpiDirection:1 |vpiLowConn: @@ -47824,7 +47824,7 @@ design: (work@sky130_fd_sc_hd__a2bb2oi) |vpiPort: \_port: (A2_N), line:39:5, endln:39:9 |vpiParent: - \_module: work@sky130_fd_sc_hd__a2bb2oi (work@sky130_fd_sc_hd__a2bb2oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a2bb2oi.functional.v, line:36:1, endln:62:10 + \_module_inst: work@sky130_fd_sc_hd__a2bb2oi (work@sky130_fd_sc_hd__a2bb2oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a2bb2oi.functional.v, line:36:1, endln:62:10 |vpiName:A2_N |vpiDirection:1 |vpiLowConn: @@ -47836,7 +47836,7 @@ design: (work@sky130_fd_sc_hd__a2bb2oi) |vpiPort: \_port: (B1), line:40:5, endln:40:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a2bb2oi (work@sky130_fd_sc_hd__a2bb2oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a2bb2oi.functional.v, line:36:1, endln:62:10 + \_module_inst: work@sky130_fd_sc_hd__a2bb2oi (work@sky130_fd_sc_hd__a2bb2oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a2bb2oi.functional.v, line:36:1, endln:62:10 |vpiName:B1 |vpiDirection:1 |vpiLowConn: @@ -47848,7 +47848,7 @@ design: (work@sky130_fd_sc_hd__a2bb2oi) |vpiPort: \_port: (B2), line:41:5, endln:41:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a2bb2oi (work@sky130_fd_sc_hd__a2bb2oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a2bb2oi.functional.v, line:36:1, endln:62:10 + \_module_inst: work@sky130_fd_sc_hd__a2bb2oi (work@sky130_fd_sc_hd__a2bb2oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a2bb2oi.functional.v, line:36:1, endln:62:10 |vpiName:B2 |vpiDirection:1 |vpiLowConn: @@ -47858,14 +47858,14 @@ design: (work@sky130_fd_sc_hd__a2bb2oi) |vpiTypedef: \_logic_typespec: , line:49:12, endln:49:12 |uhdmtopModules: -\_module: work@sky130_fd_sc_hd__a2bb2oi (work@sky130_fd_sc_hd__a2bb2oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a2bb2oi.functional.v, line:36:1, endln:62:10 +\_module_inst: work@sky130_fd_sc_hd__a2bb2oi (work@sky130_fd_sc_hd__a2bb2oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a2bb2oi.functional.v, line:36:1, endln:62:10 |vpiName:work@sky130_fd_sc_hd__a2bb2oi |vpiDefName:work@sky130_fd_sc_hd__a2bb2oi |vpiTop:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a2bb2oi.and0_out), line:52:10, endln:52:18 |vpiParent: - \_module: work@sky130_fd_sc_hd__a2bb2oi (work@sky130_fd_sc_hd__a2bb2oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a2bb2oi.functional.v, line:36:1, endln:62:10 + \_module_inst: work@sky130_fd_sc_hd__a2bb2oi (work@sky130_fd_sc_hd__a2bb2oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a2bb2oi.functional.v, line:36:1, endln:62:10 |vpiTypespec: \_logic_typespec: , line:52:5, endln:52:9 |vpiName:and0_out @@ -47874,7 +47874,7 @@ design: (work@sky130_fd_sc_hd__a2bb2oi) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a2bb2oi.nor0_out), line:53:10, endln:53:18 |vpiParent: - \_module: work@sky130_fd_sc_hd__a2bb2oi (work@sky130_fd_sc_hd__a2bb2oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a2bb2oi.functional.v, line:36:1, endln:62:10 + \_module_inst: work@sky130_fd_sc_hd__a2bb2oi (work@sky130_fd_sc_hd__a2bb2oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a2bb2oi.functional.v, line:36:1, endln:62:10 |vpiTypespec: \_logic_typespec: , line:53:5, endln:53:9 |vpiName:nor0_out @@ -47883,7 +47883,7 @@ design: (work@sky130_fd_sc_hd__a2bb2oi) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a2bb2oi.nor1_out_Y), line:54:10, endln:54:20 |vpiParent: - \_module: work@sky130_fd_sc_hd__a2bb2oi (work@sky130_fd_sc_hd__a2bb2oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a2bb2oi.functional.v, line:36:1, endln:62:10 + \_module_inst: work@sky130_fd_sc_hd__a2bb2oi (work@sky130_fd_sc_hd__a2bb2oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a2bb2oi.functional.v, line:36:1, endln:62:10 |vpiTypespec: \_logic_typespec: , line:54:5, endln:54:9 |vpiName:nor1_out_Y @@ -47892,7 +47892,7 @@ design: (work@sky130_fd_sc_hd__a2bb2oi) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a2bb2oi.Y), line:37:5, endln:37:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__a2bb2oi (work@sky130_fd_sc_hd__a2bb2oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a2bb2oi.functional.v, line:36:1, endln:62:10 + \_module_inst: work@sky130_fd_sc_hd__a2bb2oi (work@sky130_fd_sc_hd__a2bb2oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a2bb2oi.functional.v, line:36:1, endln:62:10 |vpiTypespec: \_logic_typespec: , line:45:12, endln:45:12 |vpiName:Y @@ -47900,7 +47900,7 @@ design: (work@sky130_fd_sc_hd__a2bb2oi) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a2bb2oi.A1_N), line:38:5, endln:38:9 |vpiParent: - \_module: work@sky130_fd_sc_hd__a2bb2oi (work@sky130_fd_sc_hd__a2bb2oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a2bb2oi.functional.v, line:36:1, endln:62:10 + \_module_inst: work@sky130_fd_sc_hd__a2bb2oi (work@sky130_fd_sc_hd__a2bb2oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a2bb2oi.functional.v, line:36:1, endln:62:10 |vpiTypespec: \_logic_typespec: , line:46:12, endln:46:12 |vpiName:A1_N @@ -47908,7 +47908,7 @@ design: (work@sky130_fd_sc_hd__a2bb2oi) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a2bb2oi.A2_N), line:39:5, endln:39:9 |vpiParent: - \_module: work@sky130_fd_sc_hd__a2bb2oi (work@sky130_fd_sc_hd__a2bb2oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a2bb2oi.functional.v, line:36:1, endln:62:10 + \_module_inst: work@sky130_fd_sc_hd__a2bb2oi (work@sky130_fd_sc_hd__a2bb2oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a2bb2oi.functional.v, line:36:1, endln:62:10 |vpiTypespec: \_logic_typespec: , line:47:12, endln:47:12 |vpiName:A2_N @@ -47916,7 +47916,7 @@ design: (work@sky130_fd_sc_hd__a2bb2oi) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a2bb2oi.B1), line:40:5, endln:40:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a2bb2oi (work@sky130_fd_sc_hd__a2bb2oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a2bb2oi.functional.v, line:36:1, endln:62:10 + \_module_inst: work@sky130_fd_sc_hd__a2bb2oi (work@sky130_fd_sc_hd__a2bb2oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a2bb2oi.functional.v, line:36:1, endln:62:10 |vpiTypespec: \_logic_typespec: , line:48:12, endln:48:12 |vpiName:B1 @@ -47924,7 +47924,7 @@ design: (work@sky130_fd_sc_hd__a2bb2oi) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a2bb2oi.B2), line:41:5, endln:41:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a2bb2oi (work@sky130_fd_sc_hd__a2bb2oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a2bb2oi.functional.v, line:36:1, endln:62:10 + \_module_inst: work@sky130_fd_sc_hd__a2bb2oi (work@sky130_fd_sc_hd__a2bb2oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a2bb2oi.functional.v, line:36:1, endln:62:10 |vpiTypespec: \_logic_typespec: , line:49:12, endln:49:12 |vpiName:B2 @@ -47933,7 +47933,7 @@ design: (work@sky130_fd_sc_hd__a2bb2oi) |vpiPort: \_port: (Y), line:37:5, endln:37:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__a2bb2oi (work@sky130_fd_sc_hd__a2bb2oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a2bb2oi.functional.v, line:36:1, endln:62:10 + \_module_inst: work@sky130_fd_sc_hd__a2bb2oi (work@sky130_fd_sc_hd__a2bb2oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a2bb2oi.functional.v, line:36:1, endln:62:10 |vpiName:Y |vpiDirection:2 |vpiLowConn: @@ -47947,7 +47947,7 @@ design: (work@sky130_fd_sc_hd__a2bb2oi) |vpiPort: \_port: (A1_N), line:38:5, endln:38:9 |vpiParent: - \_module: work@sky130_fd_sc_hd__a2bb2oi (work@sky130_fd_sc_hd__a2bb2oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a2bb2oi.functional.v, line:36:1, endln:62:10 + \_module_inst: work@sky130_fd_sc_hd__a2bb2oi (work@sky130_fd_sc_hd__a2bb2oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a2bb2oi.functional.v, line:36:1, endln:62:10 |vpiName:A1_N |vpiDirection:1 |vpiLowConn: @@ -47961,7 +47961,7 @@ design: (work@sky130_fd_sc_hd__a2bb2oi) |vpiPort: \_port: (A2_N), line:39:5, endln:39:9 |vpiParent: - \_module: work@sky130_fd_sc_hd__a2bb2oi (work@sky130_fd_sc_hd__a2bb2oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a2bb2oi.functional.v, line:36:1, endln:62:10 + \_module_inst: work@sky130_fd_sc_hd__a2bb2oi (work@sky130_fd_sc_hd__a2bb2oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a2bb2oi.functional.v, line:36:1, endln:62:10 |vpiName:A2_N |vpiDirection:1 |vpiLowConn: @@ -47975,7 +47975,7 @@ design: (work@sky130_fd_sc_hd__a2bb2oi) |vpiPort: \_port: (B1), line:40:5, endln:40:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a2bb2oi (work@sky130_fd_sc_hd__a2bb2oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a2bb2oi.functional.v, line:36:1, endln:62:10 + \_module_inst: work@sky130_fd_sc_hd__a2bb2oi (work@sky130_fd_sc_hd__a2bb2oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a2bb2oi.functional.v, line:36:1, endln:62:10 |vpiName:B1 |vpiDirection:1 |vpiLowConn: @@ -47989,7 +47989,7 @@ design: (work@sky130_fd_sc_hd__a2bb2oi) |vpiPort: \_port: (B2), line:41:5, endln:41:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a2bb2oi (work@sky130_fd_sc_hd__a2bb2oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a2bb2oi.functional.v, line:36:1, endln:62:10 + \_module_inst: work@sky130_fd_sc_hd__a2bb2oi (work@sky130_fd_sc_hd__a2bb2oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a2bb2oi.functional.v, line:36:1, endln:62:10 |vpiName:B2 |vpiDirection:1 |vpiLowConn: @@ -48003,7 +48003,7 @@ design: (work@sky130_fd_sc_hd__a2bb2oi) |vpiPrimitive: \_gate: work@and (work@sky130_fd_sc_hd__a2bb2oi.and0), line:57:9, endln:57:46 |vpiParent: - \_module: work@sky130_fd_sc_hd__a2bb2oi (work@sky130_fd_sc_hd__a2bb2oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a2bb2oi.functional.v, line:36:1, endln:62:10 + \_module_inst: work@sky130_fd_sc_hd__a2bb2oi (work@sky130_fd_sc_hd__a2bb2oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a2bb2oi.functional.v, line:36:1, endln:62:10 |vpiDefName:work@and |vpiName:and0 |vpiFullName:work@sky130_fd_sc_hd__a2bb2oi.and0 @@ -48052,7 +48052,7 @@ design: (work@sky130_fd_sc_hd__a2bb2oi) |vpiPrimitive: \_gate: work@nor (work@sky130_fd_sc_hd__a2bb2oi.nor0), line:58:9, endln:58:46 |vpiParent: - \_module: work@sky130_fd_sc_hd__a2bb2oi (work@sky130_fd_sc_hd__a2bb2oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a2bb2oi.functional.v, line:36:1, endln:62:10 + \_module_inst: work@sky130_fd_sc_hd__a2bb2oi (work@sky130_fd_sc_hd__a2bb2oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a2bb2oi.functional.v, line:36:1, endln:62:10 |vpiDefName:work@nor |vpiName:nor0 |vpiFullName:work@sky130_fd_sc_hd__a2bb2oi.nor0 @@ -48101,7 +48101,7 @@ design: (work@sky130_fd_sc_hd__a2bb2oi) |vpiPrimitive: \_gate: work@nor (work@sky130_fd_sc_hd__a2bb2oi.nor1), line:59:9, endln:59:46 |vpiParent: - \_module: work@sky130_fd_sc_hd__a2bb2oi (work@sky130_fd_sc_hd__a2bb2oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a2bb2oi.functional.v, line:36:1, endln:62:10 + \_module_inst: work@sky130_fd_sc_hd__a2bb2oi (work@sky130_fd_sc_hd__a2bb2oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a2bb2oi.functional.v, line:36:1, endln:62:10 |vpiDefName:work@nor |vpiName:nor1 |vpiFullName:work@sky130_fd_sc_hd__a2bb2oi.nor1 @@ -48150,7 +48150,7 @@ design: (work@sky130_fd_sc_hd__a2bb2oi) |vpiPrimitive: \_gate: work@buf (work@sky130_fd_sc_hd__a2bb2oi.buf0), line:60:9, endln:60:46 |vpiParent: - \_module: work@sky130_fd_sc_hd__a2bb2oi (work@sky130_fd_sc_hd__a2bb2oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a2bb2oi.functional.v, line:36:1, endln:62:10 + \_module_inst: work@sky130_fd_sc_hd__a2bb2oi (work@sky130_fd_sc_hd__a2bb2oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a2bb2oi.functional.v, line:36:1, endln:62:10 |vpiDefName:work@buf |vpiName:buf0 |vpiFullName:work@sky130_fd_sc_hd__a2bb2oi.buf0 @@ -48315,7 +48315,7 @@ design: (work@sky130_fd_sc_hd__dfrtn) |vpiSize:3 |STRING:? b ?x : 0 : 0 |uhdmallModules: -\_module: work@sky130_fd_sc_hd__dfrtn (work@sky130_fd_sc_hd__dfrtn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfrtn.functional.v, line:37:1, endln:61:10 +\_module_inst: work@sky130_fd_sc_hd__dfrtn (work@sky130_fd_sc_hd__dfrtn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfrtn.functional.v, line:37:1, endln:61:10 |vpiParent: \_design: (work@sky130_fd_sc_hd__dfrtn) |vpiFullName:work@sky130_fd_sc_hd__dfrtn @@ -48323,52 +48323,52 @@ design: (work@sky130_fd_sc_hd__dfrtn) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__dfrtn.buf_Q), line:51:10, endln:51:15 |vpiParent: - \_module: work@sky130_fd_sc_hd__dfrtn (work@sky130_fd_sc_hd__dfrtn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfrtn.functional.v, line:37:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__dfrtn (work@sky130_fd_sc_hd__dfrtn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfrtn.functional.v, line:37:1, endln:61:10 |vpiName:buf_Q |vpiFullName:work@sky130_fd_sc_hd__dfrtn.buf_Q |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__dfrtn.RESET), line:52:10, endln:52:15 |vpiParent: - \_module: work@sky130_fd_sc_hd__dfrtn (work@sky130_fd_sc_hd__dfrtn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfrtn.functional.v, line:37:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__dfrtn (work@sky130_fd_sc_hd__dfrtn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfrtn.functional.v, line:37:1, endln:61:10 |vpiName:RESET |vpiFullName:work@sky130_fd_sc_hd__dfrtn.RESET |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__dfrtn.intclk), line:53:10, endln:53:16 |vpiParent: - \_module: work@sky130_fd_sc_hd__dfrtn (work@sky130_fd_sc_hd__dfrtn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfrtn.functional.v, line:37:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__dfrtn (work@sky130_fd_sc_hd__dfrtn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfrtn.functional.v, line:37:1, endln:61:10 |vpiName:intclk |vpiFullName:work@sky130_fd_sc_hd__dfrtn.intclk |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__dfrtn.Q), line:38:5, endln:38:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__dfrtn (work@sky130_fd_sc_hd__dfrtn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfrtn.functional.v, line:37:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__dfrtn (work@sky130_fd_sc_hd__dfrtn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfrtn.functional.v, line:37:1, endln:61:10 |vpiName:Q |vpiFullName:work@sky130_fd_sc_hd__dfrtn.Q |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__dfrtn.CLK_N), line:39:5, endln:39:10 |vpiParent: - \_module: work@sky130_fd_sc_hd__dfrtn (work@sky130_fd_sc_hd__dfrtn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfrtn.functional.v, line:37:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__dfrtn (work@sky130_fd_sc_hd__dfrtn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfrtn.functional.v, line:37:1, endln:61:10 |vpiName:CLK_N |vpiFullName:work@sky130_fd_sc_hd__dfrtn.CLK_N |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__dfrtn.D), line:40:5, endln:40:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__dfrtn (work@sky130_fd_sc_hd__dfrtn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfrtn.functional.v, line:37:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__dfrtn (work@sky130_fd_sc_hd__dfrtn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfrtn.functional.v, line:37:1, endln:61:10 |vpiName:D |vpiFullName:work@sky130_fd_sc_hd__dfrtn.D |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__dfrtn.RESET_B), line:41:5, endln:41:12 |vpiParent: - \_module: work@sky130_fd_sc_hd__dfrtn (work@sky130_fd_sc_hd__dfrtn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfrtn.functional.v, line:37:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__dfrtn (work@sky130_fd_sc_hd__dfrtn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfrtn.functional.v, line:37:1, endln:61:10 |vpiName:RESET_B |vpiFullName:work@sky130_fd_sc_hd__dfrtn.RESET_B |vpiPort: \_port: (Q), line:38:5, endln:38:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__dfrtn (work@sky130_fd_sc_hd__dfrtn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfrtn.functional.v, line:37:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__dfrtn (work@sky130_fd_sc_hd__dfrtn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfrtn.functional.v, line:37:1, endln:61:10 |vpiName:Q |vpiDirection:2 |vpiLowConn: @@ -48380,7 +48380,7 @@ design: (work@sky130_fd_sc_hd__dfrtn) |vpiPort: \_port: (CLK_N), line:39:5, endln:39:10 |vpiParent: - \_module: work@sky130_fd_sc_hd__dfrtn (work@sky130_fd_sc_hd__dfrtn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfrtn.functional.v, line:37:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__dfrtn (work@sky130_fd_sc_hd__dfrtn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfrtn.functional.v, line:37:1, endln:61:10 |vpiName:CLK_N |vpiDirection:1 |vpiLowConn: @@ -48392,7 +48392,7 @@ design: (work@sky130_fd_sc_hd__dfrtn) |vpiPort: \_port: (D), line:40:5, endln:40:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__dfrtn (work@sky130_fd_sc_hd__dfrtn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfrtn.functional.v, line:37:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__dfrtn (work@sky130_fd_sc_hd__dfrtn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfrtn.functional.v, line:37:1, endln:61:10 |vpiName:D |vpiDirection:1 |vpiLowConn: @@ -48404,7 +48404,7 @@ design: (work@sky130_fd_sc_hd__dfrtn) |vpiPort: \_port: (RESET_B), line:41:5, endln:41:12 |vpiParent: - \_module: work@sky130_fd_sc_hd__dfrtn (work@sky130_fd_sc_hd__dfrtn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfrtn.functional.v, line:37:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__dfrtn (work@sky130_fd_sc_hd__dfrtn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfrtn.functional.v, line:37:1, endln:61:10 |vpiName:RESET_B |vpiDirection:1 |vpiLowConn: @@ -48414,14 +48414,14 @@ design: (work@sky130_fd_sc_hd__dfrtn) |vpiTypedef: \_logic_typespec: , line:48:12, endln:48:12 |uhdmtopModules: -\_module: work@sky130_fd_sc_hd__dfrtn (work@sky130_fd_sc_hd__dfrtn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfrtn.functional.v, line:37:1, endln:61:10 +\_module_inst: work@sky130_fd_sc_hd__dfrtn (work@sky130_fd_sc_hd__dfrtn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfrtn.functional.v, line:37:1, endln:61:10 |vpiName:work@sky130_fd_sc_hd__dfrtn |vpiDefName:work@sky130_fd_sc_hd__dfrtn |vpiTop:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__dfrtn.buf_Q), line:51:10, endln:51:15 |vpiParent: - \_module: work@sky130_fd_sc_hd__dfrtn (work@sky130_fd_sc_hd__dfrtn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfrtn.functional.v, line:37:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__dfrtn (work@sky130_fd_sc_hd__dfrtn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfrtn.functional.v, line:37:1, endln:61:10 |vpiTypespec: \_logic_typespec: , line:51:5, endln:51:9 |vpiName:buf_Q @@ -48430,7 +48430,7 @@ design: (work@sky130_fd_sc_hd__dfrtn) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__dfrtn.RESET), line:52:10, endln:52:15 |vpiParent: - \_module: work@sky130_fd_sc_hd__dfrtn (work@sky130_fd_sc_hd__dfrtn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfrtn.functional.v, line:37:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__dfrtn (work@sky130_fd_sc_hd__dfrtn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfrtn.functional.v, line:37:1, endln:61:10 |vpiTypespec: \_logic_typespec: , line:52:5, endln:52:9 |vpiName:RESET @@ -48439,7 +48439,7 @@ design: (work@sky130_fd_sc_hd__dfrtn) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__dfrtn.intclk), line:53:10, endln:53:16 |vpiParent: - \_module: work@sky130_fd_sc_hd__dfrtn (work@sky130_fd_sc_hd__dfrtn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfrtn.functional.v, line:37:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__dfrtn (work@sky130_fd_sc_hd__dfrtn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfrtn.functional.v, line:37:1, endln:61:10 |vpiTypespec: \_logic_typespec: , line:53:5, endln:53:9 |vpiName:intclk @@ -48448,7 +48448,7 @@ design: (work@sky130_fd_sc_hd__dfrtn) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__dfrtn.Q), line:38:5, endln:38:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__dfrtn (work@sky130_fd_sc_hd__dfrtn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfrtn.functional.v, line:37:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__dfrtn (work@sky130_fd_sc_hd__dfrtn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfrtn.functional.v, line:37:1, endln:61:10 |vpiTypespec: \_logic_typespec: , line:45:12, endln:45:12 |vpiName:Q @@ -48456,7 +48456,7 @@ design: (work@sky130_fd_sc_hd__dfrtn) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__dfrtn.CLK_N), line:39:5, endln:39:10 |vpiParent: - \_module: work@sky130_fd_sc_hd__dfrtn (work@sky130_fd_sc_hd__dfrtn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfrtn.functional.v, line:37:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__dfrtn (work@sky130_fd_sc_hd__dfrtn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfrtn.functional.v, line:37:1, endln:61:10 |vpiTypespec: \_logic_typespec: , line:46:12, endln:46:12 |vpiName:CLK_N @@ -48464,7 +48464,7 @@ design: (work@sky130_fd_sc_hd__dfrtn) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__dfrtn.D), line:40:5, endln:40:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__dfrtn (work@sky130_fd_sc_hd__dfrtn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfrtn.functional.v, line:37:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__dfrtn (work@sky130_fd_sc_hd__dfrtn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfrtn.functional.v, line:37:1, endln:61:10 |vpiTypespec: \_logic_typespec: , line:47:12, endln:47:12 |vpiName:D @@ -48472,7 +48472,7 @@ design: (work@sky130_fd_sc_hd__dfrtn) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__dfrtn.RESET_B), line:41:5, endln:41:12 |vpiParent: - \_module: work@sky130_fd_sc_hd__dfrtn (work@sky130_fd_sc_hd__dfrtn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfrtn.functional.v, line:37:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__dfrtn (work@sky130_fd_sc_hd__dfrtn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfrtn.functional.v, line:37:1, endln:61:10 |vpiTypespec: \_logic_typespec: , line:48:12, endln:48:12 |vpiName:RESET_B @@ -48481,7 +48481,7 @@ design: (work@sky130_fd_sc_hd__dfrtn) |vpiPort: \_port: (Q), line:38:5, endln:38:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__dfrtn (work@sky130_fd_sc_hd__dfrtn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfrtn.functional.v, line:37:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__dfrtn (work@sky130_fd_sc_hd__dfrtn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfrtn.functional.v, line:37:1, endln:61:10 |vpiName:Q |vpiDirection:2 |vpiLowConn: @@ -48495,7 +48495,7 @@ design: (work@sky130_fd_sc_hd__dfrtn) |vpiPort: \_port: (CLK_N), line:39:5, endln:39:10 |vpiParent: - \_module: work@sky130_fd_sc_hd__dfrtn (work@sky130_fd_sc_hd__dfrtn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfrtn.functional.v, line:37:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__dfrtn (work@sky130_fd_sc_hd__dfrtn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfrtn.functional.v, line:37:1, endln:61:10 |vpiName:CLK_N |vpiDirection:1 |vpiLowConn: @@ -48509,7 +48509,7 @@ design: (work@sky130_fd_sc_hd__dfrtn) |vpiPort: \_port: (D), line:40:5, endln:40:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__dfrtn (work@sky130_fd_sc_hd__dfrtn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfrtn.functional.v, line:37:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__dfrtn (work@sky130_fd_sc_hd__dfrtn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfrtn.functional.v, line:37:1, endln:61:10 |vpiName:D |vpiDirection:1 |vpiLowConn: @@ -48523,7 +48523,7 @@ design: (work@sky130_fd_sc_hd__dfrtn) |vpiPort: \_port: (RESET_B), line:41:5, endln:41:12 |vpiParent: - \_module: work@sky130_fd_sc_hd__dfrtn (work@sky130_fd_sc_hd__dfrtn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfrtn.functional.v, line:37:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__dfrtn (work@sky130_fd_sc_hd__dfrtn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfrtn.functional.v, line:37:1, endln:61:10 |vpiName:RESET_B |vpiDirection:1 |vpiLowConn: @@ -48537,7 +48537,7 @@ design: (work@sky130_fd_sc_hd__dfrtn) |vpiPrimitive: \_gate: work@not (work@sky130_fd_sc_hd__dfrtn.not0), line:56:45, endln:56:76 |vpiParent: - \_module: work@sky130_fd_sc_hd__dfrtn (work@sky130_fd_sc_hd__dfrtn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfrtn.functional.v, line:37:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__dfrtn (work@sky130_fd_sc_hd__dfrtn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfrtn.functional.v, line:37:1, endln:61:10 |vpiDefName:work@not |vpiName:not0 |vpiFullName:work@sky130_fd_sc_hd__dfrtn.not0 @@ -48572,7 +48572,7 @@ design: (work@sky130_fd_sc_hd__dfrtn) |vpiPrimitive: \_gate: work@not (work@sky130_fd_sc_hd__dfrtn.not1), line:57:45, endln:57:76 |vpiParent: - \_module: work@sky130_fd_sc_hd__dfrtn (work@sky130_fd_sc_hd__dfrtn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfrtn.functional.v, line:37:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__dfrtn (work@sky130_fd_sc_hd__dfrtn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfrtn.functional.v, line:37:1, endln:61:10 |vpiDefName:work@not |vpiName:not1 |vpiFullName:work@sky130_fd_sc_hd__dfrtn.not1 @@ -48607,7 +48607,7 @@ design: (work@sky130_fd_sc_hd__dfrtn) |vpiPrimitive: \_udp: work@sky130_fd_sc_hd__udp_dff$PR (work@sky130_fd_sc_hd__dfrtn.dff0), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfrtn.functional.v, line:58:5, endln:58:66 |vpiParent: - \_module: work@sky130_fd_sc_hd__dfrtn (work@sky130_fd_sc_hd__dfrtn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfrtn.functional.v, line:37:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__dfrtn (work@sky130_fd_sc_hd__dfrtn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfrtn.functional.v, line:37:1, endln:61:10 |vpiDefName:work@sky130_fd_sc_hd__udp_dff$PR |vpiName:dff0 |vpiFullName:work@sky130_fd_sc_hd__dfrtn.dff0 @@ -48616,7 +48616,7 @@ design: (work@sky130_fd_sc_hd__dfrtn) |vpiPrimitive: \_gate: work@buf (work@sky130_fd_sc_hd__dfrtn.buf0), line:59:45, endln:59:76 |vpiParent: - \_module: work@sky130_fd_sc_hd__dfrtn (work@sky130_fd_sc_hd__dfrtn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfrtn.functional.v, line:37:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__dfrtn (work@sky130_fd_sc_hd__dfrtn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfrtn.functional.v, line:37:1, endln:61:10 |vpiDefName:work@buf |vpiName:buf0 |vpiFullName:work@sky130_fd_sc_hd__dfrtn.buf0 @@ -48769,7 +48769,7 @@ design: (work@sky130_fd_sc_hd__dlrtp) |vpiSize:3 |STRING:0 x x : 0 : 0 |uhdmallModules: -\_module: work@sky130_fd_sc_hd__dlrtp (work@sky130_fd_sc_hd__dlrtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlrtp.functional.v, line:37:1, endln:59:10 +\_module_inst: work@sky130_fd_sc_hd__dlrtp (work@sky130_fd_sc_hd__dlrtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlrtp.functional.v, line:37:1, endln:59:10 |vpiParent: \_design: (work@sky130_fd_sc_hd__dlrtp) |vpiFullName:work@sky130_fd_sc_hd__dlrtp @@ -48777,45 +48777,45 @@ design: (work@sky130_fd_sc_hd__dlrtp) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__dlrtp.RESET), line:51:10, endln:51:15 |vpiParent: - \_module: work@sky130_fd_sc_hd__dlrtp (work@sky130_fd_sc_hd__dlrtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlrtp.functional.v, line:37:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__dlrtp (work@sky130_fd_sc_hd__dlrtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlrtp.functional.v, line:37:1, endln:59:10 |vpiName:RESET |vpiFullName:work@sky130_fd_sc_hd__dlrtp.RESET |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__dlrtp.buf_Q), line:52:10, endln:52:15 |vpiParent: - \_module: work@sky130_fd_sc_hd__dlrtp (work@sky130_fd_sc_hd__dlrtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlrtp.functional.v, line:37:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__dlrtp (work@sky130_fd_sc_hd__dlrtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlrtp.functional.v, line:37:1, endln:59:10 |vpiName:buf_Q |vpiFullName:work@sky130_fd_sc_hd__dlrtp.buf_Q |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__dlrtp.Q), line:38:5, endln:38:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__dlrtp (work@sky130_fd_sc_hd__dlrtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlrtp.functional.v, line:37:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__dlrtp (work@sky130_fd_sc_hd__dlrtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlrtp.functional.v, line:37:1, endln:59:10 |vpiName:Q |vpiFullName:work@sky130_fd_sc_hd__dlrtp.Q |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__dlrtp.RESET_B), line:39:5, endln:39:12 |vpiParent: - \_module: work@sky130_fd_sc_hd__dlrtp (work@sky130_fd_sc_hd__dlrtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlrtp.functional.v, line:37:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__dlrtp (work@sky130_fd_sc_hd__dlrtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlrtp.functional.v, line:37:1, endln:59:10 |vpiName:RESET_B |vpiFullName:work@sky130_fd_sc_hd__dlrtp.RESET_B |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__dlrtp.D), line:40:5, endln:40:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__dlrtp (work@sky130_fd_sc_hd__dlrtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlrtp.functional.v, line:37:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__dlrtp (work@sky130_fd_sc_hd__dlrtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlrtp.functional.v, line:37:1, endln:59:10 |vpiName:D |vpiFullName:work@sky130_fd_sc_hd__dlrtp.D |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__dlrtp.GATE), line:41:5, endln:41:9 |vpiParent: - \_module: work@sky130_fd_sc_hd__dlrtp (work@sky130_fd_sc_hd__dlrtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlrtp.functional.v, line:37:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__dlrtp (work@sky130_fd_sc_hd__dlrtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlrtp.functional.v, line:37:1, endln:59:10 |vpiName:GATE |vpiFullName:work@sky130_fd_sc_hd__dlrtp.GATE |vpiPort: \_port: (Q), line:38:5, endln:38:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__dlrtp (work@sky130_fd_sc_hd__dlrtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlrtp.functional.v, line:37:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__dlrtp (work@sky130_fd_sc_hd__dlrtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlrtp.functional.v, line:37:1, endln:59:10 |vpiName:Q |vpiDirection:2 |vpiLowConn: @@ -48827,7 +48827,7 @@ design: (work@sky130_fd_sc_hd__dlrtp) |vpiPort: \_port: (RESET_B), line:39:5, endln:39:12 |vpiParent: - \_module: work@sky130_fd_sc_hd__dlrtp (work@sky130_fd_sc_hd__dlrtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlrtp.functional.v, line:37:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__dlrtp (work@sky130_fd_sc_hd__dlrtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlrtp.functional.v, line:37:1, endln:59:10 |vpiName:RESET_B |vpiDirection:1 |vpiLowConn: @@ -48839,7 +48839,7 @@ design: (work@sky130_fd_sc_hd__dlrtp) |vpiPort: \_port: (D), line:40:5, endln:40:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__dlrtp (work@sky130_fd_sc_hd__dlrtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlrtp.functional.v, line:37:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__dlrtp (work@sky130_fd_sc_hd__dlrtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlrtp.functional.v, line:37:1, endln:59:10 |vpiName:D |vpiDirection:1 |vpiLowConn: @@ -48851,7 +48851,7 @@ design: (work@sky130_fd_sc_hd__dlrtp) |vpiPort: \_port: (GATE), line:41:5, endln:41:9 |vpiParent: - \_module: work@sky130_fd_sc_hd__dlrtp (work@sky130_fd_sc_hd__dlrtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlrtp.functional.v, line:37:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__dlrtp (work@sky130_fd_sc_hd__dlrtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlrtp.functional.v, line:37:1, endln:59:10 |vpiName:GATE |vpiDirection:1 |vpiLowConn: @@ -48861,14 +48861,14 @@ design: (work@sky130_fd_sc_hd__dlrtp) |vpiTypedef: \_logic_typespec: , line:48:12, endln:48:12 |uhdmtopModules: -\_module: work@sky130_fd_sc_hd__dlrtp (work@sky130_fd_sc_hd__dlrtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlrtp.functional.v, line:37:1, endln:59:10 +\_module_inst: work@sky130_fd_sc_hd__dlrtp (work@sky130_fd_sc_hd__dlrtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlrtp.functional.v, line:37:1, endln:59:10 |vpiName:work@sky130_fd_sc_hd__dlrtp |vpiDefName:work@sky130_fd_sc_hd__dlrtp |vpiTop:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__dlrtp.RESET), line:51:10, endln:51:15 |vpiParent: - \_module: work@sky130_fd_sc_hd__dlrtp (work@sky130_fd_sc_hd__dlrtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlrtp.functional.v, line:37:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__dlrtp (work@sky130_fd_sc_hd__dlrtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlrtp.functional.v, line:37:1, endln:59:10 |vpiTypespec: \_logic_typespec: , line:51:5, endln:51:9 |vpiName:RESET @@ -48877,7 +48877,7 @@ design: (work@sky130_fd_sc_hd__dlrtp) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__dlrtp.buf_Q), line:52:10, endln:52:15 |vpiParent: - \_module: work@sky130_fd_sc_hd__dlrtp (work@sky130_fd_sc_hd__dlrtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlrtp.functional.v, line:37:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__dlrtp (work@sky130_fd_sc_hd__dlrtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlrtp.functional.v, line:37:1, endln:59:10 |vpiTypespec: \_logic_typespec: , line:52:5, endln:52:9 |vpiName:buf_Q @@ -48886,7 +48886,7 @@ design: (work@sky130_fd_sc_hd__dlrtp) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__dlrtp.Q), line:38:5, endln:38:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__dlrtp (work@sky130_fd_sc_hd__dlrtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlrtp.functional.v, line:37:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__dlrtp (work@sky130_fd_sc_hd__dlrtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlrtp.functional.v, line:37:1, endln:59:10 |vpiTypespec: \_logic_typespec: , line:45:12, endln:45:12 |vpiName:Q @@ -48894,7 +48894,7 @@ design: (work@sky130_fd_sc_hd__dlrtp) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__dlrtp.RESET_B), line:39:5, endln:39:12 |vpiParent: - \_module: work@sky130_fd_sc_hd__dlrtp (work@sky130_fd_sc_hd__dlrtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlrtp.functional.v, line:37:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__dlrtp (work@sky130_fd_sc_hd__dlrtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlrtp.functional.v, line:37:1, endln:59:10 |vpiTypespec: \_logic_typespec: , line:46:12, endln:46:12 |vpiName:RESET_B @@ -48902,7 +48902,7 @@ design: (work@sky130_fd_sc_hd__dlrtp) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__dlrtp.D), line:40:5, endln:40:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__dlrtp (work@sky130_fd_sc_hd__dlrtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlrtp.functional.v, line:37:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__dlrtp (work@sky130_fd_sc_hd__dlrtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlrtp.functional.v, line:37:1, endln:59:10 |vpiTypespec: \_logic_typespec: , line:47:12, endln:47:12 |vpiName:D @@ -48910,7 +48910,7 @@ design: (work@sky130_fd_sc_hd__dlrtp) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__dlrtp.GATE), line:41:5, endln:41:9 |vpiParent: - \_module: work@sky130_fd_sc_hd__dlrtp (work@sky130_fd_sc_hd__dlrtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlrtp.functional.v, line:37:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__dlrtp (work@sky130_fd_sc_hd__dlrtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlrtp.functional.v, line:37:1, endln:59:10 |vpiTypespec: \_logic_typespec: , line:48:12, endln:48:12 |vpiName:GATE @@ -48919,7 +48919,7 @@ design: (work@sky130_fd_sc_hd__dlrtp) |vpiPort: \_port: (Q), line:38:5, endln:38:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__dlrtp (work@sky130_fd_sc_hd__dlrtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlrtp.functional.v, line:37:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__dlrtp (work@sky130_fd_sc_hd__dlrtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlrtp.functional.v, line:37:1, endln:59:10 |vpiName:Q |vpiDirection:2 |vpiLowConn: @@ -48933,7 +48933,7 @@ design: (work@sky130_fd_sc_hd__dlrtp) |vpiPort: \_port: (RESET_B), line:39:5, endln:39:12 |vpiParent: - \_module: work@sky130_fd_sc_hd__dlrtp (work@sky130_fd_sc_hd__dlrtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlrtp.functional.v, line:37:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__dlrtp (work@sky130_fd_sc_hd__dlrtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlrtp.functional.v, line:37:1, endln:59:10 |vpiName:RESET_B |vpiDirection:1 |vpiLowConn: @@ -48947,7 +48947,7 @@ design: (work@sky130_fd_sc_hd__dlrtp) |vpiPort: \_port: (D), line:40:5, endln:40:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__dlrtp (work@sky130_fd_sc_hd__dlrtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlrtp.functional.v, line:37:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__dlrtp (work@sky130_fd_sc_hd__dlrtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlrtp.functional.v, line:37:1, endln:59:10 |vpiName:D |vpiDirection:1 |vpiLowConn: @@ -48961,7 +48961,7 @@ design: (work@sky130_fd_sc_hd__dlrtp) |vpiPort: \_port: (GATE), line:41:5, endln:41:9 |vpiParent: - \_module: work@sky130_fd_sc_hd__dlrtp (work@sky130_fd_sc_hd__dlrtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlrtp.functional.v, line:37:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__dlrtp (work@sky130_fd_sc_hd__dlrtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlrtp.functional.v, line:37:1, endln:59:10 |vpiName:GATE |vpiDirection:1 |vpiLowConn: @@ -48975,7 +48975,7 @@ design: (work@sky130_fd_sc_hd__dlrtp) |vpiPrimitive: \_gate: work@not (work@sky130_fd_sc_hd__dlrtp.not0), line:55:48, endln:55:81 |vpiParent: - \_module: work@sky130_fd_sc_hd__dlrtp (work@sky130_fd_sc_hd__dlrtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlrtp.functional.v, line:37:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__dlrtp (work@sky130_fd_sc_hd__dlrtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlrtp.functional.v, line:37:1, endln:59:10 |vpiDefName:work@not |vpiName:not0 |vpiFullName:work@sky130_fd_sc_hd__dlrtp.not0 @@ -49010,7 +49010,7 @@ design: (work@sky130_fd_sc_hd__dlrtp) |vpiPrimitive: \_udp: work@sky130_fd_sc_hd__udp_dlatch$PR (work@sky130_fd_sc_hd__dlrtp.dlatch0), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlrtp.functional.v, line:56:5, endln:56:71 |vpiParent: - \_module: work@sky130_fd_sc_hd__dlrtp (work@sky130_fd_sc_hd__dlrtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlrtp.functional.v, line:37:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__dlrtp (work@sky130_fd_sc_hd__dlrtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlrtp.functional.v, line:37:1, endln:59:10 |vpiDefName:work@sky130_fd_sc_hd__udp_dlatch$PR |vpiName:dlatch0 |vpiFullName:work@sky130_fd_sc_hd__dlrtp.dlatch0 @@ -49019,7 +49019,7 @@ design: (work@sky130_fd_sc_hd__dlrtp) |vpiPrimitive: \_gate: work@buf (work@sky130_fd_sc_hd__dlrtp.buf0), line:57:48, endln:57:81 |vpiParent: - \_module: work@sky130_fd_sc_hd__dlrtp (work@sky130_fd_sc_hd__dlrtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlrtp.functional.v, line:37:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__dlrtp (work@sky130_fd_sc_hd__dlrtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlrtp.functional.v, line:37:1, endln:59:10 |vpiDefName:work@buf |vpiName:buf0 |vpiFullName:work@sky130_fd_sc_hd__dlrtp.buf0 @@ -49062,7 +49062,7 @@ Processing: -cd cells/cells -DUNIT_DELAY -writepp -parse -nocache -nobuiltin -no design: (work@sky130_fd_sc_hd__and4bb) |vpiName:work@sky130_fd_sc_hd__and4bb |uhdmallModules: -\_module: work@sky130_fd_sc_hd__and4bb (work@sky130_fd_sc_hd__and4bb), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and4bb.functional.v, line:33:1, endln:57:10 +\_module_inst: work@sky130_fd_sc_hd__and4bb (work@sky130_fd_sc_hd__and4bb), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and4bb.functional.v, line:33:1, endln:57:10 |vpiParent: \_design: (work@sky130_fd_sc_hd__and4bb) |vpiFullName:work@sky130_fd_sc_hd__and4bb @@ -49070,51 +49070,51 @@ design: (work@sky130_fd_sc_hd__and4bb) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__and4bb.nor0_out), line:49:10, endln:49:18 |vpiParent: - \_module: work@sky130_fd_sc_hd__and4bb (work@sky130_fd_sc_hd__and4bb), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and4bb.functional.v, line:33:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__and4bb (work@sky130_fd_sc_hd__and4bb), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and4bb.functional.v, line:33:1, endln:57:10 |vpiName:nor0_out |vpiFullName:work@sky130_fd_sc_hd__and4bb.nor0_out |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__and4bb.and0_out_X), line:50:10, endln:50:20 |vpiParent: - \_module: work@sky130_fd_sc_hd__and4bb (work@sky130_fd_sc_hd__and4bb), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and4bb.functional.v, line:33:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__and4bb (work@sky130_fd_sc_hd__and4bb), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and4bb.functional.v, line:33:1, endln:57:10 |vpiName:and0_out_X |vpiFullName:work@sky130_fd_sc_hd__and4bb.and0_out_X |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__and4bb.X), line:34:5, endln:34:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__and4bb (work@sky130_fd_sc_hd__and4bb), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and4bb.functional.v, line:33:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__and4bb (work@sky130_fd_sc_hd__and4bb), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and4bb.functional.v, line:33:1, endln:57:10 |vpiName:X |vpiFullName:work@sky130_fd_sc_hd__and4bb.X |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__and4bb.A_N), line:35:5, endln:35:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__and4bb (work@sky130_fd_sc_hd__and4bb), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and4bb.functional.v, line:33:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__and4bb (work@sky130_fd_sc_hd__and4bb), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and4bb.functional.v, line:33:1, endln:57:10 |vpiName:A_N |vpiFullName:work@sky130_fd_sc_hd__and4bb.A_N |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__and4bb.B_N), line:36:5, endln:36:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__and4bb (work@sky130_fd_sc_hd__and4bb), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and4bb.functional.v, line:33:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__and4bb (work@sky130_fd_sc_hd__and4bb), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and4bb.functional.v, line:33:1, endln:57:10 |vpiName:B_N |vpiFullName:work@sky130_fd_sc_hd__and4bb.B_N |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__and4bb.C), line:37:5, endln:37:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__and4bb (work@sky130_fd_sc_hd__and4bb), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and4bb.functional.v, line:33:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__and4bb (work@sky130_fd_sc_hd__and4bb), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and4bb.functional.v, line:33:1, endln:57:10 |vpiName:C |vpiFullName:work@sky130_fd_sc_hd__and4bb.C |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__and4bb.D), line:38:5, endln:38:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__and4bb (work@sky130_fd_sc_hd__and4bb), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and4bb.functional.v, line:33:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__and4bb (work@sky130_fd_sc_hd__and4bb), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and4bb.functional.v, line:33:1, endln:57:10 |vpiName:D |vpiFullName:work@sky130_fd_sc_hd__and4bb.D |vpiPort: \_port: (X), line:34:5, endln:34:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__and4bb (work@sky130_fd_sc_hd__and4bb), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and4bb.functional.v, line:33:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__and4bb (work@sky130_fd_sc_hd__and4bb), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and4bb.functional.v, line:33:1, endln:57:10 |vpiName:X |vpiDirection:2 |vpiLowConn: @@ -49126,7 +49126,7 @@ design: (work@sky130_fd_sc_hd__and4bb) |vpiPort: \_port: (A_N), line:35:5, endln:35:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__and4bb (work@sky130_fd_sc_hd__and4bb), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and4bb.functional.v, line:33:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__and4bb (work@sky130_fd_sc_hd__and4bb), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and4bb.functional.v, line:33:1, endln:57:10 |vpiName:A_N |vpiDirection:1 |vpiLowConn: @@ -49138,7 +49138,7 @@ design: (work@sky130_fd_sc_hd__and4bb) |vpiPort: \_port: (B_N), line:36:5, endln:36:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__and4bb (work@sky130_fd_sc_hd__and4bb), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and4bb.functional.v, line:33:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__and4bb (work@sky130_fd_sc_hd__and4bb), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and4bb.functional.v, line:33:1, endln:57:10 |vpiName:B_N |vpiDirection:1 |vpiLowConn: @@ -49150,7 +49150,7 @@ design: (work@sky130_fd_sc_hd__and4bb) |vpiPort: \_port: (C), line:37:5, endln:37:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__and4bb (work@sky130_fd_sc_hd__and4bb), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and4bb.functional.v, line:33:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__and4bb (work@sky130_fd_sc_hd__and4bb), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and4bb.functional.v, line:33:1, endln:57:10 |vpiName:C |vpiDirection:1 |vpiLowConn: @@ -49162,7 +49162,7 @@ design: (work@sky130_fd_sc_hd__and4bb) |vpiPort: \_port: (D), line:38:5, endln:38:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__and4bb (work@sky130_fd_sc_hd__and4bb), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and4bb.functional.v, line:33:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__and4bb (work@sky130_fd_sc_hd__and4bb), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and4bb.functional.v, line:33:1, endln:57:10 |vpiName:D |vpiDirection:1 |vpiLowConn: @@ -49172,14 +49172,14 @@ design: (work@sky130_fd_sc_hd__and4bb) |vpiTypedef: \_logic_typespec: , line:46:12, endln:46:12 |uhdmtopModules: -\_module: work@sky130_fd_sc_hd__and4bb (work@sky130_fd_sc_hd__and4bb), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and4bb.functional.v, line:33:1, endln:57:10 +\_module_inst: work@sky130_fd_sc_hd__and4bb (work@sky130_fd_sc_hd__and4bb), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and4bb.functional.v, line:33:1, endln:57:10 |vpiName:work@sky130_fd_sc_hd__and4bb |vpiDefName:work@sky130_fd_sc_hd__and4bb |vpiTop:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__and4bb.nor0_out), line:49:10, endln:49:18 |vpiParent: - \_module: work@sky130_fd_sc_hd__and4bb (work@sky130_fd_sc_hd__and4bb), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and4bb.functional.v, line:33:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__and4bb (work@sky130_fd_sc_hd__and4bb), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and4bb.functional.v, line:33:1, endln:57:10 |vpiTypespec: \_logic_typespec: , line:49:5, endln:49:9 |vpiName:nor0_out @@ -49188,7 +49188,7 @@ design: (work@sky130_fd_sc_hd__and4bb) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__and4bb.and0_out_X), line:50:10, endln:50:20 |vpiParent: - \_module: work@sky130_fd_sc_hd__and4bb (work@sky130_fd_sc_hd__and4bb), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and4bb.functional.v, line:33:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__and4bb (work@sky130_fd_sc_hd__and4bb), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and4bb.functional.v, line:33:1, endln:57:10 |vpiTypespec: \_logic_typespec: , line:50:5, endln:50:9 |vpiName:and0_out_X @@ -49197,7 +49197,7 @@ design: (work@sky130_fd_sc_hd__and4bb) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__and4bb.X), line:34:5, endln:34:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__and4bb (work@sky130_fd_sc_hd__and4bb), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and4bb.functional.v, line:33:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__and4bb (work@sky130_fd_sc_hd__and4bb), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and4bb.functional.v, line:33:1, endln:57:10 |vpiTypespec: \_logic_typespec: , line:42:12, endln:42:12 |vpiName:X @@ -49205,7 +49205,7 @@ design: (work@sky130_fd_sc_hd__and4bb) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__and4bb.A_N), line:35:5, endln:35:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__and4bb (work@sky130_fd_sc_hd__and4bb), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and4bb.functional.v, line:33:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__and4bb (work@sky130_fd_sc_hd__and4bb), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and4bb.functional.v, line:33:1, endln:57:10 |vpiTypespec: \_logic_typespec: , line:43:12, endln:43:12 |vpiName:A_N @@ -49213,7 +49213,7 @@ design: (work@sky130_fd_sc_hd__and4bb) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__and4bb.B_N), line:36:5, endln:36:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__and4bb (work@sky130_fd_sc_hd__and4bb), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and4bb.functional.v, line:33:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__and4bb (work@sky130_fd_sc_hd__and4bb), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and4bb.functional.v, line:33:1, endln:57:10 |vpiTypespec: \_logic_typespec: , line:44:12, endln:44:12 |vpiName:B_N @@ -49221,7 +49221,7 @@ design: (work@sky130_fd_sc_hd__and4bb) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__and4bb.C), line:37:5, endln:37:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__and4bb (work@sky130_fd_sc_hd__and4bb), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and4bb.functional.v, line:33:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__and4bb (work@sky130_fd_sc_hd__and4bb), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and4bb.functional.v, line:33:1, endln:57:10 |vpiTypespec: \_logic_typespec: , line:45:12, endln:45:12 |vpiName:C @@ -49229,7 +49229,7 @@ design: (work@sky130_fd_sc_hd__and4bb) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__and4bb.D), line:38:5, endln:38:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__and4bb (work@sky130_fd_sc_hd__and4bb), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and4bb.functional.v, line:33:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__and4bb (work@sky130_fd_sc_hd__and4bb), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and4bb.functional.v, line:33:1, endln:57:10 |vpiTypespec: \_logic_typespec: , line:46:12, endln:46:12 |vpiName:D @@ -49238,7 +49238,7 @@ design: (work@sky130_fd_sc_hd__and4bb) |vpiPort: \_port: (X), line:34:5, endln:34:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__and4bb (work@sky130_fd_sc_hd__and4bb), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and4bb.functional.v, line:33:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__and4bb (work@sky130_fd_sc_hd__and4bb), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and4bb.functional.v, line:33:1, endln:57:10 |vpiName:X |vpiDirection:2 |vpiLowConn: @@ -49252,7 +49252,7 @@ design: (work@sky130_fd_sc_hd__and4bb) |vpiPort: \_port: (A_N), line:35:5, endln:35:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__and4bb (work@sky130_fd_sc_hd__and4bb), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and4bb.functional.v, line:33:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__and4bb (work@sky130_fd_sc_hd__and4bb), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and4bb.functional.v, line:33:1, endln:57:10 |vpiName:A_N |vpiDirection:1 |vpiLowConn: @@ -49266,7 +49266,7 @@ design: (work@sky130_fd_sc_hd__and4bb) |vpiPort: \_port: (B_N), line:36:5, endln:36:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__and4bb (work@sky130_fd_sc_hd__and4bb), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and4bb.functional.v, line:33:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__and4bb (work@sky130_fd_sc_hd__and4bb), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and4bb.functional.v, line:33:1, endln:57:10 |vpiName:B_N |vpiDirection:1 |vpiLowConn: @@ -49280,7 +49280,7 @@ design: (work@sky130_fd_sc_hd__and4bb) |vpiPort: \_port: (C), line:37:5, endln:37:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__and4bb (work@sky130_fd_sc_hd__and4bb), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and4bb.functional.v, line:33:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__and4bb (work@sky130_fd_sc_hd__and4bb), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and4bb.functional.v, line:33:1, endln:57:10 |vpiName:C |vpiDirection:1 |vpiLowConn: @@ -49294,7 +49294,7 @@ design: (work@sky130_fd_sc_hd__and4bb) |vpiPort: \_port: (D), line:38:5, endln:38:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__and4bb (work@sky130_fd_sc_hd__and4bb), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and4bb.functional.v, line:33:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__and4bb (work@sky130_fd_sc_hd__and4bb), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and4bb.functional.v, line:33:1, endln:57:10 |vpiName:D |vpiDirection:1 |vpiLowConn: @@ -49308,7 +49308,7 @@ design: (work@sky130_fd_sc_hd__and4bb) |vpiPrimitive: \_gate: work@nor (work@sky130_fd_sc_hd__and4bb.nor0), line:53:9, endln:53:43 |vpiParent: - \_module: work@sky130_fd_sc_hd__and4bb (work@sky130_fd_sc_hd__and4bb), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and4bb.functional.v, line:33:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__and4bb (work@sky130_fd_sc_hd__and4bb), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and4bb.functional.v, line:33:1, endln:57:10 |vpiDefName:work@nor |vpiName:nor0 |vpiFullName:work@sky130_fd_sc_hd__and4bb.nor0 @@ -49357,7 +49357,7 @@ design: (work@sky130_fd_sc_hd__and4bb) |vpiPrimitive: \_gate: work@and (work@sky130_fd_sc_hd__and4bb.and0), line:54:9, endln:54:43 |vpiParent: - \_module: work@sky130_fd_sc_hd__and4bb (work@sky130_fd_sc_hd__and4bb), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and4bb.functional.v, line:33:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__and4bb (work@sky130_fd_sc_hd__and4bb), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and4bb.functional.v, line:33:1, endln:57:10 |vpiDefName:work@and |vpiName:and0 |vpiFullName:work@sky130_fd_sc_hd__and4bb.and0 @@ -49420,7 +49420,7 @@ design: (work@sky130_fd_sc_hd__and4bb) |vpiPrimitive: \_gate: work@buf (work@sky130_fd_sc_hd__and4bb.buf0), line:55:9, endln:55:43 |vpiParent: - \_module: work@sky130_fd_sc_hd__and4bb (work@sky130_fd_sc_hd__and4bb), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and4bb.functional.v, line:33:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__and4bb (work@sky130_fd_sc_hd__and4bb), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and4bb.functional.v, line:33:1, endln:57:10 |vpiDefName:work@buf |vpiName:buf0 |vpiFullName:work@sky130_fd_sc_hd__and4bb.buf0 @@ -49463,7 +49463,7 @@ Processing: -cd cells/cells -DUNIT_DELAY -writepp -parse -nocache -nobuiltin -no design: (work@sky130_fd_sc_hd__a41o) |vpiName:work@sky130_fd_sc_hd__a41o |uhdmallModules: -\_module: work@sky130_fd_sc_hd__a41o (work@sky130_fd_sc_hd__a41o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a41o.functional.v, line:35:1, endln:61:10 +\_module_inst: work@sky130_fd_sc_hd__a41o (work@sky130_fd_sc_hd__a41o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a41o.functional.v, line:35:1, endln:61:10 |vpiParent: \_design: (work@sky130_fd_sc_hd__a41o) |vpiFullName:work@sky130_fd_sc_hd__a41o @@ -49471,57 +49471,57 @@ design: (work@sky130_fd_sc_hd__a41o) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a41o.and0_out), line:53:10, endln:53:18 |vpiParent: - \_module: work@sky130_fd_sc_hd__a41o (work@sky130_fd_sc_hd__a41o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a41o.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__a41o (work@sky130_fd_sc_hd__a41o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a41o.functional.v, line:35:1, endln:61:10 |vpiName:and0_out |vpiFullName:work@sky130_fd_sc_hd__a41o.and0_out |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a41o.or0_out_X), line:54:10, endln:54:19 |vpiParent: - \_module: work@sky130_fd_sc_hd__a41o (work@sky130_fd_sc_hd__a41o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a41o.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__a41o (work@sky130_fd_sc_hd__a41o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a41o.functional.v, line:35:1, endln:61:10 |vpiName:or0_out_X |vpiFullName:work@sky130_fd_sc_hd__a41o.or0_out_X |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a41o.X), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__a41o (work@sky130_fd_sc_hd__a41o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a41o.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__a41o (work@sky130_fd_sc_hd__a41o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a41o.functional.v, line:35:1, endln:61:10 |vpiName:X |vpiFullName:work@sky130_fd_sc_hd__a41o.X |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a41o.A1), line:37:5, endln:37:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a41o (work@sky130_fd_sc_hd__a41o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a41o.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__a41o (work@sky130_fd_sc_hd__a41o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a41o.functional.v, line:35:1, endln:61:10 |vpiName:A1 |vpiFullName:work@sky130_fd_sc_hd__a41o.A1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a41o.A2), line:38:5, endln:38:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a41o (work@sky130_fd_sc_hd__a41o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a41o.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__a41o (work@sky130_fd_sc_hd__a41o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a41o.functional.v, line:35:1, endln:61:10 |vpiName:A2 |vpiFullName:work@sky130_fd_sc_hd__a41o.A2 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a41o.A3), line:39:5, endln:39:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a41o (work@sky130_fd_sc_hd__a41o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a41o.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__a41o (work@sky130_fd_sc_hd__a41o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a41o.functional.v, line:35:1, endln:61:10 |vpiName:A3 |vpiFullName:work@sky130_fd_sc_hd__a41o.A3 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a41o.A4), line:40:5, endln:40:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a41o (work@sky130_fd_sc_hd__a41o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a41o.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__a41o (work@sky130_fd_sc_hd__a41o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a41o.functional.v, line:35:1, endln:61:10 |vpiName:A4 |vpiFullName:work@sky130_fd_sc_hd__a41o.A4 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a41o.B1), line:41:5, endln:41:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a41o (work@sky130_fd_sc_hd__a41o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a41o.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__a41o (work@sky130_fd_sc_hd__a41o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a41o.functional.v, line:35:1, endln:61:10 |vpiName:B1 |vpiFullName:work@sky130_fd_sc_hd__a41o.B1 |vpiPort: \_port: (X), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__a41o (work@sky130_fd_sc_hd__a41o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a41o.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__a41o (work@sky130_fd_sc_hd__a41o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a41o.functional.v, line:35:1, endln:61:10 |vpiName:X |vpiDirection:2 |vpiLowConn: @@ -49533,7 +49533,7 @@ design: (work@sky130_fd_sc_hd__a41o) |vpiPort: \_port: (A1), line:37:5, endln:37:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a41o (work@sky130_fd_sc_hd__a41o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a41o.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__a41o (work@sky130_fd_sc_hd__a41o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a41o.functional.v, line:35:1, endln:61:10 |vpiName:A1 |vpiDirection:1 |vpiLowConn: @@ -49545,7 +49545,7 @@ design: (work@sky130_fd_sc_hd__a41o) |vpiPort: \_port: (A2), line:38:5, endln:38:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a41o (work@sky130_fd_sc_hd__a41o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a41o.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__a41o (work@sky130_fd_sc_hd__a41o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a41o.functional.v, line:35:1, endln:61:10 |vpiName:A2 |vpiDirection:1 |vpiLowConn: @@ -49557,7 +49557,7 @@ design: (work@sky130_fd_sc_hd__a41o) |vpiPort: \_port: (A3), line:39:5, endln:39:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a41o (work@sky130_fd_sc_hd__a41o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a41o.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__a41o (work@sky130_fd_sc_hd__a41o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a41o.functional.v, line:35:1, endln:61:10 |vpiName:A3 |vpiDirection:1 |vpiLowConn: @@ -49569,7 +49569,7 @@ design: (work@sky130_fd_sc_hd__a41o) |vpiPort: \_port: (A4), line:40:5, endln:40:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a41o (work@sky130_fd_sc_hd__a41o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a41o.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__a41o (work@sky130_fd_sc_hd__a41o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a41o.functional.v, line:35:1, endln:61:10 |vpiName:A4 |vpiDirection:1 |vpiLowConn: @@ -49581,7 +49581,7 @@ design: (work@sky130_fd_sc_hd__a41o) |vpiPort: \_port: (B1), line:41:5, endln:41:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a41o (work@sky130_fd_sc_hd__a41o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a41o.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__a41o (work@sky130_fd_sc_hd__a41o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a41o.functional.v, line:35:1, endln:61:10 |vpiName:B1 |vpiDirection:1 |vpiLowConn: @@ -49591,14 +49591,14 @@ design: (work@sky130_fd_sc_hd__a41o) |vpiTypedef: \_logic_typespec: , line:50:12, endln:50:12 |uhdmtopModules: -\_module: work@sky130_fd_sc_hd__a41o (work@sky130_fd_sc_hd__a41o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a41o.functional.v, line:35:1, endln:61:10 +\_module_inst: work@sky130_fd_sc_hd__a41o (work@sky130_fd_sc_hd__a41o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a41o.functional.v, line:35:1, endln:61:10 |vpiName:work@sky130_fd_sc_hd__a41o |vpiDefName:work@sky130_fd_sc_hd__a41o |vpiTop:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a41o.and0_out), line:53:10, endln:53:18 |vpiParent: - \_module: work@sky130_fd_sc_hd__a41o (work@sky130_fd_sc_hd__a41o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a41o.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__a41o (work@sky130_fd_sc_hd__a41o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a41o.functional.v, line:35:1, endln:61:10 |vpiTypespec: \_logic_typespec: , line:53:5, endln:53:9 |vpiName:and0_out @@ -49607,7 +49607,7 @@ design: (work@sky130_fd_sc_hd__a41o) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a41o.or0_out_X), line:54:10, endln:54:19 |vpiParent: - \_module: work@sky130_fd_sc_hd__a41o (work@sky130_fd_sc_hd__a41o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a41o.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__a41o (work@sky130_fd_sc_hd__a41o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a41o.functional.v, line:35:1, endln:61:10 |vpiTypespec: \_logic_typespec: , line:54:5, endln:54:9 |vpiName:or0_out_X @@ -49616,7 +49616,7 @@ design: (work@sky130_fd_sc_hd__a41o) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a41o.X), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__a41o (work@sky130_fd_sc_hd__a41o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a41o.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__a41o (work@sky130_fd_sc_hd__a41o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a41o.functional.v, line:35:1, endln:61:10 |vpiTypespec: \_logic_typespec: , line:45:12, endln:45:12 |vpiName:X @@ -49624,7 +49624,7 @@ design: (work@sky130_fd_sc_hd__a41o) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a41o.A1), line:37:5, endln:37:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a41o (work@sky130_fd_sc_hd__a41o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a41o.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__a41o (work@sky130_fd_sc_hd__a41o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a41o.functional.v, line:35:1, endln:61:10 |vpiTypespec: \_logic_typespec: , line:46:12, endln:46:12 |vpiName:A1 @@ -49632,7 +49632,7 @@ design: (work@sky130_fd_sc_hd__a41o) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a41o.A2), line:38:5, endln:38:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a41o (work@sky130_fd_sc_hd__a41o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a41o.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__a41o (work@sky130_fd_sc_hd__a41o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a41o.functional.v, line:35:1, endln:61:10 |vpiTypespec: \_logic_typespec: , line:47:12, endln:47:12 |vpiName:A2 @@ -49640,7 +49640,7 @@ design: (work@sky130_fd_sc_hd__a41o) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a41o.A3), line:39:5, endln:39:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a41o (work@sky130_fd_sc_hd__a41o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a41o.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__a41o (work@sky130_fd_sc_hd__a41o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a41o.functional.v, line:35:1, endln:61:10 |vpiTypespec: \_logic_typespec: , line:48:12, endln:48:12 |vpiName:A3 @@ -49648,7 +49648,7 @@ design: (work@sky130_fd_sc_hd__a41o) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a41o.A4), line:40:5, endln:40:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a41o (work@sky130_fd_sc_hd__a41o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a41o.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__a41o (work@sky130_fd_sc_hd__a41o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a41o.functional.v, line:35:1, endln:61:10 |vpiTypespec: \_logic_typespec: , line:49:12, endln:49:12 |vpiName:A4 @@ -49656,7 +49656,7 @@ design: (work@sky130_fd_sc_hd__a41o) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a41o.B1), line:41:5, endln:41:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a41o (work@sky130_fd_sc_hd__a41o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a41o.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__a41o (work@sky130_fd_sc_hd__a41o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a41o.functional.v, line:35:1, endln:61:10 |vpiTypespec: \_logic_typespec: , line:50:12, endln:50:12 |vpiName:B1 @@ -49665,7 +49665,7 @@ design: (work@sky130_fd_sc_hd__a41o) |vpiPort: \_port: (X), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__a41o (work@sky130_fd_sc_hd__a41o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a41o.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__a41o (work@sky130_fd_sc_hd__a41o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a41o.functional.v, line:35:1, endln:61:10 |vpiName:X |vpiDirection:2 |vpiLowConn: @@ -49679,7 +49679,7 @@ design: (work@sky130_fd_sc_hd__a41o) |vpiPort: \_port: (A1), line:37:5, endln:37:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a41o (work@sky130_fd_sc_hd__a41o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a41o.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__a41o (work@sky130_fd_sc_hd__a41o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a41o.functional.v, line:35:1, endln:61:10 |vpiName:A1 |vpiDirection:1 |vpiLowConn: @@ -49693,7 +49693,7 @@ design: (work@sky130_fd_sc_hd__a41o) |vpiPort: \_port: (A2), line:38:5, endln:38:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a41o (work@sky130_fd_sc_hd__a41o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a41o.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__a41o (work@sky130_fd_sc_hd__a41o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a41o.functional.v, line:35:1, endln:61:10 |vpiName:A2 |vpiDirection:1 |vpiLowConn: @@ -49707,7 +49707,7 @@ design: (work@sky130_fd_sc_hd__a41o) |vpiPort: \_port: (A3), line:39:5, endln:39:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a41o (work@sky130_fd_sc_hd__a41o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a41o.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__a41o (work@sky130_fd_sc_hd__a41o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a41o.functional.v, line:35:1, endln:61:10 |vpiName:A3 |vpiDirection:1 |vpiLowConn: @@ -49721,7 +49721,7 @@ design: (work@sky130_fd_sc_hd__a41o) |vpiPort: \_port: (A4), line:40:5, endln:40:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a41o (work@sky130_fd_sc_hd__a41o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a41o.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__a41o (work@sky130_fd_sc_hd__a41o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a41o.functional.v, line:35:1, endln:61:10 |vpiName:A4 |vpiDirection:1 |vpiLowConn: @@ -49735,7 +49735,7 @@ design: (work@sky130_fd_sc_hd__a41o) |vpiPort: \_port: (B1), line:41:5, endln:41:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a41o (work@sky130_fd_sc_hd__a41o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a41o.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__a41o (work@sky130_fd_sc_hd__a41o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a41o.functional.v, line:35:1, endln:61:10 |vpiName:B1 |vpiDirection:1 |vpiLowConn: @@ -49749,7 +49749,7 @@ design: (work@sky130_fd_sc_hd__a41o) |vpiPrimitive: \_gate: work@and (work@sky130_fd_sc_hd__a41o.and0), line:57:9, endln:57:42 |vpiParent: - \_module: work@sky130_fd_sc_hd__a41o (work@sky130_fd_sc_hd__a41o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a41o.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__a41o (work@sky130_fd_sc_hd__a41o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a41o.functional.v, line:35:1, endln:61:10 |vpiDefName:work@and |vpiName:and0 |vpiFullName:work@sky130_fd_sc_hd__a41o.and0 @@ -49826,7 +49826,7 @@ design: (work@sky130_fd_sc_hd__a41o) |vpiPrimitive: \_gate: work@or (work@sky130_fd_sc_hd__a41o.or0), line:58:9, endln:58:42 |vpiParent: - \_module: work@sky130_fd_sc_hd__a41o (work@sky130_fd_sc_hd__a41o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a41o.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__a41o (work@sky130_fd_sc_hd__a41o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a41o.functional.v, line:35:1, endln:61:10 |vpiDefName:work@or |vpiName:or0 |vpiFullName:work@sky130_fd_sc_hd__a41o.or0 @@ -49875,7 +49875,7 @@ design: (work@sky130_fd_sc_hd__a41o) |vpiPrimitive: \_gate: work@buf (work@sky130_fd_sc_hd__a41o.buf0), line:59:9, endln:59:42 |vpiParent: - \_module: work@sky130_fd_sc_hd__a41o (work@sky130_fd_sc_hd__a41o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a41o.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__a41o (work@sky130_fd_sc_hd__a41o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a41o.functional.v, line:35:1, endln:61:10 |vpiDefName:work@buf |vpiName:buf0 |vpiFullName:work@sky130_fd_sc_hd__a41o.buf0 @@ -49918,7 +49918,7 @@ Processing: -cd cells/cells -DUNIT_DELAY -writepp -parse -nocache -nobuiltin -no design: (work@sky130_fd_sc_hd__ha) |vpiName:work@sky130_fd_sc_hd__ha |uhdmallModules: -\_module: work@sky130_fd_sc_hd__ha (work@sky130_fd_sc_hd__ha), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__ha.functional.v, line:33:1, endln:56:10 +\_module_inst: work@sky130_fd_sc_hd__ha (work@sky130_fd_sc_hd__ha), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__ha.functional.v, line:33:1, endln:56:10 |vpiParent: \_design: (work@sky130_fd_sc_hd__ha) |vpiFullName:work@sky130_fd_sc_hd__ha @@ -49926,45 +49926,45 @@ design: (work@sky130_fd_sc_hd__ha) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__ha.and0_out_COUT), line:47:10, endln:47:23 |vpiParent: - \_module: work@sky130_fd_sc_hd__ha (work@sky130_fd_sc_hd__ha), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__ha.functional.v, line:33:1, endln:56:10 + \_module_inst: work@sky130_fd_sc_hd__ha (work@sky130_fd_sc_hd__ha), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__ha.functional.v, line:33:1, endln:56:10 |vpiName:and0_out_COUT |vpiFullName:work@sky130_fd_sc_hd__ha.and0_out_COUT |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__ha.xor0_out_SUM), line:48:10, endln:48:22 |vpiParent: - \_module: work@sky130_fd_sc_hd__ha (work@sky130_fd_sc_hd__ha), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__ha.functional.v, line:33:1, endln:56:10 + \_module_inst: work@sky130_fd_sc_hd__ha (work@sky130_fd_sc_hd__ha), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__ha.functional.v, line:33:1, endln:56:10 |vpiName:xor0_out_SUM |vpiFullName:work@sky130_fd_sc_hd__ha.xor0_out_SUM |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__ha.COUT), line:34:5, endln:34:9 |vpiParent: - \_module: work@sky130_fd_sc_hd__ha (work@sky130_fd_sc_hd__ha), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__ha.functional.v, line:33:1, endln:56:10 + \_module_inst: work@sky130_fd_sc_hd__ha (work@sky130_fd_sc_hd__ha), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__ha.functional.v, line:33:1, endln:56:10 |vpiName:COUT |vpiFullName:work@sky130_fd_sc_hd__ha.COUT |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__ha.SUM), line:35:5, endln:35:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__ha (work@sky130_fd_sc_hd__ha), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__ha.functional.v, line:33:1, endln:56:10 + \_module_inst: work@sky130_fd_sc_hd__ha (work@sky130_fd_sc_hd__ha), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__ha.functional.v, line:33:1, endln:56:10 |vpiName:SUM |vpiFullName:work@sky130_fd_sc_hd__ha.SUM |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__ha.A), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__ha (work@sky130_fd_sc_hd__ha), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__ha.functional.v, line:33:1, endln:56:10 + \_module_inst: work@sky130_fd_sc_hd__ha (work@sky130_fd_sc_hd__ha), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__ha.functional.v, line:33:1, endln:56:10 |vpiName:A |vpiFullName:work@sky130_fd_sc_hd__ha.A |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__ha.B), line:37:5, endln:37:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__ha (work@sky130_fd_sc_hd__ha), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__ha.functional.v, line:33:1, endln:56:10 + \_module_inst: work@sky130_fd_sc_hd__ha (work@sky130_fd_sc_hd__ha), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__ha.functional.v, line:33:1, endln:56:10 |vpiName:B |vpiFullName:work@sky130_fd_sc_hd__ha.B |vpiPort: \_port: (COUT), line:34:5, endln:34:9 |vpiParent: - \_module: work@sky130_fd_sc_hd__ha (work@sky130_fd_sc_hd__ha), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__ha.functional.v, line:33:1, endln:56:10 + \_module_inst: work@sky130_fd_sc_hd__ha (work@sky130_fd_sc_hd__ha), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__ha.functional.v, line:33:1, endln:56:10 |vpiName:COUT |vpiDirection:2 |vpiLowConn: @@ -49976,7 +49976,7 @@ design: (work@sky130_fd_sc_hd__ha) |vpiPort: \_port: (SUM), line:35:5, endln:35:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__ha (work@sky130_fd_sc_hd__ha), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__ha.functional.v, line:33:1, endln:56:10 + \_module_inst: work@sky130_fd_sc_hd__ha (work@sky130_fd_sc_hd__ha), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__ha.functional.v, line:33:1, endln:56:10 |vpiName:SUM |vpiDirection:2 |vpiLowConn: @@ -49988,7 +49988,7 @@ design: (work@sky130_fd_sc_hd__ha) |vpiPort: \_port: (A), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__ha (work@sky130_fd_sc_hd__ha), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__ha.functional.v, line:33:1, endln:56:10 + \_module_inst: work@sky130_fd_sc_hd__ha (work@sky130_fd_sc_hd__ha), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__ha.functional.v, line:33:1, endln:56:10 |vpiName:A |vpiDirection:1 |vpiLowConn: @@ -50000,7 +50000,7 @@ design: (work@sky130_fd_sc_hd__ha) |vpiPort: \_port: (B), line:37:5, endln:37:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__ha (work@sky130_fd_sc_hd__ha), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__ha.functional.v, line:33:1, endln:56:10 + \_module_inst: work@sky130_fd_sc_hd__ha (work@sky130_fd_sc_hd__ha), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__ha.functional.v, line:33:1, endln:56:10 |vpiName:B |vpiDirection:1 |vpiLowConn: @@ -50010,14 +50010,14 @@ design: (work@sky130_fd_sc_hd__ha) |vpiTypedef: \_logic_typespec: , line:44:12, endln:44:12 |uhdmtopModules: -\_module: work@sky130_fd_sc_hd__ha (work@sky130_fd_sc_hd__ha), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__ha.functional.v, line:33:1, endln:56:10 +\_module_inst: work@sky130_fd_sc_hd__ha (work@sky130_fd_sc_hd__ha), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__ha.functional.v, line:33:1, endln:56:10 |vpiName:work@sky130_fd_sc_hd__ha |vpiDefName:work@sky130_fd_sc_hd__ha |vpiTop:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__ha.and0_out_COUT), line:47:10, endln:47:23 |vpiParent: - \_module: work@sky130_fd_sc_hd__ha (work@sky130_fd_sc_hd__ha), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__ha.functional.v, line:33:1, endln:56:10 + \_module_inst: work@sky130_fd_sc_hd__ha (work@sky130_fd_sc_hd__ha), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__ha.functional.v, line:33:1, endln:56:10 |vpiTypespec: \_logic_typespec: , line:47:5, endln:47:9 |vpiName:and0_out_COUT @@ -50026,7 +50026,7 @@ design: (work@sky130_fd_sc_hd__ha) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__ha.xor0_out_SUM), line:48:10, endln:48:22 |vpiParent: - \_module: work@sky130_fd_sc_hd__ha (work@sky130_fd_sc_hd__ha), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__ha.functional.v, line:33:1, endln:56:10 + \_module_inst: work@sky130_fd_sc_hd__ha (work@sky130_fd_sc_hd__ha), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__ha.functional.v, line:33:1, endln:56:10 |vpiTypespec: \_logic_typespec: , line:48:5, endln:48:9 |vpiName:xor0_out_SUM @@ -50035,7 +50035,7 @@ design: (work@sky130_fd_sc_hd__ha) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__ha.COUT), line:34:5, endln:34:9 |vpiParent: - \_module: work@sky130_fd_sc_hd__ha (work@sky130_fd_sc_hd__ha), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__ha.functional.v, line:33:1, endln:56:10 + \_module_inst: work@sky130_fd_sc_hd__ha (work@sky130_fd_sc_hd__ha), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__ha.functional.v, line:33:1, endln:56:10 |vpiTypespec: \_logic_typespec: , line:41:12, endln:41:12 |vpiName:COUT @@ -50043,7 +50043,7 @@ design: (work@sky130_fd_sc_hd__ha) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__ha.SUM), line:35:5, endln:35:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__ha (work@sky130_fd_sc_hd__ha), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__ha.functional.v, line:33:1, endln:56:10 + \_module_inst: work@sky130_fd_sc_hd__ha (work@sky130_fd_sc_hd__ha), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__ha.functional.v, line:33:1, endln:56:10 |vpiTypespec: \_logic_typespec: , line:42:12, endln:42:12 |vpiName:SUM @@ -50051,7 +50051,7 @@ design: (work@sky130_fd_sc_hd__ha) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__ha.A), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__ha (work@sky130_fd_sc_hd__ha), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__ha.functional.v, line:33:1, endln:56:10 + \_module_inst: work@sky130_fd_sc_hd__ha (work@sky130_fd_sc_hd__ha), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__ha.functional.v, line:33:1, endln:56:10 |vpiTypespec: \_logic_typespec: , line:43:12, endln:43:12 |vpiName:A @@ -50059,7 +50059,7 @@ design: (work@sky130_fd_sc_hd__ha) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__ha.B), line:37:5, endln:37:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__ha (work@sky130_fd_sc_hd__ha), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__ha.functional.v, line:33:1, endln:56:10 + \_module_inst: work@sky130_fd_sc_hd__ha (work@sky130_fd_sc_hd__ha), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__ha.functional.v, line:33:1, endln:56:10 |vpiTypespec: \_logic_typespec: , line:44:12, endln:44:12 |vpiName:B @@ -50068,7 +50068,7 @@ design: (work@sky130_fd_sc_hd__ha) |vpiPort: \_port: (COUT), line:34:5, endln:34:9 |vpiParent: - \_module: work@sky130_fd_sc_hd__ha (work@sky130_fd_sc_hd__ha), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__ha.functional.v, line:33:1, endln:56:10 + \_module_inst: work@sky130_fd_sc_hd__ha (work@sky130_fd_sc_hd__ha), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__ha.functional.v, line:33:1, endln:56:10 |vpiName:COUT |vpiDirection:2 |vpiLowConn: @@ -50082,7 +50082,7 @@ design: (work@sky130_fd_sc_hd__ha) |vpiPort: \_port: (SUM), line:35:5, endln:35:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__ha (work@sky130_fd_sc_hd__ha), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__ha.functional.v, line:33:1, endln:56:10 + \_module_inst: work@sky130_fd_sc_hd__ha (work@sky130_fd_sc_hd__ha), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__ha.functional.v, line:33:1, endln:56:10 |vpiName:SUM |vpiDirection:2 |vpiLowConn: @@ -50096,7 +50096,7 @@ design: (work@sky130_fd_sc_hd__ha) |vpiPort: \_port: (A), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__ha (work@sky130_fd_sc_hd__ha), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__ha.functional.v, line:33:1, endln:56:10 + \_module_inst: work@sky130_fd_sc_hd__ha (work@sky130_fd_sc_hd__ha), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__ha.functional.v, line:33:1, endln:56:10 |vpiName:A |vpiDirection:1 |vpiLowConn: @@ -50110,7 +50110,7 @@ design: (work@sky130_fd_sc_hd__ha) |vpiPort: \_port: (B), line:37:5, endln:37:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__ha (work@sky130_fd_sc_hd__ha), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__ha.functional.v, line:33:1, endln:56:10 + \_module_inst: work@sky130_fd_sc_hd__ha (work@sky130_fd_sc_hd__ha), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__ha.functional.v, line:33:1, endln:56:10 |vpiName:B |vpiDirection:1 |vpiLowConn: @@ -50124,7 +50124,7 @@ design: (work@sky130_fd_sc_hd__ha) |vpiPrimitive: \_gate: work@and (work@sky130_fd_sc_hd__ha.and0), line:51:9, endln:51:46 |vpiParent: - \_module: work@sky130_fd_sc_hd__ha (work@sky130_fd_sc_hd__ha), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__ha.functional.v, line:33:1, endln:56:10 + \_module_inst: work@sky130_fd_sc_hd__ha (work@sky130_fd_sc_hd__ha), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__ha.functional.v, line:33:1, endln:56:10 |vpiDefName:work@and |vpiName:and0 |vpiFullName:work@sky130_fd_sc_hd__ha.and0 @@ -50173,7 +50173,7 @@ design: (work@sky130_fd_sc_hd__ha) |vpiPrimitive: \_gate: work@buf (work@sky130_fd_sc_hd__ha.buf0), line:52:9, endln:52:46 |vpiParent: - \_module: work@sky130_fd_sc_hd__ha (work@sky130_fd_sc_hd__ha), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__ha.functional.v, line:33:1, endln:56:10 + \_module_inst: work@sky130_fd_sc_hd__ha (work@sky130_fd_sc_hd__ha), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__ha.functional.v, line:33:1, endln:56:10 |vpiDefName:work@buf |vpiName:buf0 |vpiFullName:work@sky130_fd_sc_hd__ha.buf0 @@ -50208,7 +50208,7 @@ design: (work@sky130_fd_sc_hd__ha) |vpiPrimitive: \_gate: work@xor (work@sky130_fd_sc_hd__ha.xor0), line:53:9, endln:53:46 |vpiParent: - \_module: work@sky130_fd_sc_hd__ha (work@sky130_fd_sc_hd__ha), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__ha.functional.v, line:33:1, endln:56:10 + \_module_inst: work@sky130_fd_sc_hd__ha (work@sky130_fd_sc_hd__ha), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__ha.functional.v, line:33:1, endln:56:10 |vpiDefName:work@xor |vpiName:xor0 |vpiFullName:work@sky130_fd_sc_hd__ha.xor0 @@ -50257,7 +50257,7 @@ design: (work@sky130_fd_sc_hd__ha) |vpiPrimitive: \_gate: work@buf (work@sky130_fd_sc_hd__ha.buf1), line:54:9, endln:54:46 |vpiParent: - \_module: work@sky130_fd_sc_hd__ha (work@sky130_fd_sc_hd__ha), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__ha.functional.v, line:33:1, endln:56:10 + \_module_inst: work@sky130_fd_sc_hd__ha (work@sky130_fd_sc_hd__ha), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__ha.functional.v, line:33:1, endln:56:10 |vpiDefName:work@buf |vpiName:buf1 |vpiFullName:work@sky130_fd_sc_hd__ha.buf1 @@ -50428,7 +50428,7 @@ design: (work@sky130_fd_sc_hd__dfbbp) |vpiSize:4 |STRING:0 0 ? * : ? : - |uhdmallModules: -\_module: work@sky130_fd_sc_hd__dfbbp (work@sky130_fd_sc_hd__dfbbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfbbp.functional.v, line:37:1, endln:66:10 +\_module_inst: work@sky130_fd_sc_hd__dfbbp (work@sky130_fd_sc_hd__dfbbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfbbp.functional.v, line:37:1, endln:66:10 |vpiParent: \_design: (work@sky130_fd_sc_hd__dfbbp) |vpiFullName:work@sky130_fd_sc_hd__dfbbp @@ -50436,64 +50436,64 @@ design: (work@sky130_fd_sc_hd__dfbbp) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__dfbbp.RESET), line:55:10, endln:55:15 |vpiParent: - \_module: work@sky130_fd_sc_hd__dfbbp (work@sky130_fd_sc_hd__dfbbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfbbp.functional.v, line:37:1, endln:66:10 + \_module_inst: work@sky130_fd_sc_hd__dfbbp (work@sky130_fd_sc_hd__dfbbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfbbp.functional.v, line:37:1, endln:66:10 |vpiName:RESET |vpiFullName:work@sky130_fd_sc_hd__dfbbp.RESET |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__dfbbp.SET), line:56:10, endln:56:13 |vpiParent: - \_module: work@sky130_fd_sc_hd__dfbbp (work@sky130_fd_sc_hd__dfbbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfbbp.functional.v, line:37:1, endln:66:10 + \_module_inst: work@sky130_fd_sc_hd__dfbbp (work@sky130_fd_sc_hd__dfbbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfbbp.functional.v, line:37:1, endln:66:10 |vpiName:SET |vpiFullName:work@sky130_fd_sc_hd__dfbbp.SET |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__dfbbp.buf_Q), line:57:10, endln:57:15 |vpiParent: - \_module: work@sky130_fd_sc_hd__dfbbp (work@sky130_fd_sc_hd__dfbbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfbbp.functional.v, line:37:1, endln:66:10 + \_module_inst: work@sky130_fd_sc_hd__dfbbp (work@sky130_fd_sc_hd__dfbbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfbbp.functional.v, line:37:1, endln:66:10 |vpiName:buf_Q |vpiFullName:work@sky130_fd_sc_hd__dfbbp.buf_Q |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__dfbbp.Q), line:38:5, endln:38:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__dfbbp (work@sky130_fd_sc_hd__dfbbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfbbp.functional.v, line:37:1, endln:66:10 + \_module_inst: work@sky130_fd_sc_hd__dfbbp (work@sky130_fd_sc_hd__dfbbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfbbp.functional.v, line:37:1, endln:66:10 |vpiName:Q |vpiFullName:work@sky130_fd_sc_hd__dfbbp.Q |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__dfbbp.Q_N), line:39:5, endln:39:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__dfbbp (work@sky130_fd_sc_hd__dfbbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfbbp.functional.v, line:37:1, endln:66:10 + \_module_inst: work@sky130_fd_sc_hd__dfbbp (work@sky130_fd_sc_hd__dfbbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfbbp.functional.v, line:37:1, endln:66:10 |vpiName:Q_N |vpiFullName:work@sky130_fd_sc_hd__dfbbp.Q_N |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__dfbbp.D), line:40:5, endln:40:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__dfbbp (work@sky130_fd_sc_hd__dfbbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfbbp.functional.v, line:37:1, endln:66:10 + \_module_inst: work@sky130_fd_sc_hd__dfbbp (work@sky130_fd_sc_hd__dfbbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfbbp.functional.v, line:37:1, endln:66:10 |vpiName:D |vpiFullName:work@sky130_fd_sc_hd__dfbbp.D |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__dfbbp.CLK), line:41:5, endln:41:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__dfbbp (work@sky130_fd_sc_hd__dfbbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfbbp.functional.v, line:37:1, endln:66:10 + \_module_inst: work@sky130_fd_sc_hd__dfbbp (work@sky130_fd_sc_hd__dfbbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfbbp.functional.v, line:37:1, endln:66:10 |vpiName:CLK |vpiFullName:work@sky130_fd_sc_hd__dfbbp.CLK |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__dfbbp.SET_B), line:42:5, endln:42:10 |vpiParent: - \_module: work@sky130_fd_sc_hd__dfbbp (work@sky130_fd_sc_hd__dfbbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfbbp.functional.v, line:37:1, endln:66:10 + \_module_inst: work@sky130_fd_sc_hd__dfbbp (work@sky130_fd_sc_hd__dfbbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfbbp.functional.v, line:37:1, endln:66:10 |vpiName:SET_B |vpiFullName:work@sky130_fd_sc_hd__dfbbp.SET_B |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__dfbbp.RESET_B), line:43:5, endln:43:12 |vpiParent: - \_module: work@sky130_fd_sc_hd__dfbbp (work@sky130_fd_sc_hd__dfbbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfbbp.functional.v, line:37:1, endln:66:10 + \_module_inst: work@sky130_fd_sc_hd__dfbbp (work@sky130_fd_sc_hd__dfbbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfbbp.functional.v, line:37:1, endln:66:10 |vpiName:RESET_B |vpiFullName:work@sky130_fd_sc_hd__dfbbp.RESET_B |vpiPort: \_port: (Q), line:38:5, endln:38:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__dfbbp (work@sky130_fd_sc_hd__dfbbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfbbp.functional.v, line:37:1, endln:66:10 + \_module_inst: work@sky130_fd_sc_hd__dfbbp (work@sky130_fd_sc_hd__dfbbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfbbp.functional.v, line:37:1, endln:66:10 |vpiName:Q |vpiDirection:2 |vpiLowConn: @@ -50505,7 +50505,7 @@ design: (work@sky130_fd_sc_hd__dfbbp) |vpiPort: \_port: (Q_N), line:39:5, endln:39:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__dfbbp (work@sky130_fd_sc_hd__dfbbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfbbp.functional.v, line:37:1, endln:66:10 + \_module_inst: work@sky130_fd_sc_hd__dfbbp (work@sky130_fd_sc_hd__dfbbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfbbp.functional.v, line:37:1, endln:66:10 |vpiName:Q_N |vpiDirection:2 |vpiLowConn: @@ -50517,7 +50517,7 @@ design: (work@sky130_fd_sc_hd__dfbbp) |vpiPort: \_port: (D), line:40:5, endln:40:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__dfbbp (work@sky130_fd_sc_hd__dfbbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfbbp.functional.v, line:37:1, endln:66:10 + \_module_inst: work@sky130_fd_sc_hd__dfbbp (work@sky130_fd_sc_hd__dfbbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfbbp.functional.v, line:37:1, endln:66:10 |vpiName:D |vpiDirection:1 |vpiLowConn: @@ -50529,7 +50529,7 @@ design: (work@sky130_fd_sc_hd__dfbbp) |vpiPort: \_port: (CLK), line:41:5, endln:41:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__dfbbp (work@sky130_fd_sc_hd__dfbbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfbbp.functional.v, line:37:1, endln:66:10 + \_module_inst: work@sky130_fd_sc_hd__dfbbp (work@sky130_fd_sc_hd__dfbbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfbbp.functional.v, line:37:1, endln:66:10 |vpiName:CLK |vpiDirection:1 |vpiLowConn: @@ -50541,7 +50541,7 @@ design: (work@sky130_fd_sc_hd__dfbbp) |vpiPort: \_port: (SET_B), line:42:5, endln:42:10 |vpiParent: - \_module: work@sky130_fd_sc_hd__dfbbp (work@sky130_fd_sc_hd__dfbbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfbbp.functional.v, line:37:1, endln:66:10 + \_module_inst: work@sky130_fd_sc_hd__dfbbp (work@sky130_fd_sc_hd__dfbbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfbbp.functional.v, line:37:1, endln:66:10 |vpiName:SET_B |vpiDirection:1 |vpiLowConn: @@ -50553,7 +50553,7 @@ design: (work@sky130_fd_sc_hd__dfbbp) |vpiPort: \_port: (RESET_B), line:43:5, endln:43:12 |vpiParent: - \_module: work@sky130_fd_sc_hd__dfbbp (work@sky130_fd_sc_hd__dfbbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfbbp.functional.v, line:37:1, endln:66:10 + \_module_inst: work@sky130_fd_sc_hd__dfbbp (work@sky130_fd_sc_hd__dfbbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfbbp.functional.v, line:37:1, endln:66:10 |vpiName:RESET_B |vpiDirection:1 |vpiLowConn: @@ -50563,14 +50563,14 @@ design: (work@sky130_fd_sc_hd__dfbbp) |vpiTypedef: \_logic_typespec: , line:52:12, endln:52:12 |uhdmtopModules: -\_module: work@sky130_fd_sc_hd__dfbbp (work@sky130_fd_sc_hd__dfbbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfbbp.functional.v, line:37:1, endln:66:10 +\_module_inst: work@sky130_fd_sc_hd__dfbbp (work@sky130_fd_sc_hd__dfbbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfbbp.functional.v, line:37:1, endln:66:10 |vpiName:work@sky130_fd_sc_hd__dfbbp |vpiDefName:work@sky130_fd_sc_hd__dfbbp |vpiTop:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__dfbbp.RESET), line:55:10, endln:55:15 |vpiParent: - \_module: work@sky130_fd_sc_hd__dfbbp (work@sky130_fd_sc_hd__dfbbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfbbp.functional.v, line:37:1, endln:66:10 + \_module_inst: work@sky130_fd_sc_hd__dfbbp (work@sky130_fd_sc_hd__dfbbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfbbp.functional.v, line:37:1, endln:66:10 |vpiTypespec: \_logic_typespec: , line:55:5, endln:55:9 |vpiName:RESET @@ -50579,7 +50579,7 @@ design: (work@sky130_fd_sc_hd__dfbbp) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__dfbbp.SET), line:56:10, endln:56:13 |vpiParent: - \_module: work@sky130_fd_sc_hd__dfbbp (work@sky130_fd_sc_hd__dfbbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfbbp.functional.v, line:37:1, endln:66:10 + \_module_inst: work@sky130_fd_sc_hd__dfbbp (work@sky130_fd_sc_hd__dfbbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfbbp.functional.v, line:37:1, endln:66:10 |vpiTypespec: \_logic_typespec: , line:56:5, endln:56:9 |vpiName:SET @@ -50588,7 +50588,7 @@ design: (work@sky130_fd_sc_hd__dfbbp) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__dfbbp.buf_Q), line:57:10, endln:57:15 |vpiParent: - \_module: work@sky130_fd_sc_hd__dfbbp (work@sky130_fd_sc_hd__dfbbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfbbp.functional.v, line:37:1, endln:66:10 + \_module_inst: work@sky130_fd_sc_hd__dfbbp (work@sky130_fd_sc_hd__dfbbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfbbp.functional.v, line:37:1, endln:66:10 |vpiTypespec: \_logic_typespec: , line:57:5, endln:57:9 |vpiName:buf_Q @@ -50597,7 +50597,7 @@ design: (work@sky130_fd_sc_hd__dfbbp) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__dfbbp.Q), line:38:5, endln:38:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__dfbbp (work@sky130_fd_sc_hd__dfbbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfbbp.functional.v, line:37:1, endln:66:10 + \_module_inst: work@sky130_fd_sc_hd__dfbbp (work@sky130_fd_sc_hd__dfbbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfbbp.functional.v, line:37:1, endln:66:10 |vpiTypespec: \_logic_typespec: , line:47:12, endln:47:12 |vpiName:Q @@ -50605,7 +50605,7 @@ design: (work@sky130_fd_sc_hd__dfbbp) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__dfbbp.Q_N), line:39:5, endln:39:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__dfbbp (work@sky130_fd_sc_hd__dfbbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfbbp.functional.v, line:37:1, endln:66:10 + \_module_inst: work@sky130_fd_sc_hd__dfbbp (work@sky130_fd_sc_hd__dfbbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfbbp.functional.v, line:37:1, endln:66:10 |vpiTypespec: \_logic_typespec: , line:48:12, endln:48:12 |vpiName:Q_N @@ -50613,7 +50613,7 @@ design: (work@sky130_fd_sc_hd__dfbbp) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__dfbbp.D), line:40:5, endln:40:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__dfbbp (work@sky130_fd_sc_hd__dfbbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfbbp.functional.v, line:37:1, endln:66:10 + \_module_inst: work@sky130_fd_sc_hd__dfbbp (work@sky130_fd_sc_hd__dfbbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfbbp.functional.v, line:37:1, endln:66:10 |vpiTypespec: \_logic_typespec: , line:49:12, endln:49:12 |vpiName:D @@ -50621,7 +50621,7 @@ design: (work@sky130_fd_sc_hd__dfbbp) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__dfbbp.CLK), line:41:5, endln:41:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__dfbbp (work@sky130_fd_sc_hd__dfbbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfbbp.functional.v, line:37:1, endln:66:10 + \_module_inst: work@sky130_fd_sc_hd__dfbbp (work@sky130_fd_sc_hd__dfbbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfbbp.functional.v, line:37:1, endln:66:10 |vpiTypespec: \_logic_typespec: , line:50:12, endln:50:12 |vpiName:CLK @@ -50629,7 +50629,7 @@ design: (work@sky130_fd_sc_hd__dfbbp) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__dfbbp.SET_B), line:42:5, endln:42:10 |vpiParent: - \_module: work@sky130_fd_sc_hd__dfbbp (work@sky130_fd_sc_hd__dfbbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfbbp.functional.v, line:37:1, endln:66:10 + \_module_inst: work@sky130_fd_sc_hd__dfbbp (work@sky130_fd_sc_hd__dfbbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfbbp.functional.v, line:37:1, endln:66:10 |vpiTypespec: \_logic_typespec: , line:51:12, endln:51:12 |vpiName:SET_B @@ -50637,7 +50637,7 @@ design: (work@sky130_fd_sc_hd__dfbbp) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__dfbbp.RESET_B), line:43:5, endln:43:12 |vpiParent: - \_module: work@sky130_fd_sc_hd__dfbbp (work@sky130_fd_sc_hd__dfbbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfbbp.functional.v, line:37:1, endln:66:10 + \_module_inst: work@sky130_fd_sc_hd__dfbbp (work@sky130_fd_sc_hd__dfbbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfbbp.functional.v, line:37:1, endln:66:10 |vpiTypespec: \_logic_typespec: , line:52:12, endln:52:12 |vpiName:RESET_B @@ -50646,7 +50646,7 @@ design: (work@sky130_fd_sc_hd__dfbbp) |vpiPort: \_port: (Q), line:38:5, endln:38:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__dfbbp (work@sky130_fd_sc_hd__dfbbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfbbp.functional.v, line:37:1, endln:66:10 + \_module_inst: work@sky130_fd_sc_hd__dfbbp (work@sky130_fd_sc_hd__dfbbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfbbp.functional.v, line:37:1, endln:66:10 |vpiName:Q |vpiDirection:2 |vpiLowConn: @@ -50660,7 +50660,7 @@ design: (work@sky130_fd_sc_hd__dfbbp) |vpiPort: \_port: (Q_N), line:39:5, endln:39:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__dfbbp (work@sky130_fd_sc_hd__dfbbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfbbp.functional.v, line:37:1, endln:66:10 + \_module_inst: work@sky130_fd_sc_hd__dfbbp (work@sky130_fd_sc_hd__dfbbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfbbp.functional.v, line:37:1, endln:66:10 |vpiName:Q_N |vpiDirection:2 |vpiLowConn: @@ -50674,7 +50674,7 @@ design: (work@sky130_fd_sc_hd__dfbbp) |vpiPort: \_port: (D), line:40:5, endln:40:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__dfbbp (work@sky130_fd_sc_hd__dfbbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfbbp.functional.v, line:37:1, endln:66:10 + \_module_inst: work@sky130_fd_sc_hd__dfbbp (work@sky130_fd_sc_hd__dfbbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfbbp.functional.v, line:37:1, endln:66:10 |vpiName:D |vpiDirection:1 |vpiLowConn: @@ -50688,7 +50688,7 @@ design: (work@sky130_fd_sc_hd__dfbbp) |vpiPort: \_port: (CLK), line:41:5, endln:41:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__dfbbp (work@sky130_fd_sc_hd__dfbbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfbbp.functional.v, line:37:1, endln:66:10 + \_module_inst: work@sky130_fd_sc_hd__dfbbp (work@sky130_fd_sc_hd__dfbbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfbbp.functional.v, line:37:1, endln:66:10 |vpiName:CLK |vpiDirection:1 |vpiLowConn: @@ -50702,7 +50702,7 @@ design: (work@sky130_fd_sc_hd__dfbbp) |vpiPort: \_port: (SET_B), line:42:5, endln:42:10 |vpiParent: - \_module: work@sky130_fd_sc_hd__dfbbp (work@sky130_fd_sc_hd__dfbbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfbbp.functional.v, line:37:1, endln:66:10 + \_module_inst: work@sky130_fd_sc_hd__dfbbp (work@sky130_fd_sc_hd__dfbbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfbbp.functional.v, line:37:1, endln:66:10 |vpiName:SET_B |vpiDirection:1 |vpiLowConn: @@ -50716,7 +50716,7 @@ design: (work@sky130_fd_sc_hd__dfbbp) |vpiPort: \_port: (RESET_B), line:43:5, endln:43:12 |vpiParent: - \_module: work@sky130_fd_sc_hd__dfbbp (work@sky130_fd_sc_hd__dfbbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfbbp.functional.v, line:37:1, endln:66:10 + \_module_inst: work@sky130_fd_sc_hd__dfbbp (work@sky130_fd_sc_hd__dfbbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfbbp.functional.v, line:37:1, endln:66:10 |vpiName:RESET_B |vpiDirection:1 |vpiLowConn: @@ -50730,7 +50730,7 @@ design: (work@sky130_fd_sc_hd__dfbbp) |vpiPrimitive: \_gate: work@not (work@sky130_fd_sc_hd__dfbbp.not0), line:60:46, endln:60:79 |vpiParent: - \_module: work@sky130_fd_sc_hd__dfbbp (work@sky130_fd_sc_hd__dfbbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfbbp.functional.v, line:37:1, endln:66:10 + \_module_inst: work@sky130_fd_sc_hd__dfbbp (work@sky130_fd_sc_hd__dfbbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfbbp.functional.v, line:37:1, endln:66:10 |vpiDefName:work@not |vpiName:not0 |vpiFullName:work@sky130_fd_sc_hd__dfbbp.not0 @@ -50765,7 +50765,7 @@ design: (work@sky130_fd_sc_hd__dfbbp) |vpiPrimitive: \_gate: work@not (work@sky130_fd_sc_hd__dfbbp.not1), line:61:46, endln:61:79 |vpiParent: - \_module: work@sky130_fd_sc_hd__dfbbp (work@sky130_fd_sc_hd__dfbbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfbbp.functional.v, line:37:1, endln:66:10 + \_module_inst: work@sky130_fd_sc_hd__dfbbp (work@sky130_fd_sc_hd__dfbbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfbbp.functional.v, line:37:1, endln:66:10 |vpiDefName:work@not |vpiName:not1 |vpiFullName:work@sky130_fd_sc_hd__dfbbp.not1 @@ -50800,7 +50800,7 @@ design: (work@sky130_fd_sc_hd__dfbbp) |vpiPrimitive: \_udp: work@sky130_fd_sc_hd__udp_dff$NSR (work@sky130_fd_sc_hd__dfbbp.dff0), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfbbp.functional.v, line:62:5, endln:62:69 |vpiParent: - \_module: work@sky130_fd_sc_hd__dfbbp (work@sky130_fd_sc_hd__dfbbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfbbp.functional.v, line:37:1, endln:66:10 + \_module_inst: work@sky130_fd_sc_hd__dfbbp (work@sky130_fd_sc_hd__dfbbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfbbp.functional.v, line:37:1, endln:66:10 |vpiDefName:work@sky130_fd_sc_hd__udp_dff$NSR |vpiName:dff0 |vpiFullName:work@sky130_fd_sc_hd__dfbbp.dff0 @@ -50809,7 +50809,7 @@ design: (work@sky130_fd_sc_hd__dfbbp) |vpiPrimitive: \_gate: work@buf (work@sky130_fd_sc_hd__dfbbp.buf0), line:63:46, endln:63:79 |vpiParent: - \_module: work@sky130_fd_sc_hd__dfbbp (work@sky130_fd_sc_hd__dfbbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfbbp.functional.v, line:37:1, endln:66:10 + \_module_inst: work@sky130_fd_sc_hd__dfbbp (work@sky130_fd_sc_hd__dfbbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfbbp.functional.v, line:37:1, endln:66:10 |vpiDefName:work@buf |vpiName:buf0 |vpiFullName:work@sky130_fd_sc_hd__dfbbp.buf0 @@ -50844,7 +50844,7 @@ design: (work@sky130_fd_sc_hd__dfbbp) |vpiPrimitive: \_gate: work@not (work@sky130_fd_sc_hd__dfbbp.not2), line:64:46, endln:64:79 |vpiParent: - \_module: work@sky130_fd_sc_hd__dfbbp (work@sky130_fd_sc_hd__dfbbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfbbp.functional.v, line:37:1, endln:66:10 + \_module_inst: work@sky130_fd_sc_hd__dfbbp (work@sky130_fd_sc_hd__dfbbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfbbp.functional.v, line:37:1, endln:66:10 |vpiDefName:work@not |vpiName:not2 |vpiFullName:work@sky130_fd_sc_hd__dfbbp.not2 @@ -50887,7 +50887,7 @@ Processing: -cd cells/cells -DUNIT_DELAY -writepp -parse -nocache -nobuiltin -no design: (work@sky130_fd_sc_hd__lpflow_inputiso1p) |vpiName:work@sky130_fd_sc_hd__lpflow_inputiso1p |uhdmallModules: -\_module: work@sky130_fd_sc_hd__lpflow_inputiso1p (work@sky130_fd_sc_hd__lpflow_inputiso1p), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_inputiso1p.functional.v, line:35:1, endln:49:10 +\_module_inst: work@sky130_fd_sc_hd__lpflow_inputiso1p (work@sky130_fd_sc_hd__lpflow_inputiso1p), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_inputiso1p.functional.v, line:35:1, endln:49:10 |vpiParent: \_design: (work@sky130_fd_sc_hd__lpflow_inputiso1p) |vpiFullName:work@sky130_fd_sc_hd__lpflow_inputiso1p @@ -50895,25 +50895,25 @@ design: (work@sky130_fd_sc_hd__lpflow_inputiso1p) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__lpflow_inputiso1p.X), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__lpflow_inputiso1p (work@sky130_fd_sc_hd__lpflow_inputiso1p), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_inputiso1p.functional.v, line:35:1, endln:49:10 + \_module_inst: work@sky130_fd_sc_hd__lpflow_inputiso1p (work@sky130_fd_sc_hd__lpflow_inputiso1p), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_inputiso1p.functional.v, line:35:1, endln:49:10 |vpiName:X |vpiFullName:work@sky130_fd_sc_hd__lpflow_inputiso1p.X |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__lpflow_inputiso1p.A), line:37:5, endln:37:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__lpflow_inputiso1p (work@sky130_fd_sc_hd__lpflow_inputiso1p), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_inputiso1p.functional.v, line:35:1, endln:49:10 + \_module_inst: work@sky130_fd_sc_hd__lpflow_inputiso1p (work@sky130_fd_sc_hd__lpflow_inputiso1p), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_inputiso1p.functional.v, line:35:1, endln:49:10 |vpiName:A |vpiFullName:work@sky130_fd_sc_hd__lpflow_inputiso1p.A |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__lpflow_inputiso1p.SLEEP), line:38:5, endln:38:10 |vpiParent: - \_module: work@sky130_fd_sc_hd__lpflow_inputiso1p (work@sky130_fd_sc_hd__lpflow_inputiso1p), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_inputiso1p.functional.v, line:35:1, endln:49:10 + \_module_inst: work@sky130_fd_sc_hd__lpflow_inputiso1p (work@sky130_fd_sc_hd__lpflow_inputiso1p), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_inputiso1p.functional.v, line:35:1, endln:49:10 |vpiName:SLEEP |vpiFullName:work@sky130_fd_sc_hd__lpflow_inputiso1p.SLEEP |vpiPort: \_port: (X), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__lpflow_inputiso1p (work@sky130_fd_sc_hd__lpflow_inputiso1p), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_inputiso1p.functional.v, line:35:1, endln:49:10 + \_module_inst: work@sky130_fd_sc_hd__lpflow_inputiso1p (work@sky130_fd_sc_hd__lpflow_inputiso1p), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_inputiso1p.functional.v, line:35:1, endln:49:10 |vpiName:X |vpiDirection:2 |vpiLowConn: @@ -50925,7 +50925,7 @@ design: (work@sky130_fd_sc_hd__lpflow_inputiso1p) |vpiPort: \_port: (A), line:37:5, endln:37:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__lpflow_inputiso1p (work@sky130_fd_sc_hd__lpflow_inputiso1p), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_inputiso1p.functional.v, line:35:1, endln:49:10 + \_module_inst: work@sky130_fd_sc_hd__lpflow_inputiso1p (work@sky130_fd_sc_hd__lpflow_inputiso1p), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_inputiso1p.functional.v, line:35:1, endln:49:10 |vpiName:A |vpiDirection:1 |vpiLowConn: @@ -50937,7 +50937,7 @@ design: (work@sky130_fd_sc_hd__lpflow_inputiso1p) |vpiPort: \_port: (SLEEP), line:38:5, endln:38:10 |vpiParent: - \_module: work@sky130_fd_sc_hd__lpflow_inputiso1p (work@sky130_fd_sc_hd__lpflow_inputiso1p), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_inputiso1p.functional.v, line:35:1, endln:49:10 + \_module_inst: work@sky130_fd_sc_hd__lpflow_inputiso1p (work@sky130_fd_sc_hd__lpflow_inputiso1p), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_inputiso1p.functional.v, line:35:1, endln:49:10 |vpiName:SLEEP |vpiDirection:1 |vpiLowConn: @@ -50947,14 +50947,14 @@ design: (work@sky130_fd_sc_hd__lpflow_inputiso1p) |vpiTypedef: \_logic_typespec: , line:44:12, endln:44:12 |uhdmtopModules: -\_module: work@sky130_fd_sc_hd__lpflow_inputiso1p (work@sky130_fd_sc_hd__lpflow_inputiso1p), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_inputiso1p.functional.v, line:35:1, endln:49:10 +\_module_inst: work@sky130_fd_sc_hd__lpflow_inputiso1p (work@sky130_fd_sc_hd__lpflow_inputiso1p), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_inputiso1p.functional.v, line:35:1, endln:49:10 |vpiName:work@sky130_fd_sc_hd__lpflow_inputiso1p |vpiDefName:work@sky130_fd_sc_hd__lpflow_inputiso1p |vpiTop:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__lpflow_inputiso1p.X), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__lpflow_inputiso1p (work@sky130_fd_sc_hd__lpflow_inputiso1p), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_inputiso1p.functional.v, line:35:1, endln:49:10 + \_module_inst: work@sky130_fd_sc_hd__lpflow_inputiso1p (work@sky130_fd_sc_hd__lpflow_inputiso1p), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_inputiso1p.functional.v, line:35:1, endln:49:10 |vpiTypespec: \_logic_typespec: , line:42:12, endln:42:12 |vpiName:X @@ -50962,7 +50962,7 @@ design: (work@sky130_fd_sc_hd__lpflow_inputiso1p) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__lpflow_inputiso1p.A), line:37:5, endln:37:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__lpflow_inputiso1p (work@sky130_fd_sc_hd__lpflow_inputiso1p), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_inputiso1p.functional.v, line:35:1, endln:49:10 + \_module_inst: work@sky130_fd_sc_hd__lpflow_inputiso1p (work@sky130_fd_sc_hd__lpflow_inputiso1p), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_inputiso1p.functional.v, line:35:1, endln:49:10 |vpiTypespec: \_logic_typespec: , line:43:12, endln:43:12 |vpiName:A @@ -50970,7 +50970,7 @@ design: (work@sky130_fd_sc_hd__lpflow_inputiso1p) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__lpflow_inputiso1p.SLEEP), line:38:5, endln:38:10 |vpiParent: - \_module: work@sky130_fd_sc_hd__lpflow_inputiso1p (work@sky130_fd_sc_hd__lpflow_inputiso1p), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_inputiso1p.functional.v, line:35:1, endln:49:10 + \_module_inst: work@sky130_fd_sc_hd__lpflow_inputiso1p (work@sky130_fd_sc_hd__lpflow_inputiso1p), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_inputiso1p.functional.v, line:35:1, endln:49:10 |vpiTypespec: \_logic_typespec: , line:44:12, endln:44:12 |vpiName:SLEEP @@ -50979,7 +50979,7 @@ design: (work@sky130_fd_sc_hd__lpflow_inputiso1p) |vpiPort: \_port: (X), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__lpflow_inputiso1p (work@sky130_fd_sc_hd__lpflow_inputiso1p), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_inputiso1p.functional.v, line:35:1, endln:49:10 + \_module_inst: work@sky130_fd_sc_hd__lpflow_inputiso1p (work@sky130_fd_sc_hd__lpflow_inputiso1p), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_inputiso1p.functional.v, line:35:1, endln:49:10 |vpiName:X |vpiDirection:2 |vpiLowConn: @@ -50993,7 +50993,7 @@ design: (work@sky130_fd_sc_hd__lpflow_inputiso1p) |vpiPort: \_port: (A), line:37:5, endln:37:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__lpflow_inputiso1p (work@sky130_fd_sc_hd__lpflow_inputiso1p), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_inputiso1p.functional.v, line:35:1, endln:49:10 + \_module_inst: work@sky130_fd_sc_hd__lpflow_inputiso1p (work@sky130_fd_sc_hd__lpflow_inputiso1p), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_inputiso1p.functional.v, line:35:1, endln:49:10 |vpiName:A |vpiDirection:1 |vpiLowConn: @@ -51007,7 +51007,7 @@ design: (work@sky130_fd_sc_hd__lpflow_inputiso1p) |vpiPort: \_port: (SLEEP), line:38:5, endln:38:10 |vpiParent: - \_module: work@sky130_fd_sc_hd__lpflow_inputiso1p (work@sky130_fd_sc_hd__lpflow_inputiso1p), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_inputiso1p.functional.v, line:35:1, endln:49:10 + \_module_inst: work@sky130_fd_sc_hd__lpflow_inputiso1p (work@sky130_fd_sc_hd__lpflow_inputiso1p), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_inputiso1p.functional.v, line:35:1, endln:49:10 |vpiName:SLEEP |vpiDirection:1 |vpiLowConn: @@ -51021,7 +51021,7 @@ design: (work@sky130_fd_sc_hd__lpflow_inputiso1p) |vpiPrimitive: \_gate: work@or (work@sky130_fd_sc_hd__lpflow_inputiso1p.or0), line:47:9, endln:47:39 |vpiParent: - \_module: work@sky130_fd_sc_hd__lpflow_inputiso1p (work@sky130_fd_sc_hd__lpflow_inputiso1p), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_inputiso1p.functional.v, line:35:1, endln:49:10 + \_module_inst: work@sky130_fd_sc_hd__lpflow_inputiso1p (work@sky130_fd_sc_hd__lpflow_inputiso1p), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_inputiso1p.functional.v, line:35:1, endln:49:10 |vpiDefName:work@or |vpiName:or0 |vpiFullName:work@sky130_fd_sc_hd__lpflow_inputiso1p.or0 @@ -51078,7 +51078,7 @@ Processing: -cd cells/cells -DUNIT_DELAY -writepp -parse -nocache -nobuiltin -no design: (work@sky130_fd_sc_hd__a311o) |vpiName:work@sky130_fd_sc_hd__a311o |uhdmallModules: -\_module: work@sky130_fd_sc_hd__a311o (work@sky130_fd_sc_hd__a311o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a311o.functional.v, line:35:1, endln:61:10 +\_module_inst: work@sky130_fd_sc_hd__a311o (work@sky130_fd_sc_hd__a311o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a311o.functional.v, line:35:1, endln:61:10 |vpiParent: \_design: (work@sky130_fd_sc_hd__a311o) |vpiFullName:work@sky130_fd_sc_hd__a311o @@ -51086,57 +51086,57 @@ design: (work@sky130_fd_sc_hd__a311o) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a311o.and0_out), line:53:10, endln:53:18 |vpiParent: - \_module: work@sky130_fd_sc_hd__a311o (work@sky130_fd_sc_hd__a311o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a311o.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__a311o (work@sky130_fd_sc_hd__a311o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a311o.functional.v, line:35:1, endln:61:10 |vpiName:and0_out |vpiFullName:work@sky130_fd_sc_hd__a311o.and0_out |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a311o.or0_out_X), line:54:10, endln:54:19 |vpiParent: - \_module: work@sky130_fd_sc_hd__a311o (work@sky130_fd_sc_hd__a311o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a311o.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__a311o (work@sky130_fd_sc_hd__a311o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a311o.functional.v, line:35:1, endln:61:10 |vpiName:or0_out_X |vpiFullName:work@sky130_fd_sc_hd__a311o.or0_out_X |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a311o.X), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__a311o (work@sky130_fd_sc_hd__a311o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a311o.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__a311o (work@sky130_fd_sc_hd__a311o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a311o.functional.v, line:35:1, endln:61:10 |vpiName:X |vpiFullName:work@sky130_fd_sc_hd__a311o.X |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a311o.A1), line:37:5, endln:37:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a311o (work@sky130_fd_sc_hd__a311o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a311o.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__a311o (work@sky130_fd_sc_hd__a311o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a311o.functional.v, line:35:1, endln:61:10 |vpiName:A1 |vpiFullName:work@sky130_fd_sc_hd__a311o.A1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a311o.A2), line:38:5, endln:38:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a311o (work@sky130_fd_sc_hd__a311o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a311o.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__a311o (work@sky130_fd_sc_hd__a311o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a311o.functional.v, line:35:1, endln:61:10 |vpiName:A2 |vpiFullName:work@sky130_fd_sc_hd__a311o.A2 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a311o.A3), line:39:5, endln:39:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a311o (work@sky130_fd_sc_hd__a311o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a311o.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__a311o (work@sky130_fd_sc_hd__a311o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a311o.functional.v, line:35:1, endln:61:10 |vpiName:A3 |vpiFullName:work@sky130_fd_sc_hd__a311o.A3 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a311o.B1), line:40:5, endln:40:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a311o (work@sky130_fd_sc_hd__a311o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a311o.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__a311o (work@sky130_fd_sc_hd__a311o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a311o.functional.v, line:35:1, endln:61:10 |vpiName:B1 |vpiFullName:work@sky130_fd_sc_hd__a311o.B1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a311o.C1), line:41:5, endln:41:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a311o (work@sky130_fd_sc_hd__a311o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a311o.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__a311o (work@sky130_fd_sc_hd__a311o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a311o.functional.v, line:35:1, endln:61:10 |vpiName:C1 |vpiFullName:work@sky130_fd_sc_hd__a311o.C1 |vpiPort: \_port: (X), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__a311o (work@sky130_fd_sc_hd__a311o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a311o.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__a311o (work@sky130_fd_sc_hd__a311o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a311o.functional.v, line:35:1, endln:61:10 |vpiName:X |vpiDirection:2 |vpiLowConn: @@ -51148,7 +51148,7 @@ design: (work@sky130_fd_sc_hd__a311o) |vpiPort: \_port: (A1), line:37:5, endln:37:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a311o (work@sky130_fd_sc_hd__a311o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a311o.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__a311o (work@sky130_fd_sc_hd__a311o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a311o.functional.v, line:35:1, endln:61:10 |vpiName:A1 |vpiDirection:1 |vpiLowConn: @@ -51160,7 +51160,7 @@ design: (work@sky130_fd_sc_hd__a311o) |vpiPort: \_port: (A2), line:38:5, endln:38:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a311o (work@sky130_fd_sc_hd__a311o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a311o.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__a311o (work@sky130_fd_sc_hd__a311o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a311o.functional.v, line:35:1, endln:61:10 |vpiName:A2 |vpiDirection:1 |vpiLowConn: @@ -51172,7 +51172,7 @@ design: (work@sky130_fd_sc_hd__a311o) |vpiPort: \_port: (A3), line:39:5, endln:39:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a311o (work@sky130_fd_sc_hd__a311o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a311o.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__a311o (work@sky130_fd_sc_hd__a311o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a311o.functional.v, line:35:1, endln:61:10 |vpiName:A3 |vpiDirection:1 |vpiLowConn: @@ -51184,7 +51184,7 @@ design: (work@sky130_fd_sc_hd__a311o) |vpiPort: \_port: (B1), line:40:5, endln:40:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a311o (work@sky130_fd_sc_hd__a311o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a311o.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__a311o (work@sky130_fd_sc_hd__a311o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a311o.functional.v, line:35:1, endln:61:10 |vpiName:B1 |vpiDirection:1 |vpiLowConn: @@ -51196,7 +51196,7 @@ design: (work@sky130_fd_sc_hd__a311o) |vpiPort: \_port: (C1), line:41:5, endln:41:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a311o (work@sky130_fd_sc_hd__a311o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a311o.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__a311o (work@sky130_fd_sc_hd__a311o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a311o.functional.v, line:35:1, endln:61:10 |vpiName:C1 |vpiDirection:1 |vpiLowConn: @@ -51206,14 +51206,14 @@ design: (work@sky130_fd_sc_hd__a311o) |vpiTypedef: \_logic_typespec: , line:50:12, endln:50:12 |uhdmtopModules: -\_module: work@sky130_fd_sc_hd__a311o (work@sky130_fd_sc_hd__a311o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a311o.functional.v, line:35:1, endln:61:10 +\_module_inst: work@sky130_fd_sc_hd__a311o (work@sky130_fd_sc_hd__a311o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a311o.functional.v, line:35:1, endln:61:10 |vpiName:work@sky130_fd_sc_hd__a311o |vpiDefName:work@sky130_fd_sc_hd__a311o |vpiTop:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a311o.and0_out), line:53:10, endln:53:18 |vpiParent: - \_module: work@sky130_fd_sc_hd__a311o (work@sky130_fd_sc_hd__a311o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a311o.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__a311o (work@sky130_fd_sc_hd__a311o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a311o.functional.v, line:35:1, endln:61:10 |vpiTypespec: \_logic_typespec: , line:53:5, endln:53:9 |vpiName:and0_out @@ -51222,7 +51222,7 @@ design: (work@sky130_fd_sc_hd__a311o) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a311o.or0_out_X), line:54:10, endln:54:19 |vpiParent: - \_module: work@sky130_fd_sc_hd__a311o (work@sky130_fd_sc_hd__a311o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a311o.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__a311o (work@sky130_fd_sc_hd__a311o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a311o.functional.v, line:35:1, endln:61:10 |vpiTypespec: \_logic_typespec: , line:54:5, endln:54:9 |vpiName:or0_out_X @@ -51231,7 +51231,7 @@ design: (work@sky130_fd_sc_hd__a311o) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a311o.X), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__a311o (work@sky130_fd_sc_hd__a311o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a311o.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__a311o (work@sky130_fd_sc_hd__a311o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a311o.functional.v, line:35:1, endln:61:10 |vpiTypespec: \_logic_typespec: , line:45:12, endln:45:12 |vpiName:X @@ -51239,7 +51239,7 @@ design: (work@sky130_fd_sc_hd__a311o) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a311o.A1), line:37:5, endln:37:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a311o (work@sky130_fd_sc_hd__a311o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a311o.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__a311o (work@sky130_fd_sc_hd__a311o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a311o.functional.v, line:35:1, endln:61:10 |vpiTypespec: \_logic_typespec: , line:46:12, endln:46:12 |vpiName:A1 @@ -51247,7 +51247,7 @@ design: (work@sky130_fd_sc_hd__a311o) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a311o.A2), line:38:5, endln:38:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a311o (work@sky130_fd_sc_hd__a311o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a311o.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__a311o (work@sky130_fd_sc_hd__a311o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a311o.functional.v, line:35:1, endln:61:10 |vpiTypespec: \_logic_typespec: , line:47:12, endln:47:12 |vpiName:A2 @@ -51255,7 +51255,7 @@ design: (work@sky130_fd_sc_hd__a311o) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a311o.A3), line:39:5, endln:39:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a311o (work@sky130_fd_sc_hd__a311o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a311o.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__a311o (work@sky130_fd_sc_hd__a311o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a311o.functional.v, line:35:1, endln:61:10 |vpiTypespec: \_logic_typespec: , line:48:12, endln:48:12 |vpiName:A3 @@ -51263,7 +51263,7 @@ design: (work@sky130_fd_sc_hd__a311o) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a311o.B1), line:40:5, endln:40:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a311o (work@sky130_fd_sc_hd__a311o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a311o.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__a311o (work@sky130_fd_sc_hd__a311o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a311o.functional.v, line:35:1, endln:61:10 |vpiTypespec: \_logic_typespec: , line:49:12, endln:49:12 |vpiName:B1 @@ -51271,7 +51271,7 @@ design: (work@sky130_fd_sc_hd__a311o) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a311o.C1), line:41:5, endln:41:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a311o (work@sky130_fd_sc_hd__a311o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a311o.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__a311o (work@sky130_fd_sc_hd__a311o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a311o.functional.v, line:35:1, endln:61:10 |vpiTypespec: \_logic_typespec: , line:50:12, endln:50:12 |vpiName:C1 @@ -51280,7 +51280,7 @@ design: (work@sky130_fd_sc_hd__a311o) |vpiPort: \_port: (X), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__a311o (work@sky130_fd_sc_hd__a311o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a311o.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__a311o (work@sky130_fd_sc_hd__a311o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a311o.functional.v, line:35:1, endln:61:10 |vpiName:X |vpiDirection:2 |vpiLowConn: @@ -51294,7 +51294,7 @@ design: (work@sky130_fd_sc_hd__a311o) |vpiPort: \_port: (A1), line:37:5, endln:37:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a311o (work@sky130_fd_sc_hd__a311o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a311o.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__a311o (work@sky130_fd_sc_hd__a311o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a311o.functional.v, line:35:1, endln:61:10 |vpiName:A1 |vpiDirection:1 |vpiLowConn: @@ -51308,7 +51308,7 @@ design: (work@sky130_fd_sc_hd__a311o) |vpiPort: \_port: (A2), line:38:5, endln:38:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a311o (work@sky130_fd_sc_hd__a311o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a311o.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__a311o (work@sky130_fd_sc_hd__a311o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a311o.functional.v, line:35:1, endln:61:10 |vpiName:A2 |vpiDirection:1 |vpiLowConn: @@ -51322,7 +51322,7 @@ design: (work@sky130_fd_sc_hd__a311o) |vpiPort: \_port: (A3), line:39:5, endln:39:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a311o (work@sky130_fd_sc_hd__a311o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a311o.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__a311o (work@sky130_fd_sc_hd__a311o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a311o.functional.v, line:35:1, endln:61:10 |vpiName:A3 |vpiDirection:1 |vpiLowConn: @@ -51336,7 +51336,7 @@ design: (work@sky130_fd_sc_hd__a311o) |vpiPort: \_port: (B1), line:40:5, endln:40:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a311o (work@sky130_fd_sc_hd__a311o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a311o.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__a311o (work@sky130_fd_sc_hd__a311o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a311o.functional.v, line:35:1, endln:61:10 |vpiName:B1 |vpiDirection:1 |vpiLowConn: @@ -51350,7 +51350,7 @@ design: (work@sky130_fd_sc_hd__a311o) |vpiPort: \_port: (C1), line:41:5, endln:41:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a311o (work@sky130_fd_sc_hd__a311o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a311o.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__a311o (work@sky130_fd_sc_hd__a311o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a311o.functional.v, line:35:1, endln:61:10 |vpiName:C1 |vpiDirection:1 |vpiLowConn: @@ -51364,7 +51364,7 @@ design: (work@sky130_fd_sc_hd__a311o) |vpiPrimitive: \_gate: work@and (work@sky130_fd_sc_hd__a311o.and0), line:57:9, endln:57:43 |vpiParent: - \_module: work@sky130_fd_sc_hd__a311o (work@sky130_fd_sc_hd__a311o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a311o.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__a311o (work@sky130_fd_sc_hd__a311o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a311o.functional.v, line:35:1, endln:61:10 |vpiDefName:work@and |vpiName:and0 |vpiFullName:work@sky130_fd_sc_hd__a311o.and0 @@ -51427,7 +51427,7 @@ design: (work@sky130_fd_sc_hd__a311o) |vpiPrimitive: \_gate: work@or (work@sky130_fd_sc_hd__a311o.or0), line:58:9, endln:58:43 |vpiParent: - \_module: work@sky130_fd_sc_hd__a311o (work@sky130_fd_sc_hd__a311o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a311o.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__a311o (work@sky130_fd_sc_hd__a311o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a311o.functional.v, line:35:1, endln:61:10 |vpiDefName:work@or |vpiName:or0 |vpiFullName:work@sky130_fd_sc_hd__a311o.or0 @@ -51490,7 +51490,7 @@ design: (work@sky130_fd_sc_hd__a311o) |vpiPrimitive: \_gate: work@buf (work@sky130_fd_sc_hd__a311o.buf0), line:59:9, endln:59:43 |vpiParent: - \_module: work@sky130_fd_sc_hd__a311o (work@sky130_fd_sc_hd__a311o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a311o.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__a311o (work@sky130_fd_sc_hd__a311o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a311o.functional.v, line:35:1, endln:61:10 |vpiDefName:work@buf |vpiName:buf0 |vpiFullName:work@sky130_fd_sc_hd__a311o.buf0 @@ -51607,7 +51607,7 @@ design: (work@sky130_fd_sc_hd__dlxtn) |vpiSize:2 |STRING:1 x : 1 : 1 |uhdmallModules: -\_module: work@sky130_fd_sc_hd__dlxtn (work@sky130_fd_sc_hd__dlxtn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlxtn.functional.v, line:36:1, endln:56:10 +\_module_inst: work@sky130_fd_sc_hd__dlxtn (work@sky130_fd_sc_hd__dlxtn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlxtn.functional.v, line:36:1, endln:56:10 |vpiParent: \_design: (work@sky130_fd_sc_hd__dlxtn) |vpiFullName:work@sky130_fd_sc_hd__dlxtn @@ -51615,39 +51615,39 @@ design: (work@sky130_fd_sc_hd__dlxtn) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__dlxtn.GATE), line:48:10, endln:48:14 |vpiParent: - \_module: work@sky130_fd_sc_hd__dlxtn (work@sky130_fd_sc_hd__dlxtn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlxtn.functional.v, line:36:1, endln:56:10 + \_module_inst: work@sky130_fd_sc_hd__dlxtn (work@sky130_fd_sc_hd__dlxtn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlxtn.functional.v, line:36:1, endln:56:10 |vpiName:GATE |vpiFullName:work@sky130_fd_sc_hd__dlxtn.GATE |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__dlxtn.buf_Q), line:49:10, endln:49:15 |vpiParent: - \_module: work@sky130_fd_sc_hd__dlxtn (work@sky130_fd_sc_hd__dlxtn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlxtn.functional.v, line:36:1, endln:56:10 + \_module_inst: work@sky130_fd_sc_hd__dlxtn (work@sky130_fd_sc_hd__dlxtn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlxtn.functional.v, line:36:1, endln:56:10 |vpiName:buf_Q |vpiFullName:work@sky130_fd_sc_hd__dlxtn.buf_Q |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__dlxtn.Q), line:37:5, endln:37:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__dlxtn (work@sky130_fd_sc_hd__dlxtn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlxtn.functional.v, line:36:1, endln:56:10 + \_module_inst: work@sky130_fd_sc_hd__dlxtn (work@sky130_fd_sc_hd__dlxtn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlxtn.functional.v, line:36:1, endln:56:10 |vpiName:Q |vpiFullName:work@sky130_fd_sc_hd__dlxtn.Q |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__dlxtn.D), line:38:5, endln:38:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__dlxtn (work@sky130_fd_sc_hd__dlxtn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlxtn.functional.v, line:36:1, endln:56:10 + \_module_inst: work@sky130_fd_sc_hd__dlxtn (work@sky130_fd_sc_hd__dlxtn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlxtn.functional.v, line:36:1, endln:56:10 |vpiName:D |vpiFullName:work@sky130_fd_sc_hd__dlxtn.D |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__dlxtn.GATE_N), line:39:5, endln:39:11 |vpiParent: - \_module: work@sky130_fd_sc_hd__dlxtn (work@sky130_fd_sc_hd__dlxtn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlxtn.functional.v, line:36:1, endln:56:10 + \_module_inst: work@sky130_fd_sc_hd__dlxtn (work@sky130_fd_sc_hd__dlxtn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlxtn.functional.v, line:36:1, endln:56:10 |vpiName:GATE_N |vpiFullName:work@sky130_fd_sc_hd__dlxtn.GATE_N |vpiPort: \_port: (Q), line:37:5, endln:37:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__dlxtn (work@sky130_fd_sc_hd__dlxtn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlxtn.functional.v, line:36:1, endln:56:10 + \_module_inst: work@sky130_fd_sc_hd__dlxtn (work@sky130_fd_sc_hd__dlxtn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlxtn.functional.v, line:36:1, endln:56:10 |vpiName:Q |vpiDirection:2 |vpiLowConn: @@ -51659,7 +51659,7 @@ design: (work@sky130_fd_sc_hd__dlxtn) |vpiPort: \_port: (D), line:38:5, endln:38:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__dlxtn (work@sky130_fd_sc_hd__dlxtn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlxtn.functional.v, line:36:1, endln:56:10 + \_module_inst: work@sky130_fd_sc_hd__dlxtn (work@sky130_fd_sc_hd__dlxtn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlxtn.functional.v, line:36:1, endln:56:10 |vpiName:D |vpiDirection:1 |vpiLowConn: @@ -51671,7 +51671,7 @@ design: (work@sky130_fd_sc_hd__dlxtn) |vpiPort: \_port: (GATE_N), line:39:5, endln:39:11 |vpiParent: - \_module: work@sky130_fd_sc_hd__dlxtn (work@sky130_fd_sc_hd__dlxtn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlxtn.functional.v, line:36:1, endln:56:10 + \_module_inst: work@sky130_fd_sc_hd__dlxtn (work@sky130_fd_sc_hd__dlxtn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlxtn.functional.v, line:36:1, endln:56:10 |vpiName:GATE_N |vpiDirection:1 |vpiLowConn: @@ -51681,14 +51681,14 @@ design: (work@sky130_fd_sc_hd__dlxtn) |vpiTypedef: \_logic_typespec: , line:45:12, endln:45:12 |uhdmtopModules: -\_module: work@sky130_fd_sc_hd__dlxtn (work@sky130_fd_sc_hd__dlxtn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlxtn.functional.v, line:36:1, endln:56:10 +\_module_inst: work@sky130_fd_sc_hd__dlxtn (work@sky130_fd_sc_hd__dlxtn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlxtn.functional.v, line:36:1, endln:56:10 |vpiName:work@sky130_fd_sc_hd__dlxtn |vpiDefName:work@sky130_fd_sc_hd__dlxtn |vpiTop:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__dlxtn.GATE), line:48:10, endln:48:14 |vpiParent: - \_module: work@sky130_fd_sc_hd__dlxtn (work@sky130_fd_sc_hd__dlxtn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlxtn.functional.v, line:36:1, endln:56:10 + \_module_inst: work@sky130_fd_sc_hd__dlxtn (work@sky130_fd_sc_hd__dlxtn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlxtn.functional.v, line:36:1, endln:56:10 |vpiTypespec: \_logic_typespec: , line:48:5, endln:48:9 |vpiName:GATE @@ -51697,7 +51697,7 @@ design: (work@sky130_fd_sc_hd__dlxtn) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__dlxtn.buf_Q), line:49:10, endln:49:15 |vpiParent: - \_module: work@sky130_fd_sc_hd__dlxtn (work@sky130_fd_sc_hd__dlxtn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlxtn.functional.v, line:36:1, endln:56:10 + \_module_inst: work@sky130_fd_sc_hd__dlxtn (work@sky130_fd_sc_hd__dlxtn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlxtn.functional.v, line:36:1, endln:56:10 |vpiTypespec: \_logic_typespec: , line:49:5, endln:49:9 |vpiName:buf_Q @@ -51706,7 +51706,7 @@ design: (work@sky130_fd_sc_hd__dlxtn) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__dlxtn.Q), line:37:5, endln:37:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__dlxtn (work@sky130_fd_sc_hd__dlxtn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlxtn.functional.v, line:36:1, endln:56:10 + \_module_inst: work@sky130_fd_sc_hd__dlxtn (work@sky130_fd_sc_hd__dlxtn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlxtn.functional.v, line:36:1, endln:56:10 |vpiTypespec: \_logic_typespec: , line:43:12, endln:43:12 |vpiName:Q @@ -51714,7 +51714,7 @@ design: (work@sky130_fd_sc_hd__dlxtn) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__dlxtn.D), line:38:5, endln:38:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__dlxtn (work@sky130_fd_sc_hd__dlxtn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlxtn.functional.v, line:36:1, endln:56:10 + \_module_inst: work@sky130_fd_sc_hd__dlxtn (work@sky130_fd_sc_hd__dlxtn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlxtn.functional.v, line:36:1, endln:56:10 |vpiTypespec: \_logic_typespec: , line:44:12, endln:44:12 |vpiName:D @@ -51722,7 +51722,7 @@ design: (work@sky130_fd_sc_hd__dlxtn) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__dlxtn.GATE_N), line:39:5, endln:39:11 |vpiParent: - \_module: work@sky130_fd_sc_hd__dlxtn (work@sky130_fd_sc_hd__dlxtn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlxtn.functional.v, line:36:1, endln:56:10 + \_module_inst: work@sky130_fd_sc_hd__dlxtn (work@sky130_fd_sc_hd__dlxtn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlxtn.functional.v, line:36:1, endln:56:10 |vpiTypespec: \_logic_typespec: , line:45:12, endln:45:12 |vpiName:GATE_N @@ -51731,7 +51731,7 @@ design: (work@sky130_fd_sc_hd__dlxtn) |vpiPort: \_port: (Q), line:37:5, endln:37:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__dlxtn (work@sky130_fd_sc_hd__dlxtn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlxtn.functional.v, line:36:1, endln:56:10 + \_module_inst: work@sky130_fd_sc_hd__dlxtn (work@sky130_fd_sc_hd__dlxtn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlxtn.functional.v, line:36:1, endln:56:10 |vpiName:Q |vpiDirection:2 |vpiLowConn: @@ -51745,7 +51745,7 @@ design: (work@sky130_fd_sc_hd__dlxtn) |vpiPort: \_port: (D), line:38:5, endln:38:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__dlxtn (work@sky130_fd_sc_hd__dlxtn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlxtn.functional.v, line:36:1, endln:56:10 + \_module_inst: work@sky130_fd_sc_hd__dlxtn (work@sky130_fd_sc_hd__dlxtn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlxtn.functional.v, line:36:1, endln:56:10 |vpiName:D |vpiDirection:1 |vpiLowConn: @@ -51759,7 +51759,7 @@ design: (work@sky130_fd_sc_hd__dlxtn) |vpiPort: \_port: (GATE_N), line:39:5, endln:39:11 |vpiParent: - \_module: work@sky130_fd_sc_hd__dlxtn (work@sky130_fd_sc_hd__dlxtn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlxtn.functional.v, line:36:1, endln:56:10 + \_module_inst: work@sky130_fd_sc_hd__dlxtn (work@sky130_fd_sc_hd__dlxtn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlxtn.functional.v, line:36:1, endln:56:10 |vpiName:GATE_N |vpiDirection:1 |vpiLowConn: @@ -51773,7 +51773,7 @@ design: (work@sky130_fd_sc_hd__dlxtn) |vpiPrimitive: \_gate: work@not (work@sky130_fd_sc_hd__dlxtn.not0), line:52:35, endln:52:68 |vpiParent: - \_module: work@sky130_fd_sc_hd__dlxtn (work@sky130_fd_sc_hd__dlxtn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlxtn.functional.v, line:36:1, endln:56:10 + \_module_inst: work@sky130_fd_sc_hd__dlxtn (work@sky130_fd_sc_hd__dlxtn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlxtn.functional.v, line:36:1, endln:56:10 |vpiDefName:work@not |vpiName:not0 |vpiFullName:work@sky130_fd_sc_hd__dlxtn.not0 @@ -51808,7 +51808,7 @@ design: (work@sky130_fd_sc_hd__dlxtn) |vpiPrimitive: \_udp: work@sky130_fd_sc_hd__udp_dlatch$P (work@sky130_fd_sc_hd__dlxtn.dlatch0), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlxtn.functional.v, line:53:5, endln:53:69 |vpiParent: - \_module: work@sky130_fd_sc_hd__dlxtn (work@sky130_fd_sc_hd__dlxtn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlxtn.functional.v, line:36:1, endln:56:10 + \_module_inst: work@sky130_fd_sc_hd__dlxtn (work@sky130_fd_sc_hd__dlxtn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlxtn.functional.v, line:36:1, endln:56:10 |vpiDefName:work@sky130_fd_sc_hd__udp_dlatch$P |vpiName:dlatch0 |vpiFullName:work@sky130_fd_sc_hd__dlxtn.dlatch0 @@ -51817,7 +51817,7 @@ design: (work@sky130_fd_sc_hd__dlxtn) |vpiPrimitive: \_gate: work@buf (work@sky130_fd_sc_hd__dlxtn.buf0), line:54:35, endln:54:68 |vpiParent: - \_module: work@sky130_fd_sc_hd__dlxtn (work@sky130_fd_sc_hd__dlxtn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlxtn.functional.v, line:36:1, endln:56:10 + \_module_inst: work@sky130_fd_sc_hd__dlxtn (work@sky130_fd_sc_hd__dlxtn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlxtn.functional.v, line:36:1, endln:56:10 |vpiDefName:work@buf |vpiName:buf0 |vpiFullName:work@sky130_fd_sc_hd__dlxtn.buf0 @@ -51860,7 +51860,7 @@ Processing: -cd cells/cells -DUNIT_DELAY -writepp -parse -nocache -nobuiltin -no design: (work@sky130_fd_sc_hd__a41oi) |vpiName:work@sky130_fd_sc_hd__a41oi |uhdmallModules: -\_module: work@sky130_fd_sc_hd__a41oi (work@sky130_fd_sc_hd__a41oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a41oi.functional.v, line:35:1, endln:61:10 +\_module_inst: work@sky130_fd_sc_hd__a41oi (work@sky130_fd_sc_hd__a41oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a41oi.functional.v, line:35:1, endln:61:10 |vpiParent: \_design: (work@sky130_fd_sc_hd__a41oi) |vpiFullName:work@sky130_fd_sc_hd__a41oi @@ -51868,57 +51868,57 @@ design: (work@sky130_fd_sc_hd__a41oi) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a41oi.and0_out), line:53:10, endln:53:18 |vpiParent: - \_module: work@sky130_fd_sc_hd__a41oi (work@sky130_fd_sc_hd__a41oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a41oi.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__a41oi (work@sky130_fd_sc_hd__a41oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a41oi.functional.v, line:35:1, endln:61:10 |vpiName:and0_out |vpiFullName:work@sky130_fd_sc_hd__a41oi.and0_out |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a41oi.nor0_out_Y), line:54:10, endln:54:20 |vpiParent: - \_module: work@sky130_fd_sc_hd__a41oi (work@sky130_fd_sc_hd__a41oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a41oi.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__a41oi (work@sky130_fd_sc_hd__a41oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a41oi.functional.v, line:35:1, endln:61:10 |vpiName:nor0_out_Y |vpiFullName:work@sky130_fd_sc_hd__a41oi.nor0_out_Y |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a41oi.Y), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__a41oi (work@sky130_fd_sc_hd__a41oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a41oi.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__a41oi (work@sky130_fd_sc_hd__a41oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a41oi.functional.v, line:35:1, endln:61:10 |vpiName:Y |vpiFullName:work@sky130_fd_sc_hd__a41oi.Y |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a41oi.A1), line:37:5, endln:37:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a41oi (work@sky130_fd_sc_hd__a41oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a41oi.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__a41oi (work@sky130_fd_sc_hd__a41oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a41oi.functional.v, line:35:1, endln:61:10 |vpiName:A1 |vpiFullName:work@sky130_fd_sc_hd__a41oi.A1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a41oi.A2), line:38:5, endln:38:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a41oi (work@sky130_fd_sc_hd__a41oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a41oi.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__a41oi (work@sky130_fd_sc_hd__a41oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a41oi.functional.v, line:35:1, endln:61:10 |vpiName:A2 |vpiFullName:work@sky130_fd_sc_hd__a41oi.A2 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a41oi.A3), line:39:5, endln:39:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a41oi (work@sky130_fd_sc_hd__a41oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a41oi.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__a41oi (work@sky130_fd_sc_hd__a41oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a41oi.functional.v, line:35:1, endln:61:10 |vpiName:A3 |vpiFullName:work@sky130_fd_sc_hd__a41oi.A3 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a41oi.A4), line:40:5, endln:40:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a41oi (work@sky130_fd_sc_hd__a41oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a41oi.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__a41oi (work@sky130_fd_sc_hd__a41oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a41oi.functional.v, line:35:1, endln:61:10 |vpiName:A4 |vpiFullName:work@sky130_fd_sc_hd__a41oi.A4 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a41oi.B1), line:41:5, endln:41:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a41oi (work@sky130_fd_sc_hd__a41oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a41oi.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__a41oi (work@sky130_fd_sc_hd__a41oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a41oi.functional.v, line:35:1, endln:61:10 |vpiName:B1 |vpiFullName:work@sky130_fd_sc_hd__a41oi.B1 |vpiPort: \_port: (Y), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__a41oi (work@sky130_fd_sc_hd__a41oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a41oi.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__a41oi (work@sky130_fd_sc_hd__a41oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a41oi.functional.v, line:35:1, endln:61:10 |vpiName:Y |vpiDirection:2 |vpiLowConn: @@ -51930,7 +51930,7 @@ design: (work@sky130_fd_sc_hd__a41oi) |vpiPort: \_port: (A1), line:37:5, endln:37:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a41oi (work@sky130_fd_sc_hd__a41oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a41oi.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__a41oi (work@sky130_fd_sc_hd__a41oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a41oi.functional.v, line:35:1, endln:61:10 |vpiName:A1 |vpiDirection:1 |vpiLowConn: @@ -51942,7 +51942,7 @@ design: (work@sky130_fd_sc_hd__a41oi) |vpiPort: \_port: (A2), line:38:5, endln:38:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a41oi (work@sky130_fd_sc_hd__a41oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a41oi.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__a41oi (work@sky130_fd_sc_hd__a41oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a41oi.functional.v, line:35:1, endln:61:10 |vpiName:A2 |vpiDirection:1 |vpiLowConn: @@ -51954,7 +51954,7 @@ design: (work@sky130_fd_sc_hd__a41oi) |vpiPort: \_port: (A3), line:39:5, endln:39:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a41oi (work@sky130_fd_sc_hd__a41oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a41oi.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__a41oi (work@sky130_fd_sc_hd__a41oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a41oi.functional.v, line:35:1, endln:61:10 |vpiName:A3 |vpiDirection:1 |vpiLowConn: @@ -51966,7 +51966,7 @@ design: (work@sky130_fd_sc_hd__a41oi) |vpiPort: \_port: (A4), line:40:5, endln:40:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a41oi (work@sky130_fd_sc_hd__a41oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a41oi.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__a41oi (work@sky130_fd_sc_hd__a41oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a41oi.functional.v, line:35:1, endln:61:10 |vpiName:A4 |vpiDirection:1 |vpiLowConn: @@ -51978,7 +51978,7 @@ design: (work@sky130_fd_sc_hd__a41oi) |vpiPort: \_port: (B1), line:41:5, endln:41:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a41oi (work@sky130_fd_sc_hd__a41oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a41oi.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__a41oi (work@sky130_fd_sc_hd__a41oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a41oi.functional.v, line:35:1, endln:61:10 |vpiName:B1 |vpiDirection:1 |vpiLowConn: @@ -51988,14 +51988,14 @@ design: (work@sky130_fd_sc_hd__a41oi) |vpiTypedef: \_logic_typespec: , line:50:12, endln:50:12 |uhdmtopModules: -\_module: work@sky130_fd_sc_hd__a41oi (work@sky130_fd_sc_hd__a41oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a41oi.functional.v, line:35:1, endln:61:10 +\_module_inst: work@sky130_fd_sc_hd__a41oi (work@sky130_fd_sc_hd__a41oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a41oi.functional.v, line:35:1, endln:61:10 |vpiName:work@sky130_fd_sc_hd__a41oi |vpiDefName:work@sky130_fd_sc_hd__a41oi |vpiTop:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a41oi.and0_out), line:53:10, endln:53:18 |vpiParent: - \_module: work@sky130_fd_sc_hd__a41oi (work@sky130_fd_sc_hd__a41oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a41oi.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__a41oi (work@sky130_fd_sc_hd__a41oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a41oi.functional.v, line:35:1, endln:61:10 |vpiTypespec: \_logic_typespec: , line:53:5, endln:53:9 |vpiName:and0_out @@ -52004,7 +52004,7 @@ design: (work@sky130_fd_sc_hd__a41oi) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a41oi.nor0_out_Y), line:54:10, endln:54:20 |vpiParent: - \_module: work@sky130_fd_sc_hd__a41oi (work@sky130_fd_sc_hd__a41oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a41oi.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__a41oi (work@sky130_fd_sc_hd__a41oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a41oi.functional.v, line:35:1, endln:61:10 |vpiTypespec: \_logic_typespec: , line:54:5, endln:54:9 |vpiName:nor0_out_Y @@ -52013,7 +52013,7 @@ design: (work@sky130_fd_sc_hd__a41oi) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a41oi.Y), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__a41oi (work@sky130_fd_sc_hd__a41oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a41oi.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__a41oi (work@sky130_fd_sc_hd__a41oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a41oi.functional.v, line:35:1, endln:61:10 |vpiTypespec: \_logic_typespec: , line:45:12, endln:45:12 |vpiName:Y @@ -52021,7 +52021,7 @@ design: (work@sky130_fd_sc_hd__a41oi) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a41oi.A1), line:37:5, endln:37:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a41oi (work@sky130_fd_sc_hd__a41oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a41oi.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__a41oi (work@sky130_fd_sc_hd__a41oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a41oi.functional.v, line:35:1, endln:61:10 |vpiTypespec: \_logic_typespec: , line:46:12, endln:46:12 |vpiName:A1 @@ -52029,7 +52029,7 @@ design: (work@sky130_fd_sc_hd__a41oi) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a41oi.A2), line:38:5, endln:38:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a41oi (work@sky130_fd_sc_hd__a41oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a41oi.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__a41oi (work@sky130_fd_sc_hd__a41oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a41oi.functional.v, line:35:1, endln:61:10 |vpiTypespec: \_logic_typespec: , line:47:12, endln:47:12 |vpiName:A2 @@ -52037,7 +52037,7 @@ design: (work@sky130_fd_sc_hd__a41oi) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a41oi.A3), line:39:5, endln:39:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a41oi (work@sky130_fd_sc_hd__a41oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a41oi.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__a41oi (work@sky130_fd_sc_hd__a41oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a41oi.functional.v, line:35:1, endln:61:10 |vpiTypespec: \_logic_typespec: , line:48:12, endln:48:12 |vpiName:A3 @@ -52045,7 +52045,7 @@ design: (work@sky130_fd_sc_hd__a41oi) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a41oi.A4), line:40:5, endln:40:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a41oi (work@sky130_fd_sc_hd__a41oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a41oi.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__a41oi (work@sky130_fd_sc_hd__a41oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a41oi.functional.v, line:35:1, endln:61:10 |vpiTypespec: \_logic_typespec: , line:49:12, endln:49:12 |vpiName:A4 @@ -52053,7 +52053,7 @@ design: (work@sky130_fd_sc_hd__a41oi) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a41oi.B1), line:41:5, endln:41:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a41oi (work@sky130_fd_sc_hd__a41oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a41oi.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__a41oi (work@sky130_fd_sc_hd__a41oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a41oi.functional.v, line:35:1, endln:61:10 |vpiTypespec: \_logic_typespec: , line:50:12, endln:50:12 |vpiName:B1 @@ -52062,7 +52062,7 @@ design: (work@sky130_fd_sc_hd__a41oi) |vpiPort: \_port: (Y), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__a41oi (work@sky130_fd_sc_hd__a41oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a41oi.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__a41oi (work@sky130_fd_sc_hd__a41oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a41oi.functional.v, line:35:1, endln:61:10 |vpiName:Y |vpiDirection:2 |vpiLowConn: @@ -52076,7 +52076,7 @@ design: (work@sky130_fd_sc_hd__a41oi) |vpiPort: \_port: (A1), line:37:5, endln:37:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a41oi (work@sky130_fd_sc_hd__a41oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a41oi.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__a41oi (work@sky130_fd_sc_hd__a41oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a41oi.functional.v, line:35:1, endln:61:10 |vpiName:A1 |vpiDirection:1 |vpiLowConn: @@ -52090,7 +52090,7 @@ design: (work@sky130_fd_sc_hd__a41oi) |vpiPort: \_port: (A2), line:38:5, endln:38:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a41oi (work@sky130_fd_sc_hd__a41oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a41oi.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__a41oi (work@sky130_fd_sc_hd__a41oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a41oi.functional.v, line:35:1, endln:61:10 |vpiName:A2 |vpiDirection:1 |vpiLowConn: @@ -52104,7 +52104,7 @@ design: (work@sky130_fd_sc_hd__a41oi) |vpiPort: \_port: (A3), line:39:5, endln:39:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a41oi (work@sky130_fd_sc_hd__a41oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a41oi.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__a41oi (work@sky130_fd_sc_hd__a41oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a41oi.functional.v, line:35:1, endln:61:10 |vpiName:A3 |vpiDirection:1 |vpiLowConn: @@ -52118,7 +52118,7 @@ design: (work@sky130_fd_sc_hd__a41oi) |vpiPort: \_port: (A4), line:40:5, endln:40:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a41oi (work@sky130_fd_sc_hd__a41oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a41oi.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__a41oi (work@sky130_fd_sc_hd__a41oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a41oi.functional.v, line:35:1, endln:61:10 |vpiName:A4 |vpiDirection:1 |vpiLowConn: @@ -52132,7 +52132,7 @@ design: (work@sky130_fd_sc_hd__a41oi) |vpiPort: \_port: (B1), line:41:5, endln:41:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a41oi (work@sky130_fd_sc_hd__a41oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a41oi.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__a41oi (work@sky130_fd_sc_hd__a41oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a41oi.functional.v, line:35:1, endln:61:10 |vpiName:B1 |vpiDirection:1 |vpiLowConn: @@ -52146,7 +52146,7 @@ design: (work@sky130_fd_sc_hd__a41oi) |vpiPrimitive: \_gate: work@and (work@sky130_fd_sc_hd__a41oi.and0), line:57:9, endln:57:43 |vpiParent: - \_module: work@sky130_fd_sc_hd__a41oi (work@sky130_fd_sc_hd__a41oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a41oi.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__a41oi (work@sky130_fd_sc_hd__a41oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a41oi.functional.v, line:35:1, endln:61:10 |vpiDefName:work@and |vpiName:and0 |vpiFullName:work@sky130_fd_sc_hd__a41oi.and0 @@ -52223,7 +52223,7 @@ design: (work@sky130_fd_sc_hd__a41oi) |vpiPrimitive: \_gate: work@nor (work@sky130_fd_sc_hd__a41oi.nor0), line:58:9, endln:58:43 |vpiParent: - \_module: work@sky130_fd_sc_hd__a41oi (work@sky130_fd_sc_hd__a41oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a41oi.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__a41oi (work@sky130_fd_sc_hd__a41oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a41oi.functional.v, line:35:1, endln:61:10 |vpiDefName:work@nor |vpiName:nor0 |vpiFullName:work@sky130_fd_sc_hd__a41oi.nor0 @@ -52272,7 +52272,7 @@ design: (work@sky130_fd_sc_hd__a41oi) |vpiPrimitive: \_gate: work@buf (work@sky130_fd_sc_hd__a41oi.buf0), line:59:9, endln:59:43 |vpiParent: - \_module: work@sky130_fd_sc_hd__a41oi (work@sky130_fd_sc_hd__a41oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a41oi.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__a41oi (work@sky130_fd_sc_hd__a41oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a41oi.functional.v, line:35:1, endln:61:10 |vpiDefName:work@buf |vpiName:buf0 |vpiFullName:work@sky130_fd_sc_hd__a41oi.buf0 @@ -52529,7 +52529,7 @@ design: (work@sky130_fd_sc_hd__sdfsbp) |vpiSize:3 |STRING:? 1 1 : 1 |uhdmallModules: -\_module: work@sky130_fd_sc_hd__sdfsbp (work@sky130_fd_sc_hd__sdfsbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfsbp.functional.v, line:38:1, endln:69:10 +\_module_inst: work@sky130_fd_sc_hd__sdfsbp (work@sky130_fd_sc_hd__sdfsbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfsbp.functional.v, line:38:1, endln:69:10 |vpiParent: \_design: (work@sky130_fd_sc_hd__sdfsbp) |vpiFullName:work@sky130_fd_sc_hd__sdfsbp @@ -52537,70 +52537,70 @@ design: (work@sky130_fd_sc_hd__sdfsbp) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__sdfsbp.buf_Q), line:58:10, endln:58:15 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfsbp (work@sky130_fd_sc_hd__sdfsbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfsbp.functional.v, line:38:1, endln:69:10 + \_module_inst: work@sky130_fd_sc_hd__sdfsbp (work@sky130_fd_sc_hd__sdfsbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfsbp.functional.v, line:38:1, endln:69:10 |vpiName:buf_Q |vpiFullName:work@sky130_fd_sc_hd__sdfsbp.buf_Q |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__sdfsbp.SET), line:59:10, endln:59:13 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfsbp (work@sky130_fd_sc_hd__sdfsbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfsbp.functional.v, line:38:1, endln:69:10 + \_module_inst: work@sky130_fd_sc_hd__sdfsbp (work@sky130_fd_sc_hd__sdfsbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfsbp.functional.v, line:38:1, endln:69:10 |vpiName:SET |vpiFullName:work@sky130_fd_sc_hd__sdfsbp.SET |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__sdfsbp.mux_out), line:60:10, endln:60:17 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfsbp (work@sky130_fd_sc_hd__sdfsbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfsbp.functional.v, line:38:1, endln:69:10 + \_module_inst: work@sky130_fd_sc_hd__sdfsbp (work@sky130_fd_sc_hd__sdfsbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfsbp.functional.v, line:38:1, endln:69:10 |vpiName:mux_out |vpiFullName:work@sky130_fd_sc_hd__sdfsbp.mux_out |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__sdfsbp.Q), line:39:5, endln:39:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfsbp (work@sky130_fd_sc_hd__sdfsbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfsbp.functional.v, line:38:1, endln:69:10 + \_module_inst: work@sky130_fd_sc_hd__sdfsbp (work@sky130_fd_sc_hd__sdfsbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfsbp.functional.v, line:38:1, endln:69:10 |vpiName:Q |vpiFullName:work@sky130_fd_sc_hd__sdfsbp.Q |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__sdfsbp.Q_N), line:40:5, endln:40:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfsbp (work@sky130_fd_sc_hd__sdfsbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfsbp.functional.v, line:38:1, endln:69:10 + \_module_inst: work@sky130_fd_sc_hd__sdfsbp (work@sky130_fd_sc_hd__sdfsbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfsbp.functional.v, line:38:1, endln:69:10 |vpiName:Q_N |vpiFullName:work@sky130_fd_sc_hd__sdfsbp.Q_N |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__sdfsbp.CLK), line:41:5, endln:41:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfsbp (work@sky130_fd_sc_hd__sdfsbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfsbp.functional.v, line:38:1, endln:69:10 + \_module_inst: work@sky130_fd_sc_hd__sdfsbp (work@sky130_fd_sc_hd__sdfsbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfsbp.functional.v, line:38:1, endln:69:10 |vpiName:CLK |vpiFullName:work@sky130_fd_sc_hd__sdfsbp.CLK |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__sdfsbp.D), line:42:5, endln:42:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfsbp (work@sky130_fd_sc_hd__sdfsbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfsbp.functional.v, line:38:1, endln:69:10 + \_module_inst: work@sky130_fd_sc_hd__sdfsbp (work@sky130_fd_sc_hd__sdfsbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfsbp.functional.v, line:38:1, endln:69:10 |vpiName:D |vpiFullName:work@sky130_fd_sc_hd__sdfsbp.D |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__sdfsbp.SCD), line:43:5, endln:43:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfsbp (work@sky130_fd_sc_hd__sdfsbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfsbp.functional.v, line:38:1, endln:69:10 + \_module_inst: work@sky130_fd_sc_hd__sdfsbp (work@sky130_fd_sc_hd__sdfsbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfsbp.functional.v, line:38:1, endln:69:10 |vpiName:SCD |vpiFullName:work@sky130_fd_sc_hd__sdfsbp.SCD |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__sdfsbp.SCE), line:44:5, endln:44:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfsbp (work@sky130_fd_sc_hd__sdfsbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfsbp.functional.v, line:38:1, endln:69:10 + \_module_inst: work@sky130_fd_sc_hd__sdfsbp (work@sky130_fd_sc_hd__sdfsbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfsbp.functional.v, line:38:1, endln:69:10 |vpiName:SCE |vpiFullName:work@sky130_fd_sc_hd__sdfsbp.SCE |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__sdfsbp.SET_B), line:45:5, endln:45:10 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfsbp (work@sky130_fd_sc_hd__sdfsbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfsbp.functional.v, line:38:1, endln:69:10 + \_module_inst: work@sky130_fd_sc_hd__sdfsbp (work@sky130_fd_sc_hd__sdfsbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfsbp.functional.v, line:38:1, endln:69:10 |vpiName:SET_B |vpiFullName:work@sky130_fd_sc_hd__sdfsbp.SET_B |vpiPort: \_port: (Q), line:39:5, endln:39:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfsbp (work@sky130_fd_sc_hd__sdfsbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfsbp.functional.v, line:38:1, endln:69:10 + \_module_inst: work@sky130_fd_sc_hd__sdfsbp (work@sky130_fd_sc_hd__sdfsbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfsbp.functional.v, line:38:1, endln:69:10 |vpiName:Q |vpiDirection:2 |vpiLowConn: @@ -52612,7 +52612,7 @@ design: (work@sky130_fd_sc_hd__sdfsbp) |vpiPort: \_port: (Q_N), line:40:5, endln:40:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfsbp (work@sky130_fd_sc_hd__sdfsbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfsbp.functional.v, line:38:1, endln:69:10 + \_module_inst: work@sky130_fd_sc_hd__sdfsbp (work@sky130_fd_sc_hd__sdfsbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfsbp.functional.v, line:38:1, endln:69:10 |vpiName:Q_N |vpiDirection:2 |vpiLowConn: @@ -52624,7 +52624,7 @@ design: (work@sky130_fd_sc_hd__sdfsbp) |vpiPort: \_port: (CLK), line:41:5, endln:41:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfsbp (work@sky130_fd_sc_hd__sdfsbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfsbp.functional.v, line:38:1, endln:69:10 + \_module_inst: work@sky130_fd_sc_hd__sdfsbp (work@sky130_fd_sc_hd__sdfsbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfsbp.functional.v, line:38:1, endln:69:10 |vpiName:CLK |vpiDirection:1 |vpiLowConn: @@ -52636,7 +52636,7 @@ design: (work@sky130_fd_sc_hd__sdfsbp) |vpiPort: \_port: (D), line:42:5, endln:42:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfsbp (work@sky130_fd_sc_hd__sdfsbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfsbp.functional.v, line:38:1, endln:69:10 + \_module_inst: work@sky130_fd_sc_hd__sdfsbp (work@sky130_fd_sc_hd__sdfsbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfsbp.functional.v, line:38:1, endln:69:10 |vpiName:D |vpiDirection:1 |vpiLowConn: @@ -52648,7 +52648,7 @@ design: (work@sky130_fd_sc_hd__sdfsbp) |vpiPort: \_port: (SCD), line:43:5, endln:43:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfsbp (work@sky130_fd_sc_hd__sdfsbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfsbp.functional.v, line:38:1, endln:69:10 + \_module_inst: work@sky130_fd_sc_hd__sdfsbp (work@sky130_fd_sc_hd__sdfsbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfsbp.functional.v, line:38:1, endln:69:10 |vpiName:SCD |vpiDirection:1 |vpiLowConn: @@ -52660,7 +52660,7 @@ design: (work@sky130_fd_sc_hd__sdfsbp) |vpiPort: \_port: (SCE), line:44:5, endln:44:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfsbp (work@sky130_fd_sc_hd__sdfsbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfsbp.functional.v, line:38:1, endln:69:10 + \_module_inst: work@sky130_fd_sc_hd__sdfsbp (work@sky130_fd_sc_hd__sdfsbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfsbp.functional.v, line:38:1, endln:69:10 |vpiName:SCE |vpiDirection:1 |vpiLowConn: @@ -52672,7 +52672,7 @@ design: (work@sky130_fd_sc_hd__sdfsbp) |vpiPort: \_port: (SET_B), line:45:5, endln:45:10 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfsbp (work@sky130_fd_sc_hd__sdfsbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfsbp.functional.v, line:38:1, endln:69:10 + \_module_inst: work@sky130_fd_sc_hd__sdfsbp (work@sky130_fd_sc_hd__sdfsbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfsbp.functional.v, line:38:1, endln:69:10 |vpiName:SET_B |vpiDirection:1 |vpiLowConn: @@ -52682,14 +52682,14 @@ design: (work@sky130_fd_sc_hd__sdfsbp) |vpiTypedef: \_logic_typespec: , line:55:12, endln:55:12 |uhdmtopModules: -\_module: work@sky130_fd_sc_hd__sdfsbp (work@sky130_fd_sc_hd__sdfsbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfsbp.functional.v, line:38:1, endln:69:10 +\_module_inst: work@sky130_fd_sc_hd__sdfsbp (work@sky130_fd_sc_hd__sdfsbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfsbp.functional.v, line:38:1, endln:69:10 |vpiName:work@sky130_fd_sc_hd__sdfsbp |vpiDefName:work@sky130_fd_sc_hd__sdfsbp |vpiTop:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__sdfsbp.buf_Q), line:58:10, endln:58:15 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfsbp (work@sky130_fd_sc_hd__sdfsbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfsbp.functional.v, line:38:1, endln:69:10 + \_module_inst: work@sky130_fd_sc_hd__sdfsbp (work@sky130_fd_sc_hd__sdfsbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfsbp.functional.v, line:38:1, endln:69:10 |vpiTypespec: \_logic_typespec: , line:58:5, endln:58:9 |vpiName:buf_Q @@ -52698,7 +52698,7 @@ design: (work@sky130_fd_sc_hd__sdfsbp) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__sdfsbp.SET), line:59:10, endln:59:13 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfsbp (work@sky130_fd_sc_hd__sdfsbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfsbp.functional.v, line:38:1, endln:69:10 + \_module_inst: work@sky130_fd_sc_hd__sdfsbp (work@sky130_fd_sc_hd__sdfsbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfsbp.functional.v, line:38:1, endln:69:10 |vpiTypespec: \_logic_typespec: , line:59:5, endln:59:9 |vpiName:SET @@ -52707,7 +52707,7 @@ design: (work@sky130_fd_sc_hd__sdfsbp) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__sdfsbp.mux_out), line:60:10, endln:60:17 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfsbp (work@sky130_fd_sc_hd__sdfsbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfsbp.functional.v, line:38:1, endln:69:10 + \_module_inst: work@sky130_fd_sc_hd__sdfsbp (work@sky130_fd_sc_hd__sdfsbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfsbp.functional.v, line:38:1, endln:69:10 |vpiTypespec: \_logic_typespec: , line:60:5, endln:60:9 |vpiName:mux_out @@ -52716,7 +52716,7 @@ design: (work@sky130_fd_sc_hd__sdfsbp) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__sdfsbp.Q), line:39:5, endln:39:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfsbp (work@sky130_fd_sc_hd__sdfsbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfsbp.functional.v, line:38:1, endln:69:10 + \_module_inst: work@sky130_fd_sc_hd__sdfsbp (work@sky130_fd_sc_hd__sdfsbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfsbp.functional.v, line:38:1, endln:69:10 |vpiTypespec: \_logic_typespec: , line:49:12, endln:49:12 |vpiName:Q @@ -52724,7 +52724,7 @@ design: (work@sky130_fd_sc_hd__sdfsbp) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__sdfsbp.Q_N), line:40:5, endln:40:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfsbp (work@sky130_fd_sc_hd__sdfsbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfsbp.functional.v, line:38:1, endln:69:10 + \_module_inst: work@sky130_fd_sc_hd__sdfsbp (work@sky130_fd_sc_hd__sdfsbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfsbp.functional.v, line:38:1, endln:69:10 |vpiTypespec: \_logic_typespec: , line:50:12, endln:50:12 |vpiName:Q_N @@ -52732,7 +52732,7 @@ design: (work@sky130_fd_sc_hd__sdfsbp) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__sdfsbp.CLK), line:41:5, endln:41:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfsbp (work@sky130_fd_sc_hd__sdfsbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfsbp.functional.v, line:38:1, endln:69:10 + \_module_inst: work@sky130_fd_sc_hd__sdfsbp (work@sky130_fd_sc_hd__sdfsbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfsbp.functional.v, line:38:1, endln:69:10 |vpiTypespec: \_logic_typespec: , line:51:12, endln:51:12 |vpiName:CLK @@ -52740,7 +52740,7 @@ design: (work@sky130_fd_sc_hd__sdfsbp) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__sdfsbp.D), line:42:5, endln:42:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfsbp (work@sky130_fd_sc_hd__sdfsbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfsbp.functional.v, line:38:1, endln:69:10 + \_module_inst: work@sky130_fd_sc_hd__sdfsbp (work@sky130_fd_sc_hd__sdfsbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfsbp.functional.v, line:38:1, endln:69:10 |vpiTypespec: \_logic_typespec: , line:52:12, endln:52:12 |vpiName:D @@ -52748,7 +52748,7 @@ design: (work@sky130_fd_sc_hd__sdfsbp) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__sdfsbp.SCD), line:43:5, endln:43:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfsbp (work@sky130_fd_sc_hd__sdfsbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfsbp.functional.v, line:38:1, endln:69:10 + \_module_inst: work@sky130_fd_sc_hd__sdfsbp (work@sky130_fd_sc_hd__sdfsbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfsbp.functional.v, line:38:1, endln:69:10 |vpiTypespec: \_logic_typespec: , line:53:12, endln:53:12 |vpiName:SCD @@ -52756,7 +52756,7 @@ design: (work@sky130_fd_sc_hd__sdfsbp) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__sdfsbp.SCE), line:44:5, endln:44:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfsbp (work@sky130_fd_sc_hd__sdfsbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfsbp.functional.v, line:38:1, endln:69:10 + \_module_inst: work@sky130_fd_sc_hd__sdfsbp (work@sky130_fd_sc_hd__sdfsbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfsbp.functional.v, line:38:1, endln:69:10 |vpiTypespec: \_logic_typespec: , line:54:12, endln:54:12 |vpiName:SCE @@ -52764,7 +52764,7 @@ design: (work@sky130_fd_sc_hd__sdfsbp) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__sdfsbp.SET_B), line:45:5, endln:45:10 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfsbp (work@sky130_fd_sc_hd__sdfsbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfsbp.functional.v, line:38:1, endln:69:10 + \_module_inst: work@sky130_fd_sc_hd__sdfsbp (work@sky130_fd_sc_hd__sdfsbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfsbp.functional.v, line:38:1, endln:69:10 |vpiTypespec: \_logic_typespec: , line:55:12, endln:55:12 |vpiName:SET_B @@ -52773,7 +52773,7 @@ design: (work@sky130_fd_sc_hd__sdfsbp) |vpiPort: \_port: (Q), line:39:5, endln:39:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfsbp (work@sky130_fd_sc_hd__sdfsbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfsbp.functional.v, line:38:1, endln:69:10 + \_module_inst: work@sky130_fd_sc_hd__sdfsbp (work@sky130_fd_sc_hd__sdfsbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfsbp.functional.v, line:38:1, endln:69:10 |vpiName:Q |vpiDirection:2 |vpiLowConn: @@ -52787,7 +52787,7 @@ design: (work@sky130_fd_sc_hd__sdfsbp) |vpiPort: \_port: (Q_N), line:40:5, endln:40:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfsbp (work@sky130_fd_sc_hd__sdfsbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfsbp.functional.v, line:38:1, endln:69:10 + \_module_inst: work@sky130_fd_sc_hd__sdfsbp (work@sky130_fd_sc_hd__sdfsbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfsbp.functional.v, line:38:1, endln:69:10 |vpiName:Q_N |vpiDirection:2 |vpiLowConn: @@ -52801,7 +52801,7 @@ design: (work@sky130_fd_sc_hd__sdfsbp) |vpiPort: \_port: (CLK), line:41:5, endln:41:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfsbp (work@sky130_fd_sc_hd__sdfsbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfsbp.functional.v, line:38:1, endln:69:10 + \_module_inst: work@sky130_fd_sc_hd__sdfsbp (work@sky130_fd_sc_hd__sdfsbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfsbp.functional.v, line:38:1, endln:69:10 |vpiName:CLK |vpiDirection:1 |vpiLowConn: @@ -52815,7 +52815,7 @@ design: (work@sky130_fd_sc_hd__sdfsbp) |vpiPort: \_port: (D), line:42:5, endln:42:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfsbp (work@sky130_fd_sc_hd__sdfsbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfsbp.functional.v, line:38:1, endln:69:10 + \_module_inst: work@sky130_fd_sc_hd__sdfsbp (work@sky130_fd_sc_hd__sdfsbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfsbp.functional.v, line:38:1, endln:69:10 |vpiName:D |vpiDirection:1 |vpiLowConn: @@ -52829,7 +52829,7 @@ design: (work@sky130_fd_sc_hd__sdfsbp) |vpiPort: \_port: (SCD), line:43:5, endln:43:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfsbp (work@sky130_fd_sc_hd__sdfsbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfsbp.functional.v, line:38:1, endln:69:10 + \_module_inst: work@sky130_fd_sc_hd__sdfsbp (work@sky130_fd_sc_hd__sdfsbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfsbp.functional.v, line:38:1, endln:69:10 |vpiName:SCD |vpiDirection:1 |vpiLowConn: @@ -52843,7 +52843,7 @@ design: (work@sky130_fd_sc_hd__sdfsbp) |vpiPort: \_port: (SCE), line:44:5, endln:44:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfsbp (work@sky130_fd_sc_hd__sdfsbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfsbp.functional.v, line:38:1, endln:69:10 + \_module_inst: work@sky130_fd_sc_hd__sdfsbp (work@sky130_fd_sc_hd__sdfsbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfsbp.functional.v, line:38:1, endln:69:10 |vpiName:SCE |vpiDirection:1 |vpiLowConn: @@ -52857,7 +52857,7 @@ design: (work@sky130_fd_sc_hd__sdfsbp) |vpiPort: \_port: (SET_B), line:45:5, endln:45:10 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfsbp (work@sky130_fd_sc_hd__sdfsbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfsbp.functional.v, line:38:1, endln:69:10 + \_module_inst: work@sky130_fd_sc_hd__sdfsbp (work@sky130_fd_sc_hd__sdfsbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfsbp.functional.v, line:38:1, endln:69:10 |vpiName:SET_B |vpiDirection:1 |vpiLowConn: @@ -52871,7 +52871,7 @@ design: (work@sky130_fd_sc_hd__sdfsbp) |vpiPrimitive: \_gate: work@not (work@sky130_fd_sc_hd__sdfsbp.not0), line:63:47, endln:63:85 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfsbp (work@sky130_fd_sc_hd__sdfsbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfsbp.functional.v, line:38:1, endln:69:10 + \_module_inst: work@sky130_fd_sc_hd__sdfsbp (work@sky130_fd_sc_hd__sdfsbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfsbp.functional.v, line:38:1, endln:69:10 |vpiDefName:work@not |vpiName:not0 |vpiFullName:work@sky130_fd_sc_hd__sdfsbp.not0 @@ -52906,7 +52906,7 @@ design: (work@sky130_fd_sc_hd__sdfsbp) |vpiPrimitive: \_udp: work@sky130_fd_sc_hd__udp_mux_2to1 (work@sky130_fd_sc_hd__sdfsbp.mux_2to10), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfsbp.functional.v, line:64:5, endln:64:86 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfsbp (work@sky130_fd_sc_hd__sdfsbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfsbp.functional.v, line:38:1, endln:69:10 + \_module_inst: work@sky130_fd_sc_hd__sdfsbp (work@sky130_fd_sc_hd__sdfsbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfsbp.functional.v, line:38:1, endln:69:10 |vpiDefName:work@sky130_fd_sc_hd__udp_mux_2to1 |vpiName:mux_2to10 |vpiFullName:work@sky130_fd_sc_hd__sdfsbp.mux_2to10 @@ -52915,7 +52915,7 @@ design: (work@sky130_fd_sc_hd__sdfsbp) |vpiPrimitive: \_udp: work@sky130_fd_sc_hd__udp_dff$PS (work@sky130_fd_sc_hd__sdfsbp.dff0), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfsbp.functional.v, line:65:5, endln:65:75 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfsbp (work@sky130_fd_sc_hd__sdfsbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfsbp.functional.v, line:38:1, endln:69:10 + \_module_inst: work@sky130_fd_sc_hd__sdfsbp (work@sky130_fd_sc_hd__sdfsbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfsbp.functional.v, line:38:1, endln:69:10 |vpiDefName:work@sky130_fd_sc_hd__udp_dff$PS |vpiName:dff0 |vpiFullName:work@sky130_fd_sc_hd__sdfsbp.dff0 @@ -52924,7 +52924,7 @@ design: (work@sky130_fd_sc_hd__sdfsbp) |vpiPrimitive: \_gate: work@buf (work@sky130_fd_sc_hd__sdfsbp.buf0), line:66:47, endln:66:85 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfsbp (work@sky130_fd_sc_hd__sdfsbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfsbp.functional.v, line:38:1, endln:69:10 + \_module_inst: work@sky130_fd_sc_hd__sdfsbp (work@sky130_fd_sc_hd__sdfsbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfsbp.functional.v, line:38:1, endln:69:10 |vpiDefName:work@buf |vpiName:buf0 |vpiFullName:work@sky130_fd_sc_hd__sdfsbp.buf0 @@ -52959,7 +52959,7 @@ design: (work@sky130_fd_sc_hd__sdfsbp) |vpiPrimitive: \_gate: work@not (work@sky130_fd_sc_hd__sdfsbp.not1), line:67:47, endln:67:85 |vpiParent: - \_module: work@sky130_fd_sc_hd__sdfsbp (work@sky130_fd_sc_hd__sdfsbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfsbp.functional.v, line:38:1, endln:69:10 + \_module_inst: work@sky130_fd_sc_hd__sdfsbp (work@sky130_fd_sc_hd__sdfsbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfsbp.functional.v, line:38:1, endln:69:10 |vpiDefName:work@not |vpiName:not1 |vpiFullName:work@sky130_fd_sc_hd__sdfsbp.not1 @@ -53002,7 +53002,7 @@ Processing: -cd cells/cells -DUNIT_DELAY -writepp -parse -nocache -nobuiltin -no design: (work@sky130_fd_sc_hd__einvp) |vpiName:work@sky130_fd_sc_hd__einvp |uhdmallModules: -\_module: work@sky130_fd_sc_hd__einvp (work@sky130_fd_sc_hd__einvp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__einvp.functional.v, line:33:1, endln:47:10 +\_module_inst: work@sky130_fd_sc_hd__einvp (work@sky130_fd_sc_hd__einvp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__einvp.functional.v, line:33:1, endln:47:10 |vpiParent: \_design: (work@sky130_fd_sc_hd__einvp) |vpiFullName:work@sky130_fd_sc_hd__einvp @@ -53010,25 +53010,25 @@ design: (work@sky130_fd_sc_hd__einvp) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__einvp.Z), line:34:5, endln:34:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__einvp (work@sky130_fd_sc_hd__einvp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__einvp.functional.v, line:33:1, endln:47:10 + \_module_inst: work@sky130_fd_sc_hd__einvp (work@sky130_fd_sc_hd__einvp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__einvp.functional.v, line:33:1, endln:47:10 |vpiName:Z |vpiFullName:work@sky130_fd_sc_hd__einvp.Z |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__einvp.A), line:35:5, endln:35:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__einvp (work@sky130_fd_sc_hd__einvp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__einvp.functional.v, line:33:1, endln:47:10 + \_module_inst: work@sky130_fd_sc_hd__einvp (work@sky130_fd_sc_hd__einvp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__einvp.functional.v, line:33:1, endln:47:10 |vpiName:A |vpiFullName:work@sky130_fd_sc_hd__einvp.A |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__einvp.TE), line:36:5, endln:36:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__einvp (work@sky130_fd_sc_hd__einvp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__einvp.functional.v, line:33:1, endln:47:10 + \_module_inst: work@sky130_fd_sc_hd__einvp (work@sky130_fd_sc_hd__einvp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__einvp.functional.v, line:33:1, endln:47:10 |vpiName:TE |vpiFullName:work@sky130_fd_sc_hd__einvp.TE |vpiPort: \_port: (Z), line:34:5, endln:34:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__einvp (work@sky130_fd_sc_hd__einvp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__einvp.functional.v, line:33:1, endln:47:10 + \_module_inst: work@sky130_fd_sc_hd__einvp (work@sky130_fd_sc_hd__einvp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__einvp.functional.v, line:33:1, endln:47:10 |vpiName:Z |vpiDirection:2 |vpiLowConn: @@ -53040,7 +53040,7 @@ design: (work@sky130_fd_sc_hd__einvp) |vpiPort: \_port: (A), line:35:5, endln:35:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__einvp (work@sky130_fd_sc_hd__einvp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__einvp.functional.v, line:33:1, endln:47:10 + \_module_inst: work@sky130_fd_sc_hd__einvp (work@sky130_fd_sc_hd__einvp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__einvp.functional.v, line:33:1, endln:47:10 |vpiName:A |vpiDirection:1 |vpiLowConn: @@ -53052,7 +53052,7 @@ design: (work@sky130_fd_sc_hd__einvp) |vpiPort: \_port: (TE), line:36:5, endln:36:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__einvp (work@sky130_fd_sc_hd__einvp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__einvp.functional.v, line:33:1, endln:47:10 + \_module_inst: work@sky130_fd_sc_hd__einvp (work@sky130_fd_sc_hd__einvp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__einvp.functional.v, line:33:1, endln:47:10 |vpiName:TE |vpiDirection:1 |vpiLowConn: @@ -53062,14 +53062,14 @@ design: (work@sky130_fd_sc_hd__einvp) |vpiTypedef: \_logic_typespec: , line:42:12, endln:42:12 |uhdmtopModules: -\_module: work@sky130_fd_sc_hd__einvp (work@sky130_fd_sc_hd__einvp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__einvp.functional.v, line:33:1, endln:47:10 +\_module_inst: work@sky130_fd_sc_hd__einvp (work@sky130_fd_sc_hd__einvp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__einvp.functional.v, line:33:1, endln:47:10 |vpiName:work@sky130_fd_sc_hd__einvp |vpiDefName:work@sky130_fd_sc_hd__einvp |vpiTop:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__einvp.Z), line:34:5, endln:34:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__einvp (work@sky130_fd_sc_hd__einvp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__einvp.functional.v, line:33:1, endln:47:10 + \_module_inst: work@sky130_fd_sc_hd__einvp (work@sky130_fd_sc_hd__einvp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__einvp.functional.v, line:33:1, endln:47:10 |vpiTypespec: \_logic_typespec: , line:40:12, endln:40:12 |vpiName:Z @@ -53077,7 +53077,7 @@ design: (work@sky130_fd_sc_hd__einvp) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__einvp.A), line:35:5, endln:35:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__einvp (work@sky130_fd_sc_hd__einvp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__einvp.functional.v, line:33:1, endln:47:10 + \_module_inst: work@sky130_fd_sc_hd__einvp (work@sky130_fd_sc_hd__einvp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__einvp.functional.v, line:33:1, endln:47:10 |vpiTypespec: \_logic_typespec: , line:41:12, endln:41:12 |vpiName:A @@ -53085,7 +53085,7 @@ design: (work@sky130_fd_sc_hd__einvp) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__einvp.TE), line:36:5, endln:36:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__einvp (work@sky130_fd_sc_hd__einvp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__einvp.functional.v, line:33:1, endln:47:10 + \_module_inst: work@sky130_fd_sc_hd__einvp (work@sky130_fd_sc_hd__einvp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__einvp.functional.v, line:33:1, endln:47:10 |vpiTypespec: \_logic_typespec: , line:42:12, endln:42:12 |vpiName:TE @@ -53094,7 +53094,7 @@ design: (work@sky130_fd_sc_hd__einvp) |vpiPort: \_port: (Z), line:34:5, endln:34:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__einvp (work@sky130_fd_sc_hd__einvp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__einvp.functional.v, line:33:1, endln:47:10 + \_module_inst: work@sky130_fd_sc_hd__einvp (work@sky130_fd_sc_hd__einvp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__einvp.functional.v, line:33:1, endln:47:10 |vpiName:Z |vpiDirection:2 |vpiLowConn: @@ -53108,7 +53108,7 @@ design: (work@sky130_fd_sc_hd__einvp) |vpiPort: \_port: (A), line:35:5, endln:35:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__einvp (work@sky130_fd_sc_hd__einvp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__einvp.functional.v, line:33:1, endln:47:10 + \_module_inst: work@sky130_fd_sc_hd__einvp (work@sky130_fd_sc_hd__einvp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__einvp.functional.v, line:33:1, endln:47:10 |vpiName:A |vpiDirection:1 |vpiLowConn: @@ -53122,7 +53122,7 @@ design: (work@sky130_fd_sc_hd__einvp) |vpiPort: \_port: (TE), line:36:5, endln:36:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__einvp (work@sky130_fd_sc_hd__einvp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__einvp.functional.v, line:33:1, endln:47:10 + \_module_inst: work@sky130_fd_sc_hd__einvp (work@sky130_fd_sc_hd__einvp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__einvp.functional.v, line:33:1, endln:47:10 |vpiName:TE |vpiDirection:1 |vpiLowConn: @@ -53136,7 +53136,7 @@ design: (work@sky130_fd_sc_hd__einvp) |vpiPrimitive: \_gate: work@notif1 (work@sky130_fd_sc_hd__einvp.notif10), line:45:12, endln:45:45 |vpiParent: - \_module: work@sky130_fd_sc_hd__einvp (work@sky130_fd_sc_hd__einvp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__einvp.functional.v, line:33:1, endln:47:10 + \_module_inst: work@sky130_fd_sc_hd__einvp (work@sky130_fd_sc_hd__einvp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__einvp.functional.v, line:33:1, endln:47:10 |vpiDefName:work@notif1 |vpiName:notif10 |vpiFullName:work@sky130_fd_sc_hd__einvp.notif10 @@ -53193,7 +53193,7 @@ Processing: -cd cells/cells -DUNIT_DELAY -writepp -parse -nocache -nobuiltin -no design: (work@sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell) |vpiName:work@sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell |uhdmallModules: -\_module: work@sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell (work@sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell.functional.v, line:35:1, endln:47:10 +\_module_inst: work@sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell (work@sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell.functional.v, line:35:1, endln:47:10 |vpiParent: \_design: (work@sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell) |vpiFullName:work@sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell @@ -53201,19 +53201,19 @@ design: (work@sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell.X), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell (work@sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell.functional.v, line:35:1, endln:47:10 + \_module_inst: work@sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell (work@sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell.functional.v, line:35:1, endln:47:10 |vpiName:X |vpiFullName:work@sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell.X |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell.A), line:37:5, endln:37:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell (work@sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell.functional.v, line:35:1, endln:47:10 + \_module_inst: work@sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell (work@sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell.functional.v, line:35:1, endln:47:10 |vpiName:A |vpiFullName:work@sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell.A |vpiPort: \_port: (X), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell (work@sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell.functional.v, line:35:1, endln:47:10 + \_module_inst: work@sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell (work@sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell.functional.v, line:35:1, endln:47:10 |vpiName:X |vpiDirection:2 |vpiLowConn: @@ -53225,7 +53225,7 @@ design: (work@sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell) |vpiPort: \_port: (A), line:37:5, endln:37:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell (work@sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell.functional.v, line:35:1, endln:47:10 + \_module_inst: work@sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell (work@sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell.functional.v, line:35:1, endln:47:10 |vpiName:A |vpiDirection:1 |vpiLowConn: @@ -53235,14 +53235,14 @@ design: (work@sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell) |vpiTypedef: \_logic_typespec: , line:42:12, endln:42:12 |uhdmtopModules: -\_module: work@sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell (work@sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell.functional.v, line:35:1, endln:47:10 +\_module_inst: work@sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell (work@sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell.functional.v, line:35:1, endln:47:10 |vpiName:work@sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell |vpiDefName:work@sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell |vpiTop:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell.X), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell (work@sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell.functional.v, line:35:1, endln:47:10 + \_module_inst: work@sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell (work@sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell.functional.v, line:35:1, endln:47:10 |vpiTypespec: \_logic_typespec: , line:41:12, endln:41:12 |vpiName:X @@ -53250,7 +53250,7 @@ design: (work@sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell.A), line:37:5, endln:37:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell (work@sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell.functional.v, line:35:1, endln:47:10 + \_module_inst: work@sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell (work@sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell.functional.v, line:35:1, endln:47:10 |vpiTypespec: \_logic_typespec: , line:42:12, endln:42:12 |vpiName:A @@ -53259,7 +53259,7 @@ design: (work@sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell) |vpiPort: \_port: (X), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell (work@sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell.functional.v, line:35:1, endln:47:10 + \_module_inst: work@sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell (work@sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell.functional.v, line:35:1, endln:47:10 |vpiName:X |vpiDirection:2 |vpiLowConn: @@ -53273,7 +53273,7 @@ design: (work@sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell) |vpiPort: \_port: (A), line:37:5, endln:37:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell (work@sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell.functional.v, line:35:1, endln:47:10 + \_module_inst: work@sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell (work@sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell.functional.v, line:35:1, endln:47:10 |vpiName:A |vpiDirection:1 |vpiLowConn: @@ -53287,7 +53287,7 @@ design: (work@sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell) |vpiPrimitive: \_gate: work@buf (work@sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell.buf0), line:45:9, endln:45:39 |vpiParent: - \_module: work@sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell (work@sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell.functional.v, line:35:1, endln:47:10 + \_module_inst: work@sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell (work@sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell.functional.v, line:35:1, endln:47:10 |vpiDefName:work@buf |vpiName:buf0 |vpiFullName:work@sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell.buf0 @@ -53330,7 +53330,7 @@ Processing: -cd cells/cells -DUNIT_DELAY -writepp -parse -nocache -nobuiltin -no design: (work@sky130_fd_sc_hd__bufbuf) |vpiName:work@sky130_fd_sc_hd__bufbuf |uhdmallModules: -\_module: work@sky130_fd_sc_hd__bufbuf (work@sky130_fd_sc_hd__bufbuf), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__bufbuf.functional.v, line:33:1, endln:49:10 +\_module_inst: work@sky130_fd_sc_hd__bufbuf (work@sky130_fd_sc_hd__bufbuf), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__bufbuf.functional.v, line:33:1, endln:49:10 |vpiParent: \_design: (work@sky130_fd_sc_hd__bufbuf) |vpiFullName:work@sky130_fd_sc_hd__bufbuf @@ -53338,26 +53338,26 @@ design: (work@sky130_fd_sc_hd__bufbuf) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__bufbuf.buf0_out_X), line:43:10, endln:43:20 |vpiParent: - \_module: work@sky130_fd_sc_hd__bufbuf (work@sky130_fd_sc_hd__bufbuf), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__bufbuf.functional.v, line:33:1, endln:49:10 + \_module_inst: work@sky130_fd_sc_hd__bufbuf (work@sky130_fd_sc_hd__bufbuf), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__bufbuf.functional.v, line:33:1, endln:49:10 |vpiName:buf0_out_X |vpiFullName:work@sky130_fd_sc_hd__bufbuf.buf0_out_X |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__bufbuf.X), line:34:5, endln:34:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__bufbuf (work@sky130_fd_sc_hd__bufbuf), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__bufbuf.functional.v, line:33:1, endln:49:10 + \_module_inst: work@sky130_fd_sc_hd__bufbuf (work@sky130_fd_sc_hd__bufbuf), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__bufbuf.functional.v, line:33:1, endln:49:10 |vpiName:X |vpiFullName:work@sky130_fd_sc_hd__bufbuf.X |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__bufbuf.A), line:35:5, endln:35:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__bufbuf (work@sky130_fd_sc_hd__bufbuf), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__bufbuf.functional.v, line:33:1, endln:49:10 + \_module_inst: work@sky130_fd_sc_hd__bufbuf (work@sky130_fd_sc_hd__bufbuf), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__bufbuf.functional.v, line:33:1, endln:49:10 |vpiName:A |vpiFullName:work@sky130_fd_sc_hd__bufbuf.A |vpiPort: \_port: (X), line:34:5, endln:34:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__bufbuf (work@sky130_fd_sc_hd__bufbuf), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__bufbuf.functional.v, line:33:1, endln:49:10 + \_module_inst: work@sky130_fd_sc_hd__bufbuf (work@sky130_fd_sc_hd__bufbuf), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__bufbuf.functional.v, line:33:1, endln:49:10 |vpiName:X |vpiDirection:2 |vpiLowConn: @@ -53369,7 +53369,7 @@ design: (work@sky130_fd_sc_hd__bufbuf) |vpiPort: \_port: (A), line:35:5, endln:35:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__bufbuf (work@sky130_fd_sc_hd__bufbuf), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__bufbuf.functional.v, line:33:1, endln:49:10 + \_module_inst: work@sky130_fd_sc_hd__bufbuf (work@sky130_fd_sc_hd__bufbuf), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__bufbuf.functional.v, line:33:1, endln:49:10 |vpiName:A |vpiDirection:1 |vpiLowConn: @@ -53379,14 +53379,14 @@ design: (work@sky130_fd_sc_hd__bufbuf) |vpiTypedef: \_logic_typespec: , line:40:12, endln:40:12 |uhdmtopModules: -\_module: work@sky130_fd_sc_hd__bufbuf (work@sky130_fd_sc_hd__bufbuf), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__bufbuf.functional.v, line:33:1, endln:49:10 +\_module_inst: work@sky130_fd_sc_hd__bufbuf (work@sky130_fd_sc_hd__bufbuf), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__bufbuf.functional.v, line:33:1, endln:49:10 |vpiName:work@sky130_fd_sc_hd__bufbuf |vpiDefName:work@sky130_fd_sc_hd__bufbuf |vpiTop:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__bufbuf.buf0_out_X), line:43:10, endln:43:20 |vpiParent: - \_module: work@sky130_fd_sc_hd__bufbuf (work@sky130_fd_sc_hd__bufbuf), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__bufbuf.functional.v, line:33:1, endln:49:10 + \_module_inst: work@sky130_fd_sc_hd__bufbuf (work@sky130_fd_sc_hd__bufbuf), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__bufbuf.functional.v, line:33:1, endln:49:10 |vpiTypespec: \_logic_typespec: , line:43:5, endln:43:9 |vpiName:buf0_out_X @@ -53395,7 +53395,7 @@ design: (work@sky130_fd_sc_hd__bufbuf) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__bufbuf.X), line:34:5, endln:34:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__bufbuf (work@sky130_fd_sc_hd__bufbuf), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__bufbuf.functional.v, line:33:1, endln:49:10 + \_module_inst: work@sky130_fd_sc_hd__bufbuf (work@sky130_fd_sc_hd__bufbuf), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__bufbuf.functional.v, line:33:1, endln:49:10 |vpiTypespec: \_logic_typespec: , line:39:12, endln:39:12 |vpiName:X @@ -53403,7 +53403,7 @@ design: (work@sky130_fd_sc_hd__bufbuf) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__bufbuf.A), line:35:5, endln:35:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__bufbuf (work@sky130_fd_sc_hd__bufbuf), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__bufbuf.functional.v, line:33:1, endln:49:10 + \_module_inst: work@sky130_fd_sc_hd__bufbuf (work@sky130_fd_sc_hd__bufbuf), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__bufbuf.functional.v, line:33:1, endln:49:10 |vpiTypespec: \_logic_typespec: , line:40:12, endln:40:12 |vpiName:A @@ -53412,7 +53412,7 @@ design: (work@sky130_fd_sc_hd__bufbuf) |vpiPort: \_port: (X), line:34:5, endln:34:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__bufbuf (work@sky130_fd_sc_hd__bufbuf), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__bufbuf.functional.v, line:33:1, endln:49:10 + \_module_inst: work@sky130_fd_sc_hd__bufbuf (work@sky130_fd_sc_hd__bufbuf), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__bufbuf.functional.v, line:33:1, endln:49:10 |vpiName:X |vpiDirection:2 |vpiLowConn: @@ -53426,7 +53426,7 @@ design: (work@sky130_fd_sc_hd__bufbuf) |vpiPort: \_port: (A), line:35:5, endln:35:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__bufbuf (work@sky130_fd_sc_hd__bufbuf), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__bufbuf.functional.v, line:33:1, endln:49:10 + \_module_inst: work@sky130_fd_sc_hd__bufbuf (work@sky130_fd_sc_hd__bufbuf), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__bufbuf.functional.v, line:33:1, endln:49:10 |vpiName:A |vpiDirection:1 |vpiLowConn: @@ -53440,7 +53440,7 @@ design: (work@sky130_fd_sc_hd__bufbuf) |vpiPrimitive: \_gate: work@buf (work@sky130_fd_sc_hd__bufbuf.buf0), line:46:9, endln:46:43 |vpiParent: - \_module: work@sky130_fd_sc_hd__bufbuf (work@sky130_fd_sc_hd__bufbuf), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__bufbuf.functional.v, line:33:1, endln:49:10 + \_module_inst: work@sky130_fd_sc_hd__bufbuf (work@sky130_fd_sc_hd__bufbuf), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__bufbuf.functional.v, line:33:1, endln:49:10 |vpiDefName:work@buf |vpiName:buf0 |vpiFullName:work@sky130_fd_sc_hd__bufbuf.buf0 @@ -53475,7 +53475,7 @@ design: (work@sky130_fd_sc_hd__bufbuf) |vpiPrimitive: \_gate: work@buf (work@sky130_fd_sc_hd__bufbuf.buf1), line:47:9, endln:47:43 |vpiParent: - \_module: work@sky130_fd_sc_hd__bufbuf (work@sky130_fd_sc_hd__bufbuf), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__bufbuf.functional.v, line:33:1, endln:49:10 + \_module_inst: work@sky130_fd_sc_hd__bufbuf (work@sky130_fd_sc_hd__bufbuf), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__bufbuf.functional.v, line:33:1, endln:49:10 |vpiDefName:work@buf |vpiName:buf1 |vpiFullName:work@sky130_fd_sc_hd__bufbuf.buf1 @@ -53518,7 +53518,7 @@ Processing: -cd cells/cells -DUNIT_DELAY -writepp -parse -nocache -nobuiltin -no design: (work@sky130_fd_sc_hd__xor3) |vpiName:work@sky130_fd_sc_hd__xor3 |uhdmallModules: -\_module: work@sky130_fd_sc_hd__xor3 (work@sky130_fd_sc_hd__xor3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__xor3.functional.v, line:35:1, endln:55:10 +\_module_inst: work@sky130_fd_sc_hd__xor3 (work@sky130_fd_sc_hd__xor3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__xor3.functional.v, line:35:1, endln:55:10 |vpiParent: \_design: (work@sky130_fd_sc_hd__xor3) |vpiFullName:work@sky130_fd_sc_hd__xor3 @@ -53526,38 +53526,38 @@ design: (work@sky130_fd_sc_hd__xor3) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__xor3.xor0_out_X), line:49:10, endln:49:20 |vpiParent: - \_module: work@sky130_fd_sc_hd__xor3 (work@sky130_fd_sc_hd__xor3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__xor3.functional.v, line:35:1, endln:55:10 + \_module_inst: work@sky130_fd_sc_hd__xor3 (work@sky130_fd_sc_hd__xor3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__xor3.functional.v, line:35:1, endln:55:10 |vpiName:xor0_out_X |vpiFullName:work@sky130_fd_sc_hd__xor3.xor0_out_X |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__xor3.X), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__xor3 (work@sky130_fd_sc_hd__xor3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__xor3.functional.v, line:35:1, endln:55:10 + \_module_inst: work@sky130_fd_sc_hd__xor3 (work@sky130_fd_sc_hd__xor3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__xor3.functional.v, line:35:1, endln:55:10 |vpiName:X |vpiFullName:work@sky130_fd_sc_hd__xor3.X |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__xor3.A), line:37:5, endln:37:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__xor3 (work@sky130_fd_sc_hd__xor3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__xor3.functional.v, line:35:1, endln:55:10 + \_module_inst: work@sky130_fd_sc_hd__xor3 (work@sky130_fd_sc_hd__xor3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__xor3.functional.v, line:35:1, endln:55:10 |vpiName:A |vpiFullName:work@sky130_fd_sc_hd__xor3.A |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__xor3.B), line:38:5, endln:38:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__xor3 (work@sky130_fd_sc_hd__xor3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__xor3.functional.v, line:35:1, endln:55:10 + \_module_inst: work@sky130_fd_sc_hd__xor3 (work@sky130_fd_sc_hd__xor3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__xor3.functional.v, line:35:1, endln:55:10 |vpiName:B |vpiFullName:work@sky130_fd_sc_hd__xor3.B |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__xor3.C), line:39:5, endln:39:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__xor3 (work@sky130_fd_sc_hd__xor3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__xor3.functional.v, line:35:1, endln:55:10 + \_module_inst: work@sky130_fd_sc_hd__xor3 (work@sky130_fd_sc_hd__xor3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__xor3.functional.v, line:35:1, endln:55:10 |vpiName:C |vpiFullName:work@sky130_fd_sc_hd__xor3.C |vpiPort: \_port: (X), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__xor3 (work@sky130_fd_sc_hd__xor3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__xor3.functional.v, line:35:1, endln:55:10 + \_module_inst: work@sky130_fd_sc_hd__xor3 (work@sky130_fd_sc_hd__xor3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__xor3.functional.v, line:35:1, endln:55:10 |vpiName:X |vpiDirection:2 |vpiLowConn: @@ -53569,7 +53569,7 @@ design: (work@sky130_fd_sc_hd__xor3) |vpiPort: \_port: (A), line:37:5, endln:37:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__xor3 (work@sky130_fd_sc_hd__xor3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__xor3.functional.v, line:35:1, endln:55:10 + \_module_inst: work@sky130_fd_sc_hd__xor3 (work@sky130_fd_sc_hd__xor3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__xor3.functional.v, line:35:1, endln:55:10 |vpiName:A |vpiDirection:1 |vpiLowConn: @@ -53581,7 +53581,7 @@ design: (work@sky130_fd_sc_hd__xor3) |vpiPort: \_port: (B), line:38:5, endln:38:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__xor3 (work@sky130_fd_sc_hd__xor3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__xor3.functional.v, line:35:1, endln:55:10 + \_module_inst: work@sky130_fd_sc_hd__xor3 (work@sky130_fd_sc_hd__xor3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__xor3.functional.v, line:35:1, endln:55:10 |vpiName:B |vpiDirection:1 |vpiLowConn: @@ -53593,7 +53593,7 @@ design: (work@sky130_fd_sc_hd__xor3) |vpiPort: \_port: (C), line:39:5, endln:39:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__xor3 (work@sky130_fd_sc_hd__xor3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__xor3.functional.v, line:35:1, endln:55:10 + \_module_inst: work@sky130_fd_sc_hd__xor3 (work@sky130_fd_sc_hd__xor3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__xor3.functional.v, line:35:1, endln:55:10 |vpiName:C |vpiDirection:1 |vpiLowConn: @@ -53603,14 +53603,14 @@ design: (work@sky130_fd_sc_hd__xor3) |vpiTypedef: \_logic_typespec: , line:46:12, endln:46:12 |uhdmtopModules: -\_module: work@sky130_fd_sc_hd__xor3 (work@sky130_fd_sc_hd__xor3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__xor3.functional.v, line:35:1, endln:55:10 +\_module_inst: work@sky130_fd_sc_hd__xor3 (work@sky130_fd_sc_hd__xor3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__xor3.functional.v, line:35:1, endln:55:10 |vpiName:work@sky130_fd_sc_hd__xor3 |vpiDefName:work@sky130_fd_sc_hd__xor3 |vpiTop:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__xor3.xor0_out_X), line:49:10, endln:49:20 |vpiParent: - \_module: work@sky130_fd_sc_hd__xor3 (work@sky130_fd_sc_hd__xor3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__xor3.functional.v, line:35:1, endln:55:10 + \_module_inst: work@sky130_fd_sc_hd__xor3 (work@sky130_fd_sc_hd__xor3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__xor3.functional.v, line:35:1, endln:55:10 |vpiTypespec: \_logic_typespec: , line:49:5, endln:49:9 |vpiName:xor0_out_X @@ -53619,7 +53619,7 @@ design: (work@sky130_fd_sc_hd__xor3) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__xor3.X), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__xor3 (work@sky130_fd_sc_hd__xor3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__xor3.functional.v, line:35:1, endln:55:10 + \_module_inst: work@sky130_fd_sc_hd__xor3 (work@sky130_fd_sc_hd__xor3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__xor3.functional.v, line:35:1, endln:55:10 |vpiTypespec: \_logic_typespec: , line:43:12, endln:43:12 |vpiName:X @@ -53627,7 +53627,7 @@ design: (work@sky130_fd_sc_hd__xor3) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__xor3.A), line:37:5, endln:37:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__xor3 (work@sky130_fd_sc_hd__xor3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__xor3.functional.v, line:35:1, endln:55:10 + \_module_inst: work@sky130_fd_sc_hd__xor3 (work@sky130_fd_sc_hd__xor3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__xor3.functional.v, line:35:1, endln:55:10 |vpiTypespec: \_logic_typespec: , line:44:12, endln:44:12 |vpiName:A @@ -53635,7 +53635,7 @@ design: (work@sky130_fd_sc_hd__xor3) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__xor3.B), line:38:5, endln:38:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__xor3 (work@sky130_fd_sc_hd__xor3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__xor3.functional.v, line:35:1, endln:55:10 + \_module_inst: work@sky130_fd_sc_hd__xor3 (work@sky130_fd_sc_hd__xor3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__xor3.functional.v, line:35:1, endln:55:10 |vpiTypespec: \_logic_typespec: , line:45:12, endln:45:12 |vpiName:B @@ -53643,7 +53643,7 @@ design: (work@sky130_fd_sc_hd__xor3) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__xor3.C), line:39:5, endln:39:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__xor3 (work@sky130_fd_sc_hd__xor3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__xor3.functional.v, line:35:1, endln:55:10 + \_module_inst: work@sky130_fd_sc_hd__xor3 (work@sky130_fd_sc_hd__xor3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__xor3.functional.v, line:35:1, endln:55:10 |vpiTypespec: \_logic_typespec: , line:46:12, endln:46:12 |vpiName:C @@ -53652,7 +53652,7 @@ design: (work@sky130_fd_sc_hd__xor3) |vpiPort: \_port: (X), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__xor3 (work@sky130_fd_sc_hd__xor3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__xor3.functional.v, line:35:1, endln:55:10 + \_module_inst: work@sky130_fd_sc_hd__xor3 (work@sky130_fd_sc_hd__xor3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__xor3.functional.v, line:35:1, endln:55:10 |vpiName:X |vpiDirection:2 |vpiLowConn: @@ -53666,7 +53666,7 @@ design: (work@sky130_fd_sc_hd__xor3) |vpiPort: \_port: (A), line:37:5, endln:37:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__xor3 (work@sky130_fd_sc_hd__xor3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__xor3.functional.v, line:35:1, endln:55:10 + \_module_inst: work@sky130_fd_sc_hd__xor3 (work@sky130_fd_sc_hd__xor3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__xor3.functional.v, line:35:1, endln:55:10 |vpiName:A |vpiDirection:1 |vpiLowConn: @@ -53680,7 +53680,7 @@ design: (work@sky130_fd_sc_hd__xor3) |vpiPort: \_port: (B), line:38:5, endln:38:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__xor3 (work@sky130_fd_sc_hd__xor3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__xor3.functional.v, line:35:1, endln:55:10 + \_module_inst: work@sky130_fd_sc_hd__xor3 (work@sky130_fd_sc_hd__xor3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__xor3.functional.v, line:35:1, endln:55:10 |vpiName:B |vpiDirection:1 |vpiLowConn: @@ -53694,7 +53694,7 @@ design: (work@sky130_fd_sc_hd__xor3) |vpiPort: \_port: (C), line:39:5, endln:39:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__xor3 (work@sky130_fd_sc_hd__xor3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__xor3.functional.v, line:35:1, endln:55:10 + \_module_inst: work@sky130_fd_sc_hd__xor3 (work@sky130_fd_sc_hd__xor3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__xor3.functional.v, line:35:1, endln:55:10 |vpiName:C |vpiDirection:1 |vpiLowConn: @@ -53708,7 +53708,7 @@ design: (work@sky130_fd_sc_hd__xor3) |vpiPrimitive: \_gate: work@xor (work@sky130_fd_sc_hd__xor3.xor0), line:52:9, endln:52:43 |vpiParent: - \_module: work@sky130_fd_sc_hd__xor3 (work@sky130_fd_sc_hd__xor3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__xor3.functional.v, line:35:1, endln:55:10 + \_module_inst: work@sky130_fd_sc_hd__xor3 (work@sky130_fd_sc_hd__xor3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__xor3.functional.v, line:35:1, endln:55:10 |vpiDefName:work@xor |vpiName:xor0 |vpiFullName:work@sky130_fd_sc_hd__xor3.xor0 @@ -53771,7 +53771,7 @@ design: (work@sky130_fd_sc_hd__xor3) |vpiPrimitive: \_gate: work@buf (work@sky130_fd_sc_hd__xor3.buf0), line:53:9, endln:53:43 |vpiParent: - \_module: work@sky130_fd_sc_hd__xor3 (work@sky130_fd_sc_hd__xor3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__xor3.functional.v, line:35:1, endln:55:10 + \_module_inst: work@sky130_fd_sc_hd__xor3 (work@sky130_fd_sc_hd__xor3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__xor3.functional.v, line:35:1, endln:55:10 |vpiDefName:work@buf |vpiName:buf0 |vpiFullName:work@sky130_fd_sc_hd__xor3.buf0 @@ -53814,7 +53814,7 @@ Processing: -cd cells/cells -DUNIT_DELAY -writepp -parse -nocache -nobuiltin -no design: (work@sky130_fd_sc_hd__o2bb2ai) |vpiName:work@sky130_fd_sc_hd__o2bb2ai |uhdmallModules: -\_module: work@sky130_fd_sc_hd__o2bb2ai (work@sky130_fd_sc_hd__o2bb2ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o2bb2ai.functional.v, line:35:1, endln:61:10 +\_module_inst: work@sky130_fd_sc_hd__o2bb2ai (work@sky130_fd_sc_hd__o2bb2ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o2bb2ai.functional.v, line:35:1, endln:61:10 |vpiParent: \_design: (work@sky130_fd_sc_hd__o2bb2ai) |vpiFullName:work@sky130_fd_sc_hd__o2bb2ai @@ -53822,58 +53822,58 @@ design: (work@sky130_fd_sc_hd__o2bb2ai) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o2bb2ai.nand0_out), line:51:10, endln:51:19 |vpiParent: - \_module: work@sky130_fd_sc_hd__o2bb2ai (work@sky130_fd_sc_hd__o2bb2ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o2bb2ai.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o2bb2ai (work@sky130_fd_sc_hd__o2bb2ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o2bb2ai.functional.v, line:35:1, endln:61:10 |vpiName:nand0_out |vpiFullName:work@sky130_fd_sc_hd__o2bb2ai.nand0_out |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o2bb2ai.or0_out), line:52:10, endln:52:17 |vpiParent: - \_module: work@sky130_fd_sc_hd__o2bb2ai (work@sky130_fd_sc_hd__o2bb2ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o2bb2ai.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o2bb2ai (work@sky130_fd_sc_hd__o2bb2ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o2bb2ai.functional.v, line:35:1, endln:61:10 |vpiName:or0_out |vpiFullName:work@sky130_fd_sc_hd__o2bb2ai.or0_out |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o2bb2ai.nand1_out_Y), line:53:10, endln:53:21 |vpiParent: - \_module: work@sky130_fd_sc_hd__o2bb2ai (work@sky130_fd_sc_hd__o2bb2ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o2bb2ai.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o2bb2ai (work@sky130_fd_sc_hd__o2bb2ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o2bb2ai.functional.v, line:35:1, endln:61:10 |vpiName:nand1_out_Y |vpiFullName:work@sky130_fd_sc_hd__o2bb2ai.nand1_out_Y |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o2bb2ai.Y), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__o2bb2ai (work@sky130_fd_sc_hd__o2bb2ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o2bb2ai.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o2bb2ai (work@sky130_fd_sc_hd__o2bb2ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o2bb2ai.functional.v, line:35:1, endln:61:10 |vpiName:Y |vpiFullName:work@sky130_fd_sc_hd__o2bb2ai.Y |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o2bb2ai.A1_N), line:37:5, endln:37:9 |vpiParent: - \_module: work@sky130_fd_sc_hd__o2bb2ai (work@sky130_fd_sc_hd__o2bb2ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o2bb2ai.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o2bb2ai (work@sky130_fd_sc_hd__o2bb2ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o2bb2ai.functional.v, line:35:1, endln:61:10 |vpiName:A1_N |vpiFullName:work@sky130_fd_sc_hd__o2bb2ai.A1_N |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o2bb2ai.A2_N), line:38:5, endln:38:9 |vpiParent: - \_module: work@sky130_fd_sc_hd__o2bb2ai (work@sky130_fd_sc_hd__o2bb2ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o2bb2ai.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o2bb2ai (work@sky130_fd_sc_hd__o2bb2ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o2bb2ai.functional.v, line:35:1, endln:61:10 |vpiName:A2_N |vpiFullName:work@sky130_fd_sc_hd__o2bb2ai.A2_N |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o2bb2ai.B1), line:39:5, endln:39:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o2bb2ai (work@sky130_fd_sc_hd__o2bb2ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o2bb2ai.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o2bb2ai (work@sky130_fd_sc_hd__o2bb2ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o2bb2ai.functional.v, line:35:1, endln:61:10 |vpiName:B1 |vpiFullName:work@sky130_fd_sc_hd__o2bb2ai.B1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o2bb2ai.B2), line:40:5, endln:40:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o2bb2ai (work@sky130_fd_sc_hd__o2bb2ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o2bb2ai.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o2bb2ai (work@sky130_fd_sc_hd__o2bb2ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o2bb2ai.functional.v, line:35:1, endln:61:10 |vpiName:B2 |vpiFullName:work@sky130_fd_sc_hd__o2bb2ai.B2 |vpiPort: \_port: (Y), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__o2bb2ai (work@sky130_fd_sc_hd__o2bb2ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o2bb2ai.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o2bb2ai (work@sky130_fd_sc_hd__o2bb2ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o2bb2ai.functional.v, line:35:1, endln:61:10 |vpiName:Y |vpiDirection:2 |vpiLowConn: @@ -53885,7 +53885,7 @@ design: (work@sky130_fd_sc_hd__o2bb2ai) |vpiPort: \_port: (A1_N), line:37:5, endln:37:9 |vpiParent: - \_module: work@sky130_fd_sc_hd__o2bb2ai (work@sky130_fd_sc_hd__o2bb2ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o2bb2ai.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o2bb2ai (work@sky130_fd_sc_hd__o2bb2ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o2bb2ai.functional.v, line:35:1, endln:61:10 |vpiName:A1_N |vpiDirection:1 |vpiLowConn: @@ -53897,7 +53897,7 @@ design: (work@sky130_fd_sc_hd__o2bb2ai) |vpiPort: \_port: (A2_N), line:38:5, endln:38:9 |vpiParent: - \_module: work@sky130_fd_sc_hd__o2bb2ai (work@sky130_fd_sc_hd__o2bb2ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o2bb2ai.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o2bb2ai (work@sky130_fd_sc_hd__o2bb2ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o2bb2ai.functional.v, line:35:1, endln:61:10 |vpiName:A2_N |vpiDirection:1 |vpiLowConn: @@ -53909,7 +53909,7 @@ design: (work@sky130_fd_sc_hd__o2bb2ai) |vpiPort: \_port: (B1), line:39:5, endln:39:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o2bb2ai (work@sky130_fd_sc_hd__o2bb2ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o2bb2ai.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o2bb2ai (work@sky130_fd_sc_hd__o2bb2ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o2bb2ai.functional.v, line:35:1, endln:61:10 |vpiName:B1 |vpiDirection:1 |vpiLowConn: @@ -53921,7 +53921,7 @@ design: (work@sky130_fd_sc_hd__o2bb2ai) |vpiPort: \_port: (B2), line:40:5, endln:40:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o2bb2ai (work@sky130_fd_sc_hd__o2bb2ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o2bb2ai.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o2bb2ai (work@sky130_fd_sc_hd__o2bb2ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o2bb2ai.functional.v, line:35:1, endln:61:10 |vpiName:B2 |vpiDirection:1 |vpiLowConn: @@ -53931,14 +53931,14 @@ design: (work@sky130_fd_sc_hd__o2bb2ai) |vpiTypedef: \_logic_typespec: , line:48:12, endln:48:12 |uhdmtopModules: -\_module: work@sky130_fd_sc_hd__o2bb2ai (work@sky130_fd_sc_hd__o2bb2ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o2bb2ai.functional.v, line:35:1, endln:61:10 +\_module_inst: work@sky130_fd_sc_hd__o2bb2ai (work@sky130_fd_sc_hd__o2bb2ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o2bb2ai.functional.v, line:35:1, endln:61:10 |vpiName:work@sky130_fd_sc_hd__o2bb2ai |vpiDefName:work@sky130_fd_sc_hd__o2bb2ai |vpiTop:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o2bb2ai.nand0_out), line:51:10, endln:51:19 |vpiParent: - \_module: work@sky130_fd_sc_hd__o2bb2ai (work@sky130_fd_sc_hd__o2bb2ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o2bb2ai.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o2bb2ai (work@sky130_fd_sc_hd__o2bb2ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o2bb2ai.functional.v, line:35:1, endln:61:10 |vpiTypespec: \_logic_typespec: , line:51:5, endln:51:9 |vpiName:nand0_out @@ -53947,7 +53947,7 @@ design: (work@sky130_fd_sc_hd__o2bb2ai) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o2bb2ai.or0_out), line:52:10, endln:52:17 |vpiParent: - \_module: work@sky130_fd_sc_hd__o2bb2ai (work@sky130_fd_sc_hd__o2bb2ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o2bb2ai.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o2bb2ai (work@sky130_fd_sc_hd__o2bb2ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o2bb2ai.functional.v, line:35:1, endln:61:10 |vpiTypespec: \_logic_typespec: , line:52:5, endln:52:9 |vpiName:or0_out @@ -53956,7 +53956,7 @@ design: (work@sky130_fd_sc_hd__o2bb2ai) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o2bb2ai.nand1_out_Y), line:53:10, endln:53:21 |vpiParent: - \_module: work@sky130_fd_sc_hd__o2bb2ai (work@sky130_fd_sc_hd__o2bb2ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o2bb2ai.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o2bb2ai (work@sky130_fd_sc_hd__o2bb2ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o2bb2ai.functional.v, line:35:1, endln:61:10 |vpiTypespec: \_logic_typespec: , line:53:5, endln:53:9 |vpiName:nand1_out_Y @@ -53965,7 +53965,7 @@ design: (work@sky130_fd_sc_hd__o2bb2ai) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o2bb2ai.Y), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__o2bb2ai (work@sky130_fd_sc_hd__o2bb2ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o2bb2ai.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o2bb2ai (work@sky130_fd_sc_hd__o2bb2ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o2bb2ai.functional.v, line:35:1, endln:61:10 |vpiTypespec: \_logic_typespec: , line:44:12, endln:44:12 |vpiName:Y @@ -53973,7 +53973,7 @@ design: (work@sky130_fd_sc_hd__o2bb2ai) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o2bb2ai.A1_N), line:37:5, endln:37:9 |vpiParent: - \_module: work@sky130_fd_sc_hd__o2bb2ai (work@sky130_fd_sc_hd__o2bb2ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o2bb2ai.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o2bb2ai (work@sky130_fd_sc_hd__o2bb2ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o2bb2ai.functional.v, line:35:1, endln:61:10 |vpiTypespec: \_logic_typespec: , line:45:12, endln:45:12 |vpiName:A1_N @@ -53981,7 +53981,7 @@ design: (work@sky130_fd_sc_hd__o2bb2ai) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o2bb2ai.A2_N), line:38:5, endln:38:9 |vpiParent: - \_module: work@sky130_fd_sc_hd__o2bb2ai (work@sky130_fd_sc_hd__o2bb2ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o2bb2ai.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o2bb2ai (work@sky130_fd_sc_hd__o2bb2ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o2bb2ai.functional.v, line:35:1, endln:61:10 |vpiTypespec: \_logic_typespec: , line:46:12, endln:46:12 |vpiName:A2_N @@ -53989,7 +53989,7 @@ design: (work@sky130_fd_sc_hd__o2bb2ai) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o2bb2ai.B1), line:39:5, endln:39:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o2bb2ai (work@sky130_fd_sc_hd__o2bb2ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o2bb2ai.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o2bb2ai (work@sky130_fd_sc_hd__o2bb2ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o2bb2ai.functional.v, line:35:1, endln:61:10 |vpiTypespec: \_logic_typespec: , line:47:12, endln:47:12 |vpiName:B1 @@ -53997,7 +53997,7 @@ design: (work@sky130_fd_sc_hd__o2bb2ai) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o2bb2ai.B2), line:40:5, endln:40:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o2bb2ai (work@sky130_fd_sc_hd__o2bb2ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o2bb2ai.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o2bb2ai (work@sky130_fd_sc_hd__o2bb2ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o2bb2ai.functional.v, line:35:1, endln:61:10 |vpiTypespec: \_logic_typespec: , line:48:12, endln:48:12 |vpiName:B2 @@ -54006,7 +54006,7 @@ design: (work@sky130_fd_sc_hd__o2bb2ai) |vpiPort: \_port: (Y), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__o2bb2ai (work@sky130_fd_sc_hd__o2bb2ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o2bb2ai.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o2bb2ai (work@sky130_fd_sc_hd__o2bb2ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o2bb2ai.functional.v, line:35:1, endln:61:10 |vpiName:Y |vpiDirection:2 |vpiLowConn: @@ -54020,7 +54020,7 @@ design: (work@sky130_fd_sc_hd__o2bb2ai) |vpiPort: \_port: (A1_N), line:37:5, endln:37:9 |vpiParent: - \_module: work@sky130_fd_sc_hd__o2bb2ai (work@sky130_fd_sc_hd__o2bb2ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o2bb2ai.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o2bb2ai (work@sky130_fd_sc_hd__o2bb2ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o2bb2ai.functional.v, line:35:1, endln:61:10 |vpiName:A1_N |vpiDirection:1 |vpiLowConn: @@ -54034,7 +54034,7 @@ design: (work@sky130_fd_sc_hd__o2bb2ai) |vpiPort: \_port: (A2_N), line:38:5, endln:38:9 |vpiParent: - \_module: work@sky130_fd_sc_hd__o2bb2ai (work@sky130_fd_sc_hd__o2bb2ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o2bb2ai.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o2bb2ai (work@sky130_fd_sc_hd__o2bb2ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o2bb2ai.functional.v, line:35:1, endln:61:10 |vpiName:A2_N |vpiDirection:1 |vpiLowConn: @@ -54048,7 +54048,7 @@ design: (work@sky130_fd_sc_hd__o2bb2ai) |vpiPort: \_port: (B1), line:39:5, endln:39:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o2bb2ai (work@sky130_fd_sc_hd__o2bb2ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o2bb2ai.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o2bb2ai (work@sky130_fd_sc_hd__o2bb2ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o2bb2ai.functional.v, line:35:1, endln:61:10 |vpiName:B1 |vpiDirection:1 |vpiLowConn: @@ -54062,7 +54062,7 @@ design: (work@sky130_fd_sc_hd__o2bb2ai) |vpiPort: \_port: (B2), line:40:5, endln:40:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o2bb2ai (work@sky130_fd_sc_hd__o2bb2ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o2bb2ai.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o2bb2ai (work@sky130_fd_sc_hd__o2bb2ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o2bb2ai.functional.v, line:35:1, endln:61:10 |vpiName:B2 |vpiDirection:1 |vpiLowConn: @@ -54076,7 +54076,7 @@ design: (work@sky130_fd_sc_hd__o2bb2ai) |vpiPrimitive: \_gate: work@nand (work@sky130_fd_sc_hd__o2bb2ai.nand0), line:56:10, endln:56:49 |vpiParent: - \_module: work@sky130_fd_sc_hd__o2bb2ai (work@sky130_fd_sc_hd__o2bb2ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o2bb2ai.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o2bb2ai (work@sky130_fd_sc_hd__o2bb2ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o2bb2ai.functional.v, line:35:1, endln:61:10 |vpiDefName:work@nand |vpiName:nand0 |vpiFullName:work@sky130_fd_sc_hd__o2bb2ai.nand0 @@ -54125,7 +54125,7 @@ design: (work@sky130_fd_sc_hd__o2bb2ai) |vpiPrimitive: \_gate: work@or (work@sky130_fd_sc_hd__o2bb2ai.or0), line:57:10, endln:57:49 |vpiParent: - \_module: work@sky130_fd_sc_hd__o2bb2ai (work@sky130_fd_sc_hd__o2bb2ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o2bb2ai.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o2bb2ai (work@sky130_fd_sc_hd__o2bb2ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o2bb2ai.functional.v, line:35:1, endln:61:10 |vpiDefName:work@or |vpiName:or0 |vpiFullName:work@sky130_fd_sc_hd__o2bb2ai.or0 @@ -54174,7 +54174,7 @@ design: (work@sky130_fd_sc_hd__o2bb2ai) |vpiPrimitive: \_gate: work@nand (work@sky130_fd_sc_hd__o2bb2ai.nand1), line:58:10, endln:58:49 |vpiParent: - \_module: work@sky130_fd_sc_hd__o2bb2ai (work@sky130_fd_sc_hd__o2bb2ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o2bb2ai.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o2bb2ai (work@sky130_fd_sc_hd__o2bb2ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o2bb2ai.functional.v, line:35:1, endln:61:10 |vpiDefName:work@nand |vpiName:nand1 |vpiFullName:work@sky130_fd_sc_hd__o2bb2ai.nand1 @@ -54223,7 +54223,7 @@ design: (work@sky130_fd_sc_hd__o2bb2ai) |vpiPrimitive: \_gate: work@buf (work@sky130_fd_sc_hd__o2bb2ai.buf0), line:59:10, endln:59:49 |vpiParent: - \_module: work@sky130_fd_sc_hd__o2bb2ai (work@sky130_fd_sc_hd__o2bb2ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o2bb2ai.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o2bb2ai (work@sky130_fd_sc_hd__o2bb2ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o2bb2ai.functional.v, line:35:1, endln:61:10 |vpiDefName:work@buf |vpiName:buf0 |vpiFullName:work@sky130_fd_sc_hd__o2bb2ai.buf0 @@ -54266,7 +54266,7 @@ Processing: -cd cells/cells -DUNIT_DELAY -writepp -parse -nocache -nobuiltin -no design: (work@sky130_fd_sc_hd__nor2) |vpiName:work@sky130_fd_sc_hd__nor2 |uhdmallModules: -\_module: work@sky130_fd_sc_hd__nor2 (work@sky130_fd_sc_hd__nor2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor2.functional.v, line:33:1, endln:51:10 +\_module_inst: work@sky130_fd_sc_hd__nor2 (work@sky130_fd_sc_hd__nor2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor2.functional.v, line:33:1, endln:51:10 |vpiParent: \_design: (work@sky130_fd_sc_hd__nor2) |vpiFullName:work@sky130_fd_sc_hd__nor2 @@ -54274,32 +54274,32 @@ design: (work@sky130_fd_sc_hd__nor2) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__nor2.nor0_out_Y), line:45:10, endln:45:20 |vpiParent: - \_module: work@sky130_fd_sc_hd__nor2 (work@sky130_fd_sc_hd__nor2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor2.functional.v, line:33:1, endln:51:10 + \_module_inst: work@sky130_fd_sc_hd__nor2 (work@sky130_fd_sc_hd__nor2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor2.functional.v, line:33:1, endln:51:10 |vpiName:nor0_out_Y |vpiFullName:work@sky130_fd_sc_hd__nor2.nor0_out_Y |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__nor2.Y), line:34:5, endln:34:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__nor2 (work@sky130_fd_sc_hd__nor2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor2.functional.v, line:33:1, endln:51:10 + \_module_inst: work@sky130_fd_sc_hd__nor2 (work@sky130_fd_sc_hd__nor2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor2.functional.v, line:33:1, endln:51:10 |vpiName:Y |vpiFullName:work@sky130_fd_sc_hd__nor2.Y |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__nor2.A), line:35:5, endln:35:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__nor2 (work@sky130_fd_sc_hd__nor2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor2.functional.v, line:33:1, endln:51:10 + \_module_inst: work@sky130_fd_sc_hd__nor2 (work@sky130_fd_sc_hd__nor2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor2.functional.v, line:33:1, endln:51:10 |vpiName:A |vpiFullName:work@sky130_fd_sc_hd__nor2.A |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__nor2.B), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__nor2 (work@sky130_fd_sc_hd__nor2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor2.functional.v, line:33:1, endln:51:10 + \_module_inst: work@sky130_fd_sc_hd__nor2 (work@sky130_fd_sc_hd__nor2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor2.functional.v, line:33:1, endln:51:10 |vpiName:B |vpiFullName:work@sky130_fd_sc_hd__nor2.B |vpiPort: \_port: (Y), line:34:5, endln:34:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__nor2 (work@sky130_fd_sc_hd__nor2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor2.functional.v, line:33:1, endln:51:10 + \_module_inst: work@sky130_fd_sc_hd__nor2 (work@sky130_fd_sc_hd__nor2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor2.functional.v, line:33:1, endln:51:10 |vpiName:Y |vpiDirection:2 |vpiLowConn: @@ -54311,7 +54311,7 @@ design: (work@sky130_fd_sc_hd__nor2) |vpiPort: \_port: (A), line:35:5, endln:35:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__nor2 (work@sky130_fd_sc_hd__nor2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor2.functional.v, line:33:1, endln:51:10 + \_module_inst: work@sky130_fd_sc_hd__nor2 (work@sky130_fd_sc_hd__nor2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor2.functional.v, line:33:1, endln:51:10 |vpiName:A |vpiDirection:1 |vpiLowConn: @@ -54323,7 +54323,7 @@ design: (work@sky130_fd_sc_hd__nor2) |vpiPort: \_port: (B), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__nor2 (work@sky130_fd_sc_hd__nor2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor2.functional.v, line:33:1, endln:51:10 + \_module_inst: work@sky130_fd_sc_hd__nor2 (work@sky130_fd_sc_hd__nor2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor2.functional.v, line:33:1, endln:51:10 |vpiName:B |vpiDirection:1 |vpiLowConn: @@ -54333,14 +54333,14 @@ design: (work@sky130_fd_sc_hd__nor2) |vpiTypedef: \_logic_typespec: , line:42:12, endln:42:12 |uhdmtopModules: -\_module: work@sky130_fd_sc_hd__nor2 (work@sky130_fd_sc_hd__nor2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor2.functional.v, line:33:1, endln:51:10 +\_module_inst: work@sky130_fd_sc_hd__nor2 (work@sky130_fd_sc_hd__nor2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor2.functional.v, line:33:1, endln:51:10 |vpiName:work@sky130_fd_sc_hd__nor2 |vpiDefName:work@sky130_fd_sc_hd__nor2 |vpiTop:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__nor2.nor0_out_Y), line:45:10, endln:45:20 |vpiParent: - \_module: work@sky130_fd_sc_hd__nor2 (work@sky130_fd_sc_hd__nor2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor2.functional.v, line:33:1, endln:51:10 + \_module_inst: work@sky130_fd_sc_hd__nor2 (work@sky130_fd_sc_hd__nor2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor2.functional.v, line:33:1, endln:51:10 |vpiTypespec: \_logic_typespec: , line:45:5, endln:45:9 |vpiName:nor0_out_Y @@ -54349,7 +54349,7 @@ design: (work@sky130_fd_sc_hd__nor2) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__nor2.Y), line:34:5, endln:34:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__nor2 (work@sky130_fd_sc_hd__nor2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor2.functional.v, line:33:1, endln:51:10 + \_module_inst: work@sky130_fd_sc_hd__nor2 (work@sky130_fd_sc_hd__nor2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor2.functional.v, line:33:1, endln:51:10 |vpiTypespec: \_logic_typespec: , line:40:12, endln:40:12 |vpiName:Y @@ -54357,7 +54357,7 @@ design: (work@sky130_fd_sc_hd__nor2) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__nor2.A), line:35:5, endln:35:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__nor2 (work@sky130_fd_sc_hd__nor2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor2.functional.v, line:33:1, endln:51:10 + \_module_inst: work@sky130_fd_sc_hd__nor2 (work@sky130_fd_sc_hd__nor2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor2.functional.v, line:33:1, endln:51:10 |vpiTypespec: \_logic_typespec: , line:41:12, endln:41:12 |vpiName:A @@ -54365,7 +54365,7 @@ design: (work@sky130_fd_sc_hd__nor2) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__nor2.B), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__nor2 (work@sky130_fd_sc_hd__nor2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor2.functional.v, line:33:1, endln:51:10 + \_module_inst: work@sky130_fd_sc_hd__nor2 (work@sky130_fd_sc_hd__nor2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor2.functional.v, line:33:1, endln:51:10 |vpiTypespec: \_logic_typespec: , line:42:12, endln:42:12 |vpiName:B @@ -54374,7 +54374,7 @@ design: (work@sky130_fd_sc_hd__nor2) |vpiPort: \_port: (Y), line:34:5, endln:34:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__nor2 (work@sky130_fd_sc_hd__nor2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor2.functional.v, line:33:1, endln:51:10 + \_module_inst: work@sky130_fd_sc_hd__nor2 (work@sky130_fd_sc_hd__nor2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor2.functional.v, line:33:1, endln:51:10 |vpiName:Y |vpiDirection:2 |vpiLowConn: @@ -54388,7 +54388,7 @@ design: (work@sky130_fd_sc_hd__nor2) |vpiPort: \_port: (A), line:35:5, endln:35:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__nor2 (work@sky130_fd_sc_hd__nor2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor2.functional.v, line:33:1, endln:51:10 + \_module_inst: work@sky130_fd_sc_hd__nor2 (work@sky130_fd_sc_hd__nor2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor2.functional.v, line:33:1, endln:51:10 |vpiName:A |vpiDirection:1 |vpiLowConn: @@ -54402,7 +54402,7 @@ design: (work@sky130_fd_sc_hd__nor2) |vpiPort: \_port: (B), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__nor2 (work@sky130_fd_sc_hd__nor2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor2.functional.v, line:33:1, endln:51:10 + \_module_inst: work@sky130_fd_sc_hd__nor2 (work@sky130_fd_sc_hd__nor2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor2.functional.v, line:33:1, endln:51:10 |vpiName:B |vpiDirection:1 |vpiLowConn: @@ -54416,7 +54416,7 @@ design: (work@sky130_fd_sc_hd__nor2) |vpiPrimitive: \_gate: work@nor (work@sky130_fd_sc_hd__nor2.nor0), line:48:9, endln:48:43 |vpiParent: - \_module: work@sky130_fd_sc_hd__nor2 (work@sky130_fd_sc_hd__nor2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor2.functional.v, line:33:1, endln:51:10 + \_module_inst: work@sky130_fd_sc_hd__nor2 (work@sky130_fd_sc_hd__nor2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor2.functional.v, line:33:1, endln:51:10 |vpiDefName:work@nor |vpiName:nor0 |vpiFullName:work@sky130_fd_sc_hd__nor2.nor0 @@ -54465,7 +54465,7 @@ design: (work@sky130_fd_sc_hd__nor2) |vpiPrimitive: \_gate: work@buf (work@sky130_fd_sc_hd__nor2.buf0), line:49:9, endln:49:43 |vpiParent: - \_module: work@sky130_fd_sc_hd__nor2 (work@sky130_fd_sc_hd__nor2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor2.functional.v, line:33:1, endln:51:10 + \_module_inst: work@sky130_fd_sc_hd__nor2 (work@sky130_fd_sc_hd__nor2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor2.functional.v, line:33:1, endln:51:10 |vpiDefName:work@buf |vpiName:buf0 |vpiFullName:work@sky130_fd_sc_hd__nor2.buf0 @@ -54582,7 +54582,7 @@ design: (work@sky130_fd_sc_hd__dlxbp) |vpiSize:2 |STRING:1 x : 1 : 1 |uhdmallModules: -\_module: work@sky130_fd_sc_hd__dlxbp (work@sky130_fd_sc_hd__dlxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlxbp.functional.v, line:36:1, endln:57:10 +\_module_inst: work@sky130_fd_sc_hd__dlxbp (work@sky130_fd_sc_hd__dlxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlxbp.functional.v, line:36:1, endln:57:10 |vpiParent: \_design: (work@sky130_fd_sc_hd__dlxbp) |vpiFullName:work@sky130_fd_sc_hd__dlxbp @@ -54590,38 +54590,38 @@ design: (work@sky130_fd_sc_hd__dlxbp) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__dlxbp.buf_Q), line:50:10, endln:50:15 |vpiParent: - \_module: work@sky130_fd_sc_hd__dlxbp (work@sky130_fd_sc_hd__dlxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlxbp.functional.v, line:36:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__dlxbp (work@sky130_fd_sc_hd__dlxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlxbp.functional.v, line:36:1, endln:57:10 |vpiName:buf_Q |vpiFullName:work@sky130_fd_sc_hd__dlxbp.buf_Q |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__dlxbp.Q), line:37:5, endln:37:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__dlxbp (work@sky130_fd_sc_hd__dlxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlxbp.functional.v, line:36:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__dlxbp (work@sky130_fd_sc_hd__dlxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlxbp.functional.v, line:36:1, endln:57:10 |vpiName:Q |vpiFullName:work@sky130_fd_sc_hd__dlxbp.Q |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__dlxbp.Q_N), line:38:5, endln:38:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__dlxbp (work@sky130_fd_sc_hd__dlxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlxbp.functional.v, line:36:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__dlxbp (work@sky130_fd_sc_hd__dlxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlxbp.functional.v, line:36:1, endln:57:10 |vpiName:Q_N |vpiFullName:work@sky130_fd_sc_hd__dlxbp.Q_N |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__dlxbp.D), line:39:5, endln:39:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__dlxbp (work@sky130_fd_sc_hd__dlxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlxbp.functional.v, line:36:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__dlxbp (work@sky130_fd_sc_hd__dlxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlxbp.functional.v, line:36:1, endln:57:10 |vpiName:D |vpiFullName:work@sky130_fd_sc_hd__dlxbp.D |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__dlxbp.GATE), line:40:5, endln:40:9 |vpiParent: - \_module: work@sky130_fd_sc_hd__dlxbp (work@sky130_fd_sc_hd__dlxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlxbp.functional.v, line:36:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__dlxbp (work@sky130_fd_sc_hd__dlxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlxbp.functional.v, line:36:1, endln:57:10 |vpiName:GATE |vpiFullName:work@sky130_fd_sc_hd__dlxbp.GATE |vpiPort: \_port: (Q), line:37:5, endln:37:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__dlxbp (work@sky130_fd_sc_hd__dlxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlxbp.functional.v, line:36:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__dlxbp (work@sky130_fd_sc_hd__dlxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlxbp.functional.v, line:36:1, endln:57:10 |vpiName:Q |vpiDirection:2 |vpiLowConn: @@ -54633,7 +54633,7 @@ design: (work@sky130_fd_sc_hd__dlxbp) |vpiPort: \_port: (Q_N), line:38:5, endln:38:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__dlxbp (work@sky130_fd_sc_hd__dlxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlxbp.functional.v, line:36:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__dlxbp (work@sky130_fd_sc_hd__dlxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlxbp.functional.v, line:36:1, endln:57:10 |vpiName:Q_N |vpiDirection:2 |vpiLowConn: @@ -54645,7 +54645,7 @@ design: (work@sky130_fd_sc_hd__dlxbp) |vpiPort: \_port: (D), line:39:5, endln:39:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__dlxbp (work@sky130_fd_sc_hd__dlxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlxbp.functional.v, line:36:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__dlxbp (work@sky130_fd_sc_hd__dlxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlxbp.functional.v, line:36:1, endln:57:10 |vpiName:D |vpiDirection:1 |vpiLowConn: @@ -54657,7 +54657,7 @@ design: (work@sky130_fd_sc_hd__dlxbp) |vpiPort: \_port: (GATE), line:40:5, endln:40:9 |vpiParent: - \_module: work@sky130_fd_sc_hd__dlxbp (work@sky130_fd_sc_hd__dlxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlxbp.functional.v, line:36:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__dlxbp (work@sky130_fd_sc_hd__dlxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlxbp.functional.v, line:36:1, endln:57:10 |vpiName:GATE |vpiDirection:1 |vpiLowConn: @@ -54667,14 +54667,14 @@ design: (work@sky130_fd_sc_hd__dlxbp) |vpiTypedef: \_logic_typespec: , line:47:12, endln:47:12 |uhdmtopModules: -\_module: work@sky130_fd_sc_hd__dlxbp (work@sky130_fd_sc_hd__dlxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlxbp.functional.v, line:36:1, endln:57:10 +\_module_inst: work@sky130_fd_sc_hd__dlxbp (work@sky130_fd_sc_hd__dlxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlxbp.functional.v, line:36:1, endln:57:10 |vpiName:work@sky130_fd_sc_hd__dlxbp |vpiDefName:work@sky130_fd_sc_hd__dlxbp |vpiTop:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__dlxbp.buf_Q), line:50:10, endln:50:15 |vpiParent: - \_module: work@sky130_fd_sc_hd__dlxbp (work@sky130_fd_sc_hd__dlxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlxbp.functional.v, line:36:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__dlxbp (work@sky130_fd_sc_hd__dlxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlxbp.functional.v, line:36:1, endln:57:10 |vpiTypespec: \_logic_typespec: , line:50:5, endln:50:9 |vpiName:buf_Q @@ -54683,7 +54683,7 @@ design: (work@sky130_fd_sc_hd__dlxbp) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__dlxbp.Q), line:37:5, endln:37:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__dlxbp (work@sky130_fd_sc_hd__dlxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlxbp.functional.v, line:36:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__dlxbp (work@sky130_fd_sc_hd__dlxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlxbp.functional.v, line:36:1, endln:57:10 |vpiTypespec: \_logic_typespec: , line:44:12, endln:44:12 |vpiName:Q @@ -54691,7 +54691,7 @@ design: (work@sky130_fd_sc_hd__dlxbp) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__dlxbp.Q_N), line:38:5, endln:38:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__dlxbp (work@sky130_fd_sc_hd__dlxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlxbp.functional.v, line:36:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__dlxbp (work@sky130_fd_sc_hd__dlxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlxbp.functional.v, line:36:1, endln:57:10 |vpiTypespec: \_logic_typespec: , line:45:12, endln:45:12 |vpiName:Q_N @@ -54699,7 +54699,7 @@ design: (work@sky130_fd_sc_hd__dlxbp) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__dlxbp.D), line:39:5, endln:39:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__dlxbp (work@sky130_fd_sc_hd__dlxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlxbp.functional.v, line:36:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__dlxbp (work@sky130_fd_sc_hd__dlxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlxbp.functional.v, line:36:1, endln:57:10 |vpiTypespec: \_logic_typespec: , line:46:12, endln:46:12 |vpiName:D @@ -54707,7 +54707,7 @@ design: (work@sky130_fd_sc_hd__dlxbp) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__dlxbp.GATE), line:40:5, endln:40:9 |vpiParent: - \_module: work@sky130_fd_sc_hd__dlxbp (work@sky130_fd_sc_hd__dlxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlxbp.functional.v, line:36:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__dlxbp (work@sky130_fd_sc_hd__dlxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlxbp.functional.v, line:36:1, endln:57:10 |vpiTypespec: \_logic_typespec: , line:47:12, endln:47:12 |vpiName:GATE @@ -54716,7 +54716,7 @@ design: (work@sky130_fd_sc_hd__dlxbp) |vpiPort: \_port: (Q), line:37:5, endln:37:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__dlxbp (work@sky130_fd_sc_hd__dlxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlxbp.functional.v, line:36:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__dlxbp (work@sky130_fd_sc_hd__dlxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlxbp.functional.v, line:36:1, endln:57:10 |vpiName:Q |vpiDirection:2 |vpiLowConn: @@ -54730,7 +54730,7 @@ design: (work@sky130_fd_sc_hd__dlxbp) |vpiPort: \_port: (Q_N), line:38:5, endln:38:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__dlxbp (work@sky130_fd_sc_hd__dlxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlxbp.functional.v, line:36:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__dlxbp (work@sky130_fd_sc_hd__dlxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlxbp.functional.v, line:36:1, endln:57:10 |vpiName:Q_N |vpiDirection:2 |vpiLowConn: @@ -54744,7 +54744,7 @@ design: (work@sky130_fd_sc_hd__dlxbp) |vpiPort: \_port: (D), line:39:5, endln:39:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__dlxbp (work@sky130_fd_sc_hd__dlxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlxbp.functional.v, line:36:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__dlxbp (work@sky130_fd_sc_hd__dlxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlxbp.functional.v, line:36:1, endln:57:10 |vpiName:D |vpiDirection:1 |vpiLowConn: @@ -54758,7 +54758,7 @@ design: (work@sky130_fd_sc_hd__dlxbp) |vpiPort: \_port: (GATE), line:40:5, endln:40:9 |vpiParent: - \_module: work@sky130_fd_sc_hd__dlxbp (work@sky130_fd_sc_hd__dlxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlxbp.functional.v, line:36:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__dlxbp (work@sky130_fd_sc_hd__dlxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlxbp.functional.v, line:36:1, endln:57:10 |vpiName:GATE |vpiDirection:1 |vpiLowConn: @@ -54772,7 +54772,7 @@ design: (work@sky130_fd_sc_hd__dlxbp) |vpiPrimitive: \_udp: work@sky130_fd_sc_hd__udp_dlatch$P (work@sky130_fd_sc_hd__dlxbp.dlatch0), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlxbp.functional.v, line:53:5, endln:53:70 |vpiParent: - \_module: work@sky130_fd_sc_hd__dlxbp (work@sky130_fd_sc_hd__dlxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlxbp.functional.v, line:36:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__dlxbp (work@sky130_fd_sc_hd__dlxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlxbp.functional.v, line:36:1, endln:57:10 |vpiDefName:work@sky130_fd_sc_hd__udp_dlatch$P |vpiName:dlatch0 |vpiFullName:work@sky130_fd_sc_hd__dlxbp.dlatch0 @@ -54781,7 +54781,7 @@ design: (work@sky130_fd_sc_hd__dlxbp) |vpiPrimitive: \_gate: work@buf (work@sky130_fd_sc_hd__dlxbp.buf0), line:54:47, endln:54:80 |vpiParent: - \_module: work@sky130_fd_sc_hd__dlxbp (work@sky130_fd_sc_hd__dlxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlxbp.functional.v, line:36:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__dlxbp (work@sky130_fd_sc_hd__dlxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlxbp.functional.v, line:36:1, endln:57:10 |vpiDefName:work@buf |vpiName:buf0 |vpiFullName:work@sky130_fd_sc_hd__dlxbp.buf0 @@ -54816,7 +54816,7 @@ design: (work@sky130_fd_sc_hd__dlxbp) |vpiPrimitive: \_gate: work@not (work@sky130_fd_sc_hd__dlxbp.not0), line:55:47, endln:55:80 |vpiParent: - \_module: work@sky130_fd_sc_hd__dlxbp (work@sky130_fd_sc_hd__dlxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlxbp.functional.v, line:36:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__dlxbp (work@sky130_fd_sc_hd__dlxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlxbp.functional.v, line:36:1, endln:57:10 |vpiDefName:work@not |vpiName:not0 |vpiFullName:work@sky130_fd_sc_hd__dlxbp.not0 @@ -54859,7 +54859,7 @@ Processing: -cd cells/cells -DUNIT_DELAY -writepp -parse -nocache -nobuiltin -no design: (work@sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap) |vpiName:work@sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap |uhdmallModules: -\_module: work@sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap (work@sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap.functional.v, line:35:1, endln:47:10 +\_module_inst: work@sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap (work@sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap.functional.v, line:35:1, endln:47:10 |vpiParent: \_design: (work@sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap) |vpiFullName:work@sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap @@ -54867,19 +54867,19 @@ design: (work@sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap.X), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap (work@sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap.functional.v, line:35:1, endln:47:10 + \_module_inst: work@sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap (work@sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap.functional.v, line:35:1, endln:47:10 |vpiName:X |vpiFullName:work@sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap.X |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap.A), line:37:5, endln:37:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap (work@sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap.functional.v, line:35:1, endln:47:10 + \_module_inst: work@sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap (work@sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap.functional.v, line:35:1, endln:47:10 |vpiName:A |vpiFullName:work@sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap.A |vpiPort: \_port: (X), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap (work@sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap.functional.v, line:35:1, endln:47:10 + \_module_inst: work@sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap (work@sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap.functional.v, line:35:1, endln:47:10 |vpiName:X |vpiDirection:2 |vpiLowConn: @@ -54891,7 +54891,7 @@ design: (work@sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap) |vpiPort: \_port: (A), line:37:5, endln:37:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap (work@sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap.functional.v, line:35:1, endln:47:10 + \_module_inst: work@sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap (work@sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap.functional.v, line:35:1, endln:47:10 |vpiName:A |vpiDirection:1 |vpiLowConn: @@ -54901,14 +54901,14 @@ design: (work@sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap) |vpiTypedef: \_logic_typespec: , line:42:12, endln:42:12 |uhdmtopModules: -\_module: work@sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap (work@sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap.functional.v, line:35:1, endln:47:10 +\_module_inst: work@sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap (work@sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap.functional.v, line:35:1, endln:47:10 |vpiName:work@sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap |vpiDefName:work@sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap |vpiTop:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap.X), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap (work@sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap.functional.v, line:35:1, endln:47:10 + \_module_inst: work@sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap (work@sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap.functional.v, line:35:1, endln:47:10 |vpiTypespec: \_logic_typespec: , line:41:12, endln:41:12 |vpiName:X @@ -54916,7 +54916,7 @@ design: (work@sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap.A), line:37:5, endln:37:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap (work@sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap.functional.v, line:35:1, endln:47:10 + \_module_inst: work@sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap (work@sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap.functional.v, line:35:1, endln:47:10 |vpiTypespec: \_logic_typespec: , line:42:12, endln:42:12 |vpiName:A @@ -54925,7 +54925,7 @@ design: (work@sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap) |vpiPort: \_port: (X), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap (work@sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap.functional.v, line:35:1, endln:47:10 + \_module_inst: work@sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap (work@sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap.functional.v, line:35:1, endln:47:10 |vpiName:X |vpiDirection:2 |vpiLowConn: @@ -54939,7 +54939,7 @@ design: (work@sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap) |vpiPort: \_port: (A), line:37:5, endln:37:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap (work@sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap.functional.v, line:35:1, endln:47:10 + \_module_inst: work@sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap (work@sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap.functional.v, line:35:1, endln:47:10 |vpiName:A |vpiDirection:1 |vpiLowConn: @@ -54953,7 +54953,7 @@ design: (work@sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap) |vpiPrimitive: \_gate: work@buf (work@sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap.buf0), line:45:9, endln:45:39 |vpiParent: - \_module: work@sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap (work@sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap.functional.v, line:35:1, endln:47:10 + \_module_inst: work@sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap (work@sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap.functional.v, line:35:1, endln:47:10 |vpiDefName:work@buf |vpiName:buf0 |vpiFullName:work@sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap.buf0 @@ -54996,7 +54996,7 @@ Processing: -cd cells/cells -DUNIT_DELAY -writepp -parse -nocache -nobuiltin -no design: (work@sky130_fd_sc_hd__or3b) |vpiName:work@sky130_fd_sc_hd__or3b |uhdmallModules: -\_module: work@sky130_fd_sc_hd__or3b (work@sky130_fd_sc_hd__or3b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or3b.functional.v, line:33:1, endln:55:10 +\_module_inst: work@sky130_fd_sc_hd__or3b (work@sky130_fd_sc_hd__or3b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or3b.functional.v, line:33:1, endln:55:10 |vpiParent: \_design: (work@sky130_fd_sc_hd__or3b) |vpiFullName:work@sky130_fd_sc_hd__or3b @@ -55004,45 +55004,45 @@ design: (work@sky130_fd_sc_hd__or3b) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__or3b.not0_out), line:47:10, endln:47:18 |vpiParent: - \_module: work@sky130_fd_sc_hd__or3b (work@sky130_fd_sc_hd__or3b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or3b.functional.v, line:33:1, endln:55:10 + \_module_inst: work@sky130_fd_sc_hd__or3b (work@sky130_fd_sc_hd__or3b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or3b.functional.v, line:33:1, endln:55:10 |vpiName:not0_out |vpiFullName:work@sky130_fd_sc_hd__or3b.not0_out |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__or3b.or0_out_X), line:48:10, endln:48:19 |vpiParent: - \_module: work@sky130_fd_sc_hd__or3b (work@sky130_fd_sc_hd__or3b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or3b.functional.v, line:33:1, endln:55:10 + \_module_inst: work@sky130_fd_sc_hd__or3b (work@sky130_fd_sc_hd__or3b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or3b.functional.v, line:33:1, endln:55:10 |vpiName:or0_out_X |vpiFullName:work@sky130_fd_sc_hd__or3b.or0_out_X |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__or3b.X), line:34:5, endln:34:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__or3b (work@sky130_fd_sc_hd__or3b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or3b.functional.v, line:33:1, endln:55:10 + \_module_inst: work@sky130_fd_sc_hd__or3b (work@sky130_fd_sc_hd__or3b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or3b.functional.v, line:33:1, endln:55:10 |vpiName:X |vpiFullName:work@sky130_fd_sc_hd__or3b.X |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__or3b.A), line:35:5, endln:35:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__or3b (work@sky130_fd_sc_hd__or3b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or3b.functional.v, line:33:1, endln:55:10 + \_module_inst: work@sky130_fd_sc_hd__or3b (work@sky130_fd_sc_hd__or3b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or3b.functional.v, line:33:1, endln:55:10 |vpiName:A |vpiFullName:work@sky130_fd_sc_hd__or3b.A |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__or3b.B), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__or3b (work@sky130_fd_sc_hd__or3b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or3b.functional.v, line:33:1, endln:55:10 + \_module_inst: work@sky130_fd_sc_hd__or3b (work@sky130_fd_sc_hd__or3b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or3b.functional.v, line:33:1, endln:55:10 |vpiName:B |vpiFullName:work@sky130_fd_sc_hd__or3b.B |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__or3b.C_N), line:37:5, endln:37:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__or3b (work@sky130_fd_sc_hd__or3b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or3b.functional.v, line:33:1, endln:55:10 + \_module_inst: work@sky130_fd_sc_hd__or3b (work@sky130_fd_sc_hd__or3b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or3b.functional.v, line:33:1, endln:55:10 |vpiName:C_N |vpiFullName:work@sky130_fd_sc_hd__or3b.C_N |vpiPort: \_port: (X), line:34:5, endln:34:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__or3b (work@sky130_fd_sc_hd__or3b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or3b.functional.v, line:33:1, endln:55:10 + \_module_inst: work@sky130_fd_sc_hd__or3b (work@sky130_fd_sc_hd__or3b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or3b.functional.v, line:33:1, endln:55:10 |vpiName:X |vpiDirection:2 |vpiLowConn: @@ -55054,7 +55054,7 @@ design: (work@sky130_fd_sc_hd__or3b) |vpiPort: \_port: (A), line:35:5, endln:35:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__or3b (work@sky130_fd_sc_hd__or3b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or3b.functional.v, line:33:1, endln:55:10 + \_module_inst: work@sky130_fd_sc_hd__or3b (work@sky130_fd_sc_hd__or3b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or3b.functional.v, line:33:1, endln:55:10 |vpiName:A |vpiDirection:1 |vpiLowConn: @@ -55066,7 +55066,7 @@ design: (work@sky130_fd_sc_hd__or3b) |vpiPort: \_port: (B), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__or3b (work@sky130_fd_sc_hd__or3b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or3b.functional.v, line:33:1, endln:55:10 + \_module_inst: work@sky130_fd_sc_hd__or3b (work@sky130_fd_sc_hd__or3b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or3b.functional.v, line:33:1, endln:55:10 |vpiName:B |vpiDirection:1 |vpiLowConn: @@ -55078,7 +55078,7 @@ design: (work@sky130_fd_sc_hd__or3b) |vpiPort: \_port: (C_N), line:37:5, endln:37:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__or3b (work@sky130_fd_sc_hd__or3b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or3b.functional.v, line:33:1, endln:55:10 + \_module_inst: work@sky130_fd_sc_hd__or3b (work@sky130_fd_sc_hd__or3b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or3b.functional.v, line:33:1, endln:55:10 |vpiName:C_N |vpiDirection:1 |vpiLowConn: @@ -55088,14 +55088,14 @@ design: (work@sky130_fd_sc_hd__or3b) |vpiTypedef: \_logic_typespec: , line:44:12, endln:44:12 |uhdmtopModules: -\_module: work@sky130_fd_sc_hd__or3b (work@sky130_fd_sc_hd__or3b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or3b.functional.v, line:33:1, endln:55:10 +\_module_inst: work@sky130_fd_sc_hd__or3b (work@sky130_fd_sc_hd__or3b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or3b.functional.v, line:33:1, endln:55:10 |vpiName:work@sky130_fd_sc_hd__or3b |vpiDefName:work@sky130_fd_sc_hd__or3b |vpiTop:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__or3b.not0_out), line:47:10, endln:47:18 |vpiParent: - \_module: work@sky130_fd_sc_hd__or3b (work@sky130_fd_sc_hd__or3b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or3b.functional.v, line:33:1, endln:55:10 + \_module_inst: work@sky130_fd_sc_hd__or3b (work@sky130_fd_sc_hd__or3b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or3b.functional.v, line:33:1, endln:55:10 |vpiTypespec: \_logic_typespec: , line:47:5, endln:47:9 |vpiName:not0_out @@ -55104,7 +55104,7 @@ design: (work@sky130_fd_sc_hd__or3b) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__or3b.or0_out_X), line:48:10, endln:48:19 |vpiParent: - \_module: work@sky130_fd_sc_hd__or3b (work@sky130_fd_sc_hd__or3b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or3b.functional.v, line:33:1, endln:55:10 + \_module_inst: work@sky130_fd_sc_hd__or3b (work@sky130_fd_sc_hd__or3b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or3b.functional.v, line:33:1, endln:55:10 |vpiTypespec: \_logic_typespec: , line:48:5, endln:48:9 |vpiName:or0_out_X @@ -55113,7 +55113,7 @@ design: (work@sky130_fd_sc_hd__or3b) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__or3b.X), line:34:5, endln:34:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__or3b (work@sky130_fd_sc_hd__or3b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or3b.functional.v, line:33:1, endln:55:10 + \_module_inst: work@sky130_fd_sc_hd__or3b (work@sky130_fd_sc_hd__or3b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or3b.functional.v, line:33:1, endln:55:10 |vpiTypespec: \_logic_typespec: , line:41:12, endln:41:12 |vpiName:X @@ -55121,7 +55121,7 @@ design: (work@sky130_fd_sc_hd__or3b) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__or3b.A), line:35:5, endln:35:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__or3b (work@sky130_fd_sc_hd__or3b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or3b.functional.v, line:33:1, endln:55:10 + \_module_inst: work@sky130_fd_sc_hd__or3b (work@sky130_fd_sc_hd__or3b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or3b.functional.v, line:33:1, endln:55:10 |vpiTypespec: \_logic_typespec: , line:42:12, endln:42:12 |vpiName:A @@ -55129,7 +55129,7 @@ design: (work@sky130_fd_sc_hd__or3b) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__or3b.B), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__or3b (work@sky130_fd_sc_hd__or3b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or3b.functional.v, line:33:1, endln:55:10 + \_module_inst: work@sky130_fd_sc_hd__or3b (work@sky130_fd_sc_hd__or3b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or3b.functional.v, line:33:1, endln:55:10 |vpiTypespec: \_logic_typespec: , line:43:12, endln:43:12 |vpiName:B @@ -55137,7 +55137,7 @@ design: (work@sky130_fd_sc_hd__or3b) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__or3b.C_N), line:37:5, endln:37:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__or3b (work@sky130_fd_sc_hd__or3b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or3b.functional.v, line:33:1, endln:55:10 + \_module_inst: work@sky130_fd_sc_hd__or3b (work@sky130_fd_sc_hd__or3b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or3b.functional.v, line:33:1, endln:55:10 |vpiTypespec: \_logic_typespec: , line:44:12, endln:44:12 |vpiName:C_N @@ -55146,7 +55146,7 @@ design: (work@sky130_fd_sc_hd__or3b) |vpiPort: \_port: (X), line:34:5, endln:34:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__or3b (work@sky130_fd_sc_hd__or3b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or3b.functional.v, line:33:1, endln:55:10 + \_module_inst: work@sky130_fd_sc_hd__or3b (work@sky130_fd_sc_hd__or3b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or3b.functional.v, line:33:1, endln:55:10 |vpiName:X |vpiDirection:2 |vpiLowConn: @@ -55160,7 +55160,7 @@ design: (work@sky130_fd_sc_hd__or3b) |vpiPort: \_port: (A), line:35:5, endln:35:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__or3b (work@sky130_fd_sc_hd__or3b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or3b.functional.v, line:33:1, endln:55:10 + \_module_inst: work@sky130_fd_sc_hd__or3b (work@sky130_fd_sc_hd__or3b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or3b.functional.v, line:33:1, endln:55:10 |vpiName:A |vpiDirection:1 |vpiLowConn: @@ -55174,7 +55174,7 @@ design: (work@sky130_fd_sc_hd__or3b) |vpiPort: \_port: (B), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__or3b (work@sky130_fd_sc_hd__or3b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or3b.functional.v, line:33:1, endln:55:10 + \_module_inst: work@sky130_fd_sc_hd__or3b (work@sky130_fd_sc_hd__or3b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or3b.functional.v, line:33:1, endln:55:10 |vpiName:B |vpiDirection:1 |vpiLowConn: @@ -55188,7 +55188,7 @@ design: (work@sky130_fd_sc_hd__or3b) |vpiPort: \_port: (C_N), line:37:5, endln:37:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__or3b (work@sky130_fd_sc_hd__or3b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or3b.functional.v, line:33:1, endln:55:10 + \_module_inst: work@sky130_fd_sc_hd__or3b (work@sky130_fd_sc_hd__or3b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or3b.functional.v, line:33:1, endln:55:10 |vpiName:C_N |vpiDirection:1 |vpiLowConn: @@ -55202,7 +55202,7 @@ design: (work@sky130_fd_sc_hd__or3b) |vpiPrimitive: \_gate: work@not (work@sky130_fd_sc_hd__or3b.not0), line:51:9, endln:51:42 |vpiParent: - \_module: work@sky130_fd_sc_hd__or3b (work@sky130_fd_sc_hd__or3b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or3b.functional.v, line:33:1, endln:55:10 + \_module_inst: work@sky130_fd_sc_hd__or3b (work@sky130_fd_sc_hd__or3b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or3b.functional.v, line:33:1, endln:55:10 |vpiDefName:work@not |vpiName:not0 |vpiFullName:work@sky130_fd_sc_hd__or3b.not0 @@ -55237,7 +55237,7 @@ design: (work@sky130_fd_sc_hd__or3b) |vpiPrimitive: \_gate: work@or (work@sky130_fd_sc_hd__or3b.or0), line:52:9, endln:52:42 |vpiParent: - \_module: work@sky130_fd_sc_hd__or3b (work@sky130_fd_sc_hd__or3b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or3b.functional.v, line:33:1, endln:55:10 + \_module_inst: work@sky130_fd_sc_hd__or3b (work@sky130_fd_sc_hd__or3b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or3b.functional.v, line:33:1, endln:55:10 |vpiDefName:work@or |vpiName:or0 |vpiFullName:work@sky130_fd_sc_hd__or3b.or0 @@ -55300,7 +55300,7 @@ design: (work@sky130_fd_sc_hd__or3b) |vpiPrimitive: \_gate: work@buf (work@sky130_fd_sc_hd__or3b.buf0), line:53:9, endln:53:42 |vpiParent: - \_module: work@sky130_fd_sc_hd__or3b (work@sky130_fd_sc_hd__or3b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or3b.functional.v, line:33:1, endln:55:10 + \_module_inst: work@sky130_fd_sc_hd__or3b (work@sky130_fd_sc_hd__or3b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or3b.functional.v, line:33:1, endln:55:10 |vpiDefName:work@buf |vpiName:buf0 |vpiFullName:work@sky130_fd_sc_hd__or3b.buf0 @@ -55343,7 +55343,7 @@ Processing: -cd cells/cells -DUNIT_DELAY -writepp -parse -nocache -nobuiltin -no design: (work@sky130_fd_sc_hd__xnor2) |vpiName:work@sky130_fd_sc_hd__xnor2 |uhdmallModules: -\_module: work@sky130_fd_sc_hd__xnor2 (work@sky130_fd_sc_hd__xnor2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__xnor2.functional.v, line:35:1, endln:53:10 +\_module_inst: work@sky130_fd_sc_hd__xnor2 (work@sky130_fd_sc_hd__xnor2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__xnor2.functional.v, line:35:1, endln:53:10 |vpiParent: \_design: (work@sky130_fd_sc_hd__xnor2) |vpiFullName:work@sky130_fd_sc_hd__xnor2 @@ -55351,32 +55351,32 @@ design: (work@sky130_fd_sc_hd__xnor2) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__xnor2.xnor0_out_Y), line:47:10, endln:47:21 |vpiParent: - \_module: work@sky130_fd_sc_hd__xnor2 (work@sky130_fd_sc_hd__xnor2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__xnor2.functional.v, line:35:1, endln:53:10 + \_module_inst: work@sky130_fd_sc_hd__xnor2 (work@sky130_fd_sc_hd__xnor2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__xnor2.functional.v, line:35:1, endln:53:10 |vpiName:xnor0_out_Y |vpiFullName:work@sky130_fd_sc_hd__xnor2.xnor0_out_Y |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__xnor2.Y), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__xnor2 (work@sky130_fd_sc_hd__xnor2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__xnor2.functional.v, line:35:1, endln:53:10 + \_module_inst: work@sky130_fd_sc_hd__xnor2 (work@sky130_fd_sc_hd__xnor2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__xnor2.functional.v, line:35:1, endln:53:10 |vpiName:Y |vpiFullName:work@sky130_fd_sc_hd__xnor2.Y |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__xnor2.A), line:37:5, endln:37:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__xnor2 (work@sky130_fd_sc_hd__xnor2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__xnor2.functional.v, line:35:1, endln:53:10 + \_module_inst: work@sky130_fd_sc_hd__xnor2 (work@sky130_fd_sc_hd__xnor2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__xnor2.functional.v, line:35:1, endln:53:10 |vpiName:A |vpiFullName:work@sky130_fd_sc_hd__xnor2.A |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__xnor2.B), line:38:5, endln:38:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__xnor2 (work@sky130_fd_sc_hd__xnor2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__xnor2.functional.v, line:35:1, endln:53:10 + \_module_inst: work@sky130_fd_sc_hd__xnor2 (work@sky130_fd_sc_hd__xnor2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__xnor2.functional.v, line:35:1, endln:53:10 |vpiName:B |vpiFullName:work@sky130_fd_sc_hd__xnor2.B |vpiPort: \_port: (Y), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__xnor2 (work@sky130_fd_sc_hd__xnor2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__xnor2.functional.v, line:35:1, endln:53:10 + \_module_inst: work@sky130_fd_sc_hd__xnor2 (work@sky130_fd_sc_hd__xnor2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__xnor2.functional.v, line:35:1, endln:53:10 |vpiName:Y |vpiDirection:2 |vpiLowConn: @@ -55388,7 +55388,7 @@ design: (work@sky130_fd_sc_hd__xnor2) |vpiPort: \_port: (A), line:37:5, endln:37:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__xnor2 (work@sky130_fd_sc_hd__xnor2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__xnor2.functional.v, line:35:1, endln:53:10 + \_module_inst: work@sky130_fd_sc_hd__xnor2 (work@sky130_fd_sc_hd__xnor2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__xnor2.functional.v, line:35:1, endln:53:10 |vpiName:A |vpiDirection:1 |vpiLowConn: @@ -55400,7 +55400,7 @@ design: (work@sky130_fd_sc_hd__xnor2) |vpiPort: \_port: (B), line:38:5, endln:38:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__xnor2 (work@sky130_fd_sc_hd__xnor2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__xnor2.functional.v, line:35:1, endln:53:10 + \_module_inst: work@sky130_fd_sc_hd__xnor2 (work@sky130_fd_sc_hd__xnor2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__xnor2.functional.v, line:35:1, endln:53:10 |vpiName:B |vpiDirection:1 |vpiLowConn: @@ -55410,14 +55410,14 @@ design: (work@sky130_fd_sc_hd__xnor2) |vpiTypedef: \_logic_typespec: , line:44:12, endln:44:12 |uhdmtopModules: -\_module: work@sky130_fd_sc_hd__xnor2 (work@sky130_fd_sc_hd__xnor2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__xnor2.functional.v, line:35:1, endln:53:10 +\_module_inst: work@sky130_fd_sc_hd__xnor2 (work@sky130_fd_sc_hd__xnor2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__xnor2.functional.v, line:35:1, endln:53:10 |vpiName:work@sky130_fd_sc_hd__xnor2 |vpiDefName:work@sky130_fd_sc_hd__xnor2 |vpiTop:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__xnor2.xnor0_out_Y), line:47:10, endln:47:21 |vpiParent: - \_module: work@sky130_fd_sc_hd__xnor2 (work@sky130_fd_sc_hd__xnor2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__xnor2.functional.v, line:35:1, endln:53:10 + \_module_inst: work@sky130_fd_sc_hd__xnor2 (work@sky130_fd_sc_hd__xnor2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__xnor2.functional.v, line:35:1, endln:53:10 |vpiTypespec: \_logic_typespec: , line:47:5, endln:47:9 |vpiName:xnor0_out_Y @@ -55426,7 +55426,7 @@ design: (work@sky130_fd_sc_hd__xnor2) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__xnor2.Y), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__xnor2 (work@sky130_fd_sc_hd__xnor2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__xnor2.functional.v, line:35:1, endln:53:10 + \_module_inst: work@sky130_fd_sc_hd__xnor2 (work@sky130_fd_sc_hd__xnor2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__xnor2.functional.v, line:35:1, endln:53:10 |vpiTypespec: \_logic_typespec: , line:42:12, endln:42:12 |vpiName:Y @@ -55434,7 +55434,7 @@ design: (work@sky130_fd_sc_hd__xnor2) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__xnor2.A), line:37:5, endln:37:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__xnor2 (work@sky130_fd_sc_hd__xnor2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__xnor2.functional.v, line:35:1, endln:53:10 + \_module_inst: work@sky130_fd_sc_hd__xnor2 (work@sky130_fd_sc_hd__xnor2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__xnor2.functional.v, line:35:1, endln:53:10 |vpiTypespec: \_logic_typespec: , line:43:12, endln:43:12 |vpiName:A @@ -55442,7 +55442,7 @@ design: (work@sky130_fd_sc_hd__xnor2) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__xnor2.B), line:38:5, endln:38:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__xnor2 (work@sky130_fd_sc_hd__xnor2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__xnor2.functional.v, line:35:1, endln:53:10 + \_module_inst: work@sky130_fd_sc_hd__xnor2 (work@sky130_fd_sc_hd__xnor2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__xnor2.functional.v, line:35:1, endln:53:10 |vpiTypespec: \_logic_typespec: , line:44:12, endln:44:12 |vpiName:B @@ -55451,7 +55451,7 @@ design: (work@sky130_fd_sc_hd__xnor2) |vpiPort: \_port: (Y), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__xnor2 (work@sky130_fd_sc_hd__xnor2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__xnor2.functional.v, line:35:1, endln:53:10 + \_module_inst: work@sky130_fd_sc_hd__xnor2 (work@sky130_fd_sc_hd__xnor2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__xnor2.functional.v, line:35:1, endln:53:10 |vpiName:Y |vpiDirection:2 |vpiLowConn: @@ -55465,7 +55465,7 @@ design: (work@sky130_fd_sc_hd__xnor2) |vpiPort: \_port: (A), line:37:5, endln:37:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__xnor2 (work@sky130_fd_sc_hd__xnor2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__xnor2.functional.v, line:35:1, endln:53:10 + \_module_inst: work@sky130_fd_sc_hd__xnor2 (work@sky130_fd_sc_hd__xnor2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__xnor2.functional.v, line:35:1, endln:53:10 |vpiName:A |vpiDirection:1 |vpiLowConn: @@ -55479,7 +55479,7 @@ design: (work@sky130_fd_sc_hd__xnor2) |vpiPort: \_port: (B), line:38:5, endln:38:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__xnor2 (work@sky130_fd_sc_hd__xnor2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__xnor2.functional.v, line:35:1, endln:53:10 + \_module_inst: work@sky130_fd_sc_hd__xnor2 (work@sky130_fd_sc_hd__xnor2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__xnor2.functional.v, line:35:1, endln:53:10 |vpiName:B |vpiDirection:1 |vpiLowConn: @@ -55493,7 +55493,7 @@ design: (work@sky130_fd_sc_hd__xnor2) |vpiPrimitive: \_gate: work@xnor (work@sky130_fd_sc_hd__xnor2.xnor0), line:50:10, endln:50:46 |vpiParent: - \_module: work@sky130_fd_sc_hd__xnor2 (work@sky130_fd_sc_hd__xnor2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__xnor2.functional.v, line:35:1, endln:53:10 + \_module_inst: work@sky130_fd_sc_hd__xnor2 (work@sky130_fd_sc_hd__xnor2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__xnor2.functional.v, line:35:1, endln:53:10 |vpiDefName:work@xnor |vpiName:xnor0 |vpiFullName:work@sky130_fd_sc_hd__xnor2.xnor0 @@ -55542,7 +55542,7 @@ design: (work@sky130_fd_sc_hd__xnor2) |vpiPrimitive: \_gate: work@buf (work@sky130_fd_sc_hd__xnor2.buf0), line:51:10, endln:51:46 |vpiParent: - \_module: work@sky130_fd_sc_hd__xnor2 (work@sky130_fd_sc_hd__xnor2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__xnor2.functional.v, line:35:1, endln:53:10 + \_module_inst: work@sky130_fd_sc_hd__xnor2 (work@sky130_fd_sc_hd__xnor2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__xnor2.functional.v, line:35:1, endln:53:10 |vpiDefName:work@buf |vpiName:buf0 |vpiFullName:work@sky130_fd_sc_hd__xnor2.buf0 @@ -55585,7 +55585,7 @@ Processing: -cd cells/cells -DUNIT_DELAY -writepp -parse -nocache -nobuiltin -no design: (work@sky130_fd_sc_hd__o211a) |vpiName:work@sky130_fd_sc_hd__o211a |uhdmallModules: -\_module: work@sky130_fd_sc_hd__o211a (work@sky130_fd_sc_hd__o211a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o211a.functional.v, line:35:1, endln:59:10 +\_module_inst: work@sky130_fd_sc_hd__o211a (work@sky130_fd_sc_hd__o211a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o211a.functional.v, line:35:1, endln:59:10 |vpiParent: \_design: (work@sky130_fd_sc_hd__o211a) |vpiFullName:work@sky130_fd_sc_hd__o211a @@ -55593,51 +55593,51 @@ design: (work@sky130_fd_sc_hd__o211a) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o211a.or0_out), line:51:10, endln:51:17 |vpiParent: - \_module: work@sky130_fd_sc_hd__o211a (work@sky130_fd_sc_hd__o211a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o211a.functional.v, line:35:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__o211a (work@sky130_fd_sc_hd__o211a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o211a.functional.v, line:35:1, endln:59:10 |vpiName:or0_out |vpiFullName:work@sky130_fd_sc_hd__o211a.or0_out |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o211a.and0_out_X), line:52:10, endln:52:20 |vpiParent: - \_module: work@sky130_fd_sc_hd__o211a (work@sky130_fd_sc_hd__o211a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o211a.functional.v, line:35:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__o211a (work@sky130_fd_sc_hd__o211a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o211a.functional.v, line:35:1, endln:59:10 |vpiName:and0_out_X |vpiFullName:work@sky130_fd_sc_hd__o211a.and0_out_X |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o211a.X), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__o211a (work@sky130_fd_sc_hd__o211a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o211a.functional.v, line:35:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__o211a (work@sky130_fd_sc_hd__o211a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o211a.functional.v, line:35:1, endln:59:10 |vpiName:X |vpiFullName:work@sky130_fd_sc_hd__o211a.X |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o211a.A1), line:37:5, endln:37:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o211a (work@sky130_fd_sc_hd__o211a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o211a.functional.v, line:35:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__o211a (work@sky130_fd_sc_hd__o211a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o211a.functional.v, line:35:1, endln:59:10 |vpiName:A1 |vpiFullName:work@sky130_fd_sc_hd__o211a.A1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o211a.A2), line:38:5, endln:38:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o211a (work@sky130_fd_sc_hd__o211a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o211a.functional.v, line:35:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__o211a (work@sky130_fd_sc_hd__o211a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o211a.functional.v, line:35:1, endln:59:10 |vpiName:A2 |vpiFullName:work@sky130_fd_sc_hd__o211a.A2 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o211a.B1), line:39:5, endln:39:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o211a (work@sky130_fd_sc_hd__o211a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o211a.functional.v, line:35:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__o211a (work@sky130_fd_sc_hd__o211a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o211a.functional.v, line:35:1, endln:59:10 |vpiName:B1 |vpiFullName:work@sky130_fd_sc_hd__o211a.B1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o211a.C1), line:40:5, endln:40:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o211a (work@sky130_fd_sc_hd__o211a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o211a.functional.v, line:35:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__o211a (work@sky130_fd_sc_hd__o211a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o211a.functional.v, line:35:1, endln:59:10 |vpiName:C1 |vpiFullName:work@sky130_fd_sc_hd__o211a.C1 |vpiPort: \_port: (X), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__o211a (work@sky130_fd_sc_hd__o211a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o211a.functional.v, line:35:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__o211a (work@sky130_fd_sc_hd__o211a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o211a.functional.v, line:35:1, endln:59:10 |vpiName:X |vpiDirection:2 |vpiLowConn: @@ -55649,7 +55649,7 @@ design: (work@sky130_fd_sc_hd__o211a) |vpiPort: \_port: (A1), line:37:5, endln:37:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o211a (work@sky130_fd_sc_hd__o211a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o211a.functional.v, line:35:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__o211a (work@sky130_fd_sc_hd__o211a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o211a.functional.v, line:35:1, endln:59:10 |vpiName:A1 |vpiDirection:1 |vpiLowConn: @@ -55661,7 +55661,7 @@ design: (work@sky130_fd_sc_hd__o211a) |vpiPort: \_port: (A2), line:38:5, endln:38:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o211a (work@sky130_fd_sc_hd__o211a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o211a.functional.v, line:35:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__o211a (work@sky130_fd_sc_hd__o211a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o211a.functional.v, line:35:1, endln:59:10 |vpiName:A2 |vpiDirection:1 |vpiLowConn: @@ -55673,7 +55673,7 @@ design: (work@sky130_fd_sc_hd__o211a) |vpiPort: \_port: (B1), line:39:5, endln:39:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o211a (work@sky130_fd_sc_hd__o211a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o211a.functional.v, line:35:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__o211a (work@sky130_fd_sc_hd__o211a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o211a.functional.v, line:35:1, endln:59:10 |vpiName:B1 |vpiDirection:1 |vpiLowConn: @@ -55685,7 +55685,7 @@ design: (work@sky130_fd_sc_hd__o211a) |vpiPort: \_port: (C1), line:40:5, endln:40:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o211a (work@sky130_fd_sc_hd__o211a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o211a.functional.v, line:35:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__o211a (work@sky130_fd_sc_hd__o211a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o211a.functional.v, line:35:1, endln:59:10 |vpiName:C1 |vpiDirection:1 |vpiLowConn: @@ -55695,14 +55695,14 @@ design: (work@sky130_fd_sc_hd__o211a) |vpiTypedef: \_logic_typespec: , line:48:12, endln:48:12 |uhdmtopModules: -\_module: work@sky130_fd_sc_hd__o211a (work@sky130_fd_sc_hd__o211a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o211a.functional.v, line:35:1, endln:59:10 +\_module_inst: work@sky130_fd_sc_hd__o211a (work@sky130_fd_sc_hd__o211a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o211a.functional.v, line:35:1, endln:59:10 |vpiName:work@sky130_fd_sc_hd__o211a |vpiDefName:work@sky130_fd_sc_hd__o211a |vpiTop:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o211a.or0_out), line:51:10, endln:51:17 |vpiParent: - \_module: work@sky130_fd_sc_hd__o211a (work@sky130_fd_sc_hd__o211a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o211a.functional.v, line:35:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__o211a (work@sky130_fd_sc_hd__o211a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o211a.functional.v, line:35:1, endln:59:10 |vpiTypespec: \_logic_typespec: , line:51:5, endln:51:9 |vpiName:or0_out @@ -55711,7 +55711,7 @@ design: (work@sky130_fd_sc_hd__o211a) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o211a.and0_out_X), line:52:10, endln:52:20 |vpiParent: - \_module: work@sky130_fd_sc_hd__o211a (work@sky130_fd_sc_hd__o211a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o211a.functional.v, line:35:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__o211a (work@sky130_fd_sc_hd__o211a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o211a.functional.v, line:35:1, endln:59:10 |vpiTypespec: \_logic_typespec: , line:52:5, endln:52:9 |vpiName:and0_out_X @@ -55720,7 +55720,7 @@ design: (work@sky130_fd_sc_hd__o211a) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o211a.X), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__o211a (work@sky130_fd_sc_hd__o211a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o211a.functional.v, line:35:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__o211a (work@sky130_fd_sc_hd__o211a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o211a.functional.v, line:35:1, endln:59:10 |vpiTypespec: \_logic_typespec: , line:44:12, endln:44:12 |vpiName:X @@ -55728,7 +55728,7 @@ design: (work@sky130_fd_sc_hd__o211a) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o211a.A1), line:37:5, endln:37:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o211a (work@sky130_fd_sc_hd__o211a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o211a.functional.v, line:35:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__o211a (work@sky130_fd_sc_hd__o211a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o211a.functional.v, line:35:1, endln:59:10 |vpiTypespec: \_logic_typespec: , line:45:12, endln:45:12 |vpiName:A1 @@ -55736,7 +55736,7 @@ design: (work@sky130_fd_sc_hd__o211a) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o211a.A2), line:38:5, endln:38:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o211a (work@sky130_fd_sc_hd__o211a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o211a.functional.v, line:35:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__o211a (work@sky130_fd_sc_hd__o211a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o211a.functional.v, line:35:1, endln:59:10 |vpiTypespec: \_logic_typespec: , line:46:12, endln:46:12 |vpiName:A2 @@ -55744,7 +55744,7 @@ design: (work@sky130_fd_sc_hd__o211a) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o211a.B1), line:39:5, endln:39:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o211a (work@sky130_fd_sc_hd__o211a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o211a.functional.v, line:35:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__o211a (work@sky130_fd_sc_hd__o211a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o211a.functional.v, line:35:1, endln:59:10 |vpiTypespec: \_logic_typespec: , line:47:12, endln:47:12 |vpiName:B1 @@ -55752,7 +55752,7 @@ design: (work@sky130_fd_sc_hd__o211a) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o211a.C1), line:40:5, endln:40:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o211a (work@sky130_fd_sc_hd__o211a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o211a.functional.v, line:35:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__o211a (work@sky130_fd_sc_hd__o211a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o211a.functional.v, line:35:1, endln:59:10 |vpiTypespec: \_logic_typespec: , line:48:12, endln:48:12 |vpiName:C1 @@ -55761,7 +55761,7 @@ design: (work@sky130_fd_sc_hd__o211a) |vpiPort: \_port: (X), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__o211a (work@sky130_fd_sc_hd__o211a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o211a.functional.v, line:35:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__o211a (work@sky130_fd_sc_hd__o211a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o211a.functional.v, line:35:1, endln:59:10 |vpiName:X |vpiDirection:2 |vpiLowConn: @@ -55775,7 +55775,7 @@ design: (work@sky130_fd_sc_hd__o211a) |vpiPort: \_port: (A1), line:37:5, endln:37:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o211a (work@sky130_fd_sc_hd__o211a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o211a.functional.v, line:35:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__o211a (work@sky130_fd_sc_hd__o211a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o211a.functional.v, line:35:1, endln:59:10 |vpiName:A1 |vpiDirection:1 |vpiLowConn: @@ -55789,7 +55789,7 @@ design: (work@sky130_fd_sc_hd__o211a) |vpiPort: \_port: (A2), line:38:5, endln:38:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o211a (work@sky130_fd_sc_hd__o211a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o211a.functional.v, line:35:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__o211a (work@sky130_fd_sc_hd__o211a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o211a.functional.v, line:35:1, endln:59:10 |vpiName:A2 |vpiDirection:1 |vpiLowConn: @@ -55803,7 +55803,7 @@ design: (work@sky130_fd_sc_hd__o211a) |vpiPort: \_port: (B1), line:39:5, endln:39:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o211a (work@sky130_fd_sc_hd__o211a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o211a.functional.v, line:35:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__o211a (work@sky130_fd_sc_hd__o211a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o211a.functional.v, line:35:1, endln:59:10 |vpiName:B1 |vpiDirection:1 |vpiLowConn: @@ -55817,7 +55817,7 @@ design: (work@sky130_fd_sc_hd__o211a) |vpiPort: \_port: (C1), line:40:5, endln:40:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o211a (work@sky130_fd_sc_hd__o211a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o211a.functional.v, line:35:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__o211a (work@sky130_fd_sc_hd__o211a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o211a.functional.v, line:35:1, endln:59:10 |vpiName:C1 |vpiDirection:1 |vpiLowConn: @@ -55831,7 +55831,7 @@ design: (work@sky130_fd_sc_hd__o211a) |vpiPrimitive: \_gate: work@or (work@sky130_fd_sc_hd__o211a.or0), line:55:9, endln:55:43 |vpiParent: - \_module: work@sky130_fd_sc_hd__o211a (work@sky130_fd_sc_hd__o211a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o211a.functional.v, line:35:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__o211a (work@sky130_fd_sc_hd__o211a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o211a.functional.v, line:35:1, endln:59:10 |vpiDefName:work@or |vpiName:or0 |vpiFullName:work@sky130_fd_sc_hd__o211a.or0 @@ -55880,7 +55880,7 @@ design: (work@sky130_fd_sc_hd__o211a) |vpiPrimitive: \_gate: work@and (work@sky130_fd_sc_hd__o211a.and0), line:56:9, endln:56:43 |vpiParent: - \_module: work@sky130_fd_sc_hd__o211a (work@sky130_fd_sc_hd__o211a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o211a.functional.v, line:35:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__o211a (work@sky130_fd_sc_hd__o211a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o211a.functional.v, line:35:1, endln:59:10 |vpiDefName:work@and |vpiName:and0 |vpiFullName:work@sky130_fd_sc_hd__o211a.and0 @@ -55943,7 +55943,7 @@ design: (work@sky130_fd_sc_hd__o211a) |vpiPrimitive: \_gate: work@buf (work@sky130_fd_sc_hd__o211a.buf0), line:57:9, endln:57:43 |vpiParent: - \_module: work@sky130_fd_sc_hd__o211a (work@sky130_fd_sc_hd__o211a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o211a.functional.v, line:35:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__o211a (work@sky130_fd_sc_hd__o211a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o211a.functional.v, line:35:1, endln:59:10 |vpiDefName:work@buf |vpiName:buf0 |vpiFullName:work@sky130_fd_sc_hd__o211a.buf0 @@ -55986,7 +55986,7 @@ Processing: -cd cells/cells -DUNIT_DELAY -writepp -parse -nocache -nobuiltin -no design: (work@sky130_fd_sc_hd__nor3b) |vpiName:work@sky130_fd_sc_hd__nor3b |uhdmallModules: -\_module: work@sky130_fd_sc_hd__nor3b (work@sky130_fd_sc_hd__nor3b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor3b.functional.v, line:35:1, endln:57:10 +\_module_inst: work@sky130_fd_sc_hd__nor3b (work@sky130_fd_sc_hd__nor3b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor3b.functional.v, line:35:1, endln:57:10 |vpiParent: \_design: (work@sky130_fd_sc_hd__nor3b) |vpiFullName:work@sky130_fd_sc_hd__nor3b @@ -55994,45 +55994,45 @@ design: (work@sky130_fd_sc_hd__nor3b) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__nor3b.nor0_out), line:49:10, endln:49:18 |vpiParent: - \_module: work@sky130_fd_sc_hd__nor3b (work@sky130_fd_sc_hd__nor3b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor3b.functional.v, line:35:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__nor3b (work@sky130_fd_sc_hd__nor3b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor3b.functional.v, line:35:1, endln:57:10 |vpiName:nor0_out |vpiFullName:work@sky130_fd_sc_hd__nor3b.nor0_out |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__nor3b.and0_out_Y), line:50:10, endln:50:20 |vpiParent: - \_module: work@sky130_fd_sc_hd__nor3b (work@sky130_fd_sc_hd__nor3b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor3b.functional.v, line:35:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__nor3b (work@sky130_fd_sc_hd__nor3b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor3b.functional.v, line:35:1, endln:57:10 |vpiName:and0_out_Y |vpiFullName:work@sky130_fd_sc_hd__nor3b.and0_out_Y |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__nor3b.Y), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__nor3b (work@sky130_fd_sc_hd__nor3b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor3b.functional.v, line:35:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__nor3b (work@sky130_fd_sc_hd__nor3b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor3b.functional.v, line:35:1, endln:57:10 |vpiName:Y |vpiFullName:work@sky130_fd_sc_hd__nor3b.Y |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__nor3b.A), line:37:5, endln:37:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__nor3b (work@sky130_fd_sc_hd__nor3b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor3b.functional.v, line:35:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__nor3b (work@sky130_fd_sc_hd__nor3b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor3b.functional.v, line:35:1, endln:57:10 |vpiName:A |vpiFullName:work@sky130_fd_sc_hd__nor3b.A |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__nor3b.B), line:38:5, endln:38:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__nor3b (work@sky130_fd_sc_hd__nor3b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor3b.functional.v, line:35:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__nor3b (work@sky130_fd_sc_hd__nor3b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor3b.functional.v, line:35:1, endln:57:10 |vpiName:B |vpiFullName:work@sky130_fd_sc_hd__nor3b.B |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__nor3b.C_N), line:39:5, endln:39:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__nor3b (work@sky130_fd_sc_hd__nor3b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor3b.functional.v, line:35:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__nor3b (work@sky130_fd_sc_hd__nor3b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor3b.functional.v, line:35:1, endln:57:10 |vpiName:C_N |vpiFullName:work@sky130_fd_sc_hd__nor3b.C_N |vpiPort: \_port: (Y), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__nor3b (work@sky130_fd_sc_hd__nor3b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor3b.functional.v, line:35:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__nor3b (work@sky130_fd_sc_hd__nor3b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor3b.functional.v, line:35:1, endln:57:10 |vpiName:Y |vpiDirection:2 |vpiLowConn: @@ -56044,7 +56044,7 @@ design: (work@sky130_fd_sc_hd__nor3b) |vpiPort: \_port: (A), line:37:5, endln:37:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__nor3b (work@sky130_fd_sc_hd__nor3b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor3b.functional.v, line:35:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__nor3b (work@sky130_fd_sc_hd__nor3b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor3b.functional.v, line:35:1, endln:57:10 |vpiName:A |vpiDirection:1 |vpiLowConn: @@ -56056,7 +56056,7 @@ design: (work@sky130_fd_sc_hd__nor3b) |vpiPort: \_port: (B), line:38:5, endln:38:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__nor3b (work@sky130_fd_sc_hd__nor3b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor3b.functional.v, line:35:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__nor3b (work@sky130_fd_sc_hd__nor3b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor3b.functional.v, line:35:1, endln:57:10 |vpiName:B |vpiDirection:1 |vpiLowConn: @@ -56068,7 +56068,7 @@ design: (work@sky130_fd_sc_hd__nor3b) |vpiPort: \_port: (C_N), line:39:5, endln:39:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__nor3b (work@sky130_fd_sc_hd__nor3b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor3b.functional.v, line:35:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__nor3b (work@sky130_fd_sc_hd__nor3b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor3b.functional.v, line:35:1, endln:57:10 |vpiName:C_N |vpiDirection:1 |vpiLowConn: @@ -56078,14 +56078,14 @@ design: (work@sky130_fd_sc_hd__nor3b) |vpiTypedef: \_logic_typespec: , line:46:12, endln:46:12 |uhdmtopModules: -\_module: work@sky130_fd_sc_hd__nor3b (work@sky130_fd_sc_hd__nor3b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor3b.functional.v, line:35:1, endln:57:10 +\_module_inst: work@sky130_fd_sc_hd__nor3b (work@sky130_fd_sc_hd__nor3b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor3b.functional.v, line:35:1, endln:57:10 |vpiName:work@sky130_fd_sc_hd__nor3b |vpiDefName:work@sky130_fd_sc_hd__nor3b |vpiTop:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__nor3b.nor0_out), line:49:10, endln:49:18 |vpiParent: - \_module: work@sky130_fd_sc_hd__nor3b (work@sky130_fd_sc_hd__nor3b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor3b.functional.v, line:35:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__nor3b (work@sky130_fd_sc_hd__nor3b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor3b.functional.v, line:35:1, endln:57:10 |vpiTypespec: \_logic_typespec: , line:49:5, endln:49:9 |vpiName:nor0_out @@ -56094,7 +56094,7 @@ design: (work@sky130_fd_sc_hd__nor3b) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__nor3b.and0_out_Y), line:50:10, endln:50:20 |vpiParent: - \_module: work@sky130_fd_sc_hd__nor3b (work@sky130_fd_sc_hd__nor3b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor3b.functional.v, line:35:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__nor3b (work@sky130_fd_sc_hd__nor3b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor3b.functional.v, line:35:1, endln:57:10 |vpiTypespec: \_logic_typespec: , line:50:5, endln:50:9 |vpiName:and0_out_Y @@ -56103,7 +56103,7 @@ design: (work@sky130_fd_sc_hd__nor3b) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__nor3b.Y), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__nor3b (work@sky130_fd_sc_hd__nor3b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor3b.functional.v, line:35:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__nor3b (work@sky130_fd_sc_hd__nor3b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor3b.functional.v, line:35:1, endln:57:10 |vpiTypespec: \_logic_typespec: , line:43:12, endln:43:12 |vpiName:Y @@ -56111,7 +56111,7 @@ design: (work@sky130_fd_sc_hd__nor3b) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__nor3b.A), line:37:5, endln:37:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__nor3b (work@sky130_fd_sc_hd__nor3b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor3b.functional.v, line:35:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__nor3b (work@sky130_fd_sc_hd__nor3b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor3b.functional.v, line:35:1, endln:57:10 |vpiTypespec: \_logic_typespec: , line:44:12, endln:44:12 |vpiName:A @@ -56119,7 +56119,7 @@ design: (work@sky130_fd_sc_hd__nor3b) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__nor3b.B), line:38:5, endln:38:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__nor3b (work@sky130_fd_sc_hd__nor3b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor3b.functional.v, line:35:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__nor3b (work@sky130_fd_sc_hd__nor3b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor3b.functional.v, line:35:1, endln:57:10 |vpiTypespec: \_logic_typespec: , line:45:12, endln:45:12 |vpiName:B @@ -56127,7 +56127,7 @@ design: (work@sky130_fd_sc_hd__nor3b) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__nor3b.C_N), line:39:5, endln:39:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__nor3b (work@sky130_fd_sc_hd__nor3b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor3b.functional.v, line:35:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__nor3b (work@sky130_fd_sc_hd__nor3b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor3b.functional.v, line:35:1, endln:57:10 |vpiTypespec: \_logic_typespec: , line:46:12, endln:46:12 |vpiName:C_N @@ -56136,7 +56136,7 @@ design: (work@sky130_fd_sc_hd__nor3b) |vpiPort: \_port: (Y), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__nor3b (work@sky130_fd_sc_hd__nor3b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor3b.functional.v, line:35:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__nor3b (work@sky130_fd_sc_hd__nor3b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor3b.functional.v, line:35:1, endln:57:10 |vpiName:Y |vpiDirection:2 |vpiLowConn: @@ -56150,7 +56150,7 @@ design: (work@sky130_fd_sc_hd__nor3b) |vpiPort: \_port: (A), line:37:5, endln:37:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__nor3b (work@sky130_fd_sc_hd__nor3b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor3b.functional.v, line:35:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__nor3b (work@sky130_fd_sc_hd__nor3b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor3b.functional.v, line:35:1, endln:57:10 |vpiName:A |vpiDirection:1 |vpiLowConn: @@ -56164,7 +56164,7 @@ design: (work@sky130_fd_sc_hd__nor3b) |vpiPort: \_port: (B), line:38:5, endln:38:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__nor3b (work@sky130_fd_sc_hd__nor3b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor3b.functional.v, line:35:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__nor3b (work@sky130_fd_sc_hd__nor3b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor3b.functional.v, line:35:1, endln:57:10 |vpiName:B |vpiDirection:1 |vpiLowConn: @@ -56178,7 +56178,7 @@ design: (work@sky130_fd_sc_hd__nor3b) |vpiPort: \_port: (C_N), line:39:5, endln:39:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__nor3b (work@sky130_fd_sc_hd__nor3b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor3b.functional.v, line:35:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__nor3b (work@sky130_fd_sc_hd__nor3b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor3b.functional.v, line:35:1, endln:57:10 |vpiName:C_N |vpiDirection:1 |vpiLowConn: @@ -56192,7 +56192,7 @@ design: (work@sky130_fd_sc_hd__nor3b) |vpiPrimitive: \_gate: work@nor (work@sky130_fd_sc_hd__nor3b.nor0), line:53:9, endln:53:43 |vpiParent: - \_module: work@sky130_fd_sc_hd__nor3b (work@sky130_fd_sc_hd__nor3b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor3b.functional.v, line:35:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__nor3b (work@sky130_fd_sc_hd__nor3b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor3b.functional.v, line:35:1, endln:57:10 |vpiDefName:work@nor |vpiName:nor0 |vpiFullName:work@sky130_fd_sc_hd__nor3b.nor0 @@ -56241,7 +56241,7 @@ design: (work@sky130_fd_sc_hd__nor3b) |vpiPrimitive: \_gate: work@and (work@sky130_fd_sc_hd__nor3b.and0), line:54:9, endln:54:43 |vpiParent: - \_module: work@sky130_fd_sc_hd__nor3b (work@sky130_fd_sc_hd__nor3b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor3b.functional.v, line:35:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__nor3b (work@sky130_fd_sc_hd__nor3b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor3b.functional.v, line:35:1, endln:57:10 |vpiDefName:work@and |vpiName:and0 |vpiFullName:work@sky130_fd_sc_hd__nor3b.and0 @@ -56290,7 +56290,7 @@ design: (work@sky130_fd_sc_hd__nor3b) |vpiPrimitive: \_gate: work@buf (work@sky130_fd_sc_hd__nor3b.buf0), line:55:9, endln:55:43 |vpiParent: - \_module: work@sky130_fd_sc_hd__nor3b (work@sky130_fd_sc_hd__nor3b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor3b.functional.v, line:35:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__nor3b (work@sky130_fd_sc_hd__nor3b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor3b.functional.v, line:35:1, endln:57:10 |vpiDefName:work@buf |vpiName:buf0 |vpiFullName:work@sky130_fd_sc_hd__nor3b.buf0 @@ -56333,7 +56333,7 @@ Processing: -cd cells/cells -DUNIT_DELAY -writepp -parse -nocache -nobuiltin -no design: (work@sky130_fd_sc_hd__o31ai) |vpiName:work@sky130_fd_sc_hd__o31ai |uhdmallModules: -\_module: work@sky130_fd_sc_hd__o31ai (work@sky130_fd_sc_hd__o31ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o31ai.functional.v, line:35:1, endln:59:10 +\_module_inst: work@sky130_fd_sc_hd__o31ai (work@sky130_fd_sc_hd__o31ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o31ai.functional.v, line:35:1, endln:59:10 |vpiParent: \_design: (work@sky130_fd_sc_hd__o31ai) |vpiFullName:work@sky130_fd_sc_hd__o31ai @@ -56341,51 +56341,51 @@ design: (work@sky130_fd_sc_hd__o31ai) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o31ai.or0_out), line:51:10, endln:51:17 |vpiParent: - \_module: work@sky130_fd_sc_hd__o31ai (work@sky130_fd_sc_hd__o31ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o31ai.functional.v, line:35:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__o31ai (work@sky130_fd_sc_hd__o31ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o31ai.functional.v, line:35:1, endln:59:10 |vpiName:or0_out |vpiFullName:work@sky130_fd_sc_hd__o31ai.or0_out |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o31ai.nand0_out_Y), line:52:10, endln:52:21 |vpiParent: - \_module: work@sky130_fd_sc_hd__o31ai (work@sky130_fd_sc_hd__o31ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o31ai.functional.v, line:35:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__o31ai (work@sky130_fd_sc_hd__o31ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o31ai.functional.v, line:35:1, endln:59:10 |vpiName:nand0_out_Y |vpiFullName:work@sky130_fd_sc_hd__o31ai.nand0_out_Y |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o31ai.Y), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__o31ai (work@sky130_fd_sc_hd__o31ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o31ai.functional.v, line:35:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__o31ai (work@sky130_fd_sc_hd__o31ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o31ai.functional.v, line:35:1, endln:59:10 |vpiName:Y |vpiFullName:work@sky130_fd_sc_hd__o31ai.Y |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o31ai.A1), line:37:5, endln:37:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o31ai (work@sky130_fd_sc_hd__o31ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o31ai.functional.v, line:35:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__o31ai (work@sky130_fd_sc_hd__o31ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o31ai.functional.v, line:35:1, endln:59:10 |vpiName:A1 |vpiFullName:work@sky130_fd_sc_hd__o31ai.A1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o31ai.A2), line:38:5, endln:38:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o31ai (work@sky130_fd_sc_hd__o31ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o31ai.functional.v, line:35:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__o31ai (work@sky130_fd_sc_hd__o31ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o31ai.functional.v, line:35:1, endln:59:10 |vpiName:A2 |vpiFullName:work@sky130_fd_sc_hd__o31ai.A2 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o31ai.A3), line:39:5, endln:39:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o31ai (work@sky130_fd_sc_hd__o31ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o31ai.functional.v, line:35:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__o31ai (work@sky130_fd_sc_hd__o31ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o31ai.functional.v, line:35:1, endln:59:10 |vpiName:A3 |vpiFullName:work@sky130_fd_sc_hd__o31ai.A3 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o31ai.B1), line:40:5, endln:40:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o31ai (work@sky130_fd_sc_hd__o31ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o31ai.functional.v, line:35:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__o31ai (work@sky130_fd_sc_hd__o31ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o31ai.functional.v, line:35:1, endln:59:10 |vpiName:B1 |vpiFullName:work@sky130_fd_sc_hd__o31ai.B1 |vpiPort: \_port: (Y), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__o31ai (work@sky130_fd_sc_hd__o31ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o31ai.functional.v, line:35:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__o31ai (work@sky130_fd_sc_hd__o31ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o31ai.functional.v, line:35:1, endln:59:10 |vpiName:Y |vpiDirection:2 |vpiLowConn: @@ -56397,7 +56397,7 @@ design: (work@sky130_fd_sc_hd__o31ai) |vpiPort: \_port: (A1), line:37:5, endln:37:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o31ai (work@sky130_fd_sc_hd__o31ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o31ai.functional.v, line:35:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__o31ai (work@sky130_fd_sc_hd__o31ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o31ai.functional.v, line:35:1, endln:59:10 |vpiName:A1 |vpiDirection:1 |vpiLowConn: @@ -56409,7 +56409,7 @@ design: (work@sky130_fd_sc_hd__o31ai) |vpiPort: \_port: (A2), line:38:5, endln:38:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o31ai (work@sky130_fd_sc_hd__o31ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o31ai.functional.v, line:35:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__o31ai (work@sky130_fd_sc_hd__o31ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o31ai.functional.v, line:35:1, endln:59:10 |vpiName:A2 |vpiDirection:1 |vpiLowConn: @@ -56421,7 +56421,7 @@ design: (work@sky130_fd_sc_hd__o31ai) |vpiPort: \_port: (A3), line:39:5, endln:39:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o31ai (work@sky130_fd_sc_hd__o31ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o31ai.functional.v, line:35:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__o31ai (work@sky130_fd_sc_hd__o31ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o31ai.functional.v, line:35:1, endln:59:10 |vpiName:A3 |vpiDirection:1 |vpiLowConn: @@ -56433,7 +56433,7 @@ design: (work@sky130_fd_sc_hd__o31ai) |vpiPort: \_port: (B1), line:40:5, endln:40:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o31ai (work@sky130_fd_sc_hd__o31ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o31ai.functional.v, line:35:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__o31ai (work@sky130_fd_sc_hd__o31ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o31ai.functional.v, line:35:1, endln:59:10 |vpiName:B1 |vpiDirection:1 |vpiLowConn: @@ -56443,14 +56443,14 @@ design: (work@sky130_fd_sc_hd__o31ai) |vpiTypedef: \_logic_typespec: , line:48:12, endln:48:12 |uhdmtopModules: -\_module: work@sky130_fd_sc_hd__o31ai (work@sky130_fd_sc_hd__o31ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o31ai.functional.v, line:35:1, endln:59:10 +\_module_inst: work@sky130_fd_sc_hd__o31ai (work@sky130_fd_sc_hd__o31ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o31ai.functional.v, line:35:1, endln:59:10 |vpiName:work@sky130_fd_sc_hd__o31ai |vpiDefName:work@sky130_fd_sc_hd__o31ai |vpiTop:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o31ai.or0_out), line:51:10, endln:51:17 |vpiParent: - \_module: work@sky130_fd_sc_hd__o31ai (work@sky130_fd_sc_hd__o31ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o31ai.functional.v, line:35:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__o31ai (work@sky130_fd_sc_hd__o31ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o31ai.functional.v, line:35:1, endln:59:10 |vpiTypespec: \_logic_typespec: , line:51:5, endln:51:9 |vpiName:or0_out @@ -56459,7 +56459,7 @@ design: (work@sky130_fd_sc_hd__o31ai) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o31ai.nand0_out_Y), line:52:10, endln:52:21 |vpiParent: - \_module: work@sky130_fd_sc_hd__o31ai (work@sky130_fd_sc_hd__o31ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o31ai.functional.v, line:35:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__o31ai (work@sky130_fd_sc_hd__o31ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o31ai.functional.v, line:35:1, endln:59:10 |vpiTypespec: \_logic_typespec: , line:52:5, endln:52:9 |vpiName:nand0_out_Y @@ -56468,7 +56468,7 @@ design: (work@sky130_fd_sc_hd__o31ai) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o31ai.Y), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__o31ai (work@sky130_fd_sc_hd__o31ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o31ai.functional.v, line:35:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__o31ai (work@sky130_fd_sc_hd__o31ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o31ai.functional.v, line:35:1, endln:59:10 |vpiTypespec: \_logic_typespec: , line:44:12, endln:44:12 |vpiName:Y @@ -56476,7 +56476,7 @@ design: (work@sky130_fd_sc_hd__o31ai) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o31ai.A1), line:37:5, endln:37:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o31ai (work@sky130_fd_sc_hd__o31ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o31ai.functional.v, line:35:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__o31ai (work@sky130_fd_sc_hd__o31ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o31ai.functional.v, line:35:1, endln:59:10 |vpiTypespec: \_logic_typespec: , line:45:12, endln:45:12 |vpiName:A1 @@ -56484,7 +56484,7 @@ design: (work@sky130_fd_sc_hd__o31ai) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o31ai.A2), line:38:5, endln:38:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o31ai (work@sky130_fd_sc_hd__o31ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o31ai.functional.v, line:35:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__o31ai (work@sky130_fd_sc_hd__o31ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o31ai.functional.v, line:35:1, endln:59:10 |vpiTypespec: \_logic_typespec: , line:46:12, endln:46:12 |vpiName:A2 @@ -56492,7 +56492,7 @@ design: (work@sky130_fd_sc_hd__o31ai) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o31ai.A3), line:39:5, endln:39:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o31ai (work@sky130_fd_sc_hd__o31ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o31ai.functional.v, line:35:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__o31ai (work@sky130_fd_sc_hd__o31ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o31ai.functional.v, line:35:1, endln:59:10 |vpiTypespec: \_logic_typespec: , line:47:12, endln:47:12 |vpiName:A3 @@ -56500,7 +56500,7 @@ design: (work@sky130_fd_sc_hd__o31ai) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o31ai.B1), line:40:5, endln:40:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o31ai (work@sky130_fd_sc_hd__o31ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o31ai.functional.v, line:35:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__o31ai (work@sky130_fd_sc_hd__o31ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o31ai.functional.v, line:35:1, endln:59:10 |vpiTypespec: \_logic_typespec: , line:48:12, endln:48:12 |vpiName:B1 @@ -56509,7 +56509,7 @@ design: (work@sky130_fd_sc_hd__o31ai) |vpiPort: \_port: (Y), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__o31ai (work@sky130_fd_sc_hd__o31ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o31ai.functional.v, line:35:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__o31ai (work@sky130_fd_sc_hd__o31ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o31ai.functional.v, line:35:1, endln:59:10 |vpiName:Y |vpiDirection:2 |vpiLowConn: @@ -56523,7 +56523,7 @@ design: (work@sky130_fd_sc_hd__o31ai) |vpiPort: \_port: (A1), line:37:5, endln:37:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o31ai (work@sky130_fd_sc_hd__o31ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o31ai.functional.v, line:35:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__o31ai (work@sky130_fd_sc_hd__o31ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o31ai.functional.v, line:35:1, endln:59:10 |vpiName:A1 |vpiDirection:1 |vpiLowConn: @@ -56537,7 +56537,7 @@ design: (work@sky130_fd_sc_hd__o31ai) |vpiPort: \_port: (A2), line:38:5, endln:38:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o31ai (work@sky130_fd_sc_hd__o31ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o31ai.functional.v, line:35:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__o31ai (work@sky130_fd_sc_hd__o31ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o31ai.functional.v, line:35:1, endln:59:10 |vpiName:A2 |vpiDirection:1 |vpiLowConn: @@ -56551,7 +56551,7 @@ design: (work@sky130_fd_sc_hd__o31ai) |vpiPort: \_port: (A3), line:39:5, endln:39:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o31ai (work@sky130_fd_sc_hd__o31ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o31ai.functional.v, line:35:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__o31ai (work@sky130_fd_sc_hd__o31ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o31ai.functional.v, line:35:1, endln:59:10 |vpiName:A3 |vpiDirection:1 |vpiLowConn: @@ -56565,7 +56565,7 @@ design: (work@sky130_fd_sc_hd__o31ai) |vpiPort: \_port: (B1), line:40:5, endln:40:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o31ai (work@sky130_fd_sc_hd__o31ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o31ai.functional.v, line:35:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__o31ai (work@sky130_fd_sc_hd__o31ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o31ai.functional.v, line:35:1, endln:59:10 |vpiName:B1 |vpiDirection:1 |vpiLowConn: @@ -56579,7 +56579,7 @@ design: (work@sky130_fd_sc_hd__o31ai) |vpiPrimitive: \_gate: work@or (work@sky130_fd_sc_hd__o31ai.or0), line:55:10, endln:55:46 |vpiParent: - \_module: work@sky130_fd_sc_hd__o31ai (work@sky130_fd_sc_hd__o31ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o31ai.functional.v, line:35:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__o31ai (work@sky130_fd_sc_hd__o31ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o31ai.functional.v, line:35:1, endln:59:10 |vpiDefName:work@or |vpiName:or0 |vpiFullName:work@sky130_fd_sc_hd__o31ai.or0 @@ -56642,7 +56642,7 @@ design: (work@sky130_fd_sc_hd__o31ai) |vpiPrimitive: \_gate: work@nand (work@sky130_fd_sc_hd__o31ai.nand0), line:56:10, endln:56:46 |vpiParent: - \_module: work@sky130_fd_sc_hd__o31ai (work@sky130_fd_sc_hd__o31ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o31ai.functional.v, line:35:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__o31ai (work@sky130_fd_sc_hd__o31ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o31ai.functional.v, line:35:1, endln:59:10 |vpiDefName:work@nand |vpiName:nand0 |vpiFullName:work@sky130_fd_sc_hd__o31ai.nand0 @@ -56691,7 +56691,7 @@ design: (work@sky130_fd_sc_hd__o31ai) |vpiPrimitive: \_gate: work@buf (work@sky130_fd_sc_hd__o31ai.buf0), line:57:10, endln:57:46 |vpiParent: - \_module: work@sky130_fd_sc_hd__o31ai (work@sky130_fd_sc_hd__o31ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o31ai.functional.v, line:35:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__o31ai (work@sky130_fd_sc_hd__o31ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o31ai.functional.v, line:35:1, endln:59:10 |vpiDefName:work@buf |vpiName:buf0 |vpiFullName:work@sky130_fd_sc_hd__o31ai.buf0 @@ -56734,7 +56734,7 @@ Processing: -cd cells/cells -DUNIT_DELAY -writepp -parse -nocache -nobuiltin -no design: (work@sky130_fd_sc_hd__dlymetal6s6s) |vpiName:work@sky130_fd_sc_hd__dlymetal6s6s |uhdmallModules: -\_module: work@sky130_fd_sc_hd__dlymetal6s6s (work@sky130_fd_sc_hd__dlymetal6s6s), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlymetal6s6s.functional.v, line:34:1, endln:50:10 +\_module_inst: work@sky130_fd_sc_hd__dlymetal6s6s (work@sky130_fd_sc_hd__dlymetal6s6s), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlymetal6s6s.functional.v, line:34:1, endln:50:10 |vpiParent: \_design: (work@sky130_fd_sc_hd__dlymetal6s6s) |vpiFullName:work@sky130_fd_sc_hd__dlymetal6s6s @@ -56742,26 +56742,26 @@ design: (work@sky130_fd_sc_hd__dlymetal6s6s) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__dlymetal6s6s.buf0_out_X), line:44:10, endln:44:20 |vpiParent: - \_module: work@sky130_fd_sc_hd__dlymetal6s6s (work@sky130_fd_sc_hd__dlymetal6s6s), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlymetal6s6s.functional.v, line:34:1, endln:50:10 + \_module_inst: work@sky130_fd_sc_hd__dlymetal6s6s (work@sky130_fd_sc_hd__dlymetal6s6s), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlymetal6s6s.functional.v, line:34:1, endln:50:10 |vpiName:buf0_out_X |vpiFullName:work@sky130_fd_sc_hd__dlymetal6s6s.buf0_out_X |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__dlymetal6s6s.X), line:35:5, endln:35:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__dlymetal6s6s (work@sky130_fd_sc_hd__dlymetal6s6s), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlymetal6s6s.functional.v, line:34:1, endln:50:10 + \_module_inst: work@sky130_fd_sc_hd__dlymetal6s6s (work@sky130_fd_sc_hd__dlymetal6s6s), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlymetal6s6s.functional.v, line:34:1, endln:50:10 |vpiName:X |vpiFullName:work@sky130_fd_sc_hd__dlymetal6s6s.X |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__dlymetal6s6s.A), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__dlymetal6s6s (work@sky130_fd_sc_hd__dlymetal6s6s), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlymetal6s6s.functional.v, line:34:1, endln:50:10 + \_module_inst: work@sky130_fd_sc_hd__dlymetal6s6s (work@sky130_fd_sc_hd__dlymetal6s6s), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlymetal6s6s.functional.v, line:34:1, endln:50:10 |vpiName:A |vpiFullName:work@sky130_fd_sc_hd__dlymetal6s6s.A |vpiPort: \_port: (X), line:35:5, endln:35:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__dlymetal6s6s (work@sky130_fd_sc_hd__dlymetal6s6s), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlymetal6s6s.functional.v, line:34:1, endln:50:10 + \_module_inst: work@sky130_fd_sc_hd__dlymetal6s6s (work@sky130_fd_sc_hd__dlymetal6s6s), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlymetal6s6s.functional.v, line:34:1, endln:50:10 |vpiName:X |vpiDirection:2 |vpiLowConn: @@ -56773,7 +56773,7 @@ design: (work@sky130_fd_sc_hd__dlymetal6s6s) |vpiPort: \_port: (A), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__dlymetal6s6s (work@sky130_fd_sc_hd__dlymetal6s6s), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlymetal6s6s.functional.v, line:34:1, endln:50:10 + \_module_inst: work@sky130_fd_sc_hd__dlymetal6s6s (work@sky130_fd_sc_hd__dlymetal6s6s), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlymetal6s6s.functional.v, line:34:1, endln:50:10 |vpiName:A |vpiDirection:1 |vpiLowConn: @@ -56783,14 +56783,14 @@ design: (work@sky130_fd_sc_hd__dlymetal6s6s) |vpiTypedef: \_logic_typespec: , line:41:12, endln:41:12 |uhdmtopModules: -\_module: work@sky130_fd_sc_hd__dlymetal6s6s (work@sky130_fd_sc_hd__dlymetal6s6s), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlymetal6s6s.functional.v, line:34:1, endln:50:10 +\_module_inst: work@sky130_fd_sc_hd__dlymetal6s6s (work@sky130_fd_sc_hd__dlymetal6s6s), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlymetal6s6s.functional.v, line:34:1, endln:50:10 |vpiName:work@sky130_fd_sc_hd__dlymetal6s6s |vpiDefName:work@sky130_fd_sc_hd__dlymetal6s6s |vpiTop:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__dlymetal6s6s.buf0_out_X), line:44:10, endln:44:20 |vpiParent: - \_module: work@sky130_fd_sc_hd__dlymetal6s6s (work@sky130_fd_sc_hd__dlymetal6s6s), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlymetal6s6s.functional.v, line:34:1, endln:50:10 + \_module_inst: work@sky130_fd_sc_hd__dlymetal6s6s (work@sky130_fd_sc_hd__dlymetal6s6s), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlymetal6s6s.functional.v, line:34:1, endln:50:10 |vpiTypespec: \_logic_typespec: , line:44:5, endln:44:9 |vpiName:buf0_out_X @@ -56799,7 +56799,7 @@ design: (work@sky130_fd_sc_hd__dlymetal6s6s) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__dlymetal6s6s.X), line:35:5, endln:35:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__dlymetal6s6s (work@sky130_fd_sc_hd__dlymetal6s6s), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlymetal6s6s.functional.v, line:34:1, endln:50:10 + \_module_inst: work@sky130_fd_sc_hd__dlymetal6s6s (work@sky130_fd_sc_hd__dlymetal6s6s), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlymetal6s6s.functional.v, line:34:1, endln:50:10 |vpiTypespec: \_logic_typespec: , line:40:12, endln:40:12 |vpiName:X @@ -56807,7 +56807,7 @@ design: (work@sky130_fd_sc_hd__dlymetal6s6s) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__dlymetal6s6s.A), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__dlymetal6s6s (work@sky130_fd_sc_hd__dlymetal6s6s), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlymetal6s6s.functional.v, line:34:1, endln:50:10 + \_module_inst: work@sky130_fd_sc_hd__dlymetal6s6s (work@sky130_fd_sc_hd__dlymetal6s6s), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlymetal6s6s.functional.v, line:34:1, endln:50:10 |vpiTypespec: \_logic_typespec: , line:41:12, endln:41:12 |vpiName:A @@ -56816,7 +56816,7 @@ design: (work@sky130_fd_sc_hd__dlymetal6s6s) |vpiPort: \_port: (X), line:35:5, endln:35:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__dlymetal6s6s (work@sky130_fd_sc_hd__dlymetal6s6s), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlymetal6s6s.functional.v, line:34:1, endln:50:10 + \_module_inst: work@sky130_fd_sc_hd__dlymetal6s6s (work@sky130_fd_sc_hd__dlymetal6s6s), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlymetal6s6s.functional.v, line:34:1, endln:50:10 |vpiName:X |vpiDirection:2 |vpiLowConn: @@ -56830,7 +56830,7 @@ design: (work@sky130_fd_sc_hd__dlymetal6s6s) |vpiPort: \_port: (A), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__dlymetal6s6s (work@sky130_fd_sc_hd__dlymetal6s6s), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlymetal6s6s.functional.v, line:34:1, endln:50:10 + \_module_inst: work@sky130_fd_sc_hd__dlymetal6s6s (work@sky130_fd_sc_hd__dlymetal6s6s), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlymetal6s6s.functional.v, line:34:1, endln:50:10 |vpiName:A |vpiDirection:1 |vpiLowConn: @@ -56844,7 +56844,7 @@ design: (work@sky130_fd_sc_hd__dlymetal6s6s) |vpiPrimitive: \_gate: work@buf (work@sky130_fd_sc_hd__dlymetal6s6s.buf0), line:47:9, endln:47:43 |vpiParent: - \_module: work@sky130_fd_sc_hd__dlymetal6s6s (work@sky130_fd_sc_hd__dlymetal6s6s), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlymetal6s6s.functional.v, line:34:1, endln:50:10 + \_module_inst: work@sky130_fd_sc_hd__dlymetal6s6s (work@sky130_fd_sc_hd__dlymetal6s6s), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlymetal6s6s.functional.v, line:34:1, endln:50:10 |vpiDefName:work@buf |vpiName:buf0 |vpiFullName:work@sky130_fd_sc_hd__dlymetal6s6s.buf0 @@ -56879,7 +56879,7 @@ design: (work@sky130_fd_sc_hd__dlymetal6s6s) |vpiPrimitive: \_gate: work@buf (work@sky130_fd_sc_hd__dlymetal6s6s.buf1), line:48:9, endln:48:43 |vpiParent: - \_module: work@sky130_fd_sc_hd__dlymetal6s6s (work@sky130_fd_sc_hd__dlymetal6s6s), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlymetal6s6s.functional.v, line:34:1, endln:50:10 + \_module_inst: work@sky130_fd_sc_hd__dlymetal6s6s (work@sky130_fd_sc_hd__dlymetal6s6s), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlymetal6s6s.functional.v, line:34:1, endln:50:10 |vpiDefName:work@buf |vpiName:buf1 |vpiFullName:work@sky130_fd_sc_hd__dlymetal6s6s.buf1 @@ -56922,7 +56922,7 @@ Processing: -cd cells/cells -DUNIT_DELAY -writepp -parse -nocache -nobuiltin -no design: (work@sky130_fd_sc_hd__a311oi) |vpiName:work@sky130_fd_sc_hd__a311oi |uhdmallModules: -\_module: work@sky130_fd_sc_hd__a311oi (work@sky130_fd_sc_hd__a311oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a311oi.functional.v, line:35:1, endln:61:10 +\_module_inst: work@sky130_fd_sc_hd__a311oi (work@sky130_fd_sc_hd__a311oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a311oi.functional.v, line:35:1, endln:61:10 |vpiParent: \_design: (work@sky130_fd_sc_hd__a311oi) |vpiFullName:work@sky130_fd_sc_hd__a311oi @@ -56930,57 +56930,57 @@ design: (work@sky130_fd_sc_hd__a311oi) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a311oi.and0_out), line:53:10, endln:53:18 |vpiParent: - \_module: work@sky130_fd_sc_hd__a311oi (work@sky130_fd_sc_hd__a311oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a311oi.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__a311oi (work@sky130_fd_sc_hd__a311oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a311oi.functional.v, line:35:1, endln:61:10 |vpiName:and0_out |vpiFullName:work@sky130_fd_sc_hd__a311oi.and0_out |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a311oi.nor0_out_Y), line:54:10, endln:54:20 |vpiParent: - \_module: work@sky130_fd_sc_hd__a311oi (work@sky130_fd_sc_hd__a311oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a311oi.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__a311oi (work@sky130_fd_sc_hd__a311oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a311oi.functional.v, line:35:1, endln:61:10 |vpiName:nor0_out_Y |vpiFullName:work@sky130_fd_sc_hd__a311oi.nor0_out_Y |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a311oi.Y), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__a311oi (work@sky130_fd_sc_hd__a311oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a311oi.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__a311oi (work@sky130_fd_sc_hd__a311oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a311oi.functional.v, line:35:1, endln:61:10 |vpiName:Y |vpiFullName:work@sky130_fd_sc_hd__a311oi.Y |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a311oi.A1), line:37:5, endln:37:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a311oi (work@sky130_fd_sc_hd__a311oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a311oi.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__a311oi (work@sky130_fd_sc_hd__a311oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a311oi.functional.v, line:35:1, endln:61:10 |vpiName:A1 |vpiFullName:work@sky130_fd_sc_hd__a311oi.A1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a311oi.A2), line:38:5, endln:38:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a311oi (work@sky130_fd_sc_hd__a311oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a311oi.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__a311oi (work@sky130_fd_sc_hd__a311oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a311oi.functional.v, line:35:1, endln:61:10 |vpiName:A2 |vpiFullName:work@sky130_fd_sc_hd__a311oi.A2 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a311oi.A3), line:39:5, endln:39:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a311oi (work@sky130_fd_sc_hd__a311oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a311oi.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__a311oi (work@sky130_fd_sc_hd__a311oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a311oi.functional.v, line:35:1, endln:61:10 |vpiName:A3 |vpiFullName:work@sky130_fd_sc_hd__a311oi.A3 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a311oi.B1), line:40:5, endln:40:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a311oi (work@sky130_fd_sc_hd__a311oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a311oi.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__a311oi (work@sky130_fd_sc_hd__a311oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a311oi.functional.v, line:35:1, endln:61:10 |vpiName:B1 |vpiFullName:work@sky130_fd_sc_hd__a311oi.B1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a311oi.C1), line:41:5, endln:41:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a311oi (work@sky130_fd_sc_hd__a311oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a311oi.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__a311oi (work@sky130_fd_sc_hd__a311oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a311oi.functional.v, line:35:1, endln:61:10 |vpiName:C1 |vpiFullName:work@sky130_fd_sc_hd__a311oi.C1 |vpiPort: \_port: (Y), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__a311oi (work@sky130_fd_sc_hd__a311oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a311oi.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__a311oi (work@sky130_fd_sc_hd__a311oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a311oi.functional.v, line:35:1, endln:61:10 |vpiName:Y |vpiDirection:2 |vpiLowConn: @@ -56992,7 +56992,7 @@ design: (work@sky130_fd_sc_hd__a311oi) |vpiPort: \_port: (A1), line:37:5, endln:37:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a311oi (work@sky130_fd_sc_hd__a311oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a311oi.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__a311oi (work@sky130_fd_sc_hd__a311oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a311oi.functional.v, line:35:1, endln:61:10 |vpiName:A1 |vpiDirection:1 |vpiLowConn: @@ -57004,7 +57004,7 @@ design: (work@sky130_fd_sc_hd__a311oi) |vpiPort: \_port: (A2), line:38:5, endln:38:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a311oi (work@sky130_fd_sc_hd__a311oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a311oi.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__a311oi (work@sky130_fd_sc_hd__a311oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a311oi.functional.v, line:35:1, endln:61:10 |vpiName:A2 |vpiDirection:1 |vpiLowConn: @@ -57016,7 +57016,7 @@ design: (work@sky130_fd_sc_hd__a311oi) |vpiPort: \_port: (A3), line:39:5, endln:39:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a311oi (work@sky130_fd_sc_hd__a311oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a311oi.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__a311oi (work@sky130_fd_sc_hd__a311oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a311oi.functional.v, line:35:1, endln:61:10 |vpiName:A3 |vpiDirection:1 |vpiLowConn: @@ -57028,7 +57028,7 @@ design: (work@sky130_fd_sc_hd__a311oi) |vpiPort: \_port: (B1), line:40:5, endln:40:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a311oi (work@sky130_fd_sc_hd__a311oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a311oi.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__a311oi (work@sky130_fd_sc_hd__a311oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a311oi.functional.v, line:35:1, endln:61:10 |vpiName:B1 |vpiDirection:1 |vpiLowConn: @@ -57040,7 +57040,7 @@ design: (work@sky130_fd_sc_hd__a311oi) |vpiPort: \_port: (C1), line:41:5, endln:41:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a311oi (work@sky130_fd_sc_hd__a311oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a311oi.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__a311oi (work@sky130_fd_sc_hd__a311oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a311oi.functional.v, line:35:1, endln:61:10 |vpiName:C1 |vpiDirection:1 |vpiLowConn: @@ -57050,14 +57050,14 @@ design: (work@sky130_fd_sc_hd__a311oi) |vpiTypedef: \_logic_typespec: , line:50:12, endln:50:12 |uhdmtopModules: -\_module: work@sky130_fd_sc_hd__a311oi (work@sky130_fd_sc_hd__a311oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a311oi.functional.v, line:35:1, endln:61:10 +\_module_inst: work@sky130_fd_sc_hd__a311oi (work@sky130_fd_sc_hd__a311oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a311oi.functional.v, line:35:1, endln:61:10 |vpiName:work@sky130_fd_sc_hd__a311oi |vpiDefName:work@sky130_fd_sc_hd__a311oi |vpiTop:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a311oi.and0_out), line:53:10, endln:53:18 |vpiParent: - \_module: work@sky130_fd_sc_hd__a311oi (work@sky130_fd_sc_hd__a311oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a311oi.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__a311oi (work@sky130_fd_sc_hd__a311oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a311oi.functional.v, line:35:1, endln:61:10 |vpiTypespec: \_logic_typespec: , line:53:5, endln:53:9 |vpiName:and0_out @@ -57066,7 +57066,7 @@ design: (work@sky130_fd_sc_hd__a311oi) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a311oi.nor0_out_Y), line:54:10, endln:54:20 |vpiParent: - \_module: work@sky130_fd_sc_hd__a311oi (work@sky130_fd_sc_hd__a311oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a311oi.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__a311oi (work@sky130_fd_sc_hd__a311oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a311oi.functional.v, line:35:1, endln:61:10 |vpiTypespec: \_logic_typespec: , line:54:5, endln:54:9 |vpiName:nor0_out_Y @@ -57075,7 +57075,7 @@ design: (work@sky130_fd_sc_hd__a311oi) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a311oi.Y), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__a311oi (work@sky130_fd_sc_hd__a311oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a311oi.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__a311oi (work@sky130_fd_sc_hd__a311oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a311oi.functional.v, line:35:1, endln:61:10 |vpiTypespec: \_logic_typespec: , line:45:12, endln:45:12 |vpiName:Y @@ -57083,7 +57083,7 @@ design: (work@sky130_fd_sc_hd__a311oi) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a311oi.A1), line:37:5, endln:37:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a311oi (work@sky130_fd_sc_hd__a311oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a311oi.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__a311oi (work@sky130_fd_sc_hd__a311oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a311oi.functional.v, line:35:1, endln:61:10 |vpiTypespec: \_logic_typespec: , line:46:12, endln:46:12 |vpiName:A1 @@ -57091,7 +57091,7 @@ design: (work@sky130_fd_sc_hd__a311oi) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a311oi.A2), line:38:5, endln:38:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a311oi (work@sky130_fd_sc_hd__a311oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a311oi.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__a311oi (work@sky130_fd_sc_hd__a311oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a311oi.functional.v, line:35:1, endln:61:10 |vpiTypespec: \_logic_typespec: , line:47:12, endln:47:12 |vpiName:A2 @@ -57099,7 +57099,7 @@ design: (work@sky130_fd_sc_hd__a311oi) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a311oi.A3), line:39:5, endln:39:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a311oi (work@sky130_fd_sc_hd__a311oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a311oi.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__a311oi (work@sky130_fd_sc_hd__a311oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a311oi.functional.v, line:35:1, endln:61:10 |vpiTypespec: \_logic_typespec: , line:48:12, endln:48:12 |vpiName:A3 @@ -57107,7 +57107,7 @@ design: (work@sky130_fd_sc_hd__a311oi) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a311oi.B1), line:40:5, endln:40:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a311oi (work@sky130_fd_sc_hd__a311oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a311oi.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__a311oi (work@sky130_fd_sc_hd__a311oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a311oi.functional.v, line:35:1, endln:61:10 |vpiTypespec: \_logic_typespec: , line:49:12, endln:49:12 |vpiName:B1 @@ -57115,7 +57115,7 @@ design: (work@sky130_fd_sc_hd__a311oi) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a311oi.C1), line:41:5, endln:41:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a311oi (work@sky130_fd_sc_hd__a311oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a311oi.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__a311oi (work@sky130_fd_sc_hd__a311oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a311oi.functional.v, line:35:1, endln:61:10 |vpiTypespec: \_logic_typespec: , line:50:12, endln:50:12 |vpiName:C1 @@ -57124,7 +57124,7 @@ design: (work@sky130_fd_sc_hd__a311oi) |vpiPort: \_port: (Y), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__a311oi (work@sky130_fd_sc_hd__a311oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a311oi.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__a311oi (work@sky130_fd_sc_hd__a311oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a311oi.functional.v, line:35:1, endln:61:10 |vpiName:Y |vpiDirection:2 |vpiLowConn: @@ -57138,7 +57138,7 @@ design: (work@sky130_fd_sc_hd__a311oi) |vpiPort: \_port: (A1), line:37:5, endln:37:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a311oi (work@sky130_fd_sc_hd__a311oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a311oi.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__a311oi (work@sky130_fd_sc_hd__a311oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a311oi.functional.v, line:35:1, endln:61:10 |vpiName:A1 |vpiDirection:1 |vpiLowConn: @@ -57152,7 +57152,7 @@ design: (work@sky130_fd_sc_hd__a311oi) |vpiPort: \_port: (A2), line:38:5, endln:38:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a311oi (work@sky130_fd_sc_hd__a311oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a311oi.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__a311oi (work@sky130_fd_sc_hd__a311oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a311oi.functional.v, line:35:1, endln:61:10 |vpiName:A2 |vpiDirection:1 |vpiLowConn: @@ -57166,7 +57166,7 @@ design: (work@sky130_fd_sc_hd__a311oi) |vpiPort: \_port: (A3), line:39:5, endln:39:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a311oi (work@sky130_fd_sc_hd__a311oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a311oi.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__a311oi (work@sky130_fd_sc_hd__a311oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a311oi.functional.v, line:35:1, endln:61:10 |vpiName:A3 |vpiDirection:1 |vpiLowConn: @@ -57180,7 +57180,7 @@ design: (work@sky130_fd_sc_hd__a311oi) |vpiPort: \_port: (B1), line:40:5, endln:40:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a311oi (work@sky130_fd_sc_hd__a311oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a311oi.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__a311oi (work@sky130_fd_sc_hd__a311oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a311oi.functional.v, line:35:1, endln:61:10 |vpiName:B1 |vpiDirection:1 |vpiLowConn: @@ -57194,7 +57194,7 @@ design: (work@sky130_fd_sc_hd__a311oi) |vpiPort: \_port: (C1), line:41:5, endln:41:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a311oi (work@sky130_fd_sc_hd__a311oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a311oi.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__a311oi (work@sky130_fd_sc_hd__a311oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a311oi.functional.v, line:35:1, endln:61:10 |vpiName:C1 |vpiDirection:1 |vpiLowConn: @@ -57208,7 +57208,7 @@ design: (work@sky130_fd_sc_hd__a311oi) |vpiPrimitive: \_gate: work@and (work@sky130_fd_sc_hd__a311oi.and0), line:57:9, endln:57:44 |vpiParent: - \_module: work@sky130_fd_sc_hd__a311oi (work@sky130_fd_sc_hd__a311oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a311oi.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__a311oi (work@sky130_fd_sc_hd__a311oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a311oi.functional.v, line:35:1, endln:61:10 |vpiDefName:work@and |vpiName:and0 |vpiFullName:work@sky130_fd_sc_hd__a311oi.and0 @@ -57271,7 +57271,7 @@ design: (work@sky130_fd_sc_hd__a311oi) |vpiPrimitive: \_gate: work@nor (work@sky130_fd_sc_hd__a311oi.nor0), line:58:9, endln:58:44 |vpiParent: - \_module: work@sky130_fd_sc_hd__a311oi (work@sky130_fd_sc_hd__a311oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a311oi.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__a311oi (work@sky130_fd_sc_hd__a311oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a311oi.functional.v, line:35:1, endln:61:10 |vpiDefName:work@nor |vpiName:nor0 |vpiFullName:work@sky130_fd_sc_hd__a311oi.nor0 @@ -57334,7 +57334,7 @@ design: (work@sky130_fd_sc_hd__a311oi) |vpiPrimitive: \_gate: work@buf (work@sky130_fd_sc_hd__a311oi.buf0), line:59:9, endln:59:44 |vpiParent: - \_module: work@sky130_fd_sc_hd__a311oi (work@sky130_fd_sc_hd__a311oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a311oi.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__a311oi (work@sky130_fd_sc_hd__a311oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a311oi.functional.v, line:35:1, endln:61:10 |vpiDefName:work@buf |vpiName:buf0 |vpiFullName:work@sky130_fd_sc_hd__a311oi.buf0 @@ -57377,7 +57377,7 @@ Processing: -cd cells/cells -DUNIT_DELAY -writepp -parse -nocache -nobuiltin -no design: (work@sky130_fd_sc_hd__a31o) |vpiName:work@sky130_fd_sc_hd__a31o |uhdmallModules: -\_module: work@sky130_fd_sc_hd__a31o (work@sky130_fd_sc_hd__a31o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a31o.functional.v, line:35:1, endln:59:10 +\_module_inst: work@sky130_fd_sc_hd__a31o (work@sky130_fd_sc_hd__a31o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a31o.functional.v, line:35:1, endln:59:10 |vpiParent: \_design: (work@sky130_fd_sc_hd__a31o) |vpiFullName:work@sky130_fd_sc_hd__a31o @@ -57385,51 +57385,51 @@ design: (work@sky130_fd_sc_hd__a31o) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a31o.and0_out), line:51:10, endln:51:18 |vpiParent: - \_module: work@sky130_fd_sc_hd__a31o (work@sky130_fd_sc_hd__a31o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a31o.functional.v, line:35:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__a31o (work@sky130_fd_sc_hd__a31o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a31o.functional.v, line:35:1, endln:59:10 |vpiName:and0_out |vpiFullName:work@sky130_fd_sc_hd__a31o.and0_out |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a31o.or0_out_X), line:52:10, endln:52:19 |vpiParent: - \_module: work@sky130_fd_sc_hd__a31o (work@sky130_fd_sc_hd__a31o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a31o.functional.v, line:35:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__a31o (work@sky130_fd_sc_hd__a31o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a31o.functional.v, line:35:1, endln:59:10 |vpiName:or0_out_X |vpiFullName:work@sky130_fd_sc_hd__a31o.or0_out_X |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a31o.X), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__a31o (work@sky130_fd_sc_hd__a31o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a31o.functional.v, line:35:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__a31o (work@sky130_fd_sc_hd__a31o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a31o.functional.v, line:35:1, endln:59:10 |vpiName:X |vpiFullName:work@sky130_fd_sc_hd__a31o.X |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a31o.A1), line:37:5, endln:37:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a31o (work@sky130_fd_sc_hd__a31o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a31o.functional.v, line:35:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__a31o (work@sky130_fd_sc_hd__a31o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a31o.functional.v, line:35:1, endln:59:10 |vpiName:A1 |vpiFullName:work@sky130_fd_sc_hd__a31o.A1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a31o.A2), line:38:5, endln:38:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a31o (work@sky130_fd_sc_hd__a31o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a31o.functional.v, line:35:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__a31o (work@sky130_fd_sc_hd__a31o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a31o.functional.v, line:35:1, endln:59:10 |vpiName:A2 |vpiFullName:work@sky130_fd_sc_hd__a31o.A2 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a31o.A3), line:39:5, endln:39:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a31o (work@sky130_fd_sc_hd__a31o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a31o.functional.v, line:35:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__a31o (work@sky130_fd_sc_hd__a31o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a31o.functional.v, line:35:1, endln:59:10 |vpiName:A3 |vpiFullName:work@sky130_fd_sc_hd__a31o.A3 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a31o.B1), line:40:5, endln:40:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a31o (work@sky130_fd_sc_hd__a31o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a31o.functional.v, line:35:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__a31o (work@sky130_fd_sc_hd__a31o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a31o.functional.v, line:35:1, endln:59:10 |vpiName:B1 |vpiFullName:work@sky130_fd_sc_hd__a31o.B1 |vpiPort: \_port: (X), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__a31o (work@sky130_fd_sc_hd__a31o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a31o.functional.v, line:35:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__a31o (work@sky130_fd_sc_hd__a31o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a31o.functional.v, line:35:1, endln:59:10 |vpiName:X |vpiDirection:2 |vpiLowConn: @@ -57441,7 +57441,7 @@ design: (work@sky130_fd_sc_hd__a31o) |vpiPort: \_port: (A1), line:37:5, endln:37:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a31o (work@sky130_fd_sc_hd__a31o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a31o.functional.v, line:35:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__a31o (work@sky130_fd_sc_hd__a31o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a31o.functional.v, line:35:1, endln:59:10 |vpiName:A1 |vpiDirection:1 |vpiLowConn: @@ -57453,7 +57453,7 @@ design: (work@sky130_fd_sc_hd__a31o) |vpiPort: \_port: (A2), line:38:5, endln:38:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a31o (work@sky130_fd_sc_hd__a31o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a31o.functional.v, line:35:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__a31o (work@sky130_fd_sc_hd__a31o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a31o.functional.v, line:35:1, endln:59:10 |vpiName:A2 |vpiDirection:1 |vpiLowConn: @@ -57465,7 +57465,7 @@ design: (work@sky130_fd_sc_hd__a31o) |vpiPort: \_port: (A3), line:39:5, endln:39:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a31o (work@sky130_fd_sc_hd__a31o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a31o.functional.v, line:35:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__a31o (work@sky130_fd_sc_hd__a31o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a31o.functional.v, line:35:1, endln:59:10 |vpiName:A3 |vpiDirection:1 |vpiLowConn: @@ -57477,7 +57477,7 @@ design: (work@sky130_fd_sc_hd__a31o) |vpiPort: \_port: (B1), line:40:5, endln:40:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a31o (work@sky130_fd_sc_hd__a31o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a31o.functional.v, line:35:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__a31o (work@sky130_fd_sc_hd__a31o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a31o.functional.v, line:35:1, endln:59:10 |vpiName:B1 |vpiDirection:1 |vpiLowConn: @@ -57487,14 +57487,14 @@ design: (work@sky130_fd_sc_hd__a31o) |vpiTypedef: \_logic_typespec: , line:48:12, endln:48:12 |uhdmtopModules: -\_module: work@sky130_fd_sc_hd__a31o (work@sky130_fd_sc_hd__a31o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a31o.functional.v, line:35:1, endln:59:10 +\_module_inst: work@sky130_fd_sc_hd__a31o (work@sky130_fd_sc_hd__a31o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a31o.functional.v, line:35:1, endln:59:10 |vpiName:work@sky130_fd_sc_hd__a31o |vpiDefName:work@sky130_fd_sc_hd__a31o |vpiTop:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a31o.and0_out), line:51:10, endln:51:18 |vpiParent: - \_module: work@sky130_fd_sc_hd__a31o (work@sky130_fd_sc_hd__a31o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a31o.functional.v, line:35:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__a31o (work@sky130_fd_sc_hd__a31o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a31o.functional.v, line:35:1, endln:59:10 |vpiTypespec: \_logic_typespec: , line:51:5, endln:51:9 |vpiName:and0_out @@ -57503,7 +57503,7 @@ design: (work@sky130_fd_sc_hd__a31o) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a31o.or0_out_X), line:52:10, endln:52:19 |vpiParent: - \_module: work@sky130_fd_sc_hd__a31o (work@sky130_fd_sc_hd__a31o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a31o.functional.v, line:35:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__a31o (work@sky130_fd_sc_hd__a31o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a31o.functional.v, line:35:1, endln:59:10 |vpiTypespec: \_logic_typespec: , line:52:5, endln:52:9 |vpiName:or0_out_X @@ -57512,7 +57512,7 @@ design: (work@sky130_fd_sc_hd__a31o) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a31o.X), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__a31o (work@sky130_fd_sc_hd__a31o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a31o.functional.v, line:35:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__a31o (work@sky130_fd_sc_hd__a31o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a31o.functional.v, line:35:1, endln:59:10 |vpiTypespec: \_logic_typespec: , line:44:12, endln:44:12 |vpiName:X @@ -57520,7 +57520,7 @@ design: (work@sky130_fd_sc_hd__a31o) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a31o.A1), line:37:5, endln:37:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a31o (work@sky130_fd_sc_hd__a31o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a31o.functional.v, line:35:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__a31o (work@sky130_fd_sc_hd__a31o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a31o.functional.v, line:35:1, endln:59:10 |vpiTypespec: \_logic_typespec: , line:45:12, endln:45:12 |vpiName:A1 @@ -57528,7 +57528,7 @@ design: (work@sky130_fd_sc_hd__a31o) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a31o.A2), line:38:5, endln:38:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a31o (work@sky130_fd_sc_hd__a31o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a31o.functional.v, line:35:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__a31o (work@sky130_fd_sc_hd__a31o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a31o.functional.v, line:35:1, endln:59:10 |vpiTypespec: \_logic_typespec: , line:46:12, endln:46:12 |vpiName:A2 @@ -57536,7 +57536,7 @@ design: (work@sky130_fd_sc_hd__a31o) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a31o.A3), line:39:5, endln:39:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a31o (work@sky130_fd_sc_hd__a31o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a31o.functional.v, line:35:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__a31o (work@sky130_fd_sc_hd__a31o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a31o.functional.v, line:35:1, endln:59:10 |vpiTypespec: \_logic_typespec: , line:47:12, endln:47:12 |vpiName:A3 @@ -57544,7 +57544,7 @@ design: (work@sky130_fd_sc_hd__a31o) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a31o.B1), line:40:5, endln:40:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a31o (work@sky130_fd_sc_hd__a31o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a31o.functional.v, line:35:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__a31o (work@sky130_fd_sc_hd__a31o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a31o.functional.v, line:35:1, endln:59:10 |vpiTypespec: \_logic_typespec: , line:48:12, endln:48:12 |vpiName:B1 @@ -57553,7 +57553,7 @@ design: (work@sky130_fd_sc_hd__a31o) |vpiPort: \_port: (X), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__a31o (work@sky130_fd_sc_hd__a31o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a31o.functional.v, line:35:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__a31o (work@sky130_fd_sc_hd__a31o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a31o.functional.v, line:35:1, endln:59:10 |vpiName:X |vpiDirection:2 |vpiLowConn: @@ -57567,7 +57567,7 @@ design: (work@sky130_fd_sc_hd__a31o) |vpiPort: \_port: (A1), line:37:5, endln:37:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a31o (work@sky130_fd_sc_hd__a31o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a31o.functional.v, line:35:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__a31o (work@sky130_fd_sc_hd__a31o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a31o.functional.v, line:35:1, endln:59:10 |vpiName:A1 |vpiDirection:1 |vpiLowConn: @@ -57581,7 +57581,7 @@ design: (work@sky130_fd_sc_hd__a31o) |vpiPort: \_port: (A2), line:38:5, endln:38:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a31o (work@sky130_fd_sc_hd__a31o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a31o.functional.v, line:35:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__a31o (work@sky130_fd_sc_hd__a31o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a31o.functional.v, line:35:1, endln:59:10 |vpiName:A2 |vpiDirection:1 |vpiLowConn: @@ -57595,7 +57595,7 @@ design: (work@sky130_fd_sc_hd__a31o) |vpiPort: \_port: (A3), line:39:5, endln:39:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a31o (work@sky130_fd_sc_hd__a31o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a31o.functional.v, line:35:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__a31o (work@sky130_fd_sc_hd__a31o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a31o.functional.v, line:35:1, endln:59:10 |vpiName:A3 |vpiDirection:1 |vpiLowConn: @@ -57609,7 +57609,7 @@ design: (work@sky130_fd_sc_hd__a31o) |vpiPort: \_port: (B1), line:40:5, endln:40:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a31o (work@sky130_fd_sc_hd__a31o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a31o.functional.v, line:35:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__a31o (work@sky130_fd_sc_hd__a31o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a31o.functional.v, line:35:1, endln:59:10 |vpiName:B1 |vpiDirection:1 |vpiLowConn: @@ -57623,7 +57623,7 @@ design: (work@sky130_fd_sc_hd__a31o) |vpiPrimitive: \_gate: work@and (work@sky130_fd_sc_hd__a31o.and0), line:55:9, endln:55:42 |vpiParent: - \_module: work@sky130_fd_sc_hd__a31o (work@sky130_fd_sc_hd__a31o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a31o.functional.v, line:35:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__a31o (work@sky130_fd_sc_hd__a31o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a31o.functional.v, line:35:1, endln:59:10 |vpiDefName:work@and |vpiName:and0 |vpiFullName:work@sky130_fd_sc_hd__a31o.and0 @@ -57686,7 +57686,7 @@ design: (work@sky130_fd_sc_hd__a31o) |vpiPrimitive: \_gate: work@or (work@sky130_fd_sc_hd__a31o.or0), line:56:9, endln:56:42 |vpiParent: - \_module: work@sky130_fd_sc_hd__a31o (work@sky130_fd_sc_hd__a31o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a31o.functional.v, line:35:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__a31o (work@sky130_fd_sc_hd__a31o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a31o.functional.v, line:35:1, endln:59:10 |vpiDefName:work@or |vpiName:or0 |vpiFullName:work@sky130_fd_sc_hd__a31o.or0 @@ -57735,7 +57735,7 @@ design: (work@sky130_fd_sc_hd__a31o) |vpiPrimitive: \_gate: work@buf (work@sky130_fd_sc_hd__a31o.buf0), line:57:9, endln:57:42 |vpiParent: - \_module: work@sky130_fd_sc_hd__a31o (work@sky130_fd_sc_hd__a31o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a31o.functional.v, line:35:1, endln:59:10 + \_module_inst: work@sky130_fd_sc_hd__a31o (work@sky130_fd_sc_hd__a31o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a31o.functional.v, line:35:1, endln:59:10 |vpiDefName:work@buf |vpiName:buf0 |vpiFullName:work@sky130_fd_sc_hd__a31o.buf0 @@ -57778,7 +57778,7 @@ Processing: -cd cells/cells -DUNIT_DELAY -writepp -parse -nocache -nobuiltin -no design: (work@sky130_fd_sc_hd__nand4b) |vpiName:work@sky130_fd_sc_hd__nand4b |uhdmallModules: -\_module: work@sky130_fd_sc_hd__nand4b (work@sky130_fd_sc_hd__nand4b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand4b.functional.v, line:33:1, endln:57:10 +\_module_inst: work@sky130_fd_sc_hd__nand4b (work@sky130_fd_sc_hd__nand4b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand4b.functional.v, line:33:1, endln:57:10 |vpiParent: \_design: (work@sky130_fd_sc_hd__nand4b) |vpiFullName:work@sky130_fd_sc_hd__nand4b @@ -57786,51 +57786,51 @@ design: (work@sky130_fd_sc_hd__nand4b) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__nand4b.not0_out), line:49:10, endln:49:18 |vpiParent: - \_module: work@sky130_fd_sc_hd__nand4b (work@sky130_fd_sc_hd__nand4b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand4b.functional.v, line:33:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__nand4b (work@sky130_fd_sc_hd__nand4b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand4b.functional.v, line:33:1, endln:57:10 |vpiName:not0_out |vpiFullName:work@sky130_fd_sc_hd__nand4b.not0_out |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__nand4b.nand0_out_Y), line:50:10, endln:50:21 |vpiParent: - \_module: work@sky130_fd_sc_hd__nand4b (work@sky130_fd_sc_hd__nand4b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand4b.functional.v, line:33:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__nand4b (work@sky130_fd_sc_hd__nand4b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand4b.functional.v, line:33:1, endln:57:10 |vpiName:nand0_out_Y |vpiFullName:work@sky130_fd_sc_hd__nand4b.nand0_out_Y |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__nand4b.Y), line:34:5, endln:34:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__nand4b (work@sky130_fd_sc_hd__nand4b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand4b.functional.v, line:33:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__nand4b (work@sky130_fd_sc_hd__nand4b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand4b.functional.v, line:33:1, endln:57:10 |vpiName:Y |vpiFullName:work@sky130_fd_sc_hd__nand4b.Y |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__nand4b.A_N), line:35:5, endln:35:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__nand4b (work@sky130_fd_sc_hd__nand4b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand4b.functional.v, line:33:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__nand4b (work@sky130_fd_sc_hd__nand4b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand4b.functional.v, line:33:1, endln:57:10 |vpiName:A_N |vpiFullName:work@sky130_fd_sc_hd__nand4b.A_N |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__nand4b.B), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__nand4b (work@sky130_fd_sc_hd__nand4b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand4b.functional.v, line:33:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__nand4b (work@sky130_fd_sc_hd__nand4b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand4b.functional.v, line:33:1, endln:57:10 |vpiName:B |vpiFullName:work@sky130_fd_sc_hd__nand4b.B |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__nand4b.C), line:37:5, endln:37:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__nand4b (work@sky130_fd_sc_hd__nand4b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand4b.functional.v, line:33:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__nand4b (work@sky130_fd_sc_hd__nand4b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand4b.functional.v, line:33:1, endln:57:10 |vpiName:C |vpiFullName:work@sky130_fd_sc_hd__nand4b.C |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__nand4b.D), line:38:5, endln:38:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__nand4b (work@sky130_fd_sc_hd__nand4b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand4b.functional.v, line:33:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__nand4b (work@sky130_fd_sc_hd__nand4b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand4b.functional.v, line:33:1, endln:57:10 |vpiName:D |vpiFullName:work@sky130_fd_sc_hd__nand4b.D |vpiPort: \_port: (Y), line:34:5, endln:34:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__nand4b (work@sky130_fd_sc_hd__nand4b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand4b.functional.v, line:33:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__nand4b (work@sky130_fd_sc_hd__nand4b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand4b.functional.v, line:33:1, endln:57:10 |vpiName:Y |vpiDirection:2 |vpiLowConn: @@ -57842,7 +57842,7 @@ design: (work@sky130_fd_sc_hd__nand4b) |vpiPort: \_port: (A_N), line:35:5, endln:35:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__nand4b (work@sky130_fd_sc_hd__nand4b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand4b.functional.v, line:33:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__nand4b (work@sky130_fd_sc_hd__nand4b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand4b.functional.v, line:33:1, endln:57:10 |vpiName:A_N |vpiDirection:1 |vpiLowConn: @@ -57854,7 +57854,7 @@ design: (work@sky130_fd_sc_hd__nand4b) |vpiPort: \_port: (B), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__nand4b (work@sky130_fd_sc_hd__nand4b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand4b.functional.v, line:33:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__nand4b (work@sky130_fd_sc_hd__nand4b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand4b.functional.v, line:33:1, endln:57:10 |vpiName:B |vpiDirection:1 |vpiLowConn: @@ -57866,7 +57866,7 @@ design: (work@sky130_fd_sc_hd__nand4b) |vpiPort: \_port: (C), line:37:5, endln:37:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__nand4b (work@sky130_fd_sc_hd__nand4b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand4b.functional.v, line:33:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__nand4b (work@sky130_fd_sc_hd__nand4b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand4b.functional.v, line:33:1, endln:57:10 |vpiName:C |vpiDirection:1 |vpiLowConn: @@ -57878,7 +57878,7 @@ design: (work@sky130_fd_sc_hd__nand4b) |vpiPort: \_port: (D), line:38:5, endln:38:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__nand4b (work@sky130_fd_sc_hd__nand4b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand4b.functional.v, line:33:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__nand4b (work@sky130_fd_sc_hd__nand4b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand4b.functional.v, line:33:1, endln:57:10 |vpiName:D |vpiDirection:1 |vpiLowConn: @@ -57888,14 +57888,14 @@ design: (work@sky130_fd_sc_hd__nand4b) |vpiTypedef: \_logic_typespec: , line:46:12, endln:46:12 |uhdmtopModules: -\_module: work@sky130_fd_sc_hd__nand4b (work@sky130_fd_sc_hd__nand4b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand4b.functional.v, line:33:1, endln:57:10 +\_module_inst: work@sky130_fd_sc_hd__nand4b (work@sky130_fd_sc_hd__nand4b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand4b.functional.v, line:33:1, endln:57:10 |vpiName:work@sky130_fd_sc_hd__nand4b |vpiDefName:work@sky130_fd_sc_hd__nand4b |vpiTop:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__nand4b.not0_out), line:49:10, endln:49:18 |vpiParent: - \_module: work@sky130_fd_sc_hd__nand4b (work@sky130_fd_sc_hd__nand4b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand4b.functional.v, line:33:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__nand4b (work@sky130_fd_sc_hd__nand4b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand4b.functional.v, line:33:1, endln:57:10 |vpiTypespec: \_logic_typespec: , line:49:5, endln:49:9 |vpiName:not0_out @@ -57904,7 +57904,7 @@ design: (work@sky130_fd_sc_hd__nand4b) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__nand4b.nand0_out_Y), line:50:10, endln:50:21 |vpiParent: - \_module: work@sky130_fd_sc_hd__nand4b (work@sky130_fd_sc_hd__nand4b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand4b.functional.v, line:33:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__nand4b (work@sky130_fd_sc_hd__nand4b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand4b.functional.v, line:33:1, endln:57:10 |vpiTypespec: \_logic_typespec: , line:50:5, endln:50:9 |vpiName:nand0_out_Y @@ -57913,7 +57913,7 @@ design: (work@sky130_fd_sc_hd__nand4b) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__nand4b.Y), line:34:5, endln:34:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__nand4b (work@sky130_fd_sc_hd__nand4b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand4b.functional.v, line:33:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__nand4b (work@sky130_fd_sc_hd__nand4b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand4b.functional.v, line:33:1, endln:57:10 |vpiTypespec: \_logic_typespec: , line:42:12, endln:42:12 |vpiName:Y @@ -57921,7 +57921,7 @@ design: (work@sky130_fd_sc_hd__nand4b) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__nand4b.A_N), line:35:5, endln:35:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__nand4b (work@sky130_fd_sc_hd__nand4b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand4b.functional.v, line:33:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__nand4b (work@sky130_fd_sc_hd__nand4b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand4b.functional.v, line:33:1, endln:57:10 |vpiTypespec: \_logic_typespec: , line:43:12, endln:43:12 |vpiName:A_N @@ -57929,7 +57929,7 @@ design: (work@sky130_fd_sc_hd__nand4b) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__nand4b.B), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__nand4b (work@sky130_fd_sc_hd__nand4b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand4b.functional.v, line:33:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__nand4b (work@sky130_fd_sc_hd__nand4b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand4b.functional.v, line:33:1, endln:57:10 |vpiTypespec: \_logic_typespec: , line:44:12, endln:44:12 |vpiName:B @@ -57937,7 +57937,7 @@ design: (work@sky130_fd_sc_hd__nand4b) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__nand4b.C), line:37:5, endln:37:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__nand4b (work@sky130_fd_sc_hd__nand4b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand4b.functional.v, line:33:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__nand4b (work@sky130_fd_sc_hd__nand4b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand4b.functional.v, line:33:1, endln:57:10 |vpiTypespec: \_logic_typespec: , line:45:12, endln:45:12 |vpiName:C @@ -57945,7 +57945,7 @@ design: (work@sky130_fd_sc_hd__nand4b) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__nand4b.D), line:38:5, endln:38:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__nand4b (work@sky130_fd_sc_hd__nand4b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand4b.functional.v, line:33:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__nand4b (work@sky130_fd_sc_hd__nand4b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand4b.functional.v, line:33:1, endln:57:10 |vpiTypespec: \_logic_typespec: , line:46:12, endln:46:12 |vpiName:D @@ -57954,7 +57954,7 @@ design: (work@sky130_fd_sc_hd__nand4b) |vpiPort: \_port: (Y), line:34:5, endln:34:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__nand4b (work@sky130_fd_sc_hd__nand4b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand4b.functional.v, line:33:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__nand4b (work@sky130_fd_sc_hd__nand4b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand4b.functional.v, line:33:1, endln:57:10 |vpiName:Y |vpiDirection:2 |vpiLowConn: @@ -57968,7 +57968,7 @@ design: (work@sky130_fd_sc_hd__nand4b) |vpiPort: \_port: (A_N), line:35:5, endln:35:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__nand4b (work@sky130_fd_sc_hd__nand4b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand4b.functional.v, line:33:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__nand4b (work@sky130_fd_sc_hd__nand4b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand4b.functional.v, line:33:1, endln:57:10 |vpiName:A_N |vpiDirection:1 |vpiLowConn: @@ -57982,7 +57982,7 @@ design: (work@sky130_fd_sc_hd__nand4b) |vpiPort: \_port: (B), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__nand4b (work@sky130_fd_sc_hd__nand4b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand4b.functional.v, line:33:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__nand4b (work@sky130_fd_sc_hd__nand4b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand4b.functional.v, line:33:1, endln:57:10 |vpiName:B |vpiDirection:1 |vpiLowConn: @@ -57996,7 +57996,7 @@ design: (work@sky130_fd_sc_hd__nand4b) |vpiPort: \_port: (C), line:37:5, endln:37:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__nand4b (work@sky130_fd_sc_hd__nand4b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand4b.functional.v, line:33:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__nand4b (work@sky130_fd_sc_hd__nand4b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand4b.functional.v, line:33:1, endln:57:10 |vpiName:C |vpiDirection:1 |vpiLowConn: @@ -58010,7 +58010,7 @@ design: (work@sky130_fd_sc_hd__nand4b) |vpiPort: \_port: (D), line:38:5, endln:38:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__nand4b (work@sky130_fd_sc_hd__nand4b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand4b.functional.v, line:33:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__nand4b (work@sky130_fd_sc_hd__nand4b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand4b.functional.v, line:33:1, endln:57:10 |vpiName:D |vpiDirection:1 |vpiLowConn: @@ -58024,7 +58024,7 @@ design: (work@sky130_fd_sc_hd__nand4b) |vpiPrimitive: \_gate: work@not (work@sky130_fd_sc_hd__nand4b.not0), line:53:10, endln:53:48 |vpiParent: - \_module: work@sky130_fd_sc_hd__nand4b (work@sky130_fd_sc_hd__nand4b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand4b.functional.v, line:33:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__nand4b (work@sky130_fd_sc_hd__nand4b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand4b.functional.v, line:33:1, endln:57:10 |vpiDefName:work@not |vpiName:not0 |vpiFullName:work@sky130_fd_sc_hd__nand4b.not0 @@ -58059,7 +58059,7 @@ design: (work@sky130_fd_sc_hd__nand4b) |vpiPrimitive: \_gate: work@nand (work@sky130_fd_sc_hd__nand4b.nand0), line:54:10, endln:54:48 |vpiParent: - \_module: work@sky130_fd_sc_hd__nand4b (work@sky130_fd_sc_hd__nand4b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand4b.functional.v, line:33:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__nand4b (work@sky130_fd_sc_hd__nand4b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand4b.functional.v, line:33:1, endln:57:10 |vpiDefName:work@nand |vpiName:nand0 |vpiFullName:work@sky130_fd_sc_hd__nand4b.nand0 @@ -58136,7 +58136,7 @@ design: (work@sky130_fd_sc_hd__nand4b) |vpiPrimitive: \_gate: work@buf (work@sky130_fd_sc_hd__nand4b.buf0), line:55:10, endln:55:48 |vpiParent: - \_module: work@sky130_fd_sc_hd__nand4b (work@sky130_fd_sc_hd__nand4b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand4b.functional.v, line:33:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__nand4b (work@sky130_fd_sc_hd__nand4b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand4b.functional.v, line:33:1, endln:57:10 |vpiDefName:work@buf |vpiName:buf0 |vpiFullName:work@sky130_fd_sc_hd__nand4b.buf0 @@ -58179,7 +58179,7 @@ Processing: -cd cells/cells -DUNIT_DELAY -writepp -parse -nocache -nobuiltin -no design: (work@sky130_fd_sc_hd__lpflow_isobufsrckapwr) |vpiName:work@sky130_fd_sc_hd__lpflow_isobufsrckapwr |uhdmallModules: -\_module: work@sky130_fd_sc_hd__lpflow_isobufsrckapwr (work@sky130_fd_sc_hd__lpflow_isobufsrckapwr), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_isobufsrckapwr.functional.v, line:36:1, endln:56:10 +\_module_inst: work@sky130_fd_sc_hd__lpflow_isobufsrckapwr (work@sky130_fd_sc_hd__lpflow_isobufsrckapwr), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_isobufsrckapwr.functional.v, line:36:1, endln:56:10 |vpiParent: \_design: (work@sky130_fd_sc_hd__lpflow_isobufsrckapwr) |vpiFullName:work@sky130_fd_sc_hd__lpflow_isobufsrckapwr @@ -58187,39 +58187,39 @@ design: (work@sky130_fd_sc_hd__lpflow_isobufsrckapwr) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__lpflow_isobufsrckapwr.not0_out), line:48:10, endln:48:18 |vpiParent: - \_module: work@sky130_fd_sc_hd__lpflow_isobufsrckapwr (work@sky130_fd_sc_hd__lpflow_isobufsrckapwr), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_isobufsrckapwr.functional.v, line:36:1, endln:56:10 + \_module_inst: work@sky130_fd_sc_hd__lpflow_isobufsrckapwr (work@sky130_fd_sc_hd__lpflow_isobufsrckapwr), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_isobufsrckapwr.functional.v, line:36:1, endln:56:10 |vpiName:not0_out |vpiFullName:work@sky130_fd_sc_hd__lpflow_isobufsrckapwr.not0_out |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__lpflow_isobufsrckapwr.and0_out_X), line:49:10, endln:49:20 |vpiParent: - \_module: work@sky130_fd_sc_hd__lpflow_isobufsrckapwr (work@sky130_fd_sc_hd__lpflow_isobufsrckapwr), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_isobufsrckapwr.functional.v, line:36:1, endln:56:10 + \_module_inst: work@sky130_fd_sc_hd__lpflow_isobufsrckapwr (work@sky130_fd_sc_hd__lpflow_isobufsrckapwr), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_isobufsrckapwr.functional.v, line:36:1, endln:56:10 |vpiName:and0_out_X |vpiFullName:work@sky130_fd_sc_hd__lpflow_isobufsrckapwr.and0_out_X |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__lpflow_isobufsrckapwr.X), line:37:5, endln:37:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__lpflow_isobufsrckapwr (work@sky130_fd_sc_hd__lpflow_isobufsrckapwr), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_isobufsrckapwr.functional.v, line:36:1, endln:56:10 + \_module_inst: work@sky130_fd_sc_hd__lpflow_isobufsrckapwr (work@sky130_fd_sc_hd__lpflow_isobufsrckapwr), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_isobufsrckapwr.functional.v, line:36:1, endln:56:10 |vpiName:X |vpiFullName:work@sky130_fd_sc_hd__lpflow_isobufsrckapwr.X |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__lpflow_isobufsrckapwr.SLEEP), line:38:5, endln:38:10 |vpiParent: - \_module: work@sky130_fd_sc_hd__lpflow_isobufsrckapwr (work@sky130_fd_sc_hd__lpflow_isobufsrckapwr), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_isobufsrckapwr.functional.v, line:36:1, endln:56:10 + \_module_inst: work@sky130_fd_sc_hd__lpflow_isobufsrckapwr (work@sky130_fd_sc_hd__lpflow_isobufsrckapwr), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_isobufsrckapwr.functional.v, line:36:1, endln:56:10 |vpiName:SLEEP |vpiFullName:work@sky130_fd_sc_hd__lpflow_isobufsrckapwr.SLEEP |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__lpflow_isobufsrckapwr.A), line:39:5, endln:39:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__lpflow_isobufsrckapwr (work@sky130_fd_sc_hd__lpflow_isobufsrckapwr), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_isobufsrckapwr.functional.v, line:36:1, endln:56:10 + \_module_inst: work@sky130_fd_sc_hd__lpflow_isobufsrckapwr (work@sky130_fd_sc_hd__lpflow_isobufsrckapwr), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_isobufsrckapwr.functional.v, line:36:1, endln:56:10 |vpiName:A |vpiFullName:work@sky130_fd_sc_hd__lpflow_isobufsrckapwr.A |vpiPort: \_port: (X), line:37:5, endln:37:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__lpflow_isobufsrckapwr (work@sky130_fd_sc_hd__lpflow_isobufsrckapwr), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_isobufsrckapwr.functional.v, line:36:1, endln:56:10 + \_module_inst: work@sky130_fd_sc_hd__lpflow_isobufsrckapwr (work@sky130_fd_sc_hd__lpflow_isobufsrckapwr), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_isobufsrckapwr.functional.v, line:36:1, endln:56:10 |vpiName:X |vpiDirection:2 |vpiLowConn: @@ -58231,7 +58231,7 @@ design: (work@sky130_fd_sc_hd__lpflow_isobufsrckapwr) |vpiPort: \_port: (SLEEP), line:38:5, endln:38:10 |vpiParent: - \_module: work@sky130_fd_sc_hd__lpflow_isobufsrckapwr (work@sky130_fd_sc_hd__lpflow_isobufsrckapwr), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_isobufsrckapwr.functional.v, line:36:1, endln:56:10 + \_module_inst: work@sky130_fd_sc_hd__lpflow_isobufsrckapwr (work@sky130_fd_sc_hd__lpflow_isobufsrckapwr), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_isobufsrckapwr.functional.v, line:36:1, endln:56:10 |vpiName:SLEEP |vpiDirection:1 |vpiLowConn: @@ -58243,7 +58243,7 @@ design: (work@sky130_fd_sc_hd__lpflow_isobufsrckapwr) |vpiPort: \_port: (A), line:39:5, endln:39:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__lpflow_isobufsrckapwr (work@sky130_fd_sc_hd__lpflow_isobufsrckapwr), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_isobufsrckapwr.functional.v, line:36:1, endln:56:10 + \_module_inst: work@sky130_fd_sc_hd__lpflow_isobufsrckapwr (work@sky130_fd_sc_hd__lpflow_isobufsrckapwr), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_isobufsrckapwr.functional.v, line:36:1, endln:56:10 |vpiName:A |vpiDirection:1 |vpiLowConn: @@ -58253,14 +58253,14 @@ design: (work@sky130_fd_sc_hd__lpflow_isobufsrckapwr) |vpiTypedef: \_logic_typespec: , line:45:12, endln:45:12 |uhdmtopModules: -\_module: work@sky130_fd_sc_hd__lpflow_isobufsrckapwr (work@sky130_fd_sc_hd__lpflow_isobufsrckapwr), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_isobufsrckapwr.functional.v, line:36:1, endln:56:10 +\_module_inst: work@sky130_fd_sc_hd__lpflow_isobufsrckapwr (work@sky130_fd_sc_hd__lpflow_isobufsrckapwr), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_isobufsrckapwr.functional.v, line:36:1, endln:56:10 |vpiName:work@sky130_fd_sc_hd__lpflow_isobufsrckapwr |vpiDefName:work@sky130_fd_sc_hd__lpflow_isobufsrckapwr |vpiTop:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__lpflow_isobufsrckapwr.not0_out), line:48:10, endln:48:18 |vpiParent: - \_module: work@sky130_fd_sc_hd__lpflow_isobufsrckapwr (work@sky130_fd_sc_hd__lpflow_isobufsrckapwr), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_isobufsrckapwr.functional.v, line:36:1, endln:56:10 + \_module_inst: work@sky130_fd_sc_hd__lpflow_isobufsrckapwr (work@sky130_fd_sc_hd__lpflow_isobufsrckapwr), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_isobufsrckapwr.functional.v, line:36:1, endln:56:10 |vpiTypespec: \_logic_typespec: , line:48:5, endln:48:9 |vpiName:not0_out @@ -58269,7 +58269,7 @@ design: (work@sky130_fd_sc_hd__lpflow_isobufsrckapwr) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__lpflow_isobufsrckapwr.and0_out_X), line:49:10, endln:49:20 |vpiParent: - \_module: work@sky130_fd_sc_hd__lpflow_isobufsrckapwr (work@sky130_fd_sc_hd__lpflow_isobufsrckapwr), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_isobufsrckapwr.functional.v, line:36:1, endln:56:10 + \_module_inst: work@sky130_fd_sc_hd__lpflow_isobufsrckapwr (work@sky130_fd_sc_hd__lpflow_isobufsrckapwr), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_isobufsrckapwr.functional.v, line:36:1, endln:56:10 |vpiTypespec: \_logic_typespec: , line:49:5, endln:49:9 |vpiName:and0_out_X @@ -58278,7 +58278,7 @@ design: (work@sky130_fd_sc_hd__lpflow_isobufsrckapwr) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__lpflow_isobufsrckapwr.X), line:37:5, endln:37:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__lpflow_isobufsrckapwr (work@sky130_fd_sc_hd__lpflow_isobufsrckapwr), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_isobufsrckapwr.functional.v, line:36:1, endln:56:10 + \_module_inst: work@sky130_fd_sc_hd__lpflow_isobufsrckapwr (work@sky130_fd_sc_hd__lpflow_isobufsrckapwr), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_isobufsrckapwr.functional.v, line:36:1, endln:56:10 |vpiTypespec: \_logic_typespec: , line:43:12, endln:43:12 |vpiName:X @@ -58286,7 +58286,7 @@ design: (work@sky130_fd_sc_hd__lpflow_isobufsrckapwr) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__lpflow_isobufsrckapwr.SLEEP), line:38:5, endln:38:10 |vpiParent: - \_module: work@sky130_fd_sc_hd__lpflow_isobufsrckapwr (work@sky130_fd_sc_hd__lpflow_isobufsrckapwr), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_isobufsrckapwr.functional.v, line:36:1, endln:56:10 + \_module_inst: work@sky130_fd_sc_hd__lpflow_isobufsrckapwr (work@sky130_fd_sc_hd__lpflow_isobufsrckapwr), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_isobufsrckapwr.functional.v, line:36:1, endln:56:10 |vpiTypespec: \_logic_typespec: , line:44:12, endln:44:12 |vpiName:SLEEP @@ -58294,7 +58294,7 @@ design: (work@sky130_fd_sc_hd__lpflow_isobufsrckapwr) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__lpflow_isobufsrckapwr.A), line:39:5, endln:39:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__lpflow_isobufsrckapwr (work@sky130_fd_sc_hd__lpflow_isobufsrckapwr), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_isobufsrckapwr.functional.v, line:36:1, endln:56:10 + \_module_inst: work@sky130_fd_sc_hd__lpflow_isobufsrckapwr (work@sky130_fd_sc_hd__lpflow_isobufsrckapwr), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_isobufsrckapwr.functional.v, line:36:1, endln:56:10 |vpiTypespec: \_logic_typespec: , line:45:12, endln:45:12 |vpiName:A @@ -58303,7 +58303,7 @@ design: (work@sky130_fd_sc_hd__lpflow_isobufsrckapwr) |vpiPort: \_port: (X), line:37:5, endln:37:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__lpflow_isobufsrckapwr (work@sky130_fd_sc_hd__lpflow_isobufsrckapwr), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_isobufsrckapwr.functional.v, line:36:1, endln:56:10 + \_module_inst: work@sky130_fd_sc_hd__lpflow_isobufsrckapwr (work@sky130_fd_sc_hd__lpflow_isobufsrckapwr), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_isobufsrckapwr.functional.v, line:36:1, endln:56:10 |vpiName:X |vpiDirection:2 |vpiLowConn: @@ -58317,7 +58317,7 @@ design: (work@sky130_fd_sc_hd__lpflow_isobufsrckapwr) |vpiPort: \_port: (SLEEP), line:38:5, endln:38:10 |vpiParent: - \_module: work@sky130_fd_sc_hd__lpflow_isobufsrckapwr (work@sky130_fd_sc_hd__lpflow_isobufsrckapwr), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_isobufsrckapwr.functional.v, line:36:1, endln:56:10 + \_module_inst: work@sky130_fd_sc_hd__lpflow_isobufsrckapwr (work@sky130_fd_sc_hd__lpflow_isobufsrckapwr), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_isobufsrckapwr.functional.v, line:36:1, endln:56:10 |vpiName:SLEEP |vpiDirection:1 |vpiLowConn: @@ -58331,7 +58331,7 @@ design: (work@sky130_fd_sc_hd__lpflow_isobufsrckapwr) |vpiPort: \_port: (A), line:39:5, endln:39:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__lpflow_isobufsrckapwr (work@sky130_fd_sc_hd__lpflow_isobufsrckapwr), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_isobufsrckapwr.functional.v, line:36:1, endln:56:10 + \_module_inst: work@sky130_fd_sc_hd__lpflow_isobufsrckapwr (work@sky130_fd_sc_hd__lpflow_isobufsrckapwr), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_isobufsrckapwr.functional.v, line:36:1, endln:56:10 |vpiName:A |vpiDirection:1 |vpiLowConn: @@ -58345,7 +58345,7 @@ design: (work@sky130_fd_sc_hd__lpflow_isobufsrckapwr) |vpiPrimitive: \_gate: work@not (work@sky130_fd_sc_hd__lpflow_isobufsrckapwr.not0), line:52:9, endln:52:43 |vpiParent: - \_module: work@sky130_fd_sc_hd__lpflow_isobufsrckapwr (work@sky130_fd_sc_hd__lpflow_isobufsrckapwr), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_isobufsrckapwr.functional.v, line:36:1, endln:56:10 + \_module_inst: work@sky130_fd_sc_hd__lpflow_isobufsrckapwr (work@sky130_fd_sc_hd__lpflow_isobufsrckapwr), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_isobufsrckapwr.functional.v, line:36:1, endln:56:10 |vpiDefName:work@not |vpiName:not0 |vpiFullName:work@sky130_fd_sc_hd__lpflow_isobufsrckapwr.not0 @@ -58380,7 +58380,7 @@ design: (work@sky130_fd_sc_hd__lpflow_isobufsrckapwr) |vpiPrimitive: \_gate: work@and (work@sky130_fd_sc_hd__lpflow_isobufsrckapwr.and0), line:53:9, endln:53:43 |vpiParent: - \_module: work@sky130_fd_sc_hd__lpflow_isobufsrckapwr (work@sky130_fd_sc_hd__lpflow_isobufsrckapwr), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_isobufsrckapwr.functional.v, line:36:1, endln:56:10 + \_module_inst: work@sky130_fd_sc_hd__lpflow_isobufsrckapwr (work@sky130_fd_sc_hd__lpflow_isobufsrckapwr), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_isobufsrckapwr.functional.v, line:36:1, endln:56:10 |vpiDefName:work@and |vpiName:and0 |vpiFullName:work@sky130_fd_sc_hd__lpflow_isobufsrckapwr.and0 @@ -58429,7 +58429,7 @@ design: (work@sky130_fd_sc_hd__lpflow_isobufsrckapwr) |vpiPrimitive: \_gate: work@buf (work@sky130_fd_sc_hd__lpflow_isobufsrckapwr.buf0), line:54:9, endln:54:43 |vpiParent: - \_module: work@sky130_fd_sc_hd__lpflow_isobufsrckapwr (work@sky130_fd_sc_hd__lpflow_isobufsrckapwr), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_isobufsrckapwr.functional.v, line:36:1, endln:56:10 + \_module_inst: work@sky130_fd_sc_hd__lpflow_isobufsrckapwr (work@sky130_fd_sc_hd__lpflow_isobufsrckapwr), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_isobufsrckapwr.functional.v, line:36:1, endln:56:10 |vpiDefName:work@buf |vpiName:buf0 |vpiFullName:work@sky130_fd_sc_hd__lpflow_isobufsrckapwr.buf0 @@ -58472,7 +58472,7 @@ Processing: -cd cells/cells -DUNIT_DELAY -writepp -parse -nocache -nobuiltin -no design: (work@sky130_fd_sc_hd__a21boi) |vpiName:work@sky130_fd_sc_hd__a21boi |uhdmallModules: -\_module: work@sky130_fd_sc_hd__a21boi (work@sky130_fd_sc_hd__a21boi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a21boi.functional.v, line:36:1, endln:60:10 +\_module_inst: work@sky130_fd_sc_hd__a21boi (work@sky130_fd_sc_hd__a21boi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a21boi.functional.v, line:36:1, endln:60:10 |vpiParent: \_design: (work@sky130_fd_sc_hd__a21boi) |vpiFullName:work@sky130_fd_sc_hd__a21boi @@ -58480,52 +58480,52 @@ design: (work@sky130_fd_sc_hd__a21boi) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a21boi.b), line:50:10, endln:50:11 |vpiParent: - \_module: work@sky130_fd_sc_hd__a21boi (work@sky130_fd_sc_hd__a21boi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a21boi.functional.v, line:36:1, endln:60:10 + \_module_inst: work@sky130_fd_sc_hd__a21boi (work@sky130_fd_sc_hd__a21boi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a21boi.functional.v, line:36:1, endln:60:10 |vpiName:b |vpiFullName:work@sky130_fd_sc_hd__a21boi.b |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a21boi.and0_out), line:51:10, endln:51:18 |vpiParent: - \_module: work@sky130_fd_sc_hd__a21boi (work@sky130_fd_sc_hd__a21boi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a21boi.functional.v, line:36:1, endln:60:10 + \_module_inst: work@sky130_fd_sc_hd__a21boi (work@sky130_fd_sc_hd__a21boi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a21boi.functional.v, line:36:1, endln:60:10 |vpiName:and0_out |vpiFullName:work@sky130_fd_sc_hd__a21boi.and0_out |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a21boi.nor0_out_Y), line:52:10, endln:52:20 |vpiParent: - \_module: work@sky130_fd_sc_hd__a21boi (work@sky130_fd_sc_hd__a21boi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a21boi.functional.v, line:36:1, endln:60:10 + \_module_inst: work@sky130_fd_sc_hd__a21boi (work@sky130_fd_sc_hd__a21boi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a21boi.functional.v, line:36:1, endln:60:10 |vpiName:nor0_out_Y |vpiFullName:work@sky130_fd_sc_hd__a21boi.nor0_out_Y |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a21boi.Y), line:37:5, endln:37:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__a21boi (work@sky130_fd_sc_hd__a21boi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a21boi.functional.v, line:36:1, endln:60:10 + \_module_inst: work@sky130_fd_sc_hd__a21boi (work@sky130_fd_sc_hd__a21boi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a21boi.functional.v, line:36:1, endln:60:10 |vpiName:Y |vpiFullName:work@sky130_fd_sc_hd__a21boi.Y |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a21boi.A1), line:38:5, endln:38:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a21boi (work@sky130_fd_sc_hd__a21boi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a21boi.functional.v, line:36:1, endln:60:10 + \_module_inst: work@sky130_fd_sc_hd__a21boi (work@sky130_fd_sc_hd__a21boi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a21boi.functional.v, line:36:1, endln:60:10 |vpiName:A1 |vpiFullName:work@sky130_fd_sc_hd__a21boi.A1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a21boi.A2), line:39:5, endln:39:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a21boi (work@sky130_fd_sc_hd__a21boi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a21boi.functional.v, line:36:1, endln:60:10 + \_module_inst: work@sky130_fd_sc_hd__a21boi (work@sky130_fd_sc_hd__a21boi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a21boi.functional.v, line:36:1, endln:60:10 |vpiName:A2 |vpiFullName:work@sky130_fd_sc_hd__a21boi.A2 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a21boi.B1_N), line:40:5, endln:40:9 |vpiParent: - \_module: work@sky130_fd_sc_hd__a21boi (work@sky130_fd_sc_hd__a21boi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a21boi.functional.v, line:36:1, endln:60:10 + \_module_inst: work@sky130_fd_sc_hd__a21boi (work@sky130_fd_sc_hd__a21boi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a21boi.functional.v, line:36:1, endln:60:10 |vpiName:B1_N |vpiFullName:work@sky130_fd_sc_hd__a21boi.B1_N |vpiPort: \_port: (Y), line:37:5, endln:37:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__a21boi (work@sky130_fd_sc_hd__a21boi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a21boi.functional.v, line:36:1, endln:60:10 + \_module_inst: work@sky130_fd_sc_hd__a21boi (work@sky130_fd_sc_hd__a21boi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a21boi.functional.v, line:36:1, endln:60:10 |vpiName:Y |vpiDirection:2 |vpiLowConn: @@ -58537,7 +58537,7 @@ design: (work@sky130_fd_sc_hd__a21boi) |vpiPort: \_port: (A1), line:38:5, endln:38:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a21boi (work@sky130_fd_sc_hd__a21boi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a21boi.functional.v, line:36:1, endln:60:10 + \_module_inst: work@sky130_fd_sc_hd__a21boi (work@sky130_fd_sc_hd__a21boi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a21boi.functional.v, line:36:1, endln:60:10 |vpiName:A1 |vpiDirection:1 |vpiLowConn: @@ -58549,7 +58549,7 @@ design: (work@sky130_fd_sc_hd__a21boi) |vpiPort: \_port: (A2), line:39:5, endln:39:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a21boi (work@sky130_fd_sc_hd__a21boi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a21boi.functional.v, line:36:1, endln:60:10 + \_module_inst: work@sky130_fd_sc_hd__a21boi (work@sky130_fd_sc_hd__a21boi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a21boi.functional.v, line:36:1, endln:60:10 |vpiName:A2 |vpiDirection:1 |vpiLowConn: @@ -58561,7 +58561,7 @@ design: (work@sky130_fd_sc_hd__a21boi) |vpiPort: \_port: (B1_N), line:40:5, endln:40:9 |vpiParent: - \_module: work@sky130_fd_sc_hd__a21boi (work@sky130_fd_sc_hd__a21boi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a21boi.functional.v, line:36:1, endln:60:10 + \_module_inst: work@sky130_fd_sc_hd__a21boi (work@sky130_fd_sc_hd__a21boi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a21boi.functional.v, line:36:1, endln:60:10 |vpiName:B1_N |vpiDirection:1 |vpiLowConn: @@ -58571,14 +58571,14 @@ design: (work@sky130_fd_sc_hd__a21boi) |vpiTypedef: \_logic_typespec: , line:47:12, endln:47:12 |uhdmtopModules: -\_module: work@sky130_fd_sc_hd__a21boi (work@sky130_fd_sc_hd__a21boi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a21boi.functional.v, line:36:1, endln:60:10 +\_module_inst: work@sky130_fd_sc_hd__a21boi (work@sky130_fd_sc_hd__a21boi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a21boi.functional.v, line:36:1, endln:60:10 |vpiName:work@sky130_fd_sc_hd__a21boi |vpiDefName:work@sky130_fd_sc_hd__a21boi |vpiTop:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a21boi.b), line:50:10, endln:50:11 |vpiParent: - \_module: work@sky130_fd_sc_hd__a21boi (work@sky130_fd_sc_hd__a21boi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a21boi.functional.v, line:36:1, endln:60:10 + \_module_inst: work@sky130_fd_sc_hd__a21boi (work@sky130_fd_sc_hd__a21boi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a21boi.functional.v, line:36:1, endln:60:10 |vpiTypespec: \_logic_typespec: , line:50:5, endln:50:9 |vpiName:b @@ -58587,7 +58587,7 @@ design: (work@sky130_fd_sc_hd__a21boi) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a21boi.and0_out), line:51:10, endln:51:18 |vpiParent: - \_module: work@sky130_fd_sc_hd__a21boi (work@sky130_fd_sc_hd__a21boi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a21boi.functional.v, line:36:1, endln:60:10 + \_module_inst: work@sky130_fd_sc_hd__a21boi (work@sky130_fd_sc_hd__a21boi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a21boi.functional.v, line:36:1, endln:60:10 |vpiTypespec: \_logic_typespec: , line:51:5, endln:51:9 |vpiName:and0_out @@ -58596,7 +58596,7 @@ design: (work@sky130_fd_sc_hd__a21boi) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a21boi.nor0_out_Y), line:52:10, endln:52:20 |vpiParent: - \_module: work@sky130_fd_sc_hd__a21boi (work@sky130_fd_sc_hd__a21boi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a21boi.functional.v, line:36:1, endln:60:10 + \_module_inst: work@sky130_fd_sc_hd__a21boi (work@sky130_fd_sc_hd__a21boi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a21boi.functional.v, line:36:1, endln:60:10 |vpiTypespec: \_logic_typespec: , line:52:5, endln:52:9 |vpiName:nor0_out_Y @@ -58605,7 +58605,7 @@ design: (work@sky130_fd_sc_hd__a21boi) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a21boi.Y), line:37:5, endln:37:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__a21boi (work@sky130_fd_sc_hd__a21boi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a21boi.functional.v, line:36:1, endln:60:10 + \_module_inst: work@sky130_fd_sc_hd__a21boi (work@sky130_fd_sc_hd__a21boi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a21boi.functional.v, line:36:1, endln:60:10 |vpiTypespec: \_logic_typespec: , line:44:12, endln:44:12 |vpiName:Y @@ -58613,7 +58613,7 @@ design: (work@sky130_fd_sc_hd__a21boi) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a21boi.A1), line:38:5, endln:38:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a21boi (work@sky130_fd_sc_hd__a21boi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a21boi.functional.v, line:36:1, endln:60:10 + \_module_inst: work@sky130_fd_sc_hd__a21boi (work@sky130_fd_sc_hd__a21boi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a21boi.functional.v, line:36:1, endln:60:10 |vpiTypespec: \_logic_typespec: , line:45:12, endln:45:12 |vpiName:A1 @@ -58621,7 +58621,7 @@ design: (work@sky130_fd_sc_hd__a21boi) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a21boi.A2), line:39:5, endln:39:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a21boi (work@sky130_fd_sc_hd__a21boi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a21boi.functional.v, line:36:1, endln:60:10 + \_module_inst: work@sky130_fd_sc_hd__a21boi (work@sky130_fd_sc_hd__a21boi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a21boi.functional.v, line:36:1, endln:60:10 |vpiTypespec: \_logic_typespec: , line:46:12, endln:46:12 |vpiName:A2 @@ -58629,7 +58629,7 @@ design: (work@sky130_fd_sc_hd__a21boi) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a21boi.B1_N), line:40:5, endln:40:9 |vpiParent: - \_module: work@sky130_fd_sc_hd__a21boi (work@sky130_fd_sc_hd__a21boi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a21boi.functional.v, line:36:1, endln:60:10 + \_module_inst: work@sky130_fd_sc_hd__a21boi (work@sky130_fd_sc_hd__a21boi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a21boi.functional.v, line:36:1, endln:60:10 |vpiTypespec: \_logic_typespec: , line:47:12, endln:47:12 |vpiName:B1_N @@ -58638,7 +58638,7 @@ design: (work@sky130_fd_sc_hd__a21boi) |vpiPort: \_port: (Y), line:37:5, endln:37:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__a21boi (work@sky130_fd_sc_hd__a21boi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a21boi.functional.v, line:36:1, endln:60:10 + \_module_inst: work@sky130_fd_sc_hd__a21boi (work@sky130_fd_sc_hd__a21boi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a21boi.functional.v, line:36:1, endln:60:10 |vpiName:Y |vpiDirection:2 |vpiLowConn: @@ -58652,7 +58652,7 @@ design: (work@sky130_fd_sc_hd__a21boi) |vpiPort: \_port: (A1), line:38:5, endln:38:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a21boi (work@sky130_fd_sc_hd__a21boi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a21boi.functional.v, line:36:1, endln:60:10 + \_module_inst: work@sky130_fd_sc_hd__a21boi (work@sky130_fd_sc_hd__a21boi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a21boi.functional.v, line:36:1, endln:60:10 |vpiName:A1 |vpiDirection:1 |vpiLowConn: @@ -58666,7 +58666,7 @@ design: (work@sky130_fd_sc_hd__a21boi) |vpiPort: \_port: (A2), line:39:5, endln:39:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a21boi (work@sky130_fd_sc_hd__a21boi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a21boi.functional.v, line:36:1, endln:60:10 + \_module_inst: work@sky130_fd_sc_hd__a21boi (work@sky130_fd_sc_hd__a21boi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a21boi.functional.v, line:36:1, endln:60:10 |vpiName:A2 |vpiDirection:1 |vpiLowConn: @@ -58680,7 +58680,7 @@ design: (work@sky130_fd_sc_hd__a21boi) |vpiPort: \_port: (B1_N), line:40:5, endln:40:9 |vpiParent: - \_module: work@sky130_fd_sc_hd__a21boi (work@sky130_fd_sc_hd__a21boi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a21boi.functional.v, line:36:1, endln:60:10 + \_module_inst: work@sky130_fd_sc_hd__a21boi (work@sky130_fd_sc_hd__a21boi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a21boi.functional.v, line:36:1, endln:60:10 |vpiName:B1_N |vpiDirection:1 |vpiLowConn: @@ -58694,7 +58694,7 @@ design: (work@sky130_fd_sc_hd__a21boi) |vpiPrimitive: \_gate: work@not (work@sky130_fd_sc_hd__a21boi.not0), line:55:9, endln:55:43 |vpiParent: - \_module: work@sky130_fd_sc_hd__a21boi (work@sky130_fd_sc_hd__a21boi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a21boi.functional.v, line:36:1, endln:60:10 + \_module_inst: work@sky130_fd_sc_hd__a21boi (work@sky130_fd_sc_hd__a21boi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a21boi.functional.v, line:36:1, endln:60:10 |vpiDefName:work@not |vpiName:not0 |vpiFullName:work@sky130_fd_sc_hd__a21boi.not0 @@ -58729,7 +58729,7 @@ design: (work@sky130_fd_sc_hd__a21boi) |vpiPrimitive: \_gate: work@and (work@sky130_fd_sc_hd__a21boi.and0), line:56:9, endln:56:43 |vpiParent: - \_module: work@sky130_fd_sc_hd__a21boi (work@sky130_fd_sc_hd__a21boi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a21boi.functional.v, line:36:1, endln:60:10 + \_module_inst: work@sky130_fd_sc_hd__a21boi (work@sky130_fd_sc_hd__a21boi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a21boi.functional.v, line:36:1, endln:60:10 |vpiDefName:work@and |vpiName:and0 |vpiFullName:work@sky130_fd_sc_hd__a21boi.and0 @@ -58778,7 +58778,7 @@ design: (work@sky130_fd_sc_hd__a21boi) |vpiPrimitive: \_gate: work@nor (work@sky130_fd_sc_hd__a21boi.nor0), line:57:9, endln:57:43 |vpiParent: - \_module: work@sky130_fd_sc_hd__a21boi (work@sky130_fd_sc_hd__a21boi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a21boi.functional.v, line:36:1, endln:60:10 + \_module_inst: work@sky130_fd_sc_hd__a21boi (work@sky130_fd_sc_hd__a21boi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a21boi.functional.v, line:36:1, endln:60:10 |vpiDefName:work@nor |vpiName:nor0 |vpiFullName:work@sky130_fd_sc_hd__a21boi.nor0 @@ -58827,7 +58827,7 @@ design: (work@sky130_fd_sc_hd__a21boi) |vpiPrimitive: \_gate: work@buf (work@sky130_fd_sc_hd__a21boi.buf0), line:58:9, endln:58:43 |vpiParent: - \_module: work@sky130_fd_sc_hd__a21boi (work@sky130_fd_sc_hd__a21boi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a21boi.functional.v, line:36:1, endln:60:10 + \_module_inst: work@sky130_fd_sc_hd__a21boi (work@sky130_fd_sc_hd__a21boi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a21boi.functional.v, line:36:1, endln:60:10 |vpiDefName:work@buf |vpiName:buf0 |vpiFullName:work@sky130_fd_sc_hd__a21boi.buf0 @@ -58870,7 +58870,7 @@ Processing: -cd cells/cells -DUNIT_DELAY -writepp -parse -nocache -nobuiltin -no design: (work@sky130_fd_sc_hd__dlygate4sd1) |vpiName:work@sky130_fd_sc_hd__dlygate4sd1 |uhdmallModules: -\_module: work@sky130_fd_sc_hd__dlygate4sd1 (work@sky130_fd_sc_hd__dlygate4sd1), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlygate4sd1.functional.v, line:33:1, endln:49:10 +\_module_inst: work@sky130_fd_sc_hd__dlygate4sd1 (work@sky130_fd_sc_hd__dlygate4sd1), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlygate4sd1.functional.v, line:33:1, endln:49:10 |vpiParent: \_design: (work@sky130_fd_sc_hd__dlygate4sd1) |vpiFullName:work@sky130_fd_sc_hd__dlygate4sd1 @@ -58878,26 +58878,26 @@ design: (work@sky130_fd_sc_hd__dlygate4sd1) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__dlygate4sd1.buf0_out_X), line:43:10, endln:43:20 |vpiParent: - \_module: work@sky130_fd_sc_hd__dlygate4sd1 (work@sky130_fd_sc_hd__dlygate4sd1), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlygate4sd1.functional.v, line:33:1, endln:49:10 + \_module_inst: work@sky130_fd_sc_hd__dlygate4sd1 (work@sky130_fd_sc_hd__dlygate4sd1), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlygate4sd1.functional.v, line:33:1, endln:49:10 |vpiName:buf0_out_X |vpiFullName:work@sky130_fd_sc_hd__dlygate4sd1.buf0_out_X |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__dlygate4sd1.X), line:34:5, endln:34:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__dlygate4sd1 (work@sky130_fd_sc_hd__dlygate4sd1), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlygate4sd1.functional.v, line:33:1, endln:49:10 + \_module_inst: work@sky130_fd_sc_hd__dlygate4sd1 (work@sky130_fd_sc_hd__dlygate4sd1), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlygate4sd1.functional.v, line:33:1, endln:49:10 |vpiName:X |vpiFullName:work@sky130_fd_sc_hd__dlygate4sd1.X |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__dlygate4sd1.A), line:35:5, endln:35:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__dlygate4sd1 (work@sky130_fd_sc_hd__dlygate4sd1), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlygate4sd1.functional.v, line:33:1, endln:49:10 + \_module_inst: work@sky130_fd_sc_hd__dlygate4sd1 (work@sky130_fd_sc_hd__dlygate4sd1), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlygate4sd1.functional.v, line:33:1, endln:49:10 |vpiName:A |vpiFullName:work@sky130_fd_sc_hd__dlygate4sd1.A |vpiPort: \_port: (X), line:34:5, endln:34:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__dlygate4sd1 (work@sky130_fd_sc_hd__dlygate4sd1), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlygate4sd1.functional.v, line:33:1, endln:49:10 + \_module_inst: work@sky130_fd_sc_hd__dlygate4sd1 (work@sky130_fd_sc_hd__dlygate4sd1), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlygate4sd1.functional.v, line:33:1, endln:49:10 |vpiName:X |vpiDirection:2 |vpiLowConn: @@ -58909,7 +58909,7 @@ design: (work@sky130_fd_sc_hd__dlygate4sd1) |vpiPort: \_port: (A), line:35:5, endln:35:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__dlygate4sd1 (work@sky130_fd_sc_hd__dlygate4sd1), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlygate4sd1.functional.v, line:33:1, endln:49:10 + \_module_inst: work@sky130_fd_sc_hd__dlygate4sd1 (work@sky130_fd_sc_hd__dlygate4sd1), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlygate4sd1.functional.v, line:33:1, endln:49:10 |vpiName:A |vpiDirection:1 |vpiLowConn: @@ -58919,14 +58919,14 @@ design: (work@sky130_fd_sc_hd__dlygate4sd1) |vpiTypedef: \_logic_typespec: , line:40:12, endln:40:12 |uhdmtopModules: -\_module: work@sky130_fd_sc_hd__dlygate4sd1 (work@sky130_fd_sc_hd__dlygate4sd1), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlygate4sd1.functional.v, line:33:1, endln:49:10 +\_module_inst: work@sky130_fd_sc_hd__dlygate4sd1 (work@sky130_fd_sc_hd__dlygate4sd1), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlygate4sd1.functional.v, line:33:1, endln:49:10 |vpiName:work@sky130_fd_sc_hd__dlygate4sd1 |vpiDefName:work@sky130_fd_sc_hd__dlygate4sd1 |vpiTop:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__dlygate4sd1.buf0_out_X), line:43:10, endln:43:20 |vpiParent: - \_module: work@sky130_fd_sc_hd__dlygate4sd1 (work@sky130_fd_sc_hd__dlygate4sd1), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlygate4sd1.functional.v, line:33:1, endln:49:10 + \_module_inst: work@sky130_fd_sc_hd__dlygate4sd1 (work@sky130_fd_sc_hd__dlygate4sd1), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlygate4sd1.functional.v, line:33:1, endln:49:10 |vpiTypespec: \_logic_typespec: , line:43:5, endln:43:9 |vpiName:buf0_out_X @@ -58935,7 +58935,7 @@ design: (work@sky130_fd_sc_hd__dlygate4sd1) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__dlygate4sd1.X), line:34:5, endln:34:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__dlygate4sd1 (work@sky130_fd_sc_hd__dlygate4sd1), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlygate4sd1.functional.v, line:33:1, endln:49:10 + \_module_inst: work@sky130_fd_sc_hd__dlygate4sd1 (work@sky130_fd_sc_hd__dlygate4sd1), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlygate4sd1.functional.v, line:33:1, endln:49:10 |vpiTypespec: \_logic_typespec: , line:39:12, endln:39:12 |vpiName:X @@ -58943,7 +58943,7 @@ design: (work@sky130_fd_sc_hd__dlygate4sd1) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__dlygate4sd1.A), line:35:5, endln:35:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__dlygate4sd1 (work@sky130_fd_sc_hd__dlygate4sd1), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlygate4sd1.functional.v, line:33:1, endln:49:10 + \_module_inst: work@sky130_fd_sc_hd__dlygate4sd1 (work@sky130_fd_sc_hd__dlygate4sd1), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlygate4sd1.functional.v, line:33:1, endln:49:10 |vpiTypespec: \_logic_typespec: , line:40:12, endln:40:12 |vpiName:A @@ -58952,7 +58952,7 @@ design: (work@sky130_fd_sc_hd__dlygate4sd1) |vpiPort: \_port: (X), line:34:5, endln:34:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__dlygate4sd1 (work@sky130_fd_sc_hd__dlygate4sd1), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlygate4sd1.functional.v, line:33:1, endln:49:10 + \_module_inst: work@sky130_fd_sc_hd__dlygate4sd1 (work@sky130_fd_sc_hd__dlygate4sd1), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlygate4sd1.functional.v, line:33:1, endln:49:10 |vpiName:X |vpiDirection:2 |vpiLowConn: @@ -58966,7 +58966,7 @@ design: (work@sky130_fd_sc_hd__dlygate4sd1) |vpiPort: \_port: (A), line:35:5, endln:35:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__dlygate4sd1 (work@sky130_fd_sc_hd__dlygate4sd1), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlygate4sd1.functional.v, line:33:1, endln:49:10 + \_module_inst: work@sky130_fd_sc_hd__dlygate4sd1 (work@sky130_fd_sc_hd__dlygate4sd1), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlygate4sd1.functional.v, line:33:1, endln:49:10 |vpiName:A |vpiDirection:1 |vpiLowConn: @@ -58980,7 +58980,7 @@ design: (work@sky130_fd_sc_hd__dlygate4sd1) |vpiPrimitive: \_gate: work@buf (work@sky130_fd_sc_hd__dlygate4sd1.buf0), line:46:9, endln:46:43 |vpiParent: - \_module: work@sky130_fd_sc_hd__dlygate4sd1 (work@sky130_fd_sc_hd__dlygate4sd1), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlygate4sd1.functional.v, line:33:1, endln:49:10 + \_module_inst: work@sky130_fd_sc_hd__dlygate4sd1 (work@sky130_fd_sc_hd__dlygate4sd1), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlygate4sd1.functional.v, line:33:1, endln:49:10 |vpiDefName:work@buf |vpiName:buf0 |vpiFullName:work@sky130_fd_sc_hd__dlygate4sd1.buf0 @@ -59015,7 +59015,7 @@ design: (work@sky130_fd_sc_hd__dlygate4sd1) |vpiPrimitive: \_gate: work@buf (work@sky130_fd_sc_hd__dlygate4sd1.buf1), line:47:9, endln:47:43 |vpiParent: - \_module: work@sky130_fd_sc_hd__dlygate4sd1 (work@sky130_fd_sc_hd__dlygate4sd1), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlygate4sd1.functional.v, line:33:1, endln:49:10 + \_module_inst: work@sky130_fd_sc_hd__dlygate4sd1 (work@sky130_fd_sc_hd__dlygate4sd1), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlygate4sd1.functional.v, line:33:1, endln:49:10 |vpiDefName:work@buf |vpiName:buf1 |vpiFullName:work@sky130_fd_sc_hd__dlygate4sd1.buf1 @@ -59058,7 +59058,7 @@ Processing: -cd cells/cells -DUNIT_DELAY -writepp -parse -nocache -nobuiltin -no design: (work@sky130_fd_sc_hd__a32oi) |vpiName:work@sky130_fd_sc_hd__a32oi |uhdmallModules: -\_module: work@sky130_fd_sc_hd__a32oi (work@sky130_fd_sc_hd__a32oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a32oi.functional.v, line:36:1, endln:64:10 +\_module_inst: work@sky130_fd_sc_hd__a32oi (work@sky130_fd_sc_hd__a32oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a32oi.functional.v, line:36:1, endln:64:10 |vpiParent: \_design: (work@sky130_fd_sc_hd__a32oi) |vpiFullName:work@sky130_fd_sc_hd__a32oi @@ -59066,64 +59066,64 @@ design: (work@sky130_fd_sc_hd__a32oi) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a32oi.nand0_out), line:54:10, endln:54:19 |vpiParent: - \_module: work@sky130_fd_sc_hd__a32oi (work@sky130_fd_sc_hd__a32oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a32oi.functional.v, line:36:1, endln:64:10 + \_module_inst: work@sky130_fd_sc_hd__a32oi (work@sky130_fd_sc_hd__a32oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a32oi.functional.v, line:36:1, endln:64:10 |vpiName:nand0_out |vpiFullName:work@sky130_fd_sc_hd__a32oi.nand0_out |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a32oi.nand1_out), line:55:10, endln:55:19 |vpiParent: - \_module: work@sky130_fd_sc_hd__a32oi (work@sky130_fd_sc_hd__a32oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a32oi.functional.v, line:36:1, endln:64:10 + \_module_inst: work@sky130_fd_sc_hd__a32oi (work@sky130_fd_sc_hd__a32oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a32oi.functional.v, line:36:1, endln:64:10 |vpiName:nand1_out |vpiFullName:work@sky130_fd_sc_hd__a32oi.nand1_out |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a32oi.and0_out_Y), line:56:10, endln:56:20 |vpiParent: - \_module: work@sky130_fd_sc_hd__a32oi (work@sky130_fd_sc_hd__a32oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a32oi.functional.v, line:36:1, endln:64:10 + \_module_inst: work@sky130_fd_sc_hd__a32oi (work@sky130_fd_sc_hd__a32oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a32oi.functional.v, line:36:1, endln:64:10 |vpiName:and0_out_Y |vpiFullName:work@sky130_fd_sc_hd__a32oi.and0_out_Y |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a32oi.Y), line:37:5, endln:37:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__a32oi (work@sky130_fd_sc_hd__a32oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a32oi.functional.v, line:36:1, endln:64:10 + \_module_inst: work@sky130_fd_sc_hd__a32oi (work@sky130_fd_sc_hd__a32oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a32oi.functional.v, line:36:1, endln:64:10 |vpiName:Y |vpiFullName:work@sky130_fd_sc_hd__a32oi.Y |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a32oi.A1), line:38:5, endln:38:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a32oi (work@sky130_fd_sc_hd__a32oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a32oi.functional.v, line:36:1, endln:64:10 + \_module_inst: work@sky130_fd_sc_hd__a32oi (work@sky130_fd_sc_hd__a32oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a32oi.functional.v, line:36:1, endln:64:10 |vpiName:A1 |vpiFullName:work@sky130_fd_sc_hd__a32oi.A1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a32oi.A2), line:39:5, endln:39:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a32oi (work@sky130_fd_sc_hd__a32oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a32oi.functional.v, line:36:1, endln:64:10 + \_module_inst: work@sky130_fd_sc_hd__a32oi (work@sky130_fd_sc_hd__a32oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a32oi.functional.v, line:36:1, endln:64:10 |vpiName:A2 |vpiFullName:work@sky130_fd_sc_hd__a32oi.A2 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a32oi.A3), line:40:5, endln:40:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a32oi (work@sky130_fd_sc_hd__a32oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a32oi.functional.v, line:36:1, endln:64:10 + \_module_inst: work@sky130_fd_sc_hd__a32oi (work@sky130_fd_sc_hd__a32oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a32oi.functional.v, line:36:1, endln:64:10 |vpiName:A3 |vpiFullName:work@sky130_fd_sc_hd__a32oi.A3 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a32oi.B1), line:41:5, endln:41:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a32oi (work@sky130_fd_sc_hd__a32oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a32oi.functional.v, line:36:1, endln:64:10 + \_module_inst: work@sky130_fd_sc_hd__a32oi (work@sky130_fd_sc_hd__a32oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a32oi.functional.v, line:36:1, endln:64:10 |vpiName:B1 |vpiFullName:work@sky130_fd_sc_hd__a32oi.B1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a32oi.B2), line:42:5, endln:42:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a32oi (work@sky130_fd_sc_hd__a32oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a32oi.functional.v, line:36:1, endln:64:10 + \_module_inst: work@sky130_fd_sc_hd__a32oi (work@sky130_fd_sc_hd__a32oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a32oi.functional.v, line:36:1, endln:64:10 |vpiName:B2 |vpiFullName:work@sky130_fd_sc_hd__a32oi.B2 |vpiPort: \_port: (Y), line:37:5, endln:37:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__a32oi (work@sky130_fd_sc_hd__a32oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a32oi.functional.v, line:36:1, endln:64:10 + \_module_inst: work@sky130_fd_sc_hd__a32oi (work@sky130_fd_sc_hd__a32oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a32oi.functional.v, line:36:1, endln:64:10 |vpiName:Y |vpiDirection:2 |vpiLowConn: @@ -59135,7 +59135,7 @@ design: (work@sky130_fd_sc_hd__a32oi) |vpiPort: \_port: (A1), line:38:5, endln:38:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a32oi (work@sky130_fd_sc_hd__a32oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a32oi.functional.v, line:36:1, endln:64:10 + \_module_inst: work@sky130_fd_sc_hd__a32oi (work@sky130_fd_sc_hd__a32oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a32oi.functional.v, line:36:1, endln:64:10 |vpiName:A1 |vpiDirection:1 |vpiLowConn: @@ -59147,7 +59147,7 @@ design: (work@sky130_fd_sc_hd__a32oi) |vpiPort: \_port: (A2), line:39:5, endln:39:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a32oi (work@sky130_fd_sc_hd__a32oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a32oi.functional.v, line:36:1, endln:64:10 + \_module_inst: work@sky130_fd_sc_hd__a32oi (work@sky130_fd_sc_hd__a32oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a32oi.functional.v, line:36:1, endln:64:10 |vpiName:A2 |vpiDirection:1 |vpiLowConn: @@ -59159,7 +59159,7 @@ design: (work@sky130_fd_sc_hd__a32oi) |vpiPort: \_port: (A3), line:40:5, endln:40:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a32oi (work@sky130_fd_sc_hd__a32oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a32oi.functional.v, line:36:1, endln:64:10 + \_module_inst: work@sky130_fd_sc_hd__a32oi (work@sky130_fd_sc_hd__a32oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a32oi.functional.v, line:36:1, endln:64:10 |vpiName:A3 |vpiDirection:1 |vpiLowConn: @@ -59171,7 +59171,7 @@ design: (work@sky130_fd_sc_hd__a32oi) |vpiPort: \_port: (B1), line:41:5, endln:41:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a32oi (work@sky130_fd_sc_hd__a32oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a32oi.functional.v, line:36:1, endln:64:10 + \_module_inst: work@sky130_fd_sc_hd__a32oi (work@sky130_fd_sc_hd__a32oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a32oi.functional.v, line:36:1, endln:64:10 |vpiName:B1 |vpiDirection:1 |vpiLowConn: @@ -59183,7 +59183,7 @@ design: (work@sky130_fd_sc_hd__a32oi) |vpiPort: \_port: (B2), line:42:5, endln:42:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a32oi (work@sky130_fd_sc_hd__a32oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a32oi.functional.v, line:36:1, endln:64:10 + \_module_inst: work@sky130_fd_sc_hd__a32oi (work@sky130_fd_sc_hd__a32oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a32oi.functional.v, line:36:1, endln:64:10 |vpiName:B2 |vpiDirection:1 |vpiLowConn: @@ -59193,14 +59193,14 @@ design: (work@sky130_fd_sc_hd__a32oi) |vpiTypedef: \_logic_typespec: , line:51:12, endln:51:12 |uhdmtopModules: -\_module: work@sky130_fd_sc_hd__a32oi (work@sky130_fd_sc_hd__a32oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a32oi.functional.v, line:36:1, endln:64:10 +\_module_inst: work@sky130_fd_sc_hd__a32oi (work@sky130_fd_sc_hd__a32oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a32oi.functional.v, line:36:1, endln:64:10 |vpiName:work@sky130_fd_sc_hd__a32oi |vpiDefName:work@sky130_fd_sc_hd__a32oi |vpiTop:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a32oi.nand0_out), line:54:10, endln:54:19 |vpiParent: - \_module: work@sky130_fd_sc_hd__a32oi (work@sky130_fd_sc_hd__a32oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a32oi.functional.v, line:36:1, endln:64:10 + \_module_inst: work@sky130_fd_sc_hd__a32oi (work@sky130_fd_sc_hd__a32oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a32oi.functional.v, line:36:1, endln:64:10 |vpiTypespec: \_logic_typespec: , line:54:5, endln:54:9 |vpiName:nand0_out @@ -59209,7 +59209,7 @@ design: (work@sky130_fd_sc_hd__a32oi) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a32oi.nand1_out), line:55:10, endln:55:19 |vpiParent: - \_module: work@sky130_fd_sc_hd__a32oi (work@sky130_fd_sc_hd__a32oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a32oi.functional.v, line:36:1, endln:64:10 + \_module_inst: work@sky130_fd_sc_hd__a32oi (work@sky130_fd_sc_hd__a32oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a32oi.functional.v, line:36:1, endln:64:10 |vpiTypespec: \_logic_typespec: , line:55:5, endln:55:9 |vpiName:nand1_out @@ -59218,7 +59218,7 @@ design: (work@sky130_fd_sc_hd__a32oi) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a32oi.and0_out_Y), line:56:10, endln:56:20 |vpiParent: - \_module: work@sky130_fd_sc_hd__a32oi (work@sky130_fd_sc_hd__a32oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a32oi.functional.v, line:36:1, endln:64:10 + \_module_inst: work@sky130_fd_sc_hd__a32oi (work@sky130_fd_sc_hd__a32oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a32oi.functional.v, line:36:1, endln:64:10 |vpiTypespec: \_logic_typespec: , line:56:5, endln:56:9 |vpiName:and0_out_Y @@ -59227,7 +59227,7 @@ design: (work@sky130_fd_sc_hd__a32oi) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a32oi.Y), line:37:5, endln:37:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__a32oi (work@sky130_fd_sc_hd__a32oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a32oi.functional.v, line:36:1, endln:64:10 + \_module_inst: work@sky130_fd_sc_hd__a32oi (work@sky130_fd_sc_hd__a32oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a32oi.functional.v, line:36:1, endln:64:10 |vpiTypespec: \_logic_typespec: , line:46:12, endln:46:12 |vpiName:Y @@ -59235,7 +59235,7 @@ design: (work@sky130_fd_sc_hd__a32oi) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a32oi.A1), line:38:5, endln:38:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a32oi (work@sky130_fd_sc_hd__a32oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a32oi.functional.v, line:36:1, endln:64:10 + \_module_inst: work@sky130_fd_sc_hd__a32oi (work@sky130_fd_sc_hd__a32oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a32oi.functional.v, line:36:1, endln:64:10 |vpiTypespec: \_logic_typespec: , line:47:12, endln:47:12 |vpiName:A1 @@ -59243,7 +59243,7 @@ design: (work@sky130_fd_sc_hd__a32oi) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a32oi.A2), line:39:5, endln:39:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a32oi (work@sky130_fd_sc_hd__a32oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a32oi.functional.v, line:36:1, endln:64:10 + \_module_inst: work@sky130_fd_sc_hd__a32oi (work@sky130_fd_sc_hd__a32oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a32oi.functional.v, line:36:1, endln:64:10 |vpiTypespec: \_logic_typespec: , line:48:12, endln:48:12 |vpiName:A2 @@ -59251,7 +59251,7 @@ design: (work@sky130_fd_sc_hd__a32oi) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a32oi.A3), line:40:5, endln:40:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a32oi (work@sky130_fd_sc_hd__a32oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a32oi.functional.v, line:36:1, endln:64:10 + \_module_inst: work@sky130_fd_sc_hd__a32oi (work@sky130_fd_sc_hd__a32oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a32oi.functional.v, line:36:1, endln:64:10 |vpiTypespec: \_logic_typespec: , line:49:12, endln:49:12 |vpiName:A3 @@ -59259,7 +59259,7 @@ design: (work@sky130_fd_sc_hd__a32oi) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a32oi.B1), line:41:5, endln:41:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a32oi (work@sky130_fd_sc_hd__a32oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a32oi.functional.v, line:36:1, endln:64:10 + \_module_inst: work@sky130_fd_sc_hd__a32oi (work@sky130_fd_sc_hd__a32oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a32oi.functional.v, line:36:1, endln:64:10 |vpiTypespec: \_logic_typespec: , line:50:12, endln:50:12 |vpiName:B1 @@ -59267,7 +59267,7 @@ design: (work@sky130_fd_sc_hd__a32oi) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a32oi.B2), line:42:5, endln:42:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a32oi (work@sky130_fd_sc_hd__a32oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a32oi.functional.v, line:36:1, endln:64:10 + \_module_inst: work@sky130_fd_sc_hd__a32oi (work@sky130_fd_sc_hd__a32oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a32oi.functional.v, line:36:1, endln:64:10 |vpiTypespec: \_logic_typespec: , line:51:12, endln:51:12 |vpiName:B2 @@ -59276,7 +59276,7 @@ design: (work@sky130_fd_sc_hd__a32oi) |vpiPort: \_port: (Y), line:37:5, endln:37:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__a32oi (work@sky130_fd_sc_hd__a32oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a32oi.functional.v, line:36:1, endln:64:10 + \_module_inst: work@sky130_fd_sc_hd__a32oi (work@sky130_fd_sc_hd__a32oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a32oi.functional.v, line:36:1, endln:64:10 |vpiName:Y |vpiDirection:2 |vpiLowConn: @@ -59290,7 +59290,7 @@ design: (work@sky130_fd_sc_hd__a32oi) |vpiPort: \_port: (A1), line:38:5, endln:38:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a32oi (work@sky130_fd_sc_hd__a32oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a32oi.functional.v, line:36:1, endln:64:10 + \_module_inst: work@sky130_fd_sc_hd__a32oi (work@sky130_fd_sc_hd__a32oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a32oi.functional.v, line:36:1, endln:64:10 |vpiName:A1 |vpiDirection:1 |vpiLowConn: @@ -59304,7 +59304,7 @@ design: (work@sky130_fd_sc_hd__a32oi) |vpiPort: \_port: (A2), line:39:5, endln:39:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a32oi (work@sky130_fd_sc_hd__a32oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a32oi.functional.v, line:36:1, endln:64:10 + \_module_inst: work@sky130_fd_sc_hd__a32oi (work@sky130_fd_sc_hd__a32oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a32oi.functional.v, line:36:1, endln:64:10 |vpiName:A2 |vpiDirection:1 |vpiLowConn: @@ -59318,7 +59318,7 @@ design: (work@sky130_fd_sc_hd__a32oi) |vpiPort: \_port: (A3), line:40:5, endln:40:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a32oi (work@sky130_fd_sc_hd__a32oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a32oi.functional.v, line:36:1, endln:64:10 + \_module_inst: work@sky130_fd_sc_hd__a32oi (work@sky130_fd_sc_hd__a32oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a32oi.functional.v, line:36:1, endln:64:10 |vpiName:A3 |vpiDirection:1 |vpiLowConn: @@ -59332,7 +59332,7 @@ design: (work@sky130_fd_sc_hd__a32oi) |vpiPort: \_port: (B1), line:41:5, endln:41:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a32oi (work@sky130_fd_sc_hd__a32oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a32oi.functional.v, line:36:1, endln:64:10 + \_module_inst: work@sky130_fd_sc_hd__a32oi (work@sky130_fd_sc_hd__a32oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a32oi.functional.v, line:36:1, endln:64:10 |vpiName:B1 |vpiDirection:1 |vpiLowConn: @@ -59346,7 +59346,7 @@ design: (work@sky130_fd_sc_hd__a32oi) |vpiPort: \_port: (B2), line:42:5, endln:42:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a32oi (work@sky130_fd_sc_hd__a32oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a32oi.functional.v, line:36:1, endln:64:10 + \_module_inst: work@sky130_fd_sc_hd__a32oi (work@sky130_fd_sc_hd__a32oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a32oi.functional.v, line:36:1, endln:64:10 |vpiName:B2 |vpiDirection:1 |vpiLowConn: @@ -59360,7 +59360,7 @@ design: (work@sky130_fd_sc_hd__a32oi) |vpiPrimitive: \_gate: work@nand (work@sky130_fd_sc_hd__a32oi.nand0), line:59:10, endln:59:50 |vpiParent: - \_module: work@sky130_fd_sc_hd__a32oi (work@sky130_fd_sc_hd__a32oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a32oi.functional.v, line:36:1, endln:64:10 + \_module_inst: work@sky130_fd_sc_hd__a32oi (work@sky130_fd_sc_hd__a32oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a32oi.functional.v, line:36:1, endln:64:10 |vpiDefName:work@nand |vpiName:nand0 |vpiFullName:work@sky130_fd_sc_hd__a32oi.nand0 @@ -59423,7 +59423,7 @@ design: (work@sky130_fd_sc_hd__a32oi) |vpiPrimitive: \_gate: work@nand (work@sky130_fd_sc_hd__a32oi.nand1), line:60:10, endln:60:50 |vpiParent: - \_module: work@sky130_fd_sc_hd__a32oi (work@sky130_fd_sc_hd__a32oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a32oi.functional.v, line:36:1, endln:64:10 + \_module_inst: work@sky130_fd_sc_hd__a32oi (work@sky130_fd_sc_hd__a32oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a32oi.functional.v, line:36:1, endln:64:10 |vpiDefName:work@nand |vpiName:nand1 |vpiFullName:work@sky130_fd_sc_hd__a32oi.nand1 @@ -59472,7 +59472,7 @@ design: (work@sky130_fd_sc_hd__a32oi) |vpiPrimitive: \_gate: work@and (work@sky130_fd_sc_hd__a32oi.and0), line:61:10, endln:61:50 |vpiParent: - \_module: work@sky130_fd_sc_hd__a32oi (work@sky130_fd_sc_hd__a32oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a32oi.functional.v, line:36:1, endln:64:10 + \_module_inst: work@sky130_fd_sc_hd__a32oi (work@sky130_fd_sc_hd__a32oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a32oi.functional.v, line:36:1, endln:64:10 |vpiDefName:work@and |vpiName:and0 |vpiFullName:work@sky130_fd_sc_hd__a32oi.and0 @@ -59521,7 +59521,7 @@ design: (work@sky130_fd_sc_hd__a32oi) |vpiPrimitive: \_gate: work@buf (work@sky130_fd_sc_hd__a32oi.buf0), line:62:10, endln:62:50 |vpiParent: - \_module: work@sky130_fd_sc_hd__a32oi (work@sky130_fd_sc_hd__a32oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a32oi.functional.v, line:36:1, endln:64:10 + \_module_inst: work@sky130_fd_sc_hd__a32oi (work@sky130_fd_sc_hd__a32oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a32oi.functional.v, line:36:1, endln:64:10 |vpiDefName:work@buf |vpiName:buf0 |vpiFullName:work@sky130_fd_sc_hd__a32oi.buf0 @@ -59564,7 +59564,7 @@ Processing: -cd cells/cells -DUNIT_DELAY -writepp -parse -nocache -nobuiltin -no design: (work@sky130_fd_sc_hd__o311a) |vpiName:work@sky130_fd_sc_hd__o311a |uhdmallModules: -\_module: work@sky130_fd_sc_hd__o311a (work@sky130_fd_sc_hd__o311a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o311a.functional.v, line:35:1, endln:61:10 +\_module_inst: work@sky130_fd_sc_hd__o311a (work@sky130_fd_sc_hd__o311a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o311a.functional.v, line:35:1, endln:61:10 |vpiParent: \_design: (work@sky130_fd_sc_hd__o311a) |vpiFullName:work@sky130_fd_sc_hd__o311a @@ -59572,57 +59572,57 @@ design: (work@sky130_fd_sc_hd__o311a) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o311a.or0_out), line:53:10, endln:53:17 |vpiParent: - \_module: work@sky130_fd_sc_hd__o311a (work@sky130_fd_sc_hd__o311a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o311a.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o311a (work@sky130_fd_sc_hd__o311a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o311a.functional.v, line:35:1, endln:61:10 |vpiName:or0_out |vpiFullName:work@sky130_fd_sc_hd__o311a.or0_out |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o311a.and0_out_X), line:54:10, endln:54:20 |vpiParent: - \_module: work@sky130_fd_sc_hd__o311a (work@sky130_fd_sc_hd__o311a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o311a.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o311a (work@sky130_fd_sc_hd__o311a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o311a.functional.v, line:35:1, endln:61:10 |vpiName:and0_out_X |vpiFullName:work@sky130_fd_sc_hd__o311a.and0_out_X |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o311a.X), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__o311a (work@sky130_fd_sc_hd__o311a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o311a.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o311a (work@sky130_fd_sc_hd__o311a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o311a.functional.v, line:35:1, endln:61:10 |vpiName:X |vpiFullName:work@sky130_fd_sc_hd__o311a.X |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o311a.A1), line:37:5, endln:37:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o311a (work@sky130_fd_sc_hd__o311a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o311a.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o311a (work@sky130_fd_sc_hd__o311a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o311a.functional.v, line:35:1, endln:61:10 |vpiName:A1 |vpiFullName:work@sky130_fd_sc_hd__o311a.A1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o311a.A2), line:38:5, endln:38:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o311a (work@sky130_fd_sc_hd__o311a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o311a.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o311a (work@sky130_fd_sc_hd__o311a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o311a.functional.v, line:35:1, endln:61:10 |vpiName:A2 |vpiFullName:work@sky130_fd_sc_hd__o311a.A2 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o311a.A3), line:39:5, endln:39:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o311a (work@sky130_fd_sc_hd__o311a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o311a.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o311a (work@sky130_fd_sc_hd__o311a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o311a.functional.v, line:35:1, endln:61:10 |vpiName:A3 |vpiFullName:work@sky130_fd_sc_hd__o311a.A3 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o311a.B1), line:40:5, endln:40:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o311a (work@sky130_fd_sc_hd__o311a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o311a.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o311a (work@sky130_fd_sc_hd__o311a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o311a.functional.v, line:35:1, endln:61:10 |vpiName:B1 |vpiFullName:work@sky130_fd_sc_hd__o311a.B1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o311a.C1), line:41:5, endln:41:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o311a (work@sky130_fd_sc_hd__o311a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o311a.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o311a (work@sky130_fd_sc_hd__o311a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o311a.functional.v, line:35:1, endln:61:10 |vpiName:C1 |vpiFullName:work@sky130_fd_sc_hd__o311a.C1 |vpiPort: \_port: (X), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__o311a (work@sky130_fd_sc_hd__o311a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o311a.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o311a (work@sky130_fd_sc_hd__o311a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o311a.functional.v, line:35:1, endln:61:10 |vpiName:X |vpiDirection:2 |vpiLowConn: @@ -59634,7 +59634,7 @@ design: (work@sky130_fd_sc_hd__o311a) |vpiPort: \_port: (A1), line:37:5, endln:37:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o311a (work@sky130_fd_sc_hd__o311a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o311a.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o311a (work@sky130_fd_sc_hd__o311a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o311a.functional.v, line:35:1, endln:61:10 |vpiName:A1 |vpiDirection:1 |vpiLowConn: @@ -59646,7 +59646,7 @@ design: (work@sky130_fd_sc_hd__o311a) |vpiPort: \_port: (A2), line:38:5, endln:38:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o311a (work@sky130_fd_sc_hd__o311a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o311a.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o311a (work@sky130_fd_sc_hd__o311a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o311a.functional.v, line:35:1, endln:61:10 |vpiName:A2 |vpiDirection:1 |vpiLowConn: @@ -59658,7 +59658,7 @@ design: (work@sky130_fd_sc_hd__o311a) |vpiPort: \_port: (A3), line:39:5, endln:39:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o311a (work@sky130_fd_sc_hd__o311a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o311a.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o311a (work@sky130_fd_sc_hd__o311a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o311a.functional.v, line:35:1, endln:61:10 |vpiName:A3 |vpiDirection:1 |vpiLowConn: @@ -59670,7 +59670,7 @@ design: (work@sky130_fd_sc_hd__o311a) |vpiPort: \_port: (B1), line:40:5, endln:40:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o311a (work@sky130_fd_sc_hd__o311a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o311a.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o311a (work@sky130_fd_sc_hd__o311a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o311a.functional.v, line:35:1, endln:61:10 |vpiName:B1 |vpiDirection:1 |vpiLowConn: @@ -59682,7 +59682,7 @@ design: (work@sky130_fd_sc_hd__o311a) |vpiPort: \_port: (C1), line:41:5, endln:41:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o311a (work@sky130_fd_sc_hd__o311a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o311a.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o311a (work@sky130_fd_sc_hd__o311a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o311a.functional.v, line:35:1, endln:61:10 |vpiName:C1 |vpiDirection:1 |vpiLowConn: @@ -59692,14 +59692,14 @@ design: (work@sky130_fd_sc_hd__o311a) |vpiTypedef: \_logic_typespec: , line:50:12, endln:50:12 |uhdmtopModules: -\_module: work@sky130_fd_sc_hd__o311a (work@sky130_fd_sc_hd__o311a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o311a.functional.v, line:35:1, endln:61:10 +\_module_inst: work@sky130_fd_sc_hd__o311a (work@sky130_fd_sc_hd__o311a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o311a.functional.v, line:35:1, endln:61:10 |vpiName:work@sky130_fd_sc_hd__o311a |vpiDefName:work@sky130_fd_sc_hd__o311a |vpiTop:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o311a.or0_out), line:53:10, endln:53:17 |vpiParent: - \_module: work@sky130_fd_sc_hd__o311a (work@sky130_fd_sc_hd__o311a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o311a.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o311a (work@sky130_fd_sc_hd__o311a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o311a.functional.v, line:35:1, endln:61:10 |vpiTypespec: \_logic_typespec: , line:53:5, endln:53:9 |vpiName:or0_out @@ -59708,7 +59708,7 @@ design: (work@sky130_fd_sc_hd__o311a) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o311a.and0_out_X), line:54:10, endln:54:20 |vpiParent: - \_module: work@sky130_fd_sc_hd__o311a (work@sky130_fd_sc_hd__o311a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o311a.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o311a (work@sky130_fd_sc_hd__o311a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o311a.functional.v, line:35:1, endln:61:10 |vpiTypespec: \_logic_typespec: , line:54:5, endln:54:9 |vpiName:and0_out_X @@ -59717,7 +59717,7 @@ design: (work@sky130_fd_sc_hd__o311a) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o311a.X), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__o311a (work@sky130_fd_sc_hd__o311a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o311a.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o311a (work@sky130_fd_sc_hd__o311a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o311a.functional.v, line:35:1, endln:61:10 |vpiTypespec: \_logic_typespec: , line:45:12, endln:45:12 |vpiName:X @@ -59725,7 +59725,7 @@ design: (work@sky130_fd_sc_hd__o311a) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o311a.A1), line:37:5, endln:37:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o311a (work@sky130_fd_sc_hd__o311a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o311a.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o311a (work@sky130_fd_sc_hd__o311a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o311a.functional.v, line:35:1, endln:61:10 |vpiTypespec: \_logic_typespec: , line:46:12, endln:46:12 |vpiName:A1 @@ -59733,7 +59733,7 @@ design: (work@sky130_fd_sc_hd__o311a) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o311a.A2), line:38:5, endln:38:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o311a (work@sky130_fd_sc_hd__o311a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o311a.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o311a (work@sky130_fd_sc_hd__o311a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o311a.functional.v, line:35:1, endln:61:10 |vpiTypespec: \_logic_typespec: , line:47:12, endln:47:12 |vpiName:A2 @@ -59741,7 +59741,7 @@ design: (work@sky130_fd_sc_hd__o311a) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o311a.A3), line:39:5, endln:39:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o311a (work@sky130_fd_sc_hd__o311a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o311a.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o311a (work@sky130_fd_sc_hd__o311a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o311a.functional.v, line:35:1, endln:61:10 |vpiTypespec: \_logic_typespec: , line:48:12, endln:48:12 |vpiName:A3 @@ -59749,7 +59749,7 @@ design: (work@sky130_fd_sc_hd__o311a) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o311a.B1), line:40:5, endln:40:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o311a (work@sky130_fd_sc_hd__o311a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o311a.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o311a (work@sky130_fd_sc_hd__o311a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o311a.functional.v, line:35:1, endln:61:10 |vpiTypespec: \_logic_typespec: , line:49:12, endln:49:12 |vpiName:B1 @@ -59757,7 +59757,7 @@ design: (work@sky130_fd_sc_hd__o311a) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__o311a.C1), line:41:5, endln:41:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o311a (work@sky130_fd_sc_hd__o311a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o311a.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o311a (work@sky130_fd_sc_hd__o311a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o311a.functional.v, line:35:1, endln:61:10 |vpiTypespec: \_logic_typespec: , line:50:12, endln:50:12 |vpiName:C1 @@ -59766,7 +59766,7 @@ design: (work@sky130_fd_sc_hd__o311a) |vpiPort: \_port: (X), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__o311a (work@sky130_fd_sc_hd__o311a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o311a.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o311a (work@sky130_fd_sc_hd__o311a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o311a.functional.v, line:35:1, endln:61:10 |vpiName:X |vpiDirection:2 |vpiLowConn: @@ -59780,7 +59780,7 @@ design: (work@sky130_fd_sc_hd__o311a) |vpiPort: \_port: (A1), line:37:5, endln:37:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o311a (work@sky130_fd_sc_hd__o311a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o311a.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o311a (work@sky130_fd_sc_hd__o311a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o311a.functional.v, line:35:1, endln:61:10 |vpiName:A1 |vpiDirection:1 |vpiLowConn: @@ -59794,7 +59794,7 @@ design: (work@sky130_fd_sc_hd__o311a) |vpiPort: \_port: (A2), line:38:5, endln:38:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o311a (work@sky130_fd_sc_hd__o311a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o311a.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o311a (work@sky130_fd_sc_hd__o311a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o311a.functional.v, line:35:1, endln:61:10 |vpiName:A2 |vpiDirection:1 |vpiLowConn: @@ -59808,7 +59808,7 @@ design: (work@sky130_fd_sc_hd__o311a) |vpiPort: \_port: (A3), line:39:5, endln:39:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o311a (work@sky130_fd_sc_hd__o311a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o311a.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o311a (work@sky130_fd_sc_hd__o311a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o311a.functional.v, line:35:1, endln:61:10 |vpiName:A3 |vpiDirection:1 |vpiLowConn: @@ -59822,7 +59822,7 @@ design: (work@sky130_fd_sc_hd__o311a) |vpiPort: \_port: (B1), line:40:5, endln:40:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o311a (work@sky130_fd_sc_hd__o311a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o311a.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o311a (work@sky130_fd_sc_hd__o311a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o311a.functional.v, line:35:1, endln:61:10 |vpiName:B1 |vpiDirection:1 |vpiLowConn: @@ -59836,7 +59836,7 @@ design: (work@sky130_fd_sc_hd__o311a) |vpiPort: \_port: (C1), line:41:5, endln:41:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__o311a (work@sky130_fd_sc_hd__o311a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o311a.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o311a (work@sky130_fd_sc_hd__o311a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o311a.functional.v, line:35:1, endln:61:10 |vpiName:C1 |vpiDirection:1 |vpiLowConn: @@ -59850,7 +59850,7 @@ design: (work@sky130_fd_sc_hd__o311a) |vpiPrimitive: \_gate: work@or (work@sky130_fd_sc_hd__o311a.or0), line:57:9, endln:57:43 |vpiParent: - \_module: work@sky130_fd_sc_hd__o311a (work@sky130_fd_sc_hd__o311a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o311a.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o311a (work@sky130_fd_sc_hd__o311a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o311a.functional.v, line:35:1, endln:61:10 |vpiDefName:work@or |vpiName:or0 |vpiFullName:work@sky130_fd_sc_hd__o311a.or0 @@ -59913,7 +59913,7 @@ design: (work@sky130_fd_sc_hd__o311a) |vpiPrimitive: \_gate: work@and (work@sky130_fd_sc_hd__o311a.and0), line:58:9, endln:58:43 |vpiParent: - \_module: work@sky130_fd_sc_hd__o311a (work@sky130_fd_sc_hd__o311a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o311a.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o311a (work@sky130_fd_sc_hd__o311a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o311a.functional.v, line:35:1, endln:61:10 |vpiDefName:work@and |vpiName:and0 |vpiFullName:work@sky130_fd_sc_hd__o311a.and0 @@ -59976,7 +59976,7 @@ design: (work@sky130_fd_sc_hd__o311a) |vpiPrimitive: \_gate: work@buf (work@sky130_fd_sc_hd__o311a.buf0), line:59:9, endln:59:43 |vpiParent: - \_module: work@sky130_fd_sc_hd__o311a (work@sky130_fd_sc_hd__o311a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o311a.functional.v, line:35:1, endln:61:10 + \_module_inst: work@sky130_fd_sc_hd__o311a (work@sky130_fd_sc_hd__o311a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o311a.functional.v, line:35:1, endln:61:10 |vpiDefName:work@buf |vpiName:buf0 |vpiFullName:work@sky130_fd_sc_hd__o311a.buf0 @@ -60019,7 +60019,7 @@ Processing: -cd cells/cells -DUNIT_DELAY -writepp -parse -nocache -nobuiltin -no design: (work@sky130_fd_sc_hd__and2b) |vpiName:work@sky130_fd_sc_hd__and2b |uhdmallModules: -\_module: work@sky130_fd_sc_hd__and2b (work@sky130_fd_sc_hd__and2b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and2b.functional.v, line:33:1, endln:53:10 +\_module_inst: work@sky130_fd_sc_hd__and2b (work@sky130_fd_sc_hd__and2b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and2b.functional.v, line:33:1, endln:53:10 |vpiParent: \_design: (work@sky130_fd_sc_hd__and2b) |vpiFullName:work@sky130_fd_sc_hd__and2b @@ -60027,39 +60027,39 @@ design: (work@sky130_fd_sc_hd__and2b) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__and2b.not0_out), line:45:10, endln:45:18 |vpiParent: - \_module: work@sky130_fd_sc_hd__and2b (work@sky130_fd_sc_hd__and2b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and2b.functional.v, line:33:1, endln:53:10 + \_module_inst: work@sky130_fd_sc_hd__and2b (work@sky130_fd_sc_hd__and2b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and2b.functional.v, line:33:1, endln:53:10 |vpiName:not0_out |vpiFullName:work@sky130_fd_sc_hd__and2b.not0_out |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__and2b.and0_out_X), line:46:10, endln:46:20 |vpiParent: - \_module: work@sky130_fd_sc_hd__and2b (work@sky130_fd_sc_hd__and2b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and2b.functional.v, line:33:1, endln:53:10 + \_module_inst: work@sky130_fd_sc_hd__and2b (work@sky130_fd_sc_hd__and2b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and2b.functional.v, line:33:1, endln:53:10 |vpiName:and0_out_X |vpiFullName:work@sky130_fd_sc_hd__and2b.and0_out_X |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__and2b.X), line:34:5, endln:34:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__and2b (work@sky130_fd_sc_hd__and2b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and2b.functional.v, line:33:1, endln:53:10 + \_module_inst: work@sky130_fd_sc_hd__and2b (work@sky130_fd_sc_hd__and2b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and2b.functional.v, line:33:1, endln:53:10 |vpiName:X |vpiFullName:work@sky130_fd_sc_hd__and2b.X |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__and2b.A_N), line:35:5, endln:35:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__and2b (work@sky130_fd_sc_hd__and2b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and2b.functional.v, line:33:1, endln:53:10 + \_module_inst: work@sky130_fd_sc_hd__and2b (work@sky130_fd_sc_hd__and2b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and2b.functional.v, line:33:1, endln:53:10 |vpiName:A_N |vpiFullName:work@sky130_fd_sc_hd__and2b.A_N |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__and2b.B), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__and2b (work@sky130_fd_sc_hd__and2b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and2b.functional.v, line:33:1, endln:53:10 + \_module_inst: work@sky130_fd_sc_hd__and2b (work@sky130_fd_sc_hd__and2b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and2b.functional.v, line:33:1, endln:53:10 |vpiName:B |vpiFullName:work@sky130_fd_sc_hd__and2b.B |vpiPort: \_port: (X), line:34:5, endln:34:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__and2b (work@sky130_fd_sc_hd__and2b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and2b.functional.v, line:33:1, endln:53:10 + \_module_inst: work@sky130_fd_sc_hd__and2b (work@sky130_fd_sc_hd__and2b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and2b.functional.v, line:33:1, endln:53:10 |vpiName:X |vpiDirection:2 |vpiLowConn: @@ -60071,7 +60071,7 @@ design: (work@sky130_fd_sc_hd__and2b) |vpiPort: \_port: (A_N), line:35:5, endln:35:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__and2b (work@sky130_fd_sc_hd__and2b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and2b.functional.v, line:33:1, endln:53:10 + \_module_inst: work@sky130_fd_sc_hd__and2b (work@sky130_fd_sc_hd__and2b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and2b.functional.v, line:33:1, endln:53:10 |vpiName:A_N |vpiDirection:1 |vpiLowConn: @@ -60083,7 +60083,7 @@ design: (work@sky130_fd_sc_hd__and2b) |vpiPort: \_port: (B), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__and2b (work@sky130_fd_sc_hd__and2b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and2b.functional.v, line:33:1, endln:53:10 + \_module_inst: work@sky130_fd_sc_hd__and2b (work@sky130_fd_sc_hd__and2b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and2b.functional.v, line:33:1, endln:53:10 |vpiName:B |vpiDirection:1 |vpiLowConn: @@ -60093,14 +60093,14 @@ design: (work@sky130_fd_sc_hd__and2b) |vpiTypedef: \_logic_typespec: , line:42:12, endln:42:12 |uhdmtopModules: -\_module: work@sky130_fd_sc_hd__and2b (work@sky130_fd_sc_hd__and2b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and2b.functional.v, line:33:1, endln:53:10 +\_module_inst: work@sky130_fd_sc_hd__and2b (work@sky130_fd_sc_hd__and2b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and2b.functional.v, line:33:1, endln:53:10 |vpiName:work@sky130_fd_sc_hd__and2b |vpiDefName:work@sky130_fd_sc_hd__and2b |vpiTop:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__and2b.not0_out), line:45:10, endln:45:18 |vpiParent: - \_module: work@sky130_fd_sc_hd__and2b (work@sky130_fd_sc_hd__and2b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and2b.functional.v, line:33:1, endln:53:10 + \_module_inst: work@sky130_fd_sc_hd__and2b (work@sky130_fd_sc_hd__and2b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and2b.functional.v, line:33:1, endln:53:10 |vpiTypespec: \_logic_typespec: , line:45:5, endln:45:9 |vpiName:not0_out @@ -60109,7 +60109,7 @@ design: (work@sky130_fd_sc_hd__and2b) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__and2b.and0_out_X), line:46:10, endln:46:20 |vpiParent: - \_module: work@sky130_fd_sc_hd__and2b (work@sky130_fd_sc_hd__and2b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and2b.functional.v, line:33:1, endln:53:10 + \_module_inst: work@sky130_fd_sc_hd__and2b (work@sky130_fd_sc_hd__and2b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and2b.functional.v, line:33:1, endln:53:10 |vpiTypespec: \_logic_typespec: , line:46:5, endln:46:9 |vpiName:and0_out_X @@ -60118,7 +60118,7 @@ design: (work@sky130_fd_sc_hd__and2b) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__and2b.X), line:34:5, endln:34:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__and2b (work@sky130_fd_sc_hd__and2b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and2b.functional.v, line:33:1, endln:53:10 + \_module_inst: work@sky130_fd_sc_hd__and2b (work@sky130_fd_sc_hd__and2b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and2b.functional.v, line:33:1, endln:53:10 |vpiTypespec: \_logic_typespec: , line:40:12, endln:40:12 |vpiName:X @@ -60126,7 +60126,7 @@ design: (work@sky130_fd_sc_hd__and2b) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__and2b.A_N), line:35:5, endln:35:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__and2b (work@sky130_fd_sc_hd__and2b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and2b.functional.v, line:33:1, endln:53:10 + \_module_inst: work@sky130_fd_sc_hd__and2b (work@sky130_fd_sc_hd__and2b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and2b.functional.v, line:33:1, endln:53:10 |vpiTypespec: \_logic_typespec: , line:41:12, endln:41:12 |vpiName:A_N @@ -60134,7 +60134,7 @@ design: (work@sky130_fd_sc_hd__and2b) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__and2b.B), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__and2b (work@sky130_fd_sc_hd__and2b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and2b.functional.v, line:33:1, endln:53:10 + \_module_inst: work@sky130_fd_sc_hd__and2b (work@sky130_fd_sc_hd__and2b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and2b.functional.v, line:33:1, endln:53:10 |vpiTypespec: \_logic_typespec: , line:42:12, endln:42:12 |vpiName:B @@ -60143,7 +60143,7 @@ design: (work@sky130_fd_sc_hd__and2b) |vpiPort: \_port: (X), line:34:5, endln:34:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__and2b (work@sky130_fd_sc_hd__and2b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and2b.functional.v, line:33:1, endln:53:10 + \_module_inst: work@sky130_fd_sc_hd__and2b (work@sky130_fd_sc_hd__and2b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and2b.functional.v, line:33:1, endln:53:10 |vpiName:X |vpiDirection:2 |vpiLowConn: @@ -60157,7 +60157,7 @@ design: (work@sky130_fd_sc_hd__and2b) |vpiPort: \_port: (A_N), line:35:5, endln:35:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__and2b (work@sky130_fd_sc_hd__and2b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and2b.functional.v, line:33:1, endln:53:10 + \_module_inst: work@sky130_fd_sc_hd__and2b (work@sky130_fd_sc_hd__and2b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and2b.functional.v, line:33:1, endln:53:10 |vpiName:A_N |vpiDirection:1 |vpiLowConn: @@ -60171,7 +60171,7 @@ design: (work@sky130_fd_sc_hd__and2b) |vpiPort: \_port: (B), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__and2b (work@sky130_fd_sc_hd__and2b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and2b.functional.v, line:33:1, endln:53:10 + \_module_inst: work@sky130_fd_sc_hd__and2b (work@sky130_fd_sc_hd__and2b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and2b.functional.v, line:33:1, endln:53:10 |vpiName:B |vpiDirection:1 |vpiLowConn: @@ -60185,7 +60185,7 @@ design: (work@sky130_fd_sc_hd__and2b) |vpiPrimitive: \_gate: work@not (work@sky130_fd_sc_hd__and2b.not0), line:49:9, endln:49:43 |vpiParent: - \_module: work@sky130_fd_sc_hd__and2b (work@sky130_fd_sc_hd__and2b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and2b.functional.v, line:33:1, endln:53:10 + \_module_inst: work@sky130_fd_sc_hd__and2b (work@sky130_fd_sc_hd__and2b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and2b.functional.v, line:33:1, endln:53:10 |vpiDefName:work@not |vpiName:not0 |vpiFullName:work@sky130_fd_sc_hd__and2b.not0 @@ -60220,7 +60220,7 @@ design: (work@sky130_fd_sc_hd__and2b) |vpiPrimitive: \_gate: work@and (work@sky130_fd_sc_hd__and2b.and0), line:50:9, endln:50:43 |vpiParent: - \_module: work@sky130_fd_sc_hd__and2b (work@sky130_fd_sc_hd__and2b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and2b.functional.v, line:33:1, endln:53:10 + \_module_inst: work@sky130_fd_sc_hd__and2b (work@sky130_fd_sc_hd__and2b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and2b.functional.v, line:33:1, endln:53:10 |vpiDefName:work@and |vpiName:and0 |vpiFullName:work@sky130_fd_sc_hd__and2b.and0 @@ -60269,7 +60269,7 @@ design: (work@sky130_fd_sc_hd__and2b) |vpiPrimitive: \_gate: work@buf (work@sky130_fd_sc_hd__and2b.buf0), line:51:9, endln:51:43 |vpiParent: - \_module: work@sky130_fd_sc_hd__and2b (work@sky130_fd_sc_hd__and2b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and2b.functional.v, line:33:1, endln:53:10 + \_module_inst: work@sky130_fd_sc_hd__and2b (work@sky130_fd_sc_hd__and2b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and2b.functional.v, line:33:1, endln:53:10 |vpiDefName:work@buf |vpiName:buf0 |vpiFullName:work@sky130_fd_sc_hd__and2b.buf0 @@ -60312,7 +60312,7 @@ Processing: -cd cells/cells -DUNIT_DELAY -writepp -parse -nocache -nobuiltin -no design: (work@sky130_fd_sc_hd__a221oi) |vpiName:work@sky130_fd_sc_hd__a221oi |uhdmallModules: -\_module: work@sky130_fd_sc_hd__a221oi (work@sky130_fd_sc_hd__a221oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a221oi.functional.v, line:35:1, endln:63:10 +\_module_inst: work@sky130_fd_sc_hd__a221oi (work@sky130_fd_sc_hd__a221oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a221oi.functional.v, line:35:1, endln:63:10 |vpiParent: \_design: (work@sky130_fd_sc_hd__a221oi) |vpiFullName:work@sky130_fd_sc_hd__a221oi @@ -60320,64 +60320,64 @@ design: (work@sky130_fd_sc_hd__a221oi) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a221oi.and0_out), line:53:10, endln:53:18 |vpiParent: - \_module: work@sky130_fd_sc_hd__a221oi (work@sky130_fd_sc_hd__a221oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a221oi.functional.v, line:35:1, endln:63:10 + \_module_inst: work@sky130_fd_sc_hd__a221oi (work@sky130_fd_sc_hd__a221oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a221oi.functional.v, line:35:1, endln:63:10 |vpiName:and0_out |vpiFullName:work@sky130_fd_sc_hd__a221oi.and0_out |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a221oi.and1_out), line:54:10, endln:54:18 |vpiParent: - \_module: work@sky130_fd_sc_hd__a221oi (work@sky130_fd_sc_hd__a221oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a221oi.functional.v, line:35:1, endln:63:10 + \_module_inst: work@sky130_fd_sc_hd__a221oi (work@sky130_fd_sc_hd__a221oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a221oi.functional.v, line:35:1, endln:63:10 |vpiName:and1_out |vpiFullName:work@sky130_fd_sc_hd__a221oi.and1_out |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a221oi.nor0_out_Y), line:55:10, endln:55:20 |vpiParent: - \_module: work@sky130_fd_sc_hd__a221oi (work@sky130_fd_sc_hd__a221oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a221oi.functional.v, line:35:1, endln:63:10 + \_module_inst: work@sky130_fd_sc_hd__a221oi (work@sky130_fd_sc_hd__a221oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a221oi.functional.v, line:35:1, endln:63:10 |vpiName:nor0_out_Y |vpiFullName:work@sky130_fd_sc_hd__a221oi.nor0_out_Y |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a221oi.Y), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__a221oi (work@sky130_fd_sc_hd__a221oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a221oi.functional.v, line:35:1, endln:63:10 + \_module_inst: work@sky130_fd_sc_hd__a221oi (work@sky130_fd_sc_hd__a221oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a221oi.functional.v, line:35:1, endln:63:10 |vpiName:Y |vpiFullName:work@sky130_fd_sc_hd__a221oi.Y |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a221oi.A1), line:37:5, endln:37:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a221oi (work@sky130_fd_sc_hd__a221oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a221oi.functional.v, line:35:1, endln:63:10 + \_module_inst: work@sky130_fd_sc_hd__a221oi (work@sky130_fd_sc_hd__a221oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a221oi.functional.v, line:35:1, endln:63:10 |vpiName:A1 |vpiFullName:work@sky130_fd_sc_hd__a221oi.A1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a221oi.A2), line:38:5, endln:38:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a221oi (work@sky130_fd_sc_hd__a221oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a221oi.functional.v, line:35:1, endln:63:10 + \_module_inst: work@sky130_fd_sc_hd__a221oi (work@sky130_fd_sc_hd__a221oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a221oi.functional.v, line:35:1, endln:63:10 |vpiName:A2 |vpiFullName:work@sky130_fd_sc_hd__a221oi.A2 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a221oi.B1), line:39:5, endln:39:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a221oi (work@sky130_fd_sc_hd__a221oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a221oi.functional.v, line:35:1, endln:63:10 + \_module_inst: work@sky130_fd_sc_hd__a221oi (work@sky130_fd_sc_hd__a221oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a221oi.functional.v, line:35:1, endln:63:10 |vpiName:B1 |vpiFullName:work@sky130_fd_sc_hd__a221oi.B1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a221oi.B2), line:40:5, endln:40:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a221oi (work@sky130_fd_sc_hd__a221oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a221oi.functional.v, line:35:1, endln:63:10 + \_module_inst: work@sky130_fd_sc_hd__a221oi (work@sky130_fd_sc_hd__a221oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a221oi.functional.v, line:35:1, endln:63:10 |vpiName:B2 |vpiFullName:work@sky130_fd_sc_hd__a221oi.B2 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a221oi.C1), line:41:5, endln:41:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a221oi (work@sky130_fd_sc_hd__a221oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a221oi.functional.v, line:35:1, endln:63:10 + \_module_inst: work@sky130_fd_sc_hd__a221oi (work@sky130_fd_sc_hd__a221oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a221oi.functional.v, line:35:1, endln:63:10 |vpiName:C1 |vpiFullName:work@sky130_fd_sc_hd__a221oi.C1 |vpiPort: \_port: (Y), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__a221oi (work@sky130_fd_sc_hd__a221oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a221oi.functional.v, line:35:1, endln:63:10 + \_module_inst: work@sky130_fd_sc_hd__a221oi (work@sky130_fd_sc_hd__a221oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a221oi.functional.v, line:35:1, endln:63:10 |vpiName:Y |vpiDirection:2 |vpiLowConn: @@ -60389,7 +60389,7 @@ design: (work@sky130_fd_sc_hd__a221oi) |vpiPort: \_port: (A1), line:37:5, endln:37:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a221oi (work@sky130_fd_sc_hd__a221oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a221oi.functional.v, line:35:1, endln:63:10 + \_module_inst: work@sky130_fd_sc_hd__a221oi (work@sky130_fd_sc_hd__a221oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a221oi.functional.v, line:35:1, endln:63:10 |vpiName:A1 |vpiDirection:1 |vpiLowConn: @@ -60401,7 +60401,7 @@ design: (work@sky130_fd_sc_hd__a221oi) |vpiPort: \_port: (A2), line:38:5, endln:38:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a221oi (work@sky130_fd_sc_hd__a221oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a221oi.functional.v, line:35:1, endln:63:10 + \_module_inst: work@sky130_fd_sc_hd__a221oi (work@sky130_fd_sc_hd__a221oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a221oi.functional.v, line:35:1, endln:63:10 |vpiName:A2 |vpiDirection:1 |vpiLowConn: @@ -60413,7 +60413,7 @@ design: (work@sky130_fd_sc_hd__a221oi) |vpiPort: \_port: (B1), line:39:5, endln:39:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a221oi (work@sky130_fd_sc_hd__a221oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a221oi.functional.v, line:35:1, endln:63:10 + \_module_inst: work@sky130_fd_sc_hd__a221oi (work@sky130_fd_sc_hd__a221oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a221oi.functional.v, line:35:1, endln:63:10 |vpiName:B1 |vpiDirection:1 |vpiLowConn: @@ -60425,7 +60425,7 @@ design: (work@sky130_fd_sc_hd__a221oi) |vpiPort: \_port: (B2), line:40:5, endln:40:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a221oi (work@sky130_fd_sc_hd__a221oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a221oi.functional.v, line:35:1, endln:63:10 + \_module_inst: work@sky130_fd_sc_hd__a221oi (work@sky130_fd_sc_hd__a221oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a221oi.functional.v, line:35:1, endln:63:10 |vpiName:B2 |vpiDirection:1 |vpiLowConn: @@ -60437,7 +60437,7 @@ design: (work@sky130_fd_sc_hd__a221oi) |vpiPort: \_port: (C1), line:41:5, endln:41:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a221oi (work@sky130_fd_sc_hd__a221oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a221oi.functional.v, line:35:1, endln:63:10 + \_module_inst: work@sky130_fd_sc_hd__a221oi (work@sky130_fd_sc_hd__a221oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a221oi.functional.v, line:35:1, endln:63:10 |vpiName:C1 |vpiDirection:1 |vpiLowConn: @@ -60447,14 +60447,14 @@ design: (work@sky130_fd_sc_hd__a221oi) |vpiTypedef: \_logic_typespec: , line:50:12, endln:50:12 |uhdmtopModules: -\_module: work@sky130_fd_sc_hd__a221oi (work@sky130_fd_sc_hd__a221oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a221oi.functional.v, line:35:1, endln:63:10 +\_module_inst: work@sky130_fd_sc_hd__a221oi (work@sky130_fd_sc_hd__a221oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a221oi.functional.v, line:35:1, endln:63:10 |vpiName:work@sky130_fd_sc_hd__a221oi |vpiDefName:work@sky130_fd_sc_hd__a221oi |vpiTop:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a221oi.and0_out), line:53:10, endln:53:18 |vpiParent: - \_module: work@sky130_fd_sc_hd__a221oi (work@sky130_fd_sc_hd__a221oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a221oi.functional.v, line:35:1, endln:63:10 + \_module_inst: work@sky130_fd_sc_hd__a221oi (work@sky130_fd_sc_hd__a221oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a221oi.functional.v, line:35:1, endln:63:10 |vpiTypespec: \_logic_typespec: , line:53:5, endln:53:9 |vpiName:and0_out @@ -60463,7 +60463,7 @@ design: (work@sky130_fd_sc_hd__a221oi) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a221oi.and1_out), line:54:10, endln:54:18 |vpiParent: - \_module: work@sky130_fd_sc_hd__a221oi (work@sky130_fd_sc_hd__a221oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a221oi.functional.v, line:35:1, endln:63:10 + \_module_inst: work@sky130_fd_sc_hd__a221oi (work@sky130_fd_sc_hd__a221oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a221oi.functional.v, line:35:1, endln:63:10 |vpiTypespec: \_logic_typespec: , line:54:5, endln:54:9 |vpiName:and1_out @@ -60472,7 +60472,7 @@ design: (work@sky130_fd_sc_hd__a221oi) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a221oi.nor0_out_Y), line:55:10, endln:55:20 |vpiParent: - \_module: work@sky130_fd_sc_hd__a221oi (work@sky130_fd_sc_hd__a221oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a221oi.functional.v, line:35:1, endln:63:10 + \_module_inst: work@sky130_fd_sc_hd__a221oi (work@sky130_fd_sc_hd__a221oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a221oi.functional.v, line:35:1, endln:63:10 |vpiTypespec: \_logic_typespec: , line:55:5, endln:55:9 |vpiName:nor0_out_Y @@ -60481,7 +60481,7 @@ design: (work@sky130_fd_sc_hd__a221oi) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a221oi.Y), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__a221oi (work@sky130_fd_sc_hd__a221oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a221oi.functional.v, line:35:1, endln:63:10 + \_module_inst: work@sky130_fd_sc_hd__a221oi (work@sky130_fd_sc_hd__a221oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a221oi.functional.v, line:35:1, endln:63:10 |vpiTypespec: \_logic_typespec: , line:45:12, endln:45:12 |vpiName:Y @@ -60489,7 +60489,7 @@ design: (work@sky130_fd_sc_hd__a221oi) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a221oi.A1), line:37:5, endln:37:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a221oi (work@sky130_fd_sc_hd__a221oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a221oi.functional.v, line:35:1, endln:63:10 + \_module_inst: work@sky130_fd_sc_hd__a221oi (work@sky130_fd_sc_hd__a221oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a221oi.functional.v, line:35:1, endln:63:10 |vpiTypespec: \_logic_typespec: , line:46:12, endln:46:12 |vpiName:A1 @@ -60497,7 +60497,7 @@ design: (work@sky130_fd_sc_hd__a221oi) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a221oi.A2), line:38:5, endln:38:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a221oi (work@sky130_fd_sc_hd__a221oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a221oi.functional.v, line:35:1, endln:63:10 + \_module_inst: work@sky130_fd_sc_hd__a221oi (work@sky130_fd_sc_hd__a221oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a221oi.functional.v, line:35:1, endln:63:10 |vpiTypespec: \_logic_typespec: , line:47:12, endln:47:12 |vpiName:A2 @@ -60505,7 +60505,7 @@ design: (work@sky130_fd_sc_hd__a221oi) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a221oi.B1), line:39:5, endln:39:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a221oi (work@sky130_fd_sc_hd__a221oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a221oi.functional.v, line:35:1, endln:63:10 + \_module_inst: work@sky130_fd_sc_hd__a221oi (work@sky130_fd_sc_hd__a221oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a221oi.functional.v, line:35:1, endln:63:10 |vpiTypespec: \_logic_typespec: , line:48:12, endln:48:12 |vpiName:B1 @@ -60513,7 +60513,7 @@ design: (work@sky130_fd_sc_hd__a221oi) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a221oi.B2), line:40:5, endln:40:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a221oi (work@sky130_fd_sc_hd__a221oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a221oi.functional.v, line:35:1, endln:63:10 + \_module_inst: work@sky130_fd_sc_hd__a221oi (work@sky130_fd_sc_hd__a221oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a221oi.functional.v, line:35:1, endln:63:10 |vpiTypespec: \_logic_typespec: , line:49:12, endln:49:12 |vpiName:B2 @@ -60521,7 +60521,7 @@ design: (work@sky130_fd_sc_hd__a221oi) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__a221oi.C1), line:41:5, endln:41:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a221oi (work@sky130_fd_sc_hd__a221oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a221oi.functional.v, line:35:1, endln:63:10 + \_module_inst: work@sky130_fd_sc_hd__a221oi (work@sky130_fd_sc_hd__a221oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a221oi.functional.v, line:35:1, endln:63:10 |vpiTypespec: \_logic_typespec: , line:50:12, endln:50:12 |vpiName:C1 @@ -60530,7 +60530,7 @@ design: (work@sky130_fd_sc_hd__a221oi) |vpiPort: \_port: (Y), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__a221oi (work@sky130_fd_sc_hd__a221oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a221oi.functional.v, line:35:1, endln:63:10 + \_module_inst: work@sky130_fd_sc_hd__a221oi (work@sky130_fd_sc_hd__a221oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a221oi.functional.v, line:35:1, endln:63:10 |vpiName:Y |vpiDirection:2 |vpiLowConn: @@ -60544,7 +60544,7 @@ design: (work@sky130_fd_sc_hd__a221oi) |vpiPort: \_port: (A1), line:37:5, endln:37:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a221oi (work@sky130_fd_sc_hd__a221oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a221oi.functional.v, line:35:1, endln:63:10 + \_module_inst: work@sky130_fd_sc_hd__a221oi (work@sky130_fd_sc_hd__a221oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a221oi.functional.v, line:35:1, endln:63:10 |vpiName:A1 |vpiDirection:1 |vpiLowConn: @@ -60558,7 +60558,7 @@ design: (work@sky130_fd_sc_hd__a221oi) |vpiPort: \_port: (A2), line:38:5, endln:38:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a221oi (work@sky130_fd_sc_hd__a221oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a221oi.functional.v, line:35:1, endln:63:10 + \_module_inst: work@sky130_fd_sc_hd__a221oi (work@sky130_fd_sc_hd__a221oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a221oi.functional.v, line:35:1, endln:63:10 |vpiName:A2 |vpiDirection:1 |vpiLowConn: @@ -60572,7 +60572,7 @@ design: (work@sky130_fd_sc_hd__a221oi) |vpiPort: \_port: (B1), line:39:5, endln:39:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a221oi (work@sky130_fd_sc_hd__a221oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a221oi.functional.v, line:35:1, endln:63:10 + \_module_inst: work@sky130_fd_sc_hd__a221oi (work@sky130_fd_sc_hd__a221oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a221oi.functional.v, line:35:1, endln:63:10 |vpiName:B1 |vpiDirection:1 |vpiLowConn: @@ -60586,7 +60586,7 @@ design: (work@sky130_fd_sc_hd__a221oi) |vpiPort: \_port: (B2), line:40:5, endln:40:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a221oi (work@sky130_fd_sc_hd__a221oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a221oi.functional.v, line:35:1, endln:63:10 + \_module_inst: work@sky130_fd_sc_hd__a221oi (work@sky130_fd_sc_hd__a221oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a221oi.functional.v, line:35:1, endln:63:10 |vpiName:B2 |vpiDirection:1 |vpiLowConn: @@ -60600,7 +60600,7 @@ design: (work@sky130_fd_sc_hd__a221oi) |vpiPort: \_port: (C1), line:41:5, endln:41:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__a221oi (work@sky130_fd_sc_hd__a221oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a221oi.functional.v, line:35:1, endln:63:10 + \_module_inst: work@sky130_fd_sc_hd__a221oi (work@sky130_fd_sc_hd__a221oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a221oi.functional.v, line:35:1, endln:63:10 |vpiName:C1 |vpiDirection:1 |vpiLowConn: @@ -60614,7 +60614,7 @@ design: (work@sky130_fd_sc_hd__a221oi) |vpiPrimitive: \_gate: work@and (work@sky130_fd_sc_hd__a221oi.and0), line:58:9, endln:58:50 |vpiParent: - \_module: work@sky130_fd_sc_hd__a221oi (work@sky130_fd_sc_hd__a221oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a221oi.functional.v, line:35:1, endln:63:10 + \_module_inst: work@sky130_fd_sc_hd__a221oi (work@sky130_fd_sc_hd__a221oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a221oi.functional.v, line:35:1, endln:63:10 |vpiDefName:work@and |vpiName:and0 |vpiFullName:work@sky130_fd_sc_hd__a221oi.and0 @@ -60663,7 +60663,7 @@ design: (work@sky130_fd_sc_hd__a221oi) |vpiPrimitive: \_gate: work@and (work@sky130_fd_sc_hd__a221oi.and1), line:59:9, endln:59:50 |vpiParent: - \_module: work@sky130_fd_sc_hd__a221oi (work@sky130_fd_sc_hd__a221oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a221oi.functional.v, line:35:1, endln:63:10 + \_module_inst: work@sky130_fd_sc_hd__a221oi (work@sky130_fd_sc_hd__a221oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a221oi.functional.v, line:35:1, endln:63:10 |vpiDefName:work@and |vpiName:and1 |vpiFullName:work@sky130_fd_sc_hd__a221oi.and1 @@ -60712,7 +60712,7 @@ design: (work@sky130_fd_sc_hd__a221oi) |vpiPrimitive: \_gate: work@nor (work@sky130_fd_sc_hd__a221oi.nor0), line:60:9, endln:60:50 |vpiParent: - \_module: work@sky130_fd_sc_hd__a221oi (work@sky130_fd_sc_hd__a221oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a221oi.functional.v, line:35:1, endln:63:10 + \_module_inst: work@sky130_fd_sc_hd__a221oi (work@sky130_fd_sc_hd__a221oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a221oi.functional.v, line:35:1, endln:63:10 |vpiDefName:work@nor |vpiName:nor0 |vpiFullName:work@sky130_fd_sc_hd__a221oi.nor0 @@ -60775,7 +60775,7 @@ design: (work@sky130_fd_sc_hd__a221oi) |vpiPrimitive: \_gate: work@buf (work@sky130_fd_sc_hd__a221oi.buf0), line:61:9, endln:61:50 |vpiParent: - \_module: work@sky130_fd_sc_hd__a221oi (work@sky130_fd_sc_hd__a221oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a221oi.functional.v, line:35:1, endln:63:10 + \_module_inst: work@sky130_fd_sc_hd__a221oi (work@sky130_fd_sc_hd__a221oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a221oi.functional.v, line:35:1, endln:63:10 |vpiDefName:work@buf |vpiName:buf0 |vpiFullName:work@sky130_fd_sc_hd__a221oi.buf0 @@ -60892,7 +60892,7 @@ design: (work@sky130_fd_sc_hd__dlxtp) |vpiSize:2 |STRING:1 x : 1 : 1 |uhdmallModules: -\_module: work@sky130_fd_sc_hd__dlxtp (work@sky130_fd_sc_hd__dlxtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlxtp.functional.v, line:36:1, endln:54:10 +\_module_inst: work@sky130_fd_sc_hd__dlxtp (work@sky130_fd_sc_hd__dlxtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlxtp.functional.v, line:36:1, endln:54:10 |vpiParent: \_design: (work@sky130_fd_sc_hd__dlxtp) |vpiFullName:work@sky130_fd_sc_hd__dlxtp @@ -60900,32 +60900,32 @@ design: (work@sky130_fd_sc_hd__dlxtp) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__dlxtp.buf_Q), line:48:10, endln:48:15 |vpiParent: - \_module: work@sky130_fd_sc_hd__dlxtp (work@sky130_fd_sc_hd__dlxtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlxtp.functional.v, line:36:1, endln:54:10 + \_module_inst: work@sky130_fd_sc_hd__dlxtp (work@sky130_fd_sc_hd__dlxtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlxtp.functional.v, line:36:1, endln:54:10 |vpiName:buf_Q |vpiFullName:work@sky130_fd_sc_hd__dlxtp.buf_Q |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__dlxtp.Q), line:37:5, endln:37:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__dlxtp (work@sky130_fd_sc_hd__dlxtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlxtp.functional.v, line:36:1, endln:54:10 + \_module_inst: work@sky130_fd_sc_hd__dlxtp (work@sky130_fd_sc_hd__dlxtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlxtp.functional.v, line:36:1, endln:54:10 |vpiName:Q |vpiFullName:work@sky130_fd_sc_hd__dlxtp.Q |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__dlxtp.D), line:38:5, endln:38:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__dlxtp (work@sky130_fd_sc_hd__dlxtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlxtp.functional.v, line:36:1, endln:54:10 + \_module_inst: work@sky130_fd_sc_hd__dlxtp (work@sky130_fd_sc_hd__dlxtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlxtp.functional.v, line:36:1, endln:54:10 |vpiName:D |vpiFullName:work@sky130_fd_sc_hd__dlxtp.D |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__dlxtp.GATE), line:39:5, endln:39:9 |vpiParent: - \_module: work@sky130_fd_sc_hd__dlxtp (work@sky130_fd_sc_hd__dlxtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlxtp.functional.v, line:36:1, endln:54:10 + \_module_inst: work@sky130_fd_sc_hd__dlxtp (work@sky130_fd_sc_hd__dlxtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlxtp.functional.v, line:36:1, endln:54:10 |vpiName:GATE |vpiFullName:work@sky130_fd_sc_hd__dlxtp.GATE |vpiPort: \_port: (Q), line:37:5, endln:37:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__dlxtp (work@sky130_fd_sc_hd__dlxtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlxtp.functional.v, line:36:1, endln:54:10 + \_module_inst: work@sky130_fd_sc_hd__dlxtp (work@sky130_fd_sc_hd__dlxtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlxtp.functional.v, line:36:1, endln:54:10 |vpiName:Q |vpiDirection:2 |vpiLowConn: @@ -60937,7 +60937,7 @@ design: (work@sky130_fd_sc_hd__dlxtp) |vpiPort: \_port: (D), line:38:5, endln:38:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__dlxtp (work@sky130_fd_sc_hd__dlxtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlxtp.functional.v, line:36:1, endln:54:10 + \_module_inst: work@sky130_fd_sc_hd__dlxtp (work@sky130_fd_sc_hd__dlxtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlxtp.functional.v, line:36:1, endln:54:10 |vpiName:D |vpiDirection:1 |vpiLowConn: @@ -60949,7 +60949,7 @@ design: (work@sky130_fd_sc_hd__dlxtp) |vpiPort: \_port: (GATE), line:39:5, endln:39:9 |vpiParent: - \_module: work@sky130_fd_sc_hd__dlxtp (work@sky130_fd_sc_hd__dlxtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlxtp.functional.v, line:36:1, endln:54:10 + \_module_inst: work@sky130_fd_sc_hd__dlxtp (work@sky130_fd_sc_hd__dlxtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlxtp.functional.v, line:36:1, endln:54:10 |vpiName:GATE |vpiDirection:1 |vpiLowConn: @@ -60959,14 +60959,14 @@ design: (work@sky130_fd_sc_hd__dlxtp) |vpiTypedef: \_logic_typespec: , line:45:12, endln:45:12 |uhdmtopModules: -\_module: work@sky130_fd_sc_hd__dlxtp (work@sky130_fd_sc_hd__dlxtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlxtp.functional.v, line:36:1, endln:54:10 +\_module_inst: work@sky130_fd_sc_hd__dlxtp (work@sky130_fd_sc_hd__dlxtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlxtp.functional.v, line:36:1, endln:54:10 |vpiName:work@sky130_fd_sc_hd__dlxtp |vpiDefName:work@sky130_fd_sc_hd__dlxtp |vpiTop:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__dlxtp.buf_Q), line:48:10, endln:48:15 |vpiParent: - \_module: work@sky130_fd_sc_hd__dlxtp (work@sky130_fd_sc_hd__dlxtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlxtp.functional.v, line:36:1, endln:54:10 + \_module_inst: work@sky130_fd_sc_hd__dlxtp (work@sky130_fd_sc_hd__dlxtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlxtp.functional.v, line:36:1, endln:54:10 |vpiTypespec: \_logic_typespec: , line:48:5, endln:48:9 |vpiName:buf_Q @@ -60975,7 +60975,7 @@ design: (work@sky130_fd_sc_hd__dlxtp) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__dlxtp.Q), line:37:5, endln:37:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__dlxtp (work@sky130_fd_sc_hd__dlxtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlxtp.functional.v, line:36:1, endln:54:10 + \_module_inst: work@sky130_fd_sc_hd__dlxtp (work@sky130_fd_sc_hd__dlxtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlxtp.functional.v, line:36:1, endln:54:10 |vpiTypespec: \_logic_typespec: , line:43:12, endln:43:12 |vpiName:Q @@ -60983,7 +60983,7 @@ design: (work@sky130_fd_sc_hd__dlxtp) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__dlxtp.D), line:38:5, endln:38:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__dlxtp (work@sky130_fd_sc_hd__dlxtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlxtp.functional.v, line:36:1, endln:54:10 + \_module_inst: work@sky130_fd_sc_hd__dlxtp (work@sky130_fd_sc_hd__dlxtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlxtp.functional.v, line:36:1, endln:54:10 |vpiTypespec: \_logic_typespec: , line:44:12, endln:44:12 |vpiName:D @@ -60991,7 +60991,7 @@ design: (work@sky130_fd_sc_hd__dlxtp) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__dlxtp.GATE), line:39:5, endln:39:9 |vpiParent: - \_module: work@sky130_fd_sc_hd__dlxtp (work@sky130_fd_sc_hd__dlxtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlxtp.functional.v, line:36:1, endln:54:10 + \_module_inst: work@sky130_fd_sc_hd__dlxtp (work@sky130_fd_sc_hd__dlxtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlxtp.functional.v, line:36:1, endln:54:10 |vpiTypespec: \_logic_typespec: , line:45:12, endln:45:12 |vpiName:GATE @@ -61000,7 +61000,7 @@ design: (work@sky130_fd_sc_hd__dlxtp) |vpiPort: \_port: (Q), line:37:5, endln:37:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__dlxtp (work@sky130_fd_sc_hd__dlxtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlxtp.functional.v, line:36:1, endln:54:10 + \_module_inst: work@sky130_fd_sc_hd__dlxtp (work@sky130_fd_sc_hd__dlxtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlxtp.functional.v, line:36:1, endln:54:10 |vpiName:Q |vpiDirection:2 |vpiLowConn: @@ -61014,7 +61014,7 @@ design: (work@sky130_fd_sc_hd__dlxtp) |vpiPort: \_port: (D), line:38:5, endln:38:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__dlxtp (work@sky130_fd_sc_hd__dlxtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlxtp.functional.v, line:36:1, endln:54:10 + \_module_inst: work@sky130_fd_sc_hd__dlxtp (work@sky130_fd_sc_hd__dlxtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlxtp.functional.v, line:36:1, endln:54:10 |vpiName:D |vpiDirection:1 |vpiLowConn: @@ -61028,7 +61028,7 @@ design: (work@sky130_fd_sc_hd__dlxtp) |vpiPort: \_port: (GATE), line:39:5, endln:39:9 |vpiParent: - \_module: work@sky130_fd_sc_hd__dlxtp (work@sky130_fd_sc_hd__dlxtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlxtp.functional.v, line:36:1, endln:54:10 + \_module_inst: work@sky130_fd_sc_hd__dlxtp (work@sky130_fd_sc_hd__dlxtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlxtp.functional.v, line:36:1, endln:54:10 |vpiName:GATE |vpiDirection:1 |vpiLowConn: @@ -61042,7 +61042,7 @@ design: (work@sky130_fd_sc_hd__dlxtp) |vpiPrimitive: \_udp: work@sky130_fd_sc_hd__udp_dlatch$P (work@sky130_fd_sc_hd__dlxtp.dlatch0), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlxtp.functional.v, line:51:5, endln:51:69 |vpiParent: - \_module: work@sky130_fd_sc_hd__dlxtp (work@sky130_fd_sc_hd__dlxtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlxtp.functional.v, line:36:1, endln:54:10 + \_module_inst: work@sky130_fd_sc_hd__dlxtp (work@sky130_fd_sc_hd__dlxtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlxtp.functional.v, line:36:1, endln:54:10 |vpiDefName:work@sky130_fd_sc_hd__udp_dlatch$P |vpiName:dlatch0 |vpiFullName:work@sky130_fd_sc_hd__dlxtp.dlatch0 @@ -61051,7 +61051,7 @@ design: (work@sky130_fd_sc_hd__dlxtp) |vpiPrimitive: \_gate: work@buf (work@sky130_fd_sc_hd__dlxtp.buf0), line:52:35, endln:52:68 |vpiParent: - \_module: work@sky130_fd_sc_hd__dlxtp (work@sky130_fd_sc_hd__dlxtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlxtp.functional.v, line:36:1, endln:54:10 + \_module_inst: work@sky130_fd_sc_hd__dlxtp (work@sky130_fd_sc_hd__dlxtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlxtp.functional.v, line:36:1, endln:54:10 |vpiDefName:work@buf |vpiName:buf0 |vpiFullName:work@sky130_fd_sc_hd__dlxtp.buf0 @@ -61216,7 +61216,7 @@ design: (work@sky130_fd_sc_hd__dfstp) |vpiSize:3 |STRING:? b ?x : 1 : 1 |uhdmallModules: -\_module: work@sky130_fd_sc_hd__dfstp (work@sky130_fd_sc_hd__dfstp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfstp.functional.v, line:36:1, endln:58:10 +\_module_inst: work@sky130_fd_sc_hd__dfstp (work@sky130_fd_sc_hd__dfstp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfstp.functional.v, line:36:1, endln:58:10 |vpiParent: \_design: (work@sky130_fd_sc_hd__dfstp) |vpiFullName:work@sky130_fd_sc_hd__dfstp @@ -61224,45 +61224,45 @@ design: (work@sky130_fd_sc_hd__dfstp) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__dfstp.buf_Q), line:50:10, endln:50:15 |vpiParent: - \_module: work@sky130_fd_sc_hd__dfstp (work@sky130_fd_sc_hd__dfstp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfstp.functional.v, line:36:1, endln:58:10 + \_module_inst: work@sky130_fd_sc_hd__dfstp (work@sky130_fd_sc_hd__dfstp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfstp.functional.v, line:36:1, endln:58:10 |vpiName:buf_Q |vpiFullName:work@sky130_fd_sc_hd__dfstp.buf_Q |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__dfstp.SET), line:51:10, endln:51:13 |vpiParent: - \_module: work@sky130_fd_sc_hd__dfstp (work@sky130_fd_sc_hd__dfstp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfstp.functional.v, line:36:1, endln:58:10 + \_module_inst: work@sky130_fd_sc_hd__dfstp (work@sky130_fd_sc_hd__dfstp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfstp.functional.v, line:36:1, endln:58:10 |vpiName:SET |vpiFullName:work@sky130_fd_sc_hd__dfstp.SET |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__dfstp.Q), line:37:5, endln:37:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__dfstp (work@sky130_fd_sc_hd__dfstp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfstp.functional.v, line:36:1, endln:58:10 + \_module_inst: work@sky130_fd_sc_hd__dfstp (work@sky130_fd_sc_hd__dfstp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfstp.functional.v, line:36:1, endln:58:10 |vpiName:Q |vpiFullName:work@sky130_fd_sc_hd__dfstp.Q |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__dfstp.CLK), line:38:5, endln:38:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__dfstp (work@sky130_fd_sc_hd__dfstp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfstp.functional.v, line:36:1, endln:58:10 + \_module_inst: work@sky130_fd_sc_hd__dfstp (work@sky130_fd_sc_hd__dfstp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfstp.functional.v, line:36:1, endln:58:10 |vpiName:CLK |vpiFullName:work@sky130_fd_sc_hd__dfstp.CLK |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__dfstp.D), line:39:5, endln:39:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__dfstp (work@sky130_fd_sc_hd__dfstp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfstp.functional.v, line:36:1, endln:58:10 + \_module_inst: work@sky130_fd_sc_hd__dfstp (work@sky130_fd_sc_hd__dfstp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfstp.functional.v, line:36:1, endln:58:10 |vpiName:D |vpiFullName:work@sky130_fd_sc_hd__dfstp.D |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__dfstp.SET_B), line:40:5, endln:40:10 |vpiParent: - \_module: work@sky130_fd_sc_hd__dfstp (work@sky130_fd_sc_hd__dfstp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfstp.functional.v, line:36:1, endln:58:10 + \_module_inst: work@sky130_fd_sc_hd__dfstp (work@sky130_fd_sc_hd__dfstp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfstp.functional.v, line:36:1, endln:58:10 |vpiName:SET_B |vpiFullName:work@sky130_fd_sc_hd__dfstp.SET_B |vpiPort: \_port: (Q), line:37:5, endln:37:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__dfstp (work@sky130_fd_sc_hd__dfstp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfstp.functional.v, line:36:1, endln:58:10 + \_module_inst: work@sky130_fd_sc_hd__dfstp (work@sky130_fd_sc_hd__dfstp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfstp.functional.v, line:36:1, endln:58:10 |vpiName:Q |vpiDirection:2 |vpiLowConn: @@ -61274,7 +61274,7 @@ design: (work@sky130_fd_sc_hd__dfstp) |vpiPort: \_port: (CLK), line:38:5, endln:38:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__dfstp (work@sky130_fd_sc_hd__dfstp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfstp.functional.v, line:36:1, endln:58:10 + \_module_inst: work@sky130_fd_sc_hd__dfstp (work@sky130_fd_sc_hd__dfstp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfstp.functional.v, line:36:1, endln:58:10 |vpiName:CLK |vpiDirection:1 |vpiLowConn: @@ -61286,7 +61286,7 @@ design: (work@sky130_fd_sc_hd__dfstp) |vpiPort: \_port: (D), line:39:5, endln:39:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__dfstp (work@sky130_fd_sc_hd__dfstp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfstp.functional.v, line:36:1, endln:58:10 + \_module_inst: work@sky130_fd_sc_hd__dfstp (work@sky130_fd_sc_hd__dfstp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfstp.functional.v, line:36:1, endln:58:10 |vpiName:D |vpiDirection:1 |vpiLowConn: @@ -61298,7 +61298,7 @@ design: (work@sky130_fd_sc_hd__dfstp) |vpiPort: \_port: (SET_B), line:40:5, endln:40:10 |vpiParent: - \_module: work@sky130_fd_sc_hd__dfstp (work@sky130_fd_sc_hd__dfstp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfstp.functional.v, line:36:1, endln:58:10 + \_module_inst: work@sky130_fd_sc_hd__dfstp (work@sky130_fd_sc_hd__dfstp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfstp.functional.v, line:36:1, endln:58:10 |vpiName:SET_B |vpiDirection:1 |vpiLowConn: @@ -61308,14 +61308,14 @@ design: (work@sky130_fd_sc_hd__dfstp) |vpiTypedef: \_logic_typespec: , line:47:12, endln:47:12 |uhdmtopModules: -\_module: work@sky130_fd_sc_hd__dfstp (work@sky130_fd_sc_hd__dfstp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfstp.functional.v, line:36:1, endln:58:10 +\_module_inst: work@sky130_fd_sc_hd__dfstp (work@sky130_fd_sc_hd__dfstp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfstp.functional.v, line:36:1, endln:58:10 |vpiName:work@sky130_fd_sc_hd__dfstp |vpiDefName:work@sky130_fd_sc_hd__dfstp |vpiTop:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__dfstp.buf_Q), line:50:10, endln:50:15 |vpiParent: - \_module: work@sky130_fd_sc_hd__dfstp (work@sky130_fd_sc_hd__dfstp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfstp.functional.v, line:36:1, endln:58:10 + \_module_inst: work@sky130_fd_sc_hd__dfstp (work@sky130_fd_sc_hd__dfstp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfstp.functional.v, line:36:1, endln:58:10 |vpiTypespec: \_logic_typespec: , line:50:5, endln:50:9 |vpiName:buf_Q @@ -61324,7 +61324,7 @@ design: (work@sky130_fd_sc_hd__dfstp) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__dfstp.SET), line:51:10, endln:51:13 |vpiParent: - \_module: work@sky130_fd_sc_hd__dfstp (work@sky130_fd_sc_hd__dfstp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfstp.functional.v, line:36:1, endln:58:10 + \_module_inst: work@sky130_fd_sc_hd__dfstp (work@sky130_fd_sc_hd__dfstp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfstp.functional.v, line:36:1, endln:58:10 |vpiTypespec: \_logic_typespec: , line:51:5, endln:51:9 |vpiName:SET @@ -61333,7 +61333,7 @@ design: (work@sky130_fd_sc_hd__dfstp) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__dfstp.Q), line:37:5, endln:37:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__dfstp (work@sky130_fd_sc_hd__dfstp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfstp.functional.v, line:36:1, endln:58:10 + \_module_inst: work@sky130_fd_sc_hd__dfstp (work@sky130_fd_sc_hd__dfstp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfstp.functional.v, line:36:1, endln:58:10 |vpiTypespec: \_logic_typespec: , line:44:12, endln:44:12 |vpiName:Q @@ -61341,7 +61341,7 @@ design: (work@sky130_fd_sc_hd__dfstp) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__dfstp.CLK), line:38:5, endln:38:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__dfstp (work@sky130_fd_sc_hd__dfstp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfstp.functional.v, line:36:1, endln:58:10 + \_module_inst: work@sky130_fd_sc_hd__dfstp (work@sky130_fd_sc_hd__dfstp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfstp.functional.v, line:36:1, endln:58:10 |vpiTypespec: \_logic_typespec: , line:45:12, endln:45:12 |vpiName:CLK @@ -61349,7 +61349,7 @@ design: (work@sky130_fd_sc_hd__dfstp) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__dfstp.D), line:39:5, endln:39:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__dfstp (work@sky130_fd_sc_hd__dfstp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfstp.functional.v, line:36:1, endln:58:10 + \_module_inst: work@sky130_fd_sc_hd__dfstp (work@sky130_fd_sc_hd__dfstp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfstp.functional.v, line:36:1, endln:58:10 |vpiTypespec: \_logic_typespec: , line:46:12, endln:46:12 |vpiName:D @@ -61357,7 +61357,7 @@ design: (work@sky130_fd_sc_hd__dfstp) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__dfstp.SET_B), line:40:5, endln:40:10 |vpiParent: - \_module: work@sky130_fd_sc_hd__dfstp (work@sky130_fd_sc_hd__dfstp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfstp.functional.v, line:36:1, endln:58:10 + \_module_inst: work@sky130_fd_sc_hd__dfstp (work@sky130_fd_sc_hd__dfstp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfstp.functional.v, line:36:1, endln:58:10 |vpiTypespec: \_logic_typespec: , line:47:12, endln:47:12 |vpiName:SET_B @@ -61366,7 +61366,7 @@ design: (work@sky130_fd_sc_hd__dfstp) |vpiPort: \_port: (Q), line:37:5, endln:37:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__dfstp (work@sky130_fd_sc_hd__dfstp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfstp.functional.v, line:36:1, endln:58:10 + \_module_inst: work@sky130_fd_sc_hd__dfstp (work@sky130_fd_sc_hd__dfstp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfstp.functional.v, line:36:1, endln:58:10 |vpiName:Q |vpiDirection:2 |vpiLowConn: @@ -61380,7 +61380,7 @@ design: (work@sky130_fd_sc_hd__dfstp) |vpiPort: \_port: (CLK), line:38:5, endln:38:8 |vpiParent: - \_module: work@sky130_fd_sc_hd__dfstp (work@sky130_fd_sc_hd__dfstp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfstp.functional.v, line:36:1, endln:58:10 + \_module_inst: work@sky130_fd_sc_hd__dfstp (work@sky130_fd_sc_hd__dfstp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfstp.functional.v, line:36:1, endln:58:10 |vpiName:CLK |vpiDirection:1 |vpiLowConn: @@ -61394,7 +61394,7 @@ design: (work@sky130_fd_sc_hd__dfstp) |vpiPort: \_port: (D), line:39:5, endln:39:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__dfstp (work@sky130_fd_sc_hd__dfstp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfstp.functional.v, line:36:1, endln:58:10 + \_module_inst: work@sky130_fd_sc_hd__dfstp (work@sky130_fd_sc_hd__dfstp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfstp.functional.v, line:36:1, endln:58:10 |vpiName:D |vpiDirection:1 |vpiLowConn: @@ -61408,7 +61408,7 @@ design: (work@sky130_fd_sc_hd__dfstp) |vpiPort: \_port: (SET_B), line:40:5, endln:40:10 |vpiParent: - \_module: work@sky130_fd_sc_hd__dfstp (work@sky130_fd_sc_hd__dfstp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfstp.functional.v, line:36:1, endln:58:10 + \_module_inst: work@sky130_fd_sc_hd__dfstp (work@sky130_fd_sc_hd__dfstp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfstp.functional.v, line:36:1, endln:58:10 |vpiName:SET_B |vpiDirection:1 |vpiLowConn: @@ -61422,7 +61422,7 @@ design: (work@sky130_fd_sc_hd__dfstp) |vpiPrimitive: \_gate: work@not (work@sky130_fd_sc_hd__dfstp.not0), line:54:45, endln:54:75 |vpiParent: - \_module: work@sky130_fd_sc_hd__dfstp (work@sky130_fd_sc_hd__dfstp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfstp.functional.v, line:36:1, endln:58:10 + \_module_inst: work@sky130_fd_sc_hd__dfstp (work@sky130_fd_sc_hd__dfstp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfstp.functional.v, line:36:1, endln:58:10 |vpiDefName:work@not |vpiName:not0 |vpiFullName:work@sky130_fd_sc_hd__dfstp.not0 @@ -61457,7 +61457,7 @@ design: (work@sky130_fd_sc_hd__dfstp) |vpiPrimitive: \_udp: work@sky130_fd_sc_hd__udp_dff$PS (work@sky130_fd_sc_hd__dfstp.dff0), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfstp.functional.v, line:55:5, endln:55:65 |vpiParent: - \_module: work@sky130_fd_sc_hd__dfstp (work@sky130_fd_sc_hd__dfstp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfstp.functional.v, line:36:1, endln:58:10 + \_module_inst: work@sky130_fd_sc_hd__dfstp (work@sky130_fd_sc_hd__dfstp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfstp.functional.v, line:36:1, endln:58:10 |vpiDefName:work@sky130_fd_sc_hd__udp_dff$PS |vpiName:dff0 |vpiFullName:work@sky130_fd_sc_hd__dfstp.dff0 @@ -61466,7 +61466,7 @@ design: (work@sky130_fd_sc_hd__dfstp) |vpiPrimitive: \_gate: work@buf (work@sky130_fd_sc_hd__dfstp.buf0), line:56:45, endln:56:75 |vpiParent: - \_module: work@sky130_fd_sc_hd__dfstp (work@sky130_fd_sc_hd__dfstp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfstp.functional.v, line:36:1, endln:58:10 + \_module_inst: work@sky130_fd_sc_hd__dfstp (work@sky130_fd_sc_hd__dfstp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfstp.functional.v, line:36:1, endln:58:10 |vpiDefName:work@buf |vpiName:buf0 |vpiFullName:work@sky130_fd_sc_hd__dfstp.buf0 @@ -61509,7 +61509,7 @@ Processing: -cd cells/cells -DUNIT_DELAY -writepp -parse -nocache -nobuiltin -no design: (work@sky130_fd_sc_hd__conb) |vpiName:work@sky130_fd_sc_hd__conb |uhdmallModules: -\_module: work@sky130_fd_sc_hd__conb (work@sky130_fd_sc_hd__conb), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__conb.functional.v, line:33:1, endln:46:10 +\_module_inst: work@sky130_fd_sc_hd__conb (work@sky130_fd_sc_hd__conb), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__conb.functional.v, line:33:1, endln:46:10 |vpiParent: \_design: (work@sky130_fd_sc_hd__conb) |vpiFullName:work@sky130_fd_sc_hd__conb @@ -61517,19 +61517,19 @@ design: (work@sky130_fd_sc_hd__conb) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__conb.HI), line:34:5, endln:34:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__conb (work@sky130_fd_sc_hd__conb), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__conb.functional.v, line:33:1, endln:46:10 + \_module_inst: work@sky130_fd_sc_hd__conb (work@sky130_fd_sc_hd__conb), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__conb.functional.v, line:33:1, endln:46:10 |vpiName:HI |vpiFullName:work@sky130_fd_sc_hd__conb.HI |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__conb.LO), line:35:5, endln:35:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__conb (work@sky130_fd_sc_hd__conb), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__conb.functional.v, line:33:1, endln:46:10 + \_module_inst: work@sky130_fd_sc_hd__conb (work@sky130_fd_sc_hd__conb), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__conb.functional.v, line:33:1, endln:46:10 |vpiName:LO |vpiFullName:work@sky130_fd_sc_hd__conb.LO |vpiPort: \_port: (HI), line:34:5, endln:34:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__conb (work@sky130_fd_sc_hd__conb), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__conb.functional.v, line:33:1, endln:46:10 + \_module_inst: work@sky130_fd_sc_hd__conb (work@sky130_fd_sc_hd__conb), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__conb.functional.v, line:33:1, endln:46:10 |vpiName:HI |vpiDirection:2 |vpiLowConn: @@ -61541,7 +61541,7 @@ design: (work@sky130_fd_sc_hd__conb) |vpiPort: \_port: (LO), line:35:5, endln:35:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__conb (work@sky130_fd_sc_hd__conb), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__conb.functional.v, line:33:1, endln:46:10 + \_module_inst: work@sky130_fd_sc_hd__conb (work@sky130_fd_sc_hd__conb), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__conb.functional.v, line:33:1, endln:46:10 |vpiName:LO |vpiDirection:2 |vpiLowConn: @@ -61551,14 +61551,14 @@ design: (work@sky130_fd_sc_hd__conb) |vpiTypedef: \_logic_typespec: , line:40:12, endln:40:12 |uhdmtopModules: -\_module: work@sky130_fd_sc_hd__conb (work@sky130_fd_sc_hd__conb), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__conb.functional.v, line:33:1, endln:46:10 +\_module_inst: work@sky130_fd_sc_hd__conb (work@sky130_fd_sc_hd__conb), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__conb.functional.v, line:33:1, endln:46:10 |vpiName:work@sky130_fd_sc_hd__conb |vpiDefName:work@sky130_fd_sc_hd__conb |vpiTop:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__conb.HI), line:34:5, endln:34:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__conb (work@sky130_fd_sc_hd__conb), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__conb.functional.v, line:33:1, endln:46:10 + \_module_inst: work@sky130_fd_sc_hd__conb (work@sky130_fd_sc_hd__conb), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__conb.functional.v, line:33:1, endln:46:10 |vpiTypespec: \_logic_typespec: , line:39:12, endln:39:12 |vpiName:HI @@ -61566,7 +61566,7 @@ design: (work@sky130_fd_sc_hd__conb) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__conb.LO), line:35:5, endln:35:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__conb (work@sky130_fd_sc_hd__conb), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__conb.functional.v, line:33:1, endln:46:10 + \_module_inst: work@sky130_fd_sc_hd__conb (work@sky130_fd_sc_hd__conb), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__conb.functional.v, line:33:1, endln:46:10 |vpiTypespec: \_logic_typespec: , line:40:12, endln:40:12 |vpiName:LO @@ -61575,7 +61575,7 @@ design: (work@sky130_fd_sc_hd__conb) |vpiPort: \_port: (HI), line:34:5, endln:34:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__conb (work@sky130_fd_sc_hd__conb), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__conb.functional.v, line:33:1, endln:46:10 + \_module_inst: work@sky130_fd_sc_hd__conb (work@sky130_fd_sc_hd__conb), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__conb.functional.v, line:33:1, endln:46:10 |vpiName:HI |vpiDirection:2 |vpiLowConn: @@ -61589,7 +61589,7 @@ design: (work@sky130_fd_sc_hd__conb) |vpiPort: \_port: (LO), line:35:5, endln:35:7 |vpiParent: - \_module: work@sky130_fd_sc_hd__conb (work@sky130_fd_sc_hd__conb), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__conb.functional.v, line:33:1, endln:46:10 + \_module_inst: work@sky130_fd_sc_hd__conb (work@sky130_fd_sc_hd__conb), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__conb.functional.v, line:33:1, endln:46:10 |vpiName:LO |vpiDirection:2 |vpiLowConn: @@ -61603,7 +61603,7 @@ design: (work@sky130_fd_sc_hd__conb) |vpiPrimitive: \_gate: work@pullup (work@sky130_fd_sc_hd__conb.pullup0), line:43:14, endln:43:32 |vpiParent: - \_module: work@sky130_fd_sc_hd__conb (work@sky130_fd_sc_hd__conb), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__conb.functional.v, line:33:1, endln:46:10 + \_module_inst: work@sky130_fd_sc_hd__conb (work@sky130_fd_sc_hd__conb), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__conb.functional.v, line:33:1, endln:46:10 |vpiDefName:work@pullup |vpiName:pullup0 |vpiFullName:work@sky130_fd_sc_hd__conb.pullup0 @@ -61624,7 +61624,7 @@ design: (work@sky130_fd_sc_hd__conb) |vpiPrimitive: \_gate: work@pulldown (work@sky130_fd_sc_hd__conb.pulldown0), line:44:14, endln:44:32 |vpiParent: - \_module: work@sky130_fd_sc_hd__conb (work@sky130_fd_sc_hd__conb), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__conb.functional.v, line:33:1, endln:46:10 + \_module_inst: work@sky130_fd_sc_hd__conb (work@sky130_fd_sc_hd__conb), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__conb.functional.v, line:33:1, endln:46:10 |vpiDefName:work@pulldown |vpiName:pulldown0 |vpiFullName:work@sky130_fd_sc_hd__conb.pulldown0 @@ -61653,7 +61653,7 @@ Processing: -cd cells/cells -DUNIT_DELAY -writepp -parse -nocache -nobuiltin -no design: (work@sky130_fd_sc_hd__nor4) |vpiName:work@sky130_fd_sc_hd__nor4 |uhdmallModules: -\_module: work@sky130_fd_sc_hd__nor4 (work@sky130_fd_sc_hd__nor4), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor4.functional.v, line:35:1, endln:57:10 +\_module_inst: work@sky130_fd_sc_hd__nor4 (work@sky130_fd_sc_hd__nor4), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor4.functional.v, line:35:1, endln:57:10 |vpiParent: \_design: (work@sky130_fd_sc_hd__nor4) |vpiFullName:work@sky130_fd_sc_hd__nor4 @@ -61661,44 +61661,44 @@ design: (work@sky130_fd_sc_hd__nor4) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__nor4.nor0_out_Y), line:51:10, endln:51:20 |vpiParent: - \_module: work@sky130_fd_sc_hd__nor4 (work@sky130_fd_sc_hd__nor4), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor4.functional.v, line:35:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__nor4 (work@sky130_fd_sc_hd__nor4), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor4.functional.v, line:35:1, endln:57:10 |vpiName:nor0_out_Y |vpiFullName:work@sky130_fd_sc_hd__nor4.nor0_out_Y |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__nor4.Y), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__nor4 (work@sky130_fd_sc_hd__nor4), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor4.functional.v, line:35:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__nor4 (work@sky130_fd_sc_hd__nor4), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor4.functional.v, line:35:1, endln:57:10 |vpiName:Y |vpiFullName:work@sky130_fd_sc_hd__nor4.Y |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__nor4.A), line:37:5, endln:37:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__nor4 (work@sky130_fd_sc_hd__nor4), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor4.functional.v, line:35:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__nor4 (work@sky130_fd_sc_hd__nor4), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor4.functional.v, line:35:1, endln:57:10 |vpiName:A |vpiFullName:work@sky130_fd_sc_hd__nor4.A |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__nor4.B), line:38:5, endln:38:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__nor4 (work@sky130_fd_sc_hd__nor4), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor4.functional.v, line:35:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__nor4 (work@sky130_fd_sc_hd__nor4), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor4.functional.v, line:35:1, endln:57:10 |vpiName:B |vpiFullName:work@sky130_fd_sc_hd__nor4.B |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__nor4.C), line:39:5, endln:39:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__nor4 (work@sky130_fd_sc_hd__nor4), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor4.functional.v, line:35:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__nor4 (work@sky130_fd_sc_hd__nor4), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor4.functional.v, line:35:1, endln:57:10 |vpiName:C |vpiFullName:work@sky130_fd_sc_hd__nor4.C |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__nor4.D), line:40:5, endln:40:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__nor4 (work@sky130_fd_sc_hd__nor4), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor4.functional.v, line:35:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__nor4 (work@sky130_fd_sc_hd__nor4), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor4.functional.v, line:35:1, endln:57:10 |vpiName:D |vpiFullName:work@sky130_fd_sc_hd__nor4.D |vpiPort: \_port: (Y), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__nor4 (work@sky130_fd_sc_hd__nor4), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor4.functional.v, line:35:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__nor4 (work@sky130_fd_sc_hd__nor4), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor4.functional.v, line:35:1, endln:57:10 |vpiName:Y |vpiDirection:2 |vpiLowConn: @@ -61710,7 +61710,7 @@ design: (work@sky130_fd_sc_hd__nor4) |vpiPort: \_port: (A), line:37:5, endln:37:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__nor4 (work@sky130_fd_sc_hd__nor4), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor4.functional.v, line:35:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__nor4 (work@sky130_fd_sc_hd__nor4), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor4.functional.v, line:35:1, endln:57:10 |vpiName:A |vpiDirection:1 |vpiLowConn: @@ -61722,7 +61722,7 @@ design: (work@sky130_fd_sc_hd__nor4) |vpiPort: \_port: (B), line:38:5, endln:38:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__nor4 (work@sky130_fd_sc_hd__nor4), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor4.functional.v, line:35:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__nor4 (work@sky130_fd_sc_hd__nor4), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor4.functional.v, line:35:1, endln:57:10 |vpiName:B |vpiDirection:1 |vpiLowConn: @@ -61734,7 +61734,7 @@ design: (work@sky130_fd_sc_hd__nor4) |vpiPort: \_port: (C), line:39:5, endln:39:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__nor4 (work@sky130_fd_sc_hd__nor4), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor4.functional.v, line:35:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__nor4 (work@sky130_fd_sc_hd__nor4), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor4.functional.v, line:35:1, endln:57:10 |vpiName:C |vpiDirection:1 |vpiLowConn: @@ -61746,7 +61746,7 @@ design: (work@sky130_fd_sc_hd__nor4) |vpiPort: \_port: (D), line:40:5, endln:40:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__nor4 (work@sky130_fd_sc_hd__nor4), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor4.functional.v, line:35:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__nor4 (work@sky130_fd_sc_hd__nor4), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor4.functional.v, line:35:1, endln:57:10 |vpiName:D |vpiDirection:1 |vpiLowConn: @@ -61756,14 +61756,14 @@ design: (work@sky130_fd_sc_hd__nor4) |vpiTypedef: \_logic_typespec: , line:48:12, endln:48:12 |uhdmtopModules: -\_module: work@sky130_fd_sc_hd__nor4 (work@sky130_fd_sc_hd__nor4), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor4.functional.v, line:35:1, endln:57:10 +\_module_inst: work@sky130_fd_sc_hd__nor4 (work@sky130_fd_sc_hd__nor4), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor4.functional.v, line:35:1, endln:57:10 |vpiName:work@sky130_fd_sc_hd__nor4 |vpiDefName:work@sky130_fd_sc_hd__nor4 |vpiTop:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__nor4.nor0_out_Y), line:51:10, endln:51:20 |vpiParent: - \_module: work@sky130_fd_sc_hd__nor4 (work@sky130_fd_sc_hd__nor4), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor4.functional.v, line:35:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__nor4 (work@sky130_fd_sc_hd__nor4), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor4.functional.v, line:35:1, endln:57:10 |vpiTypespec: \_logic_typespec: , line:51:5, endln:51:9 |vpiName:nor0_out_Y @@ -61772,7 +61772,7 @@ design: (work@sky130_fd_sc_hd__nor4) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__nor4.Y), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__nor4 (work@sky130_fd_sc_hd__nor4), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor4.functional.v, line:35:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__nor4 (work@sky130_fd_sc_hd__nor4), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor4.functional.v, line:35:1, endln:57:10 |vpiTypespec: \_logic_typespec: , line:44:12, endln:44:12 |vpiName:Y @@ -61780,7 +61780,7 @@ design: (work@sky130_fd_sc_hd__nor4) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__nor4.A), line:37:5, endln:37:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__nor4 (work@sky130_fd_sc_hd__nor4), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor4.functional.v, line:35:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__nor4 (work@sky130_fd_sc_hd__nor4), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor4.functional.v, line:35:1, endln:57:10 |vpiTypespec: \_logic_typespec: , line:45:12, endln:45:12 |vpiName:A @@ -61788,7 +61788,7 @@ design: (work@sky130_fd_sc_hd__nor4) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__nor4.B), line:38:5, endln:38:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__nor4 (work@sky130_fd_sc_hd__nor4), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor4.functional.v, line:35:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__nor4 (work@sky130_fd_sc_hd__nor4), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor4.functional.v, line:35:1, endln:57:10 |vpiTypespec: \_logic_typespec: , line:46:12, endln:46:12 |vpiName:B @@ -61796,7 +61796,7 @@ design: (work@sky130_fd_sc_hd__nor4) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__nor4.C), line:39:5, endln:39:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__nor4 (work@sky130_fd_sc_hd__nor4), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor4.functional.v, line:35:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__nor4 (work@sky130_fd_sc_hd__nor4), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor4.functional.v, line:35:1, endln:57:10 |vpiTypespec: \_logic_typespec: , line:47:12, endln:47:12 |vpiName:C @@ -61804,7 +61804,7 @@ design: (work@sky130_fd_sc_hd__nor4) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__nor4.D), line:40:5, endln:40:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__nor4 (work@sky130_fd_sc_hd__nor4), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor4.functional.v, line:35:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__nor4 (work@sky130_fd_sc_hd__nor4), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor4.functional.v, line:35:1, endln:57:10 |vpiTypespec: \_logic_typespec: , line:48:12, endln:48:12 |vpiName:D @@ -61813,7 +61813,7 @@ design: (work@sky130_fd_sc_hd__nor4) |vpiPort: \_port: (Y), line:36:5, endln:36:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__nor4 (work@sky130_fd_sc_hd__nor4), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor4.functional.v, line:35:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__nor4 (work@sky130_fd_sc_hd__nor4), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor4.functional.v, line:35:1, endln:57:10 |vpiName:Y |vpiDirection:2 |vpiLowConn: @@ -61827,7 +61827,7 @@ design: (work@sky130_fd_sc_hd__nor4) |vpiPort: \_port: (A), line:37:5, endln:37:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__nor4 (work@sky130_fd_sc_hd__nor4), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor4.functional.v, line:35:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__nor4 (work@sky130_fd_sc_hd__nor4), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor4.functional.v, line:35:1, endln:57:10 |vpiName:A |vpiDirection:1 |vpiLowConn: @@ -61841,7 +61841,7 @@ design: (work@sky130_fd_sc_hd__nor4) |vpiPort: \_port: (B), line:38:5, endln:38:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__nor4 (work@sky130_fd_sc_hd__nor4), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor4.functional.v, line:35:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__nor4 (work@sky130_fd_sc_hd__nor4), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor4.functional.v, line:35:1, endln:57:10 |vpiName:B |vpiDirection:1 |vpiLowConn: @@ -61855,7 +61855,7 @@ design: (work@sky130_fd_sc_hd__nor4) |vpiPort: \_port: (C), line:39:5, endln:39:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__nor4 (work@sky130_fd_sc_hd__nor4), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor4.functional.v, line:35:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__nor4 (work@sky130_fd_sc_hd__nor4), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor4.functional.v, line:35:1, endln:57:10 |vpiName:C |vpiDirection:1 |vpiLowConn: @@ -61869,7 +61869,7 @@ design: (work@sky130_fd_sc_hd__nor4) |vpiPort: \_port: (D), line:40:5, endln:40:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__nor4 (work@sky130_fd_sc_hd__nor4), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor4.functional.v, line:35:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__nor4 (work@sky130_fd_sc_hd__nor4), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor4.functional.v, line:35:1, endln:57:10 |vpiName:D |vpiDirection:1 |vpiLowConn: @@ -61883,7 +61883,7 @@ design: (work@sky130_fd_sc_hd__nor4) |vpiPrimitive: \_gate: work@nor (work@sky130_fd_sc_hd__nor4.nor0), line:54:9, endln:54:43 |vpiParent: - \_module: work@sky130_fd_sc_hd__nor4 (work@sky130_fd_sc_hd__nor4), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor4.functional.v, line:35:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__nor4 (work@sky130_fd_sc_hd__nor4), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor4.functional.v, line:35:1, endln:57:10 |vpiDefName:work@nor |vpiName:nor0 |vpiFullName:work@sky130_fd_sc_hd__nor4.nor0 @@ -61960,7 +61960,7 @@ design: (work@sky130_fd_sc_hd__nor4) |vpiPrimitive: \_gate: work@buf (work@sky130_fd_sc_hd__nor4.buf0), line:55:9, endln:55:43 |vpiParent: - \_module: work@sky130_fd_sc_hd__nor4 (work@sky130_fd_sc_hd__nor4), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor4.functional.v, line:35:1, endln:57:10 + \_module_inst: work@sky130_fd_sc_hd__nor4 (work@sky130_fd_sc_hd__nor4), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor4.functional.v, line:35:1, endln:57:10 |vpiDefName:work@buf |vpiName:buf0 |vpiFullName:work@sky130_fd_sc_hd__nor4.buf0 @@ -62003,7 +62003,7 @@ Processing: -cd cells/cells -DUNIT_DELAY -writepp -parse -nocache -nobuiltin -no design: (work@sky130_fd_sc_hd__dlygate4sd3) |vpiName:work@sky130_fd_sc_hd__dlygate4sd3 |uhdmallModules: -\_module: work@sky130_fd_sc_hd__dlygate4sd3 (work@sky130_fd_sc_hd__dlygate4sd3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlygate4sd3.functional.v, line:33:1, endln:49:10 +\_module_inst: work@sky130_fd_sc_hd__dlygate4sd3 (work@sky130_fd_sc_hd__dlygate4sd3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlygate4sd3.functional.v, line:33:1, endln:49:10 |vpiParent: \_design: (work@sky130_fd_sc_hd__dlygate4sd3) |vpiFullName:work@sky130_fd_sc_hd__dlygate4sd3 @@ -62011,26 +62011,26 @@ design: (work@sky130_fd_sc_hd__dlygate4sd3) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__dlygate4sd3.buf0_out_X), line:43:10, endln:43:20 |vpiParent: - \_module: work@sky130_fd_sc_hd__dlygate4sd3 (work@sky130_fd_sc_hd__dlygate4sd3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlygate4sd3.functional.v, line:33:1, endln:49:10 + \_module_inst: work@sky130_fd_sc_hd__dlygate4sd3 (work@sky130_fd_sc_hd__dlygate4sd3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlygate4sd3.functional.v, line:33:1, endln:49:10 |vpiName:buf0_out_X |vpiFullName:work@sky130_fd_sc_hd__dlygate4sd3.buf0_out_X |vpiNetType:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__dlygate4sd3.X), line:34:5, endln:34:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__dlygate4sd3 (work@sky130_fd_sc_hd__dlygate4sd3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlygate4sd3.functional.v, line:33:1, endln:49:10 + \_module_inst: work@sky130_fd_sc_hd__dlygate4sd3 (work@sky130_fd_sc_hd__dlygate4sd3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlygate4sd3.functional.v, line:33:1, endln:49:10 |vpiName:X |vpiFullName:work@sky130_fd_sc_hd__dlygate4sd3.X |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__dlygate4sd3.A), line:35:5, endln:35:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__dlygate4sd3 (work@sky130_fd_sc_hd__dlygate4sd3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlygate4sd3.functional.v, line:33:1, endln:49:10 + \_module_inst: work@sky130_fd_sc_hd__dlygate4sd3 (work@sky130_fd_sc_hd__dlygate4sd3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlygate4sd3.functional.v, line:33:1, endln:49:10 |vpiName:A |vpiFullName:work@sky130_fd_sc_hd__dlygate4sd3.A |vpiPort: \_port: (X), line:34:5, endln:34:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__dlygate4sd3 (work@sky130_fd_sc_hd__dlygate4sd3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlygate4sd3.functional.v, line:33:1, endln:49:10 + \_module_inst: work@sky130_fd_sc_hd__dlygate4sd3 (work@sky130_fd_sc_hd__dlygate4sd3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlygate4sd3.functional.v, line:33:1, endln:49:10 |vpiName:X |vpiDirection:2 |vpiLowConn: @@ -62042,7 +62042,7 @@ design: (work@sky130_fd_sc_hd__dlygate4sd3) |vpiPort: \_port: (A), line:35:5, endln:35:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__dlygate4sd3 (work@sky130_fd_sc_hd__dlygate4sd3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlygate4sd3.functional.v, line:33:1, endln:49:10 + \_module_inst: work@sky130_fd_sc_hd__dlygate4sd3 (work@sky130_fd_sc_hd__dlygate4sd3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlygate4sd3.functional.v, line:33:1, endln:49:10 |vpiName:A |vpiDirection:1 |vpiLowConn: @@ -62052,14 +62052,14 @@ design: (work@sky130_fd_sc_hd__dlygate4sd3) |vpiTypedef: \_logic_typespec: , line:40:12, endln:40:12 |uhdmtopModules: -\_module: work@sky130_fd_sc_hd__dlygate4sd3 (work@sky130_fd_sc_hd__dlygate4sd3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlygate4sd3.functional.v, line:33:1, endln:49:10 +\_module_inst: work@sky130_fd_sc_hd__dlygate4sd3 (work@sky130_fd_sc_hd__dlygate4sd3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlygate4sd3.functional.v, line:33:1, endln:49:10 |vpiName:work@sky130_fd_sc_hd__dlygate4sd3 |vpiDefName:work@sky130_fd_sc_hd__dlygate4sd3 |vpiTop:1 |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__dlygate4sd3.buf0_out_X), line:43:10, endln:43:20 |vpiParent: - \_module: work@sky130_fd_sc_hd__dlygate4sd3 (work@sky130_fd_sc_hd__dlygate4sd3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlygate4sd3.functional.v, line:33:1, endln:49:10 + \_module_inst: work@sky130_fd_sc_hd__dlygate4sd3 (work@sky130_fd_sc_hd__dlygate4sd3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlygate4sd3.functional.v, line:33:1, endln:49:10 |vpiTypespec: \_logic_typespec: , line:43:5, endln:43:9 |vpiName:buf0_out_X @@ -62068,7 +62068,7 @@ design: (work@sky130_fd_sc_hd__dlygate4sd3) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__dlygate4sd3.X), line:34:5, endln:34:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__dlygate4sd3 (work@sky130_fd_sc_hd__dlygate4sd3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlygate4sd3.functional.v, line:33:1, endln:49:10 + \_module_inst: work@sky130_fd_sc_hd__dlygate4sd3 (work@sky130_fd_sc_hd__dlygate4sd3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlygate4sd3.functional.v, line:33:1, endln:49:10 |vpiTypespec: \_logic_typespec: , line:39:12, endln:39:12 |vpiName:X @@ -62076,7 +62076,7 @@ design: (work@sky130_fd_sc_hd__dlygate4sd3) |vpiNet: \_logic_net: (work@sky130_fd_sc_hd__dlygate4sd3.A), line:35:5, endln:35:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__dlygate4sd3 (work@sky130_fd_sc_hd__dlygate4sd3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlygate4sd3.functional.v, line:33:1, endln:49:10 + \_module_inst: work@sky130_fd_sc_hd__dlygate4sd3 (work@sky130_fd_sc_hd__dlygate4sd3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlygate4sd3.functional.v, line:33:1, endln:49:10 |vpiTypespec: \_logic_typespec: , line:40:12, endln:40:12 |vpiName:A @@ -62085,7 +62085,7 @@ design: (work@sky130_fd_sc_hd__dlygate4sd3) |vpiPort: \_port: (X), line:34:5, endln:34:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__dlygate4sd3 (work@sky130_fd_sc_hd__dlygate4sd3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlygate4sd3.functional.v, line:33:1, endln:49:10 + \_module_inst: work@sky130_fd_sc_hd__dlygate4sd3 (work@sky130_fd_sc_hd__dlygate4sd3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlygate4sd3.functional.v, line:33:1, endln:49:10 |vpiName:X |vpiDirection:2 |vpiLowConn: @@ -62099,7 +62099,7 @@ design: (work@sky130_fd_sc_hd__dlygate4sd3) |vpiPort: \_port: (A), line:35:5, endln:35:6 |vpiParent: - \_module: work@sky130_fd_sc_hd__dlygate4sd3 (work@sky130_fd_sc_hd__dlygate4sd3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlygate4sd3.functional.v, line:33:1, endln:49:10 + \_module_inst: work@sky130_fd_sc_hd__dlygate4sd3 (work@sky130_fd_sc_hd__dlygate4sd3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlygate4sd3.functional.v, line:33:1, endln:49:10 |vpiName:A |vpiDirection:1 |vpiLowConn: @@ -62113,7 +62113,7 @@ design: (work@sky130_fd_sc_hd__dlygate4sd3) |vpiPrimitive: \_gate: work@buf (work@sky130_fd_sc_hd__dlygate4sd3.buf0), line:46:9, endln:46:43 |vpiParent: - \_module: work@sky130_fd_sc_hd__dlygate4sd3 (work@sky130_fd_sc_hd__dlygate4sd3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlygate4sd3.functional.v, line:33:1, endln:49:10 + \_module_inst: work@sky130_fd_sc_hd__dlygate4sd3 (work@sky130_fd_sc_hd__dlygate4sd3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlygate4sd3.functional.v, line:33:1, endln:49:10 |vpiDefName:work@buf |vpiName:buf0 |vpiFullName:work@sky130_fd_sc_hd__dlygate4sd3.buf0 @@ -62148,7 +62148,7 @@ design: (work@sky130_fd_sc_hd__dlygate4sd3) |vpiPrimitive: \_gate: work@buf (work@sky130_fd_sc_hd__dlygate4sd3.buf1), line:47:9, endln:47:43 |vpiParent: - \_module: work@sky130_fd_sc_hd__dlygate4sd3 (work@sky130_fd_sc_hd__dlygate4sd3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlygate4sd3.functional.v, line:33:1, endln:49:10 + \_module_inst: work@sky130_fd_sc_hd__dlygate4sd3 (work@sky130_fd_sc_hd__dlygate4sd3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlygate4sd3.functional.v, line:33:1, endln:49:10 |vpiDefName:work@buf |vpiName:buf1 |vpiFullName:work@sky130_fd_sc_hd__dlygate4sd3.buf1 diff --git a/third_party/tests/Tnoc/Tnoc.log b/third_party/tests/Tnoc/Tnoc.log index c2c56a2e06..9a14aace81 100644 --- a/third_party/tests/Tnoc/Tnoc.log +++ b/third_party/tests/Tnoc/Tnoc.log @@ -24155,8 +24155,8 @@ import_typespec 33 indexed_part_select 2 int_typespec 739292 int_var 156 -interface 24779 interface_array 989 +interface_inst 24779 interface_typespec 40659 io_decl 97940 logic_net 9501 @@ -24164,7 +24164,7 @@ logic_typespec 71267 logic_var 49617 method_func_call 2197 modport 23337 -module 93535 +module_inst 93535 operation 428941 package 8 packed_array_typespec 8656 diff --git a/third_party/tests/UVMNestedSeq/UVMNestedSeq.log b/third_party/tests/UVMNestedSeq/UVMNestedSeq.log index 8dfe4c36c8..fa97e17484 100644 --- a/third_party/tests/UVMNestedSeq/UVMNestedSeq.log +++ b/third_party/tests/UVMNestedSeq/UVMNestedSeq.log @@ -905,7 +905,7 @@ indexed_part_select 201 initial 2 int_typespec 9398 int_var 4059 -interface 4 +interface_inst 4 interface_typespec 7 io_decl 18988 logic_net 352 @@ -914,7 +914,7 @@ logic_var 116 long_int_typespec 259 long_int_var 23 method_func_call 27624 -module 31 +module_inst 31 named_begin 30 named_event 8 named_fork 11 diff --git a/third_party/tests/UVMSwitch/UVMSwitch.log b/third_party/tests/UVMSwitch/UVMSwitch.log index 83dae65e6e..039664698c 100644 --- a/third_party/tests/UVMSwitch/UVMSwitch.log +++ b/third_party/tests/UVMSwitch/UVMSwitch.log @@ -6965,7 +6965,7 @@ int_typespec 3564 int_var 1223 integer_typespec 9 integer_var 9 -interface 17 +interface_inst 17 interface_typespec 6 io_decl 6968 logic_net 564 @@ -6975,7 +6975,7 @@ long_int_typespec 99 long_int_var 7 method_func_call 8201 modport 17 -module 42 +module_inst 42 named_begin 7 named_event 8 named_fork 3 diff --git a/third_party/tests/UnitAmiqEth/UnitAmiqEth.log b/third_party/tests/UnitAmiqEth/UnitAmiqEth.log index 256b2abbfa..493c7f987a 100644 --- a/third_party/tests/UnitAmiqEth/UnitAmiqEth.log +++ b/third_party/tests/UnitAmiqEth/UnitAmiqEth.log @@ -1336,7 +1336,7 @@ logic_var 86 long_int_typespec 139 long_int_var 11 method_func_call 16167 -module 46 +module_inst 46 named_begin 12 named_event 14 named_fork 9 diff --git a/third_party/tests/YosysBigSim/aes_5cycle_2stage/YosysBigSimAes.log b/third_party/tests/YosysBigSim/aes_5cycle_2stage/YosysBigSimAes.log index 01ba74a9ec..41cb3ea347 100644 --- a/third_party/tests/YosysBigSim/aes_5cycle_2stage/YosysBigSimAes.log +++ b/third_party/tests/YosysBigSim/aes_5cycle_2stage/YosysBigSimAes.log @@ -55,7 +55,7 @@ io_decl 6 logic_net 495 logic_typespec 288 logic_var 15 -module 102 +module_inst 102 operation 247 param_assign 32 parameter 32 diff --git a/third_party/tests/YosysBigSim/amber23/YosysBigSimAmber23.log b/third_party/tests/YosysBigSim/amber23/YosysBigSimAmber23.log index f0f92a982c..7f094c121b 100644 --- a/third_party/tests/YosysBigSim/amber23/YosysBigSimAmber23.log +++ b/third_party/tests/YosysBigSim/amber23/YosysBigSimAmber23.log @@ -532,7 +532,7 @@ io_decl 75 logic_net 1795 logic_typespec 1839 logic_var 202 -module 107 +module_inst 107 named_event 1 operation 6021 param_assign 1220 diff --git a/third_party/tests/YosysBigSim/elliptic_curve_group/YosysBigSimEllip.log b/third_party/tests/YosysBigSim/elliptic_curve_group/YosysBigSimEllip.log index dde1a1ac37..9eb5c9e169 100644 --- a/third_party/tests/YosysBigSim/elliptic_curve_group/YosysBigSimEllip.log +++ b/third_party/tests/YosysBigSim/elliptic_curve_group/YosysBigSimEllip.log @@ -196,7 +196,7 @@ io_decl 11 logic_net 853 logic_typespec 147 logic_var 1 -module 30 +module_inst 30 operation 373 package 2 part_select 249 diff --git a/third_party/tests/YosysBigSim/lm32/YosysBigSimLm32.log b/third_party/tests/YosysBigSim/lm32/YosysBigSimLm32.log index 4ef02c309e..132c0b652a 100644 --- a/third_party/tests/YosysBigSim/lm32/YosysBigSimLm32.log +++ b/third_party/tests/YosysBigSim/lm32/YosysBigSimLm32.log @@ -203,7 +203,7 @@ integer_typespec 6 integer_var 6 logic_net 1841 logic_typespec 1770 -module 87 +module_inst 87 operation 3678 param_assign 215 parameter 235 diff --git a/third_party/tests/YosysBigSim/openmsp430/YosysBigSimOpenMsp.log b/third_party/tests/YosysBigSim/openmsp430/YosysBigSimOpenMsp.log index 29bd1e5f17..0666810622 100644 --- a/third_party/tests/YosysBigSim/openmsp430/YosysBigSimOpenMsp.log +++ b/third_party/tests/YosysBigSim/openmsp430/YosysBigSimOpenMsp.log @@ -163,7 +163,7 @@ io_decl 16 logic_net 2207 logic_typespec 1949 logic_var 9 -module 65 +module_inst 65 named_event 1 operation 3558 package 2 diff --git a/third_party/tests/YosysBigSim/reed_solomon_decoder/YosysBigSimReed.log b/third_party/tests/YosysBigSim/reed_solomon_decoder/YosysBigSimReed.log index f7ad34d42a..dbdfd40482 100644 --- a/third_party/tests/YosysBigSim/reed_solomon_decoder/YosysBigSimReed.log +++ b/third_party/tests/YosysBigSim/reed_solomon_decoder/YosysBigSimReed.log @@ -108,7 +108,7 @@ integer_typespec 9 integer_var 12 logic_net 1372 logic_typespec 788 -module 75 +module_inst 75 operation 991 param_assign 140 parameter 140 diff --git a/third_party/tests/YosysBigSim/softusb_navre/YosysBigSimSoft.log b/third_party/tests/YosysBigSim/softusb_navre/YosysBigSimSoft.log index 8c0aa24377..a7706cf3b3 100644 --- a/third_party/tests/YosysBigSim/softusb_navre/YosysBigSimSoft.log +++ b/third_party/tests/YosysBigSim/softusb_navre/YosysBigSimSoft.log @@ -56,7 +56,7 @@ integer_typespec 4 integer_var 4 logic_net 229 logic_typespec 144 -module 10 +module_inst 10 named_event 1 operation 261 param_assign 96 diff --git a/third_party/tests/YosysBigSim/verilog-pong/YosysBigSimPong.log b/third_party/tests/YosysBigSim/verilog-pong/YosysBigSimPong.log index 3f4fd7a1c3..6dbfde839c 100644 --- a/third_party/tests/YosysBigSim/verilog-pong/YosysBigSimPong.log +++ b/third_party/tests/YosysBigSim/verilog-pong/YosysBigSimPong.log @@ -69,7 +69,7 @@ integer_typespec 1 integer_var 5 logic_net 271 logic_typespec 172 -module 32 +module_inst 32 operation 314 param_assign 46 parameter 46 diff --git a/third_party/tests/YosysBoom/YosysSmallBoom.log b/third_party/tests/YosysBoom/YosysSmallBoom.log index fc214e2a83..292f9617ea 100644 --- a/third_party/tests/YosysBoom/YosysSmallBoom.log +++ b/third_party/tests/YosysBoom/YosysSmallBoom.log @@ -2053,7 +2053,7 @@ io_decl 11 logic_net 171465 logic_typespec 128001 logic_var 1 -module 1933 +module_inst 1933 named_begin 1 operation 81869 package 2 diff --git a/third_party/tests/YosysCam/YosysCam.log b/third_party/tests/YosysCam/YosysCam.log index d14dab9cd1..f70afe8357 100644 --- a/third_party/tests/YosysCam/YosysCam.log +++ b/third_party/tests/YosysCam/YosysCam.log @@ -1450,7 +1450,7 @@ io_decl 11 logic_net 1877 logic_typespec 2217 logic_var 1 -module 752 +module_inst 752 operation 11053 package 2 param_assign 374 diff --git a/third_party/tests/YosysDsp/YosysDsp.log b/third_party/tests/YosysDsp/YosysDsp.log index 9c030b42c9..02af0224e8 100644 --- a/third_party/tests/YosysDsp/YosysDsp.log +++ b/third_party/tests/YosysDsp/YosysDsp.log @@ -2893,7 +2893,7 @@ io_decl 11 logic_net 6118 logic_typespec 9131 logic_var 1 -module 1490 +module_inst 1490 operation 16253 package 2 param_assign 2124 diff --git a/third_party/tests/YosysEth/YosysEth.log b/third_party/tests/YosysEth/YosysEth.log index fd4dc64636..3bcaa596c7 100644 --- a/third_party/tests/YosysEth/YosysEth.log +++ b/third_party/tests/YosysEth/YosysEth.log @@ -89,7 +89,7 @@ io_decl 11 logic_net 252 logic_typespec 378 logic_var 1 -module 7 +module_inst 7 operation 4 package 2 param_assign 21 diff --git a/third_party/tests/YosysIce40/YosysIce40.log b/third_party/tests/YosysIce40/YosysIce40.log index d48a3f79c7..2ba088b64c 100644 --- a/third_party/tests/YosysIce40/YosysIce40.log +++ b/third_party/tests/YosysIce40/YosysIce40.log @@ -648,8 +648,8 @@ io_decl 11 logic_net 4340 logic_typespec 3433 logic_var 1 -module 205 module_array 1 +module_inst 205 module_typespec 1 operation 3668 package 2 diff --git a/third_party/tests/YosysMarlann/YosysMarlann.log b/third_party/tests/YosysMarlann/YosysMarlann.log index 39c90355bf..025cfb33d5 100644 --- a/third_party/tests/YosysMarlann/YosysMarlann.log +++ b/third_party/tests/YosysMarlann/YosysMarlann.log @@ -67,8 +67,8 @@ io_decl 11 logic_net 276 logic_typespec 185 logic_var 1 -module 23 module_array 2 +module_inst 23 module_typespec 2 operation 353 package 2 diff --git a/third_party/tests/YosysOldTests/aes_core/YosysOldAes.log b/third_party/tests/YosysOldTests/aes_core/YosysOldAes.log index d56f638987..f43bb834bf 100644 --- a/third_party/tests/YosysOldTests/aes_core/YosysOldAes.log +++ b/third_party/tests/YosysOldTests/aes_core/YosysOldAes.log @@ -73,7 +73,7 @@ io_decl 26 logic_net 528 logic_typespec 360 logic_var 43 -module 107 +module_inst 107 operation 325 package 2 param_assign 32 diff --git a/third_party/tests/YosysOldTests/i2c/YosysOldI2c.log b/third_party/tests/YosysOldTests/i2c/YosysOldI2c.log index 1740709d0d..d88de040ba 100644 --- a/third_party/tests/YosysOldTests/i2c/YosysOldI2c.log +++ b/third_party/tests/YosysOldTests/i2c/YosysOldI2c.log @@ -67,7 +67,7 @@ io_decl 11 logic_net 210 logic_typespec 214 logic_var 1 -module 14 +module_inst 14 operation 126 package 2 param_assign 50 diff --git a/third_party/tests/YosysOldTests/openmsp430/YosysOldOpen.log b/third_party/tests/YosysOldTests/openmsp430/YosysOldOpen.log index c87cbcfa2f..27b3b8b369 100644 --- a/third_party/tests/YosysOldTests/openmsp430/YosysOldOpen.log +++ b/third_party/tests/YosysOldTests/openmsp430/YosysOldOpen.log @@ -187,7 +187,7 @@ io_decl 16 logic_net 2265 logic_typespec 2047 logic_var 9 -module 75 +module_inst 75 operation 3729 package 2 param_assign 222 diff --git a/third_party/tests/YosysOldTests/or1200/YosysOldOr.log b/third_party/tests/YosysOldTests/or1200/YosysOldOr.log index 781d22bafe..99fd901a7e 100644 --- a/third_party/tests/YosysOldTests/or1200/YosysOldOr.log +++ b/third_party/tests/YosysOldTests/or1200/YosysOldOr.log @@ -530,7 +530,7 @@ io_decl 14 logic_net 16855 logic_typespec 28186 logic_var 5 -module 3928 +module_inst 3928 operation 19906 package 2 param_assign 385 diff --git a/third_party/tests/YosysOldTests/sasc/YosysOldSasc.log b/third_party/tests/YosysOldTests/sasc/YosysOldSasc.log index 44f99f5828..883e5f2440 100644 --- a/third_party/tests/YosysOldTests/sasc/YosysOldSasc.log +++ b/third_party/tests/YosysOldTests/sasc/YosysOldSasc.log @@ -58,7 +58,7 @@ if_stmt 2 include_file_info 3 logic_net 572 logic_typespec 391 -module 12 +module_inst 12 operation 584 part_select 1 port 67 diff --git a/third_party/tests/YosysOldTests/simple_spi/YosysOldSimpleSpi.log b/third_party/tests/YosysOldTests/simple_spi/YosysOldSimpleSpi.log index a2f1128ab3..c20075662e 100644 --- a/third_party/tests/YosysOldTests/simple_spi/YosysOldSimpleSpi.log +++ b/third_party/tests/YosysOldTests/simple_spi/YosysOldSimpleSpi.log @@ -59,7 +59,7 @@ io_decl 11 logic_net 153 logic_typespec 126 logic_var 1 -module 11 +module_inst 11 operation 122 package 2 param_assign 3 diff --git a/third_party/tests/YosysOldTests/spi/YosysOldSpi.log b/third_party/tests/YosysOldTests/spi/YosysOldSpi.log index f0b14789a2..7a74ad7b25 100644 --- a/third_party/tests/YosysOldTests/spi/YosysOldSpi.log +++ b/third_party/tests/YosysOldTests/spi/YosysOldSpi.log @@ -70,7 +70,7 @@ io_decl 11 logic_net 144 logic_typespec 158 logic_var 1 -module 14 +module_inst 14 operation 338 package 2 param_assign 6 diff --git a/third_party/tests/YosysOldTests/ss_pcm/YosysOldSsPcm.log b/third_party/tests/YosysOldTests/ss_pcm/YosysOldSsPcm.log index 041fd1a29c..0cc9fa702a 100644 --- a/third_party/tests/YosysOldTests/ss_pcm/YosysOldSsPcm.log +++ b/third_party/tests/YosysOldTests/ss_pcm/YosysOldSsPcm.log @@ -37,7 +37,7 @@ if_stmt 12 include_file_info 1 logic_net 70 logic_typespec 42 -module 4 +module_inst 4 operation 54 part_select 7 port 22 diff --git a/third_party/tests/YosysOldTests/systemcaes/YosysOldSystem.log b/third_party/tests/YosysOldTests/systemcaes/YosysOldSystem.log index c6b00ce8b7..135b97d1ef 100644 --- a/third_party/tests/YosysOldTests/systemcaes/YosysOldSystem.log +++ b/third_party/tests/YosysOldTests/systemcaes/YosysOldSystem.log @@ -389,7 +389,7 @@ io_decl 12 logic_net 453 logic_typespec 284 logic_var 3 -module 27 +module_inst 27 operation 370 package 2 part_select 123 diff --git a/third_party/tests/YosysOldTests/usb_phy/YosysOldUsb.log b/third_party/tests/YosysOldTests/usb_phy/YosysOldUsb.log index 38bb8cd00c..aa04e30ce5 100644 --- a/third_party/tests/YosysOldTests/usb_phy/YosysOldUsb.log +++ b/third_party/tests/YosysOldTests/usb_phy/YosysOldUsb.log @@ -61,7 +61,7 @@ io_decl 11 logic_net 230 logic_typespec 162 logic_var 1 -module 13 +module_inst 13 operation 246 package 2 param_assign 28 diff --git a/third_party/tests/YosysRiscv/YosysRiscv.log b/third_party/tests/YosysRiscv/YosysRiscv.log index a871571881..b1fbe3c9c1 100644 --- a/third_party/tests/YosysRiscv/YosysRiscv.log +++ b/third_party/tests/YosysRiscv/YosysRiscv.log @@ -176,7 +176,7 @@ io_decl 14 logic_net 499 logic_typespec 461 logic_var 6 -module 179 +module_inst 179 operation 1148 package 2 param_assign 210 diff --git a/third_party/tests/YosysSmall/YosysSmall.log b/third_party/tests/YosysSmall/YosysSmall.log index 5afb4f36d4..dab7cc3a4f 100644 --- a/third_party/tests/YosysSmall/YosysSmall.log +++ b/third_party/tests/YosysSmall/YosysSmall.log @@ -89,7 +89,7 @@ io_decl 11 logic_net 58 logic_typespec 56 logic_var 1 -module 14 +module_inst 14 operation 32 package 2 part_select 1 diff --git a/third_party/tests/YosysVerx/YosysVerx.log b/third_party/tests/YosysVerx/YosysVerx.log index 9f59d19d98..a9af98c0ea 100644 --- a/third_party/tests/YosysVerx/YosysVerx.log +++ b/third_party/tests/YosysVerx/YosysVerx.log @@ -72,7 +72,7 @@ io_decl 11 logic_net 1721 logic_typespec 125 logic_var 1 -module 4 +module_inst 4 operation 1334 package 2 part_select 281 diff --git a/third_party/tests/oh/BasicOh.log b/third_party/tests/oh/BasicOh.log index 4f18d23502..8d4d7fc34d 100644 --- a/third_party/tests/oh/BasicOh.log +++ b/third_party/tests/oh/BasicOh.log @@ -2,563 +2,563 @@ [INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dffrqn.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao32.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_and3.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockmux.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_sync.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_or4.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa42.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_edgealign.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao221.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi31.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mx2.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai33.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux7.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi32.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mult.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_nor4.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_sdffqn.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockor.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_datagate.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_nor3.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa31.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mxi3.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao22.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_nand4.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_nor4.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_reg0.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux12.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux8.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_debouncer.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_reg1.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_edge2pulse.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ser2par.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_arbiter.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dffqn.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_isobuflo.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_sdffrqn.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_rsync.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_shift.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_nor3.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai32.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_isobufhi.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockmux4.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_tristate.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao311.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao222.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa33.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_or2.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_edge2pulse.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai21.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi311.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_latnq.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi221.v". + +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_latq.v". + +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_and2.v". + +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockmux2.v". [INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_and4.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_xnor4.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_7seg_decode.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockgate.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa42.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_pulse2pulse.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_or3.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux2.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_pulse2pulse.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux9.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fall2pulse.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi211.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa62.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockmux2.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_memory_sp.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_xnor2.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux9.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_sdffq.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dffsq.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_bitreverse.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux3.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockmux4.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_lat0.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_standby.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa92.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_bin2onehot.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_sdffrq.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockor.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_sdffq.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_stretcher.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_abs.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai311.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai222.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oddr.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mxi4.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_xor4.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_latnq.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dffrq.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux5.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mxi2.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai221.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockmux.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mx3.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa211.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mult.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_header.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux2.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_memory_dp.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai21.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_sdffrq.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai31.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_or3.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao221.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao32.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa22.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi21.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockgate.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_nand4.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dffrq.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao211.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_datagate.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa222.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux4.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dffnq.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_or2.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi221.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux12.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa21.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao22.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_shift.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dffnq.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_cdc.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_sdffqn.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_reg0.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_reg1.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mx2.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai32.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_tristate.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mx3.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi22.v". [INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_add.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_inv.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_par2ser.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao33.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_xor3.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockdiv.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_bin2onehot.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux6.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa222.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fall2pulse.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockdiv.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dffq.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi21.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_buffer.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_iddr.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai22.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_bitreverse.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi33.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_nor2.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_or4.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux6.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_iddr.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_pll.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux4.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_xnor4.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_delay.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mxi2.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_abs.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_and3.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_xor3.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi211.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi222.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mx4.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mxi3.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa211.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_edgealign.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_rise2pulse.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux5.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_rsync.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_bin2gray.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa221.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mxi4.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_sync.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_nor2.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_stretcher.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_xor2.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dffsqn.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao31.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux7.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_rise2pulse.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_inv.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_lat1.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa311.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mx4.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_memory_dp.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dsync.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_delay.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa221.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_isobufhi.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_sdffsq.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_header.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ser2par.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao222.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_lat0.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi33.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa62.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_sdffsq.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dffsq.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_xnor3.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_nand3.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_standby.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_sdffrqn.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oddr.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa33.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_arbiter.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_and2.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi222.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_memory_sp.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa32.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_buf.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_debouncer.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi32.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dsync.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux3.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dffq.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_par2ser.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai311.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi31.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_pwr_buf.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi22.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao31.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_pll.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_buffer.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_nand3.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux8.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_parity.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai33.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa32.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_regfile.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dffrqn.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa22.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_xnor2.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao311.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_sdffsqn.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_pwr_buf.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa31.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_gray2bin.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao211.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi311.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai22.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao21.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa21.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai31.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_isobuflo.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai221.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_xor4.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa311.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao33.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa32.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_regfile.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_latq.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_buf.v". [INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_counter.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_7seg_decode.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_cdc.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai222.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_bin2gray.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_xnor3.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_gray2bin.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_sdffsqn.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_xor2.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa32.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_lat1.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_parity.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao21.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa92.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dffqn.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao32.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dffsqn.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockmux.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_or4.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dffrqn.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_edgealign.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_and3.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi31.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_sync.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai33.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa42.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi32.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao221.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_nor4.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mx2.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockor.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux7.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_nor3.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mult.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mxi3.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_sdffqn.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_nand4.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_datagate.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_reg0.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa31.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux8.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao22.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_reg1.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_nor4.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ser2par.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux12.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dffqn.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_debouncer.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_sdffrqn.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_edge2pulse.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_shift.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_arbiter.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai32.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_isobuflo.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockmux4.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_rsync.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao311.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_nor3.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa33.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_isobufhi.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_edge2pulse.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_tristate.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi311.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao222.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi221.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_or2.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_latq.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai21.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_and2.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_latnq.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockmux2.v". [INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_and4.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_xnor4.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_7seg_decode.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockgate.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa42.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_pulse2pulse.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_or3.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux2.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_pulse2pulse.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux9.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fall2pulse.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi211.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa62.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockmux2.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_memory_sp.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_xnor2.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux9.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_sdffq.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dffsq.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_bitreverse.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux3.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockmux4.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_lat0.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_standby.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa92.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_bin2onehot.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_sdffrq.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockor.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_sdffq.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_stretcher.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_abs.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai311.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai222.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oddr.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mxi4.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_xor4.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_latnq.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dffrq.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux5.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mxi2.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai221.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockmux.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mx3.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa211.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mult.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_header.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux2.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_memory_dp.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai21.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_sdffrq.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai31.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_or3.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao221.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao32.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa22.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi21.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockgate.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_nand4.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dffrq.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao211.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_datagate.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa222.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux4.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dffnq.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_or2.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi221.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux12.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa21.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao22.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_shift.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dffnq.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_cdc.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_sdffqn.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_reg0.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_reg1.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mx2.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai32.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_tristate.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mx3.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi22.v". [INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_add.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_inv.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_par2ser.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao33.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_xor3.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockdiv.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_bin2onehot.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux6.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa222.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fall2pulse.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockdiv.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dffq.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi21.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_buffer.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_iddr.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai22.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_bitreverse.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi33.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_nor2.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_or4.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux6.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_iddr.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_pll.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux4.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_xnor4.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_delay.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mxi2.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_abs.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_and3.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_xor3.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi211.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi222.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mx4.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mxi3.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa211.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_edgealign.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_rise2pulse.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux5.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_rsync.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_bin2gray.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa221.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mxi4.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_sync.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_nor2.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_stretcher.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_xor2.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dffsqn.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao31.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux7.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_rise2pulse.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_inv.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_lat1.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa311.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mx4.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_memory_dp.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dsync.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_delay.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa221.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_isobufhi.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_sdffsq.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_header.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ser2par.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao222.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_lat0.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi33.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa62.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_sdffsq.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dffsq.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_xnor3.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_nand3.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_standby.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_sdffrqn.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oddr.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa33.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_arbiter.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_and2.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi222.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_memory_sp.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa32.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_buf.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_debouncer.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi32.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dsync.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux3.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dffq.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_par2ser.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai311.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi31.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_pwr_buf.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi22.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao31.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_pll.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_buffer.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_nand3.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux8.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_parity.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai33.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa32.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_regfile.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dffrqn.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa22.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_xnor2.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao311.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_sdffsqn.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_pwr_buf.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa31.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_gray2bin.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao211.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi311.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai22.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao21.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa21.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai31.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_isobuflo.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai221.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_xor4.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa311.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao33.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa32.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_regfile.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_latq.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_buf.v". [INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_counter.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_7seg_decode.v". - -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai222.v". - -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_xnor3.v". - -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_sdffsqn.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_cdc.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa32.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_bin2gray.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_parity.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_gray2bin.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa92.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_xor2.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dffqn.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_lat1.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dffsqn.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao21.v". [INF:CM0029] Using global timescale: "1ns/1ns". @@ -1291,8 +1291,8 @@ io_decl 11 logic_net 1063 logic_typespec 1096 logic_var 1 -module 331 module_array 4 +module_inst 331 module_typespec 4 operation 1904 package 2 @@ -1341,8 +1341,8 @@ io_decl 22 logic_net 1063 logic_typespec 1096 logic_var 1 -module 331 module_array 4 +module_inst 331 module_typespec 4 operation 2248 package 2 @@ -1846,7 +1846,7 @@ design: (work@oh_fifo_async) \_int_typespec: |vpiSigned:1 |uhdmallModules: -\_module: work@oh_7seg_decode (work@oh_7seg_decode), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_7seg_decode.v, line:8:1, endln:40:10 +\_module_inst: work@oh_7seg_decode (work@oh_7seg_decode), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_7seg_decode.v, line:8:1, endln:40:10 |vpiParent: \_design: (work@oh_fifo_async) |vpiFullName:work@oh_7seg_decode @@ -1855,55 +1855,55 @@ design: (work@oh_fifo_async) |vpiNet: \_logic_net: (work@oh_7seg_decode.bcd), line:10:17, endln:10:20 |vpiParent: - \_module: work@oh_7seg_decode (work@oh_7seg_decode), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_7seg_decode.v, line:8:1, endln:40:10 + \_module_inst: work@oh_7seg_decode (work@oh_7seg_decode), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_7seg_decode.v, line:8:1, endln:40:10 |vpiName:bcd |vpiFullName:work@oh_7seg_decode.bcd |vpiNet: \_logic_net: (work@oh_7seg_decode.a), line:11:13, endln:11:14 |vpiParent: - \_module: work@oh_7seg_decode (work@oh_7seg_decode), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_7seg_decode.v, line:8:1, endln:40:10 + \_module_inst: work@oh_7seg_decode (work@oh_7seg_decode), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_7seg_decode.v, line:8:1, endln:40:10 |vpiName:a |vpiFullName:work@oh_7seg_decode.a |vpiNet: \_logic_net: (work@oh_7seg_decode.b), line:12:13, endln:12:14 |vpiParent: - \_module: work@oh_7seg_decode (work@oh_7seg_decode), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_7seg_decode.v, line:8:1, endln:40:10 + \_module_inst: work@oh_7seg_decode (work@oh_7seg_decode), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_7seg_decode.v, line:8:1, endln:40:10 |vpiName:b |vpiFullName:work@oh_7seg_decode.b |vpiNet: \_logic_net: (work@oh_7seg_decode.c), line:13:13, endln:13:14 |vpiParent: - \_module: work@oh_7seg_decode (work@oh_7seg_decode), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_7seg_decode.v, line:8:1, endln:40:10 + \_module_inst: work@oh_7seg_decode (work@oh_7seg_decode), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_7seg_decode.v, line:8:1, endln:40:10 |vpiName:c |vpiFullName:work@oh_7seg_decode.c |vpiNet: \_logic_net: (work@oh_7seg_decode.d), line:14:13, endln:14:14 |vpiParent: - \_module: work@oh_7seg_decode (work@oh_7seg_decode), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_7seg_decode.v, line:8:1, endln:40:10 + \_module_inst: work@oh_7seg_decode (work@oh_7seg_decode), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_7seg_decode.v, line:8:1, endln:40:10 |vpiName:d |vpiFullName:work@oh_7seg_decode.d |vpiNet: \_logic_net: (work@oh_7seg_decode.e), line:15:13, endln:15:14 |vpiParent: - \_module: work@oh_7seg_decode (work@oh_7seg_decode), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_7seg_decode.v, line:8:1, endln:40:10 + \_module_inst: work@oh_7seg_decode (work@oh_7seg_decode), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_7seg_decode.v, line:8:1, endln:40:10 |vpiName:e |vpiFullName:work@oh_7seg_decode.e |vpiNet: \_logic_net: (work@oh_7seg_decode.f), line:16:13, endln:16:14 |vpiParent: - \_module: work@oh_7seg_decode (work@oh_7seg_decode), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_7seg_decode.v, line:8:1, endln:40:10 + \_module_inst: work@oh_7seg_decode (work@oh_7seg_decode), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_7seg_decode.v, line:8:1, endln:40:10 |vpiName:f |vpiFullName:work@oh_7seg_decode.f |vpiNet: \_logic_net: (work@oh_7seg_decode.g), line:17:13, endln:17:14 |vpiParent: - \_module: work@oh_7seg_decode (work@oh_7seg_decode), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_7seg_decode.v, line:8:1, endln:40:10 + \_module_inst: work@oh_7seg_decode (work@oh_7seg_decode), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_7seg_decode.v, line:8:1, endln:40:10 |vpiName:g |vpiFullName:work@oh_7seg_decode.g |vpiPort: \_port: (bcd), line:10:17, endln:10:20 |vpiParent: - \_module: work@oh_7seg_decode (work@oh_7seg_decode), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_7seg_decode.v, line:8:1, endln:40:10 + \_module_inst: work@oh_7seg_decode (work@oh_7seg_decode), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_7seg_decode.v, line:8:1, endln:40:10 |vpiName:bcd |vpiDirection:1 |vpiLowConn: @@ -1933,7 +1933,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (a), line:11:13, endln:11:14 |vpiParent: - \_module: work@oh_7seg_decode (work@oh_7seg_decode), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_7seg_decode.v, line:8:1, endln:40:10 + \_module_inst: work@oh_7seg_decode (work@oh_7seg_decode), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_7seg_decode.v, line:8:1, endln:40:10 |vpiName:a |vpiDirection:2 |vpiLowConn: @@ -1945,7 +1945,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (b), line:12:13, endln:12:14 |vpiParent: - \_module: work@oh_7seg_decode (work@oh_7seg_decode), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_7seg_decode.v, line:8:1, endln:40:10 + \_module_inst: work@oh_7seg_decode (work@oh_7seg_decode), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_7seg_decode.v, line:8:1, endln:40:10 |vpiName:b |vpiDirection:2 |vpiLowConn: @@ -1957,7 +1957,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (c), line:13:13, endln:13:14 |vpiParent: - \_module: work@oh_7seg_decode (work@oh_7seg_decode), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_7seg_decode.v, line:8:1, endln:40:10 + \_module_inst: work@oh_7seg_decode (work@oh_7seg_decode), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_7seg_decode.v, line:8:1, endln:40:10 |vpiName:c |vpiDirection:2 |vpiLowConn: @@ -1969,7 +1969,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (d), line:14:13, endln:14:14 |vpiParent: - \_module: work@oh_7seg_decode (work@oh_7seg_decode), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_7seg_decode.v, line:8:1, endln:40:10 + \_module_inst: work@oh_7seg_decode (work@oh_7seg_decode), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_7seg_decode.v, line:8:1, endln:40:10 |vpiName:d |vpiDirection:2 |vpiLowConn: @@ -1981,7 +1981,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (e), line:15:13, endln:15:14 |vpiParent: - \_module: work@oh_7seg_decode (work@oh_7seg_decode), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_7seg_decode.v, line:8:1, endln:40:10 + \_module_inst: work@oh_7seg_decode (work@oh_7seg_decode), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_7seg_decode.v, line:8:1, endln:40:10 |vpiName:e |vpiDirection:2 |vpiLowConn: @@ -1993,7 +1993,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (f), line:16:13, endln:16:14 |vpiParent: - \_module: work@oh_7seg_decode (work@oh_7seg_decode), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_7seg_decode.v, line:8:1, endln:40:10 + \_module_inst: work@oh_7seg_decode (work@oh_7seg_decode), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_7seg_decode.v, line:8:1, endln:40:10 |vpiName:f |vpiDirection:2 |vpiLowConn: @@ -2005,7 +2005,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (g), line:17:13, endln:17:14 |vpiParent: - \_module: work@oh_7seg_decode (work@oh_7seg_decode), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_7seg_decode.v, line:8:1, endln:40:10 + \_module_inst: work@oh_7seg_decode (work@oh_7seg_decode), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_7seg_decode.v, line:8:1, endln:40:10 |vpiName:g |vpiDirection:2 |vpiLowConn: @@ -2017,7 +2017,7 @@ design: (work@oh_fifo_async) |vpiContAssign: \_cont_assign: , line:20:11, endln:20:54 |vpiParent: - \_module: work@oh_7seg_decode (work@oh_7seg_decode), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_7seg_decode.v, line:8:1, endln:40:10 + \_module_inst: work@oh_7seg_decode (work@oh_7seg_decode), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_7seg_decode.v, line:8:1, endln:40:10 |vpiRhs: \_operation: , line:20:15, endln:20:54 |vpiParent: @@ -2102,7 +2102,7 @@ design: (work@oh_fifo_async) |vpiContAssign: \_cont_assign: , line:22:11, endln:22:54 |vpiParent: - \_module: work@oh_7seg_decode (work@oh_7seg_decode), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_7seg_decode.v, line:8:1, endln:40:10 + \_module_inst: work@oh_7seg_decode (work@oh_7seg_decode), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_7seg_decode.v, line:8:1, endln:40:10 |vpiRhs: \_operation: , line:22:15, endln:22:54 |vpiParent: @@ -2187,7 +2187,7 @@ design: (work@oh_fifo_async) |vpiContAssign: \_cont_assign: , line:24:11, endln:24:33 |vpiParent: - \_module: work@oh_7seg_decode (work@oh_7seg_decode), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_7seg_decode.v, line:8:1, endln:40:10 + \_module_inst: work@oh_7seg_decode (work@oh_7seg_decode), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_7seg_decode.v, line:8:1, endln:40:10 |vpiRhs: \_operation: , line:24:16, endln:24:32 |vpiParent: @@ -2232,7 +2232,7 @@ design: (work@oh_fifo_async) |vpiContAssign: \_cont_assign: , line:26:11, endln:27:54 |vpiParent: - \_module: work@oh_7seg_decode (work@oh_7seg_decode), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_7seg_decode.v, line:8:1, endln:40:10 + \_module_inst: work@oh_7seg_decode (work@oh_7seg_decode), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_7seg_decode.v, line:8:1, endln:40:10 |vpiRhs: \_operation: , line:26:15, endln:27:54 |vpiParent: @@ -2397,7 +2397,7 @@ design: (work@oh_fifo_async) |vpiContAssign: \_cont_assign: , line:29:11, endln:31:47 |vpiParent: - \_module: work@oh_7seg_decode (work@oh_7seg_decode), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_7seg_decode.v, line:8:1, endln:40:10 + \_module_inst: work@oh_7seg_decode (work@oh_7seg_decode), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_7seg_decode.v, line:8:1, endln:40:10 |vpiRhs: \_operation: , line:29:15, endln:31:47 |vpiParent: @@ -2642,7 +2642,7 @@ design: (work@oh_fifo_async) |vpiContAssign: \_cont_assign: , line:33:11, endln:34:47 |vpiParent: - \_module: work@oh_7seg_decode (work@oh_7seg_decode), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_7seg_decode.v, line:8:1, endln:40:10 + \_module_inst: work@oh_7seg_decode (work@oh_7seg_decode), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_7seg_decode.v, line:8:1, endln:40:10 |vpiRhs: \_operation: , line:33:15, endln:34:47 |vpiParent: @@ -2807,7 +2807,7 @@ design: (work@oh_fifo_async) |vpiContAssign: \_cont_assign: , line:37:11, endln:38:26 |vpiParent: - \_module: work@oh_7seg_decode (work@oh_7seg_decode), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_7seg_decode.v, line:8:1, endln:40:10 + \_module_inst: work@oh_7seg_decode (work@oh_7seg_decode), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_7seg_decode.v, line:8:1, endln:40:10 |vpiRhs: \_operation: , line:37:15, endln:38:26 |vpiParent: @@ -2930,14 +2930,14 @@ design: (work@oh_fifo_async) |vpiName:g |vpiFullName:work@oh_7seg_decode.g |uhdmallModules: -\_module: work@oh_abs (work@oh_abs), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_abs.v, line:8:1, endln:35:10 +\_module_inst: work@oh_abs (work@oh_abs), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_abs.v, line:8:1, endln:35:10 |vpiParent: \_design: (work@oh_fifo_async) |vpiFullName:work@oh_abs |vpiParameter: \_parameter: (work@oh_abs.N), line:9:15, endln:9:16 |vpiParent: - \_module: work@oh_abs (work@oh_abs), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_abs.v, line:8:1, endln:35:10 + \_module_inst: work@oh_abs (work@oh_abs), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_abs.v, line:8:1, endln:35:10 |UINT:32 |vpiTypespec: \_int_typespec: @@ -2946,7 +2946,7 @@ design: (work@oh_fifo_async) |vpiParameter: \_parameter: (work@oh_abs.SYN), line:10:15, endln:10:18 |vpiParent: - \_module: work@oh_abs (work@oh_abs), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_abs.v, line:8:1, endln:35:10 + \_module_inst: work@oh_abs (work@oh_abs), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_abs.v, line:8:1, endln:35:10 |STRING:TRUE |vpiTypespec: \_string_typespec: @@ -2955,7 +2955,7 @@ design: (work@oh_fifo_async) |vpiParameter: \_parameter: (work@oh_abs.TYPE), line:11:15, endln:11:19 |vpiParent: - \_module: work@oh_abs (work@oh_abs), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_abs.v, line:8:1, endln:35:10 + \_module_inst: work@oh_abs (work@oh_abs), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_abs.v, line:8:1, endln:35:10 |STRING:DEFAULT |vpiTypespec: \_string_typespec: @@ -2964,7 +2964,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:9:15, endln:9:24 |vpiParent: - \_module: work@oh_abs (work@oh_abs), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_abs.v, line:8:1, endln:35:10 + \_module_inst: work@oh_abs (work@oh_abs), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_abs.v, line:8:1, endln:35:10 |vpiRhs: \_constant: , line:9:22, endln:9:24 |vpiDecompile:32 @@ -2978,7 +2978,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:10:15, endln:10:28 |vpiParent: - \_module: work@oh_abs (work@oh_abs), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_abs.v, line:8:1, endln:35:10 + \_module_inst: work@oh_abs (work@oh_abs), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_abs.v, line:8:1, endln:35:10 |vpiRhs: \_constant: , line:10:22, endln:10:28 |vpiDecompile:TRUE @@ -2992,7 +2992,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:11:15, endln:11:31 |vpiParent: - \_module: work@oh_abs (work@oh_abs), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_abs.v, line:8:1, endln:35:10 + \_module_inst: work@oh_abs (work@oh_abs), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_abs.v, line:8:1, endln:35:10 |vpiRhs: \_constant: , line:11:22, endln:11:31 |vpiDecompile:DEFAULT @@ -3008,25 +3008,25 @@ design: (work@oh_fifo_async) |vpiNet: \_logic_net: (work@oh_abs.in), line:14:20, endln:14:22 |vpiParent: - \_module: work@oh_abs (work@oh_abs), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_abs.v, line:8:1, endln:35:10 + \_module_inst: work@oh_abs (work@oh_abs), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_abs.v, line:8:1, endln:35:10 |vpiName:in |vpiFullName:work@oh_abs.in |vpiNet: \_logic_net: (work@oh_abs.out), line:15:20, endln:15:23 |vpiParent: - \_module: work@oh_abs (work@oh_abs), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_abs.v, line:8:1, endln:35:10 + \_module_inst: work@oh_abs (work@oh_abs), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_abs.v, line:8:1, endln:35:10 |vpiName:out |vpiFullName:work@oh_abs.out |vpiNet: \_logic_net: (work@oh_abs.overflow), line:16:16, endln:16:24 |vpiParent: - \_module: work@oh_abs (work@oh_abs), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_abs.v, line:8:1, endln:35:10 + \_module_inst: work@oh_abs (work@oh_abs), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_abs.v, line:8:1, endln:35:10 |vpiName:overflow |vpiFullName:work@oh_abs.overflow |vpiPort: \_port: (in), line:14:20, endln:14:22 |vpiParent: - \_module: work@oh_abs (work@oh_abs), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_abs.v, line:8:1, endln:35:10 + \_module_inst: work@oh_abs (work@oh_abs), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_abs.v, line:8:1, endln:35:10 |vpiName:in |vpiDirection:1 |vpiLowConn: @@ -3066,7 +3066,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (out), line:15:20, endln:15:23 |vpiParent: - \_module: work@oh_abs (work@oh_abs), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_abs.v, line:8:1, endln:35:10 + \_module_inst: work@oh_abs (work@oh_abs), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_abs.v, line:8:1, endln:35:10 |vpiName:out |vpiDirection:2 |vpiLowConn: @@ -3106,7 +3106,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (overflow), line:16:16, endln:16:24 |vpiParent: - \_module: work@oh_abs (work@oh_abs), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_abs.v, line:8:1, endln:35:10 + \_module_inst: work@oh_abs (work@oh_abs), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_abs.v, line:8:1, endln:35:10 |vpiName:overflow |vpiDirection:2 |vpiLowConn: @@ -3116,14 +3116,14 @@ design: (work@oh_fifo_async) |vpiTypedef: \_logic_typespec: , line:16:16, endln:16:16 |uhdmallModules: -\_module: work@oh_add (work@oh_add), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_add.v, line:8:1, endln:45:10 +\_module_inst: work@oh_add (work@oh_add), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_add.v, line:8:1, endln:45:10 |vpiParent: \_design: (work@oh_fifo_async) |vpiFullName:work@oh_add |vpiParameter: \_parameter: (work@oh_add.N), line:9:15, endln:9:16 |vpiParent: - \_module: work@oh_add (work@oh_add), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_add.v, line:8:1, endln:45:10 + \_module_inst: work@oh_add (work@oh_add), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_add.v, line:8:1, endln:45:10 |UINT:32 |vpiTypespec: \_int_typespec: @@ -3132,7 +3132,7 @@ design: (work@oh_fifo_async) |vpiParameter: \_parameter: (work@oh_add.SYN), line:10:15, endln:10:18 |vpiParent: - \_module: work@oh_add (work@oh_add), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_add.v, line:8:1, endln:45:10 + \_module_inst: work@oh_add (work@oh_add), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_add.v, line:8:1, endln:45:10 |STRING:TRUE |vpiTypespec: \_string_typespec: @@ -3141,7 +3141,7 @@ design: (work@oh_fifo_async) |vpiParameter: \_parameter: (work@oh_add.TYPE), line:11:15, endln:11:19 |vpiParent: - \_module: work@oh_add (work@oh_add), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_add.v, line:8:1, endln:45:10 + \_module_inst: work@oh_add (work@oh_add), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_add.v, line:8:1, endln:45:10 |STRING:DEFAULT |vpiTypespec: \_string_typespec: @@ -3150,7 +3150,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:9:15, endln:9:24 |vpiParent: - \_module: work@oh_add (work@oh_add), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_add.v, line:8:1, endln:45:10 + \_module_inst: work@oh_add (work@oh_add), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_add.v, line:8:1, endln:45:10 |vpiRhs: \_constant: , line:9:22, endln:9:24 |vpiDecompile:32 @@ -3164,7 +3164,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:10:15, endln:10:28 |vpiParent: - \_module: work@oh_add (work@oh_add), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_add.v, line:8:1, endln:45:10 + \_module_inst: work@oh_add (work@oh_add), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_add.v, line:8:1, endln:45:10 |vpiRhs: \_constant: , line:10:22, endln:10:28 |vpiDecompile:TRUE @@ -3178,7 +3178,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:11:15, endln:11:31 |vpiParent: - \_module: work@oh_add (work@oh_add), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_add.v, line:8:1, endln:45:10 + \_module_inst: work@oh_add (work@oh_add), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_add.v, line:8:1, endln:45:10 |vpiRhs: \_constant: , line:11:22, endln:11:31 |vpiDecompile:DEFAULT @@ -3194,49 +3194,49 @@ design: (work@oh_fifo_async) |vpiNet: \_logic_net: (work@oh_add.a), line:14:20, endln:14:21 |vpiParent: - \_module: work@oh_add (work@oh_add), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_add.v, line:8:1, endln:45:10 + \_module_inst: work@oh_add (work@oh_add), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_add.v, line:8:1, endln:45:10 |vpiName:a |vpiFullName:work@oh_add.a |vpiNet: \_logic_net: (work@oh_add.b), line:15:20, endln:15:21 |vpiParent: - \_module: work@oh_add (work@oh_add), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_add.v, line:8:1, endln:45:10 + \_module_inst: work@oh_add (work@oh_add), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_add.v, line:8:1, endln:45:10 |vpiName:b |vpiFullName:work@oh_add.b |vpiNet: \_logic_net: (work@oh_add.k), line:16:20, endln:16:21 |vpiParent: - \_module: work@oh_add (work@oh_add), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_add.v, line:8:1, endln:45:10 + \_module_inst: work@oh_add (work@oh_add), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_add.v, line:8:1, endln:45:10 |vpiName:k |vpiFullName:work@oh_add.k |vpiNet: \_logic_net: (work@oh_add.cin), line:17:15, endln:17:18 |vpiParent: - \_module: work@oh_add (work@oh_add), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_add.v, line:8:1, endln:45:10 + \_module_inst: work@oh_add (work@oh_add), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_add.v, line:8:1, endln:45:10 |vpiName:cin |vpiFullName:work@oh_add.cin |vpiNet: \_logic_net: (work@oh_add.sum), line:19:20, endln:19:23 |vpiParent: - \_module: work@oh_add (work@oh_add), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_add.v, line:8:1, endln:45:10 + \_module_inst: work@oh_add (work@oh_add), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_add.v, line:8:1, endln:45:10 |vpiName:sum |vpiFullName:work@oh_add.sum |vpiNet: \_logic_net: (work@oh_add.carry), line:20:20, endln:20:25 |vpiParent: - \_module: work@oh_add (work@oh_add), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_add.v, line:8:1, endln:45:10 + \_module_inst: work@oh_add (work@oh_add), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_add.v, line:8:1, endln:45:10 |vpiName:carry |vpiFullName:work@oh_add.carry |vpiNet: \_logic_net: (work@oh_add.cout), line:21:16, endln:21:20 |vpiParent: - \_module: work@oh_add (work@oh_add), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_add.v, line:8:1, endln:45:10 + \_module_inst: work@oh_add (work@oh_add), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_add.v, line:8:1, endln:45:10 |vpiName:cout |vpiFullName:work@oh_add.cout |vpiPort: \_port: (a), line:14:20, endln:14:21 |vpiParent: - \_module: work@oh_add (work@oh_add), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_add.v, line:8:1, endln:45:10 + \_module_inst: work@oh_add (work@oh_add), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_add.v, line:8:1, endln:45:10 |vpiName:a |vpiDirection:1 |vpiLowConn: @@ -3276,7 +3276,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (b), line:15:20, endln:15:21 |vpiParent: - \_module: work@oh_add (work@oh_add), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_add.v, line:8:1, endln:45:10 + \_module_inst: work@oh_add (work@oh_add), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_add.v, line:8:1, endln:45:10 |vpiName:b |vpiDirection:1 |vpiLowConn: @@ -3316,7 +3316,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (k), line:16:20, endln:16:21 |vpiParent: - \_module: work@oh_add (work@oh_add), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_add.v, line:8:1, endln:45:10 + \_module_inst: work@oh_add (work@oh_add), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_add.v, line:8:1, endln:45:10 |vpiName:k |vpiDirection:1 |vpiLowConn: @@ -3356,7 +3356,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (cin), line:17:15, endln:17:18 |vpiParent: - \_module: work@oh_add (work@oh_add), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_add.v, line:8:1, endln:45:10 + \_module_inst: work@oh_add (work@oh_add), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_add.v, line:8:1, endln:45:10 |vpiName:cin |vpiDirection:1 |vpiLowConn: @@ -3368,7 +3368,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (sum), line:19:20, endln:19:23 |vpiParent: - \_module: work@oh_add (work@oh_add), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_add.v, line:8:1, endln:45:10 + \_module_inst: work@oh_add (work@oh_add), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_add.v, line:8:1, endln:45:10 |vpiName:sum |vpiDirection:2 |vpiLowConn: @@ -3408,7 +3408,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (carry), line:20:20, endln:20:25 |vpiParent: - \_module: work@oh_add (work@oh_add), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_add.v, line:8:1, endln:45:10 + \_module_inst: work@oh_add (work@oh_add), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_add.v, line:8:1, endln:45:10 |vpiName:carry |vpiDirection:2 |vpiLowConn: @@ -3448,7 +3448,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (cout), line:21:16, endln:21:20 |vpiParent: - \_module: work@oh_add (work@oh_add), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_add.v, line:8:1, endln:45:10 + \_module_inst: work@oh_add (work@oh_add), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_add.v, line:8:1, endln:45:10 |vpiName:cout |vpiDirection:2 |vpiLowConn: @@ -3458,14 +3458,14 @@ design: (work@oh_fifo_async) |vpiTypedef: \_logic_typespec: , line:21:16, endln:21:16 |uhdmallModules: -\_module: work@oh_and2 (work@oh_and2), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_and2.v, line:8:1, endln:33:10 +\_module_inst: work@oh_and2 (work@oh_and2), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_and2.v, line:8:1, endln:33:10 |vpiParent: \_design: (work@oh_fifo_async) |vpiFullName:work@oh_and2 |vpiParameter: \_parameter: (work@oh_and2.N), line:8:29, endln:8:30 |vpiParent: - \_module: work@oh_and2 (work@oh_and2), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_and2.v, line:8:1, endln:33:10 + \_module_inst: work@oh_and2 (work@oh_and2), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_and2.v, line:8:1, endln:33:10 |UINT:1 |vpiTypespec: \_int_typespec: @@ -3474,7 +3474,7 @@ design: (work@oh_fifo_async) |vpiParameter: \_parameter: (work@oh_and2.SYN), line:9:15, endln:9:18 |vpiParent: - \_module: work@oh_and2 (work@oh_and2), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_and2.v, line:8:1, endln:33:10 + \_module_inst: work@oh_and2 (work@oh_and2), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_and2.v, line:8:1, endln:33:10 |STRING:TRUE |vpiTypespec: \_string_typespec: @@ -3483,7 +3483,7 @@ design: (work@oh_fifo_async) |vpiParameter: \_parameter: (work@oh_and2.TYPE), line:10:15, endln:10:19 |vpiParent: - \_module: work@oh_and2 (work@oh_and2), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_and2.v, line:8:1, endln:33:10 + \_module_inst: work@oh_and2 (work@oh_and2), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_and2.v, line:8:1, endln:33:10 |STRING:DEFAULT |vpiTypespec: \_string_typespec: @@ -3492,7 +3492,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:8:29, endln:8:35 |vpiParent: - \_module: work@oh_and2 (work@oh_and2), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_and2.v, line:8:1, endln:33:10 + \_module_inst: work@oh_and2 (work@oh_and2), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_and2.v, line:8:1, endln:33:10 |vpiRhs: \_constant: , line:8:34, endln:8:35 |vpiDecompile:1 @@ -3506,7 +3506,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:9:15, endln:9:28 |vpiParent: - \_module: work@oh_and2 (work@oh_and2), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_and2.v, line:8:1, endln:33:10 + \_module_inst: work@oh_and2 (work@oh_and2), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_and2.v, line:8:1, endln:33:10 |vpiRhs: \_constant: , line:9:22, endln:9:28 |vpiDecompile:TRUE @@ -3520,7 +3520,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:10:15, endln:10:31 |vpiParent: - \_module: work@oh_and2 (work@oh_and2), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_and2.v, line:8:1, endln:33:10 + \_module_inst: work@oh_and2 (work@oh_and2), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_and2.v, line:8:1, endln:33:10 |vpiRhs: \_constant: , line:10:22, endln:10:31 |vpiDecompile:DEFAULT @@ -3536,25 +3536,25 @@ design: (work@oh_fifo_async) |vpiNet: \_logic_net: (work@oh_and2.a), line:14:20, endln:14:21 |vpiParent: - \_module: work@oh_and2 (work@oh_and2), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_and2.v, line:8:1, endln:33:10 + \_module_inst: work@oh_and2 (work@oh_and2), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_and2.v, line:8:1, endln:33:10 |vpiName:a |vpiFullName:work@oh_and2.a |vpiNet: \_logic_net: (work@oh_and2.b), line:15:20, endln:15:21 |vpiParent: - \_module: work@oh_and2 (work@oh_and2), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_and2.v, line:8:1, endln:33:10 + \_module_inst: work@oh_and2 (work@oh_and2), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_and2.v, line:8:1, endln:33:10 |vpiName:b |vpiFullName:work@oh_and2.b |vpiNet: \_logic_net: (work@oh_and2.z), line:16:20, endln:16:21 |vpiParent: - \_module: work@oh_and2 (work@oh_and2), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_and2.v, line:8:1, endln:33:10 + \_module_inst: work@oh_and2 (work@oh_and2), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_and2.v, line:8:1, endln:33:10 |vpiName:z |vpiFullName:work@oh_and2.z |vpiPort: \_port: (a), line:14:20, endln:14:21 |vpiParent: - \_module: work@oh_and2 (work@oh_and2), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_and2.v, line:8:1, endln:33:10 + \_module_inst: work@oh_and2 (work@oh_and2), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_and2.v, line:8:1, endln:33:10 |vpiName:a |vpiDirection:1 |vpiLowConn: @@ -3594,7 +3594,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (b), line:15:20, endln:15:21 |vpiParent: - \_module: work@oh_and2 (work@oh_and2), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_and2.v, line:8:1, endln:33:10 + \_module_inst: work@oh_and2 (work@oh_and2), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_and2.v, line:8:1, endln:33:10 |vpiName:b |vpiDirection:1 |vpiLowConn: @@ -3634,7 +3634,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (z), line:16:20, endln:16:21 |vpiParent: - \_module: work@oh_and2 (work@oh_and2), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_and2.v, line:8:1, endln:33:10 + \_module_inst: work@oh_and2 (work@oh_and2), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_and2.v, line:8:1, endln:33:10 |vpiName:z |vpiDirection:2 |vpiLowConn: @@ -3672,14 +3672,14 @@ design: (work@oh_fifo_async) |UINT:0 |vpiConstType:9 |uhdmallModules: -\_module: work@oh_and3 (work@oh_and3), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_and3.v, line:8:1, endln:18:10 +\_module_inst: work@oh_and3 (work@oh_and3), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_and3.v, line:8:1, endln:18:10 |vpiParent: \_design: (work@oh_fifo_async) |vpiFullName:work@oh_and3 |vpiParameter: \_parameter: (work@oh_and3.DW), line:8:28, endln:8:30 |vpiParent: - \_module: work@oh_and3 (work@oh_and3), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_and3.v, line:8:1, endln:18:10 + \_module_inst: work@oh_and3 (work@oh_and3), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_and3.v, line:8:1, endln:18:10 |UINT:1 |vpiTypespec: \_int_typespec: @@ -3688,7 +3688,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:8:28, endln:8:34 |vpiParent: - \_module: work@oh_and3 (work@oh_and3), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_and3.v, line:8:1, endln:18:10 + \_module_inst: work@oh_and3 (work@oh_and3), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_and3.v, line:8:1, endln:18:10 |vpiRhs: \_constant: , line:8:33, endln:8:34 |vpiDecompile:1 @@ -3704,31 +3704,31 @@ design: (work@oh_fifo_async) |vpiNet: \_logic_net: (work@oh_and3.a), line:10:21, endln:10:22 |vpiParent: - \_module: work@oh_and3 (work@oh_and3), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_and3.v, line:8:1, endln:18:10 + \_module_inst: work@oh_and3 (work@oh_and3), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_and3.v, line:8:1, endln:18:10 |vpiName:a |vpiFullName:work@oh_and3.a |vpiNet: \_logic_net: (work@oh_and3.b), line:11:21, endln:11:22 |vpiParent: - \_module: work@oh_and3 (work@oh_and3), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_and3.v, line:8:1, endln:18:10 + \_module_inst: work@oh_and3 (work@oh_and3), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_and3.v, line:8:1, endln:18:10 |vpiName:b |vpiFullName:work@oh_and3.b |vpiNet: \_logic_net: (work@oh_and3.c), line:12:21, endln:12:22 |vpiParent: - \_module: work@oh_and3 (work@oh_and3), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_and3.v, line:8:1, endln:18:10 + \_module_inst: work@oh_and3 (work@oh_and3), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_and3.v, line:8:1, endln:18:10 |vpiName:c |vpiFullName:work@oh_and3.c |vpiNet: \_logic_net: (work@oh_and3.z), line:13:21, endln:13:22 |vpiParent: - \_module: work@oh_and3 (work@oh_and3), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_and3.v, line:8:1, endln:18:10 + \_module_inst: work@oh_and3 (work@oh_and3), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_and3.v, line:8:1, endln:18:10 |vpiName:z |vpiFullName:work@oh_and3.z |vpiPort: \_port: (a), line:10:21, endln:10:22 |vpiParent: - \_module: work@oh_and3 (work@oh_and3), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_and3.v, line:8:1, endln:18:10 + \_module_inst: work@oh_and3 (work@oh_and3), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_and3.v, line:8:1, endln:18:10 |vpiName:a |vpiDirection:1 |vpiLowConn: @@ -3768,7 +3768,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (b), line:11:21, endln:11:22 |vpiParent: - \_module: work@oh_and3 (work@oh_and3), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_and3.v, line:8:1, endln:18:10 + \_module_inst: work@oh_and3 (work@oh_and3), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_and3.v, line:8:1, endln:18:10 |vpiName:b |vpiDirection:1 |vpiLowConn: @@ -3808,7 +3808,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (c), line:12:21, endln:12:22 |vpiParent: - \_module: work@oh_and3 (work@oh_and3), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_and3.v, line:8:1, endln:18:10 + \_module_inst: work@oh_and3 (work@oh_and3), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_and3.v, line:8:1, endln:18:10 |vpiName:c |vpiDirection:1 |vpiLowConn: @@ -3848,7 +3848,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (z), line:13:21, endln:13:22 |vpiParent: - \_module: work@oh_and3 (work@oh_and3), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_and3.v, line:8:1, endln:18:10 + \_module_inst: work@oh_and3 (work@oh_and3), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_and3.v, line:8:1, endln:18:10 |vpiName:z |vpiDirection:2 |vpiLowConn: @@ -3888,7 +3888,7 @@ design: (work@oh_fifo_async) |vpiContAssign: \_cont_assign: , line:16:11, endln:16:24 |vpiParent: - \_module: work@oh_and3 (work@oh_and3), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_and3.v, line:8:1, endln:18:10 + \_module_inst: work@oh_and3 (work@oh_and3), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_and3.v, line:8:1, endln:18:10 |vpiRhs: \_operation: , line:16:15, endln:16:24 |vpiParent: @@ -3924,14 +3924,14 @@ design: (work@oh_fifo_async) |vpiName:z |vpiFullName:work@oh_and3.z |uhdmallModules: -\_module: work@oh_and4 (work@oh_and4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_and4.v, line:8:1, endln:19:10 +\_module_inst: work@oh_and4 (work@oh_and4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_and4.v, line:8:1, endln:19:10 |vpiParent: \_design: (work@oh_fifo_async) |vpiFullName:work@oh_and4 |vpiParameter: \_parameter: (work@oh_and4.DW), line:8:28, endln:8:30 |vpiParent: - \_module: work@oh_and4 (work@oh_and4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_and4.v, line:8:1, endln:19:10 + \_module_inst: work@oh_and4 (work@oh_and4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_and4.v, line:8:1, endln:19:10 |UINT:1 |vpiTypespec: \_int_typespec: @@ -3940,7 +3940,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:8:28, endln:8:34 |vpiParent: - \_module: work@oh_and4 (work@oh_and4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_and4.v, line:8:1, endln:19:10 + \_module_inst: work@oh_and4 (work@oh_and4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_and4.v, line:8:1, endln:19:10 |vpiRhs: \_constant: , line:8:33, endln:8:34 |vpiDecompile:1 @@ -3956,37 +3956,37 @@ design: (work@oh_fifo_async) |vpiNet: \_logic_net: (work@oh_and4.a), line:10:21, endln:10:22 |vpiParent: - \_module: work@oh_and4 (work@oh_and4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_and4.v, line:8:1, endln:19:10 + \_module_inst: work@oh_and4 (work@oh_and4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_and4.v, line:8:1, endln:19:10 |vpiName:a |vpiFullName:work@oh_and4.a |vpiNet: \_logic_net: (work@oh_and4.b), line:11:21, endln:11:22 |vpiParent: - \_module: work@oh_and4 (work@oh_and4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_and4.v, line:8:1, endln:19:10 + \_module_inst: work@oh_and4 (work@oh_and4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_and4.v, line:8:1, endln:19:10 |vpiName:b |vpiFullName:work@oh_and4.b |vpiNet: \_logic_net: (work@oh_and4.c), line:12:21, endln:12:22 |vpiParent: - \_module: work@oh_and4 (work@oh_and4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_and4.v, line:8:1, endln:19:10 + \_module_inst: work@oh_and4 (work@oh_and4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_and4.v, line:8:1, endln:19:10 |vpiName:c |vpiFullName:work@oh_and4.c |vpiNet: \_logic_net: (work@oh_and4.d), line:13:21, endln:13:22 |vpiParent: - \_module: work@oh_and4 (work@oh_and4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_and4.v, line:8:1, endln:19:10 + \_module_inst: work@oh_and4 (work@oh_and4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_and4.v, line:8:1, endln:19:10 |vpiName:d |vpiFullName:work@oh_and4.d |vpiNet: \_logic_net: (work@oh_and4.z), line:14:21, endln:14:22 |vpiParent: - \_module: work@oh_and4 (work@oh_and4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_and4.v, line:8:1, endln:19:10 + \_module_inst: work@oh_and4 (work@oh_and4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_and4.v, line:8:1, endln:19:10 |vpiName:z |vpiFullName:work@oh_and4.z |vpiPort: \_port: (a), line:10:21, endln:10:22 |vpiParent: - \_module: work@oh_and4 (work@oh_and4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_and4.v, line:8:1, endln:19:10 + \_module_inst: work@oh_and4 (work@oh_and4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_and4.v, line:8:1, endln:19:10 |vpiName:a |vpiDirection:1 |vpiLowConn: @@ -4026,7 +4026,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (b), line:11:21, endln:11:22 |vpiParent: - \_module: work@oh_and4 (work@oh_and4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_and4.v, line:8:1, endln:19:10 + \_module_inst: work@oh_and4 (work@oh_and4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_and4.v, line:8:1, endln:19:10 |vpiName:b |vpiDirection:1 |vpiLowConn: @@ -4066,7 +4066,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (c), line:12:21, endln:12:22 |vpiParent: - \_module: work@oh_and4 (work@oh_and4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_and4.v, line:8:1, endln:19:10 + \_module_inst: work@oh_and4 (work@oh_and4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_and4.v, line:8:1, endln:19:10 |vpiName:c |vpiDirection:1 |vpiLowConn: @@ -4106,7 +4106,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (d), line:13:21, endln:13:22 |vpiParent: - \_module: work@oh_and4 (work@oh_and4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_and4.v, line:8:1, endln:19:10 + \_module_inst: work@oh_and4 (work@oh_and4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_and4.v, line:8:1, endln:19:10 |vpiName:d |vpiDirection:1 |vpiLowConn: @@ -4146,7 +4146,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (z), line:14:21, endln:14:22 |vpiParent: - \_module: work@oh_and4 (work@oh_and4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_and4.v, line:8:1, endln:19:10 + \_module_inst: work@oh_and4 (work@oh_and4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_and4.v, line:8:1, endln:19:10 |vpiName:z |vpiDirection:2 |vpiLowConn: @@ -4186,7 +4186,7 @@ design: (work@oh_fifo_async) |vpiContAssign: \_cont_assign: , line:17:11, endln:17:24 |vpiParent: - \_module: work@oh_and4 (work@oh_and4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_and4.v, line:8:1, endln:19:10 + \_module_inst: work@oh_and4 (work@oh_and4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_and4.v, line:8:1, endln:19:10 |vpiRhs: \_operation: , line:17:16, endln:17:23 |vpiParent: @@ -4233,14 +4233,14 @@ design: (work@oh_fifo_async) |vpiName:z |vpiFullName:work@oh_and4.z |uhdmallModules: -\_module: work@oh_ao21 (work@oh_ao21), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao21.v, line:8:1, endln:18:10 +\_module_inst: work@oh_ao21 (work@oh_ao21), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao21.v, line:8:1, endln:18:10 |vpiParent: \_design: (work@oh_fifo_async) |vpiFullName:work@oh_ao21 |vpiParameter: \_parameter: (work@oh_ao21.DW), line:8:28, endln:8:30 |vpiParent: - \_module: work@oh_ao21 (work@oh_ao21), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao21.v, line:8:1, endln:18:10 + \_module_inst: work@oh_ao21 (work@oh_ao21), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao21.v, line:8:1, endln:18:10 |UINT:1 |vpiTypespec: \_int_typespec: @@ -4249,7 +4249,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:8:28, endln:8:34 |vpiParent: - \_module: work@oh_ao21 (work@oh_ao21), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao21.v, line:8:1, endln:18:10 + \_module_inst: work@oh_ao21 (work@oh_ao21), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao21.v, line:8:1, endln:18:10 |vpiRhs: \_constant: , line:8:33, endln:8:34 |vpiDecompile:1 @@ -4265,31 +4265,31 @@ design: (work@oh_fifo_async) |vpiNet: \_logic_net: (work@oh_ao21.a0), line:10:21, endln:10:23 |vpiParent: - \_module: work@oh_ao21 (work@oh_ao21), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao21.v, line:8:1, endln:18:10 + \_module_inst: work@oh_ao21 (work@oh_ao21), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao21.v, line:8:1, endln:18:10 |vpiName:a0 |vpiFullName:work@oh_ao21.a0 |vpiNet: \_logic_net: (work@oh_ao21.a1), line:11:21, endln:11:23 |vpiParent: - \_module: work@oh_ao21 (work@oh_ao21), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao21.v, line:8:1, endln:18:10 + \_module_inst: work@oh_ao21 (work@oh_ao21), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao21.v, line:8:1, endln:18:10 |vpiName:a1 |vpiFullName:work@oh_ao21.a1 |vpiNet: \_logic_net: (work@oh_ao21.b0), line:12:21, endln:12:23 |vpiParent: - \_module: work@oh_ao21 (work@oh_ao21), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao21.v, line:8:1, endln:18:10 + \_module_inst: work@oh_ao21 (work@oh_ao21), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao21.v, line:8:1, endln:18:10 |vpiName:b0 |vpiFullName:work@oh_ao21.b0 |vpiNet: \_logic_net: (work@oh_ao21.z), line:13:21, endln:13:22 |vpiParent: - \_module: work@oh_ao21 (work@oh_ao21), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao21.v, line:8:1, endln:18:10 + \_module_inst: work@oh_ao21 (work@oh_ao21), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao21.v, line:8:1, endln:18:10 |vpiName:z |vpiFullName:work@oh_ao21.z |vpiPort: \_port: (a0), line:10:21, endln:10:23 |vpiParent: - \_module: work@oh_ao21 (work@oh_ao21), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao21.v, line:8:1, endln:18:10 + \_module_inst: work@oh_ao21 (work@oh_ao21), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao21.v, line:8:1, endln:18:10 |vpiName:a0 |vpiDirection:1 |vpiLowConn: @@ -4329,7 +4329,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (a1), line:11:21, endln:11:23 |vpiParent: - \_module: work@oh_ao21 (work@oh_ao21), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao21.v, line:8:1, endln:18:10 + \_module_inst: work@oh_ao21 (work@oh_ao21), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao21.v, line:8:1, endln:18:10 |vpiName:a1 |vpiDirection:1 |vpiLowConn: @@ -4369,7 +4369,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (b0), line:12:21, endln:12:23 |vpiParent: - \_module: work@oh_ao21 (work@oh_ao21), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao21.v, line:8:1, endln:18:10 + \_module_inst: work@oh_ao21 (work@oh_ao21), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao21.v, line:8:1, endln:18:10 |vpiName:b0 |vpiDirection:1 |vpiLowConn: @@ -4409,7 +4409,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (z), line:13:21, endln:13:22 |vpiParent: - \_module: work@oh_ao21 (work@oh_ao21), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao21.v, line:8:1, endln:18:10 + \_module_inst: work@oh_ao21 (work@oh_ao21), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao21.v, line:8:1, endln:18:10 |vpiName:z |vpiDirection:2 |vpiLowConn: @@ -4449,7 +4449,7 @@ design: (work@oh_fifo_async) |vpiContAssign: \_cont_assign: , line:16:11, endln:16:29 |vpiParent: - \_module: work@oh_ao21 (work@oh_ao21), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao21.v, line:8:1, endln:18:10 + \_module_inst: work@oh_ao21 (work@oh_ao21), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao21.v, line:8:1, endln:18:10 |vpiRhs: \_operation: , line:16:15, endln:16:29 |vpiParent: @@ -4485,14 +4485,14 @@ design: (work@oh_fifo_async) |vpiName:z |vpiFullName:work@oh_ao21.z |uhdmallModules: -\_module: work@oh_ao211 (work@oh_ao211), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao211.v, line:8:1, endln:19:10 +\_module_inst: work@oh_ao211 (work@oh_ao211), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao211.v, line:8:1, endln:19:10 |vpiParent: \_design: (work@oh_fifo_async) |vpiFullName:work@oh_ao211 |vpiParameter: \_parameter: (work@oh_ao211.DW), line:8:29, endln:8:31 |vpiParent: - \_module: work@oh_ao211 (work@oh_ao211), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao211.v, line:8:1, endln:19:10 + \_module_inst: work@oh_ao211 (work@oh_ao211), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao211.v, line:8:1, endln:19:10 |UINT:1 |vpiTypespec: \_int_typespec: @@ -4501,7 +4501,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:8:29, endln:8:35 |vpiParent: - \_module: work@oh_ao211 (work@oh_ao211), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao211.v, line:8:1, endln:19:10 + \_module_inst: work@oh_ao211 (work@oh_ao211), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao211.v, line:8:1, endln:19:10 |vpiRhs: \_constant: , line:8:34, endln:8:35 |vpiDecompile:1 @@ -4517,37 +4517,37 @@ design: (work@oh_fifo_async) |vpiNet: \_logic_net: (work@oh_ao211.a0), line:10:21, endln:10:23 |vpiParent: - \_module: work@oh_ao211 (work@oh_ao211), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao211.v, line:8:1, endln:19:10 + \_module_inst: work@oh_ao211 (work@oh_ao211), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao211.v, line:8:1, endln:19:10 |vpiName:a0 |vpiFullName:work@oh_ao211.a0 |vpiNet: \_logic_net: (work@oh_ao211.a1), line:11:21, endln:11:23 |vpiParent: - \_module: work@oh_ao211 (work@oh_ao211), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao211.v, line:8:1, endln:19:10 + \_module_inst: work@oh_ao211 (work@oh_ao211), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao211.v, line:8:1, endln:19:10 |vpiName:a1 |vpiFullName:work@oh_ao211.a1 |vpiNet: \_logic_net: (work@oh_ao211.b0), line:12:21, endln:12:23 |vpiParent: - \_module: work@oh_ao211 (work@oh_ao211), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao211.v, line:8:1, endln:19:10 + \_module_inst: work@oh_ao211 (work@oh_ao211), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao211.v, line:8:1, endln:19:10 |vpiName:b0 |vpiFullName:work@oh_ao211.b0 |vpiNet: \_logic_net: (work@oh_ao211.c0), line:13:21, endln:13:23 |vpiParent: - \_module: work@oh_ao211 (work@oh_ao211), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao211.v, line:8:1, endln:19:10 + \_module_inst: work@oh_ao211 (work@oh_ao211), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao211.v, line:8:1, endln:19:10 |vpiName:c0 |vpiFullName:work@oh_ao211.c0 |vpiNet: \_logic_net: (work@oh_ao211.z), line:14:21, endln:14:22 |vpiParent: - \_module: work@oh_ao211 (work@oh_ao211), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao211.v, line:8:1, endln:19:10 + \_module_inst: work@oh_ao211 (work@oh_ao211), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao211.v, line:8:1, endln:19:10 |vpiName:z |vpiFullName:work@oh_ao211.z |vpiPort: \_port: (a0), line:10:21, endln:10:23 |vpiParent: - \_module: work@oh_ao211 (work@oh_ao211), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao211.v, line:8:1, endln:19:10 + \_module_inst: work@oh_ao211 (work@oh_ao211), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao211.v, line:8:1, endln:19:10 |vpiName:a0 |vpiDirection:1 |vpiLowConn: @@ -4587,7 +4587,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (a1), line:11:21, endln:11:23 |vpiParent: - \_module: work@oh_ao211 (work@oh_ao211), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao211.v, line:8:1, endln:19:10 + \_module_inst: work@oh_ao211 (work@oh_ao211), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao211.v, line:8:1, endln:19:10 |vpiName:a1 |vpiDirection:1 |vpiLowConn: @@ -4627,7 +4627,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (b0), line:12:21, endln:12:23 |vpiParent: - \_module: work@oh_ao211 (work@oh_ao211), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao211.v, line:8:1, endln:19:10 + \_module_inst: work@oh_ao211 (work@oh_ao211), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao211.v, line:8:1, endln:19:10 |vpiName:b0 |vpiDirection:1 |vpiLowConn: @@ -4667,7 +4667,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (c0), line:13:21, endln:13:23 |vpiParent: - \_module: work@oh_ao211 (work@oh_ao211), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao211.v, line:8:1, endln:19:10 + \_module_inst: work@oh_ao211 (work@oh_ao211), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao211.v, line:8:1, endln:19:10 |vpiName:c0 |vpiDirection:1 |vpiLowConn: @@ -4707,7 +4707,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (z), line:14:21, endln:14:22 |vpiParent: - \_module: work@oh_ao211 (work@oh_ao211), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao211.v, line:8:1, endln:19:10 + \_module_inst: work@oh_ao211 (work@oh_ao211), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao211.v, line:8:1, endln:19:10 |vpiName:z |vpiDirection:2 |vpiLowConn: @@ -4747,7 +4747,7 @@ design: (work@oh_fifo_async) |vpiContAssign: \_cont_assign: , line:17:11, endln:17:34 |vpiParent: - \_module: work@oh_ao211 (work@oh_ao211), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao211.v, line:8:1, endln:19:10 + \_module_inst: work@oh_ao211 (work@oh_ao211), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao211.v, line:8:1, endln:19:10 |vpiRhs: \_operation: , line:17:15, endln:17:34 |vpiParent: @@ -4794,14 +4794,14 @@ design: (work@oh_fifo_async) |vpiName:z |vpiFullName:work@oh_ao211.z |uhdmallModules: -\_module: work@oh_ao22 (work@oh_ao22), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao22.v, line:8:1, endln:19:10 +\_module_inst: work@oh_ao22 (work@oh_ao22), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao22.v, line:8:1, endln:19:10 |vpiParent: \_design: (work@oh_fifo_async) |vpiFullName:work@oh_ao22 |vpiParameter: \_parameter: (work@oh_ao22.DW), line:8:28, endln:8:30 |vpiParent: - \_module: work@oh_ao22 (work@oh_ao22), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao22.v, line:8:1, endln:19:10 + \_module_inst: work@oh_ao22 (work@oh_ao22), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao22.v, line:8:1, endln:19:10 |UINT:1 |vpiTypespec: \_int_typespec: @@ -4810,7 +4810,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:8:28, endln:8:34 |vpiParent: - \_module: work@oh_ao22 (work@oh_ao22), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao22.v, line:8:1, endln:19:10 + \_module_inst: work@oh_ao22 (work@oh_ao22), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao22.v, line:8:1, endln:19:10 |vpiRhs: \_constant: , line:8:33, endln:8:34 |vpiDecompile:1 @@ -4826,37 +4826,37 @@ design: (work@oh_fifo_async) |vpiNet: \_logic_net: (work@oh_ao22.a0), line:10:21, endln:10:23 |vpiParent: - \_module: work@oh_ao22 (work@oh_ao22), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao22.v, line:8:1, endln:19:10 + \_module_inst: work@oh_ao22 (work@oh_ao22), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao22.v, line:8:1, endln:19:10 |vpiName:a0 |vpiFullName:work@oh_ao22.a0 |vpiNet: \_logic_net: (work@oh_ao22.a1), line:11:21, endln:11:23 |vpiParent: - \_module: work@oh_ao22 (work@oh_ao22), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao22.v, line:8:1, endln:19:10 + \_module_inst: work@oh_ao22 (work@oh_ao22), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao22.v, line:8:1, endln:19:10 |vpiName:a1 |vpiFullName:work@oh_ao22.a1 |vpiNet: \_logic_net: (work@oh_ao22.b0), line:12:21, endln:12:23 |vpiParent: - \_module: work@oh_ao22 (work@oh_ao22), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao22.v, line:8:1, endln:19:10 + \_module_inst: work@oh_ao22 (work@oh_ao22), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao22.v, line:8:1, endln:19:10 |vpiName:b0 |vpiFullName:work@oh_ao22.b0 |vpiNet: \_logic_net: (work@oh_ao22.b1), line:13:21, endln:13:23 |vpiParent: - \_module: work@oh_ao22 (work@oh_ao22), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao22.v, line:8:1, endln:19:10 + \_module_inst: work@oh_ao22 (work@oh_ao22), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao22.v, line:8:1, endln:19:10 |vpiName:b1 |vpiFullName:work@oh_ao22.b1 |vpiNet: \_logic_net: (work@oh_ao22.z), line:14:21, endln:14:22 |vpiParent: - \_module: work@oh_ao22 (work@oh_ao22), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao22.v, line:8:1, endln:19:10 + \_module_inst: work@oh_ao22 (work@oh_ao22), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao22.v, line:8:1, endln:19:10 |vpiName:z |vpiFullName:work@oh_ao22.z |vpiPort: \_port: (a0), line:10:21, endln:10:23 |vpiParent: - \_module: work@oh_ao22 (work@oh_ao22), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao22.v, line:8:1, endln:19:10 + \_module_inst: work@oh_ao22 (work@oh_ao22), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao22.v, line:8:1, endln:19:10 |vpiName:a0 |vpiDirection:1 |vpiLowConn: @@ -4896,7 +4896,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (a1), line:11:21, endln:11:23 |vpiParent: - \_module: work@oh_ao22 (work@oh_ao22), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao22.v, line:8:1, endln:19:10 + \_module_inst: work@oh_ao22 (work@oh_ao22), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao22.v, line:8:1, endln:19:10 |vpiName:a1 |vpiDirection:1 |vpiLowConn: @@ -4936,7 +4936,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (b0), line:12:21, endln:12:23 |vpiParent: - \_module: work@oh_ao22 (work@oh_ao22), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao22.v, line:8:1, endln:19:10 + \_module_inst: work@oh_ao22 (work@oh_ao22), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao22.v, line:8:1, endln:19:10 |vpiName:b0 |vpiDirection:1 |vpiLowConn: @@ -4976,7 +4976,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (b1), line:13:21, endln:13:23 |vpiParent: - \_module: work@oh_ao22 (work@oh_ao22), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao22.v, line:8:1, endln:19:10 + \_module_inst: work@oh_ao22 (work@oh_ao22), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao22.v, line:8:1, endln:19:10 |vpiName:b1 |vpiDirection:1 |vpiLowConn: @@ -5016,7 +5016,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (z), line:14:21, endln:14:22 |vpiParent: - \_module: work@oh_ao22 (work@oh_ao22), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao22.v, line:8:1, endln:19:10 + \_module_inst: work@oh_ao22 (work@oh_ao22), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao22.v, line:8:1, endln:19:10 |vpiName:z |vpiDirection:2 |vpiLowConn: @@ -5056,7 +5056,7 @@ design: (work@oh_fifo_async) |vpiContAssign: \_cont_assign: , line:17:11, endln:17:36 |vpiParent: - \_module: work@oh_ao22 (work@oh_ao22), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao22.v, line:8:1, endln:19:10 + \_module_inst: work@oh_ao22 (work@oh_ao22), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao22.v, line:8:1, endln:19:10 |vpiRhs: \_operation: , line:17:15, endln:17:36 |vpiParent: @@ -5103,14 +5103,14 @@ design: (work@oh_fifo_async) |vpiName:z |vpiFullName:work@oh_ao22.z |uhdmallModules: -\_module: work@oh_ao221 (work@oh_ao221), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao221.v, line:8:1, endln:20:10 +\_module_inst: work@oh_ao221 (work@oh_ao221), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao221.v, line:8:1, endln:20:10 |vpiParent: \_design: (work@oh_fifo_async) |vpiFullName:work@oh_ao221 |vpiParameter: \_parameter: (work@oh_ao221.DW), line:8:29, endln:8:31 |vpiParent: - \_module: work@oh_ao221 (work@oh_ao221), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao221.v, line:8:1, endln:20:10 + \_module_inst: work@oh_ao221 (work@oh_ao221), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao221.v, line:8:1, endln:20:10 |UINT:1 |vpiTypespec: \_int_typespec: @@ -5119,7 +5119,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:8:29, endln:8:35 |vpiParent: - \_module: work@oh_ao221 (work@oh_ao221), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao221.v, line:8:1, endln:20:10 + \_module_inst: work@oh_ao221 (work@oh_ao221), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao221.v, line:8:1, endln:20:10 |vpiRhs: \_constant: , line:8:34, endln:8:35 |vpiDecompile:1 @@ -5135,43 +5135,43 @@ design: (work@oh_fifo_async) |vpiNet: \_logic_net: (work@oh_ao221.a0), line:10:21, endln:10:23 |vpiParent: - \_module: work@oh_ao221 (work@oh_ao221), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao221.v, line:8:1, endln:20:10 + \_module_inst: work@oh_ao221 (work@oh_ao221), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao221.v, line:8:1, endln:20:10 |vpiName:a0 |vpiFullName:work@oh_ao221.a0 |vpiNet: \_logic_net: (work@oh_ao221.a1), line:11:21, endln:11:23 |vpiParent: - \_module: work@oh_ao221 (work@oh_ao221), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao221.v, line:8:1, endln:20:10 + \_module_inst: work@oh_ao221 (work@oh_ao221), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao221.v, line:8:1, endln:20:10 |vpiName:a1 |vpiFullName:work@oh_ao221.a1 |vpiNet: \_logic_net: (work@oh_ao221.b0), line:12:21, endln:12:23 |vpiParent: - \_module: work@oh_ao221 (work@oh_ao221), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao221.v, line:8:1, endln:20:10 + \_module_inst: work@oh_ao221 (work@oh_ao221), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao221.v, line:8:1, endln:20:10 |vpiName:b0 |vpiFullName:work@oh_ao221.b0 |vpiNet: \_logic_net: (work@oh_ao221.b1), line:13:21, endln:13:23 |vpiParent: - \_module: work@oh_ao221 (work@oh_ao221), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao221.v, line:8:1, endln:20:10 + \_module_inst: work@oh_ao221 (work@oh_ao221), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao221.v, line:8:1, endln:20:10 |vpiName:b1 |vpiFullName:work@oh_ao221.b1 |vpiNet: \_logic_net: (work@oh_ao221.c0), line:14:21, endln:14:23 |vpiParent: - \_module: work@oh_ao221 (work@oh_ao221), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao221.v, line:8:1, endln:20:10 + \_module_inst: work@oh_ao221 (work@oh_ao221), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao221.v, line:8:1, endln:20:10 |vpiName:c0 |vpiFullName:work@oh_ao221.c0 |vpiNet: \_logic_net: (work@oh_ao221.z), line:15:21, endln:15:22 |vpiParent: - \_module: work@oh_ao221 (work@oh_ao221), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao221.v, line:8:1, endln:20:10 + \_module_inst: work@oh_ao221 (work@oh_ao221), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao221.v, line:8:1, endln:20:10 |vpiName:z |vpiFullName:work@oh_ao221.z |vpiPort: \_port: (a0), line:10:21, endln:10:23 |vpiParent: - \_module: work@oh_ao221 (work@oh_ao221), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao221.v, line:8:1, endln:20:10 + \_module_inst: work@oh_ao221 (work@oh_ao221), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao221.v, line:8:1, endln:20:10 |vpiName:a0 |vpiDirection:1 |vpiLowConn: @@ -5211,7 +5211,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (a1), line:11:21, endln:11:23 |vpiParent: - \_module: work@oh_ao221 (work@oh_ao221), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao221.v, line:8:1, endln:20:10 + \_module_inst: work@oh_ao221 (work@oh_ao221), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao221.v, line:8:1, endln:20:10 |vpiName:a1 |vpiDirection:1 |vpiLowConn: @@ -5251,7 +5251,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (b0), line:12:21, endln:12:23 |vpiParent: - \_module: work@oh_ao221 (work@oh_ao221), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao221.v, line:8:1, endln:20:10 + \_module_inst: work@oh_ao221 (work@oh_ao221), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao221.v, line:8:1, endln:20:10 |vpiName:b0 |vpiDirection:1 |vpiLowConn: @@ -5291,7 +5291,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (b1), line:13:21, endln:13:23 |vpiParent: - \_module: work@oh_ao221 (work@oh_ao221), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao221.v, line:8:1, endln:20:10 + \_module_inst: work@oh_ao221 (work@oh_ao221), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao221.v, line:8:1, endln:20:10 |vpiName:b1 |vpiDirection:1 |vpiLowConn: @@ -5331,7 +5331,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (c0), line:14:21, endln:14:23 |vpiParent: - \_module: work@oh_ao221 (work@oh_ao221), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao221.v, line:8:1, endln:20:10 + \_module_inst: work@oh_ao221 (work@oh_ao221), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao221.v, line:8:1, endln:20:10 |vpiName:c0 |vpiDirection:1 |vpiLowConn: @@ -5371,7 +5371,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (z), line:15:21, endln:15:22 |vpiParent: - \_module: work@oh_ao221 (work@oh_ao221), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao221.v, line:8:1, endln:20:10 + \_module_inst: work@oh_ao221 (work@oh_ao221), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao221.v, line:8:1, endln:20:10 |vpiName:z |vpiDirection:2 |vpiLowConn: @@ -5411,7 +5411,7 @@ design: (work@oh_fifo_async) |vpiContAssign: \_cont_assign: , line:18:11, endln:18:43 |vpiParent: - \_module: work@oh_ao221 (work@oh_ao221), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao221.v, line:8:1, endln:20:10 + \_module_inst: work@oh_ao221 (work@oh_ao221), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao221.v, line:8:1, endln:20:10 |vpiRhs: \_operation: , line:18:15, endln:18:43 |vpiParent: @@ -5469,14 +5469,14 @@ design: (work@oh_fifo_async) |vpiName:z |vpiFullName:work@oh_ao221.z |uhdmallModules: -\_module: work@oh_ao222 (work@oh_ao222), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao222.v, line:8:1, endln:21:10 +\_module_inst: work@oh_ao222 (work@oh_ao222), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao222.v, line:8:1, endln:21:10 |vpiParent: \_design: (work@oh_fifo_async) |vpiFullName:work@oh_ao222 |vpiParameter: \_parameter: (work@oh_ao222.DW), line:8:29, endln:8:31 |vpiParent: - \_module: work@oh_ao222 (work@oh_ao222), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao222.v, line:8:1, endln:21:10 + \_module_inst: work@oh_ao222 (work@oh_ao222), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao222.v, line:8:1, endln:21:10 |UINT:1 |vpiTypespec: \_int_typespec: @@ -5485,7 +5485,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:8:29, endln:8:35 |vpiParent: - \_module: work@oh_ao222 (work@oh_ao222), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao222.v, line:8:1, endln:21:10 + \_module_inst: work@oh_ao222 (work@oh_ao222), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao222.v, line:8:1, endln:21:10 |vpiRhs: \_constant: , line:8:34, endln:8:35 |vpiDecompile:1 @@ -5501,49 +5501,49 @@ design: (work@oh_fifo_async) |vpiNet: \_logic_net: (work@oh_ao222.a0), line:10:21, endln:10:23 |vpiParent: - \_module: work@oh_ao222 (work@oh_ao222), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao222.v, line:8:1, endln:21:10 + \_module_inst: work@oh_ao222 (work@oh_ao222), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao222.v, line:8:1, endln:21:10 |vpiName:a0 |vpiFullName:work@oh_ao222.a0 |vpiNet: \_logic_net: (work@oh_ao222.a1), line:11:21, endln:11:23 |vpiParent: - \_module: work@oh_ao222 (work@oh_ao222), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao222.v, line:8:1, endln:21:10 + \_module_inst: work@oh_ao222 (work@oh_ao222), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao222.v, line:8:1, endln:21:10 |vpiName:a1 |vpiFullName:work@oh_ao222.a1 |vpiNet: \_logic_net: (work@oh_ao222.b0), line:12:21, endln:12:23 |vpiParent: - \_module: work@oh_ao222 (work@oh_ao222), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao222.v, line:8:1, endln:21:10 + \_module_inst: work@oh_ao222 (work@oh_ao222), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao222.v, line:8:1, endln:21:10 |vpiName:b0 |vpiFullName:work@oh_ao222.b0 |vpiNet: \_logic_net: (work@oh_ao222.b1), line:13:21, endln:13:23 |vpiParent: - \_module: work@oh_ao222 (work@oh_ao222), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao222.v, line:8:1, endln:21:10 + \_module_inst: work@oh_ao222 (work@oh_ao222), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao222.v, line:8:1, endln:21:10 |vpiName:b1 |vpiFullName:work@oh_ao222.b1 |vpiNet: \_logic_net: (work@oh_ao222.c0), line:14:21, endln:14:23 |vpiParent: - \_module: work@oh_ao222 (work@oh_ao222), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao222.v, line:8:1, endln:21:10 + \_module_inst: work@oh_ao222 (work@oh_ao222), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao222.v, line:8:1, endln:21:10 |vpiName:c0 |vpiFullName:work@oh_ao222.c0 |vpiNet: \_logic_net: (work@oh_ao222.c1), line:15:21, endln:15:23 |vpiParent: - \_module: work@oh_ao222 (work@oh_ao222), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao222.v, line:8:1, endln:21:10 + \_module_inst: work@oh_ao222 (work@oh_ao222), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao222.v, line:8:1, endln:21:10 |vpiName:c1 |vpiFullName:work@oh_ao222.c1 |vpiNet: \_logic_net: (work@oh_ao222.z), line:16:21, endln:16:22 |vpiParent: - \_module: work@oh_ao222 (work@oh_ao222), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao222.v, line:8:1, endln:21:10 + \_module_inst: work@oh_ao222 (work@oh_ao222), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao222.v, line:8:1, endln:21:10 |vpiName:z |vpiFullName:work@oh_ao222.z |vpiPort: \_port: (a0), line:10:21, endln:10:23 |vpiParent: - \_module: work@oh_ao222 (work@oh_ao222), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao222.v, line:8:1, endln:21:10 + \_module_inst: work@oh_ao222 (work@oh_ao222), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao222.v, line:8:1, endln:21:10 |vpiName:a0 |vpiDirection:1 |vpiLowConn: @@ -5583,7 +5583,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (a1), line:11:21, endln:11:23 |vpiParent: - \_module: work@oh_ao222 (work@oh_ao222), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao222.v, line:8:1, endln:21:10 + \_module_inst: work@oh_ao222 (work@oh_ao222), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao222.v, line:8:1, endln:21:10 |vpiName:a1 |vpiDirection:1 |vpiLowConn: @@ -5623,7 +5623,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (b0), line:12:21, endln:12:23 |vpiParent: - \_module: work@oh_ao222 (work@oh_ao222), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao222.v, line:8:1, endln:21:10 + \_module_inst: work@oh_ao222 (work@oh_ao222), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao222.v, line:8:1, endln:21:10 |vpiName:b0 |vpiDirection:1 |vpiLowConn: @@ -5663,7 +5663,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (b1), line:13:21, endln:13:23 |vpiParent: - \_module: work@oh_ao222 (work@oh_ao222), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao222.v, line:8:1, endln:21:10 + \_module_inst: work@oh_ao222 (work@oh_ao222), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao222.v, line:8:1, endln:21:10 |vpiName:b1 |vpiDirection:1 |vpiLowConn: @@ -5703,7 +5703,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (c0), line:14:21, endln:14:23 |vpiParent: - \_module: work@oh_ao222 (work@oh_ao222), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao222.v, line:8:1, endln:21:10 + \_module_inst: work@oh_ao222 (work@oh_ao222), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao222.v, line:8:1, endln:21:10 |vpiName:c0 |vpiDirection:1 |vpiLowConn: @@ -5743,7 +5743,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (c1), line:15:21, endln:15:23 |vpiParent: - \_module: work@oh_ao222 (work@oh_ao222), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao222.v, line:8:1, endln:21:10 + \_module_inst: work@oh_ao222 (work@oh_ao222), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao222.v, line:8:1, endln:21:10 |vpiName:c1 |vpiDirection:1 |vpiLowConn: @@ -5783,7 +5783,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (z), line:16:21, endln:16:22 |vpiParent: - \_module: work@oh_ao222 (work@oh_ao222), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao222.v, line:8:1, endln:21:10 + \_module_inst: work@oh_ao222 (work@oh_ao222), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao222.v, line:8:1, endln:21:10 |vpiName:z |vpiDirection:2 |vpiLowConn: @@ -5823,7 +5823,7 @@ design: (work@oh_fifo_async) |vpiContAssign: \_cont_assign: , line:19:11, endln:19:48 |vpiParent: - \_module: work@oh_ao222 (work@oh_ao222), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao222.v, line:8:1, endln:21:10 + \_module_inst: work@oh_ao222 (work@oh_ao222), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao222.v, line:8:1, endln:21:10 |vpiRhs: \_operation: , line:19:15, endln:19:48 |vpiParent: @@ -5892,14 +5892,14 @@ design: (work@oh_fifo_async) |vpiName:z |vpiFullName:work@oh_ao222.z |uhdmallModules: -\_module: work@oh_ao31 (work@oh_ao31), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao31.v, line:7:1, endln:18:10 +\_module_inst: work@oh_ao31 (work@oh_ao31), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao31.v, line:7:1, endln:18:10 |vpiParent: \_design: (work@oh_fifo_async) |vpiFullName:work@oh_ao31 |vpiParameter: \_parameter: (work@oh_ao31.DW), line:7:28, endln:7:30 |vpiParent: - \_module: work@oh_ao31 (work@oh_ao31), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao31.v, line:7:1, endln:18:10 + \_module_inst: work@oh_ao31 (work@oh_ao31), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao31.v, line:7:1, endln:18:10 |UINT:1 |vpiTypespec: \_int_typespec: @@ -5908,7 +5908,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:7:28, endln:7:34 |vpiParent: - \_module: work@oh_ao31 (work@oh_ao31), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao31.v, line:7:1, endln:18:10 + \_module_inst: work@oh_ao31 (work@oh_ao31), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao31.v, line:7:1, endln:18:10 |vpiRhs: \_constant: , line:7:33, endln:7:34 |vpiDecompile:1 @@ -5924,37 +5924,37 @@ design: (work@oh_fifo_async) |vpiNet: \_logic_net: (work@oh_ao31.a0), line:9:21, endln:9:23 |vpiParent: - \_module: work@oh_ao31 (work@oh_ao31), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao31.v, line:7:1, endln:18:10 + \_module_inst: work@oh_ao31 (work@oh_ao31), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao31.v, line:7:1, endln:18:10 |vpiName:a0 |vpiFullName:work@oh_ao31.a0 |vpiNet: \_logic_net: (work@oh_ao31.a1), line:10:21, endln:10:23 |vpiParent: - \_module: work@oh_ao31 (work@oh_ao31), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao31.v, line:7:1, endln:18:10 + \_module_inst: work@oh_ao31 (work@oh_ao31), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao31.v, line:7:1, endln:18:10 |vpiName:a1 |vpiFullName:work@oh_ao31.a1 |vpiNet: \_logic_net: (work@oh_ao31.a2), line:11:21, endln:11:23 |vpiParent: - \_module: work@oh_ao31 (work@oh_ao31), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao31.v, line:7:1, endln:18:10 + \_module_inst: work@oh_ao31 (work@oh_ao31), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao31.v, line:7:1, endln:18:10 |vpiName:a2 |vpiFullName:work@oh_ao31.a2 |vpiNet: \_logic_net: (work@oh_ao31.b0), line:12:21, endln:12:23 |vpiParent: - \_module: work@oh_ao31 (work@oh_ao31), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao31.v, line:7:1, endln:18:10 + \_module_inst: work@oh_ao31 (work@oh_ao31), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao31.v, line:7:1, endln:18:10 |vpiName:b0 |vpiFullName:work@oh_ao31.b0 |vpiNet: \_logic_net: (work@oh_ao31.z), line:13:21, endln:13:22 |vpiParent: - \_module: work@oh_ao31 (work@oh_ao31), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao31.v, line:7:1, endln:18:10 + \_module_inst: work@oh_ao31 (work@oh_ao31), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao31.v, line:7:1, endln:18:10 |vpiName:z |vpiFullName:work@oh_ao31.z |vpiPort: \_port: (a0), line:9:21, endln:9:23 |vpiParent: - \_module: work@oh_ao31 (work@oh_ao31), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao31.v, line:7:1, endln:18:10 + \_module_inst: work@oh_ao31 (work@oh_ao31), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao31.v, line:7:1, endln:18:10 |vpiName:a0 |vpiDirection:1 |vpiLowConn: @@ -5994,7 +5994,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (a1), line:10:21, endln:10:23 |vpiParent: - \_module: work@oh_ao31 (work@oh_ao31), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao31.v, line:7:1, endln:18:10 + \_module_inst: work@oh_ao31 (work@oh_ao31), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao31.v, line:7:1, endln:18:10 |vpiName:a1 |vpiDirection:1 |vpiLowConn: @@ -6034,7 +6034,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (a2), line:11:21, endln:11:23 |vpiParent: - \_module: work@oh_ao31 (work@oh_ao31), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao31.v, line:7:1, endln:18:10 + \_module_inst: work@oh_ao31 (work@oh_ao31), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao31.v, line:7:1, endln:18:10 |vpiName:a2 |vpiDirection:1 |vpiLowConn: @@ -6074,7 +6074,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (b0), line:12:21, endln:12:23 |vpiParent: - \_module: work@oh_ao31 (work@oh_ao31), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao31.v, line:7:1, endln:18:10 + \_module_inst: work@oh_ao31 (work@oh_ao31), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao31.v, line:7:1, endln:18:10 |vpiName:b0 |vpiDirection:1 |vpiLowConn: @@ -6114,7 +6114,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (z), line:13:21, endln:13:22 |vpiParent: - \_module: work@oh_ao31 (work@oh_ao31), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao31.v, line:7:1, endln:18:10 + \_module_inst: work@oh_ao31 (work@oh_ao31), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao31.v, line:7:1, endln:18:10 |vpiName:z |vpiDirection:2 |vpiLowConn: @@ -6154,7 +6154,7 @@ design: (work@oh_fifo_async) |vpiContAssign: \_cont_assign: , line:16:11, endln:16:34 |vpiParent: - \_module: work@oh_ao31 (work@oh_ao31), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao31.v, line:7:1, endln:18:10 + \_module_inst: work@oh_ao31 (work@oh_ao31), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao31.v, line:7:1, endln:18:10 |vpiRhs: \_operation: , line:16:15, endln:16:34 |vpiParent: @@ -6201,14 +6201,14 @@ design: (work@oh_fifo_async) |vpiName:z |vpiFullName:work@oh_ao31.z |uhdmallModules: -\_module: work@oh_ao311 (work@oh_ao311), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao311.v, line:7:1, endln:19:10 +\_module_inst: work@oh_ao311 (work@oh_ao311), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao311.v, line:7:1, endln:19:10 |vpiParent: \_design: (work@oh_fifo_async) |vpiFullName:work@oh_ao311 |vpiParameter: \_parameter: (work@oh_ao311.DW), line:7:29, endln:7:31 |vpiParent: - \_module: work@oh_ao311 (work@oh_ao311), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao311.v, line:7:1, endln:19:10 + \_module_inst: work@oh_ao311 (work@oh_ao311), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao311.v, line:7:1, endln:19:10 |UINT:1 |vpiTypespec: \_int_typespec: @@ -6217,7 +6217,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:7:29, endln:7:35 |vpiParent: - \_module: work@oh_ao311 (work@oh_ao311), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao311.v, line:7:1, endln:19:10 + \_module_inst: work@oh_ao311 (work@oh_ao311), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao311.v, line:7:1, endln:19:10 |vpiRhs: \_constant: , line:7:34, endln:7:35 |vpiDecompile:1 @@ -6233,43 +6233,43 @@ design: (work@oh_fifo_async) |vpiNet: \_logic_net: (work@oh_ao311.a0), line:9:21, endln:9:23 |vpiParent: - \_module: work@oh_ao311 (work@oh_ao311), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao311.v, line:7:1, endln:19:10 + \_module_inst: work@oh_ao311 (work@oh_ao311), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao311.v, line:7:1, endln:19:10 |vpiName:a0 |vpiFullName:work@oh_ao311.a0 |vpiNet: \_logic_net: (work@oh_ao311.a1), line:10:21, endln:10:23 |vpiParent: - \_module: work@oh_ao311 (work@oh_ao311), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao311.v, line:7:1, endln:19:10 + \_module_inst: work@oh_ao311 (work@oh_ao311), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao311.v, line:7:1, endln:19:10 |vpiName:a1 |vpiFullName:work@oh_ao311.a1 |vpiNet: \_logic_net: (work@oh_ao311.a2), line:11:21, endln:11:23 |vpiParent: - \_module: work@oh_ao311 (work@oh_ao311), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao311.v, line:7:1, endln:19:10 + \_module_inst: work@oh_ao311 (work@oh_ao311), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao311.v, line:7:1, endln:19:10 |vpiName:a2 |vpiFullName:work@oh_ao311.a2 |vpiNet: \_logic_net: (work@oh_ao311.b0), line:12:21, endln:12:23 |vpiParent: - \_module: work@oh_ao311 (work@oh_ao311), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao311.v, line:7:1, endln:19:10 + \_module_inst: work@oh_ao311 (work@oh_ao311), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao311.v, line:7:1, endln:19:10 |vpiName:b0 |vpiFullName:work@oh_ao311.b0 |vpiNet: \_logic_net: (work@oh_ao311.c0), line:13:21, endln:13:23 |vpiParent: - \_module: work@oh_ao311 (work@oh_ao311), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao311.v, line:7:1, endln:19:10 + \_module_inst: work@oh_ao311 (work@oh_ao311), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao311.v, line:7:1, endln:19:10 |vpiName:c0 |vpiFullName:work@oh_ao311.c0 |vpiNet: \_logic_net: (work@oh_ao311.z), line:14:21, endln:14:22 |vpiParent: - \_module: work@oh_ao311 (work@oh_ao311), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao311.v, line:7:1, endln:19:10 + \_module_inst: work@oh_ao311 (work@oh_ao311), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao311.v, line:7:1, endln:19:10 |vpiName:z |vpiFullName:work@oh_ao311.z |vpiPort: \_port: (a0), line:9:21, endln:9:23 |vpiParent: - \_module: work@oh_ao311 (work@oh_ao311), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao311.v, line:7:1, endln:19:10 + \_module_inst: work@oh_ao311 (work@oh_ao311), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao311.v, line:7:1, endln:19:10 |vpiName:a0 |vpiDirection:1 |vpiLowConn: @@ -6309,7 +6309,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (a1), line:10:21, endln:10:23 |vpiParent: - \_module: work@oh_ao311 (work@oh_ao311), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao311.v, line:7:1, endln:19:10 + \_module_inst: work@oh_ao311 (work@oh_ao311), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao311.v, line:7:1, endln:19:10 |vpiName:a1 |vpiDirection:1 |vpiLowConn: @@ -6349,7 +6349,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (a2), line:11:21, endln:11:23 |vpiParent: - \_module: work@oh_ao311 (work@oh_ao311), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao311.v, line:7:1, endln:19:10 + \_module_inst: work@oh_ao311 (work@oh_ao311), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao311.v, line:7:1, endln:19:10 |vpiName:a2 |vpiDirection:1 |vpiLowConn: @@ -6389,7 +6389,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (b0), line:12:21, endln:12:23 |vpiParent: - \_module: work@oh_ao311 (work@oh_ao311), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao311.v, line:7:1, endln:19:10 + \_module_inst: work@oh_ao311 (work@oh_ao311), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao311.v, line:7:1, endln:19:10 |vpiName:b0 |vpiDirection:1 |vpiLowConn: @@ -6429,7 +6429,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (c0), line:13:21, endln:13:23 |vpiParent: - \_module: work@oh_ao311 (work@oh_ao311), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao311.v, line:7:1, endln:19:10 + \_module_inst: work@oh_ao311 (work@oh_ao311), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao311.v, line:7:1, endln:19:10 |vpiName:c0 |vpiDirection:1 |vpiLowConn: @@ -6469,7 +6469,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (z), line:14:21, endln:14:22 |vpiParent: - \_module: work@oh_ao311 (work@oh_ao311), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao311.v, line:7:1, endln:19:10 + \_module_inst: work@oh_ao311 (work@oh_ao311), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao311.v, line:7:1, endln:19:10 |vpiName:z |vpiDirection:2 |vpiLowConn: @@ -6509,7 +6509,7 @@ design: (work@oh_fifo_async) |vpiContAssign: \_cont_assign: , line:17:11, endln:17:39 |vpiParent: - \_module: work@oh_ao311 (work@oh_ao311), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao311.v, line:7:1, endln:19:10 + \_module_inst: work@oh_ao311 (work@oh_ao311), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao311.v, line:7:1, endln:19:10 |vpiRhs: \_operation: , line:17:15, endln:17:39 |vpiParent: @@ -6567,14 +6567,14 @@ design: (work@oh_fifo_async) |vpiName:z |vpiFullName:work@oh_ao311.z |uhdmallModules: -\_module: work@oh_ao32 (work@oh_ao32), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao32.v, line:7:1, endln:19:10 +\_module_inst: work@oh_ao32 (work@oh_ao32), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao32.v, line:7:1, endln:19:10 |vpiParent: \_design: (work@oh_fifo_async) |vpiFullName:work@oh_ao32 |vpiParameter: \_parameter: (work@oh_ao32.DW), line:7:28, endln:7:30 |vpiParent: - \_module: work@oh_ao32 (work@oh_ao32), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao32.v, line:7:1, endln:19:10 + \_module_inst: work@oh_ao32 (work@oh_ao32), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao32.v, line:7:1, endln:19:10 |UINT:1 |vpiTypespec: \_int_typespec: @@ -6583,7 +6583,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:7:28, endln:7:34 |vpiParent: - \_module: work@oh_ao32 (work@oh_ao32), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao32.v, line:7:1, endln:19:10 + \_module_inst: work@oh_ao32 (work@oh_ao32), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao32.v, line:7:1, endln:19:10 |vpiRhs: \_constant: , line:7:33, endln:7:34 |vpiDecompile:1 @@ -6599,43 +6599,43 @@ design: (work@oh_fifo_async) |vpiNet: \_logic_net: (work@oh_ao32.a0), line:9:21, endln:9:23 |vpiParent: - \_module: work@oh_ao32 (work@oh_ao32), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao32.v, line:7:1, endln:19:10 + \_module_inst: work@oh_ao32 (work@oh_ao32), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao32.v, line:7:1, endln:19:10 |vpiName:a0 |vpiFullName:work@oh_ao32.a0 |vpiNet: \_logic_net: (work@oh_ao32.a1), line:10:21, endln:10:23 |vpiParent: - \_module: work@oh_ao32 (work@oh_ao32), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao32.v, line:7:1, endln:19:10 + \_module_inst: work@oh_ao32 (work@oh_ao32), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao32.v, line:7:1, endln:19:10 |vpiName:a1 |vpiFullName:work@oh_ao32.a1 |vpiNet: \_logic_net: (work@oh_ao32.a2), line:11:21, endln:11:23 |vpiParent: - \_module: work@oh_ao32 (work@oh_ao32), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao32.v, line:7:1, endln:19:10 + \_module_inst: work@oh_ao32 (work@oh_ao32), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao32.v, line:7:1, endln:19:10 |vpiName:a2 |vpiFullName:work@oh_ao32.a2 |vpiNet: \_logic_net: (work@oh_ao32.b0), line:12:21, endln:12:23 |vpiParent: - \_module: work@oh_ao32 (work@oh_ao32), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao32.v, line:7:1, endln:19:10 + \_module_inst: work@oh_ao32 (work@oh_ao32), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao32.v, line:7:1, endln:19:10 |vpiName:b0 |vpiFullName:work@oh_ao32.b0 |vpiNet: \_logic_net: (work@oh_ao32.b1), line:13:21, endln:13:23 |vpiParent: - \_module: work@oh_ao32 (work@oh_ao32), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao32.v, line:7:1, endln:19:10 + \_module_inst: work@oh_ao32 (work@oh_ao32), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao32.v, line:7:1, endln:19:10 |vpiName:b1 |vpiFullName:work@oh_ao32.b1 |vpiNet: \_logic_net: (work@oh_ao32.z), line:14:21, endln:14:22 |vpiParent: - \_module: work@oh_ao32 (work@oh_ao32), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao32.v, line:7:1, endln:19:10 + \_module_inst: work@oh_ao32 (work@oh_ao32), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao32.v, line:7:1, endln:19:10 |vpiName:z |vpiFullName:work@oh_ao32.z |vpiPort: \_port: (a0), line:9:21, endln:9:23 |vpiParent: - \_module: work@oh_ao32 (work@oh_ao32), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao32.v, line:7:1, endln:19:10 + \_module_inst: work@oh_ao32 (work@oh_ao32), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao32.v, line:7:1, endln:19:10 |vpiName:a0 |vpiDirection:1 |vpiLowConn: @@ -6675,7 +6675,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (a1), line:10:21, endln:10:23 |vpiParent: - \_module: work@oh_ao32 (work@oh_ao32), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao32.v, line:7:1, endln:19:10 + \_module_inst: work@oh_ao32 (work@oh_ao32), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao32.v, line:7:1, endln:19:10 |vpiName:a1 |vpiDirection:1 |vpiLowConn: @@ -6715,7 +6715,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (a2), line:11:21, endln:11:23 |vpiParent: - \_module: work@oh_ao32 (work@oh_ao32), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao32.v, line:7:1, endln:19:10 + \_module_inst: work@oh_ao32 (work@oh_ao32), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao32.v, line:7:1, endln:19:10 |vpiName:a2 |vpiDirection:1 |vpiLowConn: @@ -6755,7 +6755,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (b0), line:12:21, endln:12:23 |vpiParent: - \_module: work@oh_ao32 (work@oh_ao32), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao32.v, line:7:1, endln:19:10 + \_module_inst: work@oh_ao32 (work@oh_ao32), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao32.v, line:7:1, endln:19:10 |vpiName:b0 |vpiDirection:1 |vpiLowConn: @@ -6795,7 +6795,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (b1), line:13:21, endln:13:23 |vpiParent: - \_module: work@oh_ao32 (work@oh_ao32), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao32.v, line:7:1, endln:19:10 + \_module_inst: work@oh_ao32 (work@oh_ao32), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao32.v, line:7:1, endln:19:10 |vpiName:b1 |vpiDirection:1 |vpiLowConn: @@ -6835,7 +6835,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (z), line:14:21, endln:14:22 |vpiParent: - \_module: work@oh_ao32 (work@oh_ao32), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao32.v, line:7:1, endln:19:10 + \_module_inst: work@oh_ao32 (work@oh_ao32), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao32.v, line:7:1, endln:19:10 |vpiName:z |vpiDirection:2 |vpiLowConn: @@ -6875,7 +6875,7 @@ design: (work@oh_fifo_async) |vpiContAssign: \_cont_assign: , line:17:11, endln:17:41 |vpiParent: - \_module: work@oh_ao32 (work@oh_ao32), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao32.v, line:7:1, endln:19:10 + \_module_inst: work@oh_ao32 (work@oh_ao32), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao32.v, line:7:1, endln:19:10 |vpiRhs: \_operation: , line:17:15, endln:17:41 |vpiParent: @@ -6933,14 +6933,14 @@ design: (work@oh_fifo_async) |vpiName:z |vpiFullName:work@oh_ao32.z |uhdmallModules: -\_module: work@oh_ao33 (work@oh_ao33), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao33.v, line:7:1, endln:20:10 +\_module_inst: work@oh_ao33 (work@oh_ao33), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao33.v, line:7:1, endln:20:10 |vpiParent: \_design: (work@oh_fifo_async) |vpiFullName:work@oh_ao33 |vpiParameter: \_parameter: (work@oh_ao33.DW), line:7:28, endln:7:30 |vpiParent: - \_module: work@oh_ao33 (work@oh_ao33), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao33.v, line:7:1, endln:20:10 + \_module_inst: work@oh_ao33 (work@oh_ao33), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao33.v, line:7:1, endln:20:10 |UINT:1 |vpiTypespec: \_int_typespec: @@ -6949,7 +6949,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:7:28, endln:7:34 |vpiParent: - \_module: work@oh_ao33 (work@oh_ao33), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao33.v, line:7:1, endln:20:10 + \_module_inst: work@oh_ao33 (work@oh_ao33), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao33.v, line:7:1, endln:20:10 |vpiRhs: \_constant: , line:7:33, endln:7:34 |vpiDecompile:1 @@ -6965,49 +6965,49 @@ design: (work@oh_fifo_async) |vpiNet: \_logic_net: (work@oh_ao33.a0), line:9:21, endln:9:23 |vpiParent: - \_module: work@oh_ao33 (work@oh_ao33), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao33.v, line:7:1, endln:20:10 + \_module_inst: work@oh_ao33 (work@oh_ao33), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao33.v, line:7:1, endln:20:10 |vpiName:a0 |vpiFullName:work@oh_ao33.a0 |vpiNet: \_logic_net: (work@oh_ao33.a1), line:10:21, endln:10:23 |vpiParent: - \_module: work@oh_ao33 (work@oh_ao33), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao33.v, line:7:1, endln:20:10 + \_module_inst: work@oh_ao33 (work@oh_ao33), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao33.v, line:7:1, endln:20:10 |vpiName:a1 |vpiFullName:work@oh_ao33.a1 |vpiNet: \_logic_net: (work@oh_ao33.a2), line:11:21, endln:11:23 |vpiParent: - \_module: work@oh_ao33 (work@oh_ao33), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao33.v, line:7:1, endln:20:10 + \_module_inst: work@oh_ao33 (work@oh_ao33), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao33.v, line:7:1, endln:20:10 |vpiName:a2 |vpiFullName:work@oh_ao33.a2 |vpiNet: \_logic_net: (work@oh_ao33.b0), line:12:21, endln:12:23 |vpiParent: - \_module: work@oh_ao33 (work@oh_ao33), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao33.v, line:7:1, endln:20:10 + \_module_inst: work@oh_ao33 (work@oh_ao33), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao33.v, line:7:1, endln:20:10 |vpiName:b0 |vpiFullName:work@oh_ao33.b0 |vpiNet: \_logic_net: (work@oh_ao33.b1), line:13:21, endln:13:23 |vpiParent: - \_module: work@oh_ao33 (work@oh_ao33), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao33.v, line:7:1, endln:20:10 + \_module_inst: work@oh_ao33 (work@oh_ao33), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao33.v, line:7:1, endln:20:10 |vpiName:b1 |vpiFullName:work@oh_ao33.b1 |vpiNet: \_logic_net: (work@oh_ao33.b2), line:14:21, endln:14:23 |vpiParent: - \_module: work@oh_ao33 (work@oh_ao33), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao33.v, line:7:1, endln:20:10 + \_module_inst: work@oh_ao33 (work@oh_ao33), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao33.v, line:7:1, endln:20:10 |vpiName:b2 |vpiFullName:work@oh_ao33.b2 |vpiNet: \_logic_net: (work@oh_ao33.z), line:15:21, endln:15:22 |vpiParent: - \_module: work@oh_ao33 (work@oh_ao33), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao33.v, line:7:1, endln:20:10 + \_module_inst: work@oh_ao33 (work@oh_ao33), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao33.v, line:7:1, endln:20:10 |vpiName:z |vpiFullName:work@oh_ao33.z |vpiPort: \_port: (a0), line:9:21, endln:9:23 |vpiParent: - \_module: work@oh_ao33 (work@oh_ao33), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao33.v, line:7:1, endln:20:10 + \_module_inst: work@oh_ao33 (work@oh_ao33), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao33.v, line:7:1, endln:20:10 |vpiName:a0 |vpiDirection:1 |vpiLowConn: @@ -7047,7 +7047,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (a1), line:10:21, endln:10:23 |vpiParent: - \_module: work@oh_ao33 (work@oh_ao33), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao33.v, line:7:1, endln:20:10 + \_module_inst: work@oh_ao33 (work@oh_ao33), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao33.v, line:7:1, endln:20:10 |vpiName:a1 |vpiDirection:1 |vpiLowConn: @@ -7087,7 +7087,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (a2), line:11:21, endln:11:23 |vpiParent: - \_module: work@oh_ao33 (work@oh_ao33), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao33.v, line:7:1, endln:20:10 + \_module_inst: work@oh_ao33 (work@oh_ao33), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao33.v, line:7:1, endln:20:10 |vpiName:a2 |vpiDirection:1 |vpiLowConn: @@ -7127,7 +7127,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (b0), line:12:21, endln:12:23 |vpiParent: - \_module: work@oh_ao33 (work@oh_ao33), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao33.v, line:7:1, endln:20:10 + \_module_inst: work@oh_ao33 (work@oh_ao33), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao33.v, line:7:1, endln:20:10 |vpiName:b0 |vpiDirection:1 |vpiLowConn: @@ -7167,7 +7167,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (b1), line:13:21, endln:13:23 |vpiParent: - \_module: work@oh_ao33 (work@oh_ao33), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao33.v, line:7:1, endln:20:10 + \_module_inst: work@oh_ao33 (work@oh_ao33), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao33.v, line:7:1, endln:20:10 |vpiName:b1 |vpiDirection:1 |vpiLowConn: @@ -7207,7 +7207,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (b2), line:14:21, endln:14:23 |vpiParent: - \_module: work@oh_ao33 (work@oh_ao33), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao33.v, line:7:1, endln:20:10 + \_module_inst: work@oh_ao33 (work@oh_ao33), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao33.v, line:7:1, endln:20:10 |vpiName:b2 |vpiDirection:1 |vpiLowConn: @@ -7247,7 +7247,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (z), line:15:21, endln:15:22 |vpiParent: - \_module: work@oh_ao33 (work@oh_ao33), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao33.v, line:7:1, endln:20:10 + \_module_inst: work@oh_ao33 (work@oh_ao33), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao33.v, line:7:1, endln:20:10 |vpiName:z |vpiDirection:2 |vpiLowConn: @@ -7287,7 +7287,7 @@ design: (work@oh_fifo_async) |vpiContAssign: \_cont_assign: , line:18:11, endln:18:46 |vpiParent: - \_module: work@oh_ao33 (work@oh_ao33), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao33.v, line:7:1, endln:20:10 + \_module_inst: work@oh_ao33 (work@oh_ao33), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao33.v, line:7:1, endln:20:10 |vpiRhs: \_operation: , line:18:15, endln:18:46 |vpiParent: @@ -7356,14 +7356,14 @@ design: (work@oh_fifo_async) |vpiName:z |vpiFullName:work@oh_ao33.z |uhdmallModules: -\_module: work@oh_aoi21 (work@oh_aoi21), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi21.v, line:8:1, endln:18:10 +\_module_inst: work@oh_aoi21 (work@oh_aoi21), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi21.v, line:8:1, endln:18:10 |vpiParent: \_design: (work@oh_fifo_async) |vpiFullName:work@oh_aoi21 |vpiParameter: \_parameter: (work@oh_aoi21.DW), line:8:29, endln:8:31 |vpiParent: - \_module: work@oh_aoi21 (work@oh_aoi21), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi21.v, line:8:1, endln:18:10 + \_module_inst: work@oh_aoi21 (work@oh_aoi21), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi21.v, line:8:1, endln:18:10 |UINT:1 |vpiTypespec: \_int_typespec: @@ -7372,7 +7372,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:8:29, endln:8:35 |vpiParent: - \_module: work@oh_aoi21 (work@oh_aoi21), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi21.v, line:8:1, endln:18:10 + \_module_inst: work@oh_aoi21 (work@oh_aoi21), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi21.v, line:8:1, endln:18:10 |vpiRhs: \_constant: , line:8:34, endln:8:35 |vpiDecompile:1 @@ -7388,31 +7388,31 @@ design: (work@oh_fifo_async) |vpiNet: \_logic_net: (work@oh_aoi21.a0), line:10:21, endln:10:23 |vpiParent: - \_module: work@oh_aoi21 (work@oh_aoi21), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi21.v, line:8:1, endln:18:10 + \_module_inst: work@oh_aoi21 (work@oh_aoi21), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi21.v, line:8:1, endln:18:10 |vpiName:a0 |vpiFullName:work@oh_aoi21.a0 |vpiNet: \_logic_net: (work@oh_aoi21.a1), line:11:21, endln:11:23 |vpiParent: - \_module: work@oh_aoi21 (work@oh_aoi21), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi21.v, line:8:1, endln:18:10 + \_module_inst: work@oh_aoi21 (work@oh_aoi21), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi21.v, line:8:1, endln:18:10 |vpiName:a1 |vpiFullName:work@oh_aoi21.a1 |vpiNet: \_logic_net: (work@oh_aoi21.b0), line:12:21, endln:12:23 |vpiParent: - \_module: work@oh_aoi21 (work@oh_aoi21), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi21.v, line:8:1, endln:18:10 + \_module_inst: work@oh_aoi21 (work@oh_aoi21), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi21.v, line:8:1, endln:18:10 |vpiName:b0 |vpiFullName:work@oh_aoi21.b0 |vpiNet: \_logic_net: (work@oh_aoi21.z), line:13:21, endln:13:22 |vpiParent: - \_module: work@oh_aoi21 (work@oh_aoi21), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi21.v, line:8:1, endln:18:10 + \_module_inst: work@oh_aoi21 (work@oh_aoi21), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi21.v, line:8:1, endln:18:10 |vpiName:z |vpiFullName:work@oh_aoi21.z |vpiPort: \_port: (a0), line:10:21, endln:10:23 |vpiParent: - \_module: work@oh_aoi21 (work@oh_aoi21), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi21.v, line:8:1, endln:18:10 + \_module_inst: work@oh_aoi21 (work@oh_aoi21), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi21.v, line:8:1, endln:18:10 |vpiName:a0 |vpiDirection:1 |vpiLowConn: @@ -7452,7 +7452,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (a1), line:11:21, endln:11:23 |vpiParent: - \_module: work@oh_aoi21 (work@oh_aoi21), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi21.v, line:8:1, endln:18:10 + \_module_inst: work@oh_aoi21 (work@oh_aoi21), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi21.v, line:8:1, endln:18:10 |vpiName:a1 |vpiDirection:1 |vpiLowConn: @@ -7492,7 +7492,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (b0), line:12:21, endln:12:23 |vpiParent: - \_module: work@oh_aoi21 (work@oh_aoi21), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi21.v, line:8:1, endln:18:10 + \_module_inst: work@oh_aoi21 (work@oh_aoi21), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi21.v, line:8:1, endln:18:10 |vpiName:b0 |vpiDirection:1 |vpiLowConn: @@ -7532,7 +7532,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (z), line:13:21, endln:13:22 |vpiParent: - \_module: work@oh_aoi21 (work@oh_aoi21), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi21.v, line:8:1, endln:18:10 + \_module_inst: work@oh_aoi21 (work@oh_aoi21), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi21.v, line:8:1, endln:18:10 |vpiName:z |vpiDirection:2 |vpiLowConn: @@ -7572,7 +7572,7 @@ design: (work@oh_fifo_async) |vpiContAssign: \_cont_assign: , line:16:11, endln:16:32 |vpiParent: - \_module: work@oh_aoi21 (work@oh_aoi21), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi21.v, line:8:1, endln:18:10 + \_module_inst: work@oh_aoi21 (work@oh_aoi21), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi21.v, line:8:1, endln:18:10 |vpiRhs: \_operation: , line:16:15, endln:16:32 |vpiParent: @@ -7613,14 +7613,14 @@ design: (work@oh_fifo_async) |vpiName:z |vpiFullName:work@oh_aoi21.z |uhdmallModules: -\_module: work@oh_aoi211 (work@oh_aoi211), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi211.v, line:8:1, endln:19:10 +\_module_inst: work@oh_aoi211 (work@oh_aoi211), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi211.v, line:8:1, endln:19:10 |vpiParent: \_design: (work@oh_fifo_async) |vpiFullName:work@oh_aoi211 |vpiParameter: \_parameter: (work@oh_aoi211.DW), line:8:30, endln:8:32 |vpiParent: - \_module: work@oh_aoi211 (work@oh_aoi211), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi211.v, line:8:1, endln:19:10 + \_module_inst: work@oh_aoi211 (work@oh_aoi211), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi211.v, line:8:1, endln:19:10 |UINT:1 |vpiTypespec: \_int_typespec: @@ -7629,7 +7629,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:8:30, endln:8:36 |vpiParent: - \_module: work@oh_aoi211 (work@oh_aoi211), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi211.v, line:8:1, endln:19:10 + \_module_inst: work@oh_aoi211 (work@oh_aoi211), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi211.v, line:8:1, endln:19:10 |vpiRhs: \_constant: , line:8:35, endln:8:36 |vpiDecompile:1 @@ -7645,37 +7645,37 @@ design: (work@oh_fifo_async) |vpiNet: \_logic_net: (work@oh_aoi211.a0), line:10:21, endln:10:23 |vpiParent: - \_module: work@oh_aoi211 (work@oh_aoi211), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi211.v, line:8:1, endln:19:10 + \_module_inst: work@oh_aoi211 (work@oh_aoi211), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi211.v, line:8:1, endln:19:10 |vpiName:a0 |vpiFullName:work@oh_aoi211.a0 |vpiNet: \_logic_net: (work@oh_aoi211.a1), line:11:21, endln:11:23 |vpiParent: - \_module: work@oh_aoi211 (work@oh_aoi211), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi211.v, line:8:1, endln:19:10 + \_module_inst: work@oh_aoi211 (work@oh_aoi211), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi211.v, line:8:1, endln:19:10 |vpiName:a1 |vpiFullName:work@oh_aoi211.a1 |vpiNet: \_logic_net: (work@oh_aoi211.b0), line:12:21, endln:12:23 |vpiParent: - \_module: work@oh_aoi211 (work@oh_aoi211), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi211.v, line:8:1, endln:19:10 + \_module_inst: work@oh_aoi211 (work@oh_aoi211), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi211.v, line:8:1, endln:19:10 |vpiName:b0 |vpiFullName:work@oh_aoi211.b0 |vpiNet: \_logic_net: (work@oh_aoi211.c0), line:13:21, endln:13:23 |vpiParent: - \_module: work@oh_aoi211 (work@oh_aoi211), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi211.v, line:8:1, endln:19:10 + \_module_inst: work@oh_aoi211 (work@oh_aoi211), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi211.v, line:8:1, endln:19:10 |vpiName:c0 |vpiFullName:work@oh_aoi211.c0 |vpiNet: \_logic_net: (work@oh_aoi211.z), line:14:21, endln:14:22 |vpiParent: - \_module: work@oh_aoi211 (work@oh_aoi211), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi211.v, line:8:1, endln:19:10 + \_module_inst: work@oh_aoi211 (work@oh_aoi211), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi211.v, line:8:1, endln:19:10 |vpiName:z |vpiFullName:work@oh_aoi211.z |vpiPort: \_port: (a0), line:10:21, endln:10:23 |vpiParent: - \_module: work@oh_aoi211 (work@oh_aoi211), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi211.v, line:8:1, endln:19:10 + \_module_inst: work@oh_aoi211 (work@oh_aoi211), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi211.v, line:8:1, endln:19:10 |vpiName:a0 |vpiDirection:1 |vpiLowConn: @@ -7715,7 +7715,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (a1), line:11:21, endln:11:23 |vpiParent: - \_module: work@oh_aoi211 (work@oh_aoi211), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi211.v, line:8:1, endln:19:10 + \_module_inst: work@oh_aoi211 (work@oh_aoi211), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi211.v, line:8:1, endln:19:10 |vpiName:a1 |vpiDirection:1 |vpiLowConn: @@ -7755,7 +7755,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (b0), line:12:21, endln:12:23 |vpiParent: - \_module: work@oh_aoi211 (work@oh_aoi211), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi211.v, line:8:1, endln:19:10 + \_module_inst: work@oh_aoi211 (work@oh_aoi211), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi211.v, line:8:1, endln:19:10 |vpiName:b0 |vpiDirection:1 |vpiLowConn: @@ -7795,7 +7795,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (c0), line:13:21, endln:13:23 |vpiParent: - \_module: work@oh_aoi211 (work@oh_aoi211), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi211.v, line:8:1, endln:19:10 + \_module_inst: work@oh_aoi211 (work@oh_aoi211), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi211.v, line:8:1, endln:19:10 |vpiName:c0 |vpiDirection:1 |vpiLowConn: @@ -7835,7 +7835,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (z), line:14:21, endln:14:22 |vpiParent: - \_module: work@oh_aoi211 (work@oh_aoi211), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi211.v, line:8:1, endln:19:10 + \_module_inst: work@oh_aoi211 (work@oh_aoi211), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi211.v, line:8:1, endln:19:10 |vpiName:z |vpiDirection:2 |vpiLowConn: @@ -7875,7 +7875,7 @@ design: (work@oh_fifo_async) |vpiContAssign: \_cont_assign: , line:17:11, endln:17:37 |vpiParent: - \_module: work@oh_aoi211 (work@oh_aoi211), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi211.v, line:8:1, endln:19:10 + \_module_inst: work@oh_aoi211 (work@oh_aoi211), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi211.v, line:8:1, endln:19:10 |vpiRhs: \_operation: , line:17:15, endln:17:37 |vpiParent: @@ -7927,14 +7927,14 @@ design: (work@oh_fifo_async) |vpiName:z |vpiFullName:work@oh_aoi211.z |uhdmallModules: -\_module: work@oh_aoi22 (work@oh_aoi22), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi22.v, line:7:1, endln:18:10 +\_module_inst: work@oh_aoi22 (work@oh_aoi22), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi22.v, line:7:1, endln:18:10 |vpiParent: \_design: (work@oh_fifo_async) |vpiFullName:work@oh_aoi22 |vpiParameter: \_parameter: (work@oh_aoi22.DW), line:7:29, endln:7:31 |vpiParent: - \_module: work@oh_aoi22 (work@oh_aoi22), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi22.v, line:7:1, endln:18:10 + \_module_inst: work@oh_aoi22 (work@oh_aoi22), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi22.v, line:7:1, endln:18:10 |UINT:1 |vpiTypespec: \_int_typespec: @@ -7943,7 +7943,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:7:29, endln:7:35 |vpiParent: - \_module: work@oh_aoi22 (work@oh_aoi22), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi22.v, line:7:1, endln:18:10 + \_module_inst: work@oh_aoi22 (work@oh_aoi22), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi22.v, line:7:1, endln:18:10 |vpiRhs: \_constant: , line:7:34, endln:7:35 |vpiDecompile:1 @@ -7959,37 +7959,37 @@ design: (work@oh_fifo_async) |vpiNet: \_logic_net: (work@oh_aoi22.a0), line:9:21, endln:9:23 |vpiParent: - \_module: work@oh_aoi22 (work@oh_aoi22), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi22.v, line:7:1, endln:18:10 + \_module_inst: work@oh_aoi22 (work@oh_aoi22), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi22.v, line:7:1, endln:18:10 |vpiName:a0 |vpiFullName:work@oh_aoi22.a0 |vpiNet: \_logic_net: (work@oh_aoi22.a1), line:10:21, endln:10:23 |vpiParent: - \_module: work@oh_aoi22 (work@oh_aoi22), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi22.v, line:7:1, endln:18:10 + \_module_inst: work@oh_aoi22 (work@oh_aoi22), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi22.v, line:7:1, endln:18:10 |vpiName:a1 |vpiFullName:work@oh_aoi22.a1 |vpiNet: \_logic_net: (work@oh_aoi22.b0), line:11:21, endln:11:23 |vpiParent: - \_module: work@oh_aoi22 (work@oh_aoi22), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi22.v, line:7:1, endln:18:10 + \_module_inst: work@oh_aoi22 (work@oh_aoi22), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi22.v, line:7:1, endln:18:10 |vpiName:b0 |vpiFullName:work@oh_aoi22.b0 |vpiNet: \_logic_net: (work@oh_aoi22.b1), line:12:21, endln:12:23 |vpiParent: - \_module: work@oh_aoi22 (work@oh_aoi22), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi22.v, line:7:1, endln:18:10 + \_module_inst: work@oh_aoi22 (work@oh_aoi22), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi22.v, line:7:1, endln:18:10 |vpiName:b1 |vpiFullName:work@oh_aoi22.b1 |vpiNet: \_logic_net: (work@oh_aoi22.z), line:13:21, endln:13:22 |vpiParent: - \_module: work@oh_aoi22 (work@oh_aoi22), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi22.v, line:7:1, endln:18:10 + \_module_inst: work@oh_aoi22 (work@oh_aoi22), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi22.v, line:7:1, endln:18:10 |vpiName:z |vpiFullName:work@oh_aoi22.z |vpiPort: \_port: (a0), line:9:21, endln:9:23 |vpiParent: - \_module: work@oh_aoi22 (work@oh_aoi22), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi22.v, line:7:1, endln:18:10 + \_module_inst: work@oh_aoi22 (work@oh_aoi22), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi22.v, line:7:1, endln:18:10 |vpiName:a0 |vpiDirection:1 |vpiLowConn: @@ -8029,7 +8029,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (a1), line:10:21, endln:10:23 |vpiParent: - \_module: work@oh_aoi22 (work@oh_aoi22), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi22.v, line:7:1, endln:18:10 + \_module_inst: work@oh_aoi22 (work@oh_aoi22), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi22.v, line:7:1, endln:18:10 |vpiName:a1 |vpiDirection:1 |vpiLowConn: @@ -8069,7 +8069,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (b0), line:11:21, endln:11:23 |vpiParent: - \_module: work@oh_aoi22 (work@oh_aoi22), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi22.v, line:7:1, endln:18:10 + \_module_inst: work@oh_aoi22 (work@oh_aoi22), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi22.v, line:7:1, endln:18:10 |vpiName:b0 |vpiDirection:1 |vpiLowConn: @@ -8109,7 +8109,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (b1), line:12:21, endln:12:23 |vpiParent: - \_module: work@oh_aoi22 (work@oh_aoi22), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi22.v, line:7:1, endln:18:10 + \_module_inst: work@oh_aoi22 (work@oh_aoi22), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi22.v, line:7:1, endln:18:10 |vpiName:b1 |vpiDirection:1 |vpiLowConn: @@ -8149,7 +8149,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (z), line:13:21, endln:13:22 |vpiParent: - \_module: work@oh_aoi22 (work@oh_aoi22), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi22.v, line:7:1, endln:18:10 + \_module_inst: work@oh_aoi22 (work@oh_aoi22), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi22.v, line:7:1, endln:18:10 |vpiName:z |vpiDirection:2 |vpiLowConn: @@ -8189,7 +8189,7 @@ design: (work@oh_fifo_async) |vpiContAssign: \_cont_assign: , line:16:11, endln:16:39 |vpiParent: - \_module: work@oh_aoi22 (work@oh_aoi22), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi22.v, line:7:1, endln:18:10 + \_module_inst: work@oh_aoi22 (work@oh_aoi22), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi22.v, line:7:1, endln:18:10 |vpiRhs: \_operation: , line:16:15, endln:16:39 |vpiParent: @@ -8241,14 +8241,14 @@ design: (work@oh_fifo_async) |vpiName:z |vpiFullName:work@oh_aoi22.z |uhdmallModules: -\_module: work@oh_aoi221 (work@oh_aoi221), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi221.v, line:8:1, endln:20:10 +\_module_inst: work@oh_aoi221 (work@oh_aoi221), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi221.v, line:8:1, endln:20:10 |vpiParent: \_design: (work@oh_fifo_async) |vpiFullName:work@oh_aoi221 |vpiParameter: \_parameter: (work@oh_aoi221.DW), line:8:30, endln:8:32 |vpiParent: - \_module: work@oh_aoi221 (work@oh_aoi221), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi221.v, line:8:1, endln:20:10 + \_module_inst: work@oh_aoi221 (work@oh_aoi221), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi221.v, line:8:1, endln:20:10 |UINT:1 |vpiTypespec: \_int_typespec: @@ -8257,7 +8257,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:8:30, endln:8:36 |vpiParent: - \_module: work@oh_aoi221 (work@oh_aoi221), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi221.v, line:8:1, endln:20:10 + \_module_inst: work@oh_aoi221 (work@oh_aoi221), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi221.v, line:8:1, endln:20:10 |vpiRhs: \_constant: , line:8:35, endln:8:36 |vpiDecompile:1 @@ -8273,43 +8273,43 @@ design: (work@oh_fifo_async) |vpiNet: \_logic_net: (work@oh_aoi221.a0), line:10:21, endln:10:23 |vpiParent: - \_module: work@oh_aoi221 (work@oh_aoi221), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi221.v, line:8:1, endln:20:10 + \_module_inst: work@oh_aoi221 (work@oh_aoi221), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi221.v, line:8:1, endln:20:10 |vpiName:a0 |vpiFullName:work@oh_aoi221.a0 |vpiNet: \_logic_net: (work@oh_aoi221.a1), line:11:21, endln:11:23 |vpiParent: - \_module: work@oh_aoi221 (work@oh_aoi221), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi221.v, line:8:1, endln:20:10 + \_module_inst: work@oh_aoi221 (work@oh_aoi221), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi221.v, line:8:1, endln:20:10 |vpiName:a1 |vpiFullName:work@oh_aoi221.a1 |vpiNet: \_logic_net: (work@oh_aoi221.b0), line:12:21, endln:12:23 |vpiParent: - \_module: work@oh_aoi221 (work@oh_aoi221), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi221.v, line:8:1, endln:20:10 + \_module_inst: work@oh_aoi221 (work@oh_aoi221), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi221.v, line:8:1, endln:20:10 |vpiName:b0 |vpiFullName:work@oh_aoi221.b0 |vpiNet: \_logic_net: (work@oh_aoi221.b1), line:13:21, endln:13:23 |vpiParent: - \_module: work@oh_aoi221 (work@oh_aoi221), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi221.v, line:8:1, endln:20:10 + \_module_inst: work@oh_aoi221 (work@oh_aoi221), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi221.v, line:8:1, endln:20:10 |vpiName:b1 |vpiFullName:work@oh_aoi221.b1 |vpiNet: \_logic_net: (work@oh_aoi221.c0), line:14:21, endln:14:23 |vpiParent: - \_module: work@oh_aoi221 (work@oh_aoi221), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi221.v, line:8:1, endln:20:10 + \_module_inst: work@oh_aoi221 (work@oh_aoi221), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi221.v, line:8:1, endln:20:10 |vpiName:c0 |vpiFullName:work@oh_aoi221.c0 |vpiNet: \_logic_net: (work@oh_aoi221.z), line:15:21, endln:15:22 |vpiParent: - \_module: work@oh_aoi221 (work@oh_aoi221), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi221.v, line:8:1, endln:20:10 + \_module_inst: work@oh_aoi221 (work@oh_aoi221), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi221.v, line:8:1, endln:20:10 |vpiName:z |vpiFullName:work@oh_aoi221.z |vpiPort: \_port: (a0), line:10:21, endln:10:23 |vpiParent: - \_module: work@oh_aoi221 (work@oh_aoi221), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi221.v, line:8:1, endln:20:10 + \_module_inst: work@oh_aoi221 (work@oh_aoi221), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi221.v, line:8:1, endln:20:10 |vpiName:a0 |vpiDirection:1 |vpiLowConn: @@ -8349,7 +8349,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (a1), line:11:21, endln:11:23 |vpiParent: - \_module: work@oh_aoi221 (work@oh_aoi221), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi221.v, line:8:1, endln:20:10 + \_module_inst: work@oh_aoi221 (work@oh_aoi221), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi221.v, line:8:1, endln:20:10 |vpiName:a1 |vpiDirection:1 |vpiLowConn: @@ -8389,7 +8389,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (b0), line:12:21, endln:12:23 |vpiParent: - \_module: work@oh_aoi221 (work@oh_aoi221), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi221.v, line:8:1, endln:20:10 + \_module_inst: work@oh_aoi221 (work@oh_aoi221), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi221.v, line:8:1, endln:20:10 |vpiName:b0 |vpiDirection:1 |vpiLowConn: @@ -8429,7 +8429,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (b1), line:13:21, endln:13:23 |vpiParent: - \_module: work@oh_aoi221 (work@oh_aoi221), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi221.v, line:8:1, endln:20:10 + \_module_inst: work@oh_aoi221 (work@oh_aoi221), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi221.v, line:8:1, endln:20:10 |vpiName:b1 |vpiDirection:1 |vpiLowConn: @@ -8469,7 +8469,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (c0), line:14:21, endln:14:23 |vpiParent: - \_module: work@oh_aoi221 (work@oh_aoi221), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi221.v, line:8:1, endln:20:10 + \_module_inst: work@oh_aoi221 (work@oh_aoi221), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi221.v, line:8:1, endln:20:10 |vpiName:c0 |vpiDirection:1 |vpiLowConn: @@ -8509,7 +8509,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (z), line:15:21, endln:15:22 |vpiParent: - \_module: work@oh_aoi221 (work@oh_aoi221), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi221.v, line:8:1, endln:20:10 + \_module_inst: work@oh_aoi221 (work@oh_aoi221), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi221.v, line:8:1, endln:20:10 |vpiName:z |vpiDirection:2 |vpiLowConn: @@ -8549,7 +8549,7 @@ design: (work@oh_fifo_async) |vpiContAssign: \_cont_assign: , line:18:11, endln:18:44 |vpiParent: - \_module: work@oh_aoi221 (work@oh_aoi221), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi221.v, line:8:1, endln:20:10 + \_module_inst: work@oh_aoi221 (work@oh_aoi221), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi221.v, line:8:1, endln:20:10 |vpiRhs: \_operation: , line:18:15, endln:18:44 |vpiParent: @@ -8612,14 +8612,14 @@ design: (work@oh_fifo_async) |vpiName:z |vpiFullName:work@oh_aoi221.z |uhdmallModules: -\_module: work@oh_aoi222 (work@oh_aoi222), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi222.v, line:8:1, endln:21:10 +\_module_inst: work@oh_aoi222 (work@oh_aoi222), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi222.v, line:8:1, endln:21:10 |vpiParent: \_design: (work@oh_fifo_async) |vpiFullName:work@oh_aoi222 |vpiParameter: \_parameter: (work@oh_aoi222.DW), line:8:30, endln:8:32 |vpiParent: - \_module: work@oh_aoi222 (work@oh_aoi222), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi222.v, line:8:1, endln:21:10 + \_module_inst: work@oh_aoi222 (work@oh_aoi222), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi222.v, line:8:1, endln:21:10 |UINT:1 |vpiTypespec: \_int_typespec: @@ -8628,7 +8628,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:8:30, endln:8:36 |vpiParent: - \_module: work@oh_aoi222 (work@oh_aoi222), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi222.v, line:8:1, endln:21:10 + \_module_inst: work@oh_aoi222 (work@oh_aoi222), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi222.v, line:8:1, endln:21:10 |vpiRhs: \_constant: , line:8:35, endln:8:36 |vpiDecompile:1 @@ -8644,49 +8644,49 @@ design: (work@oh_fifo_async) |vpiNet: \_logic_net: (work@oh_aoi222.a0), line:10:21, endln:10:23 |vpiParent: - \_module: work@oh_aoi222 (work@oh_aoi222), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi222.v, line:8:1, endln:21:10 + \_module_inst: work@oh_aoi222 (work@oh_aoi222), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi222.v, line:8:1, endln:21:10 |vpiName:a0 |vpiFullName:work@oh_aoi222.a0 |vpiNet: \_logic_net: (work@oh_aoi222.a1), line:11:21, endln:11:23 |vpiParent: - \_module: work@oh_aoi222 (work@oh_aoi222), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi222.v, line:8:1, endln:21:10 + \_module_inst: work@oh_aoi222 (work@oh_aoi222), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi222.v, line:8:1, endln:21:10 |vpiName:a1 |vpiFullName:work@oh_aoi222.a1 |vpiNet: \_logic_net: (work@oh_aoi222.b0), line:12:21, endln:12:23 |vpiParent: - \_module: work@oh_aoi222 (work@oh_aoi222), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi222.v, line:8:1, endln:21:10 + \_module_inst: work@oh_aoi222 (work@oh_aoi222), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi222.v, line:8:1, endln:21:10 |vpiName:b0 |vpiFullName:work@oh_aoi222.b0 |vpiNet: \_logic_net: (work@oh_aoi222.b1), line:13:21, endln:13:23 |vpiParent: - \_module: work@oh_aoi222 (work@oh_aoi222), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi222.v, line:8:1, endln:21:10 + \_module_inst: work@oh_aoi222 (work@oh_aoi222), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi222.v, line:8:1, endln:21:10 |vpiName:b1 |vpiFullName:work@oh_aoi222.b1 |vpiNet: \_logic_net: (work@oh_aoi222.c0), line:14:21, endln:14:23 |vpiParent: - \_module: work@oh_aoi222 (work@oh_aoi222), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi222.v, line:8:1, endln:21:10 + \_module_inst: work@oh_aoi222 (work@oh_aoi222), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi222.v, line:8:1, endln:21:10 |vpiName:c0 |vpiFullName:work@oh_aoi222.c0 |vpiNet: \_logic_net: (work@oh_aoi222.c1), line:15:21, endln:15:23 |vpiParent: - \_module: work@oh_aoi222 (work@oh_aoi222), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi222.v, line:8:1, endln:21:10 + \_module_inst: work@oh_aoi222 (work@oh_aoi222), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi222.v, line:8:1, endln:21:10 |vpiName:c1 |vpiFullName:work@oh_aoi222.c1 |vpiNet: \_logic_net: (work@oh_aoi222.z), line:16:21, endln:16:22 |vpiParent: - \_module: work@oh_aoi222 (work@oh_aoi222), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi222.v, line:8:1, endln:21:10 + \_module_inst: work@oh_aoi222 (work@oh_aoi222), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi222.v, line:8:1, endln:21:10 |vpiName:z |vpiFullName:work@oh_aoi222.z |vpiPort: \_port: (a0), line:10:21, endln:10:23 |vpiParent: - \_module: work@oh_aoi222 (work@oh_aoi222), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi222.v, line:8:1, endln:21:10 + \_module_inst: work@oh_aoi222 (work@oh_aoi222), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi222.v, line:8:1, endln:21:10 |vpiName:a0 |vpiDirection:1 |vpiLowConn: @@ -8726,7 +8726,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (a1), line:11:21, endln:11:23 |vpiParent: - \_module: work@oh_aoi222 (work@oh_aoi222), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi222.v, line:8:1, endln:21:10 + \_module_inst: work@oh_aoi222 (work@oh_aoi222), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi222.v, line:8:1, endln:21:10 |vpiName:a1 |vpiDirection:1 |vpiLowConn: @@ -8766,7 +8766,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (b0), line:12:21, endln:12:23 |vpiParent: - \_module: work@oh_aoi222 (work@oh_aoi222), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi222.v, line:8:1, endln:21:10 + \_module_inst: work@oh_aoi222 (work@oh_aoi222), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi222.v, line:8:1, endln:21:10 |vpiName:b0 |vpiDirection:1 |vpiLowConn: @@ -8806,7 +8806,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (b1), line:13:21, endln:13:23 |vpiParent: - \_module: work@oh_aoi222 (work@oh_aoi222), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi222.v, line:8:1, endln:21:10 + \_module_inst: work@oh_aoi222 (work@oh_aoi222), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi222.v, line:8:1, endln:21:10 |vpiName:b1 |vpiDirection:1 |vpiLowConn: @@ -8846,7 +8846,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (c0), line:14:21, endln:14:23 |vpiParent: - \_module: work@oh_aoi222 (work@oh_aoi222), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi222.v, line:8:1, endln:21:10 + \_module_inst: work@oh_aoi222 (work@oh_aoi222), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi222.v, line:8:1, endln:21:10 |vpiName:c0 |vpiDirection:1 |vpiLowConn: @@ -8886,7 +8886,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (c1), line:15:21, endln:15:23 |vpiParent: - \_module: work@oh_aoi222 (work@oh_aoi222), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi222.v, line:8:1, endln:21:10 + \_module_inst: work@oh_aoi222 (work@oh_aoi222), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi222.v, line:8:1, endln:21:10 |vpiName:c1 |vpiDirection:1 |vpiLowConn: @@ -8926,7 +8926,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (z), line:16:21, endln:16:22 |vpiParent: - \_module: work@oh_aoi222 (work@oh_aoi222), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi222.v, line:8:1, endln:21:10 + \_module_inst: work@oh_aoi222 (work@oh_aoi222), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi222.v, line:8:1, endln:21:10 |vpiName:z |vpiDirection:2 |vpiLowConn: @@ -8966,7 +8966,7 @@ design: (work@oh_fifo_async) |vpiContAssign: \_cont_assign: , line:19:11, endln:19:51 |vpiParent: - \_module: work@oh_aoi222 (work@oh_aoi222), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi222.v, line:8:1, endln:21:10 + \_module_inst: work@oh_aoi222 (work@oh_aoi222), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi222.v, line:8:1, endln:21:10 |vpiRhs: \_operation: , line:19:15, endln:19:51 |vpiParent: @@ -9040,14 +9040,14 @@ design: (work@oh_fifo_async) |vpiName:z |vpiFullName:work@oh_aoi222.z |uhdmallModules: -\_module: work@oh_aoi31 (work@oh_aoi31), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi31.v, line:7:1, endln:18:10 +\_module_inst: work@oh_aoi31 (work@oh_aoi31), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi31.v, line:7:1, endln:18:10 |vpiParent: \_design: (work@oh_fifo_async) |vpiFullName:work@oh_aoi31 |vpiParameter: \_parameter: (work@oh_aoi31.DW), line:7:29, endln:7:31 |vpiParent: - \_module: work@oh_aoi31 (work@oh_aoi31), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi31.v, line:7:1, endln:18:10 + \_module_inst: work@oh_aoi31 (work@oh_aoi31), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi31.v, line:7:1, endln:18:10 |UINT:1 |vpiTypespec: \_int_typespec: @@ -9056,7 +9056,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:7:29, endln:7:35 |vpiParent: - \_module: work@oh_aoi31 (work@oh_aoi31), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi31.v, line:7:1, endln:18:10 + \_module_inst: work@oh_aoi31 (work@oh_aoi31), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi31.v, line:7:1, endln:18:10 |vpiRhs: \_constant: , line:7:34, endln:7:35 |vpiDecompile:1 @@ -9072,37 +9072,37 @@ design: (work@oh_fifo_async) |vpiNet: \_logic_net: (work@oh_aoi31.a0), line:9:21, endln:9:23 |vpiParent: - \_module: work@oh_aoi31 (work@oh_aoi31), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi31.v, line:7:1, endln:18:10 + \_module_inst: work@oh_aoi31 (work@oh_aoi31), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi31.v, line:7:1, endln:18:10 |vpiName:a0 |vpiFullName:work@oh_aoi31.a0 |vpiNet: \_logic_net: (work@oh_aoi31.a1), line:10:21, endln:10:23 |vpiParent: - \_module: work@oh_aoi31 (work@oh_aoi31), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi31.v, line:7:1, endln:18:10 + \_module_inst: work@oh_aoi31 (work@oh_aoi31), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi31.v, line:7:1, endln:18:10 |vpiName:a1 |vpiFullName:work@oh_aoi31.a1 |vpiNet: \_logic_net: (work@oh_aoi31.a2), line:11:21, endln:11:23 |vpiParent: - \_module: work@oh_aoi31 (work@oh_aoi31), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi31.v, line:7:1, endln:18:10 + \_module_inst: work@oh_aoi31 (work@oh_aoi31), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi31.v, line:7:1, endln:18:10 |vpiName:a2 |vpiFullName:work@oh_aoi31.a2 |vpiNet: \_logic_net: (work@oh_aoi31.b0), line:12:21, endln:12:23 |vpiParent: - \_module: work@oh_aoi31 (work@oh_aoi31), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi31.v, line:7:1, endln:18:10 + \_module_inst: work@oh_aoi31 (work@oh_aoi31), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi31.v, line:7:1, endln:18:10 |vpiName:b0 |vpiFullName:work@oh_aoi31.b0 |vpiNet: \_logic_net: (work@oh_aoi31.z), line:13:21, endln:13:22 |vpiParent: - \_module: work@oh_aoi31 (work@oh_aoi31), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi31.v, line:7:1, endln:18:10 + \_module_inst: work@oh_aoi31 (work@oh_aoi31), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi31.v, line:7:1, endln:18:10 |vpiName:z |vpiFullName:work@oh_aoi31.z |vpiPort: \_port: (a0), line:9:21, endln:9:23 |vpiParent: - \_module: work@oh_aoi31 (work@oh_aoi31), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi31.v, line:7:1, endln:18:10 + \_module_inst: work@oh_aoi31 (work@oh_aoi31), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi31.v, line:7:1, endln:18:10 |vpiName:a0 |vpiDirection:1 |vpiLowConn: @@ -9142,7 +9142,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (a1), line:10:21, endln:10:23 |vpiParent: - \_module: work@oh_aoi31 (work@oh_aoi31), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi31.v, line:7:1, endln:18:10 + \_module_inst: work@oh_aoi31 (work@oh_aoi31), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi31.v, line:7:1, endln:18:10 |vpiName:a1 |vpiDirection:1 |vpiLowConn: @@ -9182,7 +9182,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (a2), line:11:21, endln:11:23 |vpiParent: - \_module: work@oh_aoi31 (work@oh_aoi31), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi31.v, line:7:1, endln:18:10 + \_module_inst: work@oh_aoi31 (work@oh_aoi31), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi31.v, line:7:1, endln:18:10 |vpiName:a2 |vpiDirection:1 |vpiLowConn: @@ -9222,7 +9222,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (b0), line:12:21, endln:12:23 |vpiParent: - \_module: work@oh_aoi31 (work@oh_aoi31), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi31.v, line:7:1, endln:18:10 + \_module_inst: work@oh_aoi31 (work@oh_aoi31), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi31.v, line:7:1, endln:18:10 |vpiName:b0 |vpiDirection:1 |vpiLowConn: @@ -9262,7 +9262,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (z), line:13:21, endln:13:22 |vpiParent: - \_module: work@oh_aoi31 (work@oh_aoi31), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi31.v, line:7:1, endln:18:10 + \_module_inst: work@oh_aoi31 (work@oh_aoi31), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi31.v, line:7:1, endln:18:10 |vpiName:z |vpiDirection:2 |vpiLowConn: @@ -9302,7 +9302,7 @@ design: (work@oh_fifo_async) |vpiContAssign: \_cont_assign: , line:16:11, endln:16:37 |vpiParent: - \_module: work@oh_aoi31 (work@oh_aoi31), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi31.v, line:7:1, endln:18:10 + \_module_inst: work@oh_aoi31 (work@oh_aoi31), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi31.v, line:7:1, endln:18:10 |vpiRhs: \_operation: , line:16:15, endln:16:37 |vpiParent: @@ -9354,14 +9354,14 @@ design: (work@oh_fifo_async) |vpiName:z |vpiFullName:work@oh_aoi31.z |uhdmallModules: -\_module: work@oh_aoi311 (work@oh_aoi311), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi311.v, line:7:1, endln:19:10 +\_module_inst: work@oh_aoi311 (work@oh_aoi311), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi311.v, line:7:1, endln:19:10 |vpiParent: \_design: (work@oh_fifo_async) |vpiFullName:work@oh_aoi311 |vpiParameter: \_parameter: (work@oh_aoi311.DW), line:7:30, endln:7:32 |vpiParent: - \_module: work@oh_aoi311 (work@oh_aoi311), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi311.v, line:7:1, endln:19:10 + \_module_inst: work@oh_aoi311 (work@oh_aoi311), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi311.v, line:7:1, endln:19:10 |UINT:1 |vpiTypespec: \_int_typespec: @@ -9370,7 +9370,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:7:30, endln:7:36 |vpiParent: - \_module: work@oh_aoi311 (work@oh_aoi311), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi311.v, line:7:1, endln:19:10 + \_module_inst: work@oh_aoi311 (work@oh_aoi311), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi311.v, line:7:1, endln:19:10 |vpiRhs: \_constant: , line:7:35, endln:7:36 |vpiDecompile:1 @@ -9386,43 +9386,43 @@ design: (work@oh_fifo_async) |vpiNet: \_logic_net: (work@oh_aoi311.a0), line:9:21, endln:9:23 |vpiParent: - \_module: work@oh_aoi311 (work@oh_aoi311), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi311.v, line:7:1, endln:19:10 + \_module_inst: work@oh_aoi311 (work@oh_aoi311), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi311.v, line:7:1, endln:19:10 |vpiName:a0 |vpiFullName:work@oh_aoi311.a0 |vpiNet: \_logic_net: (work@oh_aoi311.a1), line:10:21, endln:10:23 |vpiParent: - \_module: work@oh_aoi311 (work@oh_aoi311), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi311.v, line:7:1, endln:19:10 + \_module_inst: work@oh_aoi311 (work@oh_aoi311), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi311.v, line:7:1, endln:19:10 |vpiName:a1 |vpiFullName:work@oh_aoi311.a1 |vpiNet: \_logic_net: (work@oh_aoi311.a2), line:11:21, endln:11:23 |vpiParent: - \_module: work@oh_aoi311 (work@oh_aoi311), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi311.v, line:7:1, endln:19:10 + \_module_inst: work@oh_aoi311 (work@oh_aoi311), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi311.v, line:7:1, endln:19:10 |vpiName:a2 |vpiFullName:work@oh_aoi311.a2 |vpiNet: \_logic_net: (work@oh_aoi311.b0), line:12:21, endln:12:23 |vpiParent: - \_module: work@oh_aoi311 (work@oh_aoi311), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi311.v, line:7:1, endln:19:10 + \_module_inst: work@oh_aoi311 (work@oh_aoi311), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi311.v, line:7:1, endln:19:10 |vpiName:b0 |vpiFullName:work@oh_aoi311.b0 |vpiNet: \_logic_net: (work@oh_aoi311.c0), line:13:21, endln:13:23 |vpiParent: - \_module: work@oh_aoi311 (work@oh_aoi311), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi311.v, line:7:1, endln:19:10 + \_module_inst: work@oh_aoi311 (work@oh_aoi311), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi311.v, line:7:1, endln:19:10 |vpiName:c0 |vpiFullName:work@oh_aoi311.c0 |vpiNet: \_logic_net: (work@oh_aoi311.z), line:14:21, endln:14:22 |vpiParent: - \_module: work@oh_aoi311 (work@oh_aoi311), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi311.v, line:7:1, endln:19:10 + \_module_inst: work@oh_aoi311 (work@oh_aoi311), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi311.v, line:7:1, endln:19:10 |vpiName:z |vpiFullName:work@oh_aoi311.z |vpiPort: \_port: (a0), line:9:21, endln:9:23 |vpiParent: - \_module: work@oh_aoi311 (work@oh_aoi311), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi311.v, line:7:1, endln:19:10 + \_module_inst: work@oh_aoi311 (work@oh_aoi311), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi311.v, line:7:1, endln:19:10 |vpiName:a0 |vpiDirection:1 |vpiLowConn: @@ -9462,7 +9462,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (a1), line:10:21, endln:10:23 |vpiParent: - \_module: work@oh_aoi311 (work@oh_aoi311), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi311.v, line:7:1, endln:19:10 + \_module_inst: work@oh_aoi311 (work@oh_aoi311), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi311.v, line:7:1, endln:19:10 |vpiName:a1 |vpiDirection:1 |vpiLowConn: @@ -9502,7 +9502,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (a2), line:11:21, endln:11:23 |vpiParent: - \_module: work@oh_aoi311 (work@oh_aoi311), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi311.v, line:7:1, endln:19:10 + \_module_inst: work@oh_aoi311 (work@oh_aoi311), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi311.v, line:7:1, endln:19:10 |vpiName:a2 |vpiDirection:1 |vpiLowConn: @@ -9542,7 +9542,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (b0), line:12:21, endln:12:23 |vpiParent: - \_module: work@oh_aoi311 (work@oh_aoi311), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi311.v, line:7:1, endln:19:10 + \_module_inst: work@oh_aoi311 (work@oh_aoi311), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi311.v, line:7:1, endln:19:10 |vpiName:b0 |vpiDirection:1 |vpiLowConn: @@ -9582,7 +9582,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (c0), line:13:21, endln:13:23 |vpiParent: - \_module: work@oh_aoi311 (work@oh_aoi311), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi311.v, line:7:1, endln:19:10 + \_module_inst: work@oh_aoi311 (work@oh_aoi311), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi311.v, line:7:1, endln:19:10 |vpiName:c0 |vpiDirection:1 |vpiLowConn: @@ -9622,7 +9622,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (z), line:14:21, endln:14:22 |vpiParent: - \_module: work@oh_aoi311 (work@oh_aoi311), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi311.v, line:7:1, endln:19:10 + \_module_inst: work@oh_aoi311 (work@oh_aoi311), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi311.v, line:7:1, endln:19:10 |vpiName:z |vpiDirection:2 |vpiLowConn: @@ -9662,7 +9662,7 @@ design: (work@oh_fifo_async) |vpiContAssign: \_cont_assign: , line:17:11, endln:17:42 |vpiParent: - \_module: work@oh_aoi311 (work@oh_aoi311), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi311.v, line:7:1, endln:19:10 + \_module_inst: work@oh_aoi311 (work@oh_aoi311), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi311.v, line:7:1, endln:19:10 |vpiRhs: \_operation: , line:17:15, endln:17:42 |vpiParent: @@ -9725,14 +9725,14 @@ design: (work@oh_fifo_async) |vpiName:z |vpiFullName:work@oh_aoi311.z |uhdmallModules: -\_module: work@oh_aoi32 (work@oh_aoi32), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi32.v, line:7:1, endln:19:10 +\_module_inst: work@oh_aoi32 (work@oh_aoi32), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi32.v, line:7:1, endln:19:10 |vpiParent: \_design: (work@oh_fifo_async) |vpiFullName:work@oh_aoi32 |vpiParameter: \_parameter: (work@oh_aoi32.DW), line:7:29, endln:7:31 |vpiParent: - \_module: work@oh_aoi32 (work@oh_aoi32), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi32.v, line:7:1, endln:19:10 + \_module_inst: work@oh_aoi32 (work@oh_aoi32), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi32.v, line:7:1, endln:19:10 |UINT:1 |vpiTypespec: \_int_typespec: @@ -9741,7 +9741,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:7:29, endln:7:35 |vpiParent: - \_module: work@oh_aoi32 (work@oh_aoi32), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi32.v, line:7:1, endln:19:10 + \_module_inst: work@oh_aoi32 (work@oh_aoi32), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi32.v, line:7:1, endln:19:10 |vpiRhs: \_constant: , line:7:34, endln:7:35 |vpiDecompile:1 @@ -9757,43 +9757,43 @@ design: (work@oh_fifo_async) |vpiNet: \_logic_net: (work@oh_aoi32.a0), line:9:21, endln:9:23 |vpiParent: - \_module: work@oh_aoi32 (work@oh_aoi32), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi32.v, line:7:1, endln:19:10 + \_module_inst: work@oh_aoi32 (work@oh_aoi32), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi32.v, line:7:1, endln:19:10 |vpiName:a0 |vpiFullName:work@oh_aoi32.a0 |vpiNet: \_logic_net: (work@oh_aoi32.a1), line:10:21, endln:10:23 |vpiParent: - \_module: work@oh_aoi32 (work@oh_aoi32), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi32.v, line:7:1, endln:19:10 + \_module_inst: work@oh_aoi32 (work@oh_aoi32), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi32.v, line:7:1, endln:19:10 |vpiName:a1 |vpiFullName:work@oh_aoi32.a1 |vpiNet: \_logic_net: (work@oh_aoi32.a2), line:11:21, endln:11:23 |vpiParent: - \_module: work@oh_aoi32 (work@oh_aoi32), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi32.v, line:7:1, endln:19:10 + \_module_inst: work@oh_aoi32 (work@oh_aoi32), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi32.v, line:7:1, endln:19:10 |vpiName:a2 |vpiFullName:work@oh_aoi32.a2 |vpiNet: \_logic_net: (work@oh_aoi32.b0), line:12:21, endln:12:23 |vpiParent: - \_module: work@oh_aoi32 (work@oh_aoi32), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi32.v, line:7:1, endln:19:10 + \_module_inst: work@oh_aoi32 (work@oh_aoi32), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi32.v, line:7:1, endln:19:10 |vpiName:b0 |vpiFullName:work@oh_aoi32.b0 |vpiNet: \_logic_net: (work@oh_aoi32.b1), line:13:21, endln:13:23 |vpiParent: - \_module: work@oh_aoi32 (work@oh_aoi32), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi32.v, line:7:1, endln:19:10 + \_module_inst: work@oh_aoi32 (work@oh_aoi32), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi32.v, line:7:1, endln:19:10 |vpiName:b1 |vpiFullName:work@oh_aoi32.b1 |vpiNet: \_logic_net: (work@oh_aoi32.z), line:14:21, endln:14:22 |vpiParent: - \_module: work@oh_aoi32 (work@oh_aoi32), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi32.v, line:7:1, endln:19:10 + \_module_inst: work@oh_aoi32 (work@oh_aoi32), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi32.v, line:7:1, endln:19:10 |vpiName:z |vpiFullName:work@oh_aoi32.z |vpiPort: \_port: (a0), line:9:21, endln:9:23 |vpiParent: - \_module: work@oh_aoi32 (work@oh_aoi32), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi32.v, line:7:1, endln:19:10 + \_module_inst: work@oh_aoi32 (work@oh_aoi32), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi32.v, line:7:1, endln:19:10 |vpiName:a0 |vpiDirection:1 |vpiLowConn: @@ -9833,7 +9833,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (a1), line:10:21, endln:10:23 |vpiParent: - \_module: work@oh_aoi32 (work@oh_aoi32), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi32.v, line:7:1, endln:19:10 + \_module_inst: work@oh_aoi32 (work@oh_aoi32), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi32.v, line:7:1, endln:19:10 |vpiName:a1 |vpiDirection:1 |vpiLowConn: @@ -9873,7 +9873,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (a2), line:11:21, endln:11:23 |vpiParent: - \_module: work@oh_aoi32 (work@oh_aoi32), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi32.v, line:7:1, endln:19:10 + \_module_inst: work@oh_aoi32 (work@oh_aoi32), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi32.v, line:7:1, endln:19:10 |vpiName:a2 |vpiDirection:1 |vpiLowConn: @@ -9913,7 +9913,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (b0), line:12:21, endln:12:23 |vpiParent: - \_module: work@oh_aoi32 (work@oh_aoi32), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi32.v, line:7:1, endln:19:10 + \_module_inst: work@oh_aoi32 (work@oh_aoi32), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi32.v, line:7:1, endln:19:10 |vpiName:b0 |vpiDirection:1 |vpiLowConn: @@ -9953,7 +9953,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (b1), line:13:21, endln:13:23 |vpiParent: - \_module: work@oh_aoi32 (work@oh_aoi32), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi32.v, line:7:1, endln:19:10 + \_module_inst: work@oh_aoi32 (work@oh_aoi32), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi32.v, line:7:1, endln:19:10 |vpiName:b1 |vpiDirection:1 |vpiLowConn: @@ -9993,7 +9993,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (z), line:14:21, endln:14:22 |vpiParent: - \_module: work@oh_aoi32 (work@oh_aoi32), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi32.v, line:7:1, endln:19:10 + \_module_inst: work@oh_aoi32 (work@oh_aoi32), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi32.v, line:7:1, endln:19:10 |vpiName:z |vpiDirection:2 |vpiLowConn: @@ -10033,7 +10033,7 @@ design: (work@oh_fifo_async) |vpiContAssign: \_cont_assign: , line:17:11, endln:17:44 |vpiParent: - \_module: work@oh_aoi32 (work@oh_aoi32), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi32.v, line:7:1, endln:19:10 + \_module_inst: work@oh_aoi32 (work@oh_aoi32), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi32.v, line:7:1, endln:19:10 |vpiRhs: \_operation: , line:17:15, endln:17:44 |vpiParent: @@ -10096,14 +10096,14 @@ design: (work@oh_fifo_async) |vpiName:z |vpiFullName:work@oh_aoi32.z |uhdmallModules: -\_module: work@oh_aoi33 (work@oh_aoi33), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi33.v, line:7:1, endln:20:10 +\_module_inst: work@oh_aoi33 (work@oh_aoi33), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi33.v, line:7:1, endln:20:10 |vpiParent: \_design: (work@oh_fifo_async) |vpiFullName:work@oh_aoi33 |vpiParameter: \_parameter: (work@oh_aoi33.DW), line:7:29, endln:7:31 |vpiParent: - \_module: work@oh_aoi33 (work@oh_aoi33), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi33.v, line:7:1, endln:20:10 + \_module_inst: work@oh_aoi33 (work@oh_aoi33), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi33.v, line:7:1, endln:20:10 |UINT:1 |vpiTypespec: \_int_typespec: @@ -10112,7 +10112,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:7:29, endln:7:35 |vpiParent: - \_module: work@oh_aoi33 (work@oh_aoi33), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi33.v, line:7:1, endln:20:10 + \_module_inst: work@oh_aoi33 (work@oh_aoi33), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi33.v, line:7:1, endln:20:10 |vpiRhs: \_constant: , line:7:34, endln:7:35 |vpiDecompile:1 @@ -10128,49 +10128,49 @@ design: (work@oh_fifo_async) |vpiNet: \_logic_net: (work@oh_aoi33.a0), line:9:21, endln:9:23 |vpiParent: - \_module: work@oh_aoi33 (work@oh_aoi33), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi33.v, line:7:1, endln:20:10 + \_module_inst: work@oh_aoi33 (work@oh_aoi33), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi33.v, line:7:1, endln:20:10 |vpiName:a0 |vpiFullName:work@oh_aoi33.a0 |vpiNet: \_logic_net: (work@oh_aoi33.a1), line:10:21, endln:10:23 |vpiParent: - \_module: work@oh_aoi33 (work@oh_aoi33), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi33.v, line:7:1, endln:20:10 + \_module_inst: work@oh_aoi33 (work@oh_aoi33), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi33.v, line:7:1, endln:20:10 |vpiName:a1 |vpiFullName:work@oh_aoi33.a1 |vpiNet: \_logic_net: (work@oh_aoi33.a2), line:11:21, endln:11:23 |vpiParent: - \_module: work@oh_aoi33 (work@oh_aoi33), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi33.v, line:7:1, endln:20:10 + \_module_inst: work@oh_aoi33 (work@oh_aoi33), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi33.v, line:7:1, endln:20:10 |vpiName:a2 |vpiFullName:work@oh_aoi33.a2 |vpiNet: \_logic_net: (work@oh_aoi33.b0), line:12:21, endln:12:23 |vpiParent: - \_module: work@oh_aoi33 (work@oh_aoi33), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi33.v, line:7:1, endln:20:10 + \_module_inst: work@oh_aoi33 (work@oh_aoi33), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi33.v, line:7:1, endln:20:10 |vpiName:b0 |vpiFullName:work@oh_aoi33.b0 |vpiNet: \_logic_net: (work@oh_aoi33.b1), line:13:21, endln:13:23 |vpiParent: - \_module: work@oh_aoi33 (work@oh_aoi33), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi33.v, line:7:1, endln:20:10 + \_module_inst: work@oh_aoi33 (work@oh_aoi33), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi33.v, line:7:1, endln:20:10 |vpiName:b1 |vpiFullName:work@oh_aoi33.b1 |vpiNet: \_logic_net: (work@oh_aoi33.b2), line:14:21, endln:14:23 |vpiParent: - \_module: work@oh_aoi33 (work@oh_aoi33), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi33.v, line:7:1, endln:20:10 + \_module_inst: work@oh_aoi33 (work@oh_aoi33), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi33.v, line:7:1, endln:20:10 |vpiName:b2 |vpiFullName:work@oh_aoi33.b2 |vpiNet: \_logic_net: (work@oh_aoi33.z), line:15:21, endln:15:22 |vpiParent: - \_module: work@oh_aoi33 (work@oh_aoi33), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi33.v, line:7:1, endln:20:10 + \_module_inst: work@oh_aoi33 (work@oh_aoi33), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi33.v, line:7:1, endln:20:10 |vpiName:z |vpiFullName:work@oh_aoi33.z |vpiPort: \_port: (a0), line:9:21, endln:9:23 |vpiParent: - \_module: work@oh_aoi33 (work@oh_aoi33), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi33.v, line:7:1, endln:20:10 + \_module_inst: work@oh_aoi33 (work@oh_aoi33), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi33.v, line:7:1, endln:20:10 |vpiName:a0 |vpiDirection:1 |vpiLowConn: @@ -10210,7 +10210,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (a1), line:10:21, endln:10:23 |vpiParent: - \_module: work@oh_aoi33 (work@oh_aoi33), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi33.v, line:7:1, endln:20:10 + \_module_inst: work@oh_aoi33 (work@oh_aoi33), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi33.v, line:7:1, endln:20:10 |vpiName:a1 |vpiDirection:1 |vpiLowConn: @@ -10250,7 +10250,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (a2), line:11:21, endln:11:23 |vpiParent: - \_module: work@oh_aoi33 (work@oh_aoi33), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi33.v, line:7:1, endln:20:10 + \_module_inst: work@oh_aoi33 (work@oh_aoi33), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi33.v, line:7:1, endln:20:10 |vpiName:a2 |vpiDirection:1 |vpiLowConn: @@ -10290,7 +10290,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (b0), line:12:21, endln:12:23 |vpiParent: - \_module: work@oh_aoi33 (work@oh_aoi33), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi33.v, line:7:1, endln:20:10 + \_module_inst: work@oh_aoi33 (work@oh_aoi33), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi33.v, line:7:1, endln:20:10 |vpiName:b0 |vpiDirection:1 |vpiLowConn: @@ -10330,7 +10330,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (b1), line:13:21, endln:13:23 |vpiParent: - \_module: work@oh_aoi33 (work@oh_aoi33), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi33.v, line:7:1, endln:20:10 + \_module_inst: work@oh_aoi33 (work@oh_aoi33), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi33.v, line:7:1, endln:20:10 |vpiName:b1 |vpiDirection:1 |vpiLowConn: @@ -10370,7 +10370,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (b2), line:14:21, endln:14:23 |vpiParent: - \_module: work@oh_aoi33 (work@oh_aoi33), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi33.v, line:7:1, endln:20:10 + \_module_inst: work@oh_aoi33 (work@oh_aoi33), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi33.v, line:7:1, endln:20:10 |vpiName:b2 |vpiDirection:1 |vpiLowConn: @@ -10410,7 +10410,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (z), line:15:21, endln:15:22 |vpiParent: - \_module: work@oh_aoi33 (work@oh_aoi33), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi33.v, line:7:1, endln:20:10 + \_module_inst: work@oh_aoi33 (work@oh_aoi33), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi33.v, line:7:1, endln:20:10 |vpiName:z |vpiDirection:2 |vpiLowConn: @@ -10450,7 +10450,7 @@ design: (work@oh_fifo_async) |vpiContAssign: \_cont_assign: , line:18:11, endln:18:49 |vpiParent: - \_module: work@oh_aoi33 (work@oh_aoi33), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi33.v, line:7:1, endln:20:10 + \_module_inst: work@oh_aoi33 (work@oh_aoi33), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi33.v, line:7:1, endln:20:10 |vpiRhs: \_operation: , line:18:15, endln:18:49 |vpiParent: @@ -10524,14 +10524,14 @@ design: (work@oh_fifo_async) |vpiName:z |vpiFullName:work@oh_aoi33.z |uhdmallModules: -\_module: work@oh_arbiter (work@oh_arbiter), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_arbiter.v, line:8:1, endln:33:10 +\_module_inst: work@oh_arbiter (work@oh_arbiter), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_arbiter.v, line:8:1, endln:33:10 |vpiParent: \_design: (work@oh_fifo_async) |vpiFullName:work@oh_arbiter |vpiParameter: \_parameter: (work@oh_arbiter.N), line:9:16, endln:9:17 |vpiParent: - \_module: work@oh_arbiter (work@oh_arbiter), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_arbiter.v, line:8:1, endln:33:10 + \_module_inst: work@oh_arbiter (work@oh_arbiter), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_arbiter.v, line:8:1, endln:33:10 |UINT:1 |vpiTypespec: \_int_typespec: @@ -10540,7 +10540,7 @@ design: (work@oh_fifo_async) |vpiParameter: \_parameter: (work@oh_arbiter.TYPE), line:10:16, endln:10:20 |vpiParent: - \_module: work@oh_arbiter (work@oh_arbiter), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_arbiter.v, line:8:1, endln:33:10 + \_module_inst: work@oh_arbiter (work@oh_arbiter), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_arbiter.v, line:8:1, endln:33:10 |STRING:FIXED |vpiTypespec: \_string_typespec: @@ -10549,7 +10549,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:9:16, endln:9:24 |vpiParent: - \_module: work@oh_arbiter (work@oh_arbiter), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_arbiter.v, line:8:1, endln:33:10 + \_module_inst: work@oh_arbiter (work@oh_arbiter), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_arbiter.v, line:8:1, endln:33:10 |vpiRhs: \_constant: , line:9:23, endln:9:24 |vpiDecompile:1 @@ -10563,7 +10563,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:10:16, endln:10:30 |vpiParent: - \_module: work@oh_arbiter (work@oh_arbiter), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_arbiter.v, line:8:1, endln:33:10 + \_module_inst: work@oh_arbiter (work@oh_arbiter), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_arbiter.v, line:8:1, endln:33:10 |vpiRhs: \_constant: , line:10:23, endln:10:30 |vpiDecompile:FIXED @@ -10579,26 +10579,26 @@ design: (work@oh_fifo_async) |vpiNet: \_logic_net: (work@oh_arbiter.requests), line:13:20, endln:13:28 |vpiParent: - \_module: work@oh_arbiter (work@oh_arbiter), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_arbiter.v, line:8:1, endln:33:10 + \_module_inst: work@oh_arbiter (work@oh_arbiter), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_arbiter.v, line:8:1, endln:33:10 |vpiName:requests |vpiFullName:work@oh_arbiter.requests |vpiNet: \_logic_net: (work@oh_arbiter.grants), line:14:20, endln:14:26 |vpiParent: - \_module: work@oh_arbiter (work@oh_arbiter), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_arbiter.v, line:8:1, endln:33:10 + \_module_inst: work@oh_arbiter (work@oh_arbiter), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_arbiter.v, line:8:1, endln:33:10 |vpiName:grants |vpiFullName:work@oh_arbiter.grants |vpiNet: \_logic_net: (work@oh_arbiter.waitmask), line:17:19, endln:17:27 |vpiParent: - \_module: work@oh_arbiter (work@oh_arbiter), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_arbiter.v, line:8:1, endln:33:10 + \_module_inst: work@oh_arbiter (work@oh_arbiter), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_arbiter.v, line:8:1, endln:33:10 |vpiName:waitmask |vpiFullName:work@oh_arbiter.waitmask |vpiNetType:1 |vpiPort: \_port: (requests), line:13:20, endln:13:28 |vpiParent: - \_module: work@oh_arbiter (work@oh_arbiter), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_arbiter.v, line:8:1, endln:33:10 + \_module_inst: work@oh_arbiter (work@oh_arbiter), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_arbiter.v, line:8:1, endln:33:10 |vpiName:requests |vpiDirection:1 |vpiLowConn: @@ -10638,7 +10638,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (grants), line:14:20, endln:14:26 |vpiParent: - \_module: work@oh_arbiter (work@oh_arbiter), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_arbiter.v, line:8:1, endln:33:10 + \_module_inst: work@oh_arbiter (work@oh_arbiter), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_arbiter.v, line:8:1, endln:33:10 |vpiName:grants |vpiDirection:2 |vpiLowConn: @@ -10678,7 +10678,7 @@ design: (work@oh_fifo_async) |vpiContAssign: \_cont_assign: , line:31:11, endln:31:61 |vpiParent: - \_module: work@oh_arbiter (work@oh_arbiter), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_arbiter.v, line:8:1, endln:33:10 + \_module_inst: work@oh_arbiter (work@oh_arbiter), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_arbiter.v, line:8:1, endln:33:10 |vpiRhs: \_operation: , line:31:27, endln:31:61 |vpiParent: @@ -10786,14 +10786,14 @@ design: (work@oh_fifo_async) |UINT:0 |vpiConstType:9 |uhdmallModules: -\_module: work@oh_bin2gray (work@oh_bin2gray), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_bin2gray.v, line:8:1, endln:31:10 +\_module_inst: work@oh_bin2gray (work@oh_bin2gray), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_bin2gray.v, line:8:1, endln:31:10 |vpiParent: \_design: (work@oh_fifo_async) |vpiFullName:work@oh_bin2gray |vpiParameter: \_parameter: (work@oh_bin2gray.N), line:9:15, endln:9:16 |vpiParent: - \_module: work@oh_bin2gray (work@oh_bin2gray), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_bin2gray.v, line:8:1, endln:31:10 + \_module_inst: work@oh_bin2gray (work@oh_bin2gray), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_bin2gray.v, line:8:1, endln:31:10 |UINT:32 |vpiTypespec: \_int_typespec: @@ -10802,7 +10802,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:9:15, endln:9:21 |vpiParent: - \_module: work@oh_bin2gray (work@oh_bin2gray), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_bin2gray.v, line:8:1, endln:31:10 + \_module_inst: work@oh_bin2gray (work@oh_bin2gray), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_bin2gray.v, line:8:1, endln:31:10 |vpiRhs: \_constant: , line:9:19, endln:9:21 |vpiDecompile:32 @@ -10818,39 +10818,39 @@ design: (work@oh_fifo_async) |vpiNet: \_logic_net: (work@oh_bin2gray.in), line:12:20, endln:12:22 |vpiParent: - \_module: work@oh_bin2gray (work@oh_bin2gray), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_bin2gray.v, line:8:1, endln:31:10 + \_module_inst: work@oh_bin2gray (work@oh_bin2gray), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_bin2gray.v, line:8:1, endln:31:10 |vpiName:in |vpiFullName:work@oh_bin2gray.in |vpiNet: \_logic_net: (work@oh_bin2gray.out), line:13:20, endln:13:23 |vpiParent: - \_module: work@oh_bin2gray (work@oh_bin2gray), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_bin2gray.v, line:8:1, endln:31:10 + \_module_inst: work@oh_bin2gray (work@oh_bin2gray), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_bin2gray.v, line:8:1, endln:31:10 |vpiName:out |vpiFullName:work@oh_bin2gray.out |vpiNet: \_logic_net: (work@oh_bin2gray.gray), line:16:20, endln:16:24 |vpiParent: - \_module: work@oh_bin2gray (work@oh_bin2gray), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_bin2gray.v, line:8:1, endln:31:10 + \_module_inst: work@oh_bin2gray (work@oh_bin2gray), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_bin2gray.v, line:8:1, endln:31:10 |vpiName:gray |vpiFullName:work@oh_bin2gray.gray |vpiNetType:48 |vpiNet: \_logic_net: (work@oh_bin2gray.bin), line:17:20, endln:17:23 |vpiParent: - \_module: work@oh_bin2gray (work@oh_bin2gray), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_bin2gray.v, line:8:1, endln:31:10 + \_module_inst: work@oh_bin2gray (work@oh_bin2gray), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_bin2gray.v, line:8:1, endln:31:10 |vpiName:bin |vpiFullName:work@oh_bin2gray.bin |vpiNetType:1 |vpiNet: \_logic_net: (work@oh_bin2gray.i), line:19:16, endln:19:17 |vpiParent: - \_module: work@oh_bin2gray (work@oh_bin2gray), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_bin2gray.v, line:8:1, endln:31:10 + \_module_inst: work@oh_bin2gray (work@oh_bin2gray), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_bin2gray.v, line:8:1, endln:31:10 |vpiName:i |vpiFullName:work@oh_bin2gray.i |vpiPort: \_port: (in), line:12:20, endln:12:22 |vpiParent: - \_module: work@oh_bin2gray (work@oh_bin2gray), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_bin2gray.v, line:8:1, endln:31:10 + \_module_inst: work@oh_bin2gray (work@oh_bin2gray), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_bin2gray.v, line:8:1, endln:31:10 |vpiName:in |vpiDirection:1 |vpiLowConn: @@ -10890,7 +10890,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (out), line:13:20, endln:13:23 |vpiParent: - \_module: work@oh_bin2gray (work@oh_bin2gray), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_bin2gray.v, line:8:1, endln:31:10 + \_module_inst: work@oh_bin2gray (work@oh_bin2gray), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_bin2gray.v, line:8:1, endln:31:10 |vpiName:out |vpiDirection:2 |vpiLowConn: @@ -10930,7 +10930,7 @@ design: (work@oh_fifo_async) |vpiProcess: \_always: , line:24:4, endln:29:9 |vpiParent: - \_module: work@oh_bin2gray (work@oh_bin2gray), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_bin2gray.v, line:8:1, endln:31:10 + \_module_inst: work@oh_bin2gray (work@oh_bin2gray), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_bin2gray.v, line:8:1, endln:31:10 |vpiStmt: \_event_control: , line:24:11, endln:24:13 |vpiParent: @@ -11176,7 +11176,7 @@ design: (work@oh_fifo_async) |vpiContAssign: \_cont_assign: , line:21:11, endln:21:34 |vpiParent: - \_module: work@oh_bin2gray (work@oh_bin2gray), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_bin2gray.v, line:8:1, endln:31:10 + \_module_inst: work@oh_bin2gray (work@oh_bin2gray), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_bin2gray.v, line:8:1, endln:31:10 |vpiRhs: \_part_select: , line:21:25, endln:21:34 |vpiParent: @@ -11244,7 +11244,7 @@ design: (work@oh_fifo_async) |vpiContAssign: \_cont_assign: , line:22:11, endln:22:36 |vpiParent: - \_module: work@oh_bin2gray (work@oh_bin2gray), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_bin2gray.v, line:8:1, endln:31:10 + \_module_inst: work@oh_bin2gray (work@oh_bin2gray), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_bin2gray.v, line:8:1, endln:31:10 |vpiRhs: \_part_select: , line:22:25, endln:22:36 |vpiParent: @@ -11310,14 +11310,14 @@ design: (work@oh_fifo_async) |UINT:0 |vpiConstType:9 |uhdmallModules: -\_module: work@oh_bin2onehot (work@oh_bin2onehot), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_bin2onehot.v, line:8:1, endln:21:10 +\_module_inst: work@oh_bin2onehot (work@oh_bin2onehot), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_bin2onehot.v, line:8:1, endln:21:10 |vpiParent: \_design: (work@oh_fifo_async) |vpiFullName:work@oh_bin2onehot |vpiParameter: \_parameter: (work@oh_bin2onehot.N), line:9:16, endln:9:17 |vpiParent: - \_module: work@oh_bin2onehot (work@oh_bin2onehot), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_bin2onehot.v, line:8:1, endln:21:10 + \_module_inst: work@oh_bin2onehot (work@oh_bin2onehot), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_bin2onehot.v, line:8:1, endln:21:10 |UINT:2 |vpiTypespec: \_int_typespec: @@ -11326,13 +11326,13 @@ design: (work@oh_fifo_async) |vpiParameter: \_parameter: (work@oh_bin2onehot.NB), line:10:16, endln:10:18 |vpiParent: - \_module: work@oh_bin2onehot (work@oh_bin2onehot), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_bin2onehot.v, line:8:1, endln:21:10 + \_module_inst: work@oh_bin2onehot (work@oh_bin2onehot), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_bin2onehot.v, line:8:1, endln:21:10 |vpiName:NB |vpiFullName:work@oh_bin2onehot.NB |vpiParamAssign: \_param_assign: , line:9:16, endln:9:22 |vpiParent: - \_module: work@oh_bin2onehot (work@oh_bin2onehot), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_bin2onehot.v, line:8:1, endln:21:10 + \_module_inst: work@oh_bin2onehot (work@oh_bin2onehot), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_bin2onehot.v, line:8:1, endln:21:10 |vpiRhs: \_constant: , line:9:21, endln:9:22 |vpiDecompile:2 @@ -11346,7 +11346,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:10:16, endln:10:30 |vpiParent: - \_module: work@oh_bin2onehot (work@oh_bin2onehot), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_bin2onehot.v, line:8:1, endln:21:10 + \_module_inst: work@oh_bin2onehot (work@oh_bin2onehot), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_bin2onehot.v, line:8:1, endln:21:10 |vpiRhs: \_sys_func_call: ($clog2), line:10:21, endln:10:30 |vpiArgument: @@ -11362,19 +11362,19 @@ design: (work@oh_fifo_async) |vpiNet: \_logic_net: (work@oh_bin2onehot.in), line:13:20, endln:13:22 |vpiParent: - \_module: work@oh_bin2onehot (work@oh_bin2onehot), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_bin2onehot.v, line:8:1, endln:21:10 + \_module_inst: work@oh_bin2onehot (work@oh_bin2onehot), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_bin2onehot.v, line:8:1, endln:21:10 |vpiName:in |vpiFullName:work@oh_bin2onehot.in |vpiNet: \_logic_net: (work@oh_bin2onehot.out), line:14:20, endln:14:23 |vpiParent: - \_module: work@oh_bin2onehot (work@oh_bin2onehot), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_bin2onehot.v, line:8:1, endln:21:10 + \_module_inst: work@oh_bin2onehot (work@oh_bin2onehot), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_bin2onehot.v, line:8:1, endln:21:10 |vpiName:out |vpiFullName:work@oh_bin2onehot.out |vpiPort: \_port: (in), line:13:20, endln:13:22 |vpiParent: - \_module: work@oh_bin2onehot (work@oh_bin2onehot), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_bin2onehot.v, line:8:1, endln:21:10 + \_module_inst: work@oh_bin2onehot (work@oh_bin2onehot), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_bin2onehot.v, line:8:1, endln:21:10 |vpiName:in |vpiDirection:1 |vpiLowConn: @@ -11414,7 +11414,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (out), line:14:20, endln:14:23 |vpiParent: - \_module: work@oh_bin2onehot (work@oh_bin2onehot), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_bin2onehot.v, line:8:1, endln:21:10 + \_module_inst: work@oh_bin2onehot (work@oh_bin2onehot), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_bin2onehot.v, line:8:1, endln:21:10 |vpiName:out |vpiDirection:2 |vpiLowConn: @@ -11452,14 +11452,14 @@ design: (work@oh_fifo_async) |UINT:0 |vpiConstType:9 |uhdmallModules: -\_module: work@oh_bitreverse (work@oh_bitreverse), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_bitreverse.v, line:8:1, endln:23:10 +\_module_inst: work@oh_bitreverse (work@oh_bitreverse), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_bitreverse.v, line:8:1, endln:23:10 |vpiParent: \_design: (work@oh_fifo_async) |vpiFullName:work@oh_bitreverse |vpiParameter: \_parameter: (work@oh_bitreverse.N), line:9:15, endln:9:16 |vpiParent: - \_module: work@oh_bitreverse (work@oh_bitreverse), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_bitreverse.v, line:8:1, endln:23:10 + \_module_inst: work@oh_bitreverse (work@oh_bitreverse), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_bitreverse.v, line:8:1, endln:23:10 |UINT:32 |vpiTypespec: \_int_typespec: @@ -11468,7 +11468,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:9:15, endln:9:21 |vpiParent: - \_module: work@oh_bitreverse (work@oh_bitreverse), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_bitreverse.v, line:8:1, endln:23:10 + \_module_inst: work@oh_bitreverse (work@oh_bitreverse), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_bitreverse.v, line:8:1, endln:23:10 |vpiRhs: \_constant: , line:9:19, endln:9:21 |vpiDecompile:32 @@ -11484,19 +11484,19 @@ design: (work@oh_fifo_async) |vpiNet: \_logic_net: (work@oh_bitreverse.in), line:12:20, endln:12:22 |vpiParent: - \_module: work@oh_bitreverse (work@oh_bitreverse), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_bitreverse.v, line:8:1, endln:23:10 + \_module_inst: work@oh_bitreverse (work@oh_bitreverse), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_bitreverse.v, line:8:1, endln:23:10 |vpiName:in |vpiFullName:work@oh_bitreverse.in |vpiNet: \_logic_net: (work@oh_bitreverse.out), line:13:20, endln:13:23 |vpiParent: - \_module: work@oh_bitreverse (work@oh_bitreverse), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_bitreverse.v, line:8:1, endln:23:10 + \_module_inst: work@oh_bitreverse (work@oh_bitreverse), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_bitreverse.v, line:8:1, endln:23:10 |vpiName:out |vpiFullName:work@oh_bitreverse.out |vpiPort: \_port: (in), line:12:20, endln:12:22 |vpiParent: - \_module: work@oh_bitreverse (work@oh_bitreverse), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_bitreverse.v, line:8:1, endln:23:10 + \_module_inst: work@oh_bitreverse (work@oh_bitreverse), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_bitreverse.v, line:8:1, endln:23:10 |vpiName:in |vpiDirection:1 |vpiLowConn: @@ -11536,7 +11536,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (out), line:13:20, endln:13:23 |vpiParent: - \_module: work@oh_bitreverse (work@oh_bitreverse), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_bitreverse.v, line:8:1, endln:23:10 + \_module_inst: work@oh_bitreverse (work@oh_bitreverse), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_bitreverse.v, line:8:1, endln:23:10 |vpiName:out |vpiDirection:2 |vpiLowConn: @@ -11574,14 +11574,14 @@ design: (work@oh_fifo_async) |UINT:0 |vpiConstType:9 |uhdmallModules: -\_module: work@oh_buf (work@oh_buf), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_buf.v, line:7:1, endln:15:10 +\_module_inst: work@oh_buf (work@oh_buf), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_buf.v, line:7:1, endln:15:10 |vpiParent: \_design: (work@oh_fifo_async) |vpiFullName:work@oh_buf |vpiParameter: \_parameter: (work@oh_buf.DW), line:7:27, endln:7:29 |vpiParent: - \_module: work@oh_buf (work@oh_buf), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_buf.v, line:7:1, endln:15:10 + \_module_inst: work@oh_buf (work@oh_buf), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_buf.v, line:7:1, endln:15:10 |UINT:1 |vpiTypespec: \_int_typespec: @@ -11590,7 +11590,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:7:27, endln:7:33 |vpiParent: - \_module: work@oh_buf (work@oh_buf), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_buf.v, line:7:1, endln:15:10 + \_module_inst: work@oh_buf (work@oh_buf), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_buf.v, line:7:1, endln:15:10 |vpiRhs: \_constant: , line:7:32, endln:7:33 |vpiDecompile:1 @@ -11606,19 +11606,19 @@ design: (work@oh_fifo_async) |vpiNet: \_logic_net: (work@oh_buf.a), line:9:21, endln:9:22 |vpiParent: - \_module: work@oh_buf (work@oh_buf), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_buf.v, line:7:1, endln:15:10 + \_module_inst: work@oh_buf (work@oh_buf), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_buf.v, line:7:1, endln:15:10 |vpiName:a |vpiFullName:work@oh_buf.a |vpiNet: \_logic_net: (work@oh_buf.z), line:10:21, endln:10:22 |vpiParent: - \_module: work@oh_buf (work@oh_buf), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_buf.v, line:7:1, endln:15:10 + \_module_inst: work@oh_buf (work@oh_buf), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_buf.v, line:7:1, endln:15:10 |vpiName:z |vpiFullName:work@oh_buf.z |vpiPort: \_port: (a), line:9:21, endln:9:22 |vpiParent: - \_module: work@oh_buf (work@oh_buf), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_buf.v, line:7:1, endln:15:10 + \_module_inst: work@oh_buf (work@oh_buf), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_buf.v, line:7:1, endln:15:10 |vpiName:a |vpiDirection:1 |vpiLowConn: @@ -11658,7 +11658,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (z), line:10:21, endln:10:22 |vpiParent: - \_module: work@oh_buf (work@oh_buf), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_buf.v, line:7:1, endln:15:10 + \_module_inst: work@oh_buf (work@oh_buf), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_buf.v, line:7:1, endln:15:10 |vpiName:z |vpiDirection:2 |vpiLowConn: @@ -11698,7 +11698,7 @@ design: (work@oh_fifo_async) |vpiContAssign: \_cont_assign: , line:13:11, endln:13:16 |vpiParent: - \_module: work@oh_buf (work@oh_buf), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_buf.v, line:7:1, endln:15:10 + \_module_inst: work@oh_buf (work@oh_buf), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_buf.v, line:7:1, endln:15:10 |vpiRhs: \_ref_obj: (work@oh_buf.a), line:13:15, endln:13:16 |vpiParent: @@ -11712,14 +11712,14 @@ design: (work@oh_fifo_async) |vpiName:z |vpiFullName:work@oh_buf.z |uhdmallModules: -\_module: work@oh_buffer (work@oh_buffer), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_buffer.v, line:8:1, endln:29:10 +\_module_inst: work@oh_buffer (work@oh_buffer), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_buffer.v, line:8:1, endln:29:10 |vpiParent: \_design: (work@oh_fifo_async) |vpiFullName:work@oh_buffer |vpiParameter: \_parameter: (work@oh_buffer.N), line:9:15, endln:9:16 |vpiParent: - \_module: work@oh_buffer (work@oh_buffer), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_buffer.v, line:8:1, endln:29:10 + \_module_inst: work@oh_buffer (work@oh_buffer), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_buffer.v, line:8:1, endln:29:10 |UINT:1 |vpiTypespec: \_int_typespec: @@ -11728,7 +11728,7 @@ design: (work@oh_fifo_async) |vpiParameter: \_parameter: (work@oh_buffer.SYN), line:10:15, endln:10:18 |vpiParent: - \_module: work@oh_buffer (work@oh_buffer), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_buffer.v, line:8:1, endln:29:10 + \_module_inst: work@oh_buffer (work@oh_buffer), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_buffer.v, line:8:1, endln:29:10 |STRING:TRUE |vpiTypespec: \_string_typespec: @@ -11737,7 +11737,7 @@ design: (work@oh_fifo_async) |vpiParameter: \_parameter: (work@oh_buffer.TYPE), line:11:15, endln:11:19 |vpiParent: - \_module: work@oh_buffer (work@oh_buffer), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_buffer.v, line:8:1, endln:29:10 + \_module_inst: work@oh_buffer (work@oh_buffer), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_buffer.v, line:8:1, endln:29:10 |STRING:DEFAULT |vpiTypespec: \_string_typespec: @@ -11746,7 +11746,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:9:15, endln:9:23 |vpiParent: - \_module: work@oh_buffer (work@oh_buffer), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_buffer.v, line:8:1, endln:29:10 + \_module_inst: work@oh_buffer (work@oh_buffer), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_buffer.v, line:8:1, endln:29:10 |vpiRhs: \_constant: , line:9:22, endln:9:23 |vpiDecompile:1 @@ -11760,7 +11760,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:10:15, endln:10:28 |vpiParent: - \_module: work@oh_buffer (work@oh_buffer), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_buffer.v, line:8:1, endln:29:10 + \_module_inst: work@oh_buffer (work@oh_buffer), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_buffer.v, line:8:1, endln:29:10 |vpiRhs: \_constant: , line:10:22, endln:10:28 |vpiDecompile:TRUE @@ -11774,7 +11774,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:11:15, endln:11:31 |vpiParent: - \_module: work@oh_buffer (work@oh_buffer), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_buffer.v, line:8:1, endln:29:10 + \_module_inst: work@oh_buffer (work@oh_buffer), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_buffer.v, line:8:1, endln:29:10 |vpiRhs: \_constant: , line:11:22, endln:11:31 |vpiDecompile:DEFAULT @@ -11790,19 +11790,19 @@ design: (work@oh_fifo_async) |vpiNet: \_logic_net: (work@oh_buffer.in), line:13:21, endln:13:23 |vpiParent: - \_module: work@oh_buffer (work@oh_buffer), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_buffer.v, line:8:1, endln:29:10 + \_module_inst: work@oh_buffer (work@oh_buffer), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_buffer.v, line:8:1, endln:29:10 |vpiName:in |vpiFullName:work@oh_buffer.in |vpiNet: \_logic_net: (work@oh_buffer.out), line:14:21, endln:14:24 |vpiParent: - \_module: work@oh_buffer (work@oh_buffer), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_buffer.v, line:8:1, endln:29:10 + \_module_inst: work@oh_buffer (work@oh_buffer), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_buffer.v, line:8:1, endln:29:10 |vpiName:out |vpiFullName:work@oh_buffer.out |vpiPort: \_port: (in), line:13:21, endln:13:23 |vpiParent: - \_module: work@oh_buffer (work@oh_buffer), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_buffer.v, line:8:1, endln:29:10 + \_module_inst: work@oh_buffer (work@oh_buffer), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_buffer.v, line:8:1, endln:29:10 |vpiName:in |vpiDirection:1 |vpiLowConn: @@ -11842,7 +11842,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (out), line:14:21, endln:14:24 |vpiParent: - \_module: work@oh_buffer (work@oh_buffer), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_buffer.v, line:8:1, endln:29:10 + \_module_inst: work@oh_buffer (work@oh_buffer), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_buffer.v, line:8:1, endln:29:10 |vpiName:out |vpiDirection:2 |vpiLowConn: @@ -11880,14 +11880,14 @@ design: (work@oh_fifo_async) |UINT:0 |vpiConstType:9 |uhdmallModules: -\_module: work@oh_clockdiv (work@oh_clockdiv), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockdiv.v, line:9:1, endln:167:10 +\_module_inst: work@oh_clockdiv (work@oh_clockdiv), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockdiv.v, line:9:1, endln:167:10 |vpiParent: \_design: (work@oh_fifo_async) |vpiFullName:work@oh_clockdiv |vpiParameter: \_parameter: (work@oh_clockdiv.N), line:10:15, endln:10:16 |vpiParent: - \_module: work@oh_clockdiv (work@oh_clockdiv), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockdiv.v, line:9:1, endln:167:10 + \_module_inst: work@oh_clockdiv (work@oh_clockdiv), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockdiv.v, line:9:1, endln:167:10 |UINT:2 |vpiTypespec: \_int_typespec: @@ -11896,7 +11896,7 @@ design: (work@oh_fifo_async) |vpiParameter: \_parameter: (work@oh_clockdiv.SYN), line:11:15, endln:11:18 |vpiParent: - \_module: work@oh_clockdiv (work@oh_clockdiv), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockdiv.v, line:9:1, endln:167:10 + \_module_inst: work@oh_clockdiv (work@oh_clockdiv), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockdiv.v, line:9:1, endln:167:10 |STRING:TRUE |vpiTypespec: \_string_typespec: @@ -11905,7 +11905,7 @@ design: (work@oh_fifo_async) |vpiParameter: \_parameter: (work@oh_clockdiv.LATCH_TYPE), line:12:15, endln:12:25 |vpiParent: - \_module: work@oh_clockdiv (work@oh_clockdiv), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockdiv.v, line:9:1, endln:167:10 + \_module_inst: work@oh_clockdiv (work@oh_clockdiv), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockdiv.v, line:9:1, endln:167:10 |STRING:DEFAULT |vpiTypespec: \_string_typespec: @@ -11914,7 +11914,7 @@ design: (work@oh_fifo_async) |vpiParameter: \_parameter: (work@oh_clockdiv.CLOCKMUX_TYPE), line:13:15, endln:13:28 |vpiParent: - \_module: work@oh_clockdiv (work@oh_clockdiv), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockdiv.v, line:9:1, endln:167:10 + \_module_inst: work@oh_clockdiv (work@oh_clockdiv), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockdiv.v, line:9:1, endln:167:10 |STRING:DEFAULT |vpiTypespec: \_string_typespec: @@ -11923,7 +11923,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:10:15, endln:10:32 |vpiParent: - \_module: work@oh_clockdiv (work@oh_clockdiv), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockdiv.v, line:9:1, endln:167:10 + \_module_inst: work@oh_clockdiv (work@oh_clockdiv), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockdiv.v, line:9:1, endln:167:10 |vpiRhs: \_constant: , line:10:31, endln:10:32 |vpiDecompile:2 @@ -11937,7 +11937,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:11:15, endln:11:37 |vpiParent: - \_module: work@oh_clockdiv (work@oh_clockdiv), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockdiv.v, line:9:1, endln:167:10 + \_module_inst: work@oh_clockdiv (work@oh_clockdiv), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockdiv.v, line:9:1, endln:167:10 |vpiRhs: \_constant: , line:11:31, endln:11:37 |vpiDecompile:TRUE @@ -11951,7 +11951,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:12:15, endln:12:40 |vpiParent: - \_module: work@oh_clockdiv (work@oh_clockdiv), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockdiv.v, line:9:1, endln:167:10 + \_module_inst: work@oh_clockdiv (work@oh_clockdiv), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockdiv.v, line:9:1, endln:167:10 |vpiRhs: \_constant: , line:12:31, endln:12:40 |vpiDecompile:DEFAULT @@ -11965,7 +11965,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:13:15, endln:13:40 |vpiParent: - \_module: work@oh_clockdiv (work@oh_clockdiv), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockdiv.v, line:9:1, endln:167:10 + \_module_inst: work@oh_clockdiv (work@oh_clockdiv), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockdiv.v, line:9:1, endln:167:10 |vpiRhs: \_constant: , line:13:31, endln:13:40 |vpiDecompile:DEFAULT @@ -11981,161 +11981,161 @@ design: (work@oh_fifo_async) |vpiNet: \_logic_net: (work@oh_clockdiv.clk), line:17:13, endln:17:16 |vpiParent: - \_module: work@oh_clockdiv (work@oh_clockdiv), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockdiv.v, line:9:1, endln:167:10 + \_module_inst: work@oh_clockdiv (work@oh_clockdiv), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockdiv.v, line:9:1, endln:167:10 |vpiName:clk |vpiFullName:work@oh_clockdiv.clk |vpiNet: \_logic_net: (work@oh_clockdiv.nreset), line:18:13, endln:18:19 |vpiParent: - \_module: work@oh_clockdiv (work@oh_clockdiv), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockdiv.v, line:9:1, endln:167:10 + \_module_inst: work@oh_clockdiv (work@oh_clockdiv), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockdiv.v, line:9:1, endln:167:10 |vpiName:nreset |vpiFullName:work@oh_clockdiv.nreset |vpiNet: \_logic_net: (work@oh_clockdiv.clkchange), line:19:13, endln:19:22 |vpiParent: - \_module: work@oh_clockdiv (work@oh_clockdiv), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockdiv.v, line:9:1, endln:167:10 + \_module_inst: work@oh_clockdiv (work@oh_clockdiv), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockdiv.v, line:9:1, endln:167:10 |vpiName:clkchange |vpiFullName:work@oh_clockdiv.clkchange |vpiNet: \_logic_net: (work@oh_clockdiv.clken), line:20:13, endln:20:18 |vpiParent: - \_module: work@oh_clockdiv (work@oh_clockdiv), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockdiv.v, line:9:1, endln:167:10 + \_module_inst: work@oh_clockdiv (work@oh_clockdiv), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockdiv.v, line:9:1, endln:167:10 |vpiName:clken |vpiFullName:work@oh_clockdiv.clken |vpiNet: \_logic_net: (work@oh_clockdiv.clkdiv), line:21:18, endln:21:24 |vpiParent: - \_module: work@oh_clockdiv (work@oh_clockdiv), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockdiv.v, line:9:1, endln:167:10 + \_module_inst: work@oh_clockdiv (work@oh_clockdiv), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockdiv.v, line:9:1, endln:167:10 |vpiName:clkdiv |vpiFullName:work@oh_clockdiv.clkdiv |vpiNet: \_logic_net: (work@oh_clockdiv.clkphase0), line:22:18, endln:22:27 |vpiParent: - \_module: work@oh_clockdiv (work@oh_clockdiv), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockdiv.v, line:9:1, endln:167:10 + \_module_inst: work@oh_clockdiv (work@oh_clockdiv), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockdiv.v, line:9:1, endln:167:10 |vpiName:clkphase0 |vpiFullName:work@oh_clockdiv.clkphase0 |vpiNet: \_logic_net: (work@oh_clockdiv.clkphase1), line:23:18, endln:23:27 |vpiParent: - \_module: work@oh_clockdiv (work@oh_clockdiv), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockdiv.v, line:9:1, endln:167:10 + \_module_inst: work@oh_clockdiv (work@oh_clockdiv), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockdiv.v, line:9:1, endln:167:10 |vpiName:clkphase1 |vpiFullName:work@oh_clockdiv.clkphase1 |vpiNet: \_logic_net: (work@oh_clockdiv.clkout0), line:25:14, endln:25:21 |vpiParent: - \_module: work@oh_clockdiv (work@oh_clockdiv), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockdiv.v, line:9:1, endln:167:10 + \_module_inst: work@oh_clockdiv (work@oh_clockdiv), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockdiv.v, line:9:1, endln:167:10 |vpiName:clkout0 |vpiFullName:work@oh_clockdiv.clkout0 |vpiNet: \_logic_net: (work@oh_clockdiv.clkrise0), line:26:14, endln:26:22 |vpiParent: - \_module: work@oh_clockdiv (work@oh_clockdiv), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockdiv.v, line:9:1, endln:167:10 + \_module_inst: work@oh_clockdiv (work@oh_clockdiv), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockdiv.v, line:9:1, endln:167:10 |vpiName:clkrise0 |vpiFullName:work@oh_clockdiv.clkrise0 |vpiNet: \_logic_net: (work@oh_clockdiv.clkfall0), line:27:14, endln:27:22 |vpiParent: - \_module: work@oh_clockdiv (work@oh_clockdiv), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockdiv.v, line:9:1, endln:167:10 + \_module_inst: work@oh_clockdiv (work@oh_clockdiv), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockdiv.v, line:9:1, endln:167:10 |vpiName:clkfall0 |vpiFullName:work@oh_clockdiv.clkfall0 |vpiNet: \_logic_net: (work@oh_clockdiv.clkout1), line:28:14, endln:28:21 |vpiParent: - \_module: work@oh_clockdiv (work@oh_clockdiv), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockdiv.v, line:9:1, endln:167:10 + \_module_inst: work@oh_clockdiv (work@oh_clockdiv), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockdiv.v, line:9:1, endln:167:10 |vpiName:clkout1 |vpiFullName:work@oh_clockdiv.clkout1 |vpiNet: \_logic_net: (work@oh_clockdiv.clkrise1), line:29:14, endln:29:22 |vpiParent: - \_module: work@oh_clockdiv (work@oh_clockdiv), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockdiv.v, line:9:1, endln:167:10 + \_module_inst: work@oh_clockdiv (work@oh_clockdiv), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockdiv.v, line:9:1, endln:167:10 |vpiName:clkrise1 |vpiFullName:work@oh_clockdiv.clkrise1 |vpiNet: \_logic_net: (work@oh_clockdiv.clkfall1), line:30:14, endln:30:22 |vpiParent: - \_module: work@oh_clockdiv (work@oh_clockdiv), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockdiv.v, line:9:1, endln:167:10 + \_module_inst: work@oh_clockdiv (work@oh_clockdiv), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockdiv.v, line:9:1, endln:167:10 |vpiName:clkfall1 |vpiFullName:work@oh_clockdiv.clkfall1 |vpiNet: \_logic_net: (work@oh_clockdiv.clkstable), line:31:14, endln:31:23 |vpiParent: - \_module: work@oh_clockdiv (work@oh_clockdiv), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockdiv.v, line:9:1, endln:167:10 + \_module_inst: work@oh_clockdiv (work@oh_clockdiv), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockdiv.v, line:9:1, endln:167:10 |vpiName:clkstable |vpiFullName:work@oh_clockdiv.clkstable |vpiNet: \_logic_net: (work@oh_clockdiv.counter), line:35:14, endln:35:21 |vpiParent: - \_module: work@oh_clockdiv (work@oh_clockdiv), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockdiv.v, line:9:1, endln:167:10 + \_module_inst: work@oh_clockdiv (work@oh_clockdiv), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockdiv.v, line:9:1, endln:167:10 |vpiName:counter |vpiFullName:work@oh_clockdiv.counter |vpiNetType:48 |vpiNet: \_logic_net: (work@oh_clockdiv.clkout0_reg), line:36:14, endln:36:25 |vpiParent: - \_module: work@oh_clockdiv (work@oh_clockdiv), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockdiv.v, line:9:1, endln:167:10 + \_module_inst: work@oh_clockdiv (work@oh_clockdiv), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockdiv.v, line:9:1, endln:167:10 |vpiName:clkout0_reg |vpiFullName:work@oh_clockdiv.clkout0_reg |vpiNetType:48 |vpiNet: \_logic_net: (work@oh_clockdiv.clkout1_reg), line:37:14, endln:37:25 |vpiParent: - \_module: work@oh_clockdiv (work@oh_clockdiv), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockdiv.v, line:9:1, endln:167:10 + \_module_inst: work@oh_clockdiv (work@oh_clockdiv), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockdiv.v, line:9:1, endln:167:10 |vpiName:clkout1_reg |vpiFullName:work@oh_clockdiv.clkout1_reg |vpiNetType:48 |vpiNet: \_logic_net: (work@oh_clockdiv.clkout1_shift), line:38:14, endln:38:27 |vpiParent: - \_module: work@oh_clockdiv (work@oh_clockdiv), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockdiv.v, line:9:1, endln:167:10 + \_module_inst: work@oh_clockdiv (work@oh_clockdiv), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockdiv.v, line:9:1, endln:167:10 |vpiName:clkout1_shift |vpiFullName:work@oh_clockdiv.clkout1_shift |vpiNetType:48 |vpiNet: \_logic_net: (work@oh_clockdiv.period), line:39:14, endln:39:20 |vpiParent: - \_module: work@oh_clockdiv (work@oh_clockdiv), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockdiv.v, line:9:1, endln:167:10 + \_module_inst: work@oh_clockdiv (work@oh_clockdiv), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockdiv.v, line:9:1, endln:167:10 |vpiName:period |vpiFullName:work@oh_clockdiv.period |vpiNetType:48 |vpiNet: \_logic_net: (work@oh_clockdiv.period_match), line:40:14, endln:40:26 |vpiParent: - \_module: work@oh_clockdiv (work@oh_clockdiv), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockdiv.v, line:9:1, endln:167:10 + \_module_inst: work@oh_clockdiv (work@oh_clockdiv), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockdiv.v, line:9:1, endln:167:10 |vpiName:period_match |vpiFullName:work@oh_clockdiv.period_match |vpiNetType:1 |vpiNet: \_logic_net: (work@oh_clockdiv.clk1_sel), line:41:15, endln:41:23 |vpiParent: - \_module: work@oh_clockdiv (work@oh_clockdiv), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockdiv.v, line:9:1, endln:167:10 + \_module_inst: work@oh_clockdiv (work@oh_clockdiv), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockdiv.v, line:9:1, endln:167:10 |vpiName:clk1_sel |vpiFullName:work@oh_clockdiv.clk1_sel |vpiNetType:1 |vpiNet: \_logic_net: (work@oh_clockdiv.clk1_sel_sh), line:42:15, endln:42:26 |vpiParent: - \_module: work@oh_clockdiv (work@oh_clockdiv), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockdiv.v, line:9:1, endln:167:10 + \_module_inst: work@oh_clockdiv (work@oh_clockdiv), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockdiv.v, line:9:1, endln:167:10 |vpiName:clk1_sel_sh |vpiFullName:work@oh_clockdiv.clk1_sel_sh |vpiNetType:1 |vpiNet: \_logic_net: (work@oh_clockdiv.clk0_sel), line:43:15, endln:43:23 |vpiParent: - \_module: work@oh_clockdiv (work@oh_clockdiv), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockdiv.v, line:9:1, endln:167:10 + \_module_inst: work@oh_clockdiv (work@oh_clockdiv), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockdiv.v, line:9:1, endln:167:10 |vpiName:clk0_sel |vpiFullName:work@oh_clockdiv.clk0_sel |vpiNetType:1 |vpiNet: \_logic_net: (work@oh_clockdiv.clk0_sel_sh), line:44:15, endln:44:26 |vpiParent: - \_module: work@oh_clockdiv (work@oh_clockdiv), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockdiv.v, line:9:1, endln:167:10 + \_module_inst: work@oh_clockdiv (work@oh_clockdiv), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockdiv.v, line:9:1, endln:167:10 |vpiName:clk0_sel_sh |vpiFullName:work@oh_clockdiv.clk0_sel_sh |vpiNetType:1 |vpiPort: \_port: (clk), line:17:13, endln:17:16 |vpiParent: - \_module: work@oh_clockdiv (work@oh_clockdiv), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockdiv.v, line:9:1, endln:167:10 + \_module_inst: work@oh_clockdiv (work@oh_clockdiv), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockdiv.v, line:9:1, endln:167:10 |vpiName:clk |vpiDirection:1 |vpiLowConn: @@ -12147,7 +12147,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (nreset), line:18:13, endln:18:19 |vpiParent: - \_module: work@oh_clockdiv (work@oh_clockdiv), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockdiv.v, line:9:1, endln:167:10 + \_module_inst: work@oh_clockdiv (work@oh_clockdiv), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockdiv.v, line:9:1, endln:167:10 |vpiName:nreset |vpiDirection:1 |vpiLowConn: @@ -12159,7 +12159,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (clkchange), line:19:13, endln:19:22 |vpiParent: - \_module: work@oh_clockdiv (work@oh_clockdiv), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockdiv.v, line:9:1, endln:167:10 + \_module_inst: work@oh_clockdiv (work@oh_clockdiv), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockdiv.v, line:9:1, endln:167:10 |vpiName:clkchange |vpiDirection:1 |vpiLowConn: @@ -12171,7 +12171,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (clken), line:20:13, endln:20:18 |vpiParent: - \_module: work@oh_clockdiv (work@oh_clockdiv), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockdiv.v, line:9:1, endln:167:10 + \_module_inst: work@oh_clockdiv (work@oh_clockdiv), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockdiv.v, line:9:1, endln:167:10 |vpiName:clken |vpiDirection:1 |vpiLowConn: @@ -12183,7 +12183,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (clkdiv), line:21:18, endln:21:24 |vpiParent: - \_module: work@oh_clockdiv (work@oh_clockdiv), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockdiv.v, line:9:1, endln:167:10 + \_module_inst: work@oh_clockdiv (work@oh_clockdiv), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockdiv.v, line:9:1, endln:167:10 |vpiName:clkdiv |vpiDirection:1 |vpiLowConn: @@ -12213,7 +12213,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (clkphase0), line:22:18, endln:22:27 |vpiParent: - \_module: work@oh_clockdiv (work@oh_clockdiv), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockdiv.v, line:9:1, endln:167:10 + \_module_inst: work@oh_clockdiv (work@oh_clockdiv), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockdiv.v, line:9:1, endln:167:10 |vpiName:clkphase0 |vpiDirection:1 |vpiLowConn: @@ -12243,7 +12243,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (clkphase1), line:23:18, endln:23:27 |vpiParent: - \_module: work@oh_clockdiv (work@oh_clockdiv), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockdiv.v, line:9:1, endln:167:10 + \_module_inst: work@oh_clockdiv (work@oh_clockdiv), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockdiv.v, line:9:1, endln:167:10 |vpiName:clkphase1 |vpiDirection:1 |vpiLowConn: @@ -12273,7 +12273,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (clkout0), line:25:14, endln:25:21 |vpiParent: - \_module: work@oh_clockdiv (work@oh_clockdiv), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockdiv.v, line:9:1, endln:167:10 + \_module_inst: work@oh_clockdiv (work@oh_clockdiv), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockdiv.v, line:9:1, endln:167:10 |vpiName:clkout0 |vpiDirection:2 |vpiLowConn: @@ -12285,7 +12285,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (clkrise0), line:26:14, endln:26:22 |vpiParent: - \_module: work@oh_clockdiv (work@oh_clockdiv), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockdiv.v, line:9:1, endln:167:10 + \_module_inst: work@oh_clockdiv (work@oh_clockdiv), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockdiv.v, line:9:1, endln:167:10 |vpiName:clkrise0 |vpiDirection:2 |vpiLowConn: @@ -12297,7 +12297,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (clkfall0), line:27:14, endln:27:22 |vpiParent: - \_module: work@oh_clockdiv (work@oh_clockdiv), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockdiv.v, line:9:1, endln:167:10 + \_module_inst: work@oh_clockdiv (work@oh_clockdiv), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockdiv.v, line:9:1, endln:167:10 |vpiName:clkfall0 |vpiDirection:2 |vpiLowConn: @@ -12309,7 +12309,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (clkout1), line:28:14, endln:28:21 |vpiParent: - \_module: work@oh_clockdiv (work@oh_clockdiv), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockdiv.v, line:9:1, endln:167:10 + \_module_inst: work@oh_clockdiv (work@oh_clockdiv), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockdiv.v, line:9:1, endln:167:10 |vpiName:clkout1 |vpiDirection:2 |vpiLowConn: @@ -12321,7 +12321,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (clkrise1), line:29:14, endln:29:22 |vpiParent: - \_module: work@oh_clockdiv (work@oh_clockdiv), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockdiv.v, line:9:1, endln:167:10 + \_module_inst: work@oh_clockdiv (work@oh_clockdiv), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockdiv.v, line:9:1, endln:167:10 |vpiName:clkrise1 |vpiDirection:2 |vpiLowConn: @@ -12333,7 +12333,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (clkfall1), line:30:14, endln:30:22 |vpiParent: - \_module: work@oh_clockdiv (work@oh_clockdiv), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockdiv.v, line:9:1, endln:167:10 + \_module_inst: work@oh_clockdiv (work@oh_clockdiv), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockdiv.v, line:9:1, endln:167:10 |vpiName:clkfall1 |vpiDirection:2 |vpiLowConn: @@ -12345,7 +12345,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (clkstable), line:31:14, endln:31:23 |vpiParent: - \_module: work@oh_clockdiv (work@oh_clockdiv), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockdiv.v, line:9:1, endln:167:10 + \_module_inst: work@oh_clockdiv (work@oh_clockdiv), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockdiv.v, line:9:1, endln:167:10 |vpiName:clkstable |vpiDirection:2 |vpiLowConn: @@ -12357,7 +12357,7 @@ design: (work@oh_fifo_async) |vpiProcess: \_always: , line:50:4, endln:56:41 |vpiParent: - \_module: work@oh_clockdiv (work@oh_clockdiv), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockdiv.v, line:9:1, endln:167:10 + \_module_inst: work@oh_clockdiv (work@oh_clockdiv), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockdiv.v, line:9:1, endln:167:10 |vpiStmt: \_event_control: , line:50:11, endln:50:44 |vpiParent: @@ -12568,7 +12568,7 @@ design: (work@oh_fifo_async) |vpiProcess: \_always: , line:64:4, endln:71:39 |vpiParent: - \_module: work@oh_clockdiv (work@oh_clockdiv), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockdiv.v, line:9:1, endln:167:10 + \_module_inst: work@oh_clockdiv (work@oh_clockdiv), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockdiv.v, line:9:1, endln:167:10 |vpiStmt: \_event_control: , line:64:11, endln:64:44 |vpiParent: @@ -12763,7 +12763,7 @@ design: (work@oh_fifo_async) |vpiProcess: \_always: , line:88:4, endln:94:28 |vpiParent: - \_module: work@oh_clockdiv (work@oh_clockdiv), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockdiv.v, line:9:1, endln:167:10 + \_module_inst: work@oh_clockdiv (work@oh_clockdiv), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockdiv.v, line:9:1, endln:167:10 |vpiStmt: \_event_control: , line:88:11, endln:88:44 |vpiParent: @@ -12885,7 +12885,7 @@ design: (work@oh_fifo_async) |vpiProcess: \_always: , line:122:4, endln:128:28 |vpiParent: - \_module: work@oh_clockdiv (work@oh_clockdiv), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockdiv.v, line:9:1, endln:167:10 + \_module_inst: work@oh_clockdiv (work@oh_clockdiv), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockdiv.v, line:9:1, endln:167:10 |vpiStmt: \_event_control: , line:122:11, endln:122:44 |vpiParent: @@ -13007,7 +13007,7 @@ design: (work@oh_fifo_async) |vpiProcess: \_always: , line:131:4, endln:132:35 |vpiParent: - \_module: work@oh_clockdiv (work@oh_clockdiv), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockdiv.v, line:9:1, endln:167:10 + \_module_inst: work@oh_clockdiv (work@oh_clockdiv), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockdiv.v, line:9:1, endln:167:10 |vpiStmt: \_event_control: , line:131:11, endln:131:26 |vpiParent: @@ -13044,7 +13044,7 @@ design: (work@oh_fifo_async) |vpiContAssign: \_cont_assign: , line:58:11, endln:58:44 |vpiParent: - \_module: work@oh_clockdiv (work@oh_clockdiv), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockdiv.v, line:9:1, endln:167:10 + \_module_inst: work@oh_clockdiv (work@oh_clockdiv), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockdiv.v, line:9:1, endln:167:10 |vpiRhs: \_operation: , line:58:24, endln:58:43 |vpiParent: @@ -13089,7 +13089,7 @@ design: (work@oh_fifo_async) |vpiContAssign: \_cont_assign: , line:73:11, endln:73:55 |vpiParent: - \_module: work@oh_clockdiv (work@oh_clockdiv), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockdiv.v, line:9:1, endln:167:10 + \_module_inst: work@oh_clockdiv (work@oh_clockdiv), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockdiv.v, line:9:1, endln:167:10 |vpiRhs: \_operation: , line:73:27, endln:73:54 |vpiParent: @@ -13148,7 +13148,7 @@ design: (work@oh_fifo_async) |vpiContAssign: \_cont_assign: , line:79:11, endln:79:58 |vpiParent: - \_module: work@oh_clockdiv (work@oh_clockdiv), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockdiv.v, line:9:1, endln:167:10 + \_module_inst: work@oh_clockdiv (work@oh_clockdiv), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockdiv.v, line:9:1, endln:167:10 |vpiRhs: \_operation: , line:79:27, endln:79:57 |vpiParent: @@ -13207,7 +13207,7 @@ design: (work@oh_fifo_async) |vpiContAssign: \_cont_assign: , line:80:11, endln:80:59 |vpiParent: - \_module: work@oh_clockdiv (work@oh_clockdiv), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockdiv.v, line:9:1, endln:167:10 + \_module_inst: work@oh_clockdiv (work@oh_clockdiv), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockdiv.v, line:9:1, endln:167:10 |vpiRhs: \_operation: , line:80:27, endln:80:58 |vpiParent: @@ -13266,7 +13266,7 @@ design: (work@oh_fifo_async) |vpiContAssign: \_cont_assign: , line:81:11, endln:81:58 |vpiParent: - \_module: work@oh_clockdiv (work@oh_clockdiv), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockdiv.v, line:9:1, endln:167:10 + \_module_inst: work@oh_clockdiv (work@oh_clockdiv), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockdiv.v, line:9:1, endln:167:10 |vpiRhs: \_operation: , line:81:27, endln:81:57 |vpiParent: @@ -13325,7 +13325,7 @@ design: (work@oh_fifo_async) |vpiContAssign: \_cont_assign: , line:82:11, endln:82:59 |vpiParent: - \_module: work@oh_clockdiv (work@oh_clockdiv), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockdiv.v, line:9:1, endln:167:10 + \_module_inst: work@oh_clockdiv (work@oh_clockdiv), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockdiv.v, line:9:1, endln:167:10 |vpiRhs: \_operation: , line:82:27, endln:82:58 |vpiParent: @@ -13384,7 +13384,7 @@ design: (work@oh_fifo_async) |vpiContAssign: \_cont_assign: , line:97:11, endln:97:45 |vpiParent: - \_module: work@oh_clockdiv (work@oh_clockdiv), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockdiv.v, line:9:1, endln:167:10 + \_module_inst: work@oh_clockdiv (work@oh_clockdiv), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockdiv.v, line:9:1, endln:167:10 |vpiRhs: \_operation: , line:97:27, endln:97:44 |vpiParent: @@ -13441,7 +13441,7 @@ design: (work@oh_fifo_async) |vpiContAssign: \_cont_assign: , line:98:11, endln:98:45 |vpiParent: - \_module: work@oh_clockdiv (work@oh_clockdiv), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockdiv.v, line:9:1, endln:167:10 + \_module_inst: work@oh_clockdiv (work@oh_clockdiv), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockdiv.v, line:9:1, endln:167:10 |vpiRhs: \_operation: , line:98:25, endln:98:45 |vpiParent: @@ -13503,7 +13503,7 @@ design: (work@oh_fifo_async) |vpiContAssign: \_cont_assign: , line:135:11, endln:135:30 |vpiParent: - \_module: work@oh_clockdiv (work@oh_clockdiv), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockdiv.v, line:9:1, endln:167:10 + \_module_inst: work@oh_clockdiv (work@oh_clockdiv), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockdiv.v, line:9:1, endln:167:10 |vpiRhs: \_constant: , line:135:26, endln:135:30 |vpiParent: @@ -13533,7 +13533,7 @@ design: (work@oh_fifo_async) |vpiContAssign: \_cont_assign: , line:136:11, endln:136:44 |vpiParent: - \_module: work@oh_clockdiv (work@oh_clockdiv), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockdiv.v, line:9:1, endln:167:10 + \_module_inst: work@oh_clockdiv (work@oh_clockdiv), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockdiv.v, line:9:1, endln:167:10 |vpiRhs: \_operation: , line:136:26, endln:136:43 |vpiParent: @@ -13590,7 +13590,7 @@ design: (work@oh_fifo_async) |vpiContAssign: \_cont_assign: , line:137:11, endln:137:44 |vpiParent: - \_module: work@oh_clockdiv (work@oh_clockdiv), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockdiv.v, line:9:1, endln:167:10 + \_module_inst: work@oh_clockdiv (work@oh_clockdiv), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockdiv.v, line:9:1, endln:167:10 |vpiRhs: \_operation: , line:137:26, endln:137:43 |vpiParent: @@ -13647,7 +13647,7 @@ design: (work@oh_fifo_async) |vpiContAssign: \_cont_assign: , line:138:11, endln:138:37 |vpiParent: - \_module: work@oh_clockdiv (work@oh_clockdiv), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockdiv.v, line:9:1, endln:167:10 + \_module_inst: work@oh_clockdiv (work@oh_clockdiv), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockdiv.v, line:9:1, endln:167:10 |vpiRhs: \_operation: , line:138:25, endln:138:37 |vpiParent: @@ -13693,7 +13693,7 @@ design: (work@oh_fifo_async) |vpiContAssign: \_cont_assign: , line:148:11, endln:148:30 |vpiParent: - \_module: work@oh_clockdiv (work@oh_clockdiv), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockdiv.v, line:9:1, endln:167:10 + \_module_inst: work@oh_clockdiv (work@oh_clockdiv), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockdiv.v, line:9:1, endln:167:10 |vpiRhs: \_constant: , line:148:26, endln:148:30 |vpiParent: @@ -13723,7 +13723,7 @@ design: (work@oh_fifo_async) |vpiContAssign: \_cont_assign: , line:149:11, endln:149:44 |vpiParent: - \_module: work@oh_clockdiv (work@oh_clockdiv), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockdiv.v, line:9:1, endln:167:10 + \_module_inst: work@oh_clockdiv (work@oh_clockdiv), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockdiv.v, line:9:1, endln:167:10 |vpiRhs: \_operation: , line:149:26, endln:149:43 |vpiParent: @@ -13780,7 +13780,7 @@ design: (work@oh_fifo_async) |vpiContAssign: \_cont_assign: , line:150:11, endln:150:44 |vpiParent: - \_module: work@oh_clockdiv (work@oh_clockdiv), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockdiv.v, line:9:1, endln:167:10 + \_module_inst: work@oh_clockdiv (work@oh_clockdiv), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockdiv.v, line:9:1, endln:167:10 |vpiRhs: \_operation: , line:150:26, endln:150:43 |vpiParent: @@ -13837,7 +13837,7 @@ design: (work@oh_fifo_async) |vpiContAssign: \_cont_assign: , line:151:11, endln:151:37 |vpiParent: - \_module: work@oh_clockdiv (work@oh_clockdiv), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockdiv.v, line:9:1, endln:167:10 + \_module_inst: work@oh_clockdiv (work@oh_clockdiv), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockdiv.v, line:9:1, endln:167:10 |vpiRhs: \_operation: , line:151:25, endln:151:37 |vpiParent: @@ -13881,14 +13881,14 @@ design: (work@oh_fifo_async) |UINT:0 |vpiConstType:9 |uhdmallModules: -\_module: work@oh_clockgate (work@oh_clockgate), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockgate.v, line:8:1, endln:46:10 +\_module_inst: work@oh_clockgate (work@oh_clockgate), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockgate.v, line:8:1, endln:46:10 |vpiParent: \_design: (work@oh_fifo_async) |vpiFullName:work@oh_clockgate |vpiParameter: \_parameter: (work@oh_clockgate.SYN), line:9:15, endln:9:18 |vpiParent: - \_module: work@oh_clockgate (work@oh_clockgate), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockgate.v, line:8:1, endln:46:10 + \_module_inst: work@oh_clockgate (work@oh_clockgate), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockgate.v, line:8:1, endln:46:10 |STRING:TRUE |vpiTypespec: \_string_typespec: @@ -13897,7 +13897,7 @@ design: (work@oh_fifo_async) |vpiParameter: \_parameter: (work@oh_clockgate.TYPE), line:10:15, endln:10:19 |vpiParent: - \_module: work@oh_clockgate (work@oh_clockgate), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockgate.v, line:8:1, endln:46:10 + \_module_inst: work@oh_clockgate (work@oh_clockgate), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockgate.v, line:8:1, endln:46:10 |STRING:DEFAULT |vpiTypespec: \_string_typespec: @@ -13906,7 +13906,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:9:15, endln:9:28 |vpiParent: - \_module: work@oh_clockgate (work@oh_clockgate), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockgate.v, line:8:1, endln:46:10 + \_module_inst: work@oh_clockgate (work@oh_clockgate), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockgate.v, line:8:1, endln:46:10 |vpiRhs: \_constant: , line:9:22, endln:9:28 |vpiDecompile:TRUE @@ -13920,7 +13920,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:10:15, endln:10:31 |vpiParent: - \_module: work@oh_clockgate (work@oh_clockgate), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockgate.v, line:8:1, endln:46:10 + \_module_inst: work@oh_clockgate (work@oh_clockgate), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockgate.v, line:8:1, endln:46:10 |vpiRhs: \_constant: , line:10:22, endln:10:31 |vpiDecompile:DEFAULT @@ -13936,31 +13936,31 @@ design: (work@oh_fifo_async) |vpiNet: \_logic_net: (work@oh_clockgate.clk), line:13:9, endln:13:12 |vpiParent: - \_module: work@oh_clockgate (work@oh_clockgate), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockgate.v, line:8:1, endln:46:10 + \_module_inst: work@oh_clockgate (work@oh_clockgate), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockgate.v, line:8:1, endln:46:10 |vpiName:clk |vpiFullName:work@oh_clockgate.clk |vpiNet: \_logic_net: (work@oh_clockgate.te), line:14:9, endln:14:11 |vpiParent: - \_module: work@oh_clockgate (work@oh_clockgate), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockgate.v, line:8:1, endln:46:10 + \_module_inst: work@oh_clockgate (work@oh_clockgate), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockgate.v, line:8:1, endln:46:10 |vpiName:te |vpiFullName:work@oh_clockgate.te |vpiNet: \_logic_net: (work@oh_clockgate.en), line:15:9, endln:15:11 |vpiParent: - \_module: work@oh_clockgate (work@oh_clockgate), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockgate.v, line:8:1, endln:46:10 + \_module_inst: work@oh_clockgate (work@oh_clockgate), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockgate.v, line:8:1, endln:46:10 |vpiName:en |vpiFullName:work@oh_clockgate.en |vpiNet: \_logic_net: (work@oh_clockgate.eclk), line:16:9, endln:16:13 |vpiParent: - \_module: work@oh_clockgate (work@oh_clockgate), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockgate.v, line:8:1, endln:46:10 + \_module_inst: work@oh_clockgate (work@oh_clockgate), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockgate.v, line:8:1, endln:46:10 |vpiName:eclk |vpiFullName:work@oh_clockgate.eclk |vpiPort: \_port: (clk), line:13:9, endln:13:12 |vpiParent: - \_module: work@oh_clockgate (work@oh_clockgate), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockgate.v, line:8:1, endln:46:10 + \_module_inst: work@oh_clockgate (work@oh_clockgate), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockgate.v, line:8:1, endln:46:10 |vpiName:clk |vpiDirection:1 |vpiLowConn: @@ -13972,7 +13972,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (te), line:14:9, endln:14:11 |vpiParent: - \_module: work@oh_clockgate (work@oh_clockgate), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockgate.v, line:8:1, endln:46:10 + \_module_inst: work@oh_clockgate (work@oh_clockgate), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockgate.v, line:8:1, endln:46:10 |vpiName:te |vpiDirection:1 |vpiLowConn: @@ -13984,7 +13984,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (en), line:15:9, endln:15:11 |vpiParent: - \_module: work@oh_clockgate (work@oh_clockgate), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockgate.v, line:8:1, endln:46:10 + \_module_inst: work@oh_clockgate (work@oh_clockgate), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockgate.v, line:8:1, endln:46:10 |vpiName:en |vpiDirection:1 |vpiLowConn: @@ -13996,7 +13996,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (eclk), line:16:9, endln:16:13 |vpiParent: - \_module: work@oh_clockgate (work@oh_clockgate), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockgate.v, line:8:1, endln:46:10 + \_module_inst: work@oh_clockgate (work@oh_clockgate), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockgate.v, line:8:1, endln:46:10 |vpiName:eclk |vpiDirection:2 |vpiLowConn: @@ -14006,14 +14006,14 @@ design: (work@oh_fifo_async) |vpiTypedef: \_logic_typespec: , line:16:9, endln:16:9 |uhdmallModules: -\_module: work@oh_clockmux (work@oh_clockmux), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockmux.v, line:8:1, endln:33:10 +\_module_inst: work@oh_clockmux (work@oh_clockmux), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockmux.v, line:8:1, endln:33:10 |vpiParent: \_design: (work@oh_fifo_async) |vpiFullName:work@oh_clockmux |vpiParameter: \_parameter: (work@oh_clockmux.N), line:9:15, endln:9:16 |vpiParent: - \_module: work@oh_clockmux (work@oh_clockmux), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockmux.v, line:8:1, endln:33:10 + \_module_inst: work@oh_clockmux (work@oh_clockmux), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockmux.v, line:8:1, endln:33:10 |UINT:2 |vpiTypespec: \_int_typespec: @@ -14022,7 +14022,7 @@ design: (work@oh_fifo_async) |vpiParameter: \_parameter: (work@oh_clockmux.SYN), line:10:15, endln:10:18 |vpiParent: - \_module: work@oh_clockmux (work@oh_clockmux), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockmux.v, line:8:1, endln:33:10 + \_module_inst: work@oh_clockmux (work@oh_clockmux), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockmux.v, line:8:1, endln:33:10 |STRING:TRUE |vpiTypespec: \_string_typespec: @@ -14031,7 +14031,7 @@ design: (work@oh_fifo_async) |vpiParameter: \_parameter: (work@oh_clockmux.TYPE), line:11:15, endln:11:19 |vpiParent: - \_module: work@oh_clockmux (work@oh_clockmux), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockmux.v, line:8:1, endln:33:10 + \_module_inst: work@oh_clockmux (work@oh_clockmux), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockmux.v, line:8:1, endln:33:10 |STRING:DEFAULT |vpiTypespec: \_string_typespec: @@ -14040,7 +14040,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:9:15, endln:9:23 |vpiParent: - \_module: work@oh_clockmux (work@oh_clockmux), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockmux.v, line:8:1, endln:33:10 + \_module_inst: work@oh_clockmux (work@oh_clockmux), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockmux.v, line:8:1, endln:33:10 |vpiRhs: \_constant: , line:9:22, endln:9:23 |vpiDecompile:2 @@ -14054,7 +14054,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:10:15, endln:10:28 |vpiParent: - \_module: work@oh_clockmux (work@oh_clockmux), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockmux.v, line:8:1, endln:33:10 + \_module_inst: work@oh_clockmux (work@oh_clockmux), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockmux.v, line:8:1, endln:33:10 |vpiRhs: \_constant: , line:10:22, endln:10:28 |vpiDecompile:TRUE @@ -14068,7 +14068,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:11:15, endln:11:31 |vpiParent: - \_module: work@oh_clockmux (work@oh_clockmux), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockmux.v, line:8:1, endln:33:10 + \_module_inst: work@oh_clockmux (work@oh_clockmux), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockmux.v, line:8:1, endln:33:10 |vpiRhs: \_constant: , line:11:22, endln:11:31 |vpiDecompile:DEFAULT @@ -14084,25 +14084,25 @@ design: (work@oh_fifo_async) |vpiNet: \_logic_net: (work@oh_clockmux.en), line:14:19, endln:14:21 |vpiParent: - \_module: work@oh_clockmux (work@oh_clockmux), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockmux.v, line:8:1, endln:33:10 + \_module_inst: work@oh_clockmux (work@oh_clockmux), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockmux.v, line:8:1, endln:33:10 |vpiName:en |vpiFullName:work@oh_clockmux.en |vpiNet: \_logic_net: (work@oh_clockmux.clkin), line:15:19, endln:15:24 |vpiParent: - \_module: work@oh_clockmux (work@oh_clockmux), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockmux.v, line:8:1, endln:33:10 + \_module_inst: work@oh_clockmux (work@oh_clockmux), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockmux.v, line:8:1, endln:33:10 |vpiName:clkin |vpiFullName:work@oh_clockmux.clkin |vpiNet: \_logic_net: (work@oh_clockmux.clkout), line:16:15, endln:16:21 |vpiParent: - \_module: work@oh_clockmux (work@oh_clockmux), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockmux.v, line:8:1, endln:33:10 + \_module_inst: work@oh_clockmux (work@oh_clockmux), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockmux.v, line:8:1, endln:33:10 |vpiName:clkout |vpiFullName:work@oh_clockmux.clkout |vpiPort: \_port: (en), line:14:19, endln:14:21 |vpiParent: - \_module: work@oh_clockmux (work@oh_clockmux), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockmux.v, line:8:1, endln:33:10 + \_module_inst: work@oh_clockmux (work@oh_clockmux), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockmux.v, line:8:1, endln:33:10 |vpiName:en |vpiDirection:1 |vpiLowConn: @@ -14142,7 +14142,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (clkin), line:15:19, endln:15:24 |vpiParent: - \_module: work@oh_clockmux (work@oh_clockmux), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockmux.v, line:8:1, endln:33:10 + \_module_inst: work@oh_clockmux (work@oh_clockmux), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockmux.v, line:8:1, endln:33:10 |vpiName:clkin |vpiDirection:1 |vpiLowConn: @@ -14182,7 +14182,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (clkout), line:16:15, endln:16:21 |vpiParent: - \_module: work@oh_clockmux (work@oh_clockmux), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockmux.v, line:8:1, endln:33:10 + \_module_inst: work@oh_clockmux (work@oh_clockmux), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockmux.v, line:8:1, endln:33:10 |vpiName:clkout |vpiDirection:2 |vpiLowConn: @@ -14192,14 +14192,14 @@ design: (work@oh_fifo_async) |vpiTypedef: \_logic_typespec: , line:16:15, endln:16:15 |uhdmallModules: -\_module: work@oh_clockmux2 (work@oh_clockmux2), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockmux2.v, line:8:1, endln:40:10 +\_module_inst: work@oh_clockmux2 (work@oh_clockmux2), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockmux2.v, line:8:1, endln:40:10 |vpiParent: \_design: (work@oh_fifo_async) |vpiFullName:work@oh_clockmux2 |vpiParameter: \_parameter: (work@oh_clockmux2.N), line:9:15, endln:9:16 |vpiParent: - \_module: work@oh_clockmux2 (work@oh_clockmux2), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockmux2.v, line:8:1, endln:40:10 + \_module_inst: work@oh_clockmux2 (work@oh_clockmux2), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockmux2.v, line:8:1, endln:40:10 |UINT:1 |vpiTypespec: \_int_typespec: @@ -14208,7 +14208,7 @@ design: (work@oh_fifo_async) |vpiParameter: \_parameter: (work@oh_clockmux2.SYN), line:10:15, endln:10:18 |vpiParent: - \_module: work@oh_clockmux2 (work@oh_clockmux2), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockmux2.v, line:8:1, endln:40:10 + \_module_inst: work@oh_clockmux2 (work@oh_clockmux2), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockmux2.v, line:8:1, endln:40:10 |STRING:TRUE |vpiTypespec: \_string_typespec: @@ -14217,7 +14217,7 @@ design: (work@oh_fifo_async) |vpiParameter: \_parameter: (work@oh_clockmux2.TYPE), line:11:15, endln:11:19 |vpiParent: - \_module: work@oh_clockmux2 (work@oh_clockmux2), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockmux2.v, line:8:1, endln:40:10 + \_module_inst: work@oh_clockmux2 (work@oh_clockmux2), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockmux2.v, line:8:1, endln:40:10 |STRING:DEFAULT |vpiTypespec: \_string_typespec: @@ -14226,7 +14226,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:9:15, endln:9:23 |vpiParent: - \_module: work@oh_clockmux2 (work@oh_clockmux2), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockmux2.v, line:8:1, endln:40:10 + \_module_inst: work@oh_clockmux2 (work@oh_clockmux2), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockmux2.v, line:8:1, endln:40:10 |vpiRhs: \_constant: , line:9:22, endln:9:23 |vpiDecompile:1 @@ -14240,7 +14240,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:10:15, endln:10:28 |vpiParent: - \_module: work@oh_clockmux2 (work@oh_clockmux2), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockmux2.v, line:8:1, endln:40:10 + \_module_inst: work@oh_clockmux2 (work@oh_clockmux2), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockmux2.v, line:8:1, endln:40:10 |vpiRhs: \_constant: , line:10:22, endln:10:28 |vpiDecompile:TRUE @@ -14254,7 +14254,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:11:15, endln:11:31 |vpiParent: - \_module: work@oh_clockmux2 (work@oh_clockmux2), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockmux2.v, line:8:1, endln:40:10 + \_module_inst: work@oh_clockmux2 (work@oh_clockmux2), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockmux2.v, line:8:1, endln:40:10 |vpiRhs: \_constant: , line:11:22, endln:11:31 |vpiDecompile:DEFAULT @@ -14270,37 +14270,37 @@ design: (work@oh_fifo_async) |vpiNet: \_logic_net: (work@oh_clockmux2.en0), line:14:20, endln:14:23 |vpiParent: - \_module: work@oh_clockmux2 (work@oh_clockmux2), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockmux2.v, line:8:1, endln:40:10 + \_module_inst: work@oh_clockmux2 (work@oh_clockmux2), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockmux2.v, line:8:1, endln:40:10 |vpiName:en0 |vpiFullName:work@oh_clockmux2.en0 |vpiNet: \_logic_net: (work@oh_clockmux2.en1), line:15:20, endln:15:23 |vpiParent: - \_module: work@oh_clockmux2 (work@oh_clockmux2), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockmux2.v, line:8:1, endln:40:10 + \_module_inst: work@oh_clockmux2 (work@oh_clockmux2), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockmux2.v, line:8:1, endln:40:10 |vpiName:en1 |vpiFullName:work@oh_clockmux2.en1 |vpiNet: \_logic_net: (work@oh_clockmux2.clkin0), line:16:20, endln:16:26 |vpiParent: - \_module: work@oh_clockmux2 (work@oh_clockmux2), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockmux2.v, line:8:1, endln:40:10 + \_module_inst: work@oh_clockmux2 (work@oh_clockmux2), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockmux2.v, line:8:1, endln:40:10 |vpiName:clkin0 |vpiFullName:work@oh_clockmux2.clkin0 |vpiNet: \_logic_net: (work@oh_clockmux2.clkin1), line:17:20, endln:17:26 |vpiParent: - \_module: work@oh_clockmux2 (work@oh_clockmux2), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockmux2.v, line:8:1, endln:40:10 + \_module_inst: work@oh_clockmux2 (work@oh_clockmux2), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockmux2.v, line:8:1, endln:40:10 |vpiName:clkin1 |vpiFullName:work@oh_clockmux2.clkin1 |vpiNet: \_logic_net: (work@oh_clockmux2.clkout), line:18:20, endln:18:26 |vpiParent: - \_module: work@oh_clockmux2 (work@oh_clockmux2), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockmux2.v, line:8:1, endln:40:10 + \_module_inst: work@oh_clockmux2 (work@oh_clockmux2), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockmux2.v, line:8:1, endln:40:10 |vpiName:clkout |vpiFullName:work@oh_clockmux2.clkout |vpiPort: \_port: (en0), line:14:20, endln:14:23 |vpiParent: - \_module: work@oh_clockmux2 (work@oh_clockmux2), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockmux2.v, line:8:1, endln:40:10 + \_module_inst: work@oh_clockmux2 (work@oh_clockmux2), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockmux2.v, line:8:1, endln:40:10 |vpiName:en0 |vpiDirection:1 |vpiLowConn: @@ -14340,7 +14340,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (en1), line:15:20, endln:15:23 |vpiParent: - \_module: work@oh_clockmux2 (work@oh_clockmux2), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockmux2.v, line:8:1, endln:40:10 + \_module_inst: work@oh_clockmux2 (work@oh_clockmux2), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockmux2.v, line:8:1, endln:40:10 |vpiName:en1 |vpiDirection:1 |vpiLowConn: @@ -14380,7 +14380,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (clkin0), line:16:20, endln:16:26 |vpiParent: - \_module: work@oh_clockmux2 (work@oh_clockmux2), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockmux2.v, line:8:1, endln:40:10 + \_module_inst: work@oh_clockmux2 (work@oh_clockmux2), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockmux2.v, line:8:1, endln:40:10 |vpiName:clkin0 |vpiDirection:1 |vpiLowConn: @@ -14420,7 +14420,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (clkin1), line:17:20, endln:17:26 |vpiParent: - \_module: work@oh_clockmux2 (work@oh_clockmux2), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockmux2.v, line:8:1, endln:40:10 + \_module_inst: work@oh_clockmux2 (work@oh_clockmux2), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockmux2.v, line:8:1, endln:40:10 |vpiName:clkin1 |vpiDirection:1 |vpiLowConn: @@ -14460,7 +14460,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (clkout), line:18:20, endln:18:26 |vpiParent: - \_module: work@oh_clockmux2 (work@oh_clockmux2), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockmux2.v, line:8:1, endln:40:10 + \_module_inst: work@oh_clockmux2 (work@oh_clockmux2), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockmux2.v, line:8:1, endln:40:10 |vpiName:clkout |vpiDirection:2 |vpiLowConn: @@ -14498,14 +14498,14 @@ design: (work@oh_fifo_async) |UINT:0 |vpiConstType:9 |uhdmallModules: -\_module: work@oh_clockmux4 (work@oh_clockmux4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockmux4.v, line:8:1, endln:50:10 +\_module_inst: work@oh_clockmux4 (work@oh_clockmux4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockmux4.v, line:8:1, endln:50:10 |vpiParent: \_design: (work@oh_fifo_async) |vpiFullName:work@oh_clockmux4 |vpiParameter: \_parameter: (work@oh_clockmux4.N), line:9:15, endln:9:16 |vpiParent: - \_module: work@oh_clockmux4 (work@oh_clockmux4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockmux4.v, line:8:1, endln:50:10 + \_module_inst: work@oh_clockmux4 (work@oh_clockmux4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockmux4.v, line:8:1, endln:50:10 |UINT:1 |vpiTypespec: \_int_typespec: @@ -14514,7 +14514,7 @@ design: (work@oh_fifo_async) |vpiParameter: \_parameter: (work@oh_clockmux4.SYN), line:10:15, endln:10:18 |vpiParent: - \_module: work@oh_clockmux4 (work@oh_clockmux4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockmux4.v, line:8:1, endln:50:10 + \_module_inst: work@oh_clockmux4 (work@oh_clockmux4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockmux4.v, line:8:1, endln:50:10 |STRING:TRUE |vpiTypespec: \_string_typespec: @@ -14523,7 +14523,7 @@ design: (work@oh_fifo_async) |vpiParameter: \_parameter: (work@oh_clockmux4.TYPE), line:11:15, endln:11:19 |vpiParent: - \_module: work@oh_clockmux4 (work@oh_clockmux4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockmux4.v, line:8:1, endln:50:10 + \_module_inst: work@oh_clockmux4 (work@oh_clockmux4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockmux4.v, line:8:1, endln:50:10 |STRING:DEFAULT |vpiTypespec: \_string_typespec: @@ -14532,7 +14532,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:9:15, endln:9:23 |vpiParent: - \_module: work@oh_clockmux4 (work@oh_clockmux4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockmux4.v, line:8:1, endln:50:10 + \_module_inst: work@oh_clockmux4 (work@oh_clockmux4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockmux4.v, line:8:1, endln:50:10 |vpiRhs: \_constant: , line:9:22, endln:9:23 |vpiDecompile:1 @@ -14546,7 +14546,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:10:15, endln:10:28 |vpiParent: - \_module: work@oh_clockmux4 (work@oh_clockmux4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockmux4.v, line:8:1, endln:50:10 + \_module_inst: work@oh_clockmux4 (work@oh_clockmux4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockmux4.v, line:8:1, endln:50:10 |vpiRhs: \_constant: , line:10:22, endln:10:28 |vpiDecompile:TRUE @@ -14560,7 +14560,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:11:15, endln:11:31 |vpiParent: - \_module: work@oh_clockmux4 (work@oh_clockmux4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockmux4.v, line:8:1, endln:50:10 + \_module_inst: work@oh_clockmux4 (work@oh_clockmux4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockmux4.v, line:8:1, endln:50:10 |vpiRhs: \_constant: , line:11:22, endln:11:31 |vpiDecompile:DEFAULT @@ -14576,61 +14576,61 @@ design: (work@oh_fifo_async) |vpiNet: \_logic_net: (work@oh_clockmux4.en0), line:14:20, endln:14:23 |vpiParent: - \_module: work@oh_clockmux4 (work@oh_clockmux4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockmux4.v, line:8:1, endln:50:10 + \_module_inst: work@oh_clockmux4 (work@oh_clockmux4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockmux4.v, line:8:1, endln:50:10 |vpiName:en0 |vpiFullName:work@oh_clockmux4.en0 |vpiNet: \_logic_net: (work@oh_clockmux4.en1), line:15:20, endln:15:23 |vpiParent: - \_module: work@oh_clockmux4 (work@oh_clockmux4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockmux4.v, line:8:1, endln:50:10 + \_module_inst: work@oh_clockmux4 (work@oh_clockmux4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockmux4.v, line:8:1, endln:50:10 |vpiName:en1 |vpiFullName:work@oh_clockmux4.en1 |vpiNet: \_logic_net: (work@oh_clockmux4.en2), line:16:20, endln:16:23 |vpiParent: - \_module: work@oh_clockmux4 (work@oh_clockmux4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockmux4.v, line:8:1, endln:50:10 + \_module_inst: work@oh_clockmux4 (work@oh_clockmux4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockmux4.v, line:8:1, endln:50:10 |vpiName:en2 |vpiFullName:work@oh_clockmux4.en2 |vpiNet: \_logic_net: (work@oh_clockmux4.en3), line:17:20, endln:17:23 |vpiParent: - \_module: work@oh_clockmux4 (work@oh_clockmux4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockmux4.v, line:8:1, endln:50:10 + \_module_inst: work@oh_clockmux4 (work@oh_clockmux4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockmux4.v, line:8:1, endln:50:10 |vpiName:en3 |vpiFullName:work@oh_clockmux4.en3 |vpiNet: \_logic_net: (work@oh_clockmux4.clkin0), line:18:20, endln:18:26 |vpiParent: - \_module: work@oh_clockmux4 (work@oh_clockmux4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockmux4.v, line:8:1, endln:50:10 + \_module_inst: work@oh_clockmux4 (work@oh_clockmux4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockmux4.v, line:8:1, endln:50:10 |vpiName:clkin0 |vpiFullName:work@oh_clockmux4.clkin0 |vpiNet: \_logic_net: (work@oh_clockmux4.clkin1), line:19:20, endln:19:26 |vpiParent: - \_module: work@oh_clockmux4 (work@oh_clockmux4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockmux4.v, line:8:1, endln:50:10 + \_module_inst: work@oh_clockmux4 (work@oh_clockmux4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockmux4.v, line:8:1, endln:50:10 |vpiName:clkin1 |vpiFullName:work@oh_clockmux4.clkin1 |vpiNet: \_logic_net: (work@oh_clockmux4.clkin2), line:20:20, endln:20:26 |vpiParent: - \_module: work@oh_clockmux4 (work@oh_clockmux4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockmux4.v, line:8:1, endln:50:10 + \_module_inst: work@oh_clockmux4 (work@oh_clockmux4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockmux4.v, line:8:1, endln:50:10 |vpiName:clkin2 |vpiFullName:work@oh_clockmux4.clkin2 |vpiNet: \_logic_net: (work@oh_clockmux4.clkin3), line:21:20, endln:21:26 |vpiParent: - \_module: work@oh_clockmux4 (work@oh_clockmux4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockmux4.v, line:8:1, endln:50:10 + \_module_inst: work@oh_clockmux4 (work@oh_clockmux4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockmux4.v, line:8:1, endln:50:10 |vpiName:clkin3 |vpiFullName:work@oh_clockmux4.clkin3 |vpiNet: \_logic_net: (work@oh_clockmux4.clkout), line:22:20, endln:22:26 |vpiParent: - \_module: work@oh_clockmux4 (work@oh_clockmux4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockmux4.v, line:8:1, endln:50:10 + \_module_inst: work@oh_clockmux4 (work@oh_clockmux4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockmux4.v, line:8:1, endln:50:10 |vpiName:clkout |vpiFullName:work@oh_clockmux4.clkout |vpiPort: \_port: (en0), line:14:20, endln:14:23 |vpiParent: - \_module: work@oh_clockmux4 (work@oh_clockmux4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockmux4.v, line:8:1, endln:50:10 + \_module_inst: work@oh_clockmux4 (work@oh_clockmux4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockmux4.v, line:8:1, endln:50:10 |vpiName:en0 |vpiDirection:1 |vpiLowConn: @@ -14670,7 +14670,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (en1), line:15:20, endln:15:23 |vpiParent: - \_module: work@oh_clockmux4 (work@oh_clockmux4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockmux4.v, line:8:1, endln:50:10 + \_module_inst: work@oh_clockmux4 (work@oh_clockmux4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockmux4.v, line:8:1, endln:50:10 |vpiName:en1 |vpiDirection:1 |vpiLowConn: @@ -14710,7 +14710,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (en2), line:16:20, endln:16:23 |vpiParent: - \_module: work@oh_clockmux4 (work@oh_clockmux4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockmux4.v, line:8:1, endln:50:10 + \_module_inst: work@oh_clockmux4 (work@oh_clockmux4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockmux4.v, line:8:1, endln:50:10 |vpiName:en2 |vpiDirection:1 |vpiLowConn: @@ -14750,7 +14750,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (en3), line:17:20, endln:17:23 |vpiParent: - \_module: work@oh_clockmux4 (work@oh_clockmux4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockmux4.v, line:8:1, endln:50:10 + \_module_inst: work@oh_clockmux4 (work@oh_clockmux4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockmux4.v, line:8:1, endln:50:10 |vpiName:en3 |vpiDirection:1 |vpiLowConn: @@ -14790,7 +14790,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (clkin0), line:18:20, endln:18:26 |vpiParent: - \_module: work@oh_clockmux4 (work@oh_clockmux4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockmux4.v, line:8:1, endln:50:10 + \_module_inst: work@oh_clockmux4 (work@oh_clockmux4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockmux4.v, line:8:1, endln:50:10 |vpiName:clkin0 |vpiDirection:1 |vpiLowConn: @@ -14830,7 +14830,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (clkin1), line:19:20, endln:19:26 |vpiParent: - \_module: work@oh_clockmux4 (work@oh_clockmux4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockmux4.v, line:8:1, endln:50:10 + \_module_inst: work@oh_clockmux4 (work@oh_clockmux4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockmux4.v, line:8:1, endln:50:10 |vpiName:clkin1 |vpiDirection:1 |vpiLowConn: @@ -14870,7 +14870,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (clkin2), line:20:20, endln:20:26 |vpiParent: - \_module: work@oh_clockmux4 (work@oh_clockmux4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockmux4.v, line:8:1, endln:50:10 + \_module_inst: work@oh_clockmux4 (work@oh_clockmux4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockmux4.v, line:8:1, endln:50:10 |vpiName:clkin2 |vpiDirection:1 |vpiLowConn: @@ -14910,7 +14910,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (clkin3), line:21:20, endln:21:26 |vpiParent: - \_module: work@oh_clockmux4 (work@oh_clockmux4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockmux4.v, line:8:1, endln:50:10 + \_module_inst: work@oh_clockmux4 (work@oh_clockmux4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockmux4.v, line:8:1, endln:50:10 |vpiName:clkin3 |vpiDirection:1 |vpiLowConn: @@ -14950,7 +14950,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (clkout), line:22:20, endln:22:26 |vpiParent: - \_module: work@oh_clockmux4 (work@oh_clockmux4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockmux4.v, line:8:1, endln:50:10 + \_module_inst: work@oh_clockmux4 (work@oh_clockmux4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockmux4.v, line:8:1, endln:50:10 |vpiName:clkout |vpiDirection:2 |vpiLowConn: @@ -14988,14 +14988,14 @@ design: (work@oh_fifo_async) |UINT:0 |vpiConstType:9 |uhdmallModules: -\_module: work@oh_clockor (work@oh_clockor), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockor.v, line:8:1, endln:31:10 +\_module_inst: work@oh_clockor (work@oh_clockor), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockor.v, line:8:1, endln:31:10 |vpiParent: \_design: (work@oh_fifo_async) |vpiFullName:work@oh_clockor |vpiParameter: \_parameter: (work@oh_clockor.N), line:9:15, endln:9:16 |vpiParent: - \_module: work@oh_clockor (work@oh_clockor), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockor.v, line:8:1, endln:31:10 + \_module_inst: work@oh_clockor (work@oh_clockor), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockor.v, line:8:1, endln:31:10 |UINT:2 |vpiTypespec: \_int_typespec: @@ -15004,7 +15004,7 @@ design: (work@oh_fifo_async) |vpiParameter: \_parameter: (work@oh_clockor.SYN), line:10:15, endln:10:18 |vpiParent: - \_module: work@oh_clockor (work@oh_clockor), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockor.v, line:8:1, endln:31:10 + \_module_inst: work@oh_clockor (work@oh_clockor), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockor.v, line:8:1, endln:31:10 |STRING:TRUE |vpiTypespec: \_string_typespec: @@ -15013,7 +15013,7 @@ design: (work@oh_fifo_async) |vpiParameter: \_parameter: (work@oh_clockor.TYPE), line:11:15, endln:11:19 |vpiParent: - \_module: work@oh_clockor (work@oh_clockor), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockor.v, line:8:1, endln:31:10 + \_module_inst: work@oh_clockor (work@oh_clockor), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockor.v, line:8:1, endln:31:10 |STRING:DEFAULT |vpiTypespec: \_string_typespec: @@ -15022,7 +15022,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:9:15, endln:9:23 |vpiParent: - \_module: work@oh_clockor (work@oh_clockor), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockor.v, line:8:1, endln:31:10 + \_module_inst: work@oh_clockor (work@oh_clockor), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockor.v, line:8:1, endln:31:10 |vpiRhs: \_constant: , line:9:22, endln:9:23 |vpiDecompile:2 @@ -15036,7 +15036,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:10:15, endln:10:28 |vpiParent: - \_module: work@oh_clockor (work@oh_clockor), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockor.v, line:8:1, endln:31:10 + \_module_inst: work@oh_clockor (work@oh_clockor), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockor.v, line:8:1, endln:31:10 |vpiRhs: \_constant: , line:10:22, endln:10:28 |vpiDecompile:TRUE @@ -15050,7 +15050,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:11:15, endln:11:31 |vpiParent: - \_module: work@oh_clockor (work@oh_clockor), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockor.v, line:8:1, endln:31:10 + \_module_inst: work@oh_clockor (work@oh_clockor), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockor.v, line:8:1, endln:31:10 |vpiRhs: \_constant: , line:11:22, endln:11:31 |vpiDecompile:DEFAULT @@ -15066,19 +15066,19 @@ design: (work@oh_fifo_async) |vpiNet: \_logic_net: (work@oh_clockor.clkin), line:14:19, endln:14:24 |vpiParent: - \_module: work@oh_clockor (work@oh_clockor), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockor.v, line:8:1, endln:31:10 + \_module_inst: work@oh_clockor (work@oh_clockor), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockor.v, line:8:1, endln:31:10 |vpiName:clkin |vpiFullName:work@oh_clockor.clkin |vpiNet: \_logic_net: (work@oh_clockor.clkout), line:15:15, endln:15:21 |vpiParent: - \_module: work@oh_clockor (work@oh_clockor), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockor.v, line:8:1, endln:31:10 + \_module_inst: work@oh_clockor (work@oh_clockor), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockor.v, line:8:1, endln:31:10 |vpiName:clkout |vpiFullName:work@oh_clockor.clkout |vpiPort: \_port: (clkin), line:14:19, endln:14:24 |vpiParent: - \_module: work@oh_clockor (work@oh_clockor), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockor.v, line:8:1, endln:31:10 + \_module_inst: work@oh_clockor (work@oh_clockor), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockor.v, line:8:1, endln:31:10 |vpiName:clkin |vpiDirection:1 |vpiLowConn: @@ -15118,7 +15118,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (clkout), line:15:15, endln:15:21 |vpiParent: - \_module: work@oh_clockor (work@oh_clockor), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockor.v, line:8:1, endln:31:10 + \_module_inst: work@oh_clockor (work@oh_clockor), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockor.v, line:8:1, endln:31:10 |vpiName:clkout |vpiDirection:2 |vpiLowConn: @@ -15128,14 +15128,14 @@ design: (work@oh_fifo_async) |vpiTypedef: \_logic_typespec: , line:15:15, endln:15:15 |uhdmallModules: -\_module: work@oh_counter (work@oh_counter), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_counter.v, line:8:1, endln:64:10 +\_module_inst: work@oh_counter (work@oh_counter), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_counter.v, line:8:1, endln:64:10 |vpiParent: \_design: (work@oh_fifo_async) |vpiFullName:work@oh_counter |vpiParameter: \_parameter: (work@oh_counter.N), line:9:15, endln:9:16 |vpiParent: - \_module: work@oh_counter (work@oh_counter), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_counter.v, line:8:1, endln:64:10 + \_module_inst: work@oh_counter (work@oh_counter), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_counter.v, line:8:1, endln:64:10 |UINT:32 |vpiTypespec: \_int_typespec: @@ -15144,7 +15144,7 @@ design: (work@oh_fifo_async) |vpiParameter: \_parameter: (work@oh_counter.SYN), line:10:15, endln:10:18 |vpiParent: - \_module: work@oh_counter (work@oh_counter), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_counter.v, line:8:1, endln:64:10 + \_module_inst: work@oh_counter (work@oh_counter), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_counter.v, line:8:1, endln:64:10 |STRING:TRUE |vpiTypespec: \_string_typespec: @@ -15153,7 +15153,7 @@ design: (work@oh_fifo_async) |vpiParameter: \_parameter: (work@oh_counter.TYPE), line:11:15, endln:11:19 |vpiParent: - \_module: work@oh_counter (work@oh_counter), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_counter.v, line:8:1, endln:64:10 + \_module_inst: work@oh_counter (work@oh_counter), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_counter.v, line:8:1, endln:64:10 |STRING:DEFAULT |vpiTypespec: \_string_typespec: @@ -15162,7 +15162,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:9:15, endln:9:23 |vpiParent: - \_module: work@oh_counter (work@oh_counter), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_counter.v, line:8:1, endln:64:10 + \_module_inst: work@oh_counter (work@oh_counter), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_counter.v, line:8:1, endln:64:10 |vpiRhs: \_constant: , line:9:21, endln:9:23 |vpiDecompile:32 @@ -15176,7 +15176,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:10:15, endln:10:27 |vpiParent: - \_module: work@oh_counter (work@oh_counter), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_counter.v, line:8:1, endln:64:10 + \_module_inst: work@oh_counter (work@oh_counter), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_counter.v, line:8:1, endln:64:10 |vpiRhs: \_constant: , line:10:21, endln:10:27 |vpiDecompile:TRUE @@ -15190,7 +15190,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:11:15, endln:11:31 |vpiParent: - \_module: work@oh_counter (work@oh_counter), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_counter.v, line:8:1, endln:64:10 + \_module_inst: work@oh_counter (work@oh_counter), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_counter.v, line:8:1, endln:64:10 |vpiRhs: \_constant: , line:11:22, endln:11:31 |vpiDecompile:DEFAULT @@ -15206,76 +15206,76 @@ design: (work@oh_fifo_async) |vpiNet: \_logic_net: (work@oh_counter.clk), line:15:19, endln:15:22 |vpiParent: - \_module: work@oh_counter (work@oh_counter), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_counter.v, line:8:1, endln:64:10 + \_module_inst: work@oh_counter (work@oh_counter), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_counter.v, line:8:1, endln:64:10 |vpiName:clk |vpiFullName:work@oh_counter.clk |vpiNet: \_logic_net: (work@oh_counter.in), line:16:19, endln:16:21 |vpiParent: - \_module: work@oh_counter (work@oh_counter), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_counter.v, line:8:1, endln:64:10 + \_module_inst: work@oh_counter (work@oh_counter), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_counter.v, line:8:1, endln:64:10 |vpiName:in |vpiFullName:work@oh_counter.in |vpiNet: \_logic_net: (work@oh_counter.en), line:17:19, endln:17:21 |vpiParent: - \_module: work@oh_counter (work@oh_counter), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_counter.v, line:8:1, endln:64:10 + \_module_inst: work@oh_counter (work@oh_counter), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_counter.v, line:8:1, endln:64:10 |vpiName:en |vpiFullName:work@oh_counter.en |vpiNet: \_logic_net: (work@oh_counter.dec), line:18:19, endln:18:22 |vpiParent: - \_module: work@oh_counter (work@oh_counter), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_counter.v, line:8:1, endln:64:10 + \_module_inst: work@oh_counter (work@oh_counter), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_counter.v, line:8:1, endln:64:10 |vpiName:dec |vpiFullName:work@oh_counter.dec |vpiNet: \_logic_net: (work@oh_counter.autowrap), line:19:19, endln:19:27 |vpiParent: - \_module: work@oh_counter (work@oh_counter), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_counter.v, line:8:1, endln:64:10 + \_module_inst: work@oh_counter (work@oh_counter), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_counter.v, line:8:1, endln:64:10 |vpiName:autowrap |vpiFullName:work@oh_counter.autowrap |vpiNet: \_logic_net: (work@oh_counter.load), line:20:19, endln:20:23 |vpiParent: - \_module: work@oh_counter (work@oh_counter), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_counter.v, line:8:1, endln:64:10 + \_module_inst: work@oh_counter (work@oh_counter), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_counter.v, line:8:1, endln:64:10 |vpiName:load |vpiFullName:work@oh_counter.load |vpiNet: \_logic_net: (work@oh_counter.load_data), line:21:24, endln:21:33 |vpiParent: - \_module: work@oh_counter (work@oh_counter), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_counter.v, line:8:1, endln:64:10 + \_module_inst: work@oh_counter (work@oh_counter), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_counter.v, line:8:1, endln:64:10 |vpiName:load_data |vpiFullName:work@oh_counter.load_data |vpiNet: \_logic_net: (work@oh_counter.count), line:23:24, endln:23:29 |vpiParent: - \_module: work@oh_counter (work@oh_counter), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_counter.v, line:8:1, endln:64:10 + \_module_inst: work@oh_counter (work@oh_counter), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_counter.v, line:8:1, endln:64:10 |vpiName:count |vpiFullName:work@oh_counter.count |vpiNetType:48 |vpiNet: \_logic_net: (work@oh_counter.wraparound), line:24:20, endln:24:30 |vpiParent: - \_module: work@oh_counter (work@oh_counter), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_counter.v, line:8:1, endln:64:10 + \_module_inst: work@oh_counter (work@oh_counter), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_counter.v, line:8:1, endln:64:10 |vpiName:wraparound |vpiFullName:work@oh_counter.wraparound |vpiNet: \_logic_net: (work@oh_counter.inb), line:27:18, endln:27:21 |vpiParent: - \_module: work@oh_counter (work@oh_counter), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_counter.v, line:8:1, endln:64:10 + \_module_inst: work@oh_counter (work@oh_counter), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_counter.v, line:8:1, endln:64:10 |vpiName:inb |vpiFullName:work@oh_counter.inb |vpiNetType:1 |vpiNet: \_logic_net: (work@oh_counter.count_in), line:28:18, endln:28:26 |vpiParent: - \_module: work@oh_counter (work@oh_counter), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_counter.v, line:8:1, endln:64:10 + \_module_inst: work@oh_counter (work@oh_counter), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_counter.v, line:8:1, endln:64:10 |vpiName:count_in |vpiFullName:work@oh_counter.count_in |vpiNetType:1 |vpiPort: \_port: (clk), line:15:19, endln:15:22 |vpiParent: - \_module: work@oh_counter (work@oh_counter), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_counter.v, line:8:1, endln:64:10 + \_module_inst: work@oh_counter (work@oh_counter), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_counter.v, line:8:1, endln:64:10 |vpiName:clk |vpiDirection:1 |vpiLowConn: @@ -15287,7 +15287,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (in), line:16:19, endln:16:21 |vpiParent: - \_module: work@oh_counter (work@oh_counter), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_counter.v, line:8:1, endln:64:10 + \_module_inst: work@oh_counter (work@oh_counter), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_counter.v, line:8:1, endln:64:10 |vpiName:in |vpiDirection:1 |vpiLowConn: @@ -15299,7 +15299,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (en), line:17:19, endln:17:21 |vpiParent: - \_module: work@oh_counter (work@oh_counter), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_counter.v, line:8:1, endln:64:10 + \_module_inst: work@oh_counter (work@oh_counter), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_counter.v, line:8:1, endln:64:10 |vpiName:en |vpiDirection:1 |vpiLowConn: @@ -15311,7 +15311,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (dec), line:18:19, endln:18:22 |vpiParent: - \_module: work@oh_counter (work@oh_counter), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_counter.v, line:8:1, endln:64:10 + \_module_inst: work@oh_counter (work@oh_counter), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_counter.v, line:8:1, endln:64:10 |vpiName:dec |vpiDirection:1 |vpiLowConn: @@ -15323,7 +15323,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (autowrap), line:19:19, endln:19:27 |vpiParent: - \_module: work@oh_counter (work@oh_counter), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_counter.v, line:8:1, endln:64:10 + \_module_inst: work@oh_counter (work@oh_counter), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_counter.v, line:8:1, endln:64:10 |vpiName:autowrap |vpiDirection:1 |vpiLowConn: @@ -15335,7 +15335,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (load), line:20:19, endln:20:23 |vpiParent: - \_module: work@oh_counter (work@oh_counter), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_counter.v, line:8:1, endln:64:10 + \_module_inst: work@oh_counter (work@oh_counter), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_counter.v, line:8:1, endln:64:10 |vpiName:load |vpiDirection:1 |vpiLowConn: @@ -15347,7 +15347,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (load_data), line:21:24, endln:21:33 |vpiParent: - \_module: work@oh_counter (work@oh_counter), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_counter.v, line:8:1, endln:64:10 + \_module_inst: work@oh_counter (work@oh_counter), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_counter.v, line:8:1, endln:64:10 |vpiName:load_data |vpiDirection:1 |vpiLowConn: @@ -15387,7 +15387,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (count), line:23:24, endln:23:29 |vpiParent: - \_module: work@oh_counter (work@oh_counter), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_counter.v, line:8:1, endln:64:10 + \_module_inst: work@oh_counter (work@oh_counter), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_counter.v, line:8:1, endln:64:10 |vpiName:count |vpiDirection:2 |vpiLowConn: @@ -15427,7 +15427,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (wraparound), line:24:20, endln:24:30 |vpiParent: - \_module: work@oh_counter (work@oh_counter), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_counter.v, line:8:1, endln:64:10 + \_module_inst: work@oh_counter (work@oh_counter), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_counter.v, line:8:1, endln:64:10 |vpiName:wraparound |vpiDirection:2 |vpiLowConn: @@ -15439,7 +15439,7 @@ design: (work@oh_fifo_async) |vpiProcess: \_always: , line:35:4, endln:39:40 |vpiParent: - \_module: work@oh_counter (work@oh_counter), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_counter.v, line:8:1, endln:64:10 + \_module_inst: work@oh_counter (work@oh_counter), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_counter.v, line:8:1, endln:64:10 |vpiStmt: \_event_control: , line:35:11, endln:35:25 |vpiParent: @@ -15661,7 +15661,7 @@ design: (work@oh_fifo_async) |vpiContAssign: \_cont_assign: , line:31:11, endln:31:70 |vpiParent: - \_module: work@oh_counter (work@oh_counter), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_counter.v, line:8:1, endln:64:10 + \_module_inst: work@oh_counter (work@oh_counter), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_counter.v, line:8:1, endln:64:10 |vpiRhs: \_operation: , line:31:24, endln:31:70 |vpiParent: @@ -15805,7 +15805,7 @@ design: (work@oh_fifo_async) |vpiContAssign: \_cont_assign: , line:32:11, endln:32:41 |vpiParent: - \_module: work@oh_counter (work@oh_counter), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_counter.v, line:8:1, endln:64:10 + \_module_inst: work@oh_counter (work@oh_counter), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_counter.v, line:8:1, endln:64:10 |vpiRhs: \_operation: , line:32:24, endln:32:41 |vpiParent: @@ -15842,7 +15842,7 @@ design: (work@oh_fifo_async) |vpiContAssign: \_cont_assign: , line:41:11, endln:42:39 |vpiParent: - \_module: work@oh_counter (work@oh_counter), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_counter.v, line:8:1, endln:64:10 + \_module_inst: work@oh_counter (work@oh_counter), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_counter.v, line:8:1, endln:64:10 |vpiRhs: \_operation: , line:41:24, endln:42:39 |vpiParent: @@ -15983,14 +15983,14 @@ design: (work@oh_fifo_async) |vpiName:wraparound |vpiFullName:work@oh_counter.wraparound |uhdmallModules: -\_module: work@oh_csa32 (work@oh_csa32), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa32.v, line:8:1, endln:40:10 +\_module_inst: work@oh_csa32 (work@oh_csa32), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa32.v, line:8:1, endln:40:10 |vpiParent: \_design: (work@oh_fifo_async) |vpiFullName:work@oh_csa32 |vpiParameter: \_parameter: (work@oh_csa32.N), line:9:15, endln:9:16 |vpiParent: - \_module: work@oh_csa32 (work@oh_csa32), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa32.v, line:8:1, endln:40:10 + \_module_inst: work@oh_csa32 (work@oh_csa32), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa32.v, line:8:1, endln:40:10 |UINT:1 |vpiTypespec: \_int_typespec: @@ -15999,7 +15999,7 @@ design: (work@oh_fifo_async) |vpiParameter: \_parameter: (work@oh_csa32.SYN), line:10:15, endln:10:18 |vpiParent: - \_module: work@oh_csa32 (work@oh_csa32), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa32.v, line:8:1, endln:40:10 + \_module_inst: work@oh_csa32 (work@oh_csa32), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa32.v, line:8:1, endln:40:10 |STRING:TRUE |vpiTypespec: \_string_typespec: @@ -16008,7 +16008,7 @@ design: (work@oh_fifo_async) |vpiParameter: \_parameter: (work@oh_csa32.TYPE), line:11:15, endln:11:19 |vpiParent: - \_module: work@oh_csa32 (work@oh_csa32), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa32.v, line:8:1, endln:40:10 + \_module_inst: work@oh_csa32 (work@oh_csa32), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa32.v, line:8:1, endln:40:10 |STRING:DEFAULT |vpiTypespec: \_string_typespec: @@ -16017,7 +16017,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:9:15, endln:9:23 |vpiParent: - \_module: work@oh_csa32 (work@oh_csa32), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa32.v, line:8:1, endln:40:10 + \_module_inst: work@oh_csa32 (work@oh_csa32), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa32.v, line:8:1, endln:40:10 |vpiRhs: \_constant: , line:9:22, endln:9:23 |vpiDecompile:1 @@ -16031,7 +16031,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:10:15, endln:10:28 |vpiParent: - \_module: work@oh_csa32 (work@oh_csa32), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa32.v, line:8:1, endln:40:10 + \_module_inst: work@oh_csa32 (work@oh_csa32), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa32.v, line:8:1, endln:40:10 |vpiRhs: \_constant: , line:10:22, endln:10:28 |vpiDecompile:TRUE @@ -16045,7 +16045,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:11:15, endln:11:31 |vpiParent: - \_module: work@oh_csa32 (work@oh_csa32), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa32.v, line:8:1, endln:40:10 + \_module_inst: work@oh_csa32 (work@oh_csa32), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa32.v, line:8:1, endln:40:10 |vpiRhs: \_constant: , line:11:22, endln:11:31 |vpiDecompile:DEFAULT @@ -16061,37 +16061,37 @@ design: (work@oh_fifo_async) |vpiNet: \_logic_net: (work@oh_csa32.in0), line:13:21, endln:13:24 |vpiParent: - \_module: work@oh_csa32 (work@oh_csa32), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa32.v, line:8:1, endln:40:10 + \_module_inst: work@oh_csa32 (work@oh_csa32), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa32.v, line:8:1, endln:40:10 |vpiName:in0 |vpiFullName:work@oh_csa32.in0 |vpiNet: \_logic_net: (work@oh_csa32.in1), line:14:21, endln:14:24 |vpiParent: - \_module: work@oh_csa32 (work@oh_csa32), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa32.v, line:8:1, endln:40:10 + \_module_inst: work@oh_csa32 (work@oh_csa32), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa32.v, line:8:1, endln:40:10 |vpiName:in1 |vpiFullName:work@oh_csa32.in1 |vpiNet: \_logic_net: (work@oh_csa32.in2), line:15:21, endln:15:24 |vpiParent: - \_module: work@oh_csa32 (work@oh_csa32), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa32.v, line:8:1, endln:40:10 + \_module_inst: work@oh_csa32 (work@oh_csa32), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa32.v, line:8:1, endln:40:10 |vpiName:in2 |vpiFullName:work@oh_csa32.in2 |vpiNet: \_logic_net: (work@oh_csa32.s), line:16:21, endln:16:22 |vpiParent: - \_module: work@oh_csa32 (work@oh_csa32), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa32.v, line:8:1, endln:40:10 + \_module_inst: work@oh_csa32 (work@oh_csa32), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa32.v, line:8:1, endln:40:10 |vpiName:s |vpiFullName:work@oh_csa32.s |vpiNet: \_logic_net: (work@oh_csa32.c), line:17:21, endln:17:22 |vpiParent: - \_module: work@oh_csa32 (work@oh_csa32), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa32.v, line:8:1, endln:40:10 + \_module_inst: work@oh_csa32 (work@oh_csa32), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa32.v, line:8:1, endln:40:10 |vpiName:c |vpiFullName:work@oh_csa32.c |vpiPort: \_port: (in0), line:13:21, endln:13:24 |vpiParent: - \_module: work@oh_csa32 (work@oh_csa32), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa32.v, line:8:1, endln:40:10 + \_module_inst: work@oh_csa32 (work@oh_csa32), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa32.v, line:8:1, endln:40:10 |vpiName:in0 |vpiDirection:1 |vpiLowConn: @@ -16131,7 +16131,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (in1), line:14:21, endln:14:24 |vpiParent: - \_module: work@oh_csa32 (work@oh_csa32), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa32.v, line:8:1, endln:40:10 + \_module_inst: work@oh_csa32 (work@oh_csa32), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa32.v, line:8:1, endln:40:10 |vpiName:in1 |vpiDirection:1 |vpiLowConn: @@ -16171,7 +16171,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (in2), line:15:21, endln:15:24 |vpiParent: - \_module: work@oh_csa32 (work@oh_csa32), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa32.v, line:8:1, endln:40:10 + \_module_inst: work@oh_csa32 (work@oh_csa32), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa32.v, line:8:1, endln:40:10 |vpiName:in2 |vpiDirection:1 |vpiLowConn: @@ -16211,7 +16211,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (s), line:16:21, endln:16:22 |vpiParent: - \_module: work@oh_csa32 (work@oh_csa32), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa32.v, line:8:1, endln:40:10 + \_module_inst: work@oh_csa32 (work@oh_csa32), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa32.v, line:8:1, endln:40:10 |vpiName:s |vpiDirection:2 |vpiLowConn: @@ -16251,7 +16251,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (c), line:17:21, endln:17:22 |vpiParent: - \_module: work@oh_csa32 (work@oh_csa32), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa32.v, line:8:1, endln:40:10 + \_module_inst: work@oh_csa32 (work@oh_csa32), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa32.v, line:8:1, endln:40:10 |vpiName:c |vpiDirection:2 |vpiLowConn: @@ -16289,14 +16289,14 @@ design: (work@oh_fifo_async) |UINT:0 |vpiConstType:9 |uhdmallModules: -\_module: work@oh_csa42 (work@oh_csa42), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa42.v, line:8:1, endln:77:10 +\_module_inst: work@oh_csa42 (work@oh_csa42), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa42.v, line:8:1, endln:77:10 |vpiParent: \_design: (work@oh_fifo_async) |vpiFullName:work@oh_csa42 |vpiParameter: \_parameter: (work@oh_csa42.N), line:9:15, endln:9:16 |vpiParent: - \_module: work@oh_csa42 (work@oh_csa42), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa42.v, line:8:1, endln:77:10 + \_module_inst: work@oh_csa42 (work@oh_csa42), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa42.v, line:8:1, endln:77:10 |UINT:1 |vpiTypespec: \_int_typespec: @@ -16305,7 +16305,7 @@ design: (work@oh_fifo_async) |vpiParameter: \_parameter: (work@oh_csa42.SYN), line:10:15, endln:10:18 |vpiParent: - \_module: work@oh_csa42 (work@oh_csa42), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa42.v, line:8:1, endln:77:10 + \_module_inst: work@oh_csa42 (work@oh_csa42), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa42.v, line:8:1, endln:77:10 |STRING:TRUE |vpiTypespec: \_string_typespec: @@ -16314,7 +16314,7 @@ design: (work@oh_fifo_async) |vpiParameter: \_parameter: (work@oh_csa42.TYPE), line:11:15, endln:11:19 |vpiParent: - \_module: work@oh_csa42 (work@oh_csa42), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa42.v, line:8:1, endln:77:10 + \_module_inst: work@oh_csa42 (work@oh_csa42), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa42.v, line:8:1, endln:77:10 |STRING:DEFAULT |vpiTypespec: \_string_typespec: @@ -16323,7 +16323,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:9:15, endln:9:23 |vpiParent: - \_module: work@oh_csa42 (work@oh_csa42), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa42.v, line:8:1, endln:77:10 + \_module_inst: work@oh_csa42 (work@oh_csa42), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa42.v, line:8:1, endln:77:10 |vpiRhs: \_constant: , line:9:22, endln:9:23 |vpiDecompile:1 @@ -16337,7 +16337,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:10:15, endln:10:28 |vpiParent: - \_module: work@oh_csa42 (work@oh_csa42), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa42.v, line:8:1, endln:77:10 + \_module_inst: work@oh_csa42 (work@oh_csa42), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa42.v, line:8:1, endln:77:10 |vpiRhs: \_constant: , line:10:22, endln:10:28 |vpiDecompile:TRUE @@ -16351,7 +16351,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:11:15, endln:11:31 |vpiParent: - \_module: work@oh_csa42 (work@oh_csa42), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa42.v, line:8:1, endln:77:10 + \_module_inst: work@oh_csa42 (work@oh_csa42), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa42.v, line:8:1, endln:77:10 |vpiRhs: \_constant: , line:11:22, endln:11:31 |vpiDecompile:DEFAULT @@ -16367,55 +16367,55 @@ design: (work@oh_fifo_async) |vpiNet: \_logic_net: (work@oh_csa42.in0), line:13:21, endln:13:24 |vpiParent: - \_module: work@oh_csa42 (work@oh_csa42), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa42.v, line:8:1, endln:77:10 + \_module_inst: work@oh_csa42 (work@oh_csa42), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa42.v, line:8:1, endln:77:10 |vpiName:in0 |vpiFullName:work@oh_csa42.in0 |vpiNet: \_logic_net: (work@oh_csa42.in1), line:14:21, endln:14:24 |vpiParent: - \_module: work@oh_csa42 (work@oh_csa42), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa42.v, line:8:1, endln:77:10 + \_module_inst: work@oh_csa42 (work@oh_csa42), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa42.v, line:8:1, endln:77:10 |vpiName:in1 |vpiFullName:work@oh_csa42.in1 |vpiNet: \_logic_net: (work@oh_csa42.in2), line:15:21, endln:15:24 |vpiParent: - \_module: work@oh_csa42 (work@oh_csa42), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa42.v, line:8:1, endln:77:10 + \_module_inst: work@oh_csa42 (work@oh_csa42), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa42.v, line:8:1, endln:77:10 |vpiName:in2 |vpiFullName:work@oh_csa42.in2 |vpiNet: \_logic_net: (work@oh_csa42.in3), line:16:21, endln:16:24 |vpiParent: - \_module: work@oh_csa42 (work@oh_csa42), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa42.v, line:8:1, endln:77:10 + \_module_inst: work@oh_csa42 (work@oh_csa42), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa42.v, line:8:1, endln:77:10 |vpiName:in3 |vpiFullName:work@oh_csa42.in3 |vpiNet: \_logic_net: (work@oh_csa42.cin), line:17:17, endln:17:20 |vpiParent: - \_module: work@oh_csa42 (work@oh_csa42), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa42.v, line:8:1, endln:77:10 + \_module_inst: work@oh_csa42 (work@oh_csa42), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa42.v, line:8:1, endln:77:10 |vpiName:cin |vpiFullName:work@oh_csa42.cin |vpiNet: \_logic_net: (work@oh_csa42.cout), line:18:18, endln:18:22 |vpiParent: - \_module: work@oh_csa42 (work@oh_csa42), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa42.v, line:8:1, endln:77:10 + \_module_inst: work@oh_csa42 (work@oh_csa42), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa42.v, line:8:1, endln:77:10 |vpiName:cout |vpiFullName:work@oh_csa42.cout |vpiNet: \_logic_net: (work@oh_csa42.s), line:19:21, endln:19:22 |vpiParent: - \_module: work@oh_csa42 (work@oh_csa42), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa42.v, line:8:1, endln:77:10 + \_module_inst: work@oh_csa42 (work@oh_csa42), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa42.v, line:8:1, endln:77:10 |vpiName:s |vpiFullName:work@oh_csa42.s |vpiNet: \_logic_net: (work@oh_csa42.c), line:20:21, endln:20:22 |vpiParent: - \_module: work@oh_csa42 (work@oh_csa42), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa42.v, line:8:1, endln:77:10 + \_module_inst: work@oh_csa42 (work@oh_csa42), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa42.v, line:8:1, endln:77:10 |vpiName:c |vpiFullName:work@oh_csa42.c |vpiPort: \_port: (in0), line:13:21, endln:13:24 |vpiParent: - \_module: work@oh_csa42 (work@oh_csa42), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa42.v, line:8:1, endln:77:10 + \_module_inst: work@oh_csa42 (work@oh_csa42), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa42.v, line:8:1, endln:77:10 |vpiName:in0 |vpiDirection:1 |vpiLowConn: @@ -16455,7 +16455,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (in1), line:14:21, endln:14:24 |vpiParent: - \_module: work@oh_csa42 (work@oh_csa42), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa42.v, line:8:1, endln:77:10 + \_module_inst: work@oh_csa42 (work@oh_csa42), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa42.v, line:8:1, endln:77:10 |vpiName:in1 |vpiDirection:1 |vpiLowConn: @@ -16495,7 +16495,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (in2), line:15:21, endln:15:24 |vpiParent: - \_module: work@oh_csa42 (work@oh_csa42), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa42.v, line:8:1, endln:77:10 + \_module_inst: work@oh_csa42 (work@oh_csa42), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa42.v, line:8:1, endln:77:10 |vpiName:in2 |vpiDirection:1 |vpiLowConn: @@ -16535,7 +16535,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (in3), line:16:21, endln:16:24 |vpiParent: - \_module: work@oh_csa42 (work@oh_csa42), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa42.v, line:8:1, endln:77:10 + \_module_inst: work@oh_csa42 (work@oh_csa42), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa42.v, line:8:1, endln:77:10 |vpiName:in3 |vpiDirection:1 |vpiLowConn: @@ -16575,7 +16575,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (cin), line:17:17, endln:17:20 |vpiParent: - \_module: work@oh_csa42 (work@oh_csa42), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa42.v, line:8:1, endln:77:10 + \_module_inst: work@oh_csa42 (work@oh_csa42), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa42.v, line:8:1, endln:77:10 |vpiName:cin |vpiDirection:1 |vpiLowConn: @@ -16587,7 +16587,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (cout), line:18:18, endln:18:22 |vpiParent: - \_module: work@oh_csa42 (work@oh_csa42), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa42.v, line:8:1, endln:77:10 + \_module_inst: work@oh_csa42 (work@oh_csa42), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa42.v, line:8:1, endln:77:10 |vpiName:cout |vpiDirection:2 |vpiLowConn: @@ -16599,7 +16599,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (s), line:19:21, endln:19:22 |vpiParent: - \_module: work@oh_csa42 (work@oh_csa42), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa42.v, line:8:1, endln:77:10 + \_module_inst: work@oh_csa42 (work@oh_csa42), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa42.v, line:8:1, endln:77:10 |vpiName:s |vpiDirection:2 |vpiLowConn: @@ -16639,7 +16639,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (c), line:20:21, endln:20:22 |vpiParent: - \_module: work@oh_csa42 (work@oh_csa42), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa42.v, line:8:1, endln:77:10 + \_module_inst: work@oh_csa42 (work@oh_csa42), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa42.v, line:8:1, endln:77:10 |vpiName:c |vpiDirection:2 |vpiLowConn: @@ -16677,14 +16677,14 @@ design: (work@oh_fifo_async) |UINT:0 |vpiConstType:9 |uhdmallModules: -\_module: work@oh_csa62 (work@oh_csa62), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa62.v, line:8:1, endln:62:10 +\_module_inst: work@oh_csa62 (work@oh_csa62), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa62.v, line:8:1, endln:62:10 |vpiParent: \_design: (work@oh_fifo_async) |vpiFullName:work@oh_csa62 |vpiParameter: \_parameter: (work@oh_csa62.N), line:9:15, endln:9:16 |vpiParent: - \_module: work@oh_csa62 (work@oh_csa62), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa62.v, line:8:1, endln:62:10 + \_module_inst: work@oh_csa62 (work@oh_csa62), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa62.v, line:8:1, endln:62:10 |UINT:1 |vpiTypespec: \_int_typespec: @@ -16693,7 +16693,7 @@ design: (work@oh_fifo_async) |vpiParameter: \_parameter: (work@oh_csa62.SYN), line:10:15, endln:10:18 |vpiParent: - \_module: work@oh_csa62 (work@oh_csa62), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa62.v, line:8:1, endln:62:10 + \_module_inst: work@oh_csa62 (work@oh_csa62), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa62.v, line:8:1, endln:62:10 |STRING:TRUE |vpiTypespec: \_string_typespec: @@ -16702,7 +16702,7 @@ design: (work@oh_fifo_async) |vpiParameter: \_parameter: (work@oh_csa62.TYPE), line:11:15, endln:11:19 |vpiParent: - \_module: work@oh_csa62 (work@oh_csa62), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa62.v, line:8:1, endln:62:10 + \_module_inst: work@oh_csa62 (work@oh_csa62), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa62.v, line:8:1, endln:62:10 |STRING:DEFAULT |vpiTypespec: \_string_typespec: @@ -16711,7 +16711,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:9:15, endln:9:23 |vpiParent: - \_module: work@oh_csa62 (work@oh_csa62), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa62.v, line:8:1, endln:62:10 + \_module_inst: work@oh_csa62 (work@oh_csa62), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa62.v, line:8:1, endln:62:10 |vpiRhs: \_constant: , line:9:22, endln:9:23 |vpiDecompile:1 @@ -16725,7 +16725,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:10:15, endln:10:28 |vpiParent: - \_module: work@oh_csa62 (work@oh_csa62), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa62.v, line:8:1, endln:62:10 + \_module_inst: work@oh_csa62 (work@oh_csa62), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa62.v, line:8:1, endln:62:10 |vpiRhs: \_constant: , line:10:22, endln:10:28 |vpiDecompile:TRUE @@ -16739,7 +16739,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:11:15, endln:11:31 |vpiParent: - \_module: work@oh_csa62 (work@oh_csa62), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa62.v, line:8:1, endln:62:10 + \_module_inst: work@oh_csa62 (work@oh_csa62), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa62.v, line:8:1, endln:62:10 |vpiRhs: \_constant: , line:11:22, endln:11:31 |vpiDecompile:DEFAULT @@ -16755,105 +16755,105 @@ design: (work@oh_fifo_async) |vpiNet: \_logic_net: (work@oh_csa62.in0), line:13:21, endln:13:24 |vpiParent: - \_module: work@oh_csa62 (work@oh_csa62), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa62.v, line:8:1, endln:62:10 + \_module_inst: work@oh_csa62 (work@oh_csa62), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa62.v, line:8:1, endln:62:10 |vpiName:in0 |vpiFullName:work@oh_csa62.in0 |vpiNet: \_logic_net: (work@oh_csa62.in1), line:14:21, endln:14:24 |vpiParent: - \_module: work@oh_csa62 (work@oh_csa62), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa62.v, line:8:1, endln:62:10 + \_module_inst: work@oh_csa62 (work@oh_csa62), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa62.v, line:8:1, endln:62:10 |vpiName:in1 |vpiFullName:work@oh_csa62.in1 |vpiNet: \_logic_net: (work@oh_csa62.in2), line:15:21, endln:15:24 |vpiParent: - \_module: work@oh_csa62 (work@oh_csa62), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa62.v, line:8:1, endln:62:10 + \_module_inst: work@oh_csa62 (work@oh_csa62), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa62.v, line:8:1, endln:62:10 |vpiName:in2 |vpiFullName:work@oh_csa62.in2 |vpiNet: \_logic_net: (work@oh_csa62.in3), line:16:21, endln:16:24 |vpiParent: - \_module: work@oh_csa62 (work@oh_csa62), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa62.v, line:8:1, endln:62:10 + \_module_inst: work@oh_csa62 (work@oh_csa62), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa62.v, line:8:1, endln:62:10 |vpiName:in3 |vpiFullName:work@oh_csa62.in3 |vpiNet: \_logic_net: (work@oh_csa62.in4), line:17:21, endln:17:24 |vpiParent: - \_module: work@oh_csa62 (work@oh_csa62), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa62.v, line:8:1, endln:62:10 + \_module_inst: work@oh_csa62 (work@oh_csa62), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa62.v, line:8:1, endln:62:10 |vpiName:in4 |vpiFullName:work@oh_csa62.in4 |vpiNet: \_logic_net: (work@oh_csa62.in5), line:18:21, endln:18:24 |vpiParent: - \_module: work@oh_csa62 (work@oh_csa62), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa62.v, line:8:1, endln:62:10 + \_module_inst: work@oh_csa62 (work@oh_csa62), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa62.v, line:8:1, endln:62:10 |vpiName:in5 |vpiFullName:work@oh_csa62.in5 |vpiNet: \_logic_net: (work@oh_csa62.cin0), line:19:21, endln:19:25 |vpiParent: - \_module: work@oh_csa62 (work@oh_csa62), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa62.v, line:8:1, endln:62:10 + \_module_inst: work@oh_csa62 (work@oh_csa62), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa62.v, line:8:1, endln:62:10 |vpiName:cin0 |vpiFullName:work@oh_csa62.cin0 |vpiNet: \_logic_net: (work@oh_csa62.cin1), line:20:21, endln:20:25 |vpiParent: - \_module: work@oh_csa62 (work@oh_csa62), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa62.v, line:8:1, endln:62:10 + \_module_inst: work@oh_csa62 (work@oh_csa62), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa62.v, line:8:1, endln:62:10 |vpiName:cin1 |vpiFullName:work@oh_csa62.cin1 |vpiNet: \_logic_net: (work@oh_csa62.cin2), line:21:21, endln:21:25 |vpiParent: - \_module: work@oh_csa62 (work@oh_csa62), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa62.v, line:8:1, endln:62:10 + \_module_inst: work@oh_csa62 (work@oh_csa62), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa62.v, line:8:1, endln:62:10 |vpiName:cin2 |vpiFullName:work@oh_csa62.cin2 |vpiNet: \_logic_net: (work@oh_csa62.s), line:22:21, endln:22:22 |vpiParent: - \_module: work@oh_csa62 (work@oh_csa62), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa62.v, line:8:1, endln:62:10 + \_module_inst: work@oh_csa62 (work@oh_csa62), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa62.v, line:8:1, endln:62:10 |vpiName:s |vpiFullName:work@oh_csa62.s |vpiNet: \_logic_net: (work@oh_csa62.c), line:23:21, endln:23:22 |vpiParent: - \_module: work@oh_csa62 (work@oh_csa62), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa62.v, line:8:1, endln:62:10 + \_module_inst: work@oh_csa62 (work@oh_csa62), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa62.v, line:8:1, endln:62:10 |vpiName:c |vpiFullName:work@oh_csa62.c |vpiNet: \_logic_net: (work@oh_csa62.cout0), line:24:21, endln:24:26 |vpiParent: - \_module: work@oh_csa62 (work@oh_csa62), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa62.v, line:8:1, endln:62:10 + \_module_inst: work@oh_csa62 (work@oh_csa62), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa62.v, line:8:1, endln:62:10 |vpiName:cout0 |vpiFullName:work@oh_csa62.cout0 |vpiNet: \_logic_net: (work@oh_csa62.cout1), line:25:21, endln:25:26 |vpiParent: - \_module: work@oh_csa62 (work@oh_csa62), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa62.v, line:8:1, endln:62:10 + \_module_inst: work@oh_csa62 (work@oh_csa62), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa62.v, line:8:1, endln:62:10 |vpiName:cout1 |vpiFullName:work@oh_csa62.cout1 |vpiNet: \_logic_net: (work@oh_csa62.cout2), line:26:21, endln:26:26 |vpiParent: - \_module: work@oh_csa62 (work@oh_csa62), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa62.v, line:8:1, endln:62:10 + \_module_inst: work@oh_csa62 (work@oh_csa62), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa62.v, line:8:1, endln:62:10 |vpiName:cout2 |vpiFullName:work@oh_csa62.cout2 |vpiNet: \_logic_net: (work@oh_csa62.s_int0), line:29:19, endln:29:25 |vpiParent: - \_module: work@oh_csa62 (work@oh_csa62), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa62.v, line:8:1, endln:62:10 + \_module_inst: work@oh_csa62 (work@oh_csa62), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa62.v, line:8:1, endln:62:10 |vpiName:s_int0 |vpiFullName:work@oh_csa62.s_int0 |vpiNetType:1 |vpiNet: \_logic_net: (work@oh_csa62.s_int1), line:30:19, endln:30:25 |vpiParent: - \_module: work@oh_csa62 (work@oh_csa62), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa62.v, line:8:1, endln:62:10 + \_module_inst: work@oh_csa62 (work@oh_csa62), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa62.v, line:8:1, endln:62:10 |vpiName:s_int1 |vpiFullName:work@oh_csa62.s_int1 |vpiNetType:1 |vpiPort: \_port: (in0), line:13:21, endln:13:24 |vpiParent: - \_module: work@oh_csa62 (work@oh_csa62), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa62.v, line:8:1, endln:62:10 + \_module_inst: work@oh_csa62 (work@oh_csa62), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa62.v, line:8:1, endln:62:10 |vpiName:in0 |vpiDirection:1 |vpiLowConn: @@ -16893,7 +16893,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (in1), line:14:21, endln:14:24 |vpiParent: - \_module: work@oh_csa62 (work@oh_csa62), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa62.v, line:8:1, endln:62:10 + \_module_inst: work@oh_csa62 (work@oh_csa62), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa62.v, line:8:1, endln:62:10 |vpiName:in1 |vpiDirection:1 |vpiLowConn: @@ -16933,7 +16933,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (in2), line:15:21, endln:15:24 |vpiParent: - \_module: work@oh_csa62 (work@oh_csa62), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa62.v, line:8:1, endln:62:10 + \_module_inst: work@oh_csa62 (work@oh_csa62), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa62.v, line:8:1, endln:62:10 |vpiName:in2 |vpiDirection:1 |vpiLowConn: @@ -16973,7 +16973,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (in3), line:16:21, endln:16:24 |vpiParent: - \_module: work@oh_csa62 (work@oh_csa62), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa62.v, line:8:1, endln:62:10 + \_module_inst: work@oh_csa62 (work@oh_csa62), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa62.v, line:8:1, endln:62:10 |vpiName:in3 |vpiDirection:1 |vpiLowConn: @@ -17013,7 +17013,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (in4), line:17:21, endln:17:24 |vpiParent: - \_module: work@oh_csa62 (work@oh_csa62), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa62.v, line:8:1, endln:62:10 + \_module_inst: work@oh_csa62 (work@oh_csa62), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa62.v, line:8:1, endln:62:10 |vpiName:in4 |vpiDirection:1 |vpiLowConn: @@ -17053,7 +17053,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (in5), line:18:21, endln:18:24 |vpiParent: - \_module: work@oh_csa62 (work@oh_csa62), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa62.v, line:8:1, endln:62:10 + \_module_inst: work@oh_csa62 (work@oh_csa62), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa62.v, line:8:1, endln:62:10 |vpiName:in5 |vpiDirection:1 |vpiLowConn: @@ -17093,7 +17093,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (cin0), line:19:21, endln:19:25 |vpiParent: - \_module: work@oh_csa62 (work@oh_csa62), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa62.v, line:8:1, endln:62:10 + \_module_inst: work@oh_csa62 (work@oh_csa62), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa62.v, line:8:1, endln:62:10 |vpiName:cin0 |vpiDirection:1 |vpiLowConn: @@ -17133,7 +17133,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (cin1), line:20:21, endln:20:25 |vpiParent: - \_module: work@oh_csa62 (work@oh_csa62), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa62.v, line:8:1, endln:62:10 + \_module_inst: work@oh_csa62 (work@oh_csa62), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa62.v, line:8:1, endln:62:10 |vpiName:cin1 |vpiDirection:1 |vpiLowConn: @@ -17173,7 +17173,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (cin2), line:21:21, endln:21:25 |vpiParent: - \_module: work@oh_csa62 (work@oh_csa62), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa62.v, line:8:1, endln:62:10 + \_module_inst: work@oh_csa62 (work@oh_csa62), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa62.v, line:8:1, endln:62:10 |vpiName:cin2 |vpiDirection:1 |vpiLowConn: @@ -17213,7 +17213,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (s), line:22:21, endln:22:22 |vpiParent: - \_module: work@oh_csa62 (work@oh_csa62), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa62.v, line:8:1, endln:62:10 + \_module_inst: work@oh_csa62 (work@oh_csa62), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa62.v, line:8:1, endln:62:10 |vpiName:s |vpiDirection:2 |vpiLowConn: @@ -17253,7 +17253,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (c), line:23:21, endln:23:22 |vpiParent: - \_module: work@oh_csa62 (work@oh_csa62), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa62.v, line:8:1, endln:62:10 + \_module_inst: work@oh_csa62 (work@oh_csa62), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa62.v, line:8:1, endln:62:10 |vpiName:c |vpiDirection:2 |vpiLowConn: @@ -17293,7 +17293,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (cout0), line:24:21, endln:24:26 |vpiParent: - \_module: work@oh_csa62 (work@oh_csa62), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa62.v, line:8:1, endln:62:10 + \_module_inst: work@oh_csa62 (work@oh_csa62), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa62.v, line:8:1, endln:62:10 |vpiName:cout0 |vpiDirection:2 |vpiLowConn: @@ -17333,7 +17333,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (cout1), line:25:21, endln:25:26 |vpiParent: - \_module: work@oh_csa62 (work@oh_csa62), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa62.v, line:8:1, endln:62:10 + \_module_inst: work@oh_csa62 (work@oh_csa62), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa62.v, line:8:1, endln:62:10 |vpiName:cout1 |vpiDirection:2 |vpiLowConn: @@ -17373,7 +17373,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (cout2), line:26:21, endln:26:26 |vpiParent: - \_module: work@oh_csa62 (work@oh_csa62), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa62.v, line:8:1, endln:62:10 + \_module_inst: work@oh_csa62 (work@oh_csa62), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa62.v, line:8:1, endln:62:10 |vpiName:cout2 |vpiDirection:2 |vpiLowConn: @@ -17411,14 +17411,14 @@ design: (work@oh_fifo_async) |UINT:0 |vpiConstType:9 |uhdmallModules: -\_module: work@oh_csa92 (work@oh_csa92), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa92.v, line:8:1, endln:88:10 +\_module_inst: work@oh_csa92 (work@oh_csa92), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa92.v, line:8:1, endln:88:10 |vpiParent: \_design: (work@oh_fifo_async) |vpiFullName:work@oh_csa92 |vpiParameter: \_parameter: (work@oh_csa92.N), line:9:15, endln:9:16 |vpiParent: - \_module: work@oh_csa92 (work@oh_csa92), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa92.v, line:8:1, endln:88:10 + \_module_inst: work@oh_csa92 (work@oh_csa92), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa92.v, line:8:1, endln:88:10 |UINT:1 |vpiTypespec: \_int_typespec: @@ -17427,7 +17427,7 @@ design: (work@oh_fifo_async) |vpiParameter: \_parameter: (work@oh_csa92.SYN), line:10:15, endln:10:18 |vpiParent: - \_module: work@oh_csa92 (work@oh_csa92), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa92.v, line:8:1, endln:88:10 + \_module_inst: work@oh_csa92 (work@oh_csa92), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa92.v, line:8:1, endln:88:10 |STRING:TRUE |vpiTypespec: \_string_typespec: @@ -17436,7 +17436,7 @@ design: (work@oh_fifo_async) |vpiParameter: \_parameter: (work@oh_csa92.TYPE), line:11:15, endln:11:19 |vpiParent: - \_module: work@oh_csa92 (work@oh_csa92), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa92.v, line:8:1, endln:88:10 + \_module_inst: work@oh_csa92 (work@oh_csa92), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa92.v, line:8:1, endln:88:10 |STRING:DEFAULT |vpiTypespec: \_string_typespec: @@ -17445,7 +17445,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:9:15, endln:9:23 |vpiParent: - \_module: work@oh_csa92 (work@oh_csa92), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa92.v, line:8:1, endln:88:10 + \_module_inst: work@oh_csa92 (work@oh_csa92), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa92.v, line:8:1, endln:88:10 |vpiRhs: \_constant: , line:9:22, endln:9:23 |vpiDecompile:1 @@ -17459,7 +17459,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:10:15, endln:10:28 |vpiParent: - \_module: work@oh_csa92 (work@oh_csa92), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa92.v, line:8:1, endln:88:10 + \_module_inst: work@oh_csa92 (work@oh_csa92), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa92.v, line:8:1, endln:88:10 |vpiRhs: \_constant: , line:10:22, endln:10:28 |vpiDecompile:TRUE @@ -17473,7 +17473,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:11:15, endln:11:31 |vpiParent: - \_module: work@oh_csa92 (work@oh_csa92), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa92.v, line:8:1, endln:88:10 + \_module_inst: work@oh_csa92 (work@oh_csa92), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa92.v, line:8:1, endln:88:10 |vpiRhs: \_constant: , line:11:22, endln:11:31 |vpiDecompile:DEFAULT @@ -17489,166 +17489,166 @@ design: (work@oh_fifo_async) |vpiNet: \_logic_net: (work@oh_csa92.in0), line:13:21, endln:13:24 |vpiParent: - \_module: work@oh_csa92 (work@oh_csa92), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa92.v, line:8:1, endln:88:10 + \_module_inst: work@oh_csa92 (work@oh_csa92), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa92.v, line:8:1, endln:88:10 |vpiName:in0 |vpiFullName:work@oh_csa92.in0 |vpiNet: \_logic_net: (work@oh_csa92.in1), line:14:21, endln:14:24 |vpiParent: - \_module: work@oh_csa92 (work@oh_csa92), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa92.v, line:8:1, endln:88:10 + \_module_inst: work@oh_csa92 (work@oh_csa92), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa92.v, line:8:1, endln:88:10 |vpiName:in1 |vpiFullName:work@oh_csa92.in1 |vpiNet: \_logic_net: (work@oh_csa92.in2), line:15:21, endln:15:24 |vpiParent: - \_module: work@oh_csa92 (work@oh_csa92), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa92.v, line:8:1, endln:88:10 + \_module_inst: work@oh_csa92 (work@oh_csa92), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa92.v, line:8:1, endln:88:10 |vpiName:in2 |vpiFullName:work@oh_csa92.in2 |vpiNet: \_logic_net: (work@oh_csa92.in3), line:16:21, endln:16:24 |vpiParent: - \_module: work@oh_csa92 (work@oh_csa92), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa92.v, line:8:1, endln:88:10 + \_module_inst: work@oh_csa92 (work@oh_csa92), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa92.v, line:8:1, endln:88:10 |vpiName:in3 |vpiFullName:work@oh_csa92.in3 |vpiNet: \_logic_net: (work@oh_csa92.in4), line:17:21, endln:17:24 |vpiParent: - \_module: work@oh_csa92 (work@oh_csa92), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa92.v, line:8:1, endln:88:10 + \_module_inst: work@oh_csa92 (work@oh_csa92), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa92.v, line:8:1, endln:88:10 |vpiName:in4 |vpiFullName:work@oh_csa92.in4 |vpiNet: \_logic_net: (work@oh_csa92.in5), line:18:21, endln:18:24 |vpiParent: - \_module: work@oh_csa92 (work@oh_csa92), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa92.v, line:8:1, endln:88:10 + \_module_inst: work@oh_csa92 (work@oh_csa92), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa92.v, line:8:1, endln:88:10 |vpiName:in5 |vpiFullName:work@oh_csa92.in5 |vpiNet: \_logic_net: (work@oh_csa92.in6), line:19:21, endln:19:24 |vpiParent: - \_module: work@oh_csa92 (work@oh_csa92), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa92.v, line:8:1, endln:88:10 + \_module_inst: work@oh_csa92 (work@oh_csa92), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa92.v, line:8:1, endln:88:10 |vpiName:in6 |vpiFullName:work@oh_csa92.in6 |vpiNet: \_logic_net: (work@oh_csa92.in7), line:20:21, endln:20:24 |vpiParent: - \_module: work@oh_csa92 (work@oh_csa92), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa92.v, line:8:1, endln:88:10 + \_module_inst: work@oh_csa92 (work@oh_csa92), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa92.v, line:8:1, endln:88:10 |vpiName:in7 |vpiFullName:work@oh_csa92.in7 |vpiNet: \_logic_net: (work@oh_csa92.in8), line:21:21, endln:21:24 |vpiParent: - \_module: work@oh_csa92 (work@oh_csa92), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa92.v, line:8:1, endln:88:10 + \_module_inst: work@oh_csa92 (work@oh_csa92), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa92.v, line:8:1, endln:88:10 |vpiName:in8 |vpiFullName:work@oh_csa92.in8 |vpiNet: \_logic_net: (work@oh_csa92.cin0), line:22:21, endln:22:25 |vpiParent: - \_module: work@oh_csa92 (work@oh_csa92), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa92.v, line:8:1, endln:88:10 + \_module_inst: work@oh_csa92 (work@oh_csa92), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa92.v, line:8:1, endln:88:10 |vpiName:cin0 |vpiFullName:work@oh_csa92.cin0 |vpiNet: \_logic_net: (work@oh_csa92.cin1), line:23:21, endln:23:25 |vpiParent: - \_module: work@oh_csa92 (work@oh_csa92), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa92.v, line:8:1, endln:88:10 + \_module_inst: work@oh_csa92 (work@oh_csa92), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa92.v, line:8:1, endln:88:10 |vpiName:cin1 |vpiFullName:work@oh_csa92.cin1 |vpiNet: \_logic_net: (work@oh_csa92.cin2), line:24:21, endln:24:25 |vpiParent: - \_module: work@oh_csa92 (work@oh_csa92), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa92.v, line:8:1, endln:88:10 + \_module_inst: work@oh_csa92 (work@oh_csa92), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa92.v, line:8:1, endln:88:10 |vpiName:cin2 |vpiFullName:work@oh_csa92.cin2 |vpiNet: \_logic_net: (work@oh_csa92.cin3), line:25:21, endln:25:25 |vpiParent: - \_module: work@oh_csa92 (work@oh_csa92), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa92.v, line:8:1, endln:88:10 + \_module_inst: work@oh_csa92 (work@oh_csa92), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa92.v, line:8:1, endln:88:10 |vpiName:cin3 |vpiFullName:work@oh_csa92.cin3 |vpiNet: \_logic_net: (work@oh_csa92.cin4), line:26:21, endln:26:25 |vpiParent: - \_module: work@oh_csa92 (work@oh_csa92), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa92.v, line:8:1, endln:88:10 + \_module_inst: work@oh_csa92 (work@oh_csa92), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa92.v, line:8:1, endln:88:10 |vpiName:cin4 |vpiFullName:work@oh_csa92.cin4 |vpiNet: \_logic_net: (work@oh_csa92.cin5), line:27:21, endln:27:25 |vpiParent: - \_module: work@oh_csa92 (work@oh_csa92), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa92.v, line:8:1, endln:88:10 + \_module_inst: work@oh_csa92 (work@oh_csa92), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa92.v, line:8:1, endln:88:10 |vpiName:cin5 |vpiFullName:work@oh_csa92.cin5 |vpiNet: \_logic_net: (work@oh_csa92.s), line:28:21, endln:28:22 |vpiParent: - \_module: work@oh_csa92 (work@oh_csa92), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa92.v, line:8:1, endln:88:10 + \_module_inst: work@oh_csa92 (work@oh_csa92), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa92.v, line:8:1, endln:88:10 |vpiName:s |vpiFullName:work@oh_csa92.s |vpiNet: \_logic_net: (work@oh_csa92.c), line:29:21, endln:29:22 |vpiParent: - \_module: work@oh_csa92 (work@oh_csa92), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa92.v, line:8:1, endln:88:10 + \_module_inst: work@oh_csa92 (work@oh_csa92), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa92.v, line:8:1, endln:88:10 |vpiName:c |vpiFullName:work@oh_csa92.c |vpiNet: \_logic_net: (work@oh_csa92.cout0), line:30:21, endln:30:26 |vpiParent: - \_module: work@oh_csa92 (work@oh_csa92), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa92.v, line:8:1, endln:88:10 + \_module_inst: work@oh_csa92 (work@oh_csa92), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa92.v, line:8:1, endln:88:10 |vpiName:cout0 |vpiFullName:work@oh_csa92.cout0 |vpiNet: \_logic_net: (work@oh_csa92.cout1), line:31:21, endln:31:26 |vpiParent: - \_module: work@oh_csa92 (work@oh_csa92), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa92.v, line:8:1, endln:88:10 + \_module_inst: work@oh_csa92 (work@oh_csa92), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa92.v, line:8:1, endln:88:10 |vpiName:cout1 |vpiFullName:work@oh_csa92.cout1 |vpiNet: \_logic_net: (work@oh_csa92.cout2), line:32:21, endln:32:26 |vpiParent: - \_module: work@oh_csa92 (work@oh_csa92), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa92.v, line:8:1, endln:88:10 + \_module_inst: work@oh_csa92 (work@oh_csa92), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa92.v, line:8:1, endln:88:10 |vpiName:cout2 |vpiFullName:work@oh_csa92.cout2 |vpiNet: \_logic_net: (work@oh_csa92.cout3), line:33:21, endln:33:26 |vpiParent: - \_module: work@oh_csa92 (work@oh_csa92), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa92.v, line:8:1, endln:88:10 + \_module_inst: work@oh_csa92 (work@oh_csa92), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa92.v, line:8:1, endln:88:10 |vpiName:cout3 |vpiFullName:work@oh_csa92.cout3 |vpiNet: \_logic_net: (work@oh_csa92.cout4), line:34:21, endln:34:26 |vpiParent: - \_module: work@oh_csa92 (work@oh_csa92), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa92.v, line:8:1, endln:88:10 + \_module_inst: work@oh_csa92 (work@oh_csa92), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa92.v, line:8:1, endln:88:10 |vpiName:cout4 |vpiFullName:work@oh_csa92.cout4 |vpiNet: \_logic_net: (work@oh_csa92.cout5), line:35:21, endln:35:26 |vpiParent: - \_module: work@oh_csa92 (work@oh_csa92), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa92.v, line:8:1, endln:88:10 + \_module_inst: work@oh_csa92 (work@oh_csa92), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa92.v, line:8:1, endln:88:10 |vpiName:cout5 |vpiFullName:work@oh_csa92.cout5 |vpiNet: \_logic_net: (work@oh_csa92.s_int0), line:39:21, endln:39:27 |vpiParent: - \_module: work@oh_csa92 (work@oh_csa92), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa92.v, line:8:1, endln:88:10 + \_module_inst: work@oh_csa92 (work@oh_csa92), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa92.v, line:8:1, endln:88:10 |vpiName:s_int0 |vpiFullName:work@oh_csa92.s_int0 |vpiNetType:1 |vpiNet: \_logic_net: (work@oh_csa92.s_int1), line:40:21, endln:40:27 |vpiParent: - \_module: work@oh_csa92 (work@oh_csa92), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa92.v, line:8:1, endln:88:10 + \_module_inst: work@oh_csa92 (work@oh_csa92), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa92.v, line:8:1, endln:88:10 |vpiName:s_int1 |vpiFullName:work@oh_csa92.s_int1 |vpiNetType:1 |vpiNet: \_logic_net: (work@oh_csa92.s_int2), line:41:21, endln:41:27 |vpiParent: - \_module: work@oh_csa92 (work@oh_csa92), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa92.v, line:8:1, endln:88:10 + \_module_inst: work@oh_csa92 (work@oh_csa92), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa92.v, line:8:1, endln:88:10 |vpiName:s_int2 |vpiFullName:work@oh_csa92.s_int2 |vpiNetType:1 |vpiPort: \_port: (in0), line:13:21, endln:13:24 |vpiParent: - \_module: work@oh_csa92 (work@oh_csa92), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa92.v, line:8:1, endln:88:10 + \_module_inst: work@oh_csa92 (work@oh_csa92), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa92.v, line:8:1, endln:88:10 |vpiName:in0 |vpiDirection:1 |vpiLowConn: @@ -17688,7 +17688,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (in1), line:14:21, endln:14:24 |vpiParent: - \_module: work@oh_csa92 (work@oh_csa92), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa92.v, line:8:1, endln:88:10 + \_module_inst: work@oh_csa92 (work@oh_csa92), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa92.v, line:8:1, endln:88:10 |vpiName:in1 |vpiDirection:1 |vpiLowConn: @@ -17728,7 +17728,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (in2), line:15:21, endln:15:24 |vpiParent: - \_module: work@oh_csa92 (work@oh_csa92), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa92.v, line:8:1, endln:88:10 + \_module_inst: work@oh_csa92 (work@oh_csa92), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa92.v, line:8:1, endln:88:10 |vpiName:in2 |vpiDirection:1 |vpiLowConn: @@ -17768,7 +17768,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (in3), line:16:21, endln:16:24 |vpiParent: - \_module: work@oh_csa92 (work@oh_csa92), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa92.v, line:8:1, endln:88:10 + \_module_inst: work@oh_csa92 (work@oh_csa92), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa92.v, line:8:1, endln:88:10 |vpiName:in3 |vpiDirection:1 |vpiLowConn: @@ -17808,7 +17808,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (in4), line:17:21, endln:17:24 |vpiParent: - \_module: work@oh_csa92 (work@oh_csa92), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa92.v, line:8:1, endln:88:10 + \_module_inst: work@oh_csa92 (work@oh_csa92), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa92.v, line:8:1, endln:88:10 |vpiName:in4 |vpiDirection:1 |vpiLowConn: @@ -17848,7 +17848,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (in5), line:18:21, endln:18:24 |vpiParent: - \_module: work@oh_csa92 (work@oh_csa92), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa92.v, line:8:1, endln:88:10 + \_module_inst: work@oh_csa92 (work@oh_csa92), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa92.v, line:8:1, endln:88:10 |vpiName:in5 |vpiDirection:1 |vpiLowConn: @@ -17888,7 +17888,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (in6), line:19:21, endln:19:24 |vpiParent: - \_module: work@oh_csa92 (work@oh_csa92), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa92.v, line:8:1, endln:88:10 + \_module_inst: work@oh_csa92 (work@oh_csa92), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa92.v, line:8:1, endln:88:10 |vpiName:in6 |vpiDirection:1 |vpiLowConn: @@ -17928,7 +17928,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (in7), line:20:21, endln:20:24 |vpiParent: - \_module: work@oh_csa92 (work@oh_csa92), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa92.v, line:8:1, endln:88:10 + \_module_inst: work@oh_csa92 (work@oh_csa92), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa92.v, line:8:1, endln:88:10 |vpiName:in7 |vpiDirection:1 |vpiLowConn: @@ -17968,7 +17968,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (in8), line:21:21, endln:21:24 |vpiParent: - \_module: work@oh_csa92 (work@oh_csa92), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa92.v, line:8:1, endln:88:10 + \_module_inst: work@oh_csa92 (work@oh_csa92), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa92.v, line:8:1, endln:88:10 |vpiName:in8 |vpiDirection:1 |vpiLowConn: @@ -18008,7 +18008,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (cin0), line:22:21, endln:22:25 |vpiParent: - \_module: work@oh_csa92 (work@oh_csa92), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa92.v, line:8:1, endln:88:10 + \_module_inst: work@oh_csa92 (work@oh_csa92), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa92.v, line:8:1, endln:88:10 |vpiName:cin0 |vpiDirection:1 |vpiLowConn: @@ -18048,7 +18048,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (cin1), line:23:21, endln:23:25 |vpiParent: - \_module: work@oh_csa92 (work@oh_csa92), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa92.v, line:8:1, endln:88:10 + \_module_inst: work@oh_csa92 (work@oh_csa92), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa92.v, line:8:1, endln:88:10 |vpiName:cin1 |vpiDirection:1 |vpiLowConn: @@ -18088,7 +18088,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (cin2), line:24:21, endln:24:25 |vpiParent: - \_module: work@oh_csa92 (work@oh_csa92), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa92.v, line:8:1, endln:88:10 + \_module_inst: work@oh_csa92 (work@oh_csa92), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa92.v, line:8:1, endln:88:10 |vpiName:cin2 |vpiDirection:1 |vpiLowConn: @@ -18128,7 +18128,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (cin3), line:25:21, endln:25:25 |vpiParent: - \_module: work@oh_csa92 (work@oh_csa92), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa92.v, line:8:1, endln:88:10 + \_module_inst: work@oh_csa92 (work@oh_csa92), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa92.v, line:8:1, endln:88:10 |vpiName:cin3 |vpiDirection:1 |vpiLowConn: @@ -18168,7 +18168,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (cin4), line:26:21, endln:26:25 |vpiParent: - \_module: work@oh_csa92 (work@oh_csa92), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa92.v, line:8:1, endln:88:10 + \_module_inst: work@oh_csa92 (work@oh_csa92), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa92.v, line:8:1, endln:88:10 |vpiName:cin4 |vpiDirection:1 |vpiLowConn: @@ -18208,7 +18208,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (cin5), line:27:21, endln:27:25 |vpiParent: - \_module: work@oh_csa92 (work@oh_csa92), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa92.v, line:8:1, endln:88:10 + \_module_inst: work@oh_csa92 (work@oh_csa92), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa92.v, line:8:1, endln:88:10 |vpiName:cin5 |vpiDirection:1 |vpiLowConn: @@ -18248,7 +18248,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (s), line:28:21, endln:28:22 |vpiParent: - \_module: work@oh_csa92 (work@oh_csa92), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa92.v, line:8:1, endln:88:10 + \_module_inst: work@oh_csa92 (work@oh_csa92), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa92.v, line:8:1, endln:88:10 |vpiName:s |vpiDirection:2 |vpiLowConn: @@ -18288,7 +18288,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (c), line:29:21, endln:29:22 |vpiParent: - \_module: work@oh_csa92 (work@oh_csa92), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa92.v, line:8:1, endln:88:10 + \_module_inst: work@oh_csa92 (work@oh_csa92), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa92.v, line:8:1, endln:88:10 |vpiName:c |vpiDirection:2 |vpiLowConn: @@ -18328,7 +18328,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (cout0), line:30:21, endln:30:26 |vpiParent: - \_module: work@oh_csa92 (work@oh_csa92), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa92.v, line:8:1, endln:88:10 + \_module_inst: work@oh_csa92 (work@oh_csa92), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa92.v, line:8:1, endln:88:10 |vpiName:cout0 |vpiDirection:2 |vpiLowConn: @@ -18368,7 +18368,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (cout1), line:31:21, endln:31:26 |vpiParent: - \_module: work@oh_csa92 (work@oh_csa92), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa92.v, line:8:1, endln:88:10 + \_module_inst: work@oh_csa92 (work@oh_csa92), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa92.v, line:8:1, endln:88:10 |vpiName:cout1 |vpiDirection:2 |vpiLowConn: @@ -18408,7 +18408,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (cout2), line:32:21, endln:32:26 |vpiParent: - \_module: work@oh_csa92 (work@oh_csa92), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa92.v, line:8:1, endln:88:10 + \_module_inst: work@oh_csa92 (work@oh_csa92), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa92.v, line:8:1, endln:88:10 |vpiName:cout2 |vpiDirection:2 |vpiLowConn: @@ -18448,7 +18448,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (cout3), line:33:21, endln:33:26 |vpiParent: - \_module: work@oh_csa92 (work@oh_csa92), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa92.v, line:8:1, endln:88:10 + \_module_inst: work@oh_csa92 (work@oh_csa92), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa92.v, line:8:1, endln:88:10 |vpiName:cout3 |vpiDirection:2 |vpiLowConn: @@ -18488,7 +18488,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (cout4), line:34:21, endln:34:26 |vpiParent: - \_module: work@oh_csa92 (work@oh_csa92), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa92.v, line:8:1, endln:88:10 + \_module_inst: work@oh_csa92 (work@oh_csa92), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa92.v, line:8:1, endln:88:10 |vpiName:cout4 |vpiDirection:2 |vpiLowConn: @@ -18528,7 +18528,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (cout5), line:35:21, endln:35:26 |vpiParent: - \_module: work@oh_csa92 (work@oh_csa92), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa92.v, line:8:1, endln:88:10 + \_module_inst: work@oh_csa92 (work@oh_csa92), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa92.v, line:8:1, endln:88:10 |vpiName:cout5 |vpiDirection:2 |vpiLowConn: @@ -18566,14 +18566,14 @@ design: (work@oh_fifo_async) |UINT:0 |vpiConstType:9 |uhdmallModules: -\_module: work@oh_datagate (work@oh_datagate), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_datagate.v, line:9:1, endln:49:10 +\_module_inst: work@oh_datagate (work@oh_datagate), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_datagate.v, line:9:1, endln:49:10 |vpiParent: \_design: (work@oh_fifo_async) |vpiFullName:work@oh_datagate |vpiParameter: \_parameter: (work@oh_datagate.N), line:10:15, endln:10:16 |vpiParent: - \_module: work@oh_datagate (work@oh_datagate), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_datagate.v, line:9:1, endln:49:10 + \_module_inst: work@oh_datagate (work@oh_datagate), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_datagate.v, line:9:1, endln:49:10 |UINT:2 |vpiTypespec: \_int_typespec: @@ -18582,7 +18582,7 @@ design: (work@oh_fifo_async) |vpiParameter: \_parameter: (work@oh_datagate.SYN), line:11:15, endln:11:18 |vpiParent: - \_module: work@oh_datagate (work@oh_datagate), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_datagate.v, line:9:1, endln:49:10 + \_module_inst: work@oh_datagate (work@oh_datagate), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_datagate.v, line:9:1, endln:49:10 |STRING:TRUE |vpiTypespec: \_string_typespec: @@ -18591,7 +18591,7 @@ design: (work@oh_fifo_async) |vpiParameter: \_parameter: (work@oh_datagate.TYPE), line:12:15, endln:12:19 |vpiParent: - \_module: work@oh_datagate (work@oh_datagate), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_datagate.v, line:9:1, endln:49:10 + \_module_inst: work@oh_datagate (work@oh_datagate), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_datagate.v, line:9:1, endln:49:10 |STRING:DEFAULT |vpiTypespec: \_string_typespec: @@ -18600,7 +18600,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:10:15, endln:10:23 |vpiParent: - \_module: work@oh_datagate (work@oh_datagate), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_datagate.v, line:9:1, endln:49:10 + \_module_inst: work@oh_datagate (work@oh_datagate), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_datagate.v, line:9:1, endln:49:10 |vpiRhs: \_constant: , line:10:22, endln:10:23 |vpiDecompile:2 @@ -18614,7 +18614,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:11:15, endln:11:28 |vpiParent: - \_module: work@oh_datagate (work@oh_datagate), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_datagate.v, line:9:1, endln:49:10 + \_module_inst: work@oh_datagate (work@oh_datagate), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_datagate.v, line:9:1, endln:49:10 |vpiRhs: \_constant: , line:11:22, endln:11:28 |vpiDecompile:TRUE @@ -18628,7 +18628,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:12:15, endln:12:31 |vpiParent: - \_module: work@oh_datagate (work@oh_datagate), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_datagate.v, line:9:1, endln:49:10 + \_module_inst: work@oh_datagate (work@oh_datagate), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_datagate.v, line:9:1, endln:49:10 |vpiRhs: \_constant: , line:12:22, endln:12:31 |vpiDecompile:DEFAULT @@ -18644,31 +18644,31 @@ design: (work@oh_fifo_async) |vpiNet: \_logic_net: (work@oh_datagate.clk), line:15:15, endln:15:18 |vpiParent: - \_module: work@oh_datagate (work@oh_datagate), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_datagate.v, line:9:1, endln:49:10 + \_module_inst: work@oh_datagate (work@oh_datagate), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_datagate.v, line:9:1, endln:49:10 |vpiName:clk |vpiFullName:work@oh_datagate.clk |vpiNet: \_logic_net: (work@oh_datagate.en), line:16:15, endln:16:17 |vpiParent: - \_module: work@oh_datagate (work@oh_datagate), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_datagate.v, line:9:1, endln:49:10 + \_module_inst: work@oh_datagate (work@oh_datagate), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_datagate.v, line:9:1, endln:49:10 |vpiName:en |vpiFullName:work@oh_datagate.en |vpiNet: \_logic_net: (work@oh_datagate.in), line:17:20, endln:17:22 |vpiParent: - \_module: work@oh_datagate (work@oh_datagate), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_datagate.v, line:9:1, endln:49:10 + \_module_inst: work@oh_datagate (work@oh_datagate), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_datagate.v, line:9:1, endln:49:10 |vpiName:in |vpiFullName:work@oh_datagate.in |vpiNet: \_logic_net: (work@oh_datagate.out), line:18:20, endln:18:23 |vpiParent: - \_module: work@oh_datagate (work@oh_datagate), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_datagate.v, line:9:1, endln:49:10 + \_module_inst: work@oh_datagate (work@oh_datagate), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_datagate.v, line:9:1, endln:49:10 |vpiName:out |vpiFullName:work@oh_datagate.out |vpiPort: \_port: (clk), line:15:15, endln:15:18 |vpiParent: - \_module: work@oh_datagate (work@oh_datagate), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_datagate.v, line:9:1, endln:49:10 + \_module_inst: work@oh_datagate (work@oh_datagate), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_datagate.v, line:9:1, endln:49:10 |vpiName:clk |vpiDirection:1 |vpiLowConn: @@ -18680,7 +18680,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (en), line:16:15, endln:16:17 |vpiParent: - \_module: work@oh_datagate (work@oh_datagate), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_datagate.v, line:9:1, endln:49:10 + \_module_inst: work@oh_datagate (work@oh_datagate), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_datagate.v, line:9:1, endln:49:10 |vpiName:en |vpiDirection:1 |vpiLowConn: @@ -18692,7 +18692,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (in), line:17:20, endln:17:22 |vpiParent: - \_module: work@oh_datagate (work@oh_datagate), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_datagate.v, line:9:1, endln:49:10 + \_module_inst: work@oh_datagate (work@oh_datagate), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_datagate.v, line:9:1, endln:49:10 |vpiName:in |vpiDirection:1 |vpiLowConn: @@ -18732,7 +18732,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (out), line:18:20, endln:18:23 |vpiParent: - \_module: work@oh_datagate (work@oh_datagate), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_datagate.v, line:9:1, endln:49:10 + \_module_inst: work@oh_datagate (work@oh_datagate), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_datagate.v, line:9:1, endln:49:10 |vpiName:out |vpiDirection:2 |vpiLowConn: @@ -18770,14 +18770,14 @@ design: (work@oh_fifo_async) |UINT:0 |vpiConstType:9 |uhdmallModules: -\_module: work@oh_debouncer (work@oh_debouncer), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_debouncer.v, line:8:1, endln:77:10 +\_module_inst: work@oh_debouncer (work@oh_debouncer), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_debouncer.v, line:8:1, endln:77:10 |vpiParent: \_design: (work@oh_fifo_async) |vpiFullName:work@oh_debouncer |vpiParameter: \_parameter: (work@oh_debouncer.BOUNCE), line:9:16, endln:9:22 |vpiParent: - \_module: work@oh_debouncer (work@oh_debouncer), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_debouncer.v, line:8:1, endln:77:10 + \_module_inst: work@oh_debouncer (work@oh_debouncer), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_debouncer.v, line:8:1, endln:77:10 |UINT:100 |vpiTypespec: \_int_typespec: @@ -18786,7 +18786,7 @@ design: (work@oh_fifo_async) |vpiParameter: \_parameter: (work@oh_debouncer.FREQUENCY), line:10:16, endln:10:25 |vpiParent: - \_module: work@oh_debouncer (work@oh_debouncer), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_debouncer.v, line:8:1, endln:77:10 + \_module_inst: work@oh_debouncer (work@oh_debouncer), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_debouncer.v, line:8:1, endln:77:10 |UINT:1000000 |vpiTypespec: \_int_typespec: @@ -18795,7 +18795,7 @@ design: (work@oh_fifo_async) |vpiParameter: \_parameter: (work@oh_debouncer.SYN), line:11:16, endln:11:19 |vpiParent: - \_module: work@oh_debouncer (work@oh_debouncer), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_debouncer.v, line:8:1, endln:77:10 + \_module_inst: work@oh_debouncer (work@oh_debouncer), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_debouncer.v, line:8:1, endln:77:10 |STRING:TRUE |vpiTypespec: \_string_typespec: @@ -18804,7 +18804,7 @@ design: (work@oh_fifo_async) |vpiParameter: \_parameter: (work@oh_debouncer.TYPE), line:12:16, endln:12:20 |vpiParent: - \_module: work@oh_debouncer (work@oh_debouncer), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_debouncer.v, line:8:1, endln:77:10 + \_module_inst: work@oh_debouncer (work@oh_debouncer), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_debouncer.v, line:8:1, endln:77:10 |STRING:DEFAULT |vpiTypespec: \_string_typespec: @@ -18813,7 +18813,7 @@ design: (work@oh_fifo_async) |vpiParameter: \_parameter: (work@oh_debouncer.COUNTER_WIDTH), line:21:22, endln:21:35 |vpiParent: - \_module: work@oh_debouncer (work@oh_debouncer), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_debouncer.v, line:8:1, endln:77:10 + \_module_inst: work@oh_debouncer (work@oh_debouncer), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_debouncer.v, line:8:1, endln:77:10 |vpiTypespec: \_integer_typespec: , line:21:14, endln:21:21 |vpiParent: @@ -18825,7 +18825,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:9:16, endln:9:31 |vpiParent: - \_module: work@oh_debouncer (work@oh_debouncer), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_debouncer.v, line:8:1, endln:77:10 + \_module_inst: work@oh_debouncer (work@oh_debouncer), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_debouncer.v, line:8:1, endln:77:10 |vpiRhs: \_constant: , line:9:28, endln:9:31 |vpiDecompile:100 @@ -18839,7 +18839,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:10:16, endln:10:35 |vpiParent: - \_module: work@oh_debouncer (work@oh_debouncer), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_debouncer.v, line:8:1, endln:77:10 + \_module_inst: work@oh_debouncer (work@oh_debouncer), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_debouncer.v, line:8:1, endln:77:10 |vpiRhs: \_constant: , line:10:28, endln:10:35 |vpiDecompile:1000000 @@ -18853,7 +18853,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:11:16, endln:11:34 |vpiParent: - \_module: work@oh_debouncer (work@oh_debouncer), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_debouncer.v, line:8:1, endln:77:10 + \_module_inst: work@oh_debouncer (work@oh_debouncer), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_debouncer.v, line:8:1, endln:77:10 |vpiRhs: \_constant: , line:11:28, endln:11:34 |vpiDecompile:TRUE @@ -18867,7 +18867,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:12:16, endln:12:37 |vpiParent: - \_module: work@oh_debouncer (work@oh_debouncer), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_debouncer.v, line:8:1, endln:77:10 + \_module_inst: work@oh_debouncer (work@oh_debouncer), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_debouncer.v, line:8:1, endln:77:10 |vpiRhs: \_constant: , line:12:28, endln:12:37 |vpiDecompile:DEFAULT @@ -18881,7 +18881,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:21:22, endln:21:63 |vpiParent: - \_module: work@oh_debouncer (work@oh_debouncer), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_debouncer.v, line:8:1, endln:77:10 + \_module_inst: work@oh_debouncer (work@oh_debouncer), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_debouncer.v, line:8:1, endln:77:10 |vpiRhs: \_sys_func_call: ($clog2), line:21:39, endln:21:63 |vpiArgument: @@ -18907,45 +18907,45 @@ design: (work@oh_fifo_async) |vpiNet: \_logic_net: (work@oh_debouncer.clk), line:15:12, endln:15:15 |vpiParent: - \_module: work@oh_debouncer (work@oh_debouncer), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_debouncer.v, line:8:1, endln:77:10 + \_module_inst: work@oh_debouncer (work@oh_debouncer), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_debouncer.v, line:8:1, endln:77:10 |vpiName:clk |vpiFullName:work@oh_debouncer.clk |vpiNet: \_logic_net: (work@oh_debouncer.nreset), line:16:12, endln:16:18 |vpiParent: - \_module: work@oh_debouncer (work@oh_debouncer), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_debouncer.v, line:8:1, endln:77:10 + \_module_inst: work@oh_debouncer (work@oh_debouncer), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_debouncer.v, line:8:1, endln:77:10 |vpiName:nreset |vpiFullName:work@oh_debouncer.nreset |vpiNet: \_logic_net: (work@oh_debouncer.noisy_in), line:17:12, endln:17:20 |vpiParent: - \_module: work@oh_debouncer (work@oh_debouncer), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_debouncer.v, line:8:1, endln:77:10 + \_module_inst: work@oh_debouncer (work@oh_debouncer), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_debouncer.v, line:8:1, endln:77:10 |vpiName:noisy_in |vpiFullName:work@oh_debouncer.noisy_in |vpiNet: \_logic_net: (work@oh_debouncer.clean_out), line:18:12, endln:18:21 |vpiParent: - \_module: work@oh_debouncer (work@oh_debouncer), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_debouncer.v, line:8:1, endln:77:10 + \_module_inst: work@oh_debouncer (work@oh_debouncer), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_debouncer.v, line:8:1, endln:77:10 |vpiName:clean_out |vpiFullName:work@oh_debouncer.clean_out |vpiNet: \_logic_net: (work@oh_debouncer.noisy_reg), line:24:11, endln:24:20 |vpiParent: - \_module: work@oh_debouncer (work@oh_debouncer), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_debouncer.v, line:8:1, endln:77:10 + \_module_inst: work@oh_debouncer (work@oh_debouncer), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_debouncer.v, line:8:1, endln:77:10 |vpiName:noisy_reg |vpiFullName:work@oh_debouncer.noisy_reg |vpiNetType:48 |vpiNet: \_logic_net: (work@oh_debouncer.clean_reg), line:25:11, endln:25:20 |vpiParent: - \_module: work@oh_debouncer (work@oh_debouncer), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_debouncer.v, line:8:1, endln:77:10 + \_module_inst: work@oh_debouncer (work@oh_debouncer), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_debouncer.v, line:8:1, endln:77:10 |vpiName:clean_reg |vpiFullName:work@oh_debouncer.clean_reg |vpiNetType:48 |vpiPort: \_port: (clk), line:15:12, endln:15:15 |vpiParent: - \_module: work@oh_debouncer (work@oh_debouncer), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_debouncer.v, line:8:1, endln:77:10 + \_module_inst: work@oh_debouncer (work@oh_debouncer), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_debouncer.v, line:8:1, endln:77:10 |vpiName:clk |vpiDirection:1 |vpiLowConn: @@ -18957,7 +18957,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (nreset), line:16:12, endln:16:18 |vpiParent: - \_module: work@oh_debouncer (work@oh_debouncer), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_debouncer.v, line:8:1, endln:77:10 + \_module_inst: work@oh_debouncer (work@oh_debouncer), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_debouncer.v, line:8:1, endln:77:10 |vpiName:nreset |vpiDirection:1 |vpiLowConn: @@ -18969,7 +18969,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (noisy_in), line:17:12, endln:17:20 |vpiParent: - \_module: work@oh_debouncer (work@oh_debouncer), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_debouncer.v, line:8:1, endln:77:10 + \_module_inst: work@oh_debouncer (work@oh_debouncer), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_debouncer.v, line:8:1, endln:77:10 |vpiName:noisy_in |vpiDirection:1 |vpiLowConn: @@ -18981,7 +18981,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (clean_out), line:18:12, endln:18:21 |vpiParent: - \_module: work@oh_debouncer (work@oh_debouncer), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_debouncer.v, line:8:1, endln:77:10 + \_module_inst: work@oh_debouncer (work@oh_debouncer), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_debouncer.v, line:8:1, endln:77:10 |vpiName:clean_out |vpiDirection:2 |vpiLowConn: @@ -18993,7 +18993,7 @@ design: (work@oh_fifo_async) |vpiProcess: \_always: , line:43:4, endln:47:34 |vpiParent: - \_module: work@oh_debouncer (work@oh_debouncer), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_debouncer.v, line:8:1, endln:77:10 + \_module_inst: work@oh_debouncer (work@oh_debouncer), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_debouncer.v, line:8:1, endln:77:10 |vpiStmt: \_event_control: , line:43:11, endln:43:44 |vpiParent: @@ -19074,7 +19074,7 @@ design: (work@oh_fifo_async) |vpiProcess: \_always: , line:69:4, endln:73:31 |vpiParent: - \_module: work@oh_debouncer (work@oh_debouncer), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_debouncer.v, line:8:1, endln:77:10 + \_module_inst: work@oh_debouncer (work@oh_debouncer), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_debouncer.v, line:8:1, endln:77:10 |vpiStmt: \_event_control: , line:69:11, endln:69:44 |vpiParent: @@ -19164,7 +19164,7 @@ design: (work@oh_fifo_async) |vpiContAssign: \_cont_assign: , line:49:11, endln:49:53 |vpiParent: - \_module: work@oh_debouncer (work@oh_debouncer), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_debouncer.v, line:8:1, endln:77:10 + \_module_inst: work@oh_debouncer (work@oh_debouncer), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_debouncer.v, line:8:1, endln:77:10 |vpiRhs: \_operation: , line:49:29, endln:49:53 |vpiParent: @@ -19191,7 +19191,7 @@ design: (work@oh_fifo_async) |vpiContAssign: \_cont_assign: , line:75:11, endln:75:32 |vpiParent: - \_module: work@oh_debouncer (work@oh_debouncer), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_debouncer.v, line:8:1, endln:77:10 + \_module_inst: work@oh_debouncer (work@oh_debouncer), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_debouncer.v, line:8:1, endln:77:10 |vpiRhs: \_ref_obj: (work@oh_debouncer.clean_reg), line:75:23, endln:75:32 |vpiParent: @@ -19205,14 +19205,14 @@ design: (work@oh_fifo_async) |vpiName:clean_out |vpiFullName:work@oh_debouncer.clean_out |uhdmallModules: -\_module: work@oh_delay (work@oh_delay), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_delay.v, line:8:1, endln:36:10 +\_module_inst: work@oh_delay (work@oh_delay), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_delay.v, line:8:1, endln:36:10 |vpiParent: \_design: (work@oh_fifo_async) |vpiFullName:work@oh_delay |vpiParameter: \_parameter: (work@oh_delay.N), line:9:15, endln:9:16 |vpiParent: - \_module: work@oh_delay (work@oh_delay), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_delay.v, line:8:1, endln:36:10 + \_module_inst: work@oh_delay (work@oh_delay), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_delay.v, line:8:1, endln:36:10 |UINT:1 |vpiTypespec: \_int_typespec: @@ -19221,7 +19221,7 @@ design: (work@oh_fifo_async) |vpiParameter: \_parameter: (work@oh_delay.MAXDELAY), line:10:15, endln:10:23 |vpiParent: - \_module: work@oh_delay (work@oh_delay), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_delay.v, line:8:1, endln:36:10 + \_module_inst: work@oh_delay (work@oh_delay), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_delay.v, line:8:1, endln:36:10 |UINT:4 |vpiTypespec: \_int_typespec: @@ -19230,13 +19230,13 @@ design: (work@oh_fifo_async) |vpiParameter: \_parameter: (work@oh_delay.M), line:11:15, endln:11:16 |vpiParent: - \_module: work@oh_delay (work@oh_delay), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_delay.v, line:8:1, endln:36:10 + \_module_inst: work@oh_delay (work@oh_delay), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_delay.v, line:8:1, endln:36:10 |vpiName:M |vpiFullName:work@oh_delay.M |vpiParamAssign: \_param_assign: , line:9:15, endln:9:27 |vpiParent: - \_module: work@oh_delay (work@oh_delay), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_delay.v, line:8:1, endln:36:10 + \_module_inst: work@oh_delay (work@oh_delay), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_delay.v, line:8:1, endln:36:10 |vpiRhs: \_constant: , line:9:26, endln:9:27 |vpiDecompile:1 @@ -19250,7 +19250,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:10:15, endln:10:27 |vpiParent: - \_module: work@oh_delay (work@oh_delay), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_delay.v, line:8:1, endln:36:10 + \_module_inst: work@oh_delay (work@oh_delay), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_delay.v, line:8:1, endln:36:10 |vpiRhs: \_constant: , line:10:26, endln:10:27 |vpiDecompile:4 @@ -19264,7 +19264,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:11:15, endln:11:42 |vpiParent: - \_module: work@oh_delay (work@oh_delay), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_delay.v, line:8:1, endln:36:10 + \_module_inst: work@oh_delay (work@oh_delay), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_delay.v, line:8:1, endln:36:10 |vpiRhs: \_sys_func_call: ($clog2), line:11:26, endln:11:42 |vpiArgument: @@ -19280,38 +19280,38 @@ design: (work@oh_fifo_async) |vpiNet: \_logic_net: (work@oh_delay.clk), line:14:15, endln:14:18 |vpiParent: - \_module: work@oh_delay (work@oh_delay), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_delay.v, line:8:1, endln:36:10 + \_module_inst: work@oh_delay (work@oh_delay), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_delay.v, line:8:1, endln:36:10 |vpiName:clk |vpiFullName:work@oh_delay.clk |vpiNet: \_logic_net: (work@oh_delay.in), line:15:20, endln:15:22 |vpiParent: - \_module: work@oh_delay (work@oh_delay), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_delay.v, line:8:1, endln:36:10 + \_module_inst: work@oh_delay (work@oh_delay), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_delay.v, line:8:1, endln:36:10 |vpiName:in |vpiFullName:work@oh_delay.in |vpiNet: \_logic_net: (work@oh_delay.sel), line:16:20, endln:16:23 |vpiParent: - \_module: work@oh_delay (work@oh_delay), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_delay.v, line:8:1, endln:36:10 + \_module_inst: work@oh_delay (work@oh_delay), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_delay.v, line:8:1, endln:36:10 |vpiName:sel |vpiFullName:work@oh_delay.sel |vpiNet: \_logic_net: (work@oh_delay.out), line:17:20, endln:17:23 |vpiParent: - \_module: work@oh_delay (work@oh_delay), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_delay.v, line:8:1, endln:36:10 + \_module_inst: work@oh_delay (work@oh_delay), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_delay.v, line:8:1, endln:36:10 |vpiName:out |vpiFullName:work@oh_delay.out |vpiNet: \_logic_net: (work@oh_delay.sync_pipe), line:22:20, endln:22:29 |vpiParent: - \_module: work@oh_delay (work@oh_delay), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_delay.v, line:8:1, endln:36:10 + \_module_inst: work@oh_delay (work@oh_delay), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_delay.v, line:8:1, endln:36:10 |vpiName:sync_pipe |vpiFullName:work@oh_delay.sync_pipe |vpiNetType:48 |vpiPort: \_port: (clk), line:14:15, endln:14:18 |vpiParent: - \_module: work@oh_delay (work@oh_delay), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_delay.v, line:8:1, endln:36:10 + \_module_inst: work@oh_delay (work@oh_delay), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_delay.v, line:8:1, endln:36:10 |vpiName:clk |vpiDirection:1 |vpiLowConn: @@ -19323,7 +19323,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (in), line:15:20, endln:15:22 |vpiParent: - \_module: work@oh_delay (work@oh_delay), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_delay.v, line:8:1, endln:36:10 + \_module_inst: work@oh_delay (work@oh_delay), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_delay.v, line:8:1, endln:36:10 |vpiName:in |vpiDirection:1 |vpiLowConn: @@ -19363,7 +19363,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (sel), line:16:20, endln:16:23 |vpiParent: - \_module: work@oh_delay (work@oh_delay), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_delay.v, line:8:1, endln:36:10 + \_module_inst: work@oh_delay (work@oh_delay), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_delay.v, line:8:1, endln:36:10 |vpiName:sel |vpiDirection:1 |vpiLowConn: @@ -19403,7 +19403,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (out), line:17:20, endln:17:23 |vpiParent: - \_module: work@oh_delay (work@oh_delay), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_delay.v, line:8:1, endln:36:10 + \_module_inst: work@oh_delay (work@oh_delay), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_delay.v, line:8:1, endln:36:10 |vpiName:out |vpiDirection:2 |vpiLowConn: @@ -19443,7 +19443,7 @@ design: (work@oh_fifo_async) |vpiContAssign: \_cont_assign: , line:34:11, endln:34:45 |vpiParent: - \_module: work@oh_delay (work@oh_delay), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_delay.v, line:8:1, endln:36:10 + \_module_inst: work@oh_delay (work@oh_delay), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_delay.v, line:8:1, endln:36:10 |vpiRhs: \_bit_select: (work@oh_delay.sync_pipe), line:34:24, endln:34:45 |vpiParent: @@ -19516,14 +19516,14 @@ design: (work@oh_fifo_async) |UINT:0 |vpiConstType:9 |uhdmallModules: -\_module: work@oh_dffnq (work@oh_dffnq), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dffnq.v, line:7:1, endln:17:10 +\_module_inst: work@oh_dffnq (work@oh_dffnq), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dffnq.v, line:7:1, endln:17:10 |vpiParent: \_design: (work@oh_fifo_async) |vpiFullName:work@oh_dffnq |vpiParameter: \_parameter: (work@oh_dffnq.DW), line:7:29, endln:7:31 |vpiParent: - \_module: work@oh_dffnq (work@oh_dffnq), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dffnq.v, line:7:1, endln:17:10 + \_module_inst: work@oh_dffnq (work@oh_dffnq), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dffnq.v, line:7:1, endln:17:10 |UINT:1 |vpiTypespec: \_int_typespec: @@ -19532,7 +19532,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:7:29, endln:7:35 |vpiParent: - \_module: work@oh_dffnq (work@oh_dffnq), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dffnq.v, line:7:1, endln:17:10 + \_module_inst: work@oh_dffnq (work@oh_dffnq), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dffnq.v, line:7:1, endln:17:10 |vpiRhs: \_constant: , line:7:34, endln:7:35 |vpiDecompile:1 @@ -19548,26 +19548,26 @@ design: (work@oh_fifo_async) |vpiNet: \_logic_net: (work@oh_dffnq.d), line:9:21, endln:9:22 |vpiParent: - \_module: work@oh_dffnq (work@oh_dffnq), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dffnq.v, line:7:1, endln:17:10 + \_module_inst: work@oh_dffnq (work@oh_dffnq), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dffnq.v, line:7:1, endln:17:10 |vpiName:d |vpiFullName:work@oh_dffnq.d |vpiNet: \_logic_net: (work@oh_dffnq.clk), line:10:21, endln:10:24 |vpiParent: - \_module: work@oh_dffnq (work@oh_dffnq), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dffnq.v, line:7:1, endln:17:10 + \_module_inst: work@oh_dffnq (work@oh_dffnq), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dffnq.v, line:7:1, endln:17:10 |vpiName:clk |vpiFullName:work@oh_dffnq.clk |vpiNet: \_logic_net: (work@oh_dffnq.q), line:11:25, endln:11:26 |vpiParent: - \_module: work@oh_dffnq (work@oh_dffnq), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dffnq.v, line:7:1, endln:17:10 + \_module_inst: work@oh_dffnq (work@oh_dffnq), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dffnq.v, line:7:1, endln:17:10 |vpiName:q |vpiFullName:work@oh_dffnq.q |vpiNetType:48 |vpiPort: \_port: (d), line:9:21, endln:9:22 |vpiParent: - \_module: work@oh_dffnq (work@oh_dffnq), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dffnq.v, line:7:1, endln:17:10 + \_module_inst: work@oh_dffnq (work@oh_dffnq), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dffnq.v, line:7:1, endln:17:10 |vpiName:d |vpiDirection:1 |vpiLowConn: @@ -19607,7 +19607,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (clk), line:10:21, endln:10:24 |vpiParent: - \_module: work@oh_dffnq (work@oh_dffnq), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dffnq.v, line:7:1, endln:17:10 + \_module_inst: work@oh_dffnq (work@oh_dffnq), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dffnq.v, line:7:1, endln:17:10 |vpiName:clk |vpiDirection:1 |vpiLowConn: @@ -19647,7 +19647,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (q), line:11:25, endln:11:26 |vpiParent: - \_module: work@oh_dffnq (work@oh_dffnq), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dffnq.v, line:7:1, endln:17:10 + \_module_inst: work@oh_dffnq (work@oh_dffnq), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dffnq.v, line:7:1, endln:17:10 |vpiName:q |vpiDirection:2 |vpiLowConn: @@ -19687,7 +19687,7 @@ design: (work@oh_fifo_async) |vpiProcess: \_always: , line:14:4, endln:15:13 |vpiParent: - \_module: work@oh_dffnq (work@oh_dffnq), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dffnq.v, line:7:1, endln:17:10 + \_module_inst: work@oh_dffnq (work@oh_dffnq), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dffnq.v, line:7:1, endln:17:10 |vpiStmt: \_event_control: , line:14:11, endln:14:26 |vpiParent: @@ -19722,14 +19722,14 @@ design: (work@oh_fifo_async) |vpiFullName:work@oh_dffnq.q |vpiAlwaysType:1 |uhdmallModules: -\_module: work@oh_dffq (work@oh_dffq), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dffq.v, line:8:1, endln:18:10 +\_module_inst: work@oh_dffq (work@oh_dffq), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dffq.v, line:8:1, endln:18:10 |vpiParent: \_design: (work@oh_fifo_async) |vpiFullName:work@oh_dffq |vpiParameter: \_parameter: (work@oh_dffq.DW), line:8:28, endln:8:30 |vpiParent: - \_module: work@oh_dffq (work@oh_dffq), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dffq.v, line:8:1, endln:18:10 + \_module_inst: work@oh_dffq (work@oh_dffq), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dffq.v, line:8:1, endln:18:10 |UINT:1 |vpiTypespec: \_int_typespec: @@ -19738,7 +19738,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:8:28, endln:8:34 |vpiParent: - \_module: work@oh_dffq (work@oh_dffq), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dffq.v, line:8:1, endln:18:10 + \_module_inst: work@oh_dffq (work@oh_dffq), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dffq.v, line:8:1, endln:18:10 |vpiRhs: \_constant: , line:8:33, endln:8:34 |vpiDecompile:1 @@ -19754,26 +19754,26 @@ design: (work@oh_fifo_async) |vpiNet: \_logic_net: (work@oh_dffq.d), line:10:21, endln:10:22 |vpiParent: - \_module: work@oh_dffq (work@oh_dffq), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dffq.v, line:8:1, endln:18:10 + \_module_inst: work@oh_dffq (work@oh_dffq), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dffq.v, line:8:1, endln:18:10 |vpiName:d |vpiFullName:work@oh_dffq.d |vpiNet: \_logic_net: (work@oh_dffq.clk), line:11:21, endln:11:24 |vpiParent: - \_module: work@oh_dffq (work@oh_dffq), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dffq.v, line:8:1, endln:18:10 + \_module_inst: work@oh_dffq (work@oh_dffq), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dffq.v, line:8:1, endln:18:10 |vpiName:clk |vpiFullName:work@oh_dffq.clk |vpiNet: \_logic_net: (work@oh_dffq.q), line:12:25, endln:12:26 |vpiParent: - \_module: work@oh_dffq (work@oh_dffq), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dffq.v, line:8:1, endln:18:10 + \_module_inst: work@oh_dffq (work@oh_dffq), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dffq.v, line:8:1, endln:18:10 |vpiName:q |vpiFullName:work@oh_dffq.q |vpiNetType:48 |vpiPort: \_port: (d), line:10:21, endln:10:22 |vpiParent: - \_module: work@oh_dffq (work@oh_dffq), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dffq.v, line:8:1, endln:18:10 + \_module_inst: work@oh_dffq (work@oh_dffq), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dffq.v, line:8:1, endln:18:10 |vpiName:d |vpiDirection:1 |vpiLowConn: @@ -19813,7 +19813,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (clk), line:11:21, endln:11:24 |vpiParent: - \_module: work@oh_dffq (work@oh_dffq), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dffq.v, line:8:1, endln:18:10 + \_module_inst: work@oh_dffq (work@oh_dffq), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dffq.v, line:8:1, endln:18:10 |vpiName:clk |vpiDirection:1 |vpiLowConn: @@ -19853,7 +19853,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (q), line:12:25, endln:12:26 |vpiParent: - \_module: work@oh_dffq (work@oh_dffq), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dffq.v, line:8:1, endln:18:10 + \_module_inst: work@oh_dffq (work@oh_dffq), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dffq.v, line:8:1, endln:18:10 |vpiName:q |vpiDirection:2 |vpiLowConn: @@ -19893,7 +19893,7 @@ design: (work@oh_fifo_async) |vpiProcess: \_always: , line:15:4, endln:16:13 |vpiParent: - \_module: work@oh_dffq (work@oh_dffq), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dffq.v, line:8:1, endln:18:10 + \_module_inst: work@oh_dffq (work@oh_dffq), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dffq.v, line:8:1, endln:18:10 |vpiStmt: \_event_control: , line:15:11, endln:15:26 |vpiParent: @@ -19928,14 +19928,14 @@ design: (work@oh_fifo_async) |vpiFullName:work@oh_dffq.q |vpiAlwaysType:1 |uhdmallModules: -\_module: work@oh_dffqn (work@oh_dffqn), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dffqn.v, line:7:1, endln:17:10 +\_module_inst: work@oh_dffqn (work@oh_dffqn), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dffqn.v, line:7:1, endln:17:10 |vpiParent: \_design: (work@oh_fifo_async) |vpiFullName:work@oh_dffqn |vpiParameter: \_parameter: (work@oh_dffqn.DW), line:7:29, endln:7:31 |vpiParent: - \_module: work@oh_dffqn (work@oh_dffqn), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dffqn.v, line:7:1, endln:17:10 + \_module_inst: work@oh_dffqn (work@oh_dffqn), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dffqn.v, line:7:1, endln:17:10 |UINT:1 |vpiTypespec: \_int_typespec: @@ -19944,7 +19944,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:7:29, endln:7:35 |vpiParent: - \_module: work@oh_dffqn (work@oh_dffqn), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dffqn.v, line:7:1, endln:17:10 + \_module_inst: work@oh_dffqn (work@oh_dffqn), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dffqn.v, line:7:1, endln:17:10 |vpiRhs: \_constant: , line:7:34, endln:7:35 |vpiDecompile:1 @@ -19960,26 +19960,26 @@ design: (work@oh_fifo_async) |vpiNet: \_logic_net: (work@oh_dffqn.d), line:9:21, endln:9:22 |vpiParent: - \_module: work@oh_dffqn (work@oh_dffqn), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dffqn.v, line:7:1, endln:17:10 + \_module_inst: work@oh_dffqn (work@oh_dffqn), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dffqn.v, line:7:1, endln:17:10 |vpiName:d |vpiFullName:work@oh_dffqn.d |vpiNet: \_logic_net: (work@oh_dffqn.clk), line:10:21, endln:10:24 |vpiParent: - \_module: work@oh_dffqn (work@oh_dffqn), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dffqn.v, line:7:1, endln:17:10 + \_module_inst: work@oh_dffqn (work@oh_dffqn), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dffqn.v, line:7:1, endln:17:10 |vpiName:clk |vpiFullName:work@oh_dffqn.clk |vpiNet: \_logic_net: (work@oh_dffqn.qn), line:11:25, endln:11:27 |vpiParent: - \_module: work@oh_dffqn (work@oh_dffqn), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dffqn.v, line:7:1, endln:17:10 + \_module_inst: work@oh_dffqn (work@oh_dffqn), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dffqn.v, line:7:1, endln:17:10 |vpiName:qn |vpiFullName:work@oh_dffqn.qn |vpiNetType:48 |vpiPort: \_port: (d), line:9:21, endln:9:22 |vpiParent: - \_module: work@oh_dffqn (work@oh_dffqn), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dffqn.v, line:7:1, endln:17:10 + \_module_inst: work@oh_dffqn (work@oh_dffqn), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dffqn.v, line:7:1, endln:17:10 |vpiName:d |vpiDirection:1 |vpiLowConn: @@ -20019,7 +20019,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (clk), line:10:21, endln:10:24 |vpiParent: - \_module: work@oh_dffqn (work@oh_dffqn), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dffqn.v, line:7:1, endln:17:10 + \_module_inst: work@oh_dffqn (work@oh_dffqn), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dffqn.v, line:7:1, endln:17:10 |vpiName:clk |vpiDirection:1 |vpiLowConn: @@ -20059,7 +20059,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (qn), line:11:25, endln:11:27 |vpiParent: - \_module: work@oh_dffqn (work@oh_dffqn), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dffqn.v, line:7:1, endln:17:10 + \_module_inst: work@oh_dffqn (work@oh_dffqn), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dffqn.v, line:7:1, endln:17:10 |vpiName:qn |vpiDirection:2 |vpiLowConn: @@ -20099,7 +20099,7 @@ design: (work@oh_fifo_async) |vpiProcess: \_always: , line:14:4, endln:15:15 |vpiParent: - \_module: work@oh_dffqn (work@oh_dffqn), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dffqn.v, line:7:1, endln:17:10 + \_module_inst: work@oh_dffqn (work@oh_dffqn), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dffqn.v, line:7:1, endln:17:10 |vpiStmt: \_event_control: , line:14:11, endln:14:26 |vpiParent: @@ -20139,14 +20139,14 @@ design: (work@oh_fifo_async) |vpiFullName:work@oh_dffqn.qn |vpiAlwaysType:1 |uhdmallModules: -\_module: work@oh_dffrq (work@oh_dffrq), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dffrq.v, line:9:1, endln:23:10 +\_module_inst: work@oh_dffrq (work@oh_dffrq), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dffrq.v, line:9:1, endln:23:10 |vpiParent: \_design: (work@oh_fifo_async) |vpiFullName:work@oh_dffrq |vpiParameter: \_parameter: (work@oh_dffrq.DW), line:9:29, endln:9:31 |vpiParent: - \_module: work@oh_dffrq (work@oh_dffrq), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dffrq.v, line:9:1, endln:23:10 + \_module_inst: work@oh_dffrq (work@oh_dffrq), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dffrq.v, line:9:1, endln:23:10 |UINT:1 |vpiTypespec: \_int_typespec: @@ -20155,7 +20155,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:9:29, endln:9:35 |vpiParent: - \_module: work@oh_dffrq (work@oh_dffrq), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dffrq.v, line:9:1, endln:23:10 + \_module_inst: work@oh_dffrq (work@oh_dffrq), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dffrq.v, line:9:1, endln:23:10 |vpiRhs: \_constant: , line:9:34, endln:9:35 |vpiDecompile:1 @@ -20171,32 +20171,32 @@ design: (work@oh_fifo_async) |vpiNet: \_logic_net: (work@oh_dffrq.d), line:11:21, endln:11:22 |vpiParent: - \_module: work@oh_dffrq (work@oh_dffrq), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dffrq.v, line:9:1, endln:23:10 + \_module_inst: work@oh_dffrq (work@oh_dffrq), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dffrq.v, line:9:1, endln:23:10 |vpiName:d |vpiFullName:work@oh_dffrq.d |vpiNet: \_logic_net: (work@oh_dffrq.clk), line:12:21, endln:12:24 |vpiParent: - \_module: work@oh_dffrq (work@oh_dffrq), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dffrq.v, line:9:1, endln:23:10 + \_module_inst: work@oh_dffrq (work@oh_dffrq), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dffrq.v, line:9:1, endln:23:10 |vpiName:clk |vpiFullName:work@oh_dffrq.clk |vpiNet: \_logic_net: (work@oh_dffrq.nreset), line:13:21, endln:13:27 |vpiParent: - \_module: work@oh_dffrq (work@oh_dffrq), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dffrq.v, line:9:1, endln:23:10 + \_module_inst: work@oh_dffrq (work@oh_dffrq), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dffrq.v, line:9:1, endln:23:10 |vpiName:nreset |vpiFullName:work@oh_dffrq.nreset |vpiNet: \_logic_net: (work@oh_dffrq.q), line:14:25, endln:14:26 |vpiParent: - \_module: work@oh_dffrq (work@oh_dffrq), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dffrq.v, line:9:1, endln:23:10 + \_module_inst: work@oh_dffrq (work@oh_dffrq), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dffrq.v, line:9:1, endln:23:10 |vpiName:q |vpiFullName:work@oh_dffrq.q |vpiNetType:48 |vpiPort: \_port: (d), line:11:21, endln:11:22 |vpiParent: - \_module: work@oh_dffrq (work@oh_dffrq), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dffrq.v, line:9:1, endln:23:10 + \_module_inst: work@oh_dffrq (work@oh_dffrq), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dffrq.v, line:9:1, endln:23:10 |vpiName:d |vpiDirection:1 |vpiLowConn: @@ -20236,7 +20236,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (clk), line:12:21, endln:12:24 |vpiParent: - \_module: work@oh_dffrq (work@oh_dffrq), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dffrq.v, line:9:1, endln:23:10 + \_module_inst: work@oh_dffrq (work@oh_dffrq), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dffrq.v, line:9:1, endln:23:10 |vpiName:clk |vpiDirection:1 |vpiLowConn: @@ -20276,7 +20276,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (nreset), line:13:21, endln:13:27 |vpiParent: - \_module: work@oh_dffrq (work@oh_dffrq), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dffrq.v, line:9:1, endln:23:10 + \_module_inst: work@oh_dffrq (work@oh_dffrq), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dffrq.v, line:9:1, endln:23:10 |vpiName:nreset |vpiDirection:1 |vpiLowConn: @@ -20316,7 +20316,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (q), line:14:25, endln:14:26 |vpiParent: - \_module: work@oh_dffrq (work@oh_dffrq), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dffrq.v, line:9:1, endln:23:10 + \_module_inst: work@oh_dffrq (work@oh_dffrq), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dffrq.v, line:9:1, endln:23:10 |vpiName:q |vpiDirection:2 |vpiLowConn: @@ -20356,7 +20356,7 @@ design: (work@oh_fifo_async) |vpiProcess: \_always: , line:17:4, endln:21:15 |vpiParent: - \_module: work@oh_dffrq (work@oh_dffrq), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dffrq.v, line:9:1, endln:23:10 + \_module_inst: work@oh_dffrq (work@oh_dffrq), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dffrq.v, line:9:1, endln:23:10 |vpiStmt: \_event_control: , line:17:11, endln:17:44 |vpiParent: @@ -20434,14 +20434,14 @@ design: (work@oh_fifo_async) |vpiFullName:work@oh_dffrq.q |vpiAlwaysType:1 |uhdmallModules: -\_module: work@oh_dffrqn (work@oh_dffrqn), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dffrqn.v, line:8:1, endln:22:10 +\_module_inst: work@oh_dffrqn (work@oh_dffrqn), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dffrqn.v, line:8:1, endln:22:10 |vpiParent: \_design: (work@oh_fifo_async) |vpiFullName:work@oh_dffrqn |vpiParameter: \_parameter: (work@oh_dffrqn.DW), line:8:30, endln:8:32 |vpiParent: - \_module: work@oh_dffrqn (work@oh_dffrqn), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dffrqn.v, line:8:1, endln:22:10 + \_module_inst: work@oh_dffrqn (work@oh_dffrqn), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dffrqn.v, line:8:1, endln:22:10 |UINT:1 |vpiTypespec: \_int_typespec: @@ -20450,7 +20450,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:8:30, endln:8:36 |vpiParent: - \_module: work@oh_dffrqn (work@oh_dffrqn), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dffrqn.v, line:8:1, endln:22:10 + \_module_inst: work@oh_dffrqn (work@oh_dffrqn), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dffrqn.v, line:8:1, endln:22:10 |vpiRhs: \_constant: , line:8:35, endln:8:36 |vpiDecompile:1 @@ -20466,32 +20466,32 @@ design: (work@oh_fifo_async) |vpiNet: \_logic_net: (work@oh_dffrqn.d), line:10:21, endln:10:22 |vpiParent: - \_module: work@oh_dffrqn (work@oh_dffrqn), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dffrqn.v, line:8:1, endln:22:10 + \_module_inst: work@oh_dffrqn (work@oh_dffrqn), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dffrqn.v, line:8:1, endln:22:10 |vpiName:d |vpiFullName:work@oh_dffrqn.d |vpiNet: \_logic_net: (work@oh_dffrqn.clk), line:11:21, endln:11:24 |vpiParent: - \_module: work@oh_dffrqn (work@oh_dffrqn), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dffrqn.v, line:8:1, endln:22:10 + \_module_inst: work@oh_dffrqn (work@oh_dffrqn), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dffrqn.v, line:8:1, endln:22:10 |vpiName:clk |vpiFullName:work@oh_dffrqn.clk |vpiNet: \_logic_net: (work@oh_dffrqn.nreset), line:12:21, endln:12:27 |vpiParent: - \_module: work@oh_dffrqn (work@oh_dffrqn), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dffrqn.v, line:8:1, endln:22:10 + \_module_inst: work@oh_dffrqn (work@oh_dffrqn), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dffrqn.v, line:8:1, endln:22:10 |vpiName:nreset |vpiFullName:work@oh_dffrqn.nreset |vpiNet: \_logic_net: (work@oh_dffrqn.qn), line:13:25, endln:13:27 |vpiParent: - \_module: work@oh_dffrqn (work@oh_dffrqn), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dffrqn.v, line:8:1, endln:22:10 + \_module_inst: work@oh_dffrqn (work@oh_dffrqn), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dffrqn.v, line:8:1, endln:22:10 |vpiName:qn |vpiFullName:work@oh_dffrqn.qn |vpiNetType:48 |vpiPort: \_port: (d), line:10:21, endln:10:22 |vpiParent: - \_module: work@oh_dffrqn (work@oh_dffrqn), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dffrqn.v, line:8:1, endln:22:10 + \_module_inst: work@oh_dffrqn (work@oh_dffrqn), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dffrqn.v, line:8:1, endln:22:10 |vpiName:d |vpiDirection:1 |vpiLowConn: @@ -20531,7 +20531,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (clk), line:11:21, endln:11:24 |vpiParent: - \_module: work@oh_dffrqn (work@oh_dffrqn), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dffrqn.v, line:8:1, endln:22:10 + \_module_inst: work@oh_dffrqn (work@oh_dffrqn), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dffrqn.v, line:8:1, endln:22:10 |vpiName:clk |vpiDirection:1 |vpiLowConn: @@ -20571,7 +20571,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (nreset), line:12:21, endln:12:27 |vpiParent: - \_module: work@oh_dffrqn (work@oh_dffrqn), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dffrqn.v, line:8:1, endln:22:10 + \_module_inst: work@oh_dffrqn (work@oh_dffrqn), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dffrqn.v, line:8:1, endln:22:10 |vpiName:nreset |vpiDirection:1 |vpiLowConn: @@ -20611,7 +20611,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (qn), line:13:25, endln:13:27 |vpiParent: - \_module: work@oh_dffrqn (work@oh_dffrqn), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dffrqn.v, line:8:1, endln:22:10 + \_module_inst: work@oh_dffrqn (work@oh_dffrqn), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dffrqn.v, line:8:1, endln:22:10 |vpiName:qn |vpiDirection:2 |vpiLowConn: @@ -20651,7 +20651,7 @@ design: (work@oh_fifo_async) |vpiProcess: \_always: , line:16:4, endln:20:17 |vpiParent: - \_module: work@oh_dffrqn (work@oh_dffrqn), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dffrqn.v, line:8:1, endln:22:10 + \_module_inst: work@oh_dffrqn (work@oh_dffrqn), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dffrqn.v, line:8:1, endln:22:10 |vpiStmt: \_event_control: , line:16:11, endln:16:44 |vpiParent: @@ -20749,14 +20749,14 @@ design: (work@oh_fifo_async) |vpiFullName:work@oh_dffrqn.qn |vpiAlwaysType:1 |uhdmallModules: -\_module: work@oh_dffsq (work@oh_dffsq), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dffsq.v, line:8:1, endln:22:10 +\_module_inst: work@oh_dffsq (work@oh_dffsq), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dffsq.v, line:8:1, endln:22:10 |vpiParent: \_design: (work@oh_fifo_async) |vpiFullName:work@oh_dffsq |vpiParameter: \_parameter: (work@oh_dffsq.DW), line:8:29, endln:8:31 |vpiParent: - \_module: work@oh_dffsq (work@oh_dffsq), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dffsq.v, line:8:1, endln:22:10 + \_module_inst: work@oh_dffsq (work@oh_dffsq), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dffsq.v, line:8:1, endln:22:10 |UINT:1 |vpiTypespec: \_int_typespec: @@ -20765,7 +20765,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:8:29, endln:8:35 |vpiParent: - \_module: work@oh_dffsq (work@oh_dffsq), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dffsq.v, line:8:1, endln:22:10 + \_module_inst: work@oh_dffsq (work@oh_dffsq), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dffsq.v, line:8:1, endln:22:10 |vpiRhs: \_constant: , line:8:34, endln:8:35 |vpiDecompile:1 @@ -20781,32 +20781,32 @@ design: (work@oh_fifo_async) |vpiNet: \_logic_net: (work@oh_dffsq.d), line:10:24, endln:10:25 |vpiParent: - \_module: work@oh_dffsq (work@oh_dffsq), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dffsq.v, line:8:1, endln:22:10 + \_module_inst: work@oh_dffsq (work@oh_dffsq), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dffsq.v, line:8:1, endln:22:10 |vpiName:d |vpiFullName:work@oh_dffsq.d |vpiNet: \_logic_net: (work@oh_dffsq.clk), line:11:24, endln:11:27 |vpiParent: - \_module: work@oh_dffsq (work@oh_dffsq), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dffsq.v, line:8:1, endln:22:10 + \_module_inst: work@oh_dffsq (work@oh_dffsq), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dffsq.v, line:8:1, endln:22:10 |vpiName:clk |vpiFullName:work@oh_dffsq.clk |vpiNet: \_logic_net: (work@oh_dffsq.nset), line:12:24, endln:12:28 |vpiParent: - \_module: work@oh_dffsq (work@oh_dffsq), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dffsq.v, line:8:1, endln:22:10 + \_module_inst: work@oh_dffsq (work@oh_dffsq), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dffsq.v, line:8:1, endln:22:10 |vpiName:nset |vpiFullName:work@oh_dffsq.nset |vpiNet: \_logic_net: (work@oh_dffsq.q), line:13:25, endln:13:26 |vpiParent: - \_module: work@oh_dffsq (work@oh_dffsq), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dffsq.v, line:8:1, endln:22:10 + \_module_inst: work@oh_dffsq (work@oh_dffsq), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dffsq.v, line:8:1, endln:22:10 |vpiName:q |vpiFullName:work@oh_dffsq.q |vpiNetType:48 |vpiPort: \_port: (d), line:10:24, endln:10:25 |vpiParent: - \_module: work@oh_dffsq (work@oh_dffsq), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dffsq.v, line:8:1, endln:22:10 + \_module_inst: work@oh_dffsq (work@oh_dffsq), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dffsq.v, line:8:1, endln:22:10 |vpiName:d |vpiDirection:1 |vpiLowConn: @@ -20846,7 +20846,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (clk), line:11:24, endln:11:27 |vpiParent: - \_module: work@oh_dffsq (work@oh_dffsq), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dffsq.v, line:8:1, endln:22:10 + \_module_inst: work@oh_dffsq (work@oh_dffsq), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dffsq.v, line:8:1, endln:22:10 |vpiName:clk |vpiDirection:1 |vpiLowConn: @@ -20886,7 +20886,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (nset), line:12:24, endln:12:28 |vpiParent: - \_module: work@oh_dffsq (work@oh_dffsq), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dffsq.v, line:8:1, endln:22:10 + \_module_inst: work@oh_dffsq (work@oh_dffsq), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dffsq.v, line:8:1, endln:22:10 |vpiName:nset |vpiDirection:1 |vpiLowConn: @@ -20926,7 +20926,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (q), line:13:25, endln:13:26 |vpiParent: - \_module: work@oh_dffsq (work@oh_dffsq), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dffsq.v, line:8:1, endln:22:10 + \_module_inst: work@oh_dffsq (work@oh_dffsq), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dffsq.v, line:8:1, endln:22:10 |vpiName:q |vpiDirection:2 |vpiLowConn: @@ -20966,7 +20966,7 @@ design: (work@oh_fifo_async) |vpiProcess: \_always: , line:16:4, endln:20:15 |vpiParent: - \_module: work@oh_dffsq (work@oh_dffsq), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dffsq.v, line:8:1, endln:22:10 + \_module_inst: work@oh_dffsq (work@oh_dffsq), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dffsq.v, line:8:1, endln:22:10 |vpiStmt: \_event_control: , line:16:11, endln:16:42 |vpiParent: @@ -21059,14 +21059,14 @@ design: (work@oh_fifo_async) |vpiFullName:work@oh_dffsq.q |vpiAlwaysType:1 |uhdmallModules: -\_module: work@oh_dffsqn (work@oh_dffsqn), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dffsqn.v, line:8:1, endln:22:10 +\_module_inst: work@oh_dffsqn (work@oh_dffsqn), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dffsqn.v, line:8:1, endln:22:10 |vpiParent: \_design: (work@oh_fifo_async) |vpiFullName:work@oh_dffsqn |vpiParameter: \_parameter: (work@oh_dffsqn.DW), line:8:30, endln:8:32 |vpiParent: - \_module: work@oh_dffsqn (work@oh_dffsqn), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dffsqn.v, line:8:1, endln:22:10 + \_module_inst: work@oh_dffsqn (work@oh_dffsqn), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dffsqn.v, line:8:1, endln:22:10 |UINT:1 |vpiTypespec: \_int_typespec: @@ -21075,7 +21075,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:8:30, endln:8:36 |vpiParent: - \_module: work@oh_dffsqn (work@oh_dffsqn), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dffsqn.v, line:8:1, endln:22:10 + \_module_inst: work@oh_dffsqn (work@oh_dffsqn), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dffsqn.v, line:8:1, endln:22:10 |vpiRhs: \_constant: , line:8:35, endln:8:36 |vpiDecompile:1 @@ -21091,32 +21091,32 @@ design: (work@oh_fifo_async) |vpiNet: \_logic_net: (work@oh_dffsqn.d), line:10:21, endln:10:22 |vpiParent: - \_module: work@oh_dffsqn (work@oh_dffsqn), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dffsqn.v, line:8:1, endln:22:10 + \_module_inst: work@oh_dffsqn (work@oh_dffsqn), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dffsqn.v, line:8:1, endln:22:10 |vpiName:d |vpiFullName:work@oh_dffsqn.d |vpiNet: \_logic_net: (work@oh_dffsqn.clk), line:11:21, endln:11:24 |vpiParent: - \_module: work@oh_dffsqn (work@oh_dffsqn), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dffsqn.v, line:8:1, endln:22:10 + \_module_inst: work@oh_dffsqn (work@oh_dffsqn), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dffsqn.v, line:8:1, endln:22:10 |vpiName:clk |vpiFullName:work@oh_dffsqn.clk |vpiNet: \_logic_net: (work@oh_dffsqn.nset), line:12:21, endln:12:25 |vpiParent: - \_module: work@oh_dffsqn (work@oh_dffsqn), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dffsqn.v, line:8:1, endln:22:10 + \_module_inst: work@oh_dffsqn (work@oh_dffsqn), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dffsqn.v, line:8:1, endln:22:10 |vpiName:nset |vpiFullName:work@oh_dffsqn.nset |vpiNet: \_logic_net: (work@oh_dffsqn.qn), line:13:25, endln:13:27 |vpiParent: - \_module: work@oh_dffsqn (work@oh_dffsqn), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dffsqn.v, line:8:1, endln:22:10 + \_module_inst: work@oh_dffsqn (work@oh_dffsqn), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dffsqn.v, line:8:1, endln:22:10 |vpiName:qn |vpiFullName:work@oh_dffsqn.qn |vpiNetType:48 |vpiPort: \_port: (d), line:10:21, endln:10:22 |vpiParent: - \_module: work@oh_dffsqn (work@oh_dffsqn), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dffsqn.v, line:8:1, endln:22:10 + \_module_inst: work@oh_dffsqn (work@oh_dffsqn), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dffsqn.v, line:8:1, endln:22:10 |vpiName:d |vpiDirection:1 |vpiLowConn: @@ -21156,7 +21156,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (clk), line:11:21, endln:11:24 |vpiParent: - \_module: work@oh_dffsqn (work@oh_dffsqn), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dffsqn.v, line:8:1, endln:22:10 + \_module_inst: work@oh_dffsqn (work@oh_dffsqn), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dffsqn.v, line:8:1, endln:22:10 |vpiName:clk |vpiDirection:1 |vpiLowConn: @@ -21196,7 +21196,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (nset), line:12:21, endln:12:25 |vpiParent: - \_module: work@oh_dffsqn (work@oh_dffsqn), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dffsqn.v, line:8:1, endln:22:10 + \_module_inst: work@oh_dffsqn (work@oh_dffsqn), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dffsqn.v, line:8:1, endln:22:10 |vpiName:nset |vpiDirection:1 |vpiLowConn: @@ -21236,7 +21236,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (qn), line:13:25, endln:13:27 |vpiParent: - \_module: work@oh_dffsqn (work@oh_dffsqn), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dffsqn.v, line:8:1, endln:22:10 + \_module_inst: work@oh_dffsqn (work@oh_dffsqn), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dffsqn.v, line:8:1, endln:22:10 |vpiName:qn |vpiDirection:2 |vpiLowConn: @@ -21276,7 +21276,7 @@ design: (work@oh_fifo_async) |vpiProcess: \_always: , line:16:4, endln:20:17 |vpiParent: - \_module: work@oh_dffsqn (work@oh_dffsqn), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dffsqn.v, line:8:1, endln:22:10 + \_module_inst: work@oh_dffsqn (work@oh_dffsqn), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dffsqn.v, line:8:1, endln:22:10 |vpiStmt: \_event_control: , line:16:11, endln:16:42 |vpiParent: @@ -21359,14 +21359,14 @@ design: (work@oh_fifo_async) |vpiFullName:work@oh_dffsqn.qn |vpiAlwaysType:1 |uhdmallModules: -\_module: work@oh_dsync (work@oh_dsync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dsync.v, line:8:1, endln:44:10 +\_module_inst: work@oh_dsync (work@oh_dsync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dsync.v, line:8:1, endln:44:10 |vpiParent: \_design: (work@oh_fifo_async) |vpiFullName:work@oh_dsync |vpiParameter: \_parameter: (work@oh_dsync.SYNCPIPE), line:9:15, endln:9:23 |vpiParent: - \_module: work@oh_dsync (work@oh_dsync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dsync.v, line:8:1, endln:44:10 + \_module_inst: work@oh_dsync (work@oh_dsync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dsync.v, line:8:1, endln:44:10 |UINT:2 |vpiTypespec: \_int_typespec: @@ -21375,7 +21375,7 @@ design: (work@oh_fifo_async) |vpiParameter: \_parameter: (work@oh_dsync.DELAY), line:10:15, endln:10:20 |vpiParent: - \_module: work@oh_dsync (work@oh_dsync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dsync.v, line:8:1, endln:44:10 + \_module_inst: work@oh_dsync (work@oh_dsync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dsync.v, line:8:1, endln:44:10 |UINT:0 |vpiTypespec: \_int_typespec: @@ -21384,7 +21384,7 @@ design: (work@oh_fifo_async) |vpiParameter: \_parameter: (work@oh_dsync.SYN), line:11:15, endln:11:18 |vpiParent: - \_module: work@oh_dsync (work@oh_dsync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dsync.v, line:8:1, endln:44:10 + \_module_inst: work@oh_dsync (work@oh_dsync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dsync.v, line:8:1, endln:44:10 |STRING:TRUE |vpiTypespec: \_string_typespec: @@ -21393,7 +21393,7 @@ design: (work@oh_fifo_async) |vpiParameter: \_parameter: (work@oh_dsync.TYPE), line:12:15, endln:12:19 |vpiParent: - \_module: work@oh_dsync (work@oh_dsync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dsync.v, line:8:1, endln:44:10 + \_module_inst: work@oh_dsync (work@oh_dsync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dsync.v, line:8:1, endln:44:10 |STRING:DEFAULT |vpiTypespec: \_string_typespec: @@ -21402,7 +21402,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:9:15, endln:9:27 |vpiParent: - \_module: work@oh_dsync (work@oh_dsync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dsync.v, line:8:1, endln:44:10 + \_module_inst: work@oh_dsync (work@oh_dsync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dsync.v, line:8:1, endln:44:10 |vpiRhs: \_constant: , line:9:26, endln:9:27 |vpiDecompile:2 @@ -21416,7 +21416,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:10:15, endln:10:27 |vpiParent: - \_module: work@oh_dsync (work@oh_dsync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dsync.v, line:8:1, endln:44:10 + \_module_inst: work@oh_dsync (work@oh_dsync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dsync.v, line:8:1, endln:44:10 |vpiRhs: \_constant: , line:10:26, endln:10:27 |vpiDecompile:0 @@ -21430,7 +21430,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:11:15, endln:11:32 |vpiParent: - \_module: work@oh_dsync (work@oh_dsync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dsync.v, line:8:1, endln:44:10 + \_module_inst: work@oh_dsync (work@oh_dsync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dsync.v, line:8:1, endln:44:10 |vpiRhs: \_constant: , line:11:26, endln:11:32 |vpiDecompile:TRUE @@ -21444,7 +21444,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:12:15, endln:12:35 |vpiParent: - \_module: work@oh_dsync (work@oh_dsync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dsync.v, line:8:1, endln:44:10 + \_module_inst: work@oh_dsync (work@oh_dsync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dsync.v, line:8:1, endln:44:10 |vpiRhs: \_constant: , line:12:26, endln:12:35 |vpiDecompile:DEFAULT @@ -21460,31 +21460,31 @@ design: (work@oh_fifo_async) |vpiNet: \_logic_net: (work@oh_dsync.clk), line:15:12, endln:15:15 |vpiParent: - \_module: work@oh_dsync (work@oh_dsync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dsync.v, line:8:1, endln:44:10 + \_module_inst: work@oh_dsync (work@oh_dsync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dsync.v, line:8:1, endln:44:10 |vpiName:clk |vpiFullName:work@oh_dsync.clk |vpiNet: \_logic_net: (work@oh_dsync.nreset), line:16:12, endln:16:18 |vpiParent: - \_module: work@oh_dsync (work@oh_dsync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dsync.v, line:8:1, endln:44:10 + \_module_inst: work@oh_dsync (work@oh_dsync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dsync.v, line:8:1, endln:44:10 |vpiName:nreset |vpiFullName:work@oh_dsync.nreset |vpiNet: \_logic_net: (work@oh_dsync.din), line:17:12, endln:17:15 |vpiParent: - \_module: work@oh_dsync (work@oh_dsync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dsync.v, line:8:1, endln:44:10 + \_module_inst: work@oh_dsync (work@oh_dsync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dsync.v, line:8:1, endln:44:10 |vpiName:din |vpiFullName:work@oh_dsync.din |vpiNet: \_logic_net: (work@oh_dsync.dout), line:18:12, endln:18:16 |vpiParent: - \_module: work@oh_dsync (work@oh_dsync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dsync.v, line:8:1, endln:44:10 + \_module_inst: work@oh_dsync (work@oh_dsync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dsync.v, line:8:1, endln:44:10 |vpiName:dout |vpiFullName:work@oh_dsync.dout |vpiPort: \_port: (clk), line:15:12, endln:15:15 |vpiParent: - \_module: work@oh_dsync (work@oh_dsync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dsync.v, line:8:1, endln:44:10 + \_module_inst: work@oh_dsync (work@oh_dsync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dsync.v, line:8:1, endln:44:10 |vpiName:clk |vpiDirection:1 |vpiLowConn: @@ -21496,7 +21496,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (nreset), line:16:12, endln:16:18 |vpiParent: - \_module: work@oh_dsync (work@oh_dsync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dsync.v, line:8:1, endln:44:10 + \_module_inst: work@oh_dsync (work@oh_dsync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dsync.v, line:8:1, endln:44:10 |vpiName:nreset |vpiDirection:1 |vpiLowConn: @@ -21508,7 +21508,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (din), line:17:12, endln:17:15 |vpiParent: - \_module: work@oh_dsync (work@oh_dsync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dsync.v, line:8:1, endln:44:10 + \_module_inst: work@oh_dsync (work@oh_dsync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dsync.v, line:8:1, endln:44:10 |vpiName:din |vpiDirection:1 |vpiLowConn: @@ -21520,7 +21520,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (dout), line:18:12, endln:18:16 |vpiParent: - \_module: work@oh_dsync (work@oh_dsync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dsync.v, line:8:1, endln:44:10 + \_module_inst: work@oh_dsync (work@oh_dsync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dsync.v, line:8:1, endln:44:10 |vpiName:dout |vpiDirection:2 |vpiLowConn: @@ -21530,14 +21530,14 @@ design: (work@oh_fifo_async) |vpiTypedef: \_logic_typespec: , line:18:12, endln:18:12 |uhdmallModules: -\_module: work@oh_edge2pulse (work@oh_edge2pulse), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_edge2pulse.v, line:8:1, endln:27:10 +\_module_inst: work@oh_edge2pulse (work@oh_edge2pulse), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_edge2pulse.v, line:8:1, endln:27:10 |vpiParent: \_design: (work@oh_fifo_async) |vpiFullName:work@oh_edge2pulse |vpiParameter: \_parameter: (work@oh_edge2pulse.N), line:9:16, endln:9:17 |vpiParent: - \_module: work@oh_edge2pulse (work@oh_edge2pulse), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_edge2pulse.v, line:8:1, endln:27:10 + \_module_inst: work@oh_edge2pulse (work@oh_edge2pulse), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_edge2pulse.v, line:8:1, endln:27:10 |UINT:1 |vpiTypespec: \_int_typespec: @@ -21546,7 +21546,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:9:16, endln:9:26 |vpiParent: - \_module: work@oh_edge2pulse (work@oh_edge2pulse), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_edge2pulse.v, line:8:1, endln:27:10 + \_module_inst: work@oh_edge2pulse (work@oh_edge2pulse), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_edge2pulse.v, line:8:1, endln:27:10 |vpiRhs: \_constant: , line:9:25, endln:9:26 |vpiDecompile:1 @@ -21562,38 +21562,38 @@ design: (work@oh_fifo_async) |vpiNet: \_logic_net: (work@oh_edge2pulse.clk), line:11:15, endln:11:18 |vpiParent: - \_module: work@oh_edge2pulse (work@oh_edge2pulse), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_edge2pulse.v, line:8:1, endln:27:10 + \_module_inst: work@oh_edge2pulse (work@oh_edge2pulse), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_edge2pulse.v, line:8:1, endln:27:10 |vpiName:clk |vpiFullName:work@oh_edge2pulse.clk |vpiNet: \_logic_net: (work@oh_edge2pulse.nreset), line:12:15, endln:12:21 |vpiParent: - \_module: work@oh_edge2pulse (work@oh_edge2pulse), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_edge2pulse.v, line:8:1, endln:27:10 + \_module_inst: work@oh_edge2pulse (work@oh_edge2pulse), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_edge2pulse.v, line:8:1, endln:27:10 |vpiName:nreset |vpiFullName:work@oh_edge2pulse.nreset |vpiNet: \_logic_net: (work@oh_edge2pulse.in), line:13:20, endln:13:22 |vpiParent: - \_module: work@oh_edge2pulse (work@oh_edge2pulse), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_edge2pulse.v, line:8:1, endln:27:10 + \_module_inst: work@oh_edge2pulse (work@oh_edge2pulse), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_edge2pulse.v, line:8:1, endln:27:10 |vpiName:in |vpiFullName:work@oh_edge2pulse.in |vpiNet: \_logic_net: (work@oh_edge2pulse.out), line:14:20, endln:14:23 |vpiParent: - \_module: work@oh_edge2pulse (work@oh_edge2pulse), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_edge2pulse.v, line:8:1, endln:27:10 + \_module_inst: work@oh_edge2pulse (work@oh_edge2pulse), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_edge2pulse.v, line:8:1, endln:27:10 |vpiName:out |vpiFullName:work@oh_edge2pulse.out |vpiNet: \_logic_net: (work@oh_edge2pulse.in_reg), line:17:19, endln:17:25 |vpiParent: - \_module: work@oh_edge2pulse (work@oh_edge2pulse), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_edge2pulse.v, line:8:1, endln:27:10 + \_module_inst: work@oh_edge2pulse (work@oh_edge2pulse), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_edge2pulse.v, line:8:1, endln:27:10 |vpiName:in_reg |vpiFullName:work@oh_edge2pulse.in_reg |vpiNetType:48 |vpiPort: \_port: (clk), line:11:15, endln:11:18 |vpiParent: - \_module: work@oh_edge2pulse (work@oh_edge2pulse), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_edge2pulse.v, line:8:1, endln:27:10 + \_module_inst: work@oh_edge2pulse (work@oh_edge2pulse), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_edge2pulse.v, line:8:1, endln:27:10 |vpiName:clk |vpiDirection:1 |vpiLowConn: @@ -21605,7 +21605,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (nreset), line:12:15, endln:12:21 |vpiParent: - \_module: work@oh_edge2pulse (work@oh_edge2pulse), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_edge2pulse.v, line:8:1, endln:27:10 + \_module_inst: work@oh_edge2pulse (work@oh_edge2pulse), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_edge2pulse.v, line:8:1, endln:27:10 |vpiName:nreset |vpiDirection:1 |vpiLowConn: @@ -21617,7 +21617,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (in), line:13:20, endln:13:22 |vpiParent: - \_module: work@oh_edge2pulse (work@oh_edge2pulse), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_edge2pulse.v, line:8:1, endln:27:10 + \_module_inst: work@oh_edge2pulse (work@oh_edge2pulse), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_edge2pulse.v, line:8:1, endln:27:10 |vpiName:in |vpiDirection:1 |vpiLowConn: @@ -21657,7 +21657,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (out), line:14:20, endln:14:23 |vpiParent: - \_module: work@oh_edge2pulse (work@oh_edge2pulse), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_edge2pulse.v, line:8:1, endln:27:10 + \_module_inst: work@oh_edge2pulse (work@oh_edge2pulse), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_edge2pulse.v, line:8:1, endln:27:10 |vpiName:out |vpiDirection:2 |vpiLowConn: @@ -21697,7 +21697,7 @@ design: (work@oh_fifo_async) |vpiProcess: \_always: , line:19:4, endln:23:37 |vpiParent: - \_module: work@oh_edge2pulse (work@oh_edge2pulse), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_edge2pulse.v, line:8:1, endln:27:10 + \_module_inst: work@oh_edge2pulse (work@oh_edge2pulse), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_edge2pulse.v, line:8:1, endln:27:10 |vpiStmt: \_event_control: , line:19:11, endln:19:44 |vpiParent: @@ -21864,7 +21864,7 @@ design: (work@oh_fifo_async) |vpiContAssign: \_cont_assign: , line:25:11, endln:25:51 |vpiParent: - \_module: work@oh_edge2pulse (work@oh_edge2pulse), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_edge2pulse.v, line:8:1, endln:27:10 + \_module_inst: work@oh_edge2pulse (work@oh_edge2pulse), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_edge2pulse.v, line:8:1, endln:27:10 |vpiRhs: \_operation: , line:25:25, endln:25:51 |vpiParent: @@ -21970,7 +21970,7 @@ design: (work@oh_fifo_async) |UINT:0 |vpiConstType:9 |uhdmallModules: -\_module: work@oh_edgealign (work@oh_edgealign), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_edgealign.v, line:22:1, endln:46:10 +\_module_inst: work@oh_edgealign (work@oh_edgealign), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_edgealign.v, line:22:1, endln:46:10 |vpiParent: \_design: (work@oh_fifo_async) |vpiFullName:work@oh_edgealign @@ -21979,40 +21979,40 @@ design: (work@oh_fifo_async) |vpiNet: \_logic_net: (work@oh_edgealign.clk45), line:33:11, endln:33:16 |vpiParent: - \_module: work@oh_edgealign (work@oh_edgealign), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_edgealign.v, line:22:1, endln:46:10 + \_module_inst: work@oh_edgealign (work@oh_edgealign), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_edgealign.v, line:22:1, endln:46:10 |vpiName:clk45 |vpiFullName:work@oh_edgealign.clk45 |vpiNetType:48 |vpiNet: \_logic_net: (work@oh_edgealign.clk90), line:34:11, endln:34:16 |vpiParent: - \_module: work@oh_edgealign (work@oh_edgealign), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_edgealign.v, line:22:1, endln:46:10 + \_module_inst: work@oh_edgealign (work@oh_edgealign), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_edgealign.v, line:22:1, endln:46:10 |vpiName:clk90 |vpiFullName:work@oh_edgealign.clk90 |vpiNetType:48 |vpiNet: \_logic_net: (work@oh_edgealign.firstedge), line:35:11, endln:35:20 |vpiParent: - \_module: work@oh_edgealign (work@oh_edgealign), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_edgealign.v, line:22:1, endln:46:10 + \_module_inst: work@oh_edgealign (work@oh_edgealign), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_edgealign.v, line:22:1, endln:46:10 |vpiName:firstedge |vpiFullName:work@oh_edgealign.firstedge |vpiNetType:48 |vpiNet: \_logic_net: (work@oh_edgealign.fastclk), line:26:4, endln:26:11 |vpiParent: - \_module: work@oh_edgealign (work@oh_edgealign), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_edgealign.v, line:22:1, endln:46:10 + \_module_inst: work@oh_edgealign (work@oh_edgealign), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_edgealign.v, line:22:1, endln:46:10 |vpiName:fastclk |vpiFullName:work@oh_edgealign.fastclk |vpiNet: \_logic_net: (work@oh_edgealign.slowclk), line:26:13, endln:26:20 |vpiParent: - \_module: work@oh_edgealign (work@oh_edgealign), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_edgealign.v, line:22:1, endln:46:10 + \_module_inst: work@oh_edgealign (work@oh_edgealign), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_edgealign.v, line:22:1, endln:46:10 |vpiName:slowclk |vpiFullName:work@oh_edgealign.slowclk |vpiPort: \_port: (firstedge), line:24:4, endln:24:13 |vpiParent: - \_module: work@oh_edgealign (work@oh_edgealign), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_edgealign.v, line:22:1, endln:46:10 + \_module_inst: work@oh_edgealign (work@oh_edgealign), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_edgealign.v, line:22:1, endln:46:10 |vpiName:firstedge |vpiDirection:2 |vpiLowConn: @@ -22024,7 +22024,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (fastclk), line:26:4, endln:26:11 |vpiParent: - \_module: work@oh_edgealign (work@oh_edgealign), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_edgealign.v, line:22:1, endln:46:10 + \_module_inst: work@oh_edgealign (work@oh_edgealign), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_edgealign.v, line:22:1, endln:46:10 |vpiName:fastclk |vpiDirection:1 |vpiLowConn: @@ -22036,7 +22036,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (slowclk), line:26:13, endln:26:20 |vpiParent: - \_module: work@oh_edgealign (work@oh_edgealign), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_edgealign.v, line:22:1, endln:46:10 + \_module_inst: work@oh_edgealign (work@oh_edgealign), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_edgealign.v, line:22:1, endln:46:10 |vpiName:slowclk |vpiDirection:1 |vpiLowConn: @@ -22048,7 +22048,7 @@ design: (work@oh_fifo_async) |vpiProcess: \_always: , line:37:4, endln:38:27 |vpiParent: - \_module: work@oh_edgealign (work@oh_edgealign), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_edgealign.v, line:22:1, endln:46:10 + \_module_inst: work@oh_edgealign (work@oh_edgealign), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_edgealign.v, line:22:1, endln:46:10 |vpiStmt: \_event_control: , line:37:11, endln:37:30 |vpiParent: @@ -22085,7 +22085,7 @@ design: (work@oh_fifo_async) |vpiProcess: \_always: , line:40:4, endln:44:9 |vpiParent: - \_module: work@oh_edgealign (work@oh_edgealign), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_edgealign.v, line:22:1, endln:46:10 + \_module_inst: work@oh_edgealign (work@oh_edgealign), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_edgealign.v, line:22:1, endln:46:10 |vpiStmt: \_event_control: , line:40:11, endln:40:30 |vpiParent: @@ -22158,14 +22158,14 @@ design: (work@oh_fifo_async) |vpiFullName:work@oh_edgealign.firstedge |vpiAlwaysType:1 |uhdmallModules: -\_module: work@oh_fall2pulse (work@oh_fall2pulse), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fall2pulse.v, line:8:1, endln:27:10 +\_module_inst: work@oh_fall2pulse (work@oh_fall2pulse), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fall2pulse.v, line:8:1, endln:27:10 |vpiParent: \_design: (work@oh_fifo_async) |vpiFullName:work@oh_fall2pulse |vpiParameter: \_parameter: (work@oh_fall2pulse.N), line:9:16, endln:9:17 |vpiParent: - \_module: work@oh_fall2pulse (work@oh_fall2pulse), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fall2pulse.v, line:8:1, endln:27:10 + \_module_inst: work@oh_fall2pulse (work@oh_fall2pulse), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fall2pulse.v, line:8:1, endln:27:10 |UINT:1 |vpiTypespec: \_int_typespec: @@ -22174,7 +22174,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:9:16, endln:9:21 |vpiParent: - \_module: work@oh_fall2pulse (work@oh_fall2pulse), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fall2pulse.v, line:8:1, endln:27:10 + \_module_inst: work@oh_fall2pulse (work@oh_fall2pulse), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fall2pulse.v, line:8:1, endln:27:10 |vpiRhs: \_constant: , line:9:20, endln:9:21 |vpiDecompile:1 @@ -22190,38 +22190,38 @@ design: (work@oh_fifo_async) |vpiNet: \_logic_net: (work@oh_fall2pulse.clk), line:11:15, endln:11:18 |vpiParent: - \_module: work@oh_fall2pulse (work@oh_fall2pulse), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fall2pulse.v, line:8:1, endln:27:10 + \_module_inst: work@oh_fall2pulse (work@oh_fall2pulse), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fall2pulse.v, line:8:1, endln:27:10 |vpiName:clk |vpiFullName:work@oh_fall2pulse.clk |vpiNet: \_logic_net: (work@oh_fall2pulse.nreset), line:12:15, endln:12:21 |vpiParent: - \_module: work@oh_fall2pulse (work@oh_fall2pulse), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fall2pulse.v, line:8:1, endln:27:10 + \_module_inst: work@oh_fall2pulse (work@oh_fall2pulse), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fall2pulse.v, line:8:1, endln:27:10 |vpiName:nreset |vpiFullName:work@oh_fall2pulse.nreset |vpiNet: \_logic_net: (work@oh_fall2pulse.in), line:13:20, endln:13:22 |vpiParent: - \_module: work@oh_fall2pulse (work@oh_fall2pulse), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fall2pulse.v, line:8:1, endln:27:10 + \_module_inst: work@oh_fall2pulse (work@oh_fall2pulse), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fall2pulse.v, line:8:1, endln:27:10 |vpiName:in |vpiFullName:work@oh_fall2pulse.in |vpiNet: \_logic_net: (work@oh_fall2pulse.out), line:14:20, endln:14:23 |vpiParent: - \_module: work@oh_fall2pulse (work@oh_fall2pulse), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fall2pulse.v, line:8:1, endln:27:10 + \_module_inst: work@oh_fall2pulse (work@oh_fall2pulse), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fall2pulse.v, line:8:1, endln:27:10 |vpiName:out |vpiFullName:work@oh_fall2pulse.out |vpiNet: \_logic_net: (work@oh_fall2pulse.in_reg), line:17:20, endln:17:26 |vpiParent: - \_module: work@oh_fall2pulse (work@oh_fall2pulse), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fall2pulse.v, line:8:1, endln:27:10 + \_module_inst: work@oh_fall2pulse (work@oh_fall2pulse), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fall2pulse.v, line:8:1, endln:27:10 |vpiName:in_reg |vpiFullName:work@oh_fall2pulse.in_reg |vpiNetType:48 |vpiPort: \_port: (clk), line:11:15, endln:11:18 |vpiParent: - \_module: work@oh_fall2pulse (work@oh_fall2pulse), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fall2pulse.v, line:8:1, endln:27:10 + \_module_inst: work@oh_fall2pulse (work@oh_fall2pulse), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fall2pulse.v, line:8:1, endln:27:10 |vpiName:clk |vpiDirection:1 |vpiLowConn: @@ -22233,7 +22233,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (nreset), line:12:15, endln:12:21 |vpiParent: - \_module: work@oh_fall2pulse (work@oh_fall2pulse), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fall2pulse.v, line:8:1, endln:27:10 + \_module_inst: work@oh_fall2pulse (work@oh_fall2pulse), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fall2pulse.v, line:8:1, endln:27:10 |vpiName:nreset |vpiDirection:1 |vpiLowConn: @@ -22245,7 +22245,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (in), line:13:20, endln:13:22 |vpiParent: - \_module: work@oh_fall2pulse (work@oh_fall2pulse), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fall2pulse.v, line:8:1, endln:27:10 + \_module_inst: work@oh_fall2pulse (work@oh_fall2pulse), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fall2pulse.v, line:8:1, endln:27:10 |vpiName:in |vpiDirection:1 |vpiLowConn: @@ -22285,7 +22285,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (out), line:14:20, endln:14:23 |vpiParent: - \_module: work@oh_fall2pulse (work@oh_fall2pulse), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fall2pulse.v, line:8:1, endln:27:10 + \_module_inst: work@oh_fall2pulse (work@oh_fall2pulse), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fall2pulse.v, line:8:1, endln:27:10 |vpiName:out |vpiDirection:2 |vpiLowConn: @@ -22325,7 +22325,7 @@ design: (work@oh_fifo_async) |vpiProcess: \_always: , line:19:4, endln:23:36 |vpiParent: - \_module: work@oh_fall2pulse (work@oh_fall2pulse), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fall2pulse.v, line:8:1, endln:27:10 + \_module_inst: work@oh_fall2pulse (work@oh_fall2pulse), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fall2pulse.v, line:8:1, endln:27:10 |vpiStmt: \_event_control: , line:19:11, endln:19:44 |vpiParent: @@ -22492,7 +22492,7 @@ design: (work@oh_fifo_async) |vpiContAssign: \_cont_assign: , line:25:11, endln:25:50 |vpiParent: - \_module: work@oh_fall2pulse (work@oh_fall2pulse), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fall2pulse.v, line:8:1, endln:27:10 + \_module_inst: work@oh_fall2pulse (work@oh_fall2pulse), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fall2pulse.v, line:8:1, endln:27:10 |vpiRhs: \_operation: , line:25:24, endln:25:50 |vpiParent: @@ -22603,14 +22603,14 @@ design: (work@oh_fifo_async) |UINT:0 |vpiConstType:9 |uhdmallModules: -\_module: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 +\_module_inst: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 |vpiParent: \_design: (work@oh_fifo_async) |vpiFullName:work@oh_fifo_async |vpiParameter: \_parameter: (work@oh_fifo_async.N), line:12:15, endln:12:16 |vpiParent: - \_module: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 + \_module_inst: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 |UINT:32 |vpiTypespec: \_int_typespec: @@ -22619,7 +22619,7 @@ design: (work@oh_fifo_async) |vpiParameter: \_parameter: (work@oh_fifo_async.DEPTH), line:13:15, endln:13:20 |vpiParent: - \_module: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 + \_module_inst: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 |UINT:32 |vpiTypespec: \_int_typespec: @@ -22628,7 +22628,7 @@ design: (work@oh_fifo_async) |vpiParameter: \_parameter: (work@oh_fifo_async.REG), line:14:15, endln:14:18 |vpiParent: - \_module: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 + \_module_inst: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 |UINT:1 |vpiTypespec: \_int_typespec: @@ -22637,13 +22637,13 @@ design: (work@oh_fifo_async) |vpiParameter: \_parameter: (work@oh_fifo_async.AW), line:15:15, endln:15:17 |vpiParent: - \_module: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 + \_module_inst: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 |vpiName:AW |vpiFullName:work@oh_fifo_async.AW |vpiParameter: \_parameter: (work@oh_fifo_async.SYNCPIPE), line:16:15, endln:16:23 |vpiParent: - \_module: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 + \_module_inst: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 |UINT:2 |vpiTypespec: \_int_typespec: @@ -22652,7 +22652,7 @@ design: (work@oh_fifo_async) |vpiParameter: \_parameter: (work@oh_fifo_async.SYN), line:17:15, endln:17:18 |vpiParent: - \_module: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 + \_module_inst: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 |STRING:TRUE |vpiTypespec: \_string_typespec: @@ -22661,7 +22661,7 @@ design: (work@oh_fifo_async) |vpiParameter: \_parameter: (work@oh_fifo_async.TYPE), line:18:15, endln:18:19 |vpiParent: - \_module: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 + \_module_inst: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 |STRING:DEFAULT |vpiTypespec: \_string_typespec: @@ -22670,13 +22670,13 @@ design: (work@oh_fifo_async) |vpiParameter: \_parameter: (work@oh_fifo_async.PROGFULL), line:19:15, endln:19:23 |vpiParent: - \_module: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 + \_module_inst: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 |vpiName:PROGFULL |vpiFullName:work@oh_fifo_async.PROGFULL |vpiParameter: \_parameter: (work@oh_fifo_async.SHAPE), line:20:15, endln:20:20 |vpiParent: - \_module: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 + \_module_inst: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 |STRING:SQUARE |vpiTypespec: \_string_typespec: @@ -22685,7 +22685,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:12:15, endln:12:28 |vpiParent: - \_module: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 + \_module_inst: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 |vpiRhs: \_constant: , line:12:26, endln:12:28 |vpiDecompile:32 @@ -22699,7 +22699,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:13:15, endln:13:28 |vpiParent: - \_module: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 + \_module_inst: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 |vpiRhs: \_constant: , line:13:26, endln:13:28 |vpiDecompile:32 @@ -22713,7 +22713,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:14:15, endln:14:27 |vpiParent: - \_module: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 + \_module_inst: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 |vpiRhs: \_constant: , line:14:26, endln:14:27 |vpiDecompile:1 @@ -22727,7 +22727,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:15:15, endln:15:39 |vpiParent: - \_module: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 + \_module_inst: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 |vpiRhs: \_sys_func_call: ($clog2), line:15:26, endln:15:39 |vpiArgument: @@ -22741,7 +22741,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:16:15, endln:16:27 |vpiParent: - \_module: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 + \_module_inst: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 |vpiRhs: \_constant: , line:16:26, endln:16:27 |vpiDecompile:2 @@ -22755,7 +22755,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:17:15, endln:17:32 |vpiParent: - \_module: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 + \_module_inst: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 |vpiRhs: \_constant: , line:17:26, endln:17:32 |vpiDecompile:TRUE @@ -22769,7 +22769,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:18:15, endln:18:35 |vpiParent: - \_module: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 + \_module_inst: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 |vpiRhs: \_constant: , line:18:26, endln:18:35 |vpiDecompile:DEFAULT @@ -22783,7 +22783,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:19:15, endln:19:33 |vpiParent: - \_module: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 + \_module_inst: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 |vpiRhs: \_operation: , line:19:26, endln:19:33 |vpiOpType:11 @@ -22805,7 +22805,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:20:15, endln:20:34 |vpiParent: - \_module: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 + \_module_inst: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 |vpiRhs: \_constant: , line:20:26, endln:20:34 |vpiDecompile:SQUARE @@ -22820,227 +22820,227 @@ design: (work@oh_fifo_async) |vpiNet: \_logic_net: (work@oh_fifo_async.nreset), line:23:16, endln:23:22 |vpiParent: - \_module: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 + \_module_inst: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 |vpiName:nreset |vpiFullName:work@oh_fifo_async.nreset |vpiNet: \_logic_net: (work@oh_fifo_async.wr_clk), line:25:16, endln:25:22 |vpiParent: - \_module: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 + \_module_inst: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 |vpiName:wr_clk |vpiFullName:work@oh_fifo_async.wr_clk |vpiNet: \_logic_net: (work@oh_fifo_async.wr_din), line:26:20, endln:26:26 |vpiParent: - \_module: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 + \_module_inst: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 |vpiName:wr_din |vpiFullName:work@oh_fifo_async.wr_din |vpiNet: \_logic_net: (work@oh_fifo_async.wr_en), line:27:16, endln:27:21 |vpiParent: - \_module: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 + \_module_inst: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 |vpiName:wr_en |vpiFullName:work@oh_fifo_async.wr_en |vpiNet: \_logic_net: (work@oh_fifo_async.wr_full), line:28:17, endln:28:24 |vpiParent: - \_module: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 + \_module_inst: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 |vpiName:wr_full |vpiFullName:work@oh_fifo_async.wr_full |vpiNet: \_logic_net: (work@oh_fifo_async.wr_almost_full), line:29:17, endln:29:31 |vpiParent: - \_module: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 + \_module_inst: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 |vpiName:wr_almost_full |vpiFullName:work@oh_fifo_async.wr_almost_full |vpiNet: \_logic_net: (work@oh_fifo_async.wr_prog_full), line:30:17, endln:30:29 |vpiParent: - \_module: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 + \_module_inst: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 |vpiName:wr_prog_full |vpiFullName:work@oh_fifo_async.wr_prog_full |vpiNet: \_logic_net: (work@oh_fifo_async.wr_count), line:31:21, endln:31:29 |vpiParent: - \_module: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 + \_module_inst: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 |vpiName:wr_count |vpiFullName:work@oh_fifo_async.wr_count |vpiNet: \_logic_net: (work@oh_fifo_async.rd_clk), line:33:16, endln:33:22 |vpiParent: - \_module: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 + \_module_inst: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 |vpiName:rd_clk |vpiFullName:work@oh_fifo_async.rd_clk |vpiNet: \_logic_net: (work@oh_fifo_async.rd_dout), line:34:20, endln:34:27 |vpiParent: - \_module: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 + \_module_inst: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 |vpiName:rd_dout |vpiFullName:work@oh_fifo_async.rd_dout |vpiNet: \_logic_net: (work@oh_fifo_async.rd_en), line:35:16, endln:35:21 |vpiParent: - \_module: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 + \_module_inst: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 |vpiName:rd_en |vpiFullName:work@oh_fifo_async.rd_en |vpiNet: \_logic_net: (work@oh_fifo_async.rd_empty), line:36:17, endln:36:25 |vpiParent: - \_module: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 + \_module_inst: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 |vpiName:rd_empty |vpiFullName:work@oh_fifo_async.rd_empty |vpiNet: \_logic_net: (work@oh_fifo_async.rd_count), line:37:21, endln:37:29 |vpiParent: - \_module: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 + \_module_inst: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 |vpiName:rd_count |vpiFullName:work@oh_fifo_async.rd_count |vpiNet: \_logic_net: (work@oh_fifo_async.bist_en), line:39:16, endln:39:23 |vpiParent: - \_module: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 + \_module_inst: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 |vpiName:bist_en |vpiFullName:work@oh_fifo_async.bist_en |vpiNet: \_logic_net: (work@oh_fifo_async.bist_we), line:40:16, endln:40:23 |vpiParent: - \_module: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 + \_module_inst: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 |vpiName:bist_we |vpiFullName:work@oh_fifo_async.bist_we |vpiNet: \_logic_net: (work@oh_fifo_async.bist_wem), line:41:20, endln:41:28 |vpiParent: - \_module: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 + \_module_inst: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 |vpiName:bist_wem |vpiFullName:work@oh_fifo_async.bist_wem |vpiNet: \_logic_net: (work@oh_fifo_async.bist_addr), line:42:21, endln:42:30 |vpiParent: - \_module: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 + \_module_inst: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 |vpiName:bist_addr |vpiFullName:work@oh_fifo_async.bist_addr |vpiNet: \_logic_net: (work@oh_fifo_async.bist_din), line:43:20, endln:43:28 |vpiParent: - \_module: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 + \_module_inst: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 |vpiName:bist_din |vpiFullName:work@oh_fifo_async.bist_din |vpiNet: \_logic_net: (work@oh_fifo_async.bist_dout), line:44:20, endln:44:29 |vpiParent: - \_module: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 + \_module_inst: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 |vpiName:bist_dout |vpiFullName:work@oh_fifo_async.bist_dout |vpiNet: \_logic_net: (work@oh_fifo_async.shutdown), line:46:16, endln:46:24 |vpiParent: - \_module: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 + \_module_inst: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 |vpiName:shutdown |vpiFullName:work@oh_fifo_async.shutdown |vpiNet: \_logic_net: (work@oh_fifo_async.vss), line:47:16, endln:47:19 |vpiParent: - \_module: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 + \_module_inst: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 |vpiName:vss |vpiFullName:work@oh_fifo_async.vss |vpiNet: \_logic_net: (work@oh_fifo_async.vdd), line:48:16, endln:48:19 |vpiParent: - \_module: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 + \_module_inst: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 |vpiName:vdd |vpiFullName:work@oh_fifo_async.vdd |vpiNet: \_logic_net: (work@oh_fifo_async.vddio), line:49:16, endln:49:21 |vpiParent: - \_module: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 + \_module_inst: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 |vpiName:vddio |vpiFullName:work@oh_fifo_async.vddio |vpiNet: \_logic_net: (work@oh_fifo_async.memconfig), line:50:21, endln:50:30 |vpiParent: - \_module: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 + \_module_inst: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 |vpiName:memconfig |vpiFullName:work@oh_fifo_async.memconfig |vpiNet: \_logic_net: (work@oh_fifo_async.memrepair), line:51:21, endln:51:30 |vpiParent: - \_module: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 + \_module_inst: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 |vpiName:memrepair |vpiFullName:work@oh_fifo_async.memrepair |vpiNet: \_logic_net: (work@oh_fifo_async.wr_addr), line:55:17, endln:55:24 |vpiParent: - \_module: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 + \_module_inst: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 |vpiName:wr_addr |vpiFullName:work@oh_fifo_async.wr_addr |vpiNetType:48 |vpiNet: \_logic_net: (work@oh_fifo_async.rd_addr), line:56:17, endln:56:24 |vpiParent: - \_module: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 + \_module_inst: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 |vpiName:rd_addr |vpiFullName:work@oh_fifo_async.rd_addr |vpiNetType:48 |vpiNet: \_logic_net: (work@oh_fifo_async.wr_addr_gray), line:57:18, endln:57:30 |vpiParent: - \_module: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 + \_module_inst: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 |vpiName:wr_addr_gray |vpiFullName:work@oh_fifo_async.wr_addr_gray |vpiNetType:1 |vpiNet: \_logic_net: (work@oh_fifo_async.wr_addr_gray_sync), line:58:18, endln:58:35 |vpiParent: - \_module: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 + \_module_inst: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 |vpiName:wr_addr_gray_sync |vpiFullName:work@oh_fifo_async.wr_addr_gray_sync |vpiNetType:1 |vpiNet: \_logic_net: (work@oh_fifo_async.rd_addr_gray), line:59:18, endln:59:30 |vpiParent: - \_module: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 + \_module_inst: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 |vpiName:rd_addr_gray |vpiFullName:work@oh_fifo_async.rd_addr_gray |vpiNetType:1 |vpiNet: \_logic_net: (work@oh_fifo_async.rd_addr_gray_sync), line:60:18, endln:60:35 |vpiParent: - \_module: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 + \_module_inst: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 |vpiName:rd_addr_gray_sync |vpiFullName:work@oh_fifo_async.rd_addr_gray_sync |vpiNetType:1 |vpiNet: \_logic_net: (work@oh_fifo_async.rd_addr_sync), line:61:18, endln:61:30 |vpiParent: - \_module: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 + \_module_inst: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 |vpiName:rd_addr_sync |vpiFullName:work@oh_fifo_async.rd_addr_sync |vpiNetType:1 |vpiNet: \_logic_net: (work@oh_fifo_async.fifo_write), line:62:11, endln:62:21 |vpiParent: - \_module: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 + \_module_inst: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 |vpiName:fifo_write |vpiFullName:work@oh_fifo_async.fifo_write |vpiNetType:1 |vpiNet: \_logic_net: (work@oh_fifo_async.rd_nreset), line:63:11, endln:63:20 |vpiParent: - \_module: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 + \_module_inst: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 |vpiName:rd_nreset |vpiFullName:work@oh_fifo_async.rd_nreset |vpiNetType:1 |vpiNet: \_logic_net: (work@oh_fifo_async.wr_nreset), line:64:11, endln:64:20 |vpiParent: - \_module: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 + \_module_inst: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 |vpiName:wr_nreset |vpiFullName:work@oh_fifo_async.wr_nreset |vpiNetType:1 |vpiPort: \_port: (nreset), line:23:16, endln:23:22 |vpiParent: - \_module: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 + \_module_inst: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 |vpiName:nreset |vpiDirection:1 |vpiLowConn: @@ -23052,7 +23052,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (wr_clk), line:25:16, endln:25:22 |vpiParent: - \_module: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 + \_module_inst: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 |vpiName:wr_clk |vpiDirection:1 |vpiLowConn: @@ -23064,7 +23064,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (wr_din), line:26:20, endln:26:26 |vpiParent: - \_module: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 + \_module_inst: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 |vpiName:wr_din |vpiDirection:1 |vpiLowConn: @@ -23104,7 +23104,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (wr_en), line:27:16, endln:27:21 |vpiParent: - \_module: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 + \_module_inst: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 |vpiName:wr_en |vpiDirection:1 |vpiLowConn: @@ -23116,7 +23116,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (wr_full), line:28:17, endln:28:24 |vpiParent: - \_module: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 + \_module_inst: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 |vpiName:wr_full |vpiDirection:2 |vpiLowConn: @@ -23128,7 +23128,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (wr_almost_full), line:29:17, endln:29:31 |vpiParent: - \_module: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 + \_module_inst: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 |vpiName:wr_almost_full |vpiDirection:2 |vpiLowConn: @@ -23140,7 +23140,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (wr_prog_full), line:30:17, endln:30:29 |vpiParent: - \_module: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 + \_module_inst: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 |vpiName:wr_prog_full |vpiDirection:2 |vpiLowConn: @@ -23152,7 +23152,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (wr_count), line:31:21, endln:31:29 |vpiParent: - \_module: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 + \_module_inst: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 |vpiName:wr_count |vpiDirection:2 |vpiLowConn: @@ -23192,7 +23192,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (rd_clk), line:33:16, endln:33:22 |vpiParent: - \_module: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 + \_module_inst: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 |vpiName:rd_clk |vpiDirection:1 |vpiLowConn: @@ -23204,7 +23204,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (rd_dout), line:34:20, endln:34:27 |vpiParent: - \_module: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 + \_module_inst: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 |vpiName:rd_dout |vpiDirection:2 |vpiLowConn: @@ -23244,7 +23244,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (rd_en), line:35:16, endln:35:21 |vpiParent: - \_module: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 + \_module_inst: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 |vpiName:rd_en |vpiDirection:1 |vpiLowConn: @@ -23256,7 +23256,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (rd_empty), line:36:17, endln:36:25 |vpiParent: - \_module: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 + \_module_inst: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 |vpiName:rd_empty |vpiDirection:2 |vpiLowConn: @@ -23268,7 +23268,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (rd_count), line:37:21, endln:37:29 |vpiParent: - \_module: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 + \_module_inst: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 |vpiName:rd_count |vpiDirection:2 |vpiLowConn: @@ -23308,7 +23308,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (bist_en), line:39:16, endln:39:23 |vpiParent: - \_module: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 + \_module_inst: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 |vpiName:bist_en |vpiDirection:1 |vpiLowConn: @@ -23320,7 +23320,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (bist_we), line:40:16, endln:40:23 |vpiParent: - \_module: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 + \_module_inst: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 |vpiName:bist_we |vpiDirection:1 |vpiLowConn: @@ -23332,7 +23332,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (bist_wem), line:41:20, endln:41:28 |vpiParent: - \_module: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 + \_module_inst: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 |vpiName:bist_wem |vpiDirection:1 |vpiLowConn: @@ -23372,7 +23372,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (bist_addr), line:42:21, endln:42:30 |vpiParent: - \_module: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 + \_module_inst: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 |vpiName:bist_addr |vpiDirection:1 |vpiLowConn: @@ -23412,7 +23412,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (bist_din), line:43:20, endln:43:28 |vpiParent: - \_module: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 + \_module_inst: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 |vpiName:bist_din |vpiDirection:1 |vpiLowConn: @@ -23452,7 +23452,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (bist_dout), line:44:20, endln:44:29 |vpiParent: - \_module: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 + \_module_inst: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 |vpiName:bist_dout |vpiDirection:1 |vpiLowConn: @@ -23492,7 +23492,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (shutdown), line:46:16, endln:46:24 |vpiParent: - \_module: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 + \_module_inst: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 |vpiName:shutdown |vpiDirection:1 |vpiLowConn: @@ -23504,7 +23504,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (vss), line:47:16, endln:47:19 |vpiParent: - \_module: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 + \_module_inst: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 |vpiName:vss |vpiDirection:1 |vpiLowConn: @@ -23516,7 +23516,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (vdd), line:48:16, endln:48:19 |vpiParent: - \_module: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 + \_module_inst: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 |vpiName:vdd |vpiDirection:1 |vpiLowConn: @@ -23528,7 +23528,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (vddio), line:49:16, endln:49:21 |vpiParent: - \_module: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 + \_module_inst: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 |vpiName:vddio |vpiDirection:1 |vpiLowConn: @@ -23540,7 +23540,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (memconfig), line:50:21, endln:50:30 |vpiParent: - \_module: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 + \_module_inst: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 |vpiName:memconfig |vpiDirection:1 |vpiLowConn: @@ -23570,7 +23570,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (memrepair), line:51:21, endln:51:30 |vpiParent: - \_module: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 + \_module_inst: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 |vpiName:memrepair |vpiDirection:1 |vpiLowConn: @@ -23600,7 +23600,7 @@ design: (work@oh_fifo_async) |vpiProcess: \_always: , line:90:4, endln:94:47 |vpiParent: - \_module: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 + \_module_inst: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 |vpiStmt: \_event_control: , line:90:11, endln:90:51 |vpiParent: @@ -23759,7 +23759,7 @@ design: (work@oh_fifo_async) |vpiProcess: \_always: , line:100:4, endln:104:45 |vpiParent: - \_module: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 + \_module_inst: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 |vpiStmt: \_event_control: , line:100:11, endln:100:51 |vpiParent: @@ -23919,7 +23919,7 @@ design: (work@oh_fifo_async) |vpiModuleArray: \_module_array: (work@oh_dsync), line:121:4, endln:121:11 |vpiParent: - \_module: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 + \_module_inst: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 |vpiName:wr_sync |vpiFullName:work@oh_dsync |vpiRange: @@ -23943,7 +23943,7 @@ design: (work@oh_fifo_async) |vpiModuleArray: \_module_array: (work@oh_dsync), line:137:4, endln:137:11 |vpiParent: - \_module: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 + \_module_inst: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 |vpiName:rd_sync |vpiFullName:work@oh_dsync |vpiRange: @@ -23967,7 +23967,7 @@ design: (work@oh_fifo_async) |vpiContAssign: \_cont_assign: , line:88:11, endln:88:40 |vpiParent: - \_module: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 + \_module_inst: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 |vpiRhs: \_operation: , line:88:24, endln:88:40 |vpiParent: @@ -24005,7 +24005,7 @@ design: (work@oh_fifo_async) |vpiContAssign: \_cont_assign: , line:147:11, endln:147:70 |vpiParent: - \_module: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 + \_module_inst: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 |vpiRhs: \_operation: , line:147:24, endln:147:69 |vpiParent: @@ -24063,7 +24063,7 @@ design: (work@oh_fifo_async) |vpiContAssign: \_cont_assign: , line:150:11, endln:151:46 |vpiParent: - \_module: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 + \_module_inst: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 |vpiRhs: \_operation: , line:150:23, endln:151:46 |vpiParent: @@ -24187,14 +24187,14 @@ design: (work@oh_fifo_async) |vpiActual: \_logic_net: (work@oh_fifo_async.wr_full), line:28:17, endln:28:24 |uhdmallModules: -\_module: work@oh_fifo_cdc (work@oh_fifo_cdc), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_cdc.v, line:8:1, endln:86:10 +\_module_inst: work@oh_fifo_cdc (work@oh_fifo_cdc), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_cdc.v, line:8:1, endln:86:10 |vpiParent: \_design: (work@oh_fifo_async) |vpiFullName:work@oh_fifo_cdc |vpiParameter: \_parameter: (work@oh_fifo_cdc.N), line:9:15, endln:9:16 |vpiParent: - \_module: work@oh_fifo_cdc (work@oh_fifo_cdc), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_cdc.v, line:8:1, endln:86:10 + \_module_inst: work@oh_fifo_cdc (work@oh_fifo_cdc), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_cdc.v, line:8:1, endln:86:10 |UINT:32 |vpiTypespec: \_int_typespec: @@ -24203,7 +24203,7 @@ design: (work@oh_fifo_async) |vpiParameter: \_parameter: (work@oh_fifo_cdc.DEPTH), line:10:15, endln:10:20 |vpiParent: - \_module: work@oh_fifo_cdc (work@oh_fifo_cdc), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_cdc.v, line:8:1, endln:86:10 + \_module_inst: work@oh_fifo_cdc (work@oh_fifo_cdc), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_cdc.v, line:8:1, endln:86:10 |UINT:32 |vpiTypespec: \_int_typespec: @@ -24212,7 +24212,7 @@ design: (work@oh_fifo_async) |vpiParameter: \_parameter: (work@oh_fifo_cdc.SYN), line:11:15, endln:11:18 |vpiParent: - \_module: work@oh_fifo_cdc (work@oh_fifo_cdc), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_cdc.v, line:8:1, endln:86:10 + \_module_inst: work@oh_fifo_cdc (work@oh_fifo_cdc), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_cdc.v, line:8:1, endln:86:10 |STRING:TRUE |vpiTypespec: \_string_typespec: @@ -24221,7 +24221,7 @@ design: (work@oh_fifo_async) |vpiParameter: \_parameter: (work@oh_fifo_cdc.TYPE), line:12:15, endln:12:19 |vpiParent: - \_module: work@oh_fifo_cdc (work@oh_fifo_cdc), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_cdc.v, line:8:1, endln:86:10 + \_module_inst: work@oh_fifo_cdc (work@oh_fifo_cdc), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_cdc.v, line:8:1, endln:86:10 |STRING:DEFAULT |vpiTypespec: \_string_typespec: @@ -24230,13 +24230,13 @@ design: (work@oh_fifo_async) |vpiParameter: \_parameter: (work@oh_fifo_cdc.AW), line:13:15, endln:13:17 |vpiParent: - \_module: work@oh_fifo_cdc (work@oh_fifo_cdc), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_cdc.v, line:8:1, endln:86:10 + \_module_inst: work@oh_fifo_cdc (work@oh_fifo_cdc), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_cdc.v, line:8:1, endln:86:10 |vpiName:AW |vpiFullName:work@oh_fifo_cdc.AW |vpiParamAssign: \_param_assign: , line:9:15, endln:9:25 |vpiParent: - \_module: work@oh_fifo_cdc (work@oh_fifo_cdc), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_cdc.v, line:8:1, endln:86:10 + \_module_inst: work@oh_fifo_cdc (work@oh_fifo_cdc), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_cdc.v, line:8:1, endln:86:10 |vpiRhs: \_constant: , line:9:23, endln:9:25 |vpiDecompile:32 @@ -24250,7 +24250,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:10:15, endln:10:25 |vpiParent: - \_module: work@oh_fifo_cdc (work@oh_fifo_cdc), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_cdc.v, line:8:1, endln:86:10 + \_module_inst: work@oh_fifo_cdc (work@oh_fifo_cdc), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_cdc.v, line:8:1, endln:86:10 |vpiRhs: \_constant: , line:10:23, endln:10:25 |vpiDecompile:32 @@ -24264,7 +24264,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:11:15, endln:11:29 |vpiParent: - \_module: work@oh_fifo_cdc (work@oh_fifo_cdc), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_cdc.v, line:8:1, endln:86:10 + \_module_inst: work@oh_fifo_cdc (work@oh_fifo_cdc), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_cdc.v, line:8:1, endln:86:10 |vpiRhs: \_constant: , line:11:23, endln:11:29 |vpiDecompile:TRUE @@ -24278,7 +24278,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:12:15, endln:12:32 |vpiParent: - \_module: work@oh_fifo_cdc (work@oh_fifo_cdc), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_cdc.v, line:8:1, endln:86:10 + \_module_inst: work@oh_fifo_cdc (work@oh_fifo_cdc), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_cdc.v, line:8:1, endln:86:10 |vpiRhs: \_constant: , line:12:23, endln:12:32 |vpiDecompile:DEFAULT @@ -24292,7 +24292,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:13:15, endln:13:36 |vpiParent: - \_module: work@oh_fifo_cdc (work@oh_fifo_cdc), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_cdc.v, line:8:1, endln:86:10 + \_module_inst: work@oh_fifo_cdc (work@oh_fifo_cdc), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_cdc.v, line:8:1, endln:86:10 |vpiRhs: \_sys_func_call: ($clog2), line:13:23, endln:13:36 |vpiArgument: @@ -24308,80 +24308,80 @@ design: (work@oh_fifo_async) |vpiNet: \_logic_net: (work@oh_fifo_cdc.nreset), line:16:15, endln:16:21 |vpiParent: - \_module: work@oh_fifo_cdc (work@oh_fifo_cdc), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_cdc.v, line:8:1, endln:86:10 + \_module_inst: work@oh_fifo_cdc (work@oh_fifo_cdc), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_cdc.v, line:8:1, endln:86:10 |vpiName:nreset |vpiFullName:work@oh_fifo_cdc.nreset |vpiNet: \_logic_net: (work@oh_fifo_cdc.clk_in), line:18:15, endln:18:21 |vpiParent: - \_module: work@oh_fifo_cdc (work@oh_fifo_cdc), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_cdc.v, line:8:1, endln:86:10 + \_module_inst: work@oh_fifo_cdc (work@oh_fifo_cdc), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_cdc.v, line:8:1, endln:86:10 |vpiName:clk_in |vpiFullName:work@oh_fifo_cdc.clk_in |vpiNet: \_logic_net: (work@oh_fifo_cdc.valid_in), line:19:15, endln:19:23 |vpiParent: - \_module: work@oh_fifo_cdc (work@oh_fifo_cdc), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_cdc.v, line:8:1, endln:86:10 + \_module_inst: work@oh_fifo_cdc (work@oh_fifo_cdc), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_cdc.v, line:8:1, endln:86:10 |vpiName:valid_in |vpiFullName:work@oh_fifo_cdc.valid_in |vpiNet: \_logic_net: (work@oh_fifo_cdc.packet_in), line:20:20, endln:20:29 |vpiParent: - \_module: work@oh_fifo_cdc (work@oh_fifo_cdc), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_cdc.v, line:8:1, endln:86:10 + \_module_inst: work@oh_fifo_cdc (work@oh_fifo_cdc), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_cdc.v, line:8:1, endln:86:10 |vpiName:packet_in |vpiFullName:work@oh_fifo_cdc.packet_in |vpiNet: \_logic_net: (work@oh_fifo_cdc.ready_out), line:21:16, endln:21:25 |vpiParent: - \_module: work@oh_fifo_cdc (work@oh_fifo_cdc), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_cdc.v, line:8:1, endln:86:10 + \_module_inst: work@oh_fifo_cdc (work@oh_fifo_cdc), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_cdc.v, line:8:1, endln:86:10 |vpiName:ready_out |vpiFullName:work@oh_fifo_cdc.ready_out |vpiNet: \_logic_net: (work@oh_fifo_cdc.clk_out), line:23:15, endln:23:22 |vpiParent: - \_module: work@oh_fifo_cdc (work@oh_fifo_cdc), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_cdc.v, line:8:1, endln:86:10 + \_module_inst: work@oh_fifo_cdc (work@oh_fifo_cdc), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_cdc.v, line:8:1, endln:86:10 |vpiName:clk_out |vpiFullName:work@oh_fifo_cdc.clk_out |vpiNet: \_logic_net: (work@oh_fifo_cdc.valid_out), line:24:20, endln:24:29 |vpiParent: - \_module: work@oh_fifo_cdc (work@oh_fifo_cdc), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_cdc.v, line:8:1, endln:86:10 + \_module_inst: work@oh_fifo_cdc (work@oh_fifo_cdc), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_cdc.v, line:8:1, endln:86:10 |vpiName:valid_out |vpiFullName:work@oh_fifo_cdc.valid_out |vpiNetType:48 |vpiNet: \_logic_net: (work@oh_fifo_cdc.packet_out), line:25:20, endln:25:30 |vpiParent: - \_module: work@oh_fifo_cdc (work@oh_fifo_cdc), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_cdc.v, line:8:1, endln:86:10 + \_module_inst: work@oh_fifo_cdc (work@oh_fifo_cdc), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_cdc.v, line:8:1, endln:86:10 |vpiName:packet_out |vpiFullName:work@oh_fifo_cdc.packet_out |vpiNet: \_logic_net: (work@oh_fifo_cdc.ready_in), line:26:15, endln:26:23 |vpiParent: - \_module: work@oh_fifo_cdc (work@oh_fifo_cdc), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_cdc.v, line:8:1, endln:86:10 + \_module_inst: work@oh_fifo_cdc (work@oh_fifo_cdc), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_cdc.v, line:8:1, endln:86:10 |vpiName:ready_in |vpiFullName:work@oh_fifo_cdc.ready_in |vpiNet: \_logic_net: (work@oh_fifo_cdc.prog_full), line:28:16, endln:28:25 |vpiParent: - \_module: work@oh_fifo_cdc (work@oh_fifo_cdc), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_cdc.v, line:8:1, endln:86:10 + \_module_inst: work@oh_fifo_cdc (work@oh_fifo_cdc), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_cdc.v, line:8:1, endln:86:10 |vpiName:prog_full |vpiFullName:work@oh_fifo_cdc.prog_full |vpiNet: \_logic_net: (work@oh_fifo_cdc.full), line:29:16, endln:29:20 |vpiParent: - \_module: work@oh_fifo_cdc (work@oh_fifo_cdc), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_cdc.v, line:8:1, endln:86:10 + \_module_inst: work@oh_fifo_cdc (work@oh_fifo_cdc), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_cdc.v, line:8:1, endln:86:10 |vpiName:full |vpiFullName:work@oh_fifo_cdc.full |vpiNet: \_logic_net: (work@oh_fifo_cdc.empty), line:30:16, endln:30:21 |vpiParent: - \_module: work@oh_fifo_cdc (work@oh_fifo_cdc), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_cdc.v, line:8:1, endln:86:10 + \_module_inst: work@oh_fifo_cdc (work@oh_fifo_cdc), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_cdc.v, line:8:1, endln:86:10 |vpiName:empty |vpiFullName:work@oh_fifo_cdc.empty |vpiPort: \_port: (nreset), line:16:15, endln:16:21 |vpiParent: - \_module: work@oh_fifo_cdc (work@oh_fifo_cdc), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_cdc.v, line:8:1, endln:86:10 + \_module_inst: work@oh_fifo_cdc (work@oh_fifo_cdc), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_cdc.v, line:8:1, endln:86:10 |vpiName:nreset |vpiDirection:1 |vpiLowConn: @@ -24393,7 +24393,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (clk_in), line:18:15, endln:18:21 |vpiParent: - \_module: work@oh_fifo_cdc (work@oh_fifo_cdc), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_cdc.v, line:8:1, endln:86:10 + \_module_inst: work@oh_fifo_cdc (work@oh_fifo_cdc), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_cdc.v, line:8:1, endln:86:10 |vpiName:clk_in |vpiDirection:1 |vpiLowConn: @@ -24405,7 +24405,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (valid_in), line:19:15, endln:19:23 |vpiParent: - \_module: work@oh_fifo_cdc (work@oh_fifo_cdc), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_cdc.v, line:8:1, endln:86:10 + \_module_inst: work@oh_fifo_cdc (work@oh_fifo_cdc), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_cdc.v, line:8:1, endln:86:10 |vpiName:valid_in |vpiDirection:1 |vpiLowConn: @@ -24417,7 +24417,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (packet_in), line:20:20, endln:20:29 |vpiParent: - \_module: work@oh_fifo_cdc (work@oh_fifo_cdc), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_cdc.v, line:8:1, endln:86:10 + \_module_inst: work@oh_fifo_cdc (work@oh_fifo_cdc), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_cdc.v, line:8:1, endln:86:10 |vpiName:packet_in |vpiDirection:1 |vpiLowConn: @@ -24457,7 +24457,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (ready_out), line:21:16, endln:21:25 |vpiParent: - \_module: work@oh_fifo_cdc (work@oh_fifo_cdc), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_cdc.v, line:8:1, endln:86:10 + \_module_inst: work@oh_fifo_cdc (work@oh_fifo_cdc), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_cdc.v, line:8:1, endln:86:10 |vpiName:ready_out |vpiDirection:2 |vpiLowConn: @@ -24469,7 +24469,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (clk_out), line:23:15, endln:23:22 |vpiParent: - \_module: work@oh_fifo_cdc (work@oh_fifo_cdc), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_cdc.v, line:8:1, endln:86:10 + \_module_inst: work@oh_fifo_cdc (work@oh_fifo_cdc), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_cdc.v, line:8:1, endln:86:10 |vpiName:clk_out |vpiDirection:1 |vpiLowConn: @@ -24481,7 +24481,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (valid_out), line:24:20, endln:24:29 |vpiParent: - \_module: work@oh_fifo_cdc (work@oh_fifo_cdc), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_cdc.v, line:8:1, endln:86:10 + \_module_inst: work@oh_fifo_cdc (work@oh_fifo_cdc), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_cdc.v, line:8:1, endln:86:10 |vpiName:valid_out |vpiDirection:2 |vpiLowConn: @@ -24493,7 +24493,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (packet_out), line:25:20, endln:25:30 |vpiParent: - \_module: work@oh_fifo_cdc (work@oh_fifo_cdc), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_cdc.v, line:8:1, endln:86:10 + \_module_inst: work@oh_fifo_cdc (work@oh_fifo_cdc), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_cdc.v, line:8:1, endln:86:10 |vpiName:packet_out |vpiDirection:2 |vpiLowConn: @@ -24533,7 +24533,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (ready_in), line:26:15, endln:26:23 |vpiParent: - \_module: work@oh_fifo_cdc (work@oh_fifo_cdc), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_cdc.v, line:8:1, endln:86:10 + \_module_inst: work@oh_fifo_cdc (work@oh_fifo_cdc), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_cdc.v, line:8:1, endln:86:10 |vpiName:ready_in |vpiDirection:1 |vpiLowConn: @@ -24545,7 +24545,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (prog_full), line:28:16, endln:28:25 |vpiParent: - \_module: work@oh_fifo_cdc (work@oh_fifo_cdc), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_cdc.v, line:8:1, endln:86:10 + \_module_inst: work@oh_fifo_cdc (work@oh_fifo_cdc), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_cdc.v, line:8:1, endln:86:10 |vpiName:prog_full |vpiDirection:2 |vpiLowConn: @@ -24557,7 +24557,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (full), line:29:16, endln:29:20 |vpiParent: - \_module: work@oh_fifo_cdc (work@oh_fifo_cdc), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_cdc.v, line:8:1, endln:86:10 + \_module_inst: work@oh_fifo_cdc (work@oh_fifo_cdc), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_cdc.v, line:8:1, endln:86:10 |vpiName:full |vpiDirection:2 |vpiLowConn: @@ -24569,7 +24569,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (empty), line:30:16, endln:30:21 |vpiParent: - \_module: work@oh_fifo_cdc (work@oh_fifo_cdc), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_cdc.v, line:8:1, endln:86:10 + \_module_inst: work@oh_fifo_cdc (work@oh_fifo_cdc), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_cdc.v, line:8:1, endln:86:10 |vpiName:empty |vpiDirection:2 |vpiLowConn: @@ -24581,7 +24581,7 @@ design: (work@oh_fifo_async) |vpiProcess: \_always: , line:46:4, endln:50:27 |vpiParent: - \_module: work@oh_fifo_cdc (work@oh_fifo_cdc), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_cdc.v, line:8:1, endln:86:10 + \_module_inst: work@oh_fifo_cdc (work@oh_fifo_cdc), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_cdc.v, line:8:1, endln:86:10 |vpiStmt: \_event_control: , line:46:11, endln:46:52 |vpiParent: @@ -24672,7 +24672,7 @@ design: (work@oh_fifo_async) |vpiContAssign: \_cont_assign: , line:34:11, endln:34:30 |vpiParent: - \_module: work@oh_fifo_cdc (work@oh_fifo_cdc), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_cdc.v, line:8:1, endln:86:10 + \_module_inst: work@oh_fifo_cdc (work@oh_fifo_cdc), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_cdc.v, line:8:1, endln:86:10 |vpiRhs: \_ref_obj: (work@oh_fifo_cdc.valid_in), line:34:22, endln:34:30 |vpiParent: @@ -24688,7 +24688,7 @@ design: (work@oh_fifo_async) |vpiContAssign: \_cont_assign: , line:35:11, endln:35:39 |vpiParent: - \_module: work@oh_fifo_cdc (work@oh_fifo_cdc), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_cdc.v, line:8:1, endln:86:10 + \_module_inst: work@oh_fifo_cdc (work@oh_fifo_cdc), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_cdc.v, line:8:1, endln:86:10 |vpiRhs: \_operation: , line:35:22, endln:35:39 |vpiParent: @@ -24720,7 +24720,7 @@ design: (work@oh_fifo_async) |vpiContAssign: \_cont_assign: , line:36:11, endln:36:65 |vpiParent: - \_module: work@oh_fifo_cdc (work@oh_fifo_cdc), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_cdc.v, line:8:1, endln:86:10 + \_module_inst: work@oh_fifo_cdc (work@oh_fifo_cdc), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_cdc.v, line:8:1, endln:86:10 |vpiRhs: \_operation: , line:36:23, endln:36:65 |vpiParent: @@ -24761,14 +24761,14 @@ design: (work@oh_fifo_async) |vpiName:ready_out |vpiFullName:work@oh_fifo_cdc.ready_out |uhdmallModules: -\_module: work@oh_fifo_sync (work@oh_fifo_sync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_sync.v, line:8:1, endln:144:10 +\_module_inst: work@oh_fifo_sync (work@oh_fifo_sync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_sync.v, line:8:1, endln:144:10 |vpiParent: \_design: (work@oh_fifo_async) |vpiFullName:work@oh_fifo_sync |vpiParameter: \_parameter: (work@oh_fifo_sync.N), line:9:15, endln:9:16 |vpiParent: - \_module: work@oh_fifo_sync (work@oh_fifo_sync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_sync.v, line:8:1, endln:144:10 + \_module_inst: work@oh_fifo_sync (work@oh_fifo_sync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_sync.v, line:8:1, endln:144:10 |UINT:32 |vpiTypespec: \_int_typespec: @@ -24777,7 +24777,7 @@ design: (work@oh_fifo_async) |vpiParameter: \_parameter: (work@oh_fifo_sync.DEPTH), line:10:15, endln:10:20 |vpiParent: - \_module: work@oh_fifo_sync (work@oh_fifo_sync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_sync.v, line:8:1, endln:144:10 + \_module_inst: work@oh_fifo_sync (work@oh_fifo_sync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_sync.v, line:8:1, endln:144:10 |UINT:32 |vpiTypespec: \_int_typespec: @@ -24786,7 +24786,7 @@ design: (work@oh_fifo_async) |vpiParameter: \_parameter: (work@oh_fifo_sync.REG), line:11:15, endln:11:18 |vpiParent: - \_module: work@oh_fifo_sync (work@oh_fifo_sync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_sync.v, line:8:1, endln:144:10 + \_module_inst: work@oh_fifo_sync (work@oh_fifo_sync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_sync.v, line:8:1, endln:144:10 |UINT:1 |vpiTypespec: \_int_typespec: @@ -24795,7 +24795,7 @@ design: (work@oh_fifo_async) |vpiParameter: \_parameter: (work@oh_fifo_sync.SYNCPIPE), line:12:15, endln:12:23 |vpiParent: - \_module: work@oh_fifo_sync (work@oh_fifo_sync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_sync.v, line:8:1, endln:144:10 + \_module_inst: work@oh_fifo_sync (work@oh_fifo_sync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_sync.v, line:8:1, endln:144:10 |UINT:2 |vpiTypespec: \_int_typespec: @@ -24804,7 +24804,7 @@ design: (work@oh_fifo_async) |vpiParameter: \_parameter: (work@oh_fifo_sync.SYN), line:13:15, endln:13:18 |vpiParent: - \_module: work@oh_fifo_sync (work@oh_fifo_sync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_sync.v, line:8:1, endln:144:10 + \_module_inst: work@oh_fifo_sync (work@oh_fifo_sync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_sync.v, line:8:1, endln:144:10 |STRING:TRUE |vpiTypespec: \_string_typespec: @@ -24813,7 +24813,7 @@ design: (work@oh_fifo_async) |vpiParameter: \_parameter: (work@oh_fifo_sync.TYPE), line:14:15, endln:14:19 |vpiParent: - \_module: work@oh_fifo_sync (work@oh_fifo_sync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_sync.v, line:8:1, endln:144:10 + \_module_inst: work@oh_fifo_sync (work@oh_fifo_sync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_sync.v, line:8:1, endln:144:10 |STRING:DEFAULT |vpiTypespec: \_string_typespec: @@ -24822,7 +24822,7 @@ design: (work@oh_fifo_async) |vpiParameter: \_parameter: (work@oh_fifo_sync.SHAPE), line:15:15, endln:15:20 |vpiParent: - \_module: work@oh_fifo_sync (work@oh_fifo_sync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_sync.v, line:8:1, endln:144:10 + \_module_inst: work@oh_fifo_sync (work@oh_fifo_sync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_sync.v, line:8:1, endln:144:10 |STRING:SQUARE |vpiTypespec: \_string_typespec: @@ -24831,19 +24831,19 @@ design: (work@oh_fifo_async) |vpiParameter: \_parameter: (work@oh_fifo_sync.PROGFULL), line:16:15, endln:16:23 |vpiParent: - \_module: work@oh_fifo_sync (work@oh_fifo_sync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_sync.v, line:8:1, endln:144:10 + \_module_inst: work@oh_fifo_sync (work@oh_fifo_sync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_sync.v, line:8:1, endln:144:10 |vpiName:PROGFULL |vpiFullName:work@oh_fifo_sync.PROGFULL |vpiParameter: \_parameter: (work@oh_fifo_sync.AW), line:17:15, endln:17:17 |vpiParent: - \_module: work@oh_fifo_sync (work@oh_fifo_sync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_sync.v, line:8:1, endln:144:10 + \_module_inst: work@oh_fifo_sync (work@oh_fifo_sync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_sync.v, line:8:1, endln:144:10 |vpiName:AW |vpiFullName:work@oh_fifo_sync.AW |vpiParamAssign: \_param_assign: , line:9:15, endln:9:27 |vpiParent: - \_module: work@oh_fifo_sync (work@oh_fifo_sync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_sync.v, line:8:1, endln:144:10 + \_module_inst: work@oh_fifo_sync (work@oh_fifo_sync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_sync.v, line:8:1, endln:144:10 |vpiRhs: \_constant: , line:9:25, endln:9:27 |vpiDecompile:32 @@ -24857,7 +24857,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:10:15, endln:10:28 |vpiParent: - \_module: work@oh_fifo_sync (work@oh_fifo_sync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_sync.v, line:8:1, endln:144:10 + \_module_inst: work@oh_fifo_sync (work@oh_fifo_sync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_sync.v, line:8:1, endln:144:10 |vpiRhs: \_constant: , line:10:26, endln:10:28 |vpiDecompile:32 @@ -24871,7 +24871,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:11:15, endln:11:27 |vpiParent: - \_module: work@oh_fifo_sync (work@oh_fifo_sync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_sync.v, line:8:1, endln:144:10 + \_module_inst: work@oh_fifo_sync (work@oh_fifo_sync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_sync.v, line:8:1, endln:144:10 |vpiRhs: \_constant: , line:11:26, endln:11:27 |vpiDecompile:1 @@ -24885,7 +24885,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:12:15, endln:12:27 |vpiParent: - \_module: work@oh_fifo_sync (work@oh_fifo_sync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_sync.v, line:8:1, endln:144:10 + \_module_inst: work@oh_fifo_sync (work@oh_fifo_sync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_sync.v, line:8:1, endln:144:10 |vpiRhs: \_constant: , line:12:26, endln:12:27 |vpiDecompile:2 @@ -24899,7 +24899,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:13:15, endln:13:32 |vpiParent: - \_module: work@oh_fifo_sync (work@oh_fifo_sync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_sync.v, line:8:1, endln:144:10 + \_module_inst: work@oh_fifo_sync (work@oh_fifo_sync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_sync.v, line:8:1, endln:144:10 |vpiRhs: \_constant: , line:13:26, endln:13:32 |vpiDecompile:TRUE @@ -24913,7 +24913,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:14:15, endln:14:35 |vpiParent: - \_module: work@oh_fifo_sync (work@oh_fifo_sync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_sync.v, line:8:1, endln:144:10 + \_module_inst: work@oh_fifo_sync (work@oh_fifo_sync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_sync.v, line:8:1, endln:144:10 |vpiRhs: \_constant: , line:14:26, endln:14:35 |vpiDecompile:DEFAULT @@ -24927,7 +24927,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:15:15, endln:15:34 |vpiParent: - \_module: work@oh_fifo_sync (work@oh_fifo_sync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_sync.v, line:8:1, endln:144:10 + \_module_inst: work@oh_fifo_sync (work@oh_fifo_sync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_sync.v, line:8:1, endln:144:10 |vpiRhs: \_constant: , line:15:26, endln:15:34 |vpiDecompile:SQUARE @@ -24941,7 +24941,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:16:15, endln:16:33 |vpiParent: - \_module: work@oh_fifo_sync (work@oh_fifo_sync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_sync.v, line:8:1, endln:144:10 + \_module_inst: work@oh_fifo_sync (work@oh_fifo_sync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_sync.v, line:8:1, endln:144:10 |vpiRhs: \_operation: , line:16:26, endln:16:33 |vpiOpType:11 @@ -24963,7 +24963,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:17:15, endln:17:39 |vpiParent: - \_module: work@oh_fifo_sync (work@oh_fifo_sync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_sync.v, line:8:1, endln:144:10 + \_module_inst: work@oh_fifo_sync (work@oh_fifo_sync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_sync.v, line:8:1, endln:144:10 |vpiRhs: \_sys_func_call: ($clog2), line:17:26, endln:17:39 |vpiArgument: @@ -24979,213 +24979,213 @@ design: (work@oh_fifo_async) |vpiNet: \_logic_net: (work@oh_fifo_sync.clk), line:21:13, endln:21:16 |vpiParent: - \_module: work@oh_fifo_sync (work@oh_fifo_sync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_sync.v, line:8:1, endln:144:10 + \_module_inst: work@oh_fifo_sync (work@oh_fifo_sync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_sync.v, line:8:1, endln:144:10 |vpiName:clk |vpiFullName:work@oh_fifo_sync.clk |vpiNet: \_logic_net: (work@oh_fifo_sync.nreset), line:22:13, endln:22:19 |vpiParent: - \_module: work@oh_fifo_sync (work@oh_fifo_sync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_sync.v, line:8:1, endln:144:10 + \_module_inst: work@oh_fifo_sync (work@oh_fifo_sync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_sync.v, line:8:1, endln:144:10 |vpiName:nreset |vpiFullName:work@oh_fifo_sync.nreset |vpiNet: \_logic_net: (work@oh_fifo_sync.clear), line:23:13, endln:23:18 |vpiParent: - \_module: work@oh_fifo_sync (work@oh_fifo_sync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_sync.v, line:8:1, endln:144:10 + \_module_inst: work@oh_fifo_sync (work@oh_fifo_sync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_sync.v, line:8:1, endln:144:10 |vpiName:clear |vpiFullName:work@oh_fifo_sync.clear |vpiNet: \_logic_net: (work@oh_fifo_sync.wr_clk), line:25:13, endln:25:19 |vpiParent: - \_module: work@oh_fifo_sync (work@oh_fifo_sync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_sync.v, line:8:1, endln:144:10 + \_module_inst: work@oh_fifo_sync (work@oh_fifo_sync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_sync.v, line:8:1, endln:144:10 |vpiName:wr_clk |vpiFullName:work@oh_fifo_sync.wr_clk |vpiNet: \_logic_net: (work@oh_fifo_sync.wr_din), line:26:20, endln:26:26 |vpiParent: - \_module: work@oh_fifo_sync (work@oh_fifo_sync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_sync.v, line:8:1, endln:144:10 + \_module_inst: work@oh_fifo_sync (work@oh_fifo_sync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_sync.v, line:8:1, endln:144:10 |vpiName:wr_din |vpiFullName:work@oh_fifo_sync.wr_din |vpiNet: \_logic_net: (work@oh_fifo_sync.wr_en), line:27:13, endln:27:18 |vpiParent: - \_module: work@oh_fifo_sync (work@oh_fifo_sync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_sync.v, line:8:1, endln:144:10 + \_module_inst: work@oh_fifo_sync (work@oh_fifo_sync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_sync.v, line:8:1, endln:144:10 |vpiName:wr_en |vpiFullName:work@oh_fifo_sync.wr_en |vpiNet: \_logic_net: (work@oh_fifo_sync.wr_full), line:28:14, endln:28:21 |vpiParent: - \_module: work@oh_fifo_sync (work@oh_fifo_sync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_sync.v, line:8:1, endln:144:10 + \_module_inst: work@oh_fifo_sync (work@oh_fifo_sync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_sync.v, line:8:1, endln:144:10 |vpiName:wr_full |vpiFullName:work@oh_fifo_sync.wr_full |vpiNet: \_logic_net: (work@oh_fifo_sync.wr_almost_full), line:29:14, endln:29:28 |vpiParent: - \_module: work@oh_fifo_sync (work@oh_fifo_sync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_sync.v, line:8:1, endln:144:10 + \_module_inst: work@oh_fifo_sync (work@oh_fifo_sync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_sync.v, line:8:1, endln:144:10 |vpiName:wr_almost_full |vpiFullName:work@oh_fifo_sync.wr_almost_full |vpiNet: \_logic_net: (work@oh_fifo_sync.wr_prog_full), line:30:14, endln:30:26 |vpiParent: - \_module: work@oh_fifo_sync (work@oh_fifo_sync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_sync.v, line:8:1, endln:144:10 + \_module_inst: work@oh_fifo_sync (work@oh_fifo_sync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_sync.v, line:8:1, endln:144:10 |vpiName:wr_prog_full |vpiFullName:work@oh_fifo_sync.wr_prog_full |vpiNet: \_logic_net: (work@oh_fifo_sync.wr_count), line:31:25, endln:31:33 |vpiParent: - \_module: work@oh_fifo_sync (work@oh_fifo_sync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_sync.v, line:8:1, endln:144:10 + \_module_inst: work@oh_fifo_sync (work@oh_fifo_sync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_sync.v, line:8:1, endln:144:10 |vpiName:wr_count |vpiFullName:work@oh_fifo_sync.wr_count |vpiNetType:48 |vpiNet: \_logic_net: (work@oh_fifo_sync.rd_clk), line:33:13, endln:33:19 |vpiParent: - \_module: work@oh_fifo_sync (work@oh_fifo_sync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_sync.v, line:8:1, endln:144:10 + \_module_inst: work@oh_fifo_sync (work@oh_fifo_sync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_sync.v, line:8:1, endln:144:10 |vpiName:rd_clk |vpiFullName:work@oh_fifo_sync.rd_clk |vpiNet: \_logic_net: (work@oh_fifo_sync.rd_dout), line:34:21, endln:34:28 |vpiParent: - \_module: work@oh_fifo_sync (work@oh_fifo_sync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_sync.v, line:8:1, endln:144:10 + \_module_inst: work@oh_fifo_sync (work@oh_fifo_sync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_sync.v, line:8:1, endln:144:10 |vpiName:rd_dout |vpiFullName:work@oh_fifo_sync.rd_dout |vpiNet: \_logic_net: (work@oh_fifo_sync.rd_en), line:35:13, endln:35:18 |vpiParent: - \_module: work@oh_fifo_sync (work@oh_fifo_sync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_sync.v, line:8:1, endln:144:10 + \_module_inst: work@oh_fifo_sync (work@oh_fifo_sync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_sync.v, line:8:1, endln:144:10 |vpiName:rd_en |vpiFullName:work@oh_fifo_sync.rd_en |vpiNet: \_logic_net: (work@oh_fifo_sync.rd_empty), line:36:14, endln:36:22 |vpiParent: - \_module: work@oh_fifo_sync (work@oh_fifo_sync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_sync.v, line:8:1, endln:144:10 + \_module_inst: work@oh_fifo_sync (work@oh_fifo_sync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_sync.v, line:8:1, endln:144:10 |vpiName:rd_empty |vpiFullName:work@oh_fifo_sync.rd_empty |vpiNet: \_logic_net: (work@oh_fifo_sync.bist_en), line:38:13, endln:38:20 |vpiParent: - \_module: work@oh_fifo_sync (work@oh_fifo_sync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_sync.v, line:8:1, endln:144:10 + \_module_inst: work@oh_fifo_sync (work@oh_fifo_sync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_sync.v, line:8:1, endln:144:10 |vpiName:bist_en |vpiFullName:work@oh_fifo_sync.bist_en |vpiNet: \_logic_net: (work@oh_fifo_sync.bist_we), line:39:13, endln:39:20 |vpiParent: - \_module: work@oh_fifo_sync (work@oh_fifo_sync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_sync.v, line:8:1, endln:144:10 + \_module_inst: work@oh_fifo_sync (work@oh_fifo_sync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_sync.v, line:8:1, endln:144:10 |vpiName:bist_we |vpiFullName:work@oh_fifo_sync.bist_we |vpiNet: \_logic_net: (work@oh_fifo_sync.bist_wem), line:40:20, endln:40:28 |vpiParent: - \_module: work@oh_fifo_sync (work@oh_fifo_sync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_sync.v, line:8:1, endln:144:10 + \_module_inst: work@oh_fifo_sync (work@oh_fifo_sync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_sync.v, line:8:1, endln:144:10 |vpiName:bist_wem |vpiFullName:work@oh_fifo_sync.bist_wem |vpiNet: \_logic_net: (work@oh_fifo_sync.bist_addr), line:41:21, endln:41:30 |vpiParent: - \_module: work@oh_fifo_sync (work@oh_fifo_sync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_sync.v, line:8:1, endln:144:10 + \_module_inst: work@oh_fifo_sync (work@oh_fifo_sync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_sync.v, line:8:1, endln:144:10 |vpiName:bist_addr |vpiFullName:work@oh_fifo_sync.bist_addr |vpiNet: \_logic_net: (work@oh_fifo_sync.bist_din), line:42:20, endln:42:28 |vpiParent: - \_module: work@oh_fifo_sync (work@oh_fifo_sync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_sync.v, line:8:1, endln:144:10 + \_module_inst: work@oh_fifo_sync (work@oh_fifo_sync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_sync.v, line:8:1, endln:144:10 |vpiName:bist_din |vpiFullName:work@oh_fifo_sync.bist_din |vpiNet: \_logic_net: (work@oh_fifo_sync.bist_dout), line:43:20, endln:43:29 |vpiParent: - \_module: work@oh_fifo_sync (work@oh_fifo_sync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_sync.v, line:8:1, endln:144:10 + \_module_inst: work@oh_fifo_sync (work@oh_fifo_sync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_sync.v, line:8:1, endln:144:10 |vpiName:bist_dout |vpiFullName:work@oh_fifo_sync.bist_dout |vpiNet: \_logic_net: (work@oh_fifo_sync.shutdown), line:45:13, endln:45:21 |vpiParent: - \_module: work@oh_fifo_sync (work@oh_fifo_sync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_sync.v, line:8:1, endln:144:10 + \_module_inst: work@oh_fifo_sync (work@oh_fifo_sync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_sync.v, line:8:1, endln:144:10 |vpiName:shutdown |vpiFullName:work@oh_fifo_sync.shutdown |vpiNet: \_logic_net: (work@oh_fifo_sync.vss), line:46:13, endln:46:16 |vpiParent: - \_module: work@oh_fifo_sync (work@oh_fifo_sync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_sync.v, line:8:1, endln:144:10 + \_module_inst: work@oh_fifo_sync (work@oh_fifo_sync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_sync.v, line:8:1, endln:144:10 |vpiName:vss |vpiFullName:work@oh_fifo_sync.vss |vpiNet: \_logic_net: (work@oh_fifo_sync.vdd), line:47:13, endln:47:16 |vpiParent: - \_module: work@oh_fifo_sync (work@oh_fifo_sync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_sync.v, line:8:1, endln:144:10 + \_module_inst: work@oh_fifo_sync (work@oh_fifo_sync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_sync.v, line:8:1, endln:144:10 |vpiName:vdd |vpiFullName:work@oh_fifo_sync.vdd |vpiNet: \_logic_net: (work@oh_fifo_sync.vddio), line:48:13, endln:48:18 |vpiParent: - \_module: work@oh_fifo_sync (work@oh_fifo_sync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_sync.v, line:8:1, endln:144:10 + \_module_inst: work@oh_fifo_sync (work@oh_fifo_sync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_sync.v, line:8:1, endln:144:10 |vpiName:vddio |vpiFullName:work@oh_fifo_sync.vddio |vpiNet: \_logic_net: (work@oh_fifo_sync.memconfig), line:49:18, endln:49:27 |vpiParent: - \_module: work@oh_fifo_sync (work@oh_fifo_sync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_sync.v, line:8:1, endln:144:10 + \_module_inst: work@oh_fifo_sync (work@oh_fifo_sync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_sync.v, line:8:1, endln:144:10 |vpiName:memconfig |vpiFullName:work@oh_fifo_sync.memconfig |vpiNet: \_logic_net: (work@oh_fifo_sync.memrepair), line:50:18, endln:50:27 |vpiParent: - \_module: work@oh_fifo_sync (work@oh_fifo_sync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_sync.v, line:8:1, endln:144:10 + \_module_inst: work@oh_fifo_sync (work@oh_fifo_sync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_sync.v, line:8:1, endln:144:10 |vpiName:memrepair |vpiFullName:work@oh_fifo_sync.memrepair |vpiNet: \_logic_net: (work@oh_fifo_sync.wr_addr), line:56:24, endln:56:31 |vpiParent: - \_module: work@oh_fifo_sync (work@oh_fifo_sync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_sync.v, line:8:1, endln:144:10 + \_module_inst: work@oh_fifo_sync (work@oh_fifo_sync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_sync.v, line:8:1, endln:144:10 |vpiName:wr_addr |vpiFullName:work@oh_fifo_sync.wr_addr |vpiNetType:48 |vpiNet: \_logic_net: (work@oh_fifo_sync.rd_addr), line:57:24, endln:57:31 |vpiParent: - \_module: work@oh_fifo_sync (work@oh_fifo_sync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_sync.v, line:8:1, endln:144:10 + \_module_inst: work@oh_fifo_sync (work@oh_fifo_sync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_sync.v, line:8:1, endln:144:10 |vpiName:rd_addr |vpiFullName:work@oh_fifo_sync.rd_addr |vpiNetType:48 |vpiNet: \_logic_net: (work@oh_fifo_sync.empty_reg), line:58:17, endln:58:26 |vpiParent: - \_module: work@oh_fifo_sync (work@oh_fifo_sync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_sync.v, line:8:1, endln:144:10 + \_module_inst: work@oh_fifo_sync (work@oh_fifo_sync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_sync.v, line:8:1, endln:144:10 |vpiName:empty_reg |vpiFullName:work@oh_fifo_sync.empty_reg |vpiNetType:48 |vpiNet: \_logic_net: (work@oh_fifo_sync.fifo_read), line:59:17, endln:59:26 |vpiParent: - \_module: work@oh_fifo_sync (work@oh_fifo_sync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_sync.v, line:8:1, endln:144:10 + \_module_inst: work@oh_fifo_sync (work@oh_fifo_sync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_sync.v, line:8:1, endln:144:10 |vpiName:fifo_read |vpiFullName:work@oh_fifo_sync.fifo_read |vpiNetType:1 |vpiNet: \_logic_net: (work@oh_fifo_sync.fifo_write), line:60:17, endln:60:27 |vpiParent: - \_module: work@oh_fifo_sync (work@oh_fifo_sync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_sync.v, line:8:1, endln:144:10 + \_module_inst: work@oh_fifo_sync (work@oh_fifo_sync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_sync.v, line:8:1, endln:144:10 |vpiName:fifo_write |vpiFullName:work@oh_fifo_sync.fifo_write |vpiNetType:1 |vpiNet: \_logic_net: (work@oh_fifo_sync.ptr_match), line:61:17, endln:61:26 |vpiParent: - \_module: work@oh_fifo_sync (work@oh_fifo_sync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_sync.v, line:8:1, endln:144:10 + \_module_inst: work@oh_fifo_sync (work@oh_fifo_sync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_sync.v, line:8:1, endln:144:10 |vpiName:ptr_match |vpiFullName:work@oh_fifo_sync.ptr_match |vpiNetType:1 |vpiNet: \_logic_net: (work@oh_fifo_sync.fifo_empty), line:62:17, endln:62:27 |vpiParent: - \_module: work@oh_fifo_sync (work@oh_fifo_sync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_sync.v, line:8:1, endln:144:10 + \_module_inst: work@oh_fifo_sync (work@oh_fifo_sync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_sync.v, line:8:1, endln:144:10 |vpiName:fifo_empty |vpiFullName:work@oh_fifo_sync.fifo_empty |vpiNetType:1 |vpiPort: \_port: (clk), line:21:13, endln:21:16 |vpiParent: - \_module: work@oh_fifo_sync (work@oh_fifo_sync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_sync.v, line:8:1, endln:144:10 + \_module_inst: work@oh_fifo_sync (work@oh_fifo_sync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_sync.v, line:8:1, endln:144:10 |vpiName:clk |vpiDirection:1 |vpiLowConn: @@ -25197,7 +25197,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (nreset), line:22:13, endln:22:19 |vpiParent: - \_module: work@oh_fifo_sync (work@oh_fifo_sync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_sync.v, line:8:1, endln:144:10 + \_module_inst: work@oh_fifo_sync (work@oh_fifo_sync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_sync.v, line:8:1, endln:144:10 |vpiName:nreset |vpiDirection:1 |vpiLowConn: @@ -25209,7 +25209,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (clear), line:23:13, endln:23:18 |vpiParent: - \_module: work@oh_fifo_sync (work@oh_fifo_sync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_sync.v, line:8:1, endln:144:10 + \_module_inst: work@oh_fifo_sync (work@oh_fifo_sync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_sync.v, line:8:1, endln:144:10 |vpiName:clear |vpiDirection:1 |vpiLowConn: @@ -25221,7 +25221,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (wr_clk), line:25:13, endln:25:19 |vpiParent: - \_module: work@oh_fifo_sync (work@oh_fifo_sync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_sync.v, line:8:1, endln:144:10 + \_module_inst: work@oh_fifo_sync (work@oh_fifo_sync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_sync.v, line:8:1, endln:144:10 |vpiName:wr_clk |vpiDirection:1 |vpiLowConn: @@ -25233,7 +25233,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (wr_din), line:26:20, endln:26:26 |vpiParent: - \_module: work@oh_fifo_sync (work@oh_fifo_sync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_sync.v, line:8:1, endln:144:10 + \_module_inst: work@oh_fifo_sync (work@oh_fifo_sync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_sync.v, line:8:1, endln:144:10 |vpiName:wr_din |vpiDirection:1 |vpiLowConn: @@ -25273,7 +25273,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (wr_en), line:27:13, endln:27:18 |vpiParent: - \_module: work@oh_fifo_sync (work@oh_fifo_sync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_sync.v, line:8:1, endln:144:10 + \_module_inst: work@oh_fifo_sync (work@oh_fifo_sync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_sync.v, line:8:1, endln:144:10 |vpiName:wr_en |vpiDirection:1 |vpiLowConn: @@ -25285,7 +25285,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (wr_full), line:28:14, endln:28:21 |vpiParent: - \_module: work@oh_fifo_sync (work@oh_fifo_sync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_sync.v, line:8:1, endln:144:10 + \_module_inst: work@oh_fifo_sync (work@oh_fifo_sync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_sync.v, line:8:1, endln:144:10 |vpiName:wr_full |vpiDirection:2 |vpiLowConn: @@ -25297,7 +25297,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (wr_almost_full), line:29:14, endln:29:28 |vpiParent: - \_module: work@oh_fifo_sync (work@oh_fifo_sync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_sync.v, line:8:1, endln:144:10 + \_module_inst: work@oh_fifo_sync (work@oh_fifo_sync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_sync.v, line:8:1, endln:144:10 |vpiName:wr_almost_full |vpiDirection:2 |vpiLowConn: @@ -25309,7 +25309,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (wr_prog_full), line:30:14, endln:30:26 |vpiParent: - \_module: work@oh_fifo_sync (work@oh_fifo_sync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_sync.v, line:8:1, endln:144:10 + \_module_inst: work@oh_fifo_sync (work@oh_fifo_sync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_sync.v, line:8:1, endln:144:10 |vpiName:wr_prog_full |vpiDirection:2 |vpiLowConn: @@ -25321,7 +25321,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (wr_count), line:31:25, endln:31:33 |vpiParent: - \_module: work@oh_fifo_sync (work@oh_fifo_sync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_sync.v, line:8:1, endln:144:10 + \_module_inst: work@oh_fifo_sync (work@oh_fifo_sync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_sync.v, line:8:1, endln:144:10 |vpiName:wr_count |vpiDirection:2 |vpiLowConn: @@ -25361,7 +25361,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (rd_clk), line:33:13, endln:33:19 |vpiParent: - \_module: work@oh_fifo_sync (work@oh_fifo_sync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_sync.v, line:8:1, endln:144:10 + \_module_inst: work@oh_fifo_sync (work@oh_fifo_sync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_sync.v, line:8:1, endln:144:10 |vpiName:rd_clk |vpiDirection:1 |vpiLowConn: @@ -25373,7 +25373,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (rd_dout), line:34:21, endln:34:28 |vpiParent: - \_module: work@oh_fifo_sync (work@oh_fifo_sync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_sync.v, line:8:1, endln:144:10 + \_module_inst: work@oh_fifo_sync (work@oh_fifo_sync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_sync.v, line:8:1, endln:144:10 |vpiName:rd_dout |vpiDirection:2 |vpiLowConn: @@ -25413,7 +25413,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (rd_en), line:35:13, endln:35:18 |vpiParent: - \_module: work@oh_fifo_sync (work@oh_fifo_sync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_sync.v, line:8:1, endln:144:10 + \_module_inst: work@oh_fifo_sync (work@oh_fifo_sync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_sync.v, line:8:1, endln:144:10 |vpiName:rd_en |vpiDirection:1 |vpiLowConn: @@ -25425,7 +25425,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (rd_empty), line:36:14, endln:36:22 |vpiParent: - \_module: work@oh_fifo_sync (work@oh_fifo_sync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_sync.v, line:8:1, endln:144:10 + \_module_inst: work@oh_fifo_sync (work@oh_fifo_sync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_sync.v, line:8:1, endln:144:10 |vpiName:rd_empty |vpiDirection:2 |vpiLowConn: @@ -25437,7 +25437,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (bist_en), line:38:13, endln:38:20 |vpiParent: - \_module: work@oh_fifo_sync (work@oh_fifo_sync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_sync.v, line:8:1, endln:144:10 + \_module_inst: work@oh_fifo_sync (work@oh_fifo_sync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_sync.v, line:8:1, endln:144:10 |vpiName:bist_en |vpiDirection:1 |vpiLowConn: @@ -25449,7 +25449,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (bist_we), line:39:13, endln:39:20 |vpiParent: - \_module: work@oh_fifo_sync (work@oh_fifo_sync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_sync.v, line:8:1, endln:144:10 + \_module_inst: work@oh_fifo_sync (work@oh_fifo_sync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_sync.v, line:8:1, endln:144:10 |vpiName:bist_we |vpiDirection:1 |vpiLowConn: @@ -25461,7 +25461,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (bist_wem), line:40:20, endln:40:28 |vpiParent: - \_module: work@oh_fifo_sync (work@oh_fifo_sync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_sync.v, line:8:1, endln:144:10 + \_module_inst: work@oh_fifo_sync (work@oh_fifo_sync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_sync.v, line:8:1, endln:144:10 |vpiName:bist_wem |vpiDirection:1 |vpiLowConn: @@ -25501,7 +25501,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (bist_addr), line:41:21, endln:41:30 |vpiParent: - \_module: work@oh_fifo_sync (work@oh_fifo_sync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_sync.v, line:8:1, endln:144:10 + \_module_inst: work@oh_fifo_sync (work@oh_fifo_sync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_sync.v, line:8:1, endln:144:10 |vpiName:bist_addr |vpiDirection:1 |vpiLowConn: @@ -25541,7 +25541,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (bist_din), line:42:20, endln:42:28 |vpiParent: - \_module: work@oh_fifo_sync (work@oh_fifo_sync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_sync.v, line:8:1, endln:144:10 + \_module_inst: work@oh_fifo_sync (work@oh_fifo_sync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_sync.v, line:8:1, endln:144:10 |vpiName:bist_din |vpiDirection:1 |vpiLowConn: @@ -25581,7 +25581,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (bist_dout), line:43:20, endln:43:29 |vpiParent: - \_module: work@oh_fifo_sync (work@oh_fifo_sync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_sync.v, line:8:1, endln:144:10 + \_module_inst: work@oh_fifo_sync (work@oh_fifo_sync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_sync.v, line:8:1, endln:144:10 |vpiName:bist_dout |vpiDirection:1 |vpiLowConn: @@ -25621,7 +25621,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (shutdown), line:45:13, endln:45:21 |vpiParent: - \_module: work@oh_fifo_sync (work@oh_fifo_sync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_sync.v, line:8:1, endln:144:10 + \_module_inst: work@oh_fifo_sync (work@oh_fifo_sync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_sync.v, line:8:1, endln:144:10 |vpiName:shutdown |vpiDirection:1 |vpiLowConn: @@ -25633,7 +25633,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (vss), line:46:13, endln:46:16 |vpiParent: - \_module: work@oh_fifo_sync (work@oh_fifo_sync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_sync.v, line:8:1, endln:144:10 + \_module_inst: work@oh_fifo_sync (work@oh_fifo_sync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_sync.v, line:8:1, endln:144:10 |vpiName:vss |vpiDirection:1 |vpiLowConn: @@ -25645,7 +25645,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (vdd), line:47:13, endln:47:16 |vpiParent: - \_module: work@oh_fifo_sync (work@oh_fifo_sync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_sync.v, line:8:1, endln:144:10 + \_module_inst: work@oh_fifo_sync (work@oh_fifo_sync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_sync.v, line:8:1, endln:144:10 |vpiName:vdd |vpiDirection:1 |vpiLowConn: @@ -25657,7 +25657,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (vddio), line:48:13, endln:48:18 |vpiParent: - \_module: work@oh_fifo_sync (work@oh_fifo_sync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_sync.v, line:8:1, endln:144:10 + \_module_inst: work@oh_fifo_sync (work@oh_fifo_sync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_sync.v, line:8:1, endln:144:10 |vpiName:vddio |vpiDirection:1 |vpiLowConn: @@ -25669,7 +25669,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (memconfig), line:49:18, endln:49:27 |vpiParent: - \_module: work@oh_fifo_sync (work@oh_fifo_sync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_sync.v, line:8:1, endln:144:10 + \_module_inst: work@oh_fifo_sync (work@oh_fifo_sync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_sync.v, line:8:1, endln:144:10 |vpiName:memconfig |vpiDirection:1 |vpiLowConn: @@ -25699,7 +25699,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (memrepair), line:50:18, endln:50:27 |vpiParent: - \_module: work@oh_fifo_sync (work@oh_fifo_sync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_sync.v, line:8:1, endln:144:10 + \_module_inst: work@oh_fifo_sync (work@oh_fifo_sync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_sync.v, line:8:1, endln:144:10 |vpiName:memrepair |vpiDirection:1 |vpiLowConn: @@ -25729,7 +25729,7 @@ design: (work@oh_fifo_async) |vpiProcess: \_always: , line:75:4, endln:102:11 |vpiParent: - \_module: work@oh_fifo_sync (work@oh_fifo_sync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_sync.v, line:8:1, endln:144:10 + \_module_inst: work@oh_fifo_sync (work@oh_fifo_sync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_sync.v, line:8:1, endln:144:10 |vpiStmt: \_event_control: , line:75:11, endln:75:44 |vpiParent: @@ -26506,7 +26506,7 @@ design: (work@oh_fifo_async) |vpiProcess: \_always: , line:105:4, endln:106:30 |vpiParent: - \_module: work@oh_fifo_sync (work@oh_fifo_sync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_sync.v, line:8:1, endln:144:10 + \_module_inst: work@oh_fifo_sync (work@oh_fifo_sync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_sync.v, line:8:1, endln:144:10 |vpiStmt: \_event_control: , line:105:11, endln:105:26 |vpiParent: @@ -26543,7 +26543,7 @@ design: (work@oh_fifo_async) |vpiContAssign: \_cont_assign: , line:68:11, endln:68:42 |vpiParent: - \_module: work@oh_fifo_sync (work@oh_fifo_sync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_sync.v, line:8:1, endln:144:10 + \_module_inst: work@oh_fifo_sync (work@oh_fifo_sync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_sync.v, line:8:1, endln:144:10 |vpiRhs: \_operation: , line:68:25, endln:68:42 |vpiParent: @@ -26575,7 +26575,7 @@ design: (work@oh_fifo_async) |vpiContAssign: \_cont_assign: , line:69:11, endln:69:41 |vpiParent: - \_module: work@oh_fifo_sync (work@oh_fifo_sync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_sync.v, line:8:1, endln:144:10 + \_module_inst: work@oh_fifo_sync (work@oh_fifo_sync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_sync.v, line:8:1, endln:144:10 |vpiRhs: \_operation: , line:69:25, endln:69:41 |vpiParent: @@ -26607,7 +26607,7 @@ design: (work@oh_fifo_async) |vpiContAssign: \_cont_assign: , line:70:11, endln:70:55 |vpiParent: - \_module: work@oh_fifo_sync (work@oh_fifo_sync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_sync.v, line:8:1, endln:144:10 + \_module_inst: work@oh_fifo_sync (work@oh_fifo_sync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_sync.v, line:8:1, endln:144:10 |vpiRhs: \_operation: , line:70:26, endln:70:54 |vpiParent: @@ -26660,7 +26660,7 @@ design: (work@oh_fifo_async) |vpiContAssign: \_cont_assign: , line:71:11, endln:71:61 |vpiParent: - \_module: work@oh_fifo_sync (work@oh_fifo_sync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_sync.v, line:8:1, endln:144:10 + \_module_inst: work@oh_fifo_sync (work@oh_fifo_sync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_sync.v, line:8:1, endln:144:10 |vpiRhs: \_operation: , line:71:26, endln:71:60 |vpiParent: @@ -26742,7 +26742,7 @@ design: (work@oh_fifo_async) |vpiContAssign: \_cont_assign: , line:72:11, endln:72:64 |vpiParent: - \_module: work@oh_fifo_sync (work@oh_fifo_sync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_sync.v, line:8:1, endln:144:10 + \_module_inst: work@oh_fifo_sync (work@oh_fifo_sync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_sync.v, line:8:1, endln:144:10 |vpiRhs: \_operation: , line:72:25, endln:72:64 |vpiParent: @@ -26805,7 +26805,7 @@ design: (work@oh_fifo_async) |vpiContAssign: \_cont_assign: , line:73:11, endln:73:63 |vpiParent: - \_module: work@oh_fifo_sync (work@oh_fifo_sync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_sync.v, line:8:1, endln:144:10 + \_module_inst: work@oh_fifo_sync (work@oh_fifo_sync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_sync.v, line:8:1, endln:144:10 |vpiRhs: \_operation: , line:73:25, endln:73:63 |vpiParent: @@ -26863,7 +26863,7 @@ design: (work@oh_fifo_async) |vpiContAssign: \_cont_assign: , line:108:11, endln:108:52 |vpiParent: - \_module: work@oh_fifo_sync (work@oh_fifo_sync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_sync.v, line:8:1, endln:144:10 + \_module_inst: work@oh_fifo_sync (work@oh_fifo_sync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_sync.v, line:8:1, endln:144:10 |vpiRhs: \_operation: , line:108:19, endln:108:52 |vpiParent: @@ -26907,14 +26907,14 @@ design: (work@oh_fifo_async) |vpiName:empty |vpiFullName:work@oh_fifo_sync.empty |uhdmallModules: -\_module: work@oh_gray2bin (work@oh_gray2bin), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_gray2bin.v, line:8:1, endln:33:10 +\_module_inst: work@oh_gray2bin (work@oh_gray2bin), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_gray2bin.v, line:8:1, endln:33:10 |vpiParent: \_design: (work@oh_fifo_async) |vpiFullName:work@oh_gray2bin |vpiParameter: \_parameter: (work@oh_gray2bin.N), line:8:32, endln:8:33 |vpiParent: - \_module: work@oh_gray2bin (work@oh_gray2bin), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_gray2bin.v, line:8:1, endln:33:10 + \_module_inst: work@oh_gray2bin (work@oh_gray2bin), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_gray2bin.v, line:8:1, endln:33:10 |UINT:32 |vpiTypespec: \_int_typespec: @@ -26923,7 +26923,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:8:32, endln:8:38 |vpiParent: - \_module: work@oh_gray2bin (work@oh_gray2bin), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_gray2bin.v, line:8:1, endln:33:10 + \_module_inst: work@oh_gray2bin (work@oh_gray2bin), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_gray2bin.v, line:8:1, endln:33:10 |vpiRhs: \_constant: , line:8:36, endln:8:38 |vpiDecompile:32 @@ -26939,45 +26939,45 @@ design: (work@oh_fifo_async) |vpiNet: \_logic_net: (work@oh_gray2bin.in), line:10:20, endln:10:22 |vpiParent: - \_module: work@oh_gray2bin (work@oh_gray2bin), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_gray2bin.v, line:8:1, endln:33:10 + \_module_inst: work@oh_gray2bin (work@oh_gray2bin), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_gray2bin.v, line:8:1, endln:33:10 |vpiName:in |vpiFullName:work@oh_gray2bin.in |vpiNet: \_logic_net: (work@oh_gray2bin.out), line:11:20, endln:11:23 |vpiParent: - \_module: work@oh_gray2bin (work@oh_gray2bin), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_gray2bin.v, line:8:1, endln:33:10 + \_module_inst: work@oh_gray2bin (work@oh_gray2bin), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_gray2bin.v, line:8:1, endln:33:10 |vpiName:out |vpiFullName:work@oh_gray2bin.out |vpiNet: \_logic_net: (work@oh_gray2bin.bin), line:14:20, endln:14:23 |vpiParent: - \_module: work@oh_gray2bin (work@oh_gray2bin), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_gray2bin.v, line:8:1, endln:33:10 + \_module_inst: work@oh_gray2bin (work@oh_gray2bin), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_gray2bin.v, line:8:1, endln:33:10 |vpiName:bin |vpiFullName:work@oh_gray2bin.bin |vpiNetType:48 |vpiNet: \_logic_net: (work@oh_gray2bin.gray), line:15:20, endln:15:24 |vpiParent: - \_module: work@oh_gray2bin (work@oh_gray2bin), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_gray2bin.v, line:8:1, endln:33:10 + \_module_inst: work@oh_gray2bin (work@oh_gray2bin), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_gray2bin.v, line:8:1, endln:33:10 |vpiName:gray |vpiFullName:work@oh_gray2bin.gray |vpiNetType:1 |vpiNet: \_logic_net: (work@oh_gray2bin.i), line:17:16, endln:17:17 |vpiParent: - \_module: work@oh_gray2bin (work@oh_gray2bin), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_gray2bin.v, line:8:1, endln:33:10 + \_module_inst: work@oh_gray2bin (work@oh_gray2bin), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_gray2bin.v, line:8:1, endln:33:10 |vpiName:i |vpiFullName:work@oh_gray2bin.i |vpiNet: \_logic_net: (work@oh_gray2bin.j), line:17:18, endln:17:19 |vpiParent: - \_module: work@oh_gray2bin (work@oh_gray2bin), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_gray2bin.v, line:8:1, endln:33:10 + \_module_inst: work@oh_gray2bin (work@oh_gray2bin), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_gray2bin.v, line:8:1, endln:33:10 |vpiName:j |vpiFullName:work@oh_gray2bin.j |vpiPort: \_port: (in), line:10:20, endln:10:22 |vpiParent: - \_module: work@oh_gray2bin (work@oh_gray2bin), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_gray2bin.v, line:8:1, endln:33:10 + \_module_inst: work@oh_gray2bin (work@oh_gray2bin), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_gray2bin.v, line:8:1, endln:33:10 |vpiName:in |vpiDirection:1 |vpiLowConn: @@ -27017,7 +27017,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (out), line:11:20, endln:11:23 |vpiParent: - \_module: work@oh_gray2bin (work@oh_gray2bin), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_gray2bin.v, line:8:1, endln:33:10 + \_module_inst: work@oh_gray2bin (work@oh_gray2bin), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_gray2bin.v, line:8:1, endln:33:10 |vpiName:out |vpiDirection:2 |vpiLowConn: @@ -27057,7 +27057,7 @@ design: (work@oh_fifo_async) |vpiProcess: \_always: , line:22:4, endln:31:9 |vpiParent: - \_module: work@oh_gray2bin (work@oh_gray2bin), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_gray2bin.v, line:8:1, endln:33:10 + \_module_inst: work@oh_gray2bin (work@oh_gray2bin), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_gray2bin.v, line:8:1, endln:33:10 |vpiStmt: \_event_control: , line:22:11, endln:22:13 |vpiParent: @@ -27382,7 +27382,7 @@ design: (work@oh_fifo_async) |vpiContAssign: \_cont_assign: , line:19:11, endln:19:34 |vpiParent: - \_module: work@oh_gray2bin (work@oh_gray2bin), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_gray2bin.v, line:8:1, endln:33:10 + \_module_inst: work@oh_gray2bin (work@oh_gray2bin), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_gray2bin.v, line:8:1, endln:33:10 |vpiRhs: \_part_select: , line:19:25, endln:19:34 |vpiParent: @@ -27450,7 +27450,7 @@ design: (work@oh_fifo_async) |vpiContAssign: \_cont_assign: , line:20:11, endln:20:35 |vpiParent: - \_module: work@oh_gray2bin (work@oh_gray2bin), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_gray2bin.v, line:8:1, endln:33:10 + \_module_inst: work@oh_gray2bin (work@oh_gray2bin), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_gray2bin.v, line:8:1, endln:33:10 |vpiRhs: \_part_select: , line:20:25, endln:20:35 |vpiParent: @@ -27516,14 +27516,14 @@ design: (work@oh_fifo_async) |UINT:0 |vpiConstType:9 |uhdmallModules: -\_module: work@oh_header (work@oh_header), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_header.v, line:8:1, endln:29:10 +\_module_inst: work@oh_header (work@oh_header), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_header.v, line:8:1, endln:29:10 |vpiParent: \_design: (work@oh_fifo_async) |vpiFullName:work@oh_header |vpiParameter: \_parameter: (work@oh_header.SYN), line:9:15, endln:9:18 |vpiParent: - \_module: work@oh_header (work@oh_header), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_header.v, line:8:1, endln:29:10 + \_module_inst: work@oh_header (work@oh_header), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_header.v, line:8:1, endln:29:10 |STRING:TRUE |vpiTypespec: \_string_typespec: @@ -27532,7 +27532,7 @@ design: (work@oh_fifo_async) |vpiParameter: \_parameter: (work@oh_header.TYPE), line:10:15, endln:10:19 |vpiParent: - \_module: work@oh_header (work@oh_header), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_header.v, line:8:1, endln:29:10 + \_module_inst: work@oh_header (work@oh_header), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_header.v, line:8:1, endln:29:10 |STRING:DEFAULT |vpiTypespec: \_string_typespec: @@ -27541,7 +27541,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:9:15, endln:9:29 |vpiParent: - \_module: work@oh_header (work@oh_header), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_header.v, line:8:1, endln:29:10 + \_module_inst: work@oh_header (work@oh_header), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_header.v, line:8:1, endln:29:10 |vpiRhs: \_constant: , line:9:23, endln:9:29 |vpiDecompile:TRUE @@ -27555,7 +27555,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:10:15, endln:10:32 |vpiParent: - \_module: work@oh_header (work@oh_header), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_header.v, line:8:1, endln:29:10 + \_module_inst: work@oh_header (work@oh_header), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_header.v, line:8:1, endln:29:10 |vpiRhs: \_constant: , line:10:23, endln:10:32 |vpiDecompile:DEFAULT @@ -27571,25 +27571,25 @@ design: (work@oh_fifo_async) |vpiNet: \_logic_net: (work@oh_header.npower), line:13:12, endln:13:18 |vpiParent: - \_module: work@oh_header (work@oh_header), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_header.v, line:8:1, endln:29:10 + \_module_inst: work@oh_header (work@oh_header), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_header.v, line:8:1, endln:29:10 |vpiName:npower |vpiFullName:work@oh_header.npower |vpiNet: \_logic_net: (work@oh_header.vdd), line:14:12, endln:14:15 |vpiParent: - \_module: work@oh_header (work@oh_header), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_header.v, line:8:1, endln:29:10 + \_module_inst: work@oh_header (work@oh_header), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_header.v, line:8:1, endln:29:10 |vpiName:vdd |vpiFullName:work@oh_header.vdd |vpiNet: \_logic_net: (work@oh_header.vddg), line:15:12, endln:15:16 |vpiParent: - \_module: work@oh_header (work@oh_header), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_header.v, line:8:1, endln:29:10 + \_module_inst: work@oh_header (work@oh_header), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_header.v, line:8:1, endln:29:10 |vpiName:vddg |vpiFullName:work@oh_header.vddg |vpiPort: \_port: (npower), line:13:12, endln:13:18 |vpiParent: - \_module: work@oh_header (work@oh_header), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_header.v, line:8:1, endln:29:10 + \_module_inst: work@oh_header (work@oh_header), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_header.v, line:8:1, endln:29:10 |vpiName:npower |vpiDirection:1 |vpiLowConn: @@ -27601,7 +27601,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (vdd), line:14:12, endln:14:15 |vpiParent: - \_module: work@oh_header (work@oh_header), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_header.v, line:8:1, endln:29:10 + \_module_inst: work@oh_header (work@oh_header), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_header.v, line:8:1, endln:29:10 |vpiName:vdd |vpiDirection:1 |vpiLowConn: @@ -27613,7 +27613,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (vddg), line:15:12, endln:15:16 |vpiParent: - \_module: work@oh_header (work@oh_header), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_header.v, line:8:1, endln:29:10 + \_module_inst: work@oh_header (work@oh_header), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_header.v, line:8:1, endln:29:10 |vpiName:vddg |vpiDirection:2 |vpiLowConn: @@ -27623,14 +27623,14 @@ design: (work@oh_fifo_async) |vpiTypedef: \_logic_typespec: , line:15:12, endln:15:12 |uhdmallModules: -\_module: work@oh_iddr (work@oh_iddr), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_iddr.v, line:8:1, endln:69:10 +\_module_inst: work@oh_iddr (work@oh_iddr), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_iddr.v, line:8:1, endln:69:10 |vpiParent: \_design: (work@oh_fifo_async) |vpiFullName:work@oh_iddr |vpiParameter: \_parameter: (work@oh_iddr.N), line:9:15, endln:9:16 |vpiParent: - \_module: work@oh_iddr (work@oh_iddr), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_iddr.v, line:8:1, endln:69:10 + \_module_inst: work@oh_iddr (work@oh_iddr), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_iddr.v, line:8:1, endln:69:10 |UINT:1 |vpiTypespec: \_int_typespec: @@ -27639,7 +27639,7 @@ design: (work@oh_fifo_async) |vpiParameter: \_parameter: (work@oh_iddr.SYN), line:10:15, endln:10:18 |vpiParent: - \_module: work@oh_iddr (work@oh_iddr), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_iddr.v, line:8:1, endln:69:10 + \_module_inst: work@oh_iddr (work@oh_iddr), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_iddr.v, line:8:1, endln:69:10 |STRING:TRUE |vpiTypespec: \_string_typespec: @@ -27648,7 +27648,7 @@ design: (work@oh_fifo_async) |vpiParameter: \_parameter: (work@oh_iddr.TYPE), line:11:15, endln:11:19 |vpiParent: - \_module: work@oh_iddr (work@oh_iddr), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_iddr.v, line:8:1, endln:69:10 + \_module_inst: work@oh_iddr (work@oh_iddr), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_iddr.v, line:8:1, endln:69:10 |STRING:DEFAULT |vpiTypespec: \_string_typespec: @@ -27657,7 +27657,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:9:15, endln:9:23 |vpiParent: - \_module: work@oh_iddr (work@oh_iddr), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_iddr.v, line:8:1, endln:69:10 + \_module_inst: work@oh_iddr (work@oh_iddr), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_iddr.v, line:8:1, endln:69:10 |vpiRhs: \_constant: , line:9:22, endln:9:23 |vpiDecompile:1 @@ -27671,7 +27671,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:10:15, endln:10:28 |vpiParent: - \_module: work@oh_iddr (work@oh_iddr), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_iddr.v, line:8:1, endln:69:10 + \_module_inst: work@oh_iddr (work@oh_iddr), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_iddr.v, line:8:1, endln:69:10 |vpiRhs: \_constant: , line:10:22, endln:10:28 |vpiDecompile:TRUE @@ -27685,7 +27685,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:11:15, endln:11:31 |vpiParent: - \_module: work@oh_iddr (work@oh_iddr), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_iddr.v, line:8:1, endln:69:10 + \_module_inst: work@oh_iddr (work@oh_iddr), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_iddr.v, line:8:1, endln:69:10 |vpiRhs: \_constant: , line:11:22, endln:11:31 |vpiDecompile:DEFAULT @@ -27701,38 +27701,38 @@ design: (work@oh_fifo_async) |vpiNet: \_logic_net: (work@oh_iddr.clk), line:14:14, endln:14:17 |vpiParent: - \_module: work@oh_iddr (work@oh_iddr), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_iddr.v, line:8:1, endln:69:10 + \_module_inst: work@oh_iddr (work@oh_iddr), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_iddr.v, line:8:1, endln:69:10 |vpiName:clk |vpiFullName:work@oh_iddr.clk |vpiNet: \_logic_net: (work@oh_iddr.en0), line:15:14, endln:15:17 |vpiParent: - \_module: work@oh_iddr (work@oh_iddr), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_iddr.v, line:8:1, endln:69:10 + \_module_inst: work@oh_iddr (work@oh_iddr), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_iddr.v, line:8:1, endln:69:10 |vpiName:en0 |vpiFullName:work@oh_iddr.en0 |vpiNet: \_logic_net: (work@oh_iddr.en1), line:16:14, endln:16:17 |vpiParent: - \_module: work@oh_iddr (work@oh_iddr), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_iddr.v, line:8:1, endln:69:10 + \_module_inst: work@oh_iddr (work@oh_iddr), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_iddr.v, line:8:1, endln:69:10 |vpiName:en1 |vpiFullName:work@oh_iddr.en1 |vpiNet: \_logic_net: (work@oh_iddr.in), line:17:21, endln:17:23 |vpiParent: - \_module: work@oh_iddr (work@oh_iddr), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_iddr.v, line:8:1, endln:69:10 + \_module_inst: work@oh_iddr (work@oh_iddr), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_iddr.v, line:8:1, endln:69:10 |vpiName:in |vpiFullName:work@oh_iddr.in |vpiNet: \_logic_net: (work@oh_iddr.out), line:18:26, endln:18:29 |vpiParent: - \_module: work@oh_iddr (work@oh_iddr), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_iddr.v, line:8:1, endln:69:10 + \_module_inst: work@oh_iddr (work@oh_iddr), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_iddr.v, line:8:1, endln:69:10 |vpiName:out |vpiFullName:work@oh_iddr.out |vpiNetType:48 |vpiPort: \_port: (clk), line:14:14, endln:14:17 |vpiParent: - \_module: work@oh_iddr (work@oh_iddr), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_iddr.v, line:8:1, endln:69:10 + \_module_inst: work@oh_iddr (work@oh_iddr), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_iddr.v, line:8:1, endln:69:10 |vpiName:clk |vpiDirection:1 |vpiLowConn: @@ -27744,7 +27744,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (en0), line:15:14, endln:15:17 |vpiParent: - \_module: work@oh_iddr (work@oh_iddr), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_iddr.v, line:8:1, endln:69:10 + \_module_inst: work@oh_iddr (work@oh_iddr), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_iddr.v, line:8:1, endln:69:10 |vpiName:en0 |vpiDirection:1 |vpiLowConn: @@ -27756,7 +27756,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (en1), line:16:14, endln:16:17 |vpiParent: - \_module: work@oh_iddr (work@oh_iddr), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_iddr.v, line:8:1, endln:69:10 + \_module_inst: work@oh_iddr (work@oh_iddr), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_iddr.v, line:8:1, endln:69:10 |vpiName:en1 |vpiDirection:1 |vpiLowConn: @@ -27768,7 +27768,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (in), line:17:21, endln:17:23 |vpiParent: - \_module: work@oh_iddr (work@oh_iddr), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_iddr.v, line:8:1, endln:69:10 + \_module_inst: work@oh_iddr (work@oh_iddr), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_iddr.v, line:8:1, endln:69:10 |vpiName:in |vpiDirection:1 |vpiLowConn: @@ -27808,7 +27808,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (out), line:18:26, endln:18:29 |vpiParent: - \_module: work@oh_iddr (work@oh_iddr), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_iddr.v, line:8:1, endln:69:10 + \_module_inst: work@oh_iddr (work@oh_iddr), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_iddr.v, line:8:1, endln:69:10 |vpiName:out |vpiDirection:2 |vpiLowConn: @@ -27859,14 +27859,14 @@ design: (work@oh_fifo_async) |UINT:0 |vpiConstType:9 |uhdmallModules: -\_module: work@oh_inv (work@oh_inv), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_inv.v, line:7:1, endln:15:10 +\_module_inst: work@oh_inv (work@oh_inv), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_inv.v, line:7:1, endln:15:10 |vpiParent: \_design: (work@oh_fifo_async) |vpiFullName:work@oh_inv |vpiParameter: \_parameter: (work@oh_inv.DW), line:7:27, endln:7:29 |vpiParent: - \_module: work@oh_inv (work@oh_inv), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_inv.v, line:7:1, endln:15:10 + \_module_inst: work@oh_inv (work@oh_inv), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_inv.v, line:7:1, endln:15:10 |UINT:1 |vpiTypespec: \_int_typespec: @@ -27875,7 +27875,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:7:27, endln:7:33 |vpiParent: - \_module: work@oh_inv (work@oh_inv), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_inv.v, line:7:1, endln:15:10 + \_module_inst: work@oh_inv (work@oh_inv), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_inv.v, line:7:1, endln:15:10 |vpiRhs: \_constant: , line:7:32, endln:7:33 |vpiDecompile:1 @@ -27891,19 +27891,19 @@ design: (work@oh_fifo_async) |vpiNet: \_logic_net: (work@oh_inv.a), line:9:21, endln:9:22 |vpiParent: - \_module: work@oh_inv (work@oh_inv), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_inv.v, line:7:1, endln:15:10 + \_module_inst: work@oh_inv (work@oh_inv), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_inv.v, line:7:1, endln:15:10 |vpiName:a |vpiFullName:work@oh_inv.a |vpiNet: \_logic_net: (work@oh_inv.z), line:10:21, endln:10:22 |vpiParent: - \_module: work@oh_inv (work@oh_inv), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_inv.v, line:7:1, endln:15:10 + \_module_inst: work@oh_inv (work@oh_inv), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_inv.v, line:7:1, endln:15:10 |vpiName:z |vpiFullName:work@oh_inv.z |vpiPort: \_port: (a), line:9:21, endln:9:22 |vpiParent: - \_module: work@oh_inv (work@oh_inv), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_inv.v, line:7:1, endln:15:10 + \_module_inst: work@oh_inv (work@oh_inv), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_inv.v, line:7:1, endln:15:10 |vpiName:a |vpiDirection:1 |vpiLowConn: @@ -27943,7 +27943,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (z), line:10:21, endln:10:22 |vpiParent: - \_module: work@oh_inv (work@oh_inv), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_inv.v, line:7:1, endln:15:10 + \_module_inst: work@oh_inv (work@oh_inv), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_inv.v, line:7:1, endln:15:10 |vpiName:z |vpiDirection:2 |vpiLowConn: @@ -27983,7 +27983,7 @@ design: (work@oh_fifo_async) |vpiContAssign: \_cont_assign: , line:13:11, endln:13:17 |vpiParent: - \_module: work@oh_inv (work@oh_inv), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_inv.v, line:7:1, endln:15:10 + \_module_inst: work@oh_inv (work@oh_inv), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_inv.v, line:7:1, endln:15:10 |vpiRhs: \_operation: , line:13:15, endln:13:17 |vpiParent: @@ -28002,14 +28002,14 @@ design: (work@oh_fifo_async) |vpiName:z |vpiFullName:work@oh_inv.z |uhdmallModules: -\_module: work@oh_isobufhi (work@oh_isobufhi), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_isobufhi.v, line:8:1, endln:32:10 +\_module_inst: work@oh_isobufhi (work@oh_isobufhi), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_isobufhi.v, line:8:1, endln:32:10 |vpiParent: \_design: (work@oh_fifo_async) |vpiFullName:work@oh_isobufhi |vpiParameter: \_parameter: (work@oh_isobufhi.N), line:9:15, endln:9:16 |vpiParent: - \_module: work@oh_isobufhi (work@oh_isobufhi), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_isobufhi.v, line:8:1, endln:32:10 + \_module_inst: work@oh_isobufhi (work@oh_isobufhi), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_isobufhi.v, line:8:1, endln:32:10 |UINT:1 |vpiTypespec: \_int_typespec: @@ -28018,7 +28018,7 @@ design: (work@oh_fifo_async) |vpiParameter: \_parameter: (work@oh_isobufhi.SYN), line:10:15, endln:10:18 |vpiParent: - \_module: work@oh_isobufhi (work@oh_isobufhi), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_isobufhi.v, line:8:1, endln:32:10 + \_module_inst: work@oh_isobufhi (work@oh_isobufhi), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_isobufhi.v, line:8:1, endln:32:10 |STRING:TRUE |vpiTypespec: \_string_typespec: @@ -28027,7 +28027,7 @@ design: (work@oh_fifo_async) |vpiParameter: \_parameter: (work@oh_isobufhi.TYPE), line:11:15, endln:11:19 |vpiParent: - \_module: work@oh_isobufhi (work@oh_isobufhi), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_isobufhi.v, line:8:1, endln:32:10 + \_module_inst: work@oh_isobufhi (work@oh_isobufhi), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_isobufhi.v, line:8:1, endln:32:10 |STRING:DEFAULT |vpiTypespec: \_string_typespec: @@ -28036,7 +28036,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:9:15, endln:9:24 |vpiParent: - \_module: work@oh_isobufhi (work@oh_isobufhi), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_isobufhi.v, line:8:1, endln:32:10 + \_module_inst: work@oh_isobufhi (work@oh_isobufhi), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_isobufhi.v, line:8:1, endln:32:10 |vpiRhs: \_constant: , line:9:23, endln:9:24 |vpiDecompile:1 @@ -28050,7 +28050,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:10:15, endln:10:29 |vpiParent: - \_module: work@oh_isobufhi (work@oh_isobufhi), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_isobufhi.v, line:8:1, endln:32:10 + \_module_inst: work@oh_isobufhi (work@oh_isobufhi), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_isobufhi.v, line:8:1, endln:32:10 |vpiRhs: \_constant: , line:10:23, endln:10:29 |vpiDecompile:TRUE @@ -28064,7 +28064,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:11:15, endln:11:32 |vpiParent: - \_module: work@oh_isobufhi (work@oh_isobufhi), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_isobufhi.v, line:8:1, endln:32:10 + \_module_inst: work@oh_isobufhi (work@oh_isobufhi), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_isobufhi.v, line:8:1, endln:32:10 |vpiRhs: \_constant: , line:11:23, endln:11:32 |vpiDecompile:DEFAULT @@ -28080,25 +28080,25 @@ design: (work@oh_fifo_async) |vpiNet: \_logic_net: (work@oh_isobufhi.iso), line:14:15, endln:14:18 |vpiParent: - \_module: work@oh_isobufhi (work@oh_isobufhi), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_isobufhi.v, line:8:1, endln:32:10 + \_module_inst: work@oh_isobufhi (work@oh_isobufhi), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_isobufhi.v, line:8:1, endln:32:10 |vpiName:iso |vpiFullName:work@oh_isobufhi.iso |vpiNet: \_logic_net: (work@oh_isobufhi.in), line:15:20, endln:15:22 |vpiParent: - \_module: work@oh_isobufhi (work@oh_isobufhi), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_isobufhi.v, line:8:1, endln:32:10 + \_module_inst: work@oh_isobufhi (work@oh_isobufhi), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_isobufhi.v, line:8:1, endln:32:10 |vpiName:in |vpiFullName:work@oh_isobufhi.in |vpiNet: \_logic_net: (work@oh_isobufhi.out), line:16:20, endln:16:23 |vpiParent: - \_module: work@oh_isobufhi (work@oh_isobufhi), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_isobufhi.v, line:8:1, endln:32:10 + \_module_inst: work@oh_isobufhi (work@oh_isobufhi), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_isobufhi.v, line:8:1, endln:32:10 |vpiName:out |vpiFullName:work@oh_isobufhi.out |vpiPort: \_port: (iso), line:14:15, endln:14:18 |vpiParent: - \_module: work@oh_isobufhi (work@oh_isobufhi), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_isobufhi.v, line:8:1, endln:32:10 + \_module_inst: work@oh_isobufhi (work@oh_isobufhi), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_isobufhi.v, line:8:1, endln:32:10 |vpiName:iso |vpiDirection:1 |vpiLowConn: @@ -28110,7 +28110,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (in), line:15:20, endln:15:22 |vpiParent: - \_module: work@oh_isobufhi (work@oh_isobufhi), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_isobufhi.v, line:8:1, endln:32:10 + \_module_inst: work@oh_isobufhi (work@oh_isobufhi), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_isobufhi.v, line:8:1, endln:32:10 |vpiName:in |vpiDirection:1 |vpiLowConn: @@ -28150,7 +28150,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (out), line:16:20, endln:16:23 |vpiParent: - \_module: work@oh_isobufhi (work@oh_isobufhi), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_isobufhi.v, line:8:1, endln:32:10 + \_module_inst: work@oh_isobufhi (work@oh_isobufhi), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_isobufhi.v, line:8:1, endln:32:10 |vpiName:out |vpiDirection:2 |vpiLowConn: @@ -28188,14 +28188,14 @@ design: (work@oh_fifo_async) |UINT:0 |vpiConstType:9 |uhdmallModules: -\_module: work@oh_isobuflo (work@oh_isobuflo), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_isobuflo.v, line:8:1, endln:34:10 +\_module_inst: work@oh_isobuflo (work@oh_isobuflo), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_isobuflo.v, line:8:1, endln:34:10 |vpiParent: \_design: (work@oh_fifo_async) |vpiFullName:work@oh_isobuflo |vpiParameter: \_parameter: (work@oh_isobuflo.N), line:9:15, endln:9:16 |vpiParent: - \_module: work@oh_isobuflo (work@oh_isobuflo), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_isobuflo.v, line:8:1, endln:34:10 + \_module_inst: work@oh_isobuflo (work@oh_isobuflo), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_isobuflo.v, line:8:1, endln:34:10 |UINT:1 |vpiTypespec: \_int_typespec: @@ -28204,7 +28204,7 @@ design: (work@oh_fifo_async) |vpiParameter: \_parameter: (work@oh_isobuflo.SYN), line:10:15, endln:10:18 |vpiParent: - \_module: work@oh_isobuflo (work@oh_isobuflo), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_isobuflo.v, line:8:1, endln:34:10 + \_module_inst: work@oh_isobuflo (work@oh_isobuflo), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_isobuflo.v, line:8:1, endln:34:10 |STRING:TRUE |vpiTypespec: \_string_typespec: @@ -28213,7 +28213,7 @@ design: (work@oh_fifo_async) |vpiParameter: \_parameter: (work@oh_isobuflo.TYPE), line:11:15, endln:11:19 |vpiParent: - \_module: work@oh_isobuflo (work@oh_isobuflo), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_isobuflo.v, line:8:1, endln:34:10 + \_module_inst: work@oh_isobuflo (work@oh_isobuflo), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_isobuflo.v, line:8:1, endln:34:10 |STRING:DEFAULT |vpiTypespec: \_string_typespec: @@ -28222,7 +28222,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:9:15, endln:9:24 |vpiParent: - \_module: work@oh_isobuflo (work@oh_isobuflo), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_isobuflo.v, line:8:1, endln:34:10 + \_module_inst: work@oh_isobuflo (work@oh_isobuflo), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_isobuflo.v, line:8:1, endln:34:10 |vpiRhs: \_constant: , line:9:23, endln:9:24 |vpiDecompile:1 @@ -28236,7 +28236,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:10:15, endln:10:29 |vpiParent: - \_module: work@oh_isobuflo (work@oh_isobuflo), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_isobuflo.v, line:8:1, endln:34:10 + \_module_inst: work@oh_isobuflo (work@oh_isobuflo), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_isobuflo.v, line:8:1, endln:34:10 |vpiRhs: \_constant: , line:10:23, endln:10:29 |vpiDecompile:TRUE @@ -28250,7 +28250,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:11:15, endln:11:32 |vpiParent: - \_module: work@oh_isobuflo (work@oh_isobuflo), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_isobuflo.v, line:8:1, endln:34:10 + \_module_inst: work@oh_isobuflo (work@oh_isobuflo), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_isobuflo.v, line:8:1, endln:34:10 |vpiRhs: \_constant: , line:11:23, endln:11:32 |vpiDecompile:DEFAULT @@ -28266,25 +28266,25 @@ design: (work@oh_fifo_async) |vpiNet: \_logic_net: (work@oh_isobuflo.iso), line:14:15, endln:14:18 |vpiParent: - \_module: work@oh_isobuflo (work@oh_isobuflo), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_isobuflo.v, line:8:1, endln:34:10 + \_module_inst: work@oh_isobuflo (work@oh_isobuflo), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_isobuflo.v, line:8:1, endln:34:10 |vpiName:iso |vpiFullName:work@oh_isobuflo.iso |vpiNet: \_logic_net: (work@oh_isobuflo.in), line:15:20, endln:15:22 |vpiParent: - \_module: work@oh_isobuflo (work@oh_isobuflo), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_isobuflo.v, line:8:1, endln:34:10 + \_module_inst: work@oh_isobuflo (work@oh_isobuflo), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_isobuflo.v, line:8:1, endln:34:10 |vpiName:in |vpiFullName:work@oh_isobuflo.in |vpiNet: \_logic_net: (work@oh_isobuflo.out), line:16:20, endln:16:23 |vpiParent: - \_module: work@oh_isobuflo (work@oh_isobuflo), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_isobuflo.v, line:8:1, endln:34:10 + \_module_inst: work@oh_isobuflo (work@oh_isobuflo), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_isobuflo.v, line:8:1, endln:34:10 |vpiName:out |vpiFullName:work@oh_isobuflo.out |vpiPort: \_port: (iso), line:14:15, endln:14:18 |vpiParent: - \_module: work@oh_isobuflo (work@oh_isobuflo), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_isobuflo.v, line:8:1, endln:34:10 + \_module_inst: work@oh_isobuflo (work@oh_isobuflo), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_isobuflo.v, line:8:1, endln:34:10 |vpiName:iso |vpiDirection:1 |vpiLowConn: @@ -28296,7 +28296,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (in), line:15:20, endln:15:22 |vpiParent: - \_module: work@oh_isobuflo (work@oh_isobuflo), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_isobuflo.v, line:8:1, endln:34:10 + \_module_inst: work@oh_isobuflo (work@oh_isobuflo), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_isobuflo.v, line:8:1, endln:34:10 |vpiName:in |vpiDirection:1 |vpiLowConn: @@ -28336,7 +28336,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (out), line:16:20, endln:16:23 |vpiParent: - \_module: work@oh_isobuflo (work@oh_isobuflo), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_isobuflo.v, line:8:1, endln:34:10 + \_module_inst: work@oh_isobuflo (work@oh_isobuflo), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_isobuflo.v, line:8:1, endln:34:10 |vpiName:out |vpiDirection:2 |vpiLowConn: @@ -28374,14 +28374,14 @@ design: (work@oh_fifo_async) |UINT:0 |vpiConstType:9 |uhdmallModules: -\_module: work@oh_lat0 (work@oh_lat0), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_lat0.v, line:8:1, endln:36:10 +\_module_inst: work@oh_lat0 (work@oh_lat0), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_lat0.v, line:8:1, endln:36:10 |vpiParent: \_design: (work@oh_fifo_async) |vpiFullName:work@oh_lat0 |vpiParameter: \_parameter: (work@oh_lat0.N), line:9:15, endln:9:16 |vpiParent: - \_module: work@oh_lat0 (work@oh_lat0), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_lat0.v, line:8:1, endln:36:10 + \_module_inst: work@oh_lat0 (work@oh_lat0), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_lat0.v, line:8:1, endln:36:10 |UINT:1 |vpiTypespec: \_int_typespec: @@ -28390,7 +28390,7 @@ design: (work@oh_fifo_async) |vpiParameter: \_parameter: (work@oh_lat0.SYN), line:10:15, endln:10:18 |vpiParent: - \_module: work@oh_lat0 (work@oh_lat0), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_lat0.v, line:8:1, endln:36:10 + \_module_inst: work@oh_lat0 (work@oh_lat0), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_lat0.v, line:8:1, endln:36:10 |STRING:TRUE |vpiTypespec: \_string_typespec: @@ -28399,7 +28399,7 @@ design: (work@oh_fifo_async) |vpiParameter: \_parameter: (work@oh_lat0.TYPE), line:11:15, endln:11:19 |vpiParent: - \_module: work@oh_lat0 (work@oh_lat0), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_lat0.v, line:8:1, endln:36:10 + \_module_inst: work@oh_lat0 (work@oh_lat0), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_lat0.v, line:8:1, endln:36:10 |STRING:DEFAULT |vpiTypespec: \_string_typespec: @@ -28408,7 +28408,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:9:15, endln:9:23 |vpiParent: - \_module: work@oh_lat0 (work@oh_lat0), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_lat0.v, line:8:1, endln:36:10 + \_module_inst: work@oh_lat0 (work@oh_lat0), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_lat0.v, line:8:1, endln:36:10 |vpiRhs: \_constant: , line:9:22, endln:9:23 |vpiDecompile:1 @@ -28422,7 +28422,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:10:15, endln:10:28 |vpiParent: - \_module: work@oh_lat0 (work@oh_lat0), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_lat0.v, line:8:1, endln:36:10 + \_module_inst: work@oh_lat0 (work@oh_lat0), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_lat0.v, line:8:1, endln:36:10 |vpiRhs: \_constant: , line:10:22, endln:10:28 |vpiDecompile:TRUE @@ -28436,7 +28436,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:11:15, endln:11:31 |vpiParent: - \_module: work@oh_lat0 (work@oh_lat0), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_lat0.v, line:8:1, endln:36:10 + \_module_inst: work@oh_lat0 (work@oh_lat0), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_lat0.v, line:8:1, endln:36:10 |vpiRhs: \_constant: , line:11:22, endln:11:31 |vpiDecompile:DEFAULT @@ -28452,25 +28452,25 @@ design: (work@oh_fifo_async) |vpiNet: \_logic_net: (work@oh_lat0.clk), line:13:15, endln:13:18 |vpiParent: - \_module: work@oh_lat0 (work@oh_lat0), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_lat0.v, line:8:1, endln:36:10 + \_module_inst: work@oh_lat0 (work@oh_lat0), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_lat0.v, line:8:1, endln:36:10 |vpiName:clk |vpiFullName:work@oh_lat0.clk |vpiNet: \_logic_net: (work@oh_lat0.in), line:14:20, endln:14:22 |vpiParent: - \_module: work@oh_lat0 (work@oh_lat0), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_lat0.v, line:8:1, endln:36:10 + \_module_inst: work@oh_lat0 (work@oh_lat0), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_lat0.v, line:8:1, endln:36:10 |vpiName:in |vpiFullName:work@oh_lat0.in |vpiNet: \_logic_net: (work@oh_lat0.out), line:15:20, endln:15:23 |vpiParent: - \_module: work@oh_lat0 (work@oh_lat0), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_lat0.v, line:8:1, endln:36:10 + \_module_inst: work@oh_lat0 (work@oh_lat0), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_lat0.v, line:8:1, endln:36:10 |vpiName:out |vpiFullName:work@oh_lat0.out |vpiPort: \_port: (clk), line:13:15, endln:13:18 |vpiParent: - \_module: work@oh_lat0 (work@oh_lat0), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_lat0.v, line:8:1, endln:36:10 + \_module_inst: work@oh_lat0 (work@oh_lat0), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_lat0.v, line:8:1, endln:36:10 |vpiName:clk |vpiDirection:1 |vpiLowConn: @@ -28482,7 +28482,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (in), line:14:20, endln:14:22 |vpiParent: - \_module: work@oh_lat0 (work@oh_lat0), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_lat0.v, line:8:1, endln:36:10 + \_module_inst: work@oh_lat0 (work@oh_lat0), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_lat0.v, line:8:1, endln:36:10 |vpiName:in |vpiDirection:1 |vpiLowConn: @@ -28522,7 +28522,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (out), line:15:20, endln:15:23 |vpiParent: - \_module: work@oh_lat0 (work@oh_lat0), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_lat0.v, line:8:1, endln:36:10 + \_module_inst: work@oh_lat0 (work@oh_lat0), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_lat0.v, line:8:1, endln:36:10 |vpiName:out |vpiDirection:2 |vpiLowConn: @@ -28560,14 +28560,14 @@ design: (work@oh_fifo_async) |UINT:0 |vpiConstType:9 |uhdmallModules: -\_module: work@oh_lat1 (work@oh_lat1), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_lat1.v, line:8:1, endln:37:10 +\_module_inst: work@oh_lat1 (work@oh_lat1), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_lat1.v, line:8:1, endln:37:10 |vpiParent: \_design: (work@oh_fifo_async) |vpiFullName:work@oh_lat1 |vpiParameter: \_parameter: (work@oh_lat1.N), line:9:15, endln:9:16 |vpiParent: - \_module: work@oh_lat1 (work@oh_lat1), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_lat1.v, line:8:1, endln:37:10 + \_module_inst: work@oh_lat1 (work@oh_lat1), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_lat1.v, line:8:1, endln:37:10 |UINT:1 |vpiTypespec: \_int_typespec: @@ -28576,7 +28576,7 @@ design: (work@oh_fifo_async) |vpiParameter: \_parameter: (work@oh_lat1.SYN), line:10:15, endln:10:18 |vpiParent: - \_module: work@oh_lat1 (work@oh_lat1), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_lat1.v, line:8:1, endln:37:10 + \_module_inst: work@oh_lat1 (work@oh_lat1), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_lat1.v, line:8:1, endln:37:10 |STRING:TRUE |vpiTypespec: \_string_typespec: @@ -28585,7 +28585,7 @@ design: (work@oh_fifo_async) |vpiParameter: \_parameter: (work@oh_lat1.TYPE), line:11:15, endln:11:19 |vpiParent: - \_module: work@oh_lat1 (work@oh_lat1), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_lat1.v, line:8:1, endln:37:10 + \_module_inst: work@oh_lat1 (work@oh_lat1), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_lat1.v, line:8:1, endln:37:10 |STRING:DEFAULT |vpiTypespec: \_string_typespec: @@ -28594,7 +28594,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:9:15, endln:9:23 |vpiParent: - \_module: work@oh_lat1 (work@oh_lat1), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_lat1.v, line:8:1, endln:37:10 + \_module_inst: work@oh_lat1 (work@oh_lat1), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_lat1.v, line:8:1, endln:37:10 |vpiRhs: \_constant: , line:9:22, endln:9:23 |vpiDecompile:1 @@ -28608,7 +28608,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:10:15, endln:10:28 |vpiParent: - \_module: work@oh_lat1 (work@oh_lat1), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_lat1.v, line:8:1, endln:37:10 + \_module_inst: work@oh_lat1 (work@oh_lat1), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_lat1.v, line:8:1, endln:37:10 |vpiRhs: \_constant: , line:10:22, endln:10:28 |vpiDecompile:TRUE @@ -28622,7 +28622,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:11:15, endln:11:31 |vpiParent: - \_module: work@oh_lat1 (work@oh_lat1), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_lat1.v, line:8:1, endln:37:10 + \_module_inst: work@oh_lat1 (work@oh_lat1), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_lat1.v, line:8:1, endln:37:10 |vpiRhs: \_constant: , line:11:22, endln:11:31 |vpiDecompile:DEFAULT @@ -28638,25 +28638,25 @@ design: (work@oh_fifo_async) |vpiNet: \_logic_net: (work@oh_lat1.clk), line:13:15, endln:13:18 |vpiParent: - \_module: work@oh_lat1 (work@oh_lat1), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_lat1.v, line:8:1, endln:37:10 + \_module_inst: work@oh_lat1 (work@oh_lat1), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_lat1.v, line:8:1, endln:37:10 |vpiName:clk |vpiFullName:work@oh_lat1.clk |vpiNet: \_logic_net: (work@oh_lat1.in), line:14:20, endln:14:22 |vpiParent: - \_module: work@oh_lat1 (work@oh_lat1), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_lat1.v, line:8:1, endln:37:10 + \_module_inst: work@oh_lat1 (work@oh_lat1), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_lat1.v, line:8:1, endln:37:10 |vpiName:in |vpiFullName:work@oh_lat1.in |vpiNet: \_logic_net: (work@oh_lat1.out), line:15:20, endln:15:23 |vpiParent: - \_module: work@oh_lat1 (work@oh_lat1), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_lat1.v, line:8:1, endln:37:10 + \_module_inst: work@oh_lat1 (work@oh_lat1), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_lat1.v, line:8:1, endln:37:10 |vpiName:out |vpiFullName:work@oh_lat1.out |vpiPort: \_port: (clk), line:13:15, endln:13:18 |vpiParent: - \_module: work@oh_lat1 (work@oh_lat1), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_lat1.v, line:8:1, endln:37:10 + \_module_inst: work@oh_lat1 (work@oh_lat1), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_lat1.v, line:8:1, endln:37:10 |vpiName:clk |vpiDirection:1 |vpiLowConn: @@ -28668,7 +28668,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (in), line:14:20, endln:14:22 |vpiParent: - \_module: work@oh_lat1 (work@oh_lat1), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_lat1.v, line:8:1, endln:37:10 + \_module_inst: work@oh_lat1 (work@oh_lat1), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_lat1.v, line:8:1, endln:37:10 |vpiName:in |vpiDirection:1 |vpiLowConn: @@ -28708,7 +28708,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (out), line:15:20, endln:15:23 |vpiParent: - \_module: work@oh_lat1 (work@oh_lat1), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_lat1.v, line:8:1, endln:37:10 + \_module_inst: work@oh_lat1 (work@oh_lat1), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_lat1.v, line:8:1, endln:37:10 |vpiName:out |vpiDirection:2 |vpiLowConn: @@ -28746,14 +28746,14 @@ design: (work@oh_fifo_async) |UINT:0 |vpiConstType:9 |uhdmallModules: -\_module: work@oh_latnq (work@oh_latnq), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_latnq.v, line:8:1, endln:19:10 +\_module_inst: work@oh_latnq (work@oh_latnq), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_latnq.v, line:8:1, endln:19:10 |vpiParent: \_design: (work@oh_fifo_async) |vpiFullName:work@oh_latnq |vpiParameter: \_parameter: (work@oh_latnq.DW), line:8:29, endln:8:31 |vpiParent: - \_module: work@oh_latnq (work@oh_latnq), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_latnq.v, line:8:1, endln:19:10 + \_module_inst: work@oh_latnq (work@oh_latnq), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_latnq.v, line:8:1, endln:19:10 |UINT:1 |vpiTypespec: \_int_typespec: @@ -28762,7 +28762,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:8:29, endln:8:35 |vpiParent: - \_module: work@oh_latnq (work@oh_latnq), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_latnq.v, line:8:1, endln:19:10 + \_module_inst: work@oh_latnq (work@oh_latnq), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_latnq.v, line:8:1, endln:19:10 |vpiRhs: \_constant: , line:8:34, endln:8:35 |vpiDecompile:1 @@ -28778,26 +28778,26 @@ design: (work@oh_fifo_async) |vpiNet: \_logic_net: (work@oh_latnq.d), line:10:21, endln:10:22 |vpiParent: - \_module: work@oh_latnq (work@oh_latnq), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_latnq.v, line:8:1, endln:19:10 + \_module_inst: work@oh_latnq (work@oh_latnq), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_latnq.v, line:8:1, endln:19:10 |vpiName:d |vpiFullName:work@oh_latnq.d |vpiNet: \_logic_net: (work@oh_latnq.gn), line:11:21, endln:11:23 |vpiParent: - \_module: work@oh_latnq (work@oh_latnq), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_latnq.v, line:8:1, endln:19:10 + \_module_inst: work@oh_latnq (work@oh_latnq), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_latnq.v, line:8:1, endln:19:10 |vpiName:gn |vpiFullName:work@oh_latnq.gn |vpiNet: \_logic_net: (work@oh_latnq.q), line:12:25, endln:12:26 |vpiParent: - \_module: work@oh_latnq (work@oh_latnq), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_latnq.v, line:8:1, endln:19:10 + \_module_inst: work@oh_latnq (work@oh_latnq), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_latnq.v, line:8:1, endln:19:10 |vpiName:q |vpiFullName:work@oh_latnq.q |vpiNetType:48 |vpiPort: \_port: (d), line:10:21, endln:10:22 |vpiParent: - \_module: work@oh_latnq (work@oh_latnq), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_latnq.v, line:8:1, endln:19:10 + \_module_inst: work@oh_latnq (work@oh_latnq), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_latnq.v, line:8:1, endln:19:10 |vpiName:d |vpiDirection:1 |vpiLowConn: @@ -28837,7 +28837,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (gn), line:11:21, endln:11:23 |vpiParent: - \_module: work@oh_latnq (work@oh_latnq), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_latnq.v, line:8:1, endln:19:10 + \_module_inst: work@oh_latnq (work@oh_latnq), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_latnq.v, line:8:1, endln:19:10 |vpiName:gn |vpiDirection:1 |vpiLowConn: @@ -28877,7 +28877,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (q), line:12:25, endln:12:26 |vpiParent: - \_module: work@oh_latnq (work@oh_latnq), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_latnq.v, line:8:1, endln:19:10 + \_module_inst: work@oh_latnq (work@oh_latnq), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_latnq.v, line:8:1, endln:19:10 |vpiName:q |vpiDirection:2 |vpiLowConn: @@ -28917,7 +28917,7 @@ design: (work@oh_fifo_async) |vpiProcess: \_always: , line:15:4, endln:17:15 |vpiParent: - \_module: work@oh_latnq (work@oh_latnq), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_latnq.v, line:8:1, endln:19:10 + \_module_inst: work@oh_latnq (work@oh_latnq), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_latnq.v, line:8:1, endln:19:10 |vpiStmt: \_if_stmt: , line:16:6, endln:17:15 |vpiParent: @@ -28952,14 +28952,14 @@ design: (work@oh_fifo_async) |vpiFullName:work@oh_latnq.q |vpiAlwaysType:4 |uhdmallModules: -\_module: work@oh_latq (work@oh_latq), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_latq.v, line:8:1, endln:19:10 +\_module_inst: work@oh_latq (work@oh_latq), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_latq.v, line:8:1, endln:19:10 |vpiParent: \_design: (work@oh_fifo_async) |vpiFullName:work@oh_latq |vpiParameter: \_parameter: (work@oh_latq.DW), line:8:28, endln:8:30 |vpiParent: - \_module: work@oh_latq (work@oh_latq), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_latq.v, line:8:1, endln:19:10 + \_module_inst: work@oh_latq (work@oh_latq), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_latq.v, line:8:1, endln:19:10 |UINT:1 |vpiTypespec: \_int_typespec: @@ -28968,7 +28968,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:8:28, endln:8:34 |vpiParent: - \_module: work@oh_latq (work@oh_latq), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_latq.v, line:8:1, endln:19:10 + \_module_inst: work@oh_latq (work@oh_latq), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_latq.v, line:8:1, endln:19:10 |vpiRhs: \_constant: , line:8:33, endln:8:34 |vpiDecompile:1 @@ -28984,26 +28984,26 @@ design: (work@oh_fifo_async) |vpiNet: \_logic_net: (work@oh_latq.d), line:10:21, endln:10:22 |vpiParent: - \_module: work@oh_latq (work@oh_latq), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_latq.v, line:8:1, endln:19:10 + \_module_inst: work@oh_latq (work@oh_latq), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_latq.v, line:8:1, endln:19:10 |vpiName:d |vpiFullName:work@oh_latq.d |vpiNet: \_logic_net: (work@oh_latq.g), line:11:21, endln:11:22 |vpiParent: - \_module: work@oh_latq (work@oh_latq), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_latq.v, line:8:1, endln:19:10 + \_module_inst: work@oh_latq (work@oh_latq), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_latq.v, line:8:1, endln:19:10 |vpiName:g |vpiFullName:work@oh_latq.g |vpiNet: \_logic_net: (work@oh_latq.q), line:12:25, endln:12:26 |vpiParent: - \_module: work@oh_latq (work@oh_latq), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_latq.v, line:8:1, endln:19:10 + \_module_inst: work@oh_latq (work@oh_latq), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_latq.v, line:8:1, endln:19:10 |vpiName:q |vpiFullName:work@oh_latq.q |vpiNetType:48 |vpiPort: \_port: (d), line:10:21, endln:10:22 |vpiParent: - \_module: work@oh_latq (work@oh_latq), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_latq.v, line:8:1, endln:19:10 + \_module_inst: work@oh_latq (work@oh_latq), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_latq.v, line:8:1, endln:19:10 |vpiName:d |vpiDirection:1 |vpiLowConn: @@ -29043,7 +29043,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (g), line:11:21, endln:11:22 |vpiParent: - \_module: work@oh_latq (work@oh_latq), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_latq.v, line:8:1, endln:19:10 + \_module_inst: work@oh_latq (work@oh_latq), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_latq.v, line:8:1, endln:19:10 |vpiName:g |vpiDirection:1 |vpiLowConn: @@ -29083,7 +29083,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (q), line:12:25, endln:12:26 |vpiParent: - \_module: work@oh_latq (work@oh_latq), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_latq.v, line:8:1, endln:19:10 + \_module_inst: work@oh_latq (work@oh_latq), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_latq.v, line:8:1, endln:19:10 |vpiName:q |vpiDirection:2 |vpiLowConn: @@ -29123,7 +29123,7 @@ design: (work@oh_fifo_async) |vpiProcess: \_always: , line:15:4, endln:17:15 |vpiParent: - \_module: work@oh_latq (work@oh_latq), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_latq.v, line:8:1, endln:19:10 + \_module_inst: work@oh_latq (work@oh_latq), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_latq.v, line:8:1, endln:19:10 |vpiStmt: \_if_stmt: , line:16:6, endln:17:15 |vpiParent: @@ -29153,14 +29153,14 @@ design: (work@oh_fifo_async) |vpiFullName:work@oh_latq.q |vpiAlwaysType:4 |uhdmallModules: -\_module: work@oh_memory_dp (work@oh_memory_dp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_memory_dp.v, line:8:1, endln:78:10 +\_module_inst: work@oh_memory_dp (work@oh_memory_dp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_memory_dp.v, line:8:1, endln:78:10 |vpiParent: \_design: (work@oh_fifo_async) |vpiFullName:work@oh_memory_dp |vpiParameter: \_parameter: (work@oh_memory_dp.N), line:9:15, endln:9:16 |vpiParent: - \_module: work@oh_memory_dp (work@oh_memory_dp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_memory_dp.v, line:8:1, endln:78:10 + \_module_inst: work@oh_memory_dp (work@oh_memory_dp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_memory_dp.v, line:8:1, endln:78:10 |UINT:32 |vpiTypespec: \_int_typespec: @@ -29169,7 +29169,7 @@ design: (work@oh_fifo_async) |vpiParameter: \_parameter: (work@oh_memory_dp.DEPTH), line:10:15, endln:10:20 |vpiParent: - \_module: work@oh_memory_dp (work@oh_memory_dp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_memory_dp.v, line:8:1, endln:78:10 + \_module_inst: work@oh_memory_dp (work@oh_memory_dp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_memory_dp.v, line:8:1, endln:78:10 |UINT:32 |vpiTypespec: \_int_typespec: @@ -29178,7 +29178,7 @@ design: (work@oh_fifo_async) |vpiParameter: \_parameter: (work@oh_memory_dp.REG), line:11:15, endln:11:18 |vpiParent: - \_module: work@oh_memory_dp (work@oh_memory_dp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_memory_dp.v, line:8:1, endln:78:10 + \_module_inst: work@oh_memory_dp (work@oh_memory_dp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_memory_dp.v, line:8:1, endln:78:10 |UINT:1 |vpiTypespec: \_int_typespec: @@ -29187,7 +29187,7 @@ design: (work@oh_fifo_async) |vpiParameter: \_parameter: (work@oh_memory_dp.SYN), line:12:15, endln:12:18 |vpiParent: - \_module: work@oh_memory_dp (work@oh_memory_dp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_memory_dp.v, line:8:1, endln:78:10 + \_module_inst: work@oh_memory_dp (work@oh_memory_dp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_memory_dp.v, line:8:1, endln:78:10 |STRING:TRUE |vpiTypespec: \_string_typespec: @@ -29196,7 +29196,7 @@ design: (work@oh_fifo_async) |vpiParameter: \_parameter: (work@oh_memory_dp.TYPE), line:13:15, endln:13:19 |vpiParent: - \_module: work@oh_memory_dp (work@oh_memory_dp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_memory_dp.v, line:8:1, endln:78:10 + \_module_inst: work@oh_memory_dp (work@oh_memory_dp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_memory_dp.v, line:8:1, endln:78:10 |STRING:DEFAULT |vpiTypespec: \_string_typespec: @@ -29205,7 +29205,7 @@ design: (work@oh_fifo_async) |vpiParameter: \_parameter: (work@oh_memory_dp.SHAPE), line:14:15, endln:14:20 |vpiParent: - \_module: work@oh_memory_dp (work@oh_memory_dp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_memory_dp.v, line:8:1, endln:78:10 + \_module_inst: work@oh_memory_dp (work@oh_memory_dp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_memory_dp.v, line:8:1, endln:78:10 |STRING:SQUARE |vpiTypespec: \_string_typespec: @@ -29214,13 +29214,13 @@ design: (work@oh_fifo_async) |vpiParameter: \_parameter: (work@oh_memory_dp.AW), line:15:15, endln:15:17 |vpiParent: - \_module: work@oh_memory_dp (work@oh_memory_dp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_memory_dp.v, line:8:1, endln:78:10 + \_module_inst: work@oh_memory_dp (work@oh_memory_dp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_memory_dp.v, line:8:1, endln:78:10 |vpiName:AW |vpiFullName:work@oh_memory_dp.AW |vpiParamAssign: \_param_assign: , line:9:15, endln:9:27 |vpiParent: - \_module: work@oh_memory_dp (work@oh_memory_dp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_memory_dp.v, line:8:1, endln:78:10 + \_module_inst: work@oh_memory_dp (work@oh_memory_dp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_memory_dp.v, line:8:1, endln:78:10 |vpiRhs: \_constant: , line:9:25, endln:9:27 |vpiDecompile:32 @@ -29234,7 +29234,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:10:15, endln:10:27 |vpiParent: - \_module: work@oh_memory_dp (work@oh_memory_dp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_memory_dp.v, line:8:1, endln:78:10 + \_module_inst: work@oh_memory_dp (work@oh_memory_dp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_memory_dp.v, line:8:1, endln:78:10 |vpiRhs: \_constant: , line:10:25, endln:10:27 |vpiDecompile:32 @@ -29248,7 +29248,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:11:15, endln:11:26 |vpiParent: - \_module: work@oh_memory_dp (work@oh_memory_dp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_memory_dp.v, line:8:1, endln:78:10 + \_module_inst: work@oh_memory_dp (work@oh_memory_dp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_memory_dp.v, line:8:1, endln:78:10 |vpiRhs: \_constant: , line:11:25, endln:11:26 |vpiDecompile:1 @@ -29262,7 +29262,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:12:15, endln:12:31 |vpiParent: - \_module: work@oh_memory_dp (work@oh_memory_dp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_memory_dp.v, line:8:1, endln:78:10 + \_module_inst: work@oh_memory_dp (work@oh_memory_dp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_memory_dp.v, line:8:1, endln:78:10 |vpiRhs: \_constant: , line:12:25, endln:12:31 |vpiDecompile:TRUE @@ -29276,7 +29276,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:13:15, endln:13:34 |vpiParent: - \_module: work@oh_memory_dp (work@oh_memory_dp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_memory_dp.v, line:8:1, endln:78:10 + \_module_inst: work@oh_memory_dp (work@oh_memory_dp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_memory_dp.v, line:8:1, endln:78:10 |vpiRhs: \_constant: , line:13:25, endln:13:34 |vpiDecompile:DEFAULT @@ -29290,7 +29290,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:14:15, endln:14:33 |vpiParent: - \_module: work@oh_memory_dp (work@oh_memory_dp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_memory_dp.v, line:8:1, endln:78:10 + \_module_inst: work@oh_memory_dp (work@oh_memory_dp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_memory_dp.v, line:8:1, endln:78:10 |vpiRhs: \_constant: , line:14:25, endln:14:33 |vpiDecompile:SQUARE @@ -29304,7 +29304,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:15:15, endln:15:38 |vpiParent: - \_module: work@oh_memory_dp (work@oh_memory_dp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_memory_dp.v, line:8:1, endln:78:10 + \_module_inst: work@oh_memory_dp (work@oh_memory_dp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_memory_dp.v, line:8:1, endln:78:10 |vpiRhs: \_sys_func_call: ($clog2), line:15:25, endln:15:38 |vpiArgument: @@ -29320,127 +29320,127 @@ design: (work@oh_fifo_async) |vpiNet: \_logic_net: (work@oh_memory_dp.wr_clk), line:18:16, endln:18:22 |vpiParent: - \_module: work@oh_memory_dp (work@oh_memory_dp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_memory_dp.v, line:8:1, endln:78:10 + \_module_inst: work@oh_memory_dp (work@oh_memory_dp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_memory_dp.v, line:8:1, endln:78:10 |vpiName:wr_clk |vpiFullName:work@oh_memory_dp.wr_clk |vpiNet: \_logic_net: (work@oh_memory_dp.wr_en), line:19:16, endln:19:21 |vpiParent: - \_module: work@oh_memory_dp (work@oh_memory_dp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_memory_dp.v, line:8:1, endln:78:10 + \_module_inst: work@oh_memory_dp (work@oh_memory_dp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_memory_dp.v, line:8:1, endln:78:10 |vpiName:wr_en |vpiFullName:work@oh_memory_dp.wr_en |vpiNet: \_logic_net: (work@oh_memory_dp.wr_wem), line:20:20, endln:20:26 |vpiParent: - \_module: work@oh_memory_dp (work@oh_memory_dp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_memory_dp.v, line:8:1, endln:78:10 + \_module_inst: work@oh_memory_dp (work@oh_memory_dp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_memory_dp.v, line:8:1, endln:78:10 |vpiName:wr_wem |vpiFullName:work@oh_memory_dp.wr_wem |vpiNet: \_logic_net: (work@oh_memory_dp.wr_addr), line:21:21, endln:21:28 |vpiParent: - \_module: work@oh_memory_dp (work@oh_memory_dp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_memory_dp.v, line:8:1, endln:78:10 + \_module_inst: work@oh_memory_dp (work@oh_memory_dp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_memory_dp.v, line:8:1, endln:78:10 |vpiName:wr_addr |vpiFullName:work@oh_memory_dp.wr_addr |vpiNet: \_logic_net: (work@oh_memory_dp.wr_din), line:22:20, endln:22:26 |vpiParent: - \_module: work@oh_memory_dp (work@oh_memory_dp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_memory_dp.v, line:8:1, endln:78:10 + \_module_inst: work@oh_memory_dp (work@oh_memory_dp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_memory_dp.v, line:8:1, endln:78:10 |vpiName:wr_din |vpiFullName:work@oh_memory_dp.wr_din |vpiNet: \_logic_net: (work@oh_memory_dp.rd_clk), line:23:16, endln:23:22 |vpiParent: - \_module: work@oh_memory_dp (work@oh_memory_dp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_memory_dp.v, line:8:1, endln:78:10 + \_module_inst: work@oh_memory_dp (work@oh_memory_dp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_memory_dp.v, line:8:1, endln:78:10 |vpiName:rd_clk |vpiFullName:work@oh_memory_dp.rd_clk |vpiNet: \_logic_net: (work@oh_memory_dp.rd_en), line:24:16, endln:24:21 |vpiParent: - \_module: work@oh_memory_dp (work@oh_memory_dp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_memory_dp.v, line:8:1, endln:78:10 + \_module_inst: work@oh_memory_dp (work@oh_memory_dp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_memory_dp.v, line:8:1, endln:78:10 |vpiName:rd_en |vpiFullName:work@oh_memory_dp.rd_en |vpiNet: \_logic_net: (work@oh_memory_dp.rd_addr), line:25:21, endln:25:28 |vpiParent: - \_module: work@oh_memory_dp (work@oh_memory_dp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_memory_dp.v, line:8:1, endln:78:10 + \_module_inst: work@oh_memory_dp (work@oh_memory_dp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_memory_dp.v, line:8:1, endln:78:10 |vpiName:rd_addr |vpiFullName:work@oh_memory_dp.rd_addr |vpiNet: \_logic_net: (work@oh_memory_dp.rd_dout), line:26:20, endln:26:27 |vpiParent: - \_module: work@oh_memory_dp (work@oh_memory_dp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_memory_dp.v, line:8:1, endln:78:10 + \_module_inst: work@oh_memory_dp (work@oh_memory_dp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_memory_dp.v, line:8:1, endln:78:10 |vpiName:rd_dout |vpiFullName:work@oh_memory_dp.rd_dout |vpiNet: \_logic_net: (work@oh_memory_dp.bist_en), line:28:16, endln:28:23 |vpiParent: - \_module: work@oh_memory_dp (work@oh_memory_dp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_memory_dp.v, line:8:1, endln:78:10 + \_module_inst: work@oh_memory_dp (work@oh_memory_dp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_memory_dp.v, line:8:1, endln:78:10 |vpiName:bist_en |vpiFullName:work@oh_memory_dp.bist_en |vpiNet: \_logic_net: (work@oh_memory_dp.bist_we), line:29:16, endln:29:23 |vpiParent: - \_module: work@oh_memory_dp (work@oh_memory_dp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_memory_dp.v, line:8:1, endln:78:10 + \_module_inst: work@oh_memory_dp (work@oh_memory_dp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_memory_dp.v, line:8:1, endln:78:10 |vpiName:bist_we |vpiFullName:work@oh_memory_dp.bist_we |vpiNet: \_logic_net: (work@oh_memory_dp.bist_wem), line:30:20, endln:30:28 |vpiParent: - \_module: work@oh_memory_dp (work@oh_memory_dp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_memory_dp.v, line:8:1, endln:78:10 + \_module_inst: work@oh_memory_dp (work@oh_memory_dp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_memory_dp.v, line:8:1, endln:78:10 |vpiName:bist_wem |vpiFullName:work@oh_memory_dp.bist_wem |vpiNet: \_logic_net: (work@oh_memory_dp.bist_addr), line:31:21, endln:31:30 |vpiParent: - \_module: work@oh_memory_dp (work@oh_memory_dp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_memory_dp.v, line:8:1, endln:78:10 + \_module_inst: work@oh_memory_dp (work@oh_memory_dp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_memory_dp.v, line:8:1, endln:78:10 |vpiName:bist_addr |vpiFullName:work@oh_memory_dp.bist_addr |vpiNet: \_logic_net: (work@oh_memory_dp.bist_din), line:32:20, endln:32:28 |vpiParent: - \_module: work@oh_memory_dp (work@oh_memory_dp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_memory_dp.v, line:8:1, endln:78:10 + \_module_inst: work@oh_memory_dp (work@oh_memory_dp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_memory_dp.v, line:8:1, endln:78:10 |vpiName:bist_din |vpiFullName:work@oh_memory_dp.bist_din |vpiNet: \_logic_net: (work@oh_memory_dp.shutdown), line:34:16, endln:34:24 |vpiParent: - \_module: work@oh_memory_dp (work@oh_memory_dp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_memory_dp.v, line:8:1, endln:78:10 + \_module_inst: work@oh_memory_dp (work@oh_memory_dp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_memory_dp.v, line:8:1, endln:78:10 |vpiName:shutdown |vpiFullName:work@oh_memory_dp.shutdown |vpiNet: \_logic_net: (work@oh_memory_dp.vss), line:35:16, endln:35:19 |vpiParent: - \_module: work@oh_memory_dp (work@oh_memory_dp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_memory_dp.v, line:8:1, endln:78:10 + \_module_inst: work@oh_memory_dp (work@oh_memory_dp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_memory_dp.v, line:8:1, endln:78:10 |vpiName:vss |vpiFullName:work@oh_memory_dp.vss |vpiNet: \_logic_net: (work@oh_memory_dp.vdd), line:36:16, endln:36:19 |vpiParent: - \_module: work@oh_memory_dp (work@oh_memory_dp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_memory_dp.v, line:8:1, endln:78:10 + \_module_inst: work@oh_memory_dp (work@oh_memory_dp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_memory_dp.v, line:8:1, endln:78:10 |vpiName:vdd |vpiFullName:work@oh_memory_dp.vdd |vpiNet: \_logic_net: (work@oh_memory_dp.vddio), line:37:16, endln:37:21 |vpiParent: - \_module: work@oh_memory_dp (work@oh_memory_dp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_memory_dp.v, line:8:1, endln:78:10 + \_module_inst: work@oh_memory_dp (work@oh_memory_dp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_memory_dp.v, line:8:1, endln:78:10 |vpiName:vddio |vpiFullName:work@oh_memory_dp.vddio |vpiNet: \_logic_net: (work@oh_memory_dp.memconfig), line:38:21, endln:38:30 |vpiParent: - \_module: work@oh_memory_dp (work@oh_memory_dp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_memory_dp.v, line:8:1, endln:78:10 + \_module_inst: work@oh_memory_dp (work@oh_memory_dp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_memory_dp.v, line:8:1, endln:78:10 |vpiName:memconfig |vpiFullName:work@oh_memory_dp.memconfig |vpiNet: \_logic_net: (work@oh_memory_dp.memrepair), line:39:21, endln:39:30 |vpiParent: - \_module: work@oh_memory_dp (work@oh_memory_dp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_memory_dp.v, line:8:1, endln:78:10 + \_module_inst: work@oh_memory_dp (work@oh_memory_dp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_memory_dp.v, line:8:1, endln:78:10 |vpiName:memrepair |vpiFullName:work@oh_memory_dp.memrepair |vpiPort: \_port: (wr_clk), line:18:16, endln:18:22 |vpiParent: - \_module: work@oh_memory_dp (work@oh_memory_dp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_memory_dp.v, line:8:1, endln:78:10 + \_module_inst: work@oh_memory_dp (work@oh_memory_dp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_memory_dp.v, line:8:1, endln:78:10 |vpiName:wr_clk |vpiDirection:1 |vpiLowConn: @@ -29452,7 +29452,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (wr_en), line:19:16, endln:19:21 |vpiParent: - \_module: work@oh_memory_dp (work@oh_memory_dp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_memory_dp.v, line:8:1, endln:78:10 + \_module_inst: work@oh_memory_dp (work@oh_memory_dp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_memory_dp.v, line:8:1, endln:78:10 |vpiName:wr_en |vpiDirection:1 |vpiLowConn: @@ -29464,7 +29464,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (wr_wem), line:20:20, endln:20:26 |vpiParent: - \_module: work@oh_memory_dp (work@oh_memory_dp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_memory_dp.v, line:8:1, endln:78:10 + \_module_inst: work@oh_memory_dp (work@oh_memory_dp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_memory_dp.v, line:8:1, endln:78:10 |vpiName:wr_wem |vpiDirection:1 |vpiLowConn: @@ -29504,7 +29504,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (wr_addr), line:21:21, endln:21:28 |vpiParent: - \_module: work@oh_memory_dp (work@oh_memory_dp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_memory_dp.v, line:8:1, endln:78:10 + \_module_inst: work@oh_memory_dp (work@oh_memory_dp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_memory_dp.v, line:8:1, endln:78:10 |vpiName:wr_addr |vpiDirection:1 |vpiLowConn: @@ -29544,7 +29544,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (wr_din), line:22:20, endln:22:26 |vpiParent: - \_module: work@oh_memory_dp (work@oh_memory_dp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_memory_dp.v, line:8:1, endln:78:10 + \_module_inst: work@oh_memory_dp (work@oh_memory_dp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_memory_dp.v, line:8:1, endln:78:10 |vpiName:wr_din |vpiDirection:1 |vpiLowConn: @@ -29584,7 +29584,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (rd_clk), line:23:16, endln:23:22 |vpiParent: - \_module: work@oh_memory_dp (work@oh_memory_dp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_memory_dp.v, line:8:1, endln:78:10 + \_module_inst: work@oh_memory_dp (work@oh_memory_dp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_memory_dp.v, line:8:1, endln:78:10 |vpiName:rd_clk |vpiDirection:1 |vpiLowConn: @@ -29596,7 +29596,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (rd_en), line:24:16, endln:24:21 |vpiParent: - \_module: work@oh_memory_dp (work@oh_memory_dp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_memory_dp.v, line:8:1, endln:78:10 + \_module_inst: work@oh_memory_dp (work@oh_memory_dp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_memory_dp.v, line:8:1, endln:78:10 |vpiName:rd_en |vpiDirection:1 |vpiLowConn: @@ -29608,7 +29608,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (rd_addr), line:25:21, endln:25:28 |vpiParent: - \_module: work@oh_memory_dp (work@oh_memory_dp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_memory_dp.v, line:8:1, endln:78:10 + \_module_inst: work@oh_memory_dp (work@oh_memory_dp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_memory_dp.v, line:8:1, endln:78:10 |vpiName:rd_addr |vpiDirection:1 |vpiLowConn: @@ -29648,7 +29648,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (rd_dout), line:26:20, endln:26:27 |vpiParent: - \_module: work@oh_memory_dp (work@oh_memory_dp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_memory_dp.v, line:8:1, endln:78:10 + \_module_inst: work@oh_memory_dp (work@oh_memory_dp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_memory_dp.v, line:8:1, endln:78:10 |vpiName:rd_dout |vpiDirection:2 |vpiLowConn: @@ -29688,7 +29688,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (bist_en), line:28:16, endln:28:23 |vpiParent: - \_module: work@oh_memory_dp (work@oh_memory_dp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_memory_dp.v, line:8:1, endln:78:10 + \_module_inst: work@oh_memory_dp (work@oh_memory_dp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_memory_dp.v, line:8:1, endln:78:10 |vpiName:bist_en |vpiDirection:1 |vpiLowConn: @@ -29700,7 +29700,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (bist_we), line:29:16, endln:29:23 |vpiParent: - \_module: work@oh_memory_dp (work@oh_memory_dp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_memory_dp.v, line:8:1, endln:78:10 + \_module_inst: work@oh_memory_dp (work@oh_memory_dp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_memory_dp.v, line:8:1, endln:78:10 |vpiName:bist_we |vpiDirection:1 |vpiLowConn: @@ -29712,7 +29712,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (bist_wem), line:30:20, endln:30:28 |vpiParent: - \_module: work@oh_memory_dp (work@oh_memory_dp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_memory_dp.v, line:8:1, endln:78:10 + \_module_inst: work@oh_memory_dp (work@oh_memory_dp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_memory_dp.v, line:8:1, endln:78:10 |vpiName:bist_wem |vpiDirection:1 |vpiLowConn: @@ -29752,7 +29752,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (bist_addr), line:31:21, endln:31:30 |vpiParent: - \_module: work@oh_memory_dp (work@oh_memory_dp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_memory_dp.v, line:8:1, endln:78:10 + \_module_inst: work@oh_memory_dp (work@oh_memory_dp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_memory_dp.v, line:8:1, endln:78:10 |vpiName:bist_addr |vpiDirection:1 |vpiLowConn: @@ -29792,7 +29792,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (bist_din), line:32:20, endln:32:28 |vpiParent: - \_module: work@oh_memory_dp (work@oh_memory_dp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_memory_dp.v, line:8:1, endln:78:10 + \_module_inst: work@oh_memory_dp (work@oh_memory_dp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_memory_dp.v, line:8:1, endln:78:10 |vpiName:bist_din |vpiDirection:1 |vpiLowConn: @@ -29832,7 +29832,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (shutdown), line:34:16, endln:34:24 |vpiParent: - \_module: work@oh_memory_dp (work@oh_memory_dp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_memory_dp.v, line:8:1, endln:78:10 + \_module_inst: work@oh_memory_dp (work@oh_memory_dp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_memory_dp.v, line:8:1, endln:78:10 |vpiName:shutdown |vpiDirection:1 |vpiLowConn: @@ -29844,7 +29844,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (vss), line:35:16, endln:35:19 |vpiParent: - \_module: work@oh_memory_dp (work@oh_memory_dp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_memory_dp.v, line:8:1, endln:78:10 + \_module_inst: work@oh_memory_dp (work@oh_memory_dp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_memory_dp.v, line:8:1, endln:78:10 |vpiName:vss |vpiDirection:1 |vpiLowConn: @@ -29856,7 +29856,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (vdd), line:36:16, endln:36:19 |vpiParent: - \_module: work@oh_memory_dp (work@oh_memory_dp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_memory_dp.v, line:8:1, endln:78:10 + \_module_inst: work@oh_memory_dp (work@oh_memory_dp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_memory_dp.v, line:8:1, endln:78:10 |vpiName:vdd |vpiDirection:1 |vpiLowConn: @@ -29868,7 +29868,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (vddio), line:37:16, endln:37:21 |vpiParent: - \_module: work@oh_memory_dp (work@oh_memory_dp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_memory_dp.v, line:8:1, endln:78:10 + \_module_inst: work@oh_memory_dp (work@oh_memory_dp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_memory_dp.v, line:8:1, endln:78:10 |vpiName:vddio |vpiDirection:1 |vpiLowConn: @@ -29880,7 +29880,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (memconfig), line:38:21, endln:38:30 |vpiParent: - \_module: work@oh_memory_dp (work@oh_memory_dp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_memory_dp.v, line:8:1, endln:78:10 + \_module_inst: work@oh_memory_dp (work@oh_memory_dp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_memory_dp.v, line:8:1, endln:78:10 |vpiName:memconfig |vpiDirection:1 |vpiLowConn: @@ -29910,7 +29910,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (memrepair), line:39:21, endln:39:30 |vpiParent: - \_module: work@oh_memory_dp (work@oh_memory_dp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_memory_dp.v, line:8:1, endln:78:10 + \_module_inst: work@oh_memory_dp (work@oh_memory_dp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_memory_dp.v, line:8:1, endln:78:10 |vpiName:memrepair |vpiDirection:1 |vpiLowConn: @@ -29938,14 +29938,14 @@ design: (work@oh_fifo_async) |UINT:0 |vpiConstType:9 |uhdmallModules: -\_module: work@oh_memory_sp (work@oh_memory_sp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_memory_sp.v, line:8:1, endln:75:10 +\_module_inst: work@oh_memory_sp (work@oh_memory_sp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_memory_sp.v, line:8:1, endln:75:10 |vpiParent: \_design: (work@oh_fifo_async) |vpiFullName:work@oh_memory_sp |vpiParameter: \_parameter: (work@oh_memory_sp.N), line:9:15, endln:9:16 |vpiParent: - \_module: work@oh_memory_sp (work@oh_memory_sp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_memory_sp.v, line:8:1, endln:75:10 + \_module_inst: work@oh_memory_sp (work@oh_memory_sp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_memory_sp.v, line:8:1, endln:75:10 |UINT:32 |vpiTypespec: \_int_typespec: @@ -29954,7 +29954,7 @@ design: (work@oh_fifo_async) |vpiParameter: \_parameter: (work@oh_memory_sp.DEPTH), line:10:15, endln:10:20 |vpiParent: - \_module: work@oh_memory_sp (work@oh_memory_sp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_memory_sp.v, line:8:1, endln:75:10 + \_module_inst: work@oh_memory_sp (work@oh_memory_sp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_memory_sp.v, line:8:1, endln:75:10 |UINT:32 |vpiTypespec: \_int_typespec: @@ -29963,7 +29963,7 @@ design: (work@oh_fifo_async) |vpiParameter: \_parameter: (work@oh_memory_sp.REG), line:11:15, endln:11:18 |vpiParent: - \_module: work@oh_memory_sp (work@oh_memory_sp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_memory_sp.v, line:8:1, endln:75:10 + \_module_inst: work@oh_memory_sp (work@oh_memory_sp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_memory_sp.v, line:8:1, endln:75:10 |UINT:1 |vpiTypespec: \_int_typespec: @@ -29972,7 +29972,7 @@ design: (work@oh_fifo_async) |vpiParameter: \_parameter: (work@oh_memory_sp.SYN), line:12:15, endln:12:18 |vpiParent: - \_module: work@oh_memory_sp (work@oh_memory_sp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_memory_sp.v, line:8:1, endln:75:10 + \_module_inst: work@oh_memory_sp (work@oh_memory_sp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_memory_sp.v, line:8:1, endln:75:10 |STRING:TRUE |vpiTypespec: \_string_typespec: @@ -29981,7 +29981,7 @@ design: (work@oh_fifo_async) |vpiParameter: \_parameter: (work@oh_memory_sp.TYPE), line:13:15, endln:13:19 |vpiParent: - \_module: work@oh_memory_sp (work@oh_memory_sp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_memory_sp.v, line:8:1, endln:75:10 + \_module_inst: work@oh_memory_sp (work@oh_memory_sp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_memory_sp.v, line:8:1, endln:75:10 |STRING:DEFAULT |vpiTypespec: \_string_typespec: @@ -29990,7 +29990,7 @@ design: (work@oh_fifo_async) |vpiParameter: \_parameter: (work@oh_memory_sp.SHAPE), line:14:15, endln:14:20 |vpiParent: - \_module: work@oh_memory_sp (work@oh_memory_sp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_memory_sp.v, line:8:1, endln:75:10 + \_module_inst: work@oh_memory_sp (work@oh_memory_sp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_memory_sp.v, line:8:1, endln:75:10 |STRING:SQUARE |vpiTypespec: \_string_typespec: @@ -29999,13 +29999,13 @@ design: (work@oh_fifo_async) |vpiParameter: \_parameter: (work@oh_memory_sp.AW), line:15:15, endln:15:17 |vpiParent: - \_module: work@oh_memory_sp (work@oh_memory_sp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_memory_sp.v, line:8:1, endln:75:10 + \_module_inst: work@oh_memory_sp (work@oh_memory_sp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_memory_sp.v, line:8:1, endln:75:10 |vpiName:AW |vpiFullName:work@oh_memory_sp.AW |vpiParamAssign: \_param_assign: , line:9:15, endln:9:27 |vpiParent: - \_module: work@oh_memory_sp (work@oh_memory_sp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_memory_sp.v, line:8:1, endln:75:10 + \_module_inst: work@oh_memory_sp (work@oh_memory_sp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_memory_sp.v, line:8:1, endln:75:10 |vpiRhs: \_constant: , line:9:25, endln:9:27 |vpiDecompile:32 @@ -30019,7 +30019,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:10:15, endln:10:27 |vpiParent: - \_module: work@oh_memory_sp (work@oh_memory_sp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_memory_sp.v, line:8:1, endln:75:10 + \_module_inst: work@oh_memory_sp (work@oh_memory_sp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_memory_sp.v, line:8:1, endln:75:10 |vpiRhs: \_constant: , line:10:25, endln:10:27 |vpiDecompile:32 @@ -30033,7 +30033,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:11:15, endln:11:26 |vpiParent: - \_module: work@oh_memory_sp (work@oh_memory_sp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_memory_sp.v, line:8:1, endln:75:10 + \_module_inst: work@oh_memory_sp (work@oh_memory_sp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_memory_sp.v, line:8:1, endln:75:10 |vpiRhs: \_constant: , line:11:25, endln:11:26 |vpiDecompile:1 @@ -30047,7 +30047,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:12:15, endln:12:31 |vpiParent: - \_module: work@oh_memory_sp (work@oh_memory_sp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_memory_sp.v, line:8:1, endln:75:10 + \_module_inst: work@oh_memory_sp (work@oh_memory_sp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_memory_sp.v, line:8:1, endln:75:10 |vpiRhs: \_constant: , line:12:25, endln:12:31 |vpiDecompile:TRUE @@ -30061,7 +30061,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:13:15, endln:13:34 |vpiParent: - \_module: work@oh_memory_sp (work@oh_memory_sp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_memory_sp.v, line:8:1, endln:75:10 + \_module_inst: work@oh_memory_sp (work@oh_memory_sp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_memory_sp.v, line:8:1, endln:75:10 |vpiRhs: \_constant: , line:13:25, endln:13:34 |vpiDecompile:DEFAULT @@ -30075,7 +30075,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:14:15, endln:14:33 |vpiParent: - \_module: work@oh_memory_sp (work@oh_memory_sp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_memory_sp.v, line:8:1, endln:75:10 + \_module_inst: work@oh_memory_sp (work@oh_memory_sp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_memory_sp.v, line:8:1, endln:75:10 |vpiRhs: \_constant: , line:14:25, endln:14:33 |vpiDecompile:SQUARE @@ -30089,7 +30089,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:15:15, endln:15:38 |vpiParent: - \_module: work@oh_memory_sp (work@oh_memory_sp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_memory_sp.v, line:8:1, endln:75:10 + \_module_inst: work@oh_memory_sp (work@oh_memory_sp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_memory_sp.v, line:8:1, endln:75:10 |vpiRhs: \_sys_func_call: ($clog2), line:15:25, endln:15:38 |vpiArgument: @@ -30105,109 +30105,109 @@ design: (work@oh_fifo_async) |vpiNet: \_logic_net: (work@oh_memory_sp.clk), line:18:15, endln:18:18 |vpiParent: - \_module: work@oh_memory_sp (work@oh_memory_sp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_memory_sp.v, line:8:1, endln:75:10 + \_module_inst: work@oh_memory_sp (work@oh_memory_sp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_memory_sp.v, line:8:1, endln:75:10 |vpiName:clk |vpiFullName:work@oh_memory_sp.clk |vpiNet: \_logic_net: (work@oh_memory_sp.en), line:19:15, endln:19:17 |vpiParent: - \_module: work@oh_memory_sp (work@oh_memory_sp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_memory_sp.v, line:8:1, endln:75:10 + \_module_inst: work@oh_memory_sp (work@oh_memory_sp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_memory_sp.v, line:8:1, endln:75:10 |vpiName:en |vpiFullName:work@oh_memory_sp.en |vpiNet: \_logic_net: (work@oh_memory_sp.wem), line:20:20, endln:20:23 |vpiParent: - \_module: work@oh_memory_sp (work@oh_memory_sp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_memory_sp.v, line:8:1, endln:75:10 + \_module_inst: work@oh_memory_sp (work@oh_memory_sp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_memory_sp.v, line:8:1, endln:75:10 |vpiName:wem |vpiFullName:work@oh_memory_sp.wem |vpiNet: \_logic_net: (work@oh_memory_sp.addr), line:21:20, endln:21:24 |vpiParent: - \_module: work@oh_memory_sp (work@oh_memory_sp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_memory_sp.v, line:8:1, endln:75:10 + \_module_inst: work@oh_memory_sp (work@oh_memory_sp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_memory_sp.v, line:8:1, endln:75:10 |vpiName:addr |vpiFullName:work@oh_memory_sp.addr |vpiNet: \_logic_net: (work@oh_memory_sp.din), line:22:20, endln:22:23 |vpiParent: - \_module: work@oh_memory_sp (work@oh_memory_sp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_memory_sp.v, line:8:1, endln:75:10 + \_module_inst: work@oh_memory_sp (work@oh_memory_sp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_memory_sp.v, line:8:1, endln:75:10 |vpiName:din |vpiFullName:work@oh_memory_sp.din |vpiNet: \_logic_net: (work@oh_memory_sp.dout), line:23:20, endln:23:24 |vpiParent: - \_module: work@oh_memory_sp (work@oh_memory_sp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_memory_sp.v, line:8:1, endln:75:10 + \_module_inst: work@oh_memory_sp (work@oh_memory_sp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_memory_sp.v, line:8:1, endln:75:10 |vpiName:dout |vpiFullName:work@oh_memory_sp.dout |vpiNet: \_logic_net: (work@oh_memory_sp.bist_en), line:25:15, endln:25:22 |vpiParent: - \_module: work@oh_memory_sp (work@oh_memory_sp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_memory_sp.v, line:8:1, endln:75:10 + \_module_inst: work@oh_memory_sp (work@oh_memory_sp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_memory_sp.v, line:8:1, endln:75:10 |vpiName:bist_en |vpiFullName:work@oh_memory_sp.bist_en |vpiNet: \_logic_net: (work@oh_memory_sp.bist_we), line:26:15, endln:26:22 |vpiParent: - \_module: work@oh_memory_sp (work@oh_memory_sp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_memory_sp.v, line:8:1, endln:75:10 + \_module_inst: work@oh_memory_sp (work@oh_memory_sp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_memory_sp.v, line:8:1, endln:75:10 |vpiName:bist_we |vpiFullName:work@oh_memory_sp.bist_we |vpiNet: \_logic_net: (work@oh_memory_sp.bist_wem), line:27:20, endln:27:28 |vpiParent: - \_module: work@oh_memory_sp (work@oh_memory_sp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_memory_sp.v, line:8:1, endln:75:10 + \_module_inst: work@oh_memory_sp (work@oh_memory_sp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_memory_sp.v, line:8:1, endln:75:10 |vpiName:bist_wem |vpiFullName:work@oh_memory_sp.bist_wem |vpiNet: \_logic_net: (work@oh_memory_sp.bist_addr), line:28:20, endln:28:29 |vpiParent: - \_module: work@oh_memory_sp (work@oh_memory_sp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_memory_sp.v, line:8:1, endln:75:10 + \_module_inst: work@oh_memory_sp (work@oh_memory_sp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_memory_sp.v, line:8:1, endln:75:10 |vpiName:bist_addr |vpiFullName:work@oh_memory_sp.bist_addr |vpiNet: \_logic_net: (work@oh_memory_sp.bist_din), line:29:20, endln:29:28 |vpiParent: - \_module: work@oh_memory_sp (work@oh_memory_sp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_memory_sp.v, line:8:1, endln:75:10 + \_module_inst: work@oh_memory_sp (work@oh_memory_sp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_memory_sp.v, line:8:1, endln:75:10 |vpiName:bist_din |vpiFullName:work@oh_memory_sp.bist_din |vpiNet: \_logic_net: (work@oh_memory_sp.shutdown), line:31:15, endln:31:23 |vpiParent: - \_module: work@oh_memory_sp (work@oh_memory_sp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_memory_sp.v, line:8:1, endln:75:10 + \_module_inst: work@oh_memory_sp (work@oh_memory_sp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_memory_sp.v, line:8:1, endln:75:10 |vpiName:shutdown |vpiFullName:work@oh_memory_sp.shutdown |vpiNet: \_logic_net: (work@oh_memory_sp.vss), line:32:15, endln:32:18 |vpiParent: - \_module: work@oh_memory_sp (work@oh_memory_sp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_memory_sp.v, line:8:1, endln:75:10 + \_module_inst: work@oh_memory_sp (work@oh_memory_sp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_memory_sp.v, line:8:1, endln:75:10 |vpiName:vss |vpiFullName:work@oh_memory_sp.vss |vpiNet: \_logic_net: (work@oh_memory_sp.vdd), line:33:15, endln:33:18 |vpiParent: - \_module: work@oh_memory_sp (work@oh_memory_sp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_memory_sp.v, line:8:1, endln:75:10 + \_module_inst: work@oh_memory_sp (work@oh_memory_sp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_memory_sp.v, line:8:1, endln:75:10 |vpiName:vdd |vpiFullName:work@oh_memory_sp.vdd |vpiNet: \_logic_net: (work@oh_memory_sp.vddio), line:34:15, endln:34:20 |vpiParent: - \_module: work@oh_memory_sp (work@oh_memory_sp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_memory_sp.v, line:8:1, endln:75:10 + \_module_inst: work@oh_memory_sp (work@oh_memory_sp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_memory_sp.v, line:8:1, endln:75:10 |vpiName:vddio |vpiFullName:work@oh_memory_sp.vddio |vpiNet: \_logic_net: (work@oh_memory_sp.memconfig), line:35:20, endln:35:29 |vpiParent: - \_module: work@oh_memory_sp (work@oh_memory_sp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_memory_sp.v, line:8:1, endln:75:10 + \_module_inst: work@oh_memory_sp (work@oh_memory_sp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_memory_sp.v, line:8:1, endln:75:10 |vpiName:memconfig |vpiFullName:work@oh_memory_sp.memconfig |vpiNet: \_logic_net: (work@oh_memory_sp.memrepair), line:36:20, endln:36:29 |vpiParent: - \_module: work@oh_memory_sp (work@oh_memory_sp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_memory_sp.v, line:8:1, endln:75:10 + \_module_inst: work@oh_memory_sp (work@oh_memory_sp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_memory_sp.v, line:8:1, endln:75:10 |vpiName:memrepair |vpiFullName:work@oh_memory_sp.memrepair |vpiPort: \_port: (clk), line:18:15, endln:18:18 |vpiParent: - \_module: work@oh_memory_sp (work@oh_memory_sp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_memory_sp.v, line:8:1, endln:75:10 + \_module_inst: work@oh_memory_sp (work@oh_memory_sp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_memory_sp.v, line:8:1, endln:75:10 |vpiName:clk |vpiDirection:1 |vpiLowConn: @@ -30219,7 +30219,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (en), line:19:15, endln:19:17 |vpiParent: - \_module: work@oh_memory_sp (work@oh_memory_sp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_memory_sp.v, line:8:1, endln:75:10 + \_module_inst: work@oh_memory_sp (work@oh_memory_sp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_memory_sp.v, line:8:1, endln:75:10 |vpiName:en |vpiDirection:1 |vpiLowConn: @@ -30231,7 +30231,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (wem), line:20:20, endln:20:23 |vpiParent: - \_module: work@oh_memory_sp (work@oh_memory_sp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_memory_sp.v, line:8:1, endln:75:10 + \_module_inst: work@oh_memory_sp (work@oh_memory_sp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_memory_sp.v, line:8:1, endln:75:10 |vpiName:wem |vpiDirection:1 |vpiLowConn: @@ -30271,7 +30271,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (addr), line:21:20, endln:21:24 |vpiParent: - \_module: work@oh_memory_sp (work@oh_memory_sp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_memory_sp.v, line:8:1, endln:75:10 + \_module_inst: work@oh_memory_sp (work@oh_memory_sp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_memory_sp.v, line:8:1, endln:75:10 |vpiName:addr |vpiDirection:1 |vpiLowConn: @@ -30311,7 +30311,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (din), line:22:20, endln:22:23 |vpiParent: - \_module: work@oh_memory_sp (work@oh_memory_sp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_memory_sp.v, line:8:1, endln:75:10 + \_module_inst: work@oh_memory_sp (work@oh_memory_sp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_memory_sp.v, line:8:1, endln:75:10 |vpiName:din |vpiDirection:1 |vpiLowConn: @@ -30351,7 +30351,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (dout), line:23:20, endln:23:24 |vpiParent: - \_module: work@oh_memory_sp (work@oh_memory_sp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_memory_sp.v, line:8:1, endln:75:10 + \_module_inst: work@oh_memory_sp (work@oh_memory_sp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_memory_sp.v, line:8:1, endln:75:10 |vpiName:dout |vpiDirection:2 |vpiLowConn: @@ -30391,7 +30391,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (bist_en), line:25:15, endln:25:22 |vpiParent: - \_module: work@oh_memory_sp (work@oh_memory_sp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_memory_sp.v, line:8:1, endln:75:10 + \_module_inst: work@oh_memory_sp (work@oh_memory_sp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_memory_sp.v, line:8:1, endln:75:10 |vpiName:bist_en |vpiDirection:1 |vpiLowConn: @@ -30403,7 +30403,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (bist_we), line:26:15, endln:26:22 |vpiParent: - \_module: work@oh_memory_sp (work@oh_memory_sp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_memory_sp.v, line:8:1, endln:75:10 + \_module_inst: work@oh_memory_sp (work@oh_memory_sp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_memory_sp.v, line:8:1, endln:75:10 |vpiName:bist_we |vpiDirection:1 |vpiLowConn: @@ -30415,7 +30415,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (bist_wem), line:27:20, endln:27:28 |vpiParent: - \_module: work@oh_memory_sp (work@oh_memory_sp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_memory_sp.v, line:8:1, endln:75:10 + \_module_inst: work@oh_memory_sp (work@oh_memory_sp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_memory_sp.v, line:8:1, endln:75:10 |vpiName:bist_wem |vpiDirection:1 |vpiLowConn: @@ -30455,7 +30455,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (bist_addr), line:28:20, endln:28:29 |vpiParent: - \_module: work@oh_memory_sp (work@oh_memory_sp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_memory_sp.v, line:8:1, endln:75:10 + \_module_inst: work@oh_memory_sp (work@oh_memory_sp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_memory_sp.v, line:8:1, endln:75:10 |vpiName:bist_addr |vpiDirection:1 |vpiLowConn: @@ -30495,7 +30495,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (bist_din), line:29:20, endln:29:28 |vpiParent: - \_module: work@oh_memory_sp (work@oh_memory_sp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_memory_sp.v, line:8:1, endln:75:10 + \_module_inst: work@oh_memory_sp (work@oh_memory_sp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_memory_sp.v, line:8:1, endln:75:10 |vpiName:bist_din |vpiDirection:1 |vpiLowConn: @@ -30535,7 +30535,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (shutdown), line:31:15, endln:31:23 |vpiParent: - \_module: work@oh_memory_sp (work@oh_memory_sp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_memory_sp.v, line:8:1, endln:75:10 + \_module_inst: work@oh_memory_sp (work@oh_memory_sp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_memory_sp.v, line:8:1, endln:75:10 |vpiName:shutdown |vpiDirection:1 |vpiLowConn: @@ -30547,7 +30547,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (vss), line:32:15, endln:32:18 |vpiParent: - \_module: work@oh_memory_sp (work@oh_memory_sp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_memory_sp.v, line:8:1, endln:75:10 + \_module_inst: work@oh_memory_sp (work@oh_memory_sp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_memory_sp.v, line:8:1, endln:75:10 |vpiName:vss |vpiDirection:1 |vpiLowConn: @@ -30559,7 +30559,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (vdd), line:33:15, endln:33:18 |vpiParent: - \_module: work@oh_memory_sp (work@oh_memory_sp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_memory_sp.v, line:8:1, endln:75:10 + \_module_inst: work@oh_memory_sp (work@oh_memory_sp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_memory_sp.v, line:8:1, endln:75:10 |vpiName:vdd |vpiDirection:1 |vpiLowConn: @@ -30571,7 +30571,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (vddio), line:34:15, endln:34:20 |vpiParent: - \_module: work@oh_memory_sp (work@oh_memory_sp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_memory_sp.v, line:8:1, endln:75:10 + \_module_inst: work@oh_memory_sp (work@oh_memory_sp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_memory_sp.v, line:8:1, endln:75:10 |vpiName:vddio |vpiDirection:1 |vpiLowConn: @@ -30583,7 +30583,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (memconfig), line:35:20, endln:35:29 |vpiParent: - \_module: work@oh_memory_sp (work@oh_memory_sp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_memory_sp.v, line:8:1, endln:75:10 + \_module_inst: work@oh_memory_sp (work@oh_memory_sp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_memory_sp.v, line:8:1, endln:75:10 |vpiName:memconfig |vpiDirection:1 |vpiLowConn: @@ -30613,7 +30613,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (memrepair), line:36:20, endln:36:29 |vpiParent: - \_module: work@oh_memory_sp (work@oh_memory_sp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_memory_sp.v, line:8:1, endln:75:10 + \_module_inst: work@oh_memory_sp (work@oh_memory_sp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_memory_sp.v, line:8:1, endln:75:10 |vpiName:memrepair |vpiDirection:1 |vpiLowConn: @@ -30641,14 +30641,14 @@ design: (work@oh_fifo_async) |UINT:0 |vpiConstType:9 |uhdmallModules: -\_module: work@oh_mult (work@oh_mult), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mult.v, line:10:1, endln:49:10 +\_module_inst: work@oh_mult (work@oh_mult), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mult.v, line:10:1, endln:49:10 |vpiParent: \_design: (work@oh_fifo_async) |vpiFullName:work@oh_mult |vpiParameter: \_parameter: (work@oh_mult.N), line:11:15, endln:11:16 |vpiParent: - \_module: work@oh_mult (work@oh_mult), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mult.v, line:10:1, endln:49:10 + \_module_inst: work@oh_mult (work@oh_mult), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mult.v, line:10:1, endln:49:10 |UINT:32 |vpiTypespec: \_int_typespec: @@ -30657,7 +30657,7 @@ design: (work@oh_fifo_async) |vpiParameter: \_parameter: (work@oh_mult.SYN), line:12:15, endln:12:18 |vpiParent: - \_module: work@oh_mult (work@oh_mult), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mult.v, line:10:1, endln:49:10 + \_module_inst: work@oh_mult (work@oh_mult), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mult.v, line:10:1, endln:49:10 |STRING:TRUE |vpiTypespec: \_string_typespec: @@ -30666,7 +30666,7 @@ design: (work@oh_fifo_async) |vpiParameter: \_parameter: (work@oh_mult.TYPE), line:13:15, endln:13:19 |vpiParent: - \_module: work@oh_mult (work@oh_mult), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mult.v, line:10:1, endln:49:10 + \_module_inst: work@oh_mult (work@oh_mult), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mult.v, line:10:1, endln:49:10 |STRING:DEFAULT |vpiTypespec: \_string_typespec: @@ -30675,7 +30675,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:11:15, endln:11:24 |vpiParent: - \_module: work@oh_mult (work@oh_mult), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mult.v, line:10:1, endln:49:10 + \_module_inst: work@oh_mult (work@oh_mult), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mult.v, line:10:1, endln:49:10 |vpiRhs: \_constant: , line:11:22, endln:11:24 |vpiDecompile:32 @@ -30689,7 +30689,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:12:15, endln:12:28 |vpiParent: - \_module: work@oh_mult (work@oh_mult), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mult.v, line:10:1, endln:49:10 + \_module_inst: work@oh_mult (work@oh_mult), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mult.v, line:10:1, endln:49:10 |vpiRhs: \_constant: , line:12:22, endln:12:28 |vpiDecompile:TRUE @@ -30703,7 +30703,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:13:15, endln:13:31 |vpiParent: - \_module: work@oh_mult (work@oh_mult), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mult.v, line:10:1, endln:49:10 + \_module_inst: work@oh_mult (work@oh_mult), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mult.v, line:10:1, endln:49:10 |vpiRhs: \_constant: , line:13:22, endln:13:31 |vpiDecompile:DEFAULT @@ -30719,49 +30719,49 @@ design: (work@oh_fifo_async) |vpiNet: \_logic_net: (work@oh_mult.a), line:17:22, endln:17:23 |vpiParent: - \_module: work@oh_mult (work@oh_mult), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mult.v, line:10:1, endln:49:10 + \_module_inst: work@oh_mult (work@oh_mult), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mult.v, line:10:1, endln:49:10 |vpiName:a |vpiFullName:work@oh_mult.a |vpiNet: \_logic_net: (work@oh_mult.b), line:18:22, endln:18:23 |vpiParent: - \_module: work@oh_mult (work@oh_mult), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mult.v, line:10:1, endln:49:10 + \_module_inst: work@oh_mult (work@oh_mult), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mult.v, line:10:1, endln:49:10 |vpiName:b |vpiFullName:work@oh_mult.b |vpiNet: \_logic_net: (work@oh_mult.asigned), line:19:18, endln:19:25 |vpiParent: - \_module: work@oh_mult (work@oh_mult), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mult.v, line:10:1, endln:49:10 + \_module_inst: work@oh_mult (work@oh_mult), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mult.v, line:10:1, endln:49:10 |vpiName:asigned |vpiFullName:work@oh_mult.asigned |vpiNet: \_logic_net: (work@oh_mult.bsigned), line:20:18, endln:20:25 |vpiParent: - \_module: work@oh_mult (work@oh_mult), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mult.v, line:10:1, endln:49:10 + \_module_inst: work@oh_mult (work@oh_mult), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mult.v, line:10:1, endln:49:10 |vpiName:bsigned |vpiFullName:work@oh_mult.bsigned |vpiNet: \_logic_net: (work@oh_mult.product), line:22:22, endln:22:29 |vpiParent: - \_module: work@oh_mult (work@oh_mult), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mult.v, line:10:1, endln:49:10 + \_module_inst: work@oh_mult (work@oh_mult), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mult.v, line:10:1, endln:49:10 |vpiName:product |vpiFullName:work@oh_mult.product |vpiNet: \_logic_net: (work@oh_mult.sum), line:23:22, endln:23:25 |vpiParent: - \_module: work@oh_mult (work@oh_mult), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mult.v, line:10:1, endln:49:10 + \_module_inst: work@oh_mult (work@oh_mult), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mult.v, line:10:1, endln:49:10 |vpiName:sum |vpiFullName:work@oh_mult.sum |vpiNet: \_logic_net: (work@oh_mult.carry), line:24:22, endln:24:27 |vpiParent: - \_module: work@oh_mult (work@oh_mult), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mult.v, line:10:1, endln:49:10 + \_module_inst: work@oh_mult (work@oh_mult), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mult.v, line:10:1, endln:49:10 |vpiName:carry |vpiFullName:work@oh_mult.carry |vpiPort: \_port: (a), line:17:22, endln:17:23 |vpiParent: - \_module: work@oh_mult (work@oh_mult), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mult.v, line:10:1, endln:49:10 + \_module_inst: work@oh_mult (work@oh_mult), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mult.v, line:10:1, endln:49:10 |vpiName:a |vpiDirection:1 |vpiLowConn: @@ -30801,7 +30801,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (b), line:18:22, endln:18:23 |vpiParent: - \_module: work@oh_mult (work@oh_mult), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mult.v, line:10:1, endln:49:10 + \_module_inst: work@oh_mult (work@oh_mult), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mult.v, line:10:1, endln:49:10 |vpiName:b |vpiDirection:1 |vpiLowConn: @@ -30841,7 +30841,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (asigned), line:19:18, endln:19:25 |vpiParent: - \_module: work@oh_mult (work@oh_mult), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mult.v, line:10:1, endln:49:10 + \_module_inst: work@oh_mult (work@oh_mult), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mult.v, line:10:1, endln:49:10 |vpiName:asigned |vpiDirection:1 |vpiLowConn: @@ -30853,7 +30853,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (bsigned), line:20:18, endln:20:25 |vpiParent: - \_module: work@oh_mult (work@oh_mult), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mult.v, line:10:1, endln:49:10 + \_module_inst: work@oh_mult (work@oh_mult), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mult.v, line:10:1, endln:49:10 |vpiName:bsigned |vpiDirection:1 |vpiLowConn: @@ -30865,7 +30865,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (product), line:22:22, endln:22:29 |vpiParent: - \_module: work@oh_mult (work@oh_mult), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mult.v, line:10:1, endln:49:10 + \_module_inst: work@oh_mult (work@oh_mult), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mult.v, line:10:1, endln:49:10 |vpiName:product |vpiDirection:2 |vpiLowConn: @@ -30918,7 +30918,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (sum), line:23:22, endln:23:25 |vpiParent: - \_module: work@oh_mult (work@oh_mult), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mult.v, line:10:1, endln:49:10 + \_module_inst: work@oh_mult (work@oh_mult), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mult.v, line:10:1, endln:49:10 |vpiName:sum |vpiDirection:2 |vpiLowConn: @@ -30971,7 +30971,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (carry), line:24:22, endln:24:27 |vpiParent: - \_module: work@oh_mult (work@oh_mult), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mult.v, line:10:1, endln:49:10 + \_module_inst: work@oh_mult (work@oh_mult), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mult.v, line:10:1, endln:49:10 |vpiName:carry |vpiDirection:2 |vpiLowConn: @@ -31022,14 +31022,14 @@ design: (work@oh_fifo_async) |UINT:0 |vpiConstType:9 |uhdmallModules: -\_module: work@oh_mux (work@oh_mux), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux.v, line:8:1, endln:41:10 +\_module_inst: work@oh_mux (work@oh_mux), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux.v, line:8:1, endln:41:10 |vpiParent: \_design: (work@oh_fifo_async) |vpiFullName:work@oh_mux |vpiParameter: \_parameter: (work@oh_mux.N), line:9:15, endln:9:16 |vpiParent: - \_module: work@oh_mux (work@oh_mux), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux.v, line:8:1, endln:41:10 + \_module_inst: work@oh_mux (work@oh_mux), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux.v, line:8:1, endln:41:10 |UINT:32 |vpiTypespec: \_int_typespec: @@ -31038,7 +31038,7 @@ design: (work@oh_fifo_async) |vpiParameter: \_parameter: (work@oh_mux.M), line:10:15, endln:10:16 |vpiParent: - \_module: work@oh_mux (work@oh_mux), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux.v, line:8:1, endln:41:10 + \_module_inst: work@oh_mux (work@oh_mux), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux.v, line:8:1, endln:41:10 |UINT:2 |vpiTypespec: \_int_typespec: @@ -31047,7 +31047,7 @@ design: (work@oh_fifo_async) |vpiParameter: \_parameter: (work@oh_mux.SYN), line:11:15, endln:11:18 |vpiParent: - \_module: work@oh_mux (work@oh_mux), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux.v, line:8:1, endln:41:10 + \_module_inst: work@oh_mux (work@oh_mux), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux.v, line:8:1, endln:41:10 |STRING:TRUE |vpiTypespec: \_string_typespec: @@ -31056,7 +31056,7 @@ design: (work@oh_fifo_async) |vpiParameter: \_parameter: (work@oh_mux.TYPE), line:12:15, endln:12:19 |vpiParent: - \_module: work@oh_mux (work@oh_mux), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux.v, line:8:1, endln:41:10 + \_module_inst: work@oh_mux (work@oh_mux), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux.v, line:8:1, endln:41:10 |STRING:DEFAULT |vpiTypespec: \_string_typespec: @@ -31065,7 +31065,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:9:15, endln:9:23 |vpiParent: - \_module: work@oh_mux (work@oh_mux), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux.v, line:8:1, endln:41:10 + \_module_inst: work@oh_mux (work@oh_mux), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux.v, line:8:1, endln:41:10 |vpiRhs: \_constant: , line:9:21, endln:9:23 |vpiDecompile:32 @@ -31079,7 +31079,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:10:15, endln:10:22 |vpiParent: - \_module: work@oh_mux (work@oh_mux), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux.v, line:8:1, endln:41:10 + \_module_inst: work@oh_mux (work@oh_mux), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux.v, line:8:1, endln:41:10 |vpiRhs: \_constant: , line:10:21, endln:10:22 |vpiDecompile:2 @@ -31093,7 +31093,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:11:15, endln:11:28 |vpiParent: - \_module: work@oh_mux (work@oh_mux), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux.v, line:8:1, endln:41:10 + \_module_inst: work@oh_mux (work@oh_mux), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux.v, line:8:1, endln:41:10 |vpiRhs: \_constant: , line:11:22, endln:11:28 |vpiDecompile:TRUE @@ -31107,7 +31107,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:12:15, endln:12:31 |vpiParent: - \_module: work@oh_mux (work@oh_mux), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux.v, line:8:1, endln:41:10 + \_module_inst: work@oh_mux (work@oh_mux), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux.v, line:8:1, endln:41:10 |vpiRhs: \_constant: , line:12:22, endln:12:31 |vpiDecompile:DEFAULT @@ -31123,25 +31123,25 @@ design: (work@oh_fifo_async) |vpiNet: \_logic_net: (work@oh_mux.sel), line:15:21, endln:15:24 |vpiParent: - \_module: work@oh_mux (work@oh_mux), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux.v, line:8:1, endln:41:10 + \_module_inst: work@oh_mux (work@oh_mux), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux.v, line:8:1, endln:41:10 |vpiName:sel |vpiFullName:work@oh_mux.sel |vpiNet: \_logic_net: (work@oh_mux.in), line:16:21, endln:16:23 |vpiParent: - \_module: work@oh_mux (work@oh_mux), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux.v, line:8:1, endln:41:10 + \_module_inst: work@oh_mux (work@oh_mux), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux.v, line:8:1, endln:41:10 |vpiName:in |vpiFullName:work@oh_mux.in |vpiNet: \_logic_net: (work@oh_mux.out), line:17:21, endln:17:24 |vpiParent: - \_module: work@oh_mux (work@oh_mux), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux.v, line:8:1, endln:41:10 + \_module_inst: work@oh_mux (work@oh_mux), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux.v, line:8:1, endln:41:10 |vpiName:out |vpiFullName:work@oh_mux.out |vpiPort: \_port: (sel), line:15:21, endln:15:24 |vpiParent: - \_module: work@oh_mux (work@oh_mux), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux.v, line:8:1, endln:41:10 + \_module_inst: work@oh_mux (work@oh_mux), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux.v, line:8:1, endln:41:10 |vpiName:sel |vpiDirection:1 |vpiLowConn: @@ -31181,7 +31181,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (in), line:16:21, endln:16:23 |vpiParent: - \_module: work@oh_mux (work@oh_mux), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux.v, line:8:1, endln:41:10 + \_module_inst: work@oh_mux (work@oh_mux), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux.v, line:8:1, endln:41:10 |vpiName:in |vpiDirection:1 |vpiLowConn: @@ -31231,7 +31231,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (out), line:17:21, endln:17:24 |vpiParent: - \_module: work@oh_mux (work@oh_mux), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux.v, line:8:1, endln:41:10 + \_module_inst: work@oh_mux (work@oh_mux), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux.v, line:8:1, endln:41:10 |vpiName:out |vpiDirection:2 |vpiLowConn: @@ -31269,14 +31269,14 @@ design: (work@oh_fifo_async) |UINT:0 |vpiConstType:9 |uhdmallModules: -\_module: work@oh_mux12 (work@oh_mux12), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux12.v, line:8:1, endln:51:10 +\_module_inst: work@oh_mux12 (work@oh_mux12), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux12.v, line:8:1, endln:51:10 |vpiParent: \_design: (work@oh_fifo_async) |vpiFullName:work@oh_mux12 |vpiParameter: \_parameter: (work@oh_mux12.N), line:9:15, endln:9:16 |vpiParent: - \_module: work@oh_mux12 (work@oh_mux12), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux12.v, line:8:1, endln:51:10 + \_module_inst: work@oh_mux12 (work@oh_mux12), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux12.v, line:8:1, endln:51:10 |UINT:1 |vpiTypespec: \_int_typespec: @@ -31285,7 +31285,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:9:15, endln:9:20 |vpiParent: - \_module: work@oh_mux12 (work@oh_mux12), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux12.v, line:8:1, endln:51:10 + \_module_inst: work@oh_mux12 (work@oh_mux12), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux12.v, line:8:1, endln:51:10 |vpiRhs: \_constant: , line:9:19, endln:9:20 |vpiDecompile:1 @@ -31301,157 +31301,157 @@ design: (work@oh_fifo_async) |vpiNet: \_logic_net: (work@oh_mux12.sel11), line:11:16, endln:11:21 |vpiParent: - \_module: work@oh_mux12 (work@oh_mux12), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux12.v, line:8:1, endln:51:10 + \_module_inst: work@oh_mux12 (work@oh_mux12), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux12.v, line:8:1, endln:51:10 |vpiName:sel11 |vpiFullName:work@oh_mux12.sel11 |vpiNet: \_logic_net: (work@oh_mux12.sel10), line:12:16, endln:12:21 |vpiParent: - \_module: work@oh_mux12 (work@oh_mux12), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux12.v, line:8:1, endln:51:10 + \_module_inst: work@oh_mux12 (work@oh_mux12), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux12.v, line:8:1, endln:51:10 |vpiName:sel10 |vpiFullName:work@oh_mux12.sel10 |vpiNet: \_logic_net: (work@oh_mux12.sel9), line:13:16, endln:13:20 |vpiParent: - \_module: work@oh_mux12 (work@oh_mux12), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux12.v, line:8:1, endln:51:10 + \_module_inst: work@oh_mux12 (work@oh_mux12), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux12.v, line:8:1, endln:51:10 |vpiName:sel9 |vpiFullName:work@oh_mux12.sel9 |vpiNet: \_logic_net: (work@oh_mux12.sel8), line:14:16, endln:14:20 |vpiParent: - \_module: work@oh_mux12 (work@oh_mux12), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux12.v, line:8:1, endln:51:10 + \_module_inst: work@oh_mux12 (work@oh_mux12), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux12.v, line:8:1, endln:51:10 |vpiName:sel8 |vpiFullName:work@oh_mux12.sel8 |vpiNet: \_logic_net: (work@oh_mux12.sel7), line:15:16, endln:15:20 |vpiParent: - \_module: work@oh_mux12 (work@oh_mux12), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux12.v, line:8:1, endln:51:10 + \_module_inst: work@oh_mux12 (work@oh_mux12), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux12.v, line:8:1, endln:51:10 |vpiName:sel7 |vpiFullName:work@oh_mux12.sel7 |vpiNet: \_logic_net: (work@oh_mux12.sel6), line:16:16, endln:16:20 |vpiParent: - \_module: work@oh_mux12 (work@oh_mux12), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux12.v, line:8:1, endln:51:10 + \_module_inst: work@oh_mux12 (work@oh_mux12), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux12.v, line:8:1, endln:51:10 |vpiName:sel6 |vpiFullName:work@oh_mux12.sel6 |vpiNet: \_logic_net: (work@oh_mux12.sel5), line:17:16, endln:17:20 |vpiParent: - \_module: work@oh_mux12 (work@oh_mux12), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux12.v, line:8:1, endln:51:10 + \_module_inst: work@oh_mux12 (work@oh_mux12), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux12.v, line:8:1, endln:51:10 |vpiName:sel5 |vpiFullName:work@oh_mux12.sel5 |vpiNet: \_logic_net: (work@oh_mux12.sel4), line:18:16, endln:18:20 |vpiParent: - \_module: work@oh_mux12 (work@oh_mux12), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux12.v, line:8:1, endln:51:10 + \_module_inst: work@oh_mux12 (work@oh_mux12), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux12.v, line:8:1, endln:51:10 |vpiName:sel4 |vpiFullName:work@oh_mux12.sel4 |vpiNet: \_logic_net: (work@oh_mux12.sel3), line:19:16, endln:19:20 |vpiParent: - \_module: work@oh_mux12 (work@oh_mux12), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux12.v, line:8:1, endln:51:10 + \_module_inst: work@oh_mux12 (work@oh_mux12), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux12.v, line:8:1, endln:51:10 |vpiName:sel3 |vpiFullName:work@oh_mux12.sel3 |vpiNet: \_logic_net: (work@oh_mux12.sel2), line:20:16, endln:20:20 |vpiParent: - \_module: work@oh_mux12 (work@oh_mux12), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux12.v, line:8:1, endln:51:10 + \_module_inst: work@oh_mux12 (work@oh_mux12), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux12.v, line:8:1, endln:51:10 |vpiName:sel2 |vpiFullName:work@oh_mux12.sel2 |vpiNet: \_logic_net: (work@oh_mux12.sel1), line:21:16, endln:21:20 |vpiParent: - \_module: work@oh_mux12 (work@oh_mux12), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux12.v, line:8:1, endln:51:10 + \_module_inst: work@oh_mux12 (work@oh_mux12), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux12.v, line:8:1, endln:51:10 |vpiName:sel1 |vpiFullName:work@oh_mux12.sel1 |vpiNet: \_logic_net: (work@oh_mux12.sel0), line:22:16, endln:22:20 |vpiParent: - \_module: work@oh_mux12 (work@oh_mux12), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux12.v, line:8:1, endln:51:10 + \_module_inst: work@oh_mux12 (work@oh_mux12), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux12.v, line:8:1, endln:51:10 |vpiName:sel0 |vpiFullName:work@oh_mux12.sel0 |vpiNet: \_logic_net: (work@oh_mux12.in11), line:23:20, endln:23:24 |vpiParent: - \_module: work@oh_mux12 (work@oh_mux12), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux12.v, line:8:1, endln:51:10 + \_module_inst: work@oh_mux12 (work@oh_mux12), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux12.v, line:8:1, endln:51:10 |vpiName:in11 |vpiFullName:work@oh_mux12.in11 |vpiNet: \_logic_net: (work@oh_mux12.in10), line:24:20, endln:24:24 |vpiParent: - \_module: work@oh_mux12 (work@oh_mux12), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux12.v, line:8:1, endln:51:10 + \_module_inst: work@oh_mux12 (work@oh_mux12), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux12.v, line:8:1, endln:51:10 |vpiName:in10 |vpiFullName:work@oh_mux12.in10 |vpiNet: \_logic_net: (work@oh_mux12.in9), line:25:20, endln:25:23 |vpiParent: - \_module: work@oh_mux12 (work@oh_mux12), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux12.v, line:8:1, endln:51:10 + \_module_inst: work@oh_mux12 (work@oh_mux12), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux12.v, line:8:1, endln:51:10 |vpiName:in9 |vpiFullName:work@oh_mux12.in9 |vpiNet: \_logic_net: (work@oh_mux12.in8), line:26:20, endln:26:23 |vpiParent: - \_module: work@oh_mux12 (work@oh_mux12), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux12.v, line:8:1, endln:51:10 + \_module_inst: work@oh_mux12 (work@oh_mux12), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux12.v, line:8:1, endln:51:10 |vpiName:in8 |vpiFullName:work@oh_mux12.in8 |vpiNet: \_logic_net: (work@oh_mux12.in7), line:27:20, endln:27:23 |vpiParent: - \_module: work@oh_mux12 (work@oh_mux12), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux12.v, line:8:1, endln:51:10 + \_module_inst: work@oh_mux12 (work@oh_mux12), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux12.v, line:8:1, endln:51:10 |vpiName:in7 |vpiFullName:work@oh_mux12.in7 |vpiNet: \_logic_net: (work@oh_mux12.in6), line:28:20, endln:28:23 |vpiParent: - \_module: work@oh_mux12 (work@oh_mux12), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux12.v, line:8:1, endln:51:10 + \_module_inst: work@oh_mux12 (work@oh_mux12), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux12.v, line:8:1, endln:51:10 |vpiName:in6 |vpiFullName:work@oh_mux12.in6 |vpiNet: \_logic_net: (work@oh_mux12.in5), line:29:20, endln:29:23 |vpiParent: - \_module: work@oh_mux12 (work@oh_mux12), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux12.v, line:8:1, endln:51:10 + \_module_inst: work@oh_mux12 (work@oh_mux12), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux12.v, line:8:1, endln:51:10 |vpiName:in5 |vpiFullName:work@oh_mux12.in5 |vpiNet: \_logic_net: (work@oh_mux12.in4), line:30:20, endln:30:23 |vpiParent: - \_module: work@oh_mux12 (work@oh_mux12), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux12.v, line:8:1, endln:51:10 + \_module_inst: work@oh_mux12 (work@oh_mux12), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux12.v, line:8:1, endln:51:10 |vpiName:in4 |vpiFullName:work@oh_mux12.in4 |vpiNet: \_logic_net: (work@oh_mux12.in3), line:31:20, endln:31:23 |vpiParent: - \_module: work@oh_mux12 (work@oh_mux12), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux12.v, line:8:1, endln:51:10 + \_module_inst: work@oh_mux12 (work@oh_mux12), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux12.v, line:8:1, endln:51:10 |vpiName:in3 |vpiFullName:work@oh_mux12.in3 |vpiNet: \_logic_net: (work@oh_mux12.in2), line:32:20, endln:32:23 |vpiParent: - \_module: work@oh_mux12 (work@oh_mux12), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux12.v, line:8:1, endln:51:10 + \_module_inst: work@oh_mux12 (work@oh_mux12), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux12.v, line:8:1, endln:51:10 |vpiName:in2 |vpiFullName:work@oh_mux12.in2 |vpiNet: \_logic_net: (work@oh_mux12.in1), line:33:20, endln:33:23 |vpiParent: - \_module: work@oh_mux12 (work@oh_mux12), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux12.v, line:8:1, endln:51:10 + \_module_inst: work@oh_mux12 (work@oh_mux12), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux12.v, line:8:1, endln:51:10 |vpiName:in1 |vpiFullName:work@oh_mux12.in1 |vpiNet: \_logic_net: (work@oh_mux12.in0), line:34:20, endln:34:23 |vpiParent: - \_module: work@oh_mux12 (work@oh_mux12), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux12.v, line:8:1, endln:51:10 + \_module_inst: work@oh_mux12 (work@oh_mux12), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux12.v, line:8:1, endln:51:10 |vpiName:in0 |vpiFullName:work@oh_mux12.in0 |vpiNet: \_logic_net: (work@oh_mux12.out), line:35:20, endln:35:23 |vpiParent: - \_module: work@oh_mux12 (work@oh_mux12), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux12.v, line:8:1, endln:51:10 + \_module_inst: work@oh_mux12 (work@oh_mux12), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux12.v, line:8:1, endln:51:10 |vpiName:out |vpiFullName:work@oh_mux12.out |vpiPort: \_port: (sel11), line:11:16, endln:11:21 |vpiParent: - \_module: work@oh_mux12 (work@oh_mux12), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux12.v, line:8:1, endln:51:10 + \_module_inst: work@oh_mux12 (work@oh_mux12), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux12.v, line:8:1, endln:51:10 |vpiName:sel11 |vpiDirection:1 |vpiLowConn: @@ -31463,7 +31463,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (sel10), line:12:16, endln:12:21 |vpiParent: - \_module: work@oh_mux12 (work@oh_mux12), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux12.v, line:8:1, endln:51:10 + \_module_inst: work@oh_mux12 (work@oh_mux12), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux12.v, line:8:1, endln:51:10 |vpiName:sel10 |vpiDirection:1 |vpiLowConn: @@ -31475,7 +31475,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (sel9), line:13:16, endln:13:20 |vpiParent: - \_module: work@oh_mux12 (work@oh_mux12), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux12.v, line:8:1, endln:51:10 + \_module_inst: work@oh_mux12 (work@oh_mux12), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux12.v, line:8:1, endln:51:10 |vpiName:sel9 |vpiDirection:1 |vpiLowConn: @@ -31487,7 +31487,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (sel8), line:14:16, endln:14:20 |vpiParent: - \_module: work@oh_mux12 (work@oh_mux12), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux12.v, line:8:1, endln:51:10 + \_module_inst: work@oh_mux12 (work@oh_mux12), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux12.v, line:8:1, endln:51:10 |vpiName:sel8 |vpiDirection:1 |vpiLowConn: @@ -31499,7 +31499,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (sel7), line:15:16, endln:15:20 |vpiParent: - \_module: work@oh_mux12 (work@oh_mux12), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux12.v, line:8:1, endln:51:10 + \_module_inst: work@oh_mux12 (work@oh_mux12), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux12.v, line:8:1, endln:51:10 |vpiName:sel7 |vpiDirection:1 |vpiLowConn: @@ -31511,7 +31511,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (sel6), line:16:16, endln:16:20 |vpiParent: - \_module: work@oh_mux12 (work@oh_mux12), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux12.v, line:8:1, endln:51:10 + \_module_inst: work@oh_mux12 (work@oh_mux12), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux12.v, line:8:1, endln:51:10 |vpiName:sel6 |vpiDirection:1 |vpiLowConn: @@ -31523,7 +31523,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (sel5), line:17:16, endln:17:20 |vpiParent: - \_module: work@oh_mux12 (work@oh_mux12), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux12.v, line:8:1, endln:51:10 + \_module_inst: work@oh_mux12 (work@oh_mux12), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux12.v, line:8:1, endln:51:10 |vpiName:sel5 |vpiDirection:1 |vpiLowConn: @@ -31535,7 +31535,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (sel4), line:18:16, endln:18:20 |vpiParent: - \_module: work@oh_mux12 (work@oh_mux12), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux12.v, line:8:1, endln:51:10 + \_module_inst: work@oh_mux12 (work@oh_mux12), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux12.v, line:8:1, endln:51:10 |vpiName:sel4 |vpiDirection:1 |vpiLowConn: @@ -31547,7 +31547,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (sel3), line:19:16, endln:19:20 |vpiParent: - \_module: work@oh_mux12 (work@oh_mux12), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux12.v, line:8:1, endln:51:10 + \_module_inst: work@oh_mux12 (work@oh_mux12), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux12.v, line:8:1, endln:51:10 |vpiName:sel3 |vpiDirection:1 |vpiLowConn: @@ -31559,7 +31559,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (sel2), line:20:16, endln:20:20 |vpiParent: - \_module: work@oh_mux12 (work@oh_mux12), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux12.v, line:8:1, endln:51:10 + \_module_inst: work@oh_mux12 (work@oh_mux12), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux12.v, line:8:1, endln:51:10 |vpiName:sel2 |vpiDirection:1 |vpiLowConn: @@ -31571,7 +31571,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (sel1), line:21:16, endln:21:20 |vpiParent: - \_module: work@oh_mux12 (work@oh_mux12), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux12.v, line:8:1, endln:51:10 + \_module_inst: work@oh_mux12 (work@oh_mux12), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux12.v, line:8:1, endln:51:10 |vpiName:sel1 |vpiDirection:1 |vpiLowConn: @@ -31583,7 +31583,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (sel0), line:22:16, endln:22:20 |vpiParent: - \_module: work@oh_mux12 (work@oh_mux12), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux12.v, line:8:1, endln:51:10 + \_module_inst: work@oh_mux12 (work@oh_mux12), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux12.v, line:8:1, endln:51:10 |vpiName:sel0 |vpiDirection:1 |vpiLowConn: @@ -31595,7 +31595,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (in11), line:23:20, endln:23:24 |vpiParent: - \_module: work@oh_mux12 (work@oh_mux12), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux12.v, line:8:1, endln:51:10 + \_module_inst: work@oh_mux12 (work@oh_mux12), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux12.v, line:8:1, endln:51:10 |vpiName:in11 |vpiDirection:1 |vpiLowConn: @@ -31635,7 +31635,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (in10), line:24:20, endln:24:24 |vpiParent: - \_module: work@oh_mux12 (work@oh_mux12), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux12.v, line:8:1, endln:51:10 + \_module_inst: work@oh_mux12 (work@oh_mux12), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux12.v, line:8:1, endln:51:10 |vpiName:in10 |vpiDirection:1 |vpiLowConn: @@ -31675,7 +31675,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (in9), line:25:20, endln:25:23 |vpiParent: - \_module: work@oh_mux12 (work@oh_mux12), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux12.v, line:8:1, endln:51:10 + \_module_inst: work@oh_mux12 (work@oh_mux12), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux12.v, line:8:1, endln:51:10 |vpiName:in9 |vpiDirection:1 |vpiLowConn: @@ -31715,7 +31715,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (in8), line:26:20, endln:26:23 |vpiParent: - \_module: work@oh_mux12 (work@oh_mux12), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux12.v, line:8:1, endln:51:10 + \_module_inst: work@oh_mux12 (work@oh_mux12), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux12.v, line:8:1, endln:51:10 |vpiName:in8 |vpiDirection:1 |vpiLowConn: @@ -31755,7 +31755,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (in7), line:27:20, endln:27:23 |vpiParent: - \_module: work@oh_mux12 (work@oh_mux12), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux12.v, line:8:1, endln:51:10 + \_module_inst: work@oh_mux12 (work@oh_mux12), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux12.v, line:8:1, endln:51:10 |vpiName:in7 |vpiDirection:1 |vpiLowConn: @@ -31795,7 +31795,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (in6), line:28:20, endln:28:23 |vpiParent: - \_module: work@oh_mux12 (work@oh_mux12), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux12.v, line:8:1, endln:51:10 + \_module_inst: work@oh_mux12 (work@oh_mux12), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux12.v, line:8:1, endln:51:10 |vpiName:in6 |vpiDirection:1 |vpiLowConn: @@ -31835,7 +31835,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (in5), line:29:20, endln:29:23 |vpiParent: - \_module: work@oh_mux12 (work@oh_mux12), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux12.v, line:8:1, endln:51:10 + \_module_inst: work@oh_mux12 (work@oh_mux12), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux12.v, line:8:1, endln:51:10 |vpiName:in5 |vpiDirection:1 |vpiLowConn: @@ -31875,7 +31875,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (in4), line:30:20, endln:30:23 |vpiParent: - \_module: work@oh_mux12 (work@oh_mux12), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux12.v, line:8:1, endln:51:10 + \_module_inst: work@oh_mux12 (work@oh_mux12), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux12.v, line:8:1, endln:51:10 |vpiName:in4 |vpiDirection:1 |vpiLowConn: @@ -31915,7 +31915,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (in3), line:31:20, endln:31:23 |vpiParent: - \_module: work@oh_mux12 (work@oh_mux12), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux12.v, line:8:1, endln:51:10 + \_module_inst: work@oh_mux12 (work@oh_mux12), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux12.v, line:8:1, endln:51:10 |vpiName:in3 |vpiDirection:1 |vpiLowConn: @@ -31955,7 +31955,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (in2), line:32:20, endln:32:23 |vpiParent: - \_module: work@oh_mux12 (work@oh_mux12), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux12.v, line:8:1, endln:51:10 + \_module_inst: work@oh_mux12 (work@oh_mux12), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux12.v, line:8:1, endln:51:10 |vpiName:in2 |vpiDirection:1 |vpiLowConn: @@ -31995,7 +31995,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (in1), line:33:20, endln:33:23 |vpiParent: - \_module: work@oh_mux12 (work@oh_mux12), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux12.v, line:8:1, endln:51:10 + \_module_inst: work@oh_mux12 (work@oh_mux12), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux12.v, line:8:1, endln:51:10 |vpiName:in1 |vpiDirection:1 |vpiLowConn: @@ -32035,7 +32035,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (in0), line:34:20, endln:34:23 |vpiParent: - \_module: work@oh_mux12 (work@oh_mux12), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux12.v, line:8:1, endln:51:10 + \_module_inst: work@oh_mux12 (work@oh_mux12), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux12.v, line:8:1, endln:51:10 |vpiName:in0 |vpiDirection:1 |vpiLowConn: @@ -32075,7 +32075,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (out), line:35:20, endln:35:23 |vpiParent: - \_module: work@oh_mux12 (work@oh_mux12), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux12.v, line:8:1, endln:51:10 + \_module_inst: work@oh_mux12 (work@oh_mux12), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux12.v, line:8:1, endln:51:10 |vpiName:out |vpiDirection:2 |vpiLowConn: @@ -32115,7 +32115,7 @@ design: (work@oh_fifo_async) |vpiContAssign: \_cont_assign: , line:38:11, endln:49:32 |vpiParent: - \_module: work@oh_mux12 (work@oh_mux12), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux12.v, line:8:1, endln:51:10 + \_module_inst: work@oh_mux12 (work@oh_mux12), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux12.v, line:8:1, endln:51:10 |vpiRhs: \_operation: , line:38:25, endln:49:31 |vpiParent: @@ -32945,14 +32945,14 @@ design: (work@oh_fifo_async) |UINT:0 |vpiConstType:9 |uhdmallModules: -\_module: work@oh_mux2 (work@oh_mux2), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux2.v, line:8:1, endln:21:10 +\_module_inst: work@oh_mux2 (work@oh_mux2), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux2.v, line:8:1, endln:21:10 |vpiParent: \_design: (work@oh_fifo_async) |vpiFullName:work@oh_mux2 |vpiParameter: \_parameter: (work@oh_mux2.N), line:8:28, endln:8:29 |vpiParent: - \_module: work@oh_mux2 (work@oh_mux2), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux2.v, line:8:1, endln:21:10 + \_module_inst: work@oh_mux2 (work@oh_mux2), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux2.v, line:8:1, endln:21:10 |UINT:1 |vpiTypespec: \_int_typespec: @@ -32961,7 +32961,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:8:28, endln:8:33 |vpiParent: - \_module: work@oh_mux2 (work@oh_mux2), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux2.v, line:8:1, endln:21:10 + \_module_inst: work@oh_mux2 (work@oh_mux2), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux2.v, line:8:1, endln:21:10 |vpiRhs: \_constant: , line:8:32, endln:8:33 |vpiDecompile:1 @@ -32977,37 +32977,37 @@ design: (work@oh_fifo_async) |vpiNet: \_logic_net: (work@oh_mux2.sel1), line:10:16, endln:10:20 |vpiParent: - \_module: work@oh_mux2 (work@oh_mux2), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux2.v, line:8:1, endln:21:10 + \_module_inst: work@oh_mux2 (work@oh_mux2), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux2.v, line:8:1, endln:21:10 |vpiName:sel1 |vpiFullName:work@oh_mux2.sel1 |vpiNet: \_logic_net: (work@oh_mux2.sel0), line:11:16, endln:11:20 |vpiParent: - \_module: work@oh_mux2 (work@oh_mux2), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux2.v, line:8:1, endln:21:10 + \_module_inst: work@oh_mux2 (work@oh_mux2), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux2.v, line:8:1, endln:21:10 |vpiName:sel0 |vpiFullName:work@oh_mux2.sel0 |vpiNet: \_logic_net: (work@oh_mux2.in1), line:12:20, endln:12:23 |vpiParent: - \_module: work@oh_mux2 (work@oh_mux2), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux2.v, line:8:1, endln:21:10 + \_module_inst: work@oh_mux2 (work@oh_mux2), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux2.v, line:8:1, endln:21:10 |vpiName:in1 |vpiFullName:work@oh_mux2.in1 |vpiNet: \_logic_net: (work@oh_mux2.in0), line:13:20, endln:13:23 |vpiParent: - \_module: work@oh_mux2 (work@oh_mux2), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux2.v, line:8:1, endln:21:10 + \_module_inst: work@oh_mux2 (work@oh_mux2), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux2.v, line:8:1, endln:21:10 |vpiName:in0 |vpiFullName:work@oh_mux2.in0 |vpiNet: \_logic_net: (work@oh_mux2.out), line:14:20, endln:14:23 |vpiParent: - \_module: work@oh_mux2 (work@oh_mux2), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux2.v, line:8:1, endln:21:10 + \_module_inst: work@oh_mux2 (work@oh_mux2), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux2.v, line:8:1, endln:21:10 |vpiName:out |vpiFullName:work@oh_mux2.out |vpiPort: \_port: (sel1), line:10:16, endln:10:20 |vpiParent: - \_module: work@oh_mux2 (work@oh_mux2), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux2.v, line:8:1, endln:21:10 + \_module_inst: work@oh_mux2 (work@oh_mux2), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux2.v, line:8:1, endln:21:10 |vpiName:sel1 |vpiDirection:1 |vpiLowConn: @@ -33019,7 +33019,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (sel0), line:11:16, endln:11:20 |vpiParent: - \_module: work@oh_mux2 (work@oh_mux2), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux2.v, line:8:1, endln:21:10 + \_module_inst: work@oh_mux2 (work@oh_mux2), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux2.v, line:8:1, endln:21:10 |vpiName:sel0 |vpiDirection:1 |vpiLowConn: @@ -33031,7 +33031,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (in1), line:12:20, endln:12:23 |vpiParent: - \_module: work@oh_mux2 (work@oh_mux2), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux2.v, line:8:1, endln:21:10 + \_module_inst: work@oh_mux2 (work@oh_mux2), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux2.v, line:8:1, endln:21:10 |vpiName:in1 |vpiDirection:1 |vpiLowConn: @@ -33071,7 +33071,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (in0), line:13:20, endln:13:23 |vpiParent: - \_module: work@oh_mux2 (work@oh_mux2), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux2.v, line:8:1, endln:21:10 + \_module_inst: work@oh_mux2 (work@oh_mux2), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux2.v, line:8:1, endln:21:10 |vpiName:in0 |vpiDirection:1 |vpiLowConn: @@ -33111,7 +33111,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (out), line:14:20, endln:14:23 |vpiParent: - \_module: work@oh_mux2 (work@oh_mux2), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux2.v, line:8:1, endln:21:10 + \_module_inst: work@oh_mux2 (work@oh_mux2), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux2.v, line:8:1, endln:21:10 |vpiName:out |vpiDirection:2 |vpiLowConn: @@ -33151,7 +33151,7 @@ design: (work@oh_fifo_async) |vpiContAssign: \_cont_assign: , line:17:11, endln:18:30 |vpiParent: - \_module: work@oh_mux2 (work@oh_mux2), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux2.v, line:8:1, endln:21:10 + \_module_inst: work@oh_mux2 (work@oh_mux2), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux2.v, line:8:1, endln:21:10 |vpiRhs: \_operation: , line:17:25, endln:18:29 |vpiParent: @@ -33311,14 +33311,14 @@ design: (work@oh_fifo_async) |UINT:0 |vpiConstType:9 |uhdmallModules: -\_module: work@oh_mux3 (work@oh_mux3), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux3.v, line:8:1, endln:23:10 +\_module_inst: work@oh_mux3 (work@oh_mux3), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux3.v, line:8:1, endln:23:10 |vpiParent: \_design: (work@oh_fifo_async) |vpiFullName:work@oh_mux3 |vpiParameter: \_parameter: (work@oh_mux3.N), line:8:28, endln:8:29 |vpiParent: - \_module: work@oh_mux3 (work@oh_mux3), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux3.v, line:8:1, endln:23:10 + \_module_inst: work@oh_mux3 (work@oh_mux3), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux3.v, line:8:1, endln:23:10 |UINT:1 |vpiTypespec: \_int_typespec: @@ -33327,7 +33327,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:8:28, endln:8:33 |vpiParent: - \_module: work@oh_mux3 (work@oh_mux3), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux3.v, line:8:1, endln:23:10 + \_module_inst: work@oh_mux3 (work@oh_mux3), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux3.v, line:8:1, endln:23:10 |vpiRhs: \_constant: , line:8:32, endln:8:33 |vpiDecompile:1 @@ -33343,49 +33343,49 @@ design: (work@oh_fifo_async) |vpiNet: \_logic_net: (work@oh_mux3.sel2), line:10:16, endln:10:20 |vpiParent: - \_module: work@oh_mux3 (work@oh_mux3), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux3.v, line:8:1, endln:23:10 + \_module_inst: work@oh_mux3 (work@oh_mux3), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux3.v, line:8:1, endln:23:10 |vpiName:sel2 |vpiFullName:work@oh_mux3.sel2 |vpiNet: \_logic_net: (work@oh_mux3.sel1), line:11:16, endln:11:20 |vpiParent: - \_module: work@oh_mux3 (work@oh_mux3), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux3.v, line:8:1, endln:23:10 + \_module_inst: work@oh_mux3 (work@oh_mux3), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux3.v, line:8:1, endln:23:10 |vpiName:sel1 |vpiFullName:work@oh_mux3.sel1 |vpiNet: \_logic_net: (work@oh_mux3.sel0), line:12:16, endln:12:20 |vpiParent: - \_module: work@oh_mux3 (work@oh_mux3), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux3.v, line:8:1, endln:23:10 + \_module_inst: work@oh_mux3 (work@oh_mux3), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux3.v, line:8:1, endln:23:10 |vpiName:sel0 |vpiFullName:work@oh_mux3.sel0 |vpiNet: \_logic_net: (work@oh_mux3.in2), line:13:20, endln:13:23 |vpiParent: - \_module: work@oh_mux3 (work@oh_mux3), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux3.v, line:8:1, endln:23:10 + \_module_inst: work@oh_mux3 (work@oh_mux3), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux3.v, line:8:1, endln:23:10 |vpiName:in2 |vpiFullName:work@oh_mux3.in2 |vpiNet: \_logic_net: (work@oh_mux3.in1), line:14:20, endln:14:23 |vpiParent: - \_module: work@oh_mux3 (work@oh_mux3), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux3.v, line:8:1, endln:23:10 + \_module_inst: work@oh_mux3 (work@oh_mux3), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux3.v, line:8:1, endln:23:10 |vpiName:in1 |vpiFullName:work@oh_mux3.in1 |vpiNet: \_logic_net: (work@oh_mux3.in0), line:15:20, endln:15:23 |vpiParent: - \_module: work@oh_mux3 (work@oh_mux3), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux3.v, line:8:1, endln:23:10 + \_module_inst: work@oh_mux3 (work@oh_mux3), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux3.v, line:8:1, endln:23:10 |vpiName:in0 |vpiFullName:work@oh_mux3.in0 |vpiNet: \_logic_net: (work@oh_mux3.out), line:16:20, endln:16:23 |vpiParent: - \_module: work@oh_mux3 (work@oh_mux3), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux3.v, line:8:1, endln:23:10 + \_module_inst: work@oh_mux3 (work@oh_mux3), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux3.v, line:8:1, endln:23:10 |vpiName:out |vpiFullName:work@oh_mux3.out |vpiPort: \_port: (sel2), line:10:16, endln:10:20 |vpiParent: - \_module: work@oh_mux3 (work@oh_mux3), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux3.v, line:8:1, endln:23:10 + \_module_inst: work@oh_mux3 (work@oh_mux3), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux3.v, line:8:1, endln:23:10 |vpiName:sel2 |vpiDirection:1 |vpiLowConn: @@ -33397,7 +33397,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (sel1), line:11:16, endln:11:20 |vpiParent: - \_module: work@oh_mux3 (work@oh_mux3), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux3.v, line:8:1, endln:23:10 + \_module_inst: work@oh_mux3 (work@oh_mux3), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux3.v, line:8:1, endln:23:10 |vpiName:sel1 |vpiDirection:1 |vpiLowConn: @@ -33409,7 +33409,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (sel0), line:12:16, endln:12:20 |vpiParent: - \_module: work@oh_mux3 (work@oh_mux3), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux3.v, line:8:1, endln:23:10 + \_module_inst: work@oh_mux3 (work@oh_mux3), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux3.v, line:8:1, endln:23:10 |vpiName:sel0 |vpiDirection:1 |vpiLowConn: @@ -33421,7 +33421,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (in2), line:13:20, endln:13:23 |vpiParent: - \_module: work@oh_mux3 (work@oh_mux3), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux3.v, line:8:1, endln:23:10 + \_module_inst: work@oh_mux3 (work@oh_mux3), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux3.v, line:8:1, endln:23:10 |vpiName:in2 |vpiDirection:1 |vpiLowConn: @@ -33461,7 +33461,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (in1), line:14:20, endln:14:23 |vpiParent: - \_module: work@oh_mux3 (work@oh_mux3), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux3.v, line:8:1, endln:23:10 + \_module_inst: work@oh_mux3 (work@oh_mux3), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux3.v, line:8:1, endln:23:10 |vpiName:in1 |vpiDirection:1 |vpiLowConn: @@ -33501,7 +33501,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (in0), line:15:20, endln:15:23 |vpiParent: - \_module: work@oh_mux3 (work@oh_mux3), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux3.v, line:8:1, endln:23:10 + \_module_inst: work@oh_mux3 (work@oh_mux3), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux3.v, line:8:1, endln:23:10 |vpiName:in0 |vpiDirection:1 |vpiLowConn: @@ -33541,7 +33541,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (out), line:16:20, endln:16:23 |vpiParent: - \_module: work@oh_mux3 (work@oh_mux3), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux3.v, line:8:1, endln:23:10 + \_module_inst: work@oh_mux3 (work@oh_mux3), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux3.v, line:8:1, endln:23:10 |vpiName:out |vpiDirection:2 |vpiLowConn: @@ -33581,7 +33581,7 @@ design: (work@oh_fifo_async) |vpiContAssign: \_cont_assign: , line:19:11, endln:21:30 |vpiParent: - \_module: work@oh_mux3 (work@oh_mux3), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux3.v, line:8:1, endln:23:10 + \_module_inst: work@oh_mux3 (work@oh_mux3), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux3.v, line:8:1, endln:23:10 |vpiRhs: \_operation: , line:19:25, endln:21:29 |vpiParent: @@ -33808,14 +33808,14 @@ design: (work@oh_fifo_async) |UINT:0 |vpiConstType:9 |uhdmallModules: -\_module: work@oh_mux4 (work@oh_mux4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux4.v, line:8:1, endln:36:10 +\_module_inst: work@oh_mux4 (work@oh_mux4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux4.v, line:8:1, endln:36:10 |vpiParent: \_design: (work@oh_fifo_async) |vpiFullName:work@oh_mux4 |vpiParameter: \_parameter: (work@oh_mux4.N), line:8:28, endln:8:29 |vpiParent: - \_module: work@oh_mux4 (work@oh_mux4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux4.v, line:8:1, endln:36:10 + \_module_inst: work@oh_mux4 (work@oh_mux4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux4.v, line:8:1, endln:36:10 |UINT:1 |vpiTypespec: \_int_typespec: @@ -33824,7 +33824,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:8:28, endln:8:33 |vpiParent: - \_module: work@oh_mux4 (work@oh_mux4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux4.v, line:8:1, endln:36:10 + \_module_inst: work@oh_mux4 (work@oh_mux4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux4.v, line:8:1, endln:36:10 |vpiRhs: \_constant: , line:8:32, endln:8:33 |vpiDecompile:1 @@ -33840,61 +33840,61 @@ design: (work@oh_fifo_async) |vpiNet: \_logic_net: (work@oh_mux4.sel3), line:10:16, endln:10:20 |vpiParent: - \_module: work@oh_mux4 (work@oh_mux4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux4.v, line:8:1, endln:36:10 + \_module_inst: work@oh_mux4 (work@oh_mux4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux4.v, line:8:1, endln:36:10 |vpiName:sel3 |vpiFullName:work@oh_mux4.sel3 |vpiNet: \_logic_net: (work@oh_mux4.sel2), line:11:16, endln:11:20 |vpiParent: - \_module: work@oh_mux4 (work@oh_mux4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux4.v, line:8:1, endln:36:10 + \_module_inst: work@oh_mux4 (work@oh_mux4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux4.v, line:8:1, endln:36:10 |vpiName:sel2 |vpiFullName:work@oh_mux4.sel2 |vpiNet: \_logic_net: (work@oh_mux4.sel1), line:12:16, endln:12:20 |vpiParent: - \_module: work@oh_mux4 (work@oh_mux4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux4.v, line:8:1, endln:36:10 + \_module_inst: work@oh_mux4 (work@oh_mux4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux4.v, line:8:1, endln:36:10 |vpiName:sel1 |vpiFullName:work@oh_mux4.sel1 |vpiNet: \_logic_net: (work@oh_mux4.sel0), line:13:16, endln:13:20 |vpiParent: - \_module: work@oh_mux4 (work@oh_mux4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux4.v, line:8:1, endln:36:10 + \_module_inst: work@oh_mux4 (work@oh_mux4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux4.v, line:8:1, endln:36:10 |vpiName:sel0 |vpiFullName:work@oh_mux4.sel0 |vpiNet: \_logic_net: (work@oh_mux4.in3), line:14:20, endln:14:23 |vpiParent: - \_module: work@oh_mux4 (work@oh_mux4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux4.v, line:8:1, endln:36:10 + \_module_inst: work@oh_mux4 (work@oh_mux4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux4.v, line:8:1, endln:36:10 |vpiName:in3 |vpiFullName:work@oh_mux4.in3 |vpiNet: \_logic_net: (work@oh_mux4.in2), line:15:20, endln:15:23 |vpiParent: - \_module: work@oh_mux4 (work@oh_mux4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux4.v, line:8:1, endln:36:10 + \_module_inst: work@oh_mux4 (work@oh_mux4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux4.v, line:8:1, endln:36:10 |vpiName:in2 |vpiFullName:work@oh_mux4.in2 |vpiNet: \_logic_net: (work@oh_mux4.in1), line:16:20, endln:16:23 |vpiParent: - \_module: work@oh_mux4 (work@oh_mux4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux4.v, line:8:1, endln:36:10 + \_module_inst: work@oh_mux4 (work@oh_mux4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux4.v, line:8:1, endln:36:10 |vpiName:in1 |vpiFullName:work@oh_mux4.in1 |vpiNet: \_logic_net: (work@oh_mux4.in0), line:17:20, endln:17:23 |vpiParent: - \_module: work@oh_mux4 (work@oh_mux4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux4.v, line:8:1, endln:36:10 + \_module_inst: work@oh_mux4 (work@oh_mux4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux4.v, line:8:1, endln:36:10 |vpiName:in0 |vpiFullName:work@oh_mux4.in0 |vpiNet: \_logic_net: (work@oh_mux4.out), line:18:20, endln:18:23 |vpiParent: - \_module: work@oh_mux4 (work@oh_mux4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux4.v, line:8:1, endln:36:10 + \_module_inst: work@oh_mux4 (work@oh_mux4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux4.v, line:8:1, endln:36:10 |vpiName:out |vpiFullName:work@oh_mux4.out |vpiPort: \_port: (sel3), line:10:16, endln:10:20 |vpiParent: - \_module: work@oh_mux4 (work@oh_mux4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux4.v, line:8:1, endln:36:10 + \_module_inst: work@oh_mux4 (work@oh_mux4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux4.v, line:8:1, endln:36:10 |vpiName:sel3 |vpiDirection:1 |vpiLowConn: @@ -33906,7 +33906,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (sel2), line:11:16, endln:11:20 |vpiParent: - \_module: work@oh_mux4 (work@oh_mux4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux4.v, line:8:1, endln:36:10 + \_module_inst: work@oh_mux4 (work@oh_mux4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux4.v, line:8:1, endln:36:10 |vpiName:sel2 |vpiDirection:1 |vpiLowConn: @@ -33918,7 +33918,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (sel1), line:12:16, endln:12:20 |vpiParent: - \_module: work@oh_mux4 (work@oh_mux4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux4.v, line:8:1, endln:36:10 + \_module_inst: work@oh_mux4 (work@oh_mux4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux4.v, line:8:1, endln:36:10 |vpiName:sel1 |vpiDirection:1 |vpiLowConn: @@ -33930,7 +33930,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (sel0), line:13:16, endln:13:20 |vpiParent: - \_module: work@oh_mux4 (work@oh_mux4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux4.v, line:8:1, endln:36:10 + \_module_inst: work@oh_mux4 (work@oh_mux4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux4.v, line:8:1, endln:36:10 |vpiName:sel0 |vpiDirection:1 |vpiLowConn: @@ -33942,7 +33942,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (in3), line:14:20, endln:14:23 |vpiParent: - \_module: work@oh_mux4 (work@oh_mux4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux4.v, line:8:1, endln:36:10 + \_module_inst: work@oh_mux4 (work@oh_mux4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux4.v, line:8:1, endln:36:10 |vpiName:in3 |vpiDirection:1 |vpiLowConn: @@ -33982,7 +33982,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (in2), line:15:20, endln:15:23 |vpiParent: - \_module: work@oh_mux4 (work@oh_mux4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux4.v, line:8:1, endln:36:10 + \_module_inst: work@oh_mux4 (work@oh_mux4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux4.v, line:8:1, endln:36:10 |vpiName:in2 |vpiDirection:1 |vpiLowConn: @@ -34022,7 +34022,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (in1), line:16:20, endln:16:23 |vpiParent: - \_module: work@oh_mux4 (work@oh_mux4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux4.v, line:8:1, endln:36:10 + \_module_inst: work@oh_mux4 (work@oh_mux4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux4.v, line:8:1, endln:36:10 |vpiName:in1 |vpiDirection:1 |vpiLowConn: @@ -34062,7 +34062,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (in0), line:17:20, endln:17:23 |vpiParent: - \_module: work@oh_mux4 (work@oh_mux4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux4.v, line:8:1, endln:36:10 + \_module_inst: work@oh_mux4 (work@oh_mux4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux4.v, line:8:1, endln:36:10 |vpiName:in0 |vpiDirection:1 |vpiLowConn: @@ -34102,7 +34102,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (out), line:18:20, endln:18:23 |vpiParent: - \_module: work@oh_mux4 (work@oh_mux4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux4.v, line:8:1, endln:36:10 + \_module_inst: work@oh_mux4 (work@oh_mux4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux4.v, line:8:1, endln:36:10 |vpiName:out |vpiDirection:2 |vpiLowConn: @@ -34142,7 +34142,7 @@ design: (work@oh_fifo_async) |vpiContAssign: \_cont_assign: , line:21:11, endln:24:30 |vpiParent: - \_module: work@oh_mux4 (work@oh_mux4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux4.v, line:8:1, endln:36:10 + \_module_inst: work@oh_mux4 (work@oh_mux4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux4.v, line:8:1, endln:36:10 |vpiRhs: \_operation: , line:21:25, endln:24:29 |vpiParent: @@ -34436,14 +34436,14 @@ design: (work@oh_fifo_async) |UINT:0 |vpiConstType:9 |uhdmallModules: -\_module: work@oh_mux5 (work@oh_mux5), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux5.v, line:8:1, endln:29:10 +\_module_inst: work@oh_mux5 (work@oh_mux5), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux5.v, line:8:1, endln:29:10 |vpiParent: \_design: (work@oh_fifo_async) |vpiFullName:work@oh_mux5 |vpiParameter: \_parameter: (work@oh_mux5.N), line:8:28, endln:8:29 |vpiParent: - \_module: work@oh_mux5 (work@oh_mux5), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux5.v, line:8:1, endln:29:10 + \_module_inst: work@oh_mux5 (work@oh_mux5), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux5.v, line:8:1, endln:29:10 |UINT:1 |vpiTypespec: \_int_typespec: @@ -34452,7 +34452,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:8:28, endln:8:33 |vpiParent: - \_module: work@oh_mux5 (work@oh_mux5), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux5.v, line:8:1, endln:29:10 + \_module_inst: work@oh_mux5 (work@oh_mux5), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux5.v, line:8:1, endln:29:10 |vpiRhs: \_constant: , line:8:32, endln:8:33 |vpiDecompile:1 @@ -34468,73 +34468,73 @@ design: (work@oh_fifo_async) |vpiNet: \_logic_net: (work@oh_mux5.sel4), line:10:16, endln:10:20 |vpiParent: - \_module: work@oh_mux5 (work@oh_mux5), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux5.v, line:8:1, endln:29:10 + \_module_inst: work@oh_mux5 (work@oh_mux5), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux5.v, line:8:1, endln:29:10 |vpiName:sel4 |vpiFullName:work@oh_mux5.sel4 |vpiNet: \_logic_net: (work@oh_mux5.sel3), line:11:16, endln:11:20 |vpiParent: - \_module: work@oh_mux5 (work@oh_mux5), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux5.v, line:8:1, endln:29:10 + \_module_inst: work@oh_mux5 (work@oh_mux5), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux5.v, line:8:1, endln:29:10 |vpiName:sel3 |vpiFullName:work@oh_mux5.sel3 |vpiNet: \_logic_net: (work@oh_mux5.sel2), line:12:16, endln:12:20 |vpiParent: - \_module: work@oh_mux5 (work@oh_mux5), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux5.v, line:8:1, endln:29:10 + \_module_inst: work@oh_mux5 (work@oh_mux5), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux5.v, line:8:1, endln:29:10 |vpiName:sel2 |vpiFullName:work@oh_mux5.sel2 |vpiNet: \_logic_net: (work@oh_mux5.sel1), line:13:16, endln:13:20 |vpiParent: - \_module: work@oh_mux5 (work@oh_mux5), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux5.v, line:8:1, endln:29:10 + \_module_inst: work@oh_mux5 (work@oh_mux5), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux5.v, line:8:1, endln:29:10 |vpiName:sel1 |vpiFullName:work@oh_mux5.sel1 |vpiNet: \_logic_net: (work@oh_mux5.sel0), line:14:16, endln:14:20 |vpiParent: - \_module: work@oh_mux5 (work@oh_mux5), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux5.v, line:8:1, endln:29:10 + \_module_inst: work@oh_mux5 (work@oh_mux5), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux5.v, line:8:1, endln:29:10 |vpiName:sel0 |vpiFullName:work@oh_mux5.sel0 |vpiNet: \_logic_net: (work@oh_mux5.in4), line:15:20, endln:15:23 |vpiParent: - \_module: work@oh_mux5 (work@oh_mux5), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux5.v, line:8:1, endln:29:10 + \_module_inst: work@oh_mux5 (work@oh_mux5), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux5.v, line:8:1, endln:29:10 |vpiName:in4 |vpiFullName:work@oh_mux5.in4 |vpiNet: \_logic_net: (work@oh_mux5.in3), line:16:20, endln:16:23 |vpiParent: - \_module: work@oh_mux5 (work@oh_mux5), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux5.v, line:8:1, endln:29:10 + \_module_inst: work@oh_mux5 (work@oh_mux5), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux5.v, line:8:1, endln:29:10 |vpiName:in3 |vpiFullName:work@oh_mux5.in3 |vpiNet: \_logic_net: (work@oh_mux5.in2), line:17:20, endln:17:23 |vpiParent: - \_module: work@oh_mux5 (work@oh_mux5), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux5.v, line:8:1, endln:29:10 + \_module_inst: work@oh_mux5 (work@oh_mux5), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux5.v, line:8:1, endln:29:10 |vpiName:in2 |vpiFullName:work@oh_mux5.in2 |vpiNet: \_logic_net: (work@oh_mux5.in1), line:18:20, endln:18:23 |vpiParent: - \_module: work@oh_mux5 (work@oh_mux5), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux5.v, line:8:1, endln:29:10 + \_module_inst: work@oh_mux5 (work@oh_mux5), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux5.v, line:8:1, endln:29:10 |vpiName:in1 |vpiFullName:work@oh_mux5.in1 |vpiNet: \_logic_net: (work@oh_mux5.in0), line:19:20, endln:19:23 |vpiParent: - \_module: work@oh_mux5 (work@oh_mux5), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux5.v, line:8:1, endln:29:10 + \_module_inst: work@oh_mux5 (work@oh_mux5), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux5.v, line:8:1, endln:29:10 |vpiName:in0 |vpiFullName:work@oh_mux5.in0 |vpiNet: \_logic_net: (work@oh_mux5.out), line:20:20, endln:20:23 |vpiParent: - \_module: work@oh_mux5 (work@oh_mux5), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux5.v, line:8:1, endln:29:10 + \_module_inst: work@oh_mux5 (work@oh_mux5), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux5.v, line:8:1, endln:29:10 |vpiName:out |vpiFullName:work@oh_mux5.out |vpiPort: \_port: (sel4), line:10:16, endln:10:20 |vpiParent: - \_module: work@oh_mux5 (work@oh_mux5), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux5.v, line:8:1, endln:29:10 + \_module_inst: work@oh_mux5 (work@oh_mux5), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux5.v, line:8:1, endln:29:10 |vpiName:sel4 |vpiDirection:1 |vpiLowConn: @@ -34546,7 +34546,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (sel3), line:11:16, endln:11:20 |vpiParent: - \_module: work@oh_mux5 (work@oh_mux5), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux5.v, line:8:1, endln:29:10 + \_module_inst: work@oh_mux5 (work@oh_mux5), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux5.v, line:8:1, endln:29:10 |vpiName:sel3 |vpiDirection:1 |vpiLowConn: @@ -34558,7 +34558,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (sel2), line:12:16, endln:12:20 |vpiParent: - \_module: work@oh_mux5 (work@oh_mux5), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux5.v, line:8:1, endln:29:10 + \_module_inst: work@oh_mux5 (work@oh_mux5), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux5.v, line:8:1, endln:29:10 |vpiName:sel2 |vpiDirection:1 |vpiLowConn: @@ -34570,7 +34570,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (sel1), line:13:16, endln:13:20 |vpiParent: - \_module: work@oh_mux5 (work@oh_mux5), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux5.v, line:8:1, endln:29:10 + \_module_inst: work@oh_mux5 (work@oh_mux5), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux5.v, line:8:1, endln:29:10 |vpiName:sel1 |vpiDirection:1 |vpiLowConn: @@ -34582,7 +34582,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (sel0), line:14:16, endln:14:20 |vpiParent: - \_module: work@oh_mux5 (work@oh_mux5), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux5.v, line:8:1, endln:29:10 + \_module_inst: work@oh_mux5 (work@oh_mux5), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux5.v, line:8:1, endln:29:10 |vpiName:sel0 |vpiDirection:1 |vpiLowConn: @@ -34594,7 +34594,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (in4), line:15:20, endln:15:23 |vpiParent: - \_module: work@oh_mux5 (work@oh_mux5), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux5.v, line:8:1, endln:29:10 + \_module_inst: work@oh_mux5 (work@oh_mux5), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux5.v, line:8:1, endln:29:10 |vpiName:in4 |vpiDirection:1 |vpiLowConn: @@ -34634,7 +34634,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (in3), line:16:20, endln:16:23 |vpiParent: - \_module: work@oh_mux5 (work@oh_mux5), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux5.v, line:8:1, endln:29:10 + \_module_inst: work@oh_mux5 (work@oh_mux5), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux5.v, line:8:1, endln:29:10 |vpiName:in3 |vpiDirection:1 |vpiLowConn: @@ -34674,7 +34674,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (in2), line:17:20, endln:17:23 |vpiParent: - \_module: work@oh_mux5 (work@oh_mux5), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux5.v, line:8:1, endln:29:10 + \_module_inst: work@oh_mux5 (work@oh_mux5), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux5.v, line:8:1, endln:29:10 |vpiName:in2 |vpiDirection:1 |vpiLowConn: @@ -34714,7 +34714,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (in1), line:18:20, endln:18:23 |vpiParent: - \_module: work@oh_mux5 (work@oh_mux5), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux5.v, line:8:1, endln:29:10 + \_module_inst: work@oh_mux5 (work@oh_mux5), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux5.v, line:8:1, endln:29:10 |vpiName:in1 |vpiDirection:1 |vpiLowConn: @@ -34754,7 +34754,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (in0), line:19:20, endln:19:23 |vpiParent: - \_module: work@oh_mux5 (work@oh_mux5), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux5.v, line:8:1, endln:29:10 + \_module_inst: work@oh_mux5 (work@oh_mux5), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux5.v, line:8:1, endln:29:10 |vpiName:in0 |vpiDirection:1 |vpiLowConn: @@ -34794,7 +34794,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (out), line:20:20, endln:20:23 |vpiParent: - \_module: work@oh_mux5 (work@oh_mux5), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux5.v, line:8:1, endln:29:10 + \_module_inst: work@oh_mux5 (work@oh_mux5), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux5.v, line:8:1, endln:29:10 |vpiName:out |vpiDirection:2 |vpiLowConn: @@ -34834,7 +34834,7 @@ design: (work@oh_fifo_async) |vpiContAssign: \_cont_assign: , line:23:11, endln:27:30 |vpiParent: - \_module: work@oh_mux5 (work@oh_mux5), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux5.v, line:8:1, endln:29:10 + \_module_inst: work@oh_mux5 (work@oh_mux5), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux5.v, line:8:1, endln:29:10 |vpiRhs: \_operation: , line:23:25, endln:27:29 |vpiParent: @@ -35195,14 +35195,14 @@ design: (work@oh_fifo_async) |UINT:0 |vpiConstType:9 |uhdmallModules: -\_module: work@oh_mux6 (work@oh_mux6), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux6.v, line:8:1, endln:33:10 +\_module_inst: work@oh_mux6 (work@oh_mux6), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux6.v, line:8:1, endln:33:10 |vpiParent: \_design: (work@oh_fifo_async) |vpiFullName:work@oh_mux6 |vpiParameter: \_parameter: (work@oh_mux6.N), line:8:28, endln:8:29 |vpiParent: - \_module: work@oh_mux6 (work@oh_mux6), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux6.v, line:8:1, endln:33:10 + \_module_inst: work@oh_mux6 (work@oh_mux6), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux6.v, line:8:1, endln:33:10 |UINT:1 |vpiTypespec: \_int_typespec: @@ -35211,7 +35211,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:8:28, endln:8:33 |vpiParent: - \_module: work@oh_mux6 (work@oh_mux6), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux6.v, line:8:1, endln:33:10 + \_module_inst: work@oh_mux6 (work@oh_mux6), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux6.v, line:8:1, endln:33:10 |vpiRhs: \_constant: , line:8:32, endln:8:33 |vpiDecompile:1 @@ -35227,85 +35227,85 @@ design: (work@oh_fifo_async) |vpiNet: \_logic_net: (work@oh_mux6.sel5), line:10:16, endln:10:20 |vpiParent: - \_module: work@oh_mux6 (work@oh_mux6), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux6.v, line:8:1, endln:33:10 + \_module_inst: work@oh_mux6 (work@oh_mux6), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux6.v, line:8:1, endln:33:10 |vpiName:sel5 |vpiFullName:work@oh_mux6.sel5 |vpiNet: \_logic_net: (work@oh_mux6.sel4), line:11:16, endln:11:20 |vpiParent: - \_module: work@oh_mux6 (work@oh_mux6), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux6.v, line:8:1, endln:33:10 + \_module_inst: work@oh_mux6 (work@oh_mux6), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux6.v, line:8:1, endln:33:10 |vpiName:sel4 |vpiFullName:work@oh_mux6.sel4 |vpiNet: \_logic_net: (work@oh_mux6.sel3), line:12:16, endln:12:20 |vpiParent: - \_module: work@oh_mux6 (work@oh_mux6), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux6.v, line:8:1, endln:33:10 + \_module_inst: work@oh_mux6 (work@oh_mux6), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux6.v, line:8:1, endln:33:10 |vpiName:sel3 |vpiFullName:work@oh_mux6.sel3 |vpiNet: \_logic_net: (work@oh_mux6.sel2), line:13:16, endln:13:20 |vpiParent: - \_module: work@oh_mux6 (work@oh_mux6), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux6.v, line:8:1, endln:33:10 + \_module_inst: work@oh_mux6 (work@oh_mux6), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux6.v, line:8:1, endln:33:10 |vpiName:sel2 |vpiFullName:work@oh_mux6.sel2 |vpiNet: \_logic_net: (work@oh_mux6.sel1), line:14:16, endln:14:20 |vpiParent: - \_module: work@oh_mux6 (work@oh_mux6), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux6.v, line:8:1, endln:33:10 + \_module_inst: work@oh_mux6 (work@oh_mux6), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux6.v, line:8:1, endln:33:10 |vpiName:sel1 |vpiFullName:work@oh_mux6.sel1 |vpiNet: \_logic_net: (work@oh_mux6.sel0), line:15:16, endln:15:20 |vpiParent: - \_module: work@oh_mux6 (work@oh_mux6), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux6.v, line:8:1, endln:33:10 + \_module_inst: work@oh_mux6 (work@oh_mux6), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux6.v, line:8:1, endln:33:10 |vpiName:sel0 |vpiFullName:work@oh_mux6.sel0 |vpiNet: \_logic_net: (work@oh_mux6.in5), line:16:20, endln:16:23 |vpiParent: - \_module: work@oh_mux6 (work@oh_mux6), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux6.v, line:8:1, endln:33:10 + \_module_inst: work@oh_mux6 (work@oh_mux6), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux6.v, line:8:1, endln:33:10 |vpiName:in5 |vpiFullName:work@oh_mux6.in5 |vpiNet: \_logic_net: (work@oh_mux6.in4), line:17:20, endln:17:23 |vpiParent: - \_module: work@oh_mux6 (work@oh_mux6), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux6.v, line:8:1, endln:33:10 + \_module_inst: work@oh_mux6 (work@oh_mux6), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux6.v, line:8:1, endln:33:10 |vpiName:in4 |vpiFullName:work@oh_mux6.in4 |vpiNet: \_logic_net: (work@oh_mux6.in3), line:18:20, endln:18:23 |vpiParent: - \_module: work@oh_mux6 (work@oh_mux6), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux6.v, line:8:1, endln:33:10 + \_module_inst: work@oh_mux6 (work@oh_mux6), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux6.v, line:8:1, endln:33:10 |vpiName:in3 |vpiFullName:work@oh_mux6.in3 |vpiNet: \_logic_net: (work@oh_mux6.in2), line:19:20, endln:19:23 |vpiParent: - \_module: work@oh_mux6 (work@oh_mux6), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux6.v, line:8:1, endln:33:10 + \_module_inst: work@oh_mux6 (work@oh_mux6), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux6.v, line:8:1, endln:33:10 |vpiName:in2 |vpiFullName:work@oh_mux6.in2 |vpiNet: \_logic_net: (work@oh_mux6.in1), line:20:20, endln:20:23 |vpiParent: - \_module: work@oh_mux6 (work@oh_mux6), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux6.v, line:8:1, endln:33:10 + \_module_inst: work@oh_mux6 (work@oh_mux6), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux6.v, line:8:1, endln:33:10 |vpiName:in1 |vpiFullName:work@oh_mux6.in1 |vpiNet: \_logic_net: (work@oh_mux6.in0), line:21:20, endln:21:23 |vpiParent: - \_module: work@oh_mux6 (work@oh_mux6), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux6.v, line:8:1, endln:33:10 + \_module_inst: work@oh_mux6 (work@oh_mux6), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux6.v, line:8:1, endln:33:10 |vpiName:in0 |vpiFullName:work@oh_mux6.in0 |vpiNet: \_logic_net: (work@oh_mux6.out), line:22:20, endln:22:23 |vpiParent: - \_module: work@oh_mux6 (work@oh_mux6), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux6.v, line:8:1, endln:33:10 + \_module_inst: work@oh_mux6 (work@oh_mux6), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux6.v, line:8:1, endln:33:10 |vpiName:out |vpiFullName:work@oh_mux6.out |vpiPort: \_port: (sel5), line:10:16, endln:10:20 |vpiParent: - \_module: work@oh_mux6 (work@oh_mux6), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux6.v, line:8:1, endln:33:10 + \_module_inst: work@oh_mux6 (work@oh_mux6), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux6.v, line:8:1, endln:33:10 |vpiName:sel5 |vpiDirection:1 |vpiLowConn: @@ -35317,7 +35317,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (sel4), line:11:16, endln:11:20 |vpiParent: - \_module: work@oh_mux6 (work@oh_mux6), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux6.v, line:8:1, endln:33:10 + \_module_inst: work@oh_mux6 (work@oh_mux6), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux6.v, line:8:1, endln:33:10 |vpiName:sel4 |vpiDirection:1 |vpiLowConn: @@ -35329,7 +35329,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (sel3), line:12:16, endln:12:20 |vpiParent: - \_module: work@oh_mux6 (work@oh_mux6), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux6.v, line:8:1, endln:33:10 + \_module_inst: work@oh_mux6 (work@oh_mux6), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux6.v, line:8:1, endln:33:10 |vpiName:sel3 |vpiDirection:1 |vpiLowConn: @@ -35341,7 +35341,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (sel2), line:13:16, endln:13:20 |vpiParent: - \_module: work@oh_mux6 (work@oh_mux6), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux6.v, line:8:1, endln:33:10 + \_module_inst: work@oh_mux6 (work@oh_mux6), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux6.v, line:8:1, endln:33:10 |vpiName:sel2 |vpiDirection:1 |vpiLowConn: @@ -35353,7 +35353,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (sel1), line:14:16, endln:14:20 |vpiParent: - \_module: work@oh_mux6 (work@oh_mux6), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux6.v, line:8:1, endln:33:10 + \_module_inst: work@oh_mux6 (work@oh_mux6), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux6.v, line:8:1, endln:33:10 |vpiName:sel1 |vpiDirection:1 |vpiLowConn: @@ -35365,7 +35365,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (sel0), line:15:16, endln:15:20 |vpiParent: - \_module: work@oh_mux6 (work@oh_mux6), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux6.v, line:8:1, endln:33:10 + \_module_inst: work@oh_mux6 (work@oh_mux6), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux6.v, line:8:1, endln:33:10 |vpiName:sel0 |vpiDirection:1 |vpiLowConn: @@ -35377,7 +35377,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (in5), line:16:20, endln:16:23 |vpiParent: - \_module: work@oh_mux6 (work@oh_mux6), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux6.v, line:8:1, endln:33:10 + \_module_inst: work@oh_mux6 (work@oh_mux6), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux6.v, line:8:1, endln:33:10 |vpiName:in5 |vpiDirection:1 |vpiLowConn: @@ -35417,7 +35417,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (in4), line:17:20, endln:17:23 |vpiParent: - \_module: work@oh_mux6 (work@oh_mux6), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux6.v, line:8:1, endln:33:10 + \_module_inst: work@oh_mux6 (work@oh_mux6), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux6.v, line:8:1, endln:33:10 |vpiName:in4 |vpiDirection:1 |vpiLowConn: @@ -35457,7 +35457,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (in3), line:18:20, endln:18:23 |vpiParent: - \_module: work@oh_mux6 (work@oh_mux6), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux6.v, line:8:1, endln:33:10 + \_module_inst: work@oh_mux6 (work@oh_mux6), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux6.v, line:8:1, endln:33:10 |vpiName:in3 |vpiDirection:1 |vpiLowConn: @@ -35497,7 +35497,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (in2), line:19:20, endln:19:23 |vpiParent: - \_module: work@oh_mux6 (work@oh_mux6), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux6.v, line:8:1, endln:33:10 + \_module_inst: work@oh_mux6 (work@oh_mux6), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux6.v, line:8:1, endln:33:10 |vpiName:in2 |vpiDirection:1 |vpiLowConn: @@ -35537,7 +35537,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (in1), line:20:20, endln:20:23 |vpiParent: - \_module: work@oh_mux6 (work@oh_mux6), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux6.v, line:8:1, endln:33:10 + \_module_inst: work@oh_mux6 (work@oh_mux6), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux6.v, line:8:1, endln:33:10 |vpiName:in1 |vpiDirection:1 |vpiLowConn: @@ -35577,7 +35577,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (in0), line:21:20, endln:21:23 |vpiParent: - \_module: work@oh_mux6 (work@oh_mux6), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux6.v, line:8:1, endln:33:10 + \_module_inst: work@oh_mux6 (work@oh_mux6), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux6.v, line:8:1, endln:33:10 |vpiName:in0 |vpiDirection:1 |vpiLowConn: @@ -35617,7 +35617,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (out), line:22:20, endln:22:23 |vpiParent: - \_module: work@oh_mux6 (work@oh_mux6), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux6.v, line:8:1, endln:33:10 + \_module_inst: work@oh_mux6 (work@oh_mux6), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux6.v, line:8:1, endln:33:10 |vpiName:out |vpiDirection:2 |vpiLowConn: @@ -35657,7 +35657,7 @@ design: (work@oh_fifo_async) |vpiContAssign: \_cont_assign: , line:25:11, endln:30:30 |vpiParent: - \_module: work@oh_mux6 (work@oh_mux6), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux6.v, line:8:1, endln:33:10 + \_module_inst: work@oh_mux6 (work@oh_mux6), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux6.v, line:8:1, endln:33:10 |vpiRhs: \_operation: , line:25:25, endln:30:29 |vpiParent: @@ -36085,14 +36085,14 @@ design: (work@oh_fifo_async) |UINT:0 |vpiConstType:9 |uhdmallModules: -\_module: work@oh_mux7 (work@oh_mux7), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux7.v, line:8:1, endln:36:10 +\_module_inst: work@oh_mux7 (work@oh_mux7), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux7.v, line:8:1, endln:36:10 |vpiParent: \_design: (work@oh_fifo_async) |vpiFullName:work@oh_mux7 |vpiParameter: \_parameter: (work@oh_mux7.N), line:8:28, endln:8:29 |vpiParent: - \_module: work@oh_mux7 (work@oh_mux7), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux7.v, line:8:1, endln:36:10 + \_module_inst: work@oh_mux7 (work@oh_mux7), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux7.v, line:8:1, endln:36:10 |UINT:1 |vpiTypespec: \_int_typespec: @@ -36101,7 +36101,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:8:28, endln:8:33 |vpiParent: - \_module: work@oh_mux7 (work@oh_mux7), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux7.v, line:8:1, endln:36:10 + \_module_inst: work@oh_mux7 (work@oh_mux7), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux7.v, line:8:1, endln:36:10 |vpiRhs: \_constant: , line:8:32, endln:8:33 |vpiDecompile:1 @@ -36117,97 +36117,97 @@ design: (work@oh_fifo_async) |vpiNet: \_logic_net: (work@oh_mux7.sel6), line:10:16, endln:10:20 |vpiParent: - \_module: work@oh_mux7 (work@oh_mux7), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux7.v, line:8:1, endln:36:10 + \_module_inst: work@oh_mux7 (work@oh_mux7), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux7.v, line:8:1, endln:36:10 |vpiName:sel6 |vpiFullName:work@oh_mux7.sel6 |vpiNet: \_logic_net: (work@oh_mux7.sel5), line:11:16, endln:11:20 |vpiParent: - \_module: work@oh_mux7 (work@oh_mux7), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux7.v, line:8:1, endln:36:10 + \_module_inst: work@oh_mux7 (work@oh_mux7), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux7.v, line:8:1, endln:36:10 |vpiName:sel5 |vpiFullName:work@oh_mux7.sel5 |vpiNet: \_logic_net: (work@oh_mux7.sel4), line:12:16, endln:12:20 |vpiParent: - \_module: work@oh_mux7 (work@oh_mux7), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux7.v, line:8:1, endln:36:10 + \_module_inst: work@oh_mux7 (work@oh_mux7), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux7.v, line:8:1, endln:36:10 |vpiName:sel4 |vpiFullName:work@oh_mux7.sel4 |vpiNet: \_logic_net: (work@oh_mux7.sel3), line:13:16, endln:13:20 |vpiParent: - \_module: work@oh_mux7 (work@oh_mux7), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux7.v, line:8:1, endln:36:10 + \_module_inst: work@oh_mux7 (work@oh_mux7), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux7.v, line:8:1, endln:36:10 |vpiName:sel3 |vpiFullName:work@oh_mux7.sel3 |vpiNet: \_logic_net: (work@oh_mux7.sel2), line:14:16, endln:14:20 |vpiParent: - \_module: work@oh_mux7 (work@oh_mux7), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux7.v, line:8:1, endln:36:10 + \_module_inst: work@oh_mux7 (work@oh_mux7), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux7.v, line:8:1, endln:36:10 |vpiName:sel2 |vpiFullName:work@oh_mux7.sel2 |vpiNet: \_logic_net: (work@oh_mux7.sel1), line:15:16, endln:15:20 |vpiParent: - \_module: work@oh_mux7 (work@oh_mux7), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux7.v, line:8:1, endln:36:10 + \_module_inst: work@oh_mux7 (work@oh_mux7), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux7.v, line:8:1, endln:36:10 |vpiName:sel1 |vpiFullName:work@oh_mux7.sel1 |vpiNet: \_logic_net: (work@oh_mux7.sel0), line:16:16, endln:16:20 |vpiParent: - \_module: work@oh_mux7 (work@oh_mux7), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux7.v, line:8:1, endln:36:10 + \_module_inst: work@oh_mux7 (work@oh_mux7), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux7.v, line:8:1, endln:36:10 |vpiName:sel0 |vpiFullName:work@oh_mux7.sel0 |vpiNet: \_logic_net: (work@oh_mux7.in6), line:17:20, endln:17:23 |vpiParent: - \_module: work@oh_mux7 (work@oh_mux7), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux7.v, line:8:1, endln:36:10 + \_module_inst: work@oh_mux7 (work@oh_mux7), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux7.v, line:8:1, endln:36:10 |vpiName:in6 |vpiFullName:work@oh_mux7.in6 |vpiNet: \_logic_net: (work@oh_mux7.in5), line:18:20, endln:18:23 |vpiParent: - \_module: work@oh_mux7 (work@oh_mux7), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux7.v, line:8:1, endln:36:10 + \_module_inst: work@oh_mux7 (work@oh_mux7), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux7.v, line:8:1, endln:36:10 |vpiName:in5 |vpiFullName:work@oh_mux7.in5 |vpiNet: \_logic_net: (work@oh_mux7.in4), line:19:20, endln:19:23 |vpiParent: - \_module: work@oh_mux7 (work@oh_mux7), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux7.v, line:8:1, endln:36:10 + \_module_inst: work@oh_mux7 (work@oh_mux7), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux7.v, line:8:1, endln:36:10 |vpiName:in4 |vpiFullName:work@oh_mux7.in4 |vpiNet: \_logic_net: (work@oh_mux7.in3), line:20:20, endln:20:23 |vpiParent: - \_module: work@oh_mux7 (work@oh_mux7), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux7.v, line:8:1, endln:36:10 + \_module_inst: work@oh_mux7 (work@oh_mux7), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux7.v, line:8:1, endln:36:10 |vpiName:in3 |vpiFullName:work@oh_mux7.in3 |vpiNet: \_logic_net: (work@oh_mux7.in2), line:21:20, endln:21:23 |vpiParent: - \_module: work@oh_mux7 (work@oh_mux7), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux7.v, line:8:1, endln:36:10 + \_module_inst: work@oh_mux7 (work@oh_mux7), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux7.v, line:8:1, endln:36:10 |vpiName:in2 |vpiFullName:work@oh_mux7.in2 |vpiNet: \_logic_net: (work@oh_mux7.in1), line:22:20, endln:22:23 |vpiParent: - \_module: work@oh_mux7 (work@oh_mux7), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux7.v, line:8:1, endln:36:10 + \_module_inst: work@oh_mux7 (work@oh_mux7), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux7.v, line:8:1, endln:36:10 |vpiName:in1 |vpiFullName:work@oh_mux7.in1 |vpiNet: \_logic_net: (work@oh_mux7.in0), line:23:20, endln:23:23 |vpiParent: - \_module: work@oh_mux7 (work@oh_mux7), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux7.v, line:8:1, endln:36:10 + \_module_inst: work@oh_mux7 (work@oh_mux7), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux7.v, line:8:1, endln:36:10 |vpiName:in0 |vpiFullName:work@oh_mux7.in0 |vpiNet: \_logic_net: (work@oh_mux7.out), line:24:20, endln:24:23 |vpiParent: - \_module: work@oh_mux7 (work@oh_mux7), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux7.v, line:8:1, endln:36:10 + \_module_inst: work@oh_mux7 (work@oh_mux7), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux7.v, line:8:1, endln:36:10 |vpiName:out |vpiFullName:work@oh_mux7.out |vpiPort: \_port: (sel6), line:10:16, endln:10:20 |vpiParent: - \_module: work@oh_mux7 (work@oh_mux7), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux7.v, line:8:1, endln:36:10 + \_module_inst: work@oh_mux7 (work@oh_mux7), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux7.v, line:8:1, endln:36:10 |vpiName:sel6 |vpiDirection:1 |vpiLowConn: @@ -36219,7 +36219,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (sel5), line:11:16, endln:11:20 |vpiParent: - \_module: work@oh_mux7 (work@oh_mux7), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux7.v, line:8:1, endln:36:10 + \_module_inst: work@oh_mux7 (work@oh_mux7), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux7.v, line:8:1, endln:36:10 |vpiName:sel5 |vpiDirection:1 |vpiLowConn: @@ -36231,7 +36231,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (sel4), line:12:16, endln:12:20 |vpiParent: - \_module: work@oh_mux7 (work@oh_mux7), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux7.v, line:8:1, endln:36:10 + \_module_inst: work@oh_mux7 (work@oh_mux7), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux7.v, line:8:1, endln:36:10 |vpiName:sel4 |vpiDirection:1 |vpiLowConn: @@ -36243,7 +36243,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (sel3), line:13:16, endln:13:20 |vpiParent: - \_module: work@oh_mux7 (work@oh_mux7), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux7.v, line:8:1, endln:36:10 + \_module_inst: work@oh_mux7 (work@oh_mux7), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux7.v, line:8:1, endln:36:10 |vpiName:sel3 |vpiDirection:1 |vpiLowConn: @@ -36255,7 +36255,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (sel2), line:14:16, endln:14:20 |vpiParent: - \_module: work@oh_mux7 (work@oh_mux7), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux7.v, line:8:1, endln:36:10 + \_module_inst: work@oh_mux7 (work@oh_mux7), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux7.v, line:8:1, endln:36:10 |vpiName:sel2 |vpiDirection:1 |vpiLowConn: @@ -36267,7 +36267,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (sel1), line:15:16, endln:15:20 |vpiParent: - \_module: work@oh_mux7 (work@oh_mux7), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux7.v, line:8:1, endln:36:10 + \_module_inst: work@oh_mux7 (work@oh_mux7), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux7.v, line:8:1, endln:36:10 |vpiName:sel1 |vpiDirection:1 |vpiLowConn: @@ -36279,7 +36279,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (sel0), line:16:16, endln:16:20 |vpiParent: - \_module: work@oh_mux7 (work@oh_mux7), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux7.v, line:8:1, endln:36:10 + \_module_inst: work@oh_mux7 (work@oh_mux7), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux7.v, line:8:1, endln:36:10 |vpiName:sel0 |vpiDirection:1 |vpiLowConn: @@ -36291,7 +36291,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (in6), line:17:20, endln:17:23 |vpiParent: - \_module: work@oh_mux7 (work@oh_mux7), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux7.v, line:8:1, endln:36:10 + \_module_inst: work@oh_mux7 (work@oh_mux7), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux7.v, line:8:1, endln:36:10 |vpiName:in6 |vpiDirection:1 |vpiLowConn: @@ -36331,7 +36331,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (in5), line:18:20, endln:18:23 |vpiParent: - \_module: work@oh_mux7 (work@oh_mux7), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux7.v, line:8:1, endln:36:10 + \_module_inst: work@oh_mux7 (work@oh_mux7), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux7.v, line:8:1, endln:36:10 |vpiName:in5 |vpiDirection:1 |vpiLowConn: @@ -36371,7 +36371,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (in4), line:19:20, endln:19:23 |vpiParent: - \_module: work@oh_mux7 (work@oh_mux7), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux7.v, line:8:1, endln:36:10 + \_module_inst: work@oh_mux7 (work@oh_mux7), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux7.v, line:8:1, endln:36:10 |vpiName:in4 |vpiDirection:1 |vpiLowConn: @@ -36411,7 +36411,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (in3), line:20:20, endln:20:23 |vpiParent: - \_module: work@oh_mux7 (work@oh_mux7), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux7.v, line:8:1, endln:36:10 + \_module_inst: work@oh_mux7 (work@oh_mux7), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux7.v, line:8:1, endln:36:10 |vpiName:in3 |vpiDirection:1 |vpiLowConn: @@ -36451,7 +36451,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (in2), line:21:20, endln:21:23 |vpiParent: - \_module: work@oh_mux7 (work@oh_mux7), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux7.v, line:8:1, endln:36:10 + \_module_inst: work@oh_mux7 (work@oh_mux7), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux7.v, line:8:1, endln:36:10 |vpiName:in2 |vpiDirection:1 |vpiLowConn: @@ -36491,7 +36491,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (in1), line:22:20, endln:22:23 |vpiParent: - \_module: work@oh_mux7 (work@oh_mux7), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux7.v, line:8:1, endln:36:10 + \_module_inst: work@oh_mux7 (work@oh_mux7), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux7.v, line:8:1, endln:36:10 |vpiName:in1 |vpiDirection:1 |vpiLowConn: @@ -36531,7 +36531,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (in0), line:23:20, endln:23:23 |vpiParent: - \_module: work@oh_mux7 (work@oh_mux7), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux7.v, line:8:1, endln:36:10 + \_module_inst: work@oh_mux7 (work@oh_mux7), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux7.v, line:8:1, endln:36:10 |vpiName:in0 |vpiDirection:1 |vpiLowConn: @@ -36571,7 +36571,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (out), line:24:20, endln:24:23 |vpiParent: - \_module: work@oh_mux7 (work@oh_mux7), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux7.v, line:8:1, endln:36:10 + \_module_inst: work@oh_mux7 (work@oh_mux7), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux7.v, line:8:1, endln:36:10 |vpiName:out |vpiDirection:2 |vpiLowConn: @@ -36611,7 +36611,7 @@ design: (work@oh_fifo_async) |vpiContAssign: \_cont_assign: , line:27:11, endln:33:30 |vpiParent: - \_module: work@oh_mux7 (work@oh_mux7), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux7.v, line:8:1, endln:36:10 + \_module_inst: work@oh_mux7 (work@oh_mux7), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux7.v, line:8:1, endln:36:10 |vpiRhs: \_operation: , line:27:25, endln:33:29 |vpiParent: @@ -37106,14 +37106,14 @@ design: (work@oh_fifo_async) |UINT:0 |vpiConstType:9 |uhdmallModules: -\_module: work@oh_mux8 (work@oh_mux8), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux8.v, line:8:1, endln:39:10 +\_module_inst: work@oh_mux8 (work@oh_mux8), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux8.v, line:8:1, endln:39:10 |vpiParent: \_design: (work@oh_fifo_async) |vpiFullName:work@oh_mux8 |vpiParameter: \_parameter: (work@oh_mux8.N), line:8:28, endln:8:29 |vpiParent: - \_module: work@oh_mux8 (work@oh_mux8), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux8.v, line:8:1, endln:39:10 + \_module_inst: work@oh_mux8 (work@oh_mux8), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux8.v, line:8:1, endln:39:10 |UINT:1 |vpiTypespec: \_int_typespec: @@ -37122,7 +37122,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:8:28, endln:8:33 |vpiParent: - \_module: work@oh_mux8 (work@oh_mux8), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux8.v, line:8:1, endln:39:10 + \_module_inst: work@oh_mux8 (work@oh_mux8), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux8.v, line:8:1, endln:39:10 |vpiRhs: \_constant: , line:8:32, endln:8:33 |vpiDecompile:1 @@ -37138,109 +37138,109 @@ design: (work@oh_fifo_async) |vpiNet: \_logic_net: (work@oh_mux8.sel7), line:10:16, endln:10:20 |vpiParent: - \_module: work@oh_mux8 (work@oh_mux8), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux8.v, line:8:1, endln:39:10 + \_module_inst: work@oh_mux8 (work@oh_mux8), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux8.v, line:8:1, endln:39:10 |vpiName:sel7 |vpiFullName:work@oh_mux8.sel7 |vpiNet: \_logic_net: (work@oh_mux8.sel6), line:11:16, endln:11:20 |vpiParent: - \_module: work@oh_mux8 (work@oh_mux8), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux8.v, line:8:1, endln:39:10 + \_module_inst: work@oh_mux8 (work@oh_mux8), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux8.v, line:8:1, endln:39:10 |vpiName:sel6 |vpiFullName:work@oh_mux8.sel6 |vpiNet: \_logic_net: (work@oh_mux8.sel5), line:12:16, endln:12:20 |vpiParent: - \_module: work@oh_mux8 (work@oh_mux8), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux8.v, line:8:1, endln:39:10 + \_module_inst: work@oh_mux8 (work@oh_mux8), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux8.v, line:8:1, endln:39:10 |vpiName:sel5 |vpiFullName:work@oh_mux8.sel5 |vpiNet: \_logic_net: (work@oh_mux8.sel4), line:13:16, endln:13:20 |vpiParent: - \_module: work@oh_mux8 (work@oh_mux8), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux8.v, line:8:1, endln:39:10 + \_module_inst: work@oh_mux8 (work@oh_mux8), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux8.v, line:8:1, endln:39:10 |vpiName:sel4 |vpiFullName:work@oh_mux8.sel4 |vpiNet: \_logic_net: (work@oh_mux8.sel3), line:14:16, endln:14:20 |vpiParent: - \_module: work@oh_mux8 (work@oh_mux8), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux8.v, line:8:1, endln:39:10 + \_module_inst: work@oh_mux8 (work@oh_mux8), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux8.v, line:8:1, endln:39:10 |vpiName:sel3 |vpiFullName:work@oh_mux8.sel3 |vpiNet: \_logic_net: (work@oh_mux8.sel2), line:15:16, endln:15:20 |vpiParent: - \_module: work@oh_mux8 (work@oh_mux8), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux8.v, line:8:1, endln:39:10 + \_module_inst: work@oh_mux8 (work@oh_mux8), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux8.v, line:8:1, endln:39:10 |vpiName:sel2 |vpiFullName:work@oh_mux8.sel2 |vpiNet: \_logic_net: (work@oh_mux8.sel1), line:16:16, endln:16:20 |vpiParent: - \_module: work@oh_mux8 (work@oh_mux8), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux8.v, line:8:1, endln:39:10 + \_module_inst: work@oh_mux8 (work@oh_mux8), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux8.v, line:8:1, endln:39:10 |vpiName:sel1 |vpiFullName:work@oh_mux8.sel1 |vpiNet: \_logic_net: (work@oh_mux8.sel0), line:17:16, endln:17:20 |vpiParent: - \_module: work@oh_mux8 (work@oh_mux8), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux8.v, line:8:1, endln:39:10 + \_module_inst: work@oh_mux8 (work@oh_mux8), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux8.v, line:8:1, endln:39:10 |vpiName:sel0 |vpiFullName:work@oh_mux8.sel0 |vpiNet: \_logic_net: (work@oh_mux8.in7), line:18:20, endln:18:23 |vpiParent: - \_module: work@oh_mux8 (work@oh_mux8), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux8.v, line:8:1, endln:39:10 + \_module_inst: work@oh_mux8 (work@oh_mux8), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux8.v, line:8:1, endln:39:10 |vpiName:in7 |vpiFullName:work@oh_mux8.in7 |vpiNet: \_logic_net: (work@oh_mux8.in6), line:19:20, endln:19:23 |vpiParent: - \_module: work@oh_mux8 (work@oh_mux8), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux8.v, line:8:1, endln:39:10 + \_module_inst: work@oh_mux8 (work@oh_mux8), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux8.v, line:8:1, endln:39:10 |vpiName:in6 |vpiFullName:work@oh_mux8.in6 |vpiNet: \_logic_net: (work@oh_mux8.in5), line:20:20, endln:20:23 |vpiParent: - \_module: work@oh_mux8 (work@oh_mux8), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux8.v, line:8:1, endln:39:10 + \_module_inst: work@oh_mux8 (work@oh_mux8), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux8.v, line:8:1, endln:39:10 |vpiName:in5 |vpiFullName:work@oh_mux8.in5 |vpiNet: \_logic_net: (work@oh_mux8.in4), line:21:20, endln:21:23 |vpiParent: - \_module: work@oh_mux8 (work@oh_mux8), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux8.v, line:8:1, endln:39:10 + \_module_inst: work@oh_mux8 (work@oh_mux8), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux8.v, line:8:1, endln:39:10 |vpiName:in4 |vpiFullName:work@oh_mux8.in4 |vpiNet: \_logic_net: (work@oh_mux8.in3), line:22:20, endln:22:23 |vpiParent: - \_module: work@oh_mux8 (work@oh_mux8), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux8.v, line:8:1, endln:39:10 + \_module_inst: work@oh_mux8 (work@oh_mux8), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux8.v, line:8:1, endln:39:10 |vpiName:in3 |vpiFullName:work@oh_mux8.in3 |vpiNet: \_logic_net: (work@oh_mux8.in2), line:23:20, endln:23:23 |vpiParent: - \_module: work@oh_mux8 (work@oh_mux8), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux8.v, line:8:1, endln:39:10 + \_module_inst: work@oh_mux8 (work@oh_mux8), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux8.v, line:8:1, endln:39:10 |vpiName:in2 |vpiFullName:work@oh_mux8.in2 |vpiNet: \_logic_net: (work@oh_mux8.in1), line:24:20, endln:24:23 |vpiParent: - \_module: work@oh_mux8 (work@oh_mux8), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux8.v, line:8:1, endln:39:10 + \_module_inst: work@oh_mux8 (work@oh_mux8), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux8.v, line:8:1, endln:39:10 |vpiName:in1 |vpiFullName:work@oh_mux8.in1 |vpiNet: \_logic_net: (work@oh_mux8.in0), line:25:20, endln:25:23 |vpiParent: - \_module: work@oh_mux8 (work@oh_mux8), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux8.v, line:8:1, endln:39:10 + \_module_inst: work@oh_mux8 (work@oh_mux8), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux8.v, line:8:1, endln:39:10 |vpiName:in0 |vpiFullName:work@oh_mux8.in0 |vpiNet: \_logic_net: (work@oh_mux8.out), line:26:20, endln:26:23 |vpiParent: - \_module: work@oh_mux8 (work@oh_mux8), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux8.v, line:8:1, endln:39:10 + \_module_inst: work@oh_mux8 (work@oh_mux8), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux8.v, line:8:1, endln:39:10 |vpiName:out |vpiFullName:work@oh_mux8.out |vpiPort: \_port: (sel7), line:10:16, endln:10:20 |vpiParent: - \_module: work@oh_mux8 (work@oh_mux8), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux8.v, line:8:1, endln:39:10 + \_module_inst: work@oh_mux8 (work@oh_mux8), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux8.v, line:8:1, endln:39:10 |vpiName:sel7 |vpiDirection:1 |vpiLowConn: @@ -37252,7 +37252,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (sel6), line:11:16, endln:11:20 |vpiParent: - \_module: work@oh_mux8 (work@oh_mux8), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux8.v, line:8:1, endln:39:10 + \_module_inst: work@oh_mux8 (work@oh_mux8), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux8.v, line:8:1, endln:39:10 |vpiName:sel6 |vpiDirection:1 |vpiLowConn: @@ -37264,7 +37264,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (sel5), line:12:16, endln:12:20 |vpiParent: - \_module: work@oh_mux8 (work@oh_mux8), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux8.v, line:8:1, endln:39:10 + \_module_inst: work@oh_mux8 (work@oh_mux8), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux8.v, line:8:1, endln:39:10 |vpiName:sel5 |vpiDirection:1 |vpiLowConn: @@ -37276,7 +37276,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (sel4), line:13:16, endln:13:20 |vpiParent: - \_module: work@oh_mux8 (work@oh_mux8), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux8.v, line:8:1, endln:39:10 + \_module_inst: work@oh_mux8 (work@oh_mux8), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux8.v, line:8:1, endln:39:10 |vpiName:sel4 |vpiDirection:1 |vpiLowConn: @@ -37288,7 +37288,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (sel3), line:14:16, endln:14:20 |vpiParent: - \_module: work@oh_mux8 (work@oh_mux8), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux8.v, line:8:1, endln:39:10 + \_module_inst: work@oh_mux8 (work@oh_mux8), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux8.v, line:8:1, endln:39:10 |vpiName:sel3 |vpiDirection:1 |vpiLowConn: @@ -37300,7 +37300,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (sel2), line:15:16, endln:15:20 |vpiParent: - \_module: work@oh_mux8 (work@oh_mux8), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux8.v, line:8:1, endln:39:10 + \_module_inst: work@oh_mux8 (work@oh_mux8), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux8.v, line:8:1, endln:39:10 |vpiName:sel2 |vpiDirection:1 |vpiLowConn: @@ -37312,7 +37312,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (sel1), line:16:16, endln:16:20 |vpiParent: - \_module: work@oh_mux8 (work@oh_mux8), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux8.v, line:8:1, endln:39:10 + \_module_inst: work@oh_mux8 (work@oh_mux8), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux8.v, line:8:1, endln:39:10 |vpiName:sel1 |vpiDirection:1 |vpiLowConn: @@ -37324,7 +37324,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (sel0), line:17:16, endln:17:20 |vpiParent: - \_module: work@oh_mux8 (work@oh_mux8), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux8.v, line:8:1, endln:39:10 + \_module_inst: work@oh_mux8 (work@oh_mux8), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux8.v, line:8:1, endln:39:10 |vpiName:sel0 |vpiDirection:1 |vpiLowConn: @@ -37336,7 +37336,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (in7), line:18:20, endln:18:23 |vpiParent: - \_module: work@oh_mux8 (work@oh_mux8), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux8.v, line:8:1, endln:39:10 + \_module_inst: work@oh_mux8 (work@oh_mux8), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux8.v, line:8:1, endln:39:10 |vpiName:in7 |vpiDirection:1 |vpiLowConn: @@ -37376,7 +37376,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (in6), line:19:20, endln:19:23 |vpiParent: - \_module: work@oh_mux8 (work@oh_mux8), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux8.v, line:8:1, endln:39:10 + \_module_inst: work@oh_mux8 (work@oh_mux8), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux8.v, line:8:1, endln:39:10 |vpiName:in6 |vpiDirection:1 |vpiLowConn: @@ -37416,7 +37416,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (in5), line:20:20, endln:20:23 |vpiParent: - \_module: work@oh_mux8 (work@oh_mux8), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux8.v, line:8:1, endln:39:10 + \_module_inst: work@oh_mux8 (work@oh_mux8), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux8.v, line:8:1, endln:39:10 |vpiName:in5 |vpiDirection:1 |vpiLowConn: @@ -37456,7 +37456,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (in4), line:21:20, endln:21:23 |vpiParent: - \_module: work@oh_mux8 (work@oh_mux8), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux8.v, line:8:1, endln:39:10 + \_module_inst: work@oh_mux8 (work@oh_mux8), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux8.v, line:8:1, endln:39:10 |vpiName:in4 |vpiDirection:1 |vpiLowConn: @@ -37496,7 +37496,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (in3), line:22:20, endln:22:23 |vpiParent: - \_module: work@oh_mux8 (work@oh_mux8), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux8.v, line:8:1, endln:39:10 + \_module_inst: work@oh_mux8 (work@oh_mux8), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux8.v, line:8:1, endln:39:10 |vpiName:in3 |vpiDirection:1 |vpiLowConn: @@ -37536,7 +37536,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (in2), line:23:20, endln:23:23 |vpiParent: - \_module: work@oh_mux8 (work@oh_mux8), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux8.v, line:8:1, endln:39:10 + \_module_inst: work@oh_mux8 (work@oh_mux8), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux8.v, line:8:1, endln:39:10 |vpiName:in2 |vpiDirection:1 |vpiLowConn: @@ -37576,7 +37576,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (in1), line:24:20, endln:24:23 |vpiParent: - \_module: work@oh_mux8 (work@oh_mux8), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux8.v, line:8:1, endln:39:10 + \_module_inst: work@oh_mux8 (work@oh_mux8), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux8.v, line:8:1, endln:39:10 |vpiName:in1 |vpiDirection:1 |vpiLowConn: @@ -37616,7 +37616,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (in0), line:25:20, endln:25:23 |vpiParent: - \_module: work@oh_mux8 (work@oh_mux8), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux8.v, line:8:1, endln:39:10 + \_module_inst: work@oh_mux8 (work@oh_mux8), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux8.v, line:8:1, endln:39:10 |vpiName:in0 |vpiDirection:1 |vpiLowConn: @@ -37656,7 +37656,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (out), line:26:20, endln:26:23 |vpiParent: - \_module: work@oh_mux8 (work@oh_mux8), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux8.v, line:8:1, endln:39:10 + \_module_inst: work@oh_mux8 (work@oh_mux8), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux8.v, line:8:1, endln:39:10 |vpiName:out |vpiDirection:2 |vpiLowConn: @@ -37696,7 +37696,7 @@ design: (work@oh_fifo_async) |vpiContAssign: \_cont_assign: , line:29:11, endln:36:30 |vpiParent: - \_module: work@oh_mux8 (work@oh_mux8), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux8.v, line:8:1, endln:39:10 + \_module_inst: work@oh_mux8 (work@oh_mux8), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux8.v, line:8:1, endln:39:10 |vpiRhs: \_operation: , line:29:25, endln:36:29 |vpiParent: @@ -38258,14 +38258,14 @@ design: (work@oh_fifo_async) |UINT:0 |vpiConstType:9 |uhdmallModules: -\_module: work@oh_mux9 (work@oh_mux9), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux9.v, line:8:1, endln:41:10 +\_module_inst: work@oh_mux9 (work@oh_mux9), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux9.v, line:8:1, endln:41:10 |vpiParent: \_design: (work@oh_fifo_async) |vpiFullName:work@oh_mux9 |vpiParameter: \_parameter: (work@oh_mux9.N), line:8:29, endln:8:30 |vpiParent: - \_module: work@oh_mux9 (work@oh_mux9), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux9.v, line:8:1, endln:41:10 + \_module_inst: work@oh_mux9 (work@oh_mux9), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux9.v, line:8:1, endln:41:10 |UINT:1 |vpiTypespec: \_int_typespec: @@ -38274,7 +38274,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:8:29, endln:8:34 |vpiParent: - \_module: work@oh_mux9 (work@oh_mux9), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux9.v, line:8:1, endln:41:10 + \_module_inst: work@oh_mux9 (work@oh_mux9), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux9.v, line:8:1, endln:41:10 |vpiRhs: \_constant: , line:8:33, endln:8:34 |vpiDecompile:1 @@ -38290,121 +38290,121 @@ design: (work@oh_fifo_async) |vpiNet: \_logic_net: (work@oh_mux9.sel8), line:10:16, endln:10:20 |vpiParent: - \_module: work@oh_mux9 (work@oh_mux9), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux9.v, line:8:1, endln:41:10 + \_module_inst: work@oh_mux9 (work@oh_mux9), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux9.v, line:8:1, endln:41:10 |vpiName:sel8 |vpiFullName:work@oh_mux9.sel8 |vpiNet: \_logic_net: (work@oh_mux9.sel7), line:11:16, endln:11:20 |vpiParent: - \_module: work@oh_mux9 (work@oh_mux9), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux9.v, line:8:1, endln:41:10 + \_module_inst: work@oh_mux9 (work@oh_mux9), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux9.v, line:8:1, endln:41:10 |vpiName:sel7 |vpiFullName:work@oh_mux9.sel7 |vpiNet: \_logic_net: (work@oh_mux9.sel6), line:12:16, endln:12:20 |vpiParent: - \_module: work@oh_mux9 (work@oh_mux9), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux9.v, line:8:1, endln:41:10 + \_module_inst: work@oh_mux9 (work@oh_mux9), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux9.v, line:8:1, endln:41:10 |vpiName:sel6 |vpiFullName:work@oh_mux9.sel6 |vpiNet: \_logic_net: (work@oh_mux9.sel5), line:13:16, endln:13:20 |vpiParent: - \_module: work@oh_mux9 (work@oh_mux9), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux9.v, line:8:1, endln:41:10 + \_module_inst: work@oh_mux9 (work@oh_mux9), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux9.v, line:8:1, endln:41:10 |vpiName:sel5 |vpiFullName:work@oh_mux9.sel5 |vpiNet: \_logic_net: (work@oh_mux9.sel4), line:14:16, endln:14:20 |vpiParent: - \_module: work@oh_mux9 (work@oh_mux9), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux9.v, line:8:1, endln:41:10 + \_module_inst: work@oh_mux9 (work@oh_mux9), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux9.v, line:8:1, endln:41:10 |vpiName:sel4 |vpiFullName:work@oh_mux9.sel4 |vpiNet: \_logic_net: (work@oh_mux9.sel3), line:15:16, endln:15:20 |vpiParent: - \_module: work@oh_mux9 (work@oh_mux9), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux9.v, line:8:1, endln:41:10 + \_module_inst: work@oh_mux9 (work@oh_mux9), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux9.v, line:8:1, endln:41:10 |vpiName:sel3 |vpiFullName:work@oh_mux9.sel3 |vpiNet: \_logic_net: (work@oh_mux9.sel2), line:16:16, endln:16:20 |vpiParent: - \_module: work@oh_mux9 (work@oh_mux9), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux9.v, line:8:1, endln:41:10 + \_module_inst: work@oh_mux9 (work@oh_mux9), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux9.v, line:8:1, endln:41:10 |vpiName:sel2 |vpiFullName:work@oh_mux9.sel2 |vpiNet: \_logic_net: (work@oh_mux9.sel1), line:17:16, endln:17:20 |vpiParent: - \_module: work@oh_mux9 (work@oh_mux9), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux9.v, line:8:1, endln:41:10 + \_module_inst: work@oh_mux9 (work@oh_mux9), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux9.v, line:8:1, endln:41:10 |vpiName:sel1 |vpiFullName:work@oh_mux9.sel1 |vpiNet: \_logic_net: (work@oh_mux9.sel0), line:18:16, endln:18:20 |vpiParent: - \_module: work@oh_mux9 (work@oh_mux9), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux9.v, line:8:1, endln:41:10 + \_module_inst: work@oh_mux9 (work@oh_mux9), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux9.v, line:8:1, endln:41:10 |vpiName:sel0 |vpiFullName:work@oh_mux9.sel0 |vpiNet: \_logic_net: (work@oh_mux9.in8), line:19:20, endln:19:23 |vpiParent: - \_module: work@oh_mux9 (work@oh_mux9), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux9.v, line:8:1, endln:41:10 + \_module_inst: work@oh_mux9 (work@oh_mux9), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux9.v, line:8:1, endln:41:10 |vpiName:in8 |vpiFullName:work@oh_mux9.in8 |vpiNet: \_logic_net: (work@oh_mux9.in7), line:20:20, endln:20:23 |vpiParent: - \_module: work@oh_mux9 (work@oh_mux9), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux9.v, line:8:1, endln:41:10 + \_module_inst: work@oh_mux9 (work@oh_mux9), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux9.v, line:8:1, endln:41:10 |vpiName:in7 |vpiFullName:work@oh_mux9.in7 |vpiNet: \_logic_net: (work@oh_mux9.in6), line:21:20, endln:21:23 |vpiParent: - \_module: work@oh_mux9 (work@oh_mux9), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux9.v, line:8:1, endln:41:10 + \_module_inst: work@oh_mux9 (work@oh_mux9), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux9.v, line:8:1, endln:41:10 |vpiName:in6 |vpiFullName:work@oh_mux9.in6 |vpiNet: \_logic_net: (work@oh_mux9.in5), line:22:20, endln:22:23 |vpiParent: - \_module: work@oh_mux9 (work@oh_mux9), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux9.v, line:8:1, endln:41:10 + \_module_inst: work@oh_mux9 (work@oh_mux9), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux9.v, line:8:1, endln:41:10 |vpiName:in5 |vpiFullName:work@oh_mux9.in5 |vpiNet: \_logic_net: (work@oh_mux9.in4), line:23:20, endln:23:23 |vpiParent: - \_module: work@oh_mux9 (work@oh_mux9), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux9.v, line:8:1, endln:41:10 + \_module_inst: work@oh_mux9 (work@oh_mux9), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux9.v, line:8:1, endln:41:10 |vpiName:in4 |vpiFullName:work@oh_mux9.in4 |vpiNet: \_logic_net: (work@oh_mux9.in3), line:24:20, endln:24:23 |vpiParent: - \_module: work@oh_mux9 (work@oh_mux9), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux9.v, line:8:1, endln:41:10 + \_module_inst: work@oh_mux9 (work@oh_mux9), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux9.v, line:8:1, endln:41:10 |vpiName:in3 |vpiFullName:work@oh_mux9.in3 |vpiNet: \_logic_net: (work@oh_mux9.in2), line:25:20, endln:25:23 |vpiParent: - \_module: work@oh_mux9 (work@oh_mux9), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux9.v, line:8:1, endln:41:10 + \_module_inst: work@oh_mux9 (work@oh_mux9), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux9.v, line:8:1, endln:41:10 |vpiName:in2 |vpiFullName:work@oh_mux9.in2 |vpiNet: \_logic_net: (work@oh_mux9.in1), line:26:20, endln:26:23 |vpiParent: - \_module: work@oh_mux9 (work@oh_mux9), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux9.v, line:8:1, endln:41:10 + \_module_inst: work@oh_mux9 (work@oh_mux9), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux9.v, line:8:1, endln:41:10 |vpiName:in1 |vpiFullName:work@oh_mux9.in1 |vpiNet: \_logic_net: (work@oh_mux9.in0), line:27:20, endln:27:23 |vpiParent: - \_module: work@oh_mux9 (work@oh_mux9), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux9.v, line:8:1, endln:41:10 + \_module_inst: work@oh_mux9 (work@oh_mux9), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux9.v, line:8:1, endln:41:10 |vpiName:in0 |vpiFullName:work@oh_mux9.in0 |vpiNet: \_logic_net: (work@oh_mux9.out), line:28:20, endln:28:23 |vpiParent: - \_module: work@oh_mux9 (work@oh_mux9), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux9.v, line:8:1, endln:41:10 + \_module_inst: work@oh_mux9 (work@oh_mux9), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux9.v, line:8:1, endln:41:10 |vpiName:out |vpiFullName:work@oh_mux9.out |vpiPort: \_port: (sel8), line:10:16, endln:10:20 |vpiParent: - \_module: work@oh_mux9 (work@oh_mux9), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux9.v, line:8:1, endln:41:10 + \_module_inst: work@oh_mux9 (work@oh_mux9), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux9.v, line:8:1, endln:41:10 |vpiName:sel8 |vpiDirection:1 |vpiLowConn: @@ -38416,7 +38416,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (sel7), line:11:16, endln:11:20 |vpiParent: - \_module: work@oh_mux9 (work@oh_mux9), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux9.v, line:8:1, endln:41:10 + \_module_inst: work@oh_mux9 (work@oh_mux9), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux9.v, line:8:1, endln:41:10 |vpiName:sel7 |vpiDirection:1 |vpiLowConn: @@ -38428,7 +38428,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (sel6), line:12:16, endln:12:20 |vpiParent: - \_module: work@oh_mux9 (work@oh_mux9), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux9.v, line:8:1, endln:41:10 + \_module_inst: work@oh_mux9 (work@oh_mux9), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux9.v, line:8:1, endln:41:10 |vpiName:sel6 |vpiDirection:1 |vpiLowConn: @@ -38440,7 +38440,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (sel5), line:13:16, endln:13:20 |vpiParent: - \_module: work@oh_mux9 (work@oh_mux9), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux9.v, line:8:1, endln:41:10 + \_module_inst: work@oh_mux9 (work@oh_mux9), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux9.v, line:8:1, endln:41:10 |vpiName:sel5 |vpiDirection:1 |vpiLowConn: @@ -38452,7 +38452,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (sel4), line:14:16, endln:14:20 |vpiParent: - \_module: work@oh_mux9 (work@oh_mux9), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux9.v, line:8:1, endln:41:10 + \_module_inst: work@oh_mux9 (work@oh_mux9), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux9.v, line:8:1, endln:41:10 |vpiName:sel4 |vpiDirection:1 |vpiLowConn: @@ -38464,7 +38464,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (sel3), line:15:16, endln:15:20 |vpiParent: - \_module: work@oh_mux9 (work@oh_mux9), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux9.v, line:8:1, endln:41:10 + \_module_inst: work@oh_mux9 (work@oh_mux9), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux9.v, line:8:1, endln:41:10 |vpiName:sel3 |vpiDirection:1 |vpiLowConn: @@ -38476,7 +38476,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (sel2), line:16:16, endln:16:20 |vpiParent: - \_module: work@oh_mux9 (work@oh_mux9), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux9.v, line:8:1, endln:41:10 + \_module_inst: work@oh_mux9 (work@oh_mux9), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux9.v, line:8:1, endln:41:10 |vpiName:sel2 |vpiDirection:1 |vpiLowConn: @@ -38488,7 +38488,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (sel1), line:17:16, endln:17:20 |vpiParent: - \_module: work@oh_mux9 (work@oh_mux9), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux9.v, line:8:1, endln:41:10 + \_module_inst: work@oh_mux9 (work@oh_mux9), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux9.v, line:8:1, endln:41:10 |vpiName:sel1 |vpiDirection:1 |vpiLowConn: @@ -38500,7 +38500,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (sel0), line:18:16, endln:18:20 |vpiParent: - \_module: work@oh_mux9 (work@oh_mux9), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux9.v, line:8:1, endln:41:10 + \_module_inst: work@oh_mux9 (work@oh_mux9), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux9.v, line:8:1, endln:41:10 |vpiName:sel0 |vpiDirection:1 |vpiLowConn: @@ -38512,7 +38512,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (in8), line:19:20, endln:19:23 |vpiParent: - \_module: work@oh_mux9 (work@oh_mux9), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux9.v, line:8:1, endln:41:10 + \_module_inst: work@oh_mux9 (work@oh_mux9), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux9.v, line:8:1, endln:41:10 |vpiName:in8 |vpiDirection:1 |vpiLowConn: @@ -38552,7 +38552,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (in7), line:20:20, endln:20:23 |vpiParent: - \_module: work@oh_mux9 (work@oh_mux9), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux9.v, line:8:1, endln:41:10 + \_module_inst: work@oh_mux9 (work@oh_mux9), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux9.v, line:8:1, endln:41:10 |vpiName:in7 |vpiDirection:1 |vpiLowConn: @@ -38592,7 +38592,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (in6), line:21:20, endln:21:23 |vpiParent: - \_module: work@oh_mux9 (work@oh_mux9), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux9.v, line:8:1, endln:41:10 + \_module_inst: work@oh_mux9 (work@oh_mux9), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux9.v, line:8:1, endln:41:10 |vpiName:in6 |vpiDirection:1 |vpiLowConn: @@ -38632,7 +38632,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (in5), line:22:20, endln:22:23 |vpiParent: - \_module: work@oh_mux9 (work@oh_mux9), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux9.v, line:8:1, endln:41:10 + \_module_inst: work@oh_mux9 (work@oh_mux9), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux9.v, line:8:1, endln:41:10 |vpiName:in5 |vpiDirection:1 |vpiLowConn: @@ -38672,7 +38672,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (in4), line:23:20, endln:23:23 |vpiParent: - \_module: work@oh_mux9 (work@oh_mux9), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux9.v, line:8:1, endln:41:10 + \_module_inst: work@oh_mux9 (work@oh_mux9), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux9.v, line:8:1, endln:41:10 |vpiName:in4 |vpiDirection:1 |vpiLowConn: @@ -38712,7 +38712,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (in3), line:24:20, endln:24:23 |vpiParent: - \_module: work@oh_mux9 (work@oh_mux9), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux9.v, line:8:1, endln:41:10 + \_module_inst: work@oh_mux9 (work@oh_mux9), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux9.v, line:8:1, endln:41:10 |vpiName:in3 |vpiDirection:1 |vpiLowConn: @@ -38752,7 +38752,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (in2), line:25:20, endln:25:23 |vpiParent: - \_module: work@oh_mux9 (work@oh_mux9), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux9.v, line:8:1, endln:41:10 + \_module_inst: work@oh_mux9 (work@oh_mux9), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux9.v, line:8:1, endln:41:10 |vpiName:in2 |vpiDirection:1 |vpiLowConn: @@ -38792,7 +38792,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (in1), line:26:20, endln:26:23 |vpiParent: - \_module: work@oh_mux9 (work@oh_mux9), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux9.v, line:8:1, endln:41:10 + \_module_inst: work@oh_mux9 (work@oh_mux9), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux9.v, line:8:1, endln:41:10 |vpiName:in1 |vpiDirection:1 |vpiLowConn: @@ -38832,7 +38832,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (in0), line:27:20, endln:27:23 |vpiParent: - \_module: work@oh_mux9 (work@oh_mux9), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux9.v, line:8:1, endln:41:10 + \_module_inst: work@oh_mux9 (work@oh_mux9), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux9.v, line:8:1, endln:41:10 |vpiName:in0 |vpiDirection:1 |vpiLowConn: @@ -38872,7 +38872,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (out), line:28:20, endln:28:23 |vpiParent: - \_module: work@oh_mux9 (work@oh_mux9), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux9.v, line:8:1, endln:41:10 + \_module_inst: work@oh_mux9 (work@oh_mux9), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux9.v, line:8:1, endln:41:10 |vpiName:out |vpiDirection:2 |vpiLowConn: @@ -38912,7 +38912,7 @@ design: (work@oh_fifo_async) |vpiContAssign: \_cont_assign: , line:31:11, endln:39:30 |vpiParent: - \_module: work@oh_mux9 (work@oh_mux9), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux9.v, line:8:1, endln:41:10 + \_module_inst: work@oh_mux9 (work@oh_mux9), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux9.v, line:8:1, endln:41:10 |vpiRhs: \_operation: , line:31:25, endln:39:29 |vpiParent: @@ -39541,14 +39541,14 @@ design: (work@oh_fifo_async) |UINT:0 |vpiConstType:9 |uhdmallModules: -\_module: work@oh_mx2 (work@oh_mx2), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mx2.v, line:8:1, endln:18:10 +\_module_inst: work@oh_mx2 (work@oh_mx2), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mx2.v, line:8:1, endln:18:10 |vpiParent: \_design: (work@oh_fifo_async) |vpiFullName:work@oh_mx2 |vpiParameter: \_parameter: (work@oh_mx2.DW), line:8:27, endln:8:29 |vpiParent: - \_module: work@oh_mx2 (work@oh_mx2), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mx2.v, line:8:1, endln:18:10 + \_module_inst: work@oh_mx2 (work@oh_mx2), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mx2.v, line:8:1, endln:18:10 |UINT:1 |vpiTypespec: \_int_typespec: @@ -39557,7 +39557,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:8:27, endln:8:33 |vpiParent: - \_module: work@oh_mx2 (work@oh_mx2), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mx2.v, line:8:1, endln:18:10 + \_module_inst: work@oh_mx2 (work@oh_mx2), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mx2.v, line:8:1, endln:18:10 |vpiRhs: \_constant: , line:8:32, endln:8:33 |vpiDecompile:1 @@ -39573,31 +39573,31 @@ design: (work@oh_fifo_async) |vpiNet: \_logic_net: (work@oh_mx2.d0), line:10:21, endln:10:23 |vpiParent: - \_module: work@oh_mx2 (work@oh_mx2), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mx2.v, line:8:1, endln:18:10 + \_module_inst: work@oh_mx2 (work@oh_mx2), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mx2.v, line:8:1, endln:18:10 |vpiName:d0 |vpiFullName:work@oh_mx2.d0 |vpiNet: \_logic_net: (work@oh_mx2.d1), line:11:21, endln:11:23 |vpiParent: - \_module: work@oh_mx2 (work@oh_mx2), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mx2.v, line:8:1, endln:18:10 + \_module_inst: work@oh_mx2 (work@oh_mx2), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mx2.v, line:8:1, endln:18:10 |vpiName:d1 |vpiFullName:work@oh_mx2.d1 |vpiNet: \_logic_net: (work@oh_mx2.s), line:12:21, endln:12:22 |vpiParent: - \_module: work@oh_mx2 (work@oh_mx2), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mx2.v, line:8:1, endln:18:10 + \_module_inst: work@oh_mx2 (work@oh_mx2), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mx2.v, line:8:1, endln:18:10 |vpiName:s |vpiFullName:work@oh_mx2.s |vpiNet: \_logic_net: (work@oh_mx2.z), line:13:21, endln:13:22 |vpiParent: - \_module: work@oh_mx2 (work@oh_mx2), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mx2.v, line:8:1, endln:18:10 + \_module_inst: work@oh_mx2 (work@oh_mx2), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mx2.v, line:8:1, endln:18:10 |vpiName:z |vpiFullName:work@oh_mx2.z |vpiPort: \_port: (d0), line:10:21, endln:10:23 |vpiParent: - \_module: work@oh_mx2 (work@oh_mx2), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mx2.v, line:8:1, endln:18:10 + \_module_inst: work@oh_mx2 (work@oh_mx2), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mx2.v, line:8:1, endln:18:10 |vpiName:d0 |vpiDirection:1 |vpiLowConn: @@ -39637,7 +39637,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (d1), line:11:21, endln:11:23 |vpiParent: - \_module: work@oh_mx2 (work@oh_mx2), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mx2.v, line:8:1, endln:18:10 + \_module_inst: work@oh_mx2 (work@oh_mx2), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mx2.v, line:8:1, endln:18:10 |vpiName:d1 |vpiDirection:1 |vpiLowConn: @@ -39677,7 +39677,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (s), line:12:21, endln:12:22 |vpiParent: - \_module: work@oh_mx2 (work@oh_mx2), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mx2.v, line:8:1, endln:18:10 + \_module_inst: work@oh_mx2 (work@oh_mx2), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mx2.v, line:8:1, endln:18:10 |vpiName:s |vpiDirection:1 |vpiLowConn: @@ -39717,7 +39717,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (z), line:13:21, endln:13:22 |vpiParent: - \_module: work@oh_mx2 (work@oh_mx2), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mx2.v, line:8:1, endln:18:10 + \_module_inst: work@oh_mx2 (work@oh_mx2), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mx2.v, line:8:1, endln:18:10 |vpiName:z |vpiDirection:2 |vpiLowConn: @@ -39757,7 +39757,7 @@ design: (work@oh_fifo_async) |vpiContAssign: \_cont_assign: , line:16:11, endln:16:35 |vpiParent: - \_module: work@oh_mx2 (work@oh_mx2), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mx2.v, line:8:1, endln:18:10 + \_module_inst: work@oh_mx2 (work@oh_mx2), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mx2.v, line:8:1, endln:18:10 |vpiRhs: \_operation: , line:16:15, endln:16:35 |vpiParent: @@ -39809,14 +39809,14 @@ design: (work@oh_fifo_async) |vpiName:z |vpiFullName:work@oh_mx2.z |uhdmallModules: -\_module: work@oh_mx3 (work@oh_mx3), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mx3.v, line:8:1, endln:22:10 +\_module_inst: work@oh_mx3 (work@oh_mx3), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mx3.v, line:8:1, endln:22:10 |vpiParent: \_design: (work@oh_fifo_async) |vpiFullName:work@oh_mx3 |vpiParameter: \_parameter: (work@oh_mx3.DW), line:8:27, endln:8:29 |vpiParent: - \_module: work@oh_mx3 (work@oh_mx3), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mx3.v, line:8:1, endln:22:10 + \_module_inst: work@oh_mx3 (work@oh_mx3), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mx3.v, line:8:1, endln:22:10 |UINT:1 |vpiTypespec: \_int_typespec: @@ -39825,7 +39825,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:8:27, endln:8:33 |vpiParent: - \_module: work@oh_mx3 (work@oh_mx3), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mx3.v, line:8:1, endln:22:10 + \_module_inst: work@oh_mx3 (work@oh_mx3), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mx3.v, line:8:1, endln:22:10 |vpiRhs: \_constant: , line:8:32, endln:8:33 |vpiDecompile:1 @@ -39841,43 +39841,43 @@ design: (work@oh_fifo_async) |vpiNet: \_logic_net: (work@oh_mx3.d0), line:10:21, endln:10:23 |vpiParent: - \_module: work@oh_mx3 (work@oh_mx3), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mx3.v, line:8:1, endln:22:10 + \_module_inst: work@oh_mx3 (work@oh_mx3), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mx3.v, line:8:1, endln:22:10 |vpiName:d0 |vpiFullName:work@oh_mx3.d0 |vpiNet: \_logic_net: (work@oh_mx3.d1), line:11:21, endln:11:23 |vpiParent: - \_module: work@oh_mx3 (work@oh_mx3), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mx3.v, line:8:1, endln:22:10 + \_module_inst: work@oh_mx3 (work@oh_mx3), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mx3.v, line:8:1, endln:22:10 |vpiName:d1 |vpiFullName:work@oh_mx3.d1 |vpiNet: \_logic_net: (work@oh_mx3.d2), line:12:21, endln:12:23 |vpiParent: - \_module: work@oh_mx3 (work@oh_mx3), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mx3.v, line:8:1, endln:22:10 + \_module_inst: work@oh_mx3 (work@oh_mx3), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mx3.v, line:8:1, endln:22:10 |vpiName:d2 |vpiFullName:work@oh_mx3.d2 |vpiNet: \_logic_net: (work@oh_mx3.s0), line:13:21, endln:13:23 |vpiParent: - \_module: work@oh_mx3 (work@oh_mx3), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mx3.v, line:8:1, endln:22:10 + \_module_inst: work@oh_mx3 (work@oh_mx3), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mx3.v, line:8:1, endln:22:10 |vpiName:s0 |vpiFullName:work@oh_mx3.s0 |vpiNet: \_logic_net: (work@oh_mx3.s1), line:14:21, endln:14:23 |vpiParent: - \_module: work@oh_mx3 (work@oh_mx3), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mx3.v, line:8:1, endln:22:10 + \_module_inst: work@oh_mx3 (work@oh_mx3), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mx3.v, line:8:1, endln:22:10 |vpiName:s1 |vpiFullName:work@oh_mx3.s1 |vpiNet: \_logic_net: (work@oh_mx3.z), line:15:21, endln:15:22 |vpiParent: - \_module: work@oh_mx3 (work@oh_mx3), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mx3.v, line:8:1, endln:22:10 + \_module_inst: work@oh_mx3 (work@oh_mx3), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mx3.v, line:8:1, endln:22:10 |vpiName:z |vpiFullName:work@oh_mx3.z |vpiPort: \_port: (d0), line:10:21, endln:10:23 |vpiParent: - \_module: work@oh_mx3 (work@oh_mx3), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mx3.v, line:8:1, endln:22:10 + \_module_inst: work@oh_mx3 (work@oh_mx3), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mx3.v, line:8:1, endln:22:10 |vpiName:d0 |vpiDirection:1 |vpiLowConn: @@ -39917,7 +39917,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (d1), line:11:21, endln:11:23 |vpiParent: - \_module: work@oh_mx3 (work@oh_mx3), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mx3.v, line:8:1, endln:22:10 + \_module_inst: work@oh_mx3 (work@oh_mx3), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mx3.v, line:8:1, endln:22:10 |vpiName:d1 |vpiDirection:1 |vpiLowConn: @@ -39957,7 +39957,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (d2), line:12:21, endln:12:23 |vpiParent: - \_module: work@oh_mx3 (work@oh_mx3), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mx3.v, line:8:1, endln:22:10 + \_module_inst: work@oh_mx3 (work@oh_mx3), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mx3.v, line:8:1, endln:22:10 |vpiName:d2 |vpiDirection:1 |vpiLowConn: @@ -39997,7 +39997,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (s0), line:13:21, endln:13:23 |vpiParent: - \_module: work@oh_mx3 (work@oh_mx3), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mx3.v, line:8:1, endln:22:10 + \_module_inst: work@oh_mx3 (work@oh_mx3), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mx3.v, line:8:1, endln:22:10 |vpiName:s0 |vpiDirection:1 |vpiLowConn: @@ -40037,7 +40037,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (s1), line:14:21, endln:14:23 |vpiParent: - \_module: work@oh_mx3 (work@oh_mx3), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mx3.v, line:8:1, endln:22:10 + \_module_inst: work@oh_mx3 (work@oh_mx3), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mx3.v, line:8:1, endln:22:10 |vpiName:s1 |vpiDirection:1 |vpiLowConn: @@ -40077,7 +40077,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (z), line:15:21, endln:15:22 |vpiParent: - \_module: work@oh_mx3 (work@oh_mx3), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mx3.v, line:8:1, endln:22:10 + \_module_inst: work@oh_mx3 (work@oh_mx3), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mx3.v, line:8:1, endln:22:10 |vpiName:z |vpiDirection:2 |vpiLowConn: @@ -40117,7 +40117,7 @@ design: (work@oh_fifo_async) |vpiContAssign: \_cont_assign: , line:18:11, endln:20:17 |vpiParent: - \_module: work@oh_mx3 (work@oh_mx3), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mx3.v, line:8:1, endln:22:10 + \_module_inst: work@oh_mx3 (work@oh_mx3), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mx3.v, line:8:1, endln:22:10 |vpiRhs: \_operation: , line:18:15, endln:20:17 |vpiParent: @@ -40223,14 +40223,14 @@ design: (work@oh_fifo_async) |vpiName:z |vpiFullName:work@oh_mx3.z |uhdmallModules: -\_module: work@oh_mx4 (work@oh_mx4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mx4.v, line:8:1, endln:24:10 +\_module_inst: work@oh_mx4 (work@oh_mx4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mx4.v, line:8:1, endln:24:10 |vpiParent: \_design: (work@oh_fifo_async) |vpiFullName:work@oh_mx4 |vpiParameter: \_parameter: (work@oh_mx4.DW), line:8:27, endln:8:29 |vpiParent: - \_module: work@oh_mx4 (work@oh_mx4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mx4.v, line:8:1, endln:24:10 + \_module_inst: work@oh_mx4 (work@oh_mx4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mx4.v, line:8:1, endln:24:10 |UINT:1 |vpiTypespec: \_int_typespec: @@ -40239,7 +40239,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:8:27, endln:8:33 |vpiParent: - \_module: work@oh_mx4 (work@oh_mx4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mx4.v, line:8:1, endln:24:10 + \_module_inst: work@oh_mx4 (work@oh_mx4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mx4.v, line:8:1, endln:24:10 |vpiRhs: \_constant: , line:8:32, endln:8:33 |vpiDecompile:1 @@ -40255,49 +40255,49 @@ design: (work@oh_fifo_async) |vpiNet: \_logic_net: (work@oh_mx4.d0), line:10:21, endln:10:23 |vpiParent: - \_module: work@oh_mx4 (work@oh_mx4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mx4.v, line:8:1, endln:24:10 + \_module_inst: work@oh_mx4 (work@oh_mx4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mx4.v, line:8:1, endln:24:10 |vpiName:d0 |vpiFullName:work@oh_mx4.d0 |vpiNet: \_logic_net: (work@oh_mx4.d1), line:11:21, endln:11:23 |vpiParent: - \_module: work@oh_mx4 (work@oh_mx4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mx4.v, line:8:1, endln:24:10 + \_module_inst: work@oh_mx4 (work@oh_mx4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mx4.v, line:8:1, endln:24:10 |vpiName:d1 |vpiFullName:work@oh_mx4.d1 |vpiNet: \_logic_net: (work@oh_mx4.d2), line:12:21, endln:12:23 |vpiParent: - \_module: work@oh_mx4 (work@oh_mx4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mx4.v, line:8:1, endln:24:10 + \_module_inst: work@oh_mx4 (work@oh_mx4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mx4.v, line:8:1, endln:24:10 |vpiName:d2 |vpiFullName:work@oh_mx4.d2 |vpiNet: \_logic_net: (work@oh_mx4.d3), line:13:21, endln:13:23 |vpiParent: - \_module: work@oh_mx4 (work@oh_mx4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mx4.v, line:8:1, endln:24:10 + \_module_inst: work@oh_mx4 (work@oh_mx4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mx4.v, line:8:1, endln:24:10 |vpiName:d3 |vpiFullName:work@oh_mx4.d3 |vpiNet: \_logic_net: (work@oh_mx4.s0), line:14:21, endln:14:23 |vpiParent: - \_module: work@oh_mx4 (work@oh_mx4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mx4.v, line:8:1, endln:24:10 + \_module_inst: work@oh_mx4 (work@oh_mx4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mx4.v, line:8:1, endln:24:10 |vpiName:s0 |vpiFullName:work@oh_mx4.s0 |vpiNet: \_logic_net: (work@oh_mx4.s1), line:15:21, endln:15:23 |vpiParent: - \_module: work@oh_mx4 (work@oh_mx4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mx4.v, line:8:1, endln:24:10 + \_module_inst: work@oh_mx4 (work@oh_mx4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mx4.v, line:8:1, endln:24:10 |vpiName:s1 |vpiFullName:work@oh_mx4.s1 |vpiNet: \_logic_net: (work@oh_mx4.z), line:16:21, endln:16:22 |vpiParent: - \_module: work@oh_mx4 (work@oh_mx4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mx4.v, line:8:1, endln:24:10 + \_module_inst: work@oh_mx4 (work@oh_mx4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mx4.v, line:8:1, endln:24:10 |vpiName:z |vpiFullName:work@oh_mx4.z |vpiPort: \_port: (d0), line:10:21, endln:10:23 |vpiParent: - \_module: work@oh_mx4 (work@oh_mx4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mx4.v, line:8:1, endln:24:10 + \_module_inst: work@oh_mx4 (work@oh_mx4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mx4.v, line:8:1, endln:24:10 |vpiName:d0 |vpiDirection:1 |vpiLowConn: @@ -40337,7 +40337,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (d1), line:11:21, endln:11:23 |vpiParent: - \_module: work@oh_mx4 (work@oh_mx4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mx4.v, line:8:1, endln:24:10 + \_module_inst: work@oh_mx4 (work@oh_mx4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mx4.v, line:8:1, endln:24:10 |vpiName:d1 |vpiDirection:1 |vpiLowConn: @@ -40377,7 +40377,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (d2), line:12:21, endln:12:23 |vpiParent: - \_module: work@oh_mx4 (work@oh_mx4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mx4.v, line:8:1, endln:24:10 + \_module_inst: work@oh_mx4 (work@oh_mx4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mx4.v, line:8:1, endln:24:10 |vpiName:d2 |vpiDirection:1 |vpiLowConn: @@ -40417,7 +40417,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (d3), line:13:21, endln:13:23 |vpiParent: - \_module: work@oh_mx4 (work@oh_mx4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mx4.v, line:8:1, endln:24:10 + \_module_inst: work@oh_mx4 (work@oh_mx4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mx4.v, line:8:1, endln:24:10 |vpiName:d3 |vpiDirection:1 |vpiLowConn: @@ -40457,7 +40457,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (s0), line:14:21, endln:14:23 |vpiParent: - \_module: work@oh_mx4 (work@oh_mx4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mx4.v, line:8:1, endln:24:10 + \_module_inst: work@oh_mx4 (work@oh_mx4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mx4.v, line:8:1, endln:24:10 |vpiName:s0 |vpiDirection:1 |vpiLowConn: @@ -40497,7 +40497,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (s1), line:15:21, endln:15:23 |vpiParent: - \_module: work@oh_mx4 (work@oh_mx4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mx4.v, line:8:1, endln:24:10 + \_module_inst: work@oh_mx4 (work@oh_mx4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mx4.v, line:8:1, endln:24:10 |vpiName:s1 |vpiDirection:1 |vpiLowConn: @@ -40537,7 +40537,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (z), line:16:21, endln:16:22 |vpiParent: - \_module: work@oh_mx4 (work@oh_mx4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mx4.v, line:8:1, endln:24:10 + \_module_inst: work@oh_mx4 (work@oh_mx4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mx4.v, line:8:1, endln:24:10 |vpiName:z |vpiDirection:2 |vpiLowConn: @@ -40577,7 +40577,7 @@ design: (work@oh_fifo_async) |vpiContAssign: \_cont_assign: , line:19:11, endln:22:24 |vpiParent: - \_module: work@oh_mx4 (work@oh_mx4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mx4.v, line:8:1, endln:24:10 + \_module_inst: work@oh_mx4 (work@oh_mx4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mx4.v, line:8:1, endln:24:10 |vpiRhs: \_operation: , line:19:15, endln:22:24 |vpiParent: @@ -40732,14 +40732,14 @@ design: (work@oh_fifo_async) |vpiName:z |vpiFullName:work@oh_mx4.z |uhdmallModules: -\_module: work@oh_mxi2 (work@oh_mxi2), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mxi2.v, line:8:1, endln:18:10 +\_module_inst: work@oh_mxi2 (work@oh_mxi2), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mxi2.v, line:8:1, endln:18:10 |vpiParent: \_design: (work@oh_fifo_async) |vpiFullName:work@oh_mxi2 |vpiParameter: \_parameter: (work@oh_mxi2.DW), line:8:28, endln:8:30 |vpiParent: - \_module: work@oh_mxi2 (work@oh_mxi2), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mxi2.v, line:8:1, endln:18:10 + \_module_inst: work@oh_mxi2 (work@oh_mxi2), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mxi2.v, line:8:1, endln:18:10 |UINT:1 |vpiTypespec: \_int_typespec: @@ -40748,7 +40748,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:8:28, endln:8:34 |vpiParent: - \_module: work@oh_mxi2 (work@oh_mxi2), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mxi2.v, line:8:1, endln:18:10 + \_module_inst: work@oh_mxi2 (work@oh_mxi2), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mxi2.v, line:8:1, endln:18:10 |vpiRhs: \_constant: , line:8:33, endln:8:34 |vpiDecompile:1 @@ -40764,31 +40764,31 @@ design: (work@oh_fifo_async) |vpiNet: \_logic_net: (work@oh_mxi2.d0), line:10:21, endln:10:23 |vpiParent: - \_module: work@oh_mxi2 (work@oh_mxi2), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mxi2.v, line:8:1, endln:18:10 + \_module_inst: work@oh_mxi2 (work@oh_mxi2), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mxi2.v, line:8:1, endln:18:10 |vpiName:d0 |vpiFullName:work@oh_mxi2.d0 |vpiNet: \_logic_net: (work@oh_mxi2.d1), line:11:21, endln:11:23 |vpiParent: - \_module: work@oh_mxi2 (work@oh_mxi2), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mxi2.v, line:8:1, endln:18:10 + \_module_inst: work@oh_mxi2 (work@oh_mxi2), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mxi2.v, line:8:1, endln:18:10 |vpiName:d1 |vpiFullName:work@oh_mxi2.d1 |vpiNet: \_logic_net: (work@oh_mxi2.s), line:12:21, endln:12:22 |vpiParent: - \_module: work@oh_mxi2 (work@oh_mxi2), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mxi2.v, line:8:1, endln:18:10 + \_module_inst: work@oh_mxi2 (work@oh_mxi2), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mxi2.v, line:8:1, endln:18:10 |vpiName:s |vpiFullName:work@oh_mxi2.s |vpiNet: \_logic_net: (work@oh_mxi2.z), line:13:21, endln:13:22 |vpiParent: - \_module: work@oh_mxi2 (work@oh_mxi2), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mxi2.v, line:8:1, endln:18:10 + \_module_inst: work@oh_mxi2 (work@oh_mxi2), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mxi2.v, line:8:1, endln:18:10 |vpiName:z |vpiFullName:work@oh_mxi2.z |vpiPort: \_port: (d0), line:10:21, endln:10:23 |vpiParent: - \_module: work@oh_mxi2 (work@oh_mxi2), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mxi2.v, line:8:1, endln:18:10 + \_module_inst: work@oh_mxi2 (work@oh_mxi2), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mxi2.v, line:8:1, endln:18:10 |vpiName:d0 |vpiDirection:1 |vpiLowConn: @@ -40828,7 +40828,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (d1), line:11:21, endln:11:23 |vpiParent: - \_module: work@oh_mxi2 (work@oh_mxi2), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mxi2.v, line:8:1, endln:18:10 + \_module_inst: work@oh_mxi2 (work@oh_mxi2), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mxi2.v, line:8:1, endln:18:10 |vpiName:d1 |vpiDirection:1 |vpiLowConn: @@ -40868,7 +40868,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (s), line:12:21, endln:12:22 |vpiParent: - \_module: work@oh_mxi2 (work@oh_mxi2), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mxi2.v, line:8:1, endln:18:10 + \_module_inst: work@oh_mxi2 (work@oh_mxi2), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mxi2.v, line:8:1, endln:18:10 |vpiName:s |vpiDirection:1 |vpiLowConn: @@ -40908,7 +40908,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (z), line:13:21, endln:13:22 |vpiParent: - \_module: work@oh_mxi2 (work@oh_mxi2), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mxi2.v, line:8:1, endln:18:10 + \_module_inst: work@oh_mxi2 (work@oh_mxi2), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mxi2.v, line:8:1, endln:18:10 |vpiName:z |vpiDirection:2 |vpiLowConn: @@ -40948,7 +40948,7 @@ design: (work@oh_fifo_async) |vpiContAssign: \_cont_assign: , line:16:11, endln:16:38 |vpiParent: - \_module: work@oh_mxi2 (work@oh_mxi2), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mxi2.v, line:8:1, endln:18:10 + \_module_inst: work@oh_mxi2 (work@oh_mxi2), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mxi2.v, line:8:1, endln:18:10 |vpiRhs: \_operation: , line:16:15, endln:16:38 |vpiParent: @@ -41005,14 +41005,14 @@ design: (work@oh_fifo_async) |vpiName:z |vpiFullName:work@oh_mxi2.z |uhdmallModules: -\_module: work@oh_mxi3 (work@oh_mxi3), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mxi3.v, line:8:1, endln:22:10 +\_module_inst: work@oh_mxi3 (work@oh_mxi3), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mxi3.v, line:8:1, endln:22:10 |vpiParent: \_design: (work@oh_fifo_async) |vpiFullName:work@oh_mxi3 |vpiParameter: \_parameter: (work@oh_mxi3.DW), line:8:28, endln:8:30 |vpiParent: - \_module: work@oh_mxi3 (work@oh_mxi3), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mxi3.v, line:8:1, endln:22:10 + \_module_inst: work@oh_mxi3 (work@oh_mxi3), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mxi3.v, line:8:1, endln:22:10 |UINT:1 |vpiTypespec: \_int_typespec: @@ -41021,7 +41021,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:8:28, endln:8:34 |vpiParent: - \_module: work@oh_mxi3 (work@oh_mxi3), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mxi3.v, line:8:1, endln:22:10 + \_module_inst: work@oh_mxi3 (work@oh_mxi3), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mxi3.v, line:8:1, endln:22:10 |vpiRhs: \_constant: , line:8:33, endln:8:34 |vpiDecompile:1 @@ -41037,43 +41037,43 @@ design: (work@oh_fifo_async) |vpiNet: \_logic_net: (work@oh_mxi3.d0), line:10:21, endln:10:23 |vpiParent: - \_module: work@oh_mxi3 (work@oh_mxi3), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mxi3.v, line:8:1, endln:22:10 + \_module_inst: work@oh_mxi3 (work@oh_mxi3), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mxi3.v, line:8:1, endln:22:10 |vpiName:d0 |vpiFullName:work@oh_mxi3.d0 |vpiNet: \_logic_net: (work@oh_mxi3.d1), line:11:21, endln:11:23 |vpiParent: - \_module: work@oh_mxi3 (work@oh_mxi3), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mxi3.v, line:8:1, endln:22:10 + \_module_inst: work@oh_mxi3 (work@oh_mxi3), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mxi3.v, line:8:1, endln:22:10 |vpiName:d1 |vpiFullName:work@oh_mxi3.d1 |vpiNet: \_logic_net: (work@oh_mxi3.d2), line:12:21, endln:12:23 |vpiParent: - \_module: work@oh_mxi3 (work@oh_mxi3), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mxi3.v, line:8:1, endln:22:10 + \_module_inst: work@oh_mxi3 (work@oh_mxi3), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mxi3.v, line:8:1, endln:22:10 |vpiName:d2 |vpiFullName:work@oh_mxi3.d2 |vpiNet: \_logic_net: (work@oh_mxi3.s0), line:13:21, endln:13:23 |vpiParent: - \_module: work@oh_mxi3 (work@oh_mxi3), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mxi3.v, line:8:1, endln:22:10 + \_module_inst: work@oh_mxi3 (work@oh_mxi3), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mxi3.v, line:8:1, endln:22:10 |vpiName:s0 |vpiFullName:work@oh_mxi3.s0 |vpiNet: \_logic_net: (work@oh_mxi3.s1), line:14:21, endln:14:23 |vpiParent: - \_module: work@oh_mxi3 (work@oh_mxi3), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mxi3.v, line:8:1, endln:22:10 + \_module_inst: work@oh_mxi3 (work@oh_mxi3), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mxi3.v, line:8:1, endln:22:10 |vpiName:s1 |vpiFullName:work@oh_mxi3.s1 |vpiNet: \_logic_net: (work@oh_mxi3.z), line:15:21, endln:15:22 |vpiParent: - \_module: work@oh_mxi3 (work@oh_mxi3), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mxi3.v, line:8:1, endln:22:10 + \_module_inst: work@oh_mxi3 (work@oh_mxi3), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mxi3.v, line:8:1, endln:22:10 |vpiName:z |vpiFullName:work@oh_mxi3.z |vpiPort: \_port: (d0), line:10:21, endln:10:23 |vpiParent: - \_module: work@oh_mxi3 (work@oh_mxi3), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mxi3.v, line:8:1, endln:22:10 + \_module_inst: work@oh_mxi3 (work@oh_mxi3), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mxi3.v, line:8:1, endln:22:10 |vpiName:d0 |vpiDirection:1 |vpiLowConn: @@ -41113,7 +41113,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (d1), line:11:21, endln:11:23 |vpiParent: - \_module: work@oh_mxi3 (work@oh_mxi3), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mxi3.v, line:8:1, endln:22:10 + \_module_inst: work@oh_mxi3 (work@oh_mxi3), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mxi3.v, line:8:1, endln:22:10 |vpiName:d1 |vpiDirection:1 |vpiLowConn: @@ -41153,7 +41153,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (d2), line:12:21, endln:12:23 |vpiParent: - \_module: work@oh_mxi3 (work@oh_mxi3), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mxi3.v, line:8:1, endln:22:10 + \_module_inst: work@oh_mxi3 (work@oh_mxi3), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mxi3.v, line:8:1, endln:22:10 |vpiName:d2 |vpiDirection:1 |vpiLowConn: @@ -41193,7 +41193,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (s0), line:13:21, endln:13:23 |vpiParent: - \_module: work@oh_mxi3 (work@oh_mxi3), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mxi3.v, line:8:1, endln:22:10 + \_module_inst: work@oh_mxi3 (work@oh_mxi3), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mxi3.v, line:8:1, endln:22:10 |vpiName:s0 |vpiDirection:1 |vpiLowConn: @@ -41233,7 +41233,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (s1), line:14:21, endln:14:23 |vpiParent: - \_module: work@oh_mxi3 (work@oh_mxi3), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mxi3.v, line:8:1, endln:22:10 + \_module_inst: work@oh_mxi3 (work@oh_mxi3), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mxi3.v, line:8:1, endln:22:10 |vpiName:s1 |vpiDirection:1 |vpiLowConn: @@ -41273,7 +41273,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (z), line:15:21, endln:15:22 |vpiParent: - \_module: work@oh_mxi3 (work@oh_mxi3), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mxi3.v, line:8:1, endln:22:10 + \_module_inst: work@oh_mxi3 (work@oh_mxi3), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mxi3.v, line:8:1, endln:22:10 |vpiName:z |vpiDirection:2 |vpiLowConn: @@ -41313,7 +41313,7 @@ design: (work@oh_fifo_async) |vpiContAssign: \_cont_assign: , line:18:11, endln:20:13 |vpiParent: - \_module: work@oh_mxi3 (work@oh_mxi3), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mxi3.v, line:8:1, endln:22:10 + \_module_inst: work@oh_mxi3 (work@oh_mxi3), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mxi3.v, line:8:1, endln:22:10 |vpiRhs: \_operation: , line:18:15, endln:20:13 |vpiParent: @@ -41424,14 +41424,14 @@ design: (work@oh_fifo_async) |vpiName:z |vpiFullName:work@oh_mxi3.z |uhdmallModules: -\_module: work@oh_mxi4 (work@oh_mxi4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mxi4.v, line:8:1, endln:24:10 +\_module_inst: work@oh_mxi4 (work@oh_mxi4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mxi4.v, line:8:1, endln:24:10 |vpiParent: \_design: (work@oh_fifo_async) |vpiFullName:work@oh_mxi4 |vpiParameter: \_parameter: (work@oh_mxi4.DW), line:8:28, endln:8:30 |vpiParent: - \_module: work@oh_mxi4 (work@oh_mxi4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mxi4.v, line:8:1, endln:24:10 + \_module_inst: work@oh_mxi4 (work@oh_mxi4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mxi4.v, line:8:1, endln:24:10 |UINT:1 |vpiTypespec: \_int_typespec: @@ -41440,7 +41440,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:8:28, endln:8:34 |vpiParent: - \_module: work@oh_mxi4 (work@oh_mxi4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mxi4.v, line:8:1, endln:24:10 + \_module_inst: work@oh_mxi4 (work@oh_mxi4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mxi4.v, line:8:1, endln:24:10 |vpiRhs: \_constant: , line:8:33, endln:8:34 |vpiDecompile:1 @@ -41456,49 +41456,49 @@ design: (work@oh_fifo_async) |vpiNet: \_logic_net: (work@oh_mxi4.d0), line:10:21, endln:10:23 |vpiParent: - \_module: work@oh_mxi4 (work@oh_mxi4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mxi4.v, line:8:1, endln:24:10 + \_module_inst: work@oh_mxi4 (work@oh_mxi4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mxi4.v, line:8:1, endln:24:10 |vpiName:d0 |vpiFullName:work@oh_mxi4.d0 |vpiNet: \_logic_net: (work@oh_mxi4.d1), line:11:21, endln:11:23 |vpiParent: - \_module: work@oh_mxi4 (work@oh_mxi4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mxi4.v, line:8:1, endln:24:10 + \_module_inst: work@oh_mxi4 (work@oh_mxi4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mxi4.v, line:8:1, endln:24:10 |vpiName:d1 |vpiFullName:work@oh_mxi4.d1 |vpiNet: \_logic_net: (work@oh_mxi4.d2), line:12:21, endln:12:23 |vpiParent: - \_module: work@oh_mxi4 (work@oh_mxi4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mxi4.v, line:8:1, endln:24:10 + \_module_inst: work@oh_mxi4 (work@oh_mxi4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mxi4.v, line:8:1, endln:24:10 |vpiName:d2 |vpiFullName:work@oh_mxi4.d2 |vpiNet: \_logic_net: (work@oh_mxi4.d3), line:13:21, endln:13:23 |vpiParent: - \_module: work@oh_mxi4 (work@oh_mxi4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mxi4.v, line:8:1, endln:24:10 + \_module_inst: work@oh_mxi4 (work@oh_mxi4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mxi4.v, line:8:1, endln:24:10 |vpiName:d3 |vpiFullName:work@oh_mxi4.d3 |vpiNet: \_logic_net: (work@oh_mxi4.s0), line:14:21, endln:14:23 |vpiParent: - \_module: work@oh_mxi4 (work@oh_mxi4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mxi4.v, line:8:1, endln:24:10 + \_module_inst: work@oh_mxi4 (work@oh_mxi4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mxi4.v, line:8:1, endln:24:10 |vpiName:s0 |vpiFullName:work@oh_mxi4.s0 |vpiNet: \_logic_net: (work@oh_mxi4.s1), line:15:21, endln:15:23 |vpiParent: - \_module: work@oh_mxi4 (work@oh_mxi4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mxi4.v, line:8:1, endln:24:10 + \_module_inst: work@oh_mxi4 (work@oh_mxi4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mxi4.v, line:8:1, endln:24:10 |vpiName:s1 |vpiFullName:work@oh_mxi4.s1 |vpiNet: \_logic_net: (work@oh_mxi4.z), line:16:21, endln:16:22 |vpiParent: - \_module: work@oh_mxi4 (work@oh_mxi4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mxi4.v, line:8:1, endln:24:10 + \_module_inst: work@oh_mxi4 (work@oh_mxi4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mxi4.v, line:8:1, endln:24:10 |vpiName:z |vpiFullName:work@oh_mxi4.z |vpiPort: \_port: (d0), line:10:21, endln:10:23 |vpiParent: - \_module: work@oh_mxi4 (work@oh_mxi4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mxi4.v, line:8:1, endln:24:10 + \_module_inst: work@oh_mxi4 (work@oh_mxi4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mxi4.v, line:8:1, endln:24:10 |vpiName:d0 |vpiDirection:1 |vpiLowConn: @@ -41538,7 +41538,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (d1), line:11:21, endln:11:23 |vpiParent: - \_module: work@oh_mxi4 (work@oh_mxi4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mxi4.v, line:8:1, endln:24:10 + \_module_inst: work@oh_mxi4 (work@oh_mxi4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mxi4.v, line:8:1, endln:24:10 |vpiName:d1 |vpiDirection:1 |vpiLowConn: @@ -41578,7 +41578,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (d2), line:12:21, endln:12:23 |vpiParent: - \_module: work@oh_mxi4 (work@oh_mxi4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mxi4.v, line:8:1, endln:24:10 + \_module_inst: work@oh_mxi4 (work@oh_mxi4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mxi4.v, line:8:1, endln:24:10 |vpiName:d2 |vpiDirection:1 |vpiLowConn: @@ -41618,7 +41618,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (d3), line:13:21, endln:13:23 |vpiParent: - \_module: work@oh_mxi4 (work@oh_mxi4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mxi4.v, line:8:1, endln:24:10 + \_module_inst: work@oh_mxi4 (work@oh_mxi4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mxi4.v, line:8:1, endln:24:10 |vpiName:d3 |vpiDirection:1 |vpiLowConn: @@ -41658,7 +41658,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (s0), line:14:21, endln:14:23 |vpiParent: - \_module: work@oh_mxi4 (work@oh_mxi4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mxi4.v, line:8:1, endln:24:10 + \_module_inst: work@oh_mxi4 (work@oh_mxi4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mxi4.v, line:8:1, endln:24:10 |vpiName:s0 |vpiDirection:1 |vpiLowConn: @@ -41698,7 +41698,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (s1), line:15:21, endln:15:23 |vpiParent: - \_module: work@oh_mxi4 (work@oh_mxi4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mxi4.v, line:8:1, endln:24:10 + \_module_inst: work@oh_mxi4 (work@oh_mxi4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mxi4.v, line:8:1, endln:24:10 |vpiName:s1 |vpiDirection:1 |vpiLowConn: @@ -41738,7 +41738,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (z), line:16:21, endln:16:22 |vpiParent: - \_module: work@oh_mxi4 (work@oh_mxi4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mxi4.v, line:8:1, endln:24:10 + \_module_inst: work@oh_mxi4 (work@oh_mxi4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mxi4.v, line:8:1, endln:24:10 |vpiName:z |vpiDirection:2 |vpiLowConn: @@ -41778,7 +41778,7 @@ design: (work@oh_fifo_async) |vpiContAssign: \_cont_assign: , line:19:11, endln:22:20 |vpiParent: - \_module: work@oh_mxi4 (work@oh_mxi4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mxi4.v, line:8:1, endln:24:10 + \_module_inst: work@oh_mxi4 (work@oh_mxi4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mxi4.v, line:8:1, endln:24:10 |vpiRhs: \_operation: , line:19:15, endln:22:20 |vpiParent: @@ -41938,14 +41938,14 @@ design: (work@oh_fifo_async) |vpiName:z |vpiFullName:work@oh_mxi4.z |uhdmallModules: -\_module: work@oh_nand3 (work@oh_nand3), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_nand3.v, line:7:1, endln:17:10 +\_module_inst: work@oh_nand3 (work@oh_nand3), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_nand3.v, line:7:1, endln:17:10 |vpiParent: \_design: (work@oh_fifo_async) |vpiFullName:work@oh_nand3 |vpiParameter: \_parameter: (work@oh_nand3.DW), line:7:29, endln:7:31 |vpiParent: - \_module: work@oh_nand3 (work@oh_nand3), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_nand3.v, line:7:1, endln:17:10 + \_module_inst: work@oh_nand3 (work@oh_nand3), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_nand3.v, line:7:1, endln:17:10 |UINT:1 |vpiTypespec: \_int_typespec: @@ -41954,7 +41954,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:7:29, endln:7:35 |vpiParent: - \_module: work@oh_nand3 (work@oh_nand3), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_nand3.v, line:7:1, endln:17:10 + \_module_inst: work@oh_nand3 (work@oh_nand3), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_nand3.v, line:7:1, endln:17:10 |vpiRhs: \_constant: , line:7:34, endln:7:35 |vpiDecompile:1 @@ -41970,31 +41970,31 @@ design: (work@oh_fifo_async) |vpiNet: \_logic_net: (work@oh_nand3.a), line:9:21, endln:9:22 |vpiParent: - \_module: work@oh_nand3 (work@oh_nand3), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_nand3.v, line:7:1, endln:17:10 + \_module_inst: work@oh_nand3 (work@oh_nand3), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_nand3.v, line:7:1, endln:17:10 |vpiName:a |vpiFullName:work@oh_nand3.a |vpiNet: \_logic_net: (work@oh_nand3.b), line:10:21, endln:10:22 |vpiParent: - \_module: work@oh_nand3 (work@oh_nand3), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_nand3.v, line:7:1, endln:17:10 + \_module_inst: work@oh_nand3 (work@oh_nand3), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_nand3.v, line:7:1, endln:17:10 |vpiName:b |vpiFullName:work@oh_nand3.b |vpiNet: \_logic_net: (work@oh_nand3.c), line:11:21, endln:11:22 |vpiParent: - \_module: work@oh_nand3 (work@oh_nand3), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_nand3.v, line:7:1, endln:17:10 + \_module_inst: work@oh_nand3 (work@oh_nand3), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_nand3.v, line:7:1, endln:17:10 |vpiName:c |vpiFullName:work@oh_nand3.c |vpiNet: \_logic_net: (work@oh_nand3.z), line:12:21, endln:12:22 |vpiParent: - \_module: work@oh_nand3 (work@oh_nand3), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_nand3.v, line:7:1, endln:17:10 + \_module_inst: work@oh_nand3 (work@oh_nand3), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_nand3.v, line:7:1, endln:17:10 |vpiName:z |vpiFullName:work@oh_nand3.z |vpiPort: \_port: (a), line:9:21, endln:9:22 |vpiParent: - \_module: work@oh_nand3 (work@oh_nand3), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_nand3.v, line:7:1, endln:17:10 + \_module_inst: work@oh_nand3 (work@oh_nand3), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_nand3.v, line:7:1, endln:17:10 |vpiName:a |vpiDirection:1 |vpiLowConn: @@ -42034,7 +42034,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (b), line:10:21, endln:10:22 |vpiParent: - \_module: work@oh_nand3 (work@oh_nand3), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_nand3.v, line:7:1, endln:17:10 + \_module_inst: work@oh_nand3 (work@oh_nand3), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_nand3.v, line:7:1, endln:17:10 |vpiName:b |vpiDirection:1 |vpiLowConn: @@ -42074,7 +42074,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (c), line:11:21, endln:11:22 |vpiParent: - \_module: work@oh_nand3 (work@oh_nand3), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_nand3.v, line:7:1, endln:17:10 + \_module_inst: work@oh_nand3 (work@oh_nand3), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_nand3.v, line:7:1, endln:17:10 |vpiName:c |vpiDirection:1 |vpiLowConn: @@ -42114,7 +42114,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (z), line:12:21, endln:12:22 |vpiParent: - \_module: work@oh_nand3 (work@oh_nand3), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_nand3.v, line:7:1, endln:17:10 + \_module_inst: work@oh_nand3 (work@oh_nand3), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_nand3.v, line:7:1, endln:17:10 |vpiName:z |vpiDirection:2 |vpiLowConn: @@ -42154,7 +42154,7 @@ design: (work@oh_fifo_async) |vpiContAssign: \_cont_assign: , line:15:11, endln:15:27 |vpiParent: - \_module: work@oh_nand3 (work@oh_nand3), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_nand3.v, line:7:1, endln:17:10 + \_module_inst: work@oh_nand3 (work@oh_nand3), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_nand3.v, line:7:1, endln:17:10 |vpiRhs: \_operation: , line:15:15, endln:15:27 |vpiParent: @@ -42195,14 +42195,14 @@ design: (work@oh_fifo_async) |vpiName:z |vpiFullName:work@oh_nand3.z |uhdmallModules: -\_module: work@oh_nand4 (work@oh_nand4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_nand4.v, line:7:1, endln:18:10 +\_module_inst: work@oh_nand4 (work@oh_nand4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_nand4.v, line:7:1, endln:18:10 |vpiParent: \_design: (work@oh_fifo_async) |vpiFullName:work@oh_nand4 |vpiParameter: \_parameter: (work@oh_nand4.DW), line:7:29, endln:7:31 |vpiParent: - \_module: work@oh_nand4 (work@oh_nand4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_nand4.v, line:7:1, endln:18:10 + \_module_inst: work@oh_nand4 (work@oh_nand4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_nand4.v, line:7:1, endln:18:10 |UINT:1 |vpiTypespec: \_int_typespec: @@ -42211,7 +42211,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:7:29, endln:7:35 |vpiParent: - \_module: work@oh_nand4 (work@oh_nand4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_nand4.v, line:7:1, endln:18:10 + \_module_inst: work@oh_nand4 (work@oh_nand4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_nand4.v, line:7:1, endln:18:10 |vpiRhs: \_constant: , line:7:34, endln:7:35 |vpiDecompile:1 @@ -42227,37 +42227,37 @@ design: (work@oh_fifo_async) |vpiNet: \_logic_net: (work@oh_nand4.a), line:9:21, endln:9:22 |vpiParent: - \_module: work@oh_nand4 (work@oh_nand4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_nand4.v, line:7:1, endln:18:10 + \_module_inst: work@oh_nand4 (work@oh_nand4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_nand4.v, line:7:1, endln:18:10 |vpiName:a |vpiFullName:work@oh_nand4.a |vpiNet: \_logic_net: (work@oh_nand4.b), line:10:21, endln:10:22 |vpiParent: - \_module: work@oh_nand4 (work@oh_nand4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_nand4.v, line:7:1, endln:18:10 + \_module_inst: work@oh_nand4 (work@oh_nand4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_nand4.v, line:7:1, endln:18:10 |vpiName:b |vpiFullName:work@oh_nand4.b |vpiNet: \_logic_net: (work@oh_nand4.c), line:11:21, endln:11:22 |vpiParent: - \_module: work@oh_nand4 (work@oh_nand4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_nand4.v, line:7:1, endln:18:10 + \_module_inst: work@oh_nand4 (work@oh_nand4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_nand4.v, line:7:1, endln:18:10 |vpiName:c |vpiFullName:work@oh_nand4.c |vpiNet: \_logic_net: (work@oh_nand4.d), line:12:21, endln:12:22 |vpiParent: - \_module: work@oh_nand4 (work@oh_nand4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_nand4.v, line:7:1, endln:18:10 + \_module_inst: work@oh_nand4 (work@oh_nand4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_nand4.v, line:7:1, endln:18:10 |vpiName:d |vpiFullName:work@oh_nand4.d |vpiNet: \_logic_net: (work@oh_nand4.z), line:13:21, endln:13:22 |vpiParent: - \_module: work@oh_nand4 (work@oh_nand4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_nand4.v, line:7:1, endln:18:10 + \_module_inst: work@oh_nand4 (work@oh_nand4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_nand4.v, line:7:1, endln:18:10 |vpiName:z |vpiFullName:work@oh_nand4.z |vpiPort: \_port: (a), line:9:21, endln:9:22 |vpiParent: - \_module: work@oh_nand4 (work@oh_nand4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_nand4.v, line:7:1, endln:18:10 + \_module_inst: work@oh_nand4 (work@oh_nand4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_nand4.v, line:7:1, endln:18:10 |vpiName:a |vpiDirection:1 |vpiLowConn: @@ -42297,7 +42297,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (b), line:10:21, endln:10:22 |vpiParent: - \_module: work@oh_nand4 (work@oh_nand4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_nand4.v, line:7:1, endln:18:10 + \_module_inst: work@oh_nand4 (work@oh_nand4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_nand4.v, line:7:1, endln:18:10 |vpiName:b |vpiDirection:1 |vpiLowConn: @@ -42337,7 +42337,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (c), line:11:21, endln:11:22 |vpiParent: - \_module: work@oh_nand4 (work@oh_nand4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_nand4.v, line:7:1, endln:18:10 + \_module_inst: work@oh_nand4 (work@oh_nand4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_nand4.v, line:7:1, endln:18:10 |vpiName:c |vpiDirection:1 |vpiLowConn: @@ -42377,7 +42377,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (d), line:12:21, endln:12:22 |vpiParent: - \_module: work@oh_nand4 (work@oh_nand4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_nand4.v, line:7:1, endln:18:10 + \_module_inst: work@oh_nand4 (work@oh_nand4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_nand4.v, line:7:1, endln:18:10 |vpiName:d |vpiDirection:1 |vpiLowConn: @@ -42417,7 +42417,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (z), line:13:21, endln:13:22 |vpiParent: - \_module: work@oh_nand4 (work@oh_nand4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_nand4.v, line:7:1, endln:18:10 + \_module_inst: work@oh_nand4 (work@oh_nand4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_nand4.v, line:7:1, endln:18:10 |vpiName:z |vpiDirection:2 |vpiLowConn: @@ -42457,7 +42457,7 @@ design: (work@oh_fifo_async) |vpiContAssign: \_cont_assign: , line:16:11, endln:16:31 |vpiParent: - \_module: work@oh_nand4 (work@oh_nand4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_nand4.v, line:7:1, endln:18:10 + \_module_inst: work@oh_nand4 (work@oh_nand4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_nand4.v, line:7:1, endln:18:10 |vpiRhs: \_operation: , line:16:15, endln:16:31 |vpiParent: @@ -42509,14 +42509,14 @@ design: (work@oh_fifo_async) |vpiName:z |vpiFullName:work@oh_nand4.z |uhdmallModules: -\_module: work@oh_nor2 (work@oh_nor2), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_nor2.v, line:7:1, endln:16:10 +\_module_inst: work@oh_nor2 (work@oh_nor2), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_nor2.v, line:7:1, endln:16:10 |vpiParent: \_design: (work@oh_fifo_async) |vpiFullName:work@oh_nor2 |vpiParameter: \_parameter: (work@oh_nor2.DW), line:7:28, endln:7:30 |vpiParent: - \_module: work@oh_nor2 (work@oh_nor2), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_nor2.v, line:7:1, endln:16:10 + \_module_inst: work@oh_nor2 (work@oh_nor2), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_nor2.v, line:7:1, endln:16:10 |UINT:1 |vpiTypespec: \_int_typespec: @@ -42525,7 +42525,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:7:28, endln:7:34 |vpiParent: - \_module: work@oh_nor2 (work@oh_nor2), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_nor2.v, line:7:1, endln:16:10 + \_module_inst: work@oh_nor2 (work@oh_nor2), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_nor2.v, line:7:1, endln:16:10 |vpiRhs: \_constant: , line:7:33, endln:7:34 |vpiDecompile:1 @@ -42541,25 +42541,25 @@ design: (work@oh_fifo_async) |vpiNet: \_logic_net: (work@oh_nor2.a), line:9:21, endln:9:22 |vpiParent: - \_module: work@oh_nor2 (work@oh_nor2), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_nor2.v, line:7:1, endln:16:10 + \_module_inst: work@oh_nor2 (work@oh_nor2), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_nor2.v, line:7:1, endln:16:10 |vpiName:a |vpiFullName:work@oh_nor2.a |vpiNet: \_logic_net: (work@oh_nor2.b), line:10:21, endln:10:22 |vpiParent: - \_module: work@oh_nor2 (work@oh_nor2), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_nor2.v, line:7:1, endln:16:10 + \_module_inst: work@oh_nor2 (work@oh_nor2), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_nor2.v, line:7:1, endln:16:10 |vpiName:b |vpiFullName:work@oh_nor2.b |vpiNet: \_logic_net: (work@oh_nor2.z), line:11:21, endln:11:22 |vpiParent: - \_module: work@oh_nor2 (work@oh_nor2), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_nor2.v, line:7:1, endln:16:10 + \_module_inst: work@oh_nor2 (work@oh_nor2), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_nor2.v, line:7:1, endln:16:10 |vpiName:z |vpiFullName:work@oh_nor2.z |vpiPort: \_port: (a), line:9:21, endln:9:22 |vpiParent: - \_module: work@oh_nor2 (work@oh_nor2), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_nor2.v, line:7:1, endln:16:10 + \_module_inst: work@oh_nor2 (work@oh_nor2), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_nor2.v, line:7:1, endln:16:10 |vpiName:a |vpiDirection:1 |vpiLowConn: @@ -42599,7 +42599,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (b), line:10:21, endln:10:22 |vpiParent: - \_module: work@oh_nor2 (work@oh_nor2), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_nor2.v, line:7:1, endln:16:10 + \_module_inst: work@oh_nor2 (work@oh_nor2), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_nor2.v, line:7:1, endln:16:10 |vpiName:b |vpiDirection:1 |vpiLowConn: @@ -42639,7 +42639,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (z), line:11:21, endln:11:22 |vpiParent: - \_module: work@oh_nor2 (work@oh_nor2), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_nor2.v, line:7:1, endln:16:10 + \_module_inst: work@oh_nor2 (work@oh_nor2), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_nor2.v, line:7:1, endln:16:10 |vpiName:z |vpiDirection:2 |vpiLowConn: @@ -42679,7 +42679,7 @@ design: (work@oh_fifo_async) |vpiContAssign: \_cont_assign: , line:14:11, endln:14:23 |vpiParent: - \_module: work@oh_nor2 (work@oh_nor2), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_nor2.v, line:7:1, endln:16:10 + \_module_inst: work@oh_nor2 (work@oh_nor2), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_nor2.v, line:7:1, endln:16:10 |vpiRhs: \_operation: , line:14:15, endln:14:23 |vpiParent: @@ -42709,14 +42709,14 @@ design: (work@oh_fifo_async) |vpiName:z |vpiFullName:work@oh_nor2.z |uhdmallModules: -\_module: work@oh_nor3 (work@oh_nor3), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_nor3.v, line:7:1, endln:17:10 +\_module_inst: work@oh_nor3 (work@oh_nor3), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_nor3.v, line:7:1, endln:17:10 |vpiParent: \_design: (work@oh_fifo_async) |vpiFullName:work@oh_nor3 |vpiParameter: \_parameter: (work@oh_nor3.DW), line:7:28, endln:7:30 |vpiParent: - \_module: work@oh_nor3 (work@oh_nor3), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_nor3.v, line:7:1, endln:17:10 + \_module_inst: work@oh_nor3 (work@oh_nor3), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_nor3.v, line:7:1, endln:17:10 |UINT:1 |vpiTypespec: \_int_typespec: @@ -42725,7 +42725,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:7:28, endln:7:34 |vpiParent: - \_module: work@oh_nor3 (work@oh_nor3), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_nor3.v, line:7:1, endln:17:10 + \_module_inst: work@oh_nor3 (work@oh_nor3), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_nor3.v, line:7:1, endln:17:10 |vpiRhs: \_constant: , line:7:33, endln:7:34 |vpiDecompile:1 @@ -42741,31 +42741,31 @@ design: (work@oh_fifo_async) |vpiNet: \_logic_net: (work@oh_nor3.a), line:9:21, endln:9:22 |vpiParent: - \_module: work@oh_nor3 (work@oh_nor3), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_nor3.v, line:7:1, endln:17:10 + \_module_inst: work@oh_nor3 (work@oh_nor3), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_nor3.v, line:7:1, endln:17:10 |vpiName:a |vpiFullName:work@oh_nor3.a |vpiNet: \_logic_net: (work@oh_nor3.b), line:10:21, endln:10:22 |vpiParent: - \_module: work@oh_nor3 (work@oh_nor3), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_nor3.v, line:7:1, endln:17:10 + \_module_inst: work@oh_nor3 (work@oh_nor3), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_nor3.v, line:7:1, endln:17:10 |vpiName:b |vpiFullName:work@oh_nor3.b |vpiNet: \_logic_net: (work@oh_nor3.c), line:11:21, endln:11:22 |vpiParent: - \_module: work@oh_nor3 (work@oh_nor3), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_nor3.v, line:7:1, endln:17:10 + \_module_inst: work@oh_nor3 (work@oh_nor3), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_nor3.v, line:7:1, endln:17:10 |vpiName:c |vpiFullName:work@oh_nor3.c |vpiNet: \_logic_net: (work@oh_nor3.z), line:12:21, endln:12:22 |vpiParent: - \_module: work@oh_nor3 (work@oh_nor3), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_nor3.v, line:7:1, endln:17:10 + \_module_inst: work@oh_nor3 (work@oh_nor3), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_nor3.v, line:7:1, endln:17:10 |vpiName:z |vpiFullName:work@oh_nor3.z |vpiPort: \_port: (a), line:9:21, endln:9:22 |vpiParent: - \_module: work@oh_nor3 (work@oh_nor3), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_nor3.v, line:7:1, endln:17:10 + \_module_inst: work@oh_nor3 (work@oh_nor3), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_nor3.v, line:7:1, endln:17:10 |vpiName:a |vpiDirection:1 |vpiLowConn: @@ -42805,7 +42805,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (b), line:10:21, endln:10:22 |vpiParent: - \_module: work@oh_nor3 (work@oh_nor3), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_nor3.v, line:7:1, endln:17:10 + \_module_inst: work@oh_nor3 (work@oh_nor3), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_nor3.v, line:7:1, endln:17:10 |vpiName:b |vpiDirection:1 |vpiLowConn: @@ -42845,7 +42845,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (c), line:11:21, endln:11:22 |vpiParent: - \_module: work@oh_nor3 (work@oh_nor3), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_nor3.v, line:7:1, endln:17:10 + \_module_inst: work@oh_nor3 (work@oh_nor3), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_nor3.v, line:7:1, endln:17:10 |vpiName:c |vpiDirection:1 |vpiLowConn: @@ -42885,7 +42885,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (z), line:12:21, endln:12:22 |vpiParent: - \_module: work@oh_nor3 (work@oh_nor3), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_nor3.v, line:7:1, endln:17:10 + \_module_inst: work@oh_nor3 (work@oh_nor3), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_nor3.v, line:7:1, endln:17:10 |vpiName:z |vpiDirection:2 |vpiLowConn: @@ -42925,7 +42925,7 @@ design: (work@oh_fifo_async) |vpiContAssign: \_cont_assign: , line:15:11, endln:15:27 |vpiParent: - \_module: work@oh_nor3 (work@oh_nor3), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_nor3.v, line:7:1, endln:17:10 + \_module_inst: work@oh_nor3 (work@oh_nor3), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_nor3.v, line:7:1, endln:17:10 |vpiRhs: \_operation: , line:15:15, endln:15:27 |vpiParent: @@ -42966,14 +42966,14 @@ design: (work@oh_fifo_async) |vpiName:z |vpiFullName:work@oh_nor3.z |uhdmallModules: -\_module: work@oh_nor4 (work@oh_nor4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_nor4.v, line:7:1, endln:18:10 +\_module_inst: work@oh_nor4 (work@oh_nor4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_nor4.v, line:7:1, endln:18:10 |vpiParent: \_design: (work@oh_fifo_async) |vpiFullName:work@oh_nor4 |vpiParameter: \_parameter: (work@oh_nor4.DW), line:7:28, endln:7:30 |vpiParent: - \_module: work@oh_nor4 (work@oh_nor4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_nor4.v, line:7:1, endln:18:10 + \_module_inst: work@oh_nor4 (work@oh_nor4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_nor4.v, line:7:1, endln:18:10 |UINT:1 |vpiTypespec: \_int_typespec: @@ -42982,7 +42982,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:7:28, endln:7:34 |vpiParent: - \_module: work@oh_nor4 (work@oh_nor4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_nor4.v, line:7:1, endln:18:10 + \_module_inst: work@oh_nor4 (work@oh_nor4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_nor4.v, line:7:1, endln:18:10 |vpiRhs: \_constant: , line:7:33, endln:7:34 |vpiDecompile:1 @@ -42998,37 +42998,37 @@ design: (work@oh_fifo_async) |vpiNet: \_logic_net: (work@oh_nor4.a), line:9:21, endln:9:22 |vpiParent: - \_module: work@oh_nor4 (work@oh_nor4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_nor4.v, line:7:1, endln:18:10 + \_module_inst: work@oh_nor4 (work@oh_nor4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_nor4.v, line:7:1, endln:18:10 |vpiName:a |vpiFullName:work@oh_nor4.a |vpiNet: \_logic_net: (work@oh_nor4.b), line:10:21, endln:10:22 |vpiParent: - \_module: work@oh_nor4 (work@oh_nor4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_nor4.v, line:7:1, endln:18:10 + \_module_inst: work@oh_nor4 (work@oh_nor4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_nor4.v, line:7:1, endln:18:10 |vpiName:b |vpiFullName:work@oh_nor4.b |vpiNet: \_logic_net: (work@oh_nor4.c), line:11:21, endln:11:22 |vpiParent: - \_module: work@oh_nor4 (work@oh_nor4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_nor4.v, line:7:1, endln:18:10 + \_module_inst: work@oh_nor4 (work@oh_nor4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_nor4.v, line:7:1, endln:18:10 |vpiName:c |vpiFullName:work@oh_nor4.c |vpiNet: \_logic_net: (work@oh_nor4.d), line:12:21, endln:12:22 |vpiParent: - \_module: work@oh_nor4 (work@oh_nor4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_nor4.v, line:7:1, endln:18:10 + \_module_inst: work@oh_nor4 (work@oh_nor4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_nor4.v, line:7:1, endln:18:10 |vpiName:d |vpiFullName:work@oh_nor4.d |vpiNet: \_logic_net: (work@oh_nor4.z), line:13:21, endln:13:22 |vpiParent: - \_module: work@oh_nor4 (work@oh_nor4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_nor4.v, line:7:1, endln:18:10 + \_module_inst: work@oh_nor4 (work@oh_nor4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_nor4.v, line:7:1, endln:18:10 |vpiName:z |vpiFullName:work@oh_nor4.z |vpiPort: \_port: (a), line:9:21, endln:9:22 |vpiParent: - \_module: work@oh_nor4 (work@oh_nor4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_nor4.v, line:7:1, endln:18:10 + \_module_inst: work@oh_nor4 (work@oh_nor4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_nor4.v, line:7:1, endln:18:10 |vpiName:a |vpiDirection:1 |vpiLowConn: @@ -43068,7 +43068,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (b), line:10:21, endln:10:22 |vpiParent: - \_module: work@oh_nor4 (work@oh_nor4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_nor4.v, line:7:1, endln:18:10 + \_module_inst: work@oh_nor4 (work@oh_nor4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_nor4.v, line:7:1, endln:18:10 |vpiName:b |vpiDirection:1 |vpiLowConn: @@ -43108,7 +43108,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (c), line:11:21, endln:11:22 |vpiParent: - \_module: work@oh_nor4 (work@oh_nor4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_nor4.v, line:7:1, endln:18:10 + \_module_inst: work@oh_nor4 (work@oh_nor4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_nor4.v, line:7:1, endln:18:10 |vpiName:c |vpiDirection:1 |vpiLowConn: @@ -43148,7 +43148,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (d), line:12:21, endln:12:22 |vpiParent: - \_module: work@oh_nor4 (work@oh_nor4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_nor4.v, line:7:1, endln:18:10 + \_module_inst: work@oh_nor4 (work@oh_nor4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_nor4.v, line:7:1, endln:18:10 |vpiName:d |vpiDirection:1 |vpiLowConn: @@ -43188,7 +43188,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (z), line:13:21, endln:13:22 |vpiParent: - \_module: work@oh_nor4 (work@oh_nor4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_nor4.v, line:7:1, endln:18:10 + \_module_inst: work@oh_nor4 (work@oh_nor4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_nor4.v, line:7:1, endln:18:10 |vpiName:z |vpiDirection:2 |vpiLowConn: @@ -43228,7 +43228,7 @@ design: (work@oh_fifo_async) |vpiContAssign: \_cont_assign: , line:16:11, endln:16:31 |vpiParent: - \_module: work@oh_nor4 (work@oh_nor4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_nor4.v, line:7:1, endln:18:10 + \_module_inst: work@oh_nor4 (work@oh_nor4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_nor4.v, line:7:1, endln:18:10 |vpiRhs: \_operation: , line:16:15, endln:16:31 |vpiParent: @@ -43280,14 +43280,14 @@ design: (work@oh_fifo_async) |vpiName:z |vpiFullName:work@oh_nor4.z |uhdmallModules: -\_module: work@oh_oa21 (work@oh_oa21), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa21.v, line:7:1, endln:17:10 +\_module_inst: work@oh_oa21 (work@oh_oa21), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa21.v, line:7:1, endln:17:10 |vpiParent: \_design: (work@oh_fifo_async) |vpiFullName:work@oh_oa21 |vpiParameter: \_parameter: (work@oh_oa21.DW), line:7:28, endln:7:30 |vpiParent: - \_module: work@oh_oa21 (work@oh_oa21), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa21.v, line:7:1, endln:17:10 + \_module_inst: work@oh_oa21 (work@oh_oa21), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa21.v, line:7:1, endln:17:10 |UINT:1 |vpiTypespec: \_int_typespec: @@ -43296,7 +43296,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:7:28, endln:7:34 |vpiParent: - \_module: work@oh_oa21 (work@oh_oa21), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa21.v, line:7:1, endln:17:10 + \_module_inst: work@oh_oa21 (work@oh_oa21), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa21.v, line:7:1, endln:17:10 |vpiRhs: \_constant: , line:7:33, endln:7:34 |vpiDecompile:1 @@ -43312,31 +43312,31 @@ design: (work@oh_fifo_async) |vpiNet: \_logic_net: (work@oh_oa21.a0), line:9:21, endln:9:23 |vpiParent: - \_module: work@oh_oa21 (work@oh_oa21), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa21.v, line:7:1, endln:17:10 + \_module_inst: work@oh_oa21 (work@oh_oa21), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa21.v, line:7:1, endln:17:10 |vpiName:a0 |vpiFullName:work@oh_oa21.a0 |vpiNet: \_logic_net: (work@oh_oa21.a1), line:10:21, endln:10:23 |vpiParent: - \_module: work@oh_oa21 (work@oh_oa21), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa21.v, line:7:1, endln:17:10 + \_module_inst: work@oh_oa21 (work@oh_oa21), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa21.v, line:7:1, endln:17:10 |vpiName:a1 |vpiFullName:work@oh_oa21.a1 |vpiNet: \_logic_net: (work@oh_oa21.b0), line:11:21, endln:11:23 |vpiParent: - \_module: work@oh_oa21 (work@oh_oa21), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa21.v, line:7:1, endln:17:10 + \_module_inst: work@oh_oa21 (work@oh_oa21), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa21.v, line:7:1, endln:17:10 |vpiName:b0 |vpiFullName:work@oh_oa21.b0 |vpiNet: \_logic_net: (work@oh_oa21.z), line:12:21, endln:12:22 |vpiParent: - \_module: work@oh_oa21 (work@oh_oa21), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa21.v, line:7:1, endln:17:10 + \_module_inst: work@oh_oa21 (work@oh_oa21), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa21.v, line:7:1, endln:17:10 |vpiName:z |vpiFullName:work@oh_oa21.z |vpiPort: \_port: (a0), line:9:21, endln:9:23 |vpiParent: - \_module: work@oh_oa21 (work@oh_oa21), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa21.v, line:7:1, endln:17:10 + \_module_inst: work@oh_oa21 (work@oh_oa21), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa21.v, line:7:1, endln:17:10 |vpiName:a0 |vpiDirection:1 |vpiLowConn: @@ -43376,7 +43376,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (a1), line:10:21, endln:10:23 |vpiParent: - \_module: work@oh_oa21 (work@oh_oa21), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa21.v, line:7:1, endln:17:10 + \_module_inst: work@oh_oa21 (work@oh_oa21), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa21.v, line:7:1, endln:17:10 |vpiName:a1 |vpiDirection:1 |vpiLowConn: @@ -43416,7 +43416,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (b0), line:11:21, endln:11:23 |vpiParent: - \_module: work@oh_oa21 (work@oh_oa21), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa21.v, line:7:1, endln:17:10 + \_module_inst: work@oh_oa21 (work@oh_oa21), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa21.v, line:7:1, endln:17:10 |vpiName:b0 |vpiDirection:1 |vpiLowConn: @@ -43456,7 +43456,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (z), line:12:21, endln:12:22 |vpiParent: - \_module: work@oh_oa21 (work@oh_oa21), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa21.v, line:7:1, endln:17:10 + \_module_inst: work@oh_oa21 (work@oh_oa21), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa21.v, line:7:1, endln:17:10 |vpiName:z |vpiDirection:2 |vpiLowConn: @@ -43496,7 +43496,7 @@ design: (work@oh_fifo_async) |vpiContAssign: \_cont_assign: , line:15:11, endln:15:29 |vpiParent: - \_module: work@oh_oa21 (work@oh_oa21), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa21.v, line:7:1, endln:17:10 + \_module_inst: work@oh_oa21 (work@oh_oa21), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa21.v, line:7:1, endln:17:10 |vpiRhs: \_operation: , line:15:15, endln:15:29 |vpiParent: @@ -43532,14 +43532,14 @@ design: (work@oh_fifo_async) |vpiName:z |vpiFullName:work@oh_oa21.z |uhdmallModules: -\_module: work@oh_oa211 (work@oh_oa211), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa211.v, line:7:1, endln:18:10 +\_module_inst: work@oh_oa211 (work@oh_oa211), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa211.v, line:7:1, endln:18:10 |vpiParent: \_design: (work@oh_fifo_async) |vpiFullName:work@oh_oa211 |vpiParameter: \_parameter: (work@oh_oa211.DW), line:7:29, endln:7:31 |vpiParent: - \_module: work@oh_oa211 (work@oh_oa211), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa211.v, line:7:1, endln:18:10 + \_module_inst: work@oh_oa211 (work@oh_oa211), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa211.v, line:7:1, endln:18:10 |UINT:1 |vpiTypespec: \_int_typespec: @@ -43548,7 +43548,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:7:29, endln:7:35 |vpiParent: - \_module: work@oh_oa211 (work@oh_oa211), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa211.v, line:7:1, endln:18:10 + \_module_inst: work@oh_oa211 (work@oh_oa211), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa211.v, line:7:1, endln:18:10 |vpiRhs: \_constant: , line:7:34, endln:7:35 |vpiDecompile:1 @@ -43564,37 +43564,37 @@ design: (work@oh_fifo_async) |vpiNet: \_logic_net: (work@oh_oa211.a0), line:9:21, endln:9:23 |vpiParent: - \_module: work@oh_oa211 (work@oh_oa211), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa211.v, line:7:1, endln:18:10 + \_module_inst: work@oh_oa211 (work@oh_oa211), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa211.v, line:7:1, endln:18:10 |vpiName:a0 |vpiFullName:work@oh_oa211.a0 |vpiNet: \_logic_net: (work@oh_oa211.a1), line:10:21, endln:10:23 |vpiParent: - \_module: work@oh_oa211 (work@oh_oa211), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa211.v, line:7:1, endln:18:10 + \_module_inst: work@oh_oa211 (work@oh_oa211), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa211.v, line:7:1, endln:18:10 |vpiName:a1 |vpiFullName:work@oh_oa211.a1 |vpiNet: \_logic_net: (work@oh_oa211.b0), line:11:21, endln:11:23 |vpiParent: - \_module: work@oh_oa211 (work@oh_oa211), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa211.v, line:7:1, endln:18:10 + \_module_inst: work@oh_oa211 (work@oh_oa211), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa211.v, line:7:1, endln:18:10 |vpiName:b0 |vpiFullName:work@oh_oa211.b0 |vpiNet: \_logic_net: (work@oh_oa211.c0), line:12:21, endln:12:23 |vpiParent: - \_module: work@oh_oa211 (work@oh_oa211), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa211.v, line:7:1, endln:18:10 + \_module_inst: work@oh_oa211 (work@oh_oa211), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa211.v, line:7:1, endln:18:10 |vpiName:c0 |vpiFullName:work@oh_oa211.c0 |vpiNet: \_logic_net: (work@oh_oa211.z), line:13:21, endln:13:22 |vpiParent: - \_module: work@oh_oa211 (work@oh_oa211), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa211.v, line:7:1, endln:18:10 + \_module_inst: work@oh_oa211 (work@oh_oa211), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa211.v, line:7:1, endln:18:10 |vpiName:z |vpiFullName:work@oh_oa211.z |vpiPort: \_port: (a0), line:9:21, endln:9:23 |vpiParent: - \_module: work@oh_oa211 (work@oh_oa211), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa211.v, line:7:1, endln:18:10 + \_module_inst: work@oh_oa211 (work@oh_oa211), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa211.v, line:7:1, endln:18:10 |vpiName:a0 |vpiDirection:1 |vpiLowConn: @@ -43634,7 +43634,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (a1), line:10:21, endln:10:23 |vpiParent: - \_module: work@oh_oa211 (work@oh_oa211), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa211.v, line:7:1, endln:18:10 + \_module_inst: work@oh_oa211 (work@oh_oa211), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa211.v, line:7:1, endln:18:10 |vpiName:a1 |vpiDirection:1 |vpiLowConn: @@ -43674,7 +43674,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (b0), line:11:21, endln:11:23 |vpiParent: - \_module: work@oh_oa211 (work@oh_oa211), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa211.v, line:7:1, endln:18:10 + \_module_inst: work@oh_oa211 (work@oh_oa211), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa211.v, line:7:1, endln:18:10 |vpiName:b0 |vpiDirection:1 |vpiLowConn: @@ -43714,7 +43714,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (c0), line:12:21, endln:12:23 |vpiParent: - \_module: work@oh_oa211 (work@oh_oa211), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa211.v, line:7:1, endln:18:10 + \_module_inst: work@oh_oa211 (work@oh_oa211), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa211.v, line:7:1, endln:18:10 |vpiName:c0 |vpiDirection:1 |vpiLowConn: @@ -43754,7 +43754,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (z), line:13:21, endln:13:22 |vpiParent: - \_module: work@oh_oa211 (work@oh_oa211), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa211.v, line:7:1, endln:18:10 + \_module_inst: work@oh_oa211 (work@oh_oa211), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa211.v, line:7:1, endln:18:10 |vpiName:z |vpiDirection:2 |vpiLowConn: @@ -43794,7 +43794,7 @@ design: (work@oh_fifo_async) |vpiContAssign: \_cont_assign: , line:16:11, endln:16:34 |vpiParent: - \_module: work@oh_oa211 (work@oh_oa211), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa211.v, line:7:1, endln:18:10 + \_module_inst: work@oh_oa211 (work@oh_oa211), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa211.v, line:7:1, endln:18:10 |vpiRhs: \_operation: , line:16:15, endln:16:34 |vpiParent: @@ -43841,14 +43841,14 @@ design: (work@oh_fifo_async) |vpiName:z |vpiFullName:work@oh_oa211.z |uhdmallModules: -\_module: work@oh_oa22 (work@oh_oa22), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa22.v, line:7:1, endln:18:10 +\_module_inst: work@oh_oa22 (work@oh_oa22), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa22.v, line:7:1, endln:18:10 |vpiParent: \_design: (work@oh_fifo_async) |vpiFullName:work@oh_oa22 |vpiParameter: \_parameter: (work@oh_oa22.DW), line:7:28, endln:7:30 |vpiParent: - \_module: work@oh_oa22 (work@oh_oa22), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa22.v, line:7:1, endln:18:10 + \_module_inst: work@oh_oa22 (work@oh_oa22), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa22.v, line:7:1, endln:18:10 |UINT:1 |vpiTypespec: \_int_typespec: @@ -43857,7 +43857,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:7:28, endln:7:34 |vpiParent: - \_module: work@oh_oa22 (work@oh_oa22), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa22.v, line:7:1, endln:18:10 + \_module_inst: work@oh_oa22 (work@oh_oa22), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa22.v, line:7:1, endln:18:10 |vpiRhs: \_constant: , line:7:33, endln:7:34 |vpiDecompile:1 @@ -43873,37 +43873,37 @@ design: (work@oh_fifo_async) |vpiNet: \_logic_net: (work@oh_oa22.a0), line:9:21, endln:9:23 |vpiParent: - \_module: work@oh_oa22 (work@oh_oa22), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa22.v, line:7:1, endln:18:10 + \_module_inst: work@oh_oa22 (work@oh_oa22), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa22.v, line:7:1, endln:18:10 |vpiName:a0 |vpiFullName:work@oh_oa22.a0 |vpiNet: \_logic_net: (work@oh_oa22.a1), line:10:21, endln:10:23 |vpiParent: - \_module: work@oh_oa22 (work@oh_oa22), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa22.v, line:7:1, endln:18:10 + \_module_inst: work@oh_oa22 (work@oh_oa22), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa22.v, line:7:1, endln:18:10 |vpiName:a1 |vpiFullName:work@oh_oa22.a1 |vpiNet: \_logic_net: (work@oh_oa22.b0), line:11:21, endln:11:23 |vpiParent: - \_module: work@oh_oa22 (work@oh_oa22), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa22.v, line:7:1, endln:18:10 + \_module_inst: work@oh_oa22 (work@oh_oa22), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa22.v, line:7:1, endln:18:10 |vpiName:b0 |vpiFullName:work@oh_oa22.b0 |vpiNet: \_logic_net: (work@oh_oa22.b1), line:12:21, endln:12:23 |vpiParent: - \_module: work@oh_oa22 (work@oh_oa22), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa22.v, line:7:1, endln:18:10 + \_module_inst: work@oh_oa22 (work@oh_oa22), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa22.v, line:7:1, endln:18:10 |vpiName:b1 |vpiFullName:work@oh_oa22.b1 |vpiNet: \_logic_net: (work@oh_oa22.z), line:13:21, endln:13:22 |vpiParent: - \_module: work@oh_oa22 (work@oh_oa22), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa22.v, line:7:1, endln:18:10 + \_module_inst: work@oh_oa22 (work@oh_oa22), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa22.v, line:7:1, endln:18:10 |vpiName:z |vpiFullName:work@oh_oa22.z |vpiPort: \_port: (a0), line:9:21, endln:9:23 |vpiParent: - \_module: work@oh_oa22 (work@oh_oa22), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa22.v, line:7:1, endln:18:10 + \_module_inst: work@oh_oa22 (work@oh_oa22), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa22.v, line:7:1, endln:18:10 |vpiName:a0 |vpiDirection:1 |vpiLowConn: @@ -43943,7 +43943,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (a1), line:10:21, endln:10:23 |vpiParent: - \_module: work@oh_oa22 (work@oh_oa22), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa22.v, line:7:1, endln:18:10 + \_module_inst: work@oh_oa22 (work@oh_oa22), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa22.v, line:7:1, endln:18:10 |vpiName:a1 |vpiDirection:1 |vpiLowConn: @@ -43983,7 +43983,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (b0), line:11:21, endln:11:23 |vpiParent: - \_module: work@oh_oa22 (work@oh_oa22), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa22.v, line:7:1, endln:18:10 + \_module_inst: work@oh_oa22 (work@oh_oa22), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa22.v, line:7:1, endln:18:10 |vpiName:b0 |vpiDirection:1 |vpiLowConn: @@ -44023,7 +44023,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (b1), line:12:21, endln:12:23 |vpiParent: - \_module: work@oh_oa22 (work@oh_oa22), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa22.v, line:7:1, endln:18:10 + \_module_inst: work@oh_oa22 (work@oh_oa22), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa22.v, line:7:1, endln:18:10 |vpiName:b1 |vpiDirection:1 |vpiLowConn: @@ -44063,7 +44063,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (z), line:13:21, endln:13:22 |vpiParent: - \_module: work@oh_oa22 (work@oh_oa22), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa22.v, line:7:1, endln:18:10 + \_module_inst: work@oh_oa22 (work@oh_oa22), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa22.v, line:7:1, endln:18:10 |vpiName:z |vpiDirection:2 |vpiLowConn: @@ -44103,7 +44103,7 @@ design: (work@oh_fifo_async) |vpiContAssign: \_cont_assign: , line:16:11, endln:16:36 |vpiParent: - \_module: work@oh_oa22 (work@oh_oa22), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa22.v, line:7:1, endln:18:10 + \_module_inst: work@oh_oa22 (work@oh_oa22), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa22.v, line:7:1, endln:18:10 |vpiRhs: \_operation: , line:16:15, endln:16:36 |vpiParent: @@ -44150,14 +44150,14 @@ design: (work@oh_fifo_async) |vpiName:z |vpiFullName:work@oh_oa22.z |uhdmallModules: -\_module: work@oh_oa221 (work@oh_oa221), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa221.v, line:7:1, endln:19:10 +\_module_inst: work@oh_oa221 (work@oh_oa221), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa221.v, line:7:1, endln:19:10 |vpiParent: \_design: (work@oh_fifo_async) |vpiFullName:work@oh_oa221 |vpiParameter: \_parameter: (work@oh_oa221.DW), line:7:29, endln:7:31 |vpiParent: - \_module: work@oh_oa221 (work@oh_oa221), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa221.v, line:7:1, endln:19:10 + \_module_inst: work@oh_oa221 (work@oh_oa221), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa221.v, line:7:1, endln:19:10 |UINT:1 |vpiTypespec: \_int_typespec: @@ -44166,7 +44166,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:7:29, endln:7:35 |vpiParent: - \_module: work@oh_oa221 (work@oh_oa221), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa221.v, line:7:1, endln:19:10 + \_module_inst: work@oh_oa221 (work@oh_oa221), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa221.v, line:7:1, endln:19:10 |vpiRhs: \_constant: , line:7:34, endln:7:35 |vpiDecompile:1 @@ -44182,43 +44182,43 @@ design: (work@oh_fifo_async) |vpiNet: \_logic_net: (work@oh_oa221.a0), line:9:21, endln:9:23 |vpiParent: - \_module: work@oh_oa221 (work@oh_oa221), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa221.v, line:7:1, endln:19:10 + \_module_inst: work@oh_oa221 (work@oh_oa221), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa221.v, line:7:1, endln:19:10 |vpiName:a0 |vpiFullName:work@oh_oa221.a0 |vpiNet: \_logic_net: (work@oh_oa221.a1), line:10:21, endln:10:23 |vpiParent: - \_module: work@oh_oa221 (work@oh_oa221), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa221.v, line:7:1, endln:19:10 + \_module_inst: work@oh_oa221 (work@oh_oa221), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa221.v, line:7:1, endln:19:10 |vpiName:a1 |vpiFullName:work@oh_oa221.a1 |vpiNet: \_logic_net: (work@oh_oa221.b0), line:11:21, endln:11:23 |vpiParent: - \_module: work@oh_oa221 (work@oh_oa221), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa221.v, line:7:1, endln:19:10 + \_module_inst: work@oh_oa221 (work@oh_oa221), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa221.v, line:7:1, endln:19:10 |vpiName:b0 |vpiFullName:work@oh_oa221.b0 |vpiNet: \_logic_net: (work@oh_oa221.b1), line:12:21, endln:12:23 |vpiParent: - \_module: work@oh_oa221 (work@oh_oa221), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa221.v, line:7:1, endln:19:10 + \_module_inst: work@oh_oa221 (work@oh_oa221), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa221.v, line:7:1, endln:19:10 |vpiName:b1 |vpiFullName:work@oh_oa221.b1 |vpiNet: \_logic_net: (work@oh_oa221.c0), line:13:21, endln:13:23 |vpiParent: - \_module: work@oh_oa221 (work@oh_oa221), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa221.v, line:7:1, endln:19:10 + \_module_inst: work@oh_oa221 (work@oh_oa221), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa221.v, line:7:1, endln:19:10 |vpiName:c0 |vpiFullName:work@oh_oa221.c0 |vpiNet: \_logic_net: (work@oh_oa221.z), line:14:21, endln:14:22 |vpiParent: - \_module: work@oh_oa221 (work@oh_oa221), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa221.v, line:7:1, endln:19:10 + \_module_inst: work@oh_oa221 (work@oh_oa221), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa221.v, line:7:1, endln:19:10 |vpiName:z |vpiFullName:work@oh_oa221.z |vpiPort: \_port: (a0), line:9:21, endln:9:23 |vpiParent: - \_module: work@oh_oa221 (work@oh_oa221), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa221.v, line:7:1, endln:19:10 + \_module_inst: work@oh_oa221 (work@oh_oa221), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa221.v, line:7:1, endln:19:10 |vpiName:a0 |vpiDirection:1 |vpiLowConn: @@ -44258,7 +44258,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (a1), line:10:21, endln:10:23 |vpiParent: - \_module: work@oh_oa221 (work@oh_oa221), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa221.v, line:7:1, endln:19:10 + \_module_inst: work@oh_oa221 (work@oh_oa221), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa221.v, line:7:1, endln:19:10 |vpiName:a1 |vpiDirection:1 |vpiLowConn: @@ -44298,7 +44298,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (b0), line:11:21, endln:11:23 |vpiParent: - \_module: work@oh_oa221 (work@oh_oa221), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa221.v, line:7:1, endln:19:10 + \_module_inst: work@oh_oa221 (work@oh_oa221), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa221.v, line:7:1, endln:19:10 |vpiName:b0 |vpiDirection:1 |vpiLowConn: @@ -44338,7 +44338,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (b1), line:12:21, endln:12:23 |vpiParent: - \_module: work@oh_oa221 (work@oh_oa221), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa221.v, line:7:1, endln:19:10 + \_module_inst: work@oh_oa221 (work@oh_oa221), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa221.v, line:7:1, endln:19:10 |vpiName:b1 |vpiDirection:1 |vpiLowConn: @@ -44378,7 +44378,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (c0), line:13:21, endln:13:23 |vpiParent: - \_module: work@oh_oa221 (work@oh_oa221), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa221.v, line:7:1, endln:19:10 + \_module_inst: work@oh_oa221 (work@oh_oa221), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa221.v, line:7:1, endln:19:10 |vpiName:c0 |vpiDirection:1 |vpiLowConn: @@ -44418,7 +44418,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (z), line:14:21, endln:14:22 |vpiParent: - \_module: work@oh_oa221 (work@oh_oa221), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa221.v, line:7:1, endln:19:10 + \_module_inst: work@oh_oa221 (work@oh_oa221), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa221.v, line:7:1, endln:19:10 |vpiName:z |vpiDirection:2 |vpiLowConn: @@ -44458,7 +44458,7 @@ design: (work@oh_fifo_async) |vpiContAssign: \_cont_assign: , line:17:11, endln:17:43 |vpiParent: - \_module: work@oh_oa221 (work@oh_oa221), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa221.v, line:7:1, endln:19:10 + \_module_inst: work@oh_oa221 (work@oh_oa221), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa221.v, line:7:1, endln:19:10 |vpiRhs: \_operation: , line:17:15, endln:17:43 |vpiParent: @@ -44516,14 +44516,14 @@ design: (work@oh_fifo_async) |vpiName:z |vpiFullName:work@oh_oa221.z |uhdmallModules: -\_module: work@oh_oa222 (work@oh_oa222), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa222.v, line:7:1, endln:20:10 +\_module_inst: work@oh_oa222 (work@oh_oa222), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa222.v, line:7:1, endln:20:10 |vpiParent: \_design: (work@oh_fifo_async) |vpiFullName:work@oh_oa222 |vpiParameter: \_parameter: (work@oh_oa222.DW), line:7:29, endln:7:31 |vpiParent: - \_module: work@oh_oa222 (work@oh_oa222), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa222.v, line:7:1, endln:20:10 + \_module_inst: work@oh_oa222 (work@oh_oa222), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa222.v, line:7:1, endln:20:10 |UINT:1 |vpiTypespec: \_int_typespec: @@ -44532,7 +44532,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:7:29, endln:7:35 |vpiParent: - \_module: work@oh_oa222 (work@oh_oa222), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa222.v, line:7:1, endln:20:10 + \_module_inst: work@oh_oa222 (work@oh_oa222), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa222.v, line:7:1, endln:20:10 |vpiRhs: \_constant: , line:7:34, endln:7:35 |vpiDecompile:1 @@ -44548,49 +44548,49 @@ design: (work@oh_fifo_async) |vpiNet: \_logic_net: (work@oh_oa222.a0), line:9:21, endln:9:23 |vpiParent: - \_module: work@oh_oa222 (work@oh_oa222), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa222.v, line:7:1, endln:20:10 + \_module_inst: work@oh_oa222 (work@oh_oa222), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa222.v, line:7:1, endln:20:10 |vpiName:a0 |vpiFullName:work@oh_oa222.a0 |vpiNet: \_logic_net: (work@oh_oa222.a1), line:10:21, endln:10:23 |vpiParent: - \_module: work@oh_oa222 (work@oh_oa222), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa222.v, line:7:1, endln:20:10 + \_module_inst: work@oh_oa222 (work@oh_oa222), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa222.v, line:7:1, endln:20:10 |vpiName:a1 |vpiFullName:work@oh_oa222.a1 |vpiNet: \_logic_net: (work@oh_oa222.b0), line:11:21, endln:11:23 |vpiParent: - \_module: work@oh_oa222 (work@oh_oa222), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa222.v, line:7:1, endln:20:10 + \_module_inst: work@oh_oa222 (work@oh_oa222), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa222.v, line:7:1, endln:20:10 |vpiName:b0 |vpiFullName:work@oh_oa222.b0 |vpiNet: \_logic_net: (work@oh_oa222.b1), line:12:21, endln:12:23 |vpiParent: - \_module: work@oh_oa222 (work@oh_oa222), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa222.v, line:7:1, endln:20:10 + \_module_inst: work@oh_oa222 (work@oh_oa222), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa222.v, line:7:1, endln:20:10 |vpiName:b1 |vpiFullName:work@oh_oa222.b1 |vpiNet: \_logic_net: (work@oh_oa222.c0), line:13:21, endln:13:23 |vpiParent: - \_module: work@oh_oa222 (work@oh_oa222), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa222.v, line:7:1, endln:20:10 + \_module_inst: work@oh_oa222 (work@oh_oa222), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa222.v, line:7:1, endln:20:10 |vpiName:c0 |vpiFullName:work@oh_oa222.c0 |vpiNet: \_logic_net: (work@oh_oa222.c1), line:14:21, endln:14:23 |vpiParent: - \_module: work@oh_oa222 (work@oh_oa222), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa222.v, line:7:1, endln:20:10 + \_module_inst: work@oh_oa222 (work@oh_oa222), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa222.v, line:7:1, endln:20:10 |vpiName:c1 |vpiFullName:work@oh_oa222.c1 |vpiNet: \_logic_net: (work@oh_oa222.z), line:15:21, endln:15:22 |vpiParent: - \_module: work@oh_oa222 (work@oh_oa222), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa222.v, line:7:1, endln:20:10 + \_module_inst: work@oh_oa222 (work@oh_oa222), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa222.v, line:7:1, endln:20:10 |vpiName:z |vpiFullName:work@oh_oa222.z |vpiPort: \_port: (a0), line:9:21, endln:9:23 |vpiParent: - \_module: work@oh_oa222 (work@oh_oa222), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa222.v, line:7:1, endln:20:10 + \_module_inst: work@oh_oa222 (work@oh_oa222), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa222.v, line:7:1, endln:20:10 |vpiName:a0 |vpiDirection:1 |vpiLowConn: @@ -44630,7 +44630,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (a1), line:10:21, endln:10:23 |vpiParent: - \_module: work@oh_oa222 (work@oh_oa222), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa222.v, line:7:1, endln:20:10 + \_module_inst: work@oh_oa222 (work@oh_oa222), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa222.v, line:7:1, endln:20:10 |vpiName:a1 |vpiDirection:1 |vpiLowConn: @@ -44670,7 +44670,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (b0), line:11:21, endln:11:23 |vpiParent: - \_module: work@oh_oa222 (work@oh_oa222), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa222.v, line:7:1, endln:20:10 + \_module_inst: work@oh_oa222 (work@oh_oa222), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa222.v, line:7:1, endln:20:10 |vpiName:b0 |vpiDirection:1 |vpiLowConn: @@ -44710,7 +44710,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (b1), line:12:21, endln:12:23 |vpiParent: - \_module: work@oh_oa222 (work@oh_oa222), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa222.v, line:7:1, endln:20:10 + \_module_inst: work@oh_oa222 (work@oh_oa222), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa222.v, line:7:1, endln:20:10 |vpiName:b1 |vpiDirection:1 |vpiLowConn: @@ -44750,7 +44750,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (c0), line:13:21, endln:13:23 |vpiParent: - \_module: work@oh_oa222 (work@oh_oa222), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa222.v, line:7:1, endln:20:10 + \_module_inst: work@oh_oa222 (work@oh_oa222), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa222.v, line:7:1, endln:20:10 |vpiName:c0 |vpiDirection:1 |vpiLowConn: @@ -44790,7 +44790,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (c1), line:14:21, endln:14:23 |vpiParent: - \_module: work@oh_oa222 (work@oh_oa222), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa222.v, line:7:1, endln:20:10 + \_module_inst: work@oh_oa222 (work@oh_oa222), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa222.v, line:7:1, endln:20:10 |vpiName:c1 |vpiDirection:1 |vpiLowConn: @@ -44830,7 +44830,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (z), line:15:21, endln:15:22 |vpiParent: - \_module: work@oh_oa222 (work@oh_oa222), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa222.v, line:7:1, endln:20:10 + \_module_inst: work@oh_oa222 (work@oh_oa222), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa222.v, line:7:1, endln:20:10 |vpiName:z |vpiDirection:2 |vpiLowConn: @@ -44870,7 +44870,7 @@ design: (work@oh_fifo_async) |vpiContAssign: \_cont_assign: , line:18:11, endln:18:48 |vpiParent: - \_module: work@oh_oa222 (work@oh_oa222), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa222.v, line:7:1, endln:20:10 + \_module_inst: work@oh_oa222 (work@oh_oa222), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa222.v, line:7:1, endln:20:10 |vpiRhs: \_operation: , line:18:15, endln:18:48 |vpiParent: @@ -44939,14 +44939,14 @@ design: (work@oh_fifo_async) |vpiName:z |vpiFullName:work@oh_oa222.z |uhdmallModules: -\_module: work@oh_oa31 (work@oh_oa31), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa31.v, line:7:1, endln:18:10 +\_module_inst: work@oh_oa31 (work@oh_oa31), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa31.v, line:7:1, endln:18:10 |vpiParent: \_design: (work@oh_fifo_async) |vpiFullName:work@oh_oa31 |vpiParameter: \_parameter: (work@oh_oa31.DW), line:7:28, endln:7:30 |vpiParent: - \_module: work@oh_oa31 (work@oh_oa31), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa31.v, line:7:1, endln:18:10 + \_module_inst: work@oh_oa31 (work@oh_oa31), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa31.v, line:7:1, endln:18:10 |UINT:1 |vpiTypespec: \_int_typespec: @@ -44955,7 +44955,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:7:28, endln:7:34 |vpiParent: - \_module: work@oh_oa31 (work@oh_oa31), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa31.v, line:7:1, endln:18:10 + \_module_inst: work@oh_oa31 (work@oh_oa31), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa31.v, line:7:1, endln:18:10 |vpiRhs: \_constant: , line:7:33, endln:7:34 |vpiDecompile:1 @@ -44971,37 +44971,37 @@ design: (work@oh_fifo_async) |vpiNet: \_logic_net: (work@oh_oa31.a0), line:9:21, endln:9:23 |vpiParent: - \_module: work@oh_oa31 (work@oh_oa31), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa31.v, line:7:1, endln:18:10 + \_module_inst: work@oh_oa31 (work@oh_oa31), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa31.v, line:7:1, endln:18:10 |vpiName:a0 |vpiFullName:work@oh_oa31.a0 |vpiNet: \_logic_net: (work@oh_oa31.a1), line:10:21, endln:10:23 |vpiParent: - \_module: work@oh_oa31 (work@oh_oa31), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa31.v, line:7:1, endln:18:10 + \_module_inst: work@oh_oa31 (work@oh_oa31), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa31.v, line:7:1, endln:18:10 |vpiName:a1 |vpiFullName:work@oh_oa31.a1 |vpiNet: \_logic_net: (work@oh_oa31.a2), line:11:21, endln:11:23 |vpiParent: - \_module: work@oh_oa31 (work@oh_oa31), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa31.v, line:7:1, endln:18:10 + \_module_inst: work@oh_oa31 (work@oh_oa31), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa31.v, line:7:1, endln:18:10 |vpiName:a2 |vpiFullName:work@oh_oa31.a2 |vpiNet: \_logic_net: (work@oh_oa31.b0), line:12:21, endln:12:23 |vpiParent: - \_module: work@oh_oa31 (work@oh_oa31), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa31.v, line:7:1, endln:18:10 + \_module_inst: work@oh_oa31 (work@oh_oa31), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa31.v, line:7:1, endln:18:10 |vpiName:b0 |vpiFullName:work@oh_oa31.b0 |vpiNet: \_logic_net: (work@oh_oa31.z), line:13:21, endln:13:22 |vpiParent: - \_module: work@oh_oa31 (work@oh_oa31), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa31.v, line:7:1, endln:18:10 + \_module_inst: work@oh_oa31 (work@oh_oa31), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa31.v, line:7:1, endln:18:10 |vpiName:z |vpiFullName:work@oh_oa31.z |vpiPort: \_port: (a0), line:9:21, endln:9:23 |vpiParent: - \_module: work@oh_oa31 (work@oh_oa31), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa31.v, line:7:1, endln:18:10 + \_module_inst: work@oh_oa31 (work@oh_oa31), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa31.v, line:7:1, endln:18:10 |vpiName:a0 |vpiDirection:1 |vpiLowConn: @@ -45041,7 +45041,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (a1), line:10:21, endln:10:23 |vpiParent: - \_module: work@oh_oa31 (work@oh_oa31), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa31.v, line:7:1, endln:18:10 + \_module_inst: work@oh_oa31 (work@oh_oa31), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa31.v, line:7:1, endln:18:10 |vpiName:a1 |vpiDirection:1 |vpiLowConn: @@ -45081,7 +45081,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (a2), line:11:21, endln:11:23 |vpiParent: - \_module: work@oh_oa31 (work@oh_oa31), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa31.v, line:7:1, endln:18:10 + \_module_inst: work@oh_oa31 (work@oh_oa31), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa31.v, line:7:1, endln:18:10 |vpiName:a2 |vpiDirection:1 |vpiLowConn: @@ -45121,7 +45121,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (b0), line:12:21, endln:12:23 |vpiParent: - \_module: work@oh_oa31 (work@oh_oa31), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa31.v, line:7:1, endln:18:10 + \_module_inst: work@oh_oa31 (work@oh_oa31), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa31.v, line:7:1, endln:18:10 |vpiName:b0 |vpiDirection:1 |vpiLowConn: @@ -45161,7 +45161,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (z), line:13:21, endln:13:22 |vpiParent: - \_module: work@oh_oa31 (work@oh_oa31), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa31.v, line:7:1, endln:18:10 + \_module_inst: work@oh_oa31 (work@oh_oa31), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa31.v, line:7:1, endln:18:10 |vpiName:z |vpiDirection:2 |vpiLowConn: @@ -45201,7 +45201,7 @@ design: (work@oh_fifo_async) |vpiContAssign: \_cont_assign: , line:16:11, endln:16:34 |vpiParent: - \_module: work@oh_oa31 (work@oh_oa31), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa31.v, line:7:1, endln:18:10 + \_module_inst: work@oh_oa31 (work@oh_oa31), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa31.v, line:7:1, endln:18:10 |vpiRhs: \_operation: , line:16:15, endln:16:34 |vpiParent: @@ -45248,14 +45248,14 @@ design: (work@oh_fifo_async) |vpiName:z |vpiFullName:work@oh_oa31.z |uhdmallModules: -\_module: work@oh_oa311 (work@oh_oa311), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa311.v, line:7:1, endln:19:10 +\_module_inst: work@oh_oa311 (work@oh_oa311), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa311.v, line:7:1, endln:19:10 |vpiParent: \_design: (work@oh_fifo_async) |vpiFullName:work@oh_oa311 |vpiParameter: \_parameter: (work@oh_oa311.DW), line:7:29, endln:7:31 |vpiParent: - \_module: work@oh_oa311 (work@oh_oa311), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa311.v, line:7:1, endln:19:10 + \_module_inst: work@oh_oa311 (work@oh_oa311), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa311.v, line:7:1, endln:19:10 |UINT:1 |vpiTypespec: \_int_typespec: @@ -45264,7 +45264,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:7:29, endln:7:35 |vpiParent: - \_module: work@oh_oa311 (work@oh_oa311), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa311.v, line:7:1, endln:19:10 + \_module_inst: work@oh_oa311 (work@oh_oa311), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa311.v, line:7:1, endln:19:10 |vpiRhs: \_constant: , line:7:34, endln:7:35 |vpiDecompile:1 @@ -45280,43 +45280,43 @@ design: (work@oh_fifo_async) |vpiNet: \_logic_net: (work@oh_oa311.a0), line:9:21, endln:9:23 |vpiParent: - \_module: work@oh_oa311 (work@oh_oa311), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa311.v, line:7:1, endln:19:10 + \_module_inst: work@oh_oa311 (work@oh_oa311), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa311.v, line:7:1, endln:19:10 |vpiName:a0 |vpiFullName:work@oh_oa311.a0 |vpiNet: \_logic_net: (work@oh_oa311.a1), line:10:21, endln:10:23 |vpiParent: - \_module: work@oh_oa311 (work@oh_oa311), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa311.v, line:7:1, endln:19:10 + \_module_inst: work@oh_oa311 (work@oh_oa311), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa311.v, line:7:1, endln:19:10 |vpiName:a1 |vpiFullName:work@oh_oa311.a1 |vpiNet: \_logic_net: (work@oh_oa311.a2), line:11:21, endln:11:23 |vpiParent: - \_module: work@oh_oa311 (work@oh_oa311), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa311.v, line:7:1, endln:19:10 + \_module_inst: work@oh_oa311 (work@oh_oa311), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa311.v, line:7:1, endln:19:10 |vpiName:a2 |vpiFullName:work@oh_oa311.a2 |vpiNet: \_logic_net: (work@oh_oa311.b0), line:12:21, endln:12:23 |vpiParent: - \_module: work@oh_oa311 (work@oh_oa311), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa311.v, line:7:1, endln:19:10 + \_module_inst: work@oh_oa311 (work@oh_oa311), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa311.v, line:7:1, endln:19:10 |vpiName:b0 |vpiFullName:work@oh_oa311.b0 |vpiNet: \_logic_net: (work@oh_oa311.c0), line:13:21, endln:13:23 |vpiParent: - \_module: work@oh_oa311 (work@oh_oa311), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa311.v, line:7:1, endln:19:10 + \_module_inst: work@oh_oa311 (work@oh_oa311), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa311.v, line:7:1, endln:19:10 |vpiName:c0 |vpiFullName:work@oh_oa311.c0 |vpiNet: \_logic_net: (work@oh_oa311.z), line:14:21, endln:14:22 |vpiParent: - \_module: work@oh_oa311 (work@oh_oa311), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa311.v, line:7:1, endln:19:10 + \_module_inst: work@oh_oa311 (work@oh_oa311), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa311.v, line:7:1, endln:19:10 |vpiName:z |vpiFullName:work@oh_oa311.z |vpiPort: \_port: (a0), line:9:21, endln:9:23 |vpiParent: - \_module: work@oh_oa311 (work@oh_oa311), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa311.v, line:7:1, endln:19:10 + \_module_inst: work@oh_oa311 (work@oh_oa311), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa311.v, line:7:1, endln:19:10 |vpiName:a0 |vpiDirection:1 |vpiLowConn: @@ -45356,7 +45356,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (a1), line:10:21, endln:10:23 |vpiParent: - \_module: work@oh_oa311 (work@oh_oa311), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa311.v, line:7:1, endln:19:10 + \_module_inst: work@oh_oa311 (work@oh_oa311), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa311.v, line:7:1, endln:19:10 |vpiName:a1 |vpiDirection:1 |vpiLowConn: @@ -45396,7 +45396,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (a2), line:11:21, endln:11:23 |vpiParent: - \_module: work@oh_oa311 (work@oh_oa311), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa311.v, line:7:1, endln:19:10 + \_module_inst: work@oh_oa311 (work@oh_oa311), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa311.v, line:7:1, endln:19:10 |vpiName:a2 |vpiDirection:1 |vpiLowConn: @@ -45436,7 +45436,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (b0), line:12:21, endln:12:23 |vpiParent: - \_module: work@oh_oa311 (work@oh_oa311), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa311.v, line:7:1, endln:19:10 + \_module_inst: work@oh_oa311 (work@oh_oa311), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa311.v, line:7:1, endln:19:10 |vpiName:b0 |vpiDirection:1 |vpiLowConn: @@ -45476,7 +45476,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (c0), line:13:21, endln:13:23 |vpiParent: - \_module: work@oh_oa311 (work@oh_oa311), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa311.v, line:7:1, endln:19:10 + \_module_inst: work@oh_oa311 (work@oh_oa311), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa311.v, line:7:1, endln:19:10 |vpiName:c0 |vpiDirection:1 |vpiLowConn: @@ -45516,7 +45516,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (z), line:14:21, endln:14:22 |vpiParent: - \_module: work@oh_oa311 (work@oh_oa311), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa311.v, line:7:1, endln:19:10 + \_module_inst: work@oh_oa311 (work@oh_oa311), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa311.v, line:7:1, endln:19:10 |vpiName:z |vpiDirection:2 |vpiLowConn: @@ -45556,7 +45556,7 @@ design: (work@oh_fifo_async) |vpiContAssign: \_cont_assign: , line:17:11, endln:17:39 |vpiParent: - \_module: work@oh_oa311 (work@oh_oa311), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa311.v, line:7:1, endln:19:10 + \_module_inst: work@oh_oa311 (work@oh_oa311), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa311.v, line:7:1, endln:19:10 |vpiRhs: \_operation: , line:17:15, endln:17:39 |vpiParent: @@ -45614,14 +45614,14 @@ design: (work@oh_fifo_async) |vpiName:z |vpiFullName:work@oh_oa311.z |uhdmallModules: -\_module: work@oh_oa32 (work@oh_oa32), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa32.v, line:7:1, endln:19:10 +\_module_inst: work@oh_oa32 (work@oh_oa32), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa32.v, line:7:1, endln:19:10 |vpiParent: \_design: (work@oh_fifo_async) |vpiFullName:work@oh_oa32 |vpiParameter: \_parameter: (work@oh_oa32.DW), line:7:28, endln:7:30 |vpiParent: - \_module: work@oh_oa32 (work@oh_oa32), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa32.v, line:7:1, endln:19:10 + \_module_inst: work@oh_oa32 (work@oh_oa32), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa32.v, line:7:1, endln:19:10 |UINT:1 |vpiTypespec: \_int_typespec: @@ -45630,7 +45630,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:7:28, endln:7:34 |vpiParent: - \_module: work@oh_oa32 (work@oh_oa32), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa32.v, line:7:1, endln:19:10 + \_module_inst: work@oh_oa32 (work@oh_oa32), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa32.v, line:7:1, endln:19:10 |vpiRhs: \_constant: , line:7:33, endln:7:34 |vpiDecompile:1 @@ -45646,43 +45646,43 @@ design: (work@oh_fifo_async) |vpiNet: \_logic_net: (work@oh_oa32.a0), line:9:21, endln:9:23 |vpiParent: - \_module: work@oh_oa32 (work@oh_oa32), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa32.v, line:7:1, endln:19:10 + \_module_inst: work@oh_oa32 (work@oh_oa32), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa32.v, line:7:1, endln:19:10 |vpiName:a0 |vpiFullName:work@oh_oa32.a0 |vpiNet: \_logic_net: (work@oh_oa32.a1), line:10:21, endln:10:23 |vpiParent: - \_module: work@oh_oa32 (work@oh_oa32), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa32.v, line:7:1, endln:19:10 + \_module_inst: work@oh_oa32 (work@oh_oa32), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa32.v, line:7:1, endln:19:10 |vpiName:a1 |vpiFullName:work@oh_oa32.a1 |vpiNet: \_logic_net: (work@oh_oa32.a2), line:11:21, endln:11:23 |vpiParent: - \_module: work@oh_oa32 (work@oh_oa32), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa32.v, line:7:1, endln:19:10 + \_module_inst: work@oh_oa32 (work@oh_oa32), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa32.v, line:7:1, endln:19:10 |vpiName:a2 |vpiFullName:work@oh_oa32.a2 |vpiNet: \_logic_net: (work@oh_oa32.b0), line:12:21, endln:12:23 |vpiParent: - \_module: work@oh_oa32 (work@oh_oa32), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa32.v, line:7:1, endln:19:10 + \_module_inst: work@oh_oa32 (work@oh_oa32), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa32.v, line:7:1, endln:19:10 |vpiName:b0 |vpiFullName:work@oh_oa32.b0 |vpiNet: \_logic_net: (work@oh_oa32.b1), line:13:21, endln:13:23 |vpiParent: - \_module: work@oh_oa32 (work@oh_oa32), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa32.v, line:7:1, endln:19:10 + \_module_inst: work@oh_oa32 (work@oh_oa32), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa32.v, line:7:1, endln:19:10 |vpiName:b1 |vpiFullName:work@oh_oa32.b1 |vpiNet: \_logic_net: (work@oh_oa32.z), line:14:21, endln:14:22 |vpiParent: - \_module: work@oh_oa32 (work@oh_oa32), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa32.v, line:7:1, endln:19:10 + \_module_inst: work@oh_oa32 (work@oh_oa32), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa32.v, line:7:1, endln:19:10 |vpiName:z |vpiFullName:work@oh_oa32.z |vpiPort: \_port: (a0), line:9:21, endln:9:23 |vpiParent: - \_module: work@oh_oa32 (work@oh_oa32), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa32.v, line:7:1, endln:19:10 + \_module_inst: work@oh_oa32 (work@oh_oa32), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa32.v, line:7:1, endln:19:10 |vpiName:a0 |vpiDirection:1 |vpiLowConn: @@ -45722,7 +45722,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (a1), line:10:21, endln:10:23 |vpiParent: - \_module: work@oh_oa32 (work@oh_oa32), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa32.v, line:7:1, endln:19:10 + \_module_inst: work@oh_oa32 (work@oh_oa32), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa32.v, line:7:1, endln:19:10 |vpiName:a1 |vpiDirection:1 |vpiLowConn: @@ -45762,7 +45762,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (a2), line:11:21, endln:11:23 |vpiParent: - \_module: work@oh_oa32 (work@oh_oa32), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa32.v, line:7:1, endln:19:10 + \_module_inst: work@oh_oa32 (work@oh_oa32), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa32.v, line:7:1, endln:19:10 |vpiName:a2 |vpiDirection:1 |vpiLowConn: @@ -45802,7 +45802,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (b0), line:12:21, endln:12:23 |vpiParent: - \_module: work@oh_oa32 (work@oh_oa32), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa32.v, line:7:1, endln:19:10 + \_module_inst: work@oh_oa32 (work@oh_oa32), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa32.v, line:7:1, endln:19:10 |vpiName:b0 |vpiDirection:1 |vpiLowConn: @@ -45842,7 +45842,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (b1), line:13:21, endln:13:23 |vpiParent: - \_module: work@oh_oa32 (work@oh_oa32), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa32.v, line:7:1, endln:19:10 + \_module_inst: work@oh_oa32 (work@oh_oa32), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa32.v, line:7:1, endln:19:10 |vpiName:b1 |vpiDirection:1 |vpiLowConn: @@ -45882,7 +45882,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (z), line:14:21, endln:14:22 |vpiParent: - \_module: work@oh_oa32 (work@oh_oa32), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa32.v, line:7:1, endln:19:10 + \_module_inst: work@oh_oa32 (work@oh_oa32), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa32.v, line:7:1, endln:19:10 |vpiName:z |vpiDirection:2 |vpiLowConn: @@ -45922,7 +45922,7 @@ design: (work@oh_fifo_async) |vpiContAssign: \_cont_assign: , line:17:11, endln:17:41 |vpiParent: - \_module: work@oh_oa32 (work@oh_oa32), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa32.v, line:7:1, endln:19:10 + \_module_inst: work@oh_oa32 (work@oh_oa32), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa32.v, line:7:1, endln:19:10 |vpiRhs: \_operation: , line:17:15, endln:17:41 |vpiParent: @@ -45980,14 +45980,14 @@ design: (work@oh_fifo_async) |vpiName:z |vpiFullName:work@oh_oa32.z |uhdmallModules: -\_module: work@oh_oa33 (work@oh_oa33), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa33.v, line:7:1, endln:20:10 +\_module_inst: work@oh_oa33 (work@oh_oa33), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa33.v, line:7:1, endln:20:10 |vpiParent: \_design: (work@oh_fifo_async) |vpiFullName:work@oh_oa33 |vpiParameter: \_parameter: (work@oh_oa33.DW), line:7:28, endln:7:30 |vpiParent: - \_module: work@oh_oa33 (work@oh_oa33), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa33.v, line:7:1, endln:20:10 + \_module_inst: work@oh_oa33 (work@oh_oa33), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa33.v, line:7:1, endln:20:10 |UINT:1 |vpiTypespec: \_int_typespec: @@ -45996,7 +45996,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:7:28, endln:7:34 |vpiParent: - \_module: work@oh_oa33 (work@oh_oa33), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa33.v, line:7:1, endln:20:10 + \_module_inst: work@oh_oa33 (work@oh_oa33), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa33.v, line:7:1, endln:20:10 |vpiRhs: \_constant: , line:7:33, endln:7:34 |vpiDecompile:1 @@ -46012,49 +46012,49 @@ design: (work@oh_fifo_async) |vpiNet: \_logic_net: (work@oh_oa33.a0), line:9:21, endln:9:23 |vpiParent: - \_module: work@oh_oa33 (work@oh_oa33), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa33.v, line:7:1, endln:20:10 + \_module_inst: work@oh_oa33 (work@oh_oa33), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa33.v, line:7:1, endln:20:10 |vpiName:a0 |vpiFullName:work@oh_oa33.a0 |vpiNet: \_logic_net: (work@oh_oa33.a1), line:10:21, endln:10:23 |vpiParent: - \_module: work@oh_oa33 (work@oh_oa33), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa33.v, line:7:1, endln:20:10 + \_module_inst: work@oh_oa33 (work@oh_oa33), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa33.v, line:7:1, endln:20:10 |vpiName:a1 |vpiFullName:work@oh_oa33.a1 |vpiNet: \_logic_net: (work@oh_oa33.a2), line:11:21, endln:11:23 |vpiParent: - \_module: work@oh_oa33 (work@oh_oa33), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa33.v, line:7:1, endln:20:10 + \_module_inst: work@oh_oa33 (work@oh_oa33), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa33.v, line:7:1, endln:20:10 |vpiName:a2 |vpiFullName:work@oh_oa33.a2 |vpiNet: \_logic_net: (work@oh_oa33.b0), line:12:21, endln:12:23 |vpiParent: - \_module: work@oh_oa33 (work@oh_oa33), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa33.v, line:7:1, endln:20:10 + \_module_inst: work@oh_oa33 (work@oh_oa33), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa33.v, line:7:1, endln:20:10 |vpiName:b0 |vpiFullName:work@oh_oa33.b0 |vpiNet: \_logic_net: (work@oh_oa33.b1), line:13:21, endln:13:23 |vpiParent: - \_module: work@oh_oa33 (work@oh_oa33), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa33.v, line:7:1, endln:20:10 + \_module_inst: work@oh_oa33 (work@oh_oa33), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa33.v, line:7:1, endln:20:10 |vpiName:b1 |vpiFullName:work@oh_oa33.b1 |vpiNet: \_logic_net: (work@oh_oa33.b2), line:14:21, endln:14:23 |vpiParent: - \_module: work@oh_oa33 (work@oh_oa33), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa33.v, line:7:1, endln:20:10 + \_module_inst: work@oh_oa33 (work@oh_oa33), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa33.v, line:7:1, endln:20:10 |vpiName:b2 |vpiFullName:work@oh_oa33.b2 |vpiNet: \_logic_net: (work@oh_oa33.z), line:15:21, endln:15:22 |vpiParent: - \_module: work@oh_oa33 (work@oh_oa33), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa33.v, line:7:1, endln:20:10 + \_module_inst: work@oh_oa33 (work@oh_oa33), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa33.v, line:7:1, endln:20:10 |vpiName:z |vpiFullName:work@oh_oa33.z |vpiPort: \_port: (a0), line:9:21, endln:9:23 |vpiParent: - \_module: work@oh_oa33 (work@oh_oa33), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa33.v, line:7:1, endln:20:10 + \_module_inst: work@oh_oa33 (work@oh_oa33), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa33.v, line:7:1, endln:20:10 |vpiName:a0 |vpiDirection:1 |vpiLowConn: @@ -46094,7 +46094,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (a1), line:10:21, endln:10:23 |vpiParent: - \_module: work@oh_oa33 (work@oh_oa33), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa33.v, line:7:1, endln:20:10 + \_module_inst: work@oh_oa33 (work@oh_oa33), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa33.v, line:7:1, endln:20:10 |vpiName:a1 |vpiDirection:1 |vpiLowConn: @@ -46134,7 +46134,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (a2), line:11:21, endln:11:23 |vpiParent: - \_module: work@oh_oa33 (work@oh_oa33), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa33.v, line:7:1, endln:20:10 + \_module_inst: work@oh_oa33 (work@oh_oa33), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa33.v, line:7:1, endln:20:10 |vpiName:a2 |vpiDirection:1 |vpiLowConn: @@ -46174,7 +46174,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (b0), line:12:21, endln:12:23 |vpiParent: - \_module: work@oh_oa33 (work@oh_oa33), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa33.v, line:7:1, endln:20:10 + \_module_inst: work@oh_oa33 (work@oh_oa33), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa33.v, line:7:1, endln:20:10 |vpiName:b0 |vpiDirection:1 |vpiLowConn: @@ -46214,7 +46214,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (b1), line:13:21, endln:13:23 |vpiParent: - \_module: work@oh_oa33 (work@oh_oa33), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa33.v, line:7:1, endln:20:10 + \_module_inst: work@oh_oa33 (work@oh_oa33), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa33.v, line:7:1, endln:20:10 |vpiName:b1 |vpiDirection:1 |vpiLowConn: @@ -46254,7 +46254,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (b2), line:14:21, endln:14:23 |vpiParent: - \_module: work@oh_oa33 (work@oh_oa33), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa33.v, line:7:1, endln:20:10 + \_module_inst: work@oh_oa33 (work@oh_oa33), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa33.v, line:7:1, endln:20:10 |vpiName:b2 |vpiDirection:1 |vpiLowConn: @@ -46294,7 +46294,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (z), line:15:21, endln:15:22 |vpiParent: - \_module: work@oh_oa33 (work@oh_oa33), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa33.v, line:7:1, endln:20:10 + \_module_inst: work@oh_oa33 (work@oh_oa33), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa33.v, line:7:1, endln:20:10 |vpiName:z |vpiDirection:2 |vpiLowConn: @@ -46334,7 +46334,7 @@ design: (work@oh_fifo_async) |vpiContAssign: \_cont_assign: , line:18:11, endln:18:46 |vpiParent: - \_module: work@oh_oa33 (work@oh_oa33), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa33.v, line:7:1, endln:20:10 + \_module_inst: work@oh_oa33 (work@oh_oa33), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa33.v, line:7:1, endln:20:10 |vpiRhs: \_operation: , line:18:15, endln:18:46 |vpiParent: @@ -46403,14 +46403,14 @@ design: (work@oh_fifo_async) |vpiName:z |vpiFullName:work@oh_oa33.z |uhdmallModules: -\_module: work@oh_oai21 (work@oh_oai21), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai21.v, line:7:1, endln:17:10 +\_module_inst: work@oh_oai21 (work@oh_oai21), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai21.v, line:7:1, endln:17:10 |vpiParent: \_design: (work@oh_fifo_async) |vpiFullName:work@oh_oai21 |vpiParameter: \_parameter: (work@oh_oai21.DW), line:7:29, endln:7:31 |vpiParent: - \_module: work@oh_oai21 (work@oh_oai21), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai21.v, line:7:1, endln:17:10 + \_module_inst: work@oh_oai21 (work@oh_oai21), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai21.v, line:7:1, endln:17:10 |UINT:1 |vpiTypespec: \_int_typespec: @@ -46419,7 +46419,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:7:29, endln:7:35 |vpiParent: - \_module: work@oh_oai21 (work@oh_oai21), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai21.v, line:7:1, endln:17:10 + \_module_inst: work@oh_oai21 (work@oh_oai21), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai21.v, line:7:1, endln:17:10 |vpiRhs: \_constant: , line:7:34, endln:7:35 |vpiDecompile:1 @@ -46435,31 +46435,31 @@ design: (work@oh_fifo_async) |vpiNet: \_logic_net: (work@oh_oai21.a0), line:9:21, endln:9:23 |vpiParent: - \_module: work@oh_oai21 (work@oh_oai21), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai21.v, line:7:1, endln:17:10 + \_module_inst: work@oh_oai21 (work@oh_oai21), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai21.v, line:7:1, endln:17:10 |vpiName:a0 |vpiFullName:work@oh_oai21.a0 |vpiNet: \_logic_net: (work@oh_oai21.a1), line:10:21, endln:10:23 |vpiParent: - \_module: work@oh_oai21 (work@oh_oai21), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai21.v, line:7:1, endln:17:10 + \_module_inst: work@oh_oai21 (work@oh_oai21), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai21.v, line:7:1, endln:17:10 |vpiName:a1 |vpiFullName:work@oh_oai21.a1 |vpiNet: \_logic_net: (work@oh_oai21.b0), line:11:21, endln:11:23 |vpiParent: - \_module: work@oh_oai21 (work@oh_oai21), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai21.v, line:7:1, endln:17:10 + \_module_inst: work@oh_oai21 (work@oh_oai21), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai21.v, line:7:1, endln:17:10 |vpiName:b0 |vpiFullName:work@oh_oai21.b0 |vpiNet: \_logic_net: (work@oh_oai21.z), line:12:21, endln:12:22 |vpiParent: - \_module: work@oh_oai21 (work@oh_oai21), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai21.v, line:7:1, endln:17:10 + \_module_inst: work@oh_oai21 (work@oh_oai21), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai21.v, line:7:1, endln:17:10 |vpiName:z |vpiFullName:work@oh_oai21.z |vpiPort: \_port: (a0), line:9:21, endln:9:23 |vpiParent: - \_module: work@oh_oai21 (work@oh_oai21), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai21.v, line:7:1, endln:17:10 + \_module_inst: work@oh_oai21 (work@oh_oai21), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai21.v, line:7:1, endln:17:10 |vpiName:a0 |vpiDirection:1 |vpiLowConn: @@ -46499,7 +46499,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (a1), line:10:21, endln:10:23 |vpiParent: - \_module: work@oh_oai21 (work@oh_oai21), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai21.v, line:7:1, endln:17:10 + \_module_inst: work@oh_oai21 (work@oh_oai21), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai21.v, line:7:1, endln:17:10 |vpiName:a1 |vpiDirection:1 |vpiLowConn: @@ -46539,7 +46539,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (b0), line:11:21, endln:11:23 |vpiParent: - \_module: work@oh_oai21 (work@oh_oai21), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai21.v, line:7:1, endln:17:10 + \_module_inst: work@oh_oai21 (work@oh_oai21), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai21.v, line:7:1, endln:17:10 |vpiName:b0 |vpiDirection:1 |vpiLowConn: @@ -46579,7 +46579,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (z), line:12:21, endln:12:22 |vpiParent: - \_module: work@oh_oai21 (work@oh_oai21), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai21.v, line:7:1, endln:17:10 + \_module_inst: work@oh_oai21 (work@oh_oai21), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai21.v, line:7:1, endln:17:10 |vpiName:z |vpiDirection:2 |vpiLowConn: @@ -46619,7 +46619,7 @@ design: (work@oh_fifo_async) |vpiContAssign: \_cont_assign: , line:15:11, endln:15:32 |vpiParent: - \_module: work@oh_oai21 (work@oh_oai21), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai21.v, line:7:1, endln:17:10 + \_module_inst: work@oh_oai21 (work@oh_oai21), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai21.v, line:7:1, endln:17:10 |vpiRhs: \_operation: , line:15:15, endln:15:32 |vpiParent: @@ -46660,14 +46660,14 @@ design: (work@oh_fifo_async) |vpiName:z |vpiFullName:work@oh_oai21.z |uhdmallModules: -\_module: work@oh_oai22 (work@oh_oai22), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai22.v, line:7:1, endln:18:10 +\_module_inst: work@oh_oai22 (work@oh_oai22), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai22.v, line:7:1, endln:18:10 |vpiParent: \_design: (work@oh_fifo_async) |vpiFullName:work@oh_oai22 |vpiParameter: \_parameter: (work@oh_oai22.DW), line:7:29, endln:7:31 |vpiParent: - \_module: work@oh_oai22 (work@oh_oai22), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai22.v, line:7:1, endln:18:10 + \_module_inst: work@oh_oai22 (work@oh_oai22), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai22.v, line:7:1, endln:18:10 |UINT:1 |vpiTypespec: \_int_typespec: @@ -46676,7 +46676,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:7:29, endln:7:35 |vpiParent: - \_module: work@oh_oai22 (work@oh_oai22), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai22.v, line:7:1, endln:18:10 + \_module_inst: work@oh_oai22 (work@oh_oai22), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai22.v, line:7:1, endln:18:10 |vpiRhs: \_constant: , line:7:34, endln:7:35 |vpiDecompile:1 @@ -46692,37 +46692,37 @@ design: (work@oh_fifo_async) |vpiNet: \_logic_net: (work@oh_oai22.a0), line:9:21, endln:9:23 |vpiParent: - \_module: work@oh_oai22 (work@oh_oai22), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai22.v, line:7:1, endln:18:10 + \_module_inst: work@oh_oai22 (work@oh_oai22), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai22.v, line:7:1, endln:18:10 |vpiName:a0 |vpiFullName:work@oh_oai22.a0 |vpiNet: \_logic_net: (work@oh_oai22.a1), line:10:21, endln:10:23 |vpiParent: - \_module: work@oh_oai22 (work@oh_oai22), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai22.v, line:7:1, endln:18:10 + \_module_inst: work@oh_oai22 (work@oh_oai22), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai22.v, line:7:1, endln:18:10 |vpiName:a1 |vpiFullName:work@oh_oai22.a1 |vpiNet: \_logic_net: (work@oh_oai22.b0), line:11:21, endln:11:23 |vpiParent: - \_module: work@oh_oai22 (work@oh_oai22), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai22.v, line:7:1, endln:18:10 + \_module_inst: work@oh_oai22 (work@oh_oai22), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai22.v, line:7:1, endln:18:10 |vpiName:b0 |vpiFullName:work@oh_oai22.b0 |vpiNet: \_logic_net: (work@oh_oai22.b1), line:12:21, endln:12:23 |vpiParent: - \_module: work@oh_oai22 (work@oh_oai22), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai22.v, line:7:1, endln:18:10 + \_module_inst: work@oh_oai22 (work@oh_oai22), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai22.v, line:7:1, endln:18:10 |vpiName:b1 |vpiFullName:work@oh_oai22.b1 |vpiNet: \_logic_net: (work@oh_oai22.z), line:13:21, endln:13:22 |vpiParent: - \_module: work@oh_oai22 (work@oh_oai22), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai22.v, line:7:1, endln:18:10 + \_module_inst: work@oh_oai22 (work@oh_oai22), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai22.v, line:7:1, endln:18:10 |vpiName:z |vpiFullName:work@oh_oai22.z |vpiPort: \_port: (a0), line:9:21, endln:9:23 |vpiParent: - \_module: work@oh_oai22 (work@oh_oai22), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai22.v, line:7:1, endln:18:10 + \_module_inst: work@oh_oai22 (work@oh_oai22), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai22.v, line:7:1, endln:18:10 |vpiName:a0 |vpiDirection:1 |vpiLowConn: @@ -46762,7 +46762,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (a1), line:10:21, endln:10:23 |vpiParent: - \_module: work@oh_oai22 (work@oh_oai22), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai22.v, line:7:1, endln:18:10 + \_module_inst: work@oh_oai22 (work@oh_oai22), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai22.v, line:7:1, endln:18:10 |vpiName:a1 |vpiDirection:1 |vpiLowConn: @@ -46802,7 +46802,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (b0), line:11:21, endln:11:23 |vpiParent: - \_module: work@oh_oai22 (work@oh_oai22), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai22.v, line:7:1, endln:18:10 + \_module_inst: work@oh_oai22 (work@oh_oai22), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai22.v, line:7:1, endln:18:10 |vpiName:b0 |vpiDirection:1 |vpiLowConn: @@ -46842,7 +46842,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (b1), line:12:21, endln:12:23 |vpiParent: - \_module: work@oh_oai22 (work@oh_oai22), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai22.v, line:7:1, endln:18:10 + \_module_inst: work@oh_oai22 (work@oh_oai22), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai22.v, line:7:1, endln:18:10 |vpiName:b1 |vpiDirection:1 |vpiLowConn: @@ -46882,7 +46882,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (z), line:13:21, endln:13:22 |vpiParent: - \_module: work@oh_oai22 (work@oh_oai22), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai22.v, line:7:1, endln:18:10 + \_module_inst: work@oh_oai22 (work@oh_oai22), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai22.v, line:7:1, endln:18:10 |vpiName:z |vpiDirection:2 |vpiLowConn: @@ -46922,7 +46922,7 @@ design: (work@oh_fifo_async) |vpiContAssign: \_cont_assign: , line:16:11, endln:16:39 |vpiParent: - \_module: work@oh_oai22 (work@oh_oai22), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai22.v, line:7:1, endln:18:10 + \_module_inst: work@oh_oai22 (work@oh_oai22), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai22.v, line:7:1, endln:18:10 |vpiRhs: \_operation: , line:16:15, endln:16:39 |vpiParent: @@ -46974,14 +46974,14 @@ design: (work@oh_fifo_async) |vpiName:z |vpiFullName:work@oh_oai22.z |uhdmallModules: -\_module: work@oh_oai221 (work@oh_oai221), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai221.v, line:7:1, endln:19:10 +\_module_inst: work@oh_oai221 (work@oh_oai221), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai221.v, line:7:1, endln:19:10 |vpiParent: \_design: (work@oh_fifo_async) |vpiFullName:work@oh_oai221 |vpiParameter: \_parameter: (work@oh_oai221.DW), line:7:30, endln:7:32 |vpiParent: - \_module: work@oh_oai221 (work@oh_oai221), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai221.v, line:7:1, endln:19:10 + \_module_inst: work@oh_oai221 (work@oh_oai221), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai221.v, line:7:1, endln:19:10 |UINT:1 |vpiTypespec: \_int_typespec: @@ -46990,7 +46990,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:7:30, endln:7:36 |vpiParent: - \_module: work@oh_oai221 (work@oh_oai221), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai221.v, line:7:1, endln:19:10 + \_module_inst: work@oh_oai221 (work@oh_oai221), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai221.v, line:7:1, endln:19:10 |vpiRhs: \_constant: , line:7:35, endln:7:36 |vpiDecompile:1 @@ -47006,43 +47006,43 @@ design: (work@oh_fifo_async) |vpiNet: \_logic_net: (work@oh_oai221.a0), line:9:21, endln:9:23 |vpiParent: - \_module: work@oh_oai221 (work@oh_oai221), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai221.v, line:7:1, endln:19:10 + \_module_inst: work@oh_oai221 (work@oh_oai221), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai221.v, line:7:1, endln:19:10 |vpiName:a0 |vpiFullName:work@oh_oai221.a0 |vpiNet: \_logic_net: (work@oh_oai221.a1), line:10:21, endln:10:23 |vpiParent: - \_module: work@oh_oai221 (work@oh_oai221), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai221.v, line:7:1, endln:19:10 + \_module_inst: work@oh_oai221 (work@oh_oai221), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai221.v, line:7:1, endln:19:10 |vpiName:a1 |vpiFullName:work@oh_oai221.a1 |vpiNet: \_logic_net: (work@oh_oai221.b0), line:11:21, endln:11:23 |vpiParent: - \_module: work@oh_oai221 (work@oh_oai221), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai221.v, line:7:1, endln:19:10 + \_module_inst: work@oh_oai221 (work@oh_oai221), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai221.v, line:7:1, endln:19:10 |vpiName:b0 |vpiFullName:work@oh_oai221.b0 |vpiNet: \_logic_net: (work@oh_oai221.b1), line:12:21, endln:12:23 |vpiParent: - \_module: work@oh_oai221 (work@oh_oai221), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai221.v, line:7:1, endln:19:10 + \_module_inst: work@oh_oai221 (work@oh_oai221), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai221.v, line:7:1, endln:19:10 |vpiName:b1 |vpiFullName:work@oh_oai221.b1 |vpiNet: \_logic_net: (work@oh_oai221.c0), line:13:21, endln:13:23 |vpiParent: - \_module: work@oh_oai221 (work@oh_oai221), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai221.v, line:7:1, endln:19:10 + \_module_inst: work@oh_oai221 (work@oh_oai221), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai221.v, line:7:1, endln:19:10 |vpiName:c0 |vpiFullName:work@oh_oai221.c0 |vpiNet: \_logic_net: (work@oh_oai221.z), line:14:21, endln:14:22 |vpiParent: - \_module: work@oh_oai221 (work@oh_oai221), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai221.v, line:7:1, endln:19:10 + \_module_inst: work@oh_oai221 (work@oh_oai221), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai221.v, line:7:1, endln:19:10 |vpiName:z |vpiFullName:work@oh_oai221.z |vpiPort: \_port: (a0), line:9:21, endln:9:23 |vpiParent: - \_module: work@oh_oai221 (work@oh_oai221), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai221.v, line:7:1, endln:19:10 + \_module_inst: work@oh_oai221 (work@oh_oai221), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai221.v, line:7:1, endln:19:10 |vpiName:a0 |vpiDirection:1 |vpiLowConn: @@ -47082,7 +47082,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (a1), line:10:21, endln:10:23 |vpiParent: - \_module: work@oh_oai221 (work@oh_oai221), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai221.v, line:7:1, endln:19:10 + \_module_inst: work@oh_oai221 (work@oh_oai221), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai221.v, line:7:1, endln:19:10 |vpiName:a1 |vpiDirection:1 |vpiLowConn: @@ -47122,7 +47122,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (b0), line:11:21, endln:11:23 |vpiParent: - \_module: work@oh_oai221 (work@oh_oai221), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai221.v, line:7:1, endln:19:10 + \_module_inst: work@oh_oai221 (work@oh_oai221), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai221.v, line:7:1, endln:19:10 |vpiName:b0 |vpiDirection:1 |vpiLowConn: @@ -47162,7 +47162,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (b1), line:12:21, endln:12:23 |vpiParent: - \_module: work@oh_oai221 (work@oh_oai221), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai221.v, line:7:1, endln:19:10 + \_module_inst: work@oh_oai221 (work@oh_oai221), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai221.v, line:7:1, endln:19:10 |vpiName:b1 |vpiDirection:1 |vpiLowConn: @@ -47202,7 +47202,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (c0), line:13:21, endln:13:23 |vpiParent: - \_module: work@oh_oai221 (work@oh_oai221), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai221.v, line:7:1, endln:19:10 + \_module_inst: work@oh_oai221 (work@oh_oai221), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai221.v, line:7:1, endln:19:10 |vpiName:c0 |vpiDirection:1 |vpiLowConn: @@ -47242,7 +47242,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (z), line:14:21, endln:14:22 |vpiParent: - \_module: work@oh_oai221 (work@oh_oai221), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai221.v, line:7:1, endln:19:10 + \_module_inst: work@oh_oai221 (work@oh_oai221), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai221.v, line:7:1, endln:19:10 |vpiName:z |vpiDirection:2 |vpiLowConn: @@ -47282,7 +47282,7 @@ design: (work@oh_fifo_async) |vpiContAssign: \_cont_assign: , line:17:11, endln:17:46 |vpiParent: - \_module: work@oh_oai221 (work@oh_oai221), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai221.v, line:7:1, endln:19:10 + \_module_inst: work@oh_oai221 (work@oh_oai221), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai221.v, line:7:1, endln:19:10 |vpiRhs: \_operation: , line:17:15, endln:17:46 |vpiParent: @@ -47345,14 +47345,14 @@ design: (work@oh_fifo_async) |vpiName:z |vpiFullName:work@oh_oai221.z |uhdmallModules: -\_module: work@oh_oai222 (work@oh_oai222), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai222.v, line:7:1, endln:20:10 +\_module_inst: work@oh_oai222 (work@oh_oai222), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai222.v, line:7:1, endln:20:10 |vpiParent: \_design: (work@oh_fifo_async) |vpiFullName:work@oh_oai222 |vpiParameter: \_parameter: (work@oh_oai222.DW), line:7:30, endln:7:32 |vpiParent: - \_module: work@oh_oai222 (work@oh_oai222), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai222.v, line:7:1, endln:20:10 + \_module_inst: work@oh_oai222 (work@oh_oai222), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai222.v, line:7:1, endln:20:10 |UINT:1 |vpiTypespec: \_int_typespec: @@ -47361,7 +47361,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:7:30, endln:7:36 |vpiParent: - \_module: work@oh_oai222 (work@oh_oai222), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai222.v, line:7:1, endln:20:10 + \_module_inst: work@oh_oai222 (work@oh_oai222), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai222.v, line:7:1, endln:20:10 |vpiRhs: \_constant: , line:7:35, endln:7:36 |vpiDecompile:1 @@ -47377,49 +47377,49 @@ design: (work@oh_fifo_async) |vpiNet: \_logic_net: (work@oh_oai222.a0), line:9:21, endln:9:23 |vpiParent: - \_module: work@oh_oai222 (work@oh_oai222), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai222.v, line:7:1, endln:20:10 + \_module_inst: work@oh_oai222 (work@oh_oai222), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai222.v, line:7:1, endln:20:10 |vpiName:a0 |vpiFullName:work@oh_oai222.a0 |vpiNet: \_logic_net: (work@oh_oai222.a1), line:10:21, endln:10:23 |vpiParent: - \_module: work@oh_oai222 (work@oh_oai222), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai222.v, line:7:1, endln:20:10 + \_module_inst: work@oh_oai222 (work@oh_oai222), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai222.v, line:7:1, endln:20:10 |vpiName:a1 |vpiFullName:work@oh_oai222.a1 |vpiNet: \_logic_net: (work@oh_oai222.b0), line:11:21, endln:11:23 |vpiParent: - \_module: work@oh_oai222 (work@oh_oai222), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai222.v, line:7:1, endln:20:10 + \_module_inst: work@oh_oai222 (work@oh_oai222), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai222.v, line:7:1, endln:20:10 |vpiName:b0 |vpiFullName:work@oh_oai222.b0 |vpiNet: \_logic_net: (work@oh_oai222.b1), line:12:21, endln:12:23 |vpiParent: - \_module: work@oh_oai222 (work@oh_oai222), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai222.v, line:7:1, endln:20:10 + \_module_inst: work@oh_oai222 (work@oh_oai222), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai222.v, line:7:1, endln:20:10 |vpiName:b1 |vpiFullName:work@oh_oai222.b1 |vpiNet: \_logic_net: (work@oh_oai222.c0), line:13:21, endln:13:23 |vpiParent: - \_module: work@oh_oai222 (work@oh_oai222), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai222.v, line:7:1, endln:20:10 + \_module_inst: work@oh_oai222 (work@oh_oai222), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai222.v, line:7:1, endln:20:10 |vpiName:c0 |vpiFullName:work@oh_oai222.c0 |vpiNet: \_logic_net: (work@oh_oai222.c1), line:14:21, endln:14:23 |vpiParent: - \_module: work@oh_oai222 (work@oh_oai222), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai222.v, line:7:1, endln:20:10 + \_module_inst: work@oh_oai222 (work@oh_oai222), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai222.v, line:7:1, endln:20:10 |vpiName:c1 |vpiFullName:work@oh_oai222.c1 |vpiNet: \_logic_net: (work@oh_oai222.z), line:15:21, endln:15:22 |vpiParent: - \_module: work@oh_oai222 (work@oh_oai222), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai222.v, line:7:1, endln:20:10 + \_module_inst: work@oh_oai222 (work@oh_oai222), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai222.v, line:7:1, endln:20:10 |vpiName:z |vpiFullName:work@oh_oai222.z |vpiPort: \_port: (a0), line:9:21, endln:9:23 |vpiParent: - \_module: work@oh_oai222 (work@oh_oai222), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai222.v, line:7:1, endln:20:10 + \_module_inst: work@oh_oai222 (work@oh_oai222), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai222.v, line:7:1, endln:20:10 |vpiName:a0 |vpiDirection:1 |vpiLowConn: @@ -47459,7 +47459,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (a1), line:10:21, endln:10:23 |vpiParent: - \_module: work@oh_oai222 (work@oh_oai222), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai222.v, line:7:1, endln:20:10 + \_module_inst: work@oh_oai222 (work@oh_oai222), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai222.v, line:7:1, endln:20:10 |vpiName:a1 |vpiDirection:1 |vpiLowConn: @@ -47499,7 +47499,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (b0), line:11:21, endln:11:23 |vpiParent: - \_module: work@oh_oai222 (work@oh_oai222), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai222.v, line:7:1, endln:20:10 + \_module_inst: work@oh_oai222 (work@oh_oai222), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai222.v, line:7:1, endln:20:10 |vpiName:b0 |vpiDirection:1 |vpiLowConn: @@ -47539,7 +47539,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (b1), line:12:21, endln:12:23 |vpiParent: - \_module: work@oh_oai222 (work@oh_oai222), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai222.v, line:7:1, endln:20:10 + \_module_inst: work@oh_oai222 (work@oh_oai222), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai222.v, line:7:1, endln:20:10 |vpiName:b1 |vpiDirection:1 |vpiLowConn: @@ -47579,7 +47579,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (c0), line:13:21, endln:13:23 |vpiParent: - \_module: work@oh_oai222 (work@oh_oai222), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai222.v, line:7:1, endln:20:10 + \_module_inst: work@oh_oai222 (work@oh_oai222), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai222.v, line:7:1, endln:20:10 |vpiName:c0 |vpiDirection:1 |vpiLowConn: @@ -47619,7 +47619,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (c1), line:14:21, endln:14:23 |vpiParent: - \_module: work@oh_oai222 (work@oh_oai222), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai222.v, line:7:1, endln:20:10 + \_module_inst: work@oh_oai222 (work@oh_oai222), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai222.v, line:7:1, endln:20:10 |vpiName:c1 |vpiDirection:1 |vpiLowConn: @@ -47659,7 +47659,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (z), line:15:21, endln:15:22 |vpiParent: - \_module: work@oh_oai222 (work@oh_oai222), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai222.v, line:7:1, endln:20:10 + \_module_inst: work@oh_oai222 (work@oh_oai222), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai222.v, line:7:1, endln:20:10 |vpiName:z |vpiDirection:2 |vpiLowConn: @@ -47699,7 +47699,7 @@ design: (work@oh_fifo_async) |vpiContAssign: \_cont_assign: , line:18:11, endln:18:51 |vpiParent: - \_module: work@oh_oai222 (work@oh_oai222), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai222.v, line:7:1, endln:20:10 + \_module_inst: work@oh_oai222 (work@oh_oai222), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai222.v, line:7:1, endln:20:10 |vpiRhs: \_operation: , line:18:15, endln:18:51 |vpiParent: @@ -47773,14 +47773,14 @@ design: (work@oh_fifo_async) |vpiName:z |vpiFullName:work@oh_oai222.z |uhdmallModules: -\_module: work@oh_oai31 (work@oh_oai31), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai31.v, line:7:1, endln:18:10 +\_module_inst: work@oh_oai31 (work@oh_oai31), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai31.v, line:7:1, endln:18:10 |vpiParent: \_design: (work@oh_fifo_async) |vpiFullName:work@oh_oai31 |vpiParameter: \_parameter: (work@oh_oai31.DW), line:7:29, endln:7:31 |vpiParent: - \_module: work@oh_oai31 (work@oh_oai31), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai31.v, line:7:1, endln:18:10 + \_module_inst: work@oh_oai31 (work@oh_oai31), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai31.v, line:7:1, endln:18:10 |UINT:1 |vpiTypespec: \_int_typespec: @@ -47789,7 +47789,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:7:29, endln:7:35 |vpiParent: - \_module: work@oh_oai31 (work@oh_oai31), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai31.v, line:7:1, endln:18:10 + \_module_inst: work@oh_oai31 (work@oh_oai31), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai31.v, line:7:1, endln:18:10 |vpiRhs: \_constant: , line:7:34, endln:7:35 |vpiDecompile:1 @@ -47805,37 +47805,37 @@ design: (work@oh_fifo_async) |vpiNet: \_logic_net: (work@oh_oai31.a0), line:9:21, endln:9:23 |vpiParent: - \_module: work@oh_oai31 (work@oh_oai31), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai31.v, line:7:1, endln:18:10 + \_module_inst: work@oh_oai31 (work@oh_oai31), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai31.v, line:7:1, endln:18:10 |vpiName:a0 |vpiFullName:work@oh_oai31.a0 |vpiNet: \_logic_net: (work@oh_oai31.a1), line:10:21, endln:10:23 |vpiParent: - \_module: work@oh_oai31 (work@oh_oai31), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai31.v, line:7:1, endln:18:10 + \_module_inst: work@oh_oai31 (work@oh_oai31), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai31.v, line:7:1, endln:18:10 |vpiName:a1 |vpiFullName:work@oh_oai31.a1 |vpiNet: \_logic_net: (work@oh_oai31.a2), line:11:21, endln:11:23 |vpiParent: - \_module: work@oh_oai31 (work@oh_oai31), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai31.v, line:7:1, endln:18:10 + \_module_inst: work@oh_oai31 (work@oh_oai31), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai31.v, line:7:1, endln:18:10 |vpiName:a2 |vpiFullName:work@oh_oai31.a2 |vpiNet: \_logic_net: (work@oh_oai31.b0), line:12:21, endln:12:23 |vpiParent: - \_module: work@oh_oai31 (work@oh_oai31), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai31.v, line:7:1, endln:18:10 + \_module_inst: work@oh_oai31 (work@oh_oai31), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai31.v, line:7:1, endln:18:10 |vpiName:b0 |vpiFullName:work@oh_oai31.b0 |vpiNet: \_logic_net: (work@oh_oai31.z), line:13:21, endln:13:22 |vpiParent: - \_module: work@oh_oai31 (work@oh_oai31), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai31.v, line:7:1, endln:18:10 + \_module_inst: work@oh_oai31 (work@oh_oai31), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai31.v, line:7:1, endln:18:10 |vpiName:z |vpiFullName:work@oh_oai31.z |vpiPort: \_port: (a0), line:9:21, endln:9:23 |vpiParent: - \_module: work@oh_oai31 (work@oh_oai31), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai31.v, line:7:1, endln:18:10 + \_module_inst: work@oh_oai31 (work@oh_oai31), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai31.v, line:7:1, endln:18:10 |vpiName:a0 |vpiDirection:1 |vpiLowConn: @@ -47875,7 +47875,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (a1), line:10:21, endln:10:23 |vpiParent: - \_module: work@oh_oai31 (work@oh_oai31), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai31.v, line:7:1, endln:18:10 + \_module_inst: work@oh_oai31 (work@oh_oai31), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai31.v, line:7:1, endln:18:10 |vpiName:a1 |vpiDirection:1 |vpiLowConn: @@ -47915,7 +47915,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (a2), line:11:21, endln:11:23 |vpiParent: - \_module: work@oh_oai31 (work@oh_oai31), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai31.v, line:7:1, endln:18:10 + \_module_inst: work@oh_oai31 (work@oh_oai31), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai31.v, line:7:1, endln:18:10 |vpiName:a2 |vpiDirection:1 |vpiLowConn: @@ -47955,7 +47955,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (b0), line:12:21, endln:12:23 |vpiParent: - \_module: work@oh_oai31 (work@oh_oai31), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai31.v, line:7:1, endln:18:10 + \_module_inst: work@oh_oai31 (work@oh_oai31), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai31.v, line:7:1, endln:18:10 |vpiName:b0 |vpiDirection:1 |vpiLowConn: @@ -47995,7 +47995,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (z), line:13:21, endln:13:22 |vpiParent: - \_module: work@oh_oai31 (work@oh_oai31), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai31.v, line:7:1, endln:18:10 + \_module_inst: work@oh_oai31 (work@oh_oai31), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai31.v, line:7:1, endln:18:10 |vpiName:z |vpiDirection:2 |vpiLowConn: @@ -48035,7 +48035,7 @@ design: (work@oh_fifo_async) |vpiContAssign: \_cont_assign: , line:16:11, endln:16:37 |vpiParent: - \_module: work@oh_oai31 (work@oh_oai31), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai31.v, line:7:1, endln:18:10 + \_module_inst: work@oh_oai31 (work@oh_oai31), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai31.v, line:7:1, endln:18:10 |vpiRhs: \_operation: , line:16:15, endln:16:37 |vpiParent: @@ -48087,14 +48087,14 @@ design: (work@oh_fifo_async) |vpiName:z |vpiFullName:work@oh_oai31.z |uhdmallModules: -\_module: work@oh_oai311 (work@oh_oai311), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai311.v, line:7:1, endln:19:10 +\_module_inst: work@oh_oai311 (work@oh_oai311), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai311.v, line:7:1, endln:19:10 |vpiParent: \_design: (work@oh_fifo_async) |vpiFullName:work@oh_oai311 |vpiParameter: \_parameter: (work@oh_oai311.DW), line:7:30, endln:7:32 |vpiParent: - \_module: work@oh_oai311 (work@oh_oai311), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai311.v, line:7:1, endln:19:10 + \_module_inst: work@oh_oai311 (work@oh_oai311), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai311.v, line:7:1, endln:19:10 |UINT:1 |vpiTypespec: \_int_typespec: @@ -48103,7 +48103,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:7:30, endln:7:36 |vpiParent: - \_module: work@oh_oai311 (work@oh_oai311), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai311.v, line:7:1, endln:19:10 + \_module_inst: work@oh_oai311 (work@oh_oai311), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai311.v, line:7:1, endln:19:10 |vpiRhs: \_constant: , line:7:35, endln:7:36 |vpiDecompile:1 @@ -48119,43 +48119,43 @@ design: (work@oh_fifo_async) |vpiNet: \_logic_net: (work@oh_oai311.a0), line:9:21, endln:9:23 |vpiParent: - \_module: work@oh_oai311 (work@oh_oai311), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai311.v, line:7:1, endln:19:10 + \_module_inst: work@oh_oai311 (work@oh_oai311), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai311.v, line:7:1, endln:19:10 |vpiName:a0 |vpiFullName:work@oh_oai311.a0 |vpiNet: \_logic_net: (work@oh_oai311.a1), line:10:21, endln:10:23 |vpiParent: - \_module: work@oh_oai311 (work@oh_oai311), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai311.v, line:7:1, endln:19:10 + \_module_inst: work@oh_oai311 (work@oh_oai311), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai311.v, line:7:1, endln:19:10 |vpiName:a1 |vpiFullName:work@oh_oai311.a1 |vpiNet: \_logic_net: (work@oh_oai311.a2), line:11:21, endln:11:23 |vpiParent: - \_module: work@oh_oai311 (work@oh_oai311), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai311.v, line:7:1, endln:19:10 + \_module_inst: work@oh_oai311 (work@oh_oai311), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai311.v, line:7:1, endln:19:10 |vpiName:a2 |vpiFullName:work@oh_oai311.a2 |vpiNet: \_logic_net: (work@oh_oai311.b0), line:12:21, endln:12:23 |vpiParent: - \_module: work@oh_oai311 (work@oh_oai311), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai311.v, line:7:1, endln:19:10 + \_module_inst: work@oh_oai311 (work@oh_oai311), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai311.v, line:7:1, endln:19:10 |vpiName:b0 |vpiFullName:work@oh_oai311.b0 |vpiNet: \_logic_net: (work@oh_oai311.c0), line:13:21, endln:13:23 |vpiParent: - \_module: work@oh_oai311 (work@oh_oai311), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai311.v, line:7:1, endln:19:10 + \_module_inst: work@oh_oai311 (work@oh_oai311), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai311.v, line:7:1, endln:19:10 |vpiName:c0 |vpiFullName:work@oh_oai311.c0 |vpiNet: \_logic_net: (work@oh_oai311.z), line:14:21, endln:14:22 |vpiParent: - \_module: work@oh_oai311 (work@oh_oai311), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai311.v, line:7:1, endln:19:10 + \_module_inst: work@oh_oai311 (work@oh_oai311), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai311.v, line:7:1, endln:19:10 |vpiName:z |vpiFullName:work@oh_oai311.z |vpiPort: \_port: (a0), line:9:21, endln:9:23 |vpiParent: - \_module: work@oh_oai311 (work@oh_oai311), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai311.v, line:7:1, endln:19:10 + \_module_inst: work@oh_oai311 (work@oh_oai311), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai311.v, line:7:1, endln:19:10 |vpiName:a0 |vpiDirection:1 |vpiLowConn: @@ -48195,7 +48195,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (a1), line:10:21, endln:10:23 |vpiParent: - \_module: work@oh_oai311 (work@oh_oai311), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai311.v, line:7:1, endln:19:10 + \_module_inst: work@oh_oai311 (work@oh_oai311), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai311.v, line:7:1, endln:19:10 |vpiName:a1 |vpiDirection:1 |vpiLowConn: @@ -48235,7 +48235,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (a2), line:11:21, endln:11:23 |vpiParent: - \_module: work@oh_oai311 (work@oh_oai311), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai311.v, line:7:1, endln:19:10 + \_module_inst: work@oh_oai311 (work@oh_oai311), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai311.v, line:7:1, endln:19:10 |vpiName:a2 |vpiDirection:1 |vpiLowConn: @@ -48275,7 +48275,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (b0), line:12:21, endln:12:23 |vpiParent: - \_module: work@oh_oai311 (work@oh_oai311), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai311.v, line:7:1, endln:19:10 + \_module_inst: work@oh_oai311 (work@oh_oai311), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai311.v, line:7:1, endln:19:10 |vpiName:b0 |vpiDirection:1 |vpiLowConn: @@ -48315,7 +48315,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (c0), line:13:21, endln:13:23 |vpiParent: - \_module: work@oh_oai311 (work@oh_oai311), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai311.v, line:7:1, endln:19:10 + \_module_inst: work@oh_oai311 (work@oh_oai311), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai311.v, line:7:1, endln:19:10 |vpiName:c0 |vpiDirection:1 |vpiLowConn: @@ -48355,7 +48355,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (z), line:14:21, endln:14:22 |vpiParent: - \_module: work@oh_oai311 (work@oh_oai311), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai311.v, line:7:1, endln:19:10 + \_module_inst: work@oh_oai311 (work@oh_oai311), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai311.v, line:7:1, endln:19:10 |vpiName:z |vpiDirection:2 |vpiLowConn: @@ -48395,7 +48395,7 @@ design: (work@oh_fifo_async) |vpiContAssign: \_cont_assign: , line:17:11, endln:17:42 |vpiParent: - \_module: work@oh_oai311 (work@oh_oai311), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai311.v, line:7:1, endln:19:10 + \_module_inst: work@oh_oai311 (work@oh_oai311), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai311.v, line:7:1, endln:19:10 |vpiRhs: \_operation: , line:17:15, endln:17:42 |vpiParent: @@ -48458,14 +48458,14 @@ design: (work@oh_fifo_async) |vpiName:z |vpiFullName:work@oh_oai311.z |uhdmallModules: -\_module: work@oh_oai32 (work@oh_oai32), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai32.v, line:7:1, endln:19:10 +\_module_inst: work@oh_oai32 (work@oh_oai32), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai32.v, line:7:1, endln:19:10 |vpiParent: \_design: (work@oh_fifo_async) |vpiFullName:work@oh_oai32 |vpiParameter: \_parameter: (work@oh_oai32.DW), line:7:29, endln:7:31 |vpiParent: - \_module: work@oh_oai32 (work@oh_oai32), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai32.v, line:7:1, endln:19:10 + \_module_inst: work@oh_oai32 (work@oh_oai32), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai32.v, line:7:1, endln:19:10 |UINT:1 |vpiTypespec: \_int_typespec: @@ -48474,7 +48474,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:7:29, endln:7:35 |vpiParent: - \_module: work@oh_oai32 (work@oh_oai32), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai32.v, line:7:1, endln:19:10 + \_module_inst: work@oh_oai32 (work@oh_oai32), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai32.v, line:7:1, endln:19:10 |vpiRhs: \_constant: , line:7:34, endln:7:35 |vpiDecompile:1 @@ -48490,43 +48490,43 @@ design: (work@oh_fifo_async) |vpiNet: \_logic_net: (work@oh_oai32.a0), line:9:21, endln:9:23 |vpiParent: - \_module: work@oh_oai32 (work@oh_oai32), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai32.v, line:7:1, endln:19:10 + \_module_inst: work@oh_oai32 (work@oh_oai32), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai32.v, line:7:1, endln:19:10 |vpiName:a0 |vpiFullName:work@oh_oai32.a0 |vpiNet: \_logic_net: (work@oh_oai32.a1), line:10:21, endln:10:23 |vpiParent: - \_module: work@oh_oai32 (work@oh_oai32), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai32.v, line:7:1, endln:19:10 + \_module_inst: work@oh_oai32 (work@oh_oai32), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai32.v, line:7:1, endln:19:10 |vpiName:a1 |vpiFullName:work@oh_oai32.a1 |vpiNet: \_logic_net: (work@oh_oai32.a2), line:11:21, endln:11:23 |vpiParent: - \_module: work@oh_oai32 (work@oh_oai32), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai32.v, line:7:1, endln:19:10 + \_module_inst: work@oh_oai32 (work@oh_oai32), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai32.v, line:7:1, endln:19:10 |vpiName:a2 |vpiFullName:work@oh_oai32.a2 |vpiNet: \_logic_net: (work@oh_oai32.b0), line:12:21, endln:12:23 |vpiParent: - \_module: work@oh_oai32 (work@oh_oai32), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai32.v, line:7:1, endln:19:10 + \_module_inst: work@oh_oai32 (work@oh_oai32), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai32.v, line:7:1, endln:19:10 |vpiName:b0 |vpiFullName:work@oh_oai32.b0 |vpiNet: \_logic_net: (work@oh_oai32.b1), line:13:21, endln:13:23 |vpiParent: - \_module: work@oh_oai32 (work@oh_oai32), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai32.v, line:7:1, endln:19:10 + \_module_inst: work@oh_oai32 (work@oh_oai32), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai32.v, line:7:1, endln:19:10 |vpiName:b1 |vpiFullName:work@oh_oai32.b1 |vpiNet: \_logic_net: (work@oh_oai32.z), line:14:21, endln:14:22 |vpiParent: - \_module: work@oh_oai32 (work@oh_oai32), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai32.v, line:7:1, endln:19:10 + \_module_inst: work@oh_oai32 (work@oh_oai32), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai32.v, line:7:1, endln:19:10 |vpiName:z |vpiFullName:work@oh_oai32.z |vpiPort: \_port: (a0), line:9:21, endln:9:23 |vpiParent: - \_module: work@oh_oai32 (work@oh_oai32), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai32.v, line:7:1, endln:19:10 + \_module_inst: work@oh_oai32 (work@oh_oai32), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai32.v, line:7:1, endln:19:10 |vpiName:a0 |vpiDirection:1 |vpiLowConn: @@ -48566,7 +48566,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (a1), line:10:21, endln:10:23 |vpiParent: - \_module: work@oh_oai32 (work@oh_oai32), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai32.v, line:7:1, endln:19:10 + \_module_inst: work@oh_oai32 (work@oh_oai32), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai32.v, line:7:1, endln:19:10 |vpiName:a1 |vpiDirection:1 |vpiLowConn: @@ -48606,7 +48606,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (a2), line:11:21, endln:11:23 |vpiParent: - \_module: work@oh_oai32 (work@oh_oai32), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai32.v, line:7:1, endln:19:10 + \_module_inst: work@oh_oai32 (work@oh_oai32), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai32.v, line:7:1, endln:19:10 |vpiName:a2 |vpiDirection:1 |vpiLowConn: @@ -48646,7 +48646,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (b0), line:12:21, endln:12:23 |vpiParent: - \_module: work@oh_oai32 (work@oh_oai32), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai32.v, line:7:1, endln:19:10 + \_module_inst: work@oh_oai32 (work@oh_oai32), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai32.v, line:7:1, endln:19:10 |vpiName:b0 |vpiDirection:1 |vpiLowConn: @@ -48686,7 +48686,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (b1), line:13:21, endln:13:23 |vpiParent: - \_module: work@oh_oai32 (work@oh_oai32), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai32.v, line:7:1, endln:19:10 + \_module_inst: work@oh_oai32 (work@oh_oai32), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai32.v, line:7:1, endln:19:10 |vpiName:b1 |vpiDirection:1 |vpiLowConn: @@ -48726,7 +48726,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (z), line:14:21, endln:14:22 |vpiParent: - \_module: work@oh_oai32 (work@oh_oai32), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai32.v, line:7:1, endln:19:10 + \_module_inst: work@oh_oai32 (work@oh_oai32), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai32.v, line:7:1, endln:19:10 |vpiName:z |vpiDirection:2 |vpiLowConn: @@ -48766,7 +48766,7 @@ design: (work@oh_fifo_async) |vpiContAssign: \_cont_assign: , line:17:11, endln:17:44 |vpiParent: - \_module: work@oh_oai32 (work@oh_oai32), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai32.v, line:7:1, endln:19:10 + \_module_inst: work@oh_oai32 (work@oh_oai32), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai32.v, line:7:1, endln:19:10 |vpiRhs: \_operation: , line:17:15, endln:17:44 |vpiParent: @@ -48829,14 +48829,14 @@ design: (work@oh_fifo_async) |vpiName:z |vpiFullName:work@oh_oai32.z |uhdmallModules: -\_module: work@oh_oai33 (work@oh_oai33), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai33.v, line:7:1, endln:20:10 +\_module_inst: work@oh_oai33 (work@oh_oai33), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai33.v, line:7:1, endln:20:10 |vpiParent: \_design: (work@oh_fifo_async) |vpiFullName:work@oh_oai33 |vpiParameter: \_parameter: (work@oh_oai33.DW), line:7:29, endln:7:31 |vpiParent: - \_module: work@oh_oai33 (work@oh_oai33), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai33.v, line:7:1, endln:20:10 + \_module_inst: work@oh_oai33 (work@oh_oai33), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai33.v, line:7:1, endln:20:10 |UINT:1 |vpiTypespec: \_int_typespec: @@ -48845,7 +48845,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:7:29, endln:7:35 |vpiParent: - \_module: work@oh_oai33 (work@oh_oai33), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai33.v, line:7:1, endln:20:10 + \_module_inst: work@oh_oai33 (work@oh_oai33), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai33.v, line:7:1, endln:20:10 |vpiRhs: \_constant: , line:7:34, endln:7:35 |vpiDecompile:1 @@ -48861,49 +48861,49 @@ design: (work@oh_fifo_async) |vpiNet: \_logic_net: (work@oh_oai33.a0), line:9:21, endln:9:23 |vpiParent: - \_module: work@oh_oai33 (work@oh_oai33), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai33.v, line:7:1, endln:20:10 + \_module_inst: work@oh_oai33 (work@oh_oai33), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai33.v, line:7:1, endln:20:10 |vpiName:a0 |vpiFullName:work@oh_oai33.a0 |vpiNet: \_logic_net: (work@oh_oai33.a1), line:10:21, endln:10:23 |vpiParent: - \_module: work@oh_oai33 (work@oh_oai33), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai33.v, line:7:1, endln:20:10 + \_module_inst: work@oh_oai33 (work@oh_oai33), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai33.v, line:7:1, endln:20:10 |vpiName:a1 |vpiFullName:work@oh_oai33.a1 |vpiNet: \_logic_net: (work@oh_oai33.a2), line:11:21, endln:11:23 |vpiParent: - \_module: work@oh_oai33 (work@oh_oai33), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai33.v, line:7:1, endln:20:10 + \_module_inst: work@oh_oai33 (work@oh_oai33), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai33.v, line:7:1, endln:20:10 |vpiName:a2 |vpiFullName:work@oh_oai33.a2 |vpiNet: \_logic_net: (work@oh_oai33.b0), line:12:21, endln:12:23 |vpiParent: - \_module: work@oh_oai33 (work@oh_oai33), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai33.v, line:7:1, endln:20:10 + \_module_inst: work@oh_oai33 (work@oh_oai33), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai33.v, line:7:1, endln:20:10 |vpiName:b0 |vpiFullName:work@oh_oai33.b0 |vpiNet: \_logic_net: (work@oh_oai33.b1), line:13:21, endln:13:23 |vpiParent: - \_module: work@oh_oai33 (work@oh_oai33), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai33.v, line:7:1, endln:20:10 + \_module_inst: work@oh_oai33 (work@oh_oai33), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai33.v, line:7:1, endln:20:10 |vpiName:b1 |vpiFullName:work@oh_oai33.b1 |vpiNet: \_logic_net: (work@oh_oai33.b2), line:14:21, endln:14:23 |vpiParent: - \_module: work@oh_oai33 (work@oh_oai33), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai33.v, line:7:1, endln:20:10 + \_module_inst: work@oh_oai33 (work@oh_oai33), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai33.v, line:7:1, endln:20:10 |vpiName:b2 |vpiFullName:work@oh_oai33.b2 |vpiNet: \_logic_net: (work@oh_oai33.z), line:15:21, endln:15:22 |vpiParent: - \_module: work@oh_oai33 (work@oh_oai33), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai33.v, line:7:1, endln:20:10 + \_module_inst: work@oh_oai33 (work@oh_oai33), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai33.v, line:7:1, endln:20:10 |vpiName:z |vpiFullName:work@oh_oai33.z |vpiPort: \_port: (a0), line:9:21, endln:9:23 |vpiParent: - \_module: work@oh_oai33 (work@oh_oai33), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai33.v, line:7:1, endln:20:10 + \_module_inst: work@oh_oai33 (work@oh_oai33), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai33.v, line:7:1, endln:20:10 |vpiName:a0 |vpiDirection:1 |vpiLowConn: @@ -48943,7 +48943,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (a1), line:10:21, endln:10:23 |vpiParent: - \_module: work@oh_oai33 (work@oh_oai33), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai33.v, line:7:1, endln:20:10 + \_module_inst: work@oh_oai33 (work@oh_oai33), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai33.v, line:7:1, endln:20:10 |vpiName:a1 |vpiDirection:1 |vpiLowConn: @@ -48983,7 +48983,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (a2), line:11:21, endln:11:23 |vpiParent: - \_module: work@oh_oai33 (work@oh_oai33), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai33.v, line:7:1, endln:20:10 + \_module_inst: work@oh_oai33 (work@oh_oai33), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai33.v, line:7:1, endln:20:10 |vpiName:a2 |vpiDirection:1 |vpiLowConn: @@ -49023,7 +49023,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (b0), line:12:21, endln:12:23 |vpiParent: - \_module: work@oh_oai33 (work@oh_oai33), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai33.v, line:7:1, endln:20:10 + \_module_inst: work@oh_oai33 (work@oh_oai33), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai33.v, line:7:1, endln:20:10 |vpiName:b0 |vpiDirection:1 |vpiLowConn: @@ -49063,7 +49063,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (b1), line:13:21, endln:13:23 |vpiParent: - \_module: work@oh_oai33 (work@oh_oai33), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai33.v, line:7:1, endln:20:10 + \_module_inst: work@oh_oai33 (work@oh_oai33), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai33.v, line:7:1, endln:20:10 |vpiName:b1 |vpiDirection:1 |vpiLowConn: @@ -49103,7 +49103,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (b2), line:14:21, endln:14:23 |vpiParent: - \_module: work@oh_oai33 (work@oh_oai33), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai33.v, line:7:1, endln:20:10 + \_module_inst: work@oh_oai33 (work@oh_oai33), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai33.v, line:7:1, endln:20:10 |vpiName:b2 |vpiDirection:1 |vpiLowConn: @@ -49143,7 +49143,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (z), line:15:21, endln:15:22 |vpiParent: - \_module: work@oh_oai33 (work@oh_oai33), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai33.v, line:7:1, endln:20:10 + \_module_inst: work@oh_oai33 (work@oh_oai33), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai33.v, line:7:1, endln:20:10 |vpiName:z |vpiDirection:2 |vpiLowConn: @@ -49183,7 +49183,7 @@ design: (work@oh_fifo_async) |vpiContAssign: \_cont_assign: , line:18:11, endln:18:49 |vpiParent: - \_module: work@oh_oai33 (work@oh_oai33), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai33.v, line:7:1, endln:20:10 + \_module_inst: work@oh_oai33 (work@oh_oai33), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai33.v, line:7:1, endln:20:10 |vpiRhs: \_operation: , line:18:15, endln:18:49 |vpiParent: @@ -49257,14 +49257,14 @@ design: (work@oh_fifo_async) |vpiName:z |vpiFullName:work@oh_oai33.z |uhdmallModules: -\_module: work@oh_oddr (work@oh_oddr), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oddr.v, line:8:1, endln:43:10 +\_module_inst: work@oh_oddr (work@oh_oddr), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oddr.v, line:8:1, endln:43:10 |vpiParent: \_design: (work@oh_fifo_async) |vpiFullName:work@oh_oddr |vpiParameter: \_parameter: (work@oh_oddr.N), line:9:15, endln:9:16 |vpiParent: - \_module: work@oh_oddr (work@oh_oddr), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oddr.v, line:8:1, endln:43:10 + \_module_inst: work@oh_oddr (work@oh_oddr), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oddr.v, line:8:1, endln:43:10 |UINT:1 |vpiTypespec: \_int_typespec: @@ -49273,7 +49273,7 @@ design: (work@oh_fifo_async) |vpiParameter: \_parameter: (work@oh_oddr.SYN), line:10:15, endln:10:18 |vpiParent: - \_module: work@oh_oddr (work@oh_oddr), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oddr.v, line:8:1, endln:43:10 + \_module_inst: work@oh_oddr (work@oh_oddr), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oddr.v, line:8:1, endln:43:10 |STRING:TRUE |vpiTypespec: \_string_typespec: @@ -49282,7 +49282,7 @@ design: (work@oh_fifo_async) |vpiParameter: \_parameter: (work@oh_oddr.TYPE), line:11:15, endln:11:19 |vpiParent: - \_module: work@oh_oddr (work@oh_oddr), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oddr.v, line:8:1, endln:43:10 + \_module_inst: work@oh_oddr (work@oh_oddr), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oddr.v, line:8:1, endln:43:10 |STRING:DEFAULT |vpiTypespec: \_string_typespec: @@ -49291,7 +49291,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:9:15, endln:9:24 |vpiParent: - \_module: work@oh_oddr (work@oh_oddr), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oddr.v, line:8:1, endln:43:10 + \_module_inst: work@oh_oddr (work@oh_oddr), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oddr.v, line:8:1, endln:43:10 |vpiRhs: \_constant: , line:9:23, endln:9:24 |vpiDecompile:1 @@ -49305,7 +49305,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:10:15, endln:10:28 |vpiParent: - \_module: work@oh_oddr (work@oh_oddr), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oddr.v, line:8:1, endln:43:10 + \_module_inst: work@oh_oddr (work@oh_oddr), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oddr.v, line:8:1, endln:43:10 |vpiRhs: \_constant: , line:10:22, endln:10:28 |vpiDecompile:TRUE @@ -49319,7 +49319,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:11:15, endln:11:31 |vpiParent: - \_module: work@oh_oddr (work@oh_oddr), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oddr.v, line:8:1, endln:43:10 + \_module_inst: work@oh_oddr (work@oh_oddr), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oddr.v, line:8:1, endln:43:10 |vpiRhs: \_constant: , line:11:22, endln:11:31 |vpiDecompile:DEFAULT @@ -49335,31 +49335,31 @@ design: (work@oh_fifo_async) |vpiNet: \_logic_net: (work@oh_oddr.clk), line:14:15, endln:14:18 |vpiParent: - \_module: work@oh_oddr (work@oh_oddr), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oddr.v, line:8:1, endln:43:10 + \_module_inst: work@oh_oddr (work@oh_oddr), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oddr.v, line:8:1, endln:43:10 |vpiName:clk |vpiFullName:work@oh_oddr.clk |vpiNet: \_logic_net: (work@oh_oddr.in1), line:15:20, endln:15:23 |vpiParent: - \_module: work@oh_oddr (work@oh_oddr), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oddr.v, line:8:1, endln:43:10 + \_module_inst: work@oh_oddr (work@oh_oddr), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oddr.v, line:8:1, endln:43:10 |vpiName:in1 |vpiFullName:work@oh_oddr.in1 |vpiNet: \_logic_net: (work@oh_oddr.in2), line:16:20, endln:16:23 |vpiParent: - \_module: work@oh_oddr (work@oh_oddr), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oddr.v, line:8:1, endln:43:10 + \_module_inst: work@oh_oddr (work@oh_oddr), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oddr.v, line:8:1, endln:43:10 |vpiName:in2 |vpiFullName:work@oh_oddr.in2 |vpiNet: \_logic_net: (work@oh_oddr.out), line:17:20, endln:17:23 |vpiParent: - \_module: work@oh_oddr (work@oh_oddr), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oddr.v, line:8:1, endln:43:10 + \_module_inst: work@oh_oddr (work@oh_oddr), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oddr.v, line:8:1, endln:43:10 |vpiName:out |vpiFullName:work@oh_oddr.out |vpiPort: \_port: (clk), line:14:15, endln:14:18 |vpiParent: - \_module: work@oh_oddr (work@oh_oddr), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oddr.v, line:8:1, endln:43:10 + \_module_inst: work@oh_oddr (work@oh_oddr), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oddr.v, line:8:1, endln:43:10 |vpiName:clk |vpiDirection:1 |vpiLowConn: @@ -49371,7 +49371,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (in1), line:15:20, endln:15:23 |vpiParent: - \_module: work@oh_oddr (work@oh_oddr), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oddr.v, line:8:1, endln:43:10 + \_module_inst: work@oh_oddr (work@oh_oddr), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oddr.v, line:8:1, endln:43:10 |vpiName:in1 |vpiDirection:1 |vpiLowConn: @@ -49411,7 +49411,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (in2), line:16:20, endln:16:23 |vpiParent: - \_module: work@oh_oddr (work@oh_oddr), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oddr.v, line:8:1, endln:43:10 + \_module_inst: work@oh_oddr (work@oh_oddr), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oddr.v, line:8:1, endln:43:10 |vpiName:in2 |vpiDirection:1 |vpiLowConn: @@ -49451,7 +49451,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (out), line:17:20, endln:17:23 |vpiParent: - \_module: work@oh_oddr (work@oh_oddr), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oddr.v, line:8:1, endln:43:10 + \_module_inst: work@oh_oddr (work@oh_oddr), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oddr.v, line:8:1, endln:43:10 |vpiName:out |vpiDirection:2 |vpiLowConn: @@ -49489,14 +49489,14 @@ design: (work@oh_fifo_async) |UINT:0 |vpiConstType:9 |uhdmallModules: -\_module: work@oh_or2 (work@oh_or2), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_or2.v, line:7:1, endln:16:10 +\_module_inst: work@oh_or2 (work@oh_or2), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_or2.v, line:7:1, endln:16:10 |vpiParent: \_design: (work@oh_fifo_async) |vpiFullName:work@oh_or2 |vpiParameter: \_parameter: (work@oh_or2.DW), line:7:27, endln:7:29 |vpiParent: - \_module: work@oh_or2 (work@oh_or2), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_or2.v, line:7:1, endln:16:10 + \_module_inst: work@oh_or2 (work@oh_or2), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_or2.v, line:7:1, endln:16:10 |UINT:1 |vpiTypespec: \_int_typespec: @@ -49505,7 +49505,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:7:27, endln:7:33 |vpiParent: - \_module: work@oh_or2 (work@oh_or2), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_or2.v, line:7:1, endln:16:10 + \_module_inst: work@oh_or2 (work@oh_or2), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_or2.v, line:7:1, endln:16:10 |vpiRhs: \_constant: , line:7:32, endln:7:33 |vpiDecompile:1 @@ -49521,25 +49521,25 @@ design: (work@oh_fifo_async) |vpiNet: \_logic_net: (work@oh_or2.a), line:9:21, endln:9:22 |vpiParent: - \_module: work@oh_or2 (work@oh_or2), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_or2.v, line:7:1, endln:16:10 + \_module_inst: work@oh_or2 (work@oh_or2), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_or2.v, line:7:1, endln:16:10 |vpiName:a |vpiFullName:work@oh_or2.a |vpiNet: \_logic_net: (work@oh_or2.b), line:10:21, endln:10:22 |vpiParent: - \_module: work@oh_or2 (work@oh_or2), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_or2.v, line:7:1, endln:16:10 + \_module_inst: work@oh_or2 (work@oh_or2), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_or2.v, line:7:1, endln:16:10 |vpiName:b |vpiFullName:work@oh_or2.b |vpiNet: \_logic_net: (work@oh_or2.z), line:11:21, endln:11:22 |vpiParent: - \_module: work@oh_or2 (work@oh_or2), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_or2.v, line:7:1, endln:16:10 + \_module_inst: work@oh_or2 (work@oh_or2), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_or2.v, line:7:1, endln:16:10 |vpiName:z |vpiFullName:work@oh_or2.z |vpiPort: \_port: (a), line:9:21, endln:9:22 |vpiParent: - \_module: work@oh_or2 (work@oh_or2), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_or2.v, line:7:1, endln:16:10 + \_module_inst: work@oh_or2 (work@oh_or2), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_or2.v, line:7:1, endln:16:10 |vpiName:a |vpiDirection:1 |vpiLowConn: @@ -49579,7 +49579,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (b), line:10:21, endln:10:22 |vpiParent: - \_module: work@oh_or2 (work@oh_or2), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_or2.v, line:7:1, endln:16:10 + \_module_inst: work@oh_or2 (work@oh_or2), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_or2.v, line:7:1, endln:16:10 |vpiName:b |vpiDirection:1 |vpiLowConn: @@ -49619,7 +49619,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (z), line:11:21, endln:11:22 |vpiParent: - \_module: work@oh_or2 (work@oh_or2), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_or2.v, line:7:1, endln:16:10 + \_module_inst: work@oh_or2 (work@oh_or2), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_or2.v, line:7:1, endln:16:10 |vpiName:z |vpiDirection:2 |vpiLowConn: @@ -49659,7 +49659,7 @@ design: (work@oh_fifo_async) |vpiContAssign: \_cont_assign: , line:14:11, endln:14:23 |vpiParent: - \_module: work@oh_or2 (work@oh_or2), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_or2.v, line:7:1, endln:16:10 + \_module_inst: work@oh_or2 (work@oh_or2), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_or2.v, line:7:1, endln:16:10 |vpiRhs: \_operation: , line:14:17, endln:14:22 |vpiParent: @@ -49684,14 +49684,14 @@ design: (work@oh_fifo_async) |vpiName:z |vpiFullName:work@oh_or2.z |uhdmallModules: -\_module: work@oh_or3 (work@oh_or3), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_or3.v, line:8:1, endln:18:10 +\_module_inst: work@oh_or3 (work@oh_or3), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_or3.v, line:8:1, endln:18:10 |vpiParent: \_design: (work@oh_fifo_async) |vpiFullName:work@oh_or3 |vpiParameter: \_parameter: (work@oh_or3.DW), line:8:27, endln:8:29 |vpiParent: - \_module: work@oh_or3 (work@oh_or3), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_or3.v, line:8:1, endln:18:10 + \_module_inst: work@oh_or3 (work@oh_or3), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_or3.v, line:8:1, endln:18:10 |UINT:1 |vpiTypespec: \_int_typespec: @@ -49700,7 +49700,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:8:27, endln:8:33 |vpiParent: - \_module: work@oh_or3 (work@oh_or3), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_or3.v, line:8:1, endln:18:10 + \_module_inst: work@oh_or3 (work@oh_or3), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_or3.v, line:8:1, endln:18:10 |vpiRhs: \_constant: , line:8:32, endln:8:33 |vpiDecompile:1 @@ -49716,31 +49716,31 @@ design: (work@oh_fifo_async) |vpiNet: \_logic_net: (work@oh_or3.a), line:10:21, endln:10:22 |vpiParent: - \_module: work@oh_or3 (work@oh_or3), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_or3.v, line:8:1, endln:18:10 + \_module_inst: work@oh_or3 (work@oh_or3), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_or3.v, line:8:1, endln:18:10 |vpiName:a |vpiFullName:work@oh_or3.a |vpiNet: \_logic_net: (work@oh_or3.b), line:11:21, endln:11:22 |vpiParent: - \_module: work@oh_or3 (work@oh_or3), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_or3.v, line:8:1, endln:18:10 + \_module_inst: work@oh_or3 (work@oh_or3), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_or3.v, line:8:1, endln:18:10 |vpiName:b |vpiFullName:work@oh_or3.b |vpiNet: \_logic_net: (work@oh_or3.c), line:12:21, endln:12:22 |vpiParent: - \_module: work@oh_or3 (work@oh_or3), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_or3.v, line:8:1, endln:18:10 + \_module_inst: work@oh_or3 (work@oh_or3), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_or3.v, line:8:1, endln:18:10 |vpiName:c |vpiFullName:work@oh_or3.c |vpiNet: \_logic_net: (work@oh_or3.z), line:13:21, endln:13:22 |vpiParent: - \_module: work@oh_or3 (work@oh_or3), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_or3.v, line:8:1, endln:18:10 + \_module_inst: work@oh_or3 (work@oh_or3), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_or3.v, line:8:1, endln:18:10 |vpiName:z |vpiFullName:work@oh_or3.z |vpiPort: \_port: (a), line:10:21, endln:10:22 |vpiParent: - \_module: work@oh_or3 (work@oh_or3), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_or3.v, line:8:1, endln:18:10 + \_module_inst: work@oh_or3 (work@oh_or3), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_or3.v, line:8:1, endln:18:10 |vpiName:a |vpiDirection:1 |vpiLowConn: @@ -49780,7 +49780,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (b), line:11:21, endln:11:22 |vpiParent: - \_module: work@oh_or3 (work@oh_or3), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_or3.v, line:8:1, endln:18:10 + \_module_inst: work@oh_or3 (work@oh_or3), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_or3.v, line:8:1, endln:18:10 |vpiName:b |vpiDirection:1 |vpiLowConn: @@ -49820,7 +49820,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (c), line:12:21, endln:12:22 |vpiParent: - \_module: work@oh_or3 (work@oh_or3), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_or3.v, line:8:1, endln:18:10 + \_module_inst: work@oh_or3 (work@oh_or3), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_or3.v, line:8:1, endln:18:10 |vpiName:c |vpiDirection:1 |vpiLowConn: @@ -49860,7 +49860,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (z), line:13:21, endln:13:22 |vpiParent: - \_module: work@oh_or3 (work@oh_or3), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_or3.v, line:8:1, endln:18:10 + \_module_inst: work@oh_or3 (work@oh_or3), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_or3.v, line:8:1, endln:18:10 |vpiName:z |vpiDirection:2 |vpiLowConn: @@ -49900,7 +49900,7 @@ design: (work@oh_fifo_async) |vpiContAssign: \_cont_assign: , line:16:11, endln:16:24 |vpiParent: - \_module: work@oh_or3 (work@oh_or3), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_or3.v, line:8:1, endln:18:10 + \_module_inst: work@oh_or3 (work@oh_or3), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_or3.v, line:8:1, endln:18:10 |vpiRhs: \_operation: , line:16:15, endln:16:24 |vpiParent: @@ -49936,14 +49936,14 @@ design: (work@oh_fifo_async) |vpiName:z |vpiFullName:work@oh_or3.z |uhdmallModules: -\_module: work@oh_or4 (work@oh_or4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_or4.v, line:8:1, endln:19:10 +\_module_inst: work@oh_or4 (work@oh_or4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_or4.v, line:8:1, endln:19:10 |vpiParent: \_design: (work@oh_fifo_async) |vpiFullName:work@oh_or4 |vpiParameter: \_parameter: (work@oh_or4.DW), line:8:27, endln:8:29 |vpiParent: - \_module: work@oh_or4 (work@oh_or4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_or4.v, line:8:1, endln:19:10 + \_module_inst: work@oh_or4 (work@oh_or4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_or4.v, line:8:1, endln:19:10 |UINT:1 |vpiTypespec: \_int_typespec: @@ -49952,7 +49952,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:8:27, endln:8:33 |vpiParent: - \_module: work@oh_or4 (work@oh_or4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_or4.v, line:8:1, endln:19:10 + \_module_inst: work@oh_or4 (work@oh_or4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_or4.v, line:8:1, endln:19:10 |vpiRhs: \_constant: , line:8:32, endln:8:33 |vpiDecompile:1 @@ -49968,37 +49968,37 @@ design: (work@oh_fifo_async) |vpiNet: \_logic_net: (work@oh_or4.a), line:10:21, endln:10:22 |vpiParent: - \_module: work@oh_or4 (work@oh_or4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_or4.v, line:8:1, endln:19:10 + \_module_inst: work@oh_or4 (work@oh_or4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_or4.v, line:8:1, endln:19:10 |vpiName:a |vpiFullName:work@oh_or4.a |vpiNet: \_logic_net: (work@oh_or4.b), line:11:21, endln:11:22 |vpiParent: - \_module: work@oh_or4 (work@oh_or4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_or4.v, line:8:1, endln:19:10 + \_module_inst: work@oh_or4 (work@oh_or4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_or4.v, line:8:1, endln:19:10 |vpiName:b |vpiFullName:work@oh_or4.b |vpiNet: \_logic_net: (work@oh_or4.c), line:12:21, endln:12:22 |vpiParent: - \_module: work@oh_or4 (work@oh_or4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_or4.v, line:8:1, endln:19:10 + \_module_inst: work@oh_or4 (work@oh_or4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_or4.v, line:8:1, endln:19:10 |vpiName:c |vpiFullName:work@oh_or4.c |vpiNet: \_logic_net: (work@oh_or4.d), line:13:21, endln:13:22 |vpiParent: - \_module: work@oh_or4 (work@oh_or4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_or4.v, line:8:1, endln:19:10 + \_module_inst: work@oh_or4 (work@oh_or4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_or4.v, line:8:1, endln:19:10 |vpiName:d |vpiFullName:work@oh_or4.d |vpiNet: \_logic_net: (work@oh_or4.z), line:14:21, endln:14:22 |vpiParent: - \_module: work@oh_or4 (work@oh_or4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_or4.v, line:8:1, endln:19:10 + \_module_inst: work@oh_or4 (work@oh_or4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_or4.v, line:8:1, endln:19:10 |vpiName:z |vpiFullName:work@oh_or4.z |vpiPort: \_port: (a), line:10:21, endln:10:22 |vpiParent: - \_module: work@oh_or4 (work@oh_or4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_or4.v, line:8:1, endln:19:10 + \_module_inst: work@oh_or4 (work@oh_or4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_or4.v, line:8:1, endln:19:10 |vpiName:a |vpiDirection:1 |vpiLowConn: @@ -50038,7 +50038,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (b), line:11:21, endln:11:22 |vpiParent: - \_module: work@oh_or4 (work@oh_or4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_or4.v, line:8:1, endln:19:10 + \_module_inst: work@oh_or4 (work@oh_or4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_or4.v, line:8:1, endln:19:10 |vpiName:b |vpiDirection:1 |vpiLowConn: @@ -50078,7 +50078,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (c), line:12:21, endln:12:22 |vpiParent: - \_module: work@oh_or4 (work@oh_or4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_or4.v, line:8:1, endln:19:10 + \_module_inst: work@oh_or4 (work@oh_or4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_or4.v, line:8:1, endln:19:10 |vpiName:c |vpiDirection:1 |vpiLowConn: @@ -50118,7 +50118,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (d), line:13:21, endln:13:22 |vpiParent: - \_module: work@oh_or4 (work@oh_or4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_or4.v, line:8:1, endln:19:10 + \_module_inst: work@oh_or4 (work@oh_or4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_or4.v, line:8:1, endln:19:10 |vpiName:d |vpiDirection:1 |vpiLowConn: @@ -50158,7 +50158,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (z), line:14:21, endln:14:22 |vpiParent: - \_module: work@oh_or4 (work@oh_or4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_or4.v, line:8:1, endln:19:10 + \_module_inst: work@oh_or4 (work@oh_or4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_or4.v, line:8:1, endln:19:10 |vpiName:z |vpiDirection:2 |vpiLowConn: @@ -50198,7 +50198,7 @@ design: (work@oh_fifo_async) |vpiContAssign: \_cont_assign: , line:17:11, endln:17:28 |vpiParent: - \_module: work@oh_or4 (work@oh_or4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_or4.v, line:8:1, endln:19:10 + \_module_inst: work@oh_or4 (work@oh_or4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_or4.v, line:8:1, endln:19:10 |vpiRhs: \_operation: , line:17:15, endln:17:28 |vpiParent: @@ -50245,14 +50245,14 @@ design: (work@oh_fifo_async) |vpiName:z |vpiFullName:work@oh_or4.z |uhdmallModules: -\_module: work@oh_par2ser (work@oh_par2ser), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_par2ser.v, line:8:1, endln:69:10 +\_module_inst: work@oh_par2ser (work@oh_par2ser), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_par2ser.v, line:8:1, endln:69:10 |vpiParent: \_design: (work@oh_fifo_async) |vpiFullName:work@oh_par2ser |vpiParameter: \_parameter: (work@oh_par2ser.PW), line:8:31, endln:8:33 |vpiParent: - \_module: work@oh_par2ser (work@oh_par2ser), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_par2ser.v, line:8:1, endln:69:10 + \_module_inst: work@oh_par2ser (work@oh_par2ser), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_par2ser.v, line:8:1, endln:69:10 |UINT:32 |vpiTypespec: \_int_typespec: @@ -50261,7 +50261,7 @@ design: (work@oh_fifo_async) |vpiParameter: \_parameter: (work@oh_par2ser.SW), line:9:17, endln:9:19 |vpiParent: - \_module: work@oh_par2ser (work@oh_par2ser), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_par2ser.v, line:8:1, endln:69:10 + \_module_inst: work@oh_par2ser (work@oh_par2ser), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_par2ser.v, line:8:1, endln:69:10 |UINT:1 |vpiTypespec: \_int_typespec: @@ -50270,13 +50270,13 @@ design: (work@oh_fifo_async) |vpiParameter: \_parameter: (work@oh_par2ser.CW), line:10:17, endln:10:19 |vpiParent: - \_module: work@oh_par2ser (work@oh_par2ser), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_par2ser.v, line:8:1, endln:69:10 + \_module_inst: work@oh_par2ser (work@oh_par2ser), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_par2ser.v, line:8:1, endln:69:10 |vpiName:CW |vpiFullName:work@oh_par2ser.CW |vpiParamAssign: \_param_assign: , line:8:31, endln:8:38 |vpiParent: - \_module: work@oh_par2ser (work@oh_par2ser), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_par2ser.v, line:8:1, endln:69:10 + \_module_inst: work@oh_par2ser (work@oh_par2ser), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_par2ser.v, line:8:1, endln:69:10 |vpiRhs: \_constant: , line:8:36, endln:8:38 |vpiDecompile:32 @@ -50290,7 +50290,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:9:17, endln:9:23 |vpiParent: - \_module: work@oh_par2ser (work@oh_par2ser), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_par2ser.v, line:8:1, endln:69:10 + \_module_inst: work@oh_par2ser (work@oh_par2ser), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_par2ser.v, line:8:1, endln:69:10 |vpiRhs: \_constant: , line:9:22, endln:9:23 |vpiDecompile:1 @@ -50304,7 +50304,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:10:17, endln:10:35 |vpiParent: - \_module: work@oh_par2ser (work@oh_par2ser), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_par2ser.v, line:8:1, endln:69:10 + \_module_inst: work@oh_par2ser (work@oh_par2ser), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_par2ser.v, line:8:1, endln:69:10 |vpiRhs: \_sys_func_call: ($clog2), line:10:22, endln:10:35 |vpiArgument: @@ -50330,107 +50330,107 @@ design: (work@oh_fifo_async) |vpiNet: \_logic_net: (work@oh_par2ser.clk), line:13:16, endln:13:19 |vpiParent: - \_module: work@oh_par2ser (work@oh_par2ser), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_par2ser.v, line:8:1, endln:69:10 + \_module_inst: work@oh_par2ser (work@oh_par2ser), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_par2ser.v, line:8:1, endln:69:10 |vpiName:clk |vpiFullName:work@oh_par2ser.clk |vpiNet: \_logic_net: (work@oh_par2ser.nreset), line:14:16, endln:14:22 |vpiParent: - \_module: work@oh_par2ser (work@oh_par2ser), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_par2ser.v, line:8:1, endln:69:10 + \_module_inst: work@oh_par2ser (work@oh_par2ser), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_par2ser.v, line:8:1, endln:69:10 |vpiName:nreset |vpiFullName:work@oh_par2ser.nreset |vpiNet: \_logic_net: (work@oh_par2ser.din), line:15:21, endln:15:24 |vpiParent: - \_module: work@oh_par2ser (work@oh_par2ser), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_par2ser.v, line:8:1, endln:69:10 + \_module_inst: work@oh_par2ser (work@oh_par2ser), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_par2ser.v, line:8:1, endln:69:10 |vpiName:din |vpiFullName:work@oh_par2ser.din |vpiNet: \_logic_net: (work@oh_par2ser.dout), line:16:21, endln:16:25 |vpiParent: - \_module: work@oh_par2ser (work@oh_par2ser), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_par2ser.v, line:8:1, endln:69:10 + \_module_inst: work@oh_par2ser (work@oh_par2ser), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_par2ser.v, line:8:1, endln:69:10 |vpiName:dout |vpiFullName:work@oh_par2ser.dout |vpiNet: \_logic_net: (work@oh_par2ser.access_out), line:17:17, endln:17:27 |vpiParent: - \_module: work@oh_par2ser (work@oh_par2ser), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_par2ser.v, line:8:1, endln:69:10 + \_module_inst: work@oh_par2ser (work@oh_par2ser), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_par2ser.v, line:8:1, endln:69:10 |vpiName:access_out |vpiFullName:work@oh_par2ser.access_out |vpiNet: \_logic_net: (work@oh_par2ser.load), line:18:16, endln:18:20 |vpiParent: - \_module: work@oh_par2ser (work@oh_par2ser), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_par2ser.v, line:8:1, endln:69:10 + \_module_inst: work@oh_par2ser (work@oh_par2ser), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_par2ser.v, line:8:1, endln:69:10 |vpiName:load |vpiFullName:work@oh_par2ser.load |vpiNet: \_logic_net: (work@oh_par2ser.shift), line:19:16, endln:19:21 |vpiParent: - \_module: work@oh_par2ser (work@oh_par2ser), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_par2ser.v, line:8:1, endln:69:10 + \_module_inst: work@oh_par2ser (work@oh_par2ser), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_par2ser.v, line:8:1, endln:69:10 |vpiName:shift |vpiFullName:work@oh_par2ser.shift |vpiNet: \_logic_net: (work@oh_par2ser.datasize), line:20:21, endln:20:29 |vpiParent: - \_module: work@oh_par2ser (work@oh_par2ser), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_par2ser.v, line:8:1, endln:69:10 + \_module_inst: work@oh_par2ser (work@oh_par2ser), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_par2ser.v, line:8:1, endln:69:10 |vpiName:datasize |vpiFullName:work@oh_par2ser.datasize |vpiNet: \_logic_net: (work@oh_par2ser.lsbfirst), line:21:16, endln:21:24 |vpiParent: - \_module: work@oh_par2ser (work@oh_par2ser), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_par2ser.v, line:8:1, endln:69:10 + \_module_inst: work@oh_par2ser (work@oh_par2ser), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_par2ser.v, line:8:1, endln:69:10 |vpiName:lsbfirst |vpiFullName:work@oh_par2ser.lsbfirst |vpiNet: \_logic_net: (work@oh_par2ser.fill), line:22:16, endln:22:20 |vpiParent: - \_module: work@oh_par2ser (work@oh_par2ser), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_par2ser.v, line:8:1, endln:69:10 + \_module_inst: work@oh_par2ser (work@oh_par2ser), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_par2ser.v, line:8:1, endln:69:10 |vpiName:fill |vpiFullName:work@oh_par2ser.fill |vpiNet: \_logic_net: (work@oh_par2ser.wait_in), line:23:16, endln:23:23 |vpiParent: - \_module: work@oh_par2ser (work@oh_par2ser), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_par2ser.v, line:8:1, endln:69:10 + \_module_inst: work@oh_par2ser (work@oh_par2ser), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_par2ser.v, line:8:1, endln:69:10 |vpiName:wait_in |vpiFullName:work@oh_par2ser.wait_in |vpiNet: \_logic_net: (work@oh_par2ser.wait_out), line:24:17, endln:24:25 |vpiParent: - \_module: work@oh_par2ser (work@oh_par2ser), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_par2ser.v, line:8:1, endln:69:10 + \_module_inst: work@oh_par2ser (work@oh_par2ser), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_par2ser.v, line:8:1, endln:69:10 |vpiName:wait_out |vpiFullName:work@oh_par2ser.wait_out |vpiNet: \_logic_net: (work@oh_par2ser.shiftreg), line:28:20, endln:28:28 |vpiParent: - \_module: work@oh_par2ser (work@oh_par2ser), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_par2ser.v, line:8:1, endln:69:10 + \_module_inst: work@oh_par2ser (work@oh_par2ser), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_par2ser.v, line:8:1, endln:69:10 |vpiName:shiftreg |vpiFullName:work@oh_par2ser.shiftreg |vpiNetType:48 |vpiNet: \_logic_net: (work@oh_par2ser.count), line:29:20, endln:29:25 |vpiParent: - \_module: work@oh_par2ser (work@oh_par2ser), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_par2ser.v, line:8:1, endln:69:10 + \_module_inst: work@oh_par2ser (work@oh_par2ser), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_par2ser.v, line:8:1, endln:69:10 |vpiName:count |vpiFullName:work@oh_par2ser.count |vpiNetType:48 |vpiNet: \_logic_net: (work@oh_par2ser.start_transfer), line:30:13, endln:30:27 |vpiParent: - \_module: work@oh_par2ser (work@oh_par2ser), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_par2ser.v, line:8:1, endln:69:10 + \_module_inst: work@oh_par2ser (work@oh_par2ser), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_par2ser.v, line:8:1, endln:69:10 |vpiName:start_transfer |vpiFullName:work@oh_par2ser.start_transfer |vpiNetType:1 |vpiNet: \_logic_net: (work@oh_par2ser.busy), line:31:13, endln:31:17 |vpiParent: - \_module: work@oh_par2ser (work@oh_par2ser), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_par2ser.v, line:8:1, endln:69:10 + \_module_inst: work@oh_par2ser (work@oh_par2ser), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_par2ser.v, line:8:1, endln:69:10 |vpiName:busy |vpiFullName:work@oh_par2ser.busy |vpiNetType:1 |vpiPort: \_port: (clk), line:13:16, endln:13:19 |vpiParent: - \_module: work@oh_par2ser (work@oh_par2ser), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_par2ser.v, line:8:1, endln:69:10 + \_module_inst: work@oh_par2ser (work@oh_par2ser), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_par2ser.v, line:8:1, endln:69:10 |vpiName:clk |vpiDirection:1 |vpiLowConn: @@ -50442,7 +50442,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (nreset), line:14:16, endln:14:22 |vpiParent: - \_module: work@oh_par2ser (work@oh_par2ser), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_par2ser.v, line:8:1, endln:69:10 + \_module_inst: work@oh_par2ser (work@oh_par2ser), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_par2ser.v, line:8:1, endln:69:10 |vpiName:nreset |vpiDirection:1 |vpiLowConn: @@ -50454,7 +50454,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (din), line:15:21, endln:15:24 |vpiParent: - \_module: work@oh_par2ser (work@oh_par2ser), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_par2ser.v, line:8:1, endln:69:10 + \_module_inst: work@oh_par2ser (work@oh_par2ser), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_par2ser.v, line:8:1, endln:69:10 |vpiName:din |vpiDirection:1 |vpiLowConn: @@ -50494,7 +50494,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (dout), line:16:21, endln:16:25 |vpiParent: - \_module: work@oh_par2ser (work@oh_par2ser), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_par2ser.v, line:8:1, endln:69:10 + \_module_inst: work@oh_par2ser (work@oh_par2ser), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_par2ser.v, line:8:1, endln:69:10 |vpiName:dout |vpiDirection:2 |vpiLowConn: @@ -50534,7 +50534,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (access_out), line:17:17, endln:17:27 |vpiParent: - \_module: work@oh_par2ser (work@oh_par2ser), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_par2ser.v, line:8:1, endln:69:10 + \_module_inst: work@oh_par2ser (work@oh_par2ser), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_par2ser.v, line:8:1, endln:69:10 |vpiName:access_out |vpiDirection:2 |vpiLowConn: @@ -50546,7 +50546,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (load), line:18:16, endln:18:20 |vpiParent: - \_module: work@oh_par2ser (work@oh_par2ser), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_par2ser.v, line:8:1, endln:69:10 + \_module_inst: work@oh_par2ser (work@oh_par2ser), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_par2ser.v, line:8:1, endln:69:10 |vpiName:load |vpiDirection:1 |vpiLowConn: @@ -50558,7 +50558,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (shift), line:19:16, endln:19:21 |vpiParent: - \_module: work@oh_par2ser (work@oh_par2ser), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_par2ser.v, line:8:1, endln:69:10 + \_module_inst: work@oh_par2ser (work@oh_par2ser), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_par2ser.v, line:8:1, endln:69:10 |vpiName:shift |vpiDirection:1 |vpiLowConn: @@ -50570,7 +50570,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (datasize), line:20:21, endln:20:29 |vpiParent: - \_module: work@oh_par2ser (work@oh_par2ser), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_par2ser.v, line:8:1, endln:69:10 + \_module_inst: work@oh_par2ser (work@oh_par2ser), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_par2ser.v, line:8:1, endln:69:10 |vpiName:datasize |vpiDirection:1 |vpiLowConn: @@ -50600,7 +50600,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (lsbfirst), line:21:16, endln:21:24 |vpiParent: - \_module: work@oh_par2ser (work@oh_par2ser), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_par2ser.v, line:8:1, endln:69:10 + \_module_inst: work@oh_par2ser (work@oh_par2ser), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_par2ser.v, line:8:1, endln:69:10 |vpiName:lsbfirst |vpiDirection:1 |vpiLowConn: @@ -50612,7 +50612,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (fill), line:22:16, endln:22:20 |vpiParent: - \_module: work@oh_par2ser (work@oh_par2ser), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_par2ser.v, line:8:1, endln:69:10 + \_module_inst: work@oh_par2ser (work@oh_par2ser), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_par2ser.v, line:8:1, endln:69:10 |vpiName:fill |vpiDirection:1 |vpiLowConn: @@ -50624,7 +50624,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (wait_in), line:23:16, endln:23:23 |vpiParent: - \_module: work@oh_par2ser (work@oh_par2ser), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_par2ser.v, line:8:1, endln:69:10 + \_module_inst: work@oh_par2ser (work@oh_par2ser), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_par2ser.v, line:8:1, endln:69:10 |vpiName:wait_in |vpiDirection:1 |vpiLowConn: @@ -50636,7 +50636,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (wait_out), line:24:17, endln:24:25 |vpiParent: - \_module: work@oh_par2ser (work@oh_par2ser), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_par2ser.v, line:8:1, endln:69:10 + \_module_inst: work@oh_par2ser (work@oh_par2ser), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_par2ser.v, line:8:1, endln:69:10 |vpiName:wait_out |vpiDirection:2 |vpiLowConn: @@ -50648,7 +50648,7 @@ design: (work@oh_fifo_async) |vpiProcess: \_always: , line:37:4, endln:43:46 |vpiParent: - \_module: work@oh_par2ser (work@oh_par2ser), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_par2ser.v, line:8:1, endln:69:10 + \_module_inst: work@oh_par2ser (work@oh_par2ser), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_par2ser.v, line:8:1, endln:69:10 |vpiStmt: \_event_control: , line:37:11, endln:37:44 |vpiParent: @@ -50934,7 +50934,7 @@ design: (work@oh_fifo_async) |vpiProcess: \_always: , line:55:4, endln:63:62 |vpiParent: - \_module: work@oh_par2ser (work@oh_par2ser), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_par2ser.v, line:8:1, endln:69:10 + \_module_inst: work@oh_par2ser (work@oh_par2ser), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_par2ser.v, line:8:1, endln:69:10 |vpiStmt: \_event_control: , line:55:11, endln:55:44 |vpiParent: @@ -51355,7 +51355,7 @@ design: (work@oh_fifo_async) |vpiContAssign: \_cont_assign: , line:34:11, endln:34:52 |vpiParent: - \_module: work@oh_par2ser (work@oh_par2ser), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_par2ser.v, line:8:1, endln:69:10 + \_module_inst: work@oh_par2ser (work@oh_par2ser), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_par2ser.v, line:8:1, endln:69:10 |vpiRhs: \_operation: , line:34:28, endln:34:52 |vpiParent: @@ -51403,7 +51403,7 @@ design: (work@oh_fifo_async) |vpiContAssign: \_cont_assign: , line:46:11, endln:46:32 |vpiParent: - \_module: work@oh_par2ser (work@oh_par2ser), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_par2ser.v, line:8:1, endln:69:10 + \_module_inst: work@oh_par2ser (work@oh_par2ser), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_par2ser.v, line:8:1, endln:69:10 |vpiRhs: \_operation: , line:46:18, endln:46:32 |vpiParent: @@ -51450,7 +51450,7 @@ design: (work@oh_fifo_async) |vpiContAssign: \_cont_assign: , line:49:11, endln:49:28 |vpiParent: - \_module: work@oh_par2ser (work@oh_par2ser), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_par2ser.v, line:8:1, endln:69:10 + \_module_inst: work@oh_par2ser (work@oh_par2ser), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_par2ser.v, line:8:1, endln:69:10 |vpiRhs: \_ref_obj: (work@oh_par2ser.busy), line:49:24, endln:49:28 |vpiParent: @@ -51466,7 +51466,7 @@ design: (work@oh_fifo_async) |vpiContAssign: \_cont_assign: , line:52:11, endln:52:37 |vpiParent: - \_module: work@oh_par2ser (work@oh_par2ser), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_par2ser.v, line:8:1, endln:69:10 + \_module_inst: work@oh_par2ser (work@oh_par2ser), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_par2ser.v, line:8:1, endln:69:10 |vpiRhs: \_operation: , line:52:23, endln:52:37 |vpiParent: @@ -51493,7 +51493,7 @@ design: (work@oh_fifo_async) |vpiContAssign: \_cont_assign: , line:66:11, endln:67:36 |vpiParent: - \_module: work@oh_par2ser (work@oh_par2ser), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_par2ser.v, line:8:1, endln:69:10 + \_module_inst: work@oh_par2ser (work@oh_par2ser), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_par2ser.v, line:8:1, endln:69:10 |vpiRhs: \_operation: , line:66:26, endln:67:36 |vpiParent: @@ -51619,14 +51619,14 @@ design: (work@oh_fifo_async) |UINT:0 |vpiConstType:9 |uhdmallModules: -\_module: work@oh_parity (work@oh_parity), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_parity.v, line:8:1, endln:17:10 +\_module_inst: work@oh_parity (work@oh_parity), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_parity.v, line:8:1, endln:17:10 |vpiParent: \_design: (work@oh_fifo_async) |vpiFullName:work@oh_parity |vpiParameter: \_parameter: (work@oh_parity.N), line:8:31, endln:8:32 |vpiParent: - \_module: work@oh_parity (work@oh_parity), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_parity.v, line:8:1, endln:17:10 + \_module_inst: work@oh_parity (work@oh_parity), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_parity.v, line:8:1, endln:17:10 |UINT:2 |vpiTypespec: \_int_typespec: @@ -51635,7 +51635,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:8:31, endln:8:41 |vpiParent: - \_module: work@oh_parity (work@oh_parity), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_parity.v, line:8:1, endln:17:10 + \_module_inst: work@oh_parity (work@oh_parity), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_parity.v, line:8:1, endln:17:10 |vpiRhs: \_constant: , line:8:40, endln:8:41 |vpiDecompile:2 @@ -51651,19 +51651,19 @@ design: (work@oh_fifo_async) |vpiNet: \_logic_net: (work@oh_parity.in), line:11:19, endln:11:21 |vpiParent: - \_module: work@oh_parity (work@oh_parity), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_parity.v, line:8:1, endln:17:10 + \_module_inst: work@oh_parity (work@oh_parity), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_parity.v, line:8:1, endln:17:10 |vpiName:in |vpiFullName:work@oh_parity.in |vpiNet: \_logic_net: (work@oh_parity.out), line:12:16, endln:12:19 |vpiParent: - \_module: work@oh_parity (work@oh_parity), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_parity.v, line:8:1, endln:17:10 + \_module_inst: work@oh_parity (work@oh_parity), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_parity.v, line:8:1, endln:17:10 |vpiName:out |vpiFullName:work@oh_parity.out |vpiPort: \_port: (in), line:11:19, endln:11:21 |vpiParent: - \_module: work@oh_parity (work@oh_parity), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_parity.v, line:8:1, endln:17:10 + \_module_inst: work@oh_parity (work@oh_parity), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_parity.v, line:8:1, endln:17:10 |vpiName:in |vpiDirection:1 |vpiLowConn: @@ -51703,7 +51703,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (out), line:12:16, endln:12:19 |vpiParent: - \_module: work@oh_parity (work@oh_parity), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_parity.v, line:8:1, endln:17:10 + \_module_inst: work@oh_parity (work@oh_parity), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_parity.v, line:8:1, endln:17:10 |vpiName:out |vpiDirection:2 |vpiLowConn: @@ -51715,7 +51715,7 @@ design: (work@oh_fifo_async) |vpiContAssign: \_cont_assign: , line:15:11, endln:15:30 |vpiParent: - \_module: work@oh_parity (work@oh_parity), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_parity.v, line:8:1, endln:17:10 + \_module_inst: work@oh_parity (work@oh_parity), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_parity.v, line:8:1, endln:17:10 |vpiRhs: \_operation: , line:15:20, endln:15:30 |vpiParent: @@ -51760,14 +51760,14 @@ design: (work@oh_fifo_async) |vpiName:parity |vpiFullName:work@oh_parity.parity |uhdmallModules: -\_module: work@oh_pll (work@oh_pll), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_pll.v, line:8:1, endln:26:10 +\_module_inst: work@oh_pll (work@oh_pll), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_pll.v, line:8:1, endln:26:10 |vpiParent: \_design: (work@oh_fifo_async) |vpiFullName:work@oh_pll |vpiParameter: \_parameter: (work@oh_pll.N), line:8:27, endln:8:28 |vpiParent: - \_module: work@oh_pll (work@oh_pll), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_pll.v, line:8:1, endln:26:10 + \_module_inst: work@oh_pll (work@oh_pll), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_pll.v, line:8:1, endln:26:10 |UINT:8 |vpiTypespec: \_int_typespec: @@ -51776,7 +51776,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:8:27, endln:8:32 |vpiParent: - \_module: work@oh_pll (work@oh_pll), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_pll.v, line:8:1, endln:26:10 + \_module_inst: work@oh_pll (work@oh_pll), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_pll.v, line:8:1, endln:26:10 |vpiRhs: \_constant: , line:8:31, endln:8:32 |vpiDecompile:8 @@ -51792,61 +51792,61 @@ design: (work@oh_fifo_async) |vpiNet: \_logic_net: (work@oh_pll.clkin), line:9:23, endln:9:28 |vpiParent: - \_module: work@oh_pll (work@oh_pll), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_pll.v, line:8:1, endln:26:10 + \_module_inst: work@oh_pll (work@oh_pll), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_pll.v, line:8:1, endln:26:10 |vpiName:clkin |vpiFullName:work@oh_pll.clkin |vpiNet: \_logic_net: (work@oh_pll.nreset), line:10:19, endln:10:25 |vpiParent: - \_module: work@oh_pll (work@oh_pll), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_pll.v, line:8:1, endln:26:10 + \_module_inst: work@oh_pll (work@oh_pll), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_pll.v, line:8:1, endln:26:10 |vpiName:nreset |vpiFullName:work@oh_pll.nreset |vpiNet: \_logic_net: (work@oh_pll.clkfb), line:11:19, endln:11:24 |vpiParent: - \_module: work@oh_pll (work@oh_pll), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_pll.v, line:8:1, endln:26:10 + \_module_inst: work@oh_pll (work@oh_pll), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_pll.v, line:8:1, endln:26:10 |vpiName:clkfb |vpiFullName:work@oh_pll.clkfb |vpiNet: \_logic_net: (work@oh_pll.pll_en), line:12:19, endln:12:25 |vpiParent: - \_module: work@oh_pll (work@oh_pll), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_pll.v, line:8:1, endln:26:10 + \_module_inst: work@oh_pll (work@oh_pll), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_pll.v, line:8:1, endln:26:10 |vpiName:pll_en |vpiFullName:work@oh_pll.pll_en |vpiNet: \_logic_net: (work@oh_pll.clkdiv), line:13:23, endln:13:29 |vpiParent: - \_module: work@oh_pll (work@oh_pll), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_pll.v, line:8:1, endln:26:10 + \_module_inst: work@oh_pll (work@oh_pll), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_pll.v, line:8:1, endln:26:10 |vpiName:clkdiv |vpiFullName:work@oh_pll.clkdiv |vpiNet: \_logic_net: (work@oh_pll.clkphase), line:14:23, endln:14:31 |vpiParent: - \_module: work@oh_pll (work@oh_pll), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_pll.v, line:8:1, endln:26:10 + \_module_inst: work@oh_pll (work@oh_pll), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_pll.v, line:8:1, endln:26:10 |vpiName:clkphase |vpiFullName:work@oh_pll.clkphase |vpiNet: \_logic_net: (work@oh_pll.clkmult), line:15:23, endln:15:30 |vpiParent: - \_module: work@oh_pll (work@oh_pll), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_pll.v, line:8:1, endln:26:10 + \_module_inst: work@oh_pll (work@oh_pll), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_pll.v, line:8:1, endln:26:10 |vpiName:clkmult |vpiFullName:work@oh_pll.clkmult |vpiNet: \_logic_net: (work@oh_pll.clkout), line:16:23, endln:16:29 |vpiParent: - \_module: work@oh_pll (work@oh_pll), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_pll.v, line:8:1, endln:26:10 + \_module_inst: work@oh_pll (work@oh_pll), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_pll.v, line:8:1, endln:26:10 |vpiName:clkout |vpiFullName:work@oh_pll.clkout |vpiNet: \_logic_net: (work@oh_pll.locked), line:17:20, endln:17:26 |vpiParent: - \_module: work@oh_pll (work@oh_pll), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_pll.v, line:8:1, endln:26:10 + \_module_inst: work@oh_pll (work@oh_pll), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_pll.v, line:8:1, endln:26:10 |vpiName:locked |vpiFullName:work@oh_pll.locked |vpiPort: \_port: (clkin), line:9:23, endln:9:28 |vpiParent: - \_module: work@oh_pll (work@oh_pll), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_pll.v, line:8:1, endln:26:10 + \_module_inst: work@oh_pll (work@oh_pll), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_pll.v, line:8:1, endln:26:10 |vpiName:clkin |vpiDirection:1 |vpiLowConn: @@ -51858,7 +51858,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (nreset), line:10:19, endln:10:25 |vpiParent: - \_module: work@oh_pll (work@oh_pll), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_pll.v, line:8:1, endln:26:10 + \_module_inst: work@oh_pll (work@oh_pll), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_pll.v, line:8:1, endln:26:10 |vpiName:nreset |vpiDirection:1 |vpiLowConn: @@ -51870,7 +51870,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (clkfb), line:11:19, endln:11:24 |vpiParent: - \_module: work@oh_pll (work@oh_pll), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_pll.v, line:8:1, endln:26:10 + \_module_inst: work@oh_pll (work@oh_pll), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_pll.v, line:8:1, endln:26:10 |vpiName:clkfb |vpiDirection:1 |vpiLowConn: @@ -51882,7 +51882,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (pll_en), line:12:19, endln:12:25 |vpiParent: - \_module: work@oh_pll (work@oh_pll), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_pll.v, line:8:1, endln:26:10 + \_module_inst: work@oh_pll (work@oh_pll), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_pll.v, line:8:1, endln:26:10 |vpiName:pll_en |vpiDirection:1 |vpiLowConn: @@ -51894,7 +51894,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (clkdiv), line:13:23, endln:13:29 |vpiParent: - \_module: work@oh_pll (work@oh_pll), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_pll.v, line:8:1, endln:26:10 + \_module_inst: work@oh_pll (work@oh_pll), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_pll.v, line:8:1, endln:26:10 |vpiName:clkdiv |vpiDirection:1 |vpiLowConn: @@ -51947,7 +51947,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (clkphase), line:14:23, endln:14:31 |vpiParent: - \_module: work@oh_pll (work@oh_pll), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_pll.v, line:8:1, endln:26:10 + \_module_inst: work@oh_pll (work@oh_pll), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_pll.v, line:8:1, endln:26:10 |vpiName:clkphase |vpiDirection:1 |vpiLowConn: @@ -52000,7 +52000,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (clkmult), line:15:23, endln:15:30 |vpiParent: - \_module: work@oh_pll (work@oh_pll), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_pll.v, line:8:1, endln:26:10 + \_module_inst: work@oh_pll (work@oh_pll), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_pll.v, line:8:1, endln:26:10 |vpiName:clkmult |vpiDirection:1 |vpiLowConn: @@ -52030,7 +52030,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (clkout), line:16:23, endln:16:29 |vpiParent: - \_module: work@oh_pll (work@oh_pll), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_pll.v, line:8:1, endln:26:10 + \_module_inst: work@oh_pll (work@oh_pll), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_pll.v, line:8:1, endln:26:10 |vpiName:clkout |vpiDirection:2 |vpiLowConn: @@ -52070,7 +52070,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (locked), line:17:20, endln:17:26 |vpiParent: - \_module: work@oh_pll (work@oh_pll), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_pll.v, line:8:1, endln:26:10 + \_module_inst: work@oh_pll (work@oh_pll), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_pll.v, line:8:1, endln:26:10 |vpiName:locked |vpiDirection:2 |vpiLowConn: @@ -52080,14 +52080,14 @@ design: (work@oh_fifo_async) |vpiTypedef: \_logic_typespec: , line:17:20, endln:17:20 |uhdmallModules: -\_module: work@oh_pulse2pulse (work@oh_pulse2pulse), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_pulse2pulse.v, line:9:1, endln:53:10 +\_module_inst: work@oh_pulse2pulse (work@oh_pulse2pulse), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_pulse2pulse.v, line:9:1, endln:53:10 |vpiParent: \_design: (work@oh_fifo_async) |vpiFullName:work@oh_pulse2pulse |vpiParameter: \_parameter: (work@oh_pulse2pulse.SYN), line:10:15, endln:10:18 |vpiParent: - \_module: work@oh_pulse2pulse (work@oh_pulse2pulse), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_pulse2pulse.v, line:9:1, endln:53:10 + \_module_inst: work@oh_pulse2pulse (work@oh_pulse2pulse), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_pulse2pulse.v, line:9:1, endln:53:10 |STRING:TRUE |vpiTypespec: \_string_typespec: @@ -52096,7 +52096,7 @@ design: (work@oh_fifo_async) |vpiParameter: \_parameter: (work@oh_pulse2pulse.TYPE), line:11:15, endln:11:19 |vpiParent: - \_module: work@oh_pulse2pulse (work@oh_pulse2pulse), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_pulse2pulse.v, line:9:1, endln:53:10 + \_module_inst: work@oh_pulse2pulse (work@oh_pulse2pulse), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_pulse2pulse.v, line:9:1, endln:53:10 |STRING:DEFAULT |vpiTypespec: \_string_typespec: @@ -52105,7 +52105,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:10:15, endln:10:32 |vpiParent: - \_module: work@oh_pulse2pulse (work@oh_pulse2pulse), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_pulse2pulse.v, line:9:1, endln:53:10 + \_module_inst: work@oh_pulse2pulse (work@oh_pulse2pulse), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_pulse2pulse.v, line:9:1, endln:53:10 |vpiRhs: \_constant: , line:10:26, endln:10:32 |vpiDecompile:TRUE @@ -52119,7 +52119,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:11:15, endln:11:35 |vpiParent: - \_module: work@oh_pulse2pulse (work@oh_pulse2pulse), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_pulse2pulse.v, line:9:1, endln:53:10 + \_module_inst: work@oh_pulse2pulse (work@oh_pulse2pulse), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_pulse2pulse.v, line:9:1, endln:53:10 |vpiRhs: \_constant: , line:11:26, endln:11:35 |vpiDecompile:DEFAULT @@ -52135,64 +52135,64 @@ design: (work@oh_fifo_async) |vpiNet: \_logic_net: (work@oh_pulse2pulse.nrstin), line:14:11, endln:14:17 |vpiParent: - \_module: work@oh_pulse2pulse (work@oh_pulse2pulse), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_pulse2pulse.v, line:9:1, endln:53:10 + \_module_inst: work@oh_pulse2pulse (work@oh_pulse2pulse), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_pulse2pulse.v, line:9:1, endln:53:10 |vpiName:nrstin |vpiFullName:work@oh_pulse2pulse.nrstin |vpiNet: \_logic_net: (work@oh_pulse2pulse.din), line:15:11, endln:15:14 |vpiParent: - \_module: work@oh_pulse2pulse (work@oh_pulse2pulse), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_pulse2pulse.v, line:9:1, endln:53:10 + \_module_inst: work@oh_pulse2pulse (work@oh_pulse2pulse), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_pulse2pulse.v, line:9:1, endln:53:10 |vpiName:din |vpiFullName:work@oh_pulse2pulse.din |vpiNet: \_logic_net: (work@oh_pulse2pulse.clkin), line:16:11, endln:16:16 |vpiParent: - \_module: work@oh_pulse2pulse (work@oh_pulse2pulse), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_pulse2pulse.v, line:9:1, endln:53:10 + \_module_inst: work@oh_pulse2pulse (work@oh_pulse2pulse), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_pulse2pulse.v, line:9:1, endln:53:10 |vpiName:clkin |vpiFullName:work@oh_pulse2pulse.clkin |vpiNet: \_logic_net: (work@oh_pulse2pulse.nrstout), line:17:11, endln:17:18 |vpiParent: - \_module: work@oh_pulse2pulse (work@oh_pulse2pulse), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_pulse2pulse.v, line:9:1, endln:53:10 + \_module_inst: work@oh_pulse2pulse (work@oh_pulse2pulse), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_pulse2pulse.v, line:9:1, endln:53:10 |vpiName:nrstout |vpiFullName:work@oh_pulse2pulse.nrstout |vpiNet: \_logic_net: (work@oh_pulse2pulse.clkout), line:18:11, endln:18:17 |vpiParent: - \_module: work@oh_pulse2pulse (work@oh_pulse2pulse), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_pulse2pulse.v, line:9:1, endln:53:10 + \_module_inst: work@oh_pulse2pulse (work@oh_pulse2pulse), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_pulse2pulse.v, line:9:1, endln:53:10 |vpiName:clkout |vpiFullName:work@oh_pulse2pulse.clkout |vpiNet: \_logic_net: (work@oh_pulse2pulse.dout), line:19:11, endln:19:15 |vpiParent: - \_module: work@oh_pulse2pulse (work@oh_pulse2pulse), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_pulse2pulse.v, line:9:1, endln:53:10 + \_module_inst: work@oh_pulse2pulse (work@oh_pulse2pulse), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_pulse2pulse.v, line:9:1, endln:53:10 |vpiName:dout |vpiFullName:work@oh_pulse2pulse.dout |vpiNet: \_logic_net: (work@oh_pulse2pulse.toggle_reg), line:23:11, endln:23:21 |vpiParent: - \_module: work@oh_pulse2pulse (work@oh_pulse2pulse), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_pulse2pulse.v, line:9:1, endln:53:10 + \_module_inst: work@oh_pulse2pulse (work@oh_pulse2pulse), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_pulse2pulse.v, line:9:1, endln:53:10 |vpiName:toggle_reg |vpiFullName:work@oh_pulse2pulse.toggle_reg |vpiNetType:48 |vpiNet: \_logic_net: (work@oh_pulse2pulse.pulse_reg), line:24:11, endln:24:20 |vpiParent: - \_module: work@oh_pulse2pulse (work@oh_pulse2pulse), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_pulse2pulse.v, line:9:1, endln:53:10 + \_module_inst: work@oh_pulse2pulse (work@oh_pulse2pulse), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_pulse2pulse.v, line:9:1, endln:53:10 |vpiName:pulse_reg |vpiFullName:work@oh_pulse2pulse.pulse_reg |vpiNetType:48 |vpiNet: \_logic_net: (work@oh_pulse2pulse.toggle), line:25:11, endln:25:17 |vpiParent: - \_module: work@oh_pulse2pulse (work@oh_pulse2pulse), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_pulse2pulse.v, line:9:1, endln:53:10 + \_module_inst: work@oh_pulse2pulse (work@oh_pulse2pulse), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_pulse2pulse.v, line:9:1, endln:53:10 |vpiName:toggle |vpiFullName:work@oh_pulse2pulse.toggle |vpiNetType:1 |vpiPort: \_port: (nrstin), line:14:11, endln:14:17 |vpiParent: - \_module: work@oh_pulse2pulse (work@oh_pulse2pulse), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_pulse2pulse.v, line:9:1, endln:53:10 + \_module_inst: work@oh_pulse2pulse (work@oh_pulse2pulse), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_pulse2pulse.v, line:9:1, endln:53:10 |vpiName:nrstin |vpiDirection:1 |vpiLowConn: @@ -52204,7 +52204,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (din), line:15:11, endln:15:14 |vpiParent: - \_module: work@oh_pulse2pulse (work@oh_pulse2pulse), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_pulse2pulse.v, line:9:1, endln:53:10 + \_module_inst: work@oh_pulse2pulse (work@oh_pulse2pulse), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_pulse2pulse.v, line:9:1, endln:53:10 |vpiName:din |vpiDirection:1 |vpiLowConn: @@ -52216,7 +52216,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (clkin), line:16:11, endln:16:16 |vpiParent: - \_module: work@oh_pulse2pulse (work@oh_pulse2pulse), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_pulse2pulse.v, line:9:1, endln:53:10 + \_module_inst: work@oh_pulse2pulse (work@oh_pulse2pulse), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_pulse2pulse.v, line:9:1, endln:53:10 |vpiName:clkin |vpiDirection:1 |vpiLowConn: @@ -52228,7 +52228,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (nrstout), line:17:11, endln:17:18 |vpiParent: - \_module: work@oh_pulse2pulse (work@oh_pulse2pulse), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_pulse2pulse.v, line:9:1, endln:53:10 + \_module_inst: work@oh_pulse2pulse (work@oh_pulse2pulse), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_pulse2pulse.v, line:9:1, endln:53:10 |vpiName:nrstout |vpiDirection:1 |vpiLowConn: @@ -52240,7 +52240,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (clkout), line:18:11, endln:18:17 |vpiParent: - \_module: work@oh_pulse2pulse (work@oh_pulse2pulse), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_pulse2pulse.v, line:9:1, endln:53:10 + \_module_inst: work@oh_pulse2pulse (work@oh_pulse2pulse), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_pulse2pulse.v, line:9:1, endln:53:10 |vpiName:clkout |vpiDirection:1 |vpiLowConn: @@ -52252,7 +52252,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (dout), line:19:11, endln:19:15 |vpiParent: - \_module: work@oh_pulse2pulse (work@oh_pulse2pulse), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_pulse2pulse.v, line:9:1, endln:53:10 + \_module_inst: work@oh_pulse2pulse (work@oh_pulse2pulse), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_pulse2pulse.v, line:9:1, endln:53:10 |vpiName:dout |vpiDirection:2 |vpiLowConn: @@ -52264,7 +52264,7 @@ design: (work@oh_fifo_async) |vpiProcess: \_always: , line:30:4, endln:34:29 |vpiParent: - \_module: work@oh_pulse2pulse (work@oh_pulse2pulse), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_pulse2pulse.v, line:9:1, endln:53:10 + \_module_inst: work@oh_pulse2pulse (work@oh_pulse2pulse), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_pulse2pulse.v, line:9:1, endln:53:10 |vpiStmt: \_event_control: , line:30:11, endln:30:28 |vpiParent: @@ -52335,7 +52335,7 @@ design: (work@oh_fifo_async) |vpiProcess: \_always: , line:45:4, endln:49:33 |vpiParent: - \_module: work@oh_pulse2pulse (work@oh_pulse2pulse), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_pulse2pulse.v, line:9:1, endln:53:10 + \_module_inst: work@oh_pulse2pulse (work@oh_pulse2pulse), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_pulse2pulse.v, line:9:1, endln:53:10 |vpiStmt: \_event_control: , line:45:11, endln:45:29 |vpiParent: @@ -52406,7 +52406,7 @@ design: (work@oh_fifo_async) |vpiContAssign: \_cont_assign: , line:28:11, endln:28:50 |vpiParent: - \_module: work@oh_pulse2pulse (work@oh_pulse2pulse), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_pulse2pulse.v, line:9:1, endln:53:10 + \_module_inst: work@oh_pulse2pulse (work@oh_pulse2pulse), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_pulse2pulse.v, line:9:1, endln:53:10 |vpiRhs: \_operation: , line:28:20, endln:28:50 |vpiParent: @@ -52444,7 +52444,7 @@ design: (work@oh_fifo_async) |vpiContAssign: \_cont_assign: , line:51:11, endln:51:41 |vpiParent: - \_module: work@oh_pulse2pulse (work@oh_pulse2pulse), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_pulse2pulse.v, line:9:1, endln:53:10 + \_module_inst: work@oh_pulse2pulse (work@oh_pulse2pulse), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_pulse2pulse.v, line:9:1, endln:53:10 |vpiRhs: \_operation: , line:51:18, endln:51:41 |vpiParent: @@ -52469,14 +52469,14 @@ design: (work@oh_fifo_async) |vpiName:dout |vpiFullName:work@oh_pulse2pulse.dout |uhdmallModules: -\_module: work@oh_pwr_buf (work@oh_pwr_buf), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_pwr_buf.v, line:8:1, endln:24:10 +\_module_inst: work@oh_pwr_buf (work@oh_pwr_buf), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_pwr_buf.v, line:8:1, endln:24:10 |vpiParent: \_design: (work@oh_fifo_async) |vpiFullName:work@oh_pwr_buf |vpiParameter: \_parameter: (work@oh_pwr_buf.N), line:8:32, endln:8:33 |vpiParent: - \_module: work@oh_pwr_buf (work@oh_pwr_buf), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_pwr_buf.v, line:8:1, endln:24:10 + \_module_inst: work@oh_pwr_buf (work@oh_pwr_buf), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_pwr_buf.v, line:8:1, endln:24:10 |UINT:1 |vpiTypespec: \_int_typespec: @@ -52485,7 +52485,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:8:32, endln:8:37 |vpiParent: - \_module: work@oh_pwr_buf (work@oh_pwr_buf), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_pwr_buf.v, line:8:1, endln:24:10 + \_module_inst: work@oh_pwr_buf (work@oh_pwr_buf), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_pwr_buf.v, line:8:1, endln:24:10 |vpiRhs: \_constant: , line:8:36, endln:8:37 |vpiDecompile:1 @@ -52501,31 +52501,31 @@ design: (work@oh_fifo_async) |vpiNet: \_logic_net: (work@oh_pwr_buf.vdd), line:10:11, endln:10:14 |vpiParent: - \_module: work@oh_pwr_buf (work@oh_pwr_buf), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_pwr_buf.v, line:8:1, endln:24:10 + \_module_inst: work@oh_pwr_buf (work@oh_pwr_buf), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_pwr_buf.v, line:8:1, endln:24:10 |vpiName:vdd |vpiFullName:work@oh_pwr_buf.vdd |vpiNet: \_logic_net: (work@oh_pwr_buf.vss), line:11:11, endln:11:14 |vpiParent: - \_module: work@oh_pwr_buf (work@oh_pwr_buf), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_pwr_buf.v, line:8:1, endln:24:10 + \_module_inst: work@oh_pwr_buf (work@oh_pwr_buf), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_pwr_buf.v, line:8:1, endln:24:10 |vpiName:vss |vpiFullName:work@oh_pwr_buf.vss |vpiNet: \_logic_net: (work@oh_pwr_buf.in), line:12:18, endln:12:20 |vpiParent: - \_module: work@oh_pwr_buf (work@oh_pwr_buf), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_pwr_buf.v, line:8:1, endln:24:10 + \_module_inst: work@oh_pwr_buf (work@oh_pwr_buf), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_pwr_buf.v, line:8:1, endln:24:10 |vpiName:in |vpiFullName:work@oh_pwr_buf.in |vpiNet: \_logic_net: (work@oh_pwr_buf.out), line:13:18, endln:13:21 |vpiParent: - \_module: work@oh_pwr_buf (work@oh_pwr_buf), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_pwr_buf.v, line:8:1, endln:24:10 + \_module_inst: work@oh_pwr_buf (work@oh_pwr_buf), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_pwr_buf.v, line:8:1, endln:24:10 |vpiName:out |vpiFullName:work@oh_pwr_buf.out |vpiPort: \_port: (vdd), line:10:11, endln:10:14 |vpiParent: - \_module: work@oh_pwr_buf (work@oh_pwr_buf), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_pwr_buf.v, line:8:1, endln:24:10 + \_module_inst: work@oh_pwr_buf (work@oh_pwr_buf), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_pwr_buf.v, line:8:1, endln:24:10 |vpiName:vdd |vpiDirection:1 |vpiLowConn: @@ -52537,7 +52537,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (vss), line:11:11, endln:11:14 |vpiParent: - \_module: work@oh_pwr_buf (work@oh_pwr_buf), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_pwr_buf.v, line:8:1, endln:24:10 + \_module_inst: work@oh_pwr_buf (work@oh_pwr_buf), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_pwr_buf.v, line:8:1, endln:24:10 |vpiName:vss |vpiDirection:1 |vpiLowConn: @@ -52549,7 +52549,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (in), line:12:18, endln:12:20 |vpiParent: - \_module: work@oh_pwr_buf (work@oh_pwr_buf), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_pwr_buf.v, line:8:1, endln:24:10 + \_module_inst: work@oh_pwr_buf (work@oh_pwr_buf), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_pwr_buf.v, line:8:1, endln:24:10 |vpiName:in |vpiDirection:1 |vpiLowConn: @@ -52589,7 +52589,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (out), line:13:18, endln:13:21 |vpiParent: - \_module: work@oh_pwr_buf (work@oh_pwr_buf), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_pwr_buf.v, line:8:1, endln:24:10 + \_module_inst: work@oh_pwr_buf (work@oh_pwr_buf), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_pwr_buf.v, line:8:1, endln:24:10 |vpiName:out |vpiDirection:2 |vpiLowConn: @@ -52629,7 +52629,7 @@ design: (work@oh_fifo_async) |vpiContAssign: \_cont_assign: , line:20:11, endln:20:33 |vpiParent: - \_module: work@oh_pwr_buf (work@oh_pwr_buf), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_pwr_buf.v, line:8:1, endln:24:10 + \_module_inst: work@oh_pwr_buf (work@oh_pwr_buf), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_pwr_buf.v, line:8:1, endln:24:10 |vpiRhs: \_part_select: , line:20:24, endln:20:33 |vpiParent: @@ -52695,14 +52695,14 @@ design: (work@oh_fifo_async) |UINT:0 |vpiConstType:9 |uhdmallModules: -\_module: work@oh_reg1 (work@oh_reg1), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_reg1.v, line:8:1, endln:45:10 +\_module_inst: work@oh_reg1 (work@oh_reg1), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_reg1.v, line:8:1, endln:45:10 |vpiParent: \_design: (work@oh_fifo_async) |vpiFullName:work@oh_reg1 |vpiParameter: \_parameter: (work@oh_reg1.N), line:9:15, endln:9:16 |vpiParent: - \_module: work@oh_reg1 (work@oh_reg1), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_reg1.v, line:8:1, endln:45:10 + \_module_inst: work@oh_reg1 (work@oh_reg1), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_reg1.v, line:8:1, endln:45:10 |UINT:1 |vpiTypespec: \_int_typespec: @@ -52711,7 +52711,7 @@ design: (work@oh_fifo_async) |vpiParameter: \_parameter: (work@oh_reg1.SYN), line:10:15, endln:10:18 |vpiParent: - \_module: work@oh_reg1 (work@oh_reg1), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_reg1.v, line:8:1, endln:45:10 + \_module_inst: work@oh_reg1 (work@oh_reg1), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_reg1.v, line:8:1, endln:45:10 |STRING:TRUE |vpiTypespec: \_string_typespec: @@ -52720,7 +52720,7 @@ design: (work@oh_fifo_async) |vpiParameter: \_parameter: (work@oh_reg1.TYPE), line:11:15, endln:11:19 |vpiParent: - \_module: work@oh_reg1 (work@oh_reg1), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_reg1.v, line:8:1, endln:45:10 + \_module_inst: work@oh_reg1 (work@oh_reg1), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_reg1.v, line:8:1, endln:45:10 |STRING:DEFAULT |vpiTypespec: \_string_typespec: @@ -52729,7 +52729,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:9:15, endln:9:23 |vpiParent: - \_module: work@oh_reg1 (work@oh_reg1), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_reg1.v, line:8:1, endln:45:10 + \_module_inst: work@oh_reg1 (work@oh_reg1), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_reg1.v, line:8:1, endln:45:10 |vpiRhs: \_constant: , line:9:22, endln:9:23 |vpiDecompile:1 @@ -52743,7 +52743,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:10:15, endln:10:28 |vpiParent: - \_module: work@oh_reg1 (work@oh_reg1), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_reg1.v, line:8:1, endln:45:10 + \_module_inst: work@oh_reg1 (work@oh_reg1), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_reg1.v, line:8:1, endln:45:10 |vpiRhs: \_constant: , line:10:22, endln:10:28 |vpiDecompile:TRUE @@ -52757,7 +52757,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:11:15, endln:11:31 |vpiParent: - \_module: work@oh_reg1 (work@oh_reg1), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_reg1.v, line:8:1, endln:45:10 + \_module_inst: work@oh_reg1 (work@oh_reg1), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_reg1.v, line:8:1, endln:45:10 |vpiRhs: \_constant: , line:11:22, endln:11:31 |vpiDecompile:DEFAULT @@ -52773,37 +52773,37 @@ design: (work@oh_fifo_async) |vpiNet: \_logic_net: (work@oh_reg1.nreset), line:13:21, endln:13:27 |vpiParent: - \_module: work@oh_reg1 (work@oh_reg1), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_reg1.v, line:8:1, endln:45:10 + \_module_inst: work@oh_reg1 (work@oh_reg1), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_reg1.v, line:8:1, endln:45:10 |vpiName:nreset |vpiFullName:work@oh_reg1.nreset |vpiNet: \_logic_net: (work@oh_reg1.clk), line:14:17, endln:14:20 |vpiParent: - \_module: work@oh_reg1 (work@oh_reg1), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_reg1.v, line:8:1, endln:45:10 + \_module_inst: work@oh_reg1 (work@oh_reg1), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_reg1.v, line:8:1, endln:45:10 |vpiName:clk |vpiFullName:work@oh_reg1.clk |vpiNet: \_logic_net: (work@oh_reg1.en), line:15:17, endln:15:19 |vpiParent: - \_module: work@oh_reg1 (work@oh_reg1), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_reg1.v, line:8:1, endln:45:10 + \_module_inst: work@oh_reg1 (work@oh_reg1), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_reg1.v, line:8:1, endln:45:10 |vpiName:en |vpiFullName:work@oh_reg1.en |vpiNet: \_logic_net: (work@oh_reg1.in), line:16:21, endln:16:23 |vpiParent: - \_module: work@oh_reg1 (work@oh_reg1), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_reg1.v, line:8:1, endln:45:10 + \_module_inst: work@oh_reg1 (work@oh_reg1), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_reg1.v, line:8:1, endln:45:10 |vpiName:in |vpiFullName:work@oh_reg1.in |vpiNet: \_logic_net: (work@oh_reg1.out), line:17:21, endln:17:24 |vpiParent: - \_module: work@oh_reg1 (work@oh_reg1), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_reg1.v, line:8:1, endln:45:10 + \_module_inst: work@oh_reg1 (work@oh_reg1), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_reg1.v, line:8:1, endln:45:10 |vpiName:out |vpiFullName:work@oh_reg1.out |vpiPort: \_port: (nreset), line:13:21, endln:13:27 |vpiParent: - \_module: work@oh_reg1 (work@oh_reg1), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_reg1.v, line:8:1, endln:45:10 + \_module_inst: work@oh_reg1 (work@oh_reg1), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_reg1.v, line:8:1, endln:45:10 |vpiName:nreset |vpiDirection:1 |vpiLowConn: @@ -52815,7 +52815,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (clk), line:14:17, endln:14:20 |vpiParent: - \_module: work@oh_reg1 (work@oh_reg1), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_reg1.v, line:8:1, endln:45:10 + \_module_inst: work@oh_reg1 (work@oh_reg1), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_reg1.v, line:8:1, endln:45:10 |vpiName:clk |vpiDirection:1 |vpiLowConn: @@ -52827,7 +52827,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (en), line:15:17, endln:15:19 |vpiParent: - \_module: work@oh_reg1 (work@oh_reg1), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_reg1.v, line:8:1, endln:45:10 + \_module_inst: work@oh_reg1 (work@oh_reg1), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_reg1.v, line:8:1, endln:45:10 |vpiName:en |vpiDirection:1 |vpiLowConn: @@ -52839,7 +52839,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (in), line:16:21, endln:16:23 |vpiParent: - \_module: work@oh_reg1 (work@oh_reg1), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_reg1.v, line:8:1, endln:45:10 + \_module_inst: work@oh_reg1 (work@oh_reg1), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_reg1.v, line:8:1, endln:45:10 |vpiName:in |vpiDirection:1 |vpiLowConn: @@ -52879,7 +52879,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (out), line:17:21, endln:17:24 |vpiParent: - \_module: work@oh_reg1 (work@oh_reg1), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_reg1.v, line:8:1, endln:45:10 + \_module_inst: work@oh_reg1 (work@oh_reg1), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_reg1.v, line:8:1, endln:45:10 |vpiName:out |vpiDirection:2 |vpiLowConn: @@ -52917,14 +52917,14 @@ design: (work@oh_fifo_async) |UINT:0 |vpiConstType:9 |uhdmallModules: -\_module: work@oh_regfile (work@oh_regfile), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_regfile.v, line:8:1, endln:76:10 +\_module_inst: work@oh_regfile (work@oh_regfile), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_regfile.v, line:8:1, endln:76:10 |vpiParent: \_design: (work@oh_fifo_async) |vpiFullName:work@oh_regfile |vpiParameter: \_parameter: (work@oh_regfile.REGS), line:9:16, endln:9:20 |vpiParent: - \_module: work@oh_regfile (work@oh_regfile), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_regfile.v, line:8:1, endln:76:10 + \_module_inst: work@oh_regfile (work@oh_regfile), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_regfile.v, line:8:1, endln:76:10 |UINT:8 |vpiTypespec: \_int_typespec: @@ -52933,7 +52933,7 @@ design: (work@oh_fifo_async) |vpiParameter: \_parameter: (work@oh_regfile.RW), line:10:16, endln:10:18 |vpiParent: - \_module: work@oh_regfile (work@oh_regfile), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_regfile.v, line:8:1, endln:76:10 + \_module_inst: work@oh_regfile (work@oh_regfile), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_regfile.v, line:8:1, endln:76:10 |UINT:16 |vpiTypespec: \_int_typespec: @@ -52942,7 +52942,7 @@ design: (work@oh_fifo_async) |vpiParameter: \_parameter: (work@oh_regfile.RP), line:11:16, endln:11:18 |vpiParent: - \_module: work@oh_regfile (work@oh_regfile), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_regfile.v, line:8:1, endln:76:10 + \_module_inst: work@oh_regfile (work@oh_regfile), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_regfile.v, line:8:1, endln:76:10 |UINT:5 |vpiTypespec: \_int_typespec: @@ -52951,7 +52951,7 @@ design: (work@oh_fifo_async) |vpiParameter: \_parameter: (work@oh_regfile.WP), line:12:16, endln:12:18 |vpiParent: - \_module: work@oh_regfile (work@oh_regfile), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_regfile.v, line:8:1, endln:76:10 + \_module_inst: work@oh_regfile (work@oh_regfile), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_regfile.v, line:8:1, endln:76:10 |UINT:3 |vpiTypespec: \_int_typespec: @@ -52960,13 +52960,13 @@ design: (work@oh_fifo_async) |vpiParameter: \_parameter: (work@oh_regfile.RAW), line:13:16, endln:13:19 |vpiParent: - \_module: work@oh_regfile (work@oh_regfile), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_regfile.v, line:8:1, endln:76:10 + \_module_inst: work@oh_regfile (work@oh_regfile), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_regfile.v, line:8:1, endln:76:10 |vpiName:RAW |vpiFullName:work@oh_regfile.RAW |vpiParamAssign: \_param_assign: , line:9:16, endln:9:25 |vpiParent: - \_module: work@oh_regfile (work@oh_regfile), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_regfile.v, line:8:1, endln:76:10 + \_module_inst: work@oh_regfile (work@oh_regfile), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_regfile.v, line:8:1, endln:76:10 |vpiRhs: \_constant: , line:9:24, endln:9:25 |vpiDecompile:8 @@ -52980,7 +52980,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:10:16, endln:10:26 |vpiParent: - \_module: work@oh_regfile (work@oh_regfile), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_regfile.v, line:8:1, endln:76:10 + \_module_inst: work@oh_regfile (work@oh_regfile), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_regfile.v, line:8:1, endln:76:10 |vpiRhs: \_constant: , line:10:24, endln:10:26 |vpiDecompile:16 @@ -52994,7 +52994,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:11:16, endln:11:25 |vpiParent: - \_module: work@oh_regfile (work@oh_regfile), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_regfile.v, line:8:1, endln:76:10 + \_module_inst: work@oh_regfile (work@oh_regfile), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_regfile.v, line:8:1, endln:76:10 |vpiRhs: \_constant: , line:11:24, endln:11:25 |vpiDecompile:5 @@ -53008,7 +53008,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:12:16, endln:12:25 |vpiParent: - \_module: work@oh_regfile (work@oh_regfile), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_regfile.v, line:8:1, endln:76:10 + \_module_inst: work@oh_regfile (work@oh_regfile), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_regfile.v, line:8:1, endln:76:10 |vpiRhs: \_constant: , line:12:24, endln:12:25 |vpiDecompile:3 @@ -53022,7 +53022,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:13:16, endln:13:36 |vpiParent: - \_module: work@oh_regfile (work@oh_regfile), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_regfile.v, line:8:1, endln:76:10 + \_module_inst: work@oh_regfile (work@oh_regfile), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_regfile.v, line:8:1, endln:76:10 |vpiRhs: \_sys_func_call: ($clog2), line:13:24, endln:13:36 |vpiArgument: @@ -53038,70 +53038,70 @@ design: (work@oh_fifo_async) |vpiNet: \_logic_net: (work@oh_regfile.clk), line:16:19, endln:16:22 |vpiParent: - \_module: work@oh_regfile (work@oh_regfile), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_regfile.v, line:8:1, endln:76:10 + \_module_inst: work@oh_regfile (work@oh_regfile), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_regfile.v, line:8:1, endln:76:10 |vpiName:clk |vpiFullName:work@oh_regfile.clk |vpiNet: \_logic_net: (work@oh_regfile.wr_valid), line:18:24, endln:18:32 |vpiParent: - \_module: work@oh_regfile (work@oh_regfile), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_regfile.v, line:8:1, endln:76:10 + \_module_inst: work@oh_regfile (work@oh_regfile), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_regfile.v, line:8:1, endln:76:10 |vpiName:wr_valid |vpiFullName:work@oh_regfile.wr_valid |vpiNet: \_logic_net: (work@oh_regfile.wr_addr), line:19:24, endln:19:31 |vpiParent: - \_module: work@oh_regfile (work@oh_regfile), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_regfile.v, line:8:1, endln:76:10 + \_module_inst: work@oh_regfile (work@oh_regfile), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_regfile.v, line:8:1, endln:76:10 |vpiName:wr_addr |vpiFullName:work@oh_regfile.wr_addr |vpiNet: \_logic_net: (work@oh_regfile.wr_data), line:20:24, endln:20:31 |vpiParent: - \_module: work@oh_regfile (work@oh_regfile), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_regfile.v, line:8:1, endln:76:10 + \_module_inst: work@oh_regfile (work@oh_regfile), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_regfile.v, line:8:1, endln:76:10 |vpiName:wr_data |vpiFullName:work@oh_regfile.wr_data |vpiNet: \_logic_net: (work@oh_regfile.rd_valid), line:22:24, endln:22:32 |vpiParent: - \_module: work@oh_regfile (work@oh_regfile), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_regfile.v, line:8:1, endln:76:10 + \_module_inst: work@oh_regfile (work@oh_regfile), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_regfile.v, line:8:1, endln:76:10 |vpiName:rd_valid |vpiFullName:work@oh_regfile.rd_valid |vpiNet: \_logic_net: (work@oh_regfile.rd_addr), line:23:24, endln:23:31 |vpiParent: - \_module: work@oh_regfile (work@oh_regfile), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_regfile.v, line:8:1, endln:76:10 + \_module_inst: work@oh_regfile (work@oh_regfile), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_regfile.v, line:8:1, endln:76:10 |vpiName:rd_addr |vpiFullName:work@oh_regfile.rd_addr |vpiNet: \_logic_net: (work@oh_regfile.rd_data), line:24:24, endln:24:31 |vpiParent: - \_module: work@oh_regfile (work@oh_regfile), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_regfile.v, line:8:1, endln:76:10 + \_module_inst: work@oh_regfile (work@oh_regfile), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_regfile.v, line:8:1, endln:76:10 |vpiName:rd_data |vpiFullName:work@oh_regfile.rd_data |vpiNet: \_logic_net: (work@oh_regfile.mem), line:28:24, endln:28:27 |vpiParent: - \_module: work@oh_regfile (work@oh_regfile), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_regfile.v, line:8:1, endln:76:10 + \_module_inst: work@oh_regfile (work@oh_regfile), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_regfile.v, line:8:1, endln:76:10 |vpiName:mem |vpiFullName:work@oh_regfile.mem |vpiNetType:48 |vpiNet: \_logic_net: (work@oh_regfile.write_en), line:29:24, endln:29:32 |vpiParent: - \_module: work@oh_regfile (work@oh_regfile), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_regfile.v, line:8:1, endln:76:10 + \_module_inst: work@oh_regfile (work@oh_regfile), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_regfile.v, line:8:1, endln:76:10 |vpiName:write_en |vpiFullName:work@oh_regfile.write_en |vpiNetType:1 |vpiNet: \_logic_net: (work@oh_regfile.datamux), line:30:24, endln:30:31 |vpiParent: - \_module: work@oh_regfile (work@oh_regfile), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_regfile.v, line:8:1, endln:76:10 + \_module_inst: work@oh_regfile (work@oh_regfile), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_regfile.v, line:8:1, endln:76:10 |vpiName:datamux |vpiFullName:work@oh_regfile.datamux |vpiNetType:1 |vpiPort: \_port: (clk), line:16:19, endln:16:22 |vpiParent: - \_module: work@oh_regfile (work@oh_regfile), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_regfile.v, line:8:1, endln:76:10 + \_module_inst: work@oh_regfile (work@oh_regfile), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_regfile.v, line:8:1, endln:76:10 |vpiName:clk |vpiDirection:1 |vpiLowConn: @@ -53113,7 +53113,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (wr_valid), line:18:24, endln:18:32 |vpiParent: - \_module: work@oh_regfile (work@oh_regfile), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_regfile.v, line:8:1, endln:76:10 + \_module_inst: work@oh_regfile (work@oh_regfile), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_regfile.v, line:8:1, endln:76:10 |vpiName:wr_valid |vpiDirection:1 |vpiLowConn: @@ -53153,7 +53153,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (wr_addr), line:19:24, endln:19:31 |vpiParent: - \_module: work@oh_regfile (work@oh_regfile), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_regfile.v, line:8:1, endln:76:10 + \_module_inst: work@oh_regfile (work@oh_regfile), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_regfile.v, line:8:1, endln:76:10 |vpiName:wr_addr |vpiDirection:1 |vpiLowConn: @@ -53203,7 +53203,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (wr_data), line:20:24, endln:20:31 |vpiParent: - \_module: work@oh_regfile (work@oh_regfile), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_regfile.v, line:8:1, endln:76:10 + \_module_inst: work@oh_regfile (work@oh_regfile), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_regfile.v, line:8:1, endln:76:10 |vpiName:wr_data |vpiDirection:1 |vpiLowConn: @@ -53253,7 +53253,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (rd_valid), line:22:24, endln:22:32 |vpiParent: - \_module: work@oh_regfile (work@oh_regfile), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_regfile.v, line:8:1, endln:76:10 + \_module_inst: work@oh_regfile (work@oh_regfile), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_regfile.v, line:8:1, endln:76:10 |vpiName:rd_valid |vpiDirection:1 |vpiLowConn: @@ -53293,7 +53293,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (rd_addr), line:23:24, endln:23:31 |vpiParent: - \_module: work@oh_regfile (work@oh_regfile), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_regfile.v, line:8:1, endln:76:10 + \_module_inst: work@oh_regfile (work@oh_regfile), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_regfile.v, line:8:1, endln:76:10 |vpiName:rd_addr |vpiDirection:1 |vpiLowConn: @@ -53343,7 +53343,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (rd_data), line:24:24, endln:24:31 |vpiParent: - \_module: work@oh_regfile (work@oh_regfile), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_regfile.v, line:8:1, endln:76:10 + \_module_inst: work@oh_regfile (work@oh_regfile), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_regfile.v, line:8:1, endln:76:10 |vpiName:rd_data |vpiDirection:2 |vpiLowConn: @@ -53391,14 +53391,14 @@ design: (work@oh_fifo_async) |UINT:0 |vpiConstType:9 |uhdmallModules: -\_module: work@oh_rise2pulse (work@oh_rise2pulse), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_rise2pulse.v, line:8:1, endln:26:10 +\_module_inst: work@oh_rise2pulse (work@oh_rise2pulse), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_rise2pulse.v, line:8:1, endln:26:10 |vpiParent: \_design: (work@oh_fifo_async) |vpiFullName:work@oh_rise2pulse |vpiParameter: \_parameter: (work@oh_rise2pulse.N), line:8:34, endln:8:35 |vpiParent: - \_module: work@oh_rise2pulse (work@oh_rise2pulse), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_rise2pulse.v, line:8:1, endln:26:10 + \_module_inst: work@oh_rise2pulse (work@oh_rise2pulse), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_rise2pulse.v, line:8:1, endln:26:10 |UINT:1 |vpiTypespec: \_int_typespec: @@ -53407,7 +53407,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:8:34, endln:8:39 |vpiParent: - \_module: work@oh_rise2pulse (work@oh_rise2pulse), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_rise2pulse.v, line:8:1, endln:26:10 + \_module_inst: work@oh_rise2pulse (work@oh_rise2pulse), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_rise2pulse.v, line:8:1, endln:26:10 |vpiRhs: \_constant: , line:8:38, endln:8:39 |vpiDecompile:1 @@ -53423,38 +53423,38 @@ design: (work@oh_fifo_async) |vpiNet: \_logic_net: (work@oh_rise2pulse.clk), line:10:23, endln:10:26 |vpiParent: - \_module: work@oh_rise2pulse (work@oh_rise2pulse), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_rise2pulse.v, line:8:1, endln:26:10 + \_module_inst: work@oh_rise2pulse (work@oh_rise2pulse), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_rise2pulse.v, line:8:1, endln:26:10 |vpiName:clk |vpiFullName:work@oh_rise2pulse.clk |vpiNet: \_logic_net: (work@oh_rise2pulse.nreset), line:11:20, endln:11:26 |vpiParent: - \_module: work@oh_rise2pulse (work@oh_rise2pulse), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_rise2pulse.v, line:8:1, endln:26:10 + \_module_inst: work@oh_rise2pulse (work@oh_rise2pulse), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_rise2pulse.v, line:8:1, endln:26:10 |vpiName:nreset |vpiFullName:work@oh_rise2pulse.nreset |vpiNet: \_logic_net: (work@oh_rise2pulse.in), line:12:22, endln:12:24 |vpiParent: - \_module: work@oh_rise2pulse (work@oh_rise2pulse), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_rise2pulse.v, line:8:1, endln:26:10 + \_module_inst: work@oh_rise2pulse (work@oh_rise2pulse), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_rise2pulse.v, line:8:1, endln:26:10 |vpiName:in |vpiFullName:work@oh_rise2pulse.in |vpiNet: \_logic_net: (work@oh_rise2pulse.out), line:13:22, endln:13:25 |vpiParent: - \_module: work@oh_rise2pulse (work@oh_rise2pulse), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_rise2pulse.v, line:8:1, endln:26:10 + \_module_inst: work@oh_rise2pulse (work@oh_rise2pulse), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_rise2pulse.v, line:8:1, endln:26:10 |vpiName:out |vpiFullName:work@oh_rise2pulse.out |vpiNet: \_logic_net: (work@oh_rise2pulse.in_reg), line:16:19, endln:16:25 |vpiParent: - \_module: work@oh_rise2pulse (work@oh_rise2pulse), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_rise2pulse.v, line:8:1, endln:26:10 + \_module_inst: work@oh_rise2pulse (work@oh_rise2pulse), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_rise2pulse.v, line:8:1, endln:26:10 |vpiName:in_reg |vpiFullName:work@oh_rise2pulse.in_reg |vpiNetType:48 |vpiPort: \_port: (clk), line:10:23, endln:10:26 |vpiParent: - \_module: work@oh_rise2pulse (work@oh_rise2pulse), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_rise2pulse.v, line:8:1, endln:26:10 + \_module_inst: work@oh_rise2pulse (work@oh_rise2pulse), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_rise2pulse.v, line:8:1, endln:26:10 |vpiName:clk |vpiDirection:1 |vpiLowConn: @@ -53466,7 +53466,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (nreset), line:11:20, endln:11:26 |vpiParent: - \_module: work@oh_rise2pulse (work@oh_rise2pulse), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_rise2pulse.v, line:8:1, endln:26:10 + \_module_inst: work@oh_rise2pulse (work@oh_rise2pulse), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_rise2pulse.v, line:8:1, endln:26:10 |vpiName:nreset |vpiDirection:1 |vpiLowConn: @@ -53478,7 +53478,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (in), line:12:22, endln:12:24 |vpiParent: - \_module: work@oh_rise2pulse (work@oh_rise2pulse), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_rise2pulse.v, line:8:1, endln:26:10 + \_module_inst: work@oh_rise2pulse (work@oh_rise2pulse), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_rise2pulse.v, line:8:1, endln:26:10 |vpiName:in |vpiDirection:1 |vpiLowConn: @@ -53518,7 +53518,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (out), line:13:22, endln:13:25 |vpiParent: - \_module: work@oh_rise2pulse (work@oh_rise2pulse), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_rise2pulse.v, line:8:1, endln:26:10 + \_module_inst: work@oh_rise2pulse (work@oh_rise2pulse), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_rise2pulse.v, line:8:1, endln:26:10 |vpiName:out |vpiDirection:2 |vpiLowConn: @@ -53558,7 +53558,7 @@ design: (work@oh_fifo_async) |vpiProcess: \_always: , line:18:4, endln:22:37 |vpiParent: - \_module: work@oh_rise2pulse (work@oh_rise2pulse), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_rise2pulse.v, line:8:1, endln:26:10 + \_module_inst: work@oh_rise2pulse (work@oh_rise2pulse), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_rise2pulse.v, line:8:1, endln:26:10 |vpiStmt: \_event_control: , line:18:11, endln:18:44 |vpiParent: @@ -53725,7 +53725,7 @@ design: (work@oh_fifo_async) |vpiContAssign: \_cont_assign: , line:24:11, endln:24:51 |vpiParent: - \_module: work@oh_rise2pulse (work@oh_rise2pulse), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_rise2pulse.v, line:8:1, endln:26:10 + \_module_inst: work@oh_rise2pulse (work@oh_rise2pulse), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_rise2pulse.v, line:8:1, endln:26:10 |vpiRhs: \_operation: , line:24:25, endln:24:51 |vpiParent: @@ -53833,14 +53833,14 @@ design: (work@oh_fifo_async) |UINT:0 |vpiConstType:9 |uhdmallModules: -\_module: work@oh_rsync (work@oh_rsync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_rsync.v, line:8:1, endln:40:10 +\_module_inst: work@oh_rsync (work@oh_rsync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_rsync.v, line:8:1, endln:40:10 |vpiParent: \_design: (work@oh_fifo_async) |vpiFullName:work@oh_rsync |vpiParameter: \_parameter: (work@oh_rsync.SYNCPIPE), line:9:15, endln:9:23 |vpiParent: - \_module: work@oh_rsync (work@oh_rsync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_rsync.v, line:8:1, endln:40:10 + \_module_inst: work@oh_rsync (work@oh_rsync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_rsync.v, line:8:1, endln:40:10 |UINT:2 |vpiTypespec: \_int_typespec: @@ -53849,7 +53849,7 @@ design: (work@oh_fifo_async) |vpiParameter: \_parameter: (work@oh_rsync.SYN), line:10:15, endln:10:18 |vpiParent: - \_module: work@oh_rsync (work@oh_rsync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_rsync.v, line:8:1, endln:40:10 + \_module_inst: work@oh_rsync (work@oh_rsync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_rsync.v, line:8:1, endln:40:10 |STRING:TRUE |vpiTypespec: \_string_typespec: @@ -53858,7 +53858,7 @@ design: (work@oh_fifo_async) |vpiParameter: \_parameter: (work@oh_rsync.TYPE), line:11:15, endln:11:19 |vpiParent: - \_module: work@oh_rsync (work@oh_rsync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_rsync.v, line:8:1, endln:40:10 + \_module_inst: work@oh_rsync (work@oh_rsync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_rsync.v, line:8:1, endln:40:10 |STRING:DEFAULT |vpiTypespec: \_string_typespec: @@ -53867,7 +53867,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:9:15, endln:9:27 |vpiParent: - \_module: work@oh_rsync (work@oh_rsync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_rsync.v, line:8:1, endln:40:10 + \_module_inst: work@oh_rsync (work@oh_rsync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_rsync.v, line:8:1, endln:40:10 |vpiRhs: \_constant: , line:9:26, endln:9:27 |vpiDecompile:2 @@ -53881,7 +53881,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:10:15, endln:10:32 |vpiParent: - \_module: work@oh_rsync (work@oh_rsync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_rsync.v, line:8:1, endln:40:10 + \_module_inst: work@oh_rsync (work@oh_rsync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_rsync.v, line:8:1, endln:40:10 |vpiRhs: \_constant: , line:10:26, endln:10:32 |vpiDecompile:TRUE @@ -53895,7 +53895,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:11:15, endln:11:35 |vpiParent: - \_module: work@oh_rsync (work@oh_rsync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_rsync.v, line:8:1, endln:40:10 + \_module_inst: work@oh_rsync (work@oh_rsync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_rsync.v, line:8:1, endln:40:10 |vpiRhs: \_constant: , line:11:26, endln:11:35 |vpiDecompile:DEFAULT @@ -53911,25 +53911,25 @@ design: (work@oh_fifo_async) |vpiNet: \_logic_net: (work@oh_rsync.clk), line:14:12, endln:14:15 |vpiParent: - \_module: work@oh_rsync (work@oh_rsync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_rsync.v, line:8:1, endln:40:10 + \_module_inst: work@oh_rsync (work@oh_rsync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_rsync.v, line:8:1, endln:40:10 |vpiName:clk |vpiFullName:work@oh_rsync.clk |vpiNet: \_logic_net: (work@oh_rsync.nrst_in), line:15:12, endln:15:19 |vpiParent: - \_module: work@oh_rsync (work@oh_rsync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_rsync.v, line:8:1, endln:40:10 + \_module_inst: work@oh_rsync (work@oh_rsync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_rsync.v, line:8:1, endln:40:10 |vpiName:nrst_in |vpiFullName:work@oh_rsync.nrst_in |vpiNet: \_logic_net: (work@oh_rsync.nrst_out), line:16:12, endln:16:20 |vpiParent: - \_module: work@oh_rsync (work@oh_rsync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_rsync.v, line:8:1, endln:40:10 + \_module_inst: work@oh_rsync (work@oh_rsync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_rsync.v, line:8:1, endln:40:10 |vpiName:nrst_out |vpiFullName:work@oh_rsync.nrst_out |vpiPort: \_port: (clk), line:14:12, endln:14:15 |vpiParent: - \_module: work@oh_rsync (work@oh_rsync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_rsync.v, line:8:1, endln:40:10 + \_module_inst: work@oh_rsync (work@oh_rsync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_rsync.v, line:8:1, endln:40:10 |vpiName:clk |vpiDirection:1 |vpiLowConn: @@ -53941,7 +53941,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (nrst_in), line:15:12, endln:15:19 |vpiParent: - \_module: work@oh_rsync (work@oh_rsync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_rsync.v, line:8:1, endln:40:10 + \_module_inst: work@oh_rsync (work@oh_rsync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_rsync.v, line:8:1, endln:40:10 |vpiName:nrst_in |vpiDirection:1 |vpiLowConn: @@ -53953,7 +53953,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (nrst_out), line:16:12, endln:16:20 |vpiParent: - \_module: work@oh_rsync (work@oh_rsync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_rsync.v, line:8:1, endln:40:10 + \_module_inst: work@oh_rsync (work@oh_rsync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_rsync.v, line:8:1, endln:40:10 |vpiName:nrst_out |vpiDirection:2 |vpiLowConn: @@ -53963,14 +53963,14 @@ design: (work@oh_fifo_async) |vpiTypedef: \_logic_typespec: , line:16:12, endln:16:12 |uhdmallModules: -\_module: work@oh_sdffq (work@oh_sdffq), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_sdffq.v, line:8:1, endln:20:10 +\_module_inst: work@oh_sdffq (work@oh_sdffq), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_sdffq.v, line:8:1, endln:20:10 |vpiParent: \_design: (work@oh_fifo_async) |vpiFullName:work@oh_sdffq |vpiParameter: \_parameter: (work@oh_sdffq.DW), line:8:29, endln:8:31 |vpiParent: - \_module: work@oh_sdffq (work@oh_sdffq), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_sdffq.v, line:8:1, endln:20:10 + \_module_inst: work@oh_sdffq (work@oh_sdffq), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_sdffq.v, line:8:1, endln:20:10 |UINT:1 |vpiTypespec: \_int_typespec: @@ -53979,7 +53979,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:8:29, endln:8:35 |vpiParent: - \_module: work@oh_sdffq (work@oh_sdffq), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_sdffq.v, line:8:1, endln:20:10 + \_module_inst: work@oh_sdffq (work@oh_sdffq), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_sdffq.v, line:8:1, endln:20:10 |vpiRhs: \_constant: , line:8:34, endln:8:35 |vpiDecompile:1 @@ -53995,38 +53995,38 @@ design: (work@oh_fifo_async) |vpiNet: \_logic_net: (work@oh_sdffq.d), line:10:21, endln:10:22 |vpiParent: - \_module: work@oh_sdffq (work@oh_sdffq), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_sdffq.v, line:8:1, endln:20:10 + \_module_inst: work@oh_sdffq (work@oh_sdffq), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_sdffq.v, line:8:1, endln:20:10 |vpiName:d |vpiFullName:work@oh_sdffq.d |vpiNet: \_logic_net: (work@oh_sdffq.si), line:11:21, endln:11:23 |vpiParent: - \_module: work@oh_sdffq (work@oh_sdffq), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_sdffq.v, line:8:1, endln:20:10 + \_module_inst: work@oh_sdffq (work@oh_sdffq), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_sdffq.v, line:8:1, endln:20:10 |vpiName:si |vpiFullName:work@oh_sdffq.si |vpiNet: \_logic_net: (work@oh_sdffq.se), line:12:21, endln:12:23 |vpiParent: - \_module: work@oh_sdffq (work@oh_sdffq), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_sdffq.v, line:8:1, endln:20:10 + \_module_inst: work@oh_sdffq (work@oh_sdffq), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_sdffq.v, line:8:1, endln:20:10 |vpiName:se |vpiFullName:work@oh_sdffq.se |vpiNet: \_logic_net: (work@oh_sdffq.clk), line:13:21, endln:13:24 |vpiParent: - \_module: work@oh_sdffq (work@oh_sdffq), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_sdffq.v, line:8:1, endln:20:10 + \_module_inst: work@oh_sdffq (work@oh_sdffq), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_sdffq.v, line:8:1, endln:20:10 |vpiName:clk |vpiFullName:work@oh_sdffq.clk |vpiNet: \_logic_net: (work@oh_sdffq.q), line:14:25, endln:14:26 |vpiParent: - \_module: work@oh_sdffq (work@oh_sdffq), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_sdffq.v, line:8:1, endln:20:10 + \_module_inst: work@oh_sdffq (work@oh_sdffq), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_sdffq.v, line:8:1, endln:20:10 |vpiName:q |vpiFullName:work@oh_sdffq.q |vpiNetType:48 |vpiPort: \_port: (d), line:10:21, endln:10:22 |vpiParent: - \_module: work@oh_sdffq (work@oh_sdffq), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_sdffq.v, line:8:1, endln:20:10 + \_module_inst: work@oh_sdffq (work@oh_sdffq), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_sdffq.v, line:8:1, endln:20:10 |vpiName:d |vpiDirection:1 |vpiLowConn: @@ -54066,7 +54066,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (si), line:11:21, endln:11:23 |vpiParent: - \_module: work@oh_sdffq (work@oh_sdffq), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_sdffq.v, line:8:1, endln:20:10 + \_module_inst: work@oh_sdffq (work@oh_sdffq), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_sdffq.v, line:8:1, endln:20:10 |vpiName:si |vpiDirection:1 |vpiLowConn: @@ -54106,7 +54106,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (se), line:12:21, endln:12:23 |vpiParent: - \_module: work@oh_sdffq (work@oh_sdffq), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_sdffq.v, line:8:1, endln:20:10 + \_module_inst: work@oh_sdffq (work@oh_sdffq), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_sdffq.v, line:8:1, endln:20:10 |vpiName:se |vpiDirection:1 |vpiLowConn: @@ -54146,7 +54146,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (clk), line:13:21, endln:13:24 |vpiParent: - \_module: work@oh_sdffq (work@oh_sdffq), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_sdffq.v, line:8:1, endln:20:10 + \_module_inst: work@oh_sdffq (work@oh_sdffq), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_sdffq.v, line:8:1, endln:20:10 |vpiName:clk |vpiDirection:1 |vpiLowConn: @@ -54186,7 +54186,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (q), line:14:25, endln:14:26 |vpiParent: - \_module: work@oh_sdffq (work@oh_sdffq), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_sdffq.v, line:8:1, endln:20:10 + \_module_inst: work@oh_sdffq (work@oh_sdffq), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_sdffq.v, line:8:1, endln:20:10 |vpiName:q |vpiDirection:2 |vpiLowConn: @@ -54226,7 +54226,7 @@ design: (work@oh_fifo_async) |vpiProcess: \_always: , line:17:4, endln:18:25 |vpiParent: - \_module: work@oh_sdffq (work@oh_sdffq), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_sdffq.v, line:8:1, endln:20:10 + \_module_inst: work@oh_sdffq (work@oh_sdffq), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_sdffq.v, line:8:1, endln:20:10 |vpiStmt: \_event_control: , line:17:11, endln:17:26 |vpiParent: @@ -54278,14 +54278,14 @@ design: (work@oh_fifo_async) |vpiFullName:work@oh_sdffq.q |vpiAlwaysType:1 |uhdmallModules: -\_module: work@oh_sdffqn (work@oh_sdffqn), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_sdffqn.v, line:8:1, endln:20:10 +\_module_inst: work@oh_sdffqn (work@oh_sdffqn), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_sdffqn.v, line:8:1, endln:20:10 |vpiParent: \_design: (work@oh_fifo_async) |vpiFullName:work@oh_sdffqn |vpiParameter: \_parameter: (work@oh_sdffqn.DW), line:8:30, endln:8:32 |vpiParent: - \_module: work@oh_sdffqn (work@oh_sdffqn), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_sdffqn.v, line:8:1, endln:20:10 + \_module_inst: work@oh_sdffqn (work@oh_sdffqn), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_sdffqn.v, line:8:1, endln:20:10 |UINT:1 |vpiTypespec: \_int_typespec: @@ -54294,7 +54294,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:8:30, endln:8:36 |vpiParent: - \_module: work@oh_sdffqn (work@oh_sdffqn), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_sdffqn.v, line:8:1, endln:20:10 + \_module_inst: work@oh_sdffqn (work@oh_sdffqn), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_sdffqn.v, line:8:1, endln:20:10 |vpiRhs: \_constant: , line:8:35, endln:8:36 |vpiDecompile:1 @@ -54310,38 +54310,38 @@ design: (work@oh_fifo_async) |vpiNet: \_logic_net: (work@oh_sdffqn.d), line:10:21, endln:10:22 |vpiParent: - \_module: work@oh_sdffqn (work@oh_sdffqn), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_sdffqn.v, line:8:1, endln:20:10 + \_module_inst: work@oh_sdffqn (work@oh_sdffqn), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_sdffqn.v, line:8:1, endln:20:10 |vpiName:d |vpiFullName:work@oh_sdffqn.d |vpiNet: \_logic_net: (work@oh_sdffqn.si), line:11:21, endln:11:23 |vpiParent: - \_module: work@oh_sdffqn (work@oh_sdffqn), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_sdffqn.v, line:8:1, endln:20:10 + \_module_inst: work@oh_sdffqn (work@oh_sdffqn), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_sdffqn.v, line:8:1, endln:20:10 |vpiName:si |vpiFullName:work@oh_sdffqn.si |vpiNet: \_logic_net: (work@oh_sdffqn.se), line:12:21, endln:12:23 |vpiParent: - \_module: work@oh_sdffqn (work@oh_sdffqn), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_sdffqn.v, line:8:1, endln:20:10 + \_module_inst: work@oh_sdffqn (work@oh_sdffqn), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_sdffqn.v, line:8:1, endln:20:10 |vpiName:se |vpiFullName:work@oh_sdffqn.se |vpiNet: \_logic_net: (work@oh_sdffqn.clk), line:13:21, endln:13:24 |vpiParent: - \_module: work@oh_sdffqn (work@oh_sdffqn), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_sdffqn.v, line:8:1, endln:20:10 + \_module_inst: work@oh_sdffqn (work@oh_sdffqn), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_sdffqn.v, line:8:1, endln:20:10 |vpiName:clk |vpiFullName:work@oh_sdffqn.clk |vpiNet: \_logic_net: (work@oh_sdffqn.qn), line:14:25, endln:14:27 |vpiParent: - \_module: work@oh_sdffqn (work@oh_sdffqn), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_sdffqn.v, line:8:1, endln:20:10 + \_module_inst: work@oh_sdffqn (work@oh_sdffqn), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_sdffqn.v, line:8:1, endln:20:10 |vpiName:qn |vpiFullName:work@oh_sdffqn.qn |vpiNetType:48 |vpiPort: \_port: (d), line:10:21, endln:10:22 |vpiParent: - \_module: work@oh_sdffqn (work@oh_sdffqn), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_sdffqn.v, line:8:1, endln:20:10 + \_module_inst: work@oh_sdffqn (work@oh_sdffqn), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_sdffqn.v, line:8:1, endln:20:10 |vpiName:d |vpiDirection:1 |vpiLowConn: @@ -54381,7 +54381,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (si), line:11:21, endln:11:23 |vpiParent: - \_module: work@oh_sdffqn (work@oh_sdffqn), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_sdffqn.v, line:8:1, endln:20:10 + \_module_inst: work@oh_sdffqn (work@oh_sdffqn), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_sdffqn.v, line:8:1, endln:20:10 |vpiName:si |vpiDirection:1 |vpiLowConn: @@ -54421,7 +54421,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (se), line:12:21, endln:12:23 |vpiParent: - \_module: work@oh_sdffqn (work@oh_sdffqn), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_sdffqn.v, line:8:1, endln:20:10 + \_module_inst: work@oh_sdffqn (work@oh_sdffqn), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_sdffqn.v, line:8:1, endln:20:10 |vpiName:se |vpiDirection:1 |vpiLowConn: @@ -54461,7 +54461,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (clk), line:13:21, endln:13:24 |vpiParent: - \_module: work@oh_sdffqn (work@oh_sdffqn), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_sdffqn.v, line:8:1, endln:20:10 + \_module_inst: work@oh_sdffqn (work@oh_sdffqn), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_sdffqn.v, line:8:1, endln:20:10 |vpiName:clk |vpiDirection:1 |vpiLowConn: @@ -54501,7 +54501,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (qn), line:14:25, endln:14:27 |vpiParent: - \_module: work@oh_sdffqn (work@oh_sdffqn), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_sdffqn.v, line:8:1, endln:20:10 + \_module_inst: work@oh_sdffqn (work@oh_sdffqn), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_sdffqn.v, line:8:1, endln:20:10 |vpiName:qn |vpiDirection:2 |vpiLowConn: @@ -54541,7 +54541,7 @@ design: (work@oh_fifo_async) |vpiProcess: \_always: , line:17:4, endln:18:26 |vpiParent: - \_module: work@oh_sdffqn (work@oh_sdffqn), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_sdffqn.v, line:8:1, endln:20:10 + \_module_inst: work@oh_sdffqn (work@oh_sdffqn), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_sdffqn.v, line:8:1, endln:20:10 |vpiStmt: \_event_control: , line:17:11, endln:17:26 |vpiParent: @@ -54603,14 +54603,14 @@ design: (work@oh_fifo_async) |vpiFullName:work@oh_sdffqn.qn |vpiAlwaysType:1 |uhdmallModules: -\_module: work@oh_sdffrq (work@oh_sdffrq), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_sdffrq.v, line:9:1, endln:25:10 +\_module_inst: work@oh_sdffrq (work@oh_sdffrq), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_sdffrq.v, line:9:1, endln:25:10 |vpiParent: \_design: (work@oh_fifo_async) |vpiFullName:work@oh_sdffrq |vpiParameter: \_parameter: (work@oh_sdffrq.DW), line:9:30, endln:9:32 |vpiParent: - \_module: work@oh_sdffrq (work@oh_sdffrq), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_sdffrq.v, line:9:1, endln:25:10 + \_module_inst: work@oh_sdffrq (work@oh_sdffrq), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_sdffrq.v, line:9:1, endln:25:10 |UINT:1 |vpiTypespec: \_int_typespec: @@ -54619,7 +54619,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:9:30, endln:9:36 |vpiParent: - \_module: work@oh_sdffrq (work@oh_sdffrq), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_sdffrq.v, line:9:1, endln:25:10 + \_module_inst: work@oh_sdffrq (work@oh_sdffrq), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_sdffrq.v, line:9:1, endln:25:10 |vpiRhs: \_constant: , line:9:35, endln:9:36 |vpiDecompile:1 @@ -54635,44 +54635,44 @@ design: (work@oh_fifo_async) |vpiNet: \_logic_net: (work@oh_sdffrq.d), line:11:21, endln:11:22 |vpiParent: - \_module: work@oh_sdffrq (work@oh_sdffrq), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_sdffrq.v, line:9:1, endln:25:10 + \_module_inst: work@oh_sdffrq (work@oh_sdffrq), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_sdffrq.v, line:9:1, endln:25:10 |vpiName:d |vpiFullName:work@oh_sdffrq.d |vpiNet: \_logic_net: (work@oh_sdffrq.si), line:12:21, endln:12:23 |vpiParent: - \_module: work@oh_sdffrq (work@oh_sdffrq), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_sdffrq.v, line:9:1, endln:25:10 + \_module_inst: work@oh_sdffrq (work@oh_sdffrq), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_sdffrq.v, line:9:1, endln:25:10 |vpiName:si |vpiFullName:work@oh_sdffrq.si |vpiNet: \_logic_net: (work@oh_sdffrq.se), line:13:21, endln:13:23 |vpiParent: - \_module: work@oh_sdffrq (work@oh_sdffrq), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_sdffrq.v, line:9:1, endln:25:10 + \_module_inst: work@oh_sdffrq (work@oh_sdffrq), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_sdffrq.v, line:9:1, endln:25:10 |vpiName:se |vpiFullName:work@oh_sdffrq.se |vpiNet: \_logic_net: (work@oh_sdffrq.clk), line:14:21, endln:14:24 |vpiParent: - \_module: work@oh_sdffrq (work@oh_sdffrq), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_sdffrq.v, line:9:1, endln:25:10 + \_module_inst: work@oh_sdffrq (work@oh_sdffrq), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_sdffrq.v, line:9:1, endln:25:10 |vpiName:clk |vpiFullName:work@oh_sdffrq.clk |vpiNet: \_logic_net: (work@oh_sdffrq.nreset), line:15:21, endln:15:27 |vpiParent: - \_module: work@oh_sdffrq (work@oh_sdffrq), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_sdffrq.v, line:9:1, endln:25:10 + \_module_inst: work@oh_sdffrq (work@oh_sdffrq), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_sdffrq.v, line:9:1, endln:25:10 |vpiName:nreset |vpiFullName:work@oh_sdffrq.nreset |vpiNet: \_logic_net: (work@oh_sdffrq.q), line:16:25, endln:16:26 |vpiParent: - \_module: work@oh_sdffrq (work@oh_sdffrq), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_sdffrq.v, line:9:1, endln:25:10 + \_module_inst: work@oh_sdffrq (work@oh_sdffrq), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_sdffrq.v, line:9:1, endln:25:10 |vpiName:q |vpiFullName:work@oh_sdffrq.q |vpiNetType:48 |vpiPort: \_port: (d), line:11:21, endln:11:22 |vpiParent: - \_module: work@oh_sdffrq (work@oh_sdffrq), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_sdffrq.v, line:9:1, endln:25:10 + \_module_inst: work@oh_sdffrq (work@oh_sdffrq), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_sdffrq.v, line:9:1, endln:25:10 |vpiName:d |vpiDirection:1 |vpiLowConn: @@ -54712,7 +54712,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (si), line:12:21, endln:12:23 |vpiParent: - \_module: work@oh_sdffrq (work@oh_sdffrq), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_sdffrq.v, line:9:1, endln:25:10 + \_module_inst: work@oh_sdffrq (work@oh_sdffrq), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_sdffrq.v, line:9:1, endln:25:10 |vpiName:si |vpiDirection:1 |vpiLowConn: @@ -54752,7 +54752,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (se), line:13:21, endln:13:23 |vpiParent: - \_module: work@oh_sdffrq (work@oh_sdffrq), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_sdffrq.v, line:9:1, endln:25:10 + \_module_inst: work@oh_sdffrq (work@oh_sdffrq), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_sdffrq.v, line:9:1, endln:25:10 |vpiName:se |vpiDirection:1 |vpiLowConn: @@ -54792,7 +54792,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (clk), line:14:21, endln:14:24 |vpiParent: - \_module: work@oh_sdffrq (work@oh_sdffrq), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_sdffrq.v, line:9:1, endln:25:10 + \_module_inst: work@oh_sdffrq (work@oh_sdffrq), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_sdffrq.v, line:9:1, endln:25:10 |vpiName:clk |vpiDirection:1 |vpiLowConn: @@ -54832,7 +54832,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (nreset), line:15:21, endln:15:27 |vpiParent: - \_module: work@oh_sdffrq (work@oh_sdffrq), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_sdffrq.v, line:9:1, endln:25:10 + \_module_inst: work@oh_sdffrq (work@oh_sdffrq), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_sdffrq.v, line:9:1, endln:25:10 |vpiName:nreset |vpiDirection:1 |vpiLowConn: @@ -54872,7 +54872,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (q), line:16:25, endln:16:26 |vpiParent: - \_module: work@oh_sdffrq (work@oh_sdffrq), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_sdffrq.v, line:9:1, endln:25:10 + \_module_inst: work@oh_sdffrq (work@oh_sdffrq), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_sdffrq.v, line:9:1, endln:25:10 |vpiName:q |vpiDirection:2 |vpiLowConn: @@ -54912,7 +54912,7 @@ design: (work@oh_fifo_async) |vpiProcess: \_always: , line:19:4, endln:23:25 |vpiParent: - \_module: work@oh_sdffrq (work@oh_sdffrq), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_sdffrq.v, line:9:1, endln:25:10 + \_module_inst: work@oh_sdffrq (work@oh_sdffrq), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_sdffrq.v, line:9:1, endln:25:10 |vpiStmt: \_event_control: , line:19:11, endln:19:44 |vpiParent: @@ -55007,14 +55007,14 @@ design: (work@oh_fifo_async) |vpiFullName:work@oh_sdffrq.q |vpiAlwaysType:1 |uhdmallModules: -\_module: work@oh_sdffrqn (work@oh_sdffrqn), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_sdffrqn.v, line:8:1, endln:24:10 +\_module_inst: work@oh_sdffrqn (work@oh_sdffrqn), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_sdffrqn.v, line:8:1, endln:24:10 |vpiParent: \_design: (work@oh_fifo_async) |vpiFullName:work@oh_sdffrqn |vpiParameter: \_parameter: (work@oh_sdffrqn.DW), line:8:31, endln:8:33 |vpiParent: - \_module: work@oh_sdffrqn (work@oh_sdffrqn), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_sdffrqn.v, line:8:1, endln:24:10 + \_module_inst: work@oh_sdffrqn (work@oh_sdffrqn), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_sdffrqn.v, line:8:1, endln:24:10 |UINT:1 |vpiTypespec: \_int_typespec: @@ -55023,7 +55023,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:8:31, endln:8:37 |vpiParent: - \_module: work@oh_sdffrqn (work@oh_sdffrqn), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_sdffrqn.v, line:8:1, endln:24:10 + \_module_inst: work@oh_sdffrqn (work@oh_sdffrqn), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_sdffrqn.v, line:8:1, endln:24:10 |vpiRhs: \_constant: , line:8:36, endln:8:37 |vpiDecompile:1 @@ -55039,44 +55039,44 @@ design: (work@oh_fifo_async) |vpiNet: \_logic_net: (work@oh_sdffrqn.d), line:10:21, endln:10:22 |vpiParent: - \_module: work@oh_sdffrqn (work@oh_sdffrqn), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_sdffrqn.v, line:8:1, endln:24:10 + \_module_inst: work@oh_sdffrqn (work@oh_sdffrqn), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_sdffrqn.v, line:8:1, endln:24:10 |vpiName:d |vpiFullName:work@oh_sdffrqn.d |vpiNet: \_logic_net: (work@oh_sdffrqn.si), line:11:21, endln:11:23 |vpiParent: - \_module: work@oh_sdffrqn (work@oh_sdffrqn), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_sdffrqn.v, line:8:1, endln:24:10 + \_module_inst: work@oh_sdffrqn (work@oh_sdffrqn), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_sdffrqn.v, line:8:1, endln:24:10 |vpiName:si |vpiFullName:work@oh_sdffrqn.si |vpiNet: \_logic_net: (work@oh_sdffrqn.se), line:12:21, endln:12:23 |vpiParent: - \_module: work@oh_sdffrqn (work@oh_sdffrqn), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_sdffrqn.v, line:8:1, endln:24:10 + \_module_inst: work@oh_sdffrqn (work@oh_sdffrqn), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_sdffrqn.v, line:8:1, endln:24:10 |vpiName:se |vpiFullName:work@oh_sdffrqn.se |vpiNet: \_logic_net: (work@oh_sdffrqn.clk), line:13:21, endln:13:24 |vpiParent: - \_module: work@oh_sdffrqn (work@oh_sdffrqn), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_sdffrqn.v, line:8:1, endln:24:10 + \_module_inst: work@oh_sdffrqn (work@oh_sdffrqn), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_sdffrqn.v, line:8:1, endln:24:10 |vpiName:clk |vpiFullName:work@oh_sdffrqn.clk |vpiNet: \_logic_net: (work@oh_sdffrqn.nreset), line:14:21, endln:14:27 |vpiParent: - \_module: work@oh_sdffrqn (work@oh_sdffrqn), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_sdffrqn.v, line:8:1, endln:24:10 + \_module_inst: work@oh_sdffrqn (work@oh_sdffrqn), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_sdffrqn.v, line:8:1, endln:24:10 |vpiName:nreset |vpiFullName:work@oh_sdffrqn.nreset |vpiNet: \_logic_net: (work@oh_sdffrqn.qn), line:15:25, endln:15:27 |vpiParent: - \_module: work@oh_sdffrqn (work@oh_sdffrqn), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_sdffrqn.v, line:8:1, endln:24:10 + \_module_inst: work@oh_sdffrqn (work@oh_sdffrqn), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_sdffrqn.v, line:8:1, endln:24:10 |vpiName:qn |vpiFullName:work@oh_sdffrqn.qn |vpiNetType:48 |vpiPort: \_port: (d), line:10:21, endln:10:22 |vpiParent: - \_module: work@oh_sdffrqn (work@oh_sdffrqn), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_sdffrqn.v, line:8:1, endln:24:10 + \_module_inst: work@oh_sdffrqn (work@oh_sdffrqn), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_sdffrqn.v, line:8:1, endln:24:10 |vpiName:d |vpiDirection:1 |vpiLowConn: @@ -55116,7 +55116,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (si), line:11:21, endln:11:23 |vpiParent: - \_module: work@oh_sdffrqn (work@oh_sdffrqn), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_sdffrqn.v, line:8:1, endln:24:10 + \_module_inst: work@oh_sdffrqn (work@oh_sdffrqn), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_sdffrqn.v, line:8:1, endln:24:10 |vpiName:si |vpiDirection:1 |vpiLowConn: @@ -55156,7 +55156,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (se), line:12:21, endln:12:23 |vpiParent: - \_module: work@oh_sdffrqn (work@oh_sdffrqn), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_sdffrqn.v, line:8:1, endln:24:10 + \_module_inst: work@oh_sdffrqn (work@oh_sdffrqn), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_sdffrqn.v, line:8:1, endln:24:10 |vpiName:se |vpiDirection:1 |vpiLowConn: @@ -55196,7 +55196,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (clk), line:13:21, endln:13:24 |vpiParent: - \_module: work@oh_sdffrqn (work@oh_sdffrqn), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_sdffrqn.v, line:8:1, endln:24:10 + \_module_inst: work@oh_sdffrqn (work@oh_sdffrqn), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_sdffrqn.v, line:8:1, endln:24:10 |vpiName:clk |vpiDirection:1 |vpiLowConn: @@ -55236,7 +55236,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (nreset), line:14:21, endln:14:27 |vpiParent: - \_module: work@oh_sdffrqn (work@oh_sdffrqn), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_sdffrqn.v, line:8:1, endln:24:10 + \_module_inst: work@oh_sdffrqn (work@oh_sdffrqn), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_sdffrqn.v, line:8:1, endln:24:10 |vpiName:nreset |vpiDirection:1 |vpiLowConn: @@ -55276,7 +55276,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (qn), line:15:25, endln:15:27 |vpiParent: - \_module: work@oh_sdffrqn (work@oh_sdffrqn), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_sdffrqn.v, line:8:1, endln:24:10 + \_module_inst: work@oh_sdffrqn (work@oh_sdffrqn), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_sdffrqn.v, line:8:1, endln:24:10 |vpiName:qn |vpiDirection:2 |vpiLowConn: @@ -55316,7 +55316,7 @@ design: (work@oh_fifo_async) |vpiProcess: \_always: , line:18:4, endln:22:29 |vpiParent: - \_module: work@oh_sdffrqn (work@oh_sdffrqn), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_sdffrqn.v, line:8:1, endln:24:10 + \_module_inst: work@oh_sdffrqn (work@oh_sdffrqn), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_sdffrqn.v, line:8:1, endln:24:10 |vpiStmt: \_event_control: , line:18:11, endln:18:44 |vpiParent: @@ -55436,14 +55436,14 @@ design: (work@oh_fifo_async) |vpiFullName:work@oh_sdffrqn.qn |vpiAlwaysType:1 |uhdmallModules: -\_module: work@oh_sdffsq (work@oh_sdffsq), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_sdffsq.v, line:8:1, endln:24:10 +\_module_inst: work@oh_sdffsq (work@oh_sdffsq), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_sdffsq.v, line:8:1, endln:24:10 |vpiParent: \_design: (work@oh_fifo_async) |vpiFullName:work@oh_sdffsq |vpiParameter: \_parameter: (work@oh_sdffsq.DW), line:8:30, endln:8:32 |vpiParent: - \_module: work@oh_sdffsq (work@oh_sdffsq), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_sdffsq.v, line:8:1, endln:24:10 + \_module_inst: work@oh_sdffsq (work@oh_sdffsq), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_sdffsq.v, line:8:1, endln:24:10 |UINT:1 |vpiTypespec: \_int_typespec: @@ -55452,7 +55452,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:8:30, endln:8:36 |vpiParent: - \_module: work@oh_sdffsq (work@oh_sdffsq), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_sdffsq.v, line:8:1, endln:24:10 + \_module_inst: work@oh_sdffsq (work@oh_sdffsq), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_sdffsq.v, line:8:1, endln:24:10 |vpiRhs: \_constant: , line:8:35, endln:8:36 |vpiDecompile:1 @@ -55468,44 +55468,44 @@ design: (work@oh_fifo_async) |vpiNet: \_logic_net: (work@oh_sdffsq.d), line:10:21, endln:10:22 |vpiParent: - \_module: work@oh_sdffsq (work@oh_sdffsq), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_sdffsq.v, line:8:1, endln:24:10 + \_module_inst: work@oh_sdffsq (work@oh_sdffsq), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_sdffsq.v, line:8:1, endln:24:10 |vpiName:d |vpiFullName:work@oh_sdffsq.d |vpiNet: \_logic_net: (work@oh_sdffsq.si), line:11:21, endln:11:23 |vpiParent: - \_module: work@oh_sdffsq (work@oh_sdffsq), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_sdffsq.v, line:8:1, endln:24:10 + \_module_inst: work@oh_sdffsq (work@oh_sdffsq), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_sdffsq.v, line:8:1, endln:24:10 |vpiName:si |vpiFullName:work@oh_sdffsq.si |vpiNet: \_logic_net: (work@oh_sdffsq.se), line:12:21, endln:12:23 |vpiParent: - \_module: work@oh_sdffsq (work@oh_sdffsq), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_sdffsq.v, line:8:1, endln:24:10 + \_module_inst: work@oh_sdffsq (work@oh_sdffsq), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_sdffsq.v, line:8:1, endln:24:10 |vpiName:se |vpiFullName:work@oh_sdffsq.se |vpiNet: \_logic_net: (work@oh_sdffsq.clk), line:13:21, endln:13:24 |vpiParent: - \_module: work@oh_sdffsq (work@oh_sdffsq), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_sdffsq.v, line:8:1, endln:24:10 + \_module_inst: work@oh_sdffsq (work@oh_sdffsq), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_sdffsq.v, line:8:1, endln:24:10 |vpiName:clk |vpiFullName:work@oh_sdffsq.clk |vpiNet: \_logic_net: (work@oh_sdffsq.nset), line:14:21, endln:14:25 |vpiParent: - \_module: work@oh_sdffsq (work@oh_sdffsq), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_sdffsq.v, line:8:1, endln:24:10 + \_module_inst: work@oh_sdffsq (work@oh_sdffsq), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_sdffsq.v, line:8:1, endln:24:10 |vpiName:nset |vpiFullName:work@oh_sdffsq.nset |vpiNet: \_logic_net: (work@oh_sdffsq.q), line:15:25, endln:15:26 |vpiParent: - \_module: work@oh_sdffsq (work@oh_sdffsq), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_sdffsq.v, line:8:1, endln:24:10 + \_module_inst: work@oh_sdffsq (work@oh_sdffsq), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_sdffsq.v, line:8:1, endln:24:10 |vpiName:q |vpiFullName:work@oh_sdffsq.q |vpiNetType:48 |vpiPort: \_port: (d), line:10:21, endln:10:22 |vpiParent: - \_module: work@oh_sdffsq (work@oh_sdffsq), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_sdffsq.v, line:8:1, endln:24:10 + \_module_inst: work@oh_sdffsq (work@oh_sdffsq), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_sdffsq.v, line:8:1, endln:24:10 |vpiName:d |vpiDirection:1 |vpiLowConn: @@ -55545,7 +55545,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (si), line:11:21, endln:11:23 |vpiParent: - \_module: work@oh_sdffsq (work@oh_sdffsq), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_sdffsq.v, line:8:1, endln:24:10 + \_module_inst: work@oh_sdffsq (work@oh_sdffsq), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_sdffsq.v, line:8:1, endln:24:10 |vpiName:si |vpiDirection:1 |vpiLowConn: @@ -55585,7 +55585,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (se), line:12:21, endln:12:23 |vpiParent: - \_module: work@oh_sdffsq (work@oh_sdffsq), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_sdffsq.v, line:8:1, endln:24:10 + \_module_inst: work@oh_sdffsq (work@oh_sdffsq), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_sdffsq.v, line:8:1, endln:24:10 |vpiName:se |vpiDirection:1 |vpiLowConn: @@ -55625,7 +55625,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (clk), line:13:21, endln:13:24 |vpiParent: - \_module: work@oh_sdffsq (work@oh_sdffsq), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_sdffsq.v, line:8:1, endln:24:10 + \_module_inst: work@oh_sdffsq (work@oh_sdffsq), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_sdffsq.v, line:8:1, endln:24:10 |vpiName:clk |vpiDirection:1 |vpiLowConn: @@ -55665,7 +55665,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (nset), line:14:21, endln:14:25 |vpiParent: - \_module: work@oh_sdffsq (work@oh_sdffsq), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_sdffsq.v, line:8:1, endln:24:10 + \_module_inst: work@oh_sdffsq (work@oh_sdffsq), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_sdffsq.v, line:8:1, endln:24:10 |vpiName:nset |vpiDirection:1 |vpiLowConn: @@ -55705,7 +55705,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (q), line:15:25, endln:15:26 |vpiParent: - \_module: work@oh_sdffsq (work@oh_sdffsq), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_sdffsq.v, line:8:1, endln:24:10 + \_module_inst: work@oh_sdffsq (work@oh_sdffsq), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_sdffsq.v, line:8:1, endln:24:10 |vpiName:q |vpiDirection:2 |vpiLowConn: @@ -55745,7 +55745,7 @@ design: (work@oh_fifo_async) |vpiProcess: \_always: , line:18:4, endln:22:25 |vpiParent: - \_module: work@oh_sdffsq (work@oh_sdffsq), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_sdffsq.v, line:8:1, endln:24:10 + \_module_inst: work@oh_sdffsq (work@oh_sdffsq), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_sdffsq.v, line:8:1, endln:24:10 |vpiStmt: \_event_control: , line:18:11, endln:18:42 |vpiParent: @@ -55855,14 +55855,14 @@ design: (work@oh_fifo_async) |vpiFullName:work@oh_sdffsq.q |vpiAlwaysType:1 |uhdmallModules: -\_module: work@oh_sdffsqn (work@oh_sdffsqn), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_sdffsqn.v, line:8:1, endln:24:10 +\_module_inst: work@oh_sdffsqn (work@oh_sdffsqn), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_sdffsqn.v, line:8:1, endln:24:10 |vpiParent: \_design: (work@oh_fifo_async) |vpiFullName:work@oh_sdffsqn |vpiParameter: \_parameter: (work@oh_sdffsqn.DW), line:8:31, endln:8:33 |vpiParent: - \_module: work@oh_sdffsqn (work@oh_sdffsqn), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_sdffsqn.v, line:8:1, endln:24:10 + \_module_inst: work@oh_sdffsqn (work@oh_sdffsqn), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_sdffsqn.v, line:8:1, endln:24:10 |UINT:1 |vpiTypespec: \_int_typespec: @@ -55871,7 +55871,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:8:31, endln:8:37 |vpiParent: - \_module: work@oh_sdffsqn (work@oh_sdffsqn), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_sdffsqn.v, line:8:1, endln:24:10 + \_module_inst: work@oh_sdffsqn (work@oh_sdffsqn), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_sdffsqn.v, line:8:1, endln:24:10 |vpiRhs: \_constant: , line:8:36, endln:8:37 |vpiDecompile:1 @@ -55887,44 +55887,44 @@ design: (work@oh_fifo_async) |vpiNet: \_logic_net: (work@oh_sdffsqn.d), line:10:21, endln:10:22 |vpiParent: - \_module: work@oh_sdffsqn (work@oh_sdffsqn), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_sdffsqn.v, line:8:1, endln:24:10 + \_module_inst: work@oh_sdffsqn (work@oh_sdffsqn), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_sdffsqn.v, line:8:1, endln:24:10 |vpiName:d |vpiFullName:work@oh_sdffsqn.d |vpiNet: \_logic_net: (work@oh_sdffsqn.si), line:11:21, endln:11:23 |vpiParent: - \_module: work@oh_sdffsqn (work@oh_sdffsqn), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_sdffsqn.v, line:8:1, endln:24:10 + \_module_inst: work@oh_sdffsqn (work@oh_sdffsqn), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_sdffsqn.v, line:8:1, endln:24:10 |vpiName:si |vpiFullName:work@oh_sdffsqn.si |vpiNet: \_logic_net: (work@oh_sdffsqn.se), line:12:21, endln:12:23 |vpiParent: - \_module: work@oh_sdffsqn (work@oh_sdffsqn), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_sdffsqn.v, line:8:1, endln:24:10 + \_module_inst: work@oh_sdffsqn (work@oh_sdffsqn), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_sdffsqn.v, line:8:1, endln:24:10 |vpiName:se |vpiFullName:work@oh_sdffsqn.se |vpiNet: \_logic_net: (work@oh_sdffsqn.clk), line:13:21, endln:13:24 |vpiParent: - \_module: work@oh_sdffsqn (work@oh_sdffsqn), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_sdffsqn.v, line:8:1, endln:24:10 + \_module_inst: work@oh_sdffsqn (work@oh_sdffsqn), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_sdffsqn.v, line:8:1, endln:24:10 |vpiName:clk |vpiFullName:work@oh_sdffsqn.clk |vpiNet: \_logic_net: (work@oh_sdffsqn.nset), line:14:21, endln:14:25 |vpiParent: - \_module: work@oh_sdffsqn (work@oh_sdffsqn), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_sdffsqn.v, line:8:1, endln:24:10 + \_module_inst: work@oh_sdffsqn (work@oh_sdffsqn), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_sdffsqn.v, line:8:1, endln:24:10 |vpiName:nset |vpiFullName:work@oh_sdffsqn.nset |vpiNet: \_logic_net: (work@oh_sdffsqn.qn), line:15:25, endln:15:27 |vpiParent: - \_module: work@oh_sdffsqn (work@oh_sdffsqn), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_sdffsqn.v, line:8:1, endln:24:10 + \_module_inst: work@oh_sdffsqn (work@oh_sdffsqn), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_sdffsqn.v, line:8:1, endln:24:10 |vpiName:qn |vpiFullName:work@oh_sdffsqn.qn |vpiNetType:48 |vpiPort: \_port: (d), line:10:21, endln:10:22 |vpiParent: - \_module: work@oh_sdffsqn (work@oh_sdffsqn), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_sdffsqn.v, line:8:1, endln:24:10 + \_module_inst: work@oh_sdffsqn (work@oh_sdffsqn), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_sdffsqn.v, line:8:1, endln:24:10 |vpiName:d |vpiDirection:1 |vpiLowConn: @@ -55964,7 +55964,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (si), line:11:21, endln:11:23 |vpiParent: - \_module: work@oh_sdffsqn (work@oh_sdffsqn), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_sdffsqn.v, line:8:1, endln:24:10 + \_module_inst: work@oh_sdffsqn (work@oh_sdffsqn), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_sdffsqn.v, line:8:1, endln:24:10 |vpiName:si |vpiDirection:1 |vpiLowConn: @@ -56004,7 +56004,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (se), line:12:21, endln:12:23 |vpiParent: - \_module: work@oh_sdffsqn (work@oh_sdffsqn), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_sdffsqn.v, line:8:1, endln:24:10 + \_module_inst: work@oh_sdffsqn (work@oh_sdffsqn), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_sdffsqn.v, line:8:1, endln:24:10 |vpiName:se |vpiDirection:1 |vpiLowConn: @@ -56044,7 +56044,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (clk), line:13:21, endln:13:24 |vpiParent: - \_module: work@oh_sdffsqn (work@oh_sdffsqn), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_sdffsqn.v, line:8:1, endln:24:10 + \_module_inst: work@oh_sdffsqn (work@oh_sdffsqn), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_sdffsqn.v, line:8:1, endln:24:10 |vpiName:clk |vpiDirection:1 |vpiLowConn: @@ -56084,7 +56084,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (nset), line:14:21, endln:14:25 |vpiParent: - \_module: work@oh_sdffsqn (work@oh_sdffsqn), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_sdffsqn.v, line:8:1, endln:24:10 + \_module_inst: work@oh_sdffsqn (work@oh_sdffsqn), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_sdffsqn.v, line:8:1, endln:24:10 |vpiName:nset |vpiDirection:1 |vpiLowConn: @@ -56124,7 +56124,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (qn), line:15:25, endln:15:27 |vpiParent: - \_module: work@oh_sdffsqn (work@oh_sdffsqn), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_sdffsqn.v, line:8:1, endln:24:10 + \_module_inst: work@oh_sdffsqn (work@oh_sdffsqn), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_sdffsqn.v, line:8:1, endln:24:10 |vpiName:qn |vpiDirection:2 |vpiLowConn: @@ -56164,7 +56164,7 @@ design: (work@oh_fifo_async) |vpiProcess: \_always: , line:18:4, endln:22:28 |vpiParent: - \_module: work@oh_sdffsqn (work@oh_sdffsqn), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_sdffsqn.v, line:8:1, endln:24:10 + \_module_inst: work@oh_sdffsqn (work@oh_sdffsqn), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_sdffsqn.v, line:8:1, endln:24:10 |vpiStmt: \_event_control: , line:18:11, endln:18:42 |vpiParent: @@ -56269,14 +56269,14 @@ design: (work@oh_fifo_async) |vpiFullName:work@oh_sdffsqn.qn |vpiAlwaysType:1 |uhdmallModules: -\_module: work@oh_ser2par (work@oh_ser2par), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ser2par.v, line:8:1, endln:29:10 +\_module_inst: work@oh_ser2par (work@oh_ser2par), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ser2par.v, line:8:1, endln:29:10 |vpiParent: \_design: (work@oh_fifo_async) |vpiFullName:work@oh_ser2par |vpiParameter: \_parameter: (work@oh_ser2par.PW), line:8:31, endln:8:33 |vpiParent: - \_module: work@oh_ser2par (work@oh_ser2par), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ser2par.v, line:8:1, endln:29:10 + \_module_inst: work@oh_ser2par (work@oh_ser2par), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ser2par.v, line:8:1, endln:29:10 |UINT:64 |vpiTypespec: \_int_typespec: @@ -56285,7 +56285,7 @@ design: (work@oh_fifo_async) |vpiParameter: \_parameter: (work@oh_ser2par.SW), line:9:17, endln:9:19 |vpiParent: - \_module: work@oh_ser2par (work@oh_ser2par), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ser2par.v, line:8:1, endln:29:10 + \_module_inst: work@oh_ser2par (work@oh_ser2par), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ser2par.v, line:8:1, endln:29:10 |UINT:1 |vpiTypespec: \_int_typespec: @@ -56294,13 +56294,13 @@ design: (work@oh_fifo_async) |vpiParameter: \_parameter: (work@oh_ser2par.CW), line:10:17, endln:10:19 |vpiParent: - \_module: work@oh_ser2par (work@oh_ser2par), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ser2par.v, line:8:1, endln:29:10 + \_module_inst: work@oh_ser2par (work@oh_ser2par), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ser2par.v, line:8:1, endln:29:10 |vpiName:CW |vpiFullName:work@oh_ser2par.CW |vpiParamAssign: \_param_assign: , line:8:31, endln:8:38 |vpiParent: - \_module: work@oh_ser2par (work@oh_ser2par), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ser2par.v, line:8:1, endln:29:10 + \_module_inst: work@oh_ser2par (work@oh_ser2par), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ser2par.v, line:8:1, endln:29:10 |vpiRhs: \_constant: , line:8:36, endln:8:38 |vpiDecompile:64 @@ -56314,7 +56314,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:9:17, endln:9:23 |vpiParent: - \_module: work@oh_ser2par (work@oh_ser2par), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ser2par.v, line:8:1, endln:29:10 + \_module_inst: work@oh_ser2par (work@oh_ser2par), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ser2par.v, line:8:1, endln:29:10 |vpiRhs: \_constant: , line:9:22, endln:9:23 |vpiDecompile:1 @@ -56328,7 +56328,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:10:17, endln:10:35 |vpiParent: - \_module: work@oh_ser2par (work@oh_ser2par), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ser2par.v, line:8:1, endln:29:10 + \_module_inst: work@oh_ser2par (work@oh_ser2par), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ser2par.v, line:8:1, endln:29:10 |vpiRhs: \_sys_func_call: ($clog2), line:10:22, endln:10:35 |vpiArgument: @@ -56354,52 +56354,52 @@ design: (work@oh_fifo_async) |vpiNet: \_logic_net: (work@oh_ser2par.clk), line:13:13, endln:13:16 |vpiParent: - \_module: work@oh_ser2par (work@oh_ser2par), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ser2par.v, line:8:1, endln:29:10 + \_module_inst: work@oh_ser2par (work@oh_ser2par), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ser2par.v, line:8:1, endln:29:10 |vpiName:clk |vpiFullName:work@oh_ser2par.clk |vpiNet: \_logic_net: (work@oh_ser2par.din), line:14:21, endln:14:24 |vpiParent: - \_module: work@oh_ser2par (work@oh_ser2par), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ser2par.v, line:8:1, endln:29:10 + \_module_inst: work@oh_ser2par (work@oh_ser2par), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ser2par.v, line:8:1, endln:29:10 |vpiName:din |vpiFullName:work@oh_ser2par.din |vpiNet: \_logic_net: (work@oh_ser2par.dout), line:15:25, endln:15:29 |vpiParent: - \_module: work@oh_ser2par (work@oh_ser2par), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ser2par.v, line:8:1, endln:29:10 + \_module_inst: work@oh_ser2par (work@oh_ser2par), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ser2par.v, line:8:1, endln:29:10 |vpiName:dout |vpiFullName:work@oh_ser2par.dout |vpiNetType:48 |vpiNet: \_logic_net: (work@oh_ser2par.lsbfirst), line:16:13, endln:16:21 |vpiParent: - \_module: work@oh_ser2par (work@oh_ser2par), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ser2par.v, line:8:1, endln:29:10 + \_module_inst: work@oh_ser2par (work@oh_ser2par), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ser2par.v, line:8:1, endln:29:10 |vpiName:lsbfirst |vpiFullName:work@oh_ser2par.lsbfirst |vpiNet: \_logic_net: (work@oh_ser2par.shift), line:17:13, endln:17:18 |vpiParent: - \_module: work@oh_ser2par (work@oh_ser2par), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ser2par.v, line:8:1, endln:29:10 + \_module_inst: work@oh_ser2par (work@oh_ser2par), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ser2par.v, line:8:1, endln:29:10 |vpiName:shift |vpiFullName:work@oh_ser2par.shift |vpiNet: \_logic_net: (work@oh_ser2par.count), line:20:20, endln:20:25 |vpiParent: - \_module: work@oh_ser2par (work@oh_ser2par), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ser2par.v, line:8:1, endln:29:10 + \_module_inst: work@oh_ser2par (work@oh_ser2par), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ser2par.v, line:8:1, endln:29:10 |vpiName:count |vpiFullName:work@oh_ser2par.count |vpiNetType:48 |vpiNet: \_logic_net: (work@oh_ser2par.shiftdata), line:21:20, endln:21:29 |vpiParent: - \_module: work@oh_ser2par (work@oh_ser2par), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ser2par.v, line:8:1, endln:29:10 + \_module_inst: work@oh_ser2par (work@oh_ser2par), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ser2par.v, line:8:1, endln:29:10 |vpiName:shiftdata |vpiFullName:work@oh_ser2par.shiftdata |vpiNetType:1 |vpiPort: \_port: (clk), line:13:13, endln:13:16 |vpiParent: - \_module: work@oh_ser2par (work@oh_ser2par), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ser2par.v, line:8:1, endln:29:10 + \_module_inst: work@oh_ser2par (work@oh_ser2par), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ser2par.v, line:8:1, endln:29:10 |vpiName:clk |vpiDirection:1 |vpiLowConn: @@ -56411,7 +56411,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (din), line:14:21, endln:14:24 |vpiParent: - \_module: work@oh_ser2par (work@oh_ser2par), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ser2par.v, line:8:1, endln:29:10 + \_module_inst: work@oh_ser2par (work@oh_ser2par), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ser2par.v, line:8:1, endln:29:10 |vpiName:din |vpiDirection:1 |vpiLowConn: @@ -56451,7 +56451,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (dout), line:15:25, endln:15:29 |vpiParent: - \_module: work@oh_ser2par (work@oh_ser2par), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ser2par.v, line:8:1, endln:29:10 + \_module_inst: work@oh_ser2par (work@oh_ser2par), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ser2par.v, line:8:1, endln:29:10 |vpiName:dout |vpiDirection:2 |vpiLowConn: @@ -56491,7 +56491,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (lsbfirst), line:16:13, endln:16:21 |vpiParent: - \_module: work@oh_ser2par (work@oh_ser2par), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ser2par.v, line:8:1, endln:29:10 + \_module_inst: work@oh_ser2par (work@oh_ser2par), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ser2par.v, line:8:1, endln:29:10 |vpiName:lsbfirst |vpiDirection:1 |vpiLowConn: @@ -56503,7 +56503,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (shift), line:17:13, endln:17:18 |vpiParent: - \_module: work@oh_ser2par (work@oh_ser2par), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ser2par.v, line:8:1, endln:29:10 + \_module_inst: work@oh_ser2par (work@oh_ser2par), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ser2par.v, line:8:1, endln:29:10 |vpiName:shift |vpiDirection:1 |vpiLowConn: @@ -56515,7 +56515,7 @@ design: (work@oh_fifo_async) |vpiProcess: \_always: , line:23:4, endln:27:54 |vpiParent: - \_module: work@oh_ser2par (work@oh_ser2par), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ser2par.v, line:8:1, endln:29:10 + \_module_inst: work@oh_ser2par (work@oh_ser2par), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ser2par.v, line:8:1, endln:29:10 |vpiStmt: \_event_control: , line:23:11, endln:23:26 |vpiParent: @@ -56793,14 +56793,14 @@ design: (work@oh_fifo_async) |vpiConstType:9 |vpiAlwaysType:1 |uhdmallModules: -\_module: work@oh_shift (work@oh_shift), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_shift.v, line:8:1, endln:53:10 +\_module_inst: work@oh_shift (work@oh_shift), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_shift.v, line:8:1, endln:53:10 |vpiParent: \_design: (work@oh_fifo_async) |vpiFullName:work@oh_shift |vpiParameter: \_parameter: (work@oh_shift.N), line:9:15, endln:9:16 |vpiParent: - \_module: work@oh_shift (work@oh_shift), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_shift.v, line:8:1, endln:53:10 + \_module_inst: work@oh_shift (work@oh_shift), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_shift.v, line:8:1, endln:53:10 |UINT:32 |vpiTypespec: \_int_typespec: @@ -56809,13 +56809,13 @@ design: (work@oh_fifo_async) |vpiParameter: \_parameter: (work@oh_shift.S), line:10:15, endln:10:16 |vpiParent: - \_module: work@oh_shift (work@oh_shift), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_shift.v, line:8:1, endln:53:10 + \_module_inst: work@oh_shift (work@oh_shift), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_shift.v, line:8:1, endln:53:10 |vpiName:S |vpiFullName:work@oh_shift.S |vpiParameter: \_parameter: (work@oh_shift.SYN), line:11:15, endln:11:18 |vpiParent: - \_module: work@oh_shift (work@oh_shift), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_shift.v, line:8:1, endln:53:10 + \_module_inst: work@oh_shift (work@oh_shift), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_shift.v, line:8:1, endln:53:10 |STRING:TRUE |vpiTypespec: \_string_typespec: @@ -56824,7 +56824,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:9:15, endln:9:23 |vpiParent: - \_module: work@oh_shift (work@oh_shift), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_shift.v, line:8:1, endln:53:10 + \_module_inst: work@oh_shift (work@oh_shift), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_shift.v, line:8:1, endln:53:10 |vpiRhs: \_constant: , line:9:21, endln:9:23 |vpiDecompile:32 @@ -56838,7 +56838,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:10:15, endln:10:31 |vpiParent: - \_module: work@oh_shift (work@oh_shift), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_shift.v, line:8:1, endln:53:10 + \_module_inst: work@oh_shift (work@oh_shift), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_shift.v, line:8:1, endln:53:10 |vpiRhs: \_sys_func_call: ($clog2), line:10:22, endln:10:31 |vpiArgument: @@ -56852,7 +56852,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:11:15, endln:11:27 |vpiParent: - \_module: work@oh_shift (work@oh_shift), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_shift.v, line:8:1, endln:53:10 + \_module_inst: work@oh_shift (work@oh_shift), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_shift.v, line:8:1, endln:53:10 |vpiRhs: \_constant: , line:11:21, endln:11:27 |vpiDecompile:TRUE @@ -56868,37 +56868,37 @@ design: (work@oh_fifo_async) |vpiNet: \_logic_net: (work@oh_shift.in), line:14:20, endln:14:22 |vpiParent: - \_module: work@oh_shift (work@oh_shift), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_shift.v, line:8:1, endln:53:10 + \_module_inst: work@oh_shift (work@oh_shift), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_shift.v, line:8:1, endln:53:10 |vpiName:in |vpiFullName:work@oh_shift.in |vpiNet: \_logic_net: (work@oh_shift.arithmetic), line:15:16, endln:15:26 |vpiParent: - \_module: work@oh_shift (work@oh_shift), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_shift.v, line:8:1, endln:53:10 + \_module_inst: work@oh_shift (work@oh_shift), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_shift.v, line:8:1, endln:53:10 |vpiName:arithmetic |vpiFullName:work@oh_shift.arithmetic |vpiNet: \_logic_net: (work@oh_shift.right), line:16:16, endln:16:21 |vpiParent: - \_module: work@oh_shift (work@oh_shift), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_shift.v, line:8:1, endln:53:10 + \_module_inst: work@oh_shift (work@oh_shift), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_shift.v, line:8:1, endln:53:10 |vpiName:right |vpiFullName:work@oh_shift.right |vpiNet: \_logic_net: (work@oh_shift.shamt), line:17:21, endln:17:26 |vpiParent: - \_module: work@oh_shift (work@oh_shift), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_shift.v, line:8:1, endln:53:10 + \_module_inst: work@oh_shift (work@oh_shift), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_shift.v, line:8:1, endln:53:10 |vpiName:shamt |vpiFullName:work@oh_shift.shamt |vpiNet: \_logic_net: (work@oh_shift.out), line:18:20, endln:18:23 |vpiParent: - \_module: work@oh_shift (work@oh_shift), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_shift.v, line:8:1, endln:53:10 + \_module_inst: work@oh_shift (work@oh_shift), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_shift.v, line:8:1, endln:53:10 |vpiName:out |vpiFullName:work@oh_shift.out |vpiPort: \_port: (in), line:14:20, endln:14:22 |vpiParent: - \_module: work@oh_shift (work@oh_shift), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_shift.v, line:8:1, endln:53:10 + \_module_inst: work@oh_shift (work@oh_shift), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_shift.v, line:8:1, endln:53:10 |vpiName:in |vpiDirection:1 |vpiLowConn: @@ -56938,7 +56938,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (arithmetic), line:15:16, endln:15:26 |vpiParent: - \_module: work@oh_shift (work@oh_shift), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_shift.v, line:8:1, endln:53:10 + \_module_inst: work@oh_shift (work@oh_shift), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_shift.v, line:8:1, endln:53:10 |vpiName:arithmetic |vpiDirection:1 |vpiLowConn: @@ -56950,7 +56950,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (right), line:16:16, endln:16:21 |vpiParent: - \_module: work@oh_shift (work@oh_shift), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_shift.v, line:8:1, endln:53:10 + \_module_inst: work@oh_shift (work@oh_shift), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_shift.v, line:8:1, endln:53:10 |vpiName:right |vpiDirection:1 |vpiLowConn: @@ -56962,7 +56962,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (shamt), line:17:21, endln:17:26 |vpiParent: - \_module: work@oh_shift (work@oh_shift), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_shift.v, line:8:1, endln:53:10 + \_module_inst: work@oh_shift (work@oh_shift), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_shift.v, line:8:1, endln:53:10 |vpiName:shamt |vpiDirection:1 |vpiLowConn: @@ -57002,7 +57002,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (out), line:18:20, endln:18:23 |vpiParent: - \_module: work@oh_shift (work@oh_shift), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_shift.v, line:8:1, endln:53:10 + \_module_inst: work@oh_shift (work@oh_shift), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_shift.v, line:8:1, endln:53:10 |vpiName:out |vpiDirection:2 |vpiLowConn: @@ -57040,14 +57040,14 @@ design: (work@oh_fifo_async) |UINT:0 |vpiConstType:9 |uhdmallModules: -\_module: work@oh_standby (work@oh_standby), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_standby.v, line:8:1, endln:96:10 +\_module_inst: work@oh_standby (work@oh_standby), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_standby.v, line:8:1, endln:96:10 |vpiParent: \_design: (work@oh_fifo_async) |vpiFullName:work@oh_standby |vpiParameter: \_parameter: (work@oh_standby.PD), line:9:15, endln:9:17 |vpiParent: - \_module: work@oh_standby (work@oh_standby), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_standby.v, line:8:1, endln:96:10 + \_module_inst: work@oh_standby (work@oh_standby), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_standby.v, line:8:1, endln:96:10 |UINT:5 |vpiTypespec: \_int_typespec: @@ -57056,7 +57056,7 @@ design: (work@oh_fifo_async) |vpiParameter: \_parameter: (work@oh_standby.SYNCPIPE), line:10:15, endln:10:23 |vpiParent: - \_module: work@oh_standby (work@oh_standby), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_standby.v, line:8:1, endln:96:10 + \_module_inst: work@oh_standby (work@oh_standby), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_standby.v, line:8:1, endln:96:10 |UINT:2 |vpiTypespec: \_int_typespec: @@ -57065,7 +57065,7 @@ design: (work@oh_fifo_async) |vpiParameter: \_parameter: (work@oh_standby.SYN), line:11:15, endln:11:18 |vpiParent: - \_module: work@oh_standby (work@oh_standby), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_standby.v, line:8:1, endln:96:10 + \_module_inst: work@oh_standby (work@oh_standby), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_standby.v, line:8:1, endln:96:10 |STRING:TRUE |vpiTypespec: \_string_typespec: @@ -57074,7 +57074,7 @@ design: (work@oh_fifo_async) |vpiParameter: \_parameter: (work@oh_standby.DELAY), line:12:15, endln:12:20 |vpiParent: - \_module: work@oh_standby (work@oh_standby), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_standby.v, line:8:1, endln:96:10 + \_module_inst: work@oh_standby (work@oh_standby), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_standby.v, line:8:1, endln:96:10 |UINT:5 |vpiTypespec: \_int_typespec: @@ -57083,7 +57083,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:9:15, endln:9:27 |vpiParent: - \_module: work@oh_standby (work@oh_standby), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_standby.v, line:8:1, endln:96:10 + \_module_inst: work@oh_standby (work@oh_standby), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_standby.v, line:8:1, endln:96:10 |vpiRhs: \_constant: , line:9:26, endln:9:27 |vpiDecompile:5 @@ -57097,7 +57097,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:10:15, endln:10:27 |vpiParent: - \_module: work@oh_standby (work@oh_standby), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_standby.v, line:8:1, endln:96:10 + \_module_inst: work@oh_standby (work@oh_standby), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_standby.v, line:8:1, endln:96:10 |vpiRhs: \_constant: , line:10:26, endln:10:27 |vpiDecompile:2 @@ -57111,7 +57111,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:11:15, endln:11:32 |vpiParent: - \_module: work@oh_standby (work@oh_standby), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_standby.v, line:8:1, endln:96:10 + \_module_inst: work@oh_standby (work@oh_standby), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_standby.v, line:8:1, endln:96:10 |vpiRhs: \_constant: , line:11:26, endln:11:32 |vpiDecompile:TRUE @@ -57125,7 +57125,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:12:15, endln:12:27 |vpiParent: - \_module: work@oh_standby (work@oh_standby), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_standby.v, line:8:1, endln:96:10 + \_module_inst: work@oh_standby (work@oh_standby), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_standby.v, line:8:1, endln:96:10 |vpiRhs: \_constant: , line:12:26, endln:12:27 |vpiDecompile:5 @@ -57141,91 +57141,91 @@ design: (work@oh_fifo_async) |vpiNet: \_logic_net: (work@oh_standby.clkin), line:15:12, endln:15:17 |vpiParent: - \_module: work@oh_standby (work@oh_standby), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_standby.v, line:8:1, endln:96:10 + \_module_inst: work@oh_standby (work@oh_standby), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_standby.v, line:8:1, endln:96:10 |vpiName:clkin |vpiFullName:work@oh_standby.clkin |vpiNet: \_logic_net: (work@oh_standby.nreset), line:16:12, endln:16:18 |vpiParent: - \_module: work@oh_standby (work@oh_standby), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_standby.v, line:8:1, endln:96:10 + \_module_inst: work@oh_standby (work@oh_standby), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_standby.v, line:8:1, endln:96:10 |vpiName:nreset |vpiFullName:work@oh_standby.nreset |vpiNet: \_logic_net: (work@oh_standby.testenable), line:17:12, endln:17:22 |vpiParent: - \_module: work@oh_standby (work@oh_standby), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_standby.v, line:8:1, endln:96:10 + \_module_inst: work@oh_standby (work@oh_standby), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_standby.v, line:8:1, endln:96:10 |vpiName:testenable |vpiFullName:work@oh_standby.testenable |vpiNet: \_logic_net: (work@oh_standby.wakeup), line:18:12, endln:18:18 |vpiParent: - \_module: work@oh_standby (work@oh_standby), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_standby.v, line:8:1, endln:96:10 + \_module_inst: work@oh_standby (work@oh_standby), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_standby.v, line:8:1, endln:96:10 |vpiName:wakeup |vpiFullName:work@oh_standby.wakeup |vpiNet: \_logic_net: (work@oh_standby.idle), line:19:12, endln:19:16 |vpiParent: - \_module: work@oh_standby (work@oh_standby), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_standby.v, line:8:1, endln:96:10 + \_module_inst: work@oh_standby (work@oh_standby), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_standby.v, line:8:1, endln:96:10 |vpiName:idle |vpiFullName:work@oh_standby.idle |vpiNet: \_logic_net: (work@oh_standby.resetout), line:21:12, endln:21:20 |vpiParent: - \_module: work@oh_standby (work@oh_standby), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_standby.v, line:8:1, endln:96:10 + \_module_inst: work@oh_standby (work@oh_standby), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_standby.v, line:8:1, endln:96:10 |vpiName:resetout |vpiFullName:work@oh_standby.resetout |vpiNet: \_logic_net: (work@oh_standby.clkout), line:22:12, endln:22:18 |vpiParent: - \_module: work@oh_standby (work@oh_standby), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_standby.v, line:8:1, endln:96:10 + \_module_inst: work@oh_standby (work@oh_standby), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_standby.v, line:8:1, endln:96:10 |vpiName:clkout |vpiFullName:work@oh_standby.clkout |vpiNet: \_logic_net: (work@oh_standby.wakeup_pipe), line:26:29, endln:26:40 |vpiParent: - \_module: work@oh_standby (work@oh_standby), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_standby.v, line:8:1, endln:96:10 + \_module_inst: work@oh_standby (work@oh_standby), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_standby.v, line:8:1, endln:96:10 |vpiName:wakeup_pipe |vpiFullName:work@oh_standby.wakeup_pipe |vpiNetType:48 |vpiNet: \_logic_net: (work@oh_standby.sync_reset), line:27:15, endln:27:25 |vpiParent: - \_module: work@oh_standby (work@oh_standby), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_standby.v, line:8:1, endln:96:10 + \_module_inst: work@oh_standby (work@oh_standby), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_standby.v, line:8:1, endln:96:10 |vpiName:sync_reset |vpiFullName:work@oh_standby.sync_reset |vpiNetType:1 |vpiNet: \_logic_net: (work@oh_standby.sync_reset_pulse), line:28:15, endln:28:31 |vpiParent: - \_module: work@oh_standby (work@oh_standby), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_standby.v, line:8:1, endln:96:10 + \_module_inst: work@oh_standby (work@oh_standby), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_standby.v, line:8:1, endln:96:10 |vpiName:sync_reset_pulse |vpiFullName:work@oh_standby.sync_reset_pulse |vpiNetType:1 |vpiNet: \_logic_net: (work@oh_standby.wakeup_now), line:29:15, endln:29:25 |vpiParent: - \_module: work@oh_standby (work@oh_standby), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_standby.v, line:8:1, endln:96:10 + \_module_inst: work@oh_standby (work@oh_standby), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_standby.v, line:8:1, endln:96:10 |vpiName:wakeup_now |vpiFullName:work@oh_standby.wakeup_now |vpiNetType:1 |vpiNet: \_logic_net: (work@oh_standby.clk_en), line:30:15, endln:30:21 |vpiParent: - \_module: work@oh_standby (work@oh_standby), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_standby.v, line:8:1, endln:96:10 + \_module_inst: work@oh_standby (work@oh_standby), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_standby.v, line:8:1, endln:96:10 |vpiName:clk_en |vpiFullName:work@oh_standby.clk_en |vpiNetType:1 |vpiNet: \_logic_net: (work@oh_standby.delay_sel), line:31:29, endln:31:38 |vpiParent: - \_module: work@oh_standby (work@oh_standby), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_standby.v, line:8:1, endln:96:10 + \_module_inst: work@oh_standby (work@oh_standby), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_standby.v, line:8:1, endln:96:10 |vpiName:delay_sel |vpiFullName:work@oh_standby.delay_sel |vpiNetType:1 |vpiPort: \_port: (clkin), line:15:12, endln:15:17 |vpiParent: - \_module: work@oh_standby (work@oh_standby), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_standby.v, line:8:1, endln:96:10 + \_module_inst: work@oh_standby (work@oh_standby), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_standby.v, line:8:1, endln:96:10 |vpiName:clkin |vpiDirection:1 |vpiLowConn: @@ -57237,7 +57237,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (nreset), line:16:12, endln:16:18 |vpiParent: - \_module: work@oh_standby (work@oh_standby), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_standby.v, line:8:1, endln:96:10 + \_module_inst: work@oh_standby (work@oh_standby), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_standby.v, line:8:1, endln:96:10 |vpiName:nreset |vpiDirection:1 |vpiLowConn: @@ -57249,7 +57249,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (testenable), line:17:12, endln:17:22 |vpiParent: - \_module: work@oh_standby (work@oh_standby), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_standby.v, line:8:1, endln:96:10 + \_module_inst: work@oh_standby (work@oh_standby), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_standby.v, line:8:1, endln:96:10 |vpiName:testenable |vpiDirection:1 |vpiLowConn: @@ -57261,7 +57261,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (wakeup), line:18:12, endln:18:18 |vpiParent: - \_module: work@oh_standby (work@oh_standby), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_standby.v, line:8:1, endln:96:10 + \_module_inst: work@oh_standby (work@oh_standby), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_standby.v, line:8:1, endln:96:10 |vpiName:wakeup |vpiDirection:1 |vpiLowConn: @@ -57273,7 +57273,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (idle), line:19:12, endln:19:16 |vpiParent: - \_module: work@oh_standby (work@oh_standby), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_standby.v, line:8:1, endln:96:10 + \_module_inst: work@oh_standby (work@oh_standby), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_standby.v, line:8:1, endln:96:10 |vpiName:idle |vpiDirection:1 |vpiLowConn: @@ -57285,7 +57285,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (resetout), line:21:12, endln:21:20 |vpiParent: - \_module: work@oh_standby (work@oh_standby), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_standby.v, line:8:1, endln:96:10 + \_module_inst: work@oh_standby (work@oh_standby), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_standby.v, line:8:1, endln:96:10 |vpiName:resetout |vpiDirection:2 |vpiLowConn: @@ -57297,7 +57297,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (clkout), line:22:12, endln:22:18 |vpiParent: - \_module: work@oh_standby (work@oh_standby), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_standby.v, line:8:1, endln:96:10 + \_module_inst: work@oh_standby (work@oh_standby), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_standby.v, line:8:1, endln:96:10 |vpiName:clkout |vpiDirection:2 |vpiLowConn: @@ -57309,7 +57309,7 @@ design: (work@oh_fifo_async) |vpiProcess: \_always: , line:79:4, endln:83:65 |vpiParent: - \_module: work@oh_standby (work@oh_standby), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_standby.v, line:8:1, endln:96:10 + \_module_inst: work@oh_standby (work@oh_standby), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_standby.v, line:8:1, endln:96:10 |vpiStmt: \_event_control: , line:79:11, endln:79:46 |vpiParent: @@ -57484,7 +57484,7 @@ design: (work@oh_fifo_async) |vpiContAssign: \_cont_assign: , line:60:11, endln:60:28 |vpiParent: - \_module: work@oh_standby (work@oh_standby), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_standby.v, line:8:1, endln:96:10 + \_module_inst: work@oh_standby (work@oh_standby), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_standby.v, line:8:1, endln:96:10 |vpiRhs: \_ref_obj: (work@oh_standby.DELAY), line:60:23, endln:60:28 |vpiParent: @@ -57500,7 +57500,7 @@ design: (work@oh_fifo_async) |vpiContAssign: \_cont_assign: , line:76:11, endln:76:49 |vpiParent: - \_module: work@oh_standby (work@oh_standby), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_standby.v, line:8:1, endln:96:10 + \_module_inst: work@oh_standby (work@oh_standby), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_standby.v, line:8:1, endln:96:10 |vpiRhs: \_operation: , line:76:24, endln:76:49 |vpiParent: @@ -57527,7 +57527,7 @@ design: (work@oh_fifo_async) |vpiContAssign: \_cont_assign: , line:86:12, endln:88:16 |vpiParent: - \_module: work@oh_standby (work@oh_standby), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_standby.v, line:8:1, endln:96:10 + \_module_inst: work@oh_standby (work@oh_standby), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_standby.v, line:8:1, endln:96:10 |vpiRhs: \_operation: , line:86:25, endln:88:16 |vpiParent: @@ -57599,14 +57599,14 @@ design: (work@oh_fifo_async) |vpiName:clk_en |vpiFullName:work@oh_standby.clk_en |uhdmallModules: -\_module: work@oh_stretcher (work@oh_stretcher), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_stretcher.v, line:9:1, endln:28:10 +\_module_inst: work@oh_stretcher (work@oh_stretcher), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_stretcher.v, line:9:1, endln:28:10 |vpiParent: \_design: (work@oh_fifo_async) |vpiFullName:work@oh_stretcher |vpiParameter: \_parameter: (work@oh_stretcher.CYCLES), line:9:33, endln:9:39 |vpiParent: - \_module: work@oh_stretcher (work@oh_stretcher), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_stretcher.v, line:9:1, endln:28:10 + \_module_inst: work@oh_stretcher (work@oh_stretcher), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_stretcher.v, line:9:1, endln:28:10 |UINT:5 |vpiTypespec: \_int_typespec: @@ -57615,7 +57615,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:9:33, endln:9:43 |vpiParent: - \_module: work@oh_stretcher (work@oh_stretcher), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_stretcher.v, line:9:1, endln:28:10 + \_module_inst: work@oh_stretcher (work@oh_stretcher), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_stretcher.v, line:9:1, endln:28:10 |vpiRhs: \_constant: , line:9:42, endln:9:43 |vpiDecompile:5 @@ -57631,38 +57631,38 @@ design: (work@oh_fifo_async) |vpiNet: \_logic_net: (work@oh_stretcher.clk), line:10:13, endln:10:16 |vpiParent: - \_module: work@oh_stretcher (work@oh_stretcher), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_stretcher.v, line:9:1, endln:28:10 + \_module_inst: work@oh_stretcher (work@oh_stretcher), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_stretcher.v, line:9:1, endln:28:10 |vpiName:clk |vpiFullName:work@oh_stretcher.clk |vpiNet: \_logic_net: (work@oh_stretcher.in), line:11:13, endln:11:15 |vpiParent: - \_module: work@oh_stretcher (work@oh_stretcher), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_stretcher.v, line:9:1, endln:28:10 + \_module_inst: work@oh_stretcher (work@oh_stretcher), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_stretcher.v, line:9:1, endln:28:10 |vpiName:in |vpiFullName:work@oh_stretcher.in |vpiNet: \_logic_net: (work@oh_stretcher.nreset), line:12:13, endln:12:19 |vpiParent: - \_module: work@oh_stretcher (work@oh_stretcher), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_stretcher.v, line:9:1, endln:28:10 + \_module_inst: work@oh_stretcher (work@oh_stretcher), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_stretcher.v, line:9:1, endln:28:10 |vpiName:nreset |vpiFullName:work@oh_stretcher.nreset |vpiNet: \_logic_net: (work@oh_stretcher.out), line:13:13, endln:13:16 |vpiParent: - \_module: work@oh_stretcher (work@oh_stretcher), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_stretcher.v, line:9:1, endln:28:10 + \_module_inst: work@oh_stretcher (work@oh_stretcher), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_stretcher.v, line:9:1, endln:28:10 |vpiName:out |vpiFullName:work@oh_stretcher.out |vpiNet: \_logic_net: (work@oh_stretcher.valid), line:16:21, endln:16:26 |vpiParent: - \_module: work@oh_stretcher (work@oh_stretcher), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_stretcher.v, line:9:1, endln:28:10 + \_module_inst: work@oh_stretcher (work@oh_stretcher), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_stretcher.v, line:9:1, endln:28:10 |vpiName:valid |vpiFullName:work@oh_stretcher.valid |vpiNetType:48 |vpiPort: \_port: (clk), line:10:13, endln:10:16 |vpiParent: - \_module: work@oh_stretcher (work@oh_stretcher), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_stretcher.v, line:9:1, endln:28:10 + \_module_inst: work@oh_stretcher (work@oh_stretcher), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_stretcher.v, line:9:1, endln:28:10 |vpiName:clk |vpiDirection:1 |vpiLowConn: @@ -57674,7 +57674,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (in), line:11:13, endln:11:15 |vpiParent: - \_module: work@oh_stretcher (work@oh_stretcher), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_stretcher.v, line:9:1, endln:28:10 + \_module_inst: work@oh_stretcher (work@oh_stretcher), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_stretcher.v, line:9:1, endln:28:10 |vpiName:in |vpiDirection:1 |vpiLowConn: @@ -57686,7 +57686,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (nreset), line:12:13, endln:12:19 |vpiParent: - \_module: work@oh_stretcher (work@oh_stretcher), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_stretcher.v, line:9:1, endln:28:10 + \_module_inst: work@oh_stretcher (work@oh_stretcher), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_stretcher.v, line:9:1, endln:28:10 |vpiName:nreset |vpiDirection:1 |vpiLowConn: @@ -57698,7 +57698,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (out), line:13:13, endln:13:16 |vpiParent: - \_module: work@oh_stretcher (work@oh_stretcher), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_stretcher.v, line:9:1, endln:28:10 + \_module_inst: work@oh_stretcher (work@oh_stretcher), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_stretcher.v, line:9:1, endln:28:10 |vpiName:out |vpiDirection:2 |vpiLowConn: @@ -57710,7 +57710,7 @@ design: (work@oh_fifo_async) |vpiProcess: \_always: , line:18:4, endln:24:53 |vpiParent: - \_module: work@oh_stretcher (work@oh_stretcher), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_stretcher.v, line:9:1, endln:28:10 + \_module_inst: work@oh_stretcher (work@oh_stretcher), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_stretcher.v, line:9:1, endln:28:10 |vpiStmt: \_event_control: , line:18:11, endln:18:44 |vpiParent: @@ -57959,7 +57959,7 @@ design: (work@oh_fifo_async) |vpiContAssign: \_cont_assign: , line:26:11, endln:26:32 |vpiParent: - \_module: work@oh_stretcher (work@oh_stretcher), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_stretcher.v, line:9:1, endln:28:10 + \_module_inst: work@oh_stretcher (work@oh_stretcher), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_stretcher.v, line:9:1, endln:28:10 |vpiRhs: \_bit_select: (work@oh_stretcher.valid), line:26:17, endln:26:32 |vpiParent: @@ -57996,14 +57996,14 @@ design: (work@oh_fifo_async) |vpiName:out |vpiFullName:work@oh_stretcher.out |uhdmallModules: -\_module: work@oh_tristate (work@oh_tristate), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_tristate.v, line:8:1, endln:36:10 +\_module_inst: work@oh_tristate (work@oh_tristate), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_tristate.v, line:8:1, endln:36:10 |vpiParent: \_design: (work@oh_fifo_async) |vpiFullName:work@oh_tristate |vpiParameter: \_parameter: (work@oh_tristate.N), line:9:15, endln:9:16 |vpiParent: - \_module: work@oh_tristate (work@oh_tristate), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_tristate.v, line:8:1, endln:36:10 + \_module_inst: work@oh_tristate (work@oh_tristate), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_tristate.v, line:8:1, endln:36:10 |UINT:1 |vpiTypespec: \_int_typespec: @@ -58012,7 +58012,7 @@ design: (work@oh_fifo_async) |vpiParameter: \_parameter: (work@oh_tristate.SYN), line:10:15, endln:10:18 |vpiParent: - \_module: work@oh_tristate (work@oh_tristate), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_tristate.v, line:8:1, endln:36:10 + \_module_inst: work@oh_tristate (work@oh_tristate), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_tristate.v, line:8:1, endln:36:10 |STRING:TRUE |vpiTypespec: \_string_typespec: @@ -58021,7 +58021,7 @@ design: (work@oh_fifo_async) |vpiParameter: \_parameter: (work@oh_tristate.TYPE), line:11:15, endln:11:19 |vpiParent: - \_module: work@oh_tristate (work@oh_tristate), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_tristate.v, line:8:1, endln:36:10 + \_module_inst: work@oh_tristate (work@oh_tristate), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_tristate.v, line:8:1, endln:36:10 |STRING:DEFAULT |vpiTypespec: \_string_typespec: @@ -58030,7 +58030,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:9:15, endln:9:23 |vpiParent: - \_module: work@oh_tristate (work@oh_tristate), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_tristate.v, line:8:1, endln:36:10 + \_module_inst: work@oh_tristate (work@oh_tristate), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_tristate.v, line:8:1, endln:36:10 |vpiRhs: \_constant: , line:9:22, endln:9:23 |vpiDecompile:1 @@ -58044,7 +58044,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:10:15, endln:10:28 |vpiParent: - \_module: work@oh_tristate (work@oh_tristate), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_tristate.v, line:8:1, endln:36:10 + \_module_inst: work@oh_tristate (work@oh_tristate), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_tristate.v, line:8:1, endln:36:10 |vpiRhs: \_constant: , line:10:22, endln:10:28 |vpiDecompile:TRUE @@ -58058,7 +58058,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:11:15, endln:11:31 |vpiParent: - \_module: work@oh_tristate (work@oh_tristate), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_tristate.v, line:8:1, endln:36:10 + \_module_inst: work@oh_tristate (work@oh_tristate), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_tristate.v, line:8:1, endln:36:10 |vpiRhs: \_constant: , line:11:22, endln:11:31 |vpiDecompile:DEFAULT @@ -58074,25 +58074,25 @@ design: (work@oh_fifo_async) |vpiNet: \_logic_net: (work@oh_tristate.in), line:14:20, endln:14:22 |vpiParent: - \_module: work@oh_tristate (work@oh_tristate), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_tristate.v, line:8:1, endln:36:10 + \_module_inst: work@oh_tristate (work@oh_tristate), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_tristate.v, line:8:1, endln:36:10 |vpiName:in |vpiFullName:work@oh_tristate.in |vpiNet: \_logic_net: (work@oh_tristate.oe), line:15:20, endln:15:22 |vpiParent: - \_module: work@oh_tristate (work@oh_tristate), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_tristate.v, line:8:1, endln:36:10 + \_module_inst: work@oh_tristate (work@oh_tristate), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_tristate.v, line:8:1, endln:36:10 |vpiName:oe |vpiFullName:work@oh_tristate.oe |vpiNet: \_logic_net: (work@oh_tristate.out), line:16:20, endln:16:23 |vpiParent: - \_module: work@oh_tristate (work@oh_tristate), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_tristate.v, line:8:1, endln:36:10 + \_module_inst: work@oh_tristate (work@oh_tristate), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_tristate.v, line:8:1, endln:36:10 |vpiName:out |vpiFullName:work@oh_tristate.out |vpiPort: \_port: (in), line:14:20, endln:14:22 |vpiParent: - \_module: work@oh_tristate (work@oh_tristate), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_tristate.v, line:8:1, endln:36:10 + \_module_inst: work@oh_tristate (work@oh_tristate), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_tristate.v, line:8:1, endln:36:10 |vpiName:in |vpiDirection:1 |vpiLowConn: @@ -58132,7 +58132,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (oe), line:15:20, endln:15:22 |vpiParent: - \_module: work@oh_tristate (work@oh_tristate), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_tristate.v, line:8:1, endln:36:10 + \_module_inst: work@oh_tristate (work@oh_tristate), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_tristate.v, line:8:1, endln:36:10 |vpiName:oe |vpiDirection:1 |vpiLowConn: @@ -58172,7 +58172,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (out), line:16:20, endln:16:23 |vpiParent: - \_module: work@oh_tristate (work@oh_tristate), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_tristate.v, line:8:1, endln:36:10 + \_module_inst: work@oh_tristate (work@oh_tristate), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_tristate.v, line:8:1, endln:36:10 |vpiName:out |vpiDirection:2 |vpiLowConn: @@ -58210,14 +58210,14 @@ design: (work@oh_fifo_async) |UINT:0 |vpiConstType:9 |uhdmallModules: -\_module: work@oh_xnor2 (work@oh_xnor2), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_xnor2.v, line:7:1, endln:16:10 +\_module_inst: work@oh_xnor2 (work@oh_xnor2), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_xnor2.v, line:7:1, endln:16:10 |vpiParent: \_design: (work@oh_fifo_async) |vpiFullName:work@oh_xnor2 |vpiParameter: \_parameter: (work@oh_xnor2.DW), line:7:29, endln:7:31 |vpiParent: - \_module: work@oh_xnor2 (work@oh_xnor2), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_xnor2.v, line:7:1, endln:16:10 + \_module_inst: work@oh_xnor2 (work@oh_xnor2), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_xnor2.v, line:7:1, endln:16:10 |UINT:1 |vpiTypespec: \_int_typespec: @@ -58226,7 +58226,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:7:29, endln:7:35 |vpiParent: - \_module: work@oh_xnor2 (work@oh_xnor2), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_xnor2.v, line:7:1, endln:16:10 + \_module_inst: work@oh_xnor2 (work@oh_xnor2), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_xnor2.v, line:7:1, endln:16:10 |vpiRhs: \_constant: , line:7:34, endln:7:35 |vpiDecompile:1 @@ -58242,25 +58242,25 @@ design: (work@oh_fifo_async) |vpiNet: \_logic_net: (work@oh_xnor2.a), line:9:21, endln:9:22 |vpiParent: - \_module: work@oh_xnor2 (work@oh_xnor2), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_xnor2.v, line:7:1, endln:16:10 + \_module_inst: work@oh_xnor2 (work@oh_xnor2), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_xnor2.v, line:7:1, endln:16:10 |vpiName:a |vpiFullName:work@oh_xnor2.a |vpiNet: \_logic_net: (work@oh_xnor2.b), line:10:21, endln:10:22 |vpiParent: - \_module: work@oh_xnor2 (work@oh_xnor2), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_xnor2.v, line:7:1, endln:16:10 + \_module_inst: work@oh_xnor2 (work@oh_xnor2), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_xnor2.v, line:7:1, endln:16:10 |vpiName:b |vpiFullName:work@oh_xnor2.b |vpiNet: \_logic_net: (work@oh_xnor2.z), line:11:21, endln:11:22 |vpiParent: - \_module: work@oh_xnor2 (work@oh_xnor2), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_xnor2.v, line:7:1, endln:16:10 + \_module_inst: work@oh_xnor2 (work@oh_xnor2), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_xnor2.v, line:7:1, endln:16:10 |vpiName:z |vpiFullName:work@oh_xnor2.z |vpiPort: \_port: (a), line:9:21, endln:9:22 |vpiParent: - \_module: work@oh_xnor2 (work@oh_xnor2), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_xnor2.v, line:7:1, endln:16:10 + \_module_inst: work@oh_xnor2 (work@oh_xnor2), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_xnor2.v, line:7:1, endln:16:10 |vpiName:a |vpiDirection:1 |vpiLowConn: @@ -58300,7 +58300,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (b), line:10:21, endln:10:22 |vpiParent: - \_module: work@oh_xnor2 (work@oh_xnor2), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_xnor2.v, line:7:1, endln:16:10 + \_module_inst: work@oh_xnor2 (work@oh_xnor2), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_xnor2.v, line:7:1, endln:16:10 |vpiName:b |vpiDirection:1 |vpiLowConn: @@ -58340,7 +58340,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (z), line:11:21, endln:11:22 |vpiParent: - \_module: work@oh_xnor2 (work@oh_xnor2), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_xnor2.v, line:7:1, endln:16:10 + \_module_inst: work@oh_xnor2 (work@oh_xnor2), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_xnor2.v, line:7:1, endln:16:10 |vpiName:z |vpiDirection:2 |vpiLowConn: @@ -58380,7 +58380,7 @@ design: (work@oh_fifo_async) |vpiContAssign: \_cont_assign: , line:14:11, endln:14:24 |vpiParent: - \_module: work@oh_xnor2 (work@oh_xnor2), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_xnor2.v, line:7:1, endln:16:10 + \_module_inst: work@oh_xnor2 (work@oh_xnor2), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_xnor2.v, line:7:1, endln:16:10 |vpiRhs: \_operation: , line:14:16, endln:14:24 |vpiParent: @@ -58410,14 +58410,14 @@ design: (work@oh_fifo_async) |vpiName:z |vpiFullName:work@oh_xnor2.z |uhdmallModules: -\_module: work@oh_xnor3 (work@oh_xnor3), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_xnor3.v, line:7:1, endln:17:10 +\_module_inst: work@oh_xnor3 (work@oh_xnor3), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_xnor3.v, line:7:1, endln:17:10 |vpiParent: \_design: (work@oh_fifo_async) |vpiFullName:work@oh_xnor3 |vpiParameter: \_parameter: (work@oh_xnor3.DW), line:7:29, endln:7:31 |vpiParent: - \_module: work@oh_xnor3 (work@oh_xnor3), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_xnor3.v, line:7:1, endln:17:10 + \_module_inst: work@oh_xnor3 (work@oh_xnor3), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_xnor3.v, line:7:1, endln:17:10 |UINT:1 |vpiTypespec: \_int_typespec: @@ -58426,7 +58426,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:7:29, endln:7:35 |vpiParent: - \_module: work@oh_xnor3 (work@oh_xnor3), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_xnor3.v, line:7:1, endln:17:10 + \_module_inst: work@oh_xnor3 (work@oh_xnor3), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_xnor3.v, line:7:1, endln:17:10 |vpiRhs: \_constant: , line:7:34, endln:7:35 |vpiDecompile:1 @@ -58442,31 +58442,31 @@ design: (work@oh_fifo_async) |vpiNet: \_logic_net: (work@oh_xnor3.a), line:9:21, endln:9:22 |vpiParent: - \_module: work@oh_xnor3 (work@oh_xnor3), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_xnor3.v, line:7:1, endln:17:10 + \_module_inst: work@oh_xnor3 (work@oh_xnor3), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_xnor3.v, line:7:1, endln:17:10 |vpiName:a |vpiFullName:work@oh_xnor3.a |vpiNet: \_logic_net: (work@oh_xnor3.b), line:10:21, endln:10:22 |vpiParent: - \_module: work@oh_xnor3 (work@oh_xnor3), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_xnor3.v, line:7:1, endln:17:10 + \_module_inst: work@oh_xnor3 (work@oh_xnor3), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_xnor3.v, line:7:1, endln:17:10 |vpiName:b |vpiFullName:work@oh_xnor3.b |vpiNet: \_logic_net: (work@oh_xnor3.c), line:11:21, endln:11:22 |vpiParent: - \_module: work@oh_xnor3 (work@oh_xnor3), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_xnor3.v, line:7:1, endln:17:10 + \_module_inst: work@oh_xnor3 (work@oh_xnor3), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_xnor3.v, line:7:1, endln:17:10 |vpiName:c |vpiFullName:work@oh_xnor3.c |vpiNet: \_logic_net: (work@oh_xnor3.z), line:12:21, endln:12:22 |vpiParent: - \_module: work@oh_xnor3 (work@oh_xnor3), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_xnor3.v, line:7:1, endln:17:10 + \_module_inst: work@oh_xnor3 (work@oh_xnor3), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_xnor3.v, line:7:1, endln:17:10 |vpiName:z |vpiFullName:work@oh_xnor3.z |vpiPort: \_port: (a), line:9:21, endln:9:22 |vpiParent: - \_module: work@oh_xnor3 (work@oh_xnor3), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_xnor3.v, line:7:1, endln:17:10 + \_module_inst: work@oh_xnor3 (work@oh_xnor3), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_xnor3.v, line:7:1, endln:17:10 |vpiName:a |vpiDirection:1 |vpiLowConn: @@ -58506,7 +58506,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (b), line:10:21, endln:10:22 |vpiParent: - \_module: work@oh_xnor3 (work@oh_xnor3), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_xnor3.v, line:7:1, endln:17:10 + \_module_inst: work@oh_xnor3 (work@oh_xnor3), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_xnor3.v, line:7:1, endln:17:10 |vpiName:b |vpiDirection:1 |vpiLowConn: @@ -58546,7 +58546,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (c), line:11:21, endln:11:22 |vpiParent: - \_module: work@oh_xnor3 (work@oh_xnor3), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_xnor3.v, line:7:1, endln:17:10 + \_module_inst: work@oh_xnor3 (work@oh_xnor3), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_xnor3.v, line:7:1, endln:17:10 |vpiName:c |vpiDirection:1 |vpiLowConn: @@ -58586,7 +58586,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (z), line:12:21, endln:12:22 |vpiParent: - \_module: work@oh_xnor3 (work@oh_xnor3), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_xnor3.v, line:7:1, endln:17:10 + \_module_inst: work@oh_xnor3 (work@oh_xnor3), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_xnor3.v, line:7:1, endln:17:10 |vpiName:z |vpiDirection:2 |vpiLowConn: @@ -58626,7 +58626,7 @@ design: (work@oh_fifo_async) |vpiContAssign: \_cont_assign: , line:15:11, endln:15:28 |vpiParent: - \_module: work@oh_xnor3 (work@oh_xnor3), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_xnor3.v, line:7:1, endln:17:10 + \_module_inst: work@oh_xnor3 (work@oh_xnor3), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_xnor3.v, line:7:1, endln:17:10 |vpiRhs: \_operation: , line:15:16, endln:15:28 |vpiParent: @@ -58667,14 +58667,14 @@ design: (work@oh_fifo_async) |vpiName:z |vpiFullName:work@oh_xnor3.z |uhdmallModules: -\_module: work@oh_xnor4 (work@oh_xnor4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_xnor4.v, line:7:1, endln:18:10 +\_module_inst: work@oh_xnor4 (work@oh_xnor4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_xnor4.v, line:7:1, endln:18:10 |vpiParent: \_design: (work@oh_fifo_async) |vpiFullName:work@oh_xnor4 |vpiParameter: \_parameter: (work@oh_xnor4.DW), line:7:29, endln:7:31 |vpiParent: - \_module: work@oh_xnor4 (work@oh_xnor4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_xnor4.v, line:7:1, endln:18:10 + \_module_inst: work@oh_xnor4 (work@oh_xnor4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_xnor4.v, line:7:1, endln:18:10 |UINT:1 |vpiTypespec: \_int_typespec: @@ -58683,7 +58683,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:7:29, endln:7:35 |vpiParent: - \_module: work@oh_xnor4 (work@oh_xnor4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_xnor4.v, line:7:1, endln:18:10 + \_module_inst: work@oh_xnor4 (work@oh_xnor4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_xnor4.v, line:7:1, endln:18:10 |vpiRhs: \_constant: , line:7:34, endln:7:35 |vpiDecompile:1 @@ -58699,37 +58699,37 @@ design: (work@oh_fifo_async) |vpiNet: \_logic_net: (work@oh_xnor4.a), line:9:21, endln:9:22 |vpiParent: - \_module: work@oh_xnor4 (work@oh_xnor4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_xnor4.v, line:7:1, endln:18:10 + \_module_inst: work@oh_xnor4 (work@oh_xnor4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_xnor4.v, line:7:1, endln:18:10 |vpiName:a |vpiFullName:work@oh_xnor4.a |vpiNet: \_logic_net: (work@oh_xnor4.b), line:10:21, endln:10:22 |vpiParent: - \_module: work@oh_xnor4 (work@oh_xnor4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_xnor4.v, line:7:1, endln:18:10 + \_module_inst: work@oh_xnor4 (work@oh_xnor4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_xnor4.v, line:7:1, endln:18:10 |vpiName:b |vpiFullName:work@oh_xnor4.b |vpiNet: \_logic_net: (work@oh_xnor4.c), line:11:21, endln:11:22 |vpiParent: - \_module: work@oh_xnor4 (work@oh_xnor4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_xnor4.v, line:7:1, endln:18:10 + \_module_inst: work@oh_xnor4 (work@oh_xnor4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_xnor4.v, line:7:1, endln:18:10 |vpiName:c |vpiFullName:work@oh_xnor4.c |vpiNet: \_logic_net: (work@oh_xnor4.d), line:12:21, endln:12:22 |vpiParent: - \_module: work@oh_xnor4 (work@oh_xnor4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_xnor4.v, line:7:1, endln:18:10 + \_module_inst: work@oh_xnor4 (work@oh_xnor4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_xnor4.v, line:7:1, endln:18:10 |vpiName:d |vpiFullName:work@oh_xnor4.d |vpiNet: \_logic_net: (work@oh_xnor4.z), line:13:21, endln:13:22 |vpiParent: - \_module: work@oh_xnor4 (work@oh_xnor4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_xnor4.v, line:7:1, endln:18:10 + \_module_inst: work@oh_xnor4 (work@oh_xnor4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_xnor4.v, line:7:1, endln:18:10 |vpiName:z |vpiFullName:work@oh_xnor4.z |vpiPort: \_port: (a), line:9:21, endln:9:22 |vpiParent: - \_module: work@oh_xnor4 (work@oh_xnor4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_xnor4.v, line:7:1, endln:18:10 + \_module_inst: work@oh_xnor4 (work@oh_xnor4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_xnor4.v, line:7:1, endln:18:10 |vpiName:a |vpiDirection:1 |vpiLowConn: @@ -58769,7 +58769,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (b), line:10:21, endln:10:22 |vpiParent: - \_module: work@oh_xnor4 (work@oh_xnor4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_xnor4.v, line:7:1, endln:18:10 + \_module_inst: work@oh_xnor4 (work@oh_xnor4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_xnor4.v, line:7:1, endln:18:10 |vpiName:b |vpiDirection:1 |vpiLowConn: @@ -58809,7 +58809,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (c), line:11:21, endln:11:22 |vpiParent: - \_module: work@oh_xnor4 (work@oh_xnor4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_xnor4.v, line:7:1, endln:18:10 + \_module_inst: work@oh_xnor4 (work@oh_xnor4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_xnor4.v, line:7:1, endln:18:10 |vpiName:c |vpiDirection:1 |vpiLowConn: @@ -58849,7 +58849,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (d), line:12:21, endln:12:22 |vpiParent: - \_module: work@oh_xnor4 (work@oh_xnor4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_xnor4.v, line:7:1, endln:18:10 + \_module_inst: work@oh_xnor4 (work@oh_xnor4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_xnor4.v, line:7:1, endln:18:10 |vpiName:d |vpiDirection:1 |vpiLowConn: @@ -58889,7 +58889,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (z), line:13:21, endln:13:22 |vpiParent: - \_module: work@oh_xnor4 (work@oh_xnor4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_xnor4.v, line:7:1, endln:18:10 + \_module_inst: work@oh_xnor4 (work@oh_xnor4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_xnor4.v, line:7:1, endln:18:10 |vpiName:z |vpiDirection:2 |vpiLowConn: @@ -58929,7 +58929,7 @@ design: (work@oh_fifo_async) |vpiContAssign: \_cont_assign: , line:16:11, endln:16:32 |vpiParent: - \_module: work@oh_xnor4 (work@oh_xnor4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_xnor4.v, line:7:1, endln:18:10 + \_module_inst: work@oh_xnor4 (work@oh_xnor4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_xnor4.v, line:7:1, endln:18:10 |vpiRhs: \_operation: , line:16:16, endln:16:32 |vpiParent: @@ -58981,14 +58981,14 @@ design: (work@oh_fifo_async) |vpiName:z |vpiFullName:work@oh_xnor4.z |uhdmallModules: -\_module: work@oh_xor2 (work@oh_xor2), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_xor2.v, line:7:1, endln:16:10 +\_module_inst: work@oh_xor2 (work@oh_xor2), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_xor2.v, line:7:1, endln:16:10 |vpiParent: \_design: (work@oh_fifo_async) |vpiFullName:work@oh_xor2 |vpiParameter: \_parameter: (work@oh_xor2.DW), line:7:28, endln:7:30 |vpiParent: - \_module: work@oh_xor2 (work@oh_xor2), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_xor2.v, line:7:1, endln:16:10 + \_module_inst: work@oh_xor2 (work@oh_xor2), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_xor2.v, line:7:1, endln:16:10 |UINT:1 |vpiTypespec: \_int_typespec: @@ -58997,7 +58997,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:7:28, endln:7:34 |vpiParent: - \_module: work@oh_xor2 (work@oh_xor2), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_xor2.v, line:7:1, endln:16:10 + \_module_inst: work@oh_xor2 (work@oh_xor2), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_xor2.v, line:7:1, endln:16:10 |vpiRhs: \_constant: , line:7:33, endln:7:34 |vpiDecompile:1 @@ -59013,25 +59013,25 @@ design: (work@oh_fifo_async) |vpiNet: \_logic_net: (work@oh_xor2.a), line:9:21, endln:9:22 |vpiParent: - \_module: work@oh_xor2 (work@oh_xor2), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_xor2.v, line:7:1, endln:16:10 + \_module_inst: work@oh_xor2 (work@oh_xor2), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_xor2.v, line:7:1, endln:16:10 |vpiName:a |vpiFullName:work@oh_xor2.a |vpiNet: \_logic_net: (work@oh_xor2.b), line:10:21, endln:10:22 |vpiParent: - \_module: work@oh_xor2 (work@oh_xor2), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_xor2.v, line:7:1, endln:16:10 + \_module_inst: work@oh_xor2 (work@oh_xor2), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_xor2.v, line:7:1, endln:16:10 |vpiName:b |vpiFullName:work@oh_xor2.b |vpiNet: \_logic_net: (work@oh_xor2.z), line:11:21, endln:11:22 |vpiParent: - \_module: work@oh_xor2 (work@oh_xor2), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_xor2.v, line:7:1, endln:16:10 + \_module_inst: work@oh_xor2 (work@oh_xor2), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_xor2.v, line:7:1, endln:16:10 |vpiName:z |vpiFullName:work@oh_xor2.z |vpiPort: \_port: (a), line:9:21, endln:9:22 |vpiParent: - \_module: work@oh_xor2 (work@oh_xor2), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_xor2.v, line:7:1, endln:16:10 + \_module_inst: work@oh_xor2 (work@oh_xor2), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_xor2.v, line:7:1, endln:16:10 |vpiName:a |vpiDirection:1 |vpiLowConn: @@ -59071,7 +59071,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (b), line:10:21, endln:10:22 |vpiParent: - \_module: work@oh_xor2 (work@oh_xor2), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_xor2.v, line:7:1, endln:16:10 + \_module_inst: work@oh_xor2 (work@oh_xor2), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_xor2.v, line:7:1, endln:16:10 |vpiName:b |vpiDirection:1 |vpiLowConn: @@ -59111,7 +59111,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (z), line:11:21, endln:11:22 |vpiParent: - \_module: work@oh_xor2 (work@oh_xor2), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_xor2.v, line:7:1, endln:16:10 + \_module_inst: work@oh_xor2 (work@oh_xor2), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_xor2.v, line:7:1, endln:16:10 |vpiName:z |vpiDirection:2 |vpiLowConn: @@ -59151,7 +59151,7 @@ design: (work@oh_fifo_async) |vpiContAssign: \_cont_assign: , line:14:11, endln:14:21 |vpiParent: - \_module: work@oh_xor2 (work@oh_xor2), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_xor2.v, line:7:1, endln:16:10 + \_module_inst: work@oh_xor2 (work@oh_xor2), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_xor2.v, line:7:1, endln:16:10 |vpiRhs: \_operation: , line:14:16, endln:14:21 |vpiParent: @@ -59176,14 +59176,14 @@ design: (work@oh_fifo_async) |vpiName:z |vpiFullName:work@oh_xor2.z |uhdmallModules: -\_module: work@oh_xor3 (work@oh_xor3), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_xor3.v, line:7:1, endln:17:10 +\_module_inst: work@oh_xor3 (work@oh_xor3), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_xor3.v, line:7:1, endln:17:10 |vpiParent: \_design: (work@oh_fifo_async) |vpiFullName:work@oh_xor3 |vpiParameter: \_parameter: (work@oh_xor3.DW), line:7:28, endln:7:30 |vpiParent: - \_module: work@oh_xor3 (work@oh_xor3), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_xor3.v, line:7:1, endln:17:10 + \_module_inst: work@oh_xor3 (work@oh_xor3), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_xor3.v, line:7:1, endln:17:10 |UINT:1 |vpiTypespec: \_int_typespec: @@ -59192,7 +59192,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:7:28, endln:7:34 |vpiParent: - \_module: work@oh_xor3 (work@oh_xor3), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_xor3.v, line:7:1, endln:17:10 + \_module_inst: work@oh_xor3 (work@oh_xor3), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_xor3.v, line:7:1, endln:17:10 |vpiRhs: \_constant: , line:7:33, endln:7:34 |vpiDecompile:1 @@ -59208,31 +59208,31 @@ design: (work@oh_fifo_async) |vpiNet: \_logic_net: (work@oh_xor3.a), line:9:21, endln:9:22 |vpiParent: - \_module: work@oh_xor3 (work@oh_xor3), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_xor3.v, line:7:1, endln:17:10 + \_module_inst: work@oh_xor3 (work@oh_xor3), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_xor3.v, line:7:1, endln:17:10 |vpiName:a |vpiFullName:work@oh_xor3.a |vpiNet: \_logic_net: (work@oh_xor3.b), line:10:21, endln:10:22 |vpiParent: - \_module: work@oh_xor3 (work@oh_xor3), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_xor3.v, line:7:1, endln:17:10 + \_module_inst: work@oh_xor3 (work@oh_xor3), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_xor3.v, line:7:1, endln:17:10 |vpiName:b |vpiFullName:work@oh_xor3.b |vpiNet: \_logic_net: (work@oh_xor3.c), line:11:21, endln:11:22 |vpiParent: - \_module: work@oh_xor3 (work@oh_xor3), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_xor3.v, line:7:1, endln:17:10 + \_module_inst: work@oh_xor3 (work@oh_xor3), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_xor3.v, line:7:1, endln:17:10 |vpiName:c |vpiFullName:work@oh_xor3.c |vpiNet: \_logic_net: (work@oh_xor3.z), line:12:21, endln:12:22 |vpiParent: - \_module: work@oh_xor3 (work@oh_xor3), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_xor3.v, line:7:1, endln:17:10 + \_module_inst: work@oh_xor3 (work@oh_xor3), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_xor3.v, line:7:1, endln:17:10 |vpiName:z |vpiFullName:work@oh_xor3.z |vpiPort: \_port: (a), line:9:21, endln:9:22 |vpiParent: - \_module: work@oh_xor3 (work@oh_xor3), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_xor3.v, line:7:1, endln:17:10 + \_module_inst: work@oh_xor3 (work@oh_xor3), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_xor3.v, line:7:1, endln:17:10 |vpiName:a |vpiDirection:1 |vpiLowConn: @@ -59272,7 +59272,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (b), line:10:21, endln:10:22 |vpiParent: - \_module: work@oh_xor3 (work@oh_xor3), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_xor3.v, line:7:1, endln:17:10 + \_module_inst: work@oh_xor3 (work@oh_xor3), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_xor3.v, line:7:1, endln:17:10 |vpiName:b |vpiDirection:1 |vpiLowConn: @@ -59312,7 +59312,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (c), line:11:21, endln:11:22 |vpiParent: - \_module: work@oh_xor3 (work@oh_xor3), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_xor3.v, line:7:1, endln:17:10 + \_module_inst: work@oh_xor3 (work@oh_xor3), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_xor3.v, line:7:1, endln:17:10 |vpiName:c |vpiDirection:1 |vpiLowConn: @@ -59352,7 +59352,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (z), line:12:21, endln:12:22 |vpiParent: - \_module: work@oh_xor3 (work@oh_xor3), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_xor3.v, line:7:1, endln:17:10 + \_module_inst: work@oh_xor3 (work@oh_xor3), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_xor3.v, line:7:1, endln:17:10 |vpiName:z |vpiDirection:2 |vpiLowConn: @@ -59392,7 +59392,7 @@ design: (work@oh_fifo_async) |vpiContAssign: \_cont_assign: , line:15:11, endln:15:25 |vpiParent: - \_module: work@oh_xor3 (work@oh_xor3), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_xor3.v, line:7:1, endln:17:10 + \_module_inst: work@oh_xor3 (work@oh_xor3), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_xor3.v, line:7:1, endln:17:10 |vpiRhs: \_operation: , line:15:16, endln:15:25 |vpiParent: @@ -59428,14 +59428,14 @@ design: (work@oh_fifo_async) |vpiName:z |vpiFullName:work@oh_xor3.z |uhdmallModules: -\_module: work@oh_xor4 (work@oh_xor4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_xor4.v, line:7:1, endln:18:10 +\_module_inst: work@oh_xor4 (work@oh_xor4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_xor4.v, line:7:1, endln:18:10 |vpiParent: \_design: (work@oh_fifo_async) |vpiFullName:work@oh_xor4 |vpiParameter: \_parameter: (work@oh_xor4.DW), line:7:28, endln:7:30 |vpiParent: - \_module: work@oh_xor4 (work@oh_xor4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_xor4.v, line:7:1, endln:18:10 + \_module_inst: work@oh_xor4 (work@oh_xor4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_xor4.v, line:7:1, endln:18:10 |UINT:1 |vpiTypespec: \_int_typespec: @@ -59444,7 +59444,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:7:28, endln:7:34 |vpiParent: - \_module: work@oh_xor4 (work@oh_xor4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_xor4.v, line:7:1, endln:18:10 + \_module_inst: work@oh_xor4 (work@oh_xor4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_xor4.v, line:7:1, endln:18:10 |vpiRhs: \_constant: , line:7:33, endln:7:34 |vpiDecompile:1 @@ -59460,37 +59460,37 @@ design: (work@oh_fifo_async) |vpiNet: \_logic_net: (work@oh_xor4.a), line:9:21, endln:9:22 |vpiParent: - \_module: work@oh_xor4 (work@oh_xor4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_xor4.v, line:7:1, endln:18:10 + \_module_inst: work@oh_xor4 (work@oh_xor4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_xor4.v, line:7:1, endln:18:10 |vpiName:a |vpiFullName:work@oh_xor4.a |vpiNet: \_logic_net: (work@oh_xor4.b), line:10:21, endln:10:22 |vpiParent: - \_module: work@oh_xor4 (work@oh_xor4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_xor4.v, line:7:1, endln:18:10 + \_module_inst: work@oh_xor4 (work@oh_xor4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_xor4.v, line:7:1, endln:18:10 |vpiName:b |vpiFullName:work@oh_xor4.b |vpiNet: \_logic_net: (work@oh_xor4.c), line:11:21, endln:11:22 |vpiParent: - \_module: work@oh_xor4 (work@oh_xor4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_xor4.v, line:7:1, endln:18:10 + \_module_inst: work@oh_xor4 (work@oh_xor4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_xor4.v, line:7:1, endln:18:10 |vpiName:c |vpiFullName:work@oh_xor4.c |vpiNet: \_logic_net: (work@oh_xor4.d), line:12:21, endln:12:22 |vpiParent: - \_module: work@oh_xor4 (work@oh_xor4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_xor4.v, line:7:1, endln:18:10 + \_module_inst: work@oh_xor4 (work@oh_xor4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_xor4.v, line:7:1, endln:18:10 |vpiName:d |vpiFullName:work@oh_xor4.d |vpiNet: \_logic_net: (work@oh_xor4.z), line:13:21, endln:13:22 |vpiParent: - \_module: work@oh_xor4 (work@oh_xor4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_xor4.v, line:7:1, endln:18:10 + \_module_inst: work@oh_xor4 (work@oh_xor4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_xor4.v, line:7:1, endln:18:10 |vpiName:z |vpiFullName:work@oh_xor4.z |vpiPort: \_port: (a), line:9:21, endln:9:22 |vpiParent: - \_module: work@oh_xor4 (work@oh_xor4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_xor4.v, line:7:1, endln:18:10 + \_module_inst: work@oh_xor4 (work@oh_xor4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_xor4.v, line:7:1, endln:18:10 |vpiName:a |vpiDirection:1 |vpiLowConn: @@ -59530,7 +59530,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (b), line:10:21, endln:10:22 |vpiParent: - \_module: work@oh_xor4 (work@oh_xor4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_xor4.v, line:7:1, endln:18:10 + \_module_inst: work@oh_xor4 (work@oh_xor4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_xor4.v, line:7:1, endln:18:10 |vpiName:b |vpiDirection:1 |vpiLowConn: @@ -59570,7 +59570,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (c), line:11:21, endln:11:22 |vpiParent: - \_module: work@oh_xor4 (work@oh_xor4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_xor4.v, line:7:1, endln:18:10 + \_module_inst: work@oh_xor4 (work@oh_xor4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_xor4.v, line:7:1, endln:18:10 |vpiName:c |vpiDirection:1 |vpiLowConn: @@ -59610,7 +59610,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (d), line:12:21, endln:12:22 |vpiParent: - \_module: work@oh_xor4 (work@oh_xor4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_xor4.v, line:7:1, endln:18:10 + \_module_inst: work@oh_xor4 (work@oh_xor4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_xor4.v, line:7:1, endln:18:10 |vpiName:d |vpiDirection:1 |vpiLowConn: @@ -59650,7 +59650,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (z), line:13:21, endln:13:22 |vpiParent: - \_module: work@oh_xor4 (work@oh_xor4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_xor4.v, line:7:1, endln:18:10 + \_module_inst: work@oh_xor4 (work@oh_xor4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_xor4.v, line:7:1, endln:18:10 |vpiName:z |vpiDirection:2 |vpiLowConn: @@ -59690,7 +59690,7 @@ design: (work@oh_fifo_async) |vpiContAssign: \_cont_assign: , line:16:11, endln:16:29 |vpiParent: - \_module: work@oh_xor4 (work@oh_xor4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_xor4.v, line:7:1, endln:18:10 + \_module_inst: work@oh_xor4 (work@oh_xor4), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_xor4.v, line:7:1, endln:18:10 |vpiRhs: \_operation: , line:16:16, endln:16:29 |vpiParent: @@ -59737,14 +59737,14 @@ design: (work@oh_fifo_async) |vpiName:z |vpiFullName:work@oh_xor4.z |uhdmallModules: -\_module: work@ohr_reg0 (work@ohr_reg0), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_reg0.v, line:8:1, endln:31:10 +\_module_inst: work@ohr_reg0 (work@ohr_reg0), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_reg0.v, line:8:1, endln:31:10 |vpiParent: \_design: (work@oh_fifo_async) |vpiFullName:work@ohr_reg0 |vpiParameter: \_parameter: (work@ohr_reg0.N), line:8:29, endln:8:30 |vpiParent: - \_module: work@ohr_reg0 (work@ohr_reg0), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_reg0.v, line:8:1, endln:31:10 + \_module_inst: work@ohr_reg0 (work@ohr_reg0), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_reg0.v, line:8:1, endln:31:10 |UINT:1 |vpiTypespec: \_int_typespec: @@ -59753,7 +59753,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:8:29, endln:8:34 |vpiParent: - \_module: work@ohr_reg0 (work@ohr_reg0), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_reg0.v, line:8:1, endln:31:10 + \_module_inst: work@ohr_reg0 (work@ohr_reg0), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_reg0.v, line:8:1, endln:31:10 |vpiRhs: \_constant: , line:8:33, endln:8:34 |vpiDecompile:1 @@ -59769,38 +59769,38 @@ design: (work@oh_fifo_async) |vpiNet: \_logic_net: (work@ohr_reg0.nreset), line:10:22, endln:10:28 |vpiParent: - \_module: work@ohr_reg0 (work@ohr_reg0), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_reg0.v, line:8:1, endln:31:10 + \_module_inst: work@ohr_reg0 (work@ohr_reg0), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_reg0.v, line:8:1, endln:31:10 |vpiName:nreset |vpiFullName:work@ohr_reg0.nreset |vpiNet: \_logic_net: (work@ohr_reg0.clk), line:11:18, endln:11:21 |vpiParent: - \_module: work@ohr_reg0 (work@ohr_reg0), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_reg0.v, line:8:1, endln:31:10 + \_module_inst: work@ohr_reg0 (work@ohr_reg0), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_reg0.v, line:8:1, endln:31:10 |vpiName:clk |vpiFullName:work@ohr_reg0.clk |vpiNet: \_logic_net: (work@ohr_reg0.in), line:12:21, endln:12:23 |vpiParent: - \_module: work@ohr_reg0 (work@ohr_reg0), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_reg0.v, line:8:1, endln:31:10 + \_module_inst: work@ohr_reg0 (work@ohr_reg0), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_reg0.v, line:8:1, endln:31:10 |vpiName:in |vpiFullName:work@ohr_reg0.in |vpiNet: \_logic_net: (work@ohr_reg0.out), line:13:21, endln:13:24 |vpiParent: - \_module: work@ohr_reg0 (work@ohr_reg0), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_reg0.v, line:8:1, endln:31:10 + \_module_inst: work@ohr_reg0 (work@ohr_reg0), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_reg0.v, line:8:1, endln:31:10 |vpiName:out |vpiFullName:work@ohr_reg0.out |vpiNet: \_logic_net: (work@ohr_reg0.out_reg), line:22:21, endln:22:28 |vpiParent: - \_module: work@ohr_reg0 (work@ohr_reg0), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_reg0.v, line:8:1, endln:31:10 + \_module_inst: work@ohr_reg0 (work@ohr_reg0), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_reg0.v, line:8:1, endln:31:10 |vpiName:out_reg |vpiFullName:work@ohr_reg0.out_reg |vpiNetType:48 |vpiPort: \_port: (nreset), line:10:22, endln:10:28 |vpiParent: - \_module: work@ohr_reg0 (work@ohr_reg0), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_reg0.v, line:8:1, endln:31:10 + \_module_inst: work@ohr_reg0 (work@ohr_reg0), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_reg0.v, line:8:1, endln:31:10 |vpiName:nreset |vpiDirection:1 |vpiLowConn: @@ -59812,7 +59812,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (clk), line:11:18, endln:11:21 |vpiParent: - \_module: work@ohr_reg0 (work@ohr_reg0), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_reg0.v, line:8:1, endln:31:10 + \_module_inst: work@ohr_reg0 (work@ohr_reg0), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_reg0.v, line:8:1, endln:31:10 |vpiName:clk |vpiDirection:1 |vpiLowConn: @@ -59824,7 +59824,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (in), line:12:21, endln:12:23 |vpiParent: - \_module: work@ohr_reg0 (work@ohr_reg0), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_reg0.v, line:8:1, endln:31:10 + \_module_inst: work@ohr_reg0 (work@ohr_reg0), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_reg0.v, line:8:1, endln:31:10 |vpiName:in |vpiDirection:1 |vpiLowConn: @@ -59864,7 +59864,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (out), line:13:21, endln:13:24 |vpiParent: - \_module: work@ohr_reg0 (work@ohr_reg0), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_reg0.v, line:8:1, endln:31:10 + \_module_inst: work@ohr_reg0 (work@ohr_reg0), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_reg0.v, line:8:1, endln:31:10 |vpiName:out |vpiDirection:2 |vpiLowConn: @@ -59904,7 +59904,7 @@ design: (work@oh_fifo_async) |vpiProcess: \_always: , line:23:4, endln:27:36 |vpiParent: - \_module: work@ohr_reg0 (work@ohr_reg0), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_reg0.v, line:8:1, endln:31:10 + \_module_inst: work@ohr_reg0 (work@ohr_reg0), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_reg0.v, line:8:1, endln:31:10 |vpiStmt: \_event_control: , line:23:11, endln:23:44 |vpiParent: @@ -60071,7 +60071,7 @@ design: (work@oh_fifo_async) |vpiContAssign: \_cont_assign: , line:28:11, endln:28:38 |vpiParent: - \_module: work@ohr_reg0 (work@ohr_reg0), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_reg0.v, line:8:1, endln:31:10 + \_module_inst: work@ohr_reg0 (work@ohr_reg0), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_reg0.v, line:8:1, endln:31:10 |vpiRhs: \_part_select: , line:28:24, endln:28:38 |vpiParent: @@ -60137,12 +60137,12 @@ design: (work@oh_fifo_async) |UINT:0 |vpiConstType:9 |uhdmtopModules: -\_module: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 +\_module_inst: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 |vpiName:work@oh_fifo_async |vpiParameter: \_parameter: (work@oh_fifo_async.N), line:12:15, endln:12:16 |vpiParent: - \_module: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 + \_module_inst: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 |UINT:32 |vpiTypespec: \_int_typespec: @@ -60153,7 +60153,7 @@ design: (work@oh_fifo_async) |vpiParameter: \_parameter: (work@oh_fifo_async.DEPTH), line:13:15, endln:13:20 |vpiParent: - \_module: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 + \_module_inst: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 |UINT:32 |vpiTypespec: \_int_typespec: @@ -60164,7 +60164,7 @@ design: (work@oh_fifo_async) |vpiParameter: \_parameter: (work@oh_fifo_async.REG), line:14:15, endln:14:18 |vpiParent: - \_module: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 + \_module_inst: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 |UINT:1 |vpiTypespec: \_int_typespec: @@ -60175,13 +60175,13 @@ design: (work@oh_fifo_async) |vpiParameter: \_parameter: (work@oh_fifo_async.AW), line:15:15, endln:15:17 |vpiParent: - \_module: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 + \_module_inst: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 |vpiName:AW |vpiFullName:work@oh_fifo_async.AW |vpiParameter: \_parameter: (work@oh_fifo_async.SYNCPIPE), line:16:15, endln:16:23 |vpiParent: - \_module: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 + \_module_inst: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 |UINT:2 |vpiTypespec: \_int_typespec: @@ -60192,7 +60192,7 @@ design: (work@oh_fifo_async) |vpiParameter: \_parameter: (work@oh_fifo_async.SYN), line:17:15, endln:17:18 |vpiParent: - \_module: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 + \_module_inst: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 |STRING:TRUE |vpiTypespec: \_string_typespec: @@ -60203,7 +60203,7 @@ design: (work@oh_fifo_async) |vpiParameter: \_parameter: (work@oh_fifo_async.TYPE), line:18:15, endln:18:19 |vpiParent: - \_module: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 + \_module_inst: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 |STRING:DEFAULT |vpiTypespec: \_string_typespec: @@ -60214,13 +60214,13 @@ design: (work@oh_fifo_async) |vpiParameter: \_parameter: (work@oh_fifo_async.PROGFULL), line:19:15, endln:19:23 |vpiParent: - \_module: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 + \_module_inst: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 |vpiName:PROGFULL |vpiFullName:work@oh_fifo_async.PROGFULL |vpiParameter: \_parameter: (work@oh_fifo_async.SHAPE), line:20:15, endln:20:20 |vpiParent: - \_module: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 + \_module_inst: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 |STRING:SQUARE |vpiTypespec: \_string_typespec: @@ -60231,7 +60231,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:12:15, endln:12:28 |vpiParent: - \_module: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 + \_module_inst: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 |vpiRhs: \_constant: , line:12:26, endln:12:28 |vpiDecompile:32 @@ -60245,7 +60245,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:13:15, endln:13:28 |vpiParent: - \_module: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 + \_module_inst: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 |vpiRhs: \_constant: , line:13:26, endln:13:28 |vpiDecompile:32 @@ -60259,7 +60259,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:14:15, endln:14:27 |vpiParent: - \_module: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 + \_module_inst: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 |vpiRhs: \_constant: , line:14:26, endln:14:27 |vpiDecompile:1 @@ -60273,7 +60273,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:15:15, endln:15:39 |vpiParent: - \_module: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 + \_module_inst: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 |vpiRhs: \_constant: , line:15:26, endln:15:39 |vpiDecompile:5 @@ -60285,7 +60285,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:16:15, endln:16:27 |vpiParent: - \_module: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 + \_module_inst: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 |vpiRhs: \_constant: , line:16:26, endln:16:27 |vpiDecompile:2 @@ -60299,7 +60299,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:17:15, endln:17:32 |vpiParent: - \_module: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 + \_module_inst: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 |vpiRhs: \_constant: , line:17:26, endln:17:32 |vpiDecompile:TRUE @@ -60313,7 +60313,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:18:15, endln:18:35 |vpiParent: - \_module: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 + \_module_inst: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 |vpiRhs: \_constant: , line:18:26, endln:18:35 |vpiDecompile:DEFAULT @@ -60327,7 +60327,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:19:15, endln:19:33 |vpiParent: - \_module: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 + \_module_inst: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 |vpiRhs: \_constant: , line:19:26, endln:19:33 |vpiDecompile:31 @@ -60339,7 +60339,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:20:15, endln:20:34 |vpiParent: - \_module: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 + \_module_inst: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 |vpiRhs: \_constant: , line:20:26, endln:20:34 |vpiDecompile:SQUARE @@ -60355,7 +60355,7 @@ design: (work@oh_fifo_async) |vpiNet: \_logic_net: (work@oh_fifo_async.nreset), line:23:16, endln:23:22 |vpiParent: - \_module: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 + \_module_inst: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 |vpiTypespec: \_logic_typespec: , line:23:16, endln:23:16 |vpiName:nreset @@ -60363,7 +60363,7 @@ design: (work@oh_fifo_async) |vpiNet: \_logic_net: (work@oh_fifo_async.wr_clk), line:25:16, endln:25:22 |vpiParent: - \_module: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 + \_module_inst: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 |vpiTypespec: \_logic_typespec: , line:25:16, endln:25:16 |vpiName:wr_clk @@ -60371,7 +60371,7 @@ design: (work@oh_fifo_async) |vpiNet: \_logic_net: (work@oh_fifo_async.wr_din), line:26:20, endln:26:26 |vpiParent: - \_module: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 + \_module_inst: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 |vpiTypespec: \_logic_typespec: , line:26:11, endln:26:18 |vpiRange: @@ -60397,7 +60397,7 @@ design: (work@oh_fifo_async) |vpiNet: \_logic_net: (work@oh_fifo_async.wr_en), line:27:16, endln:27:21 |vpiParent: - \_module: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 + \_module_inst: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 |vpiTypespec: \_logic_typespec: , line:27:16, endln:27:16 |vpiName:wr_en @@ -60405,7 +60405,7 @@ design: (work@oh_fifo_async) |vpiNet: \_logic_net: (work@oh_fifo_async.wr_full), line:28:17, endln:28:24 |vpiParent: - \_module: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 + \_module_inst: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 |vpiTypespec: \_logic_typespec: , line:28:17, endln:28:17 |vpiName:wr_full @@ -60413,7 +60413,7 @@ design: (work@oh_fifo_async) |vpiNet: \_logic_net: (work@oh_fifo_async.wr_almost_full), line:29:17, endln:29:31 |vpiParent: - \_module: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 + \_module_inst: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 |vpiTypespec: \_logic_typespec: , line:29:17, endln:29:17 |vpiName:wr_almost_full @@ -60421,7 +60421,7 @@ design: (work@oh_fifo_async) |vpiNet: \_logic_net: (work@oh_fifo_async.wr_prog_full), line:30:17, endln:30:29 |vpiParent: - \_module: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 + \_module_inst: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 |vpiTypespec: \_logic_typespec: , line:30:17, endln:30:17 |vpiName:wr_prog_full @@ -60429,7 +60429,7 @@ design: (work@oh_fifo_async) |vpiNet: \_logic_net: (work@oh_fifo_async.wr_count), line:31:21, endln:31:29 |vpiParent: - \_module: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 + \_module_inst: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 |vpiTypespec: \_logic_typespec: , line:31:12, endln:31:20 |vpiRange: @@ -60455,7 +60455,7 @@ design: (work@oh_fifo_async) |vpiNet: \_logic_net: (work@oh_fifo_async.rd_clk), line:33:16, endln:33:22 |vpiParent: - \_module: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 + \_module_inst: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 |vpiTypespec: \_logic_typespec: , line:33:16, endln:33:16 |vpiName:rd_clk @@ -60463,7 +60463,7 @@ design: (work@oh_fifo_async) |vpiNet: \_logic_net: (work@oh_fifo_async.rd_dout), line:34:20, endln:34:27 |vpiParent: - \_module: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 + \_module_inst: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 |vpiTypespec: \_logic_typespec: , line:34:12, endln:34:19 |vpiRange: @@ -60489,7 +60489,7 @@ design: (work@oh_fifo_async) |vpiNet: \_logic_net: (work@oh_fifo_async.rd_en), line:35:16, endln:35:21 |vpiParent: - \_module: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 + \_module_inst: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 |vpiTypespec: \_logic_typespec: , line:35:16, endln:35:16 |vpiName:rd_en @@ -60497,7 +60497,7 @@ design: (work@oh_fifo_async) |vpiNet: \_logic_net: (work@oh_fifo_async.rd_empty), line:36:17, endln:36:25 |vpiParent: - \_module: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 + \_module_inst: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 |vpiTypespec: \_logic_typespec: , line:36:17, endln:36:17 |vpiName:rd_empty @@ -60505,7 +60505,7 @@ design: (work@oh_fifo_async) |vpiNet: \_logic_net: (work@oh_fifo_async.rd_count), line:37:21, endln:37:29 |vpiParent: - \_module: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 + \_module_inst: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 |vpiTypespec: \_logic_typespec: , line:37:12, endln:37:20 |vpiRange: @@ -60531,7 +60531,7 @@ design: (work@oh_fifo_async) |vpiNet: \_logic_net: (work@oh_fifo_async.bist_en), line:39:16, endln:39:23 |vpiParent: - \_module: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 + \_module_inst: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 |vpiTypespec: \_logic_typespec: , line:39:16, endln:39:16 |vpiName:bist_en @@ -60539,7 +60539,7 @@ design: (work@oh_fifo_async) |vpiNet: \_logic_net: (work@oh_fifo_async.bist_we), line:40:16, endln:40:23 |vpiParent: - \_module: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 + \_module_inst: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 |vpiTypespec: \_logic_typespec: , line:40:16, endln:40:16 |vpiName:bist_we @@ -60547,7 +60547,7 @@ design: (work@oh_fifo_async) |vpiNet: \_logic_net: (work@oh_fifo_async.bist_wem), line:41:20, endln:41:28 |vpiParent: - \_module: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 + \_module_inst: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 |vpiTypespec: \_logic_typespec: , line:41:11, endln:41:18 |vpiRange: @@ -60573,7 +60573,7 @@ design: (work@oh_fifo_async) |vpiNet: \_logic_net: (work@oh_fifo_async.bist_addr), line:42:21, endln:42:30 |vpiParent: - \_module: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 + \_module_inst: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 |vpiTypespec: \_logic_typespec: , line:42:11, endln:42:19 |vpiRange: @@ -60599,7 +60599,7 @@ design: (work@oh_fifo_async) |vpiNet: \_logic_net: (work@oh_fifo_async.bist_din), line:43:20, endln:43:28 |vpiParent: - \_module: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 + \_module_inst: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 |vpiTypespec: \_logic_typespec: , line:43:11, endln:43:18 |vpiRange: @@ -60625,7 +60625,7 @@ design: (work@oh_fifo_async) |vpiNet: \_logic_net: (work@oh_fifo_async.bist_dout), line:44:20, endln:44:29 |vpiParent: - \_module: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 + \_module_inst: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 |vpiTypespec: \_logic_typespec: , line:44:11, endln:44:18 |vpiRange: @@ -60651,7 +60651,7 @@ design: (work@oh_fifo_async) |vpiNet: \_logic_net: (work@oh_fifo_async.shutdown), line:46:16, endln:46:24 |vpiParent: - \_module: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 + \_module_inst: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 |vpiTypespec: \_logic_typespec: , line:46:16, endln:46:16 |vpiName:shutdown @@ -60659,7 +60659,7 @@ design: (work@oh_fifo_async) |vpiNet: \_logic_net: (work@oh_fifo_async.vss), line:47:16, endln:47:19 |vpiParent: - \_module: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 + \_module_inst: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 |vpiTypespec: \_logic_typespec: , line:47:16, endln:47:16 |vpiName:vss @@ -60667,7 +60667,7 @@ design: (work@oh_fifo_async) |vpiNet: \_logic_net: (work@oh_fifo_async.vdd), line:48:16, endln:48:19 |vpiParent: - \_module: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 + \_module_inst: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 |vpiTypespec: \_logic_typespec: , line:48:16, endln:48:16 |vpiName:vdd @@ -60675,7 +60675,7 @@ design: (work@oh_fifo_async) |vpiNet: \_logic_net: (work@oh_fifo_async.vddio), line:49:16, endln:49:21 |vpiParent: - \_module: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 + \_module_inst: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 |vpiTypespec: \_logic_typespec: , line:49:16, endln:49:16 |vpiName:vddio @@ -60683,7 +60683,7 @@ design: (work@oh_fifo_async) |vpiNet: \_logic_net: (work@oh_fifo_async.memconfig), line:50:21, endln:50:30 |vpiParent: - \_module: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 + \_module_inst: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 |vpiTypespec: \_logic_typespec: , line:50:11, endln:50:16 |vpiRange: @@ -60709,7 +60709,7 @@ design: (work@oh_fifo_async) |vpiNet: \_logic_net: (work@oh_fifo_async.memrepair), line:51:21, endln:51:30 |vpiParent: - \_module: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 + \_module_inst: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 |vpiTypespec: \_logic_typespec: , line:51:11, endln:51:16 |vpiRange: @@ -60735,7 +60735,7 @@ design: (work@oh_fifo_async) |vpiNet: \_logic_net: (work@oh_fifo_async.wr_addr), line:55:17, endln:55:24 |vpiParent: - \_module: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 + \_module_inst: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 |vpiTypespec: \_logic_typespec: , line:55:4, endln:55:14 |vpiRange: @@ -60762,7 +60762,7 @@ design: (work@oh_fifo_async) |vpiNet: \_logic_net: (work@oh_fifo_async.rd_addr), line:56:17, endln:56:24 |vpiParent: - \_module: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 + \_module_inst: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 |vpiTypespec: \_logic_typespec: , line:56:4, endln:56:14 |vpiRange: @@ -60789,7 +60789,7 @@ design: (work@oh_fifo_async) |vpiNet: \_logic_net: (work@oh_fifo_async.wr_addr_gray), line:57:18, endln:57:30 |vpiParent: - \_module: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 + \_module_inst: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 |vpiTypespec: \_logic_typespec: , line:57:4, endln:57:15 |vpiRange: @@ -60816,7 +60816,7 @@ design: (work@oh_fifo_async) |vpiNet: \_logic_net: (work@oh_fifo_async.wr_addr_gray_sync), line:58:18, endln:58:35 |vpiParent: - \_module: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 + \_module_inst: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 |vpiTypespec: \_logic_typespec: , line:58:4, endln:58:15 |vpiRange: @@ -60843,7 +60843,7 @@ design: (work@oh_fifo_async) |vpiNet: \_logic_net: (work@oh_fifo_async.rd_addr_gray), line:59:18, endln:59:30 |vpiParent: - \_module: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 + \_module_inst: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 |vpiTypespec: \_logic_typespec: , line:59:4, endln:59:15 |vpiRange: @@ -60870,7 +60870,7 @@ design: (work@oh_fifo_async) |vpiNet: \_logic_net: (work@oh_fifo_async.rd_addr_gray_sync), line:60:18, endln:60:35 |vpiParent: - \_module: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 + \_module_inst: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 |vpiTypespec: \_logic_typespec: , line:60:4, endln:60:15 |vpiRange: @@ -60897,7 +60897,7 @@ design: (work@oh_fifo_async) |vpiNet: \_logic_net: (work@oh_fifo_async.rd_addr_sync), line:61:18, endln:61:30 |vpiParent: - \_module: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 + \_module_inst: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 |vpiTypespec: \_logic_typespec: , line:61:4, endln:61:15 |vpiRange: @@ -60924,7 +60924,7 @@ design: (work@oh_fifo_async) |vpiNet: \_logic_net: (work@oh_fifo_async.fifo_write), line:62:11, endln:62:21 |vpiParent: - \_module: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 + \_module_inst: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 |vpiTypespec: \_logic_typespec: , line:62:4, endln:62:8 |vpiName:fifo_write @@ -60933,7 +60933,7 @@ design: (work@oh_fifo_async) |vpiNet: \_logic_net: (work@oh_fifo_async.rd_nreset), line:63:11, endln:63:20 |vpiParent: - \_module: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 + \_module_inst: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 |vpiTypespec: \_logic_typespec: , line:63:4, endln:63:8 |vpiName:rd_nreset @@ -60942,7 +60942,7 @@ design: (work@oh_fifo_async) |vpiNet: \_logic_net: (work@oh_fifo_async.wr_nreset), line:64:11, endln:64:20 |vpiParent: - \_module: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 + \_module_inst: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 |vpiTypespec: \_logic_typespec: , line:64:4, endln:64:8 |vpiName:wr_nreset @@ -60952,7 +60952,7 @@ design: (work@oh_fifo_async) |vpiPort: \_port: (nreset), line:23:16, endln:23:22 |vpiParent: - \_module: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 + \_module_inst: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 |vpiName:nreset |vpiDirection:1 |vpiLowConn: @@ -60966,11 +60966,11 @@ design: (work@oh_fifo_async) |vpiTypedef: \_logic_typespec: , line:23:16, endln:23:16 |vpiInstance: - \_module: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 + \_module_inst: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 |vpiPort: \_port: (wr_clk), line:25:16, endln:25:22 |vpiParent: - \_module: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 + \_module_inst: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 |vpiName:wr_clk |vpiDirection:1 |vpiLowConn: @@ -60984,11 +60984,11 @@ design: (work@oh_fifo_async) |vpiTypedef: \_logic_typespec: , line:25:16, endln:25:16 |vpiInstance: - \_module: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 + \_module_inst: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 |vpiPort: \_port: (wr_din), line:26:20, endln:26:26 |vpiParent: - \_module: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 + \_module_inst: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 |vpiName:wr_din |vpiDirection:1 |vpiLowConn: @@ -61022,11 +61022,11 @@ design: (work@oh_fifo_async) |UINT:0 |vpiConstType:9 |vpiInstance: - \_module: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 + \_module_inst: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 |vpiPort: \_port: (wr_en), line:27:16, endln:27:21 |vpiParent: - \_module: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 + \_module_inst: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 |vpiName:wr_en |vpiDirection:1 |vpiLowConn: @@ -61040,11 +61040,11 @@ design: (work@oh_fifo_async) |vpiTypedef: \_logic_typespec: , line:27:16, endln:27:16 |vpiInstance: - \_module: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 + \_module_inst: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 |vpiPort: \_port: (wr_full), line:28:17, endln:28:24 |vpiParent: - \_module: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 + \_module_inst: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 |vpiName:wr_full |vpiDirection:2 |vpiLowConn: @@ -61058,11 +61058,11 @@ design: (work@oh_fifo_async) |vpiTypedef: \_logic_typespec: , line:28:17, endln:28:17 |vpiInstance: - \_module: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 + \_module_inst: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 |vpiPort: \_port: (wr_almost_full), line:29:17, endln:29:31 |vpiParent: - \_module: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 + \_module_inst: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 |vpiName:wr_almost_full |vpiDirection:2 |vpiLowConn: @@ -61076,11 +61076,11 @@ design: (work@oh_fifo_async) |vpiTypedef: \_logic_typespec: , line:29:17, endln:29:17 |vpiInstance: - \_module: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 + \_module_inst: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 |vpiPort: \_port: (wr_prog_full), line:30:17, endln:30:29 |vpiParent: - \_module: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 + \_module_inst: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 |vpiName:wr_prog_full |vpiDirection:2 |vpiLowConn: @@ -61094,11 +61094,11 @@ design: (work@oh_fifo_async) |vpiTypedef: \_logic_typespec: , line:30:17, endln:30:17 |vpiInstance: - \_module: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 + \_module_inst: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 |vpiPort: \_port: (wr_count), line:31:21, endln:31:29 |vpiParent: - \_module: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 + \_module_inst: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 |vpiName:wr_count |vpiDirection:2 |vpiLowConn: @@ -61132,11 +61132,11 @@ design: (work@oh_fifo_async) |UINT:0 |vpiConstType:9 |vpiInstance: - \_module: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 + \_module_inst: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 |vpiPort: \_port: (rd_clk), line:33:16, endln:33:22 |vpiParent: - \_module: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 + \_module_inst: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 |vpiName:rd_clk |vpiDirection:1 |vpiLowConn: @@ -61150,11 +61150,11 @@ design: (work@oh_fifo_async) |vpiTypedef: \_logic_typespec: , line:33:16, endln:33:16 |vpiInstance: - \_module: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 + \_module_inst: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 |vpiPort: \_port: (rd_dout), line:34:20, endln:34:27 |vpiParent: - \_module: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 + \_module_inst: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 |vpiName:rd_dout |vpiDirection:2 |vpiLowConn: @@ -61188,11 +61188,11 @@ design: (work@oh_fifo_async) |UINT:0 |vpiConstType:9 |vpiInstance: - \_module: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 + \_module_inst: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 |vpiPort: \_port: (rd_en), line:35:16, endln:35:21 |vpiParent: - \_module: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 + \_module_inst: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 |vpiName:rd_en |vpiDirection:1 |vpiLowConn: @@ -61206,11 +61206,11 @@ design: (work@oh_fifo_async) |vpiTypedef: \_logic_typespec: , line:35:16, endln:35:16 |vpiInstance: - \_module: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 + \_module_inst: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 |vpiPort: \_port: (rd_empty), line:36:17, endln:36:25 |vpiParent: - \_module: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 + \_module_inst: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 |vpiName:rd_empty |vpiDirection:2 |vpiLowConn: @@ -61224,11 +61224,11 @@ design: (work@oh_fifo_async) |vpiTypedef: \_logic_typespec: , line:36:17, endln:36:17 |vpiInstance: - \_module: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 + \_module_inst: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 |vpiPort: \_port: (rd_count), line:37:21, endln:37:29 |vpiParent: - \_module: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 + \_module_inst: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 |vpiName:rd_count |vpiDirection:2 |vpiLowConn: @@ -61262,11 +61262,11 @@ design: (work@oh_fifo_async) |UINT:0 |vpiConstType:9 |vpiInstance: - \_module: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 + \_module_inst: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 |vpiPort: \_port: (bist_en), line:39:16, endln:39:23 |vpiParent: - \_module: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 + \_module_inst: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 |vpiName:bist_en |vpiDirection:1 |vpiLowConn: @@ -61280,11 +61280,11 @@ design: (work@oh_fifo_async) |vpiTypedef: \_logic_typespec: , line:39:16, endln:39:16 |vpiInstance: - \_module: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 + \_module_inst: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 |vpiPort: \_port: (bist_we), line:40:16, endln:40:23 |vpiParent: - \_module: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 + \_module_inst: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 |vpiName:bist_we |vpiDirection:1 |vpiLowConn: @@ -61298,11 +61298,11 @@ design: (work@oh_fifo_async) |vpiTypedef: \_logic_typespec: , line:40:16, endln:40:16 |vpiInstance: - \_module: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 + \_module_inst: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 |vpiPort: \_port: (bist_wem), line:41:20, endln:41:28 |vpiParent: - \_module: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 + \_module_inst: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 |vpiName:bist_wem |vpiDirection:1 |vpiLowConn: @@ -61336,11 +61336,11 @@ design: (work@oh_fifo_async) |UINT:0 |vpiConstType:9 |vpiInstance: - \_module: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 + \_module_inst: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 |vpiPort: \_port: (bist_addr), line:42:21, endln:42:30 |vpiParent: - \_module: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 + \_module_inst: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 |vpiName:bist_addr |vpiDirection:1 |vpiLowConn: @@ -61374,11 +61374,11 @@ design: (work@oh_fifo_async) |UINT:0 |vpiConstType:9 |vpiInstance: - \_module: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 + \_module_inst: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 |vpiPort: \_port: (bist_din), line:43:20, endln:43:28 |vpiParent: - \_module: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 + \_module_inst: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 |vpiName:bist_din |vpiDirection:1 |vpiLowConn: @@ -61412,11 +61412,11 @@ design: (work@oh_fifo_async) |UINT:0 |vpiConstType:9 |vpiInstance: - \_module: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 + \_module_inst: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 |vpiPort: \_port: (bist_dout), line:44:20, endln:44:29 |vpiParent: - \_module: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 + \_module_inst: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 |vpiName:bist_dout |vpiDirection:1 |vpiLowConn: @@ -61450,11 +61450,11 @@ design: (work@oh_fifo_async) |UINT:0 |vpiConstType:9 |vpiInstance: - \_module: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 + \_module_inst: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 |vpiPort: \_port: (shutdown), line:46:16, endln:46:24 |vpiParent: - \_module: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 + \_module_inst: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 |vpiName:shutdown |vpiDirection:1 |vpiLowConn: @@ -61468,11 +61468,11 @@ design: (work@oh_fifo_async) |vpiTypedef: \_logic_typespec: , line:46:16, endln:46:16 |vpiInstance: - \_module: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 + \_module_inst: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 |vpiPort: \_port: (vss), line:47:16, endln:47:19 |vpiParent: - \_module: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 + \_module_inst: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 |vpiName:vss |vpiDirection:1 |vpiLowConn: @@ -61486,11 +61486,11 @@ design: (work@oh_fifo_async) |vpiTypedef: \_logic_typespec: , line:47:16, endln:47:16 |vpiInstance: - \_module: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 + \_module_inst: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 |vpiPort: \_port: (vdd), line:48:16, endln:48:19 |vpiParent: - \_module: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 + \_module_inst: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 |vpiName:vdd |vpiDirection:1 |vpiLowConn: @@ -61504,11 +61504,11 @@ design: (work@oh_fifo_async) |vpiTypedef: \_logic_typespec: , line:48:16, endln:48:16 |vpiInstance: - \_module: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 + \_module_inst: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 |vpiPort: \_port: (vddio), line:49:16, endln:49:21 |vpiParent: - \_module: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 + \_module_inst: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 |vpiName:vddio |vpiDirection:1 |vpiLowConn: @@ -61522,11 +61522,11 @@ design: (work@oh_fifo_async) |vpiTypedef: \_logic_typespec: , line:49:16, endln:49:16 |vpiInstance: - \_module: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 + \_module_inst: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 |vpiPort: \_port: (memconfig), line:50:21, endln:50:30 |vpiParent: - \_module: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 + \_module_inst: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 |vpiName:memconfig |vpiDirection:1 |vpiLowConn: @@ -61560,11 +61560,11 @@ design: (work@oh_fifo_async) |UINT:0 |vpiConstType:9 |vpiInstance: - \_module: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 + \_module_inst: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 |vpiPort: \_port: (memrepair), line:51:21, endln:51:30 |vpiParent: - \_module: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 + \_module_inst: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 |vpiName:memrepair |vpiDirection:1 |vpiLowConn: @@ -61598,11 +61598,11 @@ design: (work@oh_fifo_async) |UINT:0 |vpiConstType:9 |vpiInstance: - \_module: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 + \_module_inst: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 |vpiProcess: \_always: , line:90:4, endln:94:47 |vpiParent: - \_module: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 + \_module_inst: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 |vpiStmt: \_event_control: , line:90:11, endln:90:51 |vpiParent: @@ -61760,7 +61760,7 @@ design: (work@oh_fifo_async) |vpiProcess: \_always: , line:100:4, endln:104:45 |vpiParent: - \_module: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 + \_module_inst: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 |vpiStmt: \_event_control: , line:100:11, endln:100:51 |vpiParent: @@ -61921,16 +61921,16 @@ design: (work@oh_fifo_async) |vpiRightRange: \_constant: , line:104:19, endln:104:20 |vpiAlwaysType:1 - |vpiModule: - \_module: work@oh_rsync (work@oh_fifo_async.wr_rsync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:72:4, endln:76:27 + |vpiModuleInst: + \_module_inst: work@oh_rsync (work@oh_fifo_async.wr_rsync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:72:4, endln:76:27 |vpiParent: - \_module: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 + \_module_inst: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 |vpiName:wr_rsync |vpiFullName:work@oh_fifo_async.wr_rsync |vpiParameter: \_parameter: (work@oh_fifo_async.wr_rsync.SYNCPIPE), line:9:15, endln:9:23 |vpiParent: - \_module: work@oh_rsync (work@oh_fifo_async.wr_rsync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:72:4, endln:76:27 + \_module_inst: work@oh_rsync (work@oh_fifo_async.wr_rsync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:72:4, endln:76:27 |UINT:2 |vpiTypespec: \_int_typespec: @@ -61941,7 +61941,7 @@ design: (work@oh_fifo_async) |vpiParameter: \_parameter: (work@oh_fifo_async.wr_rsync.SYN), line:10:15, endln:10:18 |vpiParent: - \_module: work@oh_rsync (work@oh_fifo_async.wr_rsync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:72:4, endln:76:27 + \_module_inst: work@oh_rsync (work@oh_fifo_async.wr_rsync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:72:4, endln:76:27 |STRING:TRUE |vpiTypespec: \_string_typespec: @@ -61952,7 +61952,7 @@ design: (work@oh_fifo_async) |vpiParameter: \_parameter: (work@oh_fifo_async.wr_rsync.TYPE), line:11:15, endln:11:19 |vpiParent: - \_module: work@oh_rsync (work@oh_fifo_async.wr_rsync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:72:4, endln:76:27 + \_module_inst: work@oh_rsync (work@oh_fifo_async.wr_rsync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:72:4, endln:76:27 |STRING:DEFAULT |vpiTypespec: \_string_typespec: @@ -61963,7 +61963,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:9:15, endln:9:27 |vpiParent: - \_module: work@oh_rsync (work@oh_fifo_async.wr_rsync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:72:4, endln:76:27 + \_module_inst: work@oh_rsync (work@oh_fifo_async.wr_rsync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:72:4, endln:76:27 |vpiOverriden:1 |vpiRhs: \_constant: , line:9:26, endln:9:27 @@ -61978,7 +61978,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:10:15, endln:10:32 |vpiParent: - \_module: work@oh_rsync (work@oh_fifo_async.wr_rsync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:72:4, endln:76:27 + \_module_inst: work@oh_rsync (work@oh_fifo_async.wr_rsync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:72:4, endln:76:27 |vpiOverriden:1 |vpiRhs: \_constant: , line:10:26, endln:10:32 @@ -61993,7 +61993,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:11:15, endln:11:35 |vpiParent: - \_module: work@oh_rsync (work@oh_fifo_async.wr_rsync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:72:4, endln:76:27 + \_module_inst: work@oh_rsync (work@oh_fifo_async.wr_rsync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:72:4, endln:76:27 |vpiRhs: \_constant: , line:11:26, endln:11:35 |vpiDecompile:DEFAULT @@ -62011,7 +62011,7 @@ design: (work@oh_fifo_async) |vpiNet: \_logic_net: (work@oh_fifo_async.wr_rsync.clk), line:14:12, endln:14:15 |vpiParent: - \_module: work@oh_rsync (work@oh_fifo_async.wr_rsync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:72:4, endln:76:27 + \_module_inst: work@oh_rsync (work@oh_fifo_async.wr_rsync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:72:4, endln:76:27 |vpiTypespec: \_logic_typespec: , line:14:12, endln:14:12 |vpiName:clk @@ -62019,7 +62019,7 @@ design: (work@oh_fifo_async) |vpiNet: \_logic_net: (work@oh_fifo_async.wr_rsync.nrst_in), line:15:12, endln:15:19 |vpiParent: - \_module: work@oh_rsync (work@oh_fifo_async.wr_rsync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:72:4, endln:76:27 + \_module_inst: work@oh_rsync (work@oh_fifo_async.wr_rsync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:72:4, endln:76:27 |vpiTypespec: \_logic_typespec: , line:15:12, endln:15:12 |vpiName:nrst_in @@ -62027,17 +62027,17 @@ design: (work@oh_fifo_async) |vpiNet: \_logic_net: (work@oh_fifo_async.wr_rsync.nrst_out), line:16:12, endln:16:20 |vpiParent: - \_module: work@oh_rsync (work@oh_fifo_async.wr_rsync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:72:4, endln:76:27 + \_module_inst: work@oh_rsync (work@oh_fifo_async.wr_rsync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:72:4, endln:76:27 |vpiTypespec: \_logic_typespec: , line:16:12, endln:16:12 |vpiName:nrst_out |vpiFullName:work@oh_fifo_async.wr_rsync.nrst_out |vpiInstance: - \_module: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 + \_module_inst: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 |vpiPort: \_port: (clk), line:14:12, endln:14:15 |vpiParent: - \_module: work@oh_rsync (work@oh_fifo_async.wr_rsync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:72:4, endln:76:27 + \_module_inst: work@oh_rsync (work@oh_fifo_async.wr_rsync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:72:4, endln:76:27 |vpiName:clk |vpiDirection:1 |vpiHighConn: @@ -62059,11 +62059,11 @@ design: (work@oh_fifo_async) |vpiTypedef: \_logic_typespec: , line:14:12, endln:14:12 |vpiInstance: - \_module: work@oh_rsync (work@oh_fifo_async.wr_rsync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:72:4, endln:76:27 + \_module_inst: work@oh_rsync (work@oh_fifo_async.wr_rsync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:72:4, endln:76:27 |vpiPort: \_port: (nrst_in), line:15:12, endln:15:19 |vpiParent: - \_module: work@oh_rsync (work@oh_fifo_async.wr_rsync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:72:4, endln:76:27 + \_module_inst: work@oh_rsync (work@oh_fifo_async.wr_rsync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:72:4, endln:76:27 |vpiName:nrst_in |vpiDirection:1 |vpiHighConn: @@ -62085,11 +62085,11 @@ design: (work@oh_fifo_async) |vpiTypedef: \_logic_typespec: , line:15:12, endln:15:12 |vpiInstance: - \_module: work@oh_rsync (work@oh_fifo_async.wr_rsync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:72:4, endln:76:27 + \_module_inst: work@oh_rsync (work@oh_fifo_async.wr_rsync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:72:4, endln:76:27 |vpiPort: \_port: (nrst_out), line:16:12, endln:16:20 |vpiParent: - \_module: work@oh_rsync (work@oh_fifo_async.wr_rsync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:72:4, endln:76:27 + \_module_inst: work@oh_rsync (work@oh_fifo_async.wr_rsync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:72:4, endln:76:27 |vpiName:nrst_out |vpiDirection:2 |vpiHighConn: @@ -62111,11 +62111,11 @@ design: (work@oh_fifo_async) |vpiTypedef: \_logic_typespec: , line:16:12, endln:16:12 |vpiInstance: - \_module: work@oh_rsync (work@oh_fifo_async.wr_rsync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:72:4, endln:76:27 + \_module_inst: work@oh_rsync (work@oh_fifo_async.wr_rsync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:72:4, endln:76:27 |vpiGenScopeArray: \_gen_scope_array: (work@oh_fifo_async.wr_rsync.genblk1), line:20:7, endln:38:5 |vpiParent: - \_module: work@oh_rsync (work@oh_fifo_async.wr_rsync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:72:4, endln:76:27 + \_module_inst: work@oh_rsync (work@oh_fifo_async.wr_rsync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:72:4, endln:76:27 |vpiName:genblk1 |vpiFullName:work@oh_fifo_async.wr_rsync.genblk1 |vpiGenScope: @@ -62417,16 +62417,16 @@ design: (work@oh_fifo_async) |vpiFullName:work@oh_fifo_async.wr_rsync.genblk1.nrst_out |vpiActual: \_logic_net: (work@oh_fifo_async.wr_rsync.nrst_out), line:16:12, endln:16:20 - |vpiModule: - \_module: work@oh_rsync (work@oh_fifo_async.rd_rsync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:78:4, endln:82:27 + |vpiModuleInst: + \_module_inst: work@oh_rsync (work@oh_fifo_async.rd_rsync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:78:4, endln:82:27 |vpiParent: - \_module: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 + \_module_inst: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 |vpiName:rd_rsync |vpiFullName:work@oh_fifo_async.rd_rsync |vpiParameter: \_parameter: (work@oh_fifo_async.rd_rsync.SYNCPIPE), line:9:15, endln:9:23 |vpiParent: - \_module: work@oh_rsync (work@oh_fifo_async.rd_rsync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:78:4, endln:82:27 + \_module_inst: work@oh_rsync (work@oh_fifo_async.rd_rsync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:78:4, endln:82:27 |UINT:2 |vpiTypespec: \_int_typespec: @@ -62437,7 +62437,7 @@ design: (work@oh_fifo_async) |vpiParameter: \_parameter: (work@oh_fifo_async.rd_rsync.SYN), line:10:15, endln:10:18 |vpiParent: - \_module: work@oh_rsync (work@oh_fifo_async.rd_rsync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:78:4, endln:82:27 + \_module_inst: work@oh_rsync (work@oh_fifo_async.rd_rsync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:78:4, endln:82:27 |STRING:TRUE |vpiTypespec: \_string_typespec: @@ -62448,7 +62448,7 @@ design: (work@oh_fifo_async) |vpiParameter: \_parameter: (work@oh_fifo_async.rd_rsync.TYPE), line:11:15, endln:11:19 |vpiParent: - \_module: work@oh_rsync (work@oh_fifo_async.rd_rsync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:78:4, endln:82:27 + \_module_inst: work@oh_rsync (work@oh_fifo_async.rd_rsync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:78:4, endln:82:27 |STRING:DEFAULT |vpiTypespec: \_string_typespec: @@ -62459,7 +62459,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:9:15, endln:9:27 |vpiParent: - \_module: work@oh_rsync (work@oh_fifo_async.rd_rsync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:78:4, endln:82:27 + \_module_inst: work@oh_rsync (work@oh_fifo_async.rd_rsync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:78:4, endln:82:27 |vpiOverriden:1 |vpiRhs: \_constant: , line:9:26, endln:9:27 @@ -62474,7 +62474,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:10:15, endln:10:32 |vpiParent: - \_module: work@oh_rsync (work@oh_fifo_async.rd_rsync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:78:4, endln:82:27 + \_module_inst: work@oh_rsync (work@oh_fifo_async.rd_rsync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:78:4, endln:82:27 |vpiOverriden:1 |vpiRhs: \_constant: , line:10:26, endln:10:32 @@ -62489,7 +62489,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:11:15, endln:11:35 |vpiParent: - \_module: work@oh_rsync (work@oh_fifo_async.rd_rsync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:78:4, endln:82:27 + \_module_inst: work@oh_rsync (work@oh_fifo_async.rd_rsync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:78:4, endln:82:27 |vpiRhs: \_constant: , line:11:26, endln:11:35 |vpiDecompile:DEFAULT @@ -62507,7 +62507,7 @@ design: (work@oh_fifo_async) |vpiNet: \_logic_net: (work@oh_fifo_async.rd_rsync.clk), line:14:12, endln:14:15 |vpiParent: - \_module: work@oh_rsync (work@oh_fifo_async.rd_rsync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:78:4, endln:82:27 + \_module_inst: work@oh_rsync (work@oh_fifo_async.rd_rsync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:78:4, endln:82:27 |vpiTypespec: \_logic_typespec: , line:14:12, endln:14:12 |vpiName:clk @@ -62515,7 +62515,7 @@ design: (work@oh_fifo_async) |vpiNet: \_logic_net: (work@oh_fifo_async.rd_rsync.nrst_in), line:15:12, endln:15:19 |vpiParent: - \_module: work@oh_rsync (work@oh_fifo_async.rd_rsync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:78:4, endln:82:27 + \_module_inst: work@oh_rsync (work@oh_fifo_async.rd_rsync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:78:4, endln:82:27 |vpiTypespec: \_logic_typespec: , line:15:12, endln:15:12 |vpiName:nrst_in @@ -62523,17 +62523,17 @@ design: (work@oh_fifo_async) |vpiNet: \_logic_net: (work@oh_fifo_async.rd_rsync.nrst_out), line:16:12, endln:16:20 |vpiParent: - \_module: work@oh_rsync (work@oh_fifo_async.rd_rsync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:78:4, endln:82:27 + \_module_inst: work@oh_rsync (work@oh_fifo_async.rd_rsync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:78:4, endln:82:27 |vpiTypespec: \_logic_typespec: , line:16:12, endln:16:12 |vpiName:nrst_out |vpiFullName:work@oh_fifo_async.rd_rsync.nrst_out |vpiInstance: - \_module: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 + \_module_inst: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 |vpiPort: \_port: (clk), line:14:12, endln:14:15 |vpiParent: - \_module: work@oh_rsync (work@oh_fifo_async.rd_rsync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:78:4, endln:82:27 + \_module_inst: work@oh_rsync (work@oh_fifo_async.rd_rsync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:78:4, endln:82:27 |vpiName:clk |vpiDirection:1 |vpiHighConn: @@ -62555,11 +62555,11 @@ design: (work@oh_fifo_async) |vpiTypedef: \_logic_typespec: , line:14:12, endln:14:12 |vpiInstance: - \_module: work@oh_rsync (work@oh_fifo_async.rd_rsync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:78:4, endln:82:27 + \_module_inst: work@oh_rsync (work@oh_fifo_async.rd_rsync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:78:4, endln:82:27 |vpiPort: \_port: (nrst_in), line:15:12, endln:15:19 |vpiParent: - \_module: work@oh_rsync (work@oh_fifo_async.rd_rsync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:78:4, endln:82:27 + \_module_inst: work@oh_rsync (work@oh_fifo_async.rd_rsync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:78:4, endln:82:27 |vpiName:nrst_in |vpiDirection:1 |vpiHighConn: @@ -62581,11 +62581,11 @@ design: (work@oh_fifo_async) |vpiTypedef: \_logic_typespec: , line:15:12, endln:15:12 |vpiInstance: - \_module: work@oh_rsync (work@oh_fifo_async.rd_rsync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:78:4, endln:82:27 + \_module_inst: work@oh_rsync (work@oh_fifo_async.rd_rsync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:78:4, endln:82:27 |vpiPort: \_port: (nrst_out), line:16:12, endln:16:20 |vpiParent: - \_module: work@oh_rsync (work@oh_fifo_async.rd_rsync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:78:4, endln:82:27 + \_module_inst: work@oh_rsync (work@oh_fifo_async.rd_rsync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:78:4, endln:82:27 |vpiName:nrst_out |vpiDirection:2 |vpiHighConn: @@ -62607,11 +62607,11 @@ design: (work@oh_fifo_async) |vpiTypedef: \_logic_typespec: , line:16:12, endln:16:12 |vpiInstance: - \_module: work@oh_rsync (work@oh_fifo_async.rd_rsync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:78:4, endln:82:27 + \_module_inst: work@oh_rsync (work@oh_fifo_async.rd_rsync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:78:4, endln:82:27 |vpiGenScopeArray: \_gen_scope_array: (work@oh_fifo_async.rd_rsync.genblk1), line:20:7, endln:38:5 |vpiParent: - \_module: work@oh_rsync (work@oh_fifo_async.rd_rsync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:78:4, endln:82:27 + \_module_inst: work@oh_rsync (work@oh_fifo_async.rd_rsync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:78:4, endln:82:27 |vpiName:genblk1 |vpiFullName:work@oh_fifo_async.rd_rsync.genblk1 |vpiGenScope: @@ -62913,16 +62913,16 @@ design: (work@oh_fifo_async) |vpiFullName:work@oh_fifo_async.rd_rsync.genblk1.nrst_out |vpiActual: \_logic_net: (work@oh_fifo_async.rd_rsync.nrst_out), line:16:12, endln:16:20 - |vpiModule: - \_module: work@oh_bin2gray (work@oh_fifo_async.wr_bin2gray), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:114:4, endln:116:24 + |vpiModuleInst: + \_module_inst: work@oh_bin2gray (work@oh_fifo_async.wr_bin2gray), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:114:4, endln:116:24 |vpiParent: - \_module: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 + \_module_inst: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 |vpiName:wr_bin2gray |vpiFullName:work@oh_fifo_async.wr_bin2gray |vpiVariables: \_integer_var: (work@oh_fifo_async.wr_bin2gray.i), line:19:16, endln:19:17 |vpiParent: - \_module: work@oh_bin2gray (work@oh_fifo_async.wr_bin2gray), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:114:4, endln:116:24 + \_module_inst: work@oh_bin2gray (work@oh_fifo_async.wr_bin2gray), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:114:4, endln:116:24 |vpiTypespec: \_integer_typespec: , line:19:4, endln:19:11 |vpiSigned:1 @@ -62932,7 +62932,7 @@ design: (work@oh_fifo_async) |vpiParameter: \_parameter: (work@oh_fifo_async.wr_bin2gray.N), line:9:15, endln:9:16 |vpiParent: - \_module: work@oh_bin2gray (work@oh_fifo_async.wr_bin2gray), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:114:4, endln:116:24 + \_module_inst: work@oh_bin2gray (work@oh_fifo_async.wr_bin2gray), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:114:4, endln:116:24 |UINT:32 |vpiTypespec: \_int_typespec: @@ -62943,7 +62943,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:9:15, endln:9:21 |vpiParent: - \_module: work@oh_bin2gray (work@oh_fifo_async.wr_bin2gray), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:114:4, endln:116:24 + \_module_inst: work@oh_bin2gray (work@oh_fifo_async.wr_bin2gray), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:114:4, endln:116:24 |vpiOverriden:1 |vpiRhs: \_constant: , line:9:19, endln:9:21 @@ -62962,7 +62962,7 @@ design: (work@oh_fifo_async) |vpiNet: \_logic_net: (work@oh_fifo_async.wr_bin2gray.in), line:12:20, endln:12:22 |vpiParent: - \_module: work@oh_bin2gray (work@oh_fifo_async.wr_bin2gray), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:114:4, endln:116:24 + \_module_inst: work@oh_bin2gray (work@oh_fifo_async.wr_bin2gray), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:114:4, endln:116:24 |vpiTypespec: \_logic_typespec: , line:12:11, endln:12:18 |vpiRange: @@ -62988,7 +62988,7 @@ design: (work@oh_fifo_async) |vpiNet: \_logic_net: (work@oh_fifo_async.wr_bin2gray.out), line:13:20, endln:13:23 |vpiParent: - \_module: work@oh_bin2gray (work@oh_fifo_async.wr_bin2gray), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:114:4, endln:116:24 + \_module_inst: work@oh_bin2gray (work@oh_fifo_async.wr_bin2gray), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:114:4, endln:116:24 |vpiTypespec: \_logic_typespec: , line:13:12, endln:13:19 |vpiRange: @@ -63014,7 +63014,7 @@ design: (work@oh_fifo_async) |vpiNet: \_logic_net: (work@oh_fifo_async.wr_bin2gray.gray), line:16:20, endln:16:24 |vpiParent: - \_module: work@oh_bin2gray (work@oh_fifo_async.wr_bin2gray), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:114:4, endln:116:24 + \_module_inst: work@oh_bin2gray (work@oh_fifo_async.wr_bin2gray), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:114:4, endln:116:24 |vpiTypespec: \_logic_typespec: , line:16:4, endln:16:15 |vpiRange: @@ -63041,7 +63041,7 @@ design: (work@oh_fifo_async) |vpiNet: \_logic_net: (work@oh_fifo_async.wr_bin2gray.bin), line:17:20, endln:17:23 |vpiParent: - \_module: work@oh_bin2gray (work@oh_fifo_async.wr_bin2gray), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:114:4, endln:116:24 + \_module_inst: work@oh_bin2gray (work@oh_fifo_async.wr_bin2gray), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:114:4, endln:116:24 |vpiTypespec: \_logic_typespec: , line:17:4, endln:17:16 |vpiRange: @@ -63066,11 +63066,11 @@ design: (work@oh_fifo_async) |vpiFullName:work@oh_fifo_async.wr_bin2gray.bin |vpiNetType:1 |vpiInstance: - \_module: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 + \_module_inst: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 |vpiPort: \_port: (in), line:12:20, endln:12:22 |vpiParent: - \_module: work@oh_bin2gray (work@oh_fifo_async.wr_bin2gray), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:114:4, endln:116:24 + \_module_inst: work@oh_bin2gray (work@oh_fifo_async.wr_bin2gray), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:114:4, endln:116:24 |vpiName:in |vpiDirection:1 |vpiHighConn: @@ -63128,11 +63128,11 @@ design: (work@oh_fifo_async) |UINT:0 |vpiConstType:9 |vpiInstance: - \_module: work@oh_bin2gray (work@oh_fifo_async.wr_bin2gray), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:114:4, endln:116:24 + \_module_inst: work@oh_bin2gray (work@oh_fifo_async.wr_bin2gray), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:114:4, endln:116:24 |vpiPort: \_port: (out), line:13:20, endln:13:23 |vpiParent: - \_module: work@oh_bin2gray (work@oh_fifo_async.wr_bin2gray), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:114:4, endln:116:24 + \_module_inst: work@oh_bin2gray (work@oh_fifo_async.wr_bin2gray), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:114:4, endln:116:24 |vpiName:out |vpiDirection:2 |vpiHighConn: @@ -63190,11 +63190,11 @@ design: (work@oh_fifo_async) |UINT:0 |vpiConstType:9 |vpiInstance: - \_module: work@oh_bin2gray (work@oh_fifo_async.wr_bin2gray), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:114:4, endln:116:24 + \_module_inst: work@oh_bin2gray (work@oh_fifo_async.wr_bin2gray), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:114:4, endln:116:24 |vpiProcess: \_always: , line:24:4, endln:29:9 |vpiParent: - \_module: work@oh_bin2gray (work@oh_fifo_async.wr_bin2gray), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:114:4, endln:116:24 + \_module_inst: work@oh_bin2gray (work@oh_fifo_async.wr_bin2gray), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:114:4, endln:116:24 |vpiStmt: \_event_control: , line:24:11, endln:24:13 |vpiParent: @@ -63432,7 +63432,7 @@ design: (work@oh_fifo_async) |vpiContAssign: \_cont_assign: , line:21:11, endln:21:34 |vpiParent: - \_module: work@oh_bin2gray (work@oh_fifo_async.wr_bin2gray), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:114:4, endln:116:24 + \_module_inst: work@oh_bin2gray (work@oh_fifo_async.wr_bin2gray), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:114:4, endln:116:24 |vpiRhs: \_part_select: , line:21:25, endln:21:34 |vpiParent: @@ -63494,7 +63494,7 @@ design: (work@oh_fifo_async) |vpiContAssign: \_cont_assign: , line:22:11, endln:22:36 |vpiParent: - \_module: work@oh_bin2gray (work@oh_fifo_async.wr_bin2gray), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:114:4, endln:116:24 + \_module_inst: work@oh_bin2gray (work@oh_fifo_async.wr_bin2gray), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:114:4, endln:116:24 |vpiRhs: \_part_select: , line:22:25, endln:22:36 |vpiParent: @@ -63553,16 +63553,16 @@ design: (work@oh_fifo_async) \_constant: , line:22:17, endln:22:18 |vpiRightRange: \_constant: , line:22:19, endln:22:20 - |vpiModule: - \_module: work@oh_dsync (work@oh_fifo_async.wr_sync[0]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:119:4, endln:124:35 + |vpiModuleInst: + \_module_inst: work@oh_dsync (work@oh_fifo_async.wr_sync[0]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:119:4, endln:124:35 |vpiParent: - \_module: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 + \_module_inst: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 |vpiName:wr_sync[0] |vpiFullName:work@oh_fifo_async.wr_sync[0] |vpiParameter: \_parameter: (work@oh_fifo_async.wr_sync[0].SYNCPIPE), line:9:15, endln:9:23 |vpiParent: - \_module: work@oh_dsync (work@oh_fifo_async.wr_sync[0]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:119:4, endln:124:35 + \_module_inst: work@oh_dsync (work@oh_fifo_async.wr_sync[0]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:119:4, endln:124:35 |UINT:2 |vpiTypespec: \_int_typespec: @@ -63573,7 +63573,7 @@ design: (work@oh_fifo_async) |vpiParameter: \_parameter: (work@oh_fifo_async.wr_sync[0].DELAY), line:10:15, endln:10:20 |vpiParent: - \_module: work@oh_dsync (work@oh_fifo_async.wr_sync[0]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:119:4, endln:124:35 + \_module_inst: work@oh_dsync (work@oh_fifo_async.wr_sync[0]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:119:4, endln:124:35 |UINT:0 |vpiTypespec: \_int_typespec: @@ -63584,7 +63584,7 @@ design: (work@oh_fifo_async) |vpiParameter: \_parameter: (work@oh_fifo_async.wr_sync[0].SYN), line:11:15, endln:11:18 |vpiParent: - \_module: work@oh_dsync (work@oh_fifo_async.wr_sync[0]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:119:4, endln:124:35 + \_module_inst: work@oh_dsync (work@oh_fifo_async.wr_sync[0]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:119:4, endln:124:35 |STRING:TRUE |vpiTypespec: \_string_typespec: @@ -63595,7 +63595,7 @@ design: (work@oh_fifo_async) |vpiParameter: \_parameter: (work@oh_fifo_async.wr_sync[0].TYPE), line:12:15, endln:12:19 |vpiParent: - \_module: work@oh_dsync (work@oh_fifo_async.wr_sync[0]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:119:4, endln:124:35 + \_module_inst: work@oh_dsync (work@oh_fifo_async.wr_sync[0]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:119:4, endln:124:35 |STRING:DEFAULT |vpiTypespec: \_string_typespec: @@ -63606,7 +63606,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:9:15, endln:9:27 |vpiParent: - \_module: work@oh_dsync (work@oh_fifo_async.wr_sync[0]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:119:4, endln:124:35 + \_module_inst: work@oh_dsync (work@oh_fifo_async.wr_sync[0]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:119:4, endln:124:35 |vpiOverriden:1 |vpiRhs: \_constant: , line:9:26, endln:9:27 @@ -63621,7 +63621,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:10:15, endln:10:27 |vpiParent: - \_module: work@oh_dsync (work@oh_fifo_async.wr_sync[0]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:119:4, endln:124:35 + \_module_inst: work@oh_dsync (work@oh_fifo_async.wr_sync[0]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:119:4, endln:124:35 |vpiRhs: \_constant: , line:10:26, endln:10:27 |vpiDecompile:0 @@ -63635,7 +63635,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:11:15, endln:11:32 |vpiParent: - \_module: work@oh_dsync (work@oh_fifo_async.wr_sync[0]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:119:4, endln:124:35 + \_module_inst: work@oh_dsync (work@oh_fifo_async.wr_sync[0]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:119:4, endln:124:35 |vpiOverriden:1 |vpiRhs: \_constant: , line:11:26, endln:11:32 @@ -63650,7 +63650,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:12:15, endln:12:35 |vpiParent: - \_module: work@oh_dsync (work@oh_fifo_async.wr_sync[0]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:119:4, endln:124:35 + \_module_inst: work@oh_dsync (work@oh_fifo_async.wr_sync[0]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:119:4, endln:124:35 |vpiRhs: \_constant: , line:12:26, endln:12:35 |vpiDecompile:DEFAULT @@ -63668,7 +63668,7 @@ design: (work@oh_fifo_async) |vpiNet: \_logic_net: (work@oh_fifo_async.wr_sync[0].clk), line:15:12, endln:15:15 |vpiParent: - \_module: work@oh_dsync (work@oh_fifo_async.wr_sync[0]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:119:4, endln:124:35 + \_module_inst: work@oh_dsync (work@oh_fifo_async.wr_sync[0]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:119:4, endln:124:35 |vpiTypespec: \_logic_typespec: , line:15:12, endln:15:12 |vpiName:clk @@ -63676,7 +63676,7 @@ design: (work@oh_fifo_async) |vpiNet: \_logic_net: (work@oh_fifo_async.wr_sync[0].nreset), line:16:12, endln:16:18 |vpiParent: - \_module: work@oh_dsync (work@oh_fifo_async.wr_sync[0]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:119:4, endln:124:35 + \_module_inst: work@oh_dsync (work@oh_fifo_async.wr_sync[0]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:119:4, endln:124:35 |vpiTypespec: \_logic_typespec: , line:16:12, endln:16:12 |vpiName:nreset @@ -63684,7 +63684,7 @@ design: (work@oh_fifo_async) |vpiNet: \_logic_net: (work@oh_fifo_async.wr_sync[0].din), line:17:12, endln:17:15 |vpiParent: - \_module: work@oh_dsync (work@oh_fifo_async.wr_sync[0]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:119:4, endln:124:35 + \_module_inst: work@oh_dsync (work@oh_fifo_async.wr_sync[0]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:119:4, endln:124:35 |vpiTypespec: \_logic_typespec: , line:17:12, endln:17:12 |vpiName:din @@ -63692,17 +63692,17 @@ design: (work@oh_fifo_async) |vpiNet: \_logic_net: (work@oh_fifo_async.wr_sync[0].dout), line:18:12, endln:18:16 |vpiParent: - \_module: work@oh_dsync (work@oh_fifo_async.wr_sync[0]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:119:4, endln:124:35 + \_module_inst: work@oh_dsync (work@oh_fifo_async.wr_sync[0]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:119:4, endln:124:35 |vpiTypespec: \_logic_typespec: , line:18:12, endln:18:12 |vpiName:dout |vpiFullName:work@oh_fifo_async.wr_sync[0].dout |vpiInstance: - \_module: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 + \_module_inst: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 |vpiPort: \_port: (clk), line:15:12, endln:15:15 |vpiParent: - \_module: work@oh_dsync (work@oh_fifo_async.wr_sync[0]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:119:4, endln:124:35 + \_module_inst: work@oh_dsync (work@oh_fifo_async.wr_sync[0]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:119:4, endln:124:35 |vpiName:clk |vpiDirection:1 |vpiHighConn: @@ -63724,11 +63724,11 @@ design: (work@oh_fifo_async) |vpiTypedef: \_logic_typespec: , line:15:12, endln:15:12 |vpiInstance: - \_module: work@oh_dsync (work@oh_fifo_async.wr_sync[0]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:119:4, endln:124:35 + \_module_inst: work@oh_dsync (work@oh_fifo_async.wr_sync[0]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:119:4, endln:124:35 |vpiPort: \_port: (nreset), line:16:12, endln:16:18 |vpiParent: - \_module: work@oh_dsync (work@oh_fifo_async.wr_sync[0]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:119:4, endln:124:35 + \_module_inst: work@oh_dsync (work@oh_fifo_async.wr_sync[0]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:119:4, endln:124:35 |vpiName:nreset |vpiDirection:1 |vpiHighConn: @@ -63750,11 +63750,11 @@ design: (work@oh_fifo_async) |vpiTypedef: \_logic_typespec: , line:16:12, endln:16:12 |vpiInstance: - \_module: work@oh_dsync (work@oh_fifo_async.wr_sync[0]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:119:4, endln:124:35 + \_module_inst: work@oh_dsync (work@oh_fifo_async.wr_sync[0]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:119:4, endln:124:35 |vpiPort: \_port: (din), line:17:12, endln:17:15 |vpiParent: - \_module: work@oh_dsync (work@oh_fifo_async.wr_sync[0]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:119:4, endln:124:35 + \_module_inst: work@oh_dsync (work@oh_fifo_async.wr_sync[0]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:119:4, endln:124:35 |vpiName:din |vpiDirection:1 |vpiHighConn: @@ -63792,11 +63792,11 @@ design: (work@oh_fifo_async) |vpiTypedef: \_logic_typespec: , line:17:12, endln:17:12 |vpiInstance: - \_module: work@oh_dsync (work@oh_fifo_async.wr_sync[0]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:119:4, endln:124:35 + \_module_inst: work@oh_dsync (work@oh_fifo_async.wr_sync[0]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:119:4, endln:124:35 |vpiPort: \_port: (dout), line:18:12, endln:18:16 |vpiParent: - \_module: work@oh_dsync (work@oh_fifo_async.wr_sync[0]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:119:4, endln:124:35 + \_module_inst: work@oh_dsync (work@oh_fifo_async.wr_sync[0]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:119:4, endln:124:35 |vpiName:dout |vpiDirection:2 |vpiHighConn: @@ -63834,11 +63834,11 @@ design: (work@oh_fifo_async) |vpiTypedef: \_logic_typespec: , line:18:12, endln:18:12 |vpiInstance: - \_module: work@oh_dsync (work@oh_fifo_async.wr_sync[0]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:119:4, endln:124:35 + \_module_inst: work@oh_dsync (work@oh_fifo_async.wr_sync[0]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:119:4, endln:124:35 |vpiGenScopeArray: \_gen_scope_array: (work@oh_fifo_async.wr_sync[0].genblk1), line:22:7, endln:42:5 |vpiParent: - \_module: work@oh_dsync (work@oh_fifo_async.wr_sync[0]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:119:4, endln:124:35 + \_module_inst: work@oh_dsync (work@oh_fifo_async.wr_sync[0]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:119:4, endln:124:35 |vpiName:genblk1 |vpiFullName:work@oh_fifo_async.wr_sync[0].genblk1 |vpiGenScope: @@ -64180,16 +64180,16 @@ design: (work@oh_fifo_async) |vpiFullName:work@oh_fifo_async.wr_sync[0].genblk1.dout |vpiActual: \_logic_net: (work@oh_fifo_async.wr_sync[0].dout), line:18:12, endln:18:16 - |vpiModule: - \_module: work@oh_dsync (work@oh_fifo_async.wr_sync[1]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:119:4, endln:124:35 + |vpiModuleInst: + \_module_inst: work@oh_dsync (work@oh_fifo_async.wr_sync[1]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:119:4, endln:124:35 |vpiParent: - \_module: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 + \_module_inst: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 |vpiName:wr_sync[1] |vpiFullName:work@oh_fifo_async.wr_sync[1] |vpiParameter: \_parameter: (work@oh_fifo_async.wr_sync[1].SYNCPIPE), line:9:15, endln:9:23 |vpiParent: - \_module: work@oh_dsync (work@oh_fifo_async.wr_sync[1]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:119:4, endln:124:35 + \_module_inst: work@oh_dsync (work@oh_fifo_async.wr_sync[1]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:119:4, endln:124:35 |UINT:2 |vpiTypespec: \_int_typespec: @@ -64200,7 +64200,7 @@ design: (work@oh_fifo_async) |vpiParameter: \_parameter: (work@oh_fifo_async.wr_sync[1].DELAY), line:10:15, endln:10:20 |vpiParent: - \_module: work@oh_dsync (work@oh_fifo_async.wr_sync[1]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:119:4, endln:124:35 + \_module_inst: work@oh_dsync (work@oh_fifo_async.wr_sync[1]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:119:4, endln:124:35 |UINT:0 |vpiTypespec: \_int_typespec: @@ -64211,7 +64211,7 @@ design: (work@oh_fifo_async) |vpiParameter: \_parameter: (work@oh_fifo_async.wr_sync[1].SYN), line:11:15, endln:11:18 |vpiParent: - \_module: work@oh_dsync (work@oh_fifo_async.wr_sync[1]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:119:4, endln:124:35 + \_module_inst: work@oh_dsync (work@oh_fifo_async.wr_sync[1]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:119:4, endln:124:35 |STRING:TRUE |vpiTypespec: \_string_typespec: @@ -64222,7 +64222,7 @@ design: (work@oh_fifo_async) |vpiParameter: \_parameter: (work@oh_fifo_async.wr_sync[1].TYPE), line:12:15, endln:12:19 |vpiParent: - \_module: work@oh_dsync (work@oh_fifo_async.wr_sync[1]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:119:4, endln:124:35 + \_module_inst: work@oh_dsync (work@oh_fifo_async.wr_sync[1]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:119:4, endln:124:35 |STRING:DEFAULT |vpiTypespec: \_string_typespec: @@ -64233,7 +64233,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:9:15, endln:9:27 |vpiParent: - \_module: work@oh_dsync (work@oh_fifo_async.wr_sync[1]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:119:4, endln:124:35 + \_module_inst: work@oh_dsync (work@oh_fifo_async.wr_sync[1]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:119:4, endln:124:35 |vpiOverriden:1 |vpiRhs: \_constant: , line:9:26, endln:9:27 @@ -64248,7 +64248,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:10:15, endln:10:27 |vpiParent: - \_module: work@oh_dsync (work@oh_fifo_async.wr_sync[1]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:119:4, endln:124:35 + \_module_inst: work@oh_dsync (work@oh_fifo_async.wr_sync[1]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:119:4, endln:124:35 |vpiRhs: \_constant: , line:10:26, endln:10:27 |vpiDecompile:0 @@ -64262,7 +64262,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:11:15, endln:11:32 |vpiParent: - \_module: work@oh_dsync (work@oh_fifo_async.wr_sync[1]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:119:4, endln:124:35 + \_module_inst: work@oh_dsync (work@oh_fifo_async.wr_sync[1]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:119:4, endln:124:35 |vpiOverriden:1 |vpiRhs: \_constant: , line:11:26, endln:11:32 @@ -64277,7 +64277,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:12:15, endln:12:35 |vpiParent: - \_module: work@oh_dsync (work@oh_fifo_async.wr_sync[1]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:119:4, endln:124:35 + \_module_inst: work@oh_dsync (work@oh_fifo_async.wr_sync[1]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:119:4, endln:124:35 |vpiRhs: \_constant: , line:12:26, endln:12:35 |vpiDecompile:DEFAULT @@ -64295,7 +64295,7 @@ design: (work@oh_fifo_async) |vpiNet: \_logic_net: (work@oh_fifo_async.wr_sync[1].clk), line:15:12, endln:15:15 |vpiParent: - \_module: work@oh_dsync (work@oh_fifo_async.wr_sync[1]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:119:4, endln:124:35 + \_module_inst: work@oh_dsync (work@oh_fifo_async.wr_sync[1]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:119:4, endln:124:35 |vpiTypespec: \_logic_typespec: , line:15:12, endln:15:12 |vpiName:clk @@ -64303,7 +64303,7 @@ design: (work@oh_fifo_async) |vpiNet: \_logic_net: (work@oh_fifo_async.wr_sync[1].nreset), line:16:12, endln:16:18 |vpiParent: - \_module: work@oh_dsync (work@oh_fifo_async.wr_sync[1]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:119:4, endln:124:35 + \_module_inst: work@oh_dsync (work@oh_fifo_async.wr_sync[1]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:119:4, endln:124:35 |vpiTypespec: \_logic_typespec: , line:16:12, endln:16:12 |vpiName:nreset @@ -64311,7 +64311,7 @@ design: (work@oh_fifo_async) |vpiNet: \_logic_net: (work@oh_fifo_async.wr_sync[1].din), line:17:12, endln:17:15 |vpiParent: - \_module: work@oh_dsync (work@oh_fifo_async.wr_sync[1]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:119:4, endln:124:35 + \_module_inst: work@oh_dsync (work@oh_fifo_async.wr_sync[1]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:119:4, endln:124:35 |vpiTypespec: \_logic_typespec: , line:17:12, endln:17:12 |vpiName:din @@ -64319,17 +64319,17 @@ design: (work@oh_fifo_async) |vpiNet: \_logic_net: (work@oh_fifo_async.wr_sync[1].dout), line:18:12, endln:18:16 |vpiParent: - \_module: work@oh_dsync (work@oh_fifo_async.wr_sync[1]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:119:4, endln:124:35 + \_module_inst: work@oh_dsync (work@oh_fifo_async.wr_sync[1]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:119:4, endln:124:35 |vpiTypespec: \_logic_typespec: , line:18:12, endln:18:12 |vpiName:dout |vpiFullName:work@oh_fifo_async.wr_sync[1].dout |vpiInstance: - \_module: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 + \_module_inst: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 |vpiPort: \_port: (clk), line:15:12, endln:15:15 |vpiParent: - \_module: work@oh_dsync (work@oh_fifo_async.wr_sync[1]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:119:4, endln:124:35 + \_module_inst: work@oh_dsync (work@oh_fifo_async.wr_sync[1]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:119:4, endln:124:35 |vpiName:clk |vpiDirection:1 |vpiHighConn: @@ -64351,11 +64351,11 @@ design: (work@oh_fifo_async) |vpiTypedef: \_logic_typespec: , line:15:12, endln:15:12 |vpiInstance: - \_module: work@oh_dsync (work@oh_fifo_async.wr_sync[1]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:119:4, endln:124:35 + \_module_inst: work@oh_dsync (work@oh_fifo_async.wr_sync[1]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:119:4, endln:124:35 |vpiPort: \_port: (nreset), line:16:12, endln:16:18 |vpiParent: - \_module: work@oh_dsync (work@oh_fifo_async.wr_sync[1]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:119:4, endln:124:35 + \_module_inst: work@oh_dsync (work@oh_fifo_async.wr_sync[1]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:119:4, endln:124:35 |vpiName:nreset |vpiDirection:1 |vpiHighConn: @@ -64377,11 +64377,11 @@ design: (work@oh_fifo_async) |vpiTypedef: \_logic_typespec: , line:16:12, endln:16:12 |vpiInstance: - \_module: work@oh_dsync (work@oh_fifo_async.wr_sync[1]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:119:4, endln:124:35 + \_module_inst: work@oh_dsync (work@oh_fifo_async.wr_sync[1]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:119:4, endln:124:35 |vpiPort: \_port: (din), line:17:12, endln:17:15 |vpiParent: - \_module: work@oh_dsync (work@oh_fifo_async.wr_sync[1]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:119:4, endln:124:35 + \_module_inst: work@oh_dsync (work@oh_fifo_async.wr_sync[1]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:119:4, endln:124:35 |vpiName:din |vpiDirection:1 |vpiHighConn: @@ -64419,11 +64419,11 @@ design: (work@oh_fifo_async) |vpiTypedef: \_logic_typespec: , line:17:12, endln:17:12 |vpiInstance: - \_module: work@oh_dsync (work@oh_fifo_async.wr_sync[1]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:119:4, endln:124:35 + \_module_inst: work@oh_dsync (work@oh_fifo_async.wr_sync[1]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:119:4, endln:124:35 |vpiPort: \_port: (dout), line:18:12, endln:18:16 |vpiParent: - \_module: work@oh_dsync (work@oh_fifo_async.wr_sync[1]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:119:4, endln:124:35 + \_module_inst: work@oh_dsync (work@oh_fifo_async.wr_sync[1]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:119:4, endln:124:35 |vpiName:dout |vpiDirection:2 |vpiHighConn: @@ -64461,11 +64461,11 @@ design: (work@oh_fifo_async) |vpiTypedef: \_logic_typespec: , line:18:12, endln:18:12 |vpiInstance: - \_module: work@oh_dsync (work@oh_fifo_async.wr_sync[1]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:119:4, endln:124:35 + \_module_inst: work@oh_dsync (work@oh_fifo_async.wr_sync[1]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:119:4, endln:124:35 |vpiGenScopeArray: \_gen_scope_array: (work@oh_fifo_async.wr_sync[1].genblk1), line:22:7, endln:42:5 |vpiParent: - \_module: work@oh_dsync (work@oh_fifo_async.wr_sync[1]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:119:4, endln:124:35 + \_module_inst: work@oh_dsync (work@oh_fifo_async.wr_sync[1]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:119:4, endln:124:35 |vpiName:genblk1 |vpiFullName:work@oh_fifo_async.wr_sync[1].genblk1 |vpiGenScope: @@ -64807,16 +64807,16 @@ design: (work@oh_fifo_async) |vpiFullName:work@oh_fifo_async.wr_sync[1].genblk1.dout |vpiActual: \_logic_net: (work@oh_fifo_async.wr_sync[1].dout), line:18:12, endln:18:16 - |vpiModule: - \_module: work@oh_dsync (work@oh_fifo_async.wr_sync[2]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:119:4, endln:124:35 + |vpiModuleInst: + \_module_inst: work@oh_dsync (work@oh_fifo_async.wr_sync[2]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:119:4, endln:124:35 |vpiParent: - \_module: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 + \_module_inst: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 |vpiName:wr_sync[2] |vpiFullName:work@oh_fifo_async.wr_sync[2] |vpiParameter: \_parameter: (work@oh_fifo_async.wr_sync[2].SYNCPIPE), line:9:15, endln:9:23 |vpiParent: - \_module: work@oh_dsync (work@oh_fifo_async.wr_sync[2]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:119:4, endln:124:35 + \_module_inst: work@oh_dsync (work@oh_fifo_async.wr_sync[2]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:119:4, endln:124:35 |UINT:2 |vpiTypespec: \_int_typespec: @@ -64827,7 +64827,7 @@ design: (work@oh_fifo_async) |vpiParameter: \_parameter: (work@oh_fifo_async.wr_sync[2].DELAY), line:10:15, endln:10:20 |vpiParent: - \_module: work@oh_dsync (work@oh_fifo_async.wr_sync[2]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:119:4, endln:124:35 + \_module_inst: work@oh_dsync (work@oh_fifo_async.wr_sync[2]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:119:4, endln:124:35 |UINT:0 |vpiTypespec: \_int_typespec: @@ -64838,7 +64838,7 @@ design: (work@oh_fifo_async) |vpiParameter: \_parameter: (work@oh_fifo_async.wr_sync[2].SYN), line:11:15, endln:11:18 |vpiParent: - \_module: work@oh_dsync (work@oh_fifo_async.wr_sync[2]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:119:4, endln:124:35 + \_module_inst: work@oh_dsync (work@oh_fifo_async.wr_sync[2]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:119:4, endln:124:35 |STRING:TRUE |vpiTypespec: \_string_typespec: @@ -64849,7 +64849,7 @@ design: (work@oh_fifo_async) |vpiParameter: \_parameter: (work@oh_fifo_async.wr_sync[2].TYPE), line:12:15, endln:12:19 |vpiParent: - \_module: work@oh_dsync (work@oh_fifo_async.wr_sync[2]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:119:4, endln:124:35 + \_module_inst: work@oh_dsync (work@oh_fifo_async.wr_sync[2]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:119:4, endln:124:35 |STRING:DEFAULT |vpiTypespec: \_string_typespec: @@ -64860,7 +64860,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:9:15, endln:9:27 |vpiParent: - \_module: work@oh_dsync (work@oh_fifo_async.wr_sync[2]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:119:4, endln:124:35 + \_module_inst: work@oh_dsync (work@oh_fifo_async.wr_sync[2]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:119:4, endln:124:35 |vpiOverriden:1 |vpiRhs: \_constant: , line:9:26, endln:9:27 @@ -64875,7 +64875,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:10:15, endln:10:27 |vpiParent: - \_module: work@oh_dsync (work@oh_fifo_async.wr_sync[2]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:119:4, endln:124:35 + \_module_inst: work@oh_dsync (work@oh_fifo_async.wr_sync[2]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:119:4, endln:124:35 |vpiRhs: \_constant: , line:10:26, endln:10:27 |vpiDecompile:0 @@ -64889,7 +64889,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:11:15, endln:11:32 |vpiParent: - \_module: work@oh_dsync (work@oh_fifo_async.wr_sync[2]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:119:4, endln:124:35 + \_module_inst: work@oh_dsync (work@oh_fifo_async.wr_sync[2]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:119:4, endln:124:35 |vpiOverriden:1 |vpiRhs: \_constant: , line:11:26, endln:11:32 @@ -64904,7 +64904,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:12:15, endln:12:35 |vpiParent: - \_module: work@oh_dsync (work@oh_fifo_async.wr_sync[2]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:119:4, endln:124:35 + \_module_inst: work@oh_dsync (work@oh_fifo_async.wr_sync[2]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:119:4, endln:124:35 |vpiRhs: \_constant: , line:12:26, endln:12:35 |vpiDecompile:DEFAULT @@ -64922,7 +64922,7 @@ design: (work@oh_fifo_async) |vpiNet: \_logic_net: (work@oh_fifo_async.wr_sync[2].clk), line:15:12, endln:15:15 |vpiParent: - \_module: work@oh_dsync (work@oh_fifo_async.wr_sync[2]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:119:4, endln:124:35 + \_module_inst: work@oh_dsync (work@oh_fifo_async.wr_sync[2]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:119:4, endln:124:35 |vpiTypespec: \_logic_typespec: , line:15:12, endln:15:12 |vpiName:clk @@ -64930,7 +64930,7 @@ design: (work@oh_fifo_async) |vpiNet: \_logic_net: (work@oh_fifo_async.wr_sync[2].nreset), line:16:12, endln:16:18 |vpiParent: - \_module: work@oh_dsync (work@oh_fifo_async.wr_sync[2]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:119:4, endln:124:35 + \_module_inst: work@oh_dsync (work@oh_fifo_async.wr_sync[2]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:119:4, endln:124:35 |vpiTypespec: \_logic_typespec: , line:16:12, endln:16:12 |vpiName:nreset @@ -64938,7 +64938,7 @@ design: (work@oh_fifo_async) |vpiNet: \_logic_net: (work@oh_fifo_async.wr_sync[2].din), line:17:12, endln:17:15 |vpiParent: - \_module: work@oh_dsync (work@oh_fifo_async.wr_sync[2]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:119:4, endln:124:35 + \_module_inst: work@oh_dsync (work@oh_fifo_async.wr_sync[2]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:119:4, endln:124:35 |vpiTypespec: \_logic_typespec: , line:17:12, endln:17:12 |vpiName:din @@ -64946,17 +64946,17 @@ design: (work@oh_fifo_async) |vpiNet: \_logic_net: (work@oh_fifo_async.wr_sync[2].dout), line:18:12, endln:18:16 |vpiParent: - \_module: work@oh_dsync (work@oh_fifo_async.wr_sync[2]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:119:4, endln:124:35 + \_module_inst: work@oh_dsync (work@oh_fifo_async.wr_sync[2]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:119:4, endln:124:35 |vpiTypespec: \_logic_typespec: , line:18:12, endln:18:12 |vpiName:dout |vpiFullName:work@oh_fifo_async.wr_sync[2].dout |vpiInstance: - \_module: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 + \_module_inst: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 |vpiPort: \_port: (clk), line:15:12, endln:15:15 |vpiParent: - \_module: work@oh_dsync (work@oh_fifo_async.wr_sync[2]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:119:4, endln:124:35 + \_module_inst: work@oh_dsync (work@oh_fifo_async.wr_sync[2]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:119:4, endln:124:35 |vpiName:clk |vpiDirection:1 |vpiHighConn: @@ -64978,11 +64978,11 @@ design: (work@oh_fifo_async) |vpiTypedef: \_logic_typespec: , line:15:12, endln:15:12 |vpiInstance: - \_module: work@oh_dsync (work@oh_fifo_async.wr_sync[2]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:119:4, endln:124:35 + \_module_inst: work@oh_dsync (work@oh_fifo_async.wr_sync[2]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:119:4, endln:124:35 |vpiPort: \_port: (nreset), line:16:12, endln:16:18 |vpiParent: - \_module: work@oh_dsync (work@oh_fifo_async.wr_sync[2]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:119:4, endln:124:35 + \_module_inst: work@oh_dsync (work@oh_fifo_async.wr_sync[2]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:119:4, endln:124:35 |vpiName:nreset |vpiDirection:1 |vpiHighConn: @@ -65004,11 +65004,11 @@ design: (work@oh_fifo_async) |vpiTypedef: \_logic_typespec: , line:16:12, endln:16:12 |vpiInstance: - \_module: work@oh_dsync (work@oh_fifo_async.wr_sync[2]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:119:4, endln:124:35 + \_module_inst: work@oh_dsync (work@oh_fifo_async.wr_sync[2]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:119:4, endln:124:35 |vpiPort: \_port: (din), line:17:12, endln:17:15 |vpiParent: - \_module: work@oh_dsync (work@oh_fifo_async.wr_sync[2]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:119:4, endln:124:35 + \_module_inst: work@oh_dsync (work@oh_fifo_async.wr_sync[2]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:119:4, endln:124:35 |vpiName:din |vpiDirection:1 |vpiHighConn: @@ -65046,11 +65046,11 @@ design: (work@oh_fifo_async) |vpiTypedef: \_logic_typespec: , line:17:12, endln:17:12 |vpiInstance: - \_module: work@oh_dsync (work@oh_fifo_async.wr_sync[2]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:119:4, endln:124:35 + \_module_inst: work@oh_dsync (work@oh_fifo_async.wr_sync[2]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:119:4, endln:124:35 |vpiPort: \_port: (dout), line:18:12, endln:18:16 |vpiParent: - \_module: work@oh_dsync (work@oh_fifo_async.wr_sync[2]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:119:4, endln:124:35 + \_module_inst: work@oh_dsync (work@oh_fifo_async.wr_sync[2]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:119:4, endln:124:35 |vpiName:dout |vpiDirection:2 |vpiHighConn: @@ -65088,11 +65088,11 @@ design: (work@oh_fifo_async) |vpiTypedef: \_logic_typespec: , line:18:12, endln:18:12 |vpiInstance: - \_module: work@oh_dsync (work@oh_fifo_async.wr_sync[2]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:119:4, endln:124:35 + \_module_inst: work@oh_dsync (work@oh_fifo_async.wr_sync[2]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:119:4, endln:124:35 |vpiGenScopeArray: \_gen_scope_array: (work@oh_fifo_async.wr_sync[2].genblk1), line:22:7, endln:42:5 |vpiParent: - \_module: work@oh_dsync (work@oh_fifo_async.wr_sync[2]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:119:4, endln:124:35 + \_module_inst: work@oh_dsync (work@oh_fifo_async.wr_sync[2]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:119:4, endln:124:35 |vpiName:genblk1 |vpiFullName:work@oh_fifo_async.wr_sync[2].genblk1 |vpiGenScope: @@ -65434,16 +65434,16 @@ design: (work@oh_fifo_async) |vpiFullName:work@oh_fifo_async.wr_sync[2].genblk1.dout |vpiActual: \_logic_net: (work@oh_fifo_async.wr_sync[2].dout), line:18:12, endln:18:16 - |vpiModule: - \_module: work@oh_dsync (work@oh_fifo_async.wr_sync[3]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:119:4, endln:124:35 + |vpiModuleInst: + \_module_inst: work@oh_dsync (work@oh_fifo_async.wr_sync[3]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:119:4, endln:124:35 |vpiParent: - \_module: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 + \_module_inst: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 |vpiName:wr_sync[3] |vpiFullName:work@oh_fifo_async.wr_sync[3] |vpiParameter: \_parameter: (work@oh_fifo_async.wr_sync[3].SYNCPIPE), line:9:15, endln:9:23 |vpiParent: - \_module: work@oh_dsync (work@oh_fifo_async.wr_sync[3]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:119:4, endln:124:35 + \_module_inst: work@oh_dsync (work@oh_fifo_async.wr_sync[3]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:119:4, endln:124:35 |UINT:2 |vpiTypespec: \_int_typespec: @@ -65454,7 +65454,7 @@ design: (work@oh_fifo_async) |vpiParameter: \_parameter: (work@oh_fifo_async.wr_sync[3].DELAY), line:10:15, endln:10:20 |vpiParent: - \_module: work@oh_dsync (work@oh_fifo_async.wr_sync[3]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:119:4, endln:124:35 + \_module_inst: work@oh_dsync (work@oh_fifo_async.wr_sync[3]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:119:4, endln:124:35 |UINT:0 |vpiTypespec: \_int_typespec: @@ -65465,7 +65465,7 @@ design: (work@oh_fifo_async) |vpiParameter: \_parameter: (work@oh_fifo_async.wr_sync[3].SYN), line:11:15, endln:11:18 |vpiParent: - \_module: work@oh_dsync (work@oh_fifo_async.wr_sync[3]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:119:4, endln:124:35 + \_module_inst: work@oh_dsync (work@oh_fifo_async.wr_sync[3]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:119:4, endln:124:35 |STRING:TRUE |vpiTypespec: \_string_typespec: @@ -65476,7 +65476,7 @@ design: (work@oh_fifo_async) |vpiParameter: \_parameter: (work@oh_fifo_async.wr_sync[3].TYPE), line:12:15, endln:12:19 |vpiParent: - \_module: work@oh_dsync (work@oh_fifo_async.wr_sync[3]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:119:4, endln:124:35 + \_module_inst: work@oh_dsync (work@oh_fifo_async.wr_sync[3]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:119:4, endln:124:35 |STRING:DEFAULT |vpiTypespec: \_string_typespec: @@ -65487,7 +65487,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:9:15, endln:9:27 |vpiParent: - \_module: work@oh_dsync (work@oh_fifo_async.wr_sync[3]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:119:4, endln:124:35 + \_module_inst: work@oh_dsync (work@oh_fifo_async.wr_sync[3]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:119:4, endln:124:35 |vpiOverriden:1 |vpiRhs: \_constant: , line:9:26, endln:9:27 @@ -65502,7 +65502,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:10:15, endln:10:27 |vpiParent: - \_module: work@oh_dsync (work@oh_fifo_async.wr_sync[3]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:119:4, endln:124:35 + \_module_inst: work@oh_dsync (work@oh_fifo_async.wr_sync[3]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:119:4, endln:124:35 |vpiRhs: \_constant: , line:10:26, endln:10:27 |vpiDecompile:0 @@ -65516,7 +65516,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:11:15, endln:11:32 |vpiParent: - \_module: work@oh_dsync (work@oh_fifo_async.wr_sync[3]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:119:4, endln:124:35 + \_module_inst: work@oh_dsync (work@oh_fifo_async.wr_sync[3]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:119:4, endln:124:35 |vpiOverriden:1 |vpiRhs: \_constant: , line:11:26, endln:11:32 @@ -65531,7 +65531,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:12:15, endln:12:35 |vpiParent: - \_module: work@oh_dsync (work@oh_fifo_async.wr_sync[3]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:119:4, endln:124:35 + \_module_inst: work@oh_dsync (work@oh_fifo_async.wr_sync[3]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:119:4, endln:124:35 |vpiRhs: \_constant: , line:12:26, endln:12:35 |vpiDecompile:DEFAULT @@ -65549,7 +65549,7 @@ design: (work@oh_fifo_async) |vpiNet: \_logic_net: (work@oh_fifo_async.wr_sync[3].clk), line:15:12, endln:15:15 |vpiParent: - \_module: work@oh_dsync (work@oh_fifo_async.wr_sync[3]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:119:4, endln:124:35 + \_module_inst: work@oh_dsync (work@oh_fifo_async.wr_sync[3]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:119:4, endln:124:35 |vpiTypespec: \_logic_typespec: , line:15:12, endln:15:12 |vpiName:clk @@ -65557,7 +65557,7 @@ design: (work@oh_fifo_async) |vpiNet: \_logic_net: (work@oh_fifo_async.wr_sync[3].nreset), line:16:12, endln:16:18 |vpiParent: - \_module: work@oh_dsync (work@oh_fifo_async.wr_sync[3]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:119:4, endln:124:35 + \_module_inst: work@oh_dsync (work@oh_fifo_async.wr_sync[3]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:119:4, endln:124:35 |vpiTypespec: \_logic_typespec: , line:16:12, endln:16:12 |vpiName:nreset @@ -65565,7 +65565,7 @@ design: (work@oh_fifo_async) |vpiNet: \_logic_net: (work@oh_fifo_async.wr_sync[3].din), line:17:12, endln:17:15 |vpiParent: - \_module: work@oh_dsync (work@oh_fifo_async.wr_sync[3]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:119:4, endln:124:35 + \_module_inst: work@oh_dsync (work@oh_fifo_async.wr_sync[3]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:119:4, endln:124:35 |vpiTypespec: \_logic_typespec: , line:17:12, endln:17:12 |vpiName:din @@ -65573,17 +65573,17 @@ design: (work@oh_fifo_async) |vpiNet: \_logic_net: (work@oh_fifo_async.wr_sync[3].dout), line:18:12, endln:18:16 |vpiParent: - \_module: work@oh_dsync (work@oh_fifo_async.wr_sync[3]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:119:4, endln:124:35 + \_module_inst: work@oh_dsync (work@oh_fifo_async.wr_sync[3]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:119:4, endln:124:35 |vpiTypespec: \_logic_typespec: , line:18:12, endln:18:12 |vpiName:dout |vpiFullName:work@oh_fifo_async.wr_sync[3].dout |vpiInstance: - \_module: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 + \_module_inst: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 |vpiPort: \_port: (clk), line:15:12, endln:15:15 |vpiParent: - \_module: work@oh_dsync (work@oh_fifo_async.wr_sync[3]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:119:4, endln:124:35 + \_module_inst: work@oh_dsync (work@oh_fifo_async.wr_sync[3]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:119:4, endln:124:35 |vpiName:clk |vpiDirection:1 |vpiHighConn: @@ -65605,11 +65605,11 @@ design: (work@oh_fifo_async) |vpiTypedef: \_logic_typespec: , line:15:12, endln:15:12 |vpiInstance: - \_module: work@oh_dsync (work@oh_fifo_async.wr_sync[3]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:119:4, endln:124:35 + \_module_inst: work@oh_dsync (work@oh_fifo_async.wr_sync[3]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:119:4, endln:124:35 |vpiPort: \_port: (nreset), line:16:12, endln:16:18 |vpiParent: - \_module: work@oh_dsync (work@oh_fifo_async.wr_sync[3]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:119:4, endln:124:35 + \_module_inst: work@oh_dsync (work@oh_fifo_async.wr_sync[3]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:119:4, endln:124:35 |vpiName:nreset |vpiDirection:1 |vpiHighConn: @@ -65631,11 +65631,11 @@ design: (work@oh_fifo_async) |vpiTypedef: \_logic_typespec: , line:16:12, endln:16:12 |vpiInstance: - \_module: work@oh_dsync (work@oh_fifo_async.wr_sync[3]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:119:4, endln:124:35 + \_module_inst: work@oh_dsync (work@oh_fifo_async.wr_sync[3]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:119:4, endln:124:35 |vpiPort: \_port: (din), line:17:12, endln:17:15 |vpiParent: - \_module: work@oh_dsync (work@oh_fifo_async.wr_sync[3]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:119:4, endln:124:35 + \_module_inst: work@oh_dsync (work@oh_fifo_async.wr_sync[3]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:119:4, endln:124:35 |vpiName:din |vpiDirection:1 |vpiHighConn: @@ -65673,11 +65673,11 @@ design: (work@oh_fifo_async) |vpiTypedef: \_logic_typespec: , line:17:12, endln:17:12 |vpiInstance: - \_module: work@oh_dsync (work@oh_fifo_async.wr_sync[3]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:119:4, endln:124:35 + \_module_inst: work@oh_dsync (work@oh_fifo_async.wr_sync[3]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:119:4, endln:124:35 |vpiPort: \_port: (dout), line:18:12, endln:18:16 |vpiParent: - \_module: work@oh_dsync (work@oh_fifo_async.wr_sync[3]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:119:4, endln:124:35 + \_module_inst: work@oh_dsync (work@oh_fifo_async.wr_sync[3]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:119:4, endln:124:35 |vpiName:dout |vpiDirection:2 |vpiHighConn: @@ -65715,11 +65715,11 @@ design: (work@oh_fifo_async) |vpiTypedef: \_logic_typespec: , line:18:12, endln:18:12 |vpiInstance: - \_module: work@oh_dsync (work@oh_fifo_async.wr_sync[3]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:119:4, endln:124:35 + \_module_inst: work@oh_dsync (work@oh_fifo_async.wr_sync[3]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:119:4, endln:124:35 |vpiGenScopeArray: \_gen_scope_array: (work@oh_fifo_async.wr_sync[3].genblk1), line:22:7, endln:42:5 |vpiParent: - \_module: work@oh_dsync (work@oh_fifo_async.wr_sync[3]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:119:4, endln:124:35 + \_module_inst: work@oh_dsync (work@oh_fifo_async.wr_sync[3]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:119:4, endln:124:35 |vpiName:genblk1 |vpiFullName:work@oh_fifo_async.wr_sync[3].genblk1 |vpiGenScope: @@ -66061,16 +66061,16 @@ design: (work@oh_fifo_async) |vpiFullName:work@oh_fifo_async.wr_sync[3].genblk1.dout |vpiActual: \_logic_net: (work@oh_fifo_async.wr_sync[3].dout), line:18:12, endln:18:16 - |vpiModule: - \_module: work@oh_dsync (work@oh_fifo_async.wr_sync[4]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:119:4, endln:124:35 + |vpiModuleInst: + \_module_inst: work@oh_dsync (work@oh_fifo_async.wr_sync[4]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:119:4, endln:124:35 |vpiParent: - \_module: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 + \_module_inst: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 |vpiName:wr_sync[4] |vpiFullName:work@oh_fifo_async.wr_sync[4] |vpiParameter: \_parameter: (work@oh_fifo_async.wr_sync[4].SYNCPIPE), line:9:15, endln:9:23 |vpiParent: - \_module: work@oh_dsync (work@oh_fifo_async.wr_sync[4]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:119:4, endln:124:35 + \_module_inst: work@oh_dsync (work@oh_fifo_async.wr_sync[4]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:119:4, endln:124:35 |UINT:2 |vpiTypespec: \_int_typespec: @@ -66081,7 +66081,7 @@ design: (work@oh_fifo_async) |vpiParameter: \_parameter: (work@oh_fifo_async.wr_sync[4].DELAY), line:10:15, endln:10:20 |vpiParent: - \_module: work@oh_dsync (work@oh_fifo_async.wr_sync[4]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:119:4, endln:124:35 + \_module_inst: work@oh_dsync (work@oh_fifo_async.wr_sync[4]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:119:4, endln:124:35 |UINT:0 |vpiTypespec: \_int_typespec: @@ -66092,7 +66092,7 @@ design: (work@oh_fifo_async) |vpiParameter: \_parameter: (work@oh_fifo_async.wr_sync[4].SYN), line:11:15, endln:11:18 |vpiParent: - \_module: work@oh_dsync (work@oh_fifo_async.wr_sync[4]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:119:4, endln:124:35 + \_module_inst: work@oh_dsync (work@oh_fifo_async.wr_sync[4]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:119:4, endln:124:35 |STRING:TRUE |vpiTypespec: \_string_typespec: @@ -66103,7 +66103,7 @@ design: (work@oh_fifo_async) |vpiParameter: \_parameter: (work@oh_fifo_async.wr_sync[4].TYPE), line:12:15, endln:12:19 |vpiParent: - \_module: work@oh_dsync (work@oh_fifo_async.wr_sync[4]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:119:4, endln:124:35 + \_module_inst: work@oh_dsync (work@oh_fifo_async.wr_sync[4]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:119:4, endln:124:35 |STRING:DEFAULT |vpiTypespec: \_string_typespec: @@ -66114,7 +66114,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:9:15, endln:9:27 |vpiParent: - \_module: work@oh_dsync (work@oh_fifo_async.wr_sync[4]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:119:4, endln:124:35 + \_module_inst: work@oh_dsync (work@oh_fifo_async.wr_sync[4]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:119:4, endln:124:35 |vpiOverriden:1 |vpiRhs: \_constant: , line:9:26, endln:9:27 @@ -66129,7 +66129,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:10:15, endln:10:27 |vpiParent: - \_module: work@oh_dsync (work@oh_fifo_async.wr_sync[4]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:119:4, endln:124:35 + \_module_inst: work@oh_dsync (work@oh_fifo_async.wr_sync[4]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:119:4, endln:124:35 |vpiRhs: \_constant: , line:10:26, endln:10:27 |vpiDecompile:0 @@ -66143,7 +66143,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:11:15, endln:11:32 |vpiParent: - \_module: work@oh_dsync (work@oh_fifo_async.wr_sync[4]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:119:4, endln:124:35 + \_module_inst: work@oh_dsync (work@oh_fifo_async.wr_sync[4]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:119:4, endln:124:35 |vpiOverriden:1 |vpiRhs: \_constant: , line:11:26, endln:11:32 @@ -66158,7 +66158,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:12:15, endln:12:35 |vpiParent: - \_module: work@oh_dsync (work@oh_fifo_async.wr_sync[4]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:119:4, endln:124:35 + \_module_inst: work@oh_dsync (work@oh_fifo_async.wr_sync[4]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:119:4, endln:124:35 |vpiRhs: \_constant: , line:12:26, endln:12:35 |vpiDecompile:DEFAULT @@ -66176,7 +66176,7 @@ design: (work@oh_fifo_async) |vpiNet: \_logic_net: (work@oh_fifo_async.wr_sync[4].clk), line:15:12, endln:15:15 |vpiParent: - \_module: work@oh_dsync (work@oh_fifo_async.wr_sync[4]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:119:4, endln:124:35 + \_module_inst: work@oh_dsync (work@oh_fifo_async.wr_sync[4]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:119:4, endln:124:35 |vpiTypespec: \_logic_typespec: , line:15:12, endln:15:12 |vpiName:clk @@ -66184,7 +66184,7 @@ design: (work@oh_fifo_async) |vpiNet: \_logic_net: (work@oh_fifo_async.wr_sync[4].nreset), line:16:12, endln:16:18 |vpiParent: - \_module: work@oh_dsync (work@oh_fifo_async.wr_sync[4]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:119:4, endln:124:35 + \_module_inst: work@oh_dsync (work@oh_fifo_async.wr_sync[4]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:119:4, endln:124:35 |vpiTypespec: \_logic_typespec: , line:16:12, endln:16:12 |vpiName:nreset @@ -66192,7 +66192,7 @@ design: (work@oh_fifo_async) |vpiNet: \_logic_net: (work@oh_fifo_async.wr_sync[4].din), line:17:12, endln:17:15 |vpiParent: - \_module: work@oh_dsync (work@oh_fifo_async.wr_sync[4]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:119:4, endln:124:35 + \_module_inst: work@oh_dsync (work@oh_fifo_async.wr_sync[4]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:119:4, endln:124:35 |vpiTypespec: \_logic_typespec: , line:17:12, endln:17:12 |vpiName:din @@ -66200,17 +66200,17 @@ design: (work@oh_fifo_async) |vpiNet: \_logic_net: (work@oh_fifo_async.wr_sync[4].dout), line:18:12, endln:18:16 |vpiParent: - \_module: work@oh_dsync (work@oh_fifo_async.wr_sync[4]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:119:4, endln:124:35 + \_module_inst: work@oh_dsync (work@oh_fifo_async.wr_sync[4]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:119:4, endln:124:35 |vpiTypespec: \_logic_typespec: , line:18:12, endln:18:12 |vpiName:dout |vpiFullName:work@oh_fifo_async.wr_sync[4].dout |vpiInstance: - \_module: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 + \_module_inst: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 |vpiPort: \_port: (clk), line:15:12, endln:15:15 |vpiParent: - \_module: work@oh_dsync (work@oh_fifo_async.wr_sync[4]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:119:4, endln:124:35 + \_module_inst: work@oh_dsync (work@oh_fifo_async.wr_sync[4]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:119:4, endln:124:35 |vpiName:clk |vpiDirection:1 |vpiHighConn: @@ -66232,11 +66232,11 @@ design: (work@oh_fifo_async) |vpiTypedef: \_logic_typespec: , line:15:12, endln:15:12 |vpiInstance: - \_module: work@oh_dsync (work@oh_fifo_async.wr_sync[4]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:119:4, endln:124:35 + \_module_inst: work@oh_dsync (work@oh_fifo_async.wr_sync[4]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:119:4, endln:124:35 |vpiPort: \_port: (nreset), line:16:12, endln:16:18 |vpiParent: - \_module: work@oh_dsync (work@oh_fifo_async.wr_sync[4]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:119:4, endln:124:35 + \_module_inst: work@oh_dsync (work@oh_fifo_async.wr_sync[4]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:119:4, endln:124:35 |vpiName:nreset |vpiDirection:1 |vpiHighConn: @@ -66258,11 +66258,11 @@ design: (work@oh_fifo_async) |vpiTypedef: \_logic_typespec: , line:16:12, endln:16:12 |vpiInstance: - \_module: work@oh_dsync (work@oh_fifo_async.wr_sync[4]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:119:4, endln:124:35 + \_module_inst: work@oh_dsync (work@oh_fifo_async.wr_sync[4]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:119:4, endln:124:35 |vpiPort: \_port: (din), line:17:12, endln:17:15 |vpiParent: - \_module: work@oh_dsync (work@oh_fifo_async.wr_sync[4]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:119:4, endln:124:35 + \_module_inst: work@oh_dsync (work@oh_fifo_async.wr_sync[4]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:119:4, endln:124:35 |vpiName:din |vpiDirection:1 |vpiHighConn: @@ -66300,11 +66300,11 @@ design: (work@oh_fifo_async) |vpiTypedef: \_logic_typespec: , line:17:12, endln:17:12 |vpiInstance: - \_module: work@oh_dsync (work@oh_fifo_async.wr_sync[4]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:119:4, endln:124:35 + \_module_inst: work@oh_dsync (work@oh_fifo_async.wr_sync[4]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:119:4, endln:124:35 |vpiPort: \_port: (dout), line:18:12, endln:18:16 |vpiParent: - \_module: work@oh_dsync (work@oh_fifo_async.wr_sync[4]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:119:4, endln:124:35 + \_module_inst: work@oh_dsync (work@oh_fifo_async.wr_sync[4]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:119:4, endln:124:35 |vpiName:dout |vpiDirection:2 |vpiHighConn: @@ -66342,11 +66342,11 @@ design: (work@oh_fifo_async) |vpiTypedef: \_logic_typespec: , line:18:12, endln:18:12 |vpiInstance: - \_module: work@oh_dsync (work@oh_fifo_async.wr_sync[4]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:119:4, endln:124:35 + \_module_inst: work@oh_dsync (work@oh_fifo_async.wr_sync[4]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:119:4, endln:124:35 |vpiGenScopeArray: \_gen_scope_array: (work@oh_fifo_async.wr_sync[4].genblk1), line:22:7, endln:42:5 |vpiParent: - \_module: work@oh_dsync (work@oh_fifo_async.wr_sync[4]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:119:4, endln:124:35 + \_module_inst: work@oh_dsync (work@oh_fifo_async.wr_sync[4]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:119:4, endln:124:35 |vpiName:genblk1 |vpiFullName:work@oh_fifo_async.wr_sync[4].genblk1 |vpiGenScope: @@ -66688,16 +66688,16 @@ design: (work@oh_fifo_async) |vpiFullName:work@oh_fifo_async.wr_sync[4].genblk1.dout |vpiActual: \_logic_net: (work@oh_fifo_async.wr_sync[4].dout), line:18:12, endln:18:16 - |vpiModule: - \_module: work@oh_dsync (work@oh_fifo_async.wr_sync[5]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:119:4, endln:124:35 + |vpiModuleInst: + \_module_inst: work@oh_dsync (work@oh_fifo_async.wr_sync[5]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:119:4, endln:124:35 |vpiParent: - \_module: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 + \_module_inst: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 |vpiName:wr_sync[5] |vpiFullName:work@oh_fifo_async.wr_sync[5] |vpiParameter: \_parameter: (work@oh_fifo_async.wr_sync[5].SYNCPIPE), line:9:15, endln:9:23 |vpiParent: - \_module: work@oh_dsync (work@oh_fifo_async.wr_sync[5]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:119:4, endln:124:35 + \_module_inst: work@oh_dsync (work@oh_fifo_async.wr_sync[5]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:119:4, endln:124:35 |UINT:2 |vpiTypespec: \_int_typespec: @@ -66708,7 +66708,7 @@ design: (work@oh_fifo_async) |vpiParameter: \_parameter: (work@oh_fifo_async.wr_sync[5].DELAY), line:10:15, endln:10:20 |vpiParent: - \_module: work@oh_dsync (work@oh_fifo_async.wr_sync[5]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:119:4, endln:124:35 + \_module_inst: work@oh_dsync (work@oh_fifo_async.wr_sync[5]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:119:4, endln:124:35 |UINT:0 |vpiTypespec: \_int_typespec: @@ -66719,7 +66719,7 @@ design: (work@oh_fifo_async) |vpiParameter: \_parameter: (work@oh_fifo_async.wr_sync[5].SYN), line:11:15, endln:11:18 |vpiParent: - \_module: work@oh_dsync (work@oh_fifo_async.wr_sync[5]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:119:4, endln:124:35 + \_module_inst: work@oh_dsync (work@oh_fifo_async.wr_sync[5]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:119:4, endln:124:35 |STRING:TRUE |vpiTypespec: \_string_typespec: @@ -66730,7 +66730,7 @@ design: (work@oh_fifo_async) |vpiParameter: \_parameter: (work@oh_fifo_async.wr_sync[5].TYPE), line:12:15, endln:12:19 |vpiParent: - \_module: work@oh_dsync (work@oh_fifo_async.wr_sync[5]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:119:4, endln:124:35 + \_module_inst: work@oh_dsync (work@oh_fifo_async.wr_sync[5]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:119:4, endln:124:35 |STRING:DEFAULT |vpiTypespec: \_string_typespec: @@ -66741,7 +66741,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:9:15, endln:9:27 |vpiParent: - \_module: work@oh_dsync (work@oh_fifo_async.wr_sync[5]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:119:4, endln:124:35 + \_module_inst: work@oh_dsync (work@oh_fifo_async.wr_sync[5]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:119:4, endln:124:35 |vpiOverriden:1 |vpiRhs: \_constant: , line:9:26, endln:9:27 @@ -66756,7 +66756,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:10:15, endln:10:27 |vpiParent: - \_module: work@oh_dsync (work@oh_fifo_async.wr_sync[5]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:119:4, endln:124:35 + \_module_inst: work@oh_dsync (work@oh_fifo_async.wr_sync[5]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:119:4, endln:124:35 |vpiRhs: \_constant: , line:10:26, endln:10:27 |vpiDecompile:0 @@ -66770,7 +66770,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:11:15, endln:11:32 |vpiParent: - \_module: work@oh_dsync (work@oh_fifo_async.wr_sync[5]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:119:4, endln:124:35 + \_module_inst: work@oh_dsync (work@oh_fifo_async.wr_sync[5]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:119:4, endln:124:35 |vpiOverriden:1 |vpiRhs: \_constant: , line:11:26, endln:11:32 @@ -66785,7 +66785,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:12:15, endln:12:35 |vpiParent: - \_module: work@oh_dsync (work@oh_fifo_async.wr_sync[5]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:119:4, endln:124:35 + \_module_inst: work@oh_dsync (work@oh_fifo_async.wr_sync[5]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:119:4, endln:124:35 |vpiRhs: \_constant: , line:12:26, endln:12:35 |vpiDecompile:DEFAULT @@ -66803,7 +66803,7 @@ design: (work@oh_fifo_async) |vpiNet: \_logic_net: (work@oh_fifo_async.wr_sync[5].clk), line:15:12, endln:15:15 |vpiParent: - \_module: work@oh_dsync (work@oh_fifo_async.wr_sync[5]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:119:4, endln:124:35 + \_module_inst: work@oh_dsync (work@oh_fifo_async.wr_sync[5]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:119:4, endln:124:35 |vpiTypespec: \_logic_typespec: , line:15:12, endln:15:12 |vpiName:clk @@ -66811,7 +66811,7 @@ design: (work@oh_fifo_async) |vpiNet: \_logic_net: (work@oh_fifo_async.wr_sync[5].nreset), line:16:12, endln:16:18 |vpiParent: - \_module: work@oh_dsync (work@oh_fifo_async.wr_sync[5]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:119:4, endln:124:35 + \_module_inst: work@oh_dsync (work@oh_fifo_async.wr_sync[5]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:119:4, endln:124:35 |vpiTypespec: \_logic_typespec: , line:16:12, endln:16:12 |vpiName:nreset @@ -66819,7 +66819,7 @@ design: (work@oh_fifo_async) |vpiNet: \_logic_net: (work@oh_fifo_async.wr_sync[5].din), line:17:12, endln:17:15 |vpiParent: - \_module: work@oh_dsync (work@oh_fifo_async.wr_sync[5]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:119:4, endln:124:35 + \_module_inst: work@oh_dsync (work@oh_fifo_async.wr_sync[5]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:119:4, endln:124:35 |vpiTypespec: \_logic_typespec: , line:17:12, endln:17:12 |vpiName:din @@ -66827,17 +66827,17 @@ design: (work@oh_fifo_async) |vpiNet: \_logic_net: (work@oh_fifo_async.wr_sync[5].dout), line:18:12, endln:18:16 |vpiParent: - \_module: work@oh_dsync (work@oh_fifo_async.wr_sync[5]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:119:4, endln:124:35 + \_module_inst: work@oh_dsync (work@oh_fifo_async.wr_sync[5]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:119:4, endln:124:35 |vpiTypespec: \_logic_typespec: , line:18:12, endln:18:12 |vpiName:dout |vpiFullName:work@oh_fifo_async.wr_sync[5].dout |vpiInstance: - \_module: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 + \_module_inst: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 |vpiPort: \_port: (clk), line:15:12, endln:15:15 |vpiParent: - \_module: work@oh_dsync (work@oh_fifo_async.wr_sync[5]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:119:4, endln:124:35 + \_module_inst: work@oh_dsync (work@oh_fifo_async.wr_sync[5]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:119:4, endln:124:35 |vpiName:clk |vpiDirection:1 |vpiHighConn: @@ -66859,11 +66859,11 @@ design: (work@oh_fifo_async) |vpiTypedef: \_logic_typespec: , line:15:12, endln:15:12 |vpiInstance: - \_module: work@oh_dsync (work@oh_fifo_async.wr_sync[5]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:119:4, endln:124:35 + \_module_inst: work@oh_dsync (work@oh_fifo_async.wr_sync[5]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:119:4, endln:124:35 |vpiPort: \_port: (nreset), line:16:12, endln:16:18 |vpiParent: - \_module: work@oh_dsync (work@oh_fifo_async.wr_sync[5]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:119:4, endln:124:35 + \_module_inst: work@oh_dsync (work@oh_fifo_async.wr_sync[5]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:119:4, endln:124:35 |vpiName:nreset |vpiDirection:1 |vpiHighConn: @@ -66885,11 +66885,11 @@ design: (work@oh_fifo_async) |vpiTypedef: \_logic_typespec: , line:16:12, endln:16:12 |vpiInstance: - \_module: work@oh_dsync (work@oh_fifo_async.wr_sync[5]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:119:4, endln:124:35 + \_module_inst: work@oh_dsync (work@oh_fifo_async.wr_sync[5]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:119:4, endln:124:35 |vpiPort: \_port: (din), line:17:12, endln:17:15 |vpiParent: - \_module: work@oh_dsync (work@oh_fifo_async.wr_sync[5]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:119:4, endln:124:35 + \_module_inst: work@oh_dsync (work@oh_fifo_async.wr_sync[5]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:119:4, endln:124:35 |vpiName:din |vpiDirection:1 |vpiHighConn: @@ -66927,11 +66927,11 @@ design: (work@oh_fifo_async) |vpiTypedef: \_logic_typespec: , line:17:12, endln:17:12 |vpiInstance: - \_module: work@oh_dsync (work@oh_fifo_async.wr_sync[5]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:119:4, endln:124:35 + \_module_inst: work@oh_dsync (work@oh_fifo_async.wr_sync[5]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:119:4, endln:124:35 |vpiPort: \_port: (dout), line:18:12, endln:18:16 |vpiParent: - \_module: work@oh_dsync (work@oh_fifo_async.wr_sync[5]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:119:4, endln:124:35 + \_module_inst: work@oh_dsync (work@oh_fifo_async.wr_sync[5]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:119:4, endln:124:35 |vpiName:dout |vpiDirection:2 |vpiHighConn: @@ -66969,11 +66969,11 @@ design: (work@oh_fifo_async) |vpiTypedef: \_logic_typespec: , line:18:12, endln:18:12 |vpiInstance: - \_module: work@oh_dsync (work@oh_fifo_async.wr_sync[5]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:119:4, endln:124:35 + \_module_inst: work@oh_dsync (work@oh_fifo_async.wr_sync[5]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:119:4, endln:124:35 |vpiGenScopeArray: \_gen_scope_array: (work@oh_fifo_async.wr_sync[5].genblk1), line:22:7, endln:42:5 |vpiParent: - \_module: work@oh_dsync (work@oh_fifo_async.wr_sync[5]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:119:4, endln:124:35 + \_module_inst: work@oh_dsync (work@oh_fifo_async.wr_sync[5]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:119:4, endln:124:35 |vpiName:genblk1 |vpiFullName:work@oh_fifo_async.wr_sync[5].genblk1 |vpiGenScope: @@ -67315,16 +67315,16 @@ design: (work@oh_fifo_async) |vpiFullName:work@oh_fifo_async.wr_sync[5].genblk1.dout |vpiActual: \_logic_net: (work@oh_fifo_async.wr_sync[5].dout), line:18:12, endln:18:16 - |vpiModule: - \_module: work@oh_bin2gray (work@oh_fifo_async.rd_bin2gray), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:130:4, endln:132:27 + |vpiModuleInst: + \_module_inst: work@oh_bin2gray (work@oh_fifo_async.rd_bin2gray), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:130:4, endln:132:27 |vpiParent: - \_module: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 + \_module_inst: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 |vpiName:rd_bin2gray |vpiFullName:work@oh_fifo_async.rd_bin2gray |vpiVariables: \_integer_var: (work@oh_fifo_async.rd_bin2gray.i), line:19:16, endln:19:17 |vpiParent: - \_module: work@oh_bin2gray (work@oh_fifo_async.rd_bin2gray), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:130:4, endln:132:27 + \_module_inst: work@oh_bin2gray (work@oh_fifo_async.rd_bin2gray), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:130:4, endln:132:27 |vpiTypespec: \_integer_typespec: , line:19:4, endln:19:11 |vpiSigned:1 @@ -67334,7 +67334,7 @@ design: (work@oh_fifo_async) |vpiParameter: \_parameter: (work@oh_fifo_async.rd_bin2gray.N), line:9:15, endln:9:16 |vpiParent: - \_module: work@oh_bin2gray (work@oh_fifo_async.rd_bin2gray), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:130:4, endln:132:27 + \_module_inst: work@oh_bin2gray (work@oh_fifo_async.rd_bin2gray), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:130:4, endln:132:27 |UINT:32 |vpiTypespec: \_int_typespec: @@ -67345,7 +67345,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:9:15, endln:9:21 |vpiParent: - \_module: work@oh_bin2gray (work@oh_fifo_async.rd_bin2gray), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:130:4, endln:132:27 + \_module_inst: work@oh_bin2gray (work@oh_fifo_async.rd_bin2gray), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:130:4, endln:132:27 |vpiOverriden:1 |vpiRhs: \_constant: , line:9:19, endln:9:21 @@ -67364,7 +67364,7 @@ design: (work@oh_fifo_async) |vpiNet: \_logic_net: (work@oh_fifo_async.rd_bin2gray.in), line:12:20, endln:12:22 |vpiParent: - \_module: work@oh_bin2gray (work@oh_fifo_async.rd_bin2gray), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:130:4, endln:132:27 + \_module_inst: work@oh_bin2gray (work@oh_fifo_async.rd_bin2gray), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:130:4, endln:132:27 |vpiTypespec: \_logic_typespec: , line:12:11, endln:12:18 |vpiRange: @@ -67390,7 +67390,7 @@ design: (work@oh_fifo_async) |vpiNet: \_logic_net: (work@oh_fifo_async.rd_bin2gray.out), line:13:20, endln:13:23 |vpiParent: - \_module: work@oh_bin2gray (work@oh_fifo_async.rd_bin2gray), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:130:4, endln:132:27 + \_module_inst: work@oh_bin2gray (work@oh_fifo_async.rd_bin2gray), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:130:4, endln:132:27 |vpiTypespec: \_logic_typespec: , line:13:12, endln:13:19 |vpiRange: @@ -67416,7 +67416,7 @@ design: (work@oh_fifo_async) |vpiNet: \_logic_net: (work@oh_fifo_async.rd_bin2gray.gray), line:16:20, endln:16:24 |vpiParent: - \_module: work@oh_bin2gray (work@oh_fifo_async.rd_bin2gray), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:130:4, endln:132:27 + \_module_inst: work@oh_bin2gray (work@oh_fifo_async.rd_bin2gray), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:130:4, endln:132:27 |vpiTypespec: \_logic_typespec: , line:16:4, endln:16:15 |vpiRange: @@ -67443,7 +67443,7 @@ design: (work@oh_fifo_async) |vpiNet: \_logic_net: (work@oh_fifo_async.rd_bin2gray.bin), line:17:20, endln:17:23 |vpiParent: - \_module: work@oh_bin2gray (work@oh_fifo_async.rd_bin2gray), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:130:4, endln:132:27 + \_module_inst: work@oh_bin2gray (work@oh_fifo_async.rd_bin2gray), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:130:4, endln:132:27 |vpiTypespec: \_logic_typespec: , line:17:4, endln:17:16 |vpiRange: @@ -67468,11 +67468,11 @@ design: (work@oh_fifo_async) |vpiFullName:work@oh_fifo_async.rd_bin2gray.bin |vpiNetType:1 |vpiInstance: - \_module: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 + \_module_inst: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 |vpiPort: \_port: (in), line:12:20, endln:12:22 |vpiParent: - \_module: work@oh_bin2gray (work@oh_fifo_async.rd_bin2gray), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:130:4, endln:132:27 + \_module_inst: work@oh_bin2gray (work@oh_fifo_async.rd_bin2gray), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:130:4, endln:132:27 |vpiName:in |vpiDirection:1 |vpiHighConn: @@ -67530,11 +67530,11 @@ design: (work@oh_fifo_async) |UINT:0 |vpiConstType:9 |vpiInstance: - \_module: work@oh_bin2gray (work@oh_fifo_async.rd_bin2gray), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:130:4, endln:132:27 + \_module_inst: work@oh_bin2gray (work@oh_fifo_async.rd_bin2gray), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:130:4, endln:132:27 |vpiPort: \_port: (out), line:13:20, endln:13:23 |vpiParent: - \_module: work@oh_bin2gray (work@oh_fifo_async.rd_bin2gray), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:130:4, endln:132:27 + \_module_inst: work@oh_bin2gray (work@oh_fifo_async.rd_bin2gray), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:130:4, endln:132:27 |vpiName:out |vpiDirection:2 |vpiHighConn: @@ -67592,11 +67592,11 @@ design: (work@oh_fifo_async) |UINT:0 |vpiConstType:9 |vpiInstance: - \_module: work@oh_bin2gray (work@oh_fifo_async.rd_bin2gray), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:130:4, endln:132:27 + \_module_inst: work@oh_bin2gray (work@oh_fifo_async.rd_bin2gray), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:130:4, endln:132:27 |vpiProcess: \_always: , line:24:4, endln:29:9 |vpiParent: - \_module: work@oh_bin2gray (work@oh_fifo_async.rd_bin2gray), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:130:4, endln:132:27 + \_module_inst: work@oh_bin2gray (work@oh_fifo_async.rd_bin2gray), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:130:4, endln:132:27 |vpiStmt: \_event_control: , line:24:11, endln:24:13 |vpiParent: @@ -67834,7 +67834,7 @@ design: (work@oh_fifo_async) |vpiContAssign: \_cont_assign: , line:21:11, endln:21:34 |vpiParent: - \_module: work@oh_bin2gray (work@oh_fifo_async.rd_bin2gray), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:130:4, endln:132:27 + \_module_inst: work@oh_bin2gray (work@oh_fifo_async.rd_bin2gray), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:130:4, endln:132:27 |vpiRhs: \_part_select: , line:21:25, endln:21:34 |vpiParent: @@ -67896,7 +67896,7 @@ design: (work@oh_fifo_async) |vpiContAssign: \_cont_assign: , line:22:11, endln:22:36 |vpiParent: - \_module: work@oh_bin2gray (work@oh_fifo_async.rd_bin2gray), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:130:4, endln:132:27 + \_module_inst: work@oh_bin2gray (work@oh_fifo_async.rd_bin2gray), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:130:4, endln:132:27 |vpiRhs: \_part_select: , line:22:25, endln:22:36 |vpiParent: @@ -67955,16 +67955,16 @@ design: (work@oh_fifo_async) \_constant: , line:22:17, endln:22:18 |vpiRightRange: \_constant: , line:22:19, endln:22:20 - |vpiModule: - \_module: work@oh_dsync (work@oh_fifo_async.rd_sync[0]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:135:4, endln:140:35 + |vpiModuleInst: + \_module_inst: work@oh_dsync (work@oh_fifo_async.rd_sync[0]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:135:4, endln:140:35 |vpiParent: - \_module: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 + \_module_inst: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 |vpiName:rd_sync[0] |vpiFullName:work@oh_fifo_async.rd_sync[0] |vpiParameter: \_parameter: (work@oh_fifo_async.rd_sync[0].SYNCPIPE), line:9:15, endln:9:23 |vpiParent: - \_module: work@oh_dsync (work@oh_fifo_async.rd_sync[0]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:135:4, endln:140:35 + \_module_inst: work@oh_dsync (work@oh_fifo_async.rd_sync[0]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:135:4, endln:140:35 |UINT:2 |vpiTypespec: \_int_typespec: @@ -67975,7 +67975,7 @@ design: (work@oh_fifo_async) |vpiParameter: \_parameter: (work@oh_fifo_async.rd_sync[0].DELAY), line:10:15, endln:10:20 |vpiParent: - \_module: work@oh_dsync (work@oh_fifo_async.rd_sync[0]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:135:4, endln:140:35 + \_module_inst: work@oh_dsync (work@oh_fifo_async.rd_sync[0]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:135:4, endln:140:35 |UINT:0 |vpiTypespec: \_int_typespec: @@ -67986,7 +67986,7 @@ design: (work@oh_fifo_async) |vpiParameter: \_parameter: (work@oh_fifo_async.rd_sync[0].SYN), line:11:15, endln:11:18 |vpiParent: - \_module: work@oh_dsync (work@oh_fifo_async.rd_sync[0]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:135:4, endln:140:35 + \_module_inst: work@oh_dsync (work@oh_fifo_async.rd_sync[0]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:135:4, endln:140:35 |STRING:TRUE |vpiTypespec: \_string_typespec: @@ -67997,7 +67997,7 @@ design: (work@oh_fifo_async) |vpiParameter: \_parameter: (work@oh_fifo_async.rd_sync[0].TYPE), line:12:15, endln:12:19 |vpiParent: - \_module: work@oh_dsync (work@oh_fifo_async.rd_sync[0]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:135:4, endln:140:35 + \_module_inst: work@oh_dsync (work@oh_fifo_async.rd_sync[0]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:135:4, endln:140:35 |STRING:DEFAULT |vpiTypespec: \_string_typespec: @@ -68008,7 +68008,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:9:15, endln:9:27 |vpiParent: - \_module: work@oh_dsync (work@oh_fifo_async.rd_sync[0]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:135:4, endln:140:35 + \_module_inst: work@oh_dsync (work@oh_fifo_async.rd_sync[0]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:135:4, endln:140:35 |vpiOverriden:1 |vpiRhs: \_constant: , line:9:26, endln:9:27 @@ -68023,7 +68023,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:10:15, endln:10:27 |vpiParent: - \_module: work@oh_dsync (work@oh_fifo_async.rd_sync[0]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:135:4, endln:140:35 + \_module_inst: work@oh_dsync (work@oh_fifo_async.rd_sync[0]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:135:4, endln:140:35 |vpiRhs: \_constant: , line:10:26, endln:10:27 |vpiDecompile:0 @@ -68037,7 +68037,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:11:15, endln:11:32 |vpiParent: - \_module: work@oh_dsync (work@oh_fifo_async.rd_sync[0]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:135:4, endln:140:35 + \_module_inst: work@oh_dsync (work@oh_fifo_async.rd_sync[0]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:135:4, endln:140:35 |vpiOverriden:1 |vpiRhs: \_constant: , line:11:26, endln:11:32 @@ -68052,7 +68052,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:12:15, endln:12:35 |vpiParent: - \_module: work@oh_dsync (work@oh_fifo_async.rd_sync[0]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:135:4, endln:140:35 + \_module_inst: work@oh_dsync (work@oh_fifo_async.rd_sync[0]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:135:4, endln:140:35 |vpiRhs: \_constant: , line:12:26, endln:12:35 |vpiDecompile:DEFAULT @@ -68070,7 +68070,7 @@ design: (work@oh_fifo_async) |vpiNet: \_logic_net: (work@oh_fifo_async.rd_sync[0].clk), line:15:12, endln:15:15 |vpiParent: - \_module: work@oh_dsync (work@oh_fifo_async.rd_sync[0]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:135:4, endln:140:35 + \_module_inst: work@oh_dsync (work@oh_fifo_async.rd_sync[0]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:135:4, endln:140:35 |vpiTypespec: \_logic_typespec: , line:15:12, endln:15:12 |vpiName:clk @@ -68078,7 +68078,7 @@ design: (work@oh_fifo_async) |vpiNet: \_logic_net: (work@oh_fifo_async.rd_sync[0].nreset), line:16:12, endln:16:18 |vpiParent: - \_module: work@oh_dsync (work@oh_fifo_async.rd_sync[0]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:135:4, endln:140:35 + \_module_inst: work@oh_dsync (work@oh_fifo_async.rd_sync[0]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:135:4, endln:140:35 |vpiTypespec: \_logic_typespec: , line:16:12, endln:16:12 |vpiName:nreset @@ -68086,7 +68086,7 @@ design: (work@oh_fifo_async) |vpiNet: \_logic_net: (work@oh_fifo_async.rd_sync[0].din), line:17:12, endln:17:15 |vpiParent: - \_module: work@oh_dsync (work@oh_fifo_async.rd_sync[0]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:135:4, endln:140:35 + \_module_inst: work@oh_dsync (work@oh_fifo_async.rd_sync[0]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:135:4, endln:140:35 |vpiTypespec: \_logic_typespec: , line:17:12, endln:17:12 |vpiName:din @@ -68094,17 +68094,17 @@ design: (work@oh_fifo_async) |vpiNet: \_logic_net: (work@oh_fifo_async.rd_sync[0].dout), line:18:12, endln:18:16 |vpiParent: - \_module: work@oh_dsync (work@oh_fifo_async.rd_sync[0]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:135:4, endln:140:35 + \_module_inst: work@oh_dsync (work@oh_fifo_async.rd_sync[0]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:135:4, endln:140:35 |vpiTypespec: \_logic_typespec: , line:18:12, endln:18:12 |vpiName:dout |vpiFullName:work@oh_fifo_async.rd_sync[0].dout |vpiInstance: - \_module: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 + \_module_inst: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 |vpiPort: \_port: (clk), line:15:12, endln:15:15 |vpiParent: - \_module: work@oh_dsync (work@oh_fifo_async.rd_sync[0]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:135:4, endln:140:35 + \_module_inst: work@oh_dsync (work@oh_fifo_async.rd_sync[0]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:135:4, endln:140:35 |vpiName:clk |vpiDirection:1 |vpiHighConn: @@ -68126,11 +68126,11 @@ design: (work@oh_fifo_async) |vpiTypedef: \_logic_typespec: , line:15:12, endln:15:12 |vpiInstance: - \_module: work@oh_dsync (work@oh_fifo_async.rd_sync[0]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:135:4, endln:140:35 + \_module_inst: work@oh_dsync (work@oh_fifo_async.rd_sync[0]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:135:4, endln:140:35 |vpiPort: \_port: (nreset), line:16:12, endln:16:18 |vpiParent: - \_module: work@oh_dsync (work@oh_fifo_async.rd_sync[0]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:135:4, endln:140:35 + \_module_inst: work@oh_dsync (work@oh_fifo_async.rd_sync[0]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:135:4, endln:140:35 |vpiName:nreset |vpiDirection:1 |vpiHighConn: @@ -68152,11 +68152,11 @@ design: (work@oh_fifo_async) |vpiTypedef: \_logic_typespec: , line:16:12, endln:16:12 |vpiInstance: - \_module: work@oh_dsync (work@oh_fifo_async.rd_sync[0]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:135:4, endln:140:35 + \_module_inst: work@oh_dsync (work@oh_fifo_async.rd_sync[0]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:135:4, endln:140:35 |vpiPort: \_port: (din), line:17:12, endln:17:15 |vpiParent: - \_module: work@oh_dsync (work@oh_fifo_async.rd_sync[0]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:135:4, endln:140:35 + \_module_inst: work@oh_dsync (work@oh_fifo_async.rd_sync[0]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:135:4, endln:140:35 |vpiName:din |vpiDirection:1 |vpiHighConn: @@ -68194,11 +68194,11 @@ design: (work@oh_fifo_async) |vpiTypedef: \_logic_typespec: , line:17:12, endln:17:12 |vpiInstance: - \_module: work@oh_dsync (work@oh_fifo_async.rd_sync[0]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:135:4, endln:140:35 + \_module_inst: work@oh_dsync (work@oh_fifo_async.rd_sync[0]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:135:4, endln:140:35 |vpiPort: \_port: (dout), line:18:12, endln:18:16 |vpiParent: - \_module: work@oh_dsync (work@oh_fifo_async.rd_sync[0]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:135:4, endln:140:35 + \_module_inst: work@oh_dsync (work@oh_fifo_async.rd_sync[0]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:135:4, endln:140:35 |vpiName:dout |vpiDirection:2 |vpiHighConn: @@ -68236,11 +68236,11 @@ design: (work@oh_fifo_async) |vpiTypedef: \_logic_typespec: , line:18:12, endln:18:12 |vpiInstance: - \_module: work@oh_dsync (work@oh_fifo_async.rd_sync[0]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:135:4, endln:140:35 + \_module_inst: work@oh_dsync (work@oh_fifo_async.rd_sync[0]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:135:4, endln:140:35 |vpiGenScopeArray: \_gen_scope_array: (work@oh_fifo_async.rd_sync[0].genblk1), line:22:7, endln:42:5 |vpiParent: - \_module: work@oh_dsync (work@oh_fifo_async.rd_sync[0]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:135:4, endln:140:35 + \_module_inst: work@oh_dsync (work@oh_fifo_async.rd_sync[0]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:135:4, endln:140:35 |vpiName:genblk1 |vpiFullName:work@oh_fifo_async.rd_sync[0].genblk1 |vpiGenScope: @@ -68582,16 +68582,16 @@ design: (work@oh_fifo_async) |vpiFullName:work@oh_fifo_async.rd_sync[0].genblk1.dout |vpiActual: \_logic_net: (work@oh_fifo_async.rd_sync[0].dout), line:18:12, endln:18:16 - |vpiModule: - \_module: work@oh_dsync (work@oh_fifo_async.rd_sync[1]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:135:4, endln:140:35 + |vpiModuleInst: + \_module_inst: work@oh_dsync (work@oh_fifo_async.rd_sync[1]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:135:4, endln:140:35 |vpiParent: - \_module: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 + \_module_inst: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 |vpiName:rd_sync[1] |vpiFullName:work@oh_fifo_async.rd_sync[1] |vpiParameter: \_parameter: (work@oh_fifo_async.rd_sync[1].SYNCPIPE), line:9:15, endln:9:23 |vpiParent: - \_module: work@oh_dsync (work@oh_fifo_async.rd_sync[1]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:135:4, endln:140:35 + \_module_inst: work@oh_dsync (work@oh_fifo_async.rd_sync[1]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:135:4, endln:140:35 |UINT:2 |vpiTypespec: \_int_typespec: @@ -68602,7 +68602,7 @@ design: (work@oh_fifo_async) |vpiParameter: \_parameter: (work@oh_fifo_async.rd_sync[1].DELAY), line:10:15, endln:10:20 |vpiParent: - \_module: work@oh_dsync (work@oh_fifo_async.rd_sync[1]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:135:4, endln:140:35 + \_module_inst: work@oh_dsync (work@oh_fifo_async.rd_sync[1]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:135:4, endln:140:35 |UINT:0 |vpiTypespec: \_int_typespec: @@ -68613,7 +68613,7 @@ design: (work@oh_fifo_async) |vpiParameter: \_parameter: (work@oh_fifo_async.rd_sync[1].SYN), line:11:15, endln:11:18 |vpiParent: - \_module: work@oh_dsync (work@oh_fifo_async.rd_sync[1]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:135:4, endln:140:35 + \_module_inst: work@oh_dsync (work@oh_fifo_async.rd_sync[1]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:135:4, endln:140:35 |STRING:TRUE |vpiTypespec: \_string_typespec: @@ -68624,7 +68624,7 @@ design: (work@oh_fifo_async) |vpiParameter: \_parameter: (work@oh_fifo_async.rd_sync[1].TYPE), line:12:15, endln:12:19 |vpiParent: - \_module: work@oh_dsync (work@oh_fifo_async.rd_sync[1]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:135:4, endln:140:35 + \_module_inst: work@oh_dsync (work@oh_fifo_async.rd_sync[1]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:135:4, endln:140:35 |STRING:DEFAULT |vpiTypespec: \_string_typespec: @@ -68635,7 +68635,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:9:15, endln:9:27 |vpiParent: - \_module: work@oh_dsync (work@oh_fifo_async.rd_sync[1]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:135:4, endln:140:35 + \_module_inst: work@oh_dsync (work@oh_fifo_async.rd_sync[1]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:135:4, endln:140:35 |vpiOverriden:1 |vpiRhs: \_constant: , line:9:26, endln:9:27 @@ -68650,7 +68650,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:10:15, endln:10:27 |vpiParent: - \_module: work@oh_dsync (work@oh_fifo_async.rd_sync[1]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:135:4, endln:140:35 + \_module_inst: work@oh_dsync (work@oh_fifo_async.rd_sync[1]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:135:4, endln:140:35 |vpiRhs: \_constant: , line:10:26, endln:10:27 |vpiDecompile:0 @@ -68664,7 +68664,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:11:15, endln:11:32 |vpiParent: - \_module: work@oh_dsync (work@oh_fifo_async.rd_sync[1]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:135:4, endln:140:35 + \_module_inst: work@oh_dsync (work@oh_fifo_async.rd_sync[1]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:135:4, endln:140:35 |vpiOverriden:1 |vpiRhs: \_constant: , line:11:26, endln:11:32 @@ -68679,7 +68679,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:12:15, endln:12:35 |vpiParent: - \_module: work@oh_dsync (work@oh_fifo_async.rd_sync[1]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:135:4, endln:140:35 + \_module_inst: work@oh_dsync (work@oh_fifo_async.rd_sync[1]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:135:4, endln:140:35 |vpiRhs: \_constant: , line:12:26, endln:12:35 |vpiDecompile:DEFAULT @@ -68697,7 +68697,7 @@ design: (work@oh_fifo_async) |vpiNet: \_logic_net: (work@oh_fifo_async.rd_sync[1].clk), line:15:12, endln:15:15 |vpiParent: - \_module: work@oh_dsync (work@oh_fifo_async.rd_sync[1]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:135:4, endln:140:35 + \_module_inst: work@oh_dsync (work@oh_fifo_async.rd_sync[1]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:135:4, endln:140:35 |vpiTypespec: \_logic_typespec: , line:15:12, endln:15:12 |vpiName:clk @@ -68705,7 +68705,7 @@ design: (work@oh_fifo_async) |vpiNet: \_logic_net: (work@oh_fifo_async.rd_sync[1].nreset), line:16:12, endln:16:18 |vpiParent: - \_module: work@oh_dsync (work@oh_fifo_async.rd_sync[1]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:135:4, endln:140:35 + \_module_inst: work@oh_dsync (work@oh_fifo_async.rd_sync[1]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:135:4, endln:140:35 |vpiTypespec: \_logic_typespec: , line:16:12, endln:16:12 |vpiName:nreset @@ -68713,7 +68713,7 @@ design: (work@oh_fifo_async) |vpiNet: \_logic_net: (work@oh_fifo_async.rd_sync[1].din), line:17:12, endln:17:15 |vpiParent: - \_module: work@oh_dsync (work@oh_fifo_async.rd_sync[1]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:135:4, endln:140:35 + \_module_inst: work@oh_dsync (work@oh_fifo_async.rd_sync[1]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:135:4, endln:140:35 |vpiTypespec: \_logic_typespec: , line:17:12, endln:17:12 |vpiName:din @@ -68721,17 +68721,17 @@ design: (work@oh_fifo_async) |vpiNet: \_logic_net: (work@oh_fifo_async.rd_sync[1].dout), line:18:12, endln:18:16 |vpiParent: - \_module: work@oh_dsync (work@oh_fifo_async.rd_sync[1]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:135:4, endln:140:35 + \_module_inst: work@oh_dsync (work@oh_fifo_async.rd_sync[1]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:135:4, endln:140:35 |vpiTypespec: \_logic_typespec: , line:18:12, endln:18:12 |vpiName:dout |vpiFullName:work@oh_fifo_async.rd_sync[1].dout |vpiInstance: - \_module: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 + \_module_inst: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 |vpiPort: \_port: (clk), line:15:12, endln:15:15 |vpiParent: - \_module: work@oh_dsync (work@oh_fifo_async.rd_sync[1]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:135:4, endln:140:35 + \_module_inst: work@oh_dsync (work@oh_fifo_async.rd_sync[1]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:135:4, endln:140:35 |vpiName:clk |vpiDirection:1 |vpiHighConn: @@ -68753,11 +68753,11 @@ design: (work@oh_fifo_async) |vpiTypedef: \_logic_typespec: , line:15:12, endln:15:12 |vpiInstance: - \_module: work@oh_dsync (work@oh_fifo_async.rd_sync[1]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:135:4, endln:140:35 + \_module_inst: work@oh_dsync (work@oh_fifo_async.rd_sync[1]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:135:4, endln:140:35 |vpiPort: \_port: (nreset), line:16:12, endln:16:18 |vpiParent: - \_module: work@oh_dsync (work@oh_fifo_async.rd_sync[1]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:135:4, endln:140:35 + \_module_inst: work@oh_dsync (work@oh_fifo_async.rd_sync[1]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:135:4, endln:140:35 |vpiName:nreset |vpiDirection:1 |vpiHighConn: @@ -68779,11 +68779,11 @@ design: (work@oh_fifo_async) |vpiTypedef: \_logic_typespec: , line:16:12, endln:16:12 |vpiInstance: - \_module: work@oh_dsync (work@oh_fifo_async.rd_sync[1]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:135:4, endln:140:35 + \_module_inst: work@oh_dsync (work@oh_fifo_async.rd_sync[1]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:135:4, endln:140:35 |vpiPort: \_port: (din), line:17:12, endln:17:15 |vpiParent: - \_module: work@oh_dsync (work@oh_fifo_async.rd_sync[1]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:135:4, endln:140:35 + \_module_inst: work@oh_dsync (work@oh_fifo_async.rd_sync[1]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:135:4, endln:140:35 |vpiName:din |vpiDirection:1 |vpiHighConn: @@ -68821,11 +68821,11 @@ design: (work@oh_fifo_async) |vpiTypedef: \_logic_typespec: , line:17:12, endln:17:12 |vpiInstance: - \_module: work@oh_dsync (work@oh_fifo_async.rd_sync[1]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:135:4, endln:140:35 + \_module_inst: work@oh_dsync (work@oh_fifo_async.rd_sync[1]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:135:4, endln:140:35 |vpiPort: \_port: (dout), line:18:12, endln:18:16 |vpiParent: - \_module: work@oh_dsync (work@oh_fifo_async.rd_sync[1]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:135:4, endln:140:35 + \_module_inst: work@oh_dsync (work@oh_fifo_async.rd_sync[1]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:135:4, endln:140:35 |vpiName:dout |vpiDirection:2 |vpiHighConn: @@ -68863,11 +68863,11 @@ design: (work@oh_fifo_async) |vpiTypedef: \_logic_typespec: , line:18:12, endln:18:12 |vpiInstance: - \_module: work@oh_dsync (work@oh_fifo_async.rd_sync[1]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:135:4, endln:140:35 + \_module_inst: work@oh_dsync (work@oh_fifo_async.rd_sync[1]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:135:4, endln:140:35 |vpiGenScopeArray: \_gen_scope_array: (work@oh_fifo_async.rd_sync[1].genblk1), line:22:7, endln:42:5 |vpiParent: - \_module: work@oh_dsync (work@oh_fifo_async.rd_sync[1]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:135:4, endln:140:35 + \_module_inst: work@oh_dsync (work@oh_fifo_async.rd_sync[1]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:135:4, endln:140:35 |vpiName:genblk1 |vpiFullName:work@oh_fifo_async.rd_sync[1].genblk1 |vpiGenScope: @@ -69209,16 +69209,16 @@ design: (work@oh_fifo_async) |vpiFullName:work@oh_fifo_async.rd_sync[1].genblk1.dout |vpiActual: \_logic_net: (work@oh_fifo_async.rd_sync[1].dout), line:18:12, endln:18:16 - |vpiModule: - \_module: work@oh_dsync (work@oh_fifo_async.rd_sync[2]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:135:4, endln:140:35 + |vpiModuleInst: + \_module_inst: work@oh_dsync (work@oh_fifo_async.rd_sync[2]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:135:4, endln:140:35 |vpiParent: - \_module: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 + \_module_inst: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 |vpiName:rd_sync[2] |vpiFullName:work@oh_fifo_async.rd_sync[2] |vpiParameter: \_parameter: (work@oh_fifo_async.rd_sync[2].SYNCPIPE), line:9:15, endln:9:23 |vpiParent: - \_module: work@oh_dsync (work@oh_fifo_async.rd_sync[2]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:135:4, endln:140:35 + \_module_inst: work@oh_dsync (work@oh_fifo_async.rd_sync[2]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:135:4, endln:140:35 |UINT:2 |vpiTypespec: \_int_typespec: @@ -69229,7 +69229,7 @@ design: (work@oh_fifo_async) |vpiParameter: \_parameter: (work@oh_fifo_async.rd_sync[2].DELAY), line:10:15, endln:10:20 |vpiParent: - \_module: work@oh_dsync (work@oh_fifo_async.rd_sync[2]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:135:4, endln:140:35 + \_module_inst: work@oh_dsync (work@oh_fifo_async.rd_sync[2]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:135:4, endln:140:35 |UINT:0 |vpiTypespec: \_int_typespec: @@ -69240,7 +69240,7 @@ design: (work@oh_fifo_async) |vpiParameter: \_parameter: (work@oh_fifo_async.rd_sync[2].SYN), line:11:15, endln:11:18 |vpiParent: - \_module: work@oh_dsync (work@oh_fifo_async.rd_sync[2]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:135:4, endln:140:35 + \_module_inst: work@oh_dsync (work@oh_fifo_async.rd_sync[2]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:135:4, endln:140:35 |STRING:TRUE |vpiTypespec: \_string_typespec: @@ -69251,7 +69251,7 @@ design: (work@oh_fifo_async) |vpiParameter: \_parameter: (work@oh_fifo_async.rd_sync[2].TYPE), line:12:15, endln:12:19 |vpiParent: - \_module: work@oh_dsync (work@oh_fifo_async.rd_sync[2]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:135:4, endln:140:35 + \_module_inst: work@oh_dsync (work@oh_fifo_async.rd_sync[2]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:135:4, endln:140:35 |STRING:DEFAULT |vpiTypespec: \_string_typespec: @@ -69262,7 +69262,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:9:15, endln:9:27 |vpiParent: - \_module: work@oh_dsync (work@oh_fifo_async.rd_sync[2]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:135:4, endln:140:35 + \_module_inst: work@oh_dsync (work@oh_fifo_async.rd_sync[2]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:135:4, endln:140:35 |vpiOverriden:1 |vpiRhs: \_constant: , line:9:26, endln:9:27 @@ -69277,7 +69277,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:10:15, endln:10:27 |vpiParent: - \_module: work@oh_dsync (work@oh_fifo_async.rd_sync[2]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:135:4, endln:140:35 + \_module_inst: work@oh_dsync (work@oh_fifo_async.rd_sync[2]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:135:4, endln:140:35 |vpiRhs: \_constant: , line:10:26, endln:10:27 |vpiDecompile:0 @@ -69291,7 +69291,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:11:15, endln:11:32 |vpiParent: - \_module: work@oh_dsync (work@oh_fifo_async.rd_sync[2]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:135:4, endln:140:35 + \_module_inst: work@oh_dsync (work@oh_fifo_async.rd_sync[2]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:135:4, endln:140:35 |vpiOverriden:1 |vpiRhs: \_constant: , line:11:26, endln:11:32 @@ -69306,7 +69306,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:12:15, endln:12:35 |vpiParent: - \_module: work@oh_dsync (work@oh_fifo_async.rd_sync[2]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:135:4, endln:140:35 + \_module_inst: work@oh_dsync (work@oh_fifo_async.rd_sync[2]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:135:4, endln:140:35 |vpiRhs: \_constant: , line:12:26, endln:12:35 |vpiDecompile:DEFAULT @@ -69324,7 +69324,7 @@ design: (work@oh_fifo_async) |vpiNet: \_logic_net: (work@oh_fifo_async.rd_sync[2].clk), line:15:12, endln:15:15 |vpiParent: - \_module: work@oh_dsync (work@oh_fifo_async.rd_sync[2]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:135:4, endln:140:35 + \_module_inst: work@oh_dsync (work@oh_fifo_async.rd_sync[2]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:135:4, endln:140:35 |vpiTypespec: \_logic_typespec: , line:15:12, endln:15:12 |vpiName:clk @@ -69332,7 +69332,7 @@ design: (work@oh_fifo_async) |vpiNet: \_logic_net: (work@oh_fifo_async.rd_sync[2].nreset), line:16:12, endln:16:18 |vpiParent: - \_module: work@oh_dsync (work@oh_fifo_async.rd_sync[2]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:135:4, endln:140:35 + \_module_inst: work@oh_dsync (work@oh_fifo_async.rd_sync[2]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:135:4, endln:140:35 |vpiTypespec: \_logic_typespec: , line:16:12, endln:16:12 |vpiName:nreset @@ -69340,7 +69340,7 @@ design: (work@oh_fifo_async) |vpiNet: \_logic_net: (work@oh_fifo_async.rd_sync[2].din), line:17:12, endln:17:15 |vpiParent: - \_module: work@oh_dsync (work@oh_fifo_async.rd_sync[2]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:135:4, endln:140:35 + \_module_inst: work@oh_dsync (work@oh_fifo_async.rd_sync[2]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:135:4, endln:140:35 |vpiTypespec: \_logic_typespec: , line:17:12, endln:17:12 |vpiName:din @@ -69348,17 +69348,17 @@ design: (work@oh_fifo_async) |vpiNet: \_logic_net: (work@oh_fifo_async.rd_sync[2].dout), line:18:12, endln:18:16 |vpiParent: - \_module: work@oh_dsync (work@oh_fifo_async.rd_sync[2]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:135:4, endln:140:35 + \_module_inst: work@oh_dsync (work@oh_fifo_async.rd_sync[2]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:135:4, endln:140:35 |vpiTypespec: \_logic_typespec: , line:18:12, endln:18:12 |vpiName:dout |vpiFullName:work@oh_fifo_async.rd_sync[2].dout |vpiInstance: - \_module: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 + \_module_inst: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 |vpiPort: \_port: (clk), line:15:12, endln:15:15 |vpiParent: - \_module: work@oh_dsync (work@oh_fifo_async.rd_sync[2]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:135:4, endln:140:35 + \_module_inst: work@oh_dsync (work@oh_fifo_async.rd_sync[2]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:135:4, endln:140:35 |vpiName:clk |vpiDirection:1 |vpiHighConn: @@ -69380,11 +69380,11 @@ design: (work@oh_fifo_async) |vpiTypedef: \_logic_typespec: , line:15:12, endln:15:12 |vpiInstance: - \_module: work@oh_dsync (work@oh_fifo_async.rd_sync[2]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:135:4, endln:140:35 + \_module_inst: work@oh_dsync (work@oh_fifo_async.rd_sync[2]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:135:4, endln:140:35 |vpiPort: \_port: (nreset), line:16:12, endln:16:18 |vpiParent: - \_module: work@oh_dsync (work@oh_fifo_async.rd_sync[2]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:135:4, endln:140:35 + \_module_inst: work@oh_dsync (work@oh_fifo_async.rd_sync[2]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:135:4, endln:140:35 |vpiName:nreset |vpiDirection:1 |vpiHighConn: @@ -69406,11 +69406,11 @@ design: (work@oh_fifo_async) |vpiTypedef: \_logic_typespec: , line:16:12, endln:16:12 |vpiInstance: - \_module: work@oh_dsync (work@oh_fifo_async.rd_sync[2]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:135:4, endln:140:35 + \_module_inst: work@oh_dsync (work@oh_fifo_async.rd_sync[2]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:135:4, endln:140:35 |vpiPort: \_port: (din), line:17:12, endln:17:15 |vpiParent: - \_module: work@oh_dsync (work@oh_fifo_async.rd_sync[2]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:135:4, endln:140:35 + \_module_inst: work@oh_dsync (work@oh_fifo_async.rd_sync[2]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:135:4, endln:140:35 |vpiName:din |vpiDirection:1 |vpiHighConn: @@ -69448,11 +69448,11 @@ design: (work@oh_fifo_async) |vpiTypedef: \_logic_typespec: , line:17:12, endln:17:12 |vpiInstance: - \_module: work@oh_dsync (work@oh_fifo_async.rd_sync[2]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:135:4, endln:140:35 + \_module_inst: work@oh_dsync (work@oh_fifo_async.rd_sync[2]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:135:4, endln:140:35 |vpiPort: \_port: (dout), line:18:12, endln:18:16 |vpiParent: - \_module: work@oh_dsync (work@oh_fifo_async.rd_sync[2]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:135:4, endln:140:35 + \_module_inst: work@oh_dsync (work@oh_fifo_async.rd_sync[2]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:135:4, endln:140:35 |vpiName:dout |vpiDirection:2 |vpiHighConn: @@ -69490,11 +69490,11 @@ design: (work@oh_fifo_async) |vpiTypedef: \_logic_typespec: , line:18:12, endln:18:12 |vpiInstance: - \_module: work@oh_dsync (work@oh_fifo_async.rd_sync[2]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:135:4, endln:140:35 + \_module_inst: work@oh_dsync (work@oh_fifo_async.rd_sync[2]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:135:4, endln:140:35 |vpiGenScopeArray: \_gen_scope_array: (work@oh_fifo_async.rd_sync[2].genblk1), line:22:7, endln:42:5 |vpiParent: - \_module: work@oh_dsync (work@oh_fifo_async.rd_sync[2]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:135:4, endln:140:35 + \_module_inst: work@oh_dsync (work@oh_fifo_async.rd_sync[2]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:135:4, endln:140:35 |vpiName:genblk1 |vpiFullName:work@oh_fifo_async.rd_sync[2].genblk1 |vpiGenScope: @@ -69836,16 +69836,16 @@ design: (work@oh_fifo_async) |vpiFullName:work@oh_fifo_async.rd_sync[2].genblk1.dout |vpiActual: \_logic_net: (work@oh_fifo_async.rd_sync[2].dout), line:18:12, endln:18:16 - |vpiModule: - \_module: work@oh_dsync (work@oh_fifo_async.rd_sync[3]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:135:4, endln:140:35 + |vpiModuleInst: + \_module_inst: work@oh_dsync (work@oh_fifo_async.rd_sync[3]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:135:4, endln:140:35 |vpiParent: - \_module: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 + \_module_inst: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 |vpiName:rd_sync[3] |vpiFullName:work@oh_fifo_async.rd_sync[3] |vpiParameter: \_parameter: (work@oh_fifo_async.rd_sync[3].SYNCPIPE), line:9:15, endln:9:23 |vpiParent: - \_module: work@oh_dsync (work@oh_fifo_async.rd_sync[3]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:135:4, endln:140:35 + \_module_inst: work@oh_dsync (work@oh_fifo_async.rd_sync[3]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:135:4, endln:140:35 |UINT:2 |vpiTypespec: \_int_typespec: @@ -69856,7 +69856,7 @@ design: (work@oh_fifo_async) |vpiParameter: \_parameter: (work@oh_fifo_async.rd_sync[3].DELAY), line:10:15, endln:10:20 |vpiParent: - \_module: work@oh_dsync (work@oh_fifo_async.rd_sync[3]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:135:4, endln:140:35 + \_module_inst: work@oh_dsync (work@oh_fifo_async.rd_sync[3]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:135:4, endln:140:35 |UINT:0 |vpiTypespec: \_int_typespec: @@ -69867,7 +69867,7 @@ design: (work@oh_fifo_async) |vpiParameter: \_parameter: (work@oh_fifo_async.rd_sync[3].SYN), line:11:15, endln:11:18 |vpiParent: - \_module: work@oh_dsync (work@oh_fifo_async.rd_sync[3]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:135:4, endln:140:35 + \_module_inst: work@oh_dsync (work@oh_fifo_async.rd_sync[3]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:135:4, endln:140:35 |STRING:TRUE |vpiTypespec: \_string_typespec: @@ -69878,7 +69878,7 @@ design: (work@oh_fifo_async) |vpiParameter: \_parameter: (work@oh_fifo_async.rd_sync[3].TYPE), line:12:15, endln:12:19 |vpiParent: - \_module: work@oh_dsync (work@oh_fifo_async.rd_sync[3]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:135:4, endln:140:35 + \_module_inst: work@oh_dsync (work@oh_fifo_async.rd_sync[3]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:135:4, endln:140:35 |STRING:DEFAULT |vpiTypespec: \_string_typespec: @@ -69889,7 +69889,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:9:15, endln:9:27 |vpiParent: - \_module: work@oh_dsync (work@oh_fifo_async.rd_sync[3]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:135:4, endln:140:35 + \_module_inst: work@oh_dsync (work@oh_fifo_async.rd_sync[3]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:135:4, endln:140:35 |vpiOverriden:1 |vpiRhs: \_constant: , line:9:26, endln:9:27 @@ -69904,7 +69904,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:10:15, endln:10:27 |vpiParent: - \_module: work@oh_dsync (work@oh_fifo_async.rd_sync[3]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:135:4, endln:140:35 + \_module_inst: work@oh_dsync (work@oh_fifo_async.rd_sync[3]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:135:4, endln:140:35 |vpiRhs: \_constant: , line:10:26, endln:10:27 |vpiDecompile:0 @@ -69918,7 +69918,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:11:15, endln:11:32 |vpiParent: - \_module: work@oh_dsync (work@oh_fifo_async.rd_sync[3]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:135:4, endln:140:35 + \_module_inst: work@oh_dsync (work@oh_fifo_async.rd_sync[3]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:135:4, endln:140:35 |vpiOverriden:1 |vpiRhs: \_constant: , line:11:26, endln:11:32 @@ -69933,7 +69933,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:12:15, endln:12:35 |vpiParent: - \_module: work@oh_dsync (work@oh_fifo_async.rd_sync[3]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:135:4, endln:140:35 + \_module_inst: work@oh_dsync (work@oh_fifo_async.rd_sync[3]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:135:4, endln:140:35 |vpiRhs: \_constant: , line:12:26, endln:12:35 |vpiDecompile:DEFAULT @@ -69951,7 +69951,7 @@ design: (work@oh_fifo_async) |vpiNet: \_logic_net: (work@oh_fifo_async.rd_sync[3].clk), line:15:12, endln:15:15 |vpiParent: - \_module: work@oh_dsync (work@oh_fifo_async.rd_sync[3]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:135:4, endln:140:35 + \_module_inst: work@oh_dsync (work@oh_fifo_async.rd_sync[3]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:135:4, endln:140:35 |vpiTypespec: \_logic_typespec: , line:15:12, endln:15:12 |vpiName:clk @@ -69959,7 +69959,7 @@ design: (work@oh_fifo_async) |vpiNet: \_logic_net: (work@oh_fifo_async.rd_sync[3].nreset), line:16:12, endln:16:18 |vpiParent: - \_module: work@oh_dsync (work@oh_fifo_async.rd_sync[3]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:135:4, endln:140:35 + \_module_inst: work@oh_dsync (work@oh_fifo_async.rd_sync[3]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:135:4, endln:140:35 |vpiTypespec: \_logic_typespec: , line:16:12, endln:16:12 |vpiName:nreset @@ -69967,7 +69967,7 @@ design: (work@oh_fifo_async) |vpiNet: \_logic_net: (work@oh_fifo_async.rd_sync[3].din), line:17:12, endln:17:15 |vpiParent: - \_module: work@oh_dsync (work@oh_fifo_async.rd_sync[3]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:135:4, endln:140:35 + \_module_inst: work@oh_dsync (work@oh_fifo_async.rd_sync[3]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:135:4, endln:140:35 |vpiTypespec: \_logic_typespec: , line:17:12, endln:17:12 |vpiName:din @@ -69975,17 +69975,17 @@ design: (work@oh_fifo_async) |vpiNet: \_logic_net: (work@oh_fifo_async.rd_sync[3].dout), line:18:12, endln:18:16 |vpiParent: - \_module: work@oh_dsync (work@oh_fifo_async.rd_sync[3]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:135:4, endln:140:35 + \_module_inst: work@oh_dsync (work@oh_fifo_async.rd_sync[3]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:135:4, endln:140:35 |vpiTypespec: \_logic_typespec: , line:18:12, endln:18:12 |vpiName:dout |vpiFullName:work@oh_fifo_async.rd_sync[3].dout |vpiInstance: - \_module: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 + \_module_inst: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 |vpiPort: \_port: (clk), line:15:12, endln:15:15 |vpiParent: - \_module: work@oh_dsync (work@oh_fifo_async.rd_sync[3]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:135:4, endln:140:35 + \_module_inst: work@oh_dsync (work@oh_fifo_async.rd_sync[3]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:135:4, endln:140:35 |vpiName:clk |vpiDirection:1 |vpiHighConn: @@ -70007,11 +70007,11 @@ design: (work@oh_fifo_async) |vpiTypedef: \_logic_typespec: , line:15:12, endln:15:12 |vpiInstance: - \_module: work@oh_dsync (work@oh_fifo_async.rd_sync[3]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:135:4, endln:140:35 + \_module_inst: work@oh_dsync (work@oh_fifo_async.rd_sync[3]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:135:4, endln:140:35 |vpiPort: \_port: (nreset), line:16:12, endln:16:18 |vpiParent: - \_module: work@oh_dsync (work@oh_fifo_async.rd_sync[3]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:135:4, endln:140:35 + \_module_inst: work@oh_dsync (work@oh_fifo_async.rd_sync[3]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:135:4, endln:140:35 |vpiName:nreset |vpiDirection:1 |vpiHighConn: @@ -70033,11 +70033,11 @@ design: (work@oh_fifo_async) |vpiTypedef: \_logic_typespec: , line:16:12, endln:16:12 |vpiInstance: - \_module: work@oh_dsync (work@oh_fifo_async.rd_sync[3]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:135:4, endln:140:35 + \_module_inst: work@oh_dsync (work@oh_fifo_async.rd_sync[3]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:135:4, endln:140:35 |vpiPort: \_port: (din), line:17:12, endln:17:15 |vpiParent: - \_module: work@oh_dsync (work@oh_fifo_async.rd_sync[3]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:135:4, endln:140:35 + \_module_inst: work@oh_dsync (work@oh_fifo_async.rd_sync[3]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:135:4, endln:140:35 |vpiName:din |vpiDirection:1 |vpiHighConn: @@ -70075,11 +70075,11 @@ design: (work@oh_fifo_async) |vpiTypedef: \_logic_typespec: , line:17:12, endln:17:12 |vpiInstance: - \_module: work@oh_dsync (work@oh_fifo_async.rd_sync[3]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:135:4, endln:140:35 + \_module_inst: work@oh_dsync (work@oh_fifo_async.rd_sync[3]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:135:4, endln:140:35 |vpiPort: \_port: (dout), line:18:12, endln:18:16 |vpiParent: - \_module: work@oh_dsync (work@oh_fifo_async.rd_sync[3]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:135:4, endln:140:35 + \_module_inst: work@oh_dsync (work@oh_fifo_async.rd_sync[3]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:135:4, endln:140:35 |vpiName:dout |vpiDirection:2 |vpiHighConn: @@ -70117,11 +70117,11 @@ design: (work@oh_fifo_async) |vpiTypedef: \_logic_typespec: , line:18:12, endln:18:12 |vpiInstance: - \_module: work@oh_dsync (work@oh_fifo_async.rd_sync[3]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:135:4, endln:140:35 + \_module_inst: work@oh_dsync (work@oh_fifo_async.rd_sync[3]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:135:4, endln:140:35 |vpiGenScopeArray: \_gen_scope_array: (work@oh_fifo_async.rd_sync[3].genblk1), line:22:7, endln:42:5 |vpiParent: - \_module: work@oh_dsync (work@oh_fifo_async.rd_sync[3]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:135:4, endln:140:35 + \_module_inst: work@oh_dsync (work@oh_fifo_async.rd_sync[3]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:135:4, endln:140:35 |vpiName:genblk1 |vpiFullName:work@oh_fifo_async.rd_sync[3].genblk1 |vpiGenScope: @@ -70463,16 +70463,16 @@ design: (work@oh_fifo_async) |vpiFullName:work@oh_fifo_async.rd_sync[3].genblk1.dout |vpiActual: \_logic_net: (work@oh_fifo_async.rd_sync[3].dout), line:18:12, endln:18:16 - |vpiModule: - \_module: work@oh_dsync (work@oh_fifo_async.rd_sync[4]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:135:4, endln:140:35 + |vpiModuleInst: + \_module_inst: work@oh_dsync (work@oh_fifo_async.rd_sync[4]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:135:4, endln:140:35 |vpiParent: - \_module: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 + \_module_inst: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 |vpiName:rd_sync[4] |vpiFullName:work@oh_fifo_async.rd_sync[4] |vpiParameter: \_parameter: (work@oh_fifo_async.rd_sync[4].SYNCPIPE), line:9:15, endln:9:23 |vpiParent: - \_module: work@oh_dsync (work@oh_fifo_async.rd_sync[4]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:135:4, endln:140:35 + \_module_inst: work@oh_dsync (work@oh_fifo_async.rd_sync[4]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:135:4, endln:140:35 |UINT:2 |vpiTypespec: \_int_typespec: @@ -70483,7 +70483,7 @@ design: (work@oh_fifo_async) |vpiParameter: \_parameter: (work@oh_fifo_async.rd_sync[4].DELAY), line:10:15, endln:10:20 |vpiParent: - \_module: work@oh_dsync (work@oh_fifo_async.rd_sync[4]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:135:4, endln:140:35 + \_module_inst: work@oh_dsync (work@oh_fifo_async.rd_sync[4]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:135:4, endln:140:35 |UINT:0 |vpiTypespec: \_int_typespec: @@ -70494,7 +70494,7 @@ design: (work@oh_fifo_async) |vpiParameter: \_parameter: (work@oh_fifo_async.rd_sync[4].SYN), line:11:15, endln:11:18 |vpiParent: - \_module: work@oh_dsync (work@oh_fifo_async.rd_sync[4]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:135:4, endln:140:35 + \_module_inst: work@oh_dsync (work@oh_fifo_async.rd_sync[4]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:135:4, endln:140:35 |STRING:TRUE |vpiTypespec: \_string_typespec: @@ -70505,7 +70505,7 @@ design: (work@oh_fifo_async) |vpiParameter: \_parameter: (work@oh_fifo_async.rd_sync[4].TYPE), line:12:15, endln:12:19 |vpiParent: - \_module: work@oh_dsync (work@oh_fifo_async.rd_sync[4]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:135:4, endln:140:35 + \_module_inst: work@oh_dsync (work@oh_fifo_async.rd_sync[4]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:135:4, endln:140:35 |STRING:DEFAULT |vpiTypespec: \_string_typespec: @@ -70516,7 +70516,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:9:15, endln:9:27 |vpiParent: - \_module: work@oh_dsync (work@oh_fifo_async.rd_sync[4]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:135:4, endln:140:35 + \_module_inst: work@oh_dsync (work@oh_fifo_async.rd_sync[4]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:135:4, endln:140:35 |vpiOverriden:1 |vpiRhs: \_constant: , line:9:26, endln:9:27 @@ -70531,7 +70531,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:10:15, endln:10:27 |vpiParent: - \_module: work@oh_dsync (work@oh_fifo_async.rd_sync[4]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:135:4, endln:140:35 + \_module_inst: work@oh_dsync (work@oh_fifo_async.rd_sync[4]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:135:4, endln:140:35 |vpiRhs: \_constant: , line:10:26, endln:10:27 |vpiDecompile:0 @@ -70545,7 +70545,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:11:15, endln:11:32 |vpiParent: - \_module: work@oh_dsync (work@oh_fifo_async.rd_sync[4]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:135:4, endln:140:35 + \_module_inst: work@oh_dsync (work@oh_fifo_async.rd_sync[4]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:135:4, endln:140:35 |vpiOverriden:1 |vpiRhs: \_constant: , line:11:26, endln:11:32 @@ -70560,7 +70560,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:12:15, endln:12:35 |vpiParent: - \_module: work@oh_dsync (work@oh_fifo_async.rd_sync[4]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:135:4, endln:140:35 + \_module_inst: work@oh_dsync (work@oh_fifo_async.rd_sync[4]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:135:4, endln:140:35 |vpiRhs: \_constant: , line:12:26, endln:12:35 |vpiDecompile:DEFAULT @@ -70578,7 +70578,7 @@ design: (work@oh_fifo_async) |vpiNet: \_logic_net: (work@oh_fifo_async.rd_sync[4].clk), line:15:12, endln:15:15 |vpiParent: - \_module: work@oh_dsync (work@oh_fifo_async.rd_sync[4]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:135:4, endln:140:35 + \_module_inst: work@oh_dsync (work@oh_fifo_async.rd_sync[4]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:135:4, endln:140:35 |vpiTypespec: \_logic_typespec: , line:15:12, endln:15:12 |vpiName:clk @@ -70586,7 +70586,7 @@ design: (work@oh_fifo_async) |vpiNet: \_logic_net: (work@oh_fifo_async.rd_sync[4].nreset), line:16:12, endln:16:18 |vpiParent: - \_module: work@oh_dsync (work@oh_fifo_async.rd_sync[4]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:135:4, endln:140:35 + \_module_inst: work@oh_dsync (work@oh_fifo_async.rd_sync[4]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:135:4, endln:140:35 |vpiTypespec: \_logic_typespec: , line:16:12, endln:16:12 |vpiName:nreset @@ -70594,7 +70594,7 @@ design: (work@oh_fifo_async) |vpiNet: \_logic_net: (work@oh_fifo_async.rd_sync[4].din), line:17:12, endln:17:15 |vpiParent: - \_module: work@oh_dsync (work@oh_fifo_async.rd_sync[4]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:135:4, endln:140:35 + \_module_inst: work@oh_dsync (work@oh_fifo_async.rd_sync[4]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:135:4, endln:140:35 |vpiTypespec: \_logic_typespec: , line:17:12, endln:17:12 |vpiName:din @@ -70602,17 +70602,17 @@ design: (work@oh_fifo_async) |vpiNet: \_logic_net: (work@oh_fifo_async.rd_sync[4].dout), line:18:12, endln:18:16 |vpiParent: - \_module: work@oh_dsync (work@oh_fifo_async.rd_sync[4]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:135:4, endln:140:35 + \_module_inst: work@oh_dsync (work@oh_fifo_async.rd_sync[4]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:135:4, endln:140:35 |vpiTypespec: \_logic_typespec: , line:18:12, endln:18:12 |vpiName:dout |vpiFullName:work@oh_fifo_async.rd_sync[4].dout |vpiInstance: - \_module: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 + \_module_inst: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 |vpiPort: \_port: (clk), line:15:12, endln:15:15 |vpiParent: - \_module: work@oh_dsync (work@oh_fifo_async.rd_sync[4]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:135:4, endln:140:35 + \_module_inst: work@oh_dsync (work@oh_fifo_async.rd_sync[4]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:135:4, endln:140:35 |vpiName:clk |vpiDirection:1 |vpiHighConn: @@ -70634,11 +70634,11 @@ design: (work@oh_fifo_async) |vpiTypedef: \_logic_typespec: , line:15:12, endln:15:12 |vpiInstance: - \_module: work@oh_dsync (work@oh_fifo_async.rd_sync[4]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:135:4, endln:140:35 + \_module_inst: work@oh_dsync (work@oh_fifo_async.rd_sync[4]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:135:4, endln:140:35 |vpiPort: \_port: (nreset), line:16:12, endln:16:18 |vpiParent: - \_module: work@oh_dsync (work@oh_fifo_async.rd_sync[4]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:135:4, endln:140:35 + \_module_inst: work@oh_dsync (work@oh_fifo_async.rd_sync[4]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:135:4, endln:140:35 |vpiName:nreset |vpiDirection:1 |vpiHighConn: @@ -70660,11 +70660,11 @@ design: (work@oh_fifo_async) |vpiTypedef: \_logic_typespec: , line:16:12, endln:16:12 |vpiInstance: - \_module: work@oh_dsync (work@oh_fifo_async.rd_sync[4]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:135:4, endln:140:35 + \_module_inst: work@oh_dsync (work@oh_fifo_async.rd_sync[4]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:135:4, endln:140:35 |vpiPort: \_port: (din), line:17:12, endln:17:15 |vpiParent: - \_module: work@oh_dsync (work@oh_fifo_async.rd_sync[4]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:135:4, endln:140:35 + \_module_inst: work@oh_dsync (work@oh_fifo_async.rd_sync[4]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:135:4, endln:140:35 |vpiName:din |vpiDirection:1 |vpiHighConn: @@ -70702,11 +70702,11 @@ design: (work@oh_fifo_async) |vpiTypedef: \_logic_typespec: , line:17:12, endln:17:12 |vpiInstance: - \_module: work@oh_dsync (work@oh_fifo_async.rd_sync[4]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:135:4, endln:140:35 + \_module_inst: work@oh_dsync (work@oh_fifo_async.rd_sync[4]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:135:4, endln:140:35 |vpiPort: \_port: (dout), line:18:12, endln:18:16 |vpiParent: - \_module: work@oh_dsync (work@oh_fifo_async.rd_sync[4]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:135:4, endln:140:35 + \_module_inst: work@oh_dsync (work@oh_fifo_async.rd_sync[4]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:135:4, endln:140:35 |vpiName:dout |vpiDirection:2 |vpiHighConn: @@ -70744,11 +70744,11 @@ design: (work@oh_fifo_async) |vpiTypedef: \_logic_typespec: , line:18:12, endln:18:12 |vpiInstance: - \_module: work@oh_dsync (work@oh_fifo_async.rd_sync[4]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:135:4, endln:140:35 + \_module_inst: work@oh_dsync (work@oh_fifo_async.rd_sync[4]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:135:4, endln:140:35 |vpiGenScopeArray: \_gen_scope_array: (work@oh_fifo_async.rd_sync[4].genblk1), line:22:7, endln:42:5 |vpiParent: - \_module: work@oh_dsync (work@oh_fifo_async.rd_sync[4]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:135:4, endln:140:35 + \_module_inst: work@oh_dsync (work@oh_fifo_async.rd_sync[4]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:135:4, endln:140:35 |vpiName:genblk1 |vpiFullName:work@oh_fifo_async.rd_sync[4].genblk1 |vpiGenScope: @@ -71090,16 +71090,16 @@ design: (work@oh_fifo_async) |vpiFullName:work@oh_fifo_async.rd_sync[4].genblk1.dout |vpiActual: \_logic_net: (work@oh_fifo_async.rd_sync[4].dout), line:18:12, endln:18:16 - |vpiModule: - \_module: work@oh_dsync (work@oh_fifo_async.rd_sync[5]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:135:4, endln:140:35 + |vpiModuleInst: + \_module_inst: work@oh_dsync (work@oh_fifo_async.rd_sync[5]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:135:4, endln:140:35 |vpiParent: - \_module: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 + \_module_inst: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 |vpiName:rd_sync[5] |vpiFullName:work@oh_fifo_async.rd_sync[5] |vpiParameter: \_parameter: (work@oh_fifo_async.rd_sync[5].SYNCPIPE), line:9:15, endln:9:23 |vpiParent: - \_module: work@oh_dsync (work@oh_fifo_async.rd_sync[5]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:135:4, endln:140:35 + \_module_inst: work@oh_dsync (work@oh_fifo_async.rd_sync[5]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:135:4, endln:140:35 |UINT:2 |vpiTypespec: \_int_typespec: @@ -71110,7 +71110,7 @@ design: (work@oh_fifo_async) |vpiParameter: \_parameter: (work@oh_fifo_async.rd_sync[5].DELAY), line:10:15, endln:10:20 |vpiParent: - \_module: work@oh_dsync (work@oh_fifo_async.rd_sync[5]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:135:4, endln:140:35 + \_module_inst: work@oh_dsync (work@oh_fifo_async.rd_sync[5]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:135:4, endln:140:35 |UINT:0 |vpiTypespec: \_int_typespec: @@ -71121,7 +71121,7 @@ design: (work@oh_fifo_async) |vpiParameter: \_parameter: (work@oh_fifo_async.rd_sync[5].SYN), line:11:15, endln:11:18 |vpiParent: - \_module: work@oh_dsync (work@oh_fifo_async.rd_sync[5]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:135:4, endln:140:35 + \_module_inst: work@oh_dsync (work@oh_fifo_async.rd_sync[5]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:135:4, endln:140:35 |STRING:TRUE |vpiTypespec: \_string_typespec: @@ -71132,7 +71132,7 @@ design: (work@oh_fifo_async) |vpiParameter: \_parameter: (work@oh_fifo_async.rd_sync[5].TYPE), line:12:15, endln:12:19 |vpiParent: - \_module: work@oh_dsync (work@oh_fifo_async.rd_sync[5]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:135:4, endln:140:35 + \_module_inst: work@oh_dsync (work@oh_fifo_async.rd_sync[5]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:135:4, endln:140:35 |STRING:DEFAULT |vpiTypespec: \_string_typespec: @@ -71143,7 +71143,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:9:15, endln:9:27 |vpiParent: - \_module: work@oh_dsync (work@oh_fifo_async.rd_sync[5]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:135:4, endln:140:35 + \_module_inst: work@oh_dsync (work@oh_fifo_async.rd_sync[5]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:135:4, endln:140:35 |vpiOverriden:1 |vpiRhs: \_constant: , line:9:26, endln:9:27 @@ -71158,7 +71158,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:10:15, endln:10:27 |vpiParent: - \_module: work@oh_dsync (work@oh_fifo_async.rd_sync[5]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:135:4, endln:140:35 + \_module_inst: work@oh_dsync (work@oh_fifo_async.rd_sync[5]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:135:4, endln:140:35 |vpiRhs: \_constant: , line:10:26, endln:10:27 |vpiDecompile:0 @@ -71172,7 +71172,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:11:15, endln:11:32 |vpiParent: - \_module: work@oh_dsync (work@oh_fifo_async.rd_sync[5]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:135:4, endln:140:35 + \_module_inst: work@oh_dsync (work@oh_fifo_async.rd_sync[5]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:135:4, endln:140:35 |vpiOverriden:1 |vpiRhs: \_constant: , line:11:26, endln:11:32 @@ -71187,7 +71187,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:12:15, endln:12:35 |vpiParent: - \_module: work@oh_dsync (work@oh_fifo_async.rd_sync[5]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:135:4, endln:140:35 + \_module_inst: work@oh_dsync (work@oh_fifo_async.rd_sync[5]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:135:4, endln:140:35 |vpiRhs: \_constant: , line:12:26, endln:12:35 |vpiDecompile:DEFAULT @@ -71205,7 +71205,7 @@ design: (work@oh_fifo_async) |vpiNet: \_logic_net: (work@oh_fifo_async.rd_sync[5].clk), line:15:12, endln:15:15 |vpiParent: - \_module: work@oh_dsync (work@oh_fifo_async.rd_sync[5]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:135:4, endln:140:35 + \_module_inst: work@oh_dsync (work@oh_fifo_async.rd_sync[5]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:135:4, endln:140:35 |vpiTypespec: \_logic_typespec: , line:15:12, endln:15:12 |vpiName:clk @@ -71213,7 +71213,7 @@ design: (work@oh_fifo_async) |vpiNet: \_logic_net: (work@oh_fifo_async.rd_sync[5].nreset), line:16:12, endln:16:18 |vpiParent: - \_module: work@oh_dsync (work@oh_fifo_async.rd_sync[5]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:135:4, endln:140:35 + \_module_inst: work@oh_dsync (work@oh_fifo_async.rd_sync[5]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:135:4, endln:140:35 |vpiTypespec: \_logic_typespec: , line:16:12, endln:16:12 |vpiName:nreset @@ -71221,7 +71221,7 @@ design: (work@oh_fifo_async) |vpiNet: \_logic_net: (work@oh_fifo_async.rd_sync[5].din), line:17:12, endln:17:15 |vpiParent: - \_module: work@oh_dsync (work@oh_fifo_async.rd_sync[5]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:135:4, endln:140:35 + \_module_inst: work@oh_dsync (work@oh_fifo_async.rd_sync[5]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:135:4, endln:140:35 |vpiTypespec: \_logic_typespec: , line:17:12, endln:17:12 |vpiName:din @@ -71229,17 +71229,17 @@ design: (work@oh_fifo_async) |vpiNet: \_logic_net: (work@oh_fifo_async.rd_sync[5].dout), line:18:12, endln:18:16 |vpiParent: - \_module: work@oh_dsync (work@oh_fifo_async.rd_sync[5]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:135:4, endln:140:35 + \_module_inst: work@oh_dsync (work@oh_fifo_async.rd_sync[5]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:135:4, endln:140:35 |vpiTypespec: \_logic_typespec: , line:18:12, endln:18:12 |vpiName:dout |vpiFullName:work@oh_fifo_async.rd_sync[5].dout |vpiInstance: - \_module: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 + \_module_inst: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 |vpiPort: \_port: (clk), line:15:12, endln:15:15 |vpiParent: - \_module: work@oh_dsync (work@oh_fifo_async.rd_sync[5]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:135:4, endln:140:35 + \_module_inst: work@oh_dsync (work@oh_fifo_async.rd_sync[5]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:135:4, endln:140:35 |vpiName:clk |vpiDirection:1 |vpiHighConn: @@ -71261,11 +71261,11 @@ design: (work@oh_fifo_async) |vpiTypedef: \_logic_typespec: , line:15:12, endln:15:12 |vpiInstance: - \_module: work@oh_dsync (work@oh_fifo_async.rd_sync[5]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:135:4, endln:140:35 + \_module_inst: work@oh_dsync (work@oh_fifo_async.rd_sync[5]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:135:4, endln:140:35 |vpiPort: \_port: (nreset), line:16:12, endln:16:18 |vpiParent: - \_module: work@oh_dsync (work@oh_fifo_async.rd_sync[5]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:135:4, endln:140:35 + \_module_inst: work@oh_dsync (work@oh_fifo_async.rd_sync[5]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:135:4, endln:140:35 |vpiName:nreset |vpiDirection:1 |vpiHighConn: @@ -71287,11 +71287,11 @@ design: (work@oh_fifo_async) |vpiTypedef: \_logic_typespec: , line:16:12, endln:16:12 |vpiInstance: - \_module: work@oh_dsync (work@oh_fifo_async.rd_sync[5]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:135:4, endln:140:35 + \_module_inst: work@oh_dsync (work@oh_fifo_async.rd_sync[5]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:135:4, endln:140:35 |vpiPort: \_port: (din), line:17:12, endln:17:15 |vpiParent: - \_module: work@oh_dsync (work@oh_fifo_async.rd_sync[5]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:135:4, endln:140:35 + \_module_inst: work@oh_dsync (work@oh_fifo_async.rd_sync[5]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:135:4, endln:140:35 |vpiName:din |vpiDirection:1 |vpiHighConn: @@ -71329,11 +71329,11 @@ design: (work@oh_fifo_async) |vpiTypedef: \_logic_typespec: , line:17:12, endln:17:12 |vpiInstance: - \_module: work@oh_dsync (work@oh_fifo_async.rd_sync[5]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:135:4, endln:140:35 + \_module_inst: work@oh_dsync (work@oh_fifo_async.rd_sync[5]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:135:4, endln:140:35 |vpiPort: \_port: (dout), line:18:12, endln:18:16 |vpiParent: - \_module: work@oh_dsync (work@oh_fifo_async.rd_sync[5]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:135:4, endln:140:35 + \_module_inst: work@oh_dsync (work@oh_fifo_async.rd_sync[5]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:135:4, endln:140:35 |vpiName:dout |vpiDirection:2 |vpiHighConn: @@ -71371,11 +71371,11 @@ design: (work@oh_fifo_async) |vpiTypedef: \_logic_typespec: , line:18:12, endln:18:12 |vpiInstance: - \_module: work@oh_dsync (work@oh_fifo_async.rd_sync[5]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:135:4, endln:140:35 + \_module_inst: work@oh_dsync (work@oh_fifo_async.rd_sync[5]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:135:4, endln:140:35 |vpiGenScopeArray: \_gen_scope_array: (work@oh_fifo_async.rd_sync[5].genblk1), line:22:7, endln:42:5 |vpiParent: - \_module: work@oh_dsync (work@oh_fifo_async.rd_sync[5]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:135:4, endln:140:35 + \_module_inst: work@oh_dsync (work@oh_fifo_async.rd_sync[5]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:135:4, endln:140:35 |vpiName:genblk1 |vpiFullName:work@oh_fifo_async.rd_sync[5].genblk1 |vpiGenScope: @@ -71717,16 +71717,16 @@ design: (work@oh_fifo_async) |vpiFullName:work@oh_fifo_async.rd_sync[5].genblk1.dout |vpiActual: \_logic_net: (work@oh_fifo_async.rd_sync[5].dout), line:18:12, endln:18:16 - |vpiModule: - \_module: work@oh_memory_dp (work@oh_fifo_async.oh_memory_dp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:157:4, endln:184:33 + |vpiModuleInst: + \_module_inst: work@oh_memory_dp (work@oh_fifo_async.oh_memory_dp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:157:4, endln:184:33 |vpiParent: - \_module: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 + \_module_inst: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 |vpiName:oh_memory_dp |vpiFullName:work@oh_fifo_async.oh_memory_dp |vpiParameter: \_parameter: (work@oh_fifo_async.oh_memory_dp.N), line:9:15, endln:9:16 |vpiParent: - \_module: work@oh_memory_dp (work@oh_fifo_async.oh_memory_dp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:157:4, endln:184:33 + \_module_inst: work@oh_memory_dp (work@oh_fifo_async.oh_memory_dp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:157:4, endln:184:33 |UINT:32 |vpiTypespec: \_int_typespec: @@ -71737,7 +71737,7 @@ design: (work@oh_fifo_async) |vpiParameter: \_parameter: (work@oh_fifo_async.oh_memory_dp.DEPTH), line:10:15, endln:10:20 |vpiParent: - \_module: work@oh_memory_dp (work@oh_fifo_async.oh_memory_dp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:157:4, endln:184:33 + \_module_inst: work@oh_memory_dp (work@oh_fifo_async.oh_memory_dp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:157:4, endln:184:33 |UINT:32 |vpiTypespec: \_int_typespec: @@ -71748,7 +71748,7 @@ design: (work@oh_fifo_async) |vpiParameter: \_parameter: (work@oh_fifo_async.oh_memory_dp.REG), line:11:15, endln:11:18 |vpiParent: - \_module: work@oh_memory_dp (work@oh_fifo_async.oh_memory_dp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:157:4, endln:184:33 + \_module_inst: work@oh_memory_dp (work@oh_fifo_async.oh_memory_dp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:157:4, endln:184:33 |UINT:1 |vpiTypespec: \_int_typespec: @@ -71759,7 +71759,7 @@ design: (work@oh_fifo_async) |vpiParameter: \_parameter: (work@oh_fifo_async.oh_memory_dp.SYN), line:12:15, endln:12:18 |vpiParent: - \_module: work@oh_memory_dp (work@oh_fifo_async.oh_memory_dp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:157:4, endln:184:33 + \_module_inst: work@oh_memory_dp (work@oh_fifo_async.oh_memory_dp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:157:4, endln:184:33 |STRING:TRUE |vpiTypespec: \_string_typespec: @@ -71770,7 +71770,7 @@ design: (work@oh_fifo_async) |vpiParameter: \_parameter: (work@oh_fifo_async.oh_memory_dp.TYPE), line:13:15, endln:13:19 |vpiParent: - \_module: work@oh_memory_dp (work@oh_fifo_async.oh_memory_dp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:157:4, endln:184:33 + \_module_inst: work@oh_memory_dp (work@oh_fifo_async.oh_memory_dp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:157:4, endln:184:33 |STRING:DEFAULT |vpiTypespec: \_string_typespec: @@ -71781,7 +71781,7 @@ design: (work@oh_fifo_async) |vpiParameter: \_parameter: (work@oh_fifo_async.oh_memory_dp.SHAPE), line:14:15, endln:14:20 |vpiParent: - \_module: work@oh_memory_dp (work@oh_fifo_async.oh_memory_dp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:157:4, endln:184:33 + \_module_inst: work@oh_memory_dp (work@oh_fifo_async.oh_memory_dp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:157:4, endln:184:33 |STRING:SQUARE |vpiTypespec: \_string_typespec: @@ -71792,13 +71792,13 @@ design: (work@oh_fifo_async) |vpiParameter: \_parameter: (work@oh_fifo_async.oh_memory_dp.AW), line:15:15, endln:15:17 |vpiParent: - \_module: work@oh_memory_dp (work@oh_fifo_async.oh_memory_dp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:157:4, endln:184:33 + \_module_inst: work@oh_memory_dp (work@oh_fifo_async.oh_memory_dp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:157:4, endln:184:33 |vpiName:AW |vpiFullName:work@oh_fifo_async.oh_memory_dp.AW |vpiParamAssign: \_param_assign: , line:9:15, endln:9:27 |vpiParent: - \_module: work@oh_memory_dp (work@oh_fifo_async.oh_memory_dp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:157:4, endln:184:33 + \_module_inst: work@oh_memory_dp (work@oh_fifo_async.oh_memory_dp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:157:4, endln:184:33 |vpiOverriden:1 |vpiRhs: \_constant: , line:9:25, endln:9:27 @@ -71813,7 +71813,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:10:15, endln:10:27 |vpiParent: - \_module: work@oh_memory_dp (work@oh_fifo_async.oh_memory_dp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:157:4, endln:184:33 + \_module_inst: work@oh_memory_dp (work@oh_fifo_async.oh_memory_dp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:157:4, endln:184:33 |vpiOverriden:1 |vpiRhs: \_constant: , line:10:25, endln:10:27 @@ -71828,7 +71828,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:11:15, endln:11:26 |vpiParent: - \_module: work@oh_memory_dp (work@oh_fifo_async.oh_memory_dp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:157:4, endln:184:33 + \_module_inst: work@oh_memory_dp (work@oh_fifo_async.oh_memory_dp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:157:4, endln:184:33 |vpiOverriden:1 |vpiRhs: \_constant: , line:11:25, endln:11:26 @@ -71843,7 +71843,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:12:15, endln:12:31 |vpiParent: - \_module: work@oh_memory_dp (work@oh_fifo_async.oh_memory_dp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:157:4, endln:184:33 + \_module_inst: work@oh_memory_dp (work@oh_fifo_async.oh_memory_dp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:157:4, endln:184:33 |vpiOverriden:1 |vpiRhs: \_constant: , line:12:25, endln:12:31 @@ -71858,7 +71858,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:13:15, endln:13:34 |vpiParent: - \_module: work@oh_memory_dp (work@oh_fifo_async.oh_memory_dp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:157:4, endln:184:33 + \_module_inst: work@oh_memory_dp (work@oh_fifo_async.oh_memory_dp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:157:4, endln:184:33 |vpiRhs: \_constant: , line:13:25, endln:13:34 |vpiDecompile:DEFAULT @@ -71872,7 +71872,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:14:15, endln:14:33 |vpiParent: - \_module: work@oh_memory_dp (work@oh_fifo_async.oh_memory_dp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:157:4, endln:184:33 + \_module_inst: work@oh_memory_dp (work@oh_fifo_async.oh_memory_dp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:157:4, endln:184:33 |vpiOverriden:1 |vpiRhs: \_constant: , line:14:25, endln:14:33 @@ -71887,7 +71887,7 @@ design: (work@oh_fifo_async) |vpiParamAssign: \_param_assign: , line:15:15, endln:15:38 |vpiParent: - \_module: work@oh_memory_dp (work@oh_fifo_async.oh_memory_dp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:157:4, endln:184:33 + \_module_inst: work@oh_memory_dp (work@oh_fifo_async.oh_memory_dp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:157:4, endln:184:33 |vpiRhs: \_constant: , line:15:25, endln:15:38 |vpiDecompile:5 @@ -71903,7 +71903,7 @@ design: (work@oh_fifo_async) |vpiNet: \_logic_net: (work@oh_fifo_async.oh_memory_dp.wr_clk), line:18:16, endln:18:22 |vpiParent: - \_module: work@oh_memory_dp (work@oh_fifo_async.oh_memory_dp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:157:4, endln:184:33 + \_module_inst: work@oh_memory_dp (work@oh_fifo_async.oh_memory_dp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:157:4, endln:184:33 |vpiTypespec: \_logic_typespec: , line:18:16, endln:18:16 |vpiName:wr_clk @@ -71911,7 +71911,7 @@ design: (work@oh_fifo_async) |vpiNet: \_logic_net: (work@oh_fifo_async.oh_memory_dp.wr_en), line:19:16, endln:19:21 |vpiParent: - \_module: work@oh_memory_dp (work@oh_fifo_async.oh_memory_dp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:157:4, endln:184:33 + \_module_inst: work@oh_memory_dp (work@oh_fifo_async.oh_memory_dp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:157:4, endln:184:33 |vpiTypespec: \_logic_typespec: , line:19:16, endln:19:16 |vpiName:wr_en @@ -71919,7 +71919,7 @@ design: (work@oh_fifo_async) |vpiNet: \_logic_net: (work@oh_fifo_async.oh_memory_dp.wr_wem), line:20:20, endln:20:26 |vpiParent: - \_module: work@oh_memory_dp (work@oh_fifo_async.oh_memory_dp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:157:4, endln:184:33 + \_module_inst: work@oh_memory_dp (work@oh_fifo_async.oh_memory_dp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:157:4, endln:184:33 |vpiTypespec: \_logic_typespec: , line:20:11, endln:20:18 |vpiRange: @@ -71945,7 +71945,7 @@ design: (work@oh_fifo_async) |vpiNet: \_logic_net: (work@oh_fifo_async.oh_memory_dp.wr_addr), line:21:21, endln:21:28 |vpiParent: - \_module: work@oh_memory_dp (work@oh_fifo_async.oh_memory_dp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:157:4, endln:184:33 + \_module_inst: work@oh_memory_dp (work@oh_fifo_async.oh_memory_dp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:157:4, endln:184:33 |vpiTypespec: \_logic_typespec: , line:21:11, endln:21:19 |vpiRange: @@ -71971,7 +71971,7 @@ design: (work@oh_fifo_async) |vpiNet: \_logic_net: (work@oh_fifo_async.oh_memory_dp.wr_din), line:22:20, endln:22:26 |vpiParent: - \_module: work@oh_memory_dp (work@oh_fifo_async.oh_memory_dp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:157:4, endln:184:33 + \_module_inst: work@oh_memory_dp (work@oh_fifo_async.oh_memory_dp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:157:4, endln:184:33 |vpiTypespec: \_logic_typespec: , line:22:11, endln:22:18 |vpiRange: @@ -71997,7 +71997,7 @@ design: (work@oh_fifo_async) |vpiNet: \_logic_net: (work@oh_fifo_async.oh_memory_dp.rd_clk), line:23:16, endln:23:22 |vpiParent: - \_module: work@oh_memory_dp (work@oh_fifo_async.oh_memory_dp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:157:4, endln:184:33 + \_module_inst: work@oh_memory_dp (work@oh_fifo_async.oh_memory_dp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:157:4, endln:184:33 |vpiTypespec: \_logic_typespec: , line:23:16, endln:23:16 |vpiName:rd_clk @@ -72005,7 +72005,7 @@ design: (work@oh_fifo_async) |vpiNet: \_logic_net: (work@oh_fifo_async.oh_memory_dp.rd_en), line:24:16, endln:24:21 |vpiParent: - \_module: work@oh_memory_dp (work@oh_fifo_async.oh_memory_dp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:157:4, endln:184:33 + \_module_inst: work@oh_memory_dp (work@oh_fifo_async.oh_memory_dp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:157:4, endln:184:33 |vpiTypespec: \_logic_typespec: , line:24:16, endln:24:16 |vpiName:rd_en @@ -72013,7 +72013,7 @@ design: (work@oh_fifo_async) |vpiNet: \_logic_net: (work@oh_fifo_async.oh_memory_dp.rd_addr), line:25:21, endln:25:28 |vpiParent: - \_module: work@oh_memory_dp (work@oh_fifo_async.oh_memory_dp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:157:4, endln:184:33 + \_module_inst: work@oh_memory_dp (work@oh_fifo_async.oh_memory_dp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:157:4, endln:184:33 |vpiTypespec: \_logic_typespec: , line:25:11, endln:25:19 |vpiRange: @@ -72039,7 +72039,7 @@ design: (work@oh_fifo_async) |vpiNet: \_logic_net: (work@oh_fifo_async.oh_memory_dp.rd_dout), line:26:20, endln:26:27 |vpiParent: - \_module: work@oh_memory_dp (work@oh_fifo_async.oh_memory_dp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:157:4, endln:184:33 + \_module_inst: work@oh_memory_dp (work@oh_fifo_async.oh_memory_dp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:157:4, endln:184:33 |vpiTypespec: \_logic_typespec: , line:26:12, endln:26:19 |vpiRange: @@ -72065,7 +72065,7 @@ design: (work@oh_fifo_async) |vpiNet: \_logic_net: (work@oh_fifo_async.oh_memory_dp.bist_en), line:28:16, endln:28:23 |vpiParent: - \_module: work@oh_memory_dp (work@oh_fifo_async.oh_memory_dp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:157:4, endln:184:33 + \_module_inst: work@oh_memory_dp (work@oh_fifo_async.oh_memory_dp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:157:4, endln:184:33 |vpiTypespec: \_logic_typespec: , line:28:16, endln:28:16 |vpiName:bist_en @@ -72073,7 +72073,7 @@ design: (work@oh_fifo_async) |vpiNet: \_logic_net: (work@oh_fifo_async.oh_memory_dp.bist_we), line:29:16, endln:29:23 |vpiParent: - \_module: work@oh_memory_dp (work@oh_fifo_async.oh_memory_dp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:157:4, endln:184:33 + \_module_inst: work@oh_memory_dp (work@oh_fifo_async.oh_memory_dp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:157:4, endln:184:33 |vpiTypespec: \_logic_typespec: , line:29:16, endln:29:16 |vpiName:bist_we @@ -72081,7 +72081,7 @@ design: (work@oh_fifo_async) |vpiNet: \_logic_net: (work@oh_fifo_async.oh_memory_dp.bist_wem), line:30:20, endln:30:28 |vpiParent: - \_module: work@oh_memory_dp (work@oh_fifo_async.oh_memory_dp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:157:4, endln:184:33 + \_module_inst: work@oh_memory_dp (work@oh_fifo_async.oh_memory_dp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:157:4, endln:184:33 |vpiTypespec: \_logic_typespec: , line:30:11, endln:30:18 |vpiRange: @@ -72107,7 +72107,7 @@ design: (work@oh_fifo_async) |vpiNet: \_logic_net: (work@oh_fifo_async.oh_memory_dp.bist_addr), line:31:21, endln:31:30 |vpiParent: - \_module: work@oh_memory_dp (work@oh_fifo_async.oh_memory_dp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:157:4, endln:184:33 + \_module_inst: work@oh_memory_dp (work@oh_fifo_async.oh_memory_dp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:157:4, endln:184:33 |vpiTypespec: \_logic_typespec: , line:31:11, endln:31:19 |vpiRange: @@ -72133,7 +72133,7 @@ design: (work@oh_fifo_async) |vpiNet: \_logic_net: (work@oh_fifo_async.oh_memory_dp.bist_din), line:32:20, endln:32:28 |vpiParent: - \_module: work@oh_memory_dp (work@oh_fifo_async.oh_memory_dp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:157:4, endln:184:33 + \_module_inst: work@oh_memory_dp (work@oh_fifo_async.oh_memory_dp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:157:4, endln:184:33 |vpiTypespec: \_logic_typespec: , line:32:11, endln:32:18 |vpiRange: @@ -72159,7 +72159,7 @@ design: (work@oh_fifo_async) |vpiNet: \_logic_net: (work@oh_fifo_async.oh_memory_dp.shutdown), line:34:16, endln:34:24 |vpiParent: - \_module: work@oh_memory_dp (work@oh_fifo_async.oh_memory_dp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:157:4, endln:184:33 + \_module_inst: work@oh_memory_dp (work@oh_fifo_async.oh_memory_dp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:157:4, endln:184:33 |vpiTypespec: \_logic_typespec: , line:34:16, endln:34:16 |vpiName:shutdown @@ -72167,7 +72167,7 @@ design: (work@oh_fifo_async) |vpiNet: \_logic_net: (work@oh_fifo_async.oh_memory_dp.vss), line:35:16, endln:35:19 |vpiParent: - \_module: work@oh_memory_dp (work@oh_fifo_async.oh_memory_dp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:157:4, endln:184:33 + \_module_inst: work@oh_memory_dp (work@oh_fifo_async.oh_memory_dp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:157:4, endln:184:33 |vpiTypespec: \_logic_typespec: , line:35:16, endln:35:16 |vpiName:vss @@ -72175,7 +72175,7 @@ design: (work@oh_fifo_async) |vpiNet: \_logic_net: (work@oh_fifo_async.oh_memory_dp.vdd), line:36:16, endln:36:19 |vpiParent: - \_module: work@oh_memory_dp (work@oh_fifo_async.oh_memory_dp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:157:4, endln:184:33 + \_module_inst: work@oh_memory_dp (work@oh_fifo_async.oh_memory_dp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:157:4, endln:184:33 |vpiTypespec: \_logic_typespec: , line:36:16, endln:36:16 |vpiName:vdd @@ -72183,7 +72183,7 @@ design: (work@oh_fifo_async) |vpiNet: \_logic_net: (work@oh_fifo_async.oh_memory_dp.vddio), line:37:16, endln:37:21 |vpiParent: - \_module: work@oh_memory_dp (work@oh_fifo_async.oh_memory_dp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:157:4, endln:184:33 + \_module_inst: work@oh_memory_dp (work@oh_fifo_async.oh_memory_dp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:157:4, endln:184:33 |vpiTypespec: \_logic_typespec: , line:37:16, endln:37:16 |vpiName:vddio @@ -72191,7 +72191,7 @@ design: (work@oh_fifo_async) |vpiNet: \_logic_net: (work@oh_fifo_async.oh_memory_dp.memconfig), line:38:21, endln:38:30 |vpiParent: - \_module: work@oh_memory_dp (work@oh_fifo_async.oh_memory_dp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:157:4, endln:184:33 + \_module_inst: work@oh_memory_dp (work@oh_fifo_async.oh_memory_dp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:157:4, endln:184:33 |vpiTypespec: \_logic_typespec: , line:38:11, endln:38:16 |vpiRange: @@ -72217,7 +72217,7 @@ design: (work@oh_fifo_async) |vpiNet: \_logic_net: (work@oh_fifo_async.oh_memory_dp.memrepair), line:39:21, endln:39:30 |vpiParent: - \_module: work@oh_memory_dp (work@oh_fifo_async.oh_memory_dp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:157:4, endln:184:33 + \_module_inst: work@oh_memory_dp (work@oh_fifo_async.oh_memory_dp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:157:4, endln:184:33 |vpiTypespec: \_logic_typespec: , line:39:11, endln:39:16 |vpiRange: @@ -72241,11 +72241,11 @@ design: (work@oh_fifo_async) |vpiName:memrepair |vpiFullName:work@oh_fifo_async.oh_memory_dp.memrepair |vpiInstance: - \_module: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 + \_module_inst: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 |vpiPort: \_port: (wr_clk), line:18:16, endln:18:22 |vpiParent: - \_module: work@oh_memory_dp (work@oh_fifo_async.oh_memory_dp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:157:4, endln:184:33 + \_module_inst: work@oh_memory_dp (work@oh_fifo_async.oh_memory_dp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:157:4, endln:184:33 |vpiName:wr_clk |vpiDirection:1 |vpiHighConn: @@ -72267,11 +72267,11 @@ design: (work@oh_fifo_async) |vpiTypedef: \_logic_typespec: , line:18:16, endln:18:16 |vpiInstance: - \_module: work@oh_memory_dp (work@oh_fifo_async.oh_memory_dp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:157:4, endln:184:33 + \_module_inst: work@oh_memory_dp (work@oh_fifo_async.oh_memory_dp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:157:4, endln:184:33 |vpiPort: \_port: (wr_en), line:19:16, endln:19:21 |vpiParent: - \_module: work@oh_memory_dp (work@oh_fifo_async.oh_memory_dp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:157:4, endln:184:33 + \_module_inst: work@oh_memory_dp (work@oh_fifo_async.oh_memory_dp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:157:4, endln:184:33 |vpiName:wr_en |vpiDirection:1 |vpiHighConn: @@ -72293,11 +72293,11 @@ design: (work@oh_fifo_async) |vpiTypedef: \_logic_typespec: , line:19:16, endln:19:16 |vpiInstance: - \_module: work@oh_memory_dp (work@oh_fifo_async.oh_memory_dp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:157:4, endln:184:33 + \_module_inst: work@oh_memory_dp (work@oh_fifo_async.oh_memory_dp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:157:4, endln:184:33 |vpiPort: \_port: (wr_wem), line:20:20, endln:20:26 |vpiParent: - \_module: work@oh_memory_dp (work@oh_fifo_async.oh_memory_dp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:157:4, endln:184:33 + \_module_inst: work@oh_memory_dp (work@oh_fifo_async.oh_memory_dp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:157:4, endln:184:33 |vpiName:wr_wem |vpiDirection:1 |vpiHighConn: @@ -72340,11 +72340,11 @@ design: (work@oh_fifo_async) |UINT:0 |vpiConstType:9 |vpiInstance: - \_module: work@oh_memory_dp (work@oh_fifo_async.oh_memory_dp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:157:4, endln:184:33 + \_module_inst: work@oh_memory_dp (work@oh_fifo_async.oh_memory_dp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:157:4, endln:184:33 |vpiPort: \_port: (wr_addr), line:21:21, endln:21:28 |vpiParent: - \_module: work@oh_memory_dp (work@oh_fifo_async.oh_memory_dp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:157:4, endln:184:33 + \_module_inst: work@oh_memory_dp (work@oh_fifo_async.oh_memory_dp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:157:4, endln:184:33 |vpiName:wr_addr |vpiDirection:1 |vpiHighConn: @@ -72417,11 +72417,11 @@ design: (work@oh_fifo_async) |UINT:0 |vpiConstType:9 |vpiInstance: - \_module: work@oh_memory_dp (work@oh_fifo_async.oh_memory_dp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:157:4, endln:184:33 + \_module_inst: work@oh_memory_dp (work@oh_fifo_async.oh_memory_dp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:157:4, endln:184:33 |vpiPort: \_port: (wr_din), line:22:20, endln:22:26 |vpiParent: - \_module: work@oh_memory_dp (work@oh_fifo_async.oh_memory_dp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:157:4, endln:184:33 + \_module_inst: work@oh_memory_dp (work@oh_fifo_async.oh_memory_dp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:157:4, endln:184:33 |vpiName:wr_din |vpiDirection:1 |vpiHighConn: @@ -72498,11 +72498,11 @@ design: (work@oh_fifo_async) |UINT:0 |vpiConstType:9 |vpiInstance: - \_module: work@oh_memory_dp (work@oh_fifo_async.oh_memory_dp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:157:4, endln:184:33 + \_module_inst: work@oh_memory_dp (work@oh_fifo_async.oh_memory_dp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:157:4, endln:184:33 |vpiPort: \_port: (rd_clk), line:23:16, endln:23:22 |vpiParent: - \_module: work@oh_memory_dp (work@oh_fifo_async.oh_memory_dp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:157:4, endln:184:33 + \_module_inst: work@oh_memory_dp (work@oh_fifo_async.oh_memory_dp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:157:4, endln:184:33 |vpiName:rd_clk |vpiDirection:1 |vpiHighConn: @@ -72524,11 +72524,11 @@ design: (work@oh_fifo_async) |vpiTypedef: \_logic_typespec: , line:23:16, endln:23:16 |vpiInstance: - \_module: work@oh_memory_dp (work@oh_fifo_async.oh_memory_dp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:157:4, endln:184:33 + \_module_inst: work@oh_memory_dp (work@oh_fifo_async.oh_memory_dp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:157:4, endln:184:33 |vpiPort: \_port: (rd_en), line:24:16, endln:24:21 |vpiParent: - \_module: work@oh_memory_dp (work@oh_fifo_async.oh_memory_dp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:157:4, endln:184:33 + \_module_inst: work@oh_memory_dp (work@oh_fifo_async.oh_memory_dp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:157:4, endln:184:33 |vpiName:rd_en |vpiDirection:1 |vpiHighConn: @@ -72550,11 +72550,11 @@ design: (work@oh_fifo_async) |vpiTypedef: \_logic_typespec: , line:24:16, endln:24:16 |vpiInstance: - \_module: work@oh_memory_dp (work@oh_fifo_async.oh_memory_dp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:157:4, endln:184:33 + \_module_inst: work@oh_memory_dp (work@oh_fifo_async.oh_memory_dp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:157:4, endln:184:33 |vpiPort: \_port: (rd_addr), line:25:21, endln:25:28 |vpiParent: - \_module: work@oh_memory_dp (work@oh_fifo_async.oh_memory_dp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:157:4, endln:184:33 + \_module_inst: work@oh_memory_dp (work@oh_fifo_async.oh_memory_dp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:157:4, endln:184:33 |vpiName:rd_addr |vpiDirection:1 |vpiHighConn: @@ -72627,11 +72627,11 @@ design: (work@oh_fifo_async) |UINT:0 |vpiConstType:9 |vpiInstance: - \_module: work@oh_memory_dp (work@oh_fifo_async.oh_memory_dp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:157:4, endln:184:33 + \_module_inst: work@oh_memory_dp (work@oh_fifo_async.oh_memory_dp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:157:4, endln:184:33 |vpiPort: \_port: (rd_dout), line:26:20, endln:26:27 |vpiParent: - \_module: work@oh_memory_dp (work@oh_fifo_async.oh_memory_dp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:157:4, endln:184:33 + \_module_inst: work@oh_memory_dp (work@oh_fifo_async.oh_memory_dp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:157:4, endln:184:33 |vpiName:rd_dout |vpiDirection:2 |vpiHighConn: @@ -72708,11 +72708,11 @@ design: (work@oh_fifo_async) |UINT:0 |vpiConstType:9 |vpiInstance: - \_module: work@oh_memory_dp (work@oh_fifo_async.oh_memory_dp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:157:4, endln:184:33 + \_module_inst: work@oh_memory_dp (work@oh_fifo_async.oh_memory_dp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:157:4, endln:184:33 |vpiPort: \_port: (bist_en), line:28:16, endln:28:23 |vpiParent: - \_module: work@oh_memory_dp (work@oh_fifo_async.oh_memory_dp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:157:4, endln:184:33 + \_module_inst: work@oh_memory_dp (work@oh_fifo_async.oh_memory_dp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:157:4, endln:184:33 |vpiName:bist_en |vpiDirection:1 |vpiHighConn: @@ -72734,11 +72734,11 @@ design: (work@oh_fifo_async) |vpiTypedef: \_logic_typespec: , line:28:16, endln:28:16 |vpiInstance: - \_module: work@oh_memory_dp (work@oh_fifo_async.oh_memory_dp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:157:4, endln:184:33 + \_module_inst: work@oh_memory_dp (work@oh_fifo_async.oh_memory_dp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:157:4, endln:184:33 |vpiPort: \_port: (bist_we), line:29:16, endln:29:23 |vpiParent: - \_module: work@oh_memory_dp (work@oh_fifo_async.oh_memory_dp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:157:4, endln:184:33 + \_module_inst: work@oh_memory_dp (work@oh_fifo_async.oh_memory_dp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:157:4, endln:184:33 |vpiName:bist_we |vpiDirection:1 |vpiHighConn: @@ -72760,11 +72760,11 @@ design: (work@oh_fifo_async) |vpiTypedef: \_logic_typespec: , line:29:16, endln:29:16 |vpiInstance: - \_module: work@oh_memory_dp (work@oh_fifo_async.oh_memory_dp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:157:4, endln:184:33 + \_module_inst: work@oh_memory_dp (work@oh_fifo_async.oh_memory_dp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:157:4, endln:184:33 |vpiPort: \_port: (bist_wem), line:30:20, endln:30:28 |vpiParent: - \_module: work@oh_memory_dp (work@oh_fifo_async.oh_memory_dp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:157:4, endln:184:33 + \_module_inst: work@oh_memory_dp (work@oh_fifo_async.oh_memory_dp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:157:4, endln:184:33 |vpiName:bist_wem |vpiDirection:1 |vpiHighConn: @@ -72841,11 +72841,11 @@ design: (work@oh_fifo_async) |UINT:0 |vpiConstType:9 |vpiInstance: - \_module: work@oh_memory_dp (work@oh_fifo_async.oh_memory_dp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:157:4, endln:184:33 + \_module_inst: work@oh_memory_dp (work@oh_fifo_async.oh_memory_dp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:157:4, endln:184:33 |vpiPort: \_port: (bist_addr), line:31:21, endln:31:30 |vpiParent: - \_module: work@oh_memory_dp (work@oh_fifo_async.oh_memory_dp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:157:4, endln:184:33 + \_module_inst: work@oh_memory_dp (work@oh_fifo_async.oh_memory_dp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:157:4, endln:184:33 |vpiName:bist_addr |vpiDirection:1 |vpiHighConn: @@ -72918,11 +72918,11 @@ design: (work@oh_fifo_async) |UINT:0 |vpiConstType:9 |vpiInstance: - \_module: work@oh_memory_dp (work@oh_fifo_async.oh_memory_dp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:157:4, endln:184:33 + \_module_inst: work@oh_memory_dp (work@oh_fifo_async.oh_memory_dp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:157:4, endln:184:33 |vpiPort: \_port: (bist_din), line:32:20, endln:32:28 |vpiParent: - \_module: work@oh_memory_dp (work@oh_fifo_async.oh_memory_dp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:157:4, endln:184:33 + \_module_inst: work@oh_memory_dp (work@oh_fifo_async.oh_memory_dp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:157:4, endln:184:33 |vpiName:bist_din |vpiDirection:1 |vpiHighConn: @@ -72999,11 +72999,11 @@ design: (work@oh_fifo_async) |UINT:0 |vpiConstType:9 |vpiInstance: - \_module: work@oh_memory_dp (work@oh_fifo_async.oh_memory_dp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:157:4, endln:184:33 + \_module_inst: work@oh_memory_dp (work@oh_fifo_async.oh_memory_dp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:157:4, endln:184:33 |vpiPort: \_port: (shutdown), line:34:16, endln:34:24 |vpiParent: - \_module: work@oh_memory_dp (work@oh_fifo_async.oh_memory_dp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:157:4, endln:184:33 + \_module_inst: work@oh_memory_dp (work@oh_fifo_async.oh_memory_dp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:157:4, endln:184:33 |vpiName:shutdown |vpiDirection:1 |vpiHighConn: @@ -73025,11 +73025,11 @@ design: (work@oh_fifo_async) |vpiTypedef: \_logic_typespec: , line:34:16, endln:34:16 |vpiInstance: - \_module: work@oh_memory_dp (work@oh_fifo_async.oh_memory_dp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:157:4, endln:184:33 + \_module_inst: work@oh_memory_dp (work@oh_fifo_async.oh_memory_dp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:157:4, endln:184:33 |vpiPort: \_port: (vss), line:35:16, endln:35:19 |vpiParent: - \_module: work@oh_memory_dp (work@oh_fifo_async.oh_memory_dp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:157:4, endln:184:33 + \_module_inst: work@oh_memory_dp (work@oh_fifo_async.oh_memory_dp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:157:4, endln:184:33 |vpiName:vss |vpiDirection:1 |vpiHighConn: @@ -73051,11 +73051,11 @@ design: (work@oh_fifo_async) |vpiTypedef: \_logic_typespec: , line:35:16, endln:35:16 |vpiInstance: - \_module: work@oh_memory_dp (work@oh_fifo_async.oh_memory_dp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:157:4, endln:184:33 + \_module_inst: work@oh_memory_dp (work@oh_fifo_async.oh_memory_dp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:157:4, endln:184:33 |vpiPort: \_port: (vdd), line:36:16, endln:36:19 |vpiParent: - \_module: work@oh_memory_dp (work@oh_fifo_async.oh_memory_dp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:157:4, endln:184:33 + \_module_inst: work@oh_memory_dp (work@oh_fifo_async.oh_memory_dp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:157:4, endln:184:33 |vpiName:vdd |vpiDirection:1 |vpiHighConn: @@ -73077,11 +73077,11 @@ design: (work@oh_fifo_async) |vpiTypedef: \_logic_typespec: , line:36:16, endln:36:16 |vpiInstance: - \_module: work@oh_memory_dp (work@oh_fifo_async.oh_memory_dp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:157:4, endln:184:33 + \_module_inst: work@oh_memory_dp (work@oh_fifo_async.oh_memory_dp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:157:4, endln:184:33 |vpiPort: \_port: (vddio), line:37:16, endln:37:21 |vpiParent: - \_module: work@oh_memory_dp (work@oh_fifo_async.oh_memory_dp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:157:4, endln:184:33 + \_module_inst: work@oh_memory_dp (work@oh_fifo_async.oh_memory_dp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:157:4, endln:184:33 |vpiName:vddio |vpiDirection:1 |vpiHighConn: @@ -73103,11 +73103,11 @@ design: (work@oh_fifo_async) |vpiTypedef: \_logic_typespec: , line:37:16, endln:37:16 |vpiInstance: - \_module: work@oh_memory_dp (work@oh_fifo_async.oh_memory_dp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:157:4, endln:184:33 + \_module_inst: work@oh_memory_dp (work@oh_fifo_async.oh_memory_dp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:157:4, endln:184:33 |vpiPort: \_port: (memconfig), line:38:21, endln:38:30 |vpiParent: - \_module: work@oh_memory_dp (work@oh_fifo_async.oh_memory_dp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:157:4, endln:184:33 + \_module_inst: work@oh_memory_dp (work@oh_fifo_async.oh_memory_dp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:157:4, endln:184:33 |vpiName:memconfig |vpiDirection:1 |vpiHighConn: @@ -73165,11 +73165,11 @@ design: (work@oh_fifo_async) |UINT:0 |vpiConstType:9 |vpiInstance: - \_module: work@oh_memory_dp (work@oh_fifo_async.oh_memory_dp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:157:4, endln:184:33 + \_module_inst: work@oh_memory_dp (work@oh_fifo_async.oh_memory_dp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:157:4, endln:184:33 |vpiPort: \_port: (memrepair), line:39:21, endln:39:30 |vpiParent: - \_module: work@oh_memory_dp (work@oh_fifo_async.oh_memory_dp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:157:4, endln:184:33 + \_module_inst: work@oh_memory_dp (work@oh_fifo_async.oh_memory_dp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:157:4, endln:184:33 |vpiName:memrepair |vpiDirection:1 |vpiHighConn: @@ -73227,11 +73227,11 @@ design: (work@oh_fifo_async) |UINT:0 |vpiConstType:9 |vpiInstance: - \_module: work@oh_memory_dp (work@oh_fifo_async.oh_memory_dp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:157:4, endln:184:33 + \_module_inst: work@oh_memory_dp (work@oh_fifo_async.oh_memory_dp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:157:4, endln:184:33 |vpiGenScopeArray: \_gen_scope_array: (work@oh_fifo_async.oh_memory_dp.genblk1), line:43:7, endln:76:10 |vpiParent: - \_module: work@oh_memory_dp (work@oh_fifo_async.oh_memory_dp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:157:4, endln:184:33 + \_module_inst: work@oh_memory_dp (work@oh_fifo_async.oh_memory_dp), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:157:4, endln:184:33 |vpiName:genblk1 |vpiFullName:work@oh_fifo_async.oh_memory_dp.genblk1 |vpiGenScope: @@ -73973,87 +73973,87 @@ design: (work@oh_fifo_async) |UINT:0 |vpiConstType:9 |vpiModuleArray: - \_module_array: (work@oh_dsync), line:121:4, endln:121:11 + \_module_array: (work@oh_dsync), line:137:4, endln:137:11 |vpiParent: - \_module: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 - |vpiName:wr_sync + \_module_inst: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 + |vpiName:rd_sync |vpiFullName:work@oh_dsync |vpiRange: - \_range: , line:121:11, endln:121:17 + \_range: , line:137:11, endln:137:17 |vpiLeftRange: - \_constant: , line:121:12, endln:121:14 + \_constant: , line:137:12, endln:137:14 |vpiParent: - \_range: , line:121:11, endln:121:17 + \_range: , line:137:11, endln:137:17 |vpiDecompile:5 |vpiSize:64 |UINT:5 |vpiConstType:9 |vpiRightRange: - \_constant: , line:121:15, endln:121:16 + \_constant: , line:137:15, endln:137:16 |vpiParent: - \_range: , line:121:11, endln:121:17 + \_range: , line:137:11, endln:137:17 |vpiDecompile:0 |vpiSize:64 |UINT:0 |vpiConstType:9 - |vpiModule: - \_module: work@oh_dsync (work@oh_fifo_async.wr_sync[0]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:119:4, endln:124:35 - |vpiModule: - \_module: work@oh_dsync (work@oh_fifo_async.wr_sync[1]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:119:4, endln:124:35 - |vpiModule: - \_module: work@oh_dsync (work@oh_fifo_async.wr_sync[2]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:119:4, endln:124:35 - |vpiModule: - \_module: work@oh_dsync (work@oh_fifo_async.wr_sync[3]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:119:4, endln:124:35 - |vpiModule: - \_module: work@oh_dsync (work@oh_fifo_async.wr_sync[4]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:119:4, endln:124:35 - |vpiModule: - \_module: work@oh_dsync (work@oh_fifo_async.wr_sync[5]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:119:4, endln:124:35 + |vpiModuleInst: + \_module_inst: work@oh_dsync (work@oh_fifo_async.rd_sync[0]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:135:4, endln:140:35 + |vpiModuleInst: + \_module_inst: work@oh_dsync (work@oh_fifo_async.rd_sync[1]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:135:4, endln:140:35 + |vpiModuleInst: + \_module_inst: work@oh_dsync (work@oh_fifo_async.rd_sync[2]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:135:4, endln:140:35 + |vpiModuleInst: + \_module_inst: work@oh_dsync (work@oh_fifo_async.rd_sync[3]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:135:4, endln:140:35 + |vpiModuleInst: + \_module_inst: work@oh_dsync (work@oh_fifo_async.rd_sync[4]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:135:4, endln:140:35 + |vpiModuleInst: + \_module_inst: work@oh_dsync (work@oh_fifo_async.rd_sync[5]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:135:4, endln:140:35 |vpiElemTypespec: - \_module_typespec: (oh_dsync), line:119:4, endln:119:12 + \_module_typespec: (oh_dsync), line:135:4, endln:135:12 |vpiName:oh_dsync |vpiModuleArray: - \_module_array: (work@oh_dsync), line:137:4, endln:137:11 + \_module_array: (work@oh_dsync), line:121:4, endln:121:11 |vpiParent: - \_module: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 - |vpiName:rd_sync + \_module_inst: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 + |vpiName:wr_sync |vpiFullName:work@oh_dsync |vpiRange: - \_range: , line:137:11, endln:137:17 + \_range: , line:121:11, endln:121:17 |vpiLeftRange: - \_constant: , line:137:12, endln:137:14 + \_constant: , line:121:12, endln:121:14 |vpiParent: - \_range: , line:137:11, endln:137:17 + \_range: , line:121:11, endln:121:17 |vpiDecompile:5 |vpiSize:64 |UINT:5 |vpiConstType:9 |vpiRightRange: - \_constant: , line:137:15, endln:137:16 + \_constant: , line:121:15, endln:121:16 |vpiParent: - \_range: , line:137:11, endln:137:17 + \_range: , line:121:11, endln:121:17 |vpiDecompile:0 |vpiSize:64 |UINT:0 |vpiConstType:9 - |vpiModule: - \_module: work@oh_dsync (work@oh_fifo_async.rd_sync[0]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:135:4, endln:140:35 - |vpiModule: - \_module: work@oh_dsync (work@oh_fifo_async.rd_sync[1]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:135:4, endln:140:35 - |vpiModule: - \_module: work@oh_dsync (work@oh_fifo_async.rd_sync[2]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:135:4, endln:140:35 - |vpiModule: - \_module: work@oh_dsync (work@oh_fifo_async.rd_sync[3]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:135:4, endln:140:35 - |vpiModule: - \_module: work@oh_dsync (work@oh_fifo_async.rd_sync[4]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:135:4, endln:140:35 - |vpiModule: - \_module: work@oh_dsync (work@oh_fifo_async.rd_sync[5]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:135:4, endln:140:35 + |vpiModuleInst: + \_module_inst: work@oh_dsync (work@oh_fifo_async.wr_sync[0]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:119:4, endln:124:35 + |vpiModuleInst: + \_module_inst: work@oh_dsync (work@oh_fifo_async.wr_sync[1]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:119:4, endln:124:35 + |vpiModuleInst: + \_module_inst: work@oh_dsync (work@oh_fifo_async.wr_sync[2]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:119:4, endln:124:35 + |vpiModuleInst: + \_module_inst: work@oh_dsync (work@oh_fifo_async.wr_sync[3]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:119:4, endln:124:35 + |vpiModuleInst: + \_module_inst: work@oh_dsync (work@oh_fifo_async.wr_sync[4]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:119:4, endln:124:35 + |vpiModuleInst: + \_module_inst: work@oh_dsync (work@oh_fifo_async.wr_sync[5]), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:119:4, endln:124:35 |vpiElemTypespec: - \_module_typespec: (oh_dsync), line:135:4, endln:135:12 + \_module_typespec: (oh_dsync), line:119:4, endln:119:12 |vpiName:oh_dsync |vpiContAssign: \_cont_assign: , line:88:11, endln:88:40 |vpiParent: - \_module: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 + \_module_inst: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 |vpiRhs: \_operation: , line:88:24, endln:88:40 |vpiParent: @@ -74091,7 +74091,7 @@ design: (work@oh_fifo_async) |vpiContAssign: \_cont_assign: , line:147:11, endln:147:70 |vpiParent: - \_module: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 + \_module_inst: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 |vpiRhs: \_operation: , line:147:24, endln:147:69 |vpiParent: @@ -74164,7 +74164,7 @@ design: (work@oh_fifo_async) |vpiContAssign: \_cont_assign: , line:150:11, endln:151:46 |vpiParent: - \_module: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 + \_module_inst: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 |vpiRhs: \_operation: , line:150:23, endln:151:46 |vpiParent: diff --git a/third_party/tests/xgate/Xgate.log b/third_party/tests/xgate/Xgate.log index 01a57fd46f..7456d0618a 100644 --- a/third_party/tests/xgate/Xgate.log +++ b/third_party/tests/xgate/Xgate.log @@ -5489,7 +5489,7 @@ io_decl 11 logic_net 144805 logic_typespec 137110 logic_var 1 -module 23128 +module_inst 23128 operation 85464 package 2 param_assign 19436 @@ -5538,7 +5538,7 @@ io_decl 22 logic_net 144805 logic_typespec 137110 logic_var 1 -module 23128 +module_inst 23128 operation 133510 package 2 param_assign 19436